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module io_schedule(
reset,
clk,
ssd_command_fifo_empty_or_not,
ssd_command_fifo_out,
dram_permit,
data_from_dram,
dram_ready,
rd_data_valid,
gc_command_fifo_out,
gc_command_fifo_empty_or_not,
////write_data_fifo0_prog_full,
//command_fifo0_full,
////write_data_fifo1_prog_full,
//command_fifo1_full,
////write_data_fifo2_prog_full,
//command_fifo2_full,
////write_data_fifo3_prog_full,
//command_fifo3_full,
////write_data_fifo4_prog_full,
//command_fifo4_full,
////write_data_fifo5_prog_full,
//command_fifo5_full,
////write_data_fifo6_prog_full,
//command_fifo6_full,
////write_data_fifo7_prog_full,
//command_fifo7_full,
command_available,
ssd_command_fifo_out_en,
controller_command_fifo_in,
controller_command_fifo_in_en,
write_data_fifo_in,
write_data_fifo_in_en,
dram_request,
release_dram,
addr_to_dram,
data_to_dram,
dram_data_mask,
dram_en,
dram_read_or_write,
data_to_dram_en,
data_to_dram_end,
data_to_dram_ready,
gc_command_fifo_out_en,
flash_left_capacity,
free_block_fifo_heads,
free_block_fifo_tails,
register_ready,
state
);
`include"ftl_define.v"
input reset;
input clk;
input ssd_command_fifo_empty_or_not;
input [COMMAND_WIDTH-1:0] ssd_command_fifo_out;
input dram_permit;
input [DRAM_IO_WIDTH-1:0] data_from_dram;
input dram_ready;
input rd_data_valid;
input [GC_COMMAND_WIDTH-1:0] gc_command_fifo_out;
input gc_command_fifo_empty_or_not;
////input write_data_fifo0_prog_full;
//input command_fifo0_full;
////input write_data_fifo1_prog_full;
//input command_fifo1_full;
////input write_data_fifo2_prog_full;
//input command_fifo2_full;
////input write_data_fifo3_prog_full;
//input command_fifo3_full;
////input write_data_fifo4_prog_full;
//input command_fifo4_full;
////input write_data_fifo5_prog_full;
//input command_fifo5_full;
////input write_data_fifo6_prog_full;
//input command_fifo6_full;
////input write_data_fifo7_prog_full;
//input command_fifo7_full;
input [7:0] command_available;
input register_ready;
output ssd_command_fifo_out_en;
output [COMMAND_WIDTH-1:0] controller_command_fifo_in;
output [7:0] controller_command_fifo_in_en;
output [DRAM_IO_WIDTH-1:0] write_data_fifo_in;
output [7:0] write_data_fifo_in_en;
output dram_request;
output release_dram;
output [DRAM_ADDR_WIDTH-1:0] addr_to_dram;
output [DRAM_IO_WIDTH-1:0]data_to_dram;
output [DRAM_MASK_WIDTH-1:0]dram_data_mask;
output dram_en;
output dram_read_or_write;
output data_to_dram_en;
output data_to_dram_end;
input data_to_dram_ready;
output gc_command_fifo_out_en;
inout [18:0]flash_left_capacity;//512GB flash217η
inout [127:0] free_block_fifo_tails;
inout [127:0] free_block_fifo_heads;
output [4:0] state;
//output [5:0] state_addr;
reg ssd_command_fifo_out_en;
reg request_for_addr_management_en;
reg [1:0] request_for_addr_management_op;
reg [27:0] laddr_to_addr_management;
reg [COMMAND_WIDTH-1:0] controller_command_fifo_in;
reg [7:0] controller_command_fifo_in_en;
reg [DRAM_IO_WIDTH-1:0] write_data_fifo_in;
reg [7:0] write_data_fifo_in_en;
reg dram_request;
reg release_dram;
reg gc_command_fifo_out_en;
wire [18:0]flash_left_capacity;//512GB flash217η
wire [127:0] free_block_fifo_tails;
wire [127:0] free_block_fifo_heads;
wire register_ready;
//wire [5:0] state_addr;
//add by qww
wire [DRAM_ADDR_WIDTH-1:0] addr_to_dram;
wire [DRAM_IO_WIDTH-1:0]data_to_dram;
wire [DRAM_MASK_WIDTH-1:0]dram_data_mask;
wire dram_en;
wire dram_read_or_write;
wire [DRAM_ADDR_WIDTH-1:0] addr_to_dram_addr;
wire [DRAM_IO_WIDTH-1:0]data_to_dram_addr;
wire dram_en_addr;
wire dram_read_or_write_addr;
wire [DRAM_MASK_WIDTH-1:0]dram_data_mask_addr;
wire data_to_dram_en_addr;
wire data_to_dram_end_addr;
reg [DRAM_ADDR_WIDTH-1:0] addr_to_dram_io;
reg [DRAM_IO_WIDTH-1:0]data_to_dram_io;
reg dram_en_io;
reg dram_read_or_write_io;
reg [DRAM_MASK_WIDTH-1:0]dram_data_mask_io;
reg data_to_dram_en_io;
reg data_to_dram_end_io;
//add by qww
wire addr_manage_dram_busy;
assign dram_en=(addr_manage_dram_busy)?dram_en_addr:dram_en_io;
assign dram_read_or_write=(addr_manage_dram_busy)?dram_read_or_write_addr:dram_read_or_write_io;
assign addr_to_dram=(addr_manage_dram_busy)?addr_to_dram_addr:addr_to_dram_io;
assign data_to_dram=(addr_manage_dram_busy)?data_to_dram_addr:data_to_dram_io;
assign dram_data_mask=(addr_manage_dram_busy)?dram_data_mask_addr:dram_data_mask_io;
assign data_to_dram_en=(addr_manage_dram_busy)?data_to_dram_en_addr:data_to_dram_en_io;
assign data_to_dram_end=(addr_manage_dram_busy)?data_to_dram_end_addr:data_to_dram_end_io;
//add by qww
wire [PHYSICAL_ADDR_WIDTH-1:0] paddr0_from_addr_management;
wire [PHYSICAL_ADDR_WIDTH-1:0] paddr1_from_addr_management;
wire addr_management_ready;
parameter IDLE =5'b00000;
parameter WAIT_DRAM_FOR_IO =5'b00001;
parameter IO_COMMAND_INTERPRET =5'b00010;
parameter GET_PHYSICAL_ADDRESS_FOR_READ =5'b00011;
parameter WAIT_PADDR_FOR_READ =5'b00100;
parameter GENERATE_READ_COMMAND =5'b00101;
parameter GET_PHYSICAL_ADDRESS_FOR_WRITE =5'b00110;
parameter WAIT_PADDR_FOR_WRITE =5'b00111;
parameter GENERATE_WRITE_COMMAND =5'b01000;
parameter WAIT_DRAM_FOR_GC =5'b01001;
parameter GC_COMMAND_INTERPRET =5'b01010;
parameter MOVE_COMMAND =5'b01011;
parameter WAIT_PADDRS_FOR_MOVE =5'b01100;
parameter GENERATE_MOVE_COMMAND =5'b01101;
parameter ERASE_COMMAND =5'b01110;
parameter WAIT_FOR_ERASE =5'b01111;
parameter CHIP_SELECT =5'b10000;
parameter CHECK_FULL_SIGNAL =5'b10001;
parameter TRANSMIT_WRITE_DATA =5'b10010;
parameter GET_DATA_FROM_DRAM0 =5'b10011;
parameter GET_DATA_FROM_DRAM1 =5'b10100;
parameter GET_DATA_FROM_DRAM2 =5'b10101;
parameter SEND_CONTROLLER_COMMAND =5'b10110;
parameter UNLOCK_DRAM_FOR_A_WHILE =5'b10111;
parameter WAIT_DRAM_FOR_A_WHILE =5'b11000;
parameter CHANCG_TO_STATE_BUF =5'b11001;
parameter UNLOCK_DRAM =5'b11010;
parameter FINISH =5'b11111;
reg [COMMAND_WIDTH-1:0] ssd_command;
reg [PHYSICAL_ADDR_WIDTH-1:0] paddr;//25b
reg [4:0] state;
reg [4:0] state_buf;
reg [PHYSICAL_ADDR_WIDTH-1:0] target_paddr;
reg [COMMAND_WIDTH-1:0] controller_command;
//reg write_data_fifo_prog_full;
reg command_fifo_available;
reg [7:0] enable;
reg [31:0] count;
reg [10:0] count_read;
reg io_or_gc;
reg [DRAM_ADDR_WIDTH-1:0] dram_addr;
reg [GC_COMMAND_WIDTH-1:0] gc_command;
always@ (negedge reset or posedge clk)
begin
if(!reset)
begin
ssd_command_fifo_out_en <=0;
request_for_addr_management_en<=0;
request_for_addr_management_op<=0;
laddr_to_addr_management <=0;
controller_command_fifo_in <=0;
controller_command_fifo_in_en <=0;
write_data_fifo_in <=0;
write_data_fifo_in_en <=0;
dram_request <=0;
release_dram <=0;
gc_command_fifo_out_en <=0;
addr_to_dram_io <=0;
data_to_dram_io <=0;
dram_en_io <=0;
dram_read_or_write_io <=0;
dram_data_mask_io <=0;
ssd_command <=0;
paddr <=0;//25b
state <=0;
state_buf <=0;
target_paddr <=0;
controller_command <=0;
//write_data_fifo_prog_full <=0;
command_fifo_available <=0;
enable <=0;
count <=0;
count_read <=0;
io_or_gc <=0;
dram_addr <=0;
gc_command <=0;
data_to_dram_en_io <=0;
data_to_dram_end_io <=0;
end
else
begin
case (state)
IDLE://00
begin
if(ssd_command_fifo_empty_or_not==0 && (&(command_available)))
begin
ssd_command_fifo_out_en <= 1;
ssd_command <= ssd_command_fifo_out;
io_or_gc <= 1;
dram_request <= 1;
state <= WAIT_DRAM_FOR_IO;
end
else if(gc_command_fifo_empty_or_not==0)
begin
gc_command_fifo_out_en <= 1;
gc_command <= gc_command_fifo_out;
io_or_gc <= 0;
dram_request <= 1;
state <= WAIT_DRAM_FOR_GC;
end
else
state <= IDLE;
end
/////////////////////////////////for IO
WAIT_DRAM_FOR_IO://08
begin
ssd_command_fifo_out_en <= 0;
if(dram_permit==1)
begin
dram_request <= 0;
state <= IO_COMMAND_INTERPRET;
end
else state <= WAIT_DRAM_FOR_IO;
end
IO_COMMAND_INTERPRET://09
begin
case(ssd_command[127:126])
1'b00:
state <= GET_PHYSICAL_ADDRESS_FOR_READ;
1'b01:
state <= GET_PHYSICAL_ADDRESS_FOR_WRITE;
default: state <= IDLE;
endcase
end
////////////////////////////////read from flash memory
GET_PHYSICAL_ADDRESS_FOR_READ://0a
begin
request_for_addr_management_en <= 1;
request_for_addr_management_op <= READ;
laddr_to_addr_management <= ssd_command[27:0];
state <= WAIT_PADDR_FOR_READ;
end
WAIT_PADDR_FOR_READ://0b
begin
request_for_addr_management_en <= 0;
if(addr_management_ready==1)
begin
paddr <= paddr0_from_addr_management;
state <= GENERATE_READ_COMMAND;
end
else state <= WAIT_PADDR_FOR_READ;
end
GENERATE_READ_COMMAND://0c
begin
//2ͣ+370+25ַ+150+17cache_addr+32ַ=128
// controller_command <= {READ, 37'b0, paddr,15'b0,ssd_command[48:32],ssd_command[31:0]};
//controller_command <= {READ, 37'b0, paddr,ssd_command[63:32],ssd_command[31:0]};
controller_command <= {ssd_command[127:89],1'b0,paddr[23:0],ssd_command[63:32],ssd_command[31:0]};
state <= CHIP_SELECT;
end
//////////////////////////////write
GET_PHYSICAL_ADDRESS_FOR_WRITE://0d
begin
request_for_addr_management_en <= 1;
request_for_addr_management_op <= WRITE;
laddr_to_addr_management <= ssd_command[27:0];
state <= WAIT_PADDR_FOR_WRITE;
end
WAIT_PADDR_FOR_WRITE://0e
begin
request_for_addr_management_en <= 0;
if(addr_management_ready==1)
begin
paddr <= paddr1_from_addr_management;
state <= GENERATE_WRITE_COMMAND;
end
else state <= WAIT_PADDR_FOR_WRITE;
end
GENERATE_WRITE_COMMAND://0f
begin
//2ͣ+1Ƿadditional cacheϣ0ʾǣ+360+25ַ+150+17cache_addr+32ַ=128
controller_command <= {WRITE,ssd_command[125], 36'b0,1'b0, paddr[23:0],ssd_command[63:32],ssd_command[31:0]};
state <= CHIP_SELECT;
end
WAIT_DRAM_FOR_GC://01
begin
gc_command_fifo_out_en <= 0;
if(dram_permit==1)
begin
dram_request <= 0;
state <= GC_COMMAND_INTERPRET;
end
else state <= WAIT_DRAM_FOR_GC ;
end
GC_COMMAND_INTERPRET://02
begin
if(gc_command[28]==0)
state <= MOVE_COMMAND;
else
state <= ERASE_COMMAND;
end
MOVE_COMMAND://03
begin
request_for_addr_management_en <= 1;
request_for_addr_management_op <= MOVE;
laddr_to_addr_management <= gc_command[27:0];
state <= WAIT_PADDRS_FOR_MOVE;
end
WAIT_PADDRS_FOR_MOVE://04
begin
request_for_addr_management_en <= 0;
if(addr_management_ready==1)
begin
paddr <= paddr0_from_addr_management;
target_paddr <= paddr1_from_addr_management;
state <= GENERATE_MOVE_COMMAND;
end
else state <= WAIT_PADDRS_FOR_MOVE;
end
GENERATE_MOVE_COMMAND://05
begin
controller_command <= {MOVE, 62'b0,5'b0, target_paddr, 5'b0,paddr};//2+76+25+25=128
state <= CHIP_SELECT;
end
////////erase
ERASE_COMMAND://06
begin
request_for_addr_management_en <= 1;
request_for_addr_management_op <= ERASE;
laddr_to_addr_management <= gc_command[27:0];
state <= WAIT_FOR_ERASE;
end
WAIT_FOR_ERASE://07
begin
request_for_addr_management_en <= 0;
paddr <= gc_command[23:0];
controller_command <= {ERASE,101'b0 , gc_command[24:0]};//2+101+25=128
state <= CHIP_SELECT;
end
CHIP_SELECT://10
begin
case (paddr[26:24])
3'b000:
begin
//write_data_fifo_prog_full <= write_data_fifo0_prog_full;
command_fifo_available <= command_available[0];
enable <= 8'b00000001;
end
3'b001:
begin
//write_data_fifo_prog_full <= write_data_fifo1_prog_full;
command_fifo_available <= command_available[1];
enable <= 8'b00000010;
end
3'b010:
begin
//write_data_fifo_prog_full <= write_data_fifo2_prog_full;
command_fifo_available <= command_available[2];
enable <= 8'b00000100;
end
3'b011:
begin
//write_data_fifo_prog_full <= write_data_fifo3_prog_full;
command_fifo_available <= command_available[3];
enable <= 8'b00001000;
end
3'b100:
begin
//write_data_fifo_prog_full <= write_data_fifo4_prog_full;
command_fifo_available <= command_available[4];
enable <= 8'b00010000;
end
3'b101:
begin
//write_data_fifo_prog_full <= write_data_fifo5_prog_full;
command_fifo_available <= command_available[5];
enable <= 8'b00100000;
end
3'b110:
begin
//write_data_fifo_prog_full <= write_data_fifo6_prog_full;
command_fifo_available <= command_available[6];
enable <= 8'b01000000;
end
3'b111:
begin
//write_data_fifo_prog_full <= write_data_fifo7_prog_full;
command_fifo_available <= command_available[7];
enable <= 8'b10000000;
end
endcase
state <= CHECK_FULL_SIGNAL;
end
CHECK_FULL_SIGNAL://11
begin
if(io_or_gc==1 && controller_command[127:126] !=WRITE && command_fifo_available)
state <= SEND_CONTROLLER_COMMAND;
else if(io_or_gc==1 && controller_command[127:126]==WRITE && command_fifo_available)//WRITE 01 && !write_data_fifo_prog_full
begin
if(ssd_command[125])
// dram_addr <= CACHE_BASE + {ssd_command[48:32],11'b000_00000000};
dram_addr <= CACHE_BASE + {ssd_command[50:32],9'b0_00000000};
else //in additional cache
dram_addr <= ADDITIONAL_CACHE_FIFO_BASE + {ssd_command[50:32],9'b0_00000000};
//state <= TRANSMIT_WRITE_DATA;
state <= SEND_CONTROLLER_COMMAND;
end
else
begin
state <= UNLOCK_DRAM_FOR_A_WHILE;
state_buf <= CHIP_SELECT;
end
end
TRANSMIT_WRITE_DATA://12
begin
controller_command_fifo_in_en <= 0;
state <= GET_DATA_FROM_DRAM0;
dram_en_io <= 1;
dram_read_or_write_io <= 1; //read
addr_to_dram_io <= dram_addr;
count<=0;
count_read<=0;
end
GET_DATA_FROM_DRAM0://13
begin
write_data_fifo_in_en<=0;//
if(rd_data_valid)
begin
write_data_fifo_in_en <= enable;
write_data_fifo_in <= data_from_dram;
count_read<=count_read+1;
end
if(dram_ready)
begin
dram_en_io <= 0;
dram_addr <= dram_addr+8;
count <= count+1;
state<=GET_DATA_FROM_DRAM1;
end
end
GET_DATA_FROM_DRAM1: //14
begin
write_data_fifo_in_en<=0;
if(rd_data_valid)
begin
write_data_fifo_in_en <= enable;
write_data_fifo_in <= data_from_dram;
count_read<=count_read+1;
end
if(count>=DRAM_COUNT)//256
begin
state <= GET_DATA_FROM_DRAM2;
end
else
begin
state <= GET_DATA_FROM_DRAM0;
dram_en_io <= 1;
dram_read_or_write_io <= 1; //read
addr_to_dram_io <= dram_addr;
end
end
GET_DATA_FROM_DRAM2: //15
begin
write_data_fifo_in_en<=0;
if(rd_data_valid)
begin
write_data_fifo_in_en <= enable;
write_data_fifo_in <= data_from_dram;
count_read<=count_read+1;
end
else begin end
if(count_read>=DRAM_COUNT*2)//512256b
begin
//state <= SEND_CONTROLLER_COMMAND;
state <= UNLOCK_DRAM;
count<=0;
count_read<=0;
end
end
SEND_CONTROLLER_COMMAND://16
begin
controller_command_fifo_in <= controller_command;
controller_command_fifo_in_en <= enable;
if(controller_command[127:126]==WRITE)
state <= TRANSMIT_WRITE_DATA;
else
state <= UNLOCK_DRAM;
end
////////////////////////////////////////////////////above io
////////////////////////////////////////////////////
UNLOCK_DRAM_FOR_A_WHILE://17
begin
release_dram <= 1;
count <= 0;
controller_command_fifo_in_en <= 0;
state <= WAIT_DRAM_FOR_A_WHILE;
end
WAIT_DRAM_FOR_A_WHILE://18
begin
release_dram <= 0;
if(count>=63)
begin
dram_request <= 1;
count<=0;
state <= CHANCG_TO_STATE_BUF;
end
else
begin
count <= count+1;
state<=WAIT_DRAM_FOR_A_WHILE;
end
end
CHANCG_TO_STATE_BUF://19
begin
if(dram_permit)
begin
dram_request <= 0;
state <= state_buf;
end
else
state<=CHANCG_TO_STATE_BUF;
end
////////////////////////////////////////////////////
UNLOCK_DRAM://17
begin
release_dram <= 1;
controller_command_fifo_in_en <= 0;
state <= FINISH;
end
FINISH://18
begin
release_dram <= 0;
state <= IDLE;
end
default: state <= IDLE;
endcase
end
end
address_management addr_management_instance(
.reset(reset),
.clk(clk),
.request_coming(request_for_addr_management_en),
.request_op(request_for_addr_management_op),
.addr_to_addr_management(laddr_to_addr_management),
.data_from_dram(data_from_dram),
.dram_ready(dram_ready),
.rd_data_valid(rd_data_valid),
.paddr0_from_addr_management(paddr0_from_addr_management),
.paddr1_from_addr_management(paddr1_from_addr_management),
.addr_management_ready(addr_management_ready),
.dram_en_o(dram_en_addr),
.dram_read_or_write(dram_read_or_write_addr),
.addr_to_dram_o(addr_to_dram_addr),
.data_to_dram(data_to_dram_addr),
.dram_data_mask(dram_data_mask_addr),
.data_to_dram_en(data_to_dram_en_addr),
.data_to_dram_end(data_to_dram_end_addr),
.data_to_dram_ready(data_to_dram_ready),
.addr_manage_dram_busy(addr_manage_dram_busy),
.flash_left_capacity_io(flash_left_capacity),
.free_block_fifo_heads_io(free_block_fifo_heads),
.free_block_fifo_tails_io(free_block_fifo_tails),
.register_ready(register_ready)
);
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:28:50 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
OP_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n511,
n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, n522,
n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533,
n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544,
n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566,
n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577,
n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588,
n589, n590, n591, n592, n593, n594, n595, n596, n597, n598, n599,
n600, n601, n602, n603, n604, n605, n606, n607, n608, n609, n610,
n611, n612, n613, n614, n615, n616, n617, n618, n619, n620, n621,
n622, n623, n624, n625, n626, n627, n628, n629, n630, n631, n632,
n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643,
n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654,
n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676,
n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698,
n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720,
n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731,
n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742,
n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753,
n754, n755, n756, n757, n758, n759, n760, n761, n762, n763, n764,
n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, n775,
n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786,
n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, n797,
n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808,
n809, n810, n811, n812, n813, n814, n815, n817, n818, n819, n820,
n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831,
n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842,
n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, n853,
n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864,
n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, n875,
n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886,
n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897,
n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908,
n909, n910, n912, n913, n914, n915, n916, n917, n918, n919,
DP_OP_15J36_125_2314_n8, DP_OP_15J36_125_2314_n7,
DP_OP_15J36_125_2314_n6, DP_OP_15J36_125_2314_n5,
DP_OP_15J36_125_2314_n4, intadd_41_B_12_, intadd_41_B_11_,
intadd_41_B_10_, intadd_41_B_9_, intadd_41_B_8_, intadd_41_B_7_,
intadd_41_B_6_, intadd_41_B_5_, intadd_41_B_4_, intadd_41_B_3_,
intadd_41_B_2_, intadd_41_B_1_, intadd_41_B_0_, intadd_41_CI,
intadd_41_SUM_12_, intadd_41_SUM_11_, intadd_41_SUM_10_,
intadd_41_SUM_9_, intadd_41_SUM_8_, intadd_41_SUM_7_,
intadd_41_SUM_6_, intadd_41_SUM_5_, intadd_41_SUM_4_,
intadd_41_SUM_3_, intadd_41_SUM_2_, intadd_41_SUM_1_,
intadd_41_SUM_0_, intadd_41_n13, intadd_41_n12, intadd_41_n11,
intadd_41_n10, intadd_41_n9, intadd_41_n8, intadd_41_n7, intadd_41_n6,
intadd_41_n5, intadd_41_n4, intadd_41_n3, intadd_41_n2, intadd_41_n1,
intadd_42_A_1_, intadd_42_B_2_, intadd_42_B_1_, intadd_42_B_0_,
intadd_42_CI, intadd_42_SUM_2_, intadd_42_SUM_1_, intadd_42_SUM_0_,
intadd_42_n3, intadd_42_n2, intadd_42_n1, intadd_43_B_2_,
intadd_43_B_1_, intadd_43_B_0_, intadd_43_CI, intadd_43_SUM_2_,
intadd_43_SUM_1_, intadd_43_SUM_0_, intadd_43_n3, intadd_43_n2,
intadd_43_n1, n920, n921, n922, n923, n924, n925, n926, n927, n928,
n929, n930, n931, n932, n933, n934, n935, n936, n937, n938, n939,
n940, n941, n942, n943, n944, n945, n946, n947, n948, n949, n950,
n951, n952, n953, n954, n955, n956, n957, n958, n959, n960, n961,
n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972,
n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983,
n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994,
n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004,
n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014,
n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024,
n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034,
n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044,
n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074,
n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084,
n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094,
n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144,
n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154,
n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164,
n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174,
n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274,
n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284,
n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294,
n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1315,
n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325,
n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335,
n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345,
n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355,
n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1366,
n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376,
n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386,
n1387, n1388, n1389, n1390, n1391, n1392, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417,
n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427,
n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437,
n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448,
n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458,
n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468,
n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478,
n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488,
n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498,
n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508,
n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518,
n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528,
n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538,
n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548,
n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558,
n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568,
n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578,
n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588,
n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598,
n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608,
n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618,
n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628,
n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638,
n1639, n1640, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1650,
n1651, n1652;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:1] Raw_mant_NRM_SWR;
wire [24:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n914), .CK(clk), .RN(n1625), .QN(
n938) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n908), .CK(clk), .RN(n1626),
.QN(n930) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n900), .CK(clk), .RN(n1631),
.QN(n931) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n878), .CK(clk), .RN(n1631), .Q(
intAS) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n877), .CK(clk), .RN(n1625), .Q(
left_right_SHT2) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1626),
.Q(ready) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n830), .CK(clk), .RN(n1629), .QN(
n934) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n822), .CK(clk), .RN(n923), .Q(
Data_array_SWR[3]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n821), .CK(clk), .RN(n1643), .Q(
Data_array_SWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n813), .CK(clk), .RN(n1627),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n812), .CK(clk), .RN(n923), .Q(
Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n811), .CK(clk), .RN(n1633),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n810), .CK(clk), .RN(n1630),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n809), .CK(clk), .RN(n924), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n808), .CK(clk), .RN(n1644), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n807), .CK(clk), .RN(n1644), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n806), .CK(clk), .RN(n1644), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n805), .CK(clk), .RN(n1644), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n804), .CK(clk), .RN(n1644), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n803), .CK(clk), .RN(n1644), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n802), .CK(clk), .RN(n1644), .Q(
final_result_ieee[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n801), .CK(clk), .RN(n1627), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n800), .CK(clk), .RN(n1627), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n799), .CK(clk), .RN(n1629), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n798), .CK(clk), .RN(n923), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n797), .CK(clk), .RN(n1635), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n796), .CK(clk), .RN(n1630), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n795), .CK(clk), .RN(n1627), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n794), .CK(clk), .RN(n979), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n793), .CK(clk), .RN(n1629), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n792), .CK(clk), .RN(n1628), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n791), .CK(clk), .RN(n1631), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n790), .CK(clk), .RN(n1625), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n789), .CK(clk), .RN(n1626), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n788), .CK(clk), .RN(n1624), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n787), .CK(clk), .RN(n1632), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n786), .CK(clk), .RN(n1628), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n785), .CK(clk), .RN(n1626), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n784), .CK(clk), .RN(n1631), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n783), .CK(clk), .RN(n1624), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n782), .CK(clk), .RN(n1625), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n781), .CK(clk), .RN(n1643), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n780), .CK(clk), .RN(n1632), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n779), .CK(clk), .RN(n1632), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n774), .CK(clk), .RN(n1632), .QN(n939)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n773), .CK(clk), .RN(n1632), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n772), .CK(clk), .RN(n1632), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n771), .CK(clk), .RN(n1632), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n770), .CK(clk), .RN(n1632), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n769), .CK(clk), .RN(n1632), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n768), .CK(clk), .RN(n1633), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n767), .CK(clk), .RN(n1633), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1633), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n764), .CK(clk), .RN(n1633), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n763), .CK(clk), .RN(n1633), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n761), .CK(clk), .RN(n1633), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n760), .CK(clk), .RN(n1633), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n759), .CK(clk), .RN(n1633), .Q(
DMP_SFG[2]), .QN(n1608) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n758), .CK(clk), .RN(n1633), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n757), .CK(clk), .RN(n1633), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n756), .CK(clk), .RN(n1636), .Q(
DMP_SFG[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n755), .CK(clk), .RN(n1634), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n754), .CK(clk), .RN(n925), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n752), .CK(clk), .RN(n1634), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n751), .CK(clk), .RN(n1636), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n749), .CK(clk), .RN(n925), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n748), .CK(clk), .RN(n925), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n1631), .QN(n929)
);
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n924), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n745), .CK(clk), .RN(n1634), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n743), .CK(clk), .RN(n924), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n742), .CK(clk), .RN(n924), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n740), .CK(clk), .RN(n1636), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n739), .CK(clk), .RN(n1636), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n737), .CK(clk), .RN(n925), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n736), .CK(clk), .RN(n1634), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n735), .CK(clk), .RN(n926), .Q(
DMP_SFG[10]), .QN(n1560) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n734), .CK(clk), .RN(n924), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n733), .CK(clk), .RN(n924), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n732), .CK(clk), .RN(n1635), .Q(
DMP_SFG[11]), .QN(n1559) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n731), .CK(clk), .RN(n1628), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n730), .CK(clk), .RN(n1635), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n729), .CK(clk), .RN(n1628), .Q(
DMP_SFG[12]), .QN(n1567) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n728), .CK(clk), .RN(n1635), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n727), .CK(clk), .RN(n1628), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n726), .CK(clk), .RN(n1635), .Q(
DMP_SFG[13]), .QN(n1566) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n725), .CK(clk), .RN(n1628), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n724), .CK(clk), .RN(n1635), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n723), .CK(clk), .RN(n1628), .Q(
DMP_SFG[14]), .QN(n1572) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n722), .CK(clk), .RN(n1635), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n721), .CK(clk), .RN(n1628), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n720), .CK(clk), .RN(n1635), .Q(
DMP_SFG[15]), .QN(n1590) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n719), .CK(clk), .RN(n1628), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n718), .CK(clk), .RN(n1635), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n717), .CK(clk), .RN(n1628), .Q(
DMP_SFG[16]), .QN(n1589) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n716), .CK(clk), .RN(n1635), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n715), .CK(clk), .RN(n1628), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n714), .CK(clk), .RN(n1635), .Q(
DMP_SFG[17]), .QN(n1602) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n713), .CK(clk), .RN(n1628), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n712), .CK(clk), .RN(n1635), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n711), .CK(clk), .RN(n1628), .Q(
DMP_SFG[18]), .QN(n1601) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n710), .CK(clk), .RN(n1635), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n709), .CK(clk), .RN(n1628), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n708), .CK(clk), .RN(n1634), .Q(
DMP_SFG[19]), .QN(n1610) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n707), .CK(clk), .RN(n1636), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n706), .CK(clk), .RN(n1639), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n705), .CK(clk), .RN(n925), .Q(
DMP_SFG[20]), .QN(n1609) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n704), .CK(clk), .RN(n1634), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n703), .CK(clk), .RN(n924), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n702), .CK(clk), .RN(n924), .Q(
DMP_SFG[21]), .QN(n1622) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n701), .CK(clk), .RN(n924), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n700), .CK(clk), .RN(n1636), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n699), .CK(clk), .RN(n1639), .Q(
DMP_SFG[22]), .QN(n1621) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n698), .CK(clk), .RN(n925), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n697), .CK(clk), .RN(n1634), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n696), .CK(clk), .RN(n1636), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n695), .CK(clk), .RN(n925), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n693), .CK(clk), .RN(n924), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n692), .CK(clk), .RN(n924), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n691), .CK(clk), .RN(n926), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n690), .CK(clk), .RN(n925), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n688), .CK(clk), .RN(n1634), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n687), .CK(clk), .RN(n1636), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n686), .CK(clk), .RN(n1639), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n685), .CK(clk), .RN(n925), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n683), .CK(clk), .RN(n1634), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n682), .CK(clk), .RN(n1639), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n681), .CK(clk), .RN(n1625), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n680), .CK(clk), .RN(n925), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n678), .CK(clk), .RN(n925), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n677), .CK(clk), .RN(n923), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n676), .CK(clk), .RN(n1637), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n675), .CK(clk), .RN(n1640), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n673), .CK(clk), .RN(n1624), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n672), .CK(clk), .RN(n1638), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n671), .CK(clk), .RN(n925), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n670), .CK(clk), .RN(n923), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n668), .CK(clk), .RN(n1637), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n667), .CK(clk), .RN(n1640), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n666), .CK(clk), .RN(n1638), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n665), .CK(clk), .RN(n1638), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n663), .CK(clk), .RN(n1638), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n662), .CK(clk), .RN(n1638), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n661), .CK(clk), .RN(n1638), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n660), .CK(clk), .RN(n1638), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n658), .CK(clk), .RN(n1638), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n656), .CK(clk), .RN(n1638), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n654), .CK(clk), .RN(n1638), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n652), .CK(clk), .RN(n1645), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n650), .CK(clk), .RN(n926), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n649), .CK(clk), .RN(n978), .QN(
n943) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n648), .CK(clk), .RN(n926), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n647), .CK(clk), .RN(n1642), .QN(
n940) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n646), .CK(clk), .RN(n1639), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n644), .CK(clk), .RN(n1642), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n642), .CK(clk), .RN(n1639), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n640), .CK(clk), .RN(n1639), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n639), .CK(clk), .RN(n1642), .QN(
n935) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n638), .CK(clk), .RN(n926), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n636), .CK(clk), .RN(n1645), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n635), .CK(clk), .RN(n978), .QN(
n941) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n634), .CK(clk), .RN(n926), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n632), .CK(clk), .RN(n1639), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n631), .CK(clk), .RN(n1642),
.QN(n942) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n630), .CK(clk), .RN(n926), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n628), .CK(clk), .RN(n1632), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n627), .CK(clk), .RN(n1638),
.QN(n936) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n626), .CK(clk), .RN(n1644), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n624), .CK(clk), .RN(n923), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n622), .CK(clk), .RN(n1637), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n620), .CK(clk), .RN(n1640), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n619), .CK(clk), .RN(n1643),
.QN(n937) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n618), .CK(clk), .RN(n925), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n616), .CK(clk), .RN(n1625), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n614), .CK(clk), .RN(n923), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1631), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1644), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n605), .CK(clk), .RN(n1624), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n604), .CK(clk), .RN(n925), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n603), .CK(clk), .RN(n1642), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n602), .CK(clk), .RN(n926), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n601), .CK(clk), .RN(n1645), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n600), .CK(clk), .RN(n978), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n599), .CK(clk), .RN(n926), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n598), .CK(clk), .RN(n1639), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n596), .CK(clk), .RN(n1642), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n595), .CK(clk), .RN(n1645), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n594), .CK(clk), .RN(n926), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n593), .CK(clk), .RN(n978), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n592), .CK(clk), .RN(n926), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n591), .CK(clk), .RN(n1644), .Q(
final_result_ieee[31]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n574), .CK(clk), .RN(n926), .Q(
LZD_output_NRM2_EW[4]), .QN(n1573) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n571), .CK(clk), .RN(n925), .Q(
LZD_output_NRM2_EW[2]), .QN(n1569) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n566), .CK(clk), .RN(n1636), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n564), .CK(clk), .RN(n1640), .QN(
n933) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n560), .CK(clk), .RN(n1634), .Q(
LZD_output_NRM2_EW[3]), .QN(n1568) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n559), .CK(clk), .RN(n1636), .Q(
LZD_output_NRM2_EW[1]), .QN(n1561) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n552), .CK(clk), .RN(n1640), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n551), .CK(clk), .RN(n1626), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n549), .CK(clk), .RN(n1642), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n548), .CK(clk), .RN(n926), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n547), .CK(clk), .RN(n1645), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n546), .CK(clk), .RN(n978), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n544), .CK(clk), .RN(n926), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n543), .CK(clk), .RN(n1639), .Q(
final_result_ieee[14]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n542), .CK(clk), .RN(n1642), .Q(
DmP_mant_SFG_SWR[5]), .QN(n968) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n541), .CK(clk), .RN(n978), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n540), .CK(clk), .RN(n926), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n539), .CK(clk), .RN(n1645), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n538), .CK(clk), .RN(n926), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n536), .CK(clk), .RN(n1645), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n535), .CK(clk), .RN(n978), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n533), .CK(clk), .RN(n926), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n532), .CK(clk), .RN(n1639), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n531), .CK(clk), .RN(n1642), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n530), .CK(clk), .RN(n926), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n529), .CK(clk), .RN(n1645), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n528), .CK(clk), .RN(n978), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n527), .CK(clk), .RN(n926), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n526), .CK(clk), .RN(n1639), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n525), .CK(clk), .RN(n1643), .Q(
final_result_ieee[22]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n519), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[17]), .QN(n969) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n516), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[20]), .QN(n971) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n515), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[21]), .QN(n972) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n512), .CK(clk), .RN(n1644), .Q(
DmP_mant_SFG_SWR[24]), .QN(n974) );
CMPR32X2TS intadd_41_U14 ( .A(n1560), .B(intadd_41_B_0_), .C(intadd_41_CI),
.CO(intadd_41_n13), .S(intadd_41_SUM_0_) );
CMPR32X2TS intadd_41_U13 ( .A(n1559), .B(intadd_41_B_1_), .C(intadd_41_n13),
.CO(intadd_41_n12), .S(intadd_41_SUM_1_) );
CMPR32X2TS intadd_41_U12 ( .A(n1567), .B(intadd_41_B_2_), .C(intadd_41_n12),
.CO(intadd_41_n11), .S(intadd_41_SUM_2_) );
CMPR32X2TS intadd_41_U11 ( .A(n1566), .B(intadd_41_B_3_), .C(intadd_41_n11),
.CO(intadd_41_n10), .S(intadd_41_SUM_3_) );
CMPR32X2TS intadd_41_U10 ( .A(n1572), .B(intadd_41_B_4_), .C(intadd_41_n10),
.CO(intadd_41_n9), .S(intadd_41_SUM_4_) );
CMPR32X2TS intadd_41_U9 ( .A(n1590), .B(intadd_41_B_5_), .C(intadd_41_n9),
.CO(intadd_41_n8), .S(intadd_41_SUM_5_) );
CMPR32X2TS intadd_41_U8 ( .A(n1589), .B(intadd_41_B_6_), .C(intadd_41_n8),
.CO(intadd_41_n7), .S(intadd_41_SUM_6_) );
CMPR32X2TS intadd_41_U7 ( .A(n1602), .B(intadd_41_B_7_), .C(intadd_41_n7),
.CO(intadd_41_n6), .S(intadd_41_SUM_7_) );
CMPR32X2TS intadd_41_U6 ( .A(n1601), .B(intadd_41_B_8_), .C(intadd_41_n6),
.CO(intadd_41_n5), .S(intadd_41_SUM_8_) );
CMPR32X2TS intadd_41_U5 ( .A(n1610), .B(intadd_41_B_9_), .C(intadd_41_n5),
.CO(intadd_41_n4), .S(intadd_41_SUM_9_) );
CMPR32X2TS intadd_41_U4 ( .A(n1609), .B(intadd_41_B_10_), .C(intadd_41_n4),
.CO(intadd_41_n3), .S(intadd_41_SUM_10_) );
CMPR32X2TS intadd_41_U3 ( .A(n1622), .B(intadd_41_B_11_), .C(intadd_41_n3),
.CO(intadd_41_n2), .S(intadd_41_SUM_11_) );
CMPR32X2TS intadd_41_U2 ( .A(n1621), .B(intadd_41_B_12_), .C(intadd_41_n2),
.CO(intadd_41_n1), .S(intadd_41_SUM_12_) );
CMPR32X2TS intadd_42_U4 ( .A(n1608), .B(intadd_42_B_0_), .C(intadd_42_CI),
.CO(intadd_42_n3), .S(intadd_42_SUM_0_) );
CMPR32X2TS intadd_42_U3 ( .A(intadd_42_A_1_), .B(n961), .C(intadd_42_n3),
.CO(intadd_42_n2), .S(intadd_42_SUM_1_) );
CMPR32X2TS intadd_42_U2 ( .A(n1607), .B(intadd_42_B_2_), .C(intadd_42_n2),
.CO(intadd_42_n1), .S(intadd_42_SUM_2_) );
CMPR32X2TS intadd_43_U4 ( .A(n955), .B(intadd_43_B_0_), .C(intadd_43_CI),
.CO(intadd_43_n3), .S(intadd_43_SUM_0_) );
CMPR32X2TS intadd_43_U3 ( .A(DMP_SFG[7]), .B(intadd_43_B_1_), .C(
intadd_43_n3), .CO(intadd_43_n2), .S(intadd_43_SUM_1_) );
CMPR32X2TS intadd_43_U2 ( .A(DMP_SFG[8]), .B(intadd_43_B_2_), .C(
intadd_43_n2), .CO(intadd_43_n1), .S(intadd_43_SUM_2_) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n839), .CK(clk), .RN(n979), .Q(
Data_array_SWR[19]), .QN(n1619) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n610), .CK(clk), .RN(n1631), .Q(
DmP_EXP_EWSW[25]), .QN(n1618) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n775), .CK(clk), .RN(n1632), .Q(
DMP_EXP_EWSW[26]), .QN(n1617) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n828), .CK(clk), .RN(n1627), .Q(
Data_array_SWR[9]), .QN(n1616) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n609), .CK(clk), .RN(n1634), .Q(
DmP_EXP_EWSW[26]), .QN(n1613) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n826), .CK(clk), .RN(n923), .Q(
Data_array_SWR[7]), .QN(n1612) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n825), .CK(clk), .RN(n1627), .Q(
Data_array_SWR[6]), .QN(n1611) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n753), .CK(clk), .RN(n1639), .Q(
DMP_SFG[4]), .QN(n1607) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n829), .CK(clk), .RN(n1629), .Q(
Data_array_SWR[10]), .QN(n1606) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n776), .CK(clk), .RN(n1632), .Q(
DMP_EXP_EWSW[25]), .QN(n1605) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n842), .CK(clk), .RN(n1630), .Q(
Data_array_SWR[22]), .QN(n1604) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n841), .CK(clk), .RN(n1631), .Q(
Data_array_SWR[21]), .QN(n1603) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n876), .CK(clk), .RN(n1624), .Q(
intDY_EWSW[0]), .QN(n1593) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n664), .CK(clk), .RN(n1639), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1588) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n840), .CK(clk), .RN(n1627), .Q(
Data_array_SWR[20]), .QN(n1587) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n881), .CK(clk), .RN(n1625),
.Q(intDX_EWSW[29]), .QN(n1585) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n869), .CK(clk), .RN(n923), .Q(
intDY_EWSW[7]), .QN(n1584) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n849), .CK(clk), .RN(n1625),
.Q(intDY_EWSW[27]), .QN(n1583) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n872), .CK(clk), .RN(n1629), .Q(
intDY_EWSW[4]), .QN(n1579) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n874), .CK(clk), .RN(n1628), .Q(
intDY_EWSW[2]), .QN(n1578) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n867), .CK(clk), .RN(n1630), .Q(
intDY_EWSW[9]), .QN(n1575) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n870), .CK(clk), .RN(n1627), .Q(
intDY_EWSW[6]), .QN(n1574) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n669), .CK(clk), .RN(n1636), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1571) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n918), .CK(clk), .RN(
n1629), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1570) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n846), .CK(clk), .RN(n1624),
.Q(intDY_EWSW[30]), .QN(n1565) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n817), .CK(clk), .RN(n1644), .Q(
shift_value_SHT2_EWR[3]), .QN(n1564) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n694), .CK(clk), .RN(n1634), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1558) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n818), .CK(clk), .RN(n1628), .Q(
shift_value_SHT2_EWR[2]), .QN(n1557) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n567), .CK(clk), .RN(n1640), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1553) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n562), .CK(clk), .RN(n1637), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1552) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n741), .CK(clk), .RN(n924), .Q(
DMP_SFG[8]), .QN(n1551) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n577), .CK(clk), .RN(n923), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1549) );
DFFRX1TS inst_ShiftRegister_Q_reg_4_ ( .D(n915), .CK(clk), .RN(n1628), .QN(
n1623) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n833), .CK(clk), .RN(n979), .Q(
Data_array_SWR[13]), .QN(n1546) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n777), .CK(clk), .RN(n1632), .Q(
DMP_EXP_EWSW[24]), .QN(n1545) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n611), .CK(clk), .RN(n1640), .Q(
DmP_EXP_EWSW[24]), .QN(n1544) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n857), .CK(clk), .RN(n1633),
.Q(intDY_EWSW[19]), .QN(n1543) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n880), .CK(clk), .RN(n1626),
.Q(intDX_EWSW[30]), .QN(n1542) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n860), .CK(clk), .RN(n923), .Q(
intDY_EWSW[16]), .QN(n1540) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n871), .CK(clk), .RN(n1628), .Q(
intDY_EWSW[5]), .QN(n1539) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n847), .CK(clk), .RN(n1626),
.Q(intDY_EWSW[29]), .QN(n1535) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n557), .CK(clk), .RN(n923), .Q(
Raw_mant_NRM_SWR[4]), .QN(n1532) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n554), .CK(clk), .RN(n925), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1531) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n578), .CK(clk), .RN(n1637), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1530) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n852), .CK(clk), .RN(n1629),
.Q(intDY_EWSW[24]), .QN(n1527) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n585), .CK(clk), .RN(n924), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1526) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n581), .CK(clk), .RN(n925), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1525) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n590), .CK(clk), .RN(n924), .Q(
Raw_mant_NRM_SWR[12]), .QN(n1524) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n580), .CK(clk), .RN(n1636), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1522) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n579), .CK(clk), .RN(n924), .Q(
Raw_mant_NRM_SWR[23]), .QN(n1521) );
DFFSX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n965), .CK(clk), .SN(n1626), .Q(
n1646), .QN(Shift_reg_FLAGS_7[0]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1631), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1538) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n561), .CK(clk), .RN(n1634), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1597) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n916), .CK(clk), .RN(n1628), .Q(
n1529), .QN(n1620) );
DFFRX2TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n597), .CK(clk), .RN(n1639), .Q(
OP_FLAG_SFG), .QN(n1647) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n555), .CK(clk), .RN(n923), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1555) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n568), .CK(clk), .RN(n1640), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1563) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n588), .CK(clk), .RN(n925), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1523) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n575), .CK(clk), .RN(n1632), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1550) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n586), .CK(clk), .RN(n1634), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1528) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n815), .CK(clk), .RN(n1625), .Q(
shift_value_SHT2_EWR[4]), .QN(n1536) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n894), .CK(clk), .RN(n1631),
.Q(intDX_EWSW[16]), .QN(n1562) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n903), .CK(clk), .RN(n1626), .Q(
intDX_EWSW[7]), .QN(n1534) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n904), .CK(clk), .RN(n1631), .Q(
intDX_EWSW[6]), .QN(n1556) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n905), .CK(clk), .RN(n1624), .Q(
intDX_EWSW[5]), .QN(n1554) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n906), .CK(clk), .RN(n1625), .Q(
intDX_EWSW[4]), .QN(n1533) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n859), .CK(clk), .RN(n923), .Q(
intDY_EWSW[17]), .QN(n1594) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n858), .CK(clk), .RN(n1629),
.Q(intDY_EWSW[18]), .QN(n1599) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n854), .CK(clk), .RN(n1628),
.Q(intDY_EWSW[22]), .QN(n1541) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n862), .CK(clk), .RN(n1627),
.Q(intDY_EWSW[14]), .QN(n1581) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n863), .CK(clk), .RN(n1630),
.Q(intDY_EWSW[13]), .QN(n1576) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n850), .CK(clk), .RN(n1627),
.Q(intDY_EWSW[26]), .QN(n1591) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n851), .CK(clk), .RN(n1627),
.Q(intDY_EWSW[25]), .QN(n1592) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n853), .CK(clk), .RN(n979), .Q(
intDY_EWSW[23]), .QN(n1586) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n864), .CK(clk), .RN(n923), .Q(
intDY_EWSW[12]), .QN(n1580) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n868), .CK(clk), .RN(n1629), .Q(
intDY_EWSW[8]), .QN(n1596) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n875), .CK(clk), .RN(n1624), .Q(
intDY_EWSW[1]), .QN(n1595) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n882), .CK(clk), .RN(n1628),
.Q(intDX_EWSW[28]), .QN(n1598) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n884), .CK(clk), .RN(n1638),
.Q(intDX_EWSW[26]), .QN(n1548) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n885), .CK(clk), .RN(n1631),
.Q(intDX_EWSW[25]), .QN(n1547) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n886), .CK(clk), .RN(n1625),
.Q(intDX_EWSW[24]), .QN(n1615) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n844), .CK(clk), .RN(n1624), .Q(
Data_array_SWR[24]), .QN(n1537) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n831), .CK(clk), .RN(n1633), .Q(
Data_array_SWR[11]), .QN(n1614) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n887), .CK(clk), .RN(n1626),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n897), .CK(clk), .RN(n1628),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n907), .CK(clk), .RN(n1631), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n895), .CK(clk), .RN(n1624),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n889), .CK(clk), .RN(n1628),
.Q(intDX_EWSW[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n843), .CK(clk), .RN(n1626), .Q(
Data_array_SWR[23]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n582), .CK(clk), .RN(n1634), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n893), .CK(clk), .RN(n1644),
.Q(intDX_EWSW[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n902), .CK(clk), .RN(n1624), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n899), .CK(clk), .RN(n1625),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n901), .CK(clk), .RN(n1626), .Q(
intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n883), .CK(clk), .RN(n1631),
.Q(intDX_EWSW[27]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n832), .CK(clk), .RN(n1627), .Q(
Data_array_SWR[12]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n583), .CK(clk), .RN(n1626), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n910), .CK(clk), .RN(n1624), .Q(
intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n892), .CK(clk), .RN(n1631),
.Q(intDX_EWSW[18]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n587), .CK(clk), .RN(n924), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n569), .CK(clk), .RN(n925), .Q(
Raw_mant_NRM_SWR[8]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n589), .CK(clk), .RN(n978), .Q(
Raw_mant_NRM_SWR[13]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n834), .CK(clk), .RN(n1629), .Q(
Data_array_SWR[14]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n572), .CK(clk), .RN(n925), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n556), .CK(clk), .RN(n1637), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n919), .CK(clk), .RN(
n1625), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n838), .CK(clk), .RN(n923), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n827), .CK(clk), .RN(n1630), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n837), .CK(clk), .RN(n1635), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n835), .CK(clk), .RN(n1627), .Q(
Data_array_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n584), .CK(clk), .RN(n925), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n738), .CK(clk), .RN(n978), .Q(
DMP_SFG[9]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n823), .CK(clk), .RN(n1635), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n824), .CK(clk), .RN(n1630), .Q(
Data_array_SWR[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n762), .CK(clk), .RN(n1633), .Q(
DMP_SFG[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n744), .CK(clk), .RN(n1636), .Q(
DMP_SFG[7]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n879), .CK(clk), .RN(n1638),
.Q(intDX_EWSW[31]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n613), .CK(clk), .RN(n923), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n625), .CK(clk), .RN(n1636), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n623), .CK(clk), .RN(n925), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n643), .CK(clk), .RN(n926), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n651), .CK(clk), .RN(n1645), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n621), .CK(clk), .RN(n923), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n633), .CK(clk), .RN(n1645), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n637), .CK(clk), .RN(n926), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n641), .CK(clk), .RN(n978), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n866), .CK(clk), .RN(n1627),
.Q(intDY_EWSW[10]), .QN(n927) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n617), .CK(clk), .RN(n1637), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n629), .CK(clk), .RN(n978), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n615), .CK(clk), .RN(n1637), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n645), .CK(clk), .RN(n926), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n653), .CK(clk), .RN(n1638), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n655), .CK(clk), .RN(n1638), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n657), .CK(clk), .RN(n1638), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n750), .CK(clk), .RN(n925), .Q(
DMP_SFG[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n765), .CK(clk), .RN(n1633), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n534), .CK(clk), .RN(n926), .Q(
DmP_mant_SFG_SWR[7]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n537), .CK(clk), .RN(n1642), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n545), .CK(clk), .RN(n1642), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n553), .CK(clk), .RN(n1640), .Q(
DmP_mant_SFG_SWR[6]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n558), .CK(clk), .RN(n1644), .Q(
DmP_mant_SFG_SWR[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n563), .CK(clk), .RN(n1636), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n576), .CK(clk), .RN(n1636), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n513), .CK(clk), .RN(n1644), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n514), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n517), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n518), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n520), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n521), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n522), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n523), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n524), .CK(clk), .RN(n1643), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n814), .CK(clk), .RN(n1630),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n861), .CK(clk), .RN(n1629),
.Q(intDY_EWSW[15]), .QN(n1652) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n856), .CK(clk), .RN(n923), .Q(
intDY_EWSW[20]), .QN(n1582) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n855), .CK(clk), .RN(n1630),
.Q(intDY_EWSW[21]), .QN(n1577) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n778), .CK(clk), .RN(n1632), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n679), .CK(clk), .RN(n925), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n684), .CK(clk), .RN(n924), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n689), .CK(clk), .RN(n924), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n845), .CK(clk), .RN(n1625),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n898), .CK(clk), .RN(n1624),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n890), .CK(clk), .RN(n1625),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n896), .CK(clk), .RN(n1624),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n888), .CK(clk), .RN(n1626),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n909), .CK(clk), .RN(n1626), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n873), .CK(clk), .RN(n1628), .Q(
intDY_EWSW[3]), .QN(n1650) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n848), .CK(clk), .RN(n1626),
.Q(intDY_EWSW[28]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n865), .CK(clk), .RN(n979), .Q(
intDY_EWSW[11]), .QN(n1651) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n891), .CK(clk), .RN(n1628),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n836), .CK(clk), .RN(n979), .Q(
Data_array_SWR[16]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n565), .CK(clk), .RN(n1634), .Q(
DmP_mant_SFG_SWR[0]), .QN(n966) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n612), .CK(clk), .RN(n1637), .Q(
DmP_EXP_EWSW[23]), .QN(n973) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n674), .CK(clk), .RN(n924), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n819), .CK(clk), .RN(n1624), .Q(
Data_array_SWR[0]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n820), .CK(clk), .RN(n1630), .Q(
Data_array_SWR[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n608), .CK(clk), .RN(n1640), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n573), .CK(clk), .RN(n923), .Q(
DmP_mant_SFG_SWR[1]), .QN(n963) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n570), .CK(clk), .RN(n1637), .Q(
DmP_mant_SFG_SWR[8]), .QN(n964) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n550), .CK(clk), .RN(n925), .Q(
DmP_mant_SFG_SWR[4]), .QN(n967) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n511), .CK(clk), .RN(n1644), .Q(
DmP_mant_SFG_SWR[25]), .QN(n970) );
ADDFX1TS DP_OP_15J36_125_2314_U8 ( .A(n1561), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J36_125_2314_n8), .CO(DP_OP_15J36_125_2314_n7), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J36_125_2314_U7 ( .A(n1569), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J36_125_2314_n7), .CO(DP_OP_15J36_125_2314_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J36_125_2314_U6 ( .A(n1568), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J36_125_2314_n6), .CO(DP_OP_15J36_125_2314_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J36_125_2314_U5 ( .A(n1573), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J36_125_2314_n5), .CO(DP_OP_15J36_125_2314_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n659), .CK(clk), .RN(n978), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1600) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n912), .CK(clk), .RN(n1625), .Q(
Shift_reg_FLAGS_7[1]), .QN(n920) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n917), .CK(clk), .RN(n1624), .Q(
Shift_reg_FLAGS_7_6), .QN(n975) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n913), .CK(clk), .RN(n1631), .Q(
n928), .QN(n1648) );
AOI211X1TS U927 ( .A0(n1423), .A1(Data_array_SWR[3]), .B0(n1003), .C0(n1002),
.Y(n1008) );
AOI211X1TS U928 ( .A0(n1423), .A1(Data_array_SWR[2]), .B0(n1012), .C0(n1011),
.Y(n1430) );
AOI222X4TS U929 ( .A0(Data_array_SWR[20]), .A1(n945), .B0(Data_array_SWR[16]), .B1(n944), .C0(Data_array_SWR[24]), .C1(n1422), .Y(n1421) );
CLKINVX6TS U930 ( .A(rst), .Y(n978) );
NOR2XLTS U931 ( .A(n1239), .B(n1352), .Y(n1220) );
CLKINVX6TS U932 ( .A(n1360), .Y(n1214) );
INVX6TS U933 ( .A(n1341), .Y(n921) );
AOI31XLTS U934 ( .A0(n1207), .A1(Raw_mant_NRM_SWR[8]), .A2(n1563), .B0(n1316), .Y(n1208) );
NOR2XLTS U935 ( .A(n1292), .B(n1322), .Y(n998) );
AND2X4TS U936 ( .A(Shift_reg_FLAGS_7_6), .B(n1088), .Y(n1098) );
CLKINVX3TS U937 ( .A(n1336), .Y(n1335) );
CLKINVX3TS U938 ( .A(n1331), .Y(n1334) );
INVX6TS U939 ( .A(n1366), .Y(n1212) );
BUFX6TS U940 ( .A(n1627), .Y(n1628) );
INVX4TS U941 ( .A(n1009), .Y(n1000) );
BUFX6TS U942 ( .A(n980), .Y(n922) );
INVX3TS U943 ( .A(n1458), .Y(n999) );
NOR2X6TS U944 ( .A(shift_value_SHT2_EWR[4]), .B(n932), .Y(n1001) );
INVX6TS U945 ( .A(Shift_reg_FLAGS_7_6), .Y(n1089) );
BUFX6TS U946 ( .A(n926), .Y(n923) );
OR2X2TS U947 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]), .Y(
n1448) );
BUFX6TS U948 ( .A(n978), .Y(n924) );
BUFX6TS U949 ( .A(n1645), .Y(n925) );
BUFX6TS U950 ( .A(n978), .Y(n926) );
NAND2BXLTS U951 ( .AN(n959), .B(intDY_EWSW[2]), .Y(n1037) );
NAND2BXLTS U952 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1071) );
NAND2BXLTS U953 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n1025) );
NAND2BXLTS U954 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1050) );
OAI2BB2XLTS U955 ( .B0(intDY_EWSW[14]), .B1(n1056), .A0N(intDX_EWSW[15]),
.A1N(n1652), .Y(n1057) );
NAND2BXLTS U956 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1046) );
NAND2BXLTS U957 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1065) );
AOI222X4TS U958 ( .A0(Data_array_SWR[20]), .A1(n1000), .B0(
Data_array_SWR[16]), .B1(n1001), .C0(Data_array_SWR[24]), .C1(n999),
.Y(n1456) );
AOI222X1TS U959 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n921), .B0(n1350), .B1(n950), .C0(n1349), .C1(DmP_mant_SHT1_SW[14]), .Y(n1244) );
AOI222X1TS U960 ( .A0(n1290), .A1(DMP_SFG[1]), .B0(n1290), .B1(n1434), .C0(
DMP_SFG[1]), .C1(n1434), .Y(intadd_42_B_0_) );
AOI222X1TS U961 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n921), .B0(
DmP_mant_SHT1_SW[20]), .B1(n1349), .C0(n1350), .C1(n948), .Y(n1264) );
AOI211X1TS U962 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n920), .B0(n1349), .C0(
n1338), .Y(n1343) );
AOI222X1TS U963 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n921), .B0(n1350), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1349), .C1(DmP_mant_SHT1_SW[8]), .Y(n1275)
);
AOI222X1TS U964 ( .A0(n1495), .A1(n1517), .B0(Data_array_SWR[8]), .B1(n1494),
.C0(n1493), .C1(n1492), .Y(n1506) );
AOI222X1TS U965 ( .A0(n1495), .A1(n1485), .B0(n1518), .B1(Data_array_SWR[8]),
.C0(n1493), .C1(n1470), .Y(n1491) );
NAND2BXLTS U966 ( .AN(n1320), .B(n986), .Y(n989) );
BUFX4TS U967 ( .A(n1623), .Y(n1390) );
AOI222X1TS U968 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n921), .B0(n1350), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1349), .C1(DmP_mant_SHT1_SW[3]), .Y(n1283)
);
AOI222X1TS U969 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n921), .B0(n1350), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1349), .C1(n947), .Y(n1279) );
AOI222X1TS U970 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n921), .B0(n1350), .B1(n952), .C0(n1349), .C1(DmP_mant_SHT1_SW[10]), .Y(n1272) );
AOI222X1TS U971 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n921), .B0(n1350), .B1(n951), .C0(n1349), .C1(DmP_mant_SHT1_SW[12]), .Y(n1268) );
AO22XLTS U972 ( .A0(n1520), .A1(n1474), .B0(n1505), .B1(DmP_mant_SFG_SWR[11]), .Y(n576) );
AO22XLTS U973 ( .A0(n1520), .A1(n1489), .B0(n922), .B1(DmP_mant_SFG_SWR[2]),
.Y(n563) );
AO22XLTS U974 ( .A0(n1520), .A1(DMP_SHT2_EWSW[0]), .B0(n1389), .B1(
DMP_SFG[0]), .Y(n765) );
AO22XLTS U975 ( .A0(n1503), .A1(DMP_SHT2_EWSW[5]), .B0(n922), .B1(DMP_SFG[5]), .Y(n750) );
AO22XLTS U976 ( .A0(n1397), .A1(DmP_EXP_EWSW[0]), .B0(n1399), .B1(
DmP_mant_SHT1_SW[0]), .Y(n657) );
AO22XLTS U977 ( .A0(n1397), .A1(DmP_EXP_EWSW[1]), .B0(n1391), .B1(
DmP_mant_SHT1_SW[1]), .Y(n655) );
AO22XLTS U978 ( .A0(n1397), .A1(DmP_EXP_EWSW[2]), .B0(n1401), .B1(
DmP_mant_SHT1_SW[2]), .Y(n653) );
AO22XLTS U979 ( .A0(n1397), .A1(DmP_EXP_EWSW[6]), .B0(n1399), .B1(
DmP_mant_SHT1_SW[6]), .Y(n645) );
AO22XLTS U980 ( .A0(n1397), .A1(DmP_EXP_EWSW[21]), .B0(n1391), .B1(
DmP_mant_SHT1_SW[21]), .Y(n615) );
AO22XLTS U981 ( .A0(n1402), .A1(DmP_EXP_EWSW[20]), .B0(n1399), .B1(
DmP_mant_SHT1_SW[20]), .Y(n617) );
AO22XLTS U982 ( .A0(n1397), .A1(DmP_EXP_EWSW[8]), .B0(n1401), .B1(
DmP_mant_SHT1_SW[8]), .Y(n641) );
AO22XLTS U983 ( .A0(n1397), .A1(DmP_EXP_EWSW[10]), .B0(n1399), .B1(
DmP_mant_SHT1_SW[10]), .Y(n637) );
AO22XLTS U984 ( .A0(n1397), .A1(DmP_EXP_EWSW[12]), .B0(n1391), .B1(
DmP_mant_SHT1_SW[12]), .Y(n633) );
AO22XLTS U985 ( .A0(n1397), .A1(DmP_EXP_EWSW[18]), .B0(n1401), .B1(
DmP_mant_SHT1_SW[18]), .Y(n621) );
AO22XLTS U986 ( .A0(n1397), .A1(DmP_EXP_EWSW[3]), .B0(n1620), .B1(
DmP_mant_SHT1_SW[3]), .Y(n651) );
AO22XLTS U987 ( .A0(n1397), .A1(DmP_EXP_EWSW[7]), .B0(n1399), .B1(
DmP_mant_SHT1_SW[7]), .Y(n643) );
AO22XLTS U988 ( .A0(n1402), .A1(DmP_EXP_EWSW[17]), .B0(n1399), .B1(
DmP_mant_SHT1_SW[17]), .Y(n623) );
AO22XLTS U989 ( .A0(n1327), .A1(n1429), .B0(n1328), .B1(n946), .Y(n913) );
AO22XLTS U990 ( .A0(n1332), .A1(Data_X[31]), .B0(n1330), .B1(intDX_EWSW[31]),
.Y(n879) );
AO22XLTS U991 ( .A0(n1503), .A1(DMP_SHT2_EWSW[7]), .B0(n922), .B1(DMP_SFG[7]), .Y(n744) );
AO22XLTS U992 ( .A0(n1514), .A1(DMP_SHT2_EWSW[1]), .B0(n1389), .B1(
DMP_SFG[1]), .Y(n762) );
AO22XLTS U993 ( .A0(n1503), .A1(DMP_SHT2_EWSW[9]), .B0(n922), .B1(DMP_SFG[9]), .Y(n738) );
AO22XLTS U994 ( .A0(n928), .A1(intadd_43_SUM_0_), .B0(n1442), .B1(
Raw_mant_NRM_SWR[8]), .Y(n569) );
AO22XLTS U995 ( .A0(n1402), .A1(DmP_EXP_EWSW[15]), .B0(n1391), .B1(n949),
.Y(n627) );
AO22XLTS U996 ( .A0(n1402), .A1(DmP_EXP_EWSW[13]), .B0(n1401), .B1(n950),
.Y(n631) );
AO22XLTS U997 ( .A0(n1397), .A1(DmP_EXP_EWSW[11]), .B0(n1620), .B1(n951),
.Y(n635) );
AO22XLTS U998 ( .A0(n1397), .A1(DmP_EXP_EWSW[9]), .B0(n1399), .B1(n952), .Y(
n639) );
AO22XLTS U999 ( .A0(n1397), .A1(DmP_EXP_EWSW[5]), .B0(n1399), .B1(n953), .Y(
n647) );
AO22XLTS U1000 ( .A0(n1397), .A1(DmP_EXP_EWSW[4]), .B0(n1401), .B1(n947),
.Y(n649) );
AO22XLTS U1001 ( .A0(n1503), .A1(DMP_SHT2_EWSW[6]), .B0(n1389), .B1(n955),
.Y(n747) );
AO22XLTS U1002 ( .A0(n1328), .A1(busy), .B0(n1327), .B1(n946), .Y(n914) );
OR2X1TS U1003 ( .A(shift_value_SHT2_EWR[3]), .B(n1557), .Y(n932) );
NOR2BX2TS U1004 ( .AN(n1311), .B(n1310), .Y(n1200) );
NAND4XLTS U1005 ( .A(n1521), .B(n1522), .C(n1549), .D(n1530), .Y(n1310) );
BUFX4TS U1006 ( .A(n978), .Y(n1639) );
BUFX4TS U1007 ( .A(n923), .Y(n1644) );
BUFX4TS U1008 ( .A(n1643), .Y(n1633) );
BUFX4TS U1009 ( .A(n1632), .Y(n1635) );
BUFX4TS U1010 ( .A(n1635), .Y(n1638) );
BUFX4TS U1011 ( .A(n1637), .Y(n1632) );
BUFX4TS U1012 ( .A(n1640), .Y(n1643) );
CLKINVX6TS U1013 ( .A(n1391), .Y(n1400) );
BUFX6TS U1014 ( .A(n1620), .Y(n1399) );
BUFX4TS U1015 ( .A(n926), .Y(n1636) );
BUFX4TS U1016 ( .A(n1639), .Y(n1634) );
BUFX3TS U1017 ( .A(n978), .Y(n1645) );
BUFX6TS U1018 ( .A(n976), .Y(n1332) );
BUFX4TS U1019 ( .A(n976), .Y(n1336) );
BUFX4TS U1020 ( .A(n976), .Y(n1331) );
OR2X1TS U1021 ( .A(n920), .B(n1217), .Y(n1341) );
BUFX4TS U1022 ( .A(n923), .Y(n1625) );
BUFX4TS U1023 ( .A(n1633), .Y(n1624) );
BUFX4TS U1024 ( .A(n1630), .Y(n1631) );
BUFX4TS U1025 ( .A(n1627), .Y(n1626) );
NOR2X4TS U1026 ( .A(n1448), .B(shift_value_SHT2_EWR[4]), .Y(n1423) );
INVX2TS U1027 ( .A(n1448), .Y(n944) );
INVX2TS U1028 ( .A(n932), .Y(n945) );
INVX2TS U1029 ( .A(n938), .Y(n946) );
INVX2TS U1030 ( .A(n943), .Y(n947) );
INVX2TS U1031 ( .A(n937), .Y(n948) );
INVX2TS U1032 ( .A(n936), .Y(n949) );
INVX2TS U1033 ( .A(n942), .Y(n950) );
INVX2TS U1034 ( .A(n941), .Y(n951) );
INVX2TS U1035 ( .A(n935), .Y(n952) );
INVX2TS U1036 ( .A(n940), .Y(n953) );
INVX2TS U1037 ( .A(n939), .Y(n954) );
INVX2TS U1038 ( .A(n929), .Y(n955) );
CLKINVX3TS U1039 ( .A(n1462), .Y(n1518) );
CLKINVX3TS U1040 ( .A(n1488), .Y(n1494) );
INVX3TS U1041 ( .A(n1286), .Y(n1358) );
CLKINVX6TS U1042 ( .A(n1517), .Y(n1485) );
BUFX6TS U1043 ( .A(left_right_SHT2), .Y(n1517) );
BUFX6TS U1044 ( .A(n1216), .Y(n1356) );
AO22XLTS U1045 ( .A0(n1490), .A1(n1512), .B0(final_result_ieee[20]), .B1(
n1646), .Y(n527) );
AO22XLTS U1046 ( .A0(n1490), .A1(n1483), .B0(final_result_ieee[5]), .B1(
n1646), .Y(n533) );
AO22XLTS U1047 ( .A0(n1490), .A1(n1445), .B0(final_result_ieee[4]), .B1(
n1646), .Y(n552) );
AO22XLTS U1048 ( .A0(n1490), .A1(n1437), .B0(final_result_ieee[1]), .B1(
n1646), .Y(n531) );
AO22XLTS U1049 ( .A0(n1490), .A1(n1513), .B0(final_result_ieee[21]), .B1(
n1646), .Y(n526) );
BUFX4TS U1050 ( .A(n998), .Y(n1490) );
CLKINVX6TS U1051 ( .A(n1648), .Y(n1444) );
CLKINVX6TS U1052 ( .A(n1648), .Y(n1429) );
BUFX6TS U1053 ( .A(n1238), .Y(n1349) );
BUFX6TS U1054 ( .A(n1211), .Y(n1350) );
NOR2XLTS U1055 ( .A(Shift_reg_FLAGS_7[1]), .B(Shift_amount_SHT1_EWR[0]), .Y(
n1211) );
INVX3TS U1056 ( .A(n922), .Y(n1520) );
CLKINVX6TS U1057 ( .A(n1332), .Y(n1330) );
INVX2TS U1058 ( .A(n933), .Y(n956) );
INVX2TS U1059 ( .A(n934), .Y(n957) );
AOI32X1TS U1060 ( .A0(n1599), .A1(n1071), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1543), .Y(n1072) );
AOI221X1TS U1061 ( .A0(n1599), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1543), .C0(n1151), .Y(n1156) );
AOI221X1TS U1062 ( .A0(n927), .A1(n958), .B0(intDX_EWSW[11]), .B1(n1651),
.C0(n1159), .Y(n1164) );
AOI221X1TS U1063 ( .A0(n1583), .A1(intDX_EWSW[27]), .B0(intDY_EWSW[28]),
.B1(n1598), .C0(n1144), .Y(n1148) );
INVX2TS U1064 ( .A(n931), .Y(n958) );
AOI221X1TS U1065 ( .A0(n1578), .A1(n959), .B0(intDX_EWSW[3]), .B1(n1650),
.C0(n1167), .Y(n1172) );
INVX2TS U1066 ( .A(n930), .Y(n959) );
AOI221X1TS U1067 ( .A0(n1595), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[17]), .B1(
n1594), .C0(n1150), .Y(n1157) );
AOI221X1TS U1068 ( .A0(n1541), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1586), .C0(n1153), .Y(n1154) );
AOI221X1TS U1069 ( .A0(n1581), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1652), .C0(n1161), .Y(n1162) );
OAI211X2TS U1070 ( .A0(intDX_EWSW[20]), .A1(n1582), .B0(n1079), .C0(n1065),
.Y(n1074) );
AOI221X1TS U1071 ( .A0(n1582), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1577), .C0(n1152), .Y(n1155) );
OAI211X2TS U1072 ( .A0(intDX_EWSW[12]), .A1(n1580), .B0(n1060), .C0(n1046),
.Y(n1062) );
AOI221X1TS U1073 ( .A0(n1580), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1576), .C0(n1160), .Y(n1163) );
INVX6TS U1074 ( .A(OP_FLAG_SFG), .Y(n960) );
INVX1TS U1075 ( .A(DMP_SFG[3]), .Y(intadd_42_A_1_) );
OAI31XLTS U1076 ( .A0(n1388), .A1(n1181), .A2(n1394), .B0(n1180), .Y(n768)
);
NOR2X2TS U1077 ( .A(n973), .B(DMP_EXP_EWSW[23]), .Y(n1373) );
NOR2X2TS U1078 ( .A(shift_value_SHT2_EWR[2]), .B(n1564), .Y(n1422) );
BUFX4TS U1079 ( .A(n924), .Y(n1627) );
XNOR2X2TS U1080 ( .A(DMP_exp_NRM2_EW[6]), .B(n987), .Y(n1320) );
XNOR2X2TS U1081 ( .A(DMP_exp_NRM2_EW[0]), .B(n1298), .Y(n1318) );
XNOR2X2TS U1082 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J36_125_2314_n4), .Y(
n1319) );
OAI22X2TS U1083 ( .A0(n1587), .A1(n1448), .B0(n1537), .B1(n932), .Y(n1466)
);
AO22XLTS U1084 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n960), .B0(n1427), .B1(n968),
.Y(intadd_42_B_1_) );
INVX2TS U1085 ( .A(intadd_42_B_1_), .Y(n961) );
AOI222X4TS U1086 ( .A0(intadd_42_A_1_), .A1(n961), .B0(intadd_42_A_1_), .B1(
n1407), .C0(n961), .C1(n1407), .Y(n1408) );
AOI2BB2X2TS U1087 ( .B0(DmP_mant_SFG_SWR[11]), .B1(n1427), .A0N(n1427),
.A1N(DmP_mant_SFG_SWR[11]), .Y(n1412) );
AOI2BB2X2TS U1088 ( .B0(DmP_mant_SFG_SWR[3]), .B1(n1427), .A0N(n1427), .A1N(
DmP_mant_SFG_SWR[3]), .Y(n1434) );
AOI2BB2X2TS U1089 ( .B0(DmP_mant_SFG_SWR[9]), .B1(n1427), .A0N(OP_FLAG_SFG),
.A1N(DmP_mant_SFG_SWR[9]), .Y(intadd_43_B_1_) );
AOI222X1TS U1090 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n921), .B0(n1350), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1349), .C1(DmP_mant_SHT1_SW[7]), .Y(n1287)
);
AOI222X1TS U1091 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n921), .B0(n1350), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1349), .C1(DmP_mant_SHT1_SW[18]), .Y(n1267) );
AOI222X1TS U1092 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n921), .B0(n1350), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1238), .C1(DmP_mant_SHT1_SW[17]), .Y(n1258) );
NOR4BBX2TS U1093 ( .AN(n1198), .BN(n1023), .C(n1193), .D(n1022), .Y(n1239)
);
AOI222X1TS U1094 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n921), .B0(n1350), .B1(
DmP_mant_SHT1_SW[21]), .C0(n1349), .C1(DmP_mant_SHT1_SW[22]), .Y(n1261) );
NAND2X4TS U1095 ( .A(n920), .B(n1390), .Y(n1366) );
INVX4TS U1096 ( .A(n1098), .Y(n1392) );
AOI222X1TS U1097 ( .A0(n1473), .A1(n1485), .B0(n1518), .B1(Data_array_SWR[5]), .C0(n1472), .C1(n1470), .Y(n1471) );
AOI222X1TS U1098 ( .A0(n1473), .A1(n1517), .B0(Data_array_SWR[5]), .B1(n1494), .C0(n1472), .C1(n1492), .Y(n1510) );
AOI222X1TS U1099 ( .A0(n1452), .A1(n1485), .B0(n1518), .B1(Data_array_SWR[4]), .C0(n1466), .C1(n1470), .Y(n1451) );
AOI222X1TS U1100 ( .A0(n1452), .A1(n1517), .B0(Data_array_SWR[4]), .B1(n1494), .C0(n1466), .C1(n1492), .Y(n1511) );
CLKINVX6TS U1101 ( .A(n1390), .Y(n1403) );
AOI222X4TS U1102 ( .A0(n1412), .A1(DMP_SFG[9]), .B0(n1412), .B1(n1297), .C0(
DMP_SFG[9]), .C1(n1297), .Y(intadd_41_B_0_) );
AOI222X4TS U1103 ( .A0(Data_array_SWR[19]), .A1(n1000), .B0(
Data_array_SWR[23]), .B1(n999), .C0(Data_array_SWR[15]), .C1(n1001),
.Y(n1455) );
AOI222X4TS U1104 ( .A0(Data_array_SWR[19]), .A1(n945), .B0(
Data_array_SWR[23]), .B1(n1422), .C0(Data_array_SWR[15]), .C1(n944),
.Y(n1465) );
AOI22X2TS U1105 ( .A0(Data_array_SWR[21]), .A1(n945), .B0(Data_array_SWR[17]), .B1(n944), .Y(n1486) );
AOI222X4TS U1106 ( .A0(Data_array_SWR[21]), .A1(n999), .B0(
Data_array_SWR[13]), .B1(n1001), .C0(Data_array_SWR[17]), .C1(n1000),
.Y(n1481) );
AOI222X4TS U1107 ( .A0(Data_array_SWR[22]), .A1(n999), .B0(
Data_array_SWR[18]), .B1(n1000), .C0(Data_array_SWR[14]), .C1(n1001),
.Y(n1476) );
AOI22X2TS U1108 ( .A0(Data_array_SWR[22]), .A1(n945), .B0(Data_array_SWR[18]), .B1(n944), .Y(n1447) );
NOR2X2TS U1109 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1570), .Y(n1325) );
NOR3X2TS U1110 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .C(n1210),
.Y(n1203) );
NOR2X2TS U1111 ( .A(Raw_mant_NRM_SWR[13]), .B(n1013), .Y(n1204) );
AOI222X1TS U1112 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n921), .B0(n1350), .B1(n949), .C0(n1349), .C1(DmP_mant_SHT1_SW[16]), .Y(n1251) );
AOI32X1TS U1113 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1019), .A2(n1018), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1019), .Y(n1020) );
OAI21X2TS U1114 ( .A0(intDX_EWSW[18]), .A1(n1599), .B0(n1071), .Y(n1151) );
NOR3X1TS U1115 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1311) );
INVX2TS U1116 ( .A(Shift_reg_FLAGS_7[0]), .Y(n962) );
AO22XLTS U1117 ( .A0(n1328), .A1(n920), .B0(n962), .B1(n1327), .Y(n965) );
AND2X2TS U1118 ( .A(beg_OP), .B(n1329), .Y(n976) );
NOR2XLTS U1119 ( .A(n1651), .B(intDX_EWSW[11]), .Y(n1048) );
OAI21XLTS U1120 ( .A0(intDX_EWSW[15]), .A1(n1652), .B0(intDX_EWSW[14]), .Y(
n1056) );
NOR2XLTS U1121 ( .A(n1069), .B(intDY_EWSW[16]), .Y(n1070) );
OAI21XLTS U1122 ( .A0(intDX_EWSW[21]), .A1(n1577), .B0(intDX_EWSW[20]), .Y(
n1068) );
OAI21XLTS U1123 ( .A0(n1524), .A1(n1352), .B0(n1351), .Y(n1353) );
OAI21XLTS U1124 ( .A0(n1181), .A1(n1089), .B0(n1178), .Y(n1179) );
OAI21XLTS U1125 ( .A0(DmP_EXP_EWSW[25]), .A1(n1605), .B0(n1377), .Y(n1374)
);
OAI21XLTS U1126 ( .A0(n1523), .A1(n1352), .B0(n1284), .Y(n1285) );
AOI31XLTS U1127 ( .A0(n1403), .A1(Shift_amount_SHT1_EWR[4]), .A2(n920), .B0(
n1300), .Y(n1196) );
OAI21XLTS U1128 ( .A0(n1431), .A1(DMP_SFG[0]), .B0(n1433), .Y(n1432) );
OAI21XLTS U1129 ( .A0(n1575), .A1(n1392), .B0(n1115), .Y(n640) );
OAI21XLTS U1130 ( .A0(n1578), .A1(n1178), .B0(n1114), .Y(n654) );
OAI21XLTS U1131 ( .A0(n1542), .A1(n1392), .B0(n1119), .Y(n771) );
OAI21XLTS U1132 ( .A0(n1576), .A1(n1185), .B0(n1184), .Y(n788) );
OAI211XLTS U1133 ( .A0(n1268), .A1(n1356), .B0(n1246), .C0(n1245), .Y(n832)
);
NOR2XLTS U1134 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n977) );
AOI32X4TS U1135 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n977), .B1(n1570), .Y(n1328)
);
INVX2TS U1136 ( .A(n1328), .Y(n1327) );
BUFX3TS U1137 ( .A(n924), .Y(n1637) );
CLKBUFX2TS U1138 ( .A(n924), .Y(n979) );
BUFX3TS U1139 ( .A(n924), .Y(n1640) );
BUFX3TS U1140 ( .A(n978), .Y(n1642) );
BUFX3TS U1141 ( .A(n924), .Y(n1630) );
BUFX3TS U1142 ( .A(n924), .Y(n1629) );
AO22XLTS U1143 ( .A0(Shift_reg_FLAGS_7[1]), .A1(ZERO_FLAG_NRM), .B0(n920),
.B1(ZERO_FLAG_SHT1SHT2), .Y(n601) );
AO22XLTS U1144 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n920),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n592) );
NAND2X1TS U1145 ( .A(n946), .B(n1646), .Y(n980) );
BUFX3TS U1146 ( .A(n922), .Y(n1389) );
INVX4TS U1147 ( .A(n922), .Y(n1508) );
AO22XLTS U1148 ( .A0(n1389), .A1(DMP_SFG[20]), .B0(n1508), .B1(
DMP_SHT2_EWSW[20]), .Y(n705) );
AO22XLTS U1149 ( .A0(n1389), .A1(DMP_SFG[21]), .B0(n1508), .B1(
DMP_SHT2_EWSW[21]), .Y(n702) );
AO22XLTS U1150 ( .A0(n1389), .A1(DMP_SFG[18]), .B0(n1508), .B1(
DMP_SHT2_EWSW[18]), .Y(n711) );
AO22XLTS U1151 ( .A0(n1389), .A1(DMP_SFG[17]), .B0(n1508), .B1(
DMP_SHT2_EWSW[17]), .Y(n714) );
AO22XLTS U1152 ( .A0(n1389), .A1(DMP_SFG[16]), .B0(n1508), .B1(
DMP_SHT2_EWSW[16]), .Y(n717) );
AO22XLTS U1153 ( .A0(n1389), .A1(DMP_SFG[8]), .B0(n1508), .B1(
DMP_SHT2_EWSW[8]), .Y(n741) );
AO22XLTS U1154 ( .A0(n1648), .A1(Raw_mant_NRM_SWR[9]), .B0(n1444), .B1(
intadd_43_SUM_1_), .Y(n568) );
BUFX4TS U1155 ( .A(n1648), .Y(n1442) );
AO22XLTS U1156 ( .A0(n1442), .A1(Raw_mant_NRM_SWR[10]), .B0(n1444), .B1(
intadd_43_SUM_2_), .Y(n567) );
INVX2TS U1157 ( .A(DP_OP_15J36_125_2314_n4), .Y(n981) );
NAND2X1TS U1158 ( .A(n1571), .B(n981), .Y(n987) );
INVX1TS U1159 ( .A(LZD_output_NRM2_EW[0]), .Y(n1298) );
NOR2XLTS U1160 ( .A(n1318), .B(exp_rslt_NRM2_EW1[1]), .Y(n984) );
INVX2TS U1161 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n983) );
INVX2TS U1162 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n982) );
NAND4BXLTS U1163 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n984), .C(n983), .D(n982),
.Y(n985) );
NOR2XLTS U1164 ( .A(n985), .B(n1319), .Y(n986) );
INVX2TS U1165 ( .A(n987), .Y(n988) );
NAND2X1TS U1166 ( .A(n1588), .B(n988), .Y(n994) );
XNOR2X1TS U1167 ( .A(DMP_exp_NRM2_EW[7]), .B(n994), .Y(n990) );
OR2X1TS U1168 ( .A(n989), .B(n990), .Y(n1395) );
INVX2TS U1169 ( .A(n1395), .Y(n1292) );
INVX2TS U1170 ( .A(n990), .Y(n1291) );
AND4X1TS U1171 ( .A(exp_rslt_NRM2_EW1[3]), .B(n1318), .C(
exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n991) );
NAND3XLTS U1172 ( .A(n1319), .B(exp_rslt_NRM2_EW1[4]), .C(n991), .Y(n992) );
NAND2BXLTS U1173 ( .AN(n992), .B(n1320), .Y(n993) );
NOR2XLTS U1174 ( .A(n1291), .B(n993), .Y(n997) );
INVX2TS U1175 ( .A(n994), .Y(n995) );
CLKAND2X2TS U1176 ( .A(n1600), .B(n995), .Y(n996) );
OAI2BB1X1TS U1177 ( .A0N(n997), .A1N(n996), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1322) );
NAND3X1TS U1178 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.C(n1536), .Y(n1458) );
NAND2X1TS U1179 ( .A(n1536), .B(n1422), .Y(n1009) );
AO22XLTS U1180 ( .A0(Data_array_SWR[14]), .A1(n999), .B0(n957), .B1(n1000),
.Y(n1003) );
INVX2TS U1181 ( .A(n1001), .Y(n1010) );
OAI22X1TS U1182 ( .A0(n1447), .A1(n1536), .B0(n1612), .B1(n1010), .Y(n1002)
);
NAND2X2TS U1183 ( .A(n1485), .B(n1423), .Y(n1462) );
OAI22X1TS U1184 ( .A0(n1008), .A1(n1485), .B0(n1603), .B1(n1462), .Y(n1512)
);
NOR2X2TS U1185 ( .A(n1536), .B(n1448), .Y(n1460) );
AOI22X1TS U1186 ( .A0(Data_array_SWR[18]), .A1(n999), .B0(n957), .B1(n1001),
.Y(n1004) );
OAI2BB1X1TS U1187 ( .A0N(Data_array_SWR[14]), .A1N(n1000), .B0(n1004), .Y(
n1005) );
AOI21X1TS U1188 ( .A0(Data_array_SWR[22]), .A1(n1460), .B0(n1005), .Y(n1484)
);
NOR2X2TS U1189 ( .A(shift_value_SHT2_EWR[4]), .B(n1485), .Y(n1470) );
INVX2TS U1190 ( .A(n1470), .Y(n1461) );
OAI222X1TS U1191 ( .A0(n1462), .A1(n1612), .B0(n1517), .B1(n1484), .C0(n1461), .C1(n1486), .Y(n1483) );
AOI22X1TS U1192 ( .A0(Data_array_SWR[10]), .A1(n1001), .B0(
Data_array_SWR[17]), .B1(n999), .Y(n1006) );
OAI21XLTS U1193 ( .A0(n1546), .A1(n1009), .B0(n1006), .Y(n1007) );
AOI21X1TS U1194 ( .A0(Data_array_SWR[21]), .A1(n1460), .B0(n1007), .Y(n1446)
);
OAI222X1TS U1195 ( .A0(n1462), .A1(n1611), .B0(n1517), .B1(n1446), .C0(n1461), .C1(n1447), .Y(n1445) );
NAND2X2TS U1196 ( .A(n1517), .B(n1423), .Y(n1488) );
OAI22X1TS U1197 ( .A0(n1517), .A1(n1008), .B0(n1603), .B1(n1488), .Y(n1437)
);
OAI22X1TS U1198 ( .A0(n1546), .A1(n1458), .B0(n1606), .B1(n1009), .Y(n1012)
);
OAI22X1TS U1199 ( .A0(n1486), .A1(n1536), .B0(n1611), .B1(n1010), .Y(n1011)
);
OAI22X1TS U1200 ( .A0(n1430), .A1(n1485), .B0(n1604), .B1(n1462), .Y(n1513)
);
INVX4TS U1201 ( .A(n1390), .Y(busy) );
NOR2BX1TS U1202 ( .AN(n1200), .B(Raw_mant_NRM_SWR[18]), .Y(n1302) );
NOR3X1TS U1203 ( .A(Raw_mant_NRM_SWR[15]), .B(Raw_mant_NRM_SWR[17]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1303) );
CLKAND2X2TS U1204 ( .A(n1302), .B(n1303), .Y(n1301) );
NAND2X1TS U1205 ( .A(Raw_mant_NRM_SWR[14]), .B(n1301), .Y(n1198) );
NAND2X1TS U1206 ( .A(n1301), .B(n1523), .Y(n1013) );
NAND2X1TS U1207 ( .A(n1204), .B(n1550), .Y(n1014) );
NOR3X1TS U1208 ( .A(Raw_mant_NRM_SWR[12]), .B(n1553), .C(n1014), .Y(n1308)
);
AO21XLTS U1209 ( .A0(n1200), .A1(Raw_mant_NRM_SWR[18]), .B0(n1308), .Y(n1201) );
AOI31XLTS U1210 ( .A0(n1524), .A1(Raw_mant_NRM_SWR[11]), .A2(n1204), .B0(
n1201), .Y(n1023) );
NOR2XLTS U1211 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .Y(n1017)
);
NOR2X1TS U1212 ( .A(Raw_mant_NRM_SWR[10]), .B(n1014), .Y(n1207) );
NAND2X1TS U1213 ( .A(n1207), .B(n1524), .Y(n1190) );
NOR3X1TS U1214 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1190),
.Y(n1015) );
NAND2X1TS U1215 ( .A(n1015), .B(n1531), .Y(n1210) );
NAND2X1TS U1216 ( .A(n1203), .B(n1532), .Y(n1312) );
OAI21XLTS U1217 ( .A0(Raw_mant_NRM_SWR[7]), .A1(Raw_mant_NRM_SWR[6]), .B0(
n1015), .Y(n1016) );
OAI21X1TS U1218 ( .A0(n1017), .A1(n1312), .B0(n1016), .Y(n1193) );
NOR2XLTS U1219 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1021) );
NOR2X1TS U1220 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1019) );
NOR2XLTS U1221 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1018) );
AOI211X1TS U1222 ( .A0(n1021), .A1(n1020), .B0(Raw_mant_NRM_SWR[25]), .C0(
Raw_mant_NRM_SWR[24]), .Y(n1022) );
NOR2X1TS U1223 ( .A(n1239), .B(n920), .Y(n1213) );
AO21XLTS U1224 ( .A0(LZD_output_NRM2_EW[1]), .A1(n920), .B0(n1213), .Y(n559)
);
OAI21XLTS U1225 ( .A0(n1403), .A1(n1485), .B0(n920), .Y(n877) );
AOI2BB2X1TS U1226 ( .B0(DmP_mant_SFG_SWR[6]), .B1(n960), .A0N(n960), .A1N(
DmP_mant_SFG_SWR[6]), .Y(intadd_42_B_2_) );
NOR2X1TS U1227 ( .A(n1592), .B(intDX_EWSW[25]), .Y(n1082) );
NOR2XLTS U1228 ( .A(n1082), .B(intDY_EWSW[24]), .Y(n1024) );
AOI22X1TS U1229 ( .A0(intDX_EWSW[25]), .A1(n1592), .B0(intDX_EWSW[24]), .B1(
n1024), .Y(n1028) );
OAI21X1TS U1230 ( .A0(intDX_EWSW[26]), .A1(n1591), .B0(n1025), .Y(n1083) );
NAND3XLTS U1231 ( .A(n1591), .B(n1025), .C(intDX_EWSW[26]), .Y(n1027) );
NAND2BXLTS U1232 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n1026) );
OAI211XLTS U1233 ( .A0(n1028), .A1(n1083), .B0(n1027), .C0(n1026), .Y(n1033)
);
NOR2X1TS U1234 ( .A(n1565), .B(intDX_EWSW[30]), .Y(n1031) );
NOR2X1TS U1235 ( .A(n1535), .B(intDX_EWSW[29]), .Y(n1029) );
AOI211X1TS U1236 ( .A0(intDY_EWSW[28]), .A1(n1598), .B0(n1031), .C0(n1029),
.Y(n1081) );
NOR3X1TS U1237 ( .A(n1598), .B(n1029), .C(intDY_EWSW[28]), .Y(n1030) );
AOI221X1TS U1238 ( .A0(intDX_EWSW[30]), .A1(n1565), .B0(intDX_EWSW[29]),
.B1(n1535), .C0(n1030), .Y(n1032) );
AOI2BB2X1TS U1239 ( .B0(n1033), .B1(n1081), .A0N(n1032), .A1N(n1031), .Y(
n1087) );
NOR2X1TS U1240 ( .A(n1594), .B(intDX_EWSW[17]), .Y(n1069) );
OAI22X1TS U1241 ( .A0(n927), .A1(n958), .B0(n1651), .B1(intDX_EWSW[11]), .Y(
n1159) );
INVX2TS U1242 ( .A(n1159), .Y(n1053) );
OAI211XLTS U1243 ( .A0(intDX_EWSW[8]), .A1(n1596), .B0(n1050), .C0(n1053),
.Y(n1064) );
OAI2BB1X1TS U1244 ( .A0N(n1554), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n1034) );
OAI22X1TS U1245 ( .A0(intDY_EWSW[4]), .A1(n1034), .B0(n1554), .B1(
intDY_EWSW[5]), .Y(n1045) );
OAI2BB1X1TS U1246 ( .A0N(n1534), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n1035) );
OAI22X1TS U1247 ( .A0(intDY_EWSW[6]), .A1(n1035), .B0(n1534), .B1(
intDY_EWSW[7]), .Y(n1044) );
OAI21XLTS U1248 ( .A0(intDX_EWSW[1]), .A1(n1595), .B0(intDX_EWSW[0]), .Y(
n1036) );
OAI2BB2XLTS U1249 ( .B0(intDY_EWSW[0]), .B1(n1036), .A0N(intDX_EWSW[1]),
.A1N(n1595), .Y(n1038) );
OAI211XLTS U1250 ( .A0(n1650), .A1(intDX_EWSW[3]), .B0(n1038), .C0(n1037),
.Y(n1041) );
OAI21XLTS U1251 ( .A0(intDX_EWSW[3]), .A1(n1650), .B0(n959), .Y(n1039) );
AOI2BB2XLTS U1252 ( .B0(intDX_EWSW[3]), .B1(n1650), .A0N(intDY_EWSW[2]),
.A1N(n1039), .Y(n1040) );
AOI222X1TS U1253 ( .A0(intDY_EWSW[4]), .A1(n1533), .B0(n1041), .B1(n1040),
.C0(intDY_EWSW[5]), .C1(n1554), .Y(n1043) );
AOI22X1TS U1254 ( .A0(intDY_EWSW[7]), .A1(n1534), .B0(intDY_EWSW[6]), .B1(
n1556), .Y(n1042) );
OAI32X1TS U1255 ( .A0(n1045), .A1(n1044), .A2(n1043), .B0(n1042), .B1(n1044),
.Y(n1063) );
OA22X1TS U1256 ( .A0(n1581), .A1(intDX_EWSW[14]), .B0(n1652), .B1(
intDX_EWSW[15]), .Y(n1060) );
OAI21XLTS U1257 ( .A0(intDX_EWSW[13]), .A1(n1576), .B0(intDX_EWSW[12]), .Y(
n1047) );
OAI2BB2XLTS U1258 ( .B0(intDY_EWSW[12]), .B1(n1047), .A0N(intDX_EWSW[13]),
.A1N(n1576), .Y(n1059) );
NOR2XLTS U1259 ( .A(n1048), .B(intDY_EWSW[10]), .Y(n1049) );
AOI22X1TS U1260 ( .A0(intDX_EWSW[11]), .A1(n1651), .B0(n958), .B1(n1049),
.Y(n1055) );
NAND2BXLTS U1261 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1052) );
NAND3XLTS U1262 ( .A(n1596), .B(n1050), .C(intDX_EWSW[8]), .Y(n1051) );
AOI21X1TS U1263 ( .A0(n1052), .A1(n1051), .B0(n1062), .Y(n1054) );
OAI2BB2XLTS U1264 ( .B0(n1055), .B1(n1062), .A0N(n1054), .A1N(n1053), .Y(
n1058) );
AOI211X1TS U1265 ( .A0(n1060), .A1(n1059), .B0(n1058), .C0(n1057), .Y(n1061)
);
OAI31X1TS U1266 ( .A0(n1064), .A1(n1063), .A2(n1062), .B0(n1061), .Y(n1067)
);
OA22X1TS U1267 ( .A0(n1541), .A1(intDX_EWSW[22]), .B0(n1586), .B1(
intDX_EWSW[23]), .Y(n1079) );
AOI211XLTS U1268 ( .A0(intDY_EWSW[16]), .A1(n1562), .B0(n1074), .C0(n1151),
.Y(n1066) );
NAND3BXLTS U1269 ( .AN(n1069), .B(n1067), .C(n1066), .Y(n1086) );
OAI2BB2XLTS U1270 ( .B0(intDY_EWSW[20]), .B1(n1068), .A0N(intDX_EWSW[21]),
.A1N(n1577), .Y(n1078) );
AOI22X1TS U1271 ( .A0(intDX_EWSW[17]), .A1(n1594), .B0(intDX_EWSW[16]), .B1(
n1070), .Y(n1073) );
OAI32X1TS U1272 ( .A0(n1151), .A1(n1074), .A2(n1073), .B0(n1072), .B1(n1074),
.Y(n1077) );
OAI21XLTS U1273 ( .A0(intDX_EWSW[23]), .A1(n1586), .B0(intDX_EWSW[22]), .Y(
n1075) );
OAI2BB2XLTS U1274 ( .B0(intDY_EWSW[22]), .B1(n1075), .A0N(intDX_EWSW[23]),
.A1N(n1586), .Y(n1076) );
AOI211X1TS U1275 ( .A0(n1079), .A1(n1078), .B0(n1077), .C0(n1076), .Y(n1085)
);
NAND2BXLTS U1276 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1080) );
NAND4BBX1TS U1277 ( .AN(n1083), .BN(n1082), .C(n1081), .D(n1080), .Y(n1084)
);
AOI32X1TS U1278 ( .A0(n1087), .A1(n1086), .A2(n1085), .B0(n1084), .B1(n1087),
.Y(n1088) );
NOR2X1TS U1279 ( .A(n1088), .B(n975), .Y(n1099) );
INVX4TS U1280 ( .A(n1099), .Y(n1394) );
BUFX4TS U1281 ( .A(n1089), .Y(n1186) );
AOI22X1TS U1282 ( .A0(intDX_EWSW[22]), .A1(n1098), .B0(DMP_EXP_EWSW[22]),
.B1(n1186), .Y(n1090) );
OAI21XLTS U1283 ( .A0(n1541), .A1(n1394), .B0(n1090), .Y(n779) );
BUFX4TS U1284 ( .A(n1089), .Y(n1326) );
AOI22X1TS U1285 ( .A0(n954), .A1(n1326), .B0(intDX_EWSW[27]), .B1(n1098),
.Y(n1091) );
OAI21XLTS U1286 ( .A0(n1583), .A1(n1394), .B0(n1091), .Y(n774) );
AOI22X1TS U1287 ( .A0(intDX_EWSW[20]), .A1(n1098), .B0(DMP_EXP_EWSW[20]),
.B1(n1186), .Y(n1092) );
OAI21XLTS U1288 ( .A0(n1582), .A1(n1394), .B0(n1092), .Y(n781) );
INVX4TS U1289 ( .A(n1138), .Y(n1185) );
AOI22X1TS U1290 ( .A0(DMP_EXP_EWSW[23]), .A1(n1326), .B0(intDX_EWSW[23]),
.B1(n1098), .Y(n1093) );
OAI21XLTS U1291 ( .A0(n1586), .A1(n1185), .B0(n1093), .Y(n778) );
AOI22X1TS U1292 ( .A0(intDX_EWSW[4]), .A1(n1098), .B0(DMP_EXP_EWSW[4]), .B1(
n1089), .Y(n1094) );
OAI21XLTS U1293 ( .A0(n1579), .A1(n1394), .B0(n1094), .Y(n797) );
AOI22X1TS U1294 ( .A0(intDX_EWSW[5]), .A1(n1098), .B0(DMP_EXP_EWSW[5]), .B1(
n1089), .Y(n1095) );
OAI21XLTS U1295 ( .A0(n1539), .A1(n1185), .B0(n1095), .Y(n796) );
AOI22X1TS U1296 ( .A0(intDX_EWSW[7]), .A1(n1098), .B0(DMP_EXP_EWSW[7]), .B1(
n1089), .Y(n1096) );
OAI21XLTS U1297 ( .A0(n1584), .A1(n1185), .B0(n1096), .Y(n794) );
AOI22X1TS U1298 ( .A0(intDX_EWSW[6]), .A1(n1098), .B0(DMP_EXP_EWSW[6]), .B1(
n1089), .Y(n1097) );
OAI21XLTS U1299 ( .A0(n1574), .A1(n1185), .B0(n1097), .Y(n795) );
BUFX3TS U1300 ( .A(n1099), .Y(n1138) );
BUFX4TS U1301 ( .A(n1138), .Y(n1126) );
AOI22X1TS U1302 ( .A0(intDX_EWSW[18]), .A1(n1126), .B0(DmP_EXP_EWSW[18]),
.B1(n1326), .Y(n1100) );
OAI21XLTS U1303 ( .A0(n1599), .A1(n1392), .B0(n1100), .Y(n622) );
AOI22X1TS U1304 ( .A0(intDY_EWSW[28]), .A1(n1126), .B0(DMP_EXP_EWSW[28]),
.B1(n1186), .Y(n1101) );
OAI21XLTS U1305 ( .A0(n1598), .A1(n1178), .B0(n1101), .Y(n773) );
AOI22X1TS U1306 ( .A0(intDX_EWSW[19]), .A1(n1126), .B0(DmP_EXP_EWSW[19]),
.B1(n1326), .Y(n1102) );
OAI21XLTS U1307 ( .A0(n1543), .A1(n1392), .B0(n1102), .Y(n620) );
AOI22X1TS U1308 ( .A0(intDX_EWSW[22]), .A1(n1126), .B0(DmP_EXP_EWSW[22]),
.B1(n1326), .Y(n1103) );
OAI21XLTS U1309 ( .A0(n1541), .A1(n1392), .B0(n1103), .Y(n614) );
AOI22X1TS U1310 ( .A0(intDX_EWSW[17]), .A1(n1126), .B0(DmP_EXP_EWSW[17]),
.B1(n1326), .Y(n1104) );
OAI21XLTS U1311 ( .A0(n1594), .A1(n1178), .B0(n1104), .Y(n624) );
AOI22X1TS U1312 ( .A0(intDX_EWSW[20]), .A1(n1126), .B0(DmP_EXP_EWSW[20]),
.B1(n1326), .Y(n1105) );
OAI21XLTS U1313 ( .A0(n1582), .A1(n1178), .B0(n1105), .Y(n618) );
INVX4TS U1314 ( .A(n1098), .Y(n1178) );
AOI22X1TS U1315 ( .A0(intDX_EWSW[6]), .A1(n1126), .B0(DmP_EXP_EWSW[6]), .B1(
n1326), .Y(n1106) );
OAI21XLTS U1316 ( .A0(n1574), .A1(n1178), .B0(n1106), .Y(n646) );
AOI22X1TS U1317 ( .A0(intDX_EWSW[4]), .A1(n1138), .B0(DmP_EXP_EWSW[4]), .B1(
n1089), .Y(n1107) );
OAI21XLTS U1318 ( .A0(n1579), .A1(n1392), .B0(n1107), .Y(n650) );
AOI22X1TS U1319 ( .A0(intDX_EWSW[3]), .A1(n1138), .B0(DmP_EXP_EWSW[3]), .B1(
n1186), .Y(n1108) );
OAI21XLTS U1320 ( .A0(n1650), .A1(n1178), .B0(n1108), .Y(n652) );
AOI22X1TS U1321 ( .A0(intDX_EWSW[12]), .A1(n1126), .B0(DmP_EXP_EWSW[12]),
.B1(n1089), .Y(n1109) );
OAI21XLTS U1322 ( .A0(n1580), .A1(n1178), .B0(n1109), .Y(n634) );
AOI22X1TS U1323 ( .A0(intDY_EWSW[29]), .A1(n1138), .B0(DMP_EXP_EWSW[29]),
.B1(n1186), .Y(n1110) );
OAI21XLTS U1324 ( .A0(n1585), .A1(n1392), .B0(n1110), .Y(n772) );
AOI22X1TS U1325 ( .A0(intDX_EWSW[14]), .A1(n1126), .B0(DmP_EXP_EWSW[14]),
.B1(n1186), .Y(n1111) );
OAI21XLTS U1326 ( .A0(n1581), .A1(n1392), .B0(n1111), .Y(n630) );
AOI22X1TS U1327 ( .A0(intDX_EWSW[1]), .A1(n1138), .B0(DmP_EXP_EWSW[1]), .B1(
n1326), .Y(n1112) );
OAI21XLTS U1328 ( .A0(n1595), .A1(n1178), .B0(n1112), .Y(n656) );
AOI22X1TS U1329 ( .A0(DmP_EXP_EWSW[27]), .A1(n1326), .B0(intDX_EWSW[27]),
.B1(n1138), .Y(n1113) );
OAI21XLTS U1330 ( .A0(n1583), .A1(n1392), .B0(n1113), .Y(n608) );
AOI22X1TS U1331 ( .A0(n959), .A1(n1138), .B0(DmP_EXP_EWSW[2]), .B1(n1326),
.Y(n1114) );
AOI22X1TS U1332 ( .A0(intDX_EWSW[9]), .A1(n1126), .B0(DmP_EXP_EWSW[9]), .B1(
n1186), .Y(n1115) );
AOI22X1TS U1333 ( .A0(intDX_EWSW[5]), .A1(n1126), .B0(DmP_EXP_EWSW[5]), .B1(
n1186), .Y(n1116) );
OAI21XLTS U1334 ( .A0(n1539), .A1(n1178), .B0(n1116), .Y(n648) );
AOI22X1TS U1335 ( .A0(intDX_EWSW[8]), .A1(n1126), .B0(DmP_EXP_EWSW[8]), .B1(
n1089), .Y(n1117) );
OAI21XLTS U1336 ( .A0(n1596), .A1(n1392), .B0(n1117), .Y(n642) );
AOI22X1TS U1337 ( .A0(intDX_EWSW[13]), .A1(n1126), .B0(DmP_EXP_EWSW[13]),
.B1(n1326), .Y(n1118) );
OAI21XLTS U1338 ( .A0(n1576), .A1(n1178), .B0(n1118), .Y(n632) );
AOI22X1TS U1339 ( .A0(intDY_EWSW[30]), .A1(n1138), .B0(DMP_EXP_EWSW[30]),
.B1(n1186), .Y(n1119) );
AOI22X1TS U1340 ( .A0(intDX_EWSW[15]), .A1(n1126), .B0(DmP_EXP_EWSW[15]),
.B1(n1326), .Y(n1120) );
OAI21XLTS U1341 ( .A0(n1652), .A1(n1392), .B0(n1120), .Y(n628) );
AOI22X1TS U1342 ( .A0(intDX_EWSW[0]), .A1(n1138), .B0(DmP_EXP_EWSW[0]), .B1(
n1186), .Y(n1121) );
OAI21XLTS U1343 ( .A0(n1593), .A1(n1178), .B0(n1121), .Y(n658) );
AOI22X1TS U1344 ( .A0(intDX_EWSW[16]), .A1(n1126), .B0(DmP_EXP_EWSW[16]),
.B1(n1326), .Y(n1122) );
OAI21XLTS U1345 ( .A0(n1540), .A1(n1392), .B0(n1122), .Y(n626) );
AOI22X1TS U1346 ( .A0(intDX_EWSW[7]), .A1(n1138), .B0(DmP_EXP_EWSW[7]), .B1(
n1186), .Y(n1123) );
OAI21XLTS U1347 ( .A0(n1584), .A1(n1178), .B0(n1123), .Y(n644) );
AOI22X1TS U1348 ( .A0(n958), .A1(n1126), .B0(DmP_EXP_EWSW[10]), .B1(n1186),
.Y(n1124) );
OAI21XLTS U1349 ( .A0(n927), .A1(n1178), .B0(n1124), .Y(n638) );
AOI22X1TS U1350 ( .A0(intDX_EWSW[11]), .A1(n1126), .B0(DmP_EXP_EWSW[11]),
.B1(n1326), .Y(n1125) );
OAI21XLTS U1351 ( .A0(n1651), .A1(n1392), .B0(n1125), .Y(n636) );
AOI22X1TS U1352 ( .A0(intDX_EWSW[21]), .A1(n1126), .B0(DmP_EXP_EWSW[21]),
.B1(n1326), .Y(n1127) );
OAI21XLTS U1353 ( .A0(n1577), .A1(n1392), .B0(n1127), .Y(n616) );
AOI22X1TS U1354 ( .A0(intDX_EWSW[0]), .A1(n1098), .B0(DMP_EXP_EWSW[0]), .B1(
n1089), .Y(n1128) );
OAI21XLTS U1355 ( .A0(n1593), .A1(n1394), .B0(n1128), .Y(n801) );
AOI22X1TS U1356 ( .A0(intDX_EWSW[9]), .A1(n1098), .B0(DMP_EXP_EWSW[9]), .B1(
n1089), .Y(n1129) );
OAI21XLTS U1357 ( .A0(n1575), .A1(n1185), .B0(n1129), .Y(n792) );
AOI22X1TS U1358 ( .A0(intDX_EWSW[1]), .A1(n1098), .B0(DMP_EXP_EWSW[1]), .B1(
n1089), .Y(n1130) );
OAI21XLTS U1359 ( .A0(n1595), .A1(n1185), .B0(n1130), .Y(n800) );
AOI22X1TS U1360 ( .A0(n959), .A1(n1098), .B0(DMP_EXP_EWSW[2]), .B1(n1089),
.Y(n1131) );
OAI21XLTS U1361 ( .A0(n1578), .A1(n1185), .B0(n1131), .Y(n799) );
AOI22X1TS U1362 ( .A0(intDX_EWSW[8]), .A1(n1098), .B0(DMP_EXP_EWSW[8]), .B1(
n1089), .Y(n1132) );
OAI21XLTS U1363 ( .A0(n1596), .A1(n1185), .B0(n1132), .Y(n793) );
AOI22X1TS U1364 ( .A0(intDX_EWSW[3]), .A1(n1098), .B0(DMP_EXP_EWSW[3]), .B1(
n1089), .Y(n1133) );
OAI21XLTS U1365 ( .A0(n1650), .A1(n1394), .B0(n1133), .Y(n798) );
BUFX3TS U1366 ( .A(n1098), .Y(n1187) );
AOI22X1TS U1367 ( .A0(intDX_EWSW[16]), .A1(n1187), .B0(DMP_EXP_EWSW[16]),
.B1(n1186), .Y(n1134) );
OAI21XLTS U1368 ( .A0(n1540), .A1(n1185), .B0(n1134), .Y(n785) );
AOI22X1TS U1369 ( .A0(intDX_EWSW[19]), .A1(n1187), .B0(DMP_EXP_EWSW[19]),
.B1(n1186), .Y(n1135) );
OAI21XLTS U1370 ( .A0(n1543), .A1(n1394), .B0(n1135), .Y(n782) );
AOI22X1TS U1371 ( .A0(intDX_EWSW[18]), .A1(n1187), .B0(DMP_EXP_EWSW[18]),
.B1(n1186), .Y(n1136) );
OAI21XLTS U1372 ( .A0(n1599), .A1(n1185), .B0(n1136), .Y(n783) );
AOI22X1TS U1373 ( .A0(n958), .A1(n1187), .B0(DMP_EXP_EWSW[10]), .B1(n1089),
.Y(n1137) );
OAI21XLTS U1374 ( .A0(n927), .A1(n1185), .B0(n1137), .Y(n791) );
AOI222X1TS U1375 ( .A0(n1138), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1089), .C0(intDY_EWSW[23]), .C1(n1187), .Y(n1139) );
INVX2TS U1376 ( .A(n1139), .Y(n612) );
AOI22X1TS U1377 ( .A0(intDX_EWSW[14]), .A1(n1187), .B0(DMP_EXP_EWSW[14]),
.B1(n1089), .Y(n1140) );
OAI21XLTS U1378 ( .A0(n1581), .A1(n1185), .B0(n1140), .Y(n787) );
AOI22X1TS U1379 ( .A0(intDX_EWSW[17]), .A1(n1187), .B0(DMP_EXP_EWSW[17]),
.B1(n1186), .Y(n1141) );
OAI21XLTS U1380 ( .A0(n1594), .A1(n1185), .B0(n1141), .Y(n784) );
AOI22X1TS U1381 ( .A0(intDX_EWSW[12]), .A1(n1187), .B0(DMP_EXP_EWSW[12]),
.B1(n1089), .Y(n1142) );
OAI21XLTS U1382 ( .A0(n1580), .A1(n1185), .B0(n1142), .Y(n789) );
OAI22X1TS U1383 ( .A0(n1592), .A1(intDX_EWSW[25]), .B0(n1591), .B1(
intDX_EWSW[26]), .Y(n1143) );
AOI221X1TS U1384 ( .A0(n1592), .A1(intDX_EWSW[25]), .B0(intDX_EWSW[26]),
.B1(n1591), .C0(n1143), .Y(n1149) );
OAI22X1TS U1385 ( .A0(n1583), .A1(intDX_EWSW[27]), .B0(n1598), .B1(
intDY_EWSW[28]), .Y(n1144) );
OAI22X1TS U1386 ( .A0(n1585), .A1(intDY_EWSW[29]), .B0(n1542), .B1(
intDY_EWSW[30]), .Y(n1145) );
AOI221X1TS U1387 ( .A0(n1585), .A1(intDY_EWSW[29]), .B0(intDY_EWSW[30]),
.B1(n1542), .C0(n1145), .Y(n1147) );
AOI2BB2XLTS U1388 ( .B0(intDX_EWSW[7]), .B1(n1584), .A0N(n1584), .A1N(
intDX_EWSW[7]), .Y(n1146) );
NAND4XLTS U1389 ( .A(n1149), .B(n1148), .C(n1147), .D(n1146), .Y(n1177) );
OAI22X1TS U1390 ( .A0(n1595), .A1(intDX_EWSW[1]), .B0(n1594), .B1(
intDX_EWSW[17]), .Y(n1150) );
OAI22X1TS U1391 ( .A0(n1582), .A1(intDX_EWSW[20]), .B0(n1577), .B1(
intDX_EWSW[21]), .Y(n1152) );
OAI22X1TS U1392 ( .A0(n1541), .A1(intDX_EWSW[22]), .B0(n1586), .B1(
intDX_EWSW[23]), .Y(n1153) );
NAND4XLTS U1393 ( .A(n1157), .B(n1156), .C(n1155), .D(n1154), .Y(n1176) );
OAI22X1TS U1394 ( .A0(n1527), .A1(intDX_EWSW[24]), .B0(n1575), .B1(
intDX_EWSW[9]), .Y(n1158) );
AOI221X1TS U1395 ( .A0(n1527), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1575), .C0(n1158), .Y(n1165) );
OAI22X1TS U1396 ( .A0(n1580), .A1(intDX_EWSW[12]), .B0(n1576), .B1(
intDX_EWSW[13]), .Y(n1160) );
OAI22X1TS U1397 ( .A0(n1581), .A1(intDX_EWSW[14]), .B0(n1652), .B1(
intDX_EWSW[15]), .Y(n1161) );
NAND4XLTS U1398 ( .A(n1165), .B(n1164), .C(n1163), .D(n1162), .Y(n1175) );
OAI22X1TS U1399 ( .A0(n1540), .A1(intDX_EWSW[16]), .B0(n1593), .B1(
intDX_EWSW[0]), .Y(n1166) );
AOI221X1TS U1400 ( .A0(n1540), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1593), .C0(n1166), .Y(n1173) );
OAI22X1TS U1401 ( .A0(n1578), .A1(n959), .B0(n1650), .B1(intDX_EWSW[3]), .Y(
n1167) );
OAI22X1TS U1402 ( .A0(n1579), .A1(intDX_EWSW[4]), .B0(n1539), .B1(
intDX_EWSW[5]), .Y(n1168) );
AOI221X1TS U1403 ( .A0(n1579), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1539), .C0(n1168), .Y(n1171) );
OAI22X1TS U1404 ( .A0(n1596), .A1(intDX_EWSW[8]), .B0(n1574), .B1(
intDX_EWSW[6]), .Y(n1169) );
AOI221X1TS U1405 ( .A0(n1596), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1574), .C0(n1169), .Y(n1170) );
NAND4XLTS U1406 ( .A(n1173), .B(n1172), .C(n1171), .D(n1170), .Y(n1174) );
NOR4X1TS U1407 ( .A(n1177), .B(n1176), .C(n1175), .D(n1174), .Y(n1388) );
CLKXOR2X2TS U1408 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1386) );
INVX2TS U1409 ( .A(n1386), .Y(n1181) );
AOI22X1TS U1410 ( .A0(intDX_EWSW[31]), .A1(n1179), .B0(SIGN_FLAG_EXP), .B1(
n1326), .Y(n1180) );
AOI22X1TS U1411 ( .A0(intDX_EWSW[11]), .A1(n1187), .B0(DMP_EXP_EWSW[11]),
.B1(n1186), .Y(n1182) );
OAI21XLTS U1412 ( .A0(n1651), .A1(n1185), .B0(n1182), .Y(n790) );
AOI22X1TS U1413 ( .A0(intDX_EWSW[15]), .A1(n1187), .B0(DMP_EXP_EWSW[15]),
.B1(n1089), .Y(n1183) );
OAI21XLTS U1414 ( .A0(n1652), .A1(n1185), .B0(n1183), .Y(n786) );
AOI22X1TS U1415 ( .A0(intDX_EWSW[13]), .A1(n1187), .B0(DMP_EXP_EWSW[13]),
.B1(n1089), .Y(n1184) );
AOI22X1TS U1416 ( .A0(intDX_EWSW[21]), .A1(n1187), .B0(DMP_EXP_EWSW[21]),
.B1(n1186), .Y(n1188) );
OAI21XLTS U1417 ( .A0(n1577), .A1(n1394), .B0(n1188), .Y(n780) );
AOI2BB2XLTS U1418 ( .B0(beg_OP), .B1(n1538), .A0N(n1538), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1189) );
NAND3XLTS U1419 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1538), .C(
n1570), .Y(n1323) );
OAI21XLTS U1420 ( .A0(n1325), .A1(n1189), .B0(n1323), .Y(n918) );
NOR2XLTS U1421 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1191)
);
NAND2BXLTS U1422 ( .AN(n1210), .B(Raw_mant_NRM_SWR[5]), .Y(n1313) );
OAI21XLTS U1423 ( .A0(n1191), .A1(n1190), .B0(n1313), .Y(n1192) );
AOI211X1TS U1424 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1203), .B0(n1193), .C0(
n1192), .Y(n1195) );
NOR3X1TS U1425 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .C(n1312),
.Y(n1194) );
NAND2X1TS U1426 ( .A(n1194), .B(n956), .Y(n1206) );
NAND2X1TS U1427 ( .A(Raw_mant_NRM_SWR[1]), .B(n1194), .Y(n1305) );
AOI31X1TS U1428 ( .A0(n1195), .A1(n1206), .A2(n1305), .B0(n920), .Y(n1300)
);
OAI21XLTS U1429 ( .A0(n1366), .A1(n1536), .B0(n1196), .Y(n815) );
BUFX4TS U1430 ( .A(OP_FLAG_SFG), .Y(n1427) );
AOI2BB2X1TS U1431 ( .B0(DmP_mant_SFG_SWR[10]), .B1(n1427), .A0N(n1427),
.A1N(DmP_mant_SFG_SWR[10]), .Y(intadd_43_B_2_) );
AOI32X1TS U1432 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1521), .A2(n1525), .B0(
Raw_mant_NRM_SWR[22]), .B1(n1521), .Y(n1197) );
AOI32X1TS U1433 ( .A0(n1530), .A1(n1198), .A2(n1197), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1198), .Y(n1199) );
AOI31XLTS U1434 ( .A0(n1200), .A1(Raw_mant_NRM_SWR[16]), .A2(n1526), .B0(
n1199), .Y(n1209) );
OAI21XLTS U1435 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1552), .B0(n1532), .Y(n1202) );
AOI21X1TS U1436 ( .A0(n1203), .A1(n1202), .B0(n1201), .Y(n1205) );
NAND2X1TS U1437 ( .A(Raw_mant_NRM_SWR[12]), .B(n1204), .Y(n1306) );
OAI211X1TS U1438 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1206), .B0(n1205), .C0(
n1306), .Y(n1316) );
OAI211X1TS U1439 ( .A0(n1555), .A1(n1210), .B0(n1209), .C0(n1208), .Y(n1217)
);
NOR2BX1TS U1440 ( .AN(Shift_amount_SHT1_EWR[0]), .B(Shift_reg_FLAGS_7[1]),
.Y(n1238) );
AOI21X1TS U1441 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n920), .B0(n1213), .Y(
n1215) );
NOR2X2TS U1442 ( .A(n1212), .B(n1215), .Y(n1360) );
NAND2X1TS U1443 ( .A(n1215), .B(n1366), .Y(n1216) );
INVX2TS U1444 ( .A(n1356), .Y(n1233) );
NAND2X2TS U1445 ( .A(n1217), .B(Shift_reg_FLAGS_7[1]), .Y(n1352) );
INVX2TS U1446 ( .A(n1352), .Y(n1339) );
AOI22X1TS U1447 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1339), .B0(n1349), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1219) );
AOI22X1TS U1448 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n921), .B0(n1350), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1218) );
NAND2X1TS U1449 ( .A(n1219), .B(n1218), .Y(n1252) );
AOI22X1TS U1450 ( .A0(n1212), .A1(Data_array_SWR[3]), .B0(n1233), .B1(n1252),
.Y(n1222) );
BUFX3TS U1451 ( .A(n1220), .Y(n1271) );
NAND2X1TS U1452 ( .A(Raw_mant_NRM_SWR[19]), .B(n1271), .Y(n1221) );
OAI211XLTS U1453 ( .A0(n1279), .A1(n1214), .B0(n1222), .C0(n1221), .Y(n822)
);
AOI22X1TS U1454 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1339), .B0(n1349), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1224) );
AOI22X1TS U1455 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n921), .B0(n1350), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1223) );
NAND2X1TS U1456 ( .A(n1224), .B(n1223), .Y(n1359) );
AOI22X1TS U1457 ( .A0(n1212), .A1(Data_array_SWR[2]), .B0(n1233), .B1(n1359),
.Y(n1226) );
NAND2X1TS U1458 ( .A(Raw_mant_NRM_SWR[20]), .B(n1271), .Y(n1225) );
OAI211XLTS U1459 ( .A0(n1283), .A1(n1214), .B0(n1226), .C0(n1225), .Y(n821)
);
AOI22X1TS U1460 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1339), .B0(n1349), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1228) );
AOI22X1TS U1461 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n921), .B0(n1350), .B1(n953), .Y(n1227) );
NAND2X1TS U1462 ( .A(n1228), .B(n1227), .Y(n1276) );
AOI22X1TS U1463 ( .A0(n1212), .A1(Data_array_SWR[7]), .B0(n1233), .B1(n1276),
.Y(n1230) );
NAND2X1TS U1464 ( .A(Raw_mant_NRM_SWR[15]), .B(n1271), .Y(n1229) );
OAI211XLTS U1465 ( .A0(n1275), .A1(n1214), .B0(n1230), .C0(n1229), .Y(n826)
);
AOI22X1TS U1466 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1339), .B0(n1349), .B1(
n953), .Y(n1232) );
AOI22X1TS U1467 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n921), .B0(n1350), .B1(n947), .Y(n1231) );
NAND2X1TS U1468 ( .A(n1232), .B(n1231), .Y(n1280) );
AOI22X1TS U1469 ( .A0(n1212), .A1(Data_array_SWR[6]), .B0(n1233), .B1(n1280),
.Y(n1235) );
NAND2X1TS U1470 ( .A(Raw_mant_NRM_SWR[16]), .B(n1271), .Y(n1234) );
OAI211XLTS U1471 ( .A0(n1287), .A1(n1214), .B0(n1235), .C0(n1234), .Y(n825)
);
AOI22X1TS U1472 ( .A0(n1350), .A1(DmP_mant_SHT1_SW[18]), .B0(n1349), .B1(
n948), .Y(n1236) );
OAI21XLTS U1473 ( .A0(n1532), .A1(n1352), .B0(n1236), .Y(n1237) );
AOI21X1TS U1474 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n921), .B0(n1237), .Y(n1344)
);
NAND2X1TS U1475 ( .A(n1239), .B(n1339), .Y(n1286) );
OAI22X1TS U1476 ( .A0(n1258), .A1(n1356), .B0(n1555), .B1(n1286), .Y(n1240)
);
AOI21X1TS U1477 ( .A0(n1212), .A1(Data_array_SWR[17]), .B0(n1240), .Y(n1241)
);
OAI21XLTS U1478 ( .A0(n1344), .A1(n1214), .B0(n1241), .Y(n837) );
AOI22X1TS U1479 ( .A0(n1212), .A1(Data_array_SWR[14]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1271), .Y(n1243) );
AOI2BB2XLTS U1480 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n1358), .A0N(n1251), .A1N(
n1214), .Y(n1242) );
OAI211XLTS U1481 ( .A0(n1244), .A1(n1356), .B0(n1243), .C0(n1242), .Y(n834)
);
AOI22X1TS U1482 ( .A0(n1212), .A1(Data_array_SWR[12]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1271), .Y(n1246) );
AOI2BB2XLTS U1483 ( .B0(Raw_mant_NRM_SWR[11]), .B1(n1358), .A0N(n1244),
.A1N(n1214), .Y(n1245) );
AOI22X1TS U1484 ( .A0(n1212), .A1(Data_array_SWR[20]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n1271), .Y(n1248) );
AOI2BB2XLTS U1485 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n1358), .A0N(n1261), .A1N(
n1214), .Y(n1247) );
OAI211XLTS U1486 ( .A0(n1264), .A1(n1356), .B0(n1248), .C0(n1247), .Y(n840)
);
AOI22X1TS U1487 ( .A0(n1212), .A1(Data_array_SWR[16]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1271), .Y(n1250) );
AOI2BB2XLTS U1488 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n1358), .A0N(n1267), .A1N(
n1214), .Y(n1249) );
OAI211XLTS U1489 ( .A0(n1251), .A1(n1356), .B0(n1250), .C0(n1249), .Y(n836)
);
AOI22X1TS U1490 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n921), .B0(n1349), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1255) );
AOI22X1TS U1491 ( .A0(n1212), .A1(Data_array_SWR[1]), .B0(
Raw_mant_NRM_SWR[23]), .B1(n1358), .Y(n1254) );
NAND2X1TS U1492 ( .A(n1360), .B(n1252), .Y(n1253) );
OAI211XLTS U1493 ( .A0(n1255), .A1(n1356), .B0(n1254), .C0(n1253), .Y(n820)
);
AOI22X1TS U1494 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1339), .B0(n1349), .B1(n949), .Y(n1256) );
OAI21XLTS U1495 ( .A0(n1563), .A1(n1341), .B0(n1256), .Y(n1257) );
AOI21X1TS U1496 ( .A0(n1350), .A1(DmP_mant_SHT1_SW[14]), .B0(n1257), .Y(
n1348) );
OAI2BB2XLTS U1497 ( .B0(n1258), .B1(n1214), .A0N(Raw_mant_NRM_SWR[6]), .A1N(
n1271), .Y(n1259) );
AOI21X1TS U1498 ( .A0(n1212), .A1(Data_array_SWR[15]), .B0(n1259), .Y(n1260)
);
OAI21XLTS U1499 ( .A0(n1348), .A1(n1356), .B0(n1260), .Y(n835) );
AOI21X1TS U1500 ( .A0(n921), .A1(n956), .B0(n1350), .Y(n1337) );
OAI22X1TS U1501 ( .A0(n1261), .A1(n1356), .B0(n1366), .B1(n1604), .Y(n1262)
);
AOI21X1TS U1502 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1358), .B0(n1262), .Y(n1263) );
OAI21XLTS U1503 ( .A0(n1337), .A1(n1214), .B0(n1263), .Y(n842) );
AOI22X1TS U1504 ( .A0(n1212), .A1(Data_array_SWR[18]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1271), .Y(n1266) );
AOI2BB2XLTS U1505 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n1358), .A0N(n1264), .A1N(
n1214), .Y(n1265) );
OAI211XLTS U1506 ( .A0(n1267), .A1(n1356), .B0(n1266), .C0(n1265), .Y(n838)
);
AOI22X1TS U1507 ( .A0(n1212), .A1(n957), .B0(Raw_mant_NRM_SWR[11]), .B1(
n1271), .Y(n1270) );
AOI2BB2XLTS U1508 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n1358), .A0N(n1268),
.A1N(n1214), .Y(n1269) );
OAI211XLTS U1509 ( .A0(n1272), .A1(n1356), .B0(n1270), .C0(n1269), .Y(n830)
);
AOI22X1TS U1510 ( .A0(n1212), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1271), .Y(n1274) );
AOI2BB2XLTS U1511 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1358), .A0N(n1272),
.A1N(n1214), .Y(n1273) );
OAI211XLTS U1512 ( .A0(n1275), .A1(n1356), .B0(n1274), .C0(n1273), .Y(n828)
);
AOI22X1TS U1513 ( .A0(n1212), .A1(Data_array_SWR[5]), .B0(n1360), .B1(n1276),
.Y(n1278) );
NAND2X1TS U1514 ( .A(Raw_mant_NRM_SWR[19]), .B(n1358), .Y(n1277) );
OAI211XLTS U1515 ( .A0(n1279), .A1(n1356), .B0(n1278), .C0(n1277), .Y(n824)
);
AOI22X1TS U1516 ( .A0(n1212), .A1(Data_array_SWR[4]), .B0(n1360), .B1(n1280),
.Y(n1282) );
NAND2X1TS U1517 ( .A(Raw_mant_NRM_SWR[20]), .B(n1358), .Y(n1281) );
OAI211XLTS U1518 ( .A0(n1283), .A1(n1356), .B0(n1282), .C0(n1281), .Y(n823)
);
AOI22X1TS U1519 ( .A0(n1350), .A1(DmP_mant_SHT1_SW[8]), .B0(n1349), .B1(n952), .Y(n1284) );
AOI21X1TS U1520 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n921), .B0(n1285), .Y(n1355) );
OAI22X1TS U1521 ( .A0(n1287), .A1(n1356), .B0(n1528), .B1(n1286), .Y(n1288)
);
AOI21X1TS U1522 ( .A0(n1212), .A1(Data_array_SWR[8]), .B0(n1288), .Y(n1289)
);
OAI21XLTS U1523 ( .A0(n1355), .A1(n1214), .B0(n1289), .Y(n827) );
AOI2BB2X1TS U1524 ( .B0(DmP_mant_SFG_SWR[2]), .B1(n1427), .A0N(n1427), .A1N(
DmP_mant_SFG_SWR[2]), .Y(n1431) );
NAND2X1TS U1525 ( .A(n1431), .B(DMP_SFG[0]), .Y(n1433) );
INVX2TS U1526 ( .A(n1433), .Y(n1290) );
OAI2BB2XLTS U1527 ( .B0(n1322), .B1(n1291), .A0N(final_result_ieee[30]),
.A1N(n1646), .Y(n802) );
NOR2XLTS U1528 ( .A(n1292), .B(SIGN_FLAG_SHT1SHT2), .Y(n1293) );
OAI2BB2XLTS U1529 ( .B0(n1293), .B1(n1322), .A0N(n1646), .A1N(
final_result_ieee[31]), .Y(n591) );
AOI22X1TS U1530 ( .A0(DmP_mant_SFG_SWR[8]), .A1(n1427), .B0(n960), .B1(n964),
.Y(intadd_43_CI) );
INVX2TS U1531 ( .A(intadd_43_B_2_), .Y(n1296) );
AO22XLTS U1532 ( .A0(DMP_SFG[7]), .A1(intadd_43_B_1_), .B0(intadd_43_CI),
.B1(n955), .Y(n1294) );
OAI21X1TS U1533 ( .A0(DMP_SFG[7]), .A1(intadd_43_B_1_), .B0(n1294), .Y(n1295) );
AOI222X1TS U1534 ( .A0(n1551), .A1(n1296), .B0(n1551), .B1(n1295), .C0(n1296), .C1(n1295), .Y(n1297) );
INVX2TS U1535 ( .A(n1298), .Y(n1299) );
NAND2X1TS U1536 ( .A(n1558), .B(n1299), .Y(DP_OP_15J36_125_2314_n8) );
MX2X1TS U1537 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n659) );
MX2X1TS U1538 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n664) );
MX2X1TS U1539 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n669) );
MX2X1TS U1540 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n674) );
MX2X1TS U1541 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n679) );
MX2X1TS U1542 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n684) );
MX2X1TS U1543 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n689) );
MX2X1TS U1544 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n694) );
AO21XLTS U1545 ( .A0(LZD_output_NRM2_EW[4]), .A1(n920), .B0(n1300), .Y(n574)
);
OAI211X1TS U1546 ( .A0(Raw_mant_NRM_SWR[11]), .A1(Raw_mant_NRM_SWR[13]),
.B0(n1301), .C0(n1523), .Y(n1309) );
OAI2BB1X1TS U1547 ( .A0N(n1303), .A1N(n1523), .B0(n1302), .Y(n1304) );
NAND4XLTS U1548 ( .A(n1306), .B(n1309), .C(n1305), .D(n1304), .Y(n1307) );
OAI21X1TS U1549 ( .A0(n1308), .A1(n1307), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1367) );
OAI2BB1X1TS U1550 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n920), .B0(n1367), .Y(
n560) );
OAI21XLTS U1551 ( .A0(n1311), .A1(n1310), .B0(n1309), .Y(n1317) );
OAI22X1TS U1552 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1313), .B0(n1312), .B1(
n1597), .Y(n1315) );
OAI31X1TS U1553 ( .A0(n1317), .A1(n1316), .A2(n1315), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1363) );
OAI2BB1X1TS U1554 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n920), .B0(n1363), .Y(
n571) );
OAI2BB1X1TS U1555 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n920), .B0(n1352), .Y(
n566) );
NAND2X2TS U1556 ( .A(n1395), .B(Shift_reg_FLAGS_7[0]), .Y(n1321) );
OA22X1TS U1557 ( .A0(n1321), .A1(n1318), .B0(final_result_ieee[23]), .B1(
Shift_reg_FLAGS_7[0]), .Y(n809) );
OA22X1TS U1558 ( .A0(n1321), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n808) );
OA22X1TS U1559 ( .A0(n1321), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n807) );
OA22X1TS U1560 ( .A0(n1321), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n806) );
OA22X1TS U1561 ( .A0(n1321), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n805) );
OA22X1TS U1562 ( .A0(n1321), .A1(n1319), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n804) );
OA22X1TS U1563 ( .A0(n1321), .A1(n1320), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n803) );
OA21XLTS U1564 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1322),
.Y(n606) );
INVX2TS U1565 ( .A(n1325), .Y(n1324) );
AOI22X1TS U1566 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1324), .B1(n1538), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1567 ( .A(n1324), .B(n1323), .Y(n919) );
AOI22X1TS U1568 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1325), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1538), .Y(n1329) );
AO22XLTS U1569 ( .A0(n1327), .A1(Shift_reg_FLAGS_7_6), .B0(n1328), .B1(n1329), .Y(n917) );
AOI22X1TS U1570 ( .A0(n1328), .A1(n1326), .B0(n1401), .B1(n1327), .Y(n916)
);
AOI22X1TS U1571 ( .A0(n1328), .A1(n1399), .B0(n1390), .B1(n1327), .Y(n915)
);
AOI22X1TS U1572 ( .A0(n1328), .A1(n1648), .B0(n920), .B1(n1327), .Y(n912) );
AO22XLTS U1573 ( .A0(n1332), .A1(Data_X[0]), .B0(n1334), .B1(intDX_EWSW[0]),
.Y(n910) );
AO22XLTS U1574 ( .A0(n1331), .A1(Data_X[1]), .B0(n1330), .B1(intDX_EWSW[1]),
.Y(n909) );
AO22XLTS U1575 ( .A0(n1331), .A1(Data_X[2]), .B0(n1330), .B1(n959), .Y(n908)
);
AO22XLTS U1576 ( .A0(n1336), .A1(Data_X[3]), .B0(n1330), .B1(intDX_EWSW[3]),
.Y(n907) );
AO22XLTS U1577 ( .A0(n1336), .A1(Data_X[4]), .B0(n1334), .B1(intDX_EWSW[4]),
.Y(n906) );
AO22XLTS U1578 ( .A0(n1331), .A1(Data_X[5]), .B0(n1330), .B1(intDX_EWSW[5]),
.Y(n905) );
AO22XLTS U1579 ( .A0(n1332), .A1(Data_X[6]), .B0(n1330), .B1(intDX_EWSW[6]),
.Y(n904) );
AO22XLTS U1580 ( .A0(n1332), .A1(Data_X[7]), .B0(n1330), .B1(intDX_EWSW[7]),
.Y(n903) );
AO22XLTS U1581 ( .A0(n1336), .A1(Data_X[8]), .B0(n1334), .B1(intDX_EWSW[8]),
.Y(n902) );
AO22XLTS U1582 ( .A0(n1331), .A1(Data_X[9]), .B0(n1330), .B1(intDX_EWSW[9]),
.Y(n901) );
AO22XLTS U1583 ( .A0(n1332), .A1(Data_X[10]), .B0(n1334), .B1(n958), .Y(n900) );
AO22XLTS U1584 ( .A0(n1331), .A1(Data_X[11]), .B0(n1334), .B1(intDX_EWSW[11]), .Y(n899) );
AO22XLTS U1585 ( .A0(n1332), .A1(Data_X[12]), .B0(n1335), .B1(intDX_EWSW[12]), .Y(n898) );
AO22XLTS U1586 ( .A0(n1331), .A1(Data_X[13]), .B0(n1335), .B1(intDX_EWSW[13]), .Y(n897) );
AO22XLTS U1587 ( .A0(n1331), .A1(Data_X[14]), .B0(n1335), .B1(intDX_EWSW[14]), .Y(n896) );
AO22XLTS U1588 ( .A0(n1336), .A1(Data_X[15]), .B0(n1335), .B1(intDX_EWSW[15]), .Y(n895) );
AO22XLTS U1589 ( .A0(n1331), .A1(Data_X[16]), .B0(n1335), .B1(intDX_EWSW[16]), .Y(n894) );
AO22XLTS U1590 ( .A0(n1332), .A1(Data_X[17]), .B0(n1335), .B1(intDX_EWSW[17]), .Y(n893) );
AO22XLTS U1591 ( .A0(n1332), .A1(Data_X[18]), .B0(n1335), .B1(intDX_EWSW[18]), .Y(n892) );
AO22XLTS U1592 ( .A0(n1332), .A1(Data_X[19]), .B0(n1335), .B1(intDX_EWSW[19]), .Y(n891) );
AO22XLTS U1593 ( .A0(n1332), .A1(Data_X[20]), .B0(n1335), .B1(intDX_EWSW[20]), .Y(n890) );
AO22XLTS U1594 ( .A0(n1336), .A1(Data_X[21]), .B0(n1335), .B1(intDX_EWSW[21]), .Y(n889) );
AO22XLTS U1595 ( .A0(n1336), .A1(Data_X[22]), .B0(n1335), .B1(intDX_EWSW[22]), .Y(n888) );
AO22XLTS U1596 ( .A0(n1332), .A1(Data_X[23]), .B0(n1335), .B1(intDX_EWSW[23]), .Y(n887) );
AO22XLTS U1597 ( .A0(n1330), .A1(intDX_EWSW[24]), .B0(n976), .B1(Data_X[24]),
.Y(n886) );
AO22XLTS U1598 ( .A0(n1330), .A1(intDX_EWSW[25]), .B0(n1332), .B1(Data_X[25]), .Y(n885) );
AO22XLTS U1599 ( .A0(n1334), .A1(intDX_EWSW[26]), .B0(n1336), .B1(Data_X[26]), .Y(n884) );
AO22XLTS U1600 ( .A0(n1336), .A1(Data_X[27]), .B0(n1330), .B1(intDX_EWSW[27]), .Y(n883) );
AO22XLTS U1601 ( .A0(n1330), .A1(intDX_EWSW[28]), .B0(n1336), .B1(Data_X[28]), .Y(n882) );
AO22XLTS U1602 ( .A0(n1330), .A1(intDX_EWSW[29]), .B0(n1336), .B1(Data_X[29]), .Y(n881) );
AO22XLTS U1603 ( .A0(n1334), .A1(intDX_EWSW[30]), .B0(n1331), .B1(Data_X[30]), .Y(n880) );
AO22XLTS U1604 ( .A0(n1336), .A1(add_subt), .B0(n1334), .B1(intAS), .Y(n878)
);
AO22XLTS U1605 ( .A0(n1330), .A1(intDY_EWSW[0]), .B0(n1332), .B1(Data_Y[0]),
.Y(n876) );
AO22XLTS U1606 ( .A0(n1330), .A1(intDY_EWSW[1]), .B0(n1331), .B1(Data_Y[1]),
.Y(n875) );
AO22XLTS U1607 ( .A0(n1330), .A1(intDY_EWSW[2]), .B0(n1332), .B1(Data_Y[2]),
.Y(n874) );
AO22XLTS U1608 ( .A0(n1334), .A1(intDY_EWSW[3]), .B0(n1332), .B1(Data_Y[3]),
.Y(n873) );
INVX4TS U1609 ( .A(n976), .Y(n1333) );
AO22XLTS U1610 ( .A0(n1333), .A1(intDY_EWSW[4]), .B0(n1336), .B1(Data_Y[4]),
.Y(n872) );
AO22XLTS U1611 ( .A0(n1333), .A1(intDY_EWSW[5]), .B0(n1331), .B1(Data_Y[5]),
.Y(n871) );
AO22XLTS U1612 ( .A0(n1334), .A1(intDY_EWSW[6]), .B0(n1332), .B1(Data_Y[6]),
.Y(n870) );
AO22XLTS U1613 ( .A0(n1330), .A1(intDY_EWSW[7]), .B0(n976), .B1(Data_Y[7]),
.Y(n869) );
AO22XLTS U1614 ( .A0(n1333), .A1(intDY_EWSW[8]), .B0(n1331), .B1(Data_Y[8]),
.Y(n868) );
AO22XLTS U1615 ( .A0(n1330), .A1(intDY_EWSW[9]), .B0(n1331), .B1(Data_Y[9]),
.Y(n867) );
AO22XLTS U1616 ( .A0(n1334), .A1(intDY_EWSW[10]), .B0(n976), .B1(Data_Y[10]),
.Y(n866) );
AO22XLTS U1617 ( .A0(n1330), .A1(intDY_EWSW[11]), .B0(n1331), .B1(Data_Y[11]), .Y(n865) );
AO22XLTS U1618 ( .A0(n1333), .A1(intDY_EWSW[12]), .B0(n1332), .B1(Data_Y[12]), .Y(n864) );
AO22XLTS U1619 ( .A0(n1333), .A1(intDY_EWSW[13]), .B0(n1331), .B1(Data_Y[13]), .Y(n863) );
AO22XLTS U1620 ( .A0(n1333), .A1(intDY_EWSW[14]), .B0(n1336), .B1(Data_Y[14]), .Y(n862) );
AO22XLTS U1621 ( .A0(n1330), .A1(intDY_EWSW[15]), .B0(n1332), .B1(Data_Y[15]), .Y(n861) );
AO22XLTS U1622 ( .A0(n1333), .A1(intDY_EWSW[16]), .B0(n976), .B1(Data_Y[16]),
.Y(n860) );
AO22XLTS U1623 ( .A0(n1333), .A1(intDY_EWSW[17]), .B0(n1332), .B1(Data_Y[17]), .Y(n859) );
AO22XLTS U1624 ( .A0(n1333), .A1(intDY_EWSW[18]), .B0(n1336), .B1(Data_Y[18]), .Y(n858) );
AO22XLTS U1625 ( .A0(n1333), .A1(intDY_EWSW[19]), .B0(n976), .B1(Data_Y[19]),
.Y(n857) );
AO22XLTS U1626 ( .A0(n1333), .A1(intDY_EWSW[20]), .B0(n1332), .B1(Data_Y[20]), .Y(n856) );
AO22XLTS U1627 ( .A0(n1333), .A1(intDY_EWSW[21]), .B0(n1336), .B1(Data_Y[21]), .Y(n855) );
AO22XLTS U1628 ( .A0(n1333), .A1(intDY_EWSW[22]), .B0(n1331), .B1(Data_Y[22]), .Y(n854) );
AO22XLTS U1629 ( .A0(n1333), .A1(intDY_EWSW[23]), .B0(n1332), .B1(Data_Y[23]), .Y(n853) );
AO22XLTS U1630 ( .A0(n1333), .A1(intDY_EWSW[24]), .B0(n1336), .B1(Data_Y[24]), .Y(n852) );
AO22XLTS U1631 ( .A0(n1333), .A1(intDY_EWSW[25]), .B0(n1336), .B1(Data_Y[25]), .Y(n851) );
AO22XLTS U1632 ( .A0(n1333), .A1(intDY_EWSW[26]), .B0(n1331), .B1(Data_Y[26]), .Y(n850) );
AO22XLTS U1633 ( .A0(n1333), .A1(intDY_EWSW[27]), .B0(n1332), .B1(Data_Y[27]), .Y(n849) );
AO22XLTS U1634 ( .A0(n1332), .A1(Data_Y[28]), .B0(n1330), .B1(intDY_EWSW[28]), .Y(n848) );
AO22XLTS U1635 ( .A0(n1332), .A1(Data_Y[29]), .B0(n1330), .B1(intDY_EWSW[29]), .Y(n847) );
AO22XLTS U1636 ( .A0(n1331), .A1(Data_Y[30]), .B0(n1330), .B1(intDY_EWSW[30]), .Y(n846) );
AO22XLTS U1637 ( .A0(n1336), .A1(Data_Y[31]), .B0(n1334), .B1(intDY_EWSW[31]), .Y(n845) );
OAI22X1TS U1638 ( .A0(n1337), .A1(n1356), .B0(n1366), .B1(n1537), .Y(n844)
);
AO22XLTS U1639 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n921), .B0(n956), .B1(n1339),
.Y(n1338) );
OAI2BB2XLTS U1640 ( .B0(n1343), .B1(n1356), .A0N(n1212), .A1N(
Data_array_SWR[23]), .Y(n843) );
AOI22X1TS U1641 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1339), .B0(
DmP_mant_SHT1_SW[21]), .B1(n1349), .Y(n1340) );
OAI21XLTS U1642 ( .A0(n1597), .A1(n1341), .B0(n1340), .Y(n1342) );
AOI21X1TS U1643 ( .A0(DmP_mant_SHT1_SW[20]), .A1(n1350), .B0(n1342), .Y(
n1345) );
OAI222X1TS U1644 ( .A0(n1366), .A1(n1603), .B0(n1214), .B1(n1343), .C0(n1356), .C1(n1345), .Y(n841) );
OAI222X1TS U1645 ( .A0(n1619), .A1(n1366), .B0(n1214), .B1(n1345), .C0(n1356), .C1(n1344), .Y(n839) );
AOI22X1TS U1646 ( .A0(n1350), .A1(DmP_mant_SHT1_SW[12]), .B0(n1349), .B1(
n950), .Y(n1346) );
OAI21XLTS U1647 ( .A0(n1553), .A1(n1352), .B0(n1346), .Y(n1347) );
AOI21X1TS U1648 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n921), .B0(n1347), .Y(n1354) );
OAI222X1TS U1649 ( .A0(n1546), .A1(n1366), .B0(n1214), .B1(n1348), .C0(n1356), .C1(n1354), .Y(n833) );
AOI22X1TS U1650 ( .A0(n1350), .A1(DmP_mant_SHT1_SW[10]), .B0(n1349), .B1(
n951), .Y(n1351) );
AOI21X1TS U1651 ( .A0(Raw_mant_NRM_SWR[13]), .A1(n921), .B0(n1353), .Y(n1357) );
OAI222X1TS U1652 ( .A0(n1614), .A1(n1366), .B0(n1214), .B1(n1354), .C0(n1356), .C1(n1357), .Y(n831) );
OAI222X1TS U1653 ( .A0(n1606), .A1(n1366), .B0(n1214), .B1(n1357), .C0(n1356), .C1(n1355), .Y(n829) );
AOI22X1TS U1654 ( .A0(n1212), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1358), .Y(n1362) );
AOI22X1TS U1655 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n921), .B0(n1360), .B1(
n1359), .Y(n1361) );
NAND2X1TS U1656 ( .A(n1362), .B(n1361), .Y(n819) );
AOI32X1TS U1657 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1366), .A2(n920), .B0(
shift_value_SHT2_EWR[2]), .B1(n1212), .Y(n1364) );
NAND2X1TS U1658 ( .A(n1364), .B(n1363), .Y(n818) );
AOI32X1TS U1659 ( .A0(Shift_amount_SHT1_EWR[3]), .A1(n1366), .A2(n920), .B0(
shift_value_SHT2_EWR[3]), .B1(n1212), .Y(n1368) );
NAND2X1TS U1660 ( .A(n1368), .B(n1367), .Y(n817) );
INVX4TS U1661 ( .A(n1391), .Y(n1397) );
AOI21X1TS U1662 ( .A0(DMP_EXP_EWSW[23]), .A1(n973), .B0(n1373), .Y(n1369) );
AOI2BB2XLTS U1663 ( .B0(n1397), .B1(n1369), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1529), .Y(n814) );
NOR2X1TS U1664 ( .A(n1544), .B(DMP_EXP_EWSW[24]), .Y(n1372) );
AOI21X1TS U1665 ( .A0(DMP_EXP_EWSW[24]), .A1(n1544), .B0(n1372), .Y(n1370)
);
XNOR2X1TS U1666 ( .A(n1373), .B(n1370), .Y(n1371) );
AO22XLTS U1667 ( .A0(n1529), .A1(n1371), .B0(n1399), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n813) );
OAI22X1TS U1668 ( .A0(n1373), .A1(n1372), .B0(DmP_EXP_EWSW[24]), .B1(n1545),
.Y(n1376) );
NAND2X1TS U1669 ( .A(DmP_EXP_EWSW[25]), .B(n1605), .Y(n1377) );
XNOR2X1TS U1670 ( .A(n1376), .B(n1374), .Y(n1375) );
AO22XLTS U1671 ( .A0(n1529), .A1(n1375), .B0(n1401), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n812) );
AOI22X1TS U1672 ( .A0(DMP_EXP_EWSW[25]), .A1(n1618), .B0(n1377), .B1(n1376),
.Y(n1380) );
NOR2X1TS U1673 ( .A(n1613), .B(DMP_EXP_EWSW[26]), .Y(n1381) );
AOI21X1TS U1674 ( .A0(DMP_EXP_EWSW[26]), .A1(n1613), .B0(n1381), .Y(n1378)
);
XNOR2X1TS U1675 ( .A(n1380), .B(n1378), .Y(n1379) );
AO22XLTS U1676 ( .A0(n1529), .A1(n1379), .B0(n1391), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n811) );
OAI22X1TS U1677 ( .A0(n1381), .A1(n1380), .B0(DmP_EXP_EWSW[26]), .B1(n1617),
.Y(n1383) );
XNOR2X1TS U1678 ( .A(DmP_EXP_EWSW[27]), .B(n954), .Y(n1382) );
XOR2XLTS U1679 ( .A(n1383), .B(n1382), .Y(n1384) );
AO22XLTS U1680 ( .A0(n1529), .A1(n1384), .B0(n1401), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n810) );
OAI222X1TS U1681 ( .A0(n1178), .A1(n1615), .B0(n1545), .B1(
Shift_reg_FLAGS_7_6), .C0(n1527), .C1(n1394), .Y(n777) );
OAI222X1TS U1682 ( .A0(n1392), .A1(n1547), .B0(n1605), .B1(
Shift_reg_FLAGS_7_6), .C0(n1592), .C1(n1394), .Y(n776) );
OAI222X1TS U1683 ( .A0(n1178), .A1(n1548), .B0(n1617), .B1(
Shift_reg_FLAGS_7_6), .C0(n1591), .C1(n1394), .Y(n775) );
OAI21XLTS U1684 ( .A0(n1386), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1385) );
AOI21X1TS U1685 ( .A0(n1386), .A1(intDX_EWSW[31]), .B0(n1385), .Y(n1387) );
AO21XLTS U1686 ( .A0(OP_FLAG_EXP), .A1(n1089), .B0(n1387), .Y(n770) );
AO22XLTS U1687 ( .A0(n1388), .A1(n1387), .B0(ZERO_FLAG_EXP), .B1(n975), .Y(
n769) );
AO22XLTS U1688 ( .A0(n1529), .A1(DMP_EXP_EWSW[0]), .B0(n1401), .B1(
DMP_SHT1_EWSW[0]), .Y(n767) );
AO22XLTS U1689 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1390), .B1(
DMP_SHT2_EWSW[0]), .Y(n766) );
AO22XLTS U1690 ( .A0(n1529), .A1(DMP_EXP_EWSW[1]), .B0(n1399), .B1(
DMP_SHT1_EWSW[1]), .Y(n764) );
AO22XLTS U1691 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n1390), .B1(
DMP_SHT2_EWSW[1]), .Y(n763) );
INVX4TS U1692 ( .A(n922), .Y(n1514) );
AO22XLTS U1693 ( .A0(n1529), .A1(DMP_EXP_EWSW[2]), .B0(n1391), .B1(
DMP_SHT1_EWSW[2]), .Y(n761) );
AO22XLTS U1694 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1390), .B1(
DMP_SHT2_EWSW[2]), .Y(n760) );
BUFX3TS U1695 ( .A(n922), .Y(n1505) );
AO22XLTS U1696 ( .A0(n1505), .A1(DMP_SFG[2]), .B0(n1514), .B1(
DMP_SHT2_EWSW[2]), .Y(n759) );
AO22XLTS U1697 ( .A0(n1400), .A1(DMP_EXP_EWSW[3]), .B0(n1399), .B1(
DMP_SHT1_EWSW[3]), .Y(n758) );
AO22XLTS U1698 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n1390), .B1(
DMP_SHT2_EWSW[3]), .Y(n757) );
AO22XLTS U1699 ( .A0(n1505), .A1(DMP_SFG[3]), .B0(n1514), .B1(
DMP_SHT2_EWSW[3]), .Y(n756) );
AO22XLTS U1700 ( .A0(n1400), .A1(DMP_EXP_EWSW[4]), .B0(n1401), .B1(
DMP_SHT1_EWSW[4]), .Y(n755) );
AO22XLTS U1701 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1390), .B1(
DMP_SHT2_EWSW[4]), .Y(n754) );
AO22XLTS U1702 ( .A0(n1505), .A1(DMP_SFG[4]), .B0(n1508), .B1(
DMP_SHT2_EWSW[4]), .Y(n753) );
AO22XLTS U1703 ( .A0(n1400), .A1(DMP_EXP_EWSW[5]), .B0(n1399), .B1(
DMP_SHT1_EWSW[5]), .Y(n752) );
AO22XLTS U1704 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1390), .B1(
DMP_SHT2_EWSW[5]), .Y(n751) );
INVX4TS U1705 ( .A(n922), .Y(n1503) );
AO22XLTS U1706 ( .A0(n1400), .A1(DMP_EXP_EWSW[6]), .B0(n1391), .B1(
DMP_SHT1_EWSW[6]), .Y(n749) );
AO22XLTS U1707 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1390), .B1(
DMP_SHT2_EWSW[6]), .Y(n748) );
AO22XLTS U1708 ( .A0(n1400), .A1(DMP_EXP_EWSW[7]), .B0(n1401), .B1(
DMP_SHT1_EWSW[7]), .Y(n746) );
AO22XLTS U1709 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n1390), .B1(
DMP_SHT2_EWSW[7]), .Y(n745) );
AO22XLTS U1710 ( .A0(n1400), .A1(DMP_EXP_EWSW[8]), .B0(n1399), .B1(
DMP_SHT1_EWSW[8]), .Y(n743) );
AO22XLTS U1711 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1390), .B1(
DMP_SHT2_EWSW[8]), .Y(n742) );
AO22XLTS U1712 ( .A0(n1400), .A1(DMP_EXP_EWSW[9]), .B0(n1399), .B1(
DMP_SHT1_EWSW[9]), .Y(n740) );
AO22XLTS U1713 ( .A0(n1403), .A1(DMP_SHT1_EWSW[9]), .B0(n1390), .B1(
DMP_SHT2_EWSW[9]), .Y(n739) );
AO22XLTS U1714 ( .A0(n1400), .A1(DMP_EXP_EWSW[10]), .B0(n1401), .B1(
DMP_SHT1_EWSW[10]), .Y(n737) );
BUFX4TS U1715 ( .A(n1390), .Y(n1398) );
AO22XLTS U1716 ( .A0(n1403), .A1(DMP_SHT1_EWSW[10]), .B0(n1398), .B1(
DMP_SHT2_EWSW[10]), .Y(n736) );
AO22XLTS U1717 ( .A0(n1389), .A1(DMP_SFG[10]), .B0(n1514), .B1(
DMP_SHT2_EWSW[10]), .Y(n735) );
BUFX4TS U1718 ( .A(n1620), .Y(n1401) );
AO22XLTS U1719 ( .A0(n1400), .A1(DMP_EXP_EWSW[11]), .B0(n1620), .B1(
DMP_SHT1_EWSW[11]), .Y(n734) );
AO22XLTS U1720 ( .A0(n1403), .A1(DMP_SHT1_EWSW[11]), .B0(n1398), .B1(
DMP_SHT2_EWSW[11]), .Y(n733) );
BUFX3TS U1721 ( .A(n922), .Y(n1504) );
AO22XLTS U1722 ( .A0(n1504), .A1(DMP_SFG[11]), .B0(n1514), .B1(
DMP_SHT2_EWSW[11]), .Y(n732) );
AO22XLTS U1723 ( .A0(n1400), .A1(DMP_EXP_EWSW[12]), .B0(n1399), .B1(
DMP_SHT1_EWSW[12]), .Y(n731) );
AO22XLTS U1724 ( .A0(n1403), .A1(DMP_SHT1_EWSW[12]), .B0(n1398), .B1(
DMP_SHT2_EWSW[12]), .Y(n730) );
AO22XLTS U1725 ( .A0(n1505), .A1(DMP_SFG[12]), .B0(n1514), .B1(
DMP_SHT2_EWSW[12]), .Y(n729) );
AO22XLTS U1726 ( .A0(n1400), .A1(DMP_EXP_EWSW[13]), .B0(n1401), .B1(
DMP_SHT1_EWSW[13]), .Y(n728) );
AO22XLTS U1727 ( .A0(n1403), .A1(DMP_SHT1_EWSW[13]), .B0(n1398), .B1(
DMP_SHT2_EWSW[13]), .Y(n727) );
AO22XLTS U1728 ( .A0(n1389), .A1(DMP_SFG[13]), .B0(n1514), .B1(
DMP_SHT2_EWSW[13]), .Y(n726) );
AO22XLTS U1729 ( .A0(n1400), .A1(DMP_EXP_EWSW[14]), .B0(n1399), .B1(
DMP_SHT1_EWSW[14]), .Y(n725) );
AO22XLTS U1730 ( .A0(n1403), .A1(DMP_SHT1_EWSW[14]), .B0(n1398), .B1(
DMP_SHT2_EWSW[14]), .Y(n724) );
AO22XLTS U1731 ( .A0(n1505), .A1(DMP_SFG[14]), .B0(n1514), .B1(
DMP_SHT2_EWSW[14]), .Y(n723) );
AO22XLTS U1732 ( .A0(n1400), .A1(DMP_EXP_EWSW[15]), .B0(n1620), .B1(
DMP_SHT1_EWSW[15]), .Y(n722) );
AO22XLTS U1733 ( .A0(n1403), .A1(DMP_SHT1_EWSW[15]), .B0(n1398), .B1(
DMP_SHT2_EWSW[15]), .Y(n721) );
AO22XLTS U1734 ( .A0(n1389), .A1(DMP_SFG[15]), .B0(n1514), .B1(
DMP_SHT2_EWSW[15]), .Y(n720) );
AO22XLTS U1735 ( .A0(n1400), .A1(DMP_EXP_EWSW[16]), .B0(n1399), .B1(
DMP_SHT1_EWSW[16]), .Y(n719) );
AO22XLTS U1736 ( .A0(n1403), .A1(DMP_SHT1_EWSW[16]), .B0(n1398), .B1(
DMP_SHT2_EWSW[16]), .Y(n718) );
INVX4TS U1737 ( .A(n1391), .Y(n1402) );
AO22XLTS U1738 ( .A0(n1402), .A1(DMP_EXP_EWSW[17]), .B0(n1401), .B1(
DMP_SHT1_EWSW[17]), .Y(n716) );
AO22XLTS U1739 ( .A0(n1403), .A1(DMP_SHT1_EWSW[17]), .B0(n1398), .B1(
DMP_SHT2_EWSW[17]), .Y(n715) );
AO22XLTS U1740 ( .A0(n1402), .A1(DMP_EXP_EWSW[18]), .B0(n1399), .B1(
DMP_SHT1_EWSW[18]), .Y(n713) );
AO22XLTS U1741 ( .A0(busy), .A1(DMP_SHT1_EWSW[18]), .B0(n1398), .B1(
DMP_SHT2_EWSW[18]), .Y(n712) );
BUFX4TS U1742 ( .A(n1620), .Y(n1391) );
AO22XLTS U1743 ( .A0(n1402), .A1(DMP_EXP_EWSW[19]), .B0(n1401), .B1(
DMP_SHT1_EWSW[19]), .Y(n710) );
AO22XLTS U1744 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n1398), .B1(
DMP_SHT2_EWSW[19]), .Y(n709) );
AO22XLTS U1745 ( .A0(n1389), .A1(DMP_SFG[19]), .B0(n1514), .B1(
DMP_SHT2_EWSW[19]), .Y(n708) );
AO22XLTS U1746 ( .A0(n1402), .A1(DMP_EXP_EWSW[20]), .B0(n1391), .B1(
DMP_SHT1_EWSW[20]), .Y(n707) );
AO22XLTS U1747 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n1398), .B1(
DMP_SHT2_EWSW[20]), .Y(n706) );
AO22XLTS U1748 ( .A0(n1402), .A1(DMP_EXP_EWSW[21]), .B0(n1401), .B1(
DMP_SHT1_EWSW[21]), .Y(n704) );
AO22XLTS U1749 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n1398), .B1(
DMP_SHT2_EWSW[21]), .Y(n703) );
AO22XLTS U1750 ( .A0(n1402), .A1(DMP_EXP_EWSW[22]), .B0(n1401), .B1(
DMP_SHT1_EWSW[22]), .Y(n701) );
AO22XLTS U1751 ( .A0(n1403), .A1(DMP_SHT1_EWSW[22]), .B0(n1623), .B1(
DMP_SHT2_EWSW[22]), .Y(n700) );
AO22XLTS U1752 ( .A0(n1389), .A1(DMP_SFG[22]), .B0(n1514), .B1(
DMP_SHT2_EWSW[22]), .Y(n699) );
AO22XLTS U1753 ( .A0(n1402), .A1(DMP_EXP_EWSW[23]), .B0(n1399), .B1(
DMP_SHT1_EWSW[23]), .Y(n698) );
AO22XLTS U1754 ( .A0(n1403), .A1(DMP_SHT1_EWSW[23]), .B0(n1390), .B1(
DMP_SHT2_EWSW[23]), .Y(n697) );
AO22XLTS U1755 ( .A0(n1503), .A1(DMP_SHT2_EWSW[23]), .B0(n1505), .B1(
DMP_SFG[23]), .Y(n696) );
AO22XLTS U1756 ( .A0(n1429), .A1(DMP_SFG[23]), .B0(n1442), .B1(
DMP_exp_NRM_EW[0]), .Y(n695) );
AO22XLTS U1757 ( .A0(n1402), .A1(DMP_EXP_EWSW[24]), .B0(n1391), .B1(
DMP_SHT1_EWSW[24]), .Y(n693) );
AO22XLTS U1758 ( .A0(n1403), .A1(DMP_SHT1_EWSW[24]), .B0(n1398), .B1(
DMP_SHT2_EWSW[24]), .Y(n692) );
AO22XLTS U1759 ( .A0(n1503), .A1(DMP_SHT2_EWSW[24]), .B0(n1505), .B1(
DMP_SFG[24]), .Y(n691) );
AO22XLTS U1760 ( .A0(n1429), .A1(DMP_SFG[24]), .B0(n1442), .B1(
DMP_exp_NRM_EW[1]), .Y(n690) );
AO22XLTS U1761 ( .A0(n1402), .A1(DMP_EXP_EWSW[25]), .B0(n1399), .B1(
DMP_SHT1_EWSW[25]), .Y(n688) );
AO22XLTS U1762 ( .A0(n1403), .A1(DMP_SHT1_EWSW[25]), .B0(n1398), .B1(
DMP_SHT2_EWSW[25]), .Y(n687) );
AO22XLTS U1763 ( .A0(n1503), .A1(DMP_SHT2_EWSW[25]), .B0(n1505), .B1(
DMP_SFG[25]), .Y(n686) );
AO22XLTS U1764 ( .A0(n928), .A1(DMP_SFG[25]), .B0(n1442), .B1(
DMP_exp_NRM_EW[2]), .Y(n685) );
AO22XLTS U1765 ( .A0(n1402), .A1(DMP_EXP_EWSW[26]), .B0(n1401), .B1(
DMP_SHT1_EWSW[26]), .Y(n683) );
AO22XLTS U1766 ( .A0(n1403), .A1(DMP_SHT1_EWSW[26]), .B0(n1398), .B1(
DMP_SHT2_EWSW[26]), .Y(n682) );
AO22XLTS U1767 ( .A0(n1503), .A1(DMP_SHT2_EWSW[26]), .B0(n1505), .B1(
DMP_SFG[26]), .Y(n681) );
AO22XLTS U1768 ( .A0(n1429), .A1(DMP_SFG[26]), .B0(n1442), .B1(
DMP_exp_NRM_EW[3]), .Y(n680) );
AO22XLTS U1769 ( .A0(n1402), .A1(n954), .B0(n1399), .B1(DMP_SHT1_EWSW[27]),
.Y(n678) );
AO22XLTS U1770 ( .A0(n1403), .A1(DMP_SHT1_EWSW[27]), .B0(n1398), .B1(
DMP_SHT2_EWSW[27]), .Y(n677) );
AO22XLTS U1771 ( .A0(n1503), .A1(DMP_SHT2_EWSW[27]), .B0(n1504), .B1(
DMP_SFG[27]), .Y(n676) );
AO22XLTS U1772 ( .A0(n1429), .A1(DMP_SFG[27]), .B0(n1442), .B1(
DMP_exp_NRM_EW[4]), .Y(n675) );
AO22XLTS U1773 ( .A0(n1402), .A1(DMP_EXP_EWSW[28]), .B0(n1620), .B1(
DMP_SHT1_EWSW[28]), .Y(n673) );
AO22XLTS U1774 ( .A0(n1403), .A1(DMP_SHT1_EWSW[28]), .B0(n1398), .B1(
DMP_SHT2_EWSW[28]), .Y(n672) );
AO22XLTS U1775 ( .A0(n1503), .A1(DMP_SHT2_EWSW[28]), .B0(n1505), .B1(
DMP_SFG[28]), .Y(n671) );
AO22XLTS U1776 ( .A0(n1429), .A1(DMP_SFG[28]), .B0(n1648), .B1(
DMP_exp_NRM_EW[5]), .Y(n670) );
AO22XLTS U1777 ( .A0(n1402), .A1(DMP_EXP_EWSW[29]), .B0(n1401), .B1(
DMP_SHT1_EWSW[29]), .Y(n668) );
AO22XLTS U1778 ( .A0(n1403), .A1(DMP_SHT1_EWSW[29]), .B0(n1398), .B1(
DMP_SHT2_EWSW[29]), .Y(n667) );
AO22XLTS U1779 ( .A0(n1503), .A1(DMP_SHT2_EWSW[29]), .B0(n922), .B1(
DMP_SFG[29]), .Y(n666) );
AO22XLTS U1780 ( .A0(n928), .A1(DMP_SFG[29]), .B0(n1648), .B1(
DMP_exp_NRM_EW[6]), .Y(n665) );
AO22XLTS U1781 ( .A0(n1397), .A1(DMP_EXP_EWSW[30]), .B0(n1399), .B1(
DMP_SHT1_EWSW[30]), .Y(n663) );
AO22XLTS U1782 ( .A0(n1403), .A1(DMP_SHT1_EWSW[30]), .B0(n1398), .B1(
DMP_SHT2_EWSW[30]), .Y(n662) );
AO22XLTS U1783 ( .A0(n1503), .A1(DMP_SHT2_EWSW[30]), .B0(n1505), .B1(
DMP_SFG[30]), .Y(n661) );
AO22XLTS U1784 ( .A0(n1429), .A1(DMP_SFG[30]), .B0(n1648), .B1(
DMP_exp_NRM_EW[7]), .Y(n660) );
AO22XLTS U1785 ( .A0(n1400), .A1(DmP_EXP_EWSW[14]), .B0(n1391), .B1(
DmP_mant_SHT1_SW[14]), .Y(n629) );
AO22XLTS U1786 ( .A0(n1400), .A1(DmP_EXP_EWSW[16]), .B0(n1391), .B1(
DmP_mant_SHT1_SW[16]), .Y(n625) );
AO22XLTS U1787 ( .A0(n1400), .A1(DmP_EXP_EWSW[19]), .B0(n1620), .B1(n948),
.Y(n619) );
AO22XLTS U1788 ( .A0(n1400), .A1(DmP_EXP_EWSW[22]), .B0(n1401), .B1(
DmP_mant_SHT1_SW[22]), .Y(n613) );
OAI222X1TS U1789 ( .A0(n1394), .A1(n1615), .B0(n1544), .B1(
Shift_reg_FLAGS_7_6), .C0(n1527), .C1(n1392), .Y(n611) );
OAI222X1TS U1790 ( .A0(n1394), .A1(n1547), .B0(n1618), .B1(
Shift_reg_FLAGS_7_6), .C0(n1592), .C1(n1178), .Y(n610) );
OAI222X1TS U1791 ( .A0(n1394), .A1(n1548), .B0(n1613), .B1(
Shift_reg_FLAGS_7_6), .C0(n1591), .C1(n1392), .Y(n609) );
NOR2XLTS U1792 ( .A(n1395), .B(n1646), .Y(n1396) );
AO21XLTS U1793 ( .A0(underflow_flag), .A1(n962), .B0(n1396), .Y(n607) );
AO22XLTS U1794 ( .A0(n1397), .A1(ZERO_FLAG_EXP), .B0(n1391), .B1(
ZERO_FLAG_SHT1), .Y(n605) );
AO22XLTS U1795 ( .A0(n1403), .A1(ZERO_FLAG_SHT1), .B0(n1398), .B1(
ZERO_FLAG_SHT2), .Y(n604) );
AO22XLTS U1796 ( .A0(n1503), .A1(ZERO_FLAG_SHT2), .B0(n1505), .B1(
ZERO_FLAG_SFG), .Y(n603) );
AO22XLTS U1797 ( .A0(n928), .A1(ZERO_FLAG_SFG), .B0(n1442), .B1(
ZERO_FLAG_NRM), .Y(n602) );
AO22XLTS U1798 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n962), .B1(zero_flag), .Y(n600) );
AO22XLTS U1799 ( .A0(n1400), .A1(OP_FLAG_EXP), .B0(n1399), .B1(OP_FLAG_SHT1),
.Y(n599) );
AO22XLTS U1800 ( .A0(n1403), .A1(OP_FLAG_SHT1), .B0(n1623), .B1(OP_FLAG_SHT2), .Y(n598) );
AO22XLTS U1801 ( .A0(n1504), .A1(OP_FLAG_SFG), .B0(n1514), .B1(OP_FLAG_SHT2),
.Y(n597) );
AO22XLTS U1802 ( .A0(n1402), .A1(SIGN_FLAG_EXP), .B0(n1399), .B1(
SIGN_FLAG_SHT1), .Y(n596) );
AO22XLTS U1803 ( .A0(n1403), .A1(SIGN_FLAG_SHT1), .B0(n1623), .B1(
SIGN_FLAG_SHT2), .Y(n595) );
AO22XLTS U1804 ( .A0(n1503), .A1(SIGN_FLAG_SHT2), .B0(n922), .B1(
SIGN_FLAG_SFG), .Y(n594) );
AO22XLTS U1805 ( .A0(n1429), .A1(SIGN_FLAG_SFG), .B0(n1442), .B1(
SIGN_FLAG_NRM), .Y(n593) );
AOI2BB2XLTS U1806 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n960), .A0N(n960), .A1N(
DmP_mant_SFG_SWR[12]), .Y(intadd_41_CI) );
AOI22X1TS U1807 ( .A0(n1444), .A1(intadd_41_SUM_0_), .B0(n1524), .B1(n1442),
.Y(n590) );
AOI2BB2XLTS U1808 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n960), .A0N(n1647), .A1N(
DmP_mant_SFG_SWR[13]), .Y(intadd_41_B_1_) );
AOI2BB2XLTS U1809 ( .B0(n1444), .B1(intadd_41_SUM_1_), .A0N(
Raw_mant_NRM_SWR[13]), .A1N(n1444), .Y(n589) );
AOI2BB2XLTS U1810 ( .B0(DmP_mant_SFG_SWR[14]), .B1(n960), .A0N(n1647), .A1N(
DmP_mant_SFG_SWR[14]), .Y(intadd_41_B_2_) );
AOI22X1TS U1811 ( .A0(n1429), .A1(intadd_41_SUM_2_), .B0(n1523), .B1(n1442),
.Y(n588) );
AOI2BB2XLTS U1812 ( .B0(DmP_mant_SFG_SWR[15]), .B1(n960), .A0N(n960), .A1N(
DmP_mant_SFG_SWR[15]), .Y(intadd_41_B_3_) );
AOI2BB2XLTS U1813 ( .B0(n1444), .B1(intadd_41_SUM_3_), .A0N(
Raw_mant_NRM_SWR[15]), .A1N(n1444), .Y(n587) );
AOI2BB2XLTS U1814 ( .B0(DmP_mant_SFG_SWR[16]), .B1(n960), .A0N(n1647), .A1N(
DmP_mant_SFG_SWR[16]), .Y(intadd_41_B_4_) );
AOI22X1TS U1815 ( .A0(n1429), .A1(intadd_41_SUM_4_), .B0(n1528), .B1(n1442),
.Y(n586) );
AOI22X1TS U1816 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n960), .B0(n1427), .B1(n969), .Y(intadd_41_B_5_) );
AOI22X1TS U1817 ( .A0(n1429), .A1(intadd_41_SUM_5_), .B0(n1526), .B1(n1442),
.Y(n585) );
AOI2BB2XLTS U1818 ( .B0(DmP_mant_SFG_SWR[18]), .B1(n960), .A0N(n960), .A1N(
DmP_mant_SFG_SWR[18]), .Y(intadd_41_B_6_) );
AOI2BB2XLTS U1819 ( .B0(n1444), .B1(intadd_41_SUM_6_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1444), .Y(n584) );
AOI2BB2XLTS U1820 ( .B0(DmP_mant_SFG_SWR[19]), .B1(n960), .A0N(n960), .A1N(
DmP_mant_SFG_SWR[19]), .Y(intadd_41_B_7_) );
AOI2BB2XLTS U1821 ( .B0(n1444), .B1(intadd_41_SUM_7_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1444), .Y(n583) );
AOI22X1TS U1822 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n960), .B0(OP_FLAG_SFG),
.B1(n971), .Y(intadd_41_B_8_) );
AOI2BB2XLTS U1823 ( .B0(n1444), .B1(intadd_41_SUM_8_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1444), .Y(n582) );
AOI22X1TS U1824 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n960), .B0(n1427), .B1(n972), .Y(intadd_41_B_9_) );
AOI22X1TS U1825 ( .A0(n1429), .A1(intadd_41_SUM_9_), .B0(n1525), .B1(n1442),
.Y(n581) );
AOI2BB2XLTS U1826 ( .B0(DmP_mant_SFG_SWR[22]), .B1(n1647), .A0N(n960), .A1N(
DmP_mant_SFG_SWR[22]), .Y(intadd_41_B_10_) );
AOI22X1TS U1827 ( .A0(n1429), .A1(intadd_41_SUM_10_), .B0(n1522), .B1(n1442),
.Y(n580) );
AOI2BB2XLTS U1828 ( .B0(DmP_mant_SFG_SWR[23]), .B1(n960), .A0N(n960), .A1N(
DmP_mant_SFG_SWR[23]), .Y(intadd_41_B_11_) );
AOI22X1TS U1829 ( .A0(n1429), .A1(intadd_41_SUM_11_), .B0(n1521), .B1(n1442),
.Y(n579) );
AOI22X1TS U1830 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1647), .B0(n1427), .B1(
n974), .Y(intadd_41_B_12_) );
AOI22X1TS U1831 ( .A0(n1429), .A1(intadd_41_SUM_12_), .B0(n1530), .B1(n1442),
.Y(n578) );
AOI22X1TS U1832 ( .A0(DmP_mant_SFG_SWR[25]), .A1(OP_FLAG_SFG), .B0(n960),
.B1(n970), .Y(n1404) );
XNOR2X1TS U1833 ( .A(intadd_41_n1), .B(n1404), .Y(n1405) );
AOI22X1TS U1834 ( .A0(n1429), .A1(n1405), .B0(n1549), .B1(n1648), .Y(n577)
);
AOI22X1TS U1835 ( .A0(Data_array_SWR[21]), .A1(n1000), .B0(
Data_array_SWR[17]), .B1(n1001), .Y(n1477) );
AOI22X1TS U1836 ( .A0(Data_array_SWR[13]), .A1(n1494), .B0(n957), .B1(n1518),
.Y(n1406) );
OAI221X1TS U1837 ( .A0(n1517), .A1(n1476), .B0(n1485), .B1(n1477), .C0(n1406), .Y(n1474) );
AOI22X1TS U1838 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n960), .B0(n1427), .B1(n967),
.Y(intadd_42_CI) );
INVX2TS U1839 ( .A(intadd_42_B_2_), .Y(n1409) );
NAND2BXLTS U1840 ( .AN(intadd_42_CI), .B(DMP_SFG[2]), .Y(n1407) );
AOI222X1TS U1841 ( .A0(DMP_SFG[4]), .A1(n1409), .B0(DMP_SFG[4]), .B1(n1408),
.C0(n1409), .C1(n1408), .Y(n1411) );
AOI2BB2X1TS U1842 ( .B0(DmP_mant_SFG_SWR[7]), .B1(OP_FLAG_SFG), .A0N(n1427),
.A1N(DmP_mant_SFG_SWR[7]), .Y(n1410) );
NAND2X1TS U1843 ( .A(n1410), .B(DMP_SFG[5]), .Y(n1439) );
NOR2X1TS U1844 ( .A(n1410), .B(DMP_SFG[5]), .Y(n1440) );
AOI21X1TS U1845 ( .A0(n1411), .A1(n1439), .B0(n1440), .Y(intadd_43_B_0_) );
AOI2BB2XLTS U1846 ( .B0(n1412), .B1(DMP_SFG[9]), .A0N(DMP_SFG[9]), .A1N(
n1412), .Y(n1413) );
XNOR2X1TS U1847 ( .A(intadd_43_n1), .B(n1413), .Y(n1414) );
AOI22X1TS U1848 ( .A0(n1429), .A1(n1414), .B0(n1550), .B1(n1648), .Y(n575)
);
AOI22X1TS U1849 ( .A0(Data_array_SWR[12]), .A1(n999), .B0(Data_array_SWR[9]),
.B1(n1000), .Y(n1416) );
AOI22X1TS U1850 ( .A0(Data_array_SWR[5]), .A1(n1001), .B0(Data_array_SWR[1]),
.B1(n1423), .Y(n1415) );
OAI211X1TS U1851 ( .A0(n1421), .A1(n1536), .B0(n1416), .C0(n1415), .Y(n1496)
);
AOI22X1TS U1852 ( .A0(Data_array_SWR[23]), .A1(n1494), .B0(n1485), .B1(n1496), .Y(n1417) );
AOI22X1TS U1853 ( .A0(n1520), .A1(n1417), .B0(n963), .B1(n1504), .Y(n573) );
AOI22X1TS U1854 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n960), .B0(n1427), .B1(n963),
.Y(n1418) );
AOI2BB2XLTS U1855 ( .B0(n1444), .B1(n1418), .A0N(Raw_mant_NRM_SWR[1]), .A1N(
n1444), .Y(n572) );
AOI22X1TS U1856 ( .A0(Data_array_SWR[11]), .A1(n1001), .B0(
Data_array_SWR[15]), .B1(n1000), .Y(n1420) );
AOI22X1TS U1857 ( .A0(Data_array_SWR[19]), .A1(n999), .B0(Data_array_SWR[23]), .B1(n1460), .Y(n1419) );
NAND2X1TS U1858 ( .A(n1420), .B(n1419), .Y(n1495) );
INVX2TS U1859 ( .A(n1421), .Y(n1493) );
AOI22X1TS U1860 ( .A0(n1520), .A1(n1491), .B0(n964), .B1(n1504), .Y(n570) );
AOI22X1TS U1861 ( .A0(Data_array_SWR[11]), .A1(n999), .B0(Data_array_SWR[8]),
.B1(n1000), .Y(n1425) );
AOI22X1TS U1862 ( .A0(Data_array_SWR[4]), .A1(n1001), .B0(Data_array_SWR[0]),
.B1(n1423), .Y(n1424) );
OAI211X1TS U1863 ( .A0(n1465), .A1(n1536), .B0(n1425), .C0(n1424), .Y(n1516)
);
AOI22X1TS U1864 ( .A0(Data_array_SWR[24]), .A1(n1494), .B0(n1485), .B1(n1516), .Y(n1426) );
AOI22X1TS U1865 ( .A0(n1520), .A1(n1426), .B0(n966), .B1(n922), .Y(n565) );
AOI22X1TS U1866 ( .A0(DmP_mant_SFG_SWR[0]), .A1(n960), .B0(n1427), .B1(n966),
.Y(n1428) );
AOI2BB2XLTS U1867 ( .B0(n1444), .B1(n1428), .A0N(n956), .A1N(n1444), .Y(n564) );
OAI22X1TS U1868 ( .A0(n1517), .A1(n1430), .B0(n1604), .B1(n1488), .Y(n1489)
);
AOI22X1TS U1869 ( .A0(n1429), .A1(n1432), .B0(n1552), .B1(n1648), .Y(n562)
);
XNOR2X1TS U1870 ( .A(DMP_SFG[1]), .B(n1433), .Y(n1435) );
XNOR2X1TS U1871 ( .A(n1435), .B(n1434), .Y(n1436) );
AOI22X1TS U1872 ( .A0(n1429), .A1(n1436), .B0(n1597), .B1(n1648), .Y(n561)
);
AO22XLTS U1873 ( .A0(n1504), .A1(DmP_mant_SFG_SWR[3]), .B0(n1508), .B1(n1437), .Y(n558) );
AOI22X1TS U1874 ( .A0(n1429), .A1(intadd_42_SUM_0_), .B0(n1532), .B1(n1648),
.Y(n557) );
AOI2BB2XLTS U1875 ( .B0(n1444), .B1(intadd_42_SUM_1_), .A0N(
Raw_mant_NRM_SWR[5]), .A1N(n1444), .Y(n556) );
AOI22X1TS U1876 ( .A0(n1429), .A1(intadd_42_SUM_2_), .B0(n1555), .B1(n1648),
.Y(n555) );
NAND2BXLTS U1877 ( .AN(n1440), .B(n1439), .Y(n1441) );
XNOR2X1TS U1878 ( .A(intadd_42_n1), .B(n1441), .Y(n1443) );
AOI22X1TS U1879 ( .A0(n1429), .A1(n1443), .B0(n1531), .B1(n1442), .Y(n554)
);
AO22XLTS U1880 ( .A0(n1504), .A1(DmP_mant_SFG_SWR[6]), .B0(n1508), .B1(n1445), .Y(n553) );
NOR2X2TS U1881 ( .A(shift_value_SHT2_EWR[4]), .B(n1517), .Y(n1492) );
INVX2TS U1882 ( .A(n1492), .Y(n1487) );
OAI222X1TS U1883 ( .A0(n1488), .A1(n1611), .B0(n1487), .B1(n1447), .C0(n1485), .C1(n1446), .Y(n1509) );
AO22XLTS U1884 ( .A0(n1490), .A1(n1509), .B0(final_result_ieee[17]), .B1(
n1646), .Y(n551) );
AOI22X1TS U1885 ( .A0(Data_array_SWR[19]), .A1(n944), .B0(Data_array_SWR[23]), .B1(n945), .Y(n1469) );
AOI22X1TS U1886 ( .A0(Data_array_SWR[11]), .A1(n1000), .B0(Data_array_SWR[8]), .B1(n1001), .Y(n1450) );
NAND2X1TS U1887 ( .A(Data_array_SWR[15]), .B(n999), .Y(n1449) );
OAI211X1TS U1888 ( .A0(n1469), .A1(n1536), .B0(n1450), .C0(n1449), .Y(n1452)
);
AOI22X1TS U1889 ( .A0(n1520), .A1(n1451), .B0(n967), .B1(n922), .Y(n550) );
INVX2TS U1890 ( .A(n1490), .Y(n1497) );
OAI2BB2XLTS U1891 ( .B0(n1451), .B1(n1497), .A0N(final_result_ieee[2]),
.A1N(n1646), .Y(n549) );
OAI2BB2XLTS U1892 ( .B0(n1511), .B1(n1497), .A0N(final_result_ieee[19]),
.A1N(n1646), .Y(n548) );
AOI22X1TS U1893 ( .A0(Data_array_SWR[11]), .A1(n1518), .B0(
Data_array_SWR[12]), .B1(n1494), .Y(n1453) );
OAI221X1TS U1894 ( .A0(n1517), .A1(n1455), .B0(n1485), .B1(n1456), .C0(n1453), .Y(n1498) );
AO22XLTS U1895 ( .A0(n1490), .A1(n1498), .B0(final_result_ieee[10]), .B1(
n1646), .Y(n547) );
AOI22X1TS U1896 ( .A0(Data_array_SWR[11]), .A1(n1494), .B0(
Data_array_SWR[12]), .B1(n1518), .Y(n1454) );
OAI221X1TS U1897 ( .A0(n1517), .A1(n1456), .B0(n1485), .B1(n1455), .C0(n1454), .Y(n1499) );
AO22XLTS U1898 ( .A0(n1490), .A1(n1499), .B0(final_result_ieee[11]), .B1(
n1646), .Y(n546) );
AOI22X1TS U1899 ( .A0(Data_array_SWR[16]), .A1(n1000), .B0(
Data_array_SWR[12]), .B1(n1001), .Y(n1457) );
OAI21XLTS U1900 ( .A0(n1587), .A1(n1458), .B0(n1457), .Y(n1459) );
AOI21X1TS U1901 ( .A0(Data_array_SWR[24]), .A1(n1460), .B0(n1459), .Y(n1464)
);
OAI222X1TS U1902 ( .A0(n1462), .A1(n1616), .B0(n1517), .B1(n1464), .C0(n1461), .C1(n1465), .Y(n1463) );
AO22XLTS U1903 ( .A0(n1504), .A1(DmP_mant_SFG_SWR[9]), .B0(n1508), .B1(n1463), .Y(n545) );
AO22XLTS U1904 ( .A0(n1490), .A1(n1463), .B0(final_result_ieee[7]), .B1(
n1646), .Y(n544) );
OAI222X1TS U1905 ( .A0(n1488), .A1(n1616), .B0(n1487), .B1(n1465), .C0(n1485), .C1(n1464), .Y(n1502) );
AO22XLTS U1906 ( .A0(n1490), .A1(n1502), .B0(final_result_ieee[14]), .B1(
n1646), .Y(n543) );
AOI22X1TS U1907 ( .A0(Data_array_SWR[12]), .A1(n1000), .B0(Data_array_SWR[9]), .B1(n1001), .Y(n1468) );
AOI22X1TS U1908 ( .A0(Data_array_SWR[16]), .A1(n999), .B0(
shift_value_SHT2_EWR[4]), .B1(n1466), .Y(n1467) );
NAND2X1TS U1909 ( .A(n1468), .B(n1467), .Y(n1473) );
INVX2TS U1910 ( .A(n1469), .Y(n1472) );
AOI22X1TS U1911 ( .A0(n1520), .A1(n1471), .B0(n968), .B1(n922), .Y(n542) );
OAI2BB2XLTS U1912 ( .B0(n1471), .B1(n1497), .A0N(final_result_ieee[3]),
.A1N(n1646), .Y(n541) );
OAI2BB2XLTS U1913 ( .B0(n1510), .B1(n1497), .A0N(final_result_ieee[18]),
.A1N(n1646), .Y(n540) );
AO22XLTS U1914 ( .A0(n1490), .A1(n1474), .B0(final_result_ieee[9]), .B1(n962), .Y(n539) );
AOI22X1TS U1915 ( .A0(Data_array_SWR[13]), .A1(n1518), .B0(n957), .B1(n1494),
.Y(n1475) );
OAI221X1TS U1916 ( .A0(n1517), .A1(n1477), .B0(n1485), .B1(n1476), .C0(n1475), .Y(n1500) );
AO22XLTS U1917 ( .A0(n1490), .A1(n1500), .B0(final_result_ieee[12]), .B1(
n962), .Y(n538) );
AOI22X1TS U1918 ( .A0(Data_array_SWR[22]), .A1(n1000), .B0(
Data_array_SWR[18]), .B1(n1001), .Y(n1482) );
AOI22X1TS U1919 ( .A0(Data_array_SWR[10]), .A1(n1518), .B0(
Data_array_SWR[14]), .B1(n1494), .Y(n1478) );
OAI221X1TS U1920 ( .A0(n1517), .A1(n1481), .B0(n1485), .B1(n1482), .C0(n1478), .Y(n1479) );
AO22XLTS U1921 ( .A0(n1504), .A1(DmP_mant_SFG_SWR[10]), .B0(n1508), .B1(
n1479), .Y(n537) );
AO22XLTS U1922 ( .A0(n1490), .A1(n1479), .B0(final_result_ieee[8]), .B1(n962), .Y(n536) );
AOI22X1TS U1923 ( .A0(Data_array_SWR[10]), .A1(n1494), .B0(
Data_array_SWR[14]), .B1(n1518), .Y(n1480) );
OAI221X1TS U1924 ( .A0(n1517), .A1(n1482), .B0(n1485), .B1(n1481), .C0(n1480), .Y(n1501) );
AO22XLTS U1925 ( .A0(n1490), .A1(n1501), .B0(final_result_ieee[13]), .B1(
n962), .Y(n535) );
AO22XLTS U1926 ( .A0(n1504), .A1(DmP_mant_SFG_SWR[7]), .B0(n1508), .B1(n1483), .Y(n534) );
OAI222X1TS U1927 ( .A0(n1488), .A1(n1612), .B0(n1487), .B1(n1486), .C0(n1485), .C1(n1484), .Y(n1507) );
AO22XLTS U1928 ( .A0(n1490), .A1(n1507), .B0(final_result_ieee[16]), .B1(
n962), .Y(n532) );
AO22XLTS U1929 ( .A0(n1490), .A1(n1489), .B0(final_result_ieee[0]), .B1(n962), .Y(n530) );
OAI2BB2XLTS U1930 ( .B0(n1491), .B1(n1497), .A0N(final_result_ieee[6]),
.A1N(n1646), .Y(n529) );
OAI2BB2XLTS U1931 ( .B0(n1506), .B1(n1497), .A0N(final_result_ieee[15]),
.A1N(n1646), .Y(n528) );
AOI22X1TS U1932 ( .A0(Data_array_SWR[23]), .A1(n1518), .B0(n1517), .B1(n1496), .Y(n1515) );
OAI2BB2XLTS U1933 ( .B0(n1515), .B1(n1497), .A0N(final_result_ieee[22]),
.A1N(n1646), .Y(n525) );
AO22XLTS U1934 ( .A0(n1504), .A1(DmP_mant_SFG_SWR[12]), .B0(n1508), .B1(
n1498), .Y(n524) );
AO22XLTS U1935 ( .A0(n1504), .A1(DmP_mant_SFG_SWR[13]), .B0(n1508), .B1(
n1499), .Y(n523) );
AO22XLTS U1936 ( .A0(n1504), .A1(DmP_mant_SFG_SWR[14]), .B0(n1508), .B1(
n1500), .Y(n522) );
AO22XLTS U1937 ( .A0(n922), .A1(DmP_mant_SFG_SWR[15]), .B0(n1503), .B1(n1501), .Y(n521) );
AO22XLTS U1938 ( .A0(n1504), .A1(DmP_mant_SFG_SWR[16]), .B0(n1503), .B1(
n1502), .Y(n520) );
AOI22X1TS U1939 ( .A0(n1520), .A1(n1506), .B0(n1505), .B1(n969), .Y(n519) );
AO22XLTS U1940 ( .A0(n922), .A1(DmP_mant_SFG_SWR[18]), .B0(n1508), .B1(n1507), .Y(n518) );
AO22XLTS U1941 ( .A0(n922), .A1(DmP_mant_SFG_SWR[19]), .B0(n1514), .B1(n1509), .Y(n517) );
AOI22X1TS U1942 ( .A0(n1520), .A1(n1510), .B0(n922), .B1(n971), .Y(n516) );
AOI22X1TS U1943 ( .A0(n1520), .A1(n1511), .B0(n922), .B1(n972), .Y(n515) );
AO22XLTS U1944 ( .A0(n922), .A1(DmP_mant_SFG_SWR[22]), .B0(n1514), .B1(n1512), .Y(n514) );
AO22XLTS U1945 ( .A0(n922), .A1(DmP_mant_SFG_SWR[23]), .B0(n1514), .B1(n1513), .Y(n513) );
AOI22X1TS U1946 ( .A0(n1520), .A1(n1515), .B0(n922), .B1(n974), .Y(n512) );
AOI22X1TS U1947 ( .A0(Data_array_SWR[24]), .A1(n1518), .B0(n1517), .B1(n1516), .Y(n1519) );
AOI22X1TS U1948 ( .A0(n1520), .A1(n1519), .B0(n970), .B1(n922), .Y(n511) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk40.tcl_GDAN16M4P4_syn.sdf");
endmodule
|
module register16(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [15:0] out;
input [15:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 16'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register4(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [3:0] out;
input [3:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 4'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register3(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [2:0] out;
input [2:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 3'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register2(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg [1:0] out;
input [1:0] in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 2'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
module register1(clk, out, in, write, reset); // Negedge-triggered flipflop register with active-low write signal and reset
output reg out;
input in;
input clk, write, reset;
always@(posedge clk) begin
if(reset==0) begin
out = 1'b0;
end
else if(write == 1'b0) begin
out = in;
end
end
endmodule
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module pulse_synchronizer
( input pulse_in_clkA,
input clkA,
output pulse_out_clkB,
input clkB,
input reset_clkA,
input reset_clkB
);
reg ackA;
reg ackB;
reg ackA_synch;
reg ackA_clkB;
reg ackB_synch;
reg ackB_clkA;
reg pulse_in_clkA_d1;
reg ackA_clkB_d1;
reg ackB_d1;
/* detect rising edges in clkA domain, set the ackA signal
* until the pulse is acked from the other domain */
always @(posedge clkA) begin
if(reset_clkA) begin
ackA <= 0;
end
else if(!pulse_in_clkA_d1 & pulse_in_clkA) begin
ackA <= 1;
end
else if(ackB_clkA) begin
ackA <= 0;
end
end // always @ (posedge clkA)
/* detect the rising edge of ackA and set ackB until ackA falls */
always @(posedge clkB) begin
if(reset_clkB) begin
ackB <= 0;
end
else if(!ackA_clkB_d1 & ackA_clkB) begin
ackB <= 1;
end
else if(!ackA_clkB) begin
ackB <= 0;
end
end // always @ (posedge clkB)
/* detect rising edge of ackB and send pulse */
assign pulse_out_clkB = ackB & !ackB_d1;
/* synchronize the ack signals */
always @(posedge clkA) begin
if(reset_clkA) begin
pulse_in_clkA_d1 <= 0;
ackB_synch <= 0;
ackB_clkA <= 0;
end
else begin
pulse_in_clkA_d1 <= pulse_in_clkA;
ackB_synch <= ackB;
ackB_clkA <= ackB_synch;
end
end
/* synchronize the ack signals */
always @(posedge clkB) begin
if(reset_clkB) begin
ackB_d1 <= 0;
ackA_synch <= 0;
ackA_clkB <= 0;
ackA_clkB_d1 <= 0;
end
else begin
ackB_d1 <= ackB;
ackA_synch <= ackA;
ackA_clkB <= ackA_synch;
ackA_clkB_d1 <= ackA_clkB;
end
end
endmodule // pulse_synchronizer
|
`include "bsg_defines.v"
module bsg_8b10b_shift_decoder
( input clk_i
, input data_i
, output logic [7:0] data_o
, output logic k_o
, output logic v_o
, output logic frame_align_o
);
// 8b10b decode running disparity and error signals
wire decode_rd_r, decode_rd_n, decode_rd_lo;
wire decode_data_err_lo;
wire decode_rd_err_lo;
// Signal if a RD- or RD+ comma code has been shifted in
wire comma_code_rdn, comma_code_rdp;
// Signal that indicates that a frame (10b) have arrived
wire frame_recv;
// Input Shift Register
//======================
// We need to use a shift register (rather than a SIPO) becuase we don't have
// reset and we need to detect frame alignments. 8b10b shifts LSB first, so
// don't change the shift direction!
logic [9:0] shift_reg_r;
always_ff @(posedge clk_i)
begin
shift_reg_r[8:0] <= shift_reg_r[9:1];
shift_reg_r[9] <= data_i;
end
// Comma Code Detection and Frame Alignment
//==========================================
// We are using a very simple comma code detection to reduce the amount of
// logic. This means that use of K.28.7 is not allowed. Sending a K.28.7's
// to this channel will likely cause frame misalignment.
assign comma_code_rdn = (shift_reg_r[6:0] == 7'b1111100); // Comma code detect (sender was RD-, now RD+)
assign comma_code_rdp = (shift_reg_r[6:0] == 7'b0000011); // Comma code detect (sender was RD+, now RD-)
assign frame_align_o = (comma_code_rdn | comma_code_rdp);
// Frame Counter
//===============
// Keeps track of where in the 10b frame we are. Resets when a comma code is
// detected to realign the frame.
bsg_counter_overflow_en #( .max_val_p(9), .init_val_p(0) )
frame_counter
( .clk_i ( clk_i )
, .reset_i ( frame_align_o )
, .en_i ( 1'b1 )
, .count_o ()
, .overflow_o( frame_recv )
);
// 8b/10b Decoder
//================
// The 8b10b decoder has a running disparity (RD) which normally starts at
// -1. However on boot, the RD register is unknown and there is no reset.
// Therefore, we use the comma code to determine what our starting disparity
// should be. If the comma code was a RD- encoding, then we set our disparity
// to RD+ and vice-versa. This is because the allowed comma codes (K.28.1 and
// K.28.5) will swap the running disparity.
assign decode_rd_n = frame_align_o ? comma_code_rdn : (v_o ? decode_rd_lo : decode_rd_r);
bsg_dff #(.width_p($bits(decode_rd_r)))
decode_rd_reg
( .clk_i ( clk_i )
, .data_i( decode_rd_n )
, .data_o( decode_rd_r )
);
bsg_8b10b_decode_comb
decode_8b10b
( .data_i ( shift_reg_r )
, .rd_i ( decode_rd_r )
, .data_o ( data_o )
, .k_o ( k_o )
, .rd_o ( decode_rd_lo )
, .data_err_o( decode_data_err_lo )
, .rd_err_o ( decode_rd_err_lo )
);
assign v_o = frame_recv & ~(decode_data_err_lo | decode_rd_err_lo);
// Error Detection
//=================
// Display an error if we ever see a K.28.7 code. This code is not allowed
// with the given comma code detection logic.
// synopsys translate_off
always_ff @(negedge clk_i)
begin
assert (shift_reg_r !== 10'b0001_111100 && shift_reg_r !== 10'b1110_000011) else
$display("## ERROR (%M) - K.28.7 Code Detected!");
end
// synopsys translate_on
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////
//Zachary Karpinski
//Karpentium Processor
//
//alu_with_acc.v
//
//A parameterized alu unit with an internal accumulator register
// select enable function
// ddd 0 Do nothing
// 000 1 Add
// 001 1 Subtract
// 010 Increment by 1
// 011 Decrement by 1
// 100
// 101
// 110 In
// 111 Accumulator
//
///////////////////////////////////
module alu_with_acc(clk,in,out,select,enable);
parameter n = 16; //Bits for Input and Output
parameter m = 3; //Bits for Select Line
input clk, enable;
input [n-1:0] in;
input [m-1:0] select;
output [n-1:0] out;
reg [n-1:0] accumulator;
reg v;//Overflow
initial begin
accumulator <= 16'h00;
v = 0;
end
always @(posedge(clk))
begin
if (enable == 1) begin
case (select)
3'b000 : {v,accumulator} <= accumulator + in; //ADD
3'b001 : {v,accumulator} <= accumulator - ((~in) + 1); //Subtract
3'b010 : {v,accumulator} <= accumulator + 1'b1; //Increment by 1
3'b011 : {v,accumulator} <= accumulator - 1'b1; //Decrement by 1
//3'b100 :
//3'b101 :
3'b110 : accumulator <= in;
3'b111 : accumulator <= accumulator;
endcase
end
end
//Output accumulator value to databus
assign out = select[2] ? accumulator : 16'hZZ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER_20_V
`define SKY130_FD_SC_LP__BUSDRIVER_20_V
/**
* busdriver: Bus driver (pmoshvt devices).
*
* Verilog wrapper for busdriver with size of 20 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__busdriver.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busdriver_20 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__busdriver base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busdriver_20 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__busdriver base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER_20_V
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module aes_128(clk, state, key, out);
input clk;
input [127:0] state, key;
output [127:0] out;
reg [127:0] s0, k0;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9,
k1, k2, k3, k4, k5, k6, k7, k8, k9,
k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b;
always @ (posedge clk)
begin
s0 <= state ^ key;
k0 <= key;
end
expand_key_128
a1 (clk, k0, k1, k0b, 8'h1),
a2 (clk, k1, k2, k1b, 8'h2),
a3 (clk, k2, k3, k2b, 8'h4),
a4 (clk, k3, k4, k3b, 8'h8),
a5 (clk, k4, k5, k4b, 8'h10),
a6 (clk, k5, k6, k5b, 8'h20),
a7 (clk, k6, k7, k6b, 8'h40),
a8 (clk, k7, k8, k7b, 8'h80),
a9 (clk, k8, k9, k8b, 8'h1b),
a10 (clk, k9, , k9b, 8'h36);
one_round
r1 (clk, s0, k0b, s1),
r2 (clk, s1, k1b, s2),
r3 (clk, s2, k2b, s3),
r4 (clk, s3, k3b, s4),
r5 (clk, s4, k4b, s5),
r6 (clk, s5, k5b, s6),
r7 (clk, s6, k6b, s7),
r8 (clk, s7, k7b, s8),
r9 (clk, s8, k8b, s9);
final_round
rf (clk, s9, k9b, out);
endmodule
module expand_key_128(clk, in, out_1, out_2, rcon);
input clk;
input [127:0] in;
input [7:0] rcon;
output reg [127:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3,
v0, v1, v2, v3;
reg [31:0] k0a, k1a, k2a, k3a;
wire [31:0] k0b, k1b, k2b, k3b, k4a;
assign {k0, k1, k2, k3} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
assign v2 = v1 ^ k2;
assign v3 = v2 ^ k3;
always @ (posedge clk) begin
k0a <= v0;
k1a <= v1;
k2a <= v2;
k3a <= v3;
end
S4
S4_0 (clk, {k3[23:0], k3[31:24]}, k4a);
assign k0b = k0a ^ k4a;
assign k1b = k1a ^ k4a;
assign k2b = k2a ^ k4a;
assign k3b = k3a ^ k4a;
always @ (posedge clk)
out_1 <= {k0b, k1b, k2b, k3b};
assign out_2 = {k0b, k1b, k2b, k3b};
endmodule
|
`timescale 1ns/1ns
module quadrature_tb();
// Declare inputs as regs and outputs as wires
reg clk, reset, quadA, quadB;
wire [7:0] count;
quadrature_clocked DUT(
.clk(clk),
.reset(reset),
.quadA(quadA),
.quadB(quadB),
.count(count)
);
/*
module quadrature_clocked(
clk,
quadA,
quadB,
count
);
input clk, quadA, quadB;
output [7:0] count;
*/
// Initialize all variables
initial begin
clk = 1;
reset = 1;
quadA = 1;
quadB = 0;
#2
reset = 0;
# 10
quadA = 1;
quadB = 1;
# 10
quadA = 0;
quadB = 1;
# 10
quadA = 0;
quadB = 0;
# 10
quadA = 1;
quadB = 0;
# 10
quadA = 1;
quadB = 1;
# 10
quadA = 1;
quadB = 0;
# 10
quadA = 0;
quadB = 0;
# 12 // bouncy
quadA = 0;
quadB = 0;
# 12 // bouncy
quadA = 0;
quadB = 0;
# 10
quadA = 0;
quadB = 1;
end
always begin
#1 clk = !clk;
end
endmodule
|
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_external_sdram_controller_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ 42: 0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [ 42: 0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1: 0] entries;
reg [ 42: 0] entry_0;
reg [ 42: 0] entry_1;
wire full;
reg rd_address;
reg [ 42: 0] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_external_sdram_controller (
// inputs:
az_addr,
az_be_n,
az_cs,
az_data,
az_rd_n,
az_wr_n,
clk,
reset_n,
// outputs:
za_data,
za_valid,
za_waitrequest,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dq,
zs_dqm,
zs_ras_n,
zs_we_n
)
;
output [ 15: 0] za_data;
output za_valid;
output za_waitrequest;
output [ 12: 0] zs_addr;
output [ 1: 0] zs_ba;
output zs_cas_n;
output zs_cke;
output zs_cs_n;
inout [ 15: 0] zs_dq;
output [ 1: 0] zs_dqm;
output zs_ras_n;
output zs_we_n;
input [ 23: 0] az_addr;
input [ 1: 0] az_be_n;
input az_cs;
input [ 15: 0] az_data;
input az_rd_n;
input az_wr_n;
input clk;
input reset_n;
wire [ 23: 0] CODE;
reg ack_refresh_request;
reg [ 23: 0] active_addr;
wire [ 1: 0] active_bank;
reg active_cs_n;
reg [ 15: 0] active_data;
reg [ 1: 0] active_dqm;
reg active_rnw;
wire almost_empty;
wire almost_full;
wire bank_match;
wire [ 8: 0] cas_addr;
wire clk_en;
wire [ 3: 0] cmd_all;
wire [ 2: 0] cmd_code;
wire cs_n;
wire csn_decode;
wire csn_match;
wire [ 23: 0] f_addr;
wire [ 1: 0] f_bank;
wire f_cs_n;
wire [ 15: 0] f_data;
wire [ 1: 0] f_dqm;
wire f_empty;
reg f_pop;
wire f_rnw;
wire f_select;
wire [ 42: 0] fifo_read_data;
reg [ 12: 0] i_addr;
reg [ 3: 0] i_cmd;
reg [ 2: 0] i_count;
reg [ 2: 0] i_next;
reg [ 2: 0] i_refs;
reg [ 2: 0] i_state;
reg init_done;
reg [ 12: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 2: 0] m_count;
reg [ 15: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 1: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 8: 0] m_next;
reg [ 8: 0] m_state;
reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
wire pending;
wire rd_strobe;
reg [ 1: 0] rd_valid;
reg [ 14: 0] refresh_counter;
reg refresh_request;
wire rnw_match;
wire row_match;
wire [ 23: 0] txt_code;
reg za_cannotrefresh;
reg [ 15: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
reg za_valid;
wire za_waitrequest;
wire [ 12: 0] zs_addr;
wire [ 1: 0] zs_ba;
wire zs_cas_n;
wire zs_cke;
wire zs_cs_n;
wire [ 15: 0] zs_dq;
wire [ 1: 0] zs_dqm;
wire zs_ras_n;
wire zs_we_n;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
assign zs_addr = m_addr;
assign zs_cke = clk_en;
assign zs_dq = oe?m_data:{16{1'bz}};
assign zs_dqm = m_dqm;
assign zs_ba = m_bank;
assign f_select = f_pop & pending;
assign f_cs_n = 1'b0;
assign cs_n = f_select ? f_cs_n : active_cs_n;
assign csn_decode = cs_n;
assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
wasca_external_sdram_controller_input_efifo_module the_wasca_external_sdram_controller_input_efifo_module
(
.almost_empty (almost_empty),
.almost_full (almost_full),
.clk (clk),
.empty (f_empty),
.full (za_waitrequest),
.rd (f_select),
.rd_data (fifo_read_data),
.reset_n (reset_n),
.wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
.wr_data ({az_wr_n, az_addr, az_wr_n ? 2'b0 : az_be_n, az_data})
);
assign f_bank = {f_addr[23],f_addr[9]};
// Refresh/init counter.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_counter <= 11600;
else if (refresh_counter == 0)
refresh_counter <= 18095;
else
refresh_counter <= refresh_counter - 1'b1;
end
// Refresh request signal.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_request <= 0;
else if (1)
refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
end
// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_cannotrefresh <= 0;
else if (1)
za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
end
// Initialization-done flag.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
init_done <= 0;
else if (1)
init_done <= init_done | (i_state == 3'b101);
end
// **** Init FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
i_state <= 3'b000;
i_next <= 3'b000;
i_cmd <= 4'b1111;
i_addr <= {13{1'b1}};
i_count <= {3{1'b0}};
end
else
begin
i_addr <= {13{1'b1}};
case (i_state) // synthesis parallel_case full_case
3'b000: begin
i_cmd <= 4'b1111;
i_refs <= 3'b0;
//Wait for refresh count-down after reset
if (refresh_counter == 0)
i_state <= 3'b001;
end // 3'b000
3'b001: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h2};
i_count <= 2;
i_next <= 3'b010;
end // 3'b001
3'b010: begin
i_cmd <= {{1{1'b0}},3'h1};
i_refs <= i_refs + 1'b1;
i_state <= 3'b011;
i_count <= 6;
// Count up init_refresh_commands
if (i_refs == 3'h1)
i_next <= 3'b111;
else
i_next <= 3'b010;
end // 3'b010
3'b011: begin
i_cmd <= {{1{1'b0}},3'h7};
//WAIT til safe to Proceed...
if (i_count > 1)
i_count <= i_count - 1'b1;
else
i_state <= i_next;
end // 3'b011
3'b101: begin
i_state <= 3'b101;
end // 3'b101
3'b111: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h0};
i_addr <= {{3{1'b0}},1'b0,2'b00,3'h2,4'h0};
i_count <= 4;
i_next <= 3'b101;
end // 3'b111
default: begin
i_state <= 3'b000;
end // default
endcase // i_state
end
end
assign active_bank = {active_addr[23],active_addr[9]};
assign csn_match = active_cs_n == f_cs_n;
assign rnw_match = active_rnw == f_rnw;
assign bank_match = active_bank == f_bank;
assign row_match = {active_addr[22 : 10]} == {f_addr[22 : 10]};
assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
assign cas_addr = f_select ? { {4{1'b0}},f_addr[8 : 0] } : { {4{1'b0}},active_addr[8 : 0] };
// **** Main FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= 4'b1111;
m_bank <= 2'b00;
m_addr <= 13'b0000000000000;
m_data <= 16'b0000000000000000;
m_dqm <= 2'b00;
m_count <= 3'b000;
ack_refresh_request <= 1'b0;
f_pop <= 1'b0;
oe <= 1'b0;
end
else
begin
f_pop <= 1'b0;
oe <= 1'b0;
case (m_state) // synthesis parallel_case full_case
9'b000000001: begin
//Wait for init-fsm to be done...
if (init_done)
begin
//Hold bus if another cycle ended to arf.
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= 4'b1111;
ack_refresh_request <= 1'b0;
//Wait for a read/write request.
if (refresh_request)
begin
m_state <= 9'b001000000;
m_next <= 9'b010000000;
m_count <= 2;
active_cs_n <= 1'b1;
end
else if (!f_empty)
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= 9'b000000010;
end
end
else
begin
m_addr <= i_addr;
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= i_cmd;
end
end // 9'b000000001
9'b000000010: begin
m_state <= 9'b000000100;
m_cmd <= {csn_decode,3'h3};
m_bank <= active_bank;
m_addr <= active_addr[22 : 10];
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= 3;
m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
end // 9'b000000010
9'b000000100: begin
// precharge all if arf, else precharge csn_decode
if (m_next == 9'b010000000)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
m_state <= m_next;
end // 9'b000000100
9'b000001000: begin
m_cmd <= {csn_decode,3'h5};
m_bank <= f_select ? f_bank : active_bank;
m_dqm <= f_select ? f_dqm : active_dqm;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end RD spin cycle if fifo mt
if (~pending & f_pop)
m_cmd <= {csn_decode,3'h7};
m_state <= 9'b100000000;
end
end // 9'b000001000
9'b000010000: begin
m_cmd <= {csn_decode,3'h4};
oe <= 1'b1;
m_data <= f_select ? f_data : active_data;
m_dqm <= f_select ? f_dqm : active_dqm;
m_bank <= f_select ? f_bank : active_bank;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end WR spin cycle if fifo empty
if (~pending & f_pop)
begin
m_cmd <= {csn_decode,3'h7};
oe <= 1'b0;
end
m_state <= 9'b100000000;
end
end // 9'b000010000
9'b000100000: begin
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
begin
m_state <= 9'b001000000;
m_count <= 2;
end
end // 9'b000100000
9'b001000000: begin
m_state <= 9'b000000100;
m_addr <= {13{1'b1}};
// precharge all if arf, else precharge csn_decode
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h2};
else
m_cmd <= {csn_decode,3'h2};
end // 9'b001000000
9'b010000000: begin
ack_refresh_request <= 1'b1;
m_state <= 9'b000000100;
m_cmd <= {{1{1'b0}},3'h1};
m_count <= 6;
m_next <= 9'b000000001;
end // 9'b010000000
9'b100000000: begin
m_cmd <= {csn_decode,3'h7};
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else //wait for fifo to have contents
if (!f_empty)
//Are we 'pending' yet?
if (csn_match && rnw_match && bank_match && row_match)
begin
m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
else
begin
m_state <= 9'b000100000;
m_next <= 9'b000000001;
m_count <= 1;
end
end // 9'b100000000
// synthesis translate_off
default: begin
m_state <= m_state;
m_cmd <= 4'b1111;
f_pop <= 1'b0;
oe <= 1'b0;
end // default
// synthesis translate_on
endcase // m_state
end
end
assign rd_strobe = m_cmd[2 : 0] == 3'h5;
//Track RD Req's based on cas_latency w/shift reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_valid <= {2{1'b0}};
else
rd_valid <= (rd_valid << 1) | { {1{1'b0}}, rd_strobe };
end
// Register dq data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_data <= 0;
else
za_data <= zs_dq;
end
// Delay za_valid to match registered data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_valid <= 0;
else if (1)
za_valid <= rd_valid[1];
end
assign cmd_code = m_cmd[2 : 0];
assign cmd_all = m_cmd;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
initial
begin
$write("\n");
$write("This reference design requires a vendor simulation model.\n");
$write("To simulate accesses to SDRAM, you must:\n");
$write(" - Download the vendor model\n");
$write(" - Install the model in the system_sim directory\n");
$write(" - `include the vendor model in the the top-level system file,\n");
$write(" - Instantiate sdram simulation models and wire them to testbench signals\n");
$write(" - Be aware that you may have to disable some timing checks in the vendor model\n");
$write(" (because this simulation is zero-delay based)\n");
$write("\n");
end
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4B_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NAND4B_PP_SYMBOL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand4b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4B_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XOR2_1_V
`define SKY130_FD_SC_HD__XOR2_1_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xor2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xor2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR2_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRBP_TB_V
`define SKY130_FD_SC_HS__SDFRBP_TB_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfrbp.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 SCD = 1'b0;
#320 SCE = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SCE = 1'b1;
#440 SCD = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SCE = 1'bx;
#560 SCD = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__sdfrbp dut (.RESET_B(RESET_B), .D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRBP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_TB_V
`define SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_TB_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_pwrgood_pp_p.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VPWR = 1'bX;
#20 UDP_IN = 1'b0;
#40 VPWR = 1'b0;
#60 UDP_IN = 1'b1;
#80 VPWR = 1'b1;
#100 UDP_IN = 1'b0;
#120 VPWR = 1'b0;
#140 VPWR = 1'b1;
#160 UDP_IN = 1'b1;
#180 VPWR = 1'bx;
#200 UDP_IN = 1'bx;
end
sky130_fd_sc_hd__udp_pwrgood_pp$P dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__NAND4_PP_SYMBOL_V
/**
* nand4: 4-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4_PP_SYMBOL_V
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful;
but WITHOUT ANY WARRANTY, without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.1
Date: 15- 4-2016
*/
/*
parameter stg is the stage of the pipelined signal
for instance if signal is xx_VIII, then set stg to 8
*/
module sep32 #(parameter width=10, parameter stg=5'd0)
(
input clk,
input cen,
input [width-1:0] mixed,
input [4:0] cnt,
output reg [width-1:0] slot_00,
output reg [width-1:0] slot_01,
output reg [width-1:0] slot_02,
output reg [width-1:0] slot_03,
output reg [width-1:0] slot_04,
output reg [width-1:0] slot_05,
output reg [width-1:0] slot_06,
output reg [width-1:0] slot_07,
output reg [width-1:0] slot_10,
output reg [width-1:0] slot_11,
output reg [width-1:0] slot_12,
output reg [width-1:0] slot_13,
output reg [width-1:0] slot_14,
output reg [width-1:0] slot_15,
output reg [width-1:0] slot_16,
output reg [width-1:0] slot_17,
output reg [width-1:0] slot_20,
output reg [width-1:0] slot_21,
output reg [width-1:0] slot_22,
output reg [width-1:0] slot_23,
output reg [width-1:0] slot_24,
output reg [width-1:0] slot_25,
output reg [width-1:0] slot_26,
output reg [width-1:0] slot_27,
output reg [width-1:0] slot_30,
output reg [width-1:0] slot_31,
output reg [width-1:0] slot_32,
output reg [width-1:0] slot_33,
output reg [width-1:0] slot_34,
output reg [width-1:0] slot_35,
output reg [width-1:0] slot_36,
output reg [width-1:0] slot_37
);
/*verilator coverage_off*/
reg [4:0] cntadj;
reg [width-1:0] slots[0:31] /*verilator public*/;
localparam pos0 = 33-stg;
/* verilator lint_off WIDTH */
always @(*)
cntadj = (cnt+pos0)%32;
/* verilator lint_on WIDTH */
always @(posedge clk) if(cen) begin
slots[cntadj] <= mixed;
case( cntadj ) // octal numbers!
5'o00: slot_00 <= mixed;
5'o01: slot_01 <= mixed;
5'o02: slot_02 <= mixed;
5'o03: slot_03 <= mixed;
5'o04: slot_04 <= mixed;
5'o05: slot_05 <= mixed;
5'o06: slot_06 <= mixed;
5'o07: slot_07 <= mixed;
5'o10: slot_10 <= mixed;
5'o11: slot_11 <= mixed;
5'o12: slot_12 <= mixed;
5'o13: slot_13 <= mixed;
5'o14: slot_14 <= mixed;
5'o15: slot_15 <= mixed;
5'o16: slot_16 <= mixed;
5'o17: slot_17 <= mixed;
5'o20: slot_20 <= mixed;
5'o21: slot_21 <= mixed;
5'o22: slot_22 <= mixed;
5'o23: slot_23 <= mixed;
5'o24: slot_24 <= mixed;
5'o25: slot_25 <= mixed;
5'o26: slot_26 <= mixed;
5'o27: slot_27 <= mixed;
5'o30: slot_30 <= mixed;
5'o31: slot_31 <= mixed;
5'o32: slot_32 <= mixed;
5'o33: slot_33 <= mixed;
5'o34: slot_34 <= mixed;
5'o35: slot_35 <= mixed;
5'o36: slot_36 <= mixed;
5'o37: slot_37 <= mixed;
endcase
end
/*verilator coverage_on*/
endmodule
|
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 29-10-2018
*/
module jt12_eg_final(
input [ 6:0] lfo_mod,
input amsen,
input [ 1:0] ams,
input [ 6:0] tl,
input [ 9:0] eg_pure_in,
input ssg_inv,
output reg [9:0] eg_limited
);
reg [ 8:0] am_final;
reg [11:0] sum_eg_tl;
reg [11:0] sum_eg_tl_am;
reg [ 5:0] am_inverted;
reg [ 9:0] eg_pream;
always @(*) begin
am_inverted = lfo_mod[6] ? ~lfo_mod[5:0] : lfo_mod[5:0];
end
always @(*) begin
casez( {amsen, ams } )
default: am_final = 9'd0;
3'b1_01: am_final = { 5'd0, am_inverted[5:2] };
3'b1_10: am_final = { 3'd0, am_inverted };
3'b1_11: am_final = { 2'd0, am_inverted, 1'b0 };
endcase
eg_pream = ssg_inv ? (10'h200-eg_pure_in) : eg_pure_in;
sum_eg_tl = { 1'b0, tl, 3'd0 } + {1'b0, eg_pream}; // leading zeros needed to compute correctly
sum_eg_tl_am = sum_eg_tl + { 3'd0, am_final };
end
always @(*)
eg_limited = sum_eg_tl_am[11:10]==2'd0 ? sum_eg_tl_am[9:0] : 10'h3ff;
endmodule // jt12_eg_final |
module InBuff #(parameter WIDTH = 16)(
input clk,
input [WIDTH-1:0] in,
output reg [WIDTH-1:0] out,
input read,
input clkdiv,
output reg outclk,
output toread);
reg [WIDTH-1:0] inbuf [20:0];
reg [6:0] i;
reg [15:0] counter = 0;
reg oldread = 0;
reg [6:0] bufpointer = 0;
assign toread = (bufpointer > 0);
always @(posedge clk) begin
if (counter > clkdiv) begin//@TODO: external clk
outclk <= !outclk;
counter <= 0;
if (in != 0) begin
for(i=1;i<21;i=i+1) begin//probably very slow //WHAT THE FUCK-@TODO: implement cyclic buffer
inbuf[i] <= inbuf[i-1];
end
inbuf[0] <= in;
bufpointer <= bufpointer + 1;
end
end
if (!oldread) begin
if (read) begin
if(bufpointer > 0) begin
out <= inbuf[bufpointer - 1];
bufpointer <= bufpointer - 1;
oldread <= 1;
end
end
end
if (!read) begin
oldread <= 0;
end
end
endmodule
module OutBuff #(parameter WIDTH = 13)(
input clk,
input [WIDTH-1:0] in,
output reg [WIDTH-1:0] out,
input writedone,
input clkdiv,
output reg outclk,
output towrite);
reg [6:0] i;
reg [WIDTH-1:0] outbuf [20:0];
reg [15:0] counter = 0;
reg oldwrite = 0;
reg [6:0] bufpointer = 0;
assign towrite = (bufpointer < 8'd19);
always @(posedge clk) begin
if (counter > clkdiv) begin
outclk <= !outclk;
counter <= 0;
if (bufpointer > 0) begin
out <= outbuf[bufpointer - 1];
bufpointer <= bufpointer - 1;
end
end
if (!oldwrite) begin
if (writedone) begin
if(bufpointer > 0) begin
for(i=1;i<21;i=i+1) begin//probably very slow
outbuf[i] <= outbuf[i-1];
end
outbuf[0] <= in;
bufpointer <= bufpointer + 1;
oldwrite <= 1;
end
end
end
if (!writedone) begin
oldwrite <= 0;
end
end
endmodule |
`include "constants.vh"
`default_nettype none
module arf
(
input wire clk,
input wire reset,
input wire [`REG_SEL-1:0] rs1_1, //DP from here
input wire [`REG_SEL-1:0] rs2_1,
input wire [`REG_SEL-1:0] rs1_2,
input wire [`REG_SEL-1:0] rs2_2,
output wire [`DATA_LEN-1:0] rs1_1data,
output wire [`DATA_LEN-1:0] rs2_1data,
output wire [`DATA_LEN-1:0] rs1_2data,
output wire [`DATA_LEN-1:0] rs2_2data, //DP end
input wire [`REG_SEL-1:0] wreg1, //com_dst1
input wire [`REG_SEL-1:0] wreg2, //com_dst2
input wire [`DATA_LEN-1:0] wdata1, //com_data1
input wire [`DATA_LEN-1:0] wdata2, //com_data2
input wire we1, //com_en1
input wire we2, //com_en2
input wire [`RRF_SEL-1:0] wrrfent1, //comtag1
input wire [`RRF_SEL-1:0] wrrfent2, //comtag2
output wire [`RRF_SEL-1:0] rs1_1tag, // DP from here
output wire [`RRF_SEL-1:0] rs2_1tag,
output wire [`RRF_SEL-1:0] rs1_2tag,
output wire [`RRF_SEL-1:0] rs2_2tag,
input wire [`REG_SEL-1:0] tagbusy1_addr,
input wire [`REG_SEL-1:0] tagbusy2_addr,
input wire tagbusy1_we,
input wire tagbusy2_we,
input wire [`RRF_SEL-1:0] settag1,
input wire [`RRF_SEL-1:0] settag2,
input wire [`SPECTAG_LEN-1:0] tagbusy1_spectag,
input wire [`SPECTAG_LEN-1:0] tagbusy2_spectag,
output wire rs1_1busy,
output wire rs2_1busy,
output wire rs1_2busy,
output wire rs2_2busy,
input wire prmiss,
input wire prsuccess,
input wire [`SPECTAG_LEN-1:0] prtag,
input wire [`SPECTAG_LEN-1:0] mpft_valid1,
input wire [`SPECTAG_LEN-1:0] mpft_valid2
);
// Set priority on instruction2 WriteBack
// wrrfent = comtag
wire [`RRF_SEL-1:0] comreg1_tag;
wire [`RRF_SEL-1:0] comreg2_tag;
wire clearbusy1 = we1;
wire clearbusy2 = we2;
wire we1_0reg = we1 &&
(wreg1 != `REG_SEL'b0);
wire we2_0reg = we2 &&
(wreg2 != `REG_SEL'b0);
wire we1_prior2 = ((wreg1 == wreg2) &&
we1_0reg && we2_0reg) ?
1'b0 : we1_0reg;
// Set priority on instruction2 WriteBack
// we when wrrfent1 == comreg1_tag
ram_sync_nolatch_4r2w
#(`REG_SEL, `DATA_LEN, `REG_NUM)
regfile(
.clk(clk),
.raddr1(rs1_1),
.raddr2(rs2_1),
.raddr3(rs1_2),
.raddr4(rs2_2),
.rdata1(rs1_1data),
.rdata2(rs2_1data),
.rdata3(rs1_2data),
.rdata4(rs2_2data),
.waddr1(wreg1),
.waddr2(wreg2),
.wdata1(wdata1),
.wdata2(wdata2),
// .we1(we1_prior2),
.we1(we1_0reg),
.we2(we2_0reg)
);
renaming_table rt(
.clk(clk),
.reset(reset),
.rs1_1(rs1_1),
.rs2_1(rs2_1),
.rs1_2(rs1_2),
.rs2_2(rs2_2),
.comreg1(wreg1),
.comreg2(wreg2),
.rs1_1tag(rs1_1tag),
.rs2_1tag(rs2_1tag),
.rs1_2tag(rs1_2tag),
.rs2_2tag(rs2_2tag),
.rs1_1busy(rs1_1busy),
.rs2_1busy(rs2_1busy),
.rs1_2busy(rs1_2busy),
.rs2_2busy(rs2_2busy),
.settagbusy1_addr(tagbusy1_addr),
.settagbusy2_addr(tagbusy2_addr),
.settagbusy1(tagbusy1_we),
.settagbusy2(tagbusy2_we),
.settag1(settag1),
.settag2(settag2),
.setbusy1_spectag(tagbusy1_spectag),
.setbusy2_spectag(tagbusy2_spectag),
.clearbusy1(clearbusy1),
.clearbusy2(clearbusy2),
.wrrfent1(wrrfent1),
.wrrfent2(wrrfent2),
.prmiss(prmiss),
.prsuccess(prsuccess),
.prtag(prtag),
.mpft_valid1(mpft_valid1),
.mpft_valid2(mpft_valid2)
);
endmodule // arf
// Set priority on instruction2 WriteBack
/*
clear busy when comtag = rt_tag[comreg]
*/
module select_vector(
input wire [`SPECTAG_LEN-1:0] spectag,
input wire [`REG_NUM-1:0] dat0,
input wire [`REG_NUM-1:0] dat1,
input wire [`REG_NUM-1:0] dat2,
input wire [`REG_NUM-1:0] dat3,
input wire [`REG_NUM-1:0] dat4,
output reg [`REG_NUM-1:0] out
);
always @ (*) begin
out = 0;
case (spectag)
5'b00001 : out = dat1;
5'b00010 : out = dat2;
5'b00100 : out = dat3;
5'b01000 : out = dat4;
5'b10000 : out = dat0;
default : out = 0;
endcase // case (spectag)
end
endmodule // select_vector
module renaming_table
(
input wire clk,
input wire reset,
input wire [`REG_SEL-1:0] rs1_1,
input wire [`REG_SEL-1:0] rs2_1,
input wire [`REG_SEL-1:0] rs1_2,
input wire [`REG_SEL-1:0] rs2_2,
input wire [`REG_SEL-1:0] comreg1, //clearbusy1addr
input wire [`REG_SEL-1:0] comreg2, //clearbusy2addr
input wire clearbusy1, //calc on arf
input wire clearbusy2,
input wire [`RRF_SEL-1:0] wrrfent1,
input wire [`RRF_SEL-1:0] wrrfent2,
output wire [`RRF_SEL-1:0] rs1_1tag,
output wire [`RRF_SEL-1:0] rs2_1tag,
output wire [`RRF_SEL-1:0] rs1_2tag,
output wire [`RRF_SEL-1:0] rs2_2tag,
output wire rs1_1busy,
output wire rs2_1busy,
output wire rs1_2busy,
output wire rs2_2busy,
input wire [`REG_SEL-1:0] settagbusy1_addr,
input wire [`REG_SEL-1:0] settagbusy2_addr,
input wire settagbusy1,
input wire settagbusy2,
input wire [`RRF_SEL-1:0] settag1,
input wire [`RRF_SEL-1:0] settag2,
input wire [`SPECTAG_LEN-1:0] setbusy1_spectag,
input wire [`SPECTAG_LEN-1:0] setbusy2_spectag,
input wire prmiss,
input wire prsuccess,
input wire [`SPECTAG_LEN-1:0] prtag,
input wire [`SPECTAG_LEN-1:0] mpft_valid1,
input wire [`SPECTAG_LEN-1:0] mpft_valid2
);
reg [`REG_NUM-1:0] busy_0;
reg [`REG_NUM-1:0] tag0_0;
reg [`REG_NUM-1:0] tag1_0;
reg [`REG_NUM-1:0] tag2_0;
reg [`REG_NUM-1:0] tag3_0;
reg [`REG_NUM-1:0] tag4_0;
reg [`REG_NUM-1:0] tag5_0;
reg [`REG_NUM-1:0] busy_1;
reg [`REG_NUM-1:0] tag0_1;
reg [`REG_NUM-1:0] tag1_1;
reg [`REG_NUM-1:0] tag2_1;
reg [`REG_NUM-1:0] tag3_1;
reg [`REG_NUM-1:0] tag4_1;
reg [`REG_NUM-1:0] tag5_1;
reg [`REG_NUM-1:0] busy_2;
reg [`REG_NUM-1:0] tag0_2;
reg [`REG_NUM-1:0] tag1_2;
reg [`REG_NUM-1:0] tag2_2;
reg [`REG_NUM-1:0] tag3_2;
reg [`REG_NUM-1:0] tag4_2;
reg [`REG_NUM-1:0] tag5_2;
reg [`REG_NUM-1:0] busy_3;
reg [`REG_NUM-1:0] tag0_3;
reg [`REG_NUM-1:0] tag1_3;
reg [`REG_NUM-1:0] tag2_3;
reg [`REG_NUM-1:0] tag3_3;
reg [`REG_NUM-1:0] tag4_3;
reg [`REG_NUM-1:0] tag5_3;
reg [`REG_NUM-1:0] busy_4;
reg [`REG_NUM-1:0] tag0_4;
reg [`REG_NUM-1:0] tag1_4;
reg [`REG_NUM-1:0] tag2_4;
reg [`REG_NUM-1:0] tag3_4;
reg [`REG_NUM-1:0] tag4_4;
reg [`REG_NUM-1:0] tag5_4;
reg [`REG_NUM-1:0] busy_master;
reg [`REG_NUM-1:0] tag0_master;
reg [`REG_NUM-1:0] tag1_master;
reg [`REG_NUM-1:0] tag2_master;
reg [`REG_NUM-1:0] tag3_master;
reg [`REG_NUM-1:0] tag4_master;
reg [`REG_NUM-1:0] tag5_master;
wire [`REG_NUM-1:0] tag0;
wire [`REG_NUM-1:0] tag1;
wire [`REG_NUM-1:0] tag2;
wire [`REG_NUM-1:0] tag3;
wire [`REG_NUM-1:0] tag4;
wire [`REG_NUM-1:0] tag5;
wire [`SPECTAG_LEN-1:0] wesetvec1 = ~mpft_valid1;
wire [`SPECTAG_LEN-1:0] wesetvec2 = ~mpft_valid2;
wire settagbusy1_prior2 = settagbusy1 && settagbusy2 &&
(settagbusy1_addr == settagbusy2_addr) ? 1'b0 : settagbusy1;
wire clearbusy1_priorset = clearbusy1 &&
~(
(settagbusy1 && (settagbusy1_addr == comreg1)) ||
(settagbusy2 && (settagbusy2_addr == comreg1))
);
wire clearbusy2_priorset = clearbusy2 &&
~(
(settagbusy1 && (settagbusy1_addr == comreg2)) ||
(settagbusy2 && (settagbusy2_addr == comreg2))
);
wire setbusy1_master = settagbusy1_prior2;
wire setbusy2_master = settagbusy2;
wire clearbusy1_master = clearbusy1 &&
(wrrfent1 == {tag5_master[comreg1], tag4_master[comreg1],
tag3_master[comreg1], tag2_master[comreg1],
tag1_master[comreg1], tag0_master[comreg1]}) &&
~((setbusy1_master && (settagbusy1_addr == comreg1)) ||
(setbusy2_master && (settagbusy2_addr == comreg1)));
wire clearbusy2_master = clearbusy2 &&
(wrrfent2 == {tag5_master[comreg2], tag4_master[comreg2],
tag3_master[comreg2], tag2_master[comreg2],
tag1_master[comreg2], tag0_master[comreg2]}) &&
~((setbusy1_master && (settagbusy1_addr == comreg2)) ||
(setbusy2_master && (settagbusy2_addr == comreg2)));
wire setbusy1_0 = settagbusy1_prior2 && wesetvec1[0];
wire setbusy2_0 = settagbusy2 && wesetvec2[0];
wire clearbusy1_0 = clearbusy1 &&
(wrrfent1 ==
{tag5_0[comreg1], tag4_0[comreg1], tag3_0[comreg1],
tag2_0[comreg1], tag1_0[comreg1], tag0_0[comreg1]}) &&
~((setbusy1_0 && (settagbusy1_addr == comreg1)) ||
(setbusy2_0 && (settagbusy2_addr == comreg1)));
wire clearbusy2_0 = clearbusy2 &&
(wrrfent2 ==
{tag5_0[comreg2], tag4_0[comreg2], tag3_0[comreg2],
tag2_0[comreg2], tag1_0[comreg2], tag0_0[comreg2]}) &&
~((setbusy1_0 && (settagbusy1_addr == comreg2)) ||
(setbusy2_0 && (settagbusy2_addr == comreg2)));
wire setbusy1_1 = settagbusy1_prior2 && wesetvec1[1];
wire setbusy2_1 = settagbusy2 && wesetvec2[1];
wire clearbusy1_1 = clearbusy1 &&
(wrrfent1 ==
{tag5_1[comreg1], tag4_1[comreg1], tag3_1[comreg1],
tag2_1[comreg1], tag1_1[comreg1], tag0_1[comreg1]}) &&
~((setbusy1_1 && (settagbusy1_addr == comreg1)) ||
(setbusy2_1 && (settagbusy2_addr == comreg1)));
wire clearbusy2_1 = clearbusy2 &&
(wrrfent2 ==
{tag5_1[comreg2], tag4_1[comreg2], tag3_1[comreg2],
tag2_1[comreg2], tag1_1[comreg2], tag0_1[comreg2]}) &&
~((setbusy1_1 && (settagbusy1_addr == comreg2)) ||
(setbusy2_1 && (settagbusy2_addr == comreg2)));
wire setbusy1_2 = settagbusy1_prior2 && wesetvec1[2];
wire setbusy2_2 = settagbusy2 && wesetvec2[2];
wire clearbusy1_2 = clearbusy1 &&
(wrrfent1 ==
{tag5_2[comreg1], tag4_2[comreg1], tag3_2[comreg1],
tag2_2[comreg1], tag1_2[comreg1], tag0_2[comreg1]}) &&
~((setbusy1_2 && (settagbusy1_addr == comreg1)) ||
(setbusy2_2 && (settagbusy2_addr == comreg1)));
wire clearbusy2_2 = clearbusy2 &&
(wrrfent2 ==
{tag5_2[comreg2], tag4_2[comreg2], tag3_2[comreg2],
tag2_2[comreg2], tag1_2[comreg2], tag0_2[comreg2]}) &&
~((setbusy1_2 && (settagbusy1_addr == comreg2)) ||
(setbusy2_2 && (settagbusy2_addr == comreg2)));
wire setbusy1_3 = settagbusy1_prior2 && wesetvec1[3];
wire setbusy2_3 = settagbusy2 && wesetvec2[3];
wire clearbusy1_3 = clearbusy1 &&
(wrrfent1 ==
{tag5_3[comreg1], tag4_3[comreg1], tag3_3[comreg1],
tag2_3[comreg1], tag1_3[comreg1], tag0_3[comreg1]}) &&
~((setbusy1_3 && (settagbusy1_addr == comreg1)) ||
(setbusy2_3 && (settagbusy2_addr == comreg1)));
wire clearbusy2_3 = clearbusy2 &&
(wrrfent2 ==
{tag5_3[comreg2], tag4_3[comreg2], tag3_3[comreg2],
tag2_3[comreg2], tag1_3[comreg2], tag0_3[comreg2]}) &&
~((setbusy1_3 && (settagbusy1_addr == comreg2)) ||
(setbusy2_3 && (settagbusy2_addr == comreg2)));
wire setbusy1_4 = settagbusy1_prior2 && wesetvec1[4];
wire setbusy2_4 = settagbusy2 && wesetvec2[4];
wire clearbusy1_4 = clearbusy1 &&
(wrrfent1 ==
{tag5_4[comreg1], tag4_4[comreg1], tag3_4[comreg1],
tag2_4[comreg1], tag1_4[comreg1], tag0_4[comreg1]}) &&
~((setbusy1_4 && (settagbusy1_addr == comreg1)) ||
(setbusy2_4 && (settagbusy2_addr == comreg1)));
wire clearbusy2_4 = clearbusy2 &&
(wrrfent2 ==
{tag5_4[comreg2], tag4_4[comreg2], tag3_4[comreg2],
tag2_4[comreg2], tag1_4[comreg2], tag0_4[comreg2]}) &&
~((setbusy1_4 && (settagbusy1_addr == comreg2)) ||
(setbusy2_4 && (settagbusy2_addr == comreg2)));
wire [`REG_NUM-1:0] next_bsymas =
(busy_master &
((clearbusy1_master) ?
~(`REG_NUM'b1 << comreg1) :
~(`REG_NUM'b0)) &
((clearbusy2_master) ?
~(`REG_NUM'b1 << comreg2) :
~(`REG_NUM'b0))
);
wire [`REG_NUM-1:0] next_bsyand_0 =
((clearbusy1_0) ?
~(`REG_NUM'b1 << comreg1) :
~(`REG_NUM'b0)) &
((clearbusy2_0) ?
~(`REG_NUM'b1 << comreg2) :
~(`REG_NUM'b0));
wire [`REG_NUM-1:0] next_bsyand_1 =
((clearbusy1_1) ?
~(`REG_NUM'b1 << comreg1) :
~(`REG_NUM'b0)) &
((clearbusy2_1) ?
~(`REG_NUM'b1 << comreg2) :
~(`REG_NUM'b0));
wire [`REG_NUM-1:0] next_bsyand_2 =
((clearbusy1_2) ?
~(`REG_NUM'b1 << comreg1) :
~(`REG_NUM'b0)) &
((clearbusy2_2) ?
~(`REG_NUM'b1 << comreg2) :
~(`REG_NUM'b0));
wire [`REG_NUM-1:0] next_bsyand_3 =
((clearbusy1_3) ?
~(`REG_NUM'b1 << comreg1) :
~(`REG_NUM'b0)) &
((clearbusy2_3) ?
~(`REG_NUM'b1 << comreg2) :
~(`REG_NUM'b0));
wire [`REG_NUM-1:0] next_bsyand_4 =
((clearbusy1_4) ?
~(`REG_NUM'b1 << comreg1) :
~(`REG_NUM'b0)) &
((clearbusy2_4) ?
~(`REG_NUM'b1 << comreg2) :
~(`REG_NUM'b0));
assign rs1_1busy = busy_master[rs1_1];
assign rs2_1busy = busy_master[rs2_1];
assign rs1_2busy = busy_master[rs1_2];
assign rs2_2busy = busy_master[rs2_2];
assign rs1_1tag = {tag5_master[rs1_1], tag4_master[rs1_1], tag3_master[rs1_1],
tag2_master[rs1_1], tag1_master[rs1_1], tag0_master[rs1_1]};
assign rs2_1tag = {tag5_master[rs2_1], tag4_master[rs2_1], tag3_master[rs2_1],
tag2_master[rs2_1], tag1_master[rs2_1], tag0_master[rs2_1]};
assign rs1_2tag = {tag5_master[rs1_2], tag4_master[rs1_2], tag3_master[rs1_2],
tag2_master[rs1_2], tag1_master[rs1_2], tag0_master[rs1_2]};
assign rs2_2tag = {tag5_master[rs2_2], tag4_master[rs2_2], tag3_master[rs2_2],
tag2_master[rs2_2], tag1_master[rs2_2], tag0_master[rs2_2]};
always @ (posedge clk) begin
if (reset) begin
busy_0 <= 0;
busy_1 <= 0;
busy_2 <= 0;
busy_3 <= 0;
busy_4 <= 0;
busy_master <= 0;
end else begin
if (prsuccess) begin
busy_master <= next_bsymas;
busy_1 <= (prtag == 5'b00010) ? next_bsymas : (next_bsyand_1 & busy_1);
busy_2 <= (prtag == 5'b00100) ? next_bsymas : (next_bsyand_2 & busy_2);
busy_3 <= (prtag == 5'b01000) ? next_bsymas : (next_bsyand_3 & busy_3);
busy_4 <= (prtag == 5'b10000) ? next_bsymas : (next_bsyand_4 & busy_4);
busy_0 <= (prtag == 5'b00001) ? next_bsymas : (next_bsyand_0 & busy_0);
end else if (prmiss) begin // if (prsuccess)
if (prtag == 5'b00010) begin
busy_0 <= busy_1;
busy_1 <= busy_1;
busy_2 <= busy_1;
busy_3 <= busy_1;
busy_4 <= busy_1;
busy_master <= busy_1;
end else if (prtag == 5'b00100) begin
busy_0 <= busy_2;
busy_1 <= busy_2;
busy_2 <= busy_2;
busy_3 <= busy_2;
busy_4 <= busy_2;
busy_master <= busy_2;
end else if (prtag == 5'b01000) begin
busy_0 <= busy_3;
busy_1 <= busy_3;
busy_2 <= busy_3;
busy_3 <= busy_3;
busy_4 <= busy_3;
busy_master <= busy_3;
end else if (prtag == 5'b10000) begin
busy_0 <= busy_4;
busy_1 <= busy_4;
busy_2 <= busy_4;
busy_3 <= busy_4;
busy_4 <= busy_4;
busy_master <= busy_4;
end else if (prtag == 5'b00001) begin
busy_0 <= busy_0;
busy_1 <= busy_0;
busy_2 <= busy_0;
busy_3 <= busy_0;
busy_4 <= busy_0;
busy_master <= busy_0;
end
end else begin // if (prmiss)
/*
if (setbusy1_j)
busy_j[settagbusy1_addr] <= 1'b1;
if (setbusy2_j)
busy_j[settagbusy2_addr] <= 1'b1;
if (clearbusy1_j)
busy_j[comreg1] <= 1'b0;
if (clearbusy2_j)
busy_j[comreg2] <= 1'b0;
*/
if (setbusy1_master)
busy_master[settagbusy1_addr] <= 1'b1;
if (setbusy2_master)
busy_master[settagbusy2_addr] <= 1'b1;
if (clearbusy1_master)
busy_master[comreg1] <= 1'b0;
if (clearbusy2_master)
busy_master[comreg2] <= 1'b0;
if (setbusy1_0)
busy_0[settagbusy1_addr] <= 1'b1;
if (setbusy2_0)
busy_0[settagbusy2_addr] <= 1'b1;
if (clearbusy1_0)
busy_0[comreg1] <= 1'b0;
if (clearbusy2_0)
busy_0[comreg2] <= 1'b0;
if (setbusy1_1)
busy_1[settagbusy1_addr] <= 1'b1;
if (setbusy2_1)
busy_1[settagbusy2_addr] <= 1'b1;
if (clearbusy1_1)
busy_1[comreg1] <= 1'b0;
if (clearbusy2_1)
busy_1[comreg2] <= 1'b0;
if (setbusy1_2)
busy_2[settagbusy1_addr] <= 1'b1;
if (setbusy2_2)
busy_2[settagbusy2_addr] <= 1'b1;
if (clearbusy1_2)
busy_2[comreg1] <= 1'b0;
if (clearbusy2_2)
busy_2[comreg2] <= 1'b0;
if (setbusy1_3)
busy_3[settagbusy1_addr] <= 1'b1;
if (setbusy2_3)
busy_3[settagbusy2_addr] <= 1'b1;
if (clearbusy1_3)
busy_3[comreg1] <= 1'b0;
if (clearbusy2_3)
busy_3[comreg2] <= 1'b0;
if (setbusy1_4)
busy_4[settagbusy1_addr] <= 1'b1;
if (setbusy2_4)
busy_4[settagbusy2_addr] <= 1'b1;
if (clearbusy1_4)
busy_4[comreg1] <= 1'b0;
if (clearbusy2_4)
busy_4[comreg2] <= 1'b0;
end // else: !if(prmiss)
end // else: !if(reset)
end // always @ (posedge clk)
always @ (posedge clk) begin
if (reset) begin
tag0_0 <= 0;
tag1_0 <= 0;
tag2_0 <= 0;
tag3_0 <= 0;
tag4_0 <= 0;
tag5_0 <= 0;
tag0_1 <= 0;
tag1_1 <= 0;
tag2_1 <= 0;
tag3_1 <= 0;
tag4_1 <= 0;
tag5_1 <= 0;
tag0_2 <= 0;
tag1_2 <= 0;
tag2_2 <= 0;
tag3_2 <= 0;
tag4_2 <= 0;
tag5_2 <= 0;
tag0_3 <= 0;
tag1_3 <= 0;
tag2_3 <= 0;
tag3_3 <= 0;
tag4_3 <= 0;
tag5_3 <= 0;
tag0_4 <= 0;
tag1_4 <= 0;
tag2_4 <= 0;
tag3_4 <= 0;
tag4_4 <= 0;
tag5_4 <= 0;
tag0_master <= 0;
tag1_master <= 0;
tag2_master <= 0;
tag3_master <= 0;
tag4_master <= 0;
tag5_master <= 0;
end else if (prsuccess) begin
tag0_master <= tag0_master;
tag1_master <= tag1_master;
tag2_master <= tag2_master;
tag3_master <= tag3_master;
tag4_master <= tag4_master;
tag5_master <= tag5_master;
if (prtag == 5'b00010) begin
tag0_1 <= tag0_master;
tag1_1 <= tag1_master;
tag2_1 <= tag2_master;
tag3_1 <= tag3_master;
tag4_1 <= tag4_master;
tag5_1 <= tag5_master;
end else if (prtag == 5'b00100) begin
tag0_2 <= tag0_master;
tag1_2 <= tag1_master;
tag2_2 <= tag2_master;
tag3_2 <= tag3_master;
tag4_2 <= tag4_master;
tag5_2 <= tag5_master;
end else if (prtag == 5'b01000) begin
tag0_3 <= tag0_master;
tag1_3 <= tag1_master;
tag2_3 <= tag2_master;
tag3_3 <= tag3_master;
tag4_3 <= tag4_master;
tag5_3 <= tag5_master;
end else if (prtag == 5'b10000) begin
tag0_4 <= tag0_master;
tag1_4 <= tag1_master;
tag2_4 <= tag2_master;
tag3_4 <= tag3_master;
tag4_4 <= tag4_master;
tag5_4 <= tag5_master;
end else if (prtag == 5'b00001) begin
tag0_0 <= tag0_master;
tag1_0 <= tag1_master;
tag2_0 <= tag2_master;
tag3_0 <= tag3_master;
tag4_0 <= tag4_master;
tag5_0 <= tag5_master;
end
end else if (prmiss) begin // if (prsuccess)
if (prtag == 5'b00010) begin
tag0_0 <= tag0_1;
tag1_0 <= tag1_1;
tag2_0 <= tag2_1;
tag3_0 <= tag3_1;
tag4_0 <= tag4_1;
tag5_0 <= tag5_1;
tag0_1 <= tag0_1;
tag1_1 <= tag1_1;
tag2_1 <= tag2_1;
tag3_1 <= tag3_1;
tag4_1 <= tag4_1;
tag5_1 <= tag5_1;
tag0_2 <= tag0_1;
tag1_2 <= tag1_1;
tag2_2 <= tag2_1;
tag3_2 <= tag3_1;
tag4_2 <= tag4_1;
tag5_2 <= tag5_1;
tag0_3 <= tag0_1;
tag1_3 <= tag1_1;
tag2_3 <= tag2_1;
tag3_3 <= tag3_1;
tag4_3 <= tag4_1;
tag5_3 <= tag5_1;
tag0_4 <= tag0_1;
tag1_4 <= tag1_1;
tag2_4 <= tag2_1;
tag3_4 <= tag3_1;
tag4_4 <= tag4_1;
tag5_4 <= tag5_1;
tag0_master <= tag0_1;
tag1_master <= tag1_1;
tag2_master <= tag2_1;
tag3_master <= tag3_1;
tag4_master <= tag4_1;
tag5_master <= tag5_1;
end else if (prtag == 5'b00100) begin
tag0_0 <= tag0_2;
tag1_0 <= tag1_2;
tag2_0 <= tag2_2;
tag3_0 <= tag3_2;
tag4_0 <= tag4_2;
tag5_0 <= tag5_2;
tag0_1 <= tag0_2;
tag1_1 <= tag1_2;
tag2_1 <= tag2_2;
tag3_1 <= tag3_2;
tag4_1 <= tag4_2;
tag5_1 <= tag5_2;
tag0_2 <= tag0_2;
tag1_2 <= tag1_2;
tag2_2 <= tag2_2;
tag3_2 <= tag3_2;
tag4_2 <= tag4_2;
tag5_2 <= tag5_2;
tag0_3 <= tag0_2;
tag1_3 <= tag1_2;
tag2_3 <= tag2_2;
tag3_3 <= tag3_2;
tag4_3 <= tag4_2;
tag5_3 <= tag5_2;
tag0_4 <= tag0_2;
tag1_4 <= tag1_2;
tag2_4 <= tag2_2;
tag3_4 <= tag3_2;
tag4_4 <= tag4_2;
tag5_4 <= tag5_2;
tag0_master <= tag0_2;
tag1_master <= tag1_2;
tag2_master <= tag2_2;
tag3_master <= tag3_2;
tag4_master <= tag4_2;
tag5_master <= tag5_2;
end else if (prtag == 5'b01000) begin
tag0_0 <= tag0_3;
tag1_0 <= tag1_3;
tag2_0 <= tag2_3;
tag3_0 <= tag3_3;
tag4_0 <= tag4_3;
tag5_0 <= tag5_3;
tag0_1 <= tag0_3;
tag1_1 <= tag1_3;
tag2_1 <= tag2_3;
tag3_1 <= tag3_3;
tag4_1 <= tag4_3;
tag5_1 <= tag5_3;
tag0_2 <= tag0_3;
tag1_2 <= tag1_3;
tag2_2 <= tag2_3;
tag3_2 <= tag3_3;
tag4_2 <= tag4_3;
tag5_2 <= tag5_3;
tag0_3 <= tag0_3;
tag1_3 <= tag1_3;
tag2_3 <= tag2_3;
tag3_3 <= tag3_3;
tag4_3 <= tag4_3;
tag5_3 <= tag5_3;
tag0_4 <= tag0_3;
tag1_4 <= tag1_3;
tag2_4 <= tag2_3;
tag3_4 <= tag3_3;
tag4_4 <= tag4_3;
tag5_4 <= tag5_3;
tag0_master <= tag0_3;
tag1_master <= tag1_3;
tag2_master <= tag2_3;
tag3_master <= tag3_3;
tag4_master <= tag4_3;
tag5_master <= tag5_3;
end else if (prtag == 5'b10000) begin
tag0_0 <= tag0_4;
tag1_0 <= tag1_4;
tag2_0 <= tag2_4;
tag3_0 <= tag3_4;
tag4_0 <= tag4_4;
tag5_0 <= tag5_4;
tag0_1 <= tag0_4;
tag1_1 <= tag1_4;
tag2_1 <= tag2_4;
tag3_1 <= tag3_4;
tag4_1 <= tag4_4;
tag5_1 <= tag5_4;
tag0_2 <= tag0_4;
tag1_2 <= tag1_4;
tag2_2 <= tag2_4;
tag3_2 <= tag3_4;
tag4_2 <= tag4_4;
tag5_2 <= tag5_4;
tag0_3 <= tag0_4;
tag1_3 <= tag1_4;
tag2_3 <= tag2_4;
tag3_3 <= tag3_4;
tag4_3 <= tag4_4;
tag5_3 <= tag5_4;
tag0_4 <= tag0_4;
tag1_4 <= tag1_4;
tag2_4 <= tag2_4;
tag3_4 <= tag3_4;
tag4_4 <= tag4_4;
tag5_4 <= tag5_4;
tag0_master <= tag0_4;
tag1_master <= tag1_4;
tag2_master <= tag2_4;
tag3_master <= tag3_4;
tag4_master <= tag4_4;
tag5_master <= tag5_4;
end else if (prtag == 5'b00001) begin
tag0_0 <= tag0_0;
tag1_0 <= tag1_0;
tag2_0 <= tag2_0;
tag3_0 <= tag3_0;
tag4_0 <= tag4_0;
tag5_0 <= tag5_0;
tag0_1 <= tag0_0;
tag1_1 <= tag1_0;
tag2_1 <= tag2_0;
tag3_1 <= tag3_0;
tag4_1 <= tag4_0;
tag5_1 <= tag5_0;
tag0_2 <= tag0_0;
tag1_2 <= tag1_0;
tag2_2 <= tag2_0;
tag3_2 <= tag3_0;
tag4_2 <= tag4_0;
tag5_2 <= tag5_0;
tag0_3 <= tag0_0;
tag1_3 <= tag1_0;
tag2_3 <= tag2_0;
tag3_3 <= tag3_0;
tag4_3 <= tag4_0;
tag5_3 <= tag5_0;
tag0_4 <= tag0_0;
tag1_4 <= tag1_0;
tag2_4 <= tag2_0;
tag3_4 <= tag3_0;
tag4_4 <= tag4_0;
tag5_4 <= tag5_0;
tag0_master <= tag0_0;
tag1_master <= tag1_0;
tag2_master <= tag2_0;
tag3_master <= tag3_0;
tag4_master <= tag4_0;
tag5_master <= tag5_0;
end
end else begin // if (prmiss)
if (settagbusy1) begin
//TAG0
tag0_master[settagbusy1_addr] <= settagbusy1_prior2 ?
settag1[0] : tag0_master[settagbusy1_addr];
tag0_0[settagbusy1_addr] <= (wesetvec1[0] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[0] : tag0_0[settagbusy1_addr];
tag0_1[settagbusy1_addr] <= (wesetvec1[1] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[0] : tag0_1[settagbusy1_addr];
tag0_2[settagbusy1_addr] <= (wesetvec1[2] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[0] : tag0_2[settagbusy1_addr];
tag0_3[settagbusy1_addr] <= (wesetvec1[3] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[0] : tag0_3[settagbusy1_addr];
tag0_4[settagbusy1_addr] <= (wesetvec1[4] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[0] : tag0_4[settagbusy1_addr];
//TAG1
tag1_master[settagbusy1_addr] <= settagbusy1_prior2 ?
settag1[1] : tag1_master[settagbusy1_addr];
tag1_0[settagbusy1_addr] <= (wesetvec1[0] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[1] : tag1_0[settagbusy1_addr];
tag1_1[settagbusy1_addr] <= (wesetvec1[1] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[1] : tag1_1[settagbusy1_addr];
tag1_2[settagbusy1_addr] <= (wesetvec1[2] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[1] : tag1_2[settagbusy1_addr];
tag1_3[settagbusy1_addr] <= (wesetvec1[3] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[1] : tag1_3[settagbusy1_addr];
tag1_4[settagbusy1_addr] <= (wesetvec1[4] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[1] : tag1_4[settagbusy1_addr];
//TAG2
tag2_master[settagbusy1_addr] <= settagbusy1_prior2 ?
settag1[2] : tag2_master[settagbusy1_addr];
tag2_0[settagbusy1_addr] <= (wesetvec1[0] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[2] : tag2_0[settagbusy1_addr];
tag2_1[settagbusy1_addr] <= (wesetvec1[1] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[2] : tag2_1[settagbusy1_addr];
tag2_2[settagbusy1_addr] <= (wesetvec1[2] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[2] : tag2_2[settagbusy1_addr];
tag2_3[settagbusy1_addr] <= (wesetvec1[3] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[2] : tag2_3[settagbusy1_addr];
tag2_4[settagbusy1_addr] <= (wesetvec1[4] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[2] : tag2_4[settagbusy1_addr];
//TAG3
tag3_master[settagbusy1_addr] <= settagbusy1_prior2 ?
settag1[3] : tag3_master[settagbusy1_addr];
tag3_0[settagbusy1_addr] <= (wesetvec1[0] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[3] : tag3_0[settagbusy1_addr];
tag3_1[settagbusy1_addr] <= (wesetvec1[1] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[3] : tag3_1[settagbusy1_addr];
tag3_2[settagbusy1_addr] <= (wesetvec1[2] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[3] : tag3_2[settagbusy1_addr];
tag3_3[settagbusy1_addr] <= (wesetvec1[3] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[3] : tag3_3[settagbusy1_addr];
tag3_4[settagbusy1_addr] <= (wesetvec1[4] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[3] : tag3_4[settagbusy1_addr];
//TAG4
tag4_master[settagbusy1_addr] <= settagbusy1_prior2 ?
settag1[4] : tag4_master[settagbusy1_addr];
tag4_0[settagbusy1_addr] <= (wesetvec1[0] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[4] : tag4_0[settagbusy1_addr];
tag4_1[settagbusy1_addr] <= (wesetvec1[1] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[4] : tag4_1[settagbusy1_addr];
tag4_2[settagbusy1_addr] <= (wesetvec1[2] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[4] : tag4_2[settagbusy1_addr];
tag4_3[settagbusy1_addr] <= (wesetvec1[3] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[4] : tag4_3[settagbusy1_addr];
tag4_4[settagbusy1_addr] <= (wesetvec1[4] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[4] : tag4_4[settagbusy1_addr];
//TAG5
tag5_master[settagbusy1_addr] <= settagbusy1_prior2 ?
settag1[5] : tag5_master[settagbusy1_addr];
tag5_0[settagbusy1_addr] <= (wesetvec1[0] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[5] : tag5_0[settagbusy1_addr];
tag5_1[settagbusy1_addr] <= (wesetvec1[1] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[5] : tag5_1[settagbusy1_addr];
tag5_2[settagbusy1_addr] <= (wesetvec1[2] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[5] : tag5_2[settagbusy1_addr];
tag5_3[settagbusy1_addr] <= (wesetvec1[3] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[5] : tag5_3[settagbusy1_addr];
tag5_4[settagbusy1_addr] <= (wesetvec1[4] &
(settagbusy1_prior2 |
(setbusy1_spectag != setbusy2_spectag))) ?
settag1[5] : tag5_4[settagbusy1_addr];
end // if (setttagbusy1)
if (settagbusy2) begin
//TAG0
tag0_master[settagbusy2_addr] <= settag2[0];
tag0_0[settagbusy2_addr] <= wesetvec2[0] ?
settag2[0] : tag0_0[settagbusy2_addr];
tag0_1[settagbusy2_addr] <= wesetvec2[1] ?
settag2[0] : tag0_1[settagbusy2_addr];
tag0_2[settagbusy2_addr] <= wesetvec2[2] ?
settag2[0] : tag0_2[settagbusy2_addr];
tag0_3[settagbusy2_addr] <= wesetvec2[3] ?
settag2[0] : tag0_3[settagbusy2_addr];
tag0_4[settagbusy2_addr] <= wesetvec2[4] ?
settag2[0] : tag0_4[settagbusy2_addr];
//TAG1
tag1_master[settagbusy2_addr] <= settag2[1];
tag1_0[settagbusy2_addr] <= wesetvec2[0] ?
settag2[1] : tag1_0[settagbusy2_addr];
tag1_1[settagbusy2_addr] <= wesetvec2[1] ?
settag2[1] : tag1_1[settagbusy2_addr];
tag1_2[settagbusy2_addr] <= wesetvec2[2] ?
settag2[1] : tag1_2[settagbusy2_addr];
tag1_3[settagbusy2_addr] <= wesetvec2[3] ?
settag2[1] : tag1_3[settagbusy2_addr];
tag1_4[settagbusy2_addr] <= wesetvec2[4] ?
settag2[1] : tag1_4[settagbusy2_addr];
//TAG2
tag2_master[settagbusy2_addr] <= settag2[2];
tag2_0[settagbusy2_addr] <= wesetvec2[0] ?
settag2[2] : tag2_0[settagbusy2_addr];
tag2_1[settagbusy2_addr] <= wesetvec2[1] ?
settag2[2] : tag2_1[settagbusy2_addr];
tag2_2[settagbusy2_addr] <= wesetvec2[2] ?
settag2[2] : tag2_2[settagbusy2_addr];
tag2_3[settagbusy2_addr] <= wesetvec2[3] ?
settag2[2] : tag2_3[settagbusy2_addr];
tag2_4[settagbusy2_addr] <= wesetvec2[4] ?
settag2[2] : tag2_4[settagbusy2_addr];
//TAG3
tag3_master[settagbusy2_addr] <= settag2[3];
tag3_0[settagbusy2_addr] <= wesetvec2[0] ?
settag2[3] : tag3_0[settagbusy2_addr];
tag3_1[settagbusy2_addr] <= wesetvec2[1] ?
settag2[3] : tag3_1[settagbusy2_addr];
tag3_2[settagbusy2_addr] <= wesetvec2[2] ?
settag2[3] : tag3_2[settagbusy2_addr];
tag3_3[settagbusy2_addr] <= wesetvec2[3] ?
settag2[3] : tag3_3[settagbusy2_addr];
tag3_4[settagbusy2_addr] <= wesetvec2[4] ?
settag2[3] : tag3_4[settagbusy2_addr];
//TAG4
tag4_master[settagbusy2_addr] <= settag2[4];
tag4_0[settagbusy2_addr] <= wesetvec2[0] ?
settag2[4] : tag4_0[settagbusy2_addr];
tag4_1[settagbusy2_addr] <= wesetvec2[1] ?
settag2[4] : tag4_1[settagbusy2_addr];
tag4_2[settagbusy2_addr] <= wesetvec2[2] ?
settag2[4] : tag4_2[settagbusy2_addr];
tag4_3[settagbusy2_addr] <= wesetvec2[3] ?
settag2[4] : tag4_3[settagbusy2_addr];
tag4_4[settagbusy2_addr] <= wesetvec2[4] ?
settag2[4] : tag4_4[settagbusy2_addr];
//TAG5
tag5_master[settagbusy2_addr] <= settag2[5];
tag5_0[settagbusy2_addr] <= wesetvec2[0] ?
settag2[5] : tag5_0[settagbusy2_addr];
tag5_1[settagbusy2_addr] <= wesetvec2[1] ?
settag2[5] : tag5_1[settagbusy2_addr];
tag5_2[settagbusy2_addr] <= wesetvec2[2] ?
settag2[5] : tag5_2[settagbusy2_addr];
tag5_3[settagbusy2_addr] <= wesetvec2[3] ?
settag2[5] : tag5_3[settagbusy2_addr];
tag5_4[settagbusy2_addr] <= wesetvec2[4] ?
settag2[5] : tag5_4[settagbusy2_addr];
end
end
end
endmodule // renaming_table
`default_nettype wire
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Line State Machine
// File : dex_smline.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// Included by dex_sm.v
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module dex_smline
(
input de_clk,
input de_rstn,
input goline,
input [2:0] dir,
input eol,
input signx,
input eline_actv_2,
input pcbusy,
input nlst_2,
input clip,
input cstop_2,
input eneg,
input eeqz,
output reg l_ldmaj,
output reg l_ldmin,
output reg l_bound,
output reg l_incpat,
output reg inc_err,
output reg rst_err,
output reg l_chgx,
output reg l_chgy,
output reg l_dec_itr,
output reg l_pixreq,
output reg l_set_busy,
output reg l_clr_busy,
output reg l_mul,
output reg l_pc_msk_last,
output reg l_frst_pix,
output reg l_last_pixel,
output reg l_src_upd,
output reg [21:0] l_op,
output l_rht,
output l_dwn
);
/****************************************************************/
/* DEFINE PARAMETERS */
/****************************************************************/
parameter
LWAIT = 4'h0,
L1 = 4'h1,
L2 = 4'h2,
L3 = 4'h3,
L4 = 4'h4,
L5 = 4'h5,
L6 = 4'h6,
L7 = 4'h7,
L8 = 4'h8,
LIDLE1 = 4'ha,
src = 5'h0,
dst = 5'h1,
delta = 5'h2,
noop = 5'h0,
pline = 5'h10,
einc = 5'h4,
error = 5'h3,
err_inc = 5'hc,
sub = 5'h12,
add = 5'h1,
abs = 5'h0,
mov = 5'hd,
movx = 5'hf,
subx = 5'h13,
cmp_add = 5'h7,
addx = 5'h3,
wrhl = 2'b00,
wrno = 2'b11,
wrhi = 2'b01,
dorgl = 5'hf;
parameter
/* define octants */
/* |YMAJ|sign dy|sign dx| */
/* \ | / */
o0=3'b000, /* \ 7 | 6 / */
o1=3'b001, /* \ | / */
o2=3'b010, /* 3 \ | / 2 */
o3=3'b011, /* --------|------- */
o4=3'b100, /* 1 /| \ 0 */
o5=3'b101, /* / | \ */
o6=3'b110, /* / 5 | 4 \ */
o7=3'b111; /* / | \ */
/* define internal wires and make assignments */
reg [3:0] l_cs;
reg [3:0] l_ns;
/* create the state register */
always @(posedge de_clk or negedge de_rstn) begin
if(!de_rstn)l_cs <= 4'b0;
else l_cs <= l_ns;
end
assign l_rht = ((dir==o0) || (dir==o2) || (dir==o4) || (dir==o6));
assign l_dwn = ((dir==o0) || (dir==o1) || (dir==o4) || (dir==o5));
always @* begin
l_ldmaj = 1'b0;
l_ldmin = 1'b0;
l_bound = 1'b0;
l_incpat = 1'b0;
inc_err = 1'b0;
rst_err = 1'b0;
l_chgx = 1'b0;
l_chgy = 1'b0;
l_dec_itr = 1'b0;
l_pixreq = 1'b0;
l_set_busy = 1'b0;
l_clr_busy = 1'b0;
l_mul = 1'b0;
l_pc_msk_last = 1'b0;
l_frst_pix = 1'b0;
l_last_pixel = 1'b0;
l_src_upd = 1'b0;
l_op = 22'b00000_00000_00000_00000_11;
case(l_cs) /* synopsys full_case parallel_case */
LWAIT: if(goline)
begin /* calculate deltaX and deltaY */
l_ns=L1;
l_op={dst,src,sub,delta,wrhl};
l_set_busy=1'b1;
end
else l_ns= LWAIT;
L1: begin /* absolute deltaX and deltaY */
l_ns=L2;
l_op={noop,pline,abs,delta,wrhl};
l_mul=1'b1;
end
/* calculate the major axis */
L2: begin /* deltaX minus deltaY and load the resulting sign bit in L4 */
l_ldmin=1'b1;
l_ns=L3;
l_op={pline,pline,subx,noop,wrno};
end
/* wait for the pipeline delay, and add the origin to the destination. */
L3: begin /* add org low nibble to source point */
l_ns=L4;
l_op={dorgl,src,add,src,wrhi};
end
/* If deltaY < deltaX swap deltaX and deltY. */
L4: begin
l_ldmaj=1'b1;
l_ns=L5;
if(signx)l_op={delta,delta,movx,delta,wrhl};
else l_op={delta,delta,mov,noop,wrno};
end
L5: if(!eline_actv_2) /* if not eline calculate the two error increments */
begin /* fx = (ax * 2) - (ay * 2), fy= (ay * 2) */
l_ns=L6;
l_op={pline,pline,err_inc,einc,wrhl};
end
else begin
l_ns=L6;
l_op={einc,einc,subx,einc,wrhi};
end
/* initial error equals (-delta major + 2(delta minor)). */
L6: begin
l_ns=L7;
if(!eline_actv_2)l_op={pline,delta,cmp_add,error,wrhi};
else l_op={error,einc,addx,error,wrhi};
end
L7: begin
if(!pcbusy)
begin
l_op={noop,pline,mov,noop,wrno};
l_ns=4'hb;
end
else l_ns=L7;
l_frst_pix=1'b1;
// l_pipe_adv=1;
end
/* End of line with nolast set */
/* Go to IDLE state. */
L8: begin
if(eol && nlst_2)
begin
l_ns=LIDLE1;
l_pixreq=1'b1;
l_last_pixel = 1'b1;
l_pc_msk_last=1'b1;
l_op={noop,dst,mov,src,wrhl};
l_src_upd=1'b1;
end
/* End of line with nolast not set and stop or not stop. */
/* draw last pixel if pixel cache is not busy. */
/* Go to IDLE state. */
else if(!pcbusy && eol && !nlst_2)
begin
l_ns=LIDLE1;
l_incpat=1'b1;
l_op={noop,dst,mov,src,wrhl};
l_src_upd=1'b1;
end
/* Not end of line. */
/* Hit clipping boundry with stop set. */
/* Draw last pixel if pixel cache is not busy. */
/* Go to IDLE state. */
else if(!pcbusy && !eol && clip && cstop_2)
begin
l_ns=LIDLE1;
l_bound=1'b1;
l_incpat=1'b1;
l_op={noop,dst,mov,src,wrhl};
l_src_upd=1'b1;
end
/* Not end of line draw pixel if pixel cache is no busy. */
else if(!pcbusy && !eol)
begin
l_incpat=1'b1;
l_dec_itr=1'b1;
l_ns=L8;
if(!pcbusy && (dir==o1 || dir==o3 || dir==o5 || dir==o7) && !eneg && !eeqz)// > 0
/* error >=0 reset error */ rst_err=1;
else if(!pcbusy && (dir==o0 || dir==o2 || dir==o4 || dir==o6) && !eneg) // >= 0
/* error > 0 reset error */ rst_err=1;
else if(!pcbusy)
/* increment error. */ inc_err=1;
end
else begin
l_op={noop,pline,mov,noop,wrno};
l_ns=L8;
end
if(!pcbusy) begin
if(eol && !nlst_2) begin
l_pixreq=1'b1;
l_last_pixel = 1'b1;
end
else if(!eol && clip && cstop_2) l_pixreq=1'b1;
else if(!eol)l_pixreq=1'b1;
if(!eol && (dir==o1 || dir==o3 || dir==o5 || dir==o7) && !eneg && !eeqz)// > 0
l_chgx=1'b1;
else if(!eol && (dir==o0 || dir==o2 || dir==o4 || dir==o6) && !eneg) // >= 0
l_chgx=1'b1;
else if(!eol && (dir==o0 || dir==o1 || dir==o2 || dir==o3))
l_chgx=1'b1;
if(!eol && (dir==o1 || dir==o3 || dir==o5 || dir==o7) && !eneg && !eeqz)// > 0
l_chgy=1'b1;
else if(!eol && (dir==o0 || dir==o2 || dir==o4 || dir==o6) && !eneg) // >= 0
l_chgy=1'b1;
else if(!eol && (dir==o4 || dir==o5 || dir==o6 || dir==o7))
l_chgy=1'b1;
end
end
4'hb: begin
l_ns=L8;
l_op={noop,pline,mov,noop,wrno};
end
LIDLE1: begin
l_ns=LWAIT;
l_clr_busy=1'b1;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DLXTP_FUNCTIONAL_PP_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Name Output Other arguments
sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTP_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGRBP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SREGRBP_PP_SYMBOL_V
/**
* sregrbp: ????.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sregrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{scanchain|Scan Chain}}
input ASYNC,
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGRBP_PP_SYMBOL_V
|
`timescale 1ns/1ns
module uart_tx#(
parameter integer WIDTH = 12
)
(
input PCLK,
input RESET,
input [7:0] DATA_TX_I,
input [11:0] WORK_FR,
input START,
output TX_O,
output reg READY_TX
);
localparam [11:0] TX_IDLE = 12'b0000_0000_0000,
TX_START = 12'b0000_0000_0001,
TX_BIT_1 = 12'b0000_0000_0010,
TX_BIT_2 = 12'b0000_0000_0100,
TX_BIT_3 = 12'b0000_0000_1000,
TX_BIT_4 = 12'b0000_0001_0000,
TX_BIT_5 = 12'b0000_0010_0000,
TX_BIT_6 = 12'b0000_0100_0000,
TX_BIT_7 = 12'b0000_1000_0000,
TX_BIT_8 = 12'b0001_0000_0000,
TX_PARITY = 12'b0010_0000_0000,
TX_STOP = 12'b0100_0000_0000;
reg [11:0] state_tx;
reg [11:0] next_state_tx;
reg [WIDTH-1:0] DELAY_COUNTER;
assign TX_O = (state_tx == TX_START)?1'b0:
(state_tx == TX_BIT_1)?DATA_TX_I[0:0]:
(state_tx == TX_BIT_2)?DATA_TX_I[1:1]:
(state_tx == TX_BIT_3)?DATA_TX_I[2:2]:
(state_tx == TX_BIT_4)?DATA_TX_I[3:3]:
(state_tx == TX_BIT_5)?DATA_TX_I[4:4]:
(state_tx == TX_BIT_6)?DATA_TX_I[5:5]:
(state_tx == TX_BIT_7)?DATA_TX_I[6:6]:
(state_tx == TX_BIT_8)?DATA_TX_I[7:7]:
(state_tx == TX_PARITY)?DATA_TX_I[0:0]^DATA_TX_I[1:1]^DATA_TX_I[2:2]^DATA_TX_I[3:3]^DATA_TX_I[4:4]^DATA_TX_I[5:5]^DATA_TX_I[6:6]^DATA_TX_I[7:7]:
(state_tx == TX_STOP)?1'b1:1'b1;
always@(*)
begin
next_state_tx = state_tx;
case(state_tx)
TX_IDLE:
begin
if(START == 1'b0)
begin
next_state_tx = TX_IDLE;
end
else
begin
next_state_tx = TX_START;
end
end
TX_START:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_START;
end
else
begin
next_state_tx = TX_BIT_1;
end
end
TX_BIT_1:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_BIT_1;
end
else
begin
next_state_tx = TX_BIT_2;
end
end
TX_BIT_2:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_BIT_2;
end
else
begin
next_state_tx = TX_BIT_3;
end
end
TX_BIT_3:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_BIT_3;
end
else
begin
next_state_tx = TX_BIT_4;
end
end
TX_BIT_4:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_BIT_4;
end
else
begin
next_state_tx = TX_BIT_5;
end
end
TX_BIT_5:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_BIT_5;
end
else
begin
next_state_tx = TX_BIT_6;
end
end
TX_BIT_6:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_BIT_6;
end
else
begin
next_state_tx = TX_BIT_7;
end
end
TX_BIT_7:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_BIT_7;
end
else
begin
next_state_tx = TX_BIT_8;
end
end
TX_BIT_8:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_BIT_8;
end
else
begin
next_state_tx = TX_PARITY;
end
end
TX_PARITY:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_PARITY;
end
else
begin
next_state_tx = TX_STOP;
end
end
TX_STOP:
begin
if(DELAY_COUNTER != WORK_FR)
begin
next_state_tx = TX_STOP;
end
else
begin
next_state_tx = TX_IDLE;
end
end
default:
begin
next_state_tx = TX_IDLE;
end
endcase
end
always@(posedge PCLK)
begin
if(RESET)
begin
READY_TX <= 1'b1;
DELAY_COUNTER<= {WIDTH{1'b0}};
state_tx <= TX_IDLE;
end
else
begin
state_tx <= next_state_tx;
case(state_tx)
TX_IDLE:
begin
if(START == 1'b0)
begin
READY_TX<= 1'b1;
DELAY_COUNTER<= {WIDTH{1'b0}};
end
else
begin
READY_TX<= 1'b0;
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
end
TX_START:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
TX_BIT_1:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
TX_BIT_2:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
TX_BIT_3:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
TX_BIT_4:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
TX_BIT_5:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
TX_BIT_6:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
TX_BIT_7:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
TX_BIT_8:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER <= {WIDTH{1'b0}};
end
end
TX_PARITY:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER <= {WIDTH{1'b0}};
end
end
TX_STOP:
begin
if(DELAY_COUNTER < WORK_FR)
begin
DELAY_COUNTER <= DELAY_COUNTER + 1'b1;
end
else
begin
DELAY_COUNTER<= {WIDTH{1'b0}};
end
end
default:
begin
DELAY_COUNTER<= {WIDTH{1'b1}};
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4BB_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__OR4BB_BEHAVIORAL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__or4bb (
X ,
A ,
B ,
C_N,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out;
wire or0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out, D_N, C_N );
or or0 (or0_out_X, B, A, nand0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4BB_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTN_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLXTN_PP_BLACKBOX_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlxtn (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTN_PP_BLACKBOX_V
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bios_rom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module bios_rom (
address,
clock,
q);
input [13:0] address;
input clock;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({16{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "bios_rom.mif",
altsyncram_component.intended_device_family = "Arria II GX",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16384,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 14,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "bios_rom.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "bios_rom.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_rom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_rom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_rom_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios_rom_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2_TB_V
`define SKY130_FD_SC_HDLL__OR2_TB_V
/**
* or2: 2-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hdll__or2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2_TB_V
|
module adder(a, b, sum_ab);
parameter integer N_BITS_A = 4;
parameter integer BIN_PT_A = 3;
parameter integer SIGNED_A = 1;
parameter integer N_BITS_B = 4;
parameter integer BIN_PT_B = 2;
parameter integer SIGNED_B = 0;
// TODO
parameter integer N_BITS_OUT = 6;
parameter integer BIN_PT_OUT = 3;
parameter integer SIGNED_OUT = 1;
//0 = WRAP, 1 = SATURATE
parameter integer OVERFLOW_STRATEGY = 0;
//0 = TRUNCATE, 1 = ROUND
parameter integer QUANTIZATION_STRATEGY = 0;
input wire [N_BITS_A-1:0] a;
input wire [N_BITS_B-1:0] b;
output wire [N_BITS_OUT-1:0] sum_ab;
// if inputs are unsigned, pad with 0
localparam integer WHOLE_BITS_A = N_BITS_A-BIN_PT_A;
localparam integer WHOLE_BITS_B = N_BITS_B-BIN_PT_B;
localparam integer WHOLE_BITS_A_IN = (SIGNED_A == 1) ? WHOLE_BITS_A : (WHOLE_BITS_A+1);
localparam integer WHOLE_BITS_B_IN = (SIGNED_B == 1) ? WHOLE_BITS_B : (WHOLE_BITS_B+1);
localparam integer N_BITS_A_IN = WHOLE_BITS_A_IN + BIN_PT_A;
localparam integer N_BITS_B_IN = WHOLE_BITS_B_IN + BIN_PT_B;
wire [N_BITS_A_IN-1:0] a_in;
assign a_in[N_BITS_A-1:0] = a;
assign a_in[N_BITS_A_IN-1] = (SIGNED_A == 1) ? a[N_BITS_A-1] : 1'b0;
wire [N_BITS_B_IN-1:0] b_in;
assign b_in[N_BITS_B-1:0] = b;
assign b_in[N_BITS_B_IN-1] = (SIGNED_B == 1) ? b[N_BITS_B-1] : 1'b0;
// derived parameters for output of adder
localparam integer WHOLE_BITS_ADD_OUT = (WHOLE_BITS_A_IN > WHOLE_BITS_B_IN) ? WHOLE_BITS_A_IN: WHOLE_BITS_B_IN;
localparam integer BIN_PT_ADD_OUT = (BIN_PT_A > BIN_PT_B) ? BIN_PT_A: BIN_PT_B;
localparam integer N_BITS_ADD_OUT = WHOLE_BITS_ADD_OUT + BIN_PT_ADD_OUT + 1;
wire [N_BITS_ADD_OUT-1:0] sum;
add #(.N_BITS_A(N_BITS_A_IN),
.BIN_PT_A(BIN_PT_A),
.N_BITS_B(N_BITS_B_IN),
.BIN_PT_B(BIN_PT_B)) add0 (a_in, b_in, sum);
//TODO quantise and handle overflow if necessary
assign sum_ab = sum;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22A_4_V
`define SKY130_FD_SC_HDLL__O22A_4_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o22a_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o22a_4 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22A_4_V
|
// file: Clock70MHz_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module Clock70MHz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock70MHz_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:01:49 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_exp_operation_A_S, FSM_selector_A, FSM_selector_C,
FSM_selector_B_1_, Sgf_operation_Result_13_,
Sgf_operation_EVEN1_result_B_adder_2_,
Sgf_operation_EVEN1_result_A_adder_3_,
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left_8_, n168, n170, n171,
n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182,
n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193,
n194, n195, n196, n197, n198, n199, n200, n202, n203, n204, n205,
n206, n207, n208, n209, n210, n211, n212, n213, n214, n221, n222,
n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, n233,
n234, n235, n238, n240, n241, n242, n243, n245, n246, n247, n248,
n251, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262,
n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273,
n274, n285, n286, n287, n288, n289, n290, n291, n292, n293, n294,
n295, n296, n297, n298, n299, n300, n301, n302, n303, n304, n305,
n306, n307, n308, n309, n310, n311, n312, n314, n315, n316, n317,
n319, n320, n321, n322, n323, n324, n326, n327, n328, n329, n330,
n331, n332, n333, n334, n335, n336, n337, n338, n339, n340, n341,
n342, n343, n346, n348, n349, n350, n352, n353, n354, n355, n356,
n357, n358, n359, n360, n362, n363, n364, n365, n366, n367, n368,
n369, n370, n371, n372, n373, n374, n375, n376, n377, n378, n380,
n381, add_x_23_n50, add_x_23_n23, add_x_23_n21, add_x_23_n4,
DP_OP_154J6_123_2038_n795, DP_OP_154J6_123_2038_n794,
DP_OP_154J6_123_2038_n793, DP_OP_154J6_123_2038_n792,
DP_OP_154J6_123_2038_n791, DP_OP_154J6_123_2038_n782,
DP_OP_154J6_123_2038_n722, DP_OP_154J6_123_2038_n720,
DP_OP_154J6_123_2038_n719, DP_OP_154J6_123_2038_n718,
DP_OP_154J6_123_2038_n717, DP_OP_154J6_123_2038_n716,
DP_OP_154J6_123_2038_n714, DP_OP_154J6_123_2038_n705,
DP_OP_154J6_123_2038_n700, DP_OP_154J6_123_2038_n699,
DP_OP_154J6_123_2038_n695, DP_OP_154J6_123_2038_n693,
DP_OP_154J6_123_2038_n687, DP_OP_154J6_123_2038_n686,
DP_OP_154J6_123_2038_n685, DP_OP_154J6_123_2038_n684,
DP_OP_154J6_123_2038_n683, DP_OP_154J6_123_2038_n682,
DP_OP_154J6_123_2038_n636, DP_OP_154J6_123_2038_n634,
DP_OP_154J6_123_2038_n632, DP_OP_154J6_123_2038_n631,
DP_OP_154J6_123_2038_n630, DP_OP_154J6_123_2038_n628,
DP_OP_154J6_123_2038_n626, DP_OP_154J6_123_2038_n624,
DP_OP_154J6_123_2038_n620, DP_OP_154J6_123_2038_n617,
DP_OP_154J6_123_2038_n616, DP_OP_154J6_123_2038_n612,
DP_OP_154J6_123_2038_n611, DP_OP_154J6_123_2038_n605,
DP_OP_154J6_123_2038_n600, DP_OP_154J6_123_2038_n392,
DP_OP_154J6_123_2038_n388, DP_OP_154J6_123_2038_n387,
DP_OP_154J6_123_2038_n386, DP_OP_154J6_123_2038_n385,
DP_OP_154J6_123_2038_n380, DP_OP_154J6_123_2038_n379,
DP_OP_154J6_123_2038_n378, DP_OP_154J6_123_2038_n361,
DP_OP_154J6_123_2038_n312, DP_OP_153J6_122_5442_n1517,
DP_OP_153J6_122_5442_n1516, DP_OP_153J6_122_5442_n1514,
DP_OP_153J6_122_5442_n1504, DP_OP_153J6_122_5442_n1503,
DP_OP_153J6_122_5442_n1501, DP_OP_153J6_122_5442_n1479,
DP_OP_153J6_122_5442_n1477, DP_OP_153J6_122_5442_n1475,
DP_OP_153J6_122_5442_n1469, DP_OP_153J6_122_5442_n1468,
DP_OP_153J6_122_5442_n1467, DP_OP_153J6_122_5442_n1466,
DP_OP_153J6_122_5442_n1458, DP_OP_153J6_122_5442_n1385,
DP_OP_153J6_122_5442_n1376, DP_OP_153J6_122_5442_n1207,
DP_OP_153J6_122_5442_n1202, DP_OP_153J6_122_5442_n1191,
DP_OP_153J6_122_5442_n1190, DP_OP_153J6_122_5442_n1184,
DP_OP_153J6_122_5442_n1183, DP_OP_153J6_122_5442_n1182,
DP_OP_153J6_122_5442_n1181, DP_OP_153J6_122_5442_n1150,
DP_OP_153J6_122_5442_n1122, DP_OP_153J6_122_5442_n1106,
DP_OP_153J6_122_5442_n1105, DP_OP_153J6_122_5442_n1104,
DP_OP_153J6_122_5442_n1099, DP_OP_153J6_122_5442_n1098,
DP_OP_153J6_122_5442_n1097, DP_OP_153J6_122_5442_n1065,
DP_OP_153J6_122_5442_n1063, DP_OP_153J6_122_5442_n870,
DP_OP_153J6_122_5442_n838, DP_OP_153J6_122_5442_n837,
DP_OP_153J6_122_5442_n829, DP_OP_153J6_122_5442_n828,
DP_OP_153J6_122_5442_n827, DP_OP_153J6_122_5442_n792,
DP_OP_153J6_122_5442_n778, DP_OP_153J6_122_5442_n451,
DP_OP_153J6_122_5442_n72, DP_OP_153J6_122_5442_n63,
DP_OP_153J6_122_5442_n54, DP_OP_153J6_122_5442_n41,
DP_OP_153J6_122_5442_n40, DP_OP_153J6_122_5442_n36,
DP_OP_153J6_122_5442_n35, DP_OP_153J6_122_5442_n8,
DP_OP_153J6_122_5442_n7, DP_OP_153J6_122_5442_n6,
DP_OP_153J6_122_5442_n5, DP_OP_153J6_122_5442_n4,
DP_OP_153J6_122_5442_n1, add_x_55_n54, add_x_55_n47, add_x_55_n46,
add_x_55_n39, add_x_55_n38, add_x_55_n29, add_x_55_n21, add_x_55_n6,
DP_OP_155J6_124_2038_n805, DP_OP_155J6_124_2038_n804,
DP_OP_155J6_124_2038_n803, DP_OP_155J6_124_2038_n801,
DP_OP_155J6_124_2038_n798, DP_OP_155J6_124_2038_n795,
DP_OP_155J6_124_2038_n793, DP_OP_155J6_124_2038_n792,
DP_OP_155J6_124_2038_n791, DP_OP_155J6_124_2038_n790,
DP_OP_155J6_124_2038_n789, DP_OP_155J6_124_2038_n788,
DP_OP_155J6_124_2038_n787, DP_OP_155J6_124_2038_n785,
DP_OP_155J6_124_2038_n784, DP_OP_155J6_124_2038_n783,
DP_OP_155J6_124_2038_n782, DP_OP_155J6_124_2038_n730,
DP_OP_155J6_124_2038_n728, DP_OP_155J6_124_2038_n724,
DP_OP_155J6_124_2038_n723, DP_OP_155J6_124_2038_n721,
DP_OP_155J6_124_2038_n717, DP_OP_155J6_124_2038_n715,
DP_OP_155J6_124_2038_n713, DP_OP_155J6_124_2038_n710,
DP_OP_155J6_124_2038_n705, DP_OP_155J6_124_2038_n703,
DP_OP_155J6_124_2038_n700, DP_OP_155J6_124_2038_n699,
DP_OP_155J6_124_2038_n698, DP_OP_155J6_124_2038_n641,
DP_OP_155J6_124_2038_n640, DP_OP_155J6_124_2038_n635,
DP_OP_155J6_124_2038_n632, DP_OP_155J6_124_2038_n631,
DP_OP_155J6_124_2038_n625, DP_OP_155J6_124_2038_n623,
DP_OP_155J6_124_2038_n618, DP_OP_155J6_124_2038_n617,
DP_OP_155J6_124_2038_n616, DP_OP_155J6_124_2038_n613,
DP_OP_155J6_124_2038_n390, DP_OP_155J6_124_2038_n388,
DP_OP_155J6_124_2038_n380, DP_OP_155J6_124_2038_n379,
DP_OP_36J6_126_4699_n22, DP_OP_36J6_126_4699_n21,
DP_OP_36J6_126_4699_n20, DP_OP_36J6_126_4699_n19,
DP_OP_36J6_126_4699_n18, DP_OP_36J6_126_4699_n17,
DP_OP_36J6_126_4699_n16, DP_OP_36J6_126_4699_n15,
DP_OP_36J6_126_4699_n9, DP_OP_36J6_126_4699_n8,
DP_OP_36J6_126_4699_n7, DP_OP_36J6_126_4699_n6,
DP_OP_36J6_126_4699_n5, DP_OP_36J6_126_4699_n4,
DP_OP_36J6_126_4699_n3, DP_OP_36J6_126_4699_n2,
DP_OP_36J6_126_4699_n1, add_x_19_n302, add_x_19_n301, add_x_19_n300,
add_x_19_n299, add_x_19_n297, add_x_19_n291, add_x_19_n289,
add_x_19_n104, add_x_19_n103, add_x_19_n30, DP_OP_156J6_125_3370_n299,
DP_OP_156J6_125_3370_n298, DP_OP_156J6_125_3370_n297,
DP_OP_156J6_125_3370_n296, DP_OP_156J6_125_3370_n274,
DP_OP_156J6_125_3370_n272, DP_OP_156J6_125_3370_n270,
DP_OP_156J6_125_3370_n233, DP_OP_156J6_125_3370_n230,
DP_OP_156J6_125_3370_n229, DP_OP_156J6_125_3370_n228,
DP_OP_156J6_125_3370_n227, DP_OP_156J6_125_3370_n111,
DP_OP_156J6_125_3370_n108, DP_OP_156J6_125_3370_n16, n391, n392, n393,
n394, n395, n396, n397, n398, n399, n400, n401, n402, n403, n405,
n406, n407, n408, n409, n410, n411, n412, n413, n414, n415, n416,
n417, n423, n424, n425, n426, n427, n428, n429, n430, n431, n432,
n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, n443,
n444, n445, n446, n447, n448, n449, n450, n451, n452, n453, n454,
n455, n456, n457, n458, n459, n460, n462, n463, n464, n465, n466,
n467, n468, n469, n470, n471, n472, n473, n474, n475, n476, n477,
n478, n479, n480, n481, n482, n483, n484, n485, n486, n487, n488,
n489, n490, n491, n492, n493, n494, n495, n496, n497, n498, n499,
n500, n501, n502, n503, n504, n505, n506, n507, n508, n509, n510,
n511, n512, n513, n514, n515, n516, n517, n518, n519, n520, n521,
n522, n523, n524, n525, n526, n527, n528, n529, n530, n531, n532,
n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543,
n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, n554,
n555, n556, n557, n558, n559, n560, n561, n562, n563, n564, n565,
n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576,
n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587,
n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, n598,
n599, n600, n601, n602, n603, n604, n605, n606, n607, n608, n609,
n610, n611, n612, n613, n614, n615, n616, n617, n618, n619, n620,
n621, n622, n623, n624, n625, n626, n627, n628, n629, n630, n631,
n632, n633, n634, n635, n636, n637, n638, n639, n640, n641, n642,
n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, n653,
n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, n664,
n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675,
n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686,
n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n698,
n699, n700, n702, n703, n704, n705, n706, n707, n708, n709, n710,
n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721,
n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732,
n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, n743,
n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754,
n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, n765,
n766, n767, n768, n769, n770, n771, n772, n773, n774, n775, n776,
n777, n778, n779, n780, n781, n782, n783, n784, n785, n786, n787,
n788, n789, n790, n791, n792, n793, n794, n795, n796, n797, n798,
n799, n800, n801, n802, n803, n804, n805, n806, n807, n808, n809,
n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, n820,
n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831,
n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842,
n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, n853,
n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864,
n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, n875,
n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886,
n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897,
n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908,
n909, n910, n911, n912, n913, n914, n915, n916, n917, n918, n919,
n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, n930,
n931, n932, n933, n934, n935, n936, n937, n938, n939, n940, n941,
n942, n943, n944, n945, n946, n949, n950, n951, n952, n953, n954,
n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, n965,
n966, n967, n968, n969, n970, n971, n972, n973, n974, n975, n976,
n977, n978, n979, n980, n981, n982, n983, n984, n985, n986, n987,
n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998,
n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008,
n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018,
n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028,
n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038,
n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048,
n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058,
n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068,
n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078,
n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088,
n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1098, n1099,
n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109,
n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119,
n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129,
n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139,
n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149,
n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159,
n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169,
n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179,
n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189,
n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199,
n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209,
n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219,
n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229,
n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239,
n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249,
n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259,
n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269,
n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279,
n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289,
n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299,
n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309,
n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319,
n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329,
n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339,
n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370,
n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380,
n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390,
n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400,
n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410,
n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420,
n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470,
n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480,
n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490,
n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500,
n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510,
n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520,
n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530,
n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540,
n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550,
n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560,
n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570,
n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580,
n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590,
n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600,
n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610,
n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620,
n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630,
n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700,
n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710,
n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720,
n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730,
n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740,
n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750,
n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760,
n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770,
n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780,
n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790,
n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800,
n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810,
n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820,
n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830,
n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840,
n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850,
n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860,
n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870,
n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880,
n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890,
n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900,
n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910,
n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920,
n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930,
n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940,
n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950,
n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960,
n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970,
n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980,
n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990,
n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000,
n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010,
n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020,
n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030,
n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040,
n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050,
n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060,
n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070,
n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080,
n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090,
n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100,
n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110,
n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120,
n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130,
n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140,
n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150,
n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160,
n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170,
n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180,
n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190,
n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200,
n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210,
n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220,
n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230,
n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240,
n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250,
n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260,
n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270,
n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280,
n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290,
n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300,
n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310,
n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320,
n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330,
n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340,
n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350,
n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360,
n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370,
n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380,
n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390,
n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400,
n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410,
n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420,
n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430,
n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440,
n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450,
n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460,
n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470,
n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480,
n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490,
n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500,
n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510,
n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520,
n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530,
n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540,
n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550,
n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560,
n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570,
n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580,
n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590,
n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600,
n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610,
n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620,
n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630,
n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640,
n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650,
n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660,
n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670,
n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680,
n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690,
n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700,
n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710,
n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720,
n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730,
n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740,
n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750,
n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760,
n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770,
n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780,
n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790,
n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800,
n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810,
n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820,
n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830,
n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840,
n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850,
n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860,
n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870,
n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880,
n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890,
n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900,
n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910,
n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920,
n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930,
n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940,
n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950,
n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960,
n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970,
n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980,
n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990,
n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000,
n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010,
n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020,
n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030,
n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040,
n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050,
n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060,
n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070,
n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080,
n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090,
n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100,
n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110,
n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120,
n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130,
n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140,
n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150,
n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160,
n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170,
n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180,
n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190,
n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200,
n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210,
n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220,
n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230,
n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240,
n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250,
n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260,
n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270,
n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280,
n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290,
n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300,
n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310,
n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320,
n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330,
n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340,
n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350,
n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360,
n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370,
n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380,
n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390,
n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400,
n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410,
n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420,
n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430,
n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440,
n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450,
n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460,
n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470,
n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480,
n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490,
n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500,
n3501, n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510,
n3511, n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520,
n3521, n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530,
n3531, n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540,
n3541, n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550,
n3551, n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560,
n3561, n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570,
n3571, n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580,
n3581, n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590,
n3591, n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600,
n3601, n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610,
n3611, n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620,
n3621, n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630,
n3631, n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640,
n3641, n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650,
n3651, n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660,
n3661, n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670,
n3671, n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680,
n3681, n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690,
n3691, n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700,
n3701, n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710,
n3711, n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720,
n3721, n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730,
n3731, n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740,
n3741, n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750,
n3751, n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760,
n3761, n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770,
n3771, n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780,
n3781, n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790,
n3791, n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800,
n3801, n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810,
n3811, n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820,
n3821, n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830,
n3831, n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840,
n3841, n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850,
n3851, n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860,
n3861, n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870,
n3871, n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880,
n3881, n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890,
n3891, n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900,
n3901, n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910,
n3911, n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920,
n3921, n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930,
n3931, n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940,
n3941, n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950,
n3951, n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960,
n3961, n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970,
n3971, n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980,
n3981, n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990,
n3991, n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000,
n4001, n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010,
n4011, n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020,
n4021, n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030,
n4031, n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040,
n4041, n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050,
n4051, n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060,
n4061, n4062, n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070,
n4071, n4072, n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080,
n4081, n4082, n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090,
n4091, n4092, n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100,
n4101, n4102, n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110,
n4111, n4112, n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120,
n4121, n4122, n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130,
n4131, n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140,
n4141, n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150,
n4151, n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160,
n4161, n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170,
n4171, n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180,
n4181, n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190,
n4191, n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200,
n4201, n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210,
n4211, n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220,
n4221, n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230,
n4231, n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240,
n4241, n4242, n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250,
n4251, n4252, n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260,
n4261, n4262, n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270,
n4271, n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280,
n4281, n4282, n4283, n4284, n4285, n4286, n4287, n4288, n4289, n4290,
n4291, n4292, n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300,
n4301, n4302, n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310,
n4311, n4312, n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320,
n4321, n4322, n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330,
n4331, n4332, n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340,
n4341, n4342, n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350,
n4351, n4352, n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360,
n4361, n4362, n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370,
n4371, n4372, n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380,
n4381, n4382, n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390,
n4391, n4392, n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400,
n4401, n4402, n4403, n4404, n4405, n4406, n4411, n4412, n4413, n4414,
n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424,
n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434,
n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444,
n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454,
n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464,
n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474,
n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484,
n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494,
n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504,
n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514,
n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524,
n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534,
n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544,
n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554,
n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564,
n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574,
n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584,
n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594,
n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604,
n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614,
n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624,
n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634,
n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644,
n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654,
n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664,
n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674,
n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684,
n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694,
n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704,
n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714,
n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724,
n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734,
n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744,
n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754,
n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764,
n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774,
n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784,
n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794,
n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4804, n4805,
n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815,
n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825,
n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835,
n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845,
n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855,
n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865,
n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875,
n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885,
n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895,
n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905,
n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914, n4915,
n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925,
n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935,
n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945,
n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4955,
n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965,
n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975,
n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985,
n4986, n4987, n4988, n4989, n4991, n4992;
wire [12:0] P_Sgf;
wire [31:4] Op_MX;
wire [31:1] Op_MY;
wire [5:0] exp_oper_result;
wire [8:0] S_Oper_A_exp;
wire [23:1] Add_result;
wire [22:0] Sgf_normalized_result;
wire [3:1] FS_Module_state_reg;
wire [8:0] Exp_module_Data_S;
wire [10:3] Sgf_operation_EVEN1_S_B;
wire [17:15] Sgf_operation_EVEN1_Q_right;
wire [19:0] Sgf_operation_EVEN1_Q_left;
wire [9:6] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B;
wire [10:0] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left;
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(n378), .CK(clk), .RN(n4737), .Q(
FS_Module_state_reg[1]), .QN(n4747) );
DFFRX4TS FS_Module_state_reg_reg_3_ ( .D(n380), .CK(clk), .RN(n850), .Q(
FS_Module_state_reg[3]), .QN(n4746) );
DFFRX4TS Sel_A_Q_reg_0_ ( .D(n376), .CK(clk), .RN(n4797), .Q(FSM_selector_A),
.QN(n4781) );
DFFRX4TS R_1868 ( .D(n323), .CK(clk), .RN(n403), .Q(Op_MY[11]), .QN(n4874)
);
DFFRX4TS R_1720 ( .D(n321), .CK(clk), .RN(n4950), .Q(Op_MY[9]), .QN(n1488)
);
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n4742), .CK(clk), .RN(
n4940), .Q(P_Sgf[12]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n4743), .CK(clk), .RN(
n4939), .Q(P_Sgf[11]), .QN(n862) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n245), .CK(clk), .RN(
n4991), .Q(P_Sgf[7]) );
DFFRX4TS Sel_B_Q_reg_1_ ( .D(n235), .CK(clk), .RN(n846), .Q(
FSM_selector_B_1_) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n234), .CK(clk), .RN(n4945),
.Q(exp_oper_result[0]), .QN(n4783) );
DFFRX2TS Sel_C_Q_reg_0_ ( .D(n375), .CK(clk), .RN(n4946), .Q(FSM_selector_C),
.QN(n1507) );
DFFSX1TS R_5 ( .D(n4954), .CK(clk), .SN(n835), .Q(n4920) );
DFFRXLTS R_7 ( .D(n274), .CK(clk), .RN(n4940), .Q(n4919) );
DFFSX1TS R_11 ( .D(n4973), .CK(clk), .SN(n4466), .Q(n4918) );
DFFSX1TS R_14 ( .D(n4969), .CK(clk), .SN(n4650), .Q(n4917) );
DFFSX1TS R_17 ( .D(n4953), .CK(clk), .SN(n853), .Q(n4916) );
DFFSX1TS R_20 ( .D(n4951), .CK(clk), .SN(n834), .Q(n4915) );
DFFSX1TS R_23 ( .D(n4965), .CK(clk), .SN(n4468), .Q(n4914) );
DFFSX1TS R_26 ( .D(n4961), .CK(clk), .SN(n4650), .Q(n4913) );
DFFSX1TS R_29 ( .D(n4957), .CK(clk), .SN(n4650), .Q(n4912) );
DFFSX1TS R_32 ( .D(n4956), .CK(clk), .SN(n4940), .Q(n4911) );
DFFSX1TS R_35 ( .D(n4955), .CK(clk), .SN(n4940), .Q(n4910) );
DFFRXLTS R_37 ( .D(n268), .CK(clk), .RN(n4799), .Q(n4909) );
DFFRXLTS R_40 ( .D(n270), .CK(clk), .RN(n4799), .Q(n4908) );
DFFRXLTS R_43 ( .D(n269), .CK(clk), .RN(n4445), .Q(n4907) );
DFFRXLTS R_46 ( .D(n271), .CK(clk), .RN(n4466), .Q(n4906) );
DFFRXLTS R_49 ( .D(n272), .CK(clk), .RN(n4800), .Q(n4905) );
DFFRXLTS R_52 ( .D(n273), .CK(clk), .RN(n4940), .Q(n4904) );
DFFRXLTS R_55 ( .D(n267), .CK(clk), .RN(n4582), .Q(n4903) );
DFFRXLTS R_58 ( .D(n266), .CK(clk), .RN(n4799), .Q(n4902) );
DFFRXLTS R_85 ( .D(n265), .CK(clk), .RN(n4800), .Q(n4901) );
DFFRXLTS R_121 ( .D(n264), .CK(clk), .RN(n4799), .Q(n4900) );
DFFRX2TS R_263 ( .D(n3940), .CK(clk), .RN(n4802), .Q(n4928) );
DFFRXLTS R_361 ( .D(n263), .CK(clk), .RN(n4651), .Q(n4875) );
DFFRXLTS R_1884 ( .D(n330), .CK(clk), .RN(n4802), .Q(n4879) );
DFFRXLTS R_1896 ( .D(n312), .CK(clk), .RN(n848), .Q(n4922) );
DFFRXLTS R_459 ( .D(n324), .CK(clk), .RN(n4802), .Q(n4933) );
DFFRXLTS R_2004 ( .D(n356), .CK(clk), .RN(n846), .Q(n4883) );
DFFRXLTS R_1889 ( .D(n346), .CK(clk), .RN(n855), .Q(n4893) );
DFFRX4TS R_442 ( .D(n334), .CK(clk), .RN(n413), .Q(
DP_OP_153J6_122_5442_n1468), .QN(n4868) );
DFFRXLTS R_2086 ( .D(n315), .CK(clk), .RN(n403), .Q(n4885) );
DFFRXLTS R_1893 ( .D(n314), .CK(clk), .RN(n403), .Q(n4923) );
DFFRXLTS R_1726 ( .D(n327), .CK(clk), .RN(n4802), .Q(n4865) );
DFFRXLTS R_652 ( .D(n258), .CK(clk), .RN(n835), .Q(n4863) );
DFFRXLTS R_660 ( .D(n259), .CK(clk), .RN(n849), .Q(n4862) );
DFFRXLTS R_665 ( .D(n260), .CK(clk), .RN(n850), .Q(n4861) );
DFFRXLTS R_668 ( .D(n261), .CK(clk), .RN(n4467), .Q(n4860) );
DFFRXLTS R_671 ( .D(n262), .CK(clk), .RN(n4991), .Q(n4859) );
DFFRXLTS R_808 ( .D(n257), .CK(clk), .RN(n4446), .Q(n4856) );
DFFRXLTS R_969 ( .D(n225), .CK(clk), .RN(n4945), .Q(n4853) );
DFFSX1TS R_970 ( .D(n4938), .CK(clk), .SN(n411), .Q(n4852) );
DFFSX1TS R_1029 ( .D(n4989), .CK(clk), .SN(n856), .Q(n4851) );
DFFRXLTS R_1039 ( .D(n226), .CK(clk), .RN(n4946), .Q(n4850) );
DFFRXLTS R_1116 ( .D(n253), .CK(clk), .RN(n853), .Q(n4849) );
DFFSX4TS R_1244 ( .D(n4846), .CK(clk), .SN(n850), .Q(n4982) );
DFFRX2TS R_1201_RW_0 ( .D(n4936), .CK(clk), .RN(n4468), .Q(n4847) );
DFFSX2TS R_1200_RW_0 ( .D(n4776), .CK(clk), .SN(n4445), .Q(n4848) );
DFFRXLTS R_1600 ( .D(n4987), .CK(clk), .RN(n856), .Q(n4842) );
DFFSX2TS R_1609 ( .D(n4983), .CK(clk), .SN(n853), .Q(n4841) );
DFFRX2TS R_1980 ( .D(n319), .CK(clk), .RN(n403), .Q(n4869), .QN(n4782) );
DFFRXLTS R_1715 ( .D(n331), .CK(clk), .RN(n4941), .Q(n4884) );
DFFRX4TS R_1729 ( .D(n333), .CK(clk), .RN(n4945), .Q(
DP_OP_153J6_122_5442_n1467), .QN(n1492) );
DFFRX4TS R_1750 ( .D(n354), .CK(clk), .RN(n4796), .Q(
DP_OP_153J6_122_5442_n1517), .QN(n1498) );
DFFSX4TS R_1754 ( .D(n4986), .CK(clk), .SN(n836), .Q(n4832) );
DFFSX4TS R_1756 ( .D(n4935), .CK(clk), .SN(n846), .Q(n4831) );
DFFRXLTS R_1900 ( .D(n353), .CK(clk), .RN(n848), .Q(n4837) );
DFFRXLTS R_1830 ( .D(DP_OP_155J6_124_2038_n803), .CK(clk), .RN(n4560), .Q(
n4864) );
DFFRXLTS R_1846 ( .D(n4821), .CK(clk), .RN(n4797), .Q(n4929) );
DFFRX4TS R_1968 ( .D(n366), .CK(clk), .RN(n846), .Q(
DP_OP_153J6_122_5442_n1504) );
DFFRX4TS R_2017 ( .D(n4741), .CK(clk), .RN(n850), .Q(n4807) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n231), .CK(clk), .RN(n4945),
.Q(exp_oper_result[3]), .QN(n4757) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n230), .CK(clk), .RN(n4944),
.Q(exp_oper_result[4]), .QN(n4754) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n199),
.CK(clk), .RN(n4947), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n198),
.CK(clk), .RN(n4947), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n197),
.CK(clk), .RN(n4947), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n196),
.CK(clk), .RN(n4947), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n195),
.CK(clk), .RN(n4947), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n194),
.CK(clk), .RN(n4947), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n193),
.CK(clk), .RN(n4947), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n192),
.CK(clk), .RN(n4947), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n191),
.CK(clk), .RN(n4947), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n190),
.CK(clk), .RN(n4948), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n189),
.CK(clk), .RN(n4948), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n188),
.CK(clk), .RN(n4948), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n187),
.CK(clk), .RN(n4948), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n186),
.CK(clk), .RN(n4948), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n185),
.CK(clk), .RN(n4948), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n184),
.CK(clk), .RN(n4948), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n183),
.CK(clk), .RN(n4948), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n182),
.CK(clk), .RN(n4948), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n181),
.CK(clk), .RN(n4948), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n180),
.CK(clk), .RN(n867), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n179),
.CK(clk), .RN(n867), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n178),
.CK(clk), .RN(n867), .Q(final_result_ieee[22]) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n177),
.CK(clk), .RN(n867), .Q(final_result_ieee[23]) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n176),
.CK(clk), .RN(n867), .Q(final_result_ieee[24]) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n175),
.CK(clk), .RN(n867), .Q(final_result_ieee[25]) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n174),
.CK(clk), .RN(n867), .Q(final_result_ieee[26]) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n173),
.CK(clk), .RN(n867), .Q(final_result_ieee[27]) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n172),
.CK(clk), .RN(n867), .Q(final_result_ieee[28]) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n171),
.CK(clk), .RN(n867), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n200),
.CK(clk), .RN(n4947), .Q(final_result_ieee[0]) );
DFFRX1TS R_995 ( .D(n328), .CK(clk), .RN(n4945), .QN(n4882) );
DFFRX1TS R_467 ( .D(n327), .CK(clk), .RN(n4945), .QN(n4881) );
DFFRXLTS R_414 ( .D(n324), .CK(clk), .RN(n4802), .QN(n4880) );
DFFRX1TS R_282 ( .D(n4821), .CK(clk), .RN(n4941), .QN(n4895) );
DFFRXLTS R_1877 ( .D(n317), .CK(clk), .RN(n403), .Q(Op_MY[5]), .QN(n4835) );
DFFRX1TS R_432 ( .D(n358), .CK(clk), .RN(n4950), .QN(n4888) );
DFFRX1TS R_1740 ( .D(n320), .CK(clk), .RN(n403), .QN(n4870) );
DFFRX1TS R_275 ( .D(n356), .CK(clk), .RN(n4950), .QN(n4891) );
DFFRXLTS R_1808 ( .D(n348), .CK(clk), .RN(n4560), .Q(Op_MX[4]), .QN(n4897)
);
DFFSX1TS R_1811 ( .D(n4952), .CK(clk), .SN(n4561), .Q(n4827) );
DFFRXLTS R_2323 ( .D(n363), .CK(clk), .RN(n848), .Q(Op_MX[19]), .QN(n4839)
);
DFFRXLTS R_1699 ( .D(DP_OP_155J6_124_2038_n801), .CK(clk), .RN(n4942), .Q(
n4934), .QN(n4896) );
DFFRXLTS R_1812 ( .D(n310), .CK(clk), .RN(n4561), .Q(n4826) );
DFFRXLTS R_2101 ( .D(n316), .CK(clk), .RN(n403), .Q(Op_MY[4]), .QN(n4886) );
DFFRXLTS R_490 ( .D(n326), .CK(clk), .RN(n4802), .Q(n4924), .QN(n4866) );
DFFRXLTS R_2200 ( .D(n228), .CK(clk), .RN(n4946), .Q(n4804) );
DFFSX2TS R_1813 ( .D(n4202), .CK(clk), .SN(n4561), .Q(n4825) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n300), .CK(clk), .RN(n4943),
.Q(Add_result[9]), .QN(n4764) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n299), .CK(clk), .RN(n4943),
.Q(Add_result[10]), .QN(n4763) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n298), .CK(clk), .RN(n4943),
.Q(Add_result[11]), .QN(n4762) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n297), .CK(clk), .RN(n4943),
.Q(Add_result[12]), .QN(n4761) );
DFFRX2TS R_1825 ( .D(n350), .CK(clk), .RN(n4801), .Q(n4926) );
DFFRX2TS R_2120 ( .D(n357), .CK(clk), .RN(n4950), .Q(n4932) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n238), .CK(clk), .RN(
n4991), .Q(P_Sgf[0]), .QN(n4753) );
DFFSX1TS R_1326 ( .D(Sgf_operation_Result_13_), .CK(clk), .SN(n850), .Q(
n4845) );
DFFSX1TS R_1856 ( .D(n4963), .CK(clk), .SN(n4797), .Q(n4819) );
DFFSX2TS R_1855 ( .D(n4964), .CK(clk), .SN(n4797), .Q(n4820) );
DFFSX1TS R_1857 ( .D(n4962), .CK(clk), .SN(n408), .Q(n4818) );
DFFSX1TS R_1804 ( .D(n4978), .CK(clk), .SN(n4796), .Q(n4829) );
DFFSX1TS R_1859 ( .D(n4971), .CK(clk), .SN(n888), .Q(n4816) );
DFFSX1TS R_1862 ( .D(n4975), .CK(clk), .SN(n888), .Q(n4813) );
DFFSX1TS R_1882 ( .D(n4967), .CK(clk), .SN(n4796), .Q(n4810) );
DFFSX2TS R_1803 ( .D(n4979), .CK(clk), .SN(n888), .Q(n4830) );
DFFSX2TS R_1821 ( .D(n4960), .CK(clk), .SN(n4796), .Q(n4824) );
DFFSX2TS R_1861 ( .D(n4976), .CK(clk), .SN(n848), .Q(n4814) );
DFFSX2TS R_1881 ( .D(n4968), .CK(clk), .SN(n408), .Q(n4811) );
DFFSX1TS R_1805 ( .D(n4977), .CK(clk), .SN(n407), .Q(n4828) );
DFFSX1TS R_1823 ( .D(n4958), .CK(clk), .SN(n4798), .Q(n4822) );
DFFSX1TS R_1860 ( .D(n4970), .CK(clk), .SN(n4798), .Q(n4815) );
DFFSX1TS R_1863 ( .D(n4974), .CK(clk), .SN(n4797), .Q(n4812) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n223), .CK(clk),
.RN(n4561), .Q(Sgf_normalized_result[21]), .QN(n4790) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n213), .CK(clk),
.RN(n4798), .Q(Sgf_normalized_result[11]), .QN(n4792) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n209), .CK(clk),
.RN(n856), .Q(Sgf_normalized_result[7]), .QN(n4789) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n211), .CK(clk),
.RN(n4944), .Q(Sgf_normalized_result[9]), .QN(n4791) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n214), .CK(clk),
.RN(n888), .Q(Sgf_normalized_result[12]), .QN(n4779) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n206), .CK(clk),
.RN(n856), .Q(Sgf_normalized_result[4]), .QN(n4793) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n210), .CK(clk),
.RN(n4946), .Q(Sgf_normalized_result[8]), .QN(n4788) );
DFFRX1TS add_x_23_R_1592_RW_0 ( .D(n4724), .CK(clk), .RN(n4445), .Q(n4734)
);
DFFSX4TS add_x_23_R_1655 ( .D(n4739), .CK(clk), .SN(n4738), .Q(n4736) );
DFFSX1TS add_x_23_R_1453_RW_2 ( .D(n1504), .CK(clk), .SN(n4651), .Q(n4730)
);
DFFSX4TS add_x_23_R_1514_RW_1 ( .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left_8_), .CK(clk), .SN(
n4651), .Q(n4732) );
DFFSX4TS add_x_23_R_1586 ( .D(add_x_23_n23), .CK(clk), .SN(n4446), .Q(n4733)
);
DFFSX1TS add_x_23_R_1349_RW_2 ( .D(add_x_23_n21), .CK(clk), .SN(n4445), .Q(
n4727) );
DFFSX1TS add_x_23_R_1387 ( .D(n4722), .CK(clk), .SN(n849), .Q(n4728) );
DFFRX4TS DP_OP_154J6_123_2038_R_2325 ( .D(n363), .CK(clk), .RN(n4649), .Q(
DP_OP_154J6_123_2038_n705) );
DFFSX4TS DP_OP_154J6_123_2038_R_2311 ( .D(n4711), .CK(clk), .SN(n4714), .Q(
DP_OP_154J6_123_2038_n717), .QN(n813) );
DFFRX2TS DP_OP_154J6_123_2038_R_2230 ( .D(n4706), .CK(clk), .RN(n4714), .Q(
DP_OP_154J6_123_2038_n626) );
DFFSX4TS DP_OP_154J6_123_2038_R_2229 ( .D(n4705), .CK(clk), .SN(n4714), .Q(
n4668) );
DFFRX4TS DP_OP_154J6_123_2038_R_441 ( .D(n334), .CK(clk), .RN(n4560), .Q(
DP_OP_154J6_123_2038_n682) );
DFFSX4TS DP_OP_154J6_123_2038_R_2222 ( .D(n4703), .CK(clk), .SN(n4713), .Q(
DP_OP_154J6_123_2038_n628) );
DFFRX4TS DP_OP_154J6_123_2038_R_2221 ( .D(n328), .CK(clk), .RN(n4713), .Q(
DP_OP_154J6_123_2038_n782) );
DFFRX2TS DP_OP_154J6_123_2038_R_2218 ( .D(n4702), .CK(clk), .RN(n4715), .Q(
DP_OP_154J6_123_2038_n611) );
DFFSX4TS DP_OP_154J6_123_2038_R_2212 ( .D(n4719), .CK(clk), .SN(n4713), .Q(
DP_OP_154J6_123_2038_n386) );
DFFSX4TS DP_OP_154J6_123_2038_R_2211 ( .D(n4676), .CK(clk), .SN(n4715), .Q(
DP_OP_154J6_123_2038_n385) );
DFFRX4TS DP_OP_154J6_123_2038_R_2139 ( .D(n4821), .CK(clk), .RN(n4718), .Q(
n4684), .QN(n4710) );
DFFRX4TS DP_OP_154J6_123_2038_R_2123 ( .D(n332), .CK(clk), .RN(n4713), .Q(
n821), .QN(n668) );
DFFRX4TS DP_OP_154J6_123_2038_R_2122 ( .D(n357), .CK(clk), .RN(n3971), .Q(
DP_OP_154J6_123_2038_n792) );
DFFRX4TS DP_OP_154J6_123_2038_R_2112 ( .D(n4693), .CK(clk), .RN(n4716), .Q(
DP_OP_154J6_123_2038_n612) );
DFFSX4TS DP_OP_154J6_123_2038_R_2135 ( .D(n4694), .CK(clk), .SN(n4715), .Q(
DP_OP_154J6_123_2038_n632), .QN(n677) );
DFFRX4TS DP_OP_154J6_123_2038_R_2015 ( .D(n4691), .CK(clk), .RN(n4714), .Q(
DP_OP_154J6_123_2038_n616) );
DFFRX4TS DP_OP_154J6_123_2038_R_1977 ( .D(n4689), .CK(clk), .RN(n4715), .Q(
DP_OP_154J6_123_2038_n617) );
DFFSX4TS DP_OP_154J6_123_2038_R_2014 ( .D(n4690), .CK(clk), .SN(n4713), .Q(
DP_OP_154J6_123_2038_n636), .QN(n676) );
DFFRX4TS DP_OP_154J6_123_2038_R_1979 ( .D(n358), .CK(clk), .RN(n4716), .Q(
DP_OP_154J6_123_2038_n793) );
DFFSX4TS DP_OP_154J6_123_2038_R_2217 ( .D(n4688), .CK(clk), .SN(n4717), .Q(
n4667) );
DFFSX4TS DP_OP_154J6_123_2038_R_1969 ( .D(n4687), .CK(clk), .SN(n4649), .Q(
DP_OP_154J6_123_2038_n718), .QN(n814) );
DFFRX4TS DP_OP_154J6_123_2038_R_1970 ( .D(n366), .CK(clk), .RN(n4718), .Q(
DP_OP_154J6_123_2038_n687) );
DFFSX4TS DP_OP_154J6_123_2038_R_2070 ( .D(n4686), .CK(clk), .SN(n4715), .Q(
DP_OP_154J6_123_2038_n714), .QN(n703) );
DFFSX4TS DP_OP_154J6_123_2038_R_1844 ( .D(n4681), .CK(clk), .SN(n4715), .Q(
DP_OP_154J6_123_2038_n378) );
DFFSX4TS DP_OP_154J6_123_2038_R_1820 ( .D(n4674), .CK(clk), .SN(n854), .Q(
n4672) );
DFFSX4TS DP_OP_154J6_123_2038_R_1732 ( .D(n4679), .CK(clk), .SN(n4713), .Q(
DP_OP_154J6_123_2038_n716), .QN(n816) );
DFFRX4TS DP_OP_154J6_123_2038_R_1731 ( .D(n331), .CK(clk), .RN(n4716), .Q(
DP_OP_154J6_123_2038_n685) );
DFFSX4TS DP_OP_154J6_123_2038_R_1734 ( .D(n4675), .CK(clk), .SN(n4713), .Q(
DP_OP_154J6_123_2038_n392) );
DFFRX2TS DP_OP_154J6_123_2038_R_2310 ( .D(n330), .CK(clk), .RN(n4716), .Q(
DP_OP_154J6_123_2038_n686) );
DFFRX4TS DP_OP_154J6_123_2038_R_447 ( .D(n359), .CK(clk), .RN(n4717), .Q(
DP_OP_154J6_123_2038_n794) );
DFFRX4TS DP_OP_154J6_123_2038_R_439 ( .D(n4673), .CK(clk), .RN(n4942), .Q(
DP_OP_154J6_123_2038_n700) );
DFFSX4TS DP_OP_154J6_123_2038_R_2228 ( .D(n4670), .CK(clk), .SN(n4714), .Q(
DP_OP_154J6_123_2038_n630) );
DFFSX4TS DP_OP_154J6_123_2038_R_2216 ( .D(n4666), .CK(clk), .SN(n4714), .Q(
DP_OP_154J6_123_2038_n631), .QN(n4685) );
DFFSX4TS DP_OP_154J6_123_2038_R_2118 ( .D(n4665), .CK(clk), .SN(n4718), .Q(
DP_OP_154J6_123_2038_n634), .QN(n4709) );
DFFRX4TS DP_OP_154J6_123_2038_R_261 ( .D(n360), .CK(clk), .RN(n4717), .Q(
DP_OP_154J6_123_2038_n795) );
DFFSX4TS DP_OP_154J6_123_2038_R_2071 ( .D(n4664), .CK(clk), .SN(n4718), .Q(
DP_OP_154J6_123_2038_n719) );
DFFRX4TS DP_OP_154J6_123_2038_R_181 ( .D(n365), .CK(clk), .RN(n4717), .Q(
DP_OP_154J6_123_2038_n693) );
DFFSX4TS DP_OP_154J6_123_2038_R_438 ( .D(n4663), .CK(clk), .SN(n4649), .Q(
DP_OP_154J6_123_2038_n720), .QN(n695) );
DFFRX4TS DP_OP_154J6_123_2038_R_173 ( .D(n364), .CK(clk), .RN(n4649), .Q(
DP_OP_154J6_123_2038_n699) );
DFFRXLTS DP_OP_153J6_122_5442_R_1297_RW_2 ( .D(n3872), .CK(clk), .RN(n4651),
.Q(n4601) );
DFFSX1TS DP_OP_153J6_122_5442_R_1536_RW_0 ( .D(DP_OP_153J6_122_5442_n7),
.CK(clk), .SN(n4650), .Q(n4612) );
DFFRXLTS DP_OP_153J6_122_5442_R_1535_RW_0 ( .D(DP_OP_153J6_122_5442_n63),
.CK(clk), .RN(n4738), .Q(n4611) );
DFFSX1TS DP_OP_153J6_122_5442_R_1337_RW_2 ( .D(1'b0), .CK(clk), .SN(n4651),
.Q(n4602) );
DFFSX1TS DP_OP_153J6_122_5442_R_1533_RW_1 ( .D(DP_OP_153J6_122_5442_n5),
.CK(clk), .SN(n4651), .Q(n4610) );
DFFRXLTS DP_OP_153J6_122_5442_R_2326 ( .D(n4625), .CK(clk), .RN(n4649), .Q(
n4614) );
DFFSX4TS DP_OP_153J6_122_5442_R_2327 ( .D(n4647), .CK(clk), .SN(n4717), .Q(
DP_OP_153J6_122_5442_n870) );
DFFRX4TS DP_OP_153J6_122_5442_R_2305 ( .D(n4645), .CK(clk), .RN(n4648), .Q(
Sgf_operation_EVEN1_result_A_adder_3_), .QN(n1479) );
DFFSX4TS DP_OP_153J6_122_5442_R_2245 ( .D(n4644), .CK(clk), .SN(n4992), .Q(
DP_OP_153J6_122_5442_n1065) );
DFFSX4TS DP_OP_153J6_122_5442_R_2239 ( .D(n4643), .CK(clk), .SN(n4992), .Q(
DP_OP_153J6_122_5442_n1104), .QN(n4655) );
DFFSX4TS DP_OP_153J6_122_5442_R_2206 ( .D(n4597), .CK(clk), .SN(n4718), .Q(
n4584) );
DFFSX4TS DP_OP_153J6_122_5442_R_2202 ( .D(n4641), .CK(clk), .SN(n4992), .Q(
DP_OP_153J6_122_5442_n1063) );
DFFRX4TS DP_OP_153J6_122_5442_R_2140 ( .D(n4639), .CK(clk), .RN(n4802), .Q(
n4587) );
DFFRX4TS DP_OP_153J6_122_5442_R_2134 ( .D(n4638), .CK(clk), .RN(n4648), .QN(
n4656) );
DFFRX4TS DP_OP_153J6_122_5442_R_2127 ( .D(n4637), .CK(clk), .RN(n4558), .Q(
DP_OP_153J6_122_5442_n1376) );
DFFRX4TS DP_OP_153J6_122_5442_R_2106 ( .D(n4631), .CK(clk), .RN(n4649), .QN(
n1487) );
DFFRX4TS DP_OP_153J6_122_5442_R_2105 ( .D(n4618), .CK(clk), .RN(n4718), .Q(
n4596) );
DFFSX4TS DP_OP_153J6_122_5442_R_2107 ( .D(n4636), .CK(clk), .SN(n848), .Q(
n715) );
DFFSX4TS DP_OP_153J6_122_5442_R_2085 ( .D(n4633), .CK(clk), .SN(n4251), .QN(
n4659) );
DFFSX4TS DP_OP_153J6_122_5442_R_2075 ( .D(n4588), .CK(clk), .SN(n415), .Q(
DP_OP_153J6_122_5442_n1183) );
DFFRX4TS DP_OP_153J6_122_5442_R_2076 ( .D(n4632), .CK(clk), .RN(n4649), .Q(
DP_OP_153J6_122_5442_n1181) );
DFFRX2TS DP_OP_153J6_122_5442_R_2012 ( .D(n322), .CK(clk), .RN(n4944), .Q(
DP_OP_153J6_122_5442_n1479) );
DFFSX4TS DP_OP_153J6_122_5442_R_2011 ( .D(n4630), .CK(clk), .SN(n4798), .Q(
DP_OP_153J6_122_5442_n792) );
DFFRX4TS DP_OP_153J6_122_5442_R_2003 ( .D(n332), .CK(clk), .RN(n4944), .Q(
DP_OP_153J6_122_5442_n1466) );
DFFRX4TS DP_OP_153J6_122_5442_R_2002 ( .D(n320), .CK(clk), .RN(n4945), .Q(
DP_OP_153J6_122_5442_n1477), .QN(n4661) );
DFFRX1TS DP_OP_153J6_122_5442_R_2001 ( .D(n4629), .CK(clk), .RN(n4944), .Q(
DP_OP_153J6_122_5442_n827) );
DFFRX4TS DP_OP_153J6_122_5442_R_1995 ( .D(n353), .CK(clk), .RN(n4718), .Q(
DP_OP_153J6_122_5442_n1516) );
DFFRX4TS DP_OP_153J6_122_5442_R_1994 ( .D(n365), .CK(clk), .RN(n4649), .Q(
DP_OP_153J6_122_5442_n1503) );
DFFRX4TS DP_OP_153J6_122_5442_R_1996 ( .D(n4627), .CK(clk), .RN(n4718), .QN(
n4662) );
DFFSX4TS DP_OP_153J6_122_5442_R_1992 ( .D(n4594), .CK(clk), .SN(n4649), .Q(
DP_OP_153J6_122_5442_n1190) );
DFFSX4TS DP_OP_153J6_122_5442_R_1990 ( .D(n4617), .CK(clk), .SN(n4251), .Q(
DP_OP_153J6_122_5442_n1191) );
DFFSX4TS DP_OP_153J6_122_5442_R_2203 ( .D(n4593), .CK(clk), .SN(n4251), .Q(
n4585) );
DFFRX4TS DP_OP_153J6_122_5442_R_1886 ( .D(n4624), .CK(clk), .RN(n4945), .Q(
n4586), .QN(n4657) );
DFFRX4TS DP_OP_153J6_122_5442_R_1873 ( .D(n4623), .CK(clk), .RN(n4648), .Q(
n4615), .QN(n1481) );
DFFSX4TS DP_OP_153J6_122_5442_R_1866 ( .D(n4652), .CK(clk), .SN(n4251), .Q(
DP_OP_153J6_122_5442_n1184) );
DFFSX4TS DP_OP_153J6_122_5442_R_2074 ( .D(n4621), .CK(clk), .SN(n4717), .QN(
n1482) );
DFFRX4TS DP_OP_153J6_122_5442_R_1718 ( .D(n319), .CK(clk), .RN(n4941), .QN(
n4660) );
DFFRX4TS DP_OP_153J6_122_5442_R_1719 ( .D(n331), .CK(clk), .RN(n4941), .Q(
DP_OP_153J6_122_5442_n778), .QN(n4653) );
DFFSX1TS DP_OP_153J6_122_5442_R_1289_RW_3 ( .D(DP_OP_153J6_122_5442_n4),
.CK(clk), .SN(n4466), .Q(n4600) );
DFFSX1TS DP_OP_153J6_122_5442_R_1596_RW_0 ( .D(n4658), .CK(clk), .SN(n4738),
.Q(n4613) );
DFFSX1TS DP_OP_153J6_122_5442_R_1460_RW_1 ( .D(DP_OP_153J6_122_5442_n54),
.CK(clk), .SN(n4940), .Q(n4608) );
DFFSX2TS DP_OP_153J6_122_5442_R_1461 ( .D(DP_OP_153J6_122_5442_n6), .CK(clk),
.SN(n4445), .Q(n4609) );
DFFSX1TS DP_OP_153J6_122_5442_R_1447 ( .D(DP_OP_153J6_122_5442_n36), .CK(clk), .SN(n4650), .Q(n4607) );
DFFSX1TS DP_OP_153J6_122_5442_R_1438 ( .D(DP_OP_153J6_122_5442_n41), .CK(clk), .SN(n4468), .Q(n4606) );
DFFSX1TS DP_OP_153J6_122_5442_R_1437 ( .D(DP_OP_153J6_122_5442_n40), .CK(clk), .SN(n4650), .Q(n4605) );
DFFSX4TS DP_OP_153J6_122_5442_R_1009 ( .D(n4599), .CK(clk), .SN(n4992), .Q(
DP_OP_153J6_122_5442_n1106), .QN(n709) );
DFFSX4TS DP_OP_153J6_122_5442_R_2144 ( .D(n4598), .CK(clk), .SN(n4992), .Q(
DP_OP_153J6_122_5442_n1105), .QN(n736) );
DFFRX4TS DP_OP_153J6_122_5442_R_645 ( .D(n363), .CK(clk), .RN(n4648), .Q(
DP_OP_153J6_122_5442_n1501) );
DFFSX4TS DP_OP_153J6_122_5442_R_646 ( .D(n4595), .CK(clk), .SN(n836), .Q(
n4583) );
DFFSX4TS DP_OP_153J6_122_5442_R_498 ( .D(n4592), .CK(clk), .SN(n4718), .Q(
DP_OP_153J6_122_5442_n1207) );
DFFSX4TS DP_OP_153J6_122_5442_R_568 ( .D(n4591), .CK(clk), .SN(n4992), .Q(
DP_OP_153J6_122_5442_n1122), .QN(n719) );
DFFRX4TS DP_OP_153J6_122_5442_R_417 ( .D(n324), .CK(clk), .RN(n866), .Q(
DP_OP_153J6_122_5442_n1458) );
DFFRX4TS DP_OP_153J6_122_5442_R_410 ( .D(DP_OP_155J6_124_2038_n795), .CK(clk), .RN(n4648), .Q(DP_OP_153J6_122_5442_n1514), .QN(n723) );
DFFSX4TS DP_OP_153J6_122_5442_R_2145 ( .D(n4589), .CK(clk), .SN(n4950), .Q(
DP_OP_153J6_122_5442_n1098), .QN(n4654) );
DFFRX4TS add_x_55_R_1454_RW_2 ( .D(add_x_55_n39), .CK(clk), .RN(n4582), .Q(
n4574) );
DFFSX4TS add_x_55_R_1455_RW_2 ( .D(add_x_55_n38), .CK(clk), .SN(n4467), .Q(
n4575) );
DFFRX4TS add_x_55_R_1456_RW_2 ( .D(add_x_55_n54), .CK(clk), .RN(n4447), .Q(
n4576) );
DFFSX4TS add_x_55_R_1457_RW_2 ( .D(add_x_55_n6), .CK(clk), .SN(n4737), .Q(
n4577) );
DFFSX4TS add_x_55_R_1598 ( .D(add_x_55_n46), .CK(clk), .SN(n4447), .Q(n4581)
);
DFFSX4TS add_x_55_R_1459_RW_0 ( .D(n752), .CK(clk), .SN(n4737), .Q(n4578) );
DFFSX4TS add_x_55_R_1458 ( .D(add_x_55_n21), .CK(clk), .SN(n4446), .QN(n4579) );
DFFSX4TS add_x_55_R_1379_RW_1 ( .D(add_x_55_n29), .CK(clk), .SN(n4582), .Q(
n4572) );
DFFSX4TS add_x_55_R_1380_RW_0 ( .D(n1500), .CK(clk), .SN(n4737), .Q(n4573)
);
DFFRX4TS DP_OP_155J6_124_2038_R_2314 ( .D(n4554), .CK(clk), .RN(n4560), .Q(
DP_OP_155J6_124_2038_n700) );
DFFSX4TS DP_OP_155J6_124_2038_R_2303 ( .D(n4551), .CK(clk), .SN(n410), .QN(
n4564) );
DFFSX4TS DP_OP_155J6_124_2038_R_2312 ( .D(n4546), .CK(clk), .SN(n4942), .Q(
n4547), .QN(n726) );
DFFSX2TS DP_OP_155J6_124_2038_R_2258 ( .D(n4550), .CK(clk), .SN(n415), .QN(
n1489) );
DFFSX4TS DP_OP_155J6_124_2038_R_2248 ( .D(n4505), .CK(clk), .SN(n4251), .Q(
DP_OP_155J6_124_2038_n380), .QN(n4569) );
DFFRX4TS DP_OP_155J6_124_2038_R_2242 ( .D(DP_OP_153J6_122_5442_n1475), .CK(
clk), .RN(n4562), .Q(DP_OP_155J6_124_2038_n782) );
DFFSX4TS R_2422 ( .D(n4541), .CK(clk), .SN(n836), .Q(
DP_OP_155J6_124_2038_n730), .QN(n812) );
DFFRX4TS DP_OP_155J6_124_2038_R_2198 ( .D(n4539), .CK(clk), .RN(n4561), .Q(
DP_OP_155J6_124_2038_n705) );
DFFSX4TS DP_OP_155J6_124_2038_R_2143 ( .D(n4526), .CK(clk), .SN(n836), .Q(
n4482) );
DFFSX4TS DP_OP_155J6_124_2038_R_2225 ( .D(n4535), .CK(clk), .SN(n3971), .Q(
n4478), .QN(n4567) );
DFFSX4TS DP_OP_155J6_124_2038_R_2302 ( .D(n4502), .CK(clk), .SN(n836), .Q(
n4491) );
DFFSX4TS DP_OP_155J6_124_2038_R_2226 ( .D(n4529), .CK(clk), .SN(n836), .Q(
DP_OP_155J6_124_2038_n635) );
DFFRX4TS DP_OP_155J6_124_2038_R_2103 ( .D(n316), .CK(clk), .RN(n4561), .Q(
DP_OP_155J6_124_2038_n792) );
DFFSX4TS DP_OP_155J6_124_2038_R_2132 ( .D(n4487), .CK(clk), .SN(n4560), .Q(
n4488), .QN(n4568) );
DFFRX4TS DP_OP_155J6_124_2038_R_2090 ( .D(n315), .CK(clk), .RN(n854), .Q(
DP_OP_155J6_124_2038_n791), .QN(n728) );
DFFSX4TS DP_OP_155J6_124_2038_R_2083 ( .D(n4524), .CK(clk), .SN(n4558), .QN(
n430) );
DFFRX4TS DP_OP_155J6_124_2038_R_2080 ( .D(n4522), .CK(clk), .RN(n4558), .Q(
DP_OP_155J6_124_2038_n618) );
DFFSX4TS DP_OP_155J6_124_2038_R_2234 ( .D(n4503), .CK(clk), .SN(n4942), .QN(
n4530) );
DFFSX4TS DP_OP_155J6_124_2038_R_2066 ( .D(n4521), .CK(clk), .SN(n410), .QN(
n4563) );
DFFRX4TS DP_OP_155J6_124_2038_R_1988 ( .D(n4517), .CK(clk), .RN(n4558), .Q(
DP_OP_155J6_124_2038_n613) );
DFFSX4TS DP_OP_155J6_124_2038_R_2098 ( .D(n4484), .CK(clk), .SN(n407), .Q(
n4479), .QN(n4552) );
DFFRX4TS DP_OP_155J6_124_2038_R_1982 ( .D(n319), .CK(clk), .RN(n854), .Q(
DP_OP_155J6_124_2038_n783) );
DFFSX4TS DP_OP_155J6_124_2038_R_2320 ( .D(n4514), .CK(clk), .SN(n4251), .Q(
DP_OP_155J6_124_2038_n640) );
DFFSX4TS DP_OP_155J6_124_2038_R_1954 ( .D(n4494), .CK(clk), .SN(n4992), .Q(
n4489) );
DFFRX4TS DP_OP_155J6_124_2038_R_1955 ( .D(n4511), .CK(clk), .RN(n846), .Q(
DP_OP_155J6_124_2038_n390), .QN(n4566) );
DFFRX4TS DP_OP_155J6_124_2038_R_1949 ( .D(n4510), .CK(clk), .RN(n4796), .Q(
n4481), .QN(n1486) );
DFFRX4TS DP_OP_155J6_124_2038_R_1898 ( .D(n312), .CK(clk), .RN(n4558), .Q(
DP_OP_155J6_124_2038_n788) );
DFFRX4TS DP_OP_155J6_124_2038_R_1895 ( .D(n314), .CK(clk), .RN(n4561), .Q(
DP_OP_155J6_124_2038_n790) );
DFFSX4TS DP_OP_155J6_124_2038_R_1890 ( .D(n4507), .CK(clk), .SN(n4558), .QN(
n4565) );
DFFSX4TS DP_OP_155J6_124_2038_R_2097 ( .D(n4504), .CK(clk), .SN(n4560), .Q(
DP_OP_155J6_124_2038_n721), .QN(n811) );
DFFRX4TS DP_OP_155J6_124_2038_R_2317 ( .D(n348), .CK(clk), .RN(n4560), .Q(
DP_OP_155J6_124_2038_n804) );
DFFSX4TS DP_OP_155J6_124_2038_R_1952 ( .D(n4500), .CK(clk), .SN(n4796), .Q(
n4480) );
DFFSX4TS DP_OP_155J6_124_2038_R_2065 ( .D(n4490), .CK(clk), .SN(n4798), .Q(
n4486), .QN(n4532) );
DFFSX4TS DP_OP_155J6_124_2038_R_2313 ( .D(n4498), .CK(clk), .SN(n855), .Q(
DP_OP_155J6_124_2038_n728), .QN(n4533) );
DFFRX4TS DP_OP_155J6_124_2038_R_1749 ( .D(n354), .CK(clk), .RN(n4562), .Q(
DP_OP_155J6_124_2038_n798) );
DFFSX4TS DP_OP_155J6_124_2038_R_2207 ( .D(n4496), .CK(clk), .SN(n855), .Q(
DP_OP_155J6_124_2038_n724) );
DFFRX4TS DP_OP_155J6_124_2038_R_1744 ( .D(n320), .CK(clk), .RN(n4562), .Q(
DP_OP_155J6_124_2038_n784) );
DFFSX2TS DP_OP_155J6_124_2038_R_2316 ( .D(n4495), .CK(clk), .SN(n4558), .QN(
n712) );
DFFRX4TS DP_OP_155J6_124_2038_R_1739 ( .D(n4834), .CK(clk), .RN(n4558), .Q(
DP_OP_155J6_124_2038_n789) );
DFFSX4TS DP_OP_155J6_124_2038_R_2256 ( .D(n4493), .CK(clk), .SN(n866), .Q(
DP_OP_155J6_124_2038_n723), .QN(n4499) );
DFFSX4TS DP_OP_155J6_124_2038_R_1953 ( .D(n4492), .CK(clk), .SN(n4944), .Q(
n4485) );
CMPR32X2TS DP_OP_36J6_126_4699_U3 ( .A(n4475), .B(n4476), .C(n4477), .CO(
DP_OP_36J6_126_4699_n2), .S(Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_36J6_126_4699_U4 ( .A(DP_OP_36J6_126_4699_n16), .B(
S_Oper_A_exp[6]), .C(DP_OP_36J6_126_4699_n4), .CO(
DP_OP_36J6_126_4699_n3), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_36J6_126_4699_U5 ( .A(DP_OP_36J6_126_4699_n17), .B(
S_Oper_A_exp[5]), .C(DP_OP_36J6_126_4699_n5), .CO(
DP_OP_36J6_126_4699_n4), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_36J6_126_4699_U7 ( .A(DP_OP_36J6_126_4699_n19), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J6_126_4699_n7), .CO(
DP_OP_36J6_126_4699_n6), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_36J6_126_4699_U8 ( .A(DP_OP_36J6_126_4699_n20), .B(
S_Oper_A_exp[2]), .C(DP_OP_36J6_126_4699_n8), .CO(
DP_OP_36J6_126_4699_n7), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_36J6_126_4699_U2 ( .A(n4473), .B(n4474), .C(
DP_OP_36J6_126_4699_n2), .CO(DP_OP_36J6_126_4699_n1), .S(
Exp_module_Data_S[8]) );
DFFRX1TS DP_OP_36J6_126_4699_R_1852 ( .D(DP_OP_36J6_126_4699_n3), .CK(clk),
.RN(n846), .Q(n4477) );
DFFSX4TS DP_OP_36J6_126_4699_R_1851 ( .D(S_Oper_A_exp[7]), .CK(clk), .SN(
n847), .Q(n4476) );
DFFSX4TS DP_OP_36J6_126_4699_R_1850 ( .D(DP_OP_36J6_126_4699_n15), .CK(clk),
.SN(n847), .Q(n4475) );
DFFSX1TS DP_OP_36J6_126_4699_R_1321 ( .D(S_Oper_A_exp[8]), .CK(clk), .SN(
n848), .Q(n4474) );
DFFSX1TS DP_OP_36J6_126_4699_R_1320 ( .D(n796), .CK(clk), .SN(n411), .Q(
n4473) );
DFFSX1TS DP_OP_36J6_126_4699_R_1168 ( .D(FSM_exp_operation_A_S), .CK(clk),
.SN(n4718), .Q(n4472) );
DFFSX2TS add_x_19_R_1537_RW_0 ( .D(Sgf_operation_EVEN1_S_B[3]), .CK(clk),
.SN(n4468), .Q(n4460) );
DFFSX2TS add_x_19_R_1538_RW_0 ( .D(Sgf_operation_EVEN1_Q_right[15]), .CK(clk), .SN(n4991), .Q(n4461) );
DFFSX2TS add_x_19_R_1610 ( .D(Sgf_operation_EVEN1_S_B[4]), .CK(clk), .SN(
n834), .Q(n4464) );
DFFSX2TS add_x_19_R_1611 ( .D(n798), .CK(clk), .SN(n835), .Q(n4465) );
DFFSX2TS add_x_19_R_1230 ( .D(add_x_19_n302), .CK(clk), .SN(n4738), .QN(
n4470) );
DFFSX1TS add_x_19_R_1299_RW_2 ( .D(add_x_19_n30), .CK(clk), .SN(n4468), .Q(
n4455) );
DFFSX1TS add_x_19_R_1164_RW_5 ( .D(add_x_19_n289), .CK(clk), .SN(n834), .QN(
n4469) );
DFFSX1TS add_x_19_R_1607_RW_0 ( .D(add_x_19_n300), .CK(clk), .SN(n834), .Q(
n4463) );
DFFRX1TS add_x_19_R_1334_RW_2 ( .D(add_x_19_n300), .CK(clk), .RN(n849), .Q(
n4456) );
DFFRXLTS add_x_19_R_1304_RW_2 ( .D(Sgf_operation_EVEN1_S_B[8]), .CK(clk),
.RN(n835), .QN(n4471) );
DFFRX2TS add_x_19_R_1389_RW_1 ( .D(add_x_19_n299), .CK(clk), .RN(n835), .Q(
n4459) );
DFFSX2TS add_x_19_R_1606 ( .D(add_x_19_n299), .CK(clk), .SN(n4939), .Q(n4462) );
DFFRXLTS add_x_19_R_583_RW_3 ( .D(Sgf_operation_EVEN1_Q_left[13]), .CK(clk),
.RN(n849), .Q(n4452) );
DFFSX1TS add_x_19_R_1257 ( .D(Sgf_operation_EVEN1_S_B[8]), .CK(clk), .SN(
n4468), .Q(n4454) );
DFFRXLTS add_x_19_R_1031 ( .D(add_x_19_n104), .CK(clk), .RN(n4650), .Q(n4453) );
DFFSX1TS add_x_19_R_539 ( .D(Sgf_operation_EVEN1_Q_left[13]), .CK(clk), .SN(
n835), .Q(n4451) );
DFFSX1TS add_x_19_R_73 ( .D(Sgf_operation_EVEN1_Q_left[15]), .CK(clk), .SN(
n4650), .Q(n4450) );
DFFSX1TS add_x_19_R_67 ( .D(Sgf_operation_EVEN1_Q_left[14]), .CK(clk), .SN(
n834), .Q(n4449) );
DFFSX1TS DP_OP_156J6_125_3370_R_1384_RW_3 ( .D(DP_OP_156J6_125_3370_n299),
.CK(clk), .SN(n4466), .Q(n4432) );
DFFSX1TS DP_OP_156J6_125_3370_R_1588 ( .D(DP_OP_156J6_125_3370_n230), .CK(
clk), .SN(n4738), .Q(n4442) );
DFFSX2TS DP_OP_156J6_125_3370_R_1603_RW_0 ( .D(n4448), .CK(clk), .SN(n4467),
.Q(n4443) );
DFFSX1TS DP_OP_156J6_125_3370_R_1450 ( .D(DP_OP_156J6_125_3370_n16), .CK(clk), .SN(n4800), .Q(n4435) );
DFFRX4TS DP_OP_156J6_125_3370_R_1510_RW_1 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .CK(clk), .RN(
n4467), .Q(n4436) );
DFFSX2TS DP_OP_156J6_125_3370_R_1582_RW_0 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]), .CK(clk), .SN(n4467), .Q(n4441) );
DFFSX1TS DP_OP_156J6_125_3370_R_1241_RW_1 ( .D(DP_OP_156J6_125_3370_n270),
.CK(clk), .SN(n4447), .Q(n4425) );
DFFSX1TS DP_OP_156J6_125_3370_R_1225_RW_3 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .CK(clk), .SN(
n4582), .Q(n4423) );
DFFSX2TS DP_OP_156J6_125_3370_R_1604_RW_0 ( .D(DP_OP_156J6_125_3370_n108),
.CK(clk), .SN(n4738), .Q(n4444) );
DFFRXLTS DP_OP_156J6_125_3370_R_1175_RW_2 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .CK(clk), .RN(
n4737), .Q(n4417) );
DFFSX4TS DP_OP_156J6_125_3370_R_1580 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .CK(clk), .SN(
n4467), .Q(n4439) );
DFFRXLTS DP_OP_156J6_125_3370_R_1270_RW_2 ( .D(DP_OP_156J6_125_3370_n228),
.CK(clk), .RN(n4447), .Q(n4428) );
DFFSX1TS DP_OP_156J6_125_3370_R_1212_RW_1 ( .D(DP_OP_156J6_125_3370_n227),
.CK(clk), .SN(n4737), .Q(n4422) );
DFFSX1TS DP_OP_156J6_125_3370_R_1041_RW_1 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .CK(clk), .SN(
n4466), .Q(n4414) );
DFFSX4TS DP_OP_156J6_125_3370_R_1373_RW_1 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .CK(clk), .SN(
n4582), .Q(n4430) );
DFFSX1TS DP_OP_156J6_125_3370_R_1294 ( .D(DP_OP_156J6_125_3370_n228), .CK(
clk), .SN(n4445), .Q(n4429) );
DFFSX1TS DP_OP_156J6_125_3370_R_1259 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .CK(clk), .SN(
n4738), .Q(n4427) );
DFFSX1TS DP_OP_156J6_125_3370_R_1192 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]), .CK(clk), .SN(n4651), .Q(n4418) );
DFFRX2TS DP_OP_154J6_123_2038_R_2247 ( .D(n4707), .CK(clk), .RN(n4713), .Q(
n4677) );
DFFRX2TS DP_OP_156J6_125_3370_R_1385_RW_0 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]), .CK(clk), .RN(n4447), .Q(n4433) );
DFFSX4TS DP_OP_154J6_123_2038_R_2319 ( .D(n4712), .CK(clk), .SN(n4714), .Q(
DP_OP_154J6_123_2038_n361) );
DFFSX4TS DP_OP_155J6_124_2038_R_2249 ( .D(n4536), .CK(clk), .SN(n4251), .Q(
DP_OP_155J6_124_2038_n388) );
DFFRX4TS DP_OP_155J6_124_2038_R_2231 ( .D(n317), .CK(clk), .RN(n854), .Q(
DP_OP_155J6_124_2038_n793) );
DFFRX4TS DP_OP_156J6_125_3370_R_1511_RW_1 ( .D(DP_OP_156J6_125_3370_n274),
.CK(clk), .RN(n4447), .Q(n4437) );
DFFRX2TS DP_OP_153J6_122_5442_R_2000 ( .D(n4628), .CK(clk), .RN(n4941), .Q(
DP_OP_153J6_122_5442_n829) );
DFFRX2TS add_x_23_R_1302_RW_3 ( .D(add_x_23_n4), .CK(clk), .RN(n4738), .Q(
n4726) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n202), .CK(clk),
.RN(n857), .Q(Sgf_normalized_result[0]) );
DFFRX4TS DP_OP_154J6_123_2038_R_2006 ( .D(n356), .CK(clk), .RN(n3971), .Q(
DP_OP_154J6_123_2038_n791) );
DFFSX4TS DP_OP_156J6_125_3370_R_1581 ( .D(DP_OP_156J6_125_3370_n297), .CK(
clk), .SN(n4582), .Q(n4440) );
DFFSX4TS DP_OP_154J6_123_2038_R_1727 ( .D(n4678), .CK(clk), .SN(n4713), .Q(
DP_OP_154J6_123_2038_n379), .QN(n744) );
DFFSX4TS DP_OP_156J6_125_3370_R_1374_RW_1 ( .D(DP_OP_156J6_125_3370_n272),
.CK(clk), .SN(n4447), .Q(n4431) );
DFFSX4TS DP_OP_153J6_122_5442_R_2093 ( .D(n4634), .CK(clk), .SN(n848), .Q(
DP_OP_153J6_122_5442_n1150) );
DFFSX4TS DP_OP_155J6_124_2038_R_2307 ( .D(n4501), .CK(clk), .SN(n855), .Q(
DP_OP_155J6_124_2038_n641) );
DFFRX4TS DP_OP_153J6_122_5442_R_419 ( .D(n312), .CK(clk), .RN(n4714), .Q(
DP_OP_153J6_122_5442_n1469) );
DFFRXLTS R_1339 ( .D(n227), .CK(clk), .RN(n854), .Q(n4843) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n309), .CK(clk), .RN(n4946),
.QN(n4984) );
DFFRXLTS R_2219 ( .D(n328), .CK(clk), .RN(n4944), .Q(n4925) );
DFFRXLTS R_1998 ( .D(n320), .CK(clk), .RN(n403), .Q(n4930) );
DFFRXLTS R_1947 ( .D(n352), .CK(clk), .RN(n848), .Q(n4833) );
DFFRXLTS R_293 ( .D(n331), .CK(clk), .RN(n4802), .Q(n4794) );
DFFRXLTS R_1999 ( .D(n332), .CK(clk), .RN(n846), .Q(n4927) );
DFFRXLTS R_918 ( .D(n254), .CK(clk), .RN(n4800), .Q(n4854) );
DFFRXLTS R_798 ( .D(n256), .CK(clk), .RN(n853), .Q(n4857) );
DFFRXLTS R_822 ( .D(n255), .CK(clk), .RN(n4939), .Q(n4855) );
DFFRHQX1TS R_463 ( .D(n333), .CK(clk), .RN(n857), .Q(n4413) );
DFFRHQX1TS R_406 ( .D(DP_OP_155J6_124_2038_n795), .CK(clk), .RN(n857), .Q(
n4931) );
DFFRHQX1TS R_2240 ( .D(DP_OP_153J6_122_5442_n1475), .CK(clk), .RN(n866), .Q(
Op_MY[6]) );
DFFRHQX1TS R_1814 ( .D(n353), .CK(clk), .RN(n856), .Q(n4412) );
DFFRHQX1TS R_284 ( .D(n330), .CK(clk), .RN(n857), .Q(n4877) );
DFFRHQX1TS R_182 ( .D(n346), .CK(clk), .RN(n856), .Q(n4411) );
DFFRHQX1TS R_510 ( .D(n360), .CK(clk), .RN(n866), .Q(Op_MX[16]) );
DFFRHQX4TS DP_OP_155J6_124_2038_R_2091_IP ( .D(DP_OP_155J6_124_2038_n801),
.CK(clk), .RN(n856), .Q(n4523) );
DFFSRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n221), .CK(clk),
.SN(1'b1), .RN(n857), .Q(Sgf_normalized_result[19]) );
DFFRHQX2TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n168),
.CK(clk), .RN(n857), .Q(final_result_ieee[31]) );
DFFRX4TS R_1824 ( .D(n362), .CK(clk), .RN(n856), .Q(Op_MX[18]), .QN(
DP_OP_154J6_123_2038_n722) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n224), .CK(clk),
.RN(n4946), .Q(Sgf_normalized_result[22]), .QN(n4777) );
DFFRXLTS R_286 ( .D(n332), .CK(clk), .RN(n4945), .Q(n4878) );
DFFRXLTS R_483 ( .D(n314), .CK(clk), .RN(n403), .QN(n4873) );
DFFRX1TS R_1709 ( .D(n3844), .CK(clk), .RN(n4950), .Q(n4898), .QN(n4858) );
DFFSX4TS DP_OP_154J6_123_2038_R_2138 ( .D(n4682), .CK(clk), .SN(n4649), .Q(
n4683), .QN(n722) );
DFFRX4TS DP_OP_154J6_123_2038_R_2246 ( .D(n333), .CK(clk), .RN(n4716), .Q(
DP_OP_154J6_123_2038_n683) );
DFFRX4TS DP_OP_154J6_123_2038_R_2119 ( .D(n4695), .CK(clk), .RN(n4715), .Q(
DP_OP_154J6_123_2038_n605) );
DFFRX4TS DP_OP_155J6_124_2038_R_2309 ( .D(n348), .CK(clk), .RN(n4561), .Q(
n4518) );
DFFRX4TS DP_OP_155J6_124_2038_R_1870 ( .D(n323), .CK(clk), .RN(n4562), .Q(
DP_OP_155J6_124_2038_n787) );
DFFSX4TS DP_OP_155J6_124_2038_R_2133 ( .D(n4537), .CK(clk), .SN(n414), .QN(
n1494) );
DFFSX4TS DP_OP_155J6_124_2038_R_2252 ( .D(n4549), .CK(clk), .SN(n3971), .Q(
n4483) );
DFFRX4TS DP_OP_156J6_125_3370_R_1208_RW_0 ( .D(n1469), .CK(clk), .RN(n4446),
.Q(n4420) );
DFFRX4TS DP_OP_155J6_124_2038_R_2008 ( .D(n349), .CK(clk), .RN(n408), .Q(
DP_OP_155J6_124_2038_n805) );
DFFRX4TS DP_OP_156J6_125_3370_R_1463_RW_0 ( .D(DP_OP_156J6_125_3370_n230),
.CK(clk), .RN(n4799), .QN(n716) );
DFFRX4TS DP_OP_153J6_122_5442_R_1396 ( .D(DP_OP_153J6_122_5442_n8), .CK(clk),
.RN(n4651), .Q(n4604) );
DFFRX4TS DP_OP_156J6_125_3370_R_1207_RW_0 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .CK(clk), .RN(
n4446), .Q(n4419) );
DFFSX4TS add_x_23_R_1388 ( .D(n1505), .CK(clk), .SN(n849), .Q(n4729) );
DFFRX4TS DP_OP_155J6_124_2038_R_2088 ( .D(n4525), .CK(clk), .RN(n854), .Q(
DP_OP_155J6_124_2038_n616) );
DFFRX2TS DP_OP_154J6_123_2038_R_2213 ( .D(n4700), .CK(clk), .RN(n4714), .Q(
DP_OP_154J6_123_2038_n380) );
DFFRX2TS DP_OP_155J6_124_2038_R_2109 ( .D(n4531), .CK(clk), .RN(n4561), .Q(
DP_OP_155J6_124_2038_n703), .QN(n823) );
DFFSX4TS DP_OP_153J6_122_5442_R_2205 ( .D(n4642), .CK(clk), .SN(n4802), .Q(
DP_OP_153J6_122_5442_n1202) );
DFFSX4TS DP_OP_155J6_124_2038_R_2238 ( .D(n4545), .CK(clk), .SN(n415), .QN(
n1490) );
DFFSX4TS DP_OP_153J6_122_5442_R_2146 ( .D(n4635), .CK(clk), .SN(n4950), .Q(
DP_OP_153J6_122_5442_n1099) );
DFFRX4TS DP_OP_154J6_123_2038_R_465 ( .D(n4671), .CK(clk), .RN(n4713), .Q(
n4669) );
DFFRX4TS DP_OP_154J6_123_2038_R_2210 ( .D(n4680), .CK(clk), .RN(n4714), .Q(
DP_OP_154J6_123_2038_n388) );
DFFRX4TS DP_OP_154J6_123_2038_R_2223 ( .D(n4704), .CK(clk), .RN(n4716), .Q(
DP_OP_154J6_123_2038_n624) );
DFFRX4TS DP_OP_154J6_123_2038_R_2150 ( .D(n4698), .CK(clk), .RN(n4716), .Q(
DP_OP_154J6_123_2038_n620) );
DFFRX4TS DP_OP_155J6_124_2038_R_1962 ( .D(n4513), .CK(clk), .RN(n4562), .Q(
DP_OP_155J6_124_2038_n623), .QN(n730) );
DFFSX4TS add_x_23_R_1593_RW_0 ( .D(n4723), .CK(clk), .SN(n4466), .Q(n4735)
);
DFFSX4TS DP_OP_156J6_125_3370_R_1512_RW_0 ( .D(DP_OP_156J6_125_3370_n298),
.CK(clk), .SN(n4939), .Q(n4438) );
DFFSX2TS DP_OP_156J6_125_3370_R_1386_RW_3 ( .D(DP_OP_156J6_125_3370_n229),
.CK(clk), .SN(n4651), .Q(n4434) );
DFFRX4TS DP_OP_155J6_124_2038_R_2116 ( .D(n4534), .CK(clk), .RN(n4942), .Q(
DP_OP_155J6_124_2038_n617) );
DFFRX2TS R_2018 ( .D(n4981), .CK(clk), .RN(n4737), .Q(n4806) );
DFFSX2TS DP_OP_154J6_123_2038_R_2214 ( .D(n4701), .CK(clk), .SN(n4715), .Q(
DP_OP_154J6_123_2038_n387) );
DFFSX2TS DP_OP_153J6_122_5442_R_1395 ( .D(DP_OP_153J6_122_5442_n72), .CK(clk), .SN(n4466), .Q(n4603) );
DFFRX2TS DP_OP_155J6_124_2038_R_2096 ( .D(n4527), .CK(clk), .RN(n854), .Q(
DP_OP_155J6_124_2038_n715) );
DFFRX2TS DP_OP_154J6_123_2038_R_2072 ( .D(n4692), .CK(clk), .RN(n4715), .Q(
DP_OP_154J6_123_2038_n695) );
DFFRX4TS DP_OP_155J6_124_2038_R_1985 ( .D(n4516), .CK(clk), .RN(n855), .Q(
DP_OP_155J6_124_2038_n699), .QN(n808) );
DFFRX4TS DP_OP_153J6_122_5442_R_1836 ( .D(n4619), .CK(clk), .RN(n4648), .Q(
DP_OP_153J6_122_5442_n838) );
DFFSX4TS R_2016 ( .D(n797), .CK(clk), .SN(n4737), .Q(n4808) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(clk), .RN(
n888), .Q(Op_MX[28]) );
DFFRX1TS R_174 ( .D(DP_OP_155J6_124_2038_n803), .CK(clk), .RN(n4942), .QN(
n4840) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n288), .CK(clk), .RN(n855),
.Q(Add_result[21]) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n287), .CK(clk), .RN(n855),
.Q(Add_result[22]), .QN(n4758) );
DFFRX4TS DP_OP_153J6_122_5442_R_2104 ( .D(n4622), .CK(clk), .RN(n4648), .Q(
DP_OP_153J6_122_5442_n1182) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n291), .CK(clk), .RN(n4943),
.Q(Add_result[18]), .QN(n4751) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n292), .CK(clk), .RN(n4943),
.Q(Add_result[17]), .QN(n4752) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n294), .CK(clk), .RN(n4943),
.Q(Add_result[15]), .QN(n4785) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n295), .CK(clk), .RN(n4943),
.Q(Add_result[14]), .QN(n4786) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n293), .CK(clk), .RN(n4943),
.Q(Add_result[16]), .QN(n4784) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n296), .CK(clk), .RN(n4943),
.Q(Add_result[13]), .QN(n4760) );
DFFRX4TS DP_OP_155J6_124_2038_R_1960 ( .D(n4512), .CK(clk), .RN(n4560), .Q(
DP_OP_155J6_124_2038_n717) );
DFFRX4TS R_505 ( .D(n359), .CK(clk), .RN(n888), .Q(n4889) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n301), .CK(clk), .RN(n4949),
.Q(Add_result[8]), .QN(n4765) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n302), .CK(clk), .RN(n4949),
.Q(Add_result[7]), .QN(n4766) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n305), .CK(clk), .RN(n4949),
.Q(Add_result[4]), .QN(n4769) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n286), .CK(clk), .RN(n4949),
.Q(Add_result[23]) );
DFFSX2TS add_x_55_R_1597 ( .D(add_x_55_n47), .CK(clk), .SN(n4582), .Q(n4580)
);
DFFRX4TS DP_OP_156J6_125_3370_R_1240_RW_0 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .CK(clk), .RN(
n4799), .Q(n4424) );
DFFRX4TS DP_OP_155J6_124_2038_R_2208 ( .D(n4540), .CK(clk), .RN(n4562), .Q(
DP_OP_155J6_124_2038_n710) );
DFFRX4TS DP_OP_155J6_124_2038_R_1722 ( .D(n321), .CK(clk), .RN(n4562), .Q(
DP_OP_155J6_124_2038_n785) );
DFFRX4TS DP_OP_155J6_124_2038_R_1747 ( .D(n4497), .CK(clk), .RN(n4562), .Q(
DP_OP_155J6_124_2038_n698) );
DFFRX4TS DP_OP_155J6_124_2038_R_1879 ( .D(n4506), .CK(clk), .RN(n4562), .Q(
DP_OP_155J6_124_2038_n625) );
DFFSRHQX4TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n308), .CK(clk), .SN(1'b1),
.RN(n866), .Q(Add_result[1]) );
DFFSRHQX2TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n170),
.CK(clk), .SN(1'b1), .RN(n856), .Q(final_result_ieee[30]) );
DFFRX4TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n285), .CK(clk), .RN(
n4946), .QN(n753) );
DFFRX4TS DP_OP_155J6_124_2038_R_2227 ( .D(n4542), .CK(clk), .RN(n4798), .Q(
DP_OP_155J6_124_2038_n631) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n205), .CK(clk),
.RN(n4798), .Q(Sgf_normalized_result[3]), .QN(n4773) );
DFFRX4TS R_1976 ( .D(n358), .CK(clk), .RN(n4251), .Q(n4890) );
DFFRX4TS R_477 ( .D(n315), .CK(clk), .RN(n4251), .Q(n4805) );
DFFSX2TS add_x_23_R_1301_RW_3 ( .D(add_x_23_n50), .CK(clk), .SN(n4446), .Q(
n4725) );
DFFRX1TS add_x_23_R_1513_RW_1 ( .D(n1279), .CK(clk), .RN(n4466), .Q(n4731)
);
DFFSX4TS DP_OP_155J6_124_2038_R_2235 ( .D(n4544), .CK(clk), .SN(n414), .QN(
n1491) );
DFFRX4TS DP_OP_154J6_123_2038_R_2136 ( .D(n4697), .CK(clk), .RN(n4717), .Q(
DP_OP_154J6_123_2038_n600) );
DFFRXLTS add_x_19_R_1342_RW_0 ( .D(n824), .CK(clk), .RN(n834), .Q(n4457) );
DFFSHQX8TS DP_OP_154J6_123_2038_R_2151 ( .D(n4699), .CK(clk), .SN(n4715),
.Q(n809) );
DFFSHQX8TS DP_OP_154J6_123_2038_R_2149 ( .D(n4696), .CK(clk), .SN(n414), .Q(
n802) );
DFFSHQX8TS DP_OP_154J6_123_2038_R_2254 ( .D(n4708), .CK(clk), .SN(n4797),
.Q(n800) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n306), .CK(clk), .RN(n4801),
.Q(Add_result[3]), .QN(n4770) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n242), .CK(clk), .RN(
n4991), .Q(P_Sgf[4]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n246), .CK(clk), .RN(
n853), .Q(P_Sgf[8]) );
DFFRX4TS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(clk),
.RN(n4797), .Q(zero_flag), .QN(n4741) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(clk), .RN(
n406), .Q(Op_MX[29]), .QN(n4894) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n4775), .CK(clk), .RN(
n4991), .Q(P_Sgf[1]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n243), .CK(clk), .RN(
n4991), .Q(P_Sgf[5]) );
DFFRX2TS R_1899 ( .D(n365), .CK(clk), .RN(n848), .Q(Op_MX[21]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n229), .CK(clk), .RN(n4946),
.Q(exp_oper_result[5]), .QN(n4755) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n222), .CK(clk),
.RN(n4946), .Q(Sgf_normalized_result[20]), .QN(n4778) );
DFFSHQX4TS DP_OP_155J6_124_2038_R_2322 ( .D(n4557), .CK(clk), .SN(n866), .Q(
n4519) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n4745), .CK(clk), .RN(
n4991), .Q(P_Sgf[6]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n241), .CK(clk), .RN(
n4991), .Q(P_Sgf[3]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n240), .CK(clk), .RN(
n4991), .Q(P_Sgf[2]) );
DFFRX1TS R_1706 ( .D(n352), .CK(clk), .RN(n4801), .QN(n4838) );
DFFRX1TS R_1746 ( .D(n354), .CK(clk), .RN(n3971), .QN(n4836) );
DFFRX1TS R_1972 ( .D(n349), .CK(clk), .RN(n4950), .Q(Op_MX[5]), .QN(n4899)
);
DFFRX1TS R_412 ( .D(n312), .CK(clk), .RN(n846), .QN(n4887) );
DFFRX1TS R_1327 ( .D(n251), .CK(clk), .RN(n853), .Q(n4844) );
DFFRHQX4TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(clk), .RN(
n866), .Q(Op_MY[24]) );
DFFSHQX8TS DP_OP_154J6_123_2038_R_2324 ( .D(n4595), .CK(clk), .SN(n4717),
.Q(n706) );
DFFSHQX8TS R_2421 ( .D(n4515), .CK(clk), .SN(n407), .Q(n693) );
DFFSHQX8TS DP_OP_155J6_124_2038_R_2250 ( .D(n4503), .CK(clk), .SN(n855), .Q(
n684) );
DFFSHQX8TS DP_OP_155J6_124_2038_R_2306 ( .D(n4509), .CK(clk), .SN(n4942),
.Q(n683) );
DFFRHQX8TS R_2328 ( .D(n355), .CK(clk), .RN(n3971), .Q(n681) );
DFFRX4TS R_2418 ( .D(n674), .CK(clk), .RN(n410), .Q(n1867) );
DFFRX2TS R_2420 ( .D(n672), .CK(clk), .RN(n413), .Q(n1889) );
DFFRX2TS R_2423 ( .D(n671), .CK(clk), .RN(n406), .Q(n1913) );
DFFSX2TS R_2432 ( .D(n1502), .CK(clk), .SN(n4940), .Q(n665) );
DFFSX2TS R_2434 ( .D(n4985), .CK(clk), .SN(n854), .Q(n663) );
DFFSX2TS R_2435 ( .D(n1502), .CK(clk), .SN(n834), .Q(n662), .QN(n661) );
DFFSX2TS R_2436 ( .D(Exp_module_Data_S[6]), .CK(clk), .SN(n4561), .Q(n660)
);
DFFSX2TS R_2438 ( .D(n4937), .CK(clk), .SN(n4582), .Q(n658) );
DFFRX2TS R_2439 ( .D(Sgf_operation_EVEN1_S_B[6]), .CK(clk), .RN(n849), .Q(
n657) );
DFFSX2TS R_2440 ( .D(Sgf_operation_EVEN1_S_B[7]), .CK(clk), .SN(n850), .Q(
n656) );
DFFSX2TS R_2441 ( .D(Sgf_operation_EVEN1_S_B[5]), .CK(clk), .SN(n835), .Q(
n655) );
DFFSX2TS R_2442 ( .D(add_x_19_n301), .CK(clk), .SN(n834), .Q(n654), .QN(n653) );
DFFSX2TS R_2443 ( .D(Sgf_operation_EVEN1_S_B[9]), .CK(clk), .SN(n834), .Q(
n652) );
DFFSX2TS R_2444 ( .D(add_x_19_n103), .CK(clk), .SN(n4468), .Q(n651), .QN(
n650) );
DFFSX2TS R_2445 ( .D(Sgf_operation_EVEN1_Q_left[7]), .CK(clk), .SN(n4467),
.Q(n649) );
DFFSX2TS R_2446 ( .D(Sgf_operation_EVEN1_Q_left[8]), .CK(clk), .SN(n4446),
.Q(n648) );
DFFSX2TS R_2447 ( .D(add_x_19_n297), .CK(clk), .SN(n835), .Q(n647) );
DFFSX2TS R_2448 ( .D(Sgf_operation_EVEN1_Q_left[6]), .CK(clk), .SN(n4446),
.Q(n646) );
DFFSX2TS R_2449 ( .D(n433), .CK(clk), .SN(n4800), .Q(n645), .QN(n644) );
DFFSX2TS R_2450 ( .D(Sgf_operation_EVEN1_Q_left[0]), .CK(clk), .SN(n4445),
.Q(n643) );
DFFSX2TS R_2451 ( .D(Sgf_operation_EVEN1_Q_left[3]), .CK(clk), .SN(n4447),
.Q(n642) );
DFFSX2TS R_2452 ( .D(Sgf_operation_EVEN1_Q_left[4]), .CK(clk), .SN(n4738),
.Q(n641) );
DFFSX2TS R_2453 ( .D(DP_OP_156J6_125_3370_n233), .CK(clk), .SN(n4445), .Q(
n640) );
DFFRX2TS R_2454 ( .D(DP_OP_156J6_125_3370_n298), .CK(clk), .RN(n849), .Q(
n639) );
DFFSX2TS R_2455 ( .D(Sgf_operation_EVEN1_Q_left[2]), .CK(clk), .SN(n850),
.Q(n638) );
DFFSX2TS R_2456 ( .D(DP_OP_153J6_122_5442_n35), .CK(clk), .SN(n4445), .Q(
n637) );
DFFSX2TS R_2457 ( .D(Sgf_operation_EVEN1_Q_left[5]), .CK(clk), .SN(n4651),
.Q(n636) );
DFFSX2TS R_2458 ( .D(Sgf_operation_EVEN1_S_B[10]), .CK(clk), .SN(n4468), .Q(
n635) );
DFFSX2TS R_2459 ( .D(DP_OP_156J6_125_3370_n111), .CK(clk), .SN(n4466), .Q(
n634) );
DFFSX4TS R_2460 ( .D(n1279), .CK(clk), .SN(n4445), .Q(n633) );
DFFSX2TS R_2461 ( .D(Sgf_operation_EVEN1_Q_left[10]), .CK(clk), .SN(n4468),
.Q(n632) );
DFFRX2TS R_2462 ( .D(DP_OP_156J6_125_3370_n296), .CK(clk), .RN(n4467), .Q(
n631), .QN(n630) );
DFFSX2TS R_2463 ( .D(Sgf_operation_EVEN1_Q_left[19]), .CK(clk), .SN(n4582),
.Q(n629), .QN(n628) );
DFFSX2TS R_2464 ( .D(Sgf_operation_EVEN1_Q_left[1]), .CK(clk), .SN(n4466),
.Q(n627) );
DFFSX2TS R_2465 ( .D(n4938), .CK(clk), .SN(n853), .Q(n626) );
DFFSX2TS R_2466 ( .D(add_x_19_n291), .CK(clk), .SN(n4446), .Q(n625), .QN(
n624) );
DFFSX2TS R_2467 ( .D(n805), .CK(clk), .SN(n4650), .Q(n623) );
DFFSX2TS R_2468 ( .D(Sgf_operation_EVEN1_Q_left[9]), .CK(clk), .SN(n4467),
.Q(n622) );
DFFSX2TS R_2469 ( .D(Sgf_operation_EVEN1_Q_left[11]), .CK(clk), .SN(n849),
.Q(n621), .QN(n620) );
DFFSX2TS R_2470 ( .D(Sgf_operation_EVEN1_Q_right[17]), .CK(clk), .SN(n835),
.Q(n619) );
DFFSHQX8TS DP_OP_155J6_124_2038_R_2237 ( .D(n4508), .CK(clk), .SN(n866), .Q(
n618) );
ADDFHX2TS DP_OP_36J6_126_4699_U9 ( .A(DP_OP_36J6_126_4699_n21), .B(
S_Oper_A_exp[1]), .CI(DP_OP_36J6_126_4699_n9), .CO(
DP_OP_36J6_126_4699_n8), .S(Exp_module_Data_S[1]) );
ADDFHX2TS DP_OP_36J6_126_4699_U6 ( .A(DP_OP_36J6_126_4699_n18), .B(
S_Oper_A_exp[4]), .CI(DP_OP_36J6_126_4699_n6), .CO(
DP_OP_36J6_126_4699_n5), .S(Exp_module_Data_S[4]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n212), .CK(clk),
.RN(n4796), .Q(Sgf_normalized_result[10]), .QN(n4780) );
DFFRX1TS R_2419 ( .D(n673), .CK(clk), .RN(n415), .Q(n2036) );
DFFSX4TS R_2430 ( .D(n442), .CK(clk), .SN(n4939), .Q(n667) );
DFFSX4TS R_2431 ( .D(n442), .CK(clk), .SN(n4738), .Q(n666) );
DFFRX4TS R_1835 ( .D(n364), .CK(clk), .RN(n847), .Q(Op_MX[20]), .QN(n4740)
);
DFFRX4TS R_1737 ( .D(n4834), .CK(clk), .RN(n847), .Q(Op_MY[1]), .QN(n4872)
);
DFFRX4TS R_2424 ( .D(n670), .CK(clk), .RN(n847), .Q(n1888) );
DFFRX4TS DP_OP_154J6_123_2038_R_1848 ( .D(n4821), .CK(clk), .RN(n4717), .Q(
DP_OP_154J6_123_2038_n312), .QN(n4721) );
DFFSX4TS R_2437 ( .D(n4988), .CK(clk), .SN(n847), .Q(n659) );
ADDFHX2TS DP_OP_36J6_126_4699_U10 ( .A(S_Oper_A_exp[0]), .B(n797), .CI(
DP_OP_36J6_126_4699_n22), .CO(DP_OP_36J6_126_4699_n9), .S(
Exp_module_Data_S[0]) );
DFFRHQX4TS R_2010 ( .D(n322), .CK(clk), .RN(n4941), .Q(n698) );
DFFRX2TS DP_OP_155J6_124_2038_R_2142 ( .D(n4538), .CK(clk), .RN(n4562), .Q(
DP_OP_155J6_124_2038_n632) );
DFFRX1TS R_2425 ( .D(n669), .CK(clk), .RN(n847), .Q(n1868) );
DFFRX2TS DP_OP_155J6_124_2038_R_2251 ( .D(n4548), .CK(clk), .RN(n407), .Q(
DP_OP_155J6_124_2038_n379) );
DFFRX2TS DP_OP_153J6_122_5442_R_2147 ( .D(n4640), .CK(clk), .RN(n4716), .Q(
DP_OP_153J6_122_5442_n1097), .QN(n431) );
DFFSHQX4TS R_2417 ( .D(n4543), .CK(clk), .SN(n410), .Q(n696) );
DFFRX2TS DP_OP_153J6_122_5442_R_1717 ( .D(n4616), .CK(clk), .RN(n4944), .Q(
DP_OP_153J6_122_5442_n828) );
DFFRX2TS DP_OP_155J6_124_2038_R_2099 ( .D(n4528), .CK(clk), .RN(n4942), .Q(
DP_OP_155J6_124_2038_n713) );
DFFRX1TS DP_OP_156J6_125_3370_R_1247_RW_0 ( .D(n688), .CK(clk), .RN(n4737),
.Q(n4426) );
DFFRX1TS DP_OP_156J6_125_3370_R_1211_RW_0 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]), .CK(clk), .RN(n4582), .Q(n4421) );
DFFRX2TS DP_OP_154J6_123_2038_R_292 ( .D(n332), .CK(clk), .RN(n4716), .Q(
DP_OP_154J6_123_2038_n684) );
DFFRX1TS DP_OP_153J6_122_5442_R_1993 ( .D(n4626), .CK(clk), .RN(n4648), .Q(
DP_OP_153J6_122_5442_n1385) );
DFFRX2TS DP_OP_153J6_122_5442_R_409 ( .D(n4590), .CK(clk), .RN(n4648), .Q(
DP_OP_153J6_122_5442_n451) );
DFFSX2TS R_2433 ( .D(DP_OP_153J6_122_5442_n1), .CK(clk), .SN(n4650), .Q(n664) );
DFFRX2TS DP_OP_153J6_122_5442_R_2315 ( .D(n4646), .CK(clk), .RN(n4716), .Q(
Sgf_operation_EVEN1_result_B_adder_2_), .QN(n727) );
DFFSHQX1TS DP_OP_154J6_123_2038_R_2255_IP ( .D(n4708), .CK(clk), .SN(n857),
.Q(n4720) );
DFFRX1TS DP_OP_156J6_125_3370_R_1143_RW_2 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .CK(clk), .RN(
n4467), .Q(n4416) );
DFFRX2TS DP_OP_153J6_122_5442_R_1837 ( .D(n4620), .CK(clk), .RN(n4648), .Q(
DP_OP_153J6_122_5442_n837) );
DFFRX1TS DP_OP_156J6_125_3370_R_1120_RW_0 ( .D(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .CK(clk), .RN(
n4447), .Q(n4415) );
DFFSX1TS add_x_19_R_1370_RW_0 ( .D(n824), .CK(clk), .SN(n4940), .Q(n4458) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(clk), .RN(
n4946), .Q(Op_MY[23]), .QN(n4871) );
DFFRHQX4TS R_1243 ( .D(n377), .CK(clk), .RN(n853), .Q(FS_Module_state_reg[2]) );
DFFSX1TS R_1858 ( .D(n4972), .CK(clk), .SN(n408), .Q(n4817) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(clk), .RN(
n846), .Q(Op_MX[23]) );
DFFSX1TS R_1883 ( .D(n4966), .CK(clk), .SN(n888), .Q(n4809) );
DFFSX1TS R_1822 ( .D(n4959), .CK(clk), .SN(n4796), .Q(n4823) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(clk), .RN(
n4560), .Q(Op_MY[25]), .QN(n4744) );
DFFRX2TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n233), .CK(clk), .RN(n836),
.Q(exp_oper_result[1]), .QN(n4756) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(clk), .RN(
n846), .Q(Op_MX[24]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n203), .CK(clk),
.RN(n4941), .Q(Sgf_normalized_result[1]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n204), .CK(clk),
.RN(n857), .Q(Sgf_normalized_result[2]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n208), .CK(clk),
.RN(n4801), .Q(Sgf_normalized_result[6]), .QN(n4787) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n207), .CK(clk),
.RN(n4801), .Q(Sgf_normalized_result[5]), .QN(n4772) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n247), .CK(clk), .RN(
n4940), .Q(P_Sgf[9]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n248), .CK(clk), .RN(
n4468), .Q(P_Sgf[10]) );
DFFSRHQX2TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n232), .CK(clk), .SN(1'b1),
.RN(n856), .Q(exp_oper_result[2]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(clk), .RN(
n855), .Q(Op_MY[26]), .QN(n4749) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(clk), .RN(
n4796), .Q(Op_MX[25]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(clk), .RN(
n413), .Q(Op_MY[27]), .QN(n4748) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(clk), .RN(
n4797), .Q(Op_MX[26]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n381), .CK(clk), .RN(
n406), .Q(Op_MY[31]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(clk), .RN(
n4560), .Q(Op_MX[31]) );
DFFRX1TS R_266 ( .D(n359), .CK(clk), .RN(n4798), .QN(n4892) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(clk), .RN(
n855), .Q(n717), .QN(n4876) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(clk), .RN(
n888), .Q(Op_MX[30]) );
DFFSX2TS R_2 ( .D(n4980), .CK(clk), .SN(n4800), .Q(n4921) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(clk), .RN(
n857), .Q(Op_MY[28]), .QN(n4774) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(clk), .RN(
n414), .Q(Op_MY[29]), .QN(n4867) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(clk), .RN(
n4797), .Q(Op_MX[27]) );
DFFRX1TS R_2253 ( .D(n329), .CK(clk), .RN(n403), .QN(n4795) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n290), .CK(clk), .RN(n4942),
.Q(Add_result[19]), .QN(n4750) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n307), .CK(clk), .RN(n4801),
.Q(Add_result[2]), .QN(n4771) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n304), .CK(clk), .RN(n4801),
.Q(Add_result[5]), .QN(n4768) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n289), .CK(clk), .RN(n4942),
.Q(Add_result[20]), .QN(n4759) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n303), .CK(clk), .RN(n4801),
.Q(Add_result[6]), .QN(n4767) );
NAND2X2TS U406 ( .A(n4937), .B(n4228), .Y(n4969) );
CLKINVX2TS U407 ( .A(n412), .Y(n414) );
INVX1TS U408 ( .A(n412), .Y(n415) );
CLKINVX3TS U409 ( .A(add_x_19_n104), .Y(add_x_19_n103) );
CLKINVX2TS U410 ( .A(n405), .Y(n408) );
CLKINVX1TS U411 ( .A(n405), .Y(n406) );
INVX3TS U412 ( .A(n409), .Y(n403) );
CLKINVX2TS U413 ( .A(n405), .Y(n407) );
AOI21X2TS U414 ( .A0(n1057), .A1(n1302), .B0(n714), .Y(
DP_OP_153J6_122_5442_n72) );
XOR2X1TS U415 ( .A(n2549), .B(n2548), .Y(n433) );
CLKINVX2TS U416 ( .A(n409), .Y(n410) );
NAND2X2TS U417 ( .A(n4210), .B(n4228), .Y(n4970) );
CLKBUFX2TS U418 ( .A(n3880), .Y(n1301) );
NAND2X4TS U419 ( .A(n3356), .B(n3355), .Y(n3781) );
NAND2X2TS U420 ( .A(n3761), .B(n3760), .Y(n3762) );
INVX4TS U421 ( .A(n3812), .Y(n690) );
CLKINVX2TS U422 ( .A(n4299), .Y(n4307) );
NAND2X1TS U423 ( .A(n4210), .B(n270), .Y(n4116) );
NAND2X1TS U424 ( .A(n4210), .B(n272), .Y(n2820) );
AND4X1TS U425 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n4094) );
INVX2TS U426 ( .A(n1369), .Y(n911) );
OAI21X1TS U427 ( .A0(n3913), .A1(n3912), .B0(n3911), .Y(n3918) );
NAND2X1TS U428 ( .A(n4206), .B(n268), .Y(n4104) );
NAND2X1TS U429 ( .A(n2547), .B(n2546), .Y(n2548) );
NAND2XLTS U430 ( .A(n3899), .B(n3873), .Y(n3874) );
NAND2X2TS U431 ( .A(n4209), .B(n4233), .Y(n790) );
INVX2TS U432 ( .A(n4299), .Y(n4308) );
CLKBUFX3TS U433 ( .A(n4299), .Y(n4303) );
INVX4TS U434 ( .A(n1128), .Y(n3893) );
NAND3X4TS U435 ( .A(n1194), .B(n3773), .C(n1057), .Y(n1376) );
INVX1TS U436 ( .A(n902), .Y(n3973) );
BUFX4TS U437 ( .A(n4343), .Y(n4378) );
NAND2X4TS U438 ( .A(n1194), .B(n1361), .Y(n1372) );
NAND2XLTS U439 ( .A(n3903), .B(n3902), .Y(n3904) );
NAND2XLTS U440 ( .A(n3916), .B(n3915), .Y(n3917) );
NOR2X6TS U441 ( .A(n1375), .B(n1374), .Y(n1373) );
NAND2XLTS U442 ( .A(n3909), .B(n3907), .Y(n2826) );
NOR2BX1TS U443 ( .AN(n4211), .B(n1343), .Y(n1342) );
INVX2TS U444 ( .A(n3846), .Y(n405) );
INVX2TS U445 ( .A(n4559), .Y(n412) );
INVX2TS U446 ( .A(n3877), .Y(n1404) );
BUFX4TS U447 ( .A(n3876), .Y(n1074) );
INVX4TS U448 ( .A(n4234), .Y(n859) );
BUFX3TS U449 ( .A(n966), .Y(n903) );
BUFX16TS U450 ( .A(n1280), .Y(n901) );
AO21X1TS U451 ( .A0(n2115), .A1(n1835), .B0(n1836), .Y(n617) );
INVX2TS U452 ( .A(n4100), .Y(n441) );
INVX4TS U453 ( .A(n4100), .Y(n4233) );
INVX8TS U454 ( .A(n3802), .Y(n3849) );
BUFX4TS U455 ( .A(n3972), .Y(n902) );
BUFX4TS U456 ( .A(n4202), .Y(n4292) );
CLKBUFX2TS U457 ( .A(n4796), .Y(n4559) );
BUFX4TS U458 ( .A(n3884), .Y(n946) );
CLKBUFX2TS U459 ( .A(n484), .Y(n1348) );
INVX4TS U460 ( .A(n4100), .Y(n4236) );
CLKINVX3TS U461 ( .A(n865), .Y(n847) );
CLKBUFX2TS U462 ( .A(n411), .Y(n3846) );
NAND2X2TS U463 ( .A(n2614), .B(n2613), .Y(n3096) );
INVX2TS U464 ( .A(n4065), .Y(n4210) );
INVX6TS U465 ( .A(n1233), .Y(n1267) );
BUFX12TS U466 ( .A(n1369), .Y(n889) );
INVX2TS U467 ( .A(n4234), .Y(n858) );
INVX2TS U468 ( .A(n4065), .Y(n4218) );
NAND2X1TS U469 ( .A(n3481), .B(n3433), .Y(n3135) );
INVX2TS U470 ( .A(n4065), .Y(n4206) );
CLKXOR2X2TS U471 ( .A(n3987), .B(n3986), .Y(n1505) );
XNOR2X2TS U472 ( .A(n3490), .B(n3489), .Y(n3829) );
AND4X1TS U473 ( .A(n4888), .B(n4892), .C(n4268), .D(n4891), .Y(n4271) );
NAND2X4TS U474 ( .A(n3774), .B(n3775), .Y(n3889) );
NAND2X1TS U475 ( .A(n3488), .B(n3487), .Y(n3489) );
NOR2X2TS U476 ( .A(n3900), .B(n3901), .Y(n3906) );
NAND2X4TS U477 ( .A(n4213), .B(n4212), .Y(n4343) );
INVX6TS U478 ( .A(n3884), .Y(n1109) );
NAND2X2TS U479 ( .A(n3474), .B(n3473), .Y(n3760) );
INVX2TS U480 ( .A(n332), .Y(n3965) );
NAND2X4TS U481 ( .A(n3642), .B(n3641), .Y(n3885) );
NAND2X6TS U482 ( .A(n1238), .B(n1432), .Y(n1233) );
INVX4TS U483 ( .A(n4222), .Y(n3814) );
MX2X1TS U484 ( .A(Op_MX[27]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
OAI21X1TS U485 ( .A0(n3922), .A1(n3919), .B0(n3923), .Y(n2497) );
NAND2X1TS U486 ( .A(n3483), .B(n3484), .Y(n3485) );
OR2X2TS U487 ( .A(n4198), .B(FSM_selector_C), .Y(n4100) );
OAI21X2TS U488 ( .A0(n3901), .A1(n3899), .B0(n3902), .Y(n3910) );
NOR2X2TS U489 ( .A(n2825), .B(n3914), .Y(n2537) );
NOR2X1TS U490 ( .A(n3801), .B(n1500), .Y(n3349) );
NAND2XLTS U491 ( .A(n3998), .B(n3996), .Y(n3986) );
INVX2TS U492 ( .A(n4234), .Y(n860) );
CLKBUFX2TS U493 ( .A(n3995), .Y(n456) );
INVX2TS U494 ( .A(n409), .Y(n411) );
OR2X2TS U495 ( .A(n3985), .B(n3984), .Y(n3998) );
BUFX3TS U496 ( .A(n3723), .Y(n1102) );
NOR2X1TS U497 ( .A(FS_Module_state_reg[2]), .B(n4746), .Y(n4212) );
BUFX3TS U498 ( .A(n977), .Y(n890) );
NAND2XLTS U499 ( .A(n2462), .B(n2779), .Y(n2463) );
INVX6TS U500 ( .A(n3479), .Y(n1203) );
NAND2X1TS U501 ( .A(n3593), .B(n3591), .Y(n2618) );
NAND2XLTS U502 ( .A(n3598), .B(n3597), .Y(n3599) );
NAND2X4TS U503 ( .A(n3472), .B(n3471), .Y(n3777) );
NAND2XLTS U504 ( .A(n4097), .B(n4096), .Y(n4098) );
NAND2XLTS U505 ( .A(n3604), .B(n3603), .Y(n3605) );
NOR2X4TS U506 ( .A(n3472), .B(n3471), .Y(n3776) );
CLKINVX2TS U507 ( .A(n485), .Y(n2701) );
NOR2X2TS U508 ( .A(n4253), .B(FSM_selector_C), .Y(n2819) );
NAND2X4TS U509 ( .A(n2264), .B(n2828), .Y(n2293) );
INVX2TS U510 ( .A(underflow_flag), .Y(n4989) );
NAND3X6TS U511 ( .A(n511), .B(n929), .C(n1453), .Y(n524) );
OAI21XLTS U512 ( .A0(FSM_selector_B_1_), .A1(n4748), .B0(n3839), .Y(n3833)
);
INVX2TS U513 ( .A(n3815), .Y(n401) );
NAND2X1TS U514 ( .A(n2803), .B(n2712), .Y(n2446) );
AOI21X2TS U515 ( .A0(n2805), .A1(n2712), .B0(n2444), .Y(n2445) );
AND2X6TS U516 ( .A(n2995), .B(n2994), .Y(n714) );
BUFX4TS U517 ( .A(n3640), .Y(n1077) );
INVX2TS U518 ( .A(n2829), .Y(n2264) );
NOR2X1TS U519 ( .A(n3978), .B(n885), .Y(n3989) );
NAND2X4TS U520 ( .A(n2895), .B(n2896), .Y(n3892) );
NOR2X1TS U521 ( .A(n4091), .B(n4746), .Y(n4018) );
NAND2X6TS U522 ( .A(n2963), .B(n2962), .Y(n3881) );
NAND2X1TS U523 ( .A(n3985), .B(n3984), .Y(n3996) );
INVX2TS U524 ( .A(n4191), .Y(n3072) );
MX2X1TS U525 ( .A(Op_MX[25]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
BUFX3TS U526 ( .A(n3492), .Y(n691) );
NOR2X2TS U527 ( .A(n4747), .B(FS_Module_state_reg[2]), .Y(n4019) );
NAND2X2TS U528 ( .A(n870), .B(n4167), .Y(n4169) );
CLKMX2X4TS U529 ( .A(Exp_module_Data_S[8]), .B(n4850), .S0(n663), .Y(n226)
);
INVX2TS U530 ( .A(n2805), .Y(n2711) );
CLKINVX1TS U531 ( .A(n2615), .Y(n3590) );
XNOR2X2TS U532 ( .A(n2311), .B(n2310), .Y(n3375) );
CLKXOR2X2TS U533 ( .A(n4002), .B(n3719), .Y(n3722) );
NAND2XLTS U534 ( .A(n2306), .B(n2305), .Y(n2307) );
NAND2XLTS U535 ( .A(n3726), .B(n3979), .Y(n3727) );
OAI21X2TS U536 ( .A0(n3959), .A1(n3962), .B0(n3960), .Y(n3864) );
NAND2X1TS U537 ( .A(n2803), .B(n3060), .Y(n2807) );
INVX8TS U538 ( .A(n1413), .Y(n3493) );
NAND2X2TS U539 ( .A(n2784), .B(n2803), .Y(n2786) );
NAND2X1TS U540 ( .A(n3725), .B(n3724), .Y(n3979) );
INVX4TS U541 ( .A(n1414), .Y(n1413) );
NAND2X1TS U542 ( .A(n3255), .B(n3258), .Y(n3852) );
MX2X1TS U543 ( .A(Op_MX[24]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
NAND2X1TS U544 ( .A(n651), .B(n630), .Y(n4178) );
NAND2X6TS U545 ( .A(n772), .B(n443), .Y(n1448) );
INVX6TS U546 ( .A(n3491), .Y(n444) );
INVX3TS U547 ( .A(n4164), .Y(n4167) );
OR2X2TS U548 ( .A(n3556), .B(n3555), .Y(n3572) );
AOI21X2TS U549 ( .A0(n4191), .A1(n4122), .B0(n4121), .Y(n4123) );
AOI21X1TS U550 ( .A0(n3390), .A1(n3388), .B0(n3382), .Y(n3387) );
NAND2X6TS U551 ( .A(n1229), .B(n3808), .Y(n1128) );
NOR2X4TS U552 ( .A(n4186), .B(n639), .Y(n4175) );
NAND2X1TS U553 ( .A(n4385), .B(Sgf_normalized_result[19]), .Y(n4245) );
NAND3X4TS U554 ( .A(n1212), .B(n1210), .C(n1209), .Y(n466) );
CLKINVX1TS U555 ( .A(n865), .Y(n833) );
NOR2X2TS U556 ( .A(n3554), .B(n845), .Y(n3579) );
NAND2XLTS U557 ( .A(n1835), .B(n2113), .Y(n2114) );
MX2X4TS U558 ( .A(n3033), .B(n4849), .S0(n666), .Y(n253) );
NOR2X2TS U559 ( .A(n4165), .B(n4134), .Y(n4135) );
NOR2X4TS U560 ( .A(n2802), .B(n3059), .Y(n2784) );
NAND2X4TS U561 ( .A(n1168), .B(n3319), .Y(n990) );
CLKXOR2X2TS U562 ( .A(n3303), .B(n3322), .Y(n3350) );
NAND2X1TS U563 ( .A(n3534), .B(n3543), .Y(n2113) );
CLKINVX2TS U564 ( .A(n3376), .Y(n3378) );
INVX2TS U565 ( .A(n1840), .Y(n3576) );
INVX2TS U566 ( .A(n3334), .Y(n973) );
NOR2X4TS U567 ( .A(n3305), .B(n1449), .Y(n772) );
INVX2TS U568 ( .A(n4405), .Y(n3416) );
OAI2BB1X2TS U569 ( .A0N(n751), .A1N(n3526), .B0(n1316), .Y(n3629) );
BUFX8TS U570 ( .A(n3062), .Y(n4187) );
NAND2X1TS U571 ( .A(n2136), .B(n2299), .Y(n2137) );
CLKINVX2TS U572 ( .A(n4074), .Y(n4070) );
NAND2X1TS U573 ( .A(n3388), .B(n1058), .Y(n3389) );
NOR2X2TS U574 ( .A(n4165), .B(n4120), .Y(n4121) );
INVX2TS U575 ( .A(n4170), .Y(n4171) );
INVX3TS U576 ( .A(n2295), .Y(n1251) );
NAND2X4TS U577 ( .A(n2864), .B(n2863), .Y(n3808) );
NAND2XLTS U578 ( .A(n3335), .B(n3337), .Y(n3336) );
NOR2X1TS U579 ( .A(n3712), .B(n3709), .Y(n3715) );
BUFX4TS U580 ( .A(n2378), .Y(n877) );
NAND2XLTS U581 ( .A(n3341), .B(n3340), .Y(n3342) );
INVX6TS U582 ( .A(n482), .Y(n1259) );
NAND2X1TS U583 ( .A(n1299), .B(n3320), .Y(n3303) );
XNOR2X2TS U584 ( .A(n3461), .B(n3460), .Y(n3462) );
XNOR2X2TS U585 ( .A(n3786), .B(n1436), .Y(n3574) );
NAND2X1TS U586 ( .A(n3235), .B(n3234), .Y(n3854) );
INVX2TS U587 ( .A(n3534), .Y(n3560) );
NOR2X1TS U588 ( .A(n3235), .B(n3234), .Y(n3850) );
CLKINVX2TS U589 ( .A(n3516), .Y(n3538) );
BUFX8TS U590 ( .A(n3062), .Y(n870) );
INVX6TS U591 ( .A(n3305), .Y(n514) );
NOR2X2TS U592 ( .A(n1032), .B(n3717), .Y(n3978) );
NAND2X2TS U593 ( .A(n3441), .B(n3440), .Y(n3804) );
NAND2X1TS U594 ( .A(n3527), .B(n1317), .Y(n1316) );
NAND2X6TS U595 ( .A(n509), .B(n1216), .Y(n1209) );
AOI21X1TS U596 ( .A0(n3302), .A1(n1299), .B0(n1471), .Y(n1298) );
NOR2X6TS U597 ( .A(n3698), .B(n3701), .Y(n3703) );
NAND2X6TS U598 ( .A(n485), .B(n484), .Y(n480) );
INVX3TS U599 ( .A(n1399), .Y(n1232) );
NAND2X2TS U600 ( .A(n2744), .B(n3646), .Y(n2745) );
ADDFHX2TS U601 ( .A(n3618), .B(n3616), .CI(n3617), .CO(n3627), .S(n3608) );
NAND2X1TS U602 ( .A(n4133), .B(n4132), .Y(n4134) );
NAND2X4TS U603 ( .A(n992), .B(n3330), .Y(n1371) );
NAND2X1TS U604 ( .A(n1472), .B(n3324), .Y(n3325) );
OAI22X1TS U605 ( .A0(n3523), .A1(n3552), .B0(n838), .B1(n1007), .Y(n3530) );
INVX4TS U606 ( .A(FSM_exp_operation_A_S), .Y(n796) );
NAND2XLTS U607 ( .A(n3695), .B(n3710), .Y(n3696) );
NOR2X6TS U608 ( .A(n1265), .B(n3328), .Y(n1449) );
NAND2X1TS U609 ( .A(n3516), .B(n3515), .Y(n2305) );
INVX2TS U610 ( .A(n2875), .Y(n2929) );
INVX2TS U611 ( .A(n3546), .Y(n3555) );
INVX6TS U612 ( .A(n1002), .Y(n1000) );
OR2X6TS U613 ( .A(n3435), .B(n3434), .Y(n3484) );
NAND2X1TS U614 ( .A(n1041), .B(n3232), .Y(n3340) );
INVX2TS U615 ( .A(n3444), .Y(n3456) );
INVX2TS U616 ( .A(n3483), .Y(n3436) );
INVX4TS U617 ( .A(n2990), .Y(n3616) );
INVX3TS U618 ( .A(n2922), .Y(n2938) );
INVX2TS U619 ( .A(n2943), .Y(n2948) );
NAND2X1TS U620 ( .A(n3714), .B(n3675), .Y(n1408) );
OAI2BB1X2TS U621 ( .A0N(n2542), .A1N(n2541), .B0(n1306), .Y(n3525) );
NAND2X4TS U622 ( .A(n1100), .B(n1099), .Y(n2982) );
NAND2XLTS U623 ( .A(n2752), .B(n2749), .Y(n2697) );
CLKINVX6TS U624 ( .A(n2297), .Y(n445) );
OR2X2TS U625 ( .A(n3123), .B(n3122), .Y(n3481) );
INVX3TS U626 ( .A(Sgf_operation_EVEN1_Q_left[6]), .Y(n3447) );
INVX4TS U627 ( .A(n2933), .Y(n2985) );
NAND2X2TS U628 ( .A(n2970), .B(n2969), .Y(n3384) );
NOR2X1TS U629 ( .A(n3323), .B(n3321), .Y(n1473) );
NOR2X4TS U630 ( .A(n3496), .B(n3497), .Y(n2300) );
INVX2TS U631 ( .A(n3618), .Y(n3614) );
XNOR2X2TS U632 ( .A(n3786), .B(n1022), .Y(n1007) );
NAND2X4TS U633 ( .A(n3497), .B(n3496), .Y(n2299) );
CLKBUFX2TS U634 ( .A(n3716), .Y(n1032) );
CLKINVX1TS U635 ( .A(n4200), .Y(n2816) );
AO21X2TS U636 ( .A0(n3520), .A1(n3519), .B0(n447), .Y(n3541) );
INVX4TS U637 ( .A(n3691), .Y(n3701) );
NAND2X4TS U638 ( .A(n2903), .B(n2916), .Y(n1058) );
NAND2X1TS U639 ( .A(n4156), .B(n4162), .Y(n3750) );
INVX2TS U640 ( .A(n3433), .Y(n3480) );
OR2X2TS U641 ( .A(n3133), .B(n3132), .Y(n3488) );
INVX3TS U642 ( .A(n1216), .Y(n1211) );
NOR2X6TS U643 ( .A(n3326), .B(n3328), .Y(n3330) );
NAND2X6TS U644 ( .A(n891), .B(n2594), .Y(n484) );
INVX2TS U645 ( .A(n1120), .Y(n1113) );
CLKINVX6TS U646 ( .A(n4315), .Y(n3448) );
CLKXOR2X2TS U647 ( .A(n2708), .B(n2707), .Y(n2709) );
INVX2TS U648 ( .A(n2970), .Y(n3505) );
NAND2XLTS U649 ( .A(n3223), .B(n3220), .Y(n3207) );
INVX2TS U650 ( .A(n2923), .Y(n2936) );
CLKINVX3TS U651 ( .A(n2903), .Y(n2988) );
INVX2TS U652 ( .A(n3517), .Y(n3518) );
NAND2XLTS U653 ( .A(n1503), .B(n2706), .Y(n2708) );
INVX4TS U654 ( .A(n3496), .Y(n3502) );
INVX6TS U655 ( .A(n3326), .Y(n3304) );
NOR2X6TS U656 ( .A(n3318), .B(n3317), .Y(n3328) );
NOR2X2TS U657 ( .A(n3694), .B(n1745), .Y(n3712) );
NAND2X1TS U658 ( .A(n3675), .B(n3711), .Y(n3676) );
NAND2X4TS U659 ( .A(n2596), .B(n2595), .Y(n891) );
OAI2BB1X1TS U660 ( .A0N(n3544), .A1N(n1307), .B0(n2540), .Y(n1306) );
NAND2X1TS U661 ( .A(n2608), .B(n2607), .Y(n3124) );
AND2X6TS U662 ( .A(n494), .B(n2703), .Y(n425) );
NOR2X1TS U663 ( .A(n3226), .B(n3227), .Y(n3321) );
AND2X6TS U664 ( .A(n3699), .B(n3678), .Y(n1282) );
NAND2X4TS U665 ( .A(n3678), .B(n3702), .Y(n1216) );
CLKINVX6TS U666 ( .A(n3327), .Y(n1265) );
NAND2X2TS U667 ( .A(n2945), .B(n2946), .Y(n1099) );
NAND2X1TS U668 ( .A(n463), .B(n1051), .Y(n3324) );
NAND2X2TS U669 ( .A(n3435), .B(n3434), .Y(n3483) );
BUFX16TS U670 ( .A(n1065), .Y(n509) );
NAND2X6TS U671 ( .A(n914), .B(n2116), .Y(n1414) );
CLKAND2X2TS U672 ( .A(n755), .B(n2707), .Y(n1483) );
INVX8TS U673 ( .A(n1379), .Y(n1468) );
NAND2X1TS U674 ( .A(n3122), .B(n3123), .Y(n3433) );
CLKBUFX2TS U675 ( .A(n3233), .Y(n1041) );
NAND2X2TS U676 ( .A(n3691), .B(n3700), .Y(n3692) );
AOI21X2TS U677 ( .A0(n3223), .A1(n3222), .B0(n3221), .Y(n3275) );
NOR2X2TS U678 ( .A(n2608), .B(n2607), .Y(n3126) );
NOR2X1TS U679 ( .A(n3495), .B(n845), .Y(n3503) );
NAND2X2TS U680 ( .A(n2702), .B(n2586), .Y(n2590) );
NAND2X4TS U681 ( .A(n3669), .B(n3668), .Y(n3702) );
NAND2X1TS U682 ( .A(n3227), .B(n3226), .Y(n3320) );
INVX6TS U683 ( .A(n3698), .Y(n3678) );
INVX3TS U684 ( .A(n3388), .Y(n3381) );
INVX6TS U685 ( .A(n1122), .Y(n1379) );
NAND2X2TS U686 ( .A(n3690), .B(n3689), .Y(n3700) );
INVX4TS U687 ( .A(n2321), .Y(n446) );
BUFX4TS U688 ( .A(n1219), .Y(n494) );
NOR2X6TS U689 ( .A(n2969), .B(n2970), .Y(n3383) );
INVX6TS U690 ( .A(n2586), .Y(n826) );
BUFX3TS U691 ( .A(n2702), .Y(n1019) );
NAND2X6TS U692 ( .A(n1173), .B(n2128), .Y(n2596) );
NAND2X4TS U693 ( .A(n2112), .B(n2111), .Y(n2116) );
NAND2X6TS U694 ( .A(n3269), .B(n1075), .Y(n3278) );
CLKINVX3TS U695 ( .A(n2309), .Y(n2292) );
OR2X2TS U696 ( .A(n1101), .B(n2926), .Y(n2927) );
NAND2X2TS U697 ( .A(n1477), .B(n3216), .Y(n754) );
OAI22X2TS U698 ( .A0(n2544), .A1(n2513), .B0(n2525), .B1(n2543), .Y(n2528)
);
NAND2X2TS U699 ( .A(n3748), .B(n4452), .Y(n4151) );
CLKXOR2X2TS U700 ( .A(n3217), .B(n3216), .Y(n3218) );
NAND2X2TS U701 ( .A(n2885), .B(n2884), .Y(n3454) );
INVX2TS U702 ( .A(n2409), .Y(n4183) );
INVX2TS U703 ( .A(n725), .Y(n4132) );
INVX2TS U704 ( .A(n1506), .Y(n4170) );
OR2X6TS U705 ( .A(n2903), .B(n2916), .Y(n3388) );
INVX2TS U706 ( .A(n3746), .Y(n4137) );
INVX2TS U707 ( .A(Sgf_operation_EVEN1_Q_left[4]), .Y(n3431) );
NOR2X6TS U708 ( .A(n3669), .B(n3668), .Y(n3698) );
INVX2TS U709 ( .A(n3689), .Y(n1397) );
BUFX8TS U710 ( .A(n3270), .Y(n1075) );
BUFX6TS U711 ( .A(n3552), .Y(n563) );
INVX2TS U712 ( .A(n2971), .Y(n2972) );
OAI22X2TS U713 ( .A0(n2506), .A1(n435), .B0(n2520), .B1(n2514), .Y(n2517) );
NAND2X4TS U714 ( .A(n4069), .B(n2373), .Y(n2375) );
NAND2X4TS U715 ( .A(n2782), .B(n632), .Y(n3064) );
XNOR2X2TS U716 ( .A(n2515), .B(n2524), .Y(n2499) );
CLKBUFX2TS U717 ( .A(n3228), .Y(n1051) );
INVX3TS U718 ( .A(n2885), .Y(n2909) );
CLKBUFX2TS U719 ( .A(n3224), .Y(n393) );
BUFX6TS U720 ( .A(n1126), .Y(n919) );
NAND2X2TS U721 ( .A(n2438), .B(n636), .Y(n3603) );
NAND2BX2TS U722 ( .AN(n2914), .B(n1436), .Y(n2901) );
XNOR2X2TS U723 ( .A(n1129), .B(n3522), .Y(n2925) );
NAND2X2TS U724 ( .A(n2012), .B(n2011), .Y(n3216) );
XNOR2X2TS U725 ( .A(n2914), .B(n1436), .Y(n2902) );
ADDFHX2TS U726 ( .A(n3333), .B(n3332), .CI(n3331), .CO(n3334), .S(n3317) );
INVX6TS U727 ( .A(n3212), .Y(n1190) );
INVX2TS U728 ( .A(n2010), .Y(n2011) );
INVX2TS U729 ( .A(n3361), .Y(n1163) );
INVX2TS U730 ( .A(n2503), .Y(n2504) );
INVX2TS U731 ( .A(n2495), .Y(n2859) );
NAND2X1TS U732 ( .A(n3206), .B(n1082), .Y(n3214) );
NOR2X6TS U733 ( .A(n2289), .B(n2288), .Y(n3376) );
AO21X2TS U734 ( .A0(n1814), .A1(n1354), .B0(n1337), .Y(n1789) );
NOR2X1TS U735 ( .A(n521), .B(n3309), .Y(n3333) );
CLKINVX6TS U736 ( .A(n841), .Y(n842) );
INVX6TS U737 ( .A(n585), .Y(n2589) );
NOR2X6TS U738 ( .A(n1435), .B(n2898), .Y(n1437) );
NAND2X4TS U739 ( .A(n569), .B(n565), .Y(n1252) );
NOR2X4TS U740 ( .A(n2885), .B(n2884), .Y(n3455) );
NAND2X1TS U741 ( .A(n3736), .B(n3085), .Y(n3086) );
CLKBUFX2TS U742 ( .A(n3673), .Y(n1067) );
CLKBUFX2TS U743 ( .A(n3674), .Y(n453) );
NOR2X2TS U744 ( .A(n451), .B(n2545), .Y(n2542) );
NAND2X2TS U745 ( .A(n2841), .B(n2843), .Y(n3419) );
ADDFHX2TS U746 ( .A(n2270), .B(n2269), .CI(n2268), .CO(n2860), .S(n2290) );
NAND2X4TS U747 ( .A(n2106), .B(n2107), .Y(n2295) );
XNOR2X2TS U748 ( .A(n3517), .B(n2976), .Y(n2879) );
NOR2X2TS U749 ( .A(n3018), .B(n2329), .Y(n3003) );
INVX2TS U750 ( .A(n2313), .Y(n2287) );
CMPR32X2TS U751 ( .A(n3313), .B(n3312), .C(n3311), .CO(n3332), .S(n3315) );
INVX2TS U752 ( .A(n2515), .Y(n2516) );
NAND2X1TS U753 ( .A(n3366), .B(n3365), .Y(n3368) );
OR2X6TS U754 ( .A(n2090), .B(n2089), .Y(n2139) );
NOR2X1TS U755 ( .A(n3206), .B(n1082), .Y(n3213) );
CLKBUFX2TS U756 ( .A(n2746), .Y(n1044) );
NAND2X6TS U757 ( .A(n1750), .B(n1751), .Y(n2587) );
NAND2X6TS U758 ( .A(n2693), .B(n2692), .Y(n3647) );
OAI22X2TS U759 ( .A0(n1833), .A1(n1831), .B0(n1810), .B1(n840), .Y(n2843) );
INVX2TS U760 ( .A(n2493), .Y(n2270) );
NAND2X1TS U761 ( .A(n2434), .B(n2764), .Y(n2435) );
OR2X4TS U762 ( .A(n2286), .B(n2285), .Y(n2312) );
NAND2X1TS U763 ( .A(n2458), .B(n2763), .Y(n2459) );
NAND2X1TS U764 ( .A(n2423), .B(n2426), .Y(n2410) );
NOR2X1TS U765 ( .A(n1059), .B(n2900), .Y(n2898) );
OR2X2TS U766 ( .A(n3116), .B(n1381), .Y(n3131) );
OR2X4TS U767 ( .A(n955), .B(n2166), .Y(n3427) );
NOR2X2TS U768 ( .A(n656), .B(n2330), .Y(n3012) );
CLKBUFX2TS U769 ( .A(n2747), .Y(n829) );
AO21X2TS U770 ( .A0(n1496), .A1(n2316), .B0(n970), .Y(n969) );
NAND2X2TS U771 ( .A(n568), .B(n566), .Y(n565) );
NAND2X2TS U772 ( .A(n2369), .B(n627), .Y(n4050) );
INVX3TS U773 ( .A(n2138), .Y(n2091) );
NAND2X2TS U774 ( .A(n2371), .B(n642), .Y(n4083) );
NAND2X2TS U775 ( .A(n883), .B(n1711), .Y(n1714) );
INVX8TS U776 ( .A(n3519), .Y(n841) );
NAND2X2TS U777 ( .A(n3522), .B(n567), .Y(n564) );
NAND2X1TS U778 ( .A(n3743), .B(n3742), .Y(n3744) );
NAND2X2TS U779 ( .A(n1294), .B(n2906), .Y(n963) );
NAND2X1TS U780 ( .A(n635), .B(n2773), .Y(n4028) );
INVX2TS U781 ( .A(n2492), .Y(n2255) );
OR2X6TS U782 ( .A(n1666), .B(n1665), .Y(n953) );
NAND2X1TS U783 ( .A(n652), .B(n2452), .Y(n3037) );
OAI21X2TS U784 ( .A0(n3249), .A1(n3248), .B0(n3247), .Y(n1447) );
NOR2X1TS U785 ( .A(n635), .B(n2773), .Y(n3043) );
INVX2TS U786 ( .A(n3552), .Y(n568) );
NOR2BX1TS U787 ( .AN(n2477), .B(n2543), .Y(n2489) );
INVX2TS U788 ( .A(n2876), .Y(n570) );
NAND2X6TS U789 ( .A(n2180), .B(n1485), .Y(n2544) );
NAND2X1TS U790 ( .A(n3741), .B(n645), .Y(n3742) );
NAND2X2TS U791 ( .A(n2229), .B(n2167), .Y(n3109) );
INVX2TS U792 ( .A(n1753), .Y(n1172) );
CLKAND2X4TS U793 ( .A(n2868), .B(n1095), .Y(n748) );
NAND2X1TS U794 ( .A(n2797), .B(n3075), .Y(n2798) );
BUFX12TS U795 ( .A(n3522), .Y(n1022) );
NAND2BX1TS U796 ( .AN(n3741), .B(n644), .Y(n3743) );
CLKINVX6TS U797 ( .A(n2524), .Y(n2545) );
AND2X4TS U798 ( .A(n1326), .B(n2239), .Y(n750) );
NAND2X2TS U799 ( .A(n417), .B(n496), .Y(n1810) );
INVX2TS U800 ( .A(n2914), .Y(n567) );
NOR2BX2TS U801 ( .AN(n2914), .B(n3519), .Y(n2258) );
NAND2X1TS U802 ( .A(n2018), .B(n1383), .Y(n1382) );
NAND2X1TS U803 ( .A(n2705), .B(n2704), .Y(n2706) );
INVX2TS U804 ( .A(n1095), .Y(n1322) );
BUFX4TS U805 ( .A(n550), .Y(n521) );
OR2X2TS U806 ( .A(n3083), .B(n3084), .Y(n3736) );
AND2X2TS U807 ( .A(n3084), .B(n3083), .Y(n3735) );
NOR2X6TS U808 ( .A(n395), .B(n1750), .Y(n2588) );
BUFX3TS U809 ( .A(n1805), .Y(n881) );
BUFX8TS U810 ( .A(n2177), .Y(n1101) );
OR2X6TS U811 ( .A(n2075), .B(n2074), .Y(n2322) );
NAND2X6TS U812 ( .A(n1351), .B(n1350), .Y(n705) );
INVX2TS U813 ( .A(n3074), .Y(n2788) );
INVX2TS U814 ( .A(n2490), .Y(n2259) );
NAND2X4TS U815 ( .A(DP_OP_153J6_122_5442_n792), .B(n4874), .Y(n2524) );
OR2X1TS U816 ( .A(n4868), .B(n4874), .Y(n1485) );
NAND2X6TS U817 ( .A(n1697), .B(n1698), .Y(n1752) );
INVX2TS U818 ( .A(n2976), .Y(n447) );
INVX2TS U819 ( .A(n2230), .Y(n1821) );
OAI22X2TS U820 ( .A0(n3185), .A1(n747), .B0(n3234), .B1(n462), .Y(n3294) );
NAND2BX2TS U821 ( .AN(n2914), .B(n2976), .Y(n2232) );
INVX6TS U822 ( .A(n3788), .Y(n843) );
NOR2X2TS U823 ( .A(n875), .B(n3660), .Y(n3684) );
XOR2X2TS U824 ( .A(n2839), .B(n450), .Y(n1796) );
INVX12TS U825 ( .A(n1831), .Y(n417) );
NAND2X2TS U826 ( .A(n2284), .B(n971), .Y(n2315) );
INVX2TS U827 ( .A(n2871), .Y(n1327) );
INVX6TS U828 ( .A(n1270), .Y(n2520) );
INVX2TS U829 ( .A(n3869), .Y(n2277) );
NAND2X4TS U830 ( .A(n2777), .B(n2776), .Y(n3076) );
NOR2X6TS U831 ( .A(n2796), .B(n2795), .Y(n3077) );
NAND2X2TS U832 ( .A(n2796), .B(n2795), .Y(n3075) );
BUFX6TS U833 ( .A(n2165), .Y(n3519) );
NOR2X4TS U834 ( .A(n2777), .B(n2776), .Y(n3074) );
NAND2X2TS U835 ( .A(n2244), .B(n2245), .Y(n2230) );
NAND2X1TS U836 ( .A(n1662), .B(n1705), .Y(n1663) );
INVX2TS U837 ( .A(n2133), .Y(n1178) );
BUFX4TS U838 ( .A(n2870), .Y(n1095) );
INVX2TS U839 ( .A(n2153), .Y(n450) );
AND2X2TS U840 ( .A(n1270), .B(n2477), .Y(n2490) );
XNOR2X1TS U841 ( .A(n2839), .B(n2152), .Y(n1805) );
NAND2XLTS U842 ( .A(n2086), .B(n2097), .Y(n2087) );
NAND2X1TS U843 ( .A(n2150), .B(n924), .Y(n971) );
NOR2X4TS U844 ( .A(n2871), .B(n2868), .Y(n2904) );
ADDFHX2TS U845 ( .A(n2727), .B(n2726), .CI(n2725), .CO(n3667), .S(n2722) );
ADDHX1TS U846 ( .A(n4414), .B(n3740), .CO(n3741), .S(n3083) );
NOR2X2TS U847 ( .A(n1703), .B(n1706), .Y(n1709) );
INVX2TS U848 ( .A(n3259), .Y(n3289) );
NAND2X1TS U849 ( .A(n3259), .B(n3257), .Y(n2097) );
NAND2X6TS U850 ( .A(n975), .B(n976), .Y(n3193) );
NAND2X4TS U851 ( .A(n3370), .B(n3371), .Y(n1384) );
NAND2X4TS U852 ( .A(n1832), .B(n924), .Y(n959) );
NAND2X1TS U853 ( .A(n2731), .B(n1661), .Y(n1705) );
NAND2X4TS U854 ( .A(n1224), .B(n1222), .Y(n2318) );
INVX2TS U855 ( .A(n2206), .Y(n548) );
INVX3TS U856 ( .A(n1697), .Y(n1350) );
INVX6TS U857 ( .A(n2839), .Y(n1831) );
INVX4TS U858 ( .A(n3393), .Y(n2320) );
INVX3TS U859 ( .A(n1222), .Y(n1221) );
NAND2X6TS U860 ( .A(n1311), .B(n1290), .Y(n518) );
NAND2BX2TS U861 ( .AN(n2283), .B(n1085), .Y(n1816) );
OAI22X2TS U862 ( .A0(n1031), .A1(n2733), .B0(n875), .B1(n2667), .Y(n2726) );
XNOR2X2TS U863 ( .A(n2178), .B(n4874), .Y(n2179) );
XNOR2X2TS U864 ( .A(n2472), .B(n2477), .Y(n2256) );
XNOR2X1TS U865 ( .A(n1085), .B(n2283), .Y(n1813) );
NAND2BX2TS U866 ( .AN(n2477), .B(n2472), .Y(n2261) );
NAND2X1TS U867 ( .A(n2053), .B(n2052), .Y(n2055) );
NAND2X2TS U868 ( .A(n2175), .B(n2176), .Y(n542) );
INVX4TS U869 ( .A(n1081), .Y(n884) );
INVX4TS U870 ( .A(n3235), .Y(n3261) );
INVX3TS U871 ( .A(n3725), .Y(n2661) );
INVX6TS U872 ( .A(n553), .Y(n2881) );
INVX4TS U873 ( .A(n2557), .Y(n2625) );
CLKINVX6TS U874 ( .A(n769), .Y(n771) );
INVX8TS U875 ( .A(n923), .Y(n2907) );
INVX2TS U876 ( .A(n1078), .Y(n1142) );
INVX2TS U877 ( .A(n2202), .Y(n549) );
NAND2BX1TS U878 ( .AN(n2676), .B(n2735), .Y(n1185) );
BUFX16TS U879 ( .A(n1820), .Y(n1354) );
INVX2TS U880 ( .A(n2647), .Y(n2673) );
OR2X4TS U881 ( .A(n2837), .B(Op_MY[11]), .Y(n2838) );
NAND2X4TS U882 ( .A(n998), .B(n997), .Y(n3662) );
BUFX4TS U883 ( .A(n2283), .Y(n924) );
INVX6TS U884 ( .A(n1433), .Y(n2900) );
OAI21X2TS U885 ( .A0(n3240), .A1(n3241), .B0(n3239), .Y(n1136) );
INVX3TS U886 ( .A(n2472), .Y(n2535) );
NAND2X2TS U887 ( .A(n561), .B(n1999), .Y(n2077) );
NAND2X2TS U888 ( .A(n1777), .B(n1760), .Y(n1227) );
NOR2X2TS U889 ( .A(n3257), .B(n3259), .Y(n2098) );
NAND2X4TS U890 ( .A(n2474), .B(n2193), .Y(n2475) );
NOR2BX2TS U891 ( .AN(DP_OP_153J6_122_5442_n792), .B(
DP_OP_153J6_122_5442_n1468), .Y(n2178) );
INVX2TS U892 ( .A(n1650), .Y(n1651) );
NAND2X1TS U893 ( .A(n2050), .B(n2049), .Y(n2051) );
NOR2X1TS U894 ( .A(n2731), .B(n1661), .Y(n1706) );
INVX2TS U895 ( .A(n2235), .Y(n1290) );
NOR2X2TS U896 ( .A(n2851), .B(n2848), .Y(n2174) );
NOR2X4TS U897 ( .A(n561), .B(n1999), .Y(n2076) );
NAND2XLTS U898 ( .A(n3240), .B(n3241), .Y(n1274) );
INVX2TS U899 ( .A(n2758), .Y(n3371) );
NAND2X2TS U900 ( .A(n2163), .B(n2235), .Y(n2164) );
NOR2X4TS U901 ( .A(n550), .B(n3186), .Y(n3262) );
OAI22X2TS U902 ( .A0(n1480), .A1(n3293), .B0(n873), .B1(n3309), .Y(n3178) );
XOR2X2TS U903 ( .A(n2153), .B(DP_OP_153J6_122_5442_n837), .Y(n1422) );
INVX2TS U904 ( .A(n2195), .Y(n2182) );
NAND2X1TS U905 ( .A(n3185), .B(n3182), .Y(n2099) );
OR2X6TS U906 ( .A(n2412), .B(n2411), .Y(n2423) );
NAND2X1TS U907 ( .A(n2170), .B(n2169), .Y(n2172) );
NAND2X4TS U908 ( .A(n774), .B(n773), .Y(n998) );
AND2X6TS U909 ( .A(n2014), .B(n2015), .Y(n423) );
INVX6TS U910 ( .A(n679), .Y(n3159) );
INVX2TS U911 ( .A(n2637), .Y(n2666) );
NOR2X2TS U912 ( .A(n2389), .B(n2388), .Y(n2401) );
NAND2XLTS U913 ( .A(n4614), .B(n4662), .Y(n2210) );
BUFX16TS U914 ( .A(n2189), .Y(n2472) );
CLKINVX2TS U915 ( .A(n2852), .Y(n546) );
NOR2X2TS U916 ( .A(n2220), .B(DP_OP_153J6_122_5442_n451), .Y(n2221) );
INVX6TS U917 ( .A(n1220), .Y(n2105) );
INVX4TS U918 ( .A(n1790), .Y(n1777) );
INVX8TS U919 ( .A(n489), .Y(n2905) );
NAND2X2TS U920 ( .A(n1311), .B(n2234), .Y(n1264) );
INVX2TS U921 ( .A(n533), .Y(n2403) );
INVX2TS U922 ( .A(n2056), .Y(n476) );
NOR2X4TS U923 ( .A(n696), .B(n1096), .Y(n3257) );
NOR2X6TS U924 ( .A(n874), .B(n2677), .Y(n2735) );
BUFX8TS U925 ( .A(n2850), .Y(n1078) );
NAND2X1TS U926 ( .A(n1656), .B(n1707), .Y(n1609) );
CLKXOR2X2TS U927 ( .A(n1547), .B(n1587), .Y(n1559) );
OAI22X2TS U928 ( .A0(n2679), .A1(n2736), .B0(n2571), .B1(n3660), .Y(n2628)
);
INVX3TS U929 ( .A(n2102), .Y(n2040) );
CLKINVX3TS U930 ( .A(n2013), .Y(n1998) );
INVX8TS U931 ( .A(n2150), .Y(n2282) );
NOR2X4TS U932 ( .A(n2195), .B(n2468), .Y(n2470) );
OAI21X2TS U933 ( .A0(n1588), .A1(n1587), .B0(n1586), .Y(n1620) );
NAND2X1TS U934 ( .A(n1619), .B(n1618), .Y(n1621) );
INVX2TS U935 ( .A(n3984), .Y(n2738) );
INVX2TS U936 ( .A(n2169), .Y(n2158) );
INVX8TS U937 ( .A(n1815), .Y(n1337) );
NAND2X4TS U938 ( .A(n1997), .B(n1996), .Y(n2013) );
INVX2TS U939 ( .A(n1108), .Y(n2159) );
NAND2X4TS U940 ( .A(n1580), .B(n1579), .Y(n1650) );
INVX6TS U941 ( .A(n2029), .Y(n1882) );
NOR2BX2TS U942 ( .AN(n2067), .B(n2066), .Y(n1242) );
NAND2X4TS U943 ( .A(n2348), .B(n2347), .Y(n2383) );
NAND2X4TS U944 ( .A(n1368), .B(n1367), .Y(n1653) );
NAND2X4TS U945 ( .A(n508), .B(n507), .Y(n1922) );
NAND2BX2TS U946 ( .AN(n1588), .B(n1586), .Y(n1547) );
INVX3TS U947 ( .A(n3985), .Y(n773) );
CLKINVX6TS U948 ( .A(n2181), .Y(n2469) );
NAND2X1TS U949 ( .A(n2676), .B(n2669), .Y(n1707) );
INVX2TS U950 ( .A(n1538), .Y(n1386) );
OR2X4TS U951 ( .A(n2348), .B(n2346), .Y(n2380) );
NAND2X4TS U952 ( .A(n1293), .B(n1291), .Y(n2236) );
NAND2BX2TS U953 ( .AN(n3292), .B(n1257), .Y(n600) );
NAND2X1TS U954 ( .A(n1615), .B(n1614), .Y(n1616) );
BUFX6TS U955 ( .A(n2897), .Y(n1059) );
INVX4TS U956 ( .A(n2194), .Y(n2468) );
NAND2X4TS U957 ( .A(n1288), .B(n727), .Y(n2163) );
INVX2TS U958 ( .A(n1704), .Y(n1601) );
INVX2TS U959 ( .A(n2384), .Y(n2381) );
AOI2BB2X2TS U960 ( .B0(n2636), .B1(n4684), .A0N(n2679), .A1N(
DP_OP_154J6_123_2038_n312), .Y(n2637) );
INVX4TS U961 ( .A(n2151), .Y(n1790) );
XNOR2X2TS U962 ( .A(n1066), .B(DP_OP_153J6_122_5442_n1466), .Y(n1305) );
XNOR2X2TS U963 ( .A(n2471), .B(n2124), .Y(n2125) );
NAND2X4TS U964 ( .A(n558), .B(n2052), .Y(n2015) );
INVX2TS U965 ( .A(n2183), .Y(n2467) );
OR2X4TS U966 ( .A(n3310), .B(n1963), .Y(n775) );
XNOR2X2TS U967 ( .A(n1558), .B(n1557), .Y(n2756) );
NAND2X1TS U968 ( .A(n2283), .B(DP_OP_153J6_122_5442_n451), .Y(n2143) );
INVX2TS U969 ( .A(n2162), .Y(n1288) );
INVX2TS U970 ( .A(n2676), .Y(n1187) );
INVX6TS U971 ( .A(n2028), .Y(n1901) );
INVX3TS U972 ( .A(n1580), .Y(n1368) );
NAND2X2TS U973 ( .A(n1124), .B(n1123), .Y(n1874) );
OAI2BB1X2TS U974 ( .A0N(DP_OP_155J6_124_2038_n703), .A1N(
DP_OP_155J6_124_2038_n698), .B0(n1407), .Y(n3136) );
NOR2X6TS U975 ( .A(n2355), .B(n2356), .Y(n2384) );
NAND2X2TS U976 ( .A(n2053), .B(n2054), .Y(n558) );
INVX2TS U977 ( .A(n3226), .Y(n1930) );
CLKINVX2TS U978 ( .A(n1579), .Y(n1367) );
NAND2X2TS U979 ( .A(n1995), .B(n1994), .Y(n2052) );
INVX2TS U980 ( .A(n1996), .Y(n1412) );
OAI21X1TS U981 ( .A0(n2283), .A1(DP_OP_153J6_122_5442_n451), .B0(n2471), .Y(
n2144) );
NAND2X2TS U982 ( .A(n1543), .B(n1542), .Y(n1586) );
BUFX3TS U983 ( .A(n3182), .Y(n462) );
INVX2TS U984 ( .A(n1405), .Y(n794) );
CLKXOR2X4TS U985 ( .A(n4603), .B(n4604), .Y(n2408) );
OR2X4TS U986 ( .A(n1590), .B(n1589), .Y(n1619) );
NAND2X6TS U987 ( .A(n757), .B(n729), .Y(n1478) );
NAND2BX2TS U988 ( .AN(n2576), .B(n1053), .Y(n1315) );
INVX6TS U989 ( .A(n2669), .Y(n608) );
NOR2X6TS U990 ( .A(n1612), .B(n1613), .Y(n1704) );
AND2X4TS U991 ( .A(n4654), .B(DP_OP_153J6_122_5442_n1099), .Y(n429) );
NAND2X2TS U992 ( .A(n4657), .B(n4587), .Y(n491) );
OAI21X2TS U993 ( .A0(n2733), .A1(n869), .B0(n1017), .Y(n1737) );
NAND2X6TS U994 ( .A(n493), .B(n431), .Y(n492) );
OAI22X1TS U995 ( .A0(n1480), .A1(n3144), .B0(n873), .B1(n3186), .Y(n1932) );
OR2X4TS U996 ( .A(n2338), .B(n4428), .Y(n2350) );
OR2X4TS U997 ( .A(n1488), .B(n1066), .Y(n1236) );
OR2X4TS U998 ( .A(n1043), .B(n1331), .Y(n1328) );
NAND2BX2TS U999 ( .AN(n3140), .B(n3250), .Y(n507) );
NAND2X2TS U1000 ( .A(n1667), .B(n1668), .Y(n1088) );
OAI22X2TS U1001 ( .A0(n397), .A1(n3293), .B0(n852), .B1(n3309), .Y(n1898) );
XOR2X2TS U1002 ( .A(n3240), .B(n3241), .Y(n1275) );
INVX2TS U1003 ( .A(n1912), .Y(n400) );
OAI22X2TS U1004 ( .A0(n2737), .A1(n1741), .B0(n876), .B1(n2572), .Y(n1696)
);
AND2X6TS U1005 ( .A(n2151), .B(DP_OP_153J6_122_5442_n827), .Y(n1108) );
INVX4TS U1006 ( .A(n2026), .Y(n1150) );
INVX2TS U1007 ( .A(n1462), .Y(n1460) );
INVX2TS U1008 ( .A(n3227), .Y(n1149) );
OR2X6TS U1009 ( .A(n2150), .B(DP_OP_153J6_122_5442_n828), .Y(n2169) );
OR2X2TS U1010 ( .A(n1016), .B(n2667), .Y(n1017) );
NAND2X6TS U1011 ( .A(n3192), .B(n962), .Y(n2050) );
BUFX3TS U1012 ( .A(n1957), .Y(n1046) );
NAND2X2TS U1013 ( .A(n2028), .B(n2029), .Y(n2067) );
OR2X4TS U1014 ( .A(n1995), .B(n1994), .Y(n2053) );
AND2X4TS U1015 ( .A(n811), .B(n812), .Y(n810) );
NAND2X6TS U1016 ( .A(n2185), .B(n538), .Y(n2188) );
INVX4TS U1017 ( .A(n1857), .Y(n3292) );
CLKINVX6TS U1018 ( .A(n1671), .Y(n3660) );
INVX4TS U1019 ( .A(n1877), .Y(n3309) );
NOR2X2TS U1020 ( .A(DP_OP_155J6_124_2038_n723), .B(n682), .Y(n3183) );
INVX4TS U1021 ( .A(n1463), .Y(n1461) );
OAI22X2TS U1022 ( .A0(n2679), .A1(n2576), .B0(n2571), .B1(n2642), .Y(n1693)
);
INVX2TS U1023 ( .A(n2197), .Y(n1261) );
BUFX6TS U1024 ( .A(n1480), .Y(n416) );
INVX2TS U1025 ( .A(n3153), .Y(n704) );
BUFX3TS U1026 ( .A(n2638), .Y(n1098) );
INVX4TS U1027 ( .A(n1629), .Y(n1682) );
NOR2X4TS U1028 ( .A(DP_OP_154J6_123_2038_n716), .B(DP_OP_154J6_123_2038_n718), .Y(n1726) );
CLKAND2X2TS U1029 ( .A(n4709), .B(n801), .Y(n721) );
INVX4TS U1030 ( .A(n1859), .Y(n3256) );
NOR2X2TS U1031 ( .A(n1171), .B(n1741), .Y(n1558) );
INVX2TS U1032 ( .A(n1605), .Y(n1660) );
NOR2X4TS U1033 ( .A(DP_OP_154J6_123_2038_n714), .B(DP_OP_154J6_123_2038_n720), .Y(n1725) );
OA21X2TS U1034 ( .A0(n1991), .A1(n2068), .B0(n2069), .Y(n2063) );
INVX2TS U1035 ( .A(n2207), .Y(n580) );
NAND2X1TS U1036 ( .A(n3365), .B(n3364), .Y(n1158) );
OAI2BB1X2TS U1037 ( .A0N(n3366), .A1N(n1164), .B0(n1161), .Y(n1548) );
CLKXOR2X2TS U1038 ( .A(n1585), .B(n1584), .Y(n762) );
INVX12TS U1039 ( .A(n2038), .Y(n3153) );
NAND3X6TS U1040 ( .A(n2123), .B(n4596), .C(DP_OP_153J6_122_5442_n1181), .Y(
n1255) );
INVX4TS U1041 ( .A(n1445), .Y(n449) );
ADDFHX2TS U1042 ( .A(n4430), .B(n4431), .CI(n631), .CO(n2406), .S(n2393) );
OAI21X2TS U1043 ( .A0(n1846), .A1(n1884), .B0(n1845), .Y(n776) );
NOR2X4TS U1044 ( .A(n852), .B(n3293), .Y(n1879) );
OR2X2TS U1045 ( .A(n1883), .B(n1846), .Y(n551) );
NAND2X2TS U1046 ( .A(n4653), .B(n4660), .Y(n538) );
INVX2TS U1047 ( .A(n3205), .Y(n1953) );
INVX6TS U1048 ( .A(n974), .Y(n960) );
INVX6TS U1049 ( .A(n1848), .Y(n3293) );
INVX8TS U1050 ( .A(n1631), .Y(n2736) );
INVX4TS U1051 ( .A(n1576), .Y(n1647) );
INVX2TS U1052 ( .A(n1585), .Y(n759) );
OAI21X2TS U1053 ( .A0(n1491), .A1(n988), .B0(n989), .Y(n986) );
CLKINVX6TS U1054 ( .A(DP_OP_155J6_124_2038_n723), .Y(n1464) );
OR2X4TS U1055 ( .A(n2022), .B(n2021), .Y(n3113) );
INVX1TS U1056 ( .A(n1584), .Y(n760) );
NAND2X1TS U1057 ( .A(n2110), .B(n2610), .Y(n2069) );
INVX4TS U1058 ( .A(n1873), .Y(n899) );
BUFX3TS U1059 ( .A(n2679), .Y(n876) );
NOR2X2TS U1060 ( .A(n2110), .B(n2610), .Y(n2068) );
OAI22X2TS U1061 ( .A0(n1171), .A1(n2642), .B0(n869), .B1(n2576), .Y(n1583)
);
NAND2X2TS U1062 ( .A(n765), .B(n1845), .Y(n766) );
INVX3TS U1063 ( .A(n3364), .Y(n3366) );
INVX8TS U1064 ( .A(n2039), .Y(n974) );
INVX4TS U1065 ( .A(n1571), .Y(n2642) );
INVX12TS U1066 ( .A(n851), .Y(n398) );
NAND2X2TS U1067 ( .A(n1739), .B(n1669), .Y(n927) );
INVX4TS U1068 ( .A(n1639), .Y(n2733) );
INVX4TS U1069 ( .A(n1844), .Y(n1987) );
NAND2X2TS U1070 ( .A(n1392), .B(n1391), .Y(n1604) );
INVX4TS U1071 ( .A(n1856), .Y(n3186) );
NOR2X6TS U1072 ( .A(n1171), .B(n2576), .Y(n1573) );
INVX4TS U1073 ( .A(n1540), .Y(n1741) );
INVX4TS U1074 ( .A(n1541), .Y(n2572) );
INVX8TS U1075 ( .A(n1855), .Y(n3144) );
NOR2X6TS U1076 ( .A(n2021), .B(n1082), .Y(n1864) );
NAND2BX2TS U1077 ( .AN(n2605), .B(n1986), .Y(n1417) );
NAND2X4TS U1078 ( .A(n2020), .B(n2019), .Y(n3118) );
INVX2TS U1079 ( .A(n1884), .Y(n1045) );
INVX8TS U1080 ( .A(n599), .Y(n1480) );
INVX6TS U1081 ( .A(n1539), .Y(n2576) );
INVX8TS U1082 ( .A(n1565), .Y(n2592) );
NAND2X4TS U1083 ( .A(DP_OP_154J6_123_2038_n682), .B(
DP_OP_154J6_123_2038_n782), .Y(n1739) );
INVX4TS U1084 ( .A(n1891), .Y(n3140) );
INVX4TS U1085 ( .A(n1847), .Y(n1989) );
INVX12TS U1086 ( .A(n681), .Y(n682) );
INVX6TS U1087 ( .A(n1566), .Y(n2667) );
INVX6TS U1088 ( .A(n698), .Y(n699) );
INVX4TS U1089 ( .A(n1567), .Y(n2677) );
CLKINVX6TS U1090 ( .A(n2018), .Y(n2605) );
NAND2X6TS U1091 ( .A(n3206), .B(n2020), .Y(n573) );
INVX6TS U1092 ( .A(n1849), .Y(n3251) );
CLKINVX2TS U1093 ( .A(n2017), .Y(n2019) );
NOR2X2TS U1094 ( .A(n4710), .B(n809), .Y(n1608) );
NAND2X4TS U1095 ( .A(n703), .B(Op_MX[18]), .Y(n731) );
CMPR22X2TS U1096 ( .A(DP_OP_154J6_123_2038_n795), .B(
DP_OP_154J6_123_2038_n687), .CO(n1671), .S(n1631) );
NAND2X2TS U1097 ( .A(n1394), .B(n1393), .Y(n1391) );
INVX3TS U1098 ( .A(n459), .Y(n458) );
OR2X4TS U1099 ( .A(n4519), .B(n618), .Y(n2017) );
NOR2X6TS U1100 ( .A(n440), .B(n809), .Y(n1394) );
INVX3TS U1101 ( .A(n1563), .Y(n1569) );
NAND2X2TS U1102 ( .A(n4568), .B(n1958), .Y(n1964) );
AND2X4TS U1103 ( .A(n685), .B(n1958), .Y(n1851) );
NAND2X4TS U1104 ( .A(n1441), .B(DP_OP_155J6_124_2038_n623), .Y(n606) );
INVX4TS U1105 ( .A(n1890), .Y(n2037) );
INVX2TS U1106 ( .A(n684), .Y(n685) );
INVX6TS U1107 ( .A(n1892), .Y(n1963) );
BUFX8TS U1108 ( .A(n780), .Y(n587) );
CLKINVX6TS U1109 ( .A(n706), .Y(n707) );
INVX4TS U1110 ( .A(n1564), .Y(n2627) );
NOR2X2TS U1111 ( .A(n4482), .B(DP_OP_155J6_124_2038_n641), .Y(n1493) );
CMPR22X2TS U1112 ( .A(DP_OP_155J6_124_2038_n790), .B(
DP_OP_155J6_124_2038_n784), .CO(n1856), .S(n1855) );
NAND2X4TS U1113 ( .A(n676), .B(n677), .Y(n675) );
CLKINVX6TS U1114 ( .A(n4480), .Y(n894) );
NOR2X2TS U1115 ( .A(n802), .B(n800), .Y(n1531) );
AND2X4TS U1116 ( .A(n1454), .B(DP_OP_154J6_123_2038_n611), .Y(n1509) );
NOR2X6TS U1117 ( .A(DP_OP_154J6_123_2038_n631), .B(n802), .Y(n1517) );
BUFX16TS U1118 ( .A(DP_OP_154J6_123_2038_n722), .Y(n438) );
XOR2X4TS U1119 ( .A(n3894), .B(n3893), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]) );
BUFX20TS U1120 ( .A(n2855), .Y(n3522) );
XNOR2X4TS U1121 ( .A(n2714), .B(n2713), .Y(n2715) );
OAI21X4TS U1122 ( .A0(n4194), .A1(n3061), .B0(n2711), .Y(n2714) );
CLKINVX12TS U1123 ( .A(n3061), .Y(n2803) );
NAND2X8TS U1124 ( .A(n3589), .B(n2442), .Y(n3061) );
NAND3X4TS U1125 ( .A(n2998), .B(n2997), .C(n2996), .Y(n212) );
NOR2X4TS U1126 ( .A(n4021), .B(n2375), .Y(n2377) );
NOR2X6TS U1127 ( .A(n2371), .B(n642), .Y(n4082) );
OAI21X4TS U1128 ( .A0(n4194), .A1(n2807), .B0(n2806), .Y(n2810) );
CLKINVX6TS U1129 ( .A(n2701), .Y(n2593) );
XOR2X4TS U1130 ( .A(n4086), .B(n4085), .Y(n4087) );
INVX6TS U1131 ( .A(DP_OP_156J6_125_3370_n299), .Y(
Sgf_operation_EVEN1_Q_left[13]) );
XNOR2X4TS U1132 ( .A(n2810), .B(n2809), .Y(n2811) );
NAND3X4TS U1133 ( .A(n4118), .B(n4117), .C(n4116), .Y(n211) );
AOI2BB2X4TS U1134 ( .B0(n4236), .B1(n271), .A0N(n860), .A1N(n4764), .Y(n4117) );
BUFX6TS U1135 ( .A(n486), .Y(n467) );
INVX8TS U1136 ( .A(n938), .Y(n3478) );
XNOR2X4TS U1137 ( .A(n3606), .B(n3605), .Y(n3607) );
OAI21X4TS U1138 ( .A0(n4194), .A1(n4095), .B0(n4096), .Y(n3606) );
INVX4TS U1139 ( .A(n1668), .Y(n1091) );
XOR2X4TS U1140 ( .A(n796), .B(n3841), .Y(DP_OP_36J6_126_4699_n22) );
NAND2X8TS U1141 ( .A(n535), .B(n4914), .Y(n4235) );
ADDFHX4TS U1142 ( .A(n4427), .B(n628), .CI(n2428), .CO(n2454), .S(n2429) );
NAND2X4TS U1143 ( .A(n3897), .B(n3896), .Y(DP_OP_153J6_122_5442_n4) );
NAND2X4TS U1144 ( .A(n3890), .B(n3889), .Y(DP_OP_153J6_122_5442_n6) );
NOR2X6TS U1145 ( .A(n3884), .B(n3888), .Y(n1194) );
AOI2BB2X4TS U1146 ( .B0(n441), .B1(n268), .A0N(n858), .A1N(n4767), .Y(n4111)
);
MX2X6TS U1147 ( .A(n2620), .B(n4909), .S0(n667), .Y(n268) );
NAND2X4TS U1148 ( .A(DP_OP_153J6_122_5442_n40), .B(n3898), .Y(
DP_OP_153J6_122_5442_n5) );
BUFX12TS U1149 ( .A(n2180), .Y(n2543) );
NAND2X8TS U1150 ( .A(n3060), .B(n3066), .Y(n3070) );
ADDFHX4TS U1151 ( .A(n2831), .B(n2832), .CI(n2833), .CO(n2894), .S(n2862) );
INVX6TS U1152 ( .A(n3891), .Y(DP_OP_153J6_122_5442_n40) );
XNOR2X4TS U1153 ( .A(n2464), .B(n2463), .Y(n2465) );
OAI21X4TS U1154 ( .A0(n4194), .A1(n2446), .B0(n2445), .Y(n2464) );
NOR2X8TS U1155 ( .A(n2440), .B(n649), .Y(n3596) );
NAND3X4TS U1156 ( .A(n3095), .B(n3094), .C(n3093), .Y(n214) );
NAND2X8TS U1157 ( .A(n791), .B(n4916), .Y(n4209) );
NAND2X4TS U1158 ( .A(n4937), .B(n4216), .Y(n4954) );
AOI21X4TS U1159 ( .A0(n4216), .A1(n4206), .B0(n787), .Y(n786) );
NAND2X2TS U1160 ( .A(Sgf_operation_EVEN1_S_B[3]), .B(
Sgf_operation_EVEN1_Q_right[15]), .Y(add_x_19_n297) );
NOR2X8TS U1161 ( .A(n2263), .B(n2262), .Y(n2829) );
NAND3X6TS U1162 ( .A(n4221), .B(n4220), .C(n4219), .Y(n222) );
OAI21X4TS U1163 ( .A0(n877), .A1(n4182), .B0(n4181), .Y(n4184) );
INVX4TS U1164 ( .A(n529), .Y(n531) );
NOR2X8TS U1165 ( .A(n3887), .B(n3886), .Y(n3891) );
NAND2X6TS U1166 ( .A(n937), .B(n3477), .Y(n3219) );
ADDFHX4TS U1167 ( .A(n4419), .B(n4420), .CI(n2406), .CO(n2415), .S(n2396) );
NAND2X8TS U1168 ( .A(n789), .B(n662), .Y(n788) );
INVX6TS U1169 ( .A(n3776), .Y(n3778) );
NOR2X4TS U1170 ( .A(n4188), .B(n4178), .Y(n4179) );
INVX12TS U1171 ( .A(n1084), .Y(n4188) );
OR2X6TS U1172 ( .A(n4223), .B(n1080), .Y(n4225) );
NOR2X4TS U1173 ( .A(n4165), .B(n4171), .Y(n4126) );
AOI2BB2X4TS U1174 ( .B0(n441), .B1(n274), .A0N(n858), .A1N(n4761), .Y(n3094)
);
MX2X6TS U1175 ( .A(n3091), .B(n4919), .S0(n658), .Y(n274) );
NAND2X4TS U1176 ( .A(n3882), .B(n3881), .Y(n3883) );
XNOR2X4TS U1177 ( .A(n2619), .B(n2618), .Y(n2620) );
ADDFHX4TS U1178 ( .A(n3128), .B(n2259), .CI(n2258), .CO(n2269), .S(n2272) );
OR2X8TS U1179 ( .A(n1132), .B(n2994), .Y(n1302) );
NAND2X2TS U1180 ( .A(n3830), .B(add_x_19_n300), .Y(add_x_19_n30) );
NAND2X6TS U1181 ( .A(n1482), .B(DP_OP_153J6_122_5442_n1190), .Y(n1759) );
NAND2X6TS U1182 ( .A(n531), .B(n621), .Y(n3063) );
INVX16TS U1183 ( .A(n1832), .Y(n839) );
ADDFHX4TS U1184 ( .A(n2939), .B(n2938), .CI(n2937), .CO(n2979), .S(n2954) );
NAND2X6TS U1185 ( .A(n3493), .B(n691), .Y(n917) );
NOR2X4TS U1186 ( .A(n3536), .B(n845), .Y(n3559) );
NAND2X8TS U1187 ( .A(n1363), .B(n1106), .Y(n1295) );
NAND2X6TS U1188 ( .A(n1324), .B(n2904), .Y(n1106) );
NOR2X2TS U1189 ( .A(n3891), .B(n3895), .Y(DP_OP_153J6_122_5442_n35) );
INVX4TS U1190 ( .A(n3895), .Y(n3897) );
NAND2X8TS U1191 ( .A(n4223), .B(n1080), .Y(n4224) );
BUFX12TS U1192 ( .A(n4222), .Y(n1080) );
AOI2BB2X4TS U1193 ( .B0(n4233), .B1(n4216), .A0N(n858), .A1N(n4759), .Y(
n4220) );
NAND2X8TS U1194 ( .A(n788), .B(n4920), .Y(n4216) );
OAI21X4TS U1195 ( .A0(n2447), .A1(n2761), .B0(n2764), .Y(n2448) );
INVX8TS U1196 ( .A(n2613), .Y(n1156) );
NAND2X4TS U1197 ( .A(n4448), .B(n3781), .Y(DP_OP_156J6_125_3370_n16) );
OR2X8TS U1198 ( .A(n3828), .B(n3829), .Y(n3830) );
NAND3X4TS U1199 ( .A(n709), .B(n4587), .C(n2126), .Y(n540) );
NAND2X4TS U1200 ( .A(n709), .B(n2126), .Y(n493) );
ADDFHX4TS U1201 ( .A(n3583), .B(n3582), .CI(n3581), .CO(n3783), .S(n3568) );
NAND3X6TS U1202 ( .A(n782), .B(n2762), .C(n2767), .Y(n1068) );
NAND2X8TS U1203 ( .A(n705), .B(n1752), .Y(n1702) );
BUFX8TS U1204 ( .A(n1746), .Y(n465) );
NAND2X4TS U1205 ( .A(Sgf_operation_EVEN1_Q_left[15]), .B(
Sgf_operation_EVEN1_Q_left[14]), .Y(add_x_19_n104) );
NAND2X4TS U1206 ( .A(Sgf_operation_EVEN1_Q_right[16]), .B(
Sgf_operation_EVEN1_S_B[4]), .Y(add_x_19_n291) );
OAI2BB1X4TS U1207 ( .A0N(n3815), .A1N(n3816), .B0(n1070), .Y(n2120) );
NOR2X2TS U1208 ( .A(n4164), .B(n4134), .Y(n4136) );
NAND2X6TS U1209 ( .A(n1134), .B(n580), .Y(n579) );
NOR2X4TS U1210 ( .A(n1481), .B(DP_OP_153J6_122_5442_n870), .Y(n1134) );
INVX16TS U1211 ( .A(n925), .Y(n2283) );
OAI21X4TS U1212 ( .A0(n877), .A1(n4141), .B0(n4140), .Y(n4142) );
AOI21X4TS U1213 ( .A0(n1069), .A1(n4138), .B0(n1084), .Y(n4140) );
ADDFHX2TS U1214 ( .A(n1693), .B(n1692), .CI(n1691), .S(n402) );
NAND3X4TS U1215 ( .A(n991), .B(n990), .C(n1448), .Y(n972) );
NAND2X8TS U1216 ( .A(n2009), .B(n2008), .Y(n2108) );
NAND2X8TS U1217 ( .A(n3491), .B(n830), .Y(n892) );
CLKINVX12TS U1218 ( .A(n918), .Y(n1380) );
BUFX6TS U1219 ( .A(n1144), .Y(n391) );
CLKINVX12TS U1220 ( .A(n926), .Y(n1281) );
OAI2BB1X4TS U1221 ( .A0N(n1733), .A1N(n822), .B0(n392), .Y(n2565) );
OAI21X4TS U1222 ( .A0(n822), .A1(n1733), .B0(n1731), .Y(n392) );
BUFX6TS U1223 ( .A(DP_OP_154J6_123_2038_n632), .Y(n394) );
INVX16TS U1224 ( .A(n510), .Y(n1277) );
OR2X8TS U1225 ( .A(n3640), .B(n3639), .Y(n3880) );
NOR2X6TS U1226 ( .A(DP_OP_154J6_123_2038_n630), .B(n802), .Y(n1523) );
AND2X8TS U1227 ( .A(n695), .B(n821), .Y(n1686) );
NOR2X8TS U1228 ( .A(DP_OP_154J6_123_2038_n636), .B(DP_OP_154J6_123_2038_n628), .Y(n1532) );
INVX4TS U1229 ( .A(n3279), .Y(n1120) );
NAND2BX4TS U1230 ( .AN(n959), .B(n611), .Y(n956) );
XNOR2X4TS U1231 ( .A(n396), .B(n2581), .Y(n395) );
XNOR2X4TS U1232 ( .A(n2582), .B(n2583), .Y(n396) );
BUFX20TS U1233 ( .A(n1988), .Y(n851) );
INVX16TS U1234 ( .A(n851), .Y(n397) );
AND2X8TS U1235 ( .A(n466), .B(n3720), .Y(n399) );
INVX12TS U1236 ( .A(n399), .Y(n502) );
INVX3TS U1237 ( .A(n3975), .Y(n497) );
NAND2X4TS U1238 ( .A(n3203), .B(n3202), .Y(n3279) );
OR2X6TS U1239 ( .A(n3203), .B(n3202), .Y(n1122) );
NAND2BX2TS U1240 ( .AN(n771), .B(n3181), .Y(n767) );
NAND2X8TS U1241 ( .A(n501), .B(n3647), .Y(n1215) );
CLKINVX12TS U1242 ( .A(n1424), .Y(n992) );
XNOR2X4TS U1243 ( .A(n1151), .B(n400), .Y(n1952) );
XOR2X4TS U1244 ( .A(n3816), .B(n401), .Y(n806) );
CLKXOR2X4TS U1245 ( .A(n2192), .B(n2191), .Y(n2193) );
INVX16TS U1246 ( .A(n2127), .Y(n2474) );
OAI22X4TS U1247 ( .A0(n2261), .A1(n2474), .B0(n2535), .B1(n2475), .Y(n3869)
);
BUFX8TS U1248 ( .A(n1823), .Y(n611) );
AND2X6TS U1249 ( .A(n504), .B(n3352), .Y(n503) );
NAND2X6TS U1250 ( .A(n1369), .B(n426), .Y(n1235) );
BUFX12TS U1251 ( .A(n984), .Y(n909) );
NAND2X6TS U1252 ( .A(n2594), .B(n2595), .Y(n1179) );
NAND3X8TS U1253 ( .A(n832), .B(n1432), .C(n1188), .Y(n1204) );
ADDFHX2TS U1254 ( .A(n3296), .B(n3295), .CI(n3294), .CO(n3314), .S(n3299) );
NAND2XLTS U1255 ( .A(n3694), .B(n1745), .Y(n3710) );
NAND2X6TS U1256 ( .A(n966), .B(n1453), .Y(n926) );
NAND2X8TS U1257 ( .A(n528), .B(n527), .Y(n1064) );
INVX6TS U1258 ( .A(n3231), .Y(n3151) );
CLKBUFX2TS U1259 ( .A(n3230), .Y(n1104) );
INVX6TS U1260 ( .A(n3229), .Y(n1881) );
INVX2TS U1261 ( .A(n833), .Y(n409) );
INVX2TS U1262 ( .A(n412), .Y(n413) );
OR2X4TS U1263 ( .A(n1480), .B(n1963), .Y(n1446) );
OR2X4TS U1264 ( .A(n2839), .B(n2905), .Y(n428) );
XOR2X4TS U1265 ( .A(n2839), .B(n1142), .Y(n1769) );
NAND2X4TS U1266 ( .A(n536), .B(n665), .Y(n535) );
NOR2X4TS U1267 ( .A(n869), .B(DP_OP_154J6_123_2038_n312), .Y(n1170) );
OAI22X2TS U1268 ( .A0(n1031), .A1(DP_OP_154J6_123_2038_n312), .B0(n2737),
.B1(n4683), .Y(n3663) );
MX2X4TS U1269 ( .A(n4845), .B(n4844), .S0(n666), .Y(n251) );
MX2X6TS U1270 ( .A(n3024), .B(n4855), .S0(n666), .Y(n255) );
MX2X6TS U1271 ( .A(n3006), .B(n4857), .S0(n666), .Y(n256) );
MX2X6TS U1272 ( .A(n3028), .B(n4854), .S0(n666), .Y(n254) );
MX2X4TS U1273 ( .A(n3001), .B(n4863), .S0(n666), .Y(n258) );
MX2X6TS U1274 ( .A(n4087), .B(n4901), .S0(n667), .Y(n265) );
MX2X6TS U1275 ( .A(n4099), .B(n4902), .S0(n667), .Y(n266) );
MX2X6TS U1276 ( .A(n3607), .B(n4903), .S0(n667), .Y(n267) );
MX2X6TS U1277 ( .A(n4064), .B(n4900), .S0(n667), .Y(n264) );
CLKINVX3TS U1278 ( .A(DP_OP_155J6_124_2038_n390), .Y(n1398) );
NAND2X4TS U1279 ( .A(n1043), .B(n1331), .Y(n1330) );
INVX2TS U1280 ( .A(n2214), .Y(n1378) );
NOR2X2TS U1281 ( .A(n800), .B(n4667), .Y(n1606) );
INVX4TS U1282 ( .A(n1832), .Y(n840) );
INVX2TS U1283 ( .A(n2186), .Y(n2187) );
NOR2X2TS U1284 ( .A(n521), .B(n3292), .Y(n3312) );
OAI2BB1X1TS U1285 ( .A0N(n1655), .A1N(n1662), .B0(n1705), .Y(n1708) );
OR2X4TS U1286 ( .A(n2469), .B(n2468), .Y(n1197) );
OAI22X2TS U1287 ( .A0(n1171), .A1(n2572), .B0(n869), .B1(n1741), .Y(n1542)
);
NAND2X2TS U1288 ( .A(n3138), .B(n3154), .Y(n2049) );
INVX2TS U1289 ( .A(n2096), .Y(n2041) );
NOR2X2TS U1290 ( .A(n2972), .B(n845), .Y(n3500) );
CLKBUFX2TS U1291 ( .A(n2695), .Y(n1035) );
OR2X2TS U1292 ( .A(n731), .B(n711), .Y(n1475) );
NAND2X1TS U1293 ( .A(n4615), .B(n4656), .Y(n2198) );
OAI22X2TS U1294 ( .A0(n1107), .A1(n3520), .B0(n842), .B1(n3498), .Y(n3511)
);
INVX2TS U1295 ( .A(n3515), .Y(n3539) );
NAND2X1TS U1296 ( .A(n3718), .B(n3980), .Y(n3719) );
NAND2X6TS U1297 ( .A(n1112), .B(n3271), .Y(n1117) );
AO21X2TS U1298 ( .A0(n435), .A1(n2520), .B0(n2519), .Y(n2531) );
NAND2X4TS U1299 ( .A(n2289), .B(n2288), .Y(n3377) );
AND4X1TS U1300 ( .A(n4866), .B(n4880), .C(n4881), .D(n4882), .Y(n4265) );
INVX2TS U1301 ( .A(Sgf_operation_EVEN1_Q_left[0]), .Y(n1544) );
NAND2X1TS U1302 ( .A(n4077), .B(n4072), .Y(n4080) );
INVX4TS U1303 ( .A(n1174), .Y(n2130) );
NOR2X6TS U1304 ( .A(n1160), .B(n1165), .Y(n1164) );
INVX2TS U1305 ( .A(n3889), .Y(n1374) );
CLKINVX6TS U1306 ( .A(n4326), .Y(n4364) );
NAND2X1TS U1307 ( .A(n2712), .B(n2780), .Y(n2713) );
NAND2X1TS U1308 ( .A(n4210), .B(n266), .Y(n4107) );
AND2X8TS U1309 ( .A(n2132), .B(n2131), .Y(n424) );
AND2X8TS U1310 ( .A(n1277), .B(n1276), .Y(n426) );
AO21X4TS U1311 ( .A0(n700), .A1(n722), .B0(n1170), .Y(n427) );
OA21X4TS U1312 ( .A0(DP_OP_153J6_122_5442_n870), .A1(n4656), .B0(n4662), .Y(
n432) );
OA21X4TS U1313 ( .A0(n2403), .A1(n2404), .B0(n2402), .Y(n434) );
INVX2TS U1314 ( .A(n3067), .Y(n2804) );
OR2X8TS U1315 ( .A(n1270), .B(n548), .Y(n435) );
OR2X8TS U1316 ( .A(n3270), .B(n3269), .Y(n436) );
OR2X4TS U1317 ( .A(n3848), .B(n3353), .Y(n437) );
CLKINVX12TS U1318 ( .A(DP_OP_154J6_123_2038_n634), .Y(n439) );
INVX16TS U1319 ( .A(n439), .Y(n440) );
NAND3X2TS U1320 ( .A(n1346), .B(n1344), .C(n1342), .Y(n224) );
AOI2BB2X2TS U1321 ( .B0(n4236), .B1(n4231), .A0N(n859), .A1N(n4752), .Y(
n4963) );
AOI2BB2X2TS U1322 ( .B0(n4233), .B1(n4230), .A0N(n860), .A1N(n4751), .Y(
n4959) );
NAND3X2TS U1323 ( .A(n4115), .B(n4114), .C(n4113), .Y(n210) );
MX2X2TS U1324 ( .A(n4250), .B(P_Sgf[10]), .S0(n442), .Y(n248) );
NAND3X2TS U1325 ( .A(n4106), .B(n4105), .C(n4104), .Y(n209) );
MX2X2TS U1326 ( .A(n4405), .B(P_Sgf[9]), .S0(n4938), .Y(n247) );
NAND2X2TS U1327 ( .A(n4206), .B(n269), .Y(n4113) );
XNOR2X1TS U1328 ( .A(n3905), .B(n3904), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]) );
NAND2X2TS U1329 ( .A(n4187), .B(n4175), .Y(n4177) );
NAND2X2TS U1330 ( .A(n3805), .B(n3804), .Y(n3807) );
NAND3X2TS U1331 ( .A(n4103), .B(n4102), .C(n4101), .Y(n206) );
NAND2X2TS U1332 ( .A(n4218), .B(n267), .Y(n4110) );
NAND2X4TS U1333 ( .A(n446), .B(n983), .Y(n982) );
NAND2X4TS U1334 ( .A(n2322), .B(n446), .Y(n2314) );
BUFX6TS U1335 ( .A(n4139), .Y(n1084) );
INVX2TS U1336 ( .A(add_x_55_n46), .Y(n1276) );
INVX2TS U1337 ( .A(n4145), .Y(n4146) );
INVX4TS U1338 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left_8_), .Y(
n3988) );
NOR2X4TS U1339 ( .A(n2875), .B(n2880), .Y(n3922) );
INVX4TS U1340 ( .A(n3438), .Y(n3482) );
INVX3TS U1341 ( .A(n2856), .Y(n1026) );
INVX2TS U1342 ( .A(n1213), .Y(n499) );
AND2X4TS U1343 ( .A(n3394), .B(n3393), .Y(n4315) );
OAI21X1TS U1344 ( .A0(n4002), .A1(n4001), .B0(n3991), .Y(n3993) );
NOR2X4TS U1345 ( .A(n3515), .B(n3516), .Y(n2304) );
MX2X2TS U1346 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(n4985),
.Y(n231) );
INVX4TS U1347 ( .A(n1101), .Y(n1024) );
INVX2TS U1348 ( .A(n3714), .Y(n3693) );
NAND2X4TS U1349 ( .A(n1325), .B(n1321), .Y(n1320) );
INVX2TS U1350 ( .A(n1559), .Y(n906) );
MX2X4TS U1351 ( .A(n4054), .B(n4875), .S0(n626), .Y(n263) );
INVX2TS U1352 ( .A(n2315), .Y(n970) );
INVX8TS U1353 ( .A(n609), .Y(n1129) );
OR2X8TS U1354 ( .A(n4198), .B(n1507), .Y(n3092) );
NAND2X6TS U1355 ( .A(n4198), .B(n2819), .Y(n4065) );
NOR2X4TS U1356 ( .A(n2437), .B(n641), .Y(n4095) );
INVX6TS U1357 ( .A(n2058), .Y(n2056) );
NAND2X2TS U1358 ( .A(n3274), .B(n3273), .Y(n3276) );
AND2X4TS U1359 ( .A(n4502), .B(n4503), .Y(n4505) );
BUFX12TS U1360 ( .A(n4304), .Y(n4305) );
BUFX12TS U1361 ( .A(n4304), .Y(n4309) );
NOR2X4TS U1362 ( .A(n1543), .B(n1542), .Y(n1588) );
INVX6TS U1363 ( .A(n865), .Y(n866) );
NAND2X2TS U1364 ( .A(n2696), .B(n1035), .Y(n2749) );
INVX2TS U1365 ( .A(n2761), .Y(n2434) );
INVX2TS U1366 ( .A(n3255), .Y(n3288) );
MX2X6TS U1367 ( .A(Data_MY[13]), .B(n4928), .S0(n4290), .Y(n3940) );
MX2X1TS U1368 ( .A(n4282), .B(zero_flag), .S0(n4988), .Y(n311) );
INVX1TS U1369 ( .A(n4284), .Y(overflow_flag) );
NOR2X8TS U1370 ( .A(n3731), .B(n753), .Y(n4009) );
MX2X4TS U1371 ( .A(Data_MX[17]), .B(n4929), .S0(n3970), .Y(n4821) );
NAND2X6TS U1372 ( .A(n4989), .B(n4284), .Y(n4020) );
BUFX3TS U1373 ( .A(n3981), .Y(n885) );
MX2X4TS U1374 ( .A(Data_MX[1]), .B(n4934), .S0(n3970), .Y(
DP_OP_155J6_124_2038_n801) );
INVX6TS U1375 ( .A(Sgf_operation_EVEN1_Q_left[1]), .Y(n3116) );
INVX4TS U1376 ( .A(n577), .Y(n575) );
NAND2X6TS U1377 ( .A(n2204), .B(n2199), .Y(n1309) );
BUFX12TS U1378 ( .A(n2125), .Y(n2477) );
INVX4TS U1379 ( .A(n1171), .Y(n700) );
INVX6TS U1380 ( .A(n2705), .Y(n1570) );
NAND2X2TS U1381 ( .A(n4400), .B(n4370), .Y(n4374) );
INVX4TS U1382 ( .A(n4034), .Y(n3079) );
AND2X4TS U1383 ( .A(n2389), .B(n2388), .Y(n533) );
INVX1TS U1384 ( .A(n4353), .Y(n4337) );
INVX2TS U1385 ( .A(n3140), .Y(n516) );
INVX3TS U1386 ( .A(n2599), .Y(n1561) );
BUFX8TS U1387 ( .A(n2335), .Y(n4034) );
NAND4BX1TS U1388 ( .AN(n4926), .B(n4858), .C(n4899), .D(n438), .Y(n4266) );
NAND2X4TS U1389 ( .A(n1488), .B(n1066), .Y(n1310) );
INVX12TS U1390 ( .A(n1850), .Y(n1082) );
NOR2X4TS U1391 ( .A(DP_OP_154J6_123_2038_n714), .B(DP_OP_154J6_123_2038_n718), .Y(n2643) );
INVX2TS U1392 ( .A(n693), .Y(n694) );
INVX2TS U1393 ( .A(rst), .Y(n850) );
NAND3X4TS U1394 ( .A(n930), .B(n932), .C(n928), .Y(n4722) );
OAI2BB1X2TS U1395 ( .A0N(n3818), .A1N(n3817), .B0(n1071), .Y(
DP_OP_156J6_125_3370_n229) );
NAND3X4TS U1396 ( .A(n1376), .B(n1373), .C(n1372), .Y(
DP_OP_153J6_122_5442_n1) );
INVX2TS U1397 ( .A(n3974), .Y(n498) );
MX2X2TS U1398 ( .A(n690), .B(n863), .S0(n4936), .Y(n4743) );
NAND2X2TS U1399 ( .A(n4210), .B(n4230), .Y(n4203) );
NAND2X2TS U1400 ( .A(n4936), .B(n4208), .Y(n4951) );
NOR2X4TS U1401 ( .A(n1404), .B(n1074), .Y(n1403) );
NAND2X4TS U1402 ( .A(n1114), .B(n1113), .Y(n1112) );
NAND2X4TS U1403 ( .A(n3809), .B(n3808), .Y(n556) );
AND2X4TS U1404 ( .A(n3800), .B(n3799), .Y(n3872) );
NAND2X2TS U1405 ( .A(n4218), .B(n271), .Y(n2996) );
NAND2X2TS U1406 ( .A(n3824), .B(n3825), .Y(n3827) );
CLKMX2X3TS U1407 ( .A(n4384), .B(n864), .S0(n4938), .Y(n245) );
CLKMX2X2TS U1408 ( .A(n4404), .B(P_Sgf[8]), .S0(n4938), .Y(n246) );
XNOR2X1TS U1409 ( .A(n2827), .B(n2826), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]) );
AND2X4TS U1410 ( .A(n870), .B(n1201), .Y(n746) );
XNOR2X1TS U1411 ( .A(n3918), .B(n3917), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]) );
NAND2X4TS U1412 ( .A(n2694), .B(n3647), .Y(n483) );
INVX2TS U1413 ( .A(n2298), .Y(n2301) );
INVX2TS U1414 ( .A(n3866), .Y(n3921) );
NAND2X4TS U1415 ( .A(n2319), .B(n2318), .Y(n921) );
NAND2X4TS U1416 ( .A(n1026), .B(n1023), .Y(n1025) );
NAND2X6TS U1417 ( .A(n1387), .B(n2319), .Y(n1388) );
NAND2X4TS U1418 ( .A(n3318), .B(n3317), .Y(n3327) );
NAND2X2TS U1419 ( .A(n3459), .B(n3458), .Y(n3460) );
INVX2TS U1420 ( .A(n3383), .Y(n3385) );
NAND2X2TS U1421 ( .A(n2875), .B(n2880), .Y(n3923) );
INVX6TS U1422 ( .A(n3069), .Y(n2805) );
INVX2TS U1423 ( .A(n3553), .Y(n3554) );
INVX2TS U1424 ( .A(n3721), .Y(n1438) );
INVX2TS U1425 ( .A(n4194), .Y(n1201) );
NAND2X4TS U1426 ( .A(n2318), .B(n2320), .Y(n1387) );
NAND2X6TS U1427 ( .A(n1221), .B(n1223), .Y(n2319) );
OAI21X2TS U1428 ( .A0(n2105), .A1(n2082), .B0(n2081), .Y(n2088) );
INVX6TS U1429 ( .A(n1224), .Y(n1223) );
NAND2X6TS U1430 ( .A(n1397), .B(n1396), .Y(n3691) );
XNOR2X2TS U1431 ( .A(n3993), .B(n692), .Y(n3994) );
CLKMX2X3TS U1432 ( .A(n4315), .B(P_Sgf[6]), .S0(n4936), .Y(n4745) );
MX2X2TS U1433 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(n4985),
.Y(n229) );
NAND2X4TS U1434 ( .A(n3370), .B(n3369), .Y(n3372) );
INVX2TS U1435 ( .A(n3720), .Y(n1208) );
NOR2X1TS U1436 ( .A(n860), .B(n4758), .Y(n1343) );
OA21X2TS U1437 ( .A0(n4002), .A1(n4001), .B0(n4000), .Y(n1504) );
INVX4TS U1438 ( .A(n3690), .Y(n1396) );
NAND2X2TS U1439 ( .A(n2609), .B(n3124), .Y(n2611) );
NAND2X4TS U1440 ( .A(n1024), .B(n570), .Y(n569) );
INVX3TS U1441 ( .A(n884), .Y(n687) );
OA21X2TS U1442 ( .A0(n3860), .A1(n3859), .B0(n3858), .Y(n752) );
MX2X2TS U1443 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(n4985),
.Y(n230) );
NAND2X4TS U1444 ( .A(n768), .B(n767), .Y(n3244) );
NAND2X4TS U1445 ( .A(n957), .B(n956), .Y(n1808) );
INVX8TS U1446 ( .A(n3092), .Y(n4294) );
NAND2X4TS U1447 ( .A(n3392), .B(n3391), .Y(n3393) );
NAND2X2TS U1448 ( .A(n3133), .B(n3132), .Y(n3487) );
INVX2TS U1449 ( .A(n3092), .Y(n4291) );
INVX8TS U1450 ( .A(n3092), .Y(n4293) );
CLKMX2X3TS U1451 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(
n4985), .Y(n232) );
INVX2TS U1452 ( .A(n3277), .Y(n1118) );
INVX2TS U1453 ( .A(n3707), .Y(n1192) );
CLKMX2X2TS U1454 ( .A(n4297), .B(P_Sgf[2]), .S0(n4938), .Y(n240) );
CLKMX2X2TS U1455 ( .A(n4298), .B(P_Sgf[4]), .S0(n4938), .Y(n242) );
CLKMX2X2TS U1456 ( .A(n4296), .B(P_Sgf[3]), .S0(n4938), .Y(n241) );
NOR2X4TS U1457 ( .A(n2439), .B(n646), .Y(n2617) );
ADDHX1TS U1458 ( .A(n4570), .B(n4556), .CO(n670), .S(n669) );
ADDHX1TS U1459 ( .A(n4553), .B(n4571), .CO(n673), .S(n672) );
NAND2X4TS U1460 ( .A(n1409), .B(n3670), .Y(n3714) );
AND2X8TS U1461 ( .A(n4937), .B(n4988), .Y(n4985) );
NAND2X4TS U1462 ( .A(n1329), .B(n1328), .Y(n2575) );
OR2X2TS U1463 ( .A(n4251), .B(beg_FSM), .Y(n4013) );
INVX12TS U1464 ( .A(n1502), .Y(n4937) );
NAND2X6TS U1465 ( .A(n737), .B(n477), .Y(n1220) );
INVX8TS U1466 ( .A(n451), .Y(n1076) );
NOR2X4TS U1467 ( .A(n2516), .B(n2545), .Y(n2521) );
AND2X4TS U1468 ( .A(n2604), .B(n2603), .Y(n2608) );
NOR2X2TS U1469 ( .A(n4253), .B(n1507), .Y(n2818) );
OR2X4TS U1470 ( .A(n3672), .B(n3671), .Y(n1409) );
INVX8TS U1471 ( .A(n1502), .Y(n4938) );
NAND2X2TS U1472 ( .A(n3346), .B(n3854), .Y(n3347) );
INVX4TS U1473 ( .A(n2843), .Y(n2878) );
BUFX6TS U1474 ( .A(n866), .Y(n4251) );
INVX6TS U1475 ( .A(n2050), .Y(n2048) );
NOR2X1TS U1476 ( .A(n4670), .B(n4705), .Y(n4706) );
OAI21X4TS U1477 ( .A0(n3275), .A1(n3272), .B0(n3273), .Y(n3302) );
AND2X2TS U1478 ( .A(n4484), .B(n4487), .Y(n4500) );
OR2X4TS U1479 ( .A(n4484), .B(n4487), .Y(n4494) );
BUFX8TS U1480 ( .A(n4304), .Y(n4306) );
NAND2X4TS U1481 ( .A(n1159), .B(n1158), .Y(n3363) );
INVX3TS U1482 ( .A(n1502), .Y(n442) );
NAND2BX1TS U1483 ( .AN(n4495), .B(DP_OP_155J6_124_2038_n801), .Y(n4524) );
NOR2X1TS U1484 ( .A(n4670), .B(n4690), .Y(n4691) );
INVX2TS U1485 ( .A(n1656), .Y(n1703) );
NOR2X1TS U1486 ( .A(n4495), .B(n4503), .Y(n4522) );
NOR2X1TS U1487 ( .A(n4493), .B(n4502), .Y(n4531) );
NOR2X1TS U1488 ( .A(n4493), .B(n4484), .Y(n4527) );
NOR2X1TS U1489 ( .A(n4526), .B(n4503), .Y(n4525) );
AO21X4TS U1490 ( .A0(n3737), .A1(n3736), .B0(n3735), .Y(n3738) );
INVX12TS U1491 ( .A(n2907), .Y(n448) );
INVX6TS U1492 ( .A(n2236), .Y(n2213) );
OR2X4TS U1493 ( .A(n4502), .B(n4503), .Y(n4549) );
INVX2TS U1494 ( .A(n4061), .Y(n4074) );
OAI21X2TS U1495 ( .A0(n3953), .A1(n4591), .B0(n3954), .Y(n3948) );
INVX4TS U1496 ( .A(n316), .Y(n4529) );
INVX6TS U1497 ( .A(n353), .Y(n4502) );
NOR2X2TS U1498 ( .A(n3940), .B(n4834), .Y(n3953) );
NAND2X2TS U1499 ( .A(n2788), .B(n3076), .Y(n2778) );
INVX4TS U1500 ( .A(n323), .Y(n4504) );
INVX4TS U1501 ( .A(DP_OP_155J6_124_2038_n795), .Y(n4484) );
INVX4TS U1502 ( .A(n312), .Y(n4557) );
INVX4TS U1503 ( .A(n350), .Y(n4490) );
INVX6TS U1504 ( .A(n4834), .Y(n4495) );
INVX4TS U1505 ( .A(DP_OP_155J6_124_2038_n801), .Y(n4487) );
BUFX12TS U1506 ( .A(n2173), .Y(n2914) );
INVX2TS U1507 ( .A(n360), .Y(n4665) );
NAND2X4TS U1508 ( .A(n1819), .B(n1227), .Y(n2602) );
INVX4TS U1509 ( .A(n359), .Y(n4688) );
INVX4TS U1510 ( .A(n3940), .Y(n4666) );
INVX2TS U1511 ( .A(n4821), .Y(n4682) );
INVX4TS U1512 ( .A(n324), .Y(n4694) );
INVX4TS U1513 ( .A(n358), .Y(n4690) );
INVX4TS U1514 ( .A(n799), .Y(n4045) );
NOR2X2TS U1515 ( .A(n875), .B(n2572), .Y(n689) );
INVX1TS U1516 ( .A(n3731), .Y(n3057) );
MX2X6TS U1517 ( .A(Data_MY[20]), .B(n4927), .S0(n3969), .Y(n332) );
NAND2X2TS U1518 ( .A(n2398), .B(n2402), .Y(n2399) );
MX2X6TS U1519 ( .A(Data_MX[9]), .B(n4837), .S0(n4015), .Y(n353) );
NAND2X6TS U1520 ( .A(n1446), .B(n735), .Y(n1445) );
MX2X6TS U1521 ( .A(Data_MY[19]), .B(n4884), .S0(n3969), .Y(n331) );
XNOR2X2TS U1522 ( .A(n2072), .B(n2071), .Y(n3391) );
CLKMX2X2TS U1523 ( .A(n4314), .B(Add_result[2]), .S0(n4935), .Y(n307) );
MX2X6TS U1524 ( .A(Data_MY[15]), .B(n4865), .S0(n4290), .Y(n327) );
MX2X6TS U1525 ( .A(Data_MY[2]), .B(n4923), .S0(n3969), .Y(n314) );
CLKMX2X2TS U1526 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(n4295), .Y(n338) );
INVX8TS U1527 ( .A(n532), .Y(n2519) );
NAND2X4TS U1528 ( .A(n2159), .B(n2161), .Y(n1218) );
CLKMX2X2TS U1529 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n4288), .Y(n374) );
NOR2BX2TS U1530 ( .AN(n2477), .B(n2545), .Y(n2502) );
NAND2X4TS U1531 ( .A(n3717), .B(n1032), .Y(n3980) );
CLKMX2X2TS U1532 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n4295), .Y(n370) );
INVX6TS U1533 ( .A(n4992), .Y(n865) );
INVX8TS U1534 ( .A(FSM_exp_operation_A_S), .Y(n797) );
INVX2TS U1535 ( .A(n2900), .Y(n1841) );
INVX4TS U1536 ( .A(n3100), .Y(n1160) );
BUFX12TS U1537 ( .A(n4289), .Y(n4290) );
INVX2TS U1538 ( .A(n1646), .Y(n2696) );
INVX4TS U1539 ( .A(n3099), .Y(n1518) );
INVX3TS U1540 ( .A(n3101), .Y(n1165) );
NAND2X2TS U1541 ( .A(n2392), .B(n2403), .Y(n2390) );
NOR2X6TS U1542 ( .A(n226), .B(n225), .Y(n4284) );
NOR2X2TS U1543 ( .A(n852), .B(n1989), .Y(n2072) );
NAND2X4TS U1544 ( .A(n588), .B(n1568), .Y(n1062) );
NAND2X4TS U1545 ( .A(n1136), .B(n1274), .Y(n3255) );
NOR2X4TS U1546 ( .A(n3036), .B(n2363), .Y(n4026) );
INVX12TS U1547 ( .A(n1421), .Y(n2153) );
NOR2X4TS U1548 ( .A(n4006), .B(n4746), .Y(n2813) );
INVX2TS U1549 ( .A(n924), .Y(n496) );
NOR2X2TS U1550 ( .A(n4006), .B(FS_Module_state_reg[1]), .Y(n4003) );
NAND2X2TS U1551 ( .A(n2380), .B(n2383), .Y(n2352) );
NAND2BX2TS U1552 ( .AN(n2364), .B(n4034), .Y(n4036) );
NAND2X4TS U1553 ( .A(n1310), .B(DP_OP_153J6_122_5442_n1477), .Y(n1237) );
INVX4TS U1554 ( .A(n4091), .Y(n4006) );
INVX2TS U1555 ( .A(n3038), .Y(n2363) );
NAND2X2TS U1556 ( .A(n2194), .B(n2467), .Y(n2184) );
INVX4TS U1557 ( .A(n1755), .Y(n1545) );
NAND2X4TS U1558 ( .A(n2599), .B(n2598), .Y(n3106) );
NOR2X1TS U1559 ( .A(n4091), .B(n4747), .Y(n4092) );
INVX2TS U1560 ( .A(n3258), .Y(n3290) );
INVX8TS U1561 ( .A(n597), .Y(n1257) );
AND3X2TS U1562 ( .A(n4795), .B(n4871), .C(n3837), .Y(n4256) );
INVX4TS U1563 ( .A(n1846), .Y(n765) );
NOR2X4TS U1564 ( .A(n394), .B(n1042), .Y(Sgf_operation_EVEN1_Q_left[0]) );
NAND4BX1TS U1565 ( .AN(n4805), .B(n4886), .C(n4887), .D(n4260), .Y(n4261) );
INVX4TS U1566 ( .A(n2452), .Y(n2775) );
INVX8TS U1567 ( .A(n520), .Y(n1353) );
NOR2X2TS U1568 ( .A(n4238), .B(n4328), .Y(n4239) );
NAND2X4TS U1569 ( .A(n1756), .B(DP_OP_153J6_122_5442_n1184), .Y(n1757) );
INVX2TS U1570 ( .A(n2450), .Y(n2361) );
INVX4TS U1571 ( .A(n675), .Y(n1562) );
INVX2TS U1572 ( .A(n2045), .Y(n2085) );
CLKMX2X4TS U1573 ( .A(Exp_module_Data_S[7]), .B(n4843), .S0(n663), .Y(n227)
);
NAND2X4TS U1574 ( .A(n4569), .B(n4483), .Y(n601) );
CLKBUFX2TS U1575 ( .A(P_Sgf[7]), .Y(n864) );
CMPR22X2TS U1576 ( .A(DP_OP_154J6_123_2038_n792), .B(
DP_OP_154J6_123_2038_n705), .CO(n1571), .S(n1539) );
CLKBUFX2TS U1577 ( .A(Add_result[11]), .Y(n861) );
NOR2X4TS U1578 ( .A(n4464), .B(n4465), .Y(n3018) );
CMPR22X2TS U1579 ( .A(DP_OP_155J6_124_2038_n793), .B(
DP_OP_155J6_124_2038_n787), .CO(n1877), .S(n1848) );
NAND2X4TS U1580 ( .A(DP_OP_155J6_124_2038_n388), .B(n4481), .Y(n598) );
CLKBUFX2TS U1581 ( .A(P_Sgf[12]), .Y(n882) );
NAND2X2TS U1582 ( .A(n657), .B(n4458), .Y(n3008) );
NOR4BBX1TS U1583 ( .AN(n4894), .BN(n4895), .C(n4931), .D(Op_MX[30]), .Y(
n4275) );
INVX2TS U1584 ( .A(n800), .Y(n801) );
NAND3X2TS U1585 ( .A(n4814), .B(n4813), .C(n4812), .Y(n4356) );
CMPR22X2TS U1586 ( .A(DP_OP_155J6_124_2038_n789), .B(
DP_OP_155J6_124_2038_n783), .CO(n1891), .S(n1892) );
NAND3X2TS U1587 ( .A(n4817), .B(n4816), .C(n4815), .Y(n4340) );
NAND3X2TS U1588 ( .A(n4830), .B(n4829), .C(n4828), .Y(n4346) );
INVX2TS U1589 ( .A(Data_MY[7]), .Y(n3845) );
INVX3TS U1590 ( .A(n1469), .Y(Sgf_operation_EVEN1_Q_right[17]) );
INVX4TS U1591 ( .A(n825), .Y(DP_OP_156J6_125_3370_n270) );
INVX3TS U1592 ( .A(add_x_19_n302), .Y(add_x_19_n301) );
NAND2X6TS U1593 ( .A(n1156), .B(n1155), .Y(n3097) );
INVX8TS U1594 ( .A(n523), .Y(n527) );
NAND2X6TS U1595 ( .A(n972), .B(n3351), .Y(n1167) );
INVX8TS U1596 ( .A(n455), .Y(n1452) );
INVX12TS U1597 ( .A(n503), .Y(n3848) );
NAND2X6TS U1598 ( .A(n1047), .B(n3885), .Y(n3643) );
NAND2X4TS U1599 ( .A(n790), .B(n786), .Y(n223) );
NAND2X4TS U1600 ( .A(n4209), .B(n4210), .Y(n1346) );
NAND2X2TS U1601 ( .A(n4206), .B(n4235), .Y(n4966) );
NAND2X2TS U1602 ( .A(n4214), .B(n4201), .Y(n4986) );
NAND2X2TS U1603 ( .A(n4937), .B(n4235), .Y(n4965) );
NAND2X2TS U1604 ( .A(n4936), .B(n4209), .Y(n4953) );
NAND2X2TS U1605 ( .A(n1301), .B(n3879), .Y(DP_OP_153J6_122_5442_n8) );
NAND2X2TS U1606 ( .A(n4218), .B(n4232), .Y(n4962) );
NAND2X2TS U1607 ( .A(n4206), .B(n4229), .Y(n4974) );
NAND2X2TS U1608 ( .A(n4198), .B(n4197), .Y(n4952) );
NAND2X2TS U1609 ( .A(n4937), .B(n4232), .Y(n4961) );
NAND2X2TS U1610 ( .A(n4937), .B(n4229), .Y(n4973) );
NAND2X6TS U1611 ( .A(n500), .B(n499), .Y(n3972) );
INVX16TS U1612 ( .A(n909), .Y(n443) );
NAND2X2TS U1613 ( .A(n4937), .B(n4230), .Y(n4956) );
NAND2X2TS U1614 ( .A(n4936), .B(n4217), .Y(n4955) );
NAND2X2TS U1615 ( .A(n4218), .B(n274), .Y(n4977) );
NAND2X4TS U1616 ( .A(n3778), .B(n3777), .Y(n3779) );
XOR2X1TS U1617 ( .A(n3827), .B(n3826), .Y(Sgf_operation_EVEN1_S_B[6]) );
NAND2X4TS U1618 ( .A(n3585), .B(n3584), .Y(n3896) );
INVX8TS U1619 ( .A(n1060), .Y(n1440) );
XOR3X2TS U1620 ( .A(n3798), .B(n3797), .C(n3796), .Y(n3799) );
INVX2TS U1621 ( .A(n3823), .Y(n3825) );
INVX4TS U1622 ( .A(n4187), .Y(n3073) );
XOR2X1TS U1623 ( .A(n3913), .B(n3874), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]) );
ADDFHX2TS U1624 ( .A(n3795), .B(n3794), .CI(n3793), .CO(n3796), .S(n3784) );
AND2X2TS U1625 ( .A(add_x_23_n23), .B(n3994), .Y(n4739) );
XNOR2X2TS U1626 ( .A(n3600), .B(n3599), .Y(n3601) );
NAND2X4TS U1627 ( .A(n1388), .B(n2322), .Y(n983) );
NAND2X1TS U1628 ( .A(n3906), .B(n3909), .Y(n3912) );
OAI21X1TS U1629 ( .A0(n3914), .A1(n3907), .B0(n3915), .Y(n2536) );
INVX2TS U1630 ( .A(n3906), .Y(n2824) );
INVX2TS U1631 ( .A(n3910), .Y(n2823) );
NAND2X6TS U1632 ( .A(n1025), .B(n1253), .Y(n2930) );
NAND2X4TS U1633 ( .A(n953), .B(n1184), .Y(n905) );
NAND3X2TS U1634 ( .A(n3732), .B(n3057), .C(n4747), .Y(n3058) );
INVX2TS U1635 ( .A(n3988), .Y(n589) );
OAI21X2TS U1636 ( .A0(n3732), .A1(n3731), .B0(n3730), .Y(n378) );
INVX2TS U1637 ( .A(n3907), .Y(n3908) );
INVX2TS U1638 ( .A(n3525), .Y(n3528) );
AND2X4TS U1639 ( .A(n3692), .B(n3702), .Y(n1009) );
NAND2X2TS U1640 ( .A(n3514), .B(n3527), .Y(n3915) );
NAND2X4TS U1641 ( .A(n3444), .B(n1335), .Y(n1226) );
INVX2TS U1642 ( .A(n1058), .Y(n3382) );
INVX2TS U1643 ( .A(n3922), .Y(n3924) );
INVX4TS U1644 ( .A(n3354), .Y(add_x_55_n46) );
NAND2X2TS U1645 ( .A(n2808), .B(n3064), .Y(n2809) );
NAND2X4TS U1646 ( .A(n3354), .B(n3847), .Y(n3801) );
INVX2TS U1647 ( .A(n3847), .Y(add_x_55_n38) );
INVX2TS U1648 ( .A(n2614), .Y(n1155) );
AND3X2TS U1649 ( .A(Exp_module_Data_S[5]), .B(Exp_module_Data_S[4]), .C(
n4094), .Y(n4987) );
INVX4TS U1650 ( .A(n3533), .Y(n3527) );
NAND3X1TS U1651 ( .A(n4058), .B(n4057), .C(n4056), .Y(n203) );
XNOR2X1TS U1652 ( .A(n3865), .B(n3864), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]) );
NAND3X1TS U1653 ( .A(n4043), .B(n4042), .C(n4041), .Y(n202) );
NAND2X2TS U1654 ( .A(n2990), .B(n3618), .Y(n3907) );
NAND2X2TS U1655 ( .A(n2932), .B(n2933), .Y(n3902) );
NOR2X4TS U1656 ( .A(n3056), .B(n3055), .Y(n3732) );
OAI2BB1X1TS U1657 ( .A0N(n4234), .A1N(Add_result[21]), .B0(n4207), .Y(n787)
);
CLKXOR2X2TS U1658 ( .A(n2611), .B(n3125), .Y(n2614) );
OR2X2TS U1659 ( .A(n3576), .B(n3575), .Y(n3791) );
ADDFHX2TS U1660 ( .A(n2276), .B(n2275), .CI(n2274), .CO(n2267), .S(n2288) );
INVX8TS U1661 ( .A(n1698), .Y(n1351) );
INVX2TS U1662 ( .A(n2304), .Y(n2306) );
NAND2X6TS U1663 ( .A(n2014), .B(n2013), .Y(n2016) );
NAND2X2TS U1664 ( .A(n2496), .B(n2495), .Y(n3928) );
XOR2X2TS U1665 ( .A(n3243), .B(n3242), .Y(n1500) );
INVX2TS U1666 ( .A(n2113), .Y(n1836) );
BUFX16TS U1667 ( .A(n2378), .Y(n4194) );
OAI22X2TS U1668 ( .A0(n3054), .A1(n3053), .B0(round_mode[0]), .B1(
round_mode[1]), .Y(n3056) );
AOI22X1TS U1669 ( .A0(n4293), .A1(Add_result[14]), .B0(n4346), .B1(n4292),
.Y(n4979) );
OAI21X2TS U1670 ( .A0(n3860), .A1(n3338), .B0(n3337), .Y(n3343) );
NAND2X2TS U1671 ( .A(n3110), .B(n3109), .Y(n3112) );
AOI22X1TS U1672 ( .A0(n4293), .A1(Add_result[2]), .B0(
Sgf_normalized_result[1]), .B1(n4253), .Y(n4058) );
INVX2TS U1673 ( .A(n2780), .Y(n2444) );
AOI22X1TS U1674 ( .A0(n4293), .A1(Add_result[16]), .B0(n4340), .B1(n4292),
.Y(n4972) );
INVX2TS U1675 ( .A(n1024), .Y(n838) );
OR2X2TS U1676 ( .A(n3534), .B(n3543), .Y(n1835) );
INVX6TS U1677 ( .A(n3497), .Y(n3501) );
INVX4TS U1678 ( .A(n2760), .Y(n2712) );
INVX2TS U1679 ( .A(n3596), .Y(n3598) );
OAI22X2TS U1680 ( .A0(n2899), .A1(n2915), .B0(n2973), .B1(n3573), .Y(n616)
);
NAND2X2TS U1681 ( .A(n1408), .B(n3711), .Y(n3697) );
INVX2TS U1682 ( .A(n3351), .Y(n1143) );
AO21X2TS U1683 ( .A0(n563), .A1(n1101), .B0(n3551), .Y(n3580) );
AND2X2TS U1684 ( .A(n3871), .B(n3962), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]) );
INVX4TS U1685 ( .A(n2617), .Y(n3593) );
OAI21X1TS U1686 ( .A0(n4983), .A1(n4982), .B0(FS_Module_state_reg[3]), .Y(
n4254) );
INVX6TS U1687 ( .A(n1997), .Y(n559) );
INVX2TS U1688 ( .A(n3591), .Y(n3592) );
NAND2X4TS U1689 ( .A(n2443), .B(n648), .Y(n2780) );
INVX2TS U1690 ( .A(n3602), .Y(n3604) );
NOR3X2TS U1691 ( .A(n259), .B(n260), .C(P_Sgf[0]), .Y(n3047) );
ADDFHX2TS U1692 ( .A(n3432), .B(n3431), .CI(n3430), .CO(n3423), .S(n3434) );
NAND2X6TS U1693 ( .A(n964), .B(n963), .Y(n3786) );
INVX2TS U1694 ( .A(n3126), .Y(n2609) );
ADDFHX2TS U1695 ( .A(n3316), .B(n3315), .CI(n3314), .CO(n3331), .S(n3307) );
INVX2TS U1696 ( .A(n1129), .Y(n3495) );
OR2X4TS U1697 ( .A(n2757), .B(n2756), .Y(n2759) );
OAI21X1TS U1698 ( .A0(n4617), .A1(n4621), .B0(n4594), .Y(n4626) );
INVX4TS U1699 ( .A(n2166), .Y(n2846) );
NAND2X4TS U1700 ( .A(n2437), .B(n641), .Y(n4096) );
OAI21X1TS U1701 ( .A0(n4701), .A1(n4676), .B0(n4719), .Y(n4700) );
AND2X2TS U1702 ( .A(n1704), .B(n1709), .Y(n1712) );
BUFX12TS U1703 ( .A(n1713), .Y(n1081) );
XOR2X1TS U1704 ( .A(n3943), .B(n3942), .Y(n4646) );
MX2X2TS U1705 ( .A(n3040), .B(n4862), .S0(n658), .Y(n259) );
MX2X2TS U1706 ( .A(n4025), .B(n4859), .S0(n626), .Y(n262) );
NAND2X6TS U1707 ( .A(n543), .B(n2177), .Y(n3552) );
NAND2X2TS U1708 ( .A(n1496), .B(n2315), .Y(n2317) );
OAI21X1TS U1709 ( .A0(n3943), .A1(n3944), .B0(n3945), .Y(n4637) );
AND2X8TS U1710 ( .A(n4198), .B(n2818), .Y(n4234) );
INVX2TS U1711 ( .A(Sgf_operation_EVEN1_Q_left[5]), .Y(n3424) );
ADDFHX2TS U1712 ( .A(n3706), .B(n3705), .CI(n3704), .CO(n3707), .S(n3689) );
OAI21X1TS U1713 ( .A0(n4642), .A1(n4593), .B0(n4597), .Y(n3934) );
OAI2BB1X2TS U1714 ( .A0N(n1472), .A1N(n1471), .B0(n3324), .Y(n1470) );
INVX6TS U1715 ( .A(n1022), .Y(n3551) );
AND2X2TS U1716 ( .A(n4084), .B(n4083), .Y(n4085) );
NAND2X2TS U1717 ( .A(n2491), .B(n2490), .Y(n3960) );
CLKMX2X2TS U1718 ( .A(n4406), .B(P_Sgf[1]), .S0(n4936), .Y(n4775) );
OAI21X1TS U1719 ( .A0(n4500), .A1(n4492), .B0(n4494), .Y(n4511) );
XNOR2X1TS U1720 ( .A(n3045), .B(n3044), .Y(n3046) );
AO22X2TS U1721 ( .A0(n4305), .A1(Sgf_normalized_result[0]), .B0(
final_result_ieee[0]), .B1(n4310), .Y(n200) );
AO22X2TS U1722 ( .A0(n4305), .A1(Sgf_normalized_result[9]), .B0(
final_result_ieee[9]), .B1(n4308), .Y(n191) );
NAND2X6TS U1723 ( .A(n2815), .B(FS_Module_state_reg[1]), .Y(n4198) );
INVX8TS U1724 ( .A(n1502), .Y(n4936) );
INVX4TS U1725 ( .A(n4298), .Y(n3432) );
AO22X2TS U1726 ( .A0(n4309), .A1(Sgf_normalized_result[10]), .B0(
final_result_ieee[10]), .B1(n4308), .Y(n190) );
AO22X2TS U1727 ( .A0(n4309), .A1(Sgf_normalized_result[8]), .B0(
final_result_ieee[8]), .B1(n4308), .Y(n192) );
INVX2TS U1728 ( .A(n4555), .Y(n4570) );
AO22X2TS U1729 ( .A0(n4309), .A1(Sgf_normalized_result[6]), .B0(
final_result_ieee[6]), .B1(n4308), .Y(n194) );
AO22X2TS U1730 ( .A0(n4305), .A1(Sgf_normalized_result[3]), .B0(
final_result_ieee[3]), .B1(n4307), .Y(n197) );
AO22X2TS U1731 ( .A0(n4305), .A1(Sgf_normalized_result[7]), .B0(
final_result_ieee[7]), .B1(n4308), .Y(n193) );
INVX2TS U1732 ( .A(n3339), .Y(n3341) );
AO22X2TS U1733 ( .A0(n4309), .A1(Sgf_normalized_result[5]), .B0(
final_result_ieee[5]), .B1(n4307), .Y(n195) );
INVX2TS U1734 ( .A(n4520), .Y(n4571) );
AO22X2TS U1735 ( .A0(n4309), .A1(Sgf_normalized_result[4]), .B0(
final_result_ieee[4]), .B1(n4307), .Y(n196) );
AO22X2TS U1736 ( .A0(n4305), .A1(n4356), .B0(final_result_ieee[14]), .B1(
n4308), .Y(n186) );
AO22X2TS U1737 ( .A0(n4305), .A1(n4340), .B0(final_result_ieee[15]), .B1(
n4310), .Y(n185) );
AO22X2TS U1738 ( .A0(n4305), .A1(n886), .B0(final_result_ieee[21]), .B1(
n4310), .Y(n179) );
AO22X2TS U1739 ( .A0(n4309), .A1(Sgf_normalized_result[22]), .B0(
final_result_ieee[22]), .B1(n4310), .Y(n178) );
MX2X2TS U1740 ( .A(n3017), .B(n4856), .S0(n666), .Y(n257) );
AO22X2TS U1741 ( .A0(n4309), .A1(n4391), .B0(final_result_ieee[17]), .B1(
n4308), .Y(n183) );
OAI21X1TS U1742 ( .A0(n4081), .A1(n4060), .B0(n4059), .Y(n4063) );
AOI2BB2X1TS U1743 ( .B0(n4305), .B1(n4756), .A0N(n4303), .A1N(
final_result_ieee[24]), .Y(n176) );
INVX2TS U1744 ( .A(n3302), .Y(n3322) );
INVX2TS U1745 ( .A(n4082), .Y(n4084) );
AO22X2TS U1746 ( .A0(n4305), .A1(n4390), .B0(final_result_ieee[16]), .B1(
n4310), .Y(n184) );
INVX3TS U1747 ( .A(n2766), .Y(n2447) );
AOI2BB2X1TS U1748 ( .B0(n4305), .B1(n4300), .A0N(n4303), .A1N(
final_result_ieee[25]), .Y(n175) );
INVX6TS U1749 ( .A(n1140), .Y(n1138) );
OAI21X2TS U1750 ( .A0(n3966), .A1(n4675), .B0(n3967), .Y(n4680) );
OR2X4TS U1751 ( .A(n2602), .B(n2601), .Y(n2604) );
INVX2TS U1752 ( .A(n3989), .Y(n3983) );
OAI21X1TS U1753 ( .A0(n3854), .A1(n887), .B0(n3852), .Y(n3855) );
OAI21X1TS U1754 ( .A0(n3950), .A1(n3945), .B0(n3951), .Y(n3946) );
NOR2X1TS U1755 ( .A(n4666), .B(n4665), .Y(n4695) );
NAND2BX2TS U1756 ( .AN(n4495), .B(n349), .Y(n4520) );
NAND2X4TS U1757 ( .A(n2814), .B(n4010), .Y(n2815) );
INVX2TS U1758 ( .A(n3575), .Y(n3792) );
BUFX12TS U1759 ( .A(n4202), .Y(n4253) );
NOR2X1TS U1760 ( .A(n4515), .B(n4498), .Y(n4516) );
OR2X2TS U1761 ( .A(n4529), .B(n4487), .Y(n4537) );
OR2X2TS U1762 ( .A(n4546), .B(n4502), .Y(n4551) );
OR2X4TS U1763 ( .A(n3965), .B(n4670), .Y(n4719) );
NOR2X1TS U1764 ( .A(n4543), .B(n4535), .Y(n674) );
NOR2X1TS U1765 ( .A(n4515), .B(n4502), .Y(n4539) );
NOR2X1TS U1766 ( .A(n4515), .B(n4541), .Y(n671) );
OAI21X1TS U1767 ( .A0(n4081), .A1(n4048), .B0(n4047), .Y(n4053) );
OAI21X1TS U1768 ( .A0(n4081), .A1(n4033), .B0(n4032), .Y(n4039) );
OAI21X1TS U1769 ( .A0(n4081), .A1(n4021), .B0(n4022), .Y(n4024) );
INVX2TS U1770 ( .A(n3956), .Y(n3958) );
INVX2TS U1771 ( .A(n2602), .Y(n2280) );
NOR2X1TS U1772 ( .A(n4504), .B(n4484), .Y(n4528) );
NAND2X2TS U1773 ( .A(n1993), .B(n1992), .Y(n2061) );
NAND2X4TS U1774 ( .A(n2030), .B(n2065), .Y(n477) );
NAND2X4TS U1775 ( .A(n1186), .B(n1185), .Y(n3654) );
OAI21X2TS U1776 ( .A0(n4592), .A1(n3956), .B0(n3957), .Y(n3939) );
INVX2TS U1777 ( .A(n3953), .Y(n3955) );
OAI21X1TS U1778 ( .A0(n4598), .A1(n4589), .B0(n4635), .Y(n4640) );
INVX12TS U1779 ( .A(n960), .Y(n961) );
NOR2X1TS U1780 ( .A(n4621), .B(n4588), .Y(n4632) );
OAI21X1TS U1781 ( .A0(n3936), .A1(n4597), .B0(n3935), .Y(n3937) );
NOR2X1TS U1782 ( .A(n4593), .B(n3936), .Y(n3938) );
NOR2X1TS U1783 ( .A(n4509), .B(n4503), .Y(n4534) );
NAND2X2TS U1784 ( .A(n360), .B(n348), .Y(n4594) );
NAND2X2TS U1785 ( .A(n358), .B(n346), .Y(n4597) );
INVX4TS U1786 ( .A(n314), .Y(n4509) );
INVX2TS U1787 ( .A(n2099), .Y(n2079) );
OR2X4TS U1788 ( .A(n365), .B(n353), .Y(n4625) );
NAND2X2TS U1789 ( .A(n829), .B(n1044), .Y(n3670) );
INVX2TS U1790 ( .A(n363), .Y(n4595) );
ADDHX1TS U1791 ( .A(DP_OP_155J6_124_2038_n795), .B(n363), .CO(n3875), .S(
n4590) );
INVX4TS U1792 ( .A(n317), .Y(n4543) );
NAND2X4TS U1793 ( .A(n2239), .B(n1095), .Y(n2240) );
INVX4TS U1794 ( .A(n4009), .Y(n2814) );
NAND2X2TS U1795 ( .A(n357), .B(DP_OP_155J6_124_2038_n801), .Y(n3957) );
NOR2X2TS U1796 ( .A(n357), .B(DP_OP_155J6_124_2038_n801), .Y(n3956) );
NOR2X2TS U1797 ( .A(n359), .B(DP_OP_155J6_124_2038_n803), .Y(n3936) );
AND2X4TS U1798 ( .A(n362), .B(n350), .Y(n4631) );
BUFX3TS U1799 ( .A(n3229), .Y(n463) );
ADDHX1TS U1800 ( .A(n319), .B(n331), .CO(n3861), .S(n4616) );
NAND2X2TS U1801 ( .A(n356), .B(n3844), .Y(n4592) );
ADDFHX2TS U1802 ( .A(n3291), .B(n3290), .CI(n3289), .CO(n3313), .S(n3286) );
NAND2X2TS U1803 ( .A(n359), .B(DP_OP_155J6_124_2038_n803), .Y(n3935) );
INVX2TS U1804 ( .A(n327), .Y(n4699) );
NAND2X2TS U1805 ( .A(n324), .B(n312), .Y(n4591) );
INVX2TS U1806 ( .A(n2098), .Y(n2086) );
NAND2X4TS U1807 ( .A(n4009), .B(FS_Module_state_reg[1]), .Y(n4011) );
NOR2X2TS U1808 ( .A(n317), .B(n329), .Y(n4589) );
NAND3X6TS U1809 ( .A(n1197), .B(n742), .C(n1196), .Y(n1195) );
BUFX8TS U1810 ( .A(n2519), .Y(n547) );
AND2X2TS U1811 ( .A(n314), .B(n348), .Y(n4553) );
NOR2X4TS U1812 ( .A(n327), .B(n315), .Y(n3950) );
NAND2X6TS U1813 ( .A(n2882), .B(n2881), .Y(n945) );
INVX4TS U1814 ( .A(n843), .Y(n845) );
INVX4TS U1815 ( .A(n346), .Y(n4508) );
INVX6TS U1816 ( .A(n326), .Y(n4670) );
INVX8TS U1817 ( .A(DP_OP_155J6_124_2038_n803), .Y(n4503) );
INVX4TS U1818 ( .A(n319), .Y(n4515) );
NAND2X2TS U1819 ( .A(n330), .B(n324), .Y(n4675) );
INVX4TS U1820 ( .A(n320), .Y(n4496) );
NAND2X6TS U1821 ( .A(n2817), .B(FS_Module_state_reg[1]), .Y(n4202) );
INVX2TS U1822 ( .A(n3735), .Y(n3085) );
INVX2TS U1823 ( .A(n3077), .Y(n2797) );
NAND2X4TS U1824 ( .A(n3362), .B(n1163), .Y(n1162) );
NAND2X6TS U1825 ( .A(n1327), .B(n2869), .Y(n1326) );
NAND2X2TS U1826 ( .A(n331), .B(n3940), .Y(n3967) );
NOR2X8TS U1827 ( .A(n4310), .B(n4020), .Y(n4304) );
INVX6TS U1828 ( .A(n2424), .Y(n2427) );
MX2X4TS U1829 ( .A(Data_MY[12]), .B(n4933), .S0(n4290), .Y(n324) );
MX2X4TS U1830 ( .A(Data_MY[18]), .B(n4879), .S0(n3969), .Y(n330) );
MX2X4TS U1831 ( .A(Data_MX[5]), .B(Op_MX[5]), .S0(n4015), .Y(n349) );
MX2X4TS U1832 ( .A(Data_MX[2]), .B(n4893), .S0(n4015), .Y(n346) );
CLKMX2X4TS U1833 ( .A(Data_MY[22]), .B(DP_OP_153J6_122_5442_n1468), .S0(
n3969), .Y(n334) );
INVX3TS U1834 ( .A(n3400), .Y(n3402) );
NAND2X2TS U1835 ( .A(n453), .B(n1067), .Y(n3711) );
CLKMX2X2TS U1836 ( .A(n4317), .B(Add_result[4]), .S0(n4935), .Y(n305) );
CLKMX2X2TS U1837 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(n4295), .Y(n340) );
XNOR2X2TS U1838 ( .A(n3207), .B(n3222), .Y(n3208) );
NAND2X2TS U1839 ( .A(n2706), .B(n2707), .Y(n2751) );
MX2X4TS U1840 ( .A(Data_MX[14]), .B(n4890), .S0(n3964), .Y(n358) );
INVX2TS U1841 ( .A(n3076), .Y(n2787) );
MX2X4TS U1842 ( .A(Data_MX[20]), .B(Op_MX[20]), .S0(n3970), .Y(n364) );
CLKMX2X2TS U1843 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(n4295), .Y(n339) );
CLKMX2X2TS U1844 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(n4295), .Y(n341) );
OR2X2TS U1845 ( .A(n3255), .B(n3258), .Y(n3853) );
INVX2TS U1846 ( .A(n781), .Y(n2458) );
CLKMX2X2TS U1847 ( .A(n4320), .B(Add_result[3]), .S0(n4935), .Y(n306) );
MX2X4TS U1848 ( .A(Data_MY[1]), .B(Op_MY[1]), .S0(n3969), .Y(n4834) );
MX2X4TS U1849 ( .A(Data_MX[10]), .B(DP_OP_153J6_122_5442_n1517), .S0(n4015),
.Y(n354) );
NAND2X4TS U1850 ( .A(n1004), .B(n743), .Y(n2734) );
MX2X4TS U1851 ( .A(Data_MY[21]), .B(DP_OP_153J6_122_5442_n1467), .S0(n3969),
.Y(n333) );
MX2X4TS U1852 ( .A(Data_MY[4]), .B(Op_MY[4]), .S0(n3969), .Y(n316) );
MX2X4TS U1853 ( .A(Data_MY[14]), .B(n4924), .S0(n4290), .Y(n326) );
MX2X4TS U1854 ( .A(Data_MX[0]), .B(n4898), .S0(n3970), .Y(n3844) );
INVX6TS U1855 ( .A(n3228), .Y(n1899) );
NAND2X6TS U1856 ( .A(n575), .B(n573), .Y(n572) );
MX2X4TS U1857 ( .A(Data_MX[6]), .B(n4926), .S0(n4015), .Y(n350) );
MX2X4TS U1858 ( .A(Data_MX[13]), .B(n4932), .S0(n3964), .Y(n357) );
INVX2TS U1859 ( .A(n2601), .Y(n2281) );
CLKMX2X2TS U1860 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n4290), .Y(n336) );
NAND2X4TS U1861 ( .A(n3731), .B(n2816), .Y(n2817) );
MX2X4TS U1862 ( .A(Data_MY[9]), .B(Op_MY[9]), .S0(n3964), .Y(n321) );
MX2X4TS U1863 ( .A(Data_MX[16]), .B(Op_MX[16]), .S0(n3970), .Y(n360) );
MX2X4TS U1864 ( .A(Data_MY[11]), .B(Op_MY[11]), .S0(n3964), .Y(n323) );
NAND2X6TS U1865 ( .A(n1062), .B(n1061), .Y(n1633) );
CLKMX2X2TS U1866 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n4295), .Y(n337) );
MX2X4TS U1867 ( .A(Data_MX[21]), .B(Op_MX[21]), .S0(n3970), .Y(n365) );
CLKMX2X2TS U1868 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(n4295), .Y(n367) );
MX2X4TS U1869 ( .A(Data_MY[5]), .B(Op_MY[5]), .S0(n3964), .Y(n317) );
CLKMX2X2TS U1870 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(n4295), .Y(n369) );
CLKMX2X2TS U1871 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n4295), .Y(n368) );
INVX2TS U1872 ( .A(n3041), .Y(n4031) );
MX2X4TS U1873 ( .A(Data_MX[15]), .B(n4889), .S0(n3970), .Y(n359) );
AOI21X2TS U1874 ( .A0(n3027), .A1(n3003), .B0(n3002), .Y(n3007) );
INVX2TS U1875 ( .A(n4003), .Y(n4005) );
INVX6TS U1876 ( .A(n3225), .Y(n1933) );
AND2X4TS U1877 ( .A(n2368), .B(n643), .Y(n799) );
INVX8TS U1878 ( .A(n2171), .Y(n1292) );
NAND2X2TS U1879 ( .A(n4026), .B(n2367), .Y(n4021) );
BUFX8TS U1880 ( .A(n4289), .Y(n4295) );
CLKINVX6TS U1881 ( .A(n3674), .Y(n1720) );
NAND2X6TS U1882 ( .A(n2433), .B(n2432), .Y(n2764) );
NAND2X4TS U1883 ( .A(n4093), .B(n4003), .Y(n4992) );
BUFX16TS U1884 ( .A(n4289), .Y(n3964) );
NAND2X2TS U1885 ( .A(n3215), .B(n3214), .Y(n3217) );
NOR2X2TS U1886 ( .A(n4119), .B(n3747), .Y(n4156) );
INVX12TS U1887 ( .A(n4299), .Y(n4310) );
BUFX4TS U1888 ( .A(n4289), .Y(n4288) );
ADDFHX2TS U1889 ( .A(n1484), .B(n3137), .CI(n3136), .CO(n3187), .S(n3155) );
INVX2TS U1890 ( .A(n1554), .Y(n1556) );
BUFX16TS U1891 ( .A(n4289), .Y(n3970) );
INVX2TS U1892 ( .A(n1059), .Y(n1834) );
INVX2TS U1893 ( .A(n4026), .Y(n3042) );
BUFX16TS U1894 ( .A(n4289), .Y(n4015) );
INVX2TS U1895 ( .A(n4374), .Y(n4371) );
NOR2X6TS U1896 ( .A(n4326), .B(n4244), .Y(n4401) );
BUFX16TS U1897 ( .A(n4289), .Y(n3969) );
NOR2X1TS U1898 ( .A(n4374), .B(n4777), .Y(n4375) );
AND2X4TS U1899 ( .A(n2600), .B(n3106), .Y(Sgf_operation_EVEN1_Q_left[1]) );
AND2X8TS U1900 ( .A(n4019), .B(n4018), .Y(n4299) );
BUFX12TS U1901 ( .A(n2678), .Y(n1053) );
OR2X6TS U1902 ( .A(n4010), .B(FS_Module_state_reg[1]), .Y(
FSM_exp_operation_A_S) );
NAND2X6TS U1903 ( .A(n757), .B(n1739), .Y(n756) );
MXI2X4TS U1904 ( .A(n4017), .B(n4851), .S0(n659), .Y(underflow_flag) );
NAND2X6TS U1905 ( .A(n432), .B(n579), .Y(n2181) );
OAI21X1TS U1906 ( .A0(FSM_selector_B_1_), .A1(n3837), .B0(n3839), .Y(n3838)
);
INVX6TS U1907 ( .A(n2418), .Y(n2419) );
INVX2TS U1908 ( .A(n4027), .Y(n4030) );
MX2X4TS U1909 ( .A(n4012), .B(n4853), .S0(n4852), .Y(n225) );
INVX4TS U1910 ( .A(n2344), .Y(n2351) );
NAND2X6TS U1911 ( .A(n1237), .B(n1236), .Y(n2199) );
NAND2X2TS U1912 ( .A(n1545), .B(n1544), .Y(n1555) );
INVX6TS U1913 ( .A(n2215), .Y(n1377) );
INVX16TS U1914 ( .A(n1257), .Y(n873) );
NOR2X4TS U1915 ( .A(n4453), .B(n3733), .Y(n3749) );
BUFX16TS U1916 ( .A(n1670), .Y(n1043) );
INVX2TS U1917 ( .A(n2383), .Y(n2353) );
OAI21X1TS U1918 ( .A0(FSM_selector_B_1_), .A1(n4744), .B0(n3839), .Y(n3836)
);
OAI21X1TS U1919 ( .A0(n4331), .A1(n4323), .B0(n4322), .Y(n4324) );
INVX2TS U1920 ( .A(n4119), .Y(n4133) );
NAND2X1TS U1921 ( .A(n4337), .B(n4356), .Y(n4338) );
OAI21X1TS U1922 ( .A0(n4331), .A1(n4772), .B0(n4328), .Y(n4329) );
INVX2TS U1923 ( .A(n2068), .Y(n2070) );
INVX2TS U1924 ( .A(n3043), .Y(n4027) );
NOR2X1TS U1925 ( .A(n4318), .B(Sgf_normalized_result[2]), .Y(n4319) );
INVX2TS U1926 ( .A(n4028), .Y(n4029) );
NOR2X1TS U1927 ( .A(n4395), .B(n4397), .Y(n4386) );
INVX2TS U1928 ( .A(n4261), .Y(n4263) );
NAND2X6TS U1929 ( .A(n4200), .B(n4091), .Y(n4010) );
INVX2TS U1930 ( .A(n4336), .Y(n4354) );
NOR2X4TS U1931 ( .A(n3004), .B(n3012), .Y(n2332) );
NAND2BX2TS U1932 ( .AN(Exp_module_Data_S[8]), .B(n4016), .Y(n4017) );
AOI21X4TS U1933 ( .A0(n4316), .A1(n4240), .B0(n4239), .Y(n4326) );
NOR2X1TS U1934 ( .A(n4369), .B(n4246), .Y(n4247) );
INVX12TS U1935 ( .A(n471), .Y(n2020) );
INVX2TS U1936 ( .A(n4266), .Y(n4273) );
NAND2X6TS U1937 ( .A(n2606), .B(n2605), .Y(n3120) );
INVX2TS U1938 ( .A(n3257), .Y(n3291) );
NAND2X6TS U1939 ( .A(n607), .B(n606), .Y(n605) );
INVX8TS U1940 ( .A(n2152), .Y(n1228) );
INVX12TS U1941 ( .A(n1735), .Y(n868) );
NOR2X4TS U1942 ( .A(n4360), .B(n4241), .Y(n4336) );
NOR2X1TS U1943 ( .A(n4360), .B(n4780), .Y(n4350) );
OR2X2TS U1944 ( .A(n652), .B(n2452), .Y(n3038) );
AND4X2TS U1945 ( .A(n4267), .B(n4896), .C(n4840), .D(n4897), .Y(n4272) );
BUFX16TS U1946 ( .A(n2570), .Y(n1735) );
AND4X2TS U1947 ( .A(n4836), .B(n4269), .C(n4838), .D(n4839), .Y(n4270) );
NAND2X2TS U1948 ( .A(Sgf_normalized_result[12]), .B(n4346), .Y(n4353) );
NAND2X1TS U1949 ( .A(n4356), .B(n4340), .Y(n4242) );
NAND2X2TS U1950 ( .A(n4390), .B(n4391), .Y(n4395) );
INVX8TS U1951 ( .A(n1669), .Y(n758) );
NAND2X6TS U1952 ( .A(n1762), .B(n4584), .Y(n1423) );
NAND2X6TS U1953 ( .A(n4533), .B(n1464), .Y(n1463) );
INVX1TS U1954 ( .A(n2342), .Y(n2336) );
INVX2TS U1955 ( .A(n3008), .Y(n3009) );
NAND2X6TS U1956 ( .A(n894), .B(n4489), .Y(n478) );
INVX1TS U1957 ( .A(n4328), .Y(n4321) );
INVX2TS U1958 ( .A(n3659), .Y(n1661) );
INVX2TS U1959 ( .A(n4201), .Y(n3831) );
NOR4X1TS U1960 ( .A(n882), .B(P_Sgf[11]), .C(P_Sgf[10]), .D(P_Sgf[9]), .Y(
n3048) );
NOR2X4TS U1961 ( .A(DP_OP_155J6_124_2038_n721), .B(n682), .Y(n3258) );
OR2X2TS U1962 ( .A(n4459), .B(n3029), .Y(n2327) );
CLKINVX2TS U1963 ( .A(Op_MY[6]), .Y(n4260) );
AND4X1TS U1964 ( .A(n4835), .B(n4872), .C(n4873), .D(n4874), .Y(n4264) );
NAND2X4TS U1965 ( .A(DP_OP_155J6_124_2038_n805), .B(n681), .Y(n1845) );
NAND2BX2TS U1966 ( .AN(n696), .B(n4518), .Y(n2045) );
INVX2TS U1967 ( .A(n4413), .Y(n4255) );
OR2X2TS U1968 ( .A(n4710), .B(n4720), .Y(n3659) );
INVX2TS U1969 ( .A(Add_result[1]), .Y(n4055) );
CMPR22X2TS U1970 ( .A(DP_OP_155J6_124_2038_n782), .B(
DP_OP_155J6_124_2038_n788), .CO(n1844), .S(n1847) );
AOI21X2TS U1971 ( .A0(n664), .A1(n4605), .B0(n4606), .Y(n2451) );
INVX2TS U1972 ( .A(Sgf_normalized_result[19]), .Y(n4387) );
CLKINVX1TS U1973 ( .A(Op_MX[16]), .Y(n4268) );
NAND2X1TS U1974 ( .A(Sgf_normalized_result[10]), .B(
Sgf_normalized_result[11]), .Y(n4241) );
INVX2TS U1975 ( .A(n4411), .Y(n4267) );
NOR2X4TS U1976 ( .A(n4460), .B(n4461), .Y(n3029) );
NOR4X1TS U1977 ( .A(Op_MX[25]), .B(Op_MX[26]), .C(Op_MX[27]), .D(Op_MX[28]),
.Y(n4276) );
OR2X4TS U1978 ( .A(n655), .B(n619), .Y(n3021) );
XNOR2X2TS U1979 ( .A(Op_MX[31]), .B(Op_MY[31]), .Y(n4283) );
NAND2X4TS U1980 ( .A(n4655), .B(DP_OP_153J6_122_5442_n1105), .Y(n1359) );
NOR2X6TS U1981 ( .A(DP_OP_153J6_122_5442_n1458), .B(
DP_OP_153J6_122_5442_n1469), .Y(n612) );
NAND2X2TS U1982 ( .A(Sgf_normalized_result[5]), .B(Sgf_normalized_result[4]),
.Y(n4328) );
NAND2X6TS U1983 ( .A(DP_OP_153J6_122_5442_n1514), .B(
DP_OP_153J6_122_5442_n1501), .Y(n2207) );
NAND2X6TS U1984 ( .A(DP_OP_155J6_124_2038_n798), .B(
DP_OP_155J6_124_2038_n804), .Y(n1884) );
NAND2X6TS U1985 ( .A(n723), .B(n4583), .Y(n2197) );
INVX2TS U1986 ( .A(n4412), .Y(n4269) );
INVX2TS U1987 ( .A(exp_oper_result[2]), .Y(n4300) );
NAND2X4TS U1988 ( .A(n633), .B(n4736), .Y(n2791) );
CLKBUFX3TS U1989 ( .A(n853), .Y(n4939) );
NAND2X8TS U1990 ( .A(n2321), .B(n980), .Y(n933) );
NAND2X8TS U1991 ( .A(n935), .B(n936), .Y(n980) );
NOR2X8TS U1992 ( .A(n4547), .B(n682), .Y(n1843) );
INVX4TS U1993 ( .A(n3233), .Y(n3190) );
XOR2X4TS U1994 ( .A(n1040), .B(n1533), .Y(n1039) );
XNOR2X4TS U1995 ( .A(n1130), .B(n681), .Y(n451) );
INVX4TS U1996 ( .A(n2932), .Y(n2986) );
INVX8TS U1997 ( .A(n2022), .Y(n1954) );
NAND2X8TS U1998 ( .A(n3880), .B(n714), .Y(n1110) );
NAND2X8TS U1999 ( .A(n452), .B(n3278), .Y(n1399) );
NAND2X8TS U2000 ( .A(n436), .B(n985), .Y(n452) );
AND2X8TS U2001 ( .A(n472), .B(n430), .Y(n1860) );
CLKINVX6TS U2002 ( .A(n1264), .Y(n1263) );
NOR2X6TS U2003 ( .A(n4547), .B(DP_OP_155J6_124_2038_n730), .Y(n1926) );
OAI22X4TS U2004 ( .A0(n2973), .A1(n2899), .B0(n3573), .B1(n1300), .Y(n3499)
);
NOR2X6TS U2005 ( .A(n995), .B(n994), .Y(n2559) );
BUFX6TS U2006 ( .A(DP_OP_154J6_123_2038_n717), .Y(n454) );
CLKINVX12TS U2007 ( .A(n1340), .Y(n996) );
INVX12TS U2008 ( .A(n2746), .Y(n1681) );
NOR2X8TS U2009 ( .A(DP_OP_154J6_123_2038_n720), .B(DP_OP_154J6_123_2038_n717), .Y(n1578) );
NAND3X8TS U2010 ( .A(n1259), .B(n1181), .C(n2718), .Y(n455) );
NAND2X8TS U2011 ( .A(n2118), .B(n2117), .Y(n914) );
NOR2X6TS U2012 ( .A(n683), .B(n4488), .Y(n1861) );
CLKINVX12TS U2013 ( .A(n506), .Y(n1405) );
OAI22X2TS U2014 ( .A0(n794), .A1(n1987), .B0(n550), .B1(n1989), .Y(n1880) );
NOR2X6TS U2015 ( .A(n1332), .B(n736), .Y(n488) );
INVX6TS U2016 ( .A(n3204), .Y(n1929) );
ADDFHX2TS U2017 ( .A(n2575), .B(n2574), .CI(n2573), .CO(n2648), .S(n2578) );
OAI2BB1X4TS U2018 ( .A0N(DP_OP_155J6_124_2038_n616), .A1N(n459), .B0(n457),
.Y(n2035) );
OAI21X4TS U2019 ( .A0(DP_OP_155J6_124_2038_n616), .A1(n459), .B0(
DP_OP_155J6_124_2038_n625), .Y(n457) );
XOR2X4TS U2020 ( .A(n458), .B(n460), .Y(n1904) );
NOR2X8TS U2021 ( .A(DP_OP_155J6_124_2038_n635), .B(n618), .Y(n459) );
XNOR2X4TS U2022 ( .A(DP_OP_155J6_124_2038_n616), .B(
DP_OP_155J6_124_2038_n625), .Y(n460) );
BUFX12TS U2023 ( .A(DP_OP_155J6_124_2038_n635), .Y(n907) );
CLKINVX12TS U2024 ( .A(n3230), .Y(n3152) );
NAND2X8TS U2025 ( .A(n1018), .B(n2716), .Y(n2717) );
XOR2X4TS U2026 ( .A(n803), .B(n974), .Y(n3164) );
INVX12TS U2027 ( .A(n505), .Y(n3250) );
BUFX16TS U2028 ( .A(n668), .Y(n1103) );
BUFX3TS U2029 ( .A(n2647), .Y(n1056) );
INVX12TS U2030 ( .A(n464), .Y(n3977) );
NAND4X8TS U2031 ( .A(n1212), .B(n1210), .C(n1209), .D(n1208), .Y(n464) );
XOR2X4TS U2032 ( .A(n730), .B(DP_OP_155J6_124_2038_n631), .Y(n1029) );
OAI21X4TS U2033 ( .A0(n1713), .A1(n1601), .B0(n1600), .Y(n1610) );
XOR2X4TS U2034 ( .A(n1394), .B(n1393), .Y(n678) );
NAND2X6TS U2035 ( .A(n399), .B(n1453), .Y(n525) );
NAND2X8TS U2036 ( .A(n1109), .B(n1361), .Y(n1047) );
INVX6TS U2037 ( .A(n3717), .Y(n2626) );
NAND2X8TS U2038 ( .A(n2854), .B(n2853), .Y(n2882) );
INVX8TS U2039 ( .A(n3773), .Y(n3638) );
XOR2X4TS U2040 ( .A(n593), .B(n2924), .Y(n2935) );
OAI22X4TS U2041 ( .A0(n2899), .A1(n2902), .B0(n3573), .B1(n2915), .Y(n593)
);
XNOR2X4TS U2042 ( .A(n468), .B(n1021), .Y(n1919) );
XNOR2X4TS U2043 ( .A(n1873), .B(n1872), .Y(n468) );
NAND2X8TS U2044 ( .A(n1065), .B(n3678), .Y(n1014) );
NAND2X8TS U2045 ( .A(n733), .B(n3646), .Y(n1065) );
INVX12TS U2046 ( .A(n469), .Y(n733) );
NAND2X8TS U2047 ( .A(n1014), .B(n3702), .Y(n1011) );
NOR2X8TS U2048 ( .A(n3647), .B(n3648), .Y(n469) );
INVX8TS U2049 ( .A(n3976), .Y(n896) );
NAND2X8TS U2050 ( .A(n470), .B(n3721), .Y(n3976) );
INVX8TS U2051 ( .A(n1395), .Y(n470) );
NAND3X8TS U2052 ( .A(n1010), .B(n1012), .C(n1008), .Y(n1395) );
NAND3X8TS U2053 ( .A(n1234), .B(n739), .C(n1235), .Y(add_x_55_n39) );
XNOR2X4TS U2054 ( .A(n472), .B(n430), .Y(n471) );
NOR2X8TS U2055 ( .A(n4478), .B(n683), .Y(n472) );
NAND2X6TS U2056 ( .A(n2669), .B(n3984), .Y(n774) );
NOR2X2TS U2057 ( .A(n482), .B(n473), .Y(n481) );
NAND2X8TS U2058 ( .A(n1181), .B(n473), .Y(n1018) );
AOI21X4TS U2059 ( .A0(n1259), .A1(n2718), .B0(n473), .Y(n1258) );
AND2X8TS U2060 ( .A(n1296), .B(n2709), .Y(n473) );
XOR2X4TS U2061 ( .A(n474), .B(n2051), .Y(n2075) );
AOI21X4TS U2062 ( .A0(n1220), .A1(n476), .B0(n475), .Y(n474) );
INVX2TS U2063 ( .A(n2057), .Y(n475) );
NOR2X6TS U2064 ( .A(n440), .B(DP_OP_154J6_123_2038_n628), .Y(n1607) );
XOR2X4TS U2065 ( .A(n478), .B(n4485), .Y(n1988) );
CLKINVX6TS U2066 ( .A(n479), .Y(n2023) );
NAND2X1TS U2067 ( .A(n3113), .B(n479), .Y(n3115) );
NAND2X4TS U2068 ( .A(n2022), .B(n2021), .Y(n479) );
XOR2X4TS U2069 ( .A(n481), .B(n2718), .Y(Sgf_operation_EVEN1_Q_left[14]) );
NAND2X8TS U2070 ( .A(n480), .B(n2700), .Y(n2718) );
XOR2X4TS U2071 ( .A(n425), .B(n495), .Y(n1296) );
OR2X8TS U2072 ( .A(n486), .B(n1483), .Y(n485) );
XOR2X4TS U2073 ( .A(n2590), .B(n817), .Y(n486) );
OR2X8TS U2074 ( .A(n2699), .B(n2698), .Y(n1181) );
XNOR2X4TS U2075 ( .A(n3649), .B(n483), .Y(n2699) );
NAND3X8TS U2076 ( .A(n1456), .B(n1439), .C(n2703), .Y(n3649) );
NOR2X8TS U2077 ( .A(n1296), .B(n2709), .Y(n482) );
NAND2X8TS U2078 ( .A(n467), .B(n1483), .Y(n2700) );
BUFX6TS U2079 ( .A(n1842), .Y(n487) );
XOR2X4TS U2080 ( .A(n429), .B(n488), .Y(n490) );
INVX16TS U2081 ( .A(n490), .Y(n2839) );
NAND2X8TS U2082 ( .A(n2905), .B(n2839), .Y(n1842) );
XOR2X4TS U2083 ( .A(n492), .B(n491), .Y(n489) );
NOR2X8TS U2084 ( .A(DP_OP_153J6_122_5442_n1098), .B(
DP_OP_153J6_122_5442_n1104), .Y(n2126) );
NOR2X8TS U2085 ( .A(n2963), .B(n2962), .Y(n1289) );
OAI21X4TS U2086 ( .A0(n817), .A1(n826), .B0(n1019), .Y(n495) );
NOR2X8TS U2087 ( .A(n2838), .B(n2839), .Y(n2871) );
NOR2X8TS U2088 ( .A(DP_OP_153J6_122_5442_n1106), .B(
DP_OP_153J6_122_5442_n1104), .Y(n1332) );
NAND4X4TS U2089 ( .A(n1281), .B(n901), .C(n3975), .D(n589), .Y(n932) );
AOI2BB1X4TS U2090 ( .A0N(n498), .A1N(n497), .B0(n3973), .Y(add_x_23_n50) );
NAND2X8TS U2091 ( .A(n4672), .B(DP_OP_154J6_123_2038_n628), .Y(n1669) );
XNOR2X4TS U2092 ( .A(n1215), .B(n2745), .Y(n500) );
NAND2X4TS U2093 ( .A(n3649), .B(n2694), .Y(n501) );
NAND2X8TS U2094 ( .A(n511), .B(n502), .Y(add_x_23_n4) );
NAND2X6TS U2095 ( .A(n1451), .B(n502), .Y(n3782) );
NOR2X6TS U2096 ( .A(DP_OP_154J6_123_2038_n628), .B(n802), .Y(n1510) );
NOR2X8TS U2097 ( .A(n504), .B(n3352), .Y(n510) );
XOR2X4TS U2098 ( .A(n1135), .B(n973), .Y(n504) );
INVX12TS U2099 ( .A(n3250), .Y(n871) );
INVX12TS U2100 ( .A(n1405), .Y(n795) );
XNOR2X4TS U2101 ( .A(n594), .B(n1886), .Y(n505) );
NAND2BX4TS U2102 ( .AN(n1963), .B(n1405), .Y(n508) );
XOR2X4TS U2103 ( .A(n517), .B(n766), .Y(n506) );
NOR2X8TS U2104 ( .A(n2743), .B(n2742), .Y(n3648) );
NAND2X8TS U2105 ( .A(n511), .B(n929), .Y(n1451) );
INVX12TS U2106 ( .A(n3977), .Y(n511) );
NAND2X8TS U2107 ( .A(n1238), .B(n686), .Y(n910) );
AND2X8TS U2108 ( .A(n1166), .B(n3350), .Y(n686) );
XOR2X4TS U2109 ( .A(n512), .B(n749), .Y(n1166) );
OAI21X4TS U2110 ( .A0(n1424), .A1(n984), .B0(n1232), .Y(n512) );
NAND4X8TS U2111 ( .A(n1448), .B(n990), .C(n991), .D(n1143), .Y(n1238) );
NAND2X8TS U2112 ( .A(n515), .B(n513), .Y(n991) );
NAND2X8TS U2113 ( .A(n443), .B(n514), .Y(n513) );
NOR2X8TS U2114 ( .A(n1168), .B(n3319), .Y(n515) );
OAI22X4TS U2115 ( .A0(n550), .A1(n3144), .B0(n3186), .B1(n795), .Y(n769) );
NAND2X8TS U2116 ( .A(n1405), .B(n516), .Y(n777) );
OAI21X4TS U2117 ( .A0(n1886), .A1(n1883), .B0(n1884), .Y(n517) );
INVX12TS U2118 ( .A(n1324), .Y(n1325) );
NAND3X8TS U2119 ( .A(n519), .B(n2234), .C(n518), .Y(n1324) );
NAND3X8TS U2120 ( .A(n2236), .B(n2163), .C(n1311), .Y(n519) );
NAND2X8TS U2121 ( .A(n1377), .B(n1378), .Y(n1311) );
XOR2X4TS U2122 ( .A(DP_OP_153J6_122_5442_n1065), .B(
DP_OP_153J6_122_5442_n1122), .Y(n520) );
CLKINVX1TS U2123 ( .A(n3535), .Y(n3536) );
XOR2X2TS U2124 ( .A(n3535), .B(n447), .Y(n2920) );
XOR2X2TS U2125 ( .A(n3535), .B(n448), .Y(n2840) );
XNOR2X4TS U2126 ( .A(n1022), .B(n3535), .Y(n2977) );
BUFX6TS U2127 ( .A(n1453), .Y(n522) );
NAND3X8TS U2128 ( .A(n524), .B(n3976), .C(n525), .Y(n523) );
NAND2X8TS U2129 ( .A(n1395), .B(n1438), .Y(n1453) );
INVX16TS U2130 ( .A(n526), .Y(n3975) );
NAND3X8TS U2131 ( .A(n3975), .B(n522), .C(n1280), .Y(n528) );
NOR2X8TS U2132 ( .A(n3677), .B(n3977), .Y(n1280) );
NOR2X8TS U2133 ( .A(n1452), .B(n2717), .Y(n526) );
OAI21X4TS U2134 ( .A0(n2781), .A1(n2780), .B0(n2779), .Y(n3067) );
NOR2X8TS U2135 ( .A(n2461), .B(n622), .Y(n2781) );
XOR2X4TS U2136 ( .A(n2460), .B(n2459), .Y(n2461) );
OAI21X4TS U2137 ( .A0(n3065), .A1(n3064), .B0(n3063), .Y(n530) );
AND2X8TS U2138 ( .A(n529), .B(n620), .Y(n3065) );
AOI21X4TS U2139 ( .A0(n3066), .A1(n3067), .B0(n530), .Y(n3068) );
NOR2X8TS U2140 ( .A(n3065), .B(n3059), .Y(n3066) );
NOR2X8TS U2141 ( .A(n2782), .B(n632), .Y(n3059) );
XNOR2X4TS U2142 ( .A(n3739), .B(n2778), .Y(n2782) );
XNOR2X4TS U2143 ( .A(n1341), .B(n2798), .Y(n529) );
XOR2X4TS U2144 ( .A(DP_OP_153J6_122_5442_n1479), .B(n4868), .Y(n2204) );
XNOR2X4TS U2145 ( .A(n2199), .B(n2204), .Y(n532) );
NAND2X8TS U2146 ( .A(n534), .B(n3877), .Y(n1057) );
NAND2X8TS U2147 ( .A(n1314), .B(n1313), .Y(n534) );
AOI2BB2X4TS U2148 ( .B0(n4235), .B1(n4233), .A0N(n859), .A1N(n4785), .Y(
n4971) );
XOR2X4TS U2149 ( .A(n537), .B(n4450), .Y(n536) );
OAI21X4TS U2150 ( .A0(n877), .A1(n4177), .B0(n4176), .Y(n537) );
OR2X8TS U2151 ( .A(DP_OP_153J6_122_5442_n36), .B(n3872), .Y(n4658) );
OAI21X4TS U2152 ( .A0(n3898), .A1(n3895), .B0(n3896), .Y(
DP_OP_153J6_122_5442_n36) );
NAND2X8TS U2153 ( .A(n540), .B(n539), .Y(n2185) );
AOI21X4TS U2154 ( .A0(DP_OP_153J6_122_5442_n1097), .A1(n4587), .B0(n4586),
.Y(n539) );
XOR2X4TS U2155 ( .A(n541), .B(n545), .Y(n2177) );
XOR2X4TS U2156 ( .A(n542), .B(n2174), .Y(n541) );
XNOR2X4TS U2157 ( .A(n2851), .B(n2848), .Y(n2176) );
XOR2X4TS U2158 ( .A(n544), .B(n2881), .Y(n543) );
NOR2BX4TS U2159 ( .AN(n545), .B(n2849), .Y(n544) );
XOR2X4TS U2160 ( .A(n595), .B(n546), .Y(n545) );
INVX12TS U2161 ( .A(n2519), .Y(n2505) );
XOR2X4TS U2162 ( .A(n1195), .B(n547), .Y(n2514) );
OAI22X4TS U2163 ( .A0(n435), .A1(n2514), .B0(n547), .B1(n2520), .Y(n2522) );
XOR2X4TS U2164 ( .A(n1271), .B(n549), .Y(n1270) );
BUFX16TS U2165 ( .A(n3310), .Y(n550) );
AOI2BB1X4TS U2166 ( .A0N(n1886), .A1N(n551), .B0(n776), .Y(n3310) );
NOR2X8TS U2167 ( .A(n552), .B(DP_OP_155J6_124_2038_n379), .Y(n1886) );
NOR2X6TS U2168 ( .A(n1390), .B(n1486), .Y(n552) );
NAND2BX2TS U2169 ( .AN(n554), .B(n2900), .Y(n3788) );
NOR2BX4TS U2170 ( .AN(n554), .B(n1059), .Y(n2883) );
XNOR2X4TS U2171 ( .A(n1059), .B(n554), .Y(n553) );
NOR2X8TS U2172 ( .A(n681), .B(n2850), .Y(n554) );
XNOR2X4TS U2173 ( .A(n3818), .B(n3817), .Y(n1073) );
XNOR2X4TS U2174 ( .A(n556), .B(n3810), .Y(n3818) );
OR2X8TS U2175 ( .A(n2830), .B(n2829), .Y(n555) );
NOR2X8TS U2176 ( .A(n1230), .B(n2292), .Y(n2830) );
NAND2X8TS U2177 ( .A(n555), .B(n2828), .Y(n3810) );
NAND2X4TS U2178 ( .A(n2263), .B(n2262), .Y(n2828) );
OR2X8TS U2179 ( .A(n2864), .B(n2863), .Y(n3809) );
INVX12TS U2180 ( .A(n557), .Y(n561) );
XOR2X4TS U2181 ( .A(n561), .B(n1999), .Y(n560) );
XNOR2X4TS U2182 ( .A(n560), .B(n2078), .Y(n2090) );
NOR2X8TS U2183 ( .A(n1998), .B(n423), .Y(n2078) );
OAI21X4TS U2184 ( .A0(n2063), .A1(n2060), .B0(n2061), .Y(n2054) );
NAND2X8TS U2185 ( .A(n559), .B(n1412), .Y(n2014) );
XNOR2X4TS U2186 ( .A(n793), .B(n807), .Y(n557) );
XNOR2X4TS U2187 ( .A(n562), .B(n2856), .Y(n2866) );
XOR2X4TS U2188 ( .A(n1252), .B(n2874), .Y(n562) );
OAI22X4TS U2189 ( .A0(n1101), .A1(n564), .B0(n3552), .B1(n3551), .Y(n2874)
);
XNOR2X4TS U2190 ( .A(n3522), .B(n567), .Y(n566) );
NAND2X8TS U2191 ( .A(n572), .B(n571), .Y(n1962) );
OR2X8TS U2192 ( .A(n3206), .B(n2020), .Y(n571) );
INVX16TS U2193 ( .A(n574), .Y(n1144) );
INVX12TS U2194 ( .A(n1144), .Y(n852) );
XOR2X4TS U2195 ( .A(n576), .B(n3206), .Y(n1980) );
XNOR2X4TS U2196 ( .A(n2020), .B(n577), .Y(n576) );
NAND2X8TS U2197 ( .A(n1855), .B(n391), .Y(n577) );
NAND2X8TS U2198 ( .A(n1145), .B(n4485), .Y(n574) );
XOR2X4TS U2199 ( .A(n1312), .B(n578), .Y(n2585) );
XOR2X4TS U2200 ( .A(n2654), .B(n2655), .Y(n578) );
XOR2X4TS U2201 ( .A(n592), .B(n2632), .Y(n1312) );
OR2X8TS U2202 ( .A(n2585), .B(n2584), .Y(n2586) );
NOR2X8TS U2203 ( .A(n683), .B(DP_OP_155J6_124_2038_n640), .Y(n2034) );
XOR2X4TS U2204 ( .A(n2505), .B(n2523), .Y(n2480) );
XOR2X4TS U2205 ( .A(n2472), .B(n2523), .Y(n2212) );
XOR2X4TS U2206 ( .A(n2523), .B(n2524), .Y(n2513) );
XNOR2X4TS U2207 ( .A(n1131), .B(n2184), .Y(n2523) );
XOR2X4TS U2208 ( .A(n3612), .B(n615), .Y(n614) );
XNOR2X4TS U2209 ( .A(n581), .B(n3526), .Y(n615) );
XOR2X4TS U2210 ( .A(n3533), .B(n1317), .Y(n581) );
OAI22X4TS U2211 ( .A0(n3523), .A1(n1101), .B0(n3513), .B1(n563), .Y(n1317)
);
XNOR2X4TS U2212 ( .A(n2540), .B(n1308), .Y(n3533) );
INVX2TS U2213 ( .A(n2908), .Y(n2946) );
XOR2X4TS U2214 ( .A(n2945), .B(n582), .Y(n2947) );
XNOR2X4TS U2215 ( .A(n2944), .B(n2908), .Y(n582) );
INVX2TS U2216 ( .A(n1325), .Y(n1086) );
XNOR2X4TS U2217 ( .A(n3535), .B(n1436), .Y(n3524) );
XOR2X4TS U2218 ( .A(n1325), .B(n2240), .Y(n3535) );
NAND2X8TS U2219 ( .A(n1207), .B(n2587), .Y(n2656) );
NAND2X8TS U2220 ( .A(n583), .B(n585), .Y(n1207) );
NAND2X8TS U2221 ( .A(n584), .B(n1752), .Y(n585) );
INVX4TS U2222 ( .A(n2588), .Y(n583) );
NAND2X6TS U2223 ( .A(n586), .B(n1753), .Y(n584) );
OAI21X4TS U2224 ( .A0(n1701), .A1(n1700), .B0(n1699), .Y(n1753) );
NAND2X8TS U2225 ( .A(n1351), .B(n1350), .Y(n586) );
NOR2X8TS U2226 ( .A(n587), .B(n2627), .Y(n1568) );
NAND2X8TS U2227 ( .A(n1303), .B(DP_OP_154J6_123_2038_n392), .Y(n780) );
NAND2X4TS U2228 ( .A(n2705), .B(n1563), .Y(n588) );
NAND3X8TS U2229 ( .A(n1281), .B(n3975), .C(n901), .Y(n590) );
NAND3X6TS U2230 ( .A(n590), .B(n1245), .C(n1246), .Y(n1279) );
OAI2BB1X4TS U2231 ( .A0N(n2654), .A1N(n2655), .B0(n591), .Y(n2657) );
OAI21X2TS U2232 ( .A0(n2655), .A1(n2654), .B0(n1312), .Y(n591) );
XOR2X4TS U2233 ( .A(n2630), .B(n2631), .Y(n592) );
AND2X4TS U2234 ( .A(n2924), .B(n593), .Y(n2989) );
NAND2BX4TS U2235 ( .AN(n1045), .B(n1885), .Y(n594) );
NAND2X4TS U2236 ( .A(n595), .B(n2852), .Y(n2853) );
OAI21X4TS U2237 ( .A0(n595), .A1(n2852), .B0(n2851), .Y(n2854) );
XOR2X4TS U2238 ( .A(n2850), .B(n682), .Y(n595) );
NOR2X8TS U2239 ( .A(n4668), .B(n800), .Y(n1513) );
AND2X8TS U2240 ( .A(n4552), .B(n698), .Y(n1873) );
NOR2X8TS U2241 ( .A(n4482), .B(n618), .Y(n1866) );
NAND2X2TS U2242 ( .A(n2128), .B(n596), .Y(n2129) );
NAND2X8TS U2243 ( .A(n1174), .B(n596), .Y(n1173) );
OR2X8TS U2244 ( .A(n1175), .B(n1714), .Y(n596) );
XNOR2X4TS U2245 ( .A(n4566), .B(n598), .Y(n597) );
OAI21X4TS U2246 ( .A0(n1480), .A1(n3251), .B0(n600), .Y(n3146) );
XNOR2X4TS U2247 ( .A(n602), .B(n601), .Y(n599) );
OAI21X4TS U2248 ( .A0(n4566), .A1(n1486), .B0(DP_OP_155J6_124_2038_n388),
.Y(n602) );
OAI2BB1X4TS U2249 ( .A0N(n1918), .A1N(n605), .B0(n603), .Y(n2028) );
OAI21X4TS U2250 ( .A0(n1918), .A1(n605), .B0(n1917), .Y(n603) );
XOR2X4TS U2251 ( .A(n604), .B(n1917), .Y(n2027) );
XOR2X4TS U2252 ( .A(n1918), .B(n605), .Y(n604) );
OAI21X4TS U2253 ( .A0(n1441), .A1(DP_OP_155J6_124_2038_n623), .B0(
DP_OP_155J6_124_2038_n631), .Y(n607) );
NOR2X8TS U2254 ( .A(n728), .B(n4488), .Y(n1441) );
NAND2X8TS U2255 ( .A(n608), .B(n2738), .Y(n997) );
NAND2X2TS U2256 ( .A(n1187), .B(n608), .Y(n1656) );
XNOR2X4TS U2257 ( .A(n1129), .B(n2976), .Y(n2842) );
XNOR2X4TS U2258 ( .A(n2213), .B(n2164), .Y(n609) );
XNOR2X4TS U2259 ( .A(n610), .B(n1822), .Y(n2168) );
XOR2X4TS U2260 ( .A(n1823), .B(n959), .Y(n610) );
OAI22X4TS U2261 ( .A0(n1803), .A1(n2282), .B0(n1811), .B1(n1819), .Y(n1823)
);
INVX6TS U2262 ( .A(n2168), .Y(n2844) );
NOR2X8TS U2263 ( .A(n719), .B(n612), .Y(n2150) );
OAI2BB1X4TS U2264 ( .A0N(n3612), .A1N(n3611), .B0(n613), .Y(n3632) );
OAI21X4TS U2265 ( .A0(n3611), .A1(n3612), .B0(n615), .Y(n613) );
XOR2X4TS U2266 ( .A(n614), .B(n3611), .Y(n3636) );
XNOR2X4TS U2267 ( .A(n4435), .B(n634), .Y(n4035) );
XNOR2X4TS U2268 ( .A(n617), .B(n3578), .Y(n2121) );
NAND2X1TS U2269 ( .A(n655), .B(n619), .Y(n3020) );
NAND2X4TS U2270 ( .A(n3088), .B(n623), .Y(n4145) );
AND2X2TS U2271 ( .A(n3025), .B(n625), .Y(n3026) );
NOR2X6TS U2272 ( .A(n2369), .B(n627), .Y(n4049) );
NAND2X2TS U2273 ( .A(n4170), .B(n629), .Y(n4119) );
NAND2X4TS U2274 ( .A(n633), .B(n4733), .Y(n2774) );
NOR2X6TS U2275 ( .A(n2438), .B(n636), .Y(n3602) );
AO21X2TS U2276 ( .A0(n664), .A1(n637), .B0(n4613), .Y(n2789) );
AO21X2TS U2277 ( .A0(n664), .A1(n637), .B0(n4607), .Y(n2772) );
NOR2X2TS U2278 ( .A(n2370), .B(n638), .Y(n4061) );
NAND2BX4TS U2279 ( .AN(n716), .B(n640), .Y(n2340) );
NAND2X4TS U2280 ( .A(n2439), .B(n646), .Y(n3591) );
NAND2X1TS U2281 ( .A(n3030), .B(n647), .Y(n3031) );
NAND2X4TS U2282 ( .A(n2440), .B(n649), .Y(n3597) );
OAI21X1TS U2283 ( .A0(n654), .A1(n4462), .B0(n4463), .Y(n3032) );
AOI21X1TS U2284 ( .A0(n660), .A1(n4842), .B0(Exp_module_Data_S[7]), .Y(n4016) );
CLKMX2X2TS U2285 ( .A(n660), .B(n4804), .S0(n663), .Y(n228) );
XNOR2X1TS U2286 ( .A(n664), .B(n4610), .Y(n2455) );
NAND2X6TS U2287 ( .A(n3757), .B(n665), .Y(n904) );
CLKMX2X2TS U2288 ( .A(n3046), .B(n4861), .S0(n666), .Y(n260) );
CLKMX2X2TS U2289 ( .A(n4040), .B(n4860), .S0(n666), .Y(n261) );
NOR2X8TS U2290 ( .A(n438), .B(n1103), .Y(n1577) );
NOR2X6TS U2291 ( .A(n1103), .B(DP_OP_154J6_123_2038_n719), .Y(n1727) );
NAND2X2TS U2292 ( .A(n821), .B(n707), .Y(n711) );
NAND2X4TS U2293 ( .A(n1745), .B(n1746), .Y(n1458) );
NOR2X8TS U2294 ( .A(n668), .B(DP_OP_154J6_123_2038_n718), .Y(n2556) );
NAND2X8TS U2295 ( .A(n1476), .B(n1475), .Y(n2746) );
OR2X8TS U2296 ( .A(n693), .B(n4479), .Y(n1850) );
OR2X4TS U2297 ( .A(n4486), .B(n693), .Y(n1959) );
NOR2X8TS U2298 ( .A(DP_OP_155J6_124_2038_n730), .B(n699), .Y(n1256) );
CLKINVX6TS U2299 ( .A(n2702), .Y(n1474) );
NAND2X6TS U2300 ( .A(n2584), .B(n2585), .Y(n2702) );
BUFX8TS U2301 ( .A(n979), .Y(n938) );
NAND2X8TS U2302 ( .A(n953), .B(n2122), .Y(n1176) );
XOR2X4TS U2303 ( .A(n678), .B(n1596), .Y(n1595) );
NAND2X4TS U2304 ( .A(n1724), .B(n1330), .Y(n1329) );
BUFX4TS U2305 ( .A(n830), .Y(n912) );
INVX8TS U2306 ( .A(n1640), .Y(n1667) );
AOI2BB2X4TS U2307 ( .B0(n3250), .B1(n1858), .A0N(n1480), .A1N(n3256), .Y(
n679) );
NOR2X4TS U2308 ( .A(n438), .B(n4672), .Y(n1688) );
INVX16TS U2309 ( .A(n1672), .Y(n1171) );
XOR2X4TS U2310 ( .A(n680), .B(n2550), .Y(n2564) );
XOR2X4TS U2311 ( .A(n2551), .B(n2552), .Y(n680) );
NOR2X4TS U2312 ( .A(DP_OP_155J6_124_2038_n724), .B(n4479), .Y(n1497) );
XOR2X4TS U2313 ( .A(n818), .B(n810), .Y(n3157) );
OR2X2TS U2314 ( .A(n3224), .B(n2024), .Y(n1123) );
INVX8TS U2315 ( .A(n686), .Y(n1231) );
ADDFHX4TS U2316 ( .A(n3870), .B(n2277), .CI(n2278), .CO(n2271), .S(n2286) );
CLKINVX6TS U2317 ( .A(n3819), .Y(n3464) );
OAI22X4TS U2318 ( .A0(n881), .A1(n1833), .B0(n1796), .B1(n839), .Y(n1801) );
XNOR2X4TS U2319 ( .A(n3219), .B(n3478), .Y(n688) );
AOI21X2TS U2320 ( .A0(n782), .A1(n2762), .B0(n2766), .Y(n2436) );
OAI21X4TS U2321 ( .A0(n877), .A1(n4149), .B0(n4148), .Y(n4154) );
AOI2BB2X2TS U2322 ( .B0(n4236), .B1(n4229), .A0N(n860), .A1N(n4760), .Y(
n4978) );
OR2X8TS U2323 ( .A(n1385), .B(n906), .Y(n3369) );
INVX16TS U2324 ( .A(n1735), .Y(n869) );
XOR2X4TS U2325 ( .A(n4195), .B(n630), .Y(n4196) );
AOI2BB2X2TS U2326 ( .B0(n4236), .B1(n4232), .A0N(n859), .A1N(n4784), .Y(
n4967) );
NAND2X4TS U2327 ( .A(n1570), .B(n1569), .Y(n1061) );
NAND2X4TS U2328 ( .A(n4552), .B(n726), .Y(n2010) );
NOR2X8TS U2329 ( .A(n907), .B(DP_OP_155J6_124_2038_n641), .Y(n989) );
NAND2X4TS U2330 ( .A(n2742), .B(n2743), .Y(n3646) );
NAND2X6TS U2331 ( .A(n733), .B(n3646), .Y(n1193) );
OR2X4TS U2332 ( .A(n1745), .B(n1746), .Y(n740) );
NAND2X4TS U2333 ( .A(n1590), .B(n1589), .Y(n1618) );
AOI21X2TS U2334 ( .A0(n1827), .A1(n2298), .B0(n1826), .Y(n1225) );
INVX6TS U2335 ( .A(Sgf_operation_EVEN1_Q_left[8]), .Y(n3467) );
NAND2X6TS U2336 ( .A(n1623), .B(n1622), .Y(n3357) );
OR2X6TS U2337 ( .A(n1623), .B(n1622), .Y(n3358) );
OAI22X4TS U2338 ( .A0(n1031), .A1(n3660), .B0(n2736), .B1(n874), .Y(n3664)
);
INVX8TS U2339 ( .A(n4227), .Y(n3812) );
OR2X8TS U2340 ( .A(n1180), .B(n1755), .Y(n2595) );
INVX2TS U2341 ( .A(n456), .Y(n692) );
NAND2X4TS U2342 ( .A(n1672), .B(n4683), .Y(n994) );
NAND2X4TS U2343 ( .A(n2026), .B(n2027), .Y(n3396) );
NAND2X2TS U2344 ( .A(n2025), .B(n2024), .Y(n3401) );
NAND2X4TS U2345 ( .A(n1244), .B(n3396), .Y(n1243) );
XNOR2X4TS U2346 ( .A(n1362), .B(n1022), .Y(n3523) );
INVX6TS U2347 ( .A(n4404), .Y(n3469) );
NAND2X6TS U2348 ( .A(n4478), .B(n4486), .Y(n1145) );
NOR2X8TS U2349 ( .A(n1990), .B(n3179), .Y(n1928) );
NOR2X8TS U2350 ( .A(DP_OP_154J6_123_2038_n630), .B(n4667), .Y(n1511) );
XOR2X4TS U2351 ( .A(n1957), .B(n449), .Y(n702) );
OAI22X4TS U2352 ( .A0(n1031), .A1(n2572), .B0(n874), .B1(n1741), .Y(n2562)
);
INVX8TS U2353 ( .A(n1734), .Y(n2552) );
OAI22X2TS U2354 ( .A0(n3661), .A1(n2667), .B0(n2737), .B1(n2733), .Y(n2663)
);
NAND2X4TS U2355 ( .A(n2658), .B(n2657), .Y(n2703) );
ADDHX4TS U2356 ( .A(Op_MX[18]), .B(DP_OP_154J6_123_2038_n686), .CO(n2555),
.S(n1730) );
NAND3X6TS U2357 ( .A(n1465), .B(n2108), .C(n2092), .Y(n1127) );
NAND2X6TS U2358 ( .A(n1248), .B(n2092), .Y(n2094) );
OAI2BB1X2TS U2359 ( .A0N(n3224), .A1N(n2024), .B0(n1925), .Y(n1124) );
INVX1TS U2360 ( .A(n3151), .Y(n827) );
XNOR2X4TS U2361 ( .A(n702), .B(n1956), .Y(n807) );
INVX4TS U2362 ( .A(n4250), .Y(n2324) );
INVX16TS U2363 ( .A(n780), .Y(n1672) );
OR2X8TS U2364 ( .A(n682), .B(DP_OP_155J6_124_2038_n724), .Y(n1462) );
ADDHX4TS U2365 ( .A(n1865), .B(n1864), .CO(n1878), .S(n1925) );
NAND2X4TS U2366 ( .A(n436), .B(n1122), .Y(n1424) );
ADDFHX4TS U2367 ( .A(n2730), .B(n2729), .CI(n2728), .CO(n3666), .S(n2721) );
INVX6TS U2368 ( .A(n3543), .Y(n3556) );
AO21X2TS U2369 ( .A0(n1833), .A1(n839), .B0(n1831), .Y(n1839) );
ADDFHX4TS U2370 ( .A(n1839), .B(n1838), .CI(n1837), .CO(n1840), .S(n3543) );
NAND2X4TS U2371 ( .A(n1326), .B(n1095), .Y(n1319) );
OAI22X4TS U2372 ( .A0(n2977), .A1(n1101), .B0(n563), .B1(n2926), .Y(n2968)
);
INVX2TS U2373 ( .A(n1769), .Y(n1141) );
NAND2X4TS U2374 ( .A(n2200), .B(n2191), .Y(n1271) );
NOR2X2TS U2375 ( .A(n1585), .B(n1584), .Y(n761) );
INVX8TS U2376 ( .A(n1048), .Y(n3517) );
INVX4TS U2377 ( .A(n1568), .Y(n764) );
NAND2X6TS U2378 ( .A(n2150), .B(DP_OP_153J6_122_5442_n828), .Y(n2170) );
NAND2X4TS U2379 ( .A(n2601), .B(n2602), .Y(n2603) );
NAND2X6TS U2380 ( .A(n1248), .B(n2093), .Y(n1465) );
INVX4TS U2381 ( .A(n2471), .Y(n2218) );
NOR2X2TS U2382 ( .A(n2147), .B(n1422), .Y(n2148) );
INVX8TS U2383 ( .A(n949), .Y(n2903) );
INVX2TS U2384 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .Y(
n2316) );
INVX2TS U2385 ( .A(n2906), .Y(n1363) );
INVX2TS U2386 ( .A(n1842), .Y(n1786) );
OAI22X2TS U2387 ( .A0(n2525), .A1(n2544), .B0(n2543), .B1(n2532), .Y(n2533)
);
INVX2TS U2388 ( .A(n3870), .Y(n2273) );
INVX2TS U2389 ( .A(n3220), .Y(n3221) );
NOR2X4TS U2390 ( .A(n4095), .B(n3602), .Y(n3589) );
INVX2TS U2391 ( .A(n3862), .Y(n2494) );
NOR2X4TS U2392 ( .A(n2847), .B(n2856), .Y(n3920) );
NAND2X2TS U2393 ( .A(n1053), .B(n4721), .Y(n1004) );
INVX2TS U2394 ( .A(n1986), .Y(n1419) );
NAND2X2TS U2395 ( .A(n2471), .B(n2209), .Y(n1254) );
OAI21X2TS U2396 ( .A0(n1394), .A1(n1393), .B0(n1596), .Y(n1392) );
INVX4TS U2397 ( .A(n2773), .Y(n2790) );
ADDFHX2TS U2398 ( .A(n2250), .B(n2249), .CI(n2248), .CO(n2858), .S(n2268) );
INVX2TS U2399 ( .A(n2229), .Y(n2250) );
INVX2TS U2400 ( .A(n3692), .Y(n1013) );
NAND2X2TS U2401 ( .A(n2470), .B(n2471), .Y(n1196) );
NOR2X4TS U2402 ( .A(n2203), .B(n1305), .Y(n2205) );
INVX2TS U2403 ( .A(n3213), .Y(n3215) );
ADDFHX2TS U2404 ( .A(n3131), .B(n3130), .CI(n3129), .CO(n3405), .S(n3132) );
ADDFHX2TS U2405 ( .A(n3563), .B(n3562), .CI(n3561), .CO(n3581), .S(n3548) );
NAND2X6TS U2406 ( .A(n712), .B(n4567), .Y(n2018) );
INVX4TS U2407 ( .A(n4519), .Y(n1958) );
NOR2X2TS U2408 ( .A(n657), .B(n4457), .Y(n3004) );
INVX2TS U2409 ( .A(n4069), .Y(n4071) );
INVX2TS U2410 ( .A(n4165), .Y(n4166) );
INVX2TS U2411 ( .A(n4313), .Y(n4318) );
NOR2X4TS U2412 ( .A(n4395), .B(n4245), .Y(n4400) );
INVX12TS U2413 ( .A(n778), .Y(n1432) );
NAND2X2TS U2414 ( .A(n2197), .B(n2207), .Y(n2124) );
NOR2X4TS U2415 ( .A(n3450), .B(n3449), .Y(n3823) );
INVX2TS U2416 ( .A(n4078), .Y(n4022) );
AOI2BB2X2TS U2417 ( .B0(n4236), .B1(n267), .A0N(n859), .A1N(n4768), .Y(n4108) );
CLKMX2X2TS U2418 ( .A(n4349), .B(Add_result[13]), .S0(n4378), .Y(n296) );
INVX4TS U2419 ( .A(n3781), .Y(DP_OP_156J6_125_3370_n108) );
NOR2X2TS U2420 ( .A(n1164), .B(n1518), .Y(n3367) );
XOR2X1TS U2421 ( .A(n796), .B(n3842), .Y(DP_OP_36J6_126_4699_n15) );
AOI2BB2X2TS U2422 ( .B0(n441), .B1(n266), .A0N(n859), .A1N(n4769), .Y(n4102)
);
INVX12TS U2423 ( .A(n1144), .Y(n1990) );
OAI22X2TS U2424 ( .A0(n397), .A1(n3251), .B0(n852), .B1(n3292), .Y(n1876) );
INVX4TS U2425 ( .A(n2025), .Y(n1938) );
INVX12TS U2426 ( .A(n1364), .Y(n2679) );
INVX6TS U2427 ( .A(n1016), .Y(n2636) );
INVX8TS U2428 ( .A(n1033), .Y(n2152) );
NAND2X6TS U2429 ( .A(n1444), .B(n1443), .Y(n1967) );
OR2X4TS U2430 ( .A(n563), .B(n2925), .Y(n2928) );
INVX4TS U2431 ( .A(n2591), .Y(n1560) );
BUFX12TS U2432 ( .A(n1336), .Y(n1832) );
INVX8TS U2433 ( .A(n898), .Y(n2515) );
NAND2X2TS U2434 ( .A(n2874), .B(n1252), .Y(n1253) );
NOR2X4TS U2435 ( .A(n699), .B(n4486), .Y(n1870) );
INVX2TS U2436 ( .A(n1872), .Y(n900) );
INVX2TS U2437 ( .A(n3514), .Y(n3526) );
NAND2X4TS U2438 ( .A(n2238), .B(n2237), .Y(n2870) );
NOR2X4TS U2439 ( .A(n1326), .B(n1322), .Y(n1321) );
OAI22X2TS U2440 ( .A0(n2840), .A1(n2912), .B0(n922), .B1(n2873), .Y(n2890)
);
OAI22X2TS U2441 ( .A0(n2473), .A1(n2475), .B0(n2476), .B1(n2474), .Y(n2482)
);
NAND2X2TS U2442 ( .A(n1712), .B(n884), .Y(n883) );
INVX2TS U2443 ( .A(n3682), .Y(n3706) );
NAND2X4TS U2444 ( .A(n3378), .B(n3377), .Y(n3380) );
NOR2X4TS U2445 ( .A(n3455), .B(n3457), .Y(n1335) );
INVX2TS U2446 ( .A(n2872), .Y(n1294) );
INVX2TS U2447 ( .A(n2749), .Y(n2750) );
INVX2TS U2448 ( .A(n2752), .Y(n1411) );
INVX2TS U2449 ( .A(n2751), .Y(n1410) );
INVX2TS U2450 ( .A(n4156), .Y(n4157) );
NOR2X4TS U2451 ( .A(n4061), .B(n4082), .Y(n2373) );
OAI21X2TS U2452 ( .A0(n4082), .A1(n4073), .B0(n4083), .Y(n2372) );
NOR2X4TS U2453 ( .A(n3074), .B(n3077), .Y(n3734) );
OAI21X1TS U2454 ( .A0(n2099), .A1(n2098), .B0(n2097), .Y(n2100) );
AND2X4TS U2455 ( .A(n3304), .B(n3329), .Y(n749) );
INVX2TS U2456 ( .A(n2542), .Y(n1307) );
INVX12TS U2457 ( .A(n3357), .Y(n2131) );
NAND2X4TS U2458 ( .A(n2312), .B(n2313), .Y(n1054) );
INVX2TS U2459 ( .A(n3108), .Y(n3110) );
INVX2TS U2460 ( .A(n3851), .Y(n3345) );
INVX2TS U2461 ( .A(n2404), .Y(n2398) );
INVX2TS U2462 ( .A(n2606), .Y(n1383) );
NAND2X4TS U2463 ( .A(n954), .B(n2323), .Y(n981) );
INVX2TS U2464 ( .A(n4369), .Y(n4370) );
NAND2X4TS U2465 ( .A(n912), .B(n3494), .Y(n915) );
NAND2X4TS U2466 ( .A(n917), .B(n444), .Y(n916) );
NAND2X4TS U2467 ( .A(n1188), .B(n3479), .Y(n939) );
NAND2X6TS U2468 ( .A(n1277), .B(n1276), .Y(n779) );
INVX2TS U2469 ( .A(n4035), .Y(n2364) );
OR2X4TS U2470 ( .A(n4471), .B(n2362), .Y(n3035) );
INVX2TS U2471 ( .A(n2361), .Y(n2362) );
INVX2TS U2472 ( .A(n3589), .Y(n2616) );
XOR2X1TS U2473 ( .A(n3931), .B(n3930), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]) );
NOR2X1TS U2474 ( .A(n4504), .B(n4490), .Y(n4512) );
INVX2TS U2475 ( .A(n4356), .Y(n4357) );
INVX2TS U2476 ( .A(n4340), .Y(n4341) );
OAI21X2TS U2477 ( .A0(n4588), .A1(n4594), .B0(n4652), .Y(n4622) );
INVX2TS U2478 ( .A(Data_MY[17]), .Y(n3949) );
NOR2X1TS U2479 ( .A(n4686), .B(n4664), .Y(n4692) );
INVX2TS U2480 ( .A(n4680), .Y(n4701) );
NOR2X1TS U2481 ( .A(n4526), .B(n4535), .Y(n4538) );
NAND2X2TS U2482 ( .A(n4208), .B(n4236), .Y(n1344) );
INVX2TS U2483 ( .A(n329), .Y(n4708) );
INVX2TS U2484 ( .A(n3828), .Y(DP_OP_156J6_125_3370_n274) );
INVX2TS U2485 ( .A(n3843), .Y(n4536) );
NOR2X4TS U2486 ( .A(n3625), .B(n714), .Y(n1352) );
INVX2TS U2487 ( .A(n3920), .Y(n3867) );
XOR2X1TS U2488 ( .A(n3963), .B(n3962), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]) );
INVX2TS U2489 ( .A(n3813), .Y(Sgf_operation_EVEN1_Q_left[11]) );
INVX2TS U2490 ( .A(n3415), .Y(Sgf_operation_EVEN1_Q_left[9]) );
OR2X4TS U2491 ( .A(n2599), .B(n2598), .Y(n2600) );
INVX6TS U2492 ( .A(n3830), .Y(add_x_19_n299) );
INVX2TS U2493 ( .A(n4224), .Y(n1154) );
INVX4TS U2494 ( .A(n321), .Y(n4493) );
INVX4TS U2495 ( .A(n354), .Y(n4498) );
INVX4TS U2496 ( .A(n315), .Y(n4526) );
INVX4TS U2497 ( .A(n3844), .Y(n4535) );
INVX4TS U2498 ( .A(n352), .Y(n4541) );
BUFX3TS U2499 ( .A(n4798), .Y(n4562) );
NAND2X6TS U2500 ( .A(n1430), .B(n889), .Y(n1428) );
NAND3X4TS U2501 ( .A(n1268), .B(n437), .C(n1266), .Y(add_x_55_n21) );
NAND2X6TS U2502 ( .A(n889), .B(n1269), .Y(n1268) );
CLKBUFX3TS U2503 ( .A(n4800), .Y(n4582) );
NOR2X1TS U2504 ( .A(n3944), .B(n3950), .Y(n3947) );
INVX2TS U2505 ( .A(n3898), .Y(DP_OP_153J6_122_5442_n41) );
CLKBUFX3TS U2506 ( .A(n4945), .Y(n4558) );
BUFX3TS U2507 ( .A(n4717), .Y(n4648) );
INVX2TS U2508 ( .A(n4625), .Y(n4647) );
CLKBUFX3TS U2509 ( .A(n850), .Y(n4650) );
INVX2TS U2510 ( .A(n364), .Y(n4663) );
INVX2TS U2511 ( .A(n365), .Y(n4664) );
INVX2TS U2512 ( .A(n333), .Y(n4686) );
BUFX3TS U2513 ( .A(n847), .Y(n4718) );
INVX2TS U2514 ( .A(n4671), .Y(n4676) );
INVX2TS U2515 ( .A(n328), .Y(n4703) );
BUFX3TS U2516 ( .A(n847), .Y(n4717) );
INVX2TS U2517 ( .A(n3994), .Y(add_x_23_n21) );
CLKBUFX3TS U2518 ( .A(n4799), .Y(n4445) );
NAND2X2TS U2519 ( .A(n4210), .B(n273), .Y(n3093) );
AOI2BB2X2TS U2520 ( .B0(n4236), .B1(n269), .A0N(n860), .A1N(n4766), .Y(n4105) );
BUFX3TS U2521 ( .A(n411), .Y(n4798) );
AOI22X1TS U2522 ( .A0(n4294), .A1(Add_result[15]), .B0(n4356), .B1(n4292),
.Y(n4976) );
BUFX3TS U2523 ( .A(n411), .Y(n888) );
BUFX3TS U2524 ( .A(n4941), .Y(n4943) );
BUFX3TS U2525 ( .A(n836), .Y(n4942) );
BUFX3TS U2526 ( .A(n4798), .Y(n4561) );
CLKINVX3TS U2527 ( .A(n865), .Y(n867) );
BUFX3TS U2528 ( .A(n888), .Y(n4947) );
BUFX3TS U2529 ( .A(n4802), .Y(n3971) );
CLKMX2X4TS U2530 ( .A(Data_MX[22]), .B(DP_OP_153J6_122_5442_n1504), .S0(
n3970), .Y(n366) );
CLKINVX3TS U2531 ( .A(n865), .Y(n857) );
CLKBUFX3TS U2532 ( .A(n850), .Y(n4468) );
INVX2TS U2533 ( .A(n377), .Y(n4846) );
CLKBUFX3TS U2534 ( .A(n888), .Y(n854) );
CLKINVX3TS U2535 ( .A(n865), .Y(n856) );
CLKAND2X2TS U2536 ( .A(n3014), .B(n3013), .Y(n3015) );
BUFX3TS U2537 ( .A(n4800), .Y(n4467) );
BUFX3TS U2538 ( .A(n836), .Y(n855) );
CLKINVX3TS U2539 ( .A(n865), .Y(n848) );
BUFX3TS U2540 ( .A(n4944), .Y(n4802) );
XOR2X1TS U2541 ( .A(n4194), .B(n4098), .Y(n4099) );
INVX2TS U2542 ( .A(n4095), .Y(n4097) );
CLKBUFX3TS U2543 ( .A(n4939), .Y(n4800) );
CLKINVX3TS U2544 ( .A(rst), .Y(n853) );
NAND3X1TS U2545 ( .A(n4935), .B(n4988), .C(FSM_selector_B_1_), .Y(n4215) );
BUFX3TS U2546 ( .A(n4950), .Y(n4941) );
CLKMX2X4TS U2547 ( .A(Data_MY[10]), .B(n698), .S0(n3964), .Y(n322) );
BUFX3TS U2548 ( .A(n836), .Y(n4560) );
INVX3TS U2549 ( .A(n865), .Y(n846) );
BUFX3TS U2550 ( .A(n411), .Y(n4796) );
BUFX3TS U2551 ( .A(n411), .Y(n4797) );
CLKBUFX3TS U2552 ( .A(n853), .Y(n4737) );
INVX2TS U2553 ( .A(n2283), .Y(n1760) );
INVX8TS U2554 ( .A(n843), .Y(n844) );
INVX4TS U2555 ( .A(n1449), .Y(n3319) );
XNOR2X4TS U2556 ( .A(n4727), .B(n2774), .Y(n708) );
AND2X4TS U2557 ( .A(n3892), .B(n1287), .Y(n710) );
INVX4TS U2558 ( .A(n3138), .Y(n962) );
AND2X2TS U2559 ( .A(n1195), .B(n2524), .Y(n713) );
INVX2TS U2560 ( .A(n3321), .Y(n1299) );
CLKINVX3TS U2561 ( .A(rst), .Y(n4991) );
INVX2TS U2562 ( .A(n971), .Y(n2612) );
INVX2TS U2563 ( .A(n1381), .Y(n4406) );
NAND2X4TS U2564 ( .A(n3120), .B(n1382), .Y(n1381) );
INVX2TS U2565 ( .A(n2754), .Y(n1213) );
OAI21X1TS U2566 ( .A0(n4081), .A1(n3036), .B0(n3035), .Y(n718) );
INVX2TS U2567 ( .A(n3816), .Y(n805) );
OR2X8TS U2568 ( .A(n2896), .B(n2895), .Y(n720) );
OR2X8TS U2569 ( .A(n2008), .B(n2009), .Y(n724) );
XNOR2X4TS U2570 ( .A(n4731), .B(n4732), .Y(n725) );
NOR2X6TS U2571 ( .A(n2237), .B(n2238), .Y(n2868) );
AND2X2TS U2572 ( .A(n1739), .B(n800), .Y(n729) );
INVX2TS U2573 ( .A(n783), .Y(n2762) );
NAND2X6TS U2574 ( .A(n2000), .B(n2001), .Y(n2092) );
NAND2X4TS U2575 ( .A(n1665), .B(n1666), .Y(n1184) );
INVX2TS U2576 ( .A(n1707), .Y(n1655) );
OA21X4TS U2577 ( .A0(n3454), .A1(n3457), .B0(n3458), .Y(n732) );
NAND2X4TS U2578 ( .A(n3300), .B(n3301), .Y(n3329) );
AND2X6TS U2579 ( .A(n3699), .B(n3703), .Y(n734) );
INVX4TS U2580 ( .A(n4138), .Y(n4186) );
NAND2X4TS U2581 ( .A(n2964), .B(n2965), .Y(n3877) );
OR2X2TS U2582 ( .A(n873), .B(n3140), .Y(n735) );
OA21X4TS U2583 ( .A0(n2066), .A1(n3396), .B0(n2067), .Y(n737) );
OR2X4TS U2584 ( .A(n3848), .B(n3801), .Y(n738) );
OR2X8TS U2585 ( .A(n3848), .B(add_x_55_n46), .Y(n739) );
NAND2X4TS U2586 ( .A(n2215), .B(n2214), .Y(n2234) );
XOR2X2TS U2587 ( .A(n2064), .B(n2063), .Y(n2073) );
INVX4TS U2588 ( .A(n2073), .Y(n1224) );
AND2X8TS U2589 ( .A(n933), .B(n2323), .Y(n741) );
INVX2TS U2590 ( .A(n919), .Y(n3171) );
AND2X2TS U2591 ( .A(n2467), .B(n682), .Y(n742) );
INVX2TS U2592 ( .A(n2163), .Y(n2233) );
OR2X2TS U2593 ( .A(n2679), .B(n4683), .Y(n743) );
CLKXOR2X2TS U2594 ( .A(n3860), .B(n3336), .Y(n3352) );
INVX4TS U2595 ( .A(n3271), .Y(n1119) );
NAND2X6TS U2596 ( .A(n436), .B(n3278), .Y(n3271) );
INVX4TS U2597 ( .A(n1436), .Y(n1262) );
INVX2TS U2598 ( .A(n3365), .Y(n1157) );
AND2X2TS U2599 ( .A(n1802), .B(n942), .Y(n745) );
NAND2X6TS U2600 ( .A(n1640), .B(n1052), .Y(n3365) );
AND2X4TS U2601 ( .A(n3234), .B(n462), .Y(n747) );
INVX2TS U2602 ( .A(n1402), .Y(n3426) );
AND2X4TS U2603 ( .A(n2166), .B(n955), .Y(n1402) );
INVX2TS U2604 ( .A(n1302), .Y(n3625) );
OR2X2TS U2605 ( .A(n3527), .B(n1317), .Y(n751) );
INVX2TS U2606 ( .A(n3349), .Y(n3353) );
INVX2TS U2607 ( .A(n3853), .Y(n887) );
NAND2X4TS U2608 ( .A(n1958), .B(n4567), .Y(n2610) );
INVX2TS U2609 ( .A(n3323), .Y(n1472) );
INVX2TS U2610 ( .A(n1933), .Y(n804) );
INVX2TS U2611 ( .A(n3320), .Y(n1471) );
NOR2X4TS U2612 ( .A(n1067), .B(n453), .Y(n3709) );
OR2X2TS U2613 ( .A(n2592), .B(n2591), .Y(n755) );
INVX2TS U2614 ( .A(n2110), .Y(n2111) );
INVX2TS U2615 ( .A(n708), .Y(n4162) );
INVX6TS U2616 ( .A(n3745), .Y(n3746) );
CLKBUFX3TS U2617 ( .A(n4941), .Y(n4801) );
CLKINVX3TS U2618 ( .A(n865), .Y(n836) );
INVX2TS U2619 ( .A(rst), .Y(n835) );
INVX2TS U2620 ( .A(rst), .Y(n849) );
INVX2TS U2621 ( .A(rst), .Y(n834) );
CLKBUFX3TS U2622 ( .A(n4800), .Y(n4447) );
INVX12TS U2623 ( .A(n1478), .Y(n874) );
XNOR2X4TS U2624 ( .A(n756), .B(n800), .Y(n3661) );
OR2X8TS U2625 ( .A(n758), .B(n1740), .Y(n757) );
AOI21X4TS U2626 ( .A0(n1286), .A1(DP_OP_154J6_123_2038_n388), .B0(n1285),
.Y(n1740) );
OAI22X4TS U2627 ( .A0(n763), .A1(n761), .B0(n760), .B1(n759), .Y(n1638) );
XNOR2X4TS U2628 ( .A(n763), .B(n762), .Y(n1589) );
XOR2X4TS U2629 ( .A(n819), .B(n764), .Y(n763) );
OAI21X2TS U2630 ( .A0(n3181), .A1(n769), .B0(n3180), .Y(n768) );
XNOR2X4TS U2631 ( .A(n770), .B(n3181), .Y(n3196) );
XOR2X4TS U2632 ( .A(n3180), .B(n771), .Y(n770) );
NAND2X8TS U2633 ( .A(n777), .B(n775), .Y(n3158) );
NOR2X8TS U2634 ( .A(n779), .B(n1233), .Y(n1092) );
NOR2X6TS U2635 ( .A(n1166), .B(n3350), .Y(n778) );
NOR2X4TS U2636 ( .A(n781), .B(n2761), .Y(n2767) );
NOR2X8TS U2637 ( .A(n2432), .B(n2433), .Y(n2761) );
NOR2X8TS U2638 ( .A(n2457), .B(n2456), .Y(n781) );
NAND2X4TS U2639 ( .A(n2423), .B(n2424), .Y(n783) );
OAI2BB1X4TS U2640 ( .A0N(n785), .A1N(n2405), .B0(n434), .Y(n782) );
NAND2X8TS U2641 ( .A(n2385), .B(n784), .Y(n2405) );
NAND3X6TS U2642 ( .A(n2379), .B(n2380), .C(n2381), .Y(n784) );
NOR2X2TS U2643 ( .A(n2404), .B(n2401), .Y(n785) );
NOR2X8TS U2644 ( .A(n2395), .B(n2396), .Y(n2404) );
XOR2X4TS U2645 ( .A(n4125), .B(n4132), .Y(n789) );
NAND2BX4TS U2646 ( .AN(n661), .B(n792), .Y(n791) );
XOR2X4TS U2647 ( .A(n1199), .B(n4137), .Y(n792) );
XOR2X4TS U2648 ( .A(n999), .B(n3985), .Y(n2725) );
XOR2X4TS U2649 ( .A(n1968), .B(n1969), .Y(n793) );
NAND2X4TS U2650 ( .A(n3463), .B(n3462), .Y(n3819) );
OR2X6TS U2651 ( .A(n3463), .B(n3462), .Y(n3820) );
OAI22X4TS U2652 ( .A0(n2481), .A1(n435), .B0(n2480), .B1(n2520), .Y(n2485)
);
NOR2X8TS U2653 ( .A(DP_OP_155J6_124_2038_n724), .B(n4491), .Y(n1871) );
NAND2X4TS U2654 ( .A(n1653), .B(n1650), .Y(n1592) );
BUFX6TS U2655 ( .A(n993), .Y(n937) );
CLKINVX6TS U2656 ( .A(DP_OP_156J6_125_3370_n272), .Y(n798) );
INVX4TS U2657 ( .A(Sgf_operation_EVEN1_Q_right[16]), .Y(
DP_OP_156J6_125_3370_n272) );
OR2X6TS U2658 ( .A(n438), .B(DP_OP_154J6_123_2038_n716), .Y(n1565) );
OAI22X2TS U2659 ( .A0(n950), .A1(n1228), .B0(n487), .B1(n1760), .Y(n1766) );
OAI22X2TS U2660 ( .A0(n950), .A1(n450), .B0(n487), .B1(n1228), .Y(n1770) );
NOR2X4TS U2661 ( .A(n1334), .B(n2298), .Y(n1333) );
OAI21X4TS U2662 ( .A0(n3108), .A1(n3111), .B0(n3109), .Y(n3428) );
CLKINVX12TS U2663 ( .A(n815), .Y(n2704) );
ADDFHX4TS U2664 ( .A(n2989), .B(n2987), .CI(n2988), .CO(n3617), .S(n2983) );
XOR2X4TS U2665 ( .A(n3159), .B(n3158), .Y(n803) );
NAND2X2TS U2666 ( .A(n2039), .B(n704), .Y(n2057) );
XOR2X2TS U2667 ( .A(n3780), .B(n3779), .Y(Sgf_operation_EVEN1_S_B[8]) );
OAI21X4TS U2668 ( .A0(n1695), .A1(n1696), .B0(n1694), .Y(n1356) );
ADDFHX4TS U2669 ( .A(n4436), .B(n4437), .CI(n4438), .CO(n2387), .S(n2354) );
XNOR2X4TS U2670 ( .A(n806), .B(n3814), .Y(n1072) );
INVX8TS U2671 ( .A(n1273), .Y(n3234) );
NOR2X4TS U2672 ( .A(DP_OP_155J6_124_2038_n721), .B(n4491), .Y(n1495) );
XNOR2X4TS U2673 ( .A(n1843), .B(n808), .Y(n1021) );
OAI22X2TS U2674 ( .A0(n1031), .A1(n2736), .B0(n2737), .B1(n3660), .Y(n2730)
);
NAND2X2TS U2675 ( .A(n1550), .B(n1551), .Y(n1552) );
XOR2X4TS U2676 ( .A(n3380), .B(n3379), .Y(n3414) );
NOR2X8TS U2677 ( .A(n1990), .B(n3251), .Y(n1865) );
ADDFHX4TS U2678 ( .A(n3143), .B(n3142), .CI(n3141), .CO(n3197), .S(n3150) );
INVX6TS U2679 ( .A(n2569), .Y(n2639) );
NAND2X2TS U2680 ( .A(n1734), .B(n465), .Y(n1550) );
INVX6TS U2681 ( .A(n1690), .Y(n1719) );
BUFX20TS U2682 ( .A(n3661), .Y(n1031) );
BUFX20TS U2683 ( .A(n4191), .Y(n1069) );
NOR2X4TS U2684 ( .A(n3888), .B(n3885), .Y(n1375) );
ADDFHX2TS U2685 ( .A(n3509), .B(n3508), .CI(n3507), .CO(n3531), .S(n3612) );
OAI22X1TS U2686 ( .A0(n3524), .A1(n3573), .B0(n2899), .B1(n1300), .Y(n3507)
);
INVX8TS U2687 ( .A(n1435), .Y(n3573) );
NAND2X6TS U2688 ( .A(DP_OP_154J6_123_2038_n386), .B(n4669), .Y(n1349) );
AND2X8TS U2689 ( .A(n813), .B(n814), .Y(n1030) );
INVX6TS U2690 ( .A(n3209), .Y(n1153) );
ADDFHX4TS U2691 ( .A(n1768), .B(n1767), .CI(n1766), .CO(n1774), .S(n1791) );
NAND2X8TS U2692 ( .A(n816), .B(n707), .Y(n815) );
NOR2BX4TS U2693 ( .AN(n694), .B(n682), .Y(n1911) );
AND2X8TS U2694 ( .A(n1207), .B(n2587), .Y(n817) );
XOR2X4TS U2695 ( .A(n1462), .B(n1463), .Y(n818) );
NOR2X4TS U2696 ( .A(n2569), .B(n2557), .Y(n1612) );
NAND2X4TS U2697 ( .A(n2569), .B(n2557), .Y(n1611) );
XOR2X4TS U2698 ( .A(n1570), .B(n1569), .Y(n819) );
XOR2X4TS U2699 ( .A(n2109), .B(n820), .Y(n895) );
NAND2X4TS U2700 ( .A(n2092), .B(n1465), .Y(n820) );
NAND3X6TS U2701 ( .A(n1431), .B(n1430), .C(n1267), .Y(n1429) );
INVX2TS U2702 ( .A(n2405), .Y(n2391) );
ADDFHX4TS U2703 ( .A(n2623), .B(n2622), .CI(n2621), .CO(n2685), .S(n2631) );
INVX6TS U2704 ( .A(Sgf_operation_EVEN1_Q_left[10]), .Y(n2326) );
ADDFHX4TS U2705 ( .A(n1676), .B(n1675), .CI(n1674), .CO(n822) );
OAI22X4TS U2706 ( .A0(n2571), .A1(n2627), .B0(n869), .B1(n2677), .Y(n1675)
);
NAND2X4TS U2707 ( .A(n4218), .B(n4217), .Y(n4219) );
XNOR2X4TS U2708 ( .A(n1247), .B(n823), .Y(n1907) );
AOI21X4TS U2709 ( .A0(n1057), .A1(n3773), .B0(n1361), .Y(
DP_OP_153J6_122_5442_n63) );
OAI22X2TS U2710 ( .A0(n1833), .A1(n1775), .B0(n1785), .B1(n839), .Y(n1784)
);
ADDFHX4TS U2711 ( .A(n1937), .B(n1938), .CI(n1936), .CO(n1951), .S(n1970) );
NAND2X2TS U2712 ( .A(n3100), .B(n3099), .Y(n3102) );
ADDFHX4TS U2713 ( .A(n1777), .B(n1771), .CI(n1770), .CO(n1780), .S(n1773) );
INVX8TS U2714 ( .A(n943), .Y(n2850) );
NAND2X6TS U2715 ( .A(n1102), .B(n3722), .Y(n3729) );
OAI21X4TS U2716 ( .A0(n611), .A1(n958), .B0(n1822), .Y(n957) );
OAI22X4TS U2717 ( .A0(n1814), .A1(n1812), .B0(n1804), .B1(n1354), .Y(n1822)
);
AND2X6TS U2718 ( .A(n978), .B(n3208), .Y(n977) );
NAND2BX4TS U2719 ( .AN(n4547), .B(n4532), .Y(n2110) );
OAI22X4TS U2720 ( .A0(n2913), .A1(n2912), .B0(n922), .B1(n1304), .Y(n2944)
);
ADDFHX4TS U2721 ( .A(n2646), .B(n2645), .CI(n2644), .CO(n2670), .S(n2633) );
INVX6TS U2722 ( .A(n3724), .Y(n2674) );
AND2X6TS U2723 ( .A(n1277), .B(n3349), .Y(n1269) );
CLKINVX12TS U2724 ( .A(n2112), .Y(n1415) );
INVX8TS U2725 ( .A(n895), .Y(n2112) );
NAND2X2TS U2726 ( .A(n3849), .B(n1369), .Y(n1425) );
NOR2X4TS U2727 ( .A(n2066), .B(n3395), .Y(n2030) );
NOR2X6TS U2728 ( .A(n2029), .B(n2028), .Y(n2066) );
XOR2X4TS U2729 ( .A(n2669), .B(n2738), .Y(n999) );
XNOR2X4TS U2730 ( .A(n1063), .B(n3766), .Y(n824) );
XNOR2X4TS U2731 ( .A(n1063), .B(n3766), .Y(n825) );
NAND3X4TS U2732 ( .A(n1388), .B(n2322), .C(n980), .Y(n934) );
OAI22X4TS U2733 ( .A0(n2212), .A1(n2475), .B0(n2473), .B1(n2474), .Y(n2488)
);
INVX4TS U2734 ( .A(n2969), .Y(n3506) );
BUFX6TS U2735 ( .A(n3622), .Y(n828) );
NAND2X4TS U2736 ( .A(n1104), .B(n827), .Y(n3337) );
NOR2X4TS U2737 ( .A(n1104), .B(n827), .Y(n3338) );
INVX8TS U2738 ( .A(n908), .Y(n2107) );
NAND2X4TS U2739 ( .A(n2065), .B(n3397), .Y(n1244) );
ADDFHX4TS U2740 ( .A(n2641), .B(n2640), .CI(n2639), .CO(n2681), .S(n2650) );
OR2X8TS U2741 ( .A(n1406), .B(n3218), .Y(n830) );
ADDHX4TS U2742 ( .A(DP_OP_154J6_123_2038_n600), .B(n1511), .CO(n1529), .S(
n1508) );
NOR2X2TS U2743 ( .A(n1041), .B(n3232), .Y(n3339) );
OAI21X2TS U2744 ( .A0(n3339), .A1(n3337), .B0(n3340), .Y(n3857) );
NOR2X2TS U2745 ( .A(n3338), .B(n3339), .Y(n3851) );
INVX8TS U2746 ( .A(Sgf_operation_EVEN1_Q_left[12]), .Y(n3816) );
ADDFHX4TS U2747 ( .A(n2931), .B(n2930), .CI(n2929), .CO(n2953), .S(n2960) );
OAI22X4TS U2748 ( .A0(n2241), .A1(n922), .B0(n2251), .B1(n2912), .Y(n2254)
);
ADDFHX4TS U2749 ( .A(n2255), .B(n2254), .CI(n2253), .CO(n2831), .S(n2266) );
NAND2X4TS U2750 ( .A(n1690), .B(n1043), .Y(n3362) );
NOR2X4TS U2751 ( .A(n3361), .B(n1549), .Y(n1526) );
NAND2X4TS U2752 ( .A(n1324), .B(n965), .Y(n964) );
OAI22X2TS U2753 ( .A0(n2840), .A1(n922), .B0(n2241), .B1(n2912), .Y(n2857)
);
OAI22X4TS U2754 ( .A0(n1031), .A1(n2642), .B0(n875), .B1(n2576), .Y(n2623)
);
ADDFHX4TS U2755 ( .A(n1799), .B(n1798), .CI(n1797), .CO(n1792), .S(n1800) );
OAI22X4TS U2756 ( .A0(n1795), .A1(n1819), .B0(n1765), .B1(n2282), .Y(n1798)
);
ADDFHX4TS U2757 ( .A(n1924), .B(n1922), .CI(n1923), .CO(n3160), .S(n1939) );
AND2X4TS U2758 ( .A(n2904), .B(n2905), .Y(n965) );
OAI22X2TS U2759 ( .A0(n950), .A1(n1841), .B0(n1842), .B1(n1834), .Y(n1838)
);
XOR2X4TS U2760 ( .A(n4172), .B(n4171), .Y(n4173) );
ADDFHX4TS U2761 ( .A(n4423), .B(n2450), .CI(n725), .CO(n2771), .S(n2453) );
ADDFHX4TS U2762 ( .A(n2846), .B(n2845), .CI(n2844), .CO(n2877), .S(n2835) );
ADDHX4TS U2763 ( .A(n2231), .B(n2230), .CO(n2845), .S(n2249) );
ADDFHX4TS U2764 ( .A(n2942), .B(n2941), .CI(n2940), .CO(n2949), .S(n2952) );
ADDHX4TS U2765 ( .A(n2878), .B(n2877), .CO(n2941), .S(n2886) );
OAI22X2TS U2766 ( .A0(n563), .A1(n2876), .B0(n1101), .B1(n2925), .Y(n2942)
);
ADDFHX4TS U2767 ( .A(n1494), .B(n1869), .CI(n1868), .CO(n1903), .S(n1917) );
ADDFHX4TS U2768 ( .A(n2955), .B(n2953), .CI(n2954), .CO(n2992), .S(n2956) );
OR2X6TS U2769 ( .A(n936), .B(n935), .Y(n2323) );
NOR2X8TS U2770 ( .A(n3585), .B(n3584), .Y(n3895) );
ADDFHX2TS U2771 ( .A(n3560), .B(n3559), .CI(n3558), .CO(n3570), .S(n3550) );
INVX6TS U2772 ( .A(n2884), .Y(n2910) );
ADDFHX2TS U2773 ( .A(n1875), .B(n1876), .CI(n1874), .CO(n1894), .S(n1950) );
ADDFHX4TS U2774 ( .A(n2888), .B(n2886), .CI(n2887), .CO(n2917), .S(n2889) );
NOR2X4TS U2775 ( .A(n699), .B(DP_OP_155J6_124_2038_n728), .Y(n3184) );
CLKINVX6TS U2776 ( .A(add_x_19_n291), .Y(add_x_19_n289) );
INVX12TS U2777 ( .A(n1401), .Y(n1815) );
OAI22X2TS U2778 ( .A0(n2873), .A1(n2912), .B0(n2913), .B1(n922), .Y(n2931)
);
NOR2X4TS U2779 ( .A(n2026), .B(n2027), .Y(n3395) );
NAND2X4TS U2780 ( .A(n1175), .B(n1714), .Y(n2128) );
ADDFHX2TS U2781 ( .A(n3288), .B(n3287), .CI(n3286), .CO(n3316), .S(n3285) );
ADDFHX4TS U2782 ( .A(n2986), .B(n2985), .CI(n2984), .CO(n3609), .S(n2980) );
NAND2X4TS U2783 ( .A(n3358), .B(n3357), .Y(n3359) );
ADDFHX4TS U2784 ( .A(n1977), .B(n1978), .CI(n1976), .CO(n1969), .S(n1996) );
ADDFHX4TS U2785 ( .A(n1955), .B(n1954), .CI(n1953), .CO(n1936), .S(n1976) );
NAND2X4TS U2786 ( .A(n1180), .B(n1755), .Y(n2594) );
NAND4X4TS U2787 ( .A(n522), .B(n3782), .C(n903), .D(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left_8_), .Y(n928) );
ADDFHX4TS U2788 ( .A(n3615), .B(n3614), .CI(n3613), .CO(n3633), .S(n3628) );
ADDFHX4TS U2789 ( .A(n1778), .B(n1777), .CI(n1776), .CO(n1783), .S(n1779) );
XNOR2X4TS U2790 ( .A(n417), .B(n1059), .Y(n1775) );
ADDFHX4TS U2791 ( .A(n3545), .B(n713), .CI(n3544), .CO(n3546), .S(n3521) );
INVX2TS U2792 ( .A(n3521), .Y(n3540) );
NAND2X4TS U2793 ( .A(n3782), .B(n1281), .Y(n1245) );
NAND2X4TS U2794 ( .A(n1098), .B(n1056), .Y(n1614) );
NAND2X2TS U2795 ( .A(n1181), .B(n2716), .Y(n2710) );
XNOR2X2TS U2796 ( .A(n1003), .B(n2676), .Y(n2728) );
NAND2X6TS U2797 ( .A(n1203), .B(n1432), .Y(n1202) );
NAND2X4TS U2798 ( .A(n444), .B(n3492), .Y(n1416) );
XOR2X4TS U2799 ( .A(n984), .B(n831), .Y(n978) );
OR2X8TS U2800 ( .A(n1120), .B(n1379), .Y(n831) );
NAND3X6TS U2801 ( .A(n1431), .B(n1267), .C(n3849), .Y(n1426) );
ADDFHX4TS U2802 ( .A(n3655), .B(n3654), .CI(n3653), .CO(n3681), .S(n3665) );
BUFX6TS U2803 ( .A(n1380), .Y(n1060) );
OAI21X2TS U2804 ( .A0(n1233), .A1(n3803), .B0(n911), .Y(add_x_55_n54) );
NAND2X4TS U2805 ( .A(n1231), .B(n1432), .Y(n1389) );
NAND2X8TS U2806 ( .A(n2151), .B(n2282), .Y(n1819) );
INVX16TS U2807 ( .A(n1353), .Y(n2151) );
ADDHX4TS U2808 ( .A(n1825), .B(n1824), .CO(n2166), .S(n2229) );
XOR2X4TS U2809 ( .A(n968), .B(n1262), .Y(n3557) );
NAND2X8TS U2810 ( .A(n952), .B(n3477), .Y(n1205) );
NAND2X4TS U2811 ( .A(n3477), .B(n952), .Y(n832) );
INVX8TS U2812 ( .A(n1050), .Y(n3748) );
AOI2BB2X2TS U2813 ( .B0(n441), .B1(n4228), .A0N(n860), .A1N(n4786), .Y(n4975) );
OAI21X4TS U2814 ( .A0(n3077), .A1(n3076), .B0(n3075), .Y(n3737) );
AOI21X2TS U2815 ( .A0(n2102), .A1(n2080), .B0(n2079), .Y(n2081) );
OAI22X2TS U2816 ( .A0(n1031), .A1(n2677), .B0(n875), .B1(n2627), .Y(n2664)
);
NAND3X6TS U2817 ( .A(n1014), .B(n1015), .C(n1009), .Y(n1008) );
NAND2X6TS U2818 ( .A(n1282), .B(n3649), .Y(n1015) );
NAND2X6TS U2819 ( .A(n3699), .B(n3649), .Y(n1002) );
BUFX3TS U2820 ( .A(n4797), .Y(n4946) );
INVX4TS U2821 ( .A(n1831), .Y(n837) );
OAI22X1TS U2822 ( .A0(n1007), .A1(n563), .B0(n1101), .B1(n3551), .Y(n3558)
);
OAI22X2TS U2823 ( .A0(n1833), .A1(n1769), .B0(n1775), .B1(n840), .Y(n1781)
);
OAI22X2TS U2824 ( .A0(n1833), .A1(n1796), .B0(n1763), .B1(n840), .Y(n1793)
);
OAI22X2TS U2825 ( .A0(n3498), .A1(n3520), .B0(n3519), .B1(n447), .Y(n3509)
);
OAI22X2TS U2826 ( .A0(n2920), .A1(n842), .B0(n2879), .B1(n3520), .Y(n2940)
);
CLKBUFX3TS U2827 ( .A(n4940), .Y(n4738) );
CLKBUFX3TS U2828 ( .A(n4800), .Y(n4651) );
OAI22X2TS U2829 ( .A0(n3139), .A1(n3293), .B0(n397), .B1(n3309), .Y(n3147)
);
OAI22X2TS U2830 ( .A0(n3139), .A1(n3179), .B0(n398), .B1(n3256), .Y(n1875)
);
OAI22X4TS U2831 ( .A0(n398), .A1(n3144), .B0(n852), .B1(n3186), .Y(n1961) );
OAI22X4TS U2832 ( .A0(n398), .A1(n3179), .B0(n852), .B1(n3256), .Y(n1935) );
OAI22X2TS U2833 ( .A0(n397), .A1(n1963), .B0(n852), .B1(n3140), .Y(n1982) );
OAI22X2TS U2834 ( .A0(n398), .A1(n1989), .B0(n852), .B1(n1987), .Y(n1992) );
CLKBUFX3TS U2835 ( .A(n4799), .Y(n4446) );
INVX2TS U2836 ( .A(n862), .Y(n863) );
INVX2TS U2837 ( .A(n4346), .Y(n4347) );
AO22X2TS U2838 ( .A0(n4309), .A1(n4346), .B0(final_result_ieee[13]), .B1(
n4308), .Y(n187) );
OAI21X2TS U2839 ( .A0(n3213), .A1(n3216), .B0(n3214), .Y(n3222) );
CLKBUFX3TS U2840 ( .A(n4799), .Y(n4466) );
BUFX3TS U2841 ( .A(n847), .Y(n4948) );
BUFX3TS U2842 ( .A(n848), .Y(n4649) );
BUFX3TS U2843 ( .A(n3971), .Y(n4716) );
BUFX3TS U2844 ( .A(n3971), .Y(n4713) );
BUFX3TS U2845 ( .A(n3971), .Y(n4715) );
BUFX3TS U2846 ( .A(n3971), .Y(n4714) );
OAI22X2TS U2847 ( .A0(n2571), .A1(n2736), .B0(n869), .B1(n3660), .Y(n2558)
);
OAI22X2TS U2848 ( .A0(n2571), .A1(n2576), .B0(n869), .B1(n2642), .Y(n1628)
);
NAND2X2TS U2849 ( .A(n4187), .B(n4190), .Y(n4193) );
NAND2X2TS U2850 ( .A(n4187), .B(n4138), .Y(n4141) );
NAND2X2TS U2851 ( .A(n870), .B(n4147), .Y(n4149) );
NAND2X2TS U2852 ( .A(n4187), .B(n4180), .Y(n4182) );
INVX6TS U2853 ( .A(n3250), .Y(n872) );
OAI22X4TS U2854 ( .A0(n871), .A1(n3144), .B0(n1480), .B1(n3186), .Y(n1924)
);
OAI22X4TS U2855 ( .A0(n872), .A1(n1963), .B0(n416), .B1(n3140), .Y(n1949) );
OAI22X2TS U2856 ( .A0(n795), .A1(n1989), .B0(n871), .B1(n1987), .Y(n1947) );
OAI22X2TS U2857 ( .A0(n795), .A1(n3179), .B0(n871), .B1(n3256), .Y(n3181) );
OAI22X2TS U2858 ( .A0(n3139), .A1(n3144), .B0(n398), .B1(n3186), .Y(n1937)
);
OAI22X2TS U2859 ( .A0(n873), .A1(n1963), .B0(n398), .B1(n3140), .Y(n1978) );
OAI22X4TS U2860 ( .A0(n1480), .A1(n3179), .B0(n3256), .B1(n873), .Y(n1900)
);
INVX4TS U2861 ( .A(n1257), .Y(n3139) );
INVX8TS U2862 ( .A(n1478), .Y(n875) );
OAI22X4TS U2863 ( .A0(n2679), .A1(n2667), .B0(n2571), .B1(n2733), .Y(n2577)
);
OAI22X4TS U2864 ( .A0(n2737), .A1(n2736), .B0(n2679), .B1(n3660), .Y(n2660)
);
OAI22X4TS U2865 ( .A0(n876), .A1(n1741), .B0(n2571), .B1(n2572), .Y(n1626)
);
CLKBUFX2TS U2866 ( .A(Add_result[9]), .Y(n878) );
CLKBUFX2TS U2867 ( .A(Add_result[10]), .Y(n879) );
CLKBUFX2TS U2868 ( .A(Add_result[12]), .Y(n880) );
OAI21X1TS U2869 ( .A0(n4201), .A1(n3840), .B0(n3839), .Y(n3841) );
NOR2X1TS U2870 ( .A(FSM_selector_B_1_), .B(Op_MY[23]), .Y(n3840) );
INVX2TS U2871 ( .A(n4316), .Y(n4331) );
OAI21X2TS U2872 ( .A0(n4313), .A1(n4773), .B0(n4237), .Y(n4316) );
OAI21X2TS U2873 ( .A0(n3712), .A1(n3711), .B0(n3710), .Y(n3713) );
NAND2X2TS U2874 ( .A(n2847), .B(n2856), .Y(n3919) );
NAND2X1TS U2875 ( .A(n3906), .B(n2537), .Y(n2539) );
OR2X4TS U2876 ( .A(n3392), .B(n3391), .Y(n3394) );
NOR2X2TS U2877 ( .A(n349), .B(n4821), .Y(n4588) );
XOR2X4TS U2878 ( .A(n3693), .B(n3676), .Y(n3720) );
CLKXOR2X2TS U2879 ( .A(n3276), .B(n3275), .Y(n3277) );
XNOR2X4TS U2880 ( .A(n3697), .B(n3696), .Y(n3721) );
NAND3X2TS U2881 ( .A(n4090), .B(n4089), .C(n4088), .Y(n205) );
CLKBUFX2TS U2882 ( .A(Sgf_normalized_result[21]), .Y(n886) );
NOR2X1TS U2883 ( .A(n3850), .B(n887), .Y(n3856) );
NOR2X2TS U2884 ( .A(n326), .B(n314), .Y(n3944) );
NAND2X2TS U2885 ( .A(n4336), .B(n4243), .Y(n4244) );
CLKBUFX3TS U2886 ( .A(n4939), .Y(n4799) );
AOI2BB2X2TS U2887 ( .B0(n441), .B1(n264), .A0N(n859), .A1N(n4771), .Y(n4067)
);
AOI2BB2X2TS U2888 ( .B0(n441), .B1(n263), .A0N(n859), .A1N(n4055), .Y(n4057)
);
NAND3X8TS U2889 ( .A(n1219), .B(n2586), .C(n2656), .Y(n1456) );
NAND3X8TS U2890 ( .A(n893), .B(n892), .C(n3494), .Y(n979) );
NAND3X8TS U2891 ( .A(n830), .B(n1414), .C(n3492), .Y(n893) );
NAND2X8TS U2892 ( .A(n993), .B(n979), .Y(n952) );
INVX16TS U2893 ( .A(n897), .Y(n3803) );
NAND2X4TS U2894 ( .A(n896), .B(n966), .Y(n931) );
OR2X8TS U2895 ( .A(n3723), .B(n3722), .Y(n966) );
XOR2X4TS U2896 ( .A(n3708), .B(n1192), .Y(n3723) );
XOR2X4TS U2897 ( .A(n897), .B(n1389), .Y(n1469) );
NAND2X8TS U2898 ( .A(n951), .B(n3479), .Y(n897) );
ADDFHX4TS U2899 ( .A(n2325), .B(n2324), .CI(n2326), .CO(n3588), .S(n3373) );
CLKINVX12TS U2900 ( .A(DP_OP_153J6_122_5442_n1191), .Y(n2123) );
XNOR2X4TS U2901 ( .A(n2211), .B(n2210), .Y(n898) );
OAI2BB1X4TS U2902 ( .A0N(n900), .A1N(n899), .B0(n1021), .Y(n1020) );
INVX2TS U2903 ( .A(n2245), .Y(n2246) );
NAND3X6TS U2904 ( .A(n3360), .B(n2132), .C(n3358), .Y(n1183) );
XOR2X4TS U2905 ( .A(n996), .B(n1673), .Y(n1680) );
INVX4TS U2906 ( .A(n3677), .Y(n3974) );
NOR2X2TS U2907 ( .A(n1545), .B(n1544), .Y(n1554) );
NAND2X8TS U2908 ( .A(n904), .B(n4921), .Y(n4199) );
OAI21X4TS U2909 ( .A0(n4006), .A1(FS_Module_state_reg[2]), .B0(n3759), .Y(
n4981) );
NAND2X2TS U2910 ( .A(n2133), .B(n2132), .Y(n2134) );
CLKXOR2X2TS U2911 ( .A(n2148), .B(n2176), .Y(n2149) );
NAND2X8TS U2912 ( .A(n2165), .B(n2149), .Y(n3520) );
NAND2X4TS U2913 ( .A(n3752), .B(n870), .Y(n3754) );
INVX8TS U2914 ( .A(n1400), .Y(n2837) );
XNOR2X4TS U2915 ( .A(n905), .B(n2122), .Y(Sgf_operation_EVEN1_Q_left[10]) );
ADDFHX4TS U2916 ( .A(n2968), .B(n2967), .CI(n2966), .CO(n3621), .S(n2981) );
NAND2X8TS U2917 ( .A(n1338), .B(n839), .Y(n1833) );
INVX8TS U2918 ( .A(Sgf_operation_EVEN1_Q_left[7]), .Y(n3452) );
XOR2X4TS U2919 ( .A(n2094), .B(n2093), .Y(n908) );
OAI22X2TS U2920 ( .A0(n1480), .A1(n1989), .B0(n873), .B1(n1987), .Y(n1977)
);
ADDFHX4TS U2921 ( .A(n1882), .B(n1881), .CI(n1880), .CO(n3165), .S(n1944) );
NOR2X8TS U2922 ( .A(n920), .B(n1105), .Y(n984) );
INVX12TS U2923 ( .A(n1277), .Y(n3802) );
NAND2X8TS U2924 ( .A(n910), .B(n1167), .Y(n1369) );
NOR2X8TS U2925 ( .A(n754), .B(n913), .Y(n3491) );
NAND2X8TS U2926 ( .A(n913), .B(n754), .Y(n3492) );
XOR2X4TS U2927 ( .A(n1152), .B(n1126), .Y(n913) );
XOR2X4TS U2928 ( .A(n1191), .B(n1189), .Y(n1406) );
XNOR2X4TS U2929 ( .A(n916), .B(n915), .Y(n3828) );
OAI21X4TS U2930 ( .A0(n3211), .A1(n3209), .B0(n3212), .Y(n1105) );
NAND2X8TS U2931 ( .A(n1946), .B(n1945), .Y(n3209) );
NOR2X8TS U2932 ( .A(n3170), .B(n3169), .Y(n3211) );
NAND2X6TS U2933 ( .A(n3169), .B(n3170), .Y(n3212) );
NOR2X8TS U2934 ( .A(n1380), .B(n919), .Y(n920) );
NAND2X8TS U2935 ( .A(n1127), .B(n724), .Y(n1126) );
NOR2X8TS U2936 ( .A(n3210), .B(n3211), .Y(n918) );
XOR2X4TS U2937 ( .A(n921), .B(n2320), .Y(n3408) );
INVX2TS U2938 ( .A(n3408), .Y(n4384) );
NAND2X8TS U2939 ( .A(n2223), .B(n922), .Y(n2912) );
INVX12TS U2940 ( .A(n2219), .Y(n922) );
OAI21X4TS U2941 ( .A0(n448), .A1(n2914), .B0(n2912), .Y(n2279) );
XOR2X4TS U2942 ( .A(n2217), .B(n2222), .Y(n923) );
NAND2X8TS U2943 ( .A(n4659), .B(DP_OP_153J6_122_5442_n1207), .Y(n925) );
INVX12TS U2944 ( .A(n1053), .Y(n2737) );
XOR2X4TS U2945 ( .A(n927), .B(n1740), .Y(n2678) );
XOR2X4TS U2946 ( .A(n1076), .B(n2545), .Y(n2525) );
INVX8TS U2947 ( .A(n3154), .Y(n3192) );
INVX12TS U2948 ( .A(n3972), .Y(n929) );
NAND2X4TS U2949 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left_8_),
.B(n1457), .Y(n930) );
NAND2X8TS U2950 ( .A(n931), .B(n3729), .Y(n1457) );
XOR2X4TS U2951 ( .A(n2016), .B(n2015), .Y(n935) );
XOR2X4TS U2952 ( .A(n2047), .B(n2046), .Y(n936) );
NAND2X8TS U2953 ( .A(n934), .B(n741), .Y(n2140) );
AND2X8TS U2954 ( .A(n2075), .B(n2074), .Y(n2321) );
INVX12TS U2955 ( .A(n977), .Y(n3477) );
XOR2X4TS U2956 ( .A(n941), .B(n939), .Y(Sgf_operation_EVEN1_Q_right[16]) );
NAND2X8TS U2957 ( .A(n940), .B(n3277), .Y(n3479) );
NAND3X8TS U2958 ( .A(n1117), .B(n1115), .C(n1116), .Y(n940) );
AOI21X4TS U2959 ( .A0(n937), .A1(n938), .B0(n890), .Y(n941) );
OR2X8TS U2960 ( .A(n978), .B(n3208), .Y(n993) );
XOR2X4TS U2961 ( .A(n2839), .B(n2837), .Y(n1338) );
XOR2X4TS U2962 ( .A(n1802), .B(n942), .Y(n1809) );
OAI22X4TS U2963 ( .A0(n1814), .A1(n1804), .B0(n1794), .B1(n1354), .Y(n942)
);
XOR2X4TS U2964 ( .A(n1759), .B(n2123), .Y(n943) );
INVX12TS U2965 ( .A(n1437), .Y(n2899) );
XOR2X4TS U2966 ( .A(n945), .B(n944), .Y(n1435) );
XOR2X4TS U2967 ( .A(n2883), .B(n2900), .Y(n944) );
NOR2X8TS U2968 ( .A(n3642), .B(n3641), .Y(n3884) );
XOR2X4TS U2969 ( .A(n1139), .B(n1773), .Y(n949) );
NOR2X4TS U2970 ( .A(n950), .B(n925), .Y(n1797) );
OAI22X2TS U2971 ( .A0(n950), .A1(n1479), .B0(n487), .B1(n450), .Y(n1776) );
OAI22X2TS U2972 ( .A0(n950), .A1(n1142), .B0(n487), .B1(n1479), .Y(n1788) );
AOI2BB2X4TS U2973 ( .B0(n1786), .B1(n1078), .A0N(n1834), .A1N(n950), .Y(
n1787) );
NAND2X8TS U2974 ( .A(n428), .B(n1842), .Y(n950) );
CLKINVX1TS U2975 ( .A(n2905), .Y(n2872) );
NAND2X8TS U2976 ( .A(n1205), .B(n1188), .Y(n951) );
NAND4X8TS U2977 ( .A(n1117), .B(n1115), .C(n1116), .D(n1118), .Y(n1188) );
BUFX6TS U2978 ( .A(n980), .Y(n954) );
BUFX6TS U2979 ( .A(n2168), .Y(n955) );
INVX2TS U2980 ( .A(n959), .Y(n958) );
NAND2X8TS U2981 ( .A(n961), .B(n3153), .Y(n2058) );
XNOR2X4TS U2982 ( .A(n3786), .B(n2907), .Y(n1304) );
OAI21X4TS U2983 ( .A0(n2871), .A1(n2870), .B0(n2869), .Y(n2906) );
INVX2TS U2984 ( .A(n966), .Y(n1283) );
OAI2BB1X4TS U2985 ( .A0N(n3416), .A1N(n3415), .B0(n967), .Y(n3374) );
OAI21X4TS U2986 ( .A0(n3415), .A1(n3416), .B0(n3417), .Y(n967) );
BUFX12TS U2987 ( .A(n1362), .Y(n968) );
XOR2X4TS U2988 ( .A(n968), .B(n448), .Y(n2913) );
XOR2X4TS U2989 ( .A(n1295), .B(n1294), .Y(n1362) );
INVX12TS U2990 ( .A(n1551), .Y(n1549) );
OR2X8TS U2991 ( .A(n1734), .B(n465), .Y(n1551) );
NAND2X8TS U2992 ( .A(n961), .B(n3159), .Y(n975) );
OAI21X4TS U2993 ( .A0(n974), .A1(n3159), .B0(n3158), .Y(n976) );
NOR2X8TS U2994 ( .A(n2056), .B(n2048), .Y(n2096) );
XNOR2X4TS U2995 ( .A(n982), .B(n981), .Y(n4405) );
CLKINVX6TS U2996 ( .A(n3279), .Y(n985) );
OAI2BB1X4TS U2997 ( .A0N(n988), .A1N(n1491), .B0(n986), .Y(n2083) );
XOR2X4TS U2998 ( .A(n1491), .B(n987), .Y(n2042) );
XOR2X4TS U2999 ( .A(n989), .B(n988), .Y(n987) );
NOR2X8TS U3000 ( .A(n4482), .B(DP_OP_155J6_124_2038_n640), .Y(n988) );
NAND2X8TS U3001 ( .A(n992), .B(n3304), .Y(n3305) );
XOR2X4TS U3002 ( .A(n995), .B(n994), .Y(n1724) );
NAND2X8TS U3003 ( .A(n1673), .B(n996), .Y(n995) );
NAND2X8TS U3004 ( .A(n1672), .B(n1631), .Y(n1340) );
NAND2X8TS U3005 ( .A(n1000), .B(n1216), .Y(n1212) );
NAND3X8TS U3006 ( .A(n1001), .B(n1002), .C(n1211), .Y(n1210) );
INVX12TS U3007 ( .A(n509), .Y(n1001) );
XOR2X4TS U3008 ( .A(n2734), .B(n2735), .Y(n1003) );
NAND2X4TS U3009 ( .A(n1005), .B(n1649), .Y(n1699) );
NOR2X6TS U3010 ( .A(n1005), .B(n1649), .Y(n1701) );
XOR2X4TS U3011 ( .A(n1049), .B(n1683), .Y(n1005) );
OAI2BB1X4TS U3012 ( .A0N(n1633), .A1N(n1634), .B0(n1006), .Y(n1691) );
OAI21X4TS U3013 ( .A0(n1634), .A1(n1633), .B0(n1635), .Y(n1006) );
NAND2X8TS U3014 ( .A(n1011), .B(n1013), .Y(n1010) );
OR2X8TS U3015 ( .A(n1015), .B(n3692), .Y(n1012) );
XNOR2X4TS U3016 ( .A(DP_OP_154J6_123_2038_n387), .B(n1349), .Y(n1016) );
INVX12TS U3017 ( .A(n2636), .Y(n2571) );
XOR2X4TS U3018 ( .A(DP_OP_154J6_123_2038_n361), .B(DP_OP_154J6_123_2038_n392), .Y(n2570) );
NOR2X8TS U3019 ( .A(n2658), .B(n2657), .Y(n1206) );
ADDFHX2TS U3020 ( .A(n1932), .B(n1931), .CI(n1930), .CO(n1940), .S(n1966) );
ADDFHX4TS U3021 ( .A(n1737), .B(n1738), .CI(n1736), .CO(n2550), .S(n1731) );
NAND2X2TS U3022 ( .A(n3449), .B(n3450), .Y(n3824) );
XNOR2X4TS U3023 ( .A(n4577), .B(n4576), .Y(n2330) );
OAI21X1TS U3024 ( .A0(n4081), .A1(n3042), .B0(n4031), .Y(n3045) );
OAI21X1TS U3025 ( .A0(n3012), .A1(n3008), .B0(n3013), .Y(n2331) );
OAI2BB1X4TS U3026 ( .A0N(n1873), .A1N(n1872), .B0(n1020), .Y(n1906) );
OR2X8TS U3027 ( .A(n2874), .B(n1252), .Y(n1023) );
NAND2X2TS U3028 ( .A(n2928), .B(n2927), .Y(n2934) );
NOR2X6TS U3029 ( .A(n4672), .B(DP_OP_154J6_123_2038_n718), .Y(n2668) );
ADDFHX4TS U3030 ( .A(n1949), .B(n1948), .CI(n1947), .CO(n1941), .S(n2007) );
ADDFX2TS U3031 ( .A(n3656), .B(n3657), .CI(n3658), .CO(n3688), .S(n3655) );
OAI2BB1X4TS U3032 ( .A0N(n1082), .A1N(n2017), .B0(n1027), .Y(n1927) );
OAI21X4TS U3033 ( .A0(n1082), .A1(n2017), .B0(n1959), .Y(n1027) );
XNOR2X4TS U3034 ( .A(n1028), .B(n1959), .Y(n1983) );
XNOR2X4TS U3035 ( .A(n1082), .B(n2017), .Y(n1028) );
OAI21X4TS U3036 ( .A0(n4022), .A1(n2375), .B0(n2374), .Y(n2376) );
XNOR2X4TS U3037 ( .A(n1965), .B(n1966), .Y(n1442) );
OAI21X4TS U3038 ( .A0(n4194), .A1(n2616), .B0(n3590), .Y(n2619) );
XOR2X4TS U3039 ( .A(n1420), .B(n1985), .Y(n1993) );
XNOR2X4TS U3040 ( .A(n2352), .B(n2379), .Y(n2370) );
NOR2X8TS U3041 ( .A(n852), .B(n1963), .Y(n1986) );
INVX2TS U3042 ( .A(n2060), .Y(n2062) );
XNOR2X4TS U3043 ( .A(n1029), .B(n1441), .Y(n1852) );
AND2X6TS U3044 ( .A(n4684), .B(n4685), .Y(n1530) );
AND2X8TS U3045 ( .A(n1689), .B(n1030), .Y(n1728) );
XOR2X4TS U3046 ( .A(n1689), .B(n1030), .Y(n1678) );
NOR2X8TS U3047 ( .A(n3775), .B(n3774), .Y(n3888) );
XNOR2X4TS U3048 ( .A(DP_OP_153J6_122_5442_n1150), .B(
DP_OP_153J6_122_5442_n1207), .Y(n1033) );
OAI21X4TS U3049 ( .A0(n3379), .A1(n3376), .B0(n3377), .Y(n2310) );
OAI22X4TS U3050 ( .A0(n1795), .A1(n2282), .B0(n1819), .B1(n1803), .Y(n1802)
);
OAI22X2TS U3051 ( .A0(n2260), .A1(n922), .B0(n2173), .B1(n2912), .Y(n2278)
);
XOR2X4TS U3052 ( .A(n2222), .B(n2221), .Y(n2223) );
AND2X8TS U3053 ( .A(n1843), .B(DP_OP_155J6_124_2038_n699), .Y(n1910) );
NOR2X8TS U3054 ( .A(n1153), .B(n3210), .Y(n1152) );
NOR2X8TS U3055 ( .A(n1946), .B(n1945), .Y(n3210) );
ADDFHX2TS U3056 ( .A(DP_OP_154J6_123_2038_n699), .B(
DP_OP_154J6_123_2038_n684), .CI(n2643), .CO(n2671), .S(n2635) );
ADDFHX4TS U3057 ( .A(n2121), .B(n1156), .CI(n2120), .CO(
DP_OP_156J6_125_3370_n227), .S(DP_OP_156J6_125_3370_n228) );
XOR2X4TS U3058 ( .A(n2308), .B(n2307), .Y(n3811) );
XNOR2X4TS U3059 ( .A(n1034), .B(n1434), .Y(n1433) );
AOI21X4TS U3060 ( .A0(n2123), .A1(DP_OP_153J6_122_5442_n1181), .B0(
DP_OP_153J6_122_5442_n1182), .Y(n1034) );
NAND2X8TS U3061 ( .A(n2188), .B(n2187), .Y(n2200) );
XOR2X4TS U3062 ( .A(n1331), .B(n1670), .Y(n1297) );
OAI22X2TS U3063 ( .A0(n1031), .A1(n2576), .B0(n2737), .B1(n2642), .Y(n2561)
);
OAI2BB1X4TS U3064 ( .A0N(n3268), .A1N(n3267), .B0(n1036), .Y(n3269) );
OAI21X2TS U3065 ( .A0(n3267), .A1(n3268), .B0(n3266), .Y(n1036) );
XOR2X4TS U3066 ( .A(n1037), .B(n3266), .Y(n3203) );
XOR2X4TS U3067 ( .A(n3268), .B(n3267), .Y(n1037) );
ADDFHX4TS U3068 ( .A(n3176), .B(n962), .CI(n3175), .CO(n3246), .S(n3198) );
OAI2BB1X4TS U3069 ( .A0N(n1040), .A1N(n1533), .B0(n1038), .Y(n1597) );
OAI21X4TS U3070 ( .A0(n1533), .A1(n1040), .B0(n1532), .Y(n1038) );
XOR2X4TS U3071 ( .A(n1039), .B(n1532), .Y(n1535) );
NOR2X8TS U3072 ( .A(DP_OP_154J6_123_2038_n630), .B(n440), .Y(n1040) );
INVX2TS U3073 ( .A(n3694), .Y(n2573) );
XOR2X4TS U3074 ( .A(n731), .B(n711), .Y(n1182) );
BUFX6TS U3075 ( .A(n4668), .Y(n1042) );
NOR2X8TS U3076 ( .A(n2965), .B(n2964), .Y(n3876) );
ADDFHX4TS U3077 ( .A(DP_OP_154J6_123_2038_n693), .B(
DP_OP_154J6_123_2038_n683), .CI(n2668), .CO(n2732), .S(n2672) );
INVX2TS U3078 ( .A(n2598), .Y(n1574) );
ADDFHX2TS U3079 ( .A(n3146), .B(n3147), .CI(n3145), .CO(n3180), .S(n3162) );
ADDFHX2TS U3080 ( .A(n2034), .B(n1490), .CI(n1493), .CO(n2044), .S(n2033) );
NAND3X2TS U3081 ( .A(n4109), .B(n4108), .C(n4107), .Y(n207) );
ADDFHX2TS U3082 ( .A(n2409), .B(n2408), .CI(n2407), .S(n2397) );
OAI21X4TS U3083 ( .A0(n3596), .A1(n3591), .B0(n3597), .Y(n2441) );
NOR2X2TS U3084 ( .A(n3043), .B(n2365), .Y(n2367) );
AOI21X2TS U3085 ( .A0(n2805), .A1(n2784), .B0(n2783), .Y(n2785) );
OAI21X4TS U3086 ( .A0(n877), .A1(n2786), .B0(n2785), .Y(n2800) );
INVX2TS U3087 ( .A(n2170), .Y(n2160) );
XNOR2X4TS U3088 ( .A(n2216), .B(n1263), .Y(n1048) );
NOR2X2TS U3089 ( .A(n3518), .B(n845), .Y(n3542) );
INVX12TS U3090 ( .A(n3803), .Y(n1427) );
ADDFHX4TS U3091 ( .A(n1889), .B(n1888), .CI(n1887), .CO(n2032), .S(n1902) );
NOR2X8TS U3092 ( .A(n4667), .B(n809), .Y(n1533) );
ADDHX4TS U3093 ( .A(DP_OP_154J6_123_2038_n617), .B(DP_OP_154J6_123_2038_n612), .CO(n1521), .S(n1575) );
ADDHX4TS U3094 ( .A(n815), .B(n1632), .CO(n1673), .S(n1648) );
XOR2X4TS U3095 ( .A(n1256), .B(DP_OP_155J6_124_2038_n698), .Y(n1247) );
XOR2X4TS U3096 ( .A(n1684), .B(n1685), .Y(n1049) );
OR2X8TS U3097 ( .A(n2812), .B(n4841), .Y(n4091) );
CLKXOR2X2TS U3098 ( .A(n3486), .B(n3485), .Y(Sgf_operation_EVEN1_S_B[4]) );
ADDFHX4TS U3099 ( .A(n1529), .B(n1528), .CI(n1527), .CO(n1594), .S(n1534) );
ADDFHX4TS U3100 ( .A(n2675), .B(n2674), .CI(n2673), .CO(n2729), .S(n2680) );
NAND2X8TS U3101 ( .A(n4138), .B(n3749), .Y(n4164) );
NOR2X8TS U3102 ( .A(n4150), .B(n4144), .Y(n4138) );
ADDHX4TS U3103 ( .A(n1879), .B(n1878), .CO(n1897), .S(n1912) );
CLKINVX12TS U3104 ( .A(n3992), .Y(n3995) );
NAND2X8TS U3105 ( .A(n1111), .B(n3271), .Y(n1115) );
XNOR2X4TS U3106 ( .A(n1198), .B(n3744), .Y(n1050) );
XOR2X4TS U3107 ( .A(n1454), .B(DP_OP_154J6_123_2038_n611), .Y(n1520) );
ADDFHX2TS U3108 ( .A(n3688), .B(n3687), .CI(n3686), .CO(n3704), .S(n3680) );
OAI21X4TS U3109 ( .A0(n877), .A1(n4129), .B0(n4128), .Y(n4130) );
AOI2BB2X2TS U3110 ( .B0(n4236), .B1(n4217), .A0N(n860), .A1N(n4750), .Y(
n4204) );
NOR2X6TS U3111 ( .A(DP_OP_154J6_123_2038_n716), .B(DP_OP_154J6_123_2038_n719), .Y(n1687) );
NOR2X8TS U3112 ( .A(n3638), .B(n946), .Y(n3644) );
AND2X8TS U3113 ( .A(n1499), .B(n2310), .Y(n1230) );
INVX8TS U3114 ( .A(n1239), .Y(n1820) );
XNOR2X4TS U3115 ( .A(n3451), .B(n3452), .Y(n1087) );
AOI21X4TS U3116 ( .A0(n4075), .A1(n2373), .B0(n2372), .Y(n2374) );
AOI21X4TS U3117 ( .A0(n2999), .A1(n2377), .B0(n2376), .Y(n2378) );
AOI21X2TS U3118 ( .A0(n2379), .A1(n2380), .B0(n2353), .Y(n2360) );
ADDFHX4TS U3119 ( .A(n1608), .B(n1607), .CI(n1606), .CO(n1659), .S(n1603) );
BUFX6TS U3120 ( .A(n1629), .Y(n1052) );
OAI21X4TS U3121 ( .A0(n2735), .A1(n1187), .B0(n2734), .Y(n1186) );
XNOR2X4TS U3122 ( .A(n1054), .B(n969), .Y(n3470) );
XNOR2X4TS U3123 ( .A(n1055), .B(n3416), .Y(n3473) );
XNOR2X4TS U3124 ( .A(n3417), .B(n3415), .Y(n1055) );
OAI21X2TS U3125 ( .A0(n3701), .A1(n3702), .B0(n3700), .Y(n1366) );
ADDFHX4TS U3126 ( .A(n2626), .B(n2624), .CI(n2625), .CO(n2684), .S(n2652) );
INVX6TS U3127 ( .A(n2841), .Y(n2888) );
ADDFHX4TS U3128 ( .A(n2952), .B(n2951), .CI(n2950), .CO(n2957), .S(n2959) );
ADDFHX4TS U3129 ( .A(n1720), .B(n1719), .CI(n1718), .CO(n2580), .S(n1717) );
OAI22X2TS U3130 ( .A0(n1806), .A1(n1833), .B0(n881), .B1(n840), .Y(n1807) );
ADDFHX4TS U3131 ( .A(n3512), .B(n3511), .CI(n3510), .CO(n3611), .S(n3619) );
AOI21X2TS U3132 ( .A0(n3390), .A1(n2303), .B0(n2302), .Y(n2308) );
XNOR2X2TS U3133 ( .A(n2839), .B(Sgf_operation_EVEN1_result_A_adder_3_), .Y(
n1763) );
OAI22X4TS U3134 ( .A0(n871), .A1(n3251), .B0(n416), .B1(n3292), .Y(n3191) );
ADDFHX4TS U3135 ( .A(n1560), .B(n2592), .CI(n1561), .CO(n1585), .S(n1572) );
XOR2X4TS U3136 ( .A(n1633), .B(n1634), .Y(n1079) );
NAND3X6TS U3137 ( .A(n1204), .B(n1231), .C(n1202), .Y(n1063) );
INVX2TS U3138 ( .A(n2847), .Y(n2867) );
ADDFHX2TS U3139 ( .A(n3285), .B(n3284), .CI(n3283), .CO(n3308), .S(n3297) );
XNOR2X4TS U3140 ( .A(n1064), .B(n1284), .Y(Sgf_operation_EVEN1_Q_left[19])
);
OR2X2TS U3141 ( .A(n3441), .B(n3440), .Y(n3805) );
BUFX12TS U3142 ( .A(n1492), .Y(n1066) );
INVX2TS U3143 ( .A(n3418), .Y(n3420) );
NOR2X6TS U3144 ( .A(n2617), .B(n3596), .Y(n2442) );
INVX6TS U3145 ( .A(n2638), .Y(n2665) );
NOR2X6TS U3146 ( .A(DP_OP_154J6_123_2038_n714), .B(n706), .Y(n1689) );
AOI21X4TS U3147 ( .A0(n3739), .A1(n2788), .B0(n2787), .Y(n1341) );
NAND2X8TS U3148 ( .A(n2768), .B(n1068), .Y(n3739) );
INVX2TS U3149 ( .A(n2356), .Y(n2357) );
NAND2X6TS U3150 ( .A(n1418), .B(n1417), .Y(n1981) );
ADDFHX4TS U3151 ( .A(n2010), .B(n1964), .CI(n2012), .CO(n1984), .S(n1985) );
NOR2X8TS U3152 ( .A(n800), .B(DP_OP_154J6_123_2038_n636), .Y(n1393) );
NAND3X6TS U3153 ( .A(n1431), .B(n1269), .C(n1267), .Y(n1266) );
INVX4TS U3154 ( .A(n3716), .Y(n2641) );
OAI21X4TS U3155 ( .A0(n3815), .A1(n3816), .B0(n3814), .Y(n1070) );
OAI21X2TS U3156 ( .A0(n3817), .A1(n3818), .B0(n1072), .Y(n1071) );
XNOR2X4TS U3157 ( .A(n1073), .B(n1072), .Y(DP_OP_156J6_125_3370_n230) );
ADDFHX2TS U3158 ( .A(n3539), .B(n3538), .CI(n3537), .CO(n3549), .S(n3631) );
NOR2X2TS U3159 ( .A(n699), .B(n4491), .Y(n1484) );
XOR2X4TS U3160 ( .A(n3249), .B(n3248), .Y(n1272) );
OAI22X2TS U3161 ( .A0(n872), .A1(n3293), .B0(n416), .B1(n3309), .Y(n3260) );
OAI22X4TS U3162 ( .A0(n2480), .A1(n435), .B0(n2506), .B1(n2520), .Y(n2500)
);
OAI21X4TS U3163 ( .A0(n2469), .A1(n2468), .B0(n2467), .Y(n2196) );
OAI21X4TS U3164 ( .A0(n2105), .A1(n2104), .B0(n2103), .Y(n2106) );
OAI22X4TS U3165 ( .A0(n1031), .A1(n2627), .B0(n2737), .B1(n2677), .Y(n2622)
);
ADDFHX4TS U3166 ( .A(n1648), .B(n1647), .CI(n1646), .CO(n1674), .S(n1627) );
INVX2TS U3167 ( .A(n2731), .Y(n3658) );
OAI21X4TS U3168 ( .A0(n1126), .A1(n3210), .B0(n3209), .Y(n1191) );
NOR2X8TS U3169 ( .A(n3061), .B(n3070), .Y(n3062) );
OAI22X2TS U3170 ( .A0(n872), .A1(n1989), .B0(n416), .B1(n1987), .Y(n1972) );
XOR2X4TS U3171 ( .A(n1079), .B(n1635), .Y(n1637) );
OAI22X4TS U3172 ( .A0(n1814), .A1(n1794), .B0(n1764), .B1(n1354), .Y(n1799)
);
XOR2X4TS U3173 ( .A(n2021), .B(n1082), .Y(n1955) );
OAI22X2TS U3174 ( .A0(n2737), .A1(n2627), .B0(n876), .B1(n2677), .Y(n2574)
);
NAND4X2TS U3175 ( .A(n3050), .B(n3049), .C(n3048), .D(n3047), .Y(n3054) );
AO21X4TS U3176 ( .A0(n3011), .A1(n3010), .B0(n3009), .Y(n3016) );
INVX2TS U3177 ( .A(n1710), .Y(n1600) );
OR2X8TS U3178 ( .A(n1625), .B(n1624), .Y(n2132) );
NAND2X8TS U3179 ( .A(n4213), .B(n4093), .Y(n4289) );
ADDFHX2TS U3180 ( .A(n3425), .B(n3424), .CI(n3423), .CO(n3446), .S(n3440) );
XOR2X4TS U3181 ( .A(n1083), .B(n1745), .Y(n2560) );
XOR2X4TS U3182 ( .A(n1746), .B(n2577), .Y(n1083) );
INVX2TS U3183 ( .A(Sgf_operation_EVEN1_Q_left[2]), .Y(n3129) );
INVX2TS U3184 ( .A(n3103), .Y(n3105) );
AOI21X4TS U3185 ( .A0(n3739), .A1(n3734), .B0(n3737), .Y(n3087) );
NOR2X4TS U3186 ( .A(n3088), .B(n623), .Y(n4144) );
OAI21X4TS U3187 ( .A0(n877), .A1(n4161), .B0(n4160), .Y(n4163) );
MXI2X4TS U3188 ( .A(n4208), .B(Add_result[23]), .S0(FSM_selector_C), .Y(
n4197) );
MX2X6TS U3189 ( .A(n3601), .B(n4907), .S0(n667), .Y(n269) );
BUFX12TS U3190 ( .A(n1815), .Y(n1085) );
INVX2TS U3191 ( .A(n2868), .Y(n2239) );
XNOR2X4TS U3192 ( .A(n1087), .B(n3453), .Y(n3463) );
OAI22X2TS U3193 ( .A0(n2251), .A1(n922), .B0(n2260), .B1(n2912), .Y(n2276)
);
XNOR2X4TS U3194 ( .A(n1630), .B(n1182), .Y(n1646) );
ADDFHX2TS U3195 ( .A(n3265), .B(n3264), .CI(n3263), .CO(n3283), .S(n3245) );
OAI21X4TS U3196 ( .A0(n1089), .A1(n2747), .B0(n1088), .Y(n1722) );
NOR2X4TS U3197 ( .A(n1667), .B(n1668), .Y(n1089) );
XOR2X4TS U3198 ( .A(n1090), .B(n2747), .Y(n1695) );
XOR2X4TS U3199 ( .A(n1667), .B(n1091), .Y(n1090) );
NOR2BX2TS U3200 ( .AN(n2173), .B(n3573), .Y(n2911) );
NOR2X1TS U3201 ( .A(n3724), .B(n3725), .Y(n3981) );
INVX2TS U3202 ( .A(n4296), .Y(n3407) );
OAI2BB1X4TS U3203 ( .A0N(n1150), .A1N(n1912), .B0(n1148), .Y(n1923) );
NAND2X8TS U3204 ( .A(n1427), .B(n1092), .Y(n1234) );
XNOR2X4TS U3205 ( .A(n1093), .B(n1731), .Y(n1748) );
XNOR2X4TS U3206 ( .A(n1732), .B(n1733), .Y(n1093) );
XOR2X4TS U3207 ( .A(n1094), .B(n3185), .Y(n3254) );
XNOR2X4TS U3208 ( .A(n3234), .B(n3182), .Y(n1094) );
BUFX6TS U3209 ( .A(DP_OP_155J6_124_2038_n640), .Y(n1096) );
NAND2X8TS U3210 ( .A(n1474), .B(n1219), .Y(n1439) );
NAND3X8TS U3211 ( .A(n1287), .B(n3881), .C(n3892), .Y(n1314) );
NAND2X8TS U3212 ( .A(n1128), .B(n720), .Y(n1287) );
NAND2X8TS U3213 ( .A(n3810), .B(n3809), .Y(n1229) );
XNOR2X4TS U3214 ( .A(n3389), .B(n3390), .Y(n3466) );
CLKXOR2X2TS U3215 ( .A(n2205), .B(n2204), .Y(n2206) );
INVX2TS U3216 ( .A(Sgf_operation_EVEN1_Q_left[3]), .Y(n3406) );
XOR2X4TS U3217 ( .A(n3975), .B(n2755), .Y(DP_OP_156J6_125_3370_n296) );
OR2X4TS U3218 ( .A(n1576), .B(n1575), .Y(n3100) );
ADDFHX4TS U3219 ( .A(n745), .B(n1801), .CI(n1800), .CO(n2923), .S(n2885) );
OAI21X4TS U3220 ( .A0(n2945), .A1(n2946), .B0(n2944), .Y(n1100) );
OAI21X4TS U3221 ( .A0(n2154), .A1(n2153), .B0(n2152), .Y(n2156) );
INVX2TS U3222 ( .A(n4311), .Y(n3425) );
NAND2X8TS U3223 ( .A(n1384), .B(n3369), .Y(n3360) );
AOI21X4TS U3224 ( .A0(n3484), .A1(n3480), .B0(n3436), .Y(n3437) );
INVX2TS U3225 ( .A(n3395), .Y(n3397) );
INVX8TS U3226 ( .A(n1457), .Y(n1246) );
INVX2TS U3227 ( .A(n2072), .Y(n1991) );
XOR2X4TS U3228 ( .A(n1297), .B(n1724), .Y(n1733) );
ADDFHX2TS U3229 ( .A(n448), .B(n3500), .CI(n3499), .CO(n3508), .S(n3504) );
CLKINVX12TS U3230 ( .A(n1240), .Y(n1355) );
OAI22X4TS U3231 ( .A0(n1761), .A1(n1354), .B0(n1814), .B1(n1764), .Y(n1767)
);
NAND2X4TS U3232 ( .A(n1468), .B(n1105), .Y(n1114) );
OAI22X4TS U3233 ( .A0(n1107), .A1(n842), .B0(n3520), .B1(n2921), .Y(n2967)
);
XNOR2X4TS U3234 ( .A(n1362), .B(n2976), .Y(n1107) );
NAND2X8TS U3235 ( .A(n1110), .B(n3879), .Y(n1361) );
INVX8TS U3236 ( .A(n1121), .Y(n1111) );
NAND3X8TS U3237 ( .A(n3171), .B(n1440), .C(n1468), .Y(n1121) );
NAND4X8TS U3238 ( .A(n1121), .B(n1114), .C(n1113), .D(n1119), .Y(n1116) );
XOR2X4TS U3239 ( .A(n1125), .B(n1925), .Y(n1957) );
XOR2X4TS U3240 ( .A(n3224), .B(n2024), .Y(n1125) );
NAND2BX4TS U3241 ( .AN(DP_OP_153J6_122_5442_n827), .B(n1353), .Y(n2161) );
AOI21X4TS U3242 ( .A0(n2470), .A1(n2471), .B0(n2196), .Y(n1130) );
AOI21X4TS U3243 ( .A0(n2182), .A1(n2471), .B0(n2181), .Y(n1131) );
XOR2X4TS U3244 ( .A(n1133), .B(n828), .Y(n1132) );
XOR2X4TS U3245 ( .A(n3623), .B(n3624), .Y(n1133) );
NAND2X4TS U3246 ( .A(n2197), .B(n1134), .Y(n2195) );
OAI21X4TS U3247 ( .A0(n909), .A1(n1371), .B0(n1370), .Y(n1135) );
OAI2BB1X4TS U3248 ( .A0N(n1138), .A1N(n1774), .B0(n1137), .Y(n2969) );
OAI21X4TS U3249 ( .A0(n1138), .A1(n1774), .B0(n1773), .Y(n1137) );
XOR2X4TS U3250 ( .A(n1774), .B(n1140), .Y(n1139) );
AOI2BB2X4TS U3251 ( .B0(n1141), .B1(n1832), .A0N(n1763), .A1N(n1833), .Y(
n1140) );
NAND2X4TS U3252 ( .A(n1146), .B(n3764), .Y(DP_OP_156J6_125_3370_n111) );
NAND2X4TS U3253 ( .A(n1147), .B(n3475), .Y(n1146) );
INVX2TS U3254 ( .A(n3765), .Y(n1147) );
XNOR2X4TS U3255 ( .A(n3476), .B(n3475), .Y(Sgf_operation_EVEN1_S_B[10]) );
OAI21X4TS U3256 ( .A0(n1912), .A1(n1150), .B0(n1149), .Y(n1148) );
XOR2X4TS U3257 ( .A(n2026), .B(n3227), .Y(n1151) );
OAI2BB1X4TS U3258 ( .A0N(n3097), .A1N(n1154), .B0(n3096), .Y(add_x_19_n302)
);
OR3X6TS U3259 ( .A(n1518), .B(n1164), .C(n1157), .Y(n1159) );
AOI21X4TS U3260 ( .A0(n3366), .A1(n1518), .B0(n1157), .Y(n1161) );
XOR2X4TS U3261 ( .A(n3363), .B(n1162), .Y(Sgf_operation_EVEN1_Q_left[5]) );
NOR2X8TS U3262 ( .A(n1690), .B(n1043), .Y(n3361) );
NAND2X8TS U3263 ( .A(n1169), .B(n3329), .Y(n1168) );
NAND2X6TS U3264 ( .A(n3304), .B(n1399), .Y(n1169) );
NOR2X8TS U3265 ( .A(n587), .B(n2667), .Y(n1643) );
OAI22X4TS U3266 ( .A0(n587), .A1(n2677), .B0(n868), .B1(n2627), .Y(n1634) );
OAI22X4TS U3267 ( .A0(n1171), .A1(n2733), .B0(n869), .B1(n2667), .Y(n1668)
);
XOR2X4TS U3268 ( .A(n1172), .B(n1702), .Y(n1175) );
NAND2X8TS U3269 ( .A(n1176), .B(n1184), .Y(n1174) );
XNOR2X4TS U3270 ( .A(n1179), .B(n2596), .Y(Sgf_operation_EVEN1_Q_left[12])
);
NAND2X8TS U3271 ( .A(n1177), .B(n1183), .Y(n2122) );
NOR2X8TS U3272 ( .A(n424), .B(n1178), .Y(n1177) );
XOR2X4TS U3273 ( .A(n1754), .B(n2589), .Y(n1180) );
NAND2BX4TS U3274 ( .AN(n1701), .B(n1699), .Y(n1654) );
NOR2X8TS U3275 ( .A(n1190), .B(n3211), .Y(n1189) );
NOR2X8TS U3276 ( .A(n3748), .B(n4451), .Y(n4150) );
AOI21X4TS U3277 ( .A0(n1501), .A1(n3739), .B0(n3738), .Y(n1198) );
NAND2BX4TS U3278 ( .AN(n4135), .B(n1200), .Y(n1199) );
OAI21X4TS U3279 ( .A0(n746), .A1(n1069), .B0(n4136), .Y(n1200) );
XNOR2X4TS U3280 ( .A(n4572), .B(n4573), .Y(n2773) );
INVX12TS U3281 ( .A(n1206), .Y(n1219) );
AND2X8TS U3282 ( .A(n1214), .B(n1213), .Y(n3677) );
XOR2X4TS U3283 ( .A(n1215), .B(n2745), .Y(n1214) );
XNOR2X4TS U3284 ( .A(n1218), .B(n1217), .Y(n2971) );
OAI21X4TS U3285 ( .A0(n2171), .A1(n2158), .B0(n2170), .Y(n1217) );
XOR2X4TS U3286 ( .A(n2059), .B(n1220), .Y(n1222) );
OAI21X4TS U3287 ( .A0(n1828), .A1(n1360), .B0(n1225), .Y(n2115) );
OAI21X4TS U3288 ( .A0(n1058), .A1(n3383), .B0(n3384), .Y(n2298) );
INVX12TS U3289 ( .A(n3390), .Y(n1360) );
NAND2X8TS U3290 ( .A(n732), .B(n1226), .Y(n3390) );
OAI22X4TS U3291 ( .A0(n1818), .A1(n2282), .B0(n924), .B1(n1819), .Y(n2601)
);
XOR2X4TS U3292 ( .A(n1228), .B(n2151), .Y(n1818) );
XOR2X4TS U3293 ( .A(n2503), .B(n547), .Y(n2228) );
NAND2X4TS U3294 ( .A(n1167), .B(n1238), .Y(n3766) );
NAND2X8TS U3295 ( .A(n1758), .B(n1820), .Y(n1240) );
XNOR2X4TS U3296 ( .A(n1353), .B(Sgf_operation_EVEN1_result_B_adder_2_), .Y(
n1239) );
OAI2BB1X4TS U3297 ( .A0N(n3452), .A1N(n3453), .B0(n1241), .Y(n3465) );
OAI21X4TS U3298 ( .A0(n3453), .A1(n3452), .B0(n3451), .Y(n1241) );
NAND3X4TS U3299 ( .A(n1428), .B(n738), .C(n1429), .Y(add_x_55_n29) );
NAND3X4TS U3300 ( .A(n1426), .B(n1425), .C(n3848), .Y(add_x_55_n47) );
INVX2TS U3301 ( .A(n2065), .Y(n3398) );
XOR2X4TS U3302 ( .A(n1243), .B(n1242), .Y(n3392) );
OR2X8TS U3303 ( .A(n2001), .B(n2000), .Y(n1248) );
OAI2BB1X4TS U3304 ( .A0N(n1969), .A1N(n807), .B0(n1249), .Y(n2005) );
OAI21X4TS U3305 ( .A0(n807), .A1(n1969), .B0(n1968), .Y(n1249) );
XNOR2X4TS U3306 ( .A(n1250), .B(n2296), .Y(n4227) );
NOR2X8TS U3307 ( .A(n1251), .B(n2294), .Y(n1250) );
NOR2X8TS U3308 ( .A(n2107), .B(n2106), .Y(n2294) );
OAI21X4TS U3309 ( .A0(DP_OP_155J6_124_2038_n703), .A1(
DP_OP_155J6_124_2038_n698), .B0(n1256), .Y(n1407) );
NOR2BX4TS U3310 ( .AN(n1254), .B(n2208), .Y(n2211) );
NAND2X8TS U3311 ( .A(n715), .B(n1255), .Y(n2471) );
XOR2X4TS U3312 ( .A(n1258), .B(n2710), .Y(Sgf_operation_EVEN1_Q_left[15]) );
XNOR2X4TS U3313 ( .A(n2503), .B(n2524), .Y(n2479) );
XNOR2X4TS U3314 ( .A(n1260), .B(n2198), .Y(n2503) );
OAI21X2TS U3315 ( .A0(n2218), .A1(n1261), .B0(n2207), .Y(n1260) );
XOR2X4TS U3316 ( .A(n3517), .B(n1262), .Y(n1300) );
NAND2BX4TS U3317 ( .AN(n2588), .B(n2587), .Y(n1754) );
INVX12TS U3318 ( .A(n2185), .Y(n2171) );
XOR2X4TS U3319 ( .A(n1272), .B(n3247), .Y(n3266) );
XNOR2X4TS U3320 ( .A(n1275), .B(n3239), .Y(n1273) );
AOI21X4TS U3321 ( .A0(n1399), .A1(n3330), .B0(n1278), .Y(n1370) );
OAI21X4TS U3322 ( .A0(n3328), .A1(n3329), .B0(n3327), .Y(n1278) );
NOR2X8TS U3323 ( .A(n3645), .B(n3648), .Y(n3699) );
NAND2BX4TS U3324 ( .AN(n1283), .B(n3729), .Y(n1284) );
OAI21X4TS U3325 ( .A0(DP_OP_154J6_123_2038_n378), .A1(
DP_OP_154J6_123_2038_n386), .B0(DP_OP_154J6_123_2038_n379), .Y(n1285)
);
NOR2X4TS U3326 ( .A(DP_OP_154J6_123_2038_n385), .B(DP_OP_154J6_123_2038_n378), .Y(n1286) );
NAND3X4TS U3327 ( .A(n1292), .B(n2161), .C(n2169), .Y(n1291) );
AOI21X4TS U3328 ( .A0(n2160), .A1(n2161), .B0(n1108), .Y(n1293) );
XOR2X4TS U3329 ( .A(n2597), .B(n1348), .Y(DP_OP_156J6_125_3370_n299) );
XOR2X4TS U3330 ( .A(n1298), .B(n3325), .Y(n3351) );
AND2X8TS U3331 ( .A(n3880), .B(n1302), .Y(n3773) );
NAND2X8TS U3332 ( .A(DP_OP_154J6_123_2038_n717), .B(
DP_OP_154J6_123_2038_n632), .Y(n1303) );
OAI22X4TS U3333 ( .A0(n2912), .A1(n1304), .B0(n922), .B1(n448), .Y(n2987) );
XOR2X4TS U3334 ( .A(n2541), .B(n2542), .Y(n1308) );
XOR2X4TS U3335 ( .A(n2179), .B(n1309), .Y(n2180) );
NOR2X8TS U3336 ( .A(n1289), .B(n3876), .Y(n1313) );
OAI21X4TS U3337 ( .A0(n876), .A1(n2642), .B0(n1315), .Y(n1723) );
NAND2X4TS U3338 ( .A(n1086), .B(n750), .Y(n1323) );
NAND3X8TS U3339 ( .A(n1323), .B(n1320), .C(n1318), .Y(n3553) );
OAI21X4TS U3340 ( .A0(n1326), .A1(n748), .B0(n1319), .Y(n1318) );
AOI2BB2X4TS U3341 ( .B0(n1672), .B1(n1671), .A0N(n868), .A1N(n2736), .Y(
n1331) );
XOR2X4TS U3342 ( .A(n1333), .B(n2137), .Y(n2325) );
NOR2X8TS U3343 ( .A(n445), .B(n1360), .Y(n1334) );
OAI21X4TS U3344 ( .A0(n3421), .A1(n3418), .B0(n3419), .Y(n3444) );
XNOR2X4TS U3345 ( .A(n2837), .B(n1337), .Y(n1336) );
OAI2BB1X4TS U3346 ( .A0N(n2551), .A1N(n2552), .B0(n1339), .Y(n2653) );
OAI21X4TS U3347 ( .A0(n2552), .A1(n2551), .B0(n2550), .Y(n1339) );
XNOR2X4TS U3348 ( .A(n4725), .B(n4726), .Y(n2409) );
OAI21X4TS U3349 ( .A0(n1345), .A1(n661), .B0(n4915), .Y(n4208) );
XOR2X4TS U3350 ( .A(n4163), .B(n708), .Y(n1345) );
OAI22X4TS U3351 ( .A0(n2476), .A1(n2475), .B0(n2535), .B1(n2474), .Y(n2501)
);
ADDFHX4TS U3352 ( .A(n2661), .B(n2660), .CI(n2659), .CO(n2724), .S(n2682) );
INVX2TS U3353 ( .A(n2027), .Y(n1931) );
NOR2X2TS U3354 ( .A(n3185), .B(n462), .Y(n2095) );
NAND2X2TS U3355 ( .A(n2099), .B(n2080), .Y(n2046) );
ADDFHX4TS U3356 ( .A(n3262), .B(n3261), .CI(n3260), .CO(n3284), .S(n3253) );
ADDFHX4TS U3357 ( .A(n1900), .B(n1901), .CI(n1899), .CO(n3141), .S(n1895) );
ADDFHX4TS U3358 ( .A(DP_OP_155J6_124_2038_n710), .B(
DP_OP_155J6_124_2038_n715), .CI(n1870), .CO(n1921), .S(n1914) );
ADDFHX4TS U3359 ( .A(n1676), .B(n1675), .CI(n1674), .CO(n1732), .S(n1694) );
XNOR2X4TS U3360 ( .A(n2503), .B(n2472), .Y(n2257) );
OAI22X4TS U3361 ( .A0(n2257), .A1(n2475), .B0(n2252), .B1(n2474), .Y(n2491)
);
NAND2X2TS U3362 ( .A(n1576), .B(n1575), .Y(n3099) );
NOR2BX4TS U3363 ( .AN(n2914), .B(n922), .Y(n2284) );
XNOR2X4TS U3364 ( .A(n2218), .B(n2220), .Y(n2219) );
XOR2X4TS U3365 ( .A(n1057), .B(n1352), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]) );
XNOR2X4TS U3366 ( .A(n3553), .B(n2907), .Y(n2873) );
NAND2X8TS U3367 ( .A(n3639), .B(n1077), .Y(n3879) );
INVX16TS U3368 ( .A(n1355), .Y(n1814) );
OAI2BB1X4TS U3369 ( .A0N(n1696), .A1N(n1695), .B0(n1356), .Y(n1715) );
XOR2X4TS U3370 ( .A(n1357), .B(n1694), .Y(n1649) );
XOR2X4TS U3371 ( .A(n1696), .B(n1695), .Y(n1357) );
XNOR2X4TS U3372 ( .A(n2129), .B(n2130), .Y(n3813) );
OAI2BB1X4TS U3373 ( .A0N(n1684), .A1N(n1685), .B0(n1358), .Y(n1747) );
OAI21X4TS U3374 ( .A0(n1685), .A1(n402), .B0(n1683), .Y(n1358) );
XNOR2X4TS U3375 ( .A(n1359), .B(DP_OP_153J6_122_5442_n1106), .Y(n1400) );
NAND2X4TS U3376 ( .A(n1406), .B(n3218), .Y(n3494) );
XOR2X4TS U3377 ( .A(n2837), .B(n4874), .Y(n2238) );
XNOR2X4TS U3378 ( .A(n2151), .B(n2153), .Y(n1817) );
XNOR2X4TS U3379 ( .A(n1365), .B(DP_OP_154J6_123_2038_n380), .Y(n1364) );
NAND2BX4TS U3380 ( .AN(n744), .B(n4677), .Y(n1365) );
AOI21X4TS U3381 ( .A0(n1193), .A1(n3703), .B0(n1366), .Y(n1455) );
XOR2X4TS U3382 ( .A(n1654), .B(n1700), .Y(n1666) );
NOR2X8TS U3383 ( .A(n706), .B(DP_OP_154J6_123_2038_n717), .Y(n2591) );
XNOR2X4TS U3384 ( .A(n3493), .B(n1416), .Y(n2613) );
AOI21X4TS U3385 ( .A0(n2139), .A1(n2140), .B0(n2091), .Y(n2296) );
XNOR2X4TS U3386 ( .A(n2135), .B(n2134), .Y(n3415) );
NAND2BX4TS U3387 ( .AN(n1559), .B(n1385), .Y(n3370) );
XOR2X4TS U3388 ( .A(n1081), .B(n1386), .Y(n1385) );
XNOR2X4TS U3389 ( .A(n2314), .B(n1388), .Y(n4404) );
OAI21X4TS U3390 ( .A0(n1613), .A1(n1611), .B0(n1614), .Y(n1710) );
NOR2X8TS U3391 ( .A(DP_OP_155J6_124_2038_n805), .B(n681), .Y(n1846) );
OR2X8TS U3392 ( .A(DP_OP_155J6_124_2038_n380), .B(n1398), .Y(n1390) );
NAND2BX4TS U3393 ( .AN(n3765), .B(n3764), .Y(n3476) );
NAND2X4TS U3394 ( .A(n3411), .B(n3410), .Y(n3764) );
NOR2X8TS U3395 ( .A(n3411), .B(n3410), .Y(n3765) );
XOR2X4TS U3396 ( .A(DP_OP_153J6_122_5442_n1063), .B(
DP_OP_153J6_122_5442_n1376), .Y(n1401) );
XOR2X4TS U3397 ( .A(n3878), .B(n1403), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]) );
OAI22X2TS U3398 ( .A0(n872), .A1(n3186), .B0(n3144), .B1(n795), .Y(n3143) );
AOI2BB1X4TS U3399 ( .A0N(n1411), .A1N(n1410), .B0(n2750), .Y(n3672) );
NAND2X8TS U3400 ( .A(n1415), .B(n2110), .Y(n2117) );
OAI21X4TS U3401 ( .A0(n2296), .A1(n2294), .B0(n2295), .Y(n2118) );
OAI2BB1X4TS U3402 ( .A0N(n1419), .A1N(n2605), .B0(n1985), .Y(n1418) );
XOR2X4TS U3403 ( .A(n1986), .B(n2018), .Y(n1420) );
XOR2X4TS U3404 ( .A(n2154), .B(n2153), .Y(n2147) );
XNOR2X4TS U3405 ( .A(n1423), .B(DP_OP_153J6_122_5442_n1202), .Y(n1421) );
NOR2X8TS U3406 ( .A(n3802), .B(n3801), .Y(n1430) );
INVX12TS U3407 ( .A(n3803), .Y(n1431) );
NAND2X4TS U3408 ( .A(n1487), .B(n4596), .Y(n1434) );
OAI2BB1X4TS U3409 ( .A0N(n1437), .A1N(n1436), .B0(n2901), .Y(n2924) );
INVX12TS U3410 ( .A(n844), .Y(n1436) );
XOR2X4TS U3411 ( .A(n1442), .B(n1467), .Y(n2000) );
NAND2BX4TS U3412 ( .AN(n449), .B(n1046), .Y(n1443) );
OAI21X4TS U3413 ( .A0(n1046), .A1(n1445), .B0(n1956), .Y(n1444) );
OAI2BB1X4TS U3414 ( .A0N(n3249), .A1N(n3248), .B0(n1447), .Y(n3281) );
OAI2BB1X4TS U3415 ( .A0N(n2632), .A1N(n2631), .B0(n1450), .Y(n2690) );
OAI21X4TS U3416 ( .A0(n2632), .A1(n2631), .B0(n2630), .Y(n1450) );
NOR2X8TS U3417 ( .A(n440), .B(DP_OP_154J6_123_2038_n632), .Y(n1454) );
OAI2BB1X4TS U3418 ( .A0N(n734), .A1N(n3649), .B0(n1455), .Y(n3708) );
OAI2BB1X4TS U3419 ( .A0N(n2577), .A1N(n1458), .B0(n740), .Y(n2621) );
OAI2BB1X4TS U3420 ( .A0N(n1461), .A1N(n810), .B0(n1459), .Y(n3189) );
OAI21X4TS U3421 ( .A0(n810), .A1(n1461), .B0(n1460), .Y(n1459) );
OAI2BB1X4TS U3422 ( .A0N(n1967), .A1N(n1965), .B0(n1466), .Y(n2004) );
OAI21X4TS U3423 ( .A0(n1965), .A1(n1967), .B0(n1966), .Y(n1466) );
INVX2TS U3424 ( .A(n1967), .Y(n1467) );
AOI21X4TS U3425 ( .A0(n3302), .A1(n1473), .B0(n1470), .Y(n3860) );
NOR2X4TS U3426 ( .A(n1051), .B(n463), .Y(n3323) );
OAI2BB1X4TS U3427 ( .A0N(n711), .A1N(n731), .B0(n1630), .Y(n1476) );
AOI21X2TS U3428 ( .A0(n782), .A1(n2449), .B0(n2448), .Y(n2460) );
NAND2X2TS U3429 ( .A(n3989), .B(n3998), .Y(n4001) );
ADDFHX4TS U3430 ( .A(n3448), .B(n3447), .CI(n3446), .CO(n3453), .S(n3449) );
XOR2X4TS U3431 ( .A(n4184), .B(n4183), .Y(n4185) );
XOR2X4TS U3432 ( .A(n4154), .B(n4153), .Y(n4155) );
NAND2X4TS U3433 ( .A(n4215), .B(n4214), .Y(n235) );
NOR2X8TS U3434 ( .A(n3383), .B(n3381), .Y(n2297) );
OAI21X4TS U3435 ( .A0(n3019), .A1(n2334), .B0(n2333), .Y(n2999) );
AOI21X2TS U3436 ( .A0(n3002), .A1(n2332), .B0(n2331), .Y(n2333) );
NAND2X4TS U3437 ( .A(n3819), .B(n3820), .Y(n3822) );
NAND2X2TS U3438 ( .A(n3849), .B(n3848), .Y(add_x_55_n6) );
NAND2X4TS U3439 ( .A(n4937), .B(n4199), .Y(n4980) );
NAND3X4TS U3440 ( .A(n4200), .B(n4213), .C(n4199), .Y(n4214) );
NAND2X4TS U3441 ( .A(n1109), .B(n3885), .Y(DP_OP_153J6_122_5442_n7) );
NAND2X4TS U3442 ( .A(n720), .B(n3892), .Y(n3894) );
XOR2X4TS U3443 ( .A(n4142), .B(n4449), .Y(n4143) );
NAND2X8TS U3444 ( .A(n3887), .B(n3886), .Y(n3898) );
AND2X4TS U3445 ( .A(n1453), .B(n3976), .Y(n4723) );
ADDFHX4TS U3446 ( .A(n3414), .B(n3413), .CI(n3412), .CO(n3410), .S(n3474) );
ADDFHX2TS U3447 ( .A(n2724), .B(n2723), .CI(n2722), .CO(n3651), .S(n2741) );
OAI22X4TS U3448 ( .A0(n1761), .A1(n1814), .B0(n1772), .B1(n1354), .Y(n1771)
);
NOR2BX4TS U3449 ( .AN(n924), .B(n1354), .Y(n2245) );
NAND3X6TS U3450 ( .A(n4832), .B(n659), .C(n4831), .Y(n4201) );
MX2X4TS U3451 ( .A(n4226), .B(n882), .S0(n4936), .Y(n4742) );
AND2X6TS U3452 ( .A(n4225), .B(n4224), .Y(n4226) );
XOR2X4TS U3453 ( .A(n3387), .B(n3386), .Y(n3413) );
ADDFHX2TS U3454 ( .A(n3792), .B(n3791), .CI(n3790), .CO(n3797), .S(n3794) );
NOR2X1TS U3455 ( .A(n3577), .B(n845), .Y(n3790) );
ADDFHX4TS U3456 ( .A(n3082), .B(n3081), .CI(n3080), .CO(n3084), .S(n2796) );
NOR2X4TS U3457 ( .A(n2358), .B(n2357), .Y(n2382) );
NAND2X8TS U3458 ( .A(n2420), .B(n2419), .Y(n2424) );
INVX6TS U3459 ( .A(n2414), .Y(n2420) );
OAI21X2TS U3460 ( .A0(n885), .A1(n3980), .B0(n3979), .Y(n3999) );
NOR2X4TS U3461 ( .A(n2990), .B(n3618), .Y(n2825) );
ADDFHX4TS U3462 ( .A(n2509), .B(n2508), .CI(n2507), .CO(n2922), .S(n2875) );
XOR2X4TS U3463 ( .A(n3107), .B(n3106), .Y(Sgf_operation_EVEN1_Q_left[2]) );
NAND2X2TS U3464 ( .A(n3105), .B(n3104), .Y(n3107) );
OAI21X4TS U3465 ( .A0(n1081), .A1(n1612), .B0(n1611), .Y(n1617) );
OAI21X4TS U3466 ( .A0(n3930), .A1(n3927), .B0(n3928), .Y(n3866) );
AOI21X4TS U3467 ( .A0(n3864), .A1(n3863), .B0(n2494), .Y(n3930) );
NOR2X4TS U3468 ( .A(n2496), .B(n2495), .Y(n3927) );
NAND3X2TS U3469 ( .A(n4112), .B(n4111), .C(n4110), .Y(n208) );
ADDFHX4TS U3470 ( .A(n2486), .B(n2485), .CI(n2484), .CO(n2880), .S(n2847) );
OAI22X2TS U3471 ( .A0(n2479), .A1(n2543), .B0(n2478), .B1(n2544), .Y(n2486)
);
XNOR2X4TS U3472 ( .A(n3576), .B(n3575), .Y(n3578) );
XNOR2X4TS U3473 ( .A(n3786), .B(n2976), .Y(n3498) );
NAND2X4TS U3474 ( .A(n4127), .B(n870), .Y(n4129) );
ADDFHX4TS U3475 ( .A(n1628), .B(n1626), .CI(n1627), .CO(n1685), .S(n1579) );
XNOR2X4TS U3476 ( .A(n3728), .B(n3727), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left_8_) );
ADDFHX2TS U3477 ( .A(n2664), .B(n2663), .CI(n2662), .CO(n2723), .S(n2683) );
OAI21X4TS U3478 ( .A0(n3403), .A1(n3400), .B0(n3401), .Y(n2065) );
INVX6TS U3479 ( .A(n2496), .Y(n2832) );
ADDFHX4TS U3480 ( .A(n2489), .B(n2488), .CI(n2487), .CO(n2856), .S(n2496) );
OAI21X4TS U3481 ( .A0(n877), .A1(n4193), .B0(n4192), .Y(n4195) );
XNOR2X4TS U3482 ( .A(n3115), .B(n3114), .Y(n4296) );
AOI21X2TS U3483 ( .A0(n3060), .A1(n2805), .B0(n3067), .Y(n2806) );
OAI21X2TS U3484 ( .A0(n3913), .A1(n2824), .B0(n2823), .Y(n2827) );
OAI21X2TS U3485 ( .A0(n3913), .A1(n3900), .B0(n3899), .Y(n3905) );
NAND3X2TS U3486 ( .A(n4205), .B(n4204), .C(n4203), .Y(n221) );
ADDFHX2TS U3487 ( .A(n4434), .B(n4433), .CI(n4432), .CO(n2347), .S(n2338) );
AOI21X4TS U3488 ( .A0(n1069), .A1(n4175), .B0(n4174), .Y(n4176) );
AOI21X4TS U3489 ( .A0(n1069), .A1(n4147), .B0(n4146), .Y(n4148) );
AOI21X4TS U3490 ( .A0(n1069), .A1(n4180), .B0(n4179), .Y(n4181) );
AOI21X4TS U3491 ( .A0(n4191), .A1(n3752), .B0(n3751), .Y(n3753) );
AOI21X4TS U3492 ( .A0(n1069), .A1(n4190), .B0(n4189), .Y(n4192) );
AOI21X4TS U3493 ( .A0(n4191), .A1(n4159), .B0(n4158), .Y(n4160) );
AOI21X4TS U3494 ( .A0(n4191), .A1(n4127), .B0(n4126), .Y(n4128) );
ADDFHX4TS U3495 ( .A(n2580), .B(n2579), .CI(n2578), .CO(n2630), .S(n2582) );
ADDFHX4TS U3496 ( .A(n1723), .B(n1722), .CI(n1721), .CO(n2579), .S(n1749) );
AOI21X4TS U3497 ( .A0(n3360), .A1(n3358), .B0(n2131), .Y(n2135) );
OR2X8TS U3498 ( .A(n3356), .B(n3355), .Y(n4448) );
AOI21X4TS U3499 ( .A0(n634), .A1(n4443), .B0(n4444), .Y(n2343) );
INVX2TS U3500 ( .A(n2340), .Y(n2341) );
OAI22X2TS U3501 ( .A0(n1031), .A1(n1741), .B0(n2737), .B1(n2572), .Y(n1721)
);
NAND3X2TS U3502 ( .A(n4068), .B(n4067), .C(n4066), .Y(n204) );
ADDFHX4TS U3503 ( .A(n3631), .B(n3630), .CI(n3629), .CO(n3771), .S(n3768) );
ADDFHX2TS U3504 ( .A(n3530), .B(n3529), .CI(n3528), .CO(n3566), .S(n3630) );
ADDFHX4TS U3505 ( .A(n2983), .B(n2982), .CI(n2981), .CO(n3610), .S(n2993) );
ADDFHX2TS U3506 ( .A(n3506), .B(n3505), .CI(n3504), .CO(n3613), .S(n3620) );
ADDFHX4TS U3507 ( .A(n3503), .B(n3502), .CI(n3501), .CO(n3532), .S(n3615) );
XNOR2X4TS U3508 ( .A(n2203), .B(n2201), .Y(n2202) );
NOR2BX4TS U3509 ( .AN(n4661), .B(DP_OP_153J6_122_5442_n1466), .Y(n2201) );
OAI21X2TS U3510 ( .A0(n4194), .A1(n3595), .B0(n3594), .Y(n3600) );
XNOR2X2TS U3511 ( .A(n2772), .B(n4601), .Y(n2794) );
ADDFHX4TS U3512 ( .A(n2685), .B(n2684), .CI(n2683), .CO(n2719), .S(n2691) );
ADDFHX4TS U3513 ( .A(n4439), .B(n4440), .CI(n4441), .CO(n2394), .S(n2386) );
XOR2X2TS U3514 ( .A(n2337), .B(n2343), .Y(n2368) );
XNOR2X4TS U3515 ( .A(n2789), .B(n4602), .Y(n3082) );
ADDFHX4TS U3516 ( .A(n3811), .B(n3812), .CI(n3813), .CO(n3817), .S(n3586) );
OAI22X4TS U3517 ( .A0(n2532), .A1(n2544), .B0(n2543), .B1(n2545), .Y(n3544)
);
AO21X4TS U3518 ( .A0(n2544), .A1(n2543), .B0(n2545), .Y(n3545) );
NAND2X4TS U3519 ( .A(n2593), .B(n2700), .Y(n2597) );
NOR2X2TS U3520 ( .A(n655), .B(n619), .Y(n2329) );
INVX6TS U3521 ( .A(Sgf_operation_EVEN1_Q_left[14]), .Y(
DP_OP_156J6_125_3370_n298) );
ADDFHX4TS U3522 ( .A(n1829), .B(n1787), .CI(n1830), .CO(n3534), .S(n3515) );
ADDFHX4TS U3523 ( .A(n2948), .B(n2949), .CI(n2947), .CO(n2978), .S(n2958) );
NAND2X2TS U3524 ( .A(Sgf_normalized_result[8]), .B(Sgf_normalized_result[9]),
.Y(n4360) );
ADDFHX4TS U3525 ( .A(DP_OP_155J6_124_2038_n717), .B(n1871), .CI(n1489), .CO(
n1908), .S(n1920) );
OAI2BB1X4TS U3526 ( .A0N(n3041), .A1N(n2367), .B0(n2366), .Y(n4078) );
OA21X2TS U3527 ( .A0(n2365), .A1(n4028), .B0(n4036), .Y(n2366) );
OAI21X2TS U3528 ( .A0(n4002), .A1(n3983), .B0(n3982), .Y(n3987) );
INVX2TS U3529 ( .A(n3999), .Y(n3982) );
ADDFHX4TS U3530 ( .A(n1893), .B(n1895), .CI(n1894), .CO(n3163), .S(n1942) );
ADDFHX2TS U3531 ( .A(n2431), .B(n2430), .CI(n2429), .CO(n2433), .S(n2414) );
ADDFHX4TS U3532 ( .A(n3198), .B(n3197), .CI(n3196), .CO(n3247), .S(n3201) );
NAND2X4TS U3533 ( .A(n4122), .B(n4187), .Y(n4124) );
NAND2X4TS U3534 ( .A(n3974), .B(n902), .Y(n2755) );
OAI22X2TS U3535 ( .A0(n2479), .A1(n2544), .B0(n2499), .B1(n2543), .Y(n2509)
);
NAND2BX4TS U3536 ( .AN(DP_OP_155J6_124_2038_n635), .B(n4530), .Y(n1890) );
AOI21X4TS U3537 ( .A0(n4191), .A1(n4167), .B0(n4166), .Y(n4168) );
ADDFHX4TS U3538 ( .A(n2512), .B(n2511), .CI(n2510), .CO(n2932), .S(n2943) );
OAI22X2TS U3539 ( .A0(n2499), .A1(n2544), .B0(n2513), .B1(n2543), .Y(n2512)
);
ADDFHX2TS U3540 ( .A(n2518), .B(n2472), .CI(n2517), .CO(n2526), .S(n2510) );
NAND2X4TS U3541 ( .A(n4159), .B(n870), .Y(n4161) );
ADDFHX2TS U3542 ( .A(n2936), .B(n2935), .CI(n2934), .CO(n2984), .S(n2937) );
XOR2X2TS U3543 ( .A(n4611), .B(n4612), .Y(n2417) );
ADDFHX4TS U3544 ( .A(n3785), .B(n3784), .CI(n3783), .CO(n3800), .S(n3584) );
NAND2X4TS U3545 ( .A(n2339), .B(n4429), .Y(n2349) );
ADDFHX2TS U3546 ( .A(n4432), .B(n4433), .CI(n4434), .CO(n2346), .S(n2339) );
ADDFHX4TS U3547 ( .A(n1910), .B(n1909), .CI(n1908), .CO(n3156), .S(n1905) );
XOR2X4TS U3548 ( .A(n2451), .B(n4600), .Y(n2770) );
ADDFHX2TS U3549 ( .A(n2867), .B(n2866), .CI(n2865), .CO(n2961), .S(n2892) );
ADDFHX4TS U3550 ( .A(n2859), .B(n2858), .CI(n2857), .CO(n2865), .S(n2861) );
ADDFHX4TS U3551 ( .A(n1645), .B(n1643), .CI(n1644), .CO(n1676), .S(n1635) );
ADDFHX4TS U3552 ( .A(n2704), .B(n675), .CI(n1565), .CO(n1644), .S(n1584) );
XNOR2X2TS U3553 ( .A(n3116), .B(n1381), .Y(n2607) );
ADDFHX4TS U3554 ( .A(n3566), .B(n3565), .CI(n3564), .CO(n3567), .S(n3770) );
ADDFHX2TS U3555 ( .A(n3533), .B(n3532), .CI(n3531), .CO(n3565), .S(n3634) );
ADDFHX2TS U3556 ( .A(n3664), .B(n3663), .CI(n3662), .CO(n3686), .S(n3653) );
AOI21X4TS U3557 ( .A0(n3806), .A1(n3805), .B0(n3442), .Y(n3826) );
INVX2TS U3558 ( .A(n3804), .Y(n3442) );
INVX2TS U3559 ( .A(n2491), .Y(n2274) );
NAND2X2TS U3560 ( .A(n1556), .B(n1555), .Y(n1557) );
ADDFHX2TS U3561 ( .A(n4417), .B(n3079), .CI(n3078), .CO(n3740), .S(n3080) );
ADDFHX2TS U3562 ( .A(n4415), .B(n2790), .CI(n708), .CO(n3081), .S(n2793) );
OAI21X2TS U3563 ( .A0(n2304), .A1(n2299), .B0(n2305), .Y(n1826) );
ADDFHX4TS U3564 ( .A(DP_OP_154J6_123_2038_n687), .B(
DP_OP_154J6_123_2038_n682), .CI(n2732), .CO(n3992), .S(n3984) );
ADDFHX2TS U3565 ( .A(n4416), .B(n2775), .CI(n3746), .CO(n2792), .S(n2769) );
XNOR2X4TS U3566 ( .A(n2088), .B(n2087), .Y(n2089) );
OAI21X2TS U3567 ( .A0(n4081), .A1(n4080), .B0(n4079), .Y(n4086) );
ADDFHX4TS U3568 ( .A(n4424), .B(n4425), .CI(n1506), .CO(n2430), .S(n2416) );
ADDFHX4TS U3569 ( .A(n3634), .B(n3633), .CI(n3632), .CO(n3772), .S(n3767) );
ADDFHX4TS U3570 ( .A(n1972), .B(n1971), .CI(n1970), .CO(n1965), .S(n1999) );
AOI21X4TS U3571 ( .A0(n2615), .A1(n2442), .B0(n2441), .Y(n3069) );
ADDFHX2TS U3572 ( .A(n1898), .B(n1897), .CI(n1896), .CO(n3142), .S(n1893) );
OAI22X4TS U3573 ( .A0(n2257), .A1(n2474), .B0(n2256), .B1(n2475), .Y(n3870)
);
ADDFHX2TS U3574 ( .A(n3572), .B(n3571), .CI(n3570), .CO(n3785), .S(n3582) );
OAI22X2TS U3575 ( .A0(n795), .A1(n3251), .B0(n872), .B1(n3292), .Y(n3264) );
ADDFHX2TS U3576 ( .A(n1984), .B(n1983), .CI(n1982), .CO(n1975), .S(n1994) );
ADDFHX2TS U3577 ( .A(DP_OP_154J6_123_2038_n685), .B(
DP_OP_154J6_123_2038_n700), .CI(DP_OP_154J6_123_2038_n695), .CO(n2644),
.S(n2553) );
ADDFHX4TS U3578 ( .A(n3246), .B(n3244), .CI(n3245), .CO(n3282), .S(n3267) );
NAND2X2TS U3579 ( .A(n3870), .B(n3869), .Y(n3962) );
NOR2X2TS U3580 ( .A(n2491), .B(n2490), .Y(n3959) );
ADDHX4TS U3581 ( .A(n2666), .B(n2665), .CO(n2727), .S(n2659) );
NAND2X4TS U3582 ( .A(n2144), .B(n2143), .Y(n2217) );
XNOR2X4TS U3583 ( .A(n2882), .B(n2881), .Y(n2855) );
AOI21X4TS U3584 ( .A0(n3490), .A1(n3488), .B0(n3134), .Y(n3438) );
OAI21X2TS U3585 ( .A0(n3126), .A1(n3125), .B0(n3124), .Y(n3490) );
INVX2TS U3586 ( .A(n3487), .Y(n3134) );
ADDHX4TS U3587 ( .A(DP_OP_155J6_124_2038_n713), .B(n1911), .CO(n3137), .S(
n1909) );
ADDFHX2TS U3588 ( .A(n3406), .B(n3407), .CI(n3405), .CO(n3430), .S(n3122) );
NOR2X4TS U3589 ( .A(n809), .B(n4668), .Y(n1524) );
ADDFHX4TS U3590 ( .A(n2911), .B(n2910), .CI(n2909), .CO(n2945), .S(n2918) );
OA21X4TS U3591 ( .A0(n1546), .A1(n1554), .B0(n1555), .Y(n1587) );
AND2X8TS U3592 ( .A(n4499), .B(n4532), .Y(n1863) );
OAI21X4TS U3593 ( .A0(n4049), .A1(n4045), .B0(n4050), .Y(n4075) );
OAI22X2TS U3594 ( .A0(n2921), .A1(n842), .B0(n2920), .B1(n3520), .Y(n2939)
);
OAI22X2TS U3595 ( .A0(n3520), .A1(n2225), .B0(n3519), .B1(n2224), .Y(n2253)
);
OAI22X2TS U3596 ( .A0(n2879), .A1(n842), .B0(n3520), .B1(n2842), .Y(n2887)
);
OAI22X2TS U3597 ( .A0(n3520), .A1(n2224), .B0(n2842), .B1(n3519), .Y(n2836)
);
OAI22X2TS U3598 ( .A0(n3520), .A1(n447), .B0(n3519), .B1(n2232), .Y(n2248)
);
ADDHX4TS U3599 ( .A(n1642), .B(n1641), .CO(n1679), .S(n2695) );
NOR2X8TS U3600 ( .A(DP_OP_154J6_123_2038_n717), .B(DP_OP_154J6_123_2038_n719), .Y(n1642) );
ADDFHX2TS U3601 ( .A(n2535), .B(n2534), .CI(n2533), .CO(n2540), .S(n2529) );
INVX4TS U3602 ( .A(n2916), .Y(n2974) );
XNOR2X4TS U3603 ( .A(n1078), .B(n1085), .Y(n1764) );
OAI22X4TS U3604 ( .A0(n2737), .A1(n2667), .B0(n2679), .B1(n2733), .Y(n2640)
);
OAI22X2TS U3605 ( .A0(n1819), .A1(n1817), .B0(n1811), .B1(n2282), .Y(n1825)
);
XNOR2X4TS U3606 ( .A(Sgf_operation_EVEN1_result_A_adder_3_), .B(n2151), .Y(
n1811) );
ADDFHX4TS U3607 ( .A(DP_OP_154J6_123_2038_n624), .B(
DP_OP_154J6_123_2038_n616), .CI(DP_OP_154J6_123_2038_n620), .CO(n1516),
.S(n1519) );
XOR2X4TS U3608 ( .A(n4730), .B(n2791), .Y(n3755) );
ADDFHX4TS U3609 ( .A(n2687), .B(n2688), .CI(n2686), .CO(n2739), .S(n2689) );
ADDFHX4TS U3610 ( .A(n2653), .B(n2652), .CI(n2651), .CO(n2686), .S(n2655) );
ADDFHX4TS U3611 ( .A(n1599), .B(n1598), .CI(n1597), .CO(n1602), .S(n1593) );
NOR2X4TS U3612 ( .A(n4178), .B(n4186), .Y(n4180) );
ADDFHX2TS U3613 ( .A(n2562), .B(n2561), .CI(n2560), .CO(n2651), .S(n2563) );
NAND2X4TS U3614 ( .A(n2592), .B(n2591), .Y(n2707) );
NOR2X4TS U3615 ( .A(n4188), .B(n639), .Y(n4174) );
INVX2TS U3616 ( .A(n3544), .Y(n2541) );
ADDFHX4TS U3617 ( .A(n3153), .B(n3152), .CI(n3151), .CO(n3195), .S(n3161) );
XOR2X4TS U3618 ( .A(n3112), .B(n3111), .Y(n3123) );
NOR2X2TS U3619 ( .A(n550), .B(n3140), .Y(n3177) );
ADDFHX4TS U3620 ( .A(n3628), .B(n3627), .CI(n3626), .CO(n3769), .S(n3635) );
AOI21X4TS U3621 ( .A0(n2767), .A1(n2766), .B0(n2765), .Y(n2768) );
XNOR2X4TS U3622 ( .A(n2247), .B(n2246), .Y(n3128) );
INVX2TS U3623 ( .A(n2244), .Y(n2247) );
AOI2BB1X4TS U3624 ( .A0N(n2384), .A1N(n2383), .B0(n2382), .Y(n2385) );
ADDFHX4TS U3625 ( .A(n1510), .B(n1508), .CI(n1509), .CO(n1536), .S(n1514) );
OAI21X2TS U3626 ( .A0(n781), .A1(n2764), .B0(n2763), .Y(n2765) );
ADDFHX2TS U3627 ( .A(n2891), .B(n2890), .CI(n2889), .CO(n2950), .S(n2893) );
ADDHX4TS U3628 ( .A(DP_OP_154J6_123_2038_n626), .B(n1517), .CO(n1522), .S(
n1563) );
XOR2X4TS U3629 ( .A(n3404), .B(n3403), .Y(n4298) );
ADDFHX4TS U3630 ( .A(n3191), .B(n3190), .CI(n3192), .CO(n3252), .S(n3194) );
ADDFHX4TS U3631 ( .A(DP_OP_154J6_123_2038_n605), .B(n1513), .CI(n1512), .CO(
n1527), .S(n1515) );
ADDFHX4TS U3632 ( .A(DP_OP_155J6_124_2038_n617), .B(n1867), .CI(n1866), .CO(
n1887), .S(n1918) );
INVX4TS U3633 ( .A(n3232), .Y(n3176) );
ADDFHX4TS U3634 ( .A(n3588), .B(n3587), .CI(n3586), .CO(
DP_OP_156J6_125_3370_n233), .S(n3356) );
NOR2X4TS U3635 ( .A(DP_OP_155J6_124_2038_n721), .B(DP_OP_155J6_124_2038_n728), .Y(n3241) );
ADDFHX4TS U3636 ( .A(n2919), .B(n2918), .CI(n2917), .CO(n2955), .S(n2951) );
ADDFHX4TS U3637 ( .A(n1730), .B(n1729), .CI(n1728), .CO(n2567), .S(n1742) );
AOI21X4TS U3638 ( .A0(n3715), .A1(n3714), .B0(n3713), .Y(n4002) );
OAI21X4TS U3639 ( .A0(n3363), .A1(n3361), .B0(n3362), .Y(n1553) );
XNOR2X4TS U3640 ( .A(n3428), .B(n3429), .Y(n3435) );
NAND2X2TS U3641 ( .A(n3427), .B(n3426), .Y(n3429) );
XOR2X4TS U3642 ( .A(n3368), .B(n3367), .Y(Sgf_operation_EVEN1_Q_left[4]) );
XNOR2X4TS U3643 ( .A(n3553), .B(n1436), .Y(n3547) );
NAND2X2TS U3644 ( .A(n630), .B(n4183), .Y(n3733) );
ADDFHX4TS U3645 ( .A(n1916), .B(n1915), .CI(n1914), .CO(n3227), .S(n3225) );
XOR2X4TS U3646 ( .A(n3445), .B(n3456), .Y(n3450) );
XNOR2X4TS U3647 ( .A(n1664), .B(n1663), .Y(n1665) );
NOR2X4TS U3648 ( .A(n4186), .B(n650), .Y(n4190) );
NOR2X2TS U3649 ( .A(n1481), .B(n1261), .Y(n2209) );
XNOR2X4TS U3650 ( .A(n2971), .B(n3522), .Y(n2876) );
XOR2X4TS U3651 ( .A(n710), .B(n3883), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]) );
XNOR2X4TS U3652 ( .A(n3102), .B(n3101), .Y(Sgf_operation_EVEN1_Q_left[3]) );
ADDFHX4TS U3653 ( .A(n2528), .B(n2527), .CI(n2526), .CO(n3618), .S(n2933) );
ADDFHX4TS U3654 ( .A(n2521), .B(n2472), .CI(n2522), .CO(n2530), .S(n2527) );
ADDFHX4TS U3655 ( .A(n1686), .B(n1687), .CI(n1688), .CO(n1744), .S(n1677) );
OR2X8TS U3656 ( .A(FSM_selector_B_1_), .B(n3831), .Y(n3839) );
ADDFHX2TS U3657 ( .A(n2836), .B(n2835), .CI(n2834), .CO(n2891), .S(n2833) );
ADDFHX4TS U3658 ( .A(n2409), .B(n2408), .CI(n2407), .CO(n2411), .S(n2395) );
ADDFHX4TS U3659 ( .A(n4418), .B(n2394), .CI(n2393), .CO(n2407), .S(n2389) );
ADDFHX4TS U3660 ( .A(n1944), .B(n1943), .CI(n1942), .CO(n3168), .S(n2002) );
ADDFHX4TS U3661 ( .A(n1952), .B(n1951), .CI(n1950), .CO(n1943), .S(n2006) );
ADDFHX4TS U3662 ( .A(n3621), .B(n3620), .CI(n3619), .CO(n3626), .S(n3624) );
ADDFHX4TS U3663 ( .A(n2559), .B(n427), .CI(n2558), .CO(n2624), .S(n2551) );
OAI22X2TS U3664 ( .A0(n1819), .A1(n1765), .B0(n1790), .B1(n2282), .Y(n1768)
);
NOR2X4TS U3665 ( .A(n4672), .B(DP_OP_154J6_123_2038_n719), .Y(n2646) );
XNOR2X4TS U3666 ( .A(n1085), .B(Sgf_operation_EVEN1_result_A_adder_3_), .Y(
n1794) );
ADDFHX4TS U3667 ( .A(n2555), .B(n2554), .CI(n2553), .CO(n2634), .S(n2566) );
ADDHX4TS U3668 ( .A(DP_OP_154J6_123_2038_n705), .B(n2556), .CO(n2645), .S(
n2554) );
ADDFHX4TS U3669 ( .A(n1682), .B(n1681), .CI(n1680), .CO(n1736), .S(n1692) );
ADDFHX4TS U3670 ( .A(n4426), .B(n2387), .CI(n2386), .CO(n2388), .S(n2355) );
ADDHX4TS U3671 ( .A(n1531), .B(n1530), .CO(n1598), .S(n1528) );
ADDFHX4TS U3672 ( .A(n1725), .B(n1726), .CI(n1727), .CO(n2568), .S(n1743) );
ADDFHX4TS U3673 ( .A(Op_MY[9]), .B(DP_OP_153J6_122_5442_n1467), .CI(
DP_OP_153J6_122_5442_n829), .CO(n2214), .S(n2162) );
ADDFHX4TS U3674 ( .A(DP_OP_155J6_124_2038_n632), .B(n1861), .CI(n1860), .CO(
n2024), .S(n2022) );
NOR2X8TS U3675 ( .A(n2781), .B(n2760), .Y(n3060) );
XNOR2X4TS U3676 ( .A(n417), .B(n2900), .Y(n1785) );
XNOR2X4TS U3677 ( .A(n2900), .B(n1085), .Y(n1772) );
NOR2X4TS U3678 ( .A(n699), .B(n682), .Y(n3240) );
ADDFHX2TS U3679 ( .A(n3542), .B(n3541), .CI(n3540), .CO(n3563), .S(n3537) );
ADDFHX4TS U3680 ( .A(n1907), .B(n1906), .CI(n1905), .CO(n3230), .S(n3229) );
NAND2X4TS U3681 ( .A(n2090), .B(n2089), .Y(n2138) );
ADDFHX4TS U3682 ( .A(n1854), .B(n1853), .CI(n1852), .CO(n2026), .S(n2025) );
ADDHX4TS U3683 ( .A(DP_OP_155J6_124_2038_n705), .B(DP_OP_155J6_124_2038_n700), .CO(n1872), .S(n1915) );
NOR2X8TS U3684 ( .A(n2908), .B(n2923), .Y(n3457) );
NAND2X4TS U3685 ( .A(n2908), .B(n2923), .Y(n3458) );
ADDFHX4TS U3686 ( .A(n2085), .B(n2084), .CI(n2083), .CO(n3259), .S(n3182) );
NOR2X4TS U3687 ( .A(n809), .B(DP_OP_154J6_123_2038_n636), .Y(n1512) );
XNOR2X4TS U3688 ( .A(n3553), .B(n1022), .Y(n3513) );
ADDFHX4TS U3689 ( .A(n3375), .B(n3374), .CI(n3373), .CO(n3355), .S(n3411) );
NOR2X4TS U3690 ( .A(n2841), .B(n2843), .Y(n3418) );
ADDFHX4TS U3691 ( .A(n2502), .B(n2501), .CI(n2500), .CO(n2511), .S(n2507) );
ADDFHX4TS U3692 ( .A(n1921), .B(n1920), .CI(n1919), .CO(n3228), .S(n3226) );
XOR2X4TS U3693 ( .A(n3422), .B(n3421), .Y(n3441) );
NAND2X2TS U3694 ( .A(n3420), .B(n3419), .Y(n3422) );
OAI22X2TS U3695 ( .A0(n1772), .A1(n1814), .B0(n1354), .B1(n1337), .Y(n1778)
);
XNOR2X4TS U3696 ( .A(n3556), .B(n3555), .Y(n3562) );
OAI21X4TS U3697 ( .A0(n2105), .A1(n2041), .B0(n2040), .Y(n2047) );
ADDFHX4TS U3698 ( .A(n2649), .B(n2650), .CI(n2648), .CO(n2687), .S(n2632) );
OR2X4TS U3699 ( .A(n4683), .B(DP_OP_154J6_123_2038_n628), .Y(n1605) );
NAND2X4TS U3700 ( .A(n1625), .B(n1624), .Y(n2133) );
XOR2X4TS U3701 ( .A(n4130), .B(n629), .Y(n4131) );
ADDFHX4TS U3702 ( .A(n1583), .B(n1582), .CI(n1581), .CO(n1636), .S(n1590) );
ADDFHX4TS U3703 ( .A(n3681), .B(n3680), .CI(n3679), .CO(n3690), .S(n3668) );
ADDFHX4TS U3704 ( .A(n4421), .B(n4422), .CI(n2354), .CO(n2356), .S(n2348) );
MX2X6TS U3705 ( .A(n2811), .B(n4905), .S0(n667), .Y(n272) );
NAND2X4TS U3706 ( .A(n2286), .B(n2285), .Y(n2313) );
NOR2X4TS U3707 ( .A(n2922), .B(n2943), .Y(n3900) );
NOR2X4TS U3708 ( .A(DP_OP_154J6_123_2038_n716), .B(DP_OP_154J6_123_2038_n720), .Y(n1641) );
OAI21X4TS U3709 ( .A0(n1549), .A1(n3362), .B0(n1550), .Y(n1525) );
NAND2X4TS U3710 ( .A(n2290), .B(n2291), .Y(n2309) );
ADDFHX4TS U3711 ( .A(n2267), .B(n2266), .CI(n2265), .CO(n2262), .S(n2291) );
NAND2X4TS U3712 ( .A(n2943), .B(n2922), .Y(n3899) );
NOR2X4TS U3713 ( .A(n2932), .B(n2933), .Y(n3901) );
NAND2X4TS U3714 ( .A(n2839), .B(n2838), .Y(n2869) );
NOR2X8TS U3715 ( .A(n2692), .B(n2693), .Y(n3645) );
XNOR2X4TS U3716 ( .A(n2055), .B(n2054), .Y(n2074) );
ADDFHX4TS U3717 ( .A(n3195), .B(n3193), .CI(n3194), .CO(n3248), .S(n3174) );
NAND2X4TS U3718 ( .A(n2397), .B(n2396), .Y(n2402) );
OAI21X2TS U3719 ( .A0(n3860), .A1(n3238), .B0(n3237), .Y(n3243) );
OAI21X2TS U3720 ( .A0(n3860), .A1(n3345), .B0(n3344), .Y(n3348) );
OAI21X4TS U3721 ( .A0(n3103), .A1(n3106), .B0(n3104), .Y(n3101) );
NOR2X4TS U3722 ( .A(n1563), .B(n1562), .Y(n3103) );
ADDFHX4TS U3723 ( .A(n1784), .B(n1783), .CI(n1782), .CO(n3516), .S(n3497) );
ADDFHX2TS U3724 ( .A(n1790), .B(n1789), .CI(n1788), .CO(n1829), .S(n1782) );
NOR2X4TS U3725 ( .A(n3514), .B(n3527), .Y(n3914) );
ADDFHX4TS U3726 ( .A(n2531), .B(n2530), .CI(n2529), .CO(n3514), .S(n2990) );
XOR2X4TS U3727 ( .A(n3098), .B(n4224), .Y(Sgf_operation_Result_13_) );
NAND2X2TS U3728 ( .A(n1499), .B(n2309), .Y(n2311) );
AOI21X4TS U3729 ( .A0(n3428), .A1(n3427), .B0(n1402), .Y(n3421) );
ADDFHX4TS U3730 ( .A(n2681), .B(n2680), .CI(n2682), .CO(n2720), .S(n2688) );
XOR2X4TS U3731 ( .A(n4579), .B(n4578), .Y(n2335) );
ADDFHX4TS U3732 ( .A(n2980), .B(n2979), .CI(n2978), .CO(n3623), .S(n2991) );
OAI21X4TS U3733 ( .A0(n3439), .A1(n3438), .B0(n3437), .Y(n3806) );
NAND2X2TS U3734 ( .A(n3484), .B(n3481), .Y(n3439) );
ADDFHX4TS U3735 ( .A(n1793), .B(n1792), .CI(n1791), .CO(n2916), .S(n2908) );
ADDFHX4TS U3736 ( .A(n1693), .B(n1692), .CI(n1691), .CO(n1716), .S(n1684) );
ADDHX4TS U3737 ( .A(n4565), .B(n1851), .CO(n1853), .S(n2021) );
INVX4TS U3738 ( .A(n3673), .Y(n1738) );
NOR2X4TS U3739 ( .A(n2229), .B(n2167), .Y(n3108) );
XOR2X4TS U3740 ( .A(n3121), .B(n3120), .Y(n4297) );
NAND2X4TS U3741 ( .A(n3119), .B(n3118), .Y(n3121) );
NOR2X4TS U3742 ( .A(n907), .B(n1096), .Y(n2084) );
ADDFHX4TS U3743 ( .A(n3624), .B(n3623), .CI(n3622), .CO(n3639), .S(n2995) );
ADDFHX4TS U3744 ( .A(n3608), .B(n3609), .CI(n3610), .CO(n3637), .S(n3622) );
ADDFHX4TS U3745 ( .A(n2993), .B(n2992), .CI(n2991), .CO(n2994), .S(n2965) );
ADDFHX4TS U3746 ( .A(n3189), .B(n3188), .CI(n3187), .CO(n3235), .S(n3232) );
ADDFHX4TS U3747 ( .A(n1495), .B(n3184), .CI(n3183), .CO(n3239), .S(n3188) );
ADDFHX4TS U3748 ( .A(n1904), .B(n1903), .CI(n1902), .CO(n2038), .S(n2029) );
OAI21X2TS U3749 ( .A0(n2804), .A1(n3059), .B0(n3064), .Y(n2783) );
ADDFHX2TS U3750 ( .A(n2629), .B(n2628), .CI(n689), .CO(n2662), .S(n2649) );
ADDFHX4TS U3751 ( .A(n1524), .B(n1523), .CI(n1522), .CO(n1629), .S(n1576) );
NOR2X8TS U3752 ( .A(n4044), .B(n4049), .Y(n4069) );
ADDFHX4TS U3753 ( .A(n1497), .B(n1863), .CI(n1862), .CO(n3224), .S(n3205) );
ADDHX4TS U3754 ( .A(n4563), .B(n1926), .CO(n1862), .S(n3206) );
NAND2X4TS U3755 ( .A(n2412), .B(n2411), .Y(n2426) );
NOR2X2TS U3756 ( .A(n550), .B(n3256), .Y(n3287) );
NOR2X4TS U3757 ( .A(n829), .B(n1044), .Y(n3671) );
XOR2X4TS U3758 ( .A(n3399), .B(n3398), .Y(n4311) );
NAND2X2TS U3759 ( .A(n3397), .B(n3396), .Y(n3399) );
NAND2X4TS U3760 ( .A(n2457), .B(n2456), .Y(n2763) );
ADDFHX2TS U3761 ( .A(n2771), .B(n2770), .CI(n2769), .CO(n2776), .S(n2457) );
NOR2X4TS U3762 ( .A(n2504), .B(n2545), .Y(n2518) );
XNOR2X4TS U3763 ( .A(n2971), .B(n2907), .Y(n2260) );
NOR2X4TS U3764 ( .A(n4672), .B(n706), .Y(n1729) );
XNOR2X4TS U3765 ( .A(n2176), .B(n2175), .Y(n2157) );
NAND2X4TS U3766 ( .A(n2156), .B(n2155), .Y(n2175) );
ADDFHX4TS U3767 ( .A(n2794), .B(n2793), .CI(n2792), .CO(n2795), .S(n2777) );
ADDFHX4TS U3768 ( .A(n1781), .B(n1780), .CI(n1779), .CO(n3496), .S(n2970) );
XOR2X4TS U3769 ( .A(n2283), .B(DP_OP_153J6_122_5442_n451), .Y(n2220) );
XNOR2X2TS U3770 ( .A(n2897), .B(n1085), .Y(n1761) );
NOR2X2TS U3771 ( .A(n874), .B(n2733), .Y(n3656) );
XOR2X4TS U3772 ( .A(n3090), .B(n3089), .Y(n3091) );
XNOR2X4TS U3773 ( .A(n1610), .B(n1609), .Y(n1624) );
XNOR2X4TS U3774 ( .A(n4728), .B(n4729), .Y(n3745) );
ADDFHX4TS U3775 ( .A(n2583), .B(n2582), .CI(n2581), .CO(n2584), .S(n1751) );
ADDFHX4TS U3776 ( .A(n1717), .B(n1716), .CI(n1715), .CO(n2583), .S(n1697) );
ADDFHX4TS U3777 ( .A(n2672), .B(n2671), .CI(n2670), .CO(n3985), .S(n3724) );
NOR2X6TS U3778 ( .A(n1098), .B(n1056), .Y(n1613) );
ADDFHX4TS U3779 ( .A(n2958), .B(n2957), .CI(n2956), .CO(n2964), .S(n2963) );
ADDFHX4TS U3780 ( .A(n2037), .B(n2036), .CI(n2035), .CO(n2043), .S(n2031) );
NOR2X4TS U3781 ( .A(n1052), .B(n1640), .Y(n3364) );
ADDFHX4TS U3782 ( .A(n1521), .B(n1519), .CI(n1520), .CO(n1670), .S(n1640) );
ADDHX4TS U3783 ( .A(DP_OP_155J6_124_2038_n613), .B(DP_OP_155J6_124_2038_n618), .CO(n1869), .S(n1854) );
ADDFHX4TS U3784 ( .A(n2417), .B(n2415), .CI(n2416), .CO(n2418), .S(n2412) );
ADDFHX4TS U3785 ( .A(n3569), .B(n3568), .CI(n3567), .CO(n3585), .S(n3886) );
XNOR2X4TS U3786 ( .A(n2172), .B(n1292), .Y(n2173) );
NOR2X4TS U3787 ( .A(n4188), .B(n650), .Y(n4189) );
XOR2X4TS U3788 ( .A(n2391), .B(n2390), .Y(n2437) );
OAI22X2TS U3789 ( .A0(n1814), .A1(n1813), .B0(n1812), .B1(n1354), .Y(n1824)
);
XNOR2X4TS U3790 ( .A(n1085), .B(n2152), .Y(n1812) );
NOR2X4TS U3791 ( .A(n2300), .B(n2304), .Y(n1827) );
XNOR2X4TS U3792 ( .A(n1129), .B(n2907), .Y(n2251) );
NOR2X2TS U3793 ( .A(n4034), .B(n4035), .Y(n2365) );
XNOR2X4TS U3794 ( .A(n2971), .B(n1436), .Y(n2915) );
ADDFHX4TS U3795 ( .A(n3769), .B(n3768), .CI(n3767), .CO(n3774), .S(n3642) );
ADDFHX4TS U3796 ( .A(n3651), .B(n3652), .CI(n3650), .CO(n3669), .S(n2743) );
ADDFHX4TS U3797 ( .A(n2741), .B(n2739), .CI(n2740), .CO(n2742), .S(n2693) );
NOR2X4TS U3798 ( .A(n4164), .B(n4120), .Y(n4122) );
NOR2X4TS U3799 ( .A(n4164), .B(n3750), .Y(n3752) );
NOR2X4TS U3800 ( .A(n4164), .B(n4171), .Y(n4127) );
NOR2X4TS U3801 ( .A(n4164), .B(n4157), .Y(n4159) );
XNOR2X4TS U3802 ( .A(n2971), .B(n2976), .Y(n2224) );
OAI22X4TS U3803 ( .A0(n1819), .A1(n1818), .B0(n1817), .B1(n2282), .Y(n2244)
);
ADDFHX4TS U3804 ( .A(n1809), .B(n1808), .CI(n1807), .CO(n2884), .S(n2841) );
NOR2X4TS U3805 ( .A(n2368), .B(n643), .Y(n4044) );
ADDFHX4TS U3806 ( .A(n1574), .B(n1573), .CI(n1572), .CO(n1582), .S(n1543) );
OAI22X4TS U3807 ( .A0(n2252), .A1(n2475), .B0(n2212), .B1(n2474), .Y(n2492)
);
XNOR2X4TS U3808 ( .A(n2515), .B(n2472), .Y(n2252) );
OAI22X2TS U3809 ( .A0(n2466), .A1(n2543), .B0(n2544), .B1(n2545), .Y(n2483)
);
XNOR2X4TS U3810 ( .A(n1621), .B(n1620), .Y(n1622) );
NOR2X4TS U3811 ( .A(DP_OP_154J6_123_2038_n628), .B(n4667), .Y(n1599) );
ADDFHX4TS U3812 ( .A(n2565), .B(n2564), .CI(n2563), .CO(n2654), .S(n2581) );
ADDFHX4TS U3813 ( .A(n2635), .B(n2634), .CI(n2633), .CO(n3725), .S(n3717) );
OAI21X4TS U3814 ( .A0(n2363), .A1(n3035), .B0(n3037), .Y(n3041) );
XNOR2X4TS U3815 ( .A(n2171), .B(n2190), .Y(n2127) );
CLKINVX12TS U3816 ( .A(n1959), .Y(n2012) );
OAI21X4TS U3817 ( .A0(n2213), .A1(n2233), .B0(n2235), .Y(n2216) );
OAI21X4TS U3818 ( .A0(n4470), .A1(n2327), .B0(n2328), .Y(n3027) );
OA21X4TS U3819 ( .A0(n3029), .A1(n4456), .B0(n647), .Y(n2328) );
ADDFHX4TS U3820 ( .A(n1679), .B(n1678), .CI(n1677), .CO(n3673), .S(n2747) );
AOI21X4TS U3821 ( .A0(n2244), .A1(n3127), .B0(n1821), .Y(n3111) );
INVX4TS U3822 ( .A(n2603), .Y(n3127) );
NOR2X4TS U3823 ( .A(n3750), .B(n4165), .Y(n3751) );
NOR2X4TS U3824 ( .A(n4165), .B(n4157), .Y(n4158) );
XNOR2X4TS U3825 ( .A(n2200), .B(n2191), .Y(n2189) );
ADDFHX4TS U3826 ( .A(n721), .B(n1660), .CI(n1659), .CO(n2731), .S(n2669) );
ADDFHX4TS U3827 ( .A(n3201), .B(n3200), .CI(n3199), .CO(n3202), .S(n3170) );
ADDFHX4TS U3828 ( .A(n2961), .B(n2960), .CI(n2959), .CO(n2962), .S(n2896) );
XOR2X4TS U3829 ( .A(n3219), .B(n3478), .Y(Sgf_operation_EVEN1_Q_right[15])
);
NOR2X4TS U3830 ( .A(n2024), .B(n2025), .Y(n3400) );
NOR2BX4TS U3831 ( .AN(DP_OP_153J6_122_5442_n1504), .B(n1498), .Y(n2183) );
BUFX20TS U3832 ( .A(n3071), .Y(n4191) );
ADDFHX4TS U3833 ( .A(n2455), .B(n2453), .CI(n2454), .CO(n2456), .S(n2432) );
NAND2X4TS U3834 ( .A(n2698), .B(n2699), .Y(n2716) );
XNOR2X4TS U3835 ( .A(n1076), .B(n2505), .Y(n2506) );
OAI2BB1X4TS U3836 ( .A0N(n2351), .A1N(n2350), .B0(n2349), .Y(n2379) );
NOR2X2TS U3837 ( .A(n550), .B(n1987), .Y(n3145) );
NOR2X4TS U3838 ( .A(n4454), .B(n2361), .Y(n3036) );
ADDFHX4TS U3839 ( .A(n3772), .B(n3771), .CI(n3770), .CO(n3887), .S(n3775) );
XNOR2X4TS U3840 ( .A(n1492), .B(Op_MY[9]), .Y(n2203) );
ADDFHX4TS U3841 ( .A(n2893), .B(n2894), .CI(n2892), .CO(n2895), .S(n2864) );
ADDFHX4TS U3842 ( .A(n3168), .B(n3167), .CI(n3166), .CO(n3169), .S(n1946) );
NOR2X4TS U3843 ( .A(n2020), .B(n2019), .Y(n3117) );
XNOR2X4TS U3844 ( .A(n3517), .B(n3522), .Y(n2926) );
NOR2X2TS U3845 ( .A(n4557), .B(n4514), .Y(n4556) );
NOR2X8TS U3846 ( .A(n394), .B(n802), .Y(n2599) );
ADDFHX4TS U3847 ( .A(n3157), .B(n3156), .CI(n3155), .CO(n3233), .S(n3231) );
NOR2X2TS U3848 ( .A(n875), .B(n2642), .Y(n2675) );
ADDFHX4TS U3849 ( .A(n3637), .B(n3636), .CI(n3635), .CO(n3641), .S(n3640) );
XNOR2X4TS U3850 ( .A(n2515), .B(n2505), .Y(n2481) );
XNOR2X4TS U3851 ( .A(n1195), .B(n2524), .Y(n2532) );
ADDFHX4TS U3852 ( .A(n1595), .B(n1594), .CI(n1593), .CO(n2647), .S(n2557) );
NAND2X2TS U3853 ( .A(n2154), .B(n2153), .Y(n2155) );
XNOR2X4TS U3854 ( .A(n1085), .B(n2153), .Y(n1804) );
NOR2X4TS U3855 ( .A(n2190), .B(DP_OP_153J6_122_5442_n778), .Y(n2192) );
XNOR2X4TS U3856 ( .A(DP_OP_153J6_122_5442_n778), .B(n4660), .Y(n2190) );
NAND2X4TS U3857 ( .A(n3829), .B(n3828), .Y(add_x_19_n300) );
OAI21X4TS U3858 ( .A0(n2427), .A1(n2426), .B0(n2425), .Y(n2766) );
OR2X4TS U3859 ( .A(n2420), .B(n2419), .Y(n2425) );
XNOR2X4TS U3860 ( .A(n1592), .B(n1652), .Y(n1625) );
ADDFHX4TS U3861 ( .A(n3308), .B(n3307), .CI(n3306), .CO(n3318), .S(n3300) );
ADDFHX4TS U3862 ( .A(n2007), .B(n2006), .CI(n2005), .CO(n2008), .S(n2001) );
XOR2X4TS U3863 ( .A(n2360), .B(n2359), .Y(n2371) );
CMPR22X2TS U3864 ( .A(n3659), .B(n3995), .CO(n3685), .S(n3657) );
NOR2X8TS U3865 ( .A(n3301), .B(n3300), .Y(n3326) );
XOR2X4TS U3866 ( .A(n4580), .B(n4581), .Y(n2450) );
OAI21X4TS U3867 ( .A0(n2048), .A1(n2057), .B0(n2049), .Y(n2102) );
ADDHX4TS U3868 ( .A(DP_OP_154J6_123_2038_n791), .B(Op_MX[18]), .CO(n1541),
.S(n1540) );
XNOR2X4TS U3869 ( .A(n1078), .B(n2151), .Y(n1803) );
OAI22X4TS U3870 ( .A0(n1814), .A1(n1337), .B0(n1354), .B1(n1816), .Y(n2167)
);
ADDFHX4TS U3871 ( .A(n1749), .B(n1748), .CI(n1747), .CO(n1750), .S(n1698) );
XOR2X4TS U3872 ( .A(n2145), .B(n2146), .Y(n2165) );
NAND2X2TS U3873 ( .A(n2222), .B(n2217), .Y(n2145) );
XNOR2X4TS U3874 ( .A(n1059), .B(n2151), .Y(n1795) );
NAND2X4TS U3875 ( .A(n2461), .B(n622), .Y(n2779) );
NAND2X2TS U3876 ( .A(n2370), .B(n638), .Y(n4073) );
OAI21X4TS U3877 ( .A0(n3602), .A1(n4096), .B0(n3603), .Y(n2615) );
ADDHX4TS U3878 ( .A(n4564), .B(n1913), .CO(n1916), .S(n3204) );
NAND2X2TS U3879 ( .A(n1563), .B(n1562), .Y(n3104) );
ADDFHX4TS U3880 ( .A(DP_OP_153J6_122_5442_n1516), .B(
DP_OP_153J6_122_5442_n1503), .CI(DP_OP_153J6_122_5442_n838), .CO(n2848), .S(n2154) );
ADDHX4TS U3881 ( .A(DP_OP_155J6_124_2038_n792), .B(n698), .CO(n1857), .S(
n1849) );
BUFX12TS U3882 ( .A(n2157), .Y(n2976) );
XNOR2X4TS U3883 ( .A(n2152), .B(DP_OP_153J6_122_5442_n837), .Y(n2222) );
ADDFHX4TS U3884 ( .A(n2568), .B(n2567), .CI(n2566), .CO(n3716), .S(n3694) );
ADDFHX4TS U3885 ( .A(n1744), .B(n1743), .CI(n1742), .CO(n1745), .S(n3674) );
ADDFHX4TS U3886 ( .A(n1516), .B(n1515), .CI(n1514), .CO(n1746), .S(n1690) );
NOR2X4TS U3887 ( .A(n4071), .B(n4070), .Y(n4077) );
ADDFHX4TS U3888 ( .A(n2044), .B(n2043), .CI(n2042), .CO(n3185), .S(n3154) );
ADDFHX4TS U3889 ( .A(n2033), .B(n2032), .CI(n2031), .CO(n3138), .S(n2039) );
XNOR2X4TS U3890 ( .A(n3343), .B(n3342), .Y(n3354) );
NOR2X4TS U3891 ( .A(n4683), .B(DP_OP_154J6_123_2038_n630), .Y(n1596) );
XNOR2X4TS U3892 ( .A(n3348), .B(n3347), .Y(n3847) );
XNOR2X4TS U3893 ( .A(n1076), .B(n2472), .Y(n2473) );
ADDHX4TS U3894 ( .A(DP_OP_154J6_123_2038_n794), .B(DP_OP_154J6_123_2038_n693), .CO(n1639), .S(n1566) );
NOR2X2TS U3895 ( .A(n2152), .B(DP_OP_153J6_122_5442_n837), .Y(n2142) );
INVX12TS U3896 ( .A(n1858), .Y(n3179) );
ADDHX4TS U3897 ( .A(DP_OP_155J6_124_2038_n791), .B(DP_OP_155J6_124_2038_n785), .CO(n1859), .S(n1858) );
ADDHX4TS U3898 ( .A(n2243), .B(n2242), .CO(n2495), .S(n2493) );
OAI22X2TS U3899 ( .A0(n435), .A1(n547), .B0(n2520), .B1(n2226), .Y(n2243) );
XOR2X4TS U3900 ( .A(n2436), .B(n2435), .Y(n2443) );
XNOR2X4TS U3901 ( .A(n2472), .B(n1195), .Y(n2476) );
XNOR2X4TS U3902 ( .A(n2400), .B(n2399), .Y(n2438) );
ADDFHX4TS U3903 ( .A(n1604), .B(n1603), .CI(n1602), .CO(n2676), .S(n2638) );
ADDFHX4TS U3904 ( .A(n1536), .B(n1535), .CI(n1534), .CO(n2569), .S(n1734) );
NAND2BX4TS U3905 ( .AN(DP_OP_153J6_122_5442_n1504), .B(n1498), .Y(n2194) );
ADDFHX4TS U3906 ( .A(DP_OP_153J6_122_5442_n1517), .B(
DP_OP_153J6_122_5442_n1504), .CI(Sgf_operation_EVEN1_result_A_adder_3_), .CO(n2852), .S(n2851) );
XNOR2X4TS U3907 ( .A(n1129), .B(n1436), .Y(n2973) );
NAND2X4TS U3908 ( .A(n2162), .B(Sgf_operation_EVEN1_result_B_adder_2_), .Y(
n2235) );
ADDFHX4TS U3909 ( .A(DP_OP_153J6_122_5442_n1479), .B(
DP_OP_153J6_122_5442_n1468), .CI(n1815), .CO(n2237), .S(n2215) );
ADDHX4TS U3910 ( .A(DP_OP_154J6_123_2038_n793), .B(DP_OP_154J6_123_2038_n699), .CO(n1567), .S(n1564) );
ADDHX4TS U3911 ( .A(n1578), .B(n1577), .CO(n1630), .S(n2705) );
OR2X4TS U3912 ( .A(n2012), .B(n2011), .Y(n1477) );
INVX2TS U3913 ( .A(n348), .Y(n4501) );
OR2X2TS U3914 ( .A(n2284), .B(n971), .Y(n1496) );
OR2X8TS U3915 ( .A(n2291), .B(n2290), .Y(n1499) );
INVX2TS U3916 ( .A(n4021), .Y(n4072) );
AND2X2TS U3917 ( .A(n3734), .B(n3736), .Y(n1501) );
NAND2X8TS U3918 ( .A(n4011), .B(n4010), .Y(n1502) );
INVX4TS U3919 ( .A(DP_OP_153J6_122_5442_n1475), .Y(n4546) );
INVX2TS U3920 ( .A(Op_MY[24]), .Y(n3837) );
OR2X2TS U3921 ( .A(n2705), .B(n2704), .Y(n1503) );
INVX2TS U3922 ( .A(n3059), .Y(n2808) );
INVX2TS U3923 ( .A(n4144), .Y(n4147) );
XNOR2X4TS U3924 ( .A(n4734), .B(n4735), .Y(n1506) );
INVX2TS U3925 ( .A(n3755), .Y(n3078) );
INVX2TS U3926 ( .A(n2095), .Y(n2080) );
NOR2X1TS U3927 ( .A(n2095), .B(n2098), .Y(n2101) );
INVX2TS U3928 ( .A(n3272), .Y(n3274) );
ADDFHX2TS U3929 ( .A(n2975), .B(n616), .CI(n2974), .CO(n3512), .S(n2966) );
INVX2TS U3930 ( .A(n3709), .Y(n3675) );
INVX2TS U3931 ( .A(n4150), .Y(n4152) );
INVX2TS U3932 ( .A(n3007), .Y(n3011) );
INVX2TS U3933 ( .A(n2781), .Y(n2462) );
INVX2TS U3934 ( .A(n3901), .Y(n3903) );
INVX2TS U3935 ( .A(n3966), .Y(n3968) );
OAI21X1TS U3936 ( .A0(n3921), .A1(n3920), .B0(n3919), .Y(n3926) );
INVX2TS U3937 ( .A(n226), .Y(n4008) );
INVX2TS U3938 ( .A(n3948), .Y(n3943) );
OAI21X2TS U3939 ( .A0(n4002), .A1(n3978), .B0(n3980), .Y(n3728) );
NAND2X1TS U3940 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n4004) );
INVX2TS U3941 ( .A(n349), .Y(n4514) );
INVX4TS U3942 ( .A(n356), .Y(n4705) );
BUFX3TS U3943 ( .A(n866), .Y(n4950) );
NOR2X4TS U3948 ( .A(DP_OP_154J6_123_2038_n631), .B(n1042), .Y(n2598) );
AOI21X4TS U3949 ( .A0(n1526), .A1(n1548), .B0(n1525), .Y(n1713) );
INVX2TS U3950 ( .A(n1612), .Y(n1537) );
NAND2X4TS U3951 ( .A(n1537), .B(n1611), .Y(n1538) );
INVX2TS U3952 ( .A(n1558), .Y(n1546) );
NOR2X4TS U3953 ( .A(n454), .B(n438), .Y(n1755) );
XNOR2X4TS U3954 ( .A(n1553), .B(n1552), .Y(n2757) );
NAND2X4TS U3955 ( .A(n2757), .B(n2756), .Y(n2758) );
INVX4TS U3956 ( .A(n2695), .Y(n1645) );
OAI22X1TS U3957 ( .A0(n2571), .A1(n1741), .B0(n869), .B1(n2572), .Y(n1581)
);
INVX4TS U3958 ( .A(n1575), .Y(n1632) );
INVX2TS U3959 ( .A(n1618), .Y(n1591) );
AO21X4TS U3960 ( .A0(n1619), .A1(n1620), .B0(n1591), .Y(n1652) );
INVX2TS U3961 ( .A(n1613), .Y(n1615) );
XNOR2X4TS U3962 ( .A(n1617), .B(n1616), .Y(n1623) );
ADDFHX4TS U3963 ( .A(n1638), .B(n1637), .CI(n1636), .CO(n1683), .S(n1580) );
AOI21X4TS U3964 ( .A0(n1653), .A1(n1652), .B0(n1651), .Y(n1700) );
NAND2X1TS U3965 ( .A(n1704), .B(n1656), .Y(n1658) );
AOI21X1TS U3966 ( .A0(n1710), .A1(n1656), .B0(n1655), .Y(n1657) );
OAI21X2TS U3967 ( .A0(n687), .A1(n1658), .B0(n1657), .Y(n1664) );
INVX2TS U3968 ( .A(n1706), .Y(n1662) );
OAI22X1TS U3969 ( .A0(n2679), .A1(n2627), .B0(n2571), .B1(n2677), .Y(n1718)
);
AOI21X1TS U3970 ( .A0(n1709), .A1(n1710), .B0(n1708), .Y(n1711) );
XNOR2X4TS U3971 ( .A(n2900), .B(n2151), .Y(n1765) );
CLKINVX6TS U3972 ( .A(DP_OP_153J6_122_5442_n1183), .Y(n1756) );
XNOR2X4TS U3973 ( .A(DP_OP_153J6_122_5442_n1385), .B(n1757), .Y(n2897) );
XOR2X4TS U3974 ( .A(Sgf_operation_EVEN1_result_B_adder_2_), .B(n1815), .Y(
n1758) );
CLKINVX6TS U3975 ( .A(n4585), .Y(n1762) );
OAI22X1TS U3976 ( .A0(n1833), .A1(n1785), .B0(n1831), .B1(n839), .Y(n1830)
);
INVX2TS U3977 ( .A(n1787), .Y(n1837) );
NAND2X1TS U3978 ( .A(n2297), .B(n1827), .Y(n1828) );
XNOR2X1TS U3979 ( .A(n837), .B(n924), .Y(n1806) );
NOR2X2TS U3980 ( .A(n1842), .B(n1841), .Y(n3575) );
NOR2X8TS U3981 ( .A(DP_OP_155J6_124_2038_n798), .B(DP_OP_155J6_124_2038_n804), .Y(n1883) );
OAI22X1TS U3982 ( .A0(n873), .A1(n3251), .B0(n397), .B1(n3292), .Y(n1896) );
INVX2TS U3983 ( .A(n1883), .Y(n1885) );
ADDFHX4TS U3984 ( .A(n1929), .B(n1928), .CI(n1927), .CO(n1934), .S(n1960) );
ADDFHX4TS U3985 ( .A(n1935), .B(n1934), .CI(n1933), .CO(n1948), .S(n1971) );
ADDFHX4TS U3986 ( .A(n1941), .B(n1939), .CI(n1940), .CO(n3148), .S(n2003) );
ADDFHX4TS U3987 ( .A(n1962), .B(n1961), .CI(n1960), .CO(n1956), .S(n1974) );
OAI22X1TS U3988 ( .A0(n873), .A1(n1989), .B0(n397), .B1(n1987), .Y(n1979) );
ADDFHX4TS U3989 ( .A(n1975), .B(n1974), .CI(n1973), .CO(n1968), .S(n1997) );
ADDFHX4TS U3990 ( .A(n1981), .B(n1980), .CI(n1979), .CO(n1973), .S(n1995) );
NOR2X2TS U3991 ( .A(n1993), .B(n1992), .Y(n2060) );
OAI21X4TS U3992 ( .A0(n2076), .A1(n2078), .B0(n2077), .Y(n2093) );
ADDFHX4TS U3993 ( .A(n2004), .B(n2003), .CI(n2002), .CO(n1945), .S(n2009) );
AND2X2TS U3994 ( .A(n1958), .B(n4523), .Y(n2606) );
OAI21X4TS U3995 ( .A0(n3117), .A1(n3120), .B0(n3118), .Y(n3114) );
AOI21X4TS U3996 ( .A0(n3113), .A1(n3114), .B0(n2023), .Y(n3403) );
NAND2X1TS U3997 ( .A(n2058), .B(n2057), .Y(n2059) );
NAND2X2TS U3998 ( .A(n2062), .B(n2061), .Y(n2064) );
NAND2X1TS U3999 ( .A(n2070), .B(n2069), .Y(n2071) );
NAND2X1TS U4000 ( .A(n2096), .B(n2080), .Y(n2082) );
NAND2X1TS U4001 ( .A(n2096), .B(n2101), .Y(n2104) );
AOI21X1TS U4002 ( .A0(n2102), .A1(n2101), .B0(n2100), .Y(n2103) );
NAND2X4TS U4003 ( .A(n724), .B(n2108), .Y(n2109) );
XNOR2X4TS U4004 ( .A(n2115), .B(n2114), .Y(n3815) );
NAND2X4TS U4005 ( .A(n2117), .B(n2116), .Y(n2119) );
XNOR2X4TS U4006 ( .A(n2118), .B(n2119), .Y(n4222) );
NOR2BX1TS U4007 ( .AN(n2477), .B(n2474), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]) );
INVX2TS U4008 ( .A(n2300), .Y(n2136) );
NAND2X2TS U4009 ( .A(n2138), .B(n2139), .Y(n2141) );
XNOR2X4TS U4010 ( .A(n2141), .B(n2140), .Y(n4250) );
XNOR2X4TS U4011 ( .A(n2147), .B(n2142), .Y(n2146) );
INVX2TS U4012 ( .A(n2167), .Y(n2231) );
NOR2BX1TS U4013 ( .AN(n2173), .B(n1101), .Y(n2834) );
NOR2BX2TS U4014 ( .AN(DP_OP_153J6_122_5442_n778), .B(n4660), .Y(n2186) );
XNOR2X4TS U4015 ( .A(DP_OP_153J6_122_5442_n1477), .B(
DP_OP_153J6_122_5442_n1466), .Y(n2191) );
OAI21X1TS U4016 ( .A0(n1481), .A1(n2207), .B0(n4656), .Y(n2208) );
OAI22X1TS U4017 ( .A0(n2228), .A1(n435), .B0(n2481), .B1(n2520), .Y(n2487)
);
XNOR2X4TS U4018 ( .A(n3517), .B(n2907), .Y(n2241) );
XNOR2X1TS U4019 ( .A(n2976), .B(n2914), .Y(n2225) );
NAND2BX1TS U4020 ( .AN(n2477), .B(n2505), .Y(n2226) );
XNOR2X1TS U4021 ( .A(n2477), .B(n2505), .Y(n2227) );
OAI22X2TS U4022 ( .A0(n2228), .A1(n2520), .B0(n435), .B1(n2227), .Y(n2242)
);
ADDFHX4TS U4023 ( .A(n2273), .B(n2272), .CI(n2271), .CO(n2265), .S(n2289) );
CMPR32X2TS U4024 ( .A(n2281), .B(n2280), .C(n2279), .CO(n2275), .S(n2285) );
AOI21X4TS U4025 ( .A0(n2312), .A1(n969), .B0(n2287), .Y(n3379) );
XOR2X4TS U4026 ( .A(n2830), .B(n2293), .Y(n3587) );
NOR2X2TS U4027 ( .A(n445), .B(n2300), .Y(n2303) );
OAI21X2TS U4028 ( .A0(n2301), .A1(n2300), .B0(n2299), .Y(n2302) );
XNOR2X1TS U4029 ( .A(n2317), .B(n2316), .Y(n3409) );
INVX2TS U4030 ( .A(n3027), .Y(n3019) );
NAND2X1TS U4031 ( .A(n3003), .B(n2332), .Y(n2334) );
OAI2BB1X1TS U4032 ( .A0N(n3021), .A1N(n624), .B0(n3020), .Y(n3002) );
NAND2X1TS U4033 ( .A(n656), .B(n2330), .Y(n3013) );
XNOR2X4TS U4034 ( .A(n4574), .B(n4575), .Y(n2452) );
NOR2X2TS U4035 ( .A(n4442), .B(n640), .Y(n2342) );
NAND2X1TS U4036 ( .A(n2336), .B(n2340), .Y(n2337) );
NAND2X1TS U4037 ( .A(n2350), .B(n2349), .Y(n2345) );
AOI2BB1X4TS U4038 ( .A0N(n2343), .A1N(n2342), .B0(n2341), .Y(n2344) );
XNOR2X4TS U4039 ( .A(n2345), .B(n2351), .Y(n2369) );
INVX2TS U4040 ( .A(n2355), .Y(n2358) );
OR2X2TS U4041 ( .A(n2384), .B(n2382), .Y(n2359) );
INVX2TS U4042 ( .A(n2401), .Y(n2392) );
AO21X4TS U4043 ( .A0(n2405), .A1(n2392), .B0(n533), .Y(n2400) );
XNOR2X4TS U4044 ( .A(n782), .B(n2410), .Y(n2439) );
AND2X2TS U4045 ( .A(n2412), .B(n2411), .Y(n2413) );
AOI21X4TS U4046 ( .A0(n782), .A1(n2423), .B0(n2413), .Y(n2422) );
XOR2X1TS U4047 ( .A(n4608), .B(n4609), .Y(n2431) );
INVX4TS U4048 ( .A(n2330), .Y(n2428) );
NAND2X1TS U4049 ( .A(n2424), .B(n2425), .Y(n2421) );
XOR2X4TS U4050 ( .A(n2422), .B(n2421), .Y(n2440) );
NOR2X4TS U4051 ( .A(n2443), .B(n648), .Y(n2760) );
NOR2X1TS U4052 ( .A(n783), .B(n2761), .Y(n2449) );
MX2X6TS U4053 ( .A(n2465), .B(n4906), .S0(n667), .Y(n271) );
NAND2BX1TS U4054 ( .AN(n2477), .B(n2524), .Y(n2466) );
XNOR2X1TS U4055 ( .A(n2477), .B(n2524), .Y(n2478) );
CMPR22X2TS U4056 ( .A(n2483), .B(n2482), .CO(n2508), .S(n2484) );
NOR2X1TS U4057 ( .A(n3922), .B(n3920), .Y(n2498) );
OR2X1TS U4058 ( .A(n2493), .B(n2492), .Y(n3863) );
NAND2X1TS U4059 ( .A(n2493), .B(n2492), .Y(n3862) );
AOI21X4TS U4060 ( .A0(n2498), .A1(n3866), .B0(n2497), .Y(n3913) );
NOR2X2TS U4061 ( .A(n2523), .B(n2545), .Y(n2534) );
AOI21X1TS U4062 ( .A0(n3910), .A1(n2537), .B0(n2536), .Y(n2538) );
OAI21X2TS U4063 ( .A0(n3913), .A1(n2539), .B0(n2538), .Y(n2549) );
OR2X2TS U4064 ( .A(n3525), .B(n3521), .Y(n2547) );
NAND2X1TS U4065 ( .A(n3525), .B(n3521), .Y(n2546) );
AO22X1TS U4066 ( .A0(n4721), .A1(n2636), .B0(n4684), .B1(n2570), .Y(n2629)
);
AFHCONX2TS U4067 ( .A(n2612), .B(n1544), .CI(n2610), .CON(n3125), .S(n4223)
);
ADDFHX4TS U4068 ( .A(n2691), .B(n2690), .CI(n2689), .CO(n2692), .S(n2658) );
INVX4TS U4069 ( .A(n3645), .Y(n2694) );
OR2X2TS U4070 ( .A(n2696), .B(n1035), .Y(n2752) );
XNOR2X2TS U4071 ( .A(n2697), .B(n2751), .Y(n2698) );
MX2X6TS U4072 ( .A(n2715), .B(n4908), .S0(n667), .Y(n270) );
ADDFHX4TS U4073 ( .A(n2721), .B(n2720), .CI(n2719), .CO(n3652), .S(n2740) );
INVX2TS U4074 ( .A(n3648), .Y(n2744) );
INVX2TS U4075 ( .A(n3671), .Y(n2748) );
NAND2X1TS U4076 ( .A(n2748), .B(n3670), .Y(n2753) );
XOR2X1TS U4077 ( .A(n2753), .B(n3672), .Y(n2754) );
AND2X4TS U4078 ( .A(n2759), .B(n2758), .Y(Sgf_operation_EVEN1_Q_left[6]) );
INVX2TS U4079 ( .A(n3060), .Y(n2802) );
NAND2BX1TS U4080 ( .AN(n3065), .B(n3063), .Y(n2799) );
XNOR2X4TS U4081 ( .A(n2800), .B(n2799), .Y(n2801) );
MX2X6TS U4082 ( .A(n2801), .B(n4904), .S0(n667), .Y(n273) );
AOI21X4TS U4083 ( .A0(n4808), .A1(n4807), .B0(n4806), .Y(n2812) );
NAND2X6TS U4084 ( .A(n4982), .B(n2813), .Y(n3731) );
NOR2X8TS U4085 ( .A(n4982), .B(FS_Module_state_reg[3]), .Y(n4200) );
AOI22X1TS U4086 ( .A0(n4291), .A1(Add_result[12]), .B0(
Sgf_normalized_result[11]), .B1(n4292), .Y(n2822) );
AOI2BB2X4TS U4087 ( .B0(n4233), .B1(n273), .A0N(n859), .A1N(n4762), .Y(n2821) );
NAND3X4TS U4088 ( .A(n2822), .B(n2821), .C(n2820), .Y(n213) );
INVX2TS U4089 ( .A(n2825), .Y(n3909) );
INVX2TS U4090 ( .A(Sgf_operation_EVEN1_Q_left[15]), .Y(
DP_OP_156J6_125_3370_n297) );
XOR2X1TS U4091 ( .A(n2852), .B(n2848), .Y(n2849) );
ADDFHX4TS U4092 ( .A(n2860), .B(n2861), .CI(n2862), .CO(n2863), .S(n2263) );
INVX2TS U4093 ( .A(n2880), .Y(n2919) );
XNOR2X4TS U4094 ( .A(n3553), .B(n2976), .Y(n2921) );
NOR2BX1TS U4095 ( .AN(n2914), .B(n845), .Y(n2975) );
OAI22X1TS U4096 ( .A0(n3513), .A1(n1101), .B0(n2977), .B1(n563), .Y(n3510)
);
AOI22X1TS U4097 ( .A0(n4293), .A1(n861), .B0(Sgf_normalized_result[10]),
.B1(n4292), .Y(n2998) );
AOI2BB2X4TS U4098 ( .B0(n4233), .B1(n272), .A0N(n859), .A1N(n4763), .Y(n2997) );
INVX6TS U4099 ( .A(n2999), .Y(n4081) );
NAND2BX1TS U4100 ( .AN(n3036), .B(n3035), .Y(n3000) );
XOR2X1TS U4101 ( .A(n4081), .B(n3000), .Y(n3001) );
INVX2TS U4102 ( .A(n3004), .Y(n3010) );
NAND2X1TS U4103 ( .A(n3010), .B(n3008), .Y(n3005) );
XOR2X1TS U4104 ( .A(n3007), .B(n3005), .Y(n3006) );
INVX2TS U4105 ( .A(n3012), .Y(n3014) );
XOR2X1TS U4106 ( .A(n3016), .B(n3015), .Y(n3017) );
INVX2TS U4107 ( .A(n3018), .Y(n3025) );
OA21XLTS U4108 ( .A0(n3019), .A1(n3018), .B0(n4469), .Y(n3023) );
NAND2X1TS U4109 ( .A(n3021), .B(n3020), .Y(n3022) );
XOR2X1TS U4110 ( .A(n3023), .B(n3022), .Y(n3024) );
XOR2X1TS U4111 ( .A(n3027), .B(n3026), .Y(n3028) );
INVX2TS U4112 ( .A(n3029), .Y(n3030) );
XNOR2X1TS U4113 ( .A(n3032), .B(n3031), .Y(n3033) );
XNOR2X1TS U4114 ( .A(n653), .B(n4455), .Y(n3034) );
CLKMX2X2TS U4115 ( .A(n3034), .B(n4848), .S0(n4847), .Y(n4776) );
NAND2X1TS U4116 ( .A(n3038), .B(n3037), .Y(n3039) );
XNOR2X1TS U4117 ( .A(n718), .B(n3039), .Y(n3040) );
NAND2X1TS U4118 ( .A(n4027), .B(n4028), .Y(n3044) );
NOR4X1TS U4119 ( .A(n258), .B(n256), .C(n257), .D(n255), .Y(n3050) );
NOR4X1TS U4120 ( .A(n254), .B(n253), .C(n4776), .D(n251), .Y(n3049) );
NOR4X1TS U4121 ( .A(P_Sgf[8]), .B(n864), .C(P_Sgf[6]), .D(P_Sgf[5]), .Y(
n3052) );
NOR4X1TS U4122 ( .A(P_Sgf[4]), .B(P_Sgf[3]), .C(P_Sgf[2]), .D(P_Sgf[1]), .Y(
n3051) );
NAND2X1TS U4123 ( .A(n3052), .B(n3051), .Y(n3053) );
CLKMX2X2TS U4124 ( .A(round_mode[1]), .B(round_mode[0]), .S0(n4283), .Y(
n3055) );
NAND2X2TS U4125 ( .A(n3058), .B(n1507), .Y(n375) );
OAI21X4TS U4126 ( .A0(n3069), .A1(n3070), .B0(n3068), .Y(n3071) );
OAI21X4TS U4127 ( .A0(n877), .A1(n3073), .B0(n3072), .Y(n3090) );
XOR2X4TS U4128 ( .A(n3087), .B(n3086), .Y(n3088) );
AND2X2TS U4129 ( .A(n4147), .B(n4145), .Y(n3089) );
AOI22X1TS U4130 ( .A0(n4293), .A1(Add_result[13]), .B0(
Sgf_normalized_result[12]), .B1(n4292), .Y(n3095) );
NAND2X4TS U4131 ( .A(n3097), .B(n3096), .Y(n3098) );
INVX2TS U4132 ( .A(n3117), .Y(n3119) );
INVX2TS U4133 ( .A(n4297), .Y(n3130) );
XNOR2X1TS U4134 ( .A(n3127), .B(n3128), .Y(n3133) );
XNOR2X2TS U4135 ( .A(n3135), .B(n3482), .Y(Sgf_operation_EVEN1_S_B[3]) );
ADDFHX4TS U4136 ( .A(n3150), .B(n3149), .CI(n3148), .CO(n3200), .S(n3166) );
ADDFHX4TS U4137 ( .A(n3162), .B(n3160), .CI(n3161), .CO(n3173), .S(n3149) );
ADDFHX4TS U4138 ( .A(n3164), .B(n3165), .CI(n3163), .CO(n3172), .S(n3167) );
ADDFHX4TS U4139 ( .A(n3173), .B(n3174), .CI(n3172), .CO(n3268), .S(n3199) );
CMPR22X2TS U4140 ( .A(n3178), .B(n3177), .CO(n3265), .S(n3175) );
OAI22X1TS U4141 ( .A0(n795), .A1(n3256), .B0(n550), .B1(n3179), .Y(n3263) );
OR2X1TS U4142 ( .A(n3205), .B(n3204), .Y(n3223) );
NAND2X1TS U4143 ( .A(n3205), .B(n3204), .Y(n3220) );
NOR2X1TS U4144 ( .A(n804), .B(n393), .Y(n3272) );
NAND2X1TS U4145 ( .A(n804), .B(n393), .Y(n3273) );
INVX2TS U4146 ( .A(n3850), .Y(n3346) );
NAND2X1TS U4147 ( .A(n3851), .B(n3346), .Y(n3238) );
INVX2TS U4148 ( .A(n3854), .Y(n3236) );
AOI21X1TS U4149 ( .A0(n3857), .A1(n3346), .B0(n3236), .Y(n3237) );
NAND2X1TS U4150 ( .A(n3853), .B(n3852), .Y(n3242) );
OAI22X1TS U4151 ( .A0(n795), .A1(n3293), .B0(n871), .B1(n3309), .Y(n3296) );
OAI22X1TS U4152 ( .A0(n794), .A1(n3292), .B0(n550), .B1(n3251), .Y(n3295) );
ADDFHX4TS U4153 ( .A(n3254), .B(n3253), .CI(n3252), .CO(n3298), .S(n3249) );
ADDFHX4TS U4154 ( .A(n3282), .B(n3281), .CI(n3280), .CO(n3301), .S(n3270) );
OAI22X1TS U4155 ( .A0(n795), .A1(n3309), .B0(n521), .B1(n3293), .Y(n3311) );
ADDFHX4TS U4156 ( .A(n3299), .B(n3298), .CI(n3297), .CO(n3306), .S(n3280) );
INVX2TS U4157 ( .A(n3338), .Y(n3335) );
INVX2TS U4158 ( .A(n3857), .Y(n3344) );
XNOR2X4TS U4159 ( .A(n3360), .B(n3359), .Y(Sgf_operation_EVEN1_Q_left[8]) );
XNOR2X4TS U4160 ( .A(n3372), .B(n3371), .Y(Sgf_operation_EVEN1_Q_left[7]) );
NAND2X1TS U4161 ( .A(n3385), .B(n3384), .Y(n3386) );
NAND2X1TS U4162 ( .A(n3402), .B(n3401), .Y(n3404) );
CMPR22X2TS U4163 ( .A(n3409), .B(n3408), .CO(n3468), .S(n3451) );
OR2X8TS U4164 ( .A(n3473), .B(n3474), .Y(n3761) );
INVX2TS U4165 ( .A(n3455), .Y(n3443) );
NAND2X1TS U4166 ( .A(n3443), .B(n3454), .Y(n3445) );
OAI21X4TS U4167 ( .A0(n3826), .A1(n3823), .B0(n3824), .Y(n3821) );
OAI21X2TS U4168 ( .A0(n3456), .A1(n3455), .B0(n3454), .Y(n3461) );
CLKINVX1TS U4169 ( .A(n3457), .Y(n3459) );
AOI21X4TS U4170 ( .A0(n3821), .A1(n3820), .B0(n3464), .Y(n3780) );
ADDFHX4TS U4171 ( .A(n3466), .B(n3467), .CI(n3465), .CO(n3412), .S(n3472) );
ADDFHX4TS U4172 ( .A(n3470), .B(n3469), .CI(n3468), .CO(n3417), .S(n3471) );
OAI21X4TS U4173 ( .A0(n3780), .A1(n3776), .B0(n3777), .Y(n3763) );
OAI2BB1X4TS U4174 ( .A0N(n3763), .A1N(n3761), .B0(n3760), .Y(n3475) );
AOI21X1TS U4175 ( .A0(n3482), .A1(n3481), .B0(n3480), .Y(n3486) );
OAI22X1TS U4176 ( .A0(n3547), .A1(n3573), .B0(n3524), .B1(n2899), .Y(n3529)
);
OAI22X1TS U4177 ( .A0(n3547), .A1(n2899), .B0(n3557), .B1(n3573), .Y(n3561)
);
ADDFHX4TS U4178 ( .A(n3550), .B(n3549), .CI(n3548), .CO(n3569), .S(n3564) );
OAI22X1TS U4179 ( .A0(n3557), .A1(n2899), .B0(n3574), .B1(n3573), .Y(n3571)
);
OAI22X1TS U4180 ( .A0(n3574), .A1(n2899), .B0(n3573), .B1(n845), .Y(n3795)
);
CLKINVX1TS U4181 ( .A(n968), .Y(n3577) );
CMPR32X2TS U4182 ( .A(n3580), .B(n3579), .C(n3578), .CO(n3793), .S(n3583) );
NAND2X1TS U4183 ( .A(n3589), .B(n3593), .Y(n3595) );
AOI21X1TS U4184 ( .A0(n2615), .A1(n3593), .B0(n3592), .Y(n3594) );
AOI21X4TS U4185 ( .A0(n3644), .A1(n1057), .B0(n3643), .Y(
DP_OP_153J6_122_5442_n54) );
OAI22X1TS U4186 ( .A0(n3661), .A1(n4683), .B0(n874), .B1(n4684), .Y(n3683)
);
ADDFHX4TS U4187 ( .A(n3667), .B(n3666), .CI(n3665), .CO(n3679), .S(n3650) );
NAND2BX1TS U4188 ( .AN(n875), .B(n4684), .Y(n3682) );
CMPR32X2TS U4189 ( .A(n3685), .B(n3684), .C(n3683), .CO(n3705), .S(n3687) );
INVX2TS U4190 ( .A(n3712), .Y(n3695) );
INVX2TS U4191 ( .A(n3978), .Y(n3718) );
INVX2TS U4192 ( .A(n885), .Y(n3726) );
NOR2X8TS U4193 ( .A(n4091), .B(FS_Module_state_reg[1]), .Y(n4213) );
AOI22X1TS U4194 ( .A0(n4213), .A1(n4004), .B0(n4019), .B1(n4091), .Y(n3730)
);
NAND2X2TS U4195 ( .A(n4132), .B(n4137), .Y(n3747) );
OAI21X4TS U4196 ( .A0(n4150), .A1(n4145), .B0(n4151), .Y(n4139) );
NAND2X8TS U4197 ( .A(n3749), .B(n4139), .Y(n4165) );
OA21X4TS U4198 ( .A0(n877), .A1(n3754), .B0(n3753), .Y(n3756) );
XNOR2X4TS U4199 ( .A(n3756), .B(n3755), .Y(n3757) );
CLKINVX6TS U4200 ( .A(n4199), .Y(n3758) );
NAND3X4TS U4201 ( .A(n4200), .B(n4213), .C(n3758), .Y(n3759) );
XNOR2X4TS U4202 ( .A(n3763), .B(n3762), .Y(Sgf_operation_EVEN1_S_B[9]) );
AO21X4TS U4203 ( .A0(n3975), .A1(n901), .B0(n3782), .Y(n4724) );
INVX2TS U4204 ( .A(n3786), .Y(n3787) );
NOR2X1TS U4205 ( .A(n3787), .B(n845), .Y(n3789) );
XNOR2X1TS U4206 ( .A(n3789), .B(n3788), .Y(n3798) );
CLKBUFX3TS U4207 ( .A(n4939), .Y(n4940) );
XNOR2X1TS U4208 ( .A(n3807), .B(n3806), .Y(Sgf_operation_EVEN1_S_B[5]) );
XNOR2X1TS U4209 ( .A(n3822), .B(n3821), .Y(Sgf_operation_EVEN1_S_B[7]) );
OAI21X1TS U4210 ( .A0(FSM_selector_B_1_), .A1(n4774), .B0(n3839), .Y(n3832)
);
XOR2X1TS U4211 ( .A(n796), .B(n3832), .Y(DP_OP_36J6_126_4699_n17) );
XOR2X1TS U4212 ( .A(n797), .B(n3833), .Y(DP_OP_36J6_126_4699_n18) );
OAI21X1TS U4213 ( .A0(FSM_selector_B_1_), .A1(n4749), .B0(n3839), .Y(n3834)
);
XOR2X1TS U4214 ( .A(n797), .B(n3834), .Y(DP_OP_36J6_126_4699_n19) );
OAI21X1TS U4215 ( .A0(FSM_selector_B_1_), .A1(n4867), .B0(n3839), .Y(n3835)
);
XOR2X1TS U4216 ( .A(n797), .B(n3835), .Y(DP_OP_36J6_126_4699_n16) );
XOR2X1TS U4217 ( .A(n796), .B(n3836), .Y(DP_OP_36J6_126_4699_n20) );
XOR2X1TS U4218 ( .A(n797), .B(n3838), .Y(DP_OP_36J6_126_4699_n21) );
NOR3X1TS U4219 ( .A(n4876), .B(FSM_selector_B_1_), .C(n4201), .Y(n3842) );
NOR2X8TS U4220 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]), .Y(
n4093) );
NOR2BX1TS U4221 ( .AN(n317), .B(n4487), .Y(n4506) );
MX2X4TS U4222 ( .A(Data_MX[7]), .B(n4931), .S0(n4015), .Y(
DP_OP_155J6_124_2038_n795) );
MX2X6TS U4223 ( .A(Data_MX[3]), .B(n4864), .S0(n4015), .Y(
DP_OP_155J6_124_2038_n803) );
MX2X6TS U4224 ( .A(Data_MX[8]), .B(n4833), .S0(n4015), .Y(n352) );
NOR2BX1TS U4225 ( .AN(n352), .B(n4508), .Y(n3843) );
OAI21X1TS U4226 ( .A0(n4505), .A1(n4536), .B0(n4549), .Y(n4548) );
NAND2X2TS U4227 ( .A(n350), .B(n3844), .Y(n4492) );
MX2X4TS U4228 ( .A(Data_MY[3]), .B(n4885), .S0(n3969), .Y(n315) );
OR2X2TS U4229 ( .A(n4543), .B(n4508), .Y(n4545) );
MX2X6TS U4230 ( .A(Data_MX[4]), .B(Op_MX[4]), .S0(n4015), .Y(n348) );
MX2X4TS U4231 ( .A(Data_MY[0]), .B(n4922), .S0(n3969), .Y(n312) );
NOR2X1TS U4232 ( .A(n4557), .B(n4501), .Y(n4517) );
NAND2BX1TS U4233 ( .AN(n4543), .B(DP_OP_155J6_124_2038_n803), .Y(n4544) );
MXI2X4TS U4234 ( .A(n3845), .B(n4782), .S0(n3964), .Y(n319) );
MX2X4TS U4235 ( .A(Data_MY[8]), .B(n4930), .S0(n3964), .Y(n320) );
OR2X2TS U4236 ( .A(n4496), .B(n4490), .Y(n4521) );
NOR2X1TS U4237 ( .A(n4535), .B(n4529), .Y(n4542) );
NAND2BX2TS U4238 ( .AN(n4495), .B(n348), .Y(n4555) );
NAND2BX1TS U4239 ( .AN(n4495), .B(n346), .Y(n4507) );
NOR2X1TS U4240 ( .A(n4496), .B(n4541), .Y(n4540) );
MX2X4TS U4241 ( .A(Data_MY[6]), .B(Op_MY[6]), .S0(n3964), .Y(
DP_OP_153J6_122_5442_n1475) );
NOR2X1TS U4242 ( .A(n4509), .B(n4508), .Y(n4513) );
OR2X2TS U4243 ( .A(n4493), .B(n4541), .Y(n4550) );
NAND2BX1TS U4244 ( .AN(n352), .B(n4508), .Y(n4510) );
NOR2X1TS U4245 ( .A(n4496), .B(n4498), .Y(n4497) );
NOR2X1TS U4246 ( .A(n4546), .B(n4498), .Y(n4554) );
BUFX3TS U4247 ( .A(n4941), .Y(n4944) );
BUFX3TS U4248 ( .A(n4944), .Y(n4945) );
NAND2X1TS U4249 ( .A(n3851), .B(n3856), .Y(n3859) );
AOI21X1TS U4250 ( .A0(n3857), .A1(n3856), .B0(n3855), .Y(n3858) );
CMPR32X2TS U4251 ( .A(n320), .B(n332), .C(n3861), .CO(n4628), .S(n4629) );
NAND2X2TS U4252 ( .A(n349), .B(n4821), .Y(n4652) );
MX2X4TS U4253 ( .A(Data_MX[18]), .B(Op_MX[18]), .S0(n3970), .Y(n362) );
OR2X2TS U4254 ( .A(n362), .B(n350), .Y(n4618) );
AOI21X1TS U4255 ( .A0(n4622), .A1(n4618), .B0(n4631), .Y(n4636) );
NAND2X1TS U4256 ( .A(n3863), .B(n3862), .Y(n3865) );
AND2X2TS U4257 ( .A(n364), .B(n352), .Y(n4638) );
AND2X2TS U4258 ( .A(n365), .B(n353), .Y(n4627) );
MX2X4TS U4259 ( .A(Data_MX[12]), .B(n4883), .S0(n3964), .Y(n356) );
NOR2BX1TS U4260 ( .AN(n4705), .B(n3844), .Y(n4633) );
NAND2X1TS U4261 ( .A(n3867), .B(n3919), .Y(n3868) );
XOR2X1TS U4262 ( .A(n3921), .B(n3868), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]) );
OR2X1TS U4263 ( .A(n3870), .B(n3869), .Y(n3871) );
INVX2TS U4264 ( .A(n3900), .Y(n3873) );
MX2X4TS U4265 ( .A(Data_MX[19]), .B(Op_MX[19]), .S0(n3970), .Y(n363) );
CMPR32X2TS U4266 ( .A(n352), .B(n364), .C(n3875), .CO(n4619), .S(n4620) );
OAI21X4TS U4267 ( .A0(n710), .A1(n1289), .B0(n3881), .Y(n3878) );
INVX4TS U4268 ( .A(n1289), .Y(n3882) );
INVX4TS U4269 ( .A(n3888), .Y(n3890) );
AOI21X1TS U4271 ( .A0(n3910), .A1(n3909), .B0(n3908), .Y(n3911) );
INVX2TS U4272 ( .A(n3914), .Y(n3916) );
NAND2X1TS U4273 ( .A(n3924), .B(n3923), .Y(n3925) );
XNOR2X1TS U4274 ( .A(n3926), .B(n3925), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]) );
INVX2TS U4275 ( .A(n3927), .Y(n3929) );
NAND2X1TS U4276 ( .A(n3929), .B(n3928), .Y(n3931) );
INVX2TS U4277 ( .A(n3939), .Y(n4642) );
NOR2X2TS U4278 ( .A(n358), .B(n346), .Y(n4593) );
OR2X2TS U4279 ( .A(n359), .B(DP_OP_155J6_124_2038_n803), .Y(n3932) );
NAND2X1TS U4280 ( .A(n3932), .B(n3935), .Y(n3933) );
XNOR2X1TS U4281 ( .A(n3934), .B(n3933), .Y(n4645) );
AOI21X1TS U4282 ( .A0(n3939), .A1(n3938), .B0(n3937), .Y(n4617) );
NOR2X2TS U4283 ( .A(n360), .B(n348), .Y(n4621) );
NAND2X2TS U4284 ( .A(n3940), .B(n4834), .Y(n3954) );
INVX2TS U4285 ( .A(n3944), .Y(n3941) );
NAND2X2TS U4286 ( .A(n326), .B(n314), .Y(n3945) );
NAND2X1TS U4287 ( .A(n3941), .B(n3945), .Y(n3942) );
NAND2X2TS U4288 ( .A(n327), .B(n315), .Y(n3951) );
AOI21X1TS U4289 ( .A0(n3948), .A1(n3947), .B0(n3946), .Y(n4599) );
MX2X4TS U4290 ( .A(Data_MY[16]), .B(n4925), .S0(n4290), .Y(n328) );
NAND2X2TS U4291 ( .A(n328), .B(n316), .Y(n4598) );
MXI2X4TS U4292 ( .A(n3949), .B(n4795), .S0(n4290), .Y(n329) );
NAND2X2TS U4293 ( .A(n317), .B(n329), .Y(n4635) );
INVX2TS U4294 ( .A(n3950), .Y(n3952) );
NAND2X1TS U4295 ( .A(n3952), .B(n3951), .Y(n4641) );
NAND2X1TS U4296 ( .A(n3955), .B(n3954), .Y(n4644) );
OR2X2TS U4297 ( .A(n364), .B(n352), .Y(n4623) );
NAND2BX1TS U4298 ( .AN(n330), .B(n4546), .Y(n4639) );
NOR2BX1TS U4299 ( .AN(n330), .B(n4546), .Y(n4624) );
NAND2X1TS U4300 ( .A(n3958), .B(n3957), .Y(n4634) );
INVX2TS U4301 ( .A(n3959), .Y(n3961) );
NAND2X1TS U4302 ( .A(n3961), .B(n3960), .Y(n3963) );
NOR2X1TS U4303 ( .A(n328), .B(n316), .Y(n4643) );
INVX2TS U4304 ( .A(n322), .Y(n4630) );
NAND2X1TS U4305 ( .A(n333), .B(n327), .Y(n4678) );
NOR2X2TS U4306 ( .A(n331), .B(n3940), .Y(n3966) );
NAND2X2TS U4307 ( .A(n3965), .B(n4670), .Y(n4671) );
NOR2X1TS U4308 ( .A(n4682), .B(n4694), .Y(n4697) );
NAND2X1TS U4309 ( .A(n3968), .B(n3967), .Y(n4712) );
NOR2X1TS U4310 ( .A(n4666), .B(n4688), .Y(n4702) );
NOR2X1TS U4311 ( .A(n4694), .B(n4688), .Y(n4693) );
INVX2TS U4312 ( .A(n357), .Y(n4696) );
NOR2X1TS U4313 ( .A(n4699), .B(n4696), .Y(n4698) );
NOR2X1TS U4314 ( .A(n4703), .B(n4705), .Y(n4704) );
OR2X2TS U4315 ( .A(n333), .B(n327), .Y(n4707) );
INVX2TS U4316 ( .A(n334), .Y(n4674) );
NOR2X1TS U4317 ( .A(n4674), .B(n4663), .Y(n4673) );
NOR2X1TS U4318 ( .A(n4666), .B(n4690), .Y(n4689) );
INVX2TS U4319 ( .A(n331), .Y(n4679) );
NOR2X1TS U4320 ( .A(n333), .B(n327), .Y(n4681) );
INVX2TS U4321 ( .A(n330), .Y(n4711) );
INVX2TS U4322 ( .A(n366), .Y(n4687) );
NOR2X2TS U4323 ( .A(n3988), .B(n1505), .Y(add_x_23_n23) );
INVX2TS U4324 ( .A(n3996), .Y(n3990) );
AOI21X1TS U4325 ( .A0(n3999), .A1(n3998), .B0(n3990), .Y(n3991) );
NAND2X1TS U4326 ( .A(n3996), .B(n456), .Y(n3997) );
AOI21X1TS U4327 ( .A0(n3999), .A1(n3998), .B0(n3997), .Y(n4000) );
CLKBUFX2TS U4328 ( .A(n4950), .Y(n4949) );
NOR2X2TS U4329 ( .A(n4005), .B(n4004), .Y(ready) );
NAND2BX2TS U4330 ( .AN(ack_FSM), .B(ready), .Y(n4014) );
AOI22X1TS U4331 ( .A0(n4200), .A1(n4747), .B0(n4019), .B1(n4006), .Y(n4007)
);
NAND2X2TS U4332 ( .A(n4014), .B(n4007), .Y(n377) );
NOR2X1TS U4333 ( .A(n4781), .B(n4008), .Y(S_Oper_A_exp[8]) );
XNOR2X1TS U4334 ( .A(DP_OP_36J6_126_4699_n1), .B(n4472), .Y(n4012) );
NAND2X2TS U4335 ( .A(n4014), .B(n4013), .Y(n4983) );
CLKMX2X2TS U4336 ( .A(Data_MX[11]), .B(n681), .S0(n4015), .Y(n355) );
NAND3X2TS U4337 ( .A(n4820), .B(n4819), .C(n4818), .Y(n4391) );
NAND3X2TS U4338 ( .A(n4811), .B(n4810), .C(n4809), .Y(n4390) );
NAND3X2TS U4339 ( .A(n4824), .B(n4823), .C(n4822), .Y(n4385) );
AO22X2TS U4340 ( .A0(n4306), .A1(n4385), .B0(final_result_ieee[18]), .B1(
n4310), .Y(n182) );
NAND2BX1TS U4341 ( .AN(n4044), .B(n4045), .Y(n4023) );
XNOR2X1TS U4342 ( .A(n4024), .B(n4023), .Y(n4025) );
NAND2X1TS U4343 ( .A(n4026), .B(n4027), .Y(n4033) );
AOI2BB1X1TS U4344 ( .A0N(n4031), .A1N(n4030), .B0(n4029), .Y(n4032) );
OR2X2TS U4345 ( .A(n4035), .B(n4034), .Y(n4037) );
NAND2X1TS U4346 ( .A(n4037), .B(n4036), .Y(n4038) );
XNOR2X1TS U4347 ( .A(n4039), .B(n4038), .Y(n4040) );
AOI22X1TS U4348 ( .A0(n4293), .A1(Add_result[1]), .B0(
Sgf_normalized_result[0]), .B1(n4292), .Y(n4043) );
AOI2BB2X1TS U4349 ( .B0(n4236), .B1(n262), .A0N(n858), .A1N(n4984), .Y(n4042) );
NAND2X1TS U4350 ( .A(n4206), .B(n261), .Y(n4041) );
INVX2TS U4351 ( .A(n4044), .Y(n4046) );
NAND2X1TS U4352 ( .A(n4072), .B(n4046), .Y(n4048) );
AOI21X1TS U4353 ( .A0(n4078), .A1(n4046), .B0(n799), .Y(n4047) );
INVX2TS U4354 ( .A(n4049), .Y(n4051) );
NAND2X1TS U4355 ( .A(n4051), .B(n4050), .Y(n4052) );
XNOR2X1TS U4356 ( .A(n4053), .B(n4052), .Y(n4054) );
NAND2X1TS U4357 ( .A(n4218), .B(n262), .Y(n4056) );
NAND2X1TS U4358 ( .A(n4072), .B(n4069), .Y(n4060) );
AOI21X1TS U4359 ( .A0(n4078), .A1(n4069), .B0(n4075), .Y(n4059) );
AND2X2TS U4360 ( .A(n4074), .B(n4073), .Y(n4062) );
XOR2X1TS U4361 ( .A(n4063), .B(n4062), .Y(n4064) );
AOI22X1TS U4362 ( .A0(n4291), .A1(Add_result[3]), .B0(
Sgf_normalized_result[2]), .B1(n4253), .Y(n4068) );
NAND2X1TS U4363 ( .A(n4206), .B(n263), .Y(n4066) );
OAI2BB1X1TS U4364 ( .A0N(n4075), .A1N(n4074), .B0(n4073), .Y(n4076) );
AOI21X1TS U4365 ( .A0(n4078), .A1(n4077), .B0(n4076), .Y(n4079) );
AOI22X1TS U4366 ( .A0(n4294), .A1(Add_result[4]), .B0(
Sgf_normalized_result[3]), .B1(n4253), .Y(n4090) );
AOI2BB2X1TS U4367 ( .B0(n4233), .B1(n265), .A0N(n858), .A1N(n4770), .Y(n4089) );
NAND2X1TS U4368 ( .A(n4206), .B(n264), .Y(n4088) );
NAND2X2TS U4369 ( .A(n4093), .B(n4092), .Y(n4988) );
AOI22X1TS U4370 ( .A0(n4293), .A1(Add_result[5]), .B0(
Sgf_normalized_result[4]), .B1(n4253), .Y(n4103) );
NAND2X1TS U4371 ( .A(n4210), .B(n265), .Y(n4101) );
AOI22X1TS U4372 ( .A0(n4293), .A1(Add_result[8]), .B0(
Sgf_normalized_result[7]), .B1(n4253), .Y(n4106) );
AOI22X1TS U4373 ( .A0(n4294), .A1(Add_result[6]), .B0(
Sgf_normalized_result[5]), .B1(n4253), .Y(n4109) );
AOI22X1TS U4374 ( .A0(n4294), .A1(Add_result[7]), .B0(
Sgf_normalized_result[6]), .B1(n4253), .Y(n4112) );
AOI22X1TS U4375 ( .A0(n4291), .A1(Add_result[9]), .B0(
Sgf_normalized_result[8]), .B1(n4292), .Y(n4115) );
AOI2BB2X4TS U4376 ( .B0(n4236), .B1(n270), .A0N(n859), .A1N(n4765), .Y(n4114) );
AOI22X1TS U4377 ( .A0(n4294), .A1(Add_result[10]), .B0(
Sgf_normalized_result[9]), .B1(n4292), .Y(n4118) );
INVX2TS U4378 ( .A(n4133), .Y(n4120) );
OAI21X4TS U4379 ( .A0(n4194), .A1(n4124), .B0(n4123), .Y(n4125) );
OAI2BB1X4TS U4380 ( .A0N(n665), .A1N(n4131), .B0(n4910), .Y(n4217) );
OAI2BB1X4TS U4381 ( .A0N(n665), .A1N(n4143), .B0(n4917), .Y(n4228) );
AND2X2TS U4382 ( .A(n4152), .B(n4151), .Y(n4153) );
OAI2BB1X4TS U4383 ( .A0N(n665), .A1N(n4155), .B0(n4918), .Y(n4229) );
OA21X4TS U4384 ( .A0(n4194), .A1(n4169), .B0(n4168), .Y(n4172) );
OAI2BB1X4TS U4385 ( .A0N(n665), .A1N(n4173), .B0(n4911), .Y(n4230) );
OAI2BB1X4TS U4386 ( .A0N(n665), .A1N(n4185), .B0(n4912), .Y(n4231) );
NAND2X1TS U4387 ( .A(n4936), .B(n4231), .Y(n4957) );
OAI2BB1X4TS U4388 ( .A0N(n665), .A1N(n4196), .B0(n4913), .Y(n4232) );
NAND2X1TS U4389 ( .A(n4218), .B(n4231), .Y(n4958) );
AOI22X1TS U4390 ( .A0(n4293), .A1(Add_result[20]), .B0(
Sgf_normalized_result[19]), .B1(n4202), .Y(n4205) );
AOI22X1TS U4391 ( .A0(n4294), .A1(Add_result[22]), .B0(n886), .B1(n4202),
.Y(n4207) );
AOI22X1TS U4392 ( .A0(n4294), .A1(Add_result[23]), .B0(
Sgf_normalized_result[22]), .B1(n4202), .Y(n4211) );
BUFX8TS U4393 ( .A(n4343), .Y(n4935) );
AOI22X1TS U4394 ( .A0(n4294), .A1(Add_result[21]), .B0(
Sgf_normalized_result[20]), .B1(n4202), .Y(n4221) );
AO22X2TS U4395 ( .A0(n4306), .A1(Sgf_normalized_result[11]), .B0(
final_result_ieee[11]), .B1(n4308), .Y(n189) );
AO22X2TS U4396 ( .A0(n4306), .A1(Sgf_normalized_result[12]), .B0(
final_result_ieee[12]), .B1(n4308), .Y(n188) );
CLKMX2X2TS U4397 ( .A(Op_MX[23]), .B(exp_oper_result[0]), .S0(FSM_selector_A), .Y(S_Oper_A_exp[0]) );
CLKMX2X2TS U4398 ( .A(Op_MX[26]), .B(exp_oper_result[3]), .S0(FSM_selector_A), .Y(S_Oper_A_exp[3]) );
CLKMX2X2TS U4399 ( .A(Op_MX[28]), .B(exp_oper_result[5]), .S0(FSM_selector_A), .Y(S_Oper_A_exp[5]) );
CLKMX2X2TS U4400 ( .A(Op_MX[29]), .B(n228), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[6]) );
CLKMX2X2TS U4401 ( .A(n4827), .B(n4826), .S0(n4825), .Y(n310) );
NOR2X2TS U4402 ( .A(Sgf_normalized_result[1]), .B(Sgf_normalized_result[0]),
.Y(n4313) );
NAND2X1TS U4403 ( .A(Sgf_normalized_result[3]), .B(Sgf_normalized_result[2]),
.Y(n4237) );
NAND2X2TS U4404 ( .A(Sgf_normalized_result[6]), .B(Sgf_normalized_result[7]),
.Y(n4238) );
NOR2X1TS U4405 ( .A(n4238), .B(n4772), .Y(n4240) );
NOR2X1TS U4406 ( .A(n4353), .B(n4242), .Y(n4243) );
NAND2X1TS U4407 ( .A(Sgf_normalized_result[20]), .B(
Sgf_normalized_result[21]), .Y(n4369) );
NAND2X1TS U4408 ( .A(Sgf_normalized_result[22]), .B(n310), .Y(n4246) );
AND2X2TS U4409 ( .A(n4400), .B(n4247), .Y(n4248) );
NAND2X1TS U4410 ( .A(n4401), .B(n4248), .Y(n4249) );
MXI2X1TS U4411 ( .A(n4249), .B(n753), .S0(n4935), .Y(n285) );
NAND2X1TS U4412 ( .A(n4988), .B(n4781), .Y(n376) );
CLKMX2X2TS U4413 ( .A(Op_MX[30]), .B(n227), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[7]) );
NAND2X1TS U4414 ( .A(n797), .B(zero_flag), .Y(n4252) );
NAND3X1TS U4415 ( .A(n4254), .B(n4253), .C(n4252), .Y(n380) );
MXI2X1TS U4416 ( .A(n2610), .B(n4753), .S0(n4936), .Y(n238) );
NOR4X1TS U4417 ( .A(Op_MY[25]), .B(Op_MY[26]), .C(Op_MY[27]), .D(Op_MY[28]),
.Y(n4259) );
AND4X2TS U4418 ( .A(n4867), .B(n4868), .C(n4255), .D(n4876), .Y(n4258) );
NOR4X1TS U4419 ( .A(n4877), .B(n4794), .C(n698), .D(n4878), .Y(n4257) );
NAND4X1TS U4420 ( .A(n4259), .B(n4258), .C(n4257), .D(n4256), .Y(n4281) );
NOR4BX1TS U4421 ( .AN(n4870), .B(n4928), .C(Op_MY[9]), .D(n4869), .Y(n4262)
);
NAND4X1TS U4422 ( .A(n4265), .B(n4264), .C(n4263), .D(n4262), .Y(n4280) );
NAND4X1TS U4423 ( .A(n4273), .B(n4272), .C(n4271), .D(n4270), .Y(n4279) );
NOR4BX1TS U4424 ( .AN(n4740), .B(Op_MX[21]), .C(DP_OP_153J6_122_5442_n1504),
.D(n681), .Y(n4277) );
NOR3X1TS U4425 ( .A(n4932), .B(Op_MX[23]), .C(Op_MX[24]), .Y(n4274) );
NAND4X1TS U4426 ( .A(n4277), .B(n4276), .C(n4275), .D(n4274), .Y(n4278) );
OAI22X1TS U4427 ( .A0(n4281), .A1(n4280), .B0(n4279), .B1(n4278), .Y(n4282)
);
NAND2X1TS U4428 ( .A(n4283), .B(n4989), .Y(n4285) );
NAND2X1TS U4429 ( .A(n4285), .B(n4284), .Y(n4287) );
INVX2TS U4430 ( .A(final_result_ieee[31]), .Y(n4286) );
MXI2X1TS U4431 ( .A(n4287), .B(n4286), .S0(n4310), .Y(n168) );
CLKMX2X2TS U4432 ( .A(Data_MX[31]), .B(Op_MX[31]), .S0(n4290), .Y(n343) );
CLKMX2X2TS U4433 ( .A(Data_MY[31]), .B(Op_MY[31]), .S0(n4290), .Y(n381) );
CLKMX2X2TS U4434 ( .A(Data_MX[29]), .B(Op_MX[29]), .S0(n4288), .Y(n373) );
CLKMX2X2TS U4435 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n4288), .Y(n372) );
CLKMX2X2TS U4436 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n4288), .Y(n371) );
CLKMX2X2TS U4437 ( .A(Data_MY[30]), .B(n717), .S0(n4295), .Y(n342) );
CLKMX2X2TS U4438 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n4290), .Y(n335) );
AOI22X1TS U4439 ( .A0(n4294), .A1(Add_result[18]), .B0(n4391), .B1(n4202),
.Y(n4964) );
AOI22X1TS U4440 ( .A0(n4293), .A1(Add_result[17]), .B0(n4390), .B1(n4292),
.Y(n4968) );
AOI22X1TS U4441 ( .A0(n4294), .A1(Add_result[19]), .B0(n4385), .B1(n4202),
.Y(n4960) );
MXI2X1TS U4442 ( .A(Sgf_normalized_result[0]), .B(n4984), .S0(n4935), .Y(
n309) );
AOI2BB2X1TS U4443 ( .B0(n4309), .B1(n4754), .A0N(n4303), .A1N(
final_result_ieee[27]), .Y(n173) );
AOI2BB2X1TS U4444 ( .B0(n4309), .B1(n4757), .A0N(n4303), .A1N(
final_result_ieee[26]), .Y(n174) );
INVX2TS U4445 ( .A(n228), .Y(n4301) );
AOI2BB2X1TS U4446 ( .B0(n4304), .B1(n4301), .A0N(n4303), .A1N(
final_result_ieee[29]), .Y(n171) );
INVX2TS U4447 ( .A(n227), .Y(n4302) );
AOI2BB2X1TS U4448 ( .B0(n4304), .B1(n4302), .A0N(n4303), .A1N(
final_result_ieee[30]), .Y(n170) );
AOI2BB2X1TS U4449 ( .B0(n4304), .B1(n4783), .A0N(n4303), .A1N(
final_result_ieee[23]), .Y(n177) );
AOI2BB2X1TS U4450 ( .B0(n4304), .B1(n4755), .A0N(n4303), .A1N(
final_result_ieee[28]), .Y(n172) );
CLKMX2X2TS U4451 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(
n4985), .Y(n234) );
AO22X2TS U4452 ( .A0(n4306), .A1(Sgf_normalized_result[19]), .B0(
final_result_ieee[19]), .B1(n4310), .Y(n181) );
AO22X2TS U4453 ( .A0(n4306), .A1(Sgf_normalized_result[20]), .B0(
final_result_ieee[20]), .B1(n4310), .Y(n180) );
AO22X2TS U4454 ( .A0(n4306), .A1(Sgf_normalized_result[1]), .B0(
final_result_ieee[1]), .B1(n4307), .Y(n199) );
AO22X2TS U4455 ( .A0(n4306), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[2]), .B1(n4307), .Y(n198) );
CLKMX2X2TS U4456 ( .A(n4311), .B(P_Sgf[5]), .S0(n4938), .Y(n243) );
CLKMX2X2TS U4457 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(
n4985), .Y(n233) );
XNOR2X1TS U4458 ( .A(Sgf_normalized_result[1]), .B(Sgf_normalized_result[0]),
.Y(n4312) );
CLKMX2X2TS U4459 ( .A(n4312), .B(Add_result[1]), .S0(n4935), .Y(n308) );
XNOR2X1TS U4460 ( .A(n4318), .B(Sgf_normalized_result[2]), .Y(n4314) );
XOR2X1TS U4461 ( .A(n4331), .B(Sgf_normalized_result[4]), .Y(n4317) );
XOR2X1TS U4462 ( .A(n4319), .B(n4773), .Y(n4320) );
NAND2X1TS U4463 ( .A(Sgf_normalized_result[5]), .B(Sgf_normalized_result[6]),
.Y(n4323) );
NAND2X1TS U4464 ( .A(n4321), .B(Sgf_normalized_result[6]), .Y(n4322) );
XNOR2X1TS U4465 ( .A(n4324), .B(n4789), .Y(n4325) );
CLKMX2X2TS U4466 ( .A(n4325), .B(Add_result[7]), .S0(n4378), .Y(n302) );
XNOR2X1TS U4467 ( .A(n4364), .B(n4788), .Y(n4327) );
CLKMX2X2TS U4468 ( .A(n4327), .B(Add_result[8]), .S0(n4378), .Y(n301) );
XNOR2X1TS U4469 ( .A(n4329), .B(n4787), .Y(n4330) );
CLKMX2X2TS U4470 ( .A(n4330), .B(Add_result[6]), .S0(n4378), .Y(n303) );
NAND2X1TS U4471 ( .A(n4331), .B(n4793), .Y(n4332) );
XNOR2X1TS U4472 ( .A(n4332), .B(n4772), .Y(n4333) );
CLKMX2X2TS U4473 ( .A(n4333), .B(Add_result[5]), .S0(n4935), .Y(n304) );
NAND2X1TS U4474 ( .A(n4364), .B(n4336), .Y(n4334) );
XOR2X1TS U4475 ( .A(n4334), .B(n4779), .Y(n4335) );
CLKMX2X2TS U4476 ( .A(n4335), .B(n880), .S0(n4378), .Y(n297) );
NOR2X1TS U4477 ( .A(n4354), .B(n4338), .Y(n4339) );
NAND2X1TS U4478 ( .A(n4364), .B(n4339), .Y(n4342) );
XOR2X1TS U4479 ( .A(n4342), .B(n4341), .Y(n4344) );
CLKMX2X2TS U4480 ( .A(n4344), .B(Add_result[15]), .S0(n4343), .Y(n294) );
NOR2X1TS U4481 ( .A(n4354), .B(n4779), .Y(n4345) );
NAND2X1TS U4482 ( .A(n4364), .B(n4345), .Y(n4348) );
XOR2X1TS U4483 ( .A(n4348), .B(n4347), .Y(n4349) );
NAND2X1TS U4484 ( .A(n4364), .B(n4350), .Y(n4351) );
XOR2X1TS U4485 ( .A(n4351), .B(n4792), .Y(n4352) );
CLKMX2X2TS U4486 ( .A(n4352), .B(n861), .S0(n4378), .Y(n298) );
NOR2X1TS U4487 ( .A(n4354), .B(n4353), .Y(n4355) );
NAND2X1TS U4488 ( .A(n4364), .B(n4355), .Y(n4358) );
XOR2X1TS U4489 ( .A(n4358), .B(n4357), .Y(n4359) );
CLKMX2X2TS U4490 ( .A(n4359), .B(Add_result[14]), .S0(n4378), .Y(n295) );
INVX2TS U4491 ( .A(n4360), .Y(n4361) );
NAND2X1TS U4492 ( .A(n4364), .B(n4361), .Y(n4362) );
XOR2X1TS U4493 ( .A(n4362), .B(n4780), .Y(n4363) );
CLKMX2X2TS U4494 ( .A(n4363), .B(n879), .S0(n4378), .Y(n299) );
NAND2X1TS U4495 ( .A(n4364), .B(Sgf_normalized_result[8]), .Y(n4365) );
XOR2X1TS U4496 ( .A(n4365), .B(n4791), .Y(n4366) );
CLKMX2X2TS U4497 ( .A(n4366), .B(n878), .S0(n4378), .Y(n300) );
INVX2TS U4498 ( .A(n4390), .Y(n4367) );
XNOR2X1TS U4499 ( .A(n4401), .B(n4367), .Y(n4368) );
CLKMX2X2TS U4500 ( .A(n4368), .B(Add_result[16]), .S0(n4343), .Y(n293) );
NAND2X1TS U4501 ( .A(n4401), .B(n4371), .Y(n4372) );
XOR2X1TS U4502 ( .A(n4372), .B(n4777), .Y(n4373) );
CLKMX2X2TS U4503 ( .A(n4373), .B(Add_result[22]), .S0(n4935), .Y(n287) );
NAND2X1TS U4504 ( .A(n4401), .B(n4375), .Y(n4377) );
INVX2TS U4505 ( .A(n310), .Y(n4376) );
XOR2X1TS U4506 ( .A(n4377), .B(n4376), .Y(n4379) );
CLKMX2X2TS U4507 ( .A(n4379), .B(Add_result[23]), .S0(n4378), .Y(n286) );
INVX2TS U4508 ( .A(n4400), .Y(n4380) );
NOR2X1TS U4509 ( .A(n4380), .B(n4778), .Y(n4381) );
NAND2X1TS U4510 ( .A(n4401), .B(n4381), .Y(n4382) );
XOR2X1TS U4511 ( .A(n4382), .B(n4790), .Y(n4383) );
CLKMX2X2TS U4512 ( .A(n4383), .B(Add_result[21]), .S0(n4343), .Y(n288) );
INVX2TS U4513 ( .A(n4385), .Y(n4397) );
NAND2X1TS U4514 ( .A(n4401), .B(n4386), .Y(n4388) );
XOR2X1TS U4515 ( .A(n4388), .B(n4387), .Y(n4389) );
CLKMX2X2TS U4516 ( .A(n4389), .B(Add_result[19]), .S0(n4343), .Y(n290) );
NAND2X1TS U4517 ( .A(n4401), .B(n4390), .Y(n4393) );
INVX2TS U4518 ( .A(n4391), .Y(n4392) );
XOR2X1TS U4519 ( .A(n4393), .B(n4392), .Y(n4394) );
CLKMX2X2TS U4520 ( .A(n4394), .B(Add_result[17]), .S0(n4343), .Y(n292) );
INVX2TS U4521 ( .A(n4395), .Y(n4396) );
NAND2X1TS U4522 ( .A(n4401), .B(n4396), .Y(n4398) );
XOR2X1TS U4523 ( .A(n4398), .B(n4397), .Y(n4399) );
CLKMX2X2TS U4524 ( .A(n4399), .B(Add_result[18]), .S0(n4343), .Y(n291) );
NAND2X1TS U4525 ( .A(n4401), .B(n4400), .Y(n4402) );
XOR2X1TS U4526 ( .A(n4402), .B(n4778), .Y(n4403) );
CLKMX2X2TS U4527 ( .A(n4403), .B(Add_result[20]), .S0(n4343), .Y(n289) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk1.tcl_RKOA_1STAGE_syn.sdf");
endmodule
|
module decoder (cx,d);
output [6:0] d;
input [11:0] cx;
reg [6:0] d;
reg [4:0] s;
reg [11:0] cx1;
parameter s0 = 5'b01110;
parameter s1 = 5'b10000;
parameter s2 = 5'b01000;
parameter s3 = 5'b01111;
parameter s4 = 5'b11010;
parameter s5 = 5'b11011;
parameter s6 = 5'b00000;
parameter s7 = 5'b10000;
parameter s8 = 5'b01000;
parameter s9 = 5'b00100;
parameter s10 = 5'b00010;
parameter s11 = 5'b00001;
always @(cx)
begin
cx1[0] = cx[0];
cx1[1] = cx[1];
cx1[2] = cx[2];
cx1[3] = cx[3];
cx1[4] = cx[4];
cx1[5] = cx[5];
cx1[6] = cx[6];
cx1[7] = cx[7];
cx1[8] = cx[8];
cx1[9] = cx[9];
cx1[10] = cx[10];
cx1[11] = cx[11];
s[0]= cx[1]+ cx[4]+ cx[5]+ cx[7];
s[1]= cx[0]+ cx[2]+ cx[3]+ cx[4]+ cx[5]+ cx[8];
s[2]= cx[0]+ cx[3]+ cx[9];
s[3]= cx[0]+ cx[3]+ cx[4]+ cx[5]+ cx[10];
s[4]= cx[3]+ cx[5]+ cx[11];
case(s)
s0:
begin
if(cx[0]==1'b0)
begin
cx1[0]=1'b1;
end
else
begin
cx1[0]=1'b0;
end
end
s1:
begin
if(cx[1]==1'b0)
begin
cx1[1]=1'b1;
end
else
begin
cx1[1]=1'b0;
end
end
s2:
begin
if(cx[2]==1'b0)
begin
cx1[2]=1'b1;
end
else
begin
cx1[2]=1'b0;
end
end
s3:
begin
if(cx[3]==1'b0)
begin
cx1[3]=1'b1;
end
else
begin
cx1[3]=1'b0;
end
end
s4:
begin
if(cx[4]==1'b0)
begin
cx1[4]=1'b1;
end
else
begin
cx1[4]=1'b0;
end
end
s5:
begin
if(cx[5]==1'b0)
begin
cx1[5]=1'b1;
end
else
begin
cx1[5]=1'b0;
end
end
s6:
begin
if(cx[6]==1'b0)
begin
cx1[6]=1'b1;
end
else
begin
cx1[6]=1'b0;
end
end
s7:
begin
if(cx[7]==1'b0)
begin
cx1[7]=1'b1;
end
else
begin
cx1[7]=1'b0;
end
end
s8:
begin
if(cx[8]==1'b0)
begin
cx1[8]=1'b1;
end
else
begin
cx1[8]=1'b0;
end
end
s9:
begin
if(cx[9]==1'b0)
begin
cx1[9]=1'b1;
end
else
begin
cx1[9]=1'b0;
end
end
s10:
begin
if(cx[10]==1'b0)
begin
cx1[10]=1'b1;
end
else
begin
cx1[10]=1'b0;
end
end
default:
begin
if(cx[11]==1'b0)
begin
cx1[11]=1'b0;
end
else
begin
cx1[11]=1'b1;
end
end
endcase
d[0] = cx1[0];
d[1] = cx1[1];
d[2] = cx1[2];
d[3] = cx1[3];
d[4] = cx1[4];
d[5] = cx1[5];
d[6] = cx1[6];
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Oct 19 19:49:19 2016
/////////////////////////////////////////////////////////////
module Oper_Start_In_2_W32 ( clk, rst, load_b_i, intAS, intDX, intDY, DMP_o,
DmP_o, zero_flag_o, real_op_o, sign_final_result_o );
input [31:0] intDX;
input [31:0] intDY;
output [30:0] DMP_o;
output [30:0] DmP_o;
input clk, rst, load_b_i, intAS;
output zero_flag_o, real_op_o, sign_final_result_o;
wire n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146,
n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157,
n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168,
n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, n179,
n180, n181, n182, n183, n184, n185, n186, n187, n188, n189, n190,
n191, n192, n193, n194, n195, n196, n197, n198, n199, n202, n203,
n204, n205, n206, n207, n208, n209, n210, n211, n212, n213, n214,
n215, n216, n217, n218, n219, n220, n221, n222, n223, n224, n225,
n226, n227, n228, n229, n230, n231, n232, n233, n234, n235, n236,
n237, n238, n239, n240, n241, n242, n243, n244, n245, n246, n247,
n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, n258,
n259, n260, n261, n262, n263, n264, n265, n266, n267, n268, n269,
n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, n280,
n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291,
n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302,
n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313,
n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324,
n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, n335,
n336, n337, n338, n339, n340, n341, n342, n343, n344, n345, n346,
n347, n348, n349, n350, n351, n352, n353, n354, n355, n356, n357,
n358, n359, n360, n361, n362, n363, n364, n365, n366, n367, n368,
n369, n370, n371, n372, n373, n374, n375, n376, n377, n378, n379,
n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, n390,
n391, n392, n393, n394, n395, n396, n397, n398, n399, n400, n401,
n402, n403, n404, n405, n406, n407, n408, n409, n410, n411;
DFFRXLTS MRegister_Q_reg_0_ ( .D(n199), .CK(clk), .RN(n136), .Q(DMP_o[0]) );
DFFRXLTS MRegister_Q_reg_1_ ( .D(n198), .CK(clk), .RN(n136), .Q(DMP_o[1]) );
DFFRXLTS MRegister_Q_reg_2_ ( .D(n197), .CK(clk), .RN(n410), .Q(DMP_o[2]) );
DFFRXLTS MRegister_Q_reg_3_ ( .D(n196), .CK(clk), .RN(n411), .Q(DMP_o[3]) );
DFFRXLTS MRegister_Q_reg_4_ ( .D(n195), .CK(clk), .RN(n136), .Q(DMP_o[4]) );
DFFRXLTS MRegister_Q_reg_5_ ( .D(n194), .CK(clk), .RN(n410), .Q(DMP_o[5]) );
DFFRXLTS MRegister_Q_reg_6_ ( .D(n193), .CK(clk), .RN(n410), .Q(DMP_o[6]) );
DFFRXLTS MRegister_Q_reg_7_ ( .D(n192), .CK(clk), .RN(n411), .Q(DMP_o[7]) );
DFFRXLTS MRegister_Q_reg_8_ ( .D(n191), .CK(clk), .RN(n136), .Q(DMP_o[8]) );
DFFRXLTS MRegister_Q_reg_9_ ( .D(n190), .CK(clk), .RN(n411), .Q(DMP_o[9]) );
DFFRXLTS MRegister_Q_reg_10_ ( .D(n189), .CK(clk), .RN(n410), .Q(DMP_o[10])
);
DFFRXLTS MRegister_Q_reg_11_ ( .D(n188), .CK(clk), .RN(n136), .Q(DMP_o[11])
);
DFFRXLTS MRegister_Q_reg_12_ ( .D(n187), .CK(clk), .RN(n410), .Q(DMP_o[12])
);
DFFRXLTS MRegister_Q_reg_13_ ( .D(n186), .CK(clk), .RN(n411), .Q(DMP_o[13])
);
DFFRXLTS MRegister_Q_reg_14_ ( .D(n185), .CK(clk), .RN(n136), .Q(DMP_o[14])
);
DFFRXLTS MRegister_Q_reg_15_ ( .D(n184), .CK(clk), .RN(n410), .Q(DMP_o[15])
);
DFFRXLTS MRegister_Q_reg_16_ ( .D(n183), .CK(clk), .RN(n411), .Q(DMP_o[16])
);
DFFRXLTS MRegister_Q_reg_17_ ( .D(n182), .CK(clk), .RN(n136), .Q(DMP_o[17])
);
DFFRXLTS MRegister_Q_reg_18_ ( .D(n181), .CK(clk), .RN(n410), .Q(DMP_o[18])
);
DFFRXLTS MRegister_Q_reg_19_ ( .D(n180), .CK(clk), .RN(n411), .Q(DMP_o[19])
);
DFFRXLTS MRegister_Q_reg_20_ ( .D(n179), .CK(clk), .RN(n136), .Q(DMP_o[20])
);
DFFRXLTS MRegister_Q_reg_21_ ( .D(n178), .CK(clk), .RN(n410), .Q(DMP_o[21])
);
DFFRXLTS MRegister_Q_reg_22_ ( .D(n177), .CK(clk), .RN(n411), .Q(DMP_o[22])
);
DFFRXLTS MRegister_Q_reg_23_ ( .D(n176), .CK(clk), .RN(n410), .Q(DMP_o[23])
);
DFFRXLTS MRegister_Q_reg_24_ ( .D(n175), .CK(clk), .RN(n410), .Q(DMP_o[24])
);
DFFRXLTS MRegister_Q_reg_25_ ( .D(n174), .CK(clk), .RN(n410), .Q(DMP_o[25])
);
DFFRXLTS MRegister_Q_reg_26_ ( .D(n173), .CK(clk), .RN(n410), .Q(DMP_o[26])
);
DFFRXLTS MRegister_Q_reg_27_ ( .D(n172), .CK(clk), .RN(n410), .Q(DMP_o[27])
);
DFFRXLTS MRegister_Q_reg_28_ ( .D(n171), .CK(clk), .RN(n410), .Q(DMP_o[28])
);
DFFRXLTS MRegister_Q_reg_29_ ( .D(n170), .CK(clk), .RN(n410), .Q(DMP_o[29])
);
DFFRXLTS MRegister_Q_reg_30_ ( .D(n169), .CK(clk), .RN(n410), .Q(DMP_o[30])
);
DFFRXLTS SignRegister_Q_reg_0_ ( .D(n168), .CK(clk), .RN(n410), .Q(
sign_final_result_o) );
DFFRXLTS mRegister_Q_reg_0_ ( .D(n167), .CK(clk), .RN(n410), .Q(DmP_o[0]) );
DFFRXLTS mRegister_Q_reg_1_ ( .D(n166), .CK(clk), .RN(n410), .Q(DmP_o[1]) );
DFFRXLTS mRegister_Q_reg_2_ ( .D(n165), .CK(clk), .RN(n410), .Q(DmP_o[2]) );
DFFRXLTS mRegister_Q_reg_3_ ( .D(n164), .CK(clk), .RN(n136), .Q(DmP_o[3]) );
DFFRXLTS mRegister_Q_reg_4_ ( .D(n163), .CK(clk), .RN(n136), .Q(DmP_o[4]) );
DFFRXLTS mRegister_Q_reg_5_ ( .D(n162), .CK(clk), .RN(n410), .Q(DmP_o[5]) );
DFFRXLTS mRegister_Q_reg_6_ ( .D(n161), .CK(clk), .RN(n411), .Q(DmP_o[6]) );
DFFRXLTS mRegister_Q_reg_7_ ( .D(n160), .CK(clk), .RN(n136), .Q(DmP_o[7]) );
DFFRXLTS mRegister_Q_reg_8_ ( .D(n159), .CK(clk), .RN(n411), .Q(DmP_o[8]) );
DFFRXLTS mRegister_Q_reg_9_ ( .D(n158), .CK(clk), .RN(n136), .Q(DmP_o[9]) );
DFFRXLTS mRegister_Q_reg_10_ ( .D(n157), .CK(clk), .RN(n411), .Q(DmP_o[10])
);
DFFRXLTS mRegister_Q_reg_11_ ( .D(n156), .CK(clk), .RN(n136), .Q(DmP_o[11])
);
DFFRXLTS mRegister_Q_reg_12_ ( .D(n155), .CK(clk), .RN(n411), .Q(DmP_o[12])
);
DFFRXLTS mRegister_Q_reg_13_ ( .D(n154), .CK(clk), .RN(n136), .Q(DmP_o[13])
);
DFFRXLTS mRegister_Q_reg_14_ ( .D(n153), .CK(clk), .RN(n411), .Q(DmP_o[14])
);
DFFRXLTS mRegister_Q_reg_15_ ( .D(n152), .CK(clk), .RN(n136), .Q(DmP_o[15])
);
DFFRXLTS mRegister_Q_reg_16_ ( .D(n151), .CK(clk), .RN(n411), .Q(DmP_o[16])
);
DFFRXLTS mRegister_Q_reg_17_ ( .D(n150), .CK(clk), .RN(n136), .Q(DmP_o[17])
);
DFFRXLTS mRegister_Q_reg_18_ ( .D(n149), .CK(clk), .RN(n411), .Q(DmP_o[18])
);
DFFRXLTS mRegister_Q_reg_19_ ( .D(n148), .CK(clk), .RN(n136), .Q(DmP_o[19])
);
DFFRXLTS mRegister_Q_reg_20_ ( .D(n147), .CK(clk), .RN(n411), .Q(DmP_o[20])
);
DFFRXLTS mRegister_Q_reg_21_ ( .D(n146), .CK(clk), .RN(n136), .Q(DmP_o[21])
);
DFFRXLTS mRegister_Q_reg_22_ ( .D(n145), .CK(clk), .RN(n411), .Q(DmP_o[22])
);
DFFRXLTS mRegister_Q_reg_23_ ( .D(n144), .CK(clk), .RN(n136), .Q(DmP_o[23])
);
DFFRXLTS mRegister_Q_reg_24_ ( .D(n143), .CK(clk), .RN(n411), .Q(DmP_o[24])
);
DFFRXLTS mRegister_Q_reg_25_ ( .D(n142), .CK(clk), .RN(n136), .Q(DmP_o[25])
);
DFFRXLTS mRegister_Q_reg_26_ ( .D(n141), .CK(clk), .RN(n136), .Q(DmP_o[26])
);
DFFRXLTS mRegister_Q_reg_27_ ( .D(n140), .CK(clk), .RN(n411), .Q(DmP_o[27])
);
DFFRXLTS mRegister_Q_reg_28_ ( .D(n139), .CK(clk), .RN(n411), .Q(DmP_o[28])
);
DFFRXLTS mRegister_Q_reg_29_ ( .D(n138), .CK(clk), .RN(n411), .Q(DmP_o[29])
);
DFFRXLTS mRegister_Q_reg_30_ ( .D(n137), .CK(clk), .RN(n411), .Q(DmP_o[30])
);
CLKAND2X2TS U204 ( .A(load_b_i), .B(n378), .Y(n409) );
OAI21XLTS U205 ( .A0(n388), .A1(n322), .B0(n271), .Y(n139) );
OAI21XLTS U206 ( .A0(n357), .A1(n322), .B0(n326), .Y(n140) );
OAI21XLTS U207 ( .A0(n292), .A1(n322), .B0(n280), .Y(n141) );
OAI21XLTS U208 ( .A0(n350), .A1(n322), .B0(n324), .Y(n142) );
OAI21XLTS U209 ( .A0(n289), .A1(n322), .B0(n288), .Y(n143) );
OAI21XLTS U210 ( .A0(n287), .A1(n322), .B0(n286), .Y(n145) );
OAI21XLTS U211 ( .A0(n351), .A1(n322), .B0(n327), .Y(n146) );
OAI21XLTS U212 ( .A0(n382), .A1(n398), .B0(n381), .Y(n147) );
OAI21XLTS U213 ( .A0(n359), .A1(n322), .B0(n325), .Y(n148) );
OAI21XLTS U214 ( .A0(n282), .A1(n322), .B0(n281), .Y(n149) );
OAI21XLTS U215 ( .A0(n356), .A1(n322), .B0(n283), .Y(n150) );
OAI21XLTS U216 ( .A0(n308), .A1(n398), .B0(n290), .Y(n151) );
OAI21XLTS U217 ( .A0(n399), .A1(n398), .B0(n397), .Y(n152) );
OAI21XLTS U218 ( .A0(n396), .A1(n398), .B0(n395), .Y(n154) );
OAI21XLTS U219 ( .A0(n392), .A1(n322), .B0(n328), .Y(n155) );
OAI21XLTS U220 ( .A0(n285), .A1(n322), .B0(n284), .Y(n156) );
OAI21XLTS U221 ( .A0(n394), .A1(n322), .B0(n279), .Y(n157) );
OAI21XLTS U222 ( .A0(n352), .A1(n322), .B0(n306), .Y(n160) );
OAI21XLTS U223 ( .A0(n390), .A1(n322), .B0(n300), .Y(n161) );
OAI21XLTS U224 ( .A0(n358), .A1(n322), .B0(n270), .Y(n162) );
OAI21XLTS U225 ( .A0(n302), .A1(n322), .B0(n301), .Y(n163) );
OAI21XLTS U226 ( .A0(n299), .A1(n398), .B0(n298), .Y(n164) );
OAI21XLTS U227 ( .A0(n312), .A1(n322), .B0(n311), .Y(n165) );
OAI21XLTS U228 ( .A0(n275), .A1(n322), .B0(n274), .Y(n166) );
OAI21XLTS U229 ( .A0(n386), .A1(n398), .B0(n385), .Y(n167) );
OAI21XLTS U230 ( .A0(n314), .A1(n322), .B0(n313), .Y(n169) );
OAI21XLTS U231 ( .A0(n296), .A1(n322), .B0(n278), .Y(n170) );
OAI21XLTS U232 ( .A0(n388), .A1(n398), .B0(n387), .Y(n171) );
OAI21XLTS U233 ( .A0(n273), .A1(n322), .B0(n272), .Y(n172) );
OAI21XLTS U234 ( .A0(n292), .A1(n398), .B0(n291), .Y(n173) );
OAI21XLTS U235 ( .A0(n263), .A1(n322), .B0(n262), .Y(n175) );
OAI21XLTS U236 ( .A0(n384), .A1(n322), .B0(n303), .Y(n176) );
OAI21XLTS U237 ( .A0(n310), .A1(n322), .B0(n309), .Y(n177) );
OAI21XLTS U238 ( .A0(n351), .A1(n398), .B0(n293), .Y(n178) );
OAI21XLTS U239 ( .A0(n382), .A1(n322), .B0(n316), .Y(n179) );
OAI21XLTS U240 ( .A0(n359), .A1(n398), .B0(n297), .Y(n180) );
OAI21XLTS U241 ( .A0(n318), .A1(n322), .B0(n317), .Y(n181) );
OAI21XLTS U242 ( .A0(n261), .A1(n322), .B0(n260), .Y(n182) );
OAI21XLTS U243 ( .A0(n308), .A1(n322), .B0(n307), .Y(n183) );
OAI21XLTS U244 ( .A0(n399), .A1(n322), .B0(n267), .Y(n184) );
OAI21XLTS U245 ( .A0(n339), .A1(n322), .B0(n315), .Y(n185) );
OAI21XLTS U246 ( .A0(n396), .A1(n322), .B0(n266), .Y(n186) );
OAI21XLTS U247 ( .A0(n392), .A1(n398), .B0(n391), .Y(n187) );
OAI21XLTS U248 ( .A0(n259), .A1(n322), .B0(n258), .Y(n188) );
OAI21XLTS U249 ( .A0(n255), .A1(n322), .B0(n254), .Y(n190) );
OAI21XLTS U250 ( .A0(n320), .A1(n322), .B0(n319), .Y(n191) );
OAI21XLTS U251 ( .A0(n265), .A1(n322), .B0(n264), .Y(n192) );
OAI21XLTS U252 ( .A0(n390), .A1(n398), .B0(n389), .Y(n193) );
OAI21XLTS U253 ( .A0(n358), .A1(n398), .B0(n294), .Y(n194) );
OAI21XLTS U254 ( .A0(n257), .A1(n322), .B0(n256), .Y(n195) );
OAI21XLTS U255 ( .A0(n299), .A1(n322), .B0(n253), .Y(n196) );
OAI21XLTS U256 ( .A0(n305), .A1(n322), .B0(n304), .Y(n197) );
OAI21XLTS U257 ( .A0(n323), .A1(n322), .B0(n321), .Y(n198) );
OAI21XLTS U258 ( .A0(n386), .A1(n322), .B0(n329), .Y(n199) );
NOR2XLTS U259 ( .A(intDX[3]), .B(n299), .Y(n216) );
NOR2XLTS U260 ( .A(intDX[13]), .B(n396), .Y(n210) );
NOR2XLTS U261 ( .A(intDX[15]), .B(n399), .Y(n232) );
OAI211XLTS U262 ( .A0(intDY[17]), .A1(n356), .B0(n355), .C0(n354), .Y(n362)
);
OAI211XLTS U263 ( .A0(intDY[12]), .A1(n392), .B0(n341), .C0(n340), .Y(n345)
);
OAI21XLTS U264 ( .A0(intDX[20]), .A1(n382), .B0(n205), .Y(n238) );
OAI211XLTS U265 ( .A0(intDY[10]), .A1(n394), .B0(n365), .C0(n364), .Y(n366)
);
NOR2XLTS U266 ( .A(intDY[24]), .B(n289), .Y(n369) );
AOI211XLTS U267 ( .A0(intDY[12]), .A1(n392), .B0(n214), .C0(n213), .Y(n332)
);
OR2X1TS U268 ( .A(n378), .B(n406), .Y(n398) );
OAI21XLTS U269 ( .A0(n296), .A1(n398), .B0(n295), .Y(n138) );
OAI21XLTS U270 ( .A0(n384), .A1(n398), .B0(n383), .Y(n144) );
OAI21XLTS U271 ( .A0(n277), .A1(n322), .B0(n276), .Y(n159) );
OAI21XLTS U272 ( .A0(n269), .A1(n322), .B0(n268), .Y(n174) );
OAI21XLTS U273 ( .A0(n394), .A1(n398), .B0(n393), .Y(n189) );
INVX2TS U274 ( .A(rst), .Y(n136) );
CLKBUFX2TS U275 ( .A(n136), .Y(n411) );
CLKBUFX2TS U276 ( .A(n136), .Y(n410) );
INVX2TS U277 ( .A(intDY[3]), .Y(n299) );
INVX2TS U278 ( .A(intDY[29]), .Y(n296) );
NOR2XLTS U279 ( .A(intDX[29]), .B(n296), .Y(n241) );
INVX2TS U280 ( .A(intDX[28]), .Y(n388) );
INVX2TS U281 ( .A(intDY[30]), .Y(n314) );
AOI22X1TS U282 ( .A0(intDX[30]), .A1(n314), .B0(intDX[29]), .B1(n296), .Y(
n335) );
OAI31X1TS U283 ( .A0(intDY[28]), .A1(n241), .A2(n388), .B0(n335), .Y(n252)
);
NOR2XLTS U284 ( .A(n314), .B(intDX[30]), .Y(n240) );
INVX2TS U285 ( .A(n240), .Y(n251) );
INVX2TS U286 ( .A(intDX[19]), .Y(n359) );
INVX2TS U287 ( .A(intDX[18]), .Y(n282) );
AOI22X1TS U288 ( .A0(intDY[19]), .A1(n359), .B0(intDY[18]), .B1(n282), .Y(
n208) );
INVX2TS U289 ( .A(intDX[17]), .Y(n356) );
INVX2TS U290 ( .A(intDY[17]), .Y(n261) );
NOR2XLTS U291 ( .A(intDX[17]), .B(n261), .Y(n202) );
INVX2TS U292 ( .A(intDY[16]), .Y(n308) );
NAND2X1TS U293 ( .A(intDX[16]), .B(n308), .Y(n336) );
OAI22X1TS U294 ( .A0(intDY[17]), .A1(n356), .B0(n202), .B1(n336), .Y(n204)
);
INVX2TS U295 ( .A(intDY[18]), .Y(n318) );
NAND2X1TS U296 ( .A(intDX[18]), .B(n318), .Y(n355) );
AOI222XLTS U297 ( .A0(intDY[19]), .A1(n359), .B0(intDY[19]), .B1(n355), .C0(
n359), .C1(n355), .Y(n203) );
AOI21X1TS U298 ( .A0(n208), .A1(n204), .B0(n203), .Y(n239) );
INVX2TS U299 ( .A(intDY[20]), .Y(n382) );
INVX2TS U300 ( .A(intDX[21]), .Y(n351) );
INVX2TS U301 ( .A(intDY[23]), .Y(n384) );
INVX2TS U302 ( .A(intDY[22]), .Y(n310) );
OAI22X1TS U303 ( .A0(intDX[23]), .A1(n384), .B0(intDX[22]), .B1(n310), .Y(
n206) );
AOI21X1TS U304 ( .A0(intDY[21]), .A1(n351), .B0(n206), .Y(n205) );
INVX2TS U305 ( .A(intDX[22]), .Y(n287) );
NOR2XLTS U306 ( .A(intDY[22]), .B(n287), .Y(n363) );
AOI222XLTS U307 ( .A0(intDX[23]), .A1(n363), .B0(intDX[23]), .B1(n384), .C0(
n363), .C1(n384), .Y(n237) );
NAND2X1TS U308 ( .A(intDX[20]), .B(n382), .Y(n354) );
AOI222XLTS U309 ( .A0(intDY[21]), .A1(n351), .B0(intDY[21]), .B1(n354), .C0(
n351), .C1(n354), .Y(n235) );
INVX2TS U310 ( .A(n206), .Y(n234) );
INVX2TS U311 ( .A(n238), .Y(n207) );
OAI211XLTS U312 ( .A0(intDX[16]), .A1(n308), .B0(n208), .C0(n207), .Y(n209)
);
AOI21X1TS U313 ( .A0(intDY[17]), .A1(n356), .B0(n209), .Y(n373) );
INVX2TS U314 ( .A(intDY[15]), .Y(n399) );
INVX2TS U315 ( .A(intDY[14]), .Y(n339) );
NOR2XLTS U316 ( .A(n339), .B(intDX[14]), .Y(n214) );
INVX2TS U317 ( .A(n214), .Y(n212) );
INVX2TS U318 ( .A(intDY[13]), .Y(n396) );
INVX2TS U319 ( .A(intDX[12]), .Y(n392) );
NAND2X1TS U320 ( .A(intDX[13]), .B(n396), .Y(n340) );
OAI31X1TS U321 ( .A0(intDY[12]), .A1(n210), .A2(n392), .B0(n340), .Y(n211)
);
AOI22X1TS U322 ( .A0(intDX[14]), .A1(n339), .B0(n212), .B1(n211), .Y(n231)
);
OAI22X1TS U323 ( .A0(intDX[13]), .A1(n396), .B0(intDX[15]), .B1(n399), .Y(
n213) );
INVX2TS U324 ( .A(intDX[6]), .Y(n390) );
NOR2XLTS U325 ( .A(intDY[6]), .B(n390), .Y(n349) );
INVX2TS U326 ( .A(intDY[7]), .Y(n265) );
AOI222XLTS U327 ( .A0(intDX[7]), .A1(n349), .B0(intDX[7]), .B1(n265), .C0(
n349), .C1(n265), .Y(n222) );
INVX2TS U328 ( .A(intDY[11]), .Y(n259) );
NAND2X1TS U329 ( .A(intDX[11]), .B(n259), .Y(n337) );
INVX2TS U330 ( .A(intDX[4]), .Y(n302) );
INVX2TS U331 ( .A(intDX[5]), .Y(n358) );
AOI22X1TS U332 ( .A0(intDY[4]), .A1(n302), .B0(intDY[5]), .B1(n358), .Y(n344) );
INVX2TS U333 ( .A(intDX[7]), .Y(n352) );
AOI22X1TS U334 ( .A0(intDY[6]), .A1(n390), .B0(intDY[7]), .B1(n352), .Y(n343) );
INVX2TS U335 ( .A(intDY[2]), .Y(n305) );
AOI22X1TS U336 ( .A0(intDX[3]), .A1(n299), .B0(intDX[2]), .B1(n305), .Y(n330) );
INVX2TS U337 ( .A(intDY[1]), .Y(n323) );
INVX2TS U338 ( .A(intDY[0]), .Y(n386) );
AOI22X1TS U339 ( .A0(intDX[1]), .A1(n323), .B0(intDX[0]), .B1(n386), .Y(n331) );
INVX2TS U340 ( .A(intDX[1]), .Y(n275) );
INVX2TS U341 ( .A(intDX[2]), .Y(n312) );
AOI22X1TS U342 ( .A0(intDY[1]), .A1(n275), .B0(intDY[2]), .B1(n312), .Y(n215) );
OAI21XLTS U343 ( .A0(intDX[3]), .A1(n299), .B0(n215), .Y(n377) );
OAI22X1TS U344 ( .A0(n216), .A1(n330), .B0(n331), .B1(n377), .Y(n218) );
INVX2TS U345 ( .A(intDY[4]), .Y(n257) );
NAND2X1TS U346 ( .A(intDX[4]), .B(n257), .Y(n338) );
AOI222XLTS U347 ( .A0(intDY[5]), .A1(n358), .B0(intDY[5]), .B1(n338), .C0(
n358), .C1(n338), .Y(n217) );
AOI32X1TS U348 ( .A0(n344), .A1(n343), .A2(n218), .B0(n217), .B1(n343), .Y(
n221) );
INVX2TS U349 ( .A(intDX[10]), .Y(n394) );
INVX2TS U350 ( .A(intDX[8]), .Y(n277) );
AOI22X1TS U351 ( .A0(intDY[10]), .A1(n394), .B0(intDY[8]), .B1(n277), .Y(
n220) );
INVX2TS U352 ( .A(intDY[9]), .Y(n255) );
NOR2XLTS U353 ( .A(n255), .B(intDX[9]), .Y(n223) );
INVX2TS U354 ( .A(n223), .Y(n219) );
OAI211XLTS U355 ( .A0(intDX[11]), .A1(n259), .B0(n220), .C0(n219), .Y(n376)
);
AOI32X1TS U356 ( .A0(n222), .A1(n337), .A2(n221), .B0(n376), .B1(n337), .Y(
n229) );
INVX2TS U357 ( .A(intDX[11]), .Y(n285) );
NAND2X1TS U358 ( .A(intDY[11]), .B(n285), .Y(n228) );
INVX2TS U359 ( .A(n332), .Y(n224) );
INVX2TS U360 ( .A(intDY[8]), .Y(n320) );
NAND2X1TS U361 ( .A(intDX[8]), .B(n320), .Y(n334) );
NAND2X1TS U362 ( .A(intDX[9]), .B(n255), .Y(n333) );
OAI32X1TS U363 ( .A0(n224), .A1(n223), .A2(n334), .B0(n333), .B1(n224), .Y(
n225) );
AOI21X1TS U364 ( .A0(intDX[10]), .A1(n332), .B0(n225), .Y(n226) );
OAI2BB2XLTS U365 ( .B0(intDY[10]), .B1(n226), .A0N(intDX[10]), .A1N(n225),
.Y(n227) );
AOI22X1TS U366 ( .A0(n332), .A1(n229), .B0(n228), .B1(n227), .Y(n230) );
NAND2X1TS U367 ( .A(intDX[15]), .B(n399), .Y(n342) );
OAI211XLTS U368 ( .A0(n232), .A1(n231), .B0(n230), .C0(n342), .Y(n233) );
AOI22X1TS U369 ( .A0(n235), .A1(n234), .B0(n373), .B1(n233), .Y(n236) );
OAI211XLTS U370 ( .A0(n239), .A1(n238), .B0(n237), .C0(n236), .Y(n250) );
INVX2TS U371 ( .A(intDX[25]), .Y(n350) );
INVX2TS U372 ( .A(intDY[24]), .Y(n263) );
INVX2TS U373 ( .A(intDX[27]), .Y(n357) );
INVX2TS U374 ( .A(intDX[26]), .Y(n292) );
AOI22X1TS U375 ( .A0(intDY[27]), .A1(n357), .B0(intDY[26]), .B1(n292), .Y(
n244) );
AOI211XLTS U376 ( .A0(intDY[28]), .A1(n388), .B0(n241), .C0(n240), .Y(n248)
);
OAI211XLTS U377 ( .A0(intDX[24]), .A1(n263), .B0(n244), .C0(n248), .Y(n242)
);
AOI21X1TS U378 ( .A0(intDY[25]), .A1(n350), .B0(n242), .Y(n372) );
INVX2TS U379 ( .A(intDY[25]), .Y(n269) );
INVX2TS U380 ( .A(intDX[24]), .Y(n289) );
NAND2X1TS U381 ( .A(intDY[25]), .B(n350), .Y(n243) );
AOI22X1TS U382 ( .A0(intDX[25]), .A1(n269), .B0(n369), .B1(n243), .Y(n247)
);
INVX2TS U383 ( .A(n244), .Y(n246) );
NOR2XLTS U384 ( .A(intDY[26]), .B(n292), .Y(n368) );
INVX2TS U385 ( .A(intDY[27]), .Y(n273) );
AOI222XLTS U386 ( .A0(intDX[27]), .A1(n368), .B0(intDX[27]), .B1(n273), .C0(
n368), .C1(n273), .Y(n245) );
OAI21XLTS U387 ( .A0(n247), .A1(n246), .B0(n245), .Y(n249) );
AOI222XLTS U388 ( .A0(n252), .A1(n251), .B0(n250), .B1(n372), .C0(n249),
.C1(n248), .Y(n378) );
INVX2TS U389 ( .A(n409), .Y(n322) );
INVX2TS U390 ( .A(load_b_i), .Y(n403) );
CLKBUFX2TS U391 ( .A(n403), .Y(n406) );
INVX2TS U392 ( .A(n398), .Y(n407) );
AOI22X1TS U393 ( .A0(n407), .A1(intDX[3]), .B0(DMP_o[3]), .B1(n403), .Y(n253) );
AOI22X1TS U394 ( .A0(n407), .A1(intDX[9]), .B0(DMP_o[9]), .B1(n403), .Y(n254) );
INVX2TS U395 ( .A(n398), .Y(n404) );
AOI22X1TS U396 ( .A0(n404), .A1(intDX[4]), .B0(DMP_o[4]), .B1(n403), .Y(n256) );
AOI22X1TS U397 ( .A0(n407), .A1(intDX[11]), .B0(DMP_o[11]), .B1(n403), .Y(
n258) );
AOI22X1TS U398 ( .A0(n404), .A1(intDX[17]), .B0(DMP_o[17]), .B1(n403), .Y(
n260) );
AOI22X1TS U399 ( .A0(n407), .A1(intDX[24]), .B0(DMP_o[24]), .B1(n403), .Y(
n262) );
AOI22X1TS U400 ( .A0(n404), .A1(intDX[7]), .B0(DMP_o[7]), .B1(n403), .Y(n264) );
AOI22X1TS U401 ( .A0(n407), .A1(intDX[13]), .B0(DMP_o[13]), .B1(n403), .Y(
n266) );
AOI22X1TS U402 ( .A0(n407), .A1(intDX[15]), .B0(DMP_o[15]), .B1(n403), .Y(
n267) );
AOI22X1TS U403 ( .A0(n404), .A1(intDX[25]), .B0(DMP_o[25]), .B1(n403), .Y(
n268) );
AOI22X1TS U404 ( .A0(n404), .A1(intDY[5]), .B0(DmP_o[5]), .B1(n403), .Y(n270) );
AOI22X1TS U405 ( .A0(n407), .A1(intDY[28]), .B0(DmP_o[28]), .B1(n403), .Y(
n271) );
AOI22X1TS U406 ( .A0(n407), .A1(intDX[27]), .B0(DMP_o[27]), .B1(n403), .Y(
n272) );
AOI22X1TS U407 ( .A0(n404), .A1(intDY[1]), .B0(DmP_o[1]), .B1(n403), .Y(n274) );
AOI22X1TS U408 ( .A0(n404), .A1(intDY[8]), .B0(DmP_o[8]), .B1(n403), .Y(n276) );
AOI22X1TS U409 ( .A0(n404), .A1(intDX[29]), .B0(DMP_o[29]), .B1(n403), .Y(
n278) );
AOI22X1TS U410 ( .A0(n404), .A1(intDY[10]), .B0(DmP_o[10]), .B1(n403), .Y(
n279) );
AOI22X1TS U411 ( .A0(n407), .A1(intDY[26]), .B0(DmP_o[26]), .B1(n403), .Y(
n280) );
AOI22X1TS U412 ( .A0(n404), .A1(intDY[18]), .B0(DmP_o[18]), .B1(n403), .Y(
n281) );
AOI22X1TS U413 ( .A0(n404), .A1(intDY[17]), .B0(DmP_o[17]), .B1(n403), .Y(
n283) );
AOI22X1TS U414 ( .A0(n404), .A1(intDY[11]), .B0(DmP_o[11]), .B1(n403), .Y(
n284) );
AOI22X1TS U415 ( .A0(n407), .A1(intDY[22]), .B0(DmP_o[22]), .B1(n403), .Y(
n286) );
AOI22X1TS U416 ( .A0(n407), .A1(intDY[24]), .B0(DmP_o[24]), .B1(n403), .Y(
n288) );
AOI22X1TS U417 ( .A0(n409), .A1(intDX[16]), .B0(DmP_o[16]), .B1(n403), .Y(
n290) );
AOI22X1TS U418 ( .A0(n409), .A1(intDY[26]), .B0(DMP_o[26]), .B1(n403), .Y(
n291) );
AOI22X1TS U419 ( .A0(n409), .A1(intDY[21]), .B0(DMP_o[21]), .B1(n403), .Y(
n293) );
AOI22X1TS U420 ( .A0(n409), .A1(intDY[5]), .B0(DMP_o[5]), .B1(n403), .Y(n294) );
AOI22X1TS U421 ( .A0(n409), .A1(intDX[29]), .B0(DmP_o[29]), .B1(n403), .Y(
n295) );
AOI22X1TS U422 ( .A0(n409), .A1(intDY[19]), .B0(DMP_o[19]), .B1(n403), .Y(
n297) );
AOI22X1TS U423 ( .A0(n409), .A1(intDX[3]), .B0(DmP_o[3]), .B1(n403), .Y(n298) );
AOI22X1TS U424 ( .A0(n404), .A1(intDY[6]), .B0(DmP_o[6]), .B1(n406), .Y(n300) );
AOI22X1TS U425 ( .A0(n404), .A1(intDY[4]), .B0(DmP_o[4]), .B1(n406), .Y(n301) );
AOI22X1TS U426 ( .A0(n404), .A1(intDX[23]), .B0(DMP_o[23]), .B1(n406), .Y(
n303) );
AOI22X1TS U427 ( .A0(n404), .A1(intDX[2]), .B0(DMP_o[2]), .B1(n406), .Y(n304) );
AOI22X1TS U428 ( .A0(n404), .A1(intDY[7]), .B0(DmP_o[7]), .B1(n406), .Y(n306) );
AOI22X1TS U429 ( .A0(n407), .A1(intDX[16]), .B0(DMP_o[16]), .B1(n406), .Y(
n307) );
AOI22X1TS U430 ( .A0(n407), .A1(intDX[22]), .B0(DMP_o[22]), .B1(n406), .Y(
n309) );
AOI22X1TS U431 ( .A0(n407), .A1(intDY[2]), .B0(DmP_o[2]), .B1(n406), .Y(n311) );
AOI22X1TS U432 ( .A0(n407), .A1(intDX[30]), .B0(DMP_o[30]), .B1(n406), .Y(
n313) );
AOI22X1TS U433 ( .A0(n407), .A1(intDX[14]), .B0(DMP_o[14]), .B1(n406), .Y(
n315) );
AOI22X1TS U434 ( .A0(n404), .A1(intDX[20]), .B0(DMP_o[20]), .B1(n406), .Y(
n316) );
AOI22X1TS U435 ( .A0(n407), .A1(intDX[18]), .B0(DMP_o[18]), .B1(n406), .Y(
n317) );
AOI22X1TS U436 ( .A0(n407), .A1(intDX[8]), .B0(DMP_o[8]), .B1(n406), .Y(n319) );
AOI22X1TS U437 ( .A0(n407), .A1(intDX[1]), .B0(DMP_o[1]), .B1(n406), .Y(n321) );
AOI22X1TS U438 ( .A0(n407), .A1(intDY[25]), .B0(DmP_o[25]), .B1(n406), .Y(
n324) );
AOI22X1TS U439 ( .A0(n404), .A1(intDY[19]), .B0(DmP_o[19]), .B1(n406), .Y(
n325) );
AOI22X1TS U440 ( .A0(n407), .A1(intDY[27]), .B0(DmP_o[27]), .B1(n406), .Y(
n326) );
AOI22X1TS U441 ( .A0(n404), .A1(intDY[21]), .B0(DmP_o[21]), .B1(n406), .Y(
n327) );
AOI22X1TS U442 ( .A0(n404), .A1(intDY[12]), .B0(DmP_o[12]), .B1(n406), .Y(
n328) );
AOI22X1TS U443 ( .A0(n407), .A1(intDX[0]), .B0(DMP_o[0]), .B1(n406), .Y(n329) );
NAND3XLTS U444 ( .A(n332), .B(n331), .C(n330), .Y(n375) );
NAND3XLTS U445 ( .A(n335), .B(n334), .C(n333), .Y(n348) );
NAND3XLTS U446 ( .A(n338), .B(n337), .C(n336), .Y(n347) );
NAND2X1TS U447 ( .A(intDX[14]), .B(n339), .Y(n341) );
NAND4BXLTS U448 ( .AN(n345), .B(n344), .C(n343), .D(n342), .Y(n346) );
NOR4XLTS U449 ( .A(n349), .B(n348), .C(n347), .D(n346), .Y(n371) );
OAI22X1TS U450 ( .A0(intDY[28]), .A1(n388), .B0(intDY[25]), .B1(n350), .Y(
n367) );
OAI22X1TS U451 ( .A0(intDY[7]), .A1(n352), .B0(intDY[21]), .B1(n351), .Y(
n353) );
AOI21X1TS U452 ( .A0(intDX[23]), .A1(n384), .B0(n353), .Y(n365) );
OAI22X1TS U453 ( .A0(intDY[5]), .A1(n358), .B0(intDY[27]), .B1(n357), .Y(
n361) );
OAI22X1TS U454 ( .A0(intDX[0]), .A1(n386), .B0(intDY[19]), .B1(n359), .Y(
n360) );
NOR4XLTS U455 ( .A(n363), .B(n362), .C(n361), .D(n360), .Y(n364) );
NOR4XLTS U456 ( .A(n369), .B(n368), .C(n367), .D(n366), .Y(n370) );
NAND4XLTS U457 ( .A(n373), .B(n372), .C(n371), .D(n370), .Y(n374) );
NOR4XLTS U458 ( .A(n377), .B(n376), .C(n375), .D(n374), .Y(n401) );
XNOR2X1TS U459 ( .A(intDY[31]), .B(intAS), .Y(n400) );
AOI21X1TS U460 ( .A0(n378), .A1(n400), .B0(n406), .Y(n379) );
AOI22X1TS U461 ( .A0(intDX[31]), .A1(n379), .B0(sign_final_result_o), .B1(
n403), .Y(n380) );
OAI31X1TS U462 ( .A0(n401), .A1(n322), .A2(n400), .B0(n380), .Y(n168) );
AOI22X1TS U463 ( .A0(n409), .A1(intDX[20]), .B0(DmP_o[20]), .B1(n406), .Y(
n381) );
AOI22X1TS U464 ( .A0(n409), .A1(intDX[23]), .B0(DmP_o[23]), .B1(n406), .Y(
n383) );
AOI22X1TS U465 ( .A0(n409), .A1(intDX[0]), .B0(DmP_o[0]), .B1(n406), .Y(n385) );
AOI22X1TS U466 ( .A0(n409), .A1(intDY[28]), .B0(DMP_o[28]), .B1(n406), .Y(
n387) );
AOI22X1TS U467 ( .A0(n409), .A1(intDY[6]), .B0(DMP_o[6]), .B1(n406), .Y(n389) );
AOI22X1TS U468 ( .A0(n409), .A1(intDY[12]), .B0(DMP_o[12]), .B1(n406), .Y(
n391) );
AOI22X1TS U469 ( .A0(n409), .A1(intDY[10]), .B0(DMP_o[10]), .B1(n406), .Y(
n393) );
AOI22X1TS U470 ( .A0(n409), .A1(intDX[13]), .B0(DmP_o[13]), .B1(n406), .Y(
n395) );
AOI22X1TS U471 ( .A0(n409), .A1(intDX[15]), .B0(DmP_o[15]), .B1(n406), .Y(
n397) );
XNOR2X1TS U472 ( .A(intDX[31]), .B(n400), .Y(real_op_o) );
CLKAND2X2TS U473 ( .A(n401), .B(real_op_o), .Y(zero_flag_o) );
AOI22X1TS U474 ( .A0(n404), .A1(intDY[9]), .B0(DmP_o[9]), .B1(n406), .Y(n402) );
OAI2BB1X1TS U475 ( .A0N(intDX[9]), .A1N(n409), .B0(n402), .Y(n158) );
AOI22X1TS U476 ( .A0(n404), .A1(intDY[14]), .B0(DmP_o[14]), .B1(n403), .Y(
n405) );
OAI2BB1X1TS U477 ( .A0N(intDX[14]), .A1N(n409), .B0(n405), .Y(n153) );
AOI22X1TS U478 ( .A0(n407), .A1(intDY[30]), .B0(DmP_o[30]), .B1(n406), .Y(
n408) );
OAI2BB1X1TS U479 ( .A0N(intDX[30]), .A1N(n409), .B0(n408), .Y(n137) );
initial $sdf_annotate("Oper_Start_In_2_syn.sdf");
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
// ----------------------------------------------------------------------
// Filename: Filename: tx_multiplexer_64.v
// Version: Version: 1.0
// Verilog Standard: Verilog-2005
// Description: the TX Multiplexer services read and write requests from
// RIFFA channels in round robin order.
// Author: Dustin Richmond (@darichmond)
// ----------------------------------------------------------------------
`define FMT_TXENGUPR64_WR32 7'b10_00000
`define FMT_TXENGUPR64_RD32 7'b00_00000
`define FMT_TXENGUPR64_WR64 7'b11_00000
`define FMT_TXENGUPR64_RD64 7'b01_00000
`define S_TXENGUPR64_MAIN_IDLE 4'b0001
`define S_TXENGUPR64_MAIN_RD 4'b0010
`define S_TXENGUPR64_MAIN_WR 4'b0100
`define S_TXENGUPR64_MAIN_WAIT 4'b1000
`define S_TXENGUPR64_CAP_RD_WR 4'b0001
`define S_TXENGUPR64_CAP_WR_RD 4'b0010
`define S_TXENGUPR64_CAP_CAP 4'b0100
`define S_TXENGUPR64_CAP_REL 4'b1000
`include "trellis.vh"
`timescale 1ns/1ns
module tx_multiplexer_64
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_NUM_CHNL = 12,
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_VENDOR = "ALTERA"
)
(
input CLK,
input RST_IN,
input [C_NUM_CHNL-1:0] WR_REQ, // Write request
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] WR_ADDR, // Write address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] WR_LEN, // Write data length
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
output [C_NUM_CHNL-1:0] WR_DATA_REN, // Write data read enable
output [C_NUM_CHNL-1:0] WR_ACK, // Write request has been accepted
input [C_NUM_CHNL-1:0] RD_REQ, // Read request
input [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL, // Read request channel for scatter gather lists
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] RD_ADDR, // Read request address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] RD_LEN, // Read request length
output [C_NUM_CHNL-1:0] RD_ACK, // Read request has been accepted
output [5:0] INT_TAG, // Internal tag to exchange with external
output INT_TAG_VALID, // High to signal tag exchange
input [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
input EXT_TAG_VALID, // High to signal external tag is valid
output TX_ENG_RD_REQ_SENT, // Read completion request issued
input RXBUF_SPACE_AVAIL,
// Interface: TXR Engine
output TXR_DATA_VALID,
output [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
output TXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
output TXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
input TXR_DATA_READY,
output TXR_META_VALID,
output [`SIG_FBE_W-1:0] TXR_META_FDWBE,
output [`SIG_LBE_W-1:0] TXR_META_LDWBE,
output [`SIG_ADDR_W-1:0] TXR_META_ADDR,
output [`SIG_LEN_W-1:0] TXR_META_LENGTH,
output [`SIG_TAG_W-1:0] TXR_META_TAG,
output [`SIG_TC_W-1:0] TXR_META_TC,
output [`SIG_ATTR_W-1:0] TXR_META_ATTR,
output [`SIG_TYPE_W-1:0] TXR_META_TYPE,
output TXR_META_EP,
input TXR_META_READY);
`include "functions.vh"
localparam C_DATA_DELAY = 6'd6; // Delays read/write params to accommodate tx_port_buffer delay and tx_engine_formatter delay.
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [3:0] rMainState=`S_TXENGUPR64_MAIN_IDLE, _rMainState=`S_TXENGUPR64_MAIN_IDLE;
reg rCountIsWr=0, _rCountIsWr=0;
reg [3:0] rCountChnl=0, _rCountChnl=0;
reg [C_TAG_WIDTH-1:0] rCountTag=0, _rCountTag=0;
reg [9:0] rCount=0, _rCount=0;
reg rCountDone=0, _rCountDone=0;
reg rCountValid=0,_rCountValid=0;
reg rCountStart=0, _rCountStart=0;
reg rCountOdd32=0, _rCountOdd32=0;
reg [9:0] rCountLen=0, _rCountLen=0;
reg [C_NUM_CHNL-1:0] rWrDataRen=0, _rWrDataRen=0;
reg rTxEngRdReqAck, _rTxEngRdReqAck;
wire wRdReq;
wire [3:0] wRdReqChnl;
wire wWrReq;
wire [3:0] wWrReqChnl;
wire wRdAck;
wire [3:0] wCountChnl;
wire [11:0] wCountChnlShiftDW = (wCountChnl*C_PCI_DATA_WIDTH); // Mult can exceed 9 bits, so make this a wire
wire [63:0] wRdAddr;
wire [9:0] wRdLen;
wire [1:0] wRdSgChnl;
wire [63:0] wWrAddr;
wire [9:0] wWrLen;
wire [C_PCI_DATA_WIDTH-1:0] wWrData;
reg [3:0] rRdChnl=0, _rRdChnl=0;
reg [61:0] rRdAddr=62'd0, _rRdAddr=62'd0;
reg [9:0] rRdLen=0, _rRdLen=0;
reg [1:0] rRdSgChnl=0, _rRdSgChnl=0;
reg [3:0] rWrChnl=0, _rWrChnl=0;
reg [61:0] rWrAddr=62'd0, _rWrAddr=62'd0;
reg [9:0] rWrLen=0, _rWrLen=0;
reg [C_PCI_DATA_WIDTH-1:0] rWrData={C_PCI_DATA_WIDTH{1'd0}}, _rWrData={C_PCI_DATA_WIDTH{1'd0}};
assign wRdAddr = RD_ADDR[wRdReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
assign wRdLen = RD_LEN[wRdReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
assign wRdSgChnl = RD_SG_CHNL[wRdReqChnl * 2 +: 2];
assign wWrAddr = WR_ADDR[wWrReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
assign wWrLen = WR_LEN[wWrReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
assign wWrData = WR_DATA[wCountChnl * C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [3:0] rCapState=`S_TXENGUPR64_CAP_RD_WR, _rCapState=`S_TXENGUPR64_CAP_RD_WR;
reg [C_NUM_CHNL-1:0] rRdAck=0, _rRdAck=0;
reg [C_NUM_CHNL-1:0] rWrAck=0, _rWrAck=0;
reg rIsWr=0, _rIsWr=0;
reg [5:0] rCapChnl=0, _rCapChnl=0;
reg [61:0] rCapAddr=62'd0, _rCapAddr=62'd0;
reg rCapAddr64=0, _rCapAddr64=0;
reg [9:0] rCapLen=0, _rCapLen=0;
reg rCapIsWr=0, _rCapIsWr=0;
reg rExtTagReq=0, _rExtTagReq=0;
reg [C_TAG_WIDTH-1:0] rExtTag=0, _rExtTag=0;
reg [C_DATA_DELAY-1:0] rWnR=0, _rWnR=0;
reg [(C_DATA_DELAY*4)-1:0] rChnl=0, _rChnl=0;
reg [(C_DATA_DELAY*8)-1:0] rTag=0, _rTag=0;
reg [(C_DATA_DELAY*62)-1:0] rAddr=0, _rAddr=0;
reg [((C_DATA_DELAY+1)*10)-1:0] rLen=0, _rLen=0;
reg [C_DATA_DELAY-1:0] rValid=0, _rValid=0;
reg [C_DATA_DELAY-1:0] rDone=0, _rDone=0;
reg [C_DATA_DELAY-1:0] rStart=0, _rStart=0;
assign WR_DATA_REN = rWrDataRen;
assign WR_ACK = rWrAck;
assign RD_ACK = rRdAck;
assign INT_TAG = {rRdSgChnl, rRdChnl};
assign INT_TAG_VALID = rExtTagReq;
assign TX_ENG_RD_REQ_SENT = rTxEngRdReqAck;
assign wRdAck = (wRdReq & EXT_TAG_VALID & RXBUF_SPACE_AVAIL);
// Search for the next request so that we can move onto it immediately after
// the current channel has released its request.
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selRd (.RST(RST_IN), .CLK(CLK), .REQ_ALL(RD_REQ), .REQ(wRdReq), .CHNL(wRdReqChnl));
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selWr (.RST(RST_IN), .CLK(CLK), .REQ_ALL(WR_REQ), .REQ(wWrReq), .CHNL(wWrReqChnl));
// Buffer shift-selected channel request signals and FIFO data.
always @ (posedge CLK) begin
rRdChnl <= #1 _rRdChnl;
rRdAddr <= #1 _rRdAddr;
rRdLen <= #1 _rRdLen;
rRdSgChnl <= #1 _rRdSgChnl;
rWrChnl <= #1 _rWrChnl;
rWrAddr <= #1 _rWrAddr;
rWrLen <= #1 _rWrLen;
rWrData <= #1 _rWrData;
end
always @ (*) begin
_rRdChnl = wRdReqChnl;
_rRdAddr = wRdAddr[63:2];
_rRdLen = wRdLen;
_rRdSgChnl = wRdSgChnl;
_rWrChnl = wWrReqChnl;
_rWrAddr = wWrAddr[63:2];
_rWrLen = wWrLen;
_rWrData = wWrData;
end
// Accept requests when the selector indicates. Capture the buffered
// request parameters for hand-off to the formatting pipeline. Then
// acknowledge the receipt to the channel so it can deassert the
// request, and let the selector choose another channel.
always @ (posedge CLK) begin
rCapState <= #1 (RST_IN ? `S_TXENGUPR64_CAP_RD_WR : _rCapState);
rRdAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rRdAck);
rWrAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rWrAck);
rIsWr <= #1 _rIsWr;
rCapChnl <= #1 _rCapChnl;
rCapAddr <= #1 _rCapAddr;
rCapAddr64 <= #1 _rCapAddr64;
rCapLen <= #1 _rCapLen;
rCapIsWr <= #1 _rCapIsWr;
rExtTagReq <= #1 _rExtTagReq;
rExtTag <= #1 _rExtTag;
rTxEngRdReqAck <= #1 _rTxEngRdReqAck;
end
always @ (*) begin
_rCapState = rCapState;
_rRdAck = rRdAck;
_rWrAck = rWrAck;
_rIsWr = rIsWr;
_rCapChnl = rCapChnl;
_rCapAddr = rCapAddr;
_rCapAddr64 = (rCapAddr[61:30] != 0);
_rCapLen = rCapLen;
_rCapIsWr = rCapIsWr;
_rExtTagReq = rExtTagReq;
_rExtTag = rExtTag;
_rTxEngRdReqAck = rTxEngRdReqAck;
case (rCapState)
`S_TXENGUPR64_CAP_RD_WR : begin
_rIsWr = !wRdReq;
_rRdAck = (wRdAck<<wRdReqChnl);
_rTxEngRdReqAck = wRdAck;
_rExtTagReq = wRdAck;
_rCapState = (wRdAck ? `S_TXENGUPR64_CAP_CAP : `S_TXENGUPR64_CAP_WR_RD);
end
`S_TXENGUPR64_CAP_WR_RD : begin
_rIsWr = wWrReq;
_rWrAck = (wWrReq<<wWrReqChnl);
_rCapState = (wWrReq ? `S_TXENGUPR64_CAP_CAP : `S_TXENGUPR64_CAP_RD_WR);
end
`S_TXENGUPR64_CAP_CAP : begin
_rTxEngRdReqAck = 0;
_rRdAck = 0;
_rWrAck = 0;
_rCapIsWr = rIsWr;
_rExtTagReq = 0;
_rExtTag = EXT_TAG;
if (rIsWr) begin
_rCapChnl = {2'd0, rWrChnl};
_rCapAddr = rWrAddr;
_rCapLen = rWrLen;
end
else begin
_rCapChnl = {rRdSgChnl, rRdChnl};
_rCapAddr = rRdAddr;
_rCapLen = rRdLen;
end
_rCapState = `S_TXENGUPR64_CAP_REL;
end
`S_TXENGUPR64_CAP_REL : begin
// Push into the formatting pipeline when ready
if (TXR_META_READY & rMainState[0]) // S_TXENGUPR64_MAIN_IDLE
_rCapState = (`S_TXENGUPR64_CAP_WR_RD>>(rCapIsWr)); // Changes to S_TXENGUPR64_CAP_RD_WR
end
default : begin
_rCapState = `S_TXENGUPR64_CAP_RD_WR;
end
endcase
end
// Start the read/write when space is available in the output FIFO and when
// request parameters have been captured (i.e. a pending request).
always @ (posedge CLK) begin
rMainState <= #1 (RST_IN ? `S_TXENGUPR64_MAIN_IDLE : _rMainState);
rCountIsWr <= #1 _rCountIsWr;
rCountLen <= #1 _rCountLen;
rCount <= #1 _rCount;
rCountDone <= #1 _rCountDone;
rCountStart <= #1 _rCountStart;
rCountChnl <= #1 _rCountChnl;
rCountTag <= #1 _rCountTag;
rCountOdd32 <= #1 _rCountOdd32;
rWrDataRen <= #1 _rWrDataRen;
rCountValid <= #1 RST_IN ? 0 : _rCountValid;
end
always @ (*) begin
_rMainState = rMainState;
_rCountIsWr = rCountIsWr;
_rCount = rCount;
_rCountLen = rCountLen;
_rCountDone = rCountDone;
_rCountStart = rCountStart;
_rCountChnl = rCountChnl;
_rCountTag = rCountTag;
_rCountOdd32 = rCountOdd32;
_rWrDataRen = rWrDataRen;
_rCountStart = 0;
_rCountValid = rCountValid;
case (rMainState)
`S_TXENGUPR64_MAIN_IDLE : begin
_rCountIsWr = rCapIsWr;
_rCountLen = rCapLen;
_rCount = rCapLen;
_rCountDone = (rCapLen <= 2'd2);
_rCountChnl = rCapChnl[3:0];
_rCountTag = rExtTag;
_rCountOdd32 = (rCapLen[0] & ((rCapAddr[61:30] == 0)));
_rWrDataRen = ((TXR_META_READY & rCapState[3] & rCapIsWr)<<(rCapChnl[3:0])); // S_TXENGUPR64_CAP_REL
_rCountStart = (TXR_META_READY & rCapState[3]);
_rCountValid = TXR_META_READY & rCapState[3];
if (TXR_META_READY & rCapState[3]) // S_TXENGUPR64_CAP_REL
_rMainState = (`S_TXENGUPR64_MAIN_RD<<(rCapIsWr)); // Change to S_TXENGUPR64_MAIN_WR;
end
`S_TXENGUPR64_MAIN_RD : begin
_rMainState = `S_TXENGUPR64_MAIN_IDLE;
end
`S_TXENGUPR64_MAIN_WR : begin
_rCount = rCount - 2'd2;
_rCountDone = (rCount <= 3'd4);
if (rCountDone) begin
_rWrDataRen = 0;
_rCountValid = 0;
_rMainState = (rCountOdd32 ? `S_TXENGUPR64_MAIN_IDLE : `S_TXENGUPR64_MAIN_WAIT);
end
end
`S_TXENGUPR64_MAIN_WAIT : begin // Signals request FIFO ren
_rMainState = `S_TXENGUPR64_MAIN_IDLE;
end
default : begin
_rMainState = `S_TXENGUPR64_MAIN_IDLE;
end
endcase
end
// Shift in the captured parameters and valid signal every cycle.
// This pipeline will keep the formatter busy.
assign wCountChnl = rChnl[(C_DATA_DELAY-2)*4 +:4];
always @ (posedge CLK) begin
rWnR <= #1 _rWnR;
rChnl <= #1 _rChnl;
rTag <= #1 _rTag;
rAddr <= #1 _rAddr;
rLen <= #1 _rLen;
rValid <= #1 _rValid;
rDone <= #1 _rDone;
rStart <= #1 _rStart;
end
always @ (*) begin
_rWnR = {rWnR[((C_DATA_DELAY-1)*1)-1:0], rCapIsWr};
_rAddr = {rAddr[((C_DATA_DELAY-1)*62)-1:0], rCapAddr};
_rLen = {rLen[((C_DATA_DELAY-1)*10)-1:0], rCountLen};
_rChnl = {rChnl[((C_DATA_DELAY-1)*4)-1:0], rCountChnl};
_rTag = {rTag[((C_DATA_DELAY-1)*8)-1:0], (8'd0 | rCountTag)};
_rValid = {rValid[((C_DATA_DELAY-1)*1)-1:0], rCountValid & rCountIsWr}; // S_TXENGUPR64_MAIN_RD | S_TXENGUPR64_MAIN_WR
_rDone = {rDone[((C_DATA_DELAY-1)*1)-1:0], rCountDone};
_rStart = {rStart[((C_DATA_DELAY-1)*1)-1:0], rCountStart};
end
assign TXR_DATA = rWrData;
assign TXR_DATA_VALID = rValid[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_START_FLAG = rStart[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_START_OFFSET = 0;
assign TXR_DATA_END_FLAG = rDone[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_END_OFFSET = rLen[(C_DATA_DELAY-1)*10 +:`SIG_OFFSET_W] - 1;
assign TXR_META_VALID = rCountStart;
assign TXR_META_TYPE = rCapIsWr ? `TRLS_REQ_WR : `TRLS_REQ_RD;
assign TXR_META_ADDR = {rCapAddr,2'b00};
assign TXR_META_LENGTH = rCapLen;
assign TXR_META_LDWBE = rCapLen == 10'd1 ? 0 : 4'b1111; // TODO: This should be retimed
assign TXR_META_FDWBE = 4'b1111;
assign TXR_META_TAG = rCountTag;
assign TXR_META_EP = 1'b0;
assign TXR_META_ATTR = 3'b110;
assign TXR_META_TC = 0;
endmodule
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the encoder
// Import the modules that will be tested for in this testbench
`include "encoder.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_encoder();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [14:0] cout;
// Declare "reg" signals: inputs to the DUT
reg [10:0] b;
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
ham_15_11_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
b,cout);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
b = 11'b11010110000;
$display(b[1]," << b1 b2 >>",b[2]);
$display(b[3]," << b1 b2 >>",b[4]);
// @ t=0,
#1;
b = 11'b11100011100;
#1;
b = 11'b11001110101;
#1;
b = 11'b11110111001;
#1;
b = 11'b11111000010;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
`include "Global_Macros.v"
`define ADR_WIDTH 16
`define DAT_WIDTH 8
`define MEM_WIDTH 8
`define MEM_DEPTH 2**`ADR_WIDTH
module Memory(
clk_i,
we_i,
if_cnt_i,
w_cnt_i,
w_dat_i,
w_adr_i,
inst_adr_i,
if_adr_i,
ea_adr_i,
rd_adr_i,
stl_o,
inst_o,
if_dat_o,
ea_dat_o,
rd_dat_o
`ifdef DEBUG
,debug_o
`endif
);
//Input signals :
input wire clk_i;
input wire we_i;
input wire [1:0] if_cnt_i;
input wire [1:0] w_cnt_i;
input wire [3 * `DAT_WIDTH - 1:0] w_dat_i;
input wire [`ADR_WIDTH - 1:0] w_adr_i;
input wire [`ADR_WIDTH - 1:0] inst_adr_i;
input wire [`ADR_WIDTH - 1:0] if_adr_i;
input wire [`ADR_WIDTH - 1:0] ea_adr_i;
input wire [`ADR_WIDTH - 1:0] rd_adr_i;
//Output signals :
output reg stl_o;
output wire [1 * `DAT_WIDTH - 1:0] inst_o;
output wire [3 * `DAT_WIDTH - 1:0] if_dat_o;
output wire [2 * `DAT_WIDTH - 1:0] ea_dat_o;
output wire [1 * `DAT_WIDTH - 1:0] rd_dat_o;
`ifdef DEBUG
output wire [`MEM_DBG_WIDTH - 1:0] debug_o;
`endif
//Internal registers :
reg [1:0] w_cnt;
reg [`ADR_WIDTH - 1:0] w_adr;
reg [3 * `DAT_WIDTH - 1:0] w_dat;
//MEM :
reg [`MEM_WIDTH - 1:0] MEM [0:`MEM_DEPTH - 1];
//Assignments :
assign inst_o = MEM[inst_adr_i];
assign if_dat_o = (if_cnt_i == 2'h1) ? {16'hFFFF, MEM[if_adr_i]} :
(if_cnt_i == 2'h2) ? {8'hFF, MEM[if_adr_i + 1], MEM[if_adr_i]} :
(if_cnt_i == 2'h3) ? {MEM[if_adr_i + 2], MEM[if_adr_i + 1], MEM[if_adr_i]} : if_dat_o;
assign ea_dat_o = {MEM[ea_adr_i + 1], MEM[ea_adr_i]};
assign rd_dat_o = MEM[rd_adr_i];
`ifdef DEBUG
assign debug_o = {8'h0, MEM[inst_adr_i]};
`endif
//Blocks :
initial
begin
//PC Space
MEM[65532] = 8'h2E;
MEM[65533] = 8'h80;
MEM[32814] = `LDY_IME;
MEM[32815] = 8'h07;
MEM[32816] = `LDA_IME;
MEM[32817] = 8'h00;
MEM[32818] = `STA_ABS;
MEM[32819] = 8'h03;
MEM[32820] = 8'h00;
MEM[32821] = `LDA_IME;
MEM[32822] = 8'h01;
MEM[32823] = `TAX;
MEM[32824] = `ADC_ABS;
MEM[32825] = 8'h03;
MEM[32826] = 8'h00;
MEM[32827] = `STX_ABS;
MEM[32828] = 8'h03;
MEM[32829] = 8'h00;
MEM[32830] = `DEY;
MEM[32831] = `BNE;
MEM[32832] = 8'hF6;
end
always @(posedge clk_i)
begin
if(we_i || stl_o)
begin
if(w_cnt_i > 2'h1 || stl_o == 1'h1)
begin
if(stl_o == 1'h0)
begin
stl_o <= 1'h1;
w_cnt <= w_cnt_i;
w_dat <= w_dat_i;
w_adr <= w_adr_i;
end
else if(w_cnt > 2'h1 && stl_o == 1'h1)
begin
w_cnt <= w_cnt - 2'h1;
w_dat <= w_dat >> 4'h8;
MEM[w_adr + w_cnt - 2'h1] <= w_dat[7:0];
end
else
begin
stl_o <= 1'h0;
MEM[w_adr + w_cnt - 2'h1] <= w_dat[7:0];
end
end
else
begin
stl_o <= 1'h0;
MEM[w_adr_i] <= w_dat_i;
end
end
end
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:42:42 05/12/2015
// Design Name:
// Module Name: inverse_perm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module inverse_perm(
left,
right,
cipher
);
input [32:1] left;
input [32:1] right;
output reg [64:1] cipher;
wire [64:1] left_ryt ;
assign left_ryt = {right,left}; //teta5d mn 16
always @(left_ryt)
begin
cipher[1] <= left_ryt[40];
cipher[2] <= left_ryt[8];
cipher[3] <= left_ryt[48];
cipher[4] <= left_ryt[16];
cipher[5] <= left_ryt[56];
cipher[6] <= left_ryt[24];
cipher[7] <= left_ryt[64];
cipher[8] <= left_ryt[32];
cipher[9] <= left_ryt[39];
cipher[10] <= left_ryt[7];
cipher[11] <= left_ryt[47];
cipher[12] <= left_ryt[15];
cipher[13] <= left_ryt[55];
cipher[14] <= left_ryt[23];
cipher[15] <= left_ryt[63];
cipher[16] <= left_ryt[31];
cipher[17] <= left_ryt[38];
cipher[18] <= left_ryt[6];
cipher[19] <= left_ryt[46];
cipher[20] <= left_ryt[14];
cipher[21] <= left_ryt[54];
cipher[22] <= left_ryt[22];
cipher[23] <= left_ryt[62];
cipher[24] <= left_ryt[30];
cipher[25] <= left_ryt[37];
cipher[26] <= left_ryt[5];
cipher[27] <= left_ryt[45];
cipher[28] <= left_ryt[13];
cipher[29] <= left_ryt[53];
cipher[30] <= left_ryt[21];
cipher[31] <= left_ryt[61];
cipher[32] <= left_ryt[29];
cipher[33] <= left_ryt[36];
cipher[34] <= left_ryt[4];
cipher[35] <= left_ryt[44];
cipher[36] <= left_ryt[12];
cipher[37] <= left_ryt[52];
cipher[38] <= left_ryt[20];
cipher[39] <= left_ryt[60];
cipher[40] <= left_ryt[28];
cipher[41] <= left_ryt[35];
cipher[42] <= left_ryt[3];
cipher[43] <= left_ryt[43];
cipher[44] <= left_ryt[11];
cipher[45] <= left_ryt[51];
cipher[46] <= left_ryt[19];
cipher[47] <= left_ryt[59];
cipher[48] <= left_ryt[27];
cipher[49] <= left_ryt[34];
cipher[50] <= left_ryt[2];
cipher[51] <= left_ryt[42];
cipher[52] <= left_ryt[10];
cipher[53] <= left_ryt[50];
cipher[54] <= left_ryt[18];
cipher[55] <= left_ryt[58];
cipher[56] <= left_ryt[26];
cipher[57] <= left_ryt[33];
cipher[58] <= left_ryt[1];
cipher[59] <= left_ryt[41];
cipher[60] <= left_ryt[9];
cipher[61] <= left_ryt[49];
cipher[62] <= left_ryt[17];
cipher[63] <= left_ryt[57];
cipher[64] <= left_ryt[25];
end
endmodule
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
// Depth 1 FIFO data size 0!
module FIFO10(CLK,
RST,
ENQ,
FULL_N,
DEQ,
EMPTY_N,
CLR
);
parameter guarded = 1;
input CLK;
input RST;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output EMPTY_N;
reg empty_reg ;
assign EMPTY_N = empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
empty_reg = 1'b0;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg;
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFO10: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: FIFO10: %m -- Enqueuing to a full fifo" ) ;
end
end // if (RST == ! `BSV_RESET_VALUE)
end
// synopsys translate_on
endmodule
|
// file: dcm.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___333.333______0.000______50.0______260.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "dcm,clk_wiz_v3_6,{component_name=dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module dcm
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (3),
.CLKFX_MULTIPLY (10),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("NONE"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (RESET),
// Unused pin- tie low
.DSSEN (1'b0));
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
// no phase alignment active, connect to ground
assign clkfb = 1'b0;
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBEC_P_PP_SYMBOL_V
`define SKY130_FD_SC_HD__PROBEC_P_PP_SYMBOL_V
/**
* probec_p: Virtual current probe point.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__probec_p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBEC_P_PP_SYMBOL_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:30 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub
// /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_rst_ps7_0_100M_0/ip_design_rst_ps7_0_100M_0_stub.v
// Design : ip_design_rst_ps7_0_100M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2017.3" *)
module ip_design_rst_ps7_0_100M_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: sum.v
// /___/ /\ Timestamp: Tue Mar 24 21:00:40 2015
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/abc/src/sum/tmp/_cg/sum.ngc C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/abc/src/sum/tmp/_cg/sum.v
// Device : xa7a100tcsg324-2i
// Input file : C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/abc/src/sum/tmp/_cg/sum.ngc
// Output file : C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/abc/src/sum/tmp/_cg/sum.v
// # of Modules : 1
// Design Name : sum
// Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module sum (
clk, ce, a, b, s
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input ce;
input [11 : 0] a;
input [11 : 0] b;
output [12 : 0] s;
// synthesis translate_off
wire \blk00000001/sig00000070 ;
wire \blk00000001/sig0000006f ;
wire \blk00000001/sig0000006e ;
wire \blk00000001/sig0000006d ;
wire \blk00000001/sig0000006c ;
wire \blk00000001/sig0000006b ;
wire \blk00000001/sig0000006a ;
wire \blk00000001/sig00000069 ;
wire \blk00000001/sig00000068 ;
wire \blk00000001/sig00000067 ;
wire \blk00000001/sig00000066 ;
wire \blk00000001/sig00000065 ;
wire \blk00000001/sig00000064 ;
wire \blk00000001/sig00000063 ;
wire \blk00000001/sig00000062 ;
wire \blk00000001/sig00000061 ;
wire \blk00000001/sig00000060 ;
wire \blk00000001/sig0000005f ;
wire \blk00000001/sig0000005e ;
wire \blk00000001/sig0000005d ;
wire \blk00000001/sig0000005c ;
wire \blk00000001/sig0000005b ;
wire \blk00000001/sig0000005a ;
wire \blk00000001/sig00000059 ;
wire \blk00000001/sig00000058 ;
wire \blk00000001/sig00000057 ;
wire \blk00000001/sig00000056 ;
wire \blk00000001/sig00000055 ;
wire \blk00000001/sig00000054 ;
wire \blk00000001/sig00000053 ;
wire \blk00000001/sig00000052 ;
wire \blk00000001/sig00000051 ;
wire \blk00000001/sig00000050 ;
wire \blk00000001/sig0000004f ;
wire \blk00000001/sig0000004e ;
wire \blk00000001/sig0000004d ;
wire \blk00000001/sig0000004c ;
wire \blk00000001/sig0000004b ;
wire \blk00000001/sig0000004a ;
wire \blk00000001/sig00000049 ;
wire \blk00000001/sig00000048 ;
wire \blk00000001/sig00000047 ;
wire \blk00000001/sig00000046 ;
wire \blk00000001/sig00000045 ;
wire \blk00000001/sig00000044 ;
wire \blk00000001/sig00000043 ;
wire \blk00000001/sig00000042 ;
wire \blk00000001/sig00000041 ;
wire \blk00000001/sig00000040 ;
wire \blk00000001/sig0000003f ;
wire \blk00000001/sig0000003e ;
wire \blk00000001/sig0000003d ;
wire \blk00000001/sig0000003c ;
wire \blk00000001/sig0000003b ;
wire \blk00000001/sig0000003a ;
wire \blk00000001/sig00000039 ;
wire \blk00000001/sig00000038 ;
wire \blk00000001/sig00000037 ;
wire \blk00000001/sig00000036 ;
wire \blk00000001/sig00000035 ;
wire \blk00000001/sig00000034 ;
wire \blk00000001/sig00000033 ;
wire \blk00000001/sig00000032 ;
wire \blk00000001/sig00000031 ;
wire \blk00000001/sig00000030 ;
wire \blk00000001/sig0000002f ;
wire \blk00000001/sig0000002e ;
wire \blk00000001/sig0000002d ;
wire \blk00000001/sig0000002c ;
wire \blk00000001/sig0000002b ;
wire \blk00000001/sig0000002a ;
wire \blk00000001/sig00000029 ;
wire \blk00000001/sig00000028 ;
wire \NLW_blk00000001/blk00000057_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000055_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000053_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000051_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000031_O_UNCONNECTED ;
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000058 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000070 ),
.Q(s[1])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000057 (
.A0(\blk00000001/sig00000028 ),
.A1(\blk00000001/sig00000028 ),
.A2(\blk00000001/sig00000028 ),
.A3(\blk00000001/sig00000028 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000036 ),
.Q(\blk00000001/sig00000070 ),
.Q15(\NLW_blk00000001/blk00000057_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000056 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006f ),
.Q(s[2])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000055 (
.A0(\blk00000001/sig00000028 ),
.A1(\blk00000001/sig00000028 ),
.A2(\blk00000001/sig00000028 ),
.A3(\blk00000001/sig00000028 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000035 ),
.Q(\blk00000001/sig0000006f ),
.Q15(\NLW_blk00000001/blk00000055_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000054 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006e ),
.Q(s[0])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000053 (
.A0(\blk00000001/sig00000028 ),
.A1(\blk00000001/sig00000028 ),
.A2(\blk00000001/sig00000028 ),
.A3(\blk00000001/sig00000028 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000031 ),
.Q(\blk00000001/sig0000006e ),
.Q15(\NLW_blk00000001/blk00000053_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000052 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006d ),
.Q(s[4])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000051 (
.A0(\blk00000001/sig00000028 ),
.A1(\blk00000001/sig00000028 ),
.A2(\blk00000001/sig00000028 ),
.A3(\blk00000001/sig00000028 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000033 ),
.Q(\blk00000001/sig0000006d ),
.Q15(\NLW_blk00000001/blk00000051_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000050 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006c ),
.Q(s[5])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000004f (
.A0(\blk00000001/sig00000028 ),
.A1(\blk00000001/sig00000028 ),
.A2(\blk00000001/sig00000028 ),
.A3(\blk00000001/sig00000028 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000032 ),
.Q(\blk00000001/sig0000006c ),
.Q15(\NLW_blk00000001/blk0000004f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000006b ),
.Q(s[3])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000004d (
.A0(\blk00000001/sig00000028 ),
.A1(\blk00000001/sig00000028 ),
.A2(\blk00000001/sig00000028 ),
.A3(\blk00000001/sig00000028 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000034 ),
.Q(\blk00000001/sig0000006b ),
.Q15(\NLW_blk00000001/blk0000004d_Q15_UNCONNECTED )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000004c (
.I0(\blk00000001/sig00000029 ),
.O(\blk00000001/sig0000006a )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000004b (
.I0(\blk00000001/sig0000002a ),
.O(\blk00000001/sig00000069 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk0000004a (
.I0(\blk00000001/sig0000002b ),
.O(\blk00000001/sig00000068 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000049 (
.I0(\blk00000001/sig0000002f ),
.O(\blk00000001/sig00000067 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000048 (
.I0(\blk00000001/sig0000002c ),
.O(\blk00000001/sig00000066 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000047 (
.I0(\blk00000001/sig0000002d ),
.O(\blk00000001/sig00000065 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000046 (
.I0(\blk00000001/sig0000002e ),
.O(\blk00000001/sig00000064 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000045 (
.I0(a[11]),
.I1(b[11]),
.O(\blk00000001/sig00000063 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000044 (
.I0(a[11]),
.I1(b[11]),
.O(\blk00000001/sig0000004a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000043 (
.I0(a[10]),
.I1(b[10]),
.O(\blk00000001/sig0000004b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000042 (
.I0(a[9]),
.I1(b[9]),
.O(\blk00000001/sig0000004c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000041 (
.I0(a[8]),
.I1(b[8]),
.O(\blk00000001/sig0000004d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000040 (
.I0(a[7]),
.I1(b[7]),
.O(\blk00000001/sig0000004e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003f (
.I0(a[6]),
.I1(b[6]),
.O(\blk00000001/sig0000004f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003e (
.I0(a[5]),
.I1(b[5]),
.O(\blk00000001/sig0000003b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003d (
.I0(a[4]),
.I1(b[4]),
.O(\blk00000001/sig00000037 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003c (
.I0(a[3]),
.I1(b[3]),
.O(\blk00000001/sig00000038 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003b (
.I0(a[2]),
.I1(b[2]),
.O(\blk00000001/sig00000039 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a (
.I0(a[1]),
.I1(b[1]),
.O(\blk00000001/sig0000003a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000039 (
.I0(a[0]),
.I1(b[0]),
.O(\blk00000001/sig0000003c )
);
MUXCY \blk00000001/blk00000038 (
.CI(\blk00000001/sig00000030 ),
.DI(\blk00000001/sig00000028 ),
.S(\blk00000001/sig0000006a ),
.O(\blk00000001/sig00000062 )
);
XORCY \blk00000001/blk00000037 (
.CI(\blk00000001/sig00000030 ),
.LI(\blk00000001/sig0000006a ),
.O(\blk00000001/sig00000061 )
);
MUXCY \blk00000001/blk00000036 (
.CI(\blk00000001/sig00000062 ),
.DI(\blk00000001/sig00000028 ),
.S(\blk00000001/sig00000069 ),
.O(\blk00000001/sig00000060 )
);
XORCY \blk00000001/blk00000035 (
.CI(\blk00000001/sig00000062 ),
.LI(\blk00000001/sig00000069 ),
.O(\blk00000001/sig0000005f )
);
MUXCY \blk00000001/blk00000034 (
.CI(\blk00000001/sig00000060 ),
.DI(\blk00000001/sig00000028 ),
.S(\blk00000001/sig00000068 ),
.O(\blk00000001/sig0000005e )
);
XORCY \blk00000001/blk00000033 (
.CI(\blk00000001/sig00000060 ),
.LI(\blk00000001/sig00000068 ),
.O(\blk00000001/sig0000005d )
);
XORCY \blk00000001/blk00000032 (
.CI(\blk00000001/sig00000057 ),
.LI(\blk00000001/sig00000067 ),
.O(\blk00000001/sig0000005c )
);
MUXCY \blk00000001/blk00000031 (
.CI(\blk00000001/sig00000057 ),
.DI(\blk00000001/sig00000028 ),
.S(\blk00000001/sig00000067 ),
.O(\NLW_blk00000001/blk00000031_O_UNCONNECTED )
);
MUXCY \blk00000001/blk00000030 (
.CI(\blk00000001/sig0000005e ),
.DI(\blk00000001/sig00000028 ),
.S(\blk00000001/sig00000066 ),
.O(\blk00000001/sig0000005b )
);
XORCY \blk00000001/blk0000002f (
.CI(\blk00000001/sig0000005e ),
.LI(\blk00000001/sig00000066 ),
.O(\blk00000001/sig0000005a )
);
MUXCY \blk00000001/blk0000002e (
.CI(\blk00000001/sig0000005b ),
.DI(\blk00000001/sig00000028 ),
.S(\blk00000001/sig00000065 ),
.O(\blk00000001/sig00000059 )
);
XORCY \blk00000001/blk0000002d (
.CI(\blk00000001/sig0000005b ),
.LI(\blk00000001/sig00000065 ),
.O(\blk00000001/sig00000058 )
);
MUXCY \blk00000001/blk0000002c (
.CI(\blk00000001/sig00000059 ),
.DI(\blk00000001/sig00000028 ),
.S(\blk00000001/sig00000064 ),
.O(\blk00000001/sig00000057 )
);
XORCY \blk00000001/blk0000002b (
.CI(\blk00000001/sig00000059 ),
.LI(\blk00000001/sig00000064 ),
.O(\blk00000001/sig00000056 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000005c ),
.Q(s[12])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000029 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000056 ),
.Q(s[11])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000028 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000058 ),
.Q(s[10])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000027 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000005a ),
.Q(s[9])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000026 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000005d ),
.Q(s[8])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000025 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000005f ),
.Q(s[7])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000024 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000061 ),
.Q(s[6])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000023 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000043 ),
.Q(\blk00000001/sig00000029 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000022 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000049 ),
.Q(\blk00000001/sig0000002a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000021 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000048 ),
.Q(\blk00000001/sig0000002b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000020 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000047 ),
.Q(\blk00000001/sig0000002c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000046 ),
.Q(\blk00000001/sig0000002d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000045 ),
.Q(\blk00000001/sig0000002e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000044 ),
.Q(\blk00000001/sig0000002f )
);
MUXCY \blk00000001/blk0000001c (
.CI(\blk00000001/sig00000028 ),
.DI(a[6]),
.S(\blk00000001/sig0000004f ),
.O(\blk00000001/sig00000055 )
);
MUXCY \blk00000001/blk0000001b (
.CI(\blk00000001/sig00000055 ),
.DI(a[7]),
.S(\blk00000001/sig0000004e ),
.O(\blk00000001/sig00000054 )
);
MUXCY \blk00000001/blk0000001a (
.CI(\blk00000001/sig00000054 ),
.DI(a[8]),
.S(\blk00000001/sig0000004d ),
.O(\blk00000001/sig00000053 )
);
MUXCY \blk00000001/blk00000019 (
.CI(\blk00000001/sig00000053 ),
.DI(a[9]),
.S(\blk00000001/sig0000004c ),
.O(\blk00000001/sig00000052 )
);
MUXCY \blk00000001/blk00000018 (
.CI(\blk00000001/sig00000052 ),
.DI(a[10]),
.S(\blk00000001/sig0000004b ),
.O(\blk00000001/sig00000051 )
);
MUXCY \blk00000001/blk00000017 (
.CI(\blk00000001/sig00000051 ),
.DI(a[11]),
.S(\blk00000001/sig00000063 ),
.O(\blk00000001/sig00000050 )
);
XORCY \blk00000001/blk00000016 (
.CI(\blk00000001/sig00000055 ),
.LI(\blk00000001/sig0000004e ),
.O(\blk00000001/sig00000049 )
);
XORCY \blk00000001/blk00000015 (
.CI(\blk00000001/sig00000054 ),
.LI(\blk00000001/sig0000004d ),
.O(\blk00000001/sig00000048 )
);
XORCY \blk00000001/blk00000014 (
.CI(\blk00000001/sig00000053 ),
.LI(\blk00000001/sig0000004c ),
.O(\blk00000001/sig00000047 )
);
XORCY \blk00000001/blk00000013 (
.CI(\blk00000001/sig00000052 ),
.LI(\blk00000001/sig0000004b ),
.O(\blk00000001/sig00000046 )
);
XORCY \blk00000001/blk00000012 (
.CI(\blk00000001/sig00000051 ),
.LI(\blk00000001/sig00000063 ),
.O(\blk00000001/sig00000045 )
);
XORCY \blk00000001/blk00000011 (
.CI(\blk00000001/sig00000050 ),
.LI(\blk00000001/sig0000004a ),
.O(\blk00000001/sig00000044 )
);
XORCY \blk00000001/blk00000010 (
.CI(\blk00000001/sig00000028 ),
.LI(\blk00000001/sig0000004f ),
.O(\blk00000001/sig00000043 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000041 ),
.Q(\blk00000001/sig00000030 )
);
MUXCY \blk00000001/blk0000000e (
.CI(\blk00000001/sig00000028 ),
.DI(a[0]),
.S(\blk00000001/sig0000003c ),
.O(\blk00000001/sig00000042 )
);
MUXCY \blk00000001/blk0000000d (
.CI(\blk00000001/sig0000003d ),
.DI(a[5]),
.S(\blk00000001/sig0000003b ),
.O(\blk00000001/sig00000041 )
);
MUXCY \blk00000001/blk0000000c (
.CI(\blk00000001/sig00000042 ),
.DI(a[1]),
.S(\blk00000001/sig0000003a ),
.O(\blk00000001/sig00000040 )
);
MUXCY \blk00000001/blk0000000b (
.CI(\blk00000001/sig00000040 ),
.DI(a[2]),
.S(\blk00000001/sig00000039 ),
.O(\blk00000001/sig0000003f )
);
MUXCY \blk00000001/blk0000000a (
.CI(\blk00000001/sig0000003f ),
.DI(a[3]),
.S(\blk00000001/sig00000038 ),
.O(\blk00000001/sig0000003e )
);
MUXCY \blk00000001/blk00000009 (
.CI(\blk00000001/sig0000003e ),
.DI(a[4]),
.S(\blk00000001/sig00000037 ),
.O(\blk00000001/sig0000003d )
);
XORCY \blk00000001/blk00000008 (
.CI(\blk00000001/sig00000042 ),
.LI(\blk00000001/sig0000003a ),
.O(\blk00000001/sig00000036 )
);
XORCY \blk00000001/blk00000007 (
.CI(\blk00000001/sig00000040 ),
.LI(\blk00000001/sig00000039 ),
.O(\blk00000001/sig00000035 )
);
XORCY \blk00000001/blk00000006 (
.CI(\blk00000001/sig0000003f ),
.LI(\blk00000001/sig00000038 ),
.O(\blk00000001/sig00000034 )
);
XORCY \blk00000001/blk00000005 (
.CI(\blk00000001/sig0000003e ),
.LI(\blk00000001/sig00000037 ),
.O(\blk00000001/sig00000033 )
);
XORCY \blk00000001/blk00000004 (
.CI(\blk00000001/sig0000003d ),
.LI(\blk00000001/sig0000003b ),
.O(\blk00000001/sig00000032 )
);
XORCY \blk00000001/blk00000003 (
.CI(\blk00000001/sig00000028 ),
.LI(\blk00000001/sig0000003c ),
.O(\blk00000001/sig00000031 )
);
GND \blk00000001/blk00000002 (
.G(\blk00000001/sig00000028 )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
`timescale 1 ns / 1 ps
`include "hapara_bram_dma_switch_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module hapara_bram_dma_switch_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
`ifndef _sixbitmul_incl
`define _sixbitmul_incl
`include "sixbitadd.v"
`include "sixbitsub.v"
module fifteenbitadd (a, b, sum, overflow);
input[14:0] a;
input[14:0] b;
output[14:0] sum;
output overflow;
wire[14:0] carry;
fulladder fad1 (a[0], b[0], 0, carry[0], sum[0]);
fulladder fad2 (a[1], b[1], carry[0], carry[1], sum[1]);
fulladder fad3 (a[2], b[2], carry[1], carry[2], sum[2]);
fulladder fad4 (a[3], b[3], carry[2], carry[3], sum[3]);
fulladder fad5 (a[4], b[4], carry[3], carry[4], sum[4]);
fulladder fad6 (a[5], b[5], carry[4], carry[5], sum[5]);
fulladder fad7 (a[6], b[6], carry[5], carry[6], sum[6]);
fulladder fad8 (a[7], b[7], carry[6], carry[7], sum[7]);
fulladder fad9 (a[8], b[8], carry[7], carry[8], sum[8]);
fulladder fad10 (a[9], b[9], carry[8], carry[9], sum[9]);
fulladder fad11 (a[10], b[10], carry[9], carry[10], sum[10]);
fulladder fad12 (a[11], b[11], carry[10], carry[11], sum[11]);
fulladder fad13 (a[12], b[12], carry[11], carry[12], sum[12]);
fulladder fad14 (a[13], b[13], carry[12], carry[13], sum[13]);
fulladder fad15 (a[13], b[13], carry[13], overflow, sum[14]);
endmodule
module sixbitmul (ain, bin, prod, overflow);
input[5:0] ain;
input[5:0] bin;
output[5:0] prod;
output overflow;
wire[14:0] a;
wire[14:0] s;
wire[14:0] p;
wire[14:0] pa1;
wire[14:0] pa2;
wire[14:0] pa3;
wire[14:0] pa4;
wire[14:0] pa5;
wire[14:0] pa6;
wire[14:0] pa7;
wire[14:0] ps1;
wire[14:0] ps2;
wire[14:0] ps3;
wire[14:0] ps4;
wire[14:0] ps5;
wire[14:0] ps6;
wire[14:0] ps7;
wire[14:0] midres1;
wire[14:0] midres2;
wire[14:0] midres3;
wire[14:0] midres4;
wire[14:0] midres5;
wire[14:0] midres6;
wire[14:0] res;
wire[13:0] int_overflow;
assign a[14:8] = {ain[5], ain};
assign s[14:8] = ~{ain[5], ain} + 1;
assign p[7:1] = {bin[5], bin};
assign a[7:0] = 0;
assign s[7:0] = 0;
assign p[14:8] = 0;
assign p[0] = 0;
fifteenbitadd ad1 (p, a, pa1, int_overflow[0]);
fifteenbitadd ad2 (p, s, ps1, int_overflow[1]);
assign midres1[13:0] = ((p[1] ^ p[0]) ? p[0] ? pa1 : ps1 : p) >> 1;
assign midres1[14] = midres1[13];
fifteenbitadd ad3 (midres1, a, pa2, int_overflow[2]);
fifteenbitadd ad4 (midres1, s, ps2, int_overflow[3]);
assign midres2[13:0] = ((midres1[1] ^ midres1[0]) ? midres1[0] ? pa2 : ps2 : midres1) >> 1;
assign midres2[14] = midres2[13];
fifteenbitadd ad5 (midres2, a, pa3, int_overflow[4]);
fifteenbitadd ad6 (midres2, s, ps3, int_overflow[5]);
assign midres3[13:0] = ((midres2[1] ^ midres2[0]) ? midres2[0] ? pa3 : ps3 : midres2) >> 1;
assign midres3[14] = midres3[13];
fifteenbitadd ad7 (midres3, a, pa4, int_overflow[6]);
fifteenbitadd ad8 (midres3, s, ps4, int_overflow[7]);
assign midres4[13:0] = ((midres3[1] ^ midres3[0]) ? midres3[0] ? pa4 : ps4 : midres3) >> 1;
assign midres4[14] = midres4[13];
fifteenbitadd ad9 (midres4, a, pa5, int_overflow[8]);
fifteenbitadd ad10 (midres4, s, ps5, int_overflow[9]);
assign midres5[13:0] = ((midres4[1] ^ midres4[0]) ? midres4[0] ? pa5 : ps5 : midres4) >> 1;
assign midres5[14] = midres5[13];
fifteenbitadd ad11 (midres5, a, pa6, int_overflow[10]);
fifteenbitadd ad12 (midres5, s, ps6, int_overflow[11]);
assign midres6[13:0] = ((midres5[1] ^ midres5[0]) ? midres5[0] ? pa6 : ps6: midres5) >> 1;
assign midres6[14] = midres6[13];
fifteenbitadd ad13 (midres6, a, pa7, int_overflow[12]);
fifteenbitadd ad14 (midres6, s, ps7, int_overflow[13]);
assign res[13:0] = ((midres6[1] ^ midres6[0]) ? midres6[0] ? pa7 : ps7: midres6) >> 1;
assign res[14] = res[13];
assign prod = res[6:1];
wire[2:0] chkovf;
and(chkovf[0], res[14], res[13], res[12], res[11], res[10], res[9], res[8], res[7]);
or(chkovf[1], res[14], res[13], res[12], res[11], res[10], res[9], res[8], res[7]);
xor(chkovf[2], chkovf[0], chkovf[1]);
wire[2:0] chksign;
xor(chksign[0], ain[5], bin[5]);
xor(chksign[1], ain[5], res[12]);
xor(chksign[2], bin[5], res[12]);
wire overflow_ncz;
or(overflow_ncz, chkovf[2], chksign[0] ? !res[12] : (chksign[1] ^ chksign[2]));
wire[1:0] iszero;
nor(iszero[0], ain[0], ain[1], ain[2], ain[3], ain[4], ain[5]);
nor(iszero[1], bin[0], bin[1], bin[2], bin[3], bin[4], bin[5]);
and(overflow, overflow_ncz, !iszero[0], !iszero[1]);
endmodule
`endif |
module wave_gen_string(
input [5:0] ramp,
output reg [15:0]music_o
);
always@(ramp[5:0])
begin
case(ramp[5:0])
0 :music_o=16'h0;
1 :music_o=16'h0;
2 :music_o=16'h0;
3 :music_o=16'h0;
4 :music_o=16'h0;
5 :music_o=16'h0;
6 :music_o=16'h246;
7 :music_o=16'hC36;
8 :music_o=16'hCFC;
9 :music_o=16'hC17;
10 :music_o=16'hAEE;
11 :music_o=16'hAA0;
12 :music_o=16'hBB8;
13 :music_o=16'hBAE;
14 :music_o=16'h9E4;
15 :music_o=16'h834;
16 :music_o=16'h789;
17 :music_o=16'hA89;
18 :music_o=16'h115A;
19 :music_o=16'h19D4;
20 :music_o=16'h2316;
21 :music_o=16'h2825;
22 :music_o=16'h24BA;
23 :music_o=16'h1D2E;
24 :music_o=16'h143B;
25 :music_o=16'hE10;
26 :music_o=16'h1345;
27 :music_o=16'h1E4B;
28 :music_o=16'h2392;
29 :music_o=16'h1E0A;
30 :music_o=16'hF4A;
31 :music_o=16'h37F;
32 :music_o=16'h1E0;
33 :music_o=16'h560;
34 :music_o=16'h9B7;
35 :music_o=16'hF84;
36 :music_o=16'h16D8;
37 :music_o=16'h1B1D;
38 :music_o=16'h1B6C;
39 :music_o=16'h1B5D;
40 :music_o=16'h175E;
41 :music_o=16'hD34;
42 :music_o=16'h33A;
43 :music_o=16'hFFFFFCF5;
44 :music_o=16'hFFFFFAC0;
45 :music_o=16'hFFFFF9B0;
46 :music_o=16'hFFFFF3FE;
47 :music_o=16'hFFFFF103;
48 :music_o=16'hFFFFF394;
49 :music_o=16'hFFFFEBEE;
50 :music_o=16'hFFFFDD00;
51 :music_o=16'hFFFFD7D4;
52 :music_o=16'hFFFFE07A;
53 :music_o=16'hFFFFEA88;
54 :music_o=16'hFFFFE8BA;
55 :music_o=16'hFFFFE507;
56 :music_o=16'hFFFFE4C4;
57 :music_o=16'hFFFFE68E;
58 :music_o=16'hFFFFEBB8;
59 :music_o=16'hFFFFED46;
60 :music_o=16'hFFFFF2B2;
61 :music_o=16'hFFFFF899;
62 :music_o=16'hFFFFF4AF;
63 :music_o=16'hFFFFFAA7;
default :music_o=0;
endcase
end
endmodule
|
`default_nettype none
`timescale 1ns/1ns
`define simulation
module tb_dis();
wire clk, reset;
clock clock(clk, reset);
reg iobus_iob_poweron = 1;
reg iobus_iob_reset = 0;
reg iobus_datao_clear = 0;
reg iobus_datao_set = 0;
reg iobus_cono_clear = 0;
reg iobus_cono_set = 0;
reg iobus_iob_fm_datai = 0;
reg iobus_iob_fm_status = 0;
reg [3:9] iobus_ios = 0;
reg [0:35] iobus_iob_in = 0;
wire [1:7] iobus_pi_req;
wire [0:35] iobus_iob_out;
reg read = 0;
dis340 dis(.clk(clk), .reset(~reset),
.iobus_iob_poweron(iobus_iob_poweron),
.iobus_iob_reset(iobus_iob_reset),
.iobus_datao_clear(iobus_datao_clear),
.iobus_datao_set(iobus_datao_set),
.iobus_cono_clear(iobus_cono_clear),
.iobus_cono_set(iobus_cono_set),
.iobus_iob_fm_datai(iobus_iob_fm_datai),
.iobus_iob_fm_status(iobus_iob_fm_status),
.iobus_ios(iobus_ios),
.iobus_iob_in(iobus_iob_in),
.iobus_pi_req(iobus_pi_req),
.iobus_iob_out(iobus_iob_out),
.s_read(read));
task cono;
input [18:35] data;
begin
iobus_iob_in <= data;
iobus_cono_clear <= 1;
#20;
iobus_cono_clear <= 0;
#20;
iobus_cono_set <= 1;
#20;
iobus_cono_set <= 0;
#20;
end
endtask
task datao;
input [0:35] data;
begin
@(posedge dis.dis_flag_data);
#600;
@(posedge clk);
iobus_iob_in <= data;
iobus_datao_clear <= 1;
#20;
iobus_datao_clear <= 0;
#20;
iobus_datao_set <= 1;
#20;
iobus_datao_set <= 0;
#20;
end
endtask
task disp;
input [0:17] word;
begin
list[i] = word;
i = i + 1;
end
endtask
reg [0:17] list[0:1000];
integer i, n;
wire [0:18] Esc = 18'o400000;
wire [0:18] Vert = 18'o200000;
wire [0:18] Iv = 18'o200000;
wire [0:18] Ixy = 18'o002000;
wire [0:18] Stop = 18'o002000;
wire [0:18] PM = 18'o000000;
wire [0:18] XYM = 18'o020000;
wire [0:18] CM = 18'o060000;
wire [0:18] VM = 18'o100000;
wire [0:18] VCM = 18'o120000;
wire [0:18] IM = 18'o140000;
initial begin
$dumpfile("dump.vcd");
$dumpvars();
for(i = 0; i < 1000; i = i + 1)
list[i] = 0;
i = 0;
/*
disp(XYM | 'o100 | 'o17);
disp(XYM | 'o77);
disp(XYM | Vert | 'o66 | Ixy);
disp(VM | Vert | 'o55 | Ixy);
disp(Esc | Iv | { 8'o100, 8'o25 });
disp(XYM | 'o160);
disp(XYM | 'o1000);
disp(IM | 'o1000 | Vert);
disp(Iv | { 4'b1000, 4'b1000, 4'b1000, 4'b1000 });
disp(Iv | { 4'b0010, 4'b0010, 4'b0010, 4'b0010 });
disp(Iv | { 4'b1100, 4'b1100, 4'b1100, 4'b1100 });
disp(Iv | { 4'b0011, 4'b0011, 4'b0011, 4'b0011 } | Esc);
disp(VCM);
disp(Esc | Iv | { 8'b1, 8'b1 });
*/
disp(XYM | 'o160 | 'o17);
disp(XYM | 'o400 | Vert);
disp(CM | 'o1000);
disp({ 6'o01, 6'o36, 6'o03 });
disp({ 6'o37, 6'o02, 6'o03 });
disp(Stop | 'o1000);
n = i;
for(i = 0; i < n; i = i + 1)
$display("list[%d] = %o", i, list[i]);
#100;
iobus_iob_reset <= 1;
#100;
iobus_iob_reset <= 0;
#100;
iobus_ios <= 7'b001_011_0;
#200;
cono(18'o100);
for(i = 0; i < n; i = i + 2)
datao({ list[i], list[i+1] });
/*
#2000;
$display("");
cono(18'o100);
for(i = 0; i < n; i = i + 2)
datao({ list[i], list[i+1] });
*/
end
initial begin
while(1) begin
// @(posedge dis.intensify);
// $display("%o %o %o", dis.i, dis.x, dis.y);
@(posedge dis.fe_data_rq);
#700;
read <= 1;
#1;
$display("0x%X, // %t", dis.s_readdata, $time);
// $display("%o %o %o", dis.i, dis.x, dis.y);
@(posedge clk);
read <= 0;
end
end
initial begin
@(posedge dis.stop);
#100;
$finish;
end
initial begin
#2000000;
$finish;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 10:58:35 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/system_vga_hessian_0_0_stub.v
// Design : system_vga_hessian_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_hessian,Vivado 2016.4" *)
module system_vga_hessian_0_0(clk_x16, active, rst, x_addr, y_addr, g_in,
hessian_out)
/* synthesis syn_black_box black_box_pad_pin="clk_x16,active,rst,x_addr[9:0],y_addr[9:0],g_in[7:0],hessian_out[31:0]" */;
input clk_x16;
input active;
input rst;
input [9:0]x_addr;
input [9:0]y_addr;
input [7:0]g_in;
output [31:0]hessian_out;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Fri Oct 21 16:42:32 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, ADD_OVRFLW_NRM,
left_right_SHT2, bit_shift_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2,
ZERO_FLAG_SHT2, ADD_OVRFLW_NRM2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
OP_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n541,
n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552,
n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, n563,
n564, n565, n566, n567, n568, n569, n570, n571, n572, n573, n574,
n575, n576, n577, n578, n579, n580, n581, n582, n583, n584, n585,
n586, n587, n588, n589, n590, n591, n592, n593, n594, n595, n596,
n597, n598, n599, n600, n601, n602, n603, n604, n605, n606, n607,
n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, n618,
n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, n629,
n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640,
n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651,
n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662,
n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673,
n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684,
n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, n695,
n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706,
n707, n708, n709, n710, n711, n712, n713, n714, n715, n716, n717,
n718, n719, n720, n721, n722, n723, n724, n725, n726, n727, n728,
n729, n730, n731, n732, n733, n734, n735, n736, n737, n738, n739,
n740, n741, n742, n743, n744, n745, n746, n747, n748, n749, n750,
n751, n752, n753, n754, n755, n756, n757, n758, n759, n760, n761,
n762, n763, n764, n765, n766, n767, n768, n769, n770, n771, n772,
n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n784,
n785, n787, n788, n790, n791, n793, n794, n796, n797, n799, n800,
n801, n802, n803, n804, n805, n806, n807, n808, n809, n810, n811,
n812, n813, n814, n815, n816, n817, n818, n819, n820, n821, n822,
n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, n833,
n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, n844,
n845, n846, n847, n849, n850, n851, n852, n853, n854, n855, n856,
n857, n858, n859, n860, n861, n862, n863, n864, n865, n866, n867,
n868, n869, n870, n871, n872, n873, n874, n875, n876, n877, n878,
n879, n880, n881, n882, n883, n884, n885, n886, n887, n888, n889,
n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900,
n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911,
n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922,
n923, n924, n925, n926, n927, n928, n929, n930, n931, n932, n933,
n934, n935, n936, n937, n938, n939, n940, n941, n942, n943, n944,
n945, n946, n947, n948, n949, n950, n951, n952,
DP_OP_15J1_122_6956_n18, DP_OP_15J1_122_6956_n17,
DP_OP_15J1_122_6956_n16, DP_OP_15J1_122_6956_n15,
DP_OP_15J1_122_6956_n14, DP_OP_15J1_122_6956_n8,
DP_OP_15J1_122_6956_n7, DP_OP_15J1_122_6956_n6,
DP_OP_15J1_122_6956_n5, DP_OP_15J1_122_6956_n4,
DP_OP_15J1_122_6956_n3, DP_OP_15J1_122_6956_n2,
DP_OP_15J1_122_6956_n1, n955, n956, n957, n958, n959, n960, n961,
n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972,
n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983,
n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994,
n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004,
n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014,
n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024,
n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034,
n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044,
n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074,
n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084,
n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094,
n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144,
n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154,
n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164,
n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174,
n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274,
n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284,
n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294,
n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314,
n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324,
n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334,
n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344,
n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354,
n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364,
n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374,
n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384,
n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404,
n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434,
n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444,
n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454,
n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464,
n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474,
n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484,
n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494,
n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504,
n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514,
n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524,
n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534,
n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544,
n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554,
n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564,
n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574,
n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584,
n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594,
n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604,
n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614,
n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624,
n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634,
n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644,
n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654,
n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664,
n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674,
n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684,
n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694,
n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704,
n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714,
n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724,
n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734,
n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744,
n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754,
n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764,
n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774,
n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784,
n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794,
n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804,
n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814,
n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824,
n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834,
n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844,
n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854,
n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864,
n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874,
n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884,
n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894,
n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1903;
wire [3:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [7:0] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:1] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n952), .CK(clk), .RN(
n1857), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRXLTS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1857), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1756) );
DFFRXLTS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n951), .CK(clk), .RN(
n1857), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1810) );
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n950), .CK(clk), .RN(n1857), .Q(
Shift_reg_FLAGS_7_6), .QN(n1817) );
DFFRXLTS inst_ShiftRegister_Q_reg_5_ ( .D(n949), .CK(clk), .RN(n1857), .Q(
n1742), .QN(n1824) );
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n947), .CK(clk), .RN(n1857), .Q(
Shift_reg_FLAGS_7[3]), .QN(n1765) );
DFFRXLTS inst_ShiftRegister_Q_reg_2_ ( .D(n946), .CK(clk), .RN(n1901), .Q(
Shift_reg_FLAGS_7[2]), .QN(n1807) );
DFFRXLTS inst_ShiftRegister_Q_reg_0_ ( .D(n944), .CK(clk), .RN(n1857), .Q(
Shift_reg_FLAGS_7[0]), .QN(n1827) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n943), .CK(clk), .RN(n1857), .Q(
intDX_EWSW[0]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n942), .CK(clk), .RN(n1858), .Q(
intDX_EWSW[1]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n941), .CK(clk), .RN(n1858), .Q(
intDX_EWSW[2]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n940), .CK(clk), .RN(n1858), .Q(
intDX_EWSW[3]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n939), .CK(clk), .RN(n1858), .Q(
intDX_EWSW[4]), .QN(n1774) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n938), .CK(clk), .RN(n1858), .Q(
intDX_EWSW[5]), .QN(n1752) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n937), .CK(clk), .RN(n1858), .Q(
intDX_EWSW[6]), .QN(n1781) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n936), .CK(clk), .RN(n1858), .Q(
intDX_EWSW[7]), .QN(n1751) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n935), .CK(clk), .RN(n1858), .Q(
intDX_EWSW[8]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n934), .CK(clk), .RN(n1858), .Q(
intDX_EWSW[9]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n933), .CK(clk), .RN(n1858),
.Q(intDX_EWSW[10]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n932), .CK(clk), .RN(n1859),
.Q(intDX_EWSW[11]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n931), .CK(clk), .RN(n1859),
.Q(intDX_EWSW[12]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n930), .CK(clk), .RN(n1859),
.Q(intDX_EWSW[13]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n929), .CK(clk), .RN(n1859),
.Q(intDX_EWSW[14]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n928), .CK(clk), .RN(n1859),
.Q(intDX_EWSW[15]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n927), .CK(clk), .RN(n1859),
.Q(intDX_EWSW[16]), .QN(n1779) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n926), .CK(clk), .RN(n1859),
.Q(intDX_EWSW[17]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n925), .CK(clk), .RN(n1859),
.Q(intDX_EWSW[18]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n924), .CK(clk), .RN(n1859),
.Q(intDX_EWSW[19]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n923), .CK(clk), .RN(n1859),
.Q(intDX_EWSW[20]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n922), .CK(clk), .RN(n1860),
.Q(intDX_EWSW[21]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n921), .CK(clk), .RN(n1860),
.Q(intDX_EWSW[22]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n920), .CK(clk), .RN(n1860),
.Q(intDX_EWSW[23]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n919), .CK(clk), .RN(n1860),
.Q(intDX_EWSW[24]), .QN(n1819) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n918), .CK(clk), .RN(n1860),
.Q(intDX_EWSW[25]), .QN(n1744) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n917), .CK(clk), .RN(n1860),
.Q(intDX_EWSW[26]), .QN(n1745) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n916), .CK(clk), .RN(n1860),
.Q(intDX_EWSW[27]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n915), .CK(clk), .RN(n1860),
.Q(intDX_EWSW[28]), .QN(n1808) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n914), .CK(clk), .RN(n1860),
.Q(intDX_EWSW[29]), .QN(n1804) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n913), .CK(clk), .RN(n1860),
.Q(intDX_EWSW[30]), .QN(n1741) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n912), .CK(clk), .RN(n1861),
.Q(intDX_EWSW[31]) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n911), .CK(clk), .RN(n1861), .Q(
intAS) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1861),
.Q(ready) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n910), .CK(clk), .RN(n1861), .Q(
intDY_EWSW[0]), .QN(n1798) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n909), .CK(clk), .RN(n1861), .Q(
intDY_EWSW[1]), .QN(n1802) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n908), .CK(clk), .RN(n1861), .Q(
intDY_EWSW[2]), .QN(n1792) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n907), .CK(clk), .RN(n1861), .Q(
intDY_EWSW[3]), .QN(n1799) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n906), .CK(clk), .RN(n1861), .Q(
intDY_EWSW[4]), .QN(n1789) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n905), .CK(clk), .RN(n1861), .Q(
intDY_EWSW[5]), .QN(n1758) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n904), .CK(clk), .RN(n1861), .Q(
intDY_EWSW[6]), .QN(n1788) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n903), .CK(clk), .RN(n1893), .Q(
intDY_EWSW[7]), .QN(n1803) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n902), .CK(clk), .RN(n1900), .Q(
intDY_EWSW[8]), .QN(n1801) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n901), .CK(clk), .RN(n1897), .Q(
intDY_EWSW[9]), .QN(n1793) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n900), .CK(clk), .RN(n1901),
.Q(intDY_EWSW[10]), .QN(n1778) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n899), .CK(clk), .RN(n1892),
.Q(intDY_EWSW[11]), .QN(n1783) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n898), .CK(clk), .RN(n1897),
.Q(intDY_EWSW[12]), .QN(n1794) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n897), .CK(clk), .RN(n1903),
.Q(intDY_EWSW[13]), .QN(n1790) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n896), .CK(clk), .RN(n1903),
.Q(intDY_EWSW[14]), .QN(n1759) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n895), .CK(clk), .RN(n1901),
.Q(intDY_EWSW[15]), .QN(n1800) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n894), .CK(clk), .RN(n1901),
.Q(intDY_EWSW[16]), .QN(n1757) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n893), .CK(clk), .RN(n1862),
.Q(intDY_EWSW[17]), .QN(n1797) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n892), .CK(clk), .RN(n1862),
.Q(intDY_EWSW[18]), .QN(n1811) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n891), .CK(clk), .RN(n1862),
.Q(intDY_EWSW[19]), .QN(n1761) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n890), .CK(clk), .RN(n1862),
.Q(intDY_EWSW[20]), .QN(n1795) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n889), .CK(clk), .RN(n1862),
.Q(intDY_EWSW[21]), .QN(n1791) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n888), .CK(clk), .RN(n1862),
.Q(intDY_EWSW[22]), .QN(n1760) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n887), .CK(clk), .RN(n1862),
.Q(intDY_EWSW[23]), .QN(n1815) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n886), .CK(clk), .RN(n1862),
.Q(intDY_EWSW[24]), .QN(n1740) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n885), .CK(clk), .RN(n1862),
.Q(intDY_EWSW[25]), .QN(n1787) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n884), .CK(clk), .RN(n1862),
.Q(intDY_EWSW[26]), .QN(n1786) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n883), .CK(clk), .RN(n1899),
.Q(intDY_EWSW[27]), .QN(n1796) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n882), .CK(clk), .RN(n1900),
.Q(intDY_EWSW[28]) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n881), .CK(clk), .RN(n1895),
.Q(intDY_EWSW[29]), .QN(n1754) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n880), .CK(clk), .RN(n1899),
.Q(intDY_EWSW[30]), .QN(n1782) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n879), .CK(clk), .RN(n1900),
.Q(intDY_EWSW[31]) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n878), .CK(clk), .RN(n1895), .Q(
bit_shift_SHT2), .QN(n1812) );
DFFRXLTS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n849), .CK(clk), .RN(n1899), .Q(
shift_value_SHT2_EWR[3]), .QN(n1776) );
DFFRXLTS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n850), .CK(clk), .RN(n1900), .Q(
shift_value_SHT2_EWR[2]), .QN(n1748) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n876), .CK(clk), .RN(n1895), .Q(
Data_array_SWR[25]), .QN(n1809) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n875), .CK(clk), .RN(n1899), .Q(
Data_array_SWR[24]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n874), .CK(clk), .RN(n1895), .Q(
Data_array_SWR[23]), .QN(n1806) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n873), .CK(clk), .RN(n1900), .Q(
Data_array_SWR[22]), .QN(n1805) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n872), .CK(clk), .RN(n1899), .Q(
Data_array_SWR[21]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n871), .CK(clk), .RN(n1895), .Q(
Data_array_SWR[20]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n870), .CK(clk), .RN(n1900), .Q(
Data_array_SWR[19]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n869), .CK(clk), .RN(n1899), .Q(
Data_array_SWR[18]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n868), .CK(clk), .RN(n1895), .Q(
Data_array_SWR[17]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n867), .CK(clk), .RN(n1900), .Q(
Data_array_SWR[16]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n866), .CK(clk), .RN(n1899), .Q(
Data_array_SWR[15]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n865), .CK(clk), .RN(n1863), .Q(
Data_array_SWR[14]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n864), .CK(clk), .RN(n1863), .Q(
Data_array_SWR[13]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n863), .CK(clk), .RN(n1863), .Q(
Data_array_SWR[12]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n862), .CK(clk), .RN(n1863), .Q(
Data_array_SWR[11]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n861), .CK(clk), .RN(n1863), .Q(
Data_array_SWR[10]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n860), .CK(clk), .RN(n1863), .Q(
Data_array_SWR[9]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n859), .CK(clk), .RN(n1863), .Q(
Data_array_SWR[8]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n858), .CK(clk), .RN(n1863), .Q(
Data_array_SWR[7]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n857), .CK(clk), .RN(n1863), .Q(
Data_array_SWR[6]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n856), .CK(clk), .RN(n1863), .Q(
Data_array_SWR[5]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n855), .CK(clk), .RN(n1864), .Q(
Data_array_SWR[4]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n854), .CK(clk), .RN(n1864), .Q(
Data_array_SWR[3]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n853), .CK(clk), .RN(n1864), .Q(
Data_array_SWR[2]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n852), .CK(clk), .RN(n1864), .Q(
Data_array_SWR[1]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n851), .CK(clk), .RN(n1864), .Q(
Data_array_SWR[0]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n846), .CK(clk), .RN(n1864),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n845), .CK(clk), .RN(n1864),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n844), .CK(clk), .RN(n1864),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n843), .CK(clk), .RN(n1864),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n842), .CK(clk), .RN(n1865),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n833), .CK(clk), .RN(n1865), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n832), .CK(clk), .RN(n1865), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n831), .CK(clk), .RN(n1865), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n830), .CK(clk), .RN(n1865), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n829), .CK(clk), .RN(n1865), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n828), .CK(clk), .RN(n1865), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n827), .CK(clk), .RN(n1865), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n826), .CK(clk), .RN(n1865), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n825), .CK(clk), .RN(n1865), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n824), .CK(clk), .RN(n1866), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n823), .CK(clk), .RN(n1866), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n822), .CK(clk), .RN(n1866), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n821), .CK(clk), .RN(n1866), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n820), .CK(clk), .RN(n1866), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n819), .CK(clk), .RN(n1866), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n818), .CK(clk), .RN(n1866), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n817), .CK(clk), .RN(n1866), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n816), .CK(clk), .RN(n1866), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n815), .CK(clk), .RN(n1866), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n814), .CK(clk), .RN(n1867), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n813), .CK(clk), .RN(n1867), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n812), .CK(clk), .RN(n1867), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n811), .CK(clk), .RN(n1867), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(n810), .CK(clk), .RN(n1867), .Q(
DMP_EXP_EWSW[23]), .QN(n1816) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(n809), .CK(clk), .RN(n1867), .Q(
DMP_EXP_EWSW[24]), .QN(n1763) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(n808), .CK(clk), .RN(n1867), .Q(
DMP_EXP_EWSW[25]), .QN(n1813) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(n807), .CK(clk), .RN(n1867), .Q(
DMP_EXP_EWSW[26]), .QN(n1821) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n806), .CK(clk), .RN(n1867), .Q(
DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n805), .CK(clk), .RN(n1867), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n804), .CK(clk), .RN(n1868), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n803), .CK(clk), .RN(n1868), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n802), .CK(clk), .RN(n1868), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n801), .CK(clk), .RN(n1868), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n800), .CK(clk), .RN(n1868), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n799), .CK(clk), .RN(n1868), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1856), .CK(clk), .RN(n1887), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_0_ ( .D(n797), .CK(clk), .RN(n1887), .Q(
DMP_SFG[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n796), .CK(clk), .RN(n1868), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1855), .CK(clk), .RN(n1887), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_1_ ( .D(n794), .CK(clk), .RN(n1887), .Q(
DMP_SFG[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n793), .CK(clk), .RN(n1868), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1854), .CK(clk), .RN(n1887), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n791), .CK(clk), .RN(n1887), .Q(
DMP_SFG[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n790), .CK(clk), .RN(n1868), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1853), .CK(clk), .RN(n1888), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n788), .CK(clk), .RN(n1887), .Q(
DMP_SFG[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n787), .CK(clk), .RN(n1868), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1852), .CK(clk), .RN(n1888), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n785), .CK(clk), .RN(n1888), .Q(
DMP_SFG[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n784), .CK(clk), .RN(n1869), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1851), .CK(clk), .RN(n1888), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_5_ ( .D(n782), .CK(clk), .RN(n1888), .Q(
DMP_SFG[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n781), .CK(clk), .RN(n1869), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n780), .CK(clk), .RN(n1869), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n779), .CK(clk), .RN(n1888), .Q(
DMP_SFG[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n1869), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n777), .CK(clk), .RN(n1869), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_7_ ( .D(n776), .CK(clk), .RN(n1888), .Q(
DMP_SFG[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n775), .CK(clk), .RN(n1869), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n774), .CK(clk), .RN(n1869), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_8_ ( .D(n773), .CK(clk), .RN(n1888), .Q(
DMP_SFG[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n772), .CK(clk), .RN(n1869), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n771), .CK(clk), .RN(n1869), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_9_ ( .D(n770), .CK(clk), .RN(n1888), .Q(
DMP_SFG[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n769), .CK(clk), .RN(n1869), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n768), .CK(clk), .RN(n1870), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n767), .CK(clk), .RN(n1888), .Q(
DMP_SFG[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n766), .CK(clk), .RN(n1870), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n765), .CK(clk), .RN(n1870), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n764), .CK(clk), .RN(n1889), .Q(
DMP_SFG[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n763), .CK(clk), .RN(n1870), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n762), .CK(clk), .RN(n1870), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n761), .CK(clk), .RN(n1903), .Q(
DMP_SFG[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n760), .CK(clk), .RN(n1870), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n759), .CK(clk), .RN(n1870), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n758), .CK(clk), .RN(n1901), .Q(
DMP_SFG[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n757), .CK(clk), .RN(n1870), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n756), .CK(clk), .RN(n1870), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n755), .CK(clk), .RN(n1889), .Q(
DMP_SFG[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n754), .CK(clk), .RN(n1870), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n753), .CK(clk), .RN(n1892), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n752), .CK(clk), .RN(n1903), .Q(
DMP_SFG[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n751), .CK(clk), .RN(n1897), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n750), .CK(clk), .RN(n1892), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n749), .CK(clk), .RN(n1901), .Q(
DMP_SFG[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n748), .CK(clk), .RN(n1897), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n747), .CK(clk), .RN(n1892), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n746), .CK(clk), .RN(n1889), .Q(
DMP_SFG[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n745), .CK(clk), .RN(n1897), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n744), .CK(clk), .RN(n1892), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n743), .CK(clk), .RN(n1903), .Q(
DMP_SFG[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n742), .CK(clk), .RN(n1897), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n741), .CK(clk), .RN(n1892), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n740), .CK(clk), .RN(n1901), .Q(
DMP_SFG[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n739), .CK(clk), .RN(n1897), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n738), .CK(clk), .RN(n1871), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n737), .CK(clk), .RN(n1889), .Q(
DMP_SFG[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n736), .CK(clk), .RN(n1871), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n735), .CK(clk), .RN(n1871), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n734), .CK(clk), .RN(n1903), .Q(
DMP_SFG[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n733), .CK(clk), .RN(n1871), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n732), .CK(clk), .RN(n1871), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n731), .CK(clk), .RN(n1889), .Q(
DMP_SFG[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1871), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n729), .CK(clk), .RN(n1871), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n728), .CK(clk), .RN(n1871), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n727), .CK(clk), .RN(n1871), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n726), .CK(clk), .RN(n1881), .Q(
DMP_exp_NRM2_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n725), .CK(clk), .RN(n1871), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n724), .CK(clk), .RN(n1872), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n723), .CK(clk), .RN(n1872), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n1872), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n721), .CK(clk), .RN(n1881), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n720), .CK(clk), .RN(n1872), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n719), .CK(clk), .RN(n1872), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n718), .CK(clk), .RN(n1872), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n717), .CK(clk), .RN(n1872), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n716), .CK(clk), .RN(n1881), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n715), .CK(clk), .RN(n1872), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n714), .CK(clk), .RN(n1872), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n713), .CK(clk), .RN(n1872), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n712), .CK(clk), .RN(n1873), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n711), .CK(clk), .RN(n1881), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n710), .CK(clk), .RN(n1873), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n709), .CK(clk), .RN(n1873), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n708), .CK(clk), .RN(n1873), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n1873), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n706), .CK(clk), .RN(n1881), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n705), .CK(clk), .RN(n1873), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n704), .CK(clk), .RN(n1873), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n703), .CK(clk), .RN(n1873), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n1873), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n701), .CK(clk), .RN(n1881), .Q(
DMP_exp_NRM2_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n700), .CK(clk), .RN(n1873), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n699), .CK(clk), .RN(n1874), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n698), .CK(clk), .RN(n1874), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n697), .CK(clk), .RN(n1874), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n696), .CK(clk), .RN(n1881), .Q(
DMP_exp_NRM2_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n695), .CK(clk), .RN(n1874), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n694), .CK(clk), .RN(n1874), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n693), .CK(clk), .RN(n1874), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n692), .CK(clk), .RN(n1874), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n691), .CK(clk), .RN(n1881), .Q(
DMP_exp_NRM2_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n690), .CK(clk), .RN(n1874), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n689), .CK(clk), .RN(n1874), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n688), .CK(clk), .RN(n1874), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n687), .CK(clk), .RN(n1875), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n686), .CK(clk), .RN(n1875), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n685), .CK(clk), .RN(n1875), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n684), .CK(clk), .RN(n1875), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n683), .CK(clk), .RN(n1875), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n682), .CK(clk), .RN(n1875), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n681), .CK(clk), .RN(n1875), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n680), .CK(clk), .RN(n1875), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n679), .CK(clk), .RN(n1875), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n678), .CK(clk), .RN(n1875), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n677), .CK(clk), .RN(n1876), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n676), .CK(clk), .RN(n1876), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n675), .CK(clk), .RN(n1876), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n674), .CK(clk), .RN(n1876), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n673), .CK(clk), .RN(n1876), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n672), .CK(clk), .RN(n1876), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n671), .CK(clk), .RN(n1876), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n670), .CK(clk), .RN(n1876), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n669), .CK(clk), .RN(n1876), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n668), .CK(clk), .RN(n1876), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n667), .CK(clk), .RN(n1877), .Q(
DmP_mant_SHT1_SW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n666), .CK(clk), .RN(n1877), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n665), .CK(clk), .RN(n1877), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n664), .CK(clk), .RN(n1877), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n663), .CK(clk), .RN(n1877), .Q(
DmP_mant_SHT1_SW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n662), .CK(clk), .RN(n1877), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n661), .CK(clk), .RN(n1877), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n660), .CK(clk), .RN(n1877), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n659), .CK(clk), .RN(n1877), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n658), .CK(clk), .RN(n1877), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n657), .CK(clk), .RN(n1894), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n656), .CK(clk), .RN(n1894), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n655), .CK(clk), .RN(n1891), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n654), .CK(clk), .RN(n1890), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n653), .CK(clk), .RN(n1894), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n652), .CK(clk), .RN(n1891), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n651), .CK(clk), .RN(n1890), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n650), .CK(clk), .RN(n1894), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n649), .CK(clk), .RN(n1891), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n648), .CK(clk), .RN(n1890), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n647), .CK(clk), .RN(n1894), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n646), .CK(clk), .RN(n1891), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n645), .CK(clk), .RN(n1890), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(n644), .CK(clk), .RN(n1894), .Q(
DmP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_24_ ( .D(n643), .CK(clk), .RN(n1891), .Q(
DmP_EXP_EWSW[24]), .QN(n1762) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_25_ ( .D(n642), .CK(clk), .RN(n1890), .Q(
DmP_EXP_EWSW[25]), .QN(n1822) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(n641), .CK(clk), .RN(n1894), .Q(
DmP_EXP_EWSW[26]), .QN(n1818) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(n640), .CK(clk), .RN(n1891), .Q(
DmP_EXP_EWSW[27]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n637), .CK(clk), .RN(n1890), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n636), .CK(clk), .RN(n1878), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n635), .CK(clk), .RN(n1878), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n634), .CK(clk), .RN(n1878), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n633), .CK(clk), .RN(n1878), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n631), .CK(clk), .RN(n1878), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n630), .CK(clk), .RN(n1878), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n629), .CK(clk), .RN(n1884), .Q(
OP_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n628), .CK(clk), .RN(n1884), .Q(
ADD_OVRFLW_NRM), .QN(n1785) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n626), .CK(clk), .RN(n1878), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n625), .CK(clk), .RN(n1878), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n624), .CK(clk), .RN(n1878), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n623), .CK(clk), .RN(n1896), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n622), .CK(clk), .RN(n1893), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n620), .CK(clk), .RN(n1882), .Q(
Raw_mant_NRM_SWR[0]), .QN(n1820) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n619), .CK(clk), .RN(n1882), .Q(
Raw_mant_NRM_SWR[1]), .QN(n1749) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n618), .CK(clk), .RN(n1882), .Q(
Raw_mant_NRM_SWR[2]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n617), .CK(clk), .RN(n1882), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1739) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n616), .CK(clk), .RN(n1882), .Q(
Raw_mant_NRM_SWR[4]), .QN(n1750) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n615), .CK(clk), .RN(n1881), .Q(
Raw_mant_NRM_SWR[5]), .QN(n1772) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n614), .CK(clk), .RN(n1882), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1773) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n613), .CK(clk), .RN(n1882), .Q(
Raw_mant_NRM_SWR[7]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n612), .CK(clk), .RN(n1882), .Q(
Raw_mant_NRM_SWR[8]), .QN(n1747) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n611), .CK(clk), .RN(n1882), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1770) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n610), .CK(clk), .RN(n1882), .Q(
Raw_mant_NRM_SWR[10]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n609), .CK(clk), .RN(n1883), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1764) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n608), .CK(clk), .RN(n1883), .Q(
Raw_mant_NRM_SWR[12]), .QN(n1814) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n607), .CK(clk), .RN(n1883), .Q(
Raw_mant_NRM_SWR[13]), .QN(n1823) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n606), .CK(clk), .RN(n1883), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1769) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n605), .CK(clk), .RN(n1883), .Q(
Raw_mant_NRM_SWR[15]), .QN(n1755) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n604), .CK(clk), .RN(n1883), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1780) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n603), .CK(clk), .RN(n1883), .Q(
Raw_mant_NRM_SWR[17]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n602), .CK(clk), .RN(n1883), .Q(
Raw_mant_NRM_SWR[18]), .QN(n1768) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n601), .CK(clk), .RN(n1884), .Q(
Raw_mant_NRM_SWR[19]), .QN(n1784) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n600), .CK(clk), .RN(n1883), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n599), .CK(clk), .RN(n1883), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1775) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n598), .CK(clk), .RN(n1884), .Q(
Raw_mant_NRM_SWR[22]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n597), .CK(clk), .RN(n1884), .Q(
Raw_mant_NRM_SWR[23]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n596), .CK(clk), .RN(n1884), .Q(
Raw_mant_NRM_SWR[24]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n595), .CK(clk), .RN(n1884), .Q(
Raw_mant_NRM_SWR[25]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n594), .CK(clk), .RN(n1880), .Q(
LZD_output_NRM2_EW[3]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n1880), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n592), .CK(clk), .RN(n1880), .Q(
LZD_output_NRM2_EW[2]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n591), .CK(clk), .RN(n1880), .Q(
LZD_output_NRM2_EW[1]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n590), .CK(clk), .RN(n1881), .Q(
LZD_output_NRM2_EW[4]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n566), .CK(clk), .RN(n1884), .QN(
n1766) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n565), .CK(clk), .RN(n1884), .Q(
DmP_mant_SFG_SWR[1]), .QN(n1850) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n564), .CK(clk), .RN(n1884), .Q(
DmP_mant_SFG_SWR[2]), .QN(n1825) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n563), .CK(clk), .RN(n1885), .Q(
DmP_mant_SFG_SWR[3]), .QN(n1849) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n562), .CK(clk), .RN(n1885), .Q(
DmP_mant_SFG_SWR[4]), .QN(n1840) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n561), .CK(clk), .RN(n1885), .Q(
DmP_mant_SFG_SWR[5]), .QN(n1767) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n560), .CK(clk), .RN(n1885), .Q(
DmP_mant_SFG_SWR[6]), .QN(n1839) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n559), .CK(clk), .RN(n1885), .Q(
DmP_mant_SFG_SWR[7]), .QN(n1848) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n558), .CK(clk), .RN(n1885), .Q(
DmP_mant_SFG_SWR[8]), .QN(n1838) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n557), .CK(clk), .RN(n1885), .Q(
DmP_mant_SFG_SWR[9]), .QN(n1847) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n556), .CK(clk), .RN(n1885), .Q(
DmP_mant_SFG_SWR[10]), .QN(n1837) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n555), .CK(clk), .RN(n1885), .Q(
DmP_mant_SFG_SWR[11]), .QN(n1846) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n554), .CK(clk), .RN(n1885), .Q(
DmP_mant_SFG_SWR[12]), .QN(n1836) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n553), .CK(clk), .RN(n1886), .Q(
DmP_mant_SFG_SWR[13]), .QN(n1845) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n552), .CK(clk), .RN(n1886), .Q(
DmP_mant_SFG_SWR[14]), .QN(n1835) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n551), .CK(clk), .RN(n1886), .Q(
DmP_mant_SFG_SWR[15]), .QN(n1844) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n550), .CK(clk), .RN(n1886), .Q(
DmP_mant_SFG_SWR[16]), .QN(n1834) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n549), .CK(clk), .RN(n1886), .Q(
DmP_mant_SFG_SWR[17]), .QN(n1843) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n548), .CK(clk), .RN(n1886), .Q(
DmP_mant_SFG_SWR[18]), .QN(n1833) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n547), .CK(clk), .RN(n1886), .Q(
DmP_mant_SFG_SWR[19]), .QN(n1842) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n546), .CK(clk), .RN(n1886), .Q(
DmP_mant_SFG_SWR[20]), .QN(n1832) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n545), .CK(clk), .RN(n1886), .Q(
DmP_mant_SFG_SWR[21]), .QN(n1831) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n544), .CK(clk), .RN(n1886), .Q(
DmP_mant_SFG_SWR[22]), .QN(n1830) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n543), .CK(clk), .RN(n1887), .Q(
DmP_mant_SFG_SWR[23]), .QN(n1829) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n542), .CK(clk), .RN(n1887), .Q(
DmP_mant_SFG_SWR[24]), .QN(n1828) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n541), .CK(clk), .RN(n1887), .Q(
DmP_mant_SFG_SWR[25]), .QN(n1841) );
CMPR32X2TS DP_OP_15J1_122_6956_U9 ( .A(DMP_exp_NRM2_EW[0]), .B(n1746), .C(
DP_OP_15J1_122_6956_n18), .CO(DP_OP_15J1_122_6956_n8), .S(
exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_15J1_122_6956_U8 ( .A(DP_OP_15J1_122_6956_n17), .B(
DMP_exp_NRM2_EW[1]), .C(DP_OP_15J1_122_6956_n8), .CO(
DP_OP_15J1_122_6956_n7), .S(exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_15J1_122_6956_U2 ( .A(n1746), .B(DMP_exp_NRM2_EW[7]), .C(
DP_OP_15J1_122_6956_n2), .CO(DP_OP_15J1_122_6956_n1), .S(
exp_rslt_NRM2_EW1[7]) );
CMPR32X2TS DP_OP_15J1_122_6956_U7 ( .A(DP_OP_15J1_122_6956_n16), .B(
DMP_exp_NRM2_EW[2]), .C(DP_OP_15J1_122_6956_n7), .CO(
DP_OP_15J1_122_6956_n6), .S(exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_15J1_122_6956_U4 ( .A(n1746), .B(DMP_exp_NRM2_EW[5]), .C(
DP_OP_15J1_122_6956_n4), .CO(DP_OP_15J1_122_6956_n3), .S(
exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_15J1_122_6956_U3 ( .A(n1746), .B(DMP_exp_NRM2_EW[6]), .C(
DP_OP_15J1_122_6956_n3), .CO(DP_OP_15J1_122_6956_n2), .S(
exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_15J1_122_6956_U6 ( .A(DP_OP_15J1_122_6956_n15), .B(
DMP_exp_NRM2_EW[3]), .C(DP_OP_15J1_122_6956_n6), .CO(
DP_OP_15J1_122_6956_n5), .S(exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_15J1_122_6956_U5 ( .A(DP_OP_15J1_122_6956_n14), .B(
DMP_exp_NRM2_EW[4]), .C(DP_OP_15J1_122_6956_n5), .CO(
DP_OP_15J1_122_6956_n4), .S(exp_rslt_NRM2_EW1[4]) );
DFFRXLTS inst_ShiftRegister_Q_reg_4_ ( .D(n948), .CK(clk), .RN(n1857), .Q(
n1743), .QN(n1826) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n579), .CK(clk), .RN(n1893), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n621), .CK(clk), .RN(n1879), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n835), .CK(clk), .RN(n1879), .Q(
final_result_ieee[29]) );
DFFRX1TS inst_ShiftRegister_Q_reg_1_ ( .D(n945), .CK(clk), .RN(n1857), .Q(
Shift_reg_FLAGS_7[1]), .QN(n1777) );
DFFRX1TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n877), .CK(clk), .RN(n1900), .Q(
left_right_SHT2), .QN(n1771) );
DFFRXLTS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n847), .CK(clk), .RN(n1864), .Q(
shift_value_SHT2_EWR[4]), .QN(n1753) );
DFFRX1TS SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n627), .CK(clk), .RN(n1880), .Q(
ADD_OVRFLW_NRM2), .QN(n1746) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n632), .CK(clk), .RN(n1878), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n589), .CK(clk), .RN(n1898), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n1896), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n587), .CK(clk), .RN(n1893), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n586), .CK(clk), .RN(n1898), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n585), .CK(clk), .RN(n1896), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n584), .CK(clk), .RN(n1893), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n583), .CK(clk), .RN(n1898), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n582), .CK(clk), .RN(n1893), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n581), .CK(clk), .RN(n1896), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n580), .CK(clk), .RN(n1898), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n578), .CK(clk), .RN(n1896), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n577), .CK(clk), .RN(n1898), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n576), .CK(clk), .RN(n1893), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n575), .CK(clk), .RN(n1896), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n574), .CK(clk), .RN(n1898), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n573), .CK(clk), .RN(n1893), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n572), .CK(clk), .RN(n1896), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n571), .CK(clk), .RN(n1879), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n570), .CK(clk), .RN(n1879), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n569), .CK(clk), .RN(n1879), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n568), .CK(clk), .RN(n1879), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n567), .CK(clk), .RN(n1879), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n639), .CK(clk), .RN(n1894), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n834), .CK(clk), .RN(n1879), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n638), .CK(clk), .RN(n1879), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n841), .CK(clk), .RN(n1880), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n840), .CK(clk), .RN(n1880), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n839), .CK(clk), .RN(n1880), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n838), .CK(clk), .RN(n1880), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n837), .CK(clk), .RN(n1880), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n836), .CK(clk), .RN(n1879), .Q(
final_result_ieee[28]) );
CLKBUFX2TS U958 ( .A(n1085), .Y(n966) );
NOR2XLTS U959 ( .A(n1105), .B(Raw_mant_NRM_SWR[11]), .Y(n1097) );
NOR2XLTS U960 ( .A(n1046), .B(n1676), .Y(n1200) );
NOR2XLTS U961 ( .A(Raw_mant_NRM_SWR[13]), .B(n1135), .Y(n1258) );
AO22XLTS U962 ( .A0(n1152), .A1(n1626), .B0(Shift_amount_SHT1_EWR[1]), .B1(
n1708), .Y(n1113) );
AOI211XLTS U963 ( .A0(Shift_amount_SHT1_EWR[0]), .A1(n1636), .B0(n1627),
.C0(n966), .Y(n1364) );
NAND2BX1TS U964 ( .AN(n1274), .B(n1273), .Y(n1709) );
NOR2X1TS U965 ( .A(n1785), .B(n1379), .Y(n1085) );
NAND4BXLTS U966 ( .AN(exp_rslt_NRM2_EW1[3]), .B(n1286), .C(n1276), .D(n1280),
.Y(n1269) );
XOR2XLTS U967 ( .A(n1746), .B(n1384), .Y(DP_OP_15J1_122_6956_n16) );
NAND2BXLTS U968 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n992) );
NOR2XLTS U969 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(n1100) );
NOR4XLTS U970 ( .A(Raw_mant_NRM_SWR[16]), .B(Raw_mant_NRM_SWR[15]), .C(
Raw_mant_NRM_SWR[17]), .D(n1251), .Y(n1091) );
XOR2XLTS U971 ( .A(n1746), .B(n1382), .Y(DP_OP_15J1_122_6956_n14) );
XOR2XLTS U972 ( .A(n1746), .B(n1385), .Y(DP_OP_15J1_122_6956_n17) );
NOR4BXLTS U973 ( .AN(exp_rslt_NRM2_EW1[3]), .B(n1286), .C(n1276), .D(n1280),
.Y(n1145) );
AOI211XLTS U974 ( .A0(n1258), .A1(Raw_mant_NRM_SWR[12]), .B0(n1108), .C0(
n1096), .Y(n1141) );
AOI211XLTS U975 ( .A0(n1750), .A1(n1095), .B0(Raw_mant_NRM_SWR[5]), .C0(
n1138), .Y(n1096) );
NAND3XLTS U976 ( .A(n1267), .B(n1772), .C(n1750), .Y(n1263) );
NAND2BXLTS U977 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1010) );
NAND3XLTS U978 ( .A(n1801), .B(n1008), .C(intDX_EWSW[8]), .Y(n1009) );
NOR2XLTS U979 ( .A(intDY_EWSW[10]), .B(n1006), .Y(n1007) );
INVX2TS U980 ( .A(n1090), .Y(n1094) );
NOR2XLTS U981 ( .A(intDY_EWSW[16]), .B(n1027), .Y(n1028) );
OAI211XLTS U982 ( .A0(n986), .A1(n1041), .B0(n985), .C0(n984), .Y(n991) );
NAND2BXLTS U983 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n985) );
NAND3XLTS U984 ( .A(n1786), .B(n983), .C(intDX_EWSW[26]), .Y(n984) );
NAND3BXLTS U985 ( .AN(n1027), .B(n1025), .C(n1024), .Y(n1044) );
AOI211XLTS U986 ( .A0(intDY_EWSW[16]), .A1(n1779), .B0(n1032), .C0(n1216),
.Y(n1024) );
INVX2TS U987 ( .A(shift_value_SHT2_EWR[4]), .Y(n961) );
OAI21XLTS U988 ( .A0(n1253), .A1(n1263), .B0(n1107), .Y(n1266) );
NOR2XLTS U989 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(n1102) );
OAI31X1TS U990 ( .A0(n1755), .A1(Raw_mant_NRM_SWR[17]), .A2(
Raw_mant_NRM_SWR[16]), .B0(n1784), .Y(n1103) );
AOI2BB1XLTS U991 ( .A0N(n1088), .A1N(Raw_mant_NRM_SWR[23]), .B0(
Raw_mant_NRM_SWR[24]), .Y(n1089) );
OAI31X1TS U992 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1780), .A2(n1094), .B0(
n1250), .Y(n1092) );
XOR2XLTS U993 ( .A(n1746), .B(n1383), .Y(DP_OP_15J1_122_6956_n15) );
OAI21XLTS U994 ( .A0(n1750), .A1(n1373), .B0(n1319), .Y(n1337) );
OAI21XLTS U995 ( .A0(n1773), .A1(n1373), .B0(n1165), .Y(n1358) );
OAI21XLTS U996 ( .A0(n1747), .A1(n1373), .B0(n1151), .Y(n1357) );
OAI21XLTS U997 ( .A0(n1814), .A1(n1373), .B0(n1120), .Y(n1187) );
OAI21XLTS U998 ( .A0(n1780), .A1(n1373), .B0(n1116), .Y(n1169) );
NAND3XLTS U999 ( .A(n1308), .B(n1307), .C(n1306), .Y(n1343) );
NAND3XLTS U1000 ( .A(n1292), .B(n1291), .C(n1290), .Y(n1344) );
NAND2BXLTS U1001 ( .AN(n1113), .B(n1654), .Y(n1655) );
NOR4BXLTS U1002 ( .AN(n1141), .B(n1248), .C(n1140), .D(n1139), .Y(n1144) );
OAI31X1TS U1003 ( .A0(n1263), .A1(n1255), .A2(n1749), .B0(n1254), .Y(n1256)
);
AOI2BB2XLTS U1004 ( .B0(intDX_EWSW[3]), .B1(n1799), .A0N(intDY_EWSW[2]),
.A1N(n998), .Y(n999) );
NAND2BXLTS U1005 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n996) );
NAND2BXLTS U1006 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1029) );
NAND2BXLTS U1007 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n983) );
NAND2BXLTS U1008 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1008) );
AOI211XLTS U1009 ( .A0(n1018), .A1(n1017), .B0(n1016), .C0(n1015), .Y(n1019)
);
NAND2BXLTS U1010 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1023) );
NOR2XLTS U1011 ( .A(n1458), .B(n1436), .Y(n1441) );
NOR3X1TS U1012 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[4]),
.C(n1776), .Y(n981) );
NAND3XLTS U1013 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.C(n1753), .Y(n1449) );
NAND2BXLTS U1014 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1038) );
NOR2XLTS U1015 ( .A(n1087), .B(n1136), .Y(n1090) );
XOR2XLTS U1016 ( .A(n1746), .B(n1386), .Y(DP_OP_15J1_122_6956_n18) );
OAI211XLTS U1017 ( .A0(n1805), .A1(n1442), .B0(n1441), .C0(n1440), .Y(n1453)
);
OAI211XLTS U1018 ( .A0(n1806), .A1(n1449), .B0(n1439), .C0(n1438), .Y(n1452)
);
OAI211XLTS U1019 ( .A0(n1806), .A1(n1442), .B0(n1441), .C0(n1437), .Y(n1456)
);
OAI211XLTS U1020 ( .A0(n1805), .A1(n1449), .B0(n1435), .C0(n1434), .Y(n1455)
);
OAI211XLTS U1021 ( .A0(n1485), .A1(n1753), .B0(n1427), .C0(n1426), .Y(n1464)
);
OAI21XLTS U1022 ( .A0(n1413), .A1(n1805), .B0(n1412), .Y(n1399) );
OAI211XLTS U1023 ( .A0(n1482), .A1(n961), .B0(n1424), .C0(n1423), .Y(n1467)
);
OAI21XLTS U1024 ( .A0(n1413), .A1(n1806), .B0(n1412), .Y(n1403) );
OAI211XLTS U1025 ( .A0(n1479), .A1(n1753), .B0(n1421), .C0(n1420), .Y(n1470)
);
OAI211XLTS U1026 ( .A0(n1476), .A1(n961), .B0(n1418), .C0(n1417), .Y(n1471)
);
OAI211XLTS U1027 ( .A0(n1473), .A1(n961), .B0(n1411), .C0(n1410), .Y(n1478)
);
OAI211XLTS U1028 ( .A0(n1468), .A1(n1753), .B0(n1405), .C0(n1404), .Y(n1481)
);
NOR3X1TS U1029 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[4]),
.C(n1776), .Y(n1446) );
AOI211XLTS U1030 ( .A0(Data_array_SWR[24]), .A1(n1395), .B0(n1436), .C0(
n1389), .Y(n1459) );
AO22XLTS U1031 ( .A0(Data_array_SWR[20]), .A1(n1409), .B0(Data_array_SWR[16]), .B1(n1415), .Y(n1389) );
NOR3X1TS U1032 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[4]),
.C(n1776), .Y(n980) );
NOR3BXLTS U1033 ( .AN(n1097), .B(Raw_mant_NRM_SWR[12]), .C(
Raw_mant_NRM_SWR[10]), .Y(n1261) );
AOI2BB2XLTS U1034 ( .B0(n991), .B1(n1039), .A0N(n990), .A1N(n989), .Y(n1045)
);
CLKAND2X2TS U1035 ( .A(Shift_reg_FLAGS_7_6), .B(n1046), .Y(n1059) );
NOR3XLTS U1036 ( .A(n1147), .B(n1284), .C(n1146), .Y(n1148) );
NAND3BXLTS U1037 ( .AN(n1289), .B(exp_rslt_NRM2_EW1[5]), .C(n1145), .Y(n1146) );
OAI21XLTS U1038 ( .A0(n1485), .A1(n1432), .B0(n1431), .Y(n1398) );
OAI21XLTS U1039 ( .A0(n1482), .A1(n1432), .B0(n1431), .Y(n1402) );
OAI21XLTS U1040 ( .A0(n1479), .A1(n1432), .B0(n1431), .Y(n1407) );
OAI21XLTS U1041 ( .A0(n1473), .A1(n1432), .B0(n1431), .Y(n1419) );
OAI21XLTS U1042 ( .A0(n1468), .A1(n1432), .B0(n1431), .Y(n1422) );
OAI21XLTS U1043 ( .A0(n1465), .A1(n1432), .B0(n1431), .Y(n1425) );
OAI21XLTS U1044 ( .A0(n1462), .A1(n1432), .B0(n1431), .Y(n1428) );
OAI21XLTS U1045 ( .A0(n1459), .A1(n1432), .B0(n1431), .Y(n1433) );
OAI21XLTS U1046 ( .A0(n1459), .A1(n1490), .B0(n1489), .Y(n1460) );
OAI21XLTS U1047 ( .A0(n1462), .A1(n1490), .B0(n1489), .Y(n1463) );
OAI21XLTS U1048 ( .A0(n1465), .A1(n1490), .B0(n1489), .Y(n1466) );
OAI21XLTS U1049 ( .A0(n1468), .A1(n1490), .B0(n1489), .Y(n1469) );
NAND3XLTS U1050 ( .A(n1475), .B(n1474), .C(n1489), .Y(n1721) );
NAND2BXLTS U1051 ( .AN(n1473), .B(n1472), .Y(n1474) );
NAND2BXLTS U1052 ( .AN(left_right_SHT2), .B(n1471), .Y(n1475) );
OAI21XLTS U1053 ( .A0(n1476), .A1(n1490), .B0(n1489), .Y(n1477) );
OAI21XLTS U1054 ( .A0(n1479), .A1(n1490), .B0(n1489), .Y(n1480) );
OAI21XLTS U1055 ( .A0(n1482), .A1(n1490), .B0(n1489), .Y(n1483) );
OAI211XLTS U1056 ( .A0(n1462), .A1(n961), .B0(n1397), .C0(n1396), .Y(n1487)
);
OAI211XLTS U1057 ( .A0(n1459), .A1(n1753), .B0(n1391), .C0(n1390), .Y(n1493)
);
NAND2BXLTS U1058 ( .AN(n965), .B(n1458), .Y(n1489) );
AOI211XLTS U1059 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n1109), .B0(n1266), .C0(
n1108), .Y(n1110) );
AOI31XLTS U1060 ( .A0(n1099), .A1(n1141), .A2(n1098), .B0(n1636), .Y(n1627)
);
NAND3XLTS U1061 ( .A(Raw_mant_NRM_SWR[8]), .B(n1097), .C(n1770), .Y(n1098)
);
AOI211XLTS U1062 ( .A0(n1262), .A1(Raw_mant_NRM_SWR[6]), .B0(n1093), .C0(
n1092), .Y(n1099) );
XOR2XLTS U1063 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1675) );
NOR2XLTS U1064 ( .A(n1818), .B(DMP_EXP_EWSW[26]), .Y(n1670) );
NAND3XLTS U1065 ( .A(n1301), .B(n1300), .C(n1299), .Y(n1339) );
NAND3XLTS U1066 ( .A(n1326), .B(n1325), .C(n1324), .Y(n1338) );
OAI21XLTS U1067 ( .A0(n1755), .A1(n1310), .B0(n1149), .Y(n1181) );
OAI21XLTS U1068 ( .A0(n1769), .A1(n1373), .B0(n1115), .Y(n1186) );
OAI21XLTS U1069 ( .A0(n1772), .A1(n1310), .B0(n1173), .Y(n1350) );
OAI21XLTS U1070 ( .A0(n1739), .A1(n1310), .B0(n1309), .Y(n1349) );
OAI21XLTS U1071 ( .A0(n1294), .A1(n1820), .B0(n1293), .Y(n1363) );
CLKAND2X2TS U1072 ( .A(beg_OP), .B(n1638), .Y(n1643) );
NAND3XLTS U1073 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1756), .C(
n1810), .Y(n1630) );
OAI21XLTS U1074 ( .A0(n1381), .A1(n1310), .B0(n1268), .Y(n847) );
AO22XLTS U1075 ( .A0(n1629), .A1(n1710), .B0(final_result_ieee[31]), .B1(
n1628), .Y(n621) );
NAND2BXLTS U1076 ( .AN(SIGN_FLAG_SHT1SHT2), .B(n1709), .Y(n1629) );
OAI211XLTS U1077 ( .A0(n1282), .A1(n1736), .B0(n1288), .C0(n1281), .Y(n836)
);
OAI211XLTS U1078 ( .A0(n1289), .A1(n1736), .B0(n1288), .C0(n1287), .Y(n837)
);
OAI211XLTS U1079 ( .A0(n1278), .A1(n1736), .B0(n1288), .C0(n1277), .Y(n838)
);
OAI211XLTS U1080 ( .A0(n1286), .A1(n1736), .B0(n1288), .C0(n1285), .Y(n839)
);
OAI211XLTS U1081 ( .A0(n1280), .A1(n1736), .B0(n1288), .C0(n1279), .Y(n840)
);
OAI211XLTS U1082 ( .A0(n1276), .A1(n1736), .B0(n1288), .C0(n1275), .Y(n841)
);
AOI2BB1XLTS U1083 ( .A0N(Shift_reg_FLAGS_7[0]), .A1N(overflow_flag), .B0(
n1710), .Y(n638) );
AO22XLTS U1084 ( .A0(n1710), .A1(exp_rslt_NRM2_EW1[7]), .B0(
final_result_ieee[30]), .B1(n1628), .Y(n834) );
AO21XLTS U1085 ( .A0(underflow_flag), .A1(n1734), .B0(n1697), .Y(n639) );
AOI2BB2XLTS U1086 ( .B0(left_right_SHT2), .B1(n1493), .A0N(n1491), .A1N(
n1432), .Y(n1392) );
MXI2XLTS U1087 ( .A(n1738), .B(n1828), .S0(n1705), .Y(n542) );
MXI2XLTS U1088 ( .A(n1735), .B(n1829), .S0(n1705), .Y(n543) );
MXI2XLTS U1089 ( .A(n1733), .B(n1830), .S0(n1705), .Y(n544) );
MXI2XLTS U1090 ( .A(n1732), .B(n1831), .S0(n1705), .Y(n545) );
MXI2XLTS U1091 ( .A(n1731), .B(n1832), .S0(n1454), .Y(n546) );
MXI2XLTS U1092 ( .A(n1730), .B(n1842), .S0(n1454), .Y(n547) );
MXI2XLTS U1093 ( .A(n1729), .B(n1833), .S0(n1454), .Y(n548) );
MXI2XLTS U1094 ( .A(n1728), .B(n1843), .S0(n1454), .Y(n549) );
MXI2XLTS U1095 ( .A(n1727), .B(n1834), .S0(n1454), .Y(n550) );
MXI2XLTS U1096 ( .A(n1716), .B(n1844), .S0(n1454), .Y(n551) );
MXI2XLTS U1097 ( .A(n1714), .B(n1835), .S0(n1454), .Y(n552) );
MXI2XLTS U1098 ( .A(n1712), .B(n1845), .S0(n1454), .Y(n553) );
MXI2XLTS U1099 ( .A(n1711), .B(n1836), .S0(n1454), .Y(n554) );
MXI2XLTS U1100 ( .A(n1713), .B(n1846), .S0(n1454), .Y(n555) );
MXI2XLTS U1101 ( .A(n1715), .B(n1837), .S0(n1494), .Y(n556) );
MXI2XLTS U1102 ( .A(n1717), .B(n1847), .S0(n1494), .Y(n557) );
MXI2XLTS U1103 ( .A(n1718), .B(n1838), .S0(n1494), .Y(n558) );
MXI2XLTS U1104 ( .A(n1719), .B(n1848), .S0(n1494), .Y(n559) );
MXI2XLTS U1105 ( .A(n1720), .B(n1839), .S0(n1494), .Y(n560) );
MX2X1TS U1106 ( .A(n1721), .B(DmP_mant_SFG_SWR[5]), .S0(n1705), .Y(n561) );
MXI2XLTS U1107 ( .A(n1723), .B(n1840), .S0(n1494), .Y(n562) );
MXI2XLTS U1108 ( .A(n1724), .B(n1849), .S0(n1494), .Y(n563) );
MXI2XLTS U1109 ( .A(n1726), .B(n1825), .S0(n1494), .Y(n564) );
MXI2XLTS U1110 ( .A(n1488), .B(n1850), .S0(n1494), .Y(n565) );
OAI21XLTS U1111 ( .A0(n1485), .A1(n1490), .B0(n1489), .Y(n1486) );
MXI2XLTS U1112 ( .A(n1495), .B(n1766), .S0(n1494), .Y(n566) );
OAI21XLTS U1113 ( .A0(n1491), .A1(n1490), .B0(n1489), .Y(n1492) );
MX2X1TS U1114 ( .A(n1626), .B(LZD_output_NRM2_EW[1]), .S0(n1636), .Y(n591)
);
OAI21XLTS U1115 ( .A0(n1708), .A1(n1144), .B0(n1143), .Y(n592) );
AO21XLTS U1116 ( .A0(LZD_output_NRM2_EW[0]), .A1(n1636), .B0(n1627), .Y(n593) );
MXI2XLTS U1117 ( .A(n1820), .B(n1766), .S0(Shift_reg_FLAGS_7[2]), .Y(n620)
);
AO22XLTS U1118 ( .A0(n1496), .A1(n1570), .B0(ADD_OVRFLW_NRM), .B1(n1634),
.Y(n628) );
OAI21XLTS U1119 ( .A0(n1760), .A1(n1695), .B0(n1201), .Y(n646) );
OAI21XLTS U1120 ( .A0(n1795), .A1(n1695), .B0(n1199), .Y(n650) );
OAI21XLTS U1121 ( .A0(n1790), .A1(n1376), .B0(n1047), .Y(n664) );
OAI21XLTS U1122 ( .A0(n1783), .A1(n1376), .B0(n1048), .Y(n668) );
OAI21XLTS U1123 ( .A0(n1799), .A1(n1198), .B0(n1064), .Y(n684) );
OAI21XLTS U1124 ( .A0(n1798), .A1(n1243), .B0(n1192), .Y(n690) );
OAI21XLTS U1125 ( .A0(n1247), .A1(n1676), .B0(n1243), .Y(n1245) );
OAI21XLTS U1126 ( .A0(n1741), .A1(n1243), .B0(n1195), .Y(n803) );
OAI21XLTS U1127 ( .A0(n1804), .A1(n1243), .B0(n1193), .Y(n804) );
OAI21XLTS U1128 ( .A0(n1760), .A1(n1696), .B0(n1063), .Y(n811) );
OAI21XLTS U1129 ( .A0(n1790), .A1(n1207), .B0(n1049), .Y(n820) );
OAI21XLTS U1130 ( .A0(n1783), .A1(n1131), .B0(n1060), .Y(n822) );
OAI21XLTS U1131 ( .A0(n1802), .A1(n1696), .B0(n1128), .Y(n832) );
OAI21XLTS U1132 ( .A0(n1798), .A1(n1207), .B0(n1203), .Y(n833) );
XOR2XLTS U1133 ( .A(n1672), .B(n1671), .Y(n1673) );
OAI211XLTS U1134 ( .A0(n1342), .A1(n1365), .B0(n1322), .C0(n1321), .Y(n852)
);
OAI211XLTS U1135 ( .A0(n1362), .A1(n1365), .B0(n1330), .C0(n1329), .Y(n855)
);
OAI211XLTS U1136 ( .A0(n1328), .A1(n1365), .B0(n1167), .C0(n1166), .Y(n857)
);
OAI211XLTS U1137 ( .A0(n1184), .A1(n1365), .B0(n1154), .C0(n1153), .Y(n859)
);
OAI211XLTS U1138 ( .A0(n1190), .A1(n1365), .B0(n1164), .C0(n1163), .Y(n861)
);
OAI211XLTS U1139 ( .A0(n1176), .A1(n1365), .B0(n1161), .C0(n1160), .Y(n867)
);
OAI211XLTS U1140 ( .A0(n1353), .A1(n1365), .B0(n1318), .C0(n1317), .Y(n869)
);
OAI211XLTS U1141 ( .A0(n1347), .A1(n1365), .B0(n1333), .C0(n1332), .Y(n871)
);
OAI211XLTS U1142 ( .A0(n1368), .A1(n1365), .B0(n1312), .C0(n1311), .Y(n873)
);
OAI21XLTS U1143 ( .A0(n1656), .A1(n1372), .B0(n1371), .Y(n874) );
OAI21XLTS U1144 ( .A0(n1144), .A1(n1310), .B0(n1142), .Y(n850) );
OAI21XLTS U1145 ( .A0(n1378), .A1(n1310), .B0(n1259), .Y(n849) );
AO22XLTS U1146 ( .A0(n1653), .A1(Data_Y[31]), .B0(n1652), .B1(intDY_EWSW[31]), .Y(n879) );
AO22XLTS U1147 ( .A0(n1653), .A1(Data_Y[30]), .B0(n1651), .B1(intDY_EWSW[30]), .Y(n880) );
AO22XLTS U1148 ( .A0(n1653), .A1(Data_Y[29]), .B0(n1651), .B1(intDY_EWSW[29]), .Y(n881) );
AO22XLTS U1149 ( .A0(n1650), .A1(Data_Y[28]), .B0(n1651), .B1(intDY_EWSW[28]), .Y(n882) );
AO22XLTS U1150 ( .A0(n1649), .A1(intDY_EWSW[27]), .B0(n1648), .B1(Data_Y[27]), .Y(n883) );
AO22XLTS U1151 ( .A0(n1649), .A1(intDY_EWSW[26]), .B0(n1648), .B1(Data_Y[26]), .Y(n884) );
AO22XLTS U1152 ( .A0(n1649), .A1(intDY_EWSW[25]), .B0(n1648), .B1(Data_Y[25]), .Y(n885) );
AO22XLTS U1153 ( .A0(n1649), .A1(intDY_EWSW[24]), .B0(n1648), .B1(Data_Y[24]), .Y(n886) );
AO22XLTS U1154 ( .A0(n1649), .A1(intDY_EWSW[23]), .B0(n1647), .B1(Data_Y[23]), .Y(n887) );
AO22XLTS U1155 ( .A0(n1649), .A1(intDY_EWSW[22]), .B0(n1647), .B1(Data_Y[22]), .Y(n888) );
AO22XLTS U1156 ( .A0(n1649), .A1(intDY_EWSW[21]), .B0(n1647), .B1(Data_Y[21]), .Y(n889) );
AO22XLTS U1157 ( .A0(n1649), .A1(intDY_EWSW[20]), .B0(n1647), .B1(Data_Y[20]), .Y(n890) );
AO22XLTS U1158 ( .A0(n1649), .A1(intDY_EWSW[19]), .B0(n1646), .B1(Data_Y[19]), .Y(n891) );
AO22XLTS U1159 ( .A0(n1649), .A1(intDY_EWSW[18]), .B0(n1646), .B1(Data_Y[18]), .Y(n892) );
AO22XLTS U1160 ( .A0(n1644), .A1(intDY_EWSW[17]), .B0(n1646), .B1(Data_Y[17]), .Y(n893) );
AO22XLTS U1161 ( .A0(n1644), .A1(intDY_EWSW[16]), .B0(n1646), .B1(Data_Y[16]), .Y(n894) );
AO22XLTS U1162 ( .A0(n1644), .A1(intDY_EWSW[15]), .B0(n1643), .B1(Data_Y[15]), .Y(n895) );
AO22XLTS U1163 ( .A0(n1644), .A1(intDY_EWSW[14]), .B0(n1646), .B1(Data_Y[14]), .Y(n896) );
AO22XLTS U1164 ( .A0(n1644), .A1(intDY_EWSW[13]), .B0(n1648), .B1(Data_Y[13]), .Y(n897) );
AO22XLTS U1165 ( .A0(n1644), .A1(intDY_EWSW[12]), .B0(n1648), .B1(Data_Y[12]), .Y(n898) );
AO22XLTS U1166 ( .A0(n1644), .A1(intDY_EWSW[11]), .B0(n1648), .B1(Data_Y[11]), .Y(n899) );
AO22XLTS U1167 ( .A0(n1644), .A1(intDY_EWSW[10]), .B0(n1648), .B1(Data_Y[10]), .Y(n900) );
AO22XLTS U1168 ( .A0(n1644), .A1(intDY_EWSW[9]), .B0(n1645), .B1(Data_Y[9]),
.Y(n901) );
AO22XLTS U1169 ( .A0(n1644), .A1(intDY_EWSW[8]), .B0(n1645), .B1(Data_Y[8]),
.Y(n902) );
AO22XLTS U1170 ( .A0(n1642), .A1(intDY_EWSW[7]), .B0(n1645), .B1(Data_Y[7]),
.Y(n903) );
AO22XLTS U1171 ( .A0(n1642), .A1(intDY_EWSW[6]), .B0(n1645), .B1(Data_Y[6]),
.Y(n904) );
AO22XLTS U1172 ( .A0(n1642), .A1(intDY_EWSW[5]), .B0(n1645), .B1(Data_Y[5]),
.Y(n905) );
AO22XLTS U1173 ( .A0(n1642), .A1(intDY_EWSW[4]), .B0(n1645), .B1(Data_Y[4]),
.Y(n906) );
AO22XLTS U1174 ( .A0(n1642), .A1(intDY_EWSW[3]), .B0(n1646), .B1(Data_Y[3]),
.Y(n907) );
AO22XLTS U1175 ( .A0(n1642), .A1(intDY_EWSW[2]), .B0(n1646), .B1(Data_Y[2]),
.Y(n908) );
AO22XLTS U1176 ( .A0(n1642), .A1(intDY_EWSW[1]), .B0(n1646), .B1(Data_Y[1]),
.Y(n909) );
AO22XLTS U1177 ( .A0(n1642), .A1(intDY_EWSW[0]), .B0(n1646), .B1(Data_Y[0]),
.Y(n910) );
AO22XLTS U1178 ( .A0(n1650), .A1(add_subt), .B0(n1641), .B1(intAS), .Y(n911)
);
AO22XLTS U1179 ( .A0(n1650), .A1(Data_X[31]), .B0(n1641), .B1(intDX_EWSW[31]), .Y(n912) );
AO22XLTS U1180 ( .A0(n1642), .A1(intDX_EWSW[30]), .B0(n1647), .B1(Data_X[30]), .Y(n913) );
AO22XLTS U1181 ( .A0(n1642), .A1(intDX_EWSW[29]), .B0(n1643), .B1(Data_X[29]), .Y(n914) );
AO22XLTS U1182 ( .A0(n1641), .A1(intDX_EWSW[28]), .B0(n1645), .B1(Data_X[28]), .Y(n915) );
AO22XLTS U1183 ( .A0(n1653), .A1(Data_X[27]), .B0(n1641), .B1(intDX_EWSW[27]), .Y(n916) );
AO22XLTS U1184 ( .A0(n1641), .A1(intDX_EWSW[26]), .B0(n1645), .B1(Data_X[26]), .Y(n917) );
AO22XLTS U1185 ( .A0(n1641), .A1(intDX_EWSW[25]), .B0(n1645), .B1(Data_X[25]), .Y(n918) );
AO22XLTS U1186 ( .A0(n1641), .A1(intDX_EWSW[24]), .B0(n1648), .B1(Data_X[24]), .Y(n919) );
AO22XLTS U1187 ( .A0(n1653), .A1(Data_X[23]), .B0(n1641), .B1(intDX_EWSW[23]), .Y(n920) );
AO22XLTS U1188 ( .A0(n1653), .A1(Data_X[22]), .B0(n1641), .B1(intDX_EWSW[22]), .Y(n921) );
AO22XLTS U1189 ( .A0(n1653), .A1(Data_X[21]), .B0(n1641), .B1(intDX_EWSW[21]), .Y(n922) );
AO22XLTS U1190 ( .A0(n1653), .A1(Data_X[20]), .B0(n1652), .B1(intDX_EWSW[20]), .Y(n923) );
AO22XLTS U1191 ( .A0(n1640), .A1(Data_X[19]), .B0(n1652), .B1(intDX_EWSW[19]), .Y(n924) );
AO22XLTS U1192 ( .A0(n1650), .A1(Data_X[18]), .B0(n1652), .B1(intDX_EWSW[18]), .Y(n925) );
AO22XLTS U1193 ( .A0(n1640), .A1(Data_X[17]), .B0(n1652), .B1(intDX_EWSW[17]), .Y(n926) );
AO22XLTS U1194 ( .A0(n1640), .A1(Data_X[16]), .B0(n1652), .B1(intDX_EWSW[16]), .Y(n927) );
AO22XLTS U1195 ( .A0(n1640), .A1(Data_X[15]), .B0(n1652), .B1(intDX_EWSW[15]), .Y(n928) );
AO22XLTS U1196 ( .A0(n1650), .A1(Data_X[14]), .B0(n1652), .B1(intDX_EWSW[14]), .Y(n929) );
AO22XLTS U1197 ( .A0(n1650), .A1(Data_X[13]), .B0(n1652), .B1(intDX_EWSW[13]), .Y(n930) );
AO22XLTS U1198 ( .A0(n1650), .A1(Data_X[12]), .B0(n1652), .B1(intDX_EWSW[12]), .Y(n931) );
AO22XLTS U1199 ( .A0(n1650), .A1(Data_X[11]), .B0(n1639), .B1(intDX_EWSW[11]), .Y(n932) );
AO22XLTS U1200 ( .A0(n1650), .A1(Data_X[10]), .B0(n1639), .B1(intDX_EWSW[10]), .Y(n933) );
AO22XLTS U1201 ( .A0(n1653), .A1(Data_X[9]), .B0(n1639), .B1(intDX_EWSW[9]),
.Y(n934) );
AO22XLTS U1202 ( .A0(n1647), .A1(Data_X[8]), .B0(n1639), .B1(intDX_EWSW[8]),
.Y(n935) );
AO22XLTS U1203 ( .A0(n1647), .A1(Data_X[7]), .B0(n1639), .B1(intDX_EWSW[7]),
.Y(n936) );
AO22XLTS U1204 ( .A0(n1647), .A1(Data_X[6]), .B0(n1639), .B1(intDX_EWSW[6]),
.Y(n937) );
AO22XLTS U1205 ( .A0(n1647), .A1(Data_X[5]), .B0(n1639), .B1(intDX_EWSW[5]),
.Y(n938) );
AO22XLTS U1206 ( .A0(n1640), .A1(Data_X[4]), .B0(n1639), .B1(intDX_EWSW[4]),
.Y(n939) );
AO22XLTS U1207 ( .A0(n1640), .A1(Data_X[3]), .B0(n1639), .B1(intDX_EWSW[3]),
.Y(n940) );
AO22XLTS U1208 ( .A0(n1640), .A1(Data_X[2]), .B0(n1639), .B1(intDX_EWSW[2]),
.Y(n941) );
AO22XLTS U1209 ( .A0(n1640), .A1(Data_X[1]), .B0(n1651), .B1(intDX_EWSW[1]),
.Y(n942) );
AO22XLTS U1210 ( .A0(n1640), .A1(Data_X[0]), .B0(n1651), .B1(intDX_EWSW[0]),
.Y(n943) );
MXI2XLTS U1211 ( .A(n1620), .B(n1765), .S0(n1637), .Y(n946) );
AO22XLTS U1212 ( .A0(n1635), .A1(Shift_reg_FLAGS_7_6), .B0(n1637), .B1(n1638), .Y(n950) );
OAI21XLTS U1213 ( .A0(n1632), .A1(n1191), .B0(n1630), .Y(n951) );
AOI2BB2XLTS U1214 ( .B0(beg_OP), .B1(n1756), .A0N(n1756), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1191) );
OR2X1TS U1215 ( .A(n1364), .B(n1372), .Y(n955) );
NOR2X1TS U1216 ( .A(n1114), .B(n1655), .Y(n1331) );
OR2X1TS U1217 ( .A(shift_value_SHT2_EWR[4]), .B(n1406), .Y(n956) );
OR2X1TS U1218 ( .A(shift_value_SHT2_EWR[4]), .B(n1413), .Y(n957) );
INVX2TS U1219 ( .A(n1331), .Y(n958) );
INVX2TS U1220 ( .A(n958), .Y(n959) );
INVX2TS U1221 ( .A(n1359), .Y(n960) );
INVX2TS U1222 ( .A(n957), .Y(n962) );
INVX2TS U1223 ( .A(n957), .Y(n963) );
INVX2TS U1224 ( .A(n1771), .Y(n964) );
INVX2TS U1225 ( .A(n964), .Y(n965) );
INVX2TS U1226 ( .A(n955), .Y(n967) );
INVX2TS U1227 ( .A(n955), .Y(n968) );
INVX2TS U1228 ( .A(n955), .Y(n969) );
INVX2TS U1229 ( .A(n956), .Y(n970) );
INVX2TS U1230 ( .A(n956), .Y(n971) );
INVX2TS U1231 ( .A(n1449), .Y(n972) );
INVX2TS U1232 ( .A(n1684), .Y(n973) );
INVX2TS U1233 ( .A(Shift_reg_FLAGS_7[2]), .Y(n1684) );
OAI21XLTS U1234 ( .A0(n1366), .A1(n958), .B0(n1295), .Y(n875) );
OAI211XLTS U1235 ( .A0(n1342), .A1(n1367), .B0(n1341), .C0(n1340), .Y(n853)
);
OAI211XLTS U1236 ( .A0(n1353), .A1(n958), .B0(n1352), .C0(n1351), .Y(n870)
);
OAI211XLTS U1237 ( .A0(n1347), .A1(n958), .B0(n1346), .C0(n1345), .Y(n872)
);
OAI211XLTS U1238 ( .A0(n1336), .A1(n1367), .B0(n1335), .C0(n1334), .Y(n854)
);
OAI211XLTS U1239 ( .A0(n1362), .A1(n1367), .B0(n1361), .C0(n1360), .Y(n856)
);
OAI211XLTS U1240 ( .A0(n1172), .A1(n1367), .B0(n1171), .C0(n1170), .Y(n866)
);
OAI211XLTS U1241 ( .A0(n1176), .A1(n1367), .B0(n1175), .C0(n1174), .Y(n868)
);
OAI211XLTS U1242 ( .A0(n1328), .A1(n1367), .B0(n1179), .C0(n1178), .Y(n858)
);
OAI211XLTS U1243 ( .A0(n1190), .A1(n1367), .B0(n1189), .C0(n1188), .Y(n862)
);
OAI211XLTS U1244 ( .A0(n1184), .A1(n1367), .B0(n1183), .C0(n1182), .Y(n860)
);
NOR2X1TS U1245 ( .A(n1655), .B(n1364), .Y(n974) );
NOR2XLTS U1246 ( .A(n1655), .B(n1364), .Y(n1359) );
NAND2X1TS U1247 ( .A(n1710), .B(n1709), .Y(n975) );
NAND2X1TS U1248 ( .A(n1710), .B(n1709), .Y(n976) );
NAND2X1TS U1249 ( .A(n1710), .B(n1709), .Y(n1737) );
NOR2X1TS U1250 ( .A(n1114), .B(n1372), .Y(n977) );
NOR2X1TS U1251 ( .A(n1114), .B(n1372), .Y(n978) );
INVX2TS U1252 ( .A(n1355), .Y(n1305) );
NOR2XLTS U1253 ( .A(n1114), .B(n1372), .Y(n1355) );
OAI211XLTS U1254 ( .A0(n1162), .A1(n960), .B0(n1123), .C0(n1122), .Y(n863)
);
OAI211XLTS U1255 ( .A0(n1162), .A1(n1367), .B0(n1118), .C0(n1117), .Y(n864)
);
INVX2TS U1256 ( .A(n1777), .Y(n979) );
INVX2TS U1257 ( .A(Shift_reg_FLAGS_7[1]), .Y(n1150) );
NOR2XLTS U1258 ( .A(n1269), .B(exp_rslt_NRM2_EW1[4]), .Y(n1270) );
OR2X1TS U1259 ( .A(LZD_output_NRM2_EW[0]), .B(ADD_OVRFLW_NRM2), .Y(n1386) );
OAI21XLTS U1260 ( .A0(n1413), .A1(n1809), .B0(n1412), .Y(n1414) );
AOI211XLTS U1261 ( .A0(n1037), .A1(n1036), .B0(n1035), .C0(n1034), .Y(n1043)
);
AOI211XLTS U1262 ( .A0(Data_array_SWR[25]), .A1(n1395), .B0(n1436), .C0(
n1394), .Y(n1462) );
NOR2XLTS U1263 ( .A(Raw_mant_NRM_SWR[25]), .B(Raw_mant_NRM_SWR[24]), .Y(
n1104) );
NOR2XLTS U1264 ( .A(n1762), .B(DMP_EXP_EWSW[24]), .Y(n1661) );
NOR2XLTS U1265 ( .A(n1086), .B(Raw_mant_NRM_SWR[19]), .Y(n1137) );
OAI21XLTS U1266 ( .A0(n1476), .A1(n1432), .B0(n1431), .Y(n1416) );
OAI211XLTS U1267 ( .A0(n1491), .A1(n1753), .B0(n1430), .C0(n1429), .Y(n1461)
);
OAI211XLTS U1268 ( .A0(n1465), .A1(n961), .B0(n1401), .C0(n1400), .Y(n1484)
);
OAI21XLTS U1269 ( .A0(DmP_EXP_EWSW[25]), .A1(n1813), .B0(n1666), .Y(n1663)
);
OAI21XLTS U1270 ( .A0(n1768), .A1(n1373), .B0(n1157), .Y(n1316) );
INVX2TS U1271 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1725) );
OAI211XLTS U1272 ( .A0(n1112), .A1(n1111), .B0(n1110), .C0(n1250), .Y(n1626)
);
OR2X1TS U1273 ( .A(n1501), .B(DmP_mant_SFG_SWR[25]), .Y(n1496) );
AND3X1TS U1274 ( .A(n1298), .B(n1297), .C(n1296), .Y(n1342) );
OAI211XLTS U1275 ( .A0(n1284), .A1(n1736), .B0(n1288), .C0(n1283), .Y(n835)
);
OAI21XLTS U1276 ( .A0(n1802), .A1(n1198), .B0(n1197), .Y(n688) );
OAI21XLTS U1277 ( .A0(n1795), .A1(n1207), .B0(n1206), .Y(n813) );
OAI21XLTS U1278 ( .A0(n1799), .A1(n1131), .B0(n1062), .Y(n830) );
OAI211XLTS U1279 ( .A0(n1342), .A1(n1305), .B0(n1304), .C0(n1303), .Y(n851)
);
OAI211XLTS U1280 ( .A0(n1172), .A1(n960), .B0(n1156), .C0(n1155), .Y(n865)
);
NOR2XLTS U1281 ( .A(n1787), .B(intDX_EWSW[25]), .Y(n1040) );
NOR2XLTS U1282 ( .A(intDY_EWSW[24]), .B(n1040), .Y(n982) );
AOI22X1TS U1283 ( .A0(intDX_EWSW[24]), .A1(n982), .B0(intDX_EWSW[25]), .B1(
n1787), .Y(n986) );
OAI21XLTS U1284 ( .A0(intDX_EWSW[26]), .A1(n1786), .B0(n983), .Y(n1041) );
NOR2XLTS U1285 ( .A(n1782), .B(intDX_EWSW[30]), .Y(n989) );
NOR2XLTS U1286 ( .A(n1754), .B(intDX_EWSW[29]), .Y(n987) );
AOI211XLTS U1287 ( .A0(intDY_EWSW[28]), .A1(n1808), .B0(n989), .C0(n987),
.Y(n1039) );
NOR3XLTS U1288 ( .A(n1808), .B(intDY_EWSW[28]), .C(n987), .Y(n988) );
AOI221XLTS U1289 ( .A0(intDX_EWSW[30]), .A1(n1782), .B0(intDX_EWSW[29]),
.B1(n1754), .C0(n988), .Y(n990) );
NOR2XLTS U1290 ( .A(n1797), .B(intDX_EWSW[17]), .Y(n1027) );
OA22X1TS U1291 ( .A0(n1759), .A1(intDX_EWSW[14]), .B0(n1800), .B1(
intDX_EWSW[15]), .Y(n1018) );
OAI211XLTS U1292 ( .A0(intDX_EWSW[12]), .A1(n1794), .B0(n1018), .C0(n992),
.Y(n1022) );
OAI2BB1X1TS U1293 ( .A0N(n1752), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n993) );
OAI22X1TS U1294 ( .A0(intDY_EWSW[4]), .A1(n993), .B0(n1752), .B1(
intDY_EWSW[5]), .Y(n1004) );
OAI2BB1X1TS U1295 ( .A0N(n1751), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n994) );
OAI22X1TS U1296 ( .A0(intDY_EWSW[6]), .A1(n994), .B0(n1751), .B1(
intDY_EWSW[7]), .Y(n1003) );
OAI21XLTS U1297 ( .A0(intDX_EWSW[1]), .A1(n1802), .B0(intDX_EWSW[0]), .Y(
n995) );
OAI2BB2XLTS U1298 ( .B0(intDY_EWSW[0]), .B1(n995), .A0N(intDX_EWSW[1]),
.A1N(n1802), .Y(n997) );
OAI211XLTS U1299 ( .A0(n1799), .A1(intDX_EWSW[3]), .B0(n997), .C0(n996), .Y(
n1000) );
OAI21XLTS U1300 ( .A0(intDX_EWSW[3]), .A1(n1799), .B0(intDX_EWSW[2]), .Y(
n998) );
AOI222XLTS U1301 ( .A0(intDY_EWSW[4]), .A1(n1774), .B0(n1000), .B1(n999),
.C0(intDY_EWSW[5]), .C1(n1752), .Y(n1002) );
AOI22X1TS U1302 ( .A0(intDY_EWSW[7]), .A1(n1751), .B0(intDY_EWSW[6]), .B1(
n1781), .Y(n1001) );
OAI32X1TS U1303 ( .A0(n1004), .A1(n1003), .A2(n1002), .B0(n1001), .B1(n1003),
.Y(n1021) );
OAI22X1TS U1304 ( .A0(n1778), .A1(intDX_EWSW[10]), .B0(n1783), .B1(
intDX_EWSW[11]), .Y(n1224) );
INVX2TS U1305 ( .A(n1224), .Y(n1011) );
OAI211XLTS U1306 ( .A0(intDX_EWSW[8]), .A1(n1801), .B0(n1008), .C0(n1011),
.Y(n1020) );
OAI21XLTS U1307 ( .A0(intDX_EWSW[13]), .A1(n1790), .B0(intDX_EWSW[12]), .Y(
n1005) );
OAI2BB2XLTS U1308 ( .B0(intDY_EWSW[12]), .B1(n1005), .A0N(intDX_EWSW[13]),
.A1N(n1790), .Y(n1017) );
NOR2XLTS U1309 ( .A(n1783), .B(intDX_EWSW[11]), .Y(n1006) );
AOI22X1TS U1310 ( .A0(intDX_EWSW[10]), .A1(n1007), .B0(intDX_EWSW[11]), .B1(
n1783), .Y(n1013) );
AOI21X1TS U1311 ( .A0(n1010), .A1(n1009), .B0(n1022), .Y(n1012) );
OAI2BB2XLTS U1312 ( .B0(n1013), .B1(n1022), .A0N(n1012), .A1N(n1011), .Y(
n1016) );
OAI21XLTS U1313 ( .A0(intDX_EWSW[15]), .A1(n1800), .B0(intDX_EWSW[14]), .Y(
n1014) );
OAI2BB2XLTS U1314 ( .B0(intDY_EWSW[14]), .B1(n1014), .A0N(intDX_EWSW[15]),
.A1N(n1800), .Y(n1015) );
OAI31X1TS U1315 ( .A0(n1022), .A1(n1021), .A2(n1020), .B0(n1019), .Y(n1025)
);
OA22X1TS U1316 ( .A0(n1760), .A1(intDX_EWSW[22]), .B0(n1815), .B1(
intDX_EWSW[23]), .Y(n1037) );
OAI211XLTS U1317 ( .A0(intDX_EWSW[20]), .A1(n1795), .B0(n1037), .C0(n1023),
.Y(n1032) );
OAI21XLTS U1318 ( .A0(intDX_EWSW[18]), .A1(n1811), .B0(n1029), .Y(n1216) );
OAI21XLTS U1319 ( .A0(intDX_EWSW[21]), .A1(n1791), .B0(intDX_EWSW[20]), .Y(
n1026) );
OAI2BB2XLTS U1320 ( .B0(intDY_EWSW[20]), .B1(n1026), .A0N(intDX_EWSW[21]),
.A1N(n1791), .Y(n1036) );
AOI22X1TS U1321 ( .A0(intDX_EWSW[16]), .A1(n1028), .B0(intDX_EWSW[17]), .B1(
n1797), .Y(n1031) );
AOI32X1TS U1322 ( .A0(n1029), .A1(n1811), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1761), .Y(n1030) );
OAI32X1TS U1323 ( .A0(n1216), .A1(n1032), .A2(n1031), .B0(n1030), .B1(n1032),
.Y(n1035) );
OAI21XLTS U1324 ( .A0(intDX_EWSW[23]), .A1(n1815), .B0(intDX_EWSW[22]), .Y(
n1033) );
OAI2BB2XLTS U1325 ( .B0(intDY_EWSW[22]), .B1(n1033), .A0N(intDX_EWSW[23]),
.A1N(n1815), .Y(n1034) );
NAND4BBX1TS U1326 ( .AN(n1041), .BN(n1040), .C(n1039), .D(n1038), .Y(n1042)
);
AOI32X1TS U1327 ( .A0(n1045), .A1(n1044), .A2(n1043), .B0(n1042), .B1(n1045),
.Y(n1046) );
CLKBUFX2TS U1328 ( .A(n1059), .Y(n1202) );
INVX2TS U1329 ( .A(n1202), .Y(n1376) );
CLKBUFX2TS U1330 ( .A(n1817), .Y(n1676) );
CLKBUFX2TS U1331 ( .A(n1200), .Y(n1374) );
CLKBUFX2TS U1332 ( .A(n1817), .Y(n1124) );
AOI22X1TS U1333 ( .A0(intDX_EWSW[13]), .A1(n1374), .B0(DmP_EXP_EWSW[13]),
.B1(n1124), .Y(n1047) );
AOI22X1TS U1334 ( .A0(intDX_EWSW[11]), .A1(n1374), .B0(DmP_EXP_EWSW[11]),
.B1(n1124), .Y(n1048) );
CLKBUFX2TS U1335 ( .A(n1200), .Y(n1194) );
INVX2TS U1336 ( .A(n1194), .Y(n1207) );
CLKBUFX2TS U1337 ( .A(n1059), .Y(n1205) );
CLKBUFX2TS U1338 ( .A(n1817), .Y(n1204) );
AOI22X1TS U1339 ( .A0(intDX_EWSW[13]), .A1(n1205), .B0(DMP_EXP_EWSW[13]),
.B1(n1204), .Y(n1049) );
INVX2TS U1340 ( .A(n1202), .Y(n1198) );
CLKBUFX2TS U1341 ( .A(n1200), .Y(n1196) );
AOI22X1TS U1342 ( .A0(intDX_EWSW[9]), .A1(n1196), .B0(DmP_EXP_EWSW[9]), .B1(
n1124), .Y(n1050) );
OAI21XLTS U1343 ( .A0(n1793), .A1(n1198), .B0(n1050), .Y(n672) );
AOI22X1TS U1344 ( .A0(intDX_EWSW[5]), .A1(n1196), .B0(DmP_EXP_EWSW[5]), .B1(
n1124), .Y(n1051) );
OAI21XLTS U1345 ( .A0(n1758), .A1(n1198), .B0(n1051), .Y(n680) );
CLKBUFX2TS U1346 ( .A(n1817), .Y(n1244) );
AOI22X1TS U1347 ( .A0(intDX_EWSW[4]), .A1(n1196), .B0(DmP_EXP_EWSW[4]), .B1(
n1244), .Y(n1052) );
OAI21XLTS U1348 ( .A0(n1789), .A1(n1198), .B0(n1052), .Y(n682) );
AOI22X1TS U1349 ( .A0(intDX_EWSW[7]), .A1(n1196), .B0(DmP_EXP_EWSW[7]), .B1(
n1124), .Y(n1053) );
OAI21XLTS U1350 ( .A0(n1803), .A1(n1198), .B0(n1053), .Y(n676) );
CLKBUFX2TS U1351 ( .A(n1817), .Y(n1633) );
AOI22X1TS U1352 ( .A0(intDX_EWSW[19]), .A1(n1374), .B0(DmP_EXP_EWSW[19]),
.B1(n1633), .Y(n1054) );
OAI21XLTS U1353 ( .A0(n1761), .A1(n1376), .B0(n1054), .Y(n652) );
AOI22X1TS U1354 ( .A0(intDX_EWSW[14]), .A1(n1374), .B0(DmP_EXP_EWSW[14]),
.B1(n1124), .Y(n1055) );
OAI21XLTS U1355 ( .A0(n1759), .A1(n1376), .B0(n1055), .Y(n662) );
AOI22X1TS U1356 ( .A0(intDX_EWSW[16]), .A1(n1196), .B0(DmP_EXP_EWSW[16]),
.B1(n1124), .Y(n1056) );
OAI21XLTS U1357 ( .A0(n1757), .A1(n1376), .B0(n1056), .Y(n658) );
AOI22X1TS U1358 ( .A0(intDX_EWSW[6]), .A1(n1196), .B0(DmP_EXP_EWSW[6]), .B1(
n1124), .Y(n1057) );
OAI21XLTS U1359 ( .A0(n1788), .A1(n1198), .B0(n1057), .Y(n678) );
AOI22X1TS U1360 ( .A0(intDX_EWSW[10]), .A1(n1196), .B0(DmP_EXP_EWSW[10]),
.B1(n1244), .Y(n1058) );
OAI21XLTS U1361 ( .A0(n1778), .A1(n1198), .B0(n1058), .Y(n670) );
INVX2TS U1362 ( .A(n1194), .Y(n1131) );
CLKBUFX2TS U1363 ( .A(n1059), .Y(n1129) );
AOI22X1TS U1364 ( .A0(intDX_EWSW[11]), .A1(n1129), .B0(DMP_EXP_EWSW[11]),
.B1(n1204), .Y(n1060) );
AOI22X1TS U1365 ( .A0(DmP_EXP_EWSW[27]), .A1(n1633), .B0(intDX_EWSW[27]),
.B1(n1194), .Y(n1061) );
OAI21XLTS U1366 ( .A0(n1796), .A1(n1376), .B0(n1061), .Y(n640) );
CLKBUFX2TS U1367 ( .A(n1817), .Y(n1133) );
AOI22X1TS U1368 ( .A0(intDX_EWSW[3]), .A1(n1202), .B0(DMP_EXP_EWSW[3]), .B1(
n1133), .Y(n1062) );
INVX2TS U1369 ( .A(n1374), .Y(n1696) );
AOI22X1TS U1370 ( .A0(intDX_EWSW[22]), .A1(n1202), .B0(DMP_EXP_EWSW[22]),
.B1(n1204), .Y(n1063) );
AOI22X1TS U1371 ( .A0(intDX_EWSW[3]), .A1(n1196), .B0(DmP_EXP_EWSW[3]), .B1(
n1244), .Y(n1064) );
AOI22X1TS U1372 ( .A0(intDX_EWSW[4]), .A1(n1129), .B0(DMP_EXP_EWSW[4]), .B1(
n1133), .Y(n1065) );
OAI21XLTS U1373 ( .A0(n1789), .A1(n1131), .B0(n1065), .Y(n829) );
AOI22X1TS U1374 ( .A0(intDX_EWSW[6]), .A1(n1129), .B0(DMP_EXP_EWSW[6]), .B1(
n1133), .Y(n1066) );
OAI21XLTS U1375 ( .A0(n1788), .A1(n1131), .B0(n1066), .Y(n827) );
AOI22X1TS U1376 ( .A0(intDX_EWSW[19]), .A1(n1129), .B0(DMP_EXP_EWSW[19]),
.B1(n1204), .Y(n1067) );
OAI21XLTS U1377 ( .A0(n1761), .A1(n1207), .B0(n1067), .Y(n814) );
AOI22X1TS U1378 ( .A0(intDX_EWSW[7]), .A1(n1129), .B0(DMP_EXP_EWSW[7]), .B1(
n1133), .Y(n1068) );
OAI21XLTS U1379 ( .A0(n1803), .A1(n1131), .B0(n1068), .Y(n826) );
AOI22X1TS U1380 ( .A0(intDX_EWSW[14]), .A1(n1205), .B0(DMP_EXP_EWSW[14]),
.B1(n1204), .Y(n1069) );
OAI21XLTS U1381 ( .A0(n1759), .A1(n1207), .B0(n1069), .Y(n819) );
AOI22X1TS U1382 ( .A0(intDX_EWSW[16]), .A1(n1205), .B0(DMP_EXP_EWSW[16]),
.B1(n1204), .Y(n1070) );
OAI21XLTS U1383 ( .A0(n1757), .A1(n1207), .B0(n1070), .Y(n817) );
AOI22X1TS U1384 ( .A0(intDX_EWSW[5]), .A1(n1129), .B0(DMP_EXP_EWSW[5]), .B1(
n1133), .Y(n1071) );
OAI21XLTS U1385 ( .A0(n1758), .A1(n1131), .B0(n1071), .Y(n828) );
AOI22X1TS U1386 ( .A0(intDX_EWSW[9]), .A1(n1129), .B0(DMP_EXP_EWSW[9]), .B1(
n1133), .Y(n1072) );
OAI21XLTS U1387 ( .A0(n1793), .A1(n1131), .B0(n1072), .Y(n824) );
AOI22X1TS U1388 ( .A0(intDX_EWSW[10]), .A1(n1129), .B0(DMP_EXP_EWSW[10]),
.B1(n1133), .Y(n1073) );
OAI21XLTS U1389 ( .A0(n1778), .A1(n1131), .B0(n1073), .Y(n823) );
AOI22X1TS U1390 ( .A0(DMP_EXP_EWSW[27]), .A1(n1633), .B0(intDX_EWSW[27]),
.B1(n1202), .Y(n1074) );
OAI21XLTS U1391 ( .A0(n1796), .A1(n1696), .B0(n1074), .Y(n806) );
INVX2TS U1392 ( .A(n1200), .Y(n1076) );
AOI22X1TS U1393 ( .A0(intDX_EWSW[2]), .A1(n1202), .B0(DMP_EXP_EWSW[2]), .B1(
n1676), .Y(n1075) );
OAI21XLTS U1394 ( .A0(n1792), .A1(n1076), .B0(n1075), .Y(n831) );
AOI22X1TS U1395 ( .A0(intDX_EWSW[18]), .A1(n1374), .B0(DmP_EXP_EWSW[18]),
.B1(n1633), .Y(n1077) );
OAI21XLTS U1396 ( .A0(n1811), .A1(n1376), .B0(n1077), .Y(n654) );
AOI22X1TS U1397 ( .A0(intDX_EWSW[2]), .A1(n1194), .B0(DmP_EXP_EWSW[2]), .B1(
n1244), .Y(n1078) );
OAI21XLTS U1398 ( .A0(n1792), .A1(n1198), .B0(n1078), .Y(n686) );
AOI22X1TS U1399 ( .A0(intDX_EWSW[12]), .A1(n1374), .B0(DmP_EXP_EWSW[12]),
.B1(n1124), .Y(n1079) );
OAI21XLTS U1400 ( .A0(n1794), .A1(n1376), .B0(n1079), .Y(n666) );
INVX2TS U1401 ( .A(n1205), .Y(n1695) );
AOI22X1TS U1402 ( .A0(intDX_EWSW[21]), .A1(n1200), .B0(DmP_EXP_EWSW[21]),
.B1(n1633), .Y(n1080) );
OAI21XLTS U1403 ( .A0(n1791), .A1(n1695), .B0(n1080), .Y(n648) );
AOI222XLTS U1404 ( .A0(n1194), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1676), .C0(intDY_EWSW[23]), .C1(n1202), .Y(n1081) );
INVX2TS U1405 ( .A(n1081), .Y(n644) );
AOI22X1TS U1406 ( .A0(intDX_EWSW[12]), .A1(n1205), .B0(DMP_EXP_EWSW[12]),
.B1(n1133), .Y(n1082) );
OAI21XLTS U1407 ( .A0(n1794), .A1(n1131), .B0(n1082), .Y(n821) );
AOI22X1TS U1408 ( .A0(intDX_EWSW[21]), .A1(n1205), .B0(DMP_EXP_EWSW[21]),
.B1(n1204), .Y(n1083) );
OAI21XLTS U1409 ( .A0(n1791), .A1(n1207), .B0(n1083), .Y(n812) );
AOI222XLTS U1410 ( .A0(n1202), .A1(intDX_EWSW[23]), .B0(DMP_EXP_EWSW[23]),
.B1(n1676), .C0(intDY_EWSW[23]), .C1(n1194), .Y(n1084) );
INVX2TS U1411 ( .A(n1084), .Y(n810) );
CLKBUFX2TS U1412 ( .A(n1150), .Y(n1379) );
OR2X1TS U1413 ( .A(n1379), .B(ADD_OVRFLW_NRM), .Y(n1310) );
CLKBUFX2TS U1414 ( .A(n1310), .Y(n1294) );
INVX2TS U1415 ( .A(n1294), .Y(n1302) );
AOI222XLTS U1416 ( .A0(n1150), .A1(DmP_mant_SHT1_SW[11]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n966), .C0(n1302), .C1(Raw_mant_NRM_SWR[12]), .Y(n1162) );
CLKBUFX2TS U1417 ( .A(n1150), .Y(n1636) );
INVX2TS U1418 ( .A(n1102), .Y(n1086) );
INVX2TS U1419 ( .A(n1137), .Y(n1087) );
NAND2X1TS U1420 ( .A(n1104), .B(n1100), .Y(n1136) );
NAND2X1TS U1421 ( .A(n1090), .B(n1768), .Y(n1251) );
NAND2X1TS U1422 ( .A(n1091), .B(n1769), .Y(n1135) );
INVX2TS U1423 ( .A(n1258), .Y(n1105) );
NAND2X1TS U1424 ( .A(n1770), .B(n1747), .Y(n1260) );
NOR2BX1TS U1425 ( .AN(n1261), .B(n1260), .Y(n1106) );
NOR2BX1TS U1426 ( .AN(n1106), .B(Raw_mant_NRM_SWR[7]), .Y(n1262) );
AOI21X1TS U1427 ( .A0(n1775), .A1(Raw_mant_NRM_SWR[20]), .B0(
Raw_mant_NRM_SWR[22]), .Y(n1088) );
NOR2XLTS U1428 ( .A(n1089), .B(Raw_mant_NRM_SWR[25]), .Y(n1093) );
NAND2X1TS U1429 ( .A(Raw_mant_NRM_SWR[14]), .B(n1091), .Y(n1250) );
NAND2X1TS U1430 ( .A(Raw_mant_NRM_SWR[10]), .B(n1097), .Y(n1254) );
OAI22X1TS U1431 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1254), .B0(n1768), .B1(
n1094), .Y(n1108) );
AOI32X1TS U1432 ( .A0(Raw_mant_NRM_SWR[0]), .A1(n1739), .A2(n1749), .B0(
Raw_mant_NRM_SWR[2]), .B1(n1739), .Y(n1095) );
NAND2X1TS U1433 ( .A(n1262), .B(n1773), .Y(n1138) );
INVX2TS U1434 ( .A(n1364), .Y(n1114) );
INVX2TS U1435 ( .A(n1294), .Y(n1152) );
INVX2TS U1436 ( .A(n1100), .Y(n1101) );
AOI21X1TS U1437 ( .A0(n1103), .A1(n1102), .B0(n1101), .Y(n1112) );
INVX2TS U1438 ( .A(n1104), .Y(n1111) );
NOR2XLTS U1439 ( .A(Raw_mant_NRM_SWR[12]), .B(n1105), .Y(n1109) );
NOR2XLTS U1440 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1253)
);
INVX2TS U1441 ( .A(n1138), .Y(n1267) );
OAI21XLTS U1442 ( .A0(Raw_mant_NRM_SWR[7]), .A1(Raw_mant_NRM_SWR[6]), .B0(
n1106), .Y(n1107) );
CLKBUFX2TS U1443 ( .A(n1150), .Y(n1708) );
CLKBUFX2TS U1444 ( .A(n1826), .Y(n1680) );
NAND2X1TS U1445 ( .A(n1708), .B(n1680), .Y(n1654) );
INVX2TS U1446 ( .A(n959), .Y(n1367) );
INVX2TS U1447 ( .A(n1654), .Y(n1370) );
CLKBUFX2TS U1448 ( .A(n1370), .Y(n1327) );
NAND2X1TS U1449 ( .A(n1654), .B(n1113), .Y(n1372) );
AOI222XLTS U1450 ( .A0(n1708), .A1(DmP_mant_SHT1_SW[13]), .B0(
Raw_mant_NRM_SWR[15]), .B1(n966), .C0(n1302), .C1(Raw_mant_NRM_SWR[10]), .Y(n1172) );
INVX2TS U1451 ( .A(n1172), .Y(n1121) );
AOI22X1TS U1452 ( .A0(n1327), .A1(Data_array_SWR[13]), .B0(n978), .B1(n1121),
.Y(n1118) );
INVX2TS U1453 ( .A(n966), .Y(n1373) );
AOI22X1TS U1454 ( .A0(n1302), .A1(Raw_mant_NRM_SWR[11]), .B0(
DmP_mant_SHT1_SW[12]), .B1(n1150), .Y(n1115) );
AOI22X1TS U1455 ( .A0(n1302), .A1(Raw_mant_NRM_SWR[9]), .B0(
DmP_mant_SHT1_SW[14]), .B1(n1150), .Y(n1116) );
AOI22X1TS U1456 ( .A0(n974), .A1(n1186), .B0(n968), .B1(n1169), .Y(n1117) );
AOI22X1TS U1457 ( .A0(intDY_EWSW[28]), .A1(n1194), .B0(DMP_EXP_EWSW[28]),
.B1(n1244), .Y(n1119) );
OAI21XLTS U1458 ( .A0(n1808), .A1(n1695), .B0(n1119), .Y(n805) );
INVX2TS U1459 ( .A(n1359), .Y(n1365) );
AOI22X1TS U1460 ( .A0(n1327), .A1(Data_array_SWR[12]), .B0(n977), .B1(n1186),
.Y(n1123) );
AOI22X1TS U1461 ( .A0(n1302), .A1(Raw_mant_NRM_SWR[13]), .B0(
DmP_mant_SHT1_SW[10]), .B1(n1150), .Y(n1120) );
AOI22X1TS U1462 ( .A0(n959), .A1(n1187), .B0(n969), .B1(n1121), .Y(n1122) );
AOI22X1TS U1463 ( .A0(intDX_EWSW[8]), .A1(n1196), .B0(DmP_EXP_EWSW[8]), .B1(
n1124), .Y(n1125) );
OAI21XLTS U1464 ( .A0(n1801), .A1(n1198), .B0(n1125), .Y(n674) );
AOI22X1TS U1465 ( .A0(intDX_EWSW[15]), .A1(n1374), .B0(DmP_EXP_EWSW[15]),
.B1(n1633), .Y(n1126) );
OAI21XLTS U1466 ( .A0(n1800), .A1(n1376), .B0(n1126), .Y(n660) );
AOI22X1TS U1467 ( .A0(intDX_EWSW[18]), .A1(n1205), .B0(DMP_EXP_EWSW[18]),
.B1(n1204), .Y(n1127) );
OAI21XLTS U1468 ( .A0(n1811), .A1(n1207), .B0(n1127), .Y(n815) );
AOI22X1TS U1469 ( .A0(intDX_EWSW[1]), .A1(n1129), .B0(DMP_EXP_EWSW[1]), .B1(
n1676), .Y(n1128) );
INVX2TS U1470 ( .A(rst), .Y(n1903) );
CLKBUFX2TS U1471 ( .A(n1903), .Y(n1897) );
CLKBUFX2TS U1472 ( .A(n1897), .Y(n1892) );
CLKBUFX2TS U1473 ( .A(n1892), .Y(n1895) );
CLKBUFX2TS U1474 ( .A(n1895), .Y(n1875) );
CLKBUFX2TS U1475 ( .A(n1895), .Y(n1876) );
CLKBUFX2TS U1476 ( .A(n1903), .Y(n1891) );
CLKBUFX2TS U1477 ( .A(n1891), .Y(n1894) );
CLKBUFX2TS U1478 ( .A(n1894), .Y(n1890) );
CLKBUFX2TS U1479 ( .A(n1890), .Y(n1898) );
CLKBUFX2TS U1480 ( .A(n1898), .Y(n1867) );
CLKBUFX2TS U1481 ( .A(n1894), .Y(n1877) );
CLKBUFX2TS U1482 ( .A(n1898), .Y(n1866) );
CLKBUFX2TS U1483 ( .A(n1895), .Y(n1900) );
CLKBUFX2TS U1484 ( .A(n1900), .Y(n1899) );
CLKBUFX2TS U1485 ( .A(n1899), .Y(n1865) );
CLKBUFX2TS U1486 ( .A(n1898), .Y(n1893) );
CLKBUFX2TS U1487 ( .A(n1893), .Y(n1896) );
CLKBUFX2TS U1488 ( .A(n1896), .Y(n1871) );
CLKBUFX2TS U1489 ( .A(n1897), .Y(n1870) );
CLKBUFX2TS U1490 ( .A(n1896), .Y(n1872) );
CLKBUFX2TS U1491 ( .A(n1896), .Y(n1873) );
CLKBUFX2TS U1492 ( .A(n1903), .Y(n1889) );
CLKBUFX2TS U1493 ( .A(n1889), .Y(n1888) );
CLKBUFX2TS U1494 ( .A(n1898), .Y(n1868) );
CLKBUFX2TS U1495 ( .A(n1895), .Y(n1874) );
CLKBUFX2TS U1496 ( .A(n1897), .Y(n1869) );
CLKBUFX2TS U1497 ( .A(n1889), .Y(n1861) );
CLKBUFX2TS U1498 ( .A(n1890), .Y(n1886) );
CLKBUFX2TS U1499 ( .A(n1890), .Y(n1887) );
CLKBUFX2TS U1500 ( .A(n1899), .Y(n1864) );
CLKBUFX2TS U1501 ( .A(n1889), .Y(n1860) );
CLKBUFX2TS U1502 ( .A(n1889), .Y(n1901) );
CLKBUFX2TS U1503 ( .A(n1901), .Y(n1859) );
CLKBUFX2TS U1504 ( .A(n1901), .Y(n1858) );
CLKBUFX2TS U1505 ( .A(n1901), .Y(n1857) );
CLKBUFX2TS U1506 ( .A(n1892), .Y(n1879) );
CLKBUFX2TS U1507 ( .A(n1899), .Y(n1863) );
CLKBUFX2TS U1508 ( .A(n1891), .Y(n1882) );
CLKBUFX2TS U1509 ( .A(n1893), .Y(n1878) );
CLKBUFX2TS U1510 ( .A(n1891), .Y(n1883) );
CLKBUFX2TS U1511 ( .A(n1892), .Y(n1880) );
CLKBUFX2TS U1512 ( .A(n1892), .Y(n1881) );
CLKBUFX2TS U1513 ( .A(n1900), .Y(n1862) );
CLKBUFX2TS U1514 ( .A(n1891), .Y(n1884) );
CLKBUFX2TS U1515 ( .A(n1890), .Y(n1885) );
OAI21XLTS U1516 ( .A0(n1654), .A1(n1771), .B0(n1310), .Y(n877) );
OAI21XLTS U1517 ( .A0(n1654), .A1(n1812), .B0(n1373), .Y(n878) );
AOI22X1TS U1518 ( .A0(intDX_EWSW[8]), .A1(n1129), .B0(DMP_EXP_EWSW[8]), .B1(
n1133), .Y(n1130) );
OAI21XLTS U1519 ( .A0(n1801), .A1(n1131), .B0(n1130), .Y(n825) );
AOI22X1TS U1520 ( .A0(intDX_EWSW[17]), .A1(n1205), .B0(DMP_EXP_EWSW[17]),
.B1(n1204), .Y(n1132) );
OAI21XLTS U1521 ( .A0(n1797), .A1(n1207), .B0(n1132), .Y(n816) );
AOI22X1TS U1522 ( .A0(intDX_EWSW[15]), .A1(n1205), .B0(DMP_EXP_EWSW[15]),
.B1(n1133), .Y(n1134) );
OAI21XLTS U1523 ( .A0(n1800), .A1(n1207), .B0(n1134), .Y(n818) );
AOI21X1TS U1524 ( .A0(n1823), .A1(n1764), .B0(n1135), .Y(n1248) );
NOR2XLTS U1525 ( .A(n1137), .B(n1136), .Y(n1140) );
OAI22X1TS U1526 ( .A0(n1739), .A1(n1263), .B0(n1138), .B1(n1772), .Y(n1139)
);
CLKBUFX2TS U1527 ( .A(n1370), .Y(n1356) );
AOI32X1TS U1528 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1654), .A2(n1636),
.B0(shift_value_SHT2_EWR[2]), .B1(n1356), .Y(n1142) );
NAND2X1TS U1529 ( .A(n1379), .B(LZD_output_NRM2_EW[2]), .Y(n1143) );
XNOR2X1TS U1530 ( .A(DP_OP_15J1_122_6956_n1), .B(ADD_OVRFLW_NRM2), .Y(n1274)
);
INVX2TS U1531 ( .A(exp_rslt_NRM2_EW1[7]), .Y(n1147) );
INVX2TS U1532 ( .A(exp_rslt_NRM2_EW1[6]), .Y(n1284) );
INVX2TS U1533 ( .A(exp_rslt_NRM2_EW1[4]), .Y(n1289) );
INVX2TS U1534 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n1286) );
INVX2TS U1535 ( .A(exp_rslt_NRM2_EW1[0]), .Y(n1276) );
INVX2TS U1536 ( .A(exp_rslt_NRM2_EW1[1]), .Y(n1280) );
CLKBUFX2TS U1537 ( .A(n1725), .Y(n1628) );
AOI21X1TS U1538 ( .A0(n1274), .A1(n1148), .B0(n1628), .Y(n1710) );
AOI222XLTS U1539 ( .A0(n1708), .A1(DmP_mant_SHT1_SW[7]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n966), .C0(n1152), .C1(Raw_mant_NRM_SWR[16]),
.Y(n1184) );
AOI22X1TS U1540 ( .A0(n1085), .A1(Raw_mant_NRM_SWR[10]), .B0(
DmP_mant_SHT1_SW[8]), .B1(n1150), .Y(n1149) );
AOI22X1TS U1541 ( .A0(n1327), .A1(Data_array_SWR[8]), .B0(n1355), .B1(n1181),
.Y(n1154) );
AOI22X1TS U1542 ( .A0(n1302), .A1(Raw_mant_NRM_SWR[17]), .B0(
DmP_mant_SHT1_SW[6]), .B1(n1150), .Y(n1151) );
AOI222XLTS U1543 ( .A0(n1708), .A1(DmP_mant_SHT1_SW[9]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n966), .C0(n1152), .C1(Raw_mant_NRM_SWR[14]), .Y(n1190) );
INVX2TS U1544 ( .A(n1190), .Y(n1180) );
AOI22X1TS U1545 ( .A0(n1331), .A1(n1357), .B0(n967), .B1(n1180), .Y(n1153)
);
AOI22X1TS U1546 ( .A0(n1327), .A1(Data_array_SWR[14]), .B0(n1355), .B1(n1169), .Y(n1156) );
AOI222XLTS U1547 ( .A0(n1708), .A1(DmP_mant_SHT1_SW[15]), .B0(
Raw_mant_NRM_SWR[17]), .B1(n966), .C0(n1302), .C1(Raw_mant_NRM_SWR[8]),
.Y(n1176) );
INVX2TS U1548 ( .A(n1176), .Y(n1168) );
AOI22X1TS U1549 ( .A0(n1331), .A1(n1186), .B0(n968), .B1(n1168), .Y(n1155)
);
AOI22X1TS U1550 ( .A0(n1302), .A1(Raw_mant_NRM_SWR[7]), .B0(
DmP_mant_SHT1_SW[16]), .B1(n1636), .Y(n1157) );
AOI22X1TS U1551 ( .A0(n1370), .A1(Data_array_SWR[16]), .B0(n978), .B1(n1316),
.Y(n1161) );
INVX2TS U1552 ( .A(n1294), .Y(n1323) );
AOI22X1TS U1553 ( .A0(n1323), .A1(Raw_mant_NRM_SWR[6]), .B0(n1777), .B1(
DmP_mant_SHT1_SW[17]), .Y(n1159) );
NAND2X1TS U1554 ( .A(n1085), .B(Raw_mant_NRM_SWR[19]), .Y(n1158) );
NAND2X1TS U1555 ( .A(n1159), .B(n1158), .Y(n1313) );
AOI22X1TS U1556 ( .A0(n1331), .A1(n1169), .B0(n967), .B1(n1313), .Y(n1160)
);
AOI22X1TS U1557 ( .A0(n1327), .A1(Data_array_SWR[10]), .B0(n1355), .B1(n1187), .Y(n1164) );
INVX2TS U1558 ( .A(n1162), .Y(n1185) );
AOI22X1TS U1559 ( .A0(n1331), .A1(n1181), .B0(n967), .B1(n1185), .Y(n1163)
);
AOI222XLTS U1560 ( .A0(n1708), .A1(DmP_mant_SHT1_SW[5]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n966), .C0(n1302), .C1(Raw_mant_NRM_SWR[18]),
.Y(n1328) );
AOI22X1TS U1561 ( .A0(n1356), .A1(Data_array_SWR[6]), .B0(n978), .B1(n1357),
.Y(n1167) );
AOI22X1TS U1562 ( .A0(n1323), .A1(Raw_mant_NRM_SWR[19]), .B0(n1777), .B1(
DmP_mant_SHT1_SW[4]), .Y(n1165) );
INVX2TS U1563 ( .A(n1184), .Y(n1177) );
AOI22X1TS U1564 ( .A0(n1331), .A1(n1358), .B0(n967), .B1(n1177), .Y(n1166)
);
AOI22X1TS U1565 ( .A0(n1327), .A1(Data_array_SWR[15]), .B0(n978), .B1(n1168),
.Y(n1171) );
AOI22X1TS U1566 ( .A0(n974), .A1(n1169), .B0(n969), .B1(n1316), .Y(n1170) );
AOI22X1TS U1567 ( .A0(n1370), .A1(Data_array_SWR[17]), .B0(n977), .B1(n1313),
.Y(n1175) );
AOI22X1TS U1568 ( .A0(n1085), .A1(Raw_mant_NRM_SWR[20]), .B0(n1777), .B1(
DmP_mant_SHT1_SW[18]), .Y(n1173) );
AOI22X1TS U1569 ( .A0(n974), .A1(n1316), .B0(n968), .B1(n1350), .Y(n1174) );
AOI22X1TS U1570 ( .A0(n1327), .A1(Data_array_SWR[7]), .B0(n977), .B1(n1177),
.Y(n1179) );
AOI22X1TS U1571 ( .A0(n974), .A1(n1357), .B0(n969), .B1(n1181), .Y(n1178) );
AOI22X1TS U1572 ( .A0(n1327), .A1(Data_array_SWR[9]), .B0(n1355), .B1(n1180),
.Y(n1183) );
AOI22X1TS U1573 ( .A0(n1359), .A1(n1181), .B0(n969), .B1(n1187), .Y(n1182)
);
AOI22X1TS U1574 ( .A0(n1327), .A1(Data_array_SWR[11]), .B0(n977), .B1(n1185),
.Y(n1189) );
AOI22X1TS U1575 ( .A0(n1359), .A1(n1187), .B0(n968), .B1(n1186), .Y(n1188)
);
CLKBUFX2TS U1576 ( .A(n1826), .Y(n1686) );
INVX2TS U1577 ( .A(n1686), .Y(busy) );
NOR2XLTS U1578 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1810), .Y(n1632) );
INVX2TS U1579 ( .A(n1202), .Y(n1243) );
AOI22X1TS U1580 ( .A0(intDX_EWSW[0]), .A1(n1194), .B0(DmP_EXP_EWSW[0]), .B1(
n1244), .Y(n1192) );
AOI22X1TS U1581 ( .A0(intDY_EWSW[29]), .A1(n1194), .B0(DMP_EXP_EWSW[29]),
.B1(n1244), .Y(n1193) );
AOI22X1TS U1582 ( .A0(intDY_EWSW[30]), .A1(n1194), .B0(DMP_EXP_EWSW[30]),
.B1(n1244), .Y(n1195) );
AOI22X1TS U1583 ( .A0(intDX_EWSW[1]), .A1(n1196), .B0(DmP_EXP_EWSW[1]), .B1(
n1244), .Y(n1197) );
AOI22X1TS U1584 ( .A0(intDX_EWSW[20]), .A1(n1374), .B0(DmP_EXP_EWSW[20]),
.B1(n1633), .Y(n1199) );
AOI22X1TS U1585 ( .A0(intDX_EWSW[22]), .A1(n1200), .B0(DmP_EXP_EWSW[22]),
.B1(n1633), .Y(n1201) );
AOI22X1TS U1586 ( .A0(intDX_EWSW[0]), .A1(n1202), .B0(DMP_EXP_EWSW[0]), .B1(
n1676), .Y(n1203) );
AOI22X1TS U1587 ( .A0(intDX_EWSW[20]), .A1(n1205), .B0(DMP_EXP_EWSW[20]),
.B1(n1204), .Y(n1206) );
OAI22X1TS U1588 ( .A0(n1787), .A1(intDX_EWSW[25]), .B0(n1786), .B1(
intDX_EWSW[26]), .Y(n1208) );
AOI221XLTS U1589 ( .A0(n1787), .A1(intDX_EWSW[25]), .B0(intDX_EWSW[26]),
.B1(n1786), .C0(n1208), .Y(n1214) );
OAI22X1TS U1590 ( .A0(n1796), .A1(intDX_EWSW[27]), .B0(n1808), .B1(
intDY_EWSW[28]), .Y(n1209) );
AOI221XLTS U1591 ( .A0(n1796), .A1(intDX_EWSW[27]), .B0(intDY_EWSW[28]),
.B1(n1808), .C0(n1209), .Y(n1213) );
OAI22X1TS U1592 ( .A0(n1804), .A1(intDY_EWSW[29]), .B0(n1741), .B1(
intDY_EWSW[30]), .Y(n1210) );
AOI221XLTS U1593 ( .A0(n1804), .A1(intDY_EWSW[29]), .B0(intDY_EWSW[30]),
.B1(n1741), .C0(n1210), .Y(n1212) );
AOI2BB2XLTS U1594 ( .B0(intDX_EWSW[7]), .B1(n1803), .A0N(n1803), .A1N(
intDX_EWSW[7]), .Y(n1211) );
NAND4XLTS U1595 ( .A(n1214), .B(n1213), .C(n1212), .D(n1211), .Y(n1242) );
OAI22X1TS U1596 ( .A0(n1802), .A1(intDX_EWSW[1]), .B0(n1797), .B1(
intDX_EWSW[17]), .Y(n1215) );
AOI221XLTS U1597 ( .A0(n1802), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[17]), .B1(
n1797), .C0(n1215), .Y(n1222) );
AOI221XLTS U1598 ( .A0(n1811), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1761), .C0(n1216), .Y(n1221) );
OAI22X1TS U1599 ( .A0(n1795), .A1(intDX_EWSW[20]), .B0(n1791), .B1(
intDX_EWSW[21]), .Y(n1217) );
AOI221XLTS U1600 ( .A0(n1795), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1791), .C0(n1217), .Y(n1220) );
OAI22X1TS U1601 ( .A0(n1760), .A1(intDX_EWSW[22]), .B0(n1815), .B1(
intDX_EWSW[23]), .Y(n1218) );
AOI221XLTS U1602 ( .A0(n1760), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1815), .C0(n1218), .Y(n1219) );
NAND4XLTS U1603 ( .A(n1222), .B(n1221), .C(n1220), .D(n1219), .Y(n1241) );
OAI22X1TS U1604 ( .A0(n1740), .A1(intDX_EWSW[24]), .B0(n1793), .B1(
intDX_EWSW[9]), .Y(n1223) );
AOI221XLTS U1605 ( .A0(n1740), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1793), .C0(n1223), .Y(n1230) );
AOI221XLTS U1606 ( .A0(n1778), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]),
.B1(n1783), .C0(n1224), .Y(n1229) );
OAI22X1TS U1607 ( .A0(n1794), .A1(intDX_EWSW[12]), .B0(n1790), .B1(
intDX_EWSW[13]), .Y(n1225) );
AOI221XLTS U1608 ( .A0(n1794), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1790), .C0(n1225), .Y(n1228) );
OAI22X1TS U1609 ( .A0(n1759), .A1(intDX_EWSW[14]), .B0(n1800), .B1(
intDX_EWSW[15]), .Y(n1226) );
AOI221XLTS U1610 ( .A0(n1759), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1800), .C0(n1226), .Y(n1227) );
NAND4XLTS U1611 ( .A(n1230), .B(n1229), .C(n1228), .D(n1227), .Y(n1240) );
OAI22X1TS U1612 ( .A0(n1757), .A1(intDX_EWSW[16]), .B0(n1798), .B1(
intDX_EWSW[0]), .Y(n1231) );
AOI221XLTS U1613 ( .A0(n1757), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1798), .C0(n1231), .Y(n1238) );
OAI22X1TS U1614 ( .A0(n1792), .A1(intDX_EWSW[2]), .B0(n1799), .B1(
intDX_EWSW[3]), .Y(n1232) );
AOI221XLTS U1615 ( .A0(n1792), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1799), .C0(n1232), .Y(n1237) );
OAI22X1TS U1616 ( .A0(n1789), .A1(intDX_EWSW[4]), .B0(n1758), .B1(
intDX_EWSW[5]), .Y(n1233) );
AOI221XLTS U1617 ( .A0(n1789), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1758), .C0(n1233), .Y(n1236) );
OAI22X1TS U1618 ( .A0(n1801), .A1(intDX_EWSW[8]), .B0(n1788), .B1(
intDX_EWSW[6]), .Y(n1234) );
AOI221XLTS U1619 ( .A0(n1801), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1788), .C0(n1234), .Y(n1235) );
NAND4XLTS U1620 ( .A(n1238), .B(n1237), .C(n1236), .D(n1235), .Y(n1239) );
NOR4XLTS U1621 ( .A(n1242), .B(n1241), .C(n1240), .D(n1239), .Y(n1678) );
INVX2TS U1622 ( .A(n1675), .Y(n1247) );
AOI22X1TS U1623 ( .A0(intDX_EWSW[31]), .A1(n1245), .B0(SIGN_FLAG_EXP), .B1(
n1244), .Y(n1246) );
OAI31X1TS U1624 ( .A0(n1678), .A1(n1247), .A2(n1696), .B0(n1246), .Y(n800)
);
NOR3XLTS U1625 ( .A(Raw_mant_NRM_SWR[15]), .B(Raw_mant_NRM_SWR[16]), .C(
Raw_mant_NRM_SWR[17]), .Y(n1252) );
INVX2TS U1626 ( .A(n1248), .Y(n1249) );
OAI211XLTS U1627 ( .A0(n1252), .A1(n1251), .B0(n1250), .C0(n1249), .Y(n1257)
);
INVX2TS U1628 ( .A(n1253), .Y(n1255) );
AOI211XLTS U1629 ( .A0(n1258), .A1(Raw_mant_NRM_SWR[12]), .B0(n1257), .C0(
n1256), .Y(n1378) );
AOI32X1TS U1630 ( .A0(Shift_amount_SHT1_EWR[3]), .A1(n1654), .A2(n1636),
.B0(shift_value_SHT2_EWR[3]), .B1(n1356), .Y(n1259) );
AOI22X1TS U1631 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n1262), .B0(n1261), .B1(
n1260), .Y(n1264) );
AOI32X1TS U1632 ( .A0(n1749), .A1(n1264), .A2(n1820), .B0(n1263), .B1(n1264),
.Y(n1265) );
AOI211XLTS U1633 ( .A0(n1267), .A1(Raw_mant_NRM_SWR[4]), .B0(n1266), .C0(
n1265), .Y(n1381) );
AOI32X1TS U1634 ( .A0(Shift_amount_SHT1_EWR[4]), .A1(n1654), .A2(n1636),
.B0(shift_value_SHT2_EWR[4]), .B1(n1356), .Y(n1268) );
CLKBUFX2TS U1635 ( .A(n1725), .Y(n1736) );
NOR2BX1TS U1636 ( .AN(n1270), .B(exp_rslt_NRM2_EW1[5]), .Y(n1271) );
NOR2BX1TS U1637 ( .AN(n1271), .B(exp_rslt_NRM2_EW1[6]), .Y(n1272) );
NOR2BX1TS U1638 ( .AN(n1272), .B(exp_rslt_NRM2_EW1[7]), .Y(n1273) );
NOR2BX1TS U1639 ( .AN(Shift_reg_FLAGS_7[0]), .B(n1709), .Y(n1697) );
INVX2TS U1640 ( .A(n1697), .Y(n1288) );
NAND2X1TS U1641 ( .A(n1628), .B(final_result_ieee[23]), .Y(n1275) );
INVX2TS U1642 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n1278) );
NAND2X1TS U1643 ( .A(n1628), .B(final_result_ieee[26]), .Y(n1277) );
NAND2X1TS U1644 ( .A(n1628), .B(final_result_ieee[24]), .Y(n1279) );
INVX2TS U1645 ( .A(exp_rslt_NRM2_EW1[5]), .Y(n1282) );
NAND2X1TS U1646 ( .A(n1628), .B(final_result_ieee[28]), .Y(n1281) );
NAND2X1TS U1647 ( .A(n1628), .B(final_result_ieee[29]), .Y(n1283) );
NAND2X1TS U1648 ( .A(n1628), .B(final_result_ieee[25]), .Y(n1285) );
NAND2X1TS U1649 ( .A(n1628), .B(final_result_ieee[27]), .Y(n1287) );
NAND2X1TS U1650 ( .A(n1323), .B(Raw_mant_NRM_SWR[1]), .Y(n1292) );
NAND2X1TS U1651 ( .A(n966), .B(Raw_mant_NRM_SWR[24]), .Y(n1291) );
NAND2X1TS U1652 ( .A(n1379), .B(DmP_mant_SHT1_SW[22]), .Y(n1290) );
INVX2TS U1653 ( .A(n1344), .Y(n1366) );
AOI21X1TS U1654 ( .A0(n1310), .A1(Raw_mant_NRM_SWR[25]), .B0(n1777), .Y(
n1293) );
AOI22X1TS U1655 ( .A0(n1356), .A1(Data_array_SWR[24]), .B0(n974), .B1(n1363),
.Y(n1295) );
NAND2X1TS U1656 ( .A(n1323), .B(Raw_mant_NRM_SWR[23]), .Y(n1298) );
NAND2X1TS U1657 ( .A(n1085), .B(Raw_mant_NRM_SWR[2]), .Y(n1297) );
NAND2X1TS U1658 ( .A(n1379), .B(DmP_mant_SHT1_SW[0]), .Y(n1296) );
AOI22X1TS U1659 ( .A0(n1356), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1323), .Y(n1304) );
NAND2X1TS U1660 ( .A(n1323), .B(Raw_mant_NRM_SWR[22]), .Y(n1301) );
NAND2X1TS U1661 ( .A(n1085), .B(Raw_mant_NRM_SWR[3]), .Y(n1300) );
NAND2X1TS U1662 ( .A(n1379), .B(DmP_mant_SHT1_SW[1]), .Y(n1299) );
OAI2BB2XLTS U1663 ( .B0(n1749), .B1(n1373), .A0N(Raw_mant_NRM_SWR[24]),
.A1N(n1302), .Y(n1320) );
AOI21X1TS U1664 ( .A0(n969), .A1(n1339), .B0(n1320), .Y(n1303) );
NAND2X1TS U1665 ( .A(n1323), .B(Raw_mant_NRM_SWR[2]), .Y(n1308) );
NAND2X1TS U1666 ( .A(n966), .B(Raw_mant_NRM_SWR[23]), .Y(n1307) );
NAND2X1TS U1667 ( .A(n1379), .B(DmP_mant_SHT1_SW[21]), .Y(n1306) );
INVX2TS U1668 ( .A(n1343), .Y(n1368) );
AOI22X1TS U1669 ( .A0(n1085), .A1(Raw_mant_NRM_SWR[22]), .B0(n1777), .B1(
DmP_mant_SHT1_SW[20]), .Y(n1309) );
AOI22X1TS U1670 ( .A0(n1370), .A1(Data_array_SWR[22]), .B0(n959), .B1(n1349),
.Y(n1312) );
AOI22X1TS U1671 ( .A0(n977), .A1(n1344), .B0(n969), .B1(n1363), .Y(n1311) );
INVX2TS U1672 ( .A(n1313), .Y(n1353) );
AOI22X1TS U1673 ( .A0(n1370), .A1(Data_array_SWR[18]), .B0(n977), .B1(n1350),
.Y(n1318) );
AOI22X1TS U1674 ( .A0(n1323), .A1(Raw_mant_NRM_SWR[4]), .B0(n1777), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1315) );
NAND2X1TS U1675 ( .A(n1085), .B(Raw_mant_NRM_SWR[21]), .Y(n1314) );
NAND2X1TS U1676 ( .A(n1315), .B(n1314), .Y(n1348) );
AOI22X1TS U1677 ( .A0(n1331), .A1(n1316), .B0(n968), .B1(n1348), .Y(n1317)
);
AOI22X1TS U1678 ( .A0(n1356), .A1(Data_array_SWR[1]), .B0(n978), .B1(n1339),
.Y(n1322) );
AOI22X1TS U1679 ( .A0(n1323), .A1(Raw_mant_NRM_SWR[21]), .B0(n1777), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1319) );
AOI22X1TS U1680 ( .A0(n1331), .A1(n1320), .B0(n969), .B1(n1337), .Y(n1321)
);
NAND2X1TS U1681 ( .A(n1323), .B(Raw_mant_NRM_SWR[20]), .Y(n1326) );
NAND2X1TS U1682 ( .A(n1085), .B(Raw_mant_NRM_SWR[5]), .Y(n1325) );
NAND2X1TS U1683 ( .A(n1379), .B(DmP_mant_SHT1_SW[3]), .Y(n1324) );
INVX2TS U1684 ( .A(n1338), .Y(n1362) );
AOI22X1TS U1685 ( .A0(n1327), .A1(Data_array_SWR[4]), .B0(n977), .B1(n1358),
.Y(n1330) );
INVX2TS U1686 ( .A(n1328), .Y(n1354) );
AOI22X1TS U1687 ( .A0(n1331), .A1(n1337), .B0(n968), .B1(n1354), .Y(n1329)
);
INVX2TS U1688 ( .A(n1348), .Y(n1347) );
AOI22X1TS U1689 ( .A0(n1370), .A1(Data_array_SWR[20]), .B0(n978), .B1(n1349),
.Y(n1333) );
AOI22X1TS U1690 ( .A0(n1331), .A1(n1350), .B0(n968), .B1(n1343), .Y(n1332)
);
INVX2TS U1691 ( .A(n1339), .Y(n1336) );
AOI22X1TS U1692 ( .A0(n1356), .A1(Data_array_SWR[3]), .B0(n977), .B1(n1338),
.Y(n1335) );
AOI22X1TS U1693 ( .A0(n974), .A1(n1337), .B0(n967), .B1(n1358), .Y(n1334) );
AOI22X1TS U1694 ( .A0(n1356), .A1(Data_array_SWR[2]), .B0(n978), .B1(n1337),
.Y(n1341) );
AOI22X1TS U1695 ( .A0(n974), .A1(n1339), .B0(n967), .B1(n1338), .Y(n1340) );
AOI22X1TS U1696 ( .A0(n1370), .A1(Data_array_SWR[21]), .B0(n978), .B1(n1343),
.Y(n1346) );
AOI22X1TS U1697 ( .A0(n974), .A1(n1349), .B0(n968), .B1(n1344), .Y(n1345) );
AOI22X1TS U1698 ( .A0(n1370), .A1(Data_array_SWR[19]), .B0(n977), .B1(n1348),
.Y(n1352) );
AOI22X1TS U1699 ( .A0(n974), .A1(n1350), .B0(n969), .B1(n1349), .Y(n1351) );
AOI22X1TS U1700 ( .A0(n1356), .A1(Data_array_SWR[5]), .B0(n978), .B1(n1354),
.Y(n1361) );
AOI22X1TS U1701 ( .A0(n974), .A1(n1358), .B0(n967), .B1(n1357), .Y(n1360) );
AOI21X1TS U1702 ( .A0(n1364), .A1(n1363), .B0(n1085), .Y(n1656) );
OAI22X1TS U1703 ( .A0(n1368), .A1(n1367), .B0(n1366), .B1(n960), .Y(n1369)
);
AOI21X1TS U1704 ( .A0(n1370), .A1(Data_array_SWR[23]), .B0(n1369), .Y(n1371)
);
OAI21XLTS U1705 ( .A0(n979), .A1(n1746), .B0(n1373), .Y(n627) );
AOI22X1TS U1706 ( .A0(intDX_EWSW[17]), .A1(n1374), .B0(DmP_EXP_EWSW[17]),
.B1(n1633), .Y(n1375) );
OAI21XLTS U1707 ( .A0(n1797), .A1(n1376), .B0(n1375), .Y(n656) );
NAND2X1TS U1708 ( .A(n1379), .B(LZD_output_NRM2_EW[3]), .Y(n1377) );
OAI21XLTS U1709 ( .A0(n1378), .A1(n1777), .B0(n1377), .Y(n594) );
NAND2X1TS U1710 ( .A(n1379), .B(LZD_output_NRM2_EW[4]), .Y(n1380) );
OAI21XLTS U1711 ( .A0(n1381), .A1(n1777), .B0(n1380), .Y(n590) );
AO22XLTS U1712 ( .A0(n1743), .A1(DMP_SHT1_EWSW[5]), .B0(DMP_SHT2_EWSW[5]),
.B1(n1686), .Y(n1851) );
AO22XLTS U1713 ( .A0(n1743), .A1(DMP_SHT1_EWSW[4]), .B0(DMP_SHT2_EWSW[4]),
.B1(n1680), .Y(n1852) );
AO22XLTS U1714 ( .A0(n1743), .A1(DMP_SHT1_EWSW[3]), .B0(DMP_SHT2_EWSW[3]),
.B1(n1680), .Y(n1853) );
AO22XLTS U1715 ( .A0(n1743), .A1(DMP_SHT1_EWSW[2]), .B0(DMP_SHT2_EWSW[2]),
.B1(n1680), .Y(n1854) );
AO22XLTS U1716 ( .A0(n1743), .A1(DMP_SHT1_EWSW[1]), .B0(DMP_SHT2_EWSW[1]),
.B1(n1680), .Y(n1855) );
AO22XLTS U1717 ( .A0(n1743), .A1(DMP_SHT1_EWSW[0]), .B0(DMP_SHT2_EWSW[0]),
.B1(n1680), .Y(n1856) );
NOR2BX1TS U1718 ( .AN(LZD_output_NRM2_EW[4]), .B(ADD_OVRFLW_NRM2), .Y(n1382)
);
NOR2BX1TS U1719 ( .AN(LZD_output_NRM2_EW[3]), .B(ADD_OVRFLW_NRM2), .Y(n1383)
);
NOR2BX1TS U1720 ( .AN(LZD_output_NRM2_EW[2]), .B(ADD_OVRFLW_NRM2), .Y(n1384)
);
NOR2BX1TS U1721 ( .AN(LZD_output_NRM2_EW[1]), .B(ADD_OVRFLW_NRM2), .Y(n1385)
);
CLKBUFX2TS U1722 ( .A(n1684), .Y(n1620) );
NOR2XLTS U1723 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1387) );
AOI32X1TS U1724 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1387), .B1(n1810), .Y(n1637)
);
NOR2XLTS U1725 ( .A(n1765), .B(Shift_reg_FLAGS_7[0]), .Y(n1690) );
CLKBUFX2TS U1726 ( .A(n1690), .Y(n1688) );
MX2X1TS U1727 ( .A(DMP_SFG[22]), .B(DMP_SHT2_EWSW[22]), .S0(n1688), .Y(n731)
);
CLKBUFX2TS U1728 ( .A(n1690), .Y(n1457) );
MX2X1TS U1729 ( .A(DMP_SFG[21]), .B(DMP_SHT2_EWSW[21]), .S0(n1457), .Y(n734)
);
MX2X1TS U1730 ( .A(DMP_SFG[20]), .B(DMP_SHT2_EWSW[20]), .S0(n1457), .Y(n737)
);
MX2X1TS U1731 ( .A(DMP_SFG[19]), .B(DMP_SHT2_EWSW[19]), .S0(n1457), .Y(n740)
);
MX2X1TS U1732 ( .A(DMP_SFG[18]), .B(DMP_SHT2_EWSW[18]), .S0(n1457), .Y(n743)
);
MX2X1TS U1733 ( .A(DMP_SFG[17]), .B(DMP_SHT2_EWSW[17]), .S0(n1457), .Y(n746)
);
MX2X1TS U1734 ( .A(DMP_SFG[16]), .B(DMP_SHT2_EWSW[16]), .S0(n1457), .Y(n749)
);
MX2X1TS U1735 ( .A(DMP_SFG[15]), .B(DMP_SHT2_EWSW[15]), .S0(n1457), .Y(n752)
);
MX2X1TS U1736 ( .A(DMP_SFG[14]), .B(DMP_SHT2_EWSW[14]), .S0(n1457), .Y(n755)
);
MX2X1TS U1737 ( .A(DMP_SFG[13]), .B(DMP_SHT2_EWSW[13]), .S0(n1457), .Y(n758)
);
CLKBUFX2TS U1738 ( .A(n1690), .Y(n1388) );
MX2X1TS U1739 ( .A(DMP_SFG[12]), .B(DMP_SHT2_EWSW[12]), .S0(n1388), .Y(n761)
);
MX2X1TS U1740 ( .A(DMP_SFG[11]), .B(DMP_SHT2_EWSW[11]), .S0(n1388), .Y(n764)
);
MX2X1TS U1741 ( .A(DMP_SFG[10]), .B(DMP_SHT2_EWSW[10]), .S0(n1388), .Y(n767)
);
MX2X1TS U1742 ( .A(DMP_SFG[9]), .B(DMP_SHT2_EWSW[9]), .S0(n1388), .Y(n770)
);
MX2X1TS U1743 ( .A(DMP_SFG[8]), .B(DMP_SHT2_EWSW[8]), .S0(n1388), .Y(n773)
);
MX2X1TS U1744 ( .A(DMP_SFG[7]), .B(DMP_SHT2_EWSW[7]), .S0(n1388), .Y(n776)
);
MX2X1TS U1745 ( .A(DMP_SFG[6]), .B(DMP_SHT2_EWSW[6]), .S0(n1388), .Y(n779)
);
MX2X1TS U1746 ( .A(DMP_SFG[5]), .B(DMP_SHT2_EWSW[5]), .S0(n1388), .Y(n782)
);
MX2X1TS U1747 ( .A(DMP_SFG[4]), .B(DMP_SHT2_EWSW[4]), .S0(n1388), .Y(n785)
);
MX2X1TS U1748 ( .A(DMP_SFG[3]), .B(DMP_SHT2_EWSW[3]), .S0(n1388), .Y(n788)
);
CLKBUFX2TS U1749 ( .A(n1690), .Y(n1706) );
MX2X1TS U1750 ( .A(DMP_SFG[2]), .B(DMP_SHT2_EWSW[2]), .S0(n1706), .Y(n791)
);
MX2X1TS U1751 ( .A(DMP_SFG[1]), .B(DMP_SHT2_EWSW[1]), .S0(n1706), .Y(n794)
);
MX2X1TS U1752 ( .A(DMP_SFG[0]), .B(DMP_SHT2_EWSW[0]), .S0(n1706), .Y(n797)
);
INVX2TS U1753 ( .A(n1688), .Y(n1705) );
NOR2XLTS U1754 ( .A(shift_value_SHT2_EWR[2]), .B(n1776), .Y(n1395) );
NAND2X1TS U1755 ( .A(shift_value_SHT2_EWR[3]), .B(bit_shift_SHT2), .Y(n1412)
);
NOR2XLTS U1756 ( .A(n1748), .B(n1412), .Y(n1436) );
NAND2X1TS U1757 ( .A(shift_value_SHT2_EWR[2]), .B(n1776), .Y(n1413) );
INVX2TS U1758 ( .A(n1413), .Y(n1409) );
NAND2X1TS U1759 ( .A(n1748), .B(n1776), .Y(n1406) );
INVX2TS U1760 ( .A(n1406), .Y(n1415) );
AOI22X1TS U1761 ( .A0(Data_array_SWR[8]), .A1(n980), .B0(Data_array_SWR[0]),
.B1(n970), .Y(n1391) );
INVX2TS U1762 ( .A(n1449), .Y(n1443) );
AOI22X1TS U1763 ( .A0(Data_array_SWR[12]), .A1(n1443), .B0(Data_array_SWR[4]), .B1(n962), .Y(n1390) );
AOI22X1TS U1764 ( .A0(n1415), .A1(Data_array_SWR[25]), .B0(bit_shift_SHT2),
.B1(n1406), .Y(n1491) );
NAND2X1TS U1765 ( .A(n961), .B(n965), .Y(n1432) );
NOR2XLTS U1766 ( .A(n961), .B(n1812), .Y(n1458) );
NAND2X1TS U1767 ( .A(n1458), .B(n965), .Y(n1431) );
AOI21X1TS U1768 ( .A0(n1392), .A1(n1431), .B0(n1705), .Y(n1393) );
AO21XLTS U1769 ( .A0(DmP_mant_SFG_SWR[25]), .A1(n1705), .B0(n1393), .Y(n541)
);
AO22XLTS U1770 ( .A0(Data_array_SWR[21]), .A1(n1409), .B0(Data_array_SWR[17]), .B1(n1415), .Y(n1394) );
AOI22X1TS U1771 ( .A0(Data_array_SWR[9]), .A1(n1446), .B0(Data_array_SWR[1]),
.B1(n971), .Y(n1397) );
AOI22X1TS U1772 ( .A0(Data_array_SWR[13]), .A1(n1443), .B0(Data_array_SWR[5]), .B1(n963), .Y(n1396) );
AOI22X1TS U1773 ( .A0(n1415), .A1(Data_array_SWR[24]), .B0(bit_shift_SHT2),
.B1(n1406), .Y(n1485) );
AOI21X1TS U1774 ( .A0(left_right_SHT2), .A1(n1487), .B0(n1398), .Y(n1738) );
AOI21X1TS U1775 ( .A0(Data_array_SWR[18]), .A1(n1415), .B0(n1399), .Y(n1465)
);
AOI22X1TS U1776 ( .A0(Data_array_SWR[10]), .A1(n1446), .B0(Data_array_SWR[2]), .B1(n970), .Y(n1401) );
AOI22X1TS U1777 ( .A0(Data_array_SWR[14]), .A1(n1443), .B0(Data_array_SWR[6]), .B1(n962), .Y(n1400) );
AOI22X1TS U1778 ( .A0(n1415), .A1(Data_array_SWR[23]), .B0(bit_shift_SHT2),
.B1(n1406), .Y(n1482) );
AOI21X1TS U1779 ( .A0(left_right_SHT2), .A1(n1484), .B0(n1402), .Y(n1735) );
AOI21X1TS U1780 ( .A0(Data_array_SWR[19]), .A1(n1415), .B0(n1403), .Y(n1468)
);
AOI22X1TS U1781 ( .A0(Data_array_SWR[11]), .A1(n980), .B0(Data_array_SWR[3]),
.B1(n971), .Y(n1405) );
AOI22X1TS U1782 ( .A0(Data_array_SWR[15]), .A1(n1443), .B0(Data_array_SWR[7]), .B1(n963), .Y(n1404) );
AOI22X1TS U1783 ( .A0(n1415), .A1(Data_array_SWR[22]), .B0(bit_shift_SHT2),
.B1(n1406), .Y(n1479) );
AOI21X1TS U1784 ( .A0(left_right_SHT2), .A1(n1481), .B0(n1407), .Y(n1733) );
OAI2BB1X1TS U1785 ( .A0N(n1415), .A1N(Data_array_SWR[20]), .B0(n1412), .Y(
n1408) );
AOI21X1TS U1786 ( .A0(Data_array_SWR[24]), .A1(n1409), .B0(n1408), .Y(n1473)
);
AOI22X1TS U1787 ( .A0(Data_array_SWR[12]), .A1(n981), .B0(Data_array_SWR[4]),
.B1(n971), .Y(n1411) );
AOI22X1TS U1788 ( .A0(Data_array_SWR[16]), .A1(n1443), .B0(Data_array_SWR[8]), .B1(n963), .Y(n1410) );
AOI21X1TS U1789 ( .A0(Data_array_SWR[21]), .A1(n1415), .B0(n1414), .Y(n1476)
);
AOI21X1TS U1790 ( .A0(left_right_SHT2), .A1(n1478), .B0(n1416), .Y(n1732) );
AOI22X1TS U1791 ( .A0(Data_array_SWR[13]), .A1(n1446), .B0(Data_array_SWR[5]), .B1(n970), .Y(n1418) );
AOI22X1TS U1792 ( .A0(Data_array_SWR[17]), .A1(n1443), .B0(Data_array_SWR[9]), .B1(n962), .Y(n1417) );
AOI21X1TS U1793 ( .A0(n964), .A1(n1471), .B0(n1419), .Y(n1731) );
INVX2TS U1794 ( .A(n1688), .Y(n1454) );
AOI22X1TS U1795 ( .A0(Data_array_SWR[18]), .A1(n1443), .B0(
Data_array_SWR[10]), .B1(n963), .Y(n1421) );
AOI22X1TS U1796 ( .A0(Data_array_SWR[14]), .A1(n1446), .B0(Data_array_SWR[6]), .B1(n971), .Y(n1420) );
AOI21X1TS U1797 ( .A0(n964), .A1(n1470), .B0(n1422), .Y(n1730) );
AOI22X1TS U1798 ( .A0(Data_array_SWR[19]), .A1(n1443), .B0(
Data_array_SWR[11]), .B1(n963), .Y(n1424) );
AOI22X1TS U1799 ( .A0(Data_array_SWR[15]), .A1(n980), .B0(Data_array_SWR[7]),
.B1(n971), .Y(n1423) );
AOI21X1TS U1800 ( .A0(n964), .A1(n1467), .B0(n1425), .Y(n1729) );
AOI22X1TS U1801 ( .A0(Data_array_SWR[20]), .A1(n1443), .B0(
Data_array_SWR[12]), .B1(n963), .Y(n1427) );
AOI22X1TS U1802 ( .A0(Data_array_SWR[16]), .A1(n981), .B0(Data_array_SWR[8]),
.B1(n971), .Y(n1426) );
AOI21X1TS U1803 ( .A0(n964), .A1(n1464), .B0(n1428), .Y(n1728) );
AOI22X1TS U1804 ( .A0(Data_array_SWR[21]), .A1(n1443), .B0(
Data_array_SWR[13]), .B1(n962), .Y(n1430) );
AOI22X1TS U1805 ( .A0(Data_array_SWR[17]), .A1(n981), .B0(Data_array_SWR[9]),
.B1(n970), .Y(n1429) );
AOI21X1TS U1806 ( .A0(left_right_SHT2), .A1(n1461), .B0(n1433), .Y(n1727) );
AOI21X1TS U1807 ( .A0(Data_array_SWR[14]), .A1(n963), .B0(n1458), .Y(n1435)
);
AOI22X1TS U1808 ( .A0(Data_array_SWR[18]), .A1(n980), .B0(Data_array_SWR[10]), .B1(n971), .Y(n1434) );
INVX2TS U1809 ( .A(n1446), .Y(n1442) );
AOI22X1TS U1810 ( .A0(Data_array_SWR[19]), .A1(n963), .B0(Data_array_SWR[15]), .B1(n971), .Y(n1437) );
AOI22X1TS U1811 ( .A0(n964), .A1(n1455), .B0(n1456), .B1(n965), .Y(n1716) );
AOI21X1TS U1812 ( .A0(Data_array_SWR[15]), .A1(n963), .B0(n1458), .Y(n1439)
);
AOI22X1TS U1813 ( .A0(Data_array_SWR[19]), .A1(n981), .B0(Data_array_SWR[11]), .B1(n971), .Y(n1438) );
AOI22X1TS U1814 ( .A0(Data_array_SWR[18]), .A1(n963), .B0(Data_array_SWR[14]), .B1(n971), .Y(n1440) );
AOI22X1TS U1815 ( .A0(n964), .A1(n1452), .B0(n1453), .B1(n965), .Y(n1714) );
AOI22X1TS U1816 ( .A0(Data_array_SWR[20]), .A1(n981), .B0(Data_array_SWR[12]), .B1(n970), .Y(n1445) );
AOI22X1TS U1817 ( .A0(Data_array_SWR[16]), .A1(n962), .B0(Data_array_SWR[24]), .B1(n972), .Y(n1444) );
NAND2X1TS U1818 ( .A(n1445), .B(n1444), .Y(n1450) );
AOI22X1TS U1819 ( .A0(Data_array_SWR[21]), .A1(n980), .B0(Data_array_SWR[13]), .B1(n970), .Y(n1448) );
NAND2X1TS U1820 ( .A(Data_array_SWR[17]), .B(n962), .Y(n1447) );
OAI211XLTS U1821 ( .A0(n1449), .A1(n1809), .B0(n1448), .C0(n1447), .Y(n1451)
);
AOI221XLTS U1822 ( .A0(left_right_SHT2), .A1(n1450), .B0(n965), .B1(n1451),
.C0(n1458), .Y(n1712) );
AOI221XLTS U1823 ( .A0(left_right_SHT2), .A1(n1451), .B0(n965), .B1(n1450),
.C0(n1458), .Y(n1711) );
AOI22X1TS U1824 ( .A0(n964), .A1(n1453), .B0(n1452), .B1(n965), .Y(n1713) );
AOI22X1TS U1825 ( .A0(n964), .A1(n1456), .B0(n1455), .B1(n965), .Y(n1715) );
INVX2TS U1826 ( .A(n1457), .Y(n1494) );
NAND2X1TS U1827 ( .A(left_right_SHT2), .B(n1753), .Y(n1490) );
AOI21X1TS U1828 ( .A0(n1771), .A1(n1461), .B0(n1460), .Y(n1717) );
AOI21X1TS U1829 ( .A0(n1771), .A1(n1464), .B0(n1463), .Y(n1718) );
AOI21X1TS U1830 ( .A0(n1467), .A1(n1771), .B0(n1466), .Y(n1719) );
AOI21X1TS U1831 ( .A0(n1470), .A1(n1771), .B0(n1469), .Y(n1720) );
INVX2TS U1832 ( .A(n1490), .Y(n1472) );
AOI21X1TS U1833 ( .A0(n1478), .A1(n1771), .B0(n1477), .Y(n1723) );
AOI21X1TS U1834 ( .A0(n1481), .A1(n1771), .B0(n1480), .Y(n1724) );
AOI21X1TS U1835 ( .A0(n1484), .A1(n965), .B0(n1483), .Y(n1726) );
AOI21X1TS U1836 ( .A0(n1487), .A1(n1771), .B0(n1486), .Y(n1488) );
AOI21X1TS U1837 ( .A0(n1493), .A1(n1771), .B0(n1492), .Y(n1495) );
MX2X1TS U1838 ( .A(OP_FLAG_SFG), .B(OP_FLAG_SHT2), .S0(n1706), .Y(n629) );
NAND2X1TS U1839 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n1606) );
NOR2XLTS U1840 ( .A(n1620), .B(OP_FLAG_SFG), .Y(n1570) );
CLKBUFX2TS U1841 ( .A(n1684), .Y(n1634) );
CMPR32X2TS U1842 ( .A(DMP_SFG[22]), .B(DmP_mant_SFG_SWR[24]), .C(n1497),
.CO(n1501), .S(n1500) );
NOR2BX1TS U1843 ( .AN(OP_FLAG_SFG), .B(n1634), .Y(n1552) );
CLKBUFX2TS U1844 ( .A(n1552), .Y(n1617) );
AOI22X1TS U1845 ( .A0(n1498), .A1(n1617), .B0(Raw_mant_NRM_SWR[24]), .B1(
n1634), .Y(n1499) );
OAI2BB1X1TS U1846 ( .A0N(n1570), .A1N(n1500), .B0(n1499), .Y(n596) );
XNOR2X1TS U1847 ( .A(n1501), .B(DmP_mant_SFG_SWR[25]), .Y(n1506) );
CMPR32X2TS U1848 ( .A(n1828), .B(DMP_SFG[22]), .C(n1502), .CO(n1503), .S(
n1498) );
XNOR2X1TS U1849 ( .A(n1503), .B(n1841), .Y(n1504) );
AOI22X1TS U1850 ( .A0(n1504), .A1(n1617), .B0(Raw_mant_NRM_SWR[25]), .B1(
n1634), .Y(n1505) );
OAI2BB1X1TS U1851 ( .A0N(n1570), .A1N(n1506), .B0(n1505), .Y(n595) );
CMPR32X2TS U1852 ( .A(DMP_SFG[21]), .B(DmP_mant_SFG_SWR[23]), .C(n1507),
.CO(n1497), .S(n1511) );
CMPR32X2TS U1853 ( .A(n1829), .B(DMP_SFG[21]), .C(n1508), .CO(n1502), .S(
n1509) );
AOI22X1TS U1854 ( .A0(n1509), .A1(n1617), .B0(Raw_mant_NRM_SWR[23]), .B1(
n1634), .Y(n1510) );
OAI2BB1X1TS U1855 ( .A0N(n1570), .A1N(n1511), .B0(n1510), .Y(n597) );
CMPR32X2TS U1856 ( .A(DMP_SFG[20]), .B(DmP_mant_SFG_SWR[22]), .C(n1512),
.CO(n1507), .S(n1516) );
CMPR32X2TS U1857 ( .A(n1830), .B(DMP_SFG[20]), .C(n1513), .CO(n1508), .S(
n1514) );
AOI22X1TS U1858 ( .A0(n1514), .A1(n1617), .B0(Raw_mant_NRM_SWR[22]), .B1(
n1634), .Y(n1515) );
OAI2BB1X1TS U1859 ( .A0N(n1570), .A1N(n1516), .B0(n1515), .Y(n598) );
AFHCONX2TS U1860 ( .A(DMP_SFG[17]), .B(n1842), .CI(n1517), .CON(n1522), .S(
n1521) );
AFHCINX2TS U1861 ( .CIN(n1518), .B(DMP_SFG[17]), .A(DmP_mant_SFG_SWR[19]),
.S(n1519), .CO(n1523) );
CLKBUFX2TS U1862 ( .A(n1570), .Y(n1621) );
AOI22X1TS U1863 ( .A0(n1519), .A1(n1621), .B0(Raw_mant_NRM_SWR[19]), .B1(
n1634), .Y(n1520) );
OAI2BB1X1TS U1864 ( .A0N(n1617), .A1N(n1521), .B0(n1520), .Y(n601) );
AFHCINX2TS U1865 ( .CIN(n1522), .B(n1832), .A(DMP_SFG[18]), .S(n1526), .CO(
n1528) );
CMPR32X2TS U1866 ( .A(DMP_SFG[18]), .B(DmP_mant_SFG_SWR[20]), .C(n1523),
.CO(n1527), .S(n1524) );
AOI22X1TS U1867 ( .A0(n1524), .A1(n1621), .B0(Raw_mant_NRM_SWR[20]), .B1(
n1634), .Y(n1525) );
OAI2BB1X1TS U1868 ( .A0N(n1552), .A1N(n1526), .B0(n1525), .Y(n600) );
CMPR32X2TS U1869 ( .A(DMP_SFG[19]), .B(DmP_mant_SFG_SWR[21]), .C(n1527),
.CO(n1512), .S(n1531) );
CMPR32X2TS U1870 ( .A(n1831), .B(DMP_SFG[19]), .C(n1528), .CO(n1513), .S(
n1529) );
AOI22X1TS U1871 ( .A0(n1529), .A1(n1617), .B0(Raw_mant_NRM_SWR[21]), .B1(
n1807), .Y(n1530) );
OAI2BB1X1TS U1872 ( .A0N(n1570), .A1N(n1531), .B0(n1530), .Y(n599) );
AFHCINX2TS U1873 ( .CIN(n1532), .B(n1833), .A(DMP_SFG[16]), .S(n1536), .CO(
n1517) );
AFHCONX2TS U1874 ( .A(DmP_mant_SFG_SWR[18]), .B(DMP_SFG[16]), .CI(n1533),
.CON(n1518), .S(n1534) );
AOI22X1TS U1875 ( .A0(n1534), .A1(n1621), .B0(Raw_mant_NRM_SWR[18]), .B1(
n1634), .Y(n1535) );
OAI2BB1X1TS U1876 ( .A0N(n1552), .A1N(n1536), .B0(n1535), .Y(n602) );
AFHCINX2TS U1877 ( .CIN(n1537), .B(n1834), .A(DMP_SFG[14]), .S(n1541), .CO(
n1547) );
AFHCONX2TS U1878 ( .A(DmP_mant_SFG_SWR[16]), .B(DMP_SFG[14]), .CI(n1538),
.CON(n1548), .S(n1539) );
AOI22X1TS U1879 ( .A0(n1539), .A1(n1621), .B0(Raw_mant_NRM_SWR[16]), .B1(
n1807), .Y(n1540) );
OAI2BB1X1TS U1880 ( .A0N(n1552), .A1N(n1541), .B0(n1540), .Y(n604) );
AFHCONX2TS U1881 ( .A(DMP_SFG[13]), .B(n1844), .CI(n1542), .CON(n1537), .S(
n1546) );
AFHCINX2TS U1882 ( .CIN(n1543), .B(DMP_SFG[13]), .A(DmP_mant_SFG_SWR[15]),
.S(n1544), .CO(n1538) );
AOI22X1TS U1883 ( .A0(n1544), .A1(n1621), .B0(Raw_mant_NRM_SWR[15]), .B1(
n1807), .Y(n1545) );
OAI2BB1X1TS U1884 ( .A0N(n1552), .A1N(n1546), .B0(n1545), .Y(n605) );
AFHCONX2TS U1885 ( .A(DMP_SFG[15]), .B(n1843), .CI(n1547), .CON(n1532), .S(
n1551) );
AFHCINX2TS U1886 ( .CIN(n1548), .B(DMP_SFG[15]), .A(DmP_mant_SFG_SWR[17]),
.S(n1549), .CO(n1533) );
AOI22X1TS U1887 ( .A0(n1549), .A1(n1621), .B0(Raw_mant_NRM_SWR[17]), .B1(
n1807), .Y(n1550) );
OAI2BB1X1TS U1888 ( .A0N(n1552), .A1N(n1551), .B0(n1550), .Y(n603) );
CLKBUFX2TS U1889 ( .A(n1552), .Y(n1625) );
AFHCINX2TS U1890 ( .CIN(n1553), .B(n1835), .A(DMP_SFG[12]), .S(n1557), .CO(
n1542) );
AFHCONX2TS U1891 ( .A(DmP_mant_SFG_SWR[14]), .B(DMP_SFG[12]), .CI(n1554),
.CON(n1543), .S(n1555) );
AOI22X1TS U1892 ( .A0(n1555), .A1(n1621), .B0(Raw_mant_NRM_SWR[14]), .B1(
n1807), .Y(n1556) );
OAI2BB1X1TS U1893 ( .A0N(n1625), .A1N(n1557), .B0(n1556), .Y(n606) );
AFHCONX2TS U1894 ( .A(DMP_SFG[11]), .B(n1845), .CI(n1558), .CON(n1553), .S(
n1562) );
AFHCINX2TS U1895 ( .CIN(n1559), .B(DMP_SFG[11]), .A(DmP_mant_SFG_SWR[13]),
.S(n1560), .CO(n1554) );
AOI22X1TS U1896 ( .A0(n1560), .A1(n1621), .B0(Raw_mant_NRM_SWR[13]), .B1(
n1807), .Y(n1561) );
OAI2BB1X1TS U1897 ( .A0N(n1625), .A1N(n1562), .B0(n1561), .Y(n607) );
AFHCONX2TS U1898 ( .A(DMP_SFG[9]), .B(n1846), .CI(n1563), .CON(n1568), .S(
n1567) );
AFHCINX2TS U1899 ( .CIN(n1564), .B(DMP_SFG[9]), .A(DmP_mant_SFG_SWR[11]),
.S(n1565), .CO(n1569) );
AOI22X1TS U1900 ( .A0(n1565), .A1(n1621), .B0(Raw_mant_NRM_SWR[11]), .B1(
n1807), .Y(n1566) );
OAI2BB1X1TS U1901 ( .A0N(n1625), .A1N(n1567), .B0(n1566), .Y(n609) );
AFHCINX2TS U1902 ( .CIN(n1568), .B(n1836), .A(DMP_SFG[10]), .S(n1573), .CO(
n1558) );
AFHCONX2TS U1903 ( .A(DmP_mant_SFG_SWR[12]), .B(DMP_SFG[10]), .CI(n1569),
.CON(n1559), .S(n1571) );
CLKBUFX2TS U1904 ( .A(n1570), .Y(n1613) );
AOI22X1TS U1905 ( .A0(n1571), .A1(n1613), .B0(Raw_mant_NRM_SWR[12]), .B1(
n1807), .Y(n1572) );
OAI2BB1X1TS U1906 ( .A0N(n1625), .A1N(n1573), .B0(n1572), .Y(n608) );
AFHCINX2TS U1907 ( .CIN(n1574), .B(n1837), .A(DMP_SFG[8]), .S(n1578), .CO(
n1563) );
AFHCONX2TS U1908 ( .A(DmP_mant_SFG_SWR[10]), .B(DMP_SFG[8]), .CI(n1575),
.CON(n1564), .S(n1576) );
AOI22X1TS U1909 ( .A0(n1576), .A1(n1613), .B0(Raw_mant_NRM_SWR[10]), .B1(
n1807), .Y(n1577) );
OAI2BB1X1TS U1910 ( .A0N(n1625), .A1N(n1578), .B0(n1577), .Y(n610) );
AFHCONX2TS U1911 ( .A(DMP_SFG[7]), .B(n1847), .CI(n1579), .CON(n1574), .S(
n1583) );
AFHCINX2TS U1912 ( .CIN(n1580), .B(DMP_SFG[7]), .A(DmP_mant_SFG_SWR[9]), .S(
n1581), .CO(n1575) );
AOI22X1TS U1913 ( .A0(n1581), .A1(n1613), .B0(Raw_mant_NRM_SWR[9]), .B1(
n1807), .Y(n1582) );
OAI2BB1X1TS U1914 ( .A0N(n1625), .A1N(n1583), .B0(n1582), .Y(n611) );
AFHCINX2TS U1915 ( .CIN(n1584), .B(n1838), .A(DMP_SFG[6]), .S(n1588), .CO(
n1579) );
AFHCONX2TS U1916 ( .A(DmP_mant_SFG_SWR[8]), .B(DMP_SFG[6]), .CI(n1585),
.CON(n1580), .S(n1586) );
AOI22X1TS U1917 ( .A0(n1586), .A1(n1613), .B0(Raw_mant_NRM_SWR[8]), .B1(
n1620), .Y(n1587) );
OAI2BB1X1TS U1918 ( .A0N(n1625), .A1N(n1588), .B0(n1587), .Y(n612) );
AFHCONX2TS U1919 ( .A(DMP_SFG[5]), .B(n1848), .CI(n1589), .CON(n1584), .S(
n1593) );
AFHCINX2TS U1920 ( .CIN(n1590), .B(DMP_SFG[5]), .A(DmP_mant_SFG_SWR[7]), .S(
n1591), .CO(n1585) );
AOI22X1TS U1921 ( .A0(n1591), .A1(n1613), .B0(Raw_mant_NRM_SWR[7]), .B1(
n1620), .Y(n1592) );
OAI2BB1X1TS U1922 ( .A0N(n1625), .A1N(n1593), .B0(n1592), .Y(n613) );
AFHCINX2TS U1923 ( .CIN(n1594), .B(n1839), .A(DMP_SFG[4]), .S(n1598), .CO(
n1589) );
AFHCONX2TS U1924 ( .A(DmP_mant_SFG_SWR[6]), .B(DMP_SFG[4]), .CI(n1595),
.CON(n1590), .S(n1596) );
AOI22X1TS U1925 ( .A0(n1596), .A1(n1613), .B0(Raw_mant_NRM_SWR[6]), .B1(
n1620), .Y(n1597) );
OAI2BB1X1TS U1926 ( .A0N(n1625), .A1N(n1598), .B0(n1597), .Y(n614) );
AFHCONX2TS U1927 ( .A(DMP_SFG[1]), .B(n1849), .CI(n1599), .CON(n1611), .S(
n1602) );
AFHCINX2TS U1928 ( .CIN(n1606), .B(DMP_SFG[1]), .A(DmP_mant_SFG_SWR[3]), .S(
n1600), .CO(n1612) );
AOI22X1TS U1929 ( .A0(n1600), .A1(n1613), .B0(Raw_mant_NRM_SWR[3]), .B1(
n1620), .Y(n1601) );
OAI2BB1X1TS U1930 ( .A0N(n1617), .A1N(n1602), .B0(n1601), .Y(n617) );
AHHCONX2TS U1931 ( .A(n1850), .CI(n1766), .CON(n1605), .S(n1604) );
AOI22X1TS U1932 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n1613), .B0(n1620), .B1(
Raw_mant_NRM_SWR[1]), .Y(n1603) );
OAI2BB1X1TS U1933 ( .A0N(n1617), .A1N(n1604), .B0(n1603), .Y(n619) );
AFHCINX2TS U1934 ( .CIN(n1605), .B(n1825), .A(DMP_SFG[0]), .S(n1610), .CO(
n1599) );
OR2X1TS U1935 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n1607) );
CLKAND2X2TS U1936 ( .A(n1607), .B(n1606), .Y(n1608) );
AOI22X1TS U1937 ( .A0(n1608), .A1(n1613), .B0(Raw_mant_NRM_SWR[2]), .B1(
n1620), .Y(n1609) );
OAI2BB1X1TS U1938 ( .A0N(n1617), .A1N(n1610), .B0(n1609), .Y(n618) );
AFHCINX2TS U1939 ( .CIN(n1611), .B(n1840), .A(DMP_SFG[2]), .S(n1616), .CO(
n1618) );
AFHCONX2TS U1940 ( .A(DmP_mant_SFG_SWR[4]), .B(DMP_SFG[2]), .CI(n1612),
.CON(n1619), .S(n1614) );
AOI22X1TS U1941 ( .A0(n1614), .A1(n1613), .B0(Raw_mant_NRM_SWR[4]), .B1(
n1620), .Y(n1615) );
OAI2BB1X1TS U1942 ( .A0N(n1617), .A1N(n1616), .B0(n1615), .Y(n616) );
AFHCONX2TS U1943 ( .A(DMP_SFG[3]), .B(n1767), .CI(n1618), .CON(n1594), .S(
n1624) );
AFHCINX2TS U1944 ( .CIN(n1619), .B(DMP_SFG[3]), .A(DmP_mant_SFG_SWR[5]), .S(
n1622), .CO(n1595) );
AOI22X1TS U1945 ( .A0(n1622), .A1(n1621), .B0(Raw_mant_NRM_SWR[5]), .B1(
n1620), .Y(n1623) );
OAI2BB1X1TS U1946 ( .A0N(n1625), .A1N(n1624), .B0(n1623), .Y(n615) );
MX2X1TS U1947 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n691) );
MX2X1TS U1948 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n696) );
MX2X1TS U1949 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n701) );
MX2X1TS U1950 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n706) );
MX2X1TS U1951 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n711) );
MX2X1TS U1952 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n716) );
MX2X1TS U1953 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n721) );
MX2X1TS U1954 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n726) );
INVX2TS U1955 ( .A(n1632), .Y(n1631) );
AOI22X1TS U1956 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1631), .B1(n1756), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1957 ( .A(n1631), .B(n1630), .Y(n952) );
INVX2TS U1958 ( .A(n1637), .Y(n1635) );
AOI22X1TS U1959 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1632), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1756), .Y(n1638) );
CLKBUFX2TS U1960 ( .A(n1824), .Y(n1700) );
AOI22X1TS U1961 ( .A0(n1637), .A1(n1633), .B0(n1700), .B1(n1635), .Y(n949)
);
AOI22X1TS U1962 ( .A0(n1637), .A1(n1700), .B0(n1680), .B1(n1635), .Y(n948)
);
AO22XLTS U1963 ( .A0(n1637), .A1(busy), .B0(n1635), .B1(Shift_reg_FLAGS_7[3]), .Y(n947) );
AOI22X1TS U1964 ( .A0(n1637), .A1(n1634), .B0(n1636), .B1(n1635), .Y(n945)
);
AOI22X1TS U1965 ( .A0(n1637), .A1(n1636), .B0(n1736), .B1(n1635), .Y(n944)
);
CLKBUFX2TS U1966 ( .A(n1643), .Y(n1640) );
CLKBUFX2TS U1967 ( .A(n1643), .Y(n1653) );
INVX2TS U1968 ( .A(n1653), .Y(n1651) );
CLKBUFX2TS U1969 ( .A(n1643), .Y(n1650) );
INVX2TS U1970 ( .A(n1650), .Y(n1639) );
CLKBUFX2TS U1971 ( .A(n1643), .Y(n1647) );
INVX2TS U1972 ( .A(n1640), .Y(n1652) );
INVX2TS U1973 ( .A(n1647), .Y(n1641) );
CLKBUFX2TS U1974 ( .A(n1643), .Y(n1648) );
CLKBUFX2TS U1975 ( .A(n1643), .Y(n1645) );
INVX2TS U1976 ( .A(n1648), .Y(n1642) );
CLKBUFX2TS U1977 ( .A(n1643), .Y(n1646) );
INVX2TS U1978 ( .A(n1646), .Y(n1644) );
INVX2TS U1979 ( .A(n1645), .Y(n1649) );
OAI22X1TS U1980 ( .A0(n1656), .A1(n1655), .B0(n1654), .B1(n1809), .Y(n876)
);
NAND2X1TS U1981 ( .A(DmP_EXP_EWSW[23]), .B(n1816), .Y(n1658) );
OAI21XLTS U1982 ( .A0(DmP_EXP_EWSW[23]), .A1(n1816), .B0(n1658), .Y(n1657)
);
CLKBUFX2TS U1983 ( .A(n1824), .Y(n1701) );
AO22XLTS U1984 ( .A0(n1742), .A1(n1657), .B0(n1701), .B1(
Shift_amount_SHT1_EWR[0]), .Y(n846) );
INVX2TS U1985 ( .A(n1658), .Y(n1662) );
AOI21X1TS U1986 ( .A0(DMP_EXP_EWSW[24]), .A1(n1762), .B0(n1661), .Y(n1659)
);
XNOR2X1TS U1987 ( .A(n1662), .B(n1659), .Y(n1660) );
CLKBUFX2TS U1988 ( .A(n1824), .Y(n1679) );
AO22XLTS U1989 ( .A0(n1742), .A1(n1660), .B0(n1679), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n845) );
OAI22X1TS U1990 ( .A0(n1662), .A1(n1661), .B0(DmP_EXP_EWSW[24]), .B1(n1763),
.Y(n1665) );
NAND2X1TS U1991 ( .A(DmP_EXP_EWSW[25]), .B(n1813), .Y(n1666) );
XNOR2X1TS U1992 ( .A(n1665), .B(n1663), .Y(n1664) );
AO22XLTS U1993 ( .A0(n1742), .A1(n1664), .B0(n1679), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n844) );
AOI22X1TS U1994 ( .A0(DMP_EXP_EWSW[25]), .A1(n1822), .B0(n1666), .B1(n1665),
.Y(n1669) );
AOI21X1TS U1995 ( .A0(DMP_EXP_EWSW[26]), .A1(n1818), .B0(n1670), .Y(n1667)
);
XNOR2X1TS U1996 ( .A(n1669), .B(n1667), .Y(n1668) );
AO22XLTS U1997 ( .A0(n1742), .A1(n1668), .B0(n1679), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n843) );
OAI22X1TS U1998 ( .A0(n1670), .A1(n1669), .B0(DmP_EXP_EWSW[26]), .B1(n1821),
.Y(n1672) );
XNOR2X1TS U1999 ( .A(DmP_EXP_EWSW[27]), .B(DMP_EXP_EWSW[27]), .Y(n1671) );
AO22XLTS U2000 ( .A0(n1742), .A1(n1673), .B0(n1679), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n842) );
OAI222X1TS U2001 ( .A0(n1695), .A1(n1819), .B0(n1763), .B1(
Shift_reg_FLAGS_7_6), .C0(n1740), .C1(n1696), .Y(n809) );
OAI222X1TS U2002 ( .A0(n1695), .A1(n1744), .B0(n1813), .B1(
Shift_reg_FLAGS_7_6), .C0(n1787), .C1(n1696), .Y(n808) );
OAI222X1TS U2003 ( .A0(n1695), .A1(n1745), .B0(n1821), .B1(
Shift_reg_FLAGS_7_6), .C0(n1786), .C1(n1696), .Y(n807) );
OAI21XLTS U2004 ( .A0(n1675), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1674) );
AOI21X1TS U2005 ( .A0(n1675), .A1(intDX_EWSW[31]), .B0(n1674), .Y(n1677) );
AO21XLTS U2006 ( .A0(OP_FLAG_EXP), .A1(n1676), .B0(n1677), .Y(n802) );
AO22XLTS U2007 ( .A0(n1678), .A1(n1677), .B0(ZERO_FLAG_EXP), .B1(n1676), .Y(
n801) );
AO22XLTS U2008 ( .A0(n1742), .A1(DMP_EXP_EWSW[0]), .B0(n1679), .B1(
DMP_SHT1_EWSW[0]), .Y(n799) );
AO22XLTS U2009 ( .A0(n1742), .A1(DMP_EXP_EWSW[1]), .B0(n1679), .B1(
DMP_SHT1_EWSW[1]), .Y(n796) );
AO22XLTS U2010 ( .A0(n1742), .A1(DMP_EXP_EWSW[2]), .B0(n1679), .B1(
DMP_SHT1_EWSW[2]), .Y(n793) );
AO22XLTS U2011 ( .A0(n1742), .A1(DMP_EXP_EWSW[3]), .B0(n1679), .B1(
DMP_SHT1_EWSW[3]), .Y(n790) );
AO22XLTS U2012 ( .A0(n1742), .A1(DMP_EXP_EWSW[4]), .B0(n1679), .B1(
DMP_SHT1_EWSW[4]), .Y(n787) );
INVX2TS U2013 ( .A(n1701), .Y(n1681) );
AO22XLTS U2014 ( .A0(n1681), .A1(DMP_EXP_EWSW[5]), .B0(n1679), .B1(
DMP_SHT1_EWSW[5]), .Y(n784) );
CLKBUFX2TS U2015 ( .A(n1824), .Y(n1682) );
AO22XLTS U2016 ( .A0(n1681), .A1(DMP_EXP_EWSW[6]), .B0(n1682), .B1(
DMP_SHT1_EWSW[6]), .Y(n781) );
AO22XLTS U2017 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1680), .B1(
DMP_SHT2_EWSW[6]), .Y(n780) );
AO22XLTS U2018 ( .A0(n1681), .A1(DMP_EXP_EWSW[7]), .B0(n1682), .B1(
DMP_SHT1_EWSW[7]), .Y(n778) );
AO22XLTS U2019 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n1680), .B1(
DMP_SHT2_EWSW[7]), .Y(n777) );
AO22XLTS U2020 ( .A0(n1681), .A1(DMP_EXP_EWSW[8]), .B0(n1682), .B1(
DMP_SHT1_EWSW[8]), .Y(n775) );
CLKBUFX2TS U2021 ( .A(n1826), .Y(n1704) );
CLKBUFX2TS U2022 ( .A(n1704), .Y(n1683) );
AO22XLTS U2023 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1683), .B1(
DMP_SHT2_EWSW[8]), .Y(n774) );
AO22XLTS U2024 ( .A0(n1681), .A1(DMP_EXP_EWSW[9]), .B0(n1682), .B1(
DMP_SHT1_EWSW[9]), .Y(n772) );
INVX2TS U2025 ( .A(n1686), .Y(n1689) );
AO22XLTS U2026 ( .A0(n1689), .A1(DMP_SHT1_EWSW[9]), .B0(n1683), .B1(
DMP_SHT2_EWSW[9]), .Y(n771) );
AO22XLTS U2027 ( .A0(n1681), .A1(DMP_EXP_EWSW[10]), .B0(n1682), .B1(
DMP_SHT1_EWSW[10]), .Y(n769) );
AO22XLTS U2028 ( .A0(busy), .A1(DMP_SHT1_EWSW[10]), .B0(n1683), .B1(
DMP_SHT2_EWSW[10]), .Y(n768) );
AO22XLTS U2029 ( .A0(n1681), .A1(DMP_EXP_EWSW[11]), .B0(n1682), .B1(
DMP_SHT1_EWSW[11]), .Y(n766) );
AO22XLTS U2030 ( .A0(n1689), .A1(DMP_SHT1_EWSW[11]), .B0(n1683), .B1(
DMP_SHT2_EWSW[11]), .Y(n765) );
AO22XLTS U2031 ( .A0(n1681), .A1(DMP_EXP_EWSW[12]), .B0(n1682), .B1(
DMP_SHT1_EWSW[12]), .Y(n763) );
AO22XLTS U2032 ( .A0(n1689), .A1(DMP_SHT1_EWSW[12]), .B0(n1683), .B1(
DMP_SHT2_EWSW[12]), .Y(n762) );
AO22XLTS U2033 ( .A0(n1681), .A1(DMP_EXP_EWSW[13]), .B0(n1682), .B1(
DMP_SHT1_EWSW[13]), .Y(n760) );
AO22XLTS U2034 ( .A0(n1689), .A1(DMP_SHT1_EWSW[13]), .B0(n1683), .B1(
DMP_SHT2_EWSW[13]), .Y(n759) );
AO22XLTS U2035 ( .A0(n1681), .A1(DMP_EXP_EWSW[14]), .B0(n1682), .B1(
DMP_SHT1_EWSW[14]), .Y(n757) );
AO22XLTS U2036 ( .A0(n1689), .A1(DMP_SHT1_EWSW[14]), .B0(n1683), .B1(
DMP_SHT2_EWSW[14]), .Y(n756) );
INVX2TS U2037 ( .A(n1701), .Y(n1685) );
AO22XLTS U2038 ( .A0(n1685), .A1(DMP_EXP_EWSW[15]), .B0(n1682), .B1(
DMP_SHT1_EWSW[15]), .Y(n754) );
AO22XLTS U2039 ( .A0(n1689), .A1(DMP_SHT1_EWSW[15]), .B0(n1683), .B1(
DMP_SHT2_EWSW[15]), .Y(n753) );
CLKBUFX2TS U2040 ( .A(n1824), .Y(n1687) );
AO22XLTS U2041 ( .A0(n1685), .A1(DMP_EXP_EWSW[16]), .B0(n1687), .B1(
DMP_SHT1_EWSW[16]), .Y(n751) );
AO22XLTS U2042 ( .A0(n1689), .A1(DMP_SHT1_EWSW[16]), .B0(n1683), .B1(
DMP_SHT2_EWSW[16]), .Y(n750) );
AO22XLTS U2043 ( .A0(n1685), .A1(DMP_EXP_EWSW[17]), .B0(n1687), .B1(
DMP_SHT1_EWSW[17]), .Y(n748) );
AO22XLTS U2044 ( .A0(n1689), .A1(DMP_SHT1_EWSW[17]), .B0(n1683), .B1(
DMP_SHT2_EWSW[17]), .Y(n747) );
AO22XLTS U2045 ( .A0(n1685), .A1(DMP_EXP_EWSW[18]), .B0(n1687), .B1(
DMP_SHT1_EWSW[18]), .Y(n745) );
AO22XLTS U2046 ( .A0(n1689), .A1(DMP_SHT1_EWSW[18]), .B0(n1826), .B1(
DMP_SHT2_EWSW[18]), .Y(n744) );
AO22XLTS U2047 ( .A0(n1685), .A1(DMP_EXP_EWSW[19]), .B0(n1687), .B1(
DMP_SHT1_EWSW[19]), .Y(n742) );
INVX2TS U2048 ( .A(n1686), .Y(n1691) );
AO22XLTS U2049 ( .A0(n1691), .A1(DMP_SHT1_EWSW[19]), .B0(n1686), .B1(
DMP_SHT2_EWSW[19]), .Y(n741) );
AO22XLTS U2050 ( .A0(n1685), .A1(DMP_EXP_EWSW[20]), .B0(n1687), .B1(
DMP_SHT1_EWSW[20]), .Y(n739) );
AO22XLTS U2051 ( .A0(n1691), .A1(DMP_SHT1_EWSW[20]), .B0(n1686), .B1(
DMP_SHT2_EWSW[20]), .Y(n738) );
AO22XLTS U2052 ( .A0(n1685), .A1(DMP_EXP_EWSW[21]), .B0(n1687), .B1(
DMP_SHT1_EWSW[21]), .Y(n736) );
AO22XLTS U2053 ( .A0(n1691), .A1(DMP_SHT1_EWSW[21]), .B0(n1686), .B1(
DMP_SHT2_EWSW[21]), .Y(n735) );
AO22XLTS U2054 ( .A0(n1685), .A1(DMP_EXP_EWSW[22]), .B0(n1687), .B1(
DMP_SHT1_EWSW[22]), .Y(n733) );
AO22XLTS U2055 ( .A0(n1691), .A1(DMP_SHT1_EWSW[22]), .B0(n1686), .B1(
DMP_SHT2_EWSW[22]), .Y(n732) );
AO22XLTS U2056 ( .A0(n1685), .A1(DMP_EXP_EWSW[23]), .B0(n1687), .B1(
DMP_SHT1_EWSW[23]), .Y(n730) );
AO22XLTS U2057 ( .A0(n1691), .A1(DMP_SHT1_EWSW[23]), .B0(n1686), .B1(
DMP_SHT2_EWSW[23]), .Y(n729) );
AO22XLTS U2058 ( .A0(n1688), .A1(DMP_SHT2_EWSW[23]), .B0(n1705), .B1(
DMP_SFG[23]), .Y(n728) );
CLKBUFX2TS U2059 ( .A(n1684), .Y(n1707) );
AO22XLTS U2060 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[23]), .B0(n1707),
.B1(DMP_exp_NRM_EW[0]), .Y(n727) );
AO22XLTS U2061 ( .A0(n1685), .A1(DMP_EXP_EWSW[24]), .B0(n1687), .B1(
DMP_SHT1_EWSW[24]), .Y(n725) );
AO22XLTS U2062 ( .A0(n1691), .A1(DMP_SHT1_EWSW[24]), .B0(n1686), .B1(
DMP_SHT2_EWSW[24]), .Y(n724) );
INVX2TS U2063 ( .A(n1688), .Y(n1699) );
AO22XLTS U2064 ( .A0(n1688), .A1(DMP_SHT2_EWSW[24]), .B0(n1699), .B1(
DMP_SFG[24]), .Y(n723) );
AO22XLTS U2065 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[24]), .B0(n1707),
.B1(DMP_exp_NRM_EW[1]), .Y(n722) );
INVX2TS U2066 ( .A(n1701), .Y(n1692) );
AO22XLTS U2067 ( .A0(n1692), .A1(DMP_EXP_EWSW[25]), .B0(n1687), .B1(
DMP_SHT1_EWSW[25]), .Y(n720) );
AO22XLTS U2068 ( .A0(n1691), .A1(DMP_SHT1_EWSW[25]), .B0(n1704), .B1(
DMP_SHT2_EWSW[25]), .Y(n719) );
AO22XLTS U2069 ( .A0(n1688), .A1(DMP_SHT2_EWSW[25]), .B0(n1705), .B1(
DMP_SFG[25]), .Y(n718) );
AO22XLTS U2070 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[25]), .B0(n1707),
.B1(DMP_exp_NRM_EW[2]), .Y(n717) );
CLKBUFX2TS U2071 ( .A(n1824), .Y(n1702) );
AO22XLTS U2072 ( .A0(n1692), .A1(DMP_EXP_EWSW[26]), .B0(n1702), .B1(
DMP_SHT1_EWSW[26]), .Y(n715) );
AO22XLTS U2073 ( .A0(n1689), .A1(DMP_SHT1_EWSW[26]), .B0(n1704), .B1(
DMP_SHT2_EWSW[26]), .Y(n714) );
AO22XLTS U2074 ( .A0(n1690), .A1(DMP_SHT2_EWSW[26]), .B0(n1699), .B1(
DMP_SFG[26]), .Y(n713) );
AO22XLTS U2075 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[26]), .B0(n1707),
.B1(DMP_exp_NRM_EW[3]), .Y(n712) );
AO22XLTS U2076 ( .A0(n1692), .A1(DMP_EXP_EWSW[27]), .B0(n1702), .B1(
DMP_SHT1_EWSW[27]), .Y(n710) );
AO22XLTS U2077 ( .A0(n1691), .A1(DMP_SHT1_EWSW[27]), .B0(n1704), .B1(
DMP_SHT2_EWSW[27]), .Y(n709) );
AO22XLTS U2078 ( .A0(n1706), .A1(DMP_SHT2_EWSW[27]), .B0(n1699), .B1(
DMP_SFG[27]), .Y(n708) );
AO22XLTS U2079 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[27]), .B0(n1707),
.B1(DMP_exp_NRM_EW[4]), .Y(n707) );
AO22XLTS U2080 ( .A0(n1692), .A1(DMP_EXP_EWSW[28]), .B0(n1702), .B1(
DMP_SHT1_EWSW[28]), .Y(n705) );
AO22XLTS U2081 ( .A0(n1691), .A1(DMP_SHT1_EWSW[28]), .B0(n1704), .B1(
DMP_SHT2_EWSW[28]), .Y(n704) );
AO22XLTS U2082 ( .A0(n1706), .A1(DMP_SHT2_EWSW[28]), .B0(n1699), .B1(
DMP_SFG[28]), .Y(n703) );
AO22XLTS U2083 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[28]), .B0(n1707),
.B1(DMP_exp_NRM_EW[5]), .Y(n702) );
AO22XLTS U2084 ( .A0(n1692), .A1(DMP_EXP_EWSW[29]), .B0(n1702), .B1(
DMP_SHT1_EWSW[29]), .Y(n700) );
AO22XLTS U2085 ( .A0(n1691), .A1(DMP_SHT1_EWSW[29]), .B0(n1704), .B1(
DMP_SHT2_EWSW[29]), .Y(n699) );
AO22XLTS U2086 ( .A0(n1706), .A1(DMP_SHT2_EWSW[29]), .B0(n1699), .B1(
DMP_SFG[29]), .Y(n698) );
AO22XLTS U2087 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[29]), .B0(n1707),
.B1(DMP_exp_NRM_EW[6]), .Y(n697) );
AO22XLTS U2088 ( .A0(n1692), .A1(DMP_EXP_EWSW[30]), .B0(n1702), .B1(
DMP_SHT1_EWSW[30]), .Y(n695) );
AO22XLTS U2089 ( .A0(n1743), .A1(DMP_SHT1_EWSW[30]), .B0(n1704), .B1(
DMP_SHT2_EWSW[30]), .Y(n694) );
AO22XLTS U2090 ( .A0(n1706), .A1(DMP_SHT2_EWSW[30]), .B0(n1699), .B1(
DMP_SFG[30]), .Y(n693) );
AO22XLTS U2091 ( .A0(Shift_reg_FLAGS_7[2]), .A1(DMP_SFG[30]), .B0(n1707),
.B1(DMP_exp_NRM_EW[7]), .Y(n692) );
AO22XLTS U2092 ( .A0(n1692), .A1(DmP_EXP_EWSW[0]), .B0(n1702), .B1(
DmP_mant_SHT1_SW[0]), .Y(n689) );
AO22XLTS U2093 ( .A0(n1692), .A1(DmP_EXP_EWSW[1]), .B0(n1702), .B1(
DmP_mant_SHT1_SW[1]), .Y(n687) );
AO22XLTS U2094 ( .A0(n1692), .A1(DmP_EXP_EWSW[2]), .B0(n1702), .B1(
DmP_mant_SHT1_SW[2]), .Y(n685) );
AO22XLTS U2095 ( .A0(n1692), .A1(DmP_EXP_EWSW[3]), .B0(n1702), .B1(
DmP_mant_SHT1_SW[3]), .Y(n683) );
INVX2TS U2096 ( .A(n1700), .Y(n1693) );
AO22XLTS U2097 ( .A0(n1693), .A1(DmP_EXP_EWSW[4]), .B0(n1701), .B1(
DmP_mant_SHT1_SW[4]), .Y(n681) );
AO22XLTS U2098 ( .A0(n1693), .A1(DmP_EXP_EWSW[5]), .B0(n1701), .B1(
DmP_mant_SHT1_SW[5]), .Y(n679) );
AO22XLTS U2099 ( .A0(n1693), .A1(DmP_EXP_EWSW[6]), .B0(n1700), .B1(
DmP_mant_SHT1_SW[6]), .Y(n677) );
AO22XLTS U2100 ( .A0(n1693), .A1(DmP_EXP_EWSW[7]), .B0(n1701), .B1(
DmP_mant_SHT1_SW[7]), .Y(n675) );
AO22XLTS U2101 ( .A0(n1693), .A1(DmP_EXP_EWSW[8]), .B0(n1700), .B1(
DmP_mant_SHT1_SW[8]), .Y(n673) );
AO22XLTS U2102 ( .A0(n1693), .A1(DmP_EXP_EWSW[9]), .B0(n1701), .B1(
DmP_mant_SHT1_SW[9]), .Y(n671) );
AO22XLTS U2103 ( .A0(n1693), .A1(DmP_EXP_EWSW[10]), .B0(n1700), .B1(
DmP_mant_SHT1_SW[10]), .Y(n669) );
AO22XLTS U2104 ( .A0(n1693), .A1(DmP_EXP_EWSW[11]), .B0(n1700), .B1(
DmP_mant_SHT1_SW[11]), .Y(n667) );
AO22XLTS U2105 ( .A0(n1693), .A1(DmP_EXP_EWSW[12]), .B0(n1700), .B1(
DmP_mant_SHT1_SW[12]), .Y(n665) );
AO22XLTS U2106 ( .A0(n1693), .A1(DmP_EXP_EWSW[13]), .B0(n1824), .B1(
DmP_mant_SHT1_SW[13]), .Y(n663) );
INVX2TS U2107 ( .A(n1700), .Y(n1698) );
CLKBUFX2TS U2108 ( .A(n1824), .Y(n1694) );
AO22XLTS U2109 ( .A0(n1698), .A1(DmP_EXP_EWSW[14]), .B0(n1694), .B1(
DmP_mant_SHT1_SW[14]), .Y(n661) );
AO22XLTS U2110 ( .A0(n1698), .A1(DmP_EXP_EWSW[15]), .B0(n1694), .B1(
DmP_mant_SHT1_SW[15]), .Y(n659) );
AO22XLTS U2111 ( .A0(n1698), .A1(DmP_EXP_EWSW[16]), .B0(n1694), .B1(
DmP_mant_SHT1_SW[16]), .Y(n657) );
AO22XLTS U2112 ( .A0(n1698), .A1(DmP_EXP_EWSW[17]), .B0(n1694), .B1(
DmP_mant_SHT1_SW[17]), .Y(n655) );
AO22XLTS U2113 ( .A0(n1698), .A1(DmP_EXP_EWSW[18]), .B0(n1694), .B1(
DmP_mant_SHT1_SW[18]), .Y(n653) );
AO22XLTS U2114 ( .A0(n1698), .A1(DmP_EXP_EWSW[19]), .B0(n1694), .B1(
DmP_mant_SHT1_SW[19]), .Y(n651) );
AO22XLTS U2115 ( .A0(n1698), .A1(DmP_EXP_EWSW[20]), .B0(n1694), .B1(
DmP_mant_SHT1_SW[20]), .Y(n649) );
AO22XLTS U2116 ( .A0(n1698), .A1(DmP_EXP_EWSW[21]), .B0(n1694), .B1(
DmP_mant_SHT1_SW[21]), .Y(n647) );
AO22XLTS U2117 ( .A0(n1698), .A1(DmP_EXP_EWSW[22]), .B0(n1694), .B1(
DmP_mant_SHT1_SW[22]), .Y(n645) );
OAI222X1TS U2118 ( .A0(n1696), .A1(n1819), .B0(n1762), .B1(
Shift_reg_FLAGS_7_6), .C0(n1740), .C1(n1695), .Y(n643) );
OAI222X1TS U2119 ( .A0(n1696), .A1(n1744), .B0(n1822), .B1(
Shift_reg_FLAGS_7_6), .C0(n1787), .C1(n1695), .Y(n642) );
OAI222X1TS U2120 ( .A0(n1696), .A1(n1745), .B0(n1818), .B1(
Shift_reg_FLAGS_7_6), .C0(n1786), .C1(n1695), .Y(n641) );
CLKBUFX2TS U2121 ( .A(n1725), .Y(n1734) );
AO22XLTS U2122 ( .A0(n1698), .A1(ZERO_FLAG_EXP), .B0(n1701), .B1(
ZERO_FLAG_SHT1), .Y(n637) );
AO22XLTS U2123 ( .A0(n1743), .A1(ZERO_FLAG_SHT1), .B0(n1704), .B1(
ZERO_FLAG_SHT2), .Y(n636) );
AO22XLTS U2124 ( .A0(n1706), .A1(ZERO_FLAG_SHT2), .B0(n1699), .B1(
ZERO_FLAG_SFG), .Y(n635) );
AO22XLTS U2125 ( .A0(n973), .A1(ZERO_FLAG_SFG), .B0(n1707), .B1(
ZERO_FLAG_NRM), .Y(n634) );
AO22XLTS U2126 ( .A0(Shift_reg_FLAGS_7[1]), .A1(ZERO_FLAG_NRM), .B0(n1708),
.B1(ZERO_FLAG_SHT1SHT2), .Y(n633) );
AO22XLTS U2127 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1734), .B1(zero_flag), .Y(n632) );
INVX2TS U2128 ( .A(n1700), .Y(n1703) );
AO22XLTS U2129 ( .A0(n1703), .A1(OP_FLAG_EXP), .B0(n1701), .B1(OP_FLAG_SHT1),
.Y(n631) );
AO22XLTS U2130 ( .A0(n1743), .A1(OP_FLAG_SHT1), .B0(n1704), .B1(OP_FLAG_SHT2), .Y(n630) );
AO22XLTS U2131 ( .A0(n1703), .A1(SIGN_FLAG_EXP), .B0(n1702), .B1(
SIGN_FLAG_SHT1), .Y(n626) );
AO22XLTS U2132 ( .A0(n1743), .A1(SIGN_FLAG_SHT1), .B0(n1704), .B1(
SIGN_FLAG_SHT2), .Y(n625) );
AO22XLTS U2133 ( .A0(n1706), .A1(SIGN_FLAG_SHT2), .B0(n1705), .B1(
SIGN_FLAG_SFG), .Y(n624) );
AO22XLTS U2134 ( .A0(n973), .A1(SIGN_FLAG_SFG), .B0(n1707), .B1(
SIGN_FLAG_NRM), .Y(n623) );
AO22XLTS U2135 ( .A0(n979), .A1(SIGN_FLAG_NRM), .B0(n1708), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n622) );
OAI2BB2XLTS U2136 ( .B0(n1711), .B1(n1737), .A0N(final_result_ieee[10]),
.A1N(n1736), .Y(n589) );
OAI2BB2XLTS U2137 ( .B0(n1712), .B1(n975), .A0N(final_result_ieee[11]),
.A1N(n1827), .Y(n588) );
OAI2BB2XLTS U2138 ( .B0(n1713), .B1(n976), .A0N(final_result_ieee[9]), .A1N(
n1827), .Y(n587) );
OAI2BB2XLTS U2139 ( .B0(n1714), .B1(n1737), .A0N(final_result_ieee[12]),
.A1N(n1827), .Y(n586) );
OAI2BB2XLTS U2140 ( .B0(n1715), .B1(n975), .A0N(final_result_ieee[8]), .A1N(
n1827), .Y(n585) );
OAI2BB2XLTS U2141 ( .B0(n1716), .B1(n976), .A0N(final_result_ieee[13]),
.A1N(n1827), .Y(n584) );
OAI2BB2XLTS U2142 ( .B0(n1717), .B1(n1737), .A0N(final_result_ieee[7]),
.A1N(n1827), .Y(n583) );
OAI2BB2XLTS U2143 ( .B0(n1718), .B1(n975), .A0N(final_result_ieee[6]), .A1N(
n1827), .Y(n582) );
OAI2BB2XLTS U2144 ( .B0(n1719), .B1(n976), .A0N(final_result_ieee[5]), .A1N(
n1827), .Y(n581) );
OAI2BB2XLTS U2145 ( .B0(n1720), .B1(n1737), .A0N(final_result_ieee[4]),
.A1N(n1827), .Y(n580) );
INVX2TS U2146 ( .A(n1721), .Y(n1722) );
OAI2BB2XLTS U2147 ( .B0(n1722), .B1(n975), .A0N(final_result_ieee[3]), .A1N(
n1827), .Y(n579) );
OAI2BB2XLTS U2148 ( .B0(n1723), .B1(n975), .A0N(final_result_ieee[2]), .A1N(
n1725), .Y(n578) );
OAI2BB2XLTS U2149 ( .B0(n1724), .B1(n976), .A0N(final_result_ieee[1]), .A1N(
n1725), .Y(n577) );
OAI2BB2XLTS U2150 ( .B0(n1726), .B1(n1737), .A0N(final_result_ieee[0]),
.A1N(n1725), .Y(n576) );
OAI2BB2XLTS U2151 ( .B0(n1727), .B1(n975), .A0N(final_result_ieee[14]),
.A1N(n1734), .Y(n575) );
OAI2BB2XLTS U2152 ( .B0(n1728), .B1(n976), .A0N(final_result_ieee[15]),
.A1N(n1734), .Y(n574) );
OAI2BB2XLTS U2153 ( .B0(n1729), .B1(n1737), .A0N(final_result_ieee[16]),
.A1N(n1734), .Y(n573) );
OAI2BB2XLTS U2154 ( .B0(n1730), .B1(n975), .A0N(final_result_ieee[17]),
.A1N(n1734), .Y(n572) );
OAI2BB2XLTS U2155 ( .B0(n1731), .B1(n976), .A0N(final_result_ieee[18]),
.A1N(n1734), .Y(n571) );
OAI2BB2XLTS U2156 ( .B0(n1732), .B1(n1737), .A0N(final_result_ieee[19]),
.A1N(n1734), .Y(n570) );
OAI2BB2XLTS U2157 ( .B0(n1733), .B1(n975), .A0N(final_result_ieee[20]),
.A1N(n1734), .Y(n569) );
OAI2BB2XLTS U2158 ( .B0(n1735), .B1(n976), .A0N(final_result_ieee[21]),
.A1N(n1734), .Y(n568) );
OAI2BB2XLTS U2159 ( .B0(n1738), .B1(n1737), .A0N(final_result_ieee[22]),
.A1N(n1736), .Y(n567) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_syn.sdf");
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_timer_ecc_fault_itr (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg d1_data_in;
reg d2_data_in;
wire data_in;
reg edge_capture;
wire edge_capture_wr_strobe;
wire edge_detect;
wire irq;
reg irq_mask;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 2)}} & irq_mask) |
({1 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata;
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture <= 0;
else if (edge_detect)
edge_capture <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in & ~d2_data_in;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__NAND2B_FUNCTIONAL_PP_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nand2b (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y , not0_out, A_N );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2B_FUNCTIONAL_PP_V |
module barrel
#(parameter width=16)
(input [width-1:0] in,
input [$clog2(width)-1:0] ct,
input dir,
input [1:0] type,
output [width-1:0] out);
/* direct inputs = f */
/* shifted inputs = g */
/* mux outputs = h */
wire [width-1:0] f[$clog2(width)-1:0], g[$clog2(width)-1:0], h[$clog2(width):0];
assign h[0] = in;
assign out = h[$clog2(width)-1];
generate
genvar i;
for(i = 0; i < $clog2(width) - 1; i = i+1) begin : a
magic#(.width(width), .shift(2**i)) v(h[i], type, left, g[i]);
mux2 #(.width(width)) u(h[i], g[i], ct[$clog2(width)-i-1], h[i+1]);
end
endgenerate
endmodule
module magic
#(parameter width = 16,
parameter shift = $clog2(width))
(input [width-1:0]h,
input [1:0]type,
input left,
output reg [width-1:0]z);
localparam NS=0, LO=1, AR=2, RO=3;
always @(*) if (left) begin
case(type)
NS: z <= h;
LO: z <= h << shift;
AR: z <= h <<< shift;
RO: z <= { h[width-1-shift:0], h[width-1:width-1-shift-1] };
endcase
end else begin
case(type)
NS: z <= h;
LO: z <= h >> shift;
AR: z <= h >>> shift;
RO: z <= { h[width-1:width-1-shift-1], h[width-1-shift:0] };
endcase
end
endmodule
module mux2
#(parameter width=16)
(input [width-1:0] A, B,
input sel,
output [width-1:0] out);
assign out = sel ? A : B;
endmodule
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module reg_grp #(parameter
REG_ADDR_BITS = 10,
NUM_OUTPUTS = 4
)
(
// Upstream register interface
input reg_req,
input reg_rd_wr_L,
input [REG_ADDR_BITS -1:0] reg_addr,
input [`CPCI_NF2_DATA_WIDTH -1:0] reg_wr_data,
output reg reg_ack,
output reg [`CPCI_NF2_DATA_WIDTH -1:0] reg_rd_data,
// Downstream register interface
output [NUM_OUTPUTS - 1 : 0] local_reg_req,
output [NUM_OUTPUTS - 1 : 0] local_reg_rd_wr_L,
output [NUM_OUTPUTS * (REG_ADDR_BITS - log2(NUM_OUTPUTS)) -1:0] local_reg_addr,
output [NUM_OUTPUTS * `CPCI_NF2_DATA_WIDTH -1:0] local_reg_wr_data,
input [NUM_OUTPUTS - 1 : 0] local_reg_ack,
input [NUM_OUTPUTS * `CPCI_NF2_DATA_WIDTH -1:0] local_reg_rd_data,
//-- misc
input clk,
input reset
);
// Log base 2 function
//
// Returns ceil(log2(X))
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// Register addresses
localparam SWITCH_ADDR_BITS = log2(NUM_OUTPUTS);
// ===========================================
// Local variables
wire [SWITCH_ADDR_BITS - 1 : 0] sel;
integer i;
// Internal register interface signals
reg int_reg_req[NUM_OUTPUTS - 1 : 0];
reg int_reg_rd_wr_L[NUM_OUTPUTS - 1 : 0];
reg [REG_ADDR_BITS -1:0] int_reg_addr[NUM_OUTPUTS - 1 : 0];
reg [`CPCI_NF2_DATA_WIDTH -1:0] int_reg_wr_data[NUM_OUTPUTS - 1 : 0];
wire int_reg_ack[NUM_OUTPUTS - 1 : 0];
wire [`CPCI_NF2_DATA_WIDTH -1:0] int_reg_rd_data[NUM_OUTPUTS - 1 : 0];
assign sel = reg_addr[REG_ADDR_BITS - 1 : REG_ADDR_BITS - SWITCH_ADDR_BITS];
// =====================================================
// Process register requests
always @(posedge clk)
begin
for (i = 0; i < NUM_OUTPUTS ; i = i + 1) begin
if (reset || sel != i) begin
int_reg_req[i] <= 1'b0;
int_reg_rd_wr_L[i] <= 1'b0;
int_reg_addr[i] <= 'h0;
int_reg_wr_data[i] <= 'h0;
end
else begin
int_reg_req[i] <= reg_req;
int_reg_rd_wr_L[i] <= reg_rd_wr_L;
int_reg_addr[i] <= reg_addr;
int_reg_wr_data[i] <= reg_wr_data;
end
end // for
end
always @(posedge clk)
begin
if (reset || sel >= NUM_OUTPUTS) begin
// Reset the outputs
reg_ack <= 1'b0;
reg_rd_data <= reset ? 'h0 : 'h dead_beef;
end
else begin
reg_ack <= int_reg_ack[sel];
reg_rd_data <= int_reg_rd_data[sel];
end
end
// =====================================================
// Logic to split/join inputs/outputs
genvar j;
generate
for (j = 0; j < NUM_OUTPUTS ; j = j + 1) begin : flatten
assign local_reg_req[j] = int_reg_req[j];
assign local_reg_rd_wr_L[j] = int_reg_rd_wr_L[j];
assign local_reg_addr[j * (REG_ADDR_BITS - SWITCH_ADDR_BITS) +: (REG_ADDR_BITS - SWITCH_ADDR_BITS)] = int_reg_addr[j];
assign local_reg_wr_data[j * `CPCI_NF2_DATA_WIDTH +: `CPCI_NF2_DATA_WIDTH] = int_reg_wr_data[j];
assign int_reg_ack[j] = local_reg_ack[j];
assign int_reg_rd_data[j] = local_reg_rd_data[j * `CPCI_NF2_DATA_WIDTH +: `CPCI_NF2_DATA_WIDTH];
end
endgenerate
// =====================================================
// Verify that ack is never high when the request signal is low
// synthesis translate_off
integer k;
always @(posedge clk) begin
if (reg_req === 1'b0)
for (k = 0; k < NUM_OUTPUTS ; k = k + 1)
if (int_reg_ack[k] === 1'b1)
$display($time, " %m: ERROR: int_reg_ack[%1d] is high when reg_req is low", k);
end
// synthesis translate_on
endmodule // reg_grp
|
(** * Logic: Logic in Coq *)
Require Export MoreProp.
(** Coq's built-in logic is very small: the only primitives are
[Inductive] definitions, universal quantification ([forall]), and
implication ([->]), while all the other familiar logical
connectives -- conjunction, disjunction, negation, existential
quantification, even equality -- can be encoded using just these.
This chapter explains the encodings and shows how the tactics
we've seen can be used to carry out standard forms of logical
reasoning involving these connectives. *)
(* ########################################################### *)
(** * Conjunction *)
(** The logical conjunction of propositions [P] and [Q] can be
represented using an [Inductive] definition with one
constructor. *)
Inductive and (P Q : Prop) : Prop :=
conj : P -> Q -> (and P Q).
(** Note that, like the definition of [ev] in a previous
chapter, this definition is parameterized; however, in this case,
the parameters are themselves propositions, rather than numbers. *)
(** The intuition behind this definition is simple: to
construct evidence for [and P Q], we must provide evidence
for [P] and evidence for [Q]. More precisely:
- [conj p q] can be taken as evidence for [and P Q] if [p]
is evidence for [P] and [q] is evidence for [Q]; and
- this is the _only_ way to give evidence for [and P Q] --
that is, if someone gives us evidence for [and P Q], we
know it must have the form [conj p q], where [p] is
evidence for [P] and [q] is evidence for [Q].
Since we'll be using conjunction a lot, let's introduce a more
familiar-looking infix notation for it. *)
Notation "P /\ Q" := (and P Q) : type_scope.
(** (The [type_scope] annotation tells Coq that this notation
will be appearing in propositions, not values.) *)
(** Consider the "type" of the constructor [conj]: *)
Check conj.
(* ===> forall P Q : Prop, P -> Q -> P /\ Q *)
(** Notice that it takes 4 inputs -- namely the propositions [P]
and [Q] and evidence for [P] and [Q] -- and returns as output the
evidence of [P /\ Q]. *)
(** Besides the elegance of building everything up from a tiny
foundation, what's nice about defining conjunction this way is
that we can prove statements involving conjunction using the
tactics that we already know. For example, if the goal statement
is a conjuction, we can prove it by applying the single
constructor [conj], which (as can be seen from the type of [conj])
solves the current goal and leaves the two parts of the
conjunction as subgoals to be proved separately. *)
Theorem and_example :
(beautiful 0) /\ (beautiful 3).
Proof.
apply conj.
Case "left". apply b_0.
Case "right". apply b_3. Qed.
(** Just for convenience, we can use the tactic [split] as a shorthand for
[apply conj]. *)
Theorem and_example' :
(ev 0) /\ (ev 4).
Proof.
split.
Case "left". apply ev_0.
Case "right". apply ev_SS. apply ev_SS. apply ev_0. Qed.
(** Conversely, the [inversion] tactic can be used to take a
conjunction hypothesis in the context, calculate what evidence
must have been used to build it, and add variables representing
this evidence to the proof context. *)
Theorem proj1 : forall P Q : Prop,
P /\ Q -> P.
Proof.
intros P Q H.
inversion H as [HP HQ].
apply HP. Qed.
(** **** Exercise: 1 star, optional (proj2) *)
Theorem proj2 : forall P Q : Prop,
P /\ Q -> Q.
Proof.
intros P Q H. inversion H as [HP HQ]. apply HQ.
Qed.
(** [] *)
Theorem and_commut : forall P Q : Prop,
P /\ Q -> Q /\ P.
Proof.
(* WORKED IN CLASS *)
intros P Q H.
inversion H as [HP HQ].
split.
Case "left". apply HQ.
Case "right". apply HP. Qed.
(** **** Exercise: 2 stars (and_assoc) *)
(** In the following proof, notice how the _nested pattern_ in the
[inversion] breaks the hypothesis [H : P /\ (Q /\ R)] down into
[HP: P], [HQ : Q], and [HR : R]. Finish the proof from there: *)
Theorem and_assoc : forall P Q R : Prop,
P /\ (Q /\ R) -> (P /\ Q) /\ R.
Proof.
intros P Q R H.
inversion H as [HP [HQ HR]].
split. split. apply HP. apply HQ. apply HR.
Qed.
(** [] *)
(** **** Exercise: 2 stars (even__ev) *)
(** Now we can prove the other direction of the equivalence of [even]
and [ev], which we left hanging in chapter [Prop]. Notice that the
left-hand conjunct here is the statement we are actually interested
in; the right-hand conjunct is needed in order to make the
induction hypothesis strong enough that we can carry out the
reasoning in the inductive step. (To see why this is needed, try
proving the left conjunct by itself and observe where things get
stuck.) *)
Theorem even__ev : forall n : nat,
(even n -> ev n) /\ (even (S n) -> ev (S n)).
Proof.
intros n. induction n as [|n].
Case "n=0". split. intro H. apply ev_0. intro H. inversion H.
Case "n=Sn". inversion IHn. split. apply H0. intro H2. apply ev_SS. inversion IHn. apply H1.
unfold even in H2. simpl in H2. unfold even. apply H2.
Qed.
(** [] *)
(* ###################################################### *)
(** ** Iff *)
(** The handy "if and only if" connective is just the conjunction of
two implications. *)
Definition iff (P Q : Prop) := (P -> Q) /\ (Q -> P).
Notation "P <-> Q" := (iff P Q)
(at level 95, no associativity)
: type_scope.
Theorem iff_implies : forall P Q : Prop,
(P <-> Q) -> P -> Q.
Proof.
intros P Q H.
inversion H as [HAB HBA]. apply HAB. Qed.
Theorem iff_sym : forall P Q : Prop,
(P <-> Q) -> (Q <-> P).
Proof.
(* WORKED IN CLASS *)
intros P Q H.
inversion H as [HAB HBA].
split.
Case "->". apply HBA.
Case "<-". apply HAB. Qed.
(** **** Exercise: 1 star, optional (iff_properties) *)
(** Using the above proof that [<->] is symmetric ([iff_sym]) as
a guide, prove that it is also reflexive and transitive. *)
Theorem iff_refl : forall P : Prop,
P <-> P.
Proof.
intros P. unfold iff. split. intro H. apply H. intro H. apply H.
Qed.
Theorem iff_trans : forall P Q R : Prop,
(P <-> Q) -> (Q <-> R) -> (P <-> R).
Proof.
intros P Q R H1 H2. unfold iff. split.
inversion H1. inversion H2. intro. apply H3. apply H. apply H5.
inversion H1. inversion H2. intro. apply H0. apply H4. apply H5.
Qed.
(** Hint: If you have an iff hypothesis in the context, you can use
[inversion] to break it into two separate implications. (Think
about why this works.) *)
(** [] *)
(** Some of Coq's tactics treat [iff] statements specially, thus
avoiding the need for some low-level manipulation when reasoning
with them. In particular, [rewrite] can be used with [iff]
statements, not just equalities. *)
(* ############################################################ *)
(** * Disjunction *)
(** Disjunction ("logical or") can also be defined as an
inductive proposition. *)
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
Notation "P \/ Q" := (or P Q) : type_scope.
(** Consider the "type" of the constructor [or_introl]: *)
Check or_introl.
(* ===> forall P Q : Prop, P -> P \/ Q *)
(** It takes 3 inputs, namely the propositions [P], [Q] and
evidence of [P], and returns, as output, the evidence of [P \/ Q].
Next, look at the type of [or_intror]: *)
Check or_intror.
(* ===> forall P Q : Prop, Q -> P \/ Q *)
(** It is like [or_introl] but it requires evidence of [Q]
instead of evidence of [P]. *)
(** Intuitively, there are two ways of giving evidence for [P \/ Q]:
- give evidence for [P] (and say that it is [P] you are giving
evidence for -- this is the function of the [or_introl]
constructor), or
- give evidence for [Q], tagged with the [or_intror]
constructor. *)
(** Since [P \/ Q] has two constructors, doing [inversion] on a
hypothesis of type [P \/ Q] yields two subgoals. *)
Theorem or_commut : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
inversion H as [HP | HQ].
Case "left". apply or_intror. apply HP.
Case "right". apply or_introl. apply HQ. Qed.
(** From here on, we'll use the shorthand tactics [left] and [right]
in place of [apply or_introl] and [apply or_intror]. *)
Theorem or_commut' : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
inversion H as [HP | HQ].
Case "left". right. apply HP.
Case "right". left. apply HQ. Qed.
Theorem or_distributes_over_and_1 : forall P Q R : Prop,
P \/ (Q /\ R) -> (P \/ Q) /\ (P \/ R).
Proof.
intros P Q R. intros H. inversion H as [HP | [HQ HR]].
Case "left". split.
SCase "left". left. apply HP.
SCase "right". left. apply HP.
Case "right". split.
SCase "left". right. apply HQ.
SCase "right". right. apply HR. Qed.
(** **** Exercise: 2 stars (or_distributes_over_and_2) *)
Theorem or_distributes_over_and_2 : forall P Q R : Prop,
(P \/ Q) /\ (P \/ R) -> P \/ (Q /\ R).
Proof.
intros P Q R H. inversion H as [Hl Hr]. inversion Hl as [HP|HQ]. left. apply HP. inversion Hr as [HP|HR].
left. apply HP. right. split. apply HQ. apply HR.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (or_distributes_over_and) *)
Theorem or_distributes_over_and : forall P Q R : Prop,
P \/ (Q /\ R) <-> (P \/ Q) /\ (P \/ R).
Proof. unfold iff. split. apply or_distributes_over_and_1. apply or_distributes_over_and_2.
Qed.
(** [] *)
(* ################################################### *)
(** ** Relating [/\] and [\/] with [andb] and [orb] (advanced) *)
(** We've already seen several places where analogous structures
can be found in Coq's computational ([Type]) and logical ([Prop])
worlds. Here is one more: the boolean operators [andb] and [orb]
are clearly analogs of the logical connectives [/\] and [\/].
This analogy can be made more precise by the following theorems,
which show how to translate knowledge about [andb] and [orb]'s
behaviors on certain inputs into propositional facts about those
inputs. *)
Theorem andb_prop : forall b c,
andb b c = true -> b = true /\ c = true.
Proof.
(* WORKED IN CLASS *)
intros b c H.
destruct b.
Case "b = true". destruct c.
SCase "c = true". apply conj. reflexivity. reflexivity.
SCase "c = false". inversion H.
Case "b = false". inversion H. Qed.
Theorem andb_true_intro : forall b c,
b = true /\ c = true -> andb b c = true.
Proof.
(* WORKED IN CLASS *)
intros b c H.
inversion H.
rewrite H0. rewrite H1. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (bool_prop) *)
Theorem andb_false : forall b c,
andb b c = false -> b = false \/ c = false.
Proof.
intros b c H. destruct b. simpl in H. right. apply H. left. reflexivity.
Qed.
Theorem orb_prop : forall b c,
orb b c = true -> b = true \/ c = true.
Proof.
intros b c H. destruct b. left. reflexivity. simpl in H. right. apply H.
Qed.
Theorem orb_false_elim : forall b c,
orb b c = false -> b = false /\ c = false.
Proof.
intros b c H. remember b as b'. destruct b'. simpl in H.
split.
inversion H. inversion H. simpl in H.
split. reflexivity. apply H.
Qed.
(** [] *)
(* ################################################### *)
(** * Falsehood *)
(** Logical falsehood can be represented in Coq as an inductively
defined proposition with no constructors. *)
Inductive False : Prop := .
(** Intuition: [False] is a proposition for which there is no way
to give evidence. *)
(** Since [False] has no constructors, inverting an assumption
of type [False] always yields zero subgoals, allowing us to
immediately prove any goal. *)
Theorem False_implies_nonsense :
False -> 2 + 2 = 5.
Proof.
intros contra.
inversion contra. Qed.
(** How does this work? The [inversion] tactic breaks [contra] into
each of its possible cases, and yields a subgoal for each case.
As [contra] is evidence for [False], it has _no_ possible cases,
hence, there are no possible subgoals and the proof is done. *)
(** Conversely, the only way to prove [False] is if there is already
something nonsensical or contradictory in the context: *)
Theorem nonsense_implies_False :
2 + 2 = 5 -> False.
Proof.
intros contra.
inversion contra. Qed.
(** Actually, since the proof of [False_implies_nonsense]
doesn't actually have anything to do with the specific nonsensical
thing being proved; it can easily be generalized to work for an
arbitrary [P]: *)
Theorem ex_falso_quodlibet : forall (P:Prop),
False -> P.
Proof.
(* WORKED IN CLASS *)
intros P contra.
inversion contra. Qed.
(** The Latin _ex falso quodlibet_ means, literally, "from
falsehood follows whatever you please." This theorem is also
known as the _principle of explosion_. *)
(* #################################################### *)
(** ** Truth *)
(** Since we have defined falsehood in Coq, one might wonder whether
it is possible to define truth in the same way. We can. *)
(** **** Exercise: 2 stars, advanced (True) *)
(** Define [True] as another inductively defined proposition. (The
intution is that [True] should be a proposition for which it is
trivial to give evidence.) *)
(* FILL IN HERE *)
(** [] *)
(** However, unlike [False], which we'll use extensively, [True] is
used fairly rarely. By itself, it is trivial (and therefore
uninteresting) to prove as a goal, and it carries no useful
information as a hypothesis. But it can be useful when defining
complex [Prop]s using conditionals, or as a parameter to
higher-order [Prop]s. *)
(* #################################################### *)
(** * Negation *)
(** The logical complement of a proposition [P] is written [not
P] or, for shorthand, [~P]: *)
Definition not (P:Prop) := P -> False.
(** The intuition is that, if [P] is not true, then anything at
all (even [False]) follows from assuming [P]. *)
Notation "~ x" := (not x) : type_scope.
Check not.
(* ===> Prop -> Prop *)
(** It takes a little practice to get used to working with
negation in Coq. Even though you can see perfectly well why
something is true, it can be a little hard at first to get things
into the right configuration so that Coq can see it! Here are
proofs of a few familiar facts about negation to get you warmed
up. *)
Theorem not_False :
~ False.
Proof.
unfold not. intros H. inversion H. Qed.
Theorem contradiction_implies_anything : forall P Q : Prop,
(P /\ ~P) -> Q.
Proof.
(* WORKED IN CLASS *)
intros P Q H. inversion H as [HP HNA]. unfold not in HNA.
apply HNA in HP. inversion HP. Qed.
Theorem double_neg : forall P : Prop,
P -> ~~P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not. intros G. apply G. apply H. Qed.
(** **** Exercise: 2 stars, advanced (double_neg_inf) *)
(** Write an informal proof of [double_neg]:
_Theorem_: [P] implies [~~P], for any proposition [P].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars (contrapositive) *)
Theorem contrapositive : forall P Q : Prop,
(P -> Q) -> (~Q -> ~P).
Proof.
intros P Q H1. unfold not. intros H2. intros H3. apply H2. apply H1. apply H3.
Qed.
(** [] *)
(** **** Exercise: 1 star (not_both_true_and_false) *)
Theorem not_both_true_and_false : forall P : Prop,
~ (P /\ ~P).
Proof.
intros P. unfold not. intros H. inversion H. apply H1. apply H0.
Qed.
(** [] *)
(** **** Exercise: 1 star, advanced (informal_not_PNP) *)
(** Write an informal proof (in English) of the proposition [forall P
: Prop, ~(P /\ ~P)]. *)
(* FILL IN HERE *)
(** [] *)
Theorem five_not_even :
~ ev 5.
Proof.
(* WORKED IN CLASS *)
unfold not. intros Hev5. inversion Hev5 as [|n Hev3 Heqn].
inversion Hev3 as [|n' Hev1 Heqn']. inversion Hev1. Qed.
(** **** Exercise: 1 star (ev_not_ev_S) *)
(** Theorem [five_not_even] confirms the unsurprising fact that five
is not an even number. Prove this more interesting fact: *)
Theorem ev_not_ev_S : forall n,
ev n -> ~ ev (S n).
Proof.
unfold not. intros n H. induction H.
Case "n=1". intro H. inversion H.
Case "n=Sn". intro H1. apply IHev. apply SSev__even. apply H1.
Qed.
(** [] *)
(** Note that some theorems that are true in classical logic are _not_
provable in Coq's (constructive) logic. E.g., let's look at how
this proof gets stuck... *)
Theorem classic_double_neg : forall P : Prop,
~~P -> P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not in H.
(* But now what? There is no way to "invent" evidence for [~P]
from evidence for [P]. *)
Abort.
(** **** Exercise: 5 stars, advanced, optional (classical_axioms) *)
(** For those who like a challenge, here is an exercise
taken from the Coq'Art book (p. 123). The following five
statements are often considered as characterizations of
classical logic (as opposed to constructive logic, which is
what is "built in" to Coq). We can't prove them in Coq, but
we can consistently add any one of them as an unproven axiom
if we wish to work in classical logic. Prove that these five
propositions are equivalent. *)
Definition peirce := forall P Q: Prop,
((P->Q)->P)->P.
Definition classic := forall P:Prop,
~~P -> P.
Definition excluded_middle := forall P:Prop,
P \/ ~P.
Definition de_morgan_not_and_not := forall P Q:Prop,
~(~P /\ ~Q) -> P\/Q.
Definition implies_to_or := forall P Q:Prop,
(P->Q) -> (~P\/Q).
Theorem peirce_impl_classic :
peirce -> classic.
Proof.
unfold peirce. intro H. unfold classic. intros P Hnn.
unfold not in Hnn. apply H with (Q:=False). intro contra. apply Hnn in contra. inversion contra.
Qed.
Theorem classic_impl_peirce :
classic -> peirce.
Proof.
unfold classic. unfold peirce. intro Hcl. intros P Q H. unfold not in Hcl. apply Hcl. intros H2.
apply H2 in H. inversion H. intros HP. apply H2 in HP. inversion HP.
Qed.
Theorem classic_equiv_peirce :
classic <-> peirce.
Proof.
unfold iff. split. apply classic_impl_peirce. apply peirce_impl_classic.
Qed.
Theorem peirce_impl_excl_middle :
peirce -> excluded_middle.
Proof.
unfold excluded_middle. intros Hpe P. assert classic. apply peirce_impl_classic. apply Hpe.
unfold peirce in Hpe. unfold classic in H. apply H. unfold not. intro. apply H0 in H. inversion H.
unfold not.
Admitted.
Theorem classic_impl_excluded_middle :
classic -> excluded_middle.
Proof.
intro Hclassic. unfold classic in Hclassic. unfold excluded_middle. intros P.
Admitted.
Theorem classic_impl_de_morgan :
classic -> de_morgan_not_and_not.
Proof.
intro Hcl. unfold classic in Hcl. unfold de_morgan_not_and_not.
intros P Q H. unfold not in H. unfold not in Hcl. apply Hcl. intro Hor.
Admitted.
Theorem peirce_implies_excluded_middle :
peirce -> excluded_middle.
Proof.
unfold peirce. unfold excluded_middle. intros Hprc. intros P. apply Hprc with (P:=P\/~P) (Q:=~P).
Admitted.
(* FILL IN HERE *)
(** [] *)
(* ########################################################## *)
(** ** Inequality *)
(** Saying [x <> y] is just the same as saying [~(x = y)]. *)
Notation "x <> y" := (~ (x = y)) : type_scope.
(** Since inequality involves a negation, it again requires
a little practice to be able to work with it fluently. Here
is one very useful trick. If you are trying to prove a goal
that is nonsensical (e.g., the goal state is [false = true]),
apply the lemma [ex_falso_quodlibet] to change the goal to
[False]. This makes it easier to use assumptions of the form
[~P] that are available in the context -- in particular,
assumptions of the form [x<>y]. *)
Theorem not_false_then_true : forall b : bool,
b <> false -> b = true.
Proof.
intros b H. destruct b.
Case "b = true". reflexivity.
Case "b = false".
unfold not in H.
apply ex_falso_quodlibet.
apply H. reflexivity. Qed.
(** **** Exercise: 2 stars (false_beq_nat) *)
Theorem false_beq_nat : forall n m : nat,
n <> m ->
beq_nat n m = false.
Proof.
intros n. induction n as [|n].
Case "n=0". intros m H. simpl. destruct m. unfold not in H. apply ex_falso_quodlibet. apply H. reflexivity.
reflexivity.
Case "n=Sn". intros m H. destruct m. simpl. reflexivity. simpl. apply IHn. unfold not.
intros H1. rewrite -> H1 in H. unfold not in H. apply H. reflexivity.
Qed.
(** [] *)
Lemma succ_inj : forall n m,
S n = S m -> n = m.
Proof.
intros n m H. inversion H. reflexivity.
Qed.
(** **** Exercise: 2 stars, optional (beq_nat_false) *)
Theorem beq_nat_false : forall n m,
beq_nat n m = false -> n <> m.
Proof.
intro n. induction n.
Case "n=0". intros m H. destruct m. simpl in H. inversion H. unfold not. intros H1. inversion H1.
Case "n=Sn". intros m H. destruct m. unfold not. intro H1. inversion H1. unfold not. intro H1.
simpl in H. apply IHn in H. unfold not in H. apply succ_inj in H1. apply H. apply H1.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (ble_nat_false) *)
Theorem ble_nat_false : forall n m,
ble_nat n m = false -> ~(n <= m).
Proof.
intro n. induction n.
Case "n=0". intros m H. destruct m. simpl in H. inversion H. simpl in H. inversion H.
Case "n=Sn". intros m H. destruct m. unfold not. intro H1. inversion H1. simpl in H. apply IHn in H.
unfold not. intro H1. apply Sn_le_Sm__n_le_m in H1. unfold not in H. apply H. apply H1.
Qed.
(** [] *)
(* ############################################################ *)
(** * Existential Quantification *)
(** Another critical logical connective is _existential
quantification_. We can express it with the following
definition: *)
Inductive ex (X:Type) (P : X->Prop) : Prop :=
ex_intro : forall (witness:X), P witness -> ex X P.
(** That is, [ex] is a family of propositions indexed by a type [X]
and a property [P] over [X]. In order to give evidence for the
assertion "there exists an [x] for which the property [P] holds"
we must actually name a _witness_ -- a specific value [x] -- and
then give evidence for [P x], i.e., evidence that [x] has the
property [P].
*)
(** Coq's [Notation] facility can be used to introduce more
familiar notation for writing existentially quantified
propositions, exactly parallel to the built-in syntax for
universally quantified propositions. Instead of writing [ex nat
ev] to express the proposition that there exists some number that
is even, for example, we can write [exists x:nat, ev x]. (It is
not necessary to understand exactly how the [Notation] definition
works.) *)
Notation "'exists' x , p" := (ex _ (fun x => p))
(at level 200, x ident, right associativity) : type_scope.
Notation "'exists' x : X , p" := (ex _ (fun x:X => p))
(at level 200, x ident, right associativity) : type_scope.
(** We can use the usual set of tactics for
manipulating existentials. For example, to prove an
existential, we can [apply] the constructor [ex_intro]. Since the
premise of [ex_intro] involves a variable ([witness]) that does
not appear in its conclusion, we need to explicitly give its value
when we use [apply]. *)
Example exists_example_1 : exists n, n + (n * n) = 6.
Proof.
apply ex_intro with (witness:=2).
reflexivity. Qed.
(** Note that we have to explicitly give the witness. *)
(** Or, instead of writing [apply ex_intro with (witness:=e)] all the
time, we can use the convenient shorthand [exists e], which means
the same thing. *)
Example exists_example_1' : exists n, n + (n * n) = 6.
Proof.
exists 2.
reflexivity. Qed.
(** Conversely, if we have an existential hypothesis in the
context, we can eliminate it with [inversion]. Note the use
of the [as...] pattern to name the variable that Coq
introduces to name the witness value and get evidence that
the hypothesis holds for the witness. (If we don't
explicitly choose one, Coq will just call it [witness], which
makes proofs confusing.) *)
Theorem exists_example_2 : forall n,
(exists m, n = 4 + m) ->
(exists o, n = 2 + o).
Proof.
intros n H.
inversion H as [m Hm].
exists (2 + m).
apply Hm. Qed.
(** **** Exercise: 1 star, optional (english_exists) *)
(** In English, what does the proposition
ex nat (fun n => beautiful (S n))
]]
mean? *)
(* FILL IN HERE *)
(** **** Exercise: 1 star (dist_not_exists) *)
(** Prove that "[P] holds for all [x]" implies "there is no [x] for
which [P] does not hold." *)
Theorem dist_not_exists : forall (X:Type) (P : X -> Prop),
(forall x, P x) -> ~ (exists x, ~ P x).
Proof.
intros X P H. unfold not. intro Hex. inversion Hex as [x Hx]. apply Hx. apply H.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (not_exists_dist) *)
(** (The other direction of this theorem requires the classical "law
of the excluded middle".) *)
Theorem not_exists_dist :
excluded_middle ->
forall (X:Type) (P : X -> Prop),
~ (exists x, ~ P x) -> (forall x, P x).
Proof.
unfold excluded_middle. intros Hex_mid X P Hex. intro x. unfold not in Hex.
unfold not in Hex_mid.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (dist_exists_or) *)
(** Prove that existential quantification distributes over
disjunction. *)
Theorem dist_exists_or : forall (X:Type) (P Q : X -> Prop),
(exists x, P x \/ Q x) <-> (exists x, P x) \/ (exists x, Q x).
Proof.
intros X P Q. unfold iff. split. intros H. inversion H as [x Hx].
destruct Hx. left. exists x. apply H0.
right. exists x. apply H0.
intros H. destruct H. inversion H as [x Hx]. exists x. left. apply Hx.
inversion H as [x Hx]. exists x. right. apply Hx.
Qed.
(** [] *)
(* Print dist_exists_or. *)
(* ###################################################### *)
(** * Equality *)
(** Even Coq's equality relation is not built in. It has (roughly)
the following inductive definition. *)
(* (We enclose the definition in a module to avoid confusion with the
standard library equality, which we have used extensively
already.) *)
Module MyEquality.
Inductive eq {X:Type} : X -> X -> Prop :=
refl_equal : forall x, eq x x.
(** Standard infix notation: *)
Notation "x = y" := (eq x y)
(at level 70, no associativity)
: type_scope.
(** The definition of [=] is a bit subtle. The way to think about it
is that, given a set [X], it defines a _family_ of propositions
"[x] is equal to [y]," indexed by pairs of values ([x] and [y])
from [X]. There is just one way of constructing evidence for
members of this family: applying the constructor [refl_equal] to a
type [X] and a value [x : X] yields evidence that [x] is equal to
[x]. *)
(** **** Exercise: 2 stars (leibniz_equality) *)
(** The inductive definitions of equality corresponds to _Leibniz equality_:
what we mean when we say "[x] and [y] are equal" is that every
property on [P] that is true of [x] is also true of [y]. *)
Lemma leibniz_equality : forall (X : Type) (x y: X),
x = y -> forall P : X -> Prop, P x -> P y.
Proof.
intros X x y H P HPx. destruct H. apply HPx.
Qed.
(** [] *)
(** We can use
[refl_equal] to construct evidence that, for example, [2 = 2].
Can we also use it to construct evidence that [1 + 1 = 2]? Yes:
indeed, it is the very same piece of evidence! The reason is that
Coq treats as "the same" any two terms that are _convertible_
according to a simple set of computation rules. These rules,
which are similar to those used by [Eval compute], include
evaluation of function application, inlining of definitions, and
simplification of [match]es.
*)
Lemma four: 2 + 2 = 1 + 3.
Proof.
apply refl_equal.
Qed.
(** The [reflexivity] tactic that we have used to prove equalities up
to now is essentially just short-hand for [apply refl_equal]. *)
End MyEquality.
(* ###################################################### *)
(** * Evidence-carrying booleans. *)
(** So far we've seen two different forms of equality predicates:
[eq], which produces a [Prop], and
the type-specific forms, like [beq_nat], that produce [boolean]
values. The former are more convenient to reason about, but
we've relied on the latter to let us use equality tests
in _computations_. While it is straightforward to write lemmas
(e.g. [beq_nat_true] and [beq_nat_false]) that connect the two forms,
using these lemmas quickly gets tedious.
It turns out that we can get the benefits of both forms at once
by using a construct called [sumbool]. *)
Inductive sumbool (A B : Prop) : Set :=
| left : A -> sumbool A B
| right : B -> sumbool A B.
Notation "{ A } + { B }" := (sumbool A B) : type_scope.
(** Think of [sumbool] as being like the [boolean] type, but instead
of its values being just [true] and [false], they carry _evidence_
of truth or falsity. This means that when we [destruct] them, we
are left with the relevant evidence as a hypothesis -- just as with [or].
(In fact, the definition of [sumbool] is almost the same as for [or].
The only difference is that values of [sumbool] are declared to be in
[Set] rather than in [Prop]; this is a technical distinction
that allows us to compute with them.) *)
(** Here's how we can define a [sumbool] for equality on [nat]s *)
Theorem eq_nat_dec : forall n m : nat, {n = m} + {n <> m}.
Proof.
intros n.
induction n as [|n'].
Case "n = 0".
intros m.
destruct m as [|m'].
SCase "m = 0".
left. reflexivity.
SCase "m = S m'".
right. intros contra. inversion contra.
Case "n = S n'".
intros m.
destruct m as [|m'].
SCase "m = 0".
right. intros contra. inversion contra.
SCase "m = S m'".
destruct IHn' with (m := m') as [eq | neq].
left. apply f_equal. apply eq.
right. intros Heq. inversion Heq as [Heq']. apply neq. apply Heq'.
Defined.
(** Read as a theorem, this says that equality on [nat]s is decidable:
that is, given two [nat] values, we can always produce either
evidence that they are equal or evidence that they are not.
Read computationally, [eq_nat_dec] takes two [nat] values and returns
a [sumbool] constructed with [left] if they are equal and [right]
if they are not; this result can be tested with a [match] or, better,
with an [if-then-else], just like a regular [boolean].
(Notice that we ended this proof with [Defined] rather than [Qed].
The only difference this makes is that the proof becomes _transparent_,
meaning that its definition is available when Coq tries to do reductions,
which is important for the computational interpretation.)
Here's a simple example illustrating the advantages of the [sumbool] form. *)
Definition override' {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if eq_nat_dec k k' then x else f k'.
Theorem override_same' : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override' f k1 x1) k2 = f k2.
Proof.
intros X x1 k1 k2 f. intros Hx1.
unfold override'.
destruct (eq_nat_dec k1 k2). (* observe what appears as a hypothesis *)
Case "k1 = k2".
rewrite <- e.
symmetry. apply Hx1.
Case "k1 <> k2".
reflexivity. Qed.
(** Compare this to the more laborious proof (in MoreCoq.v) for the
version of [override] defined using [beq_nat], where we had to
use the auxiliary lemma [beq_nat_true] to convert a fact about booleans
to a Prop. *)
(** **** Exercise: 1 star (override_shadow') *)
Theorem override_shadow' : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override' (override' f k1 x2) k1 x1) k2 = (override' f k1 x1) k2.
Proof.
intros X x1 x2 k1 k2 f.
unfold override'.
destruct (eq_nat_dec k1 k2).
Case "k1 = k2".
reflexivity.
Case "k1 <> k2".
reflexivity.
Qed.
(** [] *)
(* ####################################################### *)
(** ** Inversion, Again (Advanced) *)
(** We've seen [inversion] used with both equality hypotheses and
hypotheses about inductively defined propositions. Now that we've
seen that these are actually the same thing, we're in a position
to take a closer look at how [inversion] behaves...
In general, the [inversion] tactic
- takes a hypothesis [H] whose type [P] is inductively defined,
and
- for each constructor [C] in [P]'s definition,
- generates a new subgoal in which we assume [H] was
built with [C],
- adds the arguments (premises) of [C] to the context of
the subgoal as extra hypotheses,
- matches the conclusion (result type) of [C] against the
current goal and calculates a set of equalities that must
hold in order for [C] to be applicable,
- adds these equalities to the context (and, for convenience,
rewrites them in the goal), and
- if the equalities are not satisfiable (e.g., they involve
things like [S n = O]), immediately solves the subgoal. *)
(** _Example_: If we invert a hypothesis built with [or], there are two
constructors, so two subgoals get generated. The
conclusion (result type) of the constructor ([P \/ Q]) doesn't
place any restrictions on the form of [P] or [Q], so we don't get
any extra equalities in the context of the subgoal.
_Example_: If we invert a hypothesis built with [and], there is
only one constructor, so only one subgoal gets generated. Again,
the conclusion (result type) of the constructor ([P /\ Q]) doesn't
place any restrictions on the form of [P] or [Q], so we don't get
any extra equalities in the context of the subgoal. The
constructor does have two arguments, though, and these can be seen
in the context in the subgoal.
_Example_: If we invert a hypothesis built with [eq], there is
again only one constructor, so only one subgoal gets generated.
Now, though, the form of the [refl_equal] constructor does give us
some extra information: it tells us that the two arguments to [eq]
must be the same! The [inversion] tactic adds this fact to the
context. *)
(** **** Exercise: 1 star, optional (dist_and_or_eq_implies_and) *)
Lemma dist_and_or_eq_implies_and : forall P Q R,
P /\ (Q \/ R) /\ Q = R -> P/\Q.
Proof.
intros P Q R H. inversion H. inversion H1. rewrite <- H3 in H2.
apply conj. apply H0. inversion H2. apply H4. apply H4.
Qed.
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (all_forallb) *)
(** Inductively define a property [all] of lists, parameterized by a
type [X] and a property [P : X -> Prop], such that [all X P l]
asserts that [P] is true for every element of the list [l]. *)
Inductive all (X : Type) (P : X -> Prop) : list X -> Prop :=
| all_empty : all X P []
| all_cons : forall (x:X) (l:list X), P x -> all X P l -> all X P (x::l).
(** Recall the function [forallb], from the exercise
[forall_exists_challenge] in chapter [Poly]: *)
Fixpoint forallb {X : Type} (test : X -> bool) (l : list X) : bool :=
match l with
| [] => true
| x :: l' => andb (test x) (forallb test l')
end.
(** Using the property [all], write down a specification for [forallb],
and prove that it satisfies the specification. Try to make your
specification as precise as possible.
Are there any important properties of the function [forallb] which
are not captured by your specification?
Not as far as I can tell.
*)
Theorem forallb_spec : forall (X:Type) (test : X -> bool) (l : list X),
all X (fun x => test x = true) l <-> forallb test l = true.
Proof.
intros X test l. split.
Case "=>".
intros H. induction H.
SCase "l=[]". simpl. reflexivity.
SCase "l=h::t". simpl. rewrite -> H. simpl. apply IHall.
Case "<=".
intros H. induction l as [|h t].
SCase "l=[]". apply all_empty.
SCase "l=h::t".
apply all_cons. simpl in H. apply andb_true_elim1 in H. apply H.
apply IHt. apply andb_true_elim2 in H. apply H.
Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced (filter_challenge) *)
(** One of the main purposes of Coq is to prove that programs match
their specifications. To this end, let's prove that our
definition of [filter] matches a specification. Here is the
specification, written out informally in English.
Suppose we have a set [X], a function [test: X->bool], and a list
[l] of type [list X]. Suppose further that [l] is an "in-order
merge" of two lists, [l1] and [l2], such that every item in [l1]
satisfies [test] and no item in [l2] satisfies test. Then [filter
test l = l1].
A list [l] is an "in-order merge" of [l1] and [l2] if it contains
all the same elements as [l1] and [l2], in the same order as [l1]
and [l2], but possibly interleaved. For example,
[1,4,6,2,3]
is an in-order merge of
[1,6,2]
and
[4,3].
Your job is to translate this specification into a Coq theorem and
prove it. (Hint: You'll need to begin by defining what it means
for one list to be a merge of two others. Do this with an
inductive relation, not a [Fixpoint].) *)
Inductive in_order_merge {X : Type} : list X -> list X -> list X -> Prop :=
| iom_nil : in_order_merge [] [] []
| iom_cons_left : forall (x:X) (l l1 l2 : list X), in_order_merge l l1 l2 -> in_order_merge (x::l) (x::l1) l2
| iom_cons_right : forall (x:X) (l l1 l2 : list X), in_order_merge l l1 l2 -> in_order_merge (x::l) l1 (x::l2).
Example in_order_merge_test : in_order_merge [1;2;3;4;5;6] [1;3;5] [2;4;6].
Proof.
apply iom_cons_left. apply iom_cons_right. apply iom_cons_left. apply iom_cons_right.
apply iom_cons_left. apply iom_cons_right. apply iom_nil.
Qed.
Theorem filter_spec : forall (X:Type) (test : X -> bool) (l l1 l2 : list X),
all X (fun x => test x = true) l1 -> all X (fun x => test x = false) l2 -> in_order_merge l l1 l2 -> filter test l = l1.
Proof.
intros X test l l1 l2 H1 H2 H3. induction H3.
Case "l=[]". simpl. reflexivity.
Case "iom_cons_left". inversion H1. simpl. rewrite -> H4. assert (filter test l = l1).
apply IHin_order_merge. apply H5. apply H2. rewrite -> H6. reflexivity.
Case "iom_cons_right". inversion H2. simpl. rewrite -> H4. apply IHin_order_merge. apply H1. apply H5.
Qed.
(** [] *)
(** **** Exercise: 5 stars, advanced, optional (filter_challenge_2) *)
(** A different way to formally characterize the behavior of [filter]
goes like this: Among all subsequences of [l] with the property
that [test] evaluates to [true] on all their members, [filter test
l] is the longest. Express this claim formally and prove it. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, advanced (no_repeats) *)
(** The following inductively defined proposition... *)
Inductive appears_in {X:Type} (a:X) : list X -> Prop :=
| ai_here : forall l, appears_in a (a::l)
| ai_later : forall b l, appears_in a l -> appears_in a (b::l).
(** ...gives us a precise way of saying that a value [a] appears at
least once as a member of a list [l].
Here's a pair of warm-ups about [appears_in].
*)
Lemma appears_in_app : forall (X:Type) (xs ys : list X) (x:X),
appears_in x (xs ++ ys) -> appears_in x xs \/ appears_in x ys.
Proof.
intros X xs ys x. induction xs as [|h t].
Case "xs=[]". intro H. simpl in H. right. apply H.
Case "xs=h::t". intro H. simpl in H. inversion H.
SCase "ai_here". left. apply ai_here. apply IHt in H1. destruct H1. left. apply ai_later. apply H1. right. apply H1.
Qed.
Lemma app_appears_in : forall (X:Type) (xs ys : list X) (x:X),
appears_in x xs \/ appears_in x ys -> appears_in x (xs ++ ys).
Proof.
intros X xs ys x. induction xs as [|h t].
Case "xs=[]". intro H. destruct H. inversion H. simpl. apply H.
Case "xs=h::t". intro H. destruct H. inversion H. apply ai_here. simpl. apply ai_later. apply IHt. left. apply H1.
simpl. apply ai_later. apply IHt. right. apply H.
Qed.
(** Now use [appears_in] to define a proposition [disjoint X l1 l2],
which should be provable exactly when [l1] and [l2] are
lists (with elements of type X) that have no elements in common. *)
Inductive disjoint {X:Type} : list X -> list X -> Prop :=
| disj_empty : disjoint [] []
| disj_cons_left : forall x l1 l2, disjoint l1 l2 -> not (appears_in x l2) -> disjoint (x::l1) l2
| disj_cons_right : forall x l1 l2, disjoint l1 l2 -> not (appears_in x l1) -> disjoint l1 (x::l2).
(** Next, use [appears_in] to define an inductive proposition
[no_repeats X l], which should be provable exactly when [l] is a
list (with elements of type [X]) where every member is different
from every other. For example, [no_repeats nat [1,2,3,4]] and
[no_repeats bool []] should be provable, while [no_repeats nat
[1,2,1]] and [no_repeats bool [true,true]] should not be. *)
Inductive no_repeats {X:Type} : list X -> Prop :=
| nr_empty : no_repeats []
| nr_cons : forall x l, no_repeats l -> not (appears_in x l) -> no_repeats (x::l).
Theorem not_or_distributes : forall P Q : Prop,
(~P /\ ~Q) <-> ~(P \/ Q).
Proof.
intros P Q. split.
Case "->". intro H. inversion H. unfold not. intros H2. inversion H2. apply H0. apply H3. apply H1. apply H3.
Case "<-". intro H.
split.
unfold not. intro HP. unfold not in H. apply H. left. apply HP.
unfold not. intro HQ. unfold not in H. apply H. right. apply HQ.
Qed.
(** Finally, state and prove one or more interesting theorems relating
[disjoint], [no_repeats] and [++] (list append). *)
Lemma not_in_sublist : forall (X:Type) (x:X) (xs ys : list X),
~ appears_in x (xs++ys) -> ~ appears_in x xs /\ ~ appears_in x ys.
Proof.
intros X x xs ys H.
apply not_or_distributes. unfold not. intro H1. apply app_appears_in in H1. apply H. apply H1.
Qed.
Theorem no_repeats__impl__disjoint : forall (X:Type) (l xs ys : list X),
no_repeats l -> l = xs ++ ys -> disjoint xs ys.
Proof.
intros X l xs ys Hnr. generalize xs ys. clear xs ys.
induction Hnr as [|h t].
Case "nr_empty". intros xs ys H.
destruct xs. destruct ys. apply disj_empty.
simpl in H. inversion H.
simpl in H. inversion H.
Case "l1=h::t". intros xs ys H1.
destruct xs. destruct ys. apply disj_empty. apply disj_cons_right. apply IHHnr. simpl in H1. inversion H1. simpl. reflexivity.
unfold not. intro. inversion H0.
simpl in H1. inversion H1. apply disj_cons_left. apply IHHnr. apply H3.
rewrite <- H2. rewrite -> H3 in H. apply not_in_sublist in H. inversion H. apply H4.
Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (nostutter) *)
(** Formulating inductive definitions of predicates is an important
skill you'll need in this course. Try to solve this exercise
without any help at all (except from your study group partner, if
you have one).
We say that a list of numbers "stutters" if it repeats the same
number consecutively. The predicate "[nostutter mylist]" means
that [mylist] does not stutter. Formulate an inductive definition
for [nostutter]. (This is different from the [no_repeats]
predicate in the exercise above; the sequence [1,4,1] repeats but
does not stutter.) *)
Inductive nostutter: list nat -> Prop :=
| ns_nil : nostutter []
| ns_one : forall x, nostutter [x]
| ns_cons : forall x h t, nostutter (h::t) -> beq_nat x h = false -> nostutter (x::h::t).
(** Make sure each of these tests succeeds, but you are free
to change the proof if the given one doesn't work for you.
Your definition might be different from mine and still correct,
in which case the examples might need a different proof.
The suggested proofs for the examples (in comments) use a number
of tactics we haven't talked about, to try to make them robust
with respect to different possible ways of defining [nostutter].
You should be able to just uncomment and use them as-is, but if
you prefer you can also prove each example with more basic
tactics. *)
Example test_nostutter_1: nostutter [3;1;4;1;5;6].
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
Example test_nostutter_2: nostutter [].
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
Example test_nostutter_3: nostutter [5].
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
Example test_nostutter_4: not (nostutter [3;1;1;4]).
Proof. intro.
repeat match goal with
h: nostutter _ |- _ => inversion h; clear h; subst
end.
simpl in H5. inversion H5.
Qed.
(* FILL IN HERE *)
(*
Proof. intro.
repeat match goal with
h: nostutter _ |- _ => inversion h; clear h; subst
end.
contradiction H1; auto. Qed.
*)
(** [] *)
(** **** Exercise: 4 stars, advanced (pigeonhole principle) *)
(** The "pigeonhole principle" states a basic fact about counting:
if you distribute more than [n] items into [n] pigeonholes, some
pigeonhole must contain at least two items. As is often the case,
this apparently trivial fact about numbers requires non-trivial
machinery to prove, but we now have enough... *)
(** First a pair of useful lemmas (we already proved these for lists
of naturals, but not for arbitrary lists). *)
Lemma succ_inj2 : forall (n m:nat),
n = m -> S n = S m.
Proof.
intros n m H. rewrite -> H. reflexivity.
Qed.
Lemma app_length : forall (X:Type) (l1 l2 : list X),
length (l1 ++ l2) = length l1 + length l2.
Proof.
intros X l1 l2. remember (l1++l2) as l. generalize l1 l2 Heql. clear l1 l2 Heql. induction l as [|h t].
Case "l=[]". intros l1 l2 H. destruct l1. destruct l2. simpl. reflexivity. simpl in H. inversion H.
simpl in H. inversion H.
Case "l=h::t". intros l1 l2 H. destruct l1. destruct l2. simpl in H. inversion H. simpl. simpl in H. inversion H. reflexivity.
simpl in H. inversion H. simpl. apply succ_inj2. rewrite <- H2. apply IHt. apply H2.
Qed.
Lemma appears_in_app_split : forall (X:Type) (x:X) (l:list X),
appears_in x l ->
exists l1, exists l2, l = l1 ++ (x::l2).
Proof.
intros.
induction H as [t|h t].
Case "[]". exists []. exists t. simpl. reflexivity.
Case "h::t". inversion IHappears_in as [l1]. inversion H0 as [l2]. exists (h::l1). exists l2. rewrite -> H1.
simpl. reflexivity.
Qed.
(** Now define a predicate [repeats] (analogous to [no_repeats] in the
exercise above), such that [repeats X l] asserts that [l] contains
at least one repeated element (of type [X]). *)
Inductive repeats {X:Type} : list X -> Prop :=
| repeats_here : forall (x:X) (l : list X), appears_in x l -> repeats (x::l)
| repeats_later : forall (x:X) (l : list X), repeats l -> repeats (x::l).
(*
Inductive ex (X:Type) (P : X->Prop) : Prop :=
ex_intro : forall (witness:X), P witness -> ex X P.
*)
(** Now here's a way to formalize the pigeonhole principle. List [l2]
represents a list of pigeonhole labels, and list [l1] represents an
assignment of items to labels: if there are more items than labels,
at least two items must have the same label. You will almost
certainly need to use the [excluded_middle] hypothesis. *)
Lemma appears_in_subl : forall (X:Type) (x y:X) (xs : list X),
x <> y -> appears_in x (y::xs) -> appears_in x xs.
Proof.
intros. inversion H0. apply H in H2. inversion H2. apply H2.
Qed.
Lemma app_nil_right : forall (X:Type) (l : list X),
l ++ [] = l.
Proof.
intros. induction l as [|h t].
simpl. reflexivity. simpl. rewrite -> IHt. reflexivity.
Qed.
Lemma unapp : forall (X:Type) (x:X) (l1 l2 : list X),
x :: l1 ++ l2 = (x::l1) ++ l2.
Proof.
intros. simpl. reflexivity.
Qed.
Lemma appears_in_reorder : forall (X:Type) (x:X) (l1 l2 : list X),
appears_in x (l1++l2) -> appears_in x (l2++l1).
Proof.
intros X x l1. induction l1 as [|h t].
Case "l=[]". intros. simpl in H. rewrite -> app_nil_right. apply H.
Case "l=h::t". intros. simpl in H. apply app_appears_in.
rewrite -> unapp in H. apply appears_in_app in H.
inversion H. right. apply H0. left. apply H0.
Qed.
Theorem pigeonhole_principle: forall (X:Type) (l1 l2:list X),
excluded_middle ->
(forall y, appears_in y l1 -> appears_in y l2) ->
length l2 < length l1 ->
repeats l1.
Proof. intros X l1. induction l1 as [|h t].
Case "l1=[]". intros. destruct l2. simpl in H1. inversion H1. simpl in H1. inversion H1.
Case "l1=h::t". intros. assert (appears_in h t \/ ~ appears_in h t). apply H.
inversion H2. clear H2. apply repeats_here. apply H3. apply repeats_later. clear H2.
(* proof idea: there exists a reordering of l2 such that l2 = h :: t2 *)
assert (appears_in h l2). apply H0. apply ai_here.
apply appears_in_app_split with (x:=h) in H2. inversion H2 as [l21]. inversion H4 as [l22].
clear H2. clear H4.
(* *)
assert (forall y:X, y <> h -> appears_in y t -> appears_in y (l21++l22)).
intros. apply ai_later with (b:=h) in H4. apply H0 in H4. rewrite -> H5 in H4.
apply appears_in_reorder in H4. simpl in H4. apply appears_in_subl in H4.
apply appears_in_reorder in H4. apply H4. apply H2.
(* now appy IH *)
apply IHt with (l2:=l21++l22). apply H. intros.
assert (y <> h). intro. rewrite -> H6 in H4. apply H3. apply H4.
apply H2. apply H6. apply H4.
(* length (l21 ++ l22) < length t *)
rewrite -> H5 in H1. rewrite -> app_length with (l1:=l21) (l2:=h::l22) in H1. simpl in H1.
rewrite -> plus_comm in H1. simpl in H1. rewrite -> plus_comm in H1.
rewrite <- app_length in H1. apply Sn_le_Sm__n_le_m in H1. apply H1.
Qed.
(** [] *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: scdata.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
/////////////////////////////////////////////////////
//`include "sys.h"
//`include "iop.h"
module scdata (/*AUTOARG*/
// Outputs
scdata_sctag_decc_c6,
scdata_scbuf_decc_out_c7, scdata_efc_fuse_data, so,
// Inputs
sctag_scdata_word_en_c2, sctag_scdata_way_sel_c2,
sctag_scdata_stdecc_c2, sctag_scdata_set_c2,
sctag_scdata_rd_wr_c2, sctag_scdata_fbrd_c3,
sctag_scdata_fb_hit_c3, sctag_scdata_col_offset_c2,
scbuf_scdata_fbdecc_c4, efc_scdata_fuse_dshift,
efc_scdata_fuse_data, efc_scdata_fuse_clk2, efc_scdata_fuse_clk1,
efc_scdata_fuse_ashift, cmp_gclk, global_shift_enable, si, arst_l,
grst_l, cluster_cken, ctu_tst_pre_grst_l, ctu_tst_scanmode,
ctu_tst_scan_disable, ctu_tst_macrotest, ctu_tst_short_chain
);
input [1:0] cmp_gclk; // To data of bw_r_l2d.v
input global_shift_enable; // To data of bw_r_l2d.v
input si; // To data of bw_r_l2d.v
input arst_l, grst_l;
input cluster_cken;
input ctu_tst_pre_grst_l;
input ctu_tst_scanmode;
input ctu_tst_scan_disable;
input ctu_tst_macrotest;
input ctu_tst_short_chain;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input efc_scdata_fuse_ashift; // To efuse_hdr of scdata_efuse_hdr.v
input efc_scdata_fuse_clk1; // To efuse_hdr of scdata_efuse_hdr.v, ...
input efc_scdata_fuse_clk2; // To efuse_hdr of scdata_efuse_hdr.v, ...
input efc_scdata_fuse_data; // To efuse_hdr of scdata_efuse_hdr.v
input efc_scdata_fuse_dshift; // To efuse_hdr of scdata_efuse_hdr.v
input [623:0] scbuf_scdata_fbdecc_c4; // To periph_io of scdata_periph_io.v
input [3:0] sctag_scdata_col_offset_c2;// To rep of scdata_rep.v
input sctag_scdata_fb_hit_c3; // To rep of scdata_rep.v
input sctag_scdata_fbrd_c3; // To rep of scdata_rep.v
input sctag_scdata_rd_wr_c2; // To rep of scdata_rep.v
input [9:0] sctag_scdata_set_c2; // To rep of scdata_rep.v
input [77:0] sctag_scdata_stdecc_c2; // To rep of scdata_rep.v
input [11:0] sctag_scdata_way_sel_c2;// To rep of scdata_rep.v
input [15:0] sctag_scdata_word_en_c2;// To rep of scdata_rep.v
// End of automatics
output so;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output scdata_efc_fuse_data; // From efuse_hdr of scdata_efuse_hdr.v
output [623:0] scdata_scbuf_decc_out_c7;// From periph_io of scdata_periph_io.v
output [155:0] scdata_sctag_decc_c6; // From rep of scdata_rep.v
// End of automatics
wire tm_l;
wire so_subbank_3;
wire so_clk_hdr;
wire so_efuse_hdr;
wire so_subbank_0;
wire mem_write_disable;
wire se_buf;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] cache_col_offset_c3; // From ctr of scdata_ctr_io.v
wire [623:0] cache_decc_in_c3; // From ctr of scdata_ctr_io.v
wire [623:0] cache_decc_out_c5; // From subbank_0 of scdata_subbank.v, ...
wire [9:0] cache_set_c3_0; // From ctr of scdata_ctr_io.v
wire [9:0] cache_set_c3_1; // From ctr of scdata_ctr_io.v
wire [9:0] cache_set_c3_2; // From ctr of scdata_ctr_io.v
wire [9:0] cache_set_c3_3; // From ctr of scdata_ctr_io.v
wire [11:0] cache_way_sel_c3_0; // From ctr of scdata_ctr_io.v
wire [11:0] cache_way_sel_c3_1; // From ctr of scdata_ctr_io.v
wire [11:0] cache_way_sel_c3_2; // From ctr of scdata_ctr_io.v
wire [11:0] cache_way_sel_c3_3; // From ctr of scdata_ctr_io.v
wire [15:0] cache_word_en_c3; // From ctr of scdata_ctr_io.v
wire cache_wr_en_c3_0; // From ctr of scdata_ctr_io.v
wire cache_wr_en_c3_1; // From ctr of scdata_ctr_io.v
wire cache_wr_en_c3_2; // From ctr of scdata_ctr_io.v
wire cache_wr_en_c3_3; // From ctr of scdata_ctr_io.v
wire fuse_red_data; // From efuse_hdr of scdata_efuse_hdr.v
wire [2:0] fuse_red_rid; // From efuse_hdr of scdata_efuse_hdr.v
wire [5:0] fuse_red_subbank0_dshift;// From efuse_hdr of scdata_efuse_hdr.v
wire fuse_red_read_shift;// From efuse_hdr of scdata_efuse_hdr.v
wire [5:0] fuse_red_subbank1_dshift;// From efuse_hdr of scdata_efuse_hdr.v
wire [5:0] fuse_red_subbank2_dshift;// From efuse_hdr of scdata_efuse_hdr.v
wire [5:0] fuse_red_subbank3_dshift;// From efuse_hdr of scdata_efuse_hdr.v
wire red_fuse_data; // From subbank_2 of scdata_subbank.v
wire red_fuse_data_0; // From subbank_0 of scdata_subbank.v
wire red_fuse_data_1; // From subbank_1 of scdata_subbank.v
wire red_fuse_data_3; // From subbank_3 of scdata_subbank.v
wire [623:0] scbuf_scdata_fbdecc_c5; // From periph_io of scdata_periph_io.v
wire [623:0] scbuf_scdata_fbdecc_c5_buf;// From subbank_1 of scdata_subbank.v, ...
wire [623:0] scdata_decc_out_c6; // From ctr of scdata_ctr_io.v
wire [623:0] scdata_scbuf_decc_c6_buf;// From subbank_1 of scdata_subbank.v, ...
wire [155:0] scdata_sctag_decc_c6_ctr;// From ctr of scdata_ctr_io.v
wire [3:0] sctag_scdata_col_offset_c2_buf;// From rep of scdata_rep.v
wire sctag_scdata_fb_hit_c3_buf;// From rep of scdata_rep.v
wire sctag_scdata_fbrd_c3_buf;// From rep of scdata_rep.v
wire sctag_scdata_rd_wr_c2_buf;// From rep of scdata_rep.v
wire [9:0] sctag_scdata_set_c2_buf;// From rep of scdata_rep.v
wire [77:0] sctag_scdata_stdecc_c2_buf;// From rep of scdata_rep.v
wire [11:0] sctag_scdata_way_sel_c2_buf;// From rep of scdata_rep.v
wire [15:0] sctag_scdata_word_en_c2_buf;// From rep of scdata_rep.v
wire so_ctr_io; // From ctr of scdata_ctr_io.v
wire so_periph_io; // From periph_io of scdata_periph_io.v
wire so_subbank_1; // From subbank_1 of scdata_subbank.v
wire so_subbank_2; // From subbank_2 of scdata_subbank.v
// End of automatics
wire rclk;
wire se;
wire sehold;
bw_clk_cl_scdata_cmp header(.cluster_grst_l(),
.gclk(cmp_gclk),
.se(global_shift_enable),
.si(so_subbank_3),
.so(so_clk_hdr),
.rclk(rclk),
.dbginit_l (),
.cluster_cken (cluster_cken),
.arst_l (arst_l),
.arst2_l (arst_l),
.grst_l (grst_l),
.adbginit_l (1'b1),
.gdbginit_l (1'b0));
test_stub_scan tstub
(// Outputs
.mux_drive_disable (mem_write_disable),
.mem_write_disable (),
.sehold (sehold),
.se (se),
.testmode_l (tm_l),
.mem_bypass (),
.so_0 (so),
.so_1 (),
.so_2 (),
// Inputs
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.arst_l (1'b1),
.global_shift_enable (global_shift_enable),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_short_chain (ctu_tst_short_chain),
.long_chain_so_0 (so_efuse_hdr),
.short_chain_so_0 (1'b0),
.long_chain_so_1 (1'b0),
.short_chain_so_1 (1'b0),
.long_chain_so_2 (1'b0),
.short_chain_so_2 (1'b0)
);
scdata_rep rep(/*AUTOINST*/
// Outputs
.sctag_scdata_col_offset_c2_buf(sctag_scdata_col_offset_c2_buf[3:0]),
.sctag_scdata_fb_hit_c3_buf(sctag_scdata_fb_hit_c3_buf),
.sctag_scdata_fbrd_c3_buf(sctag_scdata_fbrd_c3_buf),
.sctag_scdata_rd_wr_c2_buf(sctag_scdata_rd_wr_c2_buf),
.sctag_scdata_set_c2_buf(sctag_scdata_set_c2_buf[9:0]),
.sctag_scdata_stdecc_c2_buf(sctag_scdata_stdecc_c2_buf[77:0]),
.sctag_scdata_way_sel_c2_buf(sctag_scdata_way_sel_c2_buf[11:0]),
.sctag_scdata_word_en_c2_buf(sctag_scdata_word_en_c2_buf[15:0]),
.scdata_sctag_decc_c6 (scdata_sctag_decc_c6[155:0]),
// Inputs
.sctag_scdata_col_offset_c2(sctag_scdata_col_offset_c2[3:0]),
.sctag_scdata_fb_hit_c3(sctag_scdata_fb_hit_c3),
.sctag_scdata_fbrd_c3 (sctag_scdata_fbrd_c3),
.sctag_scdata_rd_wr_c2(sctag_scdata_rd_wr_c2),
.sctag_scdata_set_c2 (sctag_scdata_set_c2[9:0]),
.sctag_scdata_stdecc_c2(sctag_scdata_stdecc_c2[77:0]),
.sctag_scdata_way_sel_c2(sctag_scdata_way_sel_c2[11:0]),
.sctag_scdata_word_en_c2(sctag_scdata_word_en_c2[15:0]),
.scdata_sctag_decc_c6_ctr(scdata_sctag_decc_c6_ctr[155:0]));
scdata_ctr_io ctr(
// Inputs
.scbuf_scdata_fbdecc_c5(scbuf_scdata_fbdecc_c5_buf[623:0]),
.se (se),
.si (so_subbank_1),
// Outputs
.so (so_ctr_io),
/*AUTOINST*/
// Outputs
.scdata_sctag_decc_c6_ctr(scdata_sctag_decc_c6_ctr[155:0]),
.scdata_decc_out_c6(scdata_decc_out_c6[623:0]),
.cache_decc_in_c3 (cache_decc_in_c3[623:0]),
.cache_col_offset_c3(cache_col_offset_c3[3:0]),
.cache_word_en_c3 (cache_word_en_c3[15:0]),
.cache_way_sel_c3_0(cache_way_sel_c3_0[11:0]),
.cache_set_c3_0 (cache_set_c3_0[9:0]),
.cache_wr_en_c3_0 (cache_wr_en_c3_0),
.cache_way_sel_c3_1(cache_way_sel_c3_1[11:0]),
.cache_set_c3_1 (cache_set_c3_1[9:0]),
.cache_wr_en_c3_1 (cache_wr_en_c3_1),
.cache_way_sel_c3_2(cache_way_sel_c3_2[11:0]),
.cache_set_c3_2 (cache_set_c3_2[9:0]),
.cache_wr_en_c3_2 (cache_wr_en_c3_2),
.cache_way_sel_c3_3(cache_way_sel_c3_3[11:0]),
.cache_set_c3_3 (cache_set_c3_3[9:0]),
.cache_wr_en_c3_3 (cache_wr_en_c3_3),
// Inputs
.sctag_scdata_way_sel_c2_buf(sctag_scdata_way_sel_c2_buf[11:0]),
.sctag_scdata_rd_wr_c2_buf(sctag_scdata_rd_wr_c2_buf),
.sctag_scdata_set_c2_buf(sctag_scdata_set_c2_buf[9:0]),
.sctag_scdata_col_offset_c2_buf(sctag_scdata_col_offset_c2_buf[3:0]),
.sctag_scdata_word_en_c2_buf(sctag_scdata_word_en_c2_buf[15:0]),
.sctag_scdata_fbrd_c3_buf(sctag_scdata_fbrd_c3_buf),
.sctag_scdata_fb_hit_c3_buf(sctag_scdata_fb_hit_c3_buf),
.sctag_scdata_stdecc_c2_buf(sctag_scdata_stdecc_c2_buf[77:0]),
.cache_decc_out_c5 (cache_decc_out_c5[623:0]),
.rclk (rclk));
scdata_periph_io periph_io(
// Inputs
.scdata_decc_out_c6(scdata_scbuf_decc_c6_buf[623:0]),
.se (se_buf),
.si (si),
// Outputs
.so (so_periph_io),
/*AUTOINST*/
// Outputs
.scdata_scbuf_decc_out_c7(scdata_scbuf_decc_out_c7[623:0]),
.scbuf_scdata_fbdecc_c5(scbuf_scdata_fbdecc_c5[623:0]),
// Inputs
.scbuf_scdata_fbdecc_c4(scbuf_scdata_fbdecc_c4[623:0]),
.rclk (rclk));
scdata_efuse_hdr efuse_hdr(
.si (so_subbank_0),
.so (so_efuse_hdr),
.testmode_l(tm_l),
/*AUTOINST*/
// Outputs
.scdata_efc_fuse_data(scdata_efc_fuse_data),
.fuse_red_data(fuse_red_data),
.fuse_red_subbank0_dshift(fuse_red_subbank0_dshift[5:0]),
.fuse_red_subbank1_dshift(fuse_red_subbank1_dshift[5:0]),
.fuse_red_subbank2_dshift(fuse_red_subbank2_dshift[5:0]),
.fuse_red_subbank3_dshift(fuse_red_subbank3_dshift[5:0]),
.fuse_red_read_shift(fuse_red_read_shift),
.fuse_red_rid(fuse_red_rid[2:0]),
// Inputs
.rclk (rclk),
.se (se),
.efc_scdata_fuse_clk1(efc_scdata_fuse_clk1),
.efc_scdata_fuse_clk2(efc_scdata_fuse_clk2),
.efc_scdata_fuse_ashift(efc_scdata_fuse_ashift),
.efc_scdata_fuse_dshift(efc_scdata_fuse_dshift),
.efc_scdata_fuse_data(efc_scdata_fuse_data),
.red_fuse_data(red_fuse_data),
.arst_l (arst_l));
/*scdata_subbank AUTO_TEMPLATE(
.decc_out (cache_decc_out_c5[@"(+ 155 (* 156 @))":@"(* 156 @)"]),
// Inputs
.col_offset (cache_col_offset_c3[@]),
.decc_in (cache_decc_in_c3[@"(+ 155 (* 156 @))":@"(* 156 @)"]),
.set (cache_set_c3_@[9:0]),
.way_sel (cache_way_sel_c3_@[11:0]),
.word_en (cache_word_en_c3[@"(+ 3 (* @ 4))":@"(* @ 4)"]),
.wr_en (cache_wr_en_c3_@),
.fuse_l2d_wren (fuse_red_subbank@_dshift[5:0]),
.fuse_l2d_rden (fuse_red_read_shift),
.fuse_l2d_rid (fuse_red_rid[2:0]),
.fuse_l2d_data_in (fuse_red_data),
.l2d_fuse_data_out (red_fuse_data_@));
*/
scdata_subbank subbank_0(
// Outputs
.scbuf_scdata_fbdecc_bot_buf(),
.scbuf_scdata_fbdecc_top_buf(),
.scdata_scbuf_decc_c6_bot_buf(),
.scdata_scbuf_decc_c6_top_buf(),
.so (so_subbank_0),
.se_buf(),
// Inputs
.fuse_read_data_in(red_fuse_data_1),
.scbuf_scdata_fbdecc_bot(156'b0),
.scbuf_scdata_fbdecc_top(156'b0),
.scdata_scbuf_decc_bot(156'b0),
.scdata_scbuf_decc_top(156'b0),
.se (se),
.si (so_subbank_2),
/*AUTOINST*/
// Outputs
.decc_out (cache_decc_out_c5[155:0]), // Templated
.l2d_fuse_data_out(red_fuse_data_0), // Templated
// Inputs
.way_sel (cache_way_sel_c3_0[11:0]), // Templated
.arst_l (arst_l),
.col_offset(cache_col_offset_c3[0]), // Templated
.decc_in (cache_decc_in_c3[155:0]), // Templated
.efc_scdata_fuse_clk1(efc_scdata_fuse_clk1),
.efc_scdata_fuse_clk2(efc_scdata_fuse_clk2),
.fuse_l2d_data_in(fuse_red_data), // Templated
.fuse_l2d_rden(fuse_red_read_shift), // Templated
.fuse_l2d_rid(fuse_red_rid[2:0]), // Templated
.fuse_l2d_wren(fuse_red_subbank0_dshift[5:0]), // Templated
.mem_write_disable(mem_write_disable),
.rclk (rclk),
.sehold (sehold),
.set (cache_set_c3_0[9:0]), // Templated
.word_en (cache_word_en_c3[3:0]), // Templated
.wr_en (cache_wr_en_c3_0)); // Templated
scdata_subbank subbank_1(
// Outputs
.scbuf_scdata_fbdecc_top_buf(scbuf_scdata_fbdecc_c5_buf[311:156]),
.scbuf_scdata_fbdecc_bot_buf(scbuf_scdata_fbdecc_c5_buf[155:0]),
.scdata_scbuf_decc_c6_top_buf(scdata_scbuf_decc_c6_buf[311:156]),
.scdata_scbuf_decc_c6_bot_buf(scdata_scbuf_decc_c6_buf[155:0]),
.so (so_subbank_1),
.se_buf(),
// Inputs
.fuse_read_data_in(red_fuse_data_3),
.scbuf_scdata_fbdecc_top(scbuf_scdata_fbdecc_c5[311:156]),
.scbuf_scdata_fbdecc_bot(scbuf_scdata_fbdecc_c5[155:0]),
.scdata_scbuf_decc_top(scdata_decc_out_c6[311:156]),
.scdata_scbuf_decc_bot(scdata_decc_out_c6[155:0]),
.se (se),
.si (so_clk_hdr),
/*AUTOINST*/
// Outputs
.decc_out (cache_decc_out_c5[311:156]), // Templated
.l2d_fuse_data_out(red_fuse_data_1), // Templated
// Inputs
.way_sel (cache_way_sel_c3_1[11:0]), // Templated
.arst_l (arst_l),
.col_offset(cache_col_offset_c3[1]), // Templated
.decc_in (cache_decc_in_c3[311:156]), // Templated
.efc_scdata_fuse_clk1(efc_scdata_fuse_clk1),
.efc_scdata_fuse_clk2(efc_scdata_fuse_clk2),
.fuse_l2d_data_in(fuse_red_data), // Templated
.fuse_l2d_rden(fuse_red_read_shift), // Templated
.fuse_l2d_rid(fuse_red_rid[2:0]), // Templated
.fuse_l2d_wren(fuse_red_subbank1_dshift[5:0]), // Templated
.mem_write_disable(mem_write_disable),
.rclk (rclk),
.sehold (sehold),
.set (cache_set_c3_1[9:0]), // Templated
.word_en (cache_word_en_c3[7:4]), // Templated
.wr_en (cache_wr_en_c3_1)); // Templated
scdata_subbank subbank_2(
// Outputs
.scbuf_scdata_fbdecc_bot_buf(),
.scbuf_scdata_fbdecc_top_buf(),
.scdata_scbuf_decc_c6_bot_buf(),
.scdata_scbuf_decc_c6_top_buf(),
.so (so_subbank_2),
.se_buf(),
.l2d_fuse_data_out (red_fuse_data),
// Inputs
.fuse_read_data_in(red_fuse_data_0),
.scbuf_scdata_fbdecc_bot(156'b0),
.scbuf_scdata_fbdecc_top(156'b0),
.scdata_scbuf_decc_bot(156'b0),
.scdata_scbuf_decc_top(156'b0),
.se (se),
.si (so_ctr_io),
/*AUTOINST*/
// Outputs
.decc_out (cache_decc_out_c5[467:312]), // Templated
// Inputs
.way_sel (cache_way_sel_c3_2[11:0]), // Templated
.arst_l (arst_l),
.col_offset(cache_col_offset_c3[2]), // Templated
.decc_in (cache_decc_in_c3[467:312]), // Templated
.efc_scdata_fuse_clk1(efc_scdata_fuse_clk1),
.efc_scdata_fuse_clk2(efc_scdata_fuse_clk2),
.fuse_l2d_data_in(fuse_red_data), // Templated
.fuse_l2d_rden(fuse_red_read_shift), // Templated
.fuse_l2d_rid(fuse_red_rid[2:0]), // Templated
.fuse_l2d_wren(fuse_red_subbank2_dshift[5:0]), // Templated
.mem_write_disable(mem_write_disable),
.rclk (rclk),
.sehold (sehold),
.set (cache_set_c3_2[9:0]), // Templated
.word_en (cache_word_en_c3[11:8]), // Templated
.wr_en (cache_wr_en_c3_2)); // Templated
scdata_subbank subbank_3(
// Outputs
.scbuf_scdata_fbdecc_top_buf(scbuf_scdata_fbdecc_c5_buf[623:468]),
.scbuf_scdata_fbdecc_bot_buf(scbuf_scdata_fbdecc_c5_buf[467:312]),
.scdata_scbuf_decc_c6_top_buf(scdata_scbuf_decc_c6_buf[623:468]),
.scdata_scbuf_decc_c6_bot_buf(scdata_scbuf_decc_c6_buf[467:312]),
.so (so_subbank_3),
.se_buf(se_buf),
// Inputs
.fuse_read_data_in(1'b0),
.scbuf_scdata_fbdecc_top(scbuf_scdata_fbdecc_c5[623:468]),
.scbuf_scdata_fbdecc_bot(scbuf_scdata_fbdecc_c5[467:312]),
.scdata_scbuf_decc_top(scdata_decc_out_c6[623:468]),
.scdata_scbuf_decc_bot(scdata_decc_out_c6[467:312]),
.se (se),
.si (so_periph_io),
/*AUTOINST*/
// Outputs
.decc_out (cache_decc_out_c5[623:468]), // Templated
.l2d_fuse_data_out(red_fuse_data_3), // Templated
// Inputs
.way_sel (cache_way_sel_c3_3[11:0]), // Templated
.arst_l (arst_l),
.col_offset(cache_col_offset_c3[3]), // Templated
.decc_in (cache_decc_in_c3[623:468]), // Templated
.efc_scdata_fuse_clk1(efc_scdata_fuse_clk1),
.efc_scdata_fuse_clk2(efc_scdata_fuse_clk2),
.fuse_l2d_data_in(fuse_red_data), // Templated
.fuse_l2d_rden(fuse_red_read_shift), // Templated
.fuse_l2d_rid(fuse_red_rid[2:0]), // Templated
.fuse_l2d_wren(fuse_red_subbank3_dshift[5:0]), // Templated
.mem_write_disable(mem_write_disable),
.rclk (rclk),
.sehold (sehold),
.set (cache_set_c3_3[9:0]), // Templated
.word_en (cache_word_en_c3[15:12]), // Templated
.wr_en (cache_wr_en_c3_3)); // Templated
// synopsys translate_off
// for monitor, MSS, and debug
// breaking scdata_scbuf_decc_out_c7 into data and ecc
wire [511:0] scdata_scbuf_data_out_c7;
wire [111:0] scdata_scbuf_ecc_out_c7;
assign { scdata_scbuf_data_out_c7[31:0], scdata_scbuf_ecc_out_c7[6:0] } = scdata_scbuf_decc_out_c7[38:0];
assign { scdata_scbuf_data_out_c7[63:32], scdata_scbuf_ecc_out_c7[13:7] } = scdata_scbuf_decc_out_c7[77:39];
assign { scdata_scbuf_data_out_c7[95:64], scdata_scbuf_ecc_out_c7[20:14] } = scdata_scbuf_decc_out_c7[116:78];
assign { scdata_scbuf_data_out_c7[127:96], scdata_scbuf_ecc_out_c7[27:21] } = scdata_scbuf_decc_out_c7[155:117];
assign { scdata_scbuf_data_out_c7[159:128], scdata_scbuf_ecc_out_c7[34:28] } = scdata_scbuf_decc_out_c7[194:156];
assign { scdata_scbuf_data_out_c7[191:160], scdata_scbuf_ecc_out_c7[41:35] } = scdata_scbuf_decc_out_c7[233:195];
assign { scdata_scbuf_data_out_c7[223:192], scdata_scbuf_ecc_out_c7[48:42] } = scdata_scbuf_decc_out_c7[272:234];
assign { scdata_scbuf_data_out_c7[255:224], scdata_scbuf_ecc_out_c7[55:49] } = scdata_scbuf_decc_out_c7[311:273];
assign { scdata_scbuf_data_out_c7[287:256], scdata_scbuf_ecc_out_c7[62:56] } = scdata_scbuf_decc_out_c7[350:312];
assign { scdata_scbuf_data_out_c7[319:288], scdata_scbuf_ecc_out_c7[69:63] } = scdata_scbuf_decc_out_c7[389:351];
assign { scdata_scbuf_data_out_c7[351:320], scdata_scbuf_ecc_out_c7[76:70] } = scdata_scbuf_decc_out_c7[428:390];
assign { scdata_scbuf_data_out_c7[383:352], scdata_scbuf_ecc_out_c7[83:77] } = scdata_scbuf_decc_out_c7[467:429];
assign { scdata_scbuf_data_out_c7[415:384], scdata_scbuf_ecc_out_c7[90:84] } = scdata_scbuf_decc_out_c7[506:468];
assign { scdata_scbuf_data_out_c7[447:416], scdata_scbuf_ecc_out_c7[97:91] } = scdata_scbuf_decc_out_c7[545:507];
assign { scdata_scbuf_data_out_c7[479:448], scdata_scbuf_ecc_out_c7[104:98] } = scdata_scbuf_decc_out_c7[584:546];
assign { scdata_scbuf_data_out_c7[511:480], scdata_scbuf_ecc_out_c7[111:105] } = scdata_scbuf_decc_out_c7[623:585];
// breaking cache_decc_out_c5 into data and ecc
wire [511:0] cache_data_out_c5;
wire [111:0] cache_ecc_out_c5;
assign { cache_data_out_c5[31:0], cache_ecc_out_c5[6:0] } = cache_decc_out_c5[38:0];
assign { cache_data_out_c5[63:32], cache_ecc_out_c5[13:7] } = cache_decc_out_c5[77:39];
assign { cache_data_out_c5[95:64], cache_ecc_out_c5[20:14] } = cache_decc_out_c5[116:78];
assign { cache_data_out_c5[127:96], cache_ecc_out_c5[27:21] } = cache_decc_out_c5[155:117];
assign { cache_data_out_c5[159:128], cache_ecc_out_c5[34:28] } = cache_decc_out_c5[194:156];
assign { cache_data_out_c5[191:160], cache_ecc_out_c5[41:35] } = cache_decc_out_c5[233:195];
assign { cache_data_out_c5[223:192], cache_ecc_out_c5[48:42] } = cache_decc_out_c5[272:234];
assign { cache_data_out_c5[255:224], cache_ecc_out_c5[55:49] } = cache_decc_out_c5[311:273];
assign { cache_data_out_c5[287:256], cache_ecc_out_c5[62:56] } = cache_decc_out_c5[350:312];
assign { cache_data_out_c5[319:288], cache_ecc_out_c5[69:63] } = cache_decc_out_c5[389:351];
assign { cache_data_out_c5[351:320], cache_ecc_out_c5[76:70] } = cache_decc_out_c5[428:390];
assign { cache_data_out_c5[383:352], cache_ecc_out_c5[83:77] } = cache_decc_out_c5[467:429];
assign { cache_data_out_c5[415:384], cache_ecc_out_c5[90:84] } = cache_decc_out_c5[506:468];
assign { cache_data_out_c5[447:416], cache_ecc_out_c5[97:91] } = cache_decc_out_c5[545:507];
assign { cache_data_out_c5[479:448], cache_ecc_out_c5[104:98] } = cache_decc_out_c5[584:546];
assign { cache_data_out_c5[511:480], cache_ecc_out_c5[111:105] } = cache_decc_out_c5[623:585];
// Stagin cache_data/ecc out
reg cache_acc_en_c3, cache_acc_en_c4;
reg cache_wr_en_c4;
reg [9:0] cache_set_c4;
reg [3:0] cache_col_offset_c4;
reg [15:0] cache_word_en_c4;
reg [11:0] cache_way_sel_c4;
reg [3:0] col_offset_c3;
always @(posedge rclk) begin
// Access enable is a 16b OR of way selects.
cache_acc_en_c3 <= |(sctag_scdata_way_sel_c2);
cache_acc_en_c4 <= cache_acc_en_c3 ;
cache_wr_en_c4 <= cache_wr_en_c3_0;
cache_set_c4 <= cache_set_c3_0;
col_offset_c3 <= sctag_scdata_col_offset_c2[3:0];
cache_col_offset_c4 <= cache_col_offset_c3;
cache_word_en_c4 <= cache_word_en_c3;
cache_way_sel_c4 <= cache_way_sel_c3_0;
end
// Checkers
always @(cache_acc_en_c3 or cache_acc_en_c4
or col_offset_c3 or cache_col_offset_c4) begin
if( cache_acc_en_c3 & ~|( col_offset_c3) ) begin
`ifdef MODELSIM
$display( "SCDATA", " column Offset Should not be zero%h", col_offset_c3 );
`else
$error( "SCDATA", " column Offset Should not be zero%h", col_offset_c3 );
`endif
end
if( cache_acc_en_c3 & cache_acc_en_c4 & (|( col_offset_c3 & cache_col_offset_c4)) ) begin
`ifdef MODELSIM
$display( "SCDATA", "Illegal back to back accesses c3_col=%b c4_col=%b ",
col_offset_c3, cache_col_offset_c4 );
`else
$error( "SCDATA", "Illegal back to back accesses c3_col=%b c4_col=%b ",
col_offset_c3, cache_col_offset_c4 );
`endif
end
end
always @(posedge rclk) begin
if (arst_l & grst_l) begin
case(sctag_scdata_way_sel_c2)
12'b000000000000: ;
12'b000000000001: ;
12'b000000000010: ;
12'b000000000100: ;
12'b000000001000: ;
12'b000000010000: ;
12'b000000100000: ;
12'b000001000000: ;
12'b000010000000: ;
12'b000100000000: ;
12'b001000000000: ;
12'b010000000000: ;
12'b100000000000: ;
default:
`ifdef MODELSIM
$display("L2_DATA_ERR"," way select error %h ", sctag_scdata_way_sel_c2[11:0]);
`else
$error("L2_DATA_ERR"," way select error %h ", sctag_scdata_way_sel_c2[11:0]);
`endif
endcase
end // if (arst_l & grst_l)
end // always @ (posedge rclk)
// synopsys translate_on
endmodule // scdata
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_PP_BLACKBOX_V
/**
* sleep_pargate_plv: ????.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sleep_pargate_plv (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_PP_BLACKBOX_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module uart #(
//parameter csr_addr = 4'h0,
parameter clk_freq = 100000000,
parameter baud = 115200
) (
//cpu_read_write
//wb_input
input [31:0] dat_i,
input [31:0] adr_i,
input we_i,
input stb_i,
//wb_output
output reg [31:0] dat_o,
output ack_o,
input sys_clk,
input sys_rst,
output rx_irq,
output tx_irq,
input uart_rx,
output uart_tx,
input rx_iack
);
reg [15:0] divisor;
wire [7:0] rx_data;
wire [7:0] tx_data;
wire tx_wr;
wire rx_done, tx_done;
wire tx_busy;
wire full_rx, full_tx, empty_rx, empty_tx;
reg thru = 0;
wire uart_tx_transceiver;
wire [7:0] rx_data_out;
reg fifo_rx_wr = 0;
wire fifo_rx_rd;
reg fifo_rd_once = 0;
wire [7:0] tx_data_out;
wire fifo_tx_rd;
reg tran_tx_wr = 0;
reg fifo_tx_rd_once = 0;
reg tmp2 = 0;
reg fifo_tx_to_tran = 0;
reg fifo_busy;
wire uart_wr;
uart_transceiver transceiver(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.uart_rx(uart_rx),
.uart_tx(uart_tx_transceiver),
.divisor(divisor),
.rx_data(rx_data),
.rx_done(rx_done),
.tx_data(tx_data_out),
.tx_wr(fifo_tx_to_tran),
.tx_done(tx_done),
.tx_busy(tx_busy),
.rx_busy(rx_busy)
);
always @(posedge sys_clk) begin
if(rx_done) fifo_rx_wr = 1;
else fifo_rx_wr = 0;
end
assign fifo_rx_rd = rx_wr & ~fifo_rd_once;
always @(posedge sys_clk) begin
if(rx_wr) fifo_rd_once = 1;
else fifo_rd_once = 0;
end
assign rx_irq = full_rx & ~rx_iack;
uart_fifo fifo_rx (
.clk(sys_clk), // input clk
.rst(sys_rst), // input rst
.din(rx_data), // input [7 : 0] din
.wr_en(fifo_rx_wr), // input wr_en
.rd_en(fifo_rx_rd), // input rd_en
.dout(rx_data_out), // output [7 : 0] dout
.full(full_rx), // output full
.empty(empty_rx), // output empty
.data_count() // output [7 : 0] data_count
);
always @(posedge sys_clk) begin
if(tran_tx_wr && !fifo_tx_rd_once && !tmp2) begin
fifo_tx_rd_once = 1;
tmp2 = 1;
end
else if(tmp2 && fifo_tx_rd_once) begin fifo_tx_rd_once = 0;end
else if(!tran_tx_wr) begin tmp2 = 0;end
end
always @(posedge sys_clk) begin
if(tmp2 && !fifo_tx_rd_once) fifo_tx_to_tran = 1;
else fifo_tx_to_tran = 0;
end
assign fifo_tx_rd = ~tx_busy & ~empty_tx;
always @(posedge sys_clk) begin
tran_tx_wr = fifo_tx_rd;
end
always @(posedge sys_clk) begin
if(tx_wr) fifo_busy = 1;
else fifo_busy = 0;
end
//assign tx_irq = full_tx;
uart_fifo fifo_tx (
.clk(sys_clk), // input clk
.rst(sys_rst), // input rst
.din(tx_data), // input [7 : 0] din
.wr_en(tx_wr & ~fifo_busy), // input wr_en
.rd_en(fifo_tx_rd_once/*fifo_tx_rd*/), // input rd_en
.dout(tx_data_out), // output [7 : 0] dout
.full(full_tx), // output full
.empty(empty_tx), // output empty
.data_count() // output [7 : 0] data_count
);
assign uart_tx = thru ? uart_rx : uart_tx_transceiver;
/* CSR interface */
//wire csr_selected = csr_a[13:10] == csr_addr;
assign tx_data = dat_i[7:0];
//assign tx_wr = csr_selected & csr_we & (csr_a[1:0] == 2'b00);
assign tx_wr = stb_i & ack_o & we_i & (adr_i[1:0] == 2'b00);
assign rx_wr = stb_i & ack_o & ~we_i & (adr_i[1:0] == 2'b00) & ~empty_rx;
parameter default_divisor = clk_freq/baud/16;
assign ack_o = stb_i & (we_i?~full_tx:1) ;//& ((we_i&~full_tx) | (~we_i&~empty_rx));
assign uart_wr = stb_i && ack_o;
always @(posedge sys_clk or posedge sys_rst) begin
if(sys_rst) begin
divisor <= default_divisor;
dat_o <= 32'd0;
end else if(uart_wr) begin
dat_o <= 32'd0;
case(adr_i[1:0])
2'b00: if(rx_wr) begin dat_o <= {23'h0, 1'b1, rx_data_out}; end
2'b01: dat_o <= divisor;
2'b10: dat_o <= thru;
endcase
if(we_i/*csr_we*/) begin
case(adr_i[1:0])
2'b00:; /* handled by transceiver */
2'b01: divisor <= dat_i[15:0];
2'b10: thru <= dat_i[0];
endcase
end
end
end
//always @(posedge sys_clk) begin
// if(sys_rst) begin
// divisor <= default_divisor;
// dat_o <= 32'd0;
// end else begin
// dat_o <= 32'd0;
// if(stb_i && ack_o/*csr_selected*/) begin
// case(adr_i[1:0])
// 2'b00: dat_o <= rx_data;
// 2'b01: dat_o <= divisor;
// 2'b10: dat_o <= thru;
// endcase
// if(we_i/*csr_we*/) begin
// case(adr_i[1:0])
// 2'b00:; /* handled by transceiver */
// 2'b01: divisor <= dat_i[15:0];
// 2'b10: thru <= dat_i[0];
// endcase
// end
// end
// end
//end
endmodule
|
/******************************************************************************/
/* Test Bench for FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
`include "user_logic.v"
`include "sorter.v"
/******************************************************************************/
module tb_USER_LOGIC();
reg CLK, RST;
wire chnl_rx_clk;
wire chnl_rx;
wire chnl_rx_ack;
wire chnl_rx_last;
wire [31:0] chnl_rx_len;
wire [30:0] chnl_rx_off;
wire [128-1:0] chnl_rx_data;
wire chnl_rx_data_valid;
wire chnl_rx_data_ren;
wire chnl_tx_clk;
wire chnl_tx;
wire chnl_tx_ack;
wire chnl_tx_last;
wire [31:0] chnl_tx_len;
wire [30:0] chnl_tx_off;
wire [128-1:0] chnl_tx_data;
wire chnl_tx_data_vaild;
wire chnl_tx_data_ren = 1;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
reg sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7, cnt8, cnt9;
always @(posedge CLK) cnt0 <= (RST) ? 0 : (u.core.phase==0) ? cnt0 + 1 : cnt0;
always @(posedge CLK) cnt1 <= (RST) ? 0 : (u.core.phase==1) ? cnt1 + 1 : cnt1;
always @(posedge CLK) cnt2 <= (RST) ? 0 : (u.core.phase==2) ? cnt2 + 1 : cnt2;
always @(posedge CLK) cnt3 <= (RST) ? 0 : (u.core.phase==3) ? cnt3 + 1 : cnt3;
always @(posedge CLK) cnt4 <= (RST) ? 0 : (u.core.phase==4) ? cnt4 + 1 : cnt4;
always @(posedge CLK) cnt5 <= (RST) ? 0 : (u.core.phase==5) ? cnt5 + 1 : cnt5;
always @(posedge CLK) cnt6 <= (RST) ? 0 : (u.core.phase==6) ? cnt6 + 1 : cnt6;
always @(posedge CLK) cnt7 <= (RST) ? 0 : (u.core.phase==7) ? cnt7 + 1 : cnt7;
always @(posedge CLK) cnt8 <= (RST) ? 0 : (u.core.phase==8) ? cnt8 + 1 : cnt8;
always @(posedge CLK) cnt9 <= (RST) ? 0 : (u.core.phase==9) ? cnt9 + 1 : cnt9;
reg [31:0] rslt_cnt;
always @(posedge CLK) begin
if (RST) begin
rslt_cnt <= 0;
end else begin
if (chnl_tx_data_vaild) rslt_cnt <= rslt_cnt + 4;
end
end
always @(posedge CLK) begin
if (RST) sortdone <= 0;
else if (rslt_cnt == `SORT_ELM) sortdone <= 1;
end
// Debug Info
always @(posedge CLK) begin
if (!RST) begin
$write("%d|%d|P%d|%d%d%d|%d", cnt[19:0], u.core.elem, u.core.phase[2:0], u.core.iter_done, u.core.pchange, u.core.irst, u.core.ecnt);
$write("|");
if (d_douten) $write("%08x %08x ", d_dout[63:32], d_dout[31:0]); else $write(" ");
// $write("%d %d %x ", u.rState, u.rx_wait, u.core.req_pzero);
// if (u.idata_valid) $write("%08x %08x ", u.idata[63:32], u.idata[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_t) $write("%08x %08x ", u.core.dout_t[63:32], u.core.dout_t[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_tc) $write("%08x %08x ", u.core.dout_tc[63:32], u.core.dout_tc[31:0]); else $write(" ");
$write("|");
$write("[%d](%d)", u.core.req, u.core.state);
$write("| %d %d %d %d %d %d %d %d|",
u.core.im00.imf.cnt, u.core.im01.imf.cnt, u.core.im02.imf.cnt, u.core.im03.imf.cnt,
u.core.im04.imf.cnt, u.core.im05.imf.cnt, u.core.im06.imf.cnt, u.core.im07.imf.cnt);
// $write("| %d %d %d %d %d %d %d %d|",
// u.core.im00.im_deq, u.core.im01.im_deq, u.core.im02.im_deq, u.core.im03.im_deq,
// u.core.im04.im_deq, u.core.im05.im_deq, u.core.im06.im_deq, u.core.im07.im_deq);
$write(" ");
if (u.core.F01_deq) $write("%08x %08x %08x %08x ", u.core.F01_dot[127:96], u.core.F01_dot[95:64], u.core.F01_dot[63:32], u.core.F01_dot[31:0]); else $write(" ");
// $write("| ");
// $write("%d", u.core.dcnt);
if (d.app_wdf_wren) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
// checking the result
generate
if (`INITTYPE=="sorted" || `INITTYPE=="reverse") begin
reg [`MERGW-1:0] check_cnt;
always @(posedge CLK) begin
if (RST) begin
check_cnt[31 : 0] <= 1;
check_cnt[63 :32] <= 2;
check_cnt[95 :64] <= 3;
check_cnt[127:96] <= 4;
end else begin
if (chnl_tx_data_vaild) begin
if (check_cnt != chnl_tx_data) begin
$write("Error in sorter.v: %d %d\n", chnl_tx_data, check_cnt); // for simulation
$finish(); // for simulation
end
check_cnt[31 : 0] <= check_cnt[31 : 0] + 4;
check_cnt[63 :32] <= check_cnt[63 :32] + 4;
check_cnt[95 :64] <= check_cnt[95 :64] + 4;
check_cnt[127:96] <= check_cnt[127:96] + 4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
integer fp;
initial begin fp = $fopen("log.txt", "w"); end
always @(posedge CLK) begin
if (chnl_tx_data_vaild) begin
$fwrite(fp, "%08x\n", chnl_tx_data[31:0]);
$fwrite(fp, "%08x\n", chnl_tx_data[63:32]);
$fwrite(fp, "%08x\n", chnl_tx_data[95:64]);
$fwrite(fp, "%08x\n", chnl_tx_data[127:96]);
$fflush();
end
if (sortdone) $fclose(fp);
end
end else begin
always @(posedge CLK) begin
$write("Error! INITTYPE is wrong.\n");
$write("Please make sure src/define.vh\n");
$finish();
end
end
endgenerate
// Show the elapsed cycles
always @(posedge CLK) begin
if(sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("phase0: %d cycles\n", cnt0);
$write("phase1: %d cycles\n", cnt1);
$write("phase2: %d cycles\n", cnt2);
$write("phase3: %d cycles\n", cnt3);
$write("phase4: %d cycles\n", cnt4);
$write("phase5: %d cycles\n", cnt5);
$write("phase6: %d cycles\n", cnt6);
$write("phase7: %d cycles\n", cnt7);
$write("phase8: %d cycles\n", cnt8);
$write("phase9: %d cycles\n", cnt9);
$write("Sorting finished!\n");
$finish();
end
end
// Stub modules
/**********************************************************************************************/
Host_to_FPGA h2f(CLK, RST, chnl_rx_data_ren, chnl_rx, chnl_rx_data, chnl_rx_data_valid, chnl_rx_len);
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
/***** Core Module Instantiation *****/
/**********************************************************************************************/
USER_LOGIC u(CLK,
RST,
chnl_rx_clk,
chnl_rx,
chnl_rx_ack,
chnl_rx_last,
chnl_rx_len,
chnl_rx_off,
chnl_rx_data,
chnl_rx_data_valid,
chnl_rx_data_ren,
chnl_tx_clk,
chnl_tx,
chnl_tx_ack,
chnl_tx_last,
chnl_tx_len,
chnl_tx_off,
chnl_tx_data,
chnl_tx_data_vaild,
chnl_tx_data_ren,
d_busy, // DRAM busy
d_din, // DRAM data in
d_w, // DRAM write flag
d_dout, // DRAM data out
d_douten, // DRAM data out enable
d_req, // DRAM REQ access request (read/write)
d_initadr, // DRAM REQ initial address for the access
d_blocks // DRAM REQ the number of blocks per one access
);
endmodule
/**************************************************************************************************/
/***** Xorshift *****/
/**************************************************************************************************/
module XORSHIFT #(parameter WIDTH = 32,
parameter SEED = 1)
(input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t = x^(x<<11);
// Mask MSB for not generating the maximum value
assign RAND_VAL = {1'b0, w[WIDTH-2:0]};
reg ocen;
always @(posedge CLK) ocen <= RST;
always @(posedge CLK) begin
if (RST) begin
x <= 123456789;
y <= 362436069;
z <= 521288629;
w <= 88675123 ^ SEED;
end else begin
if (EN || ocen) begin
x <= y;
y <= z;
z <= w;
w <= (w^(w>>19))^(t^(t>>8));
end
end
end
endmodule
/**************************************************************************************************/
module Host_to_FPGA(input wire CLK,
input wire RST,
input wire ren,
output reg chnl_rx,
output wire [`MERGW-1:0] dot,
output wire doten,
output wire [31:0] length);
reg rst_buf; always @(posedge CLK) rst_buf <= RST;
wire enq;
wire deq;
wire [`MERGW-1:0] din;
wire emp;
wire ful;
wire [4:0] cnt;
reg [`SORTW-1:0] i_d,i_c,i_b,i_a;
reg onetime;
reg [31:0] enqcnt;
reg enqstop;
wire [`SORTW-1:0] r15,r14,r13,r12,r11,r10,r09,r08,r07,r06,r05,r04,r03,r02,r01,r00;
reg [1:0] selector;
wire [`MERGW-1:0] din_xorshift = (selector == 0) ? {r03,r02,r01,r00} :
(selector == 1) ? {r07,r06,r05,r04} :
(selector == 2) ? {r11,r10,r09,r08} :
(selector == 3) ? {r15,r14,r13,r12} : 0;
SRL_FIFO #(4, `MERGW) fifo(CLK, rst_buf, enq, deq, din, dot, emp, ful, cnt);
assign enq = (!enqstop && !ful);
assign deq = (ren && !emp);
assign din = (`INITTYPE=="xorshift") ? din_xorshift : {i_d,i_c,i_b,i_a};
assign doten = deq;
assign length = `SORT_ELM;
always @(posedge CLK) begin
if (rst_buf) begin
chnl_rx <= 0;
onetime <= 1;
end else begin
chnl_rx <= onetime;
onetime <= 0;
end
end
always @(posedge CLK) begin
if (rst_buf) enqcnt <= 0;
else if (enq) enqcnt <= enqcnt + 4;
end
always @(posedge CLK) begin
if (rst_buf) enqstop <= 0;
else if (enq && (enqcnt == `SORT_ELM-4)) enqstop <= 1;
end
always @(posedge CLK) begin
if (rst_buf) selector <= 0;
else if (enq) selector <= selector + 1;
end
generate
if (`INITTYPE=="sorted") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= 1;
i_b <= 2;
i_c <= 3;
i_d <= 4;
end else begin
if (enq) begin
i_a <= i_a+4;
i_b <= i_b+4;
i_c <= i_c+4;
i_d <= i_d+4;
end
end
end
end else if (`INITTYPE=="reverse") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= `SORT_ELM;
i_b <= `SORT_ELM-1;
i_c <= `SORT_ELM-2;
i_d <= `SORT_ELM-3;
end else begin
if (enq) begin
i_a <= i_a-4;
i_b <= i_b-4;
i_c <= i_c-4;
i_d <= i_d-4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
XORSHIFT #(`SORTW, 32'h00000001) xorshift00(CLK, RST, (enq && selector == 0), r00);
XORSHIFT #(`SORTW, 32'h00000002) xorshift01(CLK, RST, (enq && selector == 0), r01);
XORSHIFT #(`SORTW, 32'h00000004) xorshift02(CLK, RST, (enq && selector == 0), r02);
XORSHIFT #(`SORTW, 32'h00000008) xorshift03(CLK, RST, (enq && selector == 0), r03);
XORSHIFT #(`SORTW, 32'h00000010) xorshift04(CLK, RST, (enq && selector == 1), r04);
XORSHIFT #(`SORTW, 32'h00000020) xorshift05(CLK, RST, (enq && selector == 1), r05);
XORSHIFT #(`SORTW, 32'h00000040) xorshift06(CLK, RST, (enq && selector == 1), r06);
XORSHIFT #(`SORTW, 32'h00000080) xorshift07(CLK, RST, (enq && selector == 1), r07);
XORSHIFT #(`SORTW, 32'h00000100) xorshift08(CLK, RST, (enq && selector == 2), r08);
XORSHIFT #(`SORTW, 32'h00000200) xorshift09(CLK, RST, (enq && selector == 2), r09);
XORSHIFT #(`SORTW, 32'h00000400) xorshift10(CLK, RST, (enq && selector == 2), r10);
XORSHIFT #(`SORTW, 32'h00000800) xorshift11(CLK, RST, (enq && selector == 2), r11);
XORSHIFT #(`SORTW, 32'h00001000) xorshift12(CLK, RST, (enq && selector == 3), r12);
XORSHIFT #(`SORTW, 32'h00002000) xorshift13(CLK, RST, (enq && selector == 3), r13);
XORSHIFT #(`SORTW, 32'h00004000) xorshift14(CLK, RST, (enq && selector == 3), r14);
XORSHIFT #(`SORTW, 32'h00008000) xorshift15(CLK, RST, (enq && selector == 3), r15);
end
endgenerate
endmodule
/**************************************************************************************************/
module DRAM(input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
/**************************************************************************************************/
`default_nettype wire
|
`include "config.v"
module A2S_controller(
// system reset
rst,
// stream clk
Sclk,
// system sync(reset)
sync,
// Buffer read
Oen,
Oaddr,
obase,
osize,
oacnt,
obcnt,
// AXI Bus Signal
AXI_clk,
AXI_rst_n,
AXI_araddr,
AXI_arvalid,
AXI_arready,
AXI_rready,
AXI_rvalid,
AXI_rlast,
// Buffer write
a2s_addr,
a2s_en
);
parameter s0 = 3'd0;
parameter s1 = 3'd1;
parameter s2 = 3'd2;
parameter s3 = 3'd3;
input rst,Sclk,sync,Oen;
output[4:0] Oaddr;
input AXI_clk;
input AXI_rst_n;
output reg[31:0] AXI_araddr;
input AXI_arready,AXI_rvalid;
output reg AXI_rready,AXI_arvalid;
input AXI_rlast;
output reg[4:0] a2s_addr;
output a2s_en;
reg[21:0] cnt;
reg[31:0] bcnt;
reg start;
wire axi_start;
reg [2:0]state;
reg [31:0]AXI_araddr_reg;
input [31:0]obase;
input [23:6]osize;
output [23:6]oacnt;
output [31:0]obcnt;
assign Oaddr = cnt[4:0];
assign oacnt[23:6] = cnt[21:4];
assign obcnt = bcnt;
edgesync #(.e("pos")) start_sync
( .clk(AXI_clk)
, .async(start)
, .sync(axi_start)
);
always @(posedge Sclk or posedge rst)
begin
if( rst==1'b1 ) begin
start <= 1'b0;
cnt <= 22'h0;
bcnt <= 32'h0;
end
else begin
if ( sync==1'b1 )
begin
start <= 1'b0;
cnt <= 22'h0;
bcnt <= 32'h0;
end
else if( Oen==1'b1 )
begin
if( cnt[3:0]==4'hf )
begin
AXI_araddr_reg[5:0] <= 6'b000000;
AXI_araddr_reg[31:6] <= obase[31:6] + cnt[21:4];
cnt[3:0] <= 4'h0;
if( cnt[21:4]==(osize[23:6]-1'b1) )
begin
cnt[21:4] <= 18'h0;
bcnt <= bcnt + 32'h1;
end
else cnt[21:4] <= cnt[21:4]+18'h1;
end
else cnt[3:0] <= cnt[3:0] + 4'h1;
end
if( Oen==1'b1 && cnt[3:0]==4'hf && start==1'b0 ) start <= 1'b1;
else start <= 1'b0;
end
end
assign a2s_en = AXI_rvalid & AXI_rready;
always @(posedge AXI_clk)
begin
if( !AXI_rst_n ) begin
a2s_addr <= 5'b00000;
AXI_arvalid <= 1'b0;
AXI_rready <= 1'b0;
AXI_araddr <= obase;
state <= s0;
end
else begin
if( axi_start==1'b1 ) begin
state <= s1;
AXI_araddr <= AXI_araddr_reg;
end
else begin
case( state )
s0 : begin
AXI_rready <= AXI_rvalid;
end
s1 : begin
AXI_arvalid <= 1'b1;
if( AXI_arready==1'b1 && AXI_arvalid==1'b1 ) begin
state <= s2;
AXI_arvalid <= 1'b0;
a2s_addr[4] <= AXI_araddr[6];
a2s_addr[3:0] <= 4'h0;
AXI_rready <= 1'b1;
end
end
s2 : begin
if( a2s_en==1'b1 ) begin
a2s_addr[3:0] <= a2s_addr[3:0] + 1'b1;
if( AXI_rlast==1'b1 ) begin
state <= s0;
AXI_rready <= 1'b0;
end
end
end
endcase
end
end
end
endmodule
|
`default_nettype none
`timescale 1ns / 1ps
module cls_spi(
input wire clock,
input wire reset,
input wire [15:0] A,
input wire [7:0] Di,
input wire [7:0] Do,
input wire [15:0] PC,
input wire [15:0] SP,
input wire [15:0] AF,
input wire [15:0] BC,
input wire [15:0] DE,
input wire [15:0] HL,
input wire [15:0] joypad_state,
input wire [1:0] mode,
output wire ss,
output reg mosi,
input wire miso,
output wire sclk
);
parameter WAIT = 1;
parameter SEND = 2;
parameter SEND_2 = 3;
parameter SEND_3 = 4;
parameter SEND_4 = 5;
parameter SEND_5 = 6;
parameter SENDHEX = 7;
parameter SENDJOYPAD = 8;
parameter STARTUP_1 = 10;
parameter STARTUP_2 = 11;
parameter STARTUP_3 = 12;
parameter STARTUP_4 = 13;
parameter LOOP_1 = 20;
parameter LOOP_2 = 21;
parameter LOOP_3 = 22;
parameter LOOP_4 = 23;
parameter LOOP_5 = 24;
parameter LOOP_6 = 25;
parameter LOOP_7 = 26;
parameter LOOP_8 = 27;
parameter LOOP_9 = 28;
parameter LOOP_10 = 29;
parameter LOOP_11 = 30;
parameter LOOP_7b = 31;
parameter LOOP_8b = 32;
reg [63:0] send_buf; // send buffer (8 bytes)
reg [2:0] send_idx; // current bit (0h-7h)
reg [2:0] send_ctr; // current byte (0h-7h)
reg [2:0] send_max; // total bytes (0h-7h)
reg [31:0] wait_ctr; // current cycle
reg [31:0] wait_max; // total cycles
reg [2:0] hex_idx; // current word
reg [3:0] btn_idx; // current joypad button
reg [1:0] mode_latch; // 0-PCSP, 1-AFBC, 2-DEHL
// TODO probably don't need 7 bits for state
reg [7:0] state;
reg [7:0] next_state;
reg [7:0] next_state_hex;
reg [7:0] next_state_btn;
reg ss_enable;
reg sclk_enable;
reg [7:0] glyph_rom [15:0];
reg [31:0] data;
reg [1:0] data_idx;
initial begin
$readmemh("data/hexascii.hex", glyph_rom, 0, 15);
end
always @(posedge clock) begin
// RESET
if (reset) begin
send_buf <= 64'b0;
send_idx <= 3'b0;
send_ctr <= 3'b0;
send_max <= 3'b0;
wait_ctr <= 32'b0;
wait_max <= 32'b0;
state <= STARTUP_1;
next_state <= 8'b0;
next_state_hex <= 8'b0;
next_state_btn <= 8'b0;
mode_latch <= 2'b0;
hex_idx <= 3'b0;
btn_idx <= 4'b0;
data <= 32'b0;
data_idx <= 2'b0;
ss_enable <= 0;
sclk_enable <= 0;
mosi <= 1'b0;
end
// STATES
else begin
// SEND - send up to eight serial bytes
if (state == SEND) begin
ss_enable <= 1;
state <= SEND_2;
end
else if (state == SEND_2) begin
state <= SEND_3;
end
else if (state == SEND_3) begin
mosi <= send_buf[(7 - send_idx) + (8 * send_ctr)];
if (send_idx == 7) begin
send_idx <= 0;
state <= SEND_4;
end else begin
sclk_enable <= 1;
send_idx <= send_idx + 1;
end
end
else if (state == SEND_4) begin
mosi <= 0;
state <= SEND_5;
end
else if (state == SEND_5) begin
sclk_enable <= 0;
ss_enable <= 0;
if (send_ctr == send_max) begin
send_ctr <= 0;
send_max <= 0;
state <= next_state;
end else begin
send_ctr <= send_ctr + 1;
state <= SEND;
end
end
// SENDHEX - send a glyph corresponding to a hex value
else if (state == SENDHEX) begin
send_buf <= glyph_rom[(data >> ({hex_idx, 2'b00})) & 4'hF];
send_max <= 0;
if (hex_idx == 0) begin
next_state <= next_state_hex;
end else begin
next_state <= SENDHEX;
hex_idx <= hex_idx - 1;
end
state <= SEND;
end
// SENDJOYPAD - send a glyph corresponding to a joypad button
else if (state == SENDJOYPAD) begin
case (btn_idx)
0: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h42; // B
1: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h59; // Y
2: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h73; // Select
3: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h53; // Start
4: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h5E; // Up
5: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h64; // Down
6: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h3C; // Left
7: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h3E; // Right
8: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h41; // A
9: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h58; // X
10: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h4C; // L
11: send_buf <= joypad_state[btn_idx] ? 8'h20 : 8'h52; // R
default: send_buf <= 8'h20;
endcase
send_max <= 0;
if (btn_idx == 15) begin
btn_idx <= 4'b0;
next_state <= next_state_btn;
end else begin
next_state <= SENDJOYPAD;
btn_idx <= btn_idx + 1;
end
state <= SEND;
end
// WAIT - wait for # of cycles
else if (state == WAIT) begin
if (wait_ctr == wait_max) begin
wait_ctr <= 0;
state <= next_state;
end else begin
wait_ctr <= wait_ctr + 1;
end
end
// STARTUP_1 -- send display on, backlight on cmd
else if (state == STARTUP_1) begin
send_buf <= 32'h65335B1B; // ESC BRACKET '3' 'e'
send_max <= 3;
state <= SEND;
next_state <= STARTUP_2;
end
// STARTUP_2 -- clear the display
else if (state == STARTUP_2) begin
send_buf <= 32'h6A305B1B; // ESC BRACKET '0' 'j'
send_max <= 3;
state <= SEND;
next_state <= STARTUP_3;
end
// STARTUP_3 -- set the cursor mode
else if (state == STARTUP_3) begin
send_buf <= 32'h63305B1B; // ESC BRACKET '0' 'c'
send_max <= 3;
state <= SEND;
next_state <= STARTUP_4;
end
// STARTUP_4 -- set the display mode
else if (state == STARTUP_4) begin
send_buf <= 32'h68305B1B; // ESC BRACKET '0' 'h'
send_max <= 3;
state <= SEND;
next_state <= LOOP_1;
end
// LOOP_1 -- set cursor to 0,0
else if (state == LOOP_1) begin
send_buf <= 48'h48303B305B1B; // ESC BRACKET '0' ';' '0' 'H'
send_max <= 5;
state <= SEND;
next_state <= LOOP_2;
mode_latch <= mode;
end
else if (state == LOOP_2) begin
send_buf <= 24'h3A4120; // A:
send_max <= 2;
state <= SEND;
next_state <= LOOP_3;
end
else if (state == LOOP_3) begin
data <= A;
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_4;
end
else if (state == LOOP_4) begin
send_buf <= 32'h3A4f4920; // IO:
send_max <= 3;
state <= SEND;
next_state <= LOOP_5;
end
else if (state == LOOP_5) begin
data <= { Di, Do };
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_6;
end
else if (state == LOOP_6) begin
send_buf <= 48'h48303B315B1B; // ESC BRACKET '1' ';' '0' 'H'
send_max <= 5;
state <= SEND;
next_state <= mode_latch == 2'b11 ? LOOP_7b : LOOP_7;
end
else if (state == LOOP_7) begin
case (mode_latch)
2'b00: send_buf <= 24'h3A4350; // PC:
2'b01: send_buf <= 24'h3A4641; // AF:
2'b10: send_buf <= 24'h3A4544; // DE:
endcase
send_max <= 2;
state <= SEND;
next_state <= LOOP_8;
end
else if (state == LOOP_8) begin
case (mode_latch)
2'b00: data <= PC;
2'b01: data <= AF;
2'b10: data <= DE;
endcase
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_9;
end
else if (state == LOOP_9) begin
case (mode_latch)
2'b00: send_buf <= 32'h3A505320; // SP:
2'b01: send_buf <= 32'h3A434220; // BC:
2'b10: send_buf <= 32'h3A4C4820; // HL:
endcase
send_max <= 3;
state <= SEND;
next_state <= LOOP_10;
end
else if (state == LOOP_10) begin
case (mode_latch)
2'b00: data <= SP;
2'b01: data <= BC;
2'b10: data <= HL;
endcase
hex_idx <= 3;
state <= SENDHEX;
next_state_hex <= LOOP_11;
end
else if (state == LOOP_7b) begin
send_buf <= 16'h2020;
send_max <= 1;
state <= SEND;
next_state <= LOOP_8b;
end
else if (state == LOOP_8b) begin
state <= SENDJOYPAD;
next_state_btn <= LOOP_11;
end
else if (state == LOOP_11) begin
wait_max <= 10;
state <= WAIT;
next_state <= LOOP_1;
end
end
end
assign ss = (ss_enable) ? 1'b0 : 1'b1;
assign sclk = (sclk_enable) ? !clock : 1'b1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311AI_TB_V
`define SKY130_FD_SC_LP__O311AI_TB_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o311ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__o311ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311AI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_ISOLATCH_PP_PKG_S_TB_V
`define SKY130_FD_SC_HS__UDP_ISOLATCH_PP_PKG_S_TB_V
/**
* udp_isolatch_pp$PKG$s: Power isolating latch. Includes VPWR, KAPWR,
* and VGND power pins with active low sleep
* pin (SLEEP_B).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_isolatch_pp_pkg_s.v"
module top();
// Inputs are registered
reg D;
reg SLEEP_B;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 SLEEP_B = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 KAPWR = 1'b1;
#160 SLEEP_B = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 KAPWR = 1'b0;
#260 SLEEP_B = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 SLEEP_B = 1'b1;
#380 KAPWR = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 SLEEP_B = 1'bx;
#480 KAPWR = 1'bx;
#500 D = 1'bx;
end
sky130_fd_sc_hs__udp_isolatch_pp$PKG$s dut (.D(D), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_ISOLATCH_PP_PKG_S_TB_V
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333313, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=49.5, PCW_UIPARAM_DDR_T_RAS_MIN=36.0, PCW_UIPARAM_DDR_T_FAW=45.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.025, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.028, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.009, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.061, PCW_UIPARAM_DDR_BOARD_DELAY0=0.41, PCW_UIPARAM_DDR_BOARD_DELAY1=0.411, PCW_UIPARAM_DDR_BOARD_DELAY2=0.341, PCW_UIPARAM_DDR_BOARD_DELAY3=0.358, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=68.4725, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=71.086, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=66.794, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=108.7385, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=64.1705, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=63.686, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=68.46, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=105.4895, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\
, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200.000000, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100.000000, PCW_FPGA1_PERIPHERAL_FREQMHZ=150.000000, PCW_FPGA2_PERIPHERAL_FREQMHZ=50.000000, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100\
, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41J128M16 HA-15E, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2\
, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_SINGLE_QSPI_DATA_MODE=x4, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=MIO 46, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0\
, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X\
, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11\
}" *)
(* HW_HANDOFF = "led_controller_design_processing_system7_0_0.hwdef" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0,
// Enable and disable AFI Secure transaction
parameter C_USE_AXI_NONSECURE = 0,
//parameters for HP enable ports
parameter C_USE_S_AXI_HP0 = 0,
parameter C_USE_S_AXI_HP1 = 0,
parameter C_USE_S_AXI_HP2 = 0,
parameter C_USE_S_AXI_HP3 = 0,
//parameters for GP and ACP enable ports */
parameter C_USE_M_AXI_GP0 = 0,
parameter C_USE_M_AXI_GP1 = 0,
parameter C_USE_S_AXI_GP0 = 0,
parameter C_USE_S_AXI_GP1 = 0,
parameter C_USE_S_AXI_ACP = 0,
parameter C_GP0_EN_MODIFIABLE_TXN=0,
parameter C_GP1_EN_MODIFIABLE_TXN=0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN = 'b0,
output reg ENET0_GMII_TX_ER = 'b0,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN = 'b0,
output reg ENET1_GMII_TX_ER = 'b0,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
wire [3:0] M_AXI_GP0_ARCACHE_t;
wire [3:0] M_AXI_GP1_ARCACHE_t;
wire [3:0] M_AXI_GP0_AWCACHE_t;
wire [3:0] M_AXI_GP1_AWCACHE_t;
// Wires for connecting to the PS7
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
wire FCLK_CLK0_temp;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire S_AXI_HP0_ACLK_temp;
wire S_AXI_HP1_ACLK_temp;
wire S_AXI_HP2_ACLK_temp;
wire S_AXI_HP3_ACLK_temp;
wire M_AXI_GP0_ACLK_temp;
wire M_AXI_GP1_ACLK_temp;
wire S_AXI_GP0_ACLK_temp;
wire S_AXI_GP1_ACLK_temp;
wire S_AXI_ACP_ACLK_temp;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
else
begin
always @*
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= 1'b0;
TRACE_DATA_PIPE[j-1] <= 1'b0;
end
TRACE_CLK_OUT <= 1'b0;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
else
always@*
begin
ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= 'b0;
ENET0_GMII_CRS_i <= 'b0;
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET0_GMII_RXD_i <= 0;
ENET0_GMII_RX_DV_i <= 0;
ENET0_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
else
begin
always@*
begin
ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET1_GMII_COL_i <= 0;
ENET1_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET1_GMII_RXD_i <= 'b0;
ENET1_GMII_RX_DV_i <= 'b0;
ENET1_GMII_RX_ER_i <= 'b0;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
else
begin
assign FTMD_TRACEIN_DATA_i = 1'b0;
assign FTMD_TRACEIN_VALID_i = 1'b0;
assign FTMD_TRACEIN_ATID_i = 1'b0;
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
else
begin
assign PJTAG_TDO = 1'b0;
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
assign FCLK_CLK0 = FCLK_CLK0_temp;
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
// Connect FCLK in case of disable the AXI port for non Secure Transaction
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
end
endgenerate
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
end
endgenerate
assign M_AXI_GP0_ARCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP0_ARCACHE_t[0]}}:M_AXI_GP0_ARCACHE_t ;
assign M_AXI_GP1_ARCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP1_ARCACHE_t[0]}}:M_AXI_GP1_ARCACHE_t ;
assign M_AXI_GP0_AWCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP0_AWCACHE_t[0]}}:M_AXI_GP0_AWCACHE_t ;
assign M_AXI_GP1_AWCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP1_AWCACHE_t[0]}}:M_AXI_GP1_AWCACHE_t ;
//END
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK_temp),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
module diff_rom (
input wire [8:0] inadrs,
output wire [15:0] outdiff);
assign outdiff = sin_rom(inadrs);
function [15:0] sin_rom;
input [8:0] adrs;
begin
case (adrs)
9'D0 : sin_rom = 201 ;
9'D1 : sin_rom = 201 ;
9'D2 : sin_rom = 202 ;
9'D3 : sin_rom = 201 ;
9'D4 : sin_rom = 202 ;
9'D5 : sin_rom = 201 ;
9'D6 : sin_rom = 202 ;
9'D7 : sin_rom = 201 ;
9'D8 : sin_rom = 201 ;
9'D9 : sin_rom = 202 ;
9'D10 : sin_rom = 201 ;
9'D11 : sin_rom = 201 ;
9'D12 : sin_rom = 202 ;
9'D13 : sin_rom = 201 ;
9'D14 : sin_rom = 201 ;
9'D15 : sin_rom = 201 ;
9'D16 : sin_rom = 202 ;
9'D17 : sin_rom = 201 ;
9'D18 : sin_rom = 201 ;
9'D19 : sin_rom = 201 ;
9'D20 : sin_rom = 201 ;
9'D21 : sin_rom = 201 ;
9'D22 : sin_rom = 201 ;
9'D23 : sin_rom = 201 ;
9'D24 : sin_rom = 201 ;
9'D25 : sin_rom = 201 ;
9'D26 : sin_rom = 201 ;
9'D27 : sin_rom = 200 ;
9'D28 : sin_rom = 201 ;
9'D29 : sin_rom = 201 ;
9'D30 : sin_rom = 200 ;
9'D31 : sin_rom = 201 ;
9'D32 : sin_rom = 200 ;
9'D33 : sin_rom = 201 ;
9'D34 : sin_rom = 200 ;
9'D35 : sin_rom = 200 ;
9'D36 : sin_rom = 200 ;
9'D37 : sin_rom = 200 ;
9'D38 : sin_rom = 200 ;
9'D39 : sin_rom = 200 ;
9'D40 : sin_rom = 200 ;
9'D41 : sin_rom = 200 ;
9'D42 : sin_rom = 200 ;
9'D43 : sin_rom = 200 ;
9'D44 : sin_rom = 199 ;
9'D45 : sin_rom = 200 ;
9'D46 : sin_rom = 199 ;
9'D47 : sin_rom = 199 ;
9'D48 : sin_rom = 200 ;
9'D49 : sin_rom = 199 ;
9'D50 : sin_rom = 199 ;
9'D51 : sin_rom = 199 ;
9'D52 : sin_rom = 198 ;
9'D53 : sin_rom = 199 ;
9'D54 : sin_rom = 199 ;
9'D55 : sin_rom = 198 ;
9'D56 : sin_rom = 199 ;
9'D57 : sin_rom = 198 ;
9'D58 : sin_rom = 198 ;
9'D59 : sin_rom = 198 ;
9'D60 : sin_rom = 198 ;
9'D61 : sin_rom = 198 ;
9'D62 : sin_rom = 198 ;
9'D63 : sin_rom = 198 ;
9'D64 : sin_rom = 197 ;
9'D65 : sin_rom = 198 ;
9'D66 : sin_rom = 197 ;
9'D67 : sin_rom = 197 ;
9'D68 : sin_rom = 197 ;
9'D69 : sin_rom = 197 ;
9'D70 : sin_rom = 197 ;
9'D71 : sin_rom = 196 ;
9'D72 : sin_rom = 197 ;
9'D73 : sin_rom = 196 ;
9'D74 : sin_rom = 196 ;
9'D75 : sin_rom = 196 ;
9'D76 : sin_rom = 196 ;
9'D77 : sin_rom = 196 ;
9'D78 : sin_rom = 196 ;
9'D79 : sin_rom = 195 ;
9'D80 : sin_rom = 195 ;
9'D81 : sin_rom = 195 ;
9'D82 : sin_rom = 195 ;
9'D83 : sin_rom = 195 ;
9'D84 : sin_rom = 195 ;
9'D85 : sin_rom = 195 ;
9'D86 : sin_rom = 194 ;
9'D87 : sin_rom = 194 ;
9'D88 : sin_rom = 194 ;
9'D89 : sin_rom = 194 ;
9'D90 : sin_rom = 194 ;
9'D91 : sin_rom = 193 ;
9'D92 : sin_rom = 194 ;
9'D93 : sin_rom = 193 ;
9'D94 : sin_rom = 193 ;
9'D95 : sin_rom = 193 ;
9'D96 : sin_rom = 192 ;
9'D97 : sin_rom = 193 ;
9'D98 : sin_rom = 192 ;
9'D99 : sin_rom = 192 ;
9'D100 : sin_rom = 192 ;
9'D101 : sin_rom = 192 ;
9'D102 : sin_rom = 191 ;
9'D103 : sin_rom = 192 ;
9'D104 : sin_rom = 191 ;
9'D105 : sin_rom = 191 ;
9'D106 : sin_rom = 191 ;
9'D107 : sin_rom = 190 ;
9'D108 : sin_rom = 191 ;
9'D109 : sin_rom = 190 ;
9'D110 : sin_rom = 190 ;
9'D111 : sin_rom = 189 ;
9'D112 : sin_rom = 190 ;
9'D113 : sin_rom = 189 ;
9'D114 : sin_rom = 189 ;
9'D115 : sin_rom = 189 ;
9'D116 : sin_rom = 189 ;
9'D117 : sin_rom = 188 ;
9'D118 : sin_rom = 189 ;
9'D119 : sin_rom = 188 ;
9'D120 : sin_rom = 187 ;
9'D121 : sin_rom = 188 ;
9'D122 : sin_rom = 187 ;
9'D123 : sin_rom = 187 ;
9'D124 : sin_rom = 187 ;
9'D125 : sin_rom = 187 ;
9'D126 : sin_rom = 186 ;
9'D127 : sin_rom = 187 ;
9'D128 : sin_rom = 186 ;
9'D129 : sin_rom = 185 ;
9'D130 : sin_rom = 186 ;
9'D131 : sin_rom = 185 ;
9'D132 : sin_rom = 185 ;
9'D133 : sin_rom = 185 ;
9'D134 : sin_rom = 184 ;
9'D135 : sin_rom = 184 ;
9'D136 : sin_rom = 184 ;
9'D137 : sin_rom = 184 ;
9'D138 : sin_rom = 183 ;
9'D139 : sin_rom = 184 ;
9'D140 : sin_rom = 183 ;
9'D141 : sin_rom = 182 ;
9'D142 : sin_rom = 183 ;
9'D143 : sin_rom = 182 ;
9'D144 : sin_rom = 182 ;
9'D145 : sin_rom = 182 ;
9'D146 : sin_rom = 181 ;
9'D147 : sin_rom = 181 ;
9'D148 : sin_rom = 181 ;
9'D149 : sin_rom = 180 ;
9'D150 : sin_rom = 181 ;
9'D151 : sin_rom = 180 ;
9'D152 : sin_rom = 179 ;
9'D153 : sin_rom = 180 ;
9'D154 : sin_rom = 179 ;
9'D155 : sin_rom = 179 ;
9'D156 : sin_rom = 178 ;
9'D157 : sin_rom = 179 ;
9'D158 : sin_rom = 178 ;
9'D159 : sin_rom = 177 ;
9'D160 : sin_rom = 178 ;
9'D161 : sin_rom = 177 ;
9'D162 : sin_rom = 177 ;
9'D163 : sin_rom = 176 ;
9'D164 : sin_rom = 177 ;
9'D165 : sin_rom = 176 ;
9'D166 : sin_rom = 175 ;
9'D167 : sin_rom = 176 ;
9'D168 : sin_rom = 175 ;
9'D169 : sin_rom = 174 ;
9'D170 : sin_rom = 175 ;
9'D171 : sin_rom = 174 ;
9'D172 : sin_rom = 174 ;
9'D173 : sin_rom = 173 ;
9'D174 : sin_rom = 173 ;
9'D175 : sin_rom = 173 ;
9'D176 : sin_rom = 173 ;
9'D177 : sin_rom = 172 ;
9'D178 : sin_rom = 172 ;
9'D179 : sin_rom = 171 ;
9'D180 : sin_rom = 172 ;
9'D181 : sin_rom = 170 ;
9'D182 : sin_rom = 171 ;
9'D183 : sin_rom = 170 ;
9'D184 : sin_rom = 170 ;
9'D185 : sin_rom = 170 ;
9'D186 : sin_rom = 169 ;
9'D187 : sin_rom = 169 ;
9'D188 : sin_rom = 168 ;
9'D189 : sin_rom = 169 ;
9'D190 : sin_rom = 168 ;
9'D191 : sin_rom = 167 ;
9'D192 : sin_rom = 167 ;
9'D193 : sin_rom = 167 ;
9'D194 : sin_rom = 167 ;
9'D195 : sin_rom = 166 ;
9'D196 : sin_rom = 166 ;
9'D197 : sin_rom = 165 ;
9'D198 : sin_rom = 165 ;
9'D199 : sin_rom = 165 ;
9'D200 : sin_rom = 164 ;
9'D201 : sin_rom = 164 ;
9'D202 : sin_rom = 164 ;
9'D203 : sin_rom = 163 ;
9'D204 : sin_rom = 163 ;
9'D205 : sin_rom = 163 ;
9'D206 : sin_rom = 162 ;
9'D207 : sin_rom = 162 ;
9'D208 : sin_rom = 161 ;
9'D209 : sin_rom = 162 ;
9'D210 : sin_rom = 160 ;
9'D211 : sin_rom = 161 ;
9'D212 : sin_rom = 160 ;
9'D213 : sin_rom = 159 ;
9'D214 : sin_rom = 159 ;
9'D215 : sin_rom = 159 ;
9'D216 : sin_rom = 159 ;
9'D217 : sin_rom = 158 ;
9'D218 : sin_rom = 158 ;
9'D219 : sin_rom = 157 ;
9'D220 : sin_rom = 157 ;
9'D221 : sin_rom = 156 ;
9'D222 : sin_rom = 156 ;
9'D223 : sin_rom = 156 ;
9'D224 : sin_rom = 156 ;
9'D225 : sin_rom = 155 ;
9'D226 : sin_rom = 154 ;
9'D227 : sin_rom = 154 ;
9'D228 : sin_rom = 154 ;
9'D229 : sin_rom = 153 ;
9'D230 : sin_rom = 153 ;
9'D231 : sin_rom = 153 ;
9'D232 : sin_rom = 152 ;
9'D233 : sin_rom = 152 ;
9'D234 : sin_rom = 151 ;
9'D235 : sin_rom = 151 ;
9'D236 : sin_rom = 151 ;
9'D237 : sin_rom = 150 ;
9'D238 : sin_rom = 149 ;
9'D239 : sin_rom = 150 ;
9'D240 : sin_rom = 149 ;
9'D241 : sin_rom = 148 ;
9'D242 : sin_rom = 148 ;
9'D243 : sin_rom = 148 ;
9'D244 : sin_rom = 147 ;
9'D245 : sin_rom = 147 ;
9'D246 : sin_rom = 146 ;
9'D247 : sin_rom = 146 ;
9'D248 : sin_rom = 145 ;
9'D249 : sin_rom = 145 ;
9'D250 : sin_rom = 145 ;
9'D251 : sin_rom = 144 ;
9'D252 : sin_rom = 144 ;
9'D253 : sin_rom = 143 ;
9'D254 : sin_rom = 143 ;
9'D255 : sin_rom = 143 ;
9'D256 : sin_rom = 142 ;
9'D257 : sin_rom = 141 ;
9'D258 : sin_rom = 141 ;
9'D259 : sin_rom = 141 ;
9'D260 : sin_rom = 140 ;
9'D261 : sin_rom = 140 ;
9'D262 : sin_rom = 139 ;
9'D263 : sin_rom = 139 ;
9'D264 : sin_rom = 139 ;
9'D265 : sin_rom = 138 ;
9'D266 : sin_rom = 137 ;
9'D267 : sin_rom = 137 ;
9'D268 : sin_rom = 137 ;
9'D269 : sin_rom = 136 ;
9'D270 : sin_rom = 136 ;
9'D271 : sin_rom = 135 ;
9'D272 : sin_rom = 135 ;
9'D273 : sin_rom = 134 ;
9'D274 : sin_rom = 134 ;
9'D275 : sin_rom = 134 ;
9'D276 : sin_rom = 133 ;
9'D277 : sin_rom = 132 ;
9'D278 : sin_rom = 132 ;
9'D279 : sin_rom = 132 ;
9'D280 : sin_rom = 131 ;
9'D281 : sin_rom = 131 ;
9'D282 : sin_rom = 130 ;
9'D283 : sin_rom = 129 ;
9'D284 : sin_rom = 130 ;
9'D285 : sin_rom = 128 ;
9'D286 : sin_rom = 129 ;
9'D287 : sin_rom = 127 ;
9'D288 : sin_rom = 128 ;
9'D289 : sin_rom = 126 ;
9'D290 : sin_rom = 127 ;
9'D291 : sin_rom = 126 ;
9'D292 : sin_rom = 125 ;
9'D293 : sin_rom = 125 ;
9'D294 : sin_rom = 124 ;
9'D295 : sin_rom = 124 ;
9'D296 : sin_rom = 124 ;
9'D297 : sin_rom = 122 ;
9'D298 : sin_rom = 123 ;
9'D299 : sin_rom = 122 ;
9'D300 : sin_rom = 121 ;
9'D301 : sin_rom = 121 ;
9'D302 : sin_rom = 121 ;
9'D303 : sin_rom = 120 ;
9'D304 : sin_rom = 119 ;
9'D305 : sin_rom = 119 ;
9'D306 : sin_rom = 119 ;
9'D307 : sin_rom = 118 ;
9'D308 : sin_rom = 117 ;
9'D309 : sin_rom = 117 ;
9'D310 : sin_rom = 116 ;
9'D311 : sin_rom = 116 ;
9'D312 : sin_rom = 116 ;
9'D313 : sin_rom = 115 ;
9'D314 : sin_rom = 114 ;
9'D315 : sin_rom = 114 ;
9'D316 : sin_rom = 113 ;
9'D317 : sin_rom = 113 ;
9'D318 : sin_rom = 113 ;
9'D319 : sin_rom = 112 ;
9'D320 : sin_rom = 111 ;
9'D321 : sin_rom = 111 ;
9'D322 : sin_rom = 110 ;
9'D323 : sin_rom = 110 ;
9'D324 : sin_rom = 109 ;
9'D325 : sin_rom = 109 ;
9'D326 : sin_rom = 108 ;
9'D327 : sin_rom = 108 ;
9'D328 : sin_rom = 107 ;
9'D329 : sin_rom = 107 ;
9'D330 : sin_rom = 106 ;
9'D331 : sin_rom = 105 ;
9'D332 : sin_rom = 105 ;
9'D333 : sin_rom = 105 ;
9'D334 : sin_rom = 104 ;
9'D335 : sin_rom = 103 ;
9'D336 : sin_rom = 103 ;
9'D337 : sin_rom = 103 ;
9'D338 : sin_rom = 102 ;
9'D339 : sin_rom = 101 ;
9'D340 : sin_rom = 101 ;
9'D341 : sin_rom = 100 ;
9'D342 : sin_rom = 100 ;
9'D343 : sin_rom = 99 ;
9'D344 : sin_rom = 99 ;
9'D345 : sin_rom = 98 ;
9'D346 : sin_rom = 97 ;
9'D347 : sin_rom = 98 ;
9'D348 : sin_rom = 96 ;
9'D349 : sin_rom = 96 ;
9'D350 : sin_rom = 95 ;
9'D351 : sin_rom = 95 ;
9'D352 : sin_rom = 95 ;
9'D353 : sin_rom = 93 ;
9'D354 : sin_rom = 94 ;
9'D355 : sin_rom = 92 ;
9'D356 : sin_rom = 92 ;
9'D357 : sin_rom = 92 ;
9'D358 : sin_rom = 91 ;
9'D359 : sin_rom = 90 ;
9'D360 : sin_rom = 90 ;
9'D361 : sin_rom = 90 ;
9'D362 : sin_rom = 88 ;
9'D363 : sin_rom = 89 ;
9'D364 : sin_rom = 87 ;
9'D365 : sin_rom = 88 ;
9'D366 : sin_rom = 86 ;
9'D367 : sin_rom = 86 ;
9'D368 : sin_rom = 86 ;
9'D369 : sin_rom = 84 ;
9'D370 : sin_rom = 85 ;
9'D371 : sin_rom = 84 ;
9'D372 : sin_rom = 83 ;
9'D373 : sin_rom = 82 ;
9'D374 : sin_rom = 82 ;
9'D375 : sin_rom = 82 ;
9'D376 : sin_rom = 81 ;
9'D377 : sin_rom = 80 ;
9'D378 : sin_rom = 80 ;
9'D379 : sin_rom = 79 ;
9'D380 : sin_rom = 79 ;
9'D381 : sin_rom = 78 ;
9'D382 : sin_rom = 78 ;
9'D383 : sin_rom = 77 ;
9'D384 : sin_rom = 76 ;
9'D385 : sin_rom = 76 ;
9'D386 : sin_rom = 75 ;
9'D387 : sin_rom = 75 ;
9'D388 : sin_rom = 74 ;
9'D389 : sin_rom = 73 ;
9'D390 : sin_rom = 73 ;
9'D391 : sin_rom = 72 ;
9'D392 : sin_rom = 72 ;
9'D393 : sin_rom = 71 ;
9'D394 : sin_rom = 71 ;
9'D395 : sin_rom = 70 ;
9'D396 : sin_rom = 70 ;
9'D397 : sin_rom = 68 ;
9'D398 : sin_rom = 69 ;
9'D399 : sin_rom = 67 ;
9'D400 : sin_rom = 67 ;
9'D401 : sin_rom = 67 ;
9'D402 : sin_rom = 66 ;
9'D403 : sin_rom = 65 ;
9'D404 : sin_rom = 65 ;
9'D405 : sin_rom = 64 ;
9'D406 : sin_rom = 64 ;
9'D407 : sin_rom = 63 ;
9'D408 : sin_rom = 62 ;
9'D409 : sin_rom = 62 ;
9'D410 : sin_rom = 61 ;
9'D411 : sin_rom = 61 ;
9'D412 : sin_rom = 60 ;
9'D413 : sin_rom = 60 ;
9'D414 : sin_rom = 59 ;
9'D415 : sin_rom = 58 ;
9'D416 : sin_rom = 58 ;
9'D417 : sin_rom = 57 ;
9'D418 : sin_rom = 56 ;
9'D419 : sin_rom = 56 ;
9'D420 : sin_rom = 55 ;
9'D421 : sin_rom = 55 ;
9'D422 : sin_rom = 54 ;
9'D423 : sin_rom = 54 ;
9'D424 : sin_rom = 53 ;
9'D425 : sin_rom = 52 ;
9'D426 : sin_rom = 52 ;
9'D427 : sin_rom = 51 ;
9'D428 : sin_rom = 51 ;
9'D429 : sin_rom = 49 ;
9'D430 : sin_rom = 50 ;
9'D431 : sin_rom = 49 ;
9'D432 : sin_rom = 48 ;
9'D433 : sin_rom = 47 ;
9'D434 : sin_rom = 47 ;
9'D435 : sin_rom = 47 ;
9'D436 : sin_rom = 45 ;
9'D437 : sin_rom = 45 ;
9'D438 : sin_rom = 45 ;
9'D439 : sin_rom = 44 ;
9'D440 : sin_rom = 43 ;
9'D441 : sin_rom = 43 ;
9'D442 : sin_rom = 42 ;
9'D443 : sin_rom = 41 ;
9'D444 : sin_rom = 41 ;
9'D445 : sin_rom = 41 ;
9'D446 : sin_rom = 39 ;
9'D447 : sin_rom = 39 ;
9'D448 : sin_rom = 39 ;
9'D449 : sin_rom = 38 ;
9'D450 : sin_rom = 37 ;
9'D451 : sin_rom = 37 ;
9'D452 : sin_rom = 36 ;
9'D453 : sin_rom = 35 ;
9'D454 : sin_rom = 35 ;
9'D455 : sin_rom = 34 ;
9'D456 : sin_rom = 34 ;
9'D457 : sin_rom = 33 ;
9'D458 : sin_rom = 32 ;
9'D459 : sin_rom = 32 ;
9'D460 : sin_rom = 31 ;
9'D461 : sin_rom = 30 ;
9'D462 : sin_rom = 30 ;
9'D463 : sin_rom = 30 ;
9'D464 : sin_rom = 28 ;
9'D465 : sin_rom = 28 ;
9'D466 : sin_rom = 28 ;
9'D467 : sin_rom = 27 ;
9'D468 : sin_rom = 26 ;
9'D469 : sin_rom = 26 ;
9'D470 : sin_rom = 25 ;
9'D471 : sin_rom = 24 ;
9'D472 : sin_rom = 24 ;
9'D473 : sin_rom = 23 ;
9'D474 : sin_rom = 23 ;
9'D475 : sin_rom = 22 ;
9'D476 : sin_rom = 21 ;
9'D477 : sin_rom = 21 ;
9'D478 : sin_rom = 20 ;
9'D479 : sin_rom = 19 ;
9'D480 : sin_rom = 19 ;
9'D481 : sin_rom = 18 ;
9'D482 : sin_rom = 18 ;
9'D483 : sin_rom = 17 ;
9'D484 : sin_rom = 16 ;
9'D485 : sin_rom = 16 ;
9'D486 : sin_rom = 15 ;
9'D487 : sin_rom = 15 ;
9'D488 : sin_rom = 14 ;
9'D489 : sin_rom = 13 ;
9'D490 : sin_rom = 13 ;
9'D491 : sin_rom = 12 ;
9'D492 : sin_rom = 11 ;
9'D493 : sin_rom = 11 ;
9'D494 : sin_rom = 10 ;
9'D495 : sin_rom = 10 ;
9'D496 : sin_rom = 9 ;
9'D497 : sin_rom = 8 ;
9'D498 : sin_rom = 8 ;
9'D499 : sin_rom = 7 ;
9'D500 : sin_rom = 7 ;
9'D501 : sin_rom = 5 ;
9'D502 : sin_rom = 6 ;
9'D503 : sin_rom = 4 ;
9'D504 : sin_rom = 4 ;
9'D505 : sin_rom = 4 ;
9'D506 : sin_rom = 3 ;
9'D507 : sin_rom = 2 ;
9'D508 : sin_rom = 1 ;
9'D509 : sin_rom = 1 ;
9'D510 : sin_rom = 0 ;
9'D511 : sin_rom = 0 ;
default : sin_rom = 0 ;
endcase
end
endfunction
endmodule
|
//
// Generated by Bluespec Compiler, version 2017.07.A (build 1da80f1, 2017-07-21)
//
// On Fri Jan 18 19:51:34 EST 2019
//
//
// Ports:
// Name I/O size props
// RDY_set_verbosity O 1 const
// valid O 1
// word_fst O 64
// word_snd O 5
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// req_opcode I 7 reg
// req_f7 I 7 reg
// req_rm I 3 reg
// req_rs2 I 5 reg
// req_v1 I 64 reg
// req_v2 I 64 reg
// req_v3 I 64 reg
// EN_set_verbosity I 1
// EN_req I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkRISCV_FBox(CLK,
RST_N,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
req_opcode,
req_f7,
req_rm,
req_rs2,
req_v1,
req_v2,
req_v3,
EN_req,
valid,
word_fst,
word_snd);
input CLK;
input RST_N;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method req
input [6 : 0] req_opcode;
input [6 : 0] req_f7;
input [2 : 0] req_rm;
input [4 : 0] req_rs2;
input [63 : 0] req_v1;
input [63 : 0] req_v2;
input [63 : 0] req_v3;
input EN_req;
// value method valid
output valid;
// value method word_fst
output [63 : 0] word_fst;
// value method word_snd
output [4 : 0] word_snd;
// signals for module outputs
wire [63 : 0] word_fst;
wire [4 : 0] word_snd;
wire RDY_set_verbosity, valid;
// inlined wires
reg [68 : 0] dw_result$wget;
wire dw_valid$wget, dw_valid$whas;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register requestR
reg [214 : 0] requestR;
wire [214 : 0] requestR$D_IN;
wire requestR$EN;
// register resultR
reg [69 : 0] resultR;
reg [69 : 0] resultR$D_IN;
wire resultR$EN;
// register stateR
reg [1 : 0] stateR;
reg [1 : 0] stateR$D_IN;
wire stateR$EN;
// ports of submodule fpu
reg [201 : 0] fpu$request_put;
wire [69 : 0] fpu$response_get;
wire fpu$EN_request_put,
fpu$EN_response_get,
fpu$RDY_request_put,
fpu$RDY_response_get;
// ports of submodule frmFpuF
wire frmFpuF$CLR, frmFpuF$DEQ, frmFpuF$D_IN, frmFpuF$ENQ;
// rule scheduling signals
wire CAN_FIRE_RL_doFADD_D,
CAN_FIRE_RL_doFADD_S,
CAN_FIRE_RL_doFCLASS_D,
CAN_FIRE_RL_doFCLASS_S,
CAN_FIRE_RL_doFCVT_D_S,
CAN_FIRE_RL_doFCVT_D_W,
CAN_FIRE_RL_doFCVT_D_WU,
CAN_FIRE_RL_doFCVT_S_D,
CAN_FIRE_RL_doFCVT_S_W,
CAN_FIRE_RL_doFCVT_S_WU,
CAN_FIRE_RL_doFCVT_WU_D,
CAN_FIRE_RL_doFCVT_WU_S,
CAN_FIRE_RL_doFCVT_W_D,
CAN_FIRE_RL_doFCVT_W_S,
CAN_FIRE_RL_doFEQ_D,
CAN_FIRE_RL_doFEQ_S,
CAN_FIRE_RL_doFLE_D,
CAN_FIRE_RL_doFLE_S,
CAN_FIRE_RL_doFLT_D,
CAN_FIRE_RL_doFLT_S,
CAN_FIRE_RL_doFMADD_D,
CAN_FIRE_RL_doFMADD_S,
CAN_FIRE_RL_doFMAX_D,
CAN_FIRE_RL_doFMAX_S,
CAN_FIRE_RL_doFMIN_D,
CAN_FIRE_RL_doFMIN_S,
CAN_FIRE_RL_doFMSUB_D,
CAN_FIRE_RL_doFMSUB_S,
CAN_FIRE_RL_doFMUL_D,
CAN_FIRE_RL_doFMUL_S,
CAN_FIRE_RL_doFMV_D_X,
CAN_FIRE_RL_doFMV_W_X,
CAN_FIRE_RL_doFMV_X_D,
CAN_FIRE_RL_doFMV_X_W,
CAN_FIRE_RL_doFNMADD_D,
CAN_FIRE_RL_doFNMADD_S,
CAN_FIRE_RL_doFNMSUB_D,
CAN_FIRE_RL_doFNMSUB_S,
CAN_FIRE_RL_doFSGNJN_D,
CAN_FIRE_RL_doFSGNJN_S,
CAN_FIRE_RL_doFSGNJX_D,
CAN_FIRE_RL_doFSGNJX_S,
CAN_FIRE_RL_doFSGNJ_D,
CAN_FIRE_RL_doFSGNJ_S,
CAN_FIRE_RL_doFSUB_D,
CAN_FIRE_RL_doFSUB_S,
CAN_FIRE_RL_rl_drive_fpu_result,
CAN_FIRE_RL_rl_get_fpu_result,
CAN_FIRE_req,
CAN_FIRE_set_verbosity,
WILL_FIRE_RL_doFADD_D,
WILL_FIRE_RL_doFADD_S,
WILL_FIRE_RL_doFCLASS_D,
WILL_FIRE_RL_doFCLASS_S,
WILL_FIRE_RL_doFCVT_D_S,
WILL_FIRE_RL_doFCVT_D_W,
WILL_FIRE_RL_doFCVT_D_WU,
WILL_FIRE_RL_doFCVT_S_D,
WILL_FIRE_RL_doFCVT_S_W,
WILL_FIRE_RL_doFCVT_S_WU,
WILL_FIRE_RL_doFCVT_WU_D,
WILL_FIRE_RL_doFCVT_WU_S,
WILL_FIRE_RL_doFCVT_W_D,
WILL_FIRE_RL_doFCVT_W_S,
WILL_FIRE_RL_doFEQ_D,
WILL_FIRE_RL_doFEQ_S,
WILL_FIRE_RL_doFLE_D,
WILL_FIRE_RL_doFLE_S,
WILL_FIRE_RL_doFLT_D,
WILL_FIRE_RL_doFLT_S,
WILL_FIRE_RL_doFMADD_D,
WILL_FIRE_RL_doFMADD_S,
WILL_FIRE_RL_doFMAX_D,
WILL_FIRE_RL_doFMAX_S,
WILL_FIRE_RL_doFMIN_D,
WILL_FIRE_RL_doFMIN_S,
WILL_FIRE_RL_doFMSUB_D,
WILL_FIRE_RL_doFMSUB_S,
WILL_FIRE_RL_doFMUL_D,
WILL_FIRE_RL_doFMUL_S,
WILL_FIRE_RL_doFMV_D_X,
WILL_FIRE_RL_doFMV_W_X,
WILL_FIRE_RL_doFMV_X_D,
WILL_FIRE_RL_doFMV_X_W,
WILL_FIRE_RL_doFNMADD_D,
WILL_FIRE_RL_doFNMADD_S,
WILL_FIRE_RL_doFNMSUB_D,
WILL_FIRE_RL_doFNMSUB_S,
WILL_FIRE_RL_doFSGNJN_D,
WILL_FIRE_RL_doFSGNJN_S,
WILL_FIRE_RL_doFSGNJX_D,
WILL_FIRE_RL_doFSGNJX_S,
WILL_FIRE_RL_doFSGNJ_D,
WILL_FIRE_RL_doFSGNJ_S,
WILL_FIRE_RL_doFSUB_D,
WILL_FIRE_RL_doFSUB_S,
WILL_FIRE_RL_rl_drive_fpu_result,
WILL_FIRE_RL_rl_get_fpu_result,
WILL_FIRE_req,
WILL_FIRE_set_verbosity;
// inputs to muxes for submodule ports
wire [201 : 0] MUX_fpu$request_put_1__VAL_1,
MUX_fpu$request_put_1__VAL_10,
MUX_fpu$request_put_1__VAL_11,
MUX_fpu$request_put_1__VAL_12,
MUX_fpu$request_put_1__VAL_13,
MUX_fpu$request_put_1__VAL_14,
MUX_fpu$request_put_1__VAL_2,
MUX_fpu$request_put_1__VAL_3,
MUX_fpu$request_put_1__VAL_4,
MUX_fpu$request_put_1__VAL_5,
MUX_fpu$request_put_1__VAL_6,
MUX_fpu$request_put_1__VAL_7,
MUX_fpu$request_put_1__VAL_8,
MUX_fpu$request_put_1__VAL_9;
wire [69 : 0] MUX_resultR$write_1__VAL_10,
MUX_resultR$write_1__VAL_11,
MUX_resultR$write_1__VAL_12,
MUX_resultR$write_1__VAL_13,
MUX_resultR$write_1__VAL_14,
MUX_resultR$write_1__VAL_15,
MUX_resultR$write_1__VAL_16,
MUX_resultR$write_1__VAL_17,
MUX_resultR$write_1__VAL_18,
MUX_resultR$write_1__VAL_19,
MUX_resultR$write_1__VAL_2,
MUX_resultR$write_1__VAL_20,
MUX_resultR$write_1__VAL_21,
MUX_resultR$write_1__VAL_22,
MUX_resultR$write_1__VAL_23,
MUX_resultR$write_1__VAL_24,
MUX_resultR$write_1__VAL_25,
MUX_resultR$write_1__VAL_26,
MUX_resultR$write_1__VAL_27,
MUX_resultR$write_1__VAL_28,
MUX_resultR$write_1__VAL_29,
MUX_resultR$write_1__VAL_3,
MUX_resultR$write_1__VAL_30,
MUX_resultR$write_1__VAL_31,
MUX_resultR$write_1__VAL_32,
MUX_resultR$write_1__VAL_33,
MUX_resultR$write_1__VAL_34,
MUX_resultR$write_1__VAL_4,
MUX_resultR$write_1__VAL_6,
MUX_resultR$write_1__VAL_7,
MUX_resultR$write_1__VAL_8,
MUX_resultR$write_1__VAL_9;
wire [68 : 0] MUX_dw_result$wset_1__VAL_1,
MUX_dw_result$wset_1__VAL_10,
MUX_dw_result$wset_1__VAL_11,
MUX_dw_result$wset_1__VAL_12,
MUX_dw_result$wset_1__VAL_13,
MUX_dw_result$wset_1__VAL_14,
MUX_dw_result$wset_1__VAL_15,
MUX_dw_result$wset_1__VAL_16,
MUX_dw_result$wset_1__VAL_17,
MUX_dw_result$wset_1__VAL_18,
MUX_dw_result$wset_1__VAL_19,
MUX_dw_result$wset_1__VAL_2,
MUX_dw_result$wset_1__VAL_20,
MUX_dw_result$wset_1__VAL_21,
MUX_dw_result$wset_1__VAL_22,
MUX_dw_result$wset_1__VAL_23,
MUX_dw_result$wset_1__VAL_24,
MUX_dw_result$wset_1__VAL_25,
MUX_dw_result$wset_1__VAL_26,
MUX_dw_result$wset_1__VAL_27,
MUX_dw_result$wset_1__VAL_28,
MUX_dw_result$wset_1__VAL_29,
MUX_dw_result$wset_1__VAL_3,
MUX_dw_result$wset_1__VAL_30,
MUX_dw_result$wset_1__VAL_31,
MUX_dw_result$wset_1__VAL_32,
MUX_dw_result$wset_1__VAL_4,
MUX_dw_result$wset_1__VAL_5,
MUX_dw_result$wset_1__VAL_6,
MUX_dw_result$wset_1__VAL_7,
MUX_dw_result$wset_1__VAL_8,
MUX_dw_result$wset_1__VAL_9;
wire MUX_dw_result$wset_1__SEL_1,
MUX_dw_result$wset_1__SEL_2,
MUX_dw_result$wset_1__SEL_30;
// remaining internal signals
reg [51 : 0] CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q114,
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q115,
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q116,
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q117,
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q118,
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q119,
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q56,
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q57,
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q45,
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q46,
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q54,
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q55,
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q41,
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q42,
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1362,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1380,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1548,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1563,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3561,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3588,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3607;
reg [22 : 0] CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q80,
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q81,
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q16,
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q17,
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q78,
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q79,
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q29,
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q30,
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q27,
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q28,
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q18,
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q19,
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q84,
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q85,
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q82,
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q83,
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2726,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2745,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2772,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2791,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d402,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d420,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d720,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d735;
reg [10 : 0] CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q102,
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q103,
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q104,
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q105,
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q106,
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q107,
CASE_guard5468_0b0_0_0b1_0_0b10_out_exp6087_0b_ETC__q49,
CASE_guard5468_0b0_0_0b1_theResult___exp6084_0_ETC__q50,
CASE_guard5772_0b0_0_0b1_0_0b10_out_exp6391_0b_ETC__q44,
CASE_guard5772_0b0_0_0b1_theResult___exp6388_0_ETC__q43,
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_theR_ETC__q52,
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_x621_ETC__q53,
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_theR_ETC__q39,
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_x651_ETC__q40,
CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4,
CASE_requestR_BITS_194_TO_192_0x3_IF_guard5468_ETC__q51,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1310,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1339,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1526,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3134,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3459,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3528;
reg [7 : 0] CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q72,
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q73,
CASE_guard136_0b0_0_0b1_0_0b10_out_exp555_0b11_ETC__q13,
CASE_guard136_0b0_0_0b1_theResult___exp552_0b1_ETC__q12,
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q70,
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q71,
CASE_guard3313_0b0_0_0b1_0_0b10_out_exp3729_0b_ETC__q22,
CASE_guard3313_0b0_0_0b1_theResult___exp3726_0_ETC__q23,
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_theRe_ETC__q25,
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_x3854_ETC__q26,
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_theResu_ETC__q14,
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_x681_BI_ETC__q15,
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q76,
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q77,
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q74,
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q75,
CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2,
CASE_requestR_BITS_194_TO_192_0x3_IF_guard3313_ETC__q24,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2139,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2296,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2623,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2692,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d350,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d379,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d697;
reg [2 : 0] IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40;
reg CASE_guard0288_0b0_requestR_BIT_191_0b1_reques_ETC__q88,
CASE_guard11304_0b0_requestR_BITS_191_TO_160_E_ETC__q108,
CASE_guard136_0b0_requestR_BIT_159_0b1_request_ETC__q8,
CASE_guard1553_0b0_requestR_BIT_191_0b1_reques_ETC__q86,
CASE_guard20612_0b0_requestR_BITS_191_TO_160_E_ETC__q110,
CASE_guard29679_0b0_requestR_BITS_191_TO_160_E_ETC__q112,
CASE_guard5772_0b0_requestR_BIT_159_0b1_reques_ETC__q35,
CASE_guard6502_0b0_requestR_BIT_159_0b1_reques_ETC__q37,
CASE_guard666_0b0_requestR_BIT_159_0b1_request_ETC__q10,
CASE_guard8141_0b0_requestR_BIT_191_0b1_reques_ETC__q92,
CASE_guard9277_0b0_requestR_BIT_191_0b1_reques_ETC__q90,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93;
wire [85 : 0] IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618,
b__h47607,
x__h48283,
x__h49361;
wire [68 : 0] ab__h156914;
wire [64 : 0] _1_CONCAT_DONTCARE_CONCAT_requestR_BITS_63_TO_3_ETC___d68;
wire [63 : 0] IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1035,
IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1051,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1034,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1036,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1050,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1052,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1122,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1123,
IF_requestR_BITS_126_TO_116_745_EQ_2047_746_AN_ETC___d3793,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d3807,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d3878,
res___1__h155823,
res___1__h156261,
res___1__h156271,
res___1__h156290,
res___1__h26221,
res___1__h26457,
res___1__h26467,
res___1__h26486,
res__h139089,
res__h143531,
res__h148079,
res__h150783,
res__h153478,
res__h155355,
res__h156306,
res__h156487,
res__h17825,
res__h18062,
res__h23434,
res__h24917,
res__h25986,
res__h26502,
res__h97284,
x__h140114,
x__h144662,
x__h14804,
x__h149106,
x__h151801,
x__h153678,
x__h155805,
x__h156455,
x__h16397,
x__h17147,
x__h1773,
x__h1919,
x__h19781,
x__h2053,
x__h2201,
x__h22306,
x__h22427,
x__h22565,
x__h24048,
x__h25117,
x__h26203,
x__h27370,
x__h27492,
x__h27616,
x__h27746,
x__h37694,
x__h47361,
x__h48937,
x__h49683,
x__h8662,
x__h98388;
wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_ETC__q60,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q97,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BIT_ETC__q65,
IF_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_E_ETC__q100,
IF_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_E_ETC__q94,
IF_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_ETC__q62,
IF_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_ETC__q68,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827,
_0b0_CONCAT_NOT_IF_requestR_BITS_191_TO_160_4_E_ETC___d3152,
_0b0_CONCAT_NOT_requestR_BITS_190_TO_180_596_EQ_ETC___d2318,
_theResult____h120602,
_theResult____h61543,
_theResult____h79267,
_theResult___snd__h119216,
_theResult___snd__h119218,
_theResult___snd__h119225,
_theResult___snd__h119231,
_theResult___snd__h119254,
_theResult___snd__h128849,
_theResult___snd__h128860,
_theResult___snd__h128862,
_theResult___snd__h128872,
_theResult___snd__h128878,
_theResult___snd__h128901,
_theResult___snd__h137615,
_theResult___snd__h137629,
_theResult___snd__h137635,
_theResult___snd__h137653,
_theResult___snd__h69661,
_theResult___snd__h69672,
_theResult___snd__h69674,
_theResult___snd__h69684,
_theResult___snd__h69690,
_theResult___snd__h69713,
_theResult___snd__h78287,
_theResult___snd__h78289,
_theResult___snd__h78296,
_theResult___snd__h78302,
_theResult___snd__h78325,
_theResult___snd__h87514,
_theResult___snd__h87525,
_theResult___snd__h87527,
_theResult___snd__h87537,
_theResult___snd__h87543,
_theResult___snd__h87566,
_theResult___snd__h96164,
_theResult___snd__h96178,
_theResult___snd__h96184,
_theResult___snd__h96202,
b__h15050,
result__h121215,
result__h79880,
sfd__h53913,
sfdin__h128832,
sfdin__h69644,
sfdin__h87497,
x__h121310,
x__h15726,
x__h16821,
x__h79975;
wire [54 : 0] sfd___3__h35762, sfd___3__h45458, sfd__h27761, sfd__h37706;
wire [53 : 0] sfd__h119283,
sfd__h128930,
sfd__h137688,
sfd__h35789,
sfd__h36532,
sfd__h45485,
sfd__h46227,
value__h47609;
wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3582,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3584,
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3555,
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3557,
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3601,
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3603,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1356,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1358,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1374,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1376,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3614,
IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d1384,
IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d1567,
_theResult___fst_sfd__h104193,
_theResult___fst_sfd__h120019,
_theResult___fst_sfd__h120022,
_theResult___fst_sfd__h129666,
_theResult___fst_sfd__h129669,
_theResult___fst_sfd__h138448,
_theResult___fst_sfd__h138451,
_theResult___fst_sfd__h138460,
_theResult___fst_sfd__h138466,
_theResult___fst_sfd__h36486,
_theResult___fst_sfd__h37242,
_theResult___fst_sfd__h37245,
_theResult___fst_sfd__h46181,
_theResult___fst_sfd__h46936,
_theResult___fst_sfd__h46939,
_theResult___fst_sfd__h50209,
_theResult___sfd__h119921,
_theResult___sfd__h129568,
_theResult___sfd__h138350,
_theResult___sfd__h36389,
_theResult___sfd__h37145,
_theResult___sfd__h46085,
_theResult___sfd__h46840,
_theResult___snd_fst_sfd__h100339,
_theResult___snd_fst_sfd__h120025,
_theResult___snd_fst_sfd__h138454,
_theResult___snd_fst_sfd__h37248,
_theResult___snd_fst_sfd__h46942,
out___1_sfd__h98453,
out_sfd__h119924,
out_sfd__h129571,
out_sfd__h138353,
out_sfd__h36392,
out_sfd__h37148,
out_sfd__h46088,
out_sfd__h46843,
value__h49752;
wire [32 : 0] _theResult_____2__h14985,
_theResult_____2__h47542,
out1___1__h15477,
out1___1__h48034;
wire [31 : 0] IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1031,
IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1045,
IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1047,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1032,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1048,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d886,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d946,
IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d882,
IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d884,
IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d944,
IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1673,
IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1675,
IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1735,
IF_NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d1029,
IF_NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d1044,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d1737,
IF_requestR_BITS_190_TO_180_596_EQ_2047_597_AN_ETC___d1677,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d815,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d948,
IF_requestR_BIT_191_186_THEN_2147483648_ELSE_2_ETC___d1606,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28,
requestR_BITS_159_TO_128__q1,
sfd___3__h13303,
sfd___3__h7126,
sfd__h2222,
x__h14807,
x__h16400,
x__h1779,
x__h1925,
x__h2059,
x__h2207,
x__h47364,
x__h48940,
x__h97290;
wire [30 : 0] IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19;
wire [24 : 0] sfd__h13330,
sfd__h13869,
sfd__h69742,
sfd__h7153,
sfd__h7696,
sfd__h78354,
sfd__h87595,
sfd__h96237,
value__h15052;
wire [23 : 0] NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1611,
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1643,
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1644,
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1708;
wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2720,
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2722,
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2766,
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2768,
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2739,
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2741,
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2785,
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2787,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d396,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d398,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d414,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d416,
IF_requestR_BITS_190_TO_180_596_EQ_2047_597_AN_ETC___d2798,
_theResult___fst_sfd__h13823,
_theResult___fst_sfd__h14375,
_theResult___fst_sfd__h14378,
_theResult___fst_sfd__h61526,
_theResult___fst_sfd__h70275,
_theResult___fst_sfd__h70278,
_theResult___fst_sfd__h7650,
_theResult___fst_sfd__h78887,
_theResult___fst_sfd__h78890,
_theResult___fst_sfd__h8203,
_theResult___fst_sfd__h8206,
_theResult___fst_sfd__h88128,
_theResult___fst_sfd__h88131,
_theResult___fst_sfd__h96794,
_theResult___fst_sfd__h96797,
_theResult___fst_sfd__h96806,
_theResult___fst_sfd__h96812,
_theResult___fst_sfd__h98711,
_theResult___sfd__h13727,
_theResult___sfd__h14279,
_theResult___sfd__h70177,
_theResult___sfd__h7553,
_theResult___sfd__h78789,
_theResult___sfd__h8106,
_theResult___sfd__h88030,
_theResult___sfd__h96696,
_theResult___snd_fst_sfd__h14381,
_theResult___snd_fst_sfd__h53867,
_theResult___snd_fst_sfd__h78893,
_theResult___snd_fst_sfd__h8209,
_theResult___snd_fst_sfd__h96800,
out_sfd__h13730,
out_sfd__h14282,
out_sfd__h70180,
out_sfd__h7556,
out_sfd__h78792,
out_sfd__h8109,
out_sfd__h88033,
out_sfd__h96699,
sV1_sfd__h816,
sV2_sfd__h919,
value__h98456;
wire [19 : 0] NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d820,
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d852,
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d853,
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d917;
wire [11 : 0] IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3468,
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3145,
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q96,
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_609___d2311,
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q64,
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1840,
_3074_MINUS_SEXT_IF_requestR_BITS_191_TO_160_4__ETC___d3148,
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1230,
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1445,
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3002,
_3970_MINUS_SEXT_requestR_BITS_190_TO_180_596_M_ETC___d2314,
x__h121343,
x__h36517,
x__h46212,
x__h80008;
wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3453,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3455,
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3128,
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3130,
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3522,
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3524,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1307,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1333,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1335,
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q99,
_theResult___exp__h119920,
_theResult___exp__h129567,
_theResult___exp__h138349,
_theResult___exp__h36388,
_theResult___exp__h37144,
_theResult___exp__h46084,
_theResult___exp__h46839,
_theResult___fst_exp__h104192,
_theResult___fst_exp__h119256,
_theResult___fst_exp__h119262,
_theResult___fst_exp__h119265,
_theResult___fst_exp__h120018,
_theResult___fst_exp__h120021,
_theResult___fst_exp__h128838,
_theResult___fst_exp__h128903,
_theResult___fst_exp__h128909,
_theResult___fst_exp__h128912,
_theResult___fst_exp__h129665,
_theResult___fst_exp__h129668,
_theResult___fst_exp__h137621,
_theResult___fst_exp__h137660,
_theResult___fst_exp__h137666,
_theResult___fst_exp__h137669,
_theResult___fst_exp__h138447,
_theResult___fst_exp__h138450,
_theResult___fst_exp__h138459,
_theResult___fst_exp__h138462,
_theResult___fst_exp__h36485,
_theResult___fst_exp__h37241,
_theResult___fst_exp__h37244,
_theResult___fst_exp__h46180,
_theResult___fst_exp__h46935,
_theResult___fst_exp__h46938,
_theResult___snd_fst_exp__h120024,
_theResult___snd_fst_exp__h138453,
_theResult___snd_fst_exp__h37247,
_theResult___snd_fst_exp__h37250,
_theResult___snd_fst_exp__h37253,
_theResult___snd_fst_exp__h46941,
_theResult___snd_fst_exp__h46944,
_theResult___snd_fst_exp__h46947,
din_inc___2_exp__h138485,
din_inc___2_exp__h138515,
din_inc___2_exp__h138539,
din_inc___2_exp__h37287,
din_inc___2_exp__h46977,
out_exp__h119923,
out_exp__h129570,
out_exp__h138352,
out_exp__h36391,
out_exp__h37147,
out_exp__h46087,
out_exp__h46842,
requestR_BITS_190_TO_180_596_MINUS_1023___d1609,
x__h98397;
wire [8 : 0] IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2632,
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d258,
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d616,
x__h13854,
x__h7681;
wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2133,
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2135,
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2617,
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2619,
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2290,
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2292,
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2686,
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2688,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d347,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d373,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d375,
IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d385,
IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d703,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d818,
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q67,
_theResult___exp__h13726,
_theResult___exp__h14278,
_theResult___exp__h70176,
_theResult___exp__h7552,
_theResult___exp__h78788,
_theResult___exp__h8105,
_theResult___exp__h88029,
_theResult___exp__h96695,
_theResult___fst_exp__h13822,
_theResult___fst_exp__h14374,
_theResult___fst_exp__h14377,
_theResult___fst_exp__h61525,
_theResult___fst_exp__h69650,
_theResult___fst_exp__h69715,
_theResult___fst_exp__h69721,
_theResult___fst_exp__h69724,
_theResult___fst_exp__h70274,
_theResult___fst_exp__h70277,
_theResult___fst_exp__h7649,
_theResult___fst_exp__h78327,
_theResult___fst_exp__h78333,
_theResult___fst_exp__h78336,
_theResult___fst_exp__h78886,
_theResult___fst_exp__h78889,
_theResult___fst_exp__h8202,
_theResult___fst_exp__h8205,
_theResult___fst_exp__h87503,
_theResult___fst_exp__h87568,
_theResult___fst_exp__h87574,
_theResult___fst_exp__h87577,
_theResult___fst_exp__h88127,
_theResult___fst_exp__h88130,
_theResult___fst_exp__h96170,
_theResult___fst_exp__h96209,
_theResult___fst_exp__h96215,
_theResult___fst_exp__h96218,
_theResult___fst_exp__h96793,
_theResult___fst_exp__h96796,
_theResult___fst_exp__h96805,
_theResult___fst_exp__h96808,
_theResult___snd_fst_exp__h14380,
_theResult___snd_fst_exp__h14383,
_theResult___snd_fst_exp__h14386,
_theResult___snd_fst_exp__h78892,
_theResult___snd_fst_exp__h8208,
_theResult___snd_fst_exp__h8211,
_theResult___snd_fst_exp__h8214,
_theResult___snd_fst_exp__h96799,
din_inc___2_exp__h14416,
din_inc___2_exp__h8248,
din_inc___2_exp__h96827,
din_inc___2_exp__h96851,
din_inc___2_exp__h96881,
din_inc___2_exp__h96905,
out_exp__h13729,
out_exp__h14281,
out_exp__h70179,
out_exp__h7555,
out_exp__h78791,
out_exp__h8108,
out_exp__h88032,
out_exp__h96698,
sV1_exp__h815,
sV2_exp__h918,
x__h49692;
wire [5 : 0] IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_TO_180__ETC___d2074,
IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_191_TO__ETC___d3394,
IF_IF_3970_MINUS_SEXT_requestR_BITS_190_TO_180_ETC___d2558,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3074,
IF_IF_requestR_BIT_159_6_THEN_NEG_requestR_BIT_ETC___d1227,
IF_IF_requestR_BIT_159_6_THEN_NEG_requestR_BIT_ETC___d255,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2236,
IF_requestR_BIT_159_6_THEN_0_ELSE_IF_requestR__ETC___d1442,
IF_requestR_BIT_159_6_THEN_0_ELSE_IF_requestR__ETC___d613;
wire [4 : 0] _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2858,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3681,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2887,
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3664,
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2870,
x__h139191,
x__h143663,
x__h14520,
x__h153497,
x__h16140,
x__h16899,
x__h19186,
x__h24936,
x__h37409,
x__h47077,
x__h48680,
x__h49439,
x__h8374,
x__h97405;
wire [1 : 0] IF_sfd___3126_BIT_7_THEN_2_ELSE_0__q7,
IF_sfd___3126_BIT_8_THEN_2_ELSE_0__q6,
IF_sfd___33303_BIT_7_THEN_2_ELSE_0__q21,
IF_sfd___33303_BIT_8_THEN_2_ELSE_0__q20,
IF_sfd___35458_BIT_1_THEN_2_ELSE_0__q48,
IF_sfd___35458_BIT_2_THEN_2_ELSE_0__q47,
IF_sfd___35762_BIT_1_THEN_2_ELSE_0__q34,
IF_sfd___35762_BIT_2_THEN_2_ELSE_0__q33,
IF_sfdin28832_BIT_4_THEN_2_ELSE_0__q98,
IF_sfdin7497_BIT_33_THEN_2_ELSE_0__q66,
IF_sfdin9644_BIT_33_THEN_2_ELSE_0__q61,
IF_theResult___snd19216_BIT_4_THEN_2_ELSE_0__q95,
IF_theResult___snd37615_BIT_4_THEN_2_ELSE_0__q101,
IF_theResult___snd6164_BIT_33_THEN_2_ELSE_0__q69,
IF_theResult___snd8287_BIT_33_THEN_2_ELSE_0__q63,
IF_x5726_BIT_24_THEN_2_ELSE_0__q31,
IF_x6821_BIT_24_THEN_2_ELSE_0__q32,
IF_x8283_BIT_53_THEN_2_ELSE_0__q58,
IF_x9361_BIT_53_THEN_2_ELSE_0__q59,
guard__h111304,
guard__h120612,
guard__h129679,
guard__h13313,
guard__h13839,
guard__h14983,
guard__h15537,
guard__h16600,
guard__h35772,
guard__h36502,
guard__h45468,
guard__h46197,
guard__h47540,
guard__h48094,
guard__h49140,
guard__h61553,
guard__h70288,
guard__h7136,
guard__h7666,
guard__h79277,
guard__h88141;
wire IF_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_ETC___d2820,
IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d1286,
IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d1401,
IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d325,
IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d475,
IF_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THE_ETC___d1584,
IF_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THE_ETC___d789,
IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_191__ETC___d3638,
IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3646,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3650,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3685,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3688,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3695,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3709,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3721,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3733,
IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d908,
IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1699,
IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_15_ETC___d1287,
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_ETC___d3630,
IF_NOT_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1024,
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3648,
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3707,
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3719,
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3731,
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2838,
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2916,
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2929,
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2942,
IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_T_ETC___d1004,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2840,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2891,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2902,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2918,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2931,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2944,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1000,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1013,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1014,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1015,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1018,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1020,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1038,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1075,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1086,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1090,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d814,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d956,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d967,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d990,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1635,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1667,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1729,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d844,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d876,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d938,
IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d466,
IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d469,
IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d478,
IF_requestR_BIT_191_186_THEN_NOT_requestR_BITS_ETC___d3786,
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d855,
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d919,
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1646,
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1710,
NOT_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_76_ETC___d2910,
NOT_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_76_ETC___d2938,
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1027,
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1028,
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1085,
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1091,
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1109,
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d3047,
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d897,
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d961,
NOT_IF_requestR_BIT_159_6_THEN_NEG_requestR_BI_ETC___d263,
NOT_requestR_BITS_159_TO_128_24_EQ_0_25_26_AND_ETC___d781,
NOT_requestR_BITS_190_TO_180_596_EQ_0_607_613__ETC___d1688,
NOT_requestR_BITS_190_TO_180_596_EQ_0_607_613__ETC___d1752,
NOT_requestR_BITS_190_TO_180_596_EQ_2047_597_6_ETC___d3790,
NOT_requestR_BITS_190_TO_180_596_EQ_2047_597_6_ETC___d3855,
NOT_requestR_BITS_190_TO_180_596_ULT_requestR__ETC___d3832,
NOT_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_ETC___d1089,
NOT_requestR_BIT_158_88_89_AND_NOT_requestR_BI_ETC___d579,
NOT_requestR_BIT_179_767_142_AND_NOT_requestR__ETC___d2181,
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146,
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147,
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312,
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2076,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3396,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2560,
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3076,
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3469,
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2238,
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2633,
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841,
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842,
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2873,
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2898,
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2925,
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1231,
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1233,
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1235,
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d259,
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d261,
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d264,
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1446,
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1447,
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1448,
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d617,
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d618,
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d619,
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003,
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004,
guard__h121210,
guard__h79875,
requestR_BITS_126_TO_116_745_EQ_0_759_AND_requ_ETC___d3766,
requestR_BITS_179_TO_128_598_ULE_requestR_BITS_ETC___d3778,
requestR_BITS_179_TO_128_598_ULT_requestR_BITS_ETC___d3783,
requestR_BITS_190_TO_180_596_EQ_0_607_AND_requ_ETC___d3762,
requestR_BITS_190_TO_180_596_EQ_0_607_AND_requ_ETC___d3836,
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_0_ETC___d1747,
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_0_ETC___d1758,
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3754,
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3799,
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3821,
requestR_BITS_190_TO_180_596_EQ_requestR_BITS__ETC___d3777,
requestR_BITS_190_TO_180_596_ULE_requestR_BITS_ETC___d3775,
requestR_BITS_190_TO_180_596_ULE_requestR_BITS_ETC___d3831,
requestR_BITS_190_TO_180_596_ULT_requestR_BITS_ETC___d3782,
requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_AND_ETC___d1026,
requestR_BIT_158_88_OR_requestR_BIT_157_90_OR__ETC___d770,
requestR_BIT_159_6_OR_requestR_BIT_158_88_OR_r_ETC___d792;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method req
assign CAN_FIRE_req = 1'd1 ;
assign WILL_FIRE_req = EN_req ;
// value method valid
assign valid = dw_valid$whas && dw_valid$wget ;
// value method word_fst
assign word_fst = ab__h156914[68:5] ;
// value method word_snd
assign word_snd = ab__h156914[4:0] ;
// submodule fpu
mkFPU fpu(.CLK(CLK),
.RST_N(RST_N),
.request_put(fpu$request_put),
.EN_request_put(fpu$EN_request_put),
.EN_response_get(fpu$EN_response_get),
.RDY_request_put(fpu$RDY_request_put),
.response_get(fpu$response_get),
.RDY_response_get(fpu$RDY_response_get));
// submodule frmFpuF
FIFO2 #(.width(32'd1), .guarded(32'd1)) frmFpuF(.RST(RST_N),
.CLK(CLK),
.D_IN(frmFpuF$D_IN),
.ENQ(frmFpuF$ENQ),
.DEQ(frmFpuF$DEQ),
.CLR(frmFpuF$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// rule RL_doFADD_S
assign CAN_FIRE_RL_doFADD_S =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h0 ;
assign WILL_FIRE_RL_doFADD_S = CAN_FIRE_RL_doFADD_S ;
// rule RL_doFSUB_S
assign CAN_FIRE_RL_doFSUB_S =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h04 ;
assign WILL_FIRE_RL_doFSUB_S = CAN_FIRE_RL_doFSUB_S ;
// rule RL_doFMUL_S
assign CAN_FIRE_RL_doFMUL_S =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h08 ;
assign WILL_FIRE_RL_doFMUL_S = CAN_FIRE_RL_doFMUL_S ;
// rule RL_doFMADD_S
assign CAN_FIRE_RL_doFMADD_S =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1000011 &&
requestR[201:200] == 2'd0 ;
assign WILL_FIRE_RL_doFMADD_S = CAN_FIRE_RL_doFMADD_S ;
// rule RL_doFMSUB_S
assign CAN_FIRE_RL_doFMSUB_S =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1000111 &&
requestR[201:200] == 2'd0 ;
assign WILL_FIRE_RL_doFMSUB_S = CAN_FIRE_RL_doFMSUB_S ;
// rule RL_doFNMADD_S
assign CAN_FIRE_RL_doFNMADD_S =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1001111 &&
requestR[201:200] == 2'd0 ;
assign WILL_FIRE_RL_doFNMADD_S = CAN_FIRE_RL_doFNMADD_S ;
// rule RL_doFNMSUB_S
assign CAN_FIRE_RL_doFNMSUB_S =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1001011 &&
requestR[201:200] == 2'd0 ;
assign WILL_FIRE_RL_doFNMSUB_S = CAN_FIRE_RL_doFNMSUB_S ;
// rule RL_doFSGNJ_S
assign CAN_FIRE_RL_doFSGNJ_S = MUX_dw_result$wset_1__SEL_2 ;
assign WILL_FIRE_RL_doFSGNJ_S = MUX_dw_result$wset_1__SEL_2 ;
// rule RL_doFSGNJN_S
assign CAN_FIRE_RL_doFSGNJN_S = MUX_dw_result$wset_1__SEL_1 ;
assign WILL_FIRE_RL_doFSGNJN_S = MUX_dw_result$wset_1__SEL_1 ;
// rule RL_doFSGNJX_S
assign CAN_FIRE_RL_doFSGNJX_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h10 &&
requestR[194:192] == 3'h2 ;
assign WILL_FIRE_RL_doFSGNJX_S = CAN_FIRE_RL_doFSGNJX_S ;
// rule RL_doFCVT_S_W
assign CAN_FIRE_RL_doFCVT_S_W =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h68 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_S_W = CAN_FIRE_RL_doFCVT_S_W ;
// rule RL_doFCVT_S_WU
assign CAN_FIRE_RL_doFCVT_S_WU =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h68 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_S_WU = CAN_FIRE_RL_doFCVT_S_WU ;
// rule RL_doFCVT_W_S
assign CAN_FIRE_RL_doFCVT_W_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h60 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_W_S = CAN_FIRE_RL_doFCVT_W_S ;
// rule RL_doFCVT_WU_S
assign CAN_FIRE_RL_doFCVT_WU_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h60 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_WU_S = CAN_FIRE_RL_doFCVT_WU_S ;
// rule RL_doFMIN_S
assign CAN_FIRE_RL_doFMIN_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h14 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMIN_S = CAN_FIRE_RL_doFMIN_S ;
// rule RL_doFMAX_S
assign CAN_FIRE_RL_doFMAX_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h14 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFMAX_S = CAN_FIRE_RL_doFMAX_S ;
// rule RL_doFMV_W_X
assign CAN_FIRE_RL_doFMV_W_X =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h78 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMV_W_X = CAN_FIRE_RL_doFMV_W_X ;
// rule RL_doFMV_X_W
assign CAN_FIRE_RL_doFMV_X_W =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h70 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMV_X_W = CAN_FIRE_RL_doFMV_X_W ;
// rule RL_doFEQ_S
assign CAN_FIRE_RL_doFEQ_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h50 &&
requestR[194:192] == 3'h2 ;
assign WILL_FIRE_RL_doFEQ_S = CAN_FIRE_RL_doFEQ_S ;
// rule RL_doFLT_S
assign CAN_FIRE_RL_doFLT_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h50 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFLT_S = CAN_FIRE_RL_doFLT_S ;
// rule RL_doFLE_S
assign CAN_FIRE_RL_doFLE_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h50 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFLE_S = CAN_FIRE_RL_doFLE_S ;
// rule RL_doFCLASS_S
assign CAN_FIRE_RL_doFCLASS_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h70 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFCLASS_S = CAN_FIRE_RL_doFCLASS_S ;
// rule RL_doFADD_D
assign CAN_FIRE_RL_doFADD_D =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h01 ;
assign WILL_FIRE_RL_doFADD_D = CAN_FIRE_RL_doFADD_D ;
// rule RL_doFSUB_D
assign CAN_FIRE_RL_doFSUB_D =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h05 ;
assign WILL_FIRE_RL_doFSUB_D = CAN_FIRE_RL_doFSUB_D ;
// rule RL_doFMUL_D
assign CAN_FIRE_RL_doFMUL_D =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h09 ;
assign WILL_FIRE_RL_doFMUL_D = CAN_FIRE_RL_doFMUL_D ;
// rule RL_doFMADD_D
assign CAN_FIRE_RL_doFMADD_D =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1000011 &&
requestR[201:200] == 2'd1 ;
assign WILL_FIRE_RL_doFMADD_D = CAN_FIRE_RL_doFMADD_D ;
// rule RL_doFMSUB_D
assign CAN_FIRE_RL_doFMSUB_D =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1000111 &&
requestR[201:200] == 2'd1 ;
assign WILL_FIRE_RL_doFMSUB_D = CAN_FIRE_RL_doFMSUB_D ;
// rule RL_doFNMADD_D
assign CAN_FIRE_RL_doFNMADD_D =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1001111 &&
requestR[201:200] == 2'd1 ;
assign WILL_FIRE_RL_doFNMADD_D = CAN_FIRE_RL_doFNMADD_D ;
// rule RL_doFNMSUB_D
assign CAN_FIRE_RL_doFNMSUB_D =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1001011 &&
requestR[201:200] == 2'd1 ;
assign WILL_FIRE_RL_doFNMSUB_D = CAN_FIRE_RL_doFNMSUB_D ;
// rule RL_doFSGNJ_D
assign CAN_FIRE_RL_doFSGNJ_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h11 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFSGNJ_D = CAN_FIRE_RL_doFSGNJ_D ;
// rule RL_doFSGNJN_D
assign CAN_FIRE_RL_doFSGNJN_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h11 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFSGNJN_D = CAN_FIRE_RL_doFSGNJN_D ;
// rule RL_doFSGNJX_D
assign CAN_FIRE_RL_doFSGNJX_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h11 &&
requestR[194:192] == 3'h2 ;
assign WILL_FIRE_RL_doFSGNJX_D = CAN_FIRE_RL_doFSGNJX_D ;
// rule RL_doFCVT_D_W
assign CAN_FIRE_RL_doFCVT_D_W =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h69 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_D_W = CAN_FIRE_RL_doFCVT_D_W ;
// rule RL_doFCVT_D_WU
assign CAN_FIRE_RL_doFCVT_D_WU =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h69 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_D_WU = CAN_FIRE_RL_doFCVT_D_WU ;
// rule RL_doFCVT_W_D
assign CAN_FIRE_RL_doFCVT_W_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h61 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_W_D = CAN_FIRE_RL_doFCVT_W_D ;
// rule RL_doFCVT_WU_D
assign CAN_FIRE_RL_doFCVT_WU_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h61 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_WU_D = CAN_FIRE_RL_doFCVT_WU_D ;
// rule RL_doFCVT_S_D
assign CAN_FIRE_RL_doFCVT_S_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h20 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_S_D = CAN_FIRE_RL_doFCVT_S_D ;
// rule RL_doFCVT_D_S
assign CAN_FIRE_RL_doFCVT_D_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h21 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_D_S = CAN_FIRE_RL_doFCVT_D_S ;
// rule RL_doFMIN_D
assign CAN_FIRE_RL_doFMIN_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h15 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMIN_D = CAN_FIRE_RL_doFMIN_D ;
// rule RL_doFMAX_D
assign CAN_FIRE_RL_doFMAX_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h15 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFMAX_D = CAN_FIRE_RL_doFMAX_D ;
// rule RL_doFEQ_D
assign CAN_FIRE_RL_doFEQ_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h51 &&
requestR[194:192] == 3'h2 ;
assign WILL_FIRE_RL_doFEQ_D = CAN_FIRE_RL_doFEQ_D ;
// rule RL_doFLT_D
assign CAN_FIRE_RL_doFLT_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h51 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFLT_D = CAN_FIRE_RL_doFLT_D ;
// rule RL_doFLE_D
assign CAN_FIRE_RL_doFLE_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h51 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFLE_D = CAN_FIRE_RL_doFLE_D ;
// rule RL_doFMV_D_X
assign CAN_FIRE_RL_doFMV_D_X =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h79 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMV_D_X = CAN_FIRE_RL_doFMV_D_X ;
// rule RL_doFMV_X_D
assign CAN_FIRE_RL_doFMV_X_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h71 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMV_X_D = CAN_FIRE_RL_doFMV_X_D ;
// rule RL_doFCLASS_D
assign CAN_FIRE_RL_doFCLASS_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h71 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFCLASS_D = CAN_FIRE_RL_doFCLASS_D ;
// rule RL_rl_get_fpu_result
assign CAN_FIRE_RL_rl_get_fpu_result =
fpu$RDY_response_get && stateR == 2'd1 ;
assign WILL_FIRE_RL_rl_get_fpu_result = CAN_FIRE_RL_rl_get_fpu_result ;
// rule RL_rl_drive_fpu_result
assign CAN_FIRE_RL_rl_drive_fpu_result = stateR == 2'd2 ;
assign WILL_FIRE_RL_rl_drive_fpu_result = stateR == 2'd2 ;
// inputs to muxes for submodule ports
assign MUX_dw_result$wset_1__SEL_1 =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h10 &&
requestR[194:192] == 3'h1 ;
assign MUX_dw_result$wset_1__SEL_2 =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h10 &&
requestR[194:192] == 3'h0 ;
assign MUX_dw_result$wset_1__SEL_30 =
WILL_FIRE_RL_doFMV_X_D || WILL_FIRE_RL_doFMV_D_X ;
assign MUX_dw_result$wset_1__VAL_1 = { x__h1919, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_2 = { x__h1773, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_3 = { x__h2053, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_4 = { x__h2201, x__h8374 } ;
assign MUX_dw_result$wset_1__VAL_5 = { x__h8662, x__h14520 } ;
assign MUX_dw_result$wset_1__VAL_6 = { x__h14804, x__h16140 } ;
assign MUX_dw_result$wset_1__VAL_7 = { x__h16397, x__h16899 } ;
assign MUX_dw_result$wset_1__VAL_8 = { x__h17147, x__h19186 } ;
assign MUX_dw_result$wset_1__VAL_9 = { x__h19781, x__h19186 } ;
assign MUX_dw_result$wset_1__VAL_10 = { x__h22306, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_11 = { x__h22427, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_12 = { x__h22565, x__h19186 } ;
assign MUX_dw_result$wset_1__VAL_13 = { x__h24048, x__h24936 } ;
assign MUX_dw_result$wset_1__VAL_14 = { x__h25117, x__h24936 } ;
assign MUX_dw_result$wset_1__VAL_15 = { x__h26203, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_16 = { x__h27370, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_17 = { x__h27492, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_18 = { x__h27616, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_19 = { x__h27746, x__h37409 } ;
assign MUX_dw_result$wset_1__VAL_20 = { x__h37694, x__h47077 } ;
assign MUX_dw_result$wset_1__VAL_21 = { x__h47361, x__h48680 } ;
assign MUX_dw_result$wset_1__VAL_22 = { x__h48937, x__h49439 } ;
assign MUX_dw_result$wset_1__VAL_23 = { x__h49683, x__h97405 } ;
assign MUX_dw_result$wset_1__VAL_24 = { x__h98388, x__h139191 } ;
assign MUX_dw_result$wset_1__VAL_25 = { x__h140114, x__h143663 } ;
assign MUX_dw_result$wset_1__VAL_26 = { x__h144662, x__h143663 } ;
assign MUX_dw_result$wset_1__VAL_27 = { x__h149106, x__h143663 } ;
assign MUX_dw_result$wset_1__VAL_28 = { x__h151801, x__h153497 } ;
assign MUX_dw_result$wset_1__VAL_29 = { x__h153678, x__h153497 } ;
assign MUX_dw_result$wset_1__VAL_30 = { requestR[191:128], 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_31 = { x__h155805, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_32 =
{ x__h156455, fpu$response_get[4:0] } ;
assign MUX_fpu$request_put_1__VAL_1 =
{ 33'h1AAAAAAAA,
requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19,
33'h1AAAAAAAA,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28,
65'h0AAAAAAAAAAAAAAAA,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd0 } ;
assign MUX_fpu$request_put_1__VAL_2 =
{ 33'h1AAAAAAAA,
requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19,
33'h1AAAAAAAA,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28,
65'h0AAAAAAAAAAAAAAAA,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd1 } ;
assign MUX_fpu$request_put_1__VAL_3 =
{ 33'h1AAAAAAAA,
requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19,
33'h1AAAAAAAA,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28,
65'h0AAAAAAAAAAAAAAAA,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd2 } ;
assign MUX_fpu$request_put_1__VAL_4 =
{ 33'h1AAAAAAAA,
requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19,
33'h1AAAAAAAA,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28,
_1_CONCAT_DONTCARE_CONCAT_requestR_BITS_63_TO_3_ETC___d68,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd5 } ;
assign MUX_fpu$request_put_1__VAL_5 =
{ 33'h1AAAAAAAA,
requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19,
33'h1AAAAAAAA,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28,
_1_CONCAT_DONTCARE_CONCAT_requestR_BITS_63_TO_3_ETC___d68,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd6 } ;
assign MUX_fpu$request_put_1__VAL_6 =
{ 33'h1AAAAAAAA,
requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19,
33'h1AAAAAAAA,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28,
_1_CONCAT_DONTCARE_CONCAT_requestR_BITS_63_TO_3_ETC___d68,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd7 } ;
assign MUX_fpu$request_put_1__VAL_7 =
{ 33'h1AAAAAAAA,
requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19,
33'h1AAAAAAAA,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28,
_1_CONCAT_DONTCARE_CONCAT_requestR_BITS_63_TO_3_ETC___d68,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd8 } ;
assign MUX_fpu$request_put_1__VAL_8 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
65'h0AAAAAAAAAAAAAAAA,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd0 } ;
assign MUX_fpu$request_put_1__VAL_9 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
65'h0AAAAAAAAAAAAAAAA,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd1 } ;
assign MUX_fpu$request_put_1__VAL_10 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
65'h0AAAAAAAAAAAAAAAA,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd2 } ;
assign MUX_fpu$request_put_1__VAL_11 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
1'd0,
requestR[63:0],
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd5 } ;
assign MUX_fpu$request_put_1__VAL_12 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
1'd0,
requestR[63:0],
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd6 } ;
assign MUX_fpu$request_put_1__VAL_13 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
1'd0,
requestR[63:0],
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd7 } ;
assign MUX_fpu$request_put_1__VAL_14 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
1'd0,
requestR[63:0],
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd8 } ;
assign MUX_resultR$write_1__VAL_2 =
{ 1'd1, x__h156455, fpu$response_get[4:0] } ;
assign MUX_resultR$write_1__VAL_3 = { 1'd1, x__h155805, 5'd0 } ;
assign MUX_resultR$write_1__VAL_4 = { 1'd1, requestR[191:128], 5'd0 } ;
assign MUX_resultR$write_1__VAL_6 = { 1'd1, x__h153678, x__h153497 } ;
assign MUX_resultR$write_1__VAL_7 = { 1'd1, x__h151801, x__h153497 } ;
assign MUX_resultR$write_1__VAL_8 = { 1'd1, x__h149106, x__h143663 } ;
assign MUX_resultR$write_1__VAL_9 = { 1'd1, x__h144662, x__h143663 } ;
assign MUX_resultR$write_1__VAL_10 = { 1'd1, x__h140114, x__h143663 } ;
assign MUX_resultR$write_1__VAL_11 = { 1'd1, x__h98388, x__h139191 } ;
assign MUX_resultR$write_1__VAL_12 = { 1'd1, x__h49683, x__h97405 } ;
assign MUX_resultR$write_1__VAL_13 = { 1'd1, x__h48937, x__h49439 } ;
assign MUX_resultR$write_1__VAL_14 = { 1'd1, x__h47361, x__h48680 } ;
assign MUX_resultR$write_1__VAL_15 = { 1'd1, x__h37694, x__h47077 } ;
assign MUX_resultR$write_1__VAL_16 = { 1'd1, x__h27746, x__h37409 } ;
assign MUX_resultR$write_1__VAL_17 = { 1'd1, x__h27616, 5'd0 } ;
assign MUX_resultR$write_1__VAL_18 = { 1'd1, x__h27492, 5'd0 } ;
assign MUX_resultR$write_1__VAL_19 = { 1'd1, x__h27370, 5'd0 } ;
assign MUX_resultR$write_1__VAL_20 = { 1'd1, x__h26203, 5'd0 } ;
assign MUX_resultR$write_1__VAL_21 = { 1'd1, x__h25117, x__h24936 } ;
assign MUX_resultR$write_1__VAL_22 = { 1'd1, x__h24048, x__h24936 } ;
assign MUX_resultR$write_1__VAL_23 = { 1'd1, x__h22565, x__h19186 } ;
assign MUX_resultR$write_1__VAL_24 = { 1'd1, x__h22427, 5'd0 } ;
assign MUX_resultR$write_1__VAL_25 = { 1'd1, x__h22306, 5'd0 } ;
assign MUX_resultR$write_1__VAL_26 = { 1'd1, x__h19781, x__h19186 } ;
assign MUX_resultR$write_1__VAL_27 = { 1'd1, x__h17147, x__h19186 } ;
assign MUX_resultR$write_1__VAL_28 = { 1'd1, x__h16397, x__h16899 } ;
assign MUX_resultR$write_1__VAL_29 = { 1'd1, x__h14804, x__h16140 } ;
assign MUX_resultR$write_1__VAL_30 = { 1'd1, x__h8662, x__h14520 } ;
assign MUX_resultR$write_1__VAL_31 = { 1'd1, x__h2201, x__h8374 } ;
assign MUX_resultR$write_1__VAL_32 = { 1'd1, x__h2053, 5'd0 } ;
assign MUX_resultR$write_1__VAL_33 = { 1'd1, x__h1919, 5'd0 } ;
assign MUX_resultR$write_1__VAL_34 = { 1'd1, x__h1773, 5'd0 } ;
// inlined wires
assign dw_valid$wget = !WILL_FIRE_RL_rl_drive_fpu_result || resultR[69] ;
assign dw_valid$whas =
WILL_FIRE_RL_rl_drive_fpu_result ||
WILL_FIRE_RL_rl_get_fpu_result ||
WILL_FIRE_RL_doFCLASS_D ||
WILL_FIRE_RL_doFMV_X_D ||
WILL_FIRE_RL_doFMV_D_X ||
WILL_FIRE_RL_doFLE_D ||
WILL_FIRE_RL_doFLT_D ||
WILL_FIRE_RL_doFEQ_D ||
WILL_FIRE_RL_doFMAX_D ||
WILL_FIRE_RL_doFMIN_D ||
WILL_FIRE_RL_doFCVT_D_S ||
WILL_FIRE_RL_doFCVT_S_D ||
WILL_FIRE_RL_doFCVT_WU_D ||
WILL_FIRE_RL_doFCVT_W_D ||
WILL_FIRE_RL_doFCVT_D_WU ||
WILL_FIRE_RL_doFCVT_D_W ||
WILL_FIRE_RL_doFSGNJX_D ||
WILL_FIRE_RL_doFSGNJN_D ||
WILL_FIRE_RL_doFSGNJ_D ||
WILL_FIRE_RL_doFCLASS_S ||
WILL_FIRE_RL_doFLE_S ||
WILL_FIRE_RL_doFLT_S ||
WILL_FIRE_RL_doFEQ_S ||
WILL_FIRE_RL_doFMV_X_W ||
WILL_FIRE_RL_doFMV_W_X ||
WILL_FIRE_RL_doFMAX_S ||
WILL_FIRE_RL_doFMIN_S ||
WILL_FIRE_RL_doFCVT_WU_S ||
WILL_FIRE_RL_doFCVT_W_S ||
WILL_FIRE_RL_doFCVT_S_WU ||
WILL_FIRE_RL_doFCVT_S_W ||
WILL_FIRE_RL_doFSGNJX_S ||
WILL_FIRE_RL_doFSGNJN_S ||
WILL_FIRE_RL_doFSGNJ_S ;
always@(WILL_FIRE_RL_doFSGNJN_S or
MUX_dw_result$wset_1__VAL_1 or
WILL_FIRE_RL_doFSGNJ_S or
MUX_dw_result$wset_1__VAL_2 or
WILL_FIRE_RL_doFSGNJX_S or
MUX_dw_result$wset_1__VAL_3 or
WILL_FIRE_RL_doFCVT_S_W or
MUX_dw_result$wset_1__VAL_4 or
WILL_FIRE_RL_doFCVT_S_WU or
MUX_dw_result$wset_1__VAL_5 or
WILL_FIRE_RL_doFCVT_W_S or
MUX_dw_result$wset_1__VAL_6 or
WILL_FIRE_RL_doFCVT_WU_S or
MUX_dw_result$wset_1__VAL_7 or
WILL_FIRE_RL_doFMIN_S or
MUX_dw_result$wset_1__VAL_8 or
WILL_FIRE_RL_doFMAX_S or
MUX_dw_result$wset_1__VAL_9 or
WILL_FIRE_RL_doFMV_W_X or
MUX_dw_result$wset_1__VAL_10 or
WILL_FIRE_RL_doFMV_X_W or
MUX_dw_result$wset_1__VAL_11 or
WILL_FIRE_RL_doFEQ_S or
MUX_dw_result$wset_1__VAL_12 or
WILL_FIRE_RL_doFLT_S or
MUX_dw_result$wset_1__VAL_13 or
WILL_FIRE_RL_doFLE_S or
MUX_dw_result$wset_1__VAL_14 or
WILL_FIRE_RL_doFCLASS_S or
MUX_dw_result$wset_1__VAL_15 or
WILL_FIRE_RL_doFSGNJ_D or
MUX_dw_result$wset_1__VAL_16 or
WILL_FIRE_RL_doFSGNJN_D or
MUX_dw_result$wset_1__VAL_17 or
WILL_FIRE_RL_doFSGNJX_D or
MUX_dw_result$wset_1__VAL_18 or
WILL_FIRE_RL_doFCVT_D_W or
MUX_dw_result$wset_1__VAL_19 or
WILL_FIRE_RL_doFCVT_D_WU or
MUX_dw_result$wset_1__VAL_20 or
WILL_FIRE_RL_doFCVT_W_D or
MUX_dw_result$wset_1__VAL_21 or
WILL_FIRE_RL_doFCVT_WU_D or
MUX_dw_result$wset_1__VAL_22 or
WILL_FIRE_RL_doFCVT_S_D or
MUX_dw_result$wset_1__VAL_23 or
WILL_FIRE_RL_doFCVT_D_S or
MUX_dw_result$wset_1__VAL_24 or
WILL_FIRE_RL_doFMIN_D or
MUX_dw_result$wset_1__VAL_25 or
WILL_FIRE_RL_doFMAX_D or
MUX_dw_result$wset_1__VAL_26 or
WILL_FIRE_RL_doFEQ_D or
MUX_dw_result$wset_1__VAL_27 or
WILL_FIRE_RL_doFLT_D or
MUX_dw_result$wset_1__VAL_28 or
WILL_FIRE_RL_doFLE_D or
MUX_dw_result$wset_1__VAL_29 or
MUX_dw_result$wset_1__SEL_30 or
MUX_dw_result$wset_1__VAL_30 or
WILL_FIRE_RL_doFCLASS_D or
MUX_dw_result$wset_1__VAL_31 or
WILL_FIRE_RL_rl_get_fpu_result or
MUX_dw_result$wset_1__VAL_32 or
WILL_FIRE_RL_rl_drive_fpu_result or resultR)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_doFSGNJN_S: dw_result$wget = MUX_dw_result$wset_1__VAL_1;
WILL_FIRE_RL_doFSGNJ_S: dw_result$wget = MUX_dw_result$wset_1__VAL_2;
WILL_FIRE_RL_doFSGNJX_S: dw_result$wget = MUX_dw_result$wset_1__VAL_3;
WILL_FIRE_RL_doFCVT_S_W: dw_result$wget = MUX_dw_result$wset_1__VAL_4;
WILL_FIRE_RL_doFCVT_S_WU: dw_result$wget = MUX_dw_result$wset_1__VAL_5;
WILL_FIRE_RL_doFCVT_W_S: dw_result$wget = MUX_dw_result$wset_1__VAL_6;
WILL_FIRE_RL_doFCVT_WU_S: dw_result$wget = MUX_dw_result$wset_1__VAL_7;
WILL_FIRE_RL_doFMIN_S: dw_result$wget = MUX_dw_result$wset_1__VAL_8;
WILL_FIRE_RL_doFMAX_S: dw_result$wget = MUX_dw_result$wset_1__VAL_9;
WILL_FIRE_RL_doFMV_W_X: dw_result$wget = MUX_dw_result$wset_1__VAL_10;
WILL_FIRE_RL_doFMV_X_W: dw_result$wget = MUX_dw_result$wset_1__VAL_11;
WILL_FIRE_RL_doFEQ_S: dw_result$wget = MUX_dw_result$wset_1__VAL_12;
WILL_FIRE_RL_doFLT_S: dw_result$wget = MUX_dw_result$wset_1__VAL_13;
WILL_FIRE_RL_doFLE_S: dw_result$wget = MUX_dw_result$wset_1__VAL_14;
WILL_FIRE_RL_doFCLASS_S: dw_result$wget = MUX_dw_result$wset_1__VAL_15;
WILL_FIRE_RL_doFSGNJ_D: dw_result$wget = MUX_dw_result$wset_1__VAL_16;
WILL_FIRE_RL_doFSGNJN_D: dw_result$wget = MUX_dw_result$wset_1__VAL_17;
WILL_FIRE_RL_doFSGNJX_D: dw_result$wget = MUX_dw_result$wset_1__VAL_18;
WILL_FIRE_RL_doFCVT_D_W: dw_result$wget = MUX_dw_result$wset_1__VAL_19;
WILL_FIRE_RL_doFCVT_D_WU: dw_result$wget = MUX_dw_result$wset_1__VAL_20;
WILL_FIRE_RL_doFCVT_W_D: dw_result$wget = MUX_dw_result$wset_1__VAL_21;
WILL_FIRE_RL_doFCVT_WU_D: dw_result$wget = MUX_dw_result$wset_1__VAL_22;
WILL_FIRE_RL_doFCVT_S_D: dw_result$wget = MUX_dw_result$wset_1__VAL_23;
WILL_FIRE_RL_doFCVT_D_S: dw_result$wget = MUX_dw_result$wset_1__VAL_24;
WILL_FIRE_RL_doFMIN_D: dw_result$wget = MUX_dw_result$wset_1__VAL_25;
WILL_FIRE_RL_doFMAX_D: dw_result$wget = MUX_dw_result$wset_1__VAL_26;
WILL_FIRE_RL_doFEQ_D: dw_result$wget = MUX_dw_result$wset_1__VAL_27;
WILL_FIRE_RL_doFLT_D: dw_result$wget = MUX_dw_result$wset_1__VAL_28;
WILL_FIRE_RL_doFLE_D: dw_result$wget = MUX_dw_result$wset_1__VAL_29;
MUX_dw_result$wset_1__SEL_30:
dw_result$wget = MUX_dw_result$wset_1__VAL_30;
WILL_FIRE_RL_doFCLASS_D: dw_result$wget = MUX_dw_result$wset_1__VAL_31;
WILL_FIRE_RL_rl_get_fpu_result:
dw_result$wget = MUX_dw_result$wset_1__VAL_32;
WILL_FIRE_RL_rl_drive_fpu_result: dw_result$wget = resultR[68:0];
default: dw_result$wget =
69'h0AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
// register cfg_verbosity
assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign cfg_verbosity$EN = EN_set_verbosity ;
// register requestR
assign requestR$D_IN =
{ 1'd1,
req_opcode,
req_f7,
req_rs2,
req_rm,
req_v1,
req_v2,
req_v3 } ;
assign requestR$EN = EN_req ;
// register resultR
always@(EN_req or
WILL_FIRE_RL_rl_get_fpu_result or
MUX_resultR$write_1__VAL_2 or
WILL_FIRE_RL_doFCLASS_D or
MUX_resultR$write_1__VAL_3 or
WILL_FIRE_RL_doFMV_X_D or
MUX_resultR$write_1__VAL_4 or
WILL_FIRE_RL_doFMV_D_X or
WILL_FIRE_RL_doFLE_D or
MUX_resultR$write_1__VAL_6 or
WILL_FIRE_RL_doFLT_D or
MUX_resultR$write_1__VAL_7 or
WILL_FIRE_RL_doFEQ_D or
MUX_resultR$write_1__VAL_8 or
WILL_FIRE_RL_doFMAX_D or
MUX_resultR$write_1__VAL_9 or
WILL_FIRE_RL_doFMIN_D or
MUX_resultR$write_1__VAL_10 or
WILL_FIRE_RL_doFCVT_D_S or
MUX_resultR$write_1__VAL_11 or
WILL_FIRE_RL_doFCVT_S_D or
MUX_resultR$write_1__VAL_12 or
WILL_FIRE_RL_doFCVT_WU_D or
MUX_resultR$write_1__VAL_13 or
WILL_FIRE_RL_doFCVT_W_D or
MUX_resultR$write_1__VAL_14 or
WILL_FIRE_RL_doFCVT_D_WU or
MUX_resultR$write_1__VAL_15 or
WILL_FIRE_RL_doFCVT_D_W or
MUX_resultR$write_1__VAL_16 or
WILL_FIRE_RL_doFSGNJX_D or
MUX_resultR$write_1__VAL_17 or
WILL_FIRE_RL_doFSGNJN_D or
MUX_resultR$write_1__VAL_18 or
WILL_FIRE_RL_doFSGNJ_D or
MUX_resultR$write_1__VAL_19 or
WILL_FIRE_RL_doFCLASS_S or
MUX_resultR$write_1__VAL_20 or
WILL_FIRE_RL_doFLE_S or
MUX_resultR$write_1__VAL_21 or
WILL_FIRE_RL_doFLT_S or
MUX_resultR$write_1__VAL_22 or
WILL_FIRE_RL_doFEQ_S or
MUX_resultR$write_1__VAL_23 or
WILL_FIRE_RL_doFMV_X_W or
MUX_resultR$write_1__VAL_24 or
WILL_FIRE_RL_doFMV_W_X or
MUX_resultR$write_1__VAL_25 or
WILL_FIRE_RL_doFMAX_S or
MUX_resultR$write_1__VAL_26 or
WILL_FIRE_RL_doFMIN_S or
MUX_resultR$write_1__VAL_27 or
WILL_FIRE_RL_doFCVT_WU_S or
MUX_resultR$write_1__VAL_28 or
WILL_FIRE_RL_doFCVT_W_S or
MUX_resultR$write_1__VAL_29 or
WILL_FIRE_RL_doFCVT_S_WU or
MUX_resultR$write_1__VAL_30 or
WILL_FIRE_RL_doFCVT_S_W or
MUX_resultR$write_1__VAL_31 or
WILL_FIRE_RL_doFSGNJX_S or
MUX_resultR$write_1__VAL_32 or
WILL_FIRE_RL_doFSGNJN_S or
MUX_resultR$write_1__VAL_33 or
WILL_FIRE_RL_doFSGNJ_S or MUX_resultR$write_1__VAL_34)
case (1'b1)
EN_req: resultR$D_IN = 70'h0AAAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_get_fpu_result: resultR$D_IN = MUX_resultR$write_1__VAL_2;
WILL_FIRE_RL_doFCLASS_D: resultR$D_IN = MUX_resultR$write_1__VAL_3;
WILL_FIRE_RL_doFMV_X_D: resultR$D_IN = MUX_resultR$write_1__VAL_4;
WILL_FIRE_RL_doFMV_D_X: resultR$D_IN = MUX_resultR$write_1__VAL_4;
WILL_FIRE_RL_doFLE_D: resultR$D_IN = MUX_resultR$write_1__VAL_6;
WILL_FIRE_RL_doFLT_D: resultR$D_IN = MUX_resultR$write_1__VAL_7;
WILL_FIRE_RL_doFEQ_D: resultR$D_IN = MUX_resultR$write_1__VAL_8;
WILL_FIRE_RL_doFMAX_D: resultR$D_IN = MUX_resultR$write_1__VAL_9;
WILL_FIRE_RL_doFMIN_D: resultR$D_IN = MUX_resultR$write_1__VAL_10;
WILL_FIRE_RL_doFCVT_D_S: resultR$D_IN = MUX_resultR$write_1__VAL_11;
WILL_FIRE_RL_doFCVT_S_D: resultR$D_IN = MUX_resultR$write_1__VAL_12;
WILL_FIRE_RL_doFCVT_WU_D: resultR$D_IN = MUX_resultR$write_1__VAL_13;
WILL_FIRE_RL_doFCVT_W_D: resultR$D_IN = MUX_resultR$write_1__VAL_14;
WILL_FIRE_RL_doFCVT_D_WU: resultR$D_IN = MUX_resultR$write_1__VAL_15;
WILL_FIRE_RL_doFCVT_D_W: resultR$D_IN = MUX_resultR$write_1__VAL_16;
WILL_FIRE_RL_doFSGNJX_D: resultR$D_IN = MUX_resultR$write_1__VAL_17;
WILL_FIRE_RL_doFSGNJN_D: resultR$D_IN = MUX_resultR$write_1__VAL_18;
WILL_FIRE_RL_doFSGNJ_D: resultR$D_IN = MUX_resultR$write_1__VAL_19;
WILL_FIRE_RL_doFCLASS_S: resultR$D_IN = MUX_resultR$write_1__VAL_20;
WILL_FIRE_RL_doFLE_S: resultR$D_IN = MUX_resultR$write_1__VAL_21;
WILL_FIRE_RL_doFLT_S: resultR$D_IN = MUX_resultR$write_1__VAL_22;
WILL_FIRE_RL_doFEQ_S: resultR$D_IN = MUX_resultR$write_1__VAL_23;
WILL_FIRE_RL_doFMV_X_W: resultR$D_IN = MUX_resultR$write_1__VAL_24;
WILL_FIRE_RL_doFMV_W_X: resultR$D_IN = MUX_resultR$write_1__VAL_25;
WILL_FIRE_RL_doFMAX_S: resultR$D_IN = MUX_resultR$write_1__VAL_26;
WILL_FIRE_RL_doFMIN_S: resultR$D_IN = MUX_resultR$write_1__VAL_27;
WILL_FIRE_RL_doFCVT_WU_S: resultR$D_IN = MUX_resultR$write_1__VAL_28;
WILL_FIRE_RL_doFCVT_W_S: resultR$D_IN = MUX_resultR$write_1__VAL_29;
WILL_FIRE_RL_doFCVT_S_WU: resultR$D_IN = MUX_resultR$write_1__VAL_30;
WILL_FIRE_RL_doFCVT_S_W: resultR$D_IN = MUX_resultR$write_1__VAL_31;
WILL_FIRE_RL_doFSGNJX_S: resultR$D_IN = MUX_resultR$write_1__VAL_32;
WILL_FIRE_RL_doFSGNJN_S: resultR$D_IN = MUX_resultR$write_1__VAL_33;
WILL_FIRE_RL_doFSGNJ_S: resultR$D_IN = MUX_resultR$write_1__VAL_34;
default: resultR$D_IN = 70'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign resultR$EN =
EN_req || WILL_FIRE_RL_doFMV_X_D || WILL_FIRE_RL_doFMV_D_X ||
WILL_FIRE_RL_doFSGNJ_S ||
WILL_FIRE_RL_doFSGNJN_S ||
WILL_FIRE_RL_doFSGNJX_S ||
WILL_FIRE_RL_doFCVT_S_W ||
WILL_FIRE_RL_doFCVT_S_WU ||
WILL_FIRE_RL_doFCVT_W_S ||
WILL_FIRE_RL_doFCVT_WU_S ||
WILL_FIRE_RL_doFMIN_S ||
WILL_FIRE_RL_doFMAX_S ||
WILL_FIRE_RL_doFMV_W_X ||
WILL_FIRE_RL_doFMV_X_W ||
WILL_FIRE_RL_doFEQ_S ||
WILL_FIRE_RL_doFLT_S ||
WILL_FIRE_RL_doFLE_S ||
WILL_FIRE_RL_doFCLASS_S ||
WILL_FIRE_RL_doFSGNJ_D ||
WILL_FIRE_RL_doFSGNJN_D ||
WILL_FIRE_RL_doFSGNJX_D ||
WILL_FIRE_RL_doFCVT_D_W ||
WILL_FIRE_RL_doFCVT_D_WU ||
WILL_FIRE_RL_doFCVT_W_D ||
WILL_FIRE_RL_doFCVT_WU_D ||
WILL_FIRE_RL_doFCVT_S_D ||
WILL_FIRE_RL_doFCVT_D_S ||
WILL_FIRE_RL_doFMIN_D ||
WILL_FIRE_RL_doFMAX_D ||
WILL_FIRE_RL_doFEQ_D ||
WILL_FIRE_RL_doFLT_D ||
WILL_FIRE_RL_doFLE_D ||
WILL_FIRE_RL_doFCLASS_D ||
WILL_FIRE_RL_rl_get_fpu_result ;
// register stateR
always@(EN_req or
WILL_FIRE_RL_rl_get_fpu_result or
WILL_FIRE_RL_doFCLASS_D or
WILL_FIRE_RL_doFMV_X_D or
WILL_FIRE_RL_doFMV_D_X or
WILL_FIRE_RL_doFLE_D or
WILL_FIRE_RL_doFLT_D or
WILL_FIRE_RL_doFEQ_D or
WILL_FIRE_RL_doFMAX_D or
WILL_FIRE_RL_doFMIN_D or
WILL_FIRE_RL_doFCVT_D_S or
WILL_FIRE_RL_doFCVT_S_D or
WILL_FIRE_RL_doFCVT_WU_D or
WILL_FIRE_RL_doFCVT_W_D or
WILL_FIRE_RL_doFCVT_D_WU or
WILL_FIRE_RL_doFCVT_D_W or
WILL_FIRE_RL_doFSGNJX_D or
WILL_FIRE_RL_doFSGNJN_D or
WILL_FIRE_RL_doFSGNJ_D or
WILL_FIRE_RL_doFNMSUB_D or
WILL_FIRE_RL_doFNMADD_D or
WILL_FIRE_RL_doFMSUB_D or
WILL_FIRE_RL_doFMADD_D or
WILL_FIRE_RL_doFMUL_D or
WILL_FIRE_RL_doFSUB_D or
WILL_FIRE_RL_doFADD_D or
WILL_FIRE_RL_doFCLASS_S or
WILL_FIRE_RL_doFLE_S or
WILL_FIRE_RL_doFLT_S or
WILL_FIRE_RL_doFEQ_S or
WILL_FIRE_RL_doFMV_X_W or
WILL_FIRE_RL_doFMV_W_X or
WILL_FIRE_RL_doFMAX_S or
WILL_FIRE_RL_doFMIN_S or
WILL_FIRE_RL_doFCVT_WU_S or
WILL_FIRE_RL_doFCVT_W_S or
WILL_FIRE_RL_doFCVT_S_WU or
WILL_FIRE_RL_doFCVT_S_W or
WILL_FIRE_RL_doFSGNJX_S or
WILL_FIRE_RL_doFSGNJN_S or
WILL_FIRE_RL_doFSGNJ_S or
WILL_FIRE_RL_doFNMSUB_S or
WILL_FIRE_RL_doFNMADD_S or
WILL_FIRE_RL_doFMSUB_S or
WILL_FIRE_RL_doFMADD_S or
WILL_FIRE_RL_doFMUL_S or
WILL_FIRE_RL_doFSUB_S or WILL_FIRE_RL_doFADD_S)
case (1'b1)
EN_req: stateR$D_IN = 2'd0;
WILL_FIRE_RL_rl_get_fpu_result || WILL_FIRE_RL_doFCLASS_D ||
WILL_FIRE_RL_doFMV_X_D ||
WILL_FIRE_RL_doFMV_D_X ||
WILL_FIRE_RL_doFLE_D ||
WILL_FIRE_RL_doFLT_D ||
WILL_FIRE_RL_doFEQ_D ||
WILL_FIRE_RL_doFMAX_D ||
WILL_FIRE_RL_doFMIN_D ||
WILL_FIRE_RL_doFCVT_D_S ||
WILL_FIRE_RL_doFCVT_S_D ||
WILL_FIRE_RL_doFCVT_WU_D ||
WILL_FIRE_RL_doFCVT_W_D ||
WILL_FIRE_RL_doFCVT_D_WU ||
WILL_FIRE_RL_doFCVT_D_W ||
WILL_FIRE_RL_doFSGNJX_D ||
WILL_FIRE_RL_doFSGNJN_D ||
WILL_FIRE_RL_doFSGNJ_D:
stateR$D_IN = 2'd2;
WILL_FIRE_RL_doFNMSUB_D || WILL_FIRE_RL_doFNMADD_D ||
WILL_FIRE_RL_doFMSUB_D ||
WILL_FIRE_RL_doFMADD_D ||
WILL_FIRE_RL_doFMUL_D ||
WILL_FIRE_RL_doFSUB_D ||
WILL_FIRE_RL_doFADD_D:
stateR$D_IN = 2'd1;
WILL_FIRE_RL_doFCLASS_S || WILL_FIRE_RL_doFLE_S || WILL_FIRE_RL_doFLT_S ||
WILL_FIRE_RL_doFEQ_S ||
WILL_FIRE_RL_doFMV_X_W ||
WILL_FIRE_RL_doFMV_W_X ||
WILL_FIRE_RL_doFMAX_S ||
WILL_FIRE_RL_doFMIN_S ||
WILL_FIRE_RL_doFCVT_WU_S ||
WILL_FIRE_RL_doFCVT_W_S ||
WILL_FIRE_RL_doFCVT_S_WU ||
WILL_FIRE_RL_doFCVT_S_W ||
WILL_FIRE_RL_doFSGNJX_S ||
WILL_FIRE_RL_doFSGNJN_S ||
WILL_FIRE_RL_doFSGNJ_S:
stateR$D_IN = 2'd2;
WILL_FIRE_RL_doFNMSUB_S || WILL_FIRE_RL_doFNMADD_S ||
WILL_FIRE_RL_doFMSUB_S ||
WILL_FIRE_RL_doFMADD_S ||
WILL_FIRE_RL_doFMUL_S ||
WILL_FIRE_RL_doFSUB_S ||
WILL_FIRE_RL_doFADD_S:
stateR$D_IN = 2'd1;
default: stateR$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign stateR$EN =
EN_req || WILL_FIRE_RL_doFNMSUB_D || WILL_FIRE_RL_doFNMADD_D ||
WILL_FIRE_RL_doFMSUB_D ||
WILL_FIRE_RL_doFMADD_D ||
WILL_FIRE_RL_doFMUL_D ||
WILL_FIRE_RL_doFSUB_D ||
WILL_FIRE_RL_doFADD_D ||
WILL_FIRE_RL_doFNMSUB_S ||
WILL_FIRE_RL_doFNMADD_S ||
WILL_FIRE_RL_doFMSUB_S ||
WILL_FIRE_RL_doFMADD_S ||
WILL_FIRE_RL_doFMUL_S ||
WILL_FIRE_RL_doFSUB_S ||
WILL_FIRE_RL_doFADD_S ||
WILL_FIRE_RL_rl_get_fpu_result ||
WILL_FIRE_RL_doFCLASS_D ||
WILL_FIRE_RL_doFMV_X_D ||
WILL_FIRE_RL_doFMV_D_X ||
WILL_FIRE_RL_doFLE_D ||
WILL_FIRE_RL_doFLT_D ||
WILL_FIRE_RL_doFEQ_D ||
WILL_FIRE_RL_doFMAX_D ||
WILL_FIRE_RL_doFMIN_D ||
WILL_FIRE_RL_doFCVT_D_S ||
WILL_FIRE_RL_doFCVT_S_D ||
WILL_FIRE_RL_doFCVT_WU_D ||
WILL_FIRE_RL_doFCVT_W_D ||
WILL_FIRE_RL_doFCVT_D_WU ||
WILL_FIRE_RL_doFCVT_D_W ||
WILL_FIRE_RL_doFSGNJX_D ||
WILL_FIRE_RL_doFSGNJN_D ||
WILL_FIRE_RL_doFSGNJ_D ||
WILL_FIRE_RL_doFCLASS_S ||
WILL_FIRE_RL_doFLE_S ||
WILL_FIRE_RL_doFLT_S ||
WILL_FIRE_RL_doFEQ_S ||
WILL_FIRE_RL_doFMV_X_W ||
WILL_FIRE_RL_doFMV_W_X ||
WILL_FIRE_RL_doFMAX_S ||
WILL_FIRE_RL_doFMIN_S ||
WILL_FIRE_RL_doFCVT_WU_S ||
WILL_FIRE_RL_doFCVT_W_S ||
WILL_FIRE_RL_doFCVT_S_WU ||
WILL_FIRE_RL_doFCVT_S_W ||
WILL_FIRE_RL_doFSGNJX_S ||
WILL_FIRE_RL_doFSGNJN_S ||
WILL_FIRE_RL_doFSGNJ_S ;
// submodule fpu
always@(WILL_FIRE_RL_doFADD_S or
MUX_fpu$request_put_1__VAL_1 or
WILL_FIRE_RL_doFSUB_S or
MUX_fpu$request_put_1__VAL_2 or
WILL_FIRE_RL_doFMUL_S or
MUX_fpu$request_put_1__VAL_3 or
WILL_FIRE_RL_doFMADD_S or
MUX_fpu$request_put_1__VAL_4 or
WILL_FIRE_RL_doFMSUB_S or
MUX_fpu$request_put_1__VAL_5 or
WILL_FIRE_RL_doFNMADD_S or
MUX_fpu$request_put_1__VAL_6 or
WILL_FIRE_RL_doFNMSUB_S or
MUX_fpu$request_put_1__VAL_7 or
WILL_FIRE_RL_doFADD_D or
MUX_fpu$request_put_1__VAL_8 or
WILL_FIRE_RL_doFSUB_D or
MUX_fpu$request_put_1__VAL_9 or
WILL_FIRE_RL_doFMUL_D or
MUX_fpu$request_put_1__VAL_10 or
WILL_FIRE_RL_doFMADD_D or
MUX_fpu$request_put_1__VAL_11 or
WILL_FIRE_RL_doFMSUB_D or
MUX_fpu$request_put_1__VAL_12 or
WILL_FIRE_RL_doFNMADD_D or
MUX_fpu$request_put_1__VAL_13 or
WILL_FIRE_RL_doFNMSUB_D or MUX_fpu$request_put_1__VAL_14)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_doFADD_S: fpu$request_put = MUX_fpu$request_put_1__VAL_1;
WILL_FIRE_RL_doFSUB_S: fpu$request_put = MUX_fpu$request_put_1__VAL_2;
WILL_FIRE_RL_doFMUL_S: fpu$request_put = MUX_fpu$request_put_1__VAL_3;
WILL_FIRE_RL_doFMADD_S: fpu$request_put = MUX_fpu$request_put_1__VAL_4;
WILL_FIRE_RL_doFMSUB_S: fpu$request_put = MUX_fpu$request_put_1__VAL_5;
WILL_FIRE_RL_doFNMADD_S: fpu$request_put = MUX_fpu$request_put_1__VAL_6;
WILL_FIRE_RL_doFNMSUB_S: fpu$request_put = MUX_fpu$request_put_1__VAL_7;
WILL_FIRE_RL_doFADD_D: fpu$request_put = MUX_fpu$request_put_1__VAL_8;
WILL_FIRE_RL_doFSUB_D: fpu$request_put = MUX_fpu$request_put_1__VAL_9;
WILL_FIRE_RL_doFMUL_D: fpu$request_put = MUX_fpu$request_put_1__VAL_10;
WILL_FIRE_RL_doFMADD_D: fpu$request_put = MUX_fpu$request_put_1__VAL_11;
WILL_FIRE_RL_doFMSUB_D: fpu$request_put = MUX_fpu$request_put_1__VAL_12;
WILL_FIRE_RL_doFNMADD_D:
fpu$request_put = MUX_fpu$request_put_1__VAL_13;
WILL_FIRE_RL_doFNMSUB_D:
fpu$request_put = MUX_fpu$request_put_1__VAL_14;
default: fpu$request_put =
202'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fpu$EN_request_put =
WILL_FIRE_RL_doFADD_S || WILL_FIRE_RL_doFSUB_S ||
WILL_FIRE_RL_doFMUL_S ||
WILL_FIRE_RL_doFMADD_S ||
WILL_FIRE_RL_doFMSUB_S ||
WILL_FIRE_RL_doFNMADD_S ||
WILL_FIRE_RL_doFNMSUB_S ||
WILL_FIRE_RL_doFADD_D ||
WILL_FIRE_RL_doFSUB_D ||
WILL_FIRE_RL_doFMUL_D ||
WILL_FIRE_RL_doFMADD_D ||
WILL_FIRE_RL_doFMSUB_D ||
WILL_FIRE_RL_doFNMADD_D ||
WILL_FIRE_RL_doFNMSUB_D ;
assign fpu$EN_response_get = CAN_FIRE_RL_rl_get_fpu_result ;
// submodule frmFpuF
assign frmFpuF$D_IN = 1'b0 ;
assign frmFpuF$ENQ = 1'b0 ;
assign frmFpuF$DEQ = 1'b0 ;
assign frmFpuF$CLR = 1'b0 ;
// remaining internal signals
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_ETC__q60 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2076 ?
_theResult___snd__h69713 :
_theResult____h61543 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q97 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3396 ?
_theResult___snd__h128901 :
_theResult____h120602 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BIT_ETC__q65 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2560 ?
_theResult___snd__h87566 :
_theResult____h79267 ;
assign IF_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_E_ETC__q100 =
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3469 ?
_theResult___snd__h119254 :
_theResult___snd__h137653 ;
assign IF_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_E_ETC__q94 =
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3076 ?
_theResult___snd__h119254 :
57'd0 ;
assign IF_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_ETC__q62 =
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2238 ?
_theResult___snd__h78325 :
57'd0 ;
assign IF_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_ETC__q68 =
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2633 ?
_theResult___snd__h78325 :
_theResult___snd__h96202 ;
assign IF_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_ETC___d2820 =
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 ?
((_theResult___fst_exp__h69650 == 8'd255) ?
requestR[191] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1553_0b0_requestR_BIT_191_0b1_reques_ETC__q86 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87)) :
((_theResult___fst_exp__h78336 == 8'd255) ?
requestR[191] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard0288_0b0_requestR_BIT_191_0b1_reques_ETC__q88 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89)) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d1286 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1235 ?
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5772_0b0_requestR_BIT_159_0b1_reques_ETC__q35 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36) :
((x__h36517[10:0] == 11'd2047) ?
requestR[159] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard6502_0b0_requestR_BIT_159_0b1_reques_ETC__q37 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38)) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d1401 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1235 ?
guard__h35772 != 2'b0 :
x__h36517[10:0] != 11'd2047 && guard__h36502 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d325 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d264 ?
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard136_0b0_requestR_BIT_159_0b1_request_ETC__q8 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9) :
((x__h7681[7:0] == 8'd255) ?
requestR[159] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard666_0b0_requestR_BIT_159_0b1_request_ETC__q10 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11)) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d475 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d264 ?
guard__h7136 != 2'b0 :
x__h7681[7:0] != 8'd255 && guard__h7666 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THE_ETC___d1584 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1448 ?
guard__h45468 != 2'b0 :
x__h46212[10:0] != 11'd2047 && guard__h46197 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THE_ETC___d789 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d619 ?
guard__h13313 != 2'b0 :
x__h13854[7:0] != 8'd255 && guard__h13839 != 2'b0 ;
assign IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_TO_180__ETC___d2074 =
(_theResult____h61543[56] ?
6'd0 :
(_theResult____h61543[55] ?
6'd1 :
(_theResult____h61543[54] ?
6'd2 :
(_theResult____h61543[53] ?
6'd3 :
(_theResult____h61543[52] ?
6'd4 :
(_theResult____h61543[51] ?
6'd5 :
(_theResult____h61543[50] ?
6'd6 :
(_theResult____h61543[49] ?
6'd7 :
(_theResult____h61543[48] ?
6'd8 :
(_theResult____h61543[47] ?
6'd9 :
(_theResult____h61543[46] ?
6'd10 :
(_theResult____h61543[45] ?
6'd11 :
(_theResult____h61543[44] ?
6'd12 :
(_theResult____h61543[43] ?
6'd13 :
(_theResult____h61543[42] ?
6'd14 :
(_theResult____h61543[41] ?
6'd15 :
(_theResult____h61543[40] ?
6'd16 :
(_theResult____h61543[39] ?
6'd17 :
(_theResult____h61543[38] ?
6'd18 :
(_theResult____h61543[37] ?
6'd19 :
(_theResult____h61543[36] ?
6'd20 :
(_theResult____h61543[35] ?
6'd21 :
(_theResult____h61543[34] ?
6'd22 :
(_theResult____h61543[33] ?
6'd23 :
(_theResult____h61543[32] ?
6'd24 :
(_theResult____h61543[31] ?
6'd25 :
(_theResult____h61543[30] ?
6'd26 :
(_theResult____h61543[29] ?
6'd27 :
(_theResult____h61543[28] ?
6'd28 :
(_theResult____h61543[27] ?
6'd29 :
(_theResult____h61543[26] ?
6'd30 :
(_theResult____h61543[25] ?
6'd31 :
(_theResult____h61543[24] ?
6'd32 :
(_theResult____h61543[23] ?
6'd33 :
(_theResult____h61543[22] ?
6'd34 :
(_theResult____h61543[21] ?
6'd35 :
(_theResult____h61543[20] ?
6'd36 :
(_theResult____h61543[19] ?
6'd37 :
(_theResult____h61543[18] ?
6'd38 :
(_theResult____h61543[17] ?
6'd39 :
(_theResult____h61543[16] ?
6'd40 :
(_theResult____h61543[15] ?
6'd41 :
(_theResult____h61543[14] ?
6'd42 :
(_theResult____h61543[13] ?
6'd43 :
(_theResult____h61543[12] ?
6'd44 :
(_theResult____h61543[11] ?
6'd45 :
(_theResult____h61543[10] ?
6'd46 :
(_theResult____h61543[9] ?
6'd47 :
(_theResult____h61543[8] ?
6'd48 :
(_theResult____h61543[7] ?
6'd49 :
(_theResult____h61543[6] ?
6'd50 :
(_theResult____h61543[5] ?
6'd51 :
(_theResult____h61543[4] ?
6'd52 :
(_theResult____h61543[3] ?
6'd53 :
(_theResult____h61543[2] ?
6'd54 :
(_theResult____h61543[1] ?
6'd55 :
(_theResult____h61543[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_191_TO__ETC___d3394 =
(_theResult____h120602[56] ?
6'd0 :
(_theResult____h120602[55] ?
6'd1 :
(_theResult____h120602[54] ?
6'd2 :
(_theResult____h120602[53] ?
6'd3 :
(_theResult____h120602[52] ?
6'd4 :
(_theResult____h120602[51] ?
6'd5 :
(_theResult____h120602[50] ?
6'd6 :
(_theResult____h120602[49] ?
6'd7 :
(_theResult____h120602[48] ?
6'd8 :
(_theResult____h120602[47] ?
6'd9 :
(_theResult____h120602[46] ?
6'd10 :
(_theResult____h120602[45] ?
6'd11 :
(_theResult____h120602[44] ?
6'd12 :
(_theResult____h120602[43] ?
6'd13 :
(_theResult____h120602[42] ?
6'd14 :
(_theResult____h120602[41] ?
6'd15 :
(_theResult____h120602[40] ?
6'd16 :
(_theResult____h120602[39] ?
6'd17 :
(_theResult____h120602[38] ?
6'd18 :
(_theResult____h120602[37] ?
6'd19 :
(_theResult____h120602[36] ?
6'd20 :
(_theResult____h120602[35] ?
6'd21 :
(_theResult____h120602[34] ?
6'd22 :
(_theResult____h120602[33] ?
6'd23 :
(_theResult____h120602[32] ?
6'd24 :
(_theResult____h120602[31] ?
6'd25 :
(_theResult____h120602[30] ?
6'd26 :
(_theResult____h120602[29] ?
6'd27 :
(_theResult____h120602[28] ?
6'd28 :
(_theResult____h120602[27] ?
6'd29 :
(_theResult____h120602[26] ?
6'd30 :
(_theResult____h120602[25] ?
6'd31 :
(_theResult____h120602[24] ?
6'd32 :
(_theResult____h120602[23] ?
6'd33 :
(_theResult____h120602[22] ?
6'd34 :
(_theResult____h120602[21] ?
6'd35 :
(_theResult____h120602[20] ?
6'd36 :
(_theResult____h120602[19] ?
6'd37 :
(_theResult____h120602[18] ?
6'd38 :
(_theResult____h120602[17] ?
6'd39 :
(_theResult____h120602[16] ?
6'd40 :
(_theResult____h120602[15] ?
6'd41 :
(_theResult____h120602[14] ?
6'd42 :
(_theResult____h120602[13] ?
6'd43 :
(_theResult____h120602[12] ?
6'd44 :
(_theResult____h120602[11] ?
6'd45 :
(_theResult____h120602[10] ?
6'd46 :
(_theResult____h120602[9] ?
6'd47 :
(_theResult____h120602[8] ?
6'd48 :
(_theResult____h120602[7] ?
6'd49 :
(_theResult____h120602[6] ?
6'd50 :
(_theResult____h120602[5] ?
6'd51 :
(_theResult____h120602[4] ?
6'd52 :
(_theResult____h120602[3] ?
6'd53 :
(_theResult____h120602[2] ?
6'd54 :
(_theResult____h120602[1] ?
6'd55 :
(_theResult____h120602[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_requestR_BITS_190_TO_180_ETC___d2558 =
(_theResult____h79267[56] ?
6'd0 :
(_theResult____h79267[55] ?
6'd1 :
(_theResult____h79267[54] ?
6'd2 :
(_theResult____h79267[53] ?
6'd3 :
(_theResult____h79267[52] ?
6'd4 :
(_theResult____h79267[51] ?
6'd5 :
(_theResult____h79267[50] ?
6'd6 :
(_theResult____h79267[49] ?
6'd7 :
(_theResult____h79267[48] ?
6'd8 :
(_theResult____h79267[47] ?
6'd9 :
(_theResult____h79267[46] ?
6'd10 :
(_theResult____h79267[45] ?
6'd11 :
(_theResult____h79267[44] ?
6'd12 :
(_theResult____h79267[43] ?
6'd13 :
(_theResult____h79267[42] ?
6'd14 :
(_theResult____h79267[41] ?
6'd15 :
(_theResult____h79267[40] ?
6'd16 :
(_theResult____h79267[39] ?
6'd17 :
(_theResult____h79267[38] ?
6'd18 :
(_theResult____h79267[37] ?
6'd19 :
(_theResult____h79267[36] ?
6'd20 :
(_theResult____h79267[35] ?
6'd21 :
(_theResult____h79267[34] ?
6'd22 :
(_theResult____h79267[33] ?
6'd23 :
(_theResult____h79267[32] ?
6'd24 :
(_theResult____h79267[31] ?
6'd25 :
(_theResult____h79267[30] ?
6'd26 :
(_theResult____h79267[29] ?
6'd27 :
(_theResult____h79267[28] ?
6'd28 :
(_theResult____h79267[27] ?
6'd29 :
(_theResult____h79267[26] ?
6'd30 :
(_theResult____h79267[25] ?
6'd31 :
(_theResult____h79267[24] ?
6'd32 :
(_theResult____h79267[23] ?
6'd33 :
(_theResult____h79267[22] ?
6'd34 :
(_theResult____h79267[21] ?
6'd35 :
(_theResult____h79267[20] ?
6'd36 :
(_theResult____h79267[19] ?
6'd37 :
(_theResult____h79267[18] ?
6'd38 :
(_theResult____h79267[17] ?
6'd39 :
(_theResult____h79267[16] ?
6'd40 :
(_theResult____h79267[15] ?
6'd41 :
(_theResult____h79267[14] ?
6'd42 :
(_theResult____h79267[13] ?
6'd43 :
(_theResult____h79267[12] ?
6'd44 :
(_theResult____h79267[11] ?
6'd45 :
(_theResult____h79267[10] ?
6'd46 :
(_theResult____h79267[9] ?
6'd47 :
(_theResult____h79267[8] ?
6'd48 :
(_theResult____h79267[7] ?
6'd49 :
(_theResult____h79267[6] ?
6'd50 :
(_theResult____h79267[5] ?
6'd51 :
(_theResult____h79267[4] ?
6'd52 :
(_theResult____h79267[3] ?
6'd53 :
(_theResult____h79267[2] ?
6'd54 :
(_theResult____h79267[1] ?
6'd55 :
(_theResult____h79267[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_191__ETC___d3638 =
(_theResult___fst_exp__h128838 == 11'd2047) ?
requestR[191:160] == 32'hFFFFFFFF && requestR[159] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard20612_0b0_requestR_BITS_191_TO_160_E_ETC__q110 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2133 =
(guard__h61553 == 2'b0 || requestR[191]) ?
_theResult___fst_exp__h69650 :
_theResult___exp__h70176 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2135 =
(guard__h61553 == 2'b0) ?
_theResult___fst_exp__h69650 :
(requestR[191] ?
_theResult___exp__h70176 :
_theResult___fst_exp__h69650) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2720 =
(guard__h61553 == 2'b0 || requestR[191]) ?
sfdin__h69644[56:34] :
_theResult___sfd__h70177 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2722 =
(guard__h61553 == 2'b0) ?
sfdin__h69644[56:34] :
(requestR[191] ?
_theResult___sfd__h70177 :
sfdin__h69644[56:34]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3453 =
(guard__h120612 == 2'b0 ||
requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___fst_exp__h128838 :
_theResult___exp__h129567 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3455 =
(guard__h120612 == 2'b0) ?
_theResult___fst_exp__h128838 :
((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___exp__h129567 :
_theResult___fst_exp__h128838) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3582 =
(guard__h120612 == 2'b0 ||
requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
sfdin__h128832[56:5] :
_theResult___sfd__h129568 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3584 =
(guard__h120612 == 2'b0) ?
sfdin__h128832[56:5] :
((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___sfd__h129568 :
sfdin__h128832[56:5]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2617 =
(guard__h79277 == 2'b0 || requestR[191]) ?
_theResult___fst_exp__h87503 :
_theResult___exp__h88029 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2619 =
(guard__h79277 == 2'b0) ?
_theResult___fst_exp__h87503 :
(requestR[191] ?
_theResult___exp__h88029 :
_theResult___fst_exp__h87503) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2766 =
(guard__h79277 == 2'b0 || requestR[191]) ?
sfdin__h87497[56:34] :
_theResult___sfd__h88030 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2768 =
(guard__h79277 == 2'b0) ?
sfdin__h87497[56:34] :
(requestR[191] ?
_theResult___sfd__h88030 :
sfdin__h87497[56:34]) ;
assign IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3128 =
(guard__h111304 == 2'b0 ||
requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___fst_exp__h119265 :
_theResult___exp__h119920 ;
assign IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3130 =
(guard__h111304 == 2'b0) ?
_theResult___fst_exp__h119265 :
((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___exp__h119920 :
_theResult___fst_exp__h119265) ;
assign IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3522 =
(guard__h129679 == 2'b0 ||
requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___fst_exp__h137669 :
_theResult___exp__h138349 ;
assign IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3524 =
(guard__h129679 == 2'b0) ?
_theResult___fst_exp__h137669 :
((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___exp__h138349 :
_theResult___fst_exp__h137669) ;
assign IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3555 =
(guard__h111304 == 2'b0 ||
requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___snd__h119216[56:5] :
_theResult___sfd__h119921 ;
assign IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3557 =
(guard__h111304 == 2'b0) ?
_theResult___snd__h119216[56:5] :
((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___sfd__h119921 :
_theResult___snd__h119216[56:5]) ;
assign IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3601 =
(guard__h129679 == 2'b0 ||
requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___snd__h137615[56:5] :
_theResult___sfd__h138350 ;
assign IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3603 =
(guard__h129679 == 2'b0) ?
_theResult___snd__h137615[56:5] :
((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___sfd__h138350 :
_theResult___snd__h137615[56:5]) ;
assign IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2290 =
(guard__h70288 == 2'b0 || requestR[191]) ?
_theResult___fst_exp__h78336 :
_theResult___exp__h78788 ;
assign IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2292 =
(guard__h70288 == 2'b0) ?
_theResult___fst_exp__h78336 :
(requestR[191] ?
_theResult___exp__h78788 :
_theResult___fst_exp__h78336) ;
assign IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2686 =
(guard__h88141 == 2'b0 || requestR[191]) ?
_theResult___fst_exp__h96218 :
_theResult___exp__h96695 ;
assign IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2688 =
(guard__h88141 == 2'b0) ?
_theResult___fst_exp__h96218 :
(requestR[191] ?
_theResult___exp__h96695 :
_theResult___fst_exp__h96218) ;
assign IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2739 =
(guard__h70288 == 2'b0 || requestR[191]) ?
_theResult___snd__h78287[56:34] :
_theResult___sfd__h78789 ;
assign IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2741 =
(guard__h70288 == 2'b0) ?
_theResult___snd__h78287[56:34] :
(requestR[191] ?
_theResult___sfd__h78789 :
_theResult___snd__h78287[56:34]) ;
assign IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2785 =
(guard__h88141 == 2'b0 || requestR[191]) ?
_theResult___snd__h96164[56:34] :
_theResult___sfd__h96696 ;
assign IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2787 =
(guard__h88141 == 2'b0) ?
_theResult___snd__h96164[56:34] :
(requestR[191] ?
_theResult___sfd__h96696 :
_theResult___snd__h96164[56:34]) ;
assign IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3646 =
(_theResult___fst_exp__h137669 == 11'd2047) ?
requestR[191:160] == 32'hFFFFFFFF && requestR[159] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard29679_0b0_requestR_BITS_191_TO_160_E_ETC__q112 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113) ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1307 =
(guard__h35772 == 2'b0) ?
11'd0 :
(requestR[159] ? _theResult___exp__h36388 : 11'd0) ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1333 =
(guard__h36502 == 2'b0 || requestR[159]) ?
x__h36517[10:0] :
_theResult___exp__h37144 ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1335 =
(guard__h36502 == 2'b0) ?
x__h36517[10:0] :
(requestR[159] ? _theResult___exp__h37144 : x__h36517[10:0]) ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1356 =
(guard__h35772 == 2'b0 || requestR[159]) ?
sfd___3__h35762[54:3] :
_theResult___sfd__h36389 ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1358 =
(guard__h35772 == 2'b0) ?
sfd___3__h35762[54:3] :
(requestR[159] ?
_theResult___sfd__h36389 :
sfd___3__h35762[54:3]) ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1374 =
(guard__h36502 == 2'b0 || requestR[159]) ?
sfd___3__h35762[53:2] :
_theResult___sfd__h37145 ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1376 =
(guard__h36502 == 2'b0) ?
sfd___3__h35762[53:2] :
(requestR[159] ?
_theResult___sfd__h37145 :
sfd___3__h35762[53:2]) ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d347 =
(guard__h7136 == 2'b0) ?
8'd0 :
(requestR[159] ? _theResult___exp__h7552 : 8'd0) ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d373 =
(guard__h7666 == 2'b0 || requestR[159]) ?
x__h7681[7:0] :
_theResult___exp__h8105 ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d375 =
(guard__h7666 == 2'b0) ?
x__h7681[7:0] :
(requestR[159] ? _theResult___exp__h8105 : x__h7681[7:0]) ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d396 =
(guard__h7136 == 2'b0 || requestR[159]) ?
sfd___3__h7126[31:9] :
_theResult___sfd__h7553 ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d398 =
(guard__h7136 == 2'b0) ?
sfd___3__h7126[31:9] :
(requestR[159] ?
_theResult___sfd__h7553 :
sfd___3__h7126[31:9]) ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d414 =
(guard__h7666 == 2'b0 || requestR[159]) ?
sfd___3__h7126[30:8] :
_theResult___sfd__h8106 ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d416 =
(guard__h7666 == 2'b0) ?
sfd___3__h7126[30:8] :
(requestR[159] ?
_theResult___sfd__h8106 :
sfd___3__h7126[30:8]) ;
assign IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1031 =
(sV2_exp__h918 == 8'd255 && sV2_sfd__h919[22] ||
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1000) ?
{ requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } :
(IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_T_ETC___d1004 ?
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28 :
IF_NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d1029) ;
assign IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1035 =
(sV2_exp__h918 == 8'd255 && sV2_sfd__h919 != 23'd0 &&
!sV2_sfd__h919[22]) ?
res__h18062 :
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1034 ;
assign IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1045 =
IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_T_ETC___d1004 ?
{ requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } :
IF_NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d1044 ;
assign IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1047 =
(sV2_exp__h918 == 8'd255 && sV2_sfd__h919[22]) ?
{ requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } :
(IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1000 ?
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28 :
IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1045) ;
assign IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1051 =
(sV2_exp__h918 == 8'd255 && sV2_sfd__h919 != 23'd0 &&
!sV2_sfd__h919[22]) ?
res__h18062 :
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1050 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1032 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816[22]) ?
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28 :
IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1031 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1034 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816[22] &&
sV2_exp__h918 == 8'd255 &&
sV2_sfd__h919[22]) ?
64'hFFFFFFFF7FC00000 :
{ 32'hFFFFFFFF,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1032 } ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1036 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 &&
!sV1_sfd__h816[22]) ?
res__h17825 :
IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1035 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1048 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816[22]) ?
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28 :
IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1047 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1050 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816[22] &&
sV2_exp__h918 == 8'd255 &&
sV2_sfd__h919[22]) ?
64'hFFFFFFFF7FC00000 :
{ 32'hFFFFFFFF,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1048 } ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1052 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 &&
!sV1_sfd__h816[22]) ?
res__h17825 :
IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1051 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1122 =
(sV1_exp__h815 == 8'd0 && sV1_sfd__h816 == 23'd0) ?
res___1__h26467 :
((sV1_exp__h815 == 8'd0) ? res___1__h26486 : res__h26502) ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1123 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 == 23'd0) ?
res___1__h26457 :
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1122 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3074 =
((sV1_exp__h815 == 8'd0) ?
(sV1_sfd__h816[22] ?
6'd2 :
(sV1_sfd__h816[21] ?
6'd3 :
(sV1_sfd__h816[20] ?
6'd4 :
(sV1_sfd__h816[19] ?
6'd5 :
(sV1_sfd__h816[18] ?
6'd6 :
(sV1_sfd__h816[17] ?
6'd7 :
(sV1_sfd__h816[16] ?
6'd8 :
(sV1_sfd__h816[15] ?
6'd9 :
(sV1_sfd__h816[14] ?
6'd10 :
(sV1_sfd__h816[13] ?
6'd11 :
(sV1_sfd__h816[12] ?
6'd12 :
(sV1_sfd__h816[11] ?
6'd13 :
(sV1_sfd__h816[10] ?
6'd14 :
(sV1_sfd__h816[9] ?
6'd15 :
(sV1_sfd__h816[8] ?
6'd16 :
(sV1_sfd__h816[7] ?
6'd17 :
(sV1_sfd__h816[6] ?
6'd18 :
(sV1_sfd__h816[5] ?
6'd19 :
(sV1_sfd__h816[4] ?
6'd20 :
(sV1_sfd__h816[3] ?
6'd21 :
(sV1_sfd__h816[2] ?
6'd22 :
(sV1_sfd__h816[1] ?
6'd23 :
(sV1_sfd__h816[0] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3614 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0) ?
_theResult___snd_fst_sfd__h100339 :
_theResult___fst_sfd__h138466 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3650 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 ||
(sV1_exp__h815 == 8'd255 || sV1_exp__h815 == 8'd0) &&
sV1_sfd__h816 == 23'd0) ?
requestR[191:160] == 32'hFFFFFFFF && requestR[159] :
((sV1_exp__h815 == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_ETC___d3630 :
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3648) ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3685 =
(sV1_exp__h815 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 &&
!_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 &&
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3664[4] :
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 &&
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3681[4] ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3688 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0) ?
sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 &&
!sV1_sfd__h816[22] :
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 != 23'd0) &&
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3685 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3695 =
(sV1_exp__h815 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 &&
!_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 &&
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3664[3] :
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 &&
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3681[3] ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3709 =
(sV1_exp__h815 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 ||
!_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 &&
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3664[2] :
!SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 ||
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3707 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3721 =
(sV1_exp__h815 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 &&
(_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 ||
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3664[1]) :
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 &&
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3719 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3733 =
(sV1_exp__h815 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 ||
!_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 &&
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3664[0] :
!SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 ||
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3731 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d886 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 == 23'd0) ?
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d815 :
((sV1_exp__h815 == 8'd0 && sV1_sfd__h816 == 23'd0) ?
32'd0 :
IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d884) ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d946 =
(sV1_exp__h815 == 8'd0 && sV1_sfd__h816 == 23'd0) ?
32'd0 :
(NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d917[19] ?
32'hFFFFFFFF :
IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d944) ;
assign IF_IF_requestR_BIT_159_6_THEN_NEG_requestR_BIT_ETC___d1227 =
sfd__h2222[31] ?
6'd0 :
(sfd__h2222[30] ?
6'd1 :
(sfd__h2222[29] ?
6'd2 :
(sfd__h2222[28] ?
6'd3 :
(sfd__h2222[27] ?
6'd4 :
(sfd__h2222[26] ?
6'd5 :
(sfd__h2222[25] ?
6'd6 :
(sfd__h2222[24] ?
6'd7 :
(sfd__h2222[23] ?
6'd8 :
(sfd__h2222[22] ?
6'd9 :
(sfd__h2222[21] ?
6'd10 :
(sfd__h2222[20] ?
6'd11 :
(sfd__h2222[19] ?
6'd12 :
(sfd__h2222[18] ?
6'd13 :
(sfd__h2222[17] ?
6'd14 :
(sfd__h2222[16] ?
6'd15 :
(sfd__h2222[15] ?
6'd16 :
(sfd__h2222[14] ?
6'd17 :
(sfd__h2222[13] ?
6'd18 :
(sfd__h2222[12] ?
6'd19 :
(sfd__h2222[11] ?
6'd20 :
(sfd__h2222[10] ?
6'd21 :
(sfd__h2222[9] ?
6'd22 :
(sfd__h2222[8] ?
6'd23 :
(sfd__h2222[7] ?
6'd24 :
(sfd__h2222[6] ?
6'd25 :
(sfd__h2222[5] ?
6'd26 :
(sfd__h2222[4] ?
6'd27 :
(sfd__h2222[3] ?
6'd28 :
(sfd__h2222[2] ?
6'd29 :
(sfd__h2222[1] ?
6'd30 :
(sfd__h2222[0] ?
6'd31 :
6'd55))))))))))))))))))))))))))))))) ;
assign IF_IF_requestR_BIT_159_6_THEN_NEG_requestR_BIT_ETC___d255 =
sfd__h2222[31] ?
6'd0 :
(sfd__h2222[30] ?
6'd1 :
(sfd__h2222[29] ?
6'd2 :
(sfd__h2222[28] ?
6'd3 :
(sfd__h2222[27] ?
6'd4 :
(sfd__h2222[26] ?
6'd5 :
(sfd__h2222[25] ?
6'd6 :
(sfd__h2222[24] ?
6'd7 :
(sfd__h2222[23] ?
6'd8 :
(sfd__h2222[22] ?
6'd9 :
(sfd__h2222[21] ?
6'd10 :
(sfd__h2222[20] ?
6'd11 :
(sfd__h2222[19] ?
6'd12 :
(sfd__h2222[18] ?
6'd13 :
(sfd__h2222[17] ?
6'd14 :
(sfd__h2222[16] ?
6'd15 :
(sfd__h2222[15] ?
6'd16 :
(sfd__h2222[14] ?
6'd17 :
(sfd__h2222[13] ?
6'd18 :
(sfd__h2222[12] ?
6'd19 :
(sfd__h2222[11] ?
6'd20 :
(sfd__h2222[10] ?
6'd21 :
(sfd__h2222[9] ?
6'd22 :
(sfd__h2222[8] ?
6'd23 :
(sfd__h2222[7] ?
6'd24 :
(sfd__h2222[6] ?
6'd25 :
(sfd__h2222[5] ?
6'd26 :
(sfd__h2222[4] ?
6'd27 :
(sfd__h2222[3] ?
6'd28 :
(sfd__h2222[2] ?
6'd29 :
(sfd__h2222[1] ?
6'd30 :
(sfd__h2222[0] ?
6'd31 :
6'd32))))))))))))))))))))))))))))))) ;
assign IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d882 =
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d855 ?
(IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d876 ?
((x__h15726[56:25] == 32'h7FFFFFFF) ?
x__h15726[56:25] :
x__h15726[56:25] + 32'd1) :
x__h15726[56:25]) :
32'd0 ;
assign IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d884 =
(NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d820 ==
20'd1048545) ?
((_theResult_____2__h14985[32:31] == 2'b11) ?
_theResult_____2__h14985[31:0] :
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d815) :
(NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d853[19] ?
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d815 :
IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d882) ;
assign IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d908 =
(NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d820 ==
20'd1048545) ?
_theResult_____2__h14985[32:31] == 2'b11 &&
guard__h14983 != 2'd0 :
!NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d853[19] &&
(!NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d855 ||
guard__h15537 != 2'd0) ;
assign IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d944 =
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d919 ?
(IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d938 ?
((x__h16821[56:25] == 32'hFFFFFFFF) ?
x__h16821[56:25] :
x__h16821[56:25] + 32'd1) :
x__h16821[56:25]) :
32'd0 ;
assign IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1673 =
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1646 ?
(IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1667 ?
((x__h48283[85:54] == 32'h7FFFFFFF) ?
x__h48283[85:54] :
x__h48283[85:54] + 32'd1) :
x__h48283[85:54]) :
32'd0 ;
assign IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1675 =
(NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1611 ==
24'd16777185) ?
((_theResult_____2__h47542[32:31] == 2'b11) ?
_theResult_____2__h47542[31:0] :
IF_requestR_BIT_191_186_THEN_2147483648_ELSE_2_ETC___d1606) :
(NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1644[23] ?
IF_requestR_BIT_191_186_THEN_2147483648_ELSE_2_ETC___d1606 :
IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1673) ;
assign IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1699 =
(NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1611 ==
24'd16777185) ?
_theResult_____2__h47542[32:31] == 2'b11 &&
guard__h47540 != 2'd0 :
!NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1644[23] &&
(!NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1646 ||
guard__h48094 != 2'd0) ;
assign IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1735 =
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1710 ?
(IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1729 ?
((x__h49361[85:54] == 32'hFFFFFFFF) ?
x__h49361[85:54] :
x__h49361[85:54] + 32'd1) :
x__h49361[85:54]) :
32'd0 ;
assign IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_15_ETC___d1287 =
(!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1231 ||
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1233) ?
requestR[159] :
IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d1286 ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_ETC___d3630 =
(!_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 ||
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 ||
_theResult___fst_exp__h119265 == 11'd2047) ?
requestR[191:160] == 32'hFFFFFFFF && requestR[159] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard11304_0b0_requestR_BITS_191_TO_160_E_ETC__q108 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109) ;
assign IF_NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d1029 =
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1028 ?
{ requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } :
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28 ;
assign IF_NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d1044 =
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1028 ?
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28 :
{ requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } ;
assign IF_NOT_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1024 =
(requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ?
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1013 ||
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1014 &&
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1015 :
!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1018 ||
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1014 &&
!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1020 ;
assign IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3468 =
((SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q96[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q99[10],
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q99 }) -
12'd3074 ;
assign IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3648 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 ?
(SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 ?
IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_191__ETC___d3638 :
IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3646) :
requestR[191:160] == 32'hFFFFFFFF && requestR[159] ;
assign IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3707 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3681[2] :
_theResult___fst_exp__h138450 == 11'd2047 &&
_theResult___fst_sfd__h138451 == 52'd0 ;
assign IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3719 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3681[1] :
_theResult___fst_exp__h137669 == 11'd0 &&
guard__h129679 != 2'b0 ;
assign IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3731 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3681[0] :
_theResult___fst_exp__h137669 != 11'd2047 &&
guard__h129679 != 2'b0 ;
assign IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2632 =
((SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q64[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q67[7],
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q67 }) -
9'd386 ;
assign IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2838 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 ?
((_theResult___fst_exp__h87503 == 8'd255) ?
requestR[191] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard9277_0b0_requestR_BIT_191_0b1_reques_ETC__q90 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91)) :
((_theResult___fst_exp__h96218 == 8'd255) ?
requestR[191] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard8141_0b0_requestR_BIT_191_0b1_reques_ETC__q92 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93)) ;
assign IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2916 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2887[2] :
_theResult___fst_exp__h96796 == 8'd255 &&
_theResult___fst_sfd__h96797 == 23'd0 ;
assign IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2929 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2887[1] :
_theResult___fst_exp__h96218 == 8'd0 && guard__h88141 != 2'b0 ;
assign IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2942 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2887[0] :
_theResult___fst_exp__h96218 != 8'd255 &&
guard__h88141 != 2'b0 ;
assign IF_requestR_BITS_126_TO_116_745_EQ_2047_746_AN_ETC___d3793 =
(requestR[126:116] == 11'd2047 && requestR[115] ||
requestR_BITS_190_TO_180_596_EQ_0_607_AND_requ_ETC___d3762) ?
requestR[191:128] :
(requestR_BITS_126_TO_116_745_EQ_0_759_AND_requ_ETC___d3766 ?
requestR[127:64] :
res__h143531) ;
assign IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_T_ETC___d1004 =
sV2_exp__h918 == 8'd0 && sV2_sfd__h919 == 23'd0 &&
requestR[127:96] == 32'hFFFFFFFF &&
requestR[95] &&
sV1_exp__h815 == 8'd0 &&
sV1_sfd__h816 == 23'd0 &&
(requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ;
assign IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d1384 =
(requestR[159:128] == 32'd0 ||
!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1231 ||
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1233) ?
52'd0 :
_theResult___snd_fst_sfd__h37248 ;
assign IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d1567 =
(requestR[159:128] == 32'd0 ||
!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1446 ||
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1447) ?
52'd0 :
_theResult___snd_fst_sfd__h46942 ;
assign IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d385 =
(requestR[159:128] == 32'd0 ||
!sfd__h2222[31] && !sfd__h2222[30] && !sfd__h2222[29] &&
!sfd__h2222[28] &&
!sfd__h2222[27] &&
!sfd__h2222[26] &&
!sfd__h2222[25] &&
!sfd__h2222[24] &&
!sfd__h2222[23] &&
!sfd__h2222[22] &&
!sfd__h2222[21] &&
!sfd__h2222[20] &&
!sfd__h2222[19] &&
!sfd__h2222[18] &&
!sfd__h2222[17] &&
!sfd__h2222[16] &&
!sfd__h2222[15] &&
!sfd__h2222[14] &&
!sfd__h2222[13] &&
!sfd__h2222[12] &&
!sfd__h2222[11] &&
!sfd__h2222[10] &&
!sfd__h2222[9] &&
!sfd__h2222[8] &&
!sfd__h2222[7] &&
!sfd__h2222[6] &&
!sfd__h2222[5] &&
!sfd__h2222[4] &&
!sfd__h2222[3] &&
!sfd__h2222[2] &&
!sfd__h2222[1] &&
!sfd__h2222[0]) ?
8'd0 :
_theResult___snd_fst_exp__h8214 ;
assign IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d703 =
(requestR[159:128] == 32'd0 ||
!requestR[159] &&
NOT_requestR_BIT_158_88_89_AND_NOT_requestR_BI_ETC___d579) ?
8'd0 :
_theResult___snd_fst_exp__h14386 ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d1737 =
(requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ?
32'd0 :
(NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1708[23] ?
32'hFFFFFFFF :
IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1735) ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d3807 =
requestR_BITS_190_TO_180_596_EQ_0_607_AND_requ_ETC___d3762 ?
requestR[127:64] :
(requestR_BITS_126_TO_116_745_EQ_0_759_AND_requ_ETC___d3766 ?
requestR[191:128] :
res__h148079) ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d3878 =
(requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ?
res___1__h156271 :
((requestR[190:180] == 11'd0) ?
res___1__h156290 :
res__h156306) ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2236 =
((requestR[190:180] == 11'd0) ?
(requestR[179] ?
6'd2 :
(requestR[178] ?
6'd3 :
(requestR[177] ?
6'd4 :
(requestR[176] ?
6'd5 :
(requestR[175] ?
6'd6 :
(requestR[174] ?
6'd7 :
(requestR[173] ?
6'd8 :
(requestR[172] ?
6'd9 :
(requestR[171] ?
6'd10 :
(requestR[170] ?
6'd11 :
(requestR[169] ?
6'd12 :
(requestR[168] ?
6'd13 :
(requestR[167] ?
6'd14 :
(requestR[166] ?
6'd15 :
(requestR[165] ?
6'd16 :
(requestR[164] ?
6'd17 :
(requestR[163] ?
6'd18 :
(requestR[162] ?
6'd19 :
(requestR[161] ?
6'd20 :
(requestR[160] ?
6'd21 :
(requestR[159] ?
6'd22 :
(requestR[158] ?
6'd23 :
(requestR[157] ?
6'd24 :
(requestR[156] ?
6'd25 :
(requestR[155] ?
6'd26 :
(requestR[154] ?
6'd27 :
(requestR[153] ?
6'd28 :
(requestR[152] ?
6'd29 :
(requestR[151] ?
6'd30 :
(requestR[150] ?
6'd31 :
(requestR[149] ?
6'd32 :
(requestR[148] ?
6'd33 :
(requestR[147] ?
6'd34 :
(requestR[146] ?
6'd35 :
(requestR[145] ?
6'd36 :
(requestR[144] ?
6'd37 :
(requestR[143] ?
6'd38 :
(requestR[142] ?
6'd39 :
(requestR[141] ?
6'd40 :
(requestR[140] ?
6'd41 :
(requestR[139] ?
6'd42 :
(requestR[138] ?
6'd43 :
(requestR[137] ?
6'd44 :
(requestR[136] ?
6'd45 :
(requestR[135] ?
6'd46 :
(requestR[134] ?
6'd47 :
(requestR[133] ?
6'd48 :
(requestR[132] ?
6'd49 :
(requestR[131] ?
6'd50 :
(requestR[130] ?
6'd51 :
(requestR[129] ?
6'd52 :
(requestR[128] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2840 =
(requestR[190:180] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 ?
IF_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_ETC___d2820 :
requestR[191]) :
(SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 ?
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2838 :
requestR[191]) ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2891 =
(requestR[190:180] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2873 :
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 &&
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2887[4] ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2902 =
(requestR[190:180] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2898 :
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 &&
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2887[3] ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2918 =
(requestR[190:180] == 11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_76_ETC___d2910 :
!SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 ||
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2916 ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2931 =
(requestR[190:180] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2925 :
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 &&
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2929 ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2944 =
(requestR[190:180] == 11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_76_ETC___d2938 :
!SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 ||
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2942 ;
assign IF_requestR_BITS_190_TO_180_596_EQ_2047_597_AN_ETC___d1677 =
(requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0) ?
IF_requestR_BIT_191_186_THEN_2147483648_ELSE_2_ETC___d1606 :
((requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ?
32'd0 :
IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1675) ;
assign IF_requestR_BITS_190_TO_180_596_EQ_2047_597_AN_ETC___d2798 =
(requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ?
_theResult___snd_fst_sfd__h53867 :
_theResult___fst_sfd__h96812 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1000 =
sV1_exp__h815 == 8'd0 && sV1_sfd__h816 == 23'd0 &&
requestR[191:160] == 32'hFFFFFFFF &&
requestR[159] &&
sV2_exp__h918 == 8'd0 &&
sV2_sfd__h919 == 23'd0 &&
(requestR[127:96] != 32'hFFFFFFFF || !requestR[95]) ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1013 =
sV1_exp__h815 < sV2_exp__h918 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1014 =
sV1_exp__h815 == sV2_exp__h918 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1015 =
sV1_sfd__h816 < sV2_sfd__h919 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1018 =
sV1_exp__h815 <= sV2_exp__h918 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1020 =
sV1_sfd__h816 <= sV2_sfd__h919 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1038 =
sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 &&
!sV1_sfd__h816[22] ||
sV2_exp__h918 == 8'd255 && sV2_sfd__h919 != 23'd0 &&
!sV2_sfd__h919[22] ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1075 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1038 ||
sV1_exp__h815 == 8'd255 && sV1_sfd__h816[22] ||
sV2_exp__h918 == 8'd255 && sV2_sfd__h919[22] ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1086 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1018 &&
(!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1014 ||
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1020) &&
!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1013 &&
(!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1014 ||
!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1015) ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1090 =
sV1_exp__h815 == 8'd0 && sV1_sfd__h816 == 23'd0 &&
sV2_exp__h918 == 8'd0 &&
sV2_sfd__h919 == 23'd0 ||
NOT_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_ETC___d1089 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 =
(requestR[191:160] == 32'hFFFFFFFF) ?
requestR[158:128] :
31'h7FC00000 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d814 =
sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 ||
(requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) &&
sV1_exp__h815 == 8'd255 &&
sV1_sfd__h816 == 23'd0 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d815 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
32'h80000000 :
32'h7FFFFFFF ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d818 =
sV1_exp__h815 - 8'd127 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
-b__h15050 :
b__h15050 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d948 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
32'd0 :
((sV1_exp__h815 == 8'd255 && sV1_sfd__h816 == 23'd0) ?
32'hFFFFFFFF :
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d946) ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d956 =
sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 ||
sV1_exp__h815 == 8'd255 && sV1_sfd__h816 == 23'd0 ||
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
(NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d917[19] ||
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d919 &&
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d938 &&
x__h16821[56:25] == 32'hFFFFFFFF) ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d967 =
{ IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d956,
3'd0,
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 != 23'd0) &&
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d961 } ==
5'd0 ||
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d956 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d990 =
sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 &&
!sV1_sfd__h816[22] &&
sV2_exp__h918 == 8'd255 &&
sV2_sfd__h919 != 23'd0 &&
!sV2_sfd__h919[22] ;
assign IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1635 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h47540 == 2'b10) ?
IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618[53] :
guard__h47540 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h47540 != 2'd0 :
requestR[194:192] == 3'h1 &&
IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618[85] &&
guard__h47540 != 2'd0) ;
assign IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1667 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h48094 == 2'b10) ?
x__h48283[54] :
guard__h48094 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h48094 != 2'd0 :
requestR[194:192] == 3'h1 && x__h48283[85] &&
guard__h48094 != 2'd0) ;
assign IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1729 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h49140 == 2'b10) ?
x__h49361[54] :
guard__h49140 == 2'b11) :
requestR[194:192] == 3'h3 && guard__h49140 != 2'd0 ;
assign IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d844 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h14983 == 2'b10) ?
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827[24] :
guard__h14983 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h14983 != 2'd0 :
requestR[194:192] == 3'h1 &&
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827[56] &&
guard__h14983 != 2'd0) ;
assign IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d876 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h15537 == 2'b10) ?
x__h15726[25] :
guard__h15537 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h15537 != 2'd0 :
requestR[194:192] == 3'h1 && x__h15726[56] &&
guard__h15537 != 2'd0) ;
assign IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d938 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h16600 == 2'b10) ?
x__h16821[25] :
guard__h16600 == 2'b11) :
requestR[194:192] == 3'h3 && guard__h16600 != 2'd0 ;
assign IF_requestR_BIT_159_6_THEN_0_ELSE_IF_requestR__ETC___d1442 =
requestR[159] ?
6'd0 :
(requestR[158] ?
6'd1 :
(requestR[157] ?
6'd2 :
(requestR[156] ?
6'd3 :
(requestR[155] ?
6'd4 :
(requestR[154] ?
6'd5 :
(requestR[153] ?
6'd6 :
(requestR[152] ?
6'd7 :
(requestR[151] ?
6'd8 :
(requestR[150] ?
6'd9 :
(requestR[149] ?
6'd10 :
(requestR[148] ?
6'd11 :
(requestR[147] ?
6'd12 :
(requestR[146] ?
6'd13 :
(requestR[145] ?
6'd14 :
(requestR[144] ?
6'd15 :
(requestR[143] ?
6'd16 :
(requestR[142] ?
6'd17 :
(requestR[141] ?
6'd18 :
(requestR[140] ?
6'd19 :
(requestR[139] ?
6'd20 :
(requestR[138] ?
6'd21 :
(requestR[137] ?
6'd22 :
(requestR[136] ?
6'd23 :
(requestR[135] ?
6'd24 :
(requestR[134] ?
6'd25 :
(requestR[133] ?
6'd26 :
(requestR[132] ?
6'd27 :
(requestR[131] ?
6'd28 :
(requestR[130] ?
6'd29 :
(requestR[129] ?
6'd30 :
(requestR[128] ?
6'd31 :
6'd55))))))))))))))))))))))))))))))) ;
assign IF_requestR_BIT_159_6_THEN_0_ELSE_IF_requestR__ETC___d613 =
requestR[159] ?
6'd0 :
(requestR[158] ?
6'd1 :
(requestR[157] ?
6'd2 :
(requestR[156] ?
6'd3 :
(requestR[155] ?
6'd4 :
(requestR[154] ?
6'd5 :
(requestR[153] ?
6'd6 :
(requestR[152] ?
6'd7 :
(requestR[151] ?
6'd8 :
(requestR[150] ?
6'd9 :
(requestR[149] ?
6'd10 :
(requestR[148] ?
6'd11 :
(requestR[147] ?
6'd12 :
(requestR[146] ?
6'd13 :
(requestR[145] ?
6'd14 :
(requestR[144] ?
6'd15 :
(requestR[143] ?
6'd16 :
(requestR[142] ?
6'd17 :
(requestR[141] ?
6'd18 :
(requestR[140] ?
6'd19 :
(requestR[139] ?
6'd20 :
(requestR[138] ?
6'd21 :
(requestR[137] ?
6'd22 :
(requestR[136] ?
6'd23 :
(requestR[135] ?
6'd24 :
(requestR[134] ?
6'd25 :
(requestR[133] ?
6'd26 :
(requestR[132] ?
6'd27 :
(requestR[131] ?
6'd28 :
(requestR[130] ?
6'd29 :
(requestR[129] ?
6'd30 :
(requestR[128] ?
6'd31 :
6'd32))))))))))))))))))))))))))))))) ;
assign IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d466 =
(sfd__h2222[31] || sfd__h2222[30] || sfd__h2222[29] ||
sfd__h2222[28] ||
sfd__h2222[27] ||
sfd__h2222[26] ||
sfd__h2222[25] ||
sfd__h2222[24] ||
sfd__h2222[23] ||
sfd__h2222[22] ||
sfd__h2222[21] ||
sfd__h2222[20] ||
sfd__h2222[19] ||
sfd__h2222[18] ||
sfd__h2222[17] ||
sfd__h2222[16] ||
sfd__h2222[15] ||
sfd__h2222[14] ||
sfd__h2222[13] ||
sfd__h2222[12] ||
sfd__h2222[11] ||
sfd__h2222[10] ||
sfd__h2222[9] ||
sfd__h2222[8] ||
sfd__h2222[7] ||
sfd__h2222[6] ||
sfd__h2222[5] ||
sfd__h2222[4] ||
sfd__h2222[3] ||
sfd__h2222[2] ||
sfd__h2222[1] ||
sfd__h2222[0]) &&
(!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d259 ||
!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d261 &&
!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d264 &&
_theResult___fst_exp__h8205 == 8'd255 &&
_theResult___fst_sfd__h8206 == 23'd0) ;
assign IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d469 =
(sfd__h2222[31] || sfd__h2222[30] || sfd__h2222[29] ||
sfd__h2222[28] ||
sfd__h2222[27] ||
sfd__h2222[26] ||
sfd__h2222[25] ||
sfd__h2222[24] ||
sfd__h2222[23] ||
sfd__h2222[22] ||
sfd__h2222[21] ||
sfd__h2222[20] ||
sfd__h2222[19] ||
sfd__h2222[18] ||
sfd__h2222[17] ||
sfd__h2222[16] ||
sfd__h2222[15] ||
sfd__h2222[14] ||
sfd__h2222[13] ||
sfd__h2222[12] ||
sfd__h2222[11] ||
sfd__h2222[10] ||
sfd__h2222[9] ||
sfd__h2222[8] ||
sfd__h2222[7] ||
sfd__h2222[6] ||
sfd__h2222[5] ||
sfd__h2222[4] ||
sfd__h2222[3] ||
sfd__h2222[2] ||
sfd__h2222[1] ||
sfd__h2222[0]) &&
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d259 &&
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d261 ;
assign IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d478 =
(sfd__h2222[31] || sfd__h2222[30] || sfd__h2222[29] ||
sfd__h2222[28] ||
sfd__h2222[27] ||
sfd__h2222[26] ||
sfd__h2222[25] ||
sfd__h2222[24] ||
sfd__h2222[23] ||
sfd__h2222[22] ||
sfd__h2222[21] ||
sfd__h2222[20] ||
sfd__h2222[19] ||
sfd__h2222[18] ||
sfd__h2222[17] ||
sfd__h2222[16] ||
sfd__h2222[15] ||
sfd__h2222[14] ||
sfd__h2222[13] ||
sfd__h2222[12] ||
sfd__h2222[11] ||
sfd__h2222[10] ||
sfd__h2222[9] ||
sfd__h2222[8] ||
sfd__h2222[7] ||
sfd__h2222[6] ||
sfd__h2222[5] ||
sfd__h2222[4] ||
sfd__h2222[3] ||
sfd__h2222[2] ||
sfd__h2222[1] ||
sfd__h2222[0]) &&
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d259 &&
!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d261 &&
IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d475 ;
assign IF_requestR_BIT_191_186_THEN_2147483648_ELSE_2_ETC___d1606 =
requestR[191] ? 32'h80000000 : 32'h7FFFFFFF ;
assign IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618 =
requestR[191] ? -b__h47607 : b__h47607 ;
assign IF_requestR_BIT_191_186_THEN_NOT_requestR_BITS_ETC___d3786 =
requestR[191] ?
!requestR_BITS_190_TO_180_596_ULE_requestR_BITS_ETC___d3775 ||
requestR_BITS_190_TO_180_596_EQ_requestR_BITS__ETC___d3777 &&
!requestR_BITS_179_TO_128_598_ULE_requestR_BITS_ETC___d3778 :
requestR_BITS_190_TO_180_596_ULT_requestR_BITS_ETC___d3782 ||
requestR_BITS_190_TO_180_596_EQ_requestR_BITS__ETC___d3777 &&
requestR_BITS_179_TO_128_598_ULT_requestR_BITS_ETC___d3783 ;
assign IF_sfd___3126_BIT_7_THEN_2_ELSE_0__q7 =
sfd___3__h7126[7] ? 2'd2 : 2'd0 ;
assign IF_sfd___3126_BIT_8_THEN_2_ELSE_0__q6 =
sfd___3__h7126[8] ? 2'd2 : 2'd0 ;
assign IF_sfd___33303_BIT_7_THEN_2_ELSE_0__q21 =
sfd___3__h13303[7] ? 2'd2 : 2'd0 ;
assign IF_sfd___33303_BIT_8_THEN_2_ELSE_0__q20 =
sfd___3__h13303[8] ? 2'd2 : 2'd0 ;
assign IF_sfd___35458_BIT_1_THEN_2_ELSE_0__q48 =
sfd___3__h45458[1] ? 2'd2 : 2'd0 ;
assign IF_sfd___35458_BIT_2_THEN_2_ELSE_0__q47 =
sfd___3__h45458[2] ? 2'd2 : 2'd0 ;
assign IF_sfd___35762_BIT_1_THEN_2_ELSE_0__q34 =
sfd___3__h35762[1] ? 2'd2 : 2'd0 ;
assign IF_sfd___35762_BIT_2_THEN_2_ELSE_0__q33 =
sfd___3__h35762[2] ? 2'd2 : 2'd0 ;
assign IF_sfdin28832_BIT_4_THEN_2_ELSE_0__q98 =
sfdin__h128832[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin7497_BIT_33_THEN_2_ELSE_0__q66 =
sfdin__h87497[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin9644_BIT_33_THEN_2_ELSE_0__q61 =
sfdin__h69644[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd19216_BIT_4_THEN_2_ELSE_0__q95 =
_theResult___snd__h119216[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd37615_BIT_4_THEN_2_ELSE_0__q101 =
_theResult___snd__h137615[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd6164_BIT_33_THEN_2_ELSE_0__q69 =
_theResult___snd__h96164[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd8287_BIT_33_THEN_2_ELSE_0__q63 =
_theResult___snd__h78287[33] ? 2'd2 : 2'd0 ;
assign IF_x5726_BIT_24_THEN_2_ELSE_0__q31 = x__h15726[24] ? 2'd2 : 2'd0 ;
assign IF_x6821_BIT_24_THEN_2_ELSE_0__q32 = x__h16821[24] ? 2'd2 : 2'd0 ;
assign IF_x8283_BIT_53_THEN_2_ELSE_0__q58 = x__h48283[53] ? 2'd2 : 2'd0 ;
assign IF_x9361_BIT_53_THEN_2_ELSE_0__q59 = x__h49361[53] ? 2'd2 : 2'd0 ;
assign NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d820 =
-{ {12{IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d818[7]}},
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d818 } ;
assign NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d852 =
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d820 +
20'd32 ;
assign NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d853 =
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d852 -
20'd2 ;
assign NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d855 =
(NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d853 ^
20'h80000) <=
20'd524320 ;
assign NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d917 =
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d852 -
20'd1 ;
assign NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d919 =
(NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d917 ^
20'h80000) <=
20'd524320 ;
assign NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1611 =
-{ {13{requestR_BITS_190_TO_180_596_MINUS_1023___d1609[10]}},
requestR_BITS_190_TO_180_596_MINUS_1023___d1609 } ;
assign NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1643 =
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1611 +
24'd32 ;
assign NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1644 =
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1643 -
24'd2 ;
assign NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1646 =
(NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1644 ^
24'h800000) <=
24'd8388640 ;
assign NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1708 =
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1643 -
24'd1 ;
assign NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1710 =
(NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1708 ^
24'h800000) <=
24'd8388640 ;
assign NOT_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_76_ETC___d2910 =
!_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 ||
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2858[2] :
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2870[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_76_ETC___d2938 =
!_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 ||
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2858[0] :
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2870[0]) ;
assign NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1027 =
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0 ||
sV2_exp__h918 != 8'd0 ||
sV2_sfd__h919 != 23'd0) &&
requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_AND_ETC___d1026 ;
assign NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1028 =
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV2_exp__h918 != 8'd255 || sV2_sfd__h919 == 23'd0) &&
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1027 ;
assign NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1085 =
!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1013 &&
(!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1014 ||
!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1015) &&
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1018 &&
(!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1014 ||
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1020) ;
assign NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1091 =
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV2_exp__h918 != 8'd255 || sV2_sfd__h919 == 23'd0) &&
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1090 ;
assign NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1109 =
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV2_exp__h918 != 8'd255 || sV2_sfd__h919 == 23'd0) &&
(requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_AND_ETC___d1026 ||
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1090) ;
assign NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d3047 =
!sV1_sfd__h816[21] && !sV1_sfd__h816[20] && !sV1_sfd__h816[19] &&
!sV1_sfd__h816[18] &&
!sV1_sfd__h816[17] &&
!sV1_sfd__h816[16] &&
!sV1_sfd__h816[15] &&
!sV1_sfd__h816[14] &&
!sV1_sfd__h816[13] &&
!sV1_sfd__h816[12] &&
!sV1_sfd__h816[11] &&
!sV1_sfd__h816[10] &&
!sV1_sfd__h816[9] &&
!sV1_sfd__h816[8] &&
!sV1_sfd__h816[7] &&
!sV1_sfd__h816[6] &&
!sV1_sfd__h816[5] &&
!sV1_sfd__h816[4] &&
!sV1_sfd__h816[3] &&
!sV1_sfd__h816[2] &&
!sV1_sfd__h816[1] &&
!sV1_sfd__h816[0] ;
assign NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d897 =
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
((NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d820 ==
20'd1048545) ?
_theResult_____2__h14985[32:31] != 2'b11 :
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d853[19] ||
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d855 &&
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d876 &&
x__h15726[56:25] == 32'h7FFFFFFF) ;
assign NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d961 =
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
!NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d917[19] &&
(!NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d919 ||
guard__h16600 != 2'd0) ;
assign NOT_IF_requestR_BIT_159_6_THEN_NEG_requestR_BI_ETC___d263 =
!sfd__h2222[31] && !sfd__h2222[30] && !sfd__h2222[29] &&
!sfd__h2222[28] &&
!sfd__h2222[27] &&
!sfd__h2222[26] &&
!sfd__h2222[25] &&
!sfd__h2222[24] &&
!sfd__h2222[23] &&
!sfd__h2222[22] &&
!sfd__h2222[21] &&
!sfd__h2222[20] &&
!sfd__h2222[19] &&
!sfd__h2222[18] &&
!sfd__h2222[17] &&
!sfd__h2222[16] &&
!sfd__h2222[15] &&
!sfd__h2222[14] &&
!sfd__h2222[13] &&
!sfd__h2222[12] &&
!sfd__h2222[11] &&
!sfd__h2222[10] &&
!sfd__h2222[9] &&
!sfd__h2222[8] &&
!sfd__h2222[7] &&
!sfd__h2222[6] &&
!sfd__h2222[5] &&
!sfd__h2222[4] &&
!sfd__h2222[3] &&
!sfd__h2222[2] &&
!sfd__h2222[1] &&
!sfd__h2222[0] ||
!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d259 ||
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d261 ;
assign NOT_requestR_BITS_159_TO_128_24_EQ_0_25_26_AND_ETC___d781 =
requestR[159:128] != 32'd0 &&
(requestR[159] ||
requestR_BIT_158_88_OR_requestR_BIT_157_90_OR__ETC___d770) &&
(!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d617 ||
!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d618 &&
!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d619 &&
_theResult___fst_exp__h14377 == 8'd255 &&
_theResult___fst_sfd__h14378 == 23'd0) ;
assign NOT_requestR_BITS_190_TO_180_596_EQ_0_607_613__ETC___d1688 =
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
((NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1611 ==
24'd16777185) ?
_theResult_____2__h47542[32:31] != 2'b11 :
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1644[23] ||
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1646 &&
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1667 &&
x__h48283[85:54] == 32'h7FFFFFFF) ;
assign NOT_requestR_BITS_190_TO_180_596_EQ_0_607_613__ETC___d1752 =
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
!NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1708[23] &&
(!NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1710 ||
guard__h49140 != 2'd0) ;
assign NOT_requestR_BITS_190_TO_180_596_EQ_2047_597_6_ETC___d3790 =
(requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) &&
(requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) &&
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0 ||
requestR[126:116] != 11'd0 ||
requestR[115:64] != 52'd0) &&
(requestR[191] && !requestR[127] ||
(requestR[191] || !requestR[127]) &&
IF_requestR_BIT_191_186_THEN_NOT_requestR_BITS_ETC___d3786) ;
assign NOT_requestR_BITS_190_TO_180_596_EQ_2047_597_6_ETC___d3855 =
(requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) &&
(requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) &&
(requestR[191] && !requestR[127] ||
(requestR[191] || !requestR[127]) &&
IF_requestR_BIT_191_186_THEN_NOT_requestR_BITS_ETC___d3786 ||
requestR_BITS_190_TO_180_596_EQ_0_607_AND_requ_ETC___d3836) ;
assign NOT_requestR_BITS_190_TO_180_596_ULT_requestR__ETC___d3832 =
!requestR_BITS_190_TO_180_596_ULT_requestR_BITS_ETC___d3782 &&
(!requestR_BITS_190_TO_180_596_EQ_requestR_BITS__ETC___d3777 ||
!requestR_BITS_179_TO_128_598_ULT_requestR_BITS_ETC___d3783) &&
requestR_BITS_190_TO_180_596_ULE_requestR_BITS_ETC___d3775 &&
(!requestR_BITS_190_TO_180_596_EQ_requestR_BITS__ETC___d3777 ||
requestR_BITS_179_TO_128_598_ULE_requestR_BITS_ETC___d3778) ;
assign NOT_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_ETC___d1089 =
(requestR[191:160] != 32'hFFFFFFFF || !requestR[159] ||
requestR[127:96] == 32'hFFFFFFFF && requestR[95]) &&
(requestR[191:160] == 32'hFFFFFFFF && requestR[159] ||
requestR[127:96] != 32'hFFFFFFFF ||
!requestR[95]) &&
((requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ?
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1085 :
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1086) ;
assign NOT_requestR_BIT_158_88_89_AND_NOT_requestR_BI_ETC___d579 =
!requestR[158] && !requestR[157] && !requestR[156] &&
!requestR[155] &&
!requestR[154] &&
!requestR[153] &&
!requestR[152] &&
!requestR[151] &&
!requestR[150] &&
!requestR[149] &&
!requestR[148] &&
!requestR[147] &&
!requestR[146] &&
!requestR[145] &&
!requestR[144] &&
!requestR[143] &&
!requestR[142] &&
!requestR[141] &&
!requestR[140] &&
!requestR[139] &&
!requestR[138] &&
!requestR[137] &&
!requestR[136] &&
!requestR[135] &&
!requestR[134] &&
!requestR[133] &&
!requestR[132] &&
!requestR[131] &&
!requestR[130] &&
!requestR[129] &&
!requestR[128] ;
assign NOT_requestR_BIT_179_767_142_AND_NOT_requestR__ETC___d2181 =
!requestR[179] && !requestR[178] && !requestR[177] &&
!requestR[176] &&
!requestR[175] &&
!requestR[174] &&
!requestR[173] &&
!requestR[172] &&
!requestR[171] &&
!requestR[170] &&
!requestR[169] &&
!requestR[168] &&
!requestR[167] &&
!requestR[166] &&
!requestR[165] &&
!requestR[164] &&
!requestR[163] &&
!requestR[162] &&
!requestR[161] &&
!requestR[160] &&
!requestR[159] &&
NOT_requestR_BIT_158_88_89_AND_NOT_requestR_BI_ETC___d579 ;
assign SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3145 =
{ {4{IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d818[7]}},
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d818 } ;
assign SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 =
(SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3145 ^
12'h800) <=
12'd3071 ;
assign SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 =
(SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3145 ^
12'h800) <
12'd1026 ;
assign SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q96 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3145 +
12'd1023 ;
assign SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q99 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q96[10:0] -
11'd1023 ;
assign SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_609___d2311 =
{ requestR_BITS_190_TO_180_596_MINUS_1023___d1609[10],
requestR_BITS_190_TO_180_596_MINUS_1023___d1609 } ;
assign SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 =
(SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_609___d2311 ^
12'h800) <=
12'd2175 ;
assign SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 =
(SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_609___d2311 ^
12'h800) <
12'd1922 ;
assign SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q64 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_609___d2311 +
12'd127 ;
assign SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q67 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q64[7:0] -
8'd127 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2076 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_TO_180__ETC___d2074 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2858 =
{ 3'd0,
_theResult___fst_exp__h69650 == 8'd0 &&
(sfdin__h69644[56:34] == 23'd0 || guard__h61553 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h70277 == 8'd255 &&
_theResult___fst_sfd__h70278 == 23'd0,
1'd0,
_theResult___fst_exp__h69650 != 8'd255 &&
guard__h61553 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3396 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_191_TO__ETC___d3394 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3681 =
{ 3'd0,
_theResult___fst_exp__h128838 == 11'd0 &&
(sfdin__h128832[56:5] == 52'd0 || guard__h120612 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h129668 == 11'd2047 &&
_theResult___fst_sfd__h129669 == 52'd0,
1'd0,
_theResult___fst_exp__h128838 != 11'd2047 &&
guard__h120612 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2560 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_requestR_BITS_190_TO_180_ETC___d2558 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2887 =
{ 3'd0,
_theResult___fst_exp__h87503 == 8'd0 &&
(sfdin__h87497[56:34] == 23'd0 || guard__h79277 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h88130 == 8'd255 &&
_theResult___fst_sfd__h88131 == 23'd0,
1'd0,
_theResult___fst_exp__h87503 != 8'd255 &&
guard__h79277 != 2'b0 } ;
assign _0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3076 =
({ 6'd0,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3074 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3469 =
({ 6'd0,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3074 } ^
12'h800) <=
(IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3468 ^
12'h800) ;
assign _0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3664 =
{ 3'd0,
_theResult___fst_exp__h119265 == 11'd0 &&
guard__h111304 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h120021 == 11'd2047 &&
_theResult___fst_sfd__h120022 == 52'd0,
1'd0,
_theResult___fst_exp__h119265 != 11'd2047 &&
guard__h111304 != 2'b0 } ;
assign _0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2238 =
({ 3'd0,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2236 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2633 =
({ 3'd0,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2236 } ^
9'h100) <=
(IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2632 ^
9'h100) ;
assign _0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2870 =
{ 3'd0,
_theResult___fst_exp__h78336 == 8'd0 && guard__h70288 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h78889 == 8'd255 &&
_theResult___fst_sfd__h78890 == 23'd0,
1'd0,
_theResult___fst_exp__h78336 != 8'd255 &&
guard__h70288 != 2'b0 } ;
assign _0b0_CONCAT_NOT_IF_requestR_BITS_191_TO_160_4_E_ETC___d3152 =
b__h15050 >>
_3074_MINUS_SEXT_IF_requestR_BITS_191_TO_160_4__ETC___d3148 ;
assign _0b0_CONCAT_NOT_requestR_BITS_190_TO_180_596_EQ_ETC___d2318 =
sfd__h53913 >>
_3970_MINUS_SEXT_requestR_BITS_190_TO_180_596_M_ETC___d2314 ;
assign _1_CONCAT_DONTCARE_CONCAT_requestR_BITS_63_TO_3_ETC___d68 =
{ 33'h1AAAAAAAA,
requestR[63:32] == 32'hFFFFFFFF && requestR[31],
(requestR[63:32] == 32'hFFFFFFFF) ?
requestR[30:0] :
31'h7FC00000 } ;
assign _3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1840 =
12'd3074 -
{ 6'd0,
requestR[179] ?
6'd0 :
(requestR[178] ?
6'd1 :
(requestR[177] ?
6'd2 :
(requestR[176] ?
6'd3 :
(requestR[175] ?
6'd4 :
(requestR[174] ?
6'd5 :
(requestR[173] ?
6'd6 :
(requestR[172] ?
6'd7 :
(requestR[171] ?
6'd8 :
(requestR[170] ?
6'd9 :
(requestR[169] ?
6'd10 :
(requestR[168] ?
6'd11 :
(requestR[167] ?
6'd12 :
(requestR[166] ?
6'd13 :
(requestR[165] ?
6'd14 :
(requestR[164] ?
6'd15 :
(requestR[163] ?
6'd16 :
(requestR[162] ?
6'd17 :
(requestR[161] ?
6'd18 :
(requestR[160] ?
6'd19 :
(requestR[159] ?
6'd20 :
(requestR[158] ?
6'd21 :
(requestR[157] ?
6'd22 :
(requestR[156] ?
6'd23 :
(requestR[155] ?
6'd24 :
(requestR[154] ?
6'd25 :
(requestR[153] ?
6'd26 :
(requestR[152] ?
6'd27 :
(requestR[151] ?
6'd28 :
(requestR[150] ?
6'd29 :
(requestR[149] ?
6'd30 :
(requestR[148] ?
6'd31 :
(requestR[147] ?
6'd32 :
(requestR[146] ?
6'd33 :
(requestR[145] ?
6'd34 :
(requestR[144] ?
6'd35 :
(requestR[143] ?
6'd36 :
(requestR[142] ?
6'd37 :
(requestR[141] ?
6'd38 :
(requestR[140] ?
6'd39 :
(requestR[139] ?
6'd40 :
(requestR[138] ?
6'd41 :
(requestR[137] ?
6'd42 :
(requestR[136] ?
6'd43 :
(requestR[135] ?
6'd44 :
(requestR[134] ?
6'd45 :
(requestR[133] ?
6'd46 :
(requestR[132] ?
6'd47 :
(requestR[131] ?
6'd48 :
(requestR[130] ?
6'd49 :
(requestR[129] ?
6'd50 :
(requestR[128] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 =
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1840 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 =
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1840 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2873 =
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 &&
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2858[4] :
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2870[4]) ;
assign _3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2898 =
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 &&
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2858[3] :
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2870[3]) ;
assign _3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2925 =
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 &&
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2858[1] :
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2870[1]) ;
assign _3074_MINUS_SEXT_IF_requestR_BITS_191_TO_160_4__ETC___d3148 =
12'd3074 -
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3145 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1230 =
(12'd32 -
{ 6'd0,
IF_IF_requestR_BIT_159_6_THEN_NEG_requestR_BIT_ETC___d1227 }) -
12'd1 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1231 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1230 ^
12'h800) <=
12'd3071 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1233 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1230 ^
12'h800) <
12'd974 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1235 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1230 ^
12'h800) <
12'd1026 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d258 =
(9'd32 -
{ 3'd0,
IF_IF_requestR_BIT_159_6_THEN_NEG_requestR_BIT_ETC___d255 }) -
9'd1 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d259 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d258 ^
9'h100) <=
9'd383 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d261 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d258 ^
9'h100) <
9'd107 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d264 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d258 ^
9'h100) <
9'd130 ;
assign _32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1445 =
(12'd32 -
{ 6'd0,
IF_requestR_BIT_159_6_THEN_0_ELSE_IF_requestR__ETC___d1442 }) -
12'd1 ;
assign _32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1446 =
(_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1445 ^
12'h800) <=
12'd3071 ;
assign _32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1447 =
(_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1445 ^
12'h800) <
12'd974 ;
assign _32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1448 =
(_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1445 ^
12'h800) <
12'd1026 ;
assign _32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d616 =
(9'd32 -
{ 3'd0,
IF_requestR_BIT_159_6_THEN_0_ELSE_IF_requestR__ETC___d613 }) -
9'd1 ;
assign _32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d617 =
(_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d616 ^
9'h100) <=
9'd383 ;
assign _32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d618 =
(_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d616 ^
9'h100) <
9'd107 ;
assign _32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d619 =
(_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d616 ^
9'h100) <
9'd130 ;
assign _3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3002 =
12'd3970 -
{ 7'd0,
sV1_sfd__h816[22] ?
5'd0 :
(sV1_sfd__h816[21] ?
5'd1 :
(sV1_sfd__h816[20] ?
5'd2 :
(sV1_sfd__h816[19] ?
5'd3 :
(sV1_sfd__h816[18] ?
5'd4 :
(sV1_sfd__h816[17] ?
5'd5 :
(sV1_sfd__h816[16] ?
5'd6 :
(sV1_sfd__h816[15] ?
5'd7 :
(sV1_sfd__h816[14] ?
5'd8 :
(sV1_sfd__h816[13] ?
5'd9 :
(sV1_sfd__h816[12] ?
5'd10 :
(sV1_sfd__h816[11] ?
5'd11 :
(sV1_sfd__h816[10] ?
5'd12 :
(sV1_sfd__h816[9] ?
5'd13 :
(sV1_sfd__h816[8] ?
5'd14 :
(sV1_sfd__h816[7] ?
5'd15 :
(sV1_sfd__h816[6] ?
5'd16 :
(sV1_sfd__h816[5] ?
5'd17 :
(sV1_sfd__h816[4] ?
5'd18 :
(sV1_sfd__h816[3] ?
5'd19 :
(sV1_sfd__h816[2] ?
5'd20 :
(sV1_sfd__h816[1] ?
5'd21 :
(sV1_sfd__h816[0] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 =
(_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3002 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 =
(_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3002 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_SEXT_requestR_BITS_190_TO_180_596_M_ETC___d2314 =
12'd3970 -
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_609___d2311 ;
assign _theResult_____2__h14985 =
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d844 ?
out1___1__h15477 :
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827[56:24] ;
assign _theResult_____2__h47542 =
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1635 ?
out1___1__h48034 :
IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618[85:53] ;
assign _theResult____h120602 =
((_3074_MINUS_SEXT_IF_requestR_BITS_191_TO_160_4__ETC___d3148 ^
12'h800) <
12'd2105) ?
result__h121215 :
((value__h15052 == 25'd0) ? b__h15050 : 57'd1) ;
assign _theResult____h61543 =
(value__h47609 == 54'd0) ? sfd__h53913 : 57'd1 ;
assign _theResult____h79267 =
((_3970_MINUS_SEXT_requestR_BITS_190_TO_180_596_M_ETC___d2314 ^
12'h800) <
12'd2105) ?
result__h79880 :
_theResult____h61543 ;
assign _theResult___exp__h119920 =
sfd__h119283[53] ?
((_theResult___fst_exp__h119265 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h138485) :
((_theResult___fst_exp__h119265 == 11'd0 &&
sfd__h119283[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h119265) ;
assign _theResult___exp__h129567 =
sfd__h128930[53] ?
((_theResult___fst_exp__h128838 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h138515) :
((_theResult___fst_exp__h128838 == 11'd0 &&
sfd__h128930[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h128838) ;
assign _theResult___exp__h13726 =
(sfd__h13330[24] || sfd__h13330[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h138349 =
sfd__h137688[53] ?
((_theResult___fst_exp__h137669 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h138539) :
((_theResult___fst_exp__h137669 == 11'd0 &&
sfd__h137688[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h137669) ;
assign _theResult___exp__h14278 =
sfd__h13869[24] ?
((x__h13854[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h14416) :
((x__h13854[7:0] == 8'd0 && sfd__h13869[24:23] == 2'b01) ?
8'd1 :
x__h13854[7:0]) ;
assign _theResult___exp__h36388 =
(sfd__h35789[53] || sfd__h35789[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h37144 =
sfd__h36532[53] ?
((x__h36517[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h37287) :
((x__h36517[10:0] == 11'd0 && sfd__h36532[53:52] == 2'b01) ?
11'd1 :
x__h36517[10:0]) ;
assign _theResult___exp__h46084 =
(sfd__h45485[53] || sfd__h45485[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h46839 =
sfd__h46227[53] ?
((x__h46212[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h46977) :
((x__h46212[10:0] == 11'd0 && sfd__h46227[53:52] == 2'b01) ?
11'd1 :
x__h46212[10:0]) ;
assign _theResult___exp__h70176 =
sfd__h69742[24] ?
((_theResult___fst_exp__h69650 == 8'd254) ?
8'd255 :
din_inc___2_exp__h96827) :
((_theResult___fst_exp__h69650 == 8'd0 &&
sfd__h69742[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h69650) ;
assign _theResult___exp__h7552 =
(sfd__h7153[24] || sfd__h7153[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h78788 =
sfd__h78354[24] ?
((_theResult___fst_exp__h78336 == 8'd254) ?
8'd255 :
din_inc___2_exp__h96851) :
((_theResult___fst_exp__h78336 == 8'd0 &&
sfd__h78354[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h78336) ;
assign _theResult___exp__h8105 =
sfd__h7696[24] ?
((x__h7681[7:0] == 8'd254) ? 8'd255 : din_inc___2_exp__h8248) :
((x__h7681[7:0] == 8'd0 && sfd__h7696[24:23] == 2'b01) ?
8'd1 :
x__h7681[7:0]) ;
assign _theResult___exp__h88029 =
sfd__h87595[24] ?
((_theResult___fst_exp__h87503 == 8'd254) ?
8'd255 :
din_inc___2_exp__h96881) :
((_theResult___fst_exp__h87503 == 8'd0 &&
sfd__h87595[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h87503) ;
assign _theResult___exp__h96695 =
sfd__h96237[24] ?
((_theResult___fst_exp__h96218 == 8'd254) ?
8'd255 :
din_inc___2_exp__h96905) :
((_theResult___fst_exp__h96218 == 8'd0 &&
sfd__h96237[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h96218) ;
assign _theResult___fst_exp__h104192 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3) ?
11'd2047 :
CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 ;
assign _theResult___fst_exp__h119256 =
11'd897 -
{ 5'd0,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3074 } ;
assign _theResult___fst_exp__h119262 =
(sV1_exp__h815 == 8'd0 && !sV1_sfd__h816[22] &&
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d3047 ||
!_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3076) ?
11'd0 :
_theResult___fst_exp__h119256 ;
assign _theResult___fst_exp__h119265 =
(sV1_exp__h815 == 8'd0) ?
_theResult___fst_exp__h119262 :
11'd897 ;
assign _theResult___fst_exp__h120018 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q103 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3134 ;
assign _theResult___fst_exp__h120021 =
(_theResult___fst_exp__h119265 == 11'd2047) ?
_theResult___fst_exp__h119265 :
_theResult___fst_exp__h120018 ;
assign _theResult___fst_exp__h128838 =
_theResult____h120602[56] ?
11'd2 :
_theResult___fst_exp__h128912 ;
assign _theResult___fst_exp__h128903 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_191_TO__ETC___d3394 } ;
assign _theResult___fst_exp__h128909 =
(!_theResult____h120602[56] && !_theResult____h120602[55] &&
!_theResult____h120602[54] &&
!_theResult____h120602[53] &&
!_theResult____h120602[52] &&
!_theResult____h120602[51] &&
!_theResult____h120602[50] &&
!_theResult____h120602[49] &&
!_theResult____h120602[48] &&
!_theResult____h120602[47] &&
!_theResult____h120602[46] &&
!_theResult____h120602[45] &&
!_theResult____h120602[44] &&
!_theResult____h120602[43] &&
!_theResult____h120602[42] &&
!_theResult____h120602[41] &&
!_theResult____h120602[40] &&
!_theResult____h120602[39] &&
!_theResult____h120602[38] &&
!_theResult____h120602[37] &&
!_theResult____h120602[36] &&
!_theResult____h120602[35] &&
!_theResult____h120602[34] &&
!_theResult____h120602[33] &&
!_theResult____h120602[32] &&
!_theResult____h120602[31] &&
!_theResult____h120602[30] &&
!_theResult____h120602[29] &&
!_theResult____h120602[28] &&
!_theResult____h120602[27] &&
!_theResult____h120602[26] &&
!_theResult____h120602[25] &&
!_theResult____h120602[24] &&
!_theResult____h120602[23] &&
!_theResult____h120602[22] &&
!_theResult____h120602[21] &&
!_theResult____h120602[20] &&
!_theResult____h120602[19] &&
!_theResult____h120602[18] &&
!_theResult____h120602[17] &&
!_theResult____h120602[16] &&
!_theResult____h120602[15] &&
!_theResult____h120602[14] &&
!_theResult____h120602[13] &&
!_theResult____h120602[12] &&
!_theResult____h120602[11] &&
!_theResult____h120602[10] &&
!_theResult____h120602[9] &&
!_theResult____h120602[8] &&
!_theResult____h120602[7] &&
!_theResult____h120602[6] &&
!_theResult____h120602[5] &&
!_theResult____h120602[4] &&
!_theResult____h120602[3] &&
!_theResult____h120602[2] &&
!_theResult____h120602[1] &&
!_theResult____h120602[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3396) ?
11'd0 :
_theResult___fst_exp__h128903 ;
assign _theResult___fst_exp__h128912 =
(!_theResult____h120602[56] && _theResult____h120602[55]) ?
11'd1 :
_theResult___fst_exp__h128909 ;
assign _theResult___fst_exp__h129665 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q105 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3459 ;
assign _theResult___fst_exp__h129668 =
(_theResult___fst_exp__h128838 == 11'd2047) ?
_theResult___fst_exp__h128838 :
_theResult___fst_exp__h129665 ;
assign _theResult___fst_exp__h137621 =
(SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q96[10:0] ==
11'd0) ?
11'd1 :
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q96[10:0] ;
assign _theResult___fst_exp__h137660 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q96[10:0] -
{ 5'd0,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3074 } ;
assign _theResult___fst_exp__h137666 =
(sV1_exp__h815 == 8'd0 && !sV1_sfd__h816[22] &&
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d3047 ||
!_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3469) ?
11'd0 :
_theResult___fst_exp__h137660 ;
assign _theResult___fst_exp__h137669 =
(sV1_exp__h815 == 8'd0) ?
_theResult___fst_exp__h137666 :
_theResult___fst_exp__h137621 ;
assign _theResult___fst_exp__h13822 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard3313_0b0_0_0b1_0_0b10_out_exp3729_0b_ETC__q22 :
CASE_requestR_BITS_194_TO_192_0x3_IF_guard3313_ETC__q24 ;
assign _theResult___fst_exp__h138447 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q107 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3528 ;
assign _theResult___fst_exp__h138450 =
(_theResult___fst_exp__h137669 == 11'd2047) ?
_theResult___fst_exp__h137669 :
_theResult___fst_exp__h138447 ;
assign _theResult___fst_exp__h138459 =
(sV1_exp__h815 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 ?
_theResult___snd_fst_exp__h120024 :
_theResult___fst_exp__h104192) :
(SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 ?
_theResult___snd_fst_exp__h138453 :
_theResult___fst_exp__h104192) ;
assign _theResult___fst_exp__h138462 =
(sV1_exp__h815 == 8'd0 && sV1_sfd__h816 == 23'd0) ?
11'd0 :
_theResult___fst_exp__h138459 ;
assign _theResult___fst_exp__h14374 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_x3854_ETC__q26 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d697 ;
assign _theResult___fst_exp__h14377 =
(x__h13854[7:0] == 8'd255) ?
x__h13854[7:0] :
_theResult___fst_exp__h14374 ;
assign _theResult___fst_exp__h36485 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5772_0b0_0_0b1_0_0b10_out_exp6391_0b_ETC__q44 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1310 ;
assign _theResult___fst_exp__h37241 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_x651_ETC__q40 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1339 ;
assign _theResult___fst_exp__h37244 =
(x__h36517[10:0] == 11'd2047) ?
x__h36517[10:0] :
_theResult___fst_exp__h37241 ;
assign _theResult___fst_exp__h46180 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5468_0b0_0_0b1_0_0b10_out_exp6087_0b_ETC__q49 :
CASE_requestR_BITS_194_TO_192_0x3_IF_guard5468_ETC__q51 ;
assign _theResult___fst_exp__h46935 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_x621_ETC__q53 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1526 ;
assign _theResult___fst_exp__h46938 =
(x__h46212[10:0] == 11'd2047) ?
x__h46212[10:0] :
_theResult___fst_exp__h46935 ;
assign _theResult___fst_exp__h61525 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3) ?
8'd255 :
CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 ;
assign _theResult___fst_exp__h69650 =
_theResult____h61543[56] ? 8'd2 : _theResult___fst_exp__h69724 ;
assign _theResult___fst_exp__h69715 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_TO_180__ETC___d2074 } ;
assign _theResult___fst_exp__h69721 =
(!_theResult____h61543[56] && !_theResult____h61543[55] &&
!_theResult____h61543[54] &&
!_theResult____h61543[53] &&
!_theResult____h61543[52] &&
!_theResult____h61543[51] &&
!_theResult____h61543[50] &&
!_theResult____h61543[49] &&
!_theResult____h61543[48] &&
!_theResult____h61543[47] &&
!_theResult____h61543[46] &&
!_theResult____h61543[45] &&
!_theResult____h61543[44] &&
!_theResult____h61543[43] &&
!_theResult____h61543[42] &&
!_theResult____h61543[41] &&
!_theResult____h61543[40] &&
!_theResult____h61543[39] &&
!_theResult____h61543[38] &&
!_theResult____h61543[37] &&
!_theResult____h61543[36] &&
!_theResult____h61543[35] &&
!_theResult____h61543[34] &&
!_theResult____h61543[33] &&
!_theResult____h61543[32] &&
!_theResult____h61543[31] &&
!_theResult____h61543[30] &&
!_theResult____h61543[29] &&
!_theResult____h61543[28] &&
!_theResult____h61543[27] &&
!_theResult____h61543[26] &&
!_theResult____h61543[25] &&
!_theResult____h61543[24] &&
!_theResult____h61543[23] &&
!_theResult____h61543[22] &&
!_theResult____h61543[21] &&
!_theResult____h61543[20] &&
!_theResult____h61543[19] &&
!_theResult____h61543[18] &&
!_theResult____h61543[17] &&
!_theResult____h61543[16] &&
!_theResult____h61543[15] &&
!_theResult____h61543[14] &&
!_theResult____h61543[13] &&
!_theResult____h61543[12] &&
!_theResult____h61543[11] &&
!_theResult____h61543[10] &&
!_theResult____h61543[9] &&
!_theResult____h61543[8] &&
!_theResult____h61543[7] &&
!_theResult____h61543[6] &&
!_theResult____h61543[5] &&
!_theResult____h61543[4] &&
!_theResult____h61543[3] &&
!_theResult____h61543[2] &&
!_theResult____h61543[1] &&
!_theResult____h61543[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2076) ?
8'd0 :
_theResult___fst_exp__h69715 ;
assign _theResult___fst_exp__h69724 =
(!_theResult____h61543[56] && _theResult____h61543[55]) ?
8'd1 :
_theResult___fst_exp__h69721 ;
assign _theResult___fst_exp__h70274 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q71 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2139 ;
assign _theResult___fst_exp__h70277 =
(_theResult___fst_exp__h69650 == 8'd255) ?
_theResult___fst_exp__h69650 :
_theResult___fst_exp__h70274 ;
assign _theResult___fst_exp__h7649 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard136_0b0_0_0b1_0_0b10_out_exp555_0b11_ETC__q13 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d350 ;
assign _theResult___fst_exp__h78327 =
8'd129 -
{ 2'd0,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2236 } ;
assign _theResult___fst_exp__h78333 =
(requestR[190:180] == 11'd0 &&
NOT_requestR_BIT_179_767_142_AND_NOT_requestR__ETC___d2181 ||
!_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2238) ?
8'd0 :
_theResult___fst_exp__h78327 ;
assign _theResult___fst_exp__h78336 =
(requestR[190:180] == 11'd0) ?
_theResult___fst_exp__h78333 :
8'd129 ;
assign _theResult___fst_exp__h78886 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q73 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2296 ;
assign _theResult___fst_exp__h78889 =
(_theResult___fst_exp__h78336 == 8'd255) ?
_theResult___fst_exp__h78336 :
_theResult___fst_exp__h78886 ;
assign _theResult___fst_exp__h8202 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_x681_BI_ETC__q15 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d379 ;
assign _theResult___fst_exp__h8205 =
(x__h7681[7:0] == 8'd255) ?
x__h7681[7:0] :
_theResult___fst_exp__h8202 ;
assign _theResult___fst_exp__h87503 =
_theResult____h79267[56] ? 8'd2 : _theResult___fst_exp__h87577 ;
assign _theResult___fst_exp__h87568 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_requestR_BITS_190_TO_180_ETC___d2558 } ;
assign _theResult___fst_exp__h87574 =
(!_theResult____h79267[56] && !_theResult____h79267[55] &&
!_theResult____h79267[54] &&
!_theResult____h79267[53] &&
!_theResult____h79267[52] &&
!_theResult____h79267[51] &&
!_theResult____h79267[50] &&
!_theResult____h79267[49] &&
!_theResult____h79267[48] &&
!_theResult____h79267[47] &&
!_theResult____h79267[46] &&
!_theResult____h79267[45] &&
!_theResult____h79267[44] &&
!_theResult____h79267[43] &&
!_theResult____h79267[42] &&
!_theResult____h79267[41] &&
!_theResult____h79267[40] &&
!_theResult____h79267[39] &&
!_theResult____h79267[38] &&
!_theResult____h79267[37] &&
!_theResult____h79267[36] &&
!_theResult____h79267[35] &&
!_theResult____h79267[34] &&
!_theResult____h79267[33] &&
!_theResult____h79267[32] &&
!_theResult____h79267[31] &&
!_theResult____h79267[30] &&
!_theResult____h79267[29] &&
!_theResult____h79267[28] &&
!_theResult____h79267[27] &&
!_theResult____h79267[26] &&
!_theResult____h79267[25] &&
!_theResult____h79267[24] &&
!_theResult____h79267[23] &&
!_theResult____h79267[22] &&
!_theResult____h79267[21] &&
!_theResult____h79267[20] &&
!_theResult____h79267[19] &&
!_theResult____h79267[18] &&
!_theResult____h79267[17] &&
!_theResult____h79267[16] &&
!_theResult____h79267[15] &&
!_theResult____h79267[14] &&
!_theResult____h79267[13] &&
!_theResult____h79267[12] &&
!_theResult____h79267[11] &&
!_theResult____h79267[10] &&
!_theResult____h79267[9] &&
!_theResult____h79267[8] &&
!_theResult____h79267[7] &&
!_theResult____h79267[6] &&
!_theResult____h79267[5] &&
!_theResult____h79267[4] &&
!_theResult____h79267[3] &&
!_theResult____h79267[2] &&
!_theResult____h79267[1] &&
!_theResult____h79267[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2560) ?
8'd0 :
_theResult___fst_exp__h87568 ;
assign _theResult___fst_exp__h87577 =
(!_theResult____h79267[56] && _theResult____h79267[55]) ?
8'd1 :
_theResult___fst_exp__h87574 ;
assign _theResult___fst_exp__h88127 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q75 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2623 ;
assign _theResult___fst_exp__h88130 =
(_theResult___fst_exp__h87503 == 8'd255) ?
_theResult___fst_exp__h87503 :
_theResult___fst_exp__h88127 ;
assign _theResult___fst_exp__h96170 =
(SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q64[7:0] ==
8'd0) ?
8'd1 :
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q64[7:0] ;
assign _theResult___fst_exp__h96209 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q64[7:0] -
{ 2'd0,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2236 } ;
assign _theResult___fst_exp__h96215 =
(requestR[190:180] == 11'd0 &&
NOT_requestR_BIT_179_767_142_AND_NOT_requestR__ETC___d2181 ||
!_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2633) ?
8'd0 :
_theResult___fst_exp__h96209 ;
assign _theResult___fst_exp__h96218 =
(requestR[190:180] == 11'd0) ?
_theResult___fst_exp__h96215 :
_theResult___fst_exp__h96170 ;
assign _theResult___fst_exp__h96793 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q77 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2692 ;
assign _theResult___fst_exp__h96796 =
(_theResult___fst_exp__h96218 == 8'd255) ?
_theResult___fst_exp__h96218 :
_theResult___fst_exp__h96793 ;
assign _theResult___fst_exp__h96805 =
(requestR[190:180] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 ?
_theResult___snd_fst_exp__h78892 :
_theResult___fst_exp__h61525) :
(SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 ?
_theResult___snd_fst_exp__h96799 :
_theResult___fst_exp__h61525) ;
assign _theResult___fst_exp__h96808 =
(requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ?
8'd0 :
_theResult___fst_exp__h96805 ;
assign _theResult___fst_sfd__h104193 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3) ?
52'd0 :
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 ;
assign _theResult___fst_sfd__h120019 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q115 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3561 ;
assign _theResult___fst_sfd__h120022 =
(_theResult___fst_exp__h119265 == 11'd2047) ?
_theResult___snd__h119216[56:5] :
_theResult___fst_sfd__h120019 ;
assign _theResult___fst_sfd__h129666 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q117 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3588 ;
assign _theResult___fst_sfd__h129669 =
(_theResult___fst_exp__h128838 == 11'd2047) ?
sfdin__h128832[56:5] :
_theResult___fst_sfd__h129666 ;
assign _theResult___fst_sfd__h13823 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q30 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d720 ;
assign _theResult___fst_sfd__h138448 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q119 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3607 ;
assign _theResult___fst_sfd__h138451 =
(_theResult___fst_exp__h137669 == 11'd2047) ?
_theResult___snd__h137615[56:5] :
_theResult___fst_sfd__h138448 ;
assign _theResult___fst_sfd__h138460 =
(sV1_exp__h815 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 ?
_theResult___snd_fst_sfd__h120025 :
_theResult___fst_sfd__h104193) :
(SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 ?
_theResult___snd_fst_sfd__h138454 :
_theResult___fst_sfd__h104193) ;
assign _theResult___fst_sfd__h138466 =
((sV1_exp__h815 == 8'd255 || sV1_exp__h815 == 8'd0) &&
sV1_sfd__h816 == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h138460 ;
assign _theResult___fst_sfd__h14375 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q28 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d735 ;
assign _theResult___fst_sfd__h14378 =
(x__h13854[7:0] == 8'd255) ?
sfd___3__h13303[30:8] :
_theResult___fst_sfd__h14375 ;
assign _theResult___fst_sfd__h36486 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q46 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1362 ;
assign _theResult___fst_sfd__h37242 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q42 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1380 ;
assign _theResult___fst_sfd__h37245 =
(x__h36517[10:0] == 11'd2047) ?
sfd___3__h35762[53:2] :
_theResult___fst_sfd__h37242 ;
assign _theResult___fst_sfd__h46181 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q57 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1548 ;
assign _theResult___fst_sfd__h46936 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q55 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1563 ;
assign _theResult___fst_sfd__h46939 =
(x__h46212[10:0] == 11'd2047) ?
sfd___3__h45458[53:2] :
_theResult___fst_sfd__h46936 ;
assign _theResult___fst_sfd__h50209 = { 1'd1, requestR[178:128] } ;
assign _theResult___fst_sfd__h61526 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3) ?
23'd0 :
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 ;
assign _theResult___fst_sfd__h70275 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q79 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2726 ;
assign _theResult___fst_sfd__h70278 =
(_theResult___fst_exp__h69650 == 8'd255) ?
sfdin__h69644[56:34] :
_theResult___fst_sfd__h70275 ;
assign _theResult___fst_sfd__h7650 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q17 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d402 ;
assign _theResult___fst_sfd__h78887 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q81 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2745 ;
assign _theResult___fst_sfd__h78890 =
(_theResult___fst_exp__h78336 == 8'd255) ?
_theResult___snd__h78287[56:34] :
_theResult___fst_sfd__h78887 ;
assign _theResult___fst_sfd__h8203 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q19 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d420 ;
assign _theResult___fst_sfd__h8206 =
(x__h7681[7:0] == 8'd255) ?
sfd___3__h7126[30:8] :
_theResult___fst_sfd__h8203 ;
assign _theResult___fst_sfd__h88128 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q83 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2772 ;
assign _theResult___fst_sfd__h88131 =
(_theResult___fst_exp__h87503 == 8'd255) ?
sfdin__h87497[56:34] :
_theResult___fst_sfd__h88128 ;
assign _theResult___fst_sfd__h96794 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q85 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2791 ;
assign _theResult___fst_sfd__h96797 =
(_theResult___fst_exp__h96218 == 8'd255) ?
_theResult___snd__h96164[56:34] :
_theResult___fst_sfd__h96794 ;
assign _theResult___fst_sfd__h96806 =
(requestR[190:180] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 ?
_theResult___snd_fst_sfd__h78893 :
_theResult___fst_sfd__h61526) :
(SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 ?
_theResult___snd_fst_sfd__h96800 :
_theResult___fst_sfd__h61526) ;
assign _theResult___fst_sfd__h96812 =
((requestR[190:180] == 11'd2047 || requestR[190:180] == 11'd0) &&
requestR[179:128] == 52'd0) ?
23'd0 :
_theResult___fst_sfd__h96806 ;
assign _theResult___fst_sfd__h98711 = { 1'd1, sV1_sfd__h816[21:0] } ;
assign _theResult___sfd__h119921 =
sfd__h119283[53] ?
((_theResult___fst_exp__h119265 == 11'd2046) ?
52'd0 :
sfd__h119283[52:1]) :
sfd__h119283[51:0] ;
assign _theResult___sfd__h129568 =
sfd__h128930[53] ?
((_theResult___fst_exp__h128838 == 11'd2046) ?
52'd0 :
sfd__h128930[52:1]) :
sfd__h128930[51:0] ;
assign _theResult___sfd__h13727 =
sfd__h13330[24] ? sfd__h13330[23:1] : sfd__h13330[22:0] ;
assign _theResult___sfd__h138350 =
sfd__h137688[53] ?
((_theResult___fst_exp__h137669 == 11'd2046) ?
52'd0 :
sfd__h137688[52:1]) :
sfd__h137688[51:0] ;
assign _theResult___sfd__h14279 =
sfd__h13869[24] ?
((x__h13854[7:0] == 8'd254) ? 23'd0 : sfd__h13869[23:1]) :
sfd__h13869[22:0] ;
assign _theResult___sfd__h36389 =
sfd__h35789[53] ? sfd__h35789[52:1] : sfd__h35789[51:0] ;
assign _theResult___sfd__h37145 =
sfd__h36532[53] ?
((x__h36517[10:0] == 11'd2046) ? 52'd0 : sfd__h36532[52:1]) :
sfd__h36532[51:0] ;
assign _theResult___sfd__h46085 =
sfd__h45485[53] ? sfd__h45485[52:1] : sfd__h45485[51:0] ;
assign _theResult___sfd__h46840 =
sfd__h46227[53] ?
((x__h46212[10:0] == 11'd2046) ? 52'd0 : sfd__h46227[52:1]) :
sfd__h46227[51:0] ;
assign _theResult___sfd__h70177 =
sfd__h69742[24] ?
((_theResult___fst_exp__h69650 == 8'd254) ?
23'd0 :
sfd__h69742[23:1]) :
sfd__h69742[22:0] ;
assign _theResult___sfd__h7553 =
sfd__h7153[24] ? sfd__h7153[23:1] : sfd__h7153[22:0] ;
assign _theResult___sfd__h78789 =
sfd__h78354[24] ?
((_theResult___fst_exp__h78336 == 8'd254) ?
23'd0 :
sfd__h78354[23:1]) :
sfd__h78354[22:0] ;
assign _theResult___sfd__h8106 =
sfd__h7696[24] ?
((x__h7681[7:0] == 8'd254) ? 23'd0 : sfd__h7696[23:1]) :
sfd__h7696[22:0] ;
assign _theResult___sfd__h88030 =
sfd__h87595[24] ?
((_theResult___fst_exp__h87503 == 8'd254) ?
23'd0 :
sfd__h87595[23:1]) :
sfd__h87595[22:0] ;
assign _theResult___sfd__h96696 =
sfd__h96237[24] ?
((_theResult___fst_exp__h96218 == 8'd254) ?
23'd0 :
sfd__h96237[23:1]) :
sfd__h96237[22:0] ;
assign _theResult___snd__h119216 =
(sV1_exp__h815 == 8'd0) ?
_theResult___snd__h119225 :
_theResult___snd__h119218 ;
assign _theResult___snd__h119218 = { sV1_sfd__h816, 34'd0 } ;
assign _theResult___snd__h119225 =
(sV1_exp__h815 == 8'd0 && !sV1_sfd__h816[22] &&
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d3047) ?
b__h15050 :
_theResult___snd__h119231 ;
assign _theResult___snd__h119231 =
{ IF_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_E_ETC__q94[54:0],
2'd0 } ;
assign _theResult___snd__h119254 =
b__h15050 <<
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3074 ;
assign _theResult___snd__h128849 = { _theResult____h120602[55:0], 1'd0 } ;
assign _theResult___snd__h128860 =
(!_theResult____h120602[56] && _theResult____h120602[55]) ?
_theResult___snd__h128862 :
_theResult___snd__h128872 ;
assign _theResult___snd__h128862 = { _theResult____h120602[54:0], 2'd0 } ;
assign _theResult___snd__h128872 =
(!_theResult____h120602[56] && !_theResult____h120602[55] &&
!_theResult____h120602[54] &&
!_theResult____h120602[53] &&
!_theResult____h120602[52] &&
!_theResult____h120602[51] &&
!_theResult____h120602[50] &&
!_theResult____h120602[49] &&
!_theResult____h120602[48] &&
!_theResult____h120602[47] &&
!_theResult____h120602[46] &&
!_theResult____h120602[45] &&
!_theResult____h120602[44] &&
!_theResult____h120602[43] &&
!_theResult____h120602[42] &&
!_theResult____h120602[41] &&
!_theResult____h120602[40] &&
!_theResult____h120602[39] &&
!_theResult____h120602[38] &&
!_theResult____h120602[37] &&
!_theResult____h120602[36] &&
!_theResult____h120602[35] &&
!_theResult____h120602[34] &&
!_theResult____h120602[33] &&
!_theResult____h120602[32] &&
!_theResult____h120602[31] &&
!_theResult____h120602[30] &&
!_theResult____h120602[29] &&
!_theResult____h120602[28] &&
!_theResult____h120602[27] &&
!_theResult____h120602[26] &&
!_theResult____h120602[25] &&
!_theResult____h120602[24] &&
!_theResult____h120602[23] &&
!_theResult____h120602[22] &&
!_theResult____h120602[21] &&
!_theResult____h120602[20] &&
!_theResult____h120602[19] &&
!_theResult____h120602[18] &&
!_theResult____h120602[17] &&
!_theResult____h120602[16] &&
!_theResult____h120602[15] &&
!_theResult____h120602[14] &&
!_theResult____h120602[13] &&
!_theResult____h120602[12] &&
!_theResult____h120602[11] &&
!_theResult____h120602[10] &&
!_theResult____h120602[9] &&
!_theResult____h120602[8] &&
!_theResult____h120602[7] &&
!_theResult____h120602[6] &&
!_theResult____h120602[5] &&
!_theResult____h120602[4] &&
!_theResult____h120602[3] &&
!_theResult____h120602[2] &&
!_theResult____h120602[1] &&
!_theResult____h120602[0]) ?
_theResult____h120602 :
_theResult___snd__h128878 ;
assign _theResult___snd__h128878 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q97[54:0],
2'd0 } ;
assign _theResult___snd__h128901 =
_theResult____h120602 <<
IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_191_TO__ETC___d3394 ;
assign _theResult___snd__h137615 =
(sV1_exp__h815 == 8'd0) ?
_theResult___snd__h137629 :
_theResult___snd__h119218 ;
assign _theResult___snd__h137629 =
(sV1_exp__h815 == 8'd0 && !sV1_sfd__h816[22] &&
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d3047) ?
b__h15050 :
_theResult___snd__h137635 ;
assign _theResult___snd__h137635 =
{ IF_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_E_ETC__q100[54:0],
2'd0 } ;
assign _theResult___snd__h137653 =
b__h15050 <<
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3468 ;
assign _theResult___snd__h69661 = { _theResult____h61543[55:0], 1'd0 } ;
assign _theResult___snd__h69672 =
(!_theResult____h61543[56] && _theResult____h61543[55]) ?
_theResult___snd__h69674 :
_theResult___snd__h69684 ;
assign _theResult___snd__h69674 = { _theResult____h61543[54:0], 2'd0 } ;
assign _theResult___snd__h69684 =
(!_theResult____h61543[56] && !_theResult____h61543[55] &&
!_theResult____h61543[54] &&
!_theResult____h61543[53] &&
!_theResult____h61543[52] &&
!_theResult____h61543[51] &&
!_theResult____h61543[50] &&
!_theResult____h61543[49] &&
!_theResult____h61543[48] &&
!_theResult____h61543[47] &&
!_theResult____h61543[46] &&
!_theResult____h61543[45] &&
!_theResult____h61543[44] &&
!_theResult____h61543[43] &&
!_theResult____h61543[42] &&
!_theResult____h61543[41] &&
!_theResult____h61543[40] &&
!_theResult____h61543[39] &&
!_theResult____h61543[38] &&
!_theResult____h61543[37] &&
!_theResult____h61543[36] &&
!_theResult____h61543[35] &&
!_theResult____h61543[34] &&
!_theResult____h61543[33] &&
!_theResult____h61543[32] &&
!_theResult____h61543[31] &&
!_theResult____h61543[30] &&
!_theResult____h61543[29] &&
!_theResult____h61543[28] &&
!_theResult____h61543[27] &&
!_theResult____h61543[26] &&
!_theResult____h61543[25] &&
!_theResult____h61543[24] &&
!_theResult____h61543[23] &&
!_theResult____h61543[22] &&
!_theResult____h61543[21] &&
!_theResult____h61543[20] &&
!_theResult____h61543[19] &&
!_theResult____h61543[18] &&
!_theResult____h61543[17] &&
!_theResult____h61543[16] &&
!_theResult____h61543[15] &&
!_theResult____h61543[14] &&
!_theResult____h61543[13] &&
!_theResult____h61543[12] &&
!_theResult____h61543[11] &&
!_theResult____h61543[10] &&
!_theResult____h61543[9] &&
!_theResult____h61543[8] &&
!_theResult____h61543[7] &&
!_theResult____h61543[6] &&
!_theResult____h61543[5] &&
!_theResult____h61543[4] &&
!_theResult____h61543[3] &&
!_theResult____h61543[2] &&
!_theResult____h61543[1] &&
!_theResult____h61543[0]) ?
_theResult____h61543 :
_theResult___snd__h69690 ;
assign _theResult___snd__h69690 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_ETC__q60[54:0],
2'd0 } ;
assign _theResult___snd__h69713 =
_theResult____h61543 <<
IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_TO_180__ETC___d2074 ;
assign _theResult___snd__h78287 =
(requestR[190:180] == 11'd0) ?
_theResult___snd__h78296 :
_theResult___snd__h78289 ;
assign _theResult___snd__h78289 = { requestR[179:128], 5'd0 } ;
assign _theResult___snd__h78296 =
(requestR[190:180] == 11'd0 &&
NOT_requestR_BIT_179_767_142_AND_NOT_requestR__ETC___d2181) ?
sfd__h53913 :
_theResult___snd__h78302 ;
assign _theResult___snd__h78302 =
{ IF_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_ETC__q62[54:0],
2'd0 } ;
assign _theResult___snd__h78325 =
sfd__h53913 <<
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2236 ;
assign _theResult___snd__h87514 = { _theResult____h79267[55:0], 1'd0 } ;
assign _theResult___snd__h87525 =
(!_theResult____h79267[56] && _theResult____h79267[55]) ?
_theResult___snd__h87527 :
_theResult___snd__h87537 ;
assign _theResult___snd__h87527 = { _theResult____h79267[54:0], 2'd0 } ;
assign _theResult___snd__h87537 =
(!_theResult____h79267[56] && !_theResult____h79267[55] &&
!_theResult____h79267[54] &&
!_theResult____h79267[53] &&
!_theResult____h79267[52] &&
!_theResult____h79267[51] &&
!_theResult____h79267[50] &&
!_theResult____h79267[49] &&
!_theResult____h79267[48] &&
!_theResult____h79267[47] &&
!_theResult____h79267[46] &&
!_theResult____h79267[45] &&
!_theResult____h79267[44] &&
!_theResult____h79267[43] &&
!_theResult____h79267[42] &&
!_theResult____h79267[41] &&
!_theResult____h79267[40] &&
!_theResult____h79267[39] &&
!_theResult____h79267[38] &&
!_theResult____h79267[37] &&
!_theResult____h79267[36] &&
!_theResult____h79267[35] &&
!_theResult____h79267[34] &&
!_theResult____h79267[33] &&
!_theResult____h79267[32] &&
!_theResult____h79267[31] &&
!_theResult____h79267[30] &&
!_theResult____h79267[29] &&
!_theResult____h79267[28] &&
!_theResult____h79267[27] &&
!_theResult____h79267[26] &&
!_theResult____h79267[25] &&
!_theResult____h79267[24] &&
!_theResult____h79267[23] &&
!_theResult____h79267[22] &&
!_theResult____h79267[21] &&
!_theResult____h79267[20] &&
!_theResult____h79267[19] &&
!_theResult____h79267[18] &&
!_theResult____h79267[17] &&
!_theResult____h79267[16] &&
!_theResult____h79267[15] &&
!_theResult____h79267[14] &&
!_theResult____h79267[13] &&
!_theResult____h79267[12] &&
!_theResult____h79267[11] &&
!_theResult____h79267[10] &&
!_theResult____h79267[9] &&
!_theResult____h79267[8] &&
!_theResult____h79267[7] &&
!_theResult____h79267[6] &&
!_theResult____h79267[5] &&
!_theResult____h79267[4] &&
!_theResult____h79267[3] &&
!_theResult____h79267[2] &&
!_theResult____h79267[1] &&
!_theResult____h79267[0]) ?
_theResult____h79267 :
_theResult___snd__h87543 ;
assign _theResult___snd__h87543 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BIT_ETC__q65[54:0],
2'd0 } ;
assign _theResult___snd__h87566 =
_theResult____h79267 <<
IF_IF_3970_MINUS_SEXT_requestR_BITS_190_TO_180_ETC___d2558 ;
assign _theResult___snd__h96164 =
(requestR[190:180] == 11'd0) ?
_theResult___snd__h96178 :
_theResult___snd__h78289 ;
assign _theResult___snd__h96178 =
(requestR[190:180] == 11'd0 &&
NOT_requestR_BIT_179_767_142_AND_NOT_requestR__ETC___d2181) ?
sfd__h53913 :
_theResult___snd__h96184 ;
assign _theResult___snd__h96184 =
{ IF_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_ETC__q68[54:0],
2'd0 } ;
assign _theResult___snd__h96202 =
sfd__h53913 <<
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2632 ;
assign _theResult___snd_fst_exp__h120024 =
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 ?
11'd0 :
_theResult___fst_exp__h120021 ;
assign _theResult___snd_fst_exp__h138453 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 ?
_theResult___fst_exp__h129668 :
_theResult___fst_exp__h138450 ;
assign _theResult___snd_fst_exp__h14380 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d619 ?
_theResult___fst_exp__h13822 :
_theResult___fst_exp__h14377 ;
assign _theResult___snd_fst_exp__h14383 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d618 ?
8'd0 :
_theResult___snd_fst_exp__h14380 ;
assign _theResult___snd_fst_exp__h14386 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d617 ?
_theResult___snd_fst_exp__h14383 :
8'd255 ;
assign _theResult___snd_fst_exp__h37247 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1235 ?
_theResult___fst_exp__h36485 :
_theResult___fst_exp__h37244 ;
assign _theResult___snd_fst_exp__h37250 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1233 ?
11'd0 :
_theResult___snd_fst_exp__h37247 ;
assign _theResult___snd_fst_exp__h37253 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1231 ?
_theResult___snd_fst_exp__h37250 :
11'd2047 ;
assign _theResult___snd_fst_exp__h46941 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1448 ?
_theResult___fst_exp__h46180 :
_theResult___fst_exp__h46938 ;
assign _theResult___snd_fst_exp__h46944 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1447 ?
11'd0 :
_theResult___snd_fst_exp__h46941 ;
assign _theResult___snd_fst_exp__h46947 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1446 ?
_theResult___snd_fst_exp__h46944 :
11'd2047 ;
assign _theResult___snd_fst_exp__h78892 =
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 ?
_theResult___fst_exp__h70277 :
_theResult___fst_exp__h78889 ;
assign _theResult___snd_fst_exp__h8208 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d264 ?
_theResult___fst_exp__h7649 :
_theResult___fst_exp__h8205 ;
assign _theResult___snd_fst_exp__h8211 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d261 ?
8'd0 :
_theResult___snd_fst_exp__h8208 ;
assign _theResult___snd_fst_exp__h8214 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d259 ?
_theResult___snd_fst_exp__h8211 :
8'd255 ;
assign _theResult___snd_fst_exp__h96799 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 ?
_theResult___fst_exp__h88130 :
_theResult___fst_exp__h96796 ;
assign _theResult___snd_fst_sfd__h100339 =
(value__h98456 == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h98453 ;
assign _theResult___snd_fst_sfd__h120025 =
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 ?
52'd0 :
_theResult___fst_sfd__h120022 ;
assign _theResult___snd_fst_sfd__h138454 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 ?
_theResult___fst_sfd__h129669 :
_theResult___fst_sfd__h138451 ;
assign _theResult___snd_fst_sfd__h14381 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d619 ?
_theResult___fst_sfd__h13823 :
_theResult___fst_sfd__h14378 ;
assign _theResult___snd_fst_sfd__h37248 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1235 ?
_theResult___fst_sfd__h36486 :
_theResult___fst_sfd__h37245 ;
assign _theResult___snd_fst_sfd__h46942 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1448 ?
_theResult___fst_sfd__h46181 :
_theResult___fst_sfd__h46939 ;
assign _theResult___snd_fst_sfd__h53867 =
(value__h49752[51:29] == 23'd0) ?
23'd2097152 :
value__h49752[51:29] ;
assign _theResult___snd_fst_sfd__h78893 =
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 ?
_theResult___fst_sfd__h70278 :
_theResult___fst_sfd__h78890 ;
assign _theResult___snd_fst_sfd__h8209 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d264 ?
_theResult___fst_sfd__h7650 :
_theResult___fst_sfd__h8206 ;
assign _theResult___snd_fst_sfd__h96800 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 ?
_theResult___fst_sfd__h88131 :
_theResult___fst_sfd__h96797 ;
assign ab__h156914 = dw_result$wget ;
assign b__h15050 = { value__h15052, 32'd0 } ;
assign b__h47607 = { value__h47609, 32'd0 } ;
assign din_inc___2_exp__h138485 = _theResult___fst_exp__h119265 + 11'd1 ;
assign din_inc___2_exp__h138515 = _theResult___fst_exp__h128838 + 11'd1 ;
assign din_inc___2_exp__h138539 = _theResult___fst_exp__h137669 + 11'd1 ;
assign din_inc___2_exp__h14416 = x__h13854[7:0] + 8'd1 ;
assign din_inc___2_exp__h37287 = x__h36517[10:0] + 11'd1 ;
assign din_inc___2_exp__h46977 = x__h46212[10:0] + 11'd1 ;
assign din_inc___2_exp__h8248 = x__h7681[7:0] + 8'd1 ;
assign din_inc___2_exp__h96827 = _theResult___fst_exp__h69650 + 8'd1 ;
assign din_inc___2_exp__h96851 = _theResult___fst_exp__h78336 + 8'd1 ;
assign din_inc___2_exp__h96881 = _theResult___fst_exp__h87503 + 8'd1 ;
assign din_inc___2_exp__h96905 = _theResult___fst_exp__h96218 + 8'd1 ;
assign guard__h111304 =
{ IF_theResult___snd19216_BIT_4_THEN_2_ELSE_0__q95[1],
{ _theResult___snd__h119216[3:0], 52'd0 } != 56'd0 } ;
assign guard__h120612 =
{ IF_sfdin28832_BIT_4_THEN_2_ELSE_0__q98[1],
{ sfdin__h128832[3:0], 52'd0 } != 56'd0 } ;
assign guard__h121210 = x__h121310 != 57'd0 ;
assign guard__h129679 =
{ IF_theResult___snd37615_BIT_4_THEN_2_ELSE_0__q101[1],
{ _theResult___snd__h137615[3:0], 52'd0 } != 56'd0 } ;
assign guard__h13313 =
{ IF_sfd___33303_BIT_8_THEN_2_ELSE_0__q20[1],
{ sfd___3__h13303[7:0], 23'd0 } != 31'd0 } ;
assign guard__h13839 =
{ IF_sfd___33303_BIT_7_THEN_2_ELSE_0__q21[1],
{ sfd___3__h13303[6:0], 24'd0 } != 31'd0 } ;
assign guard__h14983 =
{ IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827[23],
{ IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827[22:0],
33'd0 } !=
56'd0 } ;
assign guard__h15537 =
{ IF_x5726_BIT_24_THEN_2_ELSE_0__q31[1],
{ x__h15726[23:0], 32'd0 } != 56'd0 } ;
assign guard__h16600 =
{ IF_x6821_BIT_24_THEN_2_ELSE_0__q32[1],
{ x__h16821[23:0], 32'd0 } != 56'd0 } ;
assign guard__h35772 =
{ IF_sfd___35762_BIT_2_THEN_2_ELSE_0__q33[1],
{ sfd___3__h35762[1:0], 52'd0 } != 54'd0 } ;
assign guard__h36502 =
{ IF_sfd___35762_BIT_1_THEN_2_ELSE_0__q34[1],
{ sfd___3__h35762[0], 53'd0 } != 54'd0 } ;
assign guard__h45468 =
{ IF_sfd___35458_BIT_2_THEN_2_ELSE_0__q47[1],
{ sfd___3__h45458[1:0], 52'd0 } != 54'd0 } ;
assign guard__h46197 =
{ IF_sfd___35458_BIT_1_THEN_2_ELSE_0__q48[1],
{ sfd___3__h45458[0], 53'd0 } != 54'd0 } ;
assign guard__h47540 =
{ IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618[52],
{ IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618[51:0],
33'd0 } !=
85'd0 } ;
assign guard__h48094 =
{ IF_x8283_BIT_53_THEN_2_ELSE_0__q58[1],
{ x__h48283[52:0], 32'd0 } != 85'd0 } ;
assign guard__h49140 =
{ IF_x9361_BIT_53_THEN_2_ELSE_0__q59[1],
{ x__h49361[52:0], 32'd0 } != 85'd0 } ;
assign guard__h61553 =
{ IF_sfdin9644_BIT_33_THEN_2_ELSE_0__q61[1],
{ sfdin__h69644[32:0], 23'd0 } != 56'd0 } ;
assign guard__h70288 =
{ IF_theResult___snd8287_BIT_33_THEN_2_ELSE_0__q63[1],
{ _theResult___snd__h78287[32:0], 23'd0 } != 56'd0 } ;
assign guard__h7136 =
{ IF_sfd___3126_BIT_8_THEN_2_ELSE_0__q6[1],
{ sfd___3__h7126[7:0], 23'd0 } != 31'd0 } ;
assign guard__h7666 =
{ IF_sfd___3126_BIT_7_THEN_2_ELSE_0__q7[1],
{ sfd___3__h7126[6:0], 24'd0 } != 31'd0 } ;
assign guard__h79277 =
{ IF_sfdin7497_BIT_33_THEN_2_ELSE_0__q66[1],
{ sfdin__h87497[32:0], 23'd0 } != 56'd0 } ;
assign guard__h79875 = x__h79975 != 57'd0 ;
assign guard__h88141 =
{ IF_theResult___snd6164_BIT_33_THEN_2_ELSE_0__q69[1],
{ _theResult___snd__h96164[32:0], 23'd0 } != 56'd0 } ;
assign out1___1__h15477 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827[56:24] +
33'd1 ;
assign out1___1__h48034 =
IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618[85:53] +
33'd1 ;
assign out___1_sfd__h98453 = { value__h98456, 29'd0 } ;
assign out_exp__h119923 =
_theResult___snd__h119216[5] ?
_theResult___exp__h119920 :
_theResult___fst_exp__h119265 ;
assign out_exp__h129570 =
sfdin__h128832[5] ?
_theResult___exp__h129567 :
_theResult___fst_exp__h128838 ;
assign out_exp__h13729 =
sfd___3__h13303[9] ? _theResult___exp__h13726 : 8'd0 ;
assign out_exp__h138352 =
_theResult___snd__h137615[5] ?
_theResult___exp__h138349 :
_theResult___fst_exp__h137669 ;
assign out_exp__h14281 =
sfd___3__h13303[8] ? _theResult___exp__h14278 : x__h13854[7:0] ;
assign out_exp__h36391 =
sfd___3__h35762[3] ? _theResult___exp__h36388 : 11'd0 ;
assign out_exp__h37147 =
sfd___3__h35762[2] ? _theResult___exp__h37144 : x__h36517[10:0] ;
assign out_exp__h46087 =
sfd___3__h45458[3] ? _theResult___exp__h46084 : 11'd0 ;
assign out_exp__h46842 =
sfd___3__h45458[2] ? _theResult___exp__h46839 : x__h46212[10:0] ;
assign out_exp__h70179 =
sfdin__h69644[34] ?
_theResult___exp__h70176 :
_theResult___fst_exp__h69650 ;
assign out_exp__h7555 = sfd___3__h7126[9] ? _theResult___exp__h7552 : 8'd0 ;
assign out_exp__h78791 =
_theResult___snd__h78287[34] ?
_theResult___exp__h78788 :
_theResult___fst_exp__h78336 ;
assign out_exp__h8108 =
sfd___3__h7126[8] ? _theResult___exp__h8105 : x__h7681[7:0] ;
assign out_exp__h88032 =
sfdin__h87497[34] ?
_theResult___exp__h88029 :
_theResult___fst_exp__h87503 ;
assign out_exp__h96698 =
_theResult___snd__h96164[34] ?
_theResult___exp__h96695 :
_theResult___fst_exp__h96218 ;
assign out_sfd__h119924 =
_theResult___snd__h119216[5] ?
_theResult___sfd__h119921 :
_theResult___snd__h119216[56:5] ;
assign out_sfd__h129571 =
sfdin__h128832[5] ?
_theResult___sfd__h129568 :
sfdin__h128832[56:5] ;
assign out_sfd__h13730 =
sfd___3__h13303[9] ?
_theResult___sfd__h13727 :
sfd___3__h13303[31:9] ;
assign out_sfd__h138353 =
_theResult___snd__h137615[5] ?
_theResult___sfd__h138350 :
_theResult___snd__h137615[56:5] ;
assign out_sfd__h14282 =
sfd___3__h13303[8] ?
_theResult___sfd__h14279 :
sfd___3__h13303[30:8] ;
assign out_sfd__h36392 =
sfd___3__h35762[3] ?
_theResult___sfd__h36389 :
sfd___3__h35762[54:3] ;
assign out_sfd__h37148 =
sfd___3__h35762[2] ?
_theResult___sfd__h37145 :
sfd___3__h35762[53:2] ;
assign out_sfd__h46088 =
sfd___3__h45458[3] ?
_theResult___sfd__h46085 :
sfd___3__h45458[54:3] ;
assign out_sfd__h46843 =
sfd___3__h45458[2] ?
_theResult___sfd__h46840 :
sfd___3__h45458[53:2] ;
assign out_sfd__h70180 =
sfdin__h69644[34] ?
_theResult___sfd__h70177 :
sfdin__h69644[56:34] ;
assign out_sfd__h7556 =
sfd___3__h7126[9] ?
_theResult___sfd__h7553 :
sfd___3__h7126[31:9] ;
assign out_sfd__h78792 =
_theResult___snd__h78287[34] ?
_theResult___sfd__h78789 :
_theResult___snd__h78287[56:34] ;
assign out_sfd__h8109 =
sfd___3__h7126[8] ?
_theResult___sfd__h8106 :
sfd___3__h7126[30:8] ;
assign out_sfd__h88033 =
sfdin__h87497[34] ?
_theResult___sfd__h88030 :
sfdin__h87497[56:34] ;
assign out_sfd__h96699 =
_theResult___snd__h96164[34] ?
_theResult___sfd__h96696 :
_theResult___snd__h96164[56:34] ;
assign requestR_BITS_126_TO_116_745_EQ_0_759_AND_requ_ETC___d3766 =
requestR[126:116] == 11'd0 && requestR[115:64] == 52'd0 &&
requestR[127] &&
requestR[190:180] == 11'd0 &&
requestR[179:128] == 52'd0 &&
!requestR[191] ;
assign requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28 =
{ requestR[127:96] == 32'hFFFFFFFF && requestR[95],
(requestR[127:96] == 32'hFFFFFFFF) ?
requestR[94:64] :
31'h7FC00000 } ;
assign requestR_BITS_159_TO_128__q1 = requestR[159:128] ;
assign requestR_BITS_179_TO_128_598_ULE_requestR_BITS_ETC___d3778 =
requestR[179:128] <= requestR[115:64] ;
assign requestR_BITS_179_TO_128_598_ULT_requestR_BITS_ETC___d3783 =
requestR[179:128] < requestR[115:64] ;
assign requestR_BITS_190_TO_180_596_EQ_0_607_AND_requ_ETC___d3762 =
requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0 &&
requestR[191] &&
requestR[126:116] == 11'd0 &&
requestR[115:64] == 52'd0 &&
!requestR[127] ;
assign requestR_BITS_190_TO_180_596_EQ_0_607_AND_requ_ETC___d3836 =
requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0 &&
requestR[126:116] == 11'd0 &&
requestR[115:64] == 52'd0 ||
(!requestR[191] || requestR[127]) &&
(requestR[191] || !requestR[127]) &&
(requestR[191] ?
requestR_BITS_190_TO_180_596_ULE_requestR_BITS_ETC___d3831 :
NOT_requestR_BITS_190_TO_180_596_ULT_requestR__ETC___d3832) ;
assign requestR_BITS_190_TO_180_596_EQ_2047_597_AND_0_ETC___d1747 =
requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 ||
requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0 ||
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
(NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1708[23] ||
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1710 &&
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1729 &&
x__h49361[85:54] == 32'hFFFFFFFF) ;
assign requestR_BITS_190_TO_180_596_EQ_2047_597_AND_0_ETC___d1758 =
{ requestR_BITS_190_TO_180_596_EQ_2047_597_AND_0_ETC___d1747,
3'd0,
(requestR[190:180] != 11'd2047 ||
requestR[179:128] == 52'd0) &&
(requestR[190:180] != 11'd2047 ||
requestR[179:128] != 52'd0) &&
NOT_requestR_BITS_190_TO_180_596_EQ_0_607_613__ETC___d1752 } ==
5'd0 ||
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_0_ETC___d1747 ;
assign requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3754 =
requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 &&
!requestR[179] &&
requestR[126:116] == 11'd2047 &&
requestR[115:64] != 52'd0 &&
!requestR[115] ;
assign requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3799 =
requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 &&
!requestR[179] ||
requestR[126:116] == 11'd2047 && requestR[115:64] != 52'd0 &&
!requestR[115] ;
assign requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3821 =
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3799 ||
requestR[190:180] == 11'd2047 && requestR[179] ||
requestR[126:116] == 11'd2047 && requestR[115] ;
assign requestR_BITS_190_TO_180_596_EQ_requestR_BITS__ETC___d3777 =
requestR[190:180] == requestR[126:116] ;
assign requestR_BITS_190_TO_180_596_MINUS_1023___d1609 =
requestR[190:180] - 11'd1023 ;
assign requestR_BITS_190_TO_180_596_ULE_requestR_BITS_ETC___d3775 =
requestR[190:180] <= requestR[126:116] ;
assign requestR_BITS_190_TO_180_596_ULE_requestR_BITS_ETC___d3831 =
requestR_BITS_190_TO_180_596_ULE_requestR_BITS_ETC___d3775 &&
(!requestR_BITS_190_TO_180_596_EQ_requestR_BITS__ETC___d3777 ||
requestR_BITS_179_TO_128_598_ULE_requestR_BITS_ETC___d3778) &&
!requestR_BITS_190_TO_180_596_ULT_requestR_BITS_ETC___d3782 &&
(!requestR_BITS_190_TO_180_596_EQ_requestR_BITS__ETC___d3777 ||
!requestR_BITS_179_TO_128_598_ULT_requestR_BITS_ETC___d3783) ;
assign requestR_BITS_190_TO_180_596_ULT_requestR_BITS_ETC___d3782 =
requestR[190:180] < requestR[126:116] ;
assign requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_AND_ETC___d1026 =
requestR[191:160] == 32'hFFFFFFFF && requestR[159] &&
(requestR[127:96] != 32'hFFFFFFFF || !requestR[95]) ||
(requestR[191:160] == 32'hFFFFFFFF && requestR[159] ||
requestR[127:96] != 32'hFFFFFFFF ||
!requestR[95]) &&
IF_NOT_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1024 ;
assign requestR_BIT_158_88_OR_requestR_BIT_157_90_OR__ETC___d770 =
requestR[158] || requestR[157] || requestR[156] ||
requestR[155] ||
requestR[154] ||
requestR[153] ||
requestR[152] ||
requestR[151] ||
requestR[150] ||
requestR[149] ||
requestR[148] ||
requestR[147] ||
requestR[146] ||
requestR[145] ||
requestR[144] ||
requestR[143] ||
requestR[142] ||
requestR[141] ||
requestR[140] ||
requestR[139] ||
requestR[138] ||
requestR[137] ||
requestR[136] ||
requestR[135] ||
requestR[134] ||
requestR[133] ||
requestR[132] ||
requestR[131] ||
requestR[130] ||
requestR[129] ||
requestR[128] ;
assign requestR_BIT_159_6_OR_requestR_BIT_158_88_OR_r_ETC___d792 =
(requestR[159] ||
requestR_BIT_158_88_OR_requestR_BIT_157_90_OR__ETC___d770) &&
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d617 &&
!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d618 &&
IF_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THE_ETC___d789 ;
assign res___1__h155823 =
(requestR[190:180] == 11'd2047 && requestR[179]) ?
64'd512 :
64'd256 ;
assign res___1__h156261 = requestR[191] ? 64'd1 : 64'd128 ;
assign res___1__h156271 = requestR[191] ? 64'd8 : 64'd16 ;
assign res___1__h156290 = requestR[191] ? 64'd4 : 64'd32 ;
assign res___1__h26221 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816[22]) ?
64'd512 :
64'd256 ;
assign res___1__h26457 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
64'd1 :
64'd128 ;
assign res___1__h26467 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
64'd8 :
64'd16 ;
assign res___1__h26486 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
64'd4 :
64'd32 ;
assign res__h139089 =
{ IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3650,
x__h98397,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3614 } ;
assign res__h143531 =
NOT_requestR_BITS_190_TO_180_596_EQ_2047_597_6_ETC___d3790 ?
requestR[191:128] :
requestR[127:64] ;
assign res__h148079 =
NOT_requestR_BITS_190_TO_180_596_EQ_2047_597_6_ETC___d3790 ?
requestR[127:64] :
requestR[191:128] ;
assign res__h150783 =
((requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) &&
(requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) &&
requestR_BITS_190_TO_180_596_EQ_0_607_AND_requ_ETC___d3836) ?
64'd1 :
64'd0 ;
assign res__h153478 =
NOT_requestR_BITS_190_TO_180_596_EQ_2047_597_6_ETC___d3790 ?
64'd1 :
64'd0 ;
assign res__h155355 =
NOT_requestR_BITS_190_TO_180_596_EQ_2047_597_6_ETC___d3855 ?
64'd1 :
64'd0 ;
assign res__h156306 = requestR[191] ? 64'd2 : 64'd64 ;
assign res__h156487 = { 32'hFFFFFFFF, fpu$response_get[36:5] } ;
assign res__h17825 =
{ 32'hFFFFFFFF,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28 } ;
assign res__h18062 =
{ 32'hFFFFFFFF,
requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } ;
assign res__h23434 =
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1091 ?
64'd1 :
64'd0 ;
assign res__h24917 =
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1028 ?
64'd1 :
64'd0 ;
assign res__h25986 =
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1109 ?
64'd1 :
64'd0 ;
assign res__h26502 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
64'd2 :
64'd64 ;
assign res__h97284 = { 32'hFFFFFFFF, x__h97290 } ;
assign result__h121215 =
{ _0b0_CONCAT_NOT_IF_requestR_BITS_191_TO_160_4_E_ETC___d3152[56:1],
_0b0_CONCAT_NOT_IF_requestR_BITS_191_TO_160_4_E_ETC___d3152[0] |
guard__h121210 } ;
assign result__h79880 =
{ _0b0_CONCAT_NOT_requestR_BITS_190_TO_180_596_EQ_ETC___d2318[56:1],
_0b0_CONCAT_NOT_requestR_BITS_190_TO_180_596_EQ_ETC___d2318[0] |
guard__h79875 } ;
assign sV1_exp__h815 =
(requestR[191:160] == 32'hFFFFFFFF) ?
requestR[158:151] :
8'd255 ;
assign sV1_sfd__h816 =
(requestR[191:160] == 32'hFFFFFFFF) ?
requestR[150:128] :
23'd4194304 ;
assign sV2_exp__h918 =
(requestR[127:96] == 32'hFFFFFFFF) ? requestR[94:87] : 8'd255 ;
assign sV2_sfd__h919 =
(requestR[127:96] == 32'hFFFFFFFF) ?
requestR[86:64] :
23'd4194304 ;
assign sfd___3__h13303 =
requestR[159:128] <<
IF_requestR_BIT_159_6_THEN_0_ELSE_IF_requestR__ETC___d613 ;
assign sfd___3__h35762 =
sfd__h27761 <<
IF_IF_requestR_BIT_159_6_THEN_NEG_requestR_BIT_ETC___d1227 ;
assign sfd___3__h45458 =
sfd__h37706 <<
IF_requestR_BIT_159_6_THEN_0_ELSE_IF_requestR__ETC___d1442 ;
assign sfd___3__h7126 =
sfd__h2222 <<
IF_IF_requestR_BIT_159_6_THEN_NEG_requestR_BIT_ETC___d255 ;
assign sfd__h119283 =
{ 1'b0,
_theResult___fst_exp__h119265 != 11'd0,
_theResult___snd__h119216[56:5] } +
54'd1 ;
assign sfd__h128930 =
{ 1'b0,
_theResult___fst_exp__h128838 != 11'd0,
sfdin__h128832[56:5] } +
54'd1 ;
assign sfd__h13330 = { 2'd0, sfd___3__h13303[31:9] } + 25'd1 ;
assign sfd__h137688 =
{ 1'b0,
_theResult___fst_exp__h137669 != 11'd0,
_theResult___snd__h137615[56:5] } +
54'd1 ;
assign sfd__h13869 =
{ 1'b0, x__h13854[7:0] != 8'd0, sfd___3__h13303[30:8] } + 25'd1 ;
assign sfd__h2222 = requestR[159] ? -requestR[159:128] : requestR[159:128] ;
assign sfd__h27761 = { sfd__h2222, 23'd0 } ;
assign sfd__h35789 = { 2'd0, sfd___3__h35762[54:3] } + 54'd1 ;
assign sfd__h36532 =
{ 1'b0, x__h36517[10:0] != 11'd0, sfd___3__h35762[53:2] } +
54'd1 ;
assign sfd__h37706 = { requestR[159:128], 23'd0 } ;
assign sfd__h45485 = { 2'd0, sfd___3__h45458[54:3] } + 54'd1 ;
assign sfd__h46227 =
{ 1'b0, x__h46212[10:0] != 11'd0, sfd___3__h45458[53:2] } +
54'd1 ;
assign sfd__h53913 = { value__h47609, 3'd0 } ;
assign sfd__h69742 =
{ 1'b0,
_theResult___fst_exp__h69650 != 8'd0,
sfdin__h69644[56:34] } +
25'd1 ;
assign sfd__h7153 = { 2'd0, sfd___3__h7126[31:9] } + 25'd1 ;
assign sfd__h7696 =
{ 1'b0, x__h7681[7:0] != 8'd0, sfd___3__h7126[30:8] } + 25'd1 ;
assign sfd__h78354 =
{ 1'b0,
_theResult___fst_exp__h78336 != 8'd0,
_theResult___snd__h78287[56:34] } +
25'd1 ;
assign sfd__h87595 =
{ 1'b0,
_theResult___fst_exp__h87503 != 8'd0,
sfdin__h87497[56:34] } +
25'd1 ;
assign sfd__h96237 =
{ 1'b0,
_theResult___fst_exp__h96218 != 8'd0,
_theResult___snd__h96164[56:34] } +
25'd1 ;
assign sfdin__h128832 =
_theResult____h120602[56] ?
_theResult___snd__h128849 :
_theResult___snd__h128860 ;
assign sfdin__h69644 =
_theResult____h61543[56] ?
_theResult___snd__h69661 :
_theResult___snd__h69672 ;
assign sfdin__h87497 =
_theResult____h79267[56] ?
_theResult___snd__h87514 :
_theResult___snd__h87525 ;
assign value__h15052 = { 1'b0, sV1_exp__h815 != 8'd0, sV1_sfd__h816 } ;
assign value__h47609 =
{ 1'b0, requestR[190:180] != 11'd0, requestR[179:128] } ;
assign value__h49752 =
(requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 &&
!requestR[179]) ?
_theResult___fst_sfd__h50209 :
requestR[179:128] ;
assign value__h98456 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 &&
!sV1_sfd__h816[22]) ?
_theResult___fst_sfd__h98711 :
sV1_sfd__h816 ;
assign x__h121310 = b__h15050 << x__h121343 ;
assign x__h121343 =
12'd57 -
_3074_MINUS_SEXT_IF_requestR_BITS_191_TO_160_4__ETC___d3148 ;
assign x__h13854 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d616 +
9'd127 ;
assign x__h139191 =
{ IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3688,
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 != 23'd0) &&
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3695,
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 != 23'd0) &&
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3709,
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 != 23'd0) &&
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3721,
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 != 23'd0) &&
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3733 } ;
assign x__h140114 =
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3754 ?
64'h7FF8000000000000 :
((requestR[190:180] == 11'd2047 &&
requestR[179:128] != 52'd0 &&
!requestR[179]) ?
requestR[127:64] :
((requestR[126:116] == 11'd2047 &&
requestR[115:64] != 52'd0 &&
!requestR[115]) ?
requestR[191:128] :
((requestR[190:180] == 11'd2047 && requestR[179] &&
requestR[126:116] == 11'd2047 &&
requestR[115]) ?
64'h7FF8000000000000 :
((requestR[190:180] == 11'd2047 && requestR[179]) ?
requestR[127:64] :
IF_requestR_BITS_126_TO_116_745_EQ_2047_746_AN_ETC___d3793)))) ;
assign x__h143663 =
{ requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3799,
4'd0 } ;
assign x__h144662 =
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3754 ?
64'h7FF8000000000000 :
((requestR[190:180] == 11'd2047 &&
requestR[179:128] != 52'd0 &&
!requestR[179]) ?
requestR[127:64] :
((requestR[126:116] == 11'd2047 &&
requestR[115:64] != 52'd0 &&
!requestR[115]) ?
requestR[191:128] :
((requestR[190:180] == 11'd2047 && requestR[179] &&
requestR[126:116] == 11'd2047 &&
requestR[115]) ?
64'h7FF8000000000000 :
((requestR[190:180] == 11'd2047 && requestR[179]) ?
requestR[127:64] :
((requestR[126:116] == 11'd2047 && requestR[115]) ?
requestR[191:128] :
IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d3807))))) ;
assign x__h14520 =
{ 2'd0,
NOT_requestR_BITS_159_TO_128_24_EQ_0_25_26_AND_ETC___d781,
requestR[159:128] != 32'd0 &&
(requestR[159] ||
requestR_BIT_158_88_OR_requestR_BIT_157_90_OR__ETC___d770) &&
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d617 &&
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d618,
requestR[159:128] != 32'd0 &&
requestR_BIT_159_6_OR_requestR_BIT_158_88_OR_r_ETC___d792 } ;
assign x__h14804 = { {32{x__h14807[31]}}, x__h14807 } ;
assign x__h14807 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d814 ?
32'h7FFFFFFF :
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d886 ;
assign x__h149106 =
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3821 ?
64'd0 :
res__h150783 ;
assign x__h151801 =
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3821 ?
64'd0 :
res__h153478 ;
assign x__h153497 =
{ requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 ||
requestR[126:116] == 11'd2047 && requestR[115:64] != 52'd0,
4'd0 } ;
assign x__h153678 =
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3821 ?
64'd0 :
res__h155355 ;
assign x__h155805 =
(requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ?
res___1__h155823 :
((requestR[190:180] == 11'd2047 &&
requestR[179:128] == 52'd0) ?
res___1__h156261 :
IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d3878) ;
assign x__h156455 =
fpu$response_get[69] ? res__h156487 : fpu$response_get[68:5] ;
assign x__h15726 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827 >>
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d853 |
~(57'h1FFFFFFFFFFFFFF >>
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d853) &
{57{IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827[56]}} ;
assign x__h16140 =
{ sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 ||
sV1_exp__h815 == 8'd255 && sV1_sfd__h816 == 23'd0 ||
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d897,
3'd0,
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 != 23'd0) &&
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d908 } ;
assign x__h16397 = { {32{x__h16400[31]}}, x__h16400 } ;
assign x__h16400 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d814 ?
32'hFFFFFFFF :
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d948 ;
assign x__h16821 =
{ sV1_exp__h815 != 8'd0, sV1_sfd__h816, 33'd0 } >>
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d917 ;
assign x__h16899 =
{ (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d967 :
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d956,
3'd0,
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 != 23'd0) &&
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d961 } ;
assign x__h17147 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d990 ?
64'hFFFFFFFF7FC00000 :
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1036 ;
assign x__h1773 = { 32'hFFFFFFFF, x__h1779 } ;
assign x__h1779 =
{ requestR[127:96] == 32'hFFFFFFFF && requestR[95],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } ;
assign x__h19186 =
{ IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1038,
4'd0 } ;
assign x__h1919 = { 32'hFFFFFFFF, x__h1925 } ;
assign x__h1925 =
{ requestR[127:96] != 32'hFFFFFFFF || !requestR[95],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } ;
assign x__h19781 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d990 ?
64'hFFFFFFFF7FC00000 :
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1052 ;
assign x__h2053 = { 32'hFFFFFFFF, x__h2059 } ;
assign x__h2059 =
{ (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) !=
(requestR[127:96] == 32'hFFFFFFFF && requestR[95]),
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } ;
assign x__h2201 = { 32'hFFFFFFFF, x__h2207 } ;
assign x__h2207 =
{ requestR[159:128] != 32'd0 &&
(NOT_IF_requestR_BIT_159_6_THEN_NEG_requestR_BI_ETC___d263 ?
requestR[159] :
IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d325),
IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d385,
(requestR[159:128] == 32'd0 ||
NOT_IF_requestR_BIT_159_6_THEN_NEG_requestR_BI_ETC___d263) ?
23'd0 :
_theResult___snd_fst_sfd__h8209 } ;
assign x__h22306 = { 32'hFFFFFFFF, requestR[159:128] } ;
assign x__h22427 =
{ {32{requestR_BITS_159_TO_128__q1[31]}},
requestR_BITS_159_TO_128__q1 } ;
assign x__h22565 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1075 ?
64'd0 :
res__h23434 ;
assign x__h24048 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1075 ?
64'd0 :
res__h24917 ;
assign x__h24936 =
{ sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 ||
sV2_exp__h918 == 8'd255 && sV2_sfd__h919 != 23'd0,
4'd0 } ;
assign x__h25117 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1075 ?
64'd0 :
res__h25986 ;
assign x__h26203 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0) ?
res___1__h26221 :
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1123 ;
assign x__h27370 = { requestR[127], requestR[190:128] } ;
assign x__h27492 = { !requestR[127], requestR[190:128] } ;
assign x__h27616 = { requestR[191] != requestR[127], requestR[190:128] } ;
assign x__h27746 =
{ requestR[159:128] != 32'd0 &&
IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_15_ETC___d1287,
(requestR[159:128] == 32'd0) ?
11'd0 :
_theResult___snd_fst_exp__h37253,
IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d1384 } ;
assign x__h36517 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1230 +
12'd1023 ;
assign x__h37409 =
{ 2'd0,
requestR[159:128] != 32'd0 &&
(!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1231 ||
!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1233 &&
!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1235 &&
_theResult___fst_exp__h37244 == 11'd2047 &&
_theResult___fst_sfd__h37245 == 52'd0),
requestR[159:128] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1231 &&
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1233,
requestR[159:128] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1231 &&
!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1233 &&
IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d1401 } ;
assign x__h37694 =
{ 1'd0,
(requestR[159:128] == 32'd0) ?
11'd0 :
_theResult___snd_fst_exp__h46947,
IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d1567 } ;
assign x__h46212 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1445 +
12'd1023 ;
assign x__h47077 =
{ 2'd0,
requestR[159:128] != 32'd0 &&
(!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1446 ||
!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1447 &&
!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1448 &&
_theResult___fst_exp__h46938 == 11'd2047 &&
_theResult___fst_sfd__h46939 == 52'd0),
requestR[159:128] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1446 &&
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1447,
requestR[159:128] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1446 &&
!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1447 &&
IF_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THE_ETC___d1584 } ;
assign x__h47361 = { {32{x__h47364[31]}}, x__h47364 } ;
assign x__h47364 =
(requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 ||
!requestR[191] && requestR[190:180] == 11'd2047 &&
requestR[179:128] == 52'd0) ?
32'h7FFFFFFF :
IF_requestR_BITS_190_TO_180_596_EQ_2047_597_AN_ETC___d1677 ;
assign x__h48283 =
IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618 >>
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1644 |
~(86'h3FFFFFFFFFFFFFFFFFFFFF >>
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1644) &
{86{IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618[85]}} ;
assign x__h48680 =
{ requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 ||
requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0 ||
NOT_requestR_BITS_190_TO_180_596_EQ_0_607_613__ETC___d1688,
3'd0,
(requestR[190:180] != 11'd2047 ||
requestR[179:128] == 52'd0) &&
(requestR[190:180] != 11'd2047 ||
requestR[179:128] != 52'd0) &&
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1699 } ;
assign x__h48937 = { {32{x__h48940[31]}}, x__h48940 } ;
assign x__h48940 =
(requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 ||
!requestR[191] && requestR[190:180] == 11'd2047 &&
requestR[179:128] == 52'd0) ?
32'hFFFFFFFF :
(requestR[191] ?
32'd0 :
((requestR[190:180] == 11'd2047 &&
requestR[179:128] == 52'd0) ?
32'hFFFFFFFF :
IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d1737)) ;
assign x__h49361 =
{ requestR[190:180] != 11'd0, requestR[179:128], 33'd0 } >>
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1708 ;
assign x__h49439 =
{ requestR[191] ?
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_0_ETC___d1758 :
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_0_ETC___d1747,
3'd0,
(requestR[190:180] != 11'd2047 ||
requestR[179:128] == 52'd0) &&
(requestR[190:180] != 11'd2047 ||
requestR[179:128] != 52'd0) &&
NOT_requestR_BITS_190_TO_180_596_EQ_0_607_613__ETC___d1752 } ;
assign x__h49683 =
(x__h49692 == 8'd255 &&
IF_requestR_BITS_190_TO_180_596_EQ_2047_597_AN_ETC___d2798[22]) ?
64'hFFFFFFFF7FC00000 :
res__h97284 ;
assign x__h49692 =
(requestR[190:180] == 11'd2047) ?
8'd255 :
_theResult___fst_exp__h96808 ;
assign x__h7681 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d258 +
9'd127 ;
assign x__h79975 = sfd__h53913 << x__h80008 ;
assign x__h80008 =
12'd57 -
_3970_MINUS_SEXT_requestR_BITS_190_TO_180_596_M_ETC___d2314 ;
assign x__h8374 =
{ 2'd0,
requestR[159:128] != 32'd0 &&
IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d466,
requestR[159:128] != 32'd0 &&
IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d469,
requestR[159:128] != 32'd0 &&
IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d478 } ;
assign x__h8662 =
{ 33'h1FFFFFFFE,
IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d703,
(requestR[159:128] == 32'd0 ||
!requestR[159] &&
NOT_requestR_BIT_158_88_89_AND_NOT_requestR_BI_ETC___d579 ||
!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d617 ||
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d618) ?
23'd0 :
_theResult___snd_fst_sfd__h14381 } ;
assign x__h97290 =
{ (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 ||
(requestR[190:180] == 11'd2047 ||
requestR[190:180] == 11'd0) &&
requestR[179:128] == 52'd0) ?
requestR[191] :
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2840,
x__h49692,
IF_requestR_BITS_190_TO_180_596_EQ_2047_597_AN_ETC___d2798 } ;
assign x__h97405 =
{ (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ?
requestR[190:180] == 11'd2047 &&
requestR[179:128] != 52'd0 &&
!requestR[179] :
(requestR[190:180] != 11'd2047 ||
requestR[179:128] != 52'd0) &&
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2891,
(requestR[190:180] != 11'd2047 ||
requestR[179:128] == 52'd0) &&
(requestR[190:180] != 11'd2047 ||
requestR[179:128] != 52'd0) &&
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2902,
(requestR[190:180] != 11'd2047 ||
requestR[179:128] == 52'd0) &&
(requestR[190:180] != 11'd2047 ||
requestR[179:128] != 52'd0) &&
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2918,
(requestR[190:180] != 11'd2047 ||
requestR[179:128] == 52'd0) &&
(requestR[190:180] != 11'd2047 ||
requestR[179:128] != 52'd0) &&
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2931,
(requestR[190:180] != 11'd2047 ||
requestR[179:128] == 52'd0) &&
(requestR[190:180] != 11'd2047 ||
requestR[179:128] != 52'd0) &&
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2944 } ;
assign x__h98388 =
(x__h98397 == 11'd2047 &&
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3614[51]) ?
64'h7FF8000000000000 :
res__h139089 ;
assign x__h98397 =
(sV1_exp__h815 == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h138462 ;
always@(requestR)
begin
case (requestR[194:192])
3'h1: CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = 8'd254;
3'h2:
CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 =
requestR[191] ? 8'd255 : 8'd254;
3'h3:
CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 =
requestR[191] ? 8'd254 : 8'd255;
default: CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = 8'd0;
endcase
end
always@(requestR)
begin
case (requestR[194:192])
3'h1:
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 =
23'd8388607;
3'h2:
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 =
requestR[191] ? 23'd0 : 23'd8388607;
3'h3:
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 =
requestR[191] ? 23'd8388607 : 23'd0;
default: CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = 23'd0;
endcase
end
always@(requestR)
begin
case (requestR[194:192])
3'h1: CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = 11'd2046;
3'h2:
CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
11'd2047 :
11'd2046;
3'h3:
CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
11'd2046 :
11'd2047;
default: CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = 11'd0;
endcase
end
always@(requestR)
begin
case (requestR[194:192])
3'h1:
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 =
52'hFFFFFFFFFFFFF;
3'h2:
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
52'd0 :
52'hFFFFFFFFFFFFF;
3'h3:
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
52'hFFFFFFFFFFFFF :
52'd0;
default: CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = 52'd0;
endcase
end
always@(requestR)
begin
case (requestR[194:192])
3'h0:
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40 =
requestR[194:192];
3'h1: IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40 = 3'd4;
3'h2: IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40 = 3'd3;
3'h3: IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40 = 3'd2;
3'h4: IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40 = 3'd1;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40 =
3'd0;
endcase
end
always@(guard__h7136 or requestR)
begin
case (guard__h7136)
2'b0, 2'b01, 2'b10:
CASE_guard136_0b0_requestR_BIT_159_0b1_request_ETC__q8 =
requestR[159];
2'd3:
CASE_guard136_0b0_requestR_BIT_159_0b1_request_ETC__q8 =
guard__h7136 == 2'b11 && requestR[159];
endcase
end
always@(requestR or guard__h7136)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9 =
requestR[159];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9 =
(guard__h7136 == 2'b0) ?
requestR[159] :
(guard__h7136 == 2'b01 || guard__h7136 == 2'b10 ||
guard__h7136 == 2'b11) &&
requestR[159];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9 =
requestR[194:192] == 3'h1 && requestR[159];
endcase
end
always@(guard__h7666 or requestR)
begin
case (guard__h7666)
2'b0, 2'b01, 2'b10:
CASE_guard666_0b0_requestR_BIT_159_0b1_request_ETC__q10 =
requestR[159];
2'd3:
CASE_guard666_0b0_requestR_BIT_159_0b1_request_ETC__q10 =
guard__h7666 == 2'b11 && requestR[159];
endcase
end
always@(requestR or guard__h7666)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 =
requestR[159];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 =
(guard__h7666 == 2'b0) ?
requestR[159] :
(guard__h7666 == 2'b01 || guard__h7666 == 2'b10 ||
guard__h7666 == 2'b11) &&
requestR[159];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 =
requestR[194:192] == 3'h1 && requestR[159];
endcase
end
always@(guard__h7136 or _theResult___exp__h7552)
begin
case (guard__h7136)
2'b0: CASE_guard136_0b0_0_0b1_theResult___exp552_0b1_ETC__q12 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard136_0b0_0_0b1_theResult___exp552_0b1_ETC__q12 =
_theResult___exp__h7552;
endcase
end
always@(requestR or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d347 or
guard__h7136 or
_theResult___exp__h7552 or
CASE_guard136_0b0_0_0b1_theResult___exp552_0b1_ETC__q12)
begin
case (requestR[194:192])
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d350 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d347;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d350 =
(guard__h7136 == 2'b0 || requestR[159]) ?
8'd0 :
_theResult___exp__h7552;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d350 =
CASE_guard136_0b0_0_0b1_theResult___exp552_0b1_ETC__q12;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d350 =
8'd0;
endcase
end
always@(guard__h7136 or out_exp__h7555 or _theResult___exp__h7552)
begin
case (guard__h7136)
2'b0, 2'b01:
CASE_guard136_0b0_0_0b1_0_0b10_out_exp555_0b11_ETC__q13 = 8'd0;
2'b10:
CASE_guard136_0b0_0_0b1_0_0b10_out_exp555_0b11_ETC__q13 =
out_exp__h7555;
2'b11:
CASE_guard136_0b0_0_0b1_0_0b10_out_exp555_0b11_ETC__q13 =
_theResult___exp__h7552;
endcase
end
always@(guard__h7666 or x__h7681 or _theResult___exp__h8105)
begin
case (guard__h7666)
2'b0:
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_theResu_ETC__q14 =
x__h7681[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_theResu_ETC__q14 =
_theResult___exp__h8105;
endcase
end
always@(requestR or
x__h7681 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d375 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d373 or
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_theResu_ETC__q14)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d379 =
x__h7681[7:0];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d379 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d375;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d379 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d373;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d379 =
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_theResu_ETC__q14;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d379 =
8'd0;
endcase
end
always@(guard__h7666 or
x__h7681 or out_exp__h8108 or _theResult___exp__h8105)
begin
case (guard__h7666)
2'b0, 2'b01:
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_x681_BI_ETC__q15 =
x__h7681[7:0];
2'b10:
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_x681_BI_ETC__q15 =
out_exp__h8108;
2'b11:
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_x681_BI_ETC__q15 =
_theResult___exp__h8105;
endcase
end
always@(guard__h7136 or sfd___3__h7126 or _theResult___sfd__h7553)
begin
case (guard__h7136)
2'b0:
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q16 =
sfd___3__h7126[31:9];
2'b01, 2'b10, 2'b11:
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q16 =
_theResult___sfd__h7553;
endcase
end
always@(requestR or
sfd___3__h7126 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d398 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d396 or
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q16)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d402 =
sfd___3__h7126[31:9];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d402 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d398;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d402 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d396;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d402 =
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q16;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d402 =
23'd0;
endcase
end
always@(guard__h7136 or
sfd___3__h7126 or out_sfd__h7556 or _theResult___sfd__h7553)
begin
case (guard__h7136)
2'b0, 2'b01:
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q17 =
sfd___3__h7126[31:9];
2'b10:
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q17 =
out_sfd__h7556;
2'b11:
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q17 =
_theResult___sfd__h7553;
endcase
end
always@(guard__h7666 or sfd___3__h7126 or _theResult___sfd__h8106)
begin
case (guard__h7666)
2'b0:
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q18 =
sfd___3__h7126[30:8];
2'b01, 2'b10, 2'b11:
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q18 =
_theResult___sfd__h8106;
endcase
end
always@(requestR or
sfd___3__h7126 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d416 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d414 or
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q18)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d420 =
sfd___3__h7126[30:8];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d420 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d416;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d420 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d414;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d420 =
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q18;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d420 =
23'd0;
endcase
end
always@(guard__h7666 or
sfd___3__h7126 or out_sfd__h8109 or _theResult___sfd__h8106)
begin
case (guard__h7666)
2'b0, 2'b01:
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q19 =
sfd___3__h7126[30:8];
2'b10:
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q19 =
out_sfd__h8109;
2'b11:
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q19 =
_theResult___sfd__h8106;
endcase
end
always@(guard__h13313 or out_exp__h13729 or _theResult___exp__h13726)
begin
case (guard__h13313)
2'b0, 2'b01:
CASE_guard3313_0b0_0_0b1_0_0b10_out_exp3729_0b_ETC__q22 = 8'd0;
2'b10:
CASE_guard3313_0b0_0_0b1_0_0b10_out_exp3729_0b_ETC__q22 =
out_exp__h13729;
2'b11:
CASE_guard3313_0b0_0_0b1_0_0b10_out_exp3729_0b_ETC__q22 =
_theResult___exp__h13726;
endcase
end
always@(guard__h13313 or _theResult___exp__h13726)
begin
case (guard__h13313)
2'b0: CASE_guard3313_0b0_0_0b1_theResult___exp3726_0_ETC__q23 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard3313_0b0_0_0b1_theResult___exp3726_0_ETC__q23 =
_theResult___exp__h13726;
endcase
end
always@(requestR or
guard__h13313 or
_theResult___exp__h13726 or
CASE_guard3313_0b0_0_0b1_theResult___exp3726_0_ETC__q23)
begin
case (requestR[194:192])
3'h3:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard3313_ETC__q24 =
(guard__h13313 == 2'b0) ? 8'd0 : _theResult___exp__h13726;
3'h4:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard3313_ETC__q24 =
CASE_guard3313_0b0_0_0b1_theResult___exp3726_0_ETC__q23;
default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard3313_ETC__q24 = 8'd0;
endcase
end
always@(guard__h13839 or x__h13854 or _theResult___exp__h14278)
begin
case (guard__h13839)
2'b0:
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_theRe_ETC__q25 =
x__h13854[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_theRe_ETC__q25 =
_theResult___exp__h14278;
endcase
end
always@(requestR or
x__h13854 or
guard__h13839 or
_theResult___exp__h14278 or
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_theRe_ETC__q25)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d697 =
x__h13854[7:0];
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d697 =
(guard__h13839 == 2'b0) ?
x__h13854[7:0] :
_theResult___exp__h14278;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d697 =
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_theRe_ETC__q25;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d697 =
8'd0;
endcase
end
always@(guard__h13839 or
x__h13854 or out_exp__h14281 or _theResult___exp__h14278)
begin
case (guard__h13839)
2'b0, 2'b01:
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_x3854_ETC__q26 =
x__h13854[7:0];
2'b10:
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_x3854_ETC__q26 =
out_exp__h14281;
2'b11:
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_x3854_ETC__q26 =
_theResult___exp__h14278;
endcase
end
always@(guard__h13839 or sfd___3__h13303 or _theResult___sfd__h14279)
begin
case (guard__h13839)
2'b0:
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q27 =
sfd___3__h13303[30:8];
2'b01, 2'b10, 2'b11:
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q27 =
_theResult___sfd__h14279;
endcase
end
always@(requestR or
sfd___3__h13303 or
guard__h13839 or
_theResult___sfd__h14279 or
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q27)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d735 =
sfd___3__h13303[30:8];
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d735 =
(guard__h13839 == 2'b0) ?
sfd___3__h13303[30:8] :
_theResult___sfd__h14279;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d735 =
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q27;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d735 =
23'd0;
endcase
end
always@(guard__h13839 or
sfd___3__h13303 or out_sfd__h14282 or _theResult___sfd__h14279)
begin
case (guard__h13839)
2'b0, 2'b01:
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q28 =
sfd___3__h13303[30:8];
2'b10:
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q28 =
out_sfd__h14282;
2'b11:
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q28 =
_theResult___sfd__h14279;
endcase
end
always@(guard__h13313 or sfd___3__h13303 or _theResult___sfd__h13727)
begin
case (guard__h13313)
2'b0:
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q29 =
sfd___3__h13303[31:9];
2'b01, 2'b10, 2'b11:
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q29 =
_theResult___sfd__h13727;
endcase
end
always@(requestR or
sfd___3__h13303 or
guard__h13313 or
_theResult___sfd__h13727 or
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q29)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d720 =
sfd___3__h13303[31:9];
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d720 =
(guard__h13313 == 2'b0) ?
sfd___3__h13303[31:9] :
_theResult___sfd__h13727;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d720 =
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q29;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d720 =
23'd0;
endcase
end
always@(guard__h13313 or
sfd___3__h13303 or out_sfd__h13730 or _theResult___sfd__h13727)
begin
case (guard__h13313)
2'b0, 2'b01:
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q30 =
sfd___3__h13303[31:9];
2'b10:
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q30 =
out_sfd__h13730;
2'b11:
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q30 =
_theResult___sfd__h13727;
endcase
end
always@(guard__h35772 or requestR)
begin
case (guard__h35772)
2'b0, 2'b01, 2'b10:
CASE_guard5772_0b0_requestR_BIT_159_0b1_reques_ETC__q35 =
requestR[159];
2'd3:
CASE_guard5772_0b0_requestR_BIT_159_0b1_reques_ETC__q35 =
guard__h35772 == 2'b11 && requestR[159];
endcase
end
always@(requestR or guard__h35772)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36 =
requestR[159];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36 =
(guard__h35772 == 2'b0) ?
requestR[159] :
(guard__h35772 == 2'b01 || guard__h35772 == 2'b10 ||
guard__h35772 == 2'b11) &&
requestR[159];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36 =
requestR[194:192] == 3'h1 && requestR[159];
endcase
end
always@(guard__h36502 or requestR)
begin
case (guard__h36502)
2'b0, 2'b01, 2'b10:
CASE_guard6502_0b0_requestR_BIT_159_0b1_reques_ETC__q37 =
requestR[159];
2'd3:
CASE_guard6502_0b0_requestR_BIT_159_0b1_reques_ETC__q37 =
guard__h36502 == 2'b11 && requestR[159];
endcase
end
always@(requestR or guard__h36502)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38 =
requestR[159];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38 =
(guard__h36502 == 2'b0) ?
requestR[159] :
(guard__h36502 == 2'b01 || guard__h36502 == 2'b10 ||
guard__h36502 == 2'b11) &&
requestR[159];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38 =
requestR[194:192] == 3'h1 && requestR[159];
endcase
end
always@(guard__h36502 or x__h36517 or _theResult___exp__h37144)
begin
case (guard__h36502)
2'b0:
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_theR_ETC__q39 =
x__h36517[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_theR_ETC__q39 =
_theResult___exp__h37144;
endcase
end
always@(requestR or
x__h36517 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1335 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1333 or
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_theR_ETC__q39)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1339 =
x__h36517[10:0];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1339 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1335;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1339 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1333;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1339 =
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_theR_ETC__q39;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1339 =
11'd0;
endcase
end
always@(guard__h36502 or
x__h36517 or out_exp__h37147 or _theResult___exp__h37144)
begin
case (guard__h36502)
2'b0, 2'b01:
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_x651_ETC__q40 =
x__h36517[10:0];
2'b10:
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_x651_ETC__q40 =
out_exp__h37147;
2'b11:
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_x651_ETC__q40 =
_theResult___exp__h37144;
endcase
end
always@(guard__h36502 or sfd___3__h35762 or _theResult___sfd__h37145)
begin
case (guard__h36502)
2'b0:
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q41 =
sfd___3__h35762[53:2];
2'b01, 2'b10, 2'b11:
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q41 =
_theResult___sfd__h37145;
endcase
end
always@(requestR or
sfd___3__h35762 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1376 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1374 or
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q41)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1380 =
sfd___3__h35762[53:2];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1380 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1376;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1380 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1374;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1380 =
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q41;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1380 =
52'd0;
endcase
end
always@(guard__h36502 or
sfd___3__h35762 or out_sfd__h37148 or _theResult___sfd__h37145)
begin
case (guard__h36502)
2'b0, 2'b01:
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q42 =
sfd___3__h35762[53:2];
2'b10:
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q42 =
out_sfd__h37148;
2'b11:
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q42 =
_theResult___sfd__h37145;
endcase
end
always@(guard__h35772 or _theResult___exp__h36388)
begin
case (guard__h35772)
2'b0: CASE_guard5772_0b0_0_0b1_theResult___exp6388_0_ETC__q43 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard5772_0b0_0_0b1_theResult___exp6388_0_ETC__q43 =
_theResult___exp__h36388;
endcase
end
always@(requestR or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1307 or
guard__h35772 or
_theResult___exp__h36388 or
CASE_guard5772_0b0_0_0b1_theResult___exp6388_0_ETC__q43)
begin
case (requestR[194:192])
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1310 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1307;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1310 =
(guard__h35772 == 2'b0 || requestR[159]) ?
11'd0 :
_theResult___exp__h36388;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1310 =
CASE_guard5772_0b0_0_0b1_theResult___exp6388_0_ETC__q43;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1310 =
11'd0;
endcase
end
always@(guard__h35772 or out_exp__h36391 or _theResult___exp__h36388)
begin
case (guard__h35772)
2'b0, 2'b01:
CASE_guard5772_0b0_0_0b1_0_0b10_out_exp6391_0b_ETC__q44 = 11'd0;
2'b10:
CASE_guard5772_0b0_0_0b1_0_0b10_out_exp6391_0b_ETC__q44 =
out_exp__h36391;
2'b11:
CASE_guard5772_0b0_0_0b1_0_0b10_out_exp6391_0b_ETC__q44 =
_theResult___exp__h36388;
endcase
end
always@(guard__h35772 or sfd___3__h35762 or _theResult___sfd__h36389)
begin
case (guard__h35772)
2'b0:
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q45 =
sfd___3__h35762[54:3];
2'b01, 2'b10, 2'b11:
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q45 =
_theResult___sfd__h36389;
endcase
end
always@(requestR or
sfd___3__h35762 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1358 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1356 or
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q45)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1362 =
sfd___3__h35762[54:3];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1362 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1358;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1362 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1356;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1362 =
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q45;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1362 =
52'd0;
endcase
end
always@(guard__h35772 or
sfd___3__h35762 or out_sfd__h36392 or _theResult___sfd__h36389)
begin
case (guard__h35772)
2'b0, 2'b01:
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q46 =
sfd___3__h35762[54:3];
2'b10:
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q46 =
out_sfd__h36392;
2'b11:
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q46 =
_theResult___sfd__h36389;
endcase
end
always@(guard__h45468 or out_exp__h46087 or _theResult___exp__h46084)
begin
case (guard__h45468)
2'b0, 2'b01:
CASE_guard5468_0b0_0_0b1_0_0b10_out_exp6087_0b_ETC__q49 = 11'd0;
2'b10:
CASE_guard5468_0b0_0_0b1_0_0b10_out_exp6087_0b_ETC__q49 =
out_exp__h46087;
2'b11:
CASE_guard5468_0b0_0_0b1_0_0b10_out_exp6087_0b_ETC__q49 =
_theResult___exp__h46084;
endcase
end
always@(guard__h45468 or _theResult___exp__h46084)
begin
case (guard__h45468)
2'b0: CASE_guard5468_0b0_0_0b1_theResult___exp6084_0_ETC__q50 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard5468_0b0_0_0b1_theResult___exp6084_0_ETC__q50 =
_theResult___exp__h46084;
endcase
end
always@(requestR or
guard__h45468 or
_theResult___exp__h46084 or
CASE_guard5468_0b0_0_0b1_theResult___exp6084_0_ETC__q50)
begin
case (requestR[194:192])
3'h3:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard5468_ETC__q51 =
(guard__h45468 == 2'b0) ? 11'd0 : _theResult___exp__h46084;
3'h4:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard5468_ETC__q51 =
CASE_guard5468_0b0_0_0b1_theResult___exp6084_0_ETC__q50;
default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard5468_ETC__q51 =
11'd0;
endcase
end
always@(guard__h46197 or x__h46212 or _theResult___exp__h46839)
begin
case (guard__h46197)
2'b0:
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_theR_ETC__q52 =
x__h46212[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_theR_ETC__q52 =
_theResult___exp__h46839;
endcase
end
always@(requestR or
x__h46212 or
guard__h46197 or
_theResult___exp__h46839 or
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_theR_ETC__q52)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1526 =
x__h46212[10:0];
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1526 =
(guard__h46197 == 2'b0) ?
x__h46212[10:0] :
_theResult___exp__h46839;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1526 =
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_theR_ETC__q52;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1526 =
11'd0;
endcase
end
always@(guard__h46197 or
x__h46212 or out_exp__h46842 or _theResult___exp__h46839)
begin
case (guard__h46197)
2'b0, 2'b01:
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_x621_ETC__q53 =
x__h46212[10:0];
2'b10:
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_x621_ETC__q53 =
out_exp__h46842;
2'b11:
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_x621_ETC__q53 =
_theResult___exp__h46839;
endcase
end
always@(guard__h46197 or sfd___3__h45458 or _theResult___sfd__h46840)
begin
case (guard__h46197)
2'b0:
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q54 =
sfd___3__h45458[53:2];
2'b01, 2'b10, 2'b11:
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q54 =
_theResult___sfd__h46840;
endcase
end
always@(requestR or
sfd___3__h45458 or
guard__h46197 or
_theResult___sfd__h46840 or
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q54)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1563 =
sfd___3__h45458[53:2];
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1563 =
(guard__h46197 == 2'b0) ?
sfd___3__h45458[53:2] :
_theResult___sfd__h46840;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1563 =
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q54;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1563 =
52'd0;
endcase
end
always@(guard__h46197 or
sfd___3__h45458 or out_sfd__h46843 or _theResult___sfd__h46840)
begin
case (guard__h46197)
2'b0, 2'b01:
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q55 =
sfd___3__h45458[53:2];
2'b10:
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q55 =
out_sfd__h46843;
2'b11:
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q55 =
_theResult___sfd__h46840;
endcase
end
always@(guard__h45468 or sfd___3__h45458 or _theResult___sfd__h46085)
begin
case (guard__h45468)
2'b0:
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q56 =
sfd___3__h45458[54:3];
2'b01, 2'b10, 2'b11:
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q56 =
_theResult___sfd__h46085;
endcase
end
always@(requestR or
sfd___3__h45458 or
guard__h45468 or
_theResult___sfd__h46085 or
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q56)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1548 =
sfd___3__h45458[54:3];
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1548 =
(guard__h45468 == 2'b0) ?
sfd___3__h45458[54:3] :
_theResult___sfd__h46085;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1548 =
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q56;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1548 =
52'd0;
endcase
end
always@(guard__h45468 or
sfd___3__h45458 or out_sfd__h46088 or _theResult___sfd__h46085)
begin
case (guard__h45468)
2'b0, 2'b01:
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q57 =
sfd___3__h45458[54:3];
2'b10:
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q57 =
out_sfd__h46088;
2'b11:
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q57 =
_theResult___sfd__h46085;
endcase
end
always@(guard__h61553 or
_theResult___fst_exp__h69650 or _theResult___exp__h70176)
begin
case (guard__h61553)
2'b0:
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q70 =
_theResult___fst_exp__h69650;
2'b01, 2'b10, 2'b11:
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q70 =
_theResult___exp__h70176;
endcase
end
always@(requestR or
_theResult___fst_exp__h69650 or
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2135 or
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2133 or
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q70)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2139 =
_theResult___fst_exp__h69650;
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2139 =
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2135;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2139 =
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2133;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2139 =
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q70;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2139 =
8'd0;
endcase
end
always@(guard__h61553 or
_theResult___fst_exp__h69650 or
out_exp__h70179 or _theResult___exp__h70176)
begin
case (guard__h61553)
2'b0, 2'b01:
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q71 =
_theResult___fst_exp__h69650;
2'b10:
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q71 =
out_exp__h70179;
2'b11:
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q71 =
_theResult___exp__h70176;
endcase
end
always@(guard__h70288 or
_theResult___fst_exp__h78336 or _theResult___exp__h78788)
begin
case (guard__h70288)
2'b0:
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q72 =
_theResult___fst_exp__h78336;
2'b01, 2'b10, 2'b11:
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q72 =
_theResult___exp__h78788;
endcase
end
always@(requestR or
_theResult___fst_exp__h78336 or
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2292 or
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2290 or
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q72)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2296 =
_theResult___fst_exp__h78336;
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2296 =
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2292;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2296 =
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2290;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2296 =
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q72;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2296 =
8'd0;
endcase
end
always@(guard__h70288 or
_theResult___fst_exp__h78336 or
out_exp__h78791 or _theResult___exp__h78788)
begin
case (guard__h70288)
2'b0, 2'b01:
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q73 =
_theResult___fst_exp__h78336;
2'b10:
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q73 =
out_exp__h78791;
2'b11:
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q73 =
_theResult___exp__h78788;
endcase
end
always@(guard__h79277 or
_theResult___fst_exp__h87503 or _theResult___exp__h88029)
begin
case (guard__h79277)
2'b0:
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q74 =
_theResult___fst_exp__h87503;
2'b01, 2'b10, 2'b11:
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q74 =
_theResult___exp__h88029;
endcase
end
always@(requestR or
_theResult___fst_exp__h87503 or
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2619 or
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2617 or
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q74)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2623 =
_theResult___fst_exp__h87503;
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2623 =
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2619;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2623 =
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2617;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2623 =
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q74;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2623 =
8'd0;
endcase
end
always@(guard__h79277 or
_theResult___fst_exp__h87503 or
out_exp__h88032 or _theResult___exp__h88029)
begin
case (guard__h79277)
2'b0, 2'b01:
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q75 =
_theResult___fst_exp__h87503;
2'b10:
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q75 =
out_exp__h88032;
2'b11:
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q75 =
_theResult___exp__h88029;
endcase
end
always@(guard__h88141 or
_theResult___fst_exp__h96218 or _theResult___exp__h96695)
begin
case (guard__h88141)
2'b0:
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q76 =
_theResult___fst_exp__h96218;
2'b01, 2'b10, 2'b11:
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q76 =
_theResult___exp__h96695;
endcase
end
always@(requestR or
_theResult___fst_exp__h96218 or
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2688 or
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2686 or
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q76)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2692 =
_theResult___fst_exp__h96218;
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2692 =
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2688;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2692 =
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2686;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2692 =
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q76;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2692 =
8'd0;
endcase
end
always@(guard__h88141 or
_theResult___fst_exp__h96218 or
out_exp__h96698 or _theResult___exp__h96695)
begin
case (guard__h88141)
2'b0, 2'b01:
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q77 =
_theResult___fst_exp__h96218;
2'b10:
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q77 =
out_exp__h96698;
2'b11:
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q77 =
_theResult___exp__h96695;
endcase
end
always@(guard__h61553 or sfdin__h69644 or _theResult___sfd__h70177)
begin
case (guard__h61553)
2'b0:
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q78 =
sfdin__h69644[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q78 =
_theResult___sfd__h70177;
endcase
end
always@(requestR or
sfdin__h69644 or
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2722 or
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2720 or
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q78)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2726 =
sfdin__h69644[56:34];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2726 =
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2722;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2726 =
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2720;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2726 =
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q78;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2726 =
23'd0;
endcase
end
always@(guard__h61553 or
sfdin__h69644 or out_sfd__h70180 or _theResult___sfd__h70177)
begin
case (guard__h61553)
2'b0, 2'b01:
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q79 =
sfdin__h69644[56:34];
2'b10:
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q79 =
out_sfd__h70180;
2'b11:
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q79 =
_theResult___sfd__h70177;
endcase
end
always@(guard__h70288 or
_theResult___snd__h78287 or _theResult___sfd__h78789)
begin
case (guard__h70288)
2'b0:
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q80 =
_theResult___snd__h78287[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q80 =
_theResult___sfd__h78789;
endcase
end
always@(requestR or
_theResult___snd__h78287 or
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2741 or
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2739 or
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q80)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2745 =
_theResult___snd__h78287[56:34];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2745 =
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2741;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2745 =
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2739;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2745 =
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q80;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2745 =
23'd0;
endcase
end
always@(guard__h70288 or
_theResult___snd__h78287 or
out_sfd__h78792 or _theResult___sfd__h78789)
begin
case (guard__h70288)
2'b0, 2'b01:
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q81 =
_theResult___snd__h78287[56:34];
2'b10:
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q81 =
out_sfd__h78792;
2'b11:
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q81 =
_theResult___sfd__h78789;
endcase
end
always@(guard__h79277 or sfdin__h87497 or _theResult___sfd__h88030)
begin
case (guard__h79277)
2'b0:
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q82 =
sfdin__h87497[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q82 =
_theResult___sfd__h88030;
endcase
end
always@(requestR or
sfdin__h87497 or
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2768 or
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2766 or
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q82)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2772 =
sfdin__h87497[56:34];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2772 =
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2768;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2772 =
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2766;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2772 =
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q82;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2772 =
23'd0;
endcase
end
always@(guard__h79277 or
sfdin__h87497 or out_sfd__h88033 or _theResult___sfd__h88030)
begin
case (guard__h79277)
2'b0, 2'b01:
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q83 =
sfdin__h87497[56:34];
2'b10:
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q83 =
out_sfd__h88033;
2'b11:
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q83 =
_theResult___sfd__h88030;
endcase
end
always@(guard__h88141 or
_theResult___snd__h96164 or _theResult___sfd__h96696)
begin
case (guard__h88141)
2'b0:
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q84 =
_theResult___snd__h96164[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q84 =
_theResult___sfd__h96696;
endcase
end
always@(requestR or
_theResult___snd__h96164 or
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2787 or
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2785 or
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q84)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2791 =
_theResult___snd__h96164[56:34];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2791 =
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2787;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2791 =
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2785;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2791 =
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q84;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2791 =
23'd0;
endcase
end
always@(guard__h88141 or
_theResult___snd__h96164 or
out_sfd__h96699 or _theResult___sfd__h96696)
begin
case (guard__h88141)
2'b0, 2'b01:
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q85 =
_theResult___snd__h96164[56:34];
2'b10:
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q85 =
out_sfd__h96699;
2'b11:
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q85 =
_theResult___sfd__h96696;
endcase
end
always@(guard__h61553 or requestR)
begin
case (guard__h61553)
2'b0, 2'b01, 2'b10:
CASE_guard1553_0b0_requestR_BIT_191_0b1_reques_ETC__q86 =
requestR[191];
2'd3:
CASE_guard1553_0b0_requestR_BIT_191_0b1_reques_ETC__q86 =
guard__h61553 == 2'b11 && requestR[191];
endcase
end
always@(requestR or guard__h61553)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87 =
requestR[191];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87 =
(guard__h61553 == 2'b0) ?
requestR[191] :
(guard__h61553 == 2'b01 || guard__h61553 == 2'b10 ||
guard__h61553 == 2'b11) &&
requestR[191];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87 =
requestR[194:192] == 3'h1 && requestR[191];
endcase
end
always@(guard__h70288 or requestR)
begin
case (guard__h70288)
2'b0, 2'b01, 2'b10:
CASE_guard0288_0b0_requestR_BIT_191_0b1_reques_ETC__q88 =
requestR[191];
2'd3:
CASE_guard0288_0b0_requestR_BIT_191_0b1_reques_ETC__q88 =
guard__h70288 == 2'b11 && requestR[191];
endcase
end
always@(requestR or guard__h70288)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89 =
requestR[191];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89 =
(guard__h70288 == 2'b0) ?
requestR[191] :
(guard__h70288 == 2'b01 || guard__h70288 == 2'b10 ||
guard__h70288 == 2'b11) &&
requestR[191];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89 =
requestR[194:192] == 3'h1 && requestR[191];
endcase
end
always@(guard__h79277 or requestR)
begin
case (guard__h79277)
2'b0, 2'b01, 2'b10:
CASE_guard9277_0b0_requestR_BIT_191_0b1_reques_ETC__q90 =
requestR[191];
2'd3:
CASE_guard9277_0b0_requestR_BIT_191_0b1_reques_ETC__q90 =
guard__h79277 == 2'b11 && requestR[191];
endcase
end
always@(requestR or guard__h79277)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91 =
requestR[191];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91 =
(guard__h79277 == 2'b0) ?
requestR[191] :
(guard__h79277 == 2'b01 || guard__h79277 == 2'b10 ||
guard__h79277 == 2'b11) &&
requestR[191];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91 =
requestR[194:192] == 3'h1 && requestR[191];
endcase
end
always@(guard__h88141 or requestR)
begin
case (guard__h88141)
2'b0, 2'b01, 2'b10:
CASE_guard8141_0b0_requestR_BIT_191_0b1_reques_ETC__q92 =
requestR[191];
2'd3:
CASE_guard8141_0b0_requestR_BIT_191_0b1_reques_ETC__q92 =
guard__h88141 == 2'b11 && requestR[191];
endcase
end
always@(requestR or guard__h88141)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93 =
requestR[191];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93 =
(guard__h88141 == 2'b0) ?
requestR[191] :
(guard__h88141 == 2'b01 || guard__h88141 == 2'b10 ||
guard__h88141 == 2'b11) &&
requestR[191];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93 =
requestR[194:192] == 3'h1 && requestR[191];
endcase
end
always@(guard__h111304 or
_theResult___fst_exp__h119265 or _theResult___exp__h119920)
begin
case (guard__h111304)
2'b0:
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q102 =
_theResult___fst_exp__h119265;
2'b01, 2'b10, 2'b11:
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q102 =
_theResult___exp__h119920;
endcase
end
always@(requestR or
_theResult___fst_exp__h119265 or
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3130 or
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3128 or
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q102)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3134 =
_theResult___fst_exp__h119265;
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3134 =
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3130;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3134 =
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3128;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3134 =
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q102;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3134 =
11'd0;
endcase
end
always@(guard__h111304 or
_theResult___fst_exp__h119265 or
out_exp__h119923 or _theResult___exp__h119920)
begin
case (guard__h111304)
2'b0, 2'b01:
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q103 =
_theResult___fst_exp__h119265;
2'b10:
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q103 =
out_exp__h119923;
2'b11:
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q103 =
_theResult___exp__h119920;
endcase
end
always@(guard__h120612 or
_theResult___fst_exp__h128838 or _theResult___exp__h129567)
begin
case (guard__h120612)
2'b0:
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q104 =
_theResult___fst_exp__h128838;
2'b01, 2'b10, 2'b11:
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q104 =
_theResult___exp__h129567;
endcase
end
always@(requestR or
_theResult___fst_exp__h128838 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3455 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3453 or
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q104)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3459 =
_theResult___fst_exp__h128838;
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3459 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3455;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3459 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3453;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3459 =
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q104;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3459 =
11'd0;
endcase
end
always@(guard__h120612 or
_theResult___fst_exp__h128838 or
out_exp__h129570 or _theResult___exp__h129567)
begin
case (guard__h120612)
2'b0, 2'b01:
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q105 =
_theResult___fst_exp__h128838;
2'b10:
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q105 =
out_exp__h129570;
2'b11:
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q105 =
_theResult___exp__h129567;
endcase
end
always@(guard__h129679 or
_theResult___fst_exp__h137669 or _theResult___exp__h138349)
begin
case (guard__h129679)
2'b0:
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q106 =
_theResult___fst_exp__h137669;
2'b01, 2'b10, 2'b11:
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q106 =
_theResult___exp__h138349;
endcase
end
always@(requestR or
_theResult___fst_exp__h137669 or
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3524 or
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3522 or
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q106)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3528 =
_theResult___fst_exp__h137669;
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3528 =
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3524;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3528 =
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3522;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3528 =
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q106;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3528 =
11'd0;
endcase
end
always@(guard__h129679 or
_theResult___fst_exp__h137669 or
out_exp__h138352 or _theResult___exp__h138349)
begin
case (guard__h129679)
2'b0, 2'b01:
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q107 =
_theResult___fst_exp__h137669;
2'b10:
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q107 =
out_exp__h138352;
2'b11:
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q107 =
_theResult___exp__h138349;
endcase
end
always@(guard__h111304 or requestR)
begin
case (guard__h111304)
2'b0, 2'b01, 2'b10:
CASE_guard11304_0b0_requestR_BITS_191_TO_160_E_ETC__q108 =
requestR[191:160] == 32'hFFFFFFFF && requestR[159];
2'd3:
CASE_guard11304_0b0_requestR_BITS_191_TO_160_E_ETC__q108 =
guard__h111304 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
endcase
end
always@(requestR or guard__h111304)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109 =
requestR[191:160] == 32'hFFFFFFFF && requestR[159];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109 =
(guard__h111304 == 2'b0) ?
requestR[191:160] == 32'hFFFFFFFF && requestR[159] :
(guard__h111304 == 2'b01 || guard__h111304 == 2'b10 ||
guard__h111304 == 2'b11) &&
requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109 =
requestR[194:192] == 3'h1 &&
requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
endcase
end
always@(guard__h120612 or requestR)
begin
case (guard__h120612)
2'b0, 2'b01, 2'b10:
CASE_guard20612_0b0_requestR_BITS_191_TO_160_E_ETC__q110 =
requestR[191:160] == 32'hFFFFFFFF && requestR[159];
2'd3:
CASE_guard20612_0b0_requestR_BITS_191_TO_160_E_ETC__q110 =
guard__h120612 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
endcase
end
always@(requestR or guard__h120612)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111 =
requestR[191:160] == 32'hFFFFFFFF && requestR[159];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111 =
(guard__h120612 == 2'b0) ?
requestR[191:160] == 32'hFFFFFFFF && requestR[159] :
(guard__h120612 == 2'b01 || guard__h120612 == 2'b10 ||
guard__h120612 == 2'b11) &&
requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111 =
requestR[194:192] == 3'h1 &&
requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
endcase
end
always@(guard__h129679 or requestR)
begin
case (guard__h129679)
2'b0, 2'b01, 2'b10:
CASE_guard29679_0b0_requestR_BITS_191_TO_160_E_ETC__q112 =
requestR[191:160] == 32'hFFFFFFFF && requestR[159];
2'd3:
CASE_guard29679_0b0_requestR_BITS_191_TO_160_E_ETC__q112 =
guard__h129679 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
endcase
end
always@(requestR or guard__h129679)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113 =
requestR[191:160] == 32'hFFFFFFFF && requestR[159];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113 =
(guard__h129679 == 2'b0) ?
requestR[191:160] == 32'hFFFFFFFF && requestR[159] :
(guard__h129679 == 2'b01 || guard__h129679 == 2'b10 ||
guard__h129679 == 2'b11) &&
requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113 =
requestR[194:192] == 3'h1 &&
requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
endcase
end
always@(guard__h111304 or
_theResult___snd__h119216 or _theResult___sfd__h119921)
begin
case (guard__h111304)
2'b0:
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q114 =
_theResult___snd__h119216[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q114 =
_theResult___sfd__h119921;
endcase
end
always@(requestR or
_theResult___snd__h119216 or
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3557 or
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3555 or
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q114)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3561 =
_theResult___snd__h119216[56:5];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3561 =
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3557;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3561 =
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3555;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3561 =
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q114;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3561 =
52'd0;
endcase
end
always@(guard__h111304 or
_theResult___snd__h119216 or
out_sfd__h119924 or _theResult___sfd__h119921)
begin
case (guard__h111304)
2'b0, 2'b01:
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q115 =
_theResult___snd__h119216[56:5];
2'b10:
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q115 =
out_sfd__h119924;
2'b11:
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q115 =
_theResult___sfd__h119921;
endcase
end
always@(guard__h120612 or sfdin__h128832 or _theResult___sfd__h129568)
begin
case (guard__h120612)
2'b0:
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q116 =
sfdin__h128832[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q116 =
_theResult___sfd__h129568;
endcase
end
always@(requestR or
sfdin__h128832 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3584 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3582 or
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q116)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3588 =
sfdin__h128832[56:5];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3588 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3584;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3588 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3582;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3588 =
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q116;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3588 =
52'd0;
endcase
end
always@(guard__h120612 or
sfdin__h128832 or out_sfd__h129571 or _theResult___sfd__h129568)
begin
case (guard__h120612)
2'b0, 2'b01:
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q117 =
sfdin__h128832[56:5];
2'b10:
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q117 =
out_sfd__h129571;
2'b11:
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q117 =
_theResult___sfd__h129568;
endcase
end
always@(guard__h129679 or
_theResult___snd__h137615 or _theResult___sfd__h138350)
begin
case (guard__h129679)
2'b0:
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q118 =
_theResult___snd__h137615[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q118 =
_theResult___sfd__h138350;
endcase
end
always@(requestR or
_theResult___snd__h137615 or
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3603 or
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3601 or
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q118)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3607 =
_theResult___snd__h137615[56:5];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3607 =
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3603;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3607 =
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3601;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3607 =
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q118;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3607 =
52'd0;
endcase
end
always@(guard__h129679 or
_theResult___snd__h137615 or
out_sfd__h138353 or _theResult___sfd__h138350)
begin
case (guard__h129679)
2'b0, 2'b01:
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q119 =
_theResult___snd__h137615[56:5];
2'b10:
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q119 =
out_sfd__h138353;
2'b11:
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q119 =
_theResult___sfd__h138350;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
requestR <= `BSV_ASSIGNMENT_DELAY
215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
resultR <= `BSV_ASSIGNMENT_DELAY 70'h0AAAAAAAAAAAAAAAAA;
stateR <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (requestR$EN) requestR <= `BSV_ASSIGNMENT_DELAY requestR$D_IN;
if (resultR$EN) resultR <= `BSV_ASSIGNMENT_DELAY resultR$D_IN;
if (stateR$EN) stateR <= `BSV_ASSIGNMENT_DELAY stateR$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
requestR = 215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
resultR = 70'h2AAAAAAAAAAAAAAAAA;
stateR = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkRISCV_FBox
|
module VGAController(
input iClk,
input inRst,
input [7:0] iR,
input [7:0] iG,
input [7:0] iB,
output [7:0] oR,
output [7:0] oG,
output [7:0] oB,
output oHSync,
output oVSync,
output oLineValid,
output oFrameValid
);
/*****************************************************************
* H timings
****************************************************************/
parameter H_SYNC_PULSE = 96;
parameter H_SYNC_BACK = 48;
parameter H_SYNC_DATA = 640;
parameter H_SYNC_FRONT = 16;
parameter H_SYNC_TOTAL = H_SYNC_FRONT + H_SYNC_PULSE + H_SYNC_BACK + H_SYNC_DATA;
/*****************************************************************
* V timings
****************************************************************/
parameter V_SYNC_PULSE = 2;
parameter V_SYNC_BACK = 36;
parameter V_SYNC_DATA = 480;
parameter V_SYNC_FRONT = 7;
parameter V_SYNC_TOTAL = V_SYNC_FRONT + V_SYNC_PULSE + V_SYNC_BACK + V_SYNC_DATA;
/*****************************************************************
* Data offsets
****************************************************************/
parameter H_START_DATA = H_SYNC_BACK + H_SYNC_PULSE + H_SYNC_FRONT;
parameter V_START_DATA = V_SYNC_BACK + V_SYNC_PULSE + V_SYNC_FRONT;
parameter H_STOP_DATA = H_START_DATA + H_SYNC_DATA;
parameter V_STOP_DATA = V_START_DATA + V_SYNC_DATA;
/*****************************************************************
* Sync pulses offsets
****************************************************************/
parameter H_START_PULSE = H_SYNC_FRONT;
parameter V_START_PULSE = V_SYNC_FRONT;
parameter H_STOP_PULSE = H_SYNC_FRONT + H_SYNC_PULSE;
parameter V_STOP_PULSE = V_SYNC_FRONT + V_SYNC_PULSE;
/*****************************************************************
* Internal schedule counters
****************************************************************/
reg [12:0] mHCounter = 0;
reg [12:0] mVCounter = 0;
/*****************************************************************
* Async assignments
****************************************************************/
assign oVSync = (mVCounter >= V_START_PULSE && mVCounter < V_STOP_PULSE && inRst ) ? 0 : 1;
assign oHSync = (mHCounter >= H_START_PULSE && mHCounter < H_STOP_PULSE && inRst ) ? 0 : 1;
assign oFrameValid = (mVCounter >= V_START_DATA && mVCounter < V_STOP_DATA && inRst ) ? 1 : 0;
assign oLineValid = (mHCounter >= H_START_DATA && mHCounter < H_STOP_DATA && oFrameValid) ? 1 : 0;
assign oR = (oLineValid && oFrameValid && inRst) ? iR : 0;
assign oG = (oLineValid && oFrameValid && inRst) ? iG : 0;
assign oB = (oLineValid && oFrameValid && inRst) ? iB : 0;
/*****************************************************************
* Pixel counter generator
****************************************************************/
always@(posedge iClk or negedge inRst)
begin
if(~inRst) mHCounter <= 0;
else
begin
if(mHCounter == (H_SYNC_TOTAL - 1)) mHCounter <= 0;
else mHCounter <= mHCounter + 1;
end
end
/*****************************************************************
* Line counter generator
****************************************************************/
always@(posedge iClk or negedge inRst)
begin
if(~inRst) mVCounter <= 0;
else
begin
if(mHCounter == (H_SYNC_TOTAL - 1))
begin
if(mVCounter == (V_SYNC_TOTAL - 1)) mVCounter <= 0;
else mVCounter <= mVCounter + 1;
end
else mVCounter <= mVCounter;
end
end
endmodule |
/* ****************************************************************************
-- (C) Copyright 2018 Kevin M. Hubbard - All rights reserved.
-- Source file: deep_sump_ram.v
-- Date: May 2018
-- Author: khubbard
-- Description: Deep Sump extension to sump2.v logic analyzer. This is a
-- simple inferrable Block RAM.
-- Language: Verilog-2001
-- Simulation: Mentor-Modelsim
-- Synthesis: Xilint-XST,Xilinx-Vivado,Lattice-Synplify
-- License: This project is licensed with the CERN Open Hardware Licence
-- v1.2. You may redistribute and modify this project under the
-- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).
-- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED
-- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL
-- v.1.2 for applicable Conditions.
--
-- a_clk _/ \_/ \_/ \_/ \_/ \_/ \_/ \_
-- a_we _____/ \____/ \_______
-- a_addr -----< >----< >< >-------
-- a_di -----< >----< >< >-------
--
-- b_clk _/ \_/ \_/ \_/ \_/ \_/ \_/ \_
-- b_rd_req _____/ \_______/ \_______
-- b_addr -----< >< >
-- b_do ----------< >--------< >
--
-- Revision History:
-- Ver# When Who What
-- ---- -------- -------- --------------------------------------------------
-- 0.1 05.01.18 khubbard Creation
-- ***************************************************************************/
`default_nettype none // Strictly enforce all nets to be declared
module deep_sump_ram #
(
parameter depth_len = 65536,
parameter depth_bits = 16
)
(
input wire a_clk,
input wire b_clk,
input wire a_we,
input wire [depth_bits-1:0] a_addr,
input wire [63:0] a_di,
output wire a_overrun,
input wire b_rd_req,
input wire [depth_bits-1:0] b_addr,
output wire [63:0] b_do
);
// Variable Size Capture BRAM
reg [63:0] rle_ram_array[depth_len-1:0];
reg [depth_bits-1:0] a_addr_p1;
reg [depth_bits-1:0] a_addr_p2;
reg a_we_p1;
reg a_we_p2;
reg [63:0] a_di_p1;
reg [63:0] a_di_p2;
reg [depth_bits-1:0] b_addr_p1;
reg [63:0] b_do_loc;
reg [63:0] b_do_p1;
assign a_overrun = 0;// This would assert if RAM wasn't available for write
//-----------------------------------------------------------------------------
// Data Dual Port RAM - Infer RAM here to make easy to change depth on the fly
//-----------------------------------------------------------------------------
always @( posedge a_clk )
begin
a_we_p1 <= a_we;
a_we_p2 <= a_we_p1;
a_addr_p1 <= a_addr;
a_addr_p2 <= a_addr_p1;
a_di_p1 <= a_di;
a_di_p2 <= a_di_p1;
if ( a_we_p2 ) begin
rle_ram_array[a_addr_p2] <= a_di_p2;
end // if ( a_we )
end // always
//-----------------------------------------------------------------------------
// 2nd Port of RAM is clocked from local bus
//-----------------------------------------------------------------------------
always @( posedge b_clk )
begin
b_addr_p1 <= b_addr;
b_do_loc <= rle_ram_array[b_addr_p1] ;
b_do_p1 <= b_do_loc;
end // always
assign b_do = b_do_p1[63:0];
endmodule // deep_sump_ram
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2016 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file DualPortRAM_Block.v when simulating
// the core, DualPortRAM_Block. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module DualPortRAM_Block(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [8 : 0] addra;
input [6 : 0] dina;
output [6 : 0] douta;
input clkb;
input [0 : 0] web;
input [8 : 0] addrb;
input [6 : 0] dinb;
output [6 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(9),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(512),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(7),
.C_READ_WIDTH_B(7),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(512),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(7),
.C_WRITE_WIDTH_B(7),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2I_TB_V
`define SKY130_FD_SC_LP__MUX2I_TB_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2i.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A0 = 1'b1;
#180 A1 = 1'b1;
#200 S = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A0 = 1'b0;
#320 A1 = 1'b0;
#340 S = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 S = 1'b1;
#540 A1 = 1'b1;
#560 A0 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 S = 1'bx;
#680 A1 = 1'bx;
#700 A0 = 1'bx;
end
sky130_fd_sc_lp__mux2i dut (.A0(A0), .A1(A1), .S(S), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2I_TB_V
|
`timescale 1 ns / 1 ps
module compute_unit_fpga #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 11
)
(
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 8;
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
wire rst;
wire clk;
wire slv_reg_wren;
wire slv_reg_rden;
reg slv_reg_wren_buffer;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
assign clk = S_AXI_ACLK;
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
wire fetch2buff_rd_en;
wire [31:0] fetch2buff_addr;
reg fetch2buff_rd_en_reg;
wire [38:0] fetch2buff_tag;
reg [38:0] fetch2buff_tag_reg;
wire cu2dispatch_wf_done;
wire [14:0] cu2dispatch_wf_tag_done;
wire [31:0] instruction_buff_out_a;
wire [31:0] instruction_buff_out_b;
// SGPR registers
reg [31:0] gprCommand;
wire mem2lsu_ack;
wire [6:0] mem2lsu_tag_resp;
wire lsu2mem_rd_en, lsu2mem_wr_en;
wire [6:0] lsu2mem_tag_req;
wire [31:0] lsu2mem_wr_data, mem2lsu_rd_data, lsu2mem_addr;
wire [2047:0] lsu2vgpr_dest_data, vgpr2lsu_source1_data;
wire [3:0] fpgamem2mb_op;
wire [31:0] fpgamem2mb_data;
wire [31:0] fpgamem2mb_addr;
reg mb2fpgamem_data_we;
reg mb2fpgamem_ack_reg;
reg mb2fpgamem_done_reg;
reg [C_S_AXI_DATA_WIDTH-1:0] waveID;
reg [C_S_AXI_DATA_WIDTH-1:0] baseVGPR;
reg [C_S_AXI_DATA_WIDTH-1:0] baseSGPR;
reg [C_S_AXI_DATA_WIDTH-1:0] baseLDS;
reg [C_S_AXI_DATA_WIDTH-1:0] waveCount;
reg [C_S_AXI_DATA_WIDTH-1:0] pcStart;
reg [C_S_AXI_DATA_WIDTH-1:0] resultsReady;
reg [C_S_AXI_DATA_WIDTH-1:0] resultsReadyTag;
reg instrBuffWrEn;
reg [31:0] instrAddrReg;
reg [8:0] quadBaseAddress;
reg [31:0] quadData0;
reg [31:0] quadData1;
reg [31:0] quadData2;
reg [31:0] quadData3;
reg lsu2sgpr_dest_wr_en_reg;
wire [127:0] sgpr2lsu_source1_data;
reg [9:0] singleVectorBaseAddress;
reg [63:0] singleVectorWrDataMask;
reg lsu2vgpr_dest_wr_en_reg;
`define IDLE_STATE 4'd0
`define DISPATCH_STATE 4'd1
`define EXECUTE_STATE 4'd2
`define RESULT_STATE 4'd3
reg [3:0] executeState;
reg [3:0] executeStateNext;
reg executeStart;
reg dispatch_idle;
reg mb_reset;
reg [31:0] singleVectorWrData0, singleVectorWrData1, singleVectorWrData2, singleVectorWrData3, singleVectorWrData4, singleVectorWrData5, singleVectorWrData6,
singleVectorWrData7, singleVectorWrData8, singleVectorWrData9, singleVectorWrData10, singleVectorWrData11, singleVectorWrData12, singleVectorWrData13,
singleVectorWrData14, singleVectorWrData15, singleVectorWrData16, singleVectorWrData17, singleVectorWrData18, singleVectorWrData19, singleVectorWrData20,
singleVectorWrData21, singleVectorWrData22, singleVectorWrData23, singleVectorWrData24, singleVectorWrData25, singleVectorWrData26, singleVectorWrData27,
singleVectorWrData28, singleVectorWrData29, singleVectorWrData30, singleVectorWrData31, singleVectorWrData32, singleVectorWrData33, singleVectorWrData34,
singleVectorWrData35, singleVectorWrData36, singleVectorWrData37, singleVectorWrData38, singleVectorWrData39, singleVectorWrData40, singleVectorWrData41,
singleVectorWrData42, singleVectorWrData43, singleVectorWrData44, singleVectorWrData45, singleVectorWrData46, singleVectorWrData47, singleVectorWrData48,
singleVectorWrData49, singleVectorWrData50, singleVectorWrData51, singleVectorWrData52, singleVectorWrData53, singleVectorWrData54, singleVectorWrData55,
singleVectorWrData56, singleVectorWrData57, singleVectorWrData58, singleVectorWrData59, singleVectorWrData60, singleVectorWrData61, singleVectorWrData62,
singleVectorWrData63;
always @( posedge S_AXI_ACLK ) begin
if ( S_AXI_ARESETN == 1'b0 ) begin
executeState <= `IDLE_STATE;
//cycle_counter <= 32'd0;
end
else begin
executeState <= executeStateNext;
//cycle_counter <= cycle_counter_next;
end
end
always @(*) begin
executeStateNext <= executeState;
//cycle_counter_next <= cycle_counter;
executeStart <= 1'b0;
resultsReady <= 32'd0;
dispatch_idle <= 1'b0;
//cycle_counter_wr_reg <= 1'b0;
case(executeState)
`IDLE_STATE: begin
dispatch_idle <= 1'b1;
if(slv_reg_wren && ~slv_reg_wren_buffer && axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 9'h000) begin
executeStart <= 1'b1;
executeStateNext <= `EXECUTE_STATE;
//cycle_counter_next <= 32'd0;
end
end
`EXECUTE_STATE: begin
//cycle_counter_next <= cycle_counter + 32'd1;
//cycle_counter_wr_reg <= 1'b1;
if(cu2dispatch_wf_done) begin
executeStateNext <= `RESULT_STATE;
end
end
`RESULT_STATE: begin
resultsReady <= 32'd1;
if(slv_reg_rden && axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 9'h000) begin
executeStateNext <= `IDLE_STATE;
end
end
endcase
end
assign rst = ~S_AXI_ARESETN;
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 ) begin
axi_awready <= 1'b0;
end
else begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID) begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 ) begin
axi_awaddr <= 0;
end
else begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID) begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 ) begin
axi_wready <= 1'b0;
end
else begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID) begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else begin
axi_wready <= 1'b0;
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK ) begin
if ( S_AXI_ARESETN == 1'b0 ) begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID) begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else begin
if (S_AXI_BREADY && axi_bvalid) begin
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK ) begin
if ( S_AXI_ARESETN == 1'b0 ) begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else begin
if (~axi_arready && S_AXI_ARVALID) begin
// indicates that the slave has accepted the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK ) begin
if ( S_AXI_ARESETN == 1'b0 ) begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid) begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY) begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
always @(*) begin
lsu2sgpr_dest_wr_en_reg <= 1'b0;
lsu2vgpr_dest_wr_en_reg <= 1'b0;
instrBuffWrEn <= 1'b1;
mb2fpgamem_data_we <= 1'b0;
if(slv_reg_wren && ~slv_reg_wren_buffer && axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 9'h0C0) begin
case(S_AXI_WDATA)
32'd0: lsu2sgpr_dest_wr_en_reg <= 1'b1;
32'd1: lsu2vgpr_dest_wr_en_reg <= 1'b1;
endcase
end
if(dispatch_idle && slv_reg_wren && ~slv_reg_wren_buffer && axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 9'h008) begin
instrBuffWrEn <= 1'b1;
end
if(slv_reg_wren && ~slv_reg_wren_buffer && axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 9'h041) begin
mb2fpgamem_data_we <= 1'b1;
end
end
always @( posedge S_AXI_ACLK ) begin
if ( S_AXI_ARESETN == 1'b0) begin
mb_reset <= 1'b1;
end
else begin
mb_reset <= mb_reset;
if (slv_reg_wren && axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 9'h009) begin
mb_reset <= ~S_AXI_WDATA[0];
end
end
end
always @( posedge S_AXI_ACLK ) begin
if ( S_AXI_ARESETN == 1'b0 || mb_reset == 1'b0 ) begin
waveID <= 32'd0;
baseVGPR <= 32'd0;
baseSGPR <= 32'd0;
baseLDS <= 32'd0;
waveCount <= 32'd0;
resultsReadyTag <= 32'd0;
slv_reg_wren_buffer <= 1'b0;
mb2fpgamem_ack_reg <= 1'b0;
mb2fpgamem_done_reg <= 1'b0;
quadBaseAddress <= 9'd0;
quadData0 <= 32'd0;
quadData1 <= 32'd0;
quadData2 <= 32'd0;
quadData3 <= 32'd0;
singleVectorBaseAddress <= 10'd0;
singleVectorWrDataMask <= 64'd0;
{
singleVectorWrData63, singleVectorWrData62, singleVectorWrData61, singleVectorWrData60, singleVectorWrData59, singleVectorWrData58,
singleVectorWrData57, singleVectorWrData56, singleVectorWrData55, singleVectorWrData54, singleVectorWrData53, singleVectorWrData52,
singleVectorWrData51, singleVectorWrData50, singleVectorWrData49, singleVectorWrData48, singleVectorWrData47, singleVectorWrData46,
singleVectorWrData45, singleVectorWrData44, singleVectorWrData43, singleVectorWrData42, singleVectorWrData41, singleVectorWrData40,
singleVectorWrData39, singleVectorWrData38, singleVectorWrData37, singleVectorWrData36, singleVectorWrData35, singleVectorWrData34,
singleVectorWrData33, singleVectorWrData32, singleVectorWrData31, singleVectorWrData30, singleVectorWrData29, singleVectorWrData28,
singleVectorWrData27, singleVectorWrData26, singleVectorWrData25, singleVectorWrData24, singleVectorWrData23, singleVectorWrData22,
singleVectorWrData21, singleVectorWrData20, singleVectorWrData19, singleVectorWrData18, singleVectorWrData17, singleVectorWrData16,
singleVectorWrData15, singleVectorWrData14, singleVectorWrData13, singleVectorWrData12, singleVectorWrData11, singleVectorWrData10,
singleVectorWrData9, singleVectorWrData8, singleVectorWrData7, singleVectorWrData6, singleVectorWrData5, singleVectorWrData4,
singleVectorWrData3, singleVectorWrData2, singleVectorWrData1, singleVectorWrData0
} <= 2048'd0;
end
else begin
slv_reg_wren_buffer <= slv_reg_wren;
if(cu2dispatch_wf_done) begin
resultsReadyTag <= {17'd0, cu2dispatch_wf_tag_done};
end
if (slv_reg_wren) begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
// 9'h00: Start command initiate program
9'h001: waveID <= S_AXI_WDATA;
9'h002: baseVGPR <= S_AXI_WDATA;
9'h003: baseSGPR <= S_AXI_WDATA;
9'h004: baseLDS <= S_AXI_WDATA;
9'h005: waveCount <= S_AXI_WDATA;
9'h006: pcStart <= S_AXI_WDATA;
9'h007: instrAddrReg <= S_AXI_WDATA;
// 9'h008: Instruction value
// 9'h009: MB reset
// 0x0100
// Memory registers
//9'h40: Writes to this address result in a write to the FPGA memory buffer
9'h041: mb2fpgamem_ack_reg <= S_AXI_WDATA[0];
9'h042: mb2fpgamem_done_reg <= S_AXI_WDATA[0];
// 0x0300
// 9'h0C0: GPR command register, used for both vector and scalar ops
// Scalar register registers
9'h0C1: quadBaseAddress <= S_AXI_WDATA[8:0];
9'h0C2: quadData0 <= S_AXI_WDATA;
9'h0C3: quadData1 <= S_AXI_WDATA;
9'h0C4: quadData2 <= S_AXI_WDATA;
9'h0C5: quadData3 <= S_AXI_WDATA;
// Vector register configuration registers
9'h0C6: singleVectorBaseAddress <= S_AXI_WDATA[9:0];
//9'h75: Vector write command
// Reset vector register inputs
9'h0C8: begin
{
singleVectorWrData63, singleVectorWrData62, singleVectorWrData61, singleVectorWrData60, singleVectorWrData59, singleVectorWrData58,
singleVectorWrData57, singleVectorWrData56, singleVectorWrData55, singleVectorWrData54, singleVectorWrData53, singleVectorWrData52,
singleVectorWrData51, singleVectorWrData50, singleVectorWrData49, singleVectorWrData48, singleVectorWrData47, singleVectorWrData46,
singleVectorWrData45, singleVectorWrData44, singleVectorWrData43, singleVectorWrData42, singleVectorWrData41, singleVectorWrData40,
singleVectorWrData39, singleVectorWrData38, singleVectorWrData37, singleVectorWrData36, singleVectorWrData35, singleVectorWrData34,
singleVectorWrData33, singleVectorWrData32, singleVectorWrData31, singleVectorWrData30, singleVectorWrData29, singleVectorWrData28,
singleVectorWrData27, singleVectorWrData26, singleVectorWrData25, singleVectorWrData24, singleVectorWrData23, singleVectorWrData22,
singleVectorWrData21, singleVectorWrData20, singleVectorWrData19, singleVectorWrData18, singleVectorWrData17, singleVectorWrData16,
singleVectorWrData15, singleVectorWrData14, singleVectorWrData13, singleVectorWrData12, singleVectorWrData11, singleVectorWrData10,
singleVectorWrData9, singleVectorWrData8, singleVectorWrData7, singleVectorWrData6, singleVectorWrData5, singleVectorWrData4,
singleVectorWrData3, singleVectorWrData2, singleVectorWrData1, singleVectorWrData0
} <= 2048'd0;
end
//DataMask_Lo
9'h0C9: singleVectorWrDataMask[31:0] <= S_AXI_WDATA;
//DataMask_Hi
9'h0CA: singleVectorWrDataMask[63:32] <= S_AXI_WDATA;
// 0x400
// Vector register data registers
9'h100: begin
singleVectorWrData0 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000000001;
end
9'h101: begin
singleVectorWrData1 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000000002;
end
9'h102: begin
singleVectorWrData2 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000000004;
end
9'h103: begin
singleVectorWrData3 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000000008;
end
9'h104: begin
singleVectorWrData4 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000000010;
end
9'h105: begin
singleVectorWrData5 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000000020;
end
9'h106: begin
singleVectorWrData6 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000000040;
end
9'h107: begin
singleVectorWrData7 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000000080;
end
9'h108: begin
singleVectorWrData8 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000000100;
end
9'h109: begin
singleVectorWrData9 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000000200;
end
9'h10A: begin
singleVectorWrData10 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000000400;
end
9'h10B: begin
singleVectorWrData11 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000000800;
end
9'h10C: begin
singleVectorWrData12 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000001000;
end
9'h10D: begin
singleVectorWrData13 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000002000;
end
9'h10E: begin
singleVectorWrData14 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000004000;
end
9'h10F: begin
singleVectorWrData15 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000008000;
end
9'h110: begin
singleVectorWrData16 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000010000;
end
9'h111: begin
singleVectorWrData17 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000020000;
end
9'h112: begin
singleVectorWrData18 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000040000;
end
9'h113: begin
singleVectorWrData19 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000080000;
end
9'h114: begin
singleVectorWrData20 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000100000;
end
9'h115: begin
singleVectorWrData21 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000200000;
end
9'h116: begin
singleVectorWrData22 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000400000;
end
9'h117: begin
singleVectorWrData23 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000000800000;
end
9'h118: begin
singleVectorWrData24 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000001000000;
end
9'h119: begin
singleVectorWrData25 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000002000000;
end
9'h11A: begin
singleVectorWrData26 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000004000000;
end
9'h11B: begin
singleVectorWrData27 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000008000000;
end
9'h11C: begin
singleVectorWrData28 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000010000000;
end
9'h11D: begin
singleVectorWrData29 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000020000000;
end
9'h11E: begin
singleVectorWrData30 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000040000000;
end
9'h11F: begin
singleVectorWrData31 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000080000000;
end
9'h120: begin
singleVectorWrData32 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000100000000;
end
9'h121: begin
singleVectorWrData33 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000200000000;
end
9'h122: begin
singleVectorWrData34 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000400000000;
end
9'h123: begin
singleVectorWrData35 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000000800000000;
end
9'h124: begin
singleVectorWrData36 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000001000000000;
end
9'h125: begin
singleVectorWrData37 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000002000000000;
end
9'h126: begin
singleVectorWrData38 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000004000000000;
end
9'h127: begin
singleVectorWrData39 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000008000000000;
end
9'h128: begin
singleVectorWrData40 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000010000000000;
end
9'h129: begin
singleVectorWrData41 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000020000000000;
end
9'h12A: begin
singleVectorWrData42 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000040000000000;
end
9'h12B: begin
singleVectorWrData43 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000080000000000;
end
9'h12C: begin
singleVectorWrData44 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000100000000000;
end
9'h12D: begin
singleVectorWrData45 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000200000000000;
end
9'h12E: begin
singleVectorWrData46 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000400000000000;
end
9'h12F: begin
singleVectorWrData47 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0000800000000000;
end
9'h130: begin
singleVectorWrData48 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0001000000000000;
end
9'h131: begin
singleVectorWrData49 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0002000000000000;
end
9'h132: begin
singleVectorWrData50 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0004000000000000;
end
9'h133: begin
singleVectorWrData51 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0008000000000000;
end
9'h134: begin
singleVectorWrData52 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0010000000000000;
end
9'h135: begin
singleVectorWrData53 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0020000000000000;
end
9'h136: begin
singleVectorWrData54 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0040000000000000;
end
9'h137: begin
singleVectorWrData55 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0080000000000000;
end
9'h138: begin
singleVectorWrData56 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0100000000000000;
end
9'h139: begin
singleVectorWrData57 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0200000000000000;
end
9'h13A: begin
singleVectorWrData58 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0400000000000000;
end
9'h13B: begin
singleVectorWrData59 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h0800000000000000;
end
9'h13C: begin
singleVectorWrData60 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h1000000000000000;
end
9'h13D: begin
singleVectorWrData61 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h2000000000000000;
end
9'h13E: begin
singleVectorWrData62 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h4000000000000000;
end
9'h13F: begin
singleVectorWrData63 <= S_AXI_WDATA;
singleVectorWrDataMask <= singleVectorWrDataMask | 64'h8000000000000000;
end
default: begin
waveID <= waveID;
baseVGPR <= baseVGPR;
baseSGPR <= baseSGPR;
baseLDS <= baseLDS;
waveCount <= waveCount;
pcStart <= pcStart;
instrAddrReg <= instrAddrReg;
mb2fpgamem_ack_reg <= mb2fpgamem_ack_reg;
mb2fpgamem_done_reg <= mb2fpgamem_done_reg;
quadBaseAddress <= quadBaseAddress;
quadData0 <= quadData0;
quadData1 <= quadData1;
quadData2 <= quadData2;
quadData3 <= quadData3;
singleVectorBaseAddress <= singleVectorBaseAddress;
singleVectorWrDataMask <= singleVectorWrDataMask;
singleVectorWrData63 <= singleVectorWrData63;
singleVectorWrData62 <= singleVectorWrData62;
singleVectorWrData61 <= singleVectorWrData61;
singleVectorWrData60 <= singleVectorWrData60;
singleVectorWrData59 <= singleVectorWrData59;
singleVectorWrData58 <= singleVectorWrData58;
singleVectorWrData57 <= singleVectorWrData57;
singleVectorWrData56 <= singleVectorWrData56;
singleVectorWrData55 <= singleVectorWrData55;
singleVectorWrData54 <= singleVectorWrData54;
singleVectorWrData53 <= singleVectorWrData53;
singleVectorWrData52 <= singleVectorWrData52;
singleVectorWrData51 <= singleVectorWrData51;
singleVectorWrData50 <= singleVectorWrData50;
singleVectorWrData49 <= singleVectorWrData49;
singleVectorWrData48 <= singleVectorWrData48;
singleVectorWrData47 <= singleVectorWrData47;
singleVectorWrData46 <= singleVectorWrData46;
singleVectorWrData45 <= singleVectorWrData45;
singleVectorWrData44 <= singleVectorWrData44;
singleVectorWrData43 <= singleVectorWrData43;
singleVectorWrData42 <= singleVectorWrData42;
singleVectorWrData41 <= singleVectorWrData41;
singleVectorWrData40 <= singleVectorWrData40;
singleVectorWrData39 <= singleVectorWrData39;
singleVectorWrData38 <= singleVectorWrData38;
singleVectorWrData37 <= singleVectorWrData37;
singleVectorWrData36 <= singleVectorWrData36;
singleVectorWrData35 <= singleVectorWrData35;
singleVectorWrData34 <= singleVectorWrData34;
singleVectorWrData33 <= singleVectorWrData33;
singleVectorWrData32 <= singleVectorWrData32;
singleVectorWrData31 <= singleVectorWrData31;
singleVectorWrData30 <= singleVectorWrData30;
singleVectorWrData29 <= singleVectorWrData29;
singleVectorWrData28 <= singleVectorWrData28;
singleVectorWrData27 <= singleVectorWrData27;
singleVectorWrData26 <= singleVectorWrData26;
singleVectorWrData25 <= singleVectorWrData25;
singleVectorWrData24 <= singleVectorWrData24;
singleVectorWrData23 <= singleVectorWrData23;
singleVectorWrData22 <= singleVectorWrData22;
singleVectorWrData21 <= singleVectorWrData21;
singleVectorWrData20 <= singleVectorWrData20;
singleVectorWrData19 <= singleVectorWrData19;
singleVectorWrData18 <= singleVectorWrData18;
singleVectorWrData17 <= singleVectorWrData17;
singleVectorWrData16 <= singleVectorWrData16;
singleVectorWrData15 <= singleVectorWrData15;
singleVectorWrData14 <= singleVectorWrData14;
singleVectorWrData13 <= singleVectorWrData13;
singleVectorWrData12 <= singleVectorWrData12;
singleVectorWrData11 <= singleVectorWrData11;
singleVectorWrData10 <= singleVectorWrData10;
singleVectorWrData9 <= singleVectorWrData9;
singleVectorWrData8 <= singleVectorWrData8;
singleVectorWrData7 <= singleVectorWrData7;
singleVectorWrData6 <= singleVectorWrData6;
singleVectorWrData5 <= singleVectorWrData5;
singleVectorWrData4 <= singleVectorWrData4;
singleVectorWrData3 <= singleVectorWrData3;
singleVectorWrData2 <= singleVectorWrData2;
singleVectorWrData1 <= singleVectorWrData1;
singleVectorWrData0 <= singleVectorWrData0;
end
endcase
end
end
end
always @(*) begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
9'h000 : reg_data_out <= resultsReady;
9'h001 : reg_data_out <= waveID;
9'h002 : reg_data_out <= baseVGPR;
9'h003 : reg_data_out <= baseSGPR;
9'h004 : reg_data_out <= baseLDS;
9'h005 : reg_data_out <= waveCount;
9'h006 : reg_data_out <= pcStart;
9'h007 : reg_data_out <= instrAddrReg;
9'h008 : reg_data_out <= instruction_buff_out_a;
9'h009 : reg_data_out <= resultsReadyTag;
//9'h00A : unused
9'h0C1 : reg_data_out <= quadBaseAddress;
9'h0C2 : reg_data_out <= sgpr2lsu_source1_data[31:0];
9'h0C3 : reg_data_out <= sgpr2lsu_source1_data[63:32];
9'h0C4 : reg_data_out <= sgpr2lsu_source1_data[95:64];
9'h0C5 : reg_data_out <= sgpr2lsu_source1_data[127:96];
9'h040 : reg_data_out <= {28'd0, fpgamem2mb_op};
9'h041 : reg_data_out <= fpgamem2mb_data;
9'h042 : reg_data_out <= fpgamem2mb_addr;
//7'h30 : reg_data_out <= cycle_counter;
//7'h31 : reg_data_out <= pc_value;
9'h100 : reg_data_out <= vgpr2lsu_source1_data[31:0];
9'h101 : reg_data_out <= vgpr2lsu_source1_data[63:32];
9'h102 : reg_data_out <= vgpr2lsu_source1_data[95:64];
9'h103 : reg_data_out <= vgpr2lsu_source1_data[127:96];
9'h104 : reg_data_out <= vgpr2lsu_source1_data[159:128];
9'h105 : reg_data_out <= vgpr2lsu_source1_data[191:160];
9'h106 : reg_data_out <= vgpr2lsu_source1_data[223:192];
9'h107 : reg_data_out <= vgpr2lsu_source1_data[255:224];
9'h108 : reg_data_out <= vgpr2lsu_source1_data[287:256];
9'h109 : reg_data_out <= vgpr2lsu_source1_data[319:288];
9'h10A : reg_data_out <= vgpr2lsu_source1_data[351:320];
9'h10B : reg_data_out <= vgpr2lsu_source1_data[383:352];
9'h10C : reg_data_out <= vgpr2lsu_source1_data[415:384];
9'h10D : reg_data_out <= vgpr2lsu_source1_data[447:416];
9'h10E : reg_data_out <= vgpr2lsu_source1_data[479:448];
9'h10F : reg_data_out <= vgpr2lsu_source1_data[511:480];
9'h110 : reg_data_out <= vgpr2lsu_source1_data[543:512];
9'h111 : reg_data_out <= vgpr2lsu_source1_data[575:544];
9'h112 : reg_data_out <= vgpr2lsu_source1_data[607:576];
9'h113 : reg_data_out <= vgpr2lsu_source1_data[639:608];
9'h114 : reg_data_out <= vgpr2lsu_source1_data[671:640];
9'h115 : reg_data_out <= vgpr2lsu_source1_data[703:672];
9'h116 : reg_data_out <= vgpr2lsu_source1_data[735:704];
9'h117 : reg_data_out <= vgpr2lsu_source1_data[767:736];
9'h118 : reg_data_out <= vgpr2lsu_source1_data[799:768];
9'h119 : reg_data_out <= vgpr2lsu_source1_data[831:800];
9'h11A : reg_data_out <= vgpr2lsu_source1_data[863:832];
9'h11B : reg_data_out <= vgpr2lsu_source1_data[895:864];
9'h11C : reg_data_out <= vgpr2lsu_source1_data[927:896];
9'h11D : reg_data_out <= vgpr2lsu_source1_data[959:928];
9'h11E : reg_data_out <= vgpr2lsu_source1_data[991:960];
9'h11F : reg_data_out <= vgpr2lsu_source1_data[1023:992];
9'h120 : reg_data_out <= vgpr2lsu_source1_data[1055:1024];
9'h121 : reg_data_out <= vgpr2lsu_source1_data[1087:1056];
9'h122 : reg_data_out <= vgpr2lsu_source1_data[1119:1088];
9'h123 : reg_data_out <= vgpr2lsu_source1_data[1151:1120];
9'h124 : reg_data_out <= vgpr2lsu_source1_data[1183:1152];
9'h125 : reg_data_out <= vgpr2lsu_source1_data[1215:1184];
9'h126 : reg_data_out <= vgpr2lsu_source1_data[1247:1216];
9'h127 : reg_data_out <= vgpr2lsu_source1_data[1279:1248];
9'h128 : reg_data_out <= vgpr2lsu_source1_data[1311:1280];
9'h129 : reg_data_out <= vgpr2lsu_source1_data[1343:1312];
9'h12A : reg_data_out <= vgpr2lsu_source1_data[1375:1344];
9'h12B : reg_data_out <= vgpr2lsu_source1_data[1407:1376];
9'h12C : reg_data_out <= vgpr2lsu_source1_data[1439:1408];
9'h12D : reg_data_out <= vgpr2lsu_source1_data[1471:1440];
9'h12E : reg_data_out <= vgpr2lsu_source1_data[1503:1472];
9'h12F : reg_data_out <= vgpr2lsu_source1_data[1535:1504];
9'h130 : reg_data_out <= vgpr2lsu_source1_data[1567:1536];
9'h131 : reg_data_out <= vgpr2lsu_source1_data[1599:1568];
9'h132 : reg_data_out <= vgpr2lsu_source1_data[1631:1600];
9'h133 : reg_data_out <= vgpr2lsu_source1_data[1663:1632];
9'h134 : reg_data_out <= vgpr2lsu_source1_data[1695:1664];
9'h135 : reg_data_out <= vgpr2lsu_source1_data[1727:1696];
9'h136 : reg_data_out <= vgpr2lsu_source1_data[1759:1728];
9'h137 : reg_data_out <= vgpr2lsu_source1_data[1791:1760];
9'h138 : reg_data_out <= vgpr2lsu_source1_data[1823:1792];
9'h139 : reg_data_out <= vgpr2lsu_source1_data[1855:1824];
9'h13A : reg_data_out <= vgpr2lsu_source1_data[1887:1856];
9'h13B : reg_data_out <= vgpr2lsu_source1_data[1919:1888];
9'h13C : reg_data_out <= vgpr2lsu_source1_data[1951:1920];
9'h13D : reg_data_out <= vgpr2lsu_source1_data[1983:1952];
9'h13E : reg_data_out <= vgpr2lsu_source1_data[2015:1984];
9'h13F : reg_data_out <= vgpr2lsu_source1_data[2047:2016];
default : reg_data_out <= 0;
endcase
end
always @( posedge S_AXI_ACLK ) begin
if ( S_AXI_ARESETN == 1'b0 ) begin
axi_rdata <= 0;
end
else begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden) begin
axi_rdata <= reg_data_out; // register read data
end
end
end
assign lsu2vgpr_dest_data = {
singleVectorWrData63, singleVectorWrData62, singleVectorWrData61, singleVectorWrData60, singleVectorWrData59, singleVectorWrData58,
singleVectorWrData57, singleVectorWrData56, singleVectorWrData55, singleVectorWrData54, singleVectorWrData53, singleVectorWrData52,
singleVectorWrData51, singleVectorWrData50, singleVectorWrData49, singleVectorWrData48, singleVectorWrData47, singleVectorWrData46,
singleVectorWrData45, singleVectorWrData44, singleVectorWrData43, singleVectorWrData42, singleVectorWrData41, singleVectorWrData40,
singleVectorWrData39, singleVectorWrData38, singleVectorWrData37, singleVectorWrData36, singleVectorWrData35, singleVectorWrData34,
singleVectorWrData33, singleVectorWrData32, singleVectorWrData31, singleVectorWrData30, singleVectorWrData29, singleVectorWrData28,
singleVectorWrData27, singleVectorWrData26, singleVectorWrData25, singleVectorWrData24, singleVectorWrData23, singleVectorWrData22,
singleVectorWrData21, singleVectorWrData20, singleVectorWrData19, singleVectorWrData18, singleVectorWrData17, singleVectorWrData16,
singleVectorWrData15, singleVectorWrData14, singleVectorWrData13, singleVectorWrData12, singleVectorWrData11, singleVectorWrData10,
singleVectorWrData9, singleVectorWrData8, singleVectorWrData7, singleVectorWrData6, singleVectorWrData5, singleVectorWrData4,
singleVectorWrData3, singleVectorWrData2, singleVectorWrData1, singleVectorWrData0
};
// I/O Connections assignments
assign buff2wave_tag = fetch2buff_tag_reg;
assign buff2fetchwave_ack = fetch2buff_rd_en_reg;
assign buff2wave_instr = instruction_buff_out_b;
always @( posedge clk) begin
fetch2buff_tag_reg <= fetch2buff_tag;
fetch2buff_rd_en_reg <= fetch2buff_rd_en;
//buff2wave_instr_reg <= instruction_buff_out_b;
end
//assign pc_value = fetch2buff_addr;
block_ram instruction_buffer
(
.clka(clk), // input clka
//.rsta(rst), // input rsta
.wea(instrBuffWrEn), // input [3 : 0] wea
.addra(instrAddrReg[9:0]), // input [31 : 0] addra
.dina(S_AXI_WDATA), // input [31 : 0] dina
.douta(instruction_buff_out_a), // output [31 : 0] douta
.clkb(clk), // input clkb
//.rstb(rst), // input rstb
.web(1'b0), // input [3 : 0] web
.addrb(fetch2buff_addr[11:2]), // input [31 : 0] addrb
.dinb(32'd0), // input [31 : 0] dinb
.doutb(instruction_buff_out_b) // output [31 : 0] doutb
);
compute_unit compute_unit0
(
// Outputs
.cu2dispatch_wf_done(cu2dispatch_wf_done),
.cu2dispatch_wf_tag_done(cu2dispatch_wf_tag_done),
.fetch2buff_rd_en(fetch2buff_rd_en),
.fetch2buff_addr(fetch2buff_addr),
.fetch2buff_tag(fetch2buff_tag),
.lsu2mem_rd_en(lsu2mem_rd_en),
.lsu2mem_wr_en(lsu2mem_wr_en),
.lsu2mem_tag_req(lsu2mem_tag_req),
.lsu2mem_wr_mask(),
.lsu2mem_addr(lsu2mem_addr),
.lsu2mem_wr_data(lsu2mem_wr_data),
.lsu2mem_gm_or_lds(),
.sgpr2dispatch_rd_data(sgpr2lsu_source1_data),
.vgpr2dispatch_rd_data(vgpr2lsu_source1_data),
// Inputs
.dispatch2cu_idle(dispatch_idle),
.dispatch2sgpr_addr(quadBaseAddress),
.dispatch2sgpr_wr_data({quadData3, quadData2, quadData1, quadData0}),
.dispatch2sgpr_wr_en(lsu2sgpr_dest_wr_en_reg),
.dispatch2vgpr_addr(singleVectorBaseAddress),
.dispatch2vgpr_wr_data(lsu2vgpr_dest_data),
.dispatch2vgpr_wr_en(lsu2vgpr_dest_wr_en_reg),
.dispatch2vgpr_wr_mask(singleVectorWrDataMask),
.dispatch2cu_wf_dispatch(executeStart),
.dispatch2cu_wf_tag_dispatch(waveID[14:0]),
.dispatch2cu_start_pc_dispatch(pcStart),
.dispatch2cu_sgpr_base_dispatch(baseSGPR[8:0]),
.dispatch2cu_vgpr_base_dispatch(baseVGPR[9:0]),
.dispatch2cu_lds_base_dispatch(baseLDS[15:0]),
// Instruction buffer
.buff2fetchwave_ack(fetch2buff_rd_en_reg),
.buff2wave_instr(instruction_buff_out_b),
.buff2wave_tag(fetch2buff_tag_reg),
.dispatch2cu_wg_wf_count(4'd1),
.dispatch2cu_wf_size_dispatch(waveCount[5:0]),
.mem2lsu_ack(mem2lsu_ack),
.mem2lsu_tag_resp(mem2lsu_tag_resp),
.mem2lsu_rd_data(mem2lsu_rd_data),
.clk(clk),
.rst(rst)
);
fpga_memory fpga_memory0(
.mem_wr_en(lsu2mem_wr_en),
.mem_rd_en(lsu2mem_rd_en),
.mem_addr(lsu2mem_addr),
.mem_wr_data(lsu2mem_wr_data),
.mem_tag_req(lsu2mem_tag_req),
// MB
//.mb_data_in(mb2fpgamem_data_in_reg),S_AXI_WDATA
.mb_data_in(S_AXI_WDATA),
.mb_data_we(mb2fpgamem_data_we),
.mb_ack(mb2fpgamem_ack_reg),
.mb_done(mb2fpgamem_done_reg),
.clk(clk),
.rst(rst),
// output
// LSU
.mem_tag_resp(mem2lsu_tag_resp),
.mem_rd_data(mem2lsu_rd_data),
.mem_ack(mem2lsu_ack),
// MB
.mb_op(fpgamem2mb_op),
.mb_data_out(fpgamem2mb_data),
.mb_addr(fpgamem2mb_addr)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32AI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O32AI_BEHAVIORAL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32AI_BEHAVIORAL_V |
/**
* $Id: red_pitaya_asg_ch.v 1271 2014-02-25 12:32:34Z matej.oblak $
*
* @brief Red Pitaya ASG submodule. Holds table and FSM for one channel.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/**
* GENERAL DESCRIPTION:
*
* Arbitrary signal generator takes data stored in buffer and sends them to DAC.
*
*
* /-----\ /--------\
* SW --------> | BUF | ------> | kx + o | ---> DAC DAT
* | \-----/ \--------/
* | ^
* | |
* | /-----\
* ----> | |
* | FSM | ------> trigger notification
* trigger ---> | |
* \-----/
*
*
* Submodule for ASG which hold buffer data and control registers for one channel.
*
*/
module red_pitaya_asg_ch #(
parameter RSZ = 14,
parameter CYCLE_BITS = 32
)(
// DAC
output reg [ 14-1: 0] dac_o , //!< dac data output
input dac_clk_i , //!< dac clock
input dac_rstn_i , //!< dac reset - active low
// trigger
input trig_sw_i , //!< software trigger
input trig_ext_i , //!< external trigger
input [ 3-1: 0] trig_src_i , //!< trigger source selector
output trig_done_o , //!< trigger event
// buffer ctrl
input buf_we_i , //!< buffer write enable
input [ 14-1: 0] buf_addr_i , //!< buffer address
input [ 14-1: 0] buf_wdata_i , //!< buffer write data
output reg [ 14-1: 0] buf_rdata_o , //!< buffer read data
output reg [RSZ-1: 0] buf_rpnt_o , //!< buffer current read pointer
// configuration
input [RSZ+16-1: 0] set_size_i , //!< set table data size
input [RSZ+16-1: 0] set_step_i , //!< set pointer step
input [RSZ+16-1: 0] set_ofs_i , //!< set reset offset
input set_rst_i , //!< set FSM to reset
input set_once_i , //!< set only once -- not used
input set_wrap_i , //!< set wrap enable
input [ 14-1: 0] set_amp_i , //!< set amplitude scale
input [ 14-1: 0] set_dc_i , //!< set output offset
input set_zero_i , //!< set output to zero
input [ CYCLE_BITS-1: 0] set_ncyc_i , //!< set number of cycle
input [ 16-1: 0] set_rnum_i , //!< set number of repetitions
input [ 32-1: 0] set_rdly_i , //!< set delay between repetitions
input set_rgate_i , //!< set external gated repetition
input rand_on_i , // random number generator on
input [RSZ-1:0] rand_pnt_i // random pointer for output data
);
//---------------------------------------------------------------------------------
//
// DAC buffer RAM
reg [ 14-1: 0] dac_buf [0:(1<<RSZ)-1] ;
reg [ 14-1: 0] dac_rd ;
reg [ 14-1: 0] dac_rdat ;
reg [ RSZ-1: 0] dac_rp ;
reg [RSZ+16-1: 0] dac_pnt ; // read pointer
reg [RSZ+16-1: 0] dac_pntp ; // previous read pointer
wire [RSZ+17-1: 0] dac_npnt ; // next read pointer
wire [RSZ+17-1: 0] dac_npnt_sub ;
wire dac_npnt_sub_neg;
reg [ 28-1: 0] dac_mult ;
reg [ 15-1: 0] dac_sum ;
// read
always @(posedge dac_clk_i)
begin
buf_rpnt_o <= dac_pnt[16+RSZ-1:16];
dac_rp <= (rand_on_i == 1'b1) ? rand_pnt_i : dac_pnt[RSZ+15:16];
dac_rd <= dac_buf[dac_rp] ;
dac_rdat <= dac_rd ; // improve timing
end
// write
always @(posedge dac_clk_i)
if (buf_we_i) dac_buf[buf_addr_i] <= buf_wdata_i[14-1:0] ;
// read-back disabled
//always @(posedge dac_clk_i)
//buf_rdata_o <= dac_buf[buf_addr_i] ;
// scale and offset
always @(posedge dac_clk_i)
begin
dac_mult <= $signed(dac_rdat) * $signed({1'b0,set_amp_i}) ;
dac_sum <= $signed(dac_mult[28-1:13]) + $signed(set_dc_i) ;
// saturation
if (set_zero_i) dac_o <= 14'h0;
else dac_o <= ^dac_sum[15-1:15-2] ? {dac_sum[15-1], {13{~dac_sum[15-1]}}} : dac_sum[13:0];
end
//---------------------------------------------------------------------------------
//
// read pointer & state machine
reg trig_in ;
wire ext_trig_p ;
wire ext_trig_n ;
reg [ 32-1: 0] cyc_cnt ;
reg [ 16-1: 0] rep_cnt ;
reg [ 32-1: 0] dly_cnt ;
reg [ 8-1: 0] dly_tick ;
reg dac_do ;
reg dac_rep ;
wire dac_trig ;
reg dac_trigr ;
// state machine
always @(posedge dac_clk_i) begin
if (dac_rstn_i == 1'b0) begin
cyc_cnt <= {CYCLE_BITS{1'b0}} ;
rep_cnt <= 16'h0 ;
dly_cnt <= 32'h0 ;
dly_tick <= 8'h0 ;
dac_do <= 1'b0 ;
dac_rep <= 1'b0 ;
trig_in <= 1'b0 ;
dac_pntp <= {RSZ+16{1'b0}} ;
dac_trigr <= 1'b0 ;
end
else begin
// make 1us tick
if (dac_do || (dly_tick == 8'd124))
dly_tick <= 8'h0 ;
else
dly_tick <= dly_tick + 8'h1 ;
// delay between repetitions
if (set_rst_i || dac_do)
dly_cnt <= set_rdly_i ;
else if (|dly_cnt && (dly_tick == 8'd124))
dly_cnt <= dly_cnt - 32'h1 ;
// repetitions counter
if (trig_in && !dac_do)
rep_cnt <= set_rnum_i ;
else if (!set_rgate_i && (|rep_cnt && dac_rep && (dac_trig && !dac_do)))
rep_cnt <= rep_cnt - 16'h1 ;
else if (set_rgate_i && ((!trig_ext_i && trig_src_i==3'd2) || (trig_ext_i && trig_src_i==3'd3)))
rep_cnt <= 16'h0 ;
// count number of table read cycles
dac_pntp <= dac_pnt;
dac_trigr <= dac_trig; // ignore trigger when count
if (dac_trig)
cyc_cnt <= set_ncyc_i ;
else if (!dac_trigr && |cyc_cnt && ({1'b0,dac_pntp} > {1'b0,dac_pnt}))
cyc_cnt <= cyc_cnt - 32'h1 ;
// trigger arrived
case (trig_src_i)
3'd1 : trig_in <= trig_sw_i ; // sw
3'd2 : trig_in <= ext_trig_p ; // external positive edge
3'd3 : trig_in <= ext_trig_n ; // external negative edge
3'd4 : trig_in <= trig_ext_i ; // unprocessed ext trigger
3'd5 : trig_in <= 1'b1 ; // always high
default : trig_in <= 1'b0 ;
endcase
// in cycle mode
if (dac_trig && !set_rst_i)
dac_do <= 1'b1 ;
else if (set_rst_i || ((cyc_cnt==32'h1) && ~dac_npnt_sub_neg) )
dac_do <= 1'b0 ;
// in repetition mode
if (dac_trig && !set_rst_i)
dac_rep <= 1'b1 ;
else if (set_rst_i || (rep_cnt==16'h0))
dac_rep <= 1'b0 ;
end
end
assign dac_trig = (!dac_rep && trig_in) || (dac_rep && |rep_cnt && (dly_cnt == 32'h0)) ;
assign dac_npnt_sub = dac_npnt - {1'b0,set_size_i} - 1;
assign dac_npnt_sub_neg = dac_npnt_sub[RSZ+16];
// read pointer logic
always @(posedge dac_clk_i)
if (dac_rstn_i == 1'b0) begin
dac_pnt <= {RSZ+16{1'b0}};
end else begin
if (set_rst_i || (dac_trig && !dac_do)) // manual reset or start
dac_pnt <= set_ofs_i;
else if (dac_do) begin
if (~dac_npnt_sub_neg) dac_pnt <= set_wrap_i ? dac_npnt_sub : set_ofs_i; // wrap or go to start
else dac_pnt <= dac_npnt[RSZ+16-1:0]; // normal increase
end
end
assign dac_npnt = dac_pnt + set_step_i;
assign trig_done_o = (!dac_rep && trig_in) | (~dac_npnt_sub_neg);
//---------------------------------------------------------------------------------
//
// External trigger
reg [ 3-1: 0] ext_trig_in ;
reg [ 2-1: 0] ext_trig_dp ;
reg [ 2-1: 0] ext_trig_dn ;
reg [ 20-1: 0] ext_trig_debp ;
reg [ 20-1: 0] ext_trig_debn ;
always @(posedge dac_clk_i) begin
if (dac_rstn_i == 1'b0) begin
ext_trig_in <= 3'h0 ;
ext_trig_dp <= 2'h0 ;
ext_trig_dn <= 2'h0 ;
ext_trig_debp <= 20'h0 ;
ext_trig_debn <= 20'h0 ;
end
else begin
//----------- External trigger
// synchronize FFs
ext_trig_in <= {ext_trig_in[1:0],trig_ext_i} ;
// look for input changes
if ((ext_trig_debp == 20'h0) && (ext_trig_in[1] && !ext_trig_in[2]))
ext_trig_debp <= 20'd62500 ; // ~0.5ms
else if (ext_trig_debp != 20'h0)
ext_trig_debp <= ext_trig_debp - 20'd1 ;
if ((ext_trig_debn == 20'h0) && (!ext_trig_in[1] && ext_trig_in[2]))
ext_trig_debn <= 20'd62500 ; // ~0.5ms
else if (ext_trig_debn != 20'h0)
ext_trig_debn <= ext_trig_debn - 20'd1 ;
// update output values
ext_trig_dp[1] <= ext_trig_dp[0] ;
if (ext_trig_debp == 20'h0)
ext_trig_dp[0] <= ext_trig_in[1] ;
ext_trig_dn[1] <= ext_trig_dn[0] ;
if (ext_trig_debn == 20'h0)
ext_trig_dn[0] <= ext_trig_in[1] ;
end
end
assign ext_trig_p = (ext_trig_dp == 2'b01) ;
assign ext_trig_n = (ext_trig_dn == 2'b10) ;
endmodule
|
module piano(sound, t0,t1,t2,t3,t4,t5,t6,t7,clk);
output wire[7:0] sound;
input t0,t1,t2,t3,t4,t5,t6,t7,clk;
wire [7:0] Chord;
wire [7:0] freq;
wire[3:0] sim,n;
wire [7:0] wave1,wave2,wave3,wave4,wave5,wave6,wave0,wave7;
wire ci0,ci1,ci2,ci3,ci4,ci5;
wire [7:0]clks;
wire [15:0]wavef;
assign Chord[0]=t0;
assign Chord[1]=t1;
assign Chord[2]=t2;
assign Chord[3]=t3;
assign Chord[4]=t4;
assign Chord[5]=t5;
assign Chord[6]=t6;
assign Chord[7]=t7;
divfreq note0(freq,Chord,clk);
assign clks = freq;
rom n0(clks[0],wave0);
rom n1(clks[1],wave1);
rom n2(clks[2],wave2);
rom n3(clks[3],wave3);
rom n4(clks[4],wave4);
rom n5(clks[5],wave5);
rom n6(clks[6],wave6);
rom n7(clks[7],wave7);
assign wavef= wave0+wave1+wave2+wave3+wave4+wave5+wave6+wave7;
assign sim = t0 + t1 + t2 + t3 + t4 + t5 + t6 + t7;
assign sound = (sim==0) ? 0:
(sim==1) ? wavef[7:0]:
(sim==2) ? wavef[8:1]:
(sim==3) ? wavef[9:2]:
(sim==4) ? wavef[10:3]:
(sim==5) ? wavef[11:4]:
(sim==6) ? wavef[12:5]:
(sim==7) ? wavef[13:6]:
(sim==8) ? wavef[14:7]:
wavef[15];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__AND3_PP_BLACKBOX_V
/**
* and3: 3-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:49:53 10/19/2015
// Design Name: UART_fifo_interface
// Module Name: C:/Users/Ariel/Xilinx/Workspace/UART/fifoTest.v
// Project Name: UART
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: UART_fifo_interface
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module fifoTest;
// Inputs
reg write_flag;
reg read_flag;
reg [7:0] data_in;
reg clock;
reg reset;
// Outputs
wire [7:0] data_out;
wire empty_flag;
wire full_flag;
// Instantiate the Unit Under Test (UUT)
UART_fifo_interface #(
.bits_depth(2)
) uut (
.write_flag(write_flag),
.read_flag(read_flag),
.data_in(data_in),
.clock(clock),
.reset(reset),
.data_out(data_out),
.empty_flag(empty_flag),
.full_flag(full_flag)
);
initial begin
// Initialize Inputs
write_flag = 0;
read_flag = 0;
data_in = 0;
clock = 0;
reset = 1;
// comienza prueba de escritura
#10;
reset = 0;
data_in = 1;
write_flag = 1;
#1;
write_flag = 0;
#1;
data_in = 2;
write_flag = 1;
#1;
write_flag = 0;
#1;
data_in = 3;
write_flag = 1;
#1;
write_flag = 0;
#1;
data_in = 4;
write_flag = 1;
#1;
write_flag = 0;
#1;
data_in = 5;
write_flag = 1;
#1;
write_flag = 0;
#1;
// hasta acá prueba de escritura, comienza prueba de lectura
read_flag = 1;
#1;
read_flag = 0;
#1;
read_flag = 1;
#1;
end
always begin
clock = ~clock;
#1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2OI_TB_V
`define SKY130_FD_SC_HS__A2BB2OI_TB_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a2bb2oi.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A1_N = 1'b1;
#160 A2_N = 1'b1;
#180 B1 = 1'b1;
#200 B2 = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A1_N = 1'b0;
#280 A2_N = 1'b0;
#300 B1 = 1'b0;
#320 B2 = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 B2 = 1'b1;
#440 B1 = 1'b1;
#460 A2_N = 1'b1;
#480 A1_N = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 B2 = 1'bx;
#560 B1 = 1'bx;
#580 A2_N = 1'bx;
#600 A1_N = 1'bx;
end
sky130_fd_sc_hs__a2bb2oi dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2OI_TB_V
|
`timescale 1 ns / 1 ps
`include "massive_pwm_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module massive_pwm_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND2_BEHAVIORAL_V
`define SKY130_FD_SC_LS__TAPVGND2_BEHAVIORAL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapvgnd2 ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND2_BEHAVIORAL_V |
`timescale 1ns/10ps
`define CYCLE_PERIOD 4.0
module PATTERN(
input [10:0] out,
input out_valid,
output reg [3:0] in,
output reg [1:0] mode,
output reg in_valid,
output reg clk,
output reg rst_n
);
parameter CYCLE = `CYCLE_PERIOD;
parameter PATTERN_NUM = 1000;
reg [7:0] times[0:8];
reg [2:0] mode_t;
reg [7:0] length,wait_clk,i,k,l;
reg [4:0] t1,t2,t3,t4,t5,t6,t7,t8,t9;
integer latency, total_latency;
integer pattern_num, j;
integer max,min,gold;
initial begin
total_latency = 0;
end
initial begin
clk = 0;
#10;
$display("before clk");
forever #(CYCLE/2) clk = ~clk;
end
initial begin
in <= 'dx;
mode <= 'dx;
in_valid <= 'bx;
rst_n <= 1'b1;
mode<='dx;
$display("before reset");
#2;
rst_n <= 1'b0;
#4;
rst_n <= 1'b1;
check_rst;
in_valid <= 'b0;
@(negedge clk);
pattern_num=0;
input_task1;
ans_calc;
wait_out;
check_ans;
for(pattern_num=1;pattern_num<PATTERN_NUM;pattern_num=pattern_num+1) begin
input_task;
ans_calc;
wait_out;
check_ans;
end
@(negedge clk);
$display ("--------------------------------------------------------------------");
$display (" Congratulations ! ");
$display (" You have passed all patterns ! ");
$display (" Your total latency is %6d ! ", total_latency);
$display ("--------------------------------------------------------------------");
@(negedge clk);
$finish;
end
task check_rst;
if(out !== 'd0 || out_valid !== 1'b0) begin
$display("");
$display("=================================================");
$display(" Output should be reset !!!! ");
$display("=================================================");
$display("");
@(negedge clk);
$finish;
end
endtask
task check_out_vaild;
if(out_valid !== 1'b0) begin
$display("");
$display("=================================================");
$display(" Out_valid should not be HIGH while in_valid is HIGH !!!!");
$display("=================================================");
$display("");
@(negedge clk);
$finish;
end
endtask
task input_task1;begin
for(i=0;i<9;i=i+1) begin
times[i] = 0;
end
length={$random()}%'d10+1;
mode_t=2;
max=0;
i=0;
while (i<9)begin
while (length>0 && times[8]<31)begin
in_valid <= 1'b1;
in <= i+1;
times[i]=times[i]+1;
if (times[i]>max) max=times[i];
if (times[i]==31) i=i+1;
length<=length-1;
check_out_vaild;
t1=times[0]; t2=times[1]; t3=times[2]; t4=times[3]; t5=times[4];
t6=times[5]; t7=times[6]; t8=times[7]; t9=times[8];
@(negedge clk);
end
in <= 'dx;
in_valid <= 1'b0;
wait_clk={$random()}%'d20;
repeat(wait_clk)@(negedge clk);
length={$random()}%'d10+1;
k=k-1;
end
in <= 0;
in_valid <= 1'b1;
@(negedge clk);
in <= 'dx;
in_valid <= 1'b0;
mode<=mode_t;
@(negedge clk);
mode<='dx;
end endtask
task input_task;begin
for(i=0;i<9;i=i+1) begin
times[i] = 0;
end
k={$random()}%'d31+1;
length={$random()}%'d10+1;
mode_t={$random()}%'d3;
max=0;
while (k>0 && max<31)begin
while (length>0 && max<31)begin
i={$random()}%'d9;
in_valid <= 1'b1;
in <= i+1;
times[i]=times[i]+1;
if (times[i]>max) max=times[i];
length<=length-1;
check_out_vaild;
t1=times[0]; t2=times[1]; t3=times[2]; t4=times[3]; t5=times[4];
t6=times[5]; t7=times[6]; t8=times[7]; t9=times[8];
@(negedge clk);
end
in <= 'dx;
in_valid <= 1'b0;
wait_clk={$random()}%'d20;
repeat(wait_clk)@(negedge clk);
length={$random()}%'d10+1;
k=k-1;
end
in <= 0;
in_valid <= 1'b1;
@(negedge clk);
in <= 'dx;
in_valid <= 1'b0;
mode<=mode_t;
@(negedge clk);
mode<='dx;
end endtask
task ans_calc;begin
min=33;
gold=0;
case (mode_t)
2'd0:gold=max;
2'd1:begin
for (i=0;i<9;i=i+1)begin
if (times[i]<min) min=times[i];
end
gold=min;
end
2'd2:begin
for (i=0;i<9;i=i+1)begin
gold=gold+(i+1)*times[i];
end
end
default:gold=0;
endcase
end endtask
task wait_out;begin
latency = -1;
while(!(out_valid === 1'b1)) begin
if(latency > 100) begin
$display("");
$display("=================================================");
$display(" Latency too more !!!! ");
$display("=================================================");
$display("");
@(negedge clk);
$finish;
end
latency = latency + 1;
total_latency = total_latency + 1;
@(negedge clk);
end
end endtask
task check_ans;begin
i=0;
while(out_valid) begin
if(out !== gold) begin
$display("");
$display("=================================================");
$display(" Failed!! PATTERN %4d is wrong! ", pattern_num+1);
$display(" mode=%d gold=%d your ans=%d ",mode_t,gold,out);
$display("=================================================");
$display("");
@(negedge clk);
$finish;
end
if(i>=1)
begin
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
$display (" FAIL! ");
$display (" Outvalid is more than 1 cycles ");
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
repeat(9) @(negedge clk);
$finish;
end
i=i+1;
@(negedge clk);
end
$display("");
$display(" Pass pattern %3d ", pattern_num+1);
@(negedge clk);
end endtask
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_PP_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__clkinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINV_FUNCTIONAL_PP_V |
/*
Copyright (c) 2014-2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* ARP ethernet frame receiver (Ethernet frame in, ARP frame out)
*/
module arp_eth_rx #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire s_eth_payload_axis_tuser,
/*
* ARP frame output
*/
output wire m_frame_valid,
input wire m_frame_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [15:0] m_arp_htype,
output wire [15:0] m_arp_ptype,
output wire [7:0] m_arp_hlen,
output wire [7:0] m_arp_plen,
output wire [15:0] m_arp_oper,
output wire [47:0] m_arp_sha,
output wire [31:0] m_arp_spa,
output wire [47:0] m_arp_tha,
output wire [31:0] m_arp_tpa,
/*
* Status signals
*/
output wire busy,
output wire error_header_early_termination,
output wire error_invalid_header
);
parameter CYCLE_COUNT = (28+KEEP_WIDTH-1)/KEEP_WIDTH;
parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
parameter OFFSET = 28 % KEEP_WIDTH;
// bus width assertions
initial begin
if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
end
/*
ARP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0806) 2 octets
HTYPE (1) 2 octets
PTYPE (0x0800) 2 octets
HLEN (6) 1 octets
PLEN (4) 1 octets
OPER 2 octets
SHA Sender MAC 6 octets
SPA Sender IP 4 octets
THA Target MAC 6 octets
TPA Target IP 4 octets
This module receives an Ethernet frame with header fields in parallel and
payload on an AXI stream interface, decodes the ARP packet fields, and
produces the frame fields in parallel.
*/
// datapath control signals
reg store_eth_hdr;
reg read_eth_header_reg = 1'b1, read_eth_header_next;
reg read_arp_header_reg = 1'b0, read_arp_header_next;
reg [PTR_WIDTH-1:0] ptr_reg = 0, ptr_next;
reg s_eth_hdr_ready_reg = 1'b0, s_eth_hdr_ready_next;
reg s_eth_payload_axis_tready_reg = 1'b0, s_eth_payload_axis_tready_next;
reg m_frame_valid_reg = 1'b0, m_frame_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg [15:0] m_arp_htype_reg = 16'd0, m_arp_htype_next;
reg [15:0] m_arp_ptype_reg = 16'd0, m_arp_ptype_next;
reg [7:0] m_arp_hlen_reg = 8'd0, m_arp_hlen_next;
reg [7:0] m_arp_plen_reg = 8'd0, m_arp_plen_next;
reg [15:0] m_arp_oper_reg = 16'd0, m_arp_oper_next;
reg [47:0] m_arp_sha_reg = 48'd0, m_arp_sha_next;
reg [31:0] m_arp_spa_reg = 32'd0, m_arp_spa_next;
reg [47:0] m_arp_tha_reg = 48'd0, m_arp_tha_next;
reg [31:0] m_arp_tpa_reg = 32'd0, m_arp_tpa_next;
reg busy_reg = 1'b0;
reg error_header_early_termination_reg = 1'b0, error_header_early_termination_next;
reg error_invalid_header_reg = 1'b0, error_invalid_header_next;
assign s_eth_hdr_ready = s_eth_hdr_ready_reg;
assign s_eth_payload_axis_tready = s_eth_payload_axis_tready_reg;
assign m_frame_valid = m_frame_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_arp_htype = m_arp_htype_reg;
assign m_arp_ptype = m_arp_ptype_reg;
assign m_arp_hlen = m_arp_hlen_reg;
assign m_arp_plen = m_arp_plen_reg;
assign m_arp_oper = m_arp_oper_reg;
assign m_arp_sha = m_arp_sha_reg;
assign m_arp_spa = m_arp_spa_reg;
assign m_arp_tha = m_arp_tha_reg;
assign m_arp_tpa = m_arp_tpa_reg;
assign busy = busy_reg;
assign error_header_early_termination = error_header_early_termination_reg;
assign error_invalid_header = error_invalid_header_reg;
always @* begin
read_eth_header_next = read_eth_header_reg;
read_arp_header_next = read_arp_header_reg;
ptr_next = ptr_reg;
s_eth_hdr_ready_next = 1'b0;
s_eth_payload_axis_tready_next = 1'b0;
store_eth_hdr = 1'b0;
m_frame_valid_next = m_frame_valid_reg && !m_frame_ready;
m_arp_htype_next = m_arp_htype_reg;
m_arp_ptype_next = m_arp_ptype_reg;
m_arp_hlen_next = m_arp_hlen_reg;
m_arp_plen_next = m_arp_plen_reg;
m_arp_oper_next = m_arp_oper_reg;
m_arp_sha_next = m_arp_sha_reg;
m_arp_spa_next = m_arp_spa_reg;
m_arp_tha_next = m_arp_tha_reg;
m_arp_tpa_next = m_arp_tpa_reg;
error_header_early_termination_next = 1'b0;
error_invalid_header_next = 1'b0;
if (s_eth_hdr_ready && s_eth_hdr_valid) begin
if (read_eth_header_reg) begin
store_eth_hdr = 1'b1;
ptr_next = 0;
read_eth_header_next = 1'b0;
read_arp_header_next = 1'b1;
end
end
if (s_eth_payload_axis_tready && s_eth_payload_axis_tvalid) begin
if (read_arp_header_reg) begin
// word transfer in - store it
ptr_next = ptr_reg + 1;
`define _HEADER_FIELD_(offset, field) \
if (ptr_reg == offset/KEEP_WIDTH && (!KEEP_ENABLE || s_eth_payload_axis_tkeep[offset%KEEP_WIDTH])) begin \
field = s_eth_payload_axis_tdata[(offset%KEEP_WIDTH)*8 +: 8]; \
end
`_HEADER_FIELD_(0, m_arp_htype_next[1*8 +: 8])
`_HEADER_FIELD_(1, m_arp_htype_next[0*8 +: 8])
`_HEADER_FIELD_(2, m_arp_ptype_next[1*8 +: 8])
`_HEADER_FIELD_(3, m_arp_ptype_next[0*8 +: 8])
`_HEADER_FIELD_(4, m_arp_hlen_next[0*8 +: 8])
`_HEADER_FIELD_(5, m_arp_plen_next[0*8 +: 8])
`_HEADER_FIELD_(6, m_arp_oper_next[1*8 +: 8])
`_HEADER_FIELD_(7, m_arp_oper_next[0*8 +: 8])
`_HEADER_FIELD_(8, m_arp_sha_next[5*8 +: 8])
`_HEADER_FIELD_(9, m_arp_sha_next[4*8 +: 8])
`_HEADER_FIELD_(10, m_arp_sha_next[3*8 +: 8])
`_HEADER_FIELD_(11, m_arp_sha_next[2*8 +: 8])
`_HEADER_FIELD_(12, m_arp_sha_next[1*8 +: 8])
`_HEADER_FIELD_(13, m_arp_sha_next[0*8 +: 8])
`_HEADER_FIELD_(14, m_arp_spa_next[3*8 +: 8])
`_HEADER_FIELD_(15, m_arp_spa_next[2*8 +: 8])
`_HEADER_FIELD_(16, m_arp_spa_next[1*8 +: 8])
`_HEADER_FIELD_(17, m_arp_spa_next[0*8 +: 8])
`_HEADER_FIELD_(18, m_arp_tha_next[5*8 +: 8])
`_HEADER_FIELD_(19, m_arp_tha_next[4*8 +: 8])
`_HEADER_FIELD_(20, m_arp_tha_next[3*8 +: 8])
`_HEADER_FIELD_(21, m_arp_tha_next[2*8 +: 8])
`_HEADER_FIELD_(22, m_arp_tha_next[1*8 +: 8])
`_HEADER_FIELD_(23, m_arp_tha_next[0*8 +: 8])
`_HEADER_FIELD_(24, m_arp_tpa_next[3*8 +: 8])
`_HEADER_FIELD_(25, m_arp_tpa_next[2*8 +: 8])
`_HEADER_FIELD_(26, m_arp_tpa_next[1*8 +: 8])
`_HEADER_FIELD_(27, m_arp_tpa_next[0*8 +: 8])
if (ptr_reg == 27/KEEP_WIDTH && (!KEEP_ENABLE || s_eth_payload_axis_tkeep[27%KEEP_WIDTH])) begin
read_arp_header_next = 1'b0;
end
`undef _HEADER_FIELD_
end
if (s_eth_payload_axis_tlast) begin
if (read_arp_header_next) begin
// don't have the whole header
error_header_early_termination_next = 1'b1;
end else if (m_arp_hlen_next != 4'd6 || m_arp_plen_next != 4'd4) begin
// lengths not valid
error_invalid_header_next = 1'b1;
end else begin
// otherwise, transfer tuser
m_frame_valid_next = !s_eth_payload_axis_tuser;
end
ptr_next = 1'b0;
read_eth_header_next = 1'b1;
read_arp_header_next = 1'b0;
end
end
if (read_eth_header_next) begin
s_eth_hdr_ready_next = !m_frame_valid_next;
end else begin
s_eth_payload_axis_tready_next = 1'b1;
end
end
always @(posedge clk) begin
read_eth_header_reg <= read_eth_header_next;
read_arp_header_reg <= read_arp_header_next;
ptr_reg <= ptr_next;
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
m_frame_valid_reg <= m_frame_valid_next;
m_arp_htype_reg <= m_arp_htype_next;
m_arp_ptype_reg <= m_arp_ptype_next;
m_arp_hlen_reg <= m_arp_hlen_next;
m_arp_plen_reg <= m_arp_plen_next;
m_arp_oper_reg <= m_arp_oper_next;
m_arp_sha_reg <= m_arp_sha_next;
m_arp_spa_reg <= m_arp_spa_next;
m_arp_tha_reg <= m_arp_tha_next;
m_arp_tpa_reg <= m_arp_tpa_next;
error_header_early_termination_reg <= error_header_early_termination_next;
error_invalid_header_reg <= error_invalid_header_next;
busy_reg <= read_arp_header_next;
// datapath
if (store_eth_hdr) begin
m_eth_dest_mac_reg <= s_eth_dest_mac;
m_eth_src_mac_reg <= s_eth_src_mac;
m_eth_type_reg <= s_eth_type;
end
if (rst) begin
read_eth_header_reg <= 1'b1;
read_arp_header_reg <= 1'b0;
ptr_reg <= 0;
s_eth_payload_axis_tready_reg <= 1'b0;
m_frame_valid_reg <= 1'b0;
busy_reg <= 1'b0;
error_header_early_termination_reg <= 1'b0;
error_invalid_header_reg <= 1'b0;
end
end
endmodule
|
module low_level_command_processor(
clk, // input
reset_n, // input, asynchronous
reset, // input, syncronous
start, // input
done, // output
command, // input
arg1, // input
arg2, // input
sda, // inout
scl, // inout
sp_trst, // output
sp_tms, // output
sp_tck, // output
sp_tdo, // output
//clk_scan, // output
lcp_state, // output, read by rf
i2c_master_state, // output, read by rf
timer_state, // output
scan_clock_frequency, // output
tap_states_feedback, // all tap states ! , input, holds tap state read from tap state monitor (in executor module)
tap_states_send // all tap states !, output, sends tap state to tap state monitor (in executor module)
);
`include "parameters_global.v"
input clk;
input reset_n;
input reset; // propagates into all submodules
input start;
output reg done;
input [`byte_width-1:0] command;
input [`byte_width-1:0] arg1; // lowbyte
input [`byte_width-1:0] arg2; // highbyte
inout sda;
inout scl;
output reg [`scanpath_count_max:1] sp_trst;
output reg [`scanpath_count_max:1] sp_tms;
output reg [`scanpath_count_max:1] sp_tck;
output reg [`scanpath_count_max:1] sp_tdo;
input [(`scanpath_count_max * `nibble_width)-1:0] tap_states_feedback; // holds all tap states
// CS: evaluate it before executing tap state commands
// CS: update it after execution of every tap state command
output reg [(`scanpath_count_max * `nibble_width)-1:0] tap_states_send; // holds all tap states
// for trst commands
`define tck_count_width 5 // holds up to 31 tck changes (or 15 tck cycles)
parameter tck_count_init = `tck_count_width'd19; // equals 10 tck cycles (must be an even number)
reg [`tck_count_width-1:0] tck_count;
output reg [`byte_width-1:0] scan_clock_frequency;
reg sct_start;
scan_clock_timer sct (
.clk(clk), // input
.reset_n(reset_n), // input
.reset(reset), // input
.delay(scan_clock_frequency), // input
.start(sct_start), // input
.done(sct_done), // output
.step_mode_tck(1'b0), // input // no step mode required here
.go_step_tck(1'b0) // input // no step mode required here
);
wire [`byte_width-1:0] i2c_rx_byte; // byte received from i2c master
reg [`byte_width-1:0] i2c_tx_byte; // byte sent by i2c master
reg i2c_tx_data, i2c_rx_data, // high indicates that i2c master is to send or receive a byte
i2c_tx_start_condition, i2c_tx_stop_condition, // high indicates that i2c master is to send a start or stop condition
i2c_start; // general start signal that triggers the i2c master
wire i2c_done;
output [`byte_width-1:0] i2c_master_state;
i2c_master im(
.clk(clk), // input
.reset_n(reset_n), // input
.reset(reset), // input
.sda(sda), // inout
.scl(scl), // inout
.tx_byte(i2c_tx_byte), // input, byte to send to slave
.rx_byte(i2c_rx_byte), // output, byte received from slave
.tx_start_condition(i2c_tx_start_condition), // input, high, when i2c master is to send a start signal
.tx_stop_condition(i2c_tx_stop_condition), // input, high, when i2c master is to send a stop signal
.tx_data(i2c_tx_data), // input, high, when i2c master is to send a byte as given in tx_byte
.rx_data(i2c_rx_data), // input, high, when i2c master is to receive a byte and output it in rx_byte
.start(i2c_start), // input, starts i2c master
.done(i2c_done), // output, high when i2c master done
.i2c_master_state(i2c_master_state) // output
);
output reg [`byte_width-1:0] lcp_state;
reg [`byte_width-1:0] lcp_state_last;
reg i2c_command_executed;
output [`timer_state_width-1:0] timer_state;
reg timer_start;
timer ti(
.clk(clk), // input
.reset_n(reset_n), // input
.reset(reset), // input
.delay(arg1), // input
.start(timer_start), // input
.done(timer_done), // output, high on timeout
.timer_state(timer_state) // output
);
always @(posedge clk or negedge reset_n) begin
if (~reset_n)
begin
done <= #`DEL 1'b0; // indicates executor that low level command has been executed
i2c_command_executed <= #`DEL 1'b0; // reset i2c_command_executed for i2c master wait states
i2c_tx_start_condition <= #`DEL 1'b0;
i2c_tx_stop_condition <= #`DEL 1'b0;
i2c_tx_data <= #`DEL 1'b0;
i2c_rx_data <= #`DEL 1'b0;
i2c_start <= #`DEL 1'b0;
i2c_tx_byte <= #`DEL `byte_width'h00;
lcp_state <= #`DEL LCP_STATE_IDLE;
lcp_state_last <= #`DEL LCP_STATE_IDLE;
timer_start <= #`DEL 1'b0;
sct_start <= #`DEL 1'b0;
tck_count <= #`DEL tck_count_init;
sp_trst <= #`DEL init_state_trst;
sp_tms <= #`DEL init_state_tms;
sp_tck <= #`DEL init_state_tck;
sp_tdo <= #`DEL init_state_tdo;
tap_states_send <= #`DEL {`scanpath_count_max * TAP_TEST_LOGIG_RESET}; //NOTE: TRST applies for ALL scanpaths !
end
else
begin
if (reset) // syncronous reset has the same effect as asynchronous reset
begin
done <= #`DEL 1'b0; // indicates executor that low level command has been executed
i2c_command_executed <= #`DEL 1'b0; // reset i2c_command_executed for i2c master wait states
i2c_tx_start_condition <= #`DEL 1'b0;
i2c_tx_stop_condition <= #`DEL 1'b0;
i2c_tx_data <= #`DEL 1'b0;
i2c_rx_data <= #`DEL 1'b0;
i2c_start <= #`DEL 1'b0;
i2c_tx_byte <= #`DEL `byte_width'h00;
lcp_state <= #`DEL LCP_STATE_IDLE;
lcp_state_last <= #`DEL LCP_STATE_IDLE;
timer_start <= #`DEL 1'b0;
sct_start <= #`DEL 1'b0;
tck_count <= #`DEL tck_count_init;
sp_trst <= #`DEL init_state_trst;
sp_tms <= #`DEL init_state_tms;
sp_tck <= #`DEL init_state_tck;
sp_tdo <= #`DEL init_state_tdo;
tap_states_send <= #`DEL {`scanpath_count_max * TAP_TEST_LOGIG_RESET}; //NOTE: TRST applies for ALL scanpaths !
end
else
begin
case (lcp_state) // synthesis parallel_case
// EVALUATE AND CHECK COMMAND AND ARGUMENTS
LCP_STATE_IDLE: //0h
begin
done <= #`DEL 1'b0;
if (start) begin
case (command) // check command. if invalid go to error state
lc_set_frq_tck:
begin // arg1 holds frequency, arg2 fixed to zero
scan_clock_frequency <= #`DEL arg1;
case (arg2) // synthesis parallel_case
lc_null_argument:
lcp_state <= #`DEL LCP_STATE_SET_FRQ; // 01h
default:
lcp_state <= #`DEL LCP_STATE_ERROR_ARG2; // F2h
endcase
end
lc_set_sp_thrshld_tdi: // addresses a DAC
begin // NOTE: check argument 1 only. if invalid argument go to error state
case (arg1) // synthesis parallel_case
lc_scanport_1, lc_scanport_2:
begin
lcp_state <= #`DEL LCP_STATE_SET_SUB_BUS_1_DAC_5;
end
default:
begin
lcp_state <= #`DEL LCP_STATE_ERROR_ARG1; // F1h
end
endcase
end
lc_set_sp_vltg_out:
begin // NOTE: check argument 1 only. if invalid argument go to error state
case (arg1) // synthesis parallel_case
lc_scanport_1, lc_scanport_2:
begin
lcp_state <= #`DEL LCP_STATE_SET_MAIN_DRV_VLTGE_1; // 1Fh // address I2C expander
end
default:
begin
lcp_state <= #`DEL LCP_STATE_ERROR_ARG1; // F1h
end
endcase
end
lc_set_drv_chr_tms_tck, lc_set_drv_chr_trst_tdo: // both address an i2c expander
begin // NOTE: check argument 1 only. if invalid argument go to error state
// CS: checking argument 2 requires comparing with valid expander output pattern
case (arg1) // synthesis parallel_case
lc_scanport_1, lc_scanport_2:
begin
lcp_state <= #`DEL LCP_STATE_SET_MAIN_DRV_CHAR_1; // Ch
end
default:
begin
lcp_state <= #`DEL LCP_STATE_ERROR_ARG1; // F1h
end
endcase
end
lc_delay:
begin // check argument. if invalid argument go to error state
case (arg2) // synthesis parallel_case
lc_delay_arg2 : // arg2 is always zero
begin
lcp_state <= #`DEL LCP_STATE_START_TIMER_1; // 10h
end
default:
begin
lcp_state <= #`DEL LCP_STATE_ERROR_ARG2; // F2h
end
endcase
end
lc_power_on_off:
begin // check arguments. if invalid arguments go to error state
case (arg1) // synthesis parallel_case
lc_pwr_gnd, lc_pwr_1, lc_pwr_2, lc_pwr_3, lc_pwr_all:
begin
case (arg2) // synthesis parallel_case
lc_off, lc_on:
begin
// Since this HW does not feature power relays nothing will happen here:
lcp_state <= #`DEL LCP_STATE_SEND_DONE_TO_EX; // 23h
end
default:
lcp_state <= #`DEL LCP_STATE_ERROR_ARG2; // F2h
endcase
end
default:
begin
lcp_state <= #`DEL LCP_STATE_ERROR_ARG1; // F1h
end
endcase
end
lc_set_imax:
begin // check arguments. if invalid arguments go to error state
// NOTE: check arg1 only
case (arg1) // synthesis parallel_case
lc_pwr_1, lc_pwr_2, lc_pwr_3:
begin
// since this HW does not feature current monitoring nothing will happen here:
lcp_state <= #`DEL LCP_STATE_SEND_DONE_TO_EX; // 23h
end
default:
begin
lcp_state <= #`DEL LCP_STATE_ERROR_ARG1; // F1h
end
endcase
end
lc_set_timeout:
begin // check arguments. if invalid arguments go to error state
// NOTE: check arg1 only
case (arg1) // synthesis parallel_case
lc_pwr_1, lc_pwr_2, lc_pwr_3:
begin
// since this HW does not feature current monitoring nothing will happen here:
lcp_state <= #`DEL LCP_STATE_SEND_DONE_TO_EX; // 23h
end
default:
begin
lcp_state <= #`DEL LCP_STATE_ERROR_ARG1; // F1h
end
endcase
end
lc_connect_disconnect:
begin // check arguments. if invalid arguments go to error state
case (arg1) // synthesis parallel_case
lc_scanport_1, lc_scanport_2:
begin
case (arg2) // synthesis parallel_case
lc_off, lc_on:
begin
// since this HW does not feature scanport relays nothing will happen here:
lcp_state <= #`DEL LCP_STATE_SEND_DONE_TO_EX; // 23h
end
default:
lcp_state <= #`DEL LCP_STATE_ERROR_ARG2; // F2h
endcase
end
default:
begin
lcp_state <= #`DEL LCP_STATE_ERROR_ARG1; // F1h
end
endcase
end
lc_tap_state:
begin // check arguments. if invalid arguments go to error state
case (arg1) // synthesis parallel_case
lc_tap_trst, lc_tap_strst, lc_tap_htrst: //, lc_tap_rti, lc_tap_pdr, lc_tap_pir
begin
case (arg2) // synthesis parallel_case
lc_null_argument:
lcp_state <= #`DEL LCP_STATE_TAP_TRST_1; // 1Bh
default:
lcp_state <= #`DEL LCP_STATE_ERROR_ARG2; // F2h
endcase
end
default:
begin
lcp_state <= #`DEL LCP_STATE_ERROR_ARG1; // F1h
end
endcase
end
default:
begin // if invalid command -> error
lcp_state <= #`DEL LCP_STATE_ERROR_CMD;
//done <= #`DEL 1'b0;
end
endcase
end
end
// This is a state that is used for non-featured functions. Its only purpose is to
// signal the executor, that the command has been executed.
// Afterward it directs the command processor to return to idle mode.
LCP_STATE_SEND_DONE_TO_EX: // 23h
begin
done <= #`DEL 1'b1; // signal executor low level command done
lcp_state <= #`DEL LCP_STATE_IDLE; // 0h
end
// SET SCAN FREQUENCY // CS:
LCP_STATE_SET_FRQ: // 01h
begin
done <= #`DEL 1'b1;
lcp_state <= #`DEL LCP_STATE_IDLE;
end
// WAIT STATE FOR I2C MASTER OPERATION
LCP_STATE_I2C_RDY: // 02h
begin // i2c master is running
i2c_start <= #`DEL 1'b0; // reset start signal
// wait for i2c master done with execution
if (i2c_done) // return to last lcp state
begin
lcp_state <= #`DEL lcp_state_last;
// set i2c_command_executed so that after return, the main line can proceed
// does not get started again
i2c_command_executed <= #`DEL 1'b1;
end
end
// SET DACS
LCP_STATE_SET_SUB_BUS_1_DAC_5: // 07h // start condition
begin
// initally i2c_command_executed is 0 -> starting i2c_master requried
// on return from LCP_STATE_WAIT i2c_command_executed is 1 -> proceed with next state
if (i2c_command_executed)
begin
i2c_command_executed <= #`DEL 1'b0; // reset i2c_command_executed for other wait states
i2c_tx_start_condition <= #`DEL 1'b0;
i2c_start <= #`DEL 1'b0;
lcp_state <= #`DEL LCP_STATE_SET_SUB_BUS_1_DAC_6; // 8h // proceed to next state
end
else // set inputs for i2c master and start i2c master
begin
i2c_tx_start_condition <= #`DEL 1'b1; // input for i2c master
i2c_start <= #`DEL 1'b1; // start i2c master
// backup this state for return from wait states
lcp_state_last <= #`DEL lcp_state;
// go to wait state
lcp_state <= #`DEL LCP_STATE_I2C_RDY; // 2h
end
end
LCP_STATE_SET_SUB_BUS_1_DAC_6: // 08h // address DAC
begin
// initally i2c_command_executed is 0 -> starting i2c_master requried
// on return from LCP_STATE_WAIT i2c_command_executed is 1 -> proceed with next state
if (i2c_command_executed)
begin
i2c_command_executed <= #`DEL 1'b0; // reset i2c_command_executed for other wait states
i2c_tx_data <= #`DEL 1'b0;
i2c_start <= #`DEL 1'b0;
lcp_state <= #`DEL LCP_STATE_SET_SUB_BUS_1_DAC_7; // 9h // proceed to next state
end
else // set inputs for i2c master and start i2c master
begin
case (arg1) // synthesis parallel_case // arg1 specifies the scanport
lc_scanport_1: i2c_tx_byte <= #`DEL i2c_addr_thrshld_tdi_1;
lc_scanport_2: i2c_tx_byte <= #`DEL i2c_addr_thrshld_tdi_2;
endcase
i2c_tx_data <= #`DEL 1'b1; // input for i2c master
i2c_start <= #`DEL 1'b1; // start i2c master
// backup this state for return from wait states
lcp_state_last <= #`DEL lcp_state;
// go to wait state
lcp_state <= #`DEL LCP_STATE_I2C_RDY; // 2h
end
end
LCP_STATE_SET_SUB_BUS_1_DAC_7: // 09h // send command byte to DAC
begin
// initally i2c_command_executed is 0 -> starting i2c_master requried
// on return from LCP_STATE_WAIT i2c_command_executed is 1 -> proceed with next state
if (i2c_command_executed)
begin
i2c_command_executed <= #`DEL 1'b0; // reset i2c_command_executed for other wait states
i2c_tx_data <= #`DEL 1'b0;
i2c_start <= #`DEL 1'b0;
lcp_state <= #`DEL LCP_STATE_SET_SUB_BUS_1_DAC_8; // Ah // proceed to next state
end
else // set inputs for i2c master and start i2c master
begin
i2c_tx_byte <= #`DEL i2c_data_dac_cmd;
i2c_tx_data <= #`DEL 1'b1; // input for i2c master
i2c_start <= #`DEL 1'b1; // start i2c master
// backup this state for return from wait states
lcp_state_last <= #`DEL lcp_state;
// go to wait state
lcp_state <= #`DEL LCP_STATE_I2C_RDY; // 2h
end
end
LCP_STATE_SET_SUB_BUS_1_DAC_8: // 0Ah // send output byte to DAC
begin
// initally i2c_command_executed is 0 -> starting i2c_master requried
// on return from LCP_STATE_WAIT i2c_command_executed is 1 -> proceed with next state
if (i2c_command_executed)
begin
i2c_command_executed <= #`DEL 1'b0; // reset i2c_command_executed for other wait states
i2c_tx_data <= #`DEL 1'b0;
i2c_start <= #`DEL 1'b0;
lcp_state <= #`DEL LCP_STATE_SET_SUB_BUS_1_DAC_9; // Bh // proceed to next state
end
else // set inputs for i2c master and start i2c master
begin
i2c_tx_byte <= #`DEL arg2; // THIS IS THE DAC OUTPUT BYTE !
i2c_tx_data <= #`DEL 1'b1; // input for i2c master
i2c_start <= #`DEL 1'b1; // start i2c master
// backup this state for return from wait states
lcp_state_last <= #`DEL lcp_state;
// go to wait state
lcp_state <= #`DEL LCP_STATE_I2C_RDY; // 2h
end
end
LCP_STATE_SET_SUB_BUS_1_DAC_9: // 0Bh // stop condition
begin
// initally i2c_command_executed is 0 -> starting i2c_master requried
// on return from LCP_STATE_WAIT i2c_command_executed is 1 -> proceed with next state
if (i2c_command_executed)
begin
i2c_command_executed <= #`DEL 1'b0; // reset i2c_command_executed for other wait states
i2c_tx_stop_condition <= #`DEL 1'b0;
i2c_start <= #`DEL 1'b0;
done <= #`DEL 1'b1; // signal executor low level command done
lcp_state <= #`DEL LCP_STATE_IDLE; // 00h // proceed to next state
end
else // set inputs for i2c master and start i2c master
begin
i2c_tx_stop_condition <= #`DEL 1'b1; // input for i2c master
i2c_start <= #`DEL 1'b1; // start i2c master
// backup this state for return from wait states
lcp_state_last <= #`DEL lcp_state;
// go to wait state
lcp_state <= #`DEL LCP_STATE_I2C_RDY; // 3h
end
end
// SET SCANPORT DRIVER CHARACTERISTICS
LCP_STATE_SET_MAIN_DRV_CHAR_1: // 0Ch // start condition
begin
// initally i2c_command_executed is 0 -> starting i2c_master requried
// on return from LCP_STATE_WAIT i2c_command_executed is 1 -> proceed with next state
if (i2c_command_executed)
begin
i2c_command_executed <= #`DEL 1'b0; // reset i2c_command_executed for other wait states
i2c_tx_start_condition <= #`DEL 1'b0;
i2c_start <= #`DEL 1'b0;
lcp_state <= #`DEL LCP_STATE_SET_MAIN_DRV_CHAR_2; // 0Dh // proceed to next state
end
else // set inputs for i2c master and start i2c master
begin
i2c_tx_start_condition <= #`DEL 1'b1; // input for i2c master
i2c_start <= #`DEL 1'b1; // start i2c master
// backup this state for return from wait states
lcp_state_last <= #`DEL lcp_state;
// go to wait state
lcp_state <= #`DEL LCP_STATE_I2C_RDY; // 2h
end
end
LCP_STATE_SET_MAIN_DRV_CHAR_2: // 0Dh // send address of register for driver characteristics
begin
// initally i2c_command_executed is 0 -> starting i2c_master requried
// on return from LCP_STATE_WAIT i2c_command_executed is 1 -> proceed with next state
if (i2c_command_executed)
begin
i2c_command_executed <= #`DEL 1'b0; // reset i2c_command_executed for other wait states
i2c_tx_data <= #`DEL 1'b0;
i2c_start <= #`DEL 1'b0;
lcp_state <= #`DEL LCP_STATE_SET_MAIN_DRV_CHAR_3; // 0Eh // proceed to next state
end
else // set inputs for i2c master and start i2c master
begin
case (command) // synthesis parallel_case // depending on given command, the i2c expander address differs
lc_set_drv_chr_tms_tck:
begin
case (arg1) // synthesis parallel_case // arg1 specifies the scanport
lc_scanport_1: i2c_tx_byte <= #`DEL i2c_addr_main_drv_char_tck_tms_tap_1;
lc_scanport_2: i2c_tx_byte <= #`DEL i2c_addr_main_drv_char_tck_tms_tap_2;
endcase
end
lc_set_drv_chr_trst_tdo:
begin
case (arg1) // synthesis parallel_case // arg1 specifies the scanport
lc_scanport_1: i2c_tx_byte <= #`DEL i2c_addr_main_drv_char_tdo_trst_tap_1;
lc_scanport_2: i2c_tx_byte <= #`DEL i2c_addr_main_drv_char_tdo_trst_tap_2;
endcase
end
endcase
i2c_tx_data <= #`DEL 1'b1; // input for i2c master
i2c_start <= #`DEL 1'b1; // start i2c master
// backup this state for return from wait states
lcp_state_last <= #`DEL lcp_state;
// go to wait state
lcp_state <= #`DEL LCP_STATE_I2C_RDY; // 2h
end
end
LCP_STATE_SET_MAIN_DRV_CHAR_3: // 0Eh // send output byte to i2c expander
begin
// initally i2c_command_executed is 0 -> starting i2c_master requried
// on return from LCP_STATE_WAIT i2c_command_executed is 1 -> proceed with next state
if (i2c_command_executed)
begin
i2c_command_executed <= #`DEL 1'b0; // reset i2c_command_executed for other wait states
i2c_tx_data <= #`DEL 1'b0;
i2c_start <= #`DEL 1'b0;
lcp_state <= #`DEL LCP_STATE_SET_MAIN_DRV_CHAR_4; // Fh // proceed to next state
end
else // set inputs for i2c master and start i2c master
begin
i2c_tx_byte <= #`DEL arg2; // THIS IS THE DRIVER CHARACTERISTICS OUTPUT BYTE !
i2c_tx_data <= #`DEL 1'b1; // input for i2c master
i2c_start <= #`DEL 1'b1; // start i2c master
// backup this state for return from wait states
lcp_state_last <= #`DEL lcp_state;
// go to wait state
lcp_state <= #`DEL LCP_STATE_I2C_RDY; // 2h
end
end
LCP_STATE_SET_MAIN_DRV_CHAR_4: // 0Fh // stop condition
begin
// initally i2c_command_executed is 0 -> starting i2c_master requried
// on return from LCP_STATE_WAIT i2c_command_executed is 1 -> proceed with next state
if (i2c_command_executed)
begin
i2c_command_executed <= #`DEL 1'b0; // reset i2c_command_executed for other wait states
i2c_tx_stop_condition <= #`DEL 1'b0;
i2c_start <= #`DEL 1'b0;
done <= #`DEL 1'b1; // signal executor: low level command done
lcp_state <= #`DEL LCP_STATE_IDLE; // 00h // proceed to next state
end
else // set inputs for i2c master and start i2c master
begin
i2c_tx_stop_condition <= #`DEL 1'b1; // input for i2c master
i2c_start <= #`DEL 1'b1; // start i2c master
// backup this state for return from wait states
lcp_state_last <= #`DEL lcp_state;
// go to wait state
lcp_state <= #`DEL LCP_STATE_I2C_RDY; // 3h
end
end
// SET DRIVER OUTPUT VOLTAGE
LCP_STATE_SET_MAIN_DRV_VLTGE_1: // 1Fh // start condition
begin
// initally i2c_command_executed is 0 -> starting i2c_master requried
// on return from LCP_STATE_WAIT i2c_command_executed is 1 -> proceed with next state
if (i2c_command_executed)
begin
i2c_command_executed <= #`DEL 1'b0; // reset i2c_command_executed for other wait states
i2c_tx_start_condition <= #`DEL 1'b0;
i2c_start <= #`DEL 1'b0;
lcp_state <= #`DEL LCP_STATE_SET_MAIN_DRV_VLTGE_2; // 20h // proceed to next state
end
else // set inputs for i2c master and start i2c master
begin
i2c_tx_start_condition <= #`DEL 1'b1; // input for i2c master
i2c_start <= #`DEL 1'b1; // start i2c master
// backup this state for return from wait states
lcp_state_last <= #`DEL lcp_state;
// go to wait state
lcp_state <= #`DEL LCP_STATE_I2C_RDY; // 2h
end
end
LCP_STATE_SET_MAIN_DRV_VLTGE_2: // 20h // send address of register for adjusting driver output voltage
begin
// initally i2c_command_executed is 0 -> starting i2c_master requried
// on return from LCP_STATE_WAIT i2c_command_executed is 1 -> proceed with next state
if (i2c_command_executed)
begin
i2c_command_executed <= #`DEL 1'b0; // reset i2c_command_executed for other wait states
i2c_tx_data <= #`DEL 1'b0;
i2c_start <= #`DEL 1'b0;
lcp_state <= #`DEL LCP_STATE_SET_MAIN_DRV_VLTGE_3; // 21h // proceed to next state
end
else // set inputs for i2c master and start i2c master
begin
case (arg1) // synthesis parallel_case // arg1 specifies the scanport
lc_scanport_1: i2c_tx_byte <= #`DEL i2c_addr_vltg_tap_1;
lc_scanport_2: i2c_tx_byte <= #`DEL i2c_addr_vltg_tap_2;
endcase
i2c_tx_data <= #`DEL 1'b1; // input for i2c master
i2c_start <= #`DEL 1'b1; // start i2c master
// backup this state for return from wait states
lcp_state_last <= #`DEL lcp_state;
// go to wait state
lcp_state <= #`DEL LCP_STATE_I2C_RDY; // 2h
end
end
LCP_STATE_SET_MAIN_DRV_VLTGE_3: // 21h // send output byte to i2c expander
begin
// initally i2c_command_executed is 0 -> starting i2c_master requried
// on return from LCP_STATE_WAIT i2c_command_executed is 1 -> proceed with next state
if (i2c_command_executed)
begin
i2c_command_executed <= #`DEL 1'b0; // reset i2c_command_executed for other wait states
i2c_tx_data <= #`DEL 1'b0;
i2c_start <= #`DEL 1'b0;
lcp_state <= #`DEL LCP_STATE_SET_MAIN_DRV_VLTGE_4; // 22h // proceed to next state
end
else // set inputs for i2c master and start i2c master
begin
case (arg2) // synthesis parallel_case
tap_driver_vltg_1V5: i2c_tx_byte <= #`DEL i2c_data_driver_vltg_1V5;
tap_driver_vltg_1V8: i2c_tx_byte <= #`DEL i2c_data_driver_vltg_1V8;
tap_driver_vltg_2V5: i2c_tx_byte <= #`DEL i2c_data_driver_vltg_2V5;
tap_driver_vltg_3V3: i2c_tx_byte <= #`DEL i2c_data_driver_vltg_3V3;
default:
begin
lcp_state <= #`DEL LCP_STATE_ERROR_ARG2; // F2h
end
endcase
i2c_tx_data <= #`DEL 1'b1; // input for i2c master
i2c_start <= #`DEL 1'b1; // start i2c master
// backup this state for return from wait states
lcp_state_last <= #`DEL lcp_state;
// go to wait state
lcp_state <= #`DEL LCP_STATE_I2C_RDY; // 2h
end
end
LCP_STATE_SET_MAIN_DRV_VLTGE_4: // 22h // stop condition
begin
// initally i2c_command_executed is 0 -> starting i2c_master requried
// on return from LCP_STATE_WAIT i2c_command_executed is 1 -> proceed with next state
if (i2c_command_executed)
begin
i2c_command_executed <= #`DEL 1'b0; // reset i2c_command_executed for other wait states
i2c_tx_stop_condition <= #`DEL 1'b0;
i2c_start <= #`DEL 1'b0;
done <= #`DEL 1'b1; // signal executor: low level command done
lcp_state <= #`DEL LCP_STATE_IDLE; // 00h // proceed to next state
end
else // set inputs for i2c master and start i2c master
begin
i2c_tx_stop_condition <= #`DEL 1'b1; // input for i2c master
i2c_start <= #`DEL 1'b1; // start i2c master
// backup this state for return from wait states
lcp_state_last <= #`DEL lcp_state;
// go to wait state
lcp_state <= #`DEL LCP_STATE_I2C_RDY; // 3h
end
end
// START TIMER
LCP_STATE_START_TIMER_1: // 10h
begin
timer_start <= #`DEL 1'b1;
lcp_state <= #`DEL LCP_STATE_START_TIMER_2; // 11h
end
LCP_STATE_START_TIMER_2: // 11h
begin
timer_start <= #`DEL 1'b0;
if (timer_done)
begin
done <= #`DEL 1'b1; // signal executor: low level command done
lcp_state <= #`DEL LCP_STATE_IDLE;
end
end
// TAP TRST
LCP_STATE_TAP_TRST_1: // 1Bh
// CS: PERFORM TRST WITH A LOW STATIC TCK FREQUENCY SO THAT UUT RESETS EVEN IN WORST CONDTITIONS !
begin
// assert hard reset only when full trst or hard trst requried
if (arg1 == lc_tap_trst || arg1 == lc_tap_htrst)
begin
sp_trst <= #`DEL 0; // assert trst
end
sct_start <= #`DEL 1; // start scan clock timer
lcp_state <= #`DEL LCP_STATE_TAP_TRST_2; // 1Ch // proceed to next state
end
LCP_STATE_TAP_TRST_2: // 1Ch
begin
// wait until scan clock timer finishes pause
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
lcp_state <= #`DEL LCP_STATE_TAP_TRST_3; // 1Dh
end
end
LCP_STATE_TAP_TRST_3: // 1Dh
begin
// toggle tck if full trst or soft trst requried
if (arg1 == lc_tap_trst || arg1 == lc_tap_strst)
begin
if (tck_count[0] == 1)
sp_tck <= #`DEL -1;
else
sp_tck <= #`DEL 0;
end
// if tck_count not zero, decement tck_count
// on zero count, proceed with next state
if (tck_count > 0)
begin
tck_count <= #`DEL tck_count - 1;
lcp_state <= #`DEL LCP_STATE_TAP_TRST_2; // 1Ch // go to wait state again
end
else
begin
tck_count <= #`DEL tck_count_init;
lcp_state <= #`DEL LCP_STATE_TAP_TRST_4; // 1Eh
end
sct_start <= #`DEL 1; // start scan clock timer, regardless which state is next
end
LCP_STATE_TAP_TRST_4: // 1Eh
begin
// wait until scan clock timer finishes pause
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_trst <= #`DEL -1; // deassert trst, even if not asserted before (due to strst)
done <= #`DEL 1'b1; // signal executor low level command done
// send executor the latest tap state. NOTE: TRST applies for ALL scanpaths !
tap_states_send <= #`DEL {`scanpath_count_max * TAP_TEST_LOGIG_RESET};
lcp_state <= #`DEL LCP_STATE_IDLE; // 00h // proceed to next state
end
end
endcase
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2I_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__MUX2I_PP_BLACKBOX_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__mux2i (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2I_PP_BLACKBOX_V
|
`include "defines.v"
//////////////////////////////////////////////////////////////////////////////////
// Company: WSIZ Copernicus
// Engineer: Rafa³ B., Szymon S., Darek B.
//
// Create Date: 25.04.2017 18:46:49
// Design Name:
// Module Name: mdk
// Project Name: Maszyna do kawy
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mdk_top(
//input wire clk, // zegar
input wire clk_div, // zegar z dzielnika czêstotliwoci
// sygna³ z przycisków
input wire [2:0]panel_przyciskow_in, // przyciski - wybór kawy
// czujnik sprawnoci maszyny
input wire sprawnosc_in, // czujnikami zajmie siê inny modu³ - tu wystarczy sygna³: 0-sprawny, 1-niesprawny
// licznik
input wire licz_in, // 0 - stoi, 1 - liczy
input wire [6:0] count_secs, // potrzebne do wywietlacza - iloæ pozosta³ych sekund
output reg [3:0] licz_out, // wyjcie do licznika
// sterowanie modu³em monet
input wire[1:0]cmd_in, // odpowiedz na koendê z modu³u odpowedzialnego za monety
input wire[4:0]stan_mm, // potrzebne do obs³ugi wywietlacza
output reg [2:0]cmd_out, // komenda do modu³u odpowedzialnego za monety
// wywietlacz
output reg [4:0] L_1, // segment 1
output reg [4:0] L_2, // segment 2
output reg [4:0] L_3, // segment 3
output reg [4:0] L_4, // segment 4
// sterowanie poszczególnymi etapami parzenia kawy - do zmiany na [2:0]
output reg [2:0]urzadzenia // sterowanie urz¹dzeniami
// 000 - nic nie pracuje
//output reg kubek, // 001 - podstawienie kubka
//output reg woda, // 010 - w³¹czanie dozowania wody
//output reg kawa, // 011 - w³¹czanie m³ynka do kawy
//output reg mleko // 100 - w³¹czanie dozowania mleka (spieniacz)
);
parameter CENA_OP1 = `m300; // cena opcji 1 (3.00z³ - expresso)
parameter CENA_OP2 = `m500; // cena opcji 2 (5.00z³ - expresso grande :P )
parameter CENA_OP3 = `m750; // cena opcji 3 (7.50z³ - cappucino :P )
parameter tick_every = 20; // pozwoli dostosowaæ czasy do zegaru (oraz przyspieszyæ symulacjê ;] )
// ³¹czymy modu³y
// pod³¹czamy modu³ monet
//^ modul_monet #(.CENA_OP1(CENA_OP1), .CENA_OP2(CENA_OP2), .CENA_OP3(CENA_OP3)) wrzut_zwrot(.clk(clk_div), .cmd_in(cmd_out), .cmd_out(cmd_in), .stan_mm(stan_mm));
// pod³¹czamy modu³ sprawnosci
//^ sprawnosc spr_test(.signal_s(sprawnosc_in));
// pod³¹czamy modu³ licznika
//^ counter #(.tick_every(tick_every)) licznik(.clk(clk_div), .count_out(licz_in), .count_in(licz_out), .count_secs(count_secs));
// pod³¹czamy modu³ wywietlacza
//^ wyswietlacz_4x7seg wys_pan(.clk(clk), .L_1(L_1), .L_2(L_2), .L_3(L_3), .L_4(L_4));
// pod³¹czamy dzielnik czêstotliwoci
//^ divider #(1) div(.clk(clk), .clk_div(clk_div));
reg [3:0]stan_top, stan_n; // stan i nastêpny stan modu³u g³ównego
function [9:0]licznikNaLiczby;
input reg [6:0] count_secs;
integer a,b;
begin
b = count_secs / 10;
a = count_secs - (b*10);
licznikNaLiczby = {b[4:0],a[4:0]};
$strobe("strobe count_secs:%b(%0d) a:%b(%0d) b:%b(%0d) @ %0t", count_secs, count_secs, b[4:0], b[4:0], a[4:0], a[4:0], $time);
end
endfunction
always @(panel_przyciskow_in)
#1 begin
if (panel_przyciskow_in == `CMD_RESET && cmd_in === 2'bXX) // automat nic nie robi - reset pocz¹tkowy
begin
// ustawienia poczatkowe
stan_top = 0;
stan_n = 0;
urzadzenia = `NIC;
cmd_out = `CMD_RESET; // resetujemy modu³ monet
licz_out = `LICZNIK_RESET; // resetujemy licznik
// reset wyswietlacza
L_1 = 5'b00000;
L_2 = 5'b00000;
L_3 = 5'b00000;
L_4 = 5'b00000;
end
if (sprawnosc_in == 1'b0) begin // sterowanie dostêpne tylko w przypadku sprawnej maszyny
case (panel_przyciskow_in)
`CMD_OP1: // wciniêto przycisk wyboru opcji 1
if(cmd_in == `ODP_NIC) // jeli modu³ nic nie robi
begin
cmd_out = `CMD_OP1; // rozpoczynamy pobór monet
stan_n = `POBIERAM;
end
`CMD_OP2: // wciniêto przycisk wyboru opcji 2
if(cmd_in == `ODP_NIC) // jeli modu³ nic nie robi
begin
cmd_out = `CMD_OP2; // rozpoczynamy pobór monet
stan_n = `POBIERAM;
end
`CMD_OP3: // wciniêto przycisk wyboru opcji 3
if(cmd_in == `ODP_NIC) // jeli modu³ nic nie robi
begin
cmd_out = `CMD_OP3; // rozpoczynamy pobór monet
stan_n = `POBIERAM;
end
`CMD_RESET:
begin
if (stan_top < `PODSTAW_KUBEK) // zapobiega resetowi w momencie, gdy automat parzy ju¿ kawê
begin
case(cmd_out)
`CMD_OP1:
begin
cmd_out = `CMD_RESET1;
stan_n = `ZWRACAM;
end
`CMD_OP2:
begin
cmd_out = `CMD_RESET2;
stan_n = `ZWRACAM;
end
`CMD_OP3:
begin
cmd_out = `CMD_RESET3;
stan_n = `ZWRACAM;
end
endcase
end
end
endcase
end
stan_top <= stan_n;
end
always @(licz_in)
begin
if (licz_in == `SKONCZYLEM_ODLICZAC)
begin
case (stan_top)
`NAPELNIJ_PRZEWODY: begin stan_n = `PODSTAW_KUBEK; licz_out <= `ODLICZ_KUBEK; urzadzenia <= `CMD_PODSTAW_KUBEK; end
`PODSTAW_KUBEK:
begin
stan_n = `ZMIEL_KAWE;
case(cmd_out)
`CMD_OP1: begin licz_out <= `ODLICZ_KAWA_OP1; end
`CMD_OP2: begin licz_out <= `ODLICZ_KAWA_OP2; end
`CMD_OP3: begin licz_out <= `ODLICZ_KAWA_OP3; end
endcase
urzadzenia <= `CMD_ZMIEL_KAWE;
end
`ZMIEL_KAWE:
begin
stan_n = `DODAJ_WODE;
case(cmd_out)
`CMD_OP1: begin licz_out <= `ODLICZ_WODA_OP1; end
`CMD_OP2: begin licz_out <= `ODLICZ_WODA_OP2; end
`CMD_OP3: begin licz_out <= `ODLICZ_WODA_OP3; end
endcase
urzadzenia <= `CMD_DODAJ_WODE;
end
`DODAJ_WODE:
begin
case(cmd_out)
`CMD_OP1: begin stan_n = `CZYSC_MASZYNE; licz_out <= `ODLICZ_CZYSC; urzadzenia <= `CMD_CZYSC_MASZYNE; end
`CMD_OP2: begin stan_n = `CZYSC_MASZYNE; licz_out <= `ODLICZ_CZYSC; urzadzenia <= `CMD_CZYSC_MASZYNE; end
`CMD_OP3: begin stan_n = `SPIENIAJ_MLEKO; licz_out <= `ODLICZ_MLEKO; urzadzenia <= `CMD_SPIENIAJ_MLEKO; end
endcase
end
`SPIENIAJ_MLEKO:
begin
stan_n = `CZYSC_MASZYNE;
licz_out <= `ODLICZ_CZYSC;
urzadzenia <= `CMD_CZYSC_MASZYNE;
end
`CZYSC_MASZYNE:
begin
stan_n = `CZEKAM;
licz_out <= `LICZNIK_NULL;
urzadzenia <= `CMD_ZERO;
end
endcase
end
stan_top <= stan_n;
end
always @(cmd_in) // odpowied z modu³u monet
begin
stan_n = stan_top;
case (stan_top)
`POBIERAM:
begin
if ( cmd_in == `ODP_OK) // zkoñczono pobór op³aty gdy brak resetu
begin
stan_n <= `NAPELNIJ_PRZEWODY;
licz_out <= `ODLICZ_NAPELN;
urzadzenia <= `CMD_NAPELNIJ_PRZEWODY;
end
end
endcase
end
always @(posedge clk_div) // g³owna czêæ
begin
stan_n <= stan_top;
case (stan_top)
`CZEKAM:
begin // NIC SIE NIE DZIEJE - PUSTY WYSWIETLACZ
{L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b0,`W_NULL,1'b0,`W_NULL,1'b0,`W_NULL};
end
`POBIERAM: // pobieram op³atê
begin
case(stan_mm)
`NIC: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_0,1'b0,`W_0,1'b0,`W_0};
`m050: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_0,1'b0,`W_5,1'b0,`W_0};
`m100: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_1,1'b0,`W_0,1'b0,`W_0};
`m150: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_1,1'b0,`W_5,1'b0,`W_0};
`m200: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_2,1'b0,`W_0,1'b0,`W_0};
`m250: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_2,1'b0,`W_5,1'b0,`W_0};
`m300: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_3,1'b0,`W_0,1'b0,`W_0};
`m350: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_3,1'b0,`W_5,1'b0,`W_0};
`m400: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_4,1'b0,`W_0,1'b0,`W_0};
`m450: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_4,1'b0,`W_5,1'b0,`W_0};
`m500: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_5,1'b0,`W_0,1'b0,`W_0};
`m550: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_5,1'b0,`W_5,1'b0,`W_0};
`m600: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_6,1'b0,`W_0,1'b0,`W_0};
`m650: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_6,1'b0,`W_5,1'b0,`W_0};
`m700: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_7,1'b0,`W_0,1'b0,`W_0};
`m750: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_7,1'b0,`W_5,1'b0,`W_0};
`m800: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_8,1'b0,`W_0,1'b0,`W_0};
`m850: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_8,1'b0,`W_5,1'b0,`W_0};
`m900: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_9,1'b0,`W_0,1'b0,`W_0};
`m950: {L_1,L_2,L_3,L_4} <= {1'b0,`W_NULL,1'b1,`W_9,1'b0,`W_5,1'b0,`W_0};
`m1000: {L_1,L_2,L_3,L_4} <= {1'b0,`W_1,1'b1,`W_0,1'b0,`W_0,1'b0,`W_0};
endcase
end
`ZWRACAM:
begin
case (L_1) // WIRUJ¥CE OKRÊGI NA WYWIETLACZU - ZWROT PIENIÊDZY
default: {L_1,L_2,L_3,L_4} <= {1'b0,`W_UM,1'b0,`W_MM,1'b0,`W_UM,1'b0,`W_MM};
`W_UM: {L_1,L_2,L_3,L_4} <= {1'b0,`W_UL,1'b0,`W_UR,1'b0,`W_UL,1'b0,`W_UR};
`W_UL: {L_1,L_2,L_3,L_4} <= {1'b0,`W_MM,1'b0,`W_UM,1'b0,`W_MM,1'b0,`W_UM};
`W_MM: {L_1,L_2,L_3,L_4} <= {1'b0,`W_UR,1'b0,`W_UL,1'b0,`W_UR,1'b0,`W_UL};
endcase
end
`NAPELNIJ_PRZEWODY: // wype³nianie przewodów wod¹
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_MM,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
`PODSTAW_KUBEK: // podtsawienie kubka
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_1,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
`ZMIEL_KAWE: // mielenie kawy
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_2,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
`DODAJ_WODE: // podgrzewanie wody (parzenie kawy)
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_3,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
`SPIENIAJ_MLEKO: // spienianie mleka
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_4,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
`CZYSC_MASZYNE: // usuwanie zu¿ytej kawy, p³ukanie instalacji i usuniêcie z przewodów wody
begin
{L_1,L_2,L_3,L_4} <= {1'b0,`W_MM,1'b0,`W_MM,licznikNaLiczby(count_secs)};
end
endcase
end
always @(negedge clk_div)
begin
if ((cmd_out == `CMD_RESET || cmd_out == `CMD_RESET1 || cmd_out == `CMD_RESET2 || cmd_out == `CMD_RESET3) && cmd_in == `ODP_NIC)
begin
cmd_out <= `CMD_NIC; // zerowanie linii komend po wstêpnym resecie
licz_out <= `LICZNIK_NULL; // zerowanie linii komend licznika po wstepnym resecie
stan_n = `CZEKAM; // zerowanie stanu maszyny
end
if (cmd_out == `CMD_NIC && stan_top != `CZEKAM)
stan_n = `CZEKAM;
stan_top <= stan_n;
end
endmodule |
//alt_oct_power CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" device_family="Stratix IV" parallelterminationcontrol rdn rup seriesterminationcontrol
//VERSION_BEGIN 11.0SP1 cbx_alt_oct_power 2011:07:03:21:10:32:SJ cbx_cycloneii 2011:07:03:21:10:33:SJ cbx_lpm_add_sub 2011:07:03:21:10:33:SJ cbx_lpm_compare 2011:07:03:21:10:33:SJ cbx_lpm_counter 2011:07:03:21:10:33:SJ cbx_lpm_decode 2011:07:03:21:10:33:SJ cbx_mgl 2011:07:03:21:11:41:SJ cbx_stratix 2011:07:03:21:10:33:SJ cbx_stratixii 2011:07:03:21:10:33:SJ cbx_stratixiii 2011:07:03:21:10:33:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = stratixiv_termination 1 stratixiv_termination_logic 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module ddr3_s4_uniphy_p0_oct_control
(
parallelterminationcontrol,
rdn,
rup,
seriesterminationcontrol) /* synthesis synthesis_clearbox=1 */;
output [13:0] parallelterminationcontrol;
input [0:0] rdn;
input [0:0] rup;
output [13:0] seriesterminationcontrol;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [0:0] rdn;
tri0 [0:0] rup;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] wire_sd1a_serializerenableout;
wire [0:0] wire_sd1a_terminationcontrol;
wire [13:0] wire_sd2a_parallelterminationcontrol;
wire [13:0] wire_sd2a_seriesterminationcontrol;
stratixiv_termination sd1a_0
(
.incrdn(),
.incrup(),
.rdn(rdn),
.rup(rup),
.scanout(),
.serializerenableout(wire_sd1a_serializerenableout[0:0]),
.shiftregisterprobe(),
.terminationcontrol(wire_sd1a_terminationcontrol[0:0]),
.terminationcontrolprobe()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.otherserializerenable({9{1'b0}}),
.scanen(1'b0),
.serializerenable(1'b0),
.terminationclear(1'b0),
.terminationclock(1'b0),
.terminationcontrolin(1'b0),
.terminationenable(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
stratixiv_termination_logic sd2a_0
(
.parallelterminationcontrol(wire_sd2a_parallelterminationcontrol[13:0]),
.serialloadenable(wire_sd1a_serializerenableout),
.seriesterminationcontrol(wire_sd2a_seriesterminationcontrol[13:0]),
.terminationdata(wire_sd1a_terminationcontrol)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.parallelloadenable(1'b0),
.terminationclock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
assign
parallelterminationcontrol = wire_sd2a_parallelterminationcontrol,
seriesterminationcontrol = wire_sd2a_seriesterminationcontrol;
endmodule //ddr3_s4_uniphy_p0_oct_control
//VALID FILE
|
/////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2005
//
// Title : Clock switch module for non programmable PLLs
// File : clk_switch.v
// Author : Jim MacLeod
// Created : 05-Mar-2013
// RCS File : $Source:$
// Status : $Id:$
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module takes in up to 6 PLL derived clocks plus a master clock (PCI).
// This module allows the glitchless switching amongst the clock frequencies.
// The purpose of this is to allow an FPGA w/o a programmable PLL
// (ex Cyclone2) to provide us with a variety of frequencies for generating
// Pixel clock and CRT clocks.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module clk_gen_ipll
(
input hb_clk,
input hb_resetn,
input refclk,
input [1:0] bpp,
input vga_mode,
input write_param, // input
input [3:0] counter_type, // input [3:0]
input [2:0] counter_param, // input[2:0]
input [8:0] data_in, // input [8:0],
input reconfig, // input.
input pll_areset_in, // input.
output busy, // Input busy.
output pix_clk,
output pix_clk_vga,
output reg crt_clk,
output pix_locked
);
pix_pll_rc_top u_pix_pll_rc_top
(
.hb_clk (hb_clk),
.hb_rstn (hb_resetn),
.ref_clk (refclk),
.reconfig (reconfig),
.write_param (write_param),
.counter_param (counter_param),// Input [2:0]
.counter_type (counter_type), // Input [3:0]
.data_in (data_in), // Input [8:0]
.pll_areset_in (pll_areset_in),
.busy (busy), // output.
.pix_clk (pix_clk), // output.
.pix_locked (pix_locked) // output.
);
reg [2:0] crt_counter;
reg [1:0] crt_divider;
always @*
begin
casex({vga_mode, bpp})
3'b1_xx: crt_divider = 2'b00;
3'b0_01: crt_divider = 2'b10;
3'b0_10: crt_divider = 2'b01;
default: crt_divider = 2'b00;
endcase
end
always @(posedge pix_clk or negedge hb_resetn)
begin
if(!hb_resetn)
begin
crt_clk <= 1'b1;
crt_counter <= 3'b000;
end
else begin
crt_counter <= crt_counter + 3'h1;
case (crt_divider)
0: crt_clk <= 1'b1;
1: crt_clk <= ~crt_counter[0];
2: crt_clk <= ~|crt_counter[1:0];
3: crt_clk <= ~|crt_counter[2:0];
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_4_V
`define SKY130_FD_SC_LP__OR4_4_V
/**
* or4: 4-input OR.
*
* Verilog wrapper for or4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4_4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4_4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 29.06.2017 01:34:06
// Design Name:
// Module Name: t_ctrlunit
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module t_ctrlunit;
// Inputs
reg [5:0] opcode, funct;
// Outputs
wire memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump;
wire [2:0] alucontrol;
// Initialise the Unit Under Test
ctrlunit uut(
.OPCode( opcode ),
.Funct( funct ),
.MemToReg( memtoreg ),
.MemWrite( memwrite ),
.Branch( branch ),
.ALUSrc( alusrc ),
.RegDst( regdst ),
.RegWrite( regwrite ),
.Jump( jump ),
.ALUControl( alucontrol )
);
initial begin
// Initialise Inputs
opcode = 0;
funct = 0;
// Wait 100 ns for global resets to finish
#100;
// Stimulus here
#10 opcode = 6'h00; funct = 6'h20; // rtype ADD, regdst, regwrite, aluop=11, alucontrol=2(add)
#40;
#10 opcode = 6'h00; funct = 6'h22; // rtype SUB, regdst, regwrite, aluop=11, alucontrol=6(sub)
#40;
#10 opcode = 6'h00; funct = 6'h24; // rtype AND, regdst, regwrite, aluop=11, alucontrol=0(and)
#40;
#10 opcode = 6'h00; funct = 6'h25; // rtype OR, regdst, regwrite, aluop=11, alucontrol=1(or)
#40;
#10 opcode = 6'h00; funct = 6'h2A; // rtype SLT, regdst, regwrite, aluop=11, alucontrol=7(slt)
#40;
#10 opcode = 6'h23; // LW, memtoreg, alusrc, regwrite, aluop=00, alucontrol=2(add)
#40;
#10 opcode = 6'h2B; // SW, memwrite, alusrc, aluop=00, alucontrol=2(add)
#40;
#10 opcode = 6'h04; // BEQ, branch, aluop=01, alucontrol=6(sub)
#40;
#10 opcode = 6'h08; // ADDI, alusrc, regwrite, aluop=00, alucontrol=2(add)
#40;
#10 opcode = 6'h02; // J, jump, aluop=00, alucontrol=2(add)
#40;
end
endmodule
|
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 1
*/
/**
* Testbench for behavioral model for Finite State Machine model of the
* sequential detector
*/
// Import the modules that will be tested for in this testbench
`include "seq_detect.syn.v"
`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"
// IMPORTANT: To run this, try: ncverilog -f seq_detector.f +gui
module tb_seq_detect();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the seq_detector
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire error,match_op;
// Declare "reg" signals: inputs to the DUT
reg inp,clock,reset;
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
/**
* Instantiate an instance of ee577bHw1q5model1() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
seq_detect sqd (
// instance_name(signal name),
// Signal name can be the same as the instance name
inp,clock,reset,error,match_op);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
$sdf_annotate("../sdf/seq_detect.sdf",sqd,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
inp = 1'd0;
reset = 1'd0;
// @ t=10,
#10
inp = 1'd0;
reset = 1'd1;
// @ t=20
#10
inp = 1'd0;
reset = 1'd0;
// @ t=30
#10
inp = 1'd1;
reset = 1'd0;
// @ t=40
#10
inp = 1'd1;
reset = 1'd0;
// @ t=50
#10
inp = 1'dx;
reset = 1'd0;
// @ t=60
#10
inp = 1'd0;
reset = 1'd0;
// @ t=70
#10
inp = 1'dz;
reset = 1'd0;
// @ t=80
#10
inp = 1'd0;
reset = 1'd0;
// @ t=90
#10
inp = 1'd1;
reset = 1'd0;
// @ t=100
#10
inp = 1'd1;
reset = 1'd0;
// @ t=110
#10
inp = 1'd0;
reset = 1'd0;
// @ t=120
#10
inp = 1'd1;
reset = 1'd0;
// @ t=130
#10
// Start of correct sequence
$display($time, " << Start of correct sequence >>");
inp = 1'd1;
reset = 1'd0;
// @ t=140
#10
inp = 1'd0;
reset = 1'd0;
// @ t=150
#10
inp = 1'd0;
reset = 1'd0;
// @ t=160
#10
inp = 1'd1;
reset = 1'd0;
// @ t=170
#10
inp = 1'd1;
reset = 1'd0;
// @ t=180
#10
inp = 1'd0;
reset = 1'd0;
// @ t=190
#10
inp = 1'd1;
reset = 1'd0;
// @ t=200
#10
inp = 1'd1;
reset = 1'd0;
// End of correct sequence
$display($time, " << End of correct sequence >>");
// @ t=210
#10
inp = 1'd1;
reset = 1'd0;
// @ t=220
#10
inp = 1'd1;
reset = 1'd0;
// @ t=230
#10
inp = 1'd0;
reset = 1'd0;
// @ t=240; reset the sequence detector
#10
inp = 1'd1;
reset = 1'd0;
// @ t=250
#10
inp = 1'd0;
reset = 1'd0;
// @ t=260
#10
inp = 1'd1;
reset = 1'd0;
// @ t=270
#10
inp = 1'd1;
reset = 1'd1;
// @ t=280
#10
inp = 1'd0;
reset = 1'd0;
// @ t=290
#10
inp = 1'd1;
reset = 1'd0;
// @ t=300
#10
inp = 1'dx;
reset = 1'd0;
// @ t=310
#10
inp = 1'd1;
reset = 1'd0;
// @ t=320
#10
inp = 1'd0;
reset = 1'd0;
// @ t=330
#10
inp = 1'd1;
reset = 1'd0;
// @ t=340
#10
inp = 1'dx;
reset = 1'd0;
// @ t=350
#10
inp = 1'dx;
reset = 1'd0;
// @ t=360
#10
inp = 1'dz;
reset = 1'd0;
// @ t=370
#10
inp = 1'd0;
reset = 1'd0;
// @ t=380
#10
inp = 1'd1;
reset = 1'd0;
// @ t=390
#10
inp = 1'd0;
reset = 1'd0;
// @ t=400
#10
inp = 1'd1;
reset = 1'd0;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2_SYMBOL_V
`define SKY130_FD_SC_HD__MUX2_SYMBOL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__mux2 (
//# {{data|Data Signals}}
input A0,
input A1,
output X ,
//# {{control|Control Signals}}
input S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTP_SYMBOL_V
`define SKY130_FD_SC_LS__DLXTP_SYMBOL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTP_SYMBOL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: spu_mared.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: state machine to do MA reduction.
*/
////////////////////////////////////////////////////////////////////////
module spu_mared (
/*outputs*/
spu_mared_data_sel_l,
spu_mared_j_ptr_sel,
spu_mared_nm_rd_oprnd_sel,
spu_mared_m_rd_oprnd_sel,
spu_mared_me_rd_oprnd_sel,
spu_mared_x_wr_oprnd_sel,
spu_mared_xe_wr_oprnd_sel,
spu_mared_nr_rd_oprnd_sel,
spu_mared_a_rd_oprnd_sel,
spu_mared_r_wr_oprnd_sel,
spu_mared_update_jptr,
spu_mared_rst_jptr,
spu_mared_maxlen_wen,
spu_mared_rdn_wen,
spu_mared_oprnd2_wen,
spu_mared_memren,
spu_mared_memwen,
spu_mared_cin_set_4sub,
spu_mared_cin_oprnd_sub_mod,
spu_mared_done_set,
spu_mared_start_wen,
spu_mared_start_sel,
spu_mared_red_done,
spu_mared_update_redwr_jptr,
spu_mared_jjptr_wen,
spu_mared_not_idle,
/*inputs*/
mul_data_out_0,
spu_madp_m_eq_n,
spu_madp_m_lt_n,
spu_mactl_expop,
spu_mactl_mulop,
spu_mactl_redop,
spu_mamul_mul_done,
spu_mactl_iss_pulse_dly,
spu_maaddr_jptr_eqz,
spu_maaddr_len_eqmax,
spu_mast_stbuf_wen,
spu_madp_cout_oprnd_sub_mod,
spu_mactl_kill_op,
spu_mactl_stxa_force_abort,
se,
reset,
rclk);
// -------------------------------------------------------------------------
input reset;
input rclk;
input se;
input mul_data_out_0;
input spu_madp_m_eq_n;
input spu_madp_m_lt_n;
input spu_mactl_expop;
input spu_mactl_mulop;
input spu_mactl_redop;
input spu_mamul_mul_done;
input spu_mactl_iss_pulse_dly;
input spu_maaddr_jptr_eqz;
input spu_maaddr_len_eqmax;
input spu_mast_stbuf_wen;
input spu_madp_cout_oprnd_sub_mod;
input spu_mactl_kill_op;
input spu_mactl_stxa_force_abort;
// -------------------------------------------------------------------------
output [3:0] spu_mared_data_sel_l;
output spu_mared_j_ptr_sel;
output spu_mared_nm_rd_oprnd_sel;
output spu_mared_m_rd_oprnd_sel;
output spu_mared_me_rd_oprnd_sel;
output spu_mared_x_wr_oprnd_sel;
output spu_mared_xe_wr_oprnd_sel;
output spu_mared_nr_rd_oprnd_sel;
output spu_mared_a_rd_oprnd_sel;
output spu_mared_r_wr_oprnd_sel;
output spu_mared_update_jptr;
output spu_mared_rst_jptr;
output spu_mared_maxlen_wen;
output spu_mared_rdn_wen;
output spu_mared_oprnd2_wen;
output spu_mared_memren;
output spu_mared_memwen;
output spu_mared_cin_set_4sub;
output spu_mared_cin_oprnd_sub_mod;
output spu_mared_done_set;
output spu_mared_start_wen;
output spu_mared_start_sel;
output spu_mared_red_done;
output spu_mared_update_redwr_jptr;
output spu_mared_jjptr_wen;
output spu_mared_not_idle;
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
wire m_gt_n_rst;
wire spu_mared_red_done;
wire m_gt_n_set,m_lt_n_rst,m_lt_n_set;
wire start_op;
wire tr2idle_frm_wr0tox,tr2idle_frm_wrmtox,tr2idle_frm_wrstox;
wire tr2rdm_frm_wr0tox,tr2rdm_frm_saveptrs,dly_saveptrs_state,
tr2rdm_frm_wrstox,tr2rdm_frm_wrmtox;
wire start_mtox_from_msw;
wire local_stxa_abort;
wire cur_rdm_state;
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
wire state_reset = reset | spu_mared_red_done | spu_mactl_kill_op |
local_stxa_abort;
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// we need a state set to indcate mulred/red is done, and when an
// masync gets issued later, then the load asi is returned.
// ********* ONLY FOR mul_op & red_op NOT exp_op.
wire spu_mared_done_wen = (spu_mared_red_done | spu_mactl_kill_op | local_stxa_abort) &
(spu_mactl_mulop | spu_mactl_redop);
wire spu_mared_done_rst = reset | spu_mactl_iss_pulse_dly;
dffre_s #(1) spu_mared_done_ff (
.din(1'b1) ,
.q(spu_mared_done_set),
.en(spu_mared_done_wen),
.rst(spu_mared_done_rst), .clk (rclk)
, .se(se), .si(), .so());
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
dff_s #(1) idle_state_ff (
.din(nxt_idle_state) ,
.q(cur_idle_state),
.clk (rclk)
, .se(se), .si(), .so());
dffr_s #(1) rdm_state_ff (
.din(nxt_rdm_state) ,
.q(cur_rdm_state),
.rst(state_reset), .clk (rclk)
, .se(se), .si(), .so());
assign local_stxa_abort = cur_rdm_state & spu_mactl_stxa_force_abort;
// the delay is for the loop which is rdm,wrmtox to
//match the cycles for other read/write loops
dffr_s #(1) rdmdly_state_ff (
.din(nxt_rdmdly_state) ,
.q(cur_rdmdly_state),
.rst(state_reset), .clk (rclk)
, .se(se), .si(), .so());
dffr_s #(1) rdn_state_ff (
.din(nxt_rdn_state) ,
.q(cur_rdn_state),
.rst(state_reset), .clk (rclk)
, .se(se), .si(), .so());
dffr_s #(1) cmpsub_state_ff (
.din(nxt_cmpsub_state) ,
.q(cur_cmpsub_state),
.rst(state_reset), .clk (rclk)
, .se(se), .si(), .so());
dffr_s #(1) wr0tox_state_ff (
.din(nxt_wr0tox_state) ,
.q(cur_wr0tox_state),
.rst(state_reset), .clk (rclk)
, .se(se), .si(), .so());
dffr_s #(1) wrmtox_state_ff (
.din(nxt_wrmtox_state) ,
.q(cur_wrmtox_state),
.rst(state_reset), .clk (rclk)
, .se(se), .si(), .so());
// s = m-n
dffr_s #(1) wrstox_state_ff (
.din(nxt_wrstox_state) ,
.q(cur_wrstox_state),
.rst(state_reset), .clk (rclk)
, .se(se), .si(), .so());
dffr_s #(1) saveptrs_state_ff (
.din(nxt_saveptrs_state) ,
.q(cur_saveptrs_state),
.rst(state_reset), .clk (rclk)
, .se(se), .si(), .so());
dffr_s #(1) submn_state_ff (
.din(nxt_submn_state) ,
.q(cur_submn_state),
.rst(state_reset), .clk (rclk)
, .se(se), .si(), .so());
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
wire m_gt_n_q,m_lt_n_q;
wire spu_mared_m_eq_n = spu_madp_m_eq_n & ~(m_lt_n_q | m_gt_n_q);
//assign spu_mared_m_gt_n = ~(spu_madp_m_eq_n | spu_madp_m_lt_n | m_lt_n_q);
wire spu_mared_m_lt_n = ~(spu_madp_m_eq_n | m_gt_n_q) & spu_madp_m_lt_n;
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
wire mamulred_op_rst = state_reset;
wire spu_mamul_mul_done_qual = spu_mamul_mul_done & ~spu_mactl_kill_op;
wire mamulred_op_set = (spu_mactl_mulop | spu_mactl_expop) & spu_mamul_mul_done_qual;
wire mulred_start = mamulred_op_set;
dffre_s #(1) mamulred_op_ff (
.din(1'b1) ,
.q(mamulred_op_q),
.en(mamulred_op_set),
.rst(mamulred_op_rst), .clk (rclk)
, .se(se), .si(), .so());
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
assign m_gt_n_rst = state_reset;
assign m_gt_n_set = ((spu_mactl_mulop | spu_mactl_expop) & mul_data_out_0 & spu_mamul_mul_done_qual) |
(cur_saveptrs_state & ~m_lt_n_q);
dffre_s #(1) m_gt_n_ff (
.din(1'b1) ,
.q(m_gt_n_q),
.en(m_gt_n_set),
.rst(m_gt_n_rst), .clk (rclk)
, .se(se), .si(), .so());
// -------------------------------------------------------------------------
assign m_lt_n_rst = state_reset;
assign m_lt_n_set = cur_cmpsub_state & spu_mared_m_lt_n;
dffre_s #(1) m_lt_n_ff (
.din(1'b1) ,
.q(m_lt_n_q),
.en(m_lt_n_set),
.rst(m_lt_n_rst), .clk (rclk)
, .se(se), .si(), .so());
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// transition to idle state
// this dley is so that m_gt_n_q is updated by the time we start. as
// this is one of the conditions to come out of idle state.
wire mulred_start_q;
dff_s #(1) dly_start_mulred_ff (
.din(mulred_start) ,
.q(mulred_start_q),
.clk (rclk)
, .se(se), .si(), .so());
// delaying mared_start so we can save len ptr to jptr before
// starting.
wire mared_start_p1 = spu_mactl_redop & spu_mactl_iss_pulse_dly;
wire mared_start_p1_q,mared_start_q;
dff_s #(2) dly_start_red_ff (
.din({mared_start_p1,mared_start_p1_q}) ,
.q({mared_start_p1_q,mared_start_q}),
.clk (rclk)
, .se(se), .si(), .so());
assign spu_mared_start_wen = mared_start_p1_q | start_mtox_from_msw | spu_mamul_mul_done_qual;
assign spu_mared_start_sel = mared_start_p1_q | start_mtox_from_msw | spu_mamul_mul_done;
assign start_op = mulred_start_q | mared_start_q;
assign tr2idle_frm_wr0tox = cur_wr0tox_state & spu_maaddr_jptr_eqz;
assign tr2idle_frm_wrmtox = cur_wrmtox_state & spu_maaddr_jptr_eqz;
assign tr2idle_frm_wrstox = cur_wrstox_state & spu_maaddr_len_eqmax;
wire spu_mared_red_done_pre = tr2idle_frm_wr0tox | tr2idle_frm_wrmtox |
tr2idle_frm_wrstox;
dffr_s #(2) spu_mared_red_done_ff (
.din({spu_mared_red_done_pre,spu_mared_red_done_dly1}) ,
.q({spu_mared_red_done_dly1,spu_mared_red_done_dly2}),
.rst(state_reset), .clk (rclk)
, .se(se), .si(), .so());
assign spu_mared_red_done = spu_mared_red_done_dly2 | local_stxa_abort;
// --------------------------
assign spu_mared_not_idle = ~cur_idle_state;
assign nxt_idle_state = (
state_reset | spu_mared_red_done |
(cur_idle_state & ~start_op));
// -------------------------------------------------------------------------
// transition to rdm state
wire twodly_saveptrs_state;
assign tr2rdm_frm_wr0tox = cur_wr0tox_state & ~spu_maaddr_jptr_eqz;
assign tr2rdm_frm_saveptrs = twodly_saveptrs_state & ~cur_idle_state;
assign tr2rdm_frm_wrstox = cur_wrstox_state & ~spu_maaddr_len_eqmax;
assign tr2rdm_frm_wrmtox = cur_wrmtox_state & m_lt_n_q & ~spu_maaddr_jptr_eqz;
assign nxt_rdm_state = (
tr2rdm_frm_wrmtox |
tr2rdm_frm_wr0tox | tr2rdm_frm_saveptrs |
tr2rdm_frm_wrstox |
(cur_idle_state & start_op & ~(m_lt_n_q|m_gt_n_q)));
//(cur_idle_state & start_op & ~m_lt_n_q));
// this goes to spu_mamul to get ored with the logic there before
// sending to spu_madp.
assign spu_mared_oprnd2_wen = cur_rdm_state;
// -------------------------------------------------------------------------
// transition to rdmdly state
assign nxt_rdmdly_state = (
(cur_rdm_state & m_lt_n_q) );
// -------------------------------------------------------------------------
// transition to rdn state
assign nxt_rdn_state = (
(cur_rdm_state & ~m_lt_n_q));
// the following is for capturing the N data into flop
// used for subtract & compare.
assign spu_mared_rdn_wen = cur_rdn_state | spu_mast_stbuf_wen;
// -------------------------------------------------------------------------
// transition to cmpsub state
assign nxt_cmpsub_state = (
(cur_rdn_state & ~(m_lt_n_q | m_gt_n_q)));
// -------------------------------------------------------------------------
// transition to wr0tox state
assign nxt_wr0tox_state = (
(cur_cmpsub_state & spu_mared_m_eq_n));
// -------------------------------------------------------------------------
// transition to wrmtox state
assign nxt_wrmtox_state = (
(cur_rdmdly_state) );
// -------------------------------------------------------------------------
// transition to wrstox state
assign nxt_wrstox_state = (
(cur_submn_state));
// -------------------------------------------------------------------------
// transition to saveptrs state
assign nxt_saveptrs_state = (
(cur_idle_state & start_op & m_gt_n_q) |
(cur_cmpsub_state & ~spu_mared_m_eq_n));
/*
(cur_cmpsub_state & spu_mared_m_gt_n) |
(cur_cmpsub_state & spu_mared_m_lt_n));
*/
dffr_s #(1) dly_saveptrs_ff (
.din(cur_saveptrs_state) ,
.q(dly_saveptrs_state),
.clk (rclk),
.rst(state_reset), .se(se), .si(), .so());
// the delay is needed so we can save the pointer before
// reseting it.
assign spu_mared_maxlen_wen = cur_saveptrs_state & ~m_lt_n_q;
assign spu_mared_rst_jptr = dly_saveptrs_state & ~m_lt_n_q;
assign start_mtox_from_msw = cur_saveptrs_state & m_lt_n_q;
// need to delay this an extra cycle to trigger nxt_rdm_state, so
// the len_eqmax has correct value by then.
dffr_s #(1) twodly_saveptrs_ff (
.din(dly_saveptrs_state) ,
.q(twodly_saveptrs_state),
.clk (rclk),
.rst(state_reset), .se(se), .si(), .so());
// -------------------------------------------------------------------------
// transition to submn state
assign nxt_submn_state = (
(cur_rdn_state & m_gt_n_q));
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
/*
assign spu_mared_incr_jptr = nxt_wr0tox_state | nxt_wrmtox_state |
nxt_wstox_state;
*/
// the follwoing is to mux the updated jjptr from a temp
// flop for the transition to rdm state and then the mux selects
// the jptr updated value for rdn and wr.
assign spu_mared_update_jptr = tr2rdm_frm_wr0tox | tr2rdm_frm_wrmtox |
tr2rdm_frm_wrstox;
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// added spu_mactl_stxa_force_abort to the following since ren causes perr_set with x's.
assign spu_mared_memren = (nxt_rdm_state | nxt_rdn_state) & ~spu_mactl_stxa_force_abort;
// ---------------------
assign spu_mared_jjptr_wen = nxt_wr0tox_state | nxt_wrmtox_state |
nxt_wrstox_state;
dff_s #(3) nxt_wr0tox_state_ff(
.din({nxt_wr0tox_state,nxt_wr0tox_state_dly1,nxt_wr0tox_state_dly2}) ,
.q({nxt_wr0tox_state_dly1,nxt_wr0tox_state_dly2,nxt_wr0tox_state_dly3}),
.clk (rclk)
, .se(se), .si(), .so());
dff_s #(3) nxt_wrstox_state_ff(
.din({nxt_wrstox_state,nxt_wrstox_state_dly1,nxt_wrstox_state_dly2}) ,
.q({nxt_wrstox_state_dly1,nxt_wrstox_state_dly2,nxt_wrstox_state_dly3}),
.clk (rclk)
, .se(se), .si(), .so());
dff_s #(2) nxt_wrmtox_state_ff(
.din({nxt_wrmtox_state,nxt_wrmtox_state_dly1}) ,
.q({nxt_wrmtox_state_dly1,nxt_wrmtox_state_dly2}),
.clk (rclk)
, .se(se), .si(), .so());
assign spu_mared_memwen = nxt_wr0tox_state_dly3 | nxt_wrmtox_state_dly2 |
nxt_wrstox_state_dly3;
// -----------------------
dff_s #(2) spu_mared_start_wen_ff(
.din({spu_mared_start_wen,spu_mared_start_wen_dly}) ,
.q({spu_mared_start_wen_dly,spu_mared_start_wen_dly2}),
.clk (rclk)
, .se(se), .si(), .so());
dff_s #(2) spu_mared_rst_jptr_ff(
.din({spu_mared_rst_jptr,spu_mared_rst_jptr_dly}) ,
.q({spu_mared_rst_jptr_dly,spu_mared_rst_jptr_dly2}),
.clk (rclk)
, .se(se), .si(), .so());
dff_s #(1) spu_mared_memwen_ff (
.din(spu_mared_memwen) ,
.q(spu_mared_memwen_dly),
.clk (rclk)
, .se(se), .si(), .so());
assign spu_mared_update_redwr_jptr = spu_mared_rst_jptr_dly2 | spu_mared_start_wen_dly2 |
spu_mared_memwen_dly;
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
/*
assign spu_mared_m_rd_oprnd_sel = nxt_rdm_state & (mamulred_op_q | mamulred_op_set);
assign spu_mared_nm_rd_oprnd_sel = nxt_rdn_state & (mamulred_op_q | mamulred_op_set);
assign spu_mared_x_wr_oprnd_sel = spu_mared_memwen & mamulred_op_q;
*/
assign spu_mared_m_rd_oprnd_sel = nxt_rdm_state & spu_mactl_mulop;
assign spu_mared_nm_rd_oprnd_sel = nxt_rdn_state & (spu_mactl_mulop | spu_mactl_expop);
assign spu_mared_x_wr_oprnd_sel = spu_mared_memwen & spu_mactl_mulop;
assign spu_mared_me_rd_oprnd_sel = nxt_rdm_state & spu_mactl_expop;
assign spu_mared_xe_wr_oprnd_sel = spu_mared_memwen & spu_mactl_expop;
assign spu_mared_a_rd_oprnd_sel = nxt_rdm_state & spu_mactl_redop;
assign spu_mared_nr_rd_oprnd_sel = nxt_rdn_state & spu_mactl_redop;
assign spu_mared_r_wr_oprnd_sel = spu_mared_memwen & spu_mactl_redop;
//assign spu_mared_j_ptr_sel = spu_mared_memren | spu_mared_memwen;
assign spu_mared_j_ptr_sel = spu_mared_memren ;
// -------------------------------------------------------------------------
// the following selects go to spu_madp.
wire [3:0] spu_mared_data_sel;
assign spu_mared_data_sel[0] = ~(mamulred_op_q | spu_mactl_redop);
//assign spu_mared_data_sel[1] = (mamulred_op_q | spu_mactl_redop) & spu_mared_m_eq_n;
assign spu_mared_data_sel[1] = (mamulred_op_q | spu_mactl_redop) & ~m_lt_n_q & ~m_gt_n_q;
assign spu_mared_data_sel[2] = (mamulred_op_q | spu_mactl_redop) & m_lt_n_q & ~m_gt_n_q;
assign spu_mared_data_sel[3] = (mamulred_op_q | spu_mactl_redop) & m_gt_n_q;
assign spu_mared_data_sel_l[3:0] = ~spu_mared_data_sel[3:0];
// -------------------------------------------------------------------------
assign spu_mared_cin_set_4sub = spu_mared_data_sel[2] | spu_mared_data_sel[1];
// -------------------------------------------------------------------------
// except for the first word subtract(starting at jptr=0), use borrow from the
// previous stage as cin for the next stage.
wire sel_cout_frm_prev_stage = (~spu_maaddr_jptr_eqz & m_gt_n_q) & ~start_op;
wire spu_mared_cin_oprnd_sub_mod_pre;
mux3ds #(1) cin_sel_mux (
.in0 (1'b0),
.in1 (1'b1),
.in2 (spu_madp_cout_oprnd_sub_mod),
.sel0 (1'b0),
.sel1 (~sel_cout_frm_prev_stage),
.sel2 (sel_cout_frm_prev_stage),
.dout (spu_mared_cin_oprnd_sub_mod_pre)
);
wire dly_cur_wrstox_state;
wire cin_cout_wen = start_op | dly_cur_wrstox_state;
wire spu_mared_cin_oprnd_sub_mod_q;
dffre_s #(1) cin_cout_ff (
.din(spu_mared_cin_oprnd_sub_mod_pre) ,
.q(spu_mared_cin_oprnd_sub_mod_q),
.en(cin_cout_wen),
.rst(reset),
.clk (rclk)
, .se(se), .si(), .so());
// for ld and store ops force cin to zero, since the adder is used for MPA calculations.
wire force_cin_to_zero = spu_mactl_expop | spu_mactl_mulop | spu_mactl_redop;
wire force_cin_to_zero_q;
dff_s #(1) force_cin_to_zero_ff (
.din(force_cin_to_zero) ,
.q(force_cin_to_zero_q),
.clk (rclk)
, .se(se), .si(), .so());
assign spu_mared_cin_oprnd_sub_mod = spu_mared_cin_oprnd_sub_mod_q & force_cin_to_zero_q;
// -------------------------
// delaying cur_wrstox_state to write the cout to cin reg. this delay
// is for when the j-ptr comes out of being zero is when we need to capture
// the next cout to cin.
dff_s #(1) dly_cur_wrstox_state_ff (
.din(cur_wrstox_state) ,
.q(dly_cur_wrstox_state),
.clk (rclk)
, .se(se), .si(), .so());
endmodule
|
// dtb_daq.v
`timescale 1 ns / 1 ps
module dtb_daq
(
input clk_daq,
input clk_sys,
input [7:0]sclk,
input reset,
input sync,
// control
input [1:0]ctrl_adc_address,
input ctrl_adc_write,
input [15:0]ctrl_adc_writedata,
input ctrl_adc_read,
output [15:0]ctrl_adc_readdata,
input [3:0]ctrl_deser160,
// pattern generator
input [5:0]pg,
input i2c_trigger,
input tin,
input tout,
// adc input port
input [11:0]adc_data,
input adc_or,
// data channel 1
input sdata1,
// data simulator
input evsim_enable,
input evsim_write,
input [15:0]evsim_data,
// data output channel 1
output reg daq0_write,
output reg [15:0]daq0_writedata,
input daq0_running,
output [5:0]TP
);
// pattern generator signals
wire pg_trigger; // trigger signal for probe
wire pg_rest; // TBM reset
wire pg_res; // ROC reset
wire pg_cal; // calibrate
wire pg_trg; // trigger
wire pg_tok; // token in
assign {pg_trigger, pg_rest, pg_res, pg_cal, pg_trg, pg_tok} = pg;
wire write_ana;
wire [15:0]data_ana;
wire write_roc;
wire [15:0]data_roc;
adc_readout adc_in
(
.clk(clk_daq),
.sync(sync),
.reset(reset),
.avs_ctrl_address(ctrl_adc_address),
.avs_ctrl_write(ctrl_adc_write),
.avs_ctrl_writedata(ctrl_adc_writedata),
.avs_ctrl_read(ctrl_adc_read),
.avs_ctrl_readdata(ctrl_adc_readdata),
.run(daq0_running),
.trig1(pg_trigger),
.trig2(i2c_trigger),
.tin(tin),
.tout(tout),
.adc_data(adc_data),
.adc_or(adc_or),
.write(write_ana),
.writedata(data_ana),
.TP(TP)
);
deser160 channel1_roc
(
.clk(clk_daq),
.sync(sync),
.reset(reset),
.sclk0(sclk[0]),
.sclk180(sclk[4]),
.ctrl(ctrl_deser160),
.sdata(sdata1),
.tin(tin),
.tout(tout),
.run(daq0_running),
.write(write_roc),
.data(data_roc)
);
always @(*)
begin
if (evsim_enable)
begin
daq0_write <= evsim_write;
daq0_writedata <= evsim_data;
end
else if (write_ana)
begin
daq0_write <= write_ana;
daq0_writedata <= data_ana;
end
else
begin
daq0_write <= write_roc;
daq0_writedata <= data_roc;
end
end
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\PWM.v
// Created: 2014-09-08 14:12:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: PWM
// Source Path: controllerPeripheralHdlAdi/PWM
// Hierarchy Level: 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module PWM
(
CLK_IN,
reset,
enb,
c_0,
c_1,
c_2,
pwm_0,
pwm_1,
pwm_2
);
input CLK_IN;
input reset;
input enb;
input [15:0] c_0; // uint16
input [15:0] c_1; // uint16
input [15:0] c_2; // uint16
output pwm_0; // boolean
output pwm_1; // boolean
output pwm_2; // boolean
wire [15:0] Timer_Period_Clock_Cycles_out1; // uint16
wire [15:0] Chart_out1; // uint16
wire [15:0] c [0:2]; // uint16 [3]
wire [15:0] Add_out1 [0:2]; // uint16 [3]
wire [15:0] Add_out1_0; // uint16
wire Relational_Operator_relop1;
wire [15:0] Add_out1_1; // uint16
wire Relational_Operator_relop2;
wire [15:0] Add_out1_2; // uint16
wire Relational_Operator_relop3;
wire [0:2] Relational_Operator_out1; // boolean [3]
wire Relational_Operator_out1_0;
wire [0:2] Compare_To_Zero_out1; // boolean [3]
wire Compare_To_Zero_out1_0;
wire Relational_Operator_out1_0_1;
wire Relational_Operator_out1_1;
wire Compare_To_Zero_out1_1;
wire Relational_Operator_out1_1_1;
wire Relational_Operator_out1_2;
wire Compare_To_Zero_out1_2;
wire Relational_Operator_out1_2_1;
// <S2>/Timer Period Clock Cycles
assign Timer_Period_Clock_Cycles_out1 = 16'd1000;
// <S2>/Chart
Chart u_Chart (.CLK_IN(CLK_IN),
.reset(reset),
.enb(enb),
.CounterMax(Timer_Period_Clock_Cycles_out1), // uint16
.count(Chart_out1) // uint16
);
assign c[0] = c_0;
assign c[1] = c_1;
assign c[2] = c_2;
// <S2>/Add
assign Add_out1[0] = Timer_Period_Clock_Cycles_out1 - c[0];
assign Add_out1[1] = Timer_Period_Clock_Cycles_out1 - c[1];
assign Add_out1[2] = Timer_Period_Clock_Cycles_out1 - c[2];
assign Add_out1_0 = Add_out1[0];
assign Relational_Operator_relop1 = (Chart_out1 >= Add_out1_0 ? 1'b1 :
1'b0);
assign Add_out1_1 = Add_out1[1];
assign Relational_Operator_relop2 = (Chart_out1 >= Add_out1_1 ? 1'b1 :
1'b0);
assign Add_out1_2 = Add_out1[2];
// <S2>/Relational Operator
assign Relational_Operator_relop3 = (Chart_out1 >= Add_out1_2 ? 1'b1 :
1'b0);
assign Relational_Operator_out1[0] = Relational_Operator_relop1;
assign Relational_Operator_out1[1] = Relational_Operator_relop2;
assign Relational_Operator_out1[2] = Relational_Operator_relop3;
assign Relational_Operator_out1_0 = Relational_Operator_out1[0];
// <S2>/Compare To Zero
assign Compare_To_Zero_out1[0] = (c[0] != 16'b0000000000000000 ? 1'b1 :
1'b0);
assign Compare_To_Zero_out1[1] = (c[1] != 16'b0000000000000000 ? 1'b1 :
1'b0);
assign Compare_To_Zero_out1[2] = (c[2] != 16'b0000000000000000 ? 1'b1 :
1'b0);
assign Compare_To_Zero_out1_0 = Compare_To_Zero_out1[0];
assign Relational_Operator_out1_0_1 = Relational_Operator_out1_0 & Compare_To_Zero_out1_0;
assign pwm_0 = Relational_Operator_out1_0_1;
assign Relational_Operator_out1_1 = Relational_Operator_out1[1];
assign Compare_To_Zero_out1_1 = Compare_To_Zero_out1[1];
assign Relational_Operator_out1_1_1 = Relational_Operator_out1_1 & Compare_To_Zero_out1_1;
assign pwm_1 = Relational_Operator_out1_1_1;
assign Relational_Operator_out1_2 = Relational_Operator_out1[2];
assign Compare_To_Zero_out1_2 = Compare_To_Zero_out1[2];
// <S2>/Logical Operator
assign Relational_Operator_out1_2_1 = Relational_Operator_out1_2 & Compare_To_Zero_out1_2;
assign pwm_2 = Relational_Operator_out1_2_1;
endmodule // PWM
|
//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
//Date : Sun Sep 22 02:31:57 2019
//Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
//Command : generate_target zybo_zynq_design_wrapper.bd
//Design : zybo_zynq_design_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module zybo_zynq_design_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
zybo_zynq_design zybo_zynq_design_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_PWRGOOD_PP_PG_BLACKBOX_V
`define SKY130_FD_SC_MS__UDP_PWRGOOD_PP_PG_BLACKBOX_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_pwrgood_pp$PG (
UDP_OUT,
UDP_IN ,
VPWR ,
VGND
);
output UDP_OUT;
input UDP_IN ;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_PWRGOOD_PP_PG_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2_2_V
`define SKY130_FD_SC_LS__NAND2_2_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2_2_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: Translation_Module_DM.v
// /___/ /\ Timestamp: Fri Jul 17 11:59:08 2015
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog C:/Users/RobertHenning/Mojo_FFT_TwoDigiMics_BasicCORDIC/ipcore_dir/tmp/_cg/Translation_Module_DM.ngc C:/Users/RobertHenning/Mojo_FFT_TwoDigiMics_BasicCORDIC/ipcore_dir/tmp/_cg/Translation_Module_DM.v
// Device : 6slx9tqg144-2
// Input file : C:/Users/RobertHenning/Mojo_FFT_TwoDigiMics_BasicCORDIC/ipcore_dir/tmp/_cg/Translation_Module_DM.ngc
// Output file : C:/Users/RobertHenning/Mojo_FFT_TwoDigiMics_BasicCORDIC/ipcore_dir/tmp/_cg/Translation_Module_DM.v
// # of Modules : 1
// Design Name : Translation_Module_DM
// Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module Translation_Module_DM (
nd, clk, rdy, rfd, x_in, y_in, x_out, phase_out
)/* synthesis syn_black_box syn_noprune=1 */;
input nd;
input clk;
output rdy;
output rfd;
input [9 : 0] x_in;
input [9 : 0] y_in;
output [9 : 0] x_out;
output [9 : 0] phase_out;
// synthesis translate_off
wire \U0/i_synth/gen_cordic.output_stage/gen_rdy/gen_rtl.gen_reg.d_reg ;
wire NlwRenamedSig_OI_rfd;
wire sig00000001;
wire sig00000002;
wire sig00000003;
wire sig00000004;
wire sig00000005;
wire sig00000006;
wire sig00000007;
wire sig00000008;
wire sig00000009;
wire sig0000000a;
wire sig0000000b;
wire sig0000000c;
wire sig0000000d;
wire sig0000000e;
wire sig0000000f;
wire sig00000010;
wire sig00000011;
wire sig00000012;
wire sig00000013;
wire sig00000014;
wire sig00000015;
wire sig00000016;
wire sig00000017;
wire sig00000018;
wire sig00000019;
wire sig0000001a;
wire sig0000001b;
wire sig0000001c;
wire sig0000001d;
wire sig0000001e;
wire sig0000001f;
wire sig00000020;
wire sig00000021;
wire sig00000022;
wire sig00000023;
wire sig00000024;
wire sig00000025;
wire sig00000026;
wire sig00000027;
wire sig00000028;
wire sig00000029;
wire sig0000002a;
wire sig0000002b;
wire sig0000002c;
wire sig0000002d;
wire sig0000002e;
wire sig0000002f;
wire sig00000030;
wire sig00000031;
wire sig00000032;
wire sig00000033;
wire sig00000034;
wire sig00000035;
wire sig00000036;
wire sig00000037;
wire sig00000038;
wire sig00000039;
wire sig0000003a;
wire sig0000003b;
wire sig0000003c;
wire sig0000003d;
wire sig0000003e;
wire sig0000003f;
wire sig00000040;
wire sig00000041;
wire sig00000042;
wire sig00000043;
wire sig00000044;
wire sig00000045;
wire sig00000046;
wire sig00000047;
wire sig00000048;
wire sig00000049;
wire sig0000004a;
wire sig0000004b;
wire sig0000004c;
wire sig0000004d;
wire sig0000004e;
wire sig0000004f;
wire sig00000050;
wire sig00000051;
wire sig00000052;
wire sig00000053;
wire sig00000054;
wire sig00000055;
wire sig00000056;
wire sig00000057;
wire sig00000058;
wire sig00000059;
wire sig0000005a;
wire sig0000005b;
wire sig0000005c;
wire sig0000005d;
wire sig0000005e;
wire sig0000005f;
wire sig00000060;
wire sig00000061;
wire sig00000062;
wire sig00000063;
wire sig00000064;
wire sig00000065;
wire sig00000066;
wire sig00000067;
wire sig00000068;
wire sig00000069;
wire sig0000006a;
wire sig0000006b;
wire sig0000006c;
wire sig0000006d;
wire sig0000006e;
wire sig0000006f;
wire sig00000070;
wire sig00000071;
wire sig00000072;
wire sig00000073;
wire sig00000074;
wire sig00000075;
wire sig00000076;
wire sig00000077;
wire sig00000078;
wire sig00000079;
wire sig0000007a;
wire sig0000007b;
wire sig0000007c;
wire sig0000007d;
wire sig0000007e;
wire sig0000007f;
wire sig00000080;
wire sig00000081;
wire sig00000082;
wire sig00000083;
wire sig00000084;
wire sig00000085;
wire sig00000086;
wire sig00000087;
wire sig00000088;
wire sig00000089;
wire sig0000008a;
wire sig0000008b;
wire sig0000008c;
wire sig0000008d;
wire sig0000008e;
wire sig0000008f;
wire sig00000090;
wire sig00000091;
wire sig00000092;
wire sig00000093;
wire sig00000094;
wire sig00000095;
wire sig00000096;
wire sig00000097;
wire sig00000098;
wire sig00000099;
wire sig0000009a;
wire sig0000009b;
wire sig0000009c;
wire sig0000009d;
wire sig0000009e;
wire sig0000009f;
wire sig000000a0;
wire sig000000a1;
wire sig000000a2;
wire sig000000a3;
wire sig000000a4;
wire sig000000a5;
wire sig000000a6;
wire sig000000a7;
wire sig000000a8;
wire sig000000a9;
wire sig000000aa;
wire sig000000ab;
wire sig000000ac;
wire sig000000ad;
wire sig000000ae;
wire sig000000af;
wire sig000000b0;
wire sig000000b1;
wire sig000000b2;
wire sig000000b3;
wire sig000000b4;
wire sig000000b5;
wire sig000000b6;
wire sig000000b7;
wire sig000000b8;
wire sig000000b9;
wire sig000000ba;
wire sig000000bb;
wire sig000000bc;
wire sig000000bd;
wire sig000000be;
wire sig000000bf;
wire sig000000c0;
wire sig000000c1;
wire sig000000c2;
wire sig000000c3;
wire sig000000c4;
wire sig000000c5;
wire sig000000c6;
wire sig000000c7;
wire sig000000c8;
wire sig000000c9;
wire sig000000ca;
wire sig000000cb;
wire sig000000cc;
wire sig000000cd;
wire sig000000ce;
wire sig000000cf;
wire sig000000d0;
wire sig000000d1;
wire sig000000d2;
wire sig000000d3;
wire sig000000d4;
wire sig000000d5;
wire sig000000d6;
wire sig000000d7;
wire sig000000d8;
wire sig000000d9;
wire sig000000da;
wire sig000000db;
wire sig000000dc;
wire sig000000dd;
wire sig000000de;
wire sig000000df;
wire sig000000e0;
wire sig000000e1;
wire sig000000e2;
wire sig000000e3;
wire sig000000e4;
wire sig000000e5;
wire sig000000e6;
wire sig000000e7;
wire sig000000e8;
wire sig000000e9;
wire sig000000ea;
wire sig000000eb;
wire sig000000ec;
wire sig000000ed;
wire sig000000ee;
wire sig000000ef;
wire sig000000f0;
wire sig000000f1;
wire sig000000f2;
wire sig000000f3;
wire sig000000f4;
wire sig000000f5;
wire sig000000f6;
wire sig000000f7;
wire sig000000f8;
wire sig000000f9;
wire sig000000fa;
wire sig000000fb;
wire sig000000fc;
wire sig000000fd;
wire sig000000fe;
wire sig000000ff;
wire sig00000100;
wire sig00000101;
wire sig00000102;
wire sig00000103;
wire sig00000104;
wire sig00000105;
wire sig00000106;
wire sig00000107;
wire sig00000108;
wire sig00000109;
wire sig0000010a;
wire sig0000010b;
wire sig0000010c;
wire sig0000010d;
wire sig0000010e;
wire sig0000010f;
wire sig00000110;
wire sig00000111;
wire sig00000112;
wire sig00000113;
wire sig00000114;
wire sig00000115;
wire sig00000116;
wire sig00000117;
wire sig00000118;
wire sig00000119;
wire sig0000011a;
wire sig0000011b;
wire sig0000011c;
wire sig0000011d;
wire sig0000011e;
wire sig0000011f;
wire sig00000120;
wire sig00000121;
wire sig00000122;
wire sig00000123;
wire sig00000124;
wire sig00000125;
wire sig00000126;
wire sig00000127;
wire sig00000128;
wire sig00000129;
wire sig0000012a;
wire sig0000012b;
wire sig0000012c;
wire sig0000012d;
wire sig0000012e;
wire sig0000012f;
wire sig00000130;
wire sig00000131;
wire sig00000132;
wire sig00000133;
wire sig00000134;
wire sig00000135;
wire sig00000136;
wire sig00000137;
wire sig00000138;
wire sig00000139;
wire sig0000013a;
wire sig0000013b;
wire sig0000013c;
wire sig0000013d;
wire sig0000013e;
wire sig0000013f;
wire sig00000140;
wire sig00000141;
wire sig0000014c;
wire sig0000014d;
wire sig0000014e;
wire sig0000014f;
wire sig00000150;
wire sig00000151;
wire sig00000152;
wire sig00000153;
wire sig00000154;
wire sig00000155;
wire sig00000156;
wire sig00000157;
wire sig00000158;
wire sig00000159;
wire sig0000015a;
wire sig0000015b;
wire sig0000015c;
wire sig0000015d;
wire sig0000015e;
wire sig0000015f;
wire sig00000160;
wire sig00000161;
wire sig00000162;
wire sig00000163;
wire sig00000164;
wire sig00000165;
wire sig00000166;
wire sig00000167;
wire sig00000168;
wire sig00000169;
wire sig0000016a;
wire sig0000016b;
wire sig0000016c;
wire sig0000016d;
wire sig0000016e;
wire sig0000016f;
wire sig00000170;
wire sig00000171;
wire sig00000172;
wire sig00000173;
wire sig00000174;
wire sig00000175;
wire sig00000176;
wire sig00000177;
wire sig00000178;
wire sig00000179;
wire sig0000017a;
wire sig0000017b;
wire sig0000017c;
wire sig0000017d;
wire sig0000017e;
wire sig0000017f;
wire sig00000180;
wire sig00000181;
wire sig00000182;
wire sig00000183;
wire sig00000184;
wire sig00000185;
wire sig00000186;
wire sig00000187;
wire sig00000188;
wire sig00000189;
wire sig0000018a;
wire sig0000018b;
wire sig0000018c;
wire sig0000018d;
wire sig0000018e;
wire sig0000018f;
wire sig00000190;
wire sig00000191;
wire sig00000192;
wire sig00000193;
wire sig00000194;
wire sig00000195;
wire sig00000196;
wire sig00000197;
wire sig00000198;
wire sig00000199;
wire sig0000019a;
wire sig0000019b;
wire sig0000019c;
wire sig0000019d;
wire sig0000019e;
wire sig0000019f;
wire sig000001a0;
wire sig000001a1;
wire sig000001a2;
wire sig000001a3;
wire sig000001a4;
wire sig000001a5;
wire sig000001a6;
wire sig000001a7;
wire sig000001a8;
wire sig000001a9;
wire sig000001aa;
wire sig000001ab;
wire sig000001ac;
wire sig000001ad;
wire sig000001ae;
wire sig000001af;
wire sig000001b0;
wire sig000001b1;
wire sig000001b2;
wire sig000001b3;
wire sig000001b4;
wire sig000001b5;
wire sig000001b6;
wire sig000001b7;
wire sig000001b8;
wire sig000001b9;
wire sig000001ba;
wire sig000001bb;
wire sig000001bc;
wire sig000001bd;
wire sig000001be;
wire sig000001bf;
wire sig000001c0;
wire sig000001c1;
wire sig000001c2;
wire sig000001c3;
wire sig000001c4;
wire sig000001c5;
wire sig000001c6;
wire sig000001c7;
wire sig000001c8;
wire sig000001c9;
wire sig000001ca;
wire sig000001cb;
wire sig000001cc;
wire sig000001cd;
wire sig000001ce;
wire sig000001cf;
wire sig000001d0;
wire sig000001d1;
wire sig000001d2;
wire sig000001d3;
wire sig000001d4;
wire sig000001d5;
wire sig000001d6;
wire sig000001d7;
wire sig000001d8;
wire sig000001d9;
wire sig000001da;
wire sig000001db;
wire sig000001dc;
wire sig000001dd;
wire sig000001de;
wire sig000001df;
wire sig000001e0;
wire sig000001e1;
wire sig000001e2;
wire sig000001e3;
wire sig000001e4;
wire sig000001e5;
wire sig000001e6;
wire sig000001e7;
wire sig000001e8;
wire sig000001e9;
wire sig000001ea;
wire sig000001eb;
wire sig000001ec;
wire sig000001ed;
wire sig000001ee;
wire sig000001ef;
wire sig000001f0;
wire sig000001f1;
wire sig000001f2;
wire sig000001f3;
wire sig000001f4;
wire sig000001f5;
wire sig000001f6;
wire sig000001f7;
wire sig000001f8;
wire sig000001f9;
wire sig000001fa;
wire sig000001fb;
wire sig000001fc;
wire sig000001fd;
wire sig000001fe;
wire sig000001ff;
wire sig00000200;
wire sig00000201;
wire sig00000202;
wire sig00000203;
wire sig00000204;
wire sig00000205;
wire sig00000206;
wire \blk0000001a/sig0000023d ;
wire \blk0000001a/sig0000023c ;
wire \blk0000001a/sig0000023b ;
wire \blk0000001a/sig0000023a ;
wire \blk0000001a/sig00000239 ;
wire \blk0000001a/sig00000238 ;
wire \blk0000001a/sig00000237 ;
wire \blk0000001a/sig00000236 ;
wire \blk0000001a/sig00000235 ;
wire \blk0000001a/sig00000234 ;
wire \blk0000001a/sig00000233 ;
wire \blk0000001a/sig00000232 ;
wire \blk0000001a/sig00000231 ;
wire \blk0000001a/sig00000230 ;
wire \blk0000001a/sig0000022f ;
wire \blk0000001a/sig0000022e ;
wire \blk0000001a/sig0000022d ;
wire \blk0000001a/sig0000022c ;
wire \blk0000001a/sig0000022b ;
wire \blk0000001a/sig0000022a ;
wire \blk0000001a/sig00000229 ;
wire \blk0000001a/sig00000228 ;
wire \blk0000001a/sig00000227 ;
wire \blk0000001a/sig00000226 ;
wire \blk0000001a/sig00000225 ;
wire \blk0000001a/sig00000224 ;
wire \blk0000001a/sig00000223 ;
wire \blk0000001a/sig00000222 ;
wire \blk00000046/sig00000274 ;
wire \blk00000046/sig00000273 ;
wire \blk00000046/sig00000272 ;
wire \blk00000046/sig00000271 ;
wire \blk00000046/sig00000270 ;
wire \blk00000046/sig0000026f ;
wire \blk00000046/sig0000026e ;
wire \blk00000046/sig0000026d ;
wire \blk00000046/sig0000026c ;
wire \blk00000046/sig0000026b ;
wire \blk00000046/sig0000026a ;
wire \blk00000046/sig00000269 ;
wire \blk00000046/sig00000268 ;
wire \blk00000046/sig00000267 ;
wire \blk00000046/sig00000266 ;
wire \blk00000046/sig00000265 ;
wire \blk00000046/sig00000264 ;
wire \blk00000046/sig00000263 ;
wire \blk00000046/sig00000262 ;
wire \blk00000046/sig00000261 ;
wire \blk00000046/sig00000260 ;
wire \blk00000046/sig0000025f ;
wire \blk00000046/sig0000025e ;
wire \blk00000046/sig0000025d ;
wire \blk00000046/sig0000025c ;
wire \blk00000046/sig0000025b ;
wire \blk00000046/sig0000025a ;
wire \blk00000046/sig00000259 ;
wire \blk00000086/sig000002c1 ;
wire \blk00000086/sig000002c0 ;
wire \blk00000086/sig000002bf ;
wire \blk00000086/sig000002be ;
wire \blk00000086/sig000002bd ;
wire \blk00000086/sig000002bc ;
wire \blk00000086/sig000002bb ;
wire \blk00000086/sig000002ba ;
wire \blk00000086/sig000002b9 ;
wire \blk00000086/sig000002b8 ;
wire \blk00000086/sig000002b7 ;
wire \blk00000086/sig000002b6 ;
wire \blk00000086/sig000002b5 ;
wire \blk00000086/sig000002b4 ;
wire \blk00000086/sig000002b3 ;
wire \blk00000086/sig000002b2 ;
wire \blk00000086/sig000002b1 ;
wire \blk00000086/sig000002b0 ;
wire \blk00000086/sig000002af ;
wire \blk00000086/sig000002ae ;
wire \blk00000086/sig000002ad ;
wire \blk00000086/sig000002ac ;
wire \blk00000086/sig000002ab ;
wire \blk00000086/sig000002aa ;
wire \blk00000086/sig000002a9 ;
wire \blk00000086/sig000002a8 ;
wire \blk00000086/sig000002a7 ;
wire \blk00000086/sig000002a6 ;
wire \blk00000086/sig000002a5 ;
wire \blk00000086/sig000002a4 ;
wire \blk00000086/sig000002a3 ;
wire \blk00000086/sig000002a2 ;
wire \blk00000086/sig000002a1 ;
wire \blk00000086/sig000002a0 ;
wire \blk00000086/sig0000029f ;
wire \blk00000086/sig0000029e ;
wire \blk00000086/sig0000029d ;
wire \blk00000086/sig0000029c ;
wire \blk00000086/sig0000029b ;
wire \blk00000086/sig0000029a ;
wire \blk000000bd/sig0000030e ;
wire \blk000000bd/sig0000030d ;
wire \blk000000bd/sig0000030c ;
wire \blk000000bd/sig0000030b ;
wire \blk000000bd/sig0000030a ;
wire \blk000000bd/sig00000309 ;
wire \blk000000bd/sig00000308 ;
wire \blk000000bd/sig00000307 ;
wire \blk000000bd/sig00000306 ;
wire \blk000000bd/sig00000305 ;
wire \blk000000bd/sig00000304 ;
wire \blk000000bd/sig00000303 ;
wire \blk000000bd/sig00000302 ;
wire \blk000000bd/sig00000301 ;
wire \blk000000bd/sig00000300 ;
wire \blk000000bd/sig000002ff ;
wire \blk000000bd/sig000002fe ;
wire \blk000000bd/sig000002fd ;
wire \blk000000bd/sig000002fc ;
wire \blk000000bd/sig000002fb ;
wire \blk000000bd/sig000002fa ;
wire \blk000000bd/sig000002f9 ;
wire \blk000000bd/sig000002f8 ;
wire \blk000000bd/sig000002f7 ;
wire \blk000000bd/sig000002f6 ;
wire \blk000000bd/sig000002f5 ;
wire \blk000000bd/sig000002f4 ;
wire \blk000000bd/sig000002f3 ;
wire \blk000000bd/sig000002f2 ;
wire \blk000000bd/sig000002f1 ;
wire \blk000000bd/sig000002f0 ;
wire \blk000000bd/sig000002ef ;
wire \blk000000bd/sig000002ee ;
wire \blk000000bd/sig000002ed ;
wire \blk000000bd/sig000002ec ;
wire \blk000000bd/sig000002eb ;
wire \blk000000bd/sig000002ea ;
wire \blk000000bd/sig000002e9 ;
wire \blk000000bd/sig000002e8 ;
wire \blk000000bd/sig000002e7 ;
wire \blk000000f4/sig0000035b ;
wire \blk000000f4/sig0000035a ;
wire \blk000000f4/sig00000359 ;
wire \blk000000f4/sig00000358 ;
wire \blk000000f4/sig00000357 ;
wire \blk000000f4/sig00000356 ;
wire \blk000000f4/sig00000355 ;
wire \blk000000f4/sig00000354 ;
wire \blk000000f4/sig00000353 ;
wire \blk000000f4/sig00000352 ;
wire \blk000000f4/sig00000351 ;
wire \blk000000f4/sig00000350 ;
wire \blk000000f4/sig0000034f ;
wire \blk000000f4/sig0000034e ;
wire \blk000000f4/sig0000034d ;
wire \blk000000f4/sig0000034c ;
wire \blk000000f4/sig0000034b ;
wire \blk000000f4/sig0000034a ;
wire \blk000000f4/sig00000349 ;
wire \blk000000f4/sig00000348 ;
wire \blk000000f4/sig00000347 ;
wire \blk000000f4/sig00000346 ;
wire \blk000000f4/sig00000345 ;
wire \blk000000f4/sig00000344 ;
wire \blk000000f4/sig00000343 ;
wire \blk000000f4/sig00000342 ;
wire \blk000000f4/sig00000341 ;
wire \blk000000f4/sig00000340 ;
wire \blk000000f4/sig0000033f ;
wire \blk000000f4/sig0000033e ;
wire \blk000000f4/sig0000033d ;
wire \blk000000f4/sig0000033c ;
wire \blk000000f4/sig0000033b ;
wire \blk000000f4/sig0000033a ;
wire \blk000000f4/sig00000339 ;
wire \blk000000f4/sig00000338 ;
wire \blk000000f4/sig00000337 ;
wire \blk000000f4/sig00000336 ;
wire \blk000000f4/sig00000335 ;
wire \blk000000f4/sig00000334 ;
wire \blk000000f4/sig00000333 ;
wire \blk0000012c/sig000003ad ;
wire \blk0000012c/sig000003ac ;
wire \blk0000012c/sig000003ab ;
wire \blk0000012c/sig000003aa ;
wire \blk0000012c/sig000003a9 ;
wire \blk0000012c/sig000003a8 ;
wire \blk0000012c/sig000003a7 ;
wire \blk0000012c/sig000003a6 ;
wire \blk0000012c/sig000003a5 ;
wire \blk0000012c/sig000003a4 ;
wire \blk0000012c/sig000003a3 ;
wire \blk0000012c/sig000003a2 ;
wire \blk0000012c/sig000003a1 ;
wire \blk0000012c/sig000003a0 ;
wire \blk0000012c/sig0000039f ;
wire \blk0000012c/sig0000039e ;
wire \blk0000012c/sig0000039d ;
wire \blk0000012c/sig0000039c ;
wire \blk0000012c/sig0000039b ;
wire \blk0000012c/sig0000039a ;
wire \blk0000012c/sig00000399 ;
wire \blk0000012c/sig00000398 ;
wire \blk0000012c/sig00000397 ;
wire \blk0000012c/sig00000396 ;
wire \blk0000012c/sig00000395 ;
wire \blk0000012c/sig00000394 ;
wire \blk0000012c/sig00000393 ;
wire \blk0000012c/sig00000392 ;
wire \blk0000012c/sig00000391 ;
wire \blk0000012c/sig00000390 ;
wire \blk0000012c/sig0000038f ;
wire \blk0000012c/sig0000038e ;
wire \blk0000012c/sig0000038d ;
wire \blk0000012c/sig0000038c ;
wire \blk0000012c/sig0000038b ;
wire \blk0000012c/sig0000038a ;
wire \blk0000012c/sig00000389 ;
wire \blk0000012c/sig00000388 ;
wire \blk0000012c/sig00000387 ;
wire \blk0000012c/sig00000386 ;
wire \blk0000012c/sig00000385 ;
wire \blk00000164/sig000003ff ;
wire \blk00000164/sig000003fe ;
wire \blk00000164/sig000003fd ;
wire \blk00000164/sig000003fc ;
wire \blk00000164/sig000003fb ;
wire \blk00000164/sig000003fa ;
wire \blk00000164/sig000003f9 ;
wire \blk00000164/sig000003f8 ;
wire \blk00000164/sig000003f7 ;
wire \blk00000164/sig000003f6 ;
wire \blk00000164/sig000003f5 ;
wire \blk00000164/sig000003f4 ;
wire \blk00000164/sig000003f3 ;
wire \blk00000164/sig000003f2 ;
wire \blk00000164/sig000003f1 ;
wire \blk00000164/sig000003f0 ;
wire \blk00000164/sig000003ef ;
wire \blk00000164/sig000003ee ;
wire \blk00000164/sig000003ed ;
wire \blk00000164/sig000003ec ;
wire \blk00000164/sig000003eb ;
wire \blk00000164/sig000003ea ;
wire \blk00000164/sig000003e9 ;
wire \blk00000164/sig000003e8 ;
wire \blk00000164/sig000003e7 ;
wire \blk00000164/sig000003e6 ;
wire \blk00000164/sig000003e5 ;
wire \blk00000164/sig000003e4 ;
wire \blk00000164/sig000003e3 ;
wire \blk00000164/sig000003e2 ;
wire \blk00000164/sig000003e1 ;
wire \blk00000164/sig000003e0 ;
wire \blk00000164/sig000003df ;
wire \blk00000164/sig000003de ;
wire \blk00000164/sig000003dd ;
wire \blk00000164/sig000003dc ;
wire \blk00000164/sig000003db ;
wire \blk00000164/sig000003da ;
wire \blk00000164/sig000003d9 ;
wire \blk00000164/sig000003d8 ;
wire \blk00000164/sig000003d7 ;
wire \blk000001b7/sig00000417 ;
wire \blk000001b7/sig00000416 ;
wire \blk000001b7/sig00000415 ;
wire \blk000001b7/sig00000414 ;
wire \blk000001b7/sig00000413 ;
wire \blk000001b7/sig00000412 ;
wire \blk000001b7/sig00000411 ;
wire \blk000001b7/sig00000410 ;
wire \blk000001b7/sig0000040f ;
wire \blk000001b7/sig0000040e ;
wire \blk000001b7/sig0000040d ;
wire \blk000001b7/sig0000040c ;
wire \blk000001b7/sig0000040b ;
wire \blk000001ca/sig0000042f ;
wire \blk000001ca/sig0000042e ;
wire \blk000001ca/sig0000042d ;
wire \blk000001ca/sig0000042c ;
wire \blk000001ca/sig0000042b ;
wire \blk000001ca/sig0000042a ;
wire \blk000001ca/sig00000429 ;
wire \blk000001ca/sig00000428 ;
wire \blk000001ca/sig00000427 ;
wire \blk000001ca/sig00000426 ;
wire \blk000001ca/sig00000425 ;
wire \blk000001ca/sig00000424 ;
wire \blk000001ca/sig00000423 ;
wire \blk000001e5/sig00000472 ;
wire \blk000001e5/sig00000471 ;
wire \blk000001e5/sig00000470 ;
wire \blk000001e5/sig0000046f ;
wire \blk000001e5/sig0000046e ;
wire \blk000001e5/sig0000046d ;
wire \blk000001e5/sig0000046c ;
wire \blk000001e5/sig0000046b ;
wire \blk000001e5/sig0000046a ;
wire \blk000001e5/sig00000469 ;
wire \blk000001e5/sig00000468 ;
wire \blk000001e5/sig00000467 ;
wire \blk000001e5/sig00000466 ;
wire \blk000001e5/sig00000465 ;
wire \blk000001e5/sig00000464 ;
wire \blk000001e5/sig00000463 ;
wire \blk000001e5/sig00000462 ;
wire \blk000001e5/sig00000461 ;
wire \blk000001e5/sig00000460 ;
wire \blk000001e5/sig0000045f ;
wire \blk000001e5/sig0000045e ;
wire \blk000001e5/sig0000045d ;
wire \blk000001e5/sig0000045c ;
wire \blk000001e5/sig0000045b ;
wire \blk000001e5/sig0000045a ;
wire \blk000001e5/sig00000459 ;
wire \blk000001e5/sig00000458 ;
wire \blk000001e5/sig00000457 ;
wire \blk000001e5/sig00000456 ;
wire \blk000001e5/sig00000455 ;
wire \blk000001e5/sig00000454 ;
wire \blk000001e5/sig00000453 ;
wire \blk000001e5/sig00000452 ;
wire \blk000001e5/sig00000451 ;
wire \blk000001e5/sig00000450 ;
wire \blk000001e5/sig0000044f ;
wire \blk000001e5/sig0000044e ;
wire \blk000001e5/sig0000044d ;
wire \blk000002d2/sig000004a5 ;
wire \blk000002d2/sig000004a4 ;
wire \blk000002d2/sig000004a3 ;
wire \blk000002d2/sig000004a2 ;
wire \blk000002d2/sig000004a1 ;
wire \blk000002d2/sig000004a0 ;
wire \blk000002d2/sig0000049f ;
wire \blk000002d2/sig0000049e ;
wire \blk000002d2/sig0000049d ;
wire \blk000002d2/sig0000049c ;
wire \blk000002d2/sig0000049b ;
wire \blk000002d2/sig0000049a ;
wire \blk000002d2/sig00000499 ;
wire \blk000002d2/sig00000498 ;
wire NLW_blk000001ab_LO_UNCONNECTED;
wire NLW_blk00000363_Q15_UNCONNECTED;
wire NLW_blk00000365_Q15_UNCONNECTED;
wire NLW_blk00000367_Q15_UNCONNECTED;
wire NLW_blk00000369_Q15_UNCONNECTED;
wire NLW_blk0000036b_Q15_UNCONNECTED;
wire NLW_blk0000036d_Q15_UNCONNECTED;
wire NLW_blk0000036f_Q15_UNCONNECTED;
wire NLW_blk00000371_Q15_UNCONNECTED;
wire NLW_blk00000373_Q15_UNCONNECTED;
wire NLW_blk00000375_Q15_UNCONNECTED;
wire NLW_blk00000377_Q15_UNCONNECTED;
wire NLW_blk00000379_Q15_UNCONNECTED;
wire NLW_blk0000037b_Q15_UNCONNECTED;
wire NLW_blk0000037c_Q15_UNCONNECTED;
wire NLW_blk0000037e_Q15_UNCONNECTED;
wire NLW_blk00000380_Q15_UNCONNECTED;
wire NLW_blk00000381_Q15_UNCONNECTED;
wire NLW_blk00000382_Q15_UNCONNECTED;
wire NLW_blk00000383_Q15_UNCONNECTED;
wire NLW_blk00000384_Q15_UNCONNECTED;
wire NLW_blk00000385_Q15_UNCONNECTED;
wire NLW_blk00000386_Q15_UNCONNECTED;
wire NLW_blk00000387_Q15_UNCONNECTED;
wire NLW_blk00000388_Q15_UNCONNECTED;
wire NLW_blk00000389_Q15_UNCONNECTED;
wire \NLW_blk0000001a/blk0000002a_O_UNCONNECTED ;
wire \NLW_blk0000001a/blk00000029_O_UNCONNECTED ;
wire \NLW_blk0000001a/blk00000028_O_UNCONNECTED ;
wire \NLW_blk0000001a/blk00000027_O_UNCONNECTED ;
wire \NLW_blk0000001a/blk00000026_O_UNCONNECTED ;
wire \NLW_blk0000001a/blk00000025_O_UNCONNECTED ;
wire \NLW_blk0000001a/blk00000024_O_UNCONNECTED ;
wire \NLW_blk0000001a/blk00000023_O_UNCONNECTED ;
wire \NLW_blk0000001a/blk00000022_O_UNCONNECTED ;
wire \NLW_blk0000001a/blk00000021_O_UNCONNECTED ;
wire \NLW_blk0000001a/blk00000020_O_UNCONNECTED ;
wire \NLW_blk0000001a/blk0000001f_O_UNCONNECTED ;
wire \NLW_blk0000001a/blk0000001d_O_UNCONNECTED ;
wire \NLW_blk0000001a/blk0000001c_O_UNCONNECTED ;
wire \NLW_blk00000046/blk00000057_O_UNCONNECTED ;
wire \NLW_blk00000046/blk00000056_O_UNCONNECTED ;
wire \NLW_blk00000046/blk00000055_O_UNCONNECTED ;
wire \NLW_blk00000046/blk00000054_O_UNCONNECTED ;
wire \NLW_blk00000046/blk00000053_O_UNCONNECTED ;
wire \NLW_blk00000046/blk00000052_O_UNCONNECTED ;
wire \NLW_blk00000046/blk00000051_O_UNCONNECTED ;
wire \NLW_blk00000046/blk00000050_O_UNCONNECTED ;
wire \NLW_blk00000046/blk0000004f_O_UNCONNECTED ;
wire \NLW_blk00000046/blk0000004e_O_UNCONNECTED ;
wire \NLW_blk00000046/blk0000004d_O_UNCONNECTED ;
wire \NLW_blk00000046/blk0000004c_O_UNCONNECTED ;
wire \NLW_blk00000046/blk0000004a_O_UNCONNECTED ;
wire \NLW_blk00000046/blk00000049_O_UNCONNECTED ;
wire \NLW_blk00000086/blk00000094_O_UNCONNECTED ;
wire \NLW_blk00000086/blk00000087_O_UNCONNECTED ;
wire \NLW_blk000000bd/blk000000cb_O_UNCONNECTED ;
wire \NLW_blk000000bd/blk000000be_O_UNCONNECTED ;
wire \NLW_blk000000f4/blk000000f5_O_UNCONNECTED ;
wire \NLW_blk0000012c/blk0000012d_O_UNCONNECTED ;
wire \NLW_blk00000164/blk00000165_O_UNCONNECTED ;
wire \NLW_blk000001b7/blk000001ba_O_UNCONNECTED ;
wire \NLW_blk000001ca/blk000001cd_O_UNCONNECTED ;
wire \NLW_blk000001e5/blk000001f3_O_UNCONNECTED ;
wire \NLW_blk000001e5/blk000001f2_O_UNCONNECTED ;
wire \NLW_blk000001e5/blk000001f1_O_UNCONNECTED ;
wire \NLW_blk000001e5/blk000001e6_O_UNCONNECTED ;
wire [9 : 0] \U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg ;
wire [9 : 0] \U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg ;
assign
x_out[9] = \U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [9],
x_out[8] = \U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [8],
x_out[7] = \U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [7],
x_out[6] = \U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [6],
x_out[5] = \U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [5],
x_out[4] = \U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [4],
x_out[3] = \U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [3],
x_out[2] = \U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [2],
x_out[1] = \U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [1],
x_out[0] = \U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [0],
phase_out[9] = \U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [9],
phase_out[8] = \U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [8],
phase_out[7] = \U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [7],
phase_out[6] = \U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [6],
phase_out[5] = \U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [5],
phase_out[4] = \U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [4],
phase_out[3] = \U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [3],
phase_out[2] = \U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [2],
phase_out[1] = \U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [1],
phase_out[0] = \U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [0],
rdy = \U0/i_synth/gen_cordic.output_stage/gen_rdy/gen_rtl.gen_reg.d_reg ,
rfd = NlwRenamedSig_OI_rfd;
VCC blk00000001 (
.P(sig00000001)
);
GND blk00000002 (
.G(sig000000a0)
);
FD #(
.INIT ( 1'b0 ))
blk00000003 (
.C(clk),
.D(sig00000095),
.Q(sig0000002d)
);
FD #(
.INIT ( 1'b0 ))
blk00000004 (
.C(clk),
.D(sig00000094),
.Q(sig0000002e)
);
FD #(
.INIT ( 1'b0 ))
blk00000005 (
.C(clk),
.D(nd),
.Q(sig0000002c)
);
FD #(
.INIT ( 1'b0 ))
blk00000006 (
.C(clk),
.D(y_in[9]),
.Q(sig000000ca)
);
FD #(
.INIT ( 1'b0 ))
blk00000007 (
.C(clk),
.D(y_in[8]),
.Q(sig000000c9)
);
FD #(
.INIT ( 1'b0 ))
blk00000008 (
.C(clk),
.D(y_in[7]),
.Q(sig000000c8)
);
FD #(
.INIT ( 1'b0 ))
blk00000009 (
.C(clk),
.D(y_in[6]),
.Q(sig000000c7)
);
FD #(
.INIT ( 1'b0 ))
blk0000000a (
.C(clk),
.D(y_in[5]),
.Q(sig000000c6)
);
FD #(
.INIT ( 1'b0 ))
blk0000000b (
.C(clk),
.D(y_in[4]),
.Q(sig000000c5)
);
FD #(
.INIT ( 1'b0 ))
blk0000000c (
.C(clk),
.D(y_in[3]),
.Q(sig000000c4)
);
FD #(
.INIT ( 1'b0 ))
blk0000000d (
.C(clk),
.D(y_in[2]),
.Q(sig000000c3)
);
FD #(
.INIT ( 1'b0 ))
blk0000000e (
.C(clk),
.D(y_in[1]),
.Q(sig000000c2)
);
FD #(
.INIT ( 1'b0 ))
blk0000000f (
.C(clk),
.D(y_in[0]),
.Q(sig000000c1)
);
FD #(
.INIT ( 1'b0 ))
blk00000010 (
.C(clk),
.D(x_in[9]),
.Q(sig000000d4)
);
FD #(
.INIT ( 1'b0 ))
blk00000011 (
.C(clk),
.D(x_in[8]),
.Q(sig000000d3)
);
FD #(
.INIT ( 1'b0 ))
blk00000012 (
.C(clk),
.D(x_in[7]),
.Q(sig000000d2)
);
FD #(
.INIT ( 1'b0 ))
blk00000013 (
.C(clk),
.D(x_in[6]),
.Q(sig000000d1)
);
FD #(
.INIT ( 1'b0 ))
blk00000014 (
.C(clk),
.D(x_in[5]),
.Q(sig000000d0)
);
FD #(
.INIT ( 1'b0 ))
blk00000015 (
.C(clk),
.D(x_in[4]),
.Q(sig000000cf)
);
FD #(
.INIT ( 1'b0 ))
blk00000016 (
.C(clk),
.D(x_in[3]),
.Q(sig000000ce)
);
FD #(
.INIT ( 1'b0 ))
blk00000017 (
.C(clk),
.D(x_in[2]),
.Q(sig000000cd)
);
FD #(
.INIT ( 1'b0 ))
blk00000018 (
.C(clk),
.D(x_in[1]),
.Q(sig000000cc)
);
FD #(
.INIT ( 1'b0 ))
blk00000019 (
.C(clk),
.D(x_in[0]),
.Q(sig000000cb)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000072 (
.C(clk),
.CE(sig00000001),
.D(sig000000ca),
.R(sig000000a0),
.Q(sig000000b4)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000073 (
.C(clk),
.CE(sig00000001),
.D(sig000000c9),
.R(sig000000a0),
.Q(sig000000b3)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000074 (
.C(clk),
.CE(sig00000001),
.D(sig000000c8),
.R(sig000000a0),
.Q(sig000000b2)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000075 (
.C(clk),
.CE(sig00000001),
.D(sig000000c7),
.R(sig000000a0),
.Q(sig000000b1)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000076 (
.C(clk),
.CE(sig00000001),
.D(sig000000c6),
.R(sig000000a0),
.Q(sig000000b0)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000077 (
.C(clk),
.CE(sig00000001),
.D(sig000000c5),
.R(sig000000a0),
.Q(sig000000af)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000078 (
.C(clk),
.CE(sig00000001),
.D(sig000000c4),
.R(sig000000a0),
.Q(sig000000ae)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000079 (
.C(clk),
.CE(sig00000001),
.D(sig000000c3),
.R(sig000000a0),
.Q(sig000000ad)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000007a (
.C(clk),
.CE(sig00000001),
.D(sig000000c2),
.R(sig000000a0),
.Q(sig000000ac)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000007b (
.C(clk),
.CE(sig00000001),
.D(sig000000c1),
.R(sig000000a0),
.Q(sig000000ab)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000007c (
.C(clk),
.CE(sig00000001),
.D(sig000000d4),
.R(sig000000a0),
.Q(sig000000be)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000007d (
.C(clk),
.CE(sig00000001),
.D(sig000000d3),
.R(sig000000a0),
.Q(sig000000bd)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000007e (
.C(clk),
.CE(sig00000001),
.D(sig000000d2),
.R(sig000000a0),
.Q(sig000000bc)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000007f (
.C(clk),
.CE(sig00000001),
.D(sig000000d1),
.R(sig000000a0),
.Q(sig000000bb)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000080 (
.C(clk),
.CE(sig00000001),
.D(sig000000d0),
.R(sig000000a0),
.Q(sig000000ba)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000081 (
.C(clk),
.CE(sig00000001),
.D(sig000000cf),
.R(sig000000a0),
.Q(sig000000b9)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000082 (
.C(clk),
.CE(sig00000001),
.D(sig000000ce),
.R(sig000000a0),
.Q(sig000000b8)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000083 (
.C(clk),
.CE(sig00000001),
.D(sig000000cd),
.R(sig000000a0),
.Q(sig000000b7)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000084 (
.C(clk),
.CE(sig00000001),
.D(sig000000cc),
.R(sig000000a0),
.Q(sig000000b6)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000085 (
.C(clk),
.CE(sig00000001),
.D(sig000000cb),
.R(sig000000a0),
.Q(sig000000b5)
);
LUT6 #(
.INIT ( 64'hFDECB9A875643120 ))
blk0000019c (
.I0(sig00000052),
.I1(sig00000053),
.I2(sig00000077),
.I3(sig00000076),
.I4(sig00000078),
.I5(sig00000079),
.O(sig000000d5)
);
LUT6 #(
.INIT ( 64'hFEDC7654BA983210 ))
blk0000019d (
.I0(sig00000052),
.I1(sig00000053),
.I2(sig00000072),
.I3(sig00000073),
.I4(sig00000075),
.I5(sig00000074),
.O(sig000000d6)
);
MUXF7 blk0000019e (
.I0(sig000000d6),
.I1(sig000000d5),
.S(sig00000054),
.O(sig0000005b)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000019f (
.I0(sig00000053),
.I1(sig00000052),
.I2(sig00000077),
.I3(sig00000078),
.I4(sig00000076),
.I5(sig00000075),
.O(sig000000d7)
);
LUT6 #(
.INIT ( 64'hFEDCBA9876543210 ))
blk000001a0 (
.I0(sig00000052),
.I1(sig00000053),
.I2(sig00000071),
.I3(sig00000072),
.I4(sig00000073),
.I5(sig00000074),
.O(sig000000d8)
);
MUXF7 blk000001a1 (
.I0(sig000000d8),
.I1(sig000000d7),
.S(sig00000054),
.O(sig0000005a)
);
LUT6 #(
.INIT ( 64'hF7E6D5C4B3A29180 ))
blk000001a2 (
.I0(sig00000052),
.I1(sig00000053),
.I2(sig00000082),
.I3(sig0000007f),
.I4(sig00000080),
.I5(sig00000081),
.O(sig000000d9)
);
LUT6 #(
.INIT ( 64'hFD75EC64B931A820 ))
blk000001a3 (
.I0(sig00000052),
.I1(sig00000053),
.I2(sig00000083),
.I3(sig00000085),
.I4(sig00000082),
.I5(sig00000084),
.O(sig000000da)
);
LUT6 #(
.INIT ( 64'hFEDC7654BA983210 ))
blk000001a4 (
.I0(sig00000052),
.I1(sig00000053),
.I2(sig0000007e),
.I3(sig0000007f),
.I4(sig00000081),
.I5(sig00000080),
.O(sig000000db)
);
MUXF7 blk000001a5 (
.I0(sig000000db),
.I1(sig000000da),
.S(sig00000054),
.O(sig00000066)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk000001a6 (
.I0(sig00000053),
.I1(sig00000052),
.I2(sig00000083),
.I3(sig00000084),
.I4(sig00000082),
.I5(sig00000081),
.O(sig000000dc)
);
LUT6 #(
.INIT ( 64'hFEDCBA9876543210 ))
blk000001a7 (
.I0(sig00000052),
.I1(sig00000053),
.I2(sig0000007d),
.I3(sig0000007e),
.I4(sig0000007f),
.I5(sig00000080),
.O(sig000000dd)
);
MUXF7 blk000001a8 (
.I0(sig000000dd),
.I1(sig000000dc),
.S(sig00000054),
.O(sig00000065)
);
LUT6 #(
.INIT ( 64'hFEDCBA9876543210 ))
blk000001a9 (
.I0(sig00000052),
.I1(sig00000053),
.I2(sig00000083),
.I3(sig00000084),
.I4(sig00000085),
.I5(sig00000086),
.O(sig000000de)
);
MUXF7 blk000001aa (
.I0(sig000000d9),
.I1(sig000000de),
.S(sig00000054),
.O(sig00000067)
);
MUXCY_D blk000001ab (
.CI(sig00000001),
.DI(sig000000a0),
.S(sig000000df),
.O(sig000000e0),
.LO(NLW_blk000001ab_LO_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ac (
.C(clk),
.CE(sig0000004f),
.D(sig0000002d),
.Q(sig00000003)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ad (
.C(clk),
.CE(sig0000004f),
.D(sig0000002e),
.Q(sig00000004)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001ae (
.C(clk),
.CE(sig00000001),
.D(sig000000e0),
.R(sig000000a0),
.Q(sig000000ea)
);
FDS #(
.INIT ( 1'b1 ))
blk000001af (
.C(clk),
.D(sig00000055),
.S(sig000000e9),
.Q(sig00000052)
);
FDS #(
.INIT ( 1'b1 ))
blk000001b0 (
.C(clk),
.D(sig00000056),
.S(sig000000e9),
.Q(sig00000053)
);
FDS #(
.INIT ( 1'b1 ))
blk000001b1 (
.C(clk),
.D(sig00000057),
.S(sig000000e9),
.Q(sig00000054)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001b2 (
.C(clk),
.CE(sig00000001),
.D(sig000000e6),
.R(sig000000a0),
.Q(sig000000e7)
);
FD #(
.INIT ( 1'b1 ))
blk000001b3 (
.C(clk),
.D(NlwRenamedSig_OI_rfd),
.Q(sig000000eb)
);
FDE #(
.INIT ( 1'b0 ))
blk000001b4 (
.C(clk),
.CE(sig00000001),
.D(sig000000e9),
.Q(sig000000e8)
);
FDE #(
.INIT ( 1'b0 ))
blk000001b5 (
.C(clk),
.CE(sig00000001),
.D(sig000000e8),
.Q(sig0000004f)
);
FDRE #(
.INIT ( 1'b0 ))
blk000001b6 (
.C(clk),
.CE(sig00000001),
.D(sig000000ea),
.R(sig000000a0),
.Q(sig00000002)
);
FD #(
.INIT ( 1'b0 ))
blk000001dd (
.C(clk),
.D(sig000000ec),
.Q(sig0000004e)
);
FD #(
.INIT ( 1'b0 ))
blk000001de (
.C(clk),
.D(sig000000ed),
.Q(sig0000004d)
);
FD #(
.INIT ( 1'b0 ))
blk000001df (
.C(clk),
.D(sig000000ee),
.Q(sig0000004c)
);
FD #(
.INIT ( 1'b0 ))
blk000001e0 (
.C(clk),
.D(sig000000ef),
.Q(sig0000004b)
);
FD #(
.INIT ( 1'b0 ))
blk000001e1 (
.C(clk),
.D(sig000000f0),
.Q(sig0000004a)
);
FD #(
.INIT ( 1'b0 ))
blk000001e2 (
.C(clk),
.D(sig000000f1),
.Q(sig00000049)
);
FD #(
.INIT ( 1'b0 ))
blk000001e3 (
.C(clk),
.D(sig000000f2),
.Q(sig00000048)
);
FD #(
.INIT ( 1'b0 ))
blk000001e4 (
.C(clk),
.D(sig000000f3),
.Q(sig00000047)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000021a (
.C(clk),
.CE(sig00000001),
.D(sig00000005),
.R(sig000000a0),
.Q(sig0000015a)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000021b (
.C(clk),
.CE(sig00000001),
.D(sig00000006),
.R(sig000000a0),
.Q(sig0000015b)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000021c (
.C(clk),
.CE(sig00000001),
.D(sig00000007),
.R(sig000000a0),
.Q(sig0000015c)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000021d (
.C(clk),
.CE(sig00000001),
.D(sig00000008),
.R(sig000000a0),
.Q(sig0000015d)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000021e (
.C(clk),
.CE(sig00000001),
.D(sig00000009),
.R(sig000000a0),
.Q(sig0000015e)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000021f (
.C(clk),
.CE(sig00000001),
.D(sig0000000a),
.R(sig000000a0),
.Q(sig0000015f)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000220 (
.C(clk),
.CE(sig00000001),
.D(sig0000000b),
.R(sig000000a0),
.Q(sig00000160)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000221 (
.C(clk),
.CE(sig00000001),
.D(sig0000000c),
.R(sig000000a0),
.Q(sig00000161)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000222 (
.C(clk),
.CE(sig00000001),
.D(sig0000000d),
.R(sig000000a0),
.Q(sig00000162)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000223 (
.C(clk),
.CE(sig00000001),
.D(sig0000000e),
.R(sig000000a0),
.Q(sig00000163)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000224 (
.C(clk),
.CE(sig00000001),
.D(sig0000000f),
.R(sig000000a0),
.Q(sig00000164)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000225 (
.C(clk),
.CE(sig00000001),
.D(sig00000010),
.R(sig000000a0),
.Q(sig00000165)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000226 (
.C(clk),
.CE(sig00000001),
.D(sig00000011),
.R(sig000000a0),
.Q(sig00000166)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000227 (
.C(clk),
.CE(sig00000001),
.D(sig00000135),
.R(sig000000a0),
.Q(sig00000158)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000228 (
.C(clk),
.CE(sig00000001),
.D(sig00000134),
.R(sig000000a0),
.Q(sig00000159)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000229 (
.C(clk),
.CE(sig00000001),
.D(sig00000136),
.R(sig000000a0),
.Q(sig0000014d)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000022a (
.C(clk),
.CE(sig00000001),
.D(sig00000137),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_rdy/gen_rtl.gen_reg.d_reg )
);
RAM64X1S #(
.INIT ( 64'hFFFFFFC000000000 ))
blk0000022b (
.A0(sig00000167),
.A1(sig00000168),
.A2(sig00000169),
.A3(sig0000016a),
.A4(sig0000016b),
.A5(sig0000016c),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig0000017e)
);
RAM64X1S #(
.INIT ( 64'hFF00003FFFF80000 ))
blk0000022c (
.A0(sig00000167),
.A1(sig00000168),
.A2(sig00000169),
.A3(sig0000016a),
.A4(sig0000016b),
.A5(sig0000016c),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig0000017d)
);
RAM64X1S #(
.INIT ( 64'h00FF803FF007FC00 ))
blk0000022d (
.A0(sig00000167),
.A1(sig00000168),
.A2(sig00000169),
.A3(sig0000016a),
.A4(sig0000016b),
.A5(sig0000016c),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig0000017c)
);
RAM64X1S #(
.INIT ( 64'hE0F07C3E0F07C3E0 ))
blk0000022e (
.A0(sig00000167),
.A1(sig00000168),
.A2(sig00000169),
.A3(sig0000016a),
.A4(sig0000016b),
.A5(sig0000016c),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig0000017b)
);
RAM64X1S #(
.INIT ( 64'h98CE63398CE63398 ))
blk0000022f (
.A0(sig00000167),
.A1(sig00000168),
.A2(sig00000169),
.A3(sig0000016a),
.A4(sig0000016b),
.A5(sig0000016c),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig0000017a)
);
RAM64X1S #(
.INIT ( 64'h54A952A54A952A54 ))
blk00000230 (
.A0(sig00000167),
.A1(sig00000168),
.A2(sig00000169),
.A3(sig0000016a),
.A4(sig0000016b),
.A5(sig0000016c),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig00000179)
);
RAM64X1S #(
.INIT ( 64'h1E3C7870E1C3870E ))
blk00000231 (
.A0(sig00000167),
.A1(sig00000168),
.A2(sig00000169),
.A3(sig0000016a),
.A4(sig0000016b),
.A5(sig0000016c),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig00000178)
);
RAM64X1S #(
.INIT ( 64'h664C99B366CC9932 ))
blk00000232 (
.A0(sig00000167),
.A1(sig00000168),
.A2(sig00000169),
.A3(sig0000016a),
.A4(sig0000016b),
.A5(sig0000016c),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig00000177)
);
RAM64X1S #(
.INIT ( 64'h2AD52AD5AA55AA54 ))
blk00000233 (
.A0(sig00000167),
.A1(sig00000168),
.A2(sig00000169),
.A3(sig0000016a),
.A4(sig0000016b),
.A5(sig0000016c),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig00000176)
);
RAM64X1S #(
.INIT ( 64'h878787870F0F0F0E ))
blk00000234 (
.A0(sig00000167),
.A1(sig00000168),
.A2(sig00000169),
.A3(sig0000016a),
.A4(sig0000016b),
.A5(sig0000016c),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig00000175)
);
RAM64X1S #(
.INIT ( 64'h9999999933333332 ))
blk00000235 (
.A0(sig00000167),
.A1(sig00000168),
.A2(sig00000169),
.A3(sig0000016a),
.A4(sig0000016b),
.A5(sig0000016c),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig00000174)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000236 (
.C(clk),
.CE(sig00000001),
.D(sig0000017e),
.R(sig000000a0),
.Q(sig000000f4)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000237 (
.C(clk),
.CE(sig00000001),
.D(sig0000017d),
.R(sig000000a0),
.Q(sig000000f5)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000238 (
.C(clk),
.CE(sig00000001),
.D(sig0000017c),
.R(sig000000a0),
.Q(sig000000f6)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000239 (
.C(clk),
.CE(sig00000001),
.D(sig0000017b),
.R(sig000000a0),
.Q(sig000000f7)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000023a (
.C(clk),
.CE(sig00000001),
.D(sig0000017a),
.R(sig000000a0),
.Q(sig000000f8)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000023b (
.C(clk),
.CE(sig00000001),
.D(sig00000179),
.R(sig000000a0),
.Q(sig000000f9)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000023c (
.C(clk),
.CE(sig00000001),
.D(sig00000178),
.R(sig000000a0),
.Q(sig000000fa)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000023d (
.C(clk),
.CE(sig00000001),
.D(sig00000177),
.R(sig000000a0),
.Q(sig000000fb)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000023e (
.C(clk),
.CE(sig00000001),
.D(sig00000176),
.R(sig000000a0),
.Q(sig000000fc)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000023f (
.C(clk),
.CE(sig00000001),
.D(sig00000175),
.R(sig000000a0),
.Q(sig000000fd)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000240 (
.C(clk),
.CE(sig00000001),
.D(sig00000174),
.R(sig000000a0),
.Q(sig000000fe)
);
RAM64X1S #(
.INIT ( 64'hFFFFFFC000000000 ))
blk00000241 (
.A0(sig0000016d),
.A1(sig0000016e),
.A2(sig0000016f),
.A3(sig00000170),
.A4(sig00000171),
.A5(sig00000172),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig0000018f)
);
RAM64X1S #(
.INIT ( 64'hFF00003FFFF80000 ))
blk00000242 (
.A0(sig0000016d),
.A1(sig0000016e),
.A2(sig0000016f),
.A3(sig00000170),
.A4(sig00000171),
.A5(sig00000172),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig0000018e)
);
RAM64X1S #(
.INIT ( 64'h00FF803FF007FC00 ))
blk00000243 (
.A0(sig0000016d),
.A1(sig0000016e),
.A2(sig0000016f),
.A3(sig00000170),
.A4(sig00000171),
.A5(sig00000172),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig0000018d)
);
RAM64X1S #(
.INIT ( 64'hE0F07C3E0F07C3E0 ))
blk00000244 (
.A0(sig0000016d),
.A1(sig0000016e),
.A2(sig0000016f),
.A3(sig00000170),
.A4(sig00000171),
.A5(sig00000172),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig0000018c)
);
RAM64X1S #(
.INIT ( 64'h98CE63398CE63398 ))
blk00000245 (
.A0(sig0000016d),
.A1(sig0000016e),
.A2(sig0000016f),
.A3(sig00000170),
.A4(sig00000171),
.A5(sig00000172),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig0000018b)
);
RAM64X1S #(
.INIT ( 64'h54A952A54A952A54 ))
blk00000246 (
.A0(sig0000016d),
.A1(sig0000016e),
.A2(sig0000016f),
.A3(sig00000170),
.A4(sig00000171),
.A5(sig00000172),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig0000018a)
);
RAM64X1S #(
.INIT ( 64'h1E3C7870E1C3870E ))
blk00000247 (
.A0(sig0000016d),
.A1(sig0000016e),
.A2(sig0000016f),
.A3(sig00000170),
.A4(sig00000171),
.A5(sig00000172),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig00000189)
);
RAM64X1S #(
.INIT ( 64'h664C99B366CC9932 ))
blk00000248 (
.A0(sig0000016d),
.A1(sig0000016e),
.A2(sig0000016f),
.A3(sig00000170),
.A4(sig00000171),
.A5(sig00000172),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig00000188)
);
RAM64X1S #(
.INIT ( 64'h2AD52AD5AA55AA54 ))
blk00000249 (
.A0(sig0000016d),
.A1(sig0000016e),
.A2(sig0000016f),
.A3(sig00000170),
.A4(sig00000171),
.A5(sig00000172),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig00000187)
);
RAM64X1S #(
.INIT ( 64'h878787870F0F0F0E ))
blk0000024a (
.A0(sig0000016d),
.A1(sig0000016e),
.A2(sig0000016f),
.A3(sig00000170),
.A4(sig00000171),
.A5(sig00000172),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig00000186)
);
RAM64X1S #(
.INIT ( 64'h9999999933333332 ))
blk0000024b (
.A0(sig0000016d),
.A1(sig0000016e),
.A2(sig0000016f),
.A3(sig00000170),
.A4(sig00000171),
.A5(sig00000172),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig00000185)
);
RAM64X1S #(
.INIT ( 64'hAAAAAAAB55555554 ))
blk0000024c (
.A0(sig0000016d),
.A1(sig0000016e),
.A2(sig0000016f),
.A3(sig00000170),
.A4(sig00000171),
.A5(sig00000172),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig00000184)
);
RAM64X1S #(
.INIT ( 64'h0001FFFE0001FFFE ))
blk0000024d (
.A0(sig0000016d),
.A1(sig0000016e),
.A2(sig0000016f),
.A3(sig00000170),
.A4(sig00000171),
.A5(sig00000172),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig00000183)
);
RAM64X1S #(
.INIT ( 64'h01FE01FE01FE01FE ))
blk0000024e (
.A0(sig0000016d),
.A1(sig0000016e),
.A2(sig0000016f),
.A3(sig00000170),
.A4(sig00000171),
.A5(sig00000172),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig00000182)
);
RAM64X1S #(
.INIT ( 64'h6666666666666666 ))
blk0000024f (
.A0(sig0000016d),
.A1(sig0000016e),
.A2(sig0000016f),
.A3(sig00000170),
.A4(sig00000171),
.A5(sig00000172),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig00000180)
);
RAM64X1S #(
.INIT ( 64'hAAAAAAAAAAAAAAAA ))
blk00000250 (
.A0(sig0000016d),
.A1(sig0000016e),
.A2(sig0000016f),
.A3(sig00000170),
.A4(sig00000171),
.A5(sig00000172),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig0000017f)
);
RAM64X1S #(
.INIT ( 64'h1E1E1E1E1E1E1E1E ))
blk00000251 (
.A0(sig0000016d),
.A1(sig0000016e),
.A2(sig0000016f),
.A3(sig00000170),
.A4(sig00000171),
.A5(sig00000172),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig00000181)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000252 (
.C(clk),
.CE(sig00000001),
.D(sig0000018f),
.R(sig000000a0),
.Q(sig000000ff)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000253 (
.C(clk),
.CE(sig00000001),
.D(sig0000018e),
.R(sig000000a0),
.Q(sig00000100)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000254 (
.C(clk),
.CE(sig00000001),
.D(sig0000018d),
.R(sig000000a0),
.Q(sig00000101)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000255 (
.C(clk),
.CE(sig00000001),
.D(sig0000018c),
.R(sig000000a0),
.Q(sig00000102)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000256 (
.C(clk),
.CE(sig00000001),
.D(sig0000018b),
.R(sig000000a0),
.Q(sig00000103)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000257 (
.C(clk),
.CE(sig00000001),
.D(sig0000018a),
.R(sig000000a0),
.Q(sig00000104)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000258 (
.C(clk),
.CE(sig00000001),
.D(sig00000189),
.R(sig000000a0),
.Q(sig00000105)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000259 (
.C(clk),
.CE(sig00000001),
.D(sig00000188),
.R(sig000000a0),
.Q(sig00000106)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000025a (
.C(clk),
.CE(sig00000001),
.D(sig00000187),
.R(sig000000a0),
.Q(sig00000107)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000025b (
.C(clk),
.CE(sig00000001),
.D(sig00000186),
.R(sig000000a0),
.Q(sig00000108)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000025c (
.C(clk),
.CE(sig00000001),
.D(sig00000185),
.R(sig000000a0),
.Q(sig00000109)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000025d (
.C(clk),
.CE(sig00000001),
.D(sig00000184),
.R(sig000000a0),
.Q(sig0000010a)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000025e (
.C(clk),
.CE(sig00000001),
.D(sig00000183),
.R(sig000000a0),
.Q(sig0000010b)
);
FDRE #(
.INIT ( 1'b0 ))
blk0000025f (
.C(clk),
.CE(sig00000001),
.D(sig00000182),
.R(sig000000a0),
.Q(sig0000010c)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000260 (
.C(clk),
.CE(sig00000001),
.D(sig00000181),
.R(sig000000a0),
.Q(sig0000010d)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000261 (
.C(clk),
.CE(sig00000001),
.D(sig00000180),
.R(sig000000a0),
.Q(sig0000010e)
);
FDRE #(
.INIT ( 1'b0 ))
blk00000262 (
.C(clk),
.CE(sig00000001),
.D(sig0000017f),
.R(sig000000a0),
.Q(sig0000010f)
);
XORCY blk00000263 (
.CI(sig00000191),
.LI(sig000001dc),
.O(sig000001b6)
);
MUXCY blk00000264 (
.CI(sig00000191),
.DI(sig000000a0),
.S(sig000001dc),
.O(sig00000190)
);
XORCY blk00000265 (
.CI(sig00000192),
.LI(sig000001dd),
.O(sig000001b5)
);
MUXCY blk00000266 (
.CI(sig00000192),
.DI(sig000000a0),
.S(sig000001dd),
.O(sig00000191)
);
XORCY blk00000267 (
.CI(sig00000193),
.LI(sig000001de),
.O(sig000001b4)
);
MUXCY blk00000268 (
.CI(sig00000193),
.DI(sig000000a0),
.S(sig000001de),
.O(sig00000192)
);
XORCY blk00000269 (
.CI(sig00000194),
.LI(sig000001df),
.O(sig000001b3)
);
MUXCY blk0000026a (
.CI(sig00000194),
.DI(sig000000a0),
.S(sig000001df),
.O(sig00000193)
);
XORCY blk0000026b (
.CI(sig00000195),
.LI(sig000001e0),
.O(sig000001b2)
);
MUXCY blk0000026c (
.CI(sig00000195),
.DI(sig000000a0),
.S(sig000001e0),
.O(sig00000194)
);
XORCY blk0000026d (
.CI(sig00000196),
.LI(sig000001e1),
.O(sig000001b1)
);
MUXCY blk0000026e (
.CI(sig00000196),
.DI(sig000000a0),
.S(sig000001e1),
.O(sig00000195)
);
XORCY blk0000026f (
.CI(sig00000198),
.LI(sig00000197),
.O(sig000001b0)
);
MUXCY blk00000270 (
.CI(sig00000198),
.DI(sig000000f4),
.S(sig00000197),
.O(sig00000196)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000271 (
.I0(sig000000f4),
.I1(sig00000105),
.O(sig00000197)
);
XORCY blk00000272 (
.CI(sig0000019a),
.LI(sig00000199),
.O(sig000001af)
);
MUXCY blk00000273 (
.CI(sig0000019a),
.DI(sig000000f5),
.S(sig00000199),
.O(sig00000198)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000274 (
.I0(sig000000f5),
.I1(sig00000106),
.O(sig00000199)
);
XORCY blk00000275 (
.CI(sig0000019c),
.LI(sig0000019b),
.O(sig000001ae)
);
MUXCY blk00000276 (
.CI(sig0000019c),
.DI(sig000000f6),
.S(sig0000019b),
.O(sig0000019a)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000277 (
.I0(sig000000f6),
.I1(sig00000107),
.O(sig0000019b)
);
XORCY blk00000278 (
.CI(sig0000019e),
.LI(sig0000019d),
.O(sig000001ad)
);
MUXCY blk00000279 (
.CI(sig0000019e),
.DI(sig000000f7),
.S(sig0000019d),
.O(sig0000019c)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000027a (
.I0(sig000000f7),
.I1(sig00000108),
.O(sig0000019d)
);
XORCY blk0000027b (
.CI(sig000001a0),
.LI(sig0000019f),
.O(sig000001ac)
);
MUXCY blk0000027c (
.CI(sig000001a0),
.DI(sig000000f8),
.S(sig0000019f),
.O(sig0000019e)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000027d (
.I0(sig000000f8),
.I1(sig00000109),
.O(sig0000019f)
);
MUXCY blk0000027e (
.CI(sig000001a2),
.DI(sig000000f9),
.S(sig000001a1),
.O(sig000001a0)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000027f (
.I0(sig000000f9),
.I1(sig0000010a),
.O(sig000001a1)
);
MUXCY blk00000280 (
.CI(sig000001a4),
.DI(sig000000fa),
.S(sig000001a3),
.O(sig000001a2)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000281 (
.I0(sig000000fa),
.I1(sig0000010b),
.O(sig000001a3)
);
MUXCY blk00000282 (
.CI(sig000001a6),
.DI(sig000000fb),
.S(sig000001a5),
.O(sig000001a4)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000283 (
.I0(sig000000fb),
.I1(sig0000010c),
.O(sig000001a5)
);
MUXCY blk00000284 (
.CI(sig000001a8),
.DI(sig000000fc),
.S(sig000001a7),
.O(sig000001a6)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000285 (
.I0(sig000000fc),
.I1(sig0000010d),
.O(sig000001a7)
);
MUXCY blk00000286 (
.CI(sig000001aa),
.DI(sig000000fd),
.S(sig000001a9),
.O(sig000001a8)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000287 (
.I0(sig000000fd),
.I1(sig0000010e),
.O(sig000001a9)
);
MUXCY blk00000288 (
.CI(sig000000a0),
.DI(sig000000fe),
.S(sig000001ab),
.O(sig000001aa)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000289 (
.I0(sig000000fe),
.I1(sig0000010f),
.O(sig000001ab)
);
FD #(
.INIT ( 1'b0 ))
blk0000028a (
.C(clk),
.D(sig00000190),
.Q(sig00000110)
);
FD #(
.INIT ( 1'b0 ))
blk0000028b (
.C(clk),
.D(sig000001b6),
.Q(sig00000111)
);
FD #(
.INIT ( 1'b0 ))
blk0000028c (
.C(clk),
.D(sig000001b5),
.Q(sig00000112)
);
FD #(
.INIT ( 1'b0 ))
blk0000028d (
.C(clk),
.D(sig000001b4),
.Q(sig00000113)
);
FD #(
.INIT ( 1'b0 ))
blk0000028e (
.C(clk),
.D(sig000001b3),
.Q(sig00000114)
);
FD #(
.INIT ( 1'b0 ))
blk0000028f (
.C(clk),
.D(sig000001b2),
.Q(sig00000115)
);
FD #(
.INIT ( 1'b0 ))
blk00000290 (
.C(clk),
.D(sig000001b1),
.Q(sig00000116)
);
FD #(
.INIT ( 1'b0 ))
blk00000291 (
.C(clk),
.D(sig000001b0),
.Q(sig00000117)
);
FD #(
.INIT ( 1'b0 ))
blk00000292 (
.C(clk),
.D(sig000001af),
.Q(sig00000118)
);
FD #(
.INIT ( 1'b0 ))
blk00000293 (
.C(clk),
.D(sig000001ae),
.Q(sig00000119)
);
FD #(
.INIT ( 1'b0 ))
blk00000294 (
.C(clk),
.D(sig000001ad),
.Q(sig0000011a)
);
FD #(
.INIT ( 1'b0 ))
blk00000295 (
.C(clk),
.D(sig000001ac),
.Q(sig0000011b)
);
RAM64X1S #(
.INIT ( 64'h0000000000000000 ))
blk00000296 (
.A0(sig00000173),
.A1(sig000000a0),
.A2(sig000000a0),
.A3(sig000000a0),
.A4(sig000000a0),
.A5(sig000000a0),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig000001b7)
);
RAM64X1S #(
.INIT ( 64'hAAAAAAAAAAAAAAAA ))
blk00000297 (
.A0(sig00000173),
.A1(sig000000a0),
.A2(sig000000a0),
.A3(sig000000a0),
.A4(sig000000a0),
.A5(sig000000a0),
.D(sig000000a0),
.WCLK(clk),
.WE(sig000000a0),
.O(sig000001b8)
);
FD #(
.INIT ( 1'b0 ))
blk00000298 (
.C(clk),
.D(sig000001b8),
.Q(sig0000011d)
);
FD #(
.INIT ( 1'b0 ))
blk00000299 (
.C(clk),
.D(sig000001b7),
.Q(sig0000011c)
);
XORCY blk000002a7 (
.CI(sig000001ba),
.LI(sig000001b9),
.O(sig000001d9)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000002a8 (
.I0(sig00000110),
.I1(sig0000011e),
.O(sig000001b9)
);
XORCY blk000002a9 (
.CI(sig000001bc),
.LI(sig000001bb),
.O(sig000001d8)
);
MUXCY blk000002aa (
.CI(sig000001bc),
.DI(sig00000111),
.S(sig000001bb),
.O(sig000001ba)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000002ab (
.I0(sig00000111),
.I1(sig0000011f),
.O(sig000001bb)
);
XORCY blk000002ac (
.CI(sig000001be),
.LI(sig000001bd),
.O(sig000001d7)
);
MUXCY blk000002ad (
.CI(sig000001be),
.DI(sig00000112),
.S(sig000001bd),
.O(sig000001bc)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000002ae (
.I0(sig00000112),
.I1(sig00000120),
.O(sig000001bd)
);
XORCY blk000002af (
.CI(sig000001c0),
.LI(sig000001bf),
.O(sig000001d6)
);
MUXCY blk000002b0 (
.CI(sig000001c0),
.DI(sig00000113),
.S(sig000001bf),
.O(sig000001be)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000002b1 (
.I0(sig00000113),
.I1(sig00000121),
.O(sig000001bf)
);
XORCY blk000002b2 (
.CI(sig000001c2),
.LI(sig000001c1),
.O(sig000001d5)
);
MUXCY blk000002b3 (
.CI(sig000001c2),
.DI(sig00000114),
.S(sig000001c1),
.O(sig000001c0)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000002b4 (
.I0(sig00000114),
.I1(sig00000122),
.O(sig000001c1)
);
XORCY blk000002b5 (
.CI(sig000001c4),
.LI(sig000001c3),
.O(sig000001d4)
);
MUXCY blk000002b6 (
.CI(sig000001c4),
.DI(sig00000115),
.S(sig000001c3),
.O(sig000001c2)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000002b7 (
.I0(sig00000115),
.I1(sig00000123),
.O(sig000001c3)
);
XORCY blk000002b8 (
.CI(sig000001c6),
.LI(sig000001c5),
.O(sig000001d3)
);
MUXCY blk000002b9 (
.CI(sig000001c6),
.DI(sig00000116),
.S(sig000001c5),
.O(sig000001c4)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000002ba (
.I0(sig00000116),
.I1(sig00000124),
.O(sig000001c5)
);
XORCY blk000002bb (
.CI(sig000001c8),
.LI(sig000001c7),
.O(sig000001d2)
);
MUXCY blk000002bc (
.CI(sig000001c8),
.DI(sig00000117),
.S(sig000001c7),
.O(sig000001c6)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000002bd (
.I0(sig00000117),
.I1(sig00000125),
.O(sig000001c7)
);
XORCY blk000002be (
.CI(sig000001ca),
.LI(sig000001c9),
.O(sig000001d1)
);
MUXCY blk000002bf (
.CI(sig000001ca),
.DI(sig00000118),
.S(sig000001c9),
.O(sig000001c8)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000002c0 (
.I0(sig00000118),
.I1(sig00000126),
.O(sig000001c9)
);
XORCY blk000002c1 (
.CI(sig000001cc),
.LI(sig000001cb),
.O(sig000001d0)
);
MUXCY blk000002c2 (
.CI(sig000001cc),
.DI(sig00000119),
.S(sig000001cb),
.O(sig000001ca)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000002c3 (
.I0(sig00000119),
.I1(sig00000127),
.O(sig000001cb)
);
MUXCY blk000002c4 (
.CI(sig000001ce),
.DI(sig0000011a),
.S(sig000001cd),
.O(sig000001cc)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000002c5 (
.I0(sig0000011a),
.I1(sig00000128),
.O(sig000001cd)
);
MUXCY blk000002c6 (
.CI(sig000000a0),
.DI(sig0000011b),
.S(sig000001cf),
.O(sig000001ce)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000002c7 (
.I0(sig0000011b),
.I1(sig00000129),
.O(sig000001cf)
);
FD #(
.INIT ( 1'b0 ))
blk000002c8 (
.C(clk),
.D(sig000001d9),
.Q(sig0000012a)
);
FD #(
.INIT ( 1'b0 ))
blk000002c9 (
.C(clk),
.D(sig000001d8),
.Q(sig0000012b)
);
FD #(
.INIT ( 1'b0 ))
blk000002ca (
.C(clk),
.D(sig000001d7),
.Q(sig0000012c)
);
FD #(
.INIT ( 1'b0 ))
blk000002cb (
.C(clk),
.D(sig000001d6),
.Q(sig0000012d)
);
FD #(
.INIT ( 1'b0 ))
blk000002cc (
.C(clk),
.D(sig000001d5),
.Q(sig0000012e)
);
FD #(
.INIT ( 1'b0 ))
blk000002cd (
.C(clk),
.D(sig000001d4),
.Q(sig0000012f)
);
FD #(
.INIT ( 1'b0 ))
blk000002ce (
.C(clk),
.D(sig000001d3),
.Q(sig00000130)
);
FD #(
.INIT ( 1'b0 ))
blk000002cf (
.C(clk),
.D(sig000001d2),
.Q(sig00000131)
);
FD #(
.INIT ( 1'b0 ))
blk000002d0 (
.C(clk),
.D(sig000001d1),
.Q(sig00000132)
);
FD #(
.INIT ( 1'b0 ))
blk000002d1 (
.C(clk),
.D(sig000001d0),
.Q(sig00000133)
);
FDRE #(
.INIT ( 1'b0 ))
blk000002d3 (
.C(clk),
.CE(sig00000137),
.D(sig0000012a),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [9])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002d4 (
.C(clk),
.CE(sig00000137),
.D(sig0000012b),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [8])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002d5 (
.C(clk),
.CE(sig00000137),
.D(sig0000012c),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [7])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002d6 (
.C(clk),
.CE(sig00000137),
.D(sig0000012d),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [6])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002d7 (
.C(clk),
.CE(sig00000137),
.D(sig0000012e),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [5])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002d8 (
.C(clk),
.CE(sig00000137),
.D(sig0000012f),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [4])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002d9 (
.C(clk),
.CE(sig00000137),
.D(sig00000130),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [3])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002da (
.C(clk),
.CE(sig00000137),
.D(sig00000131),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [2])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002db (
.C(clk),
.CE(sig00000137),
.D(sig00000132),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [1])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002dc (
.C(clk),
.CE(sig00000137),
.D(sig00000133),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_x_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [0])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002dd (
.C(clk),
.CE(sig00000137),
.D(sig00000141),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [9])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002de (
.C(clk),
.CE(sig00000137),
.D(sig00000140),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [8])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002df (
.C(clk),
.CE(sig00000137),
.D(sig0000013f),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [7])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002e0 (
.C(clk),
.CE(sig00000137),
.D(sig0000013e),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [6])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002e1 (
.C(clk),
.CE(sig00000137),
.D(sig0000013d),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [5])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002e2 (
.C(clk),
.CE(sig00000137),
.D(sig0000013c),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [4])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002e3 (
.C(clk),
.CE(sig00000137),
.D(sig0000013b),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [3])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002e4 (
.C(clk),
.CE(sig00000137),
.D(sig0000013a),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [2])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002e5 (
.C(clk),
.CE(sig00000137),
.D(sig00000139),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [1])
);
FDRE #(
.INIT ( 1'b0 ))
blk000002e6 (
.C(clk),
.CE(sig00000137),
.D(sig00000138),
.R(sig000000a0),
.Q(\U0/i_synth/gen_cordic.output_stage/gen_phase_out.round/gen_truncate.gen_round_out/gen_rtl.gen_reg.d_reg [0])
);
LUT3 #(
.INIT ( 8'hAC ))
blk000002e7 (
.I0(sig00000037),
.I1(sig0000001b),
.I2(sig000001e2),
.O(sig00000077)
);
LUT3 #(
.INIT ( 8'hAC ))
blk000002e8 (
.I0(sig00000036),
.I1(sig0000001a),
.I2(sig000001e2),
.O(sig00000076)
);
LUT3 #(
.INIT ( 8'hAC ))
blk000002e9 (
.I0(sig00000035),
.I1(sig00000019),
.I2(sig000001e5),
.O(sig00000075)
);
LUT3 #(
.INIT ( 8'hAC ))
blk000002ea (
.I0(sig00000034),
.I1(sig00000018),
.I2(sig000001e5),
.O(sig00000074)
);
LUT3 #(
.INIT ( 8'hAC ))
blk000002eb (
.I0(sig00000033),
.I1(sig00000017),
.I2(sig000001e5),
.O(sig00000073)
);
LUT3 #(
.INIT ( 8'hAC ))
blk000002ec (
.I0(sig00000032),
.I1(sig00000016),
.I2(sig000001e5),
.O(sig00000072)
);
LUT3 #(
.INIT ( 8'hAC ))
blk000002ed (
.I0(sig00000031),
.I1(sig00000015),
.I2(sig000001e5),
.O(sig00000071)
);
LUT3 #(
.INIT ( 8'hAC ))
blk000002ee (
.I0(sig00000030),
.I1(sig00000014),
.I2(sig0000004f),
.O(sig00000070)
);
LUT3 #(
.INIT ( 8'hAC ))
blk000002ef (
.I0(sig0000002f),
.I1(sig00000013),
.I2(sig0000004f),
.O(sig0000006f)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000002f0 (
.I0(sig000001e3),
.I1(sig0000003a),
.I2(sig0000001e),
.O(sig00000051)
);
LUT3 #(
.INIT ( 8'hAC ))
blk000002f1 (
.I0(sig00000039),
.I1(sig0000001d),
.I2(sig000001e2),
.O(sig00000079)
);
LUT3 #(
.INIT ( 8'hAC ))
blk000002f2 (
.I0(sig00000038),
.I1(sig0000001c),
.I2(sig000001e2),
.O(sig00000078)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000002f3 (
.I0(sig0000004f),
.I1(sig00000012),
.O(sig0000006e)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000002f4 (
.I0(sig0000004f),
.I1(sig0000000e),
.O(sig00000090)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000002f5 (
.I0(sig0000004f),
.I1(sig0000000d),
.O(sig0000008f)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000002f6 (
.I0(sig0000004f),
.I1(sig0000000c),
.O(sig0000008e)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000002f7 (
.I0(sig0000004f),
.I1(sig0000000b),
.O(sig0000008d)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000002f8 (
.I0(sig0000004f),
.I1(sig0000000a),
.O(sig0000008c)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000002f9 (
.I0(sig0000004f),
.I1(sig00000009),
.O(sig0000008b)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000002fa (
.I0(sig0000004f),
.I1(sig00000008),
.O(sig0000008a)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000002fb (
.I0(sig0000004f),
.I1(sig00000007),
.O(sig00000089)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000002fc (
.I0(sig0000004f),
.I1(sig00000006),
.O(sig00000088)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000002fd (
.I0(sig0000004f),
.I1(sig00000011),
.O(sig00000093)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000002fe (
.I0(sig0000004f),
.I1(sig00000010),
.O(sig00000092)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000002ff (
.I0(sig0000004f),
.I1(sig0000000f),
.O(sig00000091)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000300 (
.I0(sig0000004f),
.I1(sig00000005),
.O(sig00000087)
);
LUT3 #(
.INIT ( 8'hAC ))
blk00000301 (
.I0(sig00000043),
.I1(sig00000028),
.I2(sig000001e2),
.O(sig00000083)
);
LUT3 #(
.INIT ( 8'hAC ))
blk00000302 (
.I0(sig00000042),
.I1(sig00000027),
.I2(sig000001e2),
.O(sig00000082)
);
LUT3 #(
.INIT ( 8'hAC ))
blk00000303 (
.I0(sig00000041),
.I1(sig00000026),
.I2(sig000001e5),
.O(sig00000081)
);
LUT3 #(
.INIT ( 8'hAC ))
blk00000304 (
.I0(sig00000040),
.I1(sig00000025),
.I2(sig000001e5),
.O(sig00000080)
);
LUT3 #(
.INIT ( 8'hAC ))
blk00000305 (
.I0(sig0000003f),
.I1(sig00000024),
.I2(sig000001e5),
.O(sig0000007f)
);
LUT3 #(
.INIT ( 8'hAC ))
blk00000306 (
.I0(sig0000003e),
.I1(sig00000023),
.I2(sig000001e5),
.O(sig0000007e)
);
LUT3 #(
.INIT ( 8'hAC ))
blk00000307 (
.I0(sig0000003d),
.I1(sig00000022),
.I2(sig000001e5),
.O(sig0000007d)
);
LUT3 #(
.INIT ( 8'hAC ))
blk00000308 (
.I0(sig0000003c),
.I1(sig00000021),
.I2(sig0000004f),
.O(sig0000007c)
);
LUT3 #(
.INIT ( 8'hAC ))
blk00000309 (
.I0(sig0000003b),
.I1(sig00000020),
.I2(sig0000004f),
.O(sig0000007b)
);
LUT3 #(
.INIT ( 8'hAC ))
blk0000030a (
.I0(sig00000046),
.I1(sig0000002b),
.I2(sig000001e5),
.O(sig00000086)
);
LUT3 #(
.INIT ( 8'hAC ))
blk0000030b (
.I0(sig00000045),
.I1(sig0000002a),
.I2(sig000001e2),
.O(sig00000085)
);
LUT3 #(
.INIT ( 8'hAC ))
blk0000030c (
.I0(sig00000044),
.I1(sig00000029),
.I2(sig000001e2),
.O(sig00000084)
);
LUT2 #(
.INIT ( 4'h4 ))
blk0000030d (
.I0(sig0000004f),
.I1(sig0000001f),
.O(sig0000007a)
);
LUT6 #(
.INIT ( 64'hFFEFFEEE11011000 ))
blk0000030e (
.I0(sig00000053),
.I1(sig00000054),
.I2(sig00000052),
.I3(sig00000079),
.I4(sig00000078),
.I5(sig00000051),
.O(sig00000061)
);
LUT5 #(
.INIT ( 32'hFFFE0100 ))
blk0000030f (
.I0(sig00000054),
.I1(sig00000053),
.I2(sig00000052),
.I3(sig00000079),
.I4(sig00000051),
.O(sig00000062)
);
LUT6 #(
.INIT ( 64'hFFEFFEEE11011000 ))
blk00000310 (
.I0(sig00000053),
.I1(sig00000054),
.I2(sig00000052),
.I3(sig00000085),
.I4(sig00000084),
.I5(sig00000086),
.O(sig0000006c)
);
LUT5 #(
.INIT ( 32'hFFFE0100 ))
blk00000311 (
.I0(sig00000054),
.I1(sig00000053),
.I2(sig00000052),
.I3(sig00000085),
.I4(sig00000086),
.O(sig0000006d)
);
LUT4 #(
.INIT ( 16'h0400 ))
blk00000312 (
.I0(sig000000e1),
.I1(sig000000e2),
.I2(sig000000e3),
.I3(sig000000e4),
.O(sig000000df)
);
LUT3 #(
.INIT ( 8'hBA ))
blk00000313 (
.I0(sig00000002),
.I1(sig0000002c),
.I2(sig000000eb),
.O(NlwRenamedSig_OI_rfd)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000314 (
.I0(sig0000002c),
.I1(sig000000eb),
.O(sig000000e9)
);
LUT3 #(
.INIT ( 8'h29 ))
blk00000315 (
.I0(sig00000055),
.I1(sig00000056),
.I2(sig00000057),
.O(sig000000f1)
);
LUT3 #(
.INIT ( 8'h14 ))
blk00000316 (
.I0(sig00000055),
.I1(sig00000056),
.I2(sig00000057),
.O(sig000000f0)
);
LUT3 #(
.INIT ( 8'h01 ))
blk00000317 (
.I0(sig00000055),
.I1(sig00000056),
.I2(sig00000057),
.O(sig000000ec)
);
LUT3 #(
.INIT ( 8'h51 ))
blk00000318 (
.I0(sig00000057),
.I1(sig00000056),
.I2(sig00000055),
.O(sig000000ef)
);
LUT3 #(
.INIT ( 8'h51 ))
blk00000319 (
.I0(sig00000055),
.I1(sig00000056),
.I2(sig00000057),
.O(sig000000f2)
);
LUT3 #(
.INIT ( 8'hB9 ))
blk0000031a (
.I0(sig00000057),
.I1(sig00000055),
.I2(sig00000056),
.O(sig000000f3)
);
LUT3 #(
.INIT ( 8'h02 ))
blk0000031b (
.I0(sig00000055),
.I1(sig00000056),
.I2(sig00000057),
.O(sig000000ed)
);
LUT3 #(
.INIT ( 8'h02 ))
blk0000031c (
.I0(sig00000056),
.I1(sig00000055),
.I2(sig00000057),
.O(sig000000ee)
);
LUT2 #(
.INIT ( 4'h7 ))
blk0000031d (
.I0(sig00000004),
.I1(sig00000003),
.O(sig00000134)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000031e (
.I0(sig00000004),
.I1(sig00000003),
.O(sig00000135)
);
LUT3 #(
.INIT ( 8'hAB ))
blk0000031f (
.I0(sig00000004),
.I1(sig00000011),
.I2(sig00000003),
.O(sig00000136)
);
LUT6 #(
.INIT ( 64'hFFEFFAEA15051000 ))
blk00000320 (
.I0(sig00000054),
.I1(sig00000053),
.I2(sig00000052),
.I3(sig00000078),
.I4(sig000001da),
.I5(sig00000051),
.O(sig00000060)
);
LUT6 #(
.INIT ( 64'hFFFB1511EEEA0400 ))
blk00000321 (
.I0(sig00000054),
.I1(sig00000052),
.I2(sig00000053),
.I3(sig00000084),
.I4(sig00000086),
.I5(sig000001db),
.O(sig0000006b)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000322 (
.I0(sig000000ff),
.O(sig000001dc)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000323 (
.I0(sig00000100),
.O(sig000001dd)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000324 (
.I0(sig00000101),
.O(sig000001de)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000325 (
.I0(sig00000102),
.O(sig000001df)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000326 (
.I0(sig00000103),
.O(sig000001e0)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000327 (
.I0(sig00000104),
.O(sig000001e1)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk00000328 (
.I0(sig0000001b),
.I1(sig00000037),
.I2(sig0000001d),
.I3(sig00000039),
.I4(sig0000004f),
.I5(sig00000053),
.O(sig000001da)
);
LUT6 #(
.INIT ( 64'hAAAAFF00CCCCF0F0 ))
blk00000329 (
.I0(sig00000045),
.I1(sig00000043),
.I2(sig00000028),
.I3(sig0000002a),
.I4(sig0000004f),
.I5(sig00000053),
.O(sig000001db)
);
LUT5 #(
.INIT ( 32'hFD75A820 ))
blk0000032a (
.I0(sig00000054),
.I1(sig0000004f),
.I2(sig0000001e),
.I3(sig0000003a),
.I4(sig000000d5),
.O(sig0000005f)
);
LUT5 #(
.INIT ( 32'hFD75A820 ))
blk0000032b (
.I0(sig00000054),
.I1(sig0000004f),
.I2(sig0000002b),
.I3(sig00000046),
.I4(sig000000da),
.O(sig0000006a)
);
LUT3 #(
.INIT ( 8'h53 ))
blk0000032c (
.I0(sig0000003a),
.I1(sig0000001e),
.I2(sig000001e5),
.O(sig00000050)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk0000032d (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000ab),
.I3(sig000000b5),
.O(sig00000096)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk0000032e (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000b5),
.I3(sig000000ab),
.O(sig000000a1)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk0000032f (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000ac),
.I3(sig000000b6),
.O(sig00000097)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000330 (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000b6),
.I3(sig000000ac),
.O(sig000000a2)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000331 (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000ad),
.I3(sig000000b7),
.O(sig00000098)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000332 (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000b7),
.I3(sig000000ad),
.O(sig000000a3)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000333 (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000ae),
.I3(sig000000b8),
.O(sig00000099)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000334 (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000b8),
.I3(sig000000ae),
.O(sig000000a4)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000335 (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000af),
.I3(sig000000b9),
.O(sig0000009a)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000336 (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000b9),
.I3(sig000000af),
.O(sig000000a5)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000337 (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000b0),
.I3(sig000000ba),
.O(sig0000009b)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000338 (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000ba),
.I3(sig000000b0),
.O(sig000000a6)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000339 (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000b1),
.I3(sig000000bb),
.O(sig0000009c)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk0000033a (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000bb),
.I3(sig000000b1),
.O(sig000000a7)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk0000033b (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000b2),
.I3(sig000000bc),
.O(sig0000009d)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk0000033c (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000bc),
.I3(sig000000b2),
.O(sig000000a8)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk0000033d (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000b3),
.I3(sig000000bd),
.O(sig0000009e)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk0000033e (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000bd),
.I3(sig000000b3),
.O(sig000000a9)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk0000033f (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000b4),
.I3(sig000000be),
.O(sig0000009f)
);
LUT4 #(
.INIT ( 16'hF690 ))
blk00000340 (
.I0(sig000000c0),
.I1(sig000000bf),
.I2(sig000000be),
.I3(sig000000b4),
.O(sig000000aa)
);
LUT4 #(
.INIT ( 16'hF444 ))
blk00000341 (
.I0(sig000000e1),
.I1(sig000000e7),
.I2(sig000000eb),
.I3(sig0000002c),
.O(sig000000e6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000342 (
.C(clk),
.CE(sig00000001),
.D(sig000000e8),
.Q(sig000001e2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000343 (
.C(clk),
.CE(sig00000001),
.D(sig000000e8),
.Q(sig000001e3)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000344 (
.I0(sig000001e3),
.I1(sig0000003a),
.I2(sig0000001e),
.O(sig000001e4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000345 (
.C(clk),
.CE(sig00000001),
.D(sig000000e8),
.Q(sig000001e5)
);
MUXF7 blk00000346 (
.I0(sig000001e6),
.I1(sig000001e7),
.S(sig00000054),
.O(sig0000005d)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000347 (
.I0(sig00000052),
.I1(sig00000053),
.I2(sig00000075),
.I3(sig00000077),
.I4(sig00000076),
.I5(sig00000074),
.O(sig000001e6)
);
LUT5 #(
.INIT ( 32'hEFEA4540 ))
blk00000348 (
.I0(sig00000053),
.I1(sig00000079),
.I2(sig00000052),
.I3(sig00000078),
.I4(sig000001e4),
.O(sig000001e7)
);
MUXF7 blk00000349 (
.I0(sig000001e8),
.I1(sig000001e9),
.S(sig00000054),
.O(sig00000068)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000034a (
.I0(sig00000052),
.I1(sig00000053),
.I2(sig00000081),
.I3(sig00000083),
.I4(sig00000082),
.I5(sig00000080),
.O(sig000001e8)
);
LUT5 #(
.INIT ( 32'hEFEA4540 ))
blk0000034b (
.I0(sig00000053),
.I1(sig00000085),
.I2(sig00000052),
.I3(sig00000084),
.I4(sig00000086),
.O(sig000001e9)
);
MUXF7 blk0000034c (
.I0(sig000001ea),
.I1(sig000001eb),
.S(sig00000052),
.O(sig00000058)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000034d (
.I0(sig00000053),
.I1(sig00000054),
.I2(sig00000071),
.I3(sig00000075),
.I4(sig00000073),
.I5(sig0000006f),
.O(sig000001ea)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000034e (
.I0(sig00000053),
.I1(sig00000054),
.I2(sig00000072),
.I3(sig00000076),
.I4(sig00000074),
.I5(sig00000070),
.O(sig000001eb)
);
MUXF7 blk0000034f (
.I0(sig000001ec),
.I1(sig000001ed),
.S(sig00000052),
.O(sig00000063)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000350 (
.I0(sig00000053),
.I1(sig00000054),
.I2(sig0000007d),
.I3(sig00000081),
.I4(sig0000007f),
.I5(sig0000007b),
.O(sig000001ec)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000351 (
.I0(sig00000053),
.I1(sig00000054),
.I2(sig0000007e),
.I3(sig00000082),
.I4(sig00000080),
.I5(sig0000007c),
.O(sig000001ed)
);
MUXF7 blk00000352 (
.I0(sig000001ee),
.I1(sig000001ef),
.S(sig00000054),
.O(sig0000005e)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000353 (
.I0(sig00000053),
.I1(sig00000052),
.I2(sig00000077),
.I3(sig00000078),
.I4(sig00000076),
.I5(sig00000075),
.O(sig000001ee)
);
LUT6 #(
.INIT ( 64'hFFEFFEEE11011000 ))
blk00000354 (
.I0(sig00000052),
.I1(sig00000053),
.I2(sig0000004f),
.I3(sig00000039),
.I4(sig0000001d),
.I5(sig00000051),
.O(sig000001ef)
);
MUXF7 blk00000355 (
.I0(sig000001f0),
.I1(sig000001f1),
.S(sig00000054),
.O(sig00000069)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000356 (
.I0(sig00000053),
.I1(sig00000052),
.I2(sig00000083),
.I3(sig00000084),
.I4(sig00000082),
.I5(sig00000081),
.O(sig000001f0)
);
LUT6 #(
.INIT ( 64'hFEFEFE1010FE1010 ))
blk00000357 (
.I0(sig00000053),
.I1(sig00000052),
.I2(sig00000085),
.I3(sig0000004f),
.I4(sig0000002b),
.I5(sig00000046),
.O(sig000001f1)
);
MUXF7 blk00000358 (
.I0(sig000001f2),
.I1(sig000001f3),
.S(sig00000052),
.O(sig0000005c)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000359 (
.I0(sig00000053),
.I1(sig00000054),
.I2(sig00000075),
.I3(sig00000079),
.I4(sig00000077),
.I5(sig00000073),
.O(sig000001f2)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000035a (
.I0(sig00000053),
.I1(sig00000054),
.I2(sig00000076),
.I3(sig000001e4),
.I4(sig00000078),
.I5(sig00000074),
.O(sig000001f3)
);
MUXF7 blk0000035b (
.I0(sig000001f4),
.I1(sig000001f5),
.S(sig00000052),
.O(sig00000059)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000035c (
.I0(sig00000053),
.I1(sig00000054),
.I2(sig00000072),
.I3(sig00000076),
.I4(sig00000074),
.I5(sig00000070),
.O(sig000001f4)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000035d (
.I0(sig00000053),
.I1(sig00000054),
.I2(sig00000073),
.I3(sig00000077),
.I4(sig00000075),
.I5(sig00000071),
.O(sig000001f5)
);
MUXF7 blk0000035e (
.I0(sig000001f6),
.I1(sig000001f7),
.S(sig00000052),
.O(sig00000064)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk0000035f (
.I0(sig00000053),
.I1(sig00000054),
.I2(sig0000007e),
.I3(sig00000082),
.I4(sig00000080),
.I5(sig0000007c),
.O(sig000001f6)
);
LUT6 #(
.INIT ( 64'hFD75B931EC64A820 ))
blk00000360 (
.I0(sig00000053),
.I1(sig00000054),
.I2(sig0000007f),
.I3(sig00000083),
.I4(sig00000081),
.I5(sig0000007d),
.O(sig000001f7)
);
INV blk00000361 (
.I(sig000000c0),
.O(sig00000094)
);
INV blk00000362 (
.I(sig000000bf),
.O(sig00000095)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000363 (
.A0(sig000000a0),
.A1(sig00000001),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000002),
.Q(sig000001f8),
.Q15(NLW_blk00000363_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000364 (
.C(clk),
.CE(sig00000001),
.D(sig000001f8),
.Q(sig0000014c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000365 (
.A0(sig000000a0),
.A1(sig000000a0),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig0000002b),
.Q(sig000001f9),
.Q15(NLW_blk00000365_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000366 (
.C(clk),
.CE(sig00000001),
.D(sig000001f9),
.Q(sig00000173)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000367 (
.A0(sig000000a0),
.A1(sig000000a0),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig0000002a),
.Q(sig000001fa),
.Q15(NLW_blk00000367_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000368 (
.C(clk),
.CE(sig00000001),
.D(sig000001fa),
.Q(sig00000172)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000369 (
.A0(sig000000a0),
.A1(sig000000a0),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000027),
.Q(sig000001fb),
.Q15(NLW_blk00000369_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036a (
.C(clk),
.CE(sig00000001),
.D(sig000001fb),
.Q(sig0000016f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000036b (
.A0(sig000000a0),
.A1(sig000000a0),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000029),
.Q(sig000001fc),
.Q15(NLW_blk0000036b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036c (
.C(clk),
.CE(sig00000001),
.D(sig000001fc),
.Q(sig00000171)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000036d (
.A0(sig000000a0),
.A1(sig000000a0),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000028),
.Q(sig000001fd),
.Q15(NLW_blk0000036d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036e (
.C(clk),
.CE(sig00000001),
.D(sig000001fd),
.Q(sig00000170)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000036f (
.A0(sig000000a0),
.A1(sig000000a0),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000024),
.Q(sig000001fe),
.Q15(NLW_blk0000036f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000370 (
.C(clk),
.CE(sig00000001),
.D(sig000001fe),
.Q(sig0000016c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000371 (
.A0(sig000000a0),
.A1(sig000000a0),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000026),
.Q(sig000001ff),
.Q15(NLW_blk00000371_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000372 (
.C(clk),
.CE(sig00000001),
.D(sig000001ff),
.Q(sig0000016e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000373 (
.A0(sig000000a0),
.A1(sig000000a0),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000025),
.Q(sig00000200),
.Q15(NLW_blk00000373_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000374 (
.C(clk),
.CE(sig00000001),
.D(sig00000200),
.Q(sig0000016d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000375 (
.A0(sig000000a0),
.A1(sig000000a0),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000021),
.Q(sig00000201),
.Q15(NLW_blk00000375_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000376 (
.C(clk),
.CE(sig00000001),
.D(sig00000201),
.Q(sig00000169)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000377 (
.A0(sig000000a0),
.A1(sig000000a0),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000023),
.Q(sig00000202),
.Q15(NLW_blk00000377_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000378 (
.C(clk),
.CE(sig00000001),
.D(sig00000202),
.Q(sig0000016b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000379 (
.A0(sig000000a0),
.A1(sig000000a0),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000022),
.Q(sig00000203),
.Q15(NLW_blk00000379_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037a (
.C(clk),
.CE(sig00000001),
.D(sig00000203),
.Q(sig0000016a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000037b (
.A0(sig000000a0),
.A1(sig00000001),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000157),
.Q(sig00000141),
.Q15(NLW_blk0000037b_Q15_UNCONNECTED)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000037c (
.A0(sig000000a0),
.A1(sig000000a0),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000020),
.Q(sig00000204),
.Q15(NLW_blk0000037c_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037d (
.C(clk),
.CE(sig00000001),
.D(sig00000204),
.Q(sig00000168)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000037e (
.A0(sig000000a0),
.A1(sig000000a0),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig0000001f),
.Q(sig00000205),
.Q15(NLW_blk0000037e_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037f (
.C(clk),
.CE(sig00000001),
.D(sig00000205),
.Q(sig00000167)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000380 (
.A0(sig000000a0),
.A1(sig00000001),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000154),
.Q(sig0000013e),
.Q15(NLW_blk00000380_Q15_UNCONNECTED)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000381 (
.A0(sig000000a0),
.A1(sig00000001),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000156),
.Q(sig00000140),
.Q15(NLW_blk00000381_Q15_UNCONNECTED)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000382 (
.A0(sig000000a0),
.A1(sig00000001),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000155),
.Q(sig0000013f),
.Q15(NLW_blk00000382_Q15_UNCONNECTED)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000383 (
.A0(sig000000a0),
.A1(sig00000001),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000151),
.Q(sig0000013b),
.Q15(NLW_blk00000383_Q15_UNCONNECTED)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000384 (
.A0(sig000000a0),
.A1(sig00000001),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000153),
.Q(sig0000013d),
.Q15(NLW_blk00000384_Q15_UNCONNECTED)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000385 (
.A0(sig000000a0),
.A1(sig00000001),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000152),
.Q(sig0000013c),
.Q15(NLW_blk00000385_Q15_UNCONNECTED)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000386 (
.A0(sig000000a0),
.A1(sig00000001),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig0000014e),
.Q(sig00000138),
.Q15(NLW_blk00000386_Q15_UNCONNECTED)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000387 (
.A0(sig000000a0),
.A1(sig00000001),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig00000150),
.Q(sig0000013a),
.Q15(NLW_blk00000387_Q15_UNCONNECTED)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000388 (
.A0(sig000000a0),
.A1(sig00000001),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig0000014f),
.Q(sig00000139),
.Q15(NLW_blk00000388_Q15_UNCONNECTED)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000389 (
.A0(sig00000001),
.A1(sig000000a0),
.A2(sig000000a0),
.A3(sig000000a0),
.CE(sig00000001),
.CLK(clk),
.D(sig0000014c),
.Q(sig00000206),
.Q15(NLW_blk00000389_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000038a (
.C(clk),
.CE(sig00000001),
.D(sig00000206),
.Q(sig00000137)
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000001a/blk00000045 (
.I0(sig000000d4),
.I1(sig000000ca),
.O(\blk0000001a/sig0000023d )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000001a/blk00000044 (
.I0(sig000000d4),
.I1(sig000000ca),
.O(\blk0000001a/sig00000224 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000001a/blk00000043 (
.I0(sig000000d4),
.I1(sig000000ca),
.O(\blk0000001a/sig00000225 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000001a/blk00000042 (
.I0(sig000000d3),
.I1(sig000000c9),
.O(\blk0000001a/sig00000226 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000001a/blk00000041 (
.I0(sig000000d2),
.I1(sig000000c8),
.O(\blk0000001a/sig00000227 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000001a/blk00000040 (
.I0(sig000000d1),
.I1(sig000000c7),
.O(\blk0000001a/sig00000228 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000001a/blk0000003f (
.I0(sig000000d0),
.I1(sig000000c6),
.O(\blk0000001a/sig00000229 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000001a/blk0000003e (
.I0(sig000000cf),
.I1(sig000000c5),
.O(\blk0000001a/sig0000022a )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000001a/blk0000003d (
.I0(sig000000ce),
.I1(sig000000c4),
.O(\blk0000001a/sig0000022b )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000001a/blk0000003c (
.I0(sig000000cd),
.I1(sig000000c3),
.O(\blk0000001a/sig0000022c )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000001a/blk0000003b (
.I0(sig000000cc),
.I1(sig000000c2),
.O(\blk0000001a/sig0000022d )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk0000001a/blk0000003a (
.I0(sig000000cb),
.I1(sig000000c1),
.O(\blk0000001a/sig0000022e )
);
FD #(
.INIT ( 1'b0 ))
\blk0000001a/blk00000039 (
.C(clk),
.D(\blk0000001a/sig00000223 ),
.Q(sig000000c0)
);
MUXCY \blk0000001a/blk00000038 (
.CI(\blk0000001a/sig00000222 ),
.DI(sig000000a0),
.S(\blk0000001a/sig00000222 ),
.O(\blk0000001a/sig0000023c )
);
MUXCY \blk0000001a/blk00000037 (
.CI(\blk0000001a/sig0000023c ),
.DI(sig000000a0),
.S(\blk0000001a/sig00000222 ),
.O(\blk0000001a/sig0000023b )
);
MUXCY \blk0000001a/blk00000036 (
.CI(\blk0000001a/sig0000023b ),
.DI(sig000000a0),
.S(\blk0000001a/sig00000222 ),
.O(\blk0000001a/sig0000023a )
);
MUXCY \blk0000001a/blk00000035 (
.CI(\blk0000001a/sig0000023a ),
.DI(sig000000cb),
.S(\blk0000001a/sig0000022e ),
.O(\blk0000001a/sig00000239 )
);
MUXCY \blk0000001a/blk00000034 (
.CI(\blk0000001a/sig00000239 ),
.DI(sig000000cc),
.S(\blk0000001a/sig0000022d ),
.O(\blk0000001a/sig00000238 )
);
MUXCY \blk0000001a/blk00000033 (
.CI(\blk0000001a/sig00000238 ),
.DI(sig000000cd),
.S(\blk0000001a/sig0000022c ),
.O(\blk0000001a/sig00000237 )
);
MUXCY \blk0000001a/blk00000032 (
.CI(\blk0000001a/sig00000237 ),
.DI(sig000000ce),
.S(\blk0000001a/sig0000022b ),
.O(\blk0000001a/sig00000236 )
);
MUXCY \blk0000001a/blk00000031 (
.CI(\blk0000001a/sig00000236 ),
.DI(sig000000cf),
.S(\blk0000001a/sig0000022a ),
.O(\blk0000001a/sig00000235 )
);
MUXCY \blk0000001a/blk00000030 (
.CI(\blk0000001a/sig00000235 ),
.DI(sig000000d0),
.S(\blk0000001a/sig00000229 ),
.O(\blk0000001a/sig00000234 )
);
MUXCY \blk0000001a/blk0000002f (
.CI(\blk0000001a/sig00000234 ),
.DI(sig000000d1),
.S(\blk0000001a/sig00000228 ),
.O(\blk0000001a/sig00000233 )
);
MUXCY \blk0000001a/blk0000002e (
.CI(\blk0000001a/sig00000233 ),
.DI(sig000000d2),
.S(\blk0000001a/sig00000227 ),
.O(\blk0000001a/sig00000232 )
);
MUXCY \blk0000001a/blk0000002d (
.CI(\blk0000001a/sig00000232 ),
.DI(sig000000d3),
.S(\blk0000001a/sig00000226 ),
.O(\blk0000001a/sig00000231 )
);
MUXCY \blk0000001a/blk0000002c (
.CI(\blk0000001a/sig00000231 ),
.DI(sig000000d4),
.S(\blk0000001a/sig00000225 ),
.O(\blk0000001a/sig00000230 )
);
MUXCY \blk0000001a/blk0000002b (
.CI(\blk0000001a/sig00000230 ),
.DI(sig000000d4),
.S(\blk0000001a/sig0000023d ),
.O(\blk0000001a/sig0000022f )
);
XORCY \blk0000001a/blk0000002a (
.CI(\blk0000001a/sig0000023c ),
.LI(\blk0000001a/sig00000222 ),
.O(\NLW_blk0000001a/blk0000002a_O_UNCONNECTED )
);
XORCY \blk0000001a/blk00000029 (
.CI(\blk0000001a/sig0000023b ),
.LI(\blk0000001a/sig00000222 ),
.O(\NLW_blk0000001a/blk00000029_O_UNCONNECTED )
);
XORCY \blk0000001a/blk00000028 (
.CI(\blk0000001a/sig0000023a ),
.LI(\blk0000001a/sig0000022e ),
.O(\NLW_blk0000001a/blk00000028_O_UNCONNECTED )
);
XORCY \blk0000001a/blk00000027 (
.CI(\blk0000001a/sig00000239 ),
.LI(\blk0000001a/sig0000022d ),
.O(\NLW_blk0000001a/blk00000027_O_UNCONNECTED )
);
XORCY \blk0000001a/blk00000026 (
.CI(\blk0000001a/sig00000238 ),
.LI(\blk0000001a/sig0000022c ),
.O(\NLW_blk0000001a/blk00000026_O_UNCONNECTED )
);
XORCY \blk0000001a/blk00000025 (
.CI(\blk0000001a/sig00000237 ),
.LI(\blk0000001a/sig0000022b ),
.O(\NLW_blk0000001a/blk00000025_O_UNCONNECTED )
);
XORCY \blk0000001a/blk00000024 (
.CI(\blk0000001a/sig00000236 ),
.LI(\blk0000001a/sig0000022a ),
.O(\NLW_blk0000001a/blk00000024_O_UNCONNECTED )
);
XORCY \blk0000001a/blk00000023 (
.CI(\blk0000001a/sig00000235 ),
.LI(\blk0000001a/sig00000229 ),
.O(\NLW_blk0000001a/blk00000023_O_UNCONNECTED )
);
XORCY \blk0000001a/blk00000022 (
.CI(\blk0000001a/sig00000234 ),
.LI(\blk0000001a/sig00000228 ),
.O(\NLW_blk0000001a/blk00000022_O_UNCONNECTED )
);
XORCY \blk0000001a/blk00000021 (
.CI(\blk0000001a/sig00000233 ),
.LI(\blk0000001a/sig00000227 ),
.O(\NLW_blk0000001a/blk00000021_O_UNCONNECTED )
);
XORCY \blk0000001a/blk00000020 (
.CI(\blk0000001a/sig00000232 ),
.LI(\blk0000001a/sig00000226 ),
.O(\NLW_blk0000001a/blk00000020_O_UNCONNECTED )
);
XORCY \blk0000001a/blk0000001f (
.CI(\blk0000001a/sig00000231 ),
.LI(\blk0000001a/sig00000225 ),
.O(\NLW_blk0000001a/blk0000001f_O_UNCONNECTED )
);
XORCY \blk0000001a/blk0000001e (
.CI(\blk0000001a/sig00000230 ),
.LI(\blk0000001a/sig0000023d ),
.O(\blk0000001a/sig00000223 )
);
XORCY \blk0000001a/blk0000001d (
.CI(\blk0000001a/sig0000022f ),
.LI(\blk0000001a/sig00000224 ),
.O(\NLW_blk0000001a/blk0000001d_O_UNCONNECTED )
);
XORCY \blk0000001a/blk0000001c (
.CI(\blk0000001a/sig00000222 ),
.LI(\blk0000001a/sig00000222 ),
.O(\NLW_blk0000001a/blk0000001c_O_UNCONNECTED )
);
VCC \blk0000001a/blk0000001b (
.P(\blk0000001a/sig00000222 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000046/blk00000071 (
.I0(sig000000d4),
.I1(sig000000ca),
.O(\blk00000046/sig00000274 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000046/blk00000070 (
.I0(sig000000d4),
.I1(sig000000ca),
.O(\blk00000046/sig0000025b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000046/blk0000006f (
.I0(sig000000d4),
.I1(sig000000ca),
.O(\blk00000046/sig0000025c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000046/blk0000006e (
.I0(sig000000d3),
.I1(sig000000c9),
.O(\blk00000046/sig0000025d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000046/blk0000006d (
.I0(sig000000d2),
.I1(sig000000c8),
.O(\blk00000046/sig0000025e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000046/blk0000006c (
.I0(sig000000d1),
.I1(sig000000c7),
.O(\blk00000046/sig0000025f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000046/blk0000006b (
.I0(sig000000d0),
.I1(sig000000c6),
.O(\blk00000046/sig00000260 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000046/blk0000006a (
.I0(sig000000cf),
.I1(sig000000c5),
.O(\blk00000046/sig00000261 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000046/blk00000069 (
.I0(sig000000ce),
.I1(sig000000c4),
.O(\blk00000046/sig00000262 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000046/blk00000068 (
.I0(sig000000cd),
.I1(sig000000c3),
.O(\blk00000046/sig00000263 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000046/blk00000067 (
.I0(sig000000cc),
.I1(sig000000c2),
.O(\blk00000046/sig00000264 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000046/blk00000066 (
.I0(sig000000cb),
.I1(sig000000c1),
.O(\blk00000046/sig00000265 )
);
MUXCY \blk00000046/blk00000065 (
.CI(\blk00000046/sig00000259 ),
.DI(sig000000a0),
.S(\blk00000046/sig00000259 ),
.O(\blk00000046/sig00000273 )
);
MUXCY \blk00000046/blk00000064 (
.CI(\blk00000046/sig00000273 ),
.DI(sig000000a0),
.S(\blk00000046/sig00000259 ),
.O(\blk00000046/sig00000272 )
);
MUXCY \blk00000046/blk00000063 (
.CI(\blk00000046/sig00000272 ),
.DI(sig000000a0),
.S(\blk00000046/sig00000259 ),
.O(\blk00000046/sig00000271 )
);
MUXCY \blk00000046/blk00000062 (
.CI(\blk00000046/sig00000271 ),
.DI(sig000000cb),
.S(\blk00000046/sig00000265 ),
.O(\blk00000046/sig00000270 )
);
MUXCY \blk00000046/blk00000061 (
.CI(\blk00000046/sig00000270 ),
.DI(sig000000cc),
.S(\blk00000046/sig00000264 ),
.O(\blk00000046/sig0000026f )
);
MUXCY \blk00000046/blk00000060 (
.CI(\blk00000046/sig0000026f ),
.DI(sig000000cd),
.S(\blk00000046/sig00000263 ),
.O(\blk00000046/sig0000026e )
);
MUXCY \blk00000046/blk0000005f (
.CI(\blk00000046/sig0000026e ),
.DI(sig000000ce),
.S(\blk00000046/sig00000262 ),
.O(\blk00000046/sig0000026d )
);
MUXCY \blk00000046/blk0000005e (
.CI(\blk00000046/sig0000026d ),
.DI(sig000000cf),
.S(\blk00000046/sig00000261 ),
.O(\blk00000046/sig0000026c )
);
MUXCY \blk00000046/blk0000005d (
.CI(\blk00000046/sig0000026c ),
.DI(sig000000d0),
.S(\blk00000046/sig00000260 ),
.O(\blk00000046/sig0000026b )
);
MUXCY \blk00000046/blk0000005c (
.CI(\blk00000046/sig0000026b ),
.DI(sig000000d1),
.S(\blk00000046/sig0000025f ),
.O(\blk00000046/sig0000026a )
);
MUXCY \blk00000046/blk0000005b (
.CI(\blk00000046/sig0000026a ),
.DI(sig000000d2),
.S(\blk00000046/sig0000025e ),
.O(\blk00000046/sig00000269 )
);
MUXCY \blk00000046/blk0000005a (
.CI(\blk00000046/sig00000269 ),
.DI(sig000000d3),
.S(\blk00000046/sig0000025d ),
.O(\blk00000046/sig00000268 )
);
MUXCY \blk00000046/blk00000059 (
.CI(\blk00000046/sig00000268 ),
.DI(sig000000d4),
.S(\blk00000046/sig0000025c ),
.O(\blk00000046/sig00000267 )
);
MUXCY \blk00000046/blk00000058 (
.CI(\blk00000046/sig00000267 ),
.DI(sig000000d4),
.S(\blk00000046/sig00000274 ),
.O(\blk00000046/sig00000266 )
);
XORCY \blk00000046/blk00000057 (
.CI(\blk00000046/sig00000273 ),
.LI(\blk00000046/sig00000259 ),
.O(\NLW_blk00000046/blk00000057_O_UNCONNECTED )
);
XORCY \blk00000046/blk00000056 (
.CI(\blk00000046/sig00000272 ),
.LI(\blk00000046/sig00000259 ),
.O(\NLW_blk00000046/blk00000056_O_UNCONNECTED )
);
XORCY \blk00000046/blk00000055 (
.CI(\blk00000046/sig00000271 ),
.LI(\blk00000046/sig00000265 ),
.O(\NLW_blk00000046/blk00000055_O_UNCONNECTED )
);
XORCY \blk00000046/blk00000054 (
.CI(\blk00000046/sig00000270 ),
.LI(\blk00000046/sig00000264 ),
.O(\NLW_blk00000046/blk00000054_O_UNCONNECTED )
);
XORCY \blk00000046/blk00000053 (
.CI(\blk00000046/sig0000026f ),
.LI(\blk00000046/sig00000263 ),
.O(\NLW_blk00000046/blk00000053_O_UNCONNECTED )
);
XORCY \blk00000046/blk00000052 (
.CI(\blk00000046/sig0000026e ),
.LI(\blk00000046/sig00000262 ),
.O(\NLW_blk00000046/blk00000052_O_UNCONNECTED )
);
XORCY \blk00000046/blk00000051 (
.CI(\blk00000046/sig0000026d ),
.LI(\blk00000046/sig00000261 ),
.O(\NLW_blk00000046/blk00000051_O_UNCONNECTED )
);
XORCY \blk00000046/blk00000050 (
.CI(\blk00000046/sig0000026c ),
.LI(\blk00000046/sig00000260 ),
.O(\NLW_blk00000046/blk00000050_O_UNCONNECTED )
);
XORCY \blk00000046/blk0000004f (
.CI(\blk00000046/sig0000026b ),
.LI(\blk00000046/sig0000025f ),
.O(\NLW_blk00000046/blk0000004f_O_UNCONNECTED )
);
XORCY \blk00000046/blk0000004e (
.CI(\blk00000046/sig0000026a ),
.LI(\blk00000046/sig0000025e ),
.O(\NLW_blk00000046/blk0000004e_O_UNCONNECTED )
);
XORCY \blk00000046/blk0000004d (
.CI(\blk00000046/sig00000269 ),
.LI(\blk00000046/sig0000025d ),
.O(\NLW_blk00000046/blk0000004d_O_UNCONNECTED )
);
XORCY \blk00000046/blk0000004c (
.CI(\blk00000046/sig00000268 ),
.LI(\blk00000046/sig0000025c ),
.O(\NLW_blk00000046/blk0000004c_O_UNCONNECTED )
);
XORCY \blk00000046/blk0000004b (
.CI(\blk00000046/sig00000267 ),
.LI(\blk00000046/sig00000274 ),
.O(\blk00000046/sig0000025a )
);
XORCY \blk00000046/blk0000004a (
.CI(\blk00000046/sig00000266 ),
.LI(\blk00000046/sig0000025b ),
.O(\NLW_blk00000046/blk0000004a_O_UNCONNECTED )
);
XORCY \blk00000046/blk00000049 (
.CI(\blk00000046/sig00000259 ),
.LI(\blk00000046/sig00000259 ),
.O(\NLW_blk00000046/blk00000049_O_UNCONNECTED )
);
FD #(
.INIT ( 1'b0 ))
\blk00000046/blk00000048 (
.C(clk),
.D(\blk00000046/sig0000025a ),
.Q(sig000000bf)
);
GND \blk00000046/blk00000047 (
.G(\blk00000046/sig00000259 )
);
INV \blk00000086/blk000000bc (
.I(sig00000095),
.O(\blk00000086/sig000002c0 )
);
INV \blk00000086/blk000000bb (
.I(sig00000095),
.O(\blk00000086/sig000002b0 )
);
INV \blk00000086/blk000000ba (
.I(sig00000095),
.O(\blk00000086/sig000002b1 )
);
INV \blk00000086/blk000000b9 (
.I(sig00000095),
.O(\blk00000086/sig000002b2 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000086/blk000000b8 (
.I0(sig000000aa),
.I1(sig00000095),
.O(\blk00000086/sig000002c1 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000086/blk000000b7 (
.I0(sig000000a7),
.I1(sig00000095),
.O(\blk00000086/sig000002a9 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000086/blk000000b6 (
.I0(sig000000a6),
.I1(sig00000095),
.O(\blk00000086/sig000002aa )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000086/blk000000b5 (
.I0(sig000000a5),
.I1(sig00000095),
.O(\blk00000086/sig000002ab )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000086/blk000000b4 (
.I0(sig000000a4),
.I1(sig00000095),
.O(\blk00000086/sig000002ac )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000086/blk000000b3 (
.I0(sig000000a3),
.I1(sig00000095),
.O(\blk00000086/sig000002ad )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000086/blk000000b2 (
.I0(sig000000a2),
.I1(sig00000095),
.O(\blk00000086/sig000002ae )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000086/blk000000b1 (
.I0(sig000000a1),
.I1(sig00000095),
.O(\blk00000086/sig000002af )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000086/blk000000b0 (
.I0(sig000000aa),
.I1(sig00000095),
.O(\blk00000086/sig000002a6 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000086/blk000000af (
.I0(sig000000a9),
.I1(sig00000095),
.O(\blk00000086/sig000002a7 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000086/blk000000ae (
.I0(sig000000a8),
.I1(sig00000095),
.O(\blk00000086/sig000002a8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000086/blk000000ad (
.C(clk),
.D(\blk00000086/sig000002a5 ),
.Q(sig0000003b)
);
FD #(
.INIT ( 1'b0 ))
\blk00000086/blk000000ac (
.C(clk),
.D(\blk00000086/sig000002a4 ),
.Q(sig0000003c)
);
FD #(
.INIT ( 1'b0 ))
\blk00000086/blk000000ab (
.C(clk),
.D(\blk00000086/sig000002a3 ),
.Q(sig0000003d)
);
FD #(
.INIT ( 1'b0 ))
\blk00000086/blk000000aa (
.C(clk),
.D(\blk00000086/sig000002a2 ),
.Q(sig0000003e)
);
FD #(
.INIT ( 1'b0 ))
\blk00000086/blk000000a9 (
.C(clk),
.D(\blk00000086/sig000002a1 ),
.Q(sig0000003f)
);
FD #(
.INIT ( 1'b0 ))
\blk00000086/blk000000a8 (
.C(clk),
.D(\blk00000086/sig000002a0 ),
.Q(sig00000040)
);
FD #(
.INIT ( 1'b0 ))
\blk00000086/blk000000a7 (
.C(clk),
.D(\blk00000086/sig0000029f ),
.Q(sig00000041)
);
FD #(
.INIT ( 1'b0 ))
\blk00000086/blk000000a6 (
.C(clk),
.D(\blk00000086/sig0000029e ),
.Q(sig00000042)
);
FD #(
.INIT ( 1'b0 ))
\blk00000086/blk000000a5 (
.C(clk),
.D(\blk00000086/sig0000029d ),
.Q(sig00000043)
);
FD #(
.INIT ( 1'b0 ))
\blk00000086/blk000000a4 (
.C(clk),
.D(\blk00000086/sig0000029c ),
.Q(sig00000044)
);
FD #(
.INIT ( 1'b0 ))
\blk00000086/blk000000a3 (
.C(clk),
.D(\blk00000086/sig0000029b ),
.Q(sig00000045)
);
FD #(
.INIT ( 1'b0 ))
\blk00000086/blk000000a2 (
.C(clk),
.D(\blk00000086/sig0000029a ),
.Q(sig00000046)
);
MUXCY \blk00000086/blk000000a1 (
.CI(\blk00000086/sig000002c0 ),
.DI(sig000000a0),
.S(\blk00000086/sig000002b2 ),
.O(\blk00000086/sig000002bf )
);
MUXCY \blk00000086/blk000000a0 (
.CI(\blk00000086/sig000002bf ),
.DI(sig000000a0),
.S(\blk00000086/sig000002b1 ),
.O(\blk00000086/sig000002be )
);
MUXCY \blk00000086/blk0000009f (
.CI(\blk00000086/sig000002be ),
.DI(sig000000a0),
.S(\blk00000086/sig000002b0 ),
.O(\blk00000086/sig000002bd )
);
MUXCY \blk00000086/blk0000009e (
.CI(\blk00000086/sig000002bd ),
.DI(sig000000a0),
.S(\blk00000086/sig000002af ),
.O(\blk00000086/sig000002bc )
);
MUXCY \blk00000086/blk0000009d (
.CI(\blk00000086/sig000002bc ),
.DI(sig000000a0),
.S(\blk00000086/sig000002ae ),
.O(\blk00000086/sig000002bb )
);
MUXCY \blk00000086/blk0000009c (
.CI(\blk00000086/sig000002bb ),
.DI(sig000000a0),
.S(\blk00000086/sig000002ad ),
.O(\blk00000086/sig000002ba )
);
MUXCY \blk00000086/blk0000009b (
.CI(\blk00000086/sig000002ba ),
.DI(sig000000a0),
.S(\blk00000086/sig000002ac ),
.O(\blk00000086/sig000002b9 )
);
MUXCY \blk00000086/blk0000009a (
.CI(\blk00000086/sig000002b9 ),
.DI(sig000000a0),
.S(\blk00000086/sig000002ab ),
.O(\blk00000086/sig000002b8 )
);
MUXCY \blk00000086/blk00000099 (
.CI(\blk00000086/sig000002b8 ),
.DI(sig000000a0),
.S(\blk00000086/sig000002aa ),
.O(\blk00000086/sig000002b7 )
);
MUXCY \blk00000086/blk00000098 (
.CI(\blk00000086/sig000002b7 ),
.DI(sig000000a0),
.S(\blk00000086/sig000002a9 ),
.O(\blk00000086/sig000002b6 )
);
MUXCY \blk00000086/blk00000097 (
.CI(\blk00000086/sig000002b6 ),
.DI(sig000000a0),
.S(\blk00000086/sig000002a8 ),
.O(\blk00000086/sig000002b5 )
);
MUXCY \blk00000086/blk00000096 (
.CI(\blk00000086/sig000002b5 ),
.DI(sig000000a0),
.S(\blk00000086/sig000002a7 ),
.O(\blk00000086/sig000002b4 )
);
MUXCY \blk00000086/blk00000095 (
.CI(\blk00000086/sig000002b4 ),
.DI(sig000000a0),
.S(\blk00000086/sig000002c1 ),
.O(\blk00000086/sig000002b3 )
);
XORCY \blk00000086/blk00000094 (
.CI(\blk00000086/sig000002c0 ),
.LI(\blk00000086/sig000002b2 ),
.O(\NLW_blk00000086/blk00000094_O_UNCONNECTED )
);
XORCY \blk00000086/blk00000093 (
.CI(\blk00000086/sig000002bf ),
.LI(\blk00000086/sig000002b1 ),
.O(\blk00000086/sig000002a5 )
);
XORCY \blk00000086/blk00000092 (
.CI(\blk00000086/sig000002be ),
.LI(\blk00000086/sig000002b0 ),
.O(\blk00000086/sig000002a4 )
);
XORCY \blk00000086/blk00000091 (
.CI(\blk00000086/sig000002bd ),
.LI(\blk00000086/sig000002af ),
.O(\blk00000086/sig000002a3 )
);
XORCY \blk00000086/blk00000090 (
.CI(\blk00000086/sig000002bc ),
.LI(\blk00000086/sig000002ae ),
.O(\blk00000086/sig000002a2 )
);
XORCY \blk00000086/blk0000008f (
.CI(\blk00000086/sig000002bb ),
.LI(\blk00000086/sig000002ad ),
.O(\blk00000086/sig000002a1 )
);
XORCY \blk00000086/blk0000008e (
.CI(\blk00000086/sig000002ba ),
.LI(\blk00000086/sig000002ac ),
.O(\blk00000086/sig000002a0 )
);
XORCY \blk00000086/blk0000008d (
.CI(\blk00000086/sig000002b9 ),
.LI(\blk00000086/sig000002ab ),
.O(\blk00000086/sig0000029f )
);
XORCY \blk00000086/blk0000008c (
.CI(\blk00000086/sig000002b8 ),
.LI(\blk00000086/sig000002aa ),
.O(\blk00000086/sig0000029e )
);
XORCY \blk00000086/blk0000008b (
.CI(\blk00000086/sig000002b7 ),
.LI(\blk00000086/sig000002a9 ),
.O(\blk00000086/sig0000029d )
);
XORCY \blk00000086/blk0000008a (
.CI(\blk00000086/sig000002b6 ),
.LI(\blk00000086/sig000002a8 ),
.O(\blk00000086/sig0000029c )
);
XORCY \blk00000086/blk00000089 (
.CI(\blk00000086/sig000002b5 ),
.LI(\blk00000086/sig000002a7 ),
.O(\blk00000086/sig0000029b )
);
XORCY \blk00000086/blk00000088 (
.CI(\blk00000086/sig000002b4 ),
.LI(\blk00000086/sig000002c1 ),
.O(\blk00000086/sig0000029a )
);
XORCY \blk00000086/blk00000087 (
.CI(\blk00000086/sig000002b3 ),
.LI(\blk00000086/sig000002a6 ),
.O(\NLW_blk00000086/blk00000087_O_UNCONNECTED )
);
INV \blk000000bd/blk000000f3 (
.I(sig00000094),
.O(\blk000000bd/sig0000030d )
);
INV \blk000000bd/blk000000f2 (
.I(sig00000094),
.O(\blk000000bd/sig000002fd )
);
INV \blk000000bd/blk000000f1 (
.I(sig00000094),
.O(\blk000000bd/sig000002fe )
);
INV \blk000000bd/blk000000f0 (
.I(sig00000094),
.O(\blk000000bd/sig000002ff )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000000bd/blk000000ef (
.I0(sig0000009f),
.I1(sig00000094),
.O(\blk000000bd/sig0000030e )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000000bd/blk000000ee (
.I0(sig0000009c),
.I1(sig00000094),
.O(\blk000000bd/sig000002f6 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000000bd/blk000000ed (
.I0(sig0000009b),
.I1(sig00000094),
.O(\blk000000bd/sig000002f7 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000000bd/blk000000ec (
.I0(sig0000009a),
.I1(sig00000094),
.O(\blk000000bd/sig000002f8 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000000bd/blk000000eb (
.I0(sig00000099),
.I1(sig00000094),
.O(\blk000000bd/sig000002f9 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000000bd/blk000000ea (
.I0(sig00000098),
.I1(sig00000094),
.O(\blk000000bd/sig000002fa )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000000bd/blk000000e9 (
.I0(sig00000097),
.I1(sig00000094),
.O(\blk000000bd/sig000002fb )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000000bd/blk000000e8 (
.I0(sig00000096),
.I1(sig00000094),
.O(\blk000000bd/sig000002fc )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000000bd/blk000000e7 (
.I0(sig0000009f),
.I1(sig00000094),
.O(\blk000000bd/sig000002f3 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000000bd/blk000000e6 (
.I0(sig0000009e),
.I1(sig00000094),
.O(\blk000000bd/sig000002f4 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000000bd/blk000000e5 (
.I0(sig0000009d),
.I1(sig00000094),
.O(\blk000000bd/sig000002f5 )
);
FD #(
.INIT ( 1'b0 ))
\blk000000bd/blk000000e4 (
.C(clk),
.D(\blk000000bd/sig000002f2 ),
.Q(sig0000002f)
);
FD #(
.INIT ( 1'b0 ))
\blk000000bd/blk000000e3 (
.C(clk),
.D(\blk000000bd/sig000002f1 ),
.Q(sig00000030)
);
FD #(
.INIT ( 1'b0 ))
\blk000000bd/blk000000e2 (
.C(clk),
.D(\blk000000bd/sig000002f0 ),
.Q(sig00000031)
);
FD #(
.INIT ( 1'b0 ))
\blk000000bd/blk000000e1 (
.C(clk),
.D(\blk000000bd/sig000002ef ),
.Q(sig00000032)
);
FD #(
.INIT ( 1'b0 ))
\blk000000bd/blk000000e0 (
.C(clk),
.D(\blk000000bd/sig000002ee ),
.Q(sig00000033)
);
FD #(
.INIT ( 1'b0 ))
\blk000000bd/blk000000df (
.C(clk),
.D(\blk000000bd/sig000002ed ),
.Q(sig00000034)
);
FD #(
.INIT ( 1'b0 ))
\blk000000bd/blk000000de (
.C(clk),
.D(\blk000000bd/sig000002ec ),
.Q(sig00000035)
);
FD #(
.INIT ( 1'b0 ))
\blk000000bd/blk000000dd (
.C(clk),
.D(\blk000000bd/sig000002eb ),
.Q(sig00000036)
);
FD #(
.INIT ( 1'b0 ))
\blk000000bd/blk000000dc (
.C(clk),
.D(\blk000000bd/sig000002ea ),
.Q(sig00000037)
);
FD #(
.INIT ( 1'b0 ))
\blk000000bd/blk000000db (
.C(clk),
.D(\blk000000bd/sig000002e9 ),
.Q(sig00000038)
);
FD #(
.INIT ( 1'b0 ))
\blk000000bd/blk000000da (
.C(clk),
.D(\blk000000bd/sig000002e8 ),
.Q(sig00000039)
);
FD #(
.INIT ( 1'b0 ))
\blk000000bd/blk000000d9 (
.C(clk),
.D(\blk000000bd/sig000002e7 ),
.Q(sig0000003a)
);
MUXCY \blk000000bd/blk000000d8 (
.CI(\blk000000bd/sig0000030d ),
.DI(sig000000a0),
.S(\blk000000bd/sig000002ff ),
.O(\blk000000bd/sig0000030c )
);
MUXCY \blk000000bd/blk000000d7 (
.CI(\blk000000bd/sig0000030c ),
.DI(sig000000a0),
.S(\blk000000bd/sig000002fe ),
.O(\blk000000bd/sig0000030b )
);
MUXCY \blk000000bd/blk000000d6 (
.CI(\blk000000bd/sig0000030b ),
.DI(sig000000a0),
.S(\blk000000bd/sig000002fd ),
.O(\blk000000bd/sig0000030a )
);
MUXCY \blk000000bd/blk000000d5 (
.CI(\blk000000bd/sig0000030a ),
.DI(sig000000a0),
.S(\blk000000bd/sig000002fc ),
.O(\blk000000bd/sig00000309 )
);
MUXCY \blk000000bd/blk000000d4 (
.CI(\blk000000bd/sig00000309 ),
.DI(sig000000a0),
.S(\blk000000bd/sig000002fb ),
.O(\blk000000bd/sig00000308 )
);
MUXCY \blk000000bd/blk000000d3 (
.CI(\blk000000bd/sig00000308 ),
.DI(sig000000a0),
.S(\blk000000bd/sig000002fa ),
.O(\blk000000bd/sig00000307 )
);
MUXCY \blk000000bd/blk000000d2 (
.CI(\blk000000bd/sig00000307 ),
.DI(sig000000a0),
.S(\blk000000bd/sig000002f9 ),
.O(\blk000000bd/sig00000306 )
);
MUXCY \blk000000bd/blk000000d1 (
.CI(\blk000000bd/sig00000306 ),
.DI(sig000000a0),
.S(\blk000000bd/sig000002f8 ),
.O(\blk000000bd/sig00000305 )
);
MUXCY \blk000000bd/blk000000d0 (
.CI(\blk000000bd/sig00000305 ),
.DI(sig000000a0),
.S(\blk000000bd/sig000002f7 ),
.O(\blk000000bd/sig00000304 )
);
MUXCY \blk000000bd/blk000000cf (
.CI(\blk000000bd/sig00000304 ),
.DI(sig000000a0),
.S(\blk000000bd/sig000002f6 ),
.O(\blk000000bd/sig00000303 )
);
MUXCY \blk000000bd/blk000000ce (
.CI(\blk000000bd/sig00000303 ),
.DI(sig000000a0),
.S(\blk000000bd/sig000002f5 ),
.O(\blk000000bd/sig00000302 )
);
MUXCY \blk000000bd/blk000000cd (
.CI(\blk000000bd/sig00000302 ),
.DI(sig000000a0),
.S(\blk000000bd/sig000002f4 ),
.O(\blk000000bd/sig00000301 )
);
MUXCY \blk000000bd/blk000000cc (
.CI(\blk000000bd/sig00000301 ),
.DI(sig000000a0),
.S(\blk000000bd/sig0000030e ),
.O(\blk000000bd/sig00000300 )
);
XORCY \blk000000bd/blk000000cb (
.CI(\blk000000bd/sig0000030d ),
.LI(\blk000000bd/sig000002ff ),
.O(\NLW_blk000000bd/blk000000cb_O_UNCONNECTED )
);
XORCY \blk000000bd/blk000000ca (
.CI(\blk000000bd/sig0000030c ),
.LI(\blk000000bd/sig000002fe ),
.O(\blk000000bd/sig000002f2 )
);
XORCY \blk000000bd/blk000000c9 (
.CI(\blk000000bd/sig0000030b ),
.LI(\blk000000bd/sig000002fd ),
.O(\blk000000bd/sig000002f1 )
);
XORCY \blk000000bd/blk000000c8 (
.CI(\blk000000bd/sig0000030a ),
.LI(\blk000000bd/sig000002fc ),
.O(\blk000000bd/sig000002f0 )
);
XORCY \blk000000bd/blk000000c7 (
.CI(\blk000000bd/sig00000309 ),
.LI(\blk000000bd/sig000002fb ),
.O(\blk000000bd/sig000002ef )
);
XORCY \blk000000bd/blk000000c6 (
.CI(\blk000000bd/sig00000308 ),
.LI(\blk000000bd/sig000002fa ),
.O(\blk000000bd/sig000002ee )
);
XORCY \blk000000bd/blk000000c5 (
.CI(\blk000000bd/sig00000307 ),
.LI(\blk000000bd/sig000002f9 ),
.O(\blk000000bd/sig000002ed )
);
XORCY \blk000000bd/blk000000c4 (
.CI(\blk000000bd/sig00000306 ),
.LI(\blk000000bd/sig000002f8 ),
.O(\blk000000bd/sig000002ec )
);
XORCY \blk000000bd/blk000000c3 (
.CI(\blk000000bd/sig00000305 ),
.LI(\blk000000bd/sig000002f7 ),
.O(\blk000000bd/sig000002eb )
);
XORCY \blk000000bd/blk000000c2 (
.CI(\blk000000bd/sig00000304 ),
.LI(\blk000000bd/sig000002f6 ),
.O(\blk000000bd/sig000002ea )
);
XORCY \blk000000bd/blk000000c1 (
.CI(\blk000000bd/sig00000303 ),
.LI(\blk000000bd/sig000002f5 ),
.O(\blk000000bd/sig000002e9 )
);
XORCY \blk000000bd/blk000000c0 (
.CI(\blk000000bd/sig00000302 ),
.LI(\blk000000bd/sig000002f4 ),
.O(\blk000000bd/sig000002e8 )
);
XORCY \blk000000bd/blk000000bf (
.CI(\blk000000bd/sig00000301 ),
.LI(\blk000000bd/sig0000030e ),
.O(\blk000000bd/sig000002e7 )
);
XORCY \blk000000bd/blk000000be (
.CI(\blk000000bd/sig00000300 ),
.LI(\blk000000bd/sig000002f3 ),
.O(\NLW_blk000000bd/blk000000be_O_UNCONNECTED )
);
INV \blk000000f4/blk0000012b (
.I(sig00000050),
.O(\blk000000f4/sig0000035a )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000000f4/blk0000012a (
.I0(sig00000093),
.I1(sig00000050),
.O(\blk000000f4/sig0000035b )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000000f4/blk00000129 (
.I0(sig00000090),
.I1(sig00000050),
.O(\blk000000f4/sig00000343 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000000f4/blk00000128 (
.I0(sig0000008f),
.I1(sig00000050),
.O(\blk000000f4/sig00000344 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk000000f4/blk00000127 (
.I0(sig0000008e),
.I1(sig0000004e),
.I2(sig00000050),
.O(\blk000000f4/sig00000345 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk000000f4/blk00000126 (
.I0(sig0000008d),
.I1(sig0000004d),
.I2(sig00000050),
.O(\blk000000f4/sig00000346 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk000000f4/blk00000125 (
.I0(sig0000008c),
.I1(sig0000004c),
.I2(sig00000050),
.O(\blk000000f4/sig00000347 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk000000f4/blk00000124 (
.I0(sig0000008b),
.I1(sig0000004b),
.I2(sig00000050),
.O(\blk000000f4/sig00000348 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk000000f4/blk00000123 (
.I0(sig0000008a),
.I1(sig0000004a),
.I2(sig00000050),
.O(\blk000000f4/sig00000349 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk000000f4/blk00000122 (
.I0(sig00000089),
.I1(sig00000049),
.I2(sig00000050),
.O(\blk000000f4/sig0000034a )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk000000f4/blk00000121 (
.I0(sig00000088),
.I1(sig00000048),
.I2(sig00000050),
.O(\blk000000f4/sig0000034b )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000000f4/blk00000120 (
.I0(sig00000093),
.I1(sig00000050),
.O(\blk000000f4/sig00000340 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000000f4/blk0000011f (
.I0(sig00000092),
.I1(sig00000050),
.O(\blk000000f4/sig00000341 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000000f4/blk0000011e (
.I0(sig00000091),
.I1(sig00000050),
.O(\blk000000f4/sig00000342 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk000000f4/blk0000011d (
.I0(sig00000087),
.I1(sig00000047),
.I2(sig00000050),
.O(\blk000000f4/sig0000034c )
);
FD #(
.INIT ( 1'b0 ))
\blk000000f4/blk0000011c (
.C(clk),
.D(\blk000000f4/sig0000033f ),
.Q(sig00000005)
);
FD #(
.INIT ( 1'b0 ))
\blk000000f4/blk0000011b (
.C(clk),
.D(\blk000000f4/sig0000033e ),
.Q(sig00000006)
);
FD #(
.INIT ( 1'b0 ))
\blk000000f4/blk0000011a (
.C(clk),
.D(\blk000000f4/sig0000033d ),
.Q(sig00000007)
);
FD #(
.INIT ( 1'b0 ))
\blk000000f4/blk00000119 (
.C(clk),
.D(\blk000000f4/sig0000033c ),
.Q(sig00000008)
);
FD #(
.INIT ( 1'b0 ))
\blk000000f4/blk00000118 (
.C(clk),
.D(\blk000000f4/sig0000033b ),
.Q(sig00000009)
);
FD #(
.INIT ( 1'b0 ))
\blk000000f4/blk00000117 (
.C(clk),
.D(\blk000000f4/sig0000033a ),
.Q(sig0000000a)
);
FD #(
.INIT ( 1'b0 ))
\blk000000f4/blk00000116 (
.C(clk),
.D(\blk000000f4/sig00000339 ),
.Q(sig0000000b)
);
FD #(
.INIT ( 1'b0 ))
\blk000000f4/blk00000115 (
.C(clk),
.D(\blk000000f4/sig00000338 ),
.Q(sig0000000c)
);
FD #(
.INIT ( 1'b0 ))
\blk000000f4/blk00000114 (
.C(clk),
.D(\blk000000f4/sig00000337 ),
.Q(sig0000000d)
);
FD #(
.INIT ( 1'b0 ))
\blk000000f4/blk00000113 (
.C(clk),
.D(\blk000000f4/sig00000336 ),
.Q(sig0000000e)
);
FD #(
.INIT ( 1'b0 ))
\blk000000f4/blk00000112 (
.C(clk),
.D(\blk000000f4/sig00000335 ),
.Q(sig0000000f)
);
FD #(
.INIT ( 1'b0 ))
\blk000000f4/blk00000111 (
.C(clk),
.D(\blk000000f4/sig00000334 ),
.Q(sig00000010)
);
FD #(
.INIT ( 1'b0 ))
\blk000000f4/blk00000110 (
.C(clk),
.D(\blk000000f4/sig00000333 ),
.Q(sig00000011)
);
MUXCY \blk000000f4/blk0000010f (
.CI(\blk000000f4/sig0000035a ),
.DI(sig00000087),
.S(\blk000000f4/sig0000034c ),
.O(\blk000000f4/sig00000359 )
);
MUXCY \blk000000f4/blk0000010e (
.CI(\blk000000f4/sig00000359 ),
.DI(sig00000088),
.S(\blk000000f4/sig0000034b ),
.O(\blk000000f4/sig00000358 )
);
MUXCY \blk000000f4/blk0000010d (
.CI(\blk000000f4/sig00000358 ),
.DI(sig00000089),
.S(\blk000000f4/sig0000034a ),
.O(\blk000000f4/sig00000357 )
);
MUXCY \blk000000f4/blk0000010c (
.CI(\blk000000f4/sig00000357 ),
.DI(sig0000008a),
.S(\blk000000f4/sig00000349 ),
.O(\blk000000f4/sig00000356 )
);
MUXCY \blk000000f4/blk0000010b (
.CI(\blk000000f4/sig00000356 ),
.DI(sig0000008b),
.S(\blk000000f4/sig00000348 ),
.O(\blk000000f4/sig00000355 )
);
MUXCY \blk000000f4/blk0000010a (
.CI(\blk000000f4/sig00000355 ),
.DI(sig0000008c),
.S(\blk000000f4/sig00000347 ),
.O(\blk000000f4/sig00000354 )
);
MUXCY \blk000000f4/blk00000109 (
.CI(\blk000000f4/sig00000354 ),
.DI(sig0000008d),
.S(\blk000000f4/sig00000346 ),
.O(\blk000000f4/sig00000353 )
);
MUXCY \blk000000f4/blk00000108 (
.CI(\blk000000f4/sig00000353 ),
.DI(sig0000008e),
.S(\blk000000f4/sig00000345 ),
.O(\blk000000f4/sig00000352 )
);
MUXCY \blk000000f4/blk00000107 (
.CI(\blk000000f4/sig00000352 ),
.DI(sig0000008f),
.S(\blk000000f4/sig00000344 ),
.O(\blk000000f4/sig00000351 )
);
MUXCY \blk000000f4/blk00000106 (
.CI(\blk000000f4/sig00000351 ),
.DI(sig00000090),
.S(\blk000000f4/sig00000343 ),
.O(\blk000000f4/sig00000350 )
);
MUXCY \blk000000f4/blk00000105 (
.CI(\blk000000f4/sig00000350 ),
.DI(sig00000091),
.S(\blk000000f4/sig00000342 ),
.O(\blk000000f4/sig0000034f )
);
MUXCY \blk000000f4/blk00000104 (
.CI(\blk000000f4/sig0000034f ),
.DI(sig00000092),
.S(\blk000000f4/sig00000341 ),
.O(\blk000000f4/sig0000034e )
);
MUXCY \blk000000f4/blk00000103 (
.CI(\blk000000f4/sig0000034e ),
.DI(sig00000093),
.S(\blk000000f4/sig0000035b ),
.O(\blk000000f4/sig0000034d )
);
XORCY \blk000000f4/blk00000102 (
.CI(\blk000000f4/sig0000035a ),
.LI(\blk000000f4/sig0000034c ),
.O(\blk000000f4/sig0000033f )
);
XORCY \blk000000f4/blk00000101 (
.CI(\blk000000f4/sig00000359 ),
.LI(\blk000000f4/sig0000034b ),
.O(\blk000000f4/sig0000033e )
);
XORCY \blk000000f4/blk00000100 (
.CI(\blk000000f4/sig00000358 ),
.LI(\blk000000f4/sig0000034a ),
.O(\blk000000f4/sig0000033d )
);
XORCY \blk000000f4/blk000000ff (
.CI(\blk000000f4/sig00000357 ),
.LI(\blk000000f4/sig00000349 ),
.O(\blk000000f4/sig0000033c )
);
XORCY \blk000000f4/blk000000fe (
.CI(\blk000000f4/sig00000356 ),
.LI(\blk000000f4/sig00000348 ),
.O(\blk000000f4/sig0000033b )
);
XORCY \blk000000f4/blk000000fd (
.CI(\blk000000f4/sig00000355 ),
.LI(\blk000000f4/sig00000347 ),
.O(\blk000000f4/sig0000033a )
);
XORCY \blk000000f4/blk000000fc (
.CI(\blk000000f4/sig00000354 ),
.LI(\blk000000f4/sig00000346 ),
.O(\blk000000f4/sig00000339 )
);
XORCY \blk000000f4/blk000000fb (
.CI(\blk000000f4/sig00000353 ),
.LI(\blk000000f4/sig00000345 ),
.O(\blk000000f4/sig00000338 )
);
XORCY \blk000000f4/blk000000fa (
.CI(\blk000000f4/sig00000352 ),
.LI(\blk000000f4/sig00000344 ),
.O(\blk000000f4/sig00000337 )
);
XORCY \blk000000f4/blk000000f9 (
.CI(\blk000000f4/sig00000351 ),
.LI(\blk000000f4/sig00000343 ),
.O(\blk000000f4/sig00000336 )
);
XORCY \blk000000f4/blk000000f8 (
.CI(\blk000000f4/sig00000350 ),
.LI(\blk000000f4/sig00000342 ),
.O(\blk000000f4/sig00000335 )
);
XORCY \blk000000f4/blk000000f7 (
.CI(\blk000000f4/sig0000034f ),
.LI(\blk000000f4/sig00000341 ),
.O(\blk000000f4/sig00000334 )
);
XORCY \blk000000f4/blk000000f6 (
.CI(\blk000000f4/sig0000034e ),
.LI(\blk000000f4/sig0000035b ),
.O(\blk000000f4/sig00000333 )
);
XORCY \blk000000f4/blk000000f5 (
.CI(\blk000000f4/sig0000034d ),
.LI(\blk000000f4/sig00000340 ),
.O(\NLW_blk000000f4/blk000000f5_O_UNCONNECTED )
);
INV \blk0000012c/blk00000163 (
.I(sig00000050),
.O(\blk0000012c/sig000003ac )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk0000012c/blk00000162 (
.I0(sig00000086),
.I1(sig00000051),
.I2(sig00000050),
.O(\blk0000012c/sig000003ad )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk0000012c/blk00000161 (
.I0(sig00000083),
.I1(sig00000050),
.I2(sig00000061),
.O(\blk0000012c/sig00000395 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk0000012c/blk00000160 (
.I0(sig00000082),
.I1(sig00000050),
.I2(sig00000060),
.O(\blk0000012c/sig00000396 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk0000012c/blk0000015f (
.I0(sig00000081),
.I1(sig00000050),
.I2(sig0000005f),
.O(\blk0000012c/sig00000397 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk0000012c/blk0000015e (
.I0(sig00000080),
.I1(sig00000050),
.I2(sig0000005e),
.O(\blk0000012c/sig00000398 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk0000012c/blk0000015d (
.I0(sig0000007f),
.I1(sig00000050),
.I2(sig0000005d),
.O(\blk0000012c/sig00000399 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk0000012c/blk0000015c (
.I0(sig0000007e),
.I1(sig00000050),
.I2(sig0000005c),
.O(\blk0000012c/sig0000039a )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk0000012c/blk0000015b (
.I0(sig0000007d),
.I1(sig00000050),
.I2(sig0000005b),
.O(\blk0000012c/sig0000039b )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk0000012c/blk0000015a (
.I0(sig0000007c),
.I1(sig00000050),
.I2(sig0000005a),
.O(\blk0000012c/sig0000039c )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk0000012c/blk00000159 (
.I0(sig0000007b),
.I1(sig00000050),
.I2(sig00000059),
.O(\blk0000012c/sig0000039d )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk0000012c/blk00000158 (
.I0(sig00000086),
.I1(sig00000051),
.I2(sig00000050),
.O(\blk0000012c/sig00000392 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk0000012c/blk00000157 (
.I0(sig00000085),
.I1(sig00000051),
.I2(sig00000050),
.O(\blk0000012c/sig00000393 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk0000012c/blk00000156 (
.I0(sig00000084),
.I1(sig00000050),
.I2(sig00000062),
.O(\blk0000012c/sig00000394 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk0000012c/blk00000155 (
.I0(sig0000007a),
.I1(sig00000050),
.I2(sig00000058),
.O(\blk0000012c/sig0000039e )
);
FD #(
.INIT ( 1'b0 ))
\blk0000012c/blk00000154 (
.C(clk),
.D(\blk0000012c/sig00000391 ),
.Q(sig0000001f)
);
FD #(
.INIT ( 1'b0 ))
\blk0000012c/blk00000153 (
.C(clk),
.D(\blk0000012c/sig00000390 ),
.Q(sig00000020)
);
FD #(
.INIT ( 1'b0 ))
\blk0000012c/blk00000152 (
.C(clk),
.D(\blk0000012c/sig0000038f ),
.Q(sig00000021)
);
FD #(
.INIT ( 1'b0 ))
\blk0000012c/blk00000151 (
.C(clk),
.D(\blk0000012c/sig0000038e ),
.Q(sig00000022)
);
FD #(
.INIT ( 1'b0 ))
\blk0000012c/blk00000150 (
.C(clk),
.D(\blk0000012c/sig0000038d ),
.Q(sig00000023)
);
FD #(
.INIT ( 1'b0 ))
\blk0000012c/blk0000014f (
.C(clk),
.D(\blk0000012c/sig0000038c ),
.Q(sig00000024)
);
FD #(
.INIT ( 1'b0 ))
\blk0000012c/blk0000014e (
.C(clk),
.D(\blk0000012c/sig0000038b ),
.Q(sig00000025)
);
FD #(
.INIT ( 1'b0 ))
\blk0000012c/blk0000014d (
.C(clk),
.D(\blk0000012c/sig0000038a ),
.Q(sig00000026)
);
FD #(
.INIT ( 1'b0 ))
\blk0000012c/blk0000014c (
.C(clk),
.D(\blk0000012c/sig00000389 ),
.Q(sig00000027)
);
FD #(
.INIT ( 1'b0 ))
\blk0000012c/blk0000014b (
.C(clk),
.D(\blk0000012c/sig00000388 ),
.Q(sig00000028)
);
FD #(
.INIT ( 1'b0 ))
\blk0000012c/blk0000014a (
.C(clk),
.D(\blk0000012c/sig00000387 ),
.Q(sig00000029)
);
FD #(
.INIT ( 1'b0 ))
\blk0000012c/blk00000149 (
.C(clk),
.D(\blk0000012c/sig00000386 ),
.Q(sig0000002a)
);
FD #(
.INIT ( 1'b0 ))
\blk0000012c/blk00000148 (
.C(clk),
.D(\blk0000012c/sig00000385 ),
.Q(sig0000002b)
);
MUXCY \blk0000012c/blk00000147 (
.CI(\blk0000012c/sig000003ac ),
.DI(sig0000007a),
.S(\blk0000012c/sig0000039e ),
.O(\blk0000012c/sig000003ab )
);
MUXCY \blk0000012c/blk00000146 (
.CI(\blk0000012c/sig000003ab ),
.DI(sig0000007b),
.S(\blk0000012c/sig0000039d ),
.O(\blk0000012c/sig000003aa )
);
MUXCY \blk0000012c/blk00000145 (
.CI(\blk0000012c/sig000003aa ),
.DI(sig0000007c),
.S(\blk0000012c/sig0000039c ),
.O(\blk0000012c/sig000003a9 )
);
MUXCY \blk0000012c/blk00000144 (
.CI(\blk0000012c/sig000003a9 ),
.DI(sig0000007d),
.S(\blk0000012c/sig0000039b ),
.O(\blk0000012c/sig000003a8 )
);
MUXCY \blk0000012c/blk00000143 (
.CI(\blk0000012c/sig000003a8 ),
.DI(sig0000007e),
.S(\blk0000012c/sig0000039a ),
.O(\blk0000012c/sig000003a7 )
);
MUXCY \blk0000012c/blk00000142 (
.CI(\blk0000012c/sig000003a7 ),
.DI(sig0000007f),
.S(\blk0000012c/sig00000399 ),
.O(\blk0000012c/sig000003a6 )
);
MUXCY \blk0000012c/blk00000141 (
.CI(\blk0000012c/sig000003a6 ),
.DI(sig00000080),
.S(\blk0000012c/sig00000398 ),
.O(\blk0000012c/sig000003a5 )
);
MUXCY \blk0000012c/blk00000140 (
.CI(\blk0000012c/sig000003a5 ),
.DI(sig00000081),
.S(\blk0000012c/sig00000397 ),
.O(\blk0000012c/sig000003a4 )
);
MUXCY \blk0000012c/blk0000013f (
.CI(\blk0000012c/sig000003a4 ),
.DI(sig00000082),
.S(\blk0000012c/sig00000396 ),
.O(\blk0000012c/sig000003a3 )
);
MUXCY \blk0000012c/blk0000013e (
.CI(\blk0000012c/sig000003a3 ),
.DI(sig00000083),
.S(\blk0000012c/sig00000395 ),
.O(\blk0000012c/sig000003a2 )
);
MUXCY \blk0000012c/blk0000013d (
.CI(\blk0000012c/sig000003a2 ),
.DI(sig00000084),
.S(\blk0000012c/sig00000394 ),
.O(\blk0000012c/sig000003a1 )
);
MUXCY \blk0000012c/blk0000013c (
.CI(\blk0000012c/sig000003a1 ),
.DI(sig00000085),
.S(\blk0000012c/sig00000393 ),
.O(\blk0000012c/sig000003a0 )
);
MUXCY \blk0000012c/blk0000013b (
.CI(\blk0000012c/sig000003a0 ),
.DI(sig00000086),
.S(\blk0000012c/sig000003ad ),
.O(\blk0000012c/sig0000039f )
);
XORCY \blk0000012c/blk0000013a (
.CI(\blk0000012c/sig000003ac ),
.LI(\blk0000012c/sig0000039e ),
.O(\blk0000012c/sig00000391 )
);
XORCY \blk0000012c/blk00000139 (
.CI(\blk0000012c/sig000003ab ),
.LI(\blk0000012c/sig0000039d ),
.O(\blk0000012c/sig00000390 )
);
XORCY \blk0000012c/blk00000138 (
.CI(\blk0000012c/sig000003aa ),
.LI(\blk0000012c/sig0000039c ),
.O(\blk0000012c/sig0000038f )
);
XORCY \blk0000012c/blk00000137 (
.CI(\blk0000012c/sig000003a9 ),
.LI(\blk0000012c/sig0000039b ),
.O(\blk0000012c/sig0000038e )
);
XORCY \blk0000012c/blk00000136 (
.CI(\blk0000012c/sig000003a8 ),
.LI(\blk0000012c/sig0000039a ),
.O(\blk0000012c/sig0000038d )
);
XORCY \blk0000012c/blk00000135 (
.CI(\blk0000012c/sig000003a7 ),
.LI(\blk0000012c/sig00000399 ),
.O(\blk0000012c/sig0000038c )
);
XORCY \blk0000012c/blk00000134 (
.CI(\blk0000012c/sig000003a6 ),
.LI(\blk0000012c/sig00000398 ),
.O(\blk0000012c/sig0000038b )
);
XORCY \blk0000012c/blk00000133 (
.CI(\blk0000012c/sig000003a5 ),
.LI(\blk0000012c/sig00000397 ),
.O(\blk0000012c/sig0000038a )
);
XORCY \blk0000012c/blk00000132 (
.CI(\blk0000012c/sig000003a4 ),
.LI(\blk0000012c/sig00000396 ),
.O(\blk0000012c/sig00000389 )
);
XORCY \blk0000012c/blk00000131 (
.CI(\blk0000012c/sig000003a3 ),
.LI(\blk0000012c/sig00000395 ),
.O(\blk0000012c/sig00000388 )
);
XORCY \blk0000012c/blk00000130 (
.CI(\blk0000012c/sig000003a2 ),
.LI(\blk0000012c/sig00000394 ),
.O(\blk0000012c/sig00000387 )
);
XORCY \blk0000012c/blk0000012f (
.CI(\blk0000012c/sig000003a1 ),
.LI(\blk0000012c/sig00000393 ),
.O(\blk0000012c/sig00000386 )
);
XORCY \blk0000012c/blk0000012e (
.CI(\blk0000012c/sig000003a0 ),
.LI(\blk0000012c/sig000003ad ),
.O(\blk0000012c/sig00000385 )
);
XORCY \blk0000012c/blk0000012d (
.CI(\blk0000012c/sig0000039f ),
.LI(\blk0000012c/sig00000392 ),
.O(\NLW_blk0000012c/blk0000012d_O_UNCONNECTED )
);
INV \blk00000164/blk0000019b (
.I(sig00000051),
.O(\blk00000164/sig000003fe )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000164/blk0000019a (
.I0(sig00000051),
.I1(sig00000086),
.I2(sig00000051),
.O(\blk00000164/sig000003ff )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000164/blk00000199 (
.I0(sig00000077),
.I1(sig00000051),
.I2(sig0000006c),
.O(\blk00000164/sig000003e7 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000164/blk00000198 (
.I0(sig00000076),
.I1(sig00000051),
.I2(sig0000006b),
.O(\blk00000164/sig000003e8 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000164/blk00000197 (
.I0(sig00000075),
.I1(sig00000051),
.I2(sig0000006a),
.O(\blk00000164/sig000003e9 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000164/blk00000196 (
.I0(sig00000074),
.I1(sig00000051),
.I2(sig00000069),
.O(\blk00000164/sig000003ea )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000164/blk00000195 (
.I0(sig00000073),
.I1(sig00000051),
.I2(sig00000068),
.O(\blk00000164/sig000003eb )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000164/blk00000194 (
.I0(sig00000072),
.I1(sig00000051),
.I2(sig00000067),
.O(\blk00000164/sig000003ec )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000164/blk00000193 (
.I0(sig00000071),
.I1(sig00000051),
.I2(sig00000066),
.O(\blk00000164/sig000003ed )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000164/blk00000192 (
.I0(sig00000070),
.I1(sig00000051),
.I2(sig00000065),
.O(\blk00000164/sig000003ee )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000164/blk00000191 (
.I0(sig0000006f),
.I1(sig00000051),
.I2(sig00000064),
.O(\blk00000164/sig000003ef )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000164/blk00000190 (
.I0(sig00000051),
.I1(sig00000086),
.I2(sig00000051),
.O(\blk00000164/sig000003e4 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000164/blk0000018f (
.I0(sig00000079),
.I1(sig00000086),
.I2(sig00000051),
.O(\blk00000164/sig000003e5 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000164/blk0000018e (
.I0(sig00000078),
.I1(sig00000051),
.I2(sig0000006d),
.O(\blk00000164/sig000003e6 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000164/blk0000018d (
.I0(sig0000006e),
.I1(sig00000051),
.I2(sig00000063),
.O(\blk00000164/sig000003f0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000164/blk0000018c (
.C(clk),
.D(\blk00000164/sig000003e3 ),
.Q(sig00000012)
);
FD #(
.INIT ( 1'b0 ))
\blk00000164/blk0000018b (
.C(clk),
.D(\blk00000164/sig000003e2 ),
.Q(sig00000013)
);
FD #(
.INIT ( 1'b0 ))
\blk00000164/blk0000018a (
.C(clk),
.D(\blk00000164/sig000003e1 ),
.Q(sig00000014)
);
FD #(
.INIT ( 1'b0 ))
\blk00000164/blk00000189 (
.C(clk),
.D(\blk00000164/sig000003e0 ),
.Q(sig00000015)
);
FD #(
.INIT ( 1'b0 ))
\blk00000164/blk00000188 (
.C(clk),
.D(\blk00000164/sig000003df ),
.Q(sig00000016)
);
FD #(
.INIT ( 1'b0 ))
\blk00000164/blk00000187 (
.C(clk),
.D(\blk00000164/sig000003de ),
.Q(sig00000017)
);
FD #(
.INIT ( 1'b0 ))
\blk00000164/blk00000186 (
.C(clk),
.D(\blk00000164/sig000003dd ),
.Q(sig00000018)
);
FD #(
.INIT ( 1'b0 ))
\blk00000164/blk00000185 (
.C(clk),
.D(\blk00000164/sig000003dc ),
.Q(sig00000019)
);
FD #(
.INIT ( 1'b0 ))
\blk00000164/blk00000184 (
.C(clk),
.D(\blk00000164/sig000003db ),
.Q(sig0000001a)
);
FD #(
.INIT ( 1'b0 ))
\blk00000164/blk00000183 (
.C(clk),
.D(\blk00000164/sig000003da ),
.Q(sig0000001b)
);
FD #(
.INIT ( 1'b0 ))
\blk00000164/blk00000182 (
.C(clk),
.D(\blk00000164/sig000003d9 ),
.Q(sig0000001c)
);
FD #(
.INIT ( 1'b0 ))
\blk00000164/blk00000181 (
.C(clk),
.D(\blk00000164/sig000003d8 ),
.Q(sig0000001d)
);
FD #(
.INIT ( 1'b0 ))
\blk00000164/blk00000180 (
.C(clk),
.D(\blk00000164/sig000003d7 ),
.Q(sig0000001e)
);
MUXCY \blk00000164/blk0000017f (
.CI(\blk00000164/sig000003fe ),
.DI(sig0000006e),
.S(\blk00000164/sig000003f0 ),
.O(\blk00000164/sig000003fd )
);
MUXCY \blk00000164/blk0000017e (
.CI(\blk00000164/sig000003fd ),
.DI(sig0000006f),
.S(\blk00000164/sig000003ef ),
.O(\blk00000164/sig000003fc )
);
MUXCY \blk00000164/blk0000017d (
.CI(\blk00000164/sig000003fc ),
.DI(sig00000070),
.S(\blk00000164/sig000003ee ),
.O(\blk00000164/sig000003fb )
);
MUXCY \blk00000164/blk0000017c (
.CI(\blk00000164/sig000003fb ),
.DI(sig00000071),
.S(\blk00000164/sig000003ed ),
.O(\blk00000164/sig000003fa )
);
MUXCY \blk00000164/blk0000017b (
.CI(\blk00000164/sig000003fa ),
.DI(sig00000072),
.S(\blk00000164/sig000003ec ),
.O(\blk00000164/sig000003f9 )
);
MUXCY \blk00000164/blk0000017a (
.CI(\blk00000164/sig000003f9 ),
.DI(sig00000073),
.S(\blk00000164/sig000003eb ),
.O(\blk00000164/sig000003f8 )
);
MUXCY \blk00000164/blk00000179 (
.CI(\blk00000164/sig000003f8 ),
.DI(sig00000074),
.S(\blk00000164/sig000003ea ),
.O(\blk00000164/sig000003f7 )
);
MUXCY \blk00000164/blk00000178 (
.CI(\blk00000164/sig000003f7 ),
.DI(sig00000075),
.S(\blk00000164/sig000003e9 ),
.O(\blk00000164/sig000003f6 )
);
MUXCY \blk00000164/blk00000177 (
.CI(\blk00000164/sig000003f6 ),
.DI(sig00000076),
.S(\blk00000164/sig000003e8 ),
.O(\blk00000164/sig000003f5 )
);
MUXCY \blk00000164/blk00000176 (
.CI(\blk00000164/sig000003f5 ),
.DI(sig00000077),
.S(\blk00000164/sig000003e7 ),
.O(\blk00000164/sig000003f4 )
);
MUXCY \blk00000164/blk00000175 (
.CI(\blk00000164/sig000003f4 ),
.DI(sig00000078),
.S(\blk00000164/sig000003e6 ),
.O(\blk00000164/sig000003f3 )
);
MUXCY \blk00000164/blk00000174 (
.CI(\blk00000164/sig000003f3 ),
.DI(sig00000079),
.S(\blk00000164/sig000003e5 ),
.O(\blk00000164/sig000003f2 )
);
MUXCY \blk00000164/blk00000173 (
.CI(\blk00000164/sig000003f2 ),
.DI(sig00000051),
.S(\blk00000164/sig000003ff ),
.O(\blk00000164/sig000003f1 )
);
XORCY \blk00000164/blk00000172 (
.CI(\blk00000164/sig000003fe ),
.LI(\blk00000164/sig000003f0 ),
.O(\blk00000164/sig000003e3 )
);
XORCY \blk00000164/blk00000171 (
.CI(\blk00000164/sig000003fd ),
.LI(\blk00000164/sig000003ef ),
.O(\blk00000164/sig000003e2 )
);
XORCY \blk00000164/blk00000170 (
.CI(\blk00000164/sig000003fc ),
.LI(\blk00000164/sig000003ee ),
.O(\blk00000164/sig000003e1 )
);
XORCY \blk00000164/blk0000016f (
.CI(\blk00000164/sig000003fb ),
.LI(\blk00000164/sig000003ed ),
.O(\blk00000164/sig000003e0 )
);
XORCY \blk00000164/blk0000016e (
.CI(\blk00000164/sig000003fa ),
.LI(\blk00000164/sig000003ec ),
.O(\blk00000164/sig000003df )
);
XORCY \blk00000164/blk0000016d (
.CI(\blk00000164/sig000003f9 ),
.LI(\blk00000164/sig000003eb ),
.O(\blk00000164/sig000003de )
);
XORCY \blk00000164/blk0000016c (
.CI(\blk00000164/sig000003f8 ),
.LI(\blk00000164/sig000003ea ),
.O(\blk00000164/sig000003dd )
);
XORCY \blk00000164/blk0000016b (
.CI(\blk00000164/sig000003f7 ),
.LI(\blk00000164/sig000003e9 ),
.O(\blk00000164/sig000003dc )
);
XORCY \blk00000164/blk0000016a (
.CI(\blk00000164/sig000003f6 ),
.LI(\blk00000164/sig000003e8 ),
.O(\blk00000164/sig000003db )
);
XORCY \blk00000164/blk00000169 (
.CI(\blk00000164/sig000003f5 ),
.LI(\blk00000164/sig000003e7 ),
.O(\blk00000164/sig000003da )
);
XORCY \blk00000164/blk00000168 (
.CI(\blk00000164/sig000003f4 ),
.LI(\blk00000164/sig000003e6 ),
.O(\blk00000164/sig000003d9 )
);
XORCY \blk00000164/blk00000167 (
.CI(\blk00000164/sig000003f3 ),
.LI(\blk00000164/sig000003e5 ),
.O(\blk00000164/sig000003d8 )
);
XORCY \blk00000164/blk00000166 (
.CI(\blk00000164/sig000003f2 ),
.LI(\blk00000164/sig000003ff ),
.O(\blk00000164/sig000003d7 )
);
XORCY \blk00000164/blk00000165 (
.CI(\blk00000164/sig000003f1 ),
.LI(\blk00000164/sig000003e4 ),
.O(\NLW_blk00000164/blk00000165_O_UNCONNECTED )
);
INV \blk000001b7/blk000001c9 (
.I(sig000000e4),
.O(\blk000001b7/sig00000410 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk000001b7/blk000001c8 (
.I0(sig000000e3),
.O(\blk000001b7/sig00000417 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk000001b7/blk000001c7 (
.I0(sig000000e2),
.O(\blk000001b7/sig00000416 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk000001b7/blk000001c6 (
.I0(sig000000e1),
.O(\blk000001b7/sig00000415 )
);
FDRE #(
.INIT ( 1'b0 ))
\blk000001b7/blk000001c5 (
.C(clk),
.CE(sig000000e7),
.D(\blk000001b7/sig0000040c ),
.R(sig000000e9),
.Q(sig000000e4)
);
FDRE #(
.INIT ( 1'b0 ))
\blk000001b7/blk000001c4 (
.C(clk),
.CE(sig000000e7),
.D(\blk000001b7/sig0000040f ),
.R(sig000000e9),
.Q(sig000000e3)
);
FDRE #(
.INIT ( 1'b0 ))
\blk000001b7/blk000001c3 (
.C(clk),
.CE(sig000000e7),
.D(\blk000001b7/sig0000040e ),
.R(sig000000e9),
.Q(sig000000e2)
);
FDRE #(
.INIT ( 1'b0 ))
\blk000001b7/blk000001c2 (
.C(clk),
.CE(sig000000e7),
.D(\blk000001b7/sig0000040d ),
.R(sig000000e9),
.Q(sig000000e1)
);
MUXCY \blk000001b7/blk000001c1 (
.CI(\blk000001b7/sig0000040b ),
.DI(sig000000e4),
.S(\blk000001b7/sig00000410 ),
.O(\blk000001b7/sig00000414 )
);
MUXCY \blk000001b7/blk000001c0 (
.CI(\blk000001b7/sig00000414 ),
.DI(sig000000e3),
.S(\blk000001b7/sig00000417 ),
.O(\blk000001b7/sig00000413 )
);
MUXCY \blk000001b7/blk000001bf (
.CI(\blk000001b7/sig00000413 ),
.DI(sig000000e2),
.S(\blk000001b7/sig00000416 ),
.O(\blk000001b7/sig00000412 )
);
MUXCY \blk000001b7/blk000001be (
.CI(\blk000001b7/sig00000412 ),
.DI(sig000000e1),
.S(\blk000001b7/sig00000415 ),
.O(\blk000001b7/sig00000411 )
);
XORCY \blk000001b7/blk000001bd (
.CI(\blk000001b7/sig00000414 ),
.LI(\blk000001b7/sig00000417 ),
.O(\blk000001b7/sig0000040f )
);
XORCY \blk000001b7/blk000001bc (
.CI(\blk000001b7/sig00000413 ),
.LI(\blk000001b7/sig00000416 ),
.O(\blk000001b7/sig0000040e )
);
XORCY \blk000001b7/blk000001bb (
.CI(\blk000001b7/sig00000412 ),
.LI(\blk000001b7/sig00000415 ),
.O(\blk000001b7/sig0000040d )
);
XORCY \blk000001b7/blk000001ba (
.CI(\blk000001b7/sig00000411 ),
.LI(\blk000001b7/sig0000040b ),
.O(\NLW_blk000001b7/blk000001ba_O_UNCONNECTED )
);
XORCY \blk000001b7/blk000001b9 (
.CI(\blk000001b7/sig0000040b ),
.LI(\blk000001b7/sig00000410 ),
.O(\blk000001b7/sig0000040c )
);
GND \blk000001b7/blk000001b8 (
.G(\blk000001b7/sig0000040b )
);
INV \blk000001ca/blk000001dc (
.I(sig00000055),
.O(\blk000001ca/sig00000428 )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk000001ca/blk000001db (
.I0(sig00000056),
.O(\blk000001ca/sig0000042f )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk000001ca/blk000001da (
.I0(sig00000057),
.O(\blk000001ca/sig0000042e )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk000001ca/blk000001d9 (
.I0(sig000000e5),
.O(\blk000001ca/sig0000042d )
);
FDRE #(
.INIT ( 1'b0 ))
\blk000001ca/blk000001d8 (
.C(clk),
.CE(sig000000e7),
.D(\blk000001ca/sig00000424 ),
.R(sig000000e9),
.Q(sig00000055)
);
FDRE #(
.INIT ( 1'b0 ))
\blk000001ca/blk000001d7 (
.C(clk),
.CE(sig000000e7),
.D(\blk000001ca/sig00000427 ),
.R(sig000000e9),
.Q(sig00000056)
);
FDRE #(
.INIT ( 1'b0 ))
\blk000001ca/blk000001d6 (
.C(clk),
.CE(sig000000e7),
.D(\blk000001ca/sig00000426 ),
.R(sig000000e9),
.Q(sig00000057)
);
FDRE #(
.INIT ( 1'b0 ))
\blk000001ca/blk000001d5 (
.C(clk),
.CE(sig000000e7),
.D(\blk000001ca/sig00000425 ),
.R(sig000000e9),
.Q(sig000000e5)
);
MUXCY \blk000001ca/blk000001d4 (
.CI(\blk000001ca/sig00000423 ),
.DI(sig00000055),
.S(\blk000001ca/sig00000428 ),
.O(\blk000001ca/sig0000042c )
);
MUXCY \blk000001ca/blk000001d3 (
.CI(\blk000001ca/sig0000042c ),
.DI(sig00000056),
.S(\blk000001ca/sig0000042f ),
.O(\blk000001ca/sig0000042b )
);
MUXCY \blk000001ca/blk000001d2 (
.CI(\blk000001ca/sig0000042b ),
.DI(sig00000057),
.S(\blk000001ca/sig0000042e ),
.O(\blk000001ca/sig0000042a )
);
MUXCY \blk000001ca/blk000001d1 (
.CI(\blk000001ca/sig0000042a ),
.DI(sig000000e5),
.S(\blk000001ca/sig0000042d ),
.O(\blk000001ca/sig00000429 )
);
XORCY \blk000001ca/blk000001d0 (
.CI(\blk000001ca/sig0000042c ),
.LI(\blk000001ca/sig0000042f ),
.O(\blk000001ca/sig00000427 )
);
XORCY \blk000001ca/blk000001cf (
.CI(\blk000001ca/sig0000042b ),
.LI(\blk000001ca/sig0000042e ),
.O(\blk000001ca/sig00000426 )
);
XORCY \blk000001ca/blk000001ce (
.CI(\blk000001ca/sig0000042a ),
.LI(\blk000001ca/sig0000042d ),
.O(\blk000001ca/sig00000425 )
);
XORCY \blk000001ca/blk000001cd (
.CI(\blk000001ca/sig00000429 ),
.LI(\blk000001ca/sig00000423 ),
.O(\NLW_blk000001ca/blk000001cd_O_UNCONNECTED )
);
XORCY \blk000001ca/blk000001cc (
.CI(\blk000001ca/sig00000423 ),
.LI(\blk000001ca/sig00000428 ),
.O(\blk000001ca/sig00000424 )
);
GND \blk000001ca/blk000001cb (
.G(\blk000001ca/sig00000423 )
);
INV \blk000001e5/blk00000219 (
.I(sig0000014d),
.O(\blk000001e5/sig00000471 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk000001e5/blk00000218 (
.I0(sig00000166),
.I1(sig00000159),
.I2(sig0000014d),
.O(\blk000001e5/sig00000472 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk000001e5/blk00000217 (
.I0(sig00000163),
.I1(sig00000158),
.I2(sig0000014d),
.O(\blk000001e5/sig0000045a )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000001e5/blk00000216 (
.I0(sig00000162),
.I1(sig0000014d),
.O(\blk000001e5/sig0000045b )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000001e5/blk00000215 (
.I0(sig00000161),
.I1(sig0000014d),
.O(\blk000001e5/sig0000045c )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000001e5/blk00000214 (
.I0(sig00000160),
.I1(sig0000014d),
.O(\blk000001e5/sig0000045d )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000001e5/blk00000213 (
.I0(sig0000015f),
.I1(sig0000014d),
.O(\blk000001e5/sig0000045e )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000001e5/blk00000212 (
.I0(sig0000015e),
.I1(sig0000014d),
.O(\blk000001e5/sig0000045f )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000001e5/blk00000211 (
.I0(sig0000015d),
.I1(sig0000014d),
.O(\blk000001e5/sig00000460 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000001e5/blk00000210 (
.I0(sig0000015c),
.I1(sig0000014d),
.O(\blk000001e5/sig00000461 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000001e5/blk0000020f (
.I0(sig0000015b),
.I1(sig0000014d),
.O(\blk000001e5/sig00000462 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk000001e5/blk0000020e (
.I0(sig00000166),
.I1(sig00000159),
.I2(sig0000014d),
.O(\blk000001e5/sig00000457 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk000001e5/blk0000020d (
.I0(sig00000165),
.I1(sig00000159),
.I2(sig0000014d),
.O(\blk000001e5/sig00000458 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk000001e5/blk0000020c (
.I0(sig00000164),
.I1(sig00000159),
.I2(sig0000014d),
.O(\blk000001e5/sig00000459 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk000001e5/blk0000020b (
.I0(sig0000015a),
.I1(sig0000014d),
.O(\blk000001e5/sig00000463 )
);
FD #(
.INIT ( 1'b0 ))
\blk000001e5/blk0000020a (
.C(clk),
.D(\blk000001e5/sig00000456 ),
.Q(sig0000014e)
);
FD #(
.INIT ( 1'b0 ))
\blk000001e5/blk00000209 (
.C(clk),
.D(\blk000001e5/sig00000455 ),
.Q(sig0000014f)
);
FD #(
.INIT ( 1'b0 ))
\blk000001e5/blk00000208 (
.C(clk),
.D(\blk000001e5/sig00000454 ),
.Q(sig00000150)
);
FD #(
.INIT ( 1'b0 ))
\blk000001e5/blk00000207 (
.C(clk),
.D(\blk000001e5/sig00000453 ),
.Q(sig00000151)
);
FD #(
.INIT ( 1'b0 ))
\blk000001e5/blk00000206 (
.C(clk),
.D(\blk000001e5/sig00000452 ),
.Q(sig00000152)
);
FD #(
.INIT ( 1'b0 ))
\blk000001e5/blk00000205 (
.C(clk),
.D(\blk000001e5/sig00000451 ),
.Q(sig00000153)
);
FD #(
.INIT ( 1'b0 ))
\blk000001e5/blk00000204 (
.C(clk),
.D(\blk000001e5/sig00000450 ),
.Q(sig00000154)
);
FD #(
.INIT ( 1'b0 ))
\blk000001e5/blk00000203 (
.C(clk),
.D(\blk000001e5/sig0000044f ),
.Q(sig00000155)
);
FD #(
.INIT ( 1'b0 ))
\blk000001e5/blk00000202 (
.C(clk),
.D(\blk000001e5/sig0000044e ),
.Q(sig00000156)
);
FD #(
.INIT ( 1'b0 ))
\blk000001e5/blk00000201 (
.C(clk),
.D(\blk000001e5/sig0000044d ),
.Q(sig00000157)
);
MUXCY \blk000001e5/blk00000200 (
.CI(\blk000001e5/sig00000471 ),
.DI(sig0000015a),
.S(\blk000001e5/sig00000463 ),
.O(\blk000001e5/sig00000470 )
);
MUXCY \blk000001e5/blk000001ff (
.CI(\blk000001e5/sig00000470 ),
.DI(sig0000015b),
.S(\blk000001e5/sig00000462 ),
.O(\blk000001e5/sig0000046f )
);
MUXCY \blk000001e5/blk000001fe (
.CI(\blk000001e5/sig0000046f ),
.DI(sig0000015c),
.S(\blk000001e5/sig00000461 ),
.O(\blk000001e5/sig0000046e )
);
MUXCY \blk000001e5/blk000001fd (
.CI(\blk000001e5/sig0000046e ),
.DI(sig0000015d),
.S(\blk000001e5/sig00000460 ),
.O(\blk000001e5/sig0000046d )
);
MUXCY \blk000001e5/blk000001fc (
.CI(\blk000001e5/sig0000046d ),
.DI(sig0000015e),
.S(\blk000001e5/sig0000045f ),
.O(\blk000001e5/sig0000046c )
);
MUXCY \blk000001e5/blk000001fb (
.CI(\blk000001e5/sig0000046c ),
.DI(sig0000015f),
.S(\blk000001e5/sig0000045e ),
.O(\blk000001e5/sig0000046b )
);
MUXCY \blk000001e5/blk000001fa (
.CI(\blk000001e5/sig0000046b ),
.DI(sig00000160),
.S(\blk000001e5/sig0000045d ),
.O(\blk000001e5/sig0000046a )
);
MUXCY \blk000001e5/blk000001f9 (
.CI(\blk000001e5/sig0000046a ),
.DI(sig00000161),
.S(\blk000001e5/sig0000045c ),
.O(\blk000001e5/sig00000469 )
);
MUXCY \blk000001e5/blk000001f8 (
.CI(\blk000001e5/sig00000469 ),
.DI(sig00000162),
.S(\blk000001e5/sig0000045b ),
.O(\blk000001e5/sig00000468 )
);
MUXCY \blk000001e5/blk000001f7 (
.CI(\blk000001e5/sig00000468 ),
.DI(sig00000163),
.S(\blk000001e5/sig0000045a ),
.O(\blk000001e5/sig00000467 )
);
MUXCY \blk000001e5/blk000001f6 (
.CI(\blk000001e5/sig00000467 ),
.DI(sig00000164),
.S(\blk000001e5/sig00000459 ),
.O(\blk000001e5/sig00000466 )
);
MUXCY \blk000001e5/blk000001f5 (
.CI(\blk000001e5/sig00000466 ),
.DI(sig00000165),
.S(\blk000001e5/sig00000458 ),
.O(\blk000001e5/sig00000465 )
);
MUXCY \blk000001e5/blk000001f4 (
.CI(\blk000001e5/sig00000465 ),
.DI(sig00000166),
.S(\blk000001e5/sig00000472 ),
.O(\blk000001e5/sig00000464 )
);
XORCY \blk000001e5/blk000001f3 (
.CI(\blk000001e5/sig00000471 ),
.LI(\blk000001e5/sig00000463 ),
.O(\NLW_blk000001e5/blk000001f3_O_UNCONNECTED )
);
XORCY \blk000001e5/blk000001f2 (
.CI(\blk000001e5/sig00000470 ),
.LI(\blk000001e5/sig00000462 ),
.O(\NLW_blk000001e5/blk000001f2_O_UNCONNECTED )
);
XORCY \blk000001e5/blk000001f1 (
.CI(\blk000001e5/sig0000046f ),
.LI(\blk000001e5/sig00000461 ),
.O(\NLW_blk000001e5/blk000001f1_O_UNCONNECTED )
);
XORCY \blk000001e5/blk000001f0 (
.CI(\blk000001e5/sig0000046e ),
.LI(\blk000001e5/sig00000460 ),
.O(\blk000001e5/sig00000456 )
);
XORCY \blk000001e5/blk000001ef (
.CI(\blk000001e5/sig0000046d ),
.LI(\blk000001e5/sig0000045f ),
.O(\blk000001e5/sig00000455 )
);
XORCY \blk000001e5/blk000001ee (
.CI(\blk000001e5/sig0000046c ),
.LI(\blk000001e5/sig0000045e ),
.O(\blk000001e5/sig00000454 )
);
XORCY \blk000001e5/blk000001ed (
.CI(\blk000001e5/sig0000046b ),
.LI(\blk000001e5/sig0000045d ),
.O(\blk000001e5/sig00000453 )
);
XORCY \blk000001e5/blk000001ec (
.CI(\blk000001e5/sig0000046a ),
.LI(\blk000001e5/sig0000045c ),
.O(\blk000001e5/sig00000452 )
);
XORCY \blk000001e5/blk000001eb (
.CI(\blk000001e5/sig00000469 ),
.LI(\blk000001e5/sig0000045b ),
.O(\blk000001e5/sig00000451 )
);
XORCY \blk000001e5/blk000001ea (
.CI(\blk000001e5/sig00000468 ),
.LI(\blk000001e5/sig0000045a ),
.O(\blk000001e5/sig00000450 )
);
XORCY \blk000001e5/blk000001e9 (
.CI(\blk000001e5/sig00000467 ),
.LI(\blk000001e5/sig00000459 ),
.O(\blk000001e5/sig0000044f )
);
XORCY \blk000001e5/blk000001e8 (
.CI(\blk000001e5/sig00000466 ),
.LI(\blk000001e5/sig00000458 ),
.O(\blk000001e5/sig0000044e )
);
XORCY \blk000001e5/blk000001e7 (
.CI(\blk000001e5/sig00000465 ),
.LI(\blk000001e5/sig00000472 ),
.O(\blk000001e5/sig0000044d )
);
XORCY \blk000001e5/blk000001e6 (
.CI(\blk000001e5/sig00000464 ),
.LI(\blk000001e5/sig00000457 ),
.O(\NLW_blk000001e5/blk000001e6_O_UNCONNECTED )
);
FD #(
.INIT ( 1'b0 ))
\blk0000029a/blk000002a6 (
.C(clk),
.D(sig0000011d),
.Q(sig0000011e)
);
FD #(
.INIT ( 1'b0 ))
\blk0000029a/blk000002a5 (
.C(clk),
.D(sig0000011c),
.Q(sig0000011f)
);
FD #(
.INIT ( 1'b0 ))
\blk0000029a/blk000002a4 (
.C(clk),
.D(sig0000011c),
.Q(sig00000120)
);
FD #(
.INIT ( 1'b0 ))
\blk0000029a/blk000002a3 (
.C(clk),
.D(sig0000011d),
.Q(sig00000121)
);
FD #(
.INIT ( 1'b0 ))
\blk0000029a/blk000002a2 (
.C(clk),
.D(sig0000011c),
.Q(sig00000122)
);
FD #(
.INIT ( 1'b0 ))
\blk0000029a/blk000002a1 (
.C(clk),
.D(sig0000011c),
.Q(sig00000123)
);
FD #(
.INIT ( 1'b0 ))
\blk0000029a/blk000002a0 (
.C(clk),
.D(sig0000011d),
.Q(sig00000124)
);
FD #(
.INIT ( 1'b0 ))
\blk0000029a/blk0000029f (
.C(clk),
.D(sig0000011c),
.Q(sig00000125)
);
FD #(
.INIT ( 1'b0 ))
\blk0000029a/blk0000029e (
.C(clk),
.D(sig0000011c),
.Q(sig00000126)
);
FD #(
.INIT ( 1'b0 ))
\blk0000029a/blk0000029d (
.C(clk),
.D(sig0000011c),
.Q(sig00000127)
);
FD #(
.INIT ( 1'b0 ))
\blk0000029a/blk0000029c (
.C(clk),
.D(sig0000011c),
.Q(sig00000128)
);
FD #(
.INIT ( 1'b0 ))
\blk0000029a/blk0000029b (
.C(clk),
.D(sig0000011d),
.Q(sig00000129)
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
// ----------------------------
// This module impelements a linear feedback shift register (lfsr).
//
// Note:
// - Syntax works and compiles with Verilog2LPN compiler
// - async. design follows dual rail encoding that maps
// input to output and output to internal states
//
// author: Tramy Nguyen
// ----------------------------
module lfsr_imp (req, ack, a0, a1, b0, b1, c0, c1);
input req;
output reg ack, a0, a1, b0, b1, c0, c1;
reg feedback, state0, state1;
initial begin
a0 = 1'b0;
b0 = 1'b0;
c0 = 1'b0;
a1 = 1'b0;
b1 = 1'b0;
c1 = 1'b0;
ack = 1'b0;
feedback = 1'b0;
state0 = 1'b0;
state1 = 1'b0;
end
always begin
// input to output
wait(req == 1'b1) #5;
if(state0 != 1'b1 && state1 != 1'b1 && feedback != 1'b1) begin
#5 a0 = 1'b1;
#5 b0 = 1'b1;
#5 c0 = 1'b1;
#5 ack = 1'b1;
end
else if(state0 != 1'b1 && state1 != 1'b1 && feedback == 1'b1) begin
#5 a0 = 1'b1;
#5 b0 = 1'b1;
#5 c1 = 1'b1;
#5 ack = 1'b1;
end
else if(state0 != 1'b1 && state1 == 1'b1 && feedback != 1'b1) begin
#5 a0 = 1'b1;
#5 b1 = 1'b1;
#5 c0 = 1'b1;
#5 ack = 1'b1;
end
else if(state0 != 1'b1 && state1 == 1'b1 && feedback == 1'b1) begin
#5 a0 = 1'b1;
#5 b1 = 1'b1;
#5 c1 = 1'b1;
#5 ack = 1'b1;
end
else if(state0 == 1'b1 && state1 != 1'b1 && feedback != 1'b1) begin
#5 a1 = 1'b1;
#5 b0 = 1'b1;
#5 c0 = 1'b1;
#5 ack = 1'b1;
end
else if(state0 == 1'b1 && state1 != 1'b1 && feedback == 1'b1) begin
#5 a1 = 1'b1;
#5 b0 = 1'b1;
#5 c1 = 1'b1;
#5 ack = 1'b1;
end
else if(state0 == 1'b1 && state1 == 1'b1 && feedback != 1'b1) begin
#5 a1 = 1'b1;
#5 b1 = 1'b1;
#5 c0 = 1'b1;
#5 ack = 1'b1;
end
else if(state0 == 1'b1 && state1 == 1'b1 && feedback == 1'b1) begin
#5 a1 = 1'b1;
#5 b1 = 1'b1;
#5 c1 = 1'b1;
#5 ack = 1'b1;
end
// output to states
if(a0 == 1'b1 && b0 == 1'b1 && c0 == 1'b1) begin
state0 = 1'b0;
state1 = 1'b0;
feedback = 1'b1;
end
else if(a0 == 1'b1 && b1 == 1'b1 && c0 == 1'b1) begin
state0 = 1'b1;
state1 = 1'b0;
feedback = 1'b0;
end
else if(a1 == 1'b1 && b0 == 1'b1 && c0 == 1'b1) begin
state0 = 1'b0;
state1 = 1'b0;
feedback = 1'b0;
end
else if(a1 == 1'b1 && b1 == 1'b1 && c0 == 1'b1) begin
state0 = 1'b1;
state1 = 1'b0;
feedback = 1'b1;
end
else if(a0 == 1'b1 && b0 == 1'b1 && c1 == 1'b1) begin
state0 = 1'b0;
state1 = 1'b1;
feedback = 1'b1;
end
else if(a0 == 1'b1 && b1 == 1'b1 && c1 == 1'b1) begin
state0 = 1'b1;
state1 = 1'b1;
feedback = 1'b0;
end
else if(a1 == 1'b1 && b0 == 1'b1 && c1 == 1'b1) begin
state0 = 1'b0;
state1 = 1'b1;
feedback = 1'b0;
end
else if(a1 == 1'b1 && b1 == 1'b1 && c1 == 1'b1) begin
state0 = 1'b1;
state1 = 1'b1;
feedback = 1'b1;
end
//stabilize signals
wait((a0 == 1'b1 && b0 == 1'b1 && c0 == 1'b1 && state0 != 1'b1 && state1 != 1'b1 && feedback == 1'b1) ||
(a0 == 1'b1 && b1 == 1'b1 && c0 == 1'b1 && state0 == 1'b1 && state1 != 1'b1 && feedback != 1'b1) ||
(a1 == 1'b1 && b0 == 1'b1 && c0 == 1'b1 && state0 != 1'b1 && state1 != 1'b1 && feedback != 1'b1) ||
(a1 == 1'b1 && b1 == 1'b1 && c0 == 1'b1 && state0 == 1'b1 && state1 != 1'b1 && feedback == 1'b1) ||
(a0 == 1'b1 && b0 == 1'b1 && c1 == 1'b1 && state0 != 1'b1 && state1 == 1'b1 && feedback == 1'b1) ||
(a0 == 1'b1 && b1 == 1'b1 && c1 == 1'b1 && state0 == 1'b1 && state1 == 1'b1 && feedback != 1'b1) ||
(a1 == 1'b1 && b0 == 1'b1 && c1 == 1'b1 && state0 != 1'b1 && state1 == 1'b1 && feedback != 1'b1) ||
(a1 == 1'b1 && b1 == 1'b1 && c1 == 1'b1 && state0 == 1'b1 && state1 == 1'b1 && feedback == 1'b1)) #5;
// reset
wait(req != 1'b1) #5;
if(a0 == 1'b1) begin
#5 a0 = 1'b0;
end
if(a1 == 1'b1) begin
#5 a1 = 1'b0;
end
if(b0 == 1'b1) begin
#5 b0 = 1'b0;
end
if(b1 == 1'b1) begin
#5 b1 = 1'b0;
end
if(c0 == 1'b1) begin
#5 c0 = 1'b0;
end
if(c1 == 1'b1) begin
#5 c1 = 1'b0;
end
#5 ack = 1'b0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_PP_SYMBOL_V
/**
* lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer, vpb/vnb
* taps, double-row-height cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input LOWLVPWR,
input VPB ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_PP_SYMBOL_V
|
/*
Simple 8n1 UART receiver with 16-deep receive buffer.
Estimated Resource Usage:
Spartan 6: 24 Regs, 20 LUTs, 4 LUTRAMs
*/
///////////////////////////////////////////////////////////////////////////
// MODULE DECLARATION
///////////////////////////////////////////////////////////////////////////
module RxUart #(
parameter LOG2_DEPTH = 4 ///< log2(depth of FIFO). Must be an integer
)
(
input clk, ///< System clock
input rst, ///< Reset FIFO
input x16BaudStrobe, ///< Strobe at 16x baud rate
input read, ///< Read strobe for buffer
input serialIn, ///< Serial Receive
output wire [7:0] dataOut, ///< Data from receive buffer
output wire dataPresent, ///< Receive buffer not empty
output wire halfFull, ///< Receive buffer half full
output wire full ///< Receive buffer full
);
///////////////////////////////////////////////////////////////////////////
// SIGNAL DECLARATIONS
///////////////////////////////////////////////////////////////////////////
reg [7:0] data;
reg [7:0] dataOutReg; // Only used if no fifo is present
reg [3:0] div;
reg dataOutReady; // Only used if no fifo is present
reg sampleStrobe;
reg sample;
reg sampleD1;
reg write;
reg run;
reg startBit;
reg stopBit;
///////////////////////////////////////////////////////////////////////////
// MAIN CODE
///////////////////////////////////////////////////////////////////////////
if (LOG2_DEPTH > 0) begin
Fifo #(
.WIDTH(8), ///< Width of data word
.LOG2_DEPTH(LOG2_DEPTH) ///< log2(depth of FIFO). Must be an integer
)
rxFifo (
.clk(clk), ///< System clock
.rst(rst), ///< Reset FIFO pointer
.write(write), ///< Write strobe (1 clk)
.read(read), ///< Read strobe (1 clk)
.dataIn(data), ///< [7:0] Data to write
// Outputs
.dataOut(dataOut), ///< [7:0] Data from FIFO
.dataPresent(dataPresent), ///< Data is present in FIFO
.halfFull(halfFull), ///< FIFO is half full
.full(full) ///< FIFO is full
);
end
else begin
// Create a simple rxReady bit and register received data
assign dataOut = dataOutReg;
assign dataPresent = dataOutReady;
assign halfFull = dataOutReady;
assign full = dataOutReady;
always @(posedge clk) begin
if (write) begin
dataOutReg <= data;
end
dataOutReady <= dataOutReady ? (dataOutReady & ~read) : write;
end
end
initial begin
dataOutReg = 8'hFF;
dataOutReady = 1'b0;
data = 8'hFF;
div = 4'd0;
sampleStrobe = 1'b0;
sample = 1'b1;
sampleD1 = 1'b1;
write = 1'b0;
run = 1'b0;
startBit = 1'b0;
stopBit = 1'b1;
end
always @(posedge clk) begin
sampleStrobe <= x16BaudStrobe & (div[3:0] == 4'b0111);
if (x16BaudStrobe) begin
sample <= serialIn;
sampleD1 <= sample;
end
write <= sampleStrobe & ~data[0];
if (sampleStrobe) begin
{stopBit, data} <= {sample, data[7:1]};
end
if (run) begin
run <= ~sampleStrobe | sampleStrobe & data[0] & (~sample | sample & ~startBit);
startBit <= startBit & ~sampleStrobe; // Keep asserted while sampleStrobe is low
div <= (x16BaudStrobe) ? div + 4'd1 : div;
end
else begin
run <= ~sample & sampleD1;
startBit <= ~sample & sampleD1; // Start is falling edge of serialIn
div <= 4'd0;
stopBit <= 1'b1;
data <= 8'hFF;
end
end
endmodule
|
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