text
stringlengths 938
1.05M
|
|---|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.0
// Ultra-Embedded.com
// Copyright 2011 - 2013
//
// Email: [email protected]
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module top
(
// Clocking & Reset
input clk_i,
input rst_i,
// Fault Output
output fault_o,
// Break Output
output break_o,
// Interrupt Input
input intr_i
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter CLK_KHZ = 8192;
parameter BOOT_VECTOR = 32'h10000000;
parameter ISR_VECTOR = 32'h10000000;
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [31:0] soc_addr;
wire [31:0] soc_data_w;
wire [31:0] soc_data_r;
wire soc_we;
wire soc_stb;
wire soc_ack;
wire soc_irq;
wire[31:0] dmem_address;
wire[31:0] dmem_data_w;
wire[31:0] dmem_data_r;
wire[3:0] dmem_sel;
wire[2:0] dmem_cti;
wire dmem_we;
wire dmem_stb;
wire dmem_cyc;
wire dmem_stall;
wire dmem_ack;
wire[31:0] imem_addr;
wire[31:0] imem_data;
wire[3:0] imem_sel;
wire imem_stb;
wire imem_cyc;
wire[2:0] imem_cti;
wire imem_stall;
wire imem_ack;
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
ram
u_ram
(
.clka_i(clk_i),
.rsta_i(rst_i),
.stba_i(imem_stb),
.wea_i(1'b0),
.sela_i(imem_sel),
.addra_i(imem_addr[31:2]),
.dataa_i(32'b0),
.dataa_o(imem_data),
.acka_o(imem_ack),
.clkb_i(clk_i),
.rstb_i(rst_i),
.stbb_i(dmem_stb),
.web_i(dmem_we),
.selb_i(dmem_sel),
.addrb_i(dmem_address[31:2]),
.datab_i(dmem_data_w),
.datab_o(dmem_data_r),
.ackb_o(dmem_ack)
);
cpu_if
#(
.CLK_KHZ(CLK_KHZ),
.BOOT_VECTOR(32'h10000000),
.ISR_VECTOR(32'h10000000),
.ENABLE_ICACHE(`ICACHE_ENABLED),
.ENABLE_DCACHE(`DCACHE_ENABLED),
.REGISTER_FILE_TYPE("SIMULATION")
)
u_cpu
(
// General - clocking & reset
.clk_i(clk_i),
.rst_i(rst_i),
.fault_o(fault_o),
.break_o(break_o),
.nmi_i(1'b0),
.intr_i(soc_irq),
// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
.imem0_addr_o(imem_addr),
.imem0_data_i(imem_data),
.imem0_sel_o(imem_sel),
.imem0_cti_o(imem_cti),
.imem0_cyc_o(imem_cyc),
.imem0_stb_o(imem_stb),
.imem0_stall_i(1'b0),
.imem0_ack_i(imem_ack),
// Data Memory 0 (0x10000000 - 0x10FFFFFF)
.dmem0_addr_o(dmem_address),
.dmem0_data_o(dmem_data_w),
.dmem0_data_i(dmem_data_r),
.dmem0_sel_o(dmem_sel),
.dmem0_cti_o(dmem_cti),
.dmem0_cyc_o(dmem_cyc),
.dmem0_we_o(dmem_we),
.dmem0_stb_o(dmem_stb),
.dmem0_stall_i(1'b0),
.dmem0_ack_i(dmem_ack),
// Data Memory 1 (0x11000000 - 0x11FFFFFF)
.dmem1_addr_o(/*open*/),
.dmem1_data_o(/*open*/),
.dmem1_data_i(32'b0),
.dmem1_sel_o(/*open*/),
.dmem1_we_o(/*open*/),
.dmem1_stb_o(/*open*/),
.dmem1_cyc_o(/*open*/),
.dmem1_cti_o(/*open*/),
.dmem1_stall_i(1'b0),
.dmem1_ack_i(1'b1),
// Data Memory 2 (0x12000000 - 0x12FFFFFF)
.dmem2_addr_o(soc_addr),
.dmem2_data_o(soc_data_w),
.dmem2_data_i(soc_data_r),
.dmem2_sel_o(/*open*/),
.dmem2_we_o(soc_we),
.dmem2_stb_o(soc_stb),
.dmem2_cyc_o(/*open*/),
.dmem2_cti_o(/*open*/),
.dmem2_stall_i(1'b0),
.dmem2_ack_i(soc_ack)
);
// CPU SOC
soc
#(
.CLK_KHZ(CLK_KHZ),
.ENABLE_SYSTICK_TIMER("ENABLED"),
.ENABLE_HIGHRES_TIMER("ENABLED"),
.EXTERNAL_INTERRUPTS(1)
)
u_soc
(
// General - clocking & reset
.clk_i(clk_i),
.rst_i(rst_i),
.ext_intr_i(1'b0),
.intr_o(soc_irq),
// Memory Port
.io_addr_i(soc_addr),
.io_data_i(soc_data_w),
.io_data_o(soc_data_r),
.io_we_i(soc_we),
.io_stb_i(soc_stb),
.io_ack_o(soc_ack)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOLATCH_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__ISOLATCH_FUNCTIONAL_PP_V
/**
* isolatch: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_isolatch_pp_pkg_sn/sky130_fd_sc_lp__udp_isolatch_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__isolatch (
Q ,
D ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SLEEP_B_delayed;
wire D_delayed ;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_isolatch_pp$PKG$sN `UNIT_DELAY isolatch_pp0 (buf_Q , D, SLEEP_B, , KAPWR, VGND, VPWR);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOLATCH_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21O_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A21O_PP_BLACKBOX_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21O_PP_BLACKBOX_V
|
//wishbone master interconnect testbench
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/* Log
04/16/2013
-implement naming convention
08/30/2012
-Major overhall of the testbench
-modfied the way reads and writes happen, now each write requires the
number of 32-bit data packets even if the user sends only 1
-there is no more streaming as the data_count will implicity declare
that a read/write is streaming
-added the ih_reset which has not been formally defined within the
system, but will more than likely reset the entire statemachine
11/12/2011
-overhauled the design to behave more similar to a real I/O handler
-changed the timeout to 40 seconds to allow the wishbone master to catch
nacks
11/08/2011
-added interrupt support
*/
`timescale 1 ns/1 ps
`define TIMEOUT_COUNT 40
`define INPUT_FILE "sim/master_input_test_data.txt"
`define OUTPUT_FILE "sim/master_output_test_data.txt"
`define CLK_HALF_PERIOD 10
`define CLK_PERIOD (2 * `CLK_HALF_PERIOD)
`define SLEEP_HALF_CLK #(`CLK_HALF_PERIOD)
`define SLEEP_FULL_CLK #(`CLK_PERIOD)
//Sleep a number of clock cycles
`define SLEEP_CLK(x) #(x * `CLK_PERIOD)
//`define VERBOSE
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbp_we;
wire w_wbp_cyc;
wire w_wbp_stb;
wire [3:0] w_wbp_sel;
wire [31:0] w_wbp_adr;
wire [31:0] w_wbp_dat_o;
wire [31:0] w_wbp_dat_i;
wire w_wbp_ack;
wire w_wbp_int;
//Wishbone master mem bus
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (DRT) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//wishbone slave 0 signals
wire mem0_we_o;
wire mem0_cyc_o;
wire [31:0] mem0_dat_o;
wire mem0_stb_o;
wire [3:0] mem0_sel_o;
wire mem0_ack_i;
wire [31:0] mem0_dat_i;
wire [31:0] mem0_adr_o;
wire mem0_int_i;
wire w_arb0_i_wbs_stb;
wire w_arb0_i_wbs_cyc;
wire w_arb0_i_wbs_we;
wire [3:0] w_arb0_i_wbs_sel;
wire [31:0] w_arb0_i_wbs_dat;
wire [31:0] w_arb0_o_wbs_dat;
wire [31:0] w_arb0_i_wbs_adr;
wire w_arb0_o_wbs_ack;
wire w_arb0_o_wbs_int;
wire vga_mem_o_stb;
wire vga_mem_o_cyc;
wire vga_mem_o_we;
wire [3:0] vga_mem_o_sel;
wire [31:0] vga_mem_o_dat;
wire [31:0] vga_mem_o_adr;
wire [31:0] vga_mem_i_dat;
wire vga_mem_i_ack;
wire vga_mem_i_int;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
//mem slave 0
wire w_sm0_i_wbs_we;
wire w_sm0_i_wbs_cyc;
wire [31:0] w_sm0_i_wbs_dat;
wire [31:0] w_sm0_o_wbs_dat;
wire [31:0] w_sm0_i_wbs_adr;
wire w_sm0_i_wbs_stb;
wire [3:0] w_sm0_i_wbs_sel;
wire w_sm0_o_wbs_ack;
wire w_sm0_o_wbs_int;
wire w_mem_we_o;
wire w_mem_cyc_o;
wire w_mem_stb_o;
wire [3:0] w_mem_sel_o;
wire [31:0] w_mem_adr_o;
wire [31:0] w_mem_dat_i;
wire [31:0] w_mem_dat_o;
wire w_mem_ack_i;
wire w_mem_int_i;
wire w_cam_rst;
wire w_flash;
wire w_cam_in_clk;
wire w_pix_clk;
wire w_flash_strobe;
wire w_vsync;
wire w_hsync;
wire [7:0] w_pix_data;
wire start;
assign w_wbs0_int = 0;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbp_we ),
.o_per_adr (w_wbp_adr ),
.o_per_dat (w_wbp_dat_i ),
.i_per_dat (w_wbp_dat_o ),
.o_per_stb (w_wbp_stb ),
.o_per_cyc (w_wbp_cyc ),
.o_per_sel (w_wbp_sel ),
.i_per_ack (w_wbp_ack ),
.i_per_int (w_wbp_int ),
//memory interconnect signals
.o_mem_we (w_mem_we_o ),
.o_mem_adr (w_mem_adr_o ),
.o_mem_dat (w_mem_dat_o ),
.i_mem_dat (w_mem_dat_i ),
.o_mem_stb (w_mem_stb_o ),
.o_mem_cyc (w_mem_cyc_o ),
.o_mem_sel (w_mem_sel_o ),
.i_mem_ack (w_mem_ack_i ),
.i_mem_int (w_mem_int_i )
);
//slave 1
wb_fpga_nes s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int ),
.mem_o_cyc (vga_mem_o_cyc ),
.mem_o_stb (vga_mem_o_stb ),
.mem_o_we (vga_mem_o_we ),
.mem_i_ack (vga_mem_i_ack ),
.mem_o_sel (vga_mem_o_sel ),
.mem_o_adr (vga_mem_o_adr ),
.mem_o_dat (vga_mem_o_dat ),
.mem_i_dat (vga_mem_i_dat ),
.mem_i_int (vga_mem_i_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbp_we ),
.i_m_cyc (w_wbp_cyc ),
.i_m_stb (w_wbp_stb ),
.o_m_ack (w_wbp_ack ),
.i_m_dat (w_wbp_dat_i ),
.o_m_dat (w_wbp_dat_o ),
.i_m_adr (w_wbp_adr ),
.o_m_int (w_wbp_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
wishbone_mem_interconnect wmi (
.clk (clk ),
.rst (rst ),
//master
.i_m_we (w_mem_we_o ),
.i_m_cyc (w_mem_cyc_o ),
.i_m_stb (w_mem_stb_o ),
.i_m_sel (w_mem_sel_o ),
.o_m_ack (w_mem_ack_i ),
.i_m_dat (w_mem_dat_o ),
.o_m_dat (w_mem_dat_i ),
.i_m_adr (w_mem_adr_o ),
.o_m_int (w_mem_int_i ),
//slave 0
.o_s0_we (w_sm0_i_wbs_we ),
.o_s0_cyc (w_sm0_i_wbs_cyc ),
.o_s0_stb (w_sm0_i_wbs_stb ),
.o_s0_sel (w_sm0_i_wbs_sel ),
.i_s0_ack (w_sm0_o_wbs_ack ),
.o_s0_dat (w_sm0_i_wbs_dat ),
.i_s0_dat (w_sm0_o_wbs_dat ),
.o_s0_adr (w_sm0_i_wbs_adr ),
.i_s0_int (w_sm0_o_wbs_int )
);
//mem 0
wb_bram m0 (
.clk(clk),
.rst(rst),
.i_wbs_cyc (w_arb0_i_wbs_cyc ),
.i_wbs_dat (w_arb0_i_wbs_dat ),
.i_wbs_we (w_arb0_i_wbs_we ),
.i_wbs_stb (w_arb0_i_wbs_stb ),
.i_wbs_sel (w_arb0_i_wbs_sel ),
.i_wbs_adr (w_arb0_i_wbs_adr ),
.o_wbs_dat (w_arb0_o_wbs_dat ),
.o_wbs_ack (w_arb0_o_wbs_ack ),
.o_wbs_int (w_arb0_o_wbs_int )
);
arbiter_2_masters arb0 (
.clk (clk ),
.rst (rst ),
//masters
.i_m0_we (vga_mem_o_we ),
.i_m0_stb (vga_mem_o_stb ),
.i_m0_cyc (vga_mem_o_cyc ),
.i_m0_sel (vga_mem_o_sel ),
.i_m0_dat (vga_mem_o_dat ),
.i_m0_adr (vga_mem_o_adr ),
.o_m0_dat (vga_mem_i_dat ),
.o_m0_ack (vga_mem_i_ack ),
.o_m0_int (vga_mem_i_int ),
.i_m1_we (w_sm0_i_wbs_we ),
.i_m1_stb (w_sm0_i_wbs_stb ),
.i_m1_cyc (w_sm0_i_wbs_cyc ),
.i_m1_sel (w_sm0_i_wbs_sel ),
.i_m1_dat (w_sm0_i_wbs_dat ),
.i_m1_adr (w_sm0_i_wbs_adr ),
.o_m1_dat (w_sm0_o_wbs_dat ),
.o_m1_ack (w_sm0_o_wbs_ack ),
.o_m1_int (w_sm0_o_wbs_int ),
//slave
.o_s_we (w_arb0_i_wbs_we ),
.o_s_stb (w_arb0_i_wbs_stb ),
.o_s_cyc (w_arb0_i_wbs_cyc ),
.o_s_sel (w_arb0_i_wbs_sel ),
.o_s_dat (w_arb0_i_wbs_dat ),
.o_s_adr (w_arb0_i_wbs_adr ),
.i_s_dat (w_arb0_o_wbs_dat ),
.i_s_ack (w_arb0_o_wbs_ack ),
.i_s_int (w_arb0_o_wbs_int )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
`ifdef VERBOSE $display (""); `endif
end
else begin
`ifdef VERBOSE $display ("Error unrecognized line: %h" % ch); `endif
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
`ifdef VERBOSE $display ("Sleep for %h Clock cycles", r_in_data_count); `endif
`SLEEP_CLK(r_in_data_count);
`ifdef VERBOSE $display ("Sleep Finished"); `endif
end
else begin
`ifdef VERBOSE $display ("Error: read_count = %h != 4", read_count); `endif
`ifdef VERBOSE $display ("Character: %h", ch); `endif
end
end
else begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
`endif
`ifdef VERBOSE $display ("Execute Command"); `endif
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
`ifdef VERBOSE $display ("TB: reading a new double word: %h", r_in_data); `endif
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
`ifdef VERBOSE $display ("Command Finished"); `endif
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
`ifdef VERBOSE $display ("TB: finished command"); `endif
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
//initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
`endif
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
// `ifdef VERBOSE $display ("TB: sdram is ready"); `endif
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
else begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
`ifdef VERBOSE $display ("TB: Ping Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
`ifdef VERBOSE $display ("In Write Response"); `endif
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
`ifdef VERBOSE $display ("TB: Write Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Write Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
`ifdef VERBOSE $display ("TB: Read Response Good"); `endif
if (w_out_data_count > 0) begin
if (data_read_count < w_out_data_count) begin
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
`ifdef VERBOSE $display ("TB: Read Response Bad (Malformed response: %h)", w_out_status); `endif
state <= FINISHED;
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
`ifdef VERBOSE $display ("TB: Read a 32bit data packet"); `endif
`ifdef VERBOSE $display ("TB: \tRead Data: %h", w_out_data); `endif
data_read_count <= data_read_count + 1;
end
if (data_read_count >= r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
`ifdef VERBOSE $display ("Execute Command is low"); `endif
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
`ifdef VERBOSE $display("TB: Output Handler Recieved interrupt"); `endif
`ifdef VERBOSE $display("TB:\tcommand: %h", w_out_status); `endif
`ifdef VERBOSE $display("TB:\taddress: %h", w_out_address); `endif
`ifdef VERBOSE $display("TB:\tdata: %h", w_out_data); `endif
end
end//not reset
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_dbg.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Top level Module: jbi_dbg
// Where Instantiated: jbi
// Description: Debug Block
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "jbi.h"
module jbi_dbg (/*AUTOARG*/
// Outputs
dbg_req_transparent, dbg_req_arbitrate, dbg_req_priority, dbg_data,
// Inputs
clk, rst_l, dbg_rst_l, hold, testmux_sel, scan_en,
csr_16x65array_margin, csr_jbi_debug_arb_max_wait,
csr_jbi_debug_arb_hi_water, csr_jbi_debug_arb_lo_water,
csr_jbi_debug_arb_data_arb, csr_jbi_debug_arb_tstamp_wrap,
csr_jbi_debug_arb_alternate, csr_jbi_debug_arb_alternate_set_l,
iob_jbi_dbg_hi_data, iob_jbi_dbg_hi_vld, iob_jbi_dbg_lo_data,
iob_jbi_dbg_lo_vld, mout_dbg_pop
);
input clk;
input rst_l;
input dbg_rst_l;
input hold;
input testmux_sel;
input scan_en;
// CSR Interface
input [4:0] csr_16x65array_margin;
input [`JBI_CSR_DBG_MAX_WAIT_WIDTH-1:0] csr_jbi_debug_arb_max_wait;
input [`JBI_CSR_DBG_HI_WATER_WIDTH-1:0] csr_jbi_debug_arb_hi_water;
input [`JBI_CSR_DBG_LO_WATER_WIDTH-1:0] csr_jbi_debug_arb_lo_water;
input csr_jbi_debug_arb_data_arb;
input [`JBI_CSR_DBG_TSWRAP_WIDTH-1:0] csr_jbi_debug_arb_tstamp_wrap;
input csr_jbi_debug_arb_alternate;
input csr_jbi_debug_arb_alternate_set_l;
// IOB Interface.
input [47:0] iob_jbi_dbg_hi_data;
input iob_jbi_dbg_hi_vld;
input [47:0] iob_jbi_dbg_lo_data;
input iob_jbi_dbg_lo_vld;
// Memory Out (mout) Interface
input mout_dbg_pop;
output dbg_req_transparent;
output dbg_req_arbitrate;
output dbg_req_priority;
output [127:0] dbg_data;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire dbgq_hi_csn_rd; // From u_dbg_ctl of jbi_dbg_ctl.v
wire dbgq_hi_csn_wr; // From u_dbg_ctl of jbi_dbg_ctl.v
wire [`JBI_DBGQ_ADDR_WIDTH-1:0]dbgq_hi_raddr; // From u_dbg_ctl of jbi_dbg_ctl.v
wire [`JBI_DBGQ_WIDTH-1:0]dbgq_hi_rdata; // From u_dbg_buf of jbi_dbg_buf.v
wire [`JBI_DBGQ_ADDR_WIDTH-1:0]dbgq_hi_waddr; // From u_dbg_ctl of jbi_dbg_ctl.v
wire [`JBI_DBGQ_WIDTH-1:0]dbgq_hi_wdata; // From u_dbg_ctl of jbi_dbg_ctl.v
wire dbgq_lo_csn_rd; // From u_dbg_ctl of jbi_dbg_ctl.v
wire dbgq_lo_csn_wr; // From u_dbg_ctl of jbi_dbg_ctl.v
wire [`JBI_DBGQ_ADDR_WIDTH-1:0]dbgq_lo_raddr; // From u_dbg_ctl of jbi_dbg_ctl.v
wire [`JBI_DBGQ_WIDTH-1:0]dbgq_lo_rdata; // From u_dbg_buf of jbi_dbg_buf.v
wire [`JBI_DBGQ_ADDR_WIDTH-1:0]dbgq_lo_waddr; // From u_dbg_ctl of jbi_dbg_ctl.v
wire [`JBI_DBGQ_WIDTH-1:0]dbgq_lo_wdata; // From u_dbg_ctl of jbi_dbg_ctl.v
// End of automatics
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
//
// Code start here
//
jbi_dbg_ctl u_dbg_ctl (/*AUTOINST*/
// Outputs
.dbg_req_transparent(dbg_req_transparent),
.dbg_req_arbitrate(dbg_req_arbitrate),
.dbg_req_priority(dbg_req_priority),
.dbg_data (dbg_data[127:0]),
.dbgq_hi_raddr (dbgq_hi_raddr[`JBI_DBGQ_ADDR_WIDTH-1:0]),
.dbgq_hi_waddr (dbgq_hi_waddr[`JBI_DBGQ_ADDR_WIDTH-1:0]),
.dbgq_hi_csn_wr (dbgq_hi_csn_wr),
.dbgq_hi_csn_rd (dbgq_hi_csn_rd),
.dbgq_hi_wdata (dbgq_hi_wdata[`JBI_DBGQ_WIDTH-1:0]),
.dbgq_lo_raddr (dbgq_lo_raddr[`JBI_DBGQ_ADDR_WIDTH-1:0]),
.dbgq_lo_waddr (dbgq_lo_waddr[`JBI_DBGQ_ADDR_WIDTH-1:0]),
.dbgq_lo_csn_wr (dbgq_lo_csn_wr),
.dbgq_lo_csn_rd (dbgq_lo_csn_rd),
.dbgq_lo_wdata (dbgq_lo_wdata[`JBI_DBGQ_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst_l (rst_l),
.dbg_rst_l (dbg_rst_l),
.iob_jbi_dbg_hi_vld(iob_jbi_dbg_hi_vld),
.iob_jbi_dbg_hi_data(iob_jbi_dbg_hi_data[47:0]),
.iob_jbi_dbg_lo_vld(iob_jbi_dbg_lo_vld),
.iob_jbi_dbg_lo_data(iob_jbi_dbg_lo_data[47:0]),
.csr_jbi_debug_arb_max_wait(csr_jbi_debug_arb_max_wait[`JBI_CSR_DBG_MAX_WAIT_WIDTH-1:0]),
.csr_jbi_debug_arb_hi_water(csr_jbi_debug_arb_hi_water[`JBI_CSR_DBG_HI_WATER_WIDTH-1:0]),
.csr_jbi_debug_arb_lo_water(csr_jbi_debug_arb_lo_water[`JBI_CSR_DBG_LO_WATER_WIDTH-1:0]),
.csr_jbi_debug_arb_data_arb(csr_jbi_debug_arb_data_arb),
.csr_jbi_debug_arb_tstamp_wrap(csr_jbi_debug_arb_tstamp_wrap[`JBI_CSR_DBG_TSWRAP_WIDTH-1:0]),
.csr_jbi_debug_arb_alternate(csr_jbi_debug_arb_alternate),
.csr_jbi_debug_arb_alternate_set_l(csr_jbi_debug_arb_alternate_set_l),
.mout_dbg_pop (mout_dbg_pop),
.dbgq_hi_rdata (dbgq_hi_rdata[`JBI_DBGQ_WIDTH-1:0]),
.dbgq_lo_rdata (dbgq_lo_rdata[`JBI_DBGQ_WIDTH-1:0]));
jbi_dbg_buf u_dbg_buf (/*AUTOINST*/
// Outputs
.dbgq_hi_rdata (dbgq_hi_rdata[`JBI_DBGQ_WIDTH-1:0]),
.dbgq_lo_rdata (dbgq_lo_rdata[`JBI_DBGQ_WIDTH-1:0]),
// Inputs
.clk (clk),
.hold (hold),
.testmux_sel (testmux_sel),
.scan_en (scan_en),
.csr_16x65array_margin(csr_16x65array_margin[4:0]),
.dbgq_hi_raddr (dbgq_hi_raddr[`JBI_DBGQ_ADDR_WIDTH-1:0]),
.dbgq_lo_raddr (dbgq_lo_raddr[`JBI_DBGQ_ADDR_WIDTH-1:0]),
.dbgq_hi_waddr (dbgq_hi_waddr[`JBI_DBGQ_ADDR_WIDTH-1:0]),
.dbgq_lo_waddr (dbgq_lo_waddr[`JBI_DBGQ_ADDR_WIDTH-1:0]),
.dbgq_hi_csn_wr (dbgq_hi_csn_wr),
.dbgq_lo_csn_wr (dbgq_lo_csn_wr),
.dbgq_hi_csn_rd (dbgq_hi_csn_rd),
.dbgq_lo_csn_rd (dbgq_lo_csn_rd),
.dbgq_hi_wdata (dbgq_hi_wdata[`JBI_DBGQ_WIDTH-1:0]),
.dbgq_lo_wdata (dbgq_lo_wdata[`JBI_DBGQ_WIDTH-1:0]));
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-sense-defines-constant:t
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_8_V
`define SKY130_FD_SC_HVL__INV_8_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_8_V
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i64.add.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i64.add_tb.vcd");
$dumpvars(0, cpu_tb);
if(USE_64B) begin
#24
`assert(result, 3);
`assert(result_type, `i64);
`assert(result_empty, 0);
end
else begin
#12
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="array_io,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.359333,HLS_SYN_LAT=2,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=3395,HLS_SYN_LUT=1855}" *)
module array_io (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
d_o_0_din,
d_o_0_full_n,
d_o_0_write,
d_o_1_din,
d_o_1_full_n,
d_o_1_write,
d_o_2_din,
d_o_2_full_n,
d_o_2_write,
d_o_3_din,
d_o_3_full_n,
d_o_3_write,
d_o_4_din,
d_o_4_full_n,
d_o_4_write,
d_o_5_din,
d_o_5_full_n,
d_o_5_write,
d_o_6_din,
d_o_6_full_n,
d_o_6_write,
d_o_7_din,
d_o_7_full_n,
d_o_7_write,
d_o_8_din,
d_o_8_full_n,
d_o_8_write,
d_o_9_din,
d_o_9_full_n,
d_o_9_write,
d_o_10_din,
d_o_10_full_n,
d_o_10_write,
d_o_11_din,
d_o_11_full_n,
d_o_11_write,
d_o_12_din,
d_o_12_full_n,
d_o_12_write,
d_o_13_din,
d_o_13_full_n,
d_o_13_write,
d_o_14_din,
d_o_14_full_n,
d_o_14_write,
d_o_15_din,
d_o_15_full_n,
d_o_15_write,
d_o_16_din,
d_o_16_full_n,
d_o_16_write,
d_o_17_din,
d_o_17_full_n,
d_o_17_write,
d_o_18_din,
d_o_18_full_n,
d_o_18_write,
d_o_19_din,
d_o_19_full_n,
d_o_19_write,
d_o_20_din,
d_o_20_full_n,
d_o_20_write,
d_o_21_din,
d_o_21_full_n,
d_o_21_write,
d_o_22_din,
d_o_22_full_n,
d_o_22_write,
d_o_23_din,
d_o_23_full_n,
d_o_23_write,
d_o_24_din,
d_o_24_full_n,
d_o_24_write,
d_o_25_din,
d_o_25_full_n,
d_o_25_write,
d_o_26_din,
d_o_26_full_n,
d_o_26_write,
d_o_27_din,
d_o_27_full_n,
d_o_27_write,
d_o_28_din,
d_o_28_full_n,
d_o_28_write,
d_o_29_din,
d_o_29_full_n,
d_o_29_write,
d_o_30_din,
d_o_30_full_n,
d_o_30_write,
d_o_31_din,
d_o_31_full_n,
d_o_31_write,
d_i_0,
d_i_1,
d_i_2,
d_i_3,
d_i_4,
d_i_5,
d_i_6,
d_i_7,
d_i_8,
d_i_9,
d_i_10,
d_i_11,
d_i_12,
d_i_13,
d_i_14,
d_i_15,
d_i_16,
d_i_17,
d_i_18,
d_i_19,
d_i_20,
d_i_21,
d_i_22,
d_i_23,
d_i_24,
d_i_25,
d_i_26,
d_i_27,
d_i_28,
d_i_29,
d_i_30,
d_i_31
);
parameter ap_ST_fsm_state1 = 3'd1;
parameter ap_ST_fsm_state2 = 3'd2;
parameter ap_ST_fsm_state3 = 3'd4;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output [15:0] d_o_0_din;
input d_o_0_full_n;
output d_o_0_write;
output [15:0] d_o_1_din;
input d_o_1_full_n;
output d_o_1_write;
output [15:0] d_o_2_din;
input d_o_2_full_n;
output d_o_2_write;
output [15:0] d_o_3_din;
input d_o_3_full_n;
output d_o_3_write;
output [15:0] d_o_4_din;
input d_o_4_full_n;
output d_o_4_write;
output [15:0] d_o_5_din;
input d_o_5_full_n;
output d_o_5_write;
output [15:0] d_o_6_din;
input d_o_6_full_n;
output d_o_6_write;
output [15:0] d_o_7_din;
input d_o_7_full_n;
output d_o_7_write;
output [15:0] d_o_8_din;
input d_o_8_full_n;
output d_o_8_write;
output [15:0] d_o_9_din;
input d_o_9_full_n;
output d_o_9_write;
output [15:0] d_o_10_din;
input d_o_10_full_n;
output d_o_10_write;
output [15:0] d_o_11_din;
input d_o_11_full_n;
output d_o_11_write;
output [15:0] d_o_12_din;
input d_o_12_full_n;
output d_o_12_write;
output [15:0] d_o_13_din;
input d_o_13_full_n;
output d_o_13_write;
output [15:0] d_o_14_din;
input d_o_14_full_n;
output d_o_14_write;
output [15:0] d_o_15_din;
input d_o_15_full_n;
output d_o_15_write;
output [15:0] d_o_16_din;
input d_o_16_full_n;
output d_o_16_write;
output [15:0] d_o_17_din;
input d_o_17_full_n;
output d_o_17_write;
output [15:0] d_o_18_din;
input d_o_18_full_n;
output d_o_18_write;
output [15:0] d_o_19_din;
input d_o_19_full_n;
output d_o_19_write;
output [15:0] d_o_20_din;
input d_o_20_full_n;
output d_o_20_write;
output [15:0] d_o_21_din;
input d_o_21_full_n;
output d_o_21_write;
output [15:0] d_o_22_din;
input d_o_22_full_n;
output d_o_22_write;
output [15:0] d_o_23_din;
input d_o_23_full_n;
output d_o_23_write;
output [15:0] d_o_24_din;
input d_o_24_full_n;
output d_o_24_write;
output [15:0] d_o_25_din;
input d_o_25_full_n;
output d_o_25_write;
output [15:0] d_o_26_din;
input d_o_26_full_n;
output d_o_26_write;
output [15:0] d_o_27_din;
input d_o_27_full_n;
output d_o_27_write;
output [15:0] d_o_28_din;
input d_o_28_full_n;
output d_o_28_write;
output [15:0] d_o_29_din;
input d_o_29_full_n;
output d_o_29_write;
output [15:0] d_o_30_din;
input d_o_30_full_n;
output d_o_30_write;
output [15:0] d_o_31_din;
input d_o_31_full_n;
output d_o_31_write;
input [15:0] d_i_0;
input [15:0] d_i_1;
input [15:0] d_i_2;
input [15:0] d_i_3;
input [15:0] d_i_4;
input [15:0] d_i_5;
input [15:0] d_i_6;
input [15:0] d_i_7;
input [15:0] d_i_8;
input [15:0] d_i_9;
input [15:0] d_i_10;
input [15:0] d_i_11;
input [15:0] d_i_12;
input [15:0] d_i_13;
input [15:0] d_i_14;
input [15:0] d_i_15;
input [15:0] d_i_16;
input [15:0] d_i_17;
input [15:0] d_i_18;
input [15:0] d_i_19;
input [15:0] d_i_20;
input [15:0] d_i_21;
input [15:0] d_i_22;
input [15:0] d_i_23;
input [15:0] d_i_24;
input [15:0] d_i_25;
input [15:0] d_i_26;
input [15:0] d_i_27;
input [15:0] d_i_28;
input [15:0] d_i_29;
input [15:0] d_i_30;
input [15:0] d_i_31;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg d_o_0_write;
reg d_o_1_write;
reg d_o_2_write;
reg d_o_3_write;
reg d_o_4_write;
reg d_o_5_write;
reg d_o_6_write;
reg d_o_7_write;
reg d_o_8_write;
reg d_o_9_write;
reg d_o_10_write;
reg d_o_11_write;
reg d_o_12_write;
reg d_o_13_write;
reg d_o_14_write;
reg d_o_15_write;
reg d_o_16_write;
reg d_o_17_write;
reg d_o_18_write;
reg d_o_19_write;
reg d_o_20_write;
reg d_o_21_write;
reg d_o_22_write;
reg d_o_23_write;
reg d_o_24_write;
reg d_o_25_write;
reg d_o_26_write;
reg d_o_27_write;
reg d_o_28_write;
reg d_o_29_write;
reg d_o_30_write;
reg d_o_31_write;
(* fsm_encoding = "none" *) reg [2:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg [31:0] acc_0;
reg [31:0] acc_1;
reg [31:0] acc_2;
reg [31:0] acc_3;
reg [31:0] acc_4;
reg [31:0] acc_5;
reg [31:0] acc_6;
reg [31:0] acc_7;
reg d_o_0_blk_n;
wire ap_CS_fsm_state3;
reg d_o_1_blk_n;
reg d_o_2_blk_n;
reg d_o_3_blk_n;
reg d_o_4_blk_n;
reg d_o_5_blk_n;
reg d_o_6_blk_n;
reg d_o_7_blk_n;
reg d_o_8_blk_n;
reg d_o_9_blk_n;
reg d_o_10_blk_n;
reg d_o_11_blk_n;
reg d_o_12_blk_n;
reg d_o_13_blk_n;
reg d_o_14_blk_n;
reg d_o_15_blk_n;
reg d_o_16_blk_n;
reg d_o_17_blk_n;
reg d_o_18_blk_n;
reg d_o_19_blk_n;
reg d_o_20_blk_n;
reg d_o_21_blk_n;
reg d_o_22_blk_n;
reg d_o_23_blk_n;
reg d_o_24_blk_n;
reg d_o_25_blk_n;
reg d_o_26_blk_n;
reg d_o_27_blk_n;
reg d_o_28_blk_n;
reg d_o_29_blk_n;
reg d_o_30_blk_n;
reg d_o_31_blk_n;
wire [15:0] tmp_8_fu_586_p2;
reg [15:0] tmp_8_reg_1228;
wire [15:0] tmp_1_1_fu_600_p2;
reg [15:0] tmp_1_1_reg_1244;
wire [15:0] tmp_1_2_fu_614_p2;
reg [15:0] tmp_1_2_reg_1260;
wire [15:0] tmp_1_3_fu_628_p2;
reg [15:0] tmp_1_3_reg_1276;
wire [15:0] tmp_1_4_fu_642_p2;
reg [15:0] tmp_1_4_reg_1292;
wire [15:0] tmp_1_5_fu_656_p2;
reg [15:0] tmp_1_5_reg_1308;
wire [15:0] tmp_1_6_fu_670_p2;
reg [15:0] tmp_1_6_reg_1324;
wire [15:0] tmp_1_7_fu_684_p2;
reg [15:0] tmp_1_7_reg_1340;
wire [16:0] tmp3_fu_726_p2;
reg [16:0] tmp3_reg_1391;
wire [16:0] tmp6_fu_736_p2;
reg [16:0] tmp6_reg_1401;
wire [16:0] tmp9_fu_746_p2;
reg [16:0] tmp9_reg_1411;
wire [16:0] tmp12_fu_756_p2;
reg [16:0] tmp12_reg_1421;
wire [16:0] tmp15_fu_766_p2;
reg [16:0] tmp15_reg_1431;
wire [16:0] tmp18_fu_776_p2;
reg [16:0] tmp18_reg_1441;
wire [16:0] tmp21_fu_786_p2;
reg [16:0] tmp21_reg_1451;
wire [16:0] tmp24_fu_796_p2;
reg [16:0] tmp24_reg_1461;
wire [15:0] tmp_1_8_fu_830_p2;
reg [15:0] tmp_1_8_reg_1466;
wire ap_CS_fsm_state2;
wire [15:0] tmp_1_9_fu_839_p2;
reg [15:0] tmp_1_9_reg_1471;
wire [15:0] tmp_1_s_fu_848_p2;
reg [15:0] tmp_1_s_reg_1476;
wire [15:0] tmp_1_10_fu_857_p2;
reg [15:0] tmp_1_10_reg_1481;
wire [15:0] tmp_1_11_fu_866_p2;
reg [15:0] tmp_1_11_reg_1486;
wire [15:0] tmp_1_12_fu_875_p2;
reg [15:0] tmp_1_12_reg_1491;
wire [15:0] tmp_1_13_fu_884_p2;
reg [15:0] tmp_1_13_reg_1496;
wire [15:0] tmp_1_14_fu_893_p2;
reg [15:0] tmp_1_14_reg_1501;
wire [15:0] tmp_1_15_fu_898_p2;
reg [15:0] tmp_1_15_reg_1506;
wire [15:0] tmp_1_16_fu_903_p2;
reg [15:0] tmp_1_16_reg_1512;
wire [15:0] tmp_1_17_fu_908_p2;
reg [15:0] tmp_1_17_reg_1518;
wire [15:0] tmp_1_18_fu_913_p2;
reg [15:0] tmp_1_18_reg_1524;
wire [15:0] tmp_1_19_fu_918_p2;
reg [15:0] tmp_1_19_reg_1530;
wire [15:0] tmp_1_20_fu_923_p2;
reg [15:0] tmp_1_20_reg_1536;
wire [15:0] tmp_1_21_fu_928_p2;
reg [15:0] tmp_1_21_reg_1542;
wire [15:0] tmp_1_22_fu_933_p2;
reg [15:0] tmp_1_22_reg_1548;
reg ap_block_state3;
wire [31:0] temp_s_fu_956_p2;
wire [31:0] temp_1_fu_986_p2;
wire [31:0] temp_2_fu_1016_p2;
wire [31:0] temp_3_fu_1046_p2;
wire [31:0] temp_4_fu_1076_p2;
wire [31:0] temp_5_fu_1106_p2;
wire [31:0] temp_6_fu_1136_p2;
wire [31:0] temp_7_fu_1166_p2;
wire [15:0] tmp_1_fu_582_p1;
wire [15:0] tmp_9_fu_596_p1;
wire [15:0] tmp_10_fu_610_p1;
wire [15:0] tmp_11_fu_624_p1;
wire [15:0] tmp_12_fu_638_p1;
wire [15:0] tmp_13_fu_652_p1;
wire [15:0] tmp_14_fu_666_p1;
wire [15:0] tmp_15_fu_680_p1;
wire signed [16:0] tmp_16_cast_fu_690_p1;
wire signed [16:0] tmp_24_cast_fu_722_p1;
wire signed [16:0] tmp_17_cast_fu_694_p1;
wire signed [16:0] tmp_25_cast_fu_732_p1;
wire signed [16:0] tmp_18_cast_fu_698_p1;
wire signed [16:0] tmp_26_cast_fu_742_p1;
wire signed [16:0] tmp_19_cast_fu_702_p1;
wire signed [16:0] tmp_27_cast_fu_752_p1;
wire signed [16:0] tmp_20_cast_fu_706_p1;
wire signed [16:0] tmp_28_cast_fu_762_p1;
wire signed [16:0] tmp_21_cast_fu_710_p1;
wire signed [16:0] tmp_29_cast_fu_772_p1;
wire signed [16:0] tmp_22_cast_fu_714_p1;
wire signed [16:0] tmp_30_cast_fu_782_p1;
wire signed [16:0] tmp_23_cast_fu_718_p1;
wire signed [16:0] tmp_31_cast_fu_792_p1;
wire signed [31:0] tmp_fu_802_p1;
wire signed [17:0] tmp3_cast_fu_943_p1;
wire signed [17:0] tmp_8_cast_fu_826_p1;
wire [17:0] tmp2_fu_946_p2;
wire signed [31:0] tmp2_cast_fu_952_p1;
wire [31:0] tmp1_fu_938_p2;
wire signed [31:0] tmp_s_fu_805_p1;
wire signed [17:0] tmp6_cast_fu_973_p1;
wire signed [17:0] tmp_9_cast_fu_835_p1;
wire [17:0] tmp5_fu_976_p2;
wire signed [31:0] tmp5_cast_fu_982_p1;
wire [31:0] tmp4_fu_968_p2;
wire signed [31:0] tmp_2_fu_808_p1;
wire signed [17:0] tmp9_cast_fu_1003_p1;
wire signed [17:0] tmp_10_cast_fu_844_p1;
wire [17:0] tmp8_fu_1006_p2;
wire signed [31:0] tmp8_cast_fu_1012_p1;
wire [31:0] tmp7_fu_998_p2;
wire signed [31:0] tmp_3_fu_811_p1;
wire signed [17:0] tmp12_cast_fu_1033_p1;
wire signed [17:0] tmp_11_cast_fu_853_p1;
wire [17:0] tmp11_fu_1036_p2;
wire signed [31:0] tmp11_cast_fu_1042_p1;
wire [31:0] tmp10_fu_1028_p2;
wire signed [31:0] tmp_4_fu_814_p1;
wire signed [17:0] tmp15_cast_fu_1063_p1;
wire signed [17:0] tmp_12_cast_fu_862_p1;
wire [17:0] tmp14_fu_1066_p2;
wire signed [31:0] tmp14_cast_fu_1072_p1;
wire [31:0] tmp13_fu_1058_p2;
wire signed [31:0] tmp_5_fu_817_p1;
wire signed [17:0] tmp18_cast_fu_1093_p1;
wire signed [17:0] tmp_13_cast_fu_871_p1;
wire [17:0] tmp17_fu_1096_p2;
wire signed [31:0] tmp17_cast_fu_1102_p1;
wire [31:0] tmp16_fu_1088_p2;
wire signed [31:0] tmp_6_fu_820_p1;
wire signed [17:0] tmp21_cast_fu_1123_p1;
wire signed [17:0] tmp_14_cast_fu_880_p1;
wire [17:0] tmp20_fu_1126_p2;
wire signed [31:0] tmp20_cast_fu_1132_p1;
wire [31:0] tmp19_fu_1118_p2;
wire signed [31:0] tmp_7_fu_823_p1;
wire signed [17:0] tmp24_cast_fu_1153_p1;
wire signed [17:0] tmp_15_cast_fu_889_p1;
wire [17:0] tmp23_fu_1156_p2;
wire signed [31:0] tmp23_cast_fu_1162_p1;
wire [31:0] tmp22_fu_1148_p2;
reg [2:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 3'd1;
#0 acc_0 = 32'd0;
#0 acc_1 = 32'd0;
#0 acc_2 = 32'd0;
#0 acc_3 = 32'd0;
#0 acc_4 = 32'd0;
#0 acc_5 = 32'd0;
#0 acc_6 = 32'd0;
#0 acc_7 = 32'd0;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
acc_0 <= temp_s_fu_956_p2;
acc_1 <= temp_1_fu_986_p2;
acc_2 <= temp_2_fu_1016_p2;
acc_3 <= temp_3_fu_1046_p2;
acc_4 <= temp_4_fu_1076_p2;
acc_5 <= temp_5_fu_1106_p2;
acc_6 <= temp_6_fu_1136_p2;
acc_7 <= temp_7_fu_1166_p2;
tmp_1_10_reg_1481 <= tmp_1_10_fu_857_p2;
tmp_1_11_reg_1486 <= tmp_1_11_fu_866_p2;
tmp_1_12_reg_1491 <= tmp_1_12_fu_875_p2;
tmp_1_13_reg_1496 <= tmp_1_13_fu_884_p2;
tmp_1_14_reg_1501 <= tmp_1_14_fu_893_p2;
tmp_1_15_reg_1506 <= tmp_1_15_fu_898_p2;
tmp_1_16_reg_1512 <= tmp_1_16_fu_903_p2;
tmp_1_17_reg_1518 <= tmp_1_17_fu_908_p2;
tmp_1_18_reg_1524 <= tmp_1_18_fu_913_p2;
tmp_1_19_reg_1530 <= tmp_1_19_fu_918_p2;
tmp_1_20_reg_1536 <= tmp_1_20_fu_923_p2;
tmp_1_21_reg_1542 <= tmp_1_21_fu_928_p2;
tmp_1_22_reg_1548 <= tmp_1_22_fu_933_p2;
tmp_1_8_reg_1466 <= tmp_1_8_fu_830_p2;
tmp_1_9_reg_1471 <= tmp_1_9_fu_839_p2;
tmp_1_s_reg_1476 <= tmp_1_s_fu_848_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
tmp12_reg_1421 <= tmp12_fu_756_p2;
tmp15_reg_1431 <= tmp15_fu_766_p2;
tmp18_reg_1441 <= tmp18_fu_776_p2;
tmp21_reg_1451 <= tmp21_fu_786_p2;
tmp24_reg_1461 <= tmp24_fu_796_p2;
tmp3_reg_1391 <= tmp3_fu_726_p2;
tmp6_reg_1401 <= tmp6_fu_736_p2;
tmp9_reg_1411 <= tmp9_fu_746_p2;
tmp_1_1_reg_1244 <= tmp_1_1_fu_600_p2;
tmp_1_2_reg_1260 <= tmp_1_2_fu_614_p2;
tmp_1_3_reg_1276 <= tmp_1_3_fu_628_p2;
tmp_1_4_reg_1292 <= tmp_1_4_fu_642_p2;
tmp_1_5_reg_1308 <= tmp_1_5_fu_656_p2;
tmp_1_6_reg_1324 <= tmp_1_6_fu_670_p2;
tmp_1_7_reg_1340 <= tmp_1_7_fu_684_p2;
tmp_8_reg_1228 <= tmp_8_fu_586_p2;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_0_blk_n = d_o_0_full_n;
end else begin
d_o_0_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_0_write = 1'b1;
end else begin
d_o_0_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_10_blk_n = d_o_10_full_n;
end else begin
d_o_10_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_10_write = 1'b1;
end else begin
d_o_10_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_11_blk_n = d_o_11_full_n;
end else begin
d_o_11_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_11_write = 1'b1;
end else begin
d_o_11_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_12_blk_n = d_o_12_full_n;
end else begin
d_o_12_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_12_write = 1'b1;
end else begin
d_o_12_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_13_blk_n = d_o_13_full_n;
end else begin
d_o_13_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_13_write = 1'b1;
end else begin
d_o_13_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_14_blk_n = d_o_14_full_n;
end else begin
d_o_14_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_14_write = 1'b1;
end else begin
d_o_14_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_15_blk_n = d_o_15_full_n;
end else begin
d_o_15_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_15_write = 1'b1;
end else begin
d_o_15_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_16_blk_n = d_o_16_full_n;
end else begin
d_o_16_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_16_write = 1'b1;
end else begin
d_o_16_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_17_blk_n = d_o_17_full_n;
end else begin
d_o_17_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_17_write = 1'b1;
end else begin
d_o_17_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_18_blk_n = d_o_18_full_n;
end else begin
d_o_18_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_18_write = 1'b1;
end else begin
d_o_18_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_19_blk_n = d_o_19_full_n;
end else begin
d_o_19_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_19_write = 1'b1;
end else begin
d_o_19_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_1_blk_n = d_o_1_full_n;
end else begin
d_o_1_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_1_write = 1'b1;
end else begin
d_o_1_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_20_blk_n = d_o_20_full_n;
end else begin
d_o_20_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_20_write = 1'b1;
end else begin
d_o_20_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_21_blk_n = d_o_21_full_n;
end else begin
d_o_21_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_21_write = 1'b1;
end else begin
d_o_21_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_22_blk_n = d_o_22_full_n;
end else begin
d_o_22_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_22_write = 1'b1;
end else begin
d_o_22_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_23_blk_n = d_o_23_full_n;
end else begin
d_o_23_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_23_write = 1'b1;
end else begin
d_o_23_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_24_blk_n = d_o_24_full_n;
end else begin
d_o_24_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_24_write = 1'b1;
end else begin
d_o_24_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_25_blk_n = d_o_25_full_n;
end else begin
d_o_25_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_25_write = 1'b1;
end else begin
d_o_25_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_26_blk_n = d_o_26_full_n;
end else begin
d_o_26_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_26_write = 1'b1;
end else begin
d_o_26_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_27_blk_n = d_o_27_full_n;
end else begin
d_o_27_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_27_write = 1'b1;
end else begin
d_o_27_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_28_blk_n = d_o_28_full_n;
end else begin
d_o_28_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_28_write = 1'b1;
end else begin
d_o_28_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_29_blk_n = d_o_29_full_n;
end else begin
d_o_29_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_29_write = 1'b1;
end else begin
d_o_29_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_2_blk_n = d_o_2_full_n;
end else begin
d_o_2_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_2_write = 1'b1;
end else begin
d_o_2_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_30_blk_n = d_o_30_full_n;
end else begin
d_o_30_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_30_write = 1'b1;
end else begin
d_o_30_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_31_blk_n = d_o_31_full_n;
end else begin
d_o_31_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_31_write = 1'b1;
end else begin
d_o_31_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_3_blk_n = d_o_3_full_n;
end else begin
d_o_3_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_3_write = 1'b1;
end else begin
d_o_3_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_4_blk_n = d_o_4_full_n;
end else begin
d_o_4_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_4_write = 1'b1;
end else begin
d_o_4_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_5_blk_n = d_o_5_full_n;
end else begin
d_o_5_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_5_write = 1'b1;
end else begin
d_o_5_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_6_blk_n = d_o_6_full_n;
end else begin
d_o_6_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_6_write = 1'b1;
end else begin
d_o_6_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_7_blk_n = d_o_7_full_n;
end else begin
d_o_7_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_7_write = 1'b1;
end else begin
d_o_7_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_8_blk_n = d_o_8_full_n;
end else begin
d_o_8_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_8_write = 1'b1;
end else begin
d_o_8_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_9_blk_n = d_o_9_full_n;
end else begin
d_o_9_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
d_o_9_write = 1'b1;
end else begin
d_o_9_write = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
ap_NS_fsm = ap_ST_fsm_state3;
end
ap_ST_fsm_state3 : begin
if (((1'b1 == ap_CS_fsm_state3) & ~((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n)))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_state3;
end
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
always @ (*) begin
ap_block_state3 = ((1'b0 == d_o_0_full_n) | (1'b0 == d_o_1_full_n) | (1'b0 == d_o_2_full_n) | (1'b0 == d_o_3_full_n) | (1'b0 == d_o_4_full_n) | (1'b0 == d_o_5_full_n) | (1'b0 == d_o_6_full_n) | (1'b0 == d_o_7_full_n) | (1'b0 == d_o_8_full_n) | (1'b0 == d_o_9_full_n) | (1'b0 == d_o_10_full_n) | (1'b0 == d_o_11_full_n) | (1'b0 == d_o_12_full_n) | (1'b0 == d_o_13_full_n) | (1'b0 == d_o_14_full_n) | (1'b0 == d_o_15_full_n) | (1'b0 == d_o_16_full_n) | (1'b0 == d_o_17_full_n) | (1'b0 == d_o_18_full_n) | (1'b0 == d_o_19_full_n) | (1'b0 == d_o_20_full_n) | (1'b0 == d_o_21_full_n) | (1'b0 == d_o_22_full_n) | (1'b0 == d_o_23_full_n) | (1'b0 == d_o_24_full_n) | (1'b0 == d_o_25_full_n) | (1'b0 == d_o_26_full_n) | (1'b0 == d_o_27_full_n) | (1'b0 == d_o_28_full_n) | (1'b0 == d_o_29_full_n) | (1'b0 == d_o_30_full_n) | (1'b0 == d_o_31_full_n));
end
assign d_o_0_din = tmp_8_reg_1228;
assign d_o_10_din = tmp_1_s_reg_1476;
assign d_o_11_din = tmp_1_10_reg_1481;
assign d_o_12_din = tmp_1_11_reg_1486;
assign d_o_13_din = tmp_1_12_reg_1491;
assign d_o_14_din = tmp_1_13_reg_1496;
assign d_o_15_din = tmp_1_14_reg_1501;
assign d_o_16_din = tmp_1_15_reg_1506;
assign d_o_17_din = tmp_1_16_reg_1512;
assign d_o_18_din = tmp_1_17_reg_1518;
assign d_o_19_din = tmp_1_18_reg_1524;
assign d_o_1_din = tmp_1_1_reg_1244;
assign d_o_20_din = tmp_1_19_reg_1530;
assign d_o_21_din = tmp_1_20_reg_1536;
assign d_o_22_din = tmp_1_21_reg_1542;
assign d_o_23_din = tmp_1_22_reg_1548;
assign d_o_24_din = (d_i_24 + tmp_1_15_reg_1506);
assign d_o_25_din = (d_i_25 + tmp_1_16_reg_1512);
assign d_o_26_din = (d_i_26 + tmp_1_17_reg_1518);
assign d_o_27_din = (d_i_27 + tmp_1_18_reg_1524);
assign d_o_28_din = (d_i_28 + tmp_1_19_reg_1530);
assign d_o_29_din = (d_i_29 + tmp_1_20_reg_1536);
assign d_o_2_din = tmp_1_2_reg_1260;
assign d_o_30_din = (d_i_30 + tmp_1_21_reg_1542);
assign d_o_31_din = (d_i_31 + tmp_1_22_reg_1548);
assign d_o_3_din = tmp_1_3_reg_1276;
assign d_o_4_din = tmp_1_4_reg_1292;
assign d_o_5_din = tmp_1_5_reg_1308;
assign d_o_6_din = tmp_1_6_reg_1324;
assign d_o_7_din = tmp_1_7_reg_1340;
assign d_o_8_din = tmp_1_8_reg_1466;
assign d_o_9_din = tmp_1_9_reg_1471;
assign temp_1_fu_986_p2 = ($signed(tmp5_cast_fu_982_p1) + $signed(tmp4_fu_968_p2));
assign temp_2_fu_1016_p2 = ($signed(tmp8_cast_fu_1012_p1) + $signed(tmp7_fu_998_p2));
assign temp_3_fu_1046_p2 = ($signed(tmp11_cast_fu_1042_p1) + $signed(tmp10_fu_1028_p2));
assign temp_4_fu_1076_p2 = ($signed(tmp14_cast_fu_1072_p1) + $signed(tmp13_fu_1058_p2));
assign temp_5_fu_1106_p2 = ($signed(tmp17_cast_fu_1102_p1) + $signed(tmp16_fu_1088_p2));
assign temp_6_fu_1136_p2 = ($signed(tmp20_cast_fu_1132_p1) + $signed(tmp19_fu_1118_p2));
assign temp_7_fu_1166_p2 = ($signed(tmp23_cast_fu_1162_p1) + $signed(tmp22_fu_1148_p2));
assign temp_s_fu_956_p2 = ($signed(tmp2_cast_fu_952_p1) + $signed(tmp1_fu_938_p2));
assign tmp10_fu_1028_p2 = ($signed(acc_3) + $signed(tmp_3_fu_811_p1));
assign tmp11_cast_fu_1042_p1 = $signed(tmp11_fu_1036_p2);
assign tmp11_fu_1036_p2 = ($signed(tmp12_cast_fu_1033_p1) + $signed(tmp_11_cast_fu_853_p1));
assign tmp12_cast_fu_1033_p1 = $signed(tmp12_reg_1421);
assign tmp12_fu_756_p2 = ($signed(tmp_19_cast_fu_702_p1) + $signed(tmp_27_cast_fu_752_p1));
assign tmp13_fu_1058_p2 = ($signed(acc_4) + $signed(tmp_4_fu_814_p1));
assign tmp14_cast_fu_1072_p1 = $signed(tmp14_fu_1066_p2);
assign tmp14_fu_1066_p2 = ($signed(tmp15_cast_fu_1063_p1) + $signed(tmp_12_cast_fu_862_p1));
assign tmp15_cast_fu_1063_p1 = $signed(tmp15_reg_1431);
assign tmp15_fu_766_p2 = ($signed(tmp_20_cast_fu_706_p1) + $signed(tmp_28_cast_fu_762_p1));
assign tmp16_fu_1088_p2 = ($signed(acc_5) + $signed(tmp_5_fu_817_p1));
assign tmp17_cast_fu_1102_p1 = $signed(tmp17_fu_1096_p2);
assign tmp17_fu_1096_p2 = ($signed(tmp18_cast_fu_1093_p1) + $signed(tmp_13_cast_fu_871_p1));
assign tmp18_cast_fu_1093_p1 = $signed(tmp18_reg_1441);
assign tmp18_fu_776_p2 = ($signed(tmp_21_cast_fu_710_p1) + $signed(tmp_29_cast_fu_772_p1));
assign tmp19_fu_1118_p2 = ($signed(acc_6) + $signed(tmp_6_fu_820_p1));
assign tmp1_fu_938_p2 = ($signed(acc_0) + $signed(tmp_fu_802_p1));
assign tmp20_cast_fu_1132_p1 = $signed(tmp20_fu_1126_p2);
assign tmp20_fu_1126_p2 = ($signed(tmp21_cast_fu_1123_p1) + $signed(tmp_14_cast_fu_880_p1));
assign tmp21_cast_fu_1123_p1 = $signed(tmp21_reg_1451);
assign tmp21_fu_786_p2 = ($signed(tmp_22_cast_fu_714_p1) + $signed(tmp_30_cast_fu_782_p1));
assign tmp22_fu_1148_p2 = ($signed(acc_7) + $signed(tmp_7_fu_823_p1));
assign tmp23_cast_fu_1162_p1 = $signed(tmp23_fu_1156_p2);
assign tmp23_fu_1156_p2 = ($signed(tmp24_cast_fu_1153_p1) + $signed(tmp_15_cast_fu_889_p1));
assign tmp24_cast_fu_1153_p1 = $signed(tmp24_reg_1461);
assign tmp24_fu_796_p2 = ($signed(tmp_23_cast_fu_718_p1) + $signed(tmp_31_cast_fu_792_p1));
assign tmp2_cast_fu_952_p1 = $signed(tmp2_fu_946_p2);
assign tmp2_fu_946_p2 = ($signed(tmp3_cast_fu_943_p1) + $signed(tmp_8_cast_fu_826_p1));
assign tmp3_cast_fu_943_p1 = $signed(tmp3_reg_1391);
assign tmp3_fu_726_p2 = ($signed(tmp_16_cast_fu_690_p1) + $signed(tmp_24_cast_fu_722_p1));
assign tmp4_fu_968_p2 = ($signed(acc_1) + $signed(tmp_s_fu_805_p1));
assign tmp5_cast_fu_982_p1 = $signed(tmp5_fu_976_p2);
assign tmp5_fu_976_p2 = ($signed(tmp6_cast_fu_973_p1) + $signed(tmp_9_cast_fu_835_p1));
assign tmp6_cast_fu_973_p1 = $signed(tmp6_reg_1401);
assign tmp6_fu_736_p2 = ($signed(tmp_17_cast_fu_694_p1) + $signed(tmp_25_cast_fu_732_p1));
assign tmp7_fu_998_p2 = ($signed(acc_2) + $signed(tmp_2_fu_808_p1));
assign tmp8_cast_fu_1012_p1 = $signed(tmp8_fu_1006_p2);
assign tmp8_fu_1006_p2 = ($signed(tmp9_cast_fu_1003_p1) + $signed(tmp_10_cast_fu_844_p1));
assign tmp9_cast_fu_1003_p1 = $signed(tmp9_reg_1411);
assign tmp9_fu_746_p2 = ($signed(tmp_18_cast_fu_698_p1) + $signed(tmp_26_cast_fu_742_p1));
assign tmp_10_cast_fu_844_p1 = $signed(d_i_10);
assign tmp_10_fu_610_p1 = acc_2[15:0];
assign tmp_11_cast_fu_853_p1 = $signed(d_i_11);
assign tmp_11_fu_624_p1 = acc_3[15:0];
assign tmp_12_cast_fu_862_p1 = $signed(d_i_12);
assign tmp_12_fu_638_p1 = acc_4[15:0];
assign tmp_13_cast_fu_871_p1 = $signed(d_i_13);
assign tmp_13_fu_652_p1 = acc_5[15:0];
assign tmp_14_cast_fu_880_p1 = $signed(d_i_14);
assign tmp_14_fu_666_p1 = acc_6[15:0];
assign tmp_15_cast_fu_889_p1 = $signed(d_i_15);
assign tmp_15_fu_680_p1 = acc_7[15:0];
assign tmp_16_cast_fu_690_p1 = $signed(d_i_16);
assign tmp_17_cast_fu_694_p1 = $signed(d_i_17);
assign tmp_18_cast_fu_698_p1 = $signed(d_i_18);
assign tmp_19_cast_fu_702_p1 = $signed(d_i_19);
assign tmp_1_10_fu_857_p2 = (d_i_11 + tmp_1_3_reg_1276);
assign tmp_1_11_fu_866_p2 = (d_i_12 + tmp_1_4_reg_1292);
assign tmp_1_12_fu_875_p2 = (d_i_13 + tmp_1_5_reg_1308);
assign tmp_1_13_fu_884_p2 = (d_i_14 + tmp_1_6_reg_1324);
assign tmp_1_14_fu_893_p2 = (d_i_15 + tmp_1_7_reg_1340);
assign tmp_1_15_fu_898_p2 = (d_i_16 + tmp_1_8_fu_830_p2);
assign tmp_1_16_fu_903_p2 = (d_i_17 + tmp_1_9_fu_839_p2);
assign tmp_1_17_fu_908_p2 = (d_i_18 + tmp_1_s_fu_848_p2);
assign tmp_1_18_fu_913_p2 = (d_i_19 + tmp_1_10_fu_857_p2);
assign tmp_1_19_fu_918_p2 = (d_i_20 + tmp_1_11_fu_866_p2);
assign tmp_1_1_fu_600_p2 = (d_i_1 + tmp_9_fu_596_p1);
assign tmp_1_20_fu_923_p2 = (d_i_21 + tmp_1_12_fu_875_p2);
assign tmp_1_21_fu_928_p2 = (d_i_22 + tmp_1_13_fu_884_p2);
assign tmp_1_22_fu_933_p2 = (d_i_23 + tmp_1_14_fu_893_p2);
assign tmp_1_2_fu_614_p2 = (d_i_2 + tmp_10_fu_610_p1);
assign tmp_1_3_fu_628_p2 = (d_i_3 + tmp_11_fu_624_p1);
assign tmp_1_4_fu_642_p2 = (d_i_4 + tmp_12_fu_638_p1);
assign tmp_1_5_fu_656_p2 = (d_i_5 + tmp_13_fu_652_p1);
assign tmp_1_6_fu_670_p2 = (d_i_6 + tmp_14_fu_666_p1);
assign tmp_1_7_fu_684_p2 = (d_i_7 + tmp_15_fu_680_p1);
assign tmp_1_8_fu_830_p2 = (d_i_8 + tmp_8_reg_1228);
assign tmp_1_9_fu_839_p2 = (d_i_9 + tmp_1_1_reg_1244);
assign tmp_1_fu_582_p1 = acc_0[15:0];
assign tmp_1_s_fu_848_p2 = (d_i_10 + tmp_1_2_reg_1260);
assign tmp_20_cast_fu_706_p1 = $signed(d_i_20);
assign tmp_21_cast_fu_710_p1 = $signed(d_i_21);
assign tmp_22_cast_fu_714_p1 = $signed(d_i_22);
assign tmp_23_cast_fu_718_p1 = $signed(d_i_23);
assign tmp_24_cast_fu_722_p1 = $signed(d_i_24);
assign tmp_25_cast_fu_732_p1 = $signed(d_i_25);
assign tmp_26_cast_fu_742_p1 = $signed(d_i_26);
assign tmp_27_cast_fu_752_p1 = $signed(d_i_27);
assign tmp_28_cast_fu_762_p1 = $signed(d_i_28);
assign tmp_29_cast_fu_772_p1 = $signed(d_i_29);
assign tmp_2_fu_808_p1 = $signed(d_i_2);
assign tmp_30_cast_fu_782_p1 = $signed(d_i_30);
assign tmp_31_cast_fu_792_p1 = $signed(d_i_31);
assign tmp_3_fu_811_p1 = $signed(d_i_3);
assign tmp_4_fu_814_p1 = $signed(d_i_4);
assign tmp_5_fu_817_p1 = $signed(d_i_5);
assign tmp_6_fu_820_p1 = $signed(d_i_6);
assign tmp_7_fu_823_p1 = $signed(d_i_7);
assign tmp_8_cast_fu_826_p1 = $signed(d_i_8);
assign tmp_8_fu_586_p2 = (d_i_0 + tmp_1_fu_582_p1);
assign tmp_9_cast_fu_835_p1 = $signed(d_i_9);
assign tmp_9_fu_596_p1 = acc_1[15:0];
assign tmp_fu_802_p1 = $signed(d_i_0);
assign tmp_s_fu_805_p1 = $signed(d_i_1);
endmodule //array_io
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO0P_FUNCTIONAL_V
`define SKY130_FD_SC_LP__LSBUFISO0P_FUNCTIONAL_V
/**
* lsbufiso0p: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__lsbufiso0p (
X ,
SLEEP,
A
);
// Module ports
output X ;
input SLEEP;
input A ;
// Local signals
wire sleepb ;
wire and0_out_X;
wire destpwr ;
wire vgnd ;
// Name Output Other arguments
not not0 (sleepb , SLEEP );
and and0 (and0_out_X, sleepb, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , and0_out_X, destpwr, vgnd);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO0P_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O32AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__O32AI_BEHAVIORAL_PP_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o32ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O32AI_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXBP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DLXBP_BEHAVIORAL_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlxbp (
Q ,
Q_N ,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXBP_BEHAVIORAL_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_1024x8.v,v $
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_spram_1024x8(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 10;
parameter dw = 8;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_1024x8 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_1024x8_bist artisan_ssp(
`else
art_hssp_1024x8 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_1024x8 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_1024x8_bist vs_ssp(
`else
vs_hdsp_1024x8 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S4 ramb4_s4_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[3:0]),
.EN(ce),
.WE(we),
.DO(doq[3:0])
);
//
// Block 1
//
RAMB4_S4 ramb4_s4_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:4]),
.EN(ce),
.WE(we),
.DO(doq[7:4])
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S9 ramb16_s9(
.CLK(clk),
.SSR(rst),
.ADDR({1'b0,addr}),
.DI(di),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * An light axiomatization of integers (used in MSetAVL). *)
(** We define a signature for an integer datatype based on [Z].
The goal is to allow a switch after extraction to ocaml's
[big_int] or even [int] when finiteness isn't a problem
(typically : when measuring the height of an AVL tree).
*)
Require Import BinInt.
Declare Scope Int_scope.
Delimit Scope Int_scope with I.
Local Open Scope Int_scope.
(** * A specification of integers *)
Module Type Int.
Parameter t : Set.
Bind Scope Int_scope with t.
Parameter i2z : t -> Z.
Parameter _0 : t.
Parameter _1 : t.
Parameter _2 : t.
Parameter _3 : t.
Parameter add : t -> t -> t.
Parameter opp : t -> t.
Parameter sub : t -> t -> t.
Parameter mul : t -> t -> t.
Parameter max : t -> t -> t.
Notation "0" := _0 : Int_scope.
Notation "1" := _1 : Int_scope.
Notation "2" := _2 : Int_scope.
Notation "3" := _3 : Int_scope.
Infix "+" := add : Int_scope.
Infix "-" := sub : Int_scope.
Infix "*" := mul : Int_scope.
Notation "- x" := (opp x) : Int_scope.
(** For logical relations, we can rely on their counterparts in Z,
since they don't appear after extraction. Moreover, using tactics
like omega is easier this way. *)
Notation "x == y" := (i2z x = i2z y)
(at level 70, y at next level, no associativity) : Int_scope.
Notation "x <= y" := (i2z x <= i2z y)%Z : Int_scope.
Notation "x < y" := (i2z x < i2z y)%Z : Int_scope.
Notation "x >= y" := (i2z x >= i2z y)%Z : Int_scope.
Notation "x > y" := (i2z x > i2z y)%Z : Int_scope.
Notation "x <= y <= z" := (x <= y /\ y <= z) : Int_scope.
Notation "x <= y < z" := (x <= y /\ y < z) : Int_scope.
Notation "x < y < z" := (x < y /\ y < z) : Int_scope.
Notation "x < y <= z" := (x < y /\ y <= z) : Int_scope.
(** Informative comparisons. *)
Axiom eqb : t -> t -> bool.
Axiom ltb : t -> t -> bool.
Axiom leb : t -> t -> bool.
Infix "=?" := eqb.
Infix "<?" := ltb.
Infix "<=?" := leb.
(** For compatibility, some decidability fonctions (informative). *)
Axiom gt_le_dec : forall x y : t, {x > y} + {x <= y}.
Axiom ge_lt_dec : forall x y : t, {x >= y} + {x < y}.
Axiom eq_dec : forall x y : t, { x == y } + {~ x==y }.
(** Specifications *)
(** First, we ask [i2z] to be injective. Said otherwise, our ad-hoc equality
[==] and the generic [=] are in fact equivalent. We define [==]
nonetheless since the translation to [Z] for using automatic tactic
is easier. *)
Axiom i2z_eq : forall n p : t, n == p -> n = p.
(** Then, we express the specifications of the above parameters using their
Z counterparts. *)
Axiom i2z_0 : i2z _0 = 0%Z.
Axiom i2z_1 : i2z _1 = 1%Z.
Axiom i2z_2 : i2z _2 = 2%Z.
Axiom i2z_3 : i2z _3 = 3%Z.
Axiom i2z_add : forall n p, i2z (n + p) = (i2z n + i2z p)%Z.
Axiom i2z_opp : forall n, i2z (-n) = (-i2z n)%Z.
Axiom i2z_sub : forall n p, i2z (n - p) = (i2z n - i2z p)%Z.
Axiom i2z_mul : forall n p, i2z (n * p) = (i2z n * i2z p)%Z.
Axiom i2z_max : forall n p, i2z (max n p) = Z.max (i2z n) (i2z p).
Axiom i2z_eqb : forall n p, eqb n p = Z.eqb (i2z n) (i2z p).
Axiom i2z_ltb : forall n p, ltb n p = Z.ltb (i2z n) (i2z p).
Axiom i2z_leb : forall n p, leb n p = Z.leb (i2z n) (i2z p).
End Int.
(** * Facts and tactics using [Int] *)
Module MoreInt (Import I:Int).
Local Notation int := I.t.
Lemma eqb_eq n p : (n =? p) = true <-> n == p.
Proof.
now rewrite i2z_eqb, Z.eqb_eq.
Qed.
Lemma eqb_neq n p : (n =? p) = false <-> ~(n == p).
Proof.
rewrite <- eqb_eq. destruct (n =? p); intuition.
Qed.
Lemma ltb_lt n p : (n <? p) = true <-> n < p.
Proof.
now rewrite i2z_ltb, Z.ltb_lt.
Qed.
Lemma ltb_nlt n p : (n <? p) = false <-> ~(n < p).
Proof.
rewrite <- ltb_lt. destruct (n <? p); intuition.
Qed.
Lemma leb_le n p : (n <=? p) = true <-> n <= p.
Proof.
now rewrite i2z_leb, Z.leb_le.
Qed.
Lemma leb_nle n p : (n <=? p) = false <-> ~(n <= p).
Proof.
rewrite <- leb_le. destruct (n <=? p); intuition.
Qed.
(** A magic (but costly) tactic that goes from [int] back to the [Z]
friendly world ... *)
Hint Rewrite ->
i2z_0 i2z_1 i2z_2 i2z_3 i2z_add i2z_opp i2z_sub i2z_mul i2z_max
i2z_eqb i2z_ltb i2z_leb : i2z.
Ltac i2z := match goal with
| H : ?a = ?b |- _ =>
generalize (f_equal i2z H);
try autorewrite with i2z; clear H; intro H; i2z
| |- ?a = ?b =>
apply (i2z_eq a b); try autorewrite with i2z; i2z
| H : _ |- _ => progress autorewrite with i2z in H; i2z
| _ => try autorewrite with i2z
end.
(** A reflexive version of the [i2z] tactic *)
(** this [i2z_refl] is actually weaker than [i2z]. For instance, if a
[i2z] is buried deep inside a subterm, [i2z_refl] may miss it.
See also the limitation about [Set] or [Type] part below.
Anyhow, [i2z_refl] is enough for applying [romega]. *)
Ltac i2z_gen := match goal with
| |- ?a = ?b => apply (i2z_eq a b); i2z_gen
| H : ?a = ?b |- _ =>
generalize (f_equal i2z H); clear H; i2z_gen
| H : eq (A:=Z) ?a ?b |- _ => revert H; i2z_gen
| H : Z.lt ?a ?b |- _ => revert H; i2z_gen
| H : Z.le ?a ?b |- _ => revert H; i2z_gen
| H : Z.gt ?a ?b |- _ => revert H; i2z_gen
| H : Z.ge ?a ?b |- _ => revert H; i2z_gen
| H : _ -> ?X |- _ =>
(* A [Set] or [Type] part cannot be dealt with easily
using the [ExprP] datatype. So we forget it, leaving
a goal that can be weaker than the original. *)
match type of X with
| Type => clear H; i2z_gen
| Prop => revert H; i2z_gen
end
| H : _ <-> _ |- _ => revert H; i2z_gen
| H : _ /\ _ |- _ => revert H; i2z_gen
| H : _ \/ _ |- _ => revert H; i2z_gen
| H : ~ _ |- _ => revert H; i2z_gen
| _ => idtac
end.
Inductive ExprI : Set :=
| EI0 : ExprI
| EI1 : ExprI
| EI2 : ExprI
| EI3 : ExprI
| EIadd : ExprI -> ExprI -> ExprI
| EIopp : ExprI -> ExprI
| EIsub : ExprI -> ExprI -> ExprI
| EImul : ExprI -> ExprI -> ExprI
| EImax : ExprI -> ExprI -> ExprI
| EIraw : int -> ExprI.
Inductive ExprZ : Set :=
| EZadd : ExprZ -> ExprZ -> ExprZ
| EZopp : ExprZ -> ExprZ
| EZsub : ExprZ -> ExprZ -> ExprZ
| EZmul : ExprZ -> ExprZ -> ExprZ
| EZmax : ExprZ -> ExprZ -> ExprZ
| EZofI : ExprI -> ExprZ
| EZraw : Z -> ExprZ.
Inductive ExprP : Type :=
| EPeq : ExprZ -> ExprZ -> ExprP
| EPlt : ExprZ -> ExprZ -> ExprP
| EPle : ExprZ -> ExprZ -> ExprP
| EPgt : ExprZ -> ExprZ -> ExprP
| EPge : ExprZ -> ExprZ -> ExprP
| EPimpl : ExprP -> ExprP -> ExprP
| EPequiv : ExprP -> ExprP -> ExprP
| EPand : ExprP -> ExprP -> ExprP
| EPor : ExprP -> ExprP -> ExprP
| EPneg : ExprP -> ExprP
| EPraw : Prop -> ExprP.
(** [int] to [ExprI] *)
Ltac i2ei trm :=
match constr:(trm) with
| 0 => constr:(EI0)
| 1 => constr:(EI1)
| 2 => constr:(EI2)
| 3 => constr:(EI3)
| ?x + ?y => let ex := i2ei x with ey := i2ei y in constr:(EIadd ex ey)
| ?x - ?y => let ex := i2ei x with ey := i2ei y in constr:(EIsub ex ey)
| ?x * ?y => let ex := i2ei x with ey := i2ei y in constr:(EImul ex ey)
| max ?x ?y => let ex := i2ei x with ey := i2ei y in constr:(EImax ex ey)
| - ?x => let ex := i2ei x in constr:(EIopp ex)
| ?x => constr:(EIraw x)
end
(** [Z] to [ExprZ] *)
with z2ez trm :=
match constr:(trm) with
| (?x + ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZadd ex ey)
| (?x - ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZsub ex ey)
| (?x * ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZmul ex ey)
| (Z.max ?x ?y) => let ex := z2ez x with ey := z2ez y in constr:(EZmax ex ey)
| (- ?x)%Z => let ex := z2ez x in constr:(EZopp ex)
| i2z ?x => let ex := i2ei x in constr:(EZofI ex)
| ?x => constr:(EZraw x)
end.
(** [Prop] to [ExprP] *)
Ltac p2ep trm :=
match constr:(trm) with
| (?x <-> ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPequiv ex ey)
| (?x -> ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPimpl ex ey)
| (?x /\ ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPand ex ey)
| (?x \/ ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPor ex ey)
| (~ ?x) => let ex := p2ep x in constr:(EPneg ex)
| (eq (A:=Z) ?x ?y) => let ex := z2ez x with ey := z2ez y in constr:(EPeq ex ey)
| (?x < ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPlt ex ey)
| (?x <= ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPle ex ey)
| (?x > ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPgt ex ey)
| (?x >= ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPge ex ey)
| ?x => constr:(EPraw x)
end.
(** [ExprI] to [int] *)
Fixpoint ei2i (e:ExprI) : int :=
match e with
| EI0 => 0
| EI1 => 1
| EI2 => 2
| EI3 => 3
| EIadd e1 e2 => (ei2i e1)+(ei2i e2)
| EIsub e1 e2 => (ei2i e1)-(ei2i e2)
| EImul e1 e2 => (ei2i e1)*(ei2i e2)
| EImax e1 e2 => max (ei2i e1) (ei2i e2)
| EIopp e => -(ei2i e)
| EIraw i => i
end.
(** [ExprZ] to [Z] *)
Fixpoint ez2z (e:ExprZ) : Z :=
match e with
| EZadd e1 e2 => ((ez2z e1)+(ez2z e2))%Z
| EZsub e1 e2 => ((ez2z e1)-(ez2z e2))%Z
| EZmul e1 e2 => ((ez2z e1)*(ez2z e2))%Z
| EZmax e1 e2 => Z.max (ez2z e1) (ez2z e2)
| EZopp e => (-(ez2z e))%Z
| EZofI e => i2z (ei2i e)
| EZraw z => z
end.
(** [ExprP] to [Prop] *)
Fixpoint ep2p (e:ExprP) : Prop :=
match e with
| EPeq e1 e2 => (ez2z e1) = (ez2z e2)
| EPlt e1 e2 => ((ez2z e1)<(ez2z e2))%Z
| EPle e1 e2 => ((ez2z e1)<=(ez2z e2))%Z
| EPgt e1 e2 => ((ez2z e1)>(ez2z e2))%Z
| EPge e1 e2 => ((ez2z e1)>=(ez2z e2))%Z
| EPimpl e1 e2 => (ep2p e1) -> (ep2p e2)
| EPequiv e1 e2 => (ep2p e1) <-> (ep2p e2)
| EPand e1 e2 => (ep2p e1) /\ (ep2p e2)
| EPor e1 e2 => (ep2p e1) \/ (ep2p e2)
| EPneg e => ~ (ep2p e)
| EPraw p => p
end.
(** [ExprI] (supposed under a [i2z]) to a simplified [ExprZ] *)
Fixpoint norm_ei (e:ExprI) : ExprZ :=
match e with
| EI0 => EZraw (0%Z)
| EI1 => EZraw (1%Z)
| EI2 => EZraw (2%Z)
| EI3 => EZraw (3%Z)
| EIadd e1 e2 => EZadd (norm_ei e1) (norm_ei e2)
| EIsub e1 e2 => EZsub (norm_ei e1) (norm_ei e2)
| EImul e1 e2 => EZmul (norm_ei e1) (norm_ei e2)
| EImax e1 e2 => EZmax (norm_ei e1) (norm_ei e2)
| EIopp e => EZopp (norm_ei e)
| EIraw i => EZofI (EIraw i)
end.
(** [ExprZ] to a simplified [ExprZ] *)
Fixpoint norm_ez (e:ExprZ) : ExprZ :=
match e with
| EZadd e1 e2 => EZadd (norm_ez e1) (norm_ez e2)
| EZsub e1 e2 => EZsub (norm_ez e1) (norm_ez e2)
| EZmul e1 e2 => EZmul (norm_ez e1) (norm_ez e2)
| EZmax e1 e2 => EZmax (norm_ez e1) (norm_ez e2)
| EZopp e => EZopp (norm_ez e)
| EZofI e => norm_ei e
| EZraw z => EZraw z
end.
(** [ExprP] to a simplified [ExprP] *)
Fixpoint norm_ep (e:ExprP) : ExprP :=
match e with
| EPeq e1 e2 => EPeq (norm_ez e1) (norm_ez e2)
| EPlt e1 e2 => EPlt (norm_ez e1) (norm_ez e2)
| EPle e1 e2 => EPle (norm_ez e1) (norm_ez e2)
| EPgt e1 e2 => EPgt (norm_ez e1) (norm_ez e2)
| EPge e1 e2 => EPge (norm_ez e1) (norm_ez e2)
| EPimpl e1 e2 => EPimpl (norm_ep e1) (norm_ep e2)
| EPequiv e1 e2 => EPequiv (norm_ep e1) (norm_ep e2)
| EPand e1 e2 => EPand (norm_ep e1) (norm_ep e2)
| EPor e1 e2 => EPor (norm_ep e1) (norm_ep e2)
| EPneg e => EPneg (norm_ep e)
| EPraw p => EPraw p
end.
Lemma norm_ei_correct (e:ExprI) : ez2z (norm_ei e) = i2z (ei2i e).
Proof.
induction e; simpl; i2z; auto; try congruence.
Qed.
Lemma norm_ez_correct (e:ExprZ) : ez2z (norm_ez e) = ez2z e.
Proof.
induction e; simpl; i2z; auto; try congruence; apply norm_ei_correct.
Qed.
Lemma norm_ep_correct (e:ExprP) : ep2p (norm_ep e) <-> ep2p e.
Proof.
induction e; simpl; rewrite ?norm_ez_correct; intuition.
Qed.
Lemma norm_ep_correct2 (e:ExprP) : ep2p (norm_ep e) -> ep2p e.
Proof.
intros; destruct (norm_ep_correct e); auto.
Qed.
Ltac i2z_refl :=
i2z_gen;
match goal with |- ?t =>
let e := p2ep t in
change (ep2p e); apply norm_ep_correct2; simpl
end.
(* i2z_refl can be replaced below by (simpl in *; i2z).
The reflexive version improves compilation of AVL files by about 15% *)
End MoreInt.
(** * An implementation of [Int] *)
(** It's always nice to know that our [Int] interface is realizable :-) *)
Module Z_as_Int <: Int.
Local Open Scope Z_scope.
Definition t := Z.
Definition _0 := 0.
Definition _1 := 1.
Definition _2 := 2.
Definition _3 := 3.
Definition add := Z.add.
Definition opp := Z.opp.
Definition sub := Z.sub.
Definition mul := Z.mul.
Definition max := Z.max.
Definition eqb := Z.eqb.
Definition ltb := Z.ltb.
Definition leb := Z.leb.
Definition eq_dec := Z.eq_dec.
Definition gt_le_dec i j : {i > j} + { i <= j }.
Proof.
generalize (Z.ltb_spec j i).
destruct (j <? i); [left|right]; inversion H; trivial.
now apply Z.lt_gt.
Defined.
Definition ge_lt_dec i j : {i >= j} + { i < j }.
Proof.
generalize (Z.ltb_spec i j).
destruct (i <? j); [right|left]; inversion H; trivial.
now apply Z.le_ge.
Defined.
Definition i2z : t -> Z := fun n => n.
Lemma i2z_eq n p : i2z n = i2z p -> n = p. Proof. trivial. Qed.
Lemma i2z_0 : i2z _0 = 0. Proof. reflexivity. Qed.
Lemma i2z_1 : i2z _1 = 1. Proof. reflexivity. Qed.
Lemma i2z_2 : i2z _2 = 2. Proof. reflexivity. Qed.
Lemma i2z_3 : i2z _3 = 3. Proof. reflexivity. Qed.
Lemma i2z_add n p : i2z (n + p) = i2z n + i2z p.
Proof. reflexivity. Qed.
Lemma i2z_opp n : i2z (- n) = - i2z n.
Proof. reflexivity. Qed.
Lemma i2z_sub n p : i2z (n - p) = i2z n - i2z p.
Proof. reflexivity. Qed.
Lemma i2z_mul n p : i2z (n * p) = i2z n * i2z p.
Proof. reflexivity. Qed.
Lemma i2z_max n p : i2z (max n p) = Z.max (i2z n) (i2z p).
Proof. reflexivity. Qed.
Lemma i2z_eqb n p : eqb n p = Z.eqb (i2z n) (i2z p).
Proof. reflexivity. Qed.
Lemma i2z_leb n p : leb n p = Z.leb (i2z n) (i2z p).
Proof. reflexivity. Qed.
Lemma i2z_ltb n p : ltb n p = Z.ltb (i2z n) (i2z p).
Proof. reflexivity. Qed.
(** Compatibility notations for Coq v8.4 *)
Notation plus := add (only parsing).
Notation minus := sub (only parsing).
Notation mult := mul (only parsing).
End Z_as_Int.
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2009 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module reads and writes data to the Audio chip on Altera's DE1 *
* Development and Education Board. The audio chip must be in master mode *
* and the digital format must be left justified. *
* *
******************************************************************************/
module audio_codec (
// Inputs
clk,
reset,
read, write,
writedata_left, writedata_right,
AUD_ADCDAT,
// Bidirectionals
AUD_BCLK,
AUD_ADCLRCK,
AUD_DACLRCK,
// Outputs
read_ready, write_ready,
readdata_left, readdata_right,
AUD_DACDAT
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUDIO_DATA_WIDTH = 24;
parameter BIT_COUNTER_INIT = 5'd23;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input read;
input write;
input [AUDIO_DATA_WIDTH-1:0] writedata_left;
input [AUDIO_DATA_WIDTH-1:0] writedata_right;
input AUD_ADCDAT;
input AUD_BCLK;
input AUD_ADCLRCK;
input AUD_DACLRCK;
// Outputs
output read_ready, write_ready;
output [AUDIO_DATA_WIDTH-1:0] readdata_left;
output [AUDIO_DATA_WIDTH-1:0] readdata_right;
output AUD_DACDAT;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire bclk_rising_edge;
wire bclk_falling_edge;
wire adc_lrclk_rising_edge;
wire adc_lrclk_falling_edge;
wire [AUDIO_DATA_WIDTH:1] new_left_channel_audio;
wire [AUDIO_DATA_WIDTH:1] new_right_channel_audio;
wire [7:0] left_channel_read_available;
wire [7:0] right_channel_read_available;
wire dac_lrclk_rising_edge;
wire dac_lrclk_falling_edge;
wire [7:0] left_channel_write_space;
wire [7:0] right_channel_write_space;
// Internal Registers
reg done_adc_channel_sync;
reg done_dac_channel_sync;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @ (posedge clk)
begin
if (reset == 1'b1)
done_adc_channel_sync <= 1'b0;
else if (adc_lrclk_rising_edge == 1'b1)
done_adc_channel_sync <= 1'b1;
end
always @ (posedge clk)
begin
if (reset == 1'b1)
done_dac_channel_sync <= 1'b0;
else if (dac_lrclk_falling_edge == 1'b1)
done_dac_channel_sync <= 1'b1;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign read_ready = (left_channel_read_available != 8'd0) & (right_channel_read_available != 8'd0);
assign write_ready = (left_channel_write_space != 8'd0) & (right_channel_write_space != 8'd0);
assign readdata_left = new_left_channel_audio;
assign readdata_right = new_right_channel_audio;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_Clock_Edge Bit_Clock_Edges (
// Inputs
.clk (clk),
.reset (reset),
.test_clk (AUD_BCLK),
// Bidirectionals
// Outputs
.rising_edge (bclk_rising_edge),
.falling_edge (bclk_falling_edge)
);
Altera_UP_Clock_Edge ADC_Left_Right_Clock_Edges (
// Inputs
.clk (clk),
.reset (reset),
.test_clk (AUD_ADCLRCK),
// Bidirectionals
// Outputs
.rising_edge (adc_lrclk_rising_edge),
.falling_edge (adc_lrclk_falling_edge)
);
Altera_UP_Clock_Edge DAC_Left_Right_Clock_Edges (
// Inputs
.clk (clk),
.reset (reset),
.test_clk (AUD_DACLRCK),
// Bidirectionals
// Outputs
.rising_edge (dac_lrclk_rising_edge),
.falling_edge (dac_lrclk_falling_edge)
);
Altera_UP_Audio_In_Deserializer Audio_In_Deserializer (
// Inputs
.clk (clk),
.reset (reset),
.bit_clk_rising_edge (bclk_rising_edge),
.bit_clk_falling_edge (bclk_falling_edge),
.left_right_clk_rising_edge (adc_lrclk_rising_edge),
.left_right_clk_falling_edge (adc_lrclk_falling_edge),
.done_channel_sync (done_adc_channel_sync),
.serial_audio_in_data (AUD_ADCDAT),
.read_left_audio_data_en (read & (left_channel_read_available != 8'd0)),
.read_right_audio_data_en (read & (right_channel_read_available != 8'd0)),
// Bidirectionals
// Outputs
.left_audio_fifo_read_space (left_channel_read_available),
.right_audio_fifo_read_space (right_channel_read_available),
.left_channel_data (new_left_channel_audio),
.right_channel_data (new_right_channel_audio)
);
defparam
Audio_In_Deserializer.AUDIO_DATA_WIDTH = AUDIO_DATA_WIDTH,
Audio_In_Deserializer.BIT_COUNTER_INIT = BIT_COUNTER_INIT;
Altera_UP_Audio_Out_Serializer Audio_Out_Serializer (
// Inputs
.clk (clk),
.reset (reset),
.bit_clk_rising_edge (bclk_rising_edge),
.bit_clk_falling_edge (bclk_falling_edge),
.left_right_clk_rising_edge (done_dac_channel_sync & dac_lrclk_rising_edge),
.left_right_clk_falling_edge (done_dac_channel_sync & dac_lrclk_falling_edge),
.left_channel_data (writedata_left),
.left_channel_data_en (write & (left_channel_write_space != 8'd0)),
.right_channel_data (writedata_right),
.right_channel_data_en (write & (right_channel_write_space != 8'd0)),
// Bidirectionals
// Outputs
.left_channel_fifo_write_space (left_channel_write_space),
.right_channel_fifo_write_space (right_channel_write_space),
.serial_audio_out_data (AUD_DACDAT)
);
defparam
Audio_Out_Serializer.AUDIO_DATA_WIDTH = AUDIO_DATA_WIDTH; // This is 24
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4_1_V
`define SKY130_FD_SC_HD__AND4_1_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4_1 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4_1 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3B_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_V
/**
* lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
* keep-alive power rail.
*
* X = (!A | SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
X ,
SLEEP,
A
);
// Module ports
output X ;
input SLEEP;
input A ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X, not0_out, A );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_FUNCTIONAL_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module crypt_shift_salt_1(
input [31:0] L,
input [31:0] R,
input [67:0] K,
output [67:0] Kout,
input CLK,
output [31:0] L_out,
output [31:0] R_out
);
wire [55:0] Ktmp;
wire [47:0] Ktmp_in;
shifts_s1 shifts_s1_instance1(K[55:0], Ktmp);
Delay3_salt delay3_instance_s1({K[67:56], Ktmp}, Kout, CLK);
pc2 pc2_instance(Ktmp, Ktmp_in);
crypt_step_salt crypt_step_instance1(
L,
R,
{K[67:56], Ktmp_in},
CLK,
L_out,
R_out
);
endmodule
module crypt_shift_salt_2(
input [31:0] L,
input [31:0] R,
input [67:0] K,
output [67:0] Kout,
input CLK,
output [31:0] L_out,
output [31:0] R_out
);
wire [55:0] Ktmp;
wire [47:0] Ktmp_in;
shifts_s2 shifts_s2_instance2(K[55:0], Ktmp);
Delay3_salt delay3_instance_s2({K[67:56], Ktmp}, Kout, CLK);
pc2 pc2_instance2(Ktmp, Ktmp_in);
crypt_step_salt crypt_step_instance2(
L,
R,
{K[67:56], Ktmp_in},
CLK,
L_out,
R_out
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Rose-Hulman Institute of Technology
// Tom D'Agostino
// ECE398 CAN Controller Design
//
// Create Date: 23:00 03/26/2015
// Module Name: can_tx
// Project Name: CAN_Controller
// Target Devices: Nexys 3 running a Xilinx Spartan6 XC6LX16-CS324
// Description: Implements the TX portion of the protocol.
//////////////////////////////////////////////////////////////////////////////////
module can_tx(
output reg tx,
output reg can_bitstuff,
output reg txing,
input rx,
input[10:0] address,
input clk,
input baud_clk,
input rst,
input [63:0] data,
input send_data,
input bitstuffed_output,
input clear_to_tx
);
assign rx_buf = rx;
parameter all_ones = 15'b111111111111111;
parameter idle = 8'h0, start_of_frame = 8'h1, addressing =8'h2 ,rtr = 8'h3 ,ide = 8'h4, reserve_bit = 8'h5, num_of_bytes = 8'h6,
data_out = 8'h7, crc_out = 8'h8, crc_delimiter = 8'h9 , ack = 8'hA, ack_delimiter = 8'hB, end_of_frame = 8'hC, waiting = 8'hD;
parameter bytes = 5'd8;
reg[10:0] address_count = 0, crc_count = 0, eof_count = 0 , data_bit_count = 0, data_byte_count = 0;
reg[7:0] c_state=0, n_state=0;
initial txing = 0;
reg[14:0] crc_output, crc_holder;
wire one_shotted_send;
wire[14:0] crc_buff;
CRC cyclic_red_check(data, one_shotted_send, crc_buff,rst,clk);
OneShot os(send_data, clk, rst, one_shotted_send);
always @(crc_buff or crc_holder) begin
if(crc_buff != all_ones)
crc_output <= crc_buff;
else
crc_output <= crc_holder;
end
always @ (posedge clk or posedge rst) begin
if(rst == 1) begin
crc_holder <= 15'd0;
end
else begin
crc_holder <= crc_output;
end
end
//Update Logic
always @ (posedge baud_clk or posedge rst) begin
if(rst == 1) begin
c_state <= 32'd0;
end
else begin
c_state <= n_state;
end
end
//Counting Logic
always @ (posedge baud_clk) begin
case(c_state)
idle: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
waiting: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
start_of_frame:begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
addressing: begin
address_count <= address_count + 1'b1;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
rtr: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
ide: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
reserve_bit: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
num_of_bytes: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= data_byte_count +1'b1;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
data_out: begin
address_count <= 11'd0;
data_bit_count<= data_bit_count +1'b1;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
crc_out: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= crc_count + 1'b1;
eof_count <= 11'd0;
end
crc_delimiter: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
ack: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
ack_delimiter:begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
end_of_frame: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= eof_count +1'b1;
end
default: begin
address_count <= 11'd0;
data_bit_count<= 11'd0;
data_byte_count<= 11'd0;
crc_count <= 11'd0;
eof_count <= 11'd0;
end
endcase
end
//Next State Logic
always @ (c_state or rx_buf or data or send_data or address_count or bitstuffed_output or data_byte_count
or data_bit_count or crc_count or eof_count or clear_to_tx or crc_output) begin
case(c_state)
idle: begin
if(send_data && clear_to_tx) begin
n_state <= start_of_frame;
end
else begin
n_state <= idle;
end
end
start_of_frame: begin
if(!rx_buf) begin
n_state <= addressing;
end
else begin
n_state <= waiting;
end
end
waiting: begin
if(send_data && clear_to_tx) begin
n_state <= start_of_frame;
end
else begin
n_state <= waiting;
end
end
addressing: begin
if(rx_buf != bitstuffed_output) begin
n_state <= waiting; //Lost Arbitration
end
else if(address_count == 11'd10) begin
n_state <= rtr;
end
else begin
n_state <= addressing;
end
end
rtr: begin
n_state <= ide;
end
ide: begin
n_state <= reserve_bit;
end
reserve_bit: begin
n_state <= num_of_bytes;
end
num_of_bytes: begin
if(data_byte_count == 11'd3) begin
n_state <= data_out;
end
else begin
n_state <= num_of_bytes;
end
end
data_out: begin
if(data_bit_count == 11'd63) begin
n_state <= crc_out;
end
else begin
n_state <= data_out;
end
end
crc_out: begin
if(crc_count == 11'd14) begin
n_state <= crc_delimiter;
end
else begin
n_state <= crc_out;
end
end
crc_delimiter: begin
n_state <= ack;
end
ack: begin
n_state <= ack_delimiter;
end
ack_delimiter: begin
n_state <= end_of_frame;
end
end_of_frame: begin
if(eof_count == 11'd6) begin
n_state <= idle;
end
else begin
n_state <= end_of_frame;
end
end
default:
begin
n_state <= idle;
end
endcase
end
//Output Logic
always @(c_state or address or data or crc_output or crc_count or data_byte_count or data_bit_count or address_count) begin
case(c_state)
idle: begin
tx <= 1;
can_bitstuff <= 0;
txing <= 1'b0;
end
addressing: begin
tx <= address[11'd10-address_count];
can_bitstuff <= 1;
txing <= 1'b1;
end
start_of_frame: begin
tx<= 0;
can_bitstuff <= 1'b0;
txing <= 1'b1;
end
rtr: begin
tx <= 0;
can_bitstuff <= 1;
txing <= 1'b1;
end
ide: begin
tx <= 0;
can_bitstuff <= 1;
txing <= 1'b1;
end
reserve_bit: begin
tx <= 0;
can_bitstuff <= 1;
txing <= 1'b1;
end
num_of_bytes: begin
tx <= bytes[11'd3-data_byte_count];
can_bitstuff <= 1;
txing <= 1'b1;
end
data_out: begin
tx <= data[11'd63-data_bit_count];
can_bitstuff <= 1;
txing <= 1'b1;
end
crc_out: begin
tx <= crc_output[11'd14-crc_count];
can_bitstuff <= 1;
txing <= 1'b1;
end
crc_delimiter: begin
tx <= 1;
can_bitstuff <= 0;
txing <= 1'b1;
end
ack: begin
tx <= 1;
can_bitstuff <= 0;
txing <= 1'b1;
end
ack_delimiter:begin
tx <= 1;
can_bitstuff <= 0;
txing <= 1'b1;
end
end_of_frame: begin
tx <= 1;
can_bitstuff <= 0;
txing <= 1'b1;
end
waiting: begin
tx <= 1;
can_bitstuff <= 0;
txing <= 1'b0;
end
default: begin
tx <= 1;
can_bitstuff <= 0;
txing <= 1'b1;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_SN_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_SN_SYMBOL_V
/**
* udp_dff$P_pp$PKG$sN: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$P_pp$PKG$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_SN_SYMBOL_V
|
module sopc(
input clock,
input reset
);
wire rom_chip_enable ;
wire [31:0] rom_read_address;
wire [31:0] rom_read_data ;
wire ram_chip_enable ;
wire ram_read_enable ;
wire [31:0] ram_read_address ;
wire [31:0] ram_read_data ;
wire ram_write_enable ;
wire [31:0] ram_write_address;
wire [ 3:0] ram_write_select ;
wire [31:0] ram_write_data ;
cpu cpu(
.clock (clock ),
.reset (reset ),
.rom_read_address (rom_read_address ),
.rom_read_data (rom_read_data ),
.ram_read_enable (ram_read_enable ),
.ram_read_address (ram_read_address ),
.ram_read_data (ram_read_data ),
.ram_write_enable (ram_write_enable ),
.ram_write_address (ram_write_address),
.ram_write_select (ram_write_select ),
.ram_write_data (ram_write_data )
);
assign rom_chip_enable = (reset == `RESET_ENABLE) ? `CHIP_DISABLE : `CHIP_ENABLE;
assign ram_chip_enable = (reset == `RESET_ENABLE) ? `CHIP_DISABLE : `CHIP_ENABLE;
rom rom(
.chip_enable (rom_chip_enable ),
.read_address (rom_read_address),
.read_data (rom_read_data )
);
ram ram(
.clock (clock ),
.chip_enable (ram_chip_enable ),
.read_enable (ram_read_enable ),
.read_address (ram_read_address ),
.read_data (ram_read_data ),
.write_enable (ram_write_enable ),
.write_address (ram_write_address),
.write_select (ram_write_select ),
.write_data (ram_write_data )
);
endmodule |
`define bsg_dff_reset_macro(bits) \
if (harden_p && width_p==bits) \
begin: macro \
bsg_rp_tsmc_250_dff_nreset_s1_b``bits dff(.clock_i \
,.data_i \
,.nreset_i(~reset_i) \
,.data_o); \
end
module bsg_dff_reset #(width_p=-1, harden_p=1)
(input clk_i
,input reset_i
,input [width_p-1:0] data_i
,output [width_p-1:0] data_o
);
`bsg_dff_reset_macro(90)
else `bsg_dff_reset_macro(89)
else `bsg_dff_reset_macro(88)
else `bsg_dff_reset_macro(87)
else `bsg_dff_reset_macro(86)
else `bsg_dff_reset_macro(85)
else `bsg_dff_reset_macro(84)
else `bsg_dff_reset_macro(83)
else `bsg_dff_reset_macro(82)
else `bsg_dff_reset_macro(81)
else `bsg_dff_reset_macro(80)
else `bsg_dff_reset_macro(79)
else `bsg_dff_reset_macro(78)
else `bsg_dff_reset_macro(77)
else `bsg_dff_reset_macro(76)
else `bsg_dff_reset_macro(75)
else `bsg_dff_reset_macro(74)
else `bsg_dff_reset_macro(73)
else `bsg_dff_reset_macro(72)
else `bsg_dff_reset_macro(71)
else `bsg_dff_reset_macro(70)
else `bsg_dff_reset_macro(69)
else `bsg_dff_reset_macro(68)
else `bsg_dff_reset_macro(67)
else `bsg_dff_reset_macro(66)
else `bsg_dff_reset_macro(65)
else `bsg_dff_reset_macro(64)
else `bsg_dff_reset_macro(63)
else `bsg_dff_reset_macro(62)
else `bsg_dff_reset_macro(61)
else `bsg_dff_reset_macro(60)
else `bsg_dff_reset_macro(59)
else `bsg_dff_reset_macro(58)
else `bsg_dff_reset_macro(57)
else `bsg_dff_reset_macro(56)
else `bsg_dff_reset_macro(55)
else `bsg_dff_reset_macro(54)
else `bsg_dff_reset_macro(53)
else `bsg_dff_reset_macro(52)
else `bsg_dff_reset_macro(51)
else `bsg_dff_reset_macro(50)
else `bsg_dff_reset_macro(49)
else `bsg_dff_reset_macro(48)
else `bsg_dff_reset_macro(47)
else `bsg_dff_reset_macro(46)
else `bsg_dff_reset_macro(45)
else `bsg_dff_reset_macro(44)
else `bsg_dff_reset_macro(43)
else `bsg_dff_reset_macro(42)
else `bsg_dff_reset_macro(41)
else `bsg_dff_reset_macro(40)
else `bsg_dff_reset_macro(39)
else `bsg_dff_reset_macro(38)
else `bsg_dff_reset_macro(37)
else `bsg_dff_reset_macro(36)
else `bsg_dff_reset_macro(35)
else `bsg_dff_reset_macro(34)
else `bsg_dff_reset_macro(33)
else `bsg_dff_reset_macro(32)
else `bsg_dff_reset_macro(31)
else `bsg_dff_reset_macro(30)
else `bsg_dff_reset_macro(29)
else `bsg_dff_reset_macro(28)
else `bsg_dff_reset_macro(27)
else `bsg_dff_reset_macro(26)
else `bsg_dff_reset_macro(25)
else `bsg_dff_reset_macro(24)
else `bsg_dff_reset_macro(23)
else `bsg_dff_reset_macro(22)
else `bsg_dff_reset_macro(21)
else `bsg_dff_reset_macro(20)
else `bsg_dff_reset_macro(19)
else `bsg_dff_reset_macro(18)
else `bsg_dff_reset_macro(17)
else `bsg_dff_reset_macro(16)
else `bsg_dff_reset_macro(15)
else `bsg_dff_reset_macro(14)
else `bsg_dff_reset_macro(13)
else `bsg_dff_reset_macro(12)
else `bsg_dff_reset_macro(11)
else `bsg_dff_reset_macro(10)
else `bsg_dff_reset_macro(9)
else `bsg_dff_reset_macro(8)
else `bsg_dff_reset_macro(7)
else `bsg_dff_reset_macro(6)
else `bsg_dff_reset_macro(5)
else `bsg_dff_reset_macro(4)
else `bsg_dff_reset_macro(3)
else
begin: notmacro_dff_reset
reg [width_p-1:0] data_r;
assign data_o = data_r;
always @(posedge clk_i)
begin
if (reset_i)
data_r <= width_p ' (0);
else
data_r <= data_i;
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_dff_reset)
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
// No shared code for this OVL
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is not FALSE");
end
end
end
assign fire_2state_1 = (test_expr == 1'b1);
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
end
wire valid_test_expr = ((test_expr ^ test_expr) == 1'b0);
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
// No coverage for this OVL
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / IBUFDS_GTM
// /___/ /\ Filename : IBUFDS_GTM.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_GTM #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter integer REFCLK_HROW_CK_SEL = 0,
parameter integer REFCLK_ICNTL_RX = 0
)(
output O,
output ODIV2,
input CEB,
input I,
input IB
);
// define constants
localparam MODULE_NAME = "IBUFDS_GTM";
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "IBUFDS_GTM_dr.v"
`else
reg [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH;
reg [31:0] REFCLK_HROW_CK_SEL_REG = REFCLK_HROW_CK_SEL;
reg [31:0] REFCLK_ICNTL_RX_REG = REFCLK_ICNTL_RX;
`endif
`ifdef XIL_XECLIB
wire [1:0] REFCLK_HROW_CK_SEL_BIN;
wire [1:0] REFCLK_ICNTL_RX_BIN;
`else
reg [1:0] REFCLK_HROW_CK_SEL_BIN;
reg [1:0] REFCLK_ICNTL_RX_BIN;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif
`ifndef XIL_XECLIB
reg attr_test;
reg attr_err;
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign REFCLK_HROW_CK_SEL_BIN = REFCLK_HROW_CK_SEL_REG[1:0];
assign REFCLK_ICNTL_RX_BIN = REFCLK_ICNTL_RX_REG[1:0];
`else
always @ (trig_attr) begin
#1;
REFCLK_HROW_CK_SEL_BIN = REFCLK_HROW_CK_SEL_REG[1:0];
REFCLK_ICNTL_RX_BIN = REFCLK_ICNTL_RX_REG[1:0];
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((REFCLK_HROW_CK_SEL_REG != 0) &&
(REFCLK_HROW_CK_SEL_REG != 1) &&
(REFCLK_HROW_CK_SEL_REG != 2) &&
(REFCLK_HROW_CK_SEL_REG != 3))) begin
$display("Error: [Unisim %s-102] REFCLK_HROW_CK_SEL attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, REFCLK_HROW_CK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((REFCLK_ICNTL_RX_REG != 0) &&
(REFCLK_ICNTL_RX_REG != 1) &&
(REFCLK_ICNTL_RX_REG != 2) &&
(REFCLK_ICNTL_RX_REG != 3))) begin
$display("Error: [Unisim %s-103] REFCLK_ICNTL_RX attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, REFCLK_ICNTL_RX_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
// begin behavioral model
reg ODIV2_out = 1'b0;
assign ODIV2 = ODIV2_out;
reg [2:0] ce_count = 3'b001;
reg [2:0] edge_count = 3'b000;
reg allEqual = 1'b0;
// =====================
// Count the rising edges of the clk
// =====================
always @(posedge I) begin
if (allEqual)
edge_count <= 3'b000;
else
if ((CEB === 1'b0) || (CEB === 1'bz)) // rv = 0
edge_count <= edge_count + 1;
end
// Generate synchronous reset after DIVIDE number of counts
always @(edge_count)
if (edge_count == ce_count)
allEqual = 1;
else
allEqual = 0;
// =====================
// Generate ODIV2
// =====================
always @(*) begin
case (REFCLK_HROW_CK_SEL_REG)
32'b00: ODIV2_out <= ~(REFCLK_EN_TX_PATH_REG | (CEB === 1'b1)) && I;
32'b01: ODIV2_out <= allEqual;
32'b10: ODIV2_out <= 1'b0;
32'b11: ODIV2_out <= 1'b0;
default : ODIV2_out <= ~(REFCLK_EN_TX_PATH_REG | (CEB === 1'b1)) && I;
endcase
end
// =====================
// Generate O
// =====================
assign O = ~(REFCLK_EN_TX_PATH_REG | (CEB === 1'b1)) && I;
`ifndef XIL_XECLIB
//`ifdef XIL_TIMING
// "I" is actually a CLK so need I -> O/ODIV2 delays in functional as well.
specify
(I => O) = (100:100:100, 100:100:100);
(I => ODIV2) = (100:100:100, 100:100:100);
(IB => O) = (0:0:0, 0:0:0);
(IB => ODIV2) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
//`endif
`endif
// end behavioral model
endmodule
`endcelldefine
|
`timescale 1ns / 1ps
/*
-- Module Name: Link Controller Control Unit
-- Description: Unidad de Control para el modulo "Controlador de Enlace"
Se encarga de organizar los procesos de almacenaje de
flits y calculo de nueva ruta para paquetes en transito
a traves del router.
Forma parte del modulo "Link Controller".
-- Dependencies: -- system.vh
-- Original Author: Héctor Cabrera
-- Current Author:
-- History:
-- 05 de Junio 2015: Creacion
-- 09 de Junio 2015: + puerto de salida - routing_source_dout
+ maquina de estado FSM3
FSM1 maneja: write_strobe
FSM2 maneja: read_strobe
credit_out
-- 11 de Junio 2015: + Contador de paquetes y logica de
seleccion de origen de direccion {x,y}
*/
`include "system.vh"
module link_controller_control_unit
(
input wire clk,
input wire reset,
// -- inputs ------------------------------------------------- >>>>>
input wire header_field_din,
input wire transfer_strobe_din,
// -- outputs ------------------------------------------------ >>>>>
output wire write_strobe_dout,
output wire read_strobe_dout,
output wire routing_source_dout,
output wire routing_strobe_dout,
output wire credit_out_dout
);
// -- Parametros locales ----------------------------------------- >>>>>
localparam FLIT_COUNTER_WITDH = clog2(`DATA_FLITS);
localparam PKT_COUNTER_WITDH = clog2(`BUFFER_DEPTH/5);
// -- FSM1 Y FSM2 -------------------------------------------- >>>>>
localparam IDLE = 1'b0;
localparam ACTIVE = 1'b1;
// -- FSM3 --------------------------------------------------- >>>>>
localparam OFF = 2'b00;
localparam FIELD = 2'b01;
localparam BUFFER = 2'b10;
/*
-- Maquina de Estados Finito :: Recepcion de Flits
-- Descripcion: Estados - IDLE Y ACTIVE.
En estado de reposo (IDLE), la FSM1 se encuentra a la
espera de la llegada de un nuevo paquete. La señal
'header_field_din' indica la llegada del nuevo paquete.
Durante la transicion de estado de reposo a estado
activo (ACTIVE), la FSM1 emite un pulso de escritura al
buffer.
La FSM1 emita pulsos de escritura al buffer por cada
flit de datos del paquete (numero determinado por
DATA_FLITS - 1).
El contador de Flits es un restador para llevar cuenta
del numero de flits que se han recibido del paquete. A
traves de el se dispara el cambio de estado de ACTIVE
a IDLE.
-- Salidas: write_strobe_dout
*/
// -- Elemento de Memoria :: Contador de Flits --------------- >>>>>
reg [FLIT_COUNTER_WITDH-1:0] fsm1_counter_reg;
wire fsm1_counter_sub;
wire fsm1_counter_clear;
wire fsm1_counter_reset;
assign fsm1_counter_reset = reset | fsm1_counter_clear;
always @(posedge clk)
if(fsm1_counter_reset)
fsm1_counter_reg <= `DATA_FLITS;
else
if (fsm1_counter_sub)
fsm1_counter_reg <= fsm1_counter_reg - 1'b1;
// -- Logica de Estado Siguiente :: Contador de Flits FSM1 --- >>>>>
assign fsm1_counter_sub = (fsm1_state_reg == ACTIVE || fsm1_state_next == ACTIVE) ? 1'b1 : 1'b0;
assign fsm1_counter_clear = (fsm1_state_reg == ACTIVE && fsm1_state_next == IDLE) ? 1'b1 : 1'b0;
// -- FSM1 :: Elementos de Memoria --------------------------- >>>>>
reg fsm1_state_reg;
reg fsm1_state_next;
always @(posedge clk)
if(reset)
fsm1_state_reg <= IDLE;
else
fsm1_state_reg <= fsm1_state_next;
// -- FSM1 :: Logica de Estado Siguiente --------------------- >>>>>
always @(*)
begin
fsm1_state_next = fsm1_state_reg;
case (fsm1_state_reg)
IDLE:
if (header_field_din)
fsm1_state_next = ACTIVE;
ACTIVE:
if (|fsm1_counter_reg)
fsm1_state_next = ACTIVE;
else
fsm1_state_next = IDLE;
endcase // fsm1_state_reg
end
/*
-- Logica de Salida FSM1
-- Descripcion: FSM1 maneja el pulso de escritura de la cola de
almacenamiento en el camino de datos.
*/
assign write_strobe_dout = ((fsm1_state_reg == ACTIVE & fsm1_state_next == IDLE) || fsm1_state_next == ACTIVE) ? 1'b1 : 1'b0;
/*
-- Maquina de Estados Finito :: Liberacion de Flits
-- Descripcion: Estados - IDLE Y ACTIVE.
En estado de reposo (IDLE), la FSM2 se encuentra a la
espera de la llegada de la confirmacion
(transfer_strobe_din) de la consolidacion de enlace
entre el puerto de entrada y el puerto de salida
solicitado por el paquete.
Durante la transicion de estado de reposo a estado
activo (ACTIVE), la FSM2 emite un pulso de lectura al
buffer.
La FSM2 emita pulsos de lectura al buffer por cada flit
de datos en el paquete (numero determinado por
DATA_FLITS - 1). Al final de la liberarcion de todos los
flits del paquete, la FSM2 libera la señal
(credit_out_dout) para indicarle al router 'downstream'
que ha liberado un espacio en su buffer de paquetes.
El contador de Flits es un restador para llevar cuenta
del numero de flits que se han liberado del paquete. A
traves de el se dispara el cambio de estado de ACTIVE
a IDLE.
-- Salidas: read_strobe_dout
credit_out_dout
*/
// -- Elemento de Memoria :: Contador de Flits --------------- >>>>>
reg [FLIT_COUNTER_WITDH-1:0] fsm2_counter_reg;
wire fsm2_counter_sub;
wire fsm2_counter_clear;
wire fsm2_counter_reset;
wire credit_out;
assign fsm2_counter_reset = reset | fsm2_counter_clear;
always @(posedge clk)
if(fsm2_counter_reset)
fsm2_counter_reg <= `DATA_FLITS;
else
if (fsm2_counter_sub)
fsm2_counter_reg <= fsm2_counter_reg - 1'b1;
// -- Logica de Estado Siguiente :: Contador de Flits -------- >>>>>
assign fsm2_counter_sub = (fsm2_state_reg == ACTIVE || fsm2_state_next == ACTIVE) ? 1'b1 : 1'b0;
assign fsm2_counter_clear = (fsm2_state_reg == ACTIVE && fsm2_state_next == IDLE) ? 1'b1 : 1'b0;
// -- FSM2 :: Elementos de Memoria --------------------------- >>>>>
reg fsm2_state_reg;
reg fsm2_state_next;
always @(posedge clk)
if(reset)
fsm2_state_reg <= IDLE;
else
fsm2_state_reg <= fsm2_state_next;
// -- FSM2 :: Logica de Estado Siguiente --------------------- >>>>>
always @(*)
begin
fsm2_state_next = fsm2_state_reg;
case (fsm2_state_reg)
IDLE:
if (transfer_strobe_din)
fsm2_state_next = ACTIVE;
ACTIVE:
if (|fsm2_counter_reg)
fsm2_state_next = ACTIVE;
else
fsm2_state_next = IDLE;
endcase // fsm2_state_reg
end
/*
-- Logica de Salida FSM2
-- Descripcion: FSM2 maneja el pulso de lectura de la cola de
almacenamiento en el camino de datos, y la
salida de creditos al router 'downstream'.
La señal 'credit_out' es utilizada por la FSM3,
sin embargo, la misma logica maneja la salida
'credit_out_dout'.
*/
assign read_strobe_dout = ((fsm2_state_reg == ACTIVE & fsm2_state_next == IDLE) || fsm2_state_next == ACTIVE) ? 1'b1 : 1'b0;
assign credit_out = (fsm2_state_reg == IDLE & fsm2_state_next == ACTIVE) ? 1'b1 : 1'b0;
assign credit_out_dout = credit_out;
/*
-- Logica de Manejo de planificacion de ruta --------------------- >>>>>
-- Descripcion: Logica para decodificar la direccion destino de un
paquete. La direcion {x,y} puede obtenerse
directamente del canal de entrada, previo al
almacenamiento en la cola, o puede obtenerse de la
salida de la cola de almacenamiento.
Cuando la cola de almacenamiento no tiene paquetes
pendientes, el planificador de ruta es configurado para
(routing_source_dout = 0) utilizar el campo 'destino'
del flit de cabecera para el calculo de ruta. En caso de
haber paquetes en espera, al finalizar la transmision
del paquete en turno, el nuevo proceso de calculo de
ruta se lleva a cabo con el flit de cabecera a la salida
de la cola de almacenamiento (routing_source_dout = 1)
en lugar del campo destino del canal de entrada.
El proceso de calculo de ruta es desencadenado por los
siguientes eventos:
* Llegada de un nuveo paquete
* Paquete pendiente en cola despues de la
finalizacion de transmision de un paquete
anterior.
No se utiliza una FSM ya que las condiciones de disparo
de calculo de ruta se pueden deducir a partir del
contador de paquetes pendiente.
-- Salidas: routing_strobe_dout
routing_source_dout
*/
// -- Elemento de Memoria :: Contador de paquetes ------------ >>>>>
reg [PKT_COUNTER_WITDH-1:0] packet_counter_reg;
reg [PKT_COUNTER_WITDH-1:0] packet_counter_next;
wire packet_counter_sub;
wire packet_counter_add;
wire zero_packets;
always @(posedge clk)
if(reset)
packet_counter_reg <= {PKT_COUNTER_WITDH{1'b0}};
else
packet_counter_reg <= packet_counter_next;
always @(*)
begin
packet_counter_next = packet_counter_reg;
case ({packet_counter_add, packet_counter_sub})
2'b01: packet_counter_next = packet_counter_reg - 1'b1;
2'b10: packet_counter_next = packet_counter_reg + 1'b1;
endcase //{packet_counter_add, packet_counter_sub}
end
// -- Logica de Estado Siguiente :: Contador de paquetes ----- >>>>>
assign packet_counter_add = (fsm1_state_reg == IDLE & fsm1_state_next == ACTIVE) ? 1'b1 : 1'b0;
assign packet_counter_sub = (fsm2_state_reg == IDLE & fsm2_state_next == ACTIVE) ? 1'b1 : 1'b0;
assign zero_packets = (|packet_counter_reg) ? 1'b0 : 1'b1;
reg pending_routing_reg = 1'b0;
always @(posedge clk)
if (fsm2_state_reg == ACTIVE && fsm2_state_next == IDLE)
pending_routing_reg <= 1'b1;
else
pending_routing_reg <= 1'b0;
assign routing_strobe_dout = (fsm1_state_reg == IDLE && fsm1_state_next == ACTIVE && zero_packets && fsm2_state_reg == IDLE) ? 1'b1 :
(~zero_packets && pending_routing_reg) ? 1'b1 :
1'b0;
assign routing_source_dout = (|packet_counter_reg) ? 1'b1 : 1'b0;
// -- Codigo no sintetizable ------------------------------------- >>>>>
/*
-- Simbolos de Depuracion
*/
reg [6*8:0] fsm1_state_reg_dbg;
reg [6*8:0] fsm2_state_reg_dbg;
reg [5*8:0] pck_count_reg_dbg;
always @(*)
case(fsm1_state_reg)
IDLE : fsm1_state_reg_dbg = "IDLE";
ACTIVE : fsm1_state_reg_dbg = "ACTIVE";
endcase // fsm1_state_reg
always @(*)
case(fsm2_state_reg)
IDLE : fsm2_state_reg_dbg = "IDLE";
ACTIVE : fsm2_state_reg_dbg = "ACTIVE";
endcase // fsm2_state_reg
always @(*)
case(packet_counter_reg)
2'b00 : pck_count_reg_dbg = "ZERO";
2'b01 : pck_count_reg_dbg = "ONE";
2'b10 : pck_count_reg_dbg = "TWO";
2'b11 : pck_count_reg_dbg = "THREE";
endcase // fsm2_state_reg
/*
-- Funciones
*/
// Funcion de calculo: log2(x) ---------------------------------- >>>>>
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
endmodule // link_controller_control_unit
/* -- Plantilla de Instancia ------------------------------------- >>>>>
wire write_strobe;
wire routing_strobe;
wire routing_source;
wire read_strobe;
wire credit_add;
link_controller_control_unit unidad_de_control_de_control_de_enlace
(
.clk (clk),
.reset (reset),
// -- inputs ------------------------------------------------- >>>>>
.header_field_din (header_field_din),
.transfer_strobe_din (transfer_strobe_din),
// -- outputs ------------------------------------------------ >>>>>
.write_strobe_dout (write_strobe),
.routing_strobe_dout (routing_strobe),
.routing_source_dout (routing_source),
.read_strobe_dout (read_strobe),
.credit_out_dout (credit_out)
);
*/ |
`timescale 1ns / 1ps
module test_spi;
// Inputs
reg clk;
reg miso;
reg[7:0] data_in;
reg ready_send;
reg rst;
// Outputs
wire mosi;
wire sclk;
wire ss;
wire busy;
wire[7:0] data_out;
// Instantiate the Unit Under Test (UUT)
spi uut (
.clk (clk ),
.miso (miso ),
.data_in (data_in ),
.ready_send (ready_send),
.rst (rst ),
.mosi (mosi ),
.sclk (sclk ),
.ss (ss ),
.busy (busy ),
.data_out (data_out )
);
initial begin
// Initialize Inputs
clk = 0;
miso = 0;
rst = 1;
// Wait for two clocks for the global reset to finish
@(posedge clk);
@(posedge clk);
rst = 0;
data_in = 8'b00010011; // 13
ready_send = 1;
@(busy == 1);
ready_send = 0;
#1;
// 37 8'b00110111
miso = 0;
@(negedge sclk); miso = 0;
@(negedge sclk); miso = 1;
@(negedge sclk); miso = 1;
@(negedge sclk); miso = 0;
@(negedge sclk); miso = 1;
@(negedge sclk); miso = 1;
@(negedge sclk); miso = 1;
@(busy == 0);
@(posedge clk);
@(posedge clk);
@(posedge clk);
$finish;
end
always #5 clk = ! clk;
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon May 12 11:42:56 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/mono_radio/ip/multi_QI/multi_QI_funcsim.v
// Design : multi_QI
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0,Vivado 2014.1" *) (* CHECK_LICENSE_TYPE = "multi_QI,mult_gen_v12_0,{}" *)
(* core_generation_info = "multi_QI,mult_gen_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=7,C_A_WIDTH=16,C_A_TYPE=0,C_B_WIDTH=16,C_B_TYPE=0,C_OUT_HIGH=31,C_OUT_LOW=0,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}" *)
(* NotValidForBitStream *)
module multi_QI
(CLK,
A,
B,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
input [15:0]A;
input [15:0]B;
output [31:0]P;
wire [15:0]A;
wire [15:0]B;
wire CLK;
wire [31:0]P;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "0" *)
(* C_A_WIDTH = "16" *)
(* C_B_TYPE = "0" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "16" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "7" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "31" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
multi_QImult_gen_v12_0__parameterized0 U0
(.A(A),
.B(B),
.CE(1'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* ORIG_REF_NAME = "mult_gen_v12_0" *) (* C_VERBOSITY = "0" *) (* C_MODEL_TYPE = "0" *)
(* C_OPTIMIZE_GOAL = "1" *) (* C_XDEVICEFAMILY = "zynq" *) (* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *) (* C_LATENCY = "7" *) (* C_A_WIDTH = "16" *)
(* C_A_TYPE = "0" *) (* C_B_WIDTH = "16" *) (* C_B_TYPE = "0" *)
(* C_OUT_HIGH = "31" *) (* C_OUT_LOW = "0" *) (* C_MULT_TYPE = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_CCM_IMP = "0" *) (* C_B_VALUE = "10000001" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
module multi_QImult_gen_v12_0__parameterized0
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [15:0]A;
input [15:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [31:0]P;
output [47:0]PCASC;
wire [15:0]A;
wire [15:0]B;
wire CE;
wire CLK;
wire [31:0]P;
wire [47:0]PCASC;
wire SCLR;
wire [1:0]ZERO_DETECT;
(* C_A_TYPE = "0" *)
(* C_A_WIDTH = "16" *)
(* C_B_TYPE = "0" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "16" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "7" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "31" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* secure_extras = "A" *)
multi_QImult_gen_v12_0_viv__parameterized0 i_mult
(.A(A),
.B(B),
.CE(CE),
.CLK(CLK),
.P(P),
.PCASC(PCASC),
.SCLR(SCLR),
.ZERO_DETECT(ZERO_DETECT));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
AQtwTyGLz0NMO7LyR9Lhuv2cA/4y5ZLMBit+QBleYFW8IhTeXqKPD4aSeseNMhUuoCyqQPHKXbmX
LeVqKxvarw==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
hGVhv3AqeDsw7H+uancFjD279XefBZ3mwEBxW5pFk8a3sVNt7IAIfyXMtmp6XBWsae0N+Ci3/npB
3SasZ2GaBZBVMxZwKr7R+ZnX6uwtyrN2AJndaqNaMftiUp9xtV76bCQ9uH42U+M2x7hR4dtD0fvB
LYvzs92V+0bNZbbueyA=
`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
Rwsa6WOnTwbkSOakIUUGDzVbehno+eVI6KtkIdY5kK8lPoN8q0Kbk8vzYaFYPqtx24HeGf2fCrmL
UEBJpMMEdeDUWeTdVGVDGgJQqfSETdgcbKy251IhCrCQqWqIbqijbXpSb31jgoi6iOsGmyPpR2m6
gAug5BKSALEa3o/asLI95p58SZhkaUpFyJnRspVoLL7h+r+QTO86y/MjL1M2HHbiMVbK85YFLHSo
hReZLGxbL6QQS1znPiQyyVy1PkLupBaKBDXojs4pIX8/CiwzGsFTCtFrmYLQ0UqfaMo1P+9NS07F
kOR3KwphHArLEZjIth7K0OygkOWzpexPymT/LQ==
`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
GFpv4P68gj6yK06WrGFskDzgRibsxHI5jWrB5NNgR5jAhsQi6zUtxk9D39KKYeNXJovsaANReMqt
hhf/9kQFTUB17gOOYbYVuZ5Jw0U+jkdJ3RB0GtDnyrRDOZ5DC6YyDUkB2r6PLs+CT20zanhxcEtl
sQKOEnL6phaWOedi7es=
`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
c6+3pMI4bZ2mi2A6Ycj7+UeOiarlb+GAsf/fjV00iWC1qCUggxIKRxP+eJ3z6XT4BZPrG1RsEhpx
pNg3X+Fuqp0RwnM/yLWB2Ltk447QmP19vCUIvCHgqjPtI7kt0WbjsDqel6aoZNnpmEL/7gd6/3NS
nhA3XQ5QMumSsq/7bmoNg9hBobg7U7jlCr+9ZUf82X7MkdUEYGN/bzCmelYTt68FJ8ZlCW3h4ve+
YiX/yE5WOCAsimsuL0TKSZhntBGdjxuGpkF0yYXDh6gl9KfRWWkqdZXIh2qUMADKH/9YGGslBS9G
GFME+3dogZLUU37G226tsYdPFlDiwh9fU/p8oQ==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
LwVO4KRNMJcNWYurNoxwW3iLzFuFDOmAwtBGPfa0c3Jh2ohRvRLPwKncQWj9XSjN/reySM9eYk4ayGf424ISiFRoHi666WZUt3bn3SidrKzTNwKQ4k3WSqBXkJVWAVdu1P4YBnU+kyK0s92eFsmkCoIPK/4Z06KCiSdl/eMdoSFzk0nw1RjVWn1SOUPZlmToAja4in9ICn3Gk/Y3/NluSiNDBy0d6ARPYs9FCW55d7P26KLZYe+2y2fG3nfDBo1Uu9o0LczB9teTEAYVXEF8+la9egHjVFV0Xc8aywTvhdtoEj9K1eWt+c/fycuCnXDrnTyOPFA4dW+GoJFelY5QPw==
`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128)
`pragma protect key_block
Dap4xv9wi2ghIdYA69sO4k/rskd9QpOTATineSgPr9CTPtWwlArqa5lLKBwXERhdXY9Myi6aEehpnv1szx+0Lgpo7CXl3YVQZ0yJ+bTmtmVsk+IXuw8yNLOh8ehN7wJBr9E1gIiIWXnT1YkeU1URObREZ3adJSj7X69bTkvyDH8gCbZQ0sx4W4f5KT34TEBD9tGtOCJSsuvDsGnDnWudXBsA5nt7mogiUKbC2PVGaWXgWl5Ux1JrVCeajsNt7xSrfXMEj7pdDaCKiD+89px2rgxQwAIU8nW8j2shSjmIY//8B0jsMYp+P3KK7lAQyzezwuPKnbk0avwwNfwi+me7AQ==
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 435472)
`pragma protect data_block
WQ1WbvSazSBZdqBEfLnpEyn2gTH8LwkEB9Gpti6exKz/8LYOBwIuqMsedV/drhGz0PkEKpexqrJg
fHO6uYnAfJ3hADzJWLuGhSvAZ8EseslT22szS3CAeV6rwbw1j1bqxCtloQsWaDe9zyaqF/MYiv07
AvYEBfc6USdAT9xGv5nTspTiHcebUCjWTuVIsbt9GHBe6gRqqRYZMeo5XHwcJj8wckSZfInoVrdM
VqXOSNpWzopkYhiVcTX12kMwA+djzCfwsEFmx5IM+tDm/FGUPC0ruK74EIzoBcmZrhO+GMHbOBQo
BXPdwXB76IhEIGRiV4duZfqPHQJOUe5OUS9r1yAZPyGGa07rURhyBEEi7NP9bxQgt8lYF5lBN6WD
2j+2lNmlwF+7sBIwXdVUjhvg1zenbAEbcvP7Z7+C7r4lLkOS5UmfmZ8Y32q8by9G57uAOVIL0fW4
dDFcI2hfzdbdVRlB7IParrtojBXJ8iBoLCf/99nmeNJDm5WCgKnu+yPirit+2WTC6giXumLPiV+k
N0bMt8Stb0L6h19uXzdYfk/rsUWdOrK/4TWDcw0YenAYRc3DeZISDV8Hl+Tst81VW+dsbU9Xhm8u
vAhg5RZDqhGk2BKGb63KPfOe6oKE9TrVurdHMez/1CcEoHmpnxvVzrYjXEuUVbBIVugRWzrOlGO8
yRNNVTeaBm/vqhkbXIg/Jt4OwmGNapQeffiHb1sed7SkjPX5A3jKohbn9hW2qnS+RS0bvfr67adS
BX5GgFm4/JOa5CWCluFLdqcJblv+epxtV6BsJ8xcloEd5tjzi1vsFigpe30W4SZX9k/nN3aW6/0Z
5UYAX/j2MBom/plXyPi0EfNDtJC2IeizmGF5hRYYIsRLr5R+5IreYTrHjT+ZGQDeekIOMEI6rJRr
p8+3iDNHY5TxPiSq0qwU6p2I03g9S1CEMRSQrBnTd1kNxyhzSOSYszQVpMWN04p/Xk73Oq+sMofg
s+niLZoyx+8COHshMZ1y6phRNHmGJLSvROkAfoK9kSi0Mhf5DbRzR/H/FbQWrjLqaLa/6NqW/Dgc
BhkFHX4CUcaVkbZlsgv/Ln8fo2GS6JJV1kUwHlIPxO8Qtr/po+/dMi3mjF0kJvyE+RcCe6VASmlB
8kXtKlX8L0tQQBy/idy7r9fXQqBiDxFK+WR/tLD5zd/veAalfg67eev6EcuBueBdu5504PfdFAnb
sGL23i40Exq6rxoss9Q4hQaKq4Kz9kKEYIyhhYrrbrQ4Qs3yXLw9fEvBZ46hkWpGukWFsolHKwZE
ohYTztacjfotQXoiJIS5mq71hBnX7UhZ9T+5/iPp5tpVHplswoeWzAvUO/Fh9AY/NabBR8gIR3nf
aJu5mweLu+lRzXdpjGnaxOhoHcrhQxoyhsnynnT5EQIKL+J3TnF4Q2MDVEplUwrHRnRa0cK6gg2p
xW6L2OmPl1FRBb4caxqHHZawOgx0vT+IMz5MkyqJoNfrZnNpMrX/TIOzDvHVx31M2r99fPSD32oD
6fzQhI9ATblvsRHLKKe3JUxSttSW2rfeXyp2lFTiE6y5YEFRRdEXKjbPdnQPupbV8AC8Dbv4LeEg
Zntnh2EZRhiH0HyQpGtDQ5XvBIJgGCMMDCfDtVqx+5Lmty4ZQQHl2WOZjJUJXH9YsL8awzOn1LHT
Wvcz8ixRfvHoXOL3eh2XvdmRVrjug1TuSu93yEnhWWsNcms2Y0WzhLGt/PjsiDqBRMsybYraEbUw
thJoDzvNLpgbrj9oXj5RgWSXHC5RVQQKanb9e5Sku5tpGxnD6clg0qw1JJr22mURsL8XXOsKktFv
2YBKmANfIOP4dSIgIg8cMbLN8mrGXfMKVVMZOgJOYtNjI+GfHKNkFz0XcIVBulWhV1wJ7eOYuKqv
DRwJSe9xvLpVDmLKLas6XZCNI3NnLSQpgnZgE1MZJ6ZwSpuKSybxTLTJWMJos2jZxIL1XihIWX/X
Mh+8Ri51fAIutwho1IntPWiXBAOlen/xsjF/klAweSs1uzpdaiYa/FEs3+RZN83CMrSrhlwhOu/t
PLHq8yC5H5go5bBHIJEzn0f8cI100rpe5KAPy4/QvvACOmfexXwXmGYmgyaogvu7+Ox+G0u6BOaq
mMcLfxdCtCIk6o9QZtN3i94M/XM0Sv7IZSFJ+krXzDUF9lyWXqlnubRP7p58XAuGC0lyqkkavF3S
0072Wru8UFl+qhAQeO65xFEVYJEr3x1owZF/rq1dycNWKszZH9ik2JUlyr8RwtNNmEg4B7731dP8
2h8x/jgytHJZ0hjT4VEJFGW5dv8T/WTb4qVqoBAneA1QS3tcc0mww844FjWAsZz/8+f2/fsWQvlS
2enUFE9uotQHYmYjjqWE9CUGNR/CcxDqTEq5RQK3OmvDqKAcfkRiJw1Tzv5ovUmqx9oSXryrKoW4
WdZd2WqmDnrbGr4U771y7xUA5C4tjJAtmoh0vgoFqJn6QaTSS6uUiPzVwG4qNg60eCvNudveiZjh
QLHgsrjgD266SzKVYlDkEBWlVchFtQeTfltn/nPtzxsQCOdYHt5Dvtqi0CgvAkdB3XtVYcdwaIwv
8ZvIGC34sw8cSkGxlBzOROJYJuMCcq1G84CdSCCq3DmbGsy0i928LIyWZz37tXgT5sPAmKuMDWN3
x6vkioyNgSCtqZ0h+Jn+hkpm/hEtVUtl81qm8gRL6iCBcvOFq+j3NuzjmoliNu5eXOXhFw//W6kL
5p1b7v476qAmLs7BiXeJKV/0CHqZmiJdC5z5J6rO9RCNAtGx+5ijw/bpjZJNk22ZBzXjrJ9/vgBp
SrfADTInVfn40zn7uyw08uIsukWc+IeYnNk3iLnoN0/awlopsXdJ0YN9oAJcSi15d5EsPTA8Vc2q
gP8x+krwc0+IIA4RCmMD4Dz8hPu6KmOVDrp4mfsguiY0Z7OaO46j9AExFu7L66NQ81Q60qxR0/jU
TNm2hU6ObVjCctgkNH17dUC+lHpBtDLz5B6H38qwnVOTTnZHPI1dsiRq4cW0WV4Z5PHjnOoor30d
QWg/62i0uEkL/USnLErNfkKgWyiO1UVyd6lKo64siy4HJBcY2Aq4joNGxRZuDuQAlelvQ5QOwO/i
BSf/bructFM86eS1A3wGw1VNLLBtgED0qG7Mc0/Rj9yOg/7qnq6MX1ggDDQ6Q7zgKenawGEdi35h
G5wfGBAQSxVJM2N3JlhAAud0UppXc1VhEpHDQKjQiJcpmk8UgfR8ThW2uXtEbmJxk/l7RouZ2uHw
A4WnYUIHupQWWVjgzANuRAOUqNzK0juKZQ1yKRxF12iADcyaCZv/kpUZsf0aGdwxWw2cHvFIWGV8
fzdPHPOwB1gUgtPNs/0P05pn8NPvDcK1E2gBHpPwnOlObbJTN34HceqcoYa76Q0YHMZkOcgEz18f
V9FKzaeEJXdWbqyFsRSKyhmuRqENtgPQAt0+w5w7Gy7sm3N/st6ksDvMSRiNWLQvdHr5BrJ3Twjf
t+UjBQt3fJrMhTvUE56c+CmjS4suDpgHOOX/ZKG+GqNeruUKBZung745N3yv7nCn+ErwWNXEzk/U
q5GSq/PetzhOSNPVRPVw1Q46k8iodn/WFC89/mOyNeWeZDe8TofNs01BsAh9nIhAbxQjGeUXrMry
Qy/JgJ2G/iIn5SFmaIOwDvDZnidrWfxbDZ49XcEslWSLfAqSltObjk5ArGksVoBvfLIPn/egqucX
KUYhr6B692F7oVu2Sg2Lpa+3dgRnMVFSnZW8FWhdFJceNSUa9V91OaWlrXwAoE1y6ICEAN61h3PC
F7bqu3v4iHYWSXXdIdY5e/vy3FncdCUzYN4v+g5BMJDA0DgeCRb17z6HuGNb0hZoRxicmvKXGd22
hbG/HZNi7H8e9J6goz0xJxr3lZwLIkX+J8oH9wR3NoUJZKvld1ikqJUbAcszvKh74SpN+M1MQ4yi
bgktQ4Ok8B50DdJv0xwoC5fLpxnWlrrIAbl+7XLGDoucTpTek6Zh3feGSWifPG0+NAelnVm9odSf
Z/EMRiyR02lTrPFQH694YmTGzoe0pnGrALNXIUhB+B2+WN9M6mGtzS3OWtrEc3ZITi9nFZ5R6W9y
vzVIIB56wXFtV8NU+2ubx4+l2YV9EuIjadEoyygtzs0Qkg2hR43wg8rReB25YL8c43c4OqRcvjL3
Xy2NgenjaGtrzf2g60TO//UU3VEDIO9yYveCM7g0DqC1sjaWIYPJni5mceVMH5AGkG+MuCGIHEr/
ea2TNtOv+wQqUbICrkcEtIfL0OESG5BTizGU7k2nQVdGiDQ6mqHyEAi/dP4UDCMh2TGkRmopvrEk
8DE0tpQbx1FVtnEJvevIKeHldn5AoI4AN5ZTZp4bFOpjMMbkpSgo7mEsbQew2g9JK8q0mGVh+XZf
VcsOEunso3ZMuGdbq1NTtD0O9zg4DsQCOSzBYdgQrK1YlrcYnNvOqtNrSLc9saReRBkOKKILXTNe
fIzNWa4OKthI5q/DtUT5q4L3QMrGKiUFBPnajklNOS4YyWBFQsU9oFN30s5Z63gD4ZfXRPg/WRP3
iKCXejmX3ZtZRZy93YgKzg+5RdYJgYTo9fOgG1uCn/HCLx48stlqi80pswBdv+KM78v2X686RUmD
Izqh9byDh3/j3nGAZYHdnSUTElEeV4amANuWPpMUfCR9CvUPXvI0WxKk1f53QylTz3TyF7Go+mtK
sp8OFg6P7yw5L37wd9sgmaHY/yMzPrpNj4gYqV3V2c4uOKfkkoP9yb+J2D7DYYsTCkQJIvdpv6kO
scj/KAGRdCzh6iyFAj7NBREQ994wbZhA5ssTBYDN9r+t4jm8n4aGx9zj7Zc2PN7aaAqRZNmdHpyx
sCJR5GzqzijScnubYQcRCvmgVaM5bPwzYErHRYh0b/dl4U4Jg5aT0yNEkCsGqFMMO9Mmcz04PtNg
G3IdfWczKnAAndmKmu0MHGCrXnof1+JhwAxruumJPnX1q6+zAOGfoFZW78HXOoDfSbrhIaRiijOG
y1c4Z06vd9lORVkIghbT+xlg81g2duoXDANOyZbWHdq05HP/9Nda3PdPOtrv7fmANg7cFCnINYKn
sBk926gWH98U9Z0dFxTv8yGFLn7P4kvkyHE0HSI4k/7eKvz0M0neqO8wGl8SR5s7CSKL3GErQfDD
sopMlSF7XQmgPeclOMNAYbtFSsMI1TK/9CtH7QE1uhWJ7pTbxeIDZRyU8TEXgw/Z3fQ2dn+rhWU8
6MldNdVTIcdGjrxa4V2W2E4hpK3aXgvKFtiyJZYZHFTZy6ByqqNQkbjZfqtIJdYj7RcZvJ9Aqy3q
q0SvIUnrymAvjOMQyeCBekfuVQEqq2RqHoOcIf/PWrA9MOoeyQ5rCNgo65JgNNmq9VtAly553jSq
ntVk0V/zT2FeFLtC8P4Yv1y2HJI1gon7oIHUeEI87KI3BXlhFykiN7cHSGgn1PJxU8jSTlEM26il
fWq6eRzxjZ0qCA+jqppyvkNWFyH0+1Kup0qCRkcKn5LUGaCHoz6fFKsFVnkuyma9SYvuARPkbE75
GchKegr2+LfPtCLWlPCliAYYiOVUVoLVIJuDqz7uhDWMT2lw+DjqfHTtVX5eVW3NkIzPvhoIwCzo
8ISuu/ZNzhHRkOM28YbZSiwKqwriScQYEI5GqHErj16Xfl5/haQPaUUV7JklnP9DFl6zY7FYxvkL
URO3OX7d/wxPcNh1hV/hC9f8xycHqDaIQYxXNNWBVbOi1wjgjn88T9jZTtFUMbADmAxwkoxnkMmC
xyjB1wLnnMGONpOMmn2KSByrmCuijqf44CL/9Ys2zG71G1JffK7reJB2h+I+gpPs6vuETtT7cU2+
K5bTyGekcIFguieXFA64B18/lhPk1/oNmetDvt/vvfmYB7DPRmTafoYH6kww4ODfe9kNU5hv2Flt
ZyFBkNILfHz5JIMqEmu2Yb/h9PkU+Hpqx1MyeO5OdpRT2VQxrnmDtPnPNBMEOXC7eyH/eUmZGHpo
4gObDRDzEwU4XakyhKFntGDIdHNmyEEkzXOrYMurtvOKDiN0rzNrrcHcdKRVw1U3OYanCmF/GlBX
W/ELoBWjbhDkCOMQuve0gmRBYTe/8PRFmn381wIFRCajJPHHT3FTUE6vofdGSxA4Fnr4pEpTCxOG
uPQFjPsDAsdAWLTdaJ65VB+GYXr9GzX3zhEoikY4VoxDUgEmgMRbi2OF5p6jsWcujNbhewHw9j0l
hUAcutb6bPVvlGbWYk31Dgwz85a87th3TZSUpPPC9whRYvZhlE1dpNfPG0BM+o14SWmEWulGCEYC
Q63aLDZsNp4yqz1cGpHMLBNZPn4om7asDjId0SUmJzukVGRiy7JWbdBcW6E5isMjjKMLZG0YVtlj
+b/NKOMqH6GQfn3wq+ZLfVdi2fJWZPktF7E2pE3H4UaMZHDGUhx78QxvvGB1gd97ozFikPCT4mM1
kjtv4BBW1dpXtPnj+jGSqrDeoioTRKHG781VAGHabWehz+g/4nz9I7Djyp6YX7bqL1JWh8Fp4P1V
wfV9YVwkaur84IBPhBh58OsiiL80cl0uAE6UmFRY1th5p7ZPCRbYAskq7P5gder67EJTnEoOmh4D
cUaROaXx2l92dhgNCl6uENNdK92BBUcvRuRlaGIgX6YtNkd8UFeQtWcD1shk6WPs+GoWsEYc5L2W
5kyEFhH2YyIzniYFgWXVui42zvSvDn279tTWE7NYadzse6yvXNc49XSMj58VAsE6lSLbvSGHS0uV
ODqlj6Tfooxb/0VomG5hJg4zOyUwk6ELxD20TyvikX8ZFwhfAXMeYkhXhCtbQ9XlkwBaPpILSlIt
HAjx4TWiLLWfTDgWjYGlNNKBKS9I7w0EfXm1OMOaUtl7KjTchX6z0uVGYVNk6cte6SFJmqmU0ewb
dXaIQDWi0ROeO92je4iEe/VPmIip39sSgq4BttLggl1Mdb2YD8yYSSyx6efN97EgVLI4Y/GsGvBI
K9VrEB+Xcg5LpGIwVBiK6LzukJmSEhiByCu+xVe2yNkFkSEJeFeSLbe57rQXNTcljsuPCnzHUQhZ
ziJRWw4Y0i63uwufaY96TqukowXssgASlXSkO+cw7x7lkGKUMvWak9DuDIR7Icey+2RZoySk9869
rjT6wS2zrytFBizcI76cZO4STDB+9T6Dy4f7EuHqu/EYM0yYyrQV7dNLl0slKwx/ESDaHxU8tcvZ
kt3D1ecuCjXbfHCWQGo7njH3en6jgzD7X2tnngw/hE0zzrHsdAVYc+rCBh6OHgxJafDOFdc/U98M
NeyQIvlBoOZJ/Dc4dmmj4Unp9p/UaXEoPhYovAi44R3jPRfZ9oZdiYK40fMjZsVqlokjbY1GivwV
pi+/TZ4j0RZh7YoEBi0safMfLcMPtoq2E8ns7TiOnmNNSGO6b9Y+xCes0hY9AU42q89KVd0lEClu
9ou2/ZcVVYrwDn4vTBVXM3yef+lVo/RfVATouMS0KMxWV6v81w2KXtlKnTqut1jI2V1DHjIBsE4a
RIALSqn0OgeULuoAjDjfHOhuJ+t3UHU+c5DkpOR5Tq1CqxVZYaIzdAsmk1Xn3DhceoQnogwhm9hJ
U/iHIgjAF0TOGdaDoIFgl3ryWR5RfKOsLeFncKAVowhTMLl1RvV+u/xbCEb0/lldTkmd+DerC2fd
XQ934Ybm1w7gCQQ7t+UKC40l/QrZh5/NkoXNLfRcNUwBbMwtcG2ZIBFp4OhtLKJ/vICrQrgBpXw4
gukj8Dcl3iqm4c8jquePieIponBI/7+sMjY+HUMrDZTBttpO+63M+o1Jkoa6Y70TLPK/89OByTGO
8H9F2KSAw9tB3peM8ehMxVmYaKD0FY7za8/iX0p+6STb63M+9ze3fFeU3Nglpy8Bm1JvJxeZb7D5
jY6frE7XCcZtts7sC+5EGOhWFM+otB9v9ecTU9Y89qJdSuOVKidstPZVfZcz53AniZIxhiJNMaIo
h3HPMaX3JO+sYc5HDmPFrX3SXVJhBKZtbaHsTLEwDehb754WkD6o0KpehZ8HtDvLdKBixRnvBAba
UWsgt7s5/vQwW2lKAClk6vy+Z1l2Q2LOpaqdAT/pHZC9ZuuneJvch/Hh72JWlm3Zxw2bNooJUEjY
YNwMJYiDGUkH/4ijx5gzWy8dFVMTEAHaNBXzdBrsg3S4IuIDvYQjhQnlCrgf5cQQWmvXLgv21Axp
Zk9uwStIN8brqpkqfMY7zsdG8Fe75WFhR0yQLgdDG9oA8SipPHtJyGDxysmgkmQuFrt62TYh0bV3
1HBCaqtYs31PqPKR6sy4wL6zYMzaFct/NmNt1ftIbPK5m+nnpb15HAYO30VIcOSeJQAqvhBvYGfz
7zUUAAG+BNz+uoDzAjkkKSRLO56iLkgBdA1KEwpqq0gThG2dLp3T5w7EpyXe/ShODnXZu8jmk4Ze
MXUldt8+sR5fugVFY7sDsXqB6XO8z0vB0GJF9j+5WdTTNYMAKh1xhL6YOS45Ybo2PiQBXmSSdSSI
GljNjP8g+r4JUV6C2UiAZWIpwKei1KOV84v+IYWdJrF9nzHSHHfgGtA7hDUNgJNejUTGRJ9xlJV5
mbD+TsMjLrr9YofaDVzeDVIoQ+8R+Ri5erlkYBwjA3PIR8ek+Q081+gp4OP2Rd0zJ6GOhxWvcoGk
/KEDnz9eZUvda5oQ0dMEyGBObLOoaQjkfDhzvgB3o9VpAfO+ndbU6L827Y954nsRb5lWSCjFfzUK
qi5GKDp5AP7wj2ntWzil8V1sXnOE99fQAyYns4OGDrbvWxxc84jPtXYLeRhgpIOXmlGnt60v0c+/
WT65aFUp6u8d7xLAjDRgL6r/hdxiCLlNaNi7dCkOI0j8YrjB1edl1HD1vFTpDZ1yiKOSckWXjHLt
eIB/FJoIiTXcWOigRTfFYkm/IIoB02lyVJ845lp5NobdcfxRR+7aA0Z2VB6TQxwsw6CkHN7gqxaa
Jmrrzhpp4gZHnN7gO/RDceLb/d4ysfzyrWZuOo/M4b4Y3nxi1ugfHj3yasAebcXlaLM1e9dc/BKx
QP9zDnt/E5BUFThcx6CccZvANHpq3g7eUaonGox964+eM9gLFSt1cQG/+EhHy28UqfABzVfbPv1Q
NaZ+0v7BNwiUcwjRRdXSRM6pgMfOB1UHYr7nfMWh+XvHXbF9RSbzlhtseq4+Hx2r1n0UdVUYF/jr
LLgVQ/diSy8IKrp5IMqNMdZSARZh1Gi8FaPJpHy0ZEzkNmFPM1Y+po2erTkXrQJ8uNH6KnMv0mZ9
3pvQtAgYBL9RUmMNiy6lY7bXopFRKGlDeWeBmDYuWhlr8WmgzjpkLiLCM2jMeGVft6GKzRNBt+zH
h2nZOQIeA9Fr9gqgjtoUWGj7NztmY+/CnLPNHFfwhuciHeTV9XKoUlPuYeWsGgCnXljVWUp6M0h0
kIzgY8KtTaPwLvrUQ6vACWgCdEXjwfMYFStMKgSitnI88irIKuuvTEjXtmpnr2LqvGpZzl+7WETO
zT87MiIBnn5iCgVY7zP3NPbasBDT3ZohlZJZ9gP9y/7x8OJr7gIsoTuD3VxtazajaSbEv5tZolyC
PhrfgndNwnTq9JgUghFxTIK05civOGEx6ZTH5tk+u2FRVkXJebPMWgwquCmu/NC1w6WNfBbjOAZd
ju4wywutk9lU89k/ENy/3R9Z2OI0ARgRQ1HD7kjAUMmZBrg8P9bDzh9zZJB+tgvU94PJt/ZBV9yq
Us0/ZIBqqYRJlLLhxWLlMKmNJtzlfKpLQz/eXOI99+cZCEe8Ez4uvoT7MiyoS/IQzj1yOoEAuZDp
CyzJxaaGtnQbU5/Uk0Lu49o2vosBUvExlI8LbUEymHoCeb4lulWvPpEOe9U03XripGkw3VZjorEa
2OdtaHxibInOLAx3GAXtTpaYCT6II7vbm9bM72B/Fak5QEGxiPH2C8TL5cnxu9yLe84IClZQvwN8
CZBu2v6eZ1dfA1WpVwfjRtqN6rbXQ9ifASwDk2PfUutH4yUwDAZegwu0aSd24rs2bBc66CwnxkAn
do8wcJeBh6UujS6cNfT9NG1bVSPKf5lJVyerIdyxXiAcVnudFDks+3eSebmDskU4f0gL5WBnMfVA
9Igptb7ucRyRanao9mP+yWmDqfb2o0N2ARShsDh8fnEOVa4WshqlGDceGqPPCXeG1gBrERN/q1yo
Get8NHcAvNDn74UvRIA1IUcDE1d8yv9zrdhkSjfdkuKBV4z6hdO6uLs6HdaFsGcaoje7DkB7PHOL
U3O4Bc+xPCaSbISTWpDU6BAXB+tU3kWCr+SNAsq9FJvF2U5E0hHfqQGgP6/ewg6bWvXu+QEJdygU
j45QOofwI0BKdWoOlqktbhXQL8U2RpcI7xvTSZAgbY8Iz9dhdlJHM9s2og4JEqWFhFfR84tYf2gt
byTmt1B9tzkl0Dlfm/1ZRRWs0ZqaQjm/JlwWInsOb0PO3Cr0KkSQ5ap1Et0ZzJp6hEZPr0tFqwK/
oWAjc0QjG2LWhYIPp2yd+JlaNDZPKTcObFsM7eTJhL7BifnJxGu5Kgyz4Ya8J/c+mdBauMZCfip9
wJzWLTB4vJg27dA+6CvBHYoIspFQAHKeN33sO0ZTGJd1VxiE9cMlDiBttALJWQrAcWsLYD1G5m2m
NLW9tJ2WM0+YDRAWJVr7/vao9359AduVdxfWCZUhif1McZ7XzdSfRqEHaEw3plMC8uCKYjekIG95
7Rn7MdN18BZnaMackLQs+RIR32zAUYSLUdgK4ajQaQZ8l4Sr2cwAPYAqUtOrJplKBoxsIXmLVNKc
5Eb43OtfdHbjrO52obgANmmxHAvr25dnGGd2vp9/d4C7nauH5Jus1v+vjvy4+7twUKsGVQJyUoqN
vPGqCUfXgXnam+5FUnbIfRsVY6+Qm4BOrFh8sd9/z75PP16qm67yCyE8WujSZAgM4mqfagPJfyNZ
i/uQ3CwdS1Bj6bGbXOM5p3N7vdmeryxXPTOlrXMvx3uFQ6Fgt2pad9+vI1+VbFREVz8lG3W2S0k8
7jSQacRh1zOnqc+jxq6FsM3JqelunJMh4gpmB+fu+bHk45BLPJpxLaedsuZ5S9X/XilkR+HoJVJ2
ePUQ2DcVcvCTCgai5ZQzB0ZXilllFS6aQbU4uS0acgB49QCSWMib12g/vnz3nxEk0KtcTUX07geg
n+HMWcxFGfHNhWxVpYcikAsn5+8W0Q1vZLzUgB1/fBKhdPVo2yWdOJIN43FovxLJqYYevXO505uD
y0HcmycAKS63v+7Ib8uAAvwJgR++rUzBBYHnAhEU6jcz9lZ2RFvgqcg58jP7ORbn5XWWxwxR0OV/
Xx2rLPI2Seq5GK/tWgZIGpYnIl9n+js89qmTuBIOEJAtiSAm6tL8/zVAenTZnHq6XnYVnOlchJdH
Dr642mHCNg7Zk+b3eVEOFmYYidFTCPkulXPeDCCwKm1VYBrX9uwzA+0vGaHTCSb3pA2LxZheX7KI
5bDREhAEJNTIh6r29RrWX8HQ6L+ROwixWt404eHp9VvWDmyncqDdyLM9+99UmzFtwzdPioP2rwms
DMRX3P2BXGDzpxB/7U8a0HzaCfAWUBsLDJ2AUxsAHixNtsLthiBUAPFx/w6EYvTbDSF+ROIXQ8Mw
SLwm7ZVcBQma8ivOfz3H9Kn2Jr9/A/ARD9uesX394WtO+SAaoRGJi0iZHBBhioWnVQk4JMjIuUfU
upugbaxvjNUlXgQAabPmsNvCs6fZSU7XBFLPrsq+TgClR3wJ49kURAgrejP9kTJIq2bMQcIH+Dxl
nQtUNLoiyUNBZPjVr7INOcKXW/xrEOV5DdViOgNRj9/2ivFjdaY/QUIFTmGNEKosYHiYWQKL8lkC
sNrxjuKp3Ix6+zzo9O9X1vRkVOVOa7l7FNFxJn9qdIeY3JNwhAmRDse4AnPjkWiCSFMUmmbYt7/6
jgIHirz2MhGjh7mc9/CG02bnCKMxOEsBl/pLmdUx9tl+E+npyfO8ij0ZHlTImkJFkvsulUMILohS
ZNEj0AZj+PZ/4crz60Ky/8H5MZih4EiZ6H83xBKdW9LGyr9bPx3TACYEiGL39RRfFqRBK4EjIMVe
Oa7WqNi3SFAvleUEz7hTvES5Wc2MGtr0VafzobKKr0ihwNakL806IHp7axV696vkeOC6hjcdM0MH
2lA0FpBS1vrCIBXqxsG2Og7pPEIFGxbk021ZLPniDiAEozYxngEGwmURyZ9db0JYKGYpcGvQci9e
4LBSihjRfZIbKS4npbFS5lNrOzMNXyj7BuggrMFLpRx0X8gD9tfQVLKwmnjLIKeOczuuFZf7FKNM
MBW4plvA2fjitj99i+5Df+up0j0bEGwKms+wQ1JFrj94Jbf27PIJySs1l7GatiZ2tNDUEhXD3SAv
tm3VgpCKjFlt1fdZRQII7FBVs0yDULDyW/oH0++0lM9oY+2QjkRfj1nXn95FxJYzdFaxxaYwn7zq
Nnys12twnOwJLcWXvcJYJAnhG/8sFRYm84KE68RGjemqFu5lQ7ELH2o6WOHHC9enrJ5omgwEKJEH
guZjW4mcOlt3Hwex6ya+bXL59VW36Drn2kjrdGmsldap0p6Ip5cLZSPURLkjW/ml9UbORfBWssJE
6AB+rWr+4qn9bTX5kCs4dxoCX6B94Eino3R8GUSmL5due7tAwbwFnWJ9s8NNVja+2Jz7KOVTxtGb
mEFTDjp/cYPc/y3BopLia3mBC1HuIHas0/y3v/FqQjaHKrxbUF/7/t6svQQckb7P58XFDWWNrxKt
Fdak+lABAHJhneEGyM32u3xQqu9rC9hsa9bBzT6qaUQSXd0WOCqhT0OtTz59Moz8WOBPNjVChh05
jgT//QkQMGw+/rFV8FuUyOEkFOhJsIcDI7aH+5l40FTtRRVGnIuKxqT7Sr8XAxgY4KqrzjNk50VJ
TzefqvtuvgKRFiVOh1sKAiDXpVXt3HTUJk8tWduiPnqzFH+N678qtSzaE9s0WADiaSQtowckyCVj
F91rD4vsuHHNC998pdaUZiWlSHSODnhxhbpcT9y6+Wo50aMtxrl6iSL2yv2oqKKw6fnImdS9PzVe
gUwK1R3sHQFSBqzvUSzBMYw52iUSSsrLedlaQXS0Iom0Z+DU8iI+XdFKHJBE0JDmrpmaruj2S48J
us9jNEP3oBPPwt7SvzNQxKDdO3VPk1GbZO61ZFlotdzsd2hwuQE0C99yOPU1aK6q8R9gt5iQAmgS
DC/HhG3M4I6j8Y7bF89HFGi5LkKynSEJrCkZK8N4O+0TP6NHuCo6Vn+j3+ld38Za0ZviPCiFU51C
P274jQa/siLGiXr9D5mDK7+5Bx3jdGtSLqLyZvGa6ctj/P5FSarGkh9+dRum82N5WuXv084GBG1R
W6kYzt/kOVBqARq+959+DWhtKHvDir9neoOmACfnbOVg5JP5Oqob1ahvTr3RfeZXLcgPcREo27qT
kqn7SgCrxFe7KXN37KXh9ysY5g5rng8HDi0unjzzxyQ/xAEOLml+ybCEYfEyDCpsweNihYWjn3L2
LVsXn6V8wUYjzPECPlrg+Btm46fd2moAyrTiuUpTnTQgJPYT4L2aHfeaHzpWuHOsrpFL5USoDA0p
fpji8OxaOfBC50HZeNY0rphOFWhExOpOmJMkzaiHHbYxUe33JmeNoRR1qs/lwPnr+gnY4TC3YuiH
o5u6NfIyFB9vr97t/sQF0d7BNLsQj+lw6wKy3n9Al9VWlSSL3gw4s5pwsFJJGhIFlp9abKWL/RLO
UHPtdh6SDQNpzQEUncZawAfj4D3KMSCGHZPZFQh6q5bB8AdmSHymcNu7N7acQkiGOXP8Eu9iCygH
5mEichLgAQH3rDGvgp63lvHnt58nAHK/rwVeTKSkTmXeCU5M0FsndF6bsQFIguAOF1fgzbmf2QZv
kHTzyS7r1CnDuLRFjQYepWy5/PTb6LHulnHNJUhNXpWEImGcPW12Jm+4d7VfxdcPTGcKyV5Y9ye5
OcxG6HsQlRIFTPm+1K8WCGU0VfYmyQEETNRktKiv/Mnw94VGkvl/RLDIx3Ek4+JLqFob4Xe0D1Mv
SrgkdZK1eVEcNy1N1sPs/ZQyV9wX17xhSWOi2yVzxQuSD73v4fro4lNx2aVkaIB42248VunuVnx7
in4Kip9lUa/ijvcxQ1/X+e0SRUbKr4r07DE1v5BitJi4v4mdiKC5y1I0AQmdtW1U1vdqSxygG4OM
LY0eQ9HWDJpCkh4lwJzEAaN819RNfzKOkylWD7+zVGw8cR9x3ha2HlGTLIpdhLHDoyEf1tzshbTl
XXJQuzxrAbYL/UXINtpg9yHJvxRFRV8+h7lgiyyOZ/Hr+frgEqhv/ybWe65i6GCPqBUwr46aoOWk
OMrUlGv88YPBTrD5OMYy3WGoWy96WsSt8U4d5wgUdQIIeBJwpUYRrl6HKGlPVsySHJuczpAUDyjO
6XizOf+ZtUQEsxeEBCYlNYkBTeeX772/7iNteNfP2nhCOnKN2SV9yLgc2+CIkb3hCa0LWPReffBt
8uye/+ImPacKw1gK1kT2r5aAtrILW1UKGRgWhQ4+h3wDAZkG3iTkBpI3cx42OS2fx0U0fJqX5sqk
Y2aCCDt5HwQ2nRppZDgdCgPR7s+ZIgCnp1Jh3aVnxyLmD1au0XlqQ9VZ3lCDMCwi4f7Rn7Sm8ZXi
rVDULpt1FDjqaYD55dwj3BVmks+Vg/lQKQRVxE3sRBJ/snSuQFfxQUTjkG8EE93NofU/K2tjbINf
TOmT995oAv1KZ1aWjPvjdf2uYFU/Xz2XTDdeGvw5sb/XQaO3magU86ykqSSJy6TiiDVLU+mz88q4
0dIiSvToTnpFGCmtVVan9r96Pfu5Yq+dypxKDpjrXczS/L32gSdlkZ56cfj+UO66ndqKEVg5VGIB
TkOfKS10rLgeQDKY4XV/Qy1AybBHKE0R3dNCt22EmWcVJBLNiq8p9xzqbIz4lF7IYahOJCdlluFp
N2uDb9xiyodsDMQ14T8vh/56c4OMR1YDPPHMoVjQwtWWNtyjYyspB2LN7C3zdrGafV6k8x2feOnN
NC0dqBii2cWNyRD40eFvNEwSgLtkGCXnhAUmgpdw8D/fO6uIgRwKbJG27qim7zs6qsAThshOlB3L
cZPpYKBwXZOn7wL91qgtVnE/VZxgRX9HDekv5sWjzhX8qfUHXiHDCUTTsZPfOpFOWATlhKO2jtNt
q7wphQX4BSUHAnbEzg8Cav+bQ/ABX6neM/KZEYgMfDX/jOADEsv8s32+R1+ZWvZ1Cfhco8LdRCug
LRIdyUfM58ZXe/E3WDEF7+DLkr32fIPM359kO61TIGxYsUyoL8MI/DjqKVIow+WP2pRscAfm1eFy
bVPBBQuPaVLSMb0sgmUm4+D69dKyqlVod7k+79v3tnk3K3EAVKn8uFJOYPZUlUe8LyiXmc2QgyA6
/m11wWIwTG5YdJ0D0yC1Y/oC/hOLaF/4Pvofij1XT16bGKf4DtWtVm+zmE5JWBd7yoXWkOkoOH31
p6bh9tCyfKzPLIXUy6doqmCr5BWnD631WAjpp8NafryPb//OSX2O++CrlUjfT9VkdaRNZc707oGT
AmXyOoJYh9OqY5mS9/O1affR3PoYKTbgiVW6312gqp6fsmg+/A7SEQIop3Fp9wA8YjEz4qHUpKM5
CyeqnSbyyKJykixewSmCjrrNHNrOGhw2GYrq6SZvp1HIOnnXODQqAL3vwg8EXVKKOcS4dYAeZ0nN
kQEnSzP7mAn9cDI5I2jXyLUfoBKg6cBsq678hsRlxk8TaCxI2lp9rjMtfgaovsnznpLb119H3rvl
DivE/MO5H6WV655N/IHkjlhJYc+BG3jrbvj39pyTwMntLfOjukRHd5EXh+WCtUn8FtXqEnDhd2Gc
IsxJb7byMEl6eFCj420CDTpWrLxBzB8MN4kkH27wDZ7G5q3uQ7oaOzXGmfqyMGd0X73niTGLPtg3
EISwwHQo7mmkyLM4x+jA8XFzE3c/PRPCermOyg/HkjaR/7VyA0ZCx8xb6jga9QVQOkGT3OEhpQ3v
uA6tvdWwNhQBc2c+OFEax4NuVrWUyQWrakrwPVglU6EAz3oICMdxF7NBh+pgAFqr8b8VNCbR8mcB
skHRDHx/UWRNYG1FP5vWsyCJmv5X6A2SYxu4HW9FXZMKGalCEDffeBPLJ9hwr0pYIXX/YkKef1l9
mHXxarziTRe+f4fj0QRum5Anq4EM/8THO1Abf/6lZB4cC2794bR7mL/X6SYcH3yWJashsu1dpVnq
Izqke304V5akSBFJH3zI4sI9pgzijZ4epuEcIFoBqD2u489JvJ5hToOIz7gilh0OIxVIfbM//bwL
gY4oegcmrvf0J8CDOZplJ015wnAyX7QLtYvd3WEr8U6F+logX3VzPNiIJUEMreylM+T8b0jLk8kW
pgSlsxd9lvf7Pt9pYacBeytOklpmQ57Ga3JAjshB9ibhDtlRtpx7bVnqOQInHlwUWvcLQWpeFIy6
Zy/cjMSYIrAtuDLp0P7Ng4J5V8ZcpJJoZZJDJJSX4kmM3nmrNG9k63xJJvKdHIjo0WpeMu18Wthl
iYD9xpCM2h1Es5fr7UK5IoLVlx5sLm/8F6iPErUTg6Xkv7vnCLQsjoubK04WiLACL16iAt/yx39i
ebXwr9pdT8zS2DUZ81dZBO+n7LjzHzsbti00osGRCzaynoKX9zydYVbPmo9ip0pccMZhINbrX8FG
lTMmPFa5ZiWdyUde+mSCAiXQJQz1FBQ5aN27UZ4OOjqCyc1zpWV3G3u1f7vruljkRw7cNMeGOh7w
jW3DVoDRTR1OueHGNnB9ctHovqwmIEg4ZP1hi+0fbpAzkHpCIK1bqGI2j4KXTjau3w8bQbJWOUVy
yiWo5+lFBDsxTUDi1W1BtXVGd9eXJ1EHzVOW1bCD8YJtQz+uevx1ZcNJXb+dHaqU24UiCaUn5FZi
3PrV/6ODjcWrjXxDb3PJMBJEOXj42uCNuqgq+zz0uUh5P/KOGGpyCjBzZ0p3/a4PDQfWBLx5kh3M
b7OrJSS3LHA9pyeU5EOOiY/zdQPa2h7YXDgPfuLvzG7xMIXhP17c6uguhuHwigVWwKH+nggM3ThC
vl8g5nHMdHHBw0fSNDVvG5wZ5SWsWRAKRi4kOxWPBojQGdq5KYLN8y7YL0RV2bhfidqlv6i5h6eq
t0gSBKznxNAT/5LBVnZ/ozBMrqs/MTJct/rJo1ztTMES8ZgLNqqVxL/gqWbblDrt2ieThJ16yhyD
M7u+ZdAxq85w+0G2pSCGs0TdZSks041cCOPtWArxX7NAa8Jsb7eX5V2pCL4swm0nlTKo4rJQ7tSm
cPqboFYkb+8o3uQG1hPp4thCpr8iFimR4lGyil0/0zF+K0dq2sAXafR3lrnF86ecYMWTq5vQY8s7
6JQOcpp/mvnNliiRJ3jrzzvKlCyzdwfeptdnSUjdfA47ZTmrfiBzJsIqiX0ewAfBKO2atg9e3poU
5vFUAQMgaCD+JKkuT9cVx07HV8CIvI5/xK4KKwNaZx6Mb2nBxLF2HdDdc98JNHO9+u4fwPgrzbXd
qZuznzdCqApjzyY0qv6FIyPC/uoWLD46AxSJOrHXqxGqAvL4+8eaPTBLjSfKPUDFYiYhcqRhjtBY
RNarjFcsP1FJI0Gllwzyn+DKXRm/PY1oB6MYJhSkGJGgJZy/WmoPGeUELVpmqzjYEmGPGxFzY8GB
6Y56bIoY9dUBSOXWcIGiEFFpwixGscp2v8AH4ixYIIkRqH+r+6+9eXwriwomAXPi1iy+GaSXsi6p
a+m2cLmLcPRgQA3c3YsR6/JSxyZzaXfLksIWYpcJptZkrI4fu+LEl5YAN+tpMHERnuMw9/A4hF6X
pRi9bCgXQcxWUQGnUfxMUVCnQmZRx+AqoOdP7MEwtcWw8NtuXFyAek8o8QhmyG+Ca1bnm3Fkb/1i
PWVpG9pFryXglXrYCj+q0AgxqCG5V+tpzEE2D8m/pNehY90rizJ/e2oKLfSMoGQVqZAw9MThmmI/
c4QgA9/sGTfpyTMCeoeynmlIT2wySnFWtXsje3CD+WC2yLAdFE7A21E6lBT2SduE8dY1n2KxC/Eo
BiiYWh/TYSB2g/pmsQWqVAMCKloNmMAq8nA0cNqh3KMhA+o3fkVEzF7cPw+JwO7hdecHpRWnvOxq
/o+1Yg2Lp/XODCLefNr2hW+WRtF8ZHp9jj7IU/IAsxSdKbEFy1gelpA+fF74TZ+ByzSjROvU7xGT
HLVvWtggUVqwEpF6jfnSMkrMsOwWkxdlwMOqB2I7ZjMxwvHBdviAvMKO6pZiigy8i2MZk83PIGFU
1238mHjvtZNBwsyT3GVnxCsJXf7I8PkJzxybAIb9oKuBW1FmXZWku64MWo8AjSy0VfWVh/jqKeM/
rf+NfRIw3WfWSNZHMAjGGvI7+cYDsFEY9av1M/S1QFE1OqmTfaC1t9hwBl6xbHjdv4NtSZP/mT0P
lzPRG+BJcm9aLMZIDSiirZHoOBv6KukYYCN0eh9UA3L+YuEbJOl7xj0cpkv4HQv2rO7qaW1gKuCS
wVZaHVhP+B/BtlxBOdMNNd4cSTI7CVpvWCAUOWEJQnkdsP7ja09rS0vpM79sR4LnbrmrqnC+hdgS
Ud9jotpoi5BfH7i76TIf8AFRuj09ltX+Wvsd7x7XCTs7Gq6Iup1/9axBeydmlhNNmCdwG4BpAbES
++QphpuU2Jmf6yAhHMn6HvO83nW0mp4McNMqAh74opQ2Hh9VE73ob41FXaNB56Rok3EeqxX/gC1i
FOdOW7IZ3dOa77oXvI4yE22+NyTsdWqH1y8udzhfWdvu8rgwq2xZW1bm6eNReDIcLnBmCFcWmQTb
+uz0/F9cFSKMm9eOo/awAHY4XvjFfrHnQqtNflaLNR1T1vHHKbLGsMTo+lbUBMJiawGcxi8AeMwz
ewoaoMIOAPCYMk2uJsFvt9dC8uliBPZ7sww+m9vVWJBkiHDDg2rtcE5Em6wzmkfGVcyNMSOgHkYB
MpmxHuRJztt248vvqAmhb78725iJXVPHqlIGd2DdYGMuSp7m/j3ZBdn1GNF79tB3HTLido//tZba
seYK2NLlxCCcsrxmRgYg5DQeDcIAdMUAB/Ppb8JPU+0B2cT6rDtQPC5T9zgbGdPV346LrfYmzpZl
verHRlY+/qrgLMnBBHTvmt52xWTEqYld30v9vV6vgKLc0CZBnGPNt42m37Xt0pLj4M6hSjnBgPE8
4BTf291PnCUgXBIaBordEYC20QqSGrriCvabSONZwJAT5gomlCVxvA5FeXB2wyj/wW1QIPMUTaEO
eaGDQ85PQTgZQ63YkAPJHVG9KiXyle/jUNELD7SARdmMNY/oGClt4rVrTgSSIfeMG8S7Y+3gp93V
JFqD+OeBNr1Kr7qGdc3QMRYUKgq66rlHOTWl/Rp8HNzS3fQbf5xM+IyCv0qbcrcyqHtkFOgFREl5
+Pgx17j3KMJTExDLCoB3/gDYGAyUvyHhBSYKE3EElaAmzccVJsDytGS2X4wNFHSnA42ivG0m2Czn
u0QeDl0utZOoie2lFj4Uy1Fn8crkv6Xefh2JWPDvcwE0Q+JqycivFDCsSl9o3TBGPBLUJmfDBOat
uUfRJMudC7sNJTiQ9KDQa2vpTYhHxG4IDK9eD4EXJL2nFYgNbOt0TpEeek8zZDxgUDg308BTaSnc
CRJ8oSTPTnYC+/g91S9gK9HoMHOP79nIBMb0iU4isWw3nnKHiPIbfzf4PEokAJqrwGzgdCtTGcIB
dQnutVSV8jil+6QfZks2A9JckTI2ExIxk1k1d6dOXDaV38+uXcv0kqPaWDuU0lO8l0zwWK05fqx8
8yy37zn7Ev0Z3AgIEXtdI3XxbUoTrv8/GdC+broY0Q8ikDZV0YQ67keKpnYIKphXbmxVpHENkuu2
PvkoBEJz34gqPL4vzku6MMjEBTDLmzShbnaBvEznoX+J0HFqj2/vLf1edq3VJjBNrrSheAArblLD
QcOski1eRDNuGCpkEhKsne8IglyqSDI5R7C0PsLB/6PI8MQ/h+/n0kOe6gZipqB869g8b3uc513K
qjI4ytp32lhFXBZdBlqfFVL0C1wi4ELj8zV6Ffj18Ljuj4QpaVOVWbkMvJ9gY+tPJU33IBs7U6JR
im7ZzT2vwEZsoc6251SsMfjljfbB/h8rmaSyrk4ZtWOQ/5ZCiqrYkYlYOeVsJ9J6FzB2XHMXQnRS
hVN29EfoGzVQGElslVnwV2z2pAEWvl30OV/Y/BlN4iQ2NwNHD/au2s+kiSHKSJVx3Bw5ZO8Ir7ag
nHcV6tpnkhC33Vs0uF+emJ/jM0z2YsYEZh/SHQD8W9xmqJZ9lqjSEeEnNZ2NsYIt/uQYhIcUkJPH
ob+9O4BrItmCK+S92c2w4ijF6vTcn72S1FBuFY0SUzKryCfLkAgKbjVq5ksx/Z0GTD9xHQBMt+hX
25tIf8+x5fURSulcUWBMU1ldYs6xr0+mWgl1tYnyDnCb/mZPrkW1AYh20NJgfeEyCwNhhY7QPojj
5zGchMjWj6jziYMhkGiY+rfDQSe+KCXMtWRysSR7+FD+86lpW/Ln5pH2qLfH/wY6ugJ7Er3Bgm2z
/XGQEEuZAI/Qaank6FaEKigjN3sq3sFqVfETzju5iy9k9XQIfWjf4eS1ey5Jsm4iPJtg2ArKCTFi
FCoehOywSqpXIvaT7A/mKccbxu2fi3mQQRKaEwTRuVyx37XIaAqNSSXYeU4Eg7YfNCarc4v92qU5
Xs2SAjyz5iia3ItOXVW1nHgAzPDYGyr53OmozZBRxQ6dO9EswMVPUV1a2isbZxn1aEdRnq19NDT5
Sba05rDIpZwy5DfDJovBekxj89hTC2hZvNpvf6zDn6l6Nm1zGJXOllH0NntudQ/MdnYm+yaRGRXy
wY2TUPAF+6Qs0j2ZOPjiDknuh5rWzMRjYNFtkl6MkODv6zUodWDDdPkFJteuaGltPUSy6yvlUByy
kEFVJuDPhGsx6ybpYkTGIVMstEpsj7nEJsQbZXMHocIWuGmuQJ/4nzxnhCX77wCy5bZRr0zR7uND
JQXURJRuiytBzDm8oVWn4xJbRvDb3EnaEP+uHtV+V2XSABDGNZpVYGAAQSEOS/wXkIGLSxrk6+2w
yHt7eusqquCJHJz6TyFi/kRdQEofIHGTKHp45XnVnYkpGwL0j5Qq+jWF+PXNnR/ud3soLefV7g/3
RM7gMNM0N64pFeSakKB0Y8/s7nrv5SuOeO2RGCYoOkWME6jDoZtDJvX3zG6Yxz7dBjhFufSwjn/K
LT6FGzBpdPxoCC3Nb0InJfresZM7iQUwnvv1+nNDNWt0kvzFZXm1yfSusDnGf8jq6DKlUY2ALcG4
/CMSG2/irMobaK18q7277B9+biLmpdA/GM8PZ01aY/YCINOOROgpg7DRDdSChPwm1hFgVD6WTjuw
vjHMdpy/EpCzrmMxS41aFkhPGSJs6eeEck/fLYyrewZKO2Sdh+RbpCyMI7HW/xeB/I1ov1SG3IpR
HzQLNrXNdVo0kQuOYB9EJTWBHfGGya93u5xEknj2z9Oe0EGdv3On4kdrNuG7wJgecAtoQImpR6hL
B1vXsiYOXwmmoPuXuDiR5Fvo2DBkcY0iOXyqniM1pkcodDG5NAV+TMd9Kua1tTGIxW7hKS24nRJr
BpbZarXq08pXnb2USMSCwaac7c/9CekxSE/HwHnsxVBATE0Yw3LHMgbI6KbG/8rEoidhjw8QAEJ3
6j6C4fxnp39B7es8h/eFFucP7Y5Rh5Q/SGLdfXalgl7FQzmJ4GfGxF8r0OtdcQ1kabK09C04DZ/B
1mA7A7I4Pd+G5ASfwXOdQVc5T6TVX4H4dDAbj3NZmcURVCtNKXfOGaAwB+PTX19PDoOnkfYmipbQ
Z/fIvgv/X1ti/wcfXFblXzE2Dupg5VJSj2t3ak6COKRHEfYzk/kT9qG8PJ7umBt+S8um7t9YY7O7
L6RRqRA9+/ZT8rSOqvpJA+wiF1cgFj5K6JaWcxoQd2LY9qtDn/j3uW3RE+jnskIGKOnqDu6niIH2
EGW65vh60sL4PO0mADM6eepU8ynhib5VhirZOOVAbbqFJ/1VN7/ma7w+p4nVMS+ABJthqyEdch/C
gbbFSTHLtk624OhP9HKwlUdanUVh9mXoqrzVO7ivhBNuKQ+oum4/BkYdGSn6xrtaCNxHCqrhoBvp
xzMZ/4a3hibPXO5VVNTCyZO142Ij5tjlsFOubz4zTNRJCZPLyF4fIKpuLY2R8L4xw8b6KzOfIcVF
zXypsKl6A/JivSiP+FR/A9M4xWNoq8j5B2hWY1BwR4fyj7Vwkgtu/DlZvP8mxgRDO06sWR2J0qux
Ms1Cm/Wctkm/I1/bq0RPBXsNa4ggSvjBGjf5MbEainPSqd9aQy/9NyCHHkQU2A6sAVnxN7iKaY55
dEt9ZxtNK4nJVcIDmMGpmE2eswM40eMQvWtJV69hh+onlLdLOS7HS9aQMl3EBfF2iJurAiyYONoR
W3oCdsALkX7NonKj++5y6zliMRu7/9fw0/CtkSF+2e9VDzPNM4ou4D27v7AxMolyMkPc11lJ/VMK
sYB66W8X3tOeWjqzMvCUlYHd95SFdBoskrMXNQYoz6qAIzCwoHHsB7Ijxj3TocDPdNJT2ZescJ6V
7Ie56k1TURr64QroRTQFL87/tP6K2lhht3h+VqEytT2d03tpWCmMwlz5c27LpEGg0o0o8cvGZxK8
s/zSQTTbaJWUcr3vTspCv9jGWMXoJE8jUjLNZGuOOZySX03muSwUHZVdrEHEohD4QsfhyjDxLqgk
zIHK3airIs8droK3bT4Dq0ugPd08ar92MSbGdmDm7cwyCW19s2MEmB5FPTwV6QdUxcTJYzrD4QzT
3tXMIVJ2PoXndWM1f7vL3SySmxhaqp6mON/sVsijuHxDHBEtrbenKjFmED7AvgU1W8A/gPGUac4U
eMkzsZ1dzyDdE9+e/U0w7IEW7yHo7jhkXFF6uk2cr23/LG3NGJY9u+aCBI0gudDaTF1ch5i8vFC4
epKAmIeF0x0/TWl81Hr1n7W5UfETArujlmmV+0LOrC8K178fbcxnLszoaTfMiwCY2HaBDLt9H9Mj
cwf+tFgR0N3DH6MBs2+UulbareFSWw5x3a/SJRmawi4rQZ62MlVVoQPMDfnB8BWctJ6NAMv6NYlL
HBmlf3T/iSSHezqWIC9vHgf7rdYxG4ZwhPTdEnC3lPw5gtef81PQ4V+O4a+tMG8WpIM6uNyk9TX7
wmLzaGImpRR2Dahve2AY0pU6ixQqUyTVSy3ISQXOog5s56srfjjprbX/TDS7aJf/GzQp+mNHHPAN
ZtBYQjXZ8Eh4z9gOv87PbYbI0u3vzGU05kcIriFtN+3UaWINiY2jDxiwCcSHV1kUbKCmWaot6Y5Y
AtrYZDBXT8f2jiYENPMvCjCHuVEbPua+fnQnRFD/LJt80FmiNjjYhZ6gWu13T5GSdG+drMQF33jo
yBSQxLekE+NwYwuJmGMIGKM4OmUad0z2iXskFXvNLUmHwtgvczBzXo93Dc5bJh1kDlCbyeAJ2ThU
6LYQchU8wIkGKWFcgKqfJsDmKfTXZKwxWfhRH2D2SI3mcT2d6yyuxU7zYQQgkg+NWCa4ndAQhH3F
pVzBuFQeoNJqiCmPKSijFVRi8KouWijc92+n3YXepV5yK4m0GXytMtEBR3SvxNrKeokQ5y+S9Ogs
d+kUwp0z10pFY4P+7nujvEb+IriRRPfh+rnAHQkOAqK6NDA/iIWm7L0lTbQLaxZW8Xl5Z1kM7Jqy
tlQllGQ3ksxhc33L4ZOUjD9AGhkb0E0fioOD2bLKee7eb7ftCMtS6WEA7Y3EWmT2ksYL3LiyDsti
t6UQA7XjBf5kczboN4D9SEIEQ/C3bBIIq9EGJ420SGKm1b8iMmCiSDBAWkXyW7yyhlGVk7bgdXl3
ABkwje1uohM9iG7/Cu8DmXO8oSWSr6EM4b4BsIxIDbzh3hyS6cJjchaQ+1hNiMlan6oiige4ZNZM
4OtdYxZtrkfnHSLiFL1F5Ob/X++e988fvLREM/Hy0QM7hIRLMg+ZMQk2Xd53/3UU4SoXx0eWcNag
bVEX/bFI2N1p6YSpkIi2cBf9OXkPd15PLPiK/3ov0XGbe86/IUXh1ZsvDlPLAt2xsq3R4ib8VUzR
1pDsfIJzjXiQuMdES6sh8FvG8Tp+j0hQcIgDCs81GQNLz09/7bbIf/Etdx192MsFjXArhHBdt/L/
7Akvi+R3EN6ZSbu0RbJDACeX+4Bo4/g+UhFvQSXqyEjvf3yPIKGfEWFpTx0BAfpAQ1saUNJzjjZ5
Pwe77vKPtTnS9JjKsMwLXAZn6wHmwZdjwJzB9Vt6KR+Hl2jwsC23I3STBiwX0dyvsGN7AcyJ+pOL
XxnsY+2w5sLfwAbvCBQ0nAQJjoL1Uuz7EOJG1H/d+aRuMRAiOVcxjObhU5kjMUKzidi67cLCw0aD
RioInfHg+JOkGo3uJF7SspNRnsK0H2KPIZIx9mJwOaTN7+2BKAJgfdKl7V5MFC5d1IlLk3gVJi84
Rtsrpp+0RVrMmUWKfA+RNib5N13f1/GpJVvS1jjtYaFANUyF09GFPQE+DF8xbOQeb5uDBJK35UwQ
0q6qYOAYpVRz4JvXu99Hy56ppQGGpfuY6idCHGbizYSmWyK+Rhwmu4qK9dtOla+sl3qgpRgHXsQP
xKshb3pzidBI4tesGJJlgIYt1emMmqrdWa0qH6u4MZECRKkILUWzHPnDOAs1VkkKM0ZS8alkgpJZ
7lcLWzBziyZYaGe7NS2dwMikdCZy5ksTRPiib1y2Z5zLoVRRm5PjD4NFxijFJFLsCjodhbr7Csq9
hoI3L7kJfQoq/mzLQEcHT+QUwhTxFf/E+gHIlgKbs8qCfWj2yVUeziUUdGM6RAF43qrXID1N+wrS
yS9MLEulka/Ajk/gmq3AwgIDIAmcrUmUUQTNHd7uO6VerbxUOpkbERrn0u5EJTC67lkZcr+Y8q5q
purMlwgn9bXS/TA0O1J8UYLArzRHgycrN4jquW5jrrUw4dA8yHlaHTziPetE6G9KW36OFg13d82s
ZJAfZv0LkTNGqYYFtCrs1rZYUjE9LFY6Lb23gwT13aLoyYu5j3+VxZ0SyhbqSeDMiwRzk69gvbxQ
7MG19dnciBgAKkQSlhfjk8PxfmXg8eYZEqMjv7YOhiNPvfpB5U5Op5wJucCQFm8ejvDH4+gKnKkL
ZSTeEY7E81+vmLW6GQZQoDWo+pJNb/B/cla0kBi88gZutok7z6MeDMQWNV24tq8VAqBUHW22P+Q7
wPUIM0mQdC6b4P0vn1lldKIUkZmsJa2EJkO/IYw2KJdQzVBrZ29jQZ9TWw0GtpKCqKZa1Zeq6XWm
tortYUe6P5hwJ0ae5Km84wZ1sy5EncIE/hL0qjTs8xkR1GsvSMYYnLXOTYF0js6k4hPtJFOlo4UO
0SsPhxI98huGDp81L9t1MSWR1DBXSx35H9XKF0dQcDv8deZxglpVu0tBXbxmfPz0ynZ1YpldFpzL
XhvKP0ksvyIFb6qGXNCZB1Xqnx2lsrKFPq0GsWw2CNPhrPjZCoa9rDRx+iQF2xKPubwa6e2s5W+V
kj++WWsqwqVkQTahPkPkZGr4/bkJ7Hcv4pSUpnVeujjppfH28sxZTfQPAMcDfKSRtgyvBZHpO5W0
qGC+j77yam5auJObphJI4wfF+qdbkGutnoagPlDX48rppQKMJRBIncHErSuOwOmCSO7a0i1yWcvi
XqSleJbixApaUFGLFt0ZlZMg6E3rkO66bG+GbT373UPj4XG+t7y3PBne/Ct6aWieL/sRqlQlYAP5
Z0pHnpthmddweue2bTPUfOytLoknGZQ5cvErrdDQ8nZiKR+zeH2xr0LGx7D56FYbBXqpdFOjPJNh
r9VcABY9eqppZjxTuPQxF76ByjxBHRZ5Gmsa0lojvsvrvOaUa8TdvTOX+n10TDehIc95ivp3q4TA
fvtMwHIqAubUoGtd2wbp3yvtZMQY6+JmbzVKvYhTonRgEHxAxpqHeX3tkbrG2A5Mv+xeDjlquMM6
2mxGd8QQluhxrx+EdBtEG/YyHz6eCij/JzPFvFy8YLlE6Kvm6KWKXr9m2ku2VgbwapbwpDS2fzhi
Ey5D3OxYqE6F3c16fdz5eE8YGQra76B9+eSLLK86wxXtZS/A51jQRh9NAaZI9OX/EqZ0cSYYM3u1
G73u6LiUrUuAqexrfzyAa7vpMn8bazl9AjmpwyGqU1pWv0wLkdsyo/l/7cT8KWDL0l2XPGC4b3w3
eVvD2jybxQPpxwFhfE54urcv1gSH6ocfnVhEHrQsyX74vtZsmKFKaQiPStrbKcFsoOzEGxWOMNFv
nWxeF5KyGMnpyd1TTs/6J6pqzbrBEqV+MZS6zsGZM3xPI5hW9Tw61BsDzHiwXzx3CU6O/bKqRbLF
87ABl/Gp18fY3sFhyJjvmQx3+NNFezDJbLzxqsLjSD5pcYTEwIxsVVJWfxrjAEeyAXAUMzg2VNhC
tAxTnO2SEafP8Aq3xX71wwirzmm94P+osFri84Ipji/XnHBZB5Iw4iFvk0KAmoouvYqcugpADYWF
X3QYlYnMQVXiP55F06viuxylhjE8979cbKyp2L4WgGowGn3+x2cfIIstDfuniburXiIXnPwhm6rp
JljrBGzk13rCnysQOj5PGcIhwC/2okxNNC2YrEYayelc/0jVMZ7N1/ZTZ8zyjZezNahdqZO8t/vW
ib2TveGmvsow6GeS56pnTfPvjCv9ZhI67GvkiFp9CwrX+l+4UhPoxuYbdnpG36aN8g/rhTbvq98i
9SQx+Sk18x8ijMTeL4tzEoIBSzdhyKcJ3bHCx8ZC1f//IHNQ8NXESwXeWAi/vTxojbH9rc2RLRDT
fHLKHbq0jkCBy+1HH4IBdagaY2mU5L+Llu/UQJUBqdvp81gDB8WnK6HFlPnanvACOeD0gYEMDvYl
ya4Pvlrt6FNVk8FnXdn7c0MkZvfxJoSkHi3yzDGc8n4x0AYUcnKectBSLe5JqIG6hAFuJk3Lk59w
5447S+GwiF5xKMnQa4CwAPj/QgTTHH3N8ZTZZ5TblcLWUATF9qAg6d2ezAfDlSEDKXjfu/9flUI2
01yXVKCIYTtHi1WCSsZa6mwBxD4eOUIYOsmnv7FDyezsYlZo6hIiwL3l5t1hVzVvnfmVnE2hJ+St
QhTl3kocmaxOLWVhDvURLRsr+rkKX/nW0ngd4P4DcKj3raqttOjKDNgqDMxPXRR05uarWgEzFADI
wXfDNev1Ep/QoYc2/5LtzaAkU6VVg98T54E92Plb3al7+2aS6WvvnITOFQATqfKUQqEn3t0zz5fS
TpSfxzgItw/dWLEcnjuTanwCD0fA7vHxOQwP0uP+BJoK0vBZD5PdA1jZfzL0aDVGJs6TyYyQ/Iku
L/faX6i3xMh0ZfaoS1FLg1W5yBBPiScJp77Qy+VpFkkIzYHvArBcOIHelTC0RewJqsM5sIadKpit
+gX9bZYkuMMQtpJth3WuO/8+HkKEmdUWTAAt6DTiIoMvOtNcdCeWS69y9mEInuxlmo+8IFF45Fcp
3hTqCBP4QjfYM5CBKF0GGc2QJwfq9st950Y+5VIFmouRyA+wkRXFYEbCkANR/+VMj8BDs4KLfSxF
o4t6xVVY8kayWhE9EdPZk1k6AErvcc10Mt9GkTiI2d8RBd1wnx4+3FyFrjFkRFNhdFKiGT9FV96R
3eNFyoFFDEiSqBFjOfwm1eRuxo4FINxZ4FceuG2vqL41RncQ/K58ibPUqBhlrUMOrGPGnOYfp187
4H1jpytYCvzk/EuFRdiVCZKreJpwvhhDPWlSaYdig4FBBcNTDVh94848GO4sM1V0/1bRJjwS3BQo
NHDi9KcULGauj2QMTzSYbGyebzUlxv/An52GOzY6y0Oa95GVy/QuwZl6jAl468pyR1oFqF48MK/T
OWhOjoxc9VbmSTZzZHSnQh1mr7vMGQsvh2UJM6bNJvlG1d10ytQ/I3EKFAcy8CiBO5ujsN1ib1Bl
Y0LNGJw1PYjfn9dnPQMVALfS5/Yf9Y5Z3VJymscdnSieJINE4CX4ndAAd5DiobiJLuUQSjiSOuUV
hAPS4JELFvhVHYANivzR8LgYNfzdAviZL8eWQQt19kleqig6uUXPpI5QyxfKcQ6Iav1nShbxh9O2
ZOqJ3SoRWLXEALvI7AD20drTVgLBWTMk6r928ztzbr/F2Xvra3FP7aUgWD9LwfQPuS1SCiMauVzH
/s0VQE0vF2cKVN3tTTsLeXv2BKyAQxnaadin2u507ryytlOz45SgI34XH9fI3QqN2v9VL1Ud6wCv
FbhvlzjRcJOkAOxld9DmiJyK6rZ/vDrHOfwg/MMMRclp2NSOUNGVrPVn388nz1T5r6E+Fs7tzFUb
DI37OJyp8SQw4i5ZhmxB0OsUGEQ2YSBgxXDTpJ6E+99AqJbgiFPc8/iL9pc+mKWa1sRTP5F9hVS3
G4pt/I3DHw0Yyex15vyPhNHHTWQvXGPOy9IbGx2UfQU8splPNDv7IuvoQwbUUUSpi29JsjXeA7JV
x6IFfGeyveg/QI/0IxHrioBGgP8ry8dTzzEJjSNGzukRWZAdY9GaxKhLlOSJ2SmgRV9SBlWcbege
S0WPMdj1xtggElRkj24Ok/nNejDu0ui8Jjwc33fAMR9ih9wiO60q4EyAc+/V+hYnDWNdX5Gqyvsf
eJ2EOPt+ES0Rw1G4hG/iZnWE6i0IG3Wso49z7Oe+5jfzAlc928Qt7/mK6aq9IRIvjxWc9YA7XYoR
9tex58vKL3hd4WFRzpw1Mcj6NtKafJtQLaDtaNvEuMC3n6F9Gsbf1t/LmzGFOx+CjNGTdxMe/Rlv
KI6bpSjyGBCUQPwPi02vPfQ5AFzNvimYj63vePvvkYWklvTXKMribj5Zu14qxs6uFRcbDEW8MzVU
9G8Ljt1DbA1vuKXmArMpLR8eZKQKb/dbXjxQX6JnZZUBLEz8q2Q3MBoHMivHyPePHmABgWVaEZer
Wy4qsdtwzg0ntBMEzLItzV+7pTzV3TZ+mKJe5PlNWX13A4xh/n23CJztxeFtRmlyl70KdBI7ngSN
65KQSnyrOo1LY5A6Tijb77k1xsQGHADj7BPEGS+RD7bfhxvYnc+EhNuSa4OVD2pJ7AeG858lyyVv
K7uz0ezUe7nXxpyH0akyfFpEu1Nnbr8hduqB4cuK5V8C5KcvDG2HPHOTFPtUKKV9T7h4t+Bx9vuE
9es3jpgS14WKRhLrbcrSVn01eA0S0U593D345ReSenUXi5Xzi6+irKp+a+FSvTRQ4GDOVK+L6MCL
t1QjbYmZvKJzejxxFgp0faqCc+eN0t1ZSETLcg7bxKcbq9p3oJmoQRMxLEvdK/aikfjAR+K/Q4Rv
NioW0Al3+Ej3yTf/Bc/2jr7uq91EWL44yDaxAB3ACetSbDCOagQDfGVBgkacK79MM941l4DBmKgV
3ucsXYQl73U7sP2lrY2W6rcyx2wjxuSRy5urgEAUFAHuFbwFXw8Ywk0rzdIABwt9pxXTbLYnIQQ2
PwS+ZBPCIfr9fd5+HajpAbHC6oili1oDlef/4ALCfeMvNZKH+xHLMYGv7Hw4VvpSQzZEJrwtnrnm
mgfDbxuTw/pZ52HXw7EQUQOkTMeqnySq35F3XUJ59VkklA0V1odGW0WbM+P60gOxqT/Jh6w2eyp9
ycc3aeTk5JpFVVeIlfHpO9uZ8EEkQhuaoPGrTsq/KEjLH06XBYtvzE7njozj8H0TBWk5L+Pgxtm2
qixaydgLEOS+W0+g1F3IF1NJOqdOReEzuAfsjGeaMaxoSlvz+6w0UoYMvzOID/XRBa0h5TYeJ0Ey
umD6AAwmZeg0B0oxRk2BsY+OM8didWCqrgY8Xx4UthxicrOKwOvi539UktCqCEWHKRz6HVqU6x5q
qKuLIY5L6GgRdWcVINh60ir5dj/rEpH4hbniCuEzN+DqCIZWl+jSPMOmd5EOqGAMyvpOnbmfNfBL
e2b4xujJHYdJBFJdhrXJjY/B5UZ1zEMSWPSM8to7dFE3hId5x4+b4c57vck2FPPnDGNGu4S+oKN2
84zm8nLOrR1fLT9woj8rj8y87U4nNipUKUlqRwWFC99HToruxM2nVFHbd/lXcyk9IJDFCEptnr/P
2nVbjYGYPrx+K5pVqMaicPcCWEgOD2VTvh0P047nnfZl4OjI06uCoxOMTTqpu2cz6oF18W1LBIPU
6fTQMu0IeOvbMrU7fJMp9szNAvypebPStGoNjX/kVIrtYoXZJQDkgql2q542CqZ6IAqbUCtsA9m+
2GoKhJ+JAvBIjcTOM1MImVoUt9TMTp8WPaqpiODyjxryyWiSW/CEA0EXWYrBX2pfm63TyX97n3LF
sQMGOKxN5rKfEv12UGwg53/bG7/816kbIjEKFEZOGddcnwaegKU1/6i1StWkWUdW6mfcbTotJY5U
UmXfBH4xwFwV4+J0RecKz0yuJPLOhsqeotQ5PbPS28bJBDuQOgVk7YpdcfYhFHzHuvX7uf4loIDy
bdcygJ5ngp+5CYKS/S38wO0zXQAuAxqxMAdzzsKbrfq25LNiVcWqgSqXFS3iZfuJlrSnjhpkJII8
AQr+ZOjBrYh0Wx4OsNAajjhalzOOtf7+O8JHgcCAHrcoX5vuIiBccolWHfQFiKlaiwuj9G3ef8DJ
wCDcgwH4dJZfRHiGQaHG+sIfifoWHOptJBGT9bbqghGH+QFhpT8wKSnNWaqMM14C2Qeh7sSkXfMl
FIX9BHLgNsm8pO7Fv5rEMbbMc+fsPEXAtXDft2tf5JMnAJLm0/kjseGREVvAOp/85zoEfYZw0QsL
BIgLRXk/QAGjbOHpfzus0y3u2ui08yAZbZoPEL2lb7yki2SP183Doj8CVOUlhR65WSa1IvIAkkqd
g6YY6ESDXeHqt9DGQAHQ7XfNqxx3Ec/OieE0/FzjgxPh1nWmlqBIvmEaCnUwPnPN2crzEUwQXIZL
j5p9pHhkBjG7Bx/u7UKZe7wY22WAir7x3Jwk4bgVkyq17k8F592Hd8AMuSMogAogf9h8gBAujI87
X44DsD51CBfPoWPr9wUeA0Zj40/alk/0S0FdBViWCVubeGABEJWc8IWUH8hbuZvYtEejqIdnsub8
Xb387utjUAvlrc3ArtSwgBi02u+SOClDWA8lhRiGElolD2FB3PtgPAhxzgjgzWdWz+OBN56dhbxj
SeXCPeglOL5k4KCEBdZdfvfXBzptBvuD2ltoqt2HTDr2YMm2bzTZgkg4gZEeqKF1853eoUGnL1+v
A3PQXPRizg2gxBg8xldUtovYwPP0kYIGfW1xFljZDxPTqVSmgQngcvqIo/ov6L5NtPcGx18MgEjY
8tUvzJLuGLvFupxgXsHQXa1GYyb6zWX9+40L3hKV5BxV2vrGRqDCjarcT/J2N1B2F1t8jcRpmjt5
NyhTr7V7iwR3SLjk+FeBISZRTXrhw0W3PPa8QOVKR7xxPPnFQazTGtmslcjY2sIiHi98+Rfd90Yh
NZZk+x0QROcmtOqT/7dUfNX+mZmteV5UIqWR/DHSu3QtLv/2HEHN5HeppVL5HDxRmberC9n6ZMsJ
brDNAx0h88wAyfmz+Bo1we3x9nHdneswG518XWFyHVfdvwJEASnODxyXlFauZTzXiZzC+Wp3Pfs8
g9VaDhVQHnSN5CP3hAXat/QJSxBBHxg8NRkr69lLX4HRzdjA6QUw5MFJS5DYiD49Ap836CS413wf
iSkNmP04/eAN+k5i6ymOCcX2k6oaF/nkbg+S1PyrgvdmhIHCJIdQvdM8DWGhzU0toahFc82ejMuX
qmhd2rtDiAXIRt4KU+09lek14nluGkAlKOK++nWh0V905h3RI0RPHseR9DgTg49Z5ykDT+2gUUjL
tfH64xKSh7fab2d3z7KgZQ80n/w9PKkDb+ud2KFBIlnLL7yFXrB5GQbW6O+C4yQqVSldrPoczeXm
Mt77JF4Ba4SZoHZnzhzHpIrcpEwb0dQc2My4QcRmJmsk+a925624Y7iy8RdIS+7Oqa2fUYDT10vG
z58n6+TjZAcsfRDOHpMMjw0i9XZ/OG3kcbyhDPGLwoK7abRZpI8kgi+KMy0iVwhr4AhhsrmCYk1n
+3jilx94GBaMiTTDvHsnLLymeADm0dP5ZL/FiGYh/9NTmUZkRoobGENvsY1y/+ei+p65IsTdyTx+
F8xijzwgtsvmxqt07p0d4guLNVoavb4irGgs7Gca02m66RNA4ZQfWAxD3HZQ+m39kO6jSWxfSyU0
Q95pwbbZa9BH4+IuwxLRRI9P3vmyc6xYkV39zy07feN+u5gw/D48delrDNTHUbPMH90WV8RgXweP
9T+pTCLN0SLxeybfXx6oRU+A7S/Zb+hTneP0wfjy01GA5KesNhnVrYRi2/eGVWuS9gI1iKwDVJDe
qFsOSJC/zGoISA9V4PECeLwlgGslZFGviE2Z/5xLXQTdXZgBSTSWYxw59Qtw6Pn9KtJDW9gg0Hg4
m8IKM4Bj3Luu58waVexDSGu7njSa9II84EKmhvoFDC1dxQGaKztxWQsEiDwz9bcrDB4H3QCBKbVO
HX5uADuQ3CWH+wZCtpRZWiyrFl65ZE1BEJ9T0aWXV5pkBz7/G0v6Mq69jte3H/01+rLe/hmoO7Or
jSxyRUjjuEgonDzwU31I8AldRMdkqpTO5ZlvjtVrN7hI7/1KQkfsfvBdrycWwxvEQ4CFveJaKyEH
BdWHiow4OPyWpUk+4vp3SJOkfiH35wm2UGBomOPUjI3pw6DcTsrrdc+VdKl21g2C7EvZjIcqWgjd
ylBXdPsL6p+/vGvokBDloFOc9+1xWgo8TzDgK7ic51x05SnkZGdhHxubHYJ/TuqDMDoUfGfq7DKp
PP9iA5nt03h/iTADYjDRUAwu7+6XIqEnVICYmX0CwN8Ib9bN8by6s4CVh7s+87q+3KsM95na6cJc
upXn5ysSznNsfAGZTzds05Viy0ehO5/Idt2PSkHxB5ZNvXsiSxwEb4b+LDumwQa630MiDp9KDrRM
lUGpvUjqa/3wstU+AmKLndZS78+/HKUVdYUFOFTG5jMyH92Cw1XRpc9/W+ibec7P2gIfxBbydZ1S
xdjVz+rTq5XRqIgiiri5fd9kU4/4LDZogJaiVnM9VVsgcmGpNEeac7qI0WEDuvIJKCwLJxK63tV5
BRPZKvy1GMqhHseCzRf5eYwIauEVfJ0SaqQ/L+XYG7fXfKInqOyHxfwtQNDLfcNwfaJUx83gKRq1
Hrv377/eyy2Y9GvAVCZsETrrCJRZtvx2ZWzd3hALeAFzdx2qJlT/kIMReBUjXKu8EfEbpHXMCyrz
oVd7amKRK35ZQaQr0WT1UGh4rJ7C+n8RMcwXZM1LtAzhHhXG2XsusHgUMt4mITR69xiOvlbx5Hg2
V3uu4KoypPZA0Vn6/cEUsE5TjE72TAQiM4fBzVAJrd1YRokZJoXhVD2X/B+LX+f2E8bZNyLd39Gw
ehDUo+LO01YMfkBjpeK1kcejItcHcX222d7oe663TYcJ5ZP8OuZ5RGHuhYfPf1fHum8GjLYBcZ3e
ykCPfBlgt2ZPvkpOsmz09wAKA4U8fCbaT+xNcVFmFKg25BCHADGBcwevg9i+6Kh7ga9o65VIXnNE
2FS0YHp7qSuzgFCtbAIW9uid7FwDyc2VGP4RPOChOlXn/FmG66s/NsP6Px6fs83qYiOy1ns7d53L
iBVACsJiQI2dPF65pJw5oynx8AIHdRC+ZW+IOzP+04CQavRTbgFxWdAU06+lCsl0XdI7zQJgrv/b
rLXHzOzcEH/Et7il+GLWEcUXQER+oSn9ypVK8P32k0nAaHO4j84a5TopcCnsVHQLhd+pDbxYW+gY
sx5QfY320S3dPq8UYUJpjmPJvrqbdgdhTUZFtMy4kOzEAtQYe41Uan2GXsMULjTvrkDgpUQebqXJ
lg5vamQCjplAi1ygTTKvA/QjDY/cbRwwfGgIui4sgAyubitqTKsxc3YkeXzYj6YNmHzykfVwJ5CQ
Dy/jJAlgRXXCft6NMn11Cb2O+ioSuRkf3N5ESyQD7W0mtWfHg71VG/QDgzfauKFZt0PTeA3cgGWt
lzcfESkO65MFgRVDEak0WrSkFgcVlr0cfeoh6YoQXQglD3dGI8etx4BzfAXgm4+ZNOIsEVmKSH0q
B0Ri+weXHOR4IN1surrtwkByA/LmPxsON7mqLQIvLp+W6yATjN0EPR3jophHVLV29wCrEMDMAa7k
5nP0IxCS0cRNV/KFb+P/kbD0gyii8GGDasdTWXxrEiPkTOzrwZ/ce35RNXXv+OrGvwjR2gtZqx0H
vG3NZFAxsow91iAQKYTY8PlpBvHgaDjO+4/tE/s7qevkzvDc7VKI8jRFFNAueyT/hdFgGcVbf84M
2Gf58Kx2YZw2m4WU+A9WgTlO78rbbCdSRuEl6XKwaM9Czk4AsFcYHX5rORhoWs30dvvw/3kTNYSy
hFIlc0azQgWLVOx7DUAq2hZLOsT75kDBNqz3f3Khdgzt+XyEfQj9bG/4JGQgV8659zlTAaoctxL0
vphv+jy+lmW3Ps0Nxfz1hAjNgFnm0meB1axX3Le4TaLILmn5QNBTkD5wAx9SQrMfFX6mS4wSW/C9
8L2N9xZyf0shpQ6ZJ6eSTjS5fsx91uNIBGokx49Bj7L3SWOW7Op0zf5OMNmIjG8tSwG5KUiaRZaC
xIENtOU94kTH33t1FcscZKIX1/mzMT0Q4rS7Ahqah6DeYLc9JJdwNw15xLWVJtWU4tEBunkShRD+
eYiHEDbW3iaK7/IppND6cYrBYBWPQZMDdU0njCd3A9NTYB7g9ZywG9YpkRJeGTzVWLa4rQ/sRj8E
s7okYojZPuEPuSgJKl/83cSSI/we0w4zhsAC5b1AQDD+Du424UTYQgKXdJJPjY4izLLCsxhJPRzI
qgzVb+gXABdySzcZoxvv2O6D0xudmV3N91EbMqZ3HwwnKUc2D8bXdHESNUGmshlWnxM+EfcOEqQs
s4KXeKBcdS3wjmpkf7uwzc20kCxZ62urFvjcmQNoLpxGqrGWWTyccP2PjGsN9q/UJaU/MBC4reNU
pk/UGukz2RBBnXIer+do//KR7YPvbb8BLV1AGKB7uzktoF4YlaflFzIBSTcF4FmsJdj/vzXVHAvh
jwjuGq2ilZWQTgBWQRwLeL8v6tGGEHdV67eFCktehNRifIMdp189vhSmyZu4POy2b7ltinO3Cz5A
BF8KR5JLDrdcNgpGEAQQJ/VisQ5erYXCefswRMq8zYgh9boUDLVizKeQZTY84zMXJCrMZJluw+sT
U6Bz0XY3MmIg0RDtHVK7/UQ7pM5JNwHSifJR6Cwtj578xmJjn5AFDqKkhYEX8jYUqLOGozBJK2yL
4dD0LgLYePVARBdKuT+5X0c7BjIpfT7zPb2mM0KDQHhr/FfYzbkKXXOKRNHEP/WGQxwGSbYC6y39
yCxb5HU8Lq8DA+Kwhm/7efcx0F1Y8oJemDco1nivsisavo3WVpmOse3BU5i0EmfoBP5VabvayNYZ
v97XWGgacbJ8M/0lauiYu+fut8gtuN0mVt297D+w3Ihk7eCn5qUMg89EyjvHdnIAfQjIglyigFP4
L+0dS8moe1SfN/MIIh7Y1yOKxNeYBtPNGDVMeBNkk4KoaAfV2lXwJIOocRDF7TbOAzv5MN8sXOcG
/ja9OcbD30DejLExYaPlXuWB3L3L+gy4rgZoy2TPfu6sLFicStYf0AjQ7kQnvwl5+T8rPJKUHAu8
dHv4gsaH8c5dLUP3v7L/FJhbd4aX2JGpV7hmq57OZwerUM0+Q9zo0ZGDZS6fAzUSn5hLo6v6vzuR
l+4oAZM97pAZa7Iw50XNgDGl9B8q+3gLTNP+hb/oxA7ftnWTrxMlKtwlY+qnlTZoS/F/HLYbOmZ1
UEafKwrO1e+emxPKyFTTA2FkTu1nBWgO3IaqpKDSj7gVGdrQCm+PHHmOuqU/g3A9ITCqYns+5BLh
EuhEnxv0OnXaG4LUoujddmt2ptSepRCq7J6cCeMfLnSE4K5U3/nxzMALwF57kGWfVKMctpP8c+Yz
X8PHhzakrEuuc2qpYThktVl2/ReWAA/1lNo5p6/94J7DMkFro0phMNVshQUYkJYIiuKq8vBwpqW+
3Ra9uu/fXGJQX0HsNo3hfJ3EUhX/dkFIy92uRqmpcu5F47Gui3i5z4DwZ1TyW+P/Gim4a5AeFA4b
oawP6qm3krw6dn7p5IEHpL/0Rjb/fazuALs9FQQznifzcCwsiBEaGuraM8nykL+D7YJb3mEtvgWo
z1Yq9Ngx28eviynRd4i2fDHBDTHSY/WQ4pD6kzCpLQXNpL9rkvAvhdy6akvbG7faHLFLRXAK1UyR
N2jlB1B2stu5wd5UbtHqY8IsYxxGiigbAbtxDoeDnH7XVC3BRq4ENOrzSb2D3IOjE6LE19/OKQju
XhsOIyMIOkbhth8B2kxfOrM1h1BAkVsHTriuN1QJcWGbWQrVTjsnxVuv2FphfwUBu4uhai9ppKlH
8fWOSrSAaXFHxiQgzB0TwD+1vnCdgSrdINHrHwFcSQ9MRG0xpAIHy58lpVqCkxyC3zcgUw5YhH3e
g0G9L751iyWCiZniV10K4a99hrib7viD/rDe6a656dYtGGZYsbp8OyAGMGKz1nEttyh0rRd09UuI
V0YyOSz1pVbujObxyEJ0I0KgnVgCVDTWrzuX1Z+9s4ymPoJm9pB2gkfTj1MdPKDfC67syOKFxGBz
eFdxtAkLtYGYel4w73UNl2GDtlyUIp0watU140ws0tykFowQpaP81FXTSqseVqoddKWR9RqJgT/q
PA0+bmDYCQ5g6ffpnU7ixRA5L4sbg7yzZD5DfRQ2nvPf/fi6vevbeKb842X8cnUQVUm6UjT8sMDJ
kMJghKuOMeExbayuP24Xj50yTLf69hgKpwCj0f5EqNyGE5V8RpyGpPJi7d5cbm0dlL00KKBVXwAJ
/tWl/MbQ/VgZXP89pHzo07ccXS6N7poXkifegNL77LFaQODzH9TyjOaHNHgB0Ti2HCkEn881XDR9
Y3NKUT3X79PIDSVyVtLRKW7sBwCf6UbZOm8JnHM0UUcBNMW7vzV8Ourz98pqtYjW4ZZ8QlMbpxLM
XFHCKHQbyQzdAhjnTWpgK8tVFGJJi5YvNWy7W/Ji1KWcqCx6ps/E6/X6iIfZu3TJUM1VsS6iOh+x
fzdCefOIQTuiLch6hUr+dGoPFnencueUWCMYITsr6b8zeAwLJgJbpzPhMhmWP0Jsz/BzpO9bgAhF
orpDUJ5Hw2e1n1yvCjSeuBfVTZ2jt2Gy4f+o/Md1BOIh36/JQFVW9gdiks/sAf02dN3z/ZhELtOa
k8RvPG1mSgcJ4Zsf8AROyXyx3/WhgNpONYEnHyOmqVZwjH5SofAE6vtv7s/1UD71DwsQDaExR/Ag
98KVwzLAXBC3uzMM4gSCSSwe8ppaQu29Uouhdyn6OENMRawhSj9G6IzRZYV+v+w9KSAMcacUCGT9
Yx29VOOBxw9GlBNl4Vdmg+a2jyqvlzGxyxpIpdgAUa7jhouS2tFoVJgFCNgghtQEbLhua3v8aFKA
AvDx1kiEUSAI3J2axW6go/6eufmcQ5C2Sc8LRkrHC1Cl7VUl4XKonji/7JryG7+0yJJ/LMSU+Oi/
H6jGYY2aoVJqyM+2TaG012BJTeOfJH/9IQfHf304AVlHvvce586XMCBUDFOR2B3kqtb+Y5spBkCw
wqofaeJTOzsN/47Q2igwTFP1A68mB/co/bU7E3h0F0b4qokCx6KHCZMYTJIGd2WC1VntU45PPq7U
DjOxs4NOc5YL44cnTf9xDVUS9kgyjCvopah+nJPgmCAUT+EP2e/sAOs/S0Bs89UfuT4lDDjuj7J9
DA546Y1UZD4Eoyi/W4ahugzwXJ9sNy4w6ytO6EfBgphlKu1Vm2M5Xog2/rzN4RzazfnQh+moeOJl
hddDVaQsreyd5txTx+3iAvcqBhrwPglCrDshaDEnEBIHUKI/Y6sTCNYpRE4UplAcULO4QXgtkXLk
0DpkOECkN6GNkOD5X1HOKVHku+AKSxMTfz4Lhmkntd9s3JFxxAyo4JFxj8xL60dPNlBRoX/iZjjO
8Qh1GOFAPXK0hzdn5PdLF9/E0vUyqawnoQ0OlqbXfgy8e6Q0H9GVxoiakor1eCL+DNkmzbIKkpN0
Z/tniZTDupLBfS7075ZYs4tb7KAuUw5zDFlLRFrKgYJ3XRrWDHwPEmkTLLNpKZsk/3BwxPebnmTR
jrfh+BEvUkOImhrdkRYaOYEaCELyxzI24nDM2qPlofB/11OJIIui1JSJXFgJl/3S1XnPTSz8DciF
QXZ1E+JBPqnY8tOcaEtC6MIn1ihLrT4eec+GoYSQGnl7H+M88RSN3YMw7xZsi1pVlkkJdJAeUeCU
AOqPmHmmV5/s6Q2twvLAow4e6Bj7LWQ33SCPjeSIF69oBPaSEUfmACxyIIfGowJumSCw+5J2QCfd
EAQDjuSux1eQBunz8L7aWhKak12JuwWxVFMVHKkAK0V1aX4LNlDdWRnVJrCae3xh6qohsjDlK8jZ
1KQcJ0qe7Yhj4D8Ik5MwnBPTEOcaz9B4IFg9cAHh9Y2Jt5CH2tdH/v++Cut2Sfk1ClZlPvJ2qiLa
BVQjIfgVvCecT3b4kgvqN2r/M+r/rtTGvVyyI2qARSkBtLi0Qa3bRQzXM6tG2G+wWknq/e3RY8yd
SMxz+T/uxkyVW4ixjXRxTyWH1cFvqkemA2V/XjwOIC3eGrfyStOl+P79+mv42SPKPI22dkcMGURo
ikXHcHQkdc6bR7u8ymS0VRbLj+WIp1hKHZEtb5uQ+As3fUu6q98e8BNKEThG4z4XL+wsN4r5Vr4V
d4uSFOhB+bl/37ezfwoWABM5M56PzL/RmBzJtLIXeILnQpJjNlFgFRYFM1x/sgez3o7tchMl9Bw2
e2RaAgNkrzJA1dy4jOQZfad2gxTHO8d4T1OzK3xIdM+EaEjgg7xMte7tt9FrIHJP5zKVCQh/08w+
8NWDG2Wuyo4hZg4+Lzv81uTvhDWwLFI4nV3M1cCEVdcsAwOhhba2i25j5TivxYvH/LVIsfLgk6qk
MESTC0qHmruLNMf2qesGHk+qSc0Ud7K9v5iVNhV1Cxzt8OE7w/8FVIQ89h0PYLd/YLGG+qct+MV+
I+BiwWwpU/nLw5WmDMxdemdsIccnYy04Z2+/COiSNnpkiMJLx/Ozc7uh0ifIc8EpqIRFiLKxOd1O
uwNiFTjPQgw04yXKOY6TO/pVjPq9wigThupyO85kDvMsH6tE6OJiDK+aVgwO/WCZNMZqmyOyZJp2
2ZS6AhBgH9UDyl3ZQmXIWsyTAq8llcpaqNxm1TiiKr9KJwqjEznY6ZWgu2JTvpw4ahHIXws+qfbe
ORaJSrwARnDG7DdypwtgkwiaI8DcT/oetAo9jPpWEePScBafVcX6iGU7ekQhZgw1UdCwQdS4ra73
qrrPuViMtrp4ZB77FkI87fIrAnuX7RdRbZLjmg78pKc5bZDyFL0gY1DoxM2A9nC3T+7Af4vEGPFR
xBGWmjhq4vvLnkbRwuj7Q1lcsYDbmczOjuimwoaAME5bd6qaaNRGI2QY3qnPxlizpMnPvcdL9d5H
xJKLdjWLWANv5S2BwOpFb1qrUa+zRc8Y6J9assd4hdqT5+zp+BmJBaRdLJ7YsUuOj92nMKdCIaS8
MpUevz+7pf/CogIgSscgJpzGGswKbTHeey6rTzbhmVGMP0MWBNiZLQSilxc67S69Mssrj/D1P4JK
HdIB9dSSTi/WlLJuMkUzxUD84Qx3+Il/3HdMktn2jaW8kskFL+8aUPkZCw3kZvf+iLiH6Q+6xxGe
k56sds8opm8Zi+pkVWnJbU/vxm4y+8p2CSXVgRGn2BJpe6avb3u+wR54/Ys9lnOU6r5QHr44AeRd
II/Ch8U9kQx/85COtglREwfPsD0yCARebeen1minonEwh3OXkiZ4tFfahS7ZbH40oatZ6+GXOj3U
V0CF/QpKG0ApE83OL3OTP6ANHHZa3XJqwk8BJe6ow09534GLpUKRIeO/8kOeEYJj2Pyv1ISWC7/2
i02yIDbhT0yeuTPFtajrr2zuJIfRRdts/ylIJX3KnEZSyUPpLt+ycroEGc+oKR/jhG1sX0SteqlB
AauflydWBzPID7orM2IPof5ZV4niteK86oMJLK0ktBnZK7aJ0zLc1arXjGKg8or2JkxXU+rck4jS
il1VdDzR5SnXQWxey/p+/HvkO6sU1NNcl6T4PLj2qUK6Ufxlf97RlaG0h1TcVjlM+1rXVdDOXHdx
jei8RNvZl/fVc34MAbWlKtRNCJDpGMGT9VoEUJPjoV55aEFlGw1IH/NKGZsY+G5t3qe9uRg7Wg2K
kKgdyY5ULzkAgeWN1MKSViiqcJ6fCzo2yr1uGQ4nyIm+rhmfbyq5XyAbg7sNojHFSfuuGd8wqTce
xnYk5AZu2/9pwWE7mCIWA3LB4db6oO3JLg9e8YAEIQpO0BHWDW+mjA/ne6pojCD6gLuDJuk4K4ts
AZrhEKNJZIcxXnF1Uy7wpy/FNYvCEi1wD4kukj8J0H5cbPSIJDoEAsMTy+gdlAVNy3zN/56Wh9D4
ap+Ka2msGEuTB1/fLZbRsnG9W47b/U17NO4/6eSeM3MurAbOGelNjjX14s6ysb92J/r6uAGKaNch
bSWtgoqV5KKFlwW25QV8JwjlpOXWpLlg9ZhCy/xTdpb5ygd+b6E6mEH8wHbcTqSKunyEfqVyKD+z
SgmneIIMYcnKaTXPQV5fH31i+YmXPMj9Q85bKK++CWGoolI5uRd3D4h7IAKmH1hhHA0uJPQy5T8x
wZJIetnSBCCKoNBs0dpoXZz3sUomhpoiIk1rvpxyTAv17Aa+Ai8ooBwqfUYFaceWqCdNgOsGigOT
+gU1T5aidHgh6vo7bvP6GliAwOk1UWqZYFbmDL7qxrcVrmlyXOPtTUDaIJlvW9bGKtm9RV4gM01j
kWk0NCfXtH2JD9jJgxrRMuBHOwliU3UbCS1hb9mURkt4zxU+ka7visC/scJJxocLbacD0XTIk8wQ
RzZ1O2LqRVZQpSsPXHMmszkijpRhdDX7BddZ1BHMhhW5hmZJDQu+3n+vZbtEduzHbNsE/tEJScTX
6/wccw6FPY971tUHQUFkGJ6nLya4KJFk/nUWU22rhBLVj64xzU99XDkIRRAC2UJ/pWHzKAkP0yqJ
nVl5D9VF3sb+dLFp8+QWkb3MkBXF6UJsOjkud01bbZN6uO2/cAz4VSkVrvzUBhdHoQa/MVZxky2m
gVahKaK9zwf5PyF6cwwS92Y92vPZqmW1f1UBrXpOCLpXOi0SDdC9VaytTrS7XWKImnLu74pqKISm
N7Awszp9EneITxHVZ9tcv5T/DmJnzHuLrLP0JyysB4KsuIp6M+D88TgOHkJrAKnpgJmVEcPNulnc
9hHxVS/TZp1egQOK3FXp6SFSYmtH4jiVGapPMe93b3m6PFXphePw/BExxxTiZHWqorjqLSfS4qSp
bqP85EW3UFK6rEpjySdV6Oo+ENqiDq47NMfd4VBIgz446K+g7QwBQW81ubs/9TpufzxziQPF34Np
wKbLMqD+1IiiaTx6fObALt+DcRaby7hsG5DcAOgBVS1vCxkslvAtWJ+hLuJmaM5GQzhhGVoWamzK
hGRkD37tmXNPEqA6vLnuSltmNIzPPBcaYZn1v5qaWG3AQCgSOsYV0pO2VW6m1foXObZBPOmscuH+
UaLKjKpr4vPGtqlnp6+mHQepfYDRFqxXhMxGK/k65MpqBu1I/jsXcKD02EREh1WUKUPUvpXNevSu
kw1sw/vzEgXCfJayetiWW+rYEA+jo6nZ1Qnttsv8Zg7E8a8Iw0geuj0UH1zKuGy0Ur8vbsGbgTE4
NL5u8Pv6L+mu1qDoFQbOm7vWq8sAm0q0P4VzJClwOoLYHhL9M8Ol5VlsR5PQnzXbbyPI41sgC6Pt
7j3AETW+x8CWi/7Kd/VK5tz7uR3hSg8a1d3UXfqizTtJMfa6CwGrXVLqXlaf0i/2ol2LReiLB41Y
9vhPG0X6WY8iU+mdRL6+NgA5gJqks7HnN4xqP9sKRDxlv/ZBjIj7q+uITGdtBrdY/EVDr46Xv1di
ejegS2ZIsg0fu3vm50rp7hOvL/NFjmb8u/95yVuwWJRwc2Uj7YkVoJ4npRcdcrh9K9oZBH2wsQJA
n94Ul2Ttk7W6YsGfpw5omwL8xAcn+4vJv11tAe4h7wTlXVYoaFOIHZwWJTcRnmMPmoAgBT6l67BN
dprFs73LfNE4IcDJhIiut5vNAecyD/kIHcJvJVIh8d22z+ArzYv/95EVGLZP3HYke4WanyT2YWrb
MVAGyaHs4GIAZocoPuiZP0YAdygAMSTUxr6PS6EVdEJPgoji+7s+omgttOL3lfSveiKlkCg7zJT1
4S7wi95b1nF8kYuV10uPWDZ4uJ7Xv/L8Yi3+yhF+Lg4a6TsSqbMD7kQDcgoQpb/fM3ifSEhc44Fo
tKJym2Ri0/jsKQC5Oz//DhCyXESIO5U1IjdmlN47NZK962ga4gTK2An4e20+nmhjSSMGsTk+R1SB
9pvSXKaouhHxZGejdJEVhlg7Xlv1OMnLf0SvSXgcUHy26aup/9SYMAiOJyjT9g1zwD0l6MyVJtQK
iShKG66YMsdAYsonuFrbQwT3wMjTfErUrjYmMLJeVqvKn4e3CQIXq0nFeWKRc6TG/aBw0oHNlKam
aA3ysPnIKi1Cjn6zEDW2OFHDy0I+ILxGAlczPfZQg1FIMKPMhZT0bZ50XTi8WL+59SXSNEGezQm9
hH4buS0d/X+hUONq7C5hx3KdZI88qQib6h2bM8Yk36vTRC0T0b2HC7Abp6RkAf1wYtrqbFITXm2H
LTse6ZFzvoldo9VKQ3jY+V1yX/ELcz9671lnZxUEhfCfgJRC9uNInNqXxJPiHj8rLJ6h+JCGyurV
GiSMHFo0KXTXLNsXHcSI/MtDcG2Sy7qge8Ee+QbZ9Mkgc9DyACndlsgqsWoxZPe99E4GggyxlzKk
1ozLBB8uwr08si1VaWkFZ4QFBo1Ug5FOmg0ahU8445CHIConwpKcSOuB9yBShK/n96YMZuGRM9gy
GArntaSOlBvq5iVSJdHr/K5WRuQ4klVxVlmrPuPT9VJErUWx1QBdnV3syAbHCK8KGhplOSnm8dK2
cwlux+6x/y6cYl2qURhvcFboXM7vgKWo0MHnE9pJgqmD+eCawrNok+0e6Y7D8xIO+pnfMgiRuhg8
NcKXi3VXhLqriyy4Y/e78obKIGdQIg4EhpjrjPbLkA/uFCGkvRsGZIU8XcdFDpwPtUzxCGQtW4EL
zaWSqCxkh34up7EJ507IK63nISGfsgflIDXhbHPqpJSTEwqjDpF7Lf5Lr+dSVn24uR/rVr1K0Zk/
uwr+oXVtluwfXcuWq3M8NL7wvfl2qo0ySxk5XX+NdqHS+JbHNoFTC1F3FqsYKb0yB+kwkqILgmW2
czSE6aOmu77T63yJLJqJ2sa9CEGNdfbgVMEBEY5CshUzgvO1wzzUnFoztsvZeUfCWqe3NviE/kbx
9f3GC9jKSLLUADUVYKaF4bCQeBA/SEYHcXT4al3d6p1wMBHn/9LJgDU/GMdjmBYZLOCJwUgDQLbO
peLv37j4OfzBJzA6ik7adAgw2QuQgixdWfDHs79CAto2g7hIFU+/H4NNnhma5PXhBizlDW33coHh
cu/3mK0WlwEBOHEO47pb+2Yy9A7LFPG6rDdDcWQgd9jeIEOiYoF89uev6lkbza5MvwJpaAEpKxeO
PVif5RZ4lp7Id1bZBpZTLGtiyAwjPZU5aduHGdyvxErfXwtdHkp/CzuRgplokyTK3wQXF+/7yKmW
BqAYQ16OaCVR/o9SE1qzLys0cjw9Qlvi5Ix3PUJgIWCpjHUYLeBtkZqrAJxJFuV7rOCSN6LYwCVE
zlHWF9rF8xGBx/tRKgz4jW4QZXsm4PKSVTWMx90XJSZ26p6Mu1lwWRBbYYEaVpp0ZFhxO9PdB1Ab
UyS82poV2BaiMdJPN2JwRprw6tuzGykoSJ2zmalWbr0IqxQS3/Jp8lFdj50PmpmmJo4sBvfun8JM
d/ZsM55ZEBYjZlMzTf+OzxjIjZbJaKWGrywNkkguVbyDI97jVpw5XxxvaKZxDdFzaG3UKN8WL0Us
xMbp/8QNNOe7FmURuN/liG8We8NZOkeS8EeZhprikdRbnizaBiyYVIsYJh7oTp+zhGwa62m12iDf
/64zBFZ+PU6W+eGKGDtJJwAO2S1ZurkagjToqqzBVraSYwROT1tAKjrk6IiO7DopirGHN3h4hktn
rSwdi78ivKcbRL93fATAfcAnzoEDOCJCLHjRLewJNaRw7M/l5Kwft/P/nydYGr4bs6gpKTqcjAap
uob3hbk7m9LzZbNCCQmMaV/dHiLZBgBl1ykqMjP2xlZHDvMiDhG6HFqoqOIjeBfnlUQrhudKsQd1
1skGnhNUunIYdKgYYwI4qSKs7asDhSmN1Og9oREj5lX2zXc4IGPKDb/1vqQKz1vUKippk+9rjPhi
JbCKS2S22Gz/LhUgR2ncjb4FGnIYUR3aoDDmus+tePYZ7WaLk0fIg5mkiR7GEwU/JxPemBoYBPU3
TCyjMzXu85DTHwtx7Kua8y3HjjiCWCCdqMOErkRwm5DAhsjEtuD+5T7zBSduTzGfkAKxgMGckTv4
jD8k8PJN0h3DLXGssxlRfyJgYHzWFqBj69t4crP33QWaJ4OQPnQNGkpk1OCYp8j0veQikQ+qGsWk
lQ2i858+Q1P+S8siRPQsmNchjeAtyhWBi4K3A+aI7wpc6TIU0qqwyuMTi8Qg4c5tIS4kizvcZ8RP
+RW9G6RS2dki3XGB6fjpdkXIPc73Q1SC1ZPOA0N/1IlPUDvYluynR+apTjWh0sZt4owzLcJC5ZGS
zKRmS3odDRNGDY/YvTG0xb1nCR5HIQf8i/ll9H/E8B1gcIJ41D8ndQGORtBZJZSiBmEi/q0B9th7
2SBccv3P4C5S2/UlSNhCWsIt9mUtit8QL4ziJhBj9x77smRPy4XxYGz2MaAFms2ZmwX/w2uHRqlE
ei+YN7sC4moMUZa8ZdY0ogwkGGE30j+fM2R/1xerlxghi2e07K2eOnVsJdqmRDCy4HLwdGA08cf6
8VV24GYEpD1MYRUVKBNQkoVULnOOHyxOUrqYiRMDJ/U8PMIcPyvoBYfTo5bEHmOjoeo/nrs5MYv9
Pe0trbmQQvC4w3gKJYXhsGm1j30KUaoxyBU2U56+SiGlDuhZgKN7VxSFiAPvu1Qh8EcCLkS0byj8
HRHMQAjaDvVytrxwss5LMPn5mdIBA3CuSg3OvTN8GCKl5ffbDDlwXTiVMFJyMzfg+VnFOSfVy8gi
UHJyZPW9foxP0/RsW9VKzeHQqIxlLNky2XDeJ1wookWI5K22529kLFgBnM7yfwQdAIg/jGgxQhQc
Tuz9IML8/Djysg3o/u8KICfTCXBcvbQRenq2sjZKGC0M8d9oyLqshNlEuC00m5b39hGy8LMtXpcY
VsShBY0jjJiJwjrGLh2sxhnwIthR+oEJqMBrYyusgI91ticHxiBsVMwhZu9q++cCdEZGU0Fk9iMU
6dnAKeqH+wfIJorOFhe8CNO7OLoSBJFEYyK9V1zPdQNS236MjbhEwyJvrbXs+R8kLo8KyRxaXATG
1uMa25Pb79CZ6No1nCIwV97dMx1PZlXkxA3/FeFzpbkcPBXxnUUJKth0MrMCNx/nmX/fxLZrnnhw
wHZzJjwrvRxOhG6mQ9nBde4hi5PAPqM6NFecKOw0Xw2sZ7axAlrS4jvg2dbqWIA4bAkPNHvhbvzn
ZlcnZXIASX2cL6YLJchGFCGOHF6x49KgLJgJTTAdc2ClxMomt7ookiEWNUcoh7nOD/bTxrvjM8DY
Cyu+kwOuPmZmnArfZK6ib53VXxjYWbcRk7HfVxr4rJcPPUecoEFhVoWwT86w+gOnmyWjoXhPdIgA
acr2M1jrtjgaWV4mhtKSLphg0AF0vlUSM0VInZT6ykYoxKuzm/7O/cJIcrqkjY6hIidMnmswOwPd
XaZvC1Bb+oIz69uNZSfgsxmA7siG+lXppt4PZ1BzNacv6To+hGrYHz2dg3iep9kosTRkbUysYCHu
wHA/1y/IhQBaNMufrlDGGmKJnLYx/Zp2LfxkPQSI4wHAtAvK/UATlBvz/RerhHENtCSIHRU3JQKH
LDP9C1CA1aDznMmIMvZEg/w/1RPw2OihJ7hx886yxMeSGE2EiRLUTk+s/vlEq0gM794teke318wD
iqK52K6JJndCdWzFrrekr+AJXQdD1pBI25v1vdQuces2Jlm+iC7HXWTXSPGQsUjHiXM2uzU6YsHb
sGCJQOzc5DbYXSDK93L/v6cQIuyBDdqvgvcVU7lxXcDkHIIFkLVMjD84n/VCkd1UL6JTLeRurjnz
tz5KVA27Epy9I9EUbe8+HMmY8UWOQgDXBC0WRJilqLMlY5kqjBbhVq0CAfP1lq+s7QbsBYosc7Ai
3bELm02OmBGtIBieYiEV5fxva/zwrTPZ81eGG9W5/4dLDiesbAGjAN9keqqzCmAgR9CgowQ+5tHw
+bP+04kjIPINquO4y5e4f3VsU5Jd2oU3DCXAQ9GHGKFP1BxmKSB0ulPZESqWSbzdSwiBf2ssqZj7
od72+3bS3puDhLhI/fcqATSv0nZcD8P+jbsfJVIivU94b+WAg0g5KrbROY1sG1k6HYqdEl5P3NRS
DOrEBbIXyfaGiHnwTCB6/Tm9FMsWnR6xI3CPfGAXUrQvBY4Et4KskgsnIrEnMYeBsLpqJQtBs2Nt
Q9i0u7WxAx03kQD2dXNut0adA66VsCpGOHJVi0TdVQErJD74eE1BUISBbLx6PXRHSWTH1Ywod3wK
AkYT0S+YKGhDyeExH+o2mXXeTwKx8w5Rzm2bOT/20cC5fDt1M+hFNt1aEJize4DKgnHrFjHP9enn
ZMeRi9kT+5xLrk/shoulqRScu9+QUd1uRVTJeYfcYJzlhu3KHnTMQqqzdJ8Hjsxb3LOEAkYWDl/j
9Gg/HWzhzCvysWqIK3jbyoraxBFyOcY0VWQhICbsp+3JZkc9Ti6B8ir09xKadG4EzkBRk/+7QhD/
tOL1gvEUvCegpG/KnKmId6qbXKpbfC2CoHkZCmkdGZCNQprewTzwCuN2U7qrflN3cGWklSQnVLV3
VlnhsaWZeakgVzc1bO7PP+2KfF8+Aig+QXyMb43MU/Uql+bRSSFYrhHxwXlzoHF6GerP0H/eGPlK
rEpbEKg6znGnQoxVqTYgXd4OmI6+7ESogVlGTER5KqvWdnKX99p7iRx/or6AL07FKa/l1sVvFzvO
mq0/ewG+IdxczajcZ6j8gxc6JT47Pd6Kx9A+13Ha1+jC+hXhpEj523ZSNITforG+z3rbL8EtPokp
ZnmoTqgRihfxq2kTLEiYSBRYVkLw0BJ8/UQUoVgVmCt/PVi8qKr2Cw7te+H0gWtAUbHS0ewoeTLP
bPk8Pa6g9xEyDxLXn76q7DssLAfsKI7Qh/9rIIUMYzv0XRiRFWViWd6HAMZRS7UAVbuHnYFgbHpO
Vt/qMWsE/g7sCZvVb/crg/APEiG2IBtWVuPtki/1+TGAjkFL+3+FYABLs5biW/2tVnO+cxrYKR4D
78cqJguxvttigpTZkxyYl85pFxmjhmDkjBFqe+QQr38wLwV0ceaH0euMj/FV3rMV2SE59F1Gmi1T
soSa7/iGCpzH+g2DJY1vFeoqNn9Jq3+dXAcRq8tOKgm2xbufyn6Rc84+spP7axGxWFMLybEaJehA
kxwl3NkXOka5Ruv5VYW90K/RbbOTbfMZfCadYay4edIVqVFXl7KKycKIgZRWdk2SOIgy9k7gYvRR
KRS3w7L4UxvuwoEdIDzzfS24pde90WeT4AcIFo+HOLnzWvKJCNhSQQmt8VG/MpbOLlzWrESk1o6x
QsD2mutPROuydwT7vcYemkBHHGJF69uAy7dmSIWFqwljUf8KkQd2FGqDeDWKpIEcEjsskXdAFYCX
xlsxZ1JieR8cxC2SjgAGhxxtFbUruD9UQBkqUW/dbsys65nSjAL9cBnfs+ckWfPM+7OIhfkh7QBT
SmjEE6QOEmokeEnxyWHbD+jH4eE0Jjq8Cq7XjdkiKKfgd/fzeIvBU7F5ykuaVxvrYv0bZeyMH4C6
zkFvIqaK0MEQ8oYAxISvXCT+c2rKcQ86HYO092GfjYeMhx6oknE3gytiHQSyEwbB/Js2djjLzHfD
lUsKtmbQmszajWQhYWD5bwfSoABKjpMg6XsgtLdvRSnKbvA9FCghy1AiYLCKakzV0V3y5lNTbcou
S7ZcXspArGZ1y6vndButuhHaVQs3PmZMMjgKNoSm72HZx6vlTSy78StHUMvi1Cq78k6J025VanCR
ntu8KZDVGd+/mkBvSQ3Mmf6Vz9t+jQrFBdlzpBTm9lB4SoBwvGbv770zs5ZQsdpdJcPpK34rZmXF
RL0g0mc46WE2tQ6bbjgd8FL0dUZ5zN3hcmXsP52hIIXLytT0s8+Lpdb/Mya1z5O8anaZ0pLC66Qp
wgSM2JW2N/lS0FhQDHBjaBherzDRIxr2G5xIDW9V9Fs2gVEVbS113ZlzKmlrHpJABgYUZ6KzQAhD
YDcaRflyOEuP79HZNHWhhONcA2peqX/vJ/bTFyzfM0/XqlYo6IiqXB3Uvm2VWPDJbsYxkuQJ9MBU
28il74P05RABdR8/YdoZzqFABC1sW3I98ZpaCQJfRxFlesHGB68zqBjm7QDeCJWc1Vxrnm7AkZth
7jhcowtN1jAkCaqQQi791y4f/JpcY0dDYFekrq3B/HxKkOfUObW1ATalk37eKBgqrY8/AoG7AJ4V
GMZlqvXwaJVQ35Hye/ObaKJKwYr1xP/dktl19WcFacH91fFEaiJu1Fh+xrYejj1IkQalLlE7knjh
Q/o1KSK5ujkIIhrWjtVJz5IGEfQ2lOsnjEPBZfKep0vQE64hqNAvvouDN3UVjTzIMwPotUdBJ5So
hF2fBNM49qxs/po/N9VH+FasAxMPfKGZGPoU7VMm2e+L/yfwo97rQFXsDwUtqNTNvTEtAvaOzMMF
8QW4EmcvKrMdl1Lb279IIhJY1Q5Z4dB+/jqbAIA9iwu7evhNVbDuHFXI+bAIZyeKVEvx8avkC0sW
Zv7JD215UjzWj3vuTnqRW3N1isbsWtdZjC4BDoYQQKBzHPc9BeOSbf/r5PLUw0c6bS5gdsdMORLe
7vtadrki1DzmZnjndn+cO/hOlMdZYYBBCYXdEKcfG2Zxd7BZMGgSW6t+BNkYPlZ2r0//QyP/Nkrq
2vGNf/xxDJVM0QTSE+mUHsIRv0z3ok1yf3lPZlvomCdHGZ26LAR7jn6nQhjHS4ThQtto8KD2+L+q
raJDwQrwPIfjme9vHVp5VOxZe5SXYrq2zoQHkyxYjr4rtRoHT/+ItgGKeQegT7xdc1KZjPtfpXIj
Rim8bKWJHFLd9FnGOEvPoaZsQdfDU4kysSf3GvzJE5djf11MOjYe4urWJLvukyh/Zm3nfjMO0fbj
MNxXSkLw0ezqY+tMVxb9c5VUp7rTslPNn1kWvu4gWakaYwgHBKshSOoj0Jf/bS6bvrr6SDEroQpT
GBkv49ZcoxksPTrt0UhhaDdP7cJ1x5V5eOqE4fohnwkz20zO7jLUvXoWRvLQIova//MmtCRy8bkY
yDs7bK6/L+jSoXkAiGbePT3j13LZiVfDzzwVA7n/31BaLV4i+huUpDv4t4mfQXp/pYEZGJExSn9x
ddjXQi0n9a8Ivb5KadC0Xdr4nMMLVHYcvUWuXvZW47jW6ly1BYHVvYih5do+Eiz1AKffdeKywe4J
7Pg2bROLDBjYd1kQ2NGXbqPuDmaL3I49eKsBc8PO4e6obJnPqmWgpBFRmj3lUdM9xRR7DGLXzGel
Z0Ng4BZr6uYEDxBHgP1Pr9bAy3VnmWP7cGXx1ZGvGggblHNPBCfcwhEErSpAPZ0U7BItSGweN+Pn
C2tckgJaY2fLq9VjsfpdnCuShGwEuXew5bObHpl5c9cRM6IZ+x6Wuhu523V/uhFTjt4+g8FwUOM0
uvAT+9ZbD6hPBsrTEsRZEhZdg3UIhehRoK9smVGJhHAzi/ispMaTpWA21mCzifnqQabad2Ls///D
x1MJ28YtyPZ0SAkTzm55ZWyMMmQuONFJKy47r/iIQZz1JnftSMaeFVRV5Y3B8su/pGj7tIuo2Swq
ndtY1C0wypfkwSTC70jkzqdiPhIP7bVa5tkdwf0bbZ7zPCghzAtrGf+Uf2rvxj2L6GbmM0v6Iqh+
UzOr1Vsh1CpiQoaTmTE1ELL9jwSjau6QG+lqDoq6L5oAcoxUNr9A/ip5v2PEYigTcrIfi4oSALeh
yqHnVB7E5wOu+wL2SFDqJfomv7YbVFYV24ZNCRgkZKIUrsxkvKcauct09MFAFqFQ7dia9jAtf6pW
em4XTG2DQgrtrmzG/tLrftUovnJq/KEa+uZGxft0tTi9QlfAeZ05xoEWe5MMEe/uCjnvzHyKODDG
sPWnJx25DIIxnCHtQGH9BxA+g3Y+FtgvlMjefICK1AoIYJhDfczUfZo0BvZypE+pCXpRUtd9JssC
p+1wSbHxKvFM23AF3rBF5E4DJXHax0PRWxHYaA7pk3KaQMUz5bb5aeg1TnHAe4GB9M62VhrtGShL
oktySkQruSBNPlKeDmKPS3lpsxpi4FmZusQeh5lqxvP1lchxRexun7xeUM5X59rR0RQVLvjXRVpt
IqS9wyijc3t3KydV0Op3S9fa/9xKoKS2BZASJxFG2zjDhwYHPtKoufhbH5WyEIzs/s5LMxtzrdKQ
u2c3PxnQIVtd4Vs3rqL9afgW4v9GdBzasqRfjB5RU4CzZvQUOiqSL7TDeFEC4Qfb1R2xzymCczYt
cznnWgwQ4uJBoRZU4uID9ma57FQZnwFkLaQ5CnU37kYMtLtoSBe5+qgIuTAdfCfi6PlW1iIqgxXf
hGX07EFyyJmQb71jioEgiz69FtX6sDN7GRHeCsT5rQenCr+pxbV+W7Y5XdtCIWwgamU6XujOjPE/
SwCan0OgJhvJy4eSzMTAx33Ra/mDc5W9dt3c3J0W2o0qVhjghOntVZCujJR14ECRLmt5Gn89wwI7
JeG3q5WPxzFkaJqsIuBH0QdzMrOSyZM4Q/2yeH0O9OO06TSHSaQK6EIHhIl9FU1hNBe5EFu4XI1e
96S5TYx+bwL/tGwN+CEit8z7jjYiIQgsbT4wyoHzS+AsMk9ldGxVVnRbW6r93nHoXjK3LHT4G7aZ
sVnubktzYjIJ6VGYKQOZZC31yl/l2EMUgYS0VjgMx2iIrxjxlglE3tUV6Jvrc0ABfauTfJD1AsC9
y/ylSa3JCErr2FHET+W/NhhBIPSPnVopBcn1jOfyRNe3yD4MOt7YFVzmAkkynYgW8Q71nc16kDVA
kVaZVEhDgNrGLqlyjWFnObznsK5z/3FLYWhnOtwzcte96s8tZSdlEw3Ydd1wMsIyDu3y4xH53+mv
WMlX/KeIT+YfXXTHaaKHEeas1iOms7rjX33kMD90eyU0PMbRLGMTwrPM44uSWNPpBWxIQ/3Ie9Bk
V7HujqxtGKgGXdsqrnu4DQ2MfhOze5cIo1pO0RDVGSqZ9WmWnQ4lPeYlcXFRAD85FX5c2VWzcZVQ
77StIm8KBHaIyOwbHw1EU0ZL76DahnOi8LA7h9aIq4moR3MicFvqIhrnfNP46MIo4W0cvBeeMtYT
2VkMfSHmJvNab3YPjwM+3YUrw2FDypKOuYawPq/WKplGLDOp7q/oKqZ29AA508DiZRb39M+Wk9xD
EbvTPbZ449nXsUaVi80fzcMMyHFbj9ykAGu6ozlJFRWZlM+thyM90hn7b1Xy67V5mDUBfh9gwcD3
VcQHhuXny8LxsKUJo550fJoFgqhyewR8s8qYwUo9Z2/ezbntKHq2T6CZFiG7zzCvOZgBRzg8fgab
ALMSugHLWBb8MT1c0zQ3ZiH+8xPZwVpSvJ/idZ/vur51m4mwv0PX//6NpeHmBmDcY9w+vEv9gnTr
Uj0ypFz69n3ujgKFlNATO+J0+L5NcRFEoAxvqhhZ8booFdcCHjSzFRKijjf0mbxZ4hxMS3sdJx78
0Z0YvpK4riddcMQz6asAu28uCF/6VNoH2QmmK0tCHdZdmAAZTEZyoTAWoYeBoXkNGckuu7Qa6Mpy
ob28JCPzQPSCnFLDNFfFec87/ki5rXloM6RyCHnl/sKviZZkNjGzOmDDJIrv1x6vl2lP72UuDlYq
EhBa+JsDJCx7D0x6QaO0hE1l/DO9U9Ai176LgfyNOX9Yvnq7So3EinxcjP4+85gXa/EaDtCiC/sH
QW/wwXByH//AXEwXePkzoVaC+d3zIAixJjMOzYX3Qfq8bn8wSdoHPD7TLAexQkopmG8yN3yIAKTS
QdmuKxrAtSj838O38K5NPlqtKo0EPIOHS8R7E6kVvIRdbrcQXPb3ERr6tEiENzpDWzdRTniXTq1S
RHGLhHZS935goFhYpjBhsbEXBbaH2G8ZexUaP6evQqAzawNSLTLiyXFJGA7IJcqp1I8g1VqOdN8U
6OE/zzQlGlP9kUPj3hew31f2Wz8aIGPRXQLSyHAz5WrMvJnVU+abHZ8S8+yG5vBQvU/Ab0wL+Avi
83tTKELpfhJpzJqpB2TgeUYYDEpdh29RHjEMeSFEQF8FIzVg6l4YTE+g8a+S2bosWsRNdWGxpsv7
M4247jUE7SEIr1IPMuqIxN7qgTTIH+QuQe5djE8ib9nBD/QIPyWOZ6ga8APkQ7kZrrdMTrhCN1Pp
i3wS9u33OaJQR8Mk9fTXGz3xiyDAq77cz3HcYvsq0iS4QRRUjR2fEsoOXXBWShKQwT65NgS2oWQE
mRcf9GCRi3CJVlkfBHD/jfnVgi0TkT5CBKc9XYwyk+vMBr1OkTscLk+hVv0r5Y4gceo2wvPTA802
V5BJEvHnsywD1sGN6V8Hzsqvs9ggcSXhI50oXNGvunWu8lxZQh2eRkCYXRBJUnqE8JEf+88jlTCb
3kbh+iSiSsuN0XKupC7G1BPQcGa6Hh6joJ2H4hx4zn4AKcmigiKiKl1JV6Rd3ADBuPuWjhJzQxZW
DIs8pBE80vzJmExLBWh8U0Kb/wKfiq4Q5cqn7PTtGHzr89ingaJ+Y2nTWE6YNqVqxfc89tEKnrN7
PGZ6fKsfxJGls0F7t8QdX+0NoWldmdENNFlmsMJFCTrtzfRQ+mSR3oNleVEV64ljkgqFxaBDgP0J
m9QKUvHNb1xzQ3f9TqeMZzlRV+e+oduBIABOzc6sTW1yjY7WBQAbZwKtQqtmoxNlb6SiswE1hLtw
hgYivyqbpTGaYBnI2rKRAxIlduADlCDyP1IT6mQ5cC7ViBV9DBc/b7cQ3VWWAwRSvqI0y+jCwOSo
mXHluHuE3sEXbjzsQiPuvzeWsu3caUicgcnxMrs4blJeMaYayD4DrnAMvuQ2nzPw2W7k6g8uZ2uz
b7lBv9nuTjbwhqcrqzmXBLGxgbrA/9lwjFFzOHZQHZ64/omxthZJF7PxCsDEAmLBp2YhjqfhpUBx
jbdSvSZJmEnLWNmqRxUHSgOHEgDBGOHGQWRSYLxCtWbT5pK27wx/Gu7xaduxoTZsQxrwKPcHJNCM
ALrZhR3w+K5bggbbC45byOHq28icUHe7V258VZPqlpoloXX07pdqLOKvnQqNHnGmm9fsW1GW3taF
BJwqY2Nte4TaAsGCJqXMKclg7/DwojYAF8loFwA0LXuQKF8ND9cgei4puM3YDbbf96GAaOKaikdc
yAHc/BJmUhpEzV5Yx18dRYapbWydTdKGs91LSSaUVXvm1pDr8J3S6NbQ1IDcfJ2OGl17NPfS9O1f
ENoTJewWFbaFXn4PP5SDoCPpNGyCg6/pS1hieOIP4NBvq/B1TezK0UKGoj03epX3T5CLBsXu7AY/
j2EvGf9tLrUbmFkL89gC0ykkeLs8tK1wgeBCAjZ99NlWJaIMZqmQailja7i16syy5b4OkdrM+gyr
e6qLi+4x9zRpIxVjEoKAiGkT5UAN0DvsEKAPMh/fNlFfk+JTuAT4gpVPHfN+iaxlZx+hMe2y7tOH
F6suFa5TKUMeRTnrgvXqw+sJncjq4IaRov6P0LJGTMAkgeHFOGjcdvo/R8HbxyRj90TvlrA2b8AG
V/KmPJWZEWnhhh4it8mCf0kXUkoG3GjIJVGM+N63zaV1A0FnvYTV0bP3N6QDPKRLgyiNBB9VcG5Y
M373wWVyR0Z+FPkzQ/0HP2f9f66b4JYPaL0lVwhf0mkhBJgk9xXJNB2eMi9cdvwH1hkSGi18GwXr
t0iFL4DCwvredlGAg9p8ypf2/xQ5K5PqMY/5gCXEh2sPIkBs+5gWyx3Sq9zwKgVy355Q46VgQ5Fu
sUOcOzaLoKQSgWd+T6cstMiK2bLYxqJd8u8btSoIf6K56adq/0250/vgXXXI632WAJ64ftGzKFQi
4aP3QfmO3JNjA3rrmQtBRplTxADUwEX/yaFVQDLqz52tquTzag/Jizt68u/tJLxoyL/GcKoUq2mp
XUfyFrad+/Pv/u30JhUQLtHBrhNC3w6HDRjqRoGjuY1QXcpFeXs6b+JKo1msP5HDUwfRqMk3uSfE
gHUXRU+Jr+j189ijqX/d1fI0wGpEo6OSBQa2mnxPOingGgFglQHF9MbCRFVcmbyRZQW74K5D/iek
+6NhuUBJiEdFEbRxA0XTSmCNqEeMii4vrttNy/8HD8YXI7eeYKddnRvECjqczMsw4lymywo/EOGG
uGN726GMNnyJ4LMcWFhZojcbs+Y/0Ba76vgYRo2XxHTLfKTMgGr1LfsQv/hx1UjZXwQ5SV9qE8di
+1J04Y2b3E7HoaiHeJ/uwPVnA3sfgFjMQNFuCCsvSR9Gj0Ldq8f9KxPa7Jqufvdc3ZSxueKOajYJ
69SfjeGsXFDf9h09PXuDhQHMNdsCqi7IvltayCAsXlDw7hGQ+O1k4dUDZ6st60cED6S4cAqwzvqf
ueoUJ1R62J4eWGIRnirNBJrhzp2h7tj1BYwknicEN4kzHRGZ6dHh/djiBpt0J1a0Y4Icwxv+Yk4Z
WIcK/z+H1qJ08mBOolApxJSIni08tql85UlOkM9seJ7Ru/yuzriK7Gz5YjpDO7YbAxMNhN7ENoCU
TAOcN6nwaVMeWWwfAfT3242Nhz6LjraFBkEsc59f0p6gmW0WiPfTlm3yCTuFYNKYWjrX/Kq2q+sD
lAc/Iudsy+ZImBYXK7wYe/FH0HACKqYvCeM9Ktw+ddGPXVUYWFS7bLMJvuLemYTcgsLi+YTVzYMG
oTrmt9thbU4M35k7OzD6jdJwINthCxp/2qfkqWJH9anIOMksIoADWmfFVHdjSsNKz2ZoHcIor/85
5XXKi4llCgtvBL+ZEP0/aU1dnZa3zXaJi1wr5x2W1au3hWIDGgY00iLE44JKvRf7lmv+9exG/gXT
EeKKwOEbjPjABxOf14EuQlaQCwugiL93LaeW0ixaBCs8bxWQQpY6YOi3Xzo7osRs7+XiHEXoWa0T
VToeYbn3Ezm29zvXd1GYLZKy8fzsmi5Xh43qKUEMmhdmio0S/0aUFHDXowhSaE9SthTiFNB5WUmg
o2W+w2Q31VrtffF8YnPlouQF3c5h9cNNwuldEqa4HKG73Z3gA7pWXjVVcmhVZR/rIBnnhlZH/XB/
7LKNVuEwdp1ZEy7n8Jx9ZtqvrUsYiyjxaCVxO3tqVn8sNF8XknCPEo8LvxVqeoM1YYUNDAyVyVqT
uDC7cEJchrZUDsB3mWjFrBVBhV1wGKLXyjQfClp9sxM+IDgsaTmXhmTBanQIntNs4MpjzkBMpS/E
vtdcNCJERppi8YyYG0W65J5tpId1kQ2BVD2fTLuktGsGi6XVtpzxfOBEM6wQ4M8zD61dQgaQksuC
nZ1UTko3fcqiMsD/fyfVJCeCqEkwLQvXVmgXxpFONNVT3zcYmBB6wEilUcWYr5rE6MnzVhITMclk
Z20sr3TxYh7KKEODGTsEYTlkX56VAd67oaolM22eUxItF4chze9G55G/oxc54FUFjGIF1RQ3F28P
cIjFlMANX1Xr+sjLLMixpYJzo82tvYqPY/yAYLaDBWMRrXO9Irt8xW9NvzFfZ6ae9WkPk/s3q1Wy
JMUcWguEwD1F1L/4aJ7tHTvDe1eJbHzQ8XPZaXx/1p0zT3sGuZ27yqPPH0rory4efHzNoDI2Hx5K
jPA58D/VUYMSABb2CqI1Zz/K9gwN0KuyoiXcnOslJxkPifjx6/m8PtgKDtsbZNIwTjDy/PmPQ7W0
2ZOx2btTgqQVddxn/rMSamcxp59o9HdveEAstbqL0D6ik9OZS+ycdYHjLZWsf4bkHspZXqn0wRjm
7cYqC8ZDTvvIj2P/gSqPdOF2tZl2M75i19qEUFOz1xip3xXDsHrCKoMNMkvwaofgXirb9a9ZGvS7
o0B2K3zyI4CKFPtK4w40uTVNH8zQXWum5yh048hSTl4E9b+Gj/uj9PfG4CbftG/QAe3V+k1arPQp
9zOMvgDDmGsiSQR0w5iM2bSdQMPwzbt6ykqWj/cPid1kUemR/zXBNdur+gu8/s6BmtkcZCUhuwSM
JzHwDCCM/Dw5sTnngUd1ckRb9PjMEeFZrkpQykQVGzlGOP6kpcZ1O2T9IQG6yxUxAxxE8R/HcUxi
2u7Kmr5wAoymyQ7qV28Bm9xClwLxV7/vX2DhazFL5vRA0yNIz9L3/qMdvycXYO9et6D4/tewmTqN
MTs+m9SYAxqHTofOgovSLs17rM2S6W/Ew672mr+iY0azA99527gK/QEvWH4v5JzOYVJVAjFmaMQU
RAKcKs7ooLg2vIY1WAPa//qUqsw1wejZ5cT7wmWCxQMkydKn15+L/H+caKHM8tKNrmYk452yloJ7
Oloh/zU7AaUKFLJiQRNsgX4JaxfsliFisLgCEKejhsIqxb6ih4blzGGMcXR4YlX3MwVe+Hl0fSpW
z1GB63L/panT25PDR3N+mpZaPLWGsIMIz0C3nyCBjbfJbJ/iqywOkVz9gS0eqdrwvdDoRjSN/iJe
0ZSk0Sml/pfUVQzWRwoY1P9a0hSquEqfDPfmd1po7rxGtJMYYQIcV97+KAc2cSLdCpHCfrgIfOTR
MsFt++UvMq3gJ8N47CV6E/uz1FRWPDGDFCCEIT3wrbBOplc/SF3EtNrDwOYdWAk97vAsUduenZg5
7GkOeBBU1L4n7aAR5lVjZVTA8QdEKFxWYlzNbt6Pm+AJ1s9dDQiYwn3wBhfhJrNcBBGzf+U6kvdU
nVV8y1wBe0z+Is2mTqbDowFls9IgkmGnaF7XtgKnTgDu0XvuHTmsiGb3zoAfKUPXYeLCrVtyKgou
7mida9WkVju2pHV+CC9yvAap2P1RAooDAG6i6//MvhSkGIIiGtHDpUr0pW6UrCdfmdTkVyMWvX7f
jrD1XN50m1RRSoBmsX5MwIB1NHS0AD8O6rzrxiRd18mYHltvGXmJKLcctQ1d2JBLYsVfZBWRVVs2
mz1oX3RtIzY0DHisPLu0wfQRG+8oJrvxJybNn4IORDQ6XZSZr8S2wMeiygMF6HjpK7i0O4MAfUuk
bWJyGxyijZttbe4f+Qc2XX8RBOvDbfrf6XhPt7KfGjP6NYaqQ4iuCi3ztMOFUOlHxwDEvhtCLBjo
ql14RzEYtW6tnk/9OiQqyfBeKm4cbQNUhr9iPzJXfWynz3OKGbfAugYqmoRc/3/yvALkZa/w/ZLf
H2/vHrq3xyWuzZaKKXnQWTs6L/UDs69c5MEuOovCGvlJ1fmyx9gy1u9b1kh2tmVSgwFKgil/yhBS
qya/JmxhclBsM51CknppvbIJnhqh+/hjMsEX0W98u+q841HX1ZJoTqorv7kzojwEonF7Wp2/8oJK
aQcwdJoINUYfU2Au6o2ui03OQoH+adq7/SsH7n0VURLj7h3y7jwLILeGQMDnT0yN8m1nS6KMtLVj
X1vrGooIEU8DcBRCL6hQSt1NBi6xE4U910n0GxvkC6bUNGr2Mev7BdM7y0SZLNqDVSFUKNLpOm2D
AAf7Bv9C7/FD86Ou0werBuyTaCnpUq1EKFGI6R//wYP1hF5b2/BFioo8Vis4XCp3oG+3uq1T+Dov
ZIiwMCIMln9IigCeARYEJBduSbccE0dkf/EuHhlxQsLiKoJTPIwISCEyADp6NtRT3bEk4rJCdcL5
XgXYWAT/+qb73qyuxDD5pAWfK/wcDU/Lm2BzBrUQjL2a1/2wJZ3I+j93DBJdj47Phkfi8E6eNokt
JW+rPDkoetQRQaj9zKcSbJZU6Tt1naNlf937L59NdS8miMWhHY3yMmFDGtlq9H3i8L7QpV/59Q7w
R2RlHkusJujG7rgBvyiB5980doiArET5ljFzriGA+EqGDpRUdg3Oa75fqG6MjsHQhv4iueEAv1Z+
hOFj6v6OAqCsNpzvBy8fZWlXOJUHWYcn5OYTHlM6mjRD2TetvhgavbyTiwvsE+3FJEwZo9hgXWwj
scF48zRXAVZjAuCjICGTlZz43VstuxJa0FfFUhL3j7zJ8tGnnzfOF9Kx1Lh987OoYlTfwIu2grRn
BrNU3SSmDKtAGwKSjNS9Byab8/JhrIjnt1SN4yXhkQed+LNMFQQ4x8OoQ69scuiDxcfvhD2XHtjp
i+KHVRH7HLaS7JWo8iRk18daA4rdQ/UG8LBhoJzj5frsG+mvM3l/zePZGaJeYsM0Xcr7XY2eTWja
4kgcisKrvfTgJS0aJYUcC2Td4vgF+oOSK61clkfnujZw//+habg2or89OV9/FrXnwa2quxb/u3aC
cALiOt8Xk8A60+SfXNP1jj5WpvIPsSdI+8SLJum1wow7h+NE2VeRQnmND6kdLgsILaiJ3wcdCf41
q9S3NFZPcWCS3Qn1feGnHIXkIZKfdCqxx/MVLR1/wnVXOtDmq/84iC7ww5PNwB5UsMsQTA3EPcWP
9xPTj4ha+qRs0EMYqXJ1mIE7bo2MYbS8LI1DQE5eeLjZqPpAWGZgeKSgHfSevPMwtOzr/bE9sS0l
z9EpqXJ1DDzcl4PYC5PvWSWoLdaqilkRQE6EwR/fWOJqMZQvMxOJY3OrLwroMf9vaB1Pj9P3Zqpy
9VPDSg5g2j/BTm8Fk25e1AFYN7X2J9oWPLa2mcDwNSKUkQvvlXbo/R/h1HIzAWhqyTAYwbte+l+P
mS7GFx8otfm86vaHCSHExUXj772OGGpTkytwyL0m+O23Og1kQOEAqEfm4EwQQRlnG2bmTEZz9iD0
2uHmTZ8yKotGQWijQ7IHvhAJovN4iPGt4K1ovmcqW3rd8bzGJRyCqbOGpilJDzjVhDf3PP7k+5Iq
iyTtPZE5QhF68tm8hf8F8LWYAIjdhBj+MHpw7ZYpUqBkby9dmdxR1nTlnDSitxSOlhRWj4nVNCbK
6VYRZUvpBLPZ2eezLwble0R5GdefVnRC6WYtnpZg6BeVOVYvGK/JB1e7MSqLLT7XSyYfHY1BZmVf
TZH/e55bLLK537J0Xh++UobpajQYc0EDeZUI+KHAUkV2CtIN3LBqzHqTCxxxonCoRlLR7P670VYP
SDMSwLAQv9SN8Dm/EhFSKXFgzaUz4bZks3udQTN36aK4lFS6n8gxfoffvtUdqWf1M35K5p0bSfC8
XkePbaL62VmWvj3+gO2ekkSvRvKcPL08uMghCqStyNHn5NTIFY60wWUo0C+NPRaR1n+4j3+zgdx+
a1pCio94ET80GLhVJr0cRUlkYjT0PNNJF762D0OxXSAGXizGjUsrVI3mn+iAkymZBM1BuIEvs/S9
M8IZ+NOGuwSB933KsYDPWDonHE0jZVMBzObtSAzyTrMlk7RaLWksVzOTDE0I9DSyJ+kawdSD5wCd
PvEDrhEbqudMdypKFQE1kZcILWYme1yRiBPaIRc+EBhlkk+kRITnDgsM1j7rMAU3/Ozq3uHVJIlH
6I/4DzB2h3WmztPG7xptM5Q3FxAU4IMujGaegNsbpZvqzlvV6Z/BH4AGTwvagtuUlovau+6A3zVK
+L/w9eLILdUiHmQpc9h2gFsfnFFr2jQdM/49oonofUhLU4h4btO9T3kCNkhD218XNA+/oohW844f
rTkip9nT9skWW9jHJ5mmVTh/n5dnwwu/IV3tmRKGvK0Dw5TdaVDzgckHNxWzG4dUNm04AB7luOnt
yIuNQnhiMuwyhy8haPl7fyQMNrgs4DZ2vXVC7EozZmidGikBVpQjGo1VVa4eHyjhE38NIaEa9KKo
8ujLhfIp5mCbtYBW/BZRHakU5j4MQR8dn3ZpjoskAXIj3dHQ8PVazA9MPehonn2x08zmi/d6Yl6W
lvvzJHsfHRZtDrk5ogdiXqOAjHKTGuvzmNIfTn4guCPIZaBm1fUazFqXEvrzw9W4Cr7JT3gp5sTt
LpkRsDcVvRnsVI0kT5JhmDnPIJ2EwWDcPm5lG2p+oX2MConGE+1u4vgbgyouOZGs6etH48UdomMa
6ReV1h0HtjDNpAoGon+B1WUyGY9p0G80kUPgvuIC7IVmhYMkzqrqb4Hu/jcJdJWgLFJc+JSgvolr
5AhwyJAEaL6wOh/q9drlLrPxRIUnQ5q4i2cQqBEJn/nL4/ptY030yRDFtbt4MMcOrpVr9big+ZCL
jVSKCPbE91xMvBAC67h6bkzftnbYaa8nhUJS1b0elgc3XwO2aE+rD5r2/291zHg9Mx26ZtgegyQy
wXofdIg9HXteMlVGQCB4zEf9iGkylxvoBt3tP9JjD6c3xD4IhVspfO9uUp4uT1q7Bmqf6d0oZ0T/
pPoy96ivJWNhmu/OCRcQeGlOoui/bZxjZ3guRWei/jK4vvgUTzQYCMxciy09u9uiWTOJxqhS9nV0
LLG1+/veZcmQ9KGA1pCd4HI3Vj+FrR8HiCuW3wFDzLxtlaPeQGdRgEn4yVYR6xSVIatx2TZjQ9ch
w3NiLZN6rPA25/j4hNnD+YqlG5dmrFukUq9T9RRpb/np3LiJdcv6vre0oyLwuKlmd5tbDe+dIGn2
NGfCiC7gZ0d1uLmr23E4YxrqcqKvXaFlzn9RzwXReobfPwnkGtKfPEjEIq+eZd+rrgsI9wREvmsu
yxqaf6/XYgkLSz1v1V5Q2StyGCKfm+MpNNUJTEK0EldgE6+lg3t+UUgZGABfBWjDVQmIojZCyB5Q
Dyqv49T0308daVHU7ucz30aQYk/lbIYnqn2eSGoPATuGca+0av5YzL9a6nKOYuJjWcbrJjdGnk8M
jFc9c9Xjef+KHkGV1esoVwuVN3Loa+AU+IMEh4I70+TwtJdzcSe6rsWjxK+nlKnE+HyZEcXEhNCR
yQS1A7qJOEYgvJ4ysWoSaJbF94QY82Zbd7V/IoZWmAZu1lv1OOf2N6/SEgGLK6B6gLxT00QcfMFv
xlsQC5j3MFYM1X3IbCJDqo551n6jCRXWgCRvh8/oA3WqKnRd8RoiJ8wgCzkq2mObZlroeWEuoQLj
ja/m4S89y+nlWKL3yi6a12iUxVYiyrFsUSZ7JJ6dNSUu87h+cPNPJdEG2BUJ5OsibU0y81+By/A+
kRh29z/PE9Z3wIzCBAxXG/7EofEgjpyN7GeA5dxhl3r4sC0eClv1zKYD1VqY0tQ+S5pobJvKVA5n
3qC9tVI1et2fdaUZSE8JW+vJ0Fn8Jaz048liZUXYpRIkhzcBUL9P4vruTsenK+WvafojuDSRUaP0
qEVgazySu/fqd54klC9opAPbCroz0iv5MZia7YcHkiBBzn8c/FnkNYqBRli4DL2BivohysoyWd3K
nZFA+S8mIirT9O31LhoitvcJPYyztX3cvJsAY8QbxnLncIAQqnPurFDtH+4Dcp5By2W8pijgoiLQ
HljodV9hbTvucqPE5dXYpR/GHKRs3BeuEIDkMzSGkRhIcvOmk+CjKiWrH6G8f6ZxH0Br27OyZ7Zj
0W80AOCg52cGKjbTcd87uSNb9AO0reTBnQXO2yJAaXZvlZJKPU1aPXAt2dWR3h1LGwhkoumOu/Nt
7pC+XeraAwfsQKw8neXC4iYEiTN+W3af2lmUZZ+kBIXLOD+jaTpjlNzSHPAEw1eRvRmvCIeqx/Cn
HFYlHxSLDFDa25kLU/w+GxG0kund0Tmm82hc03/M31uZZBobemLSD5dkfNtcKxjNLbR7n9Wv/K//
qvNV1SBLNDC4LGctayvX0y0MdjgGRJLpul5OnQSRqucUtkTRzEdYZJQ3iGKmf/ghOm5KClspdxDX
DaViBqtEJ9HEJA8jBcw9sqjRC9ieWfCVM+MFAWya1ww2LN8cUsGyCvv8OuUjok/rOnOB32ofl9n5
sV6OqGV9O7KacAX0Wa8nazZDOqNh+PK65tMGJXewBtJsm9ljiEOjNmBBqqpvK2wYxisCREeY6JNQ
Sc7B/HAecbwhA2WuK4yWZJqMsyfxDPgsmdA16wEGLChXXbc5jFNNpVEgA7y/YeytXId28QJ/y9E8
2KDfDzr9VjXwbVFVI23Fp7p4zv+pQ6HFtcnDMHyGx9fOMnnmMwN8UQYPZ5QeZBBJYbBXYKV9NOfr
q0hY3c0XuhzkMBqp1Opr5Hg1K3BQvSyTO9DzqFGpbU5gZbrD/OyvO3X06Q9cPi6xGO2cjA20lh/U
H8hgeQad0SgH0+IUAK9fFWEbhPL8uTHxLRe2dCmhMw/GiVJNwFsYlr9b2pRKNgI1XwaVM+U9eCyV
oQYsrDTV7/Upj0w7rTZnc9DJnWmFx5IyV7j9aviqt3kZPOWU/owtEdNGuvxttXQ7LUBaba10bxxK
c/mPNgbb4kNIv+edaEwnlRifji7kkhqHPSccI9WGZQQNgRCPAf61bEeoRaevTlqV3pFVNahZbAk9
tuxxzEVWWC+Hq14RZj9PsIoVFcFvlJQPewY7T4ivTVK94IhwodFfdXr7HrDNtq0mrU6BXgMCw+lv
yUj7njt7g9yfnSZCs1Xo248MwskaSOSE/neo2sN9guzdpA9UbIkVyAOt55KCq6L4lxVXcScCOrNP
0YAlftNJNuJWNWRQkmArYlFsgaibSHgkdppRvFYzka0Wfzc1XgkeT0yphoRz61jJc1pQVgc22aHz
61ZIk95jVkoXoH/x/5y1Wgdx0k45kNXGrY3mxXqoq7gPKPJLA6Gndc6I8Sr8MNo1H5hnLEA88SjA
AKbgIbXgGX1vcs9Ne1Gn2DiPGmdxJBlbhR6bIGXIb0KpF6SSjR0rZFqnrhF+IM+wCPPufmFPvXfV
gKBNE9ujJnW0RsScynj6iEvNzlcL4ywN9PvBlGuN46NiHUbOtdipCzYoAo58HOU2kNR3UD/fb9BB
MwpRR1VzemUApHWVgO6Q4HAzqS0T06SzXXtBjJrSeefbd07PT2zv9A5lM2PxxBXDSO6JoGi1e7c1
1044OwDa8WnktKElQOExnSueLAMRfYVhAEmXqgoqLz/pk59wRWXphHktrB3iGJ9yaEhzno6aCwWC
MeXihadiO6Y1SeZSzSSiNpz53YZuEDuB/khh6TqvC64naSQAoVfdI1WlZoAMcCOjYp4y7gZUMyYI
pCiu3G0F5GN2e2WcUUEnvmPNE4aZTRIpWMIpDYXalaAXnL+fSDTEgyWYBu3prD7FEHEoJM5L9T/z
mhDuU+5cRJLtHv1NCSiwE7MQI0FEZGM3aT+nolVkkOgPXi20XwjebOt9G4MZJ2s7d7m6GcNOsb+I
wLHiDIgSn6QZFVc3f0j8RvTeDAuOT2DBPzQst+oE8dKc4BV4Un59zQ9w5ISWIdtQyjTHKp348mQS
ZIO38jr7CQSLhxYFk1iLol5sSXYouBf5g6TZ+jtBtpdiG1KtkzQzssnH1K3IrTm5oQn3GmsenT/L
hIxqKnq8M15zrnSFljkR1dCebvqJ/8VqPjGhBrQCwKir9wnLCTxxeqE6vP2Cm4SPx9SU4tQuURZt
XM15Tg5hFzJzKGTxC+Z3P94aJuWJeU5H2ZmKEFHecI1jFvbQNRLJmmB6JpQZwTdCx+sr6Clvel0k
TZwsgt8cn/l7B8v3rLE4vxUdLLqURsauMd9+1+9DPynI8aybIqy8DpKqKfcIzFuTxJ9uH9DKKith
jOerqnymx8WaGYR+FZ4miC2zh7gtA9spVoeg9vUryju6TkOZebETDTi6t6er3PYK7tn0+2SJhrxh
zRV8x/LlIStRm9RYI5E1pJKDQWdsL0jsO6bOcC2c1M9FayCYeV4bLYK5aurrF6bGHM6UXK5GuBQz
5aZPgxQs/+HzmNn46Ztxfp6QjZq7kJxEDCJOOb3EM3IQEr3kRJ/nbRPbLAb5li+fiHL7ykGwSX9g
+0awQXOY/Kbr0PNTZ/XRZ/01wBwecGfb6qvwd6UXDaEzLPohestLtIVd9DfbmVYMsQN3fI3EmqoL
8YRd71HnxN5u3AxufjPXwSvedSlcxLe5VCRbi4TvOdlXIhrqPSYKjacTRlaf3GKA7/3pgYqq31wy
VzfkLqlZXix3Pvmw1SG8efrsE5v9oP/83Wi7KixlueJ9b0FeRx90I1xbGGb2i8jfL4W6SuWq9VEZ
SjDe0sXF3nEbORm9vVPhgiyrGhuj3PbPsnmcM2n75vtpyHDVhlE4VpkXX0+7c/ommM7Vi1cdsse9
FiXaQ5mGh+S5sidLZsncdJaEzgBfP6Gfx/b9au2Wl9UuuXNQ00BioyxcLdpmyAoR17XzOlLw/luf
U5xvN5lt7dtM/Wm30XPtucg8yIIGT6mWJy1SDkRUD9LVIvktWbUieLnLoBpajETpZkNzv0w9ZeMY
E7YtatmuzFc2n6KDp2+3iDyjyxTb+9S90Xh1aOrlMe3XqzRljs2ue4zAgEvO+FUrtgP7IBTFObki
VhCFiDwATId/GM6q6f4nPnbcTdg9rw9LF7cO9p6IxPbxjc9OYZvIoxC6VxR3pfOckEe7smOU6jiO
DJOZGjHJpdIeH+lbaVwPIxUdg0n2oRWNqZEYTKw2a5jpp2Jo5BMPOxZupGOPEGvJGD712G4xfROb
V3IyA6BDGlpNmGfgQrAUwfPQg9QYfcNkTBwADtehSvxOlAPz/N1tAHOnnbU4M2msSoQnxRya9woE
wpPC2+EWk4Y6yoPh70lDjY8szu6EGlGEETNqiGtMUT7MvVczQSMyJp/TdBCIIH54+IYh4lonNM5b
PJS2qBN0SnyDdxkuJNFICe4fpVIaEshIUNzPOUC22KpMpJqOKp2Eve1qcV6ZUMBzLEqYAisPluEA
86yerfJkQ5bQurvShSyk7KGOXQjGkID9ByCWUepnNpTBymxfxKkfKEmr5cUi1P9ygwdutf+KkUNd
WV/scTY7dSLGWKSOQpSPuXZ1OUeKcRfFIRibB4hkPueMbm+fLjdv6HYvrVGVrekDqQTnr+pJ0sXm
SBqzyNbHwEhN9Hv2XytPx/0biNrAO0f9307btF3wSyorBHlFm48RHR0+yDjR2+XY2d2t46e0GDV1
0yVRRzVWND8/e5bj13A0fpFCGklMdDOvgOGZ9mYPENxqrt6oJx5OCNVcdqSx95aIrIeksY0KNDLl
bw+m6BMUI0vj07xC72Nyncr5fRODTN4MLV+6s+QyqZclzc9zdG53O4OskDMAhJvH+lXtQk02ck+t
/iK92/2QyWHUjjZumgvnlZhErSrDlAHrIJZgYHpkKiPncx30TBPVf2uvC4K5qOEukTk4UC+bzVqW
zA213sqpQ/4/QDehkkQeZFMQStESgnIZWScSQWcaygPYKJ5osjR4KjMy3nR8r+9S+eRErCyOiHiJ
3VXNm8zQW8tx+2ET3cUb7IklU/H0PibAtXl9WVSDkAUEFxQ9EMlAJ1euABJEADvxSR0337KNvfjn
wjcSa9bWFreUyhNe5GWECW/9lvC7Yd6kbdgSLHMP+55P3eHNnEmPcd9DEW9YiFr5zTvL2arZqOFy
hL6ajOU7I+VlXZYGr1yfIBXcI+viiz4WkQf40ILdRYcRAwXWbSxDX9sdo+IhjJgdhKLGQ/QF8kBZ
ihYaHmjjAmhmKq+3i3udiJ9UtaAWnsurdS1B52et7734TyrOK27e5fL7kKrUQNII+gpGggfBHozl
F6TVn7iFuZ9aLIaJUGfW0OwMTqGaX0A/wkoleWSB4/bnEJmN/OSjGPfeLO6JdZo503M5btI5qBD8
XJlaoGsIeIiPl3VjCIq09Jj0IJd37/uifMOY4834kup+aYjdRYxQkwj3KN2/D2Gx8Wwpwx83qr2F
AmOjP4bxPhK/tIufZ3a8DSlPem7jMJkRghqt61YeEjg5bfOYtcaWvpOeqkZEBUzbxDACvlyrLfqR
xfXZDlPx4PJJU7ETC8Jr0PX4mry7tpSs5Jgj3v1AcRiwshpKEmYhRhdsMUpuzCCZ8CCjdAE8eaAQ
G7YdgMdUf1Onoywdk47G7wyASGbyZXZmNrl5BBAcVS8MTcvBPdyGUx0J7mHtUYraWxL1MUwvVDT7
o7A9Ov8RecDuZqSysXxz5b51bcvx655aZBeT1BAeoB/OuHgd5dgag5Elrj9H0p6nL37g+HaaXjoc
su8/OjEtLFZ9biu1Ng2CvelmaofOw2uqUP7H0D4wif9kvCQp/lY0WTLddW4UavnqCxekjCiVuYd0
dx+CoTL6DNTFdMOcKZVFJH9ggAnFX6w6d+EfOKYbPKXXRK6R/fHjqNaEuHI5foHu8vBj/imMZf7a
s8KudHE0thX45piL+TXEOOghInlgSl9hIAjUDbGFAg6NgBbOrL75DQybnadpj45pwIM4YTMGCHyM
1t34fn2CP4mvcWiIFxz4tVbibV8jkLksO1oh4VzAbe6yC2/cYX037OinWAziW02stgyKuf32UHOV
lDUVOIqzsgVcAcAzyNu4VSBRZWWV6NlvQzydN1mVDCZZbl3EnlAPWr4mW/4lwesDfe4KzliaurQA
af0XwdOzTNrYiUW5JwJFjDFNSji59nJPpFK7rpmbNGOxsIMtcz16u7BhW1xGDDWyiu1wm3tah2sK
BadSQVnAAtn4Eqy7eDWjc0aPEDrF7bBikvbTjmnkN/OvscBdyqkdepU5TS6viN1fS5VYL5NxrmAe
ySFaxYaXXkEJiEE34SeMCZE8iPspjGbQaV9JAjeqRrv6uPZc0nAlLwuewfNhmN7AwTGkC0QXwKGD
geidIZ+YxCojVBhcuYic7juj+DfIXVRp/IpQ2RtCXJrCqjxs73xV14G33njFfctJB6w63+7G8tfX
hPqedMu40mFKURSvriPXrPAGu2zOqAaItxBCWjUoRbpzn+7Q+VIX2Y+AT4w6GwH9fuHT2DKgxCoA
5Ll0HOzJiJCjj/mZj3TT5j3+ZLKh9t4J8DtXUCJA/xBa+0CMwSnrQPVILAudgB4rQkdgCyeocPIp
6gg+UJj75Jij6gOBpkuEGE3zAonYXV01fGEfO6ow/20Gr5xn8EhZxdYKzBAH18NB0d/ezixOedXY
ZXffkhrd7gKlLOYAh1Uva2AI5g2c+Eig+onCtjb5e8cySS5iqssc0shiQsd/8WCtg7tFVnlxAhk2
BJjoUo3vZXlLrTS2O9gPsaRrEiq+MhlCJQIn3xzXH0EP6Q0/2tHh1aR2r5kruAvRda8nP+vYQinn
F0n2NdMYC7ig0f8O5kgi3OMSrothNdG/8UHpXCPfeKI8wOQ1b1yyKIjzT/aOH42NoAeCqnmD1OuS
IxLLcsY8+v2AbTPyJoAmp5gGaXksWlGdOOBgJpVNT+75ardU6zj2rbNxJ2LBHgNtrCczrFX5lv2A
it3WOETwhutkixfN2APW/N5hf00UyCpeMFmQY6mIqSbGXNSasHQ1dKAEogTTh4cFPI95zryisTXR
25xRSK/td9GSQzyKfjE0sumSEZaqAktb5VpuiGRx9lL/emo4Nks99FVj2O024F/acdTTqTDn8Cxt
BO5pteJlmIX+AieaBs/4d4U92kUiX9JWeX8d0M6HDLHgbqOLEt8ZLkHOW8EpNTGChAv/1N0zWHiV
ZS6a0h++2Mt+7WMfkfjrw2YyHKwObP+9e1br6NY5zoMf/6CJdL10EwVYo93mKQGNyCmvjKA/HxVo
qSrzTyIyo0XW+Rt/kcDrJvuf1F0eyBLDcq8fppOLJqx2RMkW30UGrIZ84K4o02KkYhRWmFs2iFmx
wHO8jpu4IrIceojidqNBd+SGZFeNYYmkONpiiz27b6AuDB3J2dtJdTK1TWdOUOCqGq7k8DC1BXib
WEWBmh1LuwB3uBxBVhEm0UV5ud8iakAGKzAV+WixTgslpBQr14eyg290JNXXjGCH9koiVOmKafD+
enxGLg4mKmM8HeldlyW/rXawsoR6uQa8dKbgsJLb0coDLpUSPYn7eFYU3xLthStCPFAWa3Iho1xG
9ZWTBv9Cdx6nqT6R2Hr05yWZxgzyAh3GW5P9GPRpdCY3q3J9wAtVFy/XGKP0kLS6MVs0ppPEGMDI
2wrkeKf5jWaV2RH+76zOUbkax8fXLT2+EIcQKF6a8TQiaU1EFyEHNYtHDu9ivK6lYVCM9+oJgwBv
nnBnhttWv7iygUxQyMHh3DzGYVVxVIZCt4LSdg2psZR0rOLUikv8jF02gVm87I2AgdxQgOtuEIqz
vtdZuIXR2ke09hslfuunq3FrvP2EdPu8T+7j5kUi6x9QeC6ev4h2sIcLaLJAY/Le//pcb8lhYp9L
9DoKsBMWOhjvH61+Ma5M8pe//BUdTfsS/vvyQ5mBuV3COgaciy8iNzPF7VF/YLXnZ2xO74ddBp2k
fC0h/kesb+rAdg8RN1bqfbmGNkgVJbS8kI0noHH8mRdp47SvgYzYL87+jtmZ8f414+/TPdQYLJwD
qSoCYJ9SmGLm8dqsg8Gs71+89i9kR8ID7UJe8yo53mmKoK5oJnxoObk3yjyxZzVBofo90+pv+DYH
kRtYXBrtKOAqTdwJQXb4CJgZQLgez1Ghb/zPGTVIb3tMui0o4v8Ik9OPvZL9dP2QqZpocELu60HZ
YEtfDlGdLQAiKYYvpPzbj274rKdaeaj8e2J6vbR9HLbHhAQL1P1EPff6Dq4G1VlPx+mGS3NhGLwA
sGPtfM/pPGzmjvQ8Yxtvy6rXrOp50U0VspFqHf6oqSdNbMreowAFdl6I99S3CoFDWnyd8wB9Lqqo
7bj5MIO7h7bMRbNG+00uBtkF5DLONspMgo0c9dCUzq4VTkMVwq6Uq9L/h+NX/HRG1HWpH4zVT25e
DMZgLY86eC3OOCpcXwxIn3ttZjud8EZAvt65yahr9+fV2OLywTb8ytJU/Mr7cZYZWf/L2l7tO4K1
qVsTq4K5pyYHu7GzPOcYWN0qMrGMfILRJ9iNO3IGlWVcgdYD66OgKbqt3G9u3NdgGbBURZYS7m7q
iUymc7p7YNO1zOvicuvprWmHGRV6U75A8Ozlz5Vm9FUYAZkyWr8+cKQCPnQLzKwDFB/cUxa3lLmG
rToe/o8Tqj5tZ/tKRvSsjCqS6COb295XaKxi9ClaitWeJfnm1u88M5Mg0nyj3kFSUOEV/shuf1rm
EMNGVtS9bW54mB85YO8WAlox/vUx6ElQhs4E/OqOJShk9BNFdC+zHeT+lgFSbpkzaGP5La10c6ml
/t5aAu4SysIKAqtz3tLKU1qLv3nlGlhFo3jYPwDoy0gdWHexFbHvuc9k36/MlG4VWZdVRWlcW2JM
aEgHGJNGec86tWx6xDQPg3z5ipiroyh1iuCeaKSC9J9pLW2zLKgJ1XiPdW3V9lB0BZPXvTro6qR4
wBpNqw/vkK+uQ6kGtBuzOUzBpXfsbJulALkhRj9WA4+c8D4nZ1Q84Cn2jQmBE9L8F0kIBMkerfgT
+Xqsxvv1VeHEdNv87BvqMLyZxF2kaNWa0v3e93gGMMbZ9AQ5y6/W6cAZUb1lVxhKo6kUUPORLFO1
Cpg8aPFJN65TSDA8Lc3aCEre5bTrwHVuJyIunt2E+WPGD6Y7pLm0im0itYulIaKOo/7EHEQbjCY/
9uP/3YsnjazdCPshPsssvuw8q9dmIArUf37UEDYciacCybBwUBuvviNxLA0JAI2VmG+E62y2vmrL
XeksNFD3PVb4VqVDrYxkYbDds3EV7dNImtFtxgPMecR1h+bOc/NqAJhh1dGOIRFwPXHuRE0N4XUN
1GDkvFiKMIGMwHFpmz7CLqyABy+KkZjS47ySEqudO/Ax/nELI5EyXysQawDeUPdJRERApJUq/UpA
76TXSVowl+WOuWssj839qU5aP9wGwJZTN3FJOCAO539TVOE+IaNTQ45gLc7QawKDrhv7wajz34RP
PxPEXqkSdVnwutQWIhmGYUNom5hByO9TRpwn951z8h+XBRA7xZjvYwm3J+s3tjmVVCFbRUFXFMiv
oW3LDN+my4DuEXXlv4lwD84KhO8uioZs4w5Fho+LbSO7uCH5C2Ee5y+Ih5A3LpEIIsR0PpqhtDWr
jedywnEewURg5sg0BoS918gBbjXNbN9EjABbxmB4isrQaeMTAC9Z0PPX0MM44KEeKEqLWfwFHLZa
iC1QPeHjornAyZCRdUeusNXnk27DzJFgCgtttALHpE7bZg+QWdpt+0hA+5Ylwp5c6Ixzhy3TyDNq
bIkGfymfOAj4NkmO70RjHu9XYc1eQqKqsLhtBWdnIyYpMyVL6Cvravi5olOUTk2nRF/NHKc+T53e
jcEHBsJIaIfM25OEYhOlAxp+nDt1O2KIrn4PcmtiZktAXh0WYlXrPqB9e6DiEtasG1Hh9KSfP1Oq
qAhJTweuBC+Hj6gCffIcC4D9+L713gVSAotr0gojUfBhIoRpQUpfZiiGrG6aEdiGjXT/J9msaJcG
Vnde90Z1mGGEonJT9aR79/KqGdrp7D2YgoE9CspYA2gxplMALNOmyTrO/V1inWfWTKvxgd4+3Z4T
VlstRLS8fDo7KnJYjNF0DyH/GiEnx/EWet4yefgu8I1ucq0M/oifXJ2bbBfCtmdMKLjklPjNTEqC
uPHrWZJEWZs+eXRF/sGIbsLZHvm40uH6nhaL9+3S4zGl5u0FtvZcYp2aruh1J1SBfEs/k7pu70qx
c5AlZkQ84flmbDjMq6I+70+1QQcx0Tuo+4lHI7H21YXmdVBpvl8zeh5Jb3K4AmdYtbb7h8GsRKWH
MQcrrWG47ZuDAN5CvcTXPMGRV41t27pVdu7NRodonuWawnJ9FUK/Al5cKiN7sYZaADC5KsQ27lOz
F6QWa0yLRmcXjFkRDx/9Re5kkG8F0UyHZy6yMRQAoZiMju4wWVPqvTF8P7neoEQNCn5+grsO7s+t
xnW7dju3qCkPlyBi1p/B8qvFU+mj03ToW7YkOoDwFYGp1NvxfYGEst4YhvLh9A261a7GJYVUN+kd
5WgzjXgLr2LpfKM1mSsyrOK469kenRY+YAQTCJ7Naua/lrG6sBjRnR0gtGZnqBoR5MvUFNMDvq2O
ywdDRfI0aJ2VRo+FDt2xl8dgKqoHmZzNlW6hc47PrwW3pdJw1V+GuXpqlIm2C8nmCJicAeqSgbaL
B7k3qv0uvWYeqqq4AxzOEaR8Zyvu0jO+8gc+QmwdN0D67evK9/Nh8Xivy0Rp4jldoZopyU+Iw9aD
uMVElJUhJOh+BWFCNmpngeInk3ZedhYK5ls8EW/ekeCooSqGGJH0uQRixygmC/ihfo+vm206fLY9
ZQzuH4OkR+hq4R0CPtHso7izbr7tX+O3wrRdWp4b77HQEagHxyB75If4BNGzWCJeJbzB3NNZv70W
gw9856eAMieVdfjl5yB7MVw0yPVCW+4dB2ikkgdVYwDD/+YUiBsGvSYVB6JYIQH5CK4O0ObM0iHW
qMrHADhrst+DrauMWKBUQMY78fr45RELqTFGYkv4IgylvKWUFScPseqT+b8ljRppFEuCui2Nnndu
PEb0LYO13gVKiUvNp5D0++Veu5lPSrDg2V8Pt1qpSed8Dw6B+JjPNlnQFHzFD0zQZCb8eDCYkYIh
MK8qnhWL1mUt5lzMRWUW7JUgwxnMnzN0NTgehKLdw7g8F9nDthRIa7461Ieq5dgiMDleej4lpkiC
p88yrLBXeKrCbAxIqm40b72q7zvtai46IBhe+FVXwAgo9TyVfOWZvkSl5rrEhq0ozi0y3gPTTyKR
fwLhmmUU3gWJhq2tKRgwBKhSSEWDe5oomoogQDD5FawBihAHJTS4yd2lwBcABM2IMdmR/QouHqei
WUZEyjjDUvaaL2PIKLAE1ZN4yGnCvWcWLcT/8Smy5j6B3RZAF0QOl8HjAvkMb1yAbfwVdajKBHci
Qu19bY/iNjclKRq8qRTp1PB2H7PVOse+scpwpscg+a4PKHUV2DtszV4Y+ImP6C4rK5BfNmNTnZQ4
iJ7suc7tK+AyZX1VP2H09sHjJWVX1yAoROiCRTJXfrCBub4nVxn931sjEn3+1VquTU/kaULNcnT3
T9PequGCK4KeN8EcNSL7+NPmoGTfoOM+JabTmEVrqBer8f/IC2JTubsEvDpqkmY4lzSfR/EvQZjj
pqP9C/MQH/JYU7w0dRhjGmkabqUlwQXrfDqTHXpshpMKWy1QZT7F0aXN4YfR3vBmags/ffAdv7kY
0JAK3N/6JVENfNwG1AA2982pvXGOmMptRcw6+y3u7kSrT7ePuZyy8F/qKuZwkLFrUgnx9IRQVPsL
QsevgsuRql6VPN84RPmZhPw3hHmnC5RrvfyNmaSbkxdbwyBJ1FSPftD9D2FHq1u4Z331Dy7oMF5r
YPSeSiXvBD67pHcQ5tU0Jb5QUZ7veZkxPSFL3xw+RyCniZZeAoF8wLwMDKkQTH/pAyOilDPMP0ky
x3EV/5NtgbWEB27y/gilAYrG5oWH99ZJU7y0IF/FaD13PQjz+WY5bq6Fb5iePvIckOJDQtzaZ72X
ImWa5++IjmhMIqTudQrWKJ+p5BoEGGeWc335bf/T2nNwWqgzTJ5DBC+e+QyxZb0c5cNOJ9Noa657
YRNJoMt1SZNeaYvLXSO1OK81w4m2melGs5zg6xugF5Z+s7SFCd8lBV/45+Ht9Gk4tZFbtwMnsICz
9B3T8hSfMvXoI0SaoqbTFnysxf8r6b/2D4hDRCpBcqf0qK8dH2FW5nFmss+qwOitqthKuMS4oJMP
jmkufASG3F0YKtudzhYKMoYvgTqN4PTE75Pr9nd5xDW+7TBTmqREyCrBAZHxizsVzAgoQQJgSHn7
aJDSF8dVYoGhqHwI4JoV7/IRubUnnkhsIzPsGe5J0oRrYUJeFSFRgyXPZaVn5YIEUzISrItKyvMP
al+hyc4UG2Byuddg4ryFfByDMC/9pJ22XeH51cmhCjolotxLjzt+LMtaqZ/A3MwAw3uoStscN+Na
wqKor7GuyshEukemD3wXr+xn5NezmO6sxsLCqAD8FIjIrH77uT3uH9/bR4qZMaBpkqh0RhLjoUpT
K1vzQvWVyP/xZwTwfemu41cqX42FzZnD11etrec/tvgwwmp9tBwDO+cfSqbcxtzIKXaWddv9aXnz
jVfAvMWGQ4+rqAjmz09Q9zB8eWdRCLK61VZXntspZc/iM1h7jzVVo/Dcxwt+Yuo5LqfI4/+E9gDB
AkPhaqXjeV07GYBY5io6kchVCeTjng6FqNqpJS3dhQvBIr5V43EYXBxW/TlD4KGqJaDQg0PNI151
r8h9B/Z7lGbKtpziB9MHLnw/OX0+5HErhTdxCq96WMHAt/vwZ7DYlG+HCS9hzsMGoUHLuVh6Yasx
/3vmOQdmYbZTflfwMxXUHowYOAzNa7MHVTBCyVm84Xi/cxAaoUNiGdfsxC+I04FQP8GHYtN0Xs41
k5wOsGRjjlR7u59sJNKz2kLdHPKBNfULD2hrZW8i5rui3kmhmK6AbViQPEwFcYZaUElh9JU0Rt78
Z5RxHhckxWdxjqRyx0ZjRye7Q3meKYt+E42JBMZoLymro/9G2Vkr3g2K9U1DdYEfeHW/aaGNdK4g
Nps6xmpRTEK4NblNxrVlrwPHjnHB1o2cnuyWzS7h7Hbt4BoIni3NjPhK6aAcDn3HlHO1lIew3p+6
SVqV9nEazL1mlfXExtCpuBpNuutUEjvZKrePxLzJ0/SXUzu59L7BegZLvp6oCE/daCkO0cQPDGaa
EQc/Cf75ZhMpQGWihLIBaoCYAQBCTPpTeWGsZzb4mBMrHJr/xdI3uZ8fnCZ/uP/bdrhARDQx+AoP
vBZi0aWQshqQT+eJJa3ypURfW3wvTiaULPVRdcUaMSO74eqNU3rY2ABLPYZIV/tTUwKxfz4uZfNk
RSjroe0QxcMC+WK+1iI68PhLuw8BHbs5+RV33X552qKUU4s+gkmw028r2m/CJDuffE9TPUQGJ+wA
AUUXs8T6xA/IahYjmOxDvbJkzBD46Qqj9oTNl4ImoKxd+iSvWfTyqxTPEA2r1IK/riktBRmouTXa
cO6dOnsM1hyZZ5zVIVKBXo1RVK0KUBgCxWMJPRHJZBc62FHcD7rWgyr4VQ8zvS1CayozKxV3rpvR
rySd+5qske7fI+38kCf0c+O2IXLdL16pnOvCyy4OJvLLFAVa0nxCFz3nqImn4+fIEP4zvZPpaA1T
DTRGKUZNdQ9OXcczL8OBfBf4IXRbpvc7d8URA8dkvu7s/k1eS9dWDAKc78j66Hrf4mMYxLhF0v0K
zJ08f3Yl0BTxIbZTlBDy2k45vVq6MRF1xe5ocP02a9OHIyTGnPWcv+OTYtbNsXUz9k2pCqSNW9V5
CTgLYho8dLko1hwAnTjqrFmURNqhtwSr439IkXBqU2/gGRqrvmoetex1bQuZvqd/SXqGmNffekFR
Dr1X085hmPChcNgkxTw5TfKNBx9x5upB0wmdpwT6wAtu4aAE6+oK/tUntoYekXVIBS99TrCvk1GY
fj/aZPthzpNIjkH5R3JGXhhC9FL9Jw8Rwg2KCtWH9XO7CiORbvfEgTUK8ueb1GVgKs3ngz6nmxfV
0yo2ixA8hpYJbSryqph7c+nVIT0vYgUgnKsT1+eyGb2zEq2ujL73YmrV18Y0BNXZzgQ+G8VaNfD3
RpgyUv9yllAVJVRhJg5tUYEAfp7+0yyrEodOGrFFlmKtI2vhVbBoJytJYnTZr4U4+i8e5mSrMBLf
6uPsZip/uS6bZSkvShFGtvgDKjU5DifXaYc5STXJDysS6BCdwdlEZlTf9JsSCOwX/IyOmM4kYaH/
N3aUMCZQVv3zy1u1a4XrUrOmJL+fdTBJL9/RlI3DksFnT9OTRsX8B953k4Iy5cNkD+G5hZGv8487
sFoms36TziNekGFdWJahe1k2AT3b8Tq/cMW5UpAKGe1vOAXh5G5mdFnpjq1I3SUnitctrQn9D7+p
XY+nr1KlcAKQw3KuIh/an6yjKiBp+RcVWN3MrfyFJkt6oUTgcccSMjL9i/eaM9L0Ebargd48fQia
MHY8yxJ3+s1nuFLC5FuI9LDiW9cecNvn/pHxpgXUze3oa+mxYdZO3mMNBAzDQgSIc+KMg0GgIzKu
73/IkM32L9Ks2uGkYwFcFeWS/yQOBl7KFXcMOE9QonM13NPk5RVdDrgjpkGrAXn9ceuDNsrH6LQX
3rpzwVlzx15tljTJrsqlqGCEkiDyBnQixlVme5CgplxyAk56ZZrqCrCd27ptVjWcqlfquM72R8uI
R/y8dcTkMxdw5l/jpub94+UBTNcJ0STTHc7NhyZV5sFXsfsRINyh4j3jAU/bne00NLn78DiPDmk7
G4NiBl8D2s44TxzLmE87qC9Wypsbum/LyZMHzkWtoj8gTahCmu78x8KR7TovebtmAaJ5QzUlAqrT
vj7bZW3hS4xARChTHWZcYgBEgg2jlV6CpgrNDbBRRwE/xtKySW8YYc1Z6gR5Fm3eHcT106cZcAyz
uydRJ3tYB0F8LFveT8FF6/k2o50bUw4t1gld5nqMY8j3bkv1lPIKzeLBJDQ3q9T6ymiBdV0ET7FO
vVFhuOzcNQQRQKYvjKjWhL0GwLvKOXDT3aRp/hugZQwGXlABzovmcSbL/A58cE34yi99agXJ1CNH
IZPeH9XppCfLPQYg032lGQ4GXG6qLYlt/1C9vlkqV4dHtJcHeJSZ6+mYfIzugfUGx6cYmPuR7YwV
LzL2VfJWFnbxNQu+rKkhwGMx5ou570W7IsgAvXC2q2jVlD3D+X/1wvXIQW9KQXYTg0ftzbpUMRCI
YExPZmbVuTPKnOY8MEIHcf1NhUuYmV2P+JGFm73cW7aqYZU2U7aU+1K7ANX1gW2NPpymwqyfRA9S
gKl94Rd/irOsFsozs8givbKmeSEuidYwBbh3gGIGDYDPeiUOTgE+joz0650oD16PSGvrc0t+eUUL
xYKvO1PeRZ24BokUZLdbLpKeYOgrZviIsZz87QHi3nkj29r9DJEFDIs60r7YWdFeNyX3RR+0Jhdo
lzjjP2oUd5+Veo/6e+Ww2SQJfW/7E+16AWyTmwIJleIHR4VTnDkfuCA3D93oasl66vXyGHyUcuWE
V3iF27yFsOgNsLUsuDUPG+8TBbG64yoSimunCBZtwLn/6pezHmAPB7EBFgZTC0d9qjqrTrsUrGzp
KaL6WEfF8iNaDg+avl1iLpCVWdcNIZA/FwLw3h/Ge+wthoZPYslrNRKfwU6TJaEvUKiAgiiq3Vzx
FXy6+zUXoedXEmmqMtD/bj/9PeDqfLJGHq2eS+e5uaGkZbBABVLsMox+pnvK9qy0FQxZ1VBjD4C+
LHIlBSDGgaXjmvflUOYwyPF7cQl2wRDnUJ491v+gaRmQiV5fvssTvHSJdEjad1F6om1/HUIOBN23
baJNYGbWYJ9gFLqpV2wKnJkjAZwH5ACXjoKKMeDRQTx+/SBICj9i4SjD68f/D03Lu2Z5kZSBc9Pn
YGMAnrBEdaw0WFFWmhg7nHxWkdSgKzejkbHK9bu8Kt9c6G5S/s3z8vXA11iGoWEC0Hk8KDh//gXG
0O5r8UhQRfskGMO8w/R5O2OcDy6D5QbAeo5ytREGLc3HLooO/ASlZs67XctQ1gjXBl9GgkEkJJbL
X86mNi87fveWo1UKo+8u64UdbPEVGQXYk1EjKni/op2Nr/BtDkoHezNhWLDFCTEwL9O3E6kRoVZb
g7tUU++eSmMrpUBqnjqFvkmrB6qzmbl0oCEj/aUDYG1FhhZ5MUGAEpTVeLB/5vkL5ph7P9vV2Rgv
X70IhjygNgE+616m23TcUytDeenid0UHaHRFP0OPfF+FagvH13fxQbANZ/h0JZo9WzhDTetdGaQu
Ln6wTWu6xVTCZaawCLX1q48N6NSOhNSOULDQw/DbPu4jJ1g6PAuI2afyhnORILG5MpQokKl/T9Ox
AMIaYEWBzSqgd0pF/qacrxCbYtArmD+qXd8JeE1wd7ktSoKjuYV7ljUrqgpE/VVJcg9EcznPLV/r
Z+eBKZ1uQpfC0CHTiojv5NN5urJ4NmNbPMEKhVeaxAXa5NvyzMcTYGoBiydO0B0Gdv7lAo6fylPB
3SuHkb/MpCEdRp7K6vMimGFYM/p7CkK2P5wZK0AjQOxW4dO98bI9bVd9Pp/Kt3/tpy8u6uaniJ4m
l4I2DJatKOVN+BkM8w4cFhMcufcfK1gTk7+EwDw5SkBd6H+nW7XPsj2MjSK2rCzH8h5fmxr7ZhUF
gWM5LAnJsEQfw0yle/C+dusTe7p8xBzX0SHUIEwAiZH0nXrVNaXuYbEW8OxCeYlmvYfR5rZaXbX7
FneQX3xExRCA5NhJHhgpOvN77eR+t5OCOfXeqUPnVJOmj0uKt/xz7AZ8YVPt+zjdJPgQZHqE7qb1
KSA3v/rrgttBp6ljPf/n5rjI5Q1Gq/XUhV5w3VUl+Bqrq4e8eaPz3oZO6BBKPFOvZqe4UKZmvjKX
Pqdz/+3TrsYObPi/+MepSxD/EdPHLENCGWNWrt/Ba0uuPioQlmk+vsEV64h0JFs6ZXSV+3ha8W8F
DtVQ14IxpwbkTTlDWsJVWA9V9E2AJHyj43PDnG0Y7N0ESiwIwU4nXnk+hqTz4qsnaFxCoiXVHYEC
CiQbZVe2cEB2hf5gKbEyBM659lfWz8Skd4KPxF2LHSo8J7ssjZcUiu66UGR9xaTLk4R5zOntWZkt
c+LfU+ffCHEpUG1ne1HsjdfjgkPdkwdTsX4yQCiM4SFdK/eta9T1bwRRTVjibA9lYHGUmwibIFQD
g8ghlA+SBsr/YhvArgwPPk5lJvRzmxCDzjhyIHHiHRBgD8T2BgkYmTf2NQWcC0p3ISOWcQZNjGhc
uf++hN+1EBEm6tXPXSLWXZcpWBsqZTtVWqu9BiEoy6K/86QxzA8wNVxT286e+5x6Nt3LtwLf/L81
/rTnTd1rHVfPs2Q85d9m05+Hr0ZceZfUbsZzdoi9Mzsaow1zQFJLGT/D35q0tqbEK/FZaJFbFR4N
M7YFpLPy0VMD0jHkLg4OUTMkSW3HCPW0Bt8Hjz+gzjygtEVffImJglHctPJqHDFLMjypDCB7K7fc
PdOnyxKNbSOYCX/Fkr09gl7KPxNtb81NFGyQtiuEfpyHMAaD6y9f8oPMqtU3AWT50Y9qxlgaVUhg
+pNc3tTBE7oHXfhq3kp+xwBGJ9UKXOp9jPIrMgoOx9LItkbvL1+4GnQrvXbTPoSZ1bV2eW4njDCK
sQk4JlQjPKMwNGFGPAUssbaWvRdEE5tlHd4X0dfmTYWRhdNhG1y+XOBUyOCd81AbR8//W23oIHd7
ZYBUgkcwEUj/psGyXN+hw76opZW76UvKJXJnyEFzcpzjeUmxny/6H63cAT/qObI/T60loXNdDFN5
EoxKAILw3DCNxjZ5/T2myUQxHQ+Inasdft7rXfvrayQ9064skYQfQFyS2Wc23lrX9kEGI/8IdY1K
Sr8QVQC18UzYZh5/TeMTCPANGhSGedjjVIYuXKfe4IV5gmRx0V0X23fYv/6961pp2WzqRFG3swMT
WT3FIjh2woIRM1sdO1Tk3GE8F3iAwide9anH9ULa46pKKOTQLVP/6nMK8krzjQSq78L0uhx8g2jf
avB3lFh5Jb/ROP5OQZOlii5CreioQLRCPOW2kb84AGT5Op+0nPONCMjnbEYTqrnBejlGjJixgM2A
DhJuW3NLjkwl+URH0TlXW4LYjg4uRVG/NFmuPSb8e/SL8ckN++3TD2odyPS/puSHnZ7ONHW1wl+g
MFrNcCw9HKLQ2dO9gPfODPZYbB8sZQR83D8tIGuPEyhAnA+ZSjZzjW6h2n9MWb0R+5hTfk0JlpCD
fEcXBaIqkAa8Q3wbQm2N034hgLJYzCDOTuI32RBDCfrMJtyUzLtjhszbThpqs1IIXW0nkLWgaJhU
EghgQOJ9AKW1V68H1fWahIr110eJba6nNb58YeiVcE0QEm/UxrbQ7h/StxcTF6+eOmWls73gvyaF
CapUTTVtPldayOreWSo3E2rbMey8+2BjRZah2txPcVDEJZKGVLoiGvprjKZzpocb3nQKlcB86+GX
PzZWAYiTSyrzcOg2uNh261fpxF+cjqBi+J8EOLLd2Zsn5W/ABFhDXIFyQLY2lBDXH+2KG9z7/vqo
jBnYdCVRuH48DGlcxvDyFloYMo7LXsabWvO+jd6rptzGHTHhp0mSQ7G966leJsfwWTw9dGnoiHu3
4E5LJ25d+WsLlmGuB9hFoY5sH+XadBxFwAxyJqZ0UEBQdq1+LN86/SdSy/BeJEFygBsGbNjO0ftX
XgmKjyLgcQs0vRO4pWC+rgADv1h/3WPvyanBzsTDpUhduydEJ4Y7Z0JVEJSSjb3YnV77i7/tQ+NJ
bqimwUuXSqZbfXmhsrRYXkog7i6PYy0i6L399JQWCYoRy8OhZEDs05CfqzMQU5SeGD8su1pUWCvy
V3Dpnwu4tyOqVimPdyqGxBo9jqwE956+eB588Nkt8o7H6j/rzpk69lktTc9dC7aRj0oOvfmIs83r
ZaWBmJ8PmH62HSA6b9AsrnK/EPod4+ZRO2YJb+FWkLk30fs9vSrDny8kRk43LBFSyph6mE4uohAH
wMCv4mIehldaVCWpZRkzk66BG57m4+0h7J5IQ/CqmT/BPfucdgrMZF0cLVL/efyl03IyZPGcnm96
ARt0w4B7Ou8qI5D1gZoj7i6gB9Q4Fq+QnmAAGC5DPUYWZJDN0k6nlXiuwXIR5U9NRrupwIr6oKaf
lgcyO9z4DqqdNqd2uz2YsIKW2aPk5Fpx1n3OkyCh5joTR/EsjCecr6DXU4ULi1d7LIaLslADcvi1
qH2KuM8h0YgyG0tN5gTv+IMTY9ZkAowQeFTxOYS2Hv8c6QJYF97MJxLDVB5IN7PkKbeIE1sTRgM1
iI3ZDKA+m5hCPSrAFs7oPaApFTeG5WXu3cO0hiGaOHQRK86aVB6+yS+463jmYq0+pAM0n7zIMe1Z
e/EZmJ8AgXQTpZ/Kw+EuvbxW+Crs8BmFMvfMa6laAlQYRkL82ANl6tcsJ7ZtqF2Ve5nNvDQW+xMt
z+fk6Ovu7eV9PlgGpRzXaJNAP2iK6nyIgzANJ8QojFNszVUvUe//B+lXHxC8NSO9TkBmpFjgc+No
XMeg1DqwPIZgHzkQSGhdER3gZNsF0uk6Go3LHINXUudNrtg9VTisxVhf1w6ZDwzYpyUlOhZzupMz
bhhirQXG9FtG33kr7YLtvQTwgfeW5s3Kx+pzCAHeH6gCFitYGy4vqNR1QjS4gv6nJQ90UifevJzC
TtYY8qPKzNimF0e3dqlIWNq6W2DewQrui/AdEpubJrKwnYrwIyEnAC+XdKPBidVrI6COjYXc6f7X
1plwc5QQgjWkJIbHTP8eF6gvMmVHeeUjGRRrWUpUG53+gP3D8J4elhyy3EqMbCdg1P5wncSH+y9F
TdwVIAUqZs+PhqARgjIODFybLbjXYQrPbhsM6dlVadRb5gmx0s+PLzftKb/12PdmZdTfGsdIoXea
ukfyfFIBUUP0meUnedgbc0iPF60LyaYaxfNmhh5J151HL9TxrBl7fO4t0z4VZc4EzpO+NV9GoBK9
5NEJnyj/WzQXlphqS/XjXdpqb4letGkspfeD3MBasBzWYGqNNoVtDJubp4I3HbWo4G3O/EdOW0Yw
SgmKR30zeYz/ZMMkuPqnRiv/cRfRsZGeWot1Zv307kfB5D8e10kXYa3G21m2R7Z+x7MCNl5wTVy5
l4dhqny0v3M5BMW8Fs/3GP08UHF9GtLoKN3DXnbRo0bzqPQhLIi5OqvQ76B7MzFSThBgbVygaOQ/
ZErrG8XVSry448bdzgSaH0Ca+6L8EIjYE1K2CmEHtK27jzjeLJmhZ+wPQUlaUKONpYSZUZs+DE0N
yM9j3cT+Ub2erp3AA3/Qp5nFycTpJHkHdf9Tz9hnrC9LRZq8mlNOBMSoruxhbKdihaghYS6GmVpQ
+r3b1YKpYFPvytceZRaiCWuhJce+LUP3DU79W9MjSEXKPwFKKzn+d3MYGGLtKFmEcLQ0wgpYf7Es
SVc/UvKa0AnFcMtIAK7w1L2dsFlz78yKyQ/Db63Wuc7iGpzvqZ2ED2Pwp3yFRFnbyCWyrXGqKh2e
2L2BdFvNcwW+6TNJBLA2246ndf5PULqrxw+0R22B3bdiMpF2glRqYz52EhjGm6DbsIyRx5U3R8bc
b5PkD9nn23EunqyVgahB9iuq6YHzqlkiCBWmc0tFoksKu3VFqBC8vzx3njcAqkacQuJ8kITYyaEc
uI2IYfXQjvahDj74UL9z0iaE+nk8R+AOjtqWrk7WHGR7g9/YeXW6WcBWqH5nfTRQp0/Yltrxnw+U
Dk/sp3CQcYXvuANzogpV3I2q55e2Q/Za23ij6drG24xP+xhzHFxswodzDTeOvNWIjuCHtpfPGZmJ
6yBcjMXHvTYI27dwiyIXtxKa/LkcrHfSdNX4sUgV0ZW6Wm5ncXw7lO6r+figX8otKsApfmnKL93Q
74BKTYNttiEu9CLj9v7CHigoI4gc9S92yB5jNGwuNc1UPu+QG74ZL2byTWilkeYj6kYRIwdtgghT
Z0dLDNIpfz9PHG3Kdcz0VTnDH28v8PYjTVF8wuNlaATXhxTt7Z2naxkH/3iNfGCbZrddYolT4DJe
73QbBuUTi+UhMtgImVVwULzCVcFqj2uaZe3D3OmfWX5jDhV4d1ywhajeM6S+7STvW8vgWxXn7x4B
slKRcB/CUMt214YWte2O0D8QS05IG8himkFVyOP1VLXOAcw7WW29JdJsfXYqA/eF0NIfPAUh1KPQ
MzfD5DNw35KBxnnGjva4Hwpu1MMEKkeNI2TkRxIuvDZd8Z/bW6HJPP+RBJ4umx6xz0IYwHsLjpfT
7mmTqECsW71Rrz2zV6EpWPxNYolA9IvT21p8EHHNP4Z146J0w3uq3WUK4noHWqaTEpEmN1ExmyX7
S8zPcchSJcw69SKfiIMXny5fYmnxzeU83E7HROhb/gQep/in5S/XfCl3CJfD4Jjfpa1cRp7ezPUW
0UPJA4fQYnAw9hYYFBjtUx3G9nDPiU8UVvOhaHUIwVO4h9MvzAu0pyDK98wS4R0xat7hU4qdn1fc
8h4eqXxtwhD1/N0SZ8i2gRsC1Dj1LXrPIvIoP+NygmQF4L7eZ13Fq4HKdi+vF1QTVZPxSGzOhxO9
ZKVtPWwJtCeQQzmvGefaznD9RkNdWydaUQ/Bu1UIjeU8CWHKzFbXVGLbV09IzRtVwNZKtstWCYMA
ajjZTBO1x6g4sr2LIZVyUhXEHw2sG3urEDbT3bEL6uej2aGz4ya935VnUJRtey5GSfolgIWR7PhP
GtvUxlyFkp/iCewsFLnYMVFNv6ee4S5RBvZ4PTj1mWZZ48Ndhw3UKmlbLG5+KPTiBpE6gCub8dSL
/gbAeDBuzp4Vlt9NglYGOBbbrag5FvMjcONhq3An6tPJHsRy+e6EUBEtS/OTbGLyYn8LTlNii915
g1Y+YqCXt0vzVcjDC1+85MWNveT+dGfteE7O2D6nOgHgzMhO7ghsfoErPPdIHOjdLN4RQGyxZfy9
wg7RBNkPr2mj1DMuO4DjGdi2bNYtxZB7qDu6SIYvJPOHWAZJ7C92efXPEjA8kXZscnbCET6tVBfi
VvcVOetd+8IwgyRQrO8sFs+ezmazEXF77ZXvXY5zAeNUrRP7ogMwY/XJoIhWwW9Eo3LIppcnUsQY
2MEPqh0PeAPVbv+6JqiStewcBYmBADgt1SjIV3bVgZisnhawxj67JhdtP8qUKIrMYFONLRv63oqk
FoFhjxLb0KN60zxAyxpqc++ZtB7Cihs+KkoOuX+jgA8w2AG9nhwVetnZbY4eZSZ4qJ0ufMXksfT+
YrdSh9KaDaKQsc8KIQThN1AUpfBUJcUTfgTiqLvneRmJb9j4C/LBn3tl+kiBL8Er4CJ3KTvZGwHl
IypcYUYzMaoJLT+MicPV0i3HWE2Rn0knqN/fJGNJMSrlNWwpjLDLYet5Q7CxvRMayOLfav3ELgG/
p/eqRmK4pwAY8ovr+1uTaBOYO6RJ9ODNtdHTQ6n52haJwSzQOPA76zKwEsTKdmqoBmgiOGSh7G2h
tBseSPsSIyiJPhUXKq5RbrflMKd5WfMz5FLKjW1PtYexBuLhMkgUcRHRZuTnNccOhBF6NQTZYga/
UFIKP3dIM9elCbTUhgjUdxNmU0g64ABX6KbOh7Re54bfpXXSBLuPVtO83w+1AJLMVo2s9YjlvFgh
2VL7qFjtFqLLmmWn7Sy81DmWRyKmLRIL+ziRD4f+o9ym1yLqdwwDkSoaRZGymJXFynCALPBiVTBc
D7QFty+onTJ0UduGRqop+yCZreOAatk8gz+VKBK2IZ79IHxLDVVIUY+2GRHvQ7/Uc2PZXKQhYTp+
GQ+gTwD9qxom0fm/Xqn7CS1vYWVizgbJFF8dSvcwiMf2I9NznwGiwH9GfJvPeDkyYHJG/p68yuuL
CltCQfK70QXaUnZtCqkgcyo5A/eNz8XJcT5wqjb75DCGGJUjGKBIvqkxLqn6DwFxYso0PghKXHZF
OY0doFcDDAe9tyRxZazyYmnT9W/oGUNXz/U1XJBB1FgupcoHRF5LHDHoFgKCiAzNm/nlvfxnbHnF
l42OQ1UqRy8wGcT2q9nGuko5tEqA9qGSryzThnHQ99U/obnXceTIcQwOqwgmSExILBt/k3i9r2uz
XxLftvVMkEFHWyAGIXOAiAHEDP5DfzoF9zTvfgNtKW9ee/lpH6ouZPJ6DtVlxZFDddKo2c2hkJX0
LuKt/CsjOWicI1pylgfWXavVC7clds2sJ03zPmLeqtKQzBiwYdEp+Sq1TqDI/Nvp8tnhBpUDdSki
4Mj5Q0eIsxOOBgqzCMY4cMzYAY+zO8ZG+nZQs7nQFGwTx/0dnU8UUrHJwx1qGyh4MIysuWBVN5kE
TCVmxSwwpPXubaRiY9ZrN/Xaegwf9HZOk9qFnG81KOhhucDa9AHocnHhj+XiWkfm748kqPHCd3NQ
nAOeOCfvFavqFO2s2gWAp01j0A2ZCHTA/JBrGlu9lzesVX9TwlF4tsN2tSYWG7ieD4urG7q3UQJS
0VpHF71Nm7WnD/9hPrb95CAnpuxEDx4llvTrQyzXWgTTHIOzm6WS0uU5ZKaos9dLni59I9hWutlj
eGHSIngtHm8FLJghIVNFPZM76swfHVciMkkX9+adA7RsHyZRpc4/+XopqWO4BURRSGV/QcLlcOy4
ZE/zCLwSMEWB/4M/OkitEcD3Gg3b1am4O+9L2F3zlwV29wSnxMrzvQuGNa8lxlufRBJOrgCbHO0Q
1omxeMGf+3LCNhvsA8TS1TAXJEg/sNKxxWiEMpNlRhaWcOwCC+xMgiCTIdpFcGCJXB8h4K4m2mOC
VSM66KpAlvgHs3JcWxle4gqyNVbZSf7c15TNVt49fFHKTuqKrJeqFDCTGyUVrHkVl7RgT8s9uBSD
a09/f/mY0dbdcI/MifdhVNpBN1p6XQRKOlvhbX+/Ei4XWkGxyna9k44irbM/13SWt75ydrPUDRZx
qJAMOWtaAvZ+WQQ2XthDHHZ2zQNUqeezkUHGcwo/pbrFvFfOrErJTS6qq21HhRxizsWqLbDIBK1o
blE2eG2CKiXQBa4niyiYKfamd3IlJik+OZcRII0v3pEQLg1+4oyGprqqZcBkNImZRrXCVODpt4fm
+P4ZolxO4RGHxALssHoUaeAQ1rPPc0Ba1J+f3fCxw/ZShSiMkn4A/GzfurltGz92IeZdgoP0Gvaf
YvAE58JZ64rdX4A+p2IZsIZKqNv+qdni/ehNg1hOyN4VrLl6PpOe7SODqk6TTaRMc+TzbMZ/1NFT
mHOPkDkqCQU+k0XU/fc8xVcSpA+ni0ua6Kd4gEv+z1yOYZC4DaP01GeIP1Uzu+oA3cvv8X9qAlcx
KSZpF5mHLYlV7WkhgVsJCXLD467PEwwlrAYMPR4HsIbQpQ/q7/jmrOZ5GcwJ/cnlBDv98LGB3Fkf
L22G+REv5ZbWiGg9rXNWuxMiH52X7XBi3hJ3PGtouVWbXZCoCKYHFvJ+StfymzZNpLz6JO31j7Hl
wb6uJURrR8e3QngFUVv9v8xLp4VvpDcc8iwN5+BtPuUiG2GeP9NAOmPzMqEQoZHcnpxBm7gt9fSO
ldm+SXKPD2VPnVe7zMgIsFUGD3NapueviVm7o1fj3UYVDVacDHExt+kcxy7+SdwvaD/PYQIP5R0C
CNVLliX4ZGSXbWUXZfv0hMkLUjvLyVISGmdFG4G71P6PjyUa2JCTEyoNi2L9QP8RoYMEOSCU4nat
K5HzFBhknKXuZJKbFiAw/JofCBBetoCbeeth9+4TyeYezDdF0r6JudgIw8y7fL2a7oLj3T+aFaVj
kOPBjGsoJPUz8C8eHAfZCgRLVzup0psuOMOvZtWUgGhRf1t986IxnhCy1gPtazIwoBR9z4IDShJN
3g4/rfooVRL3nBLjK+PaGK2L/sQaymrUVFIxwuphOJlh9UPxlMbLczqeOfX+Cymq51y0RrUqKcZ7
oT0GVPLHKme5JMN8SCmWMLm7XSnAZCtsUPfjXWqkGMgJOCwHNJ+gcnEXafMjIUZ82TB84XP9enn3
7kl/+FbxDv6Xim6K5yTjk4cyHSPb0SiawBBjjk5u8WlrdBrJxXUEsOGeHdgRJ4T/6Eynv/4Y4sbU
ObNzmFwiMyU14Qfn6rCQW/H/B9navUhOX64EHM3gMqDKmIkpF3n3esHm7w/PIxf6dNpMoUbof7xa
msH+a1gsSxrTp7ISOc9c8eNgKv2y9iNysgDGOlBbV3TRe6hUPWh9hjSvaQlrsziYH5UsYow0PmTJ
JFCXtUerJCdLrJJ3NXFIM5VnQ+CxPMsWubEwPky7xmBM1tz9QU0keDZu2P21Zt7/kvPV5Bwv0Xpg
xEqjsp/BU4tS3BKcUlKvqdiVQgfiFck43Qq1r3ugBuhTJYFuRYq3jaS2m/f2ZBsK3yLQesJVZDJ7
qYqJPY4WfpZuYXRrMgcBnzgzmRpTT+Sc0uIkUoEc0XNRlhm+a09xPsddVvyrvjb84pNgiySohLP1
wC4Fy7gY1feIb+T7VBNAjB++gy9sPWLz9CzYAYPnTCjn/FRGe3dRTIFJbUOnZFfad/KerqttADyu
2B79MV/lpnCvEHNBVBVp5IFgVNJpP06lSzxXK0BqJE1LIbQAVYtv1ekeiGEaB/eEElGOtFJsj+El
v6h+2r9V9aQIqF8nnE8omFy4irAzkPhqEYt/MVPyoJzLubVvo5hu+ThFW0tSfywCvUjFR3vtEuII
N4kGPgE8KNx+oWYYkxuKdOXo4u5u3aoZvA3Pt23S3XLLGWS7HbdhO8HkjBkiYc7GO/LmhUaTIxtm
2lp1tnP1uF+X+VH4fcIr+Wzd6wD1BEOEsi7+L4C9RaZunIBihnli+cVu+nGeEaviMAPs0GRu0lwr
S3+5IGWtBE/iIEkvH+V3O+djB5fve7FSlJ8A/lw+dzOBZlT1XJp9oF8nC2Z+pJqGpfXT3jsOuq48
fHbliFYWBm1CnH6US26akjzXQyMwc3LAs9/t+LYnJawRon8D0f2RI3yuJUx332Ksf4tuQKWHjJ72
xP9oZMHDcLNnJoAaqsnGaux7jnxqUGAEmgpC73Uy6O9mtdL017wt7KHwo2X63KsFKab6XUlRpkqD
+EDLpKE4X0vyoyXe/aW8v14QAEt+MEMe1wbbZLK/qThcsSpsu3HXPITUD2Vklo+CrefgUFlVvGDl
O1euQgpMjkZ7bzcUGEK2ol6MrojZfA40lUVpk/0Cy/a2dcdbSsQ0P7x3twUa2BGbgwO+95G1nDwe
UjfrKmNUImumV8PdoLbTdgfjD0jF+PcuVicCv22+HDRI7War64O2s44OXSdCPKUxVdZh6+B0wDCF
ESYzQsXX6dJVJogd+M+ZdxSIDKSNgBJxy85H/ZE+UNS2tnJDg50MHr8rISkmLBNIbwIDmbyVNOLc
oLFpmgixOedEGpB6DYTlLqIN4em6Q66NZyN/TcN3RWWSEdBhSZaAggn4yAnyVBeePRTieJGgdSWW
5N34Y6B73wXYpmYdhCogZtR5915tMsOAl/Lmt8eDYqkE+N1BDQ8fMSHA8OIhRYQ8fPvNhj/+w8IH
tiEf8QiZ3Hbt8/whQ2Z3a5wuK9MttOdzvtqERaQg3NBSzr8IUqklSmStNHqH0wdGJ5+fopRsA4zw
1YEI4RCsfEicgpBG+NlBnh+7eBQypwRjyYUx7CNZq5QhEPGXTMn9g6Sg7V/89UQ97IO9QgVysKBx
5hvjJsba0SEOrG9LOoOvOxTcRkF5UAmCgYef6XC02CvRGaI8IrYGGUR0egZa9ppDWNd/WXv9uPvv
qa8kOFqhRklMYDIz3bT3isz3UsO7zDrXioATsGnzNivBFfM3Bgh+a2nrcMJp6iigGjFkh95+KbBw
HeqckPi+4m9cUtksS1mYZFQ0hqapAxL5RVJXu4xjH+LFiNwkEqLtuUZ7dBQ7alO3N52EFkR7qkZA
mttg+/4XYVsj9kxIzIQuIto1C5rCMszlgDkmhrZGwzAwYba2Gw2qq3xdqXekZY/FYd584lv47s3U
gIeLoT1/HhSDJv4stuLPc/ooSnXQr0YvS9U1sGBg6Ma4Gt3xocHMK6qTTmDwg5gBRt3u/NSvYEta
+1E7YGsMTluRydYWg22sweD9HxDdU0suypJiwsCZDLZkBxw5lPUO5jGbIUNZ/e9I8WQhIPCGxzIg
J1sNTyh+QsHhsLKfRS3vs3OYaeVRyaOW1bsELXfRp4g7PU204i7cMB292ApWOL0btwe9+xeiEARg
Cr3xtv62TBuSnQc4FvB8chUwryWDHyZvgyDgaUdOVOY772usp0VowmCHWnkulO4c26dqVBkg+gqr
UtskCCdj5bqURBi2PJ/YXzeP+OtfGj0HL9VVZzhzzIHbQUXOoijvDs2oJOUW5FJAmOCYCd2pVE0K
38SSXqGZdNiwLiYhm1d4Meuu0Ofa7upChYgfpBo/A5HdkFw3nIluufrzPHqHGk9Nx/mSMMkWJrWf
coF76Pe+Wp285mhDLdMTOpApK2R6TFhZClYyW6kYB5Ox/o5IuI5uWhO3iVAEi31dYbXML53foJ6f
cC1qm9P0GWSSKe15yMP/Lv1JzX7xNA856TQ8virpxhCT7i/PWJHDPsT7hM5ccMpLFXrfnmdkbDZV
nBRg89VcnXWEbpzeWmkloJtjM+J9iXe1H82LvICFDy2EdM0huIot34NGM9fa4CaPYJPJ1zFjzrLH
U1F3h8h5MBDzQPqwvwb00NCWbvA/p0c/A2gEoQLK45lmgDeF0zABXaPS4LaLKGfWn1FuvEIdqo3q
+u80A58qauAhbkAMfdfLR3anUvLa22ef4t/F3RzcnA3WLCpBFf3z2LLB++LSF11e8jHOKMNRpmBI
jgLHwcfWGP69iyfIvDxU3G/zrxv98VQIKGbF9JZxNYad3lnALHSgKVDUOYKP1gk88S+Bjdqpp/1Z
K7AWmcIQ9FtOORpaTgnpp/w5DNX6pRX7mNTIrt1fsuT9i8CcAEO+ICtlNVzCQXyoy83NTz/56Iub
Yqu8DHDO/CYgI2NX4xbDVgbgldAKlZkfB8r2amVabHRDSfbQFhYWIMvkboWHj2VzQGD2s7KkrTNy
3jPCykI0GAR4xNVi3cBAnO5I9VxZBa5FNvPYcllWnuSgUZImmFN3gN1ZRioE2bYiHy7+yNIpjaBP
/LueXHkqlaMLGwEOnilsvAlCQyM8480ZSPi5qaQY0ymYNGfRn9NZe5oziHGAI4TDG9gO6/6XfCV9
cuOlCdW0Tvcv/P4bfJSrwDH/ZZx7w0HMlzZ30yZ7JmXH5d4Nzvlix67yNp4m0c0QF+Ldcqt2OVnP
wcrSDOTEqOLGJrobb232u3h240eMt3Yslet+xOUHyEPAbWOvokrE9L9SOeOrXL8V9nWZq8XsAKUq
fvORCnoJUigk1bUrGssAR/HYahFW5qdLAUVP0cdT9FBwOAZl22ZonTqs1i6d0NwvxyVdY9ye60Tq
Ohv1QmvBA9GQKBbnckfu5ACRKXOZD/XFZ6TljUnPd2LV4/grZ3/aYDN7PrluygXlVNn+T/CDhlw8
VlV2yb3uZIFpplpha0DNLWWSQTXlHB49aainIQdIQIOyZWiS8UL8+U3n9zhmaHYj1xVQM2xA1w1q
mZvlNjXse21TxVOIjmyIN5AgXqimAIGZRURXTDJfedVs17MkOyQhPhfVa0Dl2sGpUrbhEg4ZtK2Y
CuGd3gODntEZgsnl4xIsyqjV+Q3PuGSIsbHzw7a0KrvFchnj57zM+iRBs2vU4lKzMnUJP0T9RuwB
N6v4ChJBvZj9Wrack/rsKdSiBjk4EdaMulTLMLbs9f+X0bsRVSUZfilOXbEahe3/g8sQuR0TFLas
RpVXxYOMPvJ6EWou2wDKIHVNcN6HDTStkpq9bWTIJB1Xaam3cw+5QqATEy9xhQ9DQH4kLvHpBHue
3ke+nJXyU5xeGLu2e+GXwDM+0j6V5erQaYIbo/cr5ysB/4yVQsJaCJWS431VrgqfILRb30PXuhle
XbTQ2dXCOKcEUzt5YzM3hecfsL6D6N8fcsKVitdM7dZF60rElLvMfl9v0WAYuge25iig3deptlAc
BcBmofcFbY8/LxTmngQI2gkNcI3kBk2etKu96xXL+CRYWIMVnbTBx0bYcW4EguJyRrmNBaxfUdZT
PGZmyH9JjdRuSUjGWFoFRIMRTqDUUMX49ujhhz0BXnoLMOG9zggfGU4DY1RL1uj+7zCFEOafWCvO
puiYoqnkBZLcisZiCw0dQzgqIA6B0Ejag9vA2k8cxM60EadR1+92cfQVqIM8kRs58RGbPaqAzw9A
84VKWi3gvRMGZEDTQIIkKn30LuDFTzhr4wLYbuvAIzQwnxZHT0nGE95hJKQLadJi0NqNRV8dB/ai
QFO80v3iL5Sh8Ge+Uhznm9Zdnxq4G9nyeafxBrsBqqmsLYwmZSeTk+FG2jaI5rM35kqEdhlXRrQ+
69FNG6sAXeqcnschhxvIabSVi9F482cJFNAEzBOdJtzWihYLTutZNoQdF+AqS/8+ockt25S9R770
uDqU5HEG9kA/O/ILbl9EZ/tM5o1hgSaqTG5pKkZt8aC9BCwV+OsHZplbXrnze6Fo+vlN4TlXIDQ8
zfkQ82SkhZjpyN/6xzKouZMdWLvbHh0OoJPNM3ckTXlyHeOecc9uovTvLC1AUj7rhRorhVavq7LW
6MJOsnjCpVcsfwCCa/2FtETkK/7w6sISXyXi1g1HQ2S1NjFOR8Lz++gBSTbMaQdeDZ3Cso/1XI77
be/UQCyWnnVEVuXQGAmzzhWhYEHtmdqNJVOzu5VWeY3fIvxzOlzyJT3GeOpFq8CPdSJD+kTwsK/u
TancOQRtTEn7G62JuoGnfltJd5yf4XYQjokhUxJjSJu4QubMD3QGIboaHd2Nt4PYGTZWrY2FzwJr
macV55Juw9CvwyYCbciVbSh9BNGSAud8kUM8/AvyBmOeV2wTmEsBFNhBqeBR4h+8hLz5qe/ZbcKo
9SZATPVGIvJ6gahuRFXABblSQqvrwD5bAWTgLYzR89eKddIPlxx1D+I/kH2qbk0+ncQUAhBNq1Me
PJD2WNQ1Ur4UlP2nOu6wC10QY9feHF/85DpdihWbcWg8WXuhvUr7m6KrByJzglGn68G3Y29lc7uW
lstloVURfFevMeG7o3UY8/N7VoGNYWDs4viRX8IN5/iIKcXJpOTzflH3EANNq1PYos5Ku2XFQeSJ
P91zcQQCe8FLGbyRBdzsbgk2b+0F8f0Fl1fPHw+M5NHOXCZqgGLejPLe9Z2yp/HO5sZGM1xfxb6u
+Tlf3n4eDakynBD7K/yeIZKGP5AyQQo5mMhml7CRpk89dc001JLFXCQutoMDSrVScUdDXjuJZ/5G
yc2oQ5vh81+28nr7u9fbE21fZ/Aj1szdI7YKJ2dAF7a60u6ddPJseuCtbN7fZ2PuZ8UjYznZhLVF
LXa4NoZdD0C2oFdQJGOm6hWHmx3Surl4SAIaYqkKSDdO9xChzFnHHhvHOpUhjEAHazNBKTZ44adG
UNvu4lZYBGlcs6tfEdAMbPeug+lODupPWzWMr3I3ZjTxMOkMsh6lw2AxWldy4m2/lutGc6ChObLx
CCCPKmZGLxxVTGfRx9SnPNXlla6PVqYXH5VICnzLDez48zkVxfJAroj5bbidt58WMnBY+kg53tC/
LYRvXKqSYEJ549jHr2IP7ygZGpGtdZNL08/TSrvuYcf3P7j+oMrOq5aM5tRnt5VB7SsQv7rUYwI8
paRPqeGz6DOkZYd9iZK/n678dBiQuMSlv5wp8YDokjvQJEL2mvVHsjiiv8LxTbuDsr8AvL7xBiQI
PAZM5Q5P+kIYyGejaT+58mWiJro7enPXSAyuKuizWqecdWYH5aTRSH3EaRKGVxta9056cyrv/zYn
fR13SRhFFXGCV2GU6UqPEdPgYs+OHE8UtXV844o6f2CJOxPGpmpLlmHKoZKFGL7E1OMhcD1Tmh6A
j61l9T05pGpnhCtZRY8Ys2BDybPPQ/RZ/GsxWVgeP+ZZV2GogRyg1V5ZF4xPFKX1pgYTweern6Q7
yibPQehs+arQ40Mrgp7OoHpXxSxwM2+5TY++g0/76Xwtm+QS1BJjPUByC9dm0po0vkK2HtV06fz7
/t7CW/zk2YjI2J8ScPkMM8C0LWIMMvLoUqUphX1rt36/bjnDfq30xVvrpJvWMu8zDiNa8TV2FdN+
u8Nes2gUxB1tNxN7YtgvRLwufM15sssO5DzXCAOkcvw/n0mzZtJNyvCiNsODq1Qb2OTW45zp+QBz
eit46K35ZBCzsY+D85p3e+ZYRyDvHZq+YeFAKN2eAUt05qLqlOCleTdR++bGg8aeKBvjLYxC/oKf
wdjHBTsvmlCd/t4bdSAR4dPbKRuI7lFlkagFlm5xsyVBwPotrXsg+kz9LFKe0bHeqraj5/YhgBrO
Hv5/kjnvSWnZug64twPDXaDIA0eowUd09cssimJW4D2oYC6blM7zZxFuSN/z0m87HQo0nQa4KtKr
yuahWifNJ2UGsXKMkwhidCxEK7kJcvxUbHdTHV8Vuaj68RiiX/uNIcbpDcj4yNADi8hwyVuPSeY8
gEZtSJXhalea0rOe5NsJP4+rcwLbpZc8AE5Xfx3qRBs+P7z0sgtNobIT6EZd9X19MDVD42ijWPUV
ACEmXwpjZPizM17SUh9F13my+ZtGixQcT1wWUn1Lzn6oX0g2WbRS9viJLR7CVv2rXGoNnUUcz8vp
48qOV7JutzJWc/Qim8fseVT6Qoj6cRbknEfLYOC++7/Gl0RbeAukIYSGOPO3HobrikACwvg1EWHe
T158E0tkN52+tLOTTjxYDTmfM/y76IhbXqVFzfo5RbX+ZQarIUErLko6Gimx9Li71/0IAs9LCBnx
2PLwOcv5R/Nqvo5gupHoIhqubw2Vy2weuuy0g0C2Km4ODDsLz5dY+BEhfWqCdcBDEOc1l/J9/Rnq
fdpDrbRPPJC0t3LecikbVfXUOBjWkrxXFrAYR/ns5/KW0QKc4EFEgA1/E9XBaRD4gTFVgxrfwmta
P1Nmty6qsO1Uo2PONEzj0STi+bfXqWy9oBAPwxCnaCmVFYt8QN9mHB3PcKJBvNOhaYs9okJgJfQz
M9ySsUQ9RF/9XGtdHTomKFvQJcOqefeGE0RhNugdlFQuZBAx6H2igKBOLRe9XsA9mO3m9aR0QLq+
E9RcsZbhRqXLsqu14cGveu8p/5VgFdWWDs614Tu9KFS85U1wC0ZQ8T13YOMff+59uRGq8uRFEZRd
LY3nOw5KK7cbjrPO0dcmsvSxc161+2D6wb1OLZMZEz8Iq0ac4h//UgYmHeT8LkVVjfT1oba+GLqU
jl8f6tWMon/Dla/szI+rocO07yrHdH6p8VE8693H9mdznz9maAxfvalcBc9WIOFKFA0Gzosj5NR2
lcCYocUHwKNa3XfGknRn5zpNkRSh7jyGfrltRzzXIkwVKoZ/o2JzPabtBE2YUwiyieUIwm9EEWTk
wcLKpbpjXUYZnzXDL6aP2eBI/auTB9OmsXmmdey0jQRY1nE4JQqoBXNTiidyaj7SL7PaaEVE/EXt
iCRa9Cden/shImhIctllvapzR+98zCPRcLFf12zbRSYzki2XY5Wu4djosx/WE99/JaBaK815oYvh
y33NsxEchoigIkwGAdhXG3tHe6o4VEZ4ae4T5BLRO15uNI5PlUEnMkNbapCon6iBtpfreowKP3a3
K2oloQIvmrlGAs6KlrRv7w2ikiEA9GRN4CNiPTRwDTWwVCI9n6xbry3wx74PGxlzJmPb+XgzKpZw
EOicQ0khMCeAv00wIhbwcpZQsn2lr3b6rRRVPMuPy/+mmceuHFTy8CVE7+jn8m8xgQ7cXL9kts9W
mik/ZUS+ChxXOcXE8DqRE04gTDW/5zeSJ+UbTxrSLNyPFxwGPowalKD/HnBNVTYKsx/m+2FGCuZN
D+YGHqr7/3fg1ZRbz1IxMclDtScM9FhlbpS7jTdQaGpLpvLWwAvMQiNIcK1mxKDPi2VadA5wlpr6
b4r4RWOEt2Ohd2yIsh+9ymgwVGiqh3EiOQkWM1brnQgkp88TnQZg156aK8h+a72NQz80rkWYqfFk
EcKeJKme2Kj8yo7zGz9TgT/svMQY4bqZFA/DCNUj9DQG6SwdTeBVtexkIrPZ9oB0lDo1ms969J2P
PcSTey+/Rv9iDw/jPcU36fUEDMzNycVpqKSamq//CMc7+omQh/S0/YpitsOvZYTNDTmEtraaS1In
gn9rW6Um1oqmxl13AgCQonN8moxpvJnSIoW/4BbrJll7pZxNgTXi9qeUlaPW6e38Rkb8FiE9dh0c
i+iT8bIH7vw0Ri92tqC1aMcj82kozkixcniBv0U0Ih+LlHs9/KNUWlY5JJsCCLqDeWwfLsQAlrz3
W8x9NEQFquYdB13kei5STiQ9JMFRbFye2tpoO1DN0g+IDIngdZkFQ5eQu4CHLYe6zsiKLl2otl6V
vlG2tthOJtD8XZGzGxVD1ptTrUhEHA0xHDhtTl2RDr69/cAPBfibeW96daIfneTOmc9kxSQQvovq
poWfN/6+acHInh5b9j+wDTyvt0gwNfabqcpxBK0HO8E0plNvPnWzii4YJTt1nARdAOGzrXjqZZ2m
e6nlHUIl8IUT7yZ/Ga2dgiDYa4UpuRmwZh3FOP6hXWNHsUlcYteEhD4Ff1m98/3dqAFZStbuOkfk
OHg9TxumRkPDH/UMqPVgAx+6MtZGmHfcY++6kAG2OPd02m4woz2T2UrtTKjGcizCt5Noe+dmKbfj
9fm49RrbC/SA5tMBGQIM03WpbMr2hiliqhu9KDJUT91mzDdLsATzCC+R8IOaiNkn7xxoFZpiugrq
yoSssgqlqYvxggfm4fcXVSimPyl8VsdUWUvq1KZkpMVrMQk/JinAvm+W9WidnRNtjC4eG+5eVxfz
DPiVrqOFPws/F01ydPFlWu3KGVU14IZC5LwOnqFVBa9xc/1RiXPCxvLZ7FNjMbcM8XKCwegn6ARa
3MyQ2so2ogMpgiQN8ETmG/5TJi6mjZQS199CtmykRdaioaHGEfpOXQ3jMLi5CBH/RHOyLNqjhyTt
qfS1BWstGuTrZ64xgjPlsXxe1HP0rZlap4IoYQr5eONRlw5k1xLN+F79bJMQIMMQzbXrUSxDQVqx
42XK+8KnuC0naVGN3yG8FjQF6lekWaJf4NBZwoklh3J/2TnVfj8rvGmOgIye8tkBqqjk94oMJdBU
dMvZFZeYDuKcNYAoLNWa+aNL/tXZKLq9uDQY6KpHF7Z9TEi04DJlpOSTlrUxv6g9gJBS+xXegur9
HFUK6Zuz8R5JWD9rfqgzQurzDbyWOpr/EOQcBCoUnD0yFvsetYZBvycbkIJaxfmn41ua8wHhSbqG
e0MNcLRZZnxTlh3cMlgXbVIDRn9nPWM2h+CEz4t3gOXNEUARYoZ1WM972LBcCy3h+qUn1Te4mQ+h
mNKSctEjZxW281+qgge6xH7TbHkjuZNdms2iBFwSDrurvguOkxTZ7vlYzU80gRelOnCInrARZce1
6PS3EmNHRGrrkH70uUZwLtia+V2weTuprRuC5fKdeq3Ug/F8meJBLv94sRsGawrw6TOvFz4pJdgL
m7wd+j/wWVhq4DS25DMkP4nz+DJVLnw1zxUh/0n4+kLeICUiGa72c2ARTsvQKaDLqOQgiFUEIjLA
yCY1DxjgN4sNgkDPe3PN9pbyJNX6Ne+599soqMaxQakwBcPqOZyNw0nezGalmrwx4HVTpEA61X41
CW3WZ0rtulU+yY8YvMn47KTVcq4SA/WbCCIb/v3YuYpgn5U4RdFWuCAf0+BO15PD+MpNX5ooUeLQ
dznwraUZghM2li9yCpHYj//uEgaqDngQ5XWAi95r2knUkgaip1/+3NoAl3OTC7KlVlb6E4yPLbyi
0K29xuAt2NH61bllBDT7NZvyrJde6fjHNzKVwF5fC2W+dwVj+TXi86bFrNnw9op/4KlKCdFIaf/M
2lGkS3AgQTCa3gaBx0OzNU6SuV4xM7dG9UGbU2GcoeQns8jTAlo3u/4q9906EmHRR5ZSRuBABtVu
N2j8HmiRXm5IY74gUpMw+r3e8iwAXjI0fh4ztemH7024OYh81iyfqOzgZK8EcZrzIT8D732BYx0M
Jhs36dXAqoY/804DkaXRgc8Y/pGLTEoE19hPZ7JQWWlZD516ZXRdkiPiRxyAPHgwwHNZ60gDpww/
bkHIRtaFw2mBWtggN6MkhPnDdwsuA8d+UbsVrbmupGq233yeEix+I62GBiSIXsASj9Zle3zNIF0e
FTspuLlirXphsiin+nx5xr4x0vjHDy0DAWx6yuE8bt74xiCQQiy1tFe/86HYt56ZNXYcGe5BThfe
iXG63xRA6cTaJsT2buwa3lrh0Q0Ygou6vrwlBBJDBqlhuZx8nbaYjJLb4y7Pa466lQ/D0W6KbbdE
xKILAL65G8WUV0COr2Z+Klx2rZLbDk64v9EHuYnCJLWT4YoSBnMmuA/Pyx1M8lRF+l/mB/tpO3hX
VB+VzLoqG59hFwjw32mqL9RTEbAvODc06ZMZko2ghNBXqdIfYZlCNfwabuWTKhXC52d2jAw1x6/X
qFTmviklPWWQPf/HXp4j35oGhr/Qt/hJlMQWYUiOqk0aET8IvNdZt6oT3tokzsmPR0QKQqueoCpI
ttPx2dZPwjg6ruUL1lYNd72WNA97d97HW/ORtzoIn/e52ghIhW3/QkMaZT0OTFWF/q8kSSElJMiY
MSiVuqcLvA3RmkxUx+Q0FaJoyG6KRwm84huV6AzR0j6Ebfs65OGpyr7utbxEe89eHozyyXzABVf8
mn9TxU2c3ox6CFFa33ypdGbtOfUwBWoPRUV9Q14AEpcQMnVvjbmajL7VW0WlyLfWZB4VhUqWcGgN
hbwj0vnqmfV+xafSjjhvAHd6ecEkxTaEYmnvjoRn2pv8wPknwk0vE6hLGRwBVHT0bcgmZ88Lbhxm
EKUp7pUJ3qxhBvkH6XX+DbL5DlQYSFp/ZDwdlj4fOt6k9QSF2XB/YIsouRPsWsxPLwve7aOU/MoI
4U8iqturJ8/gwqLJ9Wq5u6iF3Tv8Mg+P3Rr3w6nKrz8kb997jHgYZKzRLByta+d/OVG+MvyyG2i/
g60+hlRC+fJhBul6CqUCNsteHYWj1gHoMhS19JeEfbEP2LynMJddMY/1v4uhSvebNnmoZrUjiGve
E0VJa2ICy9pKihxHq2WfeFIwWtO3vDdWvXR5W2cp6MSmzthDGqdCsKW0lQVewsglN8AOzUzrrhOC
vDMIHf6kaw6xb0K0xvTRmJR0BYcu4wNvNnwu9U0YLkJ9IjD8xFPalW4CJbpASm8iEbJ+hzsRGFE9
PU7uSh55YLwO6DJ5Zd/s9Yt7HmbMU+aryBVo2r4PE6oqgU7A43wgiwE/BqyHOMyfIn8n5l1UzgnP
AtUdwLS4d/I+/IdlXQxquJ2C/RuHDSlu+R6hUPAVc31cOOzySCzFkB45F8yba1RSOM6G4ARcgDeT
RIFoXnYAAZ/TSOgJWWxlH60fiiWz9Zcl9UqtNqYmdJGb5ei/Tyo7hV6DxIK9CqSjgXHgdTjE0wYb
oyiHrHRuI/ipRGMhxwLTZdZ6RQrceESD3nSIEmgDNFcT1xViBPID1aU3f0QV/8IeC1KUTUvOx9o0
+iV34OPAB+/UK9LosPkbjKq5pBdQOccBgvWvSTyM0Yv8R2UP3X2wEODpWn+rxpIyn/YTcDNoe1uI
gm70POvjOsoM7XOG/m6Oso2ptzsE3C+Mg8sZOw43HAPPu9uSOuSBzT1L0SyVntn1wTnlyIYt5Y8x
HJ31+t1TD0vK0RRsGu39usrwEAX0SA6ew8WK4rM6AKbblribKBPREUcMY1Z74VuA3Mvde7JV6e8U
cqDLTkJh40Qk36cldQdjND2LihDu0B/M+xFcEuGUS+9fP1BVD/LhEVGWuIc8829NnkHmpaCA5YvV
NmG/02zNncZ7QV3dPQ56D3NxyqT2oeT1At3Dxgr+Xj6T1PJl+qVSu+wC+BPlsYtjAXSkFnhFW27d
bVI/of3T9o8F9AqfzGoo9dBdWXLrNoVEK+WpY2NlXGjCrnL5Rg0AaX/0rdinMoC1g9vlsNpg/I8A
xYgt/S62A5JfuvqggKue3292WvT+02qMrbuUK+aci6wuB38fALz0nbc1GuU17i0jBwvtTrVnMYLk
IMDTzD5xzFFtiPfzAtW3fyTMQTu+X2NNcPT3qESjBMZ+89zHr8m4MN8crpCUqsF9YjDPDlPh8lr6
qyxz24QE313LWfjk+jd4AKCQ4I1sgcoEo+JZM+NDLEEqw49NYY0bPcBeoWIzQSHycZeAEsIhD6ga
yxVHbfzIugX4gMm+ryHGp8gYQFuWGuFoybpIPJTylzRvgeveXof3mu87LPqJlslfphpw81CirPpL
qVok1ns9xyg3vTqVPYAhv8KOsPdPccPxr/UBfp3qEiXpfMCxCIkW+2tm5G9r064AIt1Q7HVIy7Nm
GmVXP5FgBK2Fs/+VOcS/NrRmOSCeisCVqpaAlxrH+3Tj4l5ElnN0ngCgm85YvrrWUjThhk/PFwvD
bQLotrq/qbcLnXIaOis5fKAsxYg/DWApgBGbvfZkA2rRT6o9zhzlG4LrQgN1Ur//pghr2NJzKVkJ
o3KyXBIigF5w1sM1tJuGqFX3gt7nXM2AkYP7YzKX2UaB+KnuDxnzD91K19uFUve+G525Qcb+X4Y4
mv3EF8ij8ctD8/x/9R7lE5SUCdTAX1H1QLcVwOV2WK8xjtrZEM2mOiNIsnqIfhtQM2WPP/HPOTQr
Ck1WlU0zr7vQcci7j/Cnbu2yzgtsS4eYrbVjvs1+MyWPvTPFli+HOm/rmjdQ31HlSfiEEH3LY3kk
hlyef/ZS/bvSkZ4CTcGDgZMWBuhe+4mWl6ORMJR/ztiO1eobxvnHIAQ4D5ukdADUrC25C1iENDnS
XF5mHGZJ5vQSozQ0J3hrkkYe+vNE9FjqNunTnnvG7XwCOKfBKGFJVa0lfdbZX5t2RpjxomPXvZnU
rHPYkeTpEB5ZhcJkoT6NGro2VAlFiEIh74gXJQVVNA3P/GsFDqrqgbfeb/rWcZyywcBVVbxHxWc0
LQFhB9Tm1XMtp8fkSR6Pz/aD3Nn3fWYGBZ71ztQDXIDafxjIxdMcu6Ng92sDIBMGdIhtI6lfhZcG
z4obAylfJW2dkwJPv2uc6PFZgFN48meaUkFNrcsdw70D9csUJr/KtCRscFi7oKxMvud8cz7CNFjz
CfrgKt2u+CmZaGwd6679gRqnJd8UJoQ4VRvYq/plTPC/lMcE2t1BkbcDHs2ohLwc43EigciaCtiF
b+rj7PDg/VWk8ZguIvAKlO9c7LUGbOwoG2taac+DD5u+9y+Qx8+psZD90PhJBnSZ64ZZFHCHR7s9
7gFN+RwO9tTjaMIi0awQ3joTKFn+Om2ojeaP7yGALbT3JeUL7Jqoohp6JEUIPJQujjYHcbAWYS//
PlNEzGET6DBUBnxZP2IqgrstAJ9d/p3CHMm3ZJE96nlsst4jzky8o5RvdS+ayZO8Xm1Rc0tV+xUD
xr2CnE91thp5Ge9RtQO7sgXMMwcYo2eNMe98tutWNxaZZ1AE2PqoTs9ko5yCcUlKdcBTJwMzWzMO
wDpgS4ZBxOBIRsoXixj9Gg3b7S8EAGqRvtFu+GGntl/dq4znADBiqlUSXL6PT0DqD3w3NAE8RE8s
drSkGrbvb31icPZ2md/inyMMxbovluaVDIN77FOgcryUKzEqJ84vSJJ/UE7YINonkVQNQK6Ar1Jz
HzWp6jxt9jAmHPw2FjNbwNrCwGAiNWuM3kMdJrdg5uhXsUi6tYK7XFpV+ufuQmMG8Oiy9iRKAGC8
uapg9wcoDjsHdGx4+68zSwnzIJjz13hkVf+R6R0+DHocFC773imoGDYQ8eMk9YiWRoGXNHf4dcQ+
aWHiyahbTNpB9KzdKB0VHu0ABB8HnwCZdjr6nuQZa+BXYzu9zJTOqg3nCY2zlt5CUC0n/az7XhkT
DPgcE56P119U7P9LQAdc1/rkRtdGQ/Ly43tXzvUieoizyOXRCe6wUScfjnrKpK5Sf4rhsvyHZtEl
PjoZoBCKIZN2EtRHeg6awpYKuBAgrdpbLDQT3+isakK3hnEQZcarU+pA6T3D6CHHskOeb6n0cBW7
VuqhA9rD7Sx7CG/LvddqVD3hc6JF3N5fAK1MEC3SU6j5NzBiz1ZQ4iaE6qyK5gcejpJjZRjUrjdY
vs+/8Ie3fGgUpa/da1PUULfkLbrywr62/204I7duGsjZLnGVwFUTDPZra3x/By6dt0RZsNykzkLX
r8VdV526m9WUMHxq+5Iotl7QmIE4zkVZcYgRPotRbntvEirwV0+11u8khW5eg9m0fq7O5I1NChgu
9byUYKCSkG2yt4COq2/ACCcHuotoBIaKC1DGvUFxTfNuWDa7sSe8JdtJOItZ978tGUzSfPoLeWEs
xUbKTclxKD/n26HXkqFRkZmPXuX2oz4yLq/E/MT4bEpCdWF3x84UnWG9rolnJ6sOaZc0wSBXtPz9
MR3/ww2ezndnluwzRl58pznFCBaHpgTrQwg6WaPI5xqr/3WSYopmwf8ODMAjfDZQRBLVBNbbAhwJ
2/Y56sK92NVXhzpYMbTN+cSwY/WTP58qch4IkLYQwRwgLL+mM3G2TzMenIiGlzyg4bQ6X3NDgNk0
NrI324GMzhXdXyowVpsknXcimQpHyFskAcMoA/RBUJ+bu5Xfa1KJnPMwaeS24BI4M+iyuzd2mslc
tNB6g+rq8g5dN/WXee5GmmRH5/zub+bC6QB8qQfmJQ6iswc3XFrUSVDGNwkfdV0lsmkD5zGFHvrT
5P0H8569BVS8OuK32TWEt35QLYBl/N2GLr44JV34PbFxJwKYKYeEgiB8Vf0P9xnGhfeFCFPryxOu
xMJjaPoAB2dM7v6zRaoQYtk/FdsdgMiBRxuUbD20+xP7J1Oh8OBun26oA0Zu6T44bdMWScXxmUzc
O0nUsj4GOkKkzTNsLpfIVyuK5km7HOjyGJH7RTdoidBzasslL9NlqjfzyA0S9UwoY9xZ2SqTX+Lg
xOxTiX0m98LZSnwIU5q8MjcO1MtAUtHFE5VJvDeSo41PiY0bfKrqv+rJ0/Jw+arMD/zUEax8Lg1O
LAf+iUYOg+AB12KFyJjDy660NJbEbQexrx/SC+wg3+jCmh/SugE3i9DG8lt1KwZ/HrVWqJRbnNQB
vB161KrM6nn5OqMmPNms+EwKzZYIbnQkiuC3u0GcR0V9EtgYSgeDADg6FT3RongKMxLjnUOi+W7H
BVw3B5WHhOQYFSvOyC7g4iPRCQg4qj3KnTRrjUikCtbwIHdQIZVVAU9+hOlxl50Gt137gHdAABIn
Hh0qYlhcsn3VB9GtGvK8KVAdMDOdtVHYDw9Vkl/gd95ajYx/5K9mU6LsR0N2YA2FhImjsSn4F7Xl
YWVPI2VMH54sOoOf1Ml0NfbZBL/BEcGF/AoO4vny8Th19V32TgWpQZalIOMjNOH9I9KFbJ9FFaaD
yp3HEBSnywtSU2mlv8CQARvEh5XNX7VkX1gnZ9rccdB8vZ+E6nY9KPEc3JjjlM85Fr7PVxGQpbrX
M92vUMt1B3bGMNlWQSJsy3ggPzTWJJUXxMqcMO50cCDG7XP/OP6DRNAZSrx0h0FXQyLbh9VzodIk
n2l0SYU6Pe/CSgUgmzY4Tc/yPFnTE1wb0gvVpI4idnkKDPh8HlWAgSOCE8L28s2WEfRUVIVI6xXw
Wbb9OGwMu+U13r7d3c2GDFgJsbWafiJ2Osc12Jm8XBt0RX8GpcFa4VU8mMdaGmE5aXmrhf2bDD2D
YirtlWxj47Iu97KgtJKV6Oa1H6ArTLFuEhpv+TX/XqYQcJHrpcTfCnt6nJ+c/2eb8dz1Bbkr8cqd
e/MCNOmcS+DTWSJdZUwRQoQOsFKaeCUEG8DncSmpwuX+RYrv/8+CUHYLUdpESVipZ+D6FlcahWmx
mcoDCs3wnNLaV2fakspdUhZdMHZhgfdqBtErH4fK3k4VtZdYVnqPY/QeLv0rswUGlQv7azrnCuvt
JNCzkJYPYrUJLm0x3UkK7/fiBQ0Es/1H8wHD2mRa+8OJqCSQPeCUPhhw1sNIZA2naxfGUKhKmpcF
2fjEOXRseXVrPCU575gaYpyZFMJw2mZYJdXdoYliUn/dBNe8RMypfTeDNmvvxvY/ctS89qJV/dRh
IpIL0IXLGwNVw2AWe4Vc+LlXCELmCQARso1ZEMbNQ/3W9HvJroHIv5fEw1ZpmH2twidHvFb7NsJq
xWGLRauQ8q9J1s/Mh9nyUYwuHDyCfEu3Xs+CMAqXyFzbWHVHUaKGUXG00hm4AW2seeoaw8e3zcNs
4kB8+YNwHX5TJg0dqYymkQH8mDWM8CKkhZsWWT+kL6AExvys9uCt8JXnM6saZgca2MJcvdh6oEns
cnFV60IeZHWjjKGB+klyvrzgh+0UldxoxLU9yD+Cm5jraPvHYmoNvrHNq1eDUZ/43TB7zq3jaBSU
EJrov39+G2vs67IR25jMWuf5W4oad2CiOsnbtPx1Io+EUlUJniqe6p1Ugm/UzX6zaNoZCMgUGg8t
h9uuGSbjxOxOL+ap90SzUlavZkZDkkMbjzj+LCjlfxFCtm1wLCghgMo+Sy2gXwftbMSUJnB64Cmo
YJ2rVWE1zAu7QtJqfZdXxYkfedS3rOyL3ZIIjutj0lEoXeMG3ysu4FGn9Wjc9lKMZI5KxrtxjeBn
1birapDNaMim+ZVY3OZKlI9vHRUlkxldzm7zveupZjCX77kph2RnTBkd7h54soEh12ZZg9Uq8ZyQ
oT3cHDF74SFtlLTW0Z1cXuo6MOWY3LeremSJmQDoqccXAH1MLwP+J7qUIgMUHO+RP2tv0NKuPJu1
UtVIfzu3eMozkJO/X3iyhNlb7BbV9GosH+vLHF8hl8lZuOc1uwU2oScpCq46fotB3uD1WR9ameMk
NkSSey4z7EYBG2BAeJMjota6p+vdTH4TM/+FIFSKeuBaSPcbayNWxA7K6jN1IL628889+kFybHSi
oZp0THCMXGi4HanHCxAkxO0Ukuehch2s16IgKxAzjrlmKRLf6HUSz9Lp78VG6rYqzFHsCHN+KGpK
+CYBLGVc9xHiGEl2d9TQfAAIlxVHbNDfCahrNec66tAOxJSrM+xJfajTIaxD/YlhO/rkLQcMxlza
ONTHOvVrlMoWQj1VpAsLvz/7WBlUaN5YpkGiXAE2YnsHmDT7TZODdsmEKfOTZ7cGd6ouSUxmVS1c
+mTxMg/iP8hX/L7LMC6XiJ+I6NqugT8Od+C8RxniH064nb6Hip8hdAr2wOlfJ0Dalv3GXLQni5i/
NuFq67pFuc8w0hl8pn8+EA5bOz9fVV10yu9cKaDP3LFbqxbwNXAHSfj53p+e5u685tV70YVdETsz
1l+4ztCt2tu2XQwYKqhuId3fE1i6cLQzrZe4Xx4GGGAPr0zC2WGBPfY5PSttBscPGzsWXtSP1G8t
IsUUlu8BaeRDr4sBDGU8/sozx4b/+AdogsxpCFER9G9GYVV2Euhc2QkXQbqTLVMkU/FGXNdyvfvD
OUr8OQYPMxiIPnhs7VeJWCATCdqgzjUuAynwI/FtrXTT/bE9tu03c3b5bwXB/FtfUcXKHh6Fu8u+
PffP4qTQFFLgxxMeUTD3oEpKYIdbmGP39B3SNg4U8YRfmKOVzlXjibmYj9WSQeR1LCTxqjblmfXq
oxpSmMUWspOEiji6Kl0ab5EOiSMYYZG+AaBYV+8EMoDa/eq6GWsY8P/wSsjVd+gDs5MkA6MUuOWt
JsFON5pyFqOmlFmWFTKzwbRoZOANiIpq9UYdJTG8HBhELYtS24cVcJHchjxZJB8ZBUAdhQkLDd/K
H9OL6JMcQUz7WOTVhrGknFhisiOTomNPlkXhpfxUh9ZzxqlKLwcgjYDyJ/3B1CibW8B1DRFM8BQU
p05X94SwJPEsGwNGdtRZzheW9qZ0/rIYwQuNAE0Sg69G+THg7NjelKRP8zib+BD0+u2c0LX6Xj7L
TJ6H9IMKLkQTEvlwsvAf74wPd8GLqft5xnuyCVHOF7fO/3PTwi2JbHeNX/2UeCM64BSWaS+xLvUY
WL3fU7YmeQyjeRzcW0Sg1b11IxHpAB1W5OoAtF9X2x6O8p3bsYlbQO0ruzKT9D2GL7HLpJYunsjx
wlw5E5XIPUOgbQ0imY4gaIiUZbIUAjIUN2t03tMol+ZYJ2lIl9PrVFu2ZI6PP3jEelijlSx9cLTc
084QUN6ZtxXM+abjopitld4+XJUn2EvhvRuIeCc7c31MZ5ZdSG6mEGkYibhNT1Wl2cwm3TFXOMhX
fm7G0dDRIydwK+TYsdXrUWipStVMh490Ms6XwcgNpYJM5YLb6rpw5Op5iZHRkAQEuBvquO11YLyl
Fgxf74b2bcF8u8dAjSc0I26exgAmWWCimZYu/qOIvBKLtt7jtFE+nWwYaL9AI0kyqveFetsl5wOE
1UEzMbNWAGUnr/cZ3NJzBlC2mVRaMQT2jcaGy/aeKvkHuM3A/y13UIULXdNzF5+s6XgQiqKUlUi7
oFNPXnTj8EPl8SNLZYFUBWy86prYkR9UZIpx/spi6O8rvCGxtWmtDt5vFDX7oUXuA3TA5LvDJyJN
/ioDNGaQH7+fYMgzo38Y27F0S4BeOMM1ZF0ji7KsbiaVBR03fi4tlXToT/l3LzCtJZAwN+d3nN+d
sIABCU4TWYMZ+BmF6V5kt9lTRAzYl4NuQLxXdXDrd6FJK2qc+S6TXNnweRtq76uI6sXVuoVlxjWc
gw1IJWcZ+SLawQjVEQ7xGnaRppQuz5WlR1tfa7PBHctDsSXOnsN+rdE3Y90pY8ROemzB070JITt6
oSDxq7oo63hgCUtw2QQUAmX7Bj8s35BTBbItZATcek9aRxk883pHskHcf0hsdTikAsXyZs8jczLr
ZsCyi1M9jKurLq93T5Waa6jibQM7RuH+QgH6fxa2VE55hDsYNscTf/Gj3vn0Wju70N7V7CvHvgpQ
RsqwIu6rXgz44YLeroz/K7ebrxcGioexRkq/moPoMxAz8HdTg97E1ITiPiX8mT2PFedEys8G49sj
5BlqDs92Ee0R9tCfrQpv+1mltxvOLt4T5YW8+WfqmX147XXEav9bDq+m9ke8gttGTYvXsIvSVjUE
eJpBGnoePVqY7dzXeNWbVcvMSKE+k49e0v0wmezpbOcU+FooZ7by1tTmXm/iQuR+iLglvYg3CY/V
PcQMFk8vQuJ0gnBGUowKQBXO1SArPzPLhiJFUzeCrzNQTuHUav6N/tMo7cgGhCfwW96+eWiTCLkT
T5+3LzyOAgo3nquSq1NGUbbxXqKnLuhzEE9gQBKIdRkO9qSYBhmV1a6shzxhgn4/ZFVGygDFy1mG
dNRkSUXxPHB6jDrzONSj+2xoqtkbNRGdoNVzowk7rWUMEjTTR2raTpAfU2sUXfYBnQQqeC92F0LL
BszynOQnnjO1Tm3Y70ZqvvT2doeNAQfy53cfN4nGsnyeyUhisrSlDSY6B8Qo56YWWRyysTdn6JJM
V+cYsqaNL63NX6LKoHQH4CraXCj+FwTGbgyiCAvmd1Cd3ulWADAY1coJ8FeIbBD/Gvl21pO4HmSY
BfkaT5dupD/CMvUCrDSouI2GCqSAI8IbLzaQ8LxtDm8zv6gEpvlaJwwzl+e5ZteKQ/3uPP2cJECh
0CUw7kG+pP07dSXgzUmq0vyGMJC45+lnl1lsyyrdK+hPK8/52iBrJprvTI3NEkpkp9DlgpVSSlmQ
Z9JOZN+xI7cFHB5ZrBJ9M3+AuiRmTFNobPmM0PjMhmZQTr7xDzcdnTpP99nRPnAKdPl+KPabktQj
WIidtMhmTgWrhkNafSdYZqda/oXXa8ikYMAFcuAOsf5Zesqe9V0NeXgc6ZR9RuGBLqUxXqXs1t1H
ukgTMWRWwDs4fBQ20L8FjIIQWDTp8tDKW1u46GN9CIWCz7nDWVGLBjynQkzQQgXQVSXVNhoYBOzX
gL37bFwx4wmc4IAkj9Fys0ITEUSqeWSS54iDlbTfOmTJeJiMrxXJ+Pum8DwtolH4zK/fj9CNq0Rs
2JmC/cwck15pUZAEm3pWPwkgyGpJk3dhmJzYx3QhdN/W2jl152frThg0qnsTAyAPEWh6kr+6sXs+
8cE5pyGV6KM7U/oBgYXHS7Ax6z5wVIRxxLUDlBFFCQgKCVajSZJQC+eH/7AObv9EX7lNaOCWH/YM
k93Es5PBrfqw/zxQlTJdPFy/yNUF/c7BF5c0VD7FP45KzHeVMEe7igXS41zU4RGIbfFv5mQGJ7H2
YQaN1o3uvJrYUHecoqIiQD4F0AEsDgdze2Q7BF/SHaJAsJLbN/t8Z3AFb2aEC9OxyUfCUwdX0GMQ
r1Yi5/qcAmgkfVZTEDvQ7xWsHI7brLY4bGCmiTtma03QEMZ1n3G9pA7SdLNpdcSWT91o6NQwrTgK
nEGIDipRvQVOYiAeyS+WAOl5mS2ALHKcAH7h/48wJiFGJ4BQLyEGOMqQQrT3kL5rhWb66c783lU7
0/xUe7bzixI8/9JSLd/EY7LYnMDGpkqWCRCzZvJuMm2jEsoNvRd4vUbkq8Uxk3XlTco6Rf/Oulev
mvouBYQb19WSN7fMUKxI4Zzu1AeOuVds9gNPS6XBV0rNTTqxGnvwFHS8dIUQnbXbduh6Lfo/SaEl
355IshUcDlcW16D/6zKI6QLn7cFOamLGmqvItLXCavC/auR6tKcR8QUHyeOxM/8R0XKOyMx/tOVv
cfgE2KyYWmMyi0MNNchlD3IpNcF10JJVnAYR/Qpm76GvK2u7dBqwvxFn7ZghqauAPd+pwYRp7XDX
ta+uVOTy/HZL4vULFSp4uATq1otfQDogGJKuxOIosk0Ph2c/RQv08ieBDrpZn0+k58sG/577Ljh5
zkU6JdUQzN9M+koD12PYmNnra+Bqo4Utx7aia+5TSuaQ1t7RUJZiU6bZAZ76SgGVxCMYhX9U0p2L
tkaeeQrU9+T3+he5djI0RByZ7LpTgd6D2u+iJHHG+eO1K4k0iG94Th7YA2P2mnSN9FaG16AngWgY
gqxo7SiBRdIvdxZhYMomtGmw8I9ukOuT1LnRxoccrQcUKsV53JfK7KMOorVWeJbTDuGA8ZKupvCM
N3Gjfkv+ta+f3cBgk6pnlOL+Ci/d5ILqY5UPvAa0fss9ozXvr/OEY+6G80/dLAnVp29PRkihddv5
xGcCBX70ge6phN/UiSX9WQDx7qW3Zq8CAKCSS+HGjIPMhobg7aN78HlBO8mzWaWtyvSpucHyXe1z
q2dO1nnGibw05iSUl2L71JU8GBrD0GGEgrI0Vb/0ZS7sUV3HrWfmb5W9it5XGYhkMYnjTOwxf15J
dfG2wdIECPCPs8Rvelof5pJ/Cb4fTCYlrrWYV1XyNudLEcMGRUUffjKBA0bTGt0Yl3WxalOHiRuU
MHerOKqmhK9wlCsrp3xGMcneDYEybGAaWOzuyTEjqk33p+88nvSzEt1jzE8xqrh4gDGwYD5mTtYa
Gv/3nkJyj2O0ot2EKslBYbzdSpPwugn9vfvPewUOLL/PffR5ODsKiI5i5t+FH/N7W+8aQWmhYHUJ
/kLL9iSTo26GF5Cm20Q9ARKW8UTHAv3Tz254fQTZYr5Ipu0juql//oxSXJZd9fdpSJBonf8i1TOw
gBCGOnlTFlak8JqVG1ci41Mt5IVQW29Fl9hi6fCEUD3KYzejN0/GI8bedLgdiqqAfja0qyVwY+Ai
YaAlXPYM3kzHtdWDm5tqyAqh5yUFeeyxe8kMw2RzhvV0y1HuMlr7WKsaRimaxeEkEf8IUlO8L4wy
1qYuubAEjyopGFVEoh7dZuSP1Rdo8Nxd6975J9uByGiZmFQJ7Co3zNlqlgWqlg+OgRgcYBQDOmJe
+58IYEr5ZNd1CH/vNW6z00mRB22exJKXBwY+5IOke9ljzCir0zdMhoJ7DlIJWhB47m4Hc2ophI6O
MlOlpc+d0fOVIIYV2rbbTwOOvrvLVVuNEnrB+PHkaalD9EkxFG5kV7J0fDzbkN1HR+s/8fjul+7e
VR2mX3BvWeKeTZnZAb6VTrJM9aVE7fzYngpo97VB3/0/mPzOU8NAPYWaNP93KSAxqeBf1s8unUWs
r7jsht31zYa9UGgKSEN0P/wOLdmYeforS1mRF831YSKZn0ZjJ7kPRhURa6Zg3+ftsFA7+kTTWHj+
ZOwZF5OITzOrPcKnCkvspQmgLxqkUWMBiYYgV1Y2y40uHaM5WYPMtDcPEhrg2C+u8gboONoCE+0k
AzUKj+U0NCWI7z41MdSS3+DOzmUgELSh5N8o4ken4ACVrzTm4WLv+N9FOORTHN/acrFTxedPhOJu
suI8SFDWfIWdHjBs+3P3CZo/DmVIFIs7rJD+bk/gDWpWl67Nzfxv2wZscIAV5qrtP4cnQvmnnytZ
nNilYNbZPUlxyrtjSAniImdyuCnFk7al7AXnSRoWWWPQWQ/+8F0+7KdrUuHCXT5QsCm2zHbz1T52
c0icfakz4YGOfhLRzNYiS9wuMyD4lPFxRNErbg578VBUZ0aNLCZ5eyMAOieGuPTKzyP7hswqn3Vl
zLX81UhYICoc6F6kL5CNNSVN4BH+txsQCC+sIN4knq0JdBJLmHt5VRlRxIplwmsQFxyxiG9FUqiL
1uTPE0C3MlwuRZAY6m90HXpE7xQeh2vjLm7hPvklT05SAXws4Hyhe5ImKvBjJKPT128Y8ZAEOUsd
IJJ37ixkdIqTtKqVzdcV0PK1TO8HvsO7HGFaHG3oPnvU4sqrLgKalNpNmhemiFtRDpLnTI/y4aDz
3WqusnFbaO20dWNMTGmejOFNM+Kk2SlvIvvIUNXOogzhszrKpB9mVJFQUdC1dZc0sT657480Y2GK
51sfrd3uN7V3LyVwaTToXKRPlgPngcWNLUHRrT8SopcCaLsY6Gb9LI2xg6ACIQqUya1lQutWA2qe
zqexPzjQpifH9APyMCbgStURr8/p+y6CL1kDH2+vs4xKHX7Jd9QPNsp9zJo7tmAz4MLJQ5N5xJQy
j20D29qPq5+6XKXXR9M/njoRAKNvz17l5LNt5Mncni9rFc42CS5nJg30LWB0H8U8zg3KoQqQLO5L
dQ6RtPa41QTvryEGNvdf0rjDvi1GuYihbfFi9DPUVy1q0XxBFiPp58iSCGAq9wgA40tOezalZAXr
ev8b1eClbF7ZA/3TpZORyqSiD/j2VI3lUItoLtJJ9GMYxPqgOsgp1gSCcvWlBdifw2vhmyrBb3TD
bNnhvYBbmv5x/KlQHYlaucdVfCLlDdYTqh3ecOTmaT2aGMgY3Y+FoWS33weW0ybe64meKTDwN+hM
VXbCU8Y6uFwyeWtYHobhK8JOL+Uzqjk6lzOEkQsVjwwz6Jb+E90u08zoWfn85lQIqunXFad3rOL4
TWUa8we0j2u1OiTwLxVEXvmA3aLrujOGa2i4bZmXrGQEnJpRAGOTDsr9XK7o4vPiXGziBhnOH7fK
LMlOS8j0OVY6BnhcNYJv2Ep28qh+owK+2Zo8hJDvNBGjOlqq7r+pQJrOMAc+uFK0uACfa1ZqZHa8
8zrv+HX88OW4/TwpQBMiXZXgfH9GcWsjtPUt+Sf6jAxRYlgHcoKu6aZ6gZYtbPr7zKqhZ0lAWbbs
JjfzvBQqKQOmBI9+Kvq5pdmpVQgWJW/SfnF6+sZCifCIW/T18cjfbAuaHdTLk6vVhJePx6zelgzm
U52VETWcaBvustwKrPTCelx4we7Tf5L5fm8yO9as1Ymkq9HeTcCGe1zm9Em8Z7MCoB2W/zxNrXzI
A2JEOmo8+JwzT57VWyXsdQF3+g3xD0emAxGBBmYPZZ7g3pvvazf7pZWEdWKTofw9VNmCsoJU2vjS
Dlb/+s7H20QNZFVJsTohW8MtpjXw3M26ptL+0Dcf+4U/nytT2Yu0bLWDj2Vn3B47bx2FO6Eq7CT0
zj+hpQcHdxM2UHmCPZDgs/QVlCeSf1WdPVkhEJldxxPOwbuUIgWx3f5fFRzbcNBd9Euf1QuG6TQb
b5ns+1Hr3qOQA+ImodWDuR+JTwJhRJ0JObhRGakKRvec+nNEwTH+yunyJaqfYP8c2RcRqZn8iMMB
JMldnNbol7ZAmI2mBwuh8N1mfrwXUmwC8CU7tZx5O2Oti4aA0pe4ItAJbni9zcZCmojAmVpJMg1R
Zb8GMAP82WVXQmuA0v1Dxku931eWpq0csI159q3CKTdcbcM/5WO1topzyGsAyF+3zBxbNSZii0Cf
5PffTkOtSgHQGcEb8IAREbVWkJIjbVZkdMxJPcNzDwmTpPR1IBtfeg1+B4b8sj40t4I3UyE475zz
6+IRxr6/GQLfELSla9Qmy73lNoB2s/ilgvaZUlLduEdfdK/IDUrwc89/TY2i8ukq2slS5JHeuLyU
HZYFv+SzKwec67QpEs3YBlqs3VZFGixByzWDZ4GMRaFFEkJt23/ArvmASTZqkQN6s4Tye3V/u3O6
by/u5PfaAhCgOnpO6E6fCMf41fzfg8bH3M21JFu9T4hNrn8tG/UFIWlRxTh3/RZ1jugyWBKbQ2NA
cfKtq0ZyfJiE+uKyCdDBzZciuHCBgEtHHipkO4oJXvFFPfdrLrWTOxm/+IQpJNHx3/xw552NtGjP
VMCRfDnsP1otgKAZxcyb86pGn+hEwSlavgEWQXH5SDABgLA3DS06gyK6SE1pUQjpM8Z5bdRJzb4b
D5odvRoM02CP3bGZ2XBTkR7UAO3hatM7hiMd5F2da+a7zKI6r0WBdE3RP9/l3jQ/vcznGWkRbvV7
jpN7lYxuJTwBbIKeZ+qCbFvAHt1V3aLkQc1y9enJss4gTZTYCv/jh3rfGSYrh25PJFFdp8CI2OfB
cnFsglEF/MvvCwmtAdeYEzg0iY5KIJ8xkNPg12RPtThiLoppAItkw8L7rwQ6RkbEtAyXPzOT2XI/
FefpotU4TvW/8V3XkqtN2l7KB3XEF+dP2DEzMM4nTUGKKapIpOdr7WVnWKTRMuA/L84h7Y+pVplE
P6QeBR3uRVAOZjKrbfGDvAbEm/T6V/jNLxASWQaucUpKJ88ggNwCFb699N3zf0ZCre9jGeJs2D5X
yyccDf7rFIJOT8ZyOG2OVWo839ty9P04PZerJIo3MgoTZZRF7zIAabUCdrunBj1/OtVUw4JT0dx0
vZ6R/ohTMxAshp6HsbSEdTuGiccqKj8Z6n+nmVww0uv0aYV8TTgrxiciMjq5h8cuw5ouqbWA1iRx
LXNB7LYR8hZNL3ocNGOtWKLle0aFh2ZIRt2ljCsKl7DQUo4kJEA9E/fFxaRfFgJDm66q/M9hA5oQ
klGcuI7zhu745xCsUbFm4Nvf46LzMsSCtlPT+lce7n42K47ywrfGEI/W5rDfNSiUne2RFLApFo37
lrhONUTOG7sFVBQ8uresZvGWbb6i546p7GcVrgmN1x02Q4f4tfL/rD/a0B03BVTOpCCjZ/7QaRFu
n4lJy+Q3t2WWGZzu4kZ+Z8s401ygkGdZu3PKfS6cglvfg/3SxQ7rnlfEgGWKhFo8jOCIvWu6cx7B
Xvw0bhgof3XdAFcHuZ0eBLerWfNUDtUMcrX8VJ8DrpuwgA8RuuASn2L+W+LLte7nzvyxf4VbYF+/
+BkyhgOIERseWlWlr2KAduIrYI3jDVnTqhqpaMWOzMtdl4tnp3F+qc1bPmk1tzQJ90vd6xc+tJIQ
08SsLlCXYfRF+Ihl8W6DbQWLvJrNx6H5C32k3hF2SrfzZ09ZvfC7DYRy+GnNOA7Jl+GTl5RdH7OX
R8N8Ppfx5jJZFy8TopmTaIqKITSL1Omc8tBlTwdMTX5W+q0fqvGClbEBdtnNfyGPCQh6BF5hWQxL
pQy+35SYhV5ZnpjZ7ZLF0Q6txOG2e9i3QgMcJhW5w4FB/vwGZATt53+qwhLjuF2ON4/6wuR9ZYCm
Zcr9VU6Vzszf4HNsC9Z8dqFs8tx6Bbk6UVNLQcfp+mINNaolpO9dr9vnSLZa5K+glPK1sAcq67rI
z5dId7VMJLVAw4r49RViWZbBjfEl5hHL/weBzQoq5KKYQHUmXhk5j2I7qjWcKHyzoY9AaCh7yulI
hKGA6ZXPTmJMN33GecktKIVP9Qp34ewcrARfC6y/8TwkZKYX94dH0+GQVna5GyeoWCVkBl8AMQeH
alzPikmM56fGruCMnQ2eh6HPJe/gD1m/vy/lE4GvQi+m3+xzsOozYjQsMLJTq5FdDb0aV7zhKEsB
c7o9dZiqa9vKArz7Q6b16h4iTxAxC5bart8QRsk8C2PFObilrCbN2SpYeB+Nc5baPxrE1ND3gDIr
qxi5+U0bgTzbMsK1L1fYR0IMjiqccGV2YIb6Gv7CvQadMuUc+yaBtbXMEV6x6z2bXXMz0KgDN0M7
IYMQ+m8OQOMkyXPJmFKxzK+tunYElG+FtVv/6Nq4dulFlHdWkifYnTzW8qYe9ZeCyuD/gM7s+k7d
E3E86/NAFPDLxFRtHf5enkqbgY5xABshteXI+5tEbBncUMjZURiF69MSC+WHOgnsiCfWh88qBvJk
zGnSLPhqe5/o/NQ4ZjJVFXwDh1PeP699W1rlz2yXS6frZU0Oui8e2kmxQTKZFCCJzQy62H76YQ4Z
L2idgn5p00PAeHn8HZjES56EoeR+nOVqShIzE2azxoRimh6uXKC10ejqDflpdbv7cxhjoLLhfetz
w1/ElkYvvVQBUj8liL/XptDZNfgbfDjC17XvWod0SYPZxInptVqsQJQwZ/2HrUronFA+PPZZXi3q
zf95Eb3BmaQWZtU09D7tU24cs8l7KGNkJC+fNKRz2x0QwkzkU++oi3jjaguzKHZJ16UEOCkhd6s8
qYwHDD4EPqL1gY9rNUwjRhPa9WTykoSpn3Rh3E9D2GH/50e19nsga7/ocvwBHNPwdsaerea5m9vK
tXt3vPlHl1ZU/0f4AtY4xiFodSxO6vVfEBiisTd+6uvLwCd3IYIb0a1XbQi1VRoZTY6BRv2qR+jr
cXe/3Mh26lIfmDbpy9a+bey47BmpU0XKNgi9e+BlaITDNhg9bBQ8ms+ms14QyX7dLHR9lIIlXMAd
1St7K1JtJPTEHiN9x5nnxfUdm8vx8kqDS4T0DKT2jvTj2j0CrYqMo0FhokeGUCRSnhLUaKgJ3c5U
GbHqLdAJpuuOls4mARAFSJ7qrXr6YiphZFNHnQQray7E8ZRBeGT9cdtlMUzf2qxnHZdsNvP5pg8e
ltzlcr12WJheViSKfkMHdJ6GSBNlT2WWVAtsNIYcxW4IjdW8QMxXdKQfLP5bMFalLhTmMQGihPSO
eS+x3KYXVYlBIPGJDHDto3MoiRGZbDHJwWolgDkV8l0GmLoH0Mgnpm4xEK6XMu0ihZjO1UVPnO2y
vhsS+2/i7I6piqoecvHfk410eSEoQIzf3coO0Dg/SNkNkn947BW97F2XmDOKAp6ttj6b3zNfWrQX
PyG07p+iv/h9NERrk2c5AtKCqcx+XMn6cdfxcvcKhIKRvnF/c3ScY1nRIL9/qQkGOlX3/L4RBAwg
iuMGoB/wVGWmx1S8tcYc+q31bo0DUP9onKLaDJ0SE8xawFOZLhv+hg9WosKoYoYzY5nuvHTau3Ho
O7XRtG/sa4xrOafRWqKUmZluhzP/C1S/nzySZObKD8jFuWV7/vcoSo9y4GVxXUZfipNyU9V6Oa4H
AObavskz/IU6lFCWr8qmSX0DAZzgMwfnhvIBR1VSFtRm9I/VkLUn0ayhhvnBQ/rVlfAzr5Go8Gh+
3gvvT2SjOLeLQFPlhp2pOePTJ1c4lpata8NMz0OV4HGAuExx5YpkYxzp11rCsnrPT29Hs8Wvk9xS
LE8auHHY/dX+xJw3dVct/IhUIWcZTcjtapuS3N1XZYi/7cAw4+0sRHFw47UdH9M8VjY2W0+dBmse
s71EsOWRAZKBe5inBnH9kqY6PCF4V9jp3+8cfHgIXC7JMFjyVFmyZjqfDm3HpHcre4oom+9Bkrld
mmwVVrlzi4yVJ6AVsZZvUho0bh0W7VNHKKkInPBImMh4RhtYYeNAvSZ3BdkEcw7pWssU5ZYGhvZ2
rQevXqGMbDOdo5B81SCDY47K5dX+N/wJiu/NgQakCLogKMHabUoc+nNbpWgcHzE8qcXsLr+TS2yM
/s80mkFPNLdecNBvzbwMLWnEduMYvIsRZm+GD0ERJ/apc4H7/qaGil3zbAqGprD2f0JxqxlL/9Ro
dGABpaBJPIOD/FN5N+Xl44GY64jPg2UEVVnI1KtEZMhfus8+0sK9HcqZBVfGA8iRxxleXE9FztU2
V/P2wdq2dL+b5nMq5rG9tbiGUayWbN8DjRyRbwk2Xi7B1yuvwTxacv5SplPb8en+uje0vhtgXukg
dJAfyOGty+bcF8dnVbYhMZOyoYZoxLJPm13OJi0OzDHTSTDiTbVPKuaqeYvNpmJnvJrQLrxZ73ki
NqAxpFyeK05nDbKyELik+JA7IwejaqTK98OWS28xjxYUS9ulTWSOQmy5QJPChHQadcPg9aPa4UAJ
N+qxIMtZuRDzfBE4uF5bNIzdI2gEsyhjiSiID6tofZ5BTFt7Kj/6qOxkFQ6me7NNUD+QCYVVGJXu
kiNjswdBO5rD5VxZ6jL98QSET26yxXQRaBOkeXqbQ4bqDDxx3jx+I0nUwcyJXfqQ68uIYFhd7RVd
YDDCDeQdHf/CjyAzpbNoS1bbY4VMZp8t1Yud91mh9zvVa2moLvWxGD/IDaO4AL9bd+h862KMz/HS
WHd4w5RLo8oEgk8vh8DGX7Thdc5wmiO+LSyv1Yr/pw4FUqRwbWtknKZ/k7a+5SeqgpaAZxINqhXM
EaNN6dzjfKVTpJw3tPt218LZYPNsTE6DcqCIjZdksSfae7ztSu+gEUztUdksKi5vRe2K9/OYV8sj
AOsVFlhXCRNGAQOfE0NkYql00QvkBX/t3ZNRU1jVaL8cm3agXNrQECVvm+0dLwJkXzxBdZ43jIV2
okl58zoshmA+ThObhQ5VWdKUABBsS+dw3Ltpn07u9QAoe2YjVp7T/LdZTAxuUMGeASCmWslv5RDC
e+fBFkRi0/0xUW8utenXV6EC7gmnuk0JB9/Fz7lGcwosPr/rS/yh0V1Mgm8bfJv/Oezr6knj7OSO
CFpq2KZLjMEAL+UR/DbW1DixKwXLqz35Rb56IlIihHOtPynze5RXJsJ3muA91Luk1+efFe+VO1vW
HoWFsmmFPfC4GJxnVdPbJ/DiXChasoO3n800XWNIht/jUSB7u6Krx/OOsMZxwkYusNYjHyqTVlTV
IBRJ88GDfwdb4mGCVfJYwV0tvhIUY5lnOdxkA+g/q0YjJaVycsAZgB4YcKMBGLTi7jCn2eYlqEAs
pULO5kibqlimvabsDHRayzQEKDejlyAg3D+FJrXbU/DBgAPw8PNvdDpQYPOHmmeWMt5vPmtghsSq
lr76YaXCewCKdS2mlUmWFK3nh6SC6KwQcnkdCzYQuvxcJjs5HR4OdnSfVy32+tzQ0eQxeN6e+99x
/MfyJgt2tu36oeamer5orPZt3k+Xte68NifAcj+5I1FBOiUFqpesy3SuUdBzHtLcz8/dxjRdoY31
QU14SzkTL/HAcyk9OoT9k4iY72tabYnlW0uJKaF+jmJruwljVFPnugAG0IDOhp9bzulcORDrJETf
ky4jLxE+WHFEGJD0yJDGgYhGuhtuRZ44UKAUP4QLBds2CGNbmvhC+PelFwaEBfwHx3X8pDEa1b+7
F5M6uKKrZ8PteGlmiRHV2lsveC9rYnuhQ8xp29g51fwrqWyajMzgdvjWwbwaG0lMWy34C0jaHQsf
jGn76w7tdZw1BDC4rsBUjhH1lHFTLYKAnfMQX1XkTmdhKaV5O0QethF8gAKXGgah+3VPSGYpPY2K
Zr8ugQVc/ds0aw1tVy6ByZIwFJkRRjaOjqUHluDEbs9Cp4MHZrNKvOVBzgleRrB2U17NMXEWIfID
sNZh3cdWdCT7+wkQANF3dN2lubyBssd6TvlNMtzID3bMZCMOwIpna2hQKX5FZB7wMDz8mxAScIeU
MnAW8HsIaRKL/j6KJqNNyF3MxpoWq0y9VmaXg0xHJohIqfZ9fycPSn4uyitE9igKKqDIpl81A/9s
Hp6K+/JNnoJ5i45N9TdT9ggNHBDZYp0xGq0nKSTtyYXXpizD2tQLlVkLC8G0X6KUZSDE/Js/5gj1
94DTBGUrA3Wt7PvwA2ZWVo5GQac7cINIRxcIW64pVZx8mmnwIGGg7J/2kA0fFBOBuX7mlCIInmDC
soHOkts9Xo6ro9shtJ1P0MMGTsF4fxyUjs4FLv308LvHGyOb5AR+vY/Z7mTcpR6CwzmHP78Rgvvi
/L5ed3UUlQx65F/NFy/Yg+fY2BodqSQhE55pYyb9SAyMzcJYumoz+b2sD+TVp76/3IJVDnkmJxsp
V6vyzhbKmb2yQV9BVLwqXkXQuEYpcX9GW/Qp1xQ97Wnwz3ohqTjcPmGSBvyGvhdVscGlc/ndzyaX
OHKE4Pf/hQdsbnMk72KOYBZzuS0ONKxM7kS962BpERIcnDaPHY0eEeYgtMj5L6icPy+b+vsFrdoj
wqOslZWtYz7UdDJKOfwqbBemTxPNzhfAs6ZJlRD87KQr2y8KXrup+uQ1JxFBCTMtUEiXmgbZkMTH
kxS5ScFzvEhK9pSc1dY+D0dhT5eMLZ4pudxP4tmnnlOCBQ2xuvt2j22Filz7/+NasDDGV/aSQqpL
PwFixaPpcuS7P9AbVM48TCxz33pcuPNcVIDIwTk0AqbUM6qjZm427DVrod/13kHYhjtrwIwFoQTW
STtf2Dox8vhbjkqBn4e/0A/Q3Mhz7TZhKRiYeDu5DvjsoXH+gzGZJKYD5+OM55/QaYSZnBuvLE2p
m0uEC3xFEANFBmGnheiewHA3L62a3K5CaTUnI4dcyHvCNDxvYNFJC/ijgNTvIWYYMU4oCejxHdLH
jauWP84zfnWeTDNgZbNF/qznq29xb4bPsvP52BRi6Tp5sc89pbxEWE0VLQqo04w+V41kf1gZ9wxJ
8QvqNyz/TS19WRStaxfLyo0ogJSlKBfjV8iCc75Ej/Moe/pSKMB1pNO07292kEYezpBgSn8Wg2Ba
H/LTklqSBs9/M6cRyDWcXDw7Fs7FRaYiQi4CevKXWavSuwutf3QMu08bzoZutKoSi1c4fnbc4DdZ
0gNIIDc8rdGU884Fp359U8c/f73qXzgCdL1uEgXzbwkDKHhdNVKYvIuSmsgO5gE+sQn//fq0UiH8
m+ab+hPfMwBAdUiFd4QRaq+vbnxvMvttm5oCO2CradQtvwYMAlK8qe9DO1o/RbgB4jbkSb4ERKDN
M+XdiNrtrD27A1n7TLkJtLCCgAn3cmrrnmpEvMb79vdRBO9oPw5a3y76ELnJz/IZd1UsgJqc1Joh
a8O1M09QMYkrot1zTXX/iDxq4QED0h8t0DYgzSe896q2/Fyo6NnRYknJT8xdHXrNazizSZbGnlok
ymOzW5QM7UJlUfSduiZupLazHpeyv4Yb6P7kl1thfMwfzcpfnPzwXYHUn2u3mr/lXX2m1xUBf7C+
P8yPleTwiToZm74Mg94YBU2tbYpMvMC1Zvv27fF8ispYmNLlYOAbmxCnSQYvzbQvG2YnmMjJ7Oa8
V2+e8n6cu2oPFNle9Ky8H201aIKZkD3T81pqlhG4RtYaZ2Ifo42ckrRsO3qoTkxAeAJmwSbP60Cs
gvitWN8ofVTNi6u4kccQkWBWWFRJRtfz5ssdQMJ4JOdguIrT/0ZrKVp9S/h5d0hSQ6moKD4Azjj2
sk7j6yzom0EPP8/3/FjJOdPEUe5WFK4yD9QbYmX6oLB94T4H8/93G+hkvWynUDqbxktjHplYI8j3
ZSUN2I+R6SpdDFUHI53gHAmnfyDiwD7hWJrwgmNM2Ph+A9AJ3YdiQ3TZ12W89omnMTZqr0vvsEdh
FR2l/RuaS3A2MxvpzpQcmDU3ZQIs+miEUTZmGSH5WfZqmu3jJVFR823FP8YHng3s6pLu0+EPuwgB
2nT6BJ0+1xc61No/iBNMpXOi7KVyiUlUQ/pj7L7GILmOIAfeyZWxw6d8QCTWXnzcfC6fRAbCzqEy
QIT/eTnV0ptqQWpDS5TkT+LwN20bEPAIFywzHkl7AM+J1KfTOa+knNxCwyZftq8JBWeHlL+MS2MX
QKnRrZnjuQHU7a+SEat5qG+NvDeW1iaVfz/NUgcPRM0ONQ7OmCgmjFbSXGQ6/IxXwJCD7YG8kP4+
pGnuhcg9BS7if6nzCiOm1wmIcYiMBvzcbIAh+cl0jkYmc3TqV8zSKAJC96mrCnlr90LtF9cjSy1g
TbSe4fP/dFv45ZWp2E7I364l5Uii4squdp5T0wy3kCS2JnPZIPw5JHNhlsnE1Nva/xLSXs3VQbEX
0hP/iP3JYxxiiLHeGa6mxfmgaKxay2M4pCOcNXt3/tMOFTnSNcLitXKA7q5O0L51LW6KML3xWW3F
ueBM4TmeGLtKWWb+EBtrus3tDv8sku5fSBoguWr1blfdfYj9yPnPTepgDX4H+jqFutg3BJtjDJko
asEIm5OacipAO8Deysc6I8EfJ4mFsAXtccZzl+i0BwoyjQObrgVZKS7BgDA5sN3LKtQYT7tXkFj+
0RhLP4K1FancXwa1jzXaitTsNxuYAkKGg4pLlGPtg4xZlo5l1gFsPi3FJV6lH9mbpJ3vaPpifBoZ
LBB1VEKPaJRm85DTul7oe71ov69+ndvzRyW8x9dowaM1aAJX8I3tYlN6RdhqXrlVZIQTJ9hckIKX
OJ6WczxPuBfiwaTtWYSh0NBLrZHN5b95lcgiMZuUYdNkGEBvp/4cJeLLfKi4hOB+ibnbto7OFo98
Fvzmw9090kkQLz2DH3As7lPdy6T3o/jQ4jjcc4emgl8m7FRrb1XyNaw/G6xMh9WMek5vGdlGuH8A
1sLNFmVGjYbVH15dbc9coAqSq89qO5CF0ThNgZrQJ2lRb3tQg4+RInm0DFaPDmTaN56ornmBrn3i
j+pZwlvQBtNKy4xAXsLy0wsKOn7tbGJFFBXmoCxoMvU1sdLmMHb1o+tAPtJMqXK36IQDnRN3pTws
tWI9763+WLCSoGHIetGPz8yPNZeIcKHKGt2eI9Ff8YePTGiwFnp2SoeQe3x76uoARaEar4x2QU97
uCZCIMp86mgkwRVTPX4WQIBkh/E19QbWcy8bfrp874g75On7JjFUZGv7Cl7bW7cP9rSUAE4+DrMo
AwxXJsd34eG8FQACP6JQDs3mm6Ax6DxRk29GeAHbShUq3W52j6Et1ls1mmJVxLRVbp5MksGcIW6o
LVYx44jgMi4XRxpvZfAwWF3aPMSBn5LEHWJ2BX2a45R1/0vCv+8jqYmFO96FTO8r+NZnMr/LzUnN
hHquPG/G9VIbDX/lpLos0oNj7yL+wxctGd4LBDQ2Iex0zKg0wlaRGkVqSPPA8gFA90f09dDmlNd2
W7Af0smm/5bls03Ajx7tTu9Rca5MwDXrqFBFlp0rhSTV53ADzwCWuLNI5josVrPgq5kapB+VN/VN
wFgnVmRju0/VVgBLiRfs3+HTIDrL6W+ibOG3y/yZwrFUrYi76s2+WbUxVM2w0D6ohJjAU59BEOS2
lWY8sXWSXQy11PrdaoX5DWtkXAC+wCD36qieTM06caq6gKxDObUNG50q07xPS3Iv5BEPG4hW7IDi
vORiDq9EZZJpmNRxE9nKNgoyqD5x7o2vVH+Q860ImJkKbSCKP6CqVzbGyPljEmxhLVvmR6TIUpC+
wuX5gzQ6WlqgaXz4yRBHSSnKcDcq3E3e1gPkzHtXZg9HdYBbF8vjUg6vLxZ08hYux5RAOemPIIBx
DyKh7ZJd2oJnIUXTg3kZYl+QuNexagiH+qqiVIptQm4nyEtlvNuWaY87sLYHdC8sYVVa/ttEm1zA
wZ7EFm0ZPZzwk130I6rwPrDUcNj7JQQrVWoFJ+oLdz9rWB5eq8AimbZXbxQ2Vucoba3wqNXVecmW
5t6Pz4+tEgt0VIXp9svB85whstEiq6ur4fvVsl4fBBCxsmKeJn9oyo9qC+NqnceRtjg9s/yFZDLM
8gCzKqpWK0Py5RgznFbEe6EOI4RI2suouzM8jP8Sz2hsLW/xSQXNHHpdz+raVLyZkz0/1B4Pad5Z
O8K7cG7sGNovcL6TukModgI7LohHwiKvTqfuZ6HKlvM3tNnmNBtoAlxLHlYaooRjcX+tNipVhWoL
qpsx3jUfQUk7p8mihGT2QHGjoGwVTYqEAz0INfId99eiEfhhJW0DNDlJKdYR1RoQi0aV94K3k7xL
MxNasNmwzq1fY1EhblL46yjNEXuNW7gb0yPyuCtQPZ6r22vui9VEWvKdI9qekctjq+/+/yr80Sf/
WGEPFqN5JQrUfHQ2THvn3V9ULMt66Ztse11USvABkxk1qQET4+w5jdHYBmImH694aouzLEhAZ0Cv
s2soZRDj12oTOdCcmnq2x1DR4fJJQ2wCbHwd8UAOAuQ54BGPf4bVOUk0YksJ4E5oLInbSuwZe3jR
EkLhP7Nf+HKkimCHs+MLYIO5N5jI6nU2PABtlrnfLeiW5JORFMy0fkANQuiKN6Iy2zP8WYXjbk6i
EUMNtFXC7q3OFg0X+yIYZgK1zAJH3GqycNPMeEXGZ2taJSUm3T8iXH+n+WYK9wiEnARK6H/NKtWP
zijvgrFqXOxnBd+7R1JGkVNFMKALLqZLKazY2A/Tmpb0iGMBxEkFD2xGTzTU4y5x8tSrnplG3QL1
xbekwHHe8mol6FqCjn2JCT/I8fNk2VAA2p8f1qh/g6hNC+oHaL4KvyYsUaFC5TpN2GmkAxAxq3AE
nvpYJgk0vJC0+Fv4mBsETIe5XHRIoahwP3gIrkFBF3RUYAsx8mK76bVkRU64GxnQAP8NSLNrGUhq
MfEjGfRRV1GBEnszfdIp0zWJDTaQ/yF1A07655oTsYt7oJToEkPo9xsiuBP3xD0Tzbz+OtZq5re1
pZRxztsg35eruQNPQNNmf6T3jc8N3JrRRZwQoPyPyKbYYFANoHWWCuLAxbq/KfxMd/a1W+ou1BKX
PikJxp2wP12uhsdvMQc5in/oT2D/TFlb3JbIwTIiyKe7UZ7lqgvRWEJdVMWWCFTCtzlHVQnc9/zG
lNjDBWihxIMz34E3V6+CyOxnb8cUpw8TDSUzP7+4domxO9XpxY6MT1Lzmy2KaL3BK7a1I8t45XLy
Z1hPiZJ2xA21EjQDpCnYWLNuQD6gZtGRLeBOYWgi1gkg+gxJ7YAsb1MPv34QX+JhLIfUr/GvwcGO
oqXqBmZFdTd5SgbO9+qpSG0ZYSiYzSYtQbk0jE0wve0QFVjkxbS+E5EH1w6fDAbmScfomOGZNyME
zu+bTMzp0HHN0rAjMrSeuZFd12wr2xXMupJ5wQR9YkNbpERhpr7udsnshszvgN3zN3yopDBBvuhJ
vK/j8fkfVPRrhb+zfyfkDZ7gUNn1jBbl3UZavo2kyEbPOxSjnpaNkoDZHXCcurwMtoxS9xVMeFxH
TxIsuHxX/ILJ3a7aSRGM5DBGuPvXayq3GZN8ghYZ7cTWL1aMMWLspBB+56EHWGFNxZde+pNfofqE
3WlyA9fiaz9JY6A4MM/ctLfObK1C+2ORCwPC19lie4PgSHRbrbNFA39vt9AvrEks2Ft6aDnIDzNz
nVGlvVynixrnHn7COdgjhtAWqT282YLL3XWVcF8QgEp+DMUpwB9hyeOLTSnYULvGwPdHXUQEEo17
zbq7WY7zri5PJ+j4DHcHaSpMY5HeOJfggRb/QaUdSgSqgEeyysLhXBmt157jgQtdaaHb/y93q5DV
yGf2c2/aF2tvpVJEEVvJzG1ph6IMUBzematiAgndzyzpIqiNZiwyCbVxkrV/Q26io8XwA9Nebj/F
BqYeKFOB3v7LicgPDhj8LBqaNUbdhipT79Iewaz/CjUN07dTP6tyZSOUrmVq6YVdT3u7nwcEr9cz
8dHgDw3neEv4jLLNMWTwhTAzde/u3vlOPW5F+cVytt/InVNbZoEK+tXC79MAN9MGJOpgO8yMHXYm
In55DsNLYICgr5pGcEmG9b8KKTJU9mXYlVKvfSwbEbU1hFltfw6Cv44zzESSD1b1z+6UnQENWMTY
PJpC9V75/9QgdYYi9Tw2EOpkscw3Kyrq25tp1t1qLzWl1jTEeuA4DwaYzPJqtMowZXrvk3Ml+SjM
6wks1XaSMFl0JsaNXEwgp2O/MFiYPmXP9QlNyU39LO50l7I5eCkyYhItTF/LqHbtouOrCRX0nKjd
HPouzAF4Ohe/3ZU5o13njHqGtZBn8U1zI8yqydIGe09mLpz4KVeyHRYNMSKBTL6YhMuNYOkJLdjm
ykgPyEaShXr5Pu45oh0aW/h0zlhk+x9Ifdk4l838QXdc0WXFQlR6d6eoGtJzszFHzElnpIDW1A1C
UwpkCq8Np4GieBkPEaZnkC42Qnqh3HUwLZ68Y8PyyMu89fKWw5X6Qpi5JqztcrJ8tzczt9xkY9Tm
1fnAcGrSACivxgYU38Gr//lCDIFDUkxhhovzAT55FxtNxwzUpzCmB/NllBzUxFvRn0nM4Sdm+H1Q
yB3e/Qtq3KoJ/jkcKDlQlFcJAVajL9Je9KU3qn3kcxP8vfN9yhQrEvSysVUFUfGWl/X24RE18Wkg
naq4dbxaO8SQMXoCuEWXj183K8OMb6PRmQyAfSarrr8w4ASdpSHaGpXipOAgCJ4p4HYHud235Yjk
U5lweaUiXuX1vGKlGKnHpHpfRTs/XV5gj9pdus/d45A7s7ChLPSRY7NgfioDeHrvq037PiPeYnse
lZ4BdQ50+WG8AfRVXfqvhl5WDvMTIlYG1BLC/2dKvlfeFikK9lnPswgo/fjQinjqrc1QvaKkHP8+
VF/+r5i2fTL8gsig/nXG0JZ0lMvvIpxFyVtfMrfE9PJwmm9QQDSX9VZW/RyEHhXX2hyG0edtfu0r
3l7C0LLIAZOMHb9FhIaOmCwPPIdHtC0pKs9yCO8xvxIXzsBl3WxzYA+mX0rh6UY4JRrp1i0rNz6K
tYaidAJq79J7Vsy7ZU/6EvFQ2m/TsngNc5VgipN5cepbogPSbgLRHREKXavS+WuqZpwlQqbT1W5q
tnY+E24ZXBY9ivtRj8mBG8U1kOvACE+Zov3+eHp8nTdJf3ghzm+YTTle8OLXd16xK9mH4Lgcewia
2+Zj1eZHvNMbv7DDJGkcjJMvlIeyt2NmttO3THwP56WqN9sH3gfjVGgeSd7psab+hF+QKefaVASF
OzwYx9laUgJWUWtNnVV9o2DzJHC9zL42PWuA4nA8IzQWIXkZLhQ9sDxXVbHw9xdoyn9AIDuDyElz
JGv891N+oB03a/vC6farUI3lFOQfL26SVf/t1xAy5EBWuDNuRO44fcKNkaT5YzIYGhVX2rZedNwc
6MAglgSpR/be8PoYM8vjSLu9bmAwdsMzGaeoKn5XLBaE2M/wdHUhNryf/nxftED8RA5xadiOQsps
C3Foi3jXgC+EGonGvuxt90TdBWqzH7M8K3e/wF2rFKPEERFdXWW/YoObA6qQMrKzskGpRXD1dUuv
eih+84KQkZx+cfFIXtEAfY80a5PLP2Sv1qFzp6/Ic2ptHLYeKvVnNYh2mJs1y9UZh4sVzAcNJbwl
Wy5HK5DG1neicmV+YV4D5AHVyZjUEKWCOEE/iIC6N10atGqP/e3annjSDn2eXnHVvqpKKH+vbf9c
hIkj6k2Xf06f82VR9ULqYrJE9fCOsY1a/GwpYG4veS9yZZbuDo7f92lodx+Pae+UYhdKNoq3hYKB
grjp1ygTdvhdw8g+LPvfMpTdwc/uZw5ZheN/Y5sKdMLdPScYc6wIHAzjPlvyp3Rp2b9VK8FlmaoO
GT3ISRrjCBLO7TF3p0sVpOFesT/ptaudpPB3w7gu8yDHR6OQdbGiVWJK7Xu4m4VZIGgDRz7dAZGv
zC7fsrEc0mo8Ojgt32i1wGLS0tm8IhraQzHFxCUwtR6nSiwfibC8Kl8butQzbITkY+VHy91mrii2
yDWOpQ6+VXlx/BbU7/Kak133RA5WDGW1HW55iDSGquEyFIZa4lZ+S0GbFcZ1Cua1ytYmJ78Obd+w
h/HGCUXqI5d9VaQrxnmndF0QSricJJxT+aGYN0w1K0Baw9P9D1MXA7BPZ7B/qdi05lNGHbbUpUDv
d1uZxZ1MjPccPunPTGtB+7nh2m0HY3BODUcVxkNEnTp0mgWzA1yxQMzMTAMoe9RFbrYlTqCAJaxj
AZ9AgnxzHoACJNN0bWPxEerbcrm777zzjg4Pd7SHuJy5GVPJPDCXKzVjRbQ4IFcW/OY7H+3Nc6vk
DETGG8iVK2/NgbGUxFfViROCgmQHXUJPmC1uraNV1iVqIEG5QigGwjPVwU6Re8dE9GeWbXyf1aKr
I8SyqrBOiJKFzHEtnBpgz73lpGoIVEbO4nhgYFEYbJZqD8aC3hGJIM8vNf5KrEeSyKrvJXWriWAA
LfDORC6p+O/gPWkPfZ3m8Oub3Oj+6bvXdTRHh9Pn9L1LApmMdMDLnmXVcB4VTfnEAt6oEtn/KyZE
iGedYzdzkbGV/sIfU8H1DncGUwHBYqL8v6OS3J0WCba8eYfzyAGuA35TaK0G3DPGRyQeD+bSEczv
br3VTWoBOhZaWCMsW6P2GS3T5HRRdyUfTrjdGiwJim6Gf3PcBVZd4iCq7+l0qOgvNBZlMeacwTpy
FyLzat8D/DIhCaOUUozRYDncACqSwOaut9MTOkEG5zAOsUAB5cIn6lN9QFdBGN2nXqerp4GYvPK2
8Il5AHIIugyr0ds8+uxVeifM6bGCs6leSJE58kQTltdN/2MJ6dXv2vLGXiRtBTSrAqOxZe2jnj3q
H/r8byo8PKudL8UMs+HHa2NhYqK1sGHTR6QLfoB+K8E96tJbxawjhl43oRPhOZ30G++LaJOCLyhm
jp2mh8dtyIhtARW/KXBdV108UL9jA5l3H25wTdwFX1xmVP1EQxN43BI+xkLTBmoclQO6cMRams8X
niPXeFXMRipR88KKH1nIi1EXo3HHVlsizDbZt6JkRpOhQhR6bsHaonaO8idfbXuRrwfp+7HFg7qd
9g96kRGzfjxhViH2wvR8zZvh6n24I8OiC66eX33nQfSf4J1+ysMWL1LfC0LJl2KzNQ5COcRAkayJ
UXtD20+gYXWz9mC4HRUAy3lF1eeGSzIqym3lg4L9f2ukFUIVDjknXfDYZpSRgkNCF0XvB7khwP1k
w+fcTJs7ubIdrRPrPk/0qimeXexDXawtkYHT6BksLoMSaYxdDowp6LANykekpJ1H9BHp9UdVMexv
3mmOr572lmi9DYZuqiMiPI1y+N5X0fMOfnFdx5gxZctj4/fWrUJkDJfyso/tlb0GdY4yL/2Cjw74
Oe+pXP8+5CT5JjD7NLDrQGj805hbK/p5bUefH8+9A3I8eGEoeBtlez8uCRYFJ46h48/Y1lm/SJhj
qdcEiU2kGb94HdqwyGRWdmzZDpvMLyX1/ghdsTfoBh2uqS5buW5vK8VuZozLCIxRyq2Xz0q2jBC1
YTSqwba1/nodJgSz4sIs+2mUoCe6M4YrTOl9mDEv1WBgo+vnAgT1Dvqlqk9Nj9GptSSj9+TloY0H
Zg5pAXzzvWMX8Ismz/bM629+VAqez/D4kALwbMF+lYa5zRotZ7nNkfgLjW3YMeJ2wmoEyq/z0eS0
JxLGz0xlek1aGvEvu/fsOmP3Hpc3R6hLqJ2ehAixQczq8mPeSK/6/uhhkEoNgaS9kgGR6H8qP7RE
6+nQObsY0GB9W+/u7j08JwuM2Xl/vw5Jxq8aUX1r9/B4kxjJVD3+MZdzzbutkvo8/Apemd21HnwV
9KpXIp+6d7IBGNwwt/XB/EZBM/t6sH07/Hjx05CVtH/VP3iRrXW33P9MwGFbHWcSW/pT6fuDQUuq
su+SSQX7q92qxEWIAd6ReJhwZX0dlXgm1bvP8Pm3Zk0R8Wyy0rKxA8NW42QNaz9acYVvNP/VaZiu
uBDbYY/sD8gcluii/Jlq9uJCTwK7AGvPKJ9ntUC3LZ3I0FG/vRd9y3DLiIPQeAc5bDuOl/cepFCX
hlNbSYW55MVsy/X5XESh1os+0jUiBXRbTj7u6AYtWP/SY2iBxlr4I8rrObVQSL8RT+5X3pjcRvTX
nHAA9yUMIS13eQEHWTLFCWQ+JIgXl1vswAmaB4QYbUtGYZhNb7cnot8tkCdf6hM3OO3LWSg4R6f9
oyenRHwt/ELkUE5GG0lAstH056IWD9sxaghmVbsr7uGGjn80xzAk9+3Oy1QX+cSXbHK2dgrgT06C
h3Kl0BDdqVx4GPlYLKmjzzWeH1XlS6XwAu2vjYDfxaKWzi4vjxAfPPpfTmOvYoUi9U8qO6IxgJJe
IboT8+NURfxbbfi7yKTThCCTsfFw5lvfsmjGB/bWc2P7sithMxEycvs0vCzzrZlbQ4PncEiwoy3R
g/e3dvY6wgfm8p9XgywB0RVTDBw/U3jaHrdQJGB8IeikkBODFDqv3d7qz+jve5EkOwg6WxNr684+
510b8fZtz8+LfjcDN46ZLBpkbpT57SjvnFmSqy+NsiR3OwRbCIyApgp+bzRTXQIAzlO+zPiyPWli
hY0zA+yEtiCMBmVOZWPVhvCf6z/ml+0Czal56dvFYkofmz32EJ8OYvLf+T71yDeZyT9mP1/T679r
FxxG2W1kCv20D5SATSPYg37HikL1QJoZhCmvxgyNbYs0B2B3nwO+IoXM7FOkjBH839SoaO6pJ+f3
hMTZr9m17Pp6xHKRomZ9LIbDbiSyEY0gFQcgm+UaqTi2UxdWhaRlDbK47gv/Vfa4c0V+zDxVw/Lq
SItN6xXj679K2SZDzjewTv1HUsgsVN9T1umo6plKawFlskZyAyeS9GwRc+PEKcA1bjeyJTL+Fg/Z
UYJ3NOq5Kh9tPj3vWuRM/6+RMMWu42eQJ8Vw2xRL8igMLPzi0EdEx7kD1CClGGYKPhaE+cSiE6MT
2GcsS4OmJ7qjd9E2W706sW2NDCbaAPt7nCGlMK6c7bWhHZg/dOhnpqoIPjuhcqcMo65UqMDaukcp
/8KyIMP5aZE4IJgP+OPyWUhnXsKw7L/DC0IC/szYvQfcapGh0x4iW7mGtOOa9eJ5drDWuSeZ+jg2
3JLvQvRWwhMTIKPw/fNJEZmDFHByO/XkmvtozyZPBoDacLMuvq+PPCCU+ilv7lYGdLn4LPTNQiyx
gSuD3jw4Gye9546Fgxk4SYHVR6dNbJfJLnp1HopCvuPLfcCa96yWT7EQo8qvRP4QvCk0tWzZ543C
+pdLQ84xjRIkeR+uNnkiM6q2qGmQYVBZPy02aIxYy00x0eEHxI2UedMU8puH9Ded1pw4bb8Vf35a
kElQzZyA3eZNqcaRd03mZlGZxHUMuxhTXO8mo62wU5/le/YvC6HiPxm281bg60kJtHRaPGgj/BqR
fZ4X1WZFBJoJvtCURu9rs+bCdYUqUecMPtq7nCIdEHO9me2JLxhW0alMi9nqupXy741ZqtTDDMex
wSeM0AkSdo8ms4VW6SkZr9iJ51VVBgefR9oonzb2Ev1v+c6qxkluv7bewWxArdlXPhaB0IFkq8F0
vIyxj7nbxS1Cscs+luAdWQoyR+OPawwtecC8mShZ4ls9KCrDzsPLbcGz2tC9cI0QIBhtQdNnuVIe
vpOYf/IyqwKY6SVod6VOfZ7iHhrbx9fu63je8b35OU10Yd+0u+4he9fepKxCIfr4ny/2dsgQliAS
fam5NV9DgKlmo+G5v/+QgT++dXuWjvmTR9q93MxN58Q3tg7KUglpHNLAF1x3TYrt4RTsjEH2iIOw
/X6+2cTbntHVAeAmae/nQk1D+mjhnupCZ557K0vmozXuj8D4/fsvsfwSvxSEdhcrNDj7tVKRggm/
PSxVoPgU/lrrnABFnxHIFFsyYTNORo7OvjfCwssfOqe7LWAgitRgMys4opsybi2DBs07wUlnFPOD
zWvg0i/JEz0cFBRlwXkzgUno/XMgf2kfDzUZd/G24KfRr0e/+2YGsPSaI8vIR6BHSTcfg2Xddq3Z
aHPi71mMhYx0BBf9tkxyMe0TNR4mVwKLZ8xYuNqwnb0l00hdyMemue9vqKxwgCM2EwqFiWhW1Upv
EOYr9DX2V7lWRujzbYTyASifVMIIPmXpdnQaRLJQp35XP6igXb9/UvXwefuLn05/+Yb8ZT4mTXql
P9sHXZO47aI97QTBbBB+D4aDjpN3cQGQSetuZO5RwQuxwtOGdxS3Xjc/Ge2v9a/QJg3KBqZ4sGUk
Qx3IdywshRfEDgK3ZNlpEfHXaYM7APL9Zb3fFg6OUwVcglr9+V9H0S1ufJ3rwmgGN4m/11fmm3ol
uazje282BLaiojZ5gxQqstPFhO62jTlO6k51Mlhll9vmR4DVDsGPpGydBfAeQErurVtOL5kSBGtl
DLWkvxRW1/NGrv6AVDEDH8Mcgoj4NRhd20M8+EHgUX+Q+OZIEGH1Ve7PDvbYqZCUpT5Da6nvS/gk
6LZRp56CT3UBaJ4kJuc8CMzJhw/twVND8IwBkWkgdYGhnhu2YktfxW19uAzyF5b04U37YNF8UrgX
jebLnQSd3aCOUpuQLtTB0uxNuXEl5J58Qs/qJb6REFuUVomFUbR3ZdZLLHMpjAiamdJuoFbslPOP
3oZrI6ivDn0DD9kDBDTxUhUJ8PjC91Jyhwqxd4iUtLukKHbr0l9U4h+Id6yWvLEv81jg8JVC0mfl
bdvol0p2bzMGP4dGAhud8oahQAGQAeJtsBR9RmoBmmGt9pHG/gGpjCwABRJLmfew3DZCNDxruq02
XO/6Q8qIYYdZ68kTUGrU/3yVXUQC+lmckY+sRz6zNAhMoQwlg5xvEboXeyyKS7fLNUQTspbBxnaA
7k6/5b752bKA05nvQrWGqugI8v6LnsZNWVMv1Lf0Ycvozz006/GheVkAQfqb10cWQZkKm6mUpuyx
AcMwgohBXquDTX9Gekxl6MGU837GWx4vuNdd2odDYwNumSw867duq29VjkBO378wD/ejEPfPouLW
Sxvlh4MVWMp5Et8fTFkkUa3Qvec44PC4uWrqlJhuU2vLM2XEGQkyLCt0lzhZyJ7sYm7zFfE2o1KW
5pGzdvgJn5pkHjgu5IuDiZcdbJDmsrcZQEIYI7EL2uB4eTuh+u5lIjKd9o0bh5/MC4DoWSAEmExh
sZTwThDwZQkgligftx+mefkrXDYldZUh69Ykf/SV5WJj7/UUEfOZP8cRiKdVtD+VK+vz6Mre9aYk
AUm+xDBHLdlC2jDJ22OPfVIoWZddwvostqQgE3qjbrZrwzYISXD0i3UallCGKRzd4tZHXSrT5Bz5
h1s/zE0rAPQpUHMY0BlM/OJr0glOfW7UlMf9e8B7EJWUf6P0ragj57gKSapd4Zr6lCdtzRWZppvO
NkUB9/hYQ+c9mJ/ZS56ZrIGUPbllntCmKx2k5x2xPJrjvtf0gbfnjJYbwnxhc1kT+aEk3A+x3AkT
2LMnwCC87Y4Nr6Q3ly5ONqMpNibLYC12ibKVbGIeidTzrZogcDz2LQw4QBZpUXVUSJSqleylaa6M
G2weTUxTkoXEbspopuj7X5B4FXbGRLPNHjTlhjd4YT2Wuya1DyO0eSordVQvEWleA0Yaua1y9oGi
3cpIBte+/raOhDsXElJ92V99Jwyync9ACHFo11ryDSmHonieBeBwTH3daKfYUAsv7o+mzadmdIw9
d/fdxceLmNA+KHqYHHITC9e5ivDHCyldoD7eFHEiM7OnGdKgLe37ktG1eHf7zlabPy2murR+YTum
ZbFs/If9WG//WHsF/SxDOV48GbnjzQVOGclI6WvGAMqZ/cIBB3+bF/HnvTAgEs13pfL0doGHTRiW
dljYpAGJ9PFNrLBmzf/Aoxx7x/JGxE110K/Mfw6g19NwlB/NT2Cz9k1b8MAIhEjHpfAeA8MK3jSv
QrdXoBhbfz4zO47nEJeYmZtiZuMHbR17O3pnPhDnmrjrVtQfBYZBlGL1XmExKRjRBfeNjRMgrhVh
LvfkW2nmzsz061gTyVz7k3lkhq6nOjUyxfWGozFe2vGUWpqeZZtbInZDe+WDka+8ZEBMGth+pKva
lzXG5MqUNbJOZpPR1VuYEuotdhxuAgp5+J4Fu+lfWd6r6wVQEc2CKMlrUnH8VI0KHVMrutqnTRqw
PLnJ5HKsfLscFJqdHaIjyCSRx9j6loSWD2XOYC4jtxb2mx5hJ2Q/MgxrsnFqCs0Kq2kNR+Gpwnth
C60QQAe2/BQgTRZ3ZO91bsFRSQZY+E1GYdMlRZfrLlqOLesDpABHshdSrJwh+2LC/NWycHaJ8u/H
sr8ss93fL0g2H3jmBxrm9+GmMcEzBgOibbRzZYmxwExbQ0++PqACtt8rZD5voD5JxBSDBrePzOU1
qKJj3xdqdYaMBurX7roOpMIAn7mOhDdIqlT/bSJAFAAxT73HUla/qc04eszxvvyZ1aKneEjxPAjs
GOXIdxm7eaEu0zQsYnXMRf0vKFSGBxF/JUrSIWCFQ1tgZdy2r8Gnqje3kr4beOfxj41Cl1O0FztL
jRqrON/1Kxq4iuYkFzXJWzkM0D2w9Ue+TOuAbCegIZwYammzED4v9CaPsTI3V67osZap22YbP+z2
kXKc/lET1eKGvitNmK92ukmHmNx1nR3LUtoHStMVsJ35kxcvMLDSfj2GL8R9tbLOuoyZOYq5dG3j
+kDxOLwn2iU4H1gYosos5SgDo1eG8azJD76FQYe3I6bhRkz1CPtgpUuAjag4sJu3/bmup/FffbZJ
M7Bd03g+S3iIJBqjQokzaVSiBJrbsTIQt3+H4bjTYLgKXxBl8Xxc/Fn/vmr3XnxJJr2NnlmTIjsr
Nyt5+qYEVjwTEcV/KiTc/Gq4fd19VTHJcdpnTpQviZum5qsgVLgw/dASfTbFaGGhIPHlqKdU3DkX
JlfZ3f1FKqp7sK9hGNoz60wraOOl14AzqL39YP1wdyR8c3tGyOIHLdMurV3oMRj8Uj4XVFkOUTB6
FiSFRi37u7FsE4wbyjTM1uozu6jWCPJ6rXcEJWQbTNLXoFtTsZJ1LG0Gd4WiOlLK2bnCXolYy6Oq
TnoDTeLzlkQZkKccBKHsCp8F1yuUe4MP0S0TNwppCjFSPD4oSkTuJVqyyQOABf0OOwx0ejoaeWeC
RqtR9qZqMVDX48EEASdHzeILwDhR0U5X1z9an7vbe2fqO7omSddRy9c6DoWAuaGV9V3Po8WMqWxa
tU6zlmEU4+3EJx7xJO6w1RwmOgH+E0SulIsg27wKcqAZ3o+LjnohUC+PiWdalxs6bCV3CY5mfQ21
MgOc82gzLBBbIetsBs4WscGNI5D1yvNrFVva/PWGPpKfyUjgmtdZBum4vxb6JjycJlq31U7/68cH
6q64d8mVWHG5IMchn5rTmtdFZpQbq7c4D09/v3Gzt/htOJ32T6x5hXq10Vr++CbxoUwWL+9nG/zv
aFPa+GDoPVUoIezCkUnluBPSMWC8rHY2TnVY+YGJ0JhSThYlJyQ+QYgq6Ss+3MKD+CCk7tzZls9J
lY1HhWCaAW7+jgHMkDSGn91tKI8F6djp9V+F/DFPp8I4Xfzvy9TGNpib5wt6nqE9bbJNW922NrLT
ueBS1/Y5AGFByxiEDCluWIbionYYKyAsxaq1kxB2Y+Q5FhfG9clO6MIMm94sDfpz9p7dlTVXtwj/
zE9u2xOHtDK7QnDOy+c6Pn+a35ri+TbEtm/R7mXBE2lJBCa7qh5FaW6TPaUDUXbDIAnh9TLYhGt+
ZpqzMBVkzRa+JrO+0enM69xtSvyfL5IBbgLKn/O3eMnyAMPEpUIq/W/rDpfUPfdY1GlNFsENF5zN
gHrYDnjwLOgo3d3rB9s1Gucs7/zBcz8F76mF6b3Kkb4hQqog4sPRtcNFGGrK2csX+NgHGj+mNXcp
tzIdgn9+OI6VEftS/abCZ5sPatba9nXhESLH24moZft8csoGAApAsC8beyoCywIuRl4iYN0DdNkI
ZMHrxUJejL/p+R1DbrJYHwugn0N5Wd34evqxOxZ5bhSJtkQ5SfkPBvylg02zqjVep4pNNzC5zMuB
3sTmgy0AHRAh8QIxZOo1uz//NBsar0sK8POJu/ubrGbWZ4T/XjkVA0/O615nd5sfr4U5lkYnfcmp
ZK+nzuUf1TvagptDPMFGikaDAgOzO5qzZQINfBfPTsyT0G+LcyGOCIAjPcObC3cKK8SOdYAoHCZx
i/MhzGQLk5jKF5NEyZMnJA/QbRzKacricU9wpehopx6yENoSzdLscNJ+ohJ8D0q4NPii0TZ+djtG
LmMg2WG1i1wr81ZgE0/J5H0uZ481+GsBigK8X/a7CoeIr0cw2IWTsTfgTvZaTcftjcFjJhODsgq0
IX6B7MnLWrjCn0xecYsCZcfQuBaxlAOV8yx4bffPGxkmQPbpbjGvlAiRI52uJuzQEPFtTzElm5lk
qAvR9UR/PDeK5dmNc0c3EKK91iPyKMTHlZ0XC/lefm4+xtTAZdebqLHOY/iog1raWCFcKLUHUy/4
UuRsUgLo43ohsXbdypwUsxFHSXC6+M1nVPLSczf/yF/c2mH8ewEFk2+OldEiKPHh6BJXfHo9Wri4
UuPxqTL8kZFovKDugR2/cq2Uw/DawLl/g0PqidvIkciChO1DIAdBNl85VFwx2stG8TuKmz8GK79n
MdsgAMfZHs2h731kfUUb/7g8AbYQUTht4VWs1HjKN0Hpgdi72aAQ2sfffPpun2cfmHiSBEegvsAK
rbCFwpw+zc1FlrZYj0qAaFkmJT1p2wSLK8NsjKthj3guVd/qLyQ938pexyCR4jQVH+Wd71oDQO0r
51tbKyE5dilIWaAtc+1I8mFsm6Dwfg6C9/s0dDZAD2ist+lxokS7Lt/gE6AVNr5EpNvo8lfd02Dt
xHY5sOzwyU+WYBCoAkeOBmDiIWS5hemj9AMrD6atSQMZcnDa3kLooRNJXTm5DjuzaFQnOMCTLRN0
jIsosX0S1zQOB7FIZ0098jaOZ9AeMf3af/+bX8IGlKUidAOA3iLG4hFkNoSusiIka+Sw4d2YPnVr
YaBRlBL1GY8OnrOfHXIgFNqunYyezJbQcpez/UOUSscdtM/0Al70opKu1l5ly+wShRHuLMbooySD
BopiBrmuuQSuVM4lA/hNtLYa7BDu2srhXNEvR14rHR/KTstd+ST3Z8Kp5PWL14exbrlYv7iAoZCI
WBaAobVe41IsFQp1KVu22bzNTvlfUsRXAEoBfiF0KYLTT1PFACVJOoo3vTdhXvaeNaz0gBXlo6Dq
VhuUBMu+XDO8oKi8/Xb4L5wn4+YIQ6DWu4nyjRsgwRvLeHmQlwrXR+JJIB0Mh871EKLGuTOdKVje
qWUw3MAu61gu5EAFGquAULFo4ps/prVrYf9Yg1A1hci1OdnRl1n7wPEZ+dVvqApnhKWNP6bHZqYy
7jO38h3QkMbS9h0LSqS3qq/Swvvle0lnBCgP2ue701DLgG461CjjjqdxAwcmkZItQS1KBJVEli1E
kzHW8YPeDGC2CddxZl7sHrHIXoK2qB/dLQbSnVbHiA/WT3/O33snmJltAKL6fiiK6fW6g3QimeHp
4la4N2cLQkds4iP51BbmY+WONX2z9MjK/OWBex5xDhCaGTQbn0oBvLkQIHl7xGs8He9uqOabKp1m
JvZSNX7UzOVu/E2vI6yU8z99K7cOHQR1/uAuomifjKAx1PrJNBLuYy9fd2vv+gUMb1/ZnFgmOrdA
tGobvNByIbJk6GKlhmFu98b60UtqIlAp50/aC9psk5v0Adcoo7X2NvMUpKPNkltxNYuh5Z7u8j+B
Xagdb4QL7UGcaXSp8RjKHyJhurJGHrmGSFMmEkEdMsjs7ifg03E1npdTTV2RymaviGQ1xY2DrRWO
olxu8EQ2L6robJ4ZyqD14I9vFSSznwpcNWa4TZJHgI0uryQydVT8xORIG0Kf3XahAPM9K0EpHYgM
SnPOb51I0WaUwHptf+4Ca4MHwIwgwJmlGWFZkNZjwI1ijr1Ev3IRIItDPAyY0pUDBDP8ryNU+4VH
dXq/LF2cVdZ8K7fR0JhjEYNm38PEP3fxFeWdJKV6jB1whT+VY6Hf5hSezBQgaCq2OhTaqNjLdnEb
AGbRxBhGWn6CvCWCKQAtwr+Rtfb+vJ6Q+X509PnWHOYjUeWH/ZsSl96BBBKRzf76TobUGEjqGEeq
N8jt86HYZdEogBw0Y50BYfEP35EmB2BbJiI9ebvoacgljoJcDXtO3/f1rltkJhPbFb44SW/L8JcX
0S7+hjsDeLM24pzOejoXxCY6Yx2NNArS9eHToEDNEiZWFPPhNtA7efOFWstaU8N4IULxfKQoyG5N
+BlZ6rb1DaV4Ohve6QQDtJrJu/VyvL7/8xDb8W96+MxjDNYqadcMvI4OSR6TKzocDr/jLvW6PUgN
euxqX1AFutJBVkYrsohuquXiSY956vt1jvY1Yex8AEisO5eGnpp3sCORl0rDs/JNjso4Te3Uglef
d5D9BGX9j4rPTUxNIiqEEil5jVKR8vICfjTbUkndPoL+dirFfVwclob/iMs36fNQWSsd6vF4446r
fqChqbxiC0PfilfBqW0MzLUBJuYOjoEqo5A3/GGSf/ROMJ0LM3KD6uXcBowHMVkh4x6DA3D1tORM
SDkSmXCLkmy2+2Qa2y61fJbruL8rxZYxZEZREnX3b9wX+TgYHd0XcrKNABv06eWob38JO754a5wU
EGstu0HAgsLxmJEDSrlhm2i1nAHFtRDD3Y1ftaPjQ/mS/qQQeBk9pBeBz0xcpmNxrHC2RFoQ19Dt
8ljzA943nnRSFxiol8YbzZGF+OCD05BQGa8DAEo72ucJBe0qxMlc9mIfbYl3v+2IibsX8npsYHV4
trOEFEO8xF0vxPxNbS2tvq5FZEsp3qoHYFLCLiq3hlEOScQR6AHMgwxOrzMk83hRBt9SVe9sCxS9
IfdIWBHQ4HHM8IOoX4vmVYuZ1Aax5mQ0DkMsj+G3BiEZA1Jw3JihexMlN2o4qt0h4qWH+jmuZW6B
0rJDl/bHCCHNNdX/Gsp1hJt0qM7gnZEO539QqY9WxCwH6kUMz5xYX5L3fpwxeBeKsgvnv5ULOIMt
qXGu5GvokuQsliSpV/OM8L4HG+Ke2x0E+TvNiXxFcKgBMzFtRd97cixli9yJ2pfx6mrvUyVdodlC
7e6vbKAp0reW4R9vB5WbJNU+Q0etNmbWjzKKYOP/XBikUilup4QSAlxltbL0B6+Bu9xg85wLD1rD
doOUR0ZK3OgfcQ+qgDSk4h1hBTUVVyJ6X3IwSroJmerb6IU1vQtelEIsG3kRryWY0TFXYBOATqkm
xRnveFYta7F+7AwGKNpupsg0MeI6OZoOEeUmrzM6gwwxCp1UtclnTSj8MXQKTypPnm44STS3pe8G
8L8Z0Dz5aSjooJFQ7ZTvIms9vDBHRdGuCPREaqnKVegLIEiwcXa+huB0l3FgprxAszwyukgEDF+C
on7pKeG0myaIOPS9GVY61v+zt0mCq6GVNe2GzMPJVPb4xFgPLaB6T2L17ud6pHgrsDwprrlHk4kp
Q84/HM5dHspRdoj4b1uJy82oT9rnuuoX/9VjnYkG5cP+hGx+LgCDaT4Y28HpMRqbtNIEyY1rfXxa
AkhTxZD5KBhEk4Aa3ftoWwcafC85zQNw0VwT2GnGHmdxjcxtueU47yUDDyV9cTcCGsoN+mchs3Vd
AC/6WqAfspnvMWdImb6uban+b+e9xpFLtQVSPpptyCAd8QA2jz/bRcUzaSfukrcbwLYsSyr5xiZj
giVhQVYFkTu2pcChc1xu9gvnBB/oB/ryaWIy7fK5iJkqMVF9UrmB/sjltZC3y1lR3weKqiZ0gklP
bJ79i8ZXvBAZOcoX++QjrOzDArE86mWtnrNNiCHua98dEoHUHmZfefKfMH/KXpOdlC+6/AvDtkUm
pmA6HztES/6+JpxJrNkOd83MbUTIQ+iyeirU3vX1mzmpynQCg5/RfErD2VDqyp5eHYxArY7e69H0
Fr7S2xeH+bnMMYmgrSYVlQLaNaUQ42EK1dqxDDVhOmUWXzyednaFYqb4ghrzkuYFe9AHA/o2LCBZ
JP9Kneb3lvU8xF9/nYbmRVVdbyaPKFrGgzKS+oII73oHftCTyYrZqjQ4QQM9xWfDPGOS/uCd37LL
t1b9Sos0Fz0vpq4cTNIhXQZgMZYcIYNP1weTx7IN9abPLeJVERbG2dhelZXC0RI2hgZhnfYpwA61
j8uEQw1kj0mcYhxWXcg6zKU5PmZw+TqdGNI80F4g+uX8+QzdUaoCSmGRa/ZbAe2ODuEvFjx3zo7a
P2bdMSDIz9R+E2BMEd42mMbdCMR0PA+0Hl6XqaPte6OD3Y427GXlI3jDRJM6gHDpn/Iys/0HQ8kZ
67HqpvNMg/ZVFlvMR/2kaOOZnB4uuBPE2EqWfcYQGtGYHBLsGfjisMcv3QIqBNvUCjOT8QRuULJM
ZN/iUWE/33zpR1kvdLxiYIeR0HwKFrayJeyuyueKfHKIZXbfrLCFytmHfcHDmuay93EBye8zgZ1Y
atXWLlLeY027xpJHv+iDTzkAkCKKDB6RRhdlZC0Dw4vJjTXzcsEE6KTy4sCMpuwUq00YIWahxErZ
tw05gyLEp3rtk/262GmkxU6DlpuWJGFEPlA0O9h0jSXGIiNtBm5v80+wvr7UaTQ6yOgr4KWfuTia
q/oJeUqpsIaT63DBbTL3RhZaECBwRpAMg34AWfQpsHzSRKSYZcKr3f66405syRNjZxpxmi+B71am
usw9M+AMj3FV6WRebHc2HBM2K1oUeBdlpSximaHYx4YNP+rBI0R7ph9kD8FomuZvyM5I7YCyfxGU
9JPBgLUY8vtfoJKso0GHJ/LhsPvpF+J3b+ykjk1C5C+r40EH25TQPJ1wgyGKB7C1dgtIiQYbNBIR
UuD5dmRZt4GjU9strvpG0i4Vh/KwDbEJSQWllP8uQa52iWah8K0udACKjxEJrN5UpD7uER9Gaf2A
DAclR2WUNgyYHQV79VMkSmLKdl0kEAQRafBIG3cKWhupFvPXj4TLbowBib4yvNG7ioWKUEUzIPAL
t6FZVfTsvD58KaaRsY611wAr7+1ZKU03cz74fSn8mm1NPWl5t1g3hkph5MwwlvqW5oymtQmf4OSf
Sq/9R+6hncuRfTqiPW+wzSq7MTehAbK0M+Gl6tIhBrRnIoqicV4w7UJ6c50aWSN6yg47xzV2TF56
oa+LBKXWx75TVKaU8pqHY4K2S1n8RSdPBo8+8ry29s9xlpZXX7MhlBFkdOseyOyZpm+MJI/qFtv8
RydhRpzeiVKvYKkJn7SqSmEZ7NJN4YOv83/Qm7bnc4pNMInB/+VDxTkXYWxj9TugO008Caork/yy
ZWTO4L+yNZWmtnieHsmJRDdqxA5SlBdKuPu2Mfxsqzc49FJDiOTq+u7aS7n3Ja4iNFI0uhHgU68i
8Vcyv6m+nw2r/lqmp0Tn2+VU1Zf9G/32nArsZhvMj7aDRCAS4/O3MAe8XFPIwOBQ8Jt0yqxzQHg/
y2pYB9eioCqtnWGDSs/1g6yAgeKW/2dKvlLeYOxzDdyTc1jo2Nnyr6+n3UnjYN8meEz5gKXkYFX0
8czW3wrkH7MyXBzkqlPt2uuoUfbNMVUiK95H5eQzXqocxT7UhyCxqoHm4r82Ge60IIJbSq/F2Qfs
/QShxNG9uRW0i4yDJsCILONZZHDSEaO6GMJoSklUjU8mM08to0ty9s/Un1pZowH7ERmVggQTB4+t
4H6mQbzXTjwlDbXPnFZDvP1nxKBCbg3pJM37hgqrqffB3YU+7b4qZzTLaoOikr3LP8xBj2cE6/40
c0EG/Zy3HkfkZVzoBmJIfFp9eRoG8UGijRvBYuyV10CNZnenUdx+odp4bQPrimiKz74dn5Ogl5QM
BqVTIhdtLwUeBl72vCfCQ6G75+sZ9qFaGqm696O2HAsHnJtufO6g06S97OULf9CyiKlPKi3bWL4W
K3SDYBToVG5xCU6Lj/y+9HO4z+fnDFjtg2kyNateBaeCARMJ1COSVtTM0JtZGTPrUma8JlyGPHaE
8vguAIZrJjaIW1ShLqT8asER3uY/xjedCnv141JWTy99p4lTQBkxivonbvMbqCa8JKFB3hf9+dt9
areEr4nlQfczTgTuDwVT778Av+Af4EGhGMRoza1UR45ETCFNo/5lbjwSdqG0smMEO81KU2GzoZ+h
lgSTLNp5RmCHmI4I7r1hVkGgN215Vo3NDa4j7Zp7X0sHMNMJ6+4tVtYhwhwv+gALnD01NIdXo6Pn
4tGChsZoHviJmOx1Qj796bRxmOvt2AVXwhWNKHKa3++bQ83XXEQQSL3IiYlPL4nkwBV5cFDe4uM/
dfif3AL+gFmaQC8HqPEoZx7WwMhldC+6HADDbrad5P05A5PtgN8rwG2yo1AqT6xaAL5pekk1lUe3
VvsZSf8H7tYEb3RDtow/Qi5QwEUwauDLOv5kyRcvLLsmnqQvZ7DP3TmyjkGZ5zTWp/LEbo+clkPN
TFlfur0jiSCOlfaUvv6JtVWJPHVNPSgAmK8jbrSUYZ7afYYVcy0XVnui256kKE+1dXO94dDg2qno
edi4rTHj93MGtx4U/viN4f8OxkP3zH0qPci1e5PKgRed0f9r3EIP0pjjYFrBrbINHLFb3aBoAbIJ
z/H0pcvNDzEXwOPD9d5ionRxrO5/TJaIBwkypjJ/All/sw06b9p7g7py1+ikJ9P6iXnREi951LFf
oTwo1oJLy4pfQHSYXbNT5X+1aamFCiZ22J7J9UAGDFm16m617qiCu1RAa0NadSBVwoYjWmhO9qyJ
Tuar0VgeTZGeQMIrSdl461P3M9b94XihWIuxZ9Ce800GU8Q7lDFYIpuGnBaX4/rrjMqAp4HeTXZP
9toLtpFwyNKEAcgHV1LjQev1pOOnaIIAfgnn1ZVfC8AzZNHS9+Ii81fbLIIK6H/pWKYiUHYjmIGf
c8ked/gE2qTgevytdh5c4roJemVKeEf81VR+a7XAJEudbNDoDfCbJZpk3cKIl1IVBbNtks7yXQXm
wUDuowcT0hRWL9TpRHNcyGmPbGmdP+TMq9EZ3qqkbygsR9KNu8wRr0k+gUKI2dH0wf3jxm9CNIIh
4NUB0VhIeyXPFWKtc2b3dmdHo4TnMR2nUeXFOPSN2STDNWNix10KewwS5whoxL8MYWbo/muz+IGV
aQZDOJZ9B5sAFB8oi6rXZTY88WjZve56Roob//wUMq13vdA+HyGUAJsyXFhwRjf9nLidH5iOizVY
CHUdzq9LFeW3IG79T82Q3wEuUp+F1yrgXkioWEf1wJWYZvAopNEaSxbST7KgMPgH57A1yXhWxLYd
R+0Cil+oie6Ap9tRyPZcHlGvg9EjwCHrm291mLMFwnU5qQtvcCVnpoSLyfgvYEP4lNCu6ZsDLZ88
b2l4MObeHlwVNc8mHNsyzUzps+t6ZX6i8AS8N2zwPYm0t5b2OEXiYRJEMYR6vhNfxEuceyfAsCgW
njcCTxVEcrKIjE4M+d4DX+4de5ZqyPJpzeFdM5FyMrZqR4jl0b0UrrDJ7XD0XRrBca9enXoSg2UE
YlcGonl2WOvnAVlhxFmiwDuh9oqvTW0j2iQCagOJMcRs2Q7dWBy8xILw2te/kd3r8gczfgagyORu
iD72Y0CUlfbvMV9dKnFva0bK7mun9cCKvB4W8H3PoyRGlyb6NNhYlVc9gIWvWmiPQwz81tINKUwJ
RYxPhC4R2/vRkWpjWuJ6FGkzRxdWjZyjsSYlRZQ5Ob/72ohpTIUisjGFFaETIVKgtG/gC/ipU9jf
BpvpVbAiXIbxp5aC9nliF/JY3EFVmzc8WJuFexgA129Z7a57rvJM1TaCyCyCepw+hcj2MNuubHxX
HJLSwv0c8W/O6u2qiHk9qrZyyO6CaU7fSymDjMOCjHJEGVsg+xkZukrpSqU/VCUtz9vrPXolql/n
YGGDhiLBekHmWohdarY7a3H1R1pWuS6GMypXWyyNMqh1r66iGmdVFBEwk9wqWw/I895aNgPgBcCq
aq93ifJ86lkW4BsfqT4U4inG4cgh0rxkMXiDbq9SqKHDeimpF/KopmukyDfdSVkE/hr1E0iZUGqn
CPVlsfiu1N2DJoA3oLI9fBM7cMdAspzOAwdPsgUCz4fcrjUAwueRB9g4lmfBSZgdakM7f6AaIJDm
lqe0nhrtSFdpEA39ejxnOnDUL1dsxhaGvJ5JiAskOAh1qbKNx4hfv0fpgRKsuw2jBlflXxPUF+v4
ZjdA4D3ar2rSZWtoM+lZdMg4XHp1VhvpyfP1JGv8nYMDau5qWehZngqIr9krBqkiuqVAgO98Ztft
y28RrRPA/3RpcMKJbFxz40w/pCLa6OfdcOeezZXcjq6LUafVIfaLEKMLv44urFw89n85UqC97fCU
F/Vt++VYajK56avU9sg9aLzTkeMFsfoJEtVRuNxR/B42JSZCLOvUpQiv6vU77XAAOHVDjtLgUSdB
tRqHBYfN6r9vRbMPzyzfkVwcipPUrh5GPXcim4L/pr9+39KMfJBfr3FuAHcmBXJhBstwgz/iYFPC
nBledJ8XNMhBNUjCYSS4hx2U7dP9rHk5xwoCNmsspiT8xiOT0Lj8eG9C12EV94Uv4CyC2h3kHACd
EvVx19hCk2AQezl055U1E/yiohYWkdVf1L2KOXA49XNUQEkE9vRiWrz6ogAQEZNwc2ssUvg158iy
x7DNFBdW1X+I/jxrc/q2JKdUzCwpiSOcQ48ojA0AFR18bjLgbdQRBGw3ijvt6UvQ5+bunXfn8FEc
gkgcmUvyL6L2E+6j5CLKqLv/skfPkIlspiy/rVm5UDcFBM6l53mAVA+FdWzFDGbLrlQbfR8IK2OR
JZ/cIV4BdO3s0WEzHZoynN5vQq5uURCEhvKPKHlyadeM1UgG6cv3jGxnLI/tS4Z8EDEbRtgZpUF/
m4vHQkcnM1TOjOi8QfSuwQtZjhEzb40//yQKMEvbVjp/osJdf7QM5HOjZax9j43XjRNCMU93SOeT
B/bTtS/2lA1Fvqu3qfT0Taa8XdGaEb/kZoA0jzajaNtx2a9CB1Egg88LKui+2STa55V1zIrfSzcd
uE7B3MGXcahnVnm2EUbLuq3VlRpxFuzrVrBTIloJlx1hWXGZV8wKwSCOVxFrZmYWl0K4XuAmE9nF
jU4W8yf5/UmtGVLAr9NeaXpMGD96k27VF+ntR0CrjoJoEROP1Vfp3qweaYi+VCmC6whoimHyLMSU
/C4mKTZMkne/teRDogeO/zegFtdd3mDhjY4FcFU7DohJhG7EYpMjovcysBv29HtZOkeKpAQSNT3H
o4R41Qswg2NdIC7OiBmVv2h5E3+pQFra8uEdBuOVQRW6O55NmYuZNlUKCnidpJ0MYyEJy+cQgrMt
SiRnhKFE0lF9LVe0RaXOWA+deVL7BEbg2pX+Q7Ej64URDYDYBV8cfhokfg7igEhJxJaorWLsCGBQ
LLbonSQsCAPt6mx24GC/HgpSPlM0QyNP+EBbjptkX55ytT0zKRSby5jioD0/knPR2biyeRBOtJ/U
kUTOrjeOLwmR2mwzPkxd0YNAO+IvEOLDuWu53jhLSHBU82RZAZsvPCMIo7QYYAGuBU/teqlvascu
R8Lj171q6vCL7X7XfACxh5SHqhLhc66PWcoE80XJ4HlptvNHan8l7GEio1CyzfLzTvE/e7Z1lSS6
t6k9bvMXR3/ry6Z7pMDdqltkkyQJaYDEa5GieNvmYyVkVz8nks16lTAYzW3WukR0XepE0hbK1g+x
12+1UiUkF143iMGogkJLpKDaWstdcF+Fnvg8/hOU+mRlt+reKdRMooyFELfM/3kp+TPM4ZxEjZ4d
OJ+gMWNJ4Q8Y/nso2hp977JIKx8tk9qX5VkAcb2JzjQcWbJ1mJK0m1qDlABZkysNQ4l4+hCVit5C
4q+gQqweCr8JyMjH4ezHa6l5Y+v2kBw/OBtN3OjGRDwpbP9RAhEg4SCTlBMpmekpIDZ7/26mjy9B
XU4slPDgLxhKUAFngk8/8FAT+qdbBbgV+34qiOsnNBBbjTl8zb0bPRugaOiQ87WTyTUERg75E4p1
/TH57FMiB+CId90Iqf4EGqDxbAd7zMiPVoGduDyJjHLGR8utSKIjQDEK2BtWJChD4nSUUbUs0Z7Y
l/irda6MdCrIhvpDY0P5chmS1Jq/tWiKDUHPaFiFnd7+vgY6IyhOh9Yx8wgu0Z56myjUJak/hkTR
qygI66JQNB5fvnkyI3jUYRl8TCKVV0op1d+dkwWkjVZ2EZiz636Y9KUrtjAqZaE2gwsT8kC9ejjD
hhVKtN0/6sSOSQ8ft9LrxeOqwU9D1RFTnyEPeYa1imFeVq9IF7hSrISQAMnmptIdrCbotVtRBEGF
0xgJx0QIdk6k4AEEC4GzuJFaCR+ZAqdgAeuTMlvSKxHGHPAvubJJax3ylSLuZXsgQaRTlnAZXs3+
ebVSACUedVh407YsGpUWwht2ZeGUy5TRYeMU/b5FyhpdzJyLRjkoWhT1/k3RWvDSBW7wnF7wdGlZ
oN79dkRPeN7rYsF5BZPNS4/MYe+GI4Lst2YCWbixiSFwr4YT2fFya063NaUQOatpvI4SPY3x/xLs
I1EbkYjqWraPcKgYpWxbgZj2m5Cpin6SqGzHxloAaj5A74Qun1tTWkwxkSuwSpdj15xwdysYmyxO
9SdPxVSqRIw34fUcJyEXJf+QmrmPceK0gtu/GsI03rXhWoNgEOZ6yUlom52EgT95ywIzm7WH55uE
h83l8bqJQoOaUukH8EPobAx6tfitrA9kijSXDCSZRd/vwxKPHDQDeA7Vt0INqApbg/v3Eun5YTw1
XU9mDvJL34iYYm1t1vcldnwa5b0c58LERQ+QqWrW7307+H0+pVurxoTgMGnxeWqHzawp12noKB7i
ZT3mH2I/0krP53DSpZLHA3IxtEWOCeMJknjB2/UAmA9elFMTfKqjuionjDQL+gtUv9OEOFhgJ4mQ
EMt8VKMjEBJE7BEnWdDQ+dPD7lsfGhaxs6gXAk9LeU3fx2jELsv7y07LpnEqCJpCvk1hgpxOAl2H
VWg4MSLj6bFlbdgfP5A22vWl0T+YdkZ1poqrsVU6WYhsHXYw0ipaQo7fHEU59Bi3NWk8X3+KwcdH
cEIzRwKVKr5aBUOUOr7bZoUyzpfZYV8iu/CurCM9Qcxc4s4FvVJ+XGtTkHD+Ef4mnqVunv7Sf0P6
PQIkmSL4EIp0ANPI8bDov9f5lnrrnWEfXDqsgxvVCrJKT795Cl40v3URfkL/S2GMywIjTbhe3A4+
2Ux1egLctqlP0z7qPjvsevPQRAPVvRMrgb7tN5g3e833JymMh7fpeObe46iSgjeNE5ziwMcyQ3Jo
7xyjgqT9sqT6muE/e7c3kNX1KAYF7/HKJRJ1OisKS01COO7aEmXr17i/r/vc8Nr8JFkHZQNH+rdM
Zph7aGDzOEJgELTel6DgrMv2OSHvNDpDbxU2UGlmnVLl9lcYy7NXIAJU4HKTuaFl5/Wr5XYTKKQ/
AJ3iF2/6q+RYJWmM6gtjf5odRlwMV08S/rtcQcJ3yB6iP0JpbPlVd8ZdzqF41qLPhjib2s7oQhAZ
12J5E2bpBzaDZMdUFaHwhpdJRjuqe6DRUcq792QvSfholUvqZ+zxQuZ225avxg3gcZHneVlj56sZ
QOFZQ08FjZ2JZBaHi3bvsoW0cLlv8+ENV3LzIhPb24AaJyc+8zhM6h2VeWzCDXPxsHZcCGGzQJ9U
ThQT9snvYzT44rVUEMRIKUl2Sj6MvEf7YC/L+uT0lThjofTQaC8AdTRg8Qkld2nlvw2F1SPzvkPx
M2C+EUpqBQCCeYuNPgARmMyAoVJVv4AhG+whSdSo4kqCIQxL49ehRjMOkqIq+QndElvHBlSm3afx
DFvuccogoTAXxhA7ejdHJYjZQMIz2Y7LntrdLlLhYz5lPAcQn8GykYJASHGDQq8vaD+jvRN5ip6A
evAXpizEBEbm0aGZPjHdTKWi1t0w2y1/yOgFrMelRbo3TJLNV9q8+rPasueTSydjTqEK4TXml81A
bbYct+iHGeuUfQv+LybR9HYhr9GwFEblH8lDFfnY9n8OM7sNmewsSyMI+p9jE92P8Ybm3TWJzx3f
qOArdMaVRd3rs4Vm2sN4PxYOrwJnztLScbL6aHS+OApsA8YXbxS3OYDjidm0oqfV2VSH6IrIVtqG
yKzg/soDBHMKIs+JNab6KBzxNxPi85Fcqeb7T7KfToB8bZJqxnP/uuT5aTdKpSgVzcCjoskcmhaI
VKuNZWXfJhKnvJCeKKAzDa115yNPQh1QDQ6R85+FrTk7pb8G2OLbZAmW0huW70F7fMK+llQm/8gt
73tR0WVamzHa6m9qd/YfyksyoQfUpinuxzipAMumv2KkUgM8eudbGOYmgDBKqeD9Jnb5mt9xGzOZ
IaOTYwO4JMUVKRAbkKR7FYVr514xp0HApzwIrYZTj0kJThE+eGf8SRQArU1+9uyt0Ts2YY3C31Lh
ARfXITLaIJuGlDmECfxYo+KyrYk4tMTPR3VJTbyhg5Z9u7lctnD5BrNjSYmEyvBzH0//ruxsWXQS
VgNOyq32aWuIAsFJAiMsvrsGOVJe89Ou39//HcUAB5YtUeLokby+rokDArZU5Ty3FuRGZsl1MqiO
Bt0zgkzLrsH/zhbwiqyiieFHP93Dr0P8Peg4tLLa6bD/ggjUOdpFrkWeLlQCdTYhHXfX9jS49Fzl
c2PXvA4/qqubCT1zH21C0i9HojRnWw4HFBVflxzO94Pq/mMdcNBUhATb1kttsucN7bP5Up5b5Wdv
nQN+fqO7PXAiQ71z4tHiGiZPi2zm+TvsK4zcg56r/I73Req6QYtws4dV18Myxvk2jVrD1nsNJo3p
iSqOdPO60pQH8hdzFlDlQSAarumDK2ug2sJwKBsoHNPXaFr9P7r/SHQ87u1JiQCp+H9a3D4d2gjd
pSgs+LXQS8D549xEGjCY8QogJPXIvkHic9C3fCfRG8b1D9jQ3RctHRm/B82ivtoQ0Yn+oX1/qCcS
oTqosZLjtsl8DhzhR9yOgEjBlxVxBMQuHYt+LZfzSQuSxHKTg6pMbwvdOCHlecowy9suBZIM2qOK
SvJNPc6rAR/ilccSDYyrbJwsvkVEaPoyW4EFfOJuBUjZChWuZd0xG5cVPsx9+hdYhUcwKU1GyJVM
j5kOnC6JKr0Lw4nOkEZTiTaGqPfDVaw4ftioHOA6HbC2OJVk4iPun20RpZEZBTZAzEARWmSoRP+6
fMMCnr7OE7158q2oOv2P5auLIsnWsTPob6RLyVXu278MTooFLksAlZr9AVxvO3eZ9N5G5BZP0RNV
4XZGgfXrnV71M2wWz2eiA8Nkr5yQ/qw0JQavIvSo6uTXDG4USjXCcoFL5EI3bKYx1gF2OCuZhlqs
ZBecUSprQANrmBqjNtl4jK0507BGyUrzue/AGqnymksBh2D0S9r4zA7KiuaeKZQq+UZyoKev9ucg
bRTsK0JeS0OzE/nBAoqwr7Iw9lpS+5l/F1QAQ2ln5rkw8DIht6/QX6G+ILLpuQReZHAaHwfyI3OK
yZBXKGUQQXKKYfucU9E7V1lOSFXoN8mU/5Zzp7AIRZn3q89LEhDlOHRNSDJA3LJwzbK/BznuK400
mJeDQaQ1dt7MRvvu8xNJPRRgNR+19weIDUuxRa/lb41u0v9iLR7WiCaeU2lrbNUnj9RYzm061v2F
H0FjVciNCGpwBPN3I34TFVytezqmKLjA8NHox0SMRn2XpfodoUBFkAg8+tIKrlZj7ocJVCZH1x38
NV/358OcISlb1L63MW9YI8PwALiHxLw0i8lL2kYtdyB+c9SUZyOfl2OFbumv5KTwIHVsY3sVply8
fC0EF6wtEGX86k+eggvtndgvgz/iC0tE5Z9CZHSW//H+WLW9A0MyzeFhtRvndZBiGi3W8Cvwyxrd
inUQVvZhLKXfRbVwEFabrSalmFGdHlFwRD3btJ5Vcu/+y6kTBplFnpDuhvL0cPVfWCgPfNAHxeok
TfZoLuPkGDRMyFvwDmknlkET3Y68vxPL3d8Mcq5qIdLYKAiO9qfddaE8Rgd8cIGE0Ly3DIOwHNeV
nDqQdYh3fzBftuqO5IMVPbC0KIq3MYQ17Xr7edisWKH2tkeC6PROSXbmy22LyfwmYZAnO4of+KyC
YsR8N7t9JeNM3xe+gpNlUI4loDbcBcRgc9UDPe5Q6Lnz7yd6HZc2vXjT6daM5MCTgD32D8/daY6d
8v90LNLsoKls0RnP5HCf+zD37P84zpSOWMn25eqe9hF0jwp6Wma11BfBp8EMUMFnMxf4qQBFmGeq
sz4ZrCJ6UUnvYFVqxKj2N/RkSb3KgO34ui8onyWHu5BxkVZgyP0XB00FJVzZVxXJbdZKQYgy6BIz
yeg3vC83ekTCa2HN0iY3JLnI013cqQmL+0UPYIWL9C9KldpNjo9gjCqioTnrfehRRIbYEzNCIDjH
0vXsFqBiomBTuWLHALAkWF07796BZmRB+HcRgTS1VLWQO13N5DHM5QbrsL2nRvFrKXqBshxn6UoB
Ue5x6M8jYry0+wF6pe5cJqjICI+5J0aslUMe8pRYeB8xX8VYYDML3D2D8l8rA17p044i41uLahMg
1Rqkqwd4m57ghjzGtqhbLbW3l1lthlLT+VfaxeV+4/uzvIGtj3s/oD3dJSdBQ4xiNpgmyh4yzylJ
FdqI7DGegyP/3g0h6RC6wx2clb+wDbQ3MAEKmSVkIsfVf3m3HxjVVS4WuB8aUbprPsdv/rk4uvd0
1ejQF2kjNEp+6lX3E+ucovToxcpfGyBK1WuVuqiytO6fnhCgELuBODmteU1eOE4+Lm0IUzduK6Yz
Iqm5LgX8eRhw6Xb7dCnPsTNpbnfb8icJDchMyQX7jHulSLkm3Bk+C7nrnNEPK9TlWmYyGPWDNRDB
jNF1GdluSAFIRHqkNhpD5xRFoAuQ6eupRjAiAW8d9FiGwXIDRQfGuwQcmNDAvOqINIL32rEV/llg
niExr3cQvb56Y+AZvJ6CK9EIfF13NLHQM8igfQr3g3IdvqwUjoBJfsagqtRBAdAPSJi6JSCpW8IV
/ozMNp66dkdBcfE2+X5N3mivYCymy/XFOonGQhszdv/KdQk/VsNMqN6VFey6itecgp3MKtcsdHkd
wE7Dtv8BO/pGBJBb1xXCXg8d/6z1/VmSTK1ez0l7iW37NGKKp4n5PpTxhTYRs/X/lG27rqd784Bt
QPx+g4H9+8YbfSepT4q31JKNCcPPwg+tgQXhGK6E/DttdbjwT75nk9y/UyDlD9UHSaDbhSgzGrea
4W1K/Hs2gEI+0hs/F1Cf5LwC93QOGKbSu6ITmbj1eKMOzQjJvnQVEEDGFWu8J0A5PTzmK8XYoW8I
lRoO0ld3pHIYLTtOv2b0u8W4SgwICWxDB5KepGRRJHraWw5fWNvrqzi+8engSa8+pDF9OTxxFQ0C
3IYP4l8KuwxGRJRPwVAhx8o1v/f5i4eRzk1UZs5pr50NMJdZ6OoPxB+4JTdfgXQKeoLlgwRPW/HW
E8knkpNdXr0LccJBfdt5FkJtrIOTiYauAuKIXGCpfY0uSLqfoo6EoIZ1WeikkxBnUVQJv8hJRlNr
2dfr7FpdianhLTcKLNLVQ+DxYfyJUpBm6Nx+mdz/6rIHEdgPnO40n2kykEuzh+U8u22jvkm+xLtv
zTydY77yKOyDzVdxL7GVD/ln7Cu51qGaTp9uWuNtnAeMF8PpZoy+GV/ulDfz7buOYMqIILTuafSf
evAcaAhDHr7vopfwnDbsnSud9k2NHR9027TznFZyHUTOZFDHtOplmPfx8BuRluxZ+z2Xy44VpRUZ
I/eEXYbxnJHnL/KPlZVV4I0aP8sWtHVDepszIfYosSi1WB/0OIuvuk83wJonGoEgeL5ysighVfVD
CFcFejwJ+8No7t8X21uQry3RthKgdmSOTjL3xulxFgpkNnIzBgdOx3HTmTrCH/XYsM2sNxbj+Fos
GMk+/nxmWy78KBaFvaUZebQUVvWkud8bJJFLNbXVsPf9GKmIKti9L9MAnCs8ErOeiVT/YnL9eOW/
jngLP9UPTqiFzJFbJ2jydAC6GTzkYqtvaAFskWSIpOQodGAwYfBKq7EYbTLed61Xb0F+sy3YDQrN
y1duuGv64Xp+hW5btDnZFe31CR4ftd+tXI0PbPo1o7oo0GrJg8+eOMnKCXJ657vMP4rqIsEP05uM
n5CBmpP+VpEdNS/kMWYmGJ6Q1jJz+DGe+Ts7bGnIKix/8CbMUq3+Oh+sgXVTDxbOzqYaZ6vabehI
wiAjDOK41gahhbg1KR+TJejhak2QIDbAQ7BoF+gpYAbllWv8VqkNlplxhhkozr8riTJdXJvJOv3G
wr93WtrtA28NRWBMLnnnpjZkFAot5sH3dCwHdKVU2piaETibsZAMtY6Ctcy2264/c6vgEnRgiFJv
pacquWktIVzmI0JLTtQpiC+cqaDRZ9h/R10zkVmQq3xqoPxKRbdSpFSRRW9pcMybpbmEWR1GWHxh
4EEXHwI04gzhqnGEipmi9cES4APbaIw+sWrElE/Y0UYQbwoBLKLAcyzdACw5SMtQDpe8TdMHyzIv
Wyvy/mCVvIzJz6gNpE2fXltYhAaPQR/QZsx+IiczVBkRqQNNgLY3NLgespSroHbpFGrphNo1rSwi
XCrjtut+HwEG0xIbTAN22pVTSytl5Vp6GIJRzYWf9bxjclRKER7BpUEA0eQeF1FAF3tLMVQPfjvz
u0fawzNYwGky47THoEF+t+xXzQeBBf+0PX1esbuOl/BzGpuAd3x0ClOLKMynxcKcKxPfzq6daqMy
mqh3fq8xlu195ZGUDwmeU8QNKHy3nduimrZ6109bIobpQ0fMewdfLYIq9bKy64AAWfsI1gtD9cHI
ML5XA8g6Ph/SeOXP1ukhZAUCT3YlwmfVAtivCoQ1HQ03NVnk9xQF6DSC8utV8vWd2YQU4Jmf6pR6
7+3zOHqpstfmGc7kDehvWUvmsfCTkXut8RAMKLULqharYvheNUXkQyGQi3iS6b6F6vFQNxr4vGzn
gyuAz4cID9hJffASVI5G8okbxP9CA4IJ179Cmzc0DyXyAyQR62ACE9FSQVhle2+8tO0jkKRTDqAb
Y0HUID2mEOm7/nwwAuHrk/s5xBhXcJi1pH19cINzmDvIaMDLObN3ZwjhomBtLG4YzVXTUcrBB94T
cdtDuArQphbRa1pDPcwLBYSf6gj3DtRNPZyiPXoNje4tiYvuNnATpQCEmGowFcmIEpH1BeQgJIcG
BUwV034ZaaBrNAugxXT6U/21sozV+KsTXXeVNThSWF2MwfFUubLeIPT8iFsKpfTANpPb8K2updOS
/EB01LRv1c+fGfhEC7MIWBmtWnvMzUSAMp2JO95QvYFgCI484PHKApVhkfiUgNcyli4uvnVofFPD
cjwdp6XWWy65nPyKX8XAEi4mjfhQtNb0ds8me83MfpbT9Cx6LEgFimGpOitAZGut6ydyagfPlELg
cnWt+yZAW4cQegmit+SErD7UQXJGl9nK+ws2nvadOwFcXhFj/0jztvPS1wExZD2ymhWmlJ+exqmY
ACzgbTl0VR+gomWrDtCjUoNeTeMgkMBBhnwnbKkIWmXlJfRND1kNFNN1GvwbXCrWM7CKN4H2leI6
9oLH4BHEikcBkDcUzsadDDfXYIxrVNowryrCvEqBi88LFi23FbOuPtAShlqCiFWirSxmCrlJwmhv
4cIjDx/35L86Th1OI/2OgrXoX3TEHGGJKqcjjXFuyYfcfNVBeFzvJPngiZhjRwV37JLc6Oo3pvBP
P1oMcsuTcQsnGGm948SbeHdbCO/6K9rB1SROjJFUCAVEn1fEmVDytsnuX+IK5SHlz3G4++3uePgZ
KPImURdy0wRp2Xs+HQO8K1UEB2dndZZ5tXIWJCPzWv6avCkA52wMUI84gQvNLVmnAx1mXPCu9JOx
2y9cMYBZ6oghC9jqh6Et+6klxRD6W4yPUVJxDrQBdadNnUtA3yCGoPzjnOAqQZX3jHwQr5xORbOA
nYh7jmc2hPh/aZdm9YXzSKQfrYRUk5qoZSSFeMi33dZZXrDMTt4ZxAjyvBcp8ytxNk+jW/6sj9rJ
Bzt4AhNKHEbteCxwSaE4GHmqEngHTs/LhxSoVfzqREysGszOSEb+eRpSR8tm/46gYLA9k3ldJdek
QHyL54HS92+6dRLlXFZHl1DSnEAkYmE0gu71NfdOLcOpK2O5RgFI5aRhGuZ3+F33H3CinB9eFyC8
4/VZQBbjshdrW7ID5HwcBSesaGM8/eBd9R8k2lw+poQonXG0/PCNrHFPE0LCa3y2aYHTsYbSWNo8
rM1Ii96r2z8NpnX6lipsIi0AU6R5bLH8jGTeWMLOutqjfNLzZZhndTnTfsDpQScjxF8GEUNEqhtw
M1B8te9mmd85oq0k2+hqztTjrx1kLBSHdR5GQ+z7VOAjt76ZHjGq3z8EFmQszP9WAQqXq7+Q7mJq
ksMXnQUqjuR4pAohWQhKOz1Vm4bfDwbX9wmVEMub/8VsRwcgzKARTlmvHldl0lfnTiBiInx/F+Ua
Q8h3so8ocZDCK+NBt32svzZ1h4vLfbkjbVJTAyZkGuhQstVWNH1jTY8weHQzfTWRCrimvvigk9aU
KAoDjygeFFBjU0F+1HsaZlhx7Hh4Zl+LvdynMBAjJMf0P3up2EnzUi/XmKHhc+l1z9KQZ6oRj4bL
lXSP0WQhd5lPX3dbEw97vRfzV/U7fbVDoKviXY2QWHKYDOsC00fazJhzmEkPLcl4DYpKGuBzDQ7D
P9Dv3ewwcrsgrcRGEL5vazgeBjELMHlA1oDMRG2erzBH33qlaH8Wd2T6Gn5ZBj90Hzgnyh2qCsM7
hLSsfflrHKAR4VWT5kY4Lj7yx0MxPV04yTZFmPovGXobik+/ZRJKcb764ZxmmOtjOf/HZqwrjt23
UkHrCJ5bLdVLvXsn3HHuMdDErK2f6lvR0GJaKQX3f7Xv6L4rv3gaJ8oa7ffgQmHsCk/pz8+MM0yh
BkLzmt3oNxd/j36kpPgrng25bnHwyZVUm7b3UGJAxPMhbrMQs86sOE5kOaX8FJcWDHmIMRhQporb
xYVVUItit5qRMpKdZCt3Pm3nRhBpxTaVfYXpJVCa9w3wmip723fC/oRdkjcZvv3E/YLMgnFaHbWH
O9Fm2x1PAtL0eSCNxeDNhOlYIgGiD+dU49LUTZ/9cOfDX25/XvQugDQGPh5HEy+0Ng3leVCdTfQt
n9bhosXIGVKmRCXFsphiKKWAe/NTPrXjDfXyMnZ0nBA+keQfGHO8Q58bh6JSY2XVx3/B1hvh9X9q
3GXzXppFc/hRt8Hiq0UfJW4efszSr1dUNnTvpMTCY6+TlF/EcLcTAI/155UlXwIIkSMbwBRy7sn4
fYkVnjRkRC4kILBhhWxiikHxpJYwit6TZnEZbsUUwtKozArxirbXQcj1zeuGGdyhrn2gEMCiVfsW
Ivn/0Z4qJwUoAgUBThLRstcB+QU7Kmi951YjU9ZYqJGIgHKtRC83Dcduw8zVl3ZKvK2xSwE7r4t9
d+zHeT7wva9ItynkdyS8to2fZC+2HE0MN49mn0A0ULl4mLzPeTrirY8FDFpc+4JHO4qxVEQJ6s1N
xpxhlEiiYN5ux9SXHFKUYzfkXVzoGC14Jzz2flqpZLHYPVLazgR69O/7DwtiA8CqW3m/DezZkWOb
dwzCvIhkSSafIksH8Ttz/Cc/LfAN8Zlf/UA/mjRNkPlIU6NghxGpKMA6MgHWGBajH/GjKw3OZZW4
DHAoNnqfoTsN7VBk9HppA7K0Q41vsujmlsy23F37PJVUKG2r18cBU1fR1SoVgpmTH4Y7goSzmnjw
7qnUKgLVOLy+H821KKlQgiNPZXqDjh68BUCJY4fHDztkUyKqkbleEs7lnkdSuvWUxLP/SelVudnz
S5Vm/1S3sjzEwZ2XmdX/+XDQv0v3dy5lYnTuULWFimGWg4kZ22HYGRPq5sCyZ0/OSCz1TSSLkAC3
2Zm/mp7EMtCFJFk8bZgmcEs5r+u365fyslWhGQRtg0cqfMweIse8ZkYiTGDgH1aHZ5DP+U9Gu95p
sx9ZzLIN6zVeTKG2DtVKKbklHvzaX/llVLun+H3ZUw//EDBgcLPN4DRBnZi3StgqJwduC7OhWlsU
zzGfRFr+35gGQF4TeNAQrikg8yk6YXDIrYojcrGPal8GQh7EJgHlqRWQG065fJds3Zo6COvRmxoQ
pIJBwb7RDebQ2KHTavBMUzobW+odAAaZpcIsB/Gsmu6rQQcm6j9kzJ5xSYziKz4lhE7OySFF75XJ
9k/E1yRGP1hUOWKuqHlAr3hQShD8q3DjBkA2Y63+2/rcEpeyVFuIVw9hcsFqCUCGcuFK+8fyUXBY
aIR5zq8yXphmZX9nfZ7m8m/EUGXs10spkJRLAwBwat4LDqCKFWgP9a32K8tVUuycWmiJY21VDHrD
cw+UPajy9oNDv4IPRuBaJUPwoXsD6xz/jfkbUKA9kpyiTIWBEIYY+GT0lYSov2svb//aNIUplNtR
K3P5swJm3FYj/DkiELC3Z/rLO370gMJT8RsiSNHQ/nMIFJunyNcJm9lLp28tLxFoozmxq8dhVqu4
a0ZSQ/R2NfD+vUSJNOugh3eaSR3pF5vk0Bc79nRezUVZzhZzbSqY1hYFfiot4kV1GLq0rsJSF1ox
bxFzbzTRd165GS1ZiuPAXAijcy2pXF/PXx5OPcg7cIC/RRJjF21qPVOig5yuU4q2jdU9JJwsoxcn
v8aBW5qINcOistqBb/lglDRPcI4m8sUP9Z17dqwNbZ17uc2/lmBsGNiukvm26PdKsxQczTStOhZu
fJzXnu9ck/9APptXHovUt2YmHNL9f3nYlFA9Voj3KrnYKMcN+3sdihrPSWI4CffrecIY8hfvFAow
rHWdCPHVQnMJA74w8hvRDYxhzS5aBj0VAb5xQ9drUKuchAnyb7EFiverT2Vck/KbE4G7vt+1zjDp
uTZnDlD2N7gkCSEHw7tpr1ZkrRY69IS0VhtkdsiV+/tQ9mb3F2WeRDZKw9W/7bowrTuovs6CY/vG
4jkd37W1B66Suxbcpk3wqVYq6CoWgK5Lm2830V+jDZ53QtyARvclWV2Fj52WFqndtHUUzlSBg/wh
gv92hrgnMhYljgk3DTObLUe5FbzxAcmDmbYFE8SwK7FIXt+hZ9FpdYWoZe+upeazRKTOkMcqied/
86HNlqICBBDf6rdL+IPVh4GBMIUgs4HBl5k/k9r/fvjIAX6Nc7P0sMv3AFSb0ATbNhS813nFp+yb
vYTf6MHgD0B7PpP3YpM31KLJrEFRdStEdGSpWWCB+6UDhZrL8KjmCVO8qhxfg0Zsqf7rpvu5+ZZn
aXd661AfuRCAgi77Hbs16rbYPLC/+NXqdJus8DxZ3MJeXLC9ffaz2+DYH+/KAlQ8rE0Q0V4c5bkU
fa8X+yRg1ExxLYNOB6yxLowt/SRTkEoDBE2wDywR9lzCzQhqnjzqXXR0CHwXkOBRhqfNq9s9Lpow
iaCf8naK0fg4r9+cPlbzTcpBux6QZKqvoKTvy8Fg7KCwwkqXEGzq/exsWDYz6w0JQGjRo8Emjr9Y
NB76Cj4kFgXq0O/Z5QedmufNQZ+tjihkGKgCuMz8q7zDZlii4R2zZYZyKd6oFe4E/Y8vHDdTpaa+
FFxULvxAOxy+g7PkPOHSlHIyJp8ipSxqsnTMWfG/JeMkN760sMFzx36oyi14kf9M5IxQpp+/r7nE
+RqHT9KjFZmDlD/si1y7TGtPRmDrMxI39CHVPFvuDDVz7DP8QmvOUkreQRl6Z01aqGKt3Tb8Y03S
YUa6PRUhExzQRy/Ro8/79lrW4YBlxQbkFF1dv1OppvnKSvmjIL3qKOG6wgEKwOgBoORAQSBTQ44o
adNOQgW4pI7HsQ4zj3lz5Eh9iJH4g2Wcqwxf8ow+FYDguw1cId6AIZSAj0nXFeNjhv1323Ae9E0A
++wOn7/WPNeOK7MwpD3bG6yALJfwVYH3Wutv19ZcVEtHprR5pkxcQdAp2+9tUbuFk83P3GLlDr9w
QjlnlZNemVE00bcJURmGuuyiLcYP4nF/ELsEQ+5SH6dYCrTRTiOt9zlR140V1T/N4IQsQGdLkHKK
upcEZ5Utyr3nrr580J4DIgPP8IyXXfiQHE+uiMRCSJRm8BZIhJieuZl4qrdR1pIe85PpuZsAMOjC
efe/LSe/7C12+9SvpqoEzkfdZPVIrJRJe8DYV/g9sZZaysYE8wRq8BNuL2W94+rl7ClcQr5sg1X1
R8+E4ZW1ZZ8DzuntmNf5u0fbARkqa9zYh7oqvcAZJN6njhpiEeWPnV7w10rjKjm6hWf0WMK6/04b
ucVh0/vqhjr5e99zCRRT+KfIVtMUOhGTENC2JE34ixNOQ4CLwKIZJY5s/eeCMOMXyN6YYlARHAjW
leFxKXxl8w293o+kkuJkc06BLyx7Ss5AEQe9aoGw6SDrHNKoXfL9JxF3f3OwUuuBHQ3jpsgQuWXC
92UoEpWEDR/0JTkShMxLTA20kKGsurdYhzxH36kdWewi91ZzMcR70dgrOzRiprpFKg3m7mZFFExP
1u7sOGHqVh5aOEt8uyEAxtSG6YzTmmELZbp5BEGMcQR4ZFoJ0nm/N3SLESSjuCNmDtXz9H/zW/Zk
mw4qD7NP/MNMsLMesSZhaVU+AdXLrbdgwrvcC8nzOptIAAq5m930cXgYIJOifZKu+QC7EDNqSg45
h27rwynyZNurt3WNQ4KmrRFBHxeq6LRuyvBwdC4JJ34nZUSNr6qhojTO3H27nbuYjs2v0jm2UZ1t
WobLvpgSIcsWOKSORWG+hrnGqhD2B8AFYEsWZpPPlSbNcUcgwSVwGGkeex54I+feGufpCxtHgju5
95UpzE3p4qZhYnPhx16Yb8qAit0RX2BUVg/iG8X61i17APNkjLS/xG15er0OixRSJ1Q/DmlDByns
ki0EBM+isEjzKJh7EMsCs9YEeBBTQZ02ebTVoRIqDdl7HNx1Qaltr+J+hAzYsReLDu+vOS9NG6Pv
CSdeMBpOw7v7tYq1Bs5jVqwNMGJO9qpur2dMT+08ZKTkNNDS1ErwaN2MV67KEBvKBm8XdKesJq5R
9hjfea3G0uPmZlyTXOggqOJxGhJ6SgzIJzGbBY1bsFUsT7Z5X+7/jYTgexa+KrmvsCzF9EFn8CR1
sBtyQDcHA+4+fqsJ9Mi7HMv8KjChNJRnvArFdZOGVcshuFK8nxE+jgit+cBPEM+7jrl5MHiT+lcz
qeOjaHrwYIDgf13RtWpXYElS5HkT7r4QnUNrvxxFkdGzbxPIq/ID1jFR0PyZHrNUjZPaNAzc8V/s
IhOZGL2eTx2Q/SWsRXW4BgNB7GXPYWM8axbJ+2IDupOdGYj+XX/V6hmFuVz61Ycz+NA4L2ch7ItA
siNKBLjXe7l11K+v5mAsESofVj8mCpMOUHP/VnM3cgqxrgPcb4TVClcSWsoV8BFRfnu2yJhliq/J
tVt0ySNcTH5Nd8dXYsaxyvtlo3BcYqLEhmPeIOQsAY/p9geg/YBz9JMsKaDxZNfLEMST+tu9rnQe
SSTn2cMmDGJdHFAUZwWB8x6x1wE+rFThb3h0KskPNDWvVngeCUr7qbu0dA4nVYRyvz2kk+1Kq9bQ
Za9q2AytrlhCe5QKEUCg+q18NETeFXBQClMgkEVbkXULHEZnpHL8NHcQYRfGyXjUgsPuOS6TfWo9
BF3QY0CV5FN2hVu9OOa5gcnE+NIvHb+tQg2AZ9axjgQqlQ2mhztoSBqKXa9sDM99ngr/y8bFum1s
4xHhJ0fvt+5Q92Qo6V6DSz0s5N/CDwFyDC7Qe0NVuPakmHEBi5lrScN55tDxjPq/XgXDvyL3F8ak
QgJqvOhXq3UBDiac4s6qpr6upulqKsCnS6llVQqVZSCCY7TXLQZunndISfOj9560iA5hlu3EoM54
xRAUgasIKvZ89oHFFbqNGcUE4TK3aqav7ug4+sX26JcNrD+6wEKVYwXnofPYkdK36JUG0XM1Urtk
EMg6DhXexpTGsLKBko9fwoTaGmjEbXc46yX+17cLvhfJFod1og/1S4Z/jMGAjQ+oBSuzDsSYImWk
pK3572O/HMx2LGYdmClvonKe0r0/YXTxwlRDcegQ/SW49JJya9Zoqh7ZPu+c1cKEyU8AuEAwKvKk
jNSjHVQav43luvrvSnppqD0gQ57lc2yYevC0wZId3YC/YpKuJ9usi1Xcb/Q7n1ZNqsM2DPwBF4py
hbCAppDL34HZcRK/WG7ZlJ8Yn05oy7ra+4dT7JEE5IT06Q/BsEPspHZCUH7pHeMGlUhC0rYOk3Y3
WvHFiXculyxrC1AMaSsaREqSraicaphy+mphgMPNmTyjF17AxhEsW1WgZ5ngMf+lHYkj7wBPjwpk
RTWBGmlg/6vH5VWSQZxAL446iRgPfvYgp8//YOhM5BGArn/tphuiVaCnXpl3GEUFUAvEE65L5nli
0yuQ+uCOpqTGSMVsB+bUVBdJnovRing6X0TW9fDOFP+btlJre+FLZ8SFrgPT8Zb+YV5lOJ3FdyOC
bI8PlPUfYRaNKMJo0+ucjtDVyohnRkrNTye5tW0X4TRWX56rJREEZVcp8Z0Mcr2DVgyaOy7EV72g
tdEw/FcNQUAGKXJzpGUmL6pEaPzmXYpnNpzAk6xusIOonXcMuBQuoCAg3ZqmlGD9SBbVeGzmqK4T
yifIxmS9go8l++bfZvkjApJ/z3ne9sMe+1wG8HYmtGpImwuaB1jsSKgZYAE9H+i2c3hzh68zLbiJ
5JxGtZjC3yHhOaAJcf3fufGKhhxxBLCFEykruL3b1RJzmPzlBOQjw9Q8i+l8CdZ+9dD1dfDrTFVy
/oHXC/OgwsQuPgDnC5DGvp9O/QWt/fBBvKUrwvKu5+eq/SVz56ndMcKhZvzq9kuJR0TWwdkHFQym
p8cLieIWxWL/OFUAyb43EpXvRqZqTtuzpZLJEufATlXSmHq9VdZVCYC0amTQtXO2Olu1j7sjwFE1
wfVkFKMf2IvWwU7dp/2tSSS9kGg/2IXoTdVPNS4UHH66AAPQ/s/lY8cvMxwQYCmuzypoDiLSALuS
1IFXgYBAypDVlwMo3MmBD2B04SKGJnEQK1WDL6LZASKel0P9XL1XNCbdNCGAHoTy1u4izv6bSIUy
CpOTQRayLTJ0gt0dOC0rEse1AbOxRG1NLy2d/41eTrChYV+PLESmRb1tBhKEXoPQPNKlray1umUT
vUWXNkJQsRbLhAsDHZs23HVx0ncW2DyWGGmknzOnHRy9ZYfziP4z4TMzNy4fDrk1fN+IvGgcBtQO
OLqLpnP135gpkUFVUFjeVI3h0fyFZcwPFmMnJPu/LYq4Z/rJAi0VUVk0/5SeiTp+jRsSDql0r6h8
JOflHUIIaGYco2SbttC65dw8hWSQ0sYHlQWpXg2kKcwajK3btFWjdMG/vIdOze6AUupWJwSb4zjj
ZzT2dgs0EHLdXlsRb3fBSu7rvqj9JoU81XlxfnO1iRnxOYA5IXiApcA2TMdEWs9VHx1TqYIVjF+G
y1zK7dNyVfUVr8Lj5gbkUGdeStOP9QvzS2+3v6xJloGPoKcn7Dr8AdXcwrXL1g3U5YVTmqq6x+kN
QEPcE3KYm1w9cSv7HJdpzMWfDfQOTgmDbjN0IRbQd9zHdp9oMReWLdV0votxlVLEVU40W5HvZpCK
cUChUUXP+9DNjhirdLfCNbNeVxrnN80id9Lc3viZe6xCK+4TmXMxnPBWXTVRC+k13xpcEZzGYI5b
v0LQpppagaUdQJJtoIpozu9bwQQgn0yW/mmFWo+ZnBy7TE22zTJhRWYrlO0k7tDnOzjyEtDYmNoP
+BBFhdmWCZxc0+ydSd9QsLvPLJt9fUS3IVlk3QrtT6Od1bEr+ZtPQjqXYyU89PKanP0XCIu/A8dN
8jRBLAQhBQl56oCKi1dF/gobqPw9BrGuFpsUTLhIYIV7MYAxu0NA8uithynf/k2vrL8wKSY/XSqE
016repOEr+nVP1hiWM46KIyvuXgA2wV2Q6OoERlgp9LQDMK0eg3o36/Q3ZHIqqTtSEALLpfS2VNu
+JYIQSWLF/7bzIYClH4iejICgGdLiHs65/vsPVffXSO3GlAK3m1W4ZBlmEUR67vvCED8TdVWgPlD
hZpOdBZG2M1Bcl5J9amtypEPINRlTdoEa+6kXE5wE7he76+UDwNI+m/8lLVox/mwm2fBCWCDBgPJ
Gr8MGiM/keV1woEZ/fliW8cE+K3kSSiwwT0vd1fFZdGEYQyhxgx//j3a6uOX52pC394gf20eDH+6
uSApShJ/1toCnLMcU/98A34S/CNYXBpMAueltGjISPD7p2StaEjKs90/OlOTLAobBiT65xB0ZlVc
yudGehZ1YE+d+Mm8XsFYHRBY0l4L3BhhqXk+Er85iyH7dZ7rtZ+Dwh/pXG+povuURzwI0hCbPJvI
MkZjUUc686AK98zpD2+4dZSCuHkw215wI/P2+ZmnnDozjUXa803/jNF8kgokmvTn3fJB8XqUkfI9
eub6AJVtt6QgsyQdha0Fh3lrZw86WeAx3Q5V29XIIOGAKKiaj1p4nm4oazdnGT8fCaYlhNnfH4Ze
/efs+9Ghi+R+6UnjVOcH+eQuzqmwka2AJB1s94kCvMR+Bj4OQ8/lgv8JwYqP2pScy8qQapo3DN/b
b7btrXNxT4dLfIf2M9qUB+kaUGKZkPLZbge0/yT/X9Ptc1c6QPwyfyD/tJRvYcAePqZk/uXX1hs5
l2wL31cG4YzOeon3zgQ4vOuMLK0cMPLrDzv8ZmUf5Afm/wZJ+iMAI0EMJ7aR6bYXw/QQHxG4AsgS
4ajk2s/nS2W3z/X1L9AWUY6+H+43Hgq/TDexGQ61DWkZjpIM0IrClBEyc30J7UqPSrh/hXxqTN6E
HbNEykbyoChecvT7U2+rT1oAqq/oGrhYkrTnzi1MMVyW7Ifj4sutTjf1lM5yzf7XxRM+1ynkLU5s
lDkNShkfrygF2g7EAnUjRoqagWlfd2pN16HJhvrrnVlHoXW2NB15QqDo1ddEnx044Usdomh0jEdL
fvjuKxhFPVMXPDocO/7F64DNc+6AbYlpRR5JYUb9ipuySAsfRojHqzAGfZDz3zy+u1kgiAE7slBJ
2o6IHhCuA0dooElqNOgxuS6cVAl7t52ljquo89mRFqo+BGOjlKVor4vwF1zYKzdy4YvvUwzVvyFZ
ovEhZHx/dTaX4qmpAR9401zQZj3c0YUfYi25WOlGLIEElkEOpBOCfAFWkpJOQ0/5iBHH8KIF3mnY
4GvtYYj7sF9PdOmOPu/S+AH4KQirNOgvYeLBuWrXP8P7kY62VceQn3rVU7kEurXGwMV7+FaLVBg8
7Xwf0Q7RskriRxmkA8AIRAwaaNhS6XQRg09VqApgYXUCF3TIYBiR8zW9RuoAryJYi1vs/QPJMAOR
kwBfeVzAtL0uGoBVTR81Kt8G1wzZZLF74Him5ZXbqUZJ+xdlOhQ+2YcipFGcs7rWcimQoJ43JeJ2
4pFB5cHBZWu2wc2smiCcfMcX2U1KgoT/apUN94TLXDJIrAqqaU6To3Fgc/w9HHho7EDp2JiPN0GP
V0MEcpiLx60DEQkvYg4oLci1p0KQoLysd0j/1PTpDUkBH2bWVopiFukgU8ZwsAf95YktmJfl8nIL
7qRZpmkJmPGDo9gPYvIY2sFU3lqFGkqoWRZ9+qplIODO38yj+cy/+UZlVr1s0Er+uGcIH8IuoH+t
93z8COFt9KmdShcvVgiwiK/VGu0VU0D6hFC31p1LVCop2pTQvw2gTD40Ey18ZKa2nL0M4hrxU3gU
27U6sluI0xzHaef2m2JBGYdLrYaSOTBKiJwanxvl2SdU/YzpGYX+ogc2gQT7ziYZer6+PDwaRpEu
EHcdleRg9GePTX1kj2ocRWrYOWjmrLb5asnrXtoAqmKqZp6GeMoFy88HSnzj4JSRbe+v6nppbEQB
D03vFqSQhqUkmv7o9T+NkFrUKIqNlOrzokiv8zjcR6Q+NseenyEQmft6lQZMGvL1KgxJRXdwuMQx
GoqlkuwqMXH9we1nqkCEwZEvvDnVqF5Q9fJzdMPVAn21A/sdPqQ0Ol8LEN3lg4ilbB//6TZ63kmC
HZbIUAZG7wQUndtuiKZmLswcfkj7trmubwtnDYNQFLiIEUs3K4cBpWq4tg0xife9kq3BvSc4XGxY
f4yXP5H+oN7YSCGb897pyvfOecIzKolaWIkyZmyBt1DZ3HTSpB99syE4wh+HH8ufPpMMNF8eia3A
j/mgTU2oOoY2b7x44WfFlRyu3xdxNIXBuCj6NF2JK3NJ8QtDClGH5N4IEp+jkPgK6PstImWX5xhu
guAjsN7tvT5rAu9MQc99EyzZpf7jQfEluiF76Z+pTH19ZyY2qbOsgNafL6zyOPa9xRwSwaBPMe6U
IfnORWTcYqmFo0+AXFqUKTdwK0q3S3w3i4D6+Jq5sl6dc79evSmATclxAx+wGTqKsh8ciQ7tc3cx
RviQE0Z2APkhQwqe+6/5U+92jJNKgbtOrXZ6tQbUsFhNOhgSRYQfglXGX0Yn9LTKqmoKn+xi+6fN
07ZpTAI3/rTufDfP6WCN3fdEX3WCptgfJPqT7ecaWVFBg+EGg3mx1WBynUxxvKP1QaxR3H0cW5jT
4bqOAAmUSFkORErg1ildCjHLgl/RqMAysUTy3JAZ+Ywm0TpUk5e0fqEQomHSjyM7KHe5Sdp57D/w
MGBJAtKTXc18J2o2WdbcVaJcdhWhpYsa1ATs8PawE7nf23xSj3CArRqbwmf8XavTuUukTx6xQ972
PIKd9IKqjjVoCzMEuXGARgUeuLvyyJjHyf+ortq1PWA8CUrOtDoC4LDNbybNOpu+c9wm1dnmezut
/Nz0byAcEeLEj+XP8iowfd4kGPnJe22A/mbYLao34jUUfNdDA+o55mVtsPHfFaw88ixk9WGgK61x
NELE47QMM4XL1TA8DocdcQX261BzU/RFC82e+HLMAvg512R4TfCVuJO7QHlXsKNIrlkjFGN5cJAs
hwE3SbgoB8OCqF8hm73UklR9Fp6rfmnXWQhV3Sqfr7zupYQtjqoyYYfKndnUvzY65NldySn6/8uG
gZa3TvfNaljXeXqV6lHLmX7/hHInBL4hiuPrhDDMdVKQyFJWIEjrBddblMRBqg3cCUS+KUOTSU5U
0wkyl7dl1NtxFMSaeJ/7IdI+TOORv7dswSH3wOXG53HF2BUUzNuNB7OIfuLv5qvWZs2M6W2O+/5H
gBa7o13m0cW+cF44GPMADiU5hftaiWW3Frfx1uzZ6Du5YWZ9z7IdkGpm04r5lFTm45Y3FX76ltGJ
kpEWwoeA4MOKE3qnVq6Wew3XTUGYzTCbVAT5dUpaavGJenYZPsmhNjrDAd/R7CM0iZ3j15uzrjCX
RpdlB7lGUqoRbydU79zSSFu3HMNGjLZ5RLh/C7kLEYgfdDbmVErO2dXS9TU7x21XKXKlDfbDvJfo
xFD8g3U9/r/fI822oihMdzhOTN6CeZSXAbLmnzE63mUa5puEtkkRaoLDR/NK1O8bERqWPqIObXm4
Q5ibFaDV1CSGR0hEWXDAO8QfO+MGmjLpXNAX+juyFtw7SCgr8d7gYTZfOC7mA6yuQ8Mmq0xCmZZN
YZ4n3/f+/0EYe61WcUuYX2MaoFZjnR6HbQ0YG8RLigv3UzY/HJBdJpH8xbQ2icmlGq1h99Rjn5X3
utbJh7JoRpJYlGvogykcHFLWtJ7Ag6BBVxNt1/7IuQDLquywVvvRtFtirQkvZK6Pgg+Q2Pa59OWP
fNfTQ+8lawT4Kckzfx/AuT0t2vB0qf2I6l7K5zDOLy6WKAMr0dOih4jf1iT5p2uaYIBn9R+Pm0wY
CI9W9R9eSHx6K7WsE8cLioI3N1qNPzvL+LAqwOkT7Mk4GyLXAr+nUAXEGiAJGhyS2qeGZnGDl1i1
jtQYU2rITZbPiHvfSAP9Qm8AOt3enolT5YFBSsvciiQ77vYKMyW0LYGDbO/2kordSvBIOO7rBG2e
Runp5ZD/uruVbVxBNsddA2Mq7OE+3udL8ZuFefJXxCzZHNl960QCtiVKYEWSp/bpv6SabG7uCwxP
gvbdIX0sHGwaqTPHYvPH/suKJzdqNH/Q9JnUaFTFDK236A6YSVZ7YJzVmBOP7kKWl2uN0PSEKUEP
b2J8LlmvmfGeDygy7pdja1dsc6PN/uSAdSGzQ1KiGAYW08R5oqdMJ3/uOe291j02W26bFkga3E5w
Qv2Vu9yDD1JXywqU7LEKXjfzXC1Rlo1ihRgaQCvXLtrHaU29+6Ix/jN52F2wiVgNImtnozWTD0ms
L+vqTNW0vR/1x4w3pWO9VkfRWK1A+xhdaUX4df3TVQacbAATQsmvcQ/IXe9kCASt9aHuOmBiAKSD
ySNREHWzYJR/RhX8zzur8wNzQZk4r8HGGatZ+TEH6P0PzrEOl6gzuabqISSrfNsRBPv5XreR5XE5
pbi/W7d1PqQdluwH9YuDwGPad4nrzyZL9h0iFyKswZLJ+pd2XQgIRE29FQDz1YM3PJLGUx8o/9hS
oqAy1rio3Q+qVmkJAx8gTSXhp0qLpYMOYjATdRiUxv0OrRetGG+8IrhvvgRkjEr2cRWtK8G4g25e
Dc4La4uuat/m937jBYg4EPP+p74Y7Dft16O4g3WWHQVjXG79T7oqcwmaNzeMatkoesIhjCnNwM6o
X6t7CpFyMWL3QkbK1VK8p/Ww1xxMEJxw8xpQ7eYgx7DmtfheDyvPVzG9XS35BBti9Ltiq/0hrbD3
u7m2H4NrcBOBUomjq7wRorY3xiOvVhwVrvR40zHZVpzlwKHhaGBkmi2a3+tMyINTpqcS9ZaeyGkG
O5FBCHL9r/EZfPuuzlIJ8WmZ6yRD4HECpInAhIHqegRMU7lEqZYFBnphtIv27wmcF/Yz6lfur2hy
yHuasUArDx6+Zb3P9GQRwrwDDg2gPshPUKZUaPx8Ul0eufxS1vE7+Hi9cutVD0gHi5Kdi2zmr2A5
lEW8DhZ4esy60SCPM8GTc294xKhZgbbbbhJ86cvZV03KLo+Bca77aJfgTPn231TLxZSxgJ9BryRg
74PehyUzkb41625H20QaK26zUHyavfCRaKEi61byhhlHGx9d2aDYb5DzjEH/dYNn77Ztn8E6blzT
I1ktWqqPzIC4l8+lOH3+wIE36qz3GtLqz9pCgbfx285pGOfgG8NQWXFn2tEPK0gpvHXz5za5wh+w
VR8mU/VxVwaFKP9gT+Q+r/1Rwp8DuS5fhJPnV+S6IO4WghgjbLjIHabVwsKFGB/FFL9BShCUh1Mn
B1hoWShkWYuwL5TY0JOb6vmwrwfOB+HmMdIcbpxowxZWvsOD0Gk1v9LCizPB5Y9TVkRpz9+MSCpM
1Dt8vh3ln8H1IlRN68mrzhJGSrNEFna8vO57GA5CJS5MBLMR0vZ5n5ZiHw2zDCZ3/gPBEU3Z3/SJ
BkpLH0KYVh8DZv6NPZ2dGyYs6ueO4MfO6yi02PQAH0KybCnFMpaGkvrTzXSOSXnpeIjT045/72qu
7Ni3oZ/2Me6T08jYDzx7WvRU45fUphmB+/NsWEy7hQY6mKWYcjffl70uv+XoMh2GzYkmQKbJ1eIK
0925TQ05ihkF3sntdGuhJ0kVgQQkIOG1J4p/Jes+/BPppg2sIV2p8puR7vACiUbTSKiV3sZtfDPa
M+fgkO5YmV0PcIwRCLd9fImtCdVn4fZ2ULoJhqsXof9Hys65jxZbipObe00Snm05H+zEkpQx08ih
COncldHyO2XWVdMehJko11iOTLzMoOtTXiSwgYT6yCiXjWL9pVRPeCwGErHJixecEMsY8bZYj+pX
zVU1DANvppM2Y0TeDS0BIL8mDz5qAXxKhXwJUY7TaSs0tckLovLVnrJ1yZwXGdc4L6AcuAPURlZk
1BY0Udlqf0x2mm9zJXLhn/gzXtrXujlsWWkks/FLTt0X2PMkuHDE3dDNDKXrv8wWa7nfAJKpEsXQ
vNmJeSNmj6/k0ZQ9TLJw6jrI5VrOp7FqelN0M4KNFlkZ11ddVadGmsNYprBd6/XnWPh8EGVbqLZc
zc/8VOFGqIT54DDMALjGHMwlfER4zl0CylO7cSfxHZcr01M7QHYGJwgU2HRUlHKxG4QM3+Hk0hil
UWY+6VsZFT4JRA3tHqDKWoXCFV9BKDQXoYbPbwz4RAYGufaNOy2MVp/s+MHVk3DTdNiGOdgGMISW
dmeeho1S5n9DiWqcZKgv+3YbcZQOD2V/bRwVmUmXbCRZIYRf5TIeTT6PhLEOwCrvKPNGub7ycg7a
DLWBuz+INjk77WtLXdADCNUy6Q2GcSP/e5naoPi6USqPgwBbpWyWxBtgD0lJtiNoYIVCZCXkvq1r
dFSzUryeuFnQxhsg1N5FSrl3JeMpQxdli7fEm1PiI5T/3gqZIKFlk/SU2nhTpAfi0kfvE3A7hCl6
QX6sC5BiWJ/z4QiAzcaFD3+ec55iK96nNXT5V+2TdKmuKQxpZTLv2DWfgoyOutzsMSS+GC84cT7z
Ckks2Gr/w4frp8Kl1ULITLqu9bH/WCtYF+ZWze7si0x2GvP7YlHc8NQNcek4uxx7I6eHQSPomsB6
HcqY0YuiH655ZtWDmhKIKbNhhftkeqGm3lSu4HdRyn9RcD5FIziSEElrdq6ClOn9uuqF0Dxo+xvT
PFXexCgBjea6tbRuVjc3B59t3tUJiGYIf4gGrogmmeGmlVDEYmFCEISAQmU02sMY8nmPpM49zmWi
1YAQIOStiaSHVxwbV7jLa7H1ThFisDEYF6wx1Ab13As5ddaCBlYQb6iD8fvrZ7fX1UfbVtZwmUgC
MmHdgO4G0bcJbkeyoc0VrbBVpdYNJHVtUO101ba+hj4Q5lHaXnnZy+36Vuv/3NtZdGV0sA7UgmgG
bXiSCJVPv67HBynNcP0yhA7YlmQJ2lzLwXSL8qndUgFhttSnfATgMvAPA19mw6H7Zt2oUCE6tBva
g6gQX7XkEljjFCs9B8p08MApqPz8FiZL1SXtUmGKKgvnb1eKFKuD6bvtcFswg5phR4R49WWuTBjD
ols2Pes4YHPgDYX+eFVIjao/GftWVt2IWiJ4f/xl6v3G3+/rJjZQGvUG7Bg6JceK0ZqYII5+jHTd
5uos95cYeR0z2MjCSGi44287DIn1rGtBcoAiDa1KzWBnDTXusVNp8HJP+bzxEog8r/stNBHIlDL9
U/uh3+R6s8xVDz1xrzo7+6vJiqARf2g8RpaNomrt8MBnyQGCAxwnAbkOjEf8RNHG/EfxaUF4DiCZ
VwxAJ/KJy3k6Fwcq31nQX4hoqF1i+r4i1/VCfVnJqOnOmcAA7aCbJm4zDbub2wnU3p2QrWCN8WZo
FbuwXFKuN4Ifpot4Vns2W92tW7UTK8Je0WjtoHesSKijYZ5CeY62R6dsgcblAFxFJSmIQAag/WXD
bNml+PO8Pd6fimJXQhekwUTOywUPwWjmClslTBUaqihHcjehSuFhZ570Ur3e0sAFNk4uJsj9iLJk
2oH6mupDGd0np7JV1ncMxUtnJKzu37ppOBIGoILXbov48rVKWp89XAkoenkO7H8Mvehmy7Qq8d5W
awg0NdQdK6ZzZRrVnz12hUeJnm8s6Lhi69jmpm/2uEloW0bKBcb5l7mB+rwpHxZ6XBOyj0EAhUlh
x9JQvcYauvj3lwBiio3CwIKW3LfJd9sGSY7K43hGpoAS2ex80uucTe1Nvs+EEd9EAaYt8FaBUeUD
ewYOdmhoE1D5CZ0HtXfEO3JkB0aY9kJPnDZkFCfuxCQMyCJw8pFnH/1rwYEERz5cTlh9SAbaDH1D
sn3FkXS+oYJtEGo2ptlajKF1hs0sCGUkZJizFriv6mZf3/3yJwmdTd3ExmGDTmVZfwRHbpva9UYl
fNYq4nRgCBtml2ot5uuloF2ZzZz+FwF8Mcws/TbzTwGlkojtIROW2bon3PQmJGRMKDMtzH8Rf2AY
5c7iEj7BZBgcMYUdL+cF6mQzbx6uEJXtqGaGbqGEhZ0ocGdIjkWilgDtEKhwURFbshMzop0J9HnS
Yt7nvCivKuGpag60bbsfg9iKTx4Q30vWlJe9wQQ233WovEhMMH2Ck80wdYD6js9j8lYXEkjBNh3m
TLQasgn/0wxyC94QTeI90OLHewkfkFYd9R0RPJPPXyx6NEE13TlxBSiCcJ5Qk+2H9MmJS8EBqgw7
zth1NA80Y4Xqi7fRpg/2p+Y7TPva7+XopELMarixJs6wK6/CfRVGiWsRr3jshAriV2tlIfvCNynK
29eVc/Lq2F046jkNorxrEHUGwl6Hqzy4yYvpmamZXEawF3jdnaVtajSw0zBZZZeJTZvylhK0E169
x5d2KnZnlmqAUAnxdzovof9u3BmFV96lPFdGRTO6/g++0/hFa8dWSSmcXInoUU7zVBQLRzWlhSU7
YQ+D4isfTA+DH079sk8nbUuGxP7djkI+R3aA7kFe4B3q/5hjjWPP31i4Vt/ew3aR4vnvpiyJPZIn
W5zx5lRQXTsiPdycXyBmUDsYnkK8OS6d83aPOcK8dG8MsETHYjq0m9NPRj2gIFH5GlWhb1n9A28Z
KXbmrtLZhBMIjyEk29NPqXs6ABavrUFA+7GfgBIEXEw/OEpVoYf9JTKNW3nRbcYSaJl1ki4qJInY
Z1rxQE65NJxqLO1as+p2joWe0CYfR++u1SrVJT/aH9coLQoQ0JQe8MV3BUnGC4bY2Mk0QgpWGZZV
HyJOU1oJe0bcjH0cbyXa7O4JhZiK66bKXSICddYV6QfMUjCIRP8TmCFvDRDYUUtGM4NO2byB8p2k
YIlH98pcmLnmXZUFuuDCrhcj4t0XUV0E/feQ50rf6hGx6KBUdAqmGUc+1aFCrqnYiXqQ007ggSoA
xfNac9HBHwXyf7kwrvmFsTXpbSJwSsoKeoxg2cdf9YaTZgA2kzP99wf7Cut9AzECpVqYQpSYtsby
s5EWKr4zrir0Jrh7vLLzIMkiE8/ECQ1ZpAaicxWEkdF8WiMjMjWxrycBCaLmx6Dv3+2KDaqUfNc5
PWzDpFOIx49WvU4qE2QTWlI9tzA1fJurA3snAUOQIB0hLoII7zXkq6Iv/jZBYyr7ogR/DigHwSwz
MIXtjw/w6StOw9/POLbx5cSH5+LzscuWcGuGx7DbPh6Ge6rXAaSQPP/pzmIimn1UbcsVOGjWn9VN
+B/lEDplv+obvr/Kvw1EVqMl+j8mv6yuk9aQDBlJRayL4GuONxPASU3W5bWKjfpg8Jz4Yihcx8UU
1BbI7zRV+wmpOxV6paDdloGslIqbJEv5tolMm0EFNc/jd2ayedE8epbjvWOaJ0oRiMRJazM7C+gt
uG/JshRUDmtcSKnYN4KLUruYTkLsxgFqkklnbLA/MLDlUHm/rlQsRAqGLgy49bJsevnDuSa+tLdV
WbMFyjipAkU3ILyg7w6iY6fUY0DBNMGyiywdnjf0JBYWD+BpkLVqFD1fHo9UQNt9Y66TZLnuq41u
JMq4v6Ys/qHmwcglhPXyMCx2hQRjIuWx2Si/F/JEbi1KEGSDIX78ekI3sD3XkJIYDaBgOcJoE8NO
r5TYq9+RLUbOa5l7JCZ9jlbNhUE8vCMSZw5OfSFlfKtkXP9OoBSoGYtvnrZaoSl1P61tAQMKEsC8
kwPH6bRhTAvyTY8bZ9w5N4nMqC/p+H1m0D6VyLgBQjowC1xpbV/ybfikowySemnf8hy85+fqCJGk
IxyS/UULUe4FLP3ZnqwytWQ6JqCK9kpmXxVxJ9TgsA+HdYdZPWMEytom9jm3WJgjg8EUBWdH8j+C
nusCktzon5CNl7l1IsTOwilkpx7yypSWQ5svZLwcwl+49OKsasRn2sKfOadNgCQUmVxn1TBg3mXt
yv0Aeg+Rt88PDq0MvlwOmq6cVhe1MNuU/7kidl28pGKzFDf/g5aS+20jMbvG+fEf+Kqg60aJWPeg
E2HrSvoflGRSH8SYOWs+MSnNEWkIagR2KFMGZ+vm4+yHvrBmYV3Y8Ih8RZJSr6WrhE+fEhVuJz6E
ZKZY8nJ22ndjcu11t1+4H98jHcBygUy33dDHr7dfotgsyLCSE1Ai2D6baNpKyiUWlq7mHEi3Xcrn
P7vb0AO+7U1/4wbZfx3sCBHAO9t1bN4CIrZz56Z0aMgMI0CJdJmfmas5A9uC8QUYyHJoMOln8swT
kOm20PqTQdBDiHKPJsVzQXJw3raT7DfylUOy18hvlPkXNoTmqfW7PLOiM6KnAlDwXvBaVnoG9OJf
DSoeIkLbr0hJFUvvIKYXODxkycTbdofCa9fhLNrZ+l/m/ttkssJElNtN6xU/jRHMKY2QnZgj+rxp
IBOWZ+blLraj5Y4ni7ZJEuAc0yb2cnMRFd6AKFwLSL+82Z72nlS69h2BQtKkGrhXSqY4zGduR9TQ
R7pHDpiwFcMCZiD8/xg6TXmGEDhP7P8ymlEWsg+LOcIQ5pF/RZvfSUhxaXgNBGDt0wvFklD/tXW1
gqxXynAJkgjpCvz4lv03bs3N6tOCvFqulCnOR2LcFfcX1xxjvZQIUPUnbruta9hb65+YUBqHHheU
/EQRe30/4IXtI+M/ju0pMOcUa1j9t2EEtmOPbAbUWJCLjY7tpSOStG6F20aFXV1oH+jyzYv9N1yM
Y+TqUfmPDZyassHi7nUFjgAeRj7uFUkwwUoQDm20R+NXmAxqOr486ZM0+dbngYaxkiCEU1AfOgmU
6YpQLiu2QCBX+1YtrMmT+6xee8H3BtKnSq7UVnzRK7Ssm5ukwPDzDUJoY3r+hVVT7RHVICEoC+0V
zG/DzejXTtR7WLQ1nGf3EI6D4vOk8cWoGYyJzjrUpPaCFPWnahLaiA5x15aIft06OgvmS9GlXH58
wfM8wlEWusrV7awEaxKmZ4C/Kz0Cpx/BdtZEjIqCqC1QZ6KxE9C6stiNigIjCXezL74hHNrTF+Gq
846TfxG7k0o74EOKuLIAdD0sf5Kx+44ZHZXMkjr/YuTaR6iOoCZbztAoOeczwMsxs9v3TRCaJfY2
p3aDdVHmoyMA8A7oM17hM164xc/NkQ6zRK1ElQDWi6Cw0A6UU8Qo+J3W4LLWtIgyqxOL39dLr6xG
AKKU8MrjN0ULD6Lc4+GcvsDI2H6Dt/y5MqDOuQFfYewuMUuvtEj5ssUwYEccmxJowMReo/2DX+iX
DI3zKo990p5hjja7Hofe3+k0L89y9DovdW6KaOQiMmd4XeEZndRrC3dm3JEUwEdkhArUjLavbBPE
k7DDxg/QRZ1PA0MzBZS02fNeq8apfoxIRbLueqj+4LolscL6u0QLvCJIXVyBzJWWZ57Ivl5Yzuyw
3ggPQnnyqAMkgvKpsY/wTM88l5wXJ6q/Rm2zxrvWyXJbT5eJYkIe1KhILTsAhFJfX8QjTZBChV+b
HO4GA8s7LXPtbk38Zv0EcaJar1YKfrcdKrQCTpUUxqfEOSuJB1uEZQwv0T/koPpGnKKAQiJi8DSD
1ReEiHSXpLqqksqX4P1qV1XUP1h8UPA51ikXD3F0ZW4TvCYyOH85cVqnaIdJvZq5wYekcFIarlpu
FWnSveFon5LCgAMA8VdYkDzrlLHJwGE2pS4jQvOU8uqGb63Y9+HtjZtsFhwx4CuBrM13lJL/ntIT
9GGq90xl/BiRCtIXAKzLwR5vVEJEOKXTtwx1BPcVfW1YRRe3Nj5QCjCEQik/6XE4ksq0f5zmXRyB
0rTMpaTLKwBkVYG5CUyR5Ez/SoxmOv7twWcZrRxETKqqjWQlTmliFqb9vE2Iz9sxb886EFGz+Ma+
WU/stZcNBNoO5JUrtObDVKSsrtr5Xk+hKyjSW8x/sknoefznVMY4AcjspzweexRTN4v+iAb1eeCH
t7adBaKavexPFSGsXBgi1qWsU3tRCcpteVYYNIqp2srhzbapA2EgD4pkrn/FkMqeDAV7rCfNZzj2
Gx4BqgN2XF4GHgQamBezho6iT29jUKOcEOFqTN0b2Z4KpAapwzme5pnpfJfW+tSY4YALFAotCDzX
ID34G0jAgt8tbYcAQF0mBiNDpEkv1ixQQ19Vrp1CBTENB3TvS/9nxC8V4fxomegFta0eKwcjniQk
rcLGM6SHbNai6ypRG2ZxUY8XjAnZOnuEGfS0ZGgrYRQtIrx75TYtV8S/RRAiRM0wZeK8YDuki3M8
CyNXlF8p+8qsumJFPuIVOHJn9/kxKuXKcCe1RFu5lonqCz2pdhAKxaL0/B22bbvzu3EvAjbMWSfO
wfh6d6KYD27RfPMsXd2S78zXJ8n1P4Hje75zYQ9jJvJhkgCTchf50Hiusd+tx2zc0VLYi8QvfD7y
oBXfg6+8fpqBQUOV13p27azvBujhSjurA+y3Bu8EKrN3iFcjWOXxCSuN1TYy+xTCbqqr+TZU2cQx
savyT+9UFl00jniki7ms0qQ6r48liueobs1je1MrqfGVSC6jXuo+UkE/5hRAAGw2S3SZq/nJmh8B
+g8+GjkRAyV2sAH2YG0/OXDt5yHz96zRYQzJ4WwR4lx3YcVfvCRyhAIfqUjpw9KeFlujP3dsBPCL
NQ4LPOoAXXKFWt50+LLU5a2vvJcnxmpMfwmD+DwvAiRfTAZnwqFKtaBa+ppKc2/KcyEvl/j65ufg
//8+K3ovofr4kUgwrRaJ/9T7lkPNLLdPHEjGqjOi20FHfgBS1F+Jh5yaKXRPAOjZBo/hSTiV2MhV
8KWoJuNpP6ckKI5m6yCcd62iFrbEmjQVhkmuJQNDfFcfMOMpGbIKppccaDCb9FGwjEd7MTTWtWsy
CtMvo0/YCXP5RqUrZZ2CkFVFjdKQgteuinNbDtfBcGTA6XMgH7yDy9Dh9zWbvhdDTUnWNEzV6aWF
Fd58058jRO0pEHrrRNtMGXkd54kvoJ/J048TGTMZUVaWjA8yoRG0hSJt1vnxA6teROPPIwRJjwa9
4DniV8+BPqMOX2OzlObC4SK9HKpg8anHt1hsc6A765W1F9Gkd0LBrTOvz7Dr6uqiJTKqpQJtruWd
4HoP/lq01L/CwxX45ZSKR/58zWPpEVgGQJAqzXnFd2je60xZUX+CREO16G6fHP7fNCCxpuTXHpsL
XWAt9FE5JYRs3I0HWUbL2bS9VDthV/iUxHRTjzrgTxcg3Xf/ujVYBsRtknT3vtJSHACoV+JIgVjI
mm9RctbzI2kUbd3XTresvqZ9xQI0YLhRc+MWRofhiQjl4JgAeV36SLg29rS9ZDBDFeOJ6fH+IRtw
0YBKPWCECrHeHc4W72KQUySAwUMnUgI6vAi+67baVNgxKPY8/Zm/b0Ew27KmQd2WTe9+VsZhZqC4
0fFMWz7HmNA8okZhCtDd5Qh2sOphqEVGWHcNUJEII1YuOMPgAZfEcgn08Zhc73HlQT8MvMe1ooCW
dkq5Hs4UefuF8lNkzmn55QFwCXC6J0oCTGMNIOdIdEE+GkTeNMwEKJVQBQmfEJ5WGupIwFatkE5d
h+z85ROCIyVdiab4gA1N0GPBypomOOOvZXu/uHUsl8Ti6TQLYB8BEgFx+6/2pkUbq2S8St4kOGfp
pmrO6N8fgts7xqMFKGmkY0ELoqSdL6lIoNuQvqag4vN/OPPE4J7P5Y6w4B2mZyJqay9qOBMKwsWl
vrAiwsnx/V15CV7TbP4in49R5r752JcdUtGq+5OO76BUtpRbMBtmQIa6g88bmxUa8UszC5+CFbz3
snK5zdJJR1feMQCGY+ssYV5x38j2cRr+f4QMIZFzJUVyJyOnpNtVtl0vwWNr7F9g8XIZTMUi/ywp
sXSwbAv+uxCN2mdcsvtun1un+QviQtnkbP8ZvwphPMnIrsvCwYmkUCjiw6CNC986jrSFoGvcFaPl
i+weyL8D5TUvLV2+R+jRCcXGRv7uRm/tVXZF9OzN18Ww5N+YHBK8wN1m5C/sqIdCkPeizakf8aDv
GfkGa7WpP2CLt6hBT3p6msLfk5MrkwTPwj7prakN0EIEwv/zbbM3nefJzG+Eo/cHZeOq/rIGT6ZQ
izowggPQ2Y3fBk9wYQ4x2UCkKIlBctyQEEuyhx5YDJvfwidywbe06+huC7u1FWCEv3hvYlz/xShp
nV9GOIaabwvlY1jVpuTINN+QgFhqCfetxK5vSnEOFmSgzNagM7eDRu4ePoN//7NhP9qEWGDkPSUx
pMQF8X8swTApgAwDbcDzoVQANtmxS4r5gyy32sAeKuki4Myx82F+N/ZYmNb2sPyIM15A7+qvhJmf
fNYFrzVbwSX0qYkz/GtyMF2WnqlCrb7Cd1IQ9/mkNj8TSaSlMVWfYcce0zUBZsKZIq4U+eYiPdcR
lINjvVLIa0iuKaJJzPXTEjj7CY1TsfYk7Nxck9uTW1hfgaA9c9TJNQYqCVPMrCIENwjcu3dCI6Md
/vto51tkfzBSWxIuamvv7tJOe+66TjN4CVh8X1a//7RihwuP206CrBHcDMK5X0fEUTSE9xD72KAt
o8jIM5zohg/XfOyZBszodXJGwomggms7IyKmhODhFO+jI0NcBQnxH3VGZHfjRKT/Jiuxug8EXino
MOyawB/gqBoWLaK9HeA+Hf9ehN7fJWQSwVkKpSH8Vo8ZJiHPvcMZginYig4vPpcjODy1jLejB5aa
WDQgoo4hv7AQ/AuY9mZ+Rf8vgY/QuL8NH1BzBH3uRBpWei6BGLMXNdaQxuUvJ5vUqHP/h0ruR2Xc
JFqWw1PAtRnPt/xY7xUHaXLetLrgLGWDqy4PNt5YKrbrhoWtrkI0Cvam0UfjnstVaPaRcY63546S
XHxniCCHX1Zk7NNhTXLAYjomjL807z+A2tgEhB5xYYZK/uyj2+Nc5gAp9J7Ymw3BiMR+2cUrBRCw
VvQCil3R8ybNPfbp9mf4Tmolg4ggk6NElYUqHJzgOF9VZrNSh+BrvDFqWQ1aCE2y4NtU4/2ALACl
q1eVqgOzHfAOLIVROuGT1rtxVkxIHHRQa12Q+y6Jek81uo5EEMAUfJ9sFSGBtXyfBmRUu/eVgm0q
r9VizoXCpZLGA2/jRb3ah7oRDJbcM+9IcweUEZMKXWDtcizhSaiZdnevFggrjMd8qsVX4ry7Qohg
tlhpBpAe7Q/fgiQBuvp2gu0O9UDqq4VUMNb/LTgK1KwbXDYucZHhvvK9Q6mPu9GR+tKGc7KS0Gu1
0kvIdJkdPtJE4Y0rIctIalSAiB7aebhUZ+UHjVCTPZLTzb1oX3AMtve7pyzI+TQtkdtDm78gokX0
O6vbdobjtYMw4DAqUrS6M8EfXqOFu3bPt16+CbpUv2OHf2oqkygFLnbQm1KzPBAMfF4/3iELbcFM
wvpZNjXsz263rNE9mpxrcbKdGPubUr+owqKg2nfb6Rc2cOKqDGvXbxUZOcQzGhctryYUB1IvTiO2
YLO4jP0i96z6Zn3t5V7JAjs3M7hpifI/8oFp8nCzK6OS2ZAEs5G+2nnSuGEErb5SSmGlPN4eDlpa
fGo1yOcpv4ABxZ+Po0qyuLCBhWyID0B9gxQKV+7NGryoKEDQXrZtDsmlAo67eCc8ZQ4Esl3aEpIa
j67WNHLgkKKlNxX3fy92+KVz6cC1V5VGZNdFKpU/EfJSlAVT/KlQQTXoqErW+4UQovYCajzUgVis
yFqPc7TiBOBSUo4auQRPzhzOpcfkGMihMTeFuguFHZQoCALxwdnkb/snqi8SHIkZtVLrOWCkvgCE
T0HdvxM4LFcFUnyPTjVHev5LwRr9pjncrQvzn6hd9WS/9oFGvi+exFhbnHHsx+rEMSNEzRgeE+NI
gwTZyQN9YvVJ+oOA1MzGQ3S3KH2oXTMV3yASe7tb2xJ1pmuJMzBWZ3r4U1fr2R1T3MNIwQNvUa52
QDTMMFqbqeBJXTNY7DXf6JcfOzhdDjIwC6nXyabykO8wPzdfuuWU7PSNY/tkg0RKLccnbF4sL7tG
anO9VPSQFhHBpdB/4JErzc+UFPWJvbniMbcXjmosHPff9T/f0kpAZe0+B9yCLUA5HsGjwUsmEqp4
AoiizAbTaXj/N622Zb+76FW8x5TnbLdWV+jZoVa1XSz5Zp6Md7vzloVZPvAs5oXWGdA6O5DCblEx
tGZ81NvHjyXif8kyCaYxbAJqV9bXhefbngJWgDvRYOKXrU/NPzXkbY68rYiS+Wqu8C1SllwfLiSJ
3OXx9I4/VWZKOqtDVbpWye0k5cVXp57QL7uZB7Iciahnp7BSbdpbKeoEKm3TmbDC6eqRq1dJ0Yo+
b2QwMe67z5dqNGG+s2tWu9A1diiKCy3pe7kNkcxJ5JTM1ZbUhZ50faTjePx2Qhb+5PHMz5UTdNq2
iEiI36LnuyqFl3+ASNSyJ4SaDvLHp4gQdZ5KF6kD4Wd6jYN55AQVkbkLW3uql7DBT7k49XsrhBMc
rgTq6JYznmVDMghER8LO6DqCP42/K5iFD4uodjxpn6edT5ctkfPs+MFURopvcdU92I9zYjYe8UlB
jW/ckBPtreFiPC3sbfmqMK8EGHrkhyaRd1Qkd20m3aJ32DnVV243ozaQlI1PMcM8SmTH9KDAdCGb
CmLTxuhX2XmEr7nxf/+4K86iP1eyZtnVeqRURfUMthZxiAjDOCXKYgs8ChlFzX3wiQyIWZVTF//j
8yp00j/GG/icZOGC01aiTg2YB7mtAa7+gZ5UOQeSlHxXtcGkKOJJrLRrUTEH9ZI3ng2EzLJayI1U
D5P4OTzRIfy1wzQIF2EdG+m8MmTwCf146UyzmiAUwTayN+4ZY7Xe+JtwEUKunUhbIEiu1GYSVrkx
cptFGyaXjjPzog7JXWpw32Zkv7v0B8QgCMBlSfA14QN1S1zjTtXclCdiEpF34u/ZZvkptz+t1Syu
ZHBpl2rpBwrrHMZuZUBUySJLPT4BSB0DXInVybIvklYQ0o2o4vzA3rRLTZg/5uWEn4tBJn2/nSBp
LqEwO+Jsfy5bDGjbfAmz1q9Rn1oydfWKcuY30SnQ4hxBSbyK1OS0Ab5Suvie0e4rQLrFM0jmg4DG
WCX6XzbzREFT6BK6v4/oL3TcZJzEKE26kGnZGLRsif/QJ287blA5ViNZ6Xh0IQ6aY2rw85aa4TJV
Jje5tg/IDCExTg6Ilsw2ZPKmhgBXYuJ4tcTdyRDd2JNzlmhrFv9hZn7i4AVkDy7AZbrpPj/QOfBQ
j52bkG1FETQ9njhaubUk00cGF7Jn4PRRDF4+fgHw3vCTYgHD5yGXgj1RwqlUGsvfPo33+5CluZzk
D8KuBG169sGN5u12VROgCWD+T/VG2yLQoeH75WaT1Fm6QyEF1T2vKkXfz2ReDGR3ggUWsNyfsc8E
iqbpPzrzlmW9UKjpz9rbNhUwogZT6VT3BOn1Av4SbV0ex92uxQKTQHoCfRln/ts8isP7Nr3/Nsm3
j/kYifKKHHwR8CJWeITNe+mSz17WuUTH3OdMgS20nktDxYmuVC7jMRmCRouYol2cdwe/VNXWxrg4
0s1LvFuw9nSv0hBexH8GeaTe6fXuuRcGFtihS1x94smfG7ni6OngJsOqCYuMdd+EdG+vph3s4/wF
n4/w/ONZoRbVXlYU9POWxn1PmJ4AJqRYsmRMt0ktq/yMugoqcK1dlY5SX+bYl60y9+cTDAbVOYPd
qb1a8o32uoqbJ4XwrW/qk2ZxMuNIEFHpqCEYm8g5bOVd3dZsRiMz2+CD6SkqJhSv8RQroEjphRqb
KslT7xTQFG3OTZm4iIAWLi2hYxwl6GvHb2uN1IItyvPRrrt7wJGPHHZRxpQpGjMvOPbDX16F/JEK
tiEQ18Lbh71IIaH+7V1zjl4bfUfyNMPXetKMoNtfRbHJMLrh+V60zGyS7YSWZZljxA1/+t1Jn+nz
oDfY8uZ4f6PuPv7YtnDb4y+T38utkx94JP8H+oLh1jSyBKXbkBpXyuREWg4R/pX81dqAgaWDm4rr
Cw8zPHGNsfLx+d1jarE7HwgaJfEwF8DeJ3ry/z+1NLdysHbzDPCc/C8ZK7RtMfE3TBZN9mifSv0s
dx8yep4+afrp/5oO88nkIX1Zj+khi1/14Pr7GAgYe9R0HHRasnJeVGDodOs0beY967f6azo6nrQX
eMB/Qv1SlNSq1pJ2u72V89hxo+FtkwV3MlVXrCWJ+XcuhOC+kJoBiMa757MrwIGWY8SOZCa12hx2
zUgVa0p7ubf6M4nLkah+Je7i11bv8yKbOsmd3LL+BueOq0iQ3FOoK9WHJVSMhep88t1/0cWXXjzu
pDQWWXr+LVQ8E6Ogm+IxjtBEr743ShmpyX2rcfr6QHxAWLka2oKsXXXfxjBc7un7JdJ6uhWjiFXo
vLIr67r2Z218v9g7wj4CChIT1psFjqMdZ+izq10K+Dbu1sI0vLhC/5A6GhqyLKRP6rs/u7ZWA4Sf
hzX7ZJSsB5KAn9YcV8nCfDn46DckThebUxvGcSMjrV7eschkKqTbw2kiaUcv+a7Q/f2cTMokOtWC
CA1OjQA8frDe6rWIUJLPz4e9tp+AMEztzbpol+w1dARlKzXhJgHpFHQ0cSl6445+oQFaFO3vcgtx
K5gtGAUx2KRwDXM0idLgWxblSU7b/G652tBXq1vBjCelYfas/ClI9GPvVUzumGXkXVgPiEqrvUOW
PW6Fn2kv+dhBhbVxv7nADSYUH5fPAyjvbzA2f9AmAGQSyfKxGvztnpKbJNId6NyjUnlOh+30GTOf
k22q3830Y9CIfvtRdCYMOrT+/lHcRFBGqed3Q5fiwE+/hVIefUP7rtWoBgqWNAsehS3RE+AQmmnD
c16h1mOHI/+3rgLpK7m2Hc3Rkg8h9BLrrUjCwGebLHq3T/CilfS4l1kAi7qhJ2IHtRnEizWi+oTq
Xl0fml9arIsSpz5AYJleLB/X8qznEdAySjJlRiK51PLrHcLtFcF5xV0gza0FTMdl6T/0Wd9NNwOe
vDQNPmGjNyfJRuAM8CQrqyqdJDGxuokWT1o3YPY4vjmfIARu7xPPA9N7zitCD/3OA1r8TG5gZbx3
PEV5UEA8uCSeg7hC9QRHPwfqaea8lRJ6eaVRIh9WK+8TKr5UUFQyqVOdjcACvKAOE7J6TN3FV8f+
xee988R9nfa6EE0rS8kiluYXGbr2cs6Q8GDn4Y0yrjEjkM5B/+1GGFIA+Mb4CAW79LzhAZwiQeol
x0f/R7kPbV1LqOuwXp54TA/5B45LcROEtHEF7M6QNyBPXNvvJoogphOokCsWUaLkIsf3KmSQTAWL
zy2uWo+I16w/Y9NYzdzIs9Uk9QcoLKELI3xX43zwVJ4d15FuyGVQyGSsrIfVjGSGnX1nq6/taIFJ
/Jtfs9BlvQzyzAs41jRekDl6bKHHHiGzvEURdQyJ73wry/7k4z8IHJDL5bKyoPsMVaWYLzcHKCZ1
DFAE9wRz7Evvj40t0ck3PUe6ABrCt7SCN7QBqn2AyRkTDcBpPa18mbz50BJfBK8G4VW8s5U24Q7a
AS9k+u3lW8NUIb+IBVBDIqv/VbrTaKBUt6kQC5WDSiQPn2e09bxnwTowdeejFC4/qnlNiJ3ljED2
A2EZF94732zA2NGaPGdFmxKBMaf6QobZanpjpeNmIEAYDxaQjTGgijndaXIM+/DC184wOmJHr6y+
D6iLTxaA0QE4fQtCxuZwgBuiarzmeuhK26DDuR5/41q+cRSCHT2Jw+hpuMV0WAYp2ZtfQYzcFy+z
Zk/MjnxLRKIgZFmkESSIegq4uB0i8fBxf9qvEhHRplcI6Qtf7Sk0X11pjtrJ8yLo+lF6Fy7cGlzg
NMmXwfKZyA4xvrLmY8vbipPN8v99wZ4SHkVce4L5bFytC1EiDzpi3S6y7LaH+DhzvbGBnb9hqe3U
suYiuYSBtHnim8BPJNNZMNnsxeZ4D1yYekUJlJsHueNh9KV7nGFqx6G9rxdQOuDP458klyoWSzlc
Vj1b1lYlUrXNfmM1O3wZ234b51LAk2SvNDlSNJOeCz6+miUtz0czrF3qb4BClwnS4L89e5wxjcn4
W2N3qq5uXshxxn/at6c2vQngotz5k9PNQ3dI5G6vMRtH5/WEMyUXuArvOVY9DntcesKkNTDkttde
dC7TxzBk4YY5F3PNTq+07Co/J6JVf9haBYVIqNkwL+gwP6sCpA739SNi1SM14sk6FvS46hH+CVCg
rXE7DN9xI9ebvk5umxQsoHkTHrFY6X5HTPWLP73egn3lWjCKD058UsWEoPsx6fujq83BJGIGE8DB
2sq9QHumPoDw8YSCWr/omXu0v68GUlorJp9zzD4kiEHeU5Daj1pt2RyeGR5+bhgsSaGPDPwa8G/8
gMH9jwlfz5ixx8dyutjCfGHNHWKsjlx8CYa5VXGDDnqBLu5b1DzKBK5Acjvf2DkSEBUrUZdrfLXG
KZH3Jhbkyav8bgUTcyAKCsHthnK6oOKi5FbH7qVFKqVwbmolmAsjMoSaMPpeVwto08DaB99Fqq/e
2oVgrzKtFcojeeFsRZ/PzcMduSqAtXRJCdGBblY1oIM2p6k2160yNgYYO6P8wydapRrY0B+m/x13
nPihgMe9TRjQuWvtZLnejAnNvzl0t6us5LrsYnW0Zwp1qFlgCmW2bgfwdK9N9mFKrvj7sQ+hnEYA
XvrDViDqIuJok5RLWXYZNGod2wtHaKExG6JWhhQw9pc5kpef0PlLNYpYf06DCnH/J+bivcSxMkGF
OK9sEN2IDPcxgUZHGxnfZ1Gr/TScb2SnbxGxeeul35LYziBo1dd3CNa0MYEQtksLZ1iuSFNfH4cz
thXHvhPFtb0Wz4eX6CBRlR4KkG3Lry/L7oiG+nOFkRT98JBSZTHexkjEDF01sSU3zpsIW9eWpvVL
YjRF4CMXMVXrt4lYcjRPzgNQNUjC8ndxlo6V6tMsjNLhTYlKgWDGReUeJsZtmw3RZv50DlS3JT7S
3Lo0tI6f1cH1odbMmabTc10GfWHaPX7RF5D/vpMEXM2qwq2ZBeiurDIS4E6oRL7SmwNcVo9l9sh0
KKo3p69hAK5Iz2H8AX9gvvl9IMZ5xZY/5w42Rt50pHZlm6zNpSURN2tSB6cXMg40etHfvpVCi9si
78GdC/C5UTw1OCTMg9f663gAomKoFdifJ+Q0cutjfR+fc+GZMwo/W8/v2gaA16qek4WlwOk88kvV
gYM+5XtLW5QcGhSn+esdmqJBKbjSWBodtXaIGTWlmbW1iLtCMLr5pfW9FCJIX2xLsRwrfsDJCt0A
M01+kbaLIRGLlCJbEGE0lUVDGZlM5D96sWREPFwUHfa3lPEub8XeNS8NZrD6bykhKz7u+VZ+rXTo
/MnDEx7VAPwGYn5LSdH4r7J7ZeZkzWYwHbP6OC6rmgxliXt0xinN2MsG0kiSQQcDvvy14sTPgqhy
lbEnvdkNhJoi/ZcHSEsCYwZiBozzq2mvhJDvcVtUvJ0xYqaF47Z5dBW3T8Ue/rOpNU1bnGnPqiUJ
7B+Jn7phuk8ODriLWh4l3xUfkHQ3lRHiLRnT8CZ8uwWfezOGs60RYWrjswH3uZrr1GWz+hnKHGCE
3Rv/wJRKk9HzQaghVBMWnWDztWSs1Qpu8scXf0bjMP1ooBmqSe47xdLcerIkNf3KYl4JDvkY4xFX
RvYqIPGM5pVeB6E2QDats3j16PmjxZ9EtIOzdXRwqlij5Oq7kgtCQdCBhpTXlbgx4Gq7dkawqPvE
SCGrI8H+9yzOFObbD5e3azTTv20DaKh2KRcwW0HN8FuS1S5RNm8e3mrvuevXnTHd0JxrCbSmM9ka
5/gC9yLenKtZM+nSBsl0g4Wjyw53pCLOigJ1yI1ThOJbZMv5nq6vRN42K/1LV8i8sON5bXp2DNQE
VWOxK0St54bfW8XzzQWfU97JSZeDRaebcUHGE/QebyfhUudf10EHuU0D/qLd3WjfOC7HFp/ummgd
uPgzVog2PpMBkMVmZw1ZdW1MYNMYuRyOBd7gOppo9WbUf12kD8c8n0ENAGrHwtTBJscQu7WlqKlV
HQP5SUqfIHxTK/u1Cf7PH4D60tLNl+OUOtpvzRS2s6cuXONZcZthAxXLuQ0qC5p0NBbfQbl18/Ca
DwtygoydJaylsmo+17HFXbP3UFQ0CMxpc8kjEZJPc87HmFECvXfWoDBqNWeTXdtAhnmBmLkolws2
CwqICQqSfiY/03mFnwnv6LpyHxWkcA4OSU19E+FqCHTWZ6iRFcLRkgyy+TA9kvPQnk+oGWnDJl72
EHWYd+7++w7Ns5Xwx0CW5Cyj80LHkFIqzwEMyphZL5JiQnkKli58Xev+ABnDW7Z3Wdg/FvD+ZXKR
rHsbYig5hWiciSAFlWSN6fyzwgO1qcjtK+28M49f/WRzcxovQXbaA1jXLcZz1KY7WzrR0hIz6qJ/
dn+8BHWuCRPkCam5e3dLQrKg5R/aEaGST2E8YRpvfLby5ugQdOIk8Tb6GTUZL+h28XKMJIi1v6Yn
Ap7kY1ETZSwdR6mD6ZhWVdZGlLd0MaLZlyBEUhWewDfgOuMlaVNc/zFN/4Bz88a9ztZEuQLKoq9K
AB5xcu5UbedfJvtVYqhfwEdj+LnLfQMLQB+ydmNQauWZ9hSuwVIqg9pCYcqaVjN+vI7zO+ILbCZU
CB1z6hymFP5uCJt3ueG/2E2bau8ZBIg5fCawKFAV79JnwdtIWzLCc8mzcKra25GPX5T5h7yObTUr
mrJMe0odXiV+ISnlNbFLD/b/g4phhQm9MiyYTmXvuiYLPoL3s5eX5gx/5Z8QOsKQkJJYqDMDdtgZ
OEuyZ0fS/C0E6jpgigCiwGRM6EmEZkDSG5oU/woc5UJnFIvDisRTeX/4VqvFKIOvCNZgedPJAqvg
3YwrHdner3mkyycd7zS84oYmaZog5jDbmFPR/MnH5sBMlkBwUvhqlUEsPdoUZ/4aYzyCpzbBnx8x
p4B2sKeySAjTDVJ9on1Iu3RahAmHAclFuurCV9WzUwa/kMoqocBrfENX1xGOScSsZjbkHkzVlgc+
aMdYosmQkqi73WuqOgnbKIYLayvIJOj0rL9RGYWeJ2nR4iU7hSoDi213ljqnAUsRMcl4Zmu+cT9S
gS/KRFuSCqgzC+h3hlvlmyiilK4qgjacqHKW5psg9Wx6UaARKkk/QVGFbk74S8jOi34Vkp0AigBl
en8TEXc5w6tbemW5UA/O4/jtLWUDrMl1LmwczlUOtBvyCFfpQITd4olohrhzTTT1WpbIXrxTHDEt
zY/5EJ0YyeJAEljTrFBEPnJmlNCuEkUQsWwXN6GoIHsMuXMTXiEgw9CXHLPoyrZou1iYAw1KVeql
8F1jlGem7CHErRcux1tj2S0yxVIEl8r+HZ67E7/lP9wBQvXn7KdkYqiw7bWehi/Wpy+fct8hcpoL
CIidYJ6i6hjJWlyva5XKyE5aWWxIf5gU3XaMQWp4Je2cFTX1E6q96xtR2rMc5fzxhiDTREB/ymI9
71Riljje5/1T+UPsE8d/xdO+k4l8Q8URUlZPku7Jj2AgwNTzYa3MCXrLciGztiNuNgBtvLAj5aPN
RzcEaw7h/iC1wyt6g1W6yQxD6RGgV5P/iRjSTJpiBDnU+b7WGsrauVTaPm21InC+o2bbw+mp2ekU
0zJFfeQGTcLf9ksEvnSgTKGmNB8BXzpUaq5BmiJNCSkvH7oi18Kr0UeEEJwHxvhQMbpyaGsPc/Z5
kIo2VIMmmbv7cT4N31C/TmH+Xdn8lsHJNgKA+nhEas7CcWNfEFKf7G4RzH1gTOQTEppn0BNwY4+j
GH7FcoIu9z8+5ejmaZn/Dd0EjhLPku6bNGnVyGFNprGskSvV+v0w22BB7TjlKEZ5zWqHOZcTkb0D
Fl/83NjQOJ4ABx74v0UOkZMFNW8xmNAE4TFtOr4sm9pXbNsYL4ZQ/zPseYQmaX7EKqKG/Sqursh/
nrx5bt5Hf2iD2xSC8JfxcC+sy3naPo5GKSKfPY2F8gssNX0+ovprcKMivhf36CFSsAm0D7IIlECr
jIT/abSXuvv7xpJMj8ReJnaPB2i1KujC+iEj047GRKKyY/g3HfIGfPebZwYX2tRSgrDrKmX2LWi9
A6frMpm2EgBxnJ2GH9KJv40m9joP0aKSS0LwsqCgbbNX1TURHoXyH8coksd1hxN8ILPY3OISzyCg
YFXB2DVp4iCcxZmOd2VwgBH3wOq2aIvb8hxMxCQvrqFwP3GFPbiey4g6LPeCo3E5/aFT0GAugdl4
UU1xw1zvvbgYvneWjRRpB5JttgfD7+Yt4KYOVT3M1KCKdP6ro8EfgbJUoYbQhUwbLYdpI90dvh8h
/3GgnZVUpL7MCC5YGK1VYaAGWhpH2Kj+6cRJYRORWyXd4AE24oCvaftmn7QLgcilBzA7tSYYbCIf
Kl+MyW/m1SQRmyBvLRpDD30xBnnH+MdmwnmnrQo1NOEtJXGox7l3Q1pNDpgAd2VaDdD1Tk5gO1Md
naYf3vvNFiUWc5XbZM46CsUK3oP/mQrMiShrlYT1tWDWjKiZAX15dW8NjzGwlEhDvbMODanr+AZM
569wQESoSp7GeLG5cxB1/DAMav7tmnbmzDE9ovyOWzJ75O7m9w6wNbQHbPKOZSNC1TnQLFmzJqQv
Q8fmFj0Ask+CQIM/NcsJTtJSxbZ/AQUbjbO+vFVEJhz6onqiXSYwXurNCuhQUAtkmBikfgFbcuXE
vCFaSX45Q20kTfhPIvK7ZDEslogmZEROVB1gnAmr4azvCSoEIEpk+o44wJhqo4g5ls2Vk3t1dXX+
AVhJLlexaasxapd8+FHY5mHhW6GCQySRcfYzDFnBJGvpn6tUiVtRpep70hqKsVEExvfD0I1qFUpO
2TgsRCmu1AEPclbGZjB1RYUiB7OMCXOfAtq+1o8q3OURFkmaIZjv5ieka7yA2XR/dOfw3scokwd8
T3hSC+CLh1J9b9ZM3SfYHZT9Tvc64HBurNRCRW0VqtUBcfBymD/GL5JFHfs/CdN/DwdsDqn3s/IC
iSaiOtWSIcu3js0xeVWUdiBcoVgya+dCte0Gnk3DZv7f2Pp3KDRoBOXKdiSF8mrU+2wI3yY8v7GB
3vSy8o4kSa46oGuFTqfsfes8PGYzSF7Cy7ziL/1ODUAi2l0emoWSNKiG1TlfIaF+EKrgkg2dZk5X
6OXyKD8A2iq/UNUgU/gNiR4hwLE6DLPPCXNB++IVpGF5feEplZ/ZEQUtfA4rOjpc+mhO1D87PYC7
3Eyf3Om1Ey0iqFwdFEOdyiV/YitujKTanC+7D/e7CPzlnsVQw653538Ewu+BJRQ1FYgjmnA2O51d
/Niz+BJybQputrrE0Os+nGe5G++G38BMbAvbNFOxSIqWc7vuqp+j8Qa0DmxJ3/tIvl7hudW1M/NI
Kdga1WFIDu5MuYV6sFOabOd6OS2due+0gxElbn1cYdgfcrkWuN1LfEvEUnSAmIu5mxvCaXQR5485
qeZ7cQD2tR/jMDJFAuKW7GGTUIU0y2uTp0AUQknuVshlteT/L4D6sJKlv+0n6f4MYSn3Aq9kgadK
N6gW+W/uVndLhR9qIuluw5pjcZNWcNrkv2l1l1gZYjBvFKAk9eiOD/8FYb94i6bRqgZzCOlD1Qe0
yyRmP1QyEws6QhHcdS4hqMzhXBP+y+7uek7vjy3C3Ydl/8domMdzB23c5KTW6C2qGcOH4sB/jIXJ
ujw0ho0CP5zhFF1mhQFYWg1zO1oZfj5oDcytrK2n+PlmqG8bxI1C5m7gcGuH5xiKOPxI/7Z9aCCn
ncgbPh8RAEldzDYWHLMm/Zeo/kDnWOjPH3rUHvIHDD7S9rmxZyuYHeueL6vSSEzMrckLil+SdzpS
i9NS8Fx8MlI3p1ZIKogPMEW+EqkF6n9m1Gwmg6g8fzJtKsCiv+MZKhEdHRsDctXOF4Qelg+unRFb
AJxN5pVkprU0XU+WcP9bGZFWnxtRQ2uEV7fPbppZvHWfClol0lCP746PoMpSfBkvc7nxq8/HqZ/Q
3qZdXVLZIzgCY9nt+meBVd0tsJyvmqugB4GA9lwQEIW7mvuTASd0QY668K0iv/XY1E32NbgDHXgx
0rcuh9VueBr2QtjdgPW3F0FhMYGH3haCWM0fzD9j72UVVHr6+PrNa2J9Ddrwwx8RFc4k5hHYIzxN
AMxvcvjTA492zyTNSVi0vU4FDNvA+TvYzA3bWnviZ4GceNFIRksSuk364PEOCzOpIwab3j4CaWNf
lVV8wwiipNb6Aup64CnuKQD+7HrvHd7Og1HK53M/ARgNyOZ33q8toSA/xZLBnA3Y+jt1shBNTNFt
6uzhNknS2zVbOSrcaobzZtwLw+QJ/EyPkDQUw6ED5RwD1+63pz4wa4Vuxy+A7dqrwy4BB0+XUPcO
aK7Mztt4X/gj3pyKKl+Zgfc/6jVMqvm3xvp2W30sR7lS/EjHNatdqgwjDcyQZd1MlBdHh8Utsw8X
IYru9SO0eAMlreDUID3pQJU06jhrTDMNVXuJL63QE5WtaqXsh12OptrLH5hXwiLE+Ek3cgQFR7jW
w9Vgfi2XAx5i78Ej/L5MsORSQZMVOyfoJyUaSeWvtfaP9JxpIW/7RJwYVrf3k2ZBMDqm91881YYW
uF2P3Y3FbsUw1FKM6cQICvnprxbEFWszoWQv7yml8Kjxpui+tqnqZoVwzqV4RKbMuYZXuDHk/YAq
hXe5k795QQwsCbs0idxsneZ6T1RqsImqEWb1LgnT54LwAebbNBVzMjtnMfZsWRvFON/STFk46zxZ
hYytGN5mzmNBXULKUsYNl38An818lOgA+zoXiJSQbimwj4l6yzpEgM74oBxk36SRgny4TjfmW5Fn
t2vc81nX5V2bLugM5tlWprGiBhBQLZHJFmJL+RB1rMBDOESgz1eIg+qp/vuJ/rb+IHRiiYJUSqbF
+lXWziPQwdTOY/5gRiB4f/tnpuQraI1A5xQZw6vCV+pxEcO3BnIru85iR87Tgpi/38fsMZxNKa9m
HxpZ1hK+JiN4gLgAGMTNx31DXpZNb3yfsx4a5/MhR4JD5MxL33lt797vYCMlx6WBbWgLa5nnYoRl
jBIZTJWO2zscV1aanagwDlliYgjCrHFbdGLh0pnsC3nxwyP2SPDzm7weGirmXaaROHQ83oRQENJ7
+45o5S9zHfwWWn7eAQP27hv4qu8gbsIZ0+gehK38SHxVK2lK8cfWTiZWL/xXZCCz3frRUwB16iVd
q+j5kSqkdSdaJcLU07fdJZg+3HDKKYm7XAAN5+0JxfOBqIeW5qR0Cexip0kVc1iKiKopozoNjxeN
0sOFFGerlHIpsDn54AyZcTn8xRAdUTtBmHNeNvWEFiO4TPoRtJQZ3Cmfv0FSXLo0A74lp30zMr1T
FZurSbZEuBwLmuCYUPOfL0mSf2aRVrC3KzvsOd6iXwqLg0rZ4SOUaCJ4ogvfzArXk6dysUvzgHDB
QIxm6GDPGfh80KLqRfquQMG/1ak+vw8bwGfwTkyfQ2AiTLdV6yAk3QszBHAaznpkhkkquTMnG8JR
6k/aMApbDPaFIziVIci63ZzTkoUpCTXdep5S/g801/UUwZDD8KvpKn3Tpx1fLLLDDrKG1z0BIg/+
YQKULlgacBQjCYXkmlI2Lrsh0Tt6IWXmQ3dKlARsdOL8IHdUg2Zo4A8k2WuQyLFWaBjFxg9RbCew
2OLH1f5CXBstKFOSNwrqJHdX1eFb/qAkcoyTGxcEZgA86z/IhFwa42YCpsq5FKzjrcqH03bquY0m
MJBu+6+4XpIa6UqUD2YTxW+H+qYHcrD3/X0zRytE4aGFOC1qAhZctcJ5ZigqOf0vyeJGWmLvge2H
BhkRl+z/68TI2KCFGwIybTJvpkb1rRuhR+QhQaavxl2GrPIG9Xr2V362d3nrbulmVFhWENm6ehCC
jrHcdZaMJbJH/c1p6VbbCff3E5GVDpJDP1WZk/PYuNIgbU2/Ii3VvpqSFduIiP+PtayFGDS+ZZSx
gdy81mM/Fq7x71ThxAkpQYJB2PrUmN/XnLy+MjoiQAqr951rl7A79G/ijbXkWhs9S4+7oN6IY25j
CX/qHUvccG7h7+Ae/LbF/OgMWQpl15ywlnyP0nV7uxdU79NI59LOrnPrMvQhEK7QELWYvM3KrQ3a
Z+e/yJ3WIMykyDMD7UsZO4i4FitfKh7kDg1y6KX0orqcJYlrt1nU3Qk9weZAME+fSSwj1Zzzk0eb
Y8wHd593Qt/QnrV8+mjrt4tn8hIMyVgkXx9MUMZmJ589Z1m3Cp52qQUM0D41F3gfzQyznohQ26nZ
t4atCMzz4PF17woamy9Mt2x+TpjCo4wg9VjFaQa4vhsY4X8atvG1GenPpCgjQXvPe8FMmsdnHMyM
Vj+MgEi5+UU5RMBHECnQGkAgW4hdFFdydqfOctWlp0jW3fwBevc0BM5Y7rIk63qZWOneB5AGoNYT
WXjj11rgpxVcBOAx5SGcR9gOZQ9J5oYQ9rS15hzAWuwrMOqaX972yULeRvkMzuxjbiH/89xiTcCr
wpuZwmFTh1ktoAhf37milcGnMAgFR1wLSyjQlKjX37+lDmSB3x3uuSemF3sV5M0pUuJ2nxgLvjxE
t77aU3ouciyWP4CM7LcTNWP7FM1r42rXVHbtRfu5x35+TBv5FoKSfJJ6JckjXDKM3oZHcBS+HKod
mUGpjMwr4DOGTCqrYTrKeCFOuany7RB0Oa5/xeqC23G/OT5umKSWxnE9r6c73JOFH9WQPa6mOGiM
eB+6h45J54PHjLN2hHnwaYKeDfhb52MAM8VEjh1YMDHoWzZymYADFi+z4F0M4Gug1rO7ZQ1FuC/H
lBRF/veqOfBhfOoKU08PIgfzku1wJMmMlnEhkmVp7uWWoZOHUx8V3DhXj1R7a1P404+UtP9rT/0x
VJ2QWVCpKM5MEEBCOgmN9zU35TosBNCIgujgdjNVq8Zirl2onRFDP6pdbJVJRmQ9bDpUwpmgL10K
FC1SjAzSufhQUto3FaMmrIsEoqsE7KV4wDfKhUpi1r7iBIS17ZPPANVPy3TevHSWyA+M80eLR564
5FR0kl9ZXEmIOltCn4bX5W9BOt5HgyzBqWiLInQQxtxD0wuwTlZoGJVUqE3EmmO+0OdXH35WYxkj
btl2xjZNZG4lCtx8WT03cISzTN8/IiLK1f9vRpX6d4bfsijT1A9mUTeiPvmuqTbTlUMMjFlYEliK
7Cf5Otnl3m/eTTir2P2KhMx2PCFOdPf7tMulASk+pToFltnPN5mLg546ZXQndkYX8BdKLAtk4cck
sB5BcOAgg5EqFTW/wc94BXDSXb8elh/Qomt1hB8IRFM8fQSwbA/3/yaFkcJWkT2M7MKf9JSjcOuf
XblqNaQq33YIQRL1d9LvHNKEQUUKB9smEnSc0VBvhH/QSxmV+P+NcoewjqoovsbESGbfsl6WbWqp
lr92WooOv/9VWn/qcRggalgp4gf+9GxiQHUiKXufiO0HZNvu4AFh+qushibHjWgbiCiuKVlkzBRl
3Ah0BToiGNv28abN2C2MfiIgs5JNSGYv4nh5NW39pSf5cCznERKcY5wDyYQKUx7Fe31yASZuvRJA
m1ZvdFVgyozSGcSxGPEF+LyejIHhNlJunk/ITJkKmTgzzgaNhl8vSch/eKh6WNYe1KA4t4uCNRzL
EPQ8AneSBJ4YGi1400u/mXuP15aL507S2CjhzeRs6Y2h1xY8YFJIs5pkjIph0bpe2xHhC3RDvFSD
XL9ECt9h8FvE8ayJGzgJYTLEqLbQP/Xv1XaKMCNs43prPpc6T1lbd2o78HJ5cL7hLumFyP8Vma+r
1NvDhnCuXejYLyN8CBrjwI8GgRQp+J15kQmY3qJODgzFccyamSxzOaO/a0T0GXE974RMR1fLzfy7
9EHqokeHaLLa2YbSCV1poy+f6qwHY6xBU8bGXvqdl9/unSh4AGCnURKm5WJGRmDx1+hCIPMghQ4g
vOjPXKeEkNuiz0LgjjqjjvbiETo2G5tSg5/CdYZ8G5h5TObzYz6idq4b8gG7eOsQr21+Ef5fPHC/
k2NQcMi+qaGbG9tZKQt0jSEk1TQc8USZO7grA6N/ALvf7lEh2kzM0sMLTufYSj7Ex02Na4WaKtIr
O8qR+rrLt9S+HSEosNwnGr0YGJcEa3aP+nvHO08sxcQ0IdJ21+ZvRO9qYGrA5PkUKR1XXbaBHu5I
nAad9LLhhqKHhB91gKke1y45rz/UpqhQgob1z7wSANTzMxyjH+xckYawDWAX0rz6QEKcdJ8YTn9W
WhKRuLaUIGMuDQYB1laPRBpLoybef8nn9gqJR2Rts7YJVY2j4zxJrLqsuHCuY7k/qp4wOpJTBKyP
m7iN5NJcWBclsPE8JVo0u8wdux6edxjKjdFKk3n38CnRUqn/TIvL4CnMpmz0Nzz3j0dd8YkHi56T
i7KGF/xKVfzK0UJ06LfdTiUGOUMzdNAZctP4P2bYNAymjl0/Lfe3fqZ0OSjHabkWlgUo2IC9k6Wi
gYOwocTOs/DMPmw8URI57oEbZh5OKaMNjKj97035ptNqAEgZQRcaZ4k6fGc8tgU3+5hhJIjOujW8
TkTpDaP70JbAWagXSEaO+pJRtMuHNfM4ecOXZjK4AZeumbzi+50/gX4JRity94Myets7wOQf8OAb
ez6bxRvpP/XpnKnAmu79TTgD74F5ATY4ZmqB5LHmC/hto9WxaROpxTW7lp6uYTtea1MuEvQfjb5g
TEZE2f7/2wKG7EcWCTobnC0643IGHpEwrFK+lPnCIQK7qwwTkcxJQ+UEg4jf/pqMcgFZCfNapIxa
yKKJ/8OdCq4tk1ZcB6Z9zSMOVicF/eXSNdmQyjqxlkaqD5Yd52lGUsOEd3JySyN2FtEHeSg/6AwW
EeZ5dQ9uew0YeSua+HX+1nWVE5Jq4/DZjQm35jWkZz7OUKsQFLOo6H489b2WxcQiG41kWC+g/PcP
im1D3B2IB+/zjUhNgbR2Dij061ehkaxKzcSpYtjCuab+55vbxWl9sXo73BIUppiNj3Hr9XzlZNTK
GY7DIRnRpqmbMmU4QYz3sfEW45igaWRUvoAYCMQh+IIBMabxwd2pAeZqZuy9hod5C/V0hW6SN44H
7hfZ7TigxEuJlgw0GSX005zYwfEP4HekPSx3FLK7KmK0vY6YDlgDYhnpmfKV3pMf9nTZKCvwZW5Q
b1zryiclKzh1ZwbckdANlpGY3RMoB1/MxWifcwbgECY/oMY7r+VFEz2OQ1xzTIs9tsGlsfnCN53U
KsSzkAqSfJCLQ8OrNPyDBBDX+TinwdvKROHHo3WwiNTxpsvlgLu5vjb4rgsXU+k3D7PVjDY2Ya49
TEiZ+7D2PegRyjE53jZkzcUZWWLjda/bmoKMulFexhGdvzwl2jVVTQCZCsnC6cAbn/F27+zEMm7H
yPdElcOsPelcGUq65qS0bjOlVvYMgxLnTWBQbIxSTawd2oACa31KTW4vLRgvs7N0vgL1Ygfixqjp
lYRwzq96CfLU5uQfL+NNJ6HaWmaIqt2cp7dse05bgHsgkNYN0az2jJ45QgS93PV95P3hsockswCF
p1XstPw41KfrjImMJ8G01FOSF9kk17Qo7WC7BsAgbQShrBXO4FjSPmodpLYhJjoHgLbbHjyCadJO
kTIWnMVOYlGZkkq0PQQkp5oVsIAWSyFVcZI9MDcE0bb0gs/uf/Pmh9B1gdUTsrtrFnQ6ERU6NxOV
p09x/B5oThGqIHwR5qymStXUTBIEOkNeTMtJgFJC8R7DSB4BKSiJ2znO1LdAtbBjuUXTyFwRM03/
SeIF7BblJ+yVUpuahOqKI65YvQCCGYCAiAm7tAYJOYops+csWijTr4q1SxCLB3tGm7YbCvd1v+5s
5t6BCWRz+fJoLqeugNMEcGxXtZlChXP+q1DKT8DewCiDwssmbQgR3Biofy4Fxia3P6E//YrI8Nhu
8ksVX9fRbPEZKvIalVn/QNBYYKBblOu5CaW6+q3Qv9koiGMzO9dD/xX4AsaHRy5o0sXTC2C9nLcG
r5NREKgGj0ozHz4ugOn3KT2l2vXEWmTQqIz6pNI6RTpMYWQ7PYLSMhLXlvIxwE2z7BYPwkwQtREQ
KzttqxdY0negjXjacEyr2jq+mxiwW4782y4hs+75bH0tAnkNUrRpxmReAVKhbjZk25o/6tQP1uuw
mUBCeodmCFX8m1QT2M33tsYRl5eY1hjWyqM6xpidMFpuPaV/WFJGas3loL2OLZtOvQhxYLUKNNmh
rJFT3/pQwJIFANrY0KZiWOm8D8Vn/xz86XzuYVQ6eQ4svke9QhvESVmK66DMaSOzPI4a4+jZqbBl
qmJvOwnPMbzV8MLfAJcoBaUUdqLOBvg40mDdFgeycTPy15Z1f6YD5zFVSbKsuLKf8qKTm7vd5Iky
rp7cqHc6+nIAhKfvJzJx2iwcR0IhxZdJJhgL6Da5Jp2JZZtDYKEqriQ5ABEgkpMuML8Q61B9Llly
DxXxSW8d9nCsyIY0WYXAATDkBP85e4Si+GZpwHD04qW/QmXqMvfimg6YakIChjMsJtuYqcqbcPM0
yG7XNRy1Bw9ugMZv90HSyruouiFFzZLbVpNadDIVMQhdcpSv/GVQ9jtBXdl0Ybaf/0DKbyFx22dk
Tme/nkfLuAOs0oXypUCZQO+2kSdzU+5scgCLSb7zcGwXrbwvckGb1DJuKoKAoLE2D1ZX1/ywx+Ej
t5cIX1EY2A0WtvLpgxkRjdEn9DVjiMMOmoUvFtzyqzNeHJJiW1GG6FUPMh7EgtE7bVMlVBP6cB2x
XB3DZ68bYkZzsKLphk9VP1mIGAvmgXJXEyFNZKF2xzZr2oEDR0ZL+v8lMtl4/vadFSUC1uG2o61Q
panOXTluyf/5bYPYkX43YIqv52r6fVyzO40kLoCCTL8Lm4W9tmcv1sfHX1MB5NTL71QdOc97JIwW
unOoCLDsctC4nbaVQ8hut5ussf8SQHOMZHAT3g1S+VWueC4iob/OZP/REH2b1RF5KkFbx14xzlXM
vyUOWq5mAJT+FA14LLxGBHRwwaTyIZqwI/KtkSJbrDXxp5gFjIBizrbQNSW2183gttiS8hH3NLv1
OkFH5Co+xFgP4VajkR/QAKFdoUPIVUodzF3gwi6/UBJj3sFbZwTZ8UQ/tzNJ1IlOAIDVPmoPbG1N
fhIQUWDsbzmFmwEL0bVbL6xB+eWShhGyXXjauLnJuSx3dcYVDJW9bdbBj1b3RJQ1yokikA915Xud
Qu+NhVyqrR9j1mb2RRJTICxK0eVzc0+cLOD7ckzGXC0/ca+3qdIyZy9OODJu7yKeSmCTnwFuXTLc
XWuJNqcPxiyPzSGjBUculHR4tvQo4ahh47IHpOZopN6ZDu7jQckwIJt1WX42zQWa1t3ZPfx07+MW
xS6KJfN9D14WSg3vJvecnAz446bDfLUGkqsHy8+K1X5KvQcXoX1aiVav8m30WJ0BsveEaY6w6XyN
zl5GSqwh4/F/dNBr7blnAjIeenCLzrRoyW+5JWpI/L9TeEFeSUz2ciA0UX2zV7B8i8/Zmq7ij+i5
WiWXpCiVjDD+QtF3sdvv0eqd9/+O164+NRVFGoe9ozJMq5Dq5RZoOUzVmYOYkiYxcLD+TEpJWQ7s
gnTBJQ0wcREiM4VM95Peay0vxuOYEHfRIm5anAmBKx9F9fThabM+SUC05h8QlxqfTxio9J0+25dU
0guD/HAuhgQGUE8PfP6lAKOTKXbie6jNbRQZRHwFPi2F0s6mMcY1lQyLi1lvonY5JmJURU22QeOQ
A5ovnNQcY8plgSwW8dhy30h55GMRWz//B9MikN4FQsKW2QFGkXsd+TYt3PgDw8qGJCuMU0Hc0cUa
YAIqax2fAUwJKzeQ544z7B3HkU9Fl6eeGmtz4I/hjQrWLPADrd0/0Sx9y0XSW27woHC0RxmiTqJe
10+WamHMYl/1Lw8XYsVz83UypoKvajIyT+zQH13+XHaINQphBpnz0s8Mud1ls/Mmy5nTJkdxV78X
PbZSATuR8wgPN5Nm0LDKcx3jW7idmrPbGub6PWdduoHPHkHv/i0snCqv/HjP7/noIfq/amdH0vFz
dWm//S632jKPrzoSNUGec8HtdgH13+bSIXOF48vwOM4RSZZcQxOpL43CgqG3W40L6HLJDRQnMS1F
KdQs1nPdl7ZYOSAj1rTMz77cjF2ASfIIlxGvFhR3sh9a4SgxEDQ6z2xnkiKhijAWKY6XQy5ckzMt
kRD00RzPZdWl/lMKycef6YQOmDQieLQ+yND0RYtk53n9UNAyyzqAEpuADKVw73tN00nc3kRRdB+/
xsHuJjmefr/jJlv7kt+LT4EZp1pmpwxQsEfCO2U4iHKmHSqCdAep4L+o0JE9RbRXj+xyJhhRiFLV
Zxxxj0Zlfo3iNgp1DIC2iPmjr6ycKHmHgHeyBA88iJbVMM15LvuFq/Btx7VRpXngqxLmkdY5QpbS
Vjnk85J5CLy21pPs5DesRXMIiPRUgWMWtOlPpco76n+EsazWb3Zlwhik2GusoFEy7XVWs0TxF6s9
ooi9ya20G8VXaty0uUsG5eEn9FV0+xuwIqUNf1/DYwjQR8VJQjPT11euAKwT/3tZt/Tzmo+RcDK+
M3dKwr2ID33Nf16Rwn571vBMyEtjjWtV7wuRBicFJitbFiusAejgHenDxKnGziBkipEmEozKVnF0
FeFgTB9+Pf11PGQl0Kl85KirGWP9aPMJVNqlFVbtMh8VXGojplWE1au299c8iUC5UlK1jEzIUCFk
yrypINel0XlIDVGkRwRNSXW9qZ8Ycr2NtYqetmxYT1D8Nlfjyef472BclcOy6XHJa7+ivVpwWmmi
eAPKDclaDSS8yPhlV6p0cExAnrd/BYcbnFgjFrKgD5yA/Ha1zMcGg/XYukk+TJn3xyHKqkXEaTf1
zkNHzK/NWMN12dxI4sMeIC/CBnSIWkTRJgDDJY/6gSsrIDrb/TXOgnKAi6GLFMCM3Y6klhkgozRN
6sdYx7pyAtX6ugGYYAwh76kQGEKy8SgKqgVYwg4HakXUFcBL3yXwS2wV7u6EBDeZvD2uZ1Qp459+
bm+Ok/oNxewmvx3iRMDzxlLmRXGxsfQLUkTJDwFjg/47WC89aYTH6Hftc0FXU5JmmEsBCIHYxScT
QY0dgxXw/pxQLUv6oQxVTVIFK7k+Ed7huQ72seBZXpUAeb78uo23dzE+5ISwokwXZ7Yq/LbsFyJB
8Uxthy/X/k3ai3ODc6vFO4HTbBSjJM/3xKlfjyOXfxqNCnpyqKJynkqDZPOmYSc76i/jgVPQpKqJ
5UXz+oBC70Pi1xfalQj5DRAwKkStn8pCocrphv9NNH1H8ER480v9FS3He+Bn5ha1JKlYRE/t45Gb
Z3kNXiYCvQzdQRh1ntUclBV/iaNHATsPul1gfZg5Ao2t2bFW1hnpYFlkpfMnCm6khz1BvIyq+qDP
SdpvbcHxbVNbLY86S+/TMXRaGjU/nVs8lg4SH1uM/kpuLi0EcxT66fRCVHSt6UcwjQUcSZdsEdry
l2Qi2xDGeOJl6ClbQeWryoUJt30H2Ta0250EssIRgPiuEhowDN9eC5QrWiN0R4S0IVH8sLNf3T8J
sgIg4Y0/MwscmLTB9VNC2/IgQlsXAsa7aGApXSArbv0tWttnZkaYsmAtPmS+88BA8OC8woITs5ux
QdZreETBnfiyZVAU/vP47F+453m9/Wv6vjM2BnjGgSgkP5vXAoPYXamyw4apSCqWiiAFXC8PVW9P
1BBixZcKfWz63285eVfWl5R3p7o/axD2hFzyWaEOzikBwBgmh1X7tU/m0hmdhBKE+wfWy1HexEcf
/UNyReLHGhKRMTE5knGmtBlh3xbxPSfoiVS7kebx5u9huXVLT28HcY4D+0NYloZeyni9QTwQ1ZAG
sMNnwO+WU74vWy1bg4okwJJ9hkHX9A8O2CjA2qkcAdUzbVGsTIgVJFhF+WAj7RFgEzWgQjcBsh2P
ekiKIzVxjnLN8G0LrnQLdO4ezQUJjS7HK/hFwPxiGuiC45VcylP4NpeZBd7CB2STddmOkEnj3fgi
xXvu+4CecdNGeGqLum/LZGse52B61QGvuV5YeXBViQosyaQJQLaCm/JJIO9idM99qaMETMiKz7wo
QiY+UZJnj4xbpcwnigHwp2Y4N/IdbfOZfJ5g0Hrxlw7UnLZVgfaDHR4sWjS/Mf1Yt8rPOncRbuON
S5Q5oyk6Mi6RW5n2BHU3hdqUTgexr4PpieVYm9heSkHUlyuHqTASloHJEe1Xi7eAEElJtfX8AKQ2
LeD6KhHaV1gp8EKWVFkg7jkInTgQ0GPrZq54CxXYqiQeMW1SYgeDdckdIPTkCUhZPyQykyKEU3/W
K8nR0lgpkXUD/BMmAKgAy0mWqX4Pjue6MZ3rJovbxrn72/63Mjynz5SJWoWtJWjPB2mVFeYAHRt4
kgg/yTjWffJaLTer++eKmhlj4AExzZ7LXJY6eKA+5f7lRg1NPfJc4twaU22PgzeVd3hsYsBVrttZ
0akIYLBBEQbxodzAdKTpUcavzu0M68iCtEQ7UBVTsArWhItcNBUryTskpBAvrGRyzsoiH4wrSU9E
QK2tYBLLcoQMsi7nwXzeoIGpJtsdTWXs1dcaZoGEd9ldapryNiaBUwtJdyk9+aAJFsLkyEX9LO/8
nnvUp2knpF1G2o9n7ditPJDyeAHbJ5O9MnU/eT9EAf1boPYxHAXW8IejrMhVHu/bFIVzXBx5DSfG
3QB0hZpTSFghBVZffhkxxF7tCT76lGRIbDfFWE97c79CGXi6ngR7RmdWkjYkDNMq4+iZPwqb1SmU
GYEQe3tJ73hTo1Uq1mTPnRHfKve+TBy5CjPkcuZ/QJgeDHWMCBJb10hIU1I6sJIDT0etR/UqxVgX
w+0zdHyymEOIQeqFl05V1mFKXepsN7oKbCMWRyw5jSCqmQ12w6c4QmisOE57FAW2jQ4YOzSa2BOH
tWRWnndHpylBCsN3PdgBfXZp+/AKbzmACiBT2+qRCyGGsOfOX27ek2EBpy/MzPle679DDpUFpFBM
jZQyLOf7G+SX55OCU4Hj4rqeuBouDkpa7aXnaAJSOfYzM3d0WBasBbBI93jkUWCScBaiD+Vj9Dmf
MwixTDjtXgjDj9JRYEngVJk1h29yb5cWuZjAnCteCl6cXyhzhn0ylpGDspU+hFxW5Vj+TPm2WiUp
sRHFw62OQeQQRsP07dDgcfDvKdFrFw5kz0hQiaJLVI61/UwqNWG20HkfbUL0KcQjuYrLWJBB5ntn
75c3TMrbi5FwxrcvJjqczjFDuqI9i1rLVvJhGGlBw5fzDsZLcV5GzhKVkDt4IBxHA2xTjdHXHCBW
2GHi7x7c55vszaZbVowTAwNmhQRNW6h0htSewCZHQwFXZL7MLtr1pdEpA6+G+qROYNaF2OrGjrE/
THxCQ3bswHwRHmodll6+qaxwJZNNwJ/+iu4I5SqlcNmzvAa3LY8loFTiuxMtfzBfogw7ZvFsO0Mu
pfOydCRM4r+nHaNFeRsgDXaBwSogE3I4fBzF1wonNNQQy50kExKrBDtI93YzNNQM1OQKPs41/SDk
qevnWWujbzq+HuBC8zYodjqTxChaViOQszovDjVpTpVw08CV2UqGxd5dY+8DGWge+0nmzEPjmktV
FK/a/kq4wkrCYV8+c3dhtxqI9A9Nnj4diGk1cn5Kr+iILp+g/a8CqTvM2P5Btry78781xD3x+LAo
NUAukogFhwAlRNE5tOkJWlO1BOSDGrDVfndET/Hg8PdRAkz10NL8ejasZX/opaMWY1OeK6dcY0JI
ZliyKHVv1NfSTNv+UuG1c5ptxmdx3sIdIjDYgYt8W9CwOrR3R+OwYAV+7STq+s6HQU6Otj7cTzEM
ZYoBhuGgrQdxw9UI1AW9bhou+XA5RpChWdMdFoL+hj+MNo7k2aSJ495Fgzb+2ugtcwE/sGFFQYOd
137hRIk5djye1U4cqEtXeSPq0ORoKBtuSn0YAHa1Yi97x55ve7dw5f9Ti/Sfz786evvHUr+j4J4k
V0eFg8+aff0/UPaOLN9wvr12lGt2j30it446rKQtqflVv+RzyvcAAM7nJkhzizpyEGiKnPTAV3gC
sa0ackgRwrN+tlOealkGH0zQOFQ4emKx02I+xVLemZa4sTVbc5F5uDNDPVaClhMoav4daXKobJgH
6cloiHyR1P+R/es9u9zyD6Rb1xGWdv+3JmHGOR7EdIl/xxB/ab9eidOEEXhxzKEK3cCAQfjvg7jB
S+T2LTCLEBmsvuR0eGokMHU5KnUd62FzjhtQRcM6EGaD6AZ369Z3+dS9H9Dy5Q3xB6xsifjrFuaN
EANvu/SCR4UnequMgMu1RZrCuqxKuJYQl2SjarcGs48Oa44CmVaci/i4dp8yGk4EfLMp6D28BrHO
A7rzrn1YHHCWioNgyfn48/YiD2y8MmkN768OQSjTmPYeFwCsR1cv3ZwyNsPX/m75VtFI1Uji77fI
+wvHTAl6mT0y2BBD5UZd3ix5C8DBwagHF1Jwx64exJG6JF5oAsIOs21EjGYSfzr1m3A9pWbqK22u
8WhinI+Pp3OSkHNv9DliN7/3akgfaCReckfPd93NOYQ1wzdMQZ0QQLvp10fSNOpRMUOpSi9NWVCR
Dtk5t28sNsA/PNmW/jnU8XtqaH80uzk2FI6YKMTJyjA9JYQoD6EcCOuyAf8dyKvUSaMy0azDE/KU
deRgGbOVpvjrBaDXYhbGv7mXN6HjJsUcT1nRpWGXbJcPhX+ioUyUYyz9h7OSnnyq1zqCy6L/dtNT
9IiFm+Bx+wILCf3/Ms4WefGfA1VQlwDBjyVDISutkro0YjSUlsRsrvwlOTIF5IAdejgCIkSlR5V5
i6FVTpsp5yEzU+BBLkAk1mEzx8XnSR96jLVzF+GDsrf1Wxg9SNcZDtPcdoP/+7sXcXJG3fJHaFXR
IrGpOs7tOM9oAUrIu9XVx7CTl/yUVZX/xoYvrDyOWppvngOvSGCOrGiZ62PZcWMXXierTARqsm0Q
6uhpaapXp5uJts2vuiQxQOzhmmbKpA1Ias7Id77hF25Unr0dLXm/zWhdOei0/rrRhKP4bBPxITup
w9aqAnmTnjnPGcXGFrdllvNou/bvJjoM04UgX/qP76X+ou0xQ6uEJ+ObNKQ588HBfGHiuGUblfeC
hWAlJNo+vlFjLr+OMxtS50Qqu/DLlc4P+x2GlnAce8NSwLX9l1NLLu14UCcyEdAekT3wtYErUutp
btscp5mAxOxh0IHkdGU9oPumWroMigIjGabOCSMq7I99xJDGofnv2ycU7BPGAoHA03NlLjozEjkd
8Jo2dDCDOg6i03RkYQDLSaDM+57fwDqL0Yd4GghB3NXkysh6zB/0pk11AHh3qP9sSgL+Yv2/4xMF
m/DRXg3teBj7wnxwL6uCxiNtfTSIjCQLo6a8ctdyeLPUUnoK3g56t4vbUIY0sp4BYnJjag/UXl3u
gCBJfA9GCm5OqWUfoH0CMNsVqjY6kjkn4lq1mdkofvAmz8TaeZfoD9TH7oDlv0mlJT1vvrsS4S6b
UDqz/FLpG1+O5B7lj10yRVxjUhOmh7H7XDusfZ3Or4rqR1+RDBurgDYHHdoq24BEnxpazLO1i3oh
PHYNZZ9Z+v9fN9VpunH1ArHW+96yNPqZpjDBKd6mFDHkEspkoP08nMWcCWyIubG1MEKDkOL+VKY7
lQNIHrSFT9BSawxzD6kcOvHNXD9XyvHqYooBzeJhLrse2HpnNZn3i19FhONHtbfuy1tLnjRHiHkD
bm9k7ydVqgSEtrcNJnRR4gTP5kwyrVpfRpj966rK1SSfN8HNKoNPYEeN6y7OoH8hnwRpMtWe+IYp
obKT2oBx5TCGvvMkR6Km8e6YuUWBJqZVnXn5vnTofad98SkTSxaz4GOdVEwlnUWT4uGa24LOYgWo
v/5A5Irtlmg7ELXxtJ+5tovj0a0aUk0xo4YwWA4ZPxKaGMjUH4mInAHjm6hZDdgizM6M377I8cbg
02XGA8JuKE3tl+LBY1vnTNY7EYwMtsVaQiBUkfP38UTj+PGl34NlNUFzLFNqzSDmAc3yvZo/NeSd
8o9wPEr5F8inyDXITsG9QcLZYC3OlfuEf0qeX3d26SXisfjSxh21Y3jTM6Cqd2wvWTlVJAQlbjdQ
Z2kD6NZMpHsmzMZzeOysBzlzrPLy9ZGgFDWfQj4cl9RZ+OwsuY9RsrxZQBX+V336PZcFtgn/eutQ
qpPLrPghq+bs4q1t22/uKCz0f7pEyCvACrHQAk4oq35OKUe8D2cjUGyuL1rfc/331vZNyjNGYkyL
ZLcSMnQ+gEOJFC4oiizpac60P/v0heRXHYlwe6RlMj/POZ3mEbWe82kLkGN4e+NlmfhiyqAmda7l
79C8G+8D0CYaWaU/0ulcuxo7cf0tRWx1/MRKqc7ZFQ9kZ3x20pQVTwCj9g5tur7qzbXBwNtdvNrN
xZL8Iwp75gZ84UaE9AjumsHCUcScVhmfsqtMz358QZ/JoslANqYQDK2RIcFh0HK9b2dddP8ZztLY
zs86xLn82UnCqQOtnJUITKLn1t/7eEl/ObLTkywxdxfYjKc9vpICBYch2djxULgHDtBTpTg6bSEZ
GCUMeZcOZ47IRQve1/0azBlOSPSv5h3PWweYvAYJTMR/YNV/fyw7H+52KqKYjjI2+1p8Vhw00yJy
zQ8Plme4EHBpCK/8W+j3JmI7FPM3KL6zPqjnmGFznCK9Hf5//ZkcgD+ZklAn/1YAsS05y26p/3lM
VOrw6ZOTsl8yHduhBihGi34rxq7tzOloLcpvrKK1hFx3iu4hvbeMvuEUZttsAXMLWJtFd/G9tEHH
MkfZVtMuu/f1bQt0EGJA9x0jw7paVECKthvno9qZ7AsiydEU+nVJWtj4vCL2SH3/rRQElZ60F2G0
b0ZV9oq5sk0zm5s1+x2PAtqTue+cGAK0GJSsaYawF9fG71KSakzBvGfQ760cPR367YBS1+/eZaOR
xM0QK/57EcmCFwt1zbkdpQLbdeOE7BzT5fPRbhiT6bgPcsdb5sPDmqDdqtuznjlgSNDnUkvvl76c
cPx2wLSp2B6S/n/vHS3FRY0LlEDhjijSkWqbISDbfK/brQ9ZNdt1ZALFCAU7Tgakj4yPBLgeDafh
M/ITBsPIeEtTPTdgWMPxVe5N8x2VrFX2D9s6fEzbicwR8JyNlMC6EVNYdqr5BvmWT06jbCJleemy
28kA4UMLsm8/KWstXA29XKWmZU7zQR+DODTF0ksn7/kAZXbgKHy1KeqhCgm6253ICoQ7giPf62AN
FLMYiam0LDV8X9ekq8f9QzlLfSGMhDtmcCRxJ2HOjc2mT+3rcquCyZGkCwBtBCirg7XX865clQdh
wWR30aiXhCTi7sgGlmwnKOJzW3dQHkBDPdlhXAOfBAE+kK4nZolY3meilZJFRF+WrEhWBcdSswEk
d/UjZ43H65ZFf4LJA7nQj4tkToh5HrGzbJCFUM59NEDA9rwKqrN9OqGjexR5TirzAdqVPryznkVh
PfY5T24yEYW7uv4w4LOiVukkiyPOKn1EHj9wI/SyliBa/bTwKjLbi60ZEtEqqBFLdnEKt4is15pH
mqvO+/35YSv4btnlSiIL/oFnMuQeyjAxAVy1z05vg5NuHmUjOIQyq6ktZs8CY/i+gpTKaRHEpfYy
2i20K1k/JtKL65tRS6Xs83dAGrPx2tGHSLpm3ZUq5Cqi7ytv9UFjJN/VTGpqpi/JLHBw3h8x7+GG
P/Lc1Fm7npI8/HBS4QWeIBATsW2Q+bVmnnI+9w77RnT86Ah0VYUVovmzf78hqeAnqJGE3Xnln6uH
yfzBXfmaeTbE8/7vmz6EJtcGHxxfgp7lWECoGFZ/J67UpKpW+jUtB0kv/IlO8603NvuJS+hYCMAm
Mg/16MTtRudlZ2FOS9IibqlZRGIje6njDrwiEpQLXNq/do073anzwAWqgvlpksCrFMyJ7b86K0Zz
0JRZbP+ikcGZg337jEn6ygaYDjh5SEft7h1N2Hs1/f9tYZZX4wfjh85TJolwj4wgWPcg839seHQy
7yCRADuOGinRDWNJo8DZLJEZB8oHMi3l8i17+byy6Jfpq9T4WOlH88uJRCVF4+VU3XFVEC19KGi9
qL5NE6lqdmY5MCgzFycphswHCIdoskYbC8/sb3rtjdOGqy7zel+DGJqSg1umxDENi/MDEp6GBZNx
/3OJtqMmMCPTNNdavCcSPgJ1HXKA4o1SfvFvbgTFgXN5LNhrdWGQsqPSDxF9MpPPt2TeJ8v/wGh9
H6Qs4CdwoxVWcnw+LzgioyC4sr3Awc9CxCwaAv7xt9MgNtD7NOlzONz31DfGMfx2CFsdIYtQheN5
NnjZ2WCrgGRZAcTs+Om+ZQ0qjA2l7AuGOouvBAIONII403MH3eH57rDIDvmOshmW3c0gCLTidITh
0/7xfj88LK+6y2CaLqG79ju90HQcFOGCbTO5I6otX/94Rg2vP1IaV7TE9yhgpPzSCFzNSi6sje2J
M9Fjc2zLBlLyHncOVPbGwbwh2VPkvnOce7FS9ALh6sCFnQxHJE3KXnG381/05avzBPSZKPO1BaEh
eHTken+z4LeDihutOKObGGctziQaDd3r8Df+4bJAPAzxQoHxm0Q2518I6fTp/6VNZm1/jmuAQkt/
kSFYBVVqmevn3j1cEk0/cfkbGa9iFl+nOAF3K2hQzUlmY6ALEnWaEwGZjVmCPXB/BRo47RmXgtUo
AkXMKn2oq9XJ3bpFwljHV5DfsTQAduXdy/HvleCefuZ0sKD4Da6JGa/R0B7xhIFq550SP6L+HR6N
aKr8TEKRZoNrhJJ8q6Hy0jyle9fA4nOxKV6uV+BX1e0o3q4TQNfUWCyHP2pGt1A3Cq7MHXMOPhD5
C3mib1FLlrlKJM7mBzDKP96xDHKm0ys3rMZ8K1xD7YxRRxSNpxL8EANuEPSYbNyFRLmR3qfASnQ7
BH3FGwJLbCcrd3x8ncUDYKP1CJtJVBDqr0N+G5fdpW8YQL2zQMp+GdV3w161dpCOKDkrX8WFgM6A
NJUDem4r6nsV662TmZkPGQQElUcx79OwM6GLiU4fN/Q+WtHlIGuGKQwXFXbVlcuFRq8tChL6NJTF
sLDEfT+AbD88nytbOb3WbJmlZZ6tZBBVj4R7iRNM4E+zRr4eyDMXbiXkmlFtjRVKJgjpQ9wNMqvA
46v0FK6ouulZytPGiUB1Gxqn5LZVrwzC45BNZ85l4RrNDeqkzGVzxSD/mxCSKsvH8up8bqSfURWO
PqenWLWjdIOsXNGYedG/LJWpi6QnsEnu3kpAGkH5IneTwNGqZIcMrWCt+YNMfQfmGhwDnHLtbhZd
FmTOYT0sicpvOGUf+p4Iihcl5TiVvOknRGZKZH5yhT77NrGyZhH+XluOHeVL0qfmVZe3z2sgEweQ
8L4gCdr9qSARShJRx4ovv1rhICrWIQdUNBo7n3azRiqPpqCzUsTaJ1KGS52oZfWXic0UHzMpnvLn
r8z2MBooD7iwfDguIMk6Q8zeQ/R594ozpmAClXWhji6NKWmUh5mSeULmY3DFUme7Y50waxdND0Tj
xukUeoeY3AE+diUYpZklSx52OaViDlYjexCoMHNP3XCPdAUKT+IL08bmWo1biSdAARod5btW0LQn
BL80PltOx7+5ph6RNFh80skhC6EOma92qMU8MmCEOQzP+yLORdHAa8hPQd09Z+DF+MAP1Hv2unwg
htlUYKhY/UbYWWezf42yxT0ZPbT+xVdyOqVRhmNxH+2HGTXWviB1tgYY8XXc9ZrwtIbCZFPKRsh0
M3XePYFKyqV6kUJobRCRGIy7skVxmJ/iI7eqmQEcNPkNTn9RKYdoq/XD8q1UR2AN692+e602JjsC
FaWLbIYKW8nNiCMbCE2fwzQuuxuW8QV/aj0CXHnKgHHSP7U5vQ5YF0SJ/QU/h/8uxO+V3c6z6e/7
zPs1aYQzRhsVMSq3gt2zyT7NkwM3nZv2fFOBx7n8lLjXW0Z+LEFuBw5ceVIqXflW69LtvZDciUmt
kYgllvI5cpTvoj2KbGSAcvhZiYtKujutX36Ske87xgUzKhi8+GaCKmWx0of0kqtMp/FTtr/fszk+
zFKRppfbYWCu/SQp3vRRhPpM4bpbFTfe+eDssut4rK7achMpd7bGYMytKqhDCVmgHxHxGlD3jO5A
sAmFvAmVuF9gpvZnGgOcDJQeDKebFN9s6ISey3vpe3xWzvi3pnmjy8V0IPgUOolylt62HSMgN6o1
57HCP6jiU3oQSfaJS6SK+Utv8+7E/jwy38y3BunplNgcBWlI/Qn8KxUWWcxDU7LHN+DnOwv6AR1l
Gc0fbPtFaT3irLK+H67wJ02pb1AyrZ38pO4fi2242Uyx0cSpLMVijREMBn92zThXqNUkuY5F5IEl
xCN3MZOZtdihi2sjVUwXLK9ZDLldjzmyJNz987l4n0hOxpMos5vrZpPeVvmKsGJaPKofuN/khu+g
fitq1PzmlDT3DSj3iEU4SnHSUp2Zci/reaKxX6/sOSTMAR1t+8g9sL9JvQD/ny6wQrItOuATdraW
vkt/6DLqxDdh/2NC8GaMQng1jnREd2lPu+MdAK0dn3onFd+VCmknVkFAFaE1GlvYYCgf9zFvSf0A
0lvnLNA///a+Eh4f2Bo5EMPczY4sx53r15l89i3axJm3ceM9MvLCl474KPibEH/6cgEcffpX8Dc8
ckZ8fglJhVwK1DHsg56j9bqMNlQWb5AQKGnolCyxGqZzSWEPB52Fy+GyiTHTFouwHrU2miUt43ia
wKhX2PLQr0PEaurhtxCh/nX6lQIYZDYNDG0ERiw+zOpjOALCp4jk5vXCj49skesJzhBZ2ThLn0yi
o9NjbvqLpeiPBBTi6m629QkJr6n8tE2JviMN7VRyfWHk+a8zrrbEtcsQW/ugjMK9axpdWbmGAcpW
f8MnXUZDXpD2HFUjB5O3ot1807los4GHnERhj/d3S0W7UCA2OgrPuy3pZoydZ8QCCvYvSh9MpOfH
9TUNVpcqQfeqq9+vq81UbRmlRMgIqIwW8AxkT3exVBPamJpq1K2uBc3mEGyUr91Xo6hr7mqq66EI
yzVS781aG6yeWjNDfzN97VxfzVCcLizDqDBACkKenZXy1pJE8fjtD5Gepk2RLC89+s/4bI8czcU0
DAd0ZwtOSWKZXMbI0ODcBicKU1SYjnDfT0s1ZKOix7KTqVLpSMtgpThYx5eVvuqa8ICO9+Ri5usQ
2kwRo7lGn5YamxqTarfD381izB/k2KURKtcgcJemU9MEXjD5BaMvWoa1nPQ1zY2prPbvFXcsOF1o
K/blgppj5NQEDQexw73TXoQTsLWNyMBEwNshEGoFyFgsM+h8oKtVKH0GSxxiL6SlFkw99YACCk0F
8QtjkX/IYLdHKmkmJHQBHdYPVxsL0/kv25As3wZ+BuOXgkPvmUxT4MbvGcz/bflHT2CrAH/XTRLo
TMFhoZkuf/JSdUyskE4sR1yWLbjLh80aUx9gSXw5qXb0jY0iQD4SoDQW0FRR10AMZ8KuByCDnh41
/Hw9CU/CAPgpo1uJl1jSC+JIWnDdPI6RY46J8zmM8Y4k/QMLRQf85KrvjoLifMl9AHdnp680UVYG
YocNBTWb9HnxT1gztPoO41m7XqLk83ZjBazjOpT9LYo/diJcAd6DDb+313vMkeQLg4bwsO5fdLqp
N3qNlvgR3z3jknYOKaMqNbUMA0AMvwuZ7Vga4TQEpjjm3klp6QBmSQuVNNYgLUQuF9CNLbIkpmJO
akYySxlqHzkhUjvvJEe0FgKx9dNEi75MtaAbGKSQg/w9ZGGa6m23IO3d4Np4wKT4ry1bjrdEP90L
33gQUa7hgj9f6sVsIRvz/YhXmakmihem8tbR8RGR+8P50Re3FFjPxtiGVV7Ptg7yEAwJlyfrVw47
nrJavJ/iimcpOyssq8J4hWwb0KqBnblaWbmhCsE+S0KPJoIz+uEUSTO09gFs3fMwf+5ZnL1G6+nj
E2huHoW54zXx+x97+G3u31Az4axhSBcbpS7f5UioBG656spB0rtsZAPMHGu2h5f6hlmW1J4GYx5u
TM+AKpxQXqIcN09hrQemedgEgH5rIVL62Qsg0hcxkBykJUqU8Cr1em+pONdG46KnkeJB0uE6kU5X
dsVejSn/VuERJOptgC6zazzTTA1X0hf7HiVC88jhmByt9rfqBoPOWgxGUPqs44Nz40bbd2So2VBw
uPh7pjE5wa1Lrt4sNYRe2jnch+URo2ZP1gNFDJuqn5tkv2PwgBHAIgzEpz7ljboCTfbVorokq76J
HZuijIFT+L/W0qeST+D7kXe+liIpPo4/rcxrRwvPSj0NxB1uaLEGGISVa91oCBXQD5/uQdrgKMiK
6RzpW6bTlz5R5b6musSFUVcgmYNNTTXHcTcpLNZyv1XAehN/Njc3d9K1upp0P+xVb6nKjLenpKwS
kbP78jbCPQXqzZXElZ8kyZMdvYV9j8bE+fLuh7xhPtg7E1JBcGcIWvjBebs8RwNLdN1h3rvLU2+W
Gnlrey8eci2c/hNV6Dkh+4BiLJ0NrHlZzsT29oE7b06rRQUuuJLm69HFkaWhA1e9iXfM0oQu38da
kSVwoFJiXEVpXai4GuLcZXZy+WE+taYMyyLTgl1BAxqam3ZFdjBBUOup8+YpLdViR8Ix4ij437Lq
X8LOjt7OJjQmFCzjojxXNJcWtsCae4IxWy5YnzOiVAYHFMFCEAapFxPLIdqevDbH1OociSfkf+dY
7TKKjlyW2l3UH3TxF46Fp/phG12v4gaepdCpIh2uUlPGuUqwJhPD7jVDJHyabFLuvZblXMcMYA5b
9ByUUO3eOTjwAmmUQ2SLr04GXSs35KYjDEHQNx362nYdSr+thzMDc0/S2cRXPOxVfswFETYTO7zG
bly+vy0ttErnMTeynjnXXauUT272EFHnV93VGivga2+9ruPFRklr68+D22RZSJDnEGNHqCxudCn/
jWJal5/49dUzd41yJnrYYXx48IwlzVqn746+C6MxEgut/J0fXKP6wS8DYhvfrEycdmXzvdsuo+cZ
4uAGHotIcyiZ6NP8a1DodLUGoGcbx0JG1skb8g1RI2YOax4nYytj/TiHpTf0suW7x0sh8lS5zN3C
zw9T94FAka4pU/HHeE8eZU41YP2/bZ5wb1Ki1sXmVwowcOBbX6MHQy5h7yh9rduoL1IzK5ths374
h6qiKnoSHIG67zDtamTBqXr2EwMkwdUGEJWrxJckRItQ+2WBZeSIk9J+hXnfO0Ju0GiX+6cIw+c+
re9AHeFZAwsFwP1YRbhsy04Ms24uEDc7/Vn7ulOqjcaP1NKM7AHJ90qZo10oyQad1bMkfz0gRmLl
Ds1wv+UJigC2mQQMah2uJw4g1+x2aNs2+kdzNXZtWvo3biGiU0YKSTMVIkggU8iy/jp7XWlrQX3w
/mFmF9SKM4QoVKrhPpkhjqSMsWK3TwCcytkl7GCX6gShEFxiq74r66ge9XCCv9fvsRRHLUtgmRah
TM3woo/1fv+Q3NYLsFNwx6Qe/BbiUxITVLj0SwAIgTku1E/t3oRhMZ3UkWd+6q1MUScwvJHoxxpM
yLlRFzoyQggdgeNISMMXl2hvXxRpGxPCcdFC0z4vXPoyqF54RN9Y0Qm0yUaz5YN4/Z8tuk9i2DY1
MaAxOKpOx5rG6AgaT9y7uuHIxoHARBxl1q1CquN81xhxqn55sdaDD2+4ax2IJ2qG8WeEzE7aNFHR
xE7uSZ792rXkT2cyYzfwabOlGiWu5vBOeN8uP5ILGhHELSGNUp6c9qyLGluV0rsRBjEIV06WQF8d
euDvDbOguOpdANPxU3ry8kguIT3Girp4/TBIK5HebZrVGG2t1nUOtw7zmK0dbzAjds53g+CjgekA
ZrPECM+GgFi8JbfY3bMydi6TdoL7rN8Gy2IHPloxSGWaQCVCRPhYAj02S5e3pWvHDMgtaiXEs3+m
Q6z5vmUEO/TH2EBoHQBGAZowugTZiIqRGkCz+N0SIxvnvLSHHwV651hrY+uUgHQh+XwnIT6XwU8n
3rr2UIGh+8lTF2vqpzYUlsVDfxSjP14otYGYiGg3znsRmDNJew5qO3WTL0JDp/1OXlTL5EsePfkN
/Gp/XveIpapbSkCW+KvBYEkn/tPOW3yLzqS6HGfNndOMR0Djx8La9Kj9VaZIv8NB7vFxsU5Cy1yu
xR2NKbTVfd8yS1ioNRAF0/D4q+IjVOLRheeFAQau6jlDmqpFpLU7jga4FKpscLfSOJTb7aO44AQZ
SU8EHY26J0MxnmbwFx+8TEW0plr5NeS6KfgaPh+Qlez2oAexHmOzTOxlsyEwF1tXGwsfUQS/WABt
06hlSGkD/BFAsFHF7NbYcyfmzPwvvyMLrG7B5tp4CZLa6PQOlRA4DId4gIBOZ7PrZdc6pMXoBlbJ
XEBzfUJ1/X3evSDnoHYcn55Oj51kI0nBxkG6Q0TO2TIT72z9Gsa6YXGHWEL9VTuTfTc7qmPvl2Md
Sc7zx9mArfidgO5QIUYzbjHaTHGBat+dRbGTWQ6giN4J6cn33YoKjpJWTLfoL1PILnVpohnfgJI8
y5tCa7GY8qmdxvZxKpyY1EmcHnRWd0QneO/Dxu5Ge85lBPwdSSMkVVtqZUzZylCIhe4vbs9f9K0A
jnAeUpFcZuy+KmX0DoHN9/Zdnlg5scEQVO2FGzA8WkB6c77Av3SzAhNpIoqXanYgmBjdQA/BS8Ws
Rx3eXFD4U+UPY1BhlkzFQJy7uk+mxYsjjvtS7ErZqleDjSOMdW0WabP3sAzY5ghqLlxwZ7qTtZkv
pw5LQ6p2p493cHT6NZkKAqbphsYGMHr+twbIcKnhPWFJBHPmjIrTV80G+dIZZP8FnVt2TqBtxb50
fqzWgwz9GpHccGQm2//mTY6wbapVN+W0dW+ildNoMhYE8A7J7iafAyvLcGKuYFzw8rcI9ZQowKO5
3oRxotTM4GfVBuE/dawFOwd/fqUjca/aluT+uS4sGgzmE7IKRQEv2akPZcmy4H2QVEf6+FOBpXvI
fIG82J2wth5Xr2IY5LZR+JhsVvUy4CZzDhFc+V++Np5FqzOFTBQGiNJ+/TFFv83jYY9ISqYkGGZW
sOA5XT/l1gKJ8HaoK/oBZNBVxRSovTzPEzeWUGd86pMYj0SLyAcJ3ZPhyu6tUulRfkAyTXwFYcwF
M4TA9xJQs9KSk25M53cy90iAp+TfJLWVrwyXZSCendPCDF49IRIgD8my70eb7gQeN3ACtfDHmIhR
6mH/yawWFvU6H8EPdOvACDFs4FHYJtRdWAnd//8hx9QY1BzusOskgSs/tD6lEpRV8B6IyVsul5SY
rznVWMAmc+seO/LjPjVVpaNUkb+nQN1DxU5XHLIFHV0tcOzUYks9z3tZ4sZdSFow27asRQvqi/lT
CW0qKgYCfeQ2PXDuS7ph+wbUon9/rStvi+CqQ0etuMkQ2pBy6YMqGXgpipyH2zsOmfZ0VE3dFfqo
ft5HdhSt23eZDFSpE/Vh/AS5pZispo9FjeuSHJMuP8NPQ66Nx2Anj+Hk+y+6KMTiv4/oHpeBGNte
2NM+7qX5JnQp7ke2lZLAduBDTonVJ142eoHN41veuKJlz7CHDkybbII/y8MXwVb+5X88mXw1k7Xo
P1E88ADcKETSbgmqxanfk7KwjTVwYMSO7BX47Nz5cchapbgKnxSidPY2ViMvIinkwDhlwk/3Emr+
s901SEgFLD8hxjGQhgh2Aa1GZ3w0hKZq41rMBWIw5ix7g1MyC/3GJG+1oGYGtnSDx8K798vmmf4v
8HFJSL1pjSNAQKCgUm2i+ljEra/ACx4ciLH3wtdVGT+e5W8TgkRRMsY7KgtYLFqm6e2jd2J3w55/
TAy9qyb2ioSrvG4obhSDCtenF/FksiJXwfUNF6L6uCvOn9k1jTBXmQj28F4095MJSygqEnEu2t2n
dZfksVoE8D+d8EXgEJqv4d5PFq9hCJsghcSDExrkFEW/eMaw+moMJjhJj+3WPHKLpFDY0CryrYCv
5HiyxkMIC2ow8Owvt+NZGgVwksboJyiZWYfRgcprYhF9oMu/apwR1LOZy5EqEgH1KJTxeZ3YZ7O+
JqHt2hp8ZHViZwGyGX/S4ksqVYJIEX8iy2Rt5Mqsv+8mw3MUXawFRQWl4qZNSli62CIMbXY8+Xwf
Gl2IikI5tH6yf5WXuMJUvMwaYUYJJ8DAYjVsAH8RXEjPxZpXaakiLYZYIfSCkZEvmvjiq5O20pCJ
OdxEM8jVL3rvlbMgZOH68AG1TBFhPtulgh+aMh6c4cu2/RZP1q9X/TmV+0n7NM2Yeskn0/KsU/B7
WF+I4C5AKt61TO7EdrZcq380pnuSKX3qsyOwT8CWLckWE8DIG8fSypXwIleeGUsV3737D49i16gd
PmTGmi63gw80064SXfqQC5MtrIWeaJWrFIscbRgaSiIVz+YK0oDJr4EoqhV7V7n4b6Xd2zFzjt2M
3m/9/2yPC40lgg6GWjz9xbnhy1dRHcCnXPcz8ugSKV9nf8mZJVMrhnpszmjuM662XJRg/6sG1vBI
7YTnDTRGeW4fMh46QLgpBNTZKEoSUiRXD23sMZ1SYWeAnKTPMEfDXIn9xB/oJDXcTDMwuIuAeWPD
1T3RkJZeRLaRddMV8/HtsiQva25mY3ihS6hRAV1pznCmeOPPb4Idr8N2XLvwnkAEN5FklaF0s4TT
knVuI+jyz6JvChz9m0HF0kJqpBrhMYPWg7DJcc72NbBOiLjVPiFvpCxEEhHSvU8tVUcQQ3DZSeVu
kTZVchgXndH8B5cRuKdHTlxgMDiZSgegZzYDMyUzfTOOPGBCTYgVDJ5jBwIUliwxZdTvOEtBWjOe
lsYujSB4E6iOu4BvZuHSBQFmruC2L3bMY7C1SwSLkRKWylbMFM5RzYFaI/hVfUfiREzVyJ3ljT/w
hh+GJsNECVodmc6iYFIf9ObahCxUwuSv0h7ajKjoA0N8l6XWcB22S2/flTf8Pq0ZWl0dCM1YJiDQ
LT023UTVwmd7iMroPHpxuQ64MQA87SzyOOD/4dIiZHufFEhuc+UyUSDyeJ3k/WuaJQ8GxyMhH8Mv
zKtFhJUzFlc+RrPWoWJk5petKqD9ttk1wg4rW5fI2k4nNciy6THKUybPs4+LWvlzI45aWBx14jNH
kLTttROXlXXk454+INrrtGCVoEKCSvAqnjbd5/25t7BWy+tECOy2enL3RbL4jgxg5aRnvhG4mF2M
sPqs2e2pctG8LKwbxlDGVxEPNohRoteImSZmB3omNti2ElvR2/geDqpGwh31+4W+b6uzyVhen0kX
YQXeYcw13thAlokEuo0JUMuyas1Df9ekaMotH5UEi8z1dTQqvPwfAt+plp9MessN5AFdzSW7iUbi
h8QYpRotAjhWSydT5h7sleafxnaZOTWLbvOcrk3OEhbMJbMciYeM9VRPqsBSofxRvDknkos8hPlx
AbUyOUc+J7fzXAQ0xqkq7Asg+Fb3YaXZC6udhJPF7QrLm03CwbJpni95DHmHoS1o73Cm9DktSmeA
dh33F4ahSHGMWZJ8LoCSXFLs2/VSCg+5Pu9zhXcpxfPLV9z2aNOwxXy0rhhA4md4S94Roj1bdym9
h5WMv3I9OF+dH3iDETDbI3Y9WmJkXuUlHkmXIyKEsCMJIqEL4elyIjmHdj3Fj3IdOIe/ZVtUdUQp
Z5RHRw/JEp826yVRIJUb9EOXaBZhpOJB2LbjT9Eua5xHxCg/RgjLLrlv8EIf8SGqn/m5q5x9T66a
mRudxva6zZn2mTJkDAQN4jmjuJYxNynZE1wxXfgNJ+UcSrqmTINECKn4Hv89onecjtSg1x0R5t8R
ndaWJfY7CVihAsWHTGG+MlNYrUoALTQvh39sRqka6vA9ewfJU9m3PRB9t+mZ83MZbrrRp01ns1zM
zIaRYk8IZXxvSZQBdbkNVF3sKt6kJXEFjesFY7QWdPhfntLhwF5hLvC0GCd66kIww2+dGEXX31ik
/EChmhat+/B6GrSUL/uGJVv8HQU/IOQ2dOCjt4tpL5qd4g/9Fyzcj/RVTJuVMZwEWmVA7zxmzDT4
V2uE2ocMjM82UIMPD7yR/fTAs/lgyl6/rM+E/3j2xOrPARZdHY+ikEz/T4XDpl4Z9QWxojtqlMqc
DkD+YxkukO10J3dBRtCgkeXSa6XcwXMgc2dLi5/LuraiJFLy7bH46J4ep9LZVRDF2rk9Yt800o9e
9Am1z4Py8AGdQUdk/hW0UWT6/w79/rdZeh7xMUKudmBGdK2XwpGIHOYeV0g9b3taeKuAGnqBbNU9
2atRFrSUe5asWPPMxfPtPToI/R6Bb/zU0LYQoJx/OdL4lRLFmKYAtaS+6Kf90wVi+XHVahu0GmTe
pH64ZCR1L5kxLY3u056spQrkNstja4SJsRZITfdA3FAPXV7Ol+Es/6HU9AJNoVe6NJvon8sJfw7b
uBA4szVxjl6WxORIeGMxdYidp9m7mygUu5eE/k6xwsDkzupBO1QsmkwZf2WINRvpj7AhhsFFIx0S
s1Th0kqgvNazredeeVdE7sPjzKoTlHHEQR/4rh4CtMALL3B0Cg/WxD1jAvk+ac61TQZfOHqKAvXG
yz2kYg2JYm0LzyT3PIfd5TrR49f5YxbpBP9ef37HdzJ45ctQEYrKTxC6hzsS2m+etz54ls+cArOy
GSEVoD9DWOu2Pv2JG5g70cHVyAJjD0iuuxu6LVwPnHOENtxk3MqEMSePuuEQq9v57vx8BDPa9iue
f/4BkQZzoJdh4Fqgel9jUtr/2fnDedzIM2iWFT8HsaE6pp1lIxzEsGfJRBKlASHRuiqqWz2aEkB3
qGBKcHhbxu7LvhqN9gd8mbb3xBhkEAXFQPOZzr1lnu0Mn60SZBINl7+ZXUe6neDqKA/fYFKTzIPS
ZL+2y6CHu9aXsjHVP7qhbm1G0n7STKXumcoossjL0A7OJbjRf4IYLUNOC5K3kKxzkQhpsOYt/LSL
wzvdUQ2/PsVPY7fH9yAh15MZ+D5IXJp9bMwPpNYUyLXv7+tOzAPW2Os+JJ6LSk8mBj5I+j76M3Zj
JjzKBIXvJEJoNPGiG1jdswwuiv7SDgl7SPCllTkf/WMFhsxogsFNJr8Ec0m/AhA2LFnyKy+lY8z/
FarVnkczATXqDnsMoMNoaqYZHmWitZwMVeROhlMOTiuZlgpDsiMrZH6mQQgIRTiEREbSvwVCGnmO
89X/Rb0oSi0WN1rgTXWt9ki1umvnXMY3cjgsAI1XT6Q/ki/Xivz0CknBKy7DD71zRska0QeYd/Cc
tgHr0YdBF/EPxBexxrQLzzO13Yb7JotGPZTzLiGos7o4L+8M3ebM8M3swmASW5ICarSO5YH37xj0
Ch8IxW+SOpNl2e/W5mKBog/wbKESXpAtMWuaGoP5uKR9E3CsjKsPAYFyX38zSlXxwqbb8Ejj6YVu
5z6bIHcAAQI5PIDtHv8Ei9n9JYefZLhLGkRigbTXlXYz/bBWHQVUBSLQbdG2Km51O6qnKq5KOOiX
tJ7pmqG8ziXbYjgo6v9jG3X2k7AbX6GdyYaIOZGA24wp4xkPncf+UkbW29J1jI4D19qz7XrNSdpK
w7n3vDL3nPibDHPWfKkS36DwBwRUfiyaz9uCaoK7Lhcp/5OwW1dyWS3s0LBuHSNRlx2N5LppwhYd
gS6iFrn40S9JvEbk0vTEvRCCP+BM8m1JtHVAqBPnntwAsjRcEO5/bqWiSpHAg2X4x0CHXFFwtHrf
ZJb/ZagCsgW2GEjJ74flTJUXkxExoPXt1Slec3WiYR3VhIfbZpPXHCbWkDn2/YvJFc8O4DLqsOO9
iPVfVzMVSsKu+fmieMD74NwCcA2bu0iy2oFQiTQ0jcxCNgvIrQemm+8NzdPGxJVGX4BASYWaxzuE
1aaZDxbjQZ7iwp9/Qc8ZjzuTk0UtPYIO1ltfEOuLy05K3S6etj3Ps1OKY5JBg8a/zWFdUrJygGyF
zKl+rE5I002gedwzo3UqQGNRiGav36X5SkgAsedelbcJnO0AeaKm8OaK8fDuSHIMlKmyLeC6IfC/
g6MZ0lFHxlQ3LQdRoD11Ao0Gp+qJXeB8QE46QpzdPX9SdJfnEJh0Gkm1GWw7NyncQIAX49G+YE0J
o89AZKfOkd7bk4J3jpycUx4bWH89ObZ77YNFMEKHCxRSgOzyr3d4r2tIEmVZyXZC8dsy+mVsF8tc
bnN5wrz3vvLFS751JQHw+ynMdiO3w8pQMydZMdIE38oNgJ7/4/wEooUAOELhx1KTADKTfPQZNCA+
ha3OVR3D5WDjKlyRlRmHUPbQr98yjlqQ/4nL/xBMalEtYYgGGXKR2aD9kCzyIaahqXyOz8Uasc/R
f0C1pe6E1U1L/WwnBw7ORQ1spdqHKK4Qd/66oQidyxy9sKtfRCzN6ZiLDpsIWBWdoIyeS3uyzfHL
I0KmjGHWfUZ3ZWNysHSTaQ5kSqtkfZ9Az059r5bOLtWG+6ioEHpdjhFPbhiQwxjz6vDajhE0SUwH
c3oJLLjk3uOSYuJpgKT5FhlzuvLCDIvQTbMWRS5/jY9AsBtkDD5XQP2H4KHRVyadchnrxViiOL4i
32+AQfOWGU3y9UWMBH7U38CfWQZmxP0j+Xj12Rd1yPUT77xjVKduDjoR40QGOVncDKLhuuI1rW+w
jUka0A41B8Wz/8nn1UDO0QDUD7Oh5MQuUct4StOD1rj5MFElqUrYdxrOh5IITMMkyN4jSbNS4Lbu
PdFMjspvZEt9DmaxEgLI2E17i/EIsBmIlPkkRNyFVYaAKs5/XdJeRj56zDZI+oYA3WCRHCA6WKYc
dOkERL0KeF/dfpf3h7ZuiamQ30BIRfvHTu0UZULn2u7PDSw5OCM5RG7OM8fKDoCIRKnVXr7JcrKt
ysSAUpbTQhGQ19fmU5PU9hh14B4F66kdCgMBDfCRcilnAAMK+i//5pGbk8nQQzERUjSKrz+FdMlk
nhTXgU/OnO52gcSCZh44hPWCzdJyuryIWJSWuoS3O94jkRht9haAf7v6COXqZ3g3Pr41dNFOkGke
f4XqB3LpvHKuWg4AUGlozLY0yw4gy8wkV5nT6GrRVRl+IoXoM8zHS37O54yN+OX6gxCd5k+JDZoU
wZhUmwNr/BAxZLsyHmzErnw7wahcqB0t5RPIjdqQc0AHEk5FtJWrKbISZB8vEeH3i3kCNy08gLxd
k0xmkcRQiAEC6C82OSgmYoU/O5aGWabDhoumnQXRwulMvzwDPahftGbXuxzBtMfVdvuW4RPkBF6C
+hXoQEvDIVY0+J2tfRDsEN8feFfvLiiNp7sLGhgwcO0qkfbPNIxn2xc7BWANDHO/w3jPVLWzTaXD
YRhQDioQhK0+yh1YUEmvaSVFrPE3Olt6juB5MqWuAAEPUJL+bmn0NhbyV4NFEWWC7gjFntd69Mj/
QvMKljtozsiMAFzXZvXH8hc2otwxn7yeMHFB8x396Gl8VZju7Ujd6sEGbwteQ+Yo55n7fEibaEpH
qydiWZg1WtoVmEzB/c5lP/5FDuwmILubp/3Q2vobWJp6eLbdsX8p+ckcebXQQdKvbIupf6ZyKEQD
7nbnHDE9wI4M9np1PRXgyR2WcOVaJxDyhDlH8N0H+YhDrI9+y8YIp2foAg5ZNHSwNdTewmcLIOjY
+FnFRy/9sJm+BwpPX1mNHgpbW5msozkDrnAEYGgAjT5fgSFWBMLGpDsYM2GTVCJU5GWQ77LFywGc
ntn4MNlF3pIAURmkxQikFrzBVkMU3KRc3XBodU07bsw7NUygdQeKoRML7WUblf3kz11Rtmr/zwOw
udAEp8YY5OouFG5bQoQmgHcGg6B1mJMclTcdnCNG+F3VBIXfrI9VVIXQCNWWEvVgd2Qle7fx3XBC
1zYgqYi2c3r8Db93w+h7QCW5lMKxD03rFT6HxtsztO+BMXJxqV1JIVVCqXST48CgipDI7YmfuzS3
ttrpWEZdP1LXYNpnUCL5jkqBY2mGkUgyMN1J3OphPPyzl3niBzNApc/16LiD3mlSZLzfiu1xwwT5
M49UEK20fGbvqB7AIwBWhzj1IggJqe3cdjiMrmSGPcVk94D5IYKPPBzJYxwOczNBoEpiuzl8lArD
vgXvVHkJV7IGBEsut7+m1+AqEMD5xvRFG6IC8vanSJUvzXzf80ezY2g7e8Wf1u6rfCsKP4hJp2kg
TbTnp6c75dKZNJ+Mbck3zyw9YqjgA9bBTChVMfA5WLK6a0fI8ATbxl69aRfGYhoHrNpyHM8zQAGe
FvKe3eZ2kq0ivMe+gkQa6y5b1ppHQLrwpHO18nYCBr5AJwv0ZDhnLKicfJ/w2IBSF3cU5YCiduG+
m4eRlLI1PtNa6AoeiGKV0AugHkBGYfN5vUCP7ndzv9N6GM5ofRiJBsiVuY0g0lucxRups4LGu+1/
mLWxBtQOu5vUAghudQ+4T2YhjUefCwwcoMRjZixbtpQwU2aCeHnV16gZ6u+NE7cPPswqZUOEh1sS
BQuBIZcbSJXkmp3lEacWwL112jPeDY/XzgIVJjCV9OgXg7Sol1UgaG4FZMZy5BLKdVs2aZnOSuM1
a6bRSML1HQu0Q66gVHYg/u1zkVNZ/iehNMxnuaf+5ER2Jr3AviYgP5Fpv+wtGTbtzgNmOa1iyAS0
GfwL1rjKooXJSbl4upjAvJ6LYOLKuSZ2j3mh+wEI6IEu0rq+FhZhMYEslV1pBp+cteJzraSkVawd
9cUiONWb4se+WWZcL+AnHk+tkvBQgnBqBukRKW1O58wI/NGFoUwXM43RQmnUHwODjEUJxZBgcOfA
FO6Y5geOz3GIRwHe79IHmrWbhymDR4xWyn9Nku02pM69l5wIuO55UOVYdGVHwJWdsD1FTMcRAZRh
a/pX63asPuD2H4jZWCxLtGTYLPOFaVpnK+E0MJmbem3as9kP+2vQTumTT0iOMivo65zUlE/2zSUb
cqvJJ2zFVykMB0HJlcFnkHpc0H2TwMCZb0aJayisDRT92WfKdtNewVbc9LELhADSPUJggeKtycrA
BW/wIOhowj1Ia62svrDFkqQwRSQplcMFNmCDM38vXjl3DVgDPrJDwa/9obIst27Pcqx08+Vk3ZBT
dOwin+4b+q2afwD4G7wX0xjkuYWgvcN0f1otEd0tRh1z3YdyLOo+axxyZ1LpT7GfoVBeMvp5OG58
H10ff1vNllvked2Zjcsyd/TN0KWAmeqtNvtaPohW/5qVMwxRTp0KVFBouw4QjxgEALKBzvDt/HJ1
OdmObaNBjeXhSGrDqxzN2BaM8OuHNHP5foTXwCjWiOxaXKqqOz97hxn1JbKRirjwR9UR7bVVnVRv
PyuNJBSmP+Vm2e9vrbyFX/OsTYGrUHC6P9sDT7OBnFPizMfK4xhIlqBtuPIK9pQV024hG16H53rq
v2xZ2r65LcdWn2RMdGUY9W3gkPZtbzbw9tsyTwbXNqoBXVuqKeE/ZNRUaEcI+1j4Nn05Aib7XXik
/F1el5hvwCj7wgMgmQTaMuQoHjWnulChr9B/0Y69TywQijBU4bh/exRevg4cyqOf4D5qz91oqg5P
TjqMGRSGYx5p6sk6anlfWnGuf8Zul7lvhTtRrkBzhUuB/C/AQM/iCQHchtyTexPcrBFR77QEXYQg
CNHH5jFzGerbY9vSz9WZ8jPDHP14bVfQTgnhT7pl2BokGNvCC77TgmxNgL9vWXW1S8NofxydIsyR
RyFZkCSm+GYo/QD0Z3XuPk2LmEB8CwoWIRg9L4+fEPPwmuik8fWy5a/QF0xmMC1CJn4+SxUVTPVr
4nrmVO2OrbdY2stw6OLBdw596CKRzCugV/L5PnXU/KTM72KzG03XhfJAzCebmT3v7wckfzE+6jSk
Qy7+7qwhVLNKtYmXl6LWChucors1eOxklI9jHe43HzV6ifAz2hI5xAFj0ggMHkpWsBWttJeCNhsf
r03eG4SYf0r6jqz5W9DFv6MtWFVE8PkNMyDaXYZt3R9XsEzJJu5TSFhjEOLezSJL/2M57lKp1ROv
zPdUQnDV3KyvLb3QB/dlxQPEeJw35yKXPHTMPIU6Ait6gvjz7V3baiorkOetXSXN61XwayYFRrJt
8kkqFGybaOCXxgIGvBMr670kXc+o3sm94W3JBqh7eeJbG2N/NDfqQyqcnexPmDP0W4b40H9JyBKq
0h8az8dGHGD2EKEzmNkBBxHYRCToQC5Fv8oXgUVPFOlxObhnmHzqLr7ZTlVxEMskeL+cjbIex6NV
pnzpZnxddMCkrPmifojvnJJlsIqLsuI+hDsTmmZz4aqv4NWrUyYiPZsbr7xrLOQvwlScdP7rvqFM
OwjHKJeZpN3vV8xe8Ao7nEim0XjS8px1RVrx3ywMTLwHJX7RggjyorohMBvuz2XR9YpDPZMJodnE
jotAXYg2Jx4/+IqTKrp4aJeWMkJdST/lAdx+nzOgBWx7f/TxmPgXkYdqeGja7/7DsBb9tLRuM1Me
WgJ7ytcO4a5NGFmtzoF95+4NeTf6j3LR14FADKZPa+Xpbe+hSzLcbcSV9g3RYPPrqG4zGa1CB4lw
3R+tmfMzwpaxwpLCFxSILjgEeGAkiLDxamU/09LwxOPHhLPrXubgtA88tgUtNTWxenhdt06IqT1p
WwMgv61KihXbwb6GfGqcPQgkpym1j8Rlv871aFu0vJjqvtPAlK9tpu9wEYTdFYyHPpCvSo7iF4Ml
XXNa2Aqh66EXAL/hAxkWaQ1NEO0M3gZey1LAnRMYB6zuSeH17gyVoqwKEuZdFNF5kX9qISceZONf
f9Iy4bZgmG/g823/B/VaG+G4cHgvKpVcRCdtMrUx0t7fUpMXwQtEAoIjO68RcZkXQP9cRZ1dm6zI
1//Psnn++qYiP943xajekqzApvI+c3AkZRaYKVaIfyZSayk9xA3l+FQGYSscZDoY3/a6lBhxE4kG
+7EDN1x7KQ6GDPr72q1tOlXk1FO6N0yrokHjEDg3Z6NufvSnZe/Erv17/jiteg99uXPM+S8xC83a
1TYZuWeryF9EZGo+Vf3zHiMQsCgl9ZlTBPWz+s6FKxPGxV3YO66Vxd3Ccdi8rwIFq0N5SvRA/2Vt
Fu4JzQiffoxU99NydAyrqKb7eiyd7Xhl6miT/7tksCUloIUTaS/HTpxqt9RR/Uzw6BbQpxPzd4dD
vaO2CnRWSqi+oh9mFCtuobsQ/hh2wMZoRT/kwV5KtK7kfpkI78WmDr9pZybCIrVbQ7GQX8qo7CbJ
nFSsXRTAHygr333/fgum0NPpFUBt2CAUEOWaglFj8re1fIl9alGRmtcXJlvQre1iupTeTFM/5cYW
NY9RVQtqmqBD6fT0JaYemCIGaVrKVhNZK4C+RPF4yHUkWxEZpk1RGnMrfDP07WEBwofSTS8zLg4H
yKMQgoRKVMMrAygLNkJ4tZ/CHq2e777CU0+AEXIo8x2Dri1wdcKq8Psd37rmbRlgeBruoi9wwCNs
Glsr1WY7g6npICH7bLvjt3bWxFgLdtD+m0BJAwejARWSRq9q9nUeA/B4UMDTe9opE753nN4LzHNo
6iwi8ddznNUesCjPCHZGX+51AhlUN8QrwN7dX0mLZBuIN4UY6DOwNW6/jnnQS3GIN4p3LXLeylHT
HYI4lVVntU1/qSU41+JL9GiwV2UR5mU5FcCDrCQXi0MUuAT9uMmfsqBZpKBo/JS52QG2n0KRjWjw
YB0o1QsxzW6iOLYUxdTXrQg9d2pX0n1RX1NGVwXArZhaK4p8Wu5hSeyhqRMb4LD4B34OUpzeEHKS
XeBqEgGg2vx/taYA8o0bYJjQpBHZ+F3+ipnFlR+9pAC8O1ImyktlKF6Ryg0DFbKhBW3nRkSzufY+
EULv8ZyUj5LVvLFO0YvSaFVclXwcbSwG0EIPIVdce/ibUg/ii+s30dFkZb/nAc6OkqSIvpAiggQ/
kFkFmgh5Tp8fyQB9fUDm2mcQKxS9IZjZu/uHtG/w4JN3s/84x+QenE8U8nPpFR5g+LnED6yjTNHB
ued9I0caZCcJVA9yPlaKnzrW60ipH/TfwQTYjZuZjCjzRUrFejFUqQNJstelBUj36+5/OUP5RX+R
7Bo5iXE20OLwX+dI3xodrKv3NV1nZ65hDvSns9LaQH7eEB2XoQeJ2f9r+sbjB7BvGdzjyhA42K23
oXyXe+tzv9JpDwWZJhyT49keJcyDkC4LguC3lmXc32LbC2yUn+hefs60F8K7RsL8M2hVDoHSv/oA
E9Q115bJMr4u0rlkjdl7FR3zxX+rv91HrvJE7YovKf33sXGKwTyiqnViXJYVfXCYESjpmecAtxPa
0xdRnHZQDiP8c7yja9Dsu3aJaJEOaBXbLVsRmk1dyLpf7gtLonKtUuTsK7EpCdoaIvC4CSZyJSvH
t7aX2sxAREfT2lCWPqAM8WppVO+wLJzvA4oRL1I4RwoFNvQnU/P6y46aO+85xCjVU2msWipwcWtw
FdSvWh+fsOTlCWOEpM+BXUWPL3XIWgi/QcCVq9M83JJZHHJGCv2w9lIj6WkBNdTCUHrtJFGh+dVC
PtdDw8RgILidwf8ezacpNxO31ys8k0jOz9e5xYSPC32ftLVDW/1JlNDxbZssZuPGjHS9s8l+2l45
sYwD7hs3EMxkQzZeyeW2xiY1K8B0QrJWZNq4y3E9oqVHEQxDV9GS+LSrtjViCb3J5mq6Nt6EiwI1
OriiJe0ooAYG7JjKNBBS4iOwEY8NAZJDiy0AXh9LKhP57+NIyQiOYfwkBfsAevIEkzngGdGTsFyp
ekoDpZjfZseSzlwO45sBMZm1G0pLtpSwy2MO0viLm9TNUSZXhlacPn/Z5B9tevrNOZr9JuaNTERe
uXIoAYaWrBfAiMjeNh78BnEJtTxaEs43rsWQaaekKBgIoMPY6cO7nDML3bKRv9s8xmJ1D0JC2GIH
baX4/sX/B/wXpiId7k6rkIQuuYw/DVjVlqvgszLrv1YGG5yqQdwKxbm7a61w2W57VhbroM6tk3FT
zRZw39otCH8RlDZTDpqc5CLuWU09UMYML+eWPdff/flODOWrbArX2shav94HjH9O0ERkjnCmPrzW
20UEM05MnCjV4N1CmVY8d9hPaheIFsrlw1W3mIKg0rL0kvpvokjT4fL5/lW2G8uGJoJW5mp4ZLrJ
aPyZx+9HPGkgwzAXEZapPP4qmUGo0mh+eqbn70B3MnxlUKvhdMAEuaCPT7PBCxiWEJ9oSe6RkqBE
pN9Wpz+zmpb0UtI0vggTr0PVkCHIHd7+6t4C/S1fLC4uvj6DzS2pJIF4NlxhlxHptM8njbCFAFks
mjhncle2VFEcuAhEXqulli7bbx5GrJki+0x6HN3MV+domFFJxwcKS6GQ+Pzq7F4HbRU1MFmcJCrD
WIzNY6oYsrlvi2SR0MNjs6DiOhZdfB0i1r9hGUZ2GPaGMSx3pC07Je1dAv/idg2mC7ioLt5IaTHQ
P1AUarQ0tBKKgT61s3Bt4+4n4viEbc1yI96YprjEgByPVz7qMExmjxfd3fYqhQ6N5Xcdixp4MRAh
AXeneEx/jVizAwjPT6SVNug9OVCVzOagEKYfujmnRHtje5qybBnyK/V97Za8C4rbvTG4ySTKi7fU
+TT6xyfxoNpM2RkoTEHNXUcfbEWaz4tl79RrpWFNSGHKJ9ljZIAaNFiQO35EGz3qV6GMQXBJ2izw
zAS/t2Hp6B9XWlG837yp2DIvi+SXxNtFWYumdTGtQoGwnynhaelnAWIHcJ64XiOxhJyZOpZ7qxe5
7N9R5OUqIe49sMNTpWRD75hYNwBHQaEZsJBg38JZOgLLFU0NmHLX6YVXWEi3DTeTjxr0UwTBEDNC
AmVFRdF4Y62pTtFGSulzQu7ssr0nofKUr4vV++PfnM3M/4ksY6Ug4f6BKlIbKkZVNxu43VDY3X1g
r3hknE8S3QPoI0Fait4+Xsfc15o+YT8Uncq0VR0XnNehxWJ86ILv5VFvopvsIXpy+F2Wh62xZSNh
2N8MPlTZPJgLh3E0xxEwWB3sWfrp9mRd3Ao3wnYsOi4i6fgJQLHYCGte3Or8IYtAcLlxrTIY2u++
jFTzCqbJxNx9IFPvoZ5cGku7GRFl7uHQUqzPL5ChV+5Dvr/yo1hx/72C/2uHPhqls9bGpohd/U9r
Q58UiNfS30vAwPVasAUrVkC1dmlc8O6HBJ8lwtrL2zXYUIbbmDaGlTe1qUGmiLYGfQmN15ynyHSA
yKfJqcd+QpJ+opblEq4en4k/kxtHHZiqP1LgkPUrvarJRyAWXzgNst4hKZWG1h1+Su6HlxbdlRuK
MOUDZJYOEjCO1SNhB80cDJRDdHonDwmVGiCdj6qjTlWFxjcY8i5kS9bdsNNu04k8SJW/BvrhRvjb
EK0e7NqylsSqVUC9cvEbLxXsUlt72PM1zXQMyg0mgBK4TNTQwgT+qDhEz7uPxN7B4d5r+dqg3Mmg
y/iQK4xfWrj0PeIRDxOcTdupea8YIM1b7HxwQfAJ9LePEA+JjNFWbiDjVZUvZiy7PAM2OvoJ8FFx
4z+WIZtbcyAJuIfUqJtbnjd1nNY+lVgEgQopHpK0wKByf8yKC/5yLMckVqu9+qhOKWhspkDAFSEy
ZtwhP1slelzKEHEGEo3RtHjZG+8NaAQmiw1kDFhlaCqtz7aMKKC68oint9U9FoGIJkXxyxqjtB2V
rHKzvIUUrA2a/XmerGTqdmRyRoWc9Nnj8p3z7qFpUURSzCSYWAXJwYWw2YJfqnlIlfSmchOUmjux
AG6+0FPdOyilFQkLe4Rj7trSwGDsnI6WVQJyg/8MM4VkE2NCWrHl1I9NryjAAz/nYApYEG0IDT3G
Bv05kQea377n/9F+Q5Pn6Qj6uPG3hSvXk34VWl/NpJ/kPq/644Ed9jPASndrsD9YfkYUyu0ycFhF
9RKbewPVryj/9pvGNNxCnkVhppRfoYlQJVdmoW380rK7/59Y2aSq+0F5GdE8l2Wd27TxQYxDjb+G
CyXXTqxBYMW8dXqglk3R+iIP9Pt/m3hC7JbaVkzEWPlLBaWpTTOnKvZNk/+JTlqcIgmi1oJ2Lgf3
L/Hd8l1zzudxxwCU9EmGwfn4zHpZCNX9/WWR1+Ke4pTIOFIvNS/yz2KDemwEzcPzndyNAqMxP+fN
ami3Y9lI2cI6rriIor7Uf54eemvWNFrE1mambxdhHOkfVIx8cUbWDhqZWa5fhFncCSIEhYMRwADa
I9aBm6BFjSBLXRoavrn8bb0vpAlfwUYnRIU3UpZn1HUtHc4HqOe1LWKr+LnLgr97pshEx83QdWdq
ihFrcbaa5ik904B5M9fPuEjyx+KBk4g3toIO2f5U2b3LBng1UigrrwxgY5g9xYsk/mwsop8hr3gK
eq37F1SZHk9Um8IE0lfL+fK3Qz22JOUBpNxR6N/kJCBjqeQIp6OoAl5iMaOhv0Sk/y5gSEFvw90w
8AIX4nAm2A83ie1Uh3174mAdvnawBUWmHnSwBkYZlOtpU3BiOXVilhCxVmVm/SRdstFZ5pdCARFj
hsnf7ihV0yG/VFTQcezPTeYC/AgFegvuYLdWlPyAXfVZl7D55pf2ri7pFpBUvJoQIGaVe2En6MWD
8QLLUz1p3TE9jj3b406cHW1aboSN59cFKiw9s4efU6UVtiCsfGpLroFS+F/yBSYcnJP8FiTJyR5T
Mvxa/4kv/7EpFLxmlU8fL+tcOMd0txed9zBtu1bJmGYSdKQ89dmaWSI1uUWhc+I/lovRuwGvubis
sq9/HsfR2T9gwozf+48UK/YafYVbjscWyK7I7C2/+LuS4CFjppshtkqmHoiMiw2xePjFra4+OiPA
3uhwIB+M6jKYFrTqc55JTcTYoId9X3ZhqfQUpsKXVbM1TocuLyzEO14L1XeiHhaO+fhic6LWUuQy
kAJt8eaEVAQZdDG9BLPedFZG0ldFdmCyUyxpm8bYPcrEqziviU3AsgVFpU7vOXzvzckxOqhRhr9T
cKsghyukUCWJpUzr1A3Pke6n+wkG6gZYvBwEXVjRsK98T8hRiJnYwkKmKUlaS1z7qkkmJDqeriJ9
GwOJqFdbd30RdJVITIRmhSQGK+H7yD0DYmxyK4De8xlq2DWcKrMIc33m9XKlIcAizsZABNcxvhL4
U8G9+fPzmwKk8bYgeSbt11eq9d2ifPgBRRpgNCV8HhC3Dug5EXtIkf5zX8DFh7RqvvlY3rK1O2Mg
Reo/fmZ680Wu/dsNG0lSkAo6k1R6ISQiip90oDN2qI8NQPIJRRtfTkakSBvDsW1lvzRmYghuRX+Q
UfdSzKuqKsySxyLJdx/4/iuBNNTP/3RcIT4Ft9I0Zz2ACtLAH9oFEWtsJR2mrBFF2grTLXLgerLE
lPTNXMIytxWckrC83WZyHm8DuK+48YmRBdPTsIxkj0HCjEfq6a5y652bNLwHPssUW8UVs0vUbpv7
4ihL3KJDsYgUcwhstLkjT9xoaXFNlS3/rLT8A40kUk89Gaq6Xsi8SAIieIcwQ7tS0YZI5NnMcQwQ
woVwVtC0pPpuinnee0OHihKqIq2OtzVeMIHgxCOaS7SntBP9DY21hzI/tyjyusZ2YSu8sIQA9xeG
iqbhRo1uRg4t2lGAD7WxUqwHfBKXWfGmx8C10mg3HVHZl5GiadbyTM4dZZJ2j8uCx1UcWmAO0xzt
i87kUG+R/Nwzcx0OfaZOfa4GRXNL6UT4oI30O5M0ob6DGA4lPE/VMtWp9Cz7ax3EkoITd6UI04fn
VHEIbDjoum9mNEGx97e6oPmCfpgyL1ie/I0n5TK/H1+9JXnO3hC346zwIjXIoBDR+FbsBtHJoJuY
D31lp/iVFdtCqBXLDrcW3AAOt4pFn/BixwoDF2Wcxqr7zCBdAYUPVC+e2py8lmkVWXLvJVTIjR6t
Jy+tBtiBNXhvDZOkCApaFydwxKRg9gYOZqH4R9ZaUM8ye6LAQ4Ucg3RibZmnYYdF5j2hVK6/f5oL
G1i1bIeAvEvzSIxZ1uyFTxjsWLT2HkluH87t70I7srhcpN2XCvq9WlicbY+wE2a2kdPkD3waQdOU
dxyJzJqJUVwF8OvLZqT74Hr1DQ420X7zjvf+S6Kh5ZRur3hBZjr3mI3JS1p5lAtR7mrhyivYagBp
4rpgwLwRZ9ZX1FmRufzNxdFu3lkI9QFQ6q5MbdO2MpZQ7FsJ4Z/rnf1nXkWwKqPIjsilgo5KQ9q5
muv/kLtxyPBzGu0Nznz1aKn7amzSI+nBRr9uIHyapfIzegwwtk7p7cCzquLmHSF8yCV3vA9LmdY1
0ML9c/XbgUTyVcUFt9J3A6NOg0U71Py9/JxTlaKghHVmjmS+NlpxnGu68jgvIox8D0eCXwHjytmf
emaSjvGk987voECDdpfNira6VTK/Ug0cqZTnYBMQLPybfTrklzUdasCCtSx4mAt0+/wmdKJQc5F0
KaPU9CWS/jDUsfwX1IUvfcYiJC/lth5/dx5jhw29XuOU9QW9KLsp0hQKJi4+oghMa5p8ue4HDrRy
1zCTzDDMAQ/pGDDoSpGKsK2jpCPG5C+VoHXuNuQ9nS/CT3Tirf75xGwYpycFW4evT1AjLLLWd9+l
ApB1fkUp0U2KNsE6FR5zLOG+p76e86aB5wQAE06HTr12GRctBV/vjM6FNCkBPEr2y5xqHGidoUKH
KvZEwPuuGJwQavuQ4jwcRGIDEyyNMahM+sYAo3Flb9l0s4MIe6NV+6mPcvoPl57EhDVxd+ltpDjf
sMnPx/8LeN8r4d+3Bkw5rn68xr6i9JRgDd6Ajoftv5TwTggWdr8D5+4l+j70PJbDmM8SrS+SOWbF
wcBf71ckhqwfPa2X1YP8zVg+0LKOR3sc5Fu4lBOFF5RgieilZRVGrXCDVdWDy11fnI1hUa0MX74E
7oBswwC4IgKy/IIfjhfm5tPKMjwpnOqJYlm5Naj4QXN16BvVAFiY3nTETg2Tva3Clz2oWRJ437Qw
AKhUSFSQC4SVE8TNvGZn8dLO7Hi5MRgdOzhBINN2lkYh8yG8toNT/cCcC+D/44yMvvJnjv3UwBtK
ji9NjoIG4u4TnwfbgKS5Cz4KbHcJrQY1EvFVV3FZOjbbANtqWHisbGsCvzaPOB/MAnmMPAr0vzfW
RrOzcnI5UYjnTcFqdX6JZ2gYC2FU5NHM1K057hJLF9qbLgDsr6tcMBBxWeTzvKRPsd+UpwfZHk+w
e/8JKdJW1WVabLzD//Z8gp6oWUVRJWMXZBNshzH77sXFotgsmE7pU0Y0etwvggK/je6M8prGq+Jr
fkxoCZRRFRj+6gTMIRs3tv23ZT6/AczEj53AwZNr4VlQjm8Nwb4xMCY9wid9ao91EvJ66I4byMgD
graRSCKr75d7XVVhnXnFpseD8hABekwKMbkVIheOf2ah2JDr34g280hmfnTOuYr7tBhNQBfnrXVP
i5WWovFbGNFJLYwjuJi+LYYCeZQDW0idQ2Fnd/7xcfyWaOnE1cc2xk0UVS7UO7cz7TV+5+Ob5bnT
fIIULFP+PLtqUfzVLf0oYnBBidQK5lRtnByDWg+TbATjtUVEr8lTLiDZBWJynmJj7SC0/57AdvHf
u2L7EGUG/qtWAiWV2RGbX6Kk0VOFqrvBt7rF/SyRptExiLkeXgim9UI/QV4mqkZfG+G3wxodVwb2
dewmKHurHpAnH2x1QSRljZlN/oH4bPXlNGWWOj11A4QS3hMKU2zBmL3Hnhj9n2TX08aZAC5sJkqv
rN7/u560jE1Xmi9OGhVyBZflECzIkWf7epa9HY9pMtk5vP78Xqw4JyCjFsdaQexwipad4yOuKQXE
DXl77qmkiZ3fziqoFCXFxJdgJDFiaNOfqbtebA26grUiRVlAR5LCrxzQFxaoPQvs6ED8rrMjjDKU
yTxnTiQ+P8h2Nw0MvPwkCWE1B4kHf5NvfpYqddEmBgROSyLrR5W1BCxcKuua7rHX7jQh/nEnlmXs
geI4UnBoPfGz6TmOJWT4eWzn1Vx91GNbCxqJoTvOMAsPLJpiWbX35WhSU+i238gjAnaqyJd4r75W
gOQXIRryKPWnHNieP4a6QszuiqFhWGJ1bz4HCUuyZfEg6zX/fOtB2MoycSXBSryTtZW6Sel+KBEN
zoKTelX5kFp74UYNSYXgyad9VKF4XSfbrbcUkMsuE7Dz1ggrHCNOF6VaRMAfduuM6yQmk87RVw1C
e0X+wm4vUhWI8rUHGduYFbD8l5Q8eUDmeVxLZHNgiNR/ZNaZBjdvvcA73nYQDXw8UMNeZvCEYk+v
+MX9wMDR4IeNoyXzHKhF1uGgoV3cqf3K2kI8vpPtfBTL4imZ74jzvhYpqMLZcDmSCwDBxq11vh3t
CZcf9WoL5y62Bg5qZKQkuVX01hmV7bPg9PhAnKxh3NgpwRVNMu8+zNRpXlm0DBe+6v0Rk32SY2x9
gpkWAN79CMeK0CnxxRkb+mt1OOCQe05hUdXxTVAInGjc0Fq4NA5VBHWZb4VaW0010ZuIjZ0XP5vv
6Qe4ydaHqCYNPi0vAyk/LTO8b5B579CRI7cteQIsNUaF0ZKEfpa/+uazq9wOqq/8qNV90w6q51ac
mEPZtlFiBRqejlMPted/k1hMgZ1TuU1gvqISW2KhUaNjSp1zM1qtaDKrQ1lzLhUW1lr63ecqnhEK
/xuSSNsq15W/kgj1icVgQN5P6GX46aG2SCTKEP/3FI3SZqua5BvbjNY2S1i9d/yaJ0yoNcd24Gba
fOYmQIQKVr3wo+r5nZ5EY79pzubx8kdv4p0EXsTLIlwkURRD1SlsLcAtR+1luqVDUniTTqk7AuZ0
S4304fQJ13C85VZDPZYylHRu1HryydsJVElPPilJDxyVde4LG7A09O8lqteW1NEQFF7Mog1db/D4
k7vHZve7RJRlsoMmuZogQzrHInBGByef3gD8Tm1DBbe256YYpqxE+2SLDRsuNBHCqGA6t1fAQLAH
puiL4KkBFrkL0iZOTYpmoO1/G7Hn+RK0YSa+HI1prS76w/v+aOWTAXdq3ea0RAKE8QTELpWW3QkE
nq+6NXn/MTsOz3pFP/VeD4arUbXf6EMLpzPGycmJLz46TXxyG/2csoCJqSHeMSQ9fG/10Ny9pjQT
oHHPNFqyEjXsRXRkLqQ78DiivEHBr4LPxA4zm8aQpq0nDHXDUBKmEcVKoVcj/Lhm5/sy6uiI/kiv
QvfNGCKgkCf58baUVEojv8koQBfOdKI4XEfiyXjLr1gUkHCLMF9ty7CumWFCvBrsf9uE1gOfTKmd
E5YGXLjCwtpr2j5+omG1EMQ4zaq+O+FiIhNM0t8A45+wrx/bQT+mFG/svME4JgBb1879UEwJC978
6QMPdBaLChnDd80JhbUhcj/Wb2zifg9NghMuq+Cnl+hlHfNJUEvZg+wYXHj/u08Vv6cH4/3Od8Cp
pRqlzhbcsZv6hyyR4QJc+9rXkk9Erm2CuYVZrQI4W0JmaoofWL6Fmp/3QyfuGZxCbs88XipW/tZa
Pf7iW3gGqwsXj+fBK3Y/iBay3owWv4PgeMsh9MM3LgGZVxnUbTK3XxLmljUMCBSGKhq9ekZldmEV
eyPearTxNgsnlKtaRE34oR/NG46Fvh63PSvDyVf6pVW/QzO1/yXvLHrKL0onIdxpsyAhCcCaJdKI
AkfSZbVfPkqUmrYxq+MMuikahH742Jla6Vgzj0H7vkWD30IHTMcyDdGanMGFtQlOLJ7thdIkcSda
OXUKmMcupe9KR1YO0YVDenQIS7aj6c/U9QJHrybmauVSgb1uyOVlJTfSxqFeBgKyxrZTgs92iJkB
yyPgDo2fqCqPvyvlPTFA0IbUrE1bkADxEto3NyvuX9nVzRBc5bkIqzYxoyjlRfCQ/4WVwK+wf1uJ
iIdSxFaIqBPxJTMGIYw6P47D6FDXnArZZ9SKOQB8UufAi2qaPVkZcRD18RC3RfOIOQZJ++6gn4Y2
9aUfe7yX5MhXbnYbXbjN8qo70dc3kI2/FdEJbyvebVk1D3tdg7j/Lvc7qixWyruIoyj60ZyuE8w3
IJTBAB1n9mExiB3q34vRvbAWYjy+LdOzIKEkUpLt2RYr7+T6w37FuU2K+ZQjX2VhObaoCug9DT5A
4IOD/DT1RzRYzyGK6NKTZ5KmbxCYzvFYnEjBgL9Y5muB3pcxQnaqD6tDd1wIyTy0ehtmli8UR0gB
z3F1veheNYaSyB4/PFBLiib5PMFK8bm2KJYSPUeRpm5lPyyEU2+VhPvb9x6YOcC+lXH9v3Amx2dL
cAErYAkUwhCN6ccAIUJ9aB3zBKZ9Hp6FSqm5+LUnkxt+j0t9oh3TWEdfiSHhI8u2oihm5xCCAzMX
JdYbvS9Poy2Z5LhvhJWkeNzj8fqnLNNyWlBxknxudxGHvLWCLc6Sh+sFRCisVbdDsj+q8bUgzZw+
z6fvIxleSKkv69F+Mpjwa2vTOAxr7jrRwgQIl2UooLA9av4DbrcswJ0iRw+Kkjzc5a3nOXxwBReX
jqZ2WDO22KOsxRwFY90yrMprgPhbHk2XRBORY3V0BT6V/ayJf6XUUVfiLfvgaSPKKdXOMAtaAYvn
WvQ7qYqPoJL2z6HIg8apc0orOFhBOYiz89PuQ5e8KsRoCOier3Ids3T9A6AI2y0XaHfY41XhlkGF
zSN8aA2kaUjnWvA17VpXouq7EiwwAO5pQBaI5c8HMsiICV/FDdP8yJ/ryu8aWRK2mD++s1Jyqduf
1MQGBlCzYPFkdGFX/gE1F2y/XO/U4FPAhbaw9h+jj3zivarjThY1a6FY8myEIOd38otVt1OsIcBn
e4+fiYuDSD3IkArtZMOd0cj9k+fOCB5FnrmLxwn/J41TKXdq2sYXt16hGDCgIzMXlq0/ByyvPe4L
R1ywt+CgznlIWfdPH+dKGVWTdN7qlJYvhcuOxFc5kCCERTJsOHJRWZRyaGh2fOqdtc7v/VXGkrYU
uBa73GyLiJPz+C+IIPqypbiczVBoWsSQxSnMXfziEWdPOSSmFFON/+DxoDszPiHmr6JMJLe7yEp3
OSXRbqLil+Zmugs+wxUasp3VNijcJLAqzQQc9+A0mIIoxXi/3RVqsSg3wqdGCuxxx5YXWQtdSZ+x
QIO+MWEByOT59K52gPQKky6S3kPGtmBlyOY43uQV0ArB4x0YN7uBkjNhW532qOARo0FwM8lCp3MY
NTZ5goPpam9nYPImlGy1K6aU5Z07PxDSl9Vo7E/j+o2ei13YTfbWmMnLGcn22fdT+nBCs2b9ssZR
NA4QufAMvSz+x7IxilRASpEW0lPg+Sga2lb+iq3IctKKOuLo2vXBk2OG6TlU1aTesU2ccQ3ZEDNu
06nqk0+BrUQsfNwBdHwJPaZuurr1ICMtDPkoQvwdYWok9gjV0u4aeiuWjjWJWKC8396T9MXZtTTv
aMpZ4RqI0Wk8LPN6P2h6xqXzD68m53AHWvHPZKM+EzZPv9L31QMtRWvHeNhtuFMi2Pc41jludKpc
qbHvDdVsZkBIM0NRyOq6qsKMuDZvTnvawAhq7Og4mo/gtXk8rgzqj8QwoQdQqCTWSosKs+EXmT6l
rfrj/u62iZNgKMazJEowX/cYmXJhtQyXVyaC13CVlCKWeSRUJd/8LfN84vkYJ8CLkXCM4tcbEq3U
0mKNBvXzEXjsmJYX9KhaC+m2/hHpCuvm380jVCxUZuFTsOiB8G8f3YXa267/ZRWED165dYsFYdew
q/XbzmGqWoXtbbtfRbZ2zKEqNcCpyT/62Q2GKdhPSuRNpPeUXy3DonZ+DOoyhpZDRtNrBK5QNI/v
UQPUO+v3i5BxDiaEngbgKm5VbbPtt100IwBL0QG/LPKlpBLJxrb0JbsygJFM2nUVAZhIOufPJSr4
GHz71vIAyug89F/fwudIbJy+1xp4nnOduGbiWbXsnm1ZrPLaz4Q6NH8B72vu/tPWz0b0gPXVywJr
MyCExTrlDI9xBTbHCIvU87efu+PfrF+bXQlXUrO6s56T3+8M3A4fM593/Lv/c6UIRCZpCsdYfQqk
3+3ivJXous7zB0bC2O0iXO4vUnxhsBeD6s1Z2BnRa1tIGK17wu8Dz7aYiKRgaPiDYzyZIFfuE7a7
w7jjbGesAUOvVUcj5Dnv9w1I+BFSpa70b5f4vQdzhSmC+W6xuHgddPq0tUZAmEZgkAHqbsksQtuM
KN/jSvYwm+QwfLvsuDvh6G3kCpUhUpcxQQyw3tCDFI+zdyeZmu4dI5E8y5bSW2uV0fVJUWhBq9jI
pX1KUhRzhYQ0j0rWwN8XHyQ4bAY0JUs9sPnnRv9uAd8IJwAYbS/wq94UejhUdBE6gaBdZXixbqyK
/fsBchwuqjQuNVZMO/sv0YYEeIRR2PunRdUJNWJTT34zWAXGP3WP/jONUftKn8M5Hijf6KUd1KOi
lRPrDXetaDqzzod2vbAPngz2mJ6bgqwmX5FGiQRk8LHitrmz9OOMEsldvaPRqC+huTkrkhzjMK0D
l0zeZoAM0V0OKBTOav6u0Zzt1pGeM7qenT1vR0M1RBAhOwan8Zv5Fn+OLjTaybAYny1XHD7qJ+8C
einCUUNPMp3i+Z2e+WMcdLVtQu+h/OUaH4d55ltR4hmC06cOPoptSS448VJoZtybfh89VmIRf/Wo
MFnYVPX09M+oQSx4IjiIBc2sWCpiPHRdyPxir8lWow6yd6OFCrdckUocPTK2CsXTEL6PtgdgcQHm
kHW7Ed/f0TFiZ4Rr1mmHkUYzy6PyO4ojXf6vsY/ugF4MmhBHg99tnAq4vm9Vziz/+u8oSMNxEGp4
T00hbX8tEW756UR8QUCvFqGEV1MEGLcmV6bsDJx6KPVkAKE3Y5IJVEoKEeeUgjcG8oi+jyfIS3b8
Fdt8VbtRuKQAE0NR6TTSMvAqAbPKBjd+WtAr1aJhRjEim2URCTfnG1qhmyGaZ39LQvJGuRQeBB/q
cL11OW3XGA7loAbeYsx9nmqTw0M3KvYGJmYSacPUJzAI4Rair1GgqGQrVtAca9c5Kio7np+cKqPM
oeBxUCeqXTQmiHRm8XNA8K2uZPCgtjTeePwzXkMe0YgdhBD1PQNnDjDCcimhrqqYePzUX3932AVw
C5MOFI+rAyuQSZCHe/y0S8VQc7rKNGP6EfQwHHgtrVOQjcff9rK0Dl480EiqzELX5tniS5cjyEts
WsFkuxDOZLdjqOfak2R6NVGFA/ZltzqG+uOUomnZjEeh/hWMt8GQzn3F1X38vcBaoMei0UH/QUsf
uyD2+rj/MrznrMxNUO1Hu4Cv0HFKj4AwcLKA6KAcRCBWTN6x69Lruya/3sN06QM7A5bXjoz8oBCc
aP12TPAOjhShtEz85cTz/YqRxmHFk8zUzH3zV8EHDC/VATxEyD392cx+benxDAqBkpKygckCv3ZR
7Pmtww97VweeOPOCGsR9IY8olBj76JMEEAbZzhgWp5PR2EpwqWiOL8egy3DdVsk6qIpETctD166y
n4SBv02S6C0dsIrGubZjxZhhRXLvVVnPvzQAzBpUCp5jQk3ZfvPpyVFFJ6XK0lgIAUpuBe9HgMuN
1HaF9GxylcXjDK+qPWEMc3HhBvVU3Bu+lQ80rg+SE/LAUJyvHBs1YNxaJNQJnlYQd2bPZTE4gyaR
RKlO5XonoEcw2A/ovKwotHhp06qYe2ahZj9jFdOwajkmn/cU4paJNIb5W8g39wSI1wma56dCfywx
I/7kwtX1ld2L1mPxp8A/85IxyAuK8NpcSuiI8BJX0NydvdyFZgeli1OAvtdtExvYsNFmwaF6Zi1o
WynJlFJZAXbVMW36xNk3eiaZ2lVImQtl1Qh1iut57quNqkZdJ+D7XhrCuxWUYFzmciy9RWUF1N1l
n0nU2+PSOEjlPwbgrfBVoNaQJ2sbAs2LQC30MQkz2jQLRD8brFxmNXrD7h1KVjzMFgHZe5060Sld
IyJaPNlJLdTcs7j3NY4zMIErMBjyj2Bf4GW5KYdUaoyR9qGiiIlaKmg1eLjj2sOZRJJrHXybJbJm
PM/1GZLaci0qYzN0ZvLIF9aspH9JMb9F6eLW4Lnj1FfUJyeAjkOj2glToSqPqanoZhnRSLOBrDlZ
anMVzulDdnw9X50jyvOycb24rghpmEBgpK4UOENoec4jdwy67rtNn4V3/lMFclTAgFPxWUimfV6u
YGuqUq1MJW17Y3/7BUKF+dxd80/arCwpDaFKpkkgSC6z81Pt48QfNr6KOisfHu5S73mDU6FydrSI
OTSCCFGADwxyTKT7PWoqj7W9qi+1Hb1p3w39Oxd8u1pcNvuwbf3xYGBGdaqDZlWww0rFMfM4vGZ+
HtnfCzFOjllImzbfgVNKH3QEuIGPIVZ+WFiRVAY41wDnFuitGXKs+edwg/y05C+qrDCDqtIJbRYL
1xJKPYc6eQdZstPKVA4AcZL723VUd14+Juqm5hPC/xoLc48l41oXkljxf8FVObw1WwLZc62wzrlR
cffu64m8mQctPCuLSYO5Xn+RqnBvpHjyv7GxdpWtxgKUNi24kv+q3yv3mxmSf4c2jFwlUylYKyVN
GnaG9U8XNhTFxEhFSgF+kMJuHWsDmSxRi7FFS/dvA64+FXBNMb9AlT/E9Ga1FYV2rXcGbSGNpW+r
B8ZTyETqJwPvrWM9J7FehgtQKGL7CCArHLMMPzdIS0tLM3PA1a/aJLm6mAfSHyCzQ13pHl14r2WE
bN2rRfjDzMAcDxNlrR7T3Yo0N8omQfhm8sVdbGaIJvSTggbwI+rCUnt4Cm5a+YLuGPUeHZGrEx8a
drH5DO3YXUaqdQX9QOs4M+Qgn1sWbV0LK5jw3ZFv4dbpWkYnVSeuJmE/glOmtzkEZKVHLiWRYwmn
9yvkONq75+xzZ6NWE7RGQ8eoj54yyTTu4UgPw5/vEhYPTDps3LM6pbOZDp/T8EDERBbAJh2vkWYC
TtjcoRCPcp+nru4u6F+9xqh2pHoIXo/vAlRhyfneYRY5VAFXkVs1mbpDx6gGwz1KCBXJHeY4daAi
AGi4pogHsZfxDsMWpdaBtec/Xxiu0sg/K9I0b3McuRPR4ZGc8nmEbiPyHE70QxgbjiY9nLvEYSfJ
N+4P/e1vjU2bWN6QHMMtRoSC82UfEw9GQ1JXP9MVvGVV8rw4vEM5S1mVGW4RKniZ8A3Hz2fwwZrc
jr0G41MUzNyv9KMXL4a3wjwY3YvKw56FRA+wYTGMcVggTDIBprHbyHxD+30qaRGQVilLwkxzUfyJ
mp+rSqSBPnpqXMpo9xbWAk7FULtR37/lzj5IwPVQyzUVetHTv+1e8RbXTPVn2SpxhfZlTQCwsudq
uAQ20Vr0PcAuhynu07b2CWlGCMamDfktynR29b7g070wZlSJC0VjiSAD1xpZc0UQpDcOERwUXEU+
jtRB0xhifximXHyzgTAJ9SWROfiHa+XNudR0wEFLBQEC7/7TUFxsQRwywjsUmYp/GdcjGoTiRH9+
p7naNWhsZCDb6z2DHP5FoT0aN6CsTGpDzRwXobMUdOt0ch+eGnr67KFFlaTTu+/VpNvGJIjyqwlj
SuLeZEuKtfvYRUqd4L9v8zsh4y1wKPx5LlWtrpBeUWMPYT4qUYwLrQgYBuvhun5HYeMW7az+pPJW
bGvjBnBNW7dWuD9b6QmoLedQwqP00QBI/I978HDFnSv6pIeXyfNmeM4Sn3U7+irTeh2/mGzXonJc
c4ZCe8Fuxn7d36H1M700aQkVNySyZ0C8srbZ+xbbjHjOSpPi7+OdtyLl7qRQhg1HCS9wDr85oA0s
0Kd2TiOXIMwRM+pQYq6HJDBSyCXSFrZWi7th+dJpy2BmXhbAVXCRQCT9aWbn+FS8zSntJ40hzyD0
k9b61OioEgroeB3g/rtVDJLTY1LeAWGNH8T0B9EBrXDM87xlYHTnaxsBEJSS1wSdDnOS/8TZ+QRE
MX9riWI3dUlZ49EpsagkCvLF7d5vGwS/LMqllTrxXwN7nvnV9NrPYF5+MnJY8HFYx4TMdGzVIBNN
H67VWc+aH6lsY77ZPNy04Xq3mr7IviIBk3Bz4R4VgNg6BLbw8jCjdTkYUv5+dJTCkTh+taDMfM5D
R+GP4boezaSIr9fGQ+Je45hhHJODh7F7k+lY5VQPI0C3KBKzDy594+6VPOAu2Nmf/O+HfCHt4Hjl
V+sF59CWAisfjhzZocBuw7vMJsdNA23G7ac504WEwt8rm8/U0nc1hpVSpuX6JSRVznwRvHveWoWQ
1qlmLrYCASCmTgN/wp9+7IB4FOBhT1kpHsFGyI/J8woic07Uw1ft98a1fceSqxeh9fUHTQKicETI
0+Q2IyY2cYIKAblxxE0jr6xBoSBnkTKehkvSlLw1Ujyw8Irdj7cbJxPsE60/jEUrNnp9fyyWxyu0
Qf4xbzLiZNNQzcdxWt90Q5itoeDfNTZJ+jFnqUWOSh6DL0rQ7RBMysWQWtwdWvZ2OcuLTybYXY/0
e8cRajVbapB2ROIzO6+dW5ocf9sOu418yZXxhMC5r58OIpNfClU657HN6DUVial36jYzKkcTfJCt
gqV3iFBlDhnHw5oCGuBiGX+EizB1iJ+glhPMNZMc2g1y+KlNHt+Y8ww7+L/CoQaUz2jpjKaSB8WH
VfKB1l2cCwY+VIa7OflayYFLlmD2hjeIcDyxg5aZnhdilw+eYo4RVyKnnyrdEJ/GtLqpCFUxA6/d
L1pU5HVzq4XjG2SefUxnOdj5zhXQeY3wy3xx5yQoFABeXdNCTtqHmfKndvJ6d9zqXM4/DBpeW99h
6QoB13c8U5PJMYCoa1bXuaDiFgnCXt31gHEGdrdzw5WGWTAiDFDPCrnIFxUAWRnfiUfGwUsRweei
K/588COEJugd6TQVlVcFWw6ExHn5oBDCPazpkAiIfym5gdBdMo/ZElK0RVW3jyd/TCyC/XYpfcyo
xuc431t5eW59QafmZ8CLRiLMKjwP10FnsAkGG8us5kU1gLtazM7pgn4UnEuSe4ETmSzMKuEwwd9H
oFlvh9rZPfhWrtdQ7jvNgzA5jg+QwBS0F1rwqTmww6RQN7qkofB7KeTOqGsVoiLe24wQQC+tt8Ps
G+yTBqBnYNiBfahPnet4C+96+hCKFJVlvwh4K+r2n5x4iUgwlaOj4UEfanCoPIQ5llB+/1KsyMAo
Vm9mV2nFMBysS0NwmqQO8RjEHBAMdKbBTaw1kbTnXdb00Bl3jD4I9BjlpggL6PPJccmeMrBWo6dl
6sTVz9ZV9k6ZNBX6fJSumCnkKq9GBFCwO91Fgvju5aZOkqF0p3rQJPgr9pNkA9EQAxibh1mqr7nv
Gn1zdDxq9/3RHzq4ldO9lBGFfB2dKNRIxBSPGO3QQ2pGCLeStfxDgcC68fsUtg/QVmDWVA9DWSF2
Nbw+A95mGvhfFQi1ZVReyKwe06SVNA/nsWOri6+N64G0k1hV4Sp8Vvmw241Iq53XjbW0Ci/kS0BB
dAUFDUCEQlW9Mu5RN5kDwjPDwAIu0jeP+VbWh/TcfpKFZYIxPI1oVF8RpY45bqtxUXsZJzyDayQF
dyWof6/QJ5PsJxVmF02fYhZI0YBUXcO9HSVs7PrLqQYRgNVbjOu/bjjXOog8P019c/HWaTRXj560
Vz551/rG+dVzDOdXlX+O0BF1v7TSaxfzfoI0SHKJWspG/xILXD9dAjfcAqTkgs3kjRk3Z2xgWeLX
OzJHEviXPLkvmd7GT3pDagmqYzirswT/DwnHN+3uQ93yIRuuJfYYTHIOZotcM+C2i+8tf/PeG2gH
odE+n2EDLdbbGxfKA0PAU8gmdZ5M7odI6nklgugAU2a0TknwaCu7AY2543JeCR4LAdysBI2ApSbN
7e5AhAB0UGwjp/qvA1B6DaQVL/kB4RQK9cHr+CuYrDJwebt8KvVdJxlYBpzYrQfwS3LXfCk3RzGu
4BYBGt4ggd8Doawo0x4KEc9odhc2Jg9fzRxXYcvPP9sCUzVjodK4rLz6CxJVv0T7aQtlA7UD5+U7
Z8YrBou92u89w3bylxuwCC3TQJNiKt7iDsSRbkzB48yq/SKxrVDdwhBxpAj3tOHsj1BSSvZXej1e
NmV8kBvUi/2dRFj9yqU9T6B1wzBc/Ql1qNdzkyUmo8R8inzbtASHQMOEQ+YkctIjLS2E/ZGQaplD
KnVe6BDeoN2mLTFOaTrqsSZIUrwOQYPI0G4NsXdkrKPjc9LxJ67CzvOQnqT3rTbNY4AFkY4Z+zvt
YYAOyL3g16jXFqcT96a2nbql9g6DoB66brqRq9H2SRGMSkTiS6w4bNVEKnrfQfdrlw0AvF8OrBD1
oz96RsFyUqYsT9cueCRgZyNNKdlb5g/ITrGZLVVxI6DuVZQc894xGtk1XN7xVRncVB9VpnhDMycq
fl1E+AE8mHD9L2t1zVJCHQLp02wNEBbGDX/5i3DS3Vz7e72j2wzYwDQSU5akxfDxfstXUJ6SVW5D
lBiPE8PJSvqv1ljMqNuKbkHd5MW5dKRqn2ZHT6dB8QISpwwcIZTRlEfauackUYY7w9QumMCl4fsj
7rOcmm+8dfrrz9MS4PllrVz//8zWhqguzHFQ9ORDiFmUfKFZa6NPThq6trvR7I0xVrHioR31HnSK
lOa7W/f1ZsRpRl0bQDnG6gZ4CRSNy4Nj5d59Tw7jx2ROOOFZg+668gnZ6ii7nmrol/vzGT9tnv9f
oDLA7k3Ilp15zdCAPGq3Tliy0FX18SLuqL1KGZLpQL03JQygW2+r45t8JZnXOYUMTyYx4N23hjsl
4sw/lzVHwpuefNp09LxmED8EYD2AoaRJ8Tjde04rN9hqb9SbRipLfSPPIAUHyxnpfMriyTzDSHeZ
dunV0UdKi+3IUvnExa8E5YZGLsWn2FV4FDNtGDdNbbzBZL93ZehD9JRVdLsAP5NP7lNmOSVmdrYD
qE57GHefkmOiJFVcrW7JQcyEGMji3fZLA2oeMPcZf+T2y52A1YDnuvDGJS4XRHbBTsp5gYGHvuyI
7hEx8o/T8NSv6YFYl8AXM3z0cDOAuC8OfvUspemIIuScyTg5u4AbrrYcgEdks2rRxuq95cu/5MDi
+z+kz9kTRlbYTpWRdt4PoXD0P/7MUjzyCSH0fAZjJ9Ud7s8i1n28J8/c2TYKNj+CayE2azZnvcf7
hcKv+WeoelR8Z13x8SPyK87+Q/xe6N78wJS3P99+7Tsw/qjiLE8KLQXz1u3qu2ZArqx0GSWzLJmC
/0jGsMXw1aynUpsWItCnShH86d/7rI3qB5IHtILBAEOLgdKyjMhXuPf/Iwt96LjXcFHI1WXdnsrb
EXHLl0SEJR+22G2x2Fh3bpnmThUpbPYItZ/jsT+qcEztyy5KmTHaiVwCsLNTbGRwTQ0HbyBmmBr8
OusBzHuMeER8C3t5Qv+578DsV4TIczzjUlAu600srHZ6gJ6yiZw8LpTVTvDOYwNnyHJoXBLFsDbG
4hVQIl/lIl0kSRid4MhTq5jYQRRv3s76I8FVQmELke/adgknYgSOwPodDvLVTmFJvxBZu+bm3xkr
ap3CXEr9f9YifS89LL6pmYEC6/NWpD6WiUyh7Yd21W2+HSzfkcdTo/eXY3GbzQvEVlVZ5KsWtvTd
P3TAYioTa+zpEUM83C8gGMFzim6VoAWLvsm/hIzyzo6AlHgTQjsd88EynlolqdZu4zR5gztCcppG
HClOkl2Ool8Mi8qoqt1cXnD17kGwCZr0ehxAx0jhjNqXYEejkezZmBktNqhoKSctjN3FDqq7iNFp
Vh3g9KRuZATgAeZxf51t2rU21E0Ke6qBrYQAhp+wTcnYFyFQ34KLFjQZEhkcE0BNHsT3qau3Jzp5
oxaU62NpydST1KptcL+SVWrgGslDYLZ0dA6buDP5+FEFhfcdEIu8gGOBferxkgHPg4vNlZ0qvUeF
WJKDdi02R++vh10N95TwKYbdBs3f1axoEnsVnjx++dHHfE0ju1MtsSYEmZUdKk/FhG7xE+9ix26p
xTOyIF81IEfm11Hd+hQxBkRGOx153Qi7PK1cs9HFTtvK5iDnNOb93eEGURx8EQWIQNiVshsU632z
FIqLkxGrLkhGVK8m2sg2LawUghkaRhQ0+8pb6jVoKmvJf7Bo6dNv5pmbeAmoAUv0lmzZF2rchJme
yCiPQwNcHrzkZiNl2dZq+jctrsbiYviVbTnmYozWyECiP+OIMZ0JMY/hAnNKDwqkdSLP0/5PnduR
+Af89IzFIQ1+au5YKeuLWYDwdXy4fRcgiCoEziPeECPm1PkMwVAv/lfnQgoBbencwusN5dsGGqEc
Ii05QgEtP+Ewie0+NDHtf0EUeWKo+sD6kodQzxZCihovb8bASXv13NQD0tju61iIPrX2Qx/nc4Rj
yq0F4SCo2WRgAPr8rP6qsf8L5hsWhpHDFoKNuuL7fd36yFur9BRyUAO+a3rz3033ISRs7L4QTOIr
+z4m32puHO8onYVN6RCTz4Gkbe+PMB9KLEGvNSUuVsc4b9oVHrevgkVRBYvHPYoZHiDR+msZfbVw
NiLsjXRkg/S8rzq69s79A0VibT5WoPxDlw8PwjfIaCKt1FEMMdDHntcYxS9Zga8iqnPJJ25fKw9M
ZpIqcwKI2dssB2E9TAMoixKOe+GA8KZevo2af/v69ouZYtDieJ10x84Ss3IkogHTfD11tkW17HWv
Q0gPNNsFtQ8yvEl6S7euKqQguWe3ubp4kPtdUJ7LUxikTk5b/liTOkAnrTZkZ+U7n0pLA7WFPbJv
EUAowFxP0uv4LwVOBMrE4vjV5T+QwOAspg1FMDzLhLqBmvzRyftin63889lYFvTPwF03u2HMQp3f
hlzGYLb6aDP5XP/4rcgsNw1uvsNbqU9s3S1LF9SRphEWCsA1ICy++r9Ijiinr2zljUt5leQAxXXH
9itdOiBtSfoZf7h1STvd4N3i5IVt2s3fHhc1IJbjx9Po8lSfg0OvKQn6+gpDnFMRxspfoShstbR/
Kfu8ZDe4Q3XqOvXZfT07rf9ZZBTTb09cBKPhx+6nkL6iDt3mNVZ3pT/p65noa3U8Y4IeWWObPNWh
pw95hbdzkgomntwTHx72P5HeTJviN0IBxtFMOw73sOdUFLUfbp1SIAAfQxVUsc4hO2708frAiM3I
PKHuTWr0GS/8vph2YsMQ44wJeZvjs68/130ZRE3cj0oxX4xGcaMeUjjz+KGKlbRCfCkJvAcm5ypU
J+ZPLTOB12x3pNY2gijMqVTJFWj66uA82buP97T+zDgNbQpXVthTCt/D7ZFhts7mJTXONGmZPTEb
uDNW72ZD227+U2/vTxQte/7jwn6mVJ5Y4AimxouGm3YWbSsvnqSzSCVg9elVNTGoTXAiUp+D7OkY
HZ1/Gl9teuHY2JLernR+XlyuTp0803h6lOAyXLmYkwIi4KBwI3SbuPB2i2p+QidsBYGgqTRSxMWE
ruYXSIiqdIJ/tij8/V5+lIN8gorNA3V+0+5dqK9DFyzm1qsuC8K9Svy9TTYlK0LR+DY6DpZU8SQz
vkup1txk4cQLLwJv83bqu/UL20W+XUMduFsuq09SaqBo5+iddqtefogMJwTYeS17zcxp3GO1evDq
LM2FBojsUE043Ax/tVh6t2PDgggC3TceCggoCNCeb4KyGD4HVfAfGdqF/4a8NNyX75VPhtd5xTQW
Z5IHMVD3nK79wnjZcXs/jce3QE6dvCKRfQ6yh5hzYE3xN8+3CjTdw9EZUHyWmXKGesrOJdO783C6
i+fiOd3K2duqTfXb9JJiFoGGmlQjWaRSz2xsgT0E8o6FWPFSe2xhMCBOHda/KE5nhGGE28pHwfjB
x9FWLofVf/HCQJh4783ZTiVi2cYq92fB4T5l9Y9w8B0OeiSmj8/Idn9DiDGZGqZlHTyfcnCRQ2wi
S+O4W3OEv55i9tFNw/Pdd9wioEDWa5V/M+ACuDFAmv7qAgPyUWjY3nSbfNdLTTx+mo6uy14tX7nV
EpWoj/NZCwVop2ziNmzu2GYLscM4jNASQiaKP/R621+/A01Gx9jVgu3w5k+HkkUP2WP4cjA7jSEN
JCTjUSXrpdoJkeimmtqt1qlduDJ3FkKBzwXFiB2cVTMw/5qWIReJRuJ6H6ZlqOSXCCOCxn59e57L
KNJI26R7Qraa7sXBVVWnY7gZhPOhO9IFZ3RkbaAKyvHnd6xBrdm0Oj3c/FBliFvxl24FwJsEYXrM
VtpdK2g6gremYg+XU6wP5ooTmvSe1huAQ5Py1w8unKM7IOch1vih0ME5zvGDXqNtjoDYXay97RfW
m6130eCqfbldUkndozcc79yWcOr7C6K1UarzbSC0mg+ldzJTLxXz0WC1Fij0IaQcKdSYcqdfFvz8
7kRDF8GhpDCEp10lttSNVwERzT34KwvD7XAy+KOpwOkJIzR+aH2fIrCd58ENi3K+FR1IjvJE8WCu
wvH/K3hVlaO6PUR4E6/h/nz6L6vS5OJLumQtfAcMU7imx3kWKOTZJIs9eg5Dpv6T4aCryp/i+/Td
Ux9HRhws1F/RXBqOS9edLuUL2RRk7S35IKuOact1dTUyYqQDZrobwbNMFtjV4DSKjudRiLqWNNjo
IRDYbPmnim+ac1MYvFwlicbfxv7Cuwku4Gt7EEd0adWM80/IrhwcU9/c8gmMao+nZLZgYHvXd85p
t95FUh4BN0jJUA3vs6jelx/EpR4y1Bwaq3lIC7RXhQA6t2D9vHtaUpfMVL0rw77JkZNsS0Z45Ec6
UtQnP+br+KH2pJJ2BYXD3H1w8+K3Q8CPufT0pUtXtl5fdNax+oKEAvDPWqKXKS2ljnZBeC3eKQ/G
qbK0d1a6U1M8SnV4DplGPfPz0qPOqtmYVvXStuib1K1l0TrbmMpHG3S9e4uolwQk4BB8uudv5fDA
QHEl8n/9tq/yn7AVdBpPbMRp54nAOXNj3TjIUur0bihz7vPhQhaFLd3Xl/lK7X9GAIxwoqCmzLgY
bXprtlYzhOSmmP9xvfsT5hBViH4Qt72/jTTed5HWzCHnlwIeIWCXFkLDihx72fJTHYPz98iIqSP2
l05YpkYo/hzVdJh6irpAUXq/Ks/y3ije4kgwZ0s7LXvCTXBpvjh4oyUeJt2xcqq7zUoRhbrqNHFx
iUg6DtVm5bbc58hiExwZOgQa+SRjiUbntuLWbqRMFamkLrPsIvGiq/RtcwkY6mW/9Ge5OmBewGcH
oFfEXAKMfr7gQp3xxNoYU4ZUxU87C4l6zvAzX8mhciey3sxovKMBvpHtMqeWw5cpGJafGbKBbkbO
vCup+bstl25yCqHoP81cDFUOJKCgslNff6ZPEsdirQMrPLy8Yyt2+BcrbUWDetI/8hKX43x2Zpjj
utPlZ9m5PKZ0ijWCMMyvYCVbHSVRhhWX+S/q+Csf942itkCxstjmMe5DKnMp31odzzfURbR4/kdu
nZRxqq004pIUC8qj7VGo9s4UB5DcaYItprS/X1kvL9eo2HRYuGS2eSrcxSXX6GYxYT/Sqb1JM9EZ
wrmeanABk0pCK0ZecJpRJ4wN0BiiBJ/7JWq/Eq5H45OAEpFEr1ZfVzzWuAbX/kV0D3RNdBBBZGeR
coNgccnc+AKJCe2VP7iAfdoWiHSgfEz73xZa5GjRRLJ/ftsuDMQt1wn5K+Ba+SGbh6mjfgsVb6FZ
NS0Eq0ZQEvSF3N895BAKI2OiZk73j8pFhaCF+KM7hSe/uZqTRDF32opaW3jzleG7xohQVQ6o+nOE
XWOwSuZPGwBlvZHEOh9W/TCBmtigokgV/EeEY9VwgSsIkF+6RM5nOJucN+tdj1cI/DgOcD3zbwQY
5ZRcFHDb449tJrC4d4b+GMu0qlkZ0oAzla8ATGQ0MfhM8NRyVXpXLBnXGwuRWO9FQVOlbOCn2hnc
wDElrOFeVGJGfSPyJjWApkfRA7adxinII43tWu2hrfS+hsRf86lhf2W6lr8/Gmltyguv25MYwriO
NuVPmd4G25R2qyRU8c5GPmQOH1DT2cRzCrltpryfSSKwuDpqxVY0Yxg6/1sTn8QErZ5G15+A2NyK
19wYil+nr5zud3y9ZHRWQQqg9Q4b6Bw6lInOr1XW143E7DBoOr1KvA0HEYZ9EP9saS9K5GibcXQU
GhYrMbetsGq4hZ7C3TkJClG6eOt06pvYUeNToFV5YePK4e3RzynNj4bk0qmz1JnW73wYiiazvUKS
b1bOpzgsMxzAFXFlx3x/jgfCNDsyAHR18RhtbA/Rfpza4lGm+O09ESKDYcxFU6XHP6JaAQ4k6ZyG
8nWa1WeyhMpd5pdr1mstfdF/m5lGincddgL/iKmR3TWxhOrvF+Fk2LLcHUKZeDw8y8mqM+cl9zuL
CoVNEJz24IOgl/+najh2JEYKhVyMcDRtUS38Yruyk7BeS/c0GFbJSiHwZMWFKYbwdVEpJ9dQEd9i
2c23y3NAfH5xYvIehqZ0D/rD+9QGe4J0DuX+abWXnfrNDgrpGsr+oC66MLavmXqgFf//4ViHg1M8
Hw8JI+4iEAfLQDIFKGPpCp5da9wklgU/VOLfo6xhKGfdOfyPnjrAiFmO1F72mvvAKnH2WIlsYYqh
JDi6V+XTbjxb1DfSkfIE2EQfRuN/OxCFsHp6hj2gNd6Uq0Rf5ppnEgCMfYPqhQz2qRjmh+Mcaml7
qtpGo5ppS3HUbyAlQFQLTZ4tUMu/XMPVxlrxkIYOnWJh2UTsWGD/YU+COWnGndIM6XGYwh0ADdAr
qc+v2XLLaGQ4+kzIgnw8zCvjxN7GTnjzoraX9uci3rkPZvTGgnjNXroGAaismmbtktoIiiqA7DUM
jfwUrwpeQxwH8zdCamPb2fNXjIoHsEP6t95x38oarKgFVZNC2V2TUtjfElouPuG85N5l1dq7nKxZ
4JrAA/Gfq+zxSpqeF4HR9HanU+IQfrrMu/GwY9uFgc/bY8qwczHJqDfSK8V/nwKETh6aJsIVclFr
vRp/NCJWTNibqIM9jtoSXpmGT2iEWk+Ml6VFrwtGqqSLP7L7ucfr6rg6bZLP9Qlz7fiEahLbqPy6
vEhBFgT06NiAraf0s9wk9SLcKy7sQqs58bLmV9sOAPi8PJjm2tLv96sTrxcyeYFyqW1me/dpAJ24
7tVPXTP2/FggpLWUUbFDQ+9mpgKiy5NKZnDz4bHjsWC3k60we1/YuhH6JTOL3NpzrDAVmrsOqsJ5
hnqsGiNFOJWBOmNSTprHX4A6PBIdlUmiaIm+pwl1e6pbtaVyi2ITYfu/uksh1MeK2WrfoIUX1Y25
MNpa/dSOxoDc095nKseUjaG5Qcz3rpqI/OWh3dqPI9v1cEA7LyeWqZZojLQ/+Ps9mj9mha4DBsFC
YKycS7koch5R7OCpx1PFy4424Ppv61KKTvlY0s5Dzec9amyLq3ZfittoWxH35Br/9ke1/fNBWy7O
Eatmlmea+66KEo/7DnZ82REoNG0yd+ESmuapUoL4G2n6WbNo9Cy1x1CUMmW1Fs+76GzdeL2s5VjH
lCJn9hlV/YciMdhVqdM3jz2u2fq2kqOZdZti5t3wFBtcK+VkJyPgCVEu/RXlFfq1wp2UYW1AgUQh
GMqKkih1o3NKQuXY+trMP4G4GhGKsWE6Ji+EAz43hEyshVR6me+5ryFrJbRbi1f0K94vga00Ts3F
ID3Fm8sY27U1GiYMDdHVIQuMOBulnicMkazKsBwgbsOKHrgrHMn4tVOu9ax5M6u6jJzcZ7lUspZI
6HtCklOnul4rSS693iFk07I7suM/ySscSRis2/4guYn9o0t0JOaUiRBCc0zIua3/lqC+bt0oxCbL
CjSYx7nSnor7nHPYmXPWRq86H9zTcSKtsdwApiTpxUD2Kc7x99D7IOQAAZIoAPAUqgny0yKcMqXk
GjGeltbJSqOL0UE3oEZtYj2s/2gFPqzUt4Hv+f5nSg8KtjRzyhVcR/usMhGsiQGXe0VmjAjntjkU
+z2OE/GX8pMg7MFmjLwpzuh3M6ruoeMvRSkuxlJZsnR5OWtYjNKTbKhDyYcf91HxchyKc2ODFrRg
SpRcjP3mCnhRVsc0sJQZpavkzOQszp6r2FXevrQfT3wbWw5NFRlenfgd3W/ezxQfYKu2Sx8+Dacx
bO5GnyLySeVhyUrLf05vG12qbRuS0VQJwjKSNfOUdcIlsce7Qcb0SwgCKqSunGjIjKVI9V1Njurh
k6aWybCkECjR2PvcHgaByXE3j2TCfF1f+bE6DYMmDngn+RB+SI68ix11chDsHeSsPvtX99kp6Z78
dnMrSKau9qpgWBxDMBl27GWX8cCz17dgHjvSpZR61OUeUJ2916TwpQpcVTfIEP/kO6UEYTmuFZGd
WPoQ+t823N5zxSPt9D11NfNUAoyTyY4bRFBmVcUNa1ZZCmbbG9k7WpsW+Br5L0+lAEoUXLXRJlKX
9y3idFAA7WB9RDTaK0lIwWAtRnpnRtME5uIV6X01bE7uFsPM7E/njsTc+eAx5+HNqyVPnB5oA//1
CbPz5rjbsEiWfygAWS/f58O00IhiSKfw2Y69NcKnwn0uc9nP9KonQwMKbDPZBxIdsZ6OR7BJeFXH
cKLeMflrE/QzpiZ6H56MWqx0ghyz6qm7De48qYm2XBKY8+BThJZ8CftWxA2Ao9KAF02/4JE/RX+i
2bb7b0RClv7gvoD3j50hnY58D0Db4Juf5udXB/NnN+MgpjQTOmt/+1Has5eye8JVKpp3UPI32VmR
OmBiv4GhNHZrikgFTDFBpBP90PyaDSXDFHd4AiTvipCL5gTMas+0GF5PMGryiMouOsT3ytaSCMoH
c7ZC/3UgWKbxs6LgsPZPPWSSmQX9ebkUDRKcJwcK+epIVr+pQyi3mve7wHN+Web/vey1etScivDI
vkpLHs9Bbl0WdSMEqCHvDFEa+60YgMnVOINUl1mEEww+4cDUXa+FmEf70BDVb2cU1bRo7lAKPn2u
1SxywW4di34lj16PBAVU1hdtYbJHLRp6UoAm086q1DS2oxgcq3nU5kZqs7DG5vHXgql0nOfk+pKk
Rl6stwEyBdtqUoOfpnD39Qa5jwGgzBGj/KkJjv1yPBQaaUDs2zXoEKW3dcw7ujiRa/9cNoZy5d8p
1dr39X2qxAzZ1AO9Suxowwozp+UGr2FBHG6ssvCU5A36qmHSnokhVSA9FExafWp+F7CNdIlMLB5b
LJNso/1s4LSutboklIl7/LjOmfFhOwJGriMEvPvyBWD4/Pk/fNsBeJvrKdVuqHyDHfFy+IDFb4Ih
d690T8Mppnz16gwvvoL7P12GVr5RlnfqBGHE1TWgUfnWN1xbQByOAs98rnx7v+do4W0rXUnHOGA+
fHoaicz2RthPVATM5hGs8vkcC0MmCXziLTU15IW4kCVsJgLbw+VTOmcpvVuc0+1OWUlpz5FV/YxY
OspIlYEyiy5PsCa2G+vBbqpYjYSVP4l31nq8wT5Q1UN3322HFGvUHMYb2ghRtSilIV+GGNW304ci
MCHMYTWVqgeXGMS/lCsk7JbfQa842ewSTuDbT4Q6O9+qhGltzaeiwp1n2XRL4NG7YUPHvA2G7xjz
WiG1a1O7WjMIK+LydTMrF0BYZcl65dTQ9pFDAQz6GT8VWE01yai00PL1thcbDLhAf0tmmWCD/w+r
SQVXXheNLf/+zI4y7get7AUVhnm6QWf4F99YBM1sa0/Ag1bKkg6t3JS247CHPHAMq9e5DzBXcRR2
uaWWahpvLLGTf2zqsPItJM+XGH70NwyP+D75Jwck9+tsxWVn5ar7ilq3Gc4bZUz460cePXQGXuXG
J5c/3clCikp6/vqUFQFprvHAtJH9qf5zvoXL65f6sVxt2/GVk3LVt25YuRagspI7dTrp5Itju+MN
tvzzSOAYAUabAdpTvb1tYBmMVp1++9b1Q786QK+tSyvNLiPjiKSceJizlGsRwjAd9aN/7gNPupuG
ksl2GhBUwfU27ynyWzdLdIRqAJ1CudWwkkA1WaAbmACbc/VeKqNIsL+TW3dKpSeMvx4H4se18Pqm
ZhrUeiXf96bO2rPSy/zMqzPPBATR/LvU0kuQJSqili3DbPc0NG58NULJ+iw9zKrdI3vva7ZcS8xR
Q4JvzidcGfuGT2WPO72TPB4orjRETOPEqq5xP693tlqljmKZ3XEA8CwbXxpo46Nb1Gzejz/M4agi
BP6WwAiGVvB4uTxHDJargqhLCmIcNCDG/XEJQVz8BxXEQjEyIp9SfOqdCajiX9GTiMVaGxj4VfiJ
8IaBbGrOtUXJ16zJHG5j/YlwRyq/g8bRoCyJykTQYIJ89TmQm+Aj+TVTEuoTJa1ed8dZfV2HRzTs
LXOre7Xr8FQplem/405fWk2A4SvUILqIBpgZ/pjR92nJ0qnlaApORAdW/uhJCKUy4sBi/vlst9q9
jYxmacqrY9VMZhjJ940SQMhiyYf9d9KQxzwnZo2tvKrcob6ViO04uz8H/RG7Zro6Eua9sPYDYlIb
yGGLWi0HktaE9ifIX3v2HxY/L7x7c2xrFqVTuAJ3pcRIbWlEthWFWFs0usQhzJAap4bVFitlPT5p
rtDOagMy0OpGw1dR7f60Itn+kx+dhjPIGmwQjYzZ3cNBOWHdMA9Q2f62TxlA/JRj9afKL8IJJnqT
UL5YS7ROxGvsx34VZ61g8qIePx9Pb3wDRMozcFoc/8DqEeEW0AwDlwrSa3Hg5h1gP0jD8gUIXOSZ
Zln1QwOWen1Xqyb82pQ3Qtl8tRN0AuX47XmQy5hHS0cvaSPK+oS/qoxPm9QUTPfkY1UmMzL09rLs
L1bUIdNwaV7mPBJfkI0YcVgU5S6m/rhfWdfN1MSHoHR/73mV+INU4LgDj/JCWWva0MXTCG59YfB4
KlvD+lNmofwv5eGz0g21vNlncKj6ckfHFVN+BWMyt7uo/aIaDbCulpQT/I5qArv0wufxPV7HBAQ6
SihZ7M6+m+V6tgj2EjT1bzXQyltvmDYNXkTlM63maA8gI5thoS5L957iqJUtsdScTzK7Rw3ZSOIM
VUQZCF3DshNE1bySs2RugVDWngKewO3xGcw/3QwLnpv0MuK9A7wsb6jlZCCQ4NKHYaqGQKhz72cr
FZ5ToBeDpISH/LORFbhmru+bZYJPySpYBMxEHjG8qGZQY+hJKorR7xHXkQ0OLc0lDo0tuBl4h4Ax
SFvfITdwpY4I7/S/VfdW2UbGdpvmDs04nI9vOqusiZ1wPf03G6Pg9cNGpt16eRuj4PkEez8yvcfE
5+QGXLe+sfPDKzirMeRM/N6Z+zVwnaUNC/CYaYQ8XiKnczLT5aKrW0hM77GvaU4nwrOXRwhZ89BP
WCYdD75TnX0Cmzs41psEu4JDdLYzeiLMSYrk/XZHpV71++foJnZlrnDRxsmNrnZKuJ4sfcVKGHKT
MdBybDjwWhHCPY0f2QOME4BxSTrwVXbVyyQPVEyDZogW/vZMr0YGiAjNWb9TTD50HylRqndQQtdC
/4PdmawPlpJWMNd5KsJv0RBrCZoi0+NGNZ2r2jthq1TUUJgbG+diTIIvALMJ7kv0Ec6wbE+ogHI7
kCa1OrRWe4DPCk7yGnOCKnAiqwXSeB99rEmRUrGd+pLiTVITVD+QU6GHzCmJIAYugXmgrfnuGDXt
cjn5cnMFwglXuMRRf82po97NND3LX49Z5bxaNP6W3zP1htKenq0uxuNTnapj/lVvYWc66qmVEGE1
ye9FiPHWS/u3C3Iy8uogrk29PHqCxWNRzgBHbUZNawIF2sTYQ44F/oSmEj4kN2/xLEW4Vu1SmHFX
TEQvn915z8d4s6pSlsrBlfVUfRj9SKd9mI5wekfJXwP1RNsBBW68SuwLjX+8puZ83wBnXv4wX93g
98Oh2GofR9QJUDusHGZBlAY/E24m7XVmoVShavZWIN3J2lFogP+siKZWU4vKNPyP2sbVvjR7n2jb
SxrFwAb/p7C/C+YdNR7Zc2YQ6oC6imdxKVoYV8r32HmRVfIMIn4zwQFcFXi9Icyj3jN2HOi5fGzt
Hl1qpEPKR15A3b4+ALk4UK/+LMfigNJ1aGP+kGSt+weCnvyeXBkbxOgjK0cjdRc/oD1wpYAB880+
6JfNzhmCpcvbDxcaI5SKsB6m3Q8hcZBdLd8tq/Y7H7G8rLFJvanbJD6gyVJ5QlLjKSfipUcRPhmN
2vtrvmiXuaqYe1qlrNYUbp0fjo6irxS+iwkD7wX+YwQ/SYMGF/rBA4GV8vonqRr3nsEELZEAQrWH
6cVedWF5BqZs4Dy14dBLqjLg6XlVP8Fa9Y67yh4maFHx8QLCpkjEcFzbbgxaUkxh6qvsrUMn15Ej
liX6E4xc8GwYQ1sGy+v4DCZIKMpLN6kUJgV4MsrRO45k0kEDH0Gb1gNalVIQT7zywL0Kt/39R+kc
CDZDKQkEBf+ZKfLnVgcHBcKqAiMBBroZC7vKWemGpinz/jDhvVLOPF+a7QPGQmHD7UPOCjVtC3QV
3jppOBr2RojL7ihyFtUwGi1MN7ATDV+aIWB+AGMgN39mjkTnHu7Kyrf2huGG53hZrVrAcdYhncA4
3Jd/+z89Tp/FwkDUbLcYeYaFzkdw2fTxZch5RZOGFNo2x3X0B2nRg+8Nr18oyasNYQvRpAbTerNt
NcRwrmeOWUM5N59FYzhC4c9DL0K0gUiBXhi6/+C8lBXIi5d32QGRLHWoPktWyXP0Z1p9Gu8FlKOQ
8EhClSa7ChoeBVJBhYHiXV/uxebJOFbDmf6mVtA09tfojGbsgEMSYU3QqLYCPauglkLDrHh92TFO
c8vhYXE/eutNYFUkz8oQlXWhbEjd8uKt2NseJIpMiPx/3IiRvkLf9yzMymk4ZYjOMBoElV1zy+TX
KMUhQWUQDUn+O8aldrFwdgAhsmd713u1qsqGRmqEsl5gkmt0g9rWypZAy5zkIc03kBOQZ5DEDqdD
ryf5wzGyuhiQxbMq5GvSQnPlKZ/cZpFIzt5dUW4G1xGfCJJwO5fOUILm2P2yGnAtdn5PRThx3uMZ
P9viosaZL/c0JM14Ebck3X+9GjKIyNtMBjfdi5JX0UEzXF2CtpkTCT+m6gLkTbQP4iljYjc5LLhc
OxrxZp1/gG6CjRnXMuIUVF6rnC1B3AJhMRN6D2XYW0ijnil8S2VXUnGMG1VCCYCILOAgU+Ho6wYv
CPNoJSzMKnoCyOmnX7fchvs2dtgCrvlivRAqqPmqL4Xuek0ezPoT560+QHnaLI+E8bcPrWyn52S/
6h1t9EZ0JaXAxM38pL+Y+e7oAvPZHoMrSomUoXNMGjrbVc8bfdap4sozJfRf0jKS4vJInDpZTv73
tYV39np8bX/PqQ6QMF0Jd20GJb2qSODJ/hBiHFcXIh80a2hz5dqd5RBYauTV3naLWOSExAV/XP+Z
zGoZXwlerY4qfFF+3jN+UzKDxJ/rhK/Bw8ikMbQzpvG86BWxwfoFgi4r841EBYhp54c0kgTRjS5B
Cr7qzfnGV6NAhieDhCtr0VDOYL6RcQEEM1zjhed8dam/38OIfGJKRKjS07jKGFCIAedhNB1JWc9g
vGWcRUvMCs0WKp8IOY0yEy1Z82bhDmAupP0NuDY9Z/uplLjMUO93M9A0VPu0MnpiztRcdfCwOU0B
IjqkcnHXzMNGgPpPmLiA/ZrgeNO8dXxXCsfddt+55KTIWYj7JflWXeMAT9D9mF5PxCZaM0UCgkut
F61KJ/6sYXJrxZt7x+WvPGDdRj2RDzoYSub9DGtocer9I3S9QMh+V4mK/9WN1+kLlfgt3RibyiLz
mWfSN6UHU4BUe2g4OdxA6AgaEi3vOKsk5NlxNbCBvdsttNUjrQtAgRbxPU55g4DMfvSx0rzfvvmr
JKwhR+b/HPRH83kXksqBHAcIqFvMJxG66e8YRF3RQG3kQixCif64993L6hHrH42awoD3ZOmfgyvT
lgF4YzocH02SOMyMLef2pdLwuAeQh8gLRumxGyxRem1QRyIjqHouF6nbkkkeTKiRZz5HGs4D0OBF
3AF31c8Z0sJjgaPbDtQAgz3vmXgOhR6ftnxxaRE4/DeqQKLM1ZAgqY/otVNtkmvECnxZL3RQO9Pi
kS0e+1jGqw/tZL4K82xDOZpEHmr37zXetu5iTmeJ43JMdgxJo4tro+i3bLtmQFLAjIOkXQkdmXDN
f7vTdxMrMnD9uofrSFGsZVGahU8eiHwGHgHWONZCh5nBHu0AIb1Mg/gfzPgEuIG5cgopIuz3WIKj
F34cNhdillaiHOjYUoXmogAiY5UC9+nSFJoXhXc2EklXEXcRvLZppGdlHWdj+VOQmjx8nGPD941k
qRfKZ0zm06vv3VN9mevoW7UAgObokzqok1Hbu9V98zMjlIjARj9Ykzy9y1cEGkg49o2Kwf5M9Y94
n4LXdXFau4a5t046XffVAsyv9rE4GeAlFPiAHrUZr7ZEQaddfWUbroZYvh2fLk43KoOaBz3w13y0
4hWG30CVDlR5M93KvTE5Posu45yZ60oxfETrnDqnRXel7DzULWcQkYu1RLf9NYQMhzaDsCYUJnNB
oGrfUTkEkIwfqe/o5dau/BUj3aWHsxscr9KrqzNPLmV5GljR2TK4viQtYfaMqCb+mmmSZ7ppHilq
EGxmDAJ2A0ie+dFCyeVYu8Fbm/dQx38BBa71oabopu/HhxHCbb1DCskgQGvx5EpA5JJ0zp55VLZ3
sYtC8DgLSclXd0LzUMjCP4niZ/+e53nOMr0BaWeLJSYu2vq1UkwC+0HoA8Yd5A1fbEyYDgWpCacL
GHnUJZrKfPh3Nwh3Ed76AuFetq0WviWX9BBfcbaAHMMSf3RkAlQtCO5ELPGi77GvJaO4fg+be0yP
f5Z1SEiWjNeCbSrsQaQKlUAWpSbRuZ+a88fH9OY00Ad+OEY+i58MkWgSKAbqdYyr6sNG4toJLjNN
nTIwSUdfLm6i2bARdQUvWYCYCl76tagABKFv4TopG8zgrVF3bePFWW3n1GgLOgFXAdf2ch+WpaAM
M5c47rOT1Tu+9FyphTze7o6ASFKYfsFElUATDFMfeUA46w/tPcp4mofoF8f1j5yNqjfaau1qU4o6
e1yPdTpCZhfiP9Gzi//Z4YAOWts2hRpuD2cNEWD7Lvkm2sCh9oO+K7VNIcpB3eqQKemEKrnrrtOk
g/RGNDEsUNyLIwB14dqrCrgP3bxlGZTUaUyFnyk/SvbRiGt1Ks5vpQjE4h1DmOrYbjLGwSpkKUzh
Toe7d5ZYhBiz6psPNgtmbhWusowV0AjefcJ9cEYZUqbYvIkWMeUgoLzfJiB25FiFOsdLFcZQmksH
ysIkymlWL5AJR5kg5A4m/eHpjWK0kBxKVsRhdiJWqmNziUN1pYOMbCpJAihVsCqr0yLenILguZg9
fa4C7OCwmErwurV0OuW5t+5m4klQuNVX1cqsJNTI+jY71aV/fcncZH24hT72LwkE1k48/6o1c7Cl
RJlgM9YvmcoMO/g/IwslB7rTzPpWPwyfkn5NGHRL9yqWkfII+8rVzdS2Cw2BoTz63thSkNrASIWj
Zku2FQt/cSE8z4PH+vMrrnGcoKikZCrk6MAMyeSF4MSng+VFm0WHcE6ptDHYQ6xnw2pWip4QLuPu
AK6newKDBuDTP//H5fkk29mN7jJdjY9dPQNorTXF26FT+TiMhJjMGBEI0ptyt1KT61V7ckzOaCRZ
HzwZBOW6yf+4frmO9NGf603DuemF1fTUy8HfDuwMiDZleHkUjyq1GajMjjaBk8gI78GY3Znk9CsJ
HtuGLm5pJ7QpSjiYZJS1PP17tQFQsVxijT2T81QJ3+7ofL5CcLadkzyLxOI84rWIFUbGE6ctNd34
7gvTShMUMtWjDx6SojKBBDIqAtiugRtnnuVYZQPolH+XsX4n03Q1atMA8vP6+K58sVTDUwjWsriF
+wCB1im3WoyUKePrBdx7qy2nryQDyc7x9civUtBHgDwm9ihcD4GQeq+97GdQairzAdttYkAF05YV
8P6AdCxbGpjv/6CZyN3kimn5i44peGBnsazc9849RREKhzIuPadge0xObD2PiAWAmu6iCvu6xuqH
+s5zCCHfrKILnJf+MegLoHxb3ZQW+7klw+a9fzkDuO9r21YD7tI90yPU3F9BXDgvYK49qF8yTb2T
xT8t9LEr4a/Jmr9h4oea284YRLmBmxKp+a9pnLb2vf80ueLurN/WJNVzAaw5dngjpv8+BZEJIvmq
b+Co7myO+XZ9mTfGVhtsvECu8wsDrE8iejG9lE23UYpgg0CKWIgIU9cS/xVWm8mpyQLcQSGbtETT
0qHGfKAraXI9dw9NgT+awu+7Jhp87LzWEKXf1oxE3yVJJbpglIYsp2LqHvyXa89vQcZ+PFc5Tyxz
c7CF00B+q/lUN2M/kk/ps6GvecX1YkVZBlUkJxlHTqfaqUKzEDHt2u97/ghGYBv8xqfs3jj1du6k
GKoWhhYXaq1+LCb4YQ2JoFgiwFb6YFi9Ts2jCrsN4F2q8HrHAb+BfYBs7nQSDc7c94Dy7Vc2RoPo
xdqJU876t6LvTRyhJuO62tQ3Abenj+AzMwvYqhsEDG8fGOPNiyOxj9UI0H0U69RjhF6oOsTL/EO6
v+Z3LcPkdTevatI7LdVPpzWIhVWxdD3I23oWeA8iKhv+xWyBHaac33IGNYwMBensGIxWkzx4Ah6k
weXymyD31803U2jjNw4oyrC9h003olzwbRdmewgVmr+NdBf7Bw4WlZNCyr1GCfJsGQZqVL1lRNXZ
F1LZotHnpHxsgtvvTEk8BHGlhtGyHhTd/qsEY3gK1Ju619yt7bYOzCyp5LUP+o4sEO3ioa/f7Wbo
w7vE73Cs3GKTN4SW0qh9b6wHDnmsaiohTXRb8AVM6qHmPSSIJLHoG+l9R1AlyGrmKTcC7IX17/pp
QKR1anrpCIc9RpeNDYX/jw393xEn+KFlPsMuTUFfUvp38l5K0OINa5gvNRWKkGc2ly+cTQ1J6e0B
jW3DJmuOzyrqrtYu+0CNO5B45rYisUNOP7g0PLattux7LfGftNEvW2XlJEK7ZSkAK8NN42YvDD4S
SlhDcoqON6a1tMafaKzvU6ASrS1FpHYWnePW2IAkrXPeIqtxAVUDJh++IRH+SUqiRhFNxDH62m7F
LclQD7VIirAqnx7bgC5UiZnBVUn9xGFZELPeRBeBM8Q3uEvv4/FkM2qjMZ6qoiNtg8ZGGEskcOMV
stO7bSIeUVZyXjmxDZTaJlvx0eB++gKbybkxkj5hEZVyyyFCtdggW58J1sz4yS1sK0ucQ52d1PJg
i0Dukyq6W6JgXhsXbiwwz5xKVCg/rYDbFOaStvXRxdXyWKumSFojtDoV2ISPXELcRtWm1t9pyf7F
PIVcrh5RZzGOCCvnUmbTwNy64Md0LguTKNQKpY9tfX9SEVr31W3mJ9/afK5C5vwfoeWusP0Opa9e
ppcgkIB/RLGQzIp/hHb0r3vfRF7fUDpZM15ZpuPyc5659vGa7xb04l7zHMoWkt1pH81iwUhW8GLW
nm0XbknaFM49bfQy8vpf5mWaRzQ+XwoGRAPE8mSEqaOS8RcDebkQYYS66I2rfr0LUW3U99QlcdKJ
tPRH7tv/rj2152wRLauV3YfZ7YVVx/q3+RD13n9TBKqiAIxP3Kgg1wTsvRq78Myf18yHM1sTcX5t
cwJqP1GzzhBGP79tgQEwM3ryG2kwnz87D6FZARTZVbhjPlmaiuheIWWOPVUZqxD10iTvQyRtNmi3
ARsVw6JBPY5zL4VKudN4wZEbOwIRP3Gx8cE6bDa+9ytWSTZt0+arErBmmzkhXxfDnXvKY715dZII
kVj/fjCjZqN78Il0GroZJo42EgJm4MkVX9bmtAK/Y1u/1cRtx4NHCz34VpSiYXmugqP4EwR2Ovqv
HB4D5stZ8JyPqWBWkiLrrtyaUECVO0f5KX3pm9eFyBcpwhRK805jJSlVqybMvLj00cuIYFVUQiiO
Gu6xPvz230iFX1CGWHsUo6Mcp2U14NSVKw3cXAddHE8xE4YzxK+gORWoLLOhXEDbhqJsSYlZvGiO
JI7aZ36+blt6Tl2IZjTh+C5zQuTL9ZCuSFtCq/C0h7/vuYRV0iRmAB0th7+1Y+taSsak+8C2nQT4
R5dtgaQOB7pLbZzBJphLRUF45AkvNEvbo1WRTVmsY1hfD5b3dsRAh+pfreD4F9e+0R/WT18N7zBJ
IkfSgKPyAcoX9QbUTP/t4lDgtAc1M/YXTwV40bK3bPtaRZLiwgSCWbPpz9D+2JqCdZ5wxMBu64Lz
fDm3PnZkzVVkI1byw/eNcaXSI5u0HdP60s4xvbapyw5nRx2y9X3ZZctnmhFd+ZBPn0kNVFXiVT/r
DLiFC/dgNlZR1E8rl40u5ZglNcjJ2+65NdCHVY8v9Ev67cNTacPs5L11clDBvT10Dgx6mbA5cM0L
9jtvH8eHPzATDNs8fk9Yd8LS4IB1XQrtDm4igwfBYhpNqMlu0A4xADoOXSvc+Y9BolJpJ8PlqS4k
sMhcPQEvNL39uZ75Luv7tnZtPuVzDtyYhxt8Mw/AkuKVaCN2i8gQfHbM8Refa5qf+Ge5GXIxx83X
N0Yan3DqwmPIU4TYbJ6v1KJMiq1luVsPmAA+aUCS/kIyJ8G6Swy8z7Fer/edcTwrx8rpLQNlk3Zq
WuR5p9f/XsGhA9XZ2uxLpygOx905HtKs88cp5q8jIFYWtKEXKuMil6WaiH10A0STZYNcXaE4j6jD
NZWFXRIlxmQrwHvLUBSqgWXDWJPwVf27zs1kEfpqfD8iRiJxZ7ZOkuIOXLszQh3piRYKH91iVKdl
7QjZX/AozIc8soe8hLK85x1YTnWYVPzx44hej1OQ7SGhbWl7a2b/y6eZ7SPj4rI7Kp707BABPvog
tf4tUMpDUel+0Wx9quPoRxnjzAWaLUiGtY+PMsTgjTVJAeuJxc3AWdWG5TsT2BvXObKZEt5xBYJ4
O1SP5lAy8RjjuL8qM9VVeoAYRuHsqlkjjdxdYJOnNLZxe66Wa7OnPENyCJ6A7zf2pbAEpivMlfWX
YOCxoLvfK/29NYEYkp78SH9gp+ec1L2cDfh/3tse7C+XdfTGpvoeiPyQ9t/pU7sq1lVBYzoRs34S
25hF4xlyrA2klM8V6I/zR6adsfx7cj2AEEeYakKzjwlNP/tMPIY+dtF+zu/V4DaYHNB8FNXP6jH7
nXedgjMChM5/opUegSiw0KkMcKH+kzVyZR3rFNPuekeNR0Vk0KbvnJm1v6WIXPy7kwOi0bQwhPgN
bho5d8E+Ignte4tS6p/MIaKIizNh1Ka0INaZ9WDdfLJoZ68xKdZJgDIpWu59wfnEUjN+mHinf4KL
D0fBcSyFKxtmiNf2dAqczgZQ68BuDDbtTenjdhCeWhq1yecIkWuKi9Cdi3/k9bDJ+/vZmHCRMxjn
SFS6Ui1x4pi1FSXKVc3KnhFmaGDycS08WWK6kHOr2O7CqhW5d7+Xx6B4v+LxDdnA0UgDKYsz77m6
1Kjzab86MabHS6BlCC/VdiVCbLfDLM7hwJhyudRI62QLfsclJmiMbmPr9GP7iA8D7phYFAvuMT1v
9s4pzZyZxQaGCyDo3vVJTSljxJS3vLB+jADWxUUWJMBexzTJ91n50gsZmXdA+o5+pp5I31Vks6xT
8VIk6VDmMZiCvdvuW7fvOXpEOlCymncBYpTQdzHUS791Q/uNkd7snTiXvRWD4LubdJ3VVNECN9GX
8yeJzZoXomO/WIeIIUbq46pA78BALt3hpZ3Gv0KdhXR2xZ4767g0LNM4gH0FBflZV2h2vzmO6tTk
d+PXfiN3XoXCgJKyFXzFJSQ14Oq+D0i94UpIcelVtJSrfRjnVIjoyTICD/jSiUd7bEa373NyuI1Z
EPDTvOPaC56FsMtqvTL+FIQZ/yy07+AGYJ7Dq4WYLGjb00Px26n//amWN/UReYqJER7lQIYgfVAW
InL/W21pzFrFodI88haPAhQJKNjHnrnSh+eQznlNmKLzDYZM0R4jYKL7yM+OT4ozlzqqVuuHBlx6
00azUUluFkwwsBUluWZF/ieLkzy5nTsecMHomf9kOMkFtTOhPI8fUnvbKIYovNVtdzXSzTTp3CwA
ew18/qR4rqjGV2/dgGkO4uX7Cf+bBMTtstRQvZMWr5xCRzNNszC6pTNpBuz0ARe4go67WIwdt1rg
lczVXquEaD10nJAGdMey9bZsJjLbXOrqD6ngqUNJ5h7RzijQ14TYF7jT/8X5Qc2EXsaZV8DWILcg
yakc0yOktJHSpRqhDdRH6e/qgiaIQzjtnw+9aqzvav48MXpuFnrgLlw4HRwY2IWVFaNX10bCkRnD
BiQ/tLG+HZmmg9DOn9c+UfKQzouJupSitCG4H9GoHllITor6eTeCX0K6UhdoerivC0Nw24K+EZG/
Odnuqy6qweSZ8ueP+XxE3tjLKcpZjeQezz3iwLfXx0ghfGJHSvnhPy2oRAAa5HUKgE+Eay7fi889
6crA/1P1NREyh2cXvEljz3ww42C8/aYShrqIRW18hva5tx18DW83Hmfuzgh+lpZGUnHyp2TgipH0
nl3QIke3l4TJgP315FuverwgDaqdr6xnENa+4r0KPfFg2aMOHAQq2o5DIH+5pUBSGoPnZmhskb4t
wDjPALsSlZNnYUHyNqzPf8aVFn0HhoR2Qp0MzXq75o7K+zDxe5EhXlX6GCvrGCoT34l5yTeEo6Qv
Sb7T7j7beM8exT0cmSKLi0qWfyPkDqiRqPndztnOLcjt5ldZG739rDFstWqwEFDCcmxaD2pIYJMh
SZ335qCAiXoNsy+/zY79Vv1P9XMN47llAANPPPkSfrLQ8yfC3fDdTrpU519U1WrFs+19TSEsTGKz
F261eFK2g/5wXcMS7oaD6CxNTuqXwlTK2asdqTrDnC3BnQ5Jxy4peyVOI24MLX4XctUMe21/+gfb
3832Avfk1YXfIe7hqNAhLgtTZHA+By/cLzN3iFN6PlGroyWjpKAG4IJal8bPFNppxnmNRBphHCgF
DwauMnUfh3IoZez6Gzc6ePXivJDO5dSYQYUUc+oB9+7+ImUQfAqLiJYRjSBumR7jzkxZNeaShnpg
/a3Va1L1BQ25fOYZccZOKc8OFl1mv17cAopagEMs9zYEF8KQ31z0Hk+u0HtF/mpR99CTMIpkX/Mz
sZ4n9pf9/c9/z7Vi4bV6CN+H0LsRL7uFXS5cbs0PJJ633tU7nBclG8ZKNVwFedexSAVXVvVyQYAa
mr6lXzBwqScR/W252DN7H1izbkU4NmY+y9XjJGVQ3tZbiRnwn7NoPVUTySF7wgLqeuzaXjFYqI1Q
9GiAAPek5Wd31j1VUZJZ2quEDM8yentm72zBJpr3g5234yefn8bYLlbsIWxQJKnWOiMDT4nFmXaz
7AtkH44oY1TArMIcOCJefsQkBdu1FhdVjt/EsfN7ACenii8fuzMt5ZwUR4BL5kFll3dAqxA+vQRr
QkFjjfM0qIknJSR7l+5EuGWRohJzRebThfJE6ZFHczgGhWSMRp8CWFBzMBmfy657/1SWhNtAKC/8
xzUwkx+crlEafE09OVenSm+sZiQSP6VmD3YUfa02NxnhIdP0ahtpMDrnWgOjZtqL7HkjjsD/H0Bk
sM0F+deFy2rnBQvoNo7kxddEIwigyy8Es2+HVJnqdms10ZeAGmeL5YTghWc1Kj9a5/EBDZjPVUVc
s6YZWSTpYfo4nPILxcKGlG1O0qJqpBTn1RTkjYf2M2OgcNVeZpVqdF/W5AG20j2zilUmuIH8tSb+
W4QxR7qC6271mg6oMtsRLE3uU6HQx7wyY+cw2et29MHZid8JB8NNTd0vKws5OZ3EwcTUtm9VRuxr
fG2f0Yx1GAE4CHw2rk2NBaFSmJz1T7rTgUe37cnoC9fNXKujJ+WI7edtfDSHM9IqLLJUHU211yYL
QjwkgiytmExQ3dGmTwjePVvzWzwVruwZPrHu/hGiiBL2+fc6gvh4KDdotPjC3uXwZHZO2dpdc+ZJ
o9BupFZFG097bh8QHjS3VS0Um1ME2YWixBIb7Tot61JBglOO9KAtP4BQEFJcrzhvaiOSatqN3BcA
W7pKlDquBZMXWwXnVPVYv7dx2zcULXfvfT0Nj1JTVb+xmqzG3I3qh4Wj6HR1x2K/Uv1wqIiQ8RsR
UUg9XP6t3HJMzoQjzWTKiazfiaywFZfsI53Z09u+j0WomHfdurg1v2oMkTcFzhuPQb+VcEw4QD30
QQJtkjIv7LDutnPIkO+pvhNXv1e1+07XXN3Eo5qlKEOrPMjIMjaBoiCff7kkSfQqDpF517PYnNm/
M/JxBYRxIlXGqewJKvHkpEOmfCkktmEZbikpf3DjokjNVIXTX48H8qU/Z7zEHtE162DpKfHLJ4YI
B3Fupal8y8IRmkO9Z2y4lwBN5QGP0Szl02RpcUjgZZJlqDQapKYhY46bZ0Wd2jesqF031dCgcEtk
DJgo0fddcm12YrVnhDhqeEXHuBaeb9rD9+WBs4K3EG0O0xL69nTNcZOeSUuSkXBERyWcTCLefndl
MS18rDYA1Oqfe5l3SgwEpYnk5M630KaDh/tW73R7ysDpxjXf/tCipIVfoLqxVpSE2K1BzKrf2vIp
qC5vJM7I7LWboZj7j9AM0THMwbclNLWhlfxbT/k8cdH/mnpbgUk+sCFck8t4S1Nn3lhnS4GKB+v4
bDatSxfqsTiM+KdlFqChOL8HxD4zYBXyW1LITYnFJp/dMSP21b0faqf+8QAGcBzE75A4KYgEw+LH
IvZ018SDKQ7HDACAFO2rGdPnMq/FTrAgh3RKAPthVnCrisN1UBkelHhJ+lDMEXUKdtW4dCaNodwo
n2WMpDaXKyB+cMkuFQZ/8rHTtLaVr/gVjFNUBAqpVcQWvDPF9WMz4DdZ5hxDkA4LFA8HXJMa/N0q
GdXDKSaPzZQWX9hQrWKDP/ePfMr4HdmgItyWs5zOtntl2li8YDFWalNcwy3onDqmRO4E/M13YMq5
RaKE9c+ilotkBJwpX61fFwfH0194ZJ+JRiZIL7JeFimVlG+H0YNAX9+MRa5XZrBegAUiJfXzQzIy
zKJIi/gB9x4gSam30sLR6p4Ec95hEM7dHQzmLOUsab5g9Px0/YMFhcegRUcTxYkZMSuL4/R7wfNs
A+euQjMj+AiFJxC4t5/is1s5qt4SHER/JYRL8rbOTYQm8HJIXl/dixdRQa3BllL/044gWKAOZOEp
wTRBDiXndDRXkggMOiGHWKIM/7Vr95I04EjuElewKyK4M0/luJy2e+BvEaWJs6sTDq7LzsVauuNH
JdDvJhcvYopngb4fQh+na3h00YNvSGnnKV9U8PlduEGCp+bUAEJqNG4VfNqOfaZV4JMMljENwvMC
6EgII4Kd20b2qxf266kui2a48AnTBI1BcG4tAPQreEvsH/pVpiPTLyaX9ZiWoeFLhyu/YK8oknwz
bDQIjFTALPiLZSu4wQkmPVg2NtmADqFj9iL7OTlfWb19G58nrkB8q+3NtjPgVk3IW3xrO72QMOZ8
BViJsJf1fgYFJmGXrlf+rvdMU6+LvoYATgb6tVSceNeoLYn1xkhwjdPWgFbhRgn4KBc+fsfLv5J3
sfzLrepvz5W2Sxpam4jWQrsKNaTUkFJyYtG8B4iofYVJokYxPTcpDzfQJyuY3uGoeJ9hpKFs6J1b
s5x/YGythH90Q0l99HnIxbVKN4Gbh6CzY1aVA4E8ckY+SttVkgadqIr9MBo9NwPGzEWcgKA/T/wN
HeqRotVlsCAQ+dX/rdnWq1tfTC0EWiVGb2Tx97DeOVA8Ytf+pB/fvguH04Q5kMXjkFeBMS7X8A++
qxcSGkeL3einFW9JwYTxgKz+T06EQvPL8K/aPl86oxMG+pzKdPSovJA6KTQ8RgQSqKQVx20G6p23
BSJQ+GqCkwX9q7HMKAGVmzMha3/T7bcUdDRhQlMieBShtjiEpI32R1hnecMQ/Ali2cjI3fdEYrw0
i5TAOfR7BDP9CeZIoe2FSucnZ410RbEIeGBhD5c26/CVFBniyD9JTdiMSTwZAuhxgy5iJMXqLPAt
02BhH2SOoX8I2FuL+79QhuxtL8nXfjkngIhh5E4oM7bdMea8n8yFhVRfkoIkzv0fOEqNem6oC7ou
l8SQ0xPVZ3XDK6LYkMC9v52Y5A829FpnP306bU0MgFYQRqOfi3dL59waxTaJv50jp+hnMgqhNV/K
CzPlulBLvDP94w552Ti0HMfBaXQzl2fEzPxP2VxleG21AsqVNLfUF5rBlTF96PU3FUHDZz8X34fZ
L/GxUqbwYXs6tVkgV9m6W/3b3t2XJ8Ifl3LUai86jrWQlLgesG8mnd9D8NRS3nj0HD19XtHY6PZv
3V4OgOSNznjNoPnedK+MDbZYqOu9BZIZTmSRaO2dCL2BwV6H3+FkQ/OKV1galRptxtit7/th785v
SDBr5PttQQjFf8hx8R9KJFKH/dr5FK2fIzAB/b7AdKTMnjniGA3WnPMCKvid9Wd+SBYe+oF6cu3S
EGkCVXk5FDT7XauF8DVXiYAv5MT4DZUbaMbaBPtfhS0vMC1vXYRiP7Z3e6z9yJOGnqXeu54eapS1
6pDx/NtHCDgTlFlDAOxb4jhRWgwgAACYkivLMi9T7mYquNjx8q1MZrhNfWZtDl4ZrwykVXSxjP5J
gU5QZT4ydYSg3ZL9y9HKMimIHvZP+xihnjJcQQvpf4z+A6VLGNA4swHWHQ9Z5cM0E0YBMPHUUnCa
NsR9mAX+YiNFrKNuvxYIhvoYkq63n1Kd9HJjDKl5rCdKYedZ3ZTB4dNNbvJTcAFcNJ/na8PQs9xN
1aW/0ffdUC9aq/htQ1pR0VzaDvkoWv8pchLtrK0qFy1sS59VNx+23NlRFxXGuVCfi1jjSElIRvH8
5wA343Zvhm9K17zgZTv83qhc6aQk2OBOs/UAjLLb34PSf0ONoJytkU9ZY+rqXnEuur2Z0UuDr7qk
EPSyGr8QkuZv1OhJFGoTTJo8geE5PKvnPx5XgyRKrVw4lsmzsd4/fbcYXsGFgoQl+tvkaeW28oY6
phG9iwVLUmm67imSfInqzzUU6wfSvkcsW1SnEfEnZoqyjY6Z60CmZcyabUqPIkSY4ggiGVMIjco+
EudmLqfsLdOyFCtVlanpN8+3aw1qJbQOsA66QMMnusFUoFtfEkm7wNwTgdcaVtFwr1msoAvQSpI/
nvMF4piBzkqU7Vs7H0c0L6XWK5lgfTXftDF81udji+mwJQVBWq6Z0ilXFP7G5wcXYDUZ/E/SjayC
W77BhhBQKUv3RHkzPj80c7Fd78YaBkN/H2Rm9EDb7NDkSTodD1hezabRO9FCIviJcr5ChMfNid+x
cuiNJ8wdSOym5pQppso91OqWIz7V4Y7DNC6GfooRYhMEQpBJw8+N6/ZTMFJZAOcvr0hITK5OTKPj
wX7lL8lXc5WoybazJTYGh5Umr2nyVuzyMyRoZL9KaDJUxixQZyI4j9CjdJGj5YbvdBaIcfUbnX44
sOj8BqykxwdUKEMtXt2seBsiePivsrVI/+XBEbco/V2ez1eCZ7zjM9KV3zjcBcZ/HCzaOR4WWY+9
Hu9o7d/0oeoqZqtM0bWRj6Ed1IF5aC8X4z7vHZV3pN6LBXfzMLr0agJBPJKq92ihkLBa8gpPcnU3
3sbWLJ1XZ4F8m3Ky8IDFpb8ew3iD7lfEVI/NlhbNJPKndD56mbZcycwncrEvmU1wv5J131WOhXP6
2kwH4N3sd81YHmV8zb9xiH/UsoeW1SfxyM0ScbAXj2PC3kNFsM4a79TOen39XMKApgsTAWiemGoE
nwNZG9Y+xBAVI53SRFF3UZDDRuS7lX8mjzZqbndMUIQMoScKb3CCbf8bd0+moK8zKS5dcQKZGyUy
0xnKj2BAVbXlcff5ywcCPDgxlmoljQ6RGoomDXcYEl5af6eZNcUzD1vCBbTHiCtdKCtD7szkUg0F
NEe0KkfDPp8ElPbOD7MjLMOqAkAvyQd+SVTyymjPPGUhQYRLHsEJKbBsGlz/UvH73WJ07mO02k9K
zAzkkuRThONgT2BNMlBAht2kGmi5YV4PTYgIIPvEXBohWSczwpSDRE5f24s6Sndpj5AQwG+37lZl
EsgGANV/K0rVCaJDJ3oKTqZfoPnEitJ56xlito1KHhYUJKGRGMNoikMo1UCTWDS3JkbpRg8Cb2qX
lF7Oa4jdXXVoAGdFag4EUbGqTl22PAyK/sT92eoqvLKewFTvTzEiUYgVAlqxXr/Y9lCggXubPmb5
LRuU1b/M9SWgZLkQ6YE9cXZ7RYOw+Aj1cz667TEju0lcXKUkTacDy3TnxnYMsclv5paOHhPOH5Ro
SwRKtUkK/NZpb1Ybax7RM+mZHAfrUwxUoZlUL+AtMjf9acqIdTN0GteMG2uIubTn0KcNorGLf10T
tKNE7WH1176rgifSt7NPdHGtfjtkpJKqEeZlmMDh49/Mm2s9TTVjSd10p7Qss8/bhc9AnLLggmyy
+i4ba3d55zlm7nBd5gbPEGV2fmbE4TtIjla2/fl0puHkIkxzoC8KSc27ZD1qcMD/5eEs2+8bHK0I
aZz8Dyq5JPpi6vuR6iOuskKhCoVIYX7ZqHlsMMUrPOWF8scY6TS400qzo5A3cg5hGCpHCQd0OX35
B5WiWf8gidEbcyIWzQBp4p0n2KyHhpwio3UcEcMorYsg89vIG+p+OwutYsiJgLiPA2dgkXdC+roc
7hQN2KJO1khZnOpzJtcMQj7d+UTCgwqqXRBRL9EKc+AKkfjR+OU3MlrZKIseBXlkPzo1qwuU3Xpi
JjLmPd8qzuIktkLnp1hLnp4wXlTbcPYIW5EgL2I1rLDsqCAPduu7tYo5oRq90DHm6l59SdD+K0ML
LNRb+aHqmV7Cxfk4l3njAhBlxCSttBHsuodX7BI4jhVUvmxKNnh1f3FQTwc8Nqy2puA/SRCfDYX/
VQOKA0+iF3jpSJYT4xjjapQyEziYcu8qYWHMlcp5PsqQCcy5h/XNeszsENdMWhgxBhRFhpJE8/ST
rzr5OMf/NdLrJp3Lj2m86C8V/ajXWOVsloUrlxVNVHnKUcAd9pNfhZ6TEuVv9Cromt436UpZbIjV
z932lHodBv+PsPsGtwOaNQaEBdihF0YS6gCZwXft8h3SY/F6lcthkvQC6byQTK9WPgDaDqPvifZw
YHtqbpffTdJmzEN6EXNoWj2xorPrjnKcaW6M6tHu9vKjwVsvPSUrjES7TOp+s4cv/BEzXqNeuWSp
GEANCAxDkYqX7J33EjfjhkpIb/JUBdAJVG+Rhf8EDVeOumWB02YD3eI8PFpjYK9/HMDFi3njATXN
/58uqpVj2MxXCN1n7B1i8WnjCC1yKO/tqTZRE6J/vgCXtYx5uW15/nOlbpR757OIVyhfFgJYhEhw
0eYAo7BpUYBlf3/0gAslfoI3QW3b7SUYg88J035AlIWH1Pd5wW2KvQDMJjt2qtPmjuTBRyICDyfm
CvsrJXdvXu7ZSGKkGI75EpFONDSzZCG6wyjrTXyBj5aJFKBSNfgKLXBNmmnP6mNqiTw5gv0Vz3SC
z9HYs8hbSeY0yWJx/a4YepBuYoOFVq1bLI/okLoo3aTnP2RBSHkRPK/itaKAeHFVxcglCP3O2cFv
h+mYaSaE4euBmsM/A8qr0blJlBSAYNVhT9LR1DRn7hXfr44/XovH+Rdggga0+aMcaBwbg32Nuwsp
NGDqB/Y3b8O7xPBSDHIwEn9OwYp5qCyTwFI3e7R0XDxQSlS0oiZMpn9jQCbn6jQANfd1SBb+i31f
w+mCQ5gyXh/wyT7TRDjsNVVKkGwpPHSDr2izSg7eDGoZOPZnCfxPvlcB6VIICGAO084PTgaCBBT6
OTN3vPRGAUzobnlY4YpCIRtuXBf7EmUeGs3LnB8G1I8jfqaYduK+gz8NwJq5Qw/+aXpUkk9tACtr
ZhOYEvVJiMqvX628BdwKeTEMlb4YsVVI8tPxhyOPEYWAE/a5Si0sVbDmT9vY1R5FuVrYdMpY6nUs
CZZMlHhUVCC75k2QSCZh6U8O9UwX+jCHbAAo/8Wv65ksQtFT4vCb2doC3CC7WapWTSBg+gUF6C74
dH5KsQOIHBDBXe4DmtTVTwMcDkTHp1DDj6kMDjKKPoMDU9N2OVms5lJDkjjuQYSbbuKsNc0dmvpi
vyf/WO8AcaM95MguwtCvyrKvOsLgHWh2fJb4UBN7EqE/4JwannUEB1bzWn7SPzEAIxAA8WhtpIsq
h9yLbCaUZjV1tChh2XADIKaOkGJAcb6mryVq297xRO6T5mvwEv/ksX9Qe6FTKiLUq3g+HQyogUaO
vGeuP4vjvenRK/I8P54N9AUy5Rsr2Ngqsg4tuJVcl0PevfKGr5q4Nt0NHCqcJ4Z2X7+go4G8sE/X
A3IRlp46FMLHIjNcfm70c+1IqFhig6HBnFd2FcVajfa5Lo4BA1+8nKyJY426JRmnTKH7brZlvxiD
L0YGJijBshKi16wyGcRfsXd0DKrJ4UlvojHk3uh6S+b5UOyOmu1DssiIKBi2YFeYd8wuGbrR/HS1
pXmay1KJkIbV3/Had/hAkeX+BPouKtAqxUi9iRoN3nAFp5Kq1d8evU5nCFvhqaxOPxUrTgJ2FH/t
uaM8G0wOjqdeYtT3WB0iHNdJsM29SYfraz25VLbnHSX/djwhH+VP4cmbbc3W1/u7m1S1qhM4nGNj
tPWFzKikbGTKecf+bHeB/GsQOU8KTAtMNTh/PxjBoa1R33joCJFsfnbDC0r6WwXHwudSQ2vBgKNm
eaVExj4wbRxNPFu5xZ0zeh//tDeLZwN251vaaBk/dESog6w3agSoVO/Ci+itZfcJr2itlwSA/i6h
LVrVaY7eKNFMzaPPhZngNiCutX6ReVQ7ZAwN5qOTN5teJaal6Yg9Ot6zPibIBO8d9xCUlmbLCvJe
X7PxBHp7sUP7KDOFIsr20onQFvyIVdPZQhBOWdkiW4nLZePOoUaFpg8dAe8RSqY5d4bfuMtudCWt
sfVVUma7VKQPg2QYWBZAOyLhA9m/41DFof+5xeUTZIEZbuY+kYdvaIR+DIeU5vhsa/DkqrVQkZLo
200LDan20abdp3oOuh2IXlUhektmd/Rwl7VpX+6eyQ6pioRHF8kkDlhDyUE3rBF+QJMTk+m467Km
p5ad4QLgws/0QI2B4T7to4nm5DMwJL5e9ju2x/bnN5NjvhZlKXPUHn6rXMljc0R41Yih0sr0NcdC
nN3hPX39a55yyipMSbIWsj5pT2CsG+7W4nAEr7SquEgbLbQ96zxaAVxVuBAZQIiJr1U+3dUTzNAd
2pIzxA70VKIiVNJEuM6GZRFg2MpTpC2ZZhLe7/MZmfhB0W9yrCrtwU1LocpuCo+W8vmZ6FqKMReW
oqd9RR9uNTcJmQMvdzj5lNwrxE1UbgENCRHX7gLbuxxaUzc089wwoCMw3Sk2rsOqrz9aMnvGk/DD
OQaAojwFe55X7HEAnaRE5E1YU1uOVjDUzQ7eC0gQg14zQEGJ89uZbX3jXd9mTMriNjCfDJbCLa1x
qj4jd+fEfm16CAnY5P1kOlq6ePQR75jY/Tr9flXI+vD5dLPU+vy75PGgkR9ik6HDVHLTghKyTpLI
Uo3gsZo6heG5hQH1ZNppfxh2u/9vB48GT/DmvYdKEuKL8c007o/vQ0uWjefAYcf3EcYr3f2E/q8E
5IFCezUDgSWTvt/taJFn07JTLzHVKJeATTl3Egp2SwAAmZc4/hPQ05tw31HKLC4rWJWbv6bPiBsL
oLFHRGGJFNb7MV6vv/NzC4MxT9PnDnTTacbyO4Dk30+x7eA3DXAanNoCq8c4n5zLsTxSh4yDjVdH
sHEld1KfdPcsK8SkX121joFS3fhAOuzPqNQCzr8WdE8bjlQuRb40XZNak48CmF7nFAnLidjRN+u1
83Ylt0qmLabvbsFimpJvT0lVu8avLg4+w3KcHs0lr07FcsrlSggsxGgaVSSimK9brLEGdRuRMhlS
Jt8ubAfeXo1JWd5poUXSHsoMviaG471gI5207kF7oGQWsuhZZC6g98hHtoHD7CElsD0Z13KGECas
Zues5exTjqExKquXNjeLNIzA55f1MZB16puo5KTyjOa38eQftMte79DmFR83b7yQEuxKV1XZGfDe
mNXvhLvl4cQTHtzfsjJYQeDFPIdFrr6N5TYrkZlE13JNrX2GTeSIYjDi7rB14ofIWy17pW/UnEi/
svRmob0RgI+wgye6YdZWq/aELUOlCg1zoQJ/O7ybQqjruh4nNStb0ohlbISdm9mMnNL2vlyDZ99Y
VD5dm7lck7kL9dyG3HIBY5RKV5jDDiAcNF/9Uf1SwaX2PofC888p47wbx0Dkr7WBBWpGNMoVD3Yy
IAn6ilHTJoA704EANtofagyd9wRFpZH4LLMWTneZvXXBoqXfXQaagLKEFMP4SkE4goamN+hsdDaS
KzlIC6d/K+io6ZZs7pBxpTIiuiqP4dhJk9S0c87gDo6khOCztv6LV+xuaSr7YkstivZlfTvurZeJ
7Gf4KGfROr2ruA+2AKKlCZbavb4eAhLKWWnGYbSnK3d0HzKuJ8w+TR84WMHbDJd42pZS4Fl/3JMg
uySLaSNf+iBr9BM/0OXxP4/YJyCyrtuK8BmfNjKs4u1VC3PYKRabA8KJiX5FaZ7whYi3jeh3eb/g
52f/aYNAcM953M77zcX4iOcoVrHWNvEbdQi5KrNdeq/NgNUcwBsJJF5Cq6vDW0lGvREgDulYGBAF
WpJlqJhHYcFU5Z67PjPFeZPApkyqHeE1rgBp3TPxHwP2xYcMqQ8AYViQYMKTJllYEWj8ZV9d7k9P
+FOi2Ct1NQvlqKojUgiQyJiHEwacZ+zGfQm0jz2xFu15U6dmr71l6YDXH1BuHV/wGIWWjDZ9M4RY
157IQNAGbJv6X2rJkGgfaJSfrbV6/tX3+SY+ll9z0aDnTDRxcRw2Po2+jKpLRDO6eCguZUuc7CMH
rHovjFuZ3jV4FMw0Pl4HN6ys90UKlmxw61233R8DG223tbXvfQO/OUC+rOL7k2YVkhHdY3jc0R82
MzLyB9csPmzkaaAnsqoxRqlrWatpKbDKhnPmT+BZEvZAtKJasXqvu7Az+E6zzyup7eR2PTA08WZN
+APE4VQOet1pA8MQJHTEIdvxqofga1AyD0kN2QLgGvo/SmsNiATcLfQAhduIVve0uoZIkfFfzCqF
I755qXlm22X4JSb73x0YVJJpm1sfxKpbjJd9IVEedxMUWhGcRfHejwuWNhcGSdwKtHctdXiHm1QX
LwC3zp9dxLROuHuCg6zpv+lI+TuZMEJUMIA9mXcemeN+SikZR4G5EXycG3xyjzK6BycbF4IGVcj8
aUa9CsNFKtTvhTvtw26P06AHnd7ATn+obBeAyBTwx5srv79x38XcmD7VyryiBIZI3WaUipQvWIhE
GkdA2WTDjZXR+XIp8NKOGDRrg8MYKJDq+7GcciRV48oYR1XkxwUZ+ViVgALonW4q+fXYg3ywAvJe
Qqy+z4x2mRYrhanUplkvPew6zfkqzN6ajcvCAN36n92WF/0OKGbX0Nav7f1cY0yTNXSModR4T8Ni
JelzGNYm/S19Ki8A5XVKEtkK26pJZLdmUXmT+7r8km92g8V24vngEi6QcwJDtQ8OB1uGxTemnf/Z
O4G/O5xgS27/XTiY+3ZSidAAA58WoS/ueusQ2FYdbXLKPhCPaV9mMp0jmZ67S1XjCR029G269mrt
vEjNMU2WBluK70JVXfphpmHD5ASFM+GK9CEbbiBYqRoA+71tz6xG/Icviu877IpiuOqty7HsSI8t
tiRGIOejfEko9Bj6YE0sRdVcdOMK2am6oI3iLsp1XKtdeouQfYnAIaiZo8RcLYuebLt5vLEmv1pZ
ouAMNh1McFqEwXgtH9K+lQ0yBfy4JgZ1LWshIHa7+qHPds/EQJun20vsCD9+TppbfaQV6yNXPMD3
4BCJ6aar/FSa7ozRhWTLPfiWb7lT31bE/FmjoikWqdqcUg8ERpeuAUiEERrzYivkdBSRqSt0c2Gh
a0bkmjTd+Fh880274K5NF+uBU+7PH80m3TXt0lYYKwqrt+Hme2yKeN7Cl831Jy18zwGfjRrsUQe4
5KF0HZbLKt4VpmIvEPAKhwazsLs9saAOotDmavqO0ukVuW0tYnwDjdIQCoCxfN3lCmCEFVyiunER
kQH4lSF7l/5ZJiR1+cxpNO1NyJQw2vECnMvljxYOD3Tx5bDugTMPWrmvPyUiALKioO9ZSn+BUzUS
oSGmJszi6E1GKRTXNlt5V3w4Lv5h3Yyw5O0hp7aHDXcn7YoHg2LQT/LuySpHQ8hlc1Wv5/CDU9/0
MTKPK3EvYn4wbfydpV+N11Lh9O9X+1yLMbEUQ5Xt8QH0Mgiv9zdDv53M7sr38qXa0KGiIlB/4anM
lJ+xMnQkrwbPmShsMps9Haosc/93I003E1VbFvHYCIE4kAmahpJTBzNMTw0nxNNQJc49aiZS/m7w
ZtDUSpeWIee9oN5JS3tJT0Qs+s6uanWNk9RWR3d8KgsM3xcAp+60ZfwmcHjCHLjKix7v3WmTYaJn
6I0SWPctlVfX7JYbZ7Y0OdvJ9ld9TxXrCGX+HDYbScLyeQthK0M3nB0g3LurCKBAPXLE7eJoyQKV
zk1JLKQNWq18Xy1kbp87x29luI5i6Z1k3sCHKfz5n4tMcK05JIdB9jtGRfia9YqSUH/tIap05z9+
sOszohus2Wo3DKbyADXbjmaW7q2TOLo/063GmA6gtH0ZuytsFkobQjFVCEYvL4Nd16EsBtm4Bwp1
+XobIWcIWTiTKOf0ieytvLBiFT+qHH1U6Zj+lvChiF2aHPfcfjHcDQvDJesbgUs+CVNJH7Arag8p
dh3fr1ATzpk1PUATkwCecP2P/KC1fz0J6TUeLXkBGbXVY2aTCW7BtmiM/iLZN0hMJQD3Q/RBQhIP
GvzfQaU4FiwhezWrHOHUk5cY5J9tX/AhtCphqYk82Zbt0akm65U4/N7AN5Ht2fFqgNp9ktqXgcRN
fqqM1bw6VWdeAxzm3i+M6y1HnTH4lZQLGLasG55znhX4VWm+569loBt3Dm/wZMlv/0Z9HKRf9Pkh
Vfy+WH0NRC0i3HNiH1ycFdeNCrEPtA6pScozYsqloyj40kTdJ/6owFGX16cg4ZdAWrgu08iv2fwz
uli97SlpBwu6A8Sr5nsbrYZ+0oPfzYLrfg+h+buW++oxNB8swUChHD+GR6SFU3Ntgqd3zvZDiQrq
CDTGpUx6YGxOPBPljjaDpx/tWK9X4xpVGwJ6Vx5+3uTGvJ/YiSK4ikw7iicb25B+PUAl/H8Izwus
NWYtrvW7QsnDx94lTkAtn0edAEWnH6H3X9Kt9PCF0+6RdN3iOYaaTIuU/Tw7g/9XhboSTO/zI3Kl
bVGzunkAgInrGXL7CV/+3uV0dUgrfPpzV+v2hgSENM6OkI6xBWjIycRfFn+Vd0I4Yin8JlmwuD+n
wQEla6wwC/MOyb0WPa6B8/io1qc1xODIKQnmO1Tn9Y44bsYvn7kp+6Gkj6W/QZAr/T0dhpV9oLlE
Xdoz+baMVrK74bJq1Nf3TSsmFEsKYK8/Ot3R5BLzgXNVCxeWzQBu7/9vcrFYuFyo0yjaNsouPDNm
FtU3004LNL7FJzYoJLqybHjMZarEqCMEOYRl7fmNzQPG0bJbKYzhTqXI/1AjvMr1drxhf4ZRRsAY
2jB/pQ9dGJtXw/PiQW197n6XxKTTKTzVGFlJ56+qWL7RohNil0FIOoQE3m6Dof3iW/RNs8FQMuBh
OpqgpZ08/VAHNtRKfe5iY8IJ4DjaqP1D6qgM0f08aPZbiVNSMARV/Y/R0tPLnREE4h+NwPszzp+4
rZOupjiGNqWnVzA1UrfexQx1/4kA1/dkC0OgKOGSkOrmlQSHq4DTP9tcvkIJZgVtmin4A3VPiRuu
HG4r1nlpT3EmkRnU4k9Jf/exsVxI9V2I+EdQfwGqfRS3yfRQt0GCifLhlcLhnLSqsHo+gsU4OF0I
3PjzRtd1Dw57gvacm7fraf+G/urQqSGKDbBikvGw127AHxYFohXmNu3XnwyRmkeXPdCdX8uZcUWw
meT2Xj3oalWDdUz0I/VJsi4tqg3hThrGQeR57b4WUfdrO6iwWF5Ljn1qcizns0aw+547LSMR3V3w
SjdLvHmNU66NAED4iaXx8Vav5M1QyzV9D/711iPZN+3wkaLwNUoUxb/NEEViXR0xVy+FGLjh3pSn
64eRFjJu8bN4ehZZSR9ckuXTD/8UzLooqtV+YZCCcxnHtucVMLJg1e3mQqwzIMfKFZKp7t9UuEcf
zaNLiIsc67jokZSC9kOYWgsw0cH099MFlzAumYA1+v1xw6gbOVAI3rR+dWCDNwl7HNN5G/rsUJIf
K6z7FE8/UJX7grEA45Cz17MRAw2RQIFadfBOTzUIJyqAg7PWFj2gkqnbJTsLvJddXAFBE38QQ7zZ
89m4ms1wVN4+5lRF+K2dGSMTBdipdPwz4nbkuSwYpsdzFR51Q6DU24O+pGcDvDylBQIUpMAvTRJv
+j4EWgUY/FfYxzdssEd7UQHYV1Y/jXkTV7MO3ris+j9qq231oZZzU9P81Nftb/vfsheJFyCTJSe5
+ZxC681bbrRwzXgbphDzM4IVHb8YO4aH4Y+ajgC0Y513gBkqXoJhfvl6elQbg1jXdPOuVQJduSIu
tWea4SoI58qvC+0KUOxYMpgMfxHdBfE7afo62XQr/k3xenReloPTo3WylxJU6V/nd1KQH2PbVRU4
HGwDc5iXZ49PPZUDKxgJda1tOCAR0zXLMP6quEmAHZm3BnzXOQ59npKuEbdJPsCnhpRntAbwKcWp
6NpiWs3qvzoXnYMdHc079KqPoA2UQFW4S2Fmj4C6kCYpRQLs6v1Vmp8FL+nb7UKh62s/d2nDG9Lh
/EqIyg4gvbmv9YkkKqZFQQAg5sueT6ed2F07VznSBEeIOk9UyezaW5TMehJ0x5n1Cqrto/7lpCcb
E6v/illU2MJC5cMI5btC5WLmStr+6yBSoHh1aIP8Ug2qAwugeQP4tU2y15Q2JpyEIw04NzgmPFCI
kbOtA7OPY+p3O5I+AByJm0O7V5FjPgudgDfguBQqQxNxdywOr5QpLq0JMHggRQbuTBFIOCWxjH5p
9Sz7n5mL1R+wU/d82b0A8GE4iFV0dP3pJoc9s87WKXCokEfexS1E0UT1KvoGs8y3qwGNDAXntanT
p5n1Kyp/XpFPQguVuL4fnGQfoJwCOI8tqUTMyONPH0zioErdYHK7quKQfo4hSQSZvCaE8k+oNAiH
W6tWiZ4xzWtl65bLg00z1rKDppCqomAW1crGaPu6iZwruoI3fXv2VJtJMGXumIy/AXMq0Fx+uLoa
NvBYPAw+TX+VNdD2r7of73kXZnpTEn2CmlDYiEqGs/k967tSsRGVKi0TxyLYYEJP8j8iDUtezeW0
rziA/hqWhy/QX1JYYwTgWgC385ZIn3V6AimJYOwf8R7nvN/s6iOnX48E/Dt1WP9OkSO9g7lRSEbI
ZqbZahS5dGrn7X2cfuNYgJT2jaFujfCqY5DO5WvlR9zf2m12NGJ70vCwCvnqL+27W41nO7n20QeF
hnRbaZF47ieEdq/qsLbpHXg5uVMckoAMAJVr2s8OT3a1b5ABThnOYnK8WRkkIU66OAsM+c9t55eg
lBg3fZygp8Yw0gi6czkjydw6Ceg/erRcQrSCV5SFZN99xNP5zV/mo4GgS4r203IX5Co1YWvTotmF
YNjHfluN/0yiSJEe1gN4QN9mpF7p0Rxdhla/eIaS1PlHMTWwNHap5jgFgOaAsaFI/ja2Wxx5KQ12
ikyeJEoi4HGTXpRfq0F/+WeJAqlabMYebsr1CaMm8o3DH7aD077yv9dRiyAR7OdEluQvIQEC+yxC
gbbjRzF4LKfvtwQ6jSU2ftaxjhXzoEPUWssftvGK9EaS6HUxL3thnyVyvUe4gmmQy359fw4sClzq
rbVhU9hDUaX4TSEayVWh1RedgDF8bY8E2S/SZ4xcDZeQrnpyqqxDhyqXViLELwO/kzH40Kx9DMnx
8IxytpVUbGonjI5P4rXargQUkjDyDrYsVV/HDaMsYpJsvKJyVxvRk4IgQbqwo1qDqlQG54Xydnq2
aNuDMALEabxCVTmZ3YNMjIhbnpUxX+P8zRBw1hItg0WSKlm82XSQxRcE+Y9ufo1qFdlohbgBd0ch
SS/r13E88DasQGeZ5QaaO/N4xAWGwXDWL5L74MREnVEO2aVIsi2ZBRaDusO8Gqq8RZbk6LFBytAp
m1JZVPMk/isTrxFSq7CzopxRLB3ivS4B1KlKE/xfTAXcX4zpFZLVPeWRsiMfeP0mg2Pk0NoVacQl
UeMneQ4aEOXlJf+Z5HS4Bxeg9ZqgVqP3Z5/d/ZC26zwL6W8bJ4D6T9DN5qFQ+a6k7g/XUMWd0I7F
kvCUC9D2BY5B0qiQnliU49iZbsjjoTC+kStJIbkXTSqKr7SqPFBSOVrVKybwVwMsCaufUk7FFKSr
dE5egpE5GP8ybQftXf7J7Wg/MxB5SJQPsoe5FQ/5xzF7NULD5emZTvmIbQNXGsL4dySWYZEbZ7Hn
MPW0HvFlYINcL86mNhHp3PIqI+qliu4FBxi+g/gT1mpKhz89Sj746adHP3RluiHQiIRmoR/ea/P7
IkVUAdeAj2f5yjnXySkPpoQWsjs4aMR6fcKBShfebDLRKwSKEJB9OACf8dMhnfw2HPXWF5Bmx0jC
jZGltrYBvr2gG47J5+neoVWWK5tPSsqv7ZcGK8ON4mDEwJUauTmkSoqcj+jH5PFXvrNqSRJCfA6w
1doMaDa9sck/OpCRwCroGCtgbVSC7jzwovsiEBQbdtYcvMs2ZCHpza0FxSzKuJrvyCTq1Yz0h58s
7DPR8z371aajRbFvI67F4Va0JIR6g3oXTx79xVzS2Rue0eYKUjrFjDtH+KBCxFOmmuaO5x7gNbVn
E8Trs1gzQ8M3CRAka0wDrAEPCX+WY1fXM//U428uYsQ0d1DH8qrfEZSVnVfMJ+2WQk4rRjlENUWp
qKbhPS2jSauISZnX1bN6aEjR9TL4aDqcrcw7IaeUx0nL14bzTR5puAJxqtlfE/9xB3cmtPShLK6Q
KKJMHZTv9hRWC5UiQy0/t2rWl4hrZOGUQAbUFGS9fBfWkk3b929FdzsB7ck9yaqJk9KzBbwV7uE7
bMBpJZZlp5AcjOErsZ575938996DlSIFjA7J5SImuW11Z9CdxtNNouy6+6z04r8jvowyCNwVovHB
/dWZDIQpK3QPX7mLyQlOi8XvscjUvCirD7fVLm4/mU6vZkACcQpuXlURm+U+KVsDvrMkA7oCFMpu
kRKZmwWkgSV3Qnvih4ZeuLD5sCPzU8YVJ/FDg9SsGvxY7nnTHBynRswMjUOeS2UZOyxRJYh//6g8
2Jzo/tRPrOhTOSnqSifwVf/i1Cd2wF8DjNty6dAjWFMORp+ryxX8uhd+eulL7lmEhe/SQvOaihuU
SIXvbhSUiAgaMI3/Fap2mKla6hXXCOutsv7doIiVC6cDm9JmWSu9fGAxl4Y6S1qGsSOBDGCKBwzH
uGz80ywQhQbKkkItphz7pI024FCjEpUa5ClseHFh7XxaKlTKgJ4YTreO+vn9OIaZxhhs8CnqW4UH
UXFLjl2Y1MyB9gPlADcGLI1rdv/wk8XsiNiyO6yeYaq8lxTMyWYmy70TazJMGC2QuYTROBFr4Pt8
f7+brpVJwJsz2mq/ykFvmmmB3fl7p/teiDDuuHpNIfRWpvnC1/GofW+f92qxOZoQb/etLW1bPcCJ
ff1b9P99TL4mrfHJVOPtEY29jD5lF9MDj1Bb2uRUYIfTZYyu3Q6TDq5ct2jt/XMJIT7CBxmpcKMI
HMSv1HwCgADYdToSu6iKX6xKe0c5C+OgtP+JwzOEICbqhSxIA0QiH+cnIxLMd3FTZVeHpEGY9l3p
dFOdiE1X0lh3Wb16E0PP2We3S+SarilrPFlFZpbnHEkZGVM6L/rnj8uwFBYLFPMs5YxASXxczjfV
HY2aKlP64stWC8xc2H4gsdFZKQWqcs71ikgJRQh4MFG2JZ3oNVLWvV4oAkQv8rATFQeWuhSCnE+G
Iv23Otgdznf2B+3m1kKCd2RaBs5d+GtY12YVO9SBlVR3UQ/44T5vieuk3FDOqSIF3uOZWFyMXo+8
GcrPEqIwhpl2XOx0e8cYGtpgmohAxeK+rdypV5P+Bz8dd4tY6rekD5pNy9Gk2tl6gHUmTWB0Yuwy
H7T3t+olmziFCFJYFksYijluBInl0ZqQZQLfuhSZqXQ4u6Gr2UhqQhjO0n7MJWuYxrd6czpU4E8S
dE5oRWE3KdYfY7sHKhgmUntYc23sEb7llnWihL63VB5Yg5k72qPg6n6R5wNRoWk8ods6Ygq677Dq
3VPx2MraUpSxJfUjekk7sNRjAC186dph4QaccwZeCnyt7iHnrqE97v+wEJ5UVmdvPINiI6Rr0YL4
zsBw7TgAzx/GQwiG99eg7FwmM1eqSE5ARe7Gb2zuOOA55M29IU+QWCMFLzLr88lyW2Gdx9ZCvzns
31Jk3m+gx4x5q5g2FYRs8wROkv9Pa+Zr3iI6RGaFx/kmrlsRO+e+8YbLHlg/ZwStt/wElO/ek5pV
YihJR5XqPSKAeNcNf6+XEjLTLr5p397+7+PFHhdH3HUsLSpJLPn8TFGDJyuf1juTMubWhxHPUG+R
Z4BQ8G/EeJ6O6u7gZTAAQ7XhPOUdNSTaC50rZiQ9piS24Zk+DDALHQbazqXNusVut5E5oi/R+jQB
VP90e+nYW8bVHHfPwJQqyj40nkNVoaiMuyGXcs2BvEBm0EbIECIgPtzqprFoaVvJA3rV5NtpsO9h
ZT45abyDd9sXDBr3890+DOsztI9F+8zo7WdAnB+AmT0/qaJ9CVcz9P+6qm2E+ql1CYyCmtK2RLjD
kNH8IJYVbngOElEcgpBSO5pbG4hV64SYk/GSO0xsi0S1lwFvvI25TSpsfy8TyBBjKZNNYYduFckQ
GkDeI65oHS+e+WtRxrRc8AgHtenSE5CpSZl6HwHZpSzOO5qY4WISm7w1VJS3r8jmvfSWZ5E+AYbs
PykRS1Z5rggsCNOF4+FubZlUDmiXcLKZX0B0Vm1oaQqDCHYnA2G3PINaoUJXKV6qxT7xUxHAD3yW
EilpHlZHcoExBvr6t4szdtXWKcx2iMKmYS5iHtY22/LAV1yf40pn2cPluUoCZXP5twA+Z4CP7o42
OpFf4/X1ibb7+NxTsK+K92PLWJYVCzXrNYRDLjNUrovblx3fMH5vX7SS5ONMCP1Y2Zhi9u45h8Dw
XfmZWtC5rF3WkatA/po/Y5sMUKcAZmb1Q9Cav4Hq5NBT55QJ96pvI2IbbzWh+rTdCwT0Jo69nSuR
5ojl0drvoCjWG3YDbI4Aq0xTH+B5r6Kx1LWEOo73cjqNE1sSqjt1PjhtvB6ielztDslso4sCA9EP
6GnaKcg7Ko+0Q5LBV3JGdpZGqz/D268IvfSl7IV2IZJyAATGu/xlgAT3NRor4KVN5WxIkKwxFI1b
BiWeVnR5Z/7EYS2wiHenAXmQiXCthcguI7PRpWWyxqjwaWgpOspSZDugs3QZU2T4Msu7Xu5EPVAb
g07hmWxNWqlMhzedU5cJXHn7U/MAAkJqlsTmCi8WMAlJAmth683q4jiO0nzfXq3FG4kGSTNFfGeR
dq/3lGEx4esOEc7To4NdovdtKOTmz2hqUQa6ERLNwXnQsgIj7jvmJpGBzKg0R1dPKXfIimQg/sNN
BN+n6OdDwHOuMqJ1ccokFFLY92q0/i8qMGan0X85LIbrjgUZfUHqypc4drWtkUFoGINJWdb6RckU
dcdty7WMOiNlU+Pqj3L2UXuk8SFBBF5mHmRbClTz+AqNjYQIXxyp14SSbGq5jMQCROhNQVl5W3+k
Yk6y0jHZsCR6ZTMX9jTrkeqCA1Tt0VjHVC9bdKhMfEfTeSbZLYAKPulFpQcssr0lQS7vlA/jvRe+
PGbO9aNM3IuHfHUY5nevoCCcfWpQ9k4MzQisF4mLgfHBfqkADWMtXO7B0+miHnUQaeurH6UXVa5F
uz81atMkPUYUP1b63DQvCR/isL4xqRi8Ufa6MlVBUJDZ/fb13UxkYEQfZZLVgEyF1Dc7CGWj6QaC
j6IF7UxlbZ+YSTsutbVUgz343HleClfAvuf+xzUwYWxgssJuWhOFNpB/8pbqE6bGiljx4XpLbZBm
LJTYe5Sp0YU6ouX6n/dePEJMPKdy8EG9ICmSN/8xDn3eCRu/TJ61n+F0m0JU/9ExEk0E8OuniN7K
RgtX8+S4xMXRGnHhYvDmIWemwNEQb7lk/CX1AJGr7+RpbjSU2QhDxagL/uEcUZDMteFXHdl94HGM
nNzlNSsSNcpkSGOIJkLWkj7XKcn7lu3Du8hj3TjoQ6FmEbCBATLIkcoFQT6h79lJIsqyMA9gFNoU
XApTArGMZ0p5ghU9yWct+UXRs05ESDGcrirDWDmwyQtFk9su4quRYrzEZeaTgztIkXggWmMye/zM
PMQr+LYNu6oZkW2Yj/y102kN+7xn3H7/pxA6LkQDelwXgfAOwQ9u23tZh56LCXeAkBxr3m/S1Kyg
QskME1Wk2whA8y+yQdyIURNwSg0PHqHNjXsG/Z2Z3YWlTMRTz6rkEBUc4WiRhFNjm3+OT9S4f5fS
Wch6v9y9wBxWyU4WvcTpp8KgyEBFpARA60s9dEOZJuCaLgYGWYv7j4pxNiR2Y2GeyqqddI5wq3Qt
LAym2EUv1KRjv0vdQTkHt4qrtHUndnRksJCjwwBB50DWXlz1hKFtXTzW/Ccx7vZnWsRevrZ630Z+
s0TNSz8LnmtKmjtTM9b6zQbkmzt2hY+TWvbClUbkQ8wDqBqhfR1znpjHNl67YZMgMfmU+AB5WR+P
QyJaqKR+CKnkAv0MklmIMHnY+WYZ3l3GHZ5awln7iLX5BbGAMBIF9j4APrxtEv9Wv3zoFDvHoiPJ
TcQ1XQuGiv32lPmWy3ZgfO1JendqW+le8ZNP7z6TLqtTbfViA+Mlt+GlBweUTy4lrHLpH1D1IIxh
cLCqw5VLNW9M+HilNUD6nEKiUa9/6fLy32Y5dyulkHn62KvUT+3eLc+6Ndf+E+rLCSMdbKDksLvb
0AuZSGSCrplZBYLEKxBitkEzFZFEUOFQRcR6rbAvR0ifPI2KBA1+oVZLMVc+wsXouH00ClhG1t1u
IAh0I03pom9xLOWvzzOD33H9/cxGmqd7EO+D5OlwG8+CaMkuLP0kFiKasWye8BqGiGSd4HeiohGj
0b9gUHZ695sXHJ5DfQjM6APhJCZGkMwN5dAiKyBvYto9I0saAfvvaK6uF9jxG9Mav7n2OhruYEcA
InglMUoVvOwt/6/BggOKqfAA1a2PBN7h4RWyCIB85ARi1ykroieWFweqiO5ThvIRQpuO9+t+ax3g
qjkEIsORf7v6hn1K/RAP3oSufM7yloEXiqKNNAwRkpdBkOi0rSnef4cg0bd19+KbxpfcubplfdIs
7P8+z/VPgrfli7si3hYEoPgEYDfJeo2aZIkxOYrxMjyS61xGj47UVt5+8crIT/3RVlJAKDzDR9Hg
dm64JpoPT5MF9B0kV+SmTjE8Oj2n2Wz5oDCRXxGfeFpQC+8Oxz3Pfw3k9MDJfOVfM4XuAfoJFpmw
DXJJa+lZv+mGkQ/IhEDHirXzKqNyGZ00xmjOvIlYRu448rUYqUKxHWjbZooBTofmDs5b4PvmVTnz
KDNEafxaGuZ0kxnt/Ozv3g0tSqHzj2XRrY35J/2dYaVIwNGD4ZD9GH4lW8OjPk6BaNOIOaTaT6eq
XnGmWDt4G/CSTzhTD7HkS0mzlIA5ohbGDOY32KJxNi7ZVnJfeO6g1CFaRP7PrIRm3t/sC1pUTErX
AwpjwmsxmMkIhoiBGqZ0drjVFLbXRiSZ1asL6oiYVymHrCzUSh/QbmOqh/4DkEJvPmMZ8sPTZHum
+UnlJZXnXx12iTLfodL5oJYUJUf4a9KQs+soVXJEVKzH0gGLWkSFg23a5gG7YrSrk1h83ALu3FCZ
wQke4R1s3P0AvsvXozgqBHc0Qqe+RZp+ozETKAh7mBzq22d0Y0i731wr3IX8WJzaupHW6ZTlrYrv
RbQg4ue6Rpd/95djv0zCCoLm/DCQYx/+WMC0g9mzfcqXGEJG4Ds4mjSoWGmd/ge+DNjqxBVJOANI
CSBNE3UmQ7BDFUWz4UdalrmQy7FO/ckaRdm9X1lalEruEJbZgw5mkgEBummvQywFUyH9QmdgxPx5
Pt/nPvEM/JL/BpWZ0fdIJnbD4iZfxIYNHMQ011st4eW1iUxS75rcKSTmRDerm2f/u1WkjHNveawo
HmnremhG2l8+XJ2+yqjCCHLQwJs20TvS3UH8RGvE6DTPB++5E2sT2wwcJP4KovxFcaw3aHxOT+Ap
A4tlymjJC6CmkecNvK+tFOvGPTWfQfjoQ6NY9zJLN4Hn+6V7r1Fm5cdkHZEekUamWm1//1vNQlnB
SoLVj3tBGgDouyYzVMVE9EidJfkeYuPkyvbrLUQyfWGs/uhQQ17O7CVUpe5djDZCrJwrYEZOrcCf
bQDz7GThKzslbBC3Iv7RjzvsejMBb/a0Nt+MIbrOyQG9eZBwbW9FfC36wLJJPti2XxtjF2Teis5y
k4UZlBvB9zRgI1owhg/TX4nEa0Mgw2EvCOQGZmHc7+ePSuM8BWv9V8LFvOZbMu9ISMahXyCCe/EY
HvsBFtNjnbUGrdE54tyfQWV4M3YtqEL/iYK4v+S8SvvW3STHyP4hk9HNEgP9l2KEJzbbosZT3447
ZjR7XuoDc2QVL/Z/q0f6o3DaAiUWxPnqtr8Yi9oU6rALRMuFhkeJUBeywITazmk4o59Efttw/4O9
w2U7WCnI5ar51yATrTJOdT7EUDEWNa2kUBHfQinVpAg4IG8O+QLpEwNOIjXHdHW+BRA6fB51JUu6
UqDSB8pQoIBXfqbTn4tQYlC61nqq6njIfm71FiGOAG4LuaSd/hlBEtk+1cZ/I62XiASaztnwdZoJ
cOYuajSiP7dTw5i38IfES6dHw6F0nzB+9SlPi33XJdG3pYpv1ugChcLpXUEIpjWyZrZkiKAeb5Pw
sDjYhwBQtjWmKixGoBspVyB3Gw99ZbVqKIJ8DU/LWMOHTTQyLv8WTLzDd4YClcSTDkflQLcDLgic
iMv4UUL4JUcEvFvzT1XY7d89ALKPUlqg4ilSSRGFM0OHvr8tFi31Q8+a1YGXQDuNa6Bt+arFBpkk
xXqMnQHz+2rtir70VwxmRLi3ffYHRuMkOi5Tvp9kl5MHBcUWGYz8kEYs0+SOomwwYqxekWOpXrnw
wNZnMHTXMQ3AruMll22CY5KBCT3DqdPEAdsjYC21u4TE1S3KB3XzqW4lIRnEzhbeBB19+eSyNIZa
ZyUuHaBG5VDkNkgATaQVZ0GFcBSoFeQkn1kZz3+MbAoAz+cIli2fWaE82uKh/sJpDHRQO0pJ34Xu
Gh7UH5Tyw6Va3ld6M80t/K+y4eYzSwd6OMTsCv1Gy5+fHqCuvcNiFMeoFZpQ/4YOCM8bWbx1o6HU
0xJ9yfuxhWEq1NlL4xwvYfRK9aBhTI6KxbnLX2hQ3s/dyUVSIOGrs+QksJCy9lDe3CYnzagwbuW9
/2SUJMfN7X7xaAXrjlxMLh/G6NaIGLjRPcgTjIVCXkLGybHiKdTk2mBKLUQm/DAoUEm53026QwtA
qm+dvawJyebzlCCeYii+UgWyI3neFLOpYDHkKHJF6r6hrdZbsTHp3p1Obeaw5lIvjdLRVbfOKdSz
oQZ+7yFnvULepw4jKn448rh8+7RjRNnAwylf4elGIeJ+kmm1Od515dH25FTyXTpozgfsLFb3wxbE
ZIcZF+hPTuLQF7TVXiymf+KYcMXyzz5S4M+bvF/TF3fYdU5XPDajJJ947tWVUxrA3fIsxUDWAVah
w1mHjAlN4OSSvQb8A1PcVC/hXGgemtUixbJOGpAI+RrFEw2WxiEJYykWa5PhyPlv9opYisHzMycE
rTRFROEAqtonM94K/zGu5Avi9NQje8HlJdEhgXVpitvbbVjWxAhiiTJOABhUsPYTKYLyEvV8AU7X
3taSXTNO3uL39HxJZBL1Cxy+La/DdHTPCc/RAI9M0LuqqnPIhT6uQ74gsBia9b47VUZ1zHVRO7Tt
gc+5CJ1NXctvdtBUPz8rBuwOcdt2qGpkSiIcOU53cyIuwAbC57XFKIIjwAwbsyuJ0tzT/UbhjX+G
T6lSErZO2LIHw9pzVGgb3NCXnEdZN6r67qQgm/+5Bu+yKWNVW/xnEADFb2EbOzh88SpjXD2PABoF
gcXUBCB+yjjkrkM8uYV3JwXWZzcixmD//g9wU9zxluUzth+opU0Zy5g2aFgRwbTJR8IH873FlV5X
F2sm1hMxxaTuENrSgFbp6wi8PMxdHYYN+ahWtfA8ll8U83kqXusLbQolEi4sqTzoXwqfXTTvqAgf
uGQKnMKJFKHJuCaQdQK2TDIW5Zmx1UJpsYmf79iJkqRe9MKo0WupJgEHzRFldMzfzNSOJEIuzxLt
/nPUEQbkbOO6+0873fR6A+Pvj5572JBZWc1MXuhUIrU2RciVUdZratL15ignnCsizp/ioOfqAXwG
nV/KtDZmHqgYx/I8g4ZUw3VuQ2QcO75NK0oXKOrUmdkaM6Qu/FZKV8Pm5O5qC4a5Rt0En8FQDpjL
hXjeXTFTlKOGdnSDo5l9anJwQ8GKPRWT87iboAw0KFY14HcKED5+Tf66ZlNyAtKIUE3jA4xdxYii
K50xhUtES+noPMxoImLMaN34fxokofxTxSBAA2F7xuelqrqfd/HsbhIT0nAgnkX/MH6+8XbUG5ax
c8XKAQM2iT9KMxPsIndj4TTZlnhx9rfE75n+ZYBvYcHF5vO0ouJprEl/kdgWaG8sIoHhDN5SMXNc
OAMAn9TDHm8FldcW840pcit7+vO7ajZ61V5Jd7dJwF0yuFl3k6nL6nP4rKjOEn3Bqj/dKLZ5z84e
4oE8jZAcItbHMr7HAVaDYpx/B7/t3LQMEQoaL7BrnOV+P+DqPLufAmesD1ImDh+XH3Osmwv3z3Na
arYbDgkJeC3ZoQ7nR5HmB5EhQOe4XML9Qv+8vG3CPX0IVUAJhREehkPWU8JURnJW6EsuUgHgJlIt
m1EQ94j6WFjJmPHHAm+cDfI0Z6JRX4+cZk7RuHz1fRb4hpo1HZyGImMPK6u9pJyHjzOUA0PgQKHr
9twHsOB+mlYRj/bFpBOkqBYGLP8h1kzqdCd8Vp6IkEw3A0cnXoS7tPRc+72l9LJh1A5MPGStH8BC
k/zn3upbZklWdnK6Hwyr3oL/zJhju5/XhUebw9HSQNGn0GaYZ/titXxZbCmItU90/ALjEi1cTYjQ
1aoT1ZiV8z925zF1GQNLQAazSKIE3kFF7lqGQ8X6hKxQd9Z+KFRwwutwWIv2UZC0FxuErmDMKoOv
PCEfJjvsqOe9eYvhqu4qAY3G751tQVzFIVERvi+r44NzrT1U0Ja5d/61ZlhWs3w/gWaFa4A7whdg
PHjXvzAOj1+TcXO4lqUadZDeboKPu7EjX8Hj8u9oKOMhFW7GuGElax3NH4xOuhJcz9spQ0/lmpBC
Dr/zPoYOdyxiug/4MP7EaMGuEpZN7EZtZHIhGwlDEVbXWv1qQGctisCUIWjJCsfZtIwcTujoRjNJ
3sllA/bUAjeM/FsXLmW8HhvfG7Ucbz1Epr10HIRgf3pVtP+jrdQeCNIvl/XnA6E/GExYnfKLmMaN
Lg2TBVmBUUeSwg6GCtw95v6o/03Z2Vtj3lJB+LEoO33pHep+y23+B5GnRCbHIbkfp0Pu/IkN6Grh
ngws/phFAHh89U6WrMkZk3IC20CCoVK7pUgujsGJV2wPjLMlHAVWTaWqCM6P62hjC1qEv/C4Ix70
H5Opdn+P1wHDYWLCotuEFKB5hOKya3Ux9p/oy+E7vW+NFR6v1cfU8J3uuZ6buGuKaYZbhrzujliN
hOvrzRg3TndSgvW3xK5njL68egEk/eR/LG0nC3xJN1DR4f6pnr+YvBvUTnGbSXyLWMd3SNSFW/PA
6Np5LF1JIFzKQ3BH0c0soGqTdSRSzMxPy0VgvCf62ITZ3HXLvE4w0hRSE3m9U32mSeKme25LykWw
qGwryPcBqOM2aehD8HeFgcZ4UUBPu5JuFRyr5Lyk+05pTViLvlH0qqXzLeKZmdPdUh/OH8feesxk
b2aERZ3zYm0SRrJlciPTkeAbRfk/VtQmcFDXYytKN/76kkOus6ikkdz9exAxcN5b+HkYSH77eS85
CN/aQHRxEm4IjlxOcUDjzJKxjPLCquucWZrY75Aknr1VjGUwaGfjBA4dtJN6hN5XybknknLVUEPz
uaivqfNOnIxsUXgZs/eQgJKvOAlwxo8VN+mn65hGs2z6rqtN8EXP4m3x9a+zAbKRHi7+zEGLRFkY
NO7DQy0jAVa8TH/ob6nWSOUDem5wXTGmJIavKHbED8izALZC4xT1zwQ038UV0KCtgFZvwf1Q8fS/
J+uRloxtk010jJRdeT6Yjgw3YhFa0WIlIwZiR9UPIAqcsWiFffifmxc+v12J4e9FqvsDdeS0sZMT
P/vW4npWUjyveokSvsfX/G+7Hwedsk6Z5l3l66WFvD+rnTP9euevvtMLMsZgTHjPDOZ/o/06cwa1
Ci2ezaxrblnFd7lL2Ox0VycrFfRILaw96JNRcQ5asZtUMOn/3zLgi6a2r2JqrzDoa5zo4Eaf9Ihp
p8hk+ICGhXjPfVHNcJxOMSGgStNwnXa52cnPjiL7bf4w859Zml0Taw6oY8R3MMIsFEMYxTp3MZds
0VW6kIaUeFJt1SjB+zMBHwekVjBQK3hgeQhbbjRPku5ol87sDd0o11JSNYSaQkT9aPtCs/YEE2Gg
AbsSIXbI7opObHMNOVPTWOMoBhtdZdTh7AT/0poSdW82LoAGy1luiZpdM41La/qGBr7oTlwlght+
8A5llgJI2eEIF/ZCA8fdpenzTNOZv6RUkb34QC91oBznKO6iCnOTEJJSP1F8YGLSY2R34VfCX/Hc
2XEWv8YZ6fPfWVcO4HZqQowNrSFaGlgN26cVZoNX9JDrYK5vZlL5hDfa2VFFqU79esYtMi3k6sAv
mwqWglOYLOG0wH9IC2P49qAoj4ciZioN6E7cvjn6v68pkx4zas5N7jbiiCPXTOTVdSgZM0IolsL5
TTZXXlnOE/pxLcJmnbbbf+KbLxBCn1wnPg39AxdfqjrmgEtvp4OhUzHnB4fMN45vR2eiDLYq2vwQ
MAUKCjrvzh49X3Jf2g7KiSAp4ekGWyksHCLadhUfpEYJd3l+JHYdPe3Lt35QwXUNz+Ev8ar5CDS3
5u+qgkksv+9AEhGB5UAmgnfFX331BL940MtVfKhG122xgZzGYuByaHr4IPCD5LIoVIFGvN63tP2+
r+dk8J8yyQbi29TjSipiz+X7OuDe759rULSXWMHW1nZ0uh52a2Z5BIY5avFt4yyNgY2jf+6uA0Xv
Fvln9x3g7kzS7FCfFalEemmjJm6VfzhXRdcpaxpg2bCBBRzK85M/UMPcAUdaSpQRiugfsdOxJWz1
JYqPvofHodcmodOKur0B8zTZUNkH1RSRA5wmZ/gBl5jWNf2Ldo+NNBTxNhFavhQVtfwu2mnYrfDA
Jz1IKm4kvPdfBA12oYp8w8EotBLO9u1vdTDo5mOeyt1Vqz38ns/I0g5oE0EaZ5i3xherZwcYOM+B
py+qAroIBQlLUwefTC/e+i8d3geyGmofFSZiwO4RA2sw0lrD7zIFLiGHVjDDyMYlk5h9abkva8At
e0HOfOkiggIE7emsskwND7OdQG5P1V7dDbjTVCAX152cD11akmN5m68jRuqdt7TQdOk38QmEit3y
bbDpmQ0ykCmOT2rJtTHn1ZJkVHh8JQ08hqfKz8zHruCrmubhKEZ0GvJpc0rvPMjvttp/o3o/VN76
7j8L46HqRUommffSZMwz+v7GAT7n/GuWJ8R4OgFnbEe1xW4jIO59oK6ZFHVNs0b7dBJVAHYmxqE6
NDOhGMLftBYHoTy9cUcJtbTPCpkeNm6LLHECer3tCBS1ank6xvc1l0PFVPm2grJNH/miYTJsnTx0
AqvvYEys5XkdC335R+vIt2lr+zF2NRnW5z+oX+Kpu2qUxJox76obSebm8DJRzp3evQMEzEhWNmTW
I2E0VB0bzapbldtMS7wNOoxXyaOHbLK5RlDLDnGrz0IuTfSGrzm6cV3CLAV5ABHlh86+AhV5kQeK
0NByyyrtP7/Mg6YeUxx7fpSCVp7OhQ1yLw31Dvk+HyuxqHaG4Xo745rO8xYf+9tWpPSsfIoBD/yT
wbn0VRGY3UqNaHBn057KX6B/yp3H/+5AkWtRqFiJTsD7zWlqaDbdqr54M02y4e+3B6KRtidcClEu
oKco6JyyeOCHjCCv5s+Z3c0s9u54hmYO6CGgkhdQWL3cAtYjnS/7XFXrfMmzY7tcqx1ugCYxsT3Z
9zKqaJiVqlVdZfBMYKsMlOxerYuMSX0YlsSd6HTSu4N+9txyoPCGJlQYgi+zue1X+LgBB5YZENvC
TSsiDv2jI+zzKUYeBFOQC6rszX/beMjqPjFezae6KO5xt/9lbXHwVOEHsa5NhuJe7srZoO/LaD1V
l0A1j8od14/8G0CasP3VulG0/8p1qwPUh3CPOQ6wO8DXUMvdhulrI+B71okLrtEkSLp1qWavb8kv
zUa1f99DsJZxElKr8P/vkthdcRyo1oWa+W3+gCMIuJrsvVKPGFi2VQ6p5Uh6XiV3wRsKeUyXrW+t
2CGeYl0eJUEomALsG+1m08HJRCcxnmp4mY9i2W+OfBYAuhrBUmqvrnZaJhOEmzSzRLTSpopR5mLU
ozt1S05ApdBN0WnNuymAiOx1yGQqPFjAuf8D9cEPIw/M1Ent3miHtJA3y6+k3q8/eBoTt/aS6xRw
//mo6sKUrRaRm7fuyVXh/PrgdQ2KVuKbEWnIdzahcoXLuWaAeZac4td59cjB47X2Ko5ezNMQDG8y
SU220088/S4l3aLbe4wEu+r742hnS0WEQ5Pw2/AWGBLOdvdfD1ziiezQi0M4R/KzSWxC9tYHYFQM
0xbz7/erfarBlfaKk3aVn/z7TqOX1eL3MOlGIgowsdpsQGt/AqAt/HKWYalF13vrQZZxTbVSK0pG
rB4XHCxXsLxO3KJVno53+9/9K0pm4OriAS66+3T7MAgQb1YMzI/80+hgq8SE+dTq3q66mmmDfqQd
T/f1ZnPVxsgKWV+NILAMkZvtzXVLOxqMnIa85v7Kn9Y4ktxhsUbbFTPet7UsBPsrqgRaviuWxiM9
7FdpaWhKF2igR+QXLU8wLXNVkpsm9E0JFBLzJDmyT7kBJ52D1oIPk0T8ALJb+zYoli8aemp9IM1u
p7zOao/O7U8m4u+1hI2DgkhT/GUpb9tHDQD9TjeKsgxRlL4jAeZ2aQ89onpT25wjtOEwXjGXaNXj
ROv+qK0YWHtCze99t7+Au8x6sGkbKD/bmNb3PCm7Da5ABn+OvPKOgF4PVZuI+g2B4azaYmA0bhLD
SFo3dgZAiHp29Ck4oRRtVaMwzGTGHIP7/5deULveeIqS2HnlR2YYYT5enMO7G1SaP/jNZY/xOY94
yFgpPEdkJV++2HBAl9aDh1mtHVfalqT3JTXfH7oEDCKoPdc+6xbdj7rcbJmjlex+urrbtPoPD6Ec
0wpk30qF6fFzAWrad3GjXrHORzScdY9yczYMofqCJjF4U38W0vr6dqAkEO1hdzO27UD+JYCLigEf
NC5K13ackNd0Qtdspf1X2DmMtvNj8rRuWEX0t9zDHPv/SAmbDcdqRksObvhGUPfN237wYJuaXBFF
6kBSXuZ9q3lTm77vOiXTeuELT6f7OP5OVrPHygSQIK/16n5SS3IKI6ndWeEnyY5U3kNhtavQrHVb
j6GqBRflYESLVYU1AOCD8lmePUXHl8ygl1XQJ35RVPgR/dpjZ0S9gNdH5866n3mkhIA0HpK92nPE
DRwbwwPo6ES3eCtYoC1fTgWj079tiZgH7QV4fFbBLb68VAV1uiOgTZGnTuTVDy6z8/kunefjvb43
awhCgP6+VhcoknVO/Vp/jBT56KLn+6o/biZ0i3P/H/IRKhFAbYRg2qAGXLnA4BNY11ZP01/SIIIH
cybqdLWEOxlAeyScgOIE3ntwCJ34ZeO3wvKf45jnKnPOf43irZCv6M7X4SIF/tDQ+RQNAeqPGXf7
ZiIMaLSODjMgsqINfAQCy2PZ89xj49yoy0FMsOZ/16hxAyZV78jchdOcMahVpRmRAuIOI7tmpOKG
AsFSCs9zOi2XNTNU2cEWhtGUpqPo/jj6Rwu1pZmu+xk4VnHu0GPbq+/4YlImBDyM0Bs2WD9RAzLv
3QtIn2vqOAAtYci7UNZ8LwuKFZi1/EylPqVNiPpnLiAPcR/j856/ip6UDpzIjYl6mrzCYwsIb6pT
dD37twnIFwnwtIJODlm1mEdEoki3LzdZS+GIRJqpZuhLei5gzDMKG5MoA71oCtVsM79WyaB7QPjJ
DttrlSNx1WM2eIL51E61R306o6nJSUS3X+88LLHWAZ8tQhaZVx87zRV2WEf7vRIZMZAM4vo0I3ND
q/HRL2d8l3KvmGJzOJDRBQFcmJ1aK25XQiKc9y8QthsviAEqybVkz0d/xufjumABeSNuJF4r7AZJ
tP16O3Odcegm0fQLIyuigjzgO/atCUjqsMZOAsp7kbo1+cZGrDpqPb4J5CqXPWhYEDEbvPo9GQ94
N/uvoQmCy69OfrBODipBcAzgQx1doW7uVeDNLFOQjNBzQjuB2uMM39UmbXZv6sBRCekZ6q1QjQSj
C9dr1dGojioq43dXUQ6dx7Ly26JK7YhyMditnrX1LCJkYJnPHMbiUPtHZx9k9mJGdRVxmWX/QOE8
IyxsT8oOylmiGh8JnVlm5a5osnGeR9O04YeaGu/cmmGhLFwEnMHDSfXxgnekgaNf1F9G2tR76S43
K7g90wSof9KJgOozzTO5+P++0P9MpMSmd1UDQ9m0D5z8gSAlTI+jAHyhIswLGN+bnB4TD2HpjqSt
0487tA8s/jvLRNURskIyBJ4SzzK4Kkmb8JbGUZJHWF/yq3mJjMxgIU2aNV+dY1mhZACvTmkVqOKO
Wy42ECUUA6auC94tG2Lm+gUkUnHBc8yCZbrNEABbDlMgPh35xB4hQgXG8W+xIaK/+nCTcQ92V9fF
OH74SFXPCrKBrOn/yqCEhwcmoI7ZMGuXpWv7iX+vSfOIcQPpA4iqao2TDuDfo0g/g7PMcsOApv2o
RXONLwUuVSvw6QlbCHSokWGhhxRfT23jAxdPnS/4m83PxKQDMPDK2Jv29UUHsNNOa/AalJ4WdYz5
kCy5Z9D4VrkAkHM9Cdz0fPmKx/DyLKlu8RykwNNzUrV02pAjSxdBYJBAbiFUkfsGsTmW3LKLHgoj
Ot54aLQhFXmQOwKT3hdobcW53TzVnMDJjIjb5oaaYVfS06PDGgFpU6jIGDaio0FD9xCiEiqKOhH+
0m4ArWJyOWMtQz3BcMU3bI9h97IJUHKyWKJjwqTjni7xhfnCl8FrbaKPUotDvmLmG31am2gwVfsc
K2j50GPKc9w2S9ZDp8sQtAKY97cyHW/BGDXAmWDn+s5UoMIGkir1QiFakluC9zIJBxYtiB3SRTFV
0uOeTitq5IgHUHir3puUwpfeEaOm6TsvDFNNeR5zI4Jo4wgxHd7IqvhAW9t5kUydNj5T3GNOctxo
2sQqApXWvjL29o8OMFme1sM8sRMHl961tqllA6AqPVicolPv9F+her5/gTOEbH2bLrbDpJ3cS/5T
yvm0FoxdlzR4/60JZfBaOrV3+d4zTTOUvc14Xx8D6T0Kf4q6em97GBIKalkB+kurFYGzUsBQL1AT
iqIQXNo41UmRBrTfBNyymf4wBigAe5CQ+MEobwcZtBHVcMHOFeP482DafPe4L/IStZrIU25gnQ/A
hrACgskMFqHfrDmnKPRYjZRzxFOT/KE6m3M3s/PWH7DU3mLBAoFq7YEF0f68Fro4UjHLpAdCN2F/
pvZ2DD/g/GPiYUIPMPgm+NtzUNE44N+8JFJ2WLXsWdMDWxuaWR8CaXXoEQGmZ4vJkv/CjanXFhTw
Fw4MUFzBrchzxrpRXUnGn2MQyc74Fusl4g4oZnEENLz5saQ5pNZFzOqYZnzzusfxzSs7Izgn8vEX
xKRDs8blrZOxIyaKVK+HaYFwz6pm5GrsQp3v+jO2zCg9qqChQxGSNDPtwZr6Xfkh/CmYusvLRWx0
mF3E5vLWx4y+qjMJmF8gxnR708JZhHd+5K3lReTej7Dhw3npl5RujOSFjlKsXfakxb3B1bgt+FAo
tv9AxcudnYtwi1KIVEXxtj1ttwNzvcUVe/ysbeOs6BxFJquVyWAj0wYepSWhl1x43/FGFcVJDnfA
J3Gin16tWugVAEnJsmnMen+x0jVlSQe60Np9aN2t6/US80c9cdGKZTD3HH1AwoOo+LAb88rh8guc
zJ87Vpi0judL8C7MS/u6BtDKtM0SXC8mnfGN9JGMtz1nZP6qBqp6V2MaszIUVhHBC2gdaMY80Iza
BWna9y8SH4APr56gwVTGW8ov4SmhdJfAytcE7YBnVJV97UyXpd5/m7ADfPJD/2SU/8E4DE4yw9x1
ACjyEg7DEjpG9/tWybo5rL1xRZMgiRLUUVzfX+ncd2k/8VRExCrq6uedPNNLkb3EYxPC/ZShGCfV
FtLOAvffTqZ370DCX9lEWsVz8HY+7wdLrfVrPQ9NsdwFsBpWiX8f1DcoLIVyT2nEvq8/cVqpw+Ok
A91vMGAvCO2nYOAQOZckjzwJnLZeTH+2ObcN4BJK4nI6R2J9ARYE3pLpIq9SHLAk9YEOfXq3U4OV
e7s+87ZQUXiAI5zRuO/S5ryr/N+/Gf20TQTQBSnj3gmULyBcLotY8uNrYfa5r3Gze1nStVHizYKf
Wawj3MDameZPz53FdyEOiMi7zq+tylnv7Oy70eD+YutcHievsHJwzCCMNQgZW6fEAr6GrkhAv5dh
00+CGqxO1MokWajxeQqfK5MtKqp2H1yNwtMiKmQc82+SVOIzMvyCHBxrWOo/frsu+WeRIHRiTrql
vt5iVpxdOFvYpkqvs3v46hyHuE+Wb4PBNdzP6HpX0ltZdb5QHMSY/aWDoGCep5MB9s0hiOWl2UZE
PHimMNOTDfvPid4afta7SHWgnCR8f9Ej+ujroZiDcXiuOOvfxJQ35Y9TPmBhSmjj53Tuvgk3mfe2
DTODZilWR0MMqwlZKXAhfVsfrpoOTbgRwFQx9hqRUU8/EJOh6V0wCMFqPnuv6hJGk7fDRRCtF+vd
qO1aaM5kuwilFQEVMUpc40cTR+96KREK/RDmZ0Lk9wvjG4s0EaLMXBv1KkYz/55cmUHpPyLS1UlB
vJrkWGb5t4zuU0o0UqQ8Tc6I5Cv5FLmKj5Khl+tYhFJDRpIkkx7ivIV4Lu6m6J74dAXwtJLMzo7W
atkgDI9wUDjyfPYmKRO8N1OrJFB3JBAi20cs2Rr/s9pNH9XCkVMMxQDyMB8+G65e3V/80e9nzBje
Jf1lKjP/czxx6PZ8Pu+vcOB1C334Uunc0OZ7BDucmcMpRnwy/dfeQkKIUzakTY/IXgT8dMC/DmPO
fxl8w5fNxvGOn/+aQY/dVxJ+HyyQXJxEEfBJnEPUvsB28/7673Z8pjSIEnNNIeqes1PZ5RyscrcF
flIW1+2YXgNqEIGasP/cYLAM6FJiSMA062jOCPpy/UepvhwrgbSFaT62+2LMP7y9jpITxEA1NKSM
vUwMGQU0CHAbw7j3LrBKxC9LJxaohnK2xm2G1R9Ln5l7bImoWP1GVM9uSs/Z91XbN+KiHTCpum3P
PB7fWzSRiYPNL/sKDSnpKP7jfmVHP+B5cdwNvs2YZyyoX6IPdaJdmK4TytxifMzPuxsyr09Ww4ks
vr59Sp4dIMuF6ROxlwWraUuoI3gaAXV05uDar8SlFvaD/Mf4FUyvxPI51NQ9aEUT3iChkrJsFP3U
84ceMlAPyNXQoW2ug5Fk4cZWn0O4SN8BNdsKrqkI/JhJ73v4RiXThGEEozSVv85cbEd/MBc+D7Dw
egLZbJswMcYq8ZYP6dz3UrHnzqpczErchSsbXaSzU+JOHebEYnZ08CAnE9CxUj1bPNILcNwJ+a31
ybY8E8bgpFu9iXZAYM0mzFQ8ETCLQldz0Y08aXvTX1vuY+XdmVfqR16yyi84iKsc+6nAtAssGkgu
GPD+uyWFliLQaRfaSMwjs1KZMSO5+v1ICLfEMUpzTb1L5g1I+J+j0bc70uVlaJizVZLH814o0fvo
NdHxXNyQ+hUfoRkAI8mTgpd5CluiglzmgVppg6P2EfWTKQAM/2ertl3Eogjlu5dZSmC1yXyjN3BS
scupF4rrMQz1Cf0RcWuwzKF4SbbK2MIwBY4XyMET4PRqbCYHgy1RM33SE/YlXnavuZCKYbCjtyF9
/IENH+rrItx/R3VqrkjUnu0TU5pGPO5L35LDfPSklh4+/rhTGcXbDlS5lacUyAI2g81zG9Dn+8Wf
WUcpmTkIzticRwa5kCULCy+Mq1GPBGRJwfca2COkzBRx4K2h6L/t7j+u5TVrIC5CzrZRwJBwPSjp
o9dFbioqFHHXqmWN+A+t9dB36kg701ZWLC6qdKjGcyV9mcp26HpEhugfHeKFWaL9ewGpYcgg5uFm
aGC5gUa9//NZem/tvvHEtYTR4jt0YHvd+YMirbGLYC2RLI/y0n/JqDexqPI1NCmNeJxnqTh3Nlit
jvMc1R6/0+ow+grNMWFS9/8k+a2eHxWPGvOeLgYMjyGeZpdo/rftI8xIMWdzDQL0xP+mn9BMwpXU
M2pQdYJ8SQDtSz5D/bBk3jcZUxkykPRKP04w8LW33dC0EYFpqHG3bqS4DPvxalEmt6Fk80l/5JYI
0a1m5jEvYGdSyihjxVvau68mqHWS2tICng3JJIlwI0HDtK/VOFYEhqqpEP6uzPE6hikwfSczSkA4
puBYH0dPFCekgCDI3bOMRykqcQD654h9Fr3Nwe4elknmqpwi4v/yI9h5yJcDakXultwbR3OrWmFN
fBcAi4zsbzhvbbzv1U7C+orbBHVI4Wec7re4PBQXkMYiA6eER3tHQJgCDUdVUlvUPmic3eNBh+LS
ocvbDtO1YszUgM1NQxhrWgYSdt05wbRb03Vjge8BH6chqMtaF+TGGTfiZ45ffO7IaTmXs9WLLO7B
JU9xGZAUzTI2A9Axu94Q0rR0Afme9hyYa8Ycvx0nfyDjY1YbHBC7OyAf77CF6mAm6MImKY5DMBl+
yNh+4fENpK+NBswwzz/II8aXd9AD76jgNaHtM4W+Izf8TsoNqrtBXieA8N7kf/2lttn+S6ZH0uN9
PfOwrctpvWLklGR9pt/VcpjqL395tkVjIq5DQEPtfN7ps94lJ+UVQv+j1oNXM0p7XBnaBvD52drc
j0rfXaMjfQM0h2OksiPGSv8Azp5PCKibnCHSv3qrKTgHpjnpPpU9axpkftBGG7+gTqDui4XFK7ih
3R2p6WiNVsU/zNwcIBwGKWIQpOduilGvY3wPDpunIAClAt6P2tBA/rQ8HIFwNhP92dfusgqykg+C
04WfPRjfyIy+381v+FFEKnhH2G9cJmghsySqm6F6IiTr1md7pPuE1sGYnQ0hlAi0yAe1gmaTNH+z
BrrCx22D2vPDmBRUmQ1VUIz9rv3U+abAcB2/CXphJdBJhivJN/hgB8b9Xc6Q/EJF+Q574Mu8D7Cn
XcRLCAAZJ6Qz+/zYeJvN8h315z5TJgxXUn0dspm9GHDJ+TwUsiB09b5CSv9lQzN8Ujan9gdxaUOC
ry/C3inuCTkV6x8RmL2l6XfeF2yNOjmWGniU/7ctk46zkN4LjGdBisoobLhqFKEUiihLWwlSup0o
l1HR8TlLM6LXzQFbuDLetIFs1adwMp4ZdfRNhTd5MKDriMeDSKe8kfJ4vheTQquf9kvG5wiCX2Ay
45W+SfneG/Hyplx2bWIa7KyiPw3S+4M9tTE3oXkjgoHnxWI/qblWYCj27IBh8/hXu6gYk/zAX6So
TiAoATZakohxvabHeJax7q/pAfFPkF2Wm4BZzE+4+sDNoqGURXFGiIN5/dBkZtuYtJGsY0GZC8QJ
rXmMB0jBeQXsGqMN+QYXun/+UXyVtP5MU7nnnrvW1uXPvMXdNHg+MsZsZPSibmGosjHcu7FoQGdC
psdu0ZUwzaYVoLhqsbzGHLorgPI/ULQSIDrNUB436r8EiwXBxXKmnRkm5V3/11eBF1LLhk8oZHNV
Z0ZNcmt5VanYMGvnbuXR7xbQzQgWGso0kHnmAOgLfTbzPqf8RB77PcH39ppWWHcRJCTQ2eWiA4Gp
nfmlOePJuPB9hpksdMdSqUbzrNkNT5Lc/1o2oscuPkEey85IPjGgRVWOjoq6x4BEscJIISmPqPd+
mY3zRLbF2ljTNs91+ASijzJMXAnOrhoO1JiLlFGFATkE3apZq2plJMiSMBne1KaPCycX7lUvC4wb
jzTOx/7/SM27qGiVN6aQQUUmm363mq4MpAxTmnF+6qVSJZzxyO30EPHfs7AEboszeNAmsQp5U8Ys
FvOyE34UqGRTd4fegKwi611ZPqz0SDbjEGtHr9rmJ66PkPDjhtktam03IPYj/ZIn8Evgf5yzpMXd
SXOaJr03vkcFT6U78RJcb3MPjB04BJUw2UoYAIlD0JigaEuXozyG0alILWXrLd0+hn9/cMroYYpA
8di5mTO/iTJdCQMYNjm2MXle+n/181hoj0y7/eMMkfsJclcD+m+uTJCHB1pMhSwbL8cTUA4urWBy
outHRVS1w+HOMUwOKvL5tgalpHMACD9mNCv7gE6k/pcBl0opZWauXL647LhVkrsU5SKj/j9mYTTs
KpBNfMgmGlSdaixN8SfMTh0XvB3lXiSDBol4no2bjqO+6abF2mrnArzihTBje+LVJXYssr/embcZ
oeseRLUmWawQrk02OpsqwhsfkCqq5P+BnAHmlOZ+O9DVURFM12+SWa61xWu/YZZ6cqnMXV0CEyNM
wrMUjnzNuxZ6SOdTMGjMrXf20/7Kp8d2XbenwPcmh/uanMcJb7q/TxpM/gl38yL+/JeRZRxr6Les
TyOVC4ezdR+dhWcZDYThmy59/NvRbig3Pp97gimp8pOa0QCVaBxglD4Lu660Nv8unxUfqj0fPZYl
YqscPR6Yv025RCaP1dm1e0IsiN9MahmK/pVnYPLBZ14831c/O6BV2HW84mzid/bkb9lzY6tYjf3q
omZ4ayUK/JnsBXYRBmi0Cpkx8lxQeLKbLp6ATy1kMDevO4YoWdPSfWuF7YIkrGn1Fq1XXskI21Ah
1+9jIqiTUjRlRRUvkDj5NWyu0p4R2kMH0ncStVM9Yb8P5KHm/MbO3l1bSgvfGFTOqXdWViqQZ4ko
q4AW/3SHgzRRyLefBMVibbNB3bCG3d+OCCcAcJ3KBLl1pzTw0SZ1kGVKmr1FtRperXayLSphGS2w
N5f69rZfbPxPZgs+OFbuvWXIF65jD/sCB0gazvNY7Z9aM+3V9NA9Hg919YTsGMgrFbh3Hq9zPUIj
lSi/gXO4y4uNCG2YeWvw6bvXJuoUeB23Aqi+DLul7eumYbrPLq3KKcYUQo1O0j/QQIias+BxQtGP
vYeTI67R5NNTU5UOKJuSqFiLhePFDN7kVF4w5Q0wMQ6xjXc5yyQngQtTUYHkGdyZ125VUMrVzgdr
IGYKglgZR/uiNV64jiG4qGUCAr4MFPqpi0AwLxjkHXB2GPTBhoNKgl10WIyfZcLtWGG8klgsr1q8
wTTZKzGNJhyCtJZZa4zcPhTyqYc1u+QMPd6YA6jjEbn3UAq158EJZR0zFgBdN2BOSWR+anQDFgO5
DLS4TpErT/XtjsLDpgdLhGxiS1rgnh+MjY23Pxrd5zBXj44P/dPxYd/j8U0mWeJZ0mfgbXHwuVrP
S4uc/2bnzO2KJXPKXHBJs2U8QrdEbT4dQ1X9+BSW87oUiiyTpc0+4ZEOSyZTATti5GYHP8qBNJsp
t5/4LEvRr4+t8mvc977J70qkSE96Hks9l3GZhvugnrDiKH7EmjZP1v+97++ZBgnAFvxY1QfHE39t
DS0yfCSbCm+lWBPjnqK0iKLMZbHmsV1OmCZm6kRCE2+gMWhf5DoE8GhL46NMcGmjMNznfu4oP8JY
sJm4Up9nV5HwPMUQSz7PqmwT3IaFYhZmMX41ePokZFUuG35I9pepdttOxveDusZZ6n534MPVuBx0
qy5Kdg9bOoYRDV5HWppDvP+/bZWW7yyyXHgBMxoWvbhsBMbMnwxjT5TcJDWH6p3SKwyWUtr5irq0
5YAlNqtLIVsdQQgfVi1ngx0ObZd+E8jYIPT4C1/sN+fgzJgXKU2OUV9KLT0yYBvGNCcIwCznbAY7
dUPXvS2fzvRxFitixYpT0I0XVos/NEiCLeBmWSQLmZx5jJ0asm3EgVpHk8Gc4u+R9ptWfbpZx0iT
Xu9ul1wN3PgV1sX9sD1J1dXyfKu9zvS6+t1UiG5oktSV/OTCw4RfCnanaPLsm96b/oj06vWsgSzP
RyFLs5PSrzIp+y9z/8819VtEvYUsrY40n19xeDmrn1lSllC39mfaYp3sUXOYRyyiffQ56t7Q98PK
fX/SpAnZYyxJj2fkjuBVSU5qT48BN+ZJpq3xq1xevi42QXLJuonA8PhasgUrKjh0cjy5yXZ7DYi3
S3UYMp4NymOjniTDwYvTDjZWzt+JVmiFqKH43eNSUIJjrrE/ayVUYvqaINRuvrObuSmRno5Y1tSO
DELSEHw4m9+Q8nHqlQydjldyZmI5pUxyG6T59d7J/8YL/TMa/koNUFW4acK1IhqecEgFQPkoUTw7
utCfNo1yFDHQk9Itpde1V0rm9c5H9ztDo88VTwnUaXg++lDqxk/sBz54iKl2mW7PTjGGa84/DjrG
INRHp8h4GGbxZYZYeD7xFLhglmLYlFe6GV4vkCZ+SfXb/pJ5O+Db3Qe77H7e6T3wvT1JysjTlNWw
hqQXF7q/SnvvEuIVXpofP5pdxxjI9ILNXsKmpCLzJ6mQqc/uWkyGyIQTXK41sD6aizNR1Z+z/sam
pe/kgu9DitPEiDuzOYR7sGXmwHwwEiLcIgHSSBmZX0FNgbujsBLcVXEHUkmMroqxbHvd9Rni76tc
s/5z0HWustYMy9wD8MVJ0dkZ/fJM6zngqEidTup1Fqtm+y5KkoSlyRKxopcRPOgSaX7hWD7ko6RV
VUYS2pgKXtyIBAb4dLfhexQWZvZEBgIEqcrICC6XIc989iYRkF/fLliefJLVTGKWPF1ZhKU0Y35V
Z0QsDmo6bM/Cxl6lu08fuhX1Zyetjhu0ulasrVHPv/BloxpRLUjDg8YGctfxJ7Os5R3kqrfbTxsk
WnPNOW3s1Twr+xCiJM2VrzVdGa2dYt1ii7l3yYkyyrorPq2ULMK6SEMgCa2C+LPIgWvBLPZA4InE
KPUGCDsEQFWeBlRHcSuuWbp2BbaYxCpcNMbdFgqGACTg+eccE6r0OPmXgckIC1GzlJzzTAYpzf1h
pKaM810Uj/6wzUQl95PR11RqlM+PQoqoEGcoV5L7PrqdVDp6Uzmpvha3V1wu6xu/7ANXY1UxgBdb
BMQ/mwn0IX/hIzGRvti1GYRVFStNGHRjDapshSwwQFtAf+xcIUaNeqdjkaz7J0hsRskr0COqUZCK
h30F0ujwf2g5NfxEeNOrrtoaWJqYcG0020l0g60X1++3uZw+hgPUVYGFqpTxEBZ9k7PCjTKtTguB
d0c0zr6+BMcCNJH3XQoXFTS4ioTC/Q527iDd9Rs/vX/PoHQ+LwnNSwUs3nqU0TI/aAmLE7JUT3QY
Q+5K+jGu8Xi64aQs7se2JVBRajS6fD7+mnbBEHyi6M7fIK9CYyEQbNX5+lJnWzriVmWmLezjeV/J
k452eE+8oaV6UVuYWdLH9M/KP6TtGh0rVO1AjaANNSQmyUz6TJ2mvFz33iJdn6JKanyXcpfv88NW
NvXe2PlCmXFVROI+Dwj/ymqHW6kfpj1cAI2Yp36LFIc44Om/jhEb/9D2cIEN33OxqYdVymZkKgqc
U3o17AreZddAvfiTtMtRrvpFWlqgFAXxlggZynOLJlndq5jSWKlviH2o1fYvoFLNKcrzxUVG0Fgr
1rACHEB7fpu0CMaLsndkiywsiFU8LZOnloAtEG0gT5Vr2TpOTSqNwYk+Vl7qNliXdH1Uftb7hdSg
dvDCiL4pbpF3dPJdANYf7dDV6swK8EmZu/1kzxzzHq+5dl9AT5emgUiuPNupCcsLD5Q1VIyGCB8n
RX+8t2bdw32AEbJsw8D2x3wMUWs9N4BFhqqmgH2vUzmtkDwuG/kfExrPbrmQJ2xaRpKB0ME477Si
AC2ApAww4EO8B6KBbtr8lFyhYLAhFESju1c6P6uS/KGW4Ds7jfp6PjcGzt6CDHOgHlFHLN3lS+83
nqK40fE2eTump8YslGffXWuw0s7VB8YWsXZvu5voTEZe6go9e9mhBbkVdULhCAQIjhPQmXM0iIeM
GtEFSRXNIXCricHfCrQ7ZH1GP/Mb5me/33Z6hIQqbRsmvv9zCIAT4M5UYCgHqqjoNmsmpPP0SL6a
2bkUZp824ezPz5neJjnVHFLyaGvHR5B/vxJSnWQmVREOJGEfvGYt4nOQ3vAUka4pl4GnDOp+pxpF
UV0WlNQLZnFP6uF/lqtpwPLyuO031mdHDdjWpwTlhlNuLe/eW5ta9FYo8n17dtH1D817TnkJ+Ffw
IKkFPwwUI6OtyCO/6RmTjousyWaIjELt6sVPKGonupv+Br7aVWDcrb9vI5IVicCENgMH1tmHvIXe
hLOauMIdfHUZfyRXlyZ4vgGIHWfiUo12IcBJKdWQLok2l4RTZu2vBoQFzFvWMAkUngMGZ7syUlpI
N6LK7LLUUFjLi09cQC8g989BCeMCkfyQCSmfRjFHhLi/udKFcd0O1roKOdv9pCzSuR/PgiwgSqB7
cfzF8PF+hmZvzmoVAtxBGcJXQDK+ZadvO+olw5zxvDIf2svVL0NOObyyvq9KE0r7Bp7RHmrU3l8V
JESx8AocoxazxqUlxVPGSvg1Ao0RKykK4m67oGB1OvRMjjoTVC0mPJLvcyubrfVa8v+o67TsBers
rGAHKxlqyT3IO+V3DvRrwwfyQ5eiYFl3ip+FgOy3xnOcnrwUNOf9Q7Mndhkewe9jkV2HSnO+Mce8
KSWf8yTOnyhRNJ7V43um5w8L5bFHL4Kt44oufBNCgwVap/S4o/D70e/H2BMnYriCs0PF8j98tg/z
8ygECX7igR+btYVpOS1xpWccxfS+9Z8XJnqg3hJGJ2wG2aBdXSnXnXl3DrG0tAmKdCvtbA3soe57
BJQuEJKku2s71N4Kn5zcg5enU1fkdifF48BX5GnRCWPiPnOzPkCL44w6MVRH0WxxxspQzqOBw59i
Wu5uN6SIsSiGgcJKwti6u1kRVvZK78Ps0UvRwg+LHLQPQU3xXkdAjB2XF9E+WTsH51krxd90c2sf
jVLYuVxtjRPd7VR2w2623jN26LO5nxOehKbLPpGehziF8IYWTBrhT9G/XL1IrZjTBwnYKbzscun2
cEhmIP2JCrZzUGmIbK5Kv+DT3uSgLnjzUXGjZ8J2UZ7U4FHwv/NM9bIIUpGxr8m7PgDE8h1E8Lnt
GBBjE1iYi6ZwDbO+JQr5BFYdLw4BzczhndICbcI4nB+V+5tYjYFw2351p5sau3lAB1sWdbmiuUtI
l+gDUCKOTQerNOc33mtSStydhlxV7yGoCq9CSVeIwTpmP+jsQRFQ4EBTJWXe1hYd0LoS/hkQ2BXe
cUToU4uPZwfo3hvCU0f5qp6koz0uRdfRqhk8nLgRe3K06I5zlgQ5AUiqu84kZ4lNHiOQzW352yfp
SCKEpSk0UkZtNglzIggySqBhAy6ITjW9KHW3VuG1Rq2RgEoIOorJqaQN8mR7xWqfPy4DBO7SAQWQ
o0hV7cCwLaQAmBiKWCzPsq/kKRIdgAEMZ8i3X2rcHj0UXbr2iQAIny2aqER6MWrIh9qATZXDpLu6
GOf2m2Zq9guO4ZBEvPWS3Ab91/DeWTScWmBH9Yo+hYqdea69hmCvP8oJCVKKKLE/bSS8Djeeer0P
eSslOlfaj+G7DH2bTiCfJO6v0AVhvj+o4JyKnd2gbNRPEmdEwvVo5ibBVStlBU4nb2DMn7gGi3S0
P/t1H6/RVlBBiIy/otwlb/g38eibYdhr8x7f72at020O66W0J3/GoWelOXOatnntroWtAUgyXzi3
jOWrds9CkZOQeQoBVEEGOCC/ok6zZ5k1ffXRe2jI1bkCC8wzE5DaT+46JqMpJ1fb5uNA0gKEjjOm
hWkD6x6Rr068xaa4PinkHUGUcoMywlXtvxz47q+zK9Ns+qp5MwGekOJU9Z7a6F/+OLSagx0yWbzK
hR3hG9VQhnPAdbYwEMRYdQToKvzPDyqtb7TvXHAdRb3kz0H8LYJ/z2y9acSHrZTfZoxe070XtzFS
sIQzbK/Dox1YBZ7y5oSmv4Snj2D2AkC7UGoVWkg+RoxGyTIGUASNIQXze0kIPTkO/DCRCOKHYrhb
kXtflziaXaOTA+X6U3GVJwPG5oopM854x6kAvDP2F6EMOKE0djP1xvwYUK7N+mYWRzWULA8UGn+H
78tdb17GIlqk8ekuGtlAndBHwFV+RtwnO44eF7LFgKUDvZWD0EDK7YP7lnpvn76TZZaSSd44xvrF
xDcwQ+woaRODcmy9+9PWCSiFDocju1VoGPLRWy9n0RVDuJhEUyASrHh9rqBbdsP/WvA0EhEa4rkt
SiV2Os6+34cBvzrJNREPDOIc+EzFWfbElthnm8b6MKj6DBL97tmQqGO7yorkWHXiOk/nX85l0utN
bBVz0IL/kDD8c4ppUZP4SFuVLgqZynJTE9neDV4nVlcKMVSxZsJ9l4iQTLENuGA5NVGyTxSjSbN2
puNiy8IH2if6Rfgkg497cVcQug0L9YYpJSLnLcSDaBAvRge+90nXC28pKScAQVAMrFUNt4Oo0mVH
UtDNiwwaey2vLX0pCNdWxTPpy7CzoAQ2oZYRPI8mPJZXdnKxItKwGX2sXfR/ZtkouMSZnBFUNSrr
CHAANn99AUBqCiwE9b9tUmOIBVey5wbkdGlJHLQJbgQ/dpw3b6j0VsN7yHRz1NjW1x45sWxfkpL9
dnTCq7+qmrk8eAXq0SRol/RmGsEZW2snjKdpPIqLOR6wAOF1qpwkOKumtIiGen8BDCUlqWxdVJNh
spY8+RoQ4XmnVa+U2VV7Ip1WWIm4s1rClYJ5i7gAoNz3G6ZwziS6j6x7buAfPuHGnU7ERZ/t2J6f
+4paXQcf+iJTHqeyHw6KG9qvpvL/ex+SANyDfCCdorjMyuqULJEf4XhQYhoaxQnXsJQyWC0bi8g4
TmzpekAv7j8mZI4070zh+a2yXS5RyT0PJbiq8ColTRIEboEGTSAcdUO9LDTh4YIu4v6p+LdDQZ78
qKTBNqyuWUUgAZdB5JKKApTfGuKHU7PxAi48FRba3CK02otHVl67YNYGCfBkG9gSmBp+P1+yiB/k
FAEM5LoNQtKaS6ninLuUheMEFXIP11OU/535IHcTW4dWR8D7pjaC8g2n0tPnOYT+YLBF0KKfREpT
KvS+VW8MMN08Ck7dF3JphlApzNTGtLKLDyztDjxDLFx6Y1eVcwFf2DV1X7ZstQsU50rlZhG7uOBL
PKQA+AzIjW+TmNxdCiPGO7OqLfnOCnE9q7Ukr2ZCUNnn/6/etvF5cyH9rMorKUBqio5V2RKS//cJ
NRW83caNL5bLxqmvhH/s4nI5R58yHno89WNAFQ/AjQ2OOS1K28tPJWNXIOe7PVNUvgH9t6xFRRdK
9muJ6fU8/DDSO0zKkzXWc1eVLdjKRIBNNlEKrUBA++aRH27yX26BxIo1+BN68RmjcW9EQZTMDvWk
3IvXhiwl66yJ4rtocgY29OJ92z0FY+HBgRmrhpVl3+kaIMZLYo9TroHQ/85Nih7KEuifC2dex7HV
xR+swr/oIayVozhtZT5mGVo2I4iYowFSqbW5buVI3d4aJ/an3qD0d3kW/HZx2N314bPVmKSbbtuJ
He5laU6bcJUo63dv4WxFJdg3AGBLfHnUTS1YGdZeBLY2X8MKd8au2PqQF9MvUBgBHvILdDUfLWj+
THNDz/AciWDGC0zQ/gop8bo/HShm6HHKsqm6p2vT5KsdV9f+fnIwseDXOeiHSLNTVv0MEZZbRy1r
thfNb4hJtP68pWgZF0RId2Tsdb6F84cdbbP/p7UCX9RodVhjWKaFZoc0UiN+xBq+fJjgyG3QAJgk
5bBUyCADTus6wlpAMgckuerB2rnDo981n27dRz/GRuK5e20BFQhyb150NjZsJvqXyaebOkyVN/Ba
q4MbsGD1nRq+GA75I/vMJdzDAqW08CegMzPUto/YGZR/W7OMGgg38oP7vKvvtoGsmMDyPRwx8tmH
XPOBTKjAxT288vf/5xl5bRlKujtlHy2nH+PIZwWMFZyChsRX6ey5KAUB5BHKmddV0wriZ7zOWbEt
n4UsC0nMhVckaIJLh8EJNYlId2rbrcDvuxXs5lZbNMY4JsRrkLr/ZJsa279984q9KvrojyL2Ida/
hodZQrTyV1IqXzXj+yb34GC7VhG/0tpa0dyplagXblUh6PYqU2+OISFX2HIDLFMq1qysUs3GYBjN
xRbRyEsg2v6QImZ5HvNMjXdcWSD1hI+mRPLoUVm/eWFSo7f75A1CWZEeoOkOK3wXUvRPYLlNW/xV
CmdvvDGv1HRRg1WNIDiwQwH+QttJspBYIhdwlaVW/WkhtzertXMNsMWH7tB0X1RxzK0GRfSDwvJ3
+YttIDe/AYuM7FwuoV1T/WfOrtVl0EXgz3nWfuYjEuLjUuiq1eKnmkJnG8D9ftrWwQ1Sxsh3TGgS
BHPrC78cPBga24LPxok1dv42Sv0nj0Kd7W+LvY30Fg+YM+nCb1/DIleJBFc31zFdw7yLMKlhVgjp
EvQvE7gExj+wpLqmWZu/vEmFtUxj7lAZAW8yHBmyOnnt+juVOAW9v+XX+p75qLJvK9QqX4AgGH7l
qDH44YZBrrYkse0V4F1/jRh4w1M7uDEnppKt9nJclJlorbeq7+J/Ovh/BEScRWmlmWEFBDJXts2i
ewT+31vxSByubn4/VnCDQPEp9H1qlj9kuJphTb/240BIfosq7BfmaUS5aWJc16sSVcEWfzLHjXka
kWVX44F/totYgVX/K4iK9fX+CsFcCBJYUd0fwMe27bjnIUQOPhoKAw48ot70BYeHT5PEvQmFsevG
2zcjr2DRw58nhBWlyY/q/9KhJeSMtajj/35ea5M9QNpJ6jLKgQp3ailda8XUtrLRZzx6IevB9227
H6Hf2aiBeosqKpxzcBKXg3P7lXtLx+H62y+vUhv6uQ1AMIuYUV7i/mwf41QcdX6IpCSUx/IHq2ua
hT9Os2xCUaDvjVOy0LIKsB5QtNApv7cMIS3bkxQ6rbCgjXfLOTJjVuZquUE26OUzkI+iKo1d6DXk
wFrO6TzkLh/5rvShjg3N4NvfmMOGUR+lBr1V459Z8C4HMbBz/z0kruEsRSRTV/SKiZzbFO41gKWH
sSj5F603c+I10so0cskEYLZWGTq960T4yCypOMGXMyk9kGcIPqFAU+kgy9vRm2IWnRT3toAuNVaJ
03lFmbynw5bIP4v6fveh72QgT/J0MhALWCl+DOA01y5Qw79BoT2d7cVlqMHwR3j79aCjh5Pf65cW
Rzo1q4ABNDshrwIZ/rfXzEHMzteqHmMcCLc/1uhj9fEFEuQwU4N9u2/UT2LayLRSwRcxyxK6cofc
7rHk7QR3tCeyUO+PTvB9jw8DeziJ7kQz6YNGBtM3uZ+8lDyi41VBcyM7l45bzxqXooo0GyAnRQZ/
vKbhvZiY02f5Am6XdzPjqitPcTkMLLvzTAWDLxYYelh87PKE0sEF+RNxfxQbSx5W1WBedRYW04AU
gN/6rNgKuQzuqwqksn1JNOzirz7/lgRgyiM0230XFfZRlAAkcCm0V56lCHlChlSt6khWGV3Q/S4D
s4S1x3GqLFdLHsb7XFNvIwqNfDN5HNoG1Xne5SeWIDa8Z1DOUiNZzJBXiGMdZmpSYjfx4sJOTL+J
FVQSSmH62LXW7X0MPezdpIwn360mOEun/TgL500EvM41aVllsaEmxIWX7KBlk6OPPol+JA+I0WG8
bkElOpY4XnZ5beygdlGI2u+VWsDHgv3VgWDsjl/gRQ9mQGHKCFUVhIcM1SfR0B/2UzmBRvvh81I0
rPpujpdpAW9TjuJhe3lzDxgkNfYHa5ME76/XOGs89M1c57maCdGGtEe9HIT4nA2Y+vp3idlU8Bqu
+Bpv29jMkLXEfxhm6mUj5LoNYVi5bikp2yZ09x5u9QROcDD0EnZuAAxKZr0zQWkYsGPFjoBUdKYu
vPC3axOXYTQv1xlO2morIx68ZBOmia+Yb0pC/4meq/ydLzfm7/PudX8bvTFSgnRvriasLTOcTzgc
teTaioKwL3XYAudlaXA9YT2IEBpx3HARznMry+jwMN9M0unJHVART4N9L8dWQpnINcUtTfRloK76
oSgyNcr26wnydRm8wnem5zqh5ut0uGfue2ede902S4VMWCkU4qyqatfqozvA7zJsY7i6G3gfeZGM
HSF8AFpEzd5XExpYw799xh+E/604oVavF9VfqkZyEykURhPSlR5JqbVU9pG5ytduSCfqoZtVdChC
H8zYpeBzZhwj5qw+7EkjwvL7A3CBBImk15XSFxOPhCDfN7+7SHvIlynKNlnE1NYgspblEyrocGwT
73U1BAMRNwixHPVeTtHRuMUrejNBCXwMH4ugVm0B609FEDwlsW2S0826Tt7EEIXkXHn8Le6XxD4o
640SkAUdmTDBrEKXOjKaPmx1KUmdoUTovgINEsviapOKkwxjZGWKcxl4FxF1rcUosPE5ZtBeGOyh
VWkTYa/IAPwOKYXGkt+eIdfdlgxA7h89hUcLd7sHspYRL9DMNsFLUgE3hzyeHAR4zhkPFGKghwAo
WOUaL/mERkOQGVUeDOYZr+0vbK7BOIgfXtg9cLgB6L5SHFJ2Lp30Kds4tSZ3++DXuA5HC4Z49oA7
HGeKgoumbBzUD+uQ4HyrmmePvpAJlELucKG4BYB3YRKtzKfUltRWWuw+6FYezNoLqD/zhfXpHpOa
sTMk9CMV/F9wSoeM5MTFAPWT12DNc9RmrEge4ShLDdKyB/Q0gKcKovJ6G6MtGPS+/aZCNszQiepV
AS9zKx0yVsYuQ2CxQsR4WB5/G6FuAQQ3qH/UmKYqErwgdgr7DUT6ETNjyA4l5HK6xKmv71e33l5X
W1GeVVLfaCsn8KXNLF5Qrfe+adbFsg4+0hTygruzs3x/99uipDWxhHAtkIvpOIwEZzjs4i28Lxil
2eJTu4zBkrUjw5GmeFItg7fMr2wC3NnWj9cZYG1E7JnL+ZaBbXnqxrKWZnxCigRyLjvvQ/2FENNI
ALnSjKWQ8YuWn6Cu0bnhHPxn5KfKxqH+e7rZNmn6x8qEHA7tPGbiKm+OxQV8lN6GTFGJGPnw/Sht
yye/jJoHC9KoMTMNt4pW1TYPXKNMYZD87ShSJyeJJNxAGoE/ZZnLl1Fj/u5LIpb8jWYwLmha4qCv
rI+32w8MEo6e3yrG0sirD27y0+n2cjUI14oXtl2wZ2Gsp7zd468U9y2AZtfiLHijoogIBP6Z3mmS
0XrTZq40xRlLot+7HSy3GPhdLmAobsZ+pnWLE2zDAUCVFR7fl6iOPVAidHOkPpIY27LybVbFhH6h
f6vdIDvkWx4gg1L9OQPe0fMFb5LGA0JXHihdLz+2oYYuFRxcAv1Wke+VpV/790L9pqYc31hQ19Ta
Do17NjzoBgDYhgZL+UEc4DQIfZPsxTXRqo6EHEGe6ZgiuUmVTTCjAhZBGT4p2ww3mgnWh1s8kpho
ZWQjxYVtfQ7+h+YTbF4N6OItdLyEny8eRaIt7xf41fmqScnadhwQXOfAjgX42j4D5MGTmLaFpUcV
SczbwRqiWekTMKfoFBH9ghJAUC2Bu/Bc7uLBlqwaMHEdcpm+h1kKtAwp6kMVWZy+rPPtTajcytiw
nMLFSeQ1x5ZdVaawoZTeevqSh6xY62m2iEXId+CrncBMhkxdWB+sklsrMycfxFzByIrS+97kby5a
VsBdti6PWcCP0HarlYTUxep4m2HzhRdst6zr2Z6ijIDCkJBzqwQTOZ5P14A4TLvFedkarUfOXvzc
79Sg8OsFT4/NpTSyqr2gxF+YVDEJxOW1QNG6S3bheqHQqdyQUOsos4/x11/YMHDE7WA5O8R9Imi8
GGHnJJI1Xte3cNd25Eo7c+zUvsE6q/47fKOt1OSFOZDwrszRmp3tM4Wh1bV9ReCwp4Fms3/RWR9k
ySPBjfb4Nljum+sThTj4Jy75eUiRx+fqC5OhBK7SfQoBg2gjx7JBQ2uUntpAHmi4POoXzl+EhGgz
Y/modJlYl86WmgdwVPMiiDrK6rXNYgfgUXMi2dtgmZOFQu9iOOq6d2jF8KpniMBQdLkO3W9pZgYf
Tv4PpAY7gLOwBq0CUgRabH+oLPdB3sR3OubDsx5+tgIINX+OwTnvvb5H4xqQ+xeXrAyi0mu9YpaP
wnYumhQzdztSB6XOkA7G1An3JbZu/MGouc911rTuSc+WlAW46cpfh8+AR5KY5IdNOzQNPWi5kQWm
HiCP8rf3Tc7nUb/2sTYVyc58tnj2VKrEVnDixZlhooXKnUohMM0jXQWNB9phUw8Y3cdbHK5EFgys
Hu5E0XYCX2IPw01yGIQAJKpGNOxN2u1+hps8SLOqHX52X4+HknWsTb7zG5qImGVDOPNUgfLhdc7X
ElcyTdrf8peDGO4gGb7lvsEg1b+5/wJpZaUd0JXuXehl4vXhZ/kiqbsOq7ROflo/FJVxukXRutTj
hk7cCH4cY0tQN3crKTdYdMrLQ5c1xLOS2bI3E1LUkcNysxUNyaUk6wrAgAQERyYIrls5SqE7f6NA
NM1ENdi7IF3317Xc5DvBdPrbgYSz6P3w3trfe+UamMDT6vMBFlNO3L88lVJK6aAO5ADKfIn2S2sF
iW/SdS70VBgkhZGJiAn/V3gCFR8ZXTxuKLBiOKCG2Rlt+PsLuWnvam6JCpMbydnYsg9u8lWinecZ
HcVhRHTiYkTMs5+tkByBGD/xDBG41Hml8s6xDAG0MY1W6HUBnRjK3XNTIVYgUIhNKKPUmLwIp1IM
r9rbZRKKkREGTvQ71ZScOF+qgd/KyUdT9/tRyG8rQRbZBSHrI+RbC9j3r/aRGi41uAT0qceHlQoc
y+Gx/c49IO/hVk8ZSm9dMM2rnTWH57nj4cyygKYC9xoXLSTveMDPxUMJxE3VGYMuUg+U9x89EYT0
Gigy419mg+2nLoYOZGfVJTpr5ODX5r5X425n2ybbjpjWwNXZH2Xi2AtrSGlqB7A3gPvv/68P8PRe
ocIbVKW70YetCRQAcPV4I3S7fHZuL+OvR4WuiJm2HOYKoCdCgHaLNknI+iywzhihT/mbCB0q6Oaj
Dmn6VRzBRdce2C/eaWDHkqEZd9tgIzP9pBVGhgG7qk/DfbCmjGaGTOpjq56nQQ9qnVhiPxT2YuhF
abHHxPALtq7aRbH3HvWMjnswYt0o64Q7WYBVCKFj9UUxIqydwImVth/LyHavapkiO/SvS9AFr4AO
s8p4Gp025R+sN1anml/y9Opk6TYTe8P/B3JrXEJb135j1oMs3o42mKsBvJmpEWfwk/KJKnRkWPGX
6TFya3qbqaU9jzeiDn5YHOc8VshsAou2b5Vf9fkNp23kfQWjLc15N9lYgraDdsh9Ssq3TlToq7Is
/8WipLBQOEWXGSJqzu2kjyS0gVB6UAoh6iWA++4GtmaFl/qY9KZFz68kP3/5BkBOztTOshy6olc3
LkaIUYEDUQ5Y4wHGMYi9SurLY98V19FUZlZ61CW+OctpkUJhCoiOY7DyvB6vXF3gJvDED8tV5r9f
+dC2uzzW5vHo/KwSPIAxKflI66vOdt8t9lvzsm5EeKQB7nXkq+8zWJHSlLFk6+msJiB45frLeTPp
Tdc7LuRdKrKYL7mjD15yPCQy8vOv0Tm98vG8P5LuFff0oS7BCpbZzllpdfn5ruWBvQYcdS0y/JD7
qsYHLuqxL9EcKXhxhjSlYELF4rZ8h3DYXNF1GIC/5LrTpA6iH0tW6IQXefUmYX6mLCgQEbp2tTQG
5KCyF9VFT1jqnPQVTe+9JB01IJ6o80ycAxXcm/GDV+GybKhiFGpSRbDHn8a48lamOS1vrPwFZANP
BW/+bu2ufFkH/y6wKEqJcSqcLXcSgvyhetdLfNiiKGAyU3ZyGow6sAHb6bs7YExRom4h7rnV5kB2
aMqg1MFSuersCeuHOxCeOm2Mmuw3kF/5SM0PXLlJPAEI4VCR5kH2ATJoiJO500t3i5Renk5oDv0H
iqjO8gvLfVaWPWLfOW2+2xM1EITOTv0t1zcgnYzMI68LqzsH9szoPJJ6Dz4/IhQFzNmCRjX8tY5/
wINHbDRyx93gnmRZJ4jHhqj+kdvWURiylqKuEp3ad2DYNrZYO05tdGK60ve6Kfv5B7YQfx23rXFH
VyDgnpIMm63T3/qmNEre+pNFMs+8JgT6FpZbnyoU6uGFLIifqnuhFvmRqIIYicSf7gsTPsx7kvXk
1pw8HKcfpYS3NerR+PgPcLPsKNZ+yimgVdZraqpbMZx0x3c+29Nh5ByUTAchA6/4eWahEvwOnN93
lyM+03CjBDqLk5Sry9CFnBxMipNztQHq0PLu0QFX7AjP+WzeDhl8d8s+Snd5FkS7TfsmZwLMYb25
JYMsr/S5nnmB/dAr179/Em8pLIBcuQSlEVd6E5Niv4ny6fZpzNMA1PxnjA4LTW5xhIOuihtIgwU4
CHkisapcBErzl4rddRtXIPqYg6vG602o90HKFjB0+zjpV69n7ik8XJAScK5hoIA/j5yasWhoyFcP
8RCXJXBI8BBJhamccuof38otdifABbSGZsoVXzAWnzABmKjwH0/8g/HY7n8w+ZXUeRZQWi+GypRi
tn4DeAkUs1JkeftM2TATUwaYX6r6IsF/HHjCBK7m3HNmM8rMyfSWVaoQi+qklZfyDVc8XYBBGXo9
TlT9pHSUCQdIrnmfzYPXHEKJdeejsg0ii5xTG51YVU/xFw3ls7Go6fZLnDtE9/oGTfvIxuICu7uI
O1zD4gzygT04X8ycUBGY/tViaGGg2ryETvokVD8evP3eKB6j/wKXxx1XXt9QvRaMAApjVi1gbPpi
7PBy7OxVCV3MOBgvcNNqesa2Czx83yC2AH4DloNHyrqT89bR8s9m8bxVRrkvx+G+BXIhR/2eckZj
YLkAaiNKp+0AI2sussrB8dhU/ZfJRayYtkBqzkr8cTnmLpgEojOw2NqpCYJVeB0fsLozr44CDPet
ZlqM6AuIQ7TjWeYN1X+ra14RhmODmY1BwEqZpm6h2uxbk9W+lSlUZeP0wZGQAEioYrVyUIFL+hLs
LiIao7yOWeTFJbisbnCOISmr3iMI19LVydJ4qN5RDUBWCWgaiIkEuO4XyzsbQNFIdZoyShanu6pd
Ne5m6QmIxK4sX016uoHquEUslCTrTZIJTOyv/cstKG1/gPG5qlZrlpYZk6H5JsGsqUn+gfVAicgA
/JCSGJ13YSfoSYyEEmincZHp6+gykG2WQ4n/8Ukd5dxb96JYhIjMr65raeYFuHMjOP5bUdmSOAWI
T4heuVgbNX41pC3vfnh7OUPnW+uVJR9eLvjI9EttBn0tNk6u5CdJQk46LMZAmPtaiYtXpLhzab/A
WIf40kCey1i7y/VmPgj8kqi+cbNF1PS69SYZk68dLsufJmb3MV2nc4Gp7iPTcHXdcvzt/g0ZvUV1
61YI5kEDEIN1bIykOOJCilH95KAKbI5mCrler+vRlbS923mNVDFuzsxqR1VPMwSSdi8eGwQ5LQvA
BsvHiF57sQLPM+eSdP/HB4AkDoPVrdvDw6UMs2AXFmzIN5s7umoyruVuO/8eEwsod+wXsV7uDikk
M6j4mqhuqKV7OqxxrYQ8UG/laHZjVmVNmBCHL38d3PZbOY4JHGIgruQ/V/KimAFrJRWuL3CCDizu
VjDnNhi9p8t7EL60dT+kNgWALD+tRoJ4qIFToFZx7DycHgH+7cDPqbKbFvSdaENg2XBUYLavkSXG
RIcYvr607L3w3Y2cPC1NSpLlpxqFPj2ydrgTVhGMBYSp1tgHt6q7F9MQQICnshTgK8l884k/tM40
aOGp5SBOQWI72qcvoOG3oMu4VOwoZp2Sm1ioosLXq3etMHYycxMLW8lP0/FSZl4lzRLXzeqnZsHq
5cawabpE4/JudyGUK9OZlGbB64EEKPn2xMxAveW0xpzgVEZmp9aQ53LsGybwv27cow8KLZ08z0+Z
J9WQut/sVd8wQdDe9+VoPrkJi6jZgVqWHNA2YVsubyE4YggG6DQU2aHTdNm9+mDDEn5iE7pxJbWa
Yk5nstSOAY92AVHiUxH74M3zn86ndGrSROSVx5Mgfkp8sIIb0g3s6260iFf1UqJbIx5hBJqrXoGQ
hO+72mBjkRPOUx6na9NQAAIesWx6YwLt3Jgq4BOfYtT3oSHChViCb0YtWXv9DTm0i3vO49SR42Wa
q3QBY4kH+kqzpyHlgu0HR7cnX9BnfErcWSHke/i/QID+3BWhN8kiQY6ua1A/+qyX6t81DgKGXUiz
JFRARAvRvKdJYnTcJNw0DjfRwkwy+CHV9++/0hYiOzEHr4gnZP30G6+1+FTD9brP6UVD8tGQqFBn
Kuy3xWuYV0LM8zj7LJPBb93h5RpxHsKbjRrgMuHvrQWJx4SIAveo3yLJfvokMzhKvOctzB/htdi4
5XCMt/iXAZrgaLX/i9KWPgSNS7t7lFgT+k/ET8JiKBtm4yIyoLGdELYhttzYCiwYmqD3m8CiXKYV
w+b+HyyCHI4gDYJdMqtX0xNZBbYd7jilkp2Pa22VPZDYolYj+Y80fYEtt2NxgeSiy5+KB4sZd3I7
XXPZljaTjKKARL3cB79m5dh7Jo8NWL+kFT6QzSJqkqD6DBSS0W9XrcJsiwmEt6BnAJG1TJuaeKSs
NJ1a1VBDXqHPDVv8PS0rR0bk8MhlPWsUBKCLDf4tbywgLSsFZUvwUIsPEsSpdxOuuqkrFddoAuvr
yOMWZ6Ogwac7VtbOidqXxxwbXAZ9V6T536BShh/QR6wp9EUINiB1ltjFi0RCbXm34ZijGgouhhj5
eSXhIehpv/2VbhjDcZ/zBXUF4cGZtNyxhb3/Dov8Gs64OWY5YM93zn1TF+kRsGKfWvNstKVGUh5q
cBN0V33uu1k4k18YWttJiizakBRJCpOcez7wdt0vmFOoJW4dCSpEWlvF+yPUi47X+RNonjdiI2vZ
jYACHI78JEbv9foRdlSKHjwyOqQiSnIfcIAUVfaMCqdehUKKDn1QMlQOwhNR5en/AXtwXP8nILWl
MwdP/EQ72McTzFtW9i9LWDYIvvre9OPOA7QI64vI8AmhKml3r/nlCiZjZ890omemeZ/1O6Nv5Ztg
JI6cbI3tJWZ0UTB99Lc3LQn1yl8Y/TZyaXn4ljU4Ju0HyVZ9B7IOLKb0OfgKPa9SWlr9w+rUivrP
xtTrrLRLrLcrBMvtgh1GgaUYLFsqRiCyf2DSHp/16ZLvg3UDmMB4Hp9G1HThChu4Q2ruteDNmegm
kaOZoVOciEn+2ioUQ3gfnNDwFBagc/D3o5pjeZOm3wdkaAnfBn/RBcLuyhBv1iZkuzQEsH56IjDZ
ExKsFHmtcveqR6ibufVVPLWUtPFxy2XrulMHKARtV2jHp3V0AvIpizPGjEdE20PFb/NTN1jGZ/nO
V64x1KUqx3/ws0UdGyv69UoQ0I/L5fVdh2W2zAj3w3RAZfqKTbAI9h52/34Wz9PROxnmRXZU7XV+
AhbMarBZJSSIbcba6Pv1KOqTFpBCcGumAN7O7NkSJU49x2PFjrXU+8f62Ib0/hnVFi6LRbNpFfST
tZCee6gBuHt5JVfV7nuBMAx0FNVpREdO8ub/9/bIfHYjn/kQY1XS8Ummjgy8BCejTjE+bhxHE74g
z3Kkao+kA2XNjy7o8PTOiksN+d2ZMRBM1mRiD2ALmVMbHthhMUBT/7NdzjIAKmFYBt0MMlrvPCBS
CegpXs11noNq96owClpq/s2evGu8D8zPLwBvI9flkw/ATjD37Y7Xz4X6U/LV3AO+JzoGfwzkigxN
vEEY4LwcRMQjpwSYMPGIUYes6vGyF/T2MNy0vwdWrsc9ujugeI0NLsYbajtSbFLoOFTZSg58SN9L
HTFtsvodMpuj4xDEQvIiH6KWt5+lP5ZZ1ZcGEGiDynvuDqBZBvwUVX0qDAe4h+rDxR5Dgz2HfslI
e10qbTr0Li+rYv45eIFWNHM8PbwKDXlKTTV23R9w5f/Zhu7mAfPlO3U296mGN6irfjWMZ1Y3HaCe
cK1sTit9DmKfphoL3QBtVsLy1LOYx9D5DrhQuVCOkJ+MfYRNYzbeYQQVH3HoYVHBYagKilNuPPXi
L4lNgBO6wjPiPfar35NFVrw/o9hYjiz6ZOLGoD6fdw4kUZky3J17Av9rYwJi2+GwCfbfZ+CITTGF
tFRUoCyqLi+E8qtpLzvBiWUQSR5kmNDVkT2dd41OqMBIelwT6fAlQ6xxfToCXsi6oC0PEFZo7ux7
yrXgnjf/RISuNQjdeah8UCCAU5+AQggkMANTLYIIEGaiPspUkugUUvEHtjgGny7+S9Oy5MR4uUnb
qpydlz63rJzdYchZYLTulnGY//vFaHJquy1hofwQm+6jZZEchDOCbGRGEl3C/lqNkZ4xJght1tTo
iub9LR8BL8yZ/KY1BiwSjMILVqH5DSlWTVnttwgAJQzNz9O7aak5KzWjuRrp6VmiS4Bzg4nBUpHr
s0XV91ai1Y7grZxNcWMHuPCG82q3z9z/RKkpctRF9xdxzls2GF60tjKpG7lu/K+qTdPvuUJb5pwa
bhBDyTZaHEhlhOw2gqefJBDdjWA+7X1/pHdd4iieLQZYlZghyZ2cCk5tpDqmH5/XWBKKMD/5+VWM
ph6xrUEVrgZl+OUBRMmYJUG1gnh+Yhcx77KJ8c9+Vfl1u21JDQiFGOn9/qrs2oHwpGFjsIDvZg8d
FAPkqKYqpmdGTklwQ7BhyAMC7j5kqYrSzQkDwYOStZcPaLP9x6Te0KVYsrKHNarQJBQKraC5TthP
omiBXfVLPFk8EUoKE/a9Y26jdLhfJ5fq+q6U9eOkarvYWOY2MXDZIg3tZGkpj1WQyEzQiaPMOOgo
pffborTDmf535O3BXn8rh6igYC/CZbP+SLKejUT91ZERcoAA6n3bNaYjuecoE85n4mR0nmD5jDRY
L7dA/xXh6/D3qGcltduYsDyPWGXsBS3k6KOmzwIzTlSllpCyuEDOUfO1jnYuJ+7ydxyj8+hSOBLt
QcuBMzCvF7gKmZf+JOo8//gy1VBIdIhHJd71YT28tFZpSme3qDFLECKlDWBaiTnMHcEJU9H9rRs3
AFY+vsbW9EZjOuD8j+OURI9ABuJ5uHNoamexiTHwPe7bqZSUXRuTb1BBUuf0Rdseuux57vuKST+C
MR+gcVWidWoiDT49K6yMGCC4m2vM2N/+35l16kL0WuM6h4sHcKX9WorN/ms192ZLHtzvB4xGm7+6
UKYmFApe8D3rFDgxcPuXIYQty9rvohKa/2NTV2JeoZNl9T2lsA3HCfrggzImX6yrHmYygoVabz6d
rELrIlbexqvJ8xzmqM1XekHpWKH9AibJpZ1004/ubJYXFCDk6JBCMwwoRzlYFiXZB6GKfdmk3qCx
r2crUSI5cFXHb3RT40Cz77eGfErUplDIGe2yKo1YuJ/IggMvWdsuSxHoXPguGudLrnQn8g8Dmybi
8ZaJJWNeD9F0kSLDJznBSNNuRhltffRSpUCq6B61hbrJm0mQlxMfEsBG/e24IcjZJqwtuIuHQgso
FbEOBCQq1tP6WNe95tMH30Ihg3nI4sH3J8NFfyvyWPzAUnPg/NC0gic541IE6FJ8UD6y+jh3QUdj
m1ik9XlqNxqzF9+Rytyty2Pjo+7I/9okGNKm/aYlMQRrSyaG+LFtYc3G/i78Q4ok+Y5zlinSJjQJ
aLu7gXtW3Q6n7WmpIDdc7EkJVuhBcw6t1/Hovg7sCHtgsq+Adh+M20eEIgCp/f6q6EyeXC4qAYsK
Le5dhnI9svLXV8uv3zsiiZp2YNoaa28DwHFBD8D6gnN/XCJsObncmc9PWkv4UF1opwqNS21NpVW+
43Sip2WHi89ig0GuhTJuJTUo2OQQEQtbJebGBPLx9ABwzLk5qXukk5Wg2pAghZVbyaAITQTNIDcD
ZBbDyZEidGc+D6xbz/7+MueoV4S6FNerJhXWdSJy4kRwhNpd20xs9W/sdG6Z8G2isa8e5eS2u3Na
ztx1NHTPvObi/yU5ggfzukpnhiokyOvLmGtFJBIa+3oJ33oUJhnRBpYh6p1Kho1Dd63AAo+yP+sK
nNegg2xauMRXejuozk7wB4eH70PRPJk7Xwnld0265udTjCjzyGiamNb6YeHQTMEl5b/ebb9PuGFN
BfDmHPrEd2zPnAKJ+rPMMvhtWpDTg0PHCQ1v378RT63TmhaqBgj3MK/lcEz4Tuy6aWAfjBl6INO/
Pd+hHhrQKVGn7BySSS72ns+XNaBQaKnxBWU+azjKi7pNLfLdbLibRaHx9n5RDyAe9vJ3eLIA7EYg
4bmjien0cYewfdjjgPYjwhL9512C8hNZWixvfLkVjSMRQPrpeD/D7PFanIy/eAHPxCBo82vMcZgm
tQ/hNoHNSEG25d1GosTYfmXG2LmprOIHCLZrN9Q79MKU9gSq5ZV/4Urn/4q4g73mG3pNY0C0BcBb
19pZv30/No1Zc6FnnAjuZi1hI5LV49yC8rhzxUhGfiHB2qgESwy74KG5JYQNBiYOXYgy/BlpjYV4
NZPAvQ2ZXhyidsxbC7ry15qTpr2cC3safBM+DOzkFte1TC4nCZHdkUEhNjOIU+TaWyH9tNhNN5cB
nanJ9/9LF9QoNZnZwRQcgjR+2WzKevzPl16U3uZlqNA6539M611qxLhvd1gzkvb/7ksgxQ7G2j29
qy/uFCY+AYo10dA6leI5pjkJR5LoIwklpp4mP45wB5OzG4ay/qcD+sXWiWSM63ra1EAzMoDwrKa6
9AcpKvuyPnkMHoxgb2I7ta21aTuaBNAauVLr9BEplODdOwKhbM/044R5Fy5+59FzKcfkwv4F2WBP
yYYGt5rYJ3yqeSH+SzpROlOcSQCnrZAWrV5wNCHzgz+Me9DcjY0MhVPZMs24kkX2kMAq9ylsJ6Bl
cgHqpRU7WL5ryTAh7vOs3Ig5+oKowLoFe89epyilO/nSDSGhGTYHhwd0Llxmy/McBdJkO97hnmA2
Aoe0XmK3TRZlGvvjk4kaSB1Z5+G54bSKmlrn0QkrdmbfRmPYA8bvfa0lhM8KdzCAw7mpYfmP9VVg
H21julRX+9hw1DcYjBs0AkrhZ5xEZvYMT7jIRpqOEp3TTPNIMZH7I1LvtXlySlD+7pQBstjYc+Qi
HzD2lCCXkXFXBUgJv5qlslMhHJgAlIxuQz+I40ChFWyOGSSHP7TjSGSaV+c3VfeGw6iJSUWEpmT/
mayYBSAQCXmWWp4qJAJQo3RKF3XTefEUmeqrGiqhvUxbAcFcGmSfsCV0aEV7IvRB84CU95fpKo0L
2WxR9wfYidzD83ibLblxWnIyvYxr12fV5Z42QkHeUNftJsoxdfSh+rUfhu2TXXyUpMTJy4fnk8B4
eo4Tb/jEIttcXTkXRjaAJZgjH9En7p68cz0eF9tXGoX/cgfODIlXLHUqMT7Rw1OrF0qMiuBVGdOA
YR8/H55DrZs5JprkAI6s7OneGBwQyPdiq7iNj/F4fqv7HQDAFTd2yz4ycSXbw/bx1VrZjwQGR9Mv
Hef0JeE74gjXxDf79xYuNImp9ogQyAbXNQNs0m01CtNeZmx+31dWFNBM2FqaXuJtURDhSbO9BnjK
4CKJRGoLG2z9T4KyiZ4Au4AAB+1g2iEOUMAQ7854KsBgJwM92JTPW4tEwzZk0Y3YtM+EXdSfLM2m
PanENXjzD/bUV+lg36hoe33wTII5pnXKujUWLEBAVIWcl7iyV5eXw1OTlUj/0q85h5Zp/T+cp07x
QRMITVh9ZGkwDjosWBmStFQ77B7MW353ObPHyEk6PgDQEtqeJ5DCKzSXyLHmcl16l8yfQ1iIzOa3
ftYBHQ0PqaHeYaey9Adqrw42LYFoLK8lIOLf0dCLcOWjET9VMFE5NBXC2AQUI1/Kw6xdTqKwK1CT
UkOPlbaY5saOyXXj8Xp0EK9kjVtrS8aDucIdSyk1Wbhch/aU5BSmdH7vxwbj4Txvq6h/nF8TK6Pn
3/QM0pQha+6uHT2N5U/1bjDROzM6waN1rvYwCxIP3DlVnpIP96g+/m3vaegmRe3xVnCgApjlN2dB
P5ccfIO2k/cBLejsEMuXh9g/ljNWSTs9mmcMrG9SkFVoO6KZSmKurjk4thuWW0FbX0paej0o20FN
tndknp3XH1o1esPCS579uSxmy7V8+7hkk5sL0dqC0lv1dnx0m7xSHVfsrx0sxX2c00Me3qHWTyXd
SkvsYsBScVHit6JkwH/nhiKAibJzyAQSGMomxIH/dTNzxIxfFD5MQUaDV3dOHum+tnrllbgHKBwm
l8gHRP8n1Xpb9VN75bes3+jlgseohX9itfj20izreqzkaaTrJhyFn96N3s52aY2D9rD9T4LNgd+C
og/g/4U4cwUuolM3BOu9fFvJW0lOhY1g7WgKtww4HZHa0/5uptiBnCfct5UZLD81JhxQKq/wlD4f
QCqdn7nf15XFMxm3sSTCFhmhhLdQzr0ItI7IV8GUphcE1sfQE6amBk3j2qZHmCIu0LXS59MjUdeX
cSQx98kO9zJVZATphWodRhx4oYVOORNwz4yi9dEC+H9ZmqPXRHio4KqeutFSkbR4JQqovHP2Orvt
e7fRmAE2Dt/RPUJHK2ryzDbpULZr12ZgZI1vHYVWcFY/N7vYyGuDO6ExupFNxsp7nD09Bn/bTIm2
zYyiQa2fwDMRffHO/YGibU4j2MQgjO67w/11gWzfbsnKal2gCasjuRoB5zxsclVgxuZnV5gElKMg
5LE2rbmKm6Jy5ps4GNPsEEEp77RrqoEtsZxI57odb8lacEXORnyqRyGttWSoqI//lxFCbCqiT+j9
zU9Uz5hUkrJEczwDzFQZmOGOpWWBeF1Id3Jq/OdzS4I4cgpQeAa6QmY8fIw9xP70MUGHa4FkOHKD
7Yf7fxvZS9t5LlXrqOpw61ia+pa24l0iMY3+DKRFI69LKKStd6c+rn/MwOlTAbgTKd3l8WOcEjzg
iYKnYJHYaSNw1K7Fwf+H3YIbD/QQjx0zI/2vYCwTNsncJjqUyKwfiY4r8UC1FLKDa61/zPQ4qrSg
sW+g2GnJmqrODEAhyk5Y1bgy9lDZjr2pCdovR04y4vLhkpW9CiJF/HLblBoLvBwYW0rxCmbI0XYM
IYcz+xgejA7f6WRQXF6Lhj8afPidr8o+8AOtVl7Z12sCjEmRcaTJEASALqrwo40eF2L4J3xxwXj6
VUgvkfp9+tzlXPoSSakuC3lhfheJh3gC1pz+rH93AyoKj2XUE5dFOHqC4d04geCL40Odg1xd7nFr
NBudQ93OxO+Us0h0wh8yUfzSXP9rj2ag6XXpNGBEFb12fEwz6jA5thtLCDqtdardqG10KX3C+YL9
8HyCDxxZa5PrAbez4ApRyT8lQ5ZHbsC+aimXgcTDUTlnNKXqLFokZoCOIJeWgk+QHEyWs/0WFaKB
M/Bj/Zf+WHhPN8Ms9KqTx6F9AgGXxCrhVcCpn6tI2w3UQKWuZbSUsq4aTeLquD4CxiwMTnrfdUDA
FPU+VoA24vgdbGRtDvXG8k9UmrmpJZejUGn99rNCT3615K9eJnqi5UzQMofhaU+CRK8w/iRgokO5
Bi4kpGX9K9xvGPHOuvaIAMVzC3tCRQKQsQ7fmYDqiv4HmHlqonPD/B+Q0dOlHXUs9VfBkmjpcnzZ
zMrCT84b4/0MBDf4vsIpmKlffSppGzB0LZOHW3ope1MWM3bds24J1kUI/QA+LoCqPwC4tq1qM5JS
YcPPt3WIqXcDDvam2reHLwfzcDLBasVlrQOocyzHTpi3uKYjD+i1WzxR6SEiqBozqu28Wu1BV56j
RLxjUwwmFmORnZi4JZZahH/A2f+tNFsPs8fu1IxRvKqBib3SAVlz6s2Auh9cPTbBXV+S4LjgUfTC
T8kdYIMnsl043HSuvsHbDjzEzo3U6bh44LYTz14a3dW7TecMe5IRfvR3ZtIkLDArlsoES8seUaXP
pMaLPZv0+8c77z4diOTq0VgPS4kMxAtsIYLkOhiS07FNzxLlCuspT3cldxrSa31zz/bEjQ0pNcog
lLvLxDxX8Qocve2o5p6FTJieyjeqWZ80IAx0bXbfG1W9Wk4E7i5O6IWWns33EeCiaiqCFIG60X2a
Czq7S6Sq/bDdW2QO3EGWxKtUeuuc42OqQ5mEN/a5ChJzAviR8pxM8jhK1VrbaMYXby9DrKSiCuCo
kS9l5+fVEr0BoiZzqSA6i72976K5SSuExkzO1ClTm5D/mR8fDis2LRQfJMnl/+e2uuYkmJ7ONsfj
oEhNBuWkwej45txomsQQuYW7s8Nipn64pGZzXGw/BBf8npPD7y/BZajqMU1B/gM3G6wnbl8AxpRk
QXQFJwr7AliYGbRIvnISl94a78PlOrDXofurA5Pm/BDkBrlWQAhv60zL2rcavOiQCLfD+eGwcDTG
x+W/H+xMgQqS19MgSnzhd8z3l35nyABEbZ+NAdOhZoO6ED0QzrwfG4WgahmmozjAq0CX2JRkgR4L
/1d4qruXylKYrbGSwesD9tHktEtisFWjShwmC+J+iF6OJ9qDy+5N3Odl0/VDm0Y4ECJieqKSvo2V
YzHpYQoFz5cCSnIYQTGxwxz0+9G24p5YWosEV1PPGAFoEZyLiEotvQB0POpGlwU81g5Pn/OI59Ks
A9UFRcD2OfSNs2yr866Lrn9jGkHZVmoUyKiYLWGQtPwaHcy+QF/67rr/n0W6biShKFKB7On4i5rV
JfaqdH7h1D6NhG8iKgjvrgHlYBJDL2DvKGNQS1wfifJNiF6VErbYAvu4CGXRlGtrNJeo/Y8sZGkT
GQ3n78LIhzIcn+dTpF705SxBqUWP7Eal6Cv2pskBmatkgdUWBzvY7E7hYMZyKEUfsE4MU1sbB8A2
KzhBBmGHEJInDaFPPwataR+4WRxqU6nfMB+b/vIwIYqGej23dECdfbF4bAhlJawIs8Qosb8EYNTI
/jGwYt8XCIemFmUfsBHzmnf1U/7QtHc3dHGQhnFbSMhepBpjBVtXSg0BDXfXyCI9gUR6yLD6p/jY
ur6JEQw9P0Q1fttR0M2ERYgSk9w6eLmS9gs5168umG69GWYCL47fYTFtElusEND7oXz1e1eh+hjL
gn4kZhin3eXlkNf1R4R4YjNDZpMdwcCJIIgPHfK1JuEzQcnytbOA2lgq5dRE4mAwVC+oj9FaKQmR
3VM15lQwwlum7/OgmINTmZif4RxxO8W5ysnn9RhBb+RFieFXKKQzm7kHKf3fkbvDFzHLZpATa+Jz
pbrg/5JfjGzM9RlG0zNtFAN78Ovm69zHnZra2I7p1MJUJzznWX3Cf4DSEggJ2aFk7j8Xiz1OLXCc
7TvGNgxHVkWIgdA6lTL6QQ6J/dcXLiVWqMKtPQOqrssxW3LAA76m1BcOAtBX5pp7fa7tmsaCAN/T
Dc/aqwUuwUZ4kj3pOZczQIjS9Zm1gaSHmqmq1RWQ8TycRJf0/EQjhmSSzmkbtdU7CpsiGAFwF1pc
GjZ2f4A6WPFC2c3GlSiuhBTXdvCJWTUV/TYBmZbz3GQ+sBvqGM7hP8p2UieeBf+ieh4N5jD1e2fo
j42dSF43fcTVR9UKeypMaUvjVTUbEx3yxltzZT+Zu2A7Wwd26KxXNBcMcoIQMgzEELY/EBbisXKA
ezXxJaCIJ4dBtJy+x3WtRzz/TDpkF/GrMv2XrlLeIBZVyq60+T4wgmXFScElBt0QpmGjb5UnTHRe
bLkL2R6at1uNcghpgqrossz2kfhrCY2XL2WkGeTBqHGKdBPLqYSU/d8gcsJbvtKVUX14scfPzn7A
82mVwrHawoxsxTlCmQlph7fF2kk9ke58TTE4sb1QFimpNq2bmPEJBDcHpOIOA2bj4F3z+LCBABg6
E6+PekLtpLjgeOapv1eoYsF2bbaT/nAUN842FVI2+C9sERKqTTZ3VBgCBGu0co9y90UF8TSDPsSK
ChPZJg9AjvZI591fdmOfIEsf2jiDMkLGJXQ7zNVwcdixWgQBYIhbiZdAtjfCPuZjRKGeqwtXUhXp
i3cVEI5KD6tQ6CVFnDDvNYz7zKQ/AV4fVJ/SmPNZlrSc4NO/Qv5OcZP0IFR3PKXscu0YhIC1FLbL
FdkeypX9gV84f5AZ7zWUh8dvlogVE/Q6l18O8fYGffMgzWIW6PUF3b7CDlGvwks1JPHzod/8B1c8
x98LAFZ6Fv19f8XI/vJUmn+CdMWWOZenuHeptsn7s7WQJZJXSoumSNIFUvc4cDg1UKq1mR9ceIAP
HFyhQFi85N5qlBTW/Wh3t6wsEQ1e/bVpyD6uO1uSKV8RmqIuz4o6+LsIx9T3nmdwX3FmyzzhRwA9
kXkhoWHF/o+LU2LHyvbWXIiRDtb8C1v/a4CBniBMvkpyTX8x0iz7qyv8dVdbvWNB2qFM62D8mRh2
HWT/IFscfHdm2a+oiVim8rgl8gSt6mR30qFAk/Coil7ur5iDAnECTL2Cz7rZLpXi9oQ/jef6WzRN
fi07Wak9AGj7RvZERH2/DkObs0xA0ZQSqRlBIvOsMqI+tBIJTL03GKB7pyWgKkrr0vfA1kpkty55
nD0TjaTWi/84gGPY+gLS7hBzEPH9+F7EsG/4vfuSL56NH4iPZqf3DQg6499b9DCVuLW/4J2TamxW
XWnPz1BFfHyfoLX5lUqXKsMPNZesGFEMEAil4+MZrwezklv4daAiPWjxcnqHBCPR7nyv/SSmA5Uy
YtDruX/osSscehT6bKf/akELfaVigyLiHI3f1NPoKAZul2bVgfddRJivoyMBD81b1aofWYN5cz3d
RK+pfICTfeD+im/soBpY6lTy/QxYoVt92w3qffrixVP5Roj3sbsqYapX5eLcisUMXYIg8v07MrSW
kw0WtKYQBTF4xG/7L0GUeX04Foni8f3uE7z9dQGK8E3canboIjcOALPPZ3aNIH/hZZPL8V2qrntD
Vx/Zl8nyzPM/3K4Uhk9xUyNZcuYqwQD64Hixu9qZI3QukRUa0QyEysRa45nsQr4KZ03/ftzfSxKM
vDnvHe81WBdbaFQ5sTvApCxpto/fvmTBIYElwq6x8ImENkKp6mKfLcV0bVAAke8SW9Hkmr8ySwCk
uPK4LU7ubaEdXiVuK9hWjMZtg5EVOZXd4Jb2BXHPw49VQWyyJZ7fPnt+csdHHI031tpWgyWHMd4G
QXCsjgiSyjDz3Q7tiBspk6+ad/jhACLgILGgW5QokKSyjQr6BsAtqjlHxATgu/U/1n3Pea9J5XQC
TyNbIQt37SOfPnElHYS0sU9ugVAZrk/thn3UhG1ACrPcdyPSa7lrcI0Wl7JX4ojkhXkJ97WVbZpN
6s9npGF14k3T9VHY//v//8Z/fIOUA7qnTtwFrD1+9V5D/z7PeTSFJZggfRbENPZhxk0icS/kGjyG
gpG4Zh2bYgIvdNcgrqKIgYhIIMylNcj1slIbluLDHxixg4idgww/rkNnvXE1FMO93MPYMX6ktGRn
0NefSfpq5wtdSOSnt+cRfbQIUM7HOjg9ezRvEbpFJQBm7tOoZhGmi+XFZ9XC5savM1c18hZy55fv
xeitvMjhGJhpkEvyv3fyvG8APspaJQYGXPoIofCG08fj30ucA3hIMZGTMqGqpbK2XjYXncdj1Cta
B8WYzPvvtbUWMgY5tWFQ3CaNobzfnulFeLKhxVJovevQSaehnhoO4Ssdwka9LAUsigc9TpFBjr/3
tOYaTqciwSEQM/V2iJNpwKdvp1bgZCXtn7A3Qcc6/7GtOKSkBYh7hdds6yLjOWjNxN8djONYj2/K
1l1kHfkEc7yOZL0D0UjaIGmz1iNpFkdhv05bpRCbjchNn1GeUK4KKherS4t3XB+gvH4NKxCHjOEH
/KLnqsKHE0KAG0q3EzPpMbKpDAXSCc+QI+JOYrKbG96TW8C2lfxoum06kY4mgzjw8wBwPv3gb7M0
+wOv+PUs8JF450VkKz2lQ5g8FzhOgLwZJsR2u9i51ZwyACqhcpsO10JwGIWbJRQX0jTH26mrMW1M
oce2hSp7H8KstawIOAh77TV9EUAX5pj6khEe0gQPbMe2gfpT9zpiGnGBJcsahUpUtM2RU8kFvVE8
lL4KM2idzYmE29rvRQlT72z4LZu0/+BxIPTNthHGumyLuKy0KWrsJAjxdxN2tXW8cHMagq+rMji4
HzJrl04MCZevTNhGjpA9RqgjgbkA9LYxc+p9c0v3uyg7eqVY781RCEmZBqVKu2xGc7W+Lk59+Au3
hdLY7xMbcTAOp/MZB/SI3ZtB4V1FtcqX+BH1JgY+L7HN9jVqNkYzcnMYeYDGnp+UfV+mfr6+tmqx
yPkGq97LdjZUzzn64iuIbfVVrY4KXD/hxsZm0pLQl1raSb8Og+jVJ4kwfxn9F4X6I8Rh0h0X3Dt4
CtUKm9PnTx16xxpfSAqPeewe+8gMZqx3EaoT239cFfVXHaWEC1btn1Ekm0uuDX9d8sjyFoSzF9i1
uBzmbZgkZeX0VjYwCMNj0YB2FolwoGVWJbkkIWq+A6xnsyA+0CzJVnompls2uYyJ1NW0oysPjIdR
0OoYICFekjsXT2AURC/y8+VRljRGFVdK5hRmwZnOwcIK+bLe0CFnZ/CAH7SC+WfuOxZmCCsReJqN
lAWnP7SarQH7a78FG2kPky8oFBdLV+PwjNh89Rami45ktr6Tl3ACSfzIc9XEPa/TxDnysZTuIQhQ
igf1TzfuczplNWP8PX69T/rGMKbeDSIZ8AkuCiEJBOPVPIGEpK9xHDiWDZRkLWiS2n78NV9ewDtE
wSoKRnYtQwq1xl/8QId1HoDg3gCEamYb4rdYC+totLDwcK2BgCOuVnm+a25Q3f48aqp9tvSIA2Pr
D9P6psGlybLEJ9v7sh3+mSv3zANus9S5S/L9AOw5YPhJUBZX60Bgit4h0qkdz1w1pMA7lhaLmW6p
xeuCjX/ukZPs99rYDWuClqzppXOKWXstm+7w4gbh6PFIMQfLaX5H0VFenGMb8OU0RXchiFXMKAZw
uGU5BqrGDid/E95ILJdIVrmrKUhldl5Cl7aS/wbXwm2/2FmuLC6zIg7mDaOLZiSVCzhQxITOOlIB
asq825XOZJW1rjkcYat+ogmMrEygxQLqqdVp0mYpkthZil4CGWpQn5e/rgwAQQmKr1xEyYPxnB9x
Q8eQvIzW2cwMo1zjCvShxqhJczuWIkJPunRFmhACnpdGgwgskv+0UXzfMP9eBQddc+lvl5qu6HSX
VTqB1GFVJbl/3+QNAfsFRDM7zxAafvRWiYalpuL8lXcF75Awvm6zj/1fyQD03lTV8Lvk7MBGp8T6
fiwysPjhtP4UswrsksdngVp+dCjljh/9GDbKTgNeRRJ1datR2U7zvUJNPsSCIf5V0nr6t7Q/xuJe
Rk1BQI6MZoxGFEuMzlpKRpF7T80a+NftEuc8Mp/3e3BHhtD+8etN7VRTFoJsOK+1fru7PgmwOqfq
PdRh1zPZRTXr4kgdj/XbSLpXq8yLYy1hBRzh8tgLb1SjPIefYaYhOctkfgMrWRXgI4QY8GOAB7e8
nlG44hdkZgdCkKQSgvs++eVSRloCPzmS2MyFy+bofw7bGgA6Slc8MmJ3L7QhPBjZ9I3tZLjh1zvw
y6ZKEPmwYyR2E5zyr4EtxY1JNp5tdy07okTPiw0wA4x2myoezd9xrL/+/N+G3aAHpF7m1eTIBtAR
QJCeXMkFMYD6vs5oLje+8LaBfWzigioI4wMbNegyqnLlAiE2DE0BBxIMm5VPjSZJzHu4u29siZBR
YSJO+8GmLW6wtyEmza6Xlkgp1JRQqHPD8rsacK4UBwiDoyrt61/ymA2rWA1LDcUMGxOwPMJOKD90
9+x/Wk/hFGOdRCq/m6Twzibcz8ikbpBfWQrinX7BpphHb2UqOrO+yhxi0G8kNNh7zT2NCK/NlsBW
884JRZ5i7+aJKI3cegbs3XwWp3TDB9ry/WSVn5bs2vBSOQbac1AKV0+8qV6L/0u6rJrFDK6/HCaH
A24HTytK+XPGlwneOuVEJ249ip2z0je6+pi6+iyMkbkPDWZwXVXYOX+b9UNfVmGWxnUkWiPUo2+i
WWpUaBAwMtAdw1TNpyKJ5/W0Y5noT1SiwCcF73DSEXGl/CtN9FVcb/ofezgRvudoQ/IbfVkNaiTa
153+ctow++K3y5aGgJfBhBD8Dc8H51lSdrpQrIZm/gNL6YvUnC6uxwdDFHa9g9wePSxpE1eTMOF3
0lOp0TfPm1m2QjEYa5xvBgX69FGIXBH9tsvQX+SXr+mED/0lWUpKNBWh340MOtEnC31WO2JF0pUC
1Bt9HGyNsX0Le4GJv8ROwfEMc7IURKxPo4zAaXnjVIITBnP2FHobXmWLuSaQJHJSBdu22T1DB4wF
MC1ApNPDKebwr5JDblxTzibf++wWouggG2/sLCFOseVWsO4KgFqVVrBJwXMgdvbzbNCyVKgmqBMi
CLWfLBds8PChQrQG+KyOe2mkZKg8d2dJ758l1P/R0h3iQtTqGWzWU26Ev7+kjZoYSCUG9YEBrIbL
d5R5pH3KpmZrpm7YsGSRQQFo79kTkIup7QJUfdb/qPnc/dW2kzDoynpUB6+0WACYWFh8i+RTpr6P
SkdAxr3XnRaEuLY6YhMxsPGFVdaathnZNZU4q2nxXEc/FHosc9G7cvh9A9bCdTgw6qkyLLl4BCl8
PhaTWKyfMxCW6fp8pRv1KOJpk6MTesMryPdnTsGGKp3LKDdC5aM4ikfosp5lX6STHMurKnvbAPAR
GPwVkb3xzwfTHYNlyPN7A1gzoBnzKdOoe1rzrUniIQsjT1NrIsrx+GqN51sCooL824qdmoW6P7kf
T4WyWabUqQfduB/zmoJdMqZqukb+7s26GSXslTDas/Ar1R8hAWYkmcQX1GW//J8gWaGLl6zXQTO4
I5GvvS2JSF81Onnp4pL+eRe75LDMEDGo5nXovwbW5nCwU6PIrEvBdt8W9GGk5N2Yx/DQpksTRxfh
QpvQ+Lf1lG/earDFXWIe6YvRGnJIVr6H66/QU4fMo8Ap/x0kZ+qFxnDFb40T9sf8PFmuxFtmpBUk
G6hvpbL1WJFjJdbS6VQqHsdtwS9QK6klYSty47ftS7a0GE3Sd+jEMSWUvVqN5O1joB9G2trtsBIh
8crqlwVirxy1+s9IuZpzm9s1JAW/VvsBoVaOOWHt9sfqYUE9lOha+kBFvPSASy9zLs72pDo2hlmR
2GePMm6UE2Y8CjyZv4SV5Lv0AtvdYmgnVAHeZMuVOEKZZ5SzClaVYTNjTHy3VFQl5kVpeTy2UhuV
eEStns4paH5l2iDSbKR0VvQgfKeO4cc7QH58LX0jCPNDqWoL2KO/vgJECClYT/X1R/vLe3O+5Emu
RIDnN1RKGYfBy+AYoGCl+bMvPSC0UsH5fSKJ162Pu6Hf0bcF9MYhbiWLpKWiObwZOCmDcM8qN3/h
46Qc22IuEUkHaYN2bOv8F2Skozn5zSQHXqn4/+1NCYKzWhY6xcwZl8XSVPqyIkqzBsuUx4+fknJM
gwA1wI9OU2vJEW9mdOINi/LFoRTQUs4nKUBCzoMln3hlc30ip7RhEQPSnRPQ02PBci9FO3mjEZDw
bR70BjG3c9JMyp/Kha3Pkf4xVpKuFankeZ2nKPXdWIAkrIPTVCYRsjyWgReOBz7v15xULTl9WXFz
kyUW1Fjz4PCmiw5Itqjh7V/3zYexNHZXcp47bsTDKrvecEecwlDgPFTK3qsj+r9h1ztl8CHRj5xy
wrmoYwIcZqmDr4HtqK2Z8soBV4hXT/iSwDaG9yxrbl6rhfs2gnY5EwHc7oUVh8VvUA32jplW/6LE
Wk1Bi9KMtgtdZ8jNH6U96qxw62aalfJb0FSCXi7xr4ZwCKPEh+omiDFoW8WovjUzAXJf3JK5EIzX
oP13S8tuO5WnH2Z5sYetcMNZFmL8YootHFx8oglgBDeIGR28dlqh/2DqF63XoiZnvkOEJwOeTdSt
eOdCRJpDvCIg2sUThhSX5goJwACxmlPN9Pe5l4FgIfTRXRXzO90O5auFejJsEAcOPi6TeHblEtuI
C2cpJuxBDggux6+Gd0lGSpgt0qj9bNME/UeSujZ1eKGCY+fKork31kgdyLQCaXk6JSAWmSCPp3u8
Mhfd6akWzMT5xVX1Ib9DxO44c6pPUgpd8W8e1Qk57Iujh87ESwMedWV2w/DdXNU+Y172CDmXa/eZ
CK6XfgEKug+8/jYikmaBbiCTAg2p93lfz606fj5Teb2rz4YT7VWrClEi5u43cuNllalddXIdtW2T
IJAnYt5YBCSJfENjLMBQLjNHKcc4ZJdK6p5VS18qWkJUqJ+hHBzrGxajy54D2KSEHASY0iz6gACN
YY5jRCWk7E9gYR6Cg4yFwcPYjCsRhaGW6HX3dNtYr2ET5WoqHwTLT5Mb+JAlYmEP2a8nuXtEoaOP
Xk0c/qP9AfIsdD3XhmvzU4itKNyxHo6/A2m31Z4oIpLO3CatX5myV/xOtYfdpE9sVdP2l26g3rif
6Qk/b5GlrP6w6PPzlGtMQJjSlsEdGDwSNjyHgPf1j+q7fUQXyhDMJxoKGUIqyvrfz6850AB4CSbl
XiY5zA/WsLJw+KGx9JFmrn4gSsPkjxNjNW1kPqi8Ns1E2AHnyrDFe2UkcSWEVRUvdsGj6qRwZoIU
J4Lm1UTiSzQQ7V3djFVPBbZtWU8g38+Q5ucwU74jK4BkCyUl3q7OtiRPyHjBAOlLII2dQJRnbWf9
0Fc0pdsTWRUTS412gs45VsEek6NDTbZv64pYxQw/1PudcRV9dlggUU1o+Jxt0+EIY9UQDTe0UF/g
cn5nia6zNEvbQ5vZSJjOF73cjHC0qFRD+DVUYing3yVgRIz8uBqPXjkKtT+7aPPOTGQlxColoGjt
lKmCn8GyReMV24vRpe7Vc46wHCpGKRPg2YP4jIFdQcq+BRwVctHRovP2UUcwqeVFVq3znkoXyGcg
70NFsyr4DEevYswqzLSo554i75Oi7eb+z7yL5EBROzCAv2/Uv0VYUHXBZWHS461IEkpcwP8yqNk2
ReCHLAGvNT/QzMdUMMeleAkRahrdhs0iCX4sh16cVUs+P75jtUGjpbkgWiskQ4Sc56TMijdowpzc
aiCm+gc8Hw4dNmhWwP5n2kQE1uvo+TiomZJ2YAz0EFCscEM6wqsRg5yJClRWthYsRhi19XXH/fSk
OpKeCx6Ogo8tQy1hcNvmJWia6YijxF1OOVQbCoqa3qCTAr3Z6wYzGEPWvWZ3cLmT2Ral82W9Rjiv
BsFLwc3I2Mzy3x0AHsqfKx7bJ5Uwuoj9A6faF5fJ2XivTAT9lyKsPrX1DhD8F7uOBzhK85OFIgBK
jobx/EZhbHS5dcBu5FchOkpz2YQdfOu1FyBCwKKosP+pqiA8fkRLFh7ZiSjROqtYh/bswhPAe7+A
22+FqLKwnW6Zo4ldxRud//WHrHtfEdYL3NFpoe55HZFt7ALIqYHBi7sztpeNKPwRmy3B3lBFDEhI
SfE+nftHNxeJ8nUlbXrrNDo1ktv7gaSBPx645fxyUx47TNLXo4MxrVKu0wTL3QiAwW+4KkuchCbE
Vcrn+Rp+vqsrg/gRSftuzl+805QS19pcPEpU7FUgwAPdUI5HLuFw1VmiXPVO1mx2xpTVG2YcGXTl
HULLWtOY7bZXfGI2KYGkUmAGmjDjtLRnlfP+9Q1TnFD+Gmv/lnkk5tqyQZfXgKnxr9v47dtVr8Pl
j5ybufknDK/A87yOvXivFZm6BXCLHLIpx+CFaYnnej44pYqWDeEOyHuJiwzROryrgcJZHH+CWWiF
Fh3+tiwAUsjcKJSbNi9z85jHr4wZD2qdDsGooVlVr7fk/u/aTLpeCovx/QEQlC6uRJw/19oLNSnq
Wnt1RqY1Nhe7Rm3jFmpMjitOw0NJkFJipaj+3V0qMEwxBdObhDrINuy5jEw0g5CajEMmpo9hAAp3
G39cvnP8DISL/rST+bZLQU9te6SP8V/FgS4WURmQckekZxH+Yxi5465D6Ef5SSgFDlVVF7WrMkAa
UuUtqBxPMLsuHBNaa3wCHa42MbMS+Jsp6RWeS4Oaf3PZdnorQ4yDBbSWQ7eK5E/IAuQPDVLNPELB
7/CDRjUCp1lgqKJrJvj5G+IGXVBp5FDo/cgM3djX3txN/xqA8sUyzjk0xZy5Ulw7Y0MyHY3VRR9o
xVjuBbI6X6H4vEgAQs0crlxL1DErJGOCYISn3x3eTHqmZ179Ei6SzJRiGXzRDo5zWOfACTnLDahl
U1knpJY04dRRsT27x/C68LJSFE5gNxU1Sv4wkFXQ6YOnEiwsZz+IvQg1RYPdbwE8YCxd8EjkmFn6
eX8NN7012NPBphhbXrgEMJREbH/ZBq7c+AEs39LHtANHBr0iFPY3pFM5OfJF8uOeKS/mYVelXi5A
x81kroHE7avgAGLRYGjrSJh8hqb+No1pmgvtEFwYC01WJSIPTGuxodAk6U8m2lI6c395oPeRar+/
A/IlnW1sO2HhN/R1Iy+XAzpplyr9opozWMrlWCeKhzwirqcydAHRiP3qB7e6Nj6ItNUsHHXPlVhL
5X5ANletOxGTUFmI1m2VQscNqOr5/I227f5GiaLrCUW3yTLoHQcA9lrUjz8IE+o5DA9RYBI+5R7t
9Re35o0L7F+3m/bzJF2jLew9OoEoHtZPnrdng64GxRzarXy0Huake29UAh80W8+1YrlxS/f7xIzg
jUyz3ITOpDf0c0EnYbgAflYGEdP6GOvapFhrj2rsF6ZqC/11UGOcA0aqeaNzurJ3VRKHiILvCU3t
eqz+prxUAbAnsupA4FjRMvoaSZqMxfHJznLX4hLLL8ufIdnSAuxAjNKSbJ+iibWs2kMNCH4ahbaV
um5SKQ7RI0tHdjODYAYDjg1/poc+5iMFfKzf+Uy+o0Gl5H5Xqwj4NE8cNJwMyaoIgMW20cyqhK0O
uaDeaJUQdr6ad9RIZHbDVuMssEP8cJbxG8tYvgZZwjgzXKlo4d4bhLBe1/356mpqnq9k/gFiSTzL
RyAY/7B0GLrrXjHnMfKfUgTtCBqLbtaREl9m4fgCg7ctxufxJ5lVRqZ6J+vB+qHdqVkVxz0W0rW/
XFfAun109hXcKumc9sZJihOlmgkcuLw7zRtqf+DMeyDwzdgXUUjlNnJpYF1LPfyYN1N5zP5ZyWje
bwgHr4C/Od+Vc5tQp/LNS/p13D2bDTWu6IMdw11g0WrxKkS2JcudmhMzrEFJK7U50jpK3wjXfMPh
RpNha6/yCjsqUL7M2udcp3OTrnCcznKH7aby7EY1V6U4Ij0ju1yn4temaWy5qq+QWnotp+ultCWQ
pQzmaCnC9OZAs8EMYmzrsSUtuOZ5pLtcSojonIcenOvZtkzY2Mrj+DgAOpkqcyXJ2FBzQ467PvWR
ZhmRxVkS7CC1GNIm9xo186GDm83ZYbDsp72mga1z2/rN/+9+npereoph64Bor7OssN8tLcdzMnNs
7scM6iWkghGfBXQ9C79jOUNp0IVAMcSZvgfmq+yRxteD6L8uHvIaBCddtgPMrrvBweMD5S2vBzZo
at5d37ftPvcanx3jUiua0aQSttC9XBWTl3Nz7WGv0C/5C8goSICaoxCVyMNTidGBihTVK3KOh0Pl
MkuEnI/m8LMauJ7CX7R3sF1WS5Qa7FmlnY9D679W8hcyVAB23ne/N6e5aMvXCpe3HOjJ7PakmZJv
/hicvOCp09NxoID/z7JxlxlepJRqkkDwargwERYB/U/UivqRE3dCrhYehDRv89uZw3USaDKLqsxq
6a094orlzGz5niAanR2YBmd4Pck0W/rfpfAqdt9rtr3sI7kY1smhvOn/rghb9TZ1We8HXrXeW3Wt
JJ37UmsmrLgoEsV9zHpcaQ8zvEdZc2xvwZQufwbwmZChFIJPj8NuxkPVPQj/C9BbFwV6m+016ze+
QzVlCsso7u2BK6NTFSdEtF+cYj955qSDmEasyjMCK2Q022ODvigPMPKzxXh2SY0+GL+udwnLNWKV
TU2HUqUZCZ8sHXOXThY1KlgU5Flxgln+5qfh9hsXb3Sv0Pmisp0lw/297IWz7qAbclcKzE37a4Zl
XmDqCWmIKWZzJmg+unq0xwaqk8IOG1zzmegf7zDDp9feZ/BgmyAGt7GOg1FdGD8btpVi5nUXfhYA
+6D7GuOotiDW09AgviqLrlqaDNzYk0bOI2BZ62Xl36HsZxvcuxwk2G14Pq6hVCof3STCN/JOSP/d
fCyKwSZvWtdVwOQhxJPF0/OTiQqUd176eRjtL1wtC8WGKndraNpAaeOrpFtUuPqTUJBqS5NFpqyE
T1Fg/rXQhfZJqG0fE7XoSpSPk8vJo34O/JE3VXSPJLpN0j1viS5XGpjSPBGL8KoC2vHUUq+u3VcV
NqeLurc2MxCmeJhyKqhGunfk2CV46/AS/Kc8ECSY7/+nAr9jJSVDHaiLVev9iOS01PlMwtsJzNWL
tLyHWbDgimBSCboV93p6+H9hEm2gHappr9gR7qe3bPqdo3dBndrYZPFWaUr9e7ntAgGB1+Qkdiuf
XPGsAQGJt1INoVTWslAwp4ZMxg/Fzpuz4arplH/glUqVdpAcrR3224ff6HrJPBlVrH3P39+F6R1v
Xyg7/3tr+6L44+bzcfj1/fGQYbqtulZ0NYtXUdIY3xcvIIblHOYEBm2kkGLfHfT/klbFS4QJ+bTQ
aual9nU7jpBR5LyFCKrI7TZFPcgZwNlQSKlNpe3Jz1/LXMQUyD6V/u0w0TPGqXF6atnSyslvwAj2
lnyDhKVqrpiONYZVSwZIZVHiBG4LSXF+9Lw4ZmpIMLcCHmcrw6St3tZBjBe9NibA/Wd8Ogu+EFiH
VsF8A5PvEgRSNR5IezXNugR05SLlO61Jpr908CTCS0YVwfA17TMsJ1ecOpaO8HL1Se2hz0NM8Vts
4dzQdyekKi7O587WWTPYGxyATtDA990k+YywqjT/PpPDsGjA3oUyR6vO/tyeezGrM94AHtNAL8MT
htfivDiSjc6pRaddjmq37u6SnU4j+jECp0L60jIRNUcscg+I0BduIO5A6pBOSWZVLGMXJEzH+93H
5cqfnGoQE80yvCElk9z9DBwZ24bKfSkAyJr1NkB7RDt2fRCcLgQ4MtBqr0jvxCWU3egb++iAz51x
nXoaZiuSVmyf5ttX46JNO4ThHkVMPfRlmMerEiowiN1oy8HbdESWEVpg1M7F0o2gpodQDxPKGt1S
RgE24rc/HB1NMx1oYoabVTFdyVsDCOyuobK9kXGUWSjcslp/sipJbMWtN5ow1pzGVsTPT1wuvz2j
b870vOQO4tZBry2a2SSqcWqGBhKQuQwUZp4RVnwIPKcSK3uTVEhi63T3pPEMTxaZQOvaj2IP+hjn
1FlxHuKMqJOVnsGcGuo7Gd85Bu18XITfgm8vj5lME08KiXolob1zWCjuPNTqpznFRI//9jtYZ0va
hG6irBle04AKgKxpBSoII33x8UhLvggH/zkH2JDxBi7tq1DJzU4rmPY4WSAPAP+3b9vuB32XLn8h
SIPjsDbZwzEMuh4jSIuFB8NdUCZK+eXkHbuTsfpDO8d3h6SZ82EaeMqj9ji44JrdQH6DfFYS9mtP
6Mwu6hv3BlJ4SDuwrpOw7p7d7juvQiYeDX/eOQqxrbhaeVfawTRnEO6BNmWcsO0tVNW9PbikDg8U
Zt5l1KP2pwJUIAhY/A722Erfe1IWb6BkKFjFA2AALokbawN0Gf63orE3DiAT0k1vZjZf2POxWGAp
X7IcD04wltoTRgCC4KjAGgiPfpyxVRQlmLrK5Ko7SXc7uD1V+e5YoGXViGRnc03lB9D+uAEGnDdl
PZdph1+rGoEjw2uts2pDElkLJ4BaGrRDZzq+zAHNsINOBYcMkE2AoN18Uvhs3l5Fquax2XUnGsd9
DXs/LUIewYrMj5edVYbvV6bB55VvD0NalLqzt8aR1LirGHXHPTMk9BH0cRPH1fjKjH14geKXayyP
ZM+QV88DqHJaL+3lpBX6HbQcogWaVUzeQ7CuaPzqFQBx6AycMmMu3pMBXtaMnjLmEupVtzEybpYj
4L6rbJibxMPVDIOwbYGQInkQvC5QoUpkrOSWibTkraqnCTtzBpYJqQM5gjIxb2qs0Wn0Yup0bwTf
bQjRtAICafY0NdxPnZN2yGfu6PJNXOBUQUDT2lq8ItnNIb4ltI14YIQDj92VjEs7AD+R2f3V4xcn
EO9TR2yiEgRuFlmgvxz9cWJQ5KI0xnaOJhDloEn/g0MMqYlTKXkT9RlH4btVWH5Z/uBEGmgOeoBX
b4wYQUGoDoY9NRQcFV9OP848rKQ6yztqH9VgzX2cRzvsT/On4ZY4XLg1G857TgNZA61TJETxPxlN
8AIcWi0s5y3l4ynvYlWvbGRVtlbqU2V+L8pj3L5hLNYJrPxX4B3Vzoy8NretxskChzT82np9JfPe
whEY3NaH0iXEjHxzBIikGvvUxJ5D0cmhTIciPl3zhlV4JwGDpGK3ULIEWkDo6jBmbxD9VRLqUxef
1fmvFD8gpzb3Ihq6vIoBDC6GWZYuaWdDBo+ikcbGPy8DktD+ox1N8z9KedwMTRDRosqdfFcrWEDW
4UKNyCg+tIONrVr9mtj4Lhar7ShIMp+cKPh7jQ03m1gzzq09rpBlhJevCCvfmDvmVYuKUrl+bVgd
07SLtXAriCvUk8M1NyJjWcMU3+0IjcJ7z4I0m0ONAgbQioPhbeOltczjitRCAcYgfN/QmUNQuBQf
zEOp4Q22vhte1a8jORTZMyAkXl74yatODaoD2yvJ8aGpaET2HpOjbROKrQbhFhk0jnwnIA1a/erq
okDRlXt73wTjeqO82eyWXoWeLBcEy5wccy0NA/OKzGZDykHndesDtN39asR8/phKRAqDamiUCa82
kypgVEvn7IsgyNDgAMNJjywpEU9eEKNZyLcLGOhyHaob5UiWWvecrfWCjzQUaI4R+s8TtMVm+inB
vzlgaaLNXmR1XBuKYEF74+buUzKmc8gWKyyUBeA0vU8pXGl4aQn8MNSB28jBw2oJRnjmhwRBUD+J
pgWWLAnetWE9l6WMuPaMuJ8diFkOl/eqvjNJIRvX9J1Yq/1BjwT5AxEIPc5bhmS+IjO8mut84V+S
stgl8jNE5mBg7rwomgoEuWXKCNEuvvIvERKeNJJ1flr0Aj69zAFKG6XBe3oxqFzZIgDZEAdZA/ub
j2tEO3ichRASCpI+VCR+Q6iqiirI5G7sfCamcxxjmZdD1w8UVgzjSxOtvH+G1j9MFwykKCM/4i10
qUHMpbcV0/t0nsmtnyZJ1bCveQzcveOQWxtx6K6obnNumgciIq7KoeMZ1doX+Jw7plupvT2y3G2T
M70icskUU4elbNmIMlbuEBSnxjOfBjjpX7GBbexwzC8TzACy2uxel2mWthcfzkIenmzm3ZaoPcu0
u22g53Od6y+kQVBt4GS6JnqFS9Vo7wZGzMcGNnx5KkIHuzoN1Cob8UkUesqnrFpLyfvxaOIZfK6q
VvddB4LA9xrxJFhb+XU+DjNzwKVJKPbFUSc7exDn0TEBaI4wYTVQ2UA9ZNtcSPJFuJvd3NidOVPM
ISkjmgalGalIppbUkbF+TI9DAJ6mJ+NQ/K2eU/ibWPTsLxGtVfWPNfqeeD6stPpx3VZzrGwhBCiI
JuCgd2aatSKCqfVeNc71g4Hab/aTQbk8JRfnCPOrqffciwyS7lweJAV/Y/YvmHLTEM8XxyIvjvJ1
o8WzI5ODhY8TJQ7FDqsW79i48KSN52HyeSaN4eNhmtszz/2K5jnnX2jsfKRrm36ASfpTIxdiDJzf
HRick8hUSMeyOBOZ8osazVNk5LMLPcrQz4B6BkqSKo7MOCBXH/DobxBsHgfguosvqeY4DTo8JFd9
M6RtZG72KvzGdB3B5Dyn9k17w1bAS2WL7mzfRLKghsnxORB2qgrwZL+QspRPnz9k5WALy7iPit8M
2L/iQ6OHu8SPQdEG3oJJJx4fr/t8OI3jW1klO0/mOVZYRAhvercbbcgdBt/Mj86aoo8NepvB0nde
TFQZweUrB0FzOq3zefedgtpSTH9rKvnb71K/uFS4zjJ/azc8PmF77bXcvH134Gu/YS8ziZuIZqRZ
cMVP1ovYMH3/RI7bIdhUSL3gxTWSmb2fOHipgfNXKbgzMZRG4cH7Qs94vPP0cqBvkLHYIbH9+ktJ
YaHJBNeqhf1kU3/MqBZvYFB8CjqMOItyOy6lz0wWDPhsr82rcmcauPF6RjDaY4+UAX74YstEXUlv
Jz4WBqoAV2/fZlW0fzuCw3s0puX8EhBX/g3ahD8OM2cZdsO/nCSVICb1WjDy4ySAwh4TH4GX+GTD
46ukLhGwbv5DVgFZ1lAWprgJNgJxBJOoMT+iiM3l1JmMiIoBL0i8T1KXcn+XGw/780Bp6AmvyITU
84EIm5ocjmy5yl/PI1CMkW23EJ1sJZNEbYQXLxxLy7f7G0nTb/d57Fvv7JIrqoibt8i+MrGsheGy
DIISEkxkXNKybVaZJtJl3F23VUBaTXwGt30QyW1WPl9Iiqd4MqNy0MRCx5UPEtU2buVs7+YlzMf9
1JUv8j2R/JidlXbmF/pXXdxNMGFMwZPWwjE8xfg3EpTG9Hq7UtgO6u1uC+8CKKucqPlz2ymt//cc
GznbwrQzxcg4egKvyRnL6f1lqCLBU057rFJzihFfW9ufopuKfpwuYp6o7MtR6O+wLLi3O+Owz5yC
X9alaZrCRi6I2IMSO1HUi/k6/kvEZseO7wDdKtzMvVNLUfGIRCA8tEMNvFEEAyL+OmruXArI3Xe8
QVxl3RZwuzyh2t4Daa41BXEhcwoh4jKZmmnnCkeRS4vwVHVXWHL+Oz4lhR8z/G73x6hB0TPD6PKZ
ugsQbLQf+RflWsY4kdUH2Jb/QTAl5fdzqr61YGLdGPVBq+pdZSZoWmO1O0LzIjV+4xbQQoLN20Qr
QvIlSxB6eGlDQIhxc/OzfZyDJ1WGYuDDsgU/I1ISSw0smQ/aih0rgIIH20wVan3XCwj8WL+nieH1
rE9iQgWNhf8VtrGQ1HXHlVmRN3WTDdpyskgmqKt7Doa0yxa8u8IYXJsGn9QnViIXmU5m6rETd+/9
tqb1Ao2IGPonsyyKd5+PCU1CNaxX1K2fPAiwPOfCw2dPytqM42On02ya/ehG1D+qcmiMuxJ4y+BM
Z5VJ0DfTZyOBetfqzKhZhnpQLF27cielH8/btm67Q6w6Z691XbbVqV6yLcII1s5AcdKk1wTDDa7F
CM20+zjB/rH7b/TwdTl+wOMmvhz3K9dYPC6r/vyTK8wninlCZLVXjPWt97X9UZO/FyQ7mCxD1Nhm
lyf2cIfOB1d7GtywHzDg0hEK5oYPchUypBQv30fGxYK0tCWv44PX0QhpF1VzhPnkTimL6PZt8U97
ogLAwZ4HONgBvOUIIxPJymE2XkmyryNqb2dQdG90+uEkpTkTwQ/cHBCZlhZJsePU+R9vH47m30eP
faVAjhzaodwa6J+VSvtvZK7RpIj/xhXtj68+BK1TNmk9oHPsCbr1/A3+kSJN1vw/kBmIYY51wmjT
oq5SbXUxRade1RpDpQgiZMr+NyDQf3a7py6OUtzt0fFUNCnmcMP6XDveXt7iNMrPrIowt66L3G2K
FxSB1TrxMsjPSpoo2qPyvyn4TJ4Yc4c+09Z05vrTk2b3qePPSLMkyxAR3ODPanErpJnYqas6qtki
TRePq940LRKuYlAOGjRz4ZzUKxS61SWSUBRB5BaRTYXJic/q1uvQlPCC7X+DrKXqoz07HaWsxK6F
rjt/4LVVr697n3m8vOr265+nri/TaPM93qDDfetsl9I6uSRTIxYA/xBn8GCAEAuHD4vynw35HhxK
L2qBv5zj7lDxXjN5p5qvGx2Aj2vM1IQLS3202UdBWVyDTmS7A1ThfSbbYM44xnAcNH8V9Q7NsJE/
Lb6APMbl120M7OoNd1Xd8Xro2ON2wHRaF83SkHOtdvc0J5IHHzlV3En+CAqZAEEL3sgL4NgMz6AW
IkCt7/x1JNplFWK3StjI9m60mFZ6kIz1rDrAwyTdgT+ZNxXoeyGWnC29KXx0brkYNi+WdAqVCYj0
920wdVBBSKQHH/Fo4NSXFwwcdz5tcI1myd/7sSU3Lgjl6N8/qyGJEHF85NQr4QdWkuMv6XveHvJe
LnRE3ClLqoBBe1QgfsQ7Dhh3VdKybWDTsByZ7TQFszgYu/r5ReBOUujp4ZittdUcArdRr76HboNQ
i/rL27WvPCxOZ2xROPRzcJooraxaIr3ehm1gD6GI6XcDZYDtDqzeU1O+pAQnXuje9h+82LfnP9yo
QV1mkcV7e+Fi3sVz6Lhb0D7AUrnRRBgI0aaAn/4U/y6HR0d6Q0CrXfPe4F5ZvAvzMZQTOO3vuGEF
j1qIs0z0tdamB7na4IdbA5rW7jsNlERhRAp+cAO+WahuMG8g+jSprbckkaLPhwjt6YZ/cthTgZrr
mjNCH1NvsuLYl+FKZYopk0K2ZwFUpmjbxt0lrdd9ToKVYRgmyOCNM8eXBzQfGZRpBu8OM9UqaBoF
VMvnwRtS/1DWP+SIJA23lKMhQx3MZ5EEMfrqwJ+fvgzDMoHxiMzgA5QpXesFRk0yXbgcWJn8cmRX
9Sy0fgyk5iOdnh4Q8PF+QEEQFaBRN9b9kq3clNVMsWo4Krawx9c+N9zw0X47Py+53ybdP4+VUEru
X2Sj2uC4f8eSNASNTX1+YBoQZwJU2ptFUS6gZkXNk7C+FUKlotGbE09IzwJ/xlzsQ0VYSESAT7Q7
eFpEIV4H/IGiXDwuoJy13xenwD78vOxiR0Uc7SGAVSN6oZ37oUBnPjxZfwHI+CBVbtkJTh1L1vmr
xQ2w3EBwVwlH+gfSaRQApCvM1T2FU9sMm7VQ9Qnia8FDrAOEc3eIUl4Ed/whI7aDjr+kwrb4m3PQ
swNGD2eHvDAD/qBIlsYTcxIQcCsPqKoswMzU+jMCALKbppCa/KZKKyI3GWMdIlFxXv4m0wRPj2sb
f2mzbHDzs6BXK/H3Q4GFXbwqPNXelMwTxGR8lZj9SG1CD9sjfqFO8aQhUi3Z4QIUluuFyC4Lm/wF
jKDihUQyMrP+Q+BfXOmf+EXOxltb9f0S5HqutHvQAb7Tmoi9o5CsQaV+bSoUB3vOKamHxm6NHldI
t9SaOqP7QzIS1pG6si1EIHLnBgcvpBEc5E7pOD/TverBMYuhG4qBmR8flUwzta8hLfrQexdF8Ext
Nf6gQJi+NnuoDiY2qkDtYXwnAZKSRXiwJOldvWtulCJULEtjMC/rR/p3FOZIvjfaH411stLlc9HO
4ttSCZwm4/9xhvE9TQXRtaKdmcm7SSGM73SIcnrgp5HVPY2QnBC1BTITHFlFuEVm7hR9IKCNR5Xb
lwDpTWDWkiNNWKgxWzYisY1yaU8Jhqr3IfQHwfpSNFrFtz+iJVXLaKHrZSV2TTVoaJp0ZOfN45aT
vDvza25KZ/sT6GaykVTGifpd7GRBt+khp3APRxdS7ptliGtlS/vTnKh9gkAHdIn4ifO4Ml1xZsc2
LHKK4t2v8/CXLmAtYsJQjp0cj2vQMUQqVDzzrwVhoCEy+wBGuAmxIW3EAyaN21xgsGyTkJBw5oKl
8TYd+CYmnQ3lPwAYPK9pKS0F/LTRIs5ngygQQ4sNe55eLnY0QHHRu0C7BspHrnl3QjWt3LRGDcLJ
9sCmf3Tkk73OLzgjceKeZgG+FRncS9veSII9otUAaMyxYhpaoDGARhea27l5FEbCbf4hQkwz0bSn
ikVmxUrZSl+gCChzaw/DFWLSM7JGOC6X6l2EZgOhfc1QqxPTXs5oyAAuSESBOTY5MpkyjTeMlYPa
F7zZdUn8Wzzi+yrZm+05bhPddDp6FOynSbJg3OLcDKfY/vsIt3aYiFmWAcaQsxpZwKgEtBT7yVww
+o4LJyHvHrrnQb8ow+M35vnvLATrGuTFNGeBfUtFjq7uRH5aZTMF+bsMIP3laUWfYw0PUS198lkg
YAqDV10TmnnnbaV0thI/xcSbaU3pGD0txBhCipfvVrETL8TrdN14YH55eZDBcOqYLiwdrEVUzv+P
uZQHtHzokuRY8ncGGhTAFdGNZPwPDkrUkxRka0gLtsmVUn0M2tUAsqJzLcS5hqui1VskgY9l+ARh
TAQn6Jm9BCDJfUFfxccOg01lK/5bP4lkWD7ghdtLTEIT/kCs/Cp8RzT9Ly+DOXAt+E9sBt0aSIKu
x4xCWzjPBj4dtZPxCzw2aaYjTr2I56cEi073TxJ1AJPAONJKDFFbNzk5J6whfr0cbClPU4uoo0DA
V6LvMVSRrVCSdSXQL9ir2JRj/uGO3kC0/HSPbLYgtRZ4vMDQE1Volvp0/eyei11hnOxV7a22jp5X
6OtDTpN4jxf0zl6xXBePDtIy9ZjbNNoM/582BUcyekQdafWkaV7+zudcaeSdMue5VL7t3xQcu2bw
IFL6sQ7jptzDeEsySPrkx1YNSEbrlSpkK1U6nfVGFQOf0lAP1+vj30c/8MntkolhAE/52Fqjz82A
189Kymebvd1wvqtvI5j9ng1u8MWpTTUgTIfv0ggNrzknyeiYdCC4vwRfIyQ+lzYgYAyWQluJ1KA4
P50kEl/EKedaNsYADxHll+yfznzh37LusX5UjgJ1z0KqSMbSsNJi/GiiitDjkC8Wsg7jDYn/DXqw
YHiBi7VnGisXfsg34bpK7pPumJ2ubXM0OKxdr5EIxMwo/+IaVC3/lUzVq5dQ9vmdhJQuz6zpjPjf
/ZLP62hO61T7pqs584fF0EYWEoLidAw7zmEdGGWsyfDZMMHaNEevTizEG/NXBAjLQamunyIeN2VN
J/JvArEzTNhvgIte8+LJLUA1C/QGsN29S2EwT6y45Gw5iaAzN2P3g6X1pZZ9sDKyvhtlhzNDnSIU
rbcZ436RlIxID34Qy8oakxiDrP6o4MuYbt7Xh6q5fTLvOWZM06ZasoOI9vo0j76CyNkcEl33DTSS
dfleUCY6fdzJ+ksqdEG4W1GzwFz72QezFHr4lnFS3AwyV68PAuxKDt4LqlrAqEwsh4jnHgE0wPMV
nl34VpN7er4GENKnFfgk8zvOmH7YjxxNYoYNlucsRZifW1EfONO3R7Uf1DK9a269dawYRq5U3i5g
f/sKjF7r7T4oFDxDMpkibOJGyLjmVTqnfbWRFhixShsbSL3FFcQHcPLlK5/iTkS/10Q3dzqvAtRm
Z/KRmmL/gINR0a9ZSgCNn4JRMRdievrHGOMGwN3d5iM9BGR20Ncis6cwAVU6IUl/I8dVBEJCJKYJ
zL/Vzpe5awjST+5ukGjobVU8Kw8C0VmUwEHxPEhaRpdnFnfhKBU0MmiKS67KddBoVuZeEyfsOyrb
kJJbclAOcLdfuJf5aNYZWot+WwtwfDPqFFksIRVAYbO7SNDhE87GwFSYXnLh5pSMDErM/Tc01EKR
rh1Jc9GKTH51/mPHJLpeoKs+rLiFF+LsGj7sDvaic7v2ThFSSYdvcNBc6L79uESrGGNRHKyxLIte
Cr8A7OEmXY5UTV95mlz0Ty1w+yln6zXw9rXr9WmQz5v+z9ypRmvydy79XzvCSFKrgNpuNa+oWlOj
7Mw49R3c/PlmyCKfx3uWLor2hCtH9DsMqobkQ2i6W5ClTbUcX+Ygm9yTzdql+6tt3iiEnHGy0i74
ehI+R5LZUgKYeiPUXY6nfB22Tsqblvaeiqt8uyBYTBcskJ+rHH2sSXp6+DcP3aoljmrLlu4BUY5N
EVeG37cX9OOXmKxpa7FwzKAtYcpJBAFN9bvIpHAPj+bCdHp3guL4LZ9H1YOMRyUSo8Nw//9ygeZJ
IVacn5VRuxrRsORwoplRpayP/eQ0zP661i0XnCKO7xN6jBUefZyUi1BwKFst9tcNN03mzndud4Je
1CmHb2AuXMeXFQjE66Ci7gTaoyvHTealSOXBiXuCywgWcdaVtMgESE5adMdrt5+x0PmEyvifz+0f
VUl0xN3YoG8EeSMTOFC6jYXNMpXEqCAmKWM6Ct9flDnYFRTTBrqnExB+lS5cnU+YpmtVKBl09um3
WxLz5NnCT0RdsSx+UQejEo7KkdDjfui+B7Khm6FcNoCWt5Mqj0TcLwgi5eYuqoycD3JmO1o3NeX0
mJc1E1y2prWt8BBROf/mFnKU4MFA0hj2BuM96qq/KvmGxVVxRnk0NVBzzCv/nLJnJFmwuDqkieGo
L1uzv3zn04/AznppQyaUjMe0aMktS9Aoo+BkN3v3TzTwPznajXVLOnX2j7EpH3damlYO0F+p/418
FRW80oQXt0t2SMTIPk0PFn9ktPutozo+1wUnnNKNMKihiZK+8CRg6hxbV091ZT+MFBte6rqoXhEi
Bg93OgmIgC/41/vLQTXM7v+XEZxNM2KduHlej3fvCwnxtCB0milJSki4E2Aug5ULLmjJe7uVzm1m
Ny7lIh6Z+J1sYS3wMyv3l4kijPaerdTN/K9yhMpxqwGJd4NJpMOvVpiNPVWzzjH50BJ8bVnTNKet
4V9LimohuwsC3hm0pXfVRXO/cbBNfG8pzwKtZPCqy/E0IoAVtJ56sMmtguXcO5JPN5ORpwzUGEkv
FE8dEOZU12Mf3tUAUPo4d0hpz4Z4ddV7JbR2HRPr6B0Nva4DZp4A46ViaczQ5pTbSwCFxwZ05SF7
oduJaaL9beMr4tVa7sQ0efy41DoWLNpZOfmNxVQwc14L+zFNkSseU7Fuc7nNKcff7f6fRa9kH8h5
8KfWaPNik+Szm/I8IT18HgJqBDvUUorqwx4JtsHx0y7LkLFoXHwMMvuV6xz5Q7EUwkjz4Z8lGQHN
M9ldR7X3sh45yR85nYKMf3MlMJ9k6Q9HH4lc/66q63ReW550WD9hWjtOVBdmXYN6o+T0MhR7bOvK
URd2nqbNPURBvhTfrSvNzU6mu8UBunjx0XuknnXGu+qeIf2lXa+GGqcFe6Du0Hea3lP9KcIoqBYz
TobfODNixyos3rREVSSeM01vomkYVO90Zqjpyv1ZyIm/god0RrrWIpGwwWSTK1CiMLqspckrCHMN
/LYotGNBST31uHHQ+VU7tbvHHIUuPM+IzrTAOdn2IBumrtn6iRi8XZyvmDdVRmPH6KCZxL/kTRYZ
PTZ6hsaQuodDPfx7/hydwfxBUB5z515vqWw5HbXKK23S5OLck9+uep0K4F42tRHH93gPoAoGuocU
fB4n9X6E8onCVFfLA9dxhgNcw4by/2/DjZ9y6Ai1HVZZtodmPVZjEWi9C8UBEiLqyJc8XeX9aIqb
vwTCtALDS/AiU/09xAsI5pL2DN+WxaWqGDL2KWFuevvUSZ0pfwFUI4vIvYqiYp8xlW5qwKqsEcFM
CcNZtmLbDyCYbICijQ0JqzGtpV/MxnhMNhHs0phq5LIwxOBGjuVxkowebid3K/ek/Us6YTfU9k6L
2ZaBm1B+4UUctuZMArThCQ5UvKUdBD8cmT6FH8hGvDU0n27oquZNj1jnu+soAnLyMMQfp0kTO50y
q08mtlL0imS8pnKL6jVtIM162+9i5zjPBMU0yYYFPy+chyo5ecB5Ots/WrRMEEfeUzgTuxBdmroe
4Dvm4n5tNGO5UnV78104se67bun2hGo+rbkBfWo+SZQ4Br0U17ivmliLG/ySwp2V7c9BC+6TKecf
f4Aap6ltusNudAIG84LfbmRF60jR48qrq9gokSFXFzZDPcxkC+mLDQeuFuY/7sDJxJ4iU74E2CLz
+lpVH1kC+lAQOW3U/gv891PmQh7f5DRW/9WlJyLvdCmys0sneLRIM5NnrNNDRi73Z8KkW6XvM0Sa
Suu5TVATEQk/GerSMVgEZW9UJer+zF8s1DuAPCAjiNrKh13M/+bG3lAneetTkPo3NljmWEgIQhvN
O1S4muxPPgDGLR3eSTGdCZO9GklnW6TSEjVib/z9+xW/WD84z7OmsFlx2OlgO4JUdO75WO5qTxt3
0fjrBIcAlBS8DO7cW64onWa1l1sSxYap04k3X3f0kofn+/m5ukvhbGhAWA71gr+ei8zARc+qxWUr
CJWM5l6S6xonDjdYYB7hUcu41VW2uvx6dSOnXIOmtg52w4ekOy4/0PmDDTuFzPnBNZY4I1I8ZR21
tLPIqiq4mD5aZIa9vw4Ub8G9C7xAUK2Y/yzRzSCArNJDJd4jVhFLO2dpSz19am+ODlsJhi79Q0rV
0Rk8yLCRBlVGHUy+374BE2C6O1thE0ZFWpNnB6Cptp9zJfoh8l7CcEeGzTeHnbq4/RGx8Butmz6j
2IPz4g2tgOhCKd4c6ZY8um9V8PU4NXR9JGL+p/68mcB93UdxJRHhnDAL316g5gYC5njNtUnQKU1T
qqgxJRYq6fqEiBk7VqljXPj6ZXhxz5Ap9La0jvdvWyWy6D/jvfgHo3q3pf/lCruDR2Qu17Hus8o0
aJgzHZG8j0AVcTzrnhP5HkeCMHcXWI+cOPR5SxoQTZWDGLFlJSnNTU6+pV/rM1Qj5BfCqmKm1j7C
1eGblla1WymYhSa0ltZULSJEViPiYfmeg2q54dPX7s+iqGn2/8rQQgdWAoI28IAlqlD/WEsulQ3A
amifW8cZgI5wQztniu9DxLxA0444rCJvqMFezJ8j6gdCDOH3DyfNvaNv116Gyq+XVYO4ipugHcAs
Xg43fzRwgC5fdL2EKf4QqiocvwR66KhESMgxe/8VAVDBnTuifX8nFTLAO4ck9n6JoWjEoSVwdLq/
CMre3D1opT2BIZK57rHSvIfcGWU18a3JHI9X/xDyLFeGhuKSKWa46/cscNhgv9c6aC8DtJ7BjNVS
N2vAOw+cENhg6KSn9zlibfY7rItUH5O4rY5IHtybJZ0ofc7jstZjtfLN5zul8RBzDGgj9m8oG+Fh
li81DS+0EOt/ZEjf6eCMkm/Tm8Z/BUKxNZzQ97dYR63LISEgv7URbOX8Y63iu6VneRZcAXjPUzVW
tjkiCh2+tGHUUIys8XrhysQDUWkoa9nYzR5UFKVotojJc+rKxTxuK0jb8raUvt71G5+J9N5uro0n
V7DPwfQHCLStE/NoDjDfuXtkXoVlqnq2GrjpjrVyspJMTolEl8KnwRz9js75ofh3qxhiNa260I1v
gaZbjrLBqLksSzZaKkCsLWvR2g9rcNNqlaLokzP8S0NbiLs4XryP+SFZNSRmL4FCgQd1Sce+43U8
osJaANyU9cRG079p/QZUFiE9PMrvfLMuHSs6JDOzirE4ZaI62sjQ3D8Nxh9Rfuk+2fpWCvyfKzZg
zXloMv0Ur+94IUb+Qai/kggE8dJlG0MZkHFl9PH7kdJVj0bdXUf1OgV6QSSbS/SVVRBFzjTIrnRl
epBDKZfJ8uUE6HqQBxy75vtmC6q8AJJr3Dzr4VokaSdlij9c6Oio/p9U3wCTJ4mYmdMo0Tv2SNX8
QCo+Faa7zcrXLflEUUBQqe5Xosxty7aj5BSeRA2UF6PmmiQJ/fvAwSSHYBLD//CuJ6S+7HhFO5zA
pxYXtbbwX5Uzq1h8eQ4WiDl6xSJfFeXoom5O63uHYRYasn7z9HLqVX8++l+znVHIVvjPgEdbT7Az
ITX2JNy46Eb8NdcjlwxK0NFQfMFrCXPAIrI8Z1SMbW0epwPsQI7e61TWImtEnsb4BTTOMva5W19h
r/wZOkBdPnajWTCzS+57D108G2laQzsTAE/qBxN5cigA5qWTZiLIZFLHfWSj76sb96kcd60wr43C
3VZomZeCYIlr+8J6pztAeO8jQ3t5uRAEWmiKKJJVAhhuKUGW0yksA5L/5wotuESs/lXTWQeZKG6D
DW4dJm3kCapD50QUzIwI7fk0z6co9PqnVHsVgCfhCNDwK6TjCvYwk6tzf/Q0tJzucmaoiuoS2iyP
Wlns2pvTPc/z+14qID9b3gM03/9uMgSneX5kNA4TCCWmItYLYK1SfbtP0xWNjriDaUmImWgrHaJE
Y9rpSnwBw2Ezz82IOacrUfA/C0iK1S34yM+Zeseyv+F1oAte38wgnN7t+9CTWXmrmE1vIl//LuCD
q4liqKVF6KUUWRTu/1CzlxZuaXWp3JmvRwhh89LyC7KD/Xtpf2BZK4hR5bMHndn7ZeomI9IblxSB
tQIzbf71ZE+EmKLI5h7ZZE2r1QaZTemmRl9kxBR1EVEOQzY4hquytuUt8RWPS6DL3fKyGM1zBkO1
sNUF0Gy15BM0FWr6ZGuxmbHfAhwv1jowdqJC6k/V0IbKwkcLb5gupK6nCgGXoOUdHtgNnwl9qo0/
eaXar1who35msE1iCRkdCFuPQE2HUSCYiP/30fFXglbi+JYYOkPBW8JCrjlKCs8HOdLnIg6zf4xK
P4JVF+269QKEGncV8ozreVq/6OB4ggimP0WrJDJ6FemzQoIePC4wYrZagJOdtSVasvu9neXrSJ8i
JZKjrt9M0+ORq0n+Q74GUB1OvSc1JVOp+Cgfo9Y+ktIMICTPqdW7VArj4ou+s1Tx86kxFIvZ3tbe
WorDrBA0roqY6MOR2bw6G89XaAyRQqeKBGCg2MZ6cZgA3xMw8FQU1HJUCKbVVMLce9f9U43tMYsS
duwbVBy8hJ2iWf4nr8+LtmYDiy3Bk7u6/fQlEqlomuXFJqHDAFQabKnYwnqUZLH/jsAGFmRTEQzr
qkoRfQ3A2cP13ld48jc1BOrs3ufPh0QHQ71hjK4+y/LLNSkLGbTJG1sEPXuIuzeQgypz6Aubqz74
oU+hfHsZv5AZxY8w+yx9j/Y9UVSQHU0XXxCAzZDBwwGZ2ySkGybDhnd4Cd3DcKL9GJJC3DJr99NW
iuUohII284diWy1F4dPIZ5zPqvZVRxeDvkPGKR4zFluy3dg/PrvSdPVj3X6p+RCdKrvLsb0DFfoO
6JIgbGZLG88yycCp1CVv6j1nNvlGw2pXwZlliw5tffWju6XicINf/MZNxhUJzEx+LEGm7v615tpJ
gWB/bHih1BUsDZrfDmUczepviUPqk5rdhX9ZjsgI2aoUsccLpvVIY/LtKj3vcpHFo9dquCMay8LJ
sEsqtUhu8L8+JiPXPfzpTGsEOCJheJASl7MHO1xr28r2sl5Bd4l2uqzPda8N2fOSrnDXi8+bqNQF
wpFefl6Hn0t/W21szB9/VAgSOug4LZ8nucegovWrJydURHyi65enINqeUlfDFFywhy3xKHR3rJEN
wirNK5HSdrx/xuj8+06hYvfoG0VY3g8gBeVjbDKZMk7EPNHTrIdwkbGP5iehFABA0/gB31bpVW6c
17BsCMWu0bsRkHprCS8R2sbOtNLn/JqC0gnx164VDPp1pwo6BCXzXr+MktUxSMNY6Gmzz3oCjltz
/Ry4TDioly/wAqyicsDtd1RIJAMcscosMv2iwlZ2QJOUvbCme2+3Rx3uvEcO+GBZOZmZr43JpD1e
KdpXza8QpCm0K+YBvMpQ4Lyd4eQqMoTTzWDeadKsdmOlUdxWoU8OrQ03bn9JtMEdNPK93QlTwD3V
6oiSLnPVlNA3yNQyJQAbIpyNu3D5wiAwd41J9hiLUyRPIIRjJ8DPq9d4s9af9TQfHj1esJgO0BjI
6fJwpFE/BECJLZpMncON/Mxwrr3dwHNYJAyDPaUqHs1R3GRLGA4ZQQDnOeUax4DCbOgZgimQvja4
8ACJo7/cpOK874LyoTY2Xj+mgIx7SqCSCDpqo0TuhdJLlrG1kp0dllVrkauNflSarLqgulOEcNRz
OJeEI6OWSaTl6jnSec9yhMcQpkW+RluFWrxr6/wqKHUEk1PL4F8+RrZB6quj2zmmdgsHrwbvRu7l
gVk47fakSxczlWeP+IgbHK8uLPvojznRRmTMV7De8BCfZuPxswvbVX+nEQrdEiD6iJ/vWw3horuO
jYj+AHMKCpv4EBGDLp9SLnaBOh9Tu6KzqSvgtMCIVDdGkdapY0H5xtxOynCXv/30wG1s9Zc36WuX
9uVS8aAsRJZtAucTESxB/vLhoqnH9LI1rqKbwhBf9yJlxzOk5FfuCl7HIb0rRCHbnHXq63UAox+p
vz/9Tc4Aa28Tk7ebrvVNLGgFxmGkW0LQJNJ+o38HeDbyIQmlqK2T02Fsy0bSJ27FPaikvSv48uEe
aYKMmAzIXIwKo3yYdFmzK4LXmS5SG9l9f1FjcwbgPXSWC0gv67AoyeRGYM8IQiH5+EufjP71gijX
GwlpERLl6zOrWIEHbetkISvbR5P7+FcoBoex4hDfLMkQQ6XQEbm5LwzpXffvcuWx5VlAmtc0r1br
PGk6jRO/a9ZmmS0nk094hEUVHl60Jm6iz+AL+OvK/wxZsY3/xaiUAU4O/1UGjvNflXOek4Ank+eZ
Mq/6QrVkWXNoz79dxv3ac18MZfCapi6j1cEDE08vwNTQlzz965OtD/BlsRqGAf1t8d6UryysTSft
YI9RkUL88Eli2vA1vXkhKocNAZT/DqrtcpPlwf+uI/sXJW9TNCadLPj5JqP2b0l9wesXL25jYdwT
q9Gshh5PfcvAVqjFEBNsyP+ZuyTdoubZ9YevWCgBxvkR0YqH4u/AFmIDCZo7EDKmabLQwDlzwi/x
xjx4dLkBc+PJGn1ssbPjAa/1jhGCbH/cCVbBb4R5LiD1qTliYLdMLo6gljohExy5holjGN/2zpfg
jyrklMTIRWjCq/b+thpy4AAcefBp/BQMRnygSD8YmknrrwDZszi+IWeiVcBtvuwnvHdgnFehhSy1
vQYCNpSvOwIJmPtT055rqRbvACxfDBQ2ey06DjlRWWiQ3NwxDtzn0JTVb/UzcpibVNOlN+7LPg3x
c+KKDtQ89Vi2plZiRlRM7+LCioL/KmpCFCqD/kdTANt7fgaeSnFvrKOmGxvzG/DrbzxVt7Q33OB+
HtfTyqswfKNwXy0oiCoWvlVeVbKuA8tzvyy8MBAIdUy8h0drluKkDreaYK7AklZ2S9t5ZzfVc8Pm
TpXKAFc4+gfo93MYvD/91smO7aYpXkrHJLzvnf7BgK38EDYQPEzcjWzCG6r2JhqXUX9+nbTdbs+E
jKeqMUgmAvB+W/JFslita9gyhQjAQjv4vy7qFReyQ8xANeDezPRifQmmkNnzatVEU2K8fIEq+VKU
trS8DcCexDU3vdu+/kLrRKYA1/P9S3tFEgcR/+WR432toGLxB0OjjiH8i47zeBniRQhugSECldnG
NVHaCzmAsTd+jcsT8SLHCTV+iUiYn49KSMrFGqL/itdVUYG6LE+mcBHfNQGNr424fTd+qz4pQz96
clo81QmOlMhcu5djp0Gr20uR9eZZtTthreZ2jaC86v5bOEeNbvrQo57cSrfBkMON4ayezWM2IZ4+
Wy5DMwo2J74NPJSObSJVVKI8B8Mk08tG83ROyuYyoSQLt+m2t7dNKx91/huA+DUvNipEDu9/riw+
cgH3KaNHY2xQS3EJASBN3d1OWFbmmucdQU+rSIomnaJfIyhngcciNlspTzm+AmcA5ekSWwdAehFn
ZznvmalcU/Bh9f47cvEVDVvSpMetiq3Zg3TnfQUTxOZAfE8Y/V5Tjumv1AO6kgs3z7lbjp78Hhho
xVf3EGZXHIVZhFqMqgvVCNxZWIVYS/SlJ0wtz+RQ7coAWdLX6yBhGmZrQZeGiB7U3YqZIZIEXcsl
z29LczgD8CN96C9kVhFGfHhzlqG34FDQHEKGlV8K/Lpy7WgEkSjEGXLGwOm7q3otlQa0m2g8R7Mq
NVOIMPvfBtkcBxV8uP14GjMV4tQ5JoJQY2OWN1SYSh0gSPjkipgiLHdQEzW2pPfrr8bBCsVCf460
gQzKUzXiQfWUXtQD6trfZyKqqnosVyWT8mceZW/vNYNIrZYeiNAVCgj9rcYUTrldKdjyHnC2dFJS
KgYD0a2D4YdgE6lZ/8fET+HsPeJ9/qACGA0WQVEBi4bnE5kqbxXift7/tbIvXkCQwxI83P0zLz+w
YnGXmyG4hRx4UOzuctNailjr2xcK6gz6wfl+KQhPRfzcD/ONERmF7IgGByhEyHP0l518FaIU1qMl
/AMsR0JBvNKzflGz8rIFEP3hXyzg2l2vzTDjvtVXQtBqDTvwUlK/DbCvm4eIBqFH+DuWSvZ2jmQz
fDVCHht722C7LfRtyeV6PwQP3Kf6diWpWbChvu5uVwjt4cbhEb0Yt9foJAfOcS+dpRB8YyZuTSff
/UDrVVNlYUCqMj5cbZbY/Xf1+/FMnuKL4B368yGGLaMHaHi8YUsKsRW2RmdnR0kLCRU5jUgxKufv
gPq1zGG4mpeNgDQhkmrZuaAG9PHYvxzhWpmTk8BT0VI7YaLoWF+Dk4NQK9oCvS8O7FrbM77ZEbRI
Uq5/1xj/HyGjqcPJr8qJYSVR9B2Bvg1voyjVwj8LCNWyeRaOeaMuO3vHYM/ok/z5eOV4a+rp7Bpc
xQs4rG+XpzshJTZ5KgHFbsChOrqnat7VoY2TZrUBpgfF7OTF3TxdCDWI/Teg+AriTFjtHt1GyLZ5
T4m/4/XUB6wI3BJ1pVlbtb21spCVEpZJxEskj1Rj65t9JYrrJ48qJFM9TOh2xEIZCS8dljKt2nBN
h7eLOL/GZCMpecCWuV/CGytkSBECF3uqLa+CxoZZOo4LqtHoiS1A5x4iFYxC4fTYJ2QQ/VPKkVGC
805GU6Vz7SVdwZfZ9M9Ao8rp8fY1eESB/2tq+fBDI2Jb5F4N1sgq0WT/D2EvV599LB2PAlNJYYOC
baxOoyH2pxV6Gh9qA2+jv/7ytsG6XO6JJvuuSSeNqhEDbCHnAkkub8/iBzkjH5MRCvH5ksSPQASQ
pxFoiiTIATTiUerpUDMdkeZw1dFcmbIttpD3q6ZBWWPhKno4AIgAqzq3QMxrpmx1/fW1O1nrng+r
X8nO1oRC5Y7PGWlmPDpHPlsG11H+h62EHLx1BkeuYyfw3Tm1Pjz6qgWmK9cATVXf22+NKc4yBwku
E5ijz3SIXhe1V5huzA0ZCOJaoMXvToKMYto0K8heR451RPmOTfKp0n71W1rXGcC38KpzQ8yOCOCc
skZpgkQd5edaCzeSHQ5OPK7jIk5Qa/Ci+9Zwij8EM+oxQXKOMXTrKiCNsw0i9nwkb3/2wAs0Cc/F
jPFwojwyCuwW5QlI6VLcESW6JOixPDPLheOhcuDZg6k1sO2igiiGRvmW4Q1QwGbToIHrJzECv8M2
ZQlPBMyMgodfLYLWWMD9JMDtpD1tdaHDiIUu13Ct/8vJe0HI3QR8iw1cIkxjg5cPvnWfTPZ18O70
augH8AYrX25zxId6qIAU3bQFeBLpcgRN9UOYRLSdGNzAtHPR6Svdk7UroTd2iAgkNfB6ZmZEEcdX
GhXJEmNaE/yByyMWWrds8SRvLENzEX9cCw3m+vtr6FUjNfBAYV1P0u2wXwTdJ0LfQFwyM4j79A5c
SyKOnxLk4IC5ka8MsA6nekLmSY7Qp0zsXPK7R3IBXhUqq5rNlzgs6yBjaly0RrWr7TH0GlvR2iW2
8JzK8DG/o8EKIceUVCrMhnjsf638BlkPpxMU0DAuXFGOt5PSru9LrPXWWgks7KGDzaLuvhpH8Ghs
MiciDLZK2ovhtJtunpVq/PWnCAbnkV19oqTJtA+776FCxHgn4wiAa/UfbOSR8UyjXKP17ISeYXPh
8PcmMP1MPHQNnHHE1LWK7QyBfAZMqHiOcytnHc1wn5AF4uAnURxbZr+D5euCf1CgfqCwQbqXUsvY
UMrd4QuFBidUEWoSS+9mfkC8uKMHgkndT8inWJqZl89EtFKfDOsZsyuf+5/zijLpRU2JIt4qN77B
KP1CTWEqk61QC+aNTgZ+WfKBa/lCFWsu5F9DTvS35Vi7zw4XCJ+9eA8X6zclet98jfis9fx6rkML
c+AmDCVci8Y5jMP9EHtVH0gEkh6Ub4pntx2OdaXn1u++U9fXCxAWYoFol+NXjLetCA+GDwUsITV9
jRFTsBeoMgJ21/GvWKoB0L8yZKGOqvmM/H1IHSevD0u3ZBkhMmSsFqSvGf2jOFbI4fskNJbbDxjv
zg+MXX5GEZSegQawrAZFmkyj1Wt3Xp4WP5O4vFYSGZYSjgtz2LB0Xb9u72ICqCEA+U4u3ufsUPIX
49djT16aBC07ZYJff/d+SJzaPrOj/RQDYBe2fQwoPt+J4TaodKmYDNHB5Yfjv+pgB5JtXik0bzpd
3Sj7y3aZJJDNTURSu3ih1USEIW49nCIWP97Q2rpFg4Tq68Pdykg713baIWxXFASwiXr7qyN7n2Yg
dmyO1xobpLu5qEaMwfKUanlg2KJBDukl9UUZ385QvuHqtNGjdOvvfzrwgll1y+YvI3Xm7ZlObnzU
a1owgfpZDnhEPGs6X2zP5vrCLKr4CuRHP9Dnl1D9DogTLF2rt0ronkqSmZwTkifDxk7Eil3DEmIn
yVzOJcax6Ewp1JEhVvV8rW6ToUmSlsYdAGNZCnlecCOzRov3EIcVTQH7emiP5AqI3yLyRL5/9Dar
oCCIEyz478qBxMoNBKxqF8NC7Pt9UJQc6J9Sa5vYtCisD/CWDkd7a0jXjMEW72RzWJ9YZ8WIAzl/
hardUFWmikMsyM5U/yyFlFx/nUL/uks1Wl3zEZMCMukrS1gopIAlXbiR6pzsH+hSNHO/zWJD1Kzb
286ecWZF3qT9W9mKg4WWTCQyQ3A2AJ/JqNq+f02xPS8tz03/N2C1BdJGxQaKc0AqWttBzTfi2f18
RID/nZhtYB9BcEugVDN+z7PMaWJ/Fy6BgBwluYCbWYzWbTjTPAg2dMaNOLdkJ+smLHAr8bhVzTVE
jZ+H+AO4c3sQpwvyddimueqnI7ncIvCXbbYGkeCHlqbl1+sgRpHu/+nvJFMLr6MsCNsji+Vl2wdO
0JYoSJXCutFnzarelPgpcBztMymhSCgIDkH0xBmqFlt1Mb6BuUFG6QLpUDEC9sQcT99QnhMQEoq0
5YHEIDsiipi9ZpUYJvbAAAc6WB6WUF5cgKZDTm/6YwVEmzEmKb+fizD+CE7bvN1u/97CoLiaVKT5
j9E2ywoqZrSyJHWxzHItS3tBSQdWHsIXjskbYqRF+OLteXNbIibyehQBztPVhcUsrTFmDol6t+JH
Xpj7RvUfftgAp8GzJkQTfTPE8vmgdYFwIM6Jg7koWBPugdYr3XAlHl5HSyHMEMKnysjDghhInhLW
5Eu8betHnb7jb3pU+cfF0IaS2IDOZKUXJAnkPaS/wfhcWFn1HRZyrBH03yGo5SlWlhlMXE3b2Yte
6LGRBOiZKo0FQzuNWa1oOLmqLiVTAjsatQD3YpdRb+Wm98KUGWKrQGNMeMO+w6LpVLs+ilMvZWO5
bP51TTnSZN0dxeB2Z0y+anx6k1yly8hwD3clGx5Xlc10P3qYnwtYeexJZDcDox4KFLD4fKAh2DiG
an7VVJCDyBYXI3k9y/aycDPKvJTX7qDpnoMNUNlkXutmm+eEQ6GZyqb8P/vVJNL7qhlGOdbIRXUX
BfbF7jHehgmBZUD9Fb6DqYbCHo/fvauC5zgoiOlmpRVbqgsHd9FV7G/aqc7Dk9nGJnHEhoDnCq2x
ZN3DqrNYH0KBlcdL+dgjB9uWCvpb9iBMO8yR/Sy/Kdm0DhtBEFlpENThndpHSFfdVzNSu/+4GP8U
og7T6ebLUrnV0bVy2yNH+QHrSMgbZXMgOkQqO8G5mq2kY0orBUgzI5XW2Y4j9PLjVRN02Ao/DnoF
mWbRw/zw7K1DUmRTWP8JY6KU64UVnTpMz074NrW7kGSSHygs6pAgH/DLGWIB6+S8BVA9s6jKNSMh
Xyw+0C3hRbR4McYsqKoWGfQNKD4MaYE8yViQAKClB5GS3ZAK2yo7T1CHLj9dDivbbLsp//KHHrbP
vcc+zCLFc1yC048rc0SyQ53dtzq+twlUKG1v9ynkzoJCWgKDMImH1V26LiJKaPIj39o9CMv2nMrl
ftTz5n0kHmmlBpCpjtBIMgPtqkY6oj/yGx2wufSZclKO0gpb5E5gFVA+MB8bzR4io0i8G7mRLEzh
ZefDFrRJXQ3F0vUxn5GiJgId6chO7oIrKvc/x2Y4aiZHB7m6+Xhb46gN1z2nK+aq/HbcWGRahGLY
UuQNAG6MYce0vSzm6hwuV+L2ZC3RHgW/XUOVAiUBjiT4KPhzU+GN+08032mG5S7SHlUewWXjBNve
G41KsuK5ZgS/X7o9Q75OY1SajJV0OyEkZw9w2c3aQ6neDYNR63tDD76v9AwWdbR2Ryg1knW+2Rh+
703aUoO9uGMKxQieR+WuV9LraBEhOrau+7aPH6/uyCVPZTpb9LW4EmLS32SpPk5ldNr0txAkjZ3W
vV+8i6Zdl8eQ8T+LPkYKrdxz39aVJOD1CSE/DT9SMDtOG+EB2uH+RgmGXhWUgx5hbdQvNzR98Qkv
iVeFtKpO0SlzkuHN6Igv2ckyI2bntMPq3mVFP1kVBnleSvUkF9CFfdWLuBiGQcv1izI4ivz8sp3B
CLRyKjrsp8UaTTa02q1VYBgXlwUddLVpPg0LUluCjnk0Y2tx1hv5yUvgr2bq+8s0CX60i9fhNdWi
XAfqNJMXNlZyRfJ+EZtc7rU7U6a5fr8lezfv4064bO3WwaqsQ396zwJ/VOTQZvJzq59PtF/KtcQC
jx0mDKVzRk3NJoSh/QWzj3wZDfR4VVks4T5/u6DtH9SQCQ41OHt8QQ6LPyAEEeA2nft/3BUFAXYC
AETaperc94i2AjMc4PgJSgHCJU+fmGJt3NS+NwiuHLMQagd2ru21odJjZX4ob9myGBalgZntsKxG
hZODvFiCC1zM0uXZx5t6OXmY4Me2AvN8xXd/Wu0k7FJlAKQ80s9vTYH716BUY5iNLB3ngA/Kwmwh
p51W/ueBDWRkSDomdpPLg+2KHVaNha55q5pMX5+lok0XE9rW992NDk/RLqd4iEml+5hPt0v4FgXu
k6ZaKGnHevJ82MApW/Nb+CtS1z135zhcEyHnoIvgYVTgICVDhp+vfzm9ZRJ7t/onw/s7x96J7puW
ifj+AQnqZ2VE/D3t4r0Sgjw9Nxm9qteOglRzMcdHFg7rra22BpynV7jIgT54BSt3T4OXt3kQ/8NM
ppvj5ql9IdhKv4Yx6ycBAQSit/mgLp7wFSUUB+wB+L907ZKEs29zzHfDQuLDvclAKDFeOVmf6B01
Kke1VcEzoo5q4fbyLp8/10j/2WyoSk+HudprHtS+ReV2vFxFkEpDENnUXwdhL08AJtzzJmdUY/s9
1vX3JZfen2XpZ+2MegtqQedHMrkPEBKMd9qoL6KT7wR4sqzFLl/PLwJDK9NLSJg6A4bw/ejF5vyZ
4adTb9p6Xdcw8hv5dCyf0+Vajw7K1wNcBg2x6SWmVq7o/Rb8nuMq2oB5cvjIVAj53Z9W+j6uHx8H
090TN/fqSGE5Yq5XZPleKr3hpoGf3awYFkLdb+jdRwsTRC4d6+mSJ9+C1SmT2F6cGMN0feoDM8rY
5lCxDG/MG/pS9Zp4DxqwZobIYP/95OlOhKhCb5UHXqHPUBhuL+9ovBPYV5qNXoe3frC88h2Vu0++
iga6qdcoIoxWfjF6vrORLswbNfxFsCL0Y+WFDb75+0xnKW6+AbQ9D/XHNNC9aG/Va1IG7IGMtIX+
S+kpZcVLwVMXINhlpU7L+j/zGszB5awmnOnF0smJTJ7FXX34d2nzu84sCn5rJDaoEj9c8hxD1/m+
40pd+yjHM2h2cE5KLVHCctHDWwFW9uxeqUD+mDziJ/jnA6aZHBii18f+oWAr2XGDF7wW8TuTNCfG
v98IAff/+GZ5rFx0r9otyXu9/uwshDEu+WrUpuhV796Qa73dIKAm+x035A0u70+QnDphJXi1gEB2
7I18gyJBfiwnRtw+Uo2o/y6UFsiZXFpF7dn/f7K2Yg2dqioufzMIn4Vvc7vdJxhyHAEsv5so6W7R
lj3jFYEQW9LyvpBDlceBuabKNd5n+TysxGp3cUrx+RRlUQ2gNtagIHvJbKCapIEb+53B8a9+lyyG
gxffKTyPjVgPfybnBEGzqOaplqa3+AtqJp8ZsKOMGJloUPDO+iMNkqnrh9+DSYtw2bSVPMfVO4ma
zf8c9FFjmJExMOML4MOeaPrEafNHVakMDxZED2brQ6Sv/NSbOW4Gu/TlCVSXgwpcDN1kWBHGwhpE
pI62fotzX8csjqtpkC/elyQWtwYvj5Ac8b1+KhY283m15RrOWjf27kZb42E/lnk+5i9wDGKkLw+f
+ndxhqyeZphOiMWNHjNlPE9Yyly2XAppuzJTVZj6u/3ooNdCAazRKwxsdZ1wN6sJvSMSYDvXwxTc
z5LUgz/SYkXbeSVaTD4ffY82PpQFM7DQwYfCDaLFNsrZ3TZVkZwukOLhm+tExaueTYg2S2TQPfBV
EYhFF7jRaZW8ImGFGD3SiL6QpbyjjWYIQbveFvifATleKarbOxPzM/t/1rd8lslSM/8DEvp56gND
Sdi4PZJbKwo6iHH5aAfFo5mns+rhnYUp7XVP1JTr1A6Nigp5KOLVc4VzbS6jSlgUcR+18fzvoxUo
dWALKQrtdTfbgo9aJMykzRHlqDmK+/SWB1pvA+vAoV1cHVR6hhbDwo80e6jYMR1ciq19NBiUTzBb
B4b0uHOca7ZSQznCWT89h3DcS6xpysuq8+a1lghrj6DIYPHuNGNFcWrzvnMpj51P1x3S0Z47hrtb
4oWtW/qNCF0fqMsCPfe2Nux2yVsy5Kf2ya48M8WOhtb9+IB7ZOfZ3xVXndPI+3zHr6SOB6KZejhd
opbFf2mJHykyL5loSS0qNkR7heP/y9r4cNKPxY5p/SOmfE6n91RexG5+MrqLnFtvO1bTK25hP3la
NS3PKW7JjXZEQ0Cz9isphqRJH8xPIX295OMD8dYG4LxwC3BwrcfVF1yZttDRthyz1wCPGBsrhIsz
oIuUzByqefxtJvtrAWfnNTWYa5w4DCXT4UefT2ohWU5vBrySLB2bcteOlQF2OahVptXxo2H2CY7G
W+8oJkhSsehqeFH2ZrFY7+ciYRg7T/fMN70Clz9+lVhd6wFQVQ0k+NQvmyjkkdP8aXar2j87/zLL
7+siRfNn+k01/qfuv68xBH2aUGDda55LZr92Vp3Obu5/Xn0zH+F9p3GXS4Ab5AhksOITnippUA9D
3GcvzKq/EsBXk/ELVjYSPBSiQKCyfHklMiH/VLKbVlZU6e/h10/QM2H47NPU1r1Cnal15Kn/iO0U
AlXYyeF9FwbKZt4llK46Dc1ecnGH8N7acjvLdkPfufO9q1EMkYs8tkRMGzlH/jVCD5E99G7p7IKM
b65042VsuZfNc3WTDbZND/FZbZBfu4tOmR9Ybdx+kNEyRnSeReg5iw6pQ/QdTx1QbG+J+s+eFsbL
kLMmz3SWJH5ilM+nqfXrzFAxCyLvaQu6rSSfb66jJ7Wsz600RZDW7CkSYr5qTPe5IDLbG42eNRQL
b0e6Kh0Wkqw5c0q9nQt0ALdFHsfRxdUg0H00DiEJ/P/qTfifb34FJE5HZ53gDHSaxV3tVWLhmfA/
F6nNGCD+HcvFbLxQCeOdYcCi5vTs+ebcjoV+abWgtpw6RwSHU9ntRipx7WhBvc1+CAHESJ8VpLHo
wX0eImMP3XJ0lPZ72TG+yJe6qs55/pwYUDVoUE3SpOkyLCB2o6zwF18fKnsWR2aJkPt7jGTiAJ9e
/aRpFaTTBl4V5q0V4+p/sVcdSuhUrD+2M8PhY0/qELxJR3CON9ULv3mbGpXAWl4DKeysg4Rof4mO
jr2U1VGN9fh7oIbhBoCg3g4yei941V2eItxXzmcsf8WYmbuZB2TU7UPSkhi/kUCn1AzJPlxS98oB
/vGJiKqK8qGw1W8/LLuHxNXN2tBL/e+F43EZIbqHwyQz2M2MSZfULEWCioG3NdUlKf+Lv2jHUWvP
jottqChiOT9v6g8PISwOmEO9787VzDUb7/ulD2nyTLnCc8OZtmiV6/rA/aAU0pX8xC9C+kF8dVAU
HxGCElMNKF9VsUzHTqpl7/iRNpi0BNfTFzjtYDRh39DGc3KJi368T+3xGnemzypHf51HHJ30wmzo
hUjyNqyb+EpHM06wJ+ahps1xpx9rGsLmbMNnyBLh9MZ/9W3GK/KNUprgXMuhltQaCHw0f7BAlDuL
gSFgAPIwbNJc8yxYYXLklZBiR/DBmcVc46iXtiDev3rdiHgvoWSgeRBXDa5LS9QD5t60V1/ytffm
CWXM8UYewsJfFaz/dJ4Nw2P0YRZD3fv/Xo8e98nYqROVKhfBQcSXB6xfiPUYC6G/J9RhLG1HulX2
ynlH07Q5cs92ORXWWEk2b+ZnW51KN45qRS5Nlek8o0zmkt3f/d/k/Z8IsPRRXhrTTVnvPVoTy8j8
u4sfeUE4MA/SWqoT+mmCUIIrV9xuMXN5ff3o3BeVX7AYuVgMHGr87DsHRQaT4cA7O0DLHgiBJTw4
Gy+Pe9TGG4f69dBcwSH9nOGesevQNUOl+hJFuM+nzSHYLwNFDQBB0e9Ow6taOscrqQ6wFBk41hvA
X+NwJJZ/VGA0FvFsP/oDPHU+t3yyQ3g717Jin9BZe8VreSl0xqoj8eyR2Nlg2SCU3S5TCHMigLxW
8kafDZdgVV4+gCt6WXdfPyPZ9ASlcqEqvPHfXYEX/4X+yqkocB+fJm86QdrzhzOasG8M4DRFTCLx
VXRW4lMF/BRdEfnSppx1qXNpqntFQPLo6KuF6sKVGAHPCCqLhAOzllyzgqGELvO27G1N88UfsCN3
BdJpNQ08OSGCk6waufm2ZKns447qxmpp8htmvtyyJ3QxulkpCYTilGi0q1VhToMS5u8ScVPjF55+
7MC5DMFsYK4/xWU+vMQsBVjbJ9w32DBGyaRsIaDGYSl1jyfVRldpKExJKdkfiI7GNv2c7rM02YH4
thn6fUjRibPQ75ZBew4zkTUHhMho1iFapS6HECpXn7uywtTv97VwDxuVHU694pSl8fQP2y4agnun
8F4tZKrIaIuC1vodDwflWPLXlyXom2qFhOQqZ5SAfI2Ouqlz0FvOkpeD59PiDcuxgzJwKcwfdg8U
eLijAL1ixfUNpQ0oIbbqLtyFdxeq4H6GS65W3q8n2sJYChGR2/WHnVDfUqF+pHgHrIO4tyeMmWpO
X642oKkjem39hjP6dEE98ItGl/j3esLsuxaeJkA4uuJeZKfYc/gFRVtiRqFubPlWJ9UXpN2JtPoQ
yMvEFYehjJMpFihU1ybxHjVPd1OtEWzwWdVg8EQVZ/7ofYOemF5BPLHfv3B8UDI/UKy0rx+p8yH9
6GySD2fc59fXDXAaIfdIg0AudNBtvg7OtUfUttzV2YA+9mdrGosAD+ocD8GrqYwyAgVvIk7LxFKA
Q7NLCb0wsPgDOc4W4OqoYO0bMf5IIwCZmuIcyR5GxoIKWBV5aY+LYSzd3yhEN/ckGlrtGgMX1WXO
tmqU2qtfyXLnAbMfx9Qv942S/ucBQ2YsRPYnSvBYEpFPCjyOw9J5nwOlC5U8QBdGokkG2SJTYEK5
iZJAHj9KcMfa2UedqZXigecWUXNuqw7hpi6jZksxz0wRRiDo4OKLt1JXSdyQXDRSlTjYxpiQvRQT
bc5fiv3IbWyq94m4LYJDZ8tuLuzAyfkbv+HIF3DMgDZAWcSN9K2jLGFbDNrIT1frv0HQHdHPVrzv
wUYMSV0gNH0Mj5UTcOWRavWGa3iU5ATZ86yRe9c+uUwO1f020w6jO1yWjAx1tZdenp9swxjOPpsn
ZsEa1xF/Bw3u/pRfCNPUG8BRvN9nCcY/+1/f6qvW6UKOBeoqE0vpIRrmslix5VJDSgYJz6u5J6a7
AavwJHGBB27jb68+OH8m0UZIUyI9KiIt/5w7XYQIytQE68tYpRue5ybp8sy266qrnqkFEmUkofMq
HNdpnHmKU2ULYYgQvPalB4LWJlhiY5cmrczKrX45ZccA7k/KkP2Inm3QHKLgKolKviHbqoMUst7B
AP4E0nXqjWCEPlZyUlZfUs7rzQotaHX1Oevmq/WlCoTjF+rsNjqTf4p1cPJq/3BOVGeIEwZbLs1n
Lnwivq36BwC7T0YTJ8KF5AWAPpZwmgwcTlYzkkPsKVZkCQpkL6n6uTFXmVqvdHVBw3FfA1t2+SJs
eKgWAEYzKRbUAUVUHoAtedE8c7x8/ksdVpLd+xn3Ta8d5AzMMW3GQmk3Q4QLJhyAqP/tRanvY0PO
cmJRMJRzxz1ptORLqCx8iYdvJI67rVnb6ua9/9EPcD7f5HP0HU51U/urTMZ50rnVsDYusGTGRG3I
d2IJbv8zhACUcnfEqtkBlN15JVyhRLQTkQkW+yWoVpVZixoUTB33R6uXGAWub7fErSVe7wpLPsKy
QT2TO/3FGcJGDejO3xLSKrUSLPwKT9qwNK3Nj5axX5UiYV7SUGAGFIyT4PNQD9fCPpKUfdPjY+Hb
AMJzj44ZuzN5Tfl8XIFco0IzSQEDBdWSSPqKlXOMN6TkKslwM7syUDO4ZziSHdn3EK9wBGdGichn
CJXEKFdBVbRmCO2C7SA9v0c0YfYZDakYzSF//TMhPlcOyqvddvzTCXYEs53dBB/qC2pbt8CxjR9h
6FXWo829NzUFtUqcrjI261swltNhRz0aU4vIHcP+VlB1nrbCMKhyFQ/ozScmTOxGW4EGvcjEdtAw
QQEBTk896ovEstEvDaN36A3OUpp6dusskD7PCs3USyoDRC7prT/Vv1xh5DvunHWpxxs8afzqNNyV
RITfeurxFSHiv4CnvC7Mkx//xF7l4iGdhdZrG2DrcMEa9Sp+BaQ1YYLJpawVm8ToL+jV5NTSDJsL
g4d6AjiMKHT9KZBTI4udqcfe9YoGxjGsbavB8GHmw4X/SobebXJcjvsekTWOldrWjAsB1EzBnZG/
z7KMZilS1WJVB3rGQP3LpUTK8eI29enA0oxUlAPHbtaxNEtSzac+JlxU7pSRPb+zrUsAFB4l9gzC
hybTGrQV3ZkPJPXAxk20+VXGhDQ5ZmlJTVC8ZvZN1zrZVJihkFq7xs+6FqGItJqm7VRbN/SmT0qz
Br9ul34RVUJ3KyD/vdTmRgHFz27RShH19wY1qmxm/Ra1MAB9qqvcVc2pyXS7HlXHecWzWfFDGWNK
c4cC+DVIoipuQ0uKwkrndKWYHxwdkpjEax1vuyQ6pk6E1fJdrbwV5Lq8uNpl4waDFBemJuVdYdx1
ycvLb/blF66jt3BlDpB2lbNzB5eZGzGMjlCIAK6nrwHk8YTGzGsB6t/t0T8qRrLfbp7DqH+UyspU
5MkAGg7Ri/LtXRHU/7AyNncRmH4kkGUzzKJdVNKCd2YUaBy0VA17LSiKSoF/2/wgY7M3iDMfa73c
Knq1cKMwxF0mBh+3JiqEfB1PtXukr1sKOhFwhPDKbXZswEmdRnDIxcwnAdd997625hjG2SYyMI3b
Z4DnWu5eJkwWzAc6B5nvZfggO/0+UmMAI1gyPmsFj9xiqk0TrhNjXn76en8uOk4O6zzzAwse7omC
6DRqObjUAyJA1SB9klk8jmvHePFjZ3qwj+KKrP0MCbfuGuzGya4KGbjclazbLGl2qoOIvLQcW2oE
CcKsva+Qeq5081zXhCQuyMrmerMRC8kTBb59kp3RZCtV1ZH5m2+0OIs1cENLQNDx40HwFG9U6Elp
HL768qW9uR0O6e3Z3VqgpvWpj3dh5Zn5mNgVZoj+ktSSppsmg4mSpAKG7cwM5mtM+81v/cr/gNLS
KcBrCAFwWpMLRq5ac0pSgcxM6NdGW8z+L+/qt1wWr7Kwf0hs48+RSrv4RGG7rpYgBe2sM8+xH4PR
JsKK6MD8Uq6LJuhYSagbBjmr6aR7uF84PtWyhKoglb7HxMY5SY+vPxP/t1+VqYon59E7ZiwspOrw
bDKFzAB1iLXqh/9s+KQwSbhdQOFLLqvJFLVQzEqTsC13LpUBdx2gHyLDGrqCeSRdPlKNvU7tgY1D
HCXwwl4ZyutWr1qd6Ov80srIOBTDtyDsYjVLpPoj/tQxrFlyXAezyLgJ5Pm8nBlOJDztOCD7heRr
T4FY5X9UN/+UPG2/VmeAGdBJlBSMsgU98UzDeZPwFx5AmdR7XiNzZTeT9pWT3mqKAjVHjnHx0dNU
k9jXzLkv66SZWJE/1dZEJ5JL/wt1i11a6yfPgpz7LRjFYx5JPrGvSpKxVs0eEftJmBJDyPt9oSlm
Bou08i8eQdAGbHX6vO+3+M6BNDgOEXHY6tVspL9oqTbpj/FFHPJHKyy2mXLo88q0WVoQxyiP/9ps
pVZW4raL9BrZCUFsDQzFqf4MNvUNcNB9M/Wyw/T3F92MQmIClQi0iQa+O3A3Ex4na8GF2JF+IZgv
eImbYXTuWk3ozRjV4srEekK27VXj+dY+Iq2RGZi4WTORw9/NDP6H1yI0qlaGSBM55P6DyIIE+/Be
py+y1KhCXVdpbA96K97tG0GY8ryLgcIfgIsup8R1jJPEQdLgjEdwzc+wlgrSsp62ms5QUA815NDS
hrTKlQj5T6Sax21sMaHgS3TRg5uyhEHMLJ+v4lmaVAwAbHoxjB1NE9mJM5+dW3BrZNAXwppXg25/
kKQnKmSS48crMk2wyvintU7LUcHZ4nBvkxiZiE1P+HJ2Vxe/yGnApzblPZJxaNRM26wJQEHJ9QRT
7m3MRd6l/rlaeJd1Lkg+JLbWd+1VUi4WaOpKixZiwvMdx4E9g88kumDYxvkZGL6+UQnDsNQyxw66
XaMNJMUsGOdqRlqhuYX5902CFFhqN5HEWnmY5u7Yvg7XQeHROz2Gm86l/Q+4LXMvodiM+eYZzbzX
WmLtxcm6Da+wwKvaUjhImqDt2vnRmhEXzdduSshaWLi2Lrfh97H1t3A6xlO3o1hm2kw/44PrMHVA
P+vtvHmm8Jn0Yx+wbEyKg5mi98MQb2LgUX4JBUSkGNSWE772BmekvxtQOsc9y7bM+B9P6p9P0/Sm
V1P6dT6RKeyk9uL5Fp7iJp1tqAXpkKvUNa1sxCHHBB2uPvkPRCaYFCYodWgMkLrYmXsA+6nig9zS
1Kh+f+Ouw+HrmssK/05ZCG+xT+BiIUhgfReh+uoEnR+vkp8FVYyhWtfI7k0rtW7TsD7lkyCejhkM
XE+fe0K/3wgsqXAiANX5wHHObHjvXDV3Bay504uo3KZLXarNgrtMPHHjQvq3bRN3p90ZvV0trrq5
12acAhwKW35veXRlsOWU+6w0i929foNJSgZTsZGTm/4zyRyR08F4MhtBlhdEoEQqZppKrYg103dd
bV959YPExreaZ4PRIW1/0Jm3g3fsMzrbqi8CwnhNnmsF/Z0QIgzk21eIqlN63XT8SI/23f5Ul88S
LdOU7Ch+pGoEYuZoqQZd0gdAG9X5ZXGl5dwpB4H6ttNAtrgZ9C6dO82vJgqVkm09tU5Afe6FvOm+
nBjbvf/a274/O5JhMIJwmM+4BIeHqTPiiVzHgBHxHNv/tLpuYUNSGqKFnVtMAmsc4pF/wDYPDAXK
r3q8s+6GEVz5VSWN+6sAQQgWtQ/F7QTz8EAvn2j5GSjPgKxajeAYJ5vw0NC5tv74qP4iouo75ast
h0jXhPXVphYSsuznL/9oEQz3d5/wA1KHIQ7q88oML3GdgcwNIuMXaPwTSRbw9HlyR6zvfXHIL3AG
w8O1EYiofrdLUNH6R6GWNt3h37GVngAeaOn+aSayMk0ybAc6zCEapQE1xdfb9Vloa1/yMRm4srB5
NhGJ/IbizFafCLuNrdk2pw2eM8hb/snr9k5U+0tWQft7CNscfVfrEBSLZKuxcpburQK6IOYt5jMt
CifgABES+FTN0Pu+fgoDl8kuKXblrvS/z7vMKS60lGFLJiYjvTgDxkbeKwdlpGvGN6fqnVfGohlP
Ff/nbVAaKXmFDt9/Xens59Zfg/ftA0NlQvcWN5Sb+hkrbocUgx6wlQc9iQQy++bGBZT2mbEjP3Mu
NlAbKUisk50Dka8jre3z5a2cfTUg8yJJkxTPBAT5tSlKRume7ZzVv90DLWHOMoRdJgogrtRqnXm/
/3GRdu8uyjK9WhcuwM9VWZDKiwKbmMH4iN39r6XVQgU81CwbmUwUhTzR5TJ6xE4vKTrVnO+RXgWh
tnEC4eASGjD0f8L0u0nvhIXLqIVkZkMUAxQIf84ayF1Auv6Rqas7gP/FXiO855OCJDek6Hw2NjFY
pGVF54Oc8ez0jCmeC7ltjeRxXk8ony9xbFO29/kSGwsCm2FYI/fF1Uxn20gN5ia0KjfTcc2MugGH
sUsY7h7wyORJtFmrZikcZGyLEmOWA4XcbXisZxgoU7fJIGwbEPFOfD7+zv6cAPciYPYSsaN1NL44
C1cX7T/bGnVUf7lNEfgXbX1NqXmDZ/I+cpqCrel27CKccqDy+4js6Fb63i30veqnJjYI3BzrD3pT
ZN3I5rjY+N7A+yS9YLXkd4wC6avd/eE4DcTo9RI1yaGycuRc+nadCfZU50TzurxSZYO8rmEROWoy
YKT1/oOo3vgUFKSykBzhFzDkjA2ASQWxkc0nr1HB1hKXw/JEprQNVZ3SHiWuR5O8P+kWivJ8Y/TE
V+1xAbgYmNlojsixvhE2Rn4h5Di7B8VGIdSxOkKG8QRlPnIGYWAXGI20RZzM+KyRrVTGBAYAi/um
g/9dsySPW1NENkkb40jY7A+fdiNQ9thKGZ0dmOFKN1Ar7kFn6m/2T5zNiil2E0hEBQ4Bx1sIH1l7
hh58jKQYOJ8Fe6eeixESHG4gITY2Jx+8O8JaZhyVfs6yCdY9U1ytCt1oulAD4sfXjXVCPzTf9rU4
s7BXNYkK3Rv9I2nY5V8YrSFOtnkFCiGpoLLH4prQ/23kg+vTXCapIEyBt0H6DVKO4KqgvNf/wOto
HuUbVsCJHVovteG5bwr+DGwjUFjRc4tnax7+voM7c+kN4hFoWuOe5JdQldShA6ZLTHC1DKWSJwhP
SEBJA7+Jq+JqU7p6GHNN704x0eRBhuqJ9F7T9Jj68/X1pMBw2VegY0a4kke8ITGVbjTctE790FXZ
xMO4S0syV04UQyH/C/whlNqkZ0mYftItzPEpCkwJ5QLEEzdHSLM6htmVbuuw2cCKxF4H6RnfWh+D
5pVMdDqCXdWREWaXy2gsiTvlfc22yyAS5OUmFA0MV0zyL7AFw2RNiYlxPHDL7XmXpkmbjx2RelDs
hQvURBAF5yAzHzZKCudnWbK3gLNK+i1lhcaYtQizfKwOtGcLjqBe6XgW72O3T0nNYc8Pfd7f+dCV
Imhs5D9G//xJ/58zPpCRMGg1OdKWMPoFpIQ52xhViYBrlqJ1z7+iIB4bACQB6SkthOG1MxLSsgDz
V0qv4kA5YqHzpmge0tekU7KjDOJ+ui8RSN8QiZE7ZvOD0bWYJ08oEJWuSKRHrRNWW4uHs0NmNZOK
uDFCmvFCfZy8pWRg2DFd7D5CJIeh0NktKKT2m3bmIpRbyoVmvbOG3oZZgdnqXGnhgZ4wvfDWH8d/
VzHfY/+Zh99ebxm8oGIalpXN4zKYsS+ItnnLm3A7uQPGQNBmtkDM83cm18mH2+Fdka7QsubZYmmH
TRpDDQALcd1AKPG7PjRuaEy0TH6WWtIYy/cMC1dljFpwxAvm7V7MQynmLOzr7jpCw2K5UlI6kcHj
jP8KdevQ1sx8KuSiTXpkQkn+0POCQG4/efrAdO+jEs0o/4lTihVQ2t5bh5W4dTePh60fpAqVf/73
j5t68JnyyM9O2yKyjKfT5kCM+j4n/eAofNZ4S/V9QHt8lKWGa7Vb9AxWG2etBreuDxBm35yqTi+I
NdGX5NDoPql2bDejEJ/4yEH44jdXYbL+N8Ot6oeVNVTt1p643Tn1/9WZunah+PXZHqavmtO6wqNb
+AWJTZOosRG/p3aniqJfzLw5ipX3RhcbB+FEqBW3g8sJRu42FSTNo2IOlI9bqG+HaHUer1TOZzom
bt7WWvl7i4LF9WWtMUR+wzGPxiIzlFMBbOBuP+xAvjzTufOWy1OMasuhwQfDLX7m3ZDMyuxtceu8
NxJ2HumPmTTgUPqahCaGP1wX6Y6y0U1GM6H8t+lovJD4/k9YDJ5fQvthsTAo0FfDdTQjIfLRS65i
g+dpbu0bybpV6xtrZpIXyqWnBB5S/0Ru+zxuMAEhyfxBnsmH4yS3Y5HunmgF//gMRtO8PSd9vfSm
Vv8/hr7C8yrk+dnRvA30woB9s8cL+Xcnno7F4Km4/6T/ghMG6OldG5C+nKVId9FTKSjSffYgqCF1
ikGLwO7gfEN+Nw/1vj/NxsaAGdJp2W7wlQ4BxUHyxRX9k6l4zh1suHkR6rZh4AR1Dg34o52eCZQ/
kQ2UNzceuId1cDdnrZoBMwAgdvanqzeV9GEQIWWtAmaNxBdg6KhLHNkGSdoc4Yh9KaXpbB+H6Bfe
1VJe77KCsGoxf0g2C+debEsoVPRk0hCJTNvjw1fzEQ+8pO1B27wymege0oBjJ9LCOUlhq8OJ8Q/u
oY3b2iHAHgCeUByY1KN+saLjaSUrEyRoHNy/NYLxcjWA8Kw5KM6pZxtNzvipDGArSfXOKMoQw5FJ
l8XwEbi5fE8eLuqLuYUpfmwVfWU4hJRYbGhJ3oX+aOGJXMPWEmVbtUTrCH6O+zBmlJjVI/2ZuwNR
EkqFvI/YIvYfmbMJ+xe5emn399XfTjn2a3q1BoQ4anICma+g2okQdjBc21uWeBe/URcO/o6jhRLi
Xra8er/yAcediwWnrBhdSep2tcXEzKJuvUjPgo9VNEh7HgBVD2c6wnZq6zsvmO+0htWN3Q5PwOqG
bEVF9vBbzbcxhOhNiOtAm+GIe+ArwZcmIofd2Px8L20/Tz7jJCjX8cn0Y+uEPjLLUYWmIcRF07em
4vV87YLRG8UdOijMstziwbtbOUzjLGyRyXMqQBZ+xa3OgFphmZb6Fvx8WFwMHCCCSvltJ+JOI12c
JNJfkmtsd1H2GQlA/1zL/hG8kc76iBIAwUPq5hIra+BwCHTp7EAVeBywbTcqLvSuUNMY/ZBGCP3l
3ASmFlq/zqPLd+OzGHBA7jEjDmZG3V7swNCVil/Q+niiC2iTm6Jgs/osMjBuY9xKSRmPokmIVBnM
jTbseaIdI5mOseBlxZRgNJshGEm6UraEuXZ9Og11sxbxxae4IXyX5+HsHbUFBwbsIwDhv/agMpoJ
7TbomyRxcnb+D9HZI+vdL42umE3qD7Q/nGxLK5tbbkU6ETT05hqdbhjebrffdQwg4AmgimOs1ntu
JsyHbfDh/8jQN/W/rYs+VQGfarUjSQAiS29z6WWGqcJGPJX7wiuOBZ7K5uuEz0BuHOfeYIeNV8EE
kPCtJOhjfGkmx1l9TsstofmqK++i+ISoZ3gY0GyAIh+UKtXvRJicH68dL7hkxarPye18iTvPJDK9
hCILYwTNICefhdS77q+k8sm3s8XuoRXTT96gn+e1ynzguZIwXQNjlSfKhRqmQt1IrSrP3+eBPGEe
sMY6pfDffsFaioMeq19W/A2qL51xTN75LPJJ2hoxLnMsB8L4PDt26+9uIFcPjUzDpnkxb5If6wFN
Z+9vUsaZMHDgjZGm3u+BgmzfRA3blARUSDARMKeb0VSSX2wmz8S7Fngje/FV0Ont7TQq1NavL6HX
oW2EwtOlf/yVMgdStxZ9zczaAalY4WpHAzeLHZ7xJgc+9rie9fDgBlqmhecUQcEnkqzcm7ybPa4O
as65Cd5Vrf1qsuvdpSZk4pUiyyEmSe7lIdecMmpz2Eg4HNaj1i/hxEcn2GaggdLGPctj6sOYgBnE
ClTo0GRl7VgU2fptre5noRtwAPFcmSVXOvqce0ncNVbH3TMrGoDvoskWPE1EYA0qcXicyEjsENqI
zqLcCXsGP19dF9ksUCnUR7RxFT8p80kScb8Pbmfy6K32BL5n+VmBQa3id8XzaWf419QOUeyYa0pG
6c2r+haJsY5YbcnlSdwTFdWhekmyq5AnGlLawf8oNYU8HgC9pjA9dZ/hu37t8UEoBk51S25MD04M
vNW/ic8+IDQyrOhWYpV4NDGwdG1lIdPVRnTBmvYUL37k6EEjdFRDmfejqNx5QXI1mQR6NfNARzQC
BZRT28gLHRw/hm2bY48Onj5JkBEE/UM+l3bHIS4PvGdQnKtrIpAg/0wT5KPU8VFF1A8dp6dquk6r
K16NKJwSs3h34x96gNJcwUlNZqIMlQiFNBIFjfmCQ1QrRoVSULkod5NVPn0IJOkcrPW9RUB0deTl
F3ICfX1HYjeoojs5XkU7W772lWyA4AF0QC6U2mKTG2wT6GEI5gLlBBfvMaZNW6pxUZUKfZ9IzU9V
tn5lJgi0u7lqkzsRLU7ICBIUjhetgAxjWw0nRZLN3Qp1JvQM+6TYOR4Z64kxBKIjnpYQsiqjuNmP
rikL2+gsgDc30OqPm9yuGfnHdfzl6Y9BAcjV0A3pp5hUL25DDGHxYhq1Leg2qwdseFoR5GKF141f
1KPRDjsFY/3qYj70Rs1Vdp/Ct4fJjimXxfdgpWGAOCM6yzcook5ObzIh3KfZ6xiTU9qImGJ8o15k
BwfRx2BWf1K0PNwP/V447/HrzIVW/rgrIvAUR0sOU8jM2gYzvI9p2CjDo2d1WPGUC+t7+5tCD7VI
OY4I3CEYXEcJE9CsVD/dsgFN9j8ZsBAcCofURRkVpf0/TbBY7dyWmgKK15uA0GOZSQy6lTpuLQ2R
9Ztuhp7kyz0G5lwtLXR2vo4RdHEY5oC7oY9zR2G3ZljbxPhE/KZtdIPkHI+8lgDRvzzo3JWMy0fq
CvOsFkNUyea2n2Ha1l6aJ/HEUpVb1tPc48TygbcbBeepJg6UKMERae3BjY1Wk++KxmZj6u6gdDOq
upPUN3K2/4frP3B/wygp5Q1XtmwhGhxmfDoZS/Onw1TbrI3ud7XbeLr2bYsclDEIxXqmigv+VyYG
fNHGRtH5cMwGFetgTAw+aOWBfyRRagInTQA6FeYfq40w1b8EGZMGyWIZXqGnoTKbqNcqOosQjuZ1
Yv165Ckz2A0L/NigQ54wzQF6WI2q5+TUrfTyXxj7l7nRp9kPbi9J/1S7aDdBOFasosJs02OjPnqc
uc5cOccsfKe+3l5lrFo7PcfWU2OQEWifaEGpd8AkFnlKtHGg63qiDSzHyZu1h57iRHH/1k6n6eJ2
1gA0D1csmlQhcGWgdV5diNJfrlM7GL0CC55zlbzMXzS7qJTm2rVDeBoPqgvTTnZFmFfU7BrB0dqS
wOntGOU0iDQcnkLd1rOxJ4Pnm0zDHwl/pVONyfaThItKNqF0B+NvKcGulaMb20XJJfXPaAoOlIwz
0Ve7gMxO6rBL+7BPHIyjCVDp2IwM/YLb60Hwh6YzEal+m38pBNlIEHWesqABwFp9wToGmAJREykA
Tdk7ZyuqnFitiDqyG9r4rzj6vaSzcizB1G1WaY4g/j/d1Age+LoP2WxiPZ5N8XcmamBis5U6BHcg
2l32t23C7vfzeQaBHY5YSA1Yp8kiXyKcEmQdhiK9iUjVm67dim/G4JLg4euOKzjjr7L/T0qdeKoz
11foBNGrdUBx2bxMGzMaoAiTV6eyRL/4L1zen3b6SQglq8RyZKvRu4pbbKr87gAae6hqU1tM106o
MQK+hVvagzlmfy6ULuuh2LfPvGcvQo6hRbAE+K3grw6GbZTNJhJ3avyXjxakciqANNp93EQ4sGHo
IVdBFr1iCMTB7+c7rM92+oV7gU1H3UVQZRusEpsj3Ve+JGgf5VzEmwmxIV00prD0tN1R8p8OtN0T
ngIAq1/bp7M6JVBQMcsaxaFBkrPBDbKWYY6ZF0YyGnG9cvrZMkNekNgTqc3P12qUWJOhg3YLR0WP
RmYLKaVkBx+GLG1z7UnZI4lbv34fUHO/EdcPUmWeuPnyX4VkYIgQ4i6YfIJ1ttOPZ9hJxjHX734X
6swDwSCyWUvfalSQ2RJ8uTjoyWw08ZCFH2hjXxEpyDNvz9O30A1e0zHr4Qb4rwj5OEaghxAxoPmf
KjDPzaWqfFQ5vpbj02lNlC4fBykT/v17qidSjqaPsHSREY6VC/4HJXWYWvVCvi+aqDisgLbDL96M
198gPYelcZG5BmUGp7ngDIrYXW3SeDd+GimFJvgGavF+Bcj+M9L/0GsIxWnrEm7zCKPtiogrQD8p
hRqc1KeSIGxbs4sSbR4qqpUTlp01wWhs8VKXw563TxRcTylUzFYVvLkZ8uPt0aDE0GmE1X/oR0X6
sfIOoQjPyIcez23CNBOlNDZfcuS6XK/yS4yn1/63/mI6MbN029K9bniWvRvuhpGkAbxos/nOxm1l
uhQO9RFLbAeG5PLTlMDAPoRsEFzqlUHYKX1dQmxdUX9g9b0SjIEB9Ccga8AHnDST5isRVKahNJbZ
1ZInoMOQYpUMKnTESdOmr9Kb9+zq9DkVKqqxbPRViI0xOrWyDosh1OfBbYLc94HxMVXsHqA/884t
JMaB25O3LHiyNoGFAF6OCT9bZlcnCjGEv0lic+zWKRG+PM6HqteKbCGYt8gFEx/xC1cECuftx11O
tADnaMJFJYjZYI95C0u1c9zC2JtDY+Wbp5W2c4r1bpKEIR+JIUUE3rEWgimO4sJBx1UoNAp9GQqj
JHv3GAtHHwK08lFX/KqM9Y1mHsGTAupNpowyxezgJMLFH8uyVNWKxlQ+FaiErq06OI1OvVWtoxhl
pIZnVVK4zJ4xzJYslSoAVZ00y26ODaFXQukqqxZdUxNvnZFv8m/i0nOlbsGSIAA+Rg/7HfhRjP9t
QMp+vIU6QFVnD9M0u2p2F/v1ChqZHyiSNnI5mAekF/ERKO49bmbHGlF0gXHwBr/6UXL4Nv+jXVXb
R1NHjxTWrm2qO7fYMdNf3qTqNx3/ODrLCS4nzsyaFcJKsbeKGZQ+ZfQLMm9HkpGz2XVeeLIohuFF
lBQ+7uFtpzQWQ4dGg9SrOqA8QHZBxZ5Oy0sdje9hl6VS66aTfMep75gimX1CeA/wsBV1DQfqpCG4
zmid0VhD2ZToVEvHzvKKIZCZy4TFSIWwNmDVv8523eJaZsXGUtD6Acd3Q7EKx7ezDkv1W43J4R08
h+KXUNJLf3+ziAq9G1QTg/Pk4u4PMDw4Ht/cC113cd0JA8PjuNygAkdRq20h1YfGYJF/TqmkRMhS
AH1bFwD5iHRUqa9VzmjTRWw1ocV+FJxChts4ulZM3H3oxU7Uiij+pd4g/NBXNKnqx7LY5bTH7MUP
0Jos1BlH0guwctC8sLjc3FQTQud0sv+XW32a9dcE8ILJUgLZLUa9H0jbZpLrxKtqT9I8kg8EMV/h
oSdbHtXxj8x52crF2aaNIW7EEFJq2lxh5HvOG1ZBB4FH5ue/4RLkMrfcoQqGyUvc9r79QL+RjMGC
8kLEzVRiwwsBKCSLUK53M0JiiEsnvL+6iZDUVC83kvXTlSL7yr5nY3Ni9yTHhkYHxTBLpHwO/K7w
Tpgo+/LFkrX6itJdiSjvgJ8FGny0BZ5lHOEiZE0r5Guf8kXFZMQby9WooWloqSVhulhXE7dFBQpm
OANmAZHQXhmn8Z56viC4Vs37ErTzRJdme3W2qoUvpyrCp5m9Ze2OYmPWxY5u08CE7b5HFNdnqpqh
8sfStRg32fKv9s6kZSMcN75oD8dODU67uXKCIrBfORcw/yKI31Ke6Dl/4zlb9yWCBbv1RDX+ZsQM
ErrDnyFHyw4nZ66TvPNh/SQKUCjQ1exWPJGoVlRQwwg1MwPpWeVun/vB0ldb1lyLvj2abWUrxjn1
B5oL4RPhf4dRlDdpJM3tQZ4FzhYcuSELko3B//g8DrxCMyw8p+463lwtx+ZSU87bZ1J8W+d6gWqS
5aVpU2pLAxUAmvinS9oSqEn2IzIC0txH+Wcek2n24v5mbvx8QdZV/ulkThp0yKZI9Rkg1tpD5UK3
psNCTOjM1TogTcuDaa3/Jc4e05VA8e8Nq4PEloHqCJHwK3BgAfCoMuZp1uMt7HPI5E7Zih3S2GvU
uHzvnnDuCiDJs3lgvaRmNvEzjR2ptW+u0KrVbTYQKNPP8OQBC6DcE3t2ytyR7l2jz29tRzCBdiNs
vtDtLlzxftqO85e4BkThjGY7XWjUGJIAGOoJ/l5UUIca5AyzlU7Kw24EZJPmksQWZtOw6qTFrLTI
2S7YrSUaWw36d0R38Lkr+QoczXBp1dcTEUwhIiK8OjnIdLMs3H8B79453+g1+vGLhGxKvKimjPOa
a+DDUHiaNxg40t6h6DZ+FypR4G5rZ9nzzRm4mEn4tAd7W3PZdGVRsPa911TApUuB66x3idTzvDRi
EKNnWDt+yhxARLp1a7nXEE5J/cytcIHcsXK5SlyS0N+toJN4otibb2cViQqJRdm6q7a7rg/iIX8t
BfrWrz4Uau+jRzLMatXD1acFo6FgnjpHecSeNoFTeeb6UKNP0jtllZh8o20Xe0IE17mZAvgsHtpS
L3LpHb6ryTLQm/OTmZBQT8AgLlYQ8+Ifc5XYIJoxjHoXU+zkld72hfslvQVwg1Iaem5yOP7fj3F/
HQN4E/pWXu5O499KA/5SPYjsSPjNgotFz8vMKGA8Gp4NkHhmAII/pw6Y0oFZoHl8ynsWvvYC99fK
IIUt7drZtuZQgEnur8l2TUbG4PoLxZTuxn7/GUbrNdg+YboL1IFgqH+3T6c88fKeQCfieixV/R8G
2ylXDTLX8DenUm2ZN6KjFl12jPfhwy25uksejTpu1CSrgNP5ib26W3MT4mqTrAV7RNIIkIIom7TG
ts9a3WST46EMz3V697/23t3W4Qw9gQkjTNyFblB/u6VLuUGxTLBWeG15kJqxEWemtUacYr/XmNvR
3gFXovcR/v1rLf+qx2HPDN45m6r5O5GBhwpXEWUtgwWKnnt6gZvopFHsiAhaQjN3CjcIG4M8EZ/P
VCDztdXshkuCk6k/jA72zXwovo0PyoClNUOo2o4iGMQ8cY4KOw6G9Q3Im2x3OJ2yNASsuStBh3QO
bfkMbpLPuesf1EfsZJSo5/s3wbU5yKkQAd2KKgYNHKGxYv0aKAuXZSpbAExV84ZEC+q/n59KXJJg
f+eyU6IAbKnUda61hK4VvjhUxwFQd8tJl1BA159TUuLCwX+pp+sejvnK84ESS4wzVIFWaA3DBaF0
66jmESLP+7gMdCQhbPt81sUofgdi2x8pns2LVYCahddNA/76pjK3wY7sQHYcvlb1D/pKd2/ZsTXA
Mce010Cw3E4iPxUCC9m0cPJSRtbCURA4mHL2VylrT7LbtRWVImN/AnMYI0wuEDO3dCF2BQmyw/sp
2RWP6ZUjyZmVnzDL8Ot5yVCbi7bZTh7EWEL1UnXeZHOuPHZU1yhWsO5Vsycy0wgrmS66uHhrrvin
QH21NpTRY/ukMq32qn/C4Dyj8xl0iHBHLfaGCSsGDCel+kWYHPxZ//MeJBjPHVrCdBxJVapnEqcN
BazXBv3bY/f6+OnpaAsPmayEYebQ6Noi2xE3gKt7cM9qtv+CGzn4rs+LLi9krHgBsWi5RkmxScjt
YkfpvmBcQBrJeLwipF8fxvPfdkMPC0rSctzABFYHueMZ0oi4WH0+NLTVy2CMUds+4MqQJzsnd3CY
IEp/9wJvNZOL1H4Yf/ewBqNpJm0hRXrWN8dnq0T+XDaHvbluRjZq8hmi+2mK/gB/R/taz1fYHvJC
G+wQK3A7Dvwr4yqueV9+1/rVOUBz0uGjWHzejlS26rxhC4Rp1xM0HMIrqz1anR/OiipXtR8/03Pz
vMIAzwYqeZ0NE8xYSqEVLVx5Vc7yweI8Zi3OgwNe+cp94xy6coGqfEPaXtKmq/QfgMOijVRmJbae
AUg//id1EOXyJMFhnR2Sp7pM/2K82L4hgfBt3LeaIRBsJH6B6ygWSvuylRvUVAtaxmBW9/Sgi96T
LQUvSR7ek6jgYqOlDDSthppFDn7CtRSDURwIUOJFp4nYsoNSbDCDZ37Ww+zY7faYX969AJixTsPe
hir34/iqSEixZ3O7Q1oZ1Y80vBigXeD/CyyJ8g6DE0Fs0OskxVop2oKzfRC/WJmq7z3Cibd526nG
H9GtR5qxd7gNxuMeLnbRerf9tGcNodShXPEHkXW+S2491xo1hBwkIC+RdzTagHAyGCOWjjptdEwY
v7LJoZojujIr+928cpakwNIRe/gePNrPklRqMgxp/fb2c9yk6HapKfPzGeLX3DETNGQ3hq70dBac
SoMll4NyllUjKR8XzFD+0s6wnU9UTjC/fJ061gXIV+pBXQcgp2bFUiaS+JmYOKWdcnzCQ3wVpqUd
aTEXXbSP2ld7BjeNmjJVVkTEgYsiNvJOvY6c4YEIFM2TBt4HsBgKed2v9qbNV6gh3FsutOc7A6zp
yhLNLUKN/cyD1sGQi/Dv4E/AWtG3S3ioKnnW4ojAI6UIPyQcBy8GAxVgW8ZVsoKcJwQnLvyjI51p
Lw5QkzN5p8JsVMZ3L0J3nztrCqN4liNeJMOEN/vhBa5K6O/RvGqIN1PX0tpCo75QfOh0nb8Ja88p
TBOI1P4h8hS48+RB6ozR1wVWYDADBFh5PegWERCm40iXcHtN0pQyFpBPsj8NQi3rsZlOrUf4zc9G
tEGTm66Pkwekfc5TBW2WHtqYSl8IwDXj1s80fYrZzRcyFvsbJxtx0OZD60FnHuzMpTY40Djbz1R+
BfPsm2wBxFA60zOtlBCmdAzFa7DKBbGTzD0wiPuM4xkCt0BDOBnhnNkfQnNBp1ObKYSfpAyCKdKM
cAxbiBwpUpH4Avz/WGjSUa+fw3/dj3mmy+WSjSwnk2nkd3ZJl/OYUyi5b1GAD7h/BgejG1l1HApr
O3FdM9vTDW0u+vq63pMzA6dAzttDKzH7vLSeVhR93Ay3MeIDi0a/wtulh/gEAQZN5fDKi+6eL2YW
XP2sQbMyhxamRlcNYKVh3HZ1BPZ/XLm2/T2pAU3GTm6dHUEt1e+c8oRrTUIKepHwf0q1NGhwbztR
5qtYkhpi3ZR8sja0KXSz40Zxph3zYb7G/6zSb4BfZ9MLbiS/VnfjNndFhm6ZNuJoaPKfLJcorqx8
SIdqFCW5V9eZQfUoKkJmKjRH9Ou5g1+iYlYmNAtJb8qe4u5YkeLeTqU6Qe1jm2m9OMRQwxBQFd8r
DBHseqMLOFwFgO2WMovhb4B0ITSIhPgMaq0jtyy5+jWlkMhIEc0ol3gj+o0gXD/DntKhMl7prRHe
B2y68fJ5hZM5AYYMptWMNdw2gINtO2C/G956Q3OGbPNWpumKYyk4b6Huj3TkAkN5WRLWklT0j0As
AHwz3CdDuBHAKqcDPYwru+KbxXXB2uGwZ3QkYSRkNrjamOCqYgkrT1S9LNh3aeRJ6s4QfC9vZd9r
lDJtmTFbVtMIHC/ILEd/v81+QkHxKo64l+x8qOaaGR+/ZbY/I/aw19BUg9wUMaLdArGYtQMcPXOE
aHO/Q8ifIX4u5aO/WiEt9WdPJGuYrz0x2bmQ7/LHpCdZThU547VTp+lqezjppd9kpn6LLvHQJWjT
qhz8HOSJ5MLhRZ30wozRgIMVP3MUcI9XSoJ0jQd9GrEmhkXMnUbbNmAn/SYtiC3I1MQczp4SGSPL
1QJjq3cRMlCdi8D3BHLhFiYwIBqvP25oE+JSiKG+IRxGJjFrZVM6GEORY309O7K15155jf/JeH5N
YPk0FJtNZhL1gCliYC7FPPwSoAAj/9PjtaTNx7GwBZggV5x21/T7noKe4UiPWuGBwbAs2a/LDei6
eAu01aQciGXda3H8WBgSYi/22ITMBrHJUIlEbqfAEHFB3ADgitOqcfPVgcYNmJ1V77xo38kxfJAr
4273UoQmgQMY7uBr5Wor2fcY5NTkVd0QrEc/NIGeMzeqijLkSyfClWAonlwpcph/qkSQGLumvecu
ub+nlwyuyQfD23Bkx44Bl+vn7RGILtkfWvO+UXTXYQ8MWwoy1QJgYuyiI67qpPNmMiuU4j3ZWlee
eszIy4Lfq0LcULxDYl8yQ5j8fOHtiAJdkFNYv4oUVarCUUB28b0P0qWW37iB32rAjR9+mq84n8t9
bHj9r3+S1YRczIG0cIvINE3d6jUUCSZP1jZcuWHtj7fklRM2nYFpGfDqbQQaxeQhuScfPydY9yFt
tGcaei6MIv70J6i3hOzpkNZWL6KuiadggWnL78YpfM8T7wl4y9ixjoiuietHZa+VYSbM0rbk8xCp
39PbVIVopqtCI6tnL0XfQoiww0seZQmuRXRmPAzXQA3n/gm5GpmXAgaR2NsezRFxITlOVSIH4wSv
PYKyBY5pwFUJvg6kz7b2jiP8htAvG0ChAvFna1E2zTkwSbnUXdMcNXHjNwaCW6XdzdvrVpeEBZJv
DLr33A96pzZSd1iU43pA3wCThRm6OhmxUy3/IkdJXGMnEg0w375Zn+nqe/9vb0nKMJG3Y3uySUiI
jihqHWi7TzgtnQXnKqW1Ru6MesWasrCsf3wzo/uI9oRz9xslA1MBxo84I/x1wLK94bJ8TwSu9PSa
9O1R8dP+yeI8OLockgOxIl0XfqQ3pFKSqePfJDuGwNMSQfOvEkwfTd/ft5HbtZ2r6I/l7UPt9TC1
/mZb5uP4d/cSLBatnBSs+dsvU1fdP5c3S01lAW0QGWJPBj0vm/Wfy9Fk20tQGZl7bBnW+hs1cSGs
Be4YSNhJXXGNY9trf4ST/hwT0pzgfFCT9GLeZfDFq2Xerdwcsqp/M9EzlyRFvrDkQ/9rqHWsC5/M
g06NxwC4VoGzC42C0lPRx4pW7yMuJf+60gqR57fyQ3xM8rVoTgmQF42A1TcFlOsV9t/pxBWhkWw9
6t+BARdskafWSFlvaiXXHvi51XNgldOx56PxE4hnZlDYjWaGvwpMfWpjOhrB4Pc7gP9kbLCKzR4j
93qWrLdf3OundNNutDExZNtXf64DwSD1RTots6bpL6bmRgGuLviSRpQG/uAnLFg7kdnOtfxn1E5M
y3GJBmCCURVIrrDzZvBWr9HNvjQqAYAsi3sKYScw482lUsNMUNRFc1IP922U0hPUKWzOuHl6djec
1x+G5AlbKtk89hyWlm6bpOE2q3neuthx9fi31ZNv9oDpNT35QY1OS+vVTJ80Q5Ds5OaxQ+jsvzPx
wLRTuJRVCWEq08OJIJdUsw3q1jC58/db4xHmdizndrwez0njv5RXvkKyqutFZKUOc3zXbknyJ9gE
bGTisuocHpavNENbTwId75PhrOUWuo+zIIQO70NVH2BqTn9RwjxUynGl1+gZkNOXd5iFumDwmnfe
0Abxs3zATRDRH7IaDEerdWkb6jkcB6jBlGnBUPVbaYE5Xq5e/LQCFRiD4kqu5PRo+cPzfEqKLrYE
dv+jtQ5Hop4ybm6/fl9vGIRSLu2RI+0jbzjlMpdm1cE5DUqUcCkLVKt4L+20RvE7nqBllxCqN63O
YxNGLfHIHaDjofL3KCqIlhQtmeEXtvJM9LL7YkqhLxp47u87UFBb9OmK1DWDa23Yqq/JkEXylDEW
1mV/nq73q53RycQhdz6ILq33XYOCh6J8CiRl6z64pKOigZHqH1d7sJPHF4l+vahF3NST+pxbqeB5
/kla8bx7Ergi65/cigh8eWuaXZ5D6GfoXu+/0P2uwcXB+IkY6HJWTRTD3ke6fPrz3z0NGfoGOdqY
dpoKPB4SCQ/irmj7UY9b0c6fZEd1z6gIcFHwZIdyWfmET9/y5A9/kpL2JkBl1plsrazlIYbeGVt0
ncwwvh6EdnINpksE/oByt1kgrzYPeddh9tiM1PoMYyiJlbyf2hwuOu824VAt6OHCX0ZtX+rrCIR6
jpnurd5Nc/f59b90WU3AQDtCaosJtb2lubDn7HXMNee+4ZXOFYJ2xHa0QUywcZ8/GYHCzkZ//Ddq
KkAlz0fGXZD8QqbAbkGwIKGevAWjSWH/BPfHmqafr/Zcqso2oCGSWCWObXEngSrm76n9pqW/qc0y
lZ9xsBYvX4DuJIjZ/wXExnDdt5wClwa1K+6BhhCjOPe8Nh282ePE5/0c0x3TYGPCEUEV8GU6JW8N
gROTcE61cfcUq+Tmq234y3nG7ynR1AvLM2ITV0+DMl8NMN+QU4VY4ORgGi7Zv/kfU6IisS+E+oA0
vxl3boluCSwrfOjNKqJsEX9HJBzT6twNBsJGcydKl7lF8FoKQG8Aee7Oryg3O3dI/NPjG0C4z25Z
LKUCJ0aS0/+IH9dBm4JqM37IPZTwjLdaQ33NtMwbyUATqADlgRXhCKZ8XWGiVe/gBJ5A3ZuEF18C
jJomsvUXzblSNShfrIcrXq+JtdInXwQVBfxj+Wh2C4FSN7BZ8dCx59pv36ttwCIySYZESN3dNz+I
rkueHLekWRSNQPaWYQ3usZ4HPK+O1ZiithuXnq0hj0Pev7DC/EoS5ApH9VQJ6ZlwStYAhMTqSIxk
eLFxDKLtRBqJk459F0H1GQzuJ4PZ65qPeKhomPFWPD/5yrXTTc8aQ1zWnZPApNmeLUWYFWhKD35H
1ExlCdmUlNIN7Eh2RmrymuK9Bw+AQ9/RlJZJ/7wXVYhfN6LZDsKV0vwre5HtJMwVILspdFK8FrsW
5l9MtLhryOy8RJVsD582jcS2Yl8n6cIXr0QmzQQyuXDuT08cIEWEaYQSYO5DNpgDQ3B/2Y0tRQjQ
eUt3U1jrAxvyYetNLJzLbMHwHU+Te14pHs5AEE3UgI1BUaeil3q5SoSSNdlzqbH6BZb2OpavgeEr
FrH4n/dFstgft/pyZjpRMjbwKCkghB8/KWKXHTnUhlpP5Ai4WbHLKGKDYcu2XNgDVqhudYtOQDAh
rcvQS/ZbQip4dqkG5X85KkoVlHFbX1Y7GFflSHFyB36cMGEtxfiGStWsF/PWaWkcD70ET7GwQX0z
K9KoonOzw0jaM8TfEVlGRUah1NFOi1hAM2v0biJfVUdaqmEv6FWsD2nt+9dhc1OCQB8vHWkOotd4
agyo7OFKH9cPvquNCFr5y2MWrfVepEH3SE3swD6X+cpPl+HkEru9kQ2Wr7FcTPqu2p84mjckmaNu
7qnZTFKR7vXO5oOBrbs+LZN/fNhtxu2+JVYZnrG1hdUcmRp8zTVIDdYM5Fi3BBNAmqT/sbWragEV
Qw6B68b7UB7J8IL/KEsUBArItftAe+Z8duA9rYs1xGBUUaaHG4WCmZ7q35H5BPsPaUb5fFKilAkL
eANtC9OYglxDI2j+GNDrqQMtZaVRaHa+Btmu/TTZCaPxtwQ/JShn4N+hD09hOvAmYNpZS7hoGjAG
wMYR9GS3ojJHwiIY8jaAn/L04M68Ve3wubTkpX/oxqAuX4t9M8STT2tMyP2upJbISj8YsPbyqNKg
79sSktIdkB8MDfb9buD6qyARUkVROu6hD4JEFZKEV0pAyhdBhWoxHuXqZDPfXJHYG9bGR2wJL7UI
XbxxtclImTZNV+90wSgFMsbnqf0y+u9GcLWS8bVsUPZplE9y7c3OWWxOiJdd2Z6114eQsZm+Uje4
3KxUuN7agwsyU9p0CzDZdp42KBsn0IPYdlnxVE3cQJMKudTYlw1zwIr7OJCdPtk+NUmF1Hhfu890
PqYQQj9mcrsikPNb4uCJ3qEfYZP868YdmqxI+NI+xJz0heA6uMkurplrkuu5PDz4v7+rVl0Assk7
VUiXHRrj5svnwEqppHva8tCwKh4riHbCxS/9bAPvRleiQearsGRVD5HOmvOa+H4clHw0xGHqp3RC
m5hbR2k8LyrWkI16Q0i26ttMjda/g7APN6f1S/x+yhHb0KyvXcIhhojV1F1XYcErNJEVr0vEffHL
xJLAmEDqJ2p05EzffigYzL4af6xPF0C7yd3eOx91oK+v6Tsv5P/SS9gXRumvgTKK7Ag3x3g+6bq7
B+XRxCcwxlabtBvGinHDRsCwpu4fcZcjToBQt7fxmui5NB9UkGHeOmwctC0umk+FbuxeoXqg+zUZ
uavpdR0/2SozQI5ZloZ5HOvIivcI0zmyybpJjDDz//8nmjdQ3ETzL6TV+BHsZDlMHNB76slgbl+L
b+cWLYV+R7bsPGDklMn1ZrloaYnddh0Hg/wSfFxC4OIKkdFVVCB46IywG4yoDcqrE3CHb8YJag1t
H13My/tBI1CHSMzYDB1LnKpt/8Izn1edwInWtAKq7Sc/GMM/zf0QStP36D73Py5YaLUpRGS1YU97
8MpX873G24mP78jHHtI8K2zq/fzebLcN3vseISe/w4Bh6lP7740lvjAjUr4KYHfCFhqxCFnCsluu
Zo5AQPGgrHUcRKN/Wb3uRPdHn0HPSe6zxfw1P6+hEc8XSzaL8ZQ3d/GsxLTuNW11YAvMBZtRlAIQ
JN+fTZB9GlvorYhmoaY69aZ4OMhN9WeXud7NZqKJA3jptOL61flaATpgC9Y6JkOLO/v68ojLKY+/
VhVy9Lt22mHFvrYLVt6KeUAAez9HfnsIoUQTg9V0UyaiCbk/AwdAV45Fl3E9OkTNdwyyN8ifWr0t
fAbWmvMZl/yoWcJgnppAjQSvkE4SjYgzZsSqjsTNNybZqacdvEqbptJT4mpitkditmIjE0o62ywD
kqOq3Uew/T49bCuhz4Haj6PHT8v819l/YdncQ/09tWIAuN0wXhWhf/+8Q8R+XaV+8QeRjM/04i+V
BK1OKTIL2HWXzLWNW5GsvcRSATe0fzcHDV9JGtUNcfTwF+JDH7iddPmAsG01bnQbSwxuerM03Yid
ZvIldf5gk1zgbw7B1NO13cFbq8+LlDyu5ieKWalSewaH00J+pgXUFaYdQrXfsoovNnzrIw6soJiZ
OndVVPASYoHFcaievk9EEm16A9VUSaDFth2PSH5ME8aHi829zTlMSONPqpzkyDk8IPF/2IohhuZP
hlYHihZASo0vpeYEIXbPjxqaTcGJf8YYRsCjZ9rD3mvmGg3QxgFmaYnfPCT24+/hREi9nr6W/Yz3
j4Ayvpt3DdCXJ+IG5FqtRQNt9DAMpxoTlstpV3Q3ccqd9TaWEST6/PvrJmnwEBqwXFL8FSFA/JTB
z5wzR9ArRu6f1wSv0eNsiywvYiXPF7A7a8dbDTuBaHP1l3m5usqCmWSlcHaOUnbQlQQQflSQGmM9
I2jCo4wwxzIB8Ov/WGj3b5G8DkAWND26Ok7Ze49ObxafGDviGDlrW5ubiMDaRw3Te++kFSdvr435
EHY6sGqnD/sG6JPEowiqLpZJnlSYc7RUnZ0iQE/PCVc0Z590jBMdUEM8y7gadU2wsQ7Ca+6oM1dm
qfk1+rmMQRblaOKhOoQPN6IqPArWHv3LPr/HYQ6xrK4PAyv33KDC9edXQk2TlqsLjL2NczqIZ3rv
x6UrQcahXFzuAHo1cMtZuUJ+qpN89p4zBNsFrgMqGfEi+JFLIwHGzL1wQllO5GYkC1q49LYrY6N8
GXjSzGdIOmqoI1OvDjBMA3NtSu+nXvVMFvxUNJLMZZtyxHR399Ld0s4Lg3E8blb2hZ0o6PDdYYRq
pz3Y2qLRnl3C1wx8hf1g3wRDUBveH8QRzVjo6K18VAJ7WQp0UEaqUjFxr0oLabVPUajAyreFD7O6
/YVb6Hdj258mvEj/9E2LO5LFjOrda4KMKbCnhquionnk5NOWGxh5ALwRLMkARyp/j7+Wt+hKkLp+
6yZq7eh9r9LNGywPFfhqb2AbhY/Nbk+gDYW5FD+ssf+pKUYtu71zbCaqOhl+iOPtYBWJ8QHMbB7r
XnU9DZVwC3xqm4zHLU42z0gmUn5m0cbhoWeNCCCcP8vthwzTs7y8t1HWGSMhj4crrxJBWBix2hzT
LK381m0E3uxbohC1bk1j7l8z4Xi1PcK0qIWmCOFrvXvIP2lOz+zeSdPtT/jeA+H5J0DKqhA8QzjD
EOBcvu8PY6yB+g2uZ9F/6PSu+xTKv7Dt4BZWctUkvHUjMm2jSEmh2udOI5v5GdJFiEKjy9eBw7/2
EZAFGsDmD4sBRKrXmhWt/T3VdcJSIaMnaEQFMKH5i9LUTyAPzeNo2CM8fGa58RhCF7KX/ANRNqdQ
jO4uEkwSNDZHXpG145C8n/ugfeg4H2I1tn1shKwgpsd38qAYwyHHKI/ztD3AktSl9oC276JbWDvp
LL/Cw96r1t2I6B7jGlafRamp0/+zZwLxGfzl0X8g87lt2QvXAin3n9qc4i5TYTglzYtditD8kpcB
IqxzMgfLI+DRlt953q4WJcPO8xJVgIdj6OheBDf67r8j5MLaQN3HnU5NlCO0j+01vdyGTrDcjJ3q
q/JiV3ib5koffGapvm2ngYoEvVcZiVLqZ58YynWYxTZq/VUq/NwePbwrPvMlBBk9ODnWg041I/VG
0M30jMsaBYlKOjVM5QbdzDCq36OlgF+rC5AJ6Y/hLOROhypIDrLiJNm72n8yfi06tLikA6SCwCBj
QE11tRShHSoeSnTkTDq65xlGheAoFgFo5hlIVoNpQLVNCsHS5CnuvAUfV4l73EfmNZpMNpwDzd9Y
RecauLQEz3F1gXwtg2fg6QTlCNvm3unvFgKzd8iS7sdMCZyjqhHe0vV117XrHi6Jp7BUYs4RycoM
uWKkY83zP5QNoK6BX1VKLD15d+IISpY4kS+eMPlLPZvDGgZXzX+1LfbJsXIH4krGu96GVmlYET9q
ratHjgrHg3jI5qokJ1+kdxA1DJop0taYdBqGJbU4EH/hb/XvbJQeMr5spOAON1qDB+aq/F6yUZZO
vvkMOkka+J7c4nibQ9WMdGj2O7PLxuoiRWeJAOgonfoZJ8pfErQgbC2QphshydzMq0cX18Cw2ixr
iXHINo+5AMkZk9Bje4gXxzNlpuFNweW/7wj++jiW6yqbO4v+AZcIlEp+7g9pHet0xpSTl/AG2pA+
baR/zsNZNfGodTklMH4xn8mWD3LpufBf745Rqf7pI3cB2efghCmvSsgAJ7FY851rYVaVpo09a2OT
va1QNRGcsNxuwWoZgZEqSCFiIpt9JI+EX2eg61iX3TCpVf2bAv6/vr92+tV1os5MuvwMTZ0qE95q
E3mBYV5seq1xS2IpVpo9lNQ3Ilyr1xv4XbT9eYWqrxjEDN4PxT/RuqPNRLQxm/zRlZr+0dOuYyO6
T/m4YK/T55NxEyUc8n+U6KbvH8Ckt75gifcubSsWeXODTWNIVK/auzZHSrmI15pbTUoTbM3SB1SG
py5v4LkKDj66a0p0qbBxwBINe4h4lkDAG7gQsaaTwPL1vf8sYI1OgWbTdY6FBDN1n3Mm3fIa6M/H
KHhdjnca4DozG0CX41TuUNxWCDMDsPd5BDvbkL2SahP9p7lje5yLafLcxWSyl39yqHtWsHMVVnPP
7yTCYmNIdOTSQXJSgd9uqo2mSBd6yLu5z/IX5X2GzNrrfHtjXPFcXxF8MaRsosFhx8lihROOW8G/
l80SLWQZQVbNEPmxxEwS/gUh0Nu/InXCxWZKnJPYqaIUl74Sgdu4gmlCVh/knVTp4BYD8J+5gtoQ
vWjz9z84MkoTmY262c0lxF48mieJcgmM04WsC+YfEomgztiuwrfqvs2C1lvqGrdfVySangHZ3wd8
txc07c16ppAFDUQJfLKauoAQu9tZ/2mX5qRFbrwH7pL8AmnnxKJGhoA1srBAgiEL46CZJrz1Lmvx
wQz6dkxY17LPzJB3Jcd0K2qBecUKh4rqE0b9Cog9T4cjgiKVhnVJhSZsvScV0EWb5t7lAGyOWKoq
+1Rk/4T7wjAmiAyr/bxyuFDK5M79dEldnqpys0tSuriaK7+wg/PFkh/2OY8xxfj8lEBK7jn5g3ro
KOK15yRDlGQMkxLUrmw3P9UTJxCJH4aEuhelz1cCDLmXniYXnLHV7BQCkcgcDfO+h/yDHHvvq9hZ
QI2Oqgqs6MJRmKEprBUxZVmMT6wfuHWiFkkFV2G0NdTH/dxdTetq+e65UR/L5deQdenzLqBcuWLh
TtcAfddz02M8f4cQVT27HxegojKPRVBgfbZeAfq0sFp7+D20fO5onqKDP9iDhwhc32wMVaSNSKiV
+caWX+w4asjwKuAtKIfPKnwwzYbFWHzqPPRzATxd2PwJocLqj4CHGVu4rwoxacwwGHN//S+GkJnF
uWLYD7eYm+tTTslvjMMXN80VztIwcgPf7mb19xdpIpeu5zULDXyM8bnGO5RAwM7Lux391Z+pvITs
w7xmKFCDl9QGszEgdOsAJ3MTTy0XRbZ27ikfz9TipTWOChkSgF5otaemBu8XtImo5CpAhlkOQ0iH
7vDUEGPfYPpoTUlLd8vCAyigULo3uF/42o+IVoALwtzsgSiKpN31rp0OTJSPCkvL9fzFk6XqK+Qt
m+u17Shf1SO1qtx+BfMahUdKldQDSr1HS2+m0BTQYuQLN5vYzg6B4iRKHTsS0MRwUj8TgOgLAYx8
r/rLUl5GLpAoBtRhZRZKQDKMk2HeaahW+g0kCyzxgLpj1t6Pgruem9ydKW3vWePO2MP/XUUkoKy5
YGIvqjKZTu/bs6XBhWBOGT5Co13aNMSGr0/TEH+A8t/xlNgWp+v5N9bdevrQMXazu8e0qVB9HKdn
NzhDRmQyTNKwW16ouAd/F8z/s2XoIuJ/JyozauP5JD0vUs3Fi9CjtMA0avC+SxiEfpB/D5Xl07pu
/CS8Uut81PV/AI8Y6bUeWQf0gRZcC75UpyxWC0CtJzq95hSFCWasXSWKH+/lxIyubrY7bjWaSaxk
i4N3gnKfwdk1xzqKO+fU2733PjjKwR9tFpjLUIJlbOghrS5ZkddQU+Sxlg2Y/2FqsWUm6bPo9psw
mxFjER2lUZIcnFEzPrlv+lyJWnTEHchRnhRVWGlLu+1T1XzE5WdLbEq41gDzNvy7LApl6PmHhKXR
D1GMk7v5chtKQePRly3GmdKrH0JY9T0WePB8gIWOw6dl512F2emAkOYxMganq1YRTH+VQOh7xRKR
88BfVfhzxvyTpdazl+1cSXRZwnORvwYr7uvr4qpnZBrEjGY6nGNSQ9N91CmTgSqBG0Z4ie1eEFS5
WRoQpAipwUfDzOfDnXBvb5JY3CwbiLStrd+tlGU6apQmRNXbknXXpzQMS0dhNBLZ7ESmNKLWYeDM
vDUQhAHzemFhgbyVytzHBEBOgT0zDML2jPOST66SxAK2/3wZD/txXgunonT55YxxSLpPjsYUQ1j4
O/M372J1RMLrBRa++Iqfm3VZdHH/3u7SJDOTbOaFPHLPLHye8ZjDjfa0ypYK0lRvJQfEPs/mtKKx
1nwJe5v27kiVdVPZMRRhziQxx8WrqfWXCTL66q5I07R8ozFWhijrATpdRccC9C5uObGOaq1oxMok
vq8cA64G421x6yACaIrR1/z7ntdgEUItu9CZCeXtEppZSI1WgZ/QIJ3eGkeTht1Cw1QfaK85FvDS
yozVf5Cpvv35mMINNE+uNWgnKr0g9hDJVH4dkZkIYCXMEsnObafxHCKJwJTnMBigRhvQbbxNAOdG
uOrVOAGZiWsOtoykLqGMTmk000NACBOhaBLBXNxq+VXuTwSrlGMh5KPsUs29J/3vbIWT00YgRd/s
GCZIfKKatB9dTeIArsnz1v/87o7PDMzl4GS7hgyWLnu+wyn4Da0EJ3syj2btFSGyXucF4hdugqPu
RBLdjcftPCdiRG5M0KEjDZN6Qs3XMxfIDksRvRozQX9kVnVTPmhKHOem7WW+j/ZhBY0erGnOV/ac
QXgWKvSzhnmoM5WNp21FLMldS7gJESwHPfgn3WoANwiTwcQmP5IAAtqPaIimZoAnFHtR1PyYPPEF
a8UbahFLDw6r+6vH46mmwY55vdWnhmKEaPqkHOQLBgKYkStPbTBV3EdFWPv56mP595+vXYqK7ZrS
copxUhMtTY988+SNf0Njv4fnRaJ5AFHyn7aM+pfCD3U2eRHND1fK8J8NYaPd7vAyyzVN7uCiYxkH
Oc0LXYBwKpq2XjXjE5tVPxcdI91X3+SQBcyvN0562xuvJ9v2ThDMr2ZoylJZRXnKgrrUTFz8yr+Y
NTSerEHmznPo9x9krgw4qg7/PUtfZ91bq5op8HSAXm28hy+YPdGq+14Puvx2+OozBClQnTmjLBkT
6gjnFELsgAxOudHOSYwYDYrCi0r0M+vtDa5dHK1m6AdBt1FPl0bfeeZDUOcFqcd78/cPjOPqeTJK
uCv/HOtvUmuLcudXcDd4iUmUH7zY48breMn2dwRHIcAPKpUoHsyDl5h97U2WNsQPu6Lo+nQQ7eLT
HzQxvnt32Gl6mwZW3aTraH97TYvidfl0xfW+HO6a250OcabXWmQO6YSCCybEAJPPOauZ+6/Dw+Jh
JqIzCyvJUO6VTaacJBHXN6K/EOEwNo1Zoa5ZqqCh2434IyUfrt7NewMz8sMjLST+YuN/wvOSQIFF
p4dDWkBIJjZJdiL0tY2AHtHVr+L0v9QyUSrdIzX6qVCvQArphNiPq7yVb40kTq47YKgmuC7BnaMZ
W0iwka+7zKGwbqxSuN79wUrcymrB2mNstfKWHfSYwKQGlSxVSqKX3ROyhrCrxdDjlaYJCnv8T6rE
ytmxMOxCj4g1INgc9/0WlkJR839+/18A33ktWv1qkRhbNzShrwt82WKrkdQg3nGZu75m2n+J4ori
xpD5vSb2a4U5waZCkUvRxoCWTu0zfZSe7nzFBnK9cV+ewFVBO9/ymm9wLHdAB1eY9go0jJexxt0f
6b7vtR+1LGP2mC3zoskzmu0T9BL5TT4z9rpqpTu/HonTS5IAa3gTCJpcvO8qdGpuCGWuMa+EPCiW
x+ZKfsg+3USa/uWFLzW9YRfrLt7RC+uN7OAEv8qA7f+C8ay6NQZKqmULOYP/gI7s8d18kojTh8ei
NRd8pL0mUMjcLtfu1G5HTZtllB9k5XmPGhZFR1E55FnYxC7KaZ/q1CKUll2XjNySCbSBE9c2SR5U
I0w/fJUUiYRNuwDDYINK6ram4EGr6P0Dr/eUwblXk90egYusswTyQQOgcdnBOIXo2rWuaX3x6xZ4
Rhbiicmv43tnS/x1NpBb8QyTApa9ewKjUaKE3QyODEdR6NJqRikIDm0PRlbODQiTob15an9oPXog
RcMyJXaPYI+3q2aexLqn90/BawCDpaGzf4sTDpwzKTfA1/HMojkFNag6N6u9ijn4hFFXO4rAUV6S
OQ4U23cdzLB99YJIuqXMmwAi783/C8IXZyaDk2JstIhEpV7d6is9yD1lByPjX2GCrx9ySCzv17Wa
pjXZ1wQmsb/F6DATz4EdgTR22puUY9j7uvsni1vQ0aCzBeYCCGhMx1f5YOlbsMWOPvAY0mZfQnbe
eIjrSye74o5JqtsoEi7JbdXKFid2buxEVwB7N7LHGYtFwH7Z4N1tYh+CvOIHAMnv23sRLdtVuAQe
JgdbfRzFsJ4IXoOhISZpUSiUbTTidPsYHZfbo2v7X7GAJg3mRUAbSZo471aszzbQs4/9NMxCeypt
oSTyNrA7JZKOuzeqm0eNwJBQOFekBdAUdrhDdJN3Ov6sPrzw6xF/pkiWrpZewJCBUi3gDC73lTrs
xlKJd8HNKBrFXqy3sJ3B1cJK/iQQs3A1oFoTTl1YCN8RePeJI6JI/TVQbaze3JKhVwGoYcdNWaDl
+fdYx65z8+3qRnJWEN5A/0C7Creue09SJ7nbjWJvMcvPAxjXgg6k0nOCLI4Q3vxFA0dXhXygEWqm
y5sJMeX0lkI/03SrIhWj4ph1fl39cB/IVZG0JdwPYhoo0m4DTpEGT8WPi0sGB1hyzO35z363H8EB
w0iLoabO1DDPGUmr+fIWdNxiXaynAhoZGR3/5VYRDeKOY1So6ex2dW0VTD6/6cfv/BwkvGVvY7jx
ZYE/pEWPrcGkActtUF3hWjVzOftDAd0DPhnebUFEP+diYqv8v4qfbagVs6kwO15j0MOZ+lVesadR
L8eONOvw2CSDX5q4cUyItaMolSAgrzLdMubR8VRZDntgFxEaJnbOV+ub2jUIOyXxd35vpTWeu6R8
61pZn37tNMgWGkDmwSKpr+k1NWysyC5pkQMgU2M2+BOGSBOtc2kXD0ZEcXRwJ4WMLG9s3mAlDJ4O
Es+0uc9FoqMMZlCuU06BTcpRG3iBH4rO7x2E2Afi4f6EEdBbnKZFZ4o9I25h4EIue90NBPHviX5g
eNoyzMBE9p/57jRY80qXTKxtQfTFa7H6smmwCHA49ZYb0lQkpzkna2p1lV/dCahYJLxEUQ0o9d+r
H8bt06PQwr1DLvh9p2Aw+sNQfe4cAZSQUtYsBRKPzmVRDOQ3fooWMfmkMdldhVUkgLH8fjFOMAOP
CAevlEEidUtge3Kbvv4XG5tS+NjD3d7OMHWV8HA8YdSdjGjLyfZVIuo9CLa8yHirajRKFbk1hFXe
GR0jFWAIEdrlypfa1fGsBoRNZB5zXI00GTrz17AFYoYFqBnGnu09qsWfkjoLRrZZEhIvYSWapG5U
7oXBw1WNFgZUTDh+m2ivkDHjRqSZgPO94b/OV1aEV5cmYAi1V4Xl5KG6ukUuS7WYBKe2MpJhZU1u
/OGzELciBWEM5Dc6RzQI3j4Wne8o58vVGppvPOJDEndT/XhozrfjrHvYh+i+VELJjlRGI8VmtGpR
zQWoHVr90KQuuno+ohPuq1ZZ9lFb/mZI3SuC/bLrIY+b44g6tMcDB9wHRSMxl8Fhl2WcBSes83lm
kZCBL98pEpmdwrozx3k2npm9GE/LW0pyKidqm/Onm+dsKVQZAhz2HD4uTsyK/Gy/catEL14fAr6C
56Pg5uRRatYoKldUlUEJ3fbVJ5AOt5Rr9FJElI1e8DFl5dZmeOxQGPuPE+AU4OVzXu0iufGb2THV
03SYNvMR2IHNCchueWHgKWxFQfsE+RsbvhyVxWFNksuZpJO3FTnAiwxOFN9oKJzj9rfmCnfCFJtr
8kx4G4rnisxrx64cTQ/7Hga+6Qghmg/8ryLyyQveJwtMCL+ctWXYTnrC1IcFjDqPFYAvL44042zR
Tm+FSVJGJLab5x04MnlmvQ/ztN7e/W8kn3ykShUsm5e6Wiw8lsK9Syd1RaBkimbNXBxCuI1sfRD7
+Eu0f2uswfhQfsZWRXF3gKcS4XocfVQNVTOyeVL+GI18NAF/qYqLpwlOoLjQ9F9a66/ptNaRfbOc
LpvD/Gq/ARE17HMdeHPvushTrlpLXzVh0l5IkbiGVFt3JhMWveAYW79nJzKacG/jLKMQtmsU/U+T
9wGKLC0y3HV35XyiRYr3pKFRCsNE1HQRzcHZAzPAWg2XGcYkw6hIFKFUIBBIxuT/9KX397ohWYo6
L4DweyCRI8wOkU0+gaB8/Tr+qMo6sfRTPcFwJMJ9HD9In+h374kWfIhnBaUWTZ1X8N2oAbQ/LAPe
9lrJCFClMbCE/6hPHpADL9gS27IluWyXx7UxiyvCc0PmXj77PacXafkaId6koUUjPHtywNxPBxUM
cWsvuycUUkLWa2ps6VoLTOVmwQE+vfrhTcnqbbRTxt/VaxDu8AqpfM3mHLnncWZUHjqrDzh165c8
lbvTiua4CXi/4aXOd8aBQ7XYAgcmfq7xbDupR0WwFN8eXAHOwLF6aPq12y5yh8NRuUb9sMTP4xGF
onZE5+oISTTQFMXI3poyPSggrvXVLqRJDsuqvyuioEALpExoNTQ6A5y8Jp/YQF7tfkdEB1OiOXmK
tw8NMQcNRi78tCf6z3RO9QEZgQhjkycl32P4wxaBDheHYHEye6Miqnkl2Z3ELI+Ug/QUTcB8VgHa
rxTz7su02Bi7Aalq2V5keggNR7IHOsRe/6N2E9BJkSC6FoIMEyZJNKFLl/40Cp4eEZ03N+FX47Gw
00+/SoMEras4wGpCyprSmqIJhqd24B+b85YgMHl8hV/McZgOKKkSifN53hDYZLRWbdoAkKO8NHkN
ESyWfOIpm+DIvItGegZDibkJHoMPwxcwqRlvXZ0OVKrPFGKdwCJdk/b9uR/laaQuf7oni2LprXsO
OGi5GNYDJavBBsqgD0cnPk98kTNbSrS564zVSDh/1u2VtX0agexyxXfZdSOiRYsyBbROiKSMFNXP
ptb0dyfaYnOUj0nqyTKTsdkJrk3eS4YwfkMGqzhk8CExu7a+gIzMBH5eNHkdQlIMBYMuwstjB4+A
wHXnscKpOUHbaDMCKCwoaIPJwilgeFBlHdnv+4DGUEMjscQjB5IYBjYFGLYkks/4t2jS5aCd4rCH
SlrSOMnAYy3ob97CnO6qtiBNwgHimYIchx/9Vjt/AqSIHmjFj8lYExWpL57+4AqCJ9Wrq4AFDXcP
IZ4c4FsVuFsGucsjMANtYo/Ca2B/qFdElfJraS0XUChykFoMjxdgGZomVKabUFaxCPh6yZibud1D
gQzmxxbsCqNt+eMW2kQbipDopSjmAjr2pgp0wFkDO1DhEGeNv5+gCu/ky3sWHPFSDtJD+Y+8KXkK
NjuVKe3qPTQknE8PukqOA/kVy9fRD+gvKJN0faBxHpedCCb0ZsLgfVXIuE9EyjiSzH9Oa5XiPeHb
T8HxSZlAffbWzPOmjGPSLNfv3ZaVH1CgpQKBGF1jmO54W9DvX42dIbd+fvK2BFbJf6S1lBCmxmqH
us6F2bNMueYnhJhmJ05eDwGIkpjlFdF/Q+l19GreG3oJbi0HeBB4CQDhoVRbHiRbuATPRShvNgnB
hy9nVbB9/WnZKlNfN3oPr4P3TkJiYwBFWS48KWvCjKmbU7lSJJmCZO8ap+wauz/8PrWAcKdOZnqq
oJr0OY4ybxBn0XxDRNtBRSqS7Io/u10hQOZHIJvNXVXUO7ZbabAimXmOPZEsVojt428a7du1G6PH
/nOQuVhF3Zn9DiDq4F4uM/DQw6M8UdduVWxVXXKiCfcUdhP8fgVvNqoO/dv1d+DRHzcpGJhKpig/
h/RpRniw18AbzGl4+FiPNyyUbLRlogkJmuzhp5rrnX1rfDKP2hBiK2BXF9UyjnQ0V9sEJ/VtIR/C
bYZjf7HaH2FppBKa5xU0SavmT9GmDAXuB4bMIu9yY569tcYoMku0Y/4gktlQrDVE8vojP2rpL3nV
NxaTPWNvoBoNBm+VJ2WA+F/Lc+FnEShzBLrQgZ7yhx7HS7XtkyyB6bjczLrWNSNrLXvSLpWBq0FL
72nTTBLmPCGZQzCOdl2QIgCq4/MvJMx6kvpCnaaxtIHK3h1pZl8wTKrkZ31bBREyV54t8Iu5X9Ac
SObltLeAW0YNZBsE3z05PMJ9yX8KMWMpIBkX1b1zXd0xEPVDz4gG8DyqyA4ejwVR8ZQY2JRfD49v
9q7F6yo0MCSiqhM8TnhNXp5FqRJFlIaPrKo5hoxRetrX72le6xc/55ns2jnxstwtb5GUeUl+WVOV
saPeNg7e+MfxFi9RElk7cwd0X5ATy2vW2HKvbmNcD0VViyK9wgUfE5DyMgjcd/T4CaMTIYuG33EM
T5JpZpQtcQ3SEkwdrCX40km8iXzpiywaV107t3m4yct+t3v6EpLA1HF62O/KiO5WPXlujHD8ugtJ
SnusvpzEHy1xBef3Ovyd1CWD9kM4z09h6S0eD+MEN7Gv2eLa6tWxM3qD4nwAEugPHHdnahDo2ARc
1giGvi73vB5uhmjUAVM9Zs4T5mjrtediUZaJP56ZnV0lLYOPFD2ihuNrbgNYR9e3bALP2gw7ZG2X
HRtQkBKYw8NyQu7fYfbA1BvoqD24r4qvf0lJToyTK/R+PGgfK+FG/+2NZHwFiIPAiQlgq/RF8zEU
DeSk4W21oNQiabRXl2Fqv3NO+pNtWwITVk5UIN8gh/sKIo1sB4ZjphsvE6yD+rgmjmHd6UrCgEOT
tma+LH3N7Xqcob4RNoKH6rSVYzn68o0bSWeEQdcvCURto0WAzm0CubaSt2iUqgeEIFXFAifA4A6C
JaGPKYTcTddabxG60DuggP3/YN2Ic2dytWfFk+cK9efPeMeHAdZ1Lwl0/qblpYsBcvQsGZ4KUDNv
FKgz5BUWnMxoJNswa4jgJzrgxtW8/Pm2cHI2N3ExMKIRre9QqGXrtzHEtNzx5WkLwCKfRD5KKTLK
uTGm7QUfXFfUR6tIBQUI5wHIaLnq4Msja4AAz10mSVVUWhnw21Uzp6F1f7IaZEUbfzi2oWa4mAt+
UNU8kWzizkp1cvErtXy4t93jIRuxNj2MY6DFhQPvdelZR2S7GYZ/ktCK0hDHFQ4CheephtotMLQ3
nzaNh8SeEaIrdkxPbgAw5F2NOu/OZnqlIRsWgv1C5Vt+miG5APVODqOPk0Fsbd1woJ4UdmOED92x
TcOT0COc3wp/cyA3WqodXzxrOMd2Q+S/T+4KLCV0HcaNsS6xH9fu+zOEeif+6eBeiAIrr3PnS+Q7
zcAhihqJ4jL7P0RRqbdHRnR7wctO0rAgJnG0Zi0mI5WYjvtPzjUpmuiZaoF8IH+npjNCGeZaDPEh
wczxylGaJVQinWaRRFMJn4bBX8DrqxrqydOBY3WtziJw48WxpXltM/gNSgi1MP4FTQusynulpqBB
1s5+LAtej2/CEM5tQbFpxMJHKPqhbY2YG4F6PWG0SmPeAjk7+h4UyGKGrgVVHIV4zCrHV6DIKs7u
9TvMWUOjtHh5KcrWW8ItRHGNxrurEEsUmSdQHK4mgRVWUe2Nvr6mjpwEfQuW5Jx1DdCdebzSDpru
LZ3oIlYfI8bv4Hkqy7/KFxtH4wjqKMs4l13jfD4jwtIOS5yo9oR9xzkmlLvSE0bGb/MvGHU00uwc
iCNYuuWkPOE2v/plYSPxdAUlulho+Qjd/uZVP8AKDbG4k6C2REhihGh+eCFEUHDZAfZa+k/Cg22o
wSOCSi4dRj/4QKqIOa0p3Ip1zWKQY6j2mFWMSfqWU4eQ76CfnOCG0ee93E9QIXBJjqiwCHWd5F92
XzrnccnanHGVBFVgJYRAMSgPWV+tIWygA+p7W975ibUTM8IQYy7M4jDo/gQYrHD2GHIpSKF8RFvm
qzi3BC4pVYD9w6kH9+6BVRbDqoXVRTFt8CxiK4Vd7mcuj4poQExojxH8GoWj8SwQv7WpH0YcNP41
9gbsaQ9c5sYeh19PiQV5DXAwaM9AoxF+v+7DeHBemJnHsTPF5yNydCgKms44JB1TWY8Oy6XnuI0Z
0Z0Ygmwgz7NccyI9DFBdpXUeqmmIAwDavtDJZ4uwZc3Zr5RudbwYcVHGlA7ncCvQnitYZISWI8N9
4nZkr5mOvxgIK3K4ztU6U46X0hfz/G4PnVxuZxipM6GXP+La37UXXFJVY+P3G44Xgw4uAc1/OJiI
WQlpQXfotgT/fj3noLLtvXlQG7afDUYbj4tCK4+ZDG5hqDNqsfhNQIcZf5EyfYJPlmW8LH5iVqE8
wLjsQ2FISWT/k14Y+5QpOC0aAgZi+C9wMUx6Kpa8+ynulAlPEtLc8Vb0DQTVSk+8iqnFyEnq1Smo
bZltM29bMg0Ockb8kJGzW2U1wi9nTcR3wRKORIhrGQ4pDtxEc7F3ZCEUGe5lAyki/wL9VB7bKJsj
JAX8ti/cP0oh+5UB/2e3ZY8RbOPaGfbDcZ5eCMzmjaSk8weHDz5/VYcvYV14You79s5Nngt2Qdpx
eGdJ8BCrXJRKrCFqKez0S/cyjxZ0JGMfUfc4/qM21JHzjUAgQJdkBe/XT+7tYFpCeO8L/mjFv0/j
sQ1oxSWGZar56gTxU1o9Sx4nSiAWDCb8ElInAgZs6u0ELZxUYdkxWALHG7pIjK++VHegJuJ0oyKV
9akGUcfPYaFz3SNcszFUWyHWWYU6oNQXO8w4hgUWODhqpkmJJeEH0Q7BfEaYAR0KosahciWLXQ5K
I3bP1igK5r1wBpHfSYPlDJxx5pThWefryDOykwgNfo/fcX2IeuKL7XvEbdSxhhfMO8bzMhLwYxy1
mDx2yvPtoHitNmBKw4CQOHGRUmRNzIAy8vlTPHvXLN1nTxNV3q5d2AvKV62LSyfAbU3GdLmFe8mJ
R9N5HKDtSdJafkH4F0WeWKfmPVcrx1cLdIifQxXH5PUVCfwTT7wRe2w2h7jlHu2TEsx4IPj62m+W
clTbirIW2zDJVAqykCEn8ttQ8rEyIjpfu5ZElGWNown+v9kfHWq47LDyuJ3VPKX1km+ETy6QppWZ
Pv7+lr7uhppMzEVsUdk+lEUPIvO5tbQrx6erAWW6wbaCF3y921T8goT+37dTum29ggenLoPtCO10
NienLs5oG+KJKf5SIheuTYZXSRt6PeeUFWTbVg9+nak5HrBkc+2mrzGciUqVZThwpmbwBS1j7R8c
Pmyek76O3YkMS7u66lS7I6as6bo37exuIJqzuZ76RYGWxK/tOWlZvhrcIdnmiWuttGx/xC8jAOlq
obOkQVzTW2ULCARzxOYuwnztmeiSCLJW3q2SUaV0F7X3/4LeAYhME96l7+khT5NLxBv6HzdXk6e7
oPvsouiI0Ku6oQRg0+gbOnZP1VEUtJ5vE4NQyfjPZKcTjv9bC4jlpZPa9KIfuE7StrhZYzzkSZLr
jWOcoB8DRQ6ArMJRwC6jg0bC2RjaOpxXVlB7z0I19yVVKZgLLMRpIOixXL42OXqx7E2M7eNOISry
gQQVrq6l8nJ+yEqISvBoy+eg3eCOMIlv6aU+2vxygY6rQ00NIfp9QPoeaIcIJ2FL4BG1Oen4RfoZ
DJvNNZaLuXof9F+nACE0Jqa4tDLiFzSMtsY6lNldYtXSY78QMM17EuOHh0O+UJGds5GoXpf0xq9O
WB15Vx3o/2yl3AvwKtZBkoOsUH45JUhrQbNcfnMrf+UGBLPyg+/StLJd3Y4RwtaIwH/6h8OykWv1
DN1V8gRNsjyXoMzs95SWUXd6/lb4+cBN2kENI7PBqh69VzhAYPXmUIvTuGIDAIGGXCoi6dgQKytT
kLH2rZNFxx5NypMYLx0VekYMsiaizRfjC+r2myXfHAF9Pa7Ockn69zxWHjpjYO7+6QxZOvA6P6AG
zzTwlCl4ifij3L8I0aQu5zhRvdVou+Uh+bB/15YrCO/EvDiaEw2rdFZwNXBC1L44WT7Namqpibzb
5VBUduPboFaQfCs5Nom8OpFqr2XFrEcNQ4g3KpZFEHVZ7IBSjkBswGHGRweYkIg+yIUv1NLOr+3l
eVg+xU6Nf4PFKKM9kJKtQgfO63/Qa32iDb7xrNytKhjAfw3gEGb5KpzT4PMWY9TAODeuxkSbGsJK
cNZOWuHXq1rTafXwcZsERqkJWQPfeYXJyXO33PuclGomQSV8JA7EPKZjM0klcn/TisQ/t3wMrL4/
HK5p3IiaMAI5oy6TLYspDvXNYR4PTaLMc9HkdQMBXkOZVMW2BvirP5g8clohw+eigiiElzyJhVGk
vpgGGh/ekZ8JJySA0INf5N6PaEzdWAr7nuPAGt6w3wPAldHhl8s3SMEY2lzpvNScRz6e9KtBzhTi
pKRiV3s4T4kiDAwTD2o60i/JQS3otEc2tK3PK9mgHVBNaaUDzoRQu4b2kZ7p54orpnMAfjnlSxun
JRPGizFp1+2cOBW7fjSk8n0IalVeeAHf4ELN6/U5qzi58DIs8/EeKgElxkwz173IUPPV9kV91LcQ
ilGV9mmJEDB4HUX1NNFQ2mMIIkVwa6h6wtLDW6bGyxcLpWmq55ZRZ6PEcqpPhUoISokL4IZvAzjI
iJAfqEVGoPYSeVnvj9l07eqiK9hgWKwlsX+iJO/dtDWmioIamnv8eWvAVa05A2+kaWY7wGElowd7
ZMLrcFxE5g25eqkBYqs/i4NjF88A/gO4N++KR0fMl3xxz5UbS2JMZhgVFZsdbhgAjZWFaG4m2OR0
H+2L1Zt5s/SzXGU8gvySrFdtovRnmnnkCIb82Ez5QDPEZixszi0T/w4Fu11czp1uVLDLXHn0LxKX
20i3OiYDoztcJrt7eiss0kGm+mwi18a/AvOJ0AKZhNw56hUy2PuTsjBwG8q4MeNZ+wC1d8LJI3h4
FSrJyE45qpQzW50DDlDcghaz3eL8iMHugbaY/L7vnCC2sRuHa4NeUaiYBt7mhMfgWOrHGToUWdIs
W2tDY4AJdAaBbJ1sRMIYqtYwf5cdoqgduc04cu93QXvgu0sJjEeUgzOVXuhxUEN9Sh+66plXNKUc
/+oE0hrKTLBIiur8nqicga/ZctlZEWbvrjPK0vbaV7vXGMEyhhksMzTSHVTbroQgMqklPgq7BhPu
FyIj/HlU2lL9YFLAYbd7Y9uctb613V9FJIOhVMfeuFHQau0bgm0a06rO5pyjfCAqs5vDDWDiSTdY
7jVH8dvuaTKBOGWrBqQBZIoZj5pufopF+JddeSObjnjz2rFZFS0HVALMXtcBElr9kV0uf6NFxLo6
tzQsKTdwN7mq6N1vhJWG4y3sP69ndTm/lV52jfZJusxG0lFRIws+WqMMSg0RngmUo0tki9G72uLM
I4S+KgZaGLvIe6ghe72h3Eii7yr0vczatBIuNXwiOudT/B5tffnGwKmFvQJKWfyH0mPsUZEpIg1M
mjxqO5onGtnoQsVxQC/cxD5XcABTkTz0UlC5PFgAVuwYN/vllP727k0piACHXEDqeFJlM79xuFqn
AgOXIMbT9R2ivAz/tsrnKAy0fSHkg9PRC2aDeoVzB8HTs4mRt2HSeVuIEfykiE6XjKBuPR0RpD4n
Mgw2qeFL82tiVWmot2+GAlmMap8118jMyZOGtkOFKGp9ZduMiLrbKYRHnKHotXG70OVZwEaFrEjr
e15kuHagi7yaifqT76REwyIZjYAvj6cxv4HJmgH/JZV6ped6FQezRpS1yleeoJlZ+lMsbz9FRZiW
/JO63fTKHbFPdrXM8Lfb65Og0KXUQpPhYueiH4DIbtXRhrgIm8UA5UvGOalMGYaw49W/VMubq/l1
rsII5HhtR0qNLjWg+33mrHSgjJrVuJN6xM4YEwx4wRBtX5NwWE1vKpqpZCIaE2fiHbMnCk7URh5f
a4myMxtb8JzRIpJErQ09OzAnSb/qWaKE/43ZaPj/8udVipfozbg9Qz+VqVLO9lagzV8KR5VdSVyk
D5cpDDi1zcfbrd37jf3eD9RH7VyfFzGNAryFIFU6ndyhMpJFDw56TllaHLJyhsVhreaXzxXNdxED
xqi+0rUB4VDAqJRgNW4d3+ubV6dg7K50I9bQNXhnBAEd6Z8uIfLdNbcuf1lNDgXJzZgdl+cX3fQz
2PAYBoY0twKogXeZimrFe2mYm5QrJVo/GKmYUqLhm32JhTAD+vQqyTm2EbisaPDEIKdj1LFwN1sN
XUr09pF7Vx1e38QhQb0NH5zBJIkxsNu8eq/8Sca5N++N37yXb6AQ+EUTnHRug/bZ2vjtx6EbhO9w
GtL0buWKDrSGwtrE+olx53C6EFAY7c/x5D5qMFg/ROsi5BBA0BEIshATgxOMrtC0lFAYZBvcbO/e
JllmQZn0kScqxxYxr/mZ3/8FAhOPJ84+LCMJBCVnG4qI2/Ysi3+z4a0mqfojiDk7yu2ww+QprHxR
DFzAtVemcYP8fzQf58b/XpbJvQVOLWCuhH28wWhXcJClZniVYcSR/t0r2KgWJcRXXXz79bNqB2Yk
QpcqJaMXju67ffxn7/y2ANTLFTQtHf2cci/4RK7BKuQmOsPdTM4DA7MmRr//4XNEemD2mUICuRtT
IKt498FkKYxrITcuZeDAEbT5lEHruolWiqz19ELrLhu/cF33wy3iom7NmXs8WHVlz7lrTU10bzy/
5UjADjwr0BucYxscUUT36/qGCaWj0BlJEPHjkPe4bCuTcX79DV98YZWfpoX0sWA8TCaW/LhT5HeO
XCpNJ2IC06Yc1h8QbsUr8Xm98gOk3QHLWRm2zzsrYLrFcvEnNq+8kVNkvlm/EfAbICvdUpmrWaIN
yUvDC/HSBfPOUN+hg+BWoccH4gs7yUo1ZHcVkIQ9KXGeHqK3SS/N1GlkDJyclR350ERM7ojoChma
L8/IvsTbaHpIPKNP6Na+jOahsouepaEHXwdXKPxIFO+rJxtgIXT/C2ZvKTtpjUJuIReX2ss9dFAt
GvCQPcv7AiZ6cIpUoaho0Dx4Jdg2XpmVfosO2PS15c+QKKmwKw9MrfhFsTRiXPx1HzkZSj/ZcMBd
JFA3qXKPM3qs0jTcBCPUUUo3B0yc1511SrZVVduu/EfjhOvEpu0g1rgZVyEAQz1VCuF+WfgwviF9
DcGpWf9WksPW+/QIj0/KtjZfZkx/bt3OJy6aOYNJWX+2gcRByy3S4dTY1FDcRuZ9P26fxRXqu3fD
t3hSJv05UcVsOnJWYl6KNODwUXV++ELwNzmkvviApunfPP8lAhbKbmADzTvdI52yDqWk0LdHTpEa
2az08C16fP/uUMp9Yxxnet6vVEHckRdYwKF7nJtypBuuINRiXPpEDxGoqjSqBMNsAqDW+3hRu8Ze
WGNmzzO7IZuj5dnfNZxB4D5rQ9QpBUbXx4gclzSOnJzFV0tNPUmXMEB1QMTmjPtG16B0vz2gxcai
cEFKeF3yuuTSkK2qJk70wjO4+DLmZ/p9roywtcmFCF+ejJh4QVYfEUfP4ZBq5Kk6HaoPFFmMQXrY
ySRKm4zjvCxEBgyg6k8Mw3RlEJwiF3aTB45DdY/vwbSAo6TDNiwj5oAsxOfcUgNIShV8YDQzPFkO
ypo+wIorUQyV+472VeB8sfNNZFHVV2fDK8jsmbZX4tHHFp9PgUNKP+4TobCYcUNOheMFhucfPwPU
zOhEtb4wseQYliCRW9YKe3MffzuPTjkd5qJ3N6pWe1vH+ppDEdAsVNHjcxftW/O3VJNTbNFLjBSO
w00sZfyBuQDr+TIZ3y6SnIU7iVJYt9keAB3OqAuR3Bm3smqFD7ypBacMzXm4keC+dBSxdefF/WM+
XLu2YkPfLS7BiRewQLk6OUObDsvIVEn+zx7MljqYNdLxj7Gy6TdvR1HvA5FINsc5TQHyj4LZHIJW
m26dnr3GDLdxU3IBKLpZwG8HahDSg5e+6kJZ6pXV2jZiQ972h9dQrpYTJKTF/u8wxFVuGLzr1lMd
gmPUrCCGSqdnCv+4sf+DXlXGLQC5ypF7YqBxikBM+4u8XKb7T3V2+RRVA6HIywobg3GWtRNQu3M5
dvdYWPV08hzO6PYc+RUQea2sZx5Gf0Br1Fpdn4jQpeZHymOglJc0KgmsHqxG1s8Wc+d8k7N906iT
fEhsQ6BxtCDtcGm4LeW2S8tgBVzbMQURQ7mT80OWqMv6B09J/nXdk3evIpFVS50qvabEccyLJXGI
gIV5EMiEvbRBZ3xy2/JM4Ch6vyOpIVxXUlkUXKdIrzeXrQJmfFNci0bSb8trL7DdROkVsgYlmrVc
TiWRKeacHDUErRBHxoCweqVRCNrwl1vZwhkLu4SNJeDuLSGugyXFlgX36BErFwHqn1CkrFUmgamk
1uGmyvnqOzI/3+07cJwJawSl38NijHQBkG+ReJDzKSSgJLpL0b4upa2TNm87jNPyfqF0y15VeosX
7/KdtofZ+P2iDO9YMSJOLFLvYuj0G4dSjJWaoB3L3fJzL4g5+vPJpgF8itGKNJ47xqML2y6ChXdO
ewurIBCq69dZtOeU6HVPxNEg6jz+EXShavmy/LsHyGuUnL3ZGXoIKHagJH07BkPQy7qQ5UPmcazL
f793W18MvnK5oXt5cAYJKjwZRLgj0myawQpd38yky+X2VlcGQwkXXrezlZTRuUHi+ge2o9BVXYUR
uOkNDGROR2P56iaKSz77a+AgK/+ADLC4YcnsysLDNO6qkRwzjQ9IRcbxTVzegck6pY9hNltY2U5C
MkquUVo37ylBZ1/LpTOJxnBJrQJjttJebR1Nx+5pR9VnPTFWljTfKpeyMKKfmG+vQW2fh83R/u+f
8YzlbFFupCrAczwfAkG+nusuuwotwTuVOdiUqAxd0XlKsJmHpSNGWBSkDwPDWNnOzrw/TCWsKYYU
LAL/EJ9zLMGUrdX+5s5/W+p7VtuyJ9pqrMJHdYSiXA9P9hJOAntmZTTj1B+MpxI2sXRB6p9tvVGd
7JB73gdk9wMGffGPd//3IPtN3eJuyC7xU3Lbdb1kU4BRtqeCFY2pHKrzbD/mX36ISpqJ2aJ4ltYY
R+BSxkgz/uc9bap0Uu9svC0UtIxB5M0SJnCB4NjGIYx12w3/W7/XdGF8k6BM67WlxU4a5Sq8P/1+
B2iajNB9djvm/OunsaGI3p9fBn41q2dP7D0cuGJXTp+7ai3r4EtDffV6T7dlw/kmAWzF8lNDtegY
1Yv9usQhHvZlKFBOVugKtpDl/Hp1vu+BUch0OevJf/euFT+3bqKzxINlgN3s4NwRho3+N6lExnsN
C9jKv+erVbjjoZ9doCdpdk4SiJKYb3NLUeF27ALDOMHJOR4zNiD6oGyuo05FyuVJF0ZqPuEj8Xnj
BJ9Y0CzJzyfFXLX8u4xY6RqhRDg5yRw5PVqi/+QaSWjpKjBBYGWQ5ALceHmAqszBZxOMdMM0ReFo
q2o5tiyHl8NTcFsg6nQ+NCQBlWIK3wuUI3+P7qKJ9W21EDcFfb02/4rBVKMbj091RMLAViWVb3wu
kL5lEZQzG+uWLidTfNft+t647a8C+gOHYZAx9N0N/4+NwMWFUQ6pfzaO+aNaBx7XvKqnEMEm0z2b
sxrcGXTzNn/YWg6InO44tz/TZHRbX46TMuzOBppmdh9e4SRfHglCb8hdPbbIWL+m95kOpYtMfc/9
hVnqzGCp/4wx1ZSxwGZi2FNNzqMQNFqjqttnQ+fwbpUT/IZBIXigZfjQ9uD5jeKCJdT3yFElbXvp
GT5v9Gz2r9ICyLaWJ9qgwzAbV7OIKVTLDbg1Pdex4Nh63czbQrgvpGsSRFgylg3LmLrWfNd98VQV
1Fyl3R7ybVyBDmbGOEJTYnR643hVkCs2AYJyKEy8h+bnIRGCOP/on8k50996hrApPHtI0W3a5LcT
NxTtqdGJ3wETZV1wsqWDLqCui5dJo7x7UKYt55W/CTFtCtPPqhnvsGGyo9qJ5OYWmI7koEllsWj4
Xui32HWeIFMEaY0IO9Xm8rUxk/HX7MlKVa5yD8C99drXlcr4AUmlo0bbGYnkT6sN2wk21yvkhXAM
O4Heirzs8PwCEqGi0broMzu47ou+sW4ucHKq/G5uZ+Afe6d14PdYj1AA4NzsJ/40MFkNBbnb43Fo
tdR41f0n+OkSTLRUULsgpxqys+Jm4TizPhIpo35HJKm/zXR2sx49GuXCm12BtBV+TQytlAg5kTiE
gHmJaLi4cj+7jgxUuuStm4WEwzd5FdU6W0o144iQN+FJf/+7er5Uvevgo3DX3n/VMd5Rqtk66oWa
jfzk187v9xFdgacITuboLqaFTLfOPyJEUm3nydK6FpiDstMgJPTOQDOyVgNq/4VEEyUZwAcwQ5mi
Oce5HNCDjpiSExrjvnbmKl6ezzikeGVpyBVU+iuEWJIYP/0MrdhVCxG8vQrK0w6YEnBNU2JgqrJh
DDgUfrVSXH6yaP55Jq1tumhXkW3IGAKqabGXunplUniqRdl8CcT5gu0qi6ZRg2ASNxBlogCSaOlJ
5xknYz+yjDjeHSQYzu9hqYtM6E59PEGv+/nPo4r6raoNqU8+Z39FJ5YhmFyfZX7xj/hlPob8vDQU
R4SX9WOuXK8ygG+5iB7rl+1liHcLoR6588+rVJl3vsfGS1Q0Zo5YaMtCAAjoTyRSllY+VINHOW8R
dyrnt3LyZ51yQisPMh1VRhsKOc//mDbzRBcd2hZxQUgn8yUfKP0zOeGzdAIhXW94UZ9aYcY17RoG
AZ+Qx7CbcWjLa+VuCcvy/mc9uRtNeAG8etFxKILF4IyzZWKIS/OC1Bq6RHsKOX3YtA7iGDznktrf
AFkcww6REX9oVC71PwStPPhCvrcwxQNTD21JZHRuEZWaaUanwHc6j85wDU2V52yyimci4/CWFMbD
YPv3om6v6DbRIYyoFtYn+TNB8OSRkFo9FCQch44CdQBuGIQWlODz1oeB9MRbWm1TqLChDkC8ks5h
hw9Aa7p9Hnk1BqHBOVbuz3aMKDydRu5h7zvOMNSmoazVSl+xjt6JZ2jamrxyZC6q+vB8dAo4mIg7
RiMrc32b8BqiIfFcdnONzyU+eJ7junuJGssuPwm3Q9Up/r3EcnycfBmZFh2biwBhHrgSGSZlsIvU
+i3oILuk3/VSb8fXOc0b9bQ/xnik+YeRNAkTCLc75R2L4Mr6eAt2GYCgtyfXenBTpZaStHm4W9ac
lWD8fdinte04t/ODD0vGpy5k69nxW08xUK+S5+SK0kQ5sGLupCaJeh1mtk0llzIaUNNRNvCPc/ZA
5DrBWjfUJICzphHGPZI7cmdLY9EYC2yVDdKA3MKdSs5JEygE8/kF8SBQtJmzO4eia3l1C7ukf+GU
Q2LNn77Py6pBlYzQvele5weYde81odRoIXcSkqyWv7RFsYEW9aHzqaSxA4p19hol9FTvMlKh1ury
F0o4pLN9lxRef7zHZnnYTo/NeRSLPXkDjsdKkVZZM6t3nzxMGKqmat+tWpEXGvyAsU3i91LVA3j2
SRaCqxcSBjXRl2RfU94iekorTPO5eC1/rKp3y6ne1Lz4Qt23whSvykIyGn0lFxSU9uZWt4NUdYRl
N/mVv2+y9wMGOHkabRtKZXVTFYAdUZTUep79FM91CLPRTTn7/xBuXf4+cgKEtnmYN4C2FOb/aGx1
oatM6V+wLMu2qCUX7RsCY30oABu2H5PAJPlFbB9TSYK7V+29H6NStAR3ZS441Q1NLO9aMr4lUPgZ
HAN8lmLFeQ60PbWY71eUuwnOMAPrN3vPrXcbpUOPsUJIV1mn9p3zg+czc8MF2OydVq3l0TOcT+6Q
VsAREkasvKdzDa/ZdtQ372ppPmp/dhcIWOfKBdnwywso8U654lJsbfNhoDtSsP2l9B8wpqKo07uJ
hLAALfwdTprLgbR+1Z9KgQSg0bu23zowS8kx1SvA7VbW1dGvbPgrLQHTCpNyAjYkE7LTeMXvRf9O
fTA0CEel6BhOx7G9NOaKlhWOCmrh5Hra/nJp0YQBcvU41/DMTkn7KDMxV2DnrwPQ6gv1OtnqYEZF
ltrmT4VXLbSsKP+ZIU+zzp1dlhv27fTcueTm93+Gx6KnC0ST/7fd3bQYRgFOiNnx/73hYZU6n2FB
FVKfbtCyslVFGqJQVMoRkwk4KuXitaMVTb8/83HJaKO9eWmih+9A8GAPPRttVwXDlAsi3GkY/zBA
/Zhh/Grfqc2zyumfMhZEleNztayM5XOFUUJ9O2F0YRWT2ygRuUw8tlMoann8jEa0MQ2MFACj9UO0
+Xqoi5IKWAHSYBG9LqFmc+1e4KJHqQwsUkNnZW2ID/8HVl/Z+zkk6uMHLuahuWIcOMu7uDQXW12x
c7oKdteaZ+RodRyQGq7RgDntuKLoCc6NHw2eZoXvBiTbyhUgWtfD66iqjpwNTrmnf0RI3NRDJiLb
MtwiudOvxuGWJeIwbXvaJXnJ2ewb8JAgq63Vsh+MtCZGzEtNcgHB7HVUVazMj2+buuQLX15nRI0c
rvmgqo2GQbVBvKkoirgfzSq5xJDFo+K9R8zllvh2S9iwJK1LZ01C0Ge80SrTaK2lMsGlcyHtnnDZ
ZMjvGj/uRKKczJdboGkVWkYi56Lfz3LMe0qPu1Y60Gi/Z4iBuorxJH+HcMn6YpfjDfgeTE8FXXTV
yHvmYJiWckebIKX/puHgI9QMJ13ExSy0FxKttK6lFmf7J83f2h6A7ulcJqFqq1ngx3HJ3LBziIim
OKD09qx4B0ZKogUUfq7fPE75Qa4/dbUyNLtwgia0flDgGbZ4YjDJlmOJIVxKyifXuRy3OqGJg97y
CrNI1vzhu8P0JDpuqnBxmRzV7O3D8emAQGg18kXGo78NTczkhD14+NRAFFzcQtTEJA+3q/d79Sa7
8nhN+mJP6Qr7QslwOAWJrW5AAbW2nMxvj609CB6Hh1zQkq2oSgqtExyIDV4Ck3mVWdUiDY60OoRx
7WIRqIc1KSQqBvDWLogOGqpiujDii7z4WsN5SZus56dBlqcIR1k0tix3p8+PRhsTpEY23U18Lr2V
3KMybFCnT69q3YF/47ig06UL2tN/mxYp5OYJL7t3jdZ4z/yho9kuI4lwT5GLJXBAnj8f8x0o105F
gh/XSPy9UiykJqRzewK8pHvYsmlaKa0hn9mt4NXDo/irx5PwMv145x5HJcQfxntcU6UVzLJItOF6
Z6a+Wa0xWQdvDx7Jkn9/bwl2SfriNw16gJkI8oeEriKeDQK7hKHUh2NH2npdvQrMGLw1CC/7oLCB
Ovhr9NI3LSUc05VMhO4IkjHTP0Yf8zFoSmGqlzkzcxaF+Z7TNGsyw3QmtgZDEtwP4H+i7ijXiNLm
/e/JFhR3lXBkQ5yVovnBIjBRTEywwRFbUlOSsZS04TWS0lTNRtFWRofbenF1MzaGcwVBd4IcLhcW
pv3gBojAw9O1oFYdngFccTJZoMQaQPnajPhIE669As8x7gJ4qOYDP+cxzCJ10qCLK1z4SA/h70X3
0uj1kze3U4vcbgyonUNPzuJ5MZCAB/oYOhJAjYt6ukj4pA2MgyW8buaR1LRPC7A92LKaIrbYMdae
+puEgPlNep92TA1yYLKwy7OVFKG5uX1ryXdIXbd778YQusKLkn9ePs9G+k3TgMQJwu8uPDl8vfTE
dBSjRTEUkPL2TjO+TqdVSf4JBbRm7zOC+R/ElV7/kubIxCGRWDJnLJK0J1wl0WA+2zh1K5TBny/g
IzmoJZUG1cD+qZSMAiTx/3yL9HilAsgow4miv75TN4jrcXshoMlBFsNkNczSYbTNEIczw3uRMv1n
0ecK05D/AqKAKKeKuowV+DuJaEF7a2TV2TKATNYZXSASLHcsCdY4SBch6JUVmYC0khLNpomfqdMW
E9HWjg84nUrUnj+Kl4/ymhl566Ap6eVaIWUpkho32R0ESYp2fA2ZgHu5prCF7ZfvfXntN4FssNHN
s4NuhhKf17y9bxgRIEEa8cJm5CB5wv2gwDwgNKU7r1kYD9lacJLVsgyZedMMp+Dn0+uAkoBdfUJL
ZqL36F6hLP6i17JnNjkT7H8OqOPLErocAgqw7tSpSqwvQtebMhCIDA/rPaR6pNlifR79Rax9+FbL
9JZaU/RovFJdIv+As+pomDbCO2pnUxN4VPNZleJl8m+TRWssipxrHuWxBKQzkR9+gId6H2ClAG7H
rjX0qnKSB1x7EZX6+AT16TNJW0NH8DzW+zAecdbqYUFZFwX9QsvumjqcJZ7XQ+tFLms0ikpBuGmZ
W9XHCQeqN9d+/mUdW74G3v8iAuYZwpCXjiyFYVSgtp8f3DNU+BvUtAcH8Gl48W9H9QfoVqjkhCg+
2owubcPXANi50mvN+T0awIuVQJsfdk6NYc2IYWRr5KkLEw9mTou3470gsm6ykSBr2LSNmrgknUHo
2dnsfywRTHIKY8hKG3yiosS0lsBh0c9CMiV3+FLYVVSGQEVH/zGmL/Pw1R+WYEqEGLMfsotHmwS3
bQfA3ZyHihBeeqRy1SH6Ebs58vZL5Z5Rk5+d5lF9GeauvALvomzbmamvC55pKISbWQYSgKYktTyc
835DpmddhLN8+enDsbewallxn6mCLzEauGyUzcQgH/QUhU99cGIdhMlvALp2sqUSIBCkMbooVlqJ
mo9CThuZJTjCB7/Ze6gPGMGHo064MIwgyIKRmnrKgm31xdbX10dSI8/eo4i4yRN0KmgymoSNfAS/
PBA+4tUPFahYMkg0wmFvo0ufgYL+aaXjCfuo53fosxINVmO/bAG8FeA0Y7XmiKicD7jh+sA5NYaz
3dNwhXSgr8GoTC8lmGkl0g15Ak17oo3ehSlwWplHjNUXgZxH8ITcPEBUz2ycf6iecBx00jkKUywF
n629J1GgnI9FMVSOkLBnYdl7ISMe7dm6PIJcd/g28o/3hPPKFK0/9EEVcKdi2xPWjJ3VRS2+/M5q
Ej4Zs0rb0Nm6AzGjyvkbTpOwP5StVzsrr3J3mIxAB+SkL9DBw3PVv0hb1cegGCTfN+QT5y2LoegS
MEXL6Yx5ZgGW1pl2h7n+CLMKY/hq/pgNoxHacQM0wOeQGwNVMC/jGIaiJFYFew6F6h8/czC6qn/v
CKOiW4lKHrnQJMoq/ZPNOYjwWOencUxUeLjKzLCBeaf50U/kooCxTr8pO7lYNujPmhrJetpn5/Uc
S71xp8oQGLUegBIhzuF1L1gxGMYhKP6faUiMAo4qJdXtua7OXQvvS8gH93U/fW+0wADK8rtBgYtp
cFgkh65KFcRczeT6ifpGgdSBNP+a8oQ2Ck5nokYqKt7kf1bVQyjyrFw6spmWO70Qts2JYA/0jA6Z
jREylJG90PqLUaRG9NLssQ5dthmKjflSUrJ03ORcBnuK4Nz2e6qK5ESZurw+/QDlP3Vbd2kuVOcb
80qiRzfJb38hD7kTE0IVjH28vdN1S//1XZ1tbC2bNQa6PMObQB3wIoiSqW3uKI/CGrvgw3A9Z3Kl
wGAYcdtnIx+dnuvnEVjeiDZrntsBP1UdYT8VhMy3sdCRJB5YT1F8F3O3YdkXWaiG+2kSgac6l8tF
pIrqMcX6C9SVBoK7WdmzPR8YbQttE6i52qvLznoQhpfQ6+nKLig84aXPa9jAgETq2q/fgwko3DK8
hPFWQ3csprzDb6P/9ycb5BQhUFeKYxLjCjoF554+6xBXYkgLFjfg47yBMeiIApSxMFmVlmzmU7AV
jgiYxwZRackuZjtss5Mmzqi3rroq1HMpSSylAisluiuEB1AYABIX4Wl4t9nEWG070+iC7qkGSkOB
Te+lxN0X1rWQXW9mTxTUjMgvtdNp15XIfm6VGOHDHolNu6keEuc7PtGkEEcmufXRqOQTDN777yn3
3iejXzO5bPDDD82rncsrcvO03l3aF1sumh6qgNbyDnqBYuySvXjlvJ1BCIaJK6KAZICaM4OgzwtE
U9ISduhvcqqxE7nxx+GFRdnFvitMwTgPkU9ho/kz7wGr5GO/Nx7+HKLZVM3dc5d06qRi5KQ1a6vD
gX4pcZ1sTnzZRKIiszEv1iJ1C9qSceta9AKBJqokz5OM12kPhLiW3ke0P9fdTE0k0TA5NSs2Zhv3
ljH/hsdz001Vq7RTcUt/m7WzJNtwWCyR+Z+M2hXs0EHW9GK8BuhSPLbvoEmazdhK053vqFgsj/kU
bUiLVGlfsNbI8acXWhYXEcxRka0uJL9ASJ9E7evMYyjQm3+rbCiQ9buklgNzqyG2Shxuy637Xj/0
VJtOUV/IX3n/ToSQB4oOXpERGrw7pkD2GZf9h8czL+wjVfhJwsCzdCR9S4LKwUuJeRnGSw1DU5HS
0+f7R0a9zk3/NT+W+KmCsXLfQLdqFlmPYSnDt4ziDoPxWdiD4kz8PCoAGfIomMvM0WTXqIBzGIRV
bhLeP8n5E/8ReMRUf6P7G+U9gYcSNuOyGEhLNIczSPZVjMN6shANixkXP2hcPUfO1x0xnywiYYq7
Ggiz79H34JD99t9UJukQ0rVPDQApNrFzYC2r7oze0Tv5LSVxDZqvCJOqUlBP9sWed5nQT3wpK3XQ
aODEP8T9S5yOAkog4cjdhxYhwNkRTFA4T9HD4ojM88kHz9bYieStqfMAomDJpQTgFW+TQUzzboAI
X1T3Sfkdka3ueLjYrrCS9pyw7IAO8ZBem3hATqvcJQEv3tl7EBwgk7tUKahHmKeEj/bWkrzsbrYu
ipCxKItWdelJp4ONM00/qUCZJ4H6G6re7hnoBVZpuIBg3YBU+ZDp21Oc1DOU48xtgiQUA589H22P
55RmPLvdPT0sXncJUk2L4KQAH5Z5vNBSOuTyAMxTRp/F4ClFbW5yIJZCrXw9VI/7xaayCfYIdM9o
+fpol692KJo87Ej/IVsF5gOk9yIRzktACeQePKcujHwBzFbyP/z11/HxyW3vf4heC+NVxM1LOfct
BL/9Tv2hfI+0rRConzicRtn7Lo9xeEs6VfjA7e9vIZ1jXIREnKcMxONFECaabdsHRqT+BzaKPRZC
styfS/Rx2UcWRZRPEDHE6v0vPZ4r4535UC0uCuyXA+Pxk8l8wh5x+Liw9lfWQEitsaUOrkq0dmor
B5x3aJCZLXEBwBsHidV3T3Aej3Ad755UsEhaESnHWjHYXac1WY863tyzhSanlGckDjp5puk+Rvol
ZjVEKBafs6hZZYPkVbTIf4AyEohRdiFOzY15fsJs8m3GlBRlApFdl7Q09WdNEicrNYifhv/7MKYM
JUOzMD+KpQU6EHL5o9Jh/QUaWadbU7uN1PUN+qfJQSDEw0mgYXLDFXUZ0Pu1wdnMRwt/Wh6E+Llt
d+vOAIcJ/vrgqh81Tcn5/ASLuxj/Fa9KUN/iFupw3E3RND5+s+9LSLqSglKT5+5Grv5ou/f7LKgf
aHsWMbjE7nnge6Fc0uLbqzYpMYoKTuWcMCXA5T1BnhpaPVQFcyVhjkl6czTnKARwSaDryw0pm/05
2+l0oKsSDd592smFMj742PBOST24Ir+4hC5h0+9fxAgoVvo1YaWOvKdR0iv/vsP3pC2OtP80Vull
cSLcdK4ENVNOC7UL8ssI95+LIb2Q2/w5gma8osnqUBva7fJMDz1nJgHljXl0AVvB7jPZjNAY+blH
m0ILnCXBW/U3Re2PL+3ZkbnLgYU3IsqsOUFmJQmndsMR7GKBdSMBSPLVJJdiaH5U2DR2wgqN7YHo
QluAoRZto6ulIVF811DTUVHNZvlllQyBS2GcIo4+yStA4M5y2ddgR8tlDIkb/NKbQ+T3SpBMNT1o
3QVv0lgDs9VuI+f+EeWzh/GaxOpnb44Ch/ZHL1M6eBCMWamuunJ9d3mMYfxUxHFn85pRNRgl8QqY
G+/HCvfAnu9Ynogc/gDNr1lb+qf5/4T52kqfK/P3PBiE3uG3AvqoM/FeHw5MI7/QZ1epmFXB83/+
gaalmno9iQsbvYlOHybRQ6CP3A5X4OHi8TneEawuKbWrSqFInoDBWo6dkI9s93ggCtZiphZ9RZaY
/WAa7ldmUCxaeTg3kad9BmTux1WKP2ZuCBi18LAGrHBo2bUJDwpXxMLsbtTKOQh4nKI2HYrb5HMr
UEwzhx3Qr2XbiQ5cVKqYvX8EJ42CmY2vnwBMsYFfys+jdYZHUh1vfl3Gi9BzrzPvmXli2B4lL1bd
4N+mOrSTMLncKAgOyYxgvl2pxWTU7UaXMbd1GnxhinvO1+8orsBAHvsSfhr52yEmEsbqHUee+x4y
7EHP7EOJY9bdLCBO8LY6fE99kGmZPVxUq+IobLHeZLUsVe9RsQNFVpyZdQCSdRhr+vpXf7Bz5jXH
LpjwruHcMtDrcpkpNubKqpuxbGa7KV95P86XKR1vDztzNi/LipmYjZL3vR3j0bYHvQYdYJYFH6si
0Gb3YaF5r/w/TU5wBtQQwsdnkqgwTo8jljJ28R/vLhho0PI9WF57XyDipSuDBxXBOJY+0LDdO4nA
a99KVMm8c3ZoqRnp8Cu9VQjdqsndUJvX2NcUWBRz1z+0DSZqNVoBuVqvt+bBK0yiraVWBONjMxkY
OjdcKCmMroYz5E0LbAeF/Z2iVBsciQQwdnKrOED4sxpTtq6DXTL5/7dv4LZN8DjrST1g1ph6VoSS
6otiJx+HtJgcm6aSND2dL9gkSmP4VQsVva2hJHkvLhVisszYXLSYsrRYF4yer+OcGBQg5p7HgAS9
/lrD0j0a4YowZIMfaoF2x/Dp1X02/0eCEacG7jbkz4Cs2ewtXoP3lSC8hc/en+Sc1f7S/nmgo+Kf
ufMcddWvt4byrc1Oow97uqzoFPz9WDiqZrMJfOyW/7bCeLq9hEUZ+VL2Lqo0bRpnEt+azsDk3Oo+
a62Dr5exqCiHv7GHztYkliPzNuSKyQGkm6KycDUYBuERLB5fy4+lu2uu1+QrX2VaNAiRz6dPgQMX
5d0fEKUNKvm5xgDFzR3xHhMaOERfyTQqc8mNcv9p5VoZwOPHvJsfMigDg1omAap2xieFlKjUHwHw
+QG6mBczROGUV4ztcnZ8mZbEsCxhjAvUd6Uk8V3i4dnP9BfDSZ4aDYgUBKBAZZyQ6XYyeG5kMUpt
geHYQdJvV4DkVdkm6QWMaXFsmmsiuqGKEm81vNtfCPkqMto4mvYZ9ZPMmqTmUWMj12mpnMemwlfl
wXR5Fm0iqO6CZQMXipiBsjOY1GXODxxZRtyxGtFNnrRUmD4FjDQ8t9C7WyHtKvGi+e40rfN/fPP1
4VlXJEMHxn8+vrWxENUiCefZiNGpbv6rvqzKkNqATcX8VYFO+ogzS1UYIynNwiNRj0nl6foI6JfM
UAqcF18hkazuIoJHBJlaUydA3JGLpj7gBi6loIlpkjVET5VEDTpx3EA9s8hS+soe2jdTK+kv4JGf
t1qnQdYfzkGufgwGRmcpuN26sNYmRqd+L6Bikr3YRs2Rcy1ElEYFKikEbNDUD5k8kzaYc+YZz4/Y
+ATS0F60ilSVamdpYKvZfdb9s+cbamVtJ+n8cK7U7tieOquuCkIdpAV/95EvPb46sZREO4YtuRFo
Uo5aDusjx7rm89A60h+mRBzBTBiEEGGhZMx36iGWnGmENnQqB6meFZc1Ui6pQWU8UYDzeE3qGmxn
b9/Bjqovso4JvLETy7dQY+B6EiQQAvt/F+A0X4AyLzEk1gDA/3+dqD2WlgUF/5Kua3npSS5BzWTu
wN2pO2sq9CAtt8dxfI3fP2KdRj5Q46srperYhLYSj9t4taM0nqPC/hJXBIs6wyOK4ddpAWIfXg1X
rjSEwbAlF2SJjU7iQ2LwztgzYZiQ5fv+0LKcTHNxR1EkgQ9ODBm+WXmuDSjG833bIsu+Z5bmtqVu
D73FGOoQZrK9l5Ohc0LkGgPXBfCOVSyeiT/DaLRT/RXzW3R+QAM2xx8LC+VZRktb99qpKZ+MPtON
jAzYA6eYMv7NdUzuq8Dj/UpENPSNo02/mnp4dKNbecdHQV80hPiU/0NzQAIeLZ4XYpBkVDOth/oL
uUVK5Wn1NDmBSYZ8kVVhKKzdRT8hX1z2ugfqoumLk2Vppx84HVZ1JBKyXEGULrAffDy2w+fTEYvv
wxR3+wKIu5EkMbPZJdgJwPo75lWQmhlQRuNAz0bwEULCDQ/nA4phO26Z+LlUzOnjI6MmnjFYo7Nr
o9BAdP6jHoVJlP7soRThbJmbWWmZhwurTVIJ+mJOLBGz57UKNF5JHNIHccH/FhwMfAn9Oe1q1SjB
MCxX74vhQcTcnKoTdSJgmeNjjZLmRf2bvwVZzKIMwRQv8HS87MgNvIxycyaNHjWgWafkWGJz8kdR
d1GQU9MWmQKvsS38NPD+s2NLOn7HITpx7uyyxvB9agIbukhh97yPDK84AEMUKbWIAyTYJWxRaVng
9WVd5SuluRfszlhZMN4pi5ch3HrbgFystFb5tqiQLuG/H3aIxkKzBdFV0+mPi7wcxl+bTlhdybf0
72AejNdlwn9IWeDjWt/pwLhGt09XJffwXooBqBlAb8wJ9xsDipMv/el44hDVLN8gG8WBBBd0GZRz
sVAO9cdiPmnRkgDTZdhcx2MtcBU9u4JXoFfisaHE9+CwIRuIWYQxp/PORb97s1sIdzpwDIJfYgyk
j8smDQmMIg0SA3eTgDRLl5ElsUx36KEd7VA71sVRc+1s/BLBn2xw90lj+cSsIrCjYm0MSKEF9JPj
RiOo1F+ZmbRQFtneQ6lJ+ZoesVyq1Uoo0PnSqY8lPGl+ggSQfTyvxIC8INYU+3Mi2F0cwvgpfA4e
xhuW/EoI1+Hxp7+nuK/uhvKvLcW13sHQt3JdjcQ1hjA7kBhcySidoyRFYbLx+EhbhDdSaap5wSCy
MjzqJLhX2I0CRbuyNilnsYXiSeXq+5S6npkJnEPeOaJND73eeuFe+HNNEZ069tv4apaCIVAWId05
nzDDH4cvquYVAexkHVdfnhUSMisRg7PyFx3Xc7V0hZNEPsEPw12hWFLZaklN08y6zB91Rb/Cq2al
0mBuMi8SxxMrviLYQaFxi0Ju4pCJOtjq12AuEhAAl9S6Y/XryZeiwQDQ1nQstc/Fc3CRltuMuYh+
p2KQ58pXRp+aCw3+mN+6bHP5/qXwxGD6XJY5LTivXVrJmPRNqUSOvu/Yg04iz2v5Xk+wvS7xrgJL
DFFtGfj6J0L1lY4GqWCIl0hRJY1V3N15+EfIX6owx9UWcGl58WWkCXbxvluegS6wr81UmrYmMKu/
+xHKyEP8OOEjBXqu4gvGBhqp7ZyTcIvhEOEHg11N2inBpT47PCvLY+L8NGmdacwLv2vTxeVVtBei
xeIVkcZgl7BqOgUMNtI/or0L4OuaKgzbwb0rqf041fe/7D/wWF7OBkg+NOk7+2smqJ9yQxQza5wx
x7ASe1Gz+KUeFWu+YFF85h1k8PYKN0HswOuTnSflOvFwDntL4tUZXK603xynbfx4vf0ZTEx0T9vi
9vjfgAHsbAe8Hd9bNl0F15/pAsMH51P0mil0URLxCw8nfJbQSYbHWDuBdwLD2dtMy2kKFoXq3+r6
BF2xkuw/BxmRqk4oCqb7CajYezIIWP52IK/m1qNYZsJyWHiigplxsfJFGmfhD2QvPxkp7VmCwWJ6
JZ29FopagH8q8PbfUhkMKejlh4ZERAkAIDQRepDZp2FsVb+cukVIINwkr928Qz2ZOvIIU8mjrXLM
FV0PKndBR1Cu+NULX6KjSciKWq7ZHvAhyzEt4cpeYJ2wza/yJQCJm6ULr3ZC1SlPq5BwvOCzI7n9
BqbJ919EQOnLM0PVhKs0od19RmaHu5rwNNI6qLdNPmk0qfnrad87bTog7BacdtGyFGkl1OJm8TpT
ZTyIjxRjVAvswrZTYp4UXLNxdNxoIpMuRIcn+yhSc0E4R9a/gDB/FLcCTcTyDO4RUOvj/9lnBhzZ
BnUnI3NGlpDYmnFqTBF32oyLiu0qSReNoy7dvs68Dyp3Ksd64uAFgLuFoyWOgZpZIBDjKOFkJGvo
ElJ4Ch1ZCo1q0AaXBJufuWE7n5vhCWsmw9RFpnrAqghskTsmOcyEoGY7r5lNRTPkXUiJFk2R3rgl
DYIs+4bORCx8+RioVExuwWPPKvUTCXJ3TuUnHEZjOGo2A63se2ndM8vpTrv8fTCDqezx/TdoIzG2
jYgyHEcRJIZHecfSmIMc35gMmas5BmjhSKnBY1NN60YnzOgTO+sjX2eBrva2J1WcFq2Qbp65e19H
iP6NLRV09F/m4mW8zYDbvnORh0qzfB2PHzOwfMIqQ4Xm9dnGwsMzLdugnDEoNL82ktOmD876hIjN
OCzwAuGlDQIq5ZGUnVxOw+H4RslEbA3vAuoDNhh1c9VPT7DAt//7VS3xa7b0UWeBdzAy3uOZFSEu
7g9c5cdrU0po0dkoPqDOtFzYqUqoWzzkL6utWA42Gf99yyBnqGBvm7M/WTXE+405In3fpNQQOg5o
6W4RAFlhPnHPViNlwf7V9aZYJop9hm+MZQVsmyeZUprc7Dz/2CXvOVoRg9pZVVeS2oZx/GC4O1cN
X2HNautaKSLDiPg0FlwuRAj4iJAiU1ZpiUyDlf6kg2SRTFOxJpMJOexOCmFBFyE2MRjaN4MWxYv6
htHcnTz+QvwVjZYNvkO2R7Yo0U/TiPcG1qtN37MQVI93kGEO1RYFimkDMGuyaUW+fnQPyqpzHBjj
qtKmxNWlGeXHOFpWzWXMtfBBgVnl3jWL9frlG430zz3pZUSdVfu8cTrMDKp65ean1FTFLzojqzjv
mzyvJQTQd8OTk0OgHK3tCDqcM4rmZgXgtc2ygNyU8vGeJf920npzSGwTznJSg6JBfpHGSoTxms0m
YMODuMDnEQGspDjqHw/LjjF+vCinEruoA2z1nVRh+GPsAtBRwI81zbeHeB70CFegaw9b324T5KeP
tn0mCW7OSCkAmvHQ3Z+cm03HyViLh6s/4JvjcnIcv3hCunvT7nhONa6Uft/0+FhATTAKhg2/22fr
mmeFqPhZ9LNxDHUa5uGfJeljb9D2ZrHsBlNK95VV4yDXecdqgslMwycEP3vQWuT9aIAx6DCy7dVx
dCJm+jiZUrV3f/sHlUE2QUdXa3Ff6ENN2lqezhPM0+RfaLm6MV59TNk9Mh4fAWh8zdyVIfxpdFde
RDuOQEGJoVW8gMJ8eUxZarTD/G/5ynDVGwQNp6Qzh4AX8dcXKRy0bbCC9eJ6hKLuMjNW0dt1cfrf
AxJbNgonM0JwUmh6ifTZSKR4phN74VooLSKiZRtul8Up8h/m5hpqxSxZ/la2/ifowhK1UcR1stw4
ghpSpmbxXLdwF/HZCr0VYmJVVyxVBPtPthSlUJblgC6PDlI8hFmDQrhLMLq2NYrByHHYiadYkYSB
hjpdHKV5jCSuWmRNx1wCOCaoYPeYJsNPpCmlfZNvi2r70uNuznMdRikqB/Aqh5kQZw9KYXWHmIs0
eL0ABdNFQ1YTFuHHb+2AnJCLHiU5k4i1gEY3ptyd2Y5NE5QE85GhtN6aseMQY1kmSYODyLi98BNf
joDsBtjMUQE45FwVKiPthbmXVlIBor7Ydh/zdSexPTy6XJ+xno6KVs7PS0JNRaHTUB6R+0acSHQh
90pwHBOCOc/VeiMGVb7oMSW2cbRGmlRt+eWiKND83SnC/nvscxrXLyJGEJGsUTW3G5rDNM4vAMNC
Ysxe/+GuFf7CaPCgUkiU9DQHV/4uvRnYqUsPsAIvG635iaYFHJXmKtsFxpvqqtiMcA3UexH90FvM
BBsCyAw5A/B9k88NBXJD+0ctG7mfW7udUS6gfEyigoAjdr31u1sgwCIbAi5SMwPAH03rQ1+4IncV
2ZWg/rfEc6+lJe7caNqS7rW54JvzxZFBhx8GDCSdezBWsZOHpzyN6MiVyFfhAqqEWDjtVFkBxVDE
luWMByKowWiKVorpNOs8nsv1tTNHLPP4RvElgqWuELwOWYJIpxN1RF7L7IUevYpgIVLfXAgyEt1E
ugPBUxVGnkWX2Vp6lmHHrhklsv2S4pQPPkqH64tgd1cyN6YiRmqxOPrZId5N4yatdNIZcpZuVIca
29OdtLBtLNJgNbBhqQzc2XFxBwoVc9Ri7qAMKc6tTojDUn8So7ImGM8X7vC4kzpvQctBtd4uH8Ti
HhSJFdEQw0s0aIt+0Cz7DCcrWVO4TKqxA8KO/BecPBPG9YiwAcVC2YLjvF6wuhx1Hpw43j0HeTMB
Krkv4Uz/ernR/pZB4mtSxIuePHZ9yyMxcHu4PC6SG6SHtO4ehaM2iLXIc1xaIQNia9783+4DZ9vm
1lkw4zRKUSRkHT8cjZ0akefOQKumj4SGIwJHky2L+v+x+nVXkw8CmHEvOUK/8NzRtv292qFt4Chj
YNATSrX0AfG8+XTAyMfn2YVyLz951Grm+EVX1XrleFHMGq36ZFPv9QP0wZg8Thhf4JpjTWlweSQ/
hQemmFCXY3ngmWNW44Ys4A5t/du+F9smDPo4ngLxpGw70oBnj8elNug42iedkZHPyz5Zks0kzo0f
z9c02725zL6W7x40DCA/VptIxGSrib6Y9wruG1TJVd4lnqkkAuNmr/pxLgHB0m6bm+NYh3pKoqSd
2QbXNQRHdL3G9M/S+2Mm3DTffhsSw+nVp0swyGXs6na4jkae4ixQTDR0nutJwvNMcDXBonRYJ+xY
TRh+dzPyG2IugMLy/q4zruBYHX8wtoZuu/yWyLj7P+dyDcPBYR5/xv+8NWiXzbvKIv3kVqWVwDXU
P7OZX00G3En3BAtn1X1SrK6YjR3T8pYVsLFEGB19umtda3eV3gRvG1z8S9seesdkFnA6EVKGldki
S9Pb0j2/MNcNNZBerMLtMRaQq+jCbQyS4IcUhWZ2pv9XuaFkIIxF8qyYe+R3mJMOFncC0ylxbL+C
8v5H/Wa2DXYsIasldtVRl2nABFkGoDOztKu7tjFITvWLbjbom9D1ruqMWZ3S6gcjzGy9/rtVOJZp
M4G51c8IMGuhpaib/4nB4V0FmSz6H08cy+wlf7HIWHEz+gSMibI8bURWI8v5uZbz4HTlpgtJyQfF
OgmFavNhd8E3HshocZ550B+VFXvaPq3Efs2d6Az1O/Yf3lyRF7hjYfEgEEkTlq+zMY5p6+GnCQCn
kzKLYCnfQ7gqKyc8CGQtPBLxz9y4ClougCCH97/zST7iPJ8FmxHcuHdivD2pYofnIjSLgXZSmmBO
6dTDhKStPWMmPCUvQGL5xm97YysQsPg2RuoifOy9GfI1P4QSulTxSDIQBzPOyxNTAOCYpOBQqtzk
SkhV58oAxHFksZZFEqXyTeS1G3trfDIX3D8vmcpNfltlROhT6aYWSLHQXo+/VpyQEbookmC1WfnC
ekJcKwQZm4hez8qY6imoMw54RCVc2NAMIeNo3yI5zYzRID/UG+q2TrCunmM1R2xVw3ZKTT/k9/SO
B5fWJtrRmE2rj3eEe6WnAL9u/2DVqwraXBiqGgYAd5NIblGmO0i9L/TIL2PD1kDCEfEfyYSLWKkx
FZ4iouhIK1gISwrAyxR87NUF4i44eaPWRVuVvRLHBcMk38m+paDm1GyB1e3hHTWgqQqlJHCpLuJJ
QoVN6tmjcPZN0MtJBOqPi/DvaOy7Hol+yI57QUOX2/MGqAhE8uHPRk0BKKKd6O+B/+qPR5TCS9tt
01QqHdbN24uNwZPxCWqB289z8yHWnQv7uosIe10sPaezRKGuU4yudsARrMdoaefUo+61o6wmMO+l
aqi4KNCueq+x5kdpnx8pIRgoo5Hhgis3/P8OUlY/0EPx5KqyEOe2W364jOBjwqUfczmCT6rIfkBf
phOQg+dJ4fjeODhAGiG4VlbORukR2F+NjXGnLKiv6G+EZZRp8AsSr+6+jMGmQDmPlQlec6YYKvLy
WDEwtvdwMThBz2dDPGNQ56bJNUZ3509QEJL577iVnhJ1zUIe/rWUU5IThQ2xbZe73aHwkWuMifAV
fIGcdciKMiMUtNQHePLrrDTW7Dd7G94ETNc3Tvqo0DiatPYquNsZoADVwv4qO0wf6nEWgu8Yd1NL
1ju14vUvkM5wgKv1ZGeDi5acueh2K92MkuePhRHNzompxFZuaUWYuwoYwMVl8QmTblsNOKQ2Rwe4
rkYmSCUsLq+hj6wKBpaxNoXfzMNKjCXJSvJt5saLtIirwPvJKkCa4ZprSSiX3KD83L8Acmb86nVO
7VTFe9gViffIEh2O3R0uA+T0UL5rucanl37omMWKly6SGl7IglISTinQIxKl+rRbkreUg/tQsg7j
uNP02pdtsqZka1erOxFt8HQeqerrDjaghUAnN2w8HGRxNghWrC8F6+7g+Hxp2c9ovjUMcpgHtFiX
kbqiqN2vUDAKKmyS4dOUbfV2zIpZB1JyJ56p7JqipMKsHKZkb9CnfoKiHRukwH/fX0YewM5/T+w1
i6NNX5X+OwQ17nEOl2vBkzRhEC1C8KeWt3kekK7Wl7gbQHIlPx0LBoo3HDWQfB2otZcbdkqEZrW5
vd9+13Azvt5161S71uCuOl11QDMMz870O4KA0fDTxSFxTYUgLvHJTz0fZ5owkY6vR55PUewU8uBq
NPqdL+rbfWiVvS0pXYSx2tqloI+TdqWBoRv+6/9zE4zOMkTRVSpERsxct28SYD/GxuQVvJJnjI1p
4vm1zvt7BDRMxNBgP3sj3GnZ1UhiShEvTpMQdZ432YkyyQpZJk69MPBVmDy9/QHdN5DkjVbMh8UY
8IwrbavINha+a1cktfPnd6APAPLbv5N5ZsHPWXgE0A9FBRlOgR5o14a2Th7WJwP8cDBZ7+ZEY3v2
xEmciHeW6i8uHkE5XCyg6tiQ/1aC4EvFe6/GqLE71xId3fui0g58t2FBW2aA69hshnu/jVeF10Q7
Q4Uzc/O+ajW46gG4h0deRzqZcSI85o+7czgYxglOBAz9EA2S99d8CWz2ROxlbvGRfyZC71keA9EN
1rTj8MSKlomXikm3cjY/Yg1VpS97Kvm6+G9hSvz97AShkirWOH0RBOHnKQIxNQ+cu45Git7qZ0TZ
du96x4xrtIcn97O+2pbo+StMenvXm1KWALGfMmsY6dXVDWNmYsnO/6JUiopOpgIcVYjmp9X1cgKN
ruWzsHnBdWiM5gF7EwulnAdFvmtesEHZZpDYzbdhfg+G9aUOwPBNSR4qnQrXtTOslciJGfAU1L16
wAgvsLxPFtWAWkEcIjaGHSyg/0HZWmq/+lQaAQ9nNX5qwTJYUKQt6BMjIHLfIe8vcNvWXjpaZVTV
XpAhWAsGk694R83JO1SeaEXzzmMJW0Mpfs5H+9zvFzgjjaVTbxVDmNxbk12DjXVt5gb6PSBlSL0M
qL3xo2pU83ZNqsZVDwZGE7zHnrmSEri+xBMtwkCQQfLEF3Oxb3QUMv+iQq90u2c8sD7ecuJUiU0W
mnHbhkID1uPEwc2gYgn6rapJc8jm+8uoX2sl879tTWMyGzIRsWCvVKMtZsMgGHIkt9ssG8vay6qN
Wkwr149N6QiMe9pDVGnHuyTlhM3v/4AvQuxx/Lo8lEtru5/tT2kTmKG2OhzkhsREXzXOhxDnz0yG
mx0ik154f4xmi7jnpOI/7y8HUyiowyYEFg7lnNZZKvMuaumE7xOqiscvj31grrXQq28wAsbGJxGD
a5zKNLXD/hKEYZKXqorbxygBYsT7caOvbBShl9nLhE3OFFk9xb1gv+N6rAIWBijMXhVNNQYys+WZ
wVK2TcEjOL9tMLmzQzOo+sYBAL26Xym0rTPy86sKABEkIKt+rq/uzWxdKEpAzoW60z8z99sqlx9z
X6e3hHkVEa9Vnx3EttSYj0cZp69ra8h9JIcltXOBp7Fhz1CfUj9LGmmOpN9HEIXcK5Jzfwvo+6D+
J3KXyDtBpgMLI7FuyhNRvjRtxgt8faDgvrQpFoZ7eXYe6fpe9dzwjp37C2QTAR45v8DnNTbfnVm3
81BYKHpaQNwFJKv0gy6ylDzyNEVxa4RyHAWBQwAPhvF/cu06OEJuk/C8vZ27iyNdSh57wAyMSKuR
UrAPp/gCYwxakqVcji6yBhBze9HeDbumcOQIjTBdVWyDrcCDdiHjgFSpsErpkvh0XJr1LVlPmKDa
2hUeMKbOp6ZKk5DIXPTXEhO3WrAiWiwFMC1fOiyzTNR/7uptg2Tt0KjCKfR9wDOsJOg4K+Y9S61m
6PTlBBIv0hRHpqYm8vJi4Xxa237MH7kQFLXJK6KfZeGbPyl7VruQ4ThzC3tNdo0ywRG0VspYDzxL
iBGAtlGp0p3ITYLJGsBDdgJ9PY7cl6jzgHnQCs2Doz2r8zV/9ULdjLaKo0ix4DnMi6BrKQBS9OqF
4Fynxk/DiZButPkTc+5rgVMiTAQg8RrakIOBf9NEe7krjBJ0D8X5e1y17Cb7+eyTrwA/VDlW9QXR
37YWe/aO/IBMiStMza6PAkBnOHKgIkEsLHJCJGJ9KaxcfU6Y3VsCfesx6CJ3B0g4RQoaqsIW4XAK
SfZKG8QJnoNbbT3sus4qVgQ69ibhzAp/AY9VLkN83xsvG2nyxiE1RVxDkjGeuowSgup8D5CXjGSI
PT0WaNQoN52kJVMQcEI7MNuJ+cWZqvDwPcVunqpX57vpLwsL3Oamk9p/JQZyKxSBIaLej4/wxib5
OftH21qUjG0+ySwv9q/pR8vXVYQCq5JTgHJkWNV3k1NmRRx6jhC919UwuQQx3fNGoE2XSO0HqW7P
SWEug3/J6vcrdnoev96TnnCRy2JdsULP+a1WH9/yhehXkPCDYg/HC3+/CFiR+wwBIduUDoPSIWVi
83E2Bk1ntrXoOxP6YE80NBH54MsZ55aWgxywS2FP3TFVQ0MB56E9tSkvNaUfOqBSUUwV2PkS0CWB
zPj6T/tuzfPuweXKEU/VciBNajj0LeqnCHdYX5bbYxExSjpN7xerIX9s/1q/2joE8xvTHIbifUKk
/RGzw8FhtkDnI6ACD5BlEHeAs/xHQvrEHxFnp/mf3qL5Fp9BcRlPCt/zZC/dNR52/WSGA9f4/qf5
fQYxRyU5xc5SC7P7r5ofORGR4no9oNX9EOzE8/nM9F58OxlgZpx0kFCEt6ChJpFMksi2/kxF+BqC
ghNmRFeswLmLBGYsK6keGAbxF319sK5CrAr9OhR1Ljp/JLwTHRJFPLPf+JXqwk6EGTzsQsm85FDd
gMk99O2cycAEsDCgXsr//me+a6ovBdBcNzEl6BLrgNrmrcxTvofySoLAE5ovPHSu34uZWJLLeZEv
pJ+e8QSRh9KfLgbIB2bU/nhe28t8PzeTd+1Q8Phg/6Re/LGR/jiK5axJy2WvFpV7AUkMUqxZptA/
e2+f7QpWvOkat2gxoz8Knk+s4Gz0s58x6GHHQCxQop7DcLwKM+jEylgS9EhZl48UHdB2NnU4E7QM
G4izfuQqe7Xkhzwm1xIzA6S2+ivwdMnisS/Rwlx0PCtZ1NFwgcCRxDEdo6vttsqCUi2AvBEYHzz2
f5IlV9VhxwortcmJd0p8Bv+PqN/VABfEfc651Oxa3El1ySUldNFVqRHpXtVdvkFziJPTU2bEVYD8
h/jDWkAplvR0YTfeM3Ipow7oINqB49ANtPiXFbQJuMHmfM52Oz5Fhp6/uoiq3rkb20fZLOl6yvFb
94p8Eu5NrxIWbqu/Rf4mIeyXLgMctBW75mvRBcIGhywv3eyRXdCsWjmKGFwNf1SNk8FLto2yf/G6
XLPjGzPbs24A23VFoRRQ92Xf/45lxb66APrQznvrIXFhlidG9zwX5bwVYTqw1DFrZnUHYBvnisOK
FZplJ0O+2QCUpwcy6VrvszW6NU2W8OkyKQnVsOB1F3TBi+mHez0D+A8bnYc3b44ExeRJB/Zxwjwr
Y1UxfPF/mGR1mR8rn8q8cO/oBH8VmSb2K5qYVspF3HHWSIYXk0AjfL5ASYh/169d7zEj/OUzIWBv
YYIpEj9HgsGXp8L2IMjTmUz7FspCuHoX09m/wvCEsUwAfFUnsjvXBaKe9v3/L0TEFdYCQ7PuP4yl
1E/uxPmN0JiI/18vpHBVs1xu9DdzsCebor9ub9g77BCSdA2O1sAKaz6vnnW0OxjMOh6oyVMgT6sx
3PWIRBgznoiVbbKcv7fev8qVd+d8vuKkZiing6+uTmlmbbNasNaWf8FHGdw531GkhKZE3AkaKJlY
f5Dp81w+By+TkYXg6vSwnYAFOTZ7JMpD1Peo5JyogEhuX+0lNaJqrBNQzJdb7bVXNGvg0etG3KPA
P1+xlFWqsR85V19AUazbkm2fWRGDTU42FLtCrdoxn7gUL7Q8uD9Bvc59yqI0DsYoWU2x89/aAxQ1
VzvPtdq8RkmngEFs7F3u2gJsr27CUtD4mALs8WqrLPlPM7QztBYwzwSye8qcgSgceAy9UpZAwTuQ
OVwO4sdF0MrERga2qRUxJgVkm6qyVJQf0iBxlOgU1LBJ2cdcnZviFEti0Hya9O5TYHh5E14+IDEp
2cB49LzvSoR7e6rjd/fIbLcw2I8XxAdQcWEvXeJfj/yAgOSIXSq3JD6veeHZgbQWua0ASy3oQQ/M
/ankZJPBmzbp+BTfm0hcSCpxxkzkZKsq2bivZ5HOB3cMIGsInwA4jpDshVvTX7cFrIYK8bYPjrkB
3eqsaZKIvdYL144VqEkPQjWs4/cCWLYwxaKv4TbnEO9e8ggnm65KZnaxI3IStoOpHbdE0PVl9+9B
xQX2WRqJlVJtorYCRuZs1Ppmf8K0W4Zq66Rkr1Dsve/NVA3ZjMqkPlzOrGvGiBqk1zA9hR3Vq31H
NBLCDW/Zubbj7MU0LRXSpTOa/XqpqhEYzExEpgEch523u3/rsxEc3BUsyAms0QZqC2jpQK4Q8AYe
BOayHAs6D9yMF4XZwXlMdExtl6NLMh+8Xo0S5XmtyzcvUZA4VqB5r4PZACq6bqrkDZFS5fhIA8tz
CiIvsQbb86JMufpHpmApJMGE1yDTj3wd82SRe2i0FEbg6pshLPgRisYwh9hsofZl0s7Pt6ddW4+n
ZzhA8nkfuU58SYBIrV5TmNemwV2MYOESLR/qN2CMunNBquVMDPqbavcuiwwsCR5H5izCU33N8uCS
z5ruVuk2C3rHKSERZYw7t1uzA8VElkS8gF6xm1TkFvUAz9Nrc33eSiJ2OgL7fuoKIgZIwI1OGsq5
O483rAdWIHxosvK+36f6pwIQVs67FrjqkSwUu5t5fniFVOUEyLGTKyuk80iFTs3n+OkHhheVTZlu
1thORJpajJvuY1SoctiJu7Ez7gIeBm52xOGJUsNZC52swWgoS3sRfbyu2B8djxiX76Awl4pqVe+G
hubeer+2zRG15qGG/jsW/9pnQntpXF6kCKdN42yBr5J1hwHYXz1llQpZPwsgJIjRT/1YheqopW30
ytrd5GmdOoq0eDY7R30UzuDtEyWPZDrv95/42hgVJOFR2KU4PRlS9LzYUJK4dyZnvIEKYP27VeLy
XjXE3DQxuuG2ZtOCHfFh7uidQ8OZoYT1WkuW2DJF6HFmbOt4TblpG60Hc8iJ8I3zslcQjliEYhrZ
I1tnThyeD8jHgcWEFM9RTbopENbyEYTXxJ8oF7vlKUL5ihZSxS8aFC9RrUQszJgr/fbwMdkglc3w
cMzD2qqn8fuieARPaZ9KOWOFSzX9lOSTNo/MZpp3GKSuJ+FKt34IOmk6bT8GET93+jSCBSHmlSqk
5MZ8wzOFdTT+cdt1DFClIl1IkUH8V8ibIwYPYY7yw8IonWol9SeKDNaDMScDgbkcXa31mpsw3EyM
zgJceGIDbgaB4AdzD4Qd77a0U34E6YKv1AXjIBOdUTMSOFFBFTpRaYsJ3y51K/hIGXkoEsNvmjCY
8gAUtn0NzA7Q4cSlqUPJiHFBzd4uKuCKMxlvkrWk/3IpWNrPRmf8kmw0lUIC2BMzWGBpbUHgGDnn
C4QaIzjAhzlw29/bxK4PF/38hrWuLGTW7EPKCyjnZ88MPNsgpkSa5xCGIh5/z0UqGQU9eKN6/QpW
DUwG456H/TK6+Fnc/3OlT94pKek9APRvf4eBC6t6slz0Cy9KfYHOv2RSIWi272x14zKmKXavTrYg
8LfYOYhsyOp/aU53Y5riVdyOszB9xCrjuQHTxJj2aETxi5/he7gXtFdfevuWJ1HAw0+SsGAuzS6M
dzBhOBkuAfjqurSmL9nnbRQV1y+2K4hO7M1nVY3d3HZnzI1ikHv8p9089i0e88PMcM91ihapatRJ
+djhbBzIxroyvzQHBtnqHkokNkcAfgEhQNMby7mg1ajNPVLidSrobNm4+V26HMp+ssdYYNJh2rqK
4ZBEoljLSYi135QRcIH4tD6sxawoV64C+Q6ay6k1pyay4PoL/kREQhAdgU/4XetkuRUeU8HUTR3O
Cq5N9vbampzBh8hSy6C6uLTT7kAUCWF53fBZbKdtx/cdroieavBWFwX0yA7hS2WPAlKhvCOaO1BQ
Ut7OIsmX2A7VTi9OPEkUWkWWDgXPViLl/E4RpQiI1E8wtzFQo1l58n8CbOp0wcMVbp90HmyG4j0s
OAKfvpAALOWYr89a+ikUXbjzHBUzRK5NohYkI9ow9bvXAQli7Um6yIT7GyEcy0M0uOZo71liaDaQ
mRjW5qEB8AXhL2LPYv38467ZM/xTvkCo1d+UV7KZScjnaKZzE5K43IiYH7+SSctjUANpwEqgBhw+
68xE4634qzgeljW9UWpOpjnXe6pXmzXYL5+yzCzg8aDvTxFvtTD/pe5rMUho0VhS9XaPs/CB4S1X
rGyE1RMNIkqUAkY+naN4AM0Su/ngmh8iilqxGvqA0dcw0vrZkGNlqTIdKZLmCWEz+WLb7zWwV+iC
2Ec/QuKiNyRvmUyFJT2sWCKUAW+gqpAhZFSnRjphI6ZN7hvZ9zG9LPLGEC6Dd6PGroQlzqUXZ2zZ
E2qynRPK9sv/f4waXpMzY7SJwa4ur6az3jeYvmM2s+OVT58JZLy5//CsNcOT1RUPYsCH2Nnd+PMd
6APIrEEwJYDG2Em1oatwKlhdyRXwAn81Vov08m1CXLLJDFDM4ZbZqb9IN2nJ1UBFobQ+SVYZITKf
RzYN3l1vfmwyqyRuytuRgUq6OjuAdB10hJYK10yDIg60ZuvrQv1tNheryfGVR/KYtEYWbwIIXfSx
Tw7j+QvCjFVSJMNsyrJzBbd+a9/FGTsXPrg14SF3d/BdDmRGGnUVIqEvHp44RZtP5dOhznXTWv82
5UU9yMoyjuzUoogsV9V2X6urp4XNRgTf/O3P+EVz9S3MbDyqEoC8L3f4n8nn32RKJ1xXGbFe+xe4
7hEzoJiw25KgSHprsf8t97EuQ+81EOqBMIizL1osA3VQ4i8cq7jGMXGlvyaTH9aDbp7Z84PO3JOm
+mPGQLGMIAOFRwe1mUwdK5cnIqdJqasw/3FuBOBYiKvnxkUuS7BD9D9mo7Ld81p6VKUFJKKCdKmr
/dknhHSl5/NBI8HnXxjfIkP0xZ3dEw8iWdiKHsijcbalFnsfdSKpY3PwCvrYIER1fDIGpaP2FuJf
8Ea/t/7O2u/SPwovN8XsT7i/EmCi6+xTkS9I/TInK3Ns08367Y+hWyAEcdIEIyrqC7rOp8vJ3zND
iVu2iE6eKxjKQkzV4NaNiBrrQ+wCiTX9x68lchzaVksw7zG1ZK0m8n+mFarzn4Dj1d+gHLzzk5uO
EibLgin2s35PaEFWpMg6FsOZqZFBkhu9prsEwNh+nhvnSDBYy1xXjCGJ9GDlVGSe41Of1+v2LLMu
LSLjQhnusTrOtZGOfxWywNoTOrpd0nfe4v1+HoIecP/aL+FtA5lgA0F4F5RtpKQDirkmF1gkSJ0G
hF/z4P94yeD96W0CWVXw5pyZSAL4PAcBTvdMbhwmqkGg47M98cWZB1EZS6TMe5PXuq9ligtNbi+W
WsQKrUUZcuLkCv0Sh3GSI7jaHIs2Tn2uNtNvW0bBgfIhJfcFXzWHvY9xaP5VDFeLRpUQ8BEHzJUN
1uTb8onuoTW4OuwaqutFH9vvorDQJOFNMOWy1Cd+1GE34M7+3zjgBwqP72D/u5r5Z/BpTlg2SkLD
xnejgOBt9bA7JsF4R4d6+/2roQxCHqkrmKAGkaFbtjox3BzOkC0uPlBQ1P7Gb6b6F3mxn830+foD
2dM1c+TCpz3Br5cyM/z7j3hxO52IpuPnrfVOy50c+dV+HdjaBzAbzdqBvagLkKgmAU3WOXoKYnYm
9XW/Lhq6aKG15jq8t5UqHAAKarG/7dd9UO/IAtQ1z/3xn8RxZfz8ByRG3/7d0cDlx2LtBFm5oNiC
vt6ubH3Px0qMxIirhquvxqYebwjpBgv1Bn4iOS9YripdFaUuD1z7bd6T1k8HSBTZlIlKSA/XEX+J
CzAj/cwhOCxzGYLBzVRdnsqMbtMaaHYNid0+MkSyouAs4pNSfc7ZyWY6UYM39RtGPEyPmjAKMVzG
ZB4gkETeGkU0VlK5WVgBdxd4wMX+ACiyyqd2Fan2jaC+FeRONNpQeEguEb2gFinbs1p4FGKdf2Xg
cAs6DnK0ZNxpVzlfVPp38M4OMj8H+Ujg9RIo15z5WBJDNs8EDfKh3Gtx0nVprd8I4mcP5BY5jx/g
YPPlu1XLeJ+aFaRaOt+ui7/aLijmkLmTfyomVXOlG1GS0z82xZEelGHWUrCyQplPjhogge+R9K6E
opstN53JkTvCwCmTFqDOaw66ctbJALD6h/7agx0W8aMaRpB6mLVV+3hBehCVE6kmgBntC1mP8aXA
YMjFk3O3RaaP3jp18jsaW3lGqk2+pvopb3RhGDF/tQrLYZ4p52zEURjhvS6+aQxwZpXNe8+Elx33
au5bJfpu7BLKfSTOwpDtIygbLxfRAOt5MN1lPN3NDAGPbCrP9pWhbloWk8Ytl5sufV2B1pVF1UdV
yEZUsHNBoFVXk1grGR8W/dk4aRMAhiDmOd0rN13BBJV9w9qWGg8WazwLhRc77VdQMD64qZY3KLAx
uRKhfRy6mClS1FSyq6eruESiD9q/0kMoPaveBCbhwN6YzSKUypmZYbiYHs9h2yzYHKbNxGq4Ffmk
Dbmk2kPpvxYdfj8tH/+j5rABHuIkFpA5rrLxUFz/Sff3NFAoG23/kYx3vOvKFHsk40MdQZaJyizx
08wzlzlyCVxy6ilKIJh/TqScwFS1fiexz8VH+QTHIE7LlMrak3HHOH4WKxwB41Tcy3JoDVmPf24o
MC37jlSO5WujGWALwvhsYCpQt05dwIfPIK0zHUVzNOd5cIvZ/7yLoctckyVg03UVNZaKnBjXriL1
pDu1deDbUYcK2tHbSmNUvFro9704AbnrAc2bDBLZNff/L3upV47U+CgC0p2+LGqJmkRUHI6Z6Sm1
6lvu0zpTuvYODLeSJfjgDWtRwSDaIzhtw8xMwGSe1MYUufZmbkdcm/Dknuw+SPU0dNXoOmQFOfu/
1kRnFROV7tt9ANSa1NIS7Obu4asPj76NRbXSirQBtRSemVCWZ3909gCb6gHUXUoCsguOxABX5PpB
T1SsuZBHYaqHkh1Vu7qMm0le8UP/o+8gxkQHOBJlYVoNxU13X90osOC1l2RlynvQkRgWQU+OhDgc
JO0k7F5h5Clltv+UU4kg7aca+4WvlTSMqKX96sfSpoY7AotrPauCYhGpsVILeDprD/lLXUIicjvH
780qodAzwt//Si1ZB2/vfD/lb5aGdKFOi9JL637g/bjiDF+4QQicV8UFErS/V0dQP+QEBVJwNAaA
HuaCoPqC3WAqfbYLyS7Wkuoa4eQ6ux/q/5dTQ65wMkDJJwlyYN5lEv0Ie44LE9HjVnyMUTvjQPMu
aojCE1Pkd4PWBA7DaUcG4FbXlaO1eARhfVVLqaNFVf+GNPkxjG6w+J1TEj67ullRzpsfz26U6kEQ
Den1xvmZ/Gcu8csVp13YXg72YhIxPuBPn0d6gJRfwqqU9ualWJH24nBs7QSda//MoFW6Kq9lz1pt
dGnAd1dzxit8su7AZ9PGzszg1POQQLbPKsi28wi1x0hSlsBqrnTYs3+5cu+5yXiErL47No5j7n4C
FV2aGmmIQ0cbKIo1DAj7r8YB/kpJBU1GFg8M4y94+Odn4xa2wQWEJopqdSY7QGS/9tHIi3y0ajyV
zXPvzyOjVaWsvUMZmsM7OYtLFscNqCTsv3k0kNEtiK9dtiG11Rp8C5V2kUS4Jld6VylgC8MkCywT
3mJFI45+EOPyWmTy0GI1bb5FtCJGrYFUqoPfj4FxXMbyz2YFDxau+caDcYGk1/vayKgubUjkCcS9
j7abS3isW1miYV+KA2k4TTvyZPo8RIq1VoepliTlgj9E0GqrH6Rhl6EYcesjiyRAkSBNByeMY1aq
IJlz02EbOLlaY/zvgdGvle3vVEJY+kZGYSLLa5uQLGWA8Fmf9i5qos1oK3jc+VWRTZ2L9EiBABoq
CEJ+RPWd8cqg7ir/quhPNGlbfoijd/gkwDSCSkD9SpK/NCIMhbyGr6K53cGqktiXYePq1hcG8O++
zA6KN+C25gcvj1WYeQTZejFLZ5EsrgKb2GYMqDGJ9dwEr2vC3zO0KFHnS6gKO6MhfoBfdKVQPKGM
g3CmHH5rdkkeoMsXbOs+b6VijqAy2WZwGXUl39h9klOYLums94b4cFaiKKKOO8vAXknl1iEDhOE/
YJbABbZzEfbRZTA1Ynz/HUbmcdXo0TIeA3lPos7NZuCS18w6669GYfDu4E2OovqabbK3oukPRGmA
NYmP9nzz6vBviwYDzSOb5bokS1R0FnUlpaKfU3zrKBRvrOV4Efp3GbPEdGD8Bap9zKN/k6u6Fqap
DPp6uvDvXTEXJl0OKZzyqVkOYsgm4fLlYof1bqNYzmK4myfyPknjxOYrVYW2nsxbD+QajmQJWRUs
Qw5hdleJt9jvW5Jx0sTNkDyyGxyzvn5RgZU/1jsVCJ/gTVUr3VACT3Qta8kFQJAi5696Acm03EcW
Db5ZYHIFaBbTd/Kb0z5SaNMgY+zggqYc+kW6HOpPneH4HzaVHcN0IQOUxdcXxWuDZZiSgPVNaEHd
dBFJTWNfRBide7xytZ5l1WerC4Vrkr/CDxnfc9HaCb5q1U5rViUK8B/T+Ng/0OgEW1jr+ySgCCGN
z0WL/9ldZ+Q6hkjGTgh6wbl5LckzZVqlEkOboQMvFmDFBNQHb4rAK6eOLeO1HXyP6ROShlafOE/e
NNv/4NAw4wpXfXmZQiYs0Gxz7Afvq6sP+Zfx9Ud0Dme9sEP0KemxLQymBrUntvohzNklvl3s9BKE
NEkLNYgk4VepGlNrI7A+yqTil3H/NpuLvQjN52kcC8jB+nglLdHahgo2E1znqDfCJx76R8droHLQ
0QCwZNqL97+PangPDk42lVlbmT1BuCTapyPLd0DUzU51yL8O7fyOSJcYPMWv9cKcKcJ+nfxmOk7v
Bp+RVm5qdGMZ+KJGlzVpUIgZQiQorGEFY1sxcg4zYVW7VjO1a7kCidJPCNuGd2De0zKoe4d620wy
A573VRurnP3okHAvfMhfaHMwFmwpJK5mmlLsP2CZnilKBeGfBk4fZBiQ/d+SZITm8me1WUd0WHT0
sI0XiOV2KPSgZLtiMFqpNoUhy1a9SEr84zv6loLYbIXx3NZh9X+kprItVOvmltsb7rw9MSCeWVFb
JHBoULcvxpCBzUbtb+O72APY8jwgRAiSIy9c5dG8dFub+Ss2X67xgjTbVV/E9cLLpLDvv/gZMjva
8LWIDuk8xTQV+Xeq34WXM1dyri/svWL4qLuS9QHwLqg+fHv9SfAFYYzTsj1h0TN1zrD2breHZgNc
4x7u6+1pFTzkcMTkBEFpoCXBq1BpmcTl9veVNeuO7lWwiazL/XeRXVQgHc2fdnorGmGxHxpVbRln
G5ENF8twY03isyiWWceevTDwaBgF0U2X/2AVOUdsNhSZhFxFOy/MBU+E2TjHzbFATyFIqBQri4Pf
QgVastnawpjaUlJCqTeTowJT9y9KI0byf5kwdYVXkjU9oUln1JytnU4f+Eu7/J6yGy4QP1ABkN4T
XYMht6GKtS/CCKZonAOyouxxblEobtFfpbdL408/rnjfDWpwYim/h39m6GTczu2/dLaVVKekMS+T
GHbZxHqBYW0I0SgTnP+tV23xBPk3BcMjOXkdGlsbJZ5XrLlAdtUmwjn+N+SKYsTNuBqMCnncWn/V
r36yQiQqfEYMTYZtQIZgWPqFg2FelbuiU0U4NJYfZYxIlsKd9sjCDE7vtVIPL9hdt0wwpG4+A3Ru
ngrVLK7Od2gQEQV1wDxOm3LdO6z/tHukFQJHCzxGjxM/Jthi1jc3RqrRDBGmIAfYWg5nJJmC8zJR
DMETbEneHmRFV11Lk7Gkic6HI4ugFIDIce3zcD8F7Bm1xJR+a2vUotBi+K4WoEMdl+McO72EwSCk
+49mpLBiZ3TupGN9B+P/yjk38fjxniPr2dqr9fL9VnWpdzPQh4WosbSysZvG7ltRg+fe+6dAiIMA
e7jer82Yh9tnZmHFebvOuqfKpUUoqlDYlcYZxGxR148VKiOWlNjApTk8cjMMd/dJEbWVpBQQyi4W
WbZ/eSFmao7zXwzqGZ/WF8K+I7Yb4NsOjVkzdcYPAtLwb1UcDHaTuJwD8Xsv7CPEUfj+OjaHUvz7
oYeHr12+Gp3F7Dc1Z01O/Djlt24SRt96c+UtDzmE3w8TAk8A8LwjGJVxm8OaGYJmoxB0lXWLDaSp
eU6FCPOJpmSoTZJLs8gt170ZcAEUrQqAvTYfHLer3jPGDPqchg+Or/xHChjUJBtgmcVhwL6MexaM
E6vubH3lSZsERsjrlQlSPuQN20ulk30yEdM3tkRkp80B4QRb2KyHTtUtnnhownHpeRWt8e5qbTSg
tOBHt3Ggp8grBcg3MUz4aGBmL6VdZhG65MkbDyB9v51bSbTHSnFOJHCrl0HpvB1hym+0t11xz56+
C9fUNxlE5E3dGe1vSGCuCaKggG7JlUfpX/sUNfRXkf5tICIIykp7UY2ZVzQ91BZw2l7yBI6QH1rw
ZWvFuPFtWXFm8sN6AE4PCESAkefS+HEjpBehJ2ioJUdDtaUGmkPViir1lraNuWddCOCZOhtaNCQO
3OcAnxncPGVbXfA6vysS0NOsGuDh5a4wOoibYEAodYF0hvfmlXq+YwFsknrTa6AuQuSIzS5lqwMW
MTkeV5rYJ1Qp1wJ12208qqg9vNsagf+RD58JdBYMD5w6dHnjUkz2tEeyLefq5dFuvHPRkIJ8Zz4T
9RoWBKKpf6LyzEDRp4o9Zn8B0cuDOXgPzvyI69S2F9PIsU4pbokvEMOnMlD/M1lbK2Q7G0Y2VJ5f
l8b0Bv3ZzhlWX11D7+5f/ntxLRxlrugUwl2WcCiC5Mk8o5S9OgOWPc5LFLBw+tzoB+H2dr0j5Dhf
0Fd8bmjcNomTthtF327Gu6Q68VBRDGN451ZUZF6rc3Tf7WitigL/0AF6wGEjDb6c4kb1mm+TuEyo
wt/zvV4SvFjAd4WMBocC1dmKVZPWikfcDc8ZXdVNvPv+Vx57B3kSAEZjlkDR4Y3F+GUYdtQ/On/8
FPPf1QwxMhXxf2pnfdanG30NGnmueyOMbKR9Ing+RLJ4CIkPrqYmeE0mzObzZTIvlVS0lpJDvrLQ
fQ6EQFLpeK97qvMWbqVu2HiFjX+Hd8QhrkKZWEtBe2yjhqoWgRaupRtEN8HQjhRluY2wVBOMdqk+
O8sCrkM6PZTWBUi4Nwg0C0ldOXAK1HR5cK39zHlug7JktnBezv315mC/Il4VygRHTpobIWG785fL
qjudbxsD2PnIEyyQWaYfkAHWxFvrqtzRFR4lp/UCHSa9rretlxbMjR1KI33ZeeCjDiM32PNL33VJ
iqmdgNPSTs2In0ZALMZu0RALVcceYvt1DXK372vamOYlm5SSwoTl3Lg9XWoQ9w3/RD2T+jExNqfD
yNVKQVJzINMRacObet8iucpmwzMPO7fH7FvmWLabNBDgaCX5DQfu2QI4jgJdsgiRW9ajMNbowGOk
XhlAZ8XDv34Cn8JCBICCjaw3XCyFxSFW5WMpJaNBUkFgtKMtuP1SRvkQwe/BHC37fmct14kK/x9s
3VRngTRXLKdzLFKpE5Dbh7n1pTJ2YgyqCn0w36ucGaoM4Ocz59FJp3hq1SPu7j+rsFAND3VHO2dn
uvLiHe5BmsZNtl7e0mQO25fBmxXVpaeQ18d9PQJZCOIHF2roSM1gwh5UOwaZmXmTQC6iKkP/Sg7S
izo4sqorlZVfLKb7fAmpWUkMrai0kysTK4n0dJ7cYhLM2btSrHM3LH30yUKhkYxClSgrChCaaXRW
K9g/1bTk4TeLEuy1JJErgsvhrfpTRJcE0CvrrYvqPrihYVOys2w4auR5FB9g+uYIHFC46j2FtQBa
PN5Ook954kRBmyps/yGmLxe2hB0QUU+DB9Tf5wHCcz5/onyU6XF8M+iHpxV3ZMr2sWotoU/TLFpN
Bz6QTCnwGFWx3oC7EfTr4Z9gMOyRPlM5DgHyVeuNNca+FxhrYbRLuJpsS7+DxnlReGrikU4A4SBw
AmvCNksG/e2WfIOeKt7L7AaQ96v2F/TyYHWPyvTYE0MNCbG+9ACPto0tXqijzy3Ihwu8gKQ7/Ngs
4G5dG8ErPVuWqMpVuasDmVhBZPHiGB8YQzcU9NtlIizvhJRl2re98V0yazZWl2VkkCVcYAfmEt7S
ZD04E+saLHIWazMb32d9YWn2Clqxoo+BHdGRZC5//xvN7BpqEEzO4VO9KhQnBjV1DvMJtyVxEEBr
zZmTsPF515AVwPRv6cPCCuVovwYhu1iFggrIgyeUpIZxCTE6i2+l8wXHmxLJrr55VdJnmclvHaG2
NuyoEOSFWaxSWbMQ3IX1CdiyApTo2KucpqieDJZ1W+c777JqjAnTv8MHRTS2n/9v+bP/3e/T0p5v
y3RvAQUUG81NizHeU9IahElPcelTGFnRu60nteFWkEN2x245EdrTHqN3X1EPnpHkhnqE7mYBnGWs
eXUGoc9Dw8Ikv4OgmXTi5WAkGmoG1UB2zhurud4hbzsetRY1eUsImKg/QDD0Qfi8QP5Jb7aGavgC
g46+ly3lw/eHQ0h5hQBFTC7YAVLj8/aacqO276ND3fTD2l5v4DYDO/i3VuemiIK2rsCvRMVLnVIL
9uAmIZntGBie+pN8WvdlYanls2JPsOj4NMveQa1F5XDOaJyCCehxNRnyntLMI9A3UgE84pp/mPA5
KykuXB6y/eBPYH71PW3YbDbsNfYQHDxGiml1d3R85iPKkUFK7osN18fBI037uYhrxaqittzwvG8r
qDJefJO3iY0IR7m1V0aQ0YyXH3qmrwPjTxypEbiEpUDMM29Fz77CPhQOgHf3XzAs/pUY7Hezk2mJ
B4Noa5GzuDhwl85l5czXwKu82mZ+xLkxrg+NaHbVWLkICHtGU4TB83jIt2lLgyGBB4wAtQLv8bQO
cop2XsEIiu++q2XcJ+7WZbgzISNQsLVDkMQXL95EkbZKUdqKYuMEyqfy1M5ma9tOogLKTGsQtjSt
BDFoGXG+NBj+78ckRUOmdEdnCDtfIfuNqFTfcnZ9FWEMw0GmpJF4WsfBZwCVIUDjwKLzuCoJlaDx
BTxVnVAlcihm4zBSZaG/bhtOHroBDI5iIB75OaDlhtrPl4JrORT4uCq4ypt6QRFLjQkqcE5Us151
FyB5zE7FcGk9V90G/f7VGroKG6aXEZiqbKs8qPdhxLDt4eFxxNMnGhe5CKtGjBSWB8qHqRZWRP5K
mtFxSW+TtJlpSVAs2TaaoJu601rRltgdw8vAa8boVk+0tRFBRMYnPKGHUCRMwF1y7SZncEq5mz6I
u5qhHLL0fkpfO0dUCsZ7hfIyzg5b/GtNNmHK+7+DPJS+wXTA/G2vy7ZimklnA63ViLHoM6aNzQyJ
FFwlhWe3tnKLca2+Nd/qXwQv73ydskibpBYMbZaHXqbcrJUyYaMXyZotLCRxpyOlikmsuf6lirz4
tzQqUZbZXEz2AUdedoXLjO/yrN26RY2Zm/RAbkSLX+bMTjebK1aGzssml5AvRZr6URU+iEdUA1dC
hqvQpyHCQvXGSPEOLtdCaJrzIjgkpwz6M8PjM8cL3ACszWHVZptrw4njRcUYaAfdpkbSoT4qG1d8
O7vr0ckGpoMBi3AdMFEhuIgFicKTJYAVy7Og1TVHxw3LrqOvJtT/McidatKvsgAxknVr45UKbk4+
c6/mSJThrx6h/wEwYDOsr7+Y937nQJp29WOBEByBfFbNyIFxMZZXRsfqIA5c7a2UyAcizUk0jRLx
zHPSF2C52Q4f4nHOHiFVz1am2c4CdztD84hUY3Guk1dUIdsTkXFL8L5ziCh1BDN+1iIIL4Bmlqnd
aFPF/W8AolzzMDJswmx+NLSe/HDZXGxoa8Xw/UCGYZ+USYl7i5LXFdxUYRDQDqaojKsj8/LmyZ1m
H2Q9HRgrtYrQv9M61oUN9tYAptUN1B2HMqHBa7E1XZ+rPbxWZqc6NHQQtpy1uQ6Ua4hA7EMCjfe/
7PID2HYG9GGgDFVRIwlwc5TJeXV0K1eLe4EebCQfukVUq9uxDQT7xvXQHj9Oprtqgj8PXsJ+0C8h
s3ot/gqbDH2o6Y2yk/nKBooE1XaHrphxrmxCkGduqUUvT7tKUKgwH4ZPTMA+Tp4aqLEc1euJypXU
hA0d/Rja208UT0V9vgcQGnm3Fi1LLRYKUK0pCOFWiTlJHj7AUQ1LmEKagPkL4PQnqwcJ5omZvxML
WvKsHgouiW/Bs2+AfRXhVAZndIe6XvG8NtE+vQkGLY5M8E+im9mXgWHikI3FvTbP+VfWiUoh1uCs
BfmZe/Zi+NDIIohsz9uMyX/7K6oyhIVI9rtaIaJ/1fSGB/fy/wp5Ba3jm2MtQoyLLy3TRzYjrljO
TDC2x3JXjziO/yk874OQG6fF2Iz1Ei8+mg1V3U9m4iW3suWyqhLVKN0uPNW6ilnQB83sPfD6koKi
cchC8cwvfjHdfdjbZ+gNc72eSjQQ1kdGlTmhQqZ7sEVs9f4WHMOePnDEounlCzCjxMiqArVCXDEK
AF4H8i3kSxnq4G2YtVZfwcu+Q3SpctPmaov4AjGWr1K2oGMWDDIT3jmHzqnmws1wnC3cFqlwW2PA
MCbpQi9vu2G8WEBDP7/iVpRE6en5ijFke9Jj7MMZ5bczAzksJEplNvqEH7PBst8NaRoHtYw4wYnO
QMjEWXYerQK+wmcYw+2De0MIYbnroY/fXkZI5vfWAlTq2nKCE/VSo8dS8HifCSQIyIY4Q458EnkW
qgbvoRz5egnmzPPlbvCtU7v7WX7EZZvS2TX3wgHZ7AftCNgNK5MW+z2QVZ/bfCB16avf0kJhx5T9
oUalqu/n6W1d8jYQkaw8T5wsaJYMHpRsTGiuP0yiyui7JhF3XKa3ExYxiB3NJn2xTXOiJ/6h1TbM
EMx9jYLoea7Veb94r2JC0DhfVMBAoMMSx/wcEHYdmKvXSy8m0f45H0XfmdaJCexRudQ/4yGCbwqo
iEKQZwW+hJjXAC6fbeo6he2lU2+OK5k33n4yk2iHC+O120JtOgPKMfZpBziL87B6MkMxgn9HH0Jm
xmwHEnBKBU1TffNx9l3c6zlkAVwcqAayO+x43QIU463Ng+vHXYzIKLdLTw7hv3ChnOhCv9qSSz9N
9byXmOb36xdBcZwaswWI8uQ3jTt+SKSMx4nk4Z9j+171MXQ78cEfVuC0KC9w45rDezCmIu+hnQK+
L/ZlpQ8KtIqv8OdSAocMcF3dZyMX/g23ddlO/4CH2j4f4ereylTHGYjGK0O2FUuzLLzuEJM6LJFH
q6kqpZiEnOmwhveYWxyADPCTWm43hlQhnZTDAjK6dVrjjTpoXqerLgNfH7+cXL012yIIw2OBOlqF
4crjPeRGmBjhSIKWzZKTpW3SPpMpqdDKfVUAzyVFvAKqLN9IOMOosHrAoOElbK5EgFocAiEH8dVC
yNCjYZwEYd1y9S+UhibjRfLw5YE5FNULAt3p6ywqpaGH/xfbt/eByipuIMhoUcCR77zHM7paUqcd
iNB4iBSYn628gNyIqBx/q9PPBLGdrfs+NBEuE83Bc12GmiFy/rq6pnZ0/97WP+Isl24ObUz42I2i
5+fCR+7WPUR3wKUVaSI5SmOYMeI8uEU0rFyaaZeLVH4euqXlOqckKp9te3NgymrhPilE1222e4hp
+v+Al7oeIRIvXsjLi320A83ZsrKdM5wiUQCupR3mKNdSGX8t9qTt0JI47X7onw3ZRA7I3PNYlsy2
UtuuhSlEy1qlevO9QyQZ+bSp3OmtgBz3V67ytj1q17plyXpFpN0Hl8f+Yh03fFbKgNLoaAXIvpo2
Z7uHJ1KJYsvFnmNzz4GpY+L345dcicNNMAHOz8Yi69/U8Ys6Dnk5DTziP9N1Flcs7cGZSYxnF67v
nd2p/NzAoJ2up/unnEw7UswLyfRq0DoGA02S4qwvBP3744CegvM/aj966HsFzmSdRD75D2eK7ejS
YLOLQuiPBYzTtlwQ4J0AX3UKpb6Y7veW010aK0DCVz9Uxb7e1uedljzAGjYuRmiF7TILjANv8NTt
PkPXJtCeZbmfRSXWjE/uo4KBtgwU5ozeXJqnl0dwfpA+WPejehRpfboi7eQhNNGlwrmVhRb/o8VG
oDXDoEG/KF5HlZnrQ1xfPZFkWwvPyb2n5FM3CnkxQ5OJemE1DWHpDCKPOpzPjus+I/Er7k24li9q
PFMLM7Z+IkxxgSp9v8UaMTumKooJhwBcRJm1ylcVtF+gSkwFy/kKTvw43BN2WJpODOZR0IXiXmu2
ZarmOQrY49WJTDkWl/+WYQq88ez/+e+pUJ4eXEdvOWzf18hhNG82K4UI0kJF/evO3QFIL8ckpMaf
NpebGKhNMdzLGj66ipwhkcxdYvjGB5KYhJbg0rDR3pHwShtFjT0e3fsFznIZ5WvpC3WEByVhf7Y2
LYDiKn/r6/jjyT3a8Z5Z0k4oKKNFNBNWQiln4RiBCqggFMCjZDFZ0upm1dg6Oj7+RHh8aT2lyL+h
WcY1YgC1xN5Vope7Jj4A27ObYM9T46t+GXljbIf3CRrssjE+Ehxkj/2Iy/XykYiP0qj3SP97GtAj
zaKNpE1HHtACkG69WDhQ5VaccHXApc2MvEgf4vtrIDKuBIOYpQGE1USTdKLgD97IE8lvcTXzOykA
yDUrGPy/r5tjrsFNPutDLNHrGDSPXpsxnvcfFDoP/q3BNzxkCGqlKAzOh5RAmGtU/Zu93JHFUBGZ
fCYPFSY6lIMVD6LE1Sm/5iPd7DagNuuWehmkC+sObU72Nn5IRlG5Bq4zbFUMq68DCgJC0nVukqT3
xSuVwQ3mMTjL9FqTOLjR2SCzYDzkMVnHGnLKnJ4P8kzbPbHpgQEnbcR7LGTVGNZ636be1bOXmbDl
1Wa1uNAlnlUvzzUv8E52yG7fCFFC6HGbA4IwcOOD19OY7F1WuoLY4ZUD5I/ja4V29h2oZVyGdap1
ZzxeNlZn7P4xjwV8UziT/6lHrCTqtcK5wMRlBCEpuOKhtC/onm4tGO4ZQM2vXdITumwHEjajdgu8
dr0DpYXRKm82nqdkAdgEKMwxPghp+V4Z29IRXDGCNlwH+zsArNw4O+hKnMiDDHAVqwoLqBlNHadk
TLxSxN6KOOyrtNe9Lx72fPkjMGCBXT8vqxv6yXeRfB3pLTnzX5pjy1yGcwCfGurhAxk0WGPUGcpx
IOb5GjBSzJY02iMgvSLwteJjq+T9jR4IVyBOLDO5rmA8Phtgi1Ze7NpkjC4V0Tro9WCnpcgCLgVf
ctN+N4xxqe+/GA/LHmJnnSxHkoDuqeG7lEaTW5wbi/hRRHnM1Do5P8wLfhlH9muhoHRZ+zA139wn
hZ3YX5ikj1D3XIonXto5FR0/30t0I1/1Yo57jPAPXt5rVVgRPutQsTPjAFm7uuMNBD1LbkCE1Hn2
59wEDaRRxqYiaPKF1LWa6QK+BIvYX8oX8IM6L2nyD9gUvvVddUnndr1+TB9CZ21/hOGM7yTEqMqm
GB9eY/FkKHt2Nk0FTuwFcXP8DMpCEOg7x/vC8SJD1WD2WdLJeoFw7blQ1l63uLDXyEFzf9tGSOcO
K1WTgQ7h49IIUcRoiJyoldfCurZm8ui8CdGc8LRVcTjhGYx+96sOjj94AhXukb9B3CnHinhttSmo
XrST6KrIG6mR+Btu1Woposmks8XqCacAeU1df7dGnUBM10ALCfwoqsf039uYngG2/66QolVthj3o
ZgGtBVjSF18OeQuNIdmPZfpvAy2GdsKd/arg8MF1l2hr+VjVj85z9c/EzBiRoUvP6QMqbORJnx3d
B/logQLEF4I5zKwC43JfcQ0e1wph8ymMdNh0Kry8TLscML9KdK7dv00lHFQ5Hgd9iK7P848nVRdo
jvDR9C5M+9SX4/z+pbgTN0mBXfR3dOM6+2dr39unZe6D2jXJSHPm5bFmaxdVQn0LctbjPwvzgQOR
p40XFfv78aQIuO5BYvXklIzJ8YEZAosiTZCJ55cQzxDodG+X1jSfxWfIKM54AxkyEfr4gzlrVqO0
iTwCBTOv7JLH06/0loCCnpDdPFyaL2mj5VWBrfuzDE/TiamMGljpH+D7ekNv3B0o03IIt7Rc6p3j
1onsCmT7rt+yPD5BbTJrVS2oYqxki2W95sW8iVI5Qns6xDGwe9853SvE66l7WA4IfoTqqxQyXM1K
USe1VgZ6gkSMDYHTnNA+HQl0/M1MRWyXN7NM5GZNH81mKZhITW7hrlWsDJwVWp+Y5QQIQhAkHfTJ
gPgYfhWwdiW3DoGckQNJFexvdbjjUSuFUns3uFA5blPKlO2qtZtuRpg3tzvjfBwNFumAOrooIMhH
sdYkJvn5w88t/YPDtCqMiSOto0viHJeoQiZqydhKE+amNZs0xrYE7Y2rhMy5JCgDIQg+n3egdOW3
Pj8JDN3ggOBCmlJkPIDaj84qA7sldzIrYf99DxHWmllWAQkP3GGKLDj7Tyv6kzXUMCsW+/sj9WnC
RjTc3yNUSIn8JX0GuhQCahU0ar5im0QzCUfOJ/eHOYcqLVT9O3lxeaEvY05AU6o8Xk+eOjIde4U3
mZoFuJx4pUmTCgDtV6kDnN0dA4sCEnMXzdguckCD35L6gUHKNcPvK2hSpBHlkOZ4Q/J/YRiwJK9h
7pA3C+vtNTwUfWLSpako3LYqKWPshx8oLLE9FquYZyf9WYi3OFqK5r8y0wE0osf9uiu5a35HccdQ
ID07zIs0Bl1nFGyYbSmI5ScDHHH3Q7Ls3s5RbUvR9/LaJVn/JJJGansRU9Zhsm85YnCssDryHcza
dwHv5+Qh6FIAwA5buigHO6w7Qi0wXFxTR/actjc2DHk9/dXdBSRiKUdn6N24GtcB4mqmNGHxiO6z
xO/ivTlUO4LHC4pXJm4abB0Pe3Y/Yl8uI92XfbCZ0zgvf0yOhY6AutBFbL/Gl/HNeHImIYmCra3j
XzegwynixCC2LYXgyPDTw22F0KmmY1wdF5rOam4RV4vVp1wTGRLGk/QfRKhq7zPzHOhWOP4GspGg
Bfw34179Iyu9jNo8XBLmrukK3hJw9AU2dsq86DEF5f4ZGXyrnf98XOn/1B2nhDQOVf3mQIOWBvHQ
0O318cWsoRbIIM0jgnuRYj9TuUrLcaV+XEY6q1KcCDRYbAo0liYOghlqnnACruLW7EvojCwTQOZR
L+BjDNRdDvq3cA40A9FiN3vye/Shj+WUxMVDKaSHS0ThioJ7UV0P6m0hYRRcFpfs46PA2f+HxFid
YZDTK6S7TRQH0ewIZhfEUFqntT8GVUaPMHmoxMODsQSWH5n1qvIuZkK4b1beahaJhRwfM2PxLchW
OVdcZIZv4tTTNnMM4tHTBL+A7xYm9F9tK8n9ASQ3WQ94G/TwQUQ7qduQlqohWyn1Ykm6ozhk2wrA
W0+yTrCsdyTy1fFtheU0NeVpUSELMrrXv3jSgMsnYOHXXwbHPkYfRVyl5+RGVjON5khyvustkdCR
TX1OKP3MU0C7COgy4D+B+rmr8uxiHfsWnqLUQCzWdul14qGA85wEDzA4SQkS1eEjH31uGBKH+x4X
qJJDJ63oGIc5onI7c7jnpkw1WinSaHZDGHDUaoPgizWNSmAi8Zl9Bi2o+bBpnBnaGvzT52xeBpIE
wjdFJYevAMNI6Kkss/z132QbTjWTReK3+uvnOlxyHvhhP1CBRRRn51cQp8VJEHXAQVp6V625Tky6
zb3AB9oBdWBB8D90t9i6Y8uD6va18M9/CkqgFfLdwBDwLR3C0HjTIwDAF68dS3QJJP+emvVJo+98
vVbSlCB8/SgraYyeBZv531hwiuZZpNAXdeSHGpNUYkVxSQ9N4vkQpgCHsqZvLZTdtUGPuMfzvO94
xmaOHDtUOpgODyeXZX2OqBWey9rGNmwtb+B+C+csjRl0UssTRTm/Pur1OUGX/NYk3mKtJe8WXtcM
Y8TgHalreTf8fuBgsBTWOe/PAYpxbVml7GmOZEn6Pk5pmbxXqonlpmdnp6m7MK64kSOCDPa9oPiW
yTvlB4MZZIqj/YQX/6NHLPuDDD+4xkDDT/hlpDtnMCEWMTPduCrMQQqCesL7iuUt6gcfKUMrpZdM
5m6bFUY1TEHr6uxF3hgJOym3n30sq1U1YCBagRrUR4QA7d7Q2jYGqR36ibTIySH6Via1SV4ekJj5
42aYDDiSui/OqsaiesGFEV59YeJjL5gIFl2jM3LC5dqHyw9sCpY4zu2zEee//PbvnNatLbh5PzeD
pveCdh1ZJo00IDz+j6tA5MBGBc5iHlo0qtYQ2BlQid5b7CKMsv0bwJlySjp/ttbnVa+0qHqnt2X3
EZ2I35KHjN39ZRdcqmmXizFgf93yRrq02+fdXt8a6JQtcQiQyIKtMIG/t/WarOGZwlNl3dD9IOoq
Eo9RqXQfZhDatXFYt3DpQmzuXQQHZ9PvcTnz50GXjlyFckQJ4iN1co4rE1BzZLu7zyWNZdRyNwuF
rgFOuFv9XzQy+3BAUbnTYx4ssmN1u3VCDMy7+NMz2gr1VBDbMmLMwkI1Rv5KQUCKCYmD8khMZ356
sozqral3rH4y7YuTfag9jxpmuKPA8yeEc3AQue+txYrVmxogQ4ZEd7CB7p4Vlt5RvcIp9OwPSKjT
JtrclKhrQ122M0vRBtNqENUfj4SAI3R2AMaGuS4SxVCPR+lsrNKUUvxDogVkZks++wPwk1e0X+Nr
raGKDVIXJsouCVfe6XQxSKThd0e442yVt9bKkv0AedQRz/go3jo2eCnIytKWoHmZEFaGqC1i/qJU
RcSkJeax4aL9J+BC4et3FqO3yMGfF+HpaAP5NbdXnmFbme+eBI7F27FUtxyEgZh0s/s4qJZ4MQF7
ryV7j6AiMi3WGQxfWV2UdKvvByWEl5iFIBN6nBTWyGCq+WU+C7RPp0/KkJjorRf4KUJI6vht+juf
6TpvVtsQLuKszHr+kKZTSdkzhsQxYUs4IEIj4Zvnf9ulzpxE/aRRlpkDJnwcBssBMUGC3CtmvgMM
/kUhjtejBRtIf81NpX/IekSmoqRq/X1CeX47k72pig0SuFGRYXigV2p/e7hurC/1Z9a/Z7ajsbMs
rmhgW9ufDGEvohX3hfY+HTTZvNQsFsxhShJJSXny5oaUANI9Dd0tVu5uxbQ+IIOuH1VBND3zurzc
efwJjwr9MMqh6P+35kd4ezis5yFf0zGbX+menasWEwOTRjmNnn4qef5yMSVjuZ8lKNOXmL3W+BlM
/VlpcwGJy7/apLxnczYeb8pM8HKOB/eqXI9Eenqf9/5l5PbVXaDyG2pT9BvZ6ydEPK8ogm2H1NPf
hkX+VKdF2S9ZI/jR83jFgIJ7xhQHr4ebjRCpdw3dLPKV7I3lZIvGJw5vttkaanfghhmzcCzXJ+LL
WA2rqDQ9JwKtohWbhFhzInziZdr/BVmiGnHkVq6LLsbj092JXhcUbFSB4HSD/MMW5BOXlH+mBKpl
jNJCBtbse93p7hewZt2T7lzO4oRisfMQ5W+bT0lwZDbtqP90MRclqlGxOq1fwrn/kWAlpElx0rzL
tS+YCt0yZBQbpb0qH0LYUaURJz0o+zIuCa7t5Q6mLZ4CgPkW/pnDat26BiCXKdXywIJiOp4Xs7+B
2VmsgfwTpSkmFRk1cW5SHYi0cPdBd55GM3E/ZDrQ0FW/aOcvkUerwmwPZtp70q2O9b+WzEWTNWL1
wqWK5s+nv+1sSeeYLojWShjv8JYx1T5qgG2hCrqmYP2vzCLEBpX8OIlVinsrw9DJ4mWjKrWU514S
ORNvtCHQPpGbWcajG2cBiiLfEVdrbP44MYdiMHTIj5BwrV4j91XMBsrmfqkpEi7G3lj6MaTF+b6S
g/GBV8M/fMYr86N5FjXWN6ne9N1bZrbOXO95uaPdzTabyrTByeGucH5GxURXNtA0O5soXxcrd5zI
N1QZsGarYK9zGvc7vI7Rlir+lrOaEgEKZYttZAhlAxZQASTKbTFiVqPGd7zG+6ELcEawarF/eq7Y
ZmvNm+1BLRRm38uSm5WOn+Uvl7zpC8RpTC57yiUSmQOCLRWP4lMHxtx8ICKvNrYZzLX51NfxbK76
n/+rlBrzcBRT8WL95n5rkfQ8qKfe4DUoNsHylFCxN2NqVxIUqa0IzgLUlz7ailvxo89W44d85t2Y
PpYBaCzYYQwCRbD0t8e22gViR0fb8iCU58v0PjvhC3PhvxQxygTjX7RrOJff7oeyB5/sH0jhUNDe
au7NpS104/I2ihZkUD9EK1wdTdozlw6/YUgIYiyq/YbulLuSYqezPH1+HKc5obiPgLiVZYWsXp7T
uFVeNDPkXYzmMUnvITY5poWevWEUd2SYpDVFGVbIZdrZXfPRbstIK1eNUwYjPegbHpZrFxMPTF3t
3ygwTh7o6iZPdpr5ojpZo12eCWyiBv0TdNHedKW9vIopfSVxYiQOBOgP9s6Xs4nSeD0mKAJn++rP
kyKTSm4gOJp8tt1zzKwFp3DCOSt+sIUIzyJqoua7wKbsfJ9SalDuTsLjKdgH2oFoTooTINoXofyk
i8EWbMIBM/RObW5VN+fmwro5JigvKzjcQTDnTbSJPD7sDYbMta6dU9WgXQswn//l6L9T74BeylTs
eVk3l+Gn9ZBumEVTenNSVE51Z+Am5XYcK3a5Pl7jEEyP+lfusvIX1fWqwaItLZkBIyBK/eXLWFle
kzc3CWZ1tngIe5kEP/6EUtaKD4zXBJn3xH5WTX69xoPKftm7fRVufuTs4ju5WLXg8SQLNOyuuJER
bXGFr8uj2r3/wbRtFj5OkhvhcCa2SnRyhK9P4GbTXEVc1DahJOwn04cXrz58Ca34yCXABnJ8jPtc
xxGe0oYz/v6zYcmpM6htzfLpB6CNArUbdziBH+61yeyQr+XpT5UQX/LS1LYmdHF9Uoqq1r/h2y4V
70j2UD2faHwPmz3/nJoMzElkpauFZWswdNFgUTo6K9+zW9B5alILFoErqUwcTA12hED024JKY62R
kCZg/M+k+5zZNqX5Liv81mgUFxNev4YUm1tl82ULGEierl/y2YU8fm+owZK+5zk8YPtePwyelahp
eC3JUz8l0mIa0vLiPF4pDAj1vBHSQcu8+TgGSTVrrn0MvzTt4Zhh21HxUin2dJBCvo/Ib3uDLbYd
ySPpeE+36EnolmtaXgNGIDLPrh8q5DbMAOKbWTMC3iNtiD3NlXtUU7z+Y56fly+GbtyA49z3pjTI
DkIZIjequkhsqgwZZa2yctyaZJjO7Jr4+mM0NZmc4vh4iDy9NPYsrP3AS1prcfKv6wdy5q+nOz+D
a6WJRwtByU96NBvRXe9yKAMRS4aVlx6oKcEKaFqFhg7KAJkReUk/oYVQGf424R91Rl9zV8VdIoUK
9LNd0SAk6YxhuRr33hjcoEEpROmydFT4LXnBvdziZhdzrEnHNo4YolyvC0kXBEuuQf1FSnUGBohl
5aUp+XGNweDJsLmY3rpIBpGH2aE8YqSkllQf65wy/v+pGvGXwmmw3m07wP9md2XnFmhPDSaVJMkn
PGBMIIF4/1xdoxVPD9XYew1Z4NxKPFiU+ejWgNOQOrYTlKzGqmUH0JVMAb4OSwT0jME+iVgYFHC/
cIqEMeXZ8LdFZlBd2RV6xLIQhbrv7w7YtXKceKR47muMMqNHB93r06epHTUYEOn3QW1Ksb/ChVws
mwat0oYrF/wiRsq2phCAVz8fDdcnNGPJaUIbCgzbqe1iWBNg3NqTJ6+nahhQn/wv5Y+F2hEyTsW0
UIIcEg/cqJ8FlWURtNN3ZBULXLACaHHjw21TKPw1XxJvjkhaOLbDVIMz4MENtYav0uf3cLBSWlUM
kWlFGA76rPptaq1i04/9c5Blld+SePwL8xtrLvyW52w0DMeDanPTMiwYmcYYRZsvG/iOKxh/BR+O
nawJQvSiaGkvlbVR1PocLGHPpGqZgisCwU9Hp10pp4yiNxcvI6uwulbqSlOoZAkS+61aO+/BDgLS
zyaBcVgKRcKqaPO5zmHwRtnXDCAqeI0ESLVzs7BuZb26Th5KLMpMzWZDGNaaNsiYWcU5y5iqlBH3
a68SQGMjymQj2o+mL93s4OMDzQpZLJXQXynZ3mfN+onuXut98i7VdvVBEEsTxzvhuuKoH1oZbG3A
tlCMOE9yuDHwg9XL6gLKl48G2labFilED8z8E6I3H60vlcrSP1Ychs3WsR40rQk3ZPpmXzGU5YX1
f4KdaW0fgcbxJy9ARTaVgGZKm49IeGyZQvqKI1DMyuhRbS8n5WNhWWvvRBI3FswXkOv5kEdpm8DN
0hDW0AfbgF19KGgZSsvzjgXr3heUa9xfKbmrleNbBu9OEaeMR96MPDQ01Zl/lS8wfMDSgH/WgSy9
HlR+LdW8sIapIqAxk2kSA3tUEn2Nx+szEKuosjD39HkyBTlGQLIn8lgE6Qkm69zLow+7Zx7UwPTT
YeaO7k27dNXhx0OcpHjLDEF5i+7JEgn7D2UwbWixgmGnhDL90bVcpRQ6XpvTqlTHEQuTvlXpPBdU
WSaukpwr5JsaP0fI5Fq3cO64hx3W1Yotq0E6/R2PaqEfw8gOuhua1yrXq/Dzu3kZJjt/0mpBKR2C
cjcwhkEcV5y8syL06ADH9L/ZiC2pha9T8UP5BUmTp+bfGdKNNqHo+B7ZJQl9BiIB+uDtEWMn3agZ
P+2Xd4DvD9h8aogHIkFo/DjpI/3QVAuYPZw0WKmT/XR1c9dl+E5H2x+IeyTmgeTd+L3+7VzvscUw
MbZgnitYw7Qiy5ZgZBJFMK56dRm5PMXDuh1SrtyACNRSmx6mVckrI707eBmpSt343Pe7vPYJeFET
o5SlIJf1YrZVZedlhVxTy2rnmpwG/8GPiB3hEhZvUxbmNeCG8mYhj9SmzQXAa4T1yu+Fb+8R4M+h
io35ldZb3yZ1vdJGRBesOHX3LhwRaZKhKyB6pmozIH84vLQrqyE5Elyo8lLxLzJYQF0pAG4dYBTY
zfeD5dP+6c7n6DYqnveyi9eErSPXt5HIyEgV84RTmFsQzRSjiAcTfoNbSZ+6910ktOaHggRbdvDe
gAP1sEnjCGAbPGmlTdp1FNRDv7Y26A/zTPJTcq6lLPSm0byKP/0h1bEu/GAX+GHOF7YzvK+ITQ5W
nukR8qXo9DVZaxiOQRO2dOt4aFb5OjEflT/LhazzmNPiLpXmLmCJoXUCaaGllHF2We8EbYjrNUYm
fFj23iO0NCB9OwChnDDh+8VwOARAwfqs2NtyHWGiC2qzwcUTW9ZW/RDWjNQkGL43q7knz5SN6WA2
cgl2bnxnLp5L/tOpM+o4H7XP3kM7scQB4b/wzITf1dAJHfGrCroHxKSsdX1zzY5qZrLzRFYCrtZp
CxR36fWJy9zh28S8XnwYJOjyaLPeQ5O6NgxVYgaMQEiaDLsjHhjUerfs6CW5lIOVGB8jbxvZB+0f
pjt6X9AOf9z9sOlniQZ8Xf0QNsK5glCdoOtto7PX1WUyLo9tCSlBb+OJ0yGyt+DdS2GMW+2ERYDJ
q7TozLFMkhHUGXheMZBQ9+Cgbmm9BHgghl8RxTOuBX/x9urxSCx8JaPlO6VfToW/mLHr+cgcJaXU
nUsDz03qhh8KJsFM2AiykICp9eBwZNvyIHBuZGXiCg/GfjG1/E4N2ULkF8Li5YidIFy30dWabyXz
wyekZKxIJ/KVtMquDJKuEY5lbzIpmFNb/lMrDt08FWm40TcdNUfIr4/uoxQKqAVUhaP5e3Wxnbml
6+5nt2NUDYp63I9ule0DEl9QNrQF5sBXqGpa7PDQUP+GGlAerZbhSIQw4cbTg2Wsrgf6w5gVYFlN
1gifD81Pkbz1CvwmFi69MURaau9jonpuwlziGJ2rTXaWFq8FIyCvEk+WzKZXIoNPtlMEZYaUccRK
y4vd2yrnkOBSCWDsj1G7Vgif6anKh0Xw29QEygwdL0Aj/B9n6yBtDTcXRXO2aUefLxDMn4mTZ/Up
27Y5jZg2fJA5hWnWmn7pexJ82YIcv1NHWeW2eW/PpQUAn4C1xO7PeFSEY2XQlu2KGDTJ8mahTS3W
PPtLruTqfKSgTjlDtwvv2ZbJ/Ck3Xig7PN/dvYhb3Z1FpMM+rgzz8VWOJK9DbJBZJfIv68IygnCH
SQavgon7XMDUujQk2T9kEoyAI6pnveF0AEZpzkcSx/SwLF4Tc7H3OKYHfnlVpd5OnXy9zkTwnfTs
FXbL5UF1RutK5fentbUueXlkSf3zViqWqfVwgpJe/UP2v/awLiACJcss6seGgwuMbbwedSx4ZoiS
FXh4B0XBJ1CsuHWsgPy2iwEZRDyLJG1W7gDSl02YqiuhE97qNrRZqeGbK+ovNAb3Cb5mrVtZuovk
eWZNFW9t8IPONnYjLf2sYJVoAY/0gOVLn0oUNSaTNJl16zYi7JeV7O90uSmG3C4hBGoZYGPMKBMq
CiZ6+6R3umIi7xQpKDmJxA5RYTPv36gNPC3lpwz981fpfBlPBxFtHKB3ni/CtFv9XQi8YLireRCI
pP9JnlPxSj3LL4og7dnY5CyKG6UEL+ViDk1am7AIGgMyTS5nkVpnIaaMKaz3m47Bl+7VxCHJEj11
s+vQrVL+/afvJI/TJi1IVKy05LkIm68vmKW/JSfpj/EP8O8K/nb1xGFlqS3B3euyvUNlgrN/FtTT
RmH8pq3s6gMnraiH5lCPdHaDmIvQVS4oWsAOHDVA30ODEMDoSHfAE7bMYY6k1tWxSkNpnrc7G/LD
2C2yPf//EWbu/I6ZeABpCXoogPzHEHVT6PFyj4v+YGsxCW56GOKGHBVA564HTms3EBxR+iIcmhp9
u1vEWV5NY0iEqRuHwFQhDGTwVg7nSUze1k/MkkOzTjtsc+ITtmu0cK0KgDy1IiZwAcw79+nhrgFe
J0QADbUWcDYskUBV+/dcKOnmV8j0mP9W6MNug3uhhRPFSvzJHNZ/cMfdHEFozJ4+S+ByAk9ySSD2
0RVZiZ0Ru/bQ834wuLTm0w9k1bKMri63rXOAhuhlncIyAj87oNaEMWN0DlnKM0OIoK9cAU5BtDaJ
m89/SIc8MqYJQ7BOAtj2KRFcxJPF68a5eccWS6HLJ51uJ8vqFiiDjROxy/CJsufEqs5zv35O0iYC
+HiNAjsEeAL5y2XrX/KcRdXAjOIGcJ7JOf3DWiV99panwgH+Vz6eMAtcWIx3K3fO66Ij79IauOBV
YIgcWGMtNBPieUdaLY5RYMEGcMjh5WgQMSKSJAqQFHO9NUFKnkdlK5+iHeI1dJbt6/eZDrPU3xmA
ycweu3UlMz8EMUdiL2rCJzrlzDQ134vRgioPSs/i87SooDXEhG1hdvXC+50yImPUsQ9GFKMZhWfI
fMSl3Uei7LuBPgbtLKuW126NtfOE/dGTFTr/8KVxSBCA6AwWZu4pkMCYGjyGzTc1Fod0zQH6is+u
sEQE96gLF0uxnl2nebdlrsp5m1qdlms2rRvhaWFxX+eNxxoBBjBtiTp/UpL8dDJRFr4TJwwA7TuV
a38llzfciF0opJfWyNatY8JCvFo8KO9crHxYjBLn+L89PvgfMdCrBeW1WlCFSPTK1dtjO3ilDgFc
mQtoBUWYWp88ubH2vwXNoHtbYSnEaxNlsYb/RGAqdKrdiZbJVuYMMcudbN9qerWOtC6m7wvVBw0x
DW6vHfGFQudHJrI61U/lHXPxOlT6cgcUOkTICfynsvZpbRqVgIrYDXQzcRRefIWS7N9ncRRt0+WV
2lJYxiXPsxFArY8QNmrDOJzz42KqvyjKYDnBhSuxrHqRyI03bhHfqP2jEQj+BZ+Bz15F10+dRM6I
iFpUJ2uMNEstrYBKjeqNE3OEOiZXjmi5r2G2ejw2Z7PFS7WE7Lhun3xh1eAGVlcut3wipHiKA2oI
t206BPjP4MUcZ9gwUJ/eB1Pn4dxOANSCOr1/KcTltdIei4UesxcNEmn5W+b1k5Wzxbm1F0dH4JsU
qcSx6kXuGvE3jmTUYoruk/9JT4K8SbyAKg69dMLC95YMCxTn+HIh66L6dfR76f3G5kNfF6YyQr70
Ocpuk9b2duPOySddQATIREsHsFphHwQWlJxUjHZMJm1GPRq/hmNSJmt7glLChkLRUcrcLtjmeObW
THc5QQ/863VzWYWlzBZI3+IWo05TzRjXlB9l8pkb33B3FvkEKRS1MHLutN/Q9YUmI7m7FDrWeBm+
C1E6fnHnfdM6yzD48toC89UhPsjeisWqs62T2GzsSSG7Hkvaq/4DBFG8/5GMwuOQ4baaCuSI8+SP
YdZdippEhPPPxFrunvvSKH1kVFYmJVeBN/918aft+jUcttp/LevgQKDQdT31rpYN119s0Fcn4eIG
AVEKhKLqCdB4qqWhig1XjJx97MISmS3vLWrb3TUvAmph111RhF6z+9MqPmKw8vLIarKrBDSQpRli
F2hgTUGuAQ1b4F5U+vtrJBlu27Didxe94C2eezGqCy4p/6edbUcNVzsPRT6wkzaWzZsGiFaaxAMK
H57326HUqZ6koURlk9Kx5BiV8swYR3A7qaxqVXk2QvOIzOwZkyytcaESEteYfB5KucESVMCeN4oc
fRcPiKPEPffMc19rihW19i9RLFoYH6dacmQ/sQ1flx/kHYaF8Zpygz/HzSIMDOgre8f9XGi/frDN
BTGUkkNmCZ79cauUL8wIKv2IYR1+EnH7FnRqotLoQjSCCpnSS0EDmySGp1fEBDrwy73FTEtKo7Bz
RXD6HXWhYkqb/fvPNFCq9GU+SAxTGJkGRgbU2vKZ2quFcpkap4OvGm7e44wk33mjDapvwUgQXv1n
NLchrcjH3vGt0knY+ULWMLpNWeR2j0l/kTV5hCrErJa3Ip3rR6RvlOOjXRSZg7Ii8tKR8YcU/RDo
ONpgU3yQXvJip0qx1b14udlQMpGRXdHHYxGlkVDV3qMT6RKIMUVX+9wc8vK7y9tNZpG29PwV11Yo
r9QoYCoDoc+iKpn5qYAOQvoHG/fz8EEIk4XScb9Bglj9dEgWC0Mrb8h4Z+PqMjN6P+dYMz1I0KUl
HL5HnveEg4U7zBqXNtAaENP74ZOEEYh2UMtIFs9N4OlNK31XPU9oHXeApYANpLhr+XY8ks7jnX2x
VvoYFja22VqVDSowcVyV54tW8zdbrOXZyW5blhWsca6Nynr6B80K1FsYNdcc18+74ob47yJzV3i9
YlJULkWIkb8mpGE2Rk0ZeeC/tKstlu2u4BXFtNCF0aIX5xhTpJVIu5S+5L1wmIJ5hF+tJ6ohLNX0
lJ7Fpc4IhWkj8fZcOzCk4Dgm7sAuJ0M5VZHRiiHz2s0dLo0OuDdB0xcCl3pVqdnsbmpU6n99XV2I
JKQbI9fAL6gKFCG/pya8bVvK8Fio2EI41bH0rs9IP9/5QJf7qeyEU7dSWX6TOJdgH5zboqdEApv4
52HKqQYjuhil73EMcg/C8+6Xkd4pE68ljGGJl66tlpYdT3Nbnlk26Vj2xm7vBovynhdz7n3KxZbF
fABMBAwvQAczqDs9EuXI/FhRZIwvXmsf+UUr0y8pf6oe9TgJaekhwYGmol4s//RwNL9+8PJZc3UC
EEh7BhDpxELPOHpj/f39niN3Svuw/lP3InycLC/bv+mRt42YhR9DPsWYHl3IRsS8zMVDxUb6idzl
anJkeymNT9e+KAWpb7gPnmJaqWZ4PHWf2xERAvTMxBq6xFba1u1nDTyYvob8Lnmq6MAgyDPThw3x
vPxaOnfb9ilp74X5Dyptz3vPV1U/BgBgRgbKAoPGWGaT3ZD4WYAEY7yZYh6FkD4T1tiufMA2NtAq
lauKXzIrah9PSUseEReS5Kui66qNFtepD5lRlSENZLL6+AFwuqNn/99grRPcgO6nehaBa5vGRBtM
Ghe7/awlpCWFx9VPSldPWefQj5s4MnIwOqbxh0BdqYyDcWgJbzfUFMEQxcECpJtGrHzlbOb3+EdA
5/7btQYQS5n1jL0WhkcOxl0WD1NIubiGAM3y0Vfwt01ijLsMgstJimBbktv+n17z/eRcK8wn5YEC
qFiHmkTcTf1cwBiPu3sb/alGRcEl8jXwPPZRjdyMVnj0Soeomb6jLBudkX5ojWTyIa/lIZzsWIAI
G79W9nRdFr5z8NcFDwAA8CHH0DSZ58m/kXACYJmh7/cVoLoqOhErTh9jeRN/YMYuUaDVrWNiPbKi
RGKo2K98tHMIEg4MAKawGo6P7i3TWN5BU9tlJnQe0x3mza+s+1aixID1JYg/TFINyUXIRFP1yeoJ
yEplDu27+h/cQ2jihF38be3/Xg0zkBDY2P8E9b/iO0nv5RqW4E9wxYceomwB4Ji21AqJ137vvxh4
QgbtWCbYTcqAlj1kke0AziP2E9CIWnxJdHM89pIydrYCLRdeWPUXMTOcYevd0V7xkAOBEv2egShV
/xIZITu7e8LyZg+RPKhG0F4gDmnIRYy83NLY17NJodRbKmeu/MWyY7nJfYdTgEAl/CrpMaLgjy23
VVYZTaQlU05F9FvjmUa3feRxR9UY3zSwFSSSo7a27RuP7qafYXSBclQqze7iU5eVB4BlDuNzL5ZW
bDinHdGuRGSdxat0ib8z3BfVp2Xc3F7cHCpOHTYGx3TB4jO9fEaa1OHA9HrvFlw3GXSNelVnxM4+
oLquEjtkg/ddgRaOmIj6ybAWXmEwqImKsmdyjWjjU4Ko3iNzFj3NmjWOWzxwCtt8wlm8CIKKSH57
MHuHbY5yLfnEZr4PTegQ275jhC+jKLgrw1ZBF0iSQbRY5cAf2q3FT/27nzrJfPwDHMCz3BXFYqVG
V2Leiu3l6BwMxa2HDi1egiZjawvsUv55oJ/ZGPm7KZtmaNYabAQuwYwWpQki6ZjKvn1v2jj4jSEy
gLqvm+cdOUzONVy9XgaDa1Y+BT8/57yolh0h3hHRWdm5tEs8aWvlCn+3+eD/brb1Am9t0c1SLrhE
QLTxBl2cABm9aY2PFVy1btWlTm/zWw2FC/T3+6Ej7seJl/yU5AAqXssU7ZyTvswosXKta9UbFCpI
/ubn5L4V/38VdIO6ZR1bMiqxWNVxP/oNnAJaH45Zp/pkfizLQdbW2Ve1ASjfWLZz32C6u4mq5ZO9
I4eREL95SUG2i89+np/96u+oVOddYkGcnvUQpmJFa9J12oZo2WZGLqRKVSjN/uletpPybaGe01zI
8DJLGzX/d2+aAYH+RiUd+CV32KiOpJDPQF7dEZzXQP/AW+LXhmEr+Rgdz6riW5GhOF0r4dD/Gf30
32xmCfmtZHNlT0fAjR0LTzu5C8LjkDafGHmQhv4BMAaBIaPamR2pZQv5VYjQvy4Db8R9Gh9W11sc
b90ei9tGoFvbP7OHyUb7hxa9NdJv67h9qNWyD/3iHhSnvVfRf8+sSa0E0Ey8REmrdcZtxEEng28B
FiA+3ClJ4osgpISYPInMfHPG41gHhmvx9Qml3x7g9zDzr/dSZ6AV6pUgAuDXRCSuDRNP5DmqOSDb
pJeZp1pg2DsURKbUPyHo1pZbpZO9sfyMtgfJrjHHJ+O8YbjvLlqfjH8m2n5jX0Gaucot9i6O2/zo
7PycC/NvhYWDTdvpY7daksBSJZYs2jbHx7nx/Kg7eg3K0cGBr8ju9xhVsvbuX2PlmhIQmwjqIGIt
sNdLnpEqbPoQ7ON0BDO7qX8hWxigL9/BT+rBtz2dSvSRobYbUa/BOnwaxzACxBijCjfQgTXNy/y0
aFSNhsNyylMOcD0CFpZ9RzCIZRhZd9TMbBZ2DN32NCvoUf5jov9FF38BN93Au3NL7hCg8hqe4giD
q83sPlV+GU8jfzHmGebI9DtJl8i47kuFTgkYtFDkpJIHSVvzA/Zj/0QzhFzs+GHbtJl2VWhi05DS
8t9/3CHubAH6EjrDv0U+KREL+REh3pATUNFyPOd7jTAdlXt0HglCqam5i+KLVfhUh4XQs7uzTgS0
AdpM6HSxqw8oiJ7SxiqG6w3NGz9nKHqg0AxJUvAr9VqxVrGtYjcrsIObp29o5nMk65uWGsNp1J/E
jrDLhHJ/l1m4ZL92KmE1Txzw3vxn45IEVVSCc1kxnvwqYETU8rqzNAMGr4g49zws8PJDdGOl1EqM
chasE8aX5cIYQ/NoGlqiBpIIE/EN4naqfdQ4XiVmJHGoaF25/NF67qrRvXdGCfgWbxWxXJU1NMiR
3PNDc+/0+V4M1ST8DGcADkm3YjAlDmMekH1rOm/ebPfJDi/+bubbS84JxXK5Ss8hid5TtvSTxPLE
WpkcBpqd5+IA53EM2lrXka8aWfzcr4aOUbJtFcVaBdVJIbsKPmtyWf5wtvpuLsm9p2omUPyVMXa3
S2ys0rnSvvkKgOBb9fWmu0dAELE64nshfhz0BWLL5lf2Gt9caqUawbV5MZkAL58DqMXs9Zzfbekg
/8N4rhLQjmG57X5X33CMOEEMhnID72qiAeRorrnrkMWs3sBuq33Bcr2dv6oQeMlTGs2tNxJEPR6z
NSf/7EmE817OuhY1xPyC9i95vqCPndsgmqOEmWSdM2cIhh9TCXICahwQqghLDsHsOll06MB+mTwb
r/a3yVR1DCT7/ZnH4qsmBFKhv1Jwahkl402xJDBC/6aMy7t0oDhkkfahjKa0xlaUh+KHlOqhL4Fc
t529fY7LVj+k2bU+leplEfX/IkqeEa/jPVpfHG444rd/V74099xtwY3/nnKwoVviZkwr2wvQQhda
4pXVgQLjhkLs+WsdQXmT23/sFbr4iJs0oAbXOo90FOrv1fZa7kweBvZymkpACg0Q1LMsKHam8ewM
VM2UAJIeWzlmp06rjeEEMNQuu/FpRNEappnwi/uR+NnDcrET6nHWOEptOs11Hd6keQFLfJDUPAaM
r99/YXLW9UAYaCe1EJwIf/avHEv0w4ztc8+ohTb36eksNgE5jfTTRImIzL010HqnstafRR18QFgL
xBUXmUnXfm/+6zt/cSMxHdVoc2lG/W1vF7KfgWeDx+I49Be2td/wdzYXYc6XsXJUToYU6ICSlXPA
Ctr627VJ1/ToOh5e7KvFAfTFOCBcqHHn3Q4UmDkYNSWcnAYZqKlrHT2q0uaJo1KipPtyD9R0deDv
qDTz8ZbVQHI/vfoubt48CnECj1MAiFBlVt0yoWpYFEV8OTT3llRuQiauo2YMxHb83KDwvHVHBubF
kXjPmYl3tQx/khbDfGaQCiHLnfye+J7yrn7LBtips7YtdqbSVQkghPdG3teSCXmw9YhsFCrFiEd9
vgR9seIT8Dk+womwhziF4rcl4cpDbBAuugY9c8XG9wg/zwZ8migrcboubwfne/9mICB0IGYXk0dK
oH/Vf2jZTA1BjaecwEWUKnDIazb51pbiPBVuuABD07zv1gCUYUrU1mq1ky4w5Gt1pH2GwpFa1oGn
b7RMmFywaQBs36VO6gpkYMObvyF5aHABBzO+woBmlPCv5I3dyMNV8cPgVq3TZI90upL+/PS8anJB
sPLG+2J2QUkuIONjCBsFpGxOAzDqH50gQEp6v3zWWu6sDR+wN2m2LgXA/QfTo1mEmusVBvuZIXXa
E566K6XzisfFF24doYoBl39cSta9J+QWoIcC9Wf+9UqY1G0XqBLLVoSgsCDLJWF7OHakD6Lc1hQc
YoLXAlw8qEz3yBSPY+S6692PhwFCJBUPRSYtfJ3hMC4Btv26E7g4soYJPgikvE7U5Zt9OkS8d4bY
H+kIJjfkM8ikz8GF6HIBD/uEvkvJt9hhfny81P3rAl2f9XduaMc7fkEkOOJdQXNVQKoEw7pOloMv
AxDUcJ0NiCK2j8pCduYsKWfzj7SVmRYg2H3iwfK8Vc6nhGHjDqmXJNG59wSBLIAZSrd8VBvblz0A
OUGs8YfiUAFXOukd/Ro4IWptkpST5IUexrFOrmxRWdPft7CvP/hyqpxYNAaI5PQ1uUE0BkTM47Gg
7K0vtTW5nGbFGsPvt+w3pGlfDG45jJmbVXfsNp59dU5AOIOsUCxjyT4FgYZYYbm5rQdpqy8LqrKy
43ya/SNXe5knZcwojeVnEDg4489nAaIzGVMtNZdXryD8wSHS/0JZH+hw3OYT1I52mm7r0LuaS7uQ
0iqXs6R1IqcupVtsQGdJKUhZmYuAnJYzEQhcGCe5mOdbQ5YEoJ0/mKDJxHzTC1niI50oQF6ewHdg
vKiC37xw4CPhHzuJWoQntbknEwwblX8nqkII6d2UYg+/N0SUYBR/6JGDOmc7LlcUsz032E3eTdnU
pe2M70cp/zDTUVywrUNiWzLhVzZO3HTyOi7TMtFBm6FYlLdVE1ewl8v6BeXaz0BQEjPeBG0sPSM3
UmzQIKU4Rm0xyJ0xHICMRhTfhwzwUr6IXiYHYW0E1nXZ9TezUybK7KP3WuDQiEIP7/BN3Gb4ny9g
SrvEpjSjpjDZ+8TIj/dF0/IuCr+x6FJoPYlnVaBiPCBdRmMO8VR4pFn+6cUP6Zuw4posxOM3UhJe
tOTW0/nKbKcd3whQHtEKnLfX5o7Mv4uNWoMZcT/6k86XlCBmgpOvK7o5lAxBtSzzcwWNBBT4SC0F
9eA2/EcjwF7X3r+pwvq9ZKDMDRwKr9V02fp1vwldtF622+I+BBpJngtikez3Bud4axLMw9y/heBF
/cI1aZ7oyET0JLzcbvoPY+f5jt1N51vFkz8mWugZaDokJPji+MVtLMc5BMr1M49eDw2X7ZohgRdS
XiiFabpCQQotUwTTmZNJY/Ec7mFhfvZp7jK83gXqKT+cK8XBr2f5ZuBAQwXufXDf01yN4GtKnUr7
/wfdKuORC7diELV6HybpvPd+S+klnt08pOWyFOQVXWwi9tdmVQxfqv1/CFC1j8/U9Z4wVhmw14YZ
xw+l3COrHQdu1CNIVmEOFsnEzF+PXED3cuoopeB5ox32HGH4GxNQmsKE9SVNZY7fII/nof+cqbuU
7csKU5oCacWSB+Hl12RrAouChkbjPyJ1cZsAD0pRN1ld00KzuUKswL/TqlE7RqwDxfGMqiANnqmj
/xswr/TFNoeX8bw9IzBR83TxFALxe76nxJ/m4HejoowBFwa84tLK00ztKw8dT5/3+Q+OWi07rBLw
lofDEkz7plx2sVPp144oR5shLX+SmGxOjJDxNObMzPMWabuAUlE5+w1S3mYK4jAPzwzK4qtAAOJ5
corcKO/GgbYIElxPb//zFnfv9lJuySlfsGe1bS49A+8i/9trWH8LcPlWWwc3Sbl/3B4CbEdUrrYz
bhVb3L9wsBj5Gb7r/B1f5433FG3cq2g/3wHuM3Z2JYinNCmmXcB2xskUtqq93oOKEutT4abJTcuY
0f1b4nR+cIHc+tNe/o01pvJeLk9dnGqTxU3fD+6QS7tIfBir5/76TqkuDyXHbx7899+7xUa+PMas
d/TtGPlSJuAazj2+ZzBsN/pWdhQegT759/WwS0k8MaB6tJVFb3lUk61lQcK3m1hVBWqfzr0qRQk+
rtTU1ZwCJWP6hK09XTzVEms5gFmsFyI4oKSn61AMQT3UoNyBhA3bf3kjK0MiPqC8bdLAWM2Ht1aO
v2ew+j6WPg8DfWfImi+U1peS+BCpvvCMXbbs7XIHVtTcaDgUVcSree+DXSv6Fln9Xfjbl+sV0N7C
/9wDI4pakpPpWkMz9r9JtsYzO64vINFMgH95Dm4/CXh5YGn4YZOYde9d1pGbwDz5pljyImmXQ36f
ptW5hwGf9IdE9zbjrEbmrJTXzz11MElkSpBDV2nrz1wJDbIW42QNBuXjBcesbMbN7JnUpj2eJHK2
Fnhv2kjnUsMI7xu5yZOukf2dHM9ye6/t78IivtKgbtr8O7E4sDQpnO0BpWak2vDcictyxKcCPCfQ
sNIdNolwo9Cs+3Pmoj3N3F/B6ACm3wT68EuGkUUn1HaqAFlnji302RslNJStPVA0lQ8K6g/je97f
t3KG8oZQgcrPRCakOLln1PEIardzW0ll3bksn4W9Mec1P2gl5fZRSSm0pcs3KMK+pJuGdbZ2BFnR
xbCcBAaFYkv2KyN5P6Qvjxg/gQvdBaXDyz2wyCiR6ZwNvn8A9nNtFTgPwEvEWZNPmqC7Yrsxec8m
gvib80MqlXBwSFVaHJBjODCam7nI0dAbeu7e465qapx/Q4KaTI2O4NUBdEXfiDZ/0RjcjRoRgqtp
NaAWABpKntQhU2BznwbblpYC31bss/IfzAl2Do5QOdWUnxWe0UuAryDPo9n7erANi+lNzi0Heoa1
OJ80Og0J3DM/o5cbzchcglDq05YQf1m8hmDDGORvI4dZ0cVOx8Ju8AyJKttbCP3A9rFvXpAq+Cmo
HF/kyhcnwYiYOWUJ3YKUSUlZlOwTjgSin4WhSxC6LZ3fp9SQrwxSTb56f81ilKFWB5Uh7sMu4N1v
jSCnmpk8SIYm9pllfiJEZ44YXua4mv+OQwmuJC5V35llWqpgLh7yH2+VUiDu314x9SYhVPJKeqmc
JT+Uz4roEOpUqFMjrs9VBor0Rgf8Hw0SXWCDc3Tx6oJ0JBfyfvHI8CfzXai1ct29ArFNTNBvevIE
sRo4Hr9TFZCn98VX1fuvVkRSVIDLmA5GJOoUQAPVNF46jAsFpwrgqa3ScJBIlQL+gr7zx5UX0V5l
nWHGqE08gWMtHfizZCdjgfAjv9m9W0+l4WY6gXa5Fst/HJnSoy5pAyVbUuSn+w5638XTesOKpbzN
Ihkv7sWYfrjeY5hDQb04Y3vmsO1UYwWaJn9rj0GKoBOmpiruAa/gtjehUwlHkUYJ44nHcUch07gD
l04zH/VPYAKStAyyLebKYWZGKmuVzo5Uqei/wpgoJSx8HCw8rXXGzRik3XvF9z/SG0yzufRYsAR/
oLIe/67jWPup3gevAm/pfQTHTzuuIoSgio1MvimbMtuC2JGZ3uARSo+JHOFxh1QyNBBCqpsdXADW
/nAikQb6FhUHvpjjOxc5Uv7AmQy6DzNybwpH2Q6l51CSkcGT/73jbnms5wNZKEenUIo50JPSwh1E
UxRFnggsEM9qShwivfp6SxzIqUfmg7RC8vqtZLkTtNfMovBp/7JqQThl5PwitAYqGi6hBiHck40E
0wa4H4EA+8+zA8y7iloQIjpysDK6laUZ1/2zAzphOigOiptG4S5ALBPxoghoky+Lfww3JyxLos4u
wecroocB+hGgxmbmXlJvpPeKt7FwirXGAH2/6UXZfQBFubTtXsqj4jb+u31+E3lxb4DlJzsGlOii
j++nq8NpTY+roi5xamaxFcLYdMoYkicxuueT2sL/TGiTf4UYUUdTUabMXTKObNSgyOmd/mVHBYTL
lOER7LvymuW3YFpiNHLI7SdA0r1RZwJL5DqikoFlTT7pgayMZ6Q/Iogs23q/7x22861nwR9XjlX+
ZjkWNLX9DWnFsZDvgOjLmKciMJkaaPHgpXGamHTdyH7XnkJFHsUIRb+rhVEVsPgFTJvO2+9/FIqm
pNaQ1T5sj/xvmZRaXZOQo+hrkAODEpZivbclDZACMke+MjLHWyNZNWGOdzzf1BNAteIoxuc8Wd1p
GTjNz979J+/pceCNgUQkEPBe2q8yTcMhQ3434ad9Ibtk6onCw5u3uzt83LSTskWdJddRUF5Mo43Y
Y2MKMflOtwZQMuYhSB8kl8QopAW5FZqPaP3rkyiNhsryuZGuyRqBvllV3kydAE7hdAqzctj/7Vpi
oINvGVtlRuL/CHXmsr5RXwcRqae/SegvG1MQSDqWygHaMX0YHCxqLa77AiPhyVsw2yDUoT1S4QIG
vCTNG1TuR6lg19h9u3IkcnPcK/UDLj5LZStPanuOWhVsFbq2/S0slEf6h6MfFtLczvLnecAzRYLu
0eblrPv0VgEdaAJl1QPTn5dbznLC08hcsSsihh1O3T736ZNQZycK9z8xAnT2Q5blku92O2HF10Jf
hWcxCasgj7lhna1jIMYyd9vF7PsMHS5ybESb6XE11ALwE8fieHXMBziJ9LPAi8P5TbYg23um2UPv
XLrOVxP9j3rXTZtbm/I8MOTljcngRKwOY5/hk48HoWYmD/xX98YE4rk9oQ6FPWeGmxsmbLeTrfgD
ieGKFwv/SsoXBtH66X2Et/P54p/1x6AgCOIlp+L7OGt7GDCvf4+Bl1dgVwMeIaXLDQ30XFqumg/S
pmhs35hllIg44tYcBkX2V1dK2DE/JkGNPROaQM8td7vfwhIdFCfPAOFqHHGK0daCnz+T4jr+Fa88
WDzdg7UmNXmdn77wyZ3n0fqHdeFwNAvXQUlxj5kH39WVw2TdmaWjjQxE3wV0cO4UwKlu+Ie/F//k
W8T/fqqE5DspeAb31SGAHOJR6Pa21kcUs27jKsxdkj2bgFbaW8Ya/SaQ8dGXUutibMdzliJ2ZlJF
lDE4x2a8kug64Sl/z9a6PUHzmv6V6rrsEahB4Pka9HscfVxXxJqWaloSTadTG80e4oBm/wl0Pnqs
HAJ6VXRpztCZb8vjjn3vGeDQWnANBl99j2YDQKBePpmxMrgO+YuM3ozmZt7qralRWXZCDa5IlcxE
u1Y5ngaBgD3DvvySNUlVqjqIzy/X4G9HuhWMX5VnaZwWnu7YCuQJjVQb8yGEomQz+xBVB8wio13k
qDIlFEbDzJwVJ5+jS/Vtuxl9Wq9w2LysmpOCcX55sCPYCZd//g12GaG8HgavKoKklfxlCSFIpAJg
pdykGTHoBcahb0buZ5hmldKxM4OFpgZy+nxnUiuuysAip5km9KV/TbvnSwWLADtO21Bg88X7pFlL
8AHX7qfk6bOTU4xglidXZ9JHqidhN+ZQUAixvZ4F/0fa0hhS6JvqiQyAnNU5O31BWaZSRAWwid//
DSox8pfypY8aA/h+KJswyrvh9O3OVPuSzgoDgxeUW7gSbE0CAqow4HxJWiecB/88DHFQ1jOvtFZ/
pyG0P2KVmsJux4RCoGFG0P+KNVQjWrxkLjJGIJAyFPB02w5FRIQd04gLdxag1EPkSZPXXQpAUN2W
Dqx5hwS2psuXACr9kBq9U+rtWeYFxqR6K/gL9nyRFdnnHztN9nNnEVbYdeYs0pQyc2qHLcp1p6Ya
4yA9v710/zGVwuzS3e5JJhD7/of1PuTppmuJwQ5SiNG8dI0ZdFyM2uyluN8jNxaEtgasi44jmYCX
YINvY6ki2VQtfg9TMPxiKNR8zf2WUsop7LhDPWFlm/kFWG7RwGvdKNY9ZanTdNze/LXuZHw0gGA2
+O/+330tm0Yj9hB+giMYHuQiTcsacvgQ/SttQ8YHxtNTjfs93oAhlArdx0Mb8v54wyfSuMqGt7CI
nx0V6yOW4knY74x5vG2sV8hnKUiK4jX2Kp06fOi8zCSG14wK1o0PwSX35OQzqYX9sKhzCGAuxIZf
zD6KaU2L9f/h//zsYKDB+syeRR1pIVKkf1gG9h0ksNTIGurRAyEcLGNWPZeQpCIBmJPLG86VEnaB
H0rx1b35YNWsCdfRaYfuOkwJUw2OPSH4cDjkY3SpCwuxXhqVPUJn/ixw0l2veGstzMCBj8B3DMPw
jeFTYZ8N2lhrclcyqPdWRqO6ISYG4EmIomtDgcwAMviy6fJL8WWBZWdn+WSkiotiIMAXpq7LuVNa
QnNufiCSU3U1whkLS44FzV/9V0HA5NiGqS1HSF2D/gQ9MVD+vuGqundRA8lUz/qaWzIQSEbm2hba
sDy99Xcc8OTnmysuEbOt/JAnMQcuebCTwHJXEWNJwLcexxcJqvQWuY9SueExgY8FqdewJzJP7oVC
zYrTeRH78mvaiH61nDbkNaAS9tEM7Q7G4ww1IzyjHr4TRP7nIetosH8THRWzNFBs8mXZ2lmZmLpQ
t30h/ABnS129h6znxaSKSrfj/KDuXHv1i87k288H8tELufVLeXWQcGvNDy+Sf5KYTLtbRU5y3nEG
KSl5LusryWE6D9NdCo2Ew20R/Mj5VfpUvYsR/4FiT0hJRDey6k1FA9kJZc0AjLLl+REfIzmA8diu
soO57RYbx8W7RoQBKCF54WGZ6vhnonq8MQbeHbYPfUmLlOMW7V+Y2zHIOy8mWpbm/qdH1vxyG8f7
cXdhbBQpQziu0iOs1maMccbQ48xin/jwU/XU5RBtd3/KNd+x8f/OjVtc0+2KEj4d32rLMt1pgaVc
BhzmmhIY5u2Cmb70DjDs4JBZ5YyRMRxX0Cd6mgmaIhoWxE+i5OeIBX4LWWDTJ9dpprX4duv4vEXT
Vvpq6Nb27KEEFZuK7AdcRncDKrZN3Gu4GAGYA14n7RPV32st0mn1bBtNZJg5yKsP4JludFS4teAj
omjaZiLn7FF5tcgzoGGnD/lioii6a6BLBzufXNNGGGikDJNPsIDVVCAxrhvmGlekI/VdG2k230Ma
FQ9hXhdeh6UsRlDeckWC0Hgs0Sj+qyicriLLLXBlTHfKEzWi8yaXjjLJyozgLAjHJ23aVHchcSLd
JGWVfFPVyKRHaXRDxxLr/eUCzcX84pF6VKWC1BlHWKTR41ndxPPbdFp4QXB42DIyDIKHMCvBB2HI
YEu6Wqur5bFiLIi+t3SjVLbeQKDmF7SX3tCVNdTECatKZ8l0YxjBl/abzRtnZTSBfBsZv36yPIzk
H2sPzNYSXpg6l+DgF/2XxM2NBnfu1Y4GFp3YR+razWYTVnYTPA8jkPCHZWqoACQ1J6vDzWrIp3OF
CnxaNpfOCInztWModTZR3cWS9EZP9OlnBc2TSZw9Dl1oFtHM5WjExm/yCOqT61+P+QuLyGMfBJLI
pkcTIU9IvJsJkCIgMrxWKVU8dexH5uauyarVIGoCHYEIILr1PVFTCqk4qxXJzQGAx2P1zu/bzsX2
VKDs7xhnCuXTj8ojLdVvGxP4FRJbXG9dQu7phYlHg8v+lA5IqyvZHCn3EzRdIo3znMQE8P66DdCS
Ku6SpMs8JVphl7m3oOBspGA6PG3Fi8VDB7Q4LvbeXKM8XfdTBIpJ8kCEaxYLHntET196K9bEWtCG
cRjnmuvVuzPPfrqZ1k5mecgA5cCZkAo+rMrptUhy5S3mdT98aXZ8asa2f5iSFwU52HSpCopqzoVn
E4ZOEKFP3+RhPDMq7fZibCmPrqpj6/UemW1MRL+wTUo0HcH9uM0RbQ+/zRvvfK4RGhmrMKKjxtQe
mD+BopDZI/bRF0fE5SK9htCLkRElIYS5T9LNQu6t588q3Io7DLd6tuLh4lDiE0kgnBLek4+9npxu
570bBAYDNJjGjZ0TISRsEQWroxdEUdRXtEmABddZ/sdLCN2yh/X9NuLALj2CYS7Ed4I12loQg5Hi
eSmb4bRgwsbZHWz0gGDwF22tGOyC2gfwxStr397cNWJcCtuHuGr2ToiKM7hqUzCRSmhaA6qs2Aee
jebUGsg9M1cKJrSuEqCiJ6d7MAxvSIPmpzKrJk0CtpV7icpH4JtLY3uBfsZ5xEEm3ouacR2NcR/O
YOlAYWgAZtiC3G6B+cU6yfj616Rlj5Ua5K/FbcK5P2baXRSY97faqjIcKwuQQksz6L8dDkMEn9HP
xDX84ateJybTjhrZd1e/TjWNjXmHDZrBjeLD1hz9slEkAcQU66+csh9xUhy53+qkkm7WxqnV3pGt
gn1T6/1tBAka6UqMmpzgQUuS6RD1CzaXeO7wVRS8vc9xXW8fMFVvS7y6FegoNyQ5m4VURGGCIbHP
ldY0Enzuj9AEHNgP2lOhUYpU/E8FKZoBw3+xNvS45wHfFP6bYh74IW17odTL9jqmBaji+pLkqr2y
K7YptZ/X/Noq3wJw565JX778TksI7JpC5Uhhm3AMY6BH3qGrJDuY+4KqJmxY/3XAXc1oySAG6rMw
bNWmmzj/im8wHWsgsnfNsYjcGQ88XRI1k/1t2hAQXrJI2GpA6daHU1kG+W1pBUoTihwRLwNL8VUW
ZiAHjObTVbEuLykGLjrNkpCT/ACoOZqjZ48uDqKzv6Kp9cEGhWRb2cDUAXDf4odGdAH3S+tozqs8
IjqzXSV3Tz5mouSShHy/8yR1dtpBUJ9dvevEKLxeqRPYZMfA4Rf8k2axoNUqTc/4QhPX/+STFCGv
EJcDU0gUspw4BBIUFOy8kK+pxnJvaOG2FSO5UEogebDr/Cho+rfEbLPJiMHGDnyIHy/aliWHLGUq
9v8a27BkfyCrWmQKSNlwJJhqtndHkdQ2BdQp369K/wL8ippbRCsIRTK4oMdsA19sdzahR8BtVt1M
C7Rd6LlRYQFgSRAiA+fJQVPkTrHWBM1/R/1GweBf2+HJrgGJ2Rd0MfZn7Pb/uFvgo9gt9my0YZv9
+OmvYSZWva8oD8jD6gv09GP/sLjS1wcteeMm4D8cEjHpuwOtfmkoCqFRXf/tyGbaHGlFAQ/VeZVz
I7LI04Zf6mQ0J4rZK1mbuDC845/lmaR9wU1p13AqZCIIR0Fc16QRXC74QJTAvjyg36OeO6/DHzpF
/fZGQgKOUcBJ1fp39sTXdlqoqAYsGe9M9iNzIaAfWk54sa1MtECUPXimTjzZkl0GxDIni+UIKkc7
VtPkm5uneKOm3l6PWUCOPZHEP7ORZbb5NkyokDToul79qE+th1b0WIzkVD1LErX+t20DLfipJXVN
oMcd/Wy3kmILmJu+GSjyaM5fy3ckoWtPisyTpZ99WMOKpgdnOLfweDBNB91ED34Th1bVs0QpzZSR
2vi+2Q/Hv1IIQME//l0ErQgi5/rbzRR0sEJ5PP7epkE9aGLUEx4lNMVZH0gPV8vMVC55jorDw+wl
xTIBp+f8iR8QLCJek8IZ6cAUEG7MVB27R+8iWWe3jx668PmF/m4Ih0JfyVZ7VEPm7apsY9NIVvC4
dPb5yXx/vy/OxpF/8RRZZ+qzNWyTk2q3MeD54Hqx0oF4707KUpdrs67OKmouQjnamByQq/bH6S1o
UDTWhQ0R6MIRTixVFymei7/B/mWUsXYOsDDzv+m0ErV5I3TIGZhA7zCCy2GDXoDxByOsNPsAJUbp
U9pGaYvEECT1rk4L4i5ReYYa0PmRdA1R7D0M0matdas6s8O+nLpVu+ohXlju5GyWhlzvk3IVduy3
DyCQzRY6NMJBn7OEA9tNF09D9y2blmoFHQYJaQjV8C6zLvLtGfobiBxA0GwV7E/kCQPWSXcg68uk
ho7AONnlDuDaB3m6RHUExt6Q8lyRV2y6p2OOKEU1gseFV12RHWup/G4SvJsmXct5uZ6XVg+aMKp+
rM8rl9hUJ1glaKmrz9m0mgTs2rjuRiysq7/sg4eKxgS2CFaKL86pXJSGLJdTE+bvpmGMvc6i2tNE
GWuB82haRO3dPaNxiYas+gKlX5h+6uFweJxRoS/kKACNhe3c3GcSf8PLCrzDmy9b0EWa7oKvRit3
jQ+6eR92vwqJBesfFoO5e7/tN6WbNHwrxxQnT4AoJeZJvRGDn+8MRATaNXdOvH997iuooyLyujX+
ylhyoQIjli0vQwg18lmVuBaokiW5VtYxUnFhIOJqyRU8vOTVo6Wq9yDOiNdes73/5D1z9dHiPLlc
5MrujMYpfNrdkBloICanaNoUyN4NIhnhTAO7nYiCVwXynDh3Ov8grPhAhgGoT1XMN1V6MfnT8t4t
ehqMR0F14I5IHgr7pl+Ijy9OGVx5R9o+K0WqnxHHAZL15x2DROPasrt/wxbdU9TM4zfrWSVbRgac
nSZWCWQGU53/xHFqcFgeq8nhxhDm4ViLEHKz7k/Ho+5K3Qh+SvqrRw0Bj4J7jyOniJQYAMAY7eSb
4l+RywmpVS/vI1q6g3D7UhrPLy1RMIKTcj8UcXqDs2PtZwzwGMEtfvRJv00DbwUblvWG37jF2SSb
n59MW30nmhDoNgYlmwSE2TFuOfeGF7Qt2sFHBKrGj4coCPiBr8NAjDcC8WumPnfdrDNJqLQ4CTMc
tmZTYHnae/QwzKxRUyrUN7nebgU+c1EGCWnqXowy6gadDEwhhO3Vb/Bp1JJ/akTO79cwEFc4SYvb
esXe6CskbzwTVvLVTxaB5uArrvcJQH5f1QWl1AYI5k6ltp6eEd3RUQFjWHrAYH7gS3XkXLuHiQfQ
GFBvJcru/pmNW/aHWeAH6d30GcT0cHpTTed5Q0uQbmGhKx9WbCE7yqEEMAn9qx5JPWAiLn9a3S62
3WNzBnX9LS6Wgvqw1D+V1uDznObE1bSWG7OYFR6BTTdB5Gb8y4bWQCN7O8rcJ6ae36Q7P/2W11DS
ZjMGNO6i7OtJbEKfLacfxVzNdVl/Jhbf1nPkqBMHJm4cDh2/rVkIapIlJcYU6ifAofyPCmVT84Vr
erBb1TsQ1MNFn9UZg+INlSCBekIR9r5Ik1V9Ubj50/f2zSaN9DwpbFh8G0wmxHu22etVKo4ewTm4
nVxMN/yCxFZMUfx2odN+5iRmxI9gMtD1B4/illW06SVYWvuoVcsE6S6TjFz+uiwxd9YcLix4bcff
sy8HqxNINJKjygqd2vmNdQ5ElNCcGZO92kEfVFid4YIPe+cNcUCVjUkNWVq/NksGIijD3KyIHI9I
JlBTucSQWQ5yoFJAsXnVPYo9lZ55v7kMpl0wGqDmLo7L9NdL0Nw+ru0Gihw9yGNtn66rVjSg8GW3
MofpbFCfDkY9DWqj3Lxilq+2ZdQm7cRYVTfLrjdkKsHM4mq7835CLh1TLREWiZboms2KNHMNOvyu
GUfnRprUu8G90pRnuvB5cJLWACUWnYxtKtkereU5dJZqx7S+hD/HVK2hbuh7ol+aEMitg1dVJ0Rw
PlVGflmAWY6NdlZuNJkU3kiAwhk3bw54GLWgwfJFSeREuye7XDmaZJliNKq5IHX7ttS4fvNiOdUY
OrpJqsdDoKAw5YdiWr/fHM0reMNXbttxojCeWoEmmN2XlOLMVT1Ixl7Dka1/IDgukZwxN97rw9re
KAULj7/xPG3gV7IMMmgoezPQeFii5L43yU7G65SOEYskTcUipkdXvpaUmXgoqrYjNUfqCA8riAmB
IJcSQrk0b5rr0IlTruFF3jAFHshmFOzUjJQAxMjU33CV9MgYjK4Re8/c8Hxmezcy2Y8eogRA6Ocg
Xi9BEL/28W/H9mitEtvZCz7at5pMt3dSgGgJLRuXytTr00yEEuEt7cUbTTYSLmW53Pwk0UjbDLwY
u3eE9Z0LekhR8df1m+PA2fnt48HDjL6z5H1CVORiad1dk2FZFriquChiuR0JQLwlYFhqC7RIu/bR
2oaQXyVr1fenmdXkthM/Zi30ICJpN8yDh8b647uzQBrtq3jrCIjZm0sIuDTbrMQNm7DBzH8SqW6z
WJXUqUBNorxm8UvEgI2jkxe2LATwrqTIxe6/hJcG+N4lKgWgYP4oO0djYLRpk4dKcmUswwXO8HU9
/pkuc8egf2d3qZQC3+EHuE/Y5DZwu/PXyRVUui/fpQUPlMg7E7YKzbEXPgauJr3ZFAFc4CLXqQ3s
GMLZnsWkE4o1GOuG9m27a4DZJ46D0gQs5nCz3KHrh+I1DMzzG3xjSaDnnIBXN5FIvS7VqtfCshx/
GN9Vfa/qkG9RQegB2VLq0sFhdT08XTM6t/q3hfItxk7Zry3wsr/PPhVMGP4U5/u6ExyITLbcfKcZ
L3KMybGhbiJK4xi2CEtdYwrtTc3AKlexxcDXf3kgwYfM7aHKMaDfw+EvPJi67HvZoTF6N8MDONy0
yeu0SlVL7VI7PxB6cgKUDanUGubmM10nspRYaoDwXVURjJfi0C3hhLDAWRFVIVlQhB6i5Coo9h3l
joIMyu3EjYSTbs+ktn0wmi6JL5RVGLy8lnL/exWhUr8cIXLvZqiFt3vvfq+/iNTT+pieE3Pbjund
BGeMzt82zWlDiuEGyl3o1GnYP8NbFD4YbclDgGIwbH3b1FUZdUKPYvcTAFB/GXbngm1GJdmn2uiy
BagjB2Ha1EL5h9OQWd3J1272FvmV7qG3SSpDoJzzwivLJwQtfpI7jzR2p2qHt+f0P2O7gM4p6XLA
YbVMFOCYtBlEspptauIEuydq3cEbL0LNFMYe8J4YLIDCGX84IbLR2CTkD4AiHXoDfC6uRDy3Clul
LqvHPqlDGlGXsd6SkMqYxg/bIOEQQ+NVIzmeT7Zcjhli7jbAiVFOqV9MEwOHD4OztiAkliQA4FAF
IP2/mXz2cDxfWIDf3SrTGlfj8XcRyRdeTG6ArB24MsnBLvjTkoxETbYnxCDP1YvMU0Ml1f4EV3Z6
HwRD25ixEqaw47nzL6Tmdx5NUidBA1h6ujuicdzHx2zHDm3lDb3mTNjFNjGqHahXbE2DA8A8d7Kn
9B60NEQt6voDliilwLYfts96JK1zcf+lKUZrha4zAbMSxCByEgUwgW6vlHerE7SCqEWL2BxfF6SZ
Kf8V0/YxJitFhNOlNM3KsXPPUjqQ3LwzLsp44jtgaeIocORCK1X/23yp3Sp3blsgtJRw5t80ig5R
DGY0yHIPMHaAvPmRcqplY+spePW7/3nyT31pW28clEhOJIZLq0D/FVPokIDdIJW8onblJ/9HvO0a
NqGufB35R9LIgSYcrJpU8B7zIf25EezZfbqll91tXyhsqg36IWF4PMThnJ9c2xo+YltM386D96Q0
CNh9ZjgnR1gaSuMHnbqTXZE3SgQ017DLSK2q2haa4nzwKriaqz2vWl0IZra64nkJe0Ji/ksNNTgs
N5iTn2BPLBttZS/wDR1qFJms4oJUnV9kk2PLEaMRJzrHWvdJC5R3iLzr8EPYUpQOVgIK7R5KxyoB
FRXf1K4eM9+ZH8SUmeBI4WLpWjLNuTin1C/3gtzJ6coVRlNMXov6Dlx1JOhUZrurpuk7SJ9mMljy
32WYQs3BjLHgE6ypOT+Gsfk0LeOrz3FGgSOTI073c5TwnzxDCZiPLqG4Q56yMrLOPi7Vh4KtgEzw
ryrX0cuKFO9n7bw2fldCQlnanZkbOzxVUNUmj/h4Q2te3azL5Nu7ueUqe81PcWtTyso0CD5opGAP
/xhNBzvDoIJEDNioOfXtBfF4xzncuGGNS30DFddJ8YRI3laPwCN/SWaBzourW8N7RFT/UgoYO4vL
j01U3Nl0YyENtc1weOwqtrFKYwxfkyRD3CaPui2wLa7pOxRtkaz6xE2dVlL+KWRBM47UNWJGrhAN
FPUcEC/WPBS0tk5Du/DIDtEBMMRenXsjzi9hDHhXZeGLJRmLWttLoBEL2Q/a187CgHODJcQMA99F
7oaDqWU06FiYKmVHQtJYYZIVT1gxV0XXk111zAhSPRk4QsLglQPhUYrTkdg6GxMhysm+wq/VcNQ8
kfgA/KwlH81qwnQNkLVwVecTSkRnxG0gYjQ68HJRlAsW9nZ5r1nHHlHdtSq8sNTT0VuViThg59F9
fgBwpNvyO70gYNyP6d4kwQDKOyNb4v5UctEpAIlcxwH694NO+RBZAHfx3ny/uMms/uU1pNIzgvms
VeX+m9y7fi3S6yftL7ti+SmDpTXCSasoepTblmYCHXL12NjWlvx45hdvPgMcNGt00r+AZJzdgRb4
aXSeiq4V1mCU88a5Uwij14naXVRvsktqn53S35afgcD9hu16le/4TIBsBLeGSw/jUu99zQWXsNGV
mIeQXa/2sBk8GXJVtc43FI1Gx2TwoTvoYM9HX7YRKZaHlakON14Uxea06yT+4mxsPSZLJPbQVx+d
ktDzzZg4tKNAUkdzNOGjauFj3eIJ37yDpDZwrTWjiTlfHzN0kfZeZql4G53FEvPcdaFiEEItTjzC
ym7t2ViMOz6m6Wz8yBOscuncHjm2roY8IzP0pViR7z5kovV9hCOn7TNp8p6Z7Ooh8HyhyddpAC/f
PFLj6yg9iOSAVyWeheuhMuU2srUdlJNlvK/WTRl8upDAIqiThhB500RKGNgKuoETG+z0Rrg+cam8
zYCT/vAWce2DdP4njzBEMJNvOHLwg5j5dOvJ90h6aAjd/4d1Gy+mlaQU43GGW9MJGriwjtYJv9Te
WZTu/QWcQTPWASJR34bCwe7FijpmIFzWnPTZRLdqvHSVtJq3ovPFtYMLlowvyC2YF6IXKmM+FT/B
+W2VJZbrEdxMWJbDXgy/tYVTfYWpUZh0DEIeAJtY3oZn2Rkq/GK94tE8cYhn3tzOQ9LcoLnNWG0d
+9Cjp3LsGb2iigE7NtGPGFhU5pntfWi4NLwM4gjRDpnDlRVHmAH7TYLGjzPqEWw85IkEA13lWn8n
OAeX9Jgv0X7QfLwT+tCOePfqRTkipWMHOyuTL+QG3qzgKnmXhzAXy443HnPxszb4zmYW67rW7vjs
7LAd0QuljzDzk4z8sdiJbmARSihgB91ZxAPOu+C8SnsTD9yIKkH0RM8hkHqvujYIcdtqkt+ldblS
oheTmJ+m4FLd9kHpIW/U+UTCWY3T2uNZPticfsXGlDabKADVp/l9LADtCImoa/bAATd/mdhyh8m4
A9dnNpZl/R24JIuLzyiwX4QB6BOYTFr/gQDyH9b/Ab0ejfYnaa+3kpuoCHQtpUOU6bpbG7CYiBSa
hnfCAYTReEfF+qL8Tt8hRBHosHdiYyfmpXRW5gIbBM7nl2pdmtjGzRTjI0tCDgV1JoFDMK5v77Be
CKq/6BVuRydbaGmwwDeDYgrKNPmQkS9JJfG0/EF8PR0KCgLTmqQJxoNCn+JsFU/QtU9vIqyimTBk
iul9ASiI28ZnInM8Mlo3G2OuQ8ijkXBZ7HfsCsy487oNRtdDXA48cc6dtsAgchXKmJmDcl3xVQPx
6B/s+cXdSMw4blwDUqBERt8lr8Jtsff0iNGQO+jlzVGUjEjj5mqrpfB+TBPzqwfbjZnCrWHmJPEQ
iX/Lm24BmBhDbO1EJhcYUyktU7HdvaWkd6X8YMTfJROy46CnxBQMOp7yLeF/7wOqy2vNJVUzCFQv
jScNDQZMNK5NSIHxf8dhNEfcreDG9HuEEM9U8GEamYxTDVoaWcdB5u5NoiGHNfMmg5M9ZSeViXLH
mNWE8rm0sji1COzlb3yJ3eZLYzAvvsxZnKY3dwVqM0if2jG7f4rbSXFVcxTXRMwpmhjMZVTORj6n
f/OEGQHNqyN0dkvKB8ppAXpXpslI1tTKQerxOL+p4KtRGW9+UdOfKPPaMUeQ1SUZLtXY5bOs03We
ekSIU47yv9CI+wWe4sTXGa+bANEyDB0jJimAQ84Jf2O9ZbD4rWwtwPjfjGPJvg3fwSeo+tHqu5Lk
2pVoX29oIWfsQuUoZ6EJRkD7XJKEIs+QQGjpsPK9HTUpxvd/ibpxxjU5sfodhsANMolNRwF/kbla
qfdBB3WWGGHCAPxBE4MuQuZn1ynSu8zd/TsaI49Lr+PvjAMcSHqg+GXz83rgImcE5+4r3TfCcgZX
6OrEF9u4NPeMcsK6zbrbMHPDbXORgxkypvLPvSowcrNk7bgBKJLcrOhvM09Ncb6qVDhXXbSiStpu
xyqYRDLfjBq8olvdvpuyqZcGHnkhYCaHRN+RLuWKpOy8y26KxCAhRrfwvZPobXWRip9K6zc3j27P
P/xd7PAz+GwnF5AgiAKxBQjokHmTqoxUqQfqcUaij0MhO69Ci/wGU32mYCXY0CJn2TZwWr76O4qE
u89vPoD496J+AGoDUZJy20HfF7E0P6GW5muP1Zw1CPJZ1bSpgHly3Dg/csXrCwGYLh1VXMVzXpQh
X8JZsF+55OnHbduOLNW7LE2Os3V5iWg4qQLU6ne/NQLqjczljlrRT+S1mBPpusKRyLZ1ALAFBTzt
4aF/1vE0/a1knrM77Og0t1zCUuUyUHyz4xLAeMm4YNrbZk2bK0wCdH2YNorBQNLa3sgdWZrZO6Qk
MgqJtkJkc258KsLULfzf9Tn6WFS9Uv/fdbuoDF1b41Fbw6t4jekhYmBWdMnQGrlpEuc+q4WYreTs
DnysEEsbLdPiTo93o/7WDIQmcM3YDpgUCM/iU7UJfSj6iZWC1pjntxO0F3taRQ74CrWaKO0TpLIl
OMUEcnQmeULPFiAW4Ebm0l6m8Vi3EgZYqw+FMg1fe52rJsDd7eq3NTswT3T74KTWumCDd5BT8TfF
n+DzwrqZrU2jq+ETEVxNfJoEg6Stw1sw75qSZgvxkLOEXBVAPcDeLwilKaPk+4CI74coUchOI7pd
LfHHrsHepoXikqJlNqRFDrSVBHnI8brv+zEV2/OcdDQzujjqfZb9gCFFCpxTtUaWE4c7oX909aeE
yuOyqgsyJ6zrWOBXuXmxHmMFYqfTBHcvfSFwAeCSoqifol7E2TDjczoVkrx3ZSoPPLn8ESnNspSE
ATrpQDbGbhs9KKAnLixkZXqmr6vhv1disLGGX6gTKADCjmOZNMa6oZ3VzaPkGpqkORzNAOYhRprP
ASnzIfhZYYgd/pc0lx2IcQJ0uyDMg48DwRxgQH4Cye94y8STDL4ftNHTjxjavC+YlLhNTWJfDYTF
8VS/2om8f5amR2sL1E5iO5re3THSdXlKsT+Ntpq2IWmDRJzCaGRiryYrh/3O2m5R3URzvt2/gpLK
qhBejIXWhAlh7vXgA5z4HvzcfMJkkt+t0kdx3V3KP/rEyPXz/RMZTwAjNehwOum2Uol9T2XlJFR4
B3olzewr9G2K1KVmtR62aM8uu1TV03FaJ+Z12yGJ5DSZBqe9cnNjCUP9hccDbXL2QaMIO6Y1y5Cx
P5QHb9GhL3AeWAJlQu+04URTjp1FG/2ubnmd0UJjNMJ0mOJEOt+maJZgpAanKF5fKcQqXaNJgr2O
IyYwCekXTw/jqJ65tV9tSjdihYFP98qXHGvzvFMIlvZcuOZoO25qMf0Gq3RG5nwNS5B/6ZsYSxdp
EBkQ8y5vEdQb8QjL8Ql2S93tRMs7NJlD32qgh+5LxrVWqGtPzKEeHbVn4kmumyHdgJ2cexW2G7n7
tYWuv7shdzXfeeaYzaVlpOZUIWMX+iQ6SBaAjk/fGOPXC7iex4tmIPnHsvZruE1tb99BZpAmB5wV
zvrAGekCPVw4SUaKrZYDIfL+74jGMXiW0hnIwNxt+Vlqrglwc5E4gmUfyL82DlNgyQjeQEIz4E5P
Z71gBXwilNTrWLhprPRVfXDS5Ctk+g8sUhvUbhw//WIaqOZEZo08vBpVOqkWIIwkIvhFFA9E9CbX
0vmpcyvKCYJDsHXEoz2773PSviO1rLBuXGLysPT7olvFjW+449zk+Bplev83smkLVyogoFTjuw24
C0Q/LJtOD8Sl1Xk+/M/vvxVvOITSY3c4jgb63/hX04Ff64P0BmWD8cx9Fko4eCfpOI4RR6GHN+SE
g7gcEVCKkCVsSBxdwVdIrM3/rYlGFQUzY3ssptFcpt6tJRrApSbVqDHkmxPNl4jSzbXfqKOR66Mh
iX7fB0xVF/XrXTWYzuKPgrYQv0HcLwR0ansh9pj+kioGiElPD88juN/6WeCpaElBfyVzNZZcqYuB
XcRmS4OefiBDbNponT5ILvM96qe+imD4gL07eBoKnSZgKS2ZEUA7vJ+Z72XC/9qRc0GMwl+XUTLj
YOhZfoXY4Pgfb05aKnam6ORdFrfZj400CD9esuSIy++xjNxlkb5dfknlPPxeUr4ZkVFtVtGqH3xn
zT8jjXqHAAHBEtBJmW1OK6b6hgOBkmbU5K7NQ8bAh0APIUsoRFkitJPzOxN4O5C1XA78eOWSeZaY
J8weZ0W5kvoi54ElcqHrRbB/jIJrmw3k5tCtFddPJKqaZVmUgiRr7jAUtnl8FXfpl5Frf/MglEI3
hcZTfsObDdyd0PE3svbWnTO01cXMceJEf+s8Xr9qTLlGmkyQQYPTaNlkS24K/ckS5NyLxaofDFXj
toMOB1u37fVckUVTQOGtQ4lBKfJ4aOxZfrbityBqIfeFPshRj1/J06/48NJUxgtPAR/Bs83CQyNl
506FfI+hpwuKgr+rIvWakwWYTfQvd5P0YFQrwfnPNjY7QMaVqMlsYvW5gtvIZyZI9ImJ4KvySLYB
OlPH8pyOoNXt9xqMA81qnSPGenNCXOaEXiCIWF+UWMPQ0cfdZV87MxavpF8zIw5b9wHIR3gPeClO
XsiRhUexVjTHhvV1gpxpF8e/wr2/zxV6QQ2cBKLwXHIBC8oNY1bDdMXC+uw0Ayqx2lq7Q1avhOdO
9XHJ8c1V4CNqaWUYNRDknbiv94t0Lry007dtInoO4q0H7yLdjGpn3Pmw7QxWPF2qfetXNK1mhbDu
tNYyJa2Vop3OuMxa0lbIeUxUgDih8MJ3JnG0EWX36rdIbx4wMOXJhBX2e557zdrn3j8giCcpHQ6p
qEBhxgAL44NLv9sYHBoTQQdPrfWvqSb92Yz0yMcSUxNLqR2q6sxCkl3zIrtKV2PL76Z/Tje/u4Yq
z+JVeiFk8YhzYFyH3oH18epp1LwT8w9eaOvS+PKxci9o25f4fYB4Gm8/9bSG4vkbf4ijP8iytNI6
BvKzrLCgU8guRIaOHn3gxLn58V3i0ZG2pCtS2TWmWCUDXE/Zp1RkoGrNLoiIZOIiN1P73AvYg9rb
XdmNz0N5sVJwXir8gFqsWQjEP6jHtfLIhm8KEywjWpL8picEXAO2Ag/R5ZENPVko5molywhxCW8F
lof+atKLjv/hz+CxF9hgnlwHX2gIJjpvwnR3HP5OF7XP5i6oB76MSj8LF8PwTh0mUVrHuwSIHqii
yzvO7WpxF7ZUCzKzE5h5ctz74RL7wN1b4q2OQkfsbrav3ww0JdqU7eHisOEpmwXL0BakDlIswOps
wbaWpuPWLjeyVoiqmkTttLn1LxnlOZ3oA3yzgq+Co2GPHVoUDzXZYhOwtpHooZvEWcD23O4001KH
+nZT/A2yI504KAZ9dxsSKlJcp9TFtIN+6un/anyxCpvekrqcUbYiVH1w8IskIN1Pe4XuMbbvF6X+
FJho9S4vIvVxSYf3Cz+XVl5hU2SY16KmXz3LjJ5dD0dycIfJKZSPaMjnULqAPL+xxyRf6Mu1hkFQ
7IEAUjAQwGtnGRyQ12FZfeFJ59hFIt29UurLnK45vtbgrdVCF+myjNA16bRnQ0MEmRZ2zBBpsZaz
57KOzH1X96Dc9KYgxJWQvzrIaKvwhbT28LPUB5gFZlElMYRsmB4bw8eXUoRCE8swdRSRzvlKPcya
KSeEFMUL4Ebz+kZ724g0OPK0QOuVS3OVdZoUEHQ6U+3xgwxco/7epQpcIZezMjBcVWra+la9YWzA
dbvFcVGw3C2ucil701SyhTo5FLJ+NmgGTGq5nBWBTEjJyXvoxqn2C2WyraOOsXvPPNxW0Z3hzgZ/
6Al/w0IUH1xBo7M/em0GHqFZAPJocODpZChwZ7wEP2n0rYZVCfJJn/bwuOIuELhPy+D+l0cMa1xJ
tcVGNEXDFcNdsR1F3Yko00erPp9WUMlzwdinPvkn5/L2emkvZQmQcr8wfYusCGEH7oCXZNzj3kiO
VptHJgrEK9AJJA7sfh1mfmp87fbAjfHyCb43LGo8ZE5tnCPCbmElFyUYwhHphdwGK80hyzzaaG2+
TLPxVzAhlvuLWY6QA8QKwncREiA0Nhy4pelZOHFI7b9X1tG73H0KAU39jAGVOPWw0dgkizb4YDUH
kWFbly1lXl24N+YbxErecQSVG+l+gYqAj29qLA3Gw3bkTKBz3RCWVIopCSLT6b+WWvu2qSz1VYZi
1ZhY4PHgkRuMS/0IKSaocY8mmfDYnJLtR27gFMJaGuLFSWLjZjLO0hpUusfucWuWqsUItFfsNtQ3
vPRAPmY72UltadKxALNSurgjRATdaZmdMy2rZkslJxgKCr648rV1uMDTcARbMAgJxEfcdnxkheZu
goTEaQS3+gQ49Rr2E2OFT+nZaMe9f0hWU1SALilgGYl9OUKyzd0LUKRG+ZSFj7mhOqXWpoM/0/cC
sxqI+F/Y4cE2GTSRBF5p7zMKrUpubglllA1nYkYQovzrT38St89XPkV1IjMkeGQo+ZP+hExykX6m
R+ajveMnPTzY6gVQAY7h023ZO/rW57HsYpkF70eM4Vb382ynEpdpoLuCa69IGMeblETt9LpCRCIx
pmCSHo3Ze03HiWMZ2PcErTfGM6p128aItoaJPO/0s5zNLTJxNIEe5+IWtlu1fhH6ErcMgk4FujdN
3AGIjEgbrdpgavYhP/FQ8mRopRIyH2HQXaZ2sMyY29jOSc2FQQjavPVWzsTWw1Zt8ZkgIVvI8/Zr
cbhu/ZAcDX3zKm2maXz+Y7IfdTEN1pVQ4HvQ7vkW6tjqWQ/3kq08+daWgTMathwZmrWQen5rXBH7
FemJvqKgYTAVKqLubJVAfztbZIr7+R1Ze4+YI7/KkXppkj9KsqUzhgVFPK0P005kvtKTJxkAtUhY
+xbpjSOiidn/hlaiLj8AKFLMpXUDkoOL7mSo7QhrPRhh7G5nD8oIDTrI8npj5wARkP/YFm4smKKE
apjQ7MxCOHPTVGeqe/ew4kgBFCM77ghZBGs2XgDuDk+7ZOHlDaz3Wx2vevqe38ButhQA9EIT4tz/
aEkiO8qP8M28ob3Rxx6/yY8sUZbr5TxEvk6p2mfbkiVACvxR3OqzNyOA9/P8ehBROhkJpYhgJa55
3rh0j5M+bbNe+tSW/r50XefDnbDJ1Al80SgHsO7IIQMDMLKpudT398k1moLpRrmAaNLHPGbPeMWh
QMFAjIdQW5qfh4yANg/z1oEAS7KU8/iySpc615LASWN9hb50GxtS1HUGB49ae1I1kvg7RXd1TBVJ
x85r7tGVpRwlpJummd1NVzo5xdFavnIsZE8k76RReANVkCSGwX+w2T6T5pPtupH0Nf+WJ8U6f3Kl
EfS6Ia2PKwV4MvZJ3kSopBL+l4UzO/GvEvEdoL9AMQ7uc3wNS69TU+Tn+scoWzzB+e3kAAKB6x4/
ExnOQ6dxMg1Fgub7byaHbmy3IRdQprX416ExW9xNi1xrPieiOYEklX+smoBxtU8ZqeD0xXmdcQPR
UyFMQf4w448M6mwI0KlL7V5AQrq//1A5kR7ornHCUjQf+xF+8+36vazuTl6ksA5HBUIKaN1JTReP
crtNAB366oWkV69Xct83PplD7cDjIgenlyUXwGScnPHeuLm2E6G8tyKpu+BSiBAwHi8D3xG2D/b/
y5ItzOaO7EJdtQuMQCCUbbNtQCa8pmYybVpR+6BlSt/T8IKpTFSpJ9+1fF82tzAnQAMm7ZlZ++Jo
3H7ycrk9Mm7wr8szC3594ezP8/2E1Ir9PwHVdT5OPAouJg/t5xfBnHfZGoF16Wh7Sx7KRPdCdElX
uSWnmh6nggPwR2PKuZiXJlA6J+7HYsp9uEySUZTksFPTMSFTrDMuGHg981jnl1S+AQk3r+xqs7RG
NikwfhKVrNfWLDUhHZ6YN1fpZaGxRvONtuW9L3EwMO9+l8g4Gy7akGqGe/DN8z+k/t8MomH6ABXV
QpvMYged1/5tqPB0RWETo0AAoVNApFde8DJyve5J6rAaspoRmw/YjYdePayTRV7aO7+TYQsr+gqV
NX+bhfdmFVW1zYfhtrh1eKNobFX7vrsfOhjOZLgolwm6o0euWx+TQ3w2coKG6kMs7jF31LLp+4Yt
zULphDIcF87wQElLrzskWUQkWGsijPa6qlSK5YYtuXLChylmqp+8vOx/bOJFtvSctqpm+TYhPct2
8/c1ap3hLWnH/CrkglrAxlSXPusR1aj3IgqhIguXzCUg+X70DNEWxoQOB6Y+I2sJULJowumPBf7w
slaALLchYiPqIg1vHM7iEKT3yOaAkf7xfFlYvEAjAo6e6wEqucgQy7nDuowq7jQt+0noWpyeHpUM
Wjy8TxXHasEqqJWqxDnSNLcplMJUzsut6hiL90zlNK2n3+xYT/1+Hh8ej798Fx7UTcU8GUGOEHRi
IJe/Y8loba+qC+XWAZoP4nDD3h5EhWFpihnpyK9cUMgM7LCoVWSVcUiIBgAJGhaR2H3ZfimlfSCC
34NSINY8t+U+InUilBteZlLuRWhLThfF4iD91NsvA/9iBouaelZMvyNAIKYsrTDHPcQC4sefsFfv
1FQHU91dknM7K0IeUkhF5+MQcRHryijEjZ2xWh/7AoRIkQsESQEdJlq2vBSFJJY3rMQzd/XT0OHs
FJK2dEAOoGjuv5JwQ3PTf8Zv7taNemtSUU42M7ijFxGmJV9kCjQTSP7CLTMGcWwB5zvi81Kl+gdx
0OdR4EGDocJfVfJ63HSUOcpGpHRWO+pSBnLktuN0WlyfqORaeW4oeibbV+/1dsCU9mMnc42LDpmx
a7RIUPlZQVQpv77dSKoURdDtDgLg8IsJ02zLYPC1j7Z3HiopVAdkLSu5vDGiRpiy8ryvK+81Uruz
BMFVIe/jJMTTCFGm+H1XjoFPNPj1XTe0rflvJr/q2nmWC/Z5Z/AffRtOqJHFjv4OKCnqoycPeJQp
BkZ4DgYAbCdBK8r9AoSRshkQoDIKFa05rdveJnRJXQdfW6lXXY3K9vNrQsx5V8Ea1icKyjfxOKw8
BCLB9xf+TsLGgSypYKXfGoqr7yAUqIb4MdR88HyxoDdj3PEAN5qqTwnljn9tj9I1IHj7HwkLLXOJ
RtiIu5EKdQ1Bvrbo6/Up9UDiYWm30doegn8TMczmOSGqiOW45VHwwNakvvOKgAfet6X1Q20tn18H
nFVPEk+ik7iaI6ONOsQF9rX92BDDoNG3tCaOVu8XJwTr5qkVmcic9uSlpuRyqRG2cZOCtxVzfkNv
PLo4bf4/gSJyXbkBJBjjJtYzfa5l9jajxnrIdFi53veloKAY1TBoVTflngNOyqp2WHG5wk3fEi7+
Yja6Z0/X9LLfy1HrlYX2WaQhXOof3IXH9sG40ef0V+1veKAVE38mNB8exzsTNeKbvX2TtrswMxUZ
/HBtKmhwowt/Ixm+VBcja/0zCroDqhURHMxdK3U4IN5zV1+YA1YJy/rmQ3VeJHVEajRqw46CXsFM
tz9tFZRb3Uu0W137aCvonkEGL6d/jJ7B3aIsSI7IK+rC9WWBkFVnCam1D83m32s3ZWTc1RJxYq9o
Uxypc+RO/dFP1sEcBf06ZGHLlsXK/Tdwc/6FOBPKC5yycrS4oTExawgtuQ++3orumdk3q6dT7t02
L2pzU5x/mUPQZerOujJHUAJf1/fUs10amk8rBwscdWRJLjLE90qqIPeyFL6lPFYIni+YlCBMW7sq
YfrIFVat8+Db/yBM6TK+jsq7eKDbNXQc3vkL9FqVamlBXDdA0w8wocBIqcwvUZ9sOip08sDjHsHP
4EkOvk+IIgqbGHnNRFA/p/vAgVJyrWl42v9N7PQODD9Sq6eFNrEHodYZg8D9ObBXkKBfZaCMDGKF
MOW0NbMrD9yjyI/mgAs9P1+rFQVjU98Vw9f5t4N/STiDCr8WHn/iVXGGt6h6GH3Xes5+SvO2SH+B
6TPKA1jPwllL61bYgpIXCktshUJC+hW7jKYj2G0uTCJTpDIrqrDt1QKmSRDTtmUrtsKKtNnMTLNb
+pPZOXqGNsNGMrsRKbBHJUPFpWDzQaYnRvod9HDUe9x1zcsl4HACXQi4ojgArKnGaSzgzN+gkwq3
7VRfLbvnWH2HvWtdKEzAIq3ZpFQ5EMzhpFbD6r63Kfy3ti0reqAh1d276bCL8dt1GX13mQgBpJIg
7/p0libu/uCD7pG+ORqRvvbhTlsYHGNSo/IwPnn03WeRy9x4Ohalj9HMxQLfRWfagH0tjLWoHUIj
xF7my9kI2T9hsAGeZbMvua5c5smNNj40HsgV72EXURxuasD3AqmvnXm3djn/dplxAiW67zX19RMK
tyAI2VMcA/fSxZMYaruZHLwbWOnIS54Qc1fMfUk6QdJ1C+LInb6dQxAggjPrCUlHN5aYoddCeKka
+mLmtj3woIW6EHouSgLuA2Kd2A82/RWnDRM9bq7ikMiq33o8725FEPmw9Uvs/De6ioEHIc6E0wxK
jeVTdFBcQ4DsrZ+lv3gj0CTCt1Dw7Hv0SEO+FCGL1mEOfebOmHA6RK5cwvUHcMrWgROrC+OjX3wH
FFFiqYTBljmhY1Y1iq3KdmUWzIeiTRqlTJBxzS+eKKLY7oeBhZutl25GyEaEMtYzmWnZLSK4idxB
43XA5ucJRQvFiznzXaCui9VRqeGfF57A0gLnP5YHks8CxnodwPw+se3OSJCfFi+1R1EwJiRQ7TFW
z9BZzPYKIvPl4ZImvlSRB00qgWQziqdEGoz81aMIxZ+dkTY3hjBedfHJ8fRng0lpYTxpvLQzXZ8S
mG+9SYg1RcRd0MnppIn89sKBUjGy3T9ldSuV4TxYCk8H/BSX3iEAgvpLFB2bBqL6Lx7hk7MttM2u
ASMH4DcoL13fwa1UC7rRryGmz6nxouJprP3N1GXMbMtQRHtNfqgYXRCF6g3u+zMqyrbSotuT1zx5
Btz7fp6QkS0jSFgrIS61YCsrDnapc00tGjpN2jN5ZKDfc2H6TSjf5qpS5Ass0+ZdzxtS4jRNwgDl
VhRxis63heAWDRC1ZEkDLHLZCgy3nZH2v893LJa8tkQAJfZ3s1/MeZ35roUgXWC+ByFVN424XK2m
ThI4eGIjljzxo2Ers1e5Skuox8RRAwjAOFyRhPI9OICXWQc9FAwiPXZoKhovpiWerOv0Vg8nBaUY
/Bom/I/6OWmJUo41ZEhmtjOEtvr89rMMB79rHzXcvd+ZUEjRPjAwfKAFQhG7JQRZo4OUZeDQblTc
jatt7mJ362vP45KIxLA8pq/0JlL5XmQaftA72rAkZ4AP84Rxj9be/SfDR21074+9hups9wW0FdTC
BhwPi9npDE9S9RZCfknvgAvRKeh/w8gVcd0HKpskv/U9uUdwCFPxRIe24N7iyXGvNxrC4cyeaNk1
0jp8+5kbM+VZhSk6/c6ee3+E4McwcZTGmUD0C7DNzC8XiIjbCyshNTmk5VOaFk+0xgnHKBWir5fm
1dTpYYKtMiSGBzBzelnQvIXG7KL1Pv/YE1n1Ir3fUrVEt0YRenaJdHqf05NfVBudzDmn80xNlFtz
isGR2F04xAz5oBBV9emaSUWRPewhR0K1ZgUQ3BjWWUd8cGVBAk6qv2QfBiiYTSu3tm4mv3dlKKOI
tPRqU0iDnBD6FYjM1i2H/dxiMAsRnaMf+5u3RXxCJnEYJEJw8gSMwzX0zr2YggGZDRdVnhSmxbn+
+ISOgYONaWt/ALAxnf243tzKXzEEkMrqxC7MPFr+thrm4wItodHJDURrK0v7Mv5iobqo5WQxGZhd
+6Vr6OLYiuA3fKgqY8KsfIIuHd1KQpsvCT916tXFG7IovAdxPMxXf6cbmnmELN1zmaraINEn9YOp
YutrXTLzxQDiLgPVdEnYQsHJBhXsnotxFx6uFQ6XKtPvtW/atxCas0znf4gJcJqFcbouFxLKAM0N
v2meYdSGyV0Wt81UHXCFUjtR9fxoAhEA+w4i9pd8IiPnEn/69Mm8awjsPJULaPo8X6QFd0sBb77a
YUtoylTDrfc4vnvqv15Ce8B9iwkqbDjBe0a2AkemFsbRiY0NjPA6urxa0iXcTaCVxi3APRWGSvJN
PdzXf499SocfqFmlyfqLvOVrSB6wabgjJ7ab+UgsM88vxSO+FwxSbc0CrBS9OApl+dJ+OoGMrs+x
U/29pd3OvX+tzDvz1ex2K7g61HNa8Ahni9qT+jZMnt5L4To45XgdUt3Kv7mCHLBv8hcesScPtqEV
BK7iqk7vCXkqONSJM27FkaL3cM1oqp0PHWmSiL53+SP4+g6Zu/RIYzVKFweaOy/mD1bFbLGE9a5S
zkKDRvAj8SedBKWDUM/1cwzpFBJ3JG3Bq9JJmYAzUW3MyFqb81xgjhqbsLR1OL+B01LcNY3Qj5qV
7DsNpPs/K4VX4lIMjVPNHhN5f3fLFthkIQpCDjrJModr062+L8y+TiszSJsdp7iCDeKjKOoBIJNv
+824nKrCnaBP1aOxVFDSpUstfWOi8HvmJcvJQd8V2qZ5KL4fB4mcgHPdRpJovjKm4H/WQHHceLsb
oRWYGRW6xdzBGRXEGJQ6NRB2IjMt7XtG5E7geAbWeJpgQ0jOUnCR1el+cAT66JKGIc4+Tc2lGX9w
YoWTKYiDUy7FMOkJ4Nsqs2vkFv9v4YBNjvcOg1W5Q+9LyQ7zOcR3k9Q7H17XR9sFpB/NnAE13FYC
ctzsSRoi19FTcepIajbUNvUKVy3hxLP+IOdxLlbC58DuM5jgPxgzRX3R6544GorYEU9JbC8dzIV8
WoylNmdwOV2bx5r8aSfvpqzAVN6kffy7pTzsiCMBz0Xr3tMmMOUbtzR8i9KRrFq4+XVDW4V/rH8M
i6seYuqLfSPWKJx6Et7Tg9lE/9n33e2+p2MYTQgi3eClRnROR2Jx299/SqZP39q/tiBMzGQMFY1X
6Pnk9NkrIEAsPUX4FlsOvfyATjeryLzlFdRhNCm/kfp09bmJuAxxhA6xQ/SPNh52yV4EMJ8/zGN+
oOY1nFO0Sx1QVN5JoMx3L3WFQKjwmxjAZfsBoLOAIi6cmRVO8FzVrSf3SvhpTwAYNAr99h+7y/XI
8aoPfUKINaYejJ9ghFY9O/vB5dVpuGwaRl7LPziEQIIBjh9IfwqFoLuqHNNVJ2CHbq1FqaIl71cw
W8sTaeuX+kvT/3XGiE1n9UsMGQwtpJlzy7GucmDw6+TI7GbMOmyPYe0rhbXBlg+NtFtejcWgebXV
DYhM8KsUSBhc0RjhJ+Pl0SAj3uIMPoYUzgznPOjBv+d4iOMstV3IEMg5v9qHeDbAq/cYg0BrVT1/
eTPkjsohOG5Oy+YKUVnyl9cIKJnY9KuW3Pyo6ZNW9jOis+I4qS199c1VZ+IBTLaJttv8gnnO1iXL
B9KNxefTQWgpBLz8DKDSXqyAYivrBWluKQ66nWVDGttKWn5TfeqAe7rejRkWGTKV4S4kdXIIsQZP
EauchlICIvlIT63V5D8HYTcBGoaV+6Xw37qlvvUbausshDgodMM787r0KTIEmCkw0ur+HRd8bUZ1
wWZGKzDmEXrWa7ToXv3YxaLhurqoWFDOOoh+TjlcnZooE5VyQUDCv5VH6pT6zwUTrrMEHizT3XLi
pSl5B0Amba5+ox7EvkXAykYgyrQN1w8S5LqR0ySsoKWeLLN8SIoMRR4GUkVrtemlmWBgqjo+FeDm
TbL3+7lXWf5QVp98V7T/j1ntyLGnKzmNtIBsNEHvGPooVdoUMWf+iBpvDj/CI4sKoWo4SItIFN4W
QGOuYn3yGWIk0H6BMGpmaIz66LH3ZWrycXWAb8187qliJDopoYGXCFk37fDcQaM4+HQWZHuGDiGV
vmor62oUxrX/cqvLDOGtE++c8fuVr0jSf4vnMLQmcrdxsjVTMOCOXwffC/VuiaOHqOyzzpvx1TLR
GxOfVNIvpSKx/d2iX0QXSUBFIvY19y00fmBHMhEDhTmjTxGCDNnmyCvDKETWFQHSg4fpK7W221mK
T3v8AZ5vPMC/6NpqzuXUPft8yizyZaTPAi8FTYiOwpE6FNZhSISyorfBReIRTkdVDy1yZ4pqmQT/
Mo1+VnETfvGzREIvNIxxi4iv+zPf9cc2sDkXB9XGRMvTH1PfJfxoh+f8/oNPqocPoBk7UWaFmmU/
8vHGORV4yoyr0SvQ90PbX4+2MrRP74eUN7t7MrkpmZAFN/pQqwA7anujMeiTiOwdpBMAAHkns+5V
LeN6yQfzMBJqGYsPzVcNTfRwMW4/7nh82Kf8VOACK4lcJ/ntDgaldz0A/FCeBKyV4R2cNxkX4XBg
Z9VyHVybbYLC6i351e8MLgWWHLWBUpDMD6oi5D/54dX2gUAXgyWs69GL0YkxIz/YbQmCfv2x3kb4
HkltiaXsi1NHQ/hKR9w+gln8cEf42fOOG3vTwYVpy3WW+Bj0EjzQhEvcfpZIp3pEZO7DiHv5E5eG
jiGvait/Xd6iQaiwTSjOArNRXzN2CdVxXG+hcDLaund4Rn6mAguxT3G34ACdO/y12zG6AfHdyiYg
ocVW1Tg1CR2/RvkBmDr7OiUkNyNMhkUxhHl8Y4fE58lSOZK9uWSlF3zTn9sms3ReeBFapeND8CZE
ZsvhPu7U02lDQZlnPaLa+iC8QG7IpEXSiq/mTC2+dNz2mHq5Gz9UD3eZJjRmv8R511JzDKrfS9Kt
pZlisNmHNcSfvIvSECT9QaqaV7hnd0vMpXJPiGoPmqXG0YS1mkPQygOioOVqeqepwtgS0cMocFyX
HiVzyjqfkekTKsxrw085JjJLC3R4p3zwRXyEoF1LqcIC4xtso5s9Fy9FUcWrASl1EDVwZ4tHeUxJ
rv277yfKHvvQdxLRG+A5rGZRQpKcEPbpV48ipBILBYUcQ1ng1da1LlHFmGPXVmeUM+tLTyEyTfdo
g/xWl9wLStFBPyQqzo6oC9dt71DnBLUChlaFPOBxFwFW3EdvvdZQ1pUOZQHIG3sS/sxmltFzD7OE
fOhv27i3eVe5y1BnmX7GtDvk7dOi521mnz3G6zJsbbR4Mvz2w4I8eY7xzDFGnwWE2u9E1sbZ9VKe
f9TnsvaGrxK2Xu33PZEGrMLmCq7OtlM5o+khOmJcHJwtHMdqaSJhdXNYobB/+G3430cTg1x0sLvs
TGpsoZW+2l0QWlfNGLcA2GEAsZ11Z/PhNfUMlQr6aqcSxY3V9DEj1nIW4V5KiS+A89Cs8BriELpl
4js2NQ9IueWCXXEK7YPeQL7i5pa9+4gvQYD63/MDehW1XG4Fvpa3GhQ58OMYhpo4AzCrOXrWN34O
fj/WJwbcAwmEk56Ds9nsPO2ND8qtpxy/OsWHgIjcXJDQX06Ssvb1mqxJU4XFvabh87huAlccH7Nw
tsivYiT8Cr36YH8gXpaksZngG5OPM1HgVL3sd9Ol0/zjOCHr+i+R0XJI8IOQYSy2qVQ8cjvDYvux
PLWJb6BoGSGbZS3+LHSuq3c+4K/PBDUMcYzq/1MzKRnv+pE5HldJR2+Y7iTRlxVzsZRl77hk3eu8
0GvWYmDRbozSbj/D7z3LrbiM78gXcCFgNsJgOUwlv8BtGh29+2k1A6FGfxYpRTqibyvD5YLHnlfk
xnwdeN11NE+GviPpIwspL489I3cV/0kf/MWTtDCM5mDVa4uD8ewFPOCS2G05AJD7Kegg7eO9TPyb
xzg0YuP6QUL4Yo2uBNUgMADIyUFQYUTqlpw83/I079z7G5BqiCb6jhwdg1SimegXkGZ94f9cmNhJ
scznhr7Gt4+defupeVCrXVoMV2i+CBxOY6An5kHgZKUa1gS+enyPK4oJ1T/fcRsy1I1TvIsFjA69
3oqMe1FZRLDX9bApiMXwRft2FWZXhtobAAVbxb9fmZWaXciMCL84rTeGQ81Gu5OMsTVRKQRoRgTc
G4W0Zy+UEopC12rujlv9obi5BRlVDpErKyCtzWsmFxQb+Pv167j7W9hoppBnbRRM8Zvuixf8cAi1
nmR0H8WuaH3ZVUt7g3XA6tj+4fSdYf4R2mtX7vqAzNcrX9FK58TlmWaUKA2KqS4yKHdsCOr174mD
c7miYdnu29sAXxsws/zmjL+sJnbdqnfqu7L+oXxewzqWo65sdcNErDWEKZ8aAvcM3gSAG0rzZD8v
G90tmkNhHTyisf2yMh7oHVBpToEh3BUSFowiDQ62WMj40H7w9F/zKb5V7XtvwxI3kRpavP64Hxhr
jy9eAGuY4JLKE1Z56Jlgf0J+w5Md9omjSHB2y9gWdkmnZMTBcpqu2vVmo5VFgPQDxEijBqBAnBrF
qDNuWJQUyzV0vUmNok2qbnuJjC3p0BHVP5YQOm5uHiR2rmzvM07vCs2bV83OrDfvohAizR6GHXCQ
V2CUIV5tT58T3cUFWxB++3KUGDPKVLyHAS35F8an5PMsHg2o0lR8AHkO7jtsU2S4hJPqte1IyPGA
hXh51LjCpKrvPbBGlSiKyWBgdZzkamUXR9EIGQ2YbyAzOp3RtBsNsVCEddrQq4/0Ee31rW5ltHOj
W/1xQnHICMo/VZIZxuwEckfJdxmDMGo84VQY6R+7iK4DxV1u9zk8JrGktXsF/6JT3/sJ+lQLAHYw
bKPfkCGkj9Z0i0fJ/VOeKZ7NevKOo1Pb4IPqUU5bgxFF39SpIn+5lONSYjjH7P1BfYx1A8L93zB/
e8Ll+MgW4OTWbFR9j/3o3gBlFlOf449upAX3KBSvWkEsWiyCogHggru5gIgwQ1w07EM3aAIW0Q0T
DNFOnjtHjuK2cXzUjI5ijkKjr7Uc24qX1/jI7a4acYx3n7IQV4WCmgd6NjS7nf98IepfLFpHgOec
Wr8t/hG1u1MpQIT0JojI+UnrUP5Gevi1LWiN7KnWxUzPH8cJ6Ud3Wc5Z+g+ehcrA0kswR8DjyQgw
Q9vLZth6u7e1EyevPC3KBejCFjy6BbS2wapkfbZDcNWwp7WltM+xTkqKUkcJeoecBia7ZoWvi2YI
lSszlee7gpPCAzmwUYfSyOMN/Te4rs3p41Qyhk2vG7WG/0bDW6sWOwBEXa0htsxiY6EYfm3pRJXb
PQs3xfPBCpq1XjNGhfWeoHvrSISTCrZgk9pEJUUtUkOP+OxCeSWeap3UJCVAeudNH8CHAjHIe91V
GDcniYt2LDyJpmTeAh4wCnIilxzUmVAXvoYelo/BgBIOG/5nUmLL6SSWLU8LkAl3U9NDkrY7yL4n
s/uL65CoRHnQ3AmLDTV+GrTYgtA9qFZehyyZUQ2Upcpx7F4PmiE84IF+WsYUMNNx8/J8aYT3A08w
l0bFBF8Jq3hVjgbXwMPPcp/hfBBeiaxPnETYRHus/mOJTDS0u1FjZ7d0eD90iMBJzcIqJRAhU8oJ
nN2MPw0LefutAdV0IHq3YcsyXvE21v27Tx1G5CyY8AWwof+GL3CilI2sdi8ofZFBR+huZgIdH8kT
djYQNf095Afgkt4NTDsnAnS+L73d90OEwAsga9pf6hXSqaqn/T31AXXTIb4Y4FNT1j4wKlpe/qF8
crYf1umOm7YoPob8/ZmXqOIRChBx93t2A5Nnx4U4I5y4vflXKb8AxAB1gyZCt2rmI15XVbz+sRHH
qph5llJCgQovjGTyFQqrSbGkJlOZt6xSwPvKsIvLoyjau32GtzfL4CwgvMrATjcjdyARuWakn8sf
I/mQZ3W4P67D+XpV1MGfmXT42gqPjIsB90ybtwcwD6by8Lr6X5HD59X3c8TjqXZet0JcIO4GGUMy
BI0kCytXyZqVOTZwWHkhXOMJ4pZzaG/R9SBShR/n19/FB7jbZXrwx45prjEF9a11sjw36i39xbin
bJxM7FzOU4dHnzx0W6Fujlvgo+NV5lESp8Uw/5a91N5/bX+TzzmYJBXVCQbrPUpZaZhRPhp9TBHc
rhasaLVjglfJOTtrtChqBHjBFlDVhCHAbBT7IMlx+DXSyWIVkk3d+/SmCgkDAsVQ+bSab+ENSdrL
fUcvyQnYp4VjxEtFscRpmeQJ8xdnvHIIDiEuQ/IAPsZ+MEobxgxEYGhViehySBe4Xv5bQisn1unB
NFBOzSejOwlIjUCegHV19fs7GutTx0Ck4Ia3DPhlEvwNk/uzRbJlg1Q5z3ho3WIiyvfkdBC9Krpw
Lrta/O774G/nP77QprRJtgAoTG1elEWCRUCmocjH+OPrZlVIx7K2EJ8JdlNFfqRC9/3+6QgcevjB
fXbtqNK8g5iBKq5HQZ0qpklZCz+3lCK9Nxl6JDlqyowYqwzreq3IMQVfxaQBiA6WSdRzTK+9L7or
tR2VncsleYTMUJvqjMTjK6kPvDgWfgHwU1lvoljBxJQDftVUdBSGdCRjyH0JSJ9d/LnPU8QZKKVR
de7VYYpTpVmWAWvEK40s7QNGEQCzr09NCqs1XJrvLIBBHuOJv34dfEKZD/J4+ANVy0T/tRQMCIpr
Hgdc5hGs0/yGqbG3j+BNHkMdcMxIqJNoQe0rPgCue4toVeM4qAXtByYZljkgj1mybmY8Lr6bq+59
0mfhFwjRYd7QcAo/1+TBHBqsm8PbGDGF51EQmlEAHiD/0U8uhggGy+bwYugJsU2hyG/tQ/jbO61A
gncmff5adD4fgFb8yzIRPqJzQwOr1rqK2WJHsVRL5JAIBkv3usB48mRif+yexWm+enJiGXWoKD5/
3fuzHKqLf4VTTlAJLuQYdYQzAQGe4Rir4Itdo7W3IA+DVXB+7eftlFGRIGWcnTbzThfpiya0WIeJ
R5Z8NMPYiOF2nJ5flgxK8djXwu2LZMDfvrsDvNcY518+vpbQhSu1xDRUqOAVhL1xWG7lK3mT9y6I
fGp9gXDgQp7Qm2N4dwJa99NasTiLOksNLTqLxAIPf6y78+Yua2EiYbXzfyC7USal1Gtu8talAuGz
+nMO4V6cMhFPnsfYZ/Q62+1CwY5bcKaI+eMxoT/UPbMm23L7T7/d224eR3l1kEfzj3qzeA7FlmD8
o4x6yNACsLCsLF1ixLikB6KE+TGw3s3X6GcGs245bZ0lJSukA9yaNxnsw1uoAGSbzqU8cCKJVJiw
eEyAGvS2iW9uMvgyvXuPwfcFxpqva6CnwUQAVMkYzmzrm+sH8Iv+6P124bq5oy7PWSQL0o9AlBcR
GVhujUGxXdQ51o8FWOfErrb9Y9olwDEE+jWLwCG4pptFGnmhMX5d/y1S7/lwCIdYsw93Al4lNflT
OSce0LkOgCy6NIYdW9NhGPw4XkYHSRgTDVQuzcEPyzIhGFm6Oiq0lYhW+QJu4MbQVL4k4smK/C23
cOnhVeU6R2RHiiSuJFpvK45W1ZGpXNxoNXk3CqvoGAb8TqnQOQFp5/0AlxkUKe9j7hL2s6Q6wORp
DGA5kx23iYbP6p4EH7fxT/7pXgvHi69gfhX37iEACAYO/wpYeWMRPMDC47DNZiITEzAhoqyuiQET
m66pEYsO2xdygfrKujP7qBQBvyxOjKLwoUcng4IeqMbcA/AiMHxbHyAySJOyvvvh+EkI8YZMVVbb
pz0j24LNsTI2i4UMDzlVDB+DaF8wNpkW2sXE+HK72PdgNJusPrAb6tFRoarJAGwXZmMVBj7Asl1H
SA795hqncUMamueznXWuhUdb/Tf36vksjNJxdyYLfYnEkuhM81APJMN43VkKWl7xLa9tl+K9s0b0
El+PoMSlkxJyWEGiv1BPrs7cjeekeEGbNn3WY0mBYNyGXlkJ0oPBjZ2TlIsxGXhnMz5JQiHoccdE
odR963QdS7echSbmx1LAJlcBzzUqvjbaQCE0rbKlki/PIG7p95/jkfuSZyjYtT/NN/fskE8fjbV1
IqQCgXDGedtL+4y2NO5xzn5iP5QMCIDD8gFzajU7Wo18zsQ/gZu3/SG5adtSXVX9ZpXGTa7CBMZC
GZxctwp7nh1/Fl5+hzdU9wrarewiuepJHkR1OBHk6PCEWDCS2iuHNoH+6t3Nt0HTsrHz3X0fizps
UiIS4SmDeUtQgKyNYdHpBk2el/AH0MpVCyGqz/50ekNh90FUcD/NYvZUPM3Oq5K6HcGuFKIPEcGp
UJulYzaF9CoQGbt/j9Ue+YiTJQYDQb1RbWL7L4Bp9MktFhh1eRUXk5GgiykO7UKxX2J5i7j3mxi5
U3w+1Z0AklXOa2nqJ+J5Fc+7DcmP0GomPKMAdC9XO3IOv/63ql5Vx6BkOpoPMDHfDm1q6YQfI3zl
tRWNqLjObMAufPPwVSovcKds5WUPCktJvR+SVyxxPB6wgLRGhGSdx8mWzBDIlc4m1J5oR+puglyN
GVmxCkSm37qAfpONlaGD2DB2qtV+2FPoAaCh71lsHD1qajLIZkpOqA3KafrSZi78urUGxwxap2H1
Oc/8vY230CQngpuByncSqXpTTWmUNw/7s4Ewv6hbHOSxjDcZcm0gr0GuIPcJ/Xrlpco/ld44cA7O
EhKq8oq4U5LiFtogB0wh7Uzis6DLIURXY3MQxUmOHOPCexPMMWgBRRGq5Ew4yBjo/cP26E6wDZCM
EeUdU7WLdHkXhjSjAOQOx/k4LTk53qSBGbKlygrcwwd/Qt/Lk/bh5JUoisElSKaL8n9cIfN1qktO
HUVy1Ray2JS1IL+ZVJoyrqtnncuKeTjvW84jcUVYsYKJ94YkZ5Ec4iy89aOewY0YN9q91dyMAjXg
9j6Ob8wkxn8zdgrBFumUzst2KckdgKotZtcmRrQVFAUANjGBjTM5HzRIVpNdcog7tmN8bS8F3y/G
cBsM38H3V7Amz3+x0atsJJBxyINfLI2l5DYDcyWF22oghrrOYyovfARL570sxeQUkQ1ApWm/SsBW
8Sn2eXDQxcV29U2zNFDZ/UWnRbRWHpUJiQlHScrLmWgniD9jtNtAmul+KbzrdDAEb/yeb+PudLbF
8d4vLxTAru5yIrptqqj/KDB6TR4O89ZKrDlgfyKPCts735NCrXyo83KxXefZ88RnlORlnXXb4AlT
WrWsIdM+UHN7voK4xni2oyOiuLyxu1CGg9Y4j67PN4x2i0w9Lqutrq3yviyk8R0dhspaZiD/ixi/
mMFQ6gGOn+/rx1akWs2uETe4cA3ctmR7fM6hgiu6GnM5FWiZlZ7oQ8wuK+xdaNLofU+BjCHM/ohI
8SBWuEorwdvZcRIsNO9UvkP/oyEss7l7UMRgXZ/O+EhAjnWM3g8HHZ63Unf03ZihzYg+fdAUCBcB
OD23gF9gx63tGWybyC3CUI9O5w/O/qKNdy39LZUzrxf4um7gIREaxNwTn1SzLsRaej7ULvMaLE5K
bLp70hYCF8sT1Kei9WUomhXuqYTib0YUxIZBEIb42BF5vGs2cqaXmUSNOyiFPrZqrjkWd8T8bAHG
Q0a0D0bNMPA8O8A3WcGw74i4KcyUQ9IFliuVQvaVOqRxuWiZVn1gGF986zn/BB1nLqC1vudXQVs6
U8YT1PsY1131DmeX9GOVsAxylzNBDbTZlAr5vbcYDBUe/xyjHi9b+ZGTW2+SM3GLxbRjYgei5V/o
LjcSHV0gb+8kUmKpNpjtgy0YZwTux6cp1gJQPQQZ5GL//0PbPwhqyp384H3FVo/Xq0N36s6zm+pa
kp5Xzua4dqnXGLNiQImzKz5hgYtM9RnQ8vboMu+Tfr/mBuk64/pDjHUa/tjM5MG7uEirm2doFRTW
3/q4SUvl+c+SE3Uzj6K+znxrWCv2D0W2t52w2xY5vnfWO1AHvdHH0Q2arudQ6di+/AME9GiHxZOB
3+fl7UYJqhQJ5uAT2GZY7kN+M4Wu111yh/AO9vLUdg7ZQnBC0DGZ79rWuKk6OmBYblSqrhQ4Adxj
jzYA4YSmUpF8zXABYlTis8nh1qrQIOjVUd1QNb/wJ9CzeIv8Hk61IChfNH1p0NIpMP7vAEI6MYQ5
r7vvJwc6OmMT9jdrRlBHFg1BlEn+jbJqOM7vsov6TP/IHpUaqPXuHT7KWxSp3S+vX4EmUzjbYND3
t1N4omCxX8pByMPOT/uxX5pgwADwH3WvOJa05mLfGJ6BOQ4XHKP4TFQJrMid///v4+o0NiA2TxMJ
t/TNX+hju392oeBQDBudtsDZjGmlCh5+dg7C84m32Zq8M1eGGiNbBIi+4jJhdBAkazK2g6WdTYnK
oz5kkAAAsc3T9xqjghwlv3v7kVEg4OBp+p5Ewyjuj8XNWoNrPFVNoRI7lG2ehO1EQFP/UZu0yOpR
WQcvRoWQJwbXLBzJVh+JBA2vjLDMoplJWUKNLIqK3K7BFk5LxO2tiHV2OFJJNGo9jKsUj98V0beT
Gs6ZaJvMju+xZEuAkiLfnmnSfTXaOzxUdc6w4ItG4CT9ni+m/e093k3beP5IsTOlDg27JdpRU0iv
eg9ZP7DfIjOtdqzd1mNx/Ei5y8uOO3lr6rEZNaFdRjv19NMihLFYiLp/6GT98mN0UR7B2mjzGOxo
eBDAXHQ0KrDAMIJP6oeYXor3wqgUAQIFVJKdx29plMd3E/fX0w6G8frybiM+jrIo/OqDmxnDNhFW
bAxQ0yHBVDNcqzbaTi7dVTHMZPmiLK9v3Y9+b69zgGZEAh7MxEbcjitCchURefOm3BZhSNrgzrR2
R912fA2dU7HmsXbIRXm7+trbFd2fdnuvVJkuxd4ADmQtSywYWkvjwKnEYuXi0ob3ll9qlZDmV/7t
iMnIIq3aFaZkWOxhDm7HRzT2pYAXDpbjTUpCZ+0P8WUTiYdueNnodkCs2In0NDR2Ek4reIAii79/
x/SAGY4vOqfy/Ml6O9zNURuE3iNpGVl6g2BwYw4sBuB02Qu/63lbntIVJHKIeK6ZFA2w2c+HvMXK
0X1H8loq1dPcCtxLaBnvF9sLF+88R9kStq2T3ix223q75Cz07kUj4AYcHEQRGt2LM7wxmkGRT4Zl
JmRecnlJZhVzhZ3yYDV4n9DYQ+A/7S8tl/MwWoIeauidQ2vcLwTJ25g23hNf8epMtm0dKbUWVUOt
kMu3DPs1nTY3cknUaOtcm43hPg8gUkRRppHUE1ppbIPrBa9avdiAa36nyslOjy8I+fGgLvLPzZbe
wm2EiCIYPZW8NJggrJJOjMDLGJBiuQQ+Ep2mCecNB+seew/G4sazFnrtUYEFD25iMJDjDHfCUSl8
NKPj9+if3Uml6ipdQgm2A3wBIMMh7+XyFdtRg4h0XZCReJlw0zyTNxhxiI3QbGfVmmy9H2Vn3sdZ
DCEx6KD4Z3iXTEThAxhM9zS1BNlSPPJnBuWY+LEUGcnTVXmjXgXUaU3Axarvuf385MECDyesKuIZ
aqqmOOl3EUrtFdlLg+0pOPxX/3nN1A7f+JP4hgSbLXb2+VwExaViSiDal/YnGuoaq9toywn0Z+Gx
mSUVu7520OGqVPkrGkfas76DGXIMeaGHRM/zUverFcRasC4wF8UbeNBRCesrirQYw+eiQvdz7N3r
8ZUjwU7TIKeocdMtDOwwwHdkHhGKp93G2NGvEWFhWuAXhsfTrCQer85YEg2pqErMo66xglrdKQdJ
Q5FOab7s1V2UW4zs41zNvSuLjDk4wwGdDEzLmvI6x4kZhiZrGOTBujzJVt+BojvTbPiUB9bvbPF3
2LWY4SMkN5d+5XJYx5tjl7uLn6TYW5N5uWoROtH5qQA44JfzbtbxLLKCjMgM65SqzcLWHGFiFC6Q
wAP97j/aEIjzt5FS0nKXr167/8K3RZLCMve6gaRVSWxiEAPTjno1+a3yfg8kVxOtrLpPOPoIJtIx
C9kYReo/P1iB7QQB72U3ighMRwIHjzhhzIPjeCOC7EfmM2Eq65FPvAN9ir+SgLawub3a6N98NJwy
fRE4hwsirgdu3bil+QrcDJSOsqTQpUkC5MkykH07iha8uQI211Gy8n/oeeHeIRTt1fkW+5nAXaFU
48pr93+fijQN/1uCJTEkT1qcNcQswUApWI+eJZUun4Apfb99ERHEHU9L/f83Wkz4KUMW5SSR0fz1
9JDqsyrj35lU47xnah4PANdqFwugUiNiwr6x4ryzJOWDRK/f1GxkvYXw+hbL5ms8/JiUzhgknaU6
pwvyP8GeKOg5ndsEsOZSY73LNy/GhbcyDGTt0+0gsYRZBGNcpqZGXLLLuCXpnYcunJ+VJWKkWobP
xkH9IfUxHRCOC2ZdqA1Y3BAE38kyeXrpXjj/ucIrjNL9oella70GapqvHZFAmgiXkvsj8YckWoDl
RojoVujYuJJBIlV/neX57nueH4JfOHusbvuW8Yopyfv9YcnSudaLOvqUw6ho0xmYzPoHIjofeDgR
Nh5XC2YZZ+J30K6puxcJ8x6+KoFT5RE79BI0A+UyYNxt41S2u1lFy61i5C71e9nrK5OIvZjw7/Tk
l5CZmbARJvBrPFA6u2mx6nqLypyZ4/w++AtoI29QzVxW/mWTpbzT6Xq61jw+jNE0LoCQHK2A9wZ7
BGv9tq+5dxfhnCG6r1qI2DAVnZvVYT1YYSDHRAZmUL8QbO7DnixUA2zBXkycLw5UEAz0U4HY6WS4
OWGzhaP6XB2sQkRyKSDF5X3GDep/Yun5U1fMA7GzJ6SQJTttUr8WekrQkx5IH3/mQdS2Ke2NZ8uI
ZTrUeXXLDK7s8Xx400iIoCdPGhhIqVEg37XZujgJsuW/ZxGr+8fEQsBWge7JCOSNCpCMtgge3NXW
D2teAr8mXVrFjJlKsHfcvVYNNKDkkclHZtxaeF4aNJAhBDKibXE4vmmMdaiyxzwAniwXR/BjrpMn
ujtgUyZBdaeQPO/t5Qfool8cH/uBnb4afokVcFKVjplAovmP3BaDzmBvfBERVnKkm1RKGOZWWeG5
4Pgk3a6qKlBird+zPW3yyJyYqZUmI7rR2By06MKdqo24SbX0Tc2ExOU3e7cmmOuwot+6j9pZh+bR
5EhAXWUkt+q6RtKIVK4R9tapSR1hvlXSRc/Lv7fKYW+SP7ZwCjH4UGTIcK06uNcKknKvilrNIv4J
K5VTtNY3atwMMIa2mlfnn756I0KqlPEwZBfN8F8/I84SnL8TKyvaAOGEh7yTLSf50F/YI2sMspNT
9yOnAA5u6YyA/IbHbQiuGPb0IYuzPzkwBz2UtaLNbQiU4OCVFqNEdFvnnuI/uJHvciAXkl86XPr5
5fbeM4rYC7PNLJsZF7Dp3/qt1cG6jAOZoWDROS5vNUyNXsOOcP8umM3RPNcxzdwc9HCvi13+O2Oh
NS+8VDmsQx/aba819lp3gCUMNqJ9wPc5WUBJjcVgITAdaV1yWp3nS8N3/3WDnQXHwAcijEpc6Lp7
HU9MX24nElzA9s8sINkK0mPsGf18zEAOuyXONUaNkDniNE/te9gWWmYReM5fgj9AIXHNdBAy3LQg
24jcMNqAIxghKRULKeqjDGFiN01tK4mhow1/SnTqAT5QPCqSL1Lo4Udh7ySREfDnazQwH+ZDMzvU
8qMjlV1qx2ZaRU6zv01ZYN+qEzrsylsa00Z2hvFcDV1gBFeVIzMZSIY7L0vXlc1/GmSn3dlu8Ogr
N1XKmileenS2PXmXu9oSmyPp2gfTHJ4H5xC4djPdkNvqxSKG9ePt/2d9jnsOiDD2hvlgVtS7Vic8
neMjLcDHGcnIMYHpfumuoz0nXl4dQkgil13h4IVa5DTQ2Pz6+QjFG4XRwC7c4N7EU8AWkOhH9Jiv
ubMYUdswVrxsIC2Z6iMscy/LmmzCIuv+c7psA+qtQtGTLsS9RRxB6P1QVpZh4Li4aAkVPya9/wNl
IBS669Wc2b1nx9KAveL6HVNbKUPmGZkl8CEmcM4bMzKsw0rMHlr6RpPj5SwoFYkURykqWNSLTWA/
J8c9rpdeZR/A+NclCt+a5GZPZRXJXl19KHRRJCWeAUHYjjcnxjikfWAJcMOvG++uTRQ+BjH1SzNx
G3DfB2LCt3IgNeyOWUa+aG9/zae3Lkg5zbqdxY18cfFUz0/mgfMUTYYsZJVuLFymHOTiKCxhfmDk
35vUkTTLNJNNrdrWQ8F45iamyAWhH10Chr18iCmTOGDX+hdT+5RIyLS2WwtTpLbyNQZDFL7muCsM
Fe2dgHGd5JG35YY+uZNTJgtIlCG3S8L+mnUZK4RyADbPMcd02/kGyApCx0lv4Bf06k+tGm/qlMdc
qD4Kf6EZoMqlQ/rN8kdsDmltkR2e423Uuwg7BX2OToh5zHLXs1g2NCTkdeA1fl8g/Hx6RpINxpm+
zc1AOSz6XcSAy0YeQMCPGwzSx3pUJ8HM2jDbcEW4dDcxkDSMLb279FIiyxeLWPvMIBgnyjojcTYn
891XuLLRysd1YhAQeOebaXIeDy722NV9GSSQGvK9d02nLMQ8dU1ZHWO/Mngz60XuACu9oWzcEEFg
czOWdEZbbwVbvJd1F7sE/NFpFwmBYI7tEG+FH8dmC8TYfG1dtQ57q9iedO8cWfY+8pgbM+A0/enW
hau+HKvyfoCccrb3rKYg/V15uT/Hm9fQDN/FrfD2tNCXfRA6PM/q/Spyl9oy1x2Vuno/xA6Rf/pd
kwxZYq/TbrY7z66LZ6ZkbWtzmV195Bc8WURVOlnAtU/dSij1HiyXigSvaatz7SmjRxSjnz4t6JDO
3r4ibQc4KibuVc7TGEY/BY2h4ynw+JniUl7XBWz+Sbdm1soUUjp+5vKaYqTlSarhr7xrqpwuEjPt
B3BD5G8k4txtbVL10kerYIasB/VFnmibag3Rt3w3rhjJt4jUA0OXhCt/wLWzEYcPVgCn5+qaJEJT
BwtKDunsnPAHpDkepd8HoQk/V2VnpZAvKW6KKm74GcG4Q8qo+4OUfy9m0tgo8rQdJuKTmLCXaRvr
q00ROBcaNQ9fCNZ4eQOell7t/3emUo55nwgjuusHCZbJXby+iWUuaMOpLHhEIIq1KgFuYh1AMYEK
xq1RqWbEKTI1V/jmyV8AZqOKl/cfRphpxAScsCvLpHReV2GvA/8OQJBK4jMKIYo0y+kmtcpU5XXd
TnV8Qzu4OUZ8XPlyrnvu4lV68elJKuVUjR6OQqYVk9eihyrQjp4vBW1KXsFjLKXjco4RjOy231aW
0QPG7ETG/P1MMAHxi22BlVBCND4Kyb8aX0AwxNAuDFpW6h847ONVy/N1pJdKa36LFzuq8fE8jGk1
LKY4+uIuzslaybwJN+pVhejgmD+eipXDBDL2qQ5PCrZ11KM8fBOGeSOKkGOBb+MkPf1bff+v2I2E
Us8gEwExSiS3Mz7hzRW/w3tKFGS7muF4AhkQeqr2BkTqWz+kC5eZIX8A8xy9l4QgGltnYesKssa/
gf4ztacVSHZnsVp+BgGsi2yulk3KJd9NW5YQgiFWHYX9EuIXwC7fcdpDFB/drfFG2cnZImw+WqgX
JdYx/BE0eu5nvnC2Jh9SpzteG3Dw7XqQMPlvDeR9AozY0LsoQ6OZ9mgSuzVMVwK7U9IXQFv/aj5e
0PNcM2/BvhWUw52k0BPBKYA2Vg+4von3pq3jvXut0VmfVYC/QrnyPycpmMTSFvrYFGnyJrsNae6z
xn8BcRNiSUljEWFkReXUIkF7S9kDlF+Ilh6t/rMUCeDfEsZwglFt0fOjLXULQjiTUT9t5wmTIm3Y
mK9Lr4MIa8JgyOy05si4JuLEiSaCyq+Q3q53FRZLmD7vDldOR+BD1FKGbeuMuqVNCVO9WtMBCXbb
dDLywbP8xyAYbqmTIbiu3wWrWqoC9rrLGRZSV38GwNJOsD6yOLjRjmJm7cnyCsIJlHI9vQbh4DkC
CRhJOYdDX/AAY8zRi/5KjVQJOvVqwRJXyP+PWloJt7875lmcF2oejexCWd19XZD1Xgw+PI7SCAqn
K4WfzmkTTjY5VukPuzU/2WiirXe+PKxQ4c+WPStuhpOH2UpZSYKWKAtY48oLFANjrmZycPU1YpcP
9OlM/OsGi3ywesvDHBM+4Q2L/vESegyCrN57x4MCCiBRnPzrLKQQu8Kg14kZSQMQMstFRRO7Zwxs
NBag4Vajgan8zm4ssQ6IDYSpVuZ6G8qtNjStqX+guGEDrNDPrP1yrWuDS7MWXRh+FoH3jjO5Baew
bN9PtAjCmaLkKIhIxOii5Z60dBVdRJ2k4lxNmp7vUIAvfnePwNEwXTZTxAS54TpvByC2/fhN1HZB
WpZJH9E/7yzOFGDgpQFq8ePJYx3sCn1YnMjrvev7Uog/fN57kWio/YAOdQSjOM6FqhOer2WU9k8p
IQRYHXuvZt7zz0/6BEjfxLnf03zpdtV/iF8lUjL9tqUNfV1M8BMYKBocGKQ75bXIdKleym+lK5nK
2uYQdXboDqC0S2KDhTVAhASOUPK/MgLh1XKrGGqFQUcVvTPRs6pW6mTjrpaoEL6MJw+rgMyo42Xh
iWOBrpH8ADIEdD4BbMjLqpPp0bmBa3dXWATWLMVhIOihZwpRPoh54a5O9V75uzftDN+uTd+D5MGm
SCP+Btzkx04vCBEQl2jyXYS2Lt3ztuams3KqwGJInPwXc9KodZTTgepazGSFGdpcub48cokwWaVa
k+zU+DduIdhvS7T0y++HfNkqkdrkb60VU3jIH/JfnSCKKzYTPQw6gejoPqEhf7/jvUOyaNZZ8XfY
k2KhLUHCGLfv0Tew2p/OAfntDnD1fRe9HTXDIANiqihn02bdQ6sda01dhkbqr2+O3NCTmoL2mTen
1UbWQj/84Anh94oc/x5z4WqCMj2VWmkEIvzOTYM1XBZQCakJT5bq9E8+VQPGvlggn75H1aMXWmVm
vR9VkwTV4WEi+1B4T9LXP/4bOALleFMbY3UaO+VKnUQiNBT9JdNbjKB3/7y9jC4HIT7wQLI+95yT
ru9J5Dv55bW+tfX9C0TLJRNZibJeZJ67Pd0KpWFSZF17qmDL/PLx6EWhHQazkU9jdq07Es3iPQW3
R00R909g3X7LO0s5kIbBA9FNnZMiemBqQVj0ljf7LCUhhmeMUJLpb45k1KcEP6knS93uxVlJD6sS
IutCukRv33ULkzt6kRfrI5f8cYu+gZUOoxFYhrQNPo0pdbJk8qQT8zuLV4LFGZrSwJgiGNzECHD1
Ar8yIWju4w+gOyz+svw0G3bIAS1/oRB5ih7/UrwnF8FVIBPd9yWdhaXk8opltgiBTXoy2HJ+1fNn
UAw6smomHoE2yD/GIri3MLGzxYYhZW20UBMVB1h8nXA1ar8nVYl8BOK/LtRp3ZthWObpTQQLqRD8
tHujFspCKvGkuQ5PW9GPyX+XDbGqSrqjVVqXETyv2ABoKvz0R3Wrqbutu6z1/BqF7ph5J50YTUgz
uivui8tJKqLOBBga7ljCymioewRwH+6wWPhMi593/yPD47pBzo5iWNb4uh+cP7jfU2sBQybQxMXq
itsK2T2NEk16Ac1QPjSioqYHj/YlB1SjFNGHE52DnZy3lmHOFQvF3V8r7BtIIeXbj9Kc8XMqwWBp
EuqUabIHwDrqiLabhXvtx4hbHa+XsOtmxDY6sCZGpPNGQXRGHu2+UQzVln8l1glUB1yS7irXlKmc
LEfs8xWnKBGmmUlUPBBDytls4vLfok7917pZ7UlY77fiv6vKgfyY9LB2mFWybfNeCyiYxFWyakj3
L129H8+3LLZgNXY4KZdmsclgXmN18fPjpGqkTzMdSCrc1lPzdly9icgfxVr6KJG3I5tbNzjluOA1
7BR4TuphVclV2zN2ot4+xka0wkCawCtU+GFVu/Nq6WzQ7Pu4MlnqM94hd8lRzrLpASKswEhCADgZ
hofJs/jAXN+wxNwZjAs9j91fggUFdj1EH4h0hgUlPNBp57wZow4AGbFiFUKj8P+0fZtINt7Gjr0F
CLizu/pxiKo4h3cUmfl/K+Vt4qzgR0cunyEf81kSb0TvPlNgQnoMRHRIJASfDQGa/syThoBJAfWY
A13U8E/Vgu5abrf0XzzCmGpOXcWwmbBZAu2Zvsz1n3EtINc4fb7sgGEpaeBLF7yGvHtu3tbcUHjT
0Mx+0GEjYayysinJfC2uqFCJ2UoTja1Sir8eSpwhvvVjpEVx2A+ZZzvOi3UN5IxM0qHZRZ6oJyPz
RzWKOg6WwEP3dAwC7SYubEDy1AeOlhECVhsNB2muqn0hdCNH1pkOwSM4ghNHqWh+CCyYWK3JWzKk
f9M5xF4aK+qU+RQ6yfB2JT84sHfguOSn8/xLIPnbKs3A0IeZWZA0xz3DLkvbS9kAKuenTH6J99ro
muUk5sukfy9F/zdo2nh1kVQMWeJ2GYK+EROiK94IwwIAtojuuztcCMODHqUGZJMFWhZlugmsyley
3zP5pDjRv++Iz04RuBQFlqgJCPLaZp2mPxC9qpnL2Rvw5/kXdZWQi75EXJsKw4kvDsNsgfuSd4VI
VeyR8lEonW19EIahSlOse2TRINFuRh3/x5oC6BFh9MwZBYk4ghbzI96IhV9qf6HvP/dPi7RV6MLt
IUjFM+Be3+MxoX0Ik52el/Y0QR3TBDTzMRCFJ8FzS0ay7sOFaih2PNklr20qNHHxPbFHqiOd6Hjs
BA4zmm67RR/9czUGg5FKS1xumGzMe/Ft+IQlj50oWYvJSOgIjMcTNWEZdMR9aoLxJWzNVIbFZ8/N
FFHu2cYfhHIH8y9Y244sz7eIVk2kg7lM/k7LuA6u3zsXQemH2nvE+gFA5G+Ckw+5NpXEYibSOV1Q
T4jyF7RSoopGxG2C2iBqpsX3hefOatXTkLN6CC75EspdJVrIbGJG6B52jVxlo2UMzO+eZYxKvFuJ
A8Vz9OJ6Ho99XEiVFB46hpj3bOdN198rjC+ukC0v2gwu4lC5D/qHjw/5nA5NecUU+ZVaOt5wHDDS
VAnQ/8PBRRZQVk5neq2jXmu2sWfT1G/9SpUV/3vOCcNJ/cHg/WjokXZEB0OFBU3yL0n4ZguecVwp
quEASsIWLRcMxCPLM+PG1EUPHw8U/grI6eF2usBoTdZ7wV2P09NmRIEYj8VOyM+i4Go7tatSMSiy
3J5GNt2BU8K0ZoSEaAlHbzOD/mEVImoMLyH14eHa11bW4IOpWaJtiIvegCfkYhw+hgUa3nb+A1SG
RTY8bmUffEqN0W6QLvvFooowqHMUshwd8IuwkVbc68r+QoREA8cvIcaQBk8+uHf67LA+Itg9ulW8
wletE1XeeLsNWSSBr1jenNATnj8YhR3emcVAlwe3W+HvtkkZ58dQXvrlT1MI8FAiZXiHXKECwY72
XFbTY9JgFBAOTEhAB09dBcYHC7mTD9BNVRRmOJJAVLS2Be+4LEpoxu3g2LFQ5ROXk4c30fWL3gO6
fi1l7dezCwRig8yGunFxelZutWCrmT10DRvf/WPE1frkys7AzLp3Vj/u46H/2wvaEtwUx2PS2mwJ
aBDYZuwttKKJGfhd3G/cMp3oZff2LRUC9laVzWmcGiuGptnxQiraZXodW38SYtY1mp+GehhU53xF
YwDQ+XPUUImM2UypVu0wDRuuH45JUulIiIKTFQEK85jQViy3GV9i4hMJ4JwaQEWLtUPjaknVnZaH
2v1Af0FBPARicCT4bbiksLN3bBnqTBD0XFj74dDldd3NyTOIefuiObtO6GMt13CTnZiet/S1YTrc
6WdYS7K0ZCi/5uju6BTqVMW1Ev+dtVMfp7H+CN5vhmp3iupZjUdO/iDswEKm2dVREA1772LzSO8Q
KXBmscirQ0+8mLOy8pdk1mLDSw3BUDRpZeA4wpTOJLGmitnVRYedM5BVuxXs+B/v6I2d5VF5EiYy
9S5Fi41RozXRmDBoj1JtCaQwMjG96udhbDpkNa7+FbP5KhOCZwHnGPtn2kL6mH8sirOkMUFFWwBp
2gDbcFps05Pq3aSpiq8MGcaqhQZUg3EUD4oc+pTB/qMziGh8EBvlDApwUOSQ74b5TGvQfvbupqia
T0bxEehItP5Si94XBzKwwlko+TJ6FAf5UBOOSw/UDJEBAK25NwwLH1We7GU8gFngygSjxEU6ilbm
aBkqfqtf/3KiLkVJbI2db0gUYFCQqF/keBgIQtf611Ps2cHF4pGpPJKLSPfXIvQHRmPwc/lH/GZA
YzGPLWyE++SPQp9uvgU4YhzZU/hRid7jaasCWqU84RvquzmWSj1WO857zD0490n+Np33PAYEGbj2
Sr88stVoTVcXa7MXsTvFxO8URsyonJ49heNMYUresexr00F2iOAHtXpItbawoBJxhSLyCzKJ2kxE
/8DUBG6WalrbTB/5TOV003WE42Z7+VJmjFqKVtUCM8vayQhoeCqqNQfmAp3AlTLSsFR45n5FZbQK
svJpnjxlExdDAiVQVFycsI52hd9jaqlLx1PLy+QSUyVH/atJ2rKQLxcwIVh6TRrWelHcC1qGN0vu
mLLDE670YPa4wJ3mKTVq4LiPiudcD+dBCLS/+K/XYm0l5Jzt74WLwW/hVLmq6ejnQNwnKFMElFgx
n8ZlNM+3trLmEzfkVz0JAW3jA3NU5UAEHp78RXxPk4dHVtrsYsIlQo8g1rI+w/7oHHnZl+SvDsC6
wgFeCULoad2F44W7dlQVCFuPN8aKDQF2v15oWedYMqDxIQrv7f00TsKtPTkISsRb6nRuV7epO7To
OjCtgOETCgooXUWMi2h8EKEkFr8ee9JUgoCtHxRDnYP8kvsDljByMEboMZaT7OeGTUkvGW+nEw2X
Ulri58FyC03TSJbtXXeqkGWSXMjt0AxYIbieR8xt7sGm46ZAtnle7OCnf5ni9iiw+8C4WD2w0BxM
d3/L0X9h3Z47AFj6rDLcQkmhwYK6x8AF5jKGW1jYhAQXqks8u1g2spwi0JfWDGwGEs5HEkpMoXAs
d39OVLuN/63DnI57IOqC/YXqWSiNxBfAJOjYyhqBAWurREO5Hc1iz0HVaeI8FrzcRbd74s2Azd8n
oBUIHq4JHgReWY/w0WN1M19AOEEzUaDQY7t2NIRFoxX6t+yf/DIammEHvtK6dW/O1H/jQxtyQuKo
mncI+xUMrAxYRdOWYr9y9jzLsxAmSDztMKdNtNeyOHnO4sR8EeSRlhfUAfsnqHmbZby9G7l05qYz
4V9XajuOHZ08j4W2UaXTAAi1htLVDqMuuqRUbMt9MrI+L2pFtYxAAY6flvpxSP78OzsQ723aV+2t
gMNh8oRNQqlRNwsFSe0526gw4mCUulc4gElwqEAUv+wjF7gNEKZ1fQCVaPC2Zr7nZR3iME+9uG7S
rrgr5F2DyTwHI49ggkxJ3YexN7WY7tcyN7KnZ0bZLCJmHZlcR4pyphbnp/CC4EshKkoXyvaNmz/W
gG5j2fPiA5JhKC2axdHqj80hJtFylHCJdbEPSTfAHEzOiD+S16WSthEqftns/df0a+1T4tJeqvOo
mXqMw5GRFnktmaLfMuzDaeGwIpvtsjvxrVKmJBLCBw7+ad6dc7d+Imn6NJYc08q1vLhEWi4X4F10
pIgEZ+2MuKzbcoF3SMRv0AcpFKbByaV6nZlDhZYyJARE0mN6QqtMt/8RCe77betpkaOWnebgD2LV
slcZUXFaLkcP9NpBqfXzFzPf5REJZ+DnbLS0bV5iosx8jkMeTXsylGK9Qq4wrT9j0SxZIJg9hs5n
AXWu5XG5YL4CX8G79LyQVv9jq1Oy9Pj8O8NSFs9omgCiFcBJb5b+JRyKQlqD1mZKvsCtIL9sCu6A
/5ugbITZhYCJQ0/OTVFE0PfGT3Or/yKBT9ShlgXou7SDvGO9zeZnuAjgC3koc22ewVBA47hJpcOF
Vcak1ix78dtDkU3yy/nn1wa5uj5ipA58XfHKqLOt7RKVpByrq/brgd9TidWNPfsYLUcoSYnW6hZq
tG/dwgA4wE8w8buBtl1W3W1eP9PoECkudEwv/sWAK9K1nI0BeeaA53PBm78aDpup3dVJPjfA0sgy
rqYrq//sM19FyZ98EEGjREKg9ibfuzxcTcO9bM+6O4rjU7JInb83mx8/+4maeRuXFjDosbPpdvWp
XrTI0eheXOL1NaXfFmS+TKq5tA/jVtPuBOvEDO1o7cp3GAhVyVmSyFtDTOCm5KvQ6con5/5WS7cZ
1wpCcuZr+1mo0y6jhRiyasb507wqpjIqNCIrh2zdthaPaiCk1aXYIqg8P2zPvBfJlVKg8Y6t6KXJ
GmtFP79SwORVFG3+lt0tT551d7roYOdMJDav/osZ2UY4AojoYoNshaI3tpa9BeOtf15SOqY/jdt6
zE3Mm4D1LUPsD7LCtqRLPYeWAx7JKbErVnBgQlfSfElnFx2pXhB7aFfObT1NOhmLKtJDDBTkzJ0y
/2Dd1GjtvVZhknfrsKyCWotXSfRzLvPsnct+DsP4fTf0ccU2CAgFYKp6eHWFx2SZMAolj4YbAo7t
ExwivUOOtgk4iIyrJaecen5HiA/5v09Nzfw8KEVV8Vgug6bgTW1GaaIoB9p3HjoYLmzFDcE88kAu
JWPZ3CTeNuIgsHv5tTnD2eE57pyQM92EukSFkRnEQ59dTusn5e3dbgvzpb9ppyW8dZAF86YZMEw6
p7cb7NQwr4pBko0uGGOvGyAsI5pZ4ErsmWW1hCteHkm74Rm2+VmtDw2y0/VsYbOoaPJShQY8+TV6
pP4746mLMKFA7DXH36cBnd9ieZ0oa0MwuXe0Ioa6xtQ/4ZPSQtxlg5ncIRGd5YxQ0TUzRc+9AXuc
kO+1qtO5d5tDfJ0z1qYGMb7TuFcq8781EjESxCxpk9U20MfpP7mfwDaa+t7NvYkGTq47up5fTbZC
UiQOeJ1J9KbUYtpwsqBliHAMMmVipbJmxy4QEQV0GYm6RNJ4WCtXKACbnTJ/fhTaXx+3g3+IM53C
d4gukUqN6Ttxu+LBDX7bi/joCeqB4awj7zkbBMS/gsZUeMu2Q0rCXdcVJxwtzfi+Q0fFRiuTb6t9
IuVY6Vw5vHAT9y1fYDp1inuXETX/RJataFduJoHE4wUzTtJU4OiLZOyVDisq6g1Lf9hYbh3N2N7N
qJH0BtriedF7Vc4XJXqzjTbO4J6i/ki2bFTGm+/loqvhUV5NykWQUm8Gx8IQokKyXxQnt4Jltv3D
3ftqmb2QQhIwbV1bxOQgyTeUMbVeMG75OTGMYzW7aXg9vZlzCLUoXe0uMTfmfmIq+dOZmw5Dc3FW
a2F14Ejzkt4jxzmBGxl31SGRlHP+q5BvDtmZuioBXYp0JOCKk/a6LWMa1IE9L31T8/s38prIqz0w
mQRMaEY9TlMTtufcGXJoY2ZmXPNLHmMfOuqGeAkP/IsNcMRY1SnlD6USFJvOh1sR+ORmG7OKMqAi
TwV2Du09N5+fzvDhGCHMErzztXAmdOlOV0MfnVTTX8s1nuhTXSEs6vQoTH82NUuOLAkEbLYl6Oy6
z17tCNEJgnWTJGdRRnuhh0ZXGNjFQnbn+u7TWGuZ68Lp9EBfQHsYJpQd7Hs/ppE7VgQsV1kHObud
FVS3vNQh3itZastPm8+WfV3rbc1DddHgLVy6REF/v8KR1Gad0hLaqLsH8YWwcaA+8PbAdBd0hUR7
LB+WudAhBIE8DfGGTI7FNDme3cgS6EKP3NlmpMaUOqpADhrZL3eS8tu4MBFfLzoXHi6rEoL0E2+F
bK+AQs0W4mrjn8omJr/F4LvKQ1ZzW9hZDp+UM4rEQGyAKsr400K9T68f9FAJk4+/8mMgVvVgWiID
+0Bamqt+Rjgva/tw6Y35eNGKuEFykXB+OUqjDcAUHUAypVNJrATjlfPZbsWsX8/vpFgSMRJXCF15
8t/bze/QCJ6zoyWLstpIh5PUMdnSfSNUY0vb6lXnk6w+K3DrgZPmcEersMDy5ZHM7+Nbc16ieyWm
/8EXvO2tQqEfw0gNp5X5dIhgS1bIKbX0NotZhCn1s/gvZfOR1XicRluOJNVqXG4DFq2+SNjUpICy
xOMF5piKtqy8/mgvZUCLt1v6cged9/IAQ12EcEYyoxWJXms4K2nioTQXrkqA9voMSBEHfdOijSeL
Ms0kaPd0Rnk8hYgHS+Qfoobzfh1Nu266EWPozA/ir829UAM4q6B1hp0ViZAq4isLkbSsM226qSH6
fbVUbtMbeJqNrof5cmR6KM1LH9MRpJgXLYXhx/JqgfXl3wV9hEEthvokhzVp0ixDGkzOsMtD/0/w
UfugKjOu9sjLzmhPdmPXouN1g9/kNsB2YGVAFEH88oU8wfwyVPjT/+/8abkZhc/kcQsZHhZexaC/
m+79AYwSB5qikntBPCjUhU7u9wnBI8R3F1s4eb98OPV9ha6Z46EpgTaOlCiuL6YPro7bcjAEaL3f
Ca6HuyFIG11iPMmEG4HKAz5DBsdWztwM+fVJGk4cT2X8wcPcnzbbetuxwHSYw+NicYP6I9cn9bCZ
Wkwyj+raiC4Db2SZ0+sf5gSfVmEmAiW5mA/EU3R9M99iSMtDpG8qCZ6sMn1U1XNMsTpJDHHePhqW
OsXqXevarFG83jmWV69plA87unuQ5uGImBdQpgurcmXttIEbRC5yUn0tcAc4nTImTtnrNig7rgp2
+QGxRb2q2evsKwLTjPJnNU6kUNIkoZhdiiFvqjbbGCcDJ4WadsBokG1+3vE95PCBFcasTm4kmI56
e2G84rSt8awUiZtBnWVamLOmBPsu9HHxSP+bC+Iw2nN0D+6L0VJvSiKphS7HY/cQZKS3Q0HYmxuY
EaKfUD+fpU+xEyfAfFcXYwnjRdHbzIBbrfe0Z8SCOSMqFP3R0b9Uqw0iQTt3BaIbrhEMX/3/r+WQ
QPb/QMcVrQQUK/7KVY1RaGZCWuZ0lEUmhDeqrI2NAGD10i3JFSCA2hSiY2ngDMTUvVNsuo/S+6iM
48+fNHpzC1J3hddkoopa75da2LicPk+Tq3nbE8ncjkOlXgcgI2+oJ2CcSt3EUM2Buglsck6V+wZx
C/qOwrk0Qg2DXmOtjAr3hvYHTFmJ9t2c9HMt9wGfmyp3y/UwZQMid88BQHMFt+s5b3fqCX2jGi6U
AEK3H7XjNzBjCHNQex4NPPM19uXO0sE7ZQfm7B2FRCBd1woth9+jhZuG+H85YwN2NY0Qq/58W7Xn
wMuYl9WPWWIG/lyX3G1otzmmjdSWbmRoFM5tsvGZgL7WgWY5cVl55z9/mVRtcqw9exWtbHU6/PSU
rRWij/mfFghRGG6to00MmnpfjSvTpuKJpZdnjI5dTYw5WdmxYg781nlDiAa91bKl5iLvYeMZ+Aup
smqP3YJvxRtCBWxoKKg55O50cOzPmmDOEgeGgFRuZz+X1wYjWKFe2tWemjBgurX0Vp4U9wWk8Cll
zhTAkWYW8cjyyAHZu8+gLLxZ8/eX6JCio1Ajio0uWs+UQ5KifpFFkV1pmoeUgHe/ASQe2rsKznn/
qnaF8VD1dmPZcmTMWazm+euc5/llqijGIvZzYLKJnqB4G81CTGmSYUJK/uLaHVrrLFHqyJMjUdkL
RZLbf+s/gkb8R+yUj7NHsleiS2KH28Su4dnrtEcbiC79x9id+cWqcRyLbeNL0Jz2pjwyxRGDsDy2
8669lepAWc/eSbEySUKVx07S8+8bluvXkbUqcNyPFHzShKnaEw5X6l10NQngm9z7JdBvsRA/Qx6R
wyEiWxCNjxHcpbQQDsKskYlbovoCoxME0SHqMdmu53sbAua74Dm9vyxLbGDgTfvawnBeu0KXt0dS
SbLqUiNKdaJMKimq3/mxYSAGz0UoXr3IgT72q619rsx2TVY0rhk6TuHBBPz2FMZM7TSEbrIsUKVv
LZrtuik3Vf2jUgeqsUBDA2oV5RGsGGpxxFG/6kpAbbWdj6rY1dkvEmLE68pcRM19O1D5YQ4xMLLM
k8KY9gX27t5twbglIdaKrrs3uLNjPg7L0PoyVo+ZczHYO8zW3QYLpv+tY21TXcvAzayFvMN25S0h
5DYDWHy2PsbxK6iy2f9FEG8LftWxXCIW6kjcwiSA0+tHMm3X2eO0yp/RrIA2AtQXIJg3NuQ9c/GQ
FxaSZeSnsfbYrtv1ZxIa+sLiDcxdbVfNLWwW4mHt22dMrL4qEQg/IUchUV0YoZb5ryJLH5aqic0o
4ePy9zNTCb4GCtTFitQHdz2T57RKlMXxu5OSEfFk/7uA+CxsIUmI91E7ZOBTxM1SoWIWoevEpnep
+9eXbr8L72wYxcP0O4WOXE66oD7BnmCmlWV4qt3npsbXWwBDrRx8gt+CEesrJsFJAnO09trN8Xto
y/Fr+9tYd5hvR1Mmyl0sqnQC8Xzr75Umyzdak1ZCn3E/JAwfIblx+fBvWlnqSExsb4ajtAcbkg/U
fcUGLOjQUKVSoma0j3bnxh3XtQAPwUpOVD9PONtoYjQNs/FLsA4VW17IV6eJKbXd0NVLmhIzMdSJ
Gq9mo+zQQMxJUvs7R+vZt5lIrXDfEt1jpLxF3cDsJ0AN4m/52eC+TyTBEJGO41Fwc8QGIg/E8GA0
dw0IN7oBt3hmXueguETaD1GQduPDD3lW/NGB4MX/2CJBS+IbW1d9y379GOe9WYPIkVsWz0pnhb20
3g9Y0VQ9WgGSr+wq5QMNglfF9nWSl6ykSQEzWEIzwQxM5n/7vXPt3/uMAuwo+GSBcltLXB48R+wv
OuzulhfPDdpiBlxZWTiP/UQIHAad4jePqXp/SCHkefDrQNwf+udYbQgkJHyZhwAQgo7Ba9zsOfHH
9oTQz2UEMhPHCxwIZkTZtK3PRGZoXcdFW2tgLoUAIcCZWON4bEaiRAn2cwROLk8+StB+OdFYVUG8
YeHx2pmocVHCHVFLjg918rLMXAin3LTBZIGYb1ZU/0uDf7jCZbFwm2vw9lxrmeLn4bNCxbGJRlqC
4TtjC2sGQebw1egFdH0e8ybdEluxf+14FaVfT7uwbBy7oeoRjDx+j2qNcl4KHDUYlKRDYvRmb/v0
BIul/jbakOAEv78CwHJzjuMz1NuJGm3o+PyDieefoSGBYOjzHGL0tNmhUvRncrudPTcjCAICUru7
BkJA5vxm0r5sEvED7QZylmNSxu0repw86/t/AzpBqxHDDnN/j5BcIx3NdGOnAgkdtvQDfk9GhzoU
Awi1v6IFmkChMENVTX6weotaNqdjVFnR8+SvNPJFzQY6kJDJzGv+a8sRbKuE2fuplGp1U3tVECJP
96D9lwx6N2llcuHIlvO9+lhlbrGtqi7MMCEACZj1QKzO04VpHF8xp9/O0uZ9cu/ly88Py9/aCFK4
EmzShlYyDNXaPV2j7sh86vLYwOjZdnHHBTFNQF32WdAfOeP25AhcgQlv7JTAcozc6qWFpZqcEKE0
5TIGL1H5/XkygI3CqhC4OnKrvDKtvxPNGBV6qUzZ3i0+YGXcQzVPWp8ROq2ZlNudqz1jL09IOSeI
6XyP1QdBKm2XsqGJBkYCadUWkHNiCI1S9+FyXJ8pny3TyaRkVTKIbnRLZQB1WcvFDAINWdRUHZW6
M11VlawWpYyrKovEizaOLD5b9X9e4jprNQLz8HKN3OOQJ/JSEtu+ki8Ockc4ETKizjHtb4GV3kdZ
RLa4q7D4b2JhBATOLjo9xISuA/dJUfcGGNU7RYcFkKr1SPqBBgN3PEdYWqHW/JpY3sq241wQ93gc
e2HYNCIQ/xwgiI1i8g9PEYdVOkdL0UNIGqz3RHxQ5n3WJTjAJb4jDFUHtFaaSyUTtfdQpJ4/u/mq
09fhCwjGI02xXXypJvGOEJBrgHiGXswHeO+g/84E35yPfVYVBC07RGyeWuoW2k0sAOQ1g4WjzwAI
9qLAO83iFn49LRTSBeDbW56lQ6HicC3hr4m/ir/k0sE4HSFTlzeNdo0jRS0f/Fs3uZ28+sr85I/E
RaHQiz5QwwtoaGfJHK+AgLD/us1VMov5mqv7aYBmMzJ+Vagsj1MOSLX3TT9LqRf8bEdRWLo4lWtM
Iw4FLvCgEatnD+bSBAYmYCvjxYjzXY73oUuitoOC+ZxXq9USuVwDudxNoBP9l22KVrnXzeri8Qnt
j32zRP+GVUfFZAaA3fon9Zt2koRJu5TgrxnJL0XDFoJrcCh9w6XVDC4s2ik5RcM7wnTpQPkKstnh
PNGYrt9btkcgC2k58XNgCRiPZD4SzMyMujpXPo6qwKUbNnpG+tuov2tQIU1jo86xT04FWSzgzz3t
itlFmKGXLYiTGN3ktHPJ3ovYHf0iFRp96/fRrB0wY5+FOvXe34jFl1twNxTYfvyQRjvJLW94lgcY
TF13m1cvRhwhN9qQRgzZEIUTm445jX1qFHI1GOHBU8Vf2uXM9nCFAZenv7RLwIv2voxFASXwDIU6
iVi/ZgLv2LKn3JOu7MR8kYaqvScdAD0FrMJmg4PkqYX93sbPjkLG5QlqHk5g5Z2yXSGPjEpPEqaO
YZIY5X5Whn1NeMhs2swETlyfYJqLGbdH1tcQIuPqMQcemuwh2u8AOgXXruKLvnVpRK0xowsNHgiK
zk21z+1esjZ/JsReiRBlaNtYqrdraNxrjKzrRWZ/z5EwRZ+nyMbuYbY1vixhjOJ/hfFI2HYHEYTE
FQO/3ufxdlQJxxNdQbb7UraQq3yBaG9CbNWC1uDoyo5R0AB2T8iniR7bGw1ZXjezuIeMbDns0u91
Pxao7adQVYRIcp+QVFqck/5aUEznrVbxL8+DEUF5MNFC/qLbEZgkzyBmOFw9AQdqZj0+ZCvzIC4R
zc2J0n+kBmoEOkjY7iUgGKl3Fx+GMAvidPYECwcG9fUNTCt16eMs9F7fY1cozaUaqOL7COPCZgIL
v3KS1JOGMshcAI36VZ34UnNN/adYKK7mzu0WvIoBt33b88/8kY1y9yy9op4iR7yyLhjUmFGujQiU
XulY1k5czZr+SowliRfLursvGc3mHOChGX7EGY6JAvA4DPZj7rUb7d5TT6+/eB0CWw9Rpvexzq7N
taKUJrmMKtupH4R5vPz/EpXReHs0muWBfKdEbkjV7MPyQmDrv8jDI0QrUZRahqH5cOQJ3HgidFYj
1/ByZdcApAVlbGfnYw8/gQ2q2LzRZ5DtAsXSd2LuKdwgNheBH6KnqtoN/XB7qJH/72aD+NN8RhS6
su+Jq5OVXhcw4t20vblaRGpR8gynqt/LNStLskBYhdzWaBgF1NjE22cKcUhH/T2OLVuOFOQMbFnk
rH3MHKKHKdKbk81Zoiv09Ai7HpPu8vZ6sdoAoS5GyU7tTsRlsCSRQEhpycM/dxqrxsnSb2XAqEBS
UdgS7fiL1g2mpoXyOHUrp6pwXsWBIctG2U4dRit4ZT8CS6OMWSYsdOwOWS5caQF66HSqh/ei2DGP
U64OhasVTMbsj4N81HiY4sx3p5SJtJimZzFXpGhU4ZQEGey7V/mxW/54/qc0WA84VrRMoalGiOLx
clobTw8SaeTHXA8nwjl3UbJu21p8Se7VibxpL09wpHC7Z27YRKWMU0hLqMoSNBMK75MbiR91fkzJ
3wEr+89YCNUzlYUZI5vcrfu4iCBUmsi/aHgZaWhs2NZNsM7n/fH5KIMphbcKgci0UUCmJLIVaSF8
DNYdpds/cIpiJJVfU20uHIVZ7pWziM2RnrlUFdxNjMevPpJx2BFRHm5IBFtB2YPdMGSyJ3CjihP0
avM4srADpxghFqHfOc8VYWL+CF0ZTAT2HR9/rkUcKvqsy7kPOQUvhUv3/6EptcBxDGO0kTiAD+k+
VaoCVkHlBglC6vTBtkhtxLhXBU+D0U4Is7Q4G+6aYB0xsKsdnabYQ7px/I2uwFlE8gqZbqC9c+cN
FQwGzcdXIYbDCXi1NdRH5FvIa6EZ7a0NF5xpIqhGbXkZxTaFqemphXVXekuwIvRtukheLTPJid0c
CjWV+ddi+iYowLkIeB0dLRKtYD5FM6oWGLoFJZ+OKHYGJkE0xjGGcn3mCLffoeFSvIwDpjCTbBKG
qtpXXky2CCfZLSRI3En4yDPtlh4ol1CUDAH9ug2axXSa5/oXT03JGqJgEBqSnwbVjrby9Q0R/srK
Rpn2GECTvhB1+WKSj6s29wZbSr4EXXd109tCXMhzkugDcsQr7oRIfaUY9R6MTnYrv+VpdaHoGlH1
PSBQvkVOOUmRd3VJXn8tfXZYLTHYrkGp1UDJNkZGoAShDbBAXmr6idvdEognBnlPKXymXq2n4/y+
vZAlhbfTaIwAI3X2uT2yFHXmqfdGdgIQRYEBVag71/9Pxd0gZlZhrZBYz7Wq1X2qmMH/UjZX9tJi
cu/0bmtKldSmN/u2Ygc8n2pLImay0etujSz9SxUXv2ITgOc9UlOnwEJFJZN5yNZvgu384MROCdDE
dWoB8P7iG2I72e1TgBba/41oPKZw0mZsc4DBi0gYDflOpS6SUYgYJuF0b4QxiE+O1zKumC+KrTtX
ZspRY89X+iq0l107bXzkHuDR/AGacO8I4x05yW0PzBdfGc2ZJWcXXzz3SmUBobqRyqGTnyM7k6d6
P7LsGyDXdkYrJvvoIGhz0LKwLGqdzFLz8CvPclSg5ijHyGCv4TmSym8NYEhpIHjx0qcuIAvJyBEa
DjlHZilhiq51HOcnNkSQvjNNz5EtbE9s7xwMiaY/Wi38yj2O4TcU75YC9Xw4kfFl5bN98AZyvi5Y
yn+1hnEc6/eKsdD9ftI/EU1CzcVQF1ZQiC+Tk9GQ1jIYi4U7H90kpi0ugojhefv/V7yaT99kohjF
ExrCJpT7UBcsdt9g2BfpBgefhT5EaYLe3/Rgo80JE48FgNCQ87SrrpBsOIfMvDVJQPm+Kg0eGNo/
QZqA4zDVF/hHwihzfrnj4KwHRFI8xp2kVuiqJduCftlCCBWedk7fz/qhWhTRUBmeOiRSLJstYRfk
qeE7/Fj5Ekd4Vl12kGcfj9NmngpG9UxXnu/d74l7VQr2XFCZj04iniSknymo4+JvuqyI0gz5UDAt
PsHYIP3p77HQJhWsj40dHq5Uk0MyXmcIEy9zDlDipCPnqGlAzB54xNpiRfL0qmYrUZeWLZnpdzoW
0DfMRunxRM+XpXjfqjHnlFJR7Fe8BnE3Uw+MgxGrBy/bpHaoKPWxeWf2fXphqUpxmOshUobvrXef
EtcDF+GXSwVvyHwQ89rcfv0hQvRG+qCKXfqKQ0PeSggITOVv8ZhyxSkSmW18hLpej1a74eNNHbXH
gQMsj68eVaQQlh/ISQra8UUwdSUUIzd23xEAplcBNY+0X9mT5/O3VmvWHYQhs3dL/Aftk/gSbkqR
g9GSKJ2uhytnh1FQqN2igAS5rMPnk3vREm6BcSVvTuvh8CLRYsLTDFokrLkKi2kdjs6hWH47Cf10
7CPQ6OZvTnCiikUF8acjeG0LMEU7929gcBCvPh82zeOCn1sEzR8tZh5vZSTh2FIiq9CjRpEUCRqR
nwMdWETmPN/rp+eGqinqFjPy5OC6lcSpQfy/cjkOchUyL48KhkyjXg9YPhv/SCG99awUfSEF4l+q
CFZxBPfDzFXRfrzYur99w9ruB4cSiuTBUOH/F5RnHvSXC5X56AgkV+4MICXSuNSvjc/WTk7BodhD
tquUkgh9y395G+WjBmd6IEwe6QEWMWhTDOVY6VNlNqJhiNpx5vctUASRjOHfi68U+EVTEbCzp+hD
o2FjrcscKX06LqWq3SRiUZDkt9yk3ukyREUb3WT4pUa9v7UkUKyT8ecPmryt9vBo0yGRgWwj5SXS
99SQq3qyYYkwypkUcdIkehdMwKRJ9yjchABVfFKZD3B3tthmAPwAXVq7XoNnGT40ra/YJfli6sav
sDFGXYq2KEI0R8optE21scJjiMG2FkDQcRE4kLJS4rd48gLp0k78CWUKD59yRmud1MPf8PGzyKLS
HEkMr9hwsX+zf5cEuErWX6Xwv3b4CA9gMgpKM8RO7TmRTNkPZmbPZ5NkxaMyvyuAbqPQStr3xN02
muZXOuE/TMCemTGOHs0AxowVuNDkr0AYNZ3NP76+GSKMJO1R4GwPGkIjgIdk/3OHRxS+sk9mDwHg
IAK+o+bT/TSK4eixsNBg2EwMHlgtePNX5pTL7e8O1qsJZ8R2vm2WY37i63pgjnszzXS+FJhfEXlN
Cm0BLR/2VgRA367ddAMa89N68uVUFAanqSzH3Q0AnqVqpty5dnlHQuEbQeuo4hlwACxAOOdq8jIO
5K3mExU5usth5XCgyC7/8u/YLTOvbp0rweGzxsfYPyZAlOXJTYrOwWmF0ClejKCz93wB6h3vORB+
dGmRd5Zcme1wVNlswOK7372cGOxcw7eqDm4PwElVlml4t2BaOqmpblq5221iEZRCtnoOK9J5WaeJ
ydc8ua/qjuCzXzZizPaW2i90OxYzwqNBCMkujOnUGSA7cj2IF4hKAHz30/5Y4nA2xDtnA4fm8sID
p0ZjqsBayohE++efaHAJrRCjgzyWL5V+XfX2ddT7d7uAz3tZsIUSN4/O1q1LfxrnKJwIRf+GnnFl
z0uWsORpN5QHeHzcIsx+N5kyxmDjYlGlO6mWT0iHrDaobNoxwViC490VzWec6VZGBoG711i6d9RW
Ctuqhd8s5jle+gz7ZBJAccW6jxMIe5cownige8+CVr+m771UWMOzvIRidwzOx1+l49VPlp2Zf3iR
0UB8Hi+ug78Gp00EZ3co8ibTWFWNPuoDCfyaRDC+FNLYPLRfaHos7/1Slk4xlf/Rx/YzSV5Y1qqD
5JiCls42cCk+ojNKQCAUUZlgq6mcZqytVAR3otx0dkO5H9k1BRy2t7DXbcOWQh+CGtg/Rhcg5ruN
AArUeBq/ZtBnchbST/ZUOLE6bxX8P/kTC80IZZE1s91cIx4szHS+nQsxlVRzwSDpdL/HDcj3JzMe
N+70DUWNc1yHIFao7IfYGxv0Fe1Xwnlqr9RUj8oc7LkyzzHvt8kSYE7ZMLokfH6ztyXfcvBrGgfE
kWb0mw76/Gwg7okWrm6t/GY4o76IunUpiXjk7bteNhkVcD1EoQJmOiWkWExl8F6sCbSDXqWGnX6A
2yzoZ4uG5gCGdRWZgmsREo66pCHswzb5o5kKRW5r+5ar1z5/XtCdpxzDmZd7ZiFA/3wKvMCnVe8f
TCIi0NSBaxJNs37QLHuMYpjfMOhcyXaN2bcWp6Q4isCZ++knw0tWLZiVRaY3MmxEzMXg+lGzkmhT
Tva+SxYi1N+xsO4HuNM6Bx5PnvMgoFG5VNYA1cZhLMFiqs2CbdI3yaCXpVYSDc0XeXMkm6hQziPn
dMyCAQWAfL+xzN1Pm9HCDqGmzxM4VAvr7ZZ4m5WlIuZAqGmnuLJNeK4WmzTUVJTG2Y6VQYvlGkE/
9pOZFrkSpkn5chvy0GSuINKoO27hjVUpCnhgjv9fjTYUpWvD5j1UPNuMcVGEn4jIhVC1/BE9qeiu
Jo6akPUraXZAf9uR1/gJhgr8AdaA6QtEk/rSQF5mcazzpyr+PxvqMD/gx8rNNWTweQG9cuC7or23
zHJall7AZoHdRuePiO3OYpi7cVe6IUvFySM7sCT1UU6B6G5q/5WxC1ZAqHDw9/KyCKQgt2h7gRYD
MCvhtoG0PmY0vrEWjCv6WwUkLAd5q42AzsjpApGI2l3ETfw8/LpQTUmexUOh4xzHHC6YBRpnPNFD
sFZr3UmeCkWZbbsDq5Qy9LrMCnixjpjqV6nuvPa1qRPpoA0xLpsZd5qQnjy3VrqH6m3OkC/ZwYQM
geicCbnQpyus8KMNVJAhz4cdZGtyp2VTxIqnEy9b44MVyjB8D+yZzJQogtYcPNIk89l9T+25wrI8
PayGMV3wHPlKjM5vEwJYCsJqhoIBBh/3ReTmtfEGG7UvuIuGXK3/YZcqbBDWE4JbMEtlqPAqtOZi
IMRwDQ9gsTxwNiiMbw432bjSrUsmZl+toPSaqnvou7J3lTrPNS4NhelsBCyt7AGWyDL6WaQCon/Y
l1GEHGm2/HWBp+KE2Gz5W8HjEJbXMDYAij1j8jGPe+OWcjSeWfc8m+0MMulule0KQR7Sd9RLx+az
upGeoEu4aEVFE8UkHw78eA2/2Dp629O0o4xSILgPu6cfoim8RI8U47EkhjzXFhuiAYrpGI8ubzmM
q1K8h9+lj86yyBLa9ps8ozXetqqL26b4xLQ6PDiPTSa4sMkoZIR4yhxu0BkCgGGA+dxofhe1KGKY
ErB43lWSHchkzE4icc3mwJipHMVw763UWu/0ZatbCkPY+zsPvMC7V4FlRQi9LH3KusDKCv7nfJ6q
C7fG+H1AhSG2RCJrmiPoJwipMUGAW8x7AxNzPZLTdWV8YkeA0KoqzpdJ6O7Q9sTVs+VNOO5Psbqu
LDBTYaH10KNfhjr6JD2zkk3V0TbSbay3SfMoaTz1GcObH9anrCrNoLv+jh4iHnmVhuzkfwwkLjFz
zBPPLAzK5OQOJ3e9eWRZ2AQosV1bnWoVyWOzaoEDmkq1LFIn5jxctDTKzNpfgHWT39h9wfmdcIoH
ylDI9L3nGnCTILn0G0HvQmVqW77JswRukGQ4ac7uKHk9hgAiejGew8ZOGsBnnEjxaJj7o1B5eJZh
gh1sBYFu1btmuOdqwIHKMI0lBa+vvfEsHpoknxnY22zbKdeXRIlN6Me7mZ4SGIn5up1td9O1VrUO
cE6RIDpU+RmkBu3ZqB1HJuIdOUydLYvi+AtY56Kdng9wb3TP5JXF5oADBMB7hwUYTrbrD64AXVCS
PaZg2M4DGDtvfxxRKnnEQUwiAIMxmtZDErMLRgyzHHwvvjcMoYcXCWvX4+Lf3TFa5wxKPsGRL3/y
k+1VoGcu3ELOkIjSZ7sBZIT5qLcha7MbV7maQIY0pfz0ZnCCuc9XYx/Cnok3J4AZjzQco0c+ljad
4rR65AAvddE3kagJ0i+BTC+XuRyN9Ffs8shE2nsAkEG3m05ASVr8PxO7W5qAgeWvhfRIeZzNWO9Z
SYjjiEnLKH7oSHvLe/FxQf6v9+SK3M0dz/a7DxCchLfRYM13Zj01u+u31m43xkFNRMr3M+X4qvBe
nYkec6nvOXXewnZLJQoiWNb/wXMNeJRkF2GOzjrl8LMhrUvRr3B0iXEM90grDpaDRLHMGHNT2TpF
DrazjGJrrhan3yJEZKhV5NLf8W9DExOBeEKoywNI8BBVdMieK2+Mn8gzWeJZ1NHA8LgypAK0yzvU
WDzv8s3DO9cbQEsBtQ+0OvPrnxT4oD7I3w1x7PuPTjbEds8Xu/9jGgbLpptkqXqyEyEgjub/TmOd
Qk/cwAJuG4M7Gtq3fv/asmEG96SFQQECrsMiYHz/RJxndvVHkDk9HZ2s/x02KveM3XoJl7kupFLI
/hlirXaa6muW0naAAX0hGiBtR5lRYVhVx/51Xd3H/QNaRYdbrExGomNcbkmKtDPgH85a0rPrziW9
M2bss2VRagqDrhoGTjgd9lGwVpQb9U0Hg8ODUI+GRz001ABKPmNdPg/yJT+kRDIw8ixhq+cTMHC3
xuMTE7Z3CVrikCkztgZlEcEUZ6D/bvQwfA/vJpg5p/CEs6kVkR3H6kp6A9TNIql4ZpQ+4FD3tByA
RafxTvZ5QPqUC7DQwaysHpA3n1rEiWQcRXusMGnqgWMHynSL1CeURPNoyfsxQL2dhK1S4W8HhJU6
TogJtVnuySNc8i2kK7+soyLd97KrG5XsIN9ES2h8DRbN1ARZdW1Z02EYfD9gZAnfphn28uD96d4/
aYYpB3fPu48kjwUHUyUMY/oe8hBrulDWO95Lz06Tv0bvHy8hsmXQsmLQAqog+F28r1xCOf+li34r
FpZc9NxDGnbGR5poCFdP29OOu8sD1RJKSu4xlO7YEzUYq1X6sGeoeMOzvueRVbS8CwoR0zelGU0l
xYdu5a8x4UCe2cZbNL4WTJJs85/+gy1jlYTwR7sK5XT4RuqKQX2z6CM/VLXw0Wx3rF3DqCFf602V
ZxdYrlG1GX525VNTvczeim5fIH0Lg+Z+OzNlB20DIXLKQBJisJToKB2E4wU1QfFsJv+/4JSEA9gA
OERL4s35qYZiaR3dK/Gire41VXve28QY91Eg3jHrdwpQcszGAmXxeg07W0bMq30eZHyqkfWEKd2x
uKIknnXtn3qV+X2W1SEx70HEIVMUTHaGCmTdAUOtLA0gJtvLiNlkT8zCGET0q2r8RweFJG3ngoJR
8tCjypqbPtHyx+mUMTIRkLm+i7JhaSR4pdNT7dx4NTIf6Z/KBGEgujELP4h7bpF/NHcNvmv9OVd1
+mgyO3ZuXlWuyPbmBupmCztZjt0zIb5VBVtfgYuwZk+UjD+irMFTM5VspebULyYPpVY1/DtVpPPn
GUi0qQbzXw6c1bO/BC74dHQ7deRwgE7IkBWjoz73jnQxx4u+Qp41vfV/G7/dqgigE58V0UGGshr9
E4XBvAUvXSfFNjXM2kl7MvgI18Ot9IlDGk2k16TMVl1CDw2oDapTEwS+yEcdJjHGhdsn6xAktEtn
OTOs7xv788el7lf1qqc0FKpI5NygbZu6LDB36udIqTNDK5VUKsE8fNe96cMJD40S3LKs+/abykV5
elWnFGXR5zXmmcv4qd5miyYbCoAsRIOc2OM6ktRtHQAsVulYM1sSYo5XJQKkr+UqGqgKxdqeVIAu
dwosXuifCmkT4KCHbuPnllBpxkDVyXOtruW4w+qRpeIMVriQ40XXj7VQ6MG3VTmgcJ956DbVUwQe
HDhmtzOTxGGZFhh5Z7wxD5He7XTZvjnHwUH1JVLsoK+gNkz3tzJKZDeO0nvW4et5d7caiAaYe36r
urqZhSSllRMfi/nHw/Mpja9COhdk6JXJdm2P44LLVAN1zzrATqn7TftUElOrsCwx4Ix3lxnXRysk
/Nkhx2eS2nzAb067qPqCHkuHHOQ+r5bm0Q3SuyXDRMUGo9RkvIiqiIfRKnKattjwGvMrRwLier4n
mpmYQx7cnFOkeRGOUa4rtUZbYSJo1lzjFKjBTtc7kRUxYrcoFTiJG7BlvnrDPejPsAdXa2dQ18in
NXJUAxgdoTvwgud+omxHl6InjqUmsVw3f5/yY1B2jrLIOJt2YXnNyfrqbYMl5cIofT+qjU4QJSz8
5g3SQsK6jATVILa5aM5+OC+mHF6Z/vmzR22Z1W2ImhBZvpnQyYUEZR6qm7/jjBD+zP9bd8iQYzIQ
EhqwGA1o59X2WzD8jdwAY9qWLhJ+WLxla7ETte/lZfQKzK/41VMsKee2WanMdPbBaYD4h2ndgdvP
/Swvmbdskh2tCmGCcFyduOpmoyz32m9hOqxn1xg1umHD0Oqxii5rmA+TzTy5J5lemMty0DPinEfi
GhDjlfJvs6BjRjb668gywBC43+/RstUmVEWMnxMmcwbyQXKwLGTfhtSLBEieLpE+xlaP7D9TJuQH
NJY/J2uU6DKTZ7jTA8KTbCPjB9R+XrOtPaIPgk5/nAYS2QM4xtxc/4Ia4VcM1LrR8Zy5zIlIT6al
25DhpINv2Fe1i5wvFUyuzSBStsrKIFGb5RzdQ4FomsJwvmBSMjLiw4437DFBaVLQSFN2PztFAm5B
b3e730TMS6XWWorIGIxs/haOWv1/PPMvOoi3/rJxWCeq0gx5pd5ppWHTtIgYTLsjZYO51nKc/77T
uyE1X41OGd+NiBhafCo687GVt8QfjrrdFuVnlC/RaDkNhtIw1O7onQtbirMXDx4JxjaeG8rQarav
ZIGYG90lScNzRTUVFC1lbdGVUlBfRTMbKsvq6SFuRhd4Sxyjwu88ix6sxP3/qXSJgpSFtgP0J+vz
yaeHl8WzL3oB+kHrSnpEh4yLsHG1YGvne+i3tSeqz05QYOocjq331bN35sIn8s0igddTKxT0CY/y
3J0ePKWGTPF71NY9hUTTIxdF3AHA0uuQJ+AF6Iq1hZHailooAnE9vuRPSzvmSE06wgZZgEskirnT
WT6GZLeSfFLSNAcZWP4S52ulaR9RNRCv5F208XfzkVCa6tiOn8OwoRXC9nmexgOQPAlKm1RUOOUU
ifWnDezUlCXSut4k2gBk+rPHI4KHGY6SvNYJipwjGff4iScnAKyksY/aHboU6efYerQ0P4facfoZ
JZGJyJbNVrV+LnORrWqdJ1H+KaMHBcWG8d6sgPbsFCdpC3Gy1x+vgBB2UfNIiDghAR0pE6Vc5uzY
O0HPcWNOb+kU+FMMZXS/dT5IhJYjs9ixNU1G0n9O3FeBOVt3Q8SOqKC8uJ+rxjsdTykM8u0S6pnp
oQjj1WEnVOy0hZveo36H3KrzEuEAEChunjVJotb8hGGHwuoTm/8f/nM5I3ydoYC+LQKFV4Vj9NGf
jJttIf9B9h10VoauLLa6RPIvxVvE01tJBQz3A+m0V/itoZJcXBdxrVLVvnHjqFwHsTUau22bpWES
vT8gKqb0j2aLBL+V4RNWrDE77GrB5pTEIBk5ekdlVLMRjaBRP6dBeoHs8znvoWo9r8zrQM92K51I
CvJ/4uw+xKXLf5EWL/k4cnHsQbZO9O8q50Wund0DT+vbUmp4037PM3xkYefQvojQI4cjkiTnb1Ae
3IX9V6QSJb48hsoR4fgGGJsQE+3qPHthncLjIU6sraEzJQp0UQ7O57kgjm0VWV5sLIt8d2YjbEqw
5qoEqGQqLDCbtGdPRzSMQOb4iyHmYtEC/pBPzScIc1nabr/akimvDGYBjVc+D8HsjGVGb3iIQQ3S
Ji6iJFreV9RGLG2hYF93hnzSQhe0sen/9dBeyjjEEp3F7SDxA/lkZUtsn4Qt2r3TZMHRARNOlKrM
SaO0ZNr2j1lWMOyhkPDlZXVbc8ZXfhTsUMil9wZGnDxr0Zo/XcTFN3/+dHKS+tQghQCmrcU/vxU7
uqcTH6AjsUmF8lBHmwh3nlYYctqOUivdUezHOF7mKBWAg8hvCvMPNBLykrCp0xILGvl4GuKys65t
wiy2oyvHpgz0oUR/IgrLiWuPi+diE9eMDtGYyJtf4Fq2XojEL7fKCmEBp0Mj7L4vZB8sF1nkurN8
7fnuksms83J+yKxlQesYGoCfXGbF0/Y0UqnUcyMRUm248s1byNnZSRKuOTSlCgHtw7nVwZdalG3f
nGHz6ProTGKthJrHEu5TboxDmRAQX3i30WjqAupqzRPPg3Xg8OEHD6u/Nd2dXxixbzCkirDxfqIg
4/ZhktZ+ePmtx6Fih0+phi8vZDzQpnIsHVA4gLfXlnFd5yso8NCklh0dwfzPds6tj1kt3dMdH4Pc
3ZJguVpPI7CljomTwaqMSK3U7uOr/DcogB30y2sDNfBWyQNI6cAqf2tnUWfufneFmA+TqBaqfF+U
P+5zxt3t3Yis9YOdcIbQHSf85QM64ksa++8S1/tXd3ZVQm3qDEpxWUie1Y+8Eog0Apo/uyKX5AOo
QQlk6dWIOOnBMpWsHs2MMbOnfQNNfTBl9Cj58Cyv9XsZvThKySQ5iKwlG19MPNVAXfTT2egqLJFP
9mOhXWJXNiEjiUZRXNIBW0CfXfZQxi1otUZ7sy5AvPeoUBhK2fX2p6Seoub80OmQ5B2xzBEQEpRq
TmcjaFyaGdQxklXjSpau/w1WHGFWe/LoZ1kabiFnKZWt6qKrs3CsyHIeSTmp1bcyLmBjGbibUmIt
rPlOd5IItSoOWKLRODeFpkzX0BhPmsaHxZDecwcoDEcr/cgYu+OQatwUKHNXmLcU7RZh3w2fY2AI
xep6lmCEZQFE4DZH4ile6njOKyWSPfxOPSYdOreDpOpf7QMKAVCjbonzegXLL6b13KpEMZ8cVCfg
NXPGC/iqzFhF1S+bxY0LYMQHb+AfkzSL95fy8mheRWzZ+Rz5san4urLEpORtWhY+a1rORRCgtNF4
dv3FR4/FuHw3RGm4Bk/iLKHJsVHW+C44wT2cSfsHPn9oZpOdyeCS1BAzuCwptwtSYytVuD1QFbAQ
trEe9WnKZE60sPCfvg0EvIRMft+0AX3vW5FRSmctd8EO9gfT6YYK/4dbA74Mwu66NH2AtmKC5y4R
+BqJKsImMM32QVXFBfVwn5npDARf4gh5Dz1b/uQ9VuAX8ziuWQ9Jjzf2zo9OisnvlUjSj4YImZKU
9rwYfpxvEGTWYyPw/4uLvwcdQx5JUzfcHwAYKT9wrkNveZvpxpU+d08AEWrbwx8AodvysqkRLLsn
1n/+12Rmj2fHeay9Vld6GnBHiisLgc/5yMu0IvLwCa/kWdq+yErKuwP8TTORj17sy6wpmutGHf77
0i01uEv2w3K9PoRXnlHMAEr33xdfPyXEhWrp7YFTEGtqXIxpmylf86wXIzXUXSkZlRu2IucJ5DJt
dV+RJIgrUb2HYOpVGzfDRB24queSv/pysYradPUeRCDeq2DeggRuQNE/EO/PSFupotfEDxbTK4bz
Ov+pjsF6tV0yw86gI0GVLNuCE22Ya34p8HhWxPoesRfa9wowRS45upQ3FYhBIppL83JTaCUc1ctW
mMcOCAKxQ6vuyjfhqAp+7rfVLP0P/nhA3t2Luyf2t/KIpZ5K0s1S14T807ZF5NkaQgGDvyNepjQy
SPUA6MQfvMBuiLEQIRuTi7Clf4sJ1qqytKn78lBdW9ywUJyGd6JEbfBgz2vMQhnpbYXmEvVxiOeZ
g/79kIh/VQAxDb57v7qrjrNkvUKSTESQxRGsFF8KAIQreaBQ5kFqxJcp6nQ4VPedFzy3/T6RyHhY
Vf04gRwuj78ABmmbvQH1xV8vUUgp0wiQ2yyAgtfucPcIO2ptuH1xoYR14mm3VXmZg5Sweb3lEl5c
KHgROYOUBV8LycP5HX9VYtEjBQjmIesXuLfph1LStLKnKPDK+aJVr7Tz7ZVq9FnF2xv5aWI0UpqI
Hs+T+4i9Uhm4Rvt3decJH5to/gg8XWa8vtu7THE5c+SEItRvQ9jvaGu+rkcFzRCeC0MFhzXnoKz4
Yi+LShiTbWtXmdIDXCu2g04Elx7qZeyx37OJG5pTUHAM4jBoqydUKcDlk4brTbBUJSUAC1hjssiW
YRx5uvLmD/1smnJsW9SMlJy762MSSZ7NMi+Xkb/73ga3hGAug/8G8gK46z9zAuRfVnKBJGrihqjJ
HgNwKchQUgbFGy12j0qbiDSGgQWk27Nj2BtelpHQ2sxOd/XREO32cDY5RoR+KwLyQcxwa9svZcTl
ReKK/Ul9+wcVAb8J3u+UjqFLBgObW66XeC1KTMTZPT6D/My5rSK4h08n/NpheETLXFYkJj1vrxj2
ac8/2+9OpEeD/ANbf0qx+qEcquRObB8OE7rMO6/Rup/4fvKYToY3ZD8d5R2EwQEquwkVRcNtAN4K
ztHPrI3ipdJytalGTtesmsad7mQ71B9gW+nF81cKop3xLdf1ik9N6TxZPgyMyKOdP/UafzlBWj/h
auQxxAQ3sEqsmw3g4v3KHUeIYn43FV602TIgcL74wJv6wyowax+QaXUrPOgdKb9aG017WKDqG7GL
FaIyx/2G0UacMTOQgi8gwI1GKvJw4eioLnTcdPKCLn8WdMYHQt9ViX7GRAf0dZ20lLleOqnt+Vzx
5VE+biT7aLJg4UAY8rtJ5eogiAN2OeRtfyfWbx1Kw3nWi8NShpCSduCGpbwNKj6Ibllv+feiJK/8
OwgJ48ixCmNiCnDaDgZjTlXfXR/Lvo3XmkDDcz52akPelLgdxvWKugb3hb4IG72zMaTHncFl9iuW
zvEKj10pit6JjrRrJ653qZhicKHWeJPN+4U9MyfPQVHwQugsnzg7KgrwXX7BOIgfmD5Gf3hwajzu
jGK1XM7fhmKjpSjzOOO8GecVqq3Pp9d8fzD1sb8iDnM81RHt4af56KWpRv181XgCmH/yHVCXBHHp
9/OvV+2knHPawqBkQtNQJ0WkAYWzdqVOcnLI3JKYVI4PVGbVYiiFx0tXQzUcc2NY8WJJJDVeWxue
ZSqTzt74cftluZRM3IHlu4kM3OgG9nXGjD0dEAUWP/MxS1wqMsYFr7fHEmKYn29/zNXmJ7yyWvnx
BZTzDKO8wpVJ9y0J61/6vyr9luyV9SbIfXysBgPApfWt5EFbKIbFO+3c7/AlaDEXT7EVo/91RB9I
lMnKDHsznpmNYzlUUoVME1omnrL8hq3Lb1z16twCRFt4MsPyz4We59Y73/KiAgULLjrpX2VhFjAB
CSRg1Um9B2heea2Sb+3evg4xoEpmshNOEBeyJ5I5S6bpLrqWxHlgjPjBiWzuiAIf6FmnyYmeiab+
l+10JW7SrNYKNzkXGp0o86Bkzq2LO/v6ooKff4ORMlBNH9CtkuZ8Lbdr8OfKkuNyOZmjHxy8Q92z
+EwD34Ufsf8EjSduoomllRTQ1h82VRKcCRLVYQEqSqsq3C8jqqwOz6cFztIH5HiLHOWXS1DHgJbz
ArRgTwcBrsd+GWsdGo6GMC+rv6KKvb/2VoRdTpMTrKfoUjtPpmNB3dDFG6VNvsMPBGaO9dDwOKQT
1kJywJARBb+QsxRetA4lvQl9EJwVPxPoxCECC9+jxJwXca8jnK9G52t081V3fhv/rBAp8gpONAXm
Vn+bEBohEVyA9E2USJRF5PeyAgS93KdrGzeFFJJbKTlcyP/U6DeNZOpFEiwXcA4/CgH4zMW2OUvW
eSH93Dm34Uossqx0GjvbH21CqqDo4Qu0g4LPna7QQRX1LrjoKwu1JhM3BmS3+YZGfXpm0vO1r1if
Ia2xhWn4UVwIPFEzl65nnxSSKVcnV9JZMPZrHocTDIdRRvSBdywg+g7y2Vvl5j1CiaqCOFAXhOyD
yAEsZm/WNe774wCxDELzMYOQBSn/zKms8FDEEpnCt5K8fuEz3JLxCrG5T2sOY+YbHgvDl+AtJtwT
T7unep8WOTcv4apTg6KTVhrlpk43lL88Mq+LASaLl0wFK8jt7p7Pf09PNxu/6EYZKlc8/HiLNPR3
Gyo86/MRQ7UTFITrcY1o+DNsUm0vdcqz2OZetB3IDpV+5fZc0ujDsORoixs0SxDpqWBKG12IMG9U
GkS1lr01f2T0iPGHA6gUtV82CQcaUvxe7zNhtycSEmwvb9x8AsiZMHOEfKuLnv7SYtTD4EEz00WN
RHjSPV1XiO8qzBcDOKXLn3quN2srXjnvmSn6vy4Rd5ceodt/T+2Eii5b52Ac9F2NiNsDgOad5l2z
M7QQ2nSdtPGOafm0xGrSB4sD8E6XOBcoh0rDC/CJZxpvs+hmKOxnLRiab5YrsM18HHE47R5SXBrJ
AmFKsuChtQ4dN2BzJTaws4SUb7aUEwQx7gRNaQyRMNEncDeXkJjcUCwW1R5A5MNO1h6DlXEgSzR/
OIhjt0cGtFEznrrBh02/iDluAY5cT0KmAQW7B5X5ClktlxeRs8pV7fZ3L8edfehyp3cYxmIdfZiA
mGnM6zvulVerC3vIvw40RRftZfb07eropv0WQgrTvtmxj76I4BB78G/8IvRmGWB/ksK8MiMxJsJ/
Af1GRZk8lHuf9scjPEUWOeUtxa27enzwdi63zNuWsGd9aKnaSroeoOd1ELp+3lEHYbimkjR1UlQX
wBp5pMFCgBu0yeMzHJsBgBHEcrWnEmJ+mRHeJfWQgY4P5yMjw5sESDlDz8AsX4X4MiHOajR3Dvkw
tMwxpIW6EInFiRG79FKgWSTOqKpFqa2OLA0vBpiBB7oTyCssAs6CtMrwVuOPNbya30wUDZQ8D/UY
yke8FtB4DSwVkOm0RG4kD100kHK48hCF8/e8fmRkC8Y1WxpsEsYdkIGebBjjUaThcRkCueFeplKF
8NCdqLawpY/CuxCN3Nat2ZbYlWYy0/U09P0fiCAL+OdFdfW8C5b1Jrf+8c3A0FS6o8IQoOaGZ2P6
1C6XGd7gzKiqX3Udl9JOYnfV7+LkWzJb157QwOSutn95RAsgj+fgvfnMJ33KmhcDkE4hZkeTAzKo
41xOp7mJzjxfmg+nPMWDF5Z7wXmhwp4fDNm+Ju1CNQSJ4JYcoIEn3DMxEni86np51XdFx613i2qb
b6PNcVp+9JUmzxg+EYkmLI7/Kwi/itKHRJthV95OKK7H9DyZAX3zmjRus80ujzEfKOPucjYwmfwn
rM8Q1oQhZ8HZWPHG2Wzim8FzhNseEmNpgzJJHXnsPOTXATZafTZYrZy52Z3bHurlZrml2lOFX5OG
0NMidwhJf3ip5/u3/XZe7fqwE+D86krcgyNgWrnN23t+MmFa2gY0A0s6SMRRSpObBqByMFTGCi51
7OWPZkCmspXt8udNq+lK1OEmzjAgFg0ghGVSvTSKpecspIwxq4Bu3nh9vuxtY7t1Q3h5g3Qp402F
HYH206imsKzwYd+k+9K4EmubbMlW8GtcIQGC7WL5VK0xmxB8jHgQpbSuIW2COirtKvC2rFB8KDKi
rRi6Q/ZW8fdjVoEN/ap3zc9kDglTIQZ0wW0JbzPE7Zd1EwkjeDvo0qqxup9gu/JtWVDaWIRPQWdB
o4E1+79gar80xndvtqI2XeEFoODs96ovN+d/rQHzfVdlRKGgHWCQE4oBuBN+yMPfHDHeUsFBziVw
BwFE/llFX2w46yIuTh+OsbbVMaWyhysgbXmMziIys2My0uYD33kb3mn7TC/BYMBOaSna716fIdSR
qNsKsnxT/mMXXWBhgz8KS9a+JcCp181reEIdn9PldTE6S/m6KeRAqlRqjma+I5r+EEJVMe93OTgF
1ehbB88RTeZpVjEKTvRx20XSdK5kb45/kFgTrA3pOjFlLoMoVhANNm1yqfnfUFzGRwnQIWMvJAHp
nrqsBbq2WKrkeFdK+hWeQEbBKKzHz8TDaOfPxvnmg9e/Qn4Vy45e6TYZKo9adLK74h9/N+ImqeHa
13sNhHevK+hB5tKCcTYzXj/HpVrmJG2Cmxn6L8BkI9Q1CWKRW+ohvszqWnrtBsh1NafzKgXx8MfF
dRCE2yi3xoG7C6NeNri6/gTbSm7n+OYXBuSIU3jhpBMv6BOkd+kyjJ9VCaUrZ+GexuGqCYnn4g2r
GmrIfQs2veOX+gQ+vYkM84t05cxhkRatJyja0x0Aw6pmImUeEQDNMPdTlok1YxPSECk13MY1ODIS
y3qUbxiWdiTqXKTX8xtP//j5VWAu/sgoZ2b10bXU1k2WTwymSHZAkhRhsBJl6x+vKIMMH0MpRuZZ
kZtiBIz3ytSIQr8HiQBUsWWdFmLqUeKKjpjrDy/uz9co39eFV4fSZzNwx6k1yqmZYiGfFTgUzZiT
csHFxQvNUoN9tMjZMJauY4s2x1mWly9rYK7rTpgZHxk5Pc9o3KUzkC+ULljbyBH2pTDog285M5Sl
/e/62gEcVw7LfFsR2S8u4Wkga6PU9/ON/ZCGgcB1ZFRQw9j1hmSjnXOxr24Onv47E+Q3vqjpZT9U
j0VWFrcJ6q+0IF5f3757y4agn6SRoGgpL9ha7+1ImB5DFuxs4fx/yBxR59/U39z14Ynv3wJ2r8Ch
LpmrbJQR/bVQRrKpDETzVBOVXlcR+UIhRUx7nlkh4SfHRLChIGPVNXpdg6+3xdGFcnMgk5Ry/0iS
jr/AZhjNoyXNjgvH3hlDq9igE/ejJl4EYdOYr2JKFIKNcgBm5fbVT7Wd5Me1CX41hEXQQ+wBB+i0
KqIr2EnHwIisozhunWLLXQrQVBH0xR/Dlm4JzsP2YqEBfnLht+Tucxei7UhIO/A7aoOhRaiIFi5H
WEcFeBDmFH0MWE/y2rY4t62YPFtdnvHMqFJbxlz12D5gBKLgypg1Ef4YNHfnfVr3D2dh+GYCuHMn
BIVz96rGeU6Sc6hyzrcI8DcKe8O4SFDj4+v/0B96lKwbzI1Ae3R+3K/kVTK8MvyICaHNHjIPTzhj
2ZNUH67wXFpBKZ9ICoeIbvXP3LaW+1nxeLJB66YaGlrXnQFvatXHI6tuj6wM2fRqC/Hq+VR2qFso
IdtREvQCikTFUVL9vx2LwfimvI3JwPX/s6pqxFwP8vzNXGAi4FAWpgzMMx8c9YnnRojV6C8tangJ
eMATgomMYwfSX1totihXYaCoVxGbhZPgf/nIskWWypQGBVzSC1Km8zpqcVaIShM85kJB07Zjegdc
Poq0HBwW9uDQY5rgUrlNmzpRccTKhfTtnuzZsIWXbjJi07mDX3Eoa5e0/7ZyVz2iurcxgbMK4Dx/
QtzOq6XKb3YYe1HF3BFjRSynWpo1h68y/0hlSktS1qTYVW9LKYNukj4K/gGQ6G8DujdbtUsF4vWL
bJgsGrKw3SSYft3ym/PTzpDw26hWUtxVs2ZrYWUcwRk3ZbvnqHD3CfyJnIwy73cAAufXGh+nUp34
vjHmq+Q1njPUpBEJD9soiZU+N1lTlKVJQXB+VzHKhb0ROZg0BvOzLNtMHVwrbYLU0qD/z67IckJE
5SZEggzGgspQH3zc2tmnDgNp34p1RmXn7QeRDzyxJL67/G16DqFCJliSIDUp0+cvggPsya7oxRMB
G+Y0BuXbWXjylwHsD/W3bAxNc4J9HuPnKGcqyrr14rIWlIni8O9spPUMsrB63mAFYlcIIHE5lxh7
3ihQCcsujfy+CIqp6p9P3xoXS+WIk8OEtg2yqRRjwgTRMuSRZLp9zt4819I+RlZSp95xCnKjEMzj
/y/O3ucR7lqjfPbDg3NZDfBL0d5QvUsMBynWBvfuGnllgZqrBexLIKR28XEm6BpUz24xnaOhA17Z
ak5MRt9ZEzM8QpoX55DfAtXzO31irLkm8hl6RaGl8QHzcBusfMZxMZh1Bm3SEXviMAjVxImAtikN
0azu74Zr/5pACJd6Ni9toYI0rHwsiyF5TOh11OAqp+QiFic+3ohj2x5WsAgaUEEtbHa2DVYWpcMx
PFm7zy1ZT0Y1alodbuow6O83K+w2goJjNTYwyQcAgb8Nlbv4Gd6Uact0fADiyKGRUoECNN/0JDQN
QIXWi+dH/S/FQnuPUeBGez4rq6IEmsbzp+neaeJNpOP4Vo3l43OWwrW3Uq8UuHNkTzAxDejylAuO
G1BbRWusbEe5PK6/N/l9gcKmNpL5oS0TN0jNV5N6ls2NtgTzE5by3JsPyvs8yGmmUDpJAAFWJUrZ
krk4WZAO1w9t3aOlotFlZnJTQ62acCkA2H/zLFLS2ahknf8buhTca14ri9WkHEyZZl+3tDZ67UAP
ZBX8LzYDVEnMp2PNH3X0zxUn6xR2g8FRxc4Z7DpyJCxXDhY6O0NI28jPZxst7puYq+SSu1l5Zcsl
C46QJt5qNx8xJpa1a77rfqb8WGvqLfgvTWi6u7ApeQhoRBFnTHNXIvp6YCyIOUe9ASSoSwoOqXL0
V8VaQcj24GSGCrXwuuUw/q8PAkJmPRSVutoOrPnCCUoCqXCw7JNqg+rV9+Ze9XDU6pCPBrSKM9eT
INu8W0Ncti+VCabBb/j8+3FS0q/zPZaJc3ipkbDVr3kMkqVhw8DhtVOglv4Ssw3dmGvndB0whtYd
K2ICQm6Okw77p8NDBj5s3x6SfJd5JLGP1V3l1NDKKBsiCIbCWHYL2XpDE6CzVgs96ov6+YuigHiu
rV9JoAWSpTwvzxbZ168SRQC/xgypyvzA/RmfWhmM0hoit3bryPc+1AKAZfW2d8SjXPU3J66NMKQJ
vcG1cbdtOLN4KtpZpdnFbywcAlHNvlxuR56EGrKtce0S3qxb4XUfdh+2EtO9djcacKaEH08HezsZ
UCiH3DKnfYa7Q8F9B8gyQd6m522/MuTZlT3IN0RDv/bCsu92Jj0Kwpv5S6l7ak6+mbwCiFf70hHj
FaJrsRChVXribPbUsYkg/RJIhCspaUXfX7YgD8eubC/c4h6YKv3xjoM0i08wVrMIRdRf2fFDwEOV
dh4Cr1XM5va1W3NgFGG9e7ujZmyAD/AXP6hZdzjco4iFzmgpZqX/AkOBXmuU8Z0WjJY5tel9nzKZ
z82UKtOcL+i82pRdflm5kJNtswtFMBfAT0+0DSl3AFQ4KIwZtR7CcDoa53qXCPz3RPQtgiadX8AP
2+Yl6TSEd4jb3cda0rsfKLLikL1ZSsDMd1hvbUO3zoyJb3FskBLVJwi1vlvOpOT0y0x8ceKKHRSJ
yKVQjg8oToPcQIGcKKo+0LdhZmjDLcowrQ/Bmut4oMCP8mTq9Ks2hsDgq29Cb/pWghe2MhF4dxjc
/Wt4IcQWWmQPfccjQ6fa1fS/j02WsHpsXFdhbM/oSqXMsrJwINd1p8YBLYTEv7DVDWI7aWmkA/T0
9y0SopaUdnkgLd4jhTMu8niETGBgV4bHBZhS4S5SJYjQecPaSoYR8tu3/mxRG1RNW+YbmGIT3qJ7
9tuWdet+apmTjoZbkprYn+8YMAD/0pxxdWWPmZe+Y59VGusgQ4BExgyz8TDIeeo5oIe1EAIv4zkS
C25ey33KFT2aXEYFqXpbHglKGjLWLtL0NSmXeIrrk+QwPtl5K62KCuWxFAt5UtmFEjzsc2314l+k
a2Vw5/YW5OB7/jfGK9yUjy/nVoIwySMqopFngREFksHy5zBQxPNmWL1ZIUYnQtSbP4npPYJHx9vG
KbOGHc2X6HMqn+ZQbY37ikaIOytvJ3r5mv8P3xezpqVD5vAfReNprcMfBiensDZQe34sKbdR20S0
+/f/A+tGkczsMR8rJ4a51TggLQd3MmX6KYKwilg6mM2GBja/f+ipuvvL5QIUKOzKhQ6G6IX/3rDK
8Wn5EF6R4Fv0/0OEiJiDymerElQozKaMQ4VZmFXuMb6amxfVD7Bkhas2kCl0hBaGHmf/6QOm3vdc
v64lmdNZ5wwSf3gnUZeDlRvIACR4b67zu8LDhe8UVHhxpO5Purnh0ua+VJ0JQCnkTgl2er08vC0o
KTF9YRAoOEyqwv83lRhZZ4OMh1N+ukDUCyo4Awq2eVx+q7DoNf8cgbVTbrtWub82nHPIxeq19W3v
ctHFyM6fpiklO28MrwfawNDMhZOi0CqG0egadvy5vnkl76U+07ptpEld9jTZmmP1M3sJ7VJoGEzZ
MITCUCvupfGxJBpaXk4xLEke4G84U23DblsY4ufwm8nxsJ03R/BYQGBCcIAzmeFPEzLiVV0mggYU
uSaRa5vghi0Z4/wgVX7FDxnAsfujNDFQL1RcARkeeIy68jpEvTC9v90c+C9NpXU5Vi38kVZJBPJR
Rg6KbWl29aWWlj8AHH73Xz1u/DyJsbVdocULDvik3KHRHgqhq/B4SQXrb6R5W5+lryfXRMNYs0lI
62WU+9VQFLomb9diTDHL0bYPkgx9/ZaRPCTbwNqAKBpOBqpw0wGWeQGxaLuhkdBnJNlfW6El+1UQ
978aXPpJjl9dTZwjvxYPozvbdcW48FtOXu/MF/gcHLZRYDvPecv59ajxPknKTBuoIEwQMlJ/ylS/
igvs6boUlvsoXNC/Rz36jsTKWgLTHegkU93xsgSwwt4bz610NmvFGKh0qsI8zulz4ABA8Yp3wBdI
LyOp6zqWgmR2zA6wp47GGwEo5iU/eilJew9ecKO7kL8Xa6+mTyirwNOm6M9hP4Ra9xJ/donZRPgF
qBRDhXAdIai5qVLRsnod1oRQ0uD6iHE3NcNH0jmjU/FI/yLsbqQxoVxTzabkpnc4SaktFJvrZS6z
Y6MOWWmAe90Ye2IX9Jy3afNKaooag2sLw7RcrhMdapCMQ/gEK8eXKrY8hkdgtUgnaX/Z6FdDXvIH
WcY09jZMyCFIaBTjg7POKVPoozTJ3klnizEzVQH7cDUM6uPE5Auiv/YPC60ISNp6ivPTZbwRQHqE
w/0iJVfojZVDC1P9dcpx6dkCevtwD9jZ6+NyRbrXNDyYboRfVW/ZzzgUpH9OV6ffnr4J+b1C/gQh
eUG50JOI3Mq2GlYQN97iw7fkPVHQ2DBUICBHOXY2QIn5+peOq19CA9cChvQCNh00YX7SOJxBspRX
ogeBt4wPXksamDeNfe1hfbyPVP9PXn1vjRSWVXdaj7MF+p15qPr+WworK36hwgLiGRzM+dAAivoW
mq/Y3aO5ctDrJwiOV0TvEqQQUsKIzDlRua5BZ8lXmdZ0gnwrg6JT0zu/r4wYfCny62bhouCgCcax
LzW8ZumyMtLDt+F2YzH4Jgm0mEebEk5PprlPsPQi2xizKzNfbImcEyGVHPzCu3fOyLfQzObbRvJX
wExJ9JEub4T4GgRS48SMb/wAJEmOorCUJVv51hWIdewq9SO3vNvBIuw2tRgjN1D0M7GQnSRKYQEa
oF+ZFRtkBUlN/b2JvAUrx9JzBTILKjkm5QbpaHtofE3Qgt1tIYbOqozZpgDrEoYzbEYrmOxUWHJL
BCynB8Vqc0OZSHEQCdZJHAwdk2EQEy1qdnJZ0OTXjndo3dB7+LBg3nfMAnkbP7DrG4VUNY2C2JdX
oFnWK7xTkirnnXe02+jkIT7CXpuhDAoy9ek0KuePkXBAMdF9Xnp/YfF64qWO3RuIPmY1VcEOQueV
LAXmfUDBWcSek4EHFHtErp5sA10hSKx9hEKvyoRO7mVs8b2yHxDyyYLDq8AO8ScYvSJ9Je35Ge5a
zY9FREYYqhe2mF3qdQ07WmerbfymaxCfa2Cbjq5svkYgyEHPuvc6rLPAa7xNs2JgzfneTEz2NU08
rM6eUjz8qHBxpm1WOPMTlAiEbodFzttQGCy0q43S19iB9MGeHknm+EXTvhcC0SyYtWGkiR58O6nQ
4zrLuGwY1E6EF/4p4DxG6YxrgjW7LQKfgMk6wZx9kuldvEuSj/ghVhlbkj6Bqabr9zoFI5VYKwdO
Sbxs1SvG6ygWM9kt7mW+D8JZvd3zGn7fMo7WJIEw2uKzTZEvb8EBz5R9M1aUhKTlYMqQS1rPptPr
vT2n4ap3x5W3P4wySQtsa4xEJMdcD479HAYZytI3B5jkcWSEWFUSDz7ARggbJq/6DvZu+AFFuMOF
1HpC6GvK6m3GLftAMWrJHOMzUDXF6sozYw+k6tRC1J0V3JhJub9xtsiAMqU7D8bHSBdz2nJgK4QQ
nw2DMJ3XFYW3BXfmZB/vvVSaACmfmxDz0xvZkYmUsLch0bCeIfn42HfEH+lb1K+q+k2jmawDBAWL
MuR3sA8awwzfLXEhr/s6meRt8BUprMym8k3aSvHCH0Apwu05M6maYPYe7ZDAydKg+OwD7tsiDaQF
a7/2t6D7zR/QCKLDVfeMxpofNAEgLp2Xxjbgym5YYtOJEnCSGvcsF2tB62IYF5sqNN5ObCbCT4g8
M75pdntz3/IFphmkc+CGkLIsZvWoVy59dx+HUruOTsc/mzZrnx0vqHvyWzPQgMdAWtTc1lOPWy9Y
fCtcp9m26hJF6Xx6do1z/XyS3CzzX5DQQYg+UgYaFRfZv0lkzQzq73H54vnrd5LIGiRavijx8fnP
PrtBmqDOMbuw7fmjZ5h8IuE9NNyhUNvzhcMUgoJt+3Yx5ElVALjW7b3VIUx9nvaqNxBUIiukrPPD
24mH0yCH2gPcPSXtHYmJ+B1JfdMtijLXbTaLeB3jEZnckr8uGD8yKOC8KfkcLySCmQRfwOawP8v4
xowqL/EQK7qlCoAX6mIEGZ8LTXW+5FNymVYClzb9SfUkLSMsgk9w4dMBnfbb9cMeo3Doh5LC3W0G
/qUz/rpgKBUcsTZll39sHHogiu4ylRbDYyeVCOwTl0XGiHaxQ39Wd/aOwIkubtZYfPABLdJqCyFH
tMHQFVAX3KaXNuMSxbdptoV5roy6ry3Q/iLXMwqvDoqgvSx3m2vppWDRmqF1OhibBM8UuYhRIXgj
BxanZvx3cM87ndaBDM+C4DMQZ1X5zRVUg/53Sk1BqvyouKrvGwzgAmJLWm3qQFoqEERKFlKTjeJf
ZcefHVb/8b3QfgypGCqfOeGi+pcFbFbKlF88qQmwSeaz1APsppow7lzOVEb3+kuGlgzjmvKmMWdq
oIt/1Nui98xh83mR6asTVkUdBMeIV+ITdtd/79O6ozymcIn77fTnMo8V5eAP5q+fBcaQRGplJu8d
hQZOg92z3Gmgh2Cia488uTtcIoXuNkXC3t3PrkDher9LnDQlwqww0Pj2+UbOoviefiDRRXy2A++y
y55IOI3dfw4Pll0gDvoVIvkH9pNi0+GvuNEady4R1YK4uq2hTH8kUKvrl09gNBMmawxhbXrShqR7
d0bJY1MlJqOa7sMXwrY2o+NCekbJBZNLlEvHbMnXZh498gdGh+4odvLqY5hyI4QzRoYg+JuNAib8
9NWVqOcqHH3JoGCHs6s7u5zANfRFUNFv/2taZZqfAkyirqiHlzOQvbPGOPgswDFt2r2a2VbEIQh6
JyrIDO/7UVna69Lb8ogQvByKyocZ2BjTWj7AgUTrHGGkNJtIzYYYPH82SgOq/3o3h6HE6/ein5vX
kxcJXjvpBXxXn7H6VWEJsVs5xttUQiy+BQF7RW3zHzoUz1qJWtqWsgpB1apgHDUIaduNoDMkvDQA
UflADcYdj+z2ZQICnrMmzgJBFpxNP7Oa1gkEpciLU+Av2s1/676+h1ibY6+T6o+RBDuG/WexmKTx
znTDdTvfgfvTguywrJ1j4o4zbgRR6r/l2fsz66Q4anX1M/tPVRsXJjIGsKSffNP+IOJifKDospW+
gueUY2e/fEa3jAKLoi0a+rreVv7cp2fSCgXRAbGNexGz2+1Kh0MQu3Q01sDyjoydR2UT8rb+tOVR
lg5iLrSThAX1pHPqi+CO0cZKyV4bggQA4AfoJ2NY48xum3FoqFkZ2/RK0tUbGA33Uz/aE+SpCqxS
fRfSYy6WLzl9cLOsJFbNFcEKmIVfrfWyQP/oCboJAscmOFBSAz6N7PwSrfXbggpoA2XERtFebibu
lydScQJ54QLlSFPlY0r9zQrf+2as8jf8eFtQAOcJMj7WVPEJ2ls7IEiteGa8A2rTP+NBbiYSJtqN
YAAa8hh7Jfd8j8i97wnj6gO+2cdiiV9UGdyhyVuw2Ua54a+i5984qjf1GKLIgbLjsxSEKi4dM/VV
574F5AOPgjXSlyugyrkIFouCyVJTIFls3HJ2z79Qem8MA95WLDFF1iBB6vl2AgYeL/3XxTkI9ZrE
WVIjEZilpGlER1fNpANuYumHlvCIvlniOXAcd11GY8RUor/BsA+7rYdrf+w/fKUVq/8CAoyN6JzR
yzw8Cq/GGXocQcS+ZOehgwhZjhIMQ6VJc06ckkEp6nmmxgPzO3v7KVfchlyCfSr01yLjdLAVpdK7
1xIsas4pB8CSjOfe7p2+3pAgzS2WgcrRBv9mL2Lc4lGL8CEWxgnHlZYC0Og1XFmcYZFim3+rJ7l1
x/s7ZTI/4MrlRlLshK+HV0eekodsMKiS8mUAPIu603hISMs0vJ2XeQHJjazEEeNmH7L7ewHwlD2r
FQhY+9sBGP5TOQdreVlcLk6RY6OYI2jPSAz5jQKGGoMFpkBZWsqb+4jdbgrCEpspk1luTLjQIkv5
m88HV7QzqeNb6k5pKWCRKX/rMRzN+cQIxbJIi9RDQlmuTYw5ps5D/irOKbmFdYEtS6NaFkpwMbqI
xPd5a1a2m+dbQCAyhbZDdFooOS5WzjMTQqnQGPMZ6BRVTuGLFBhMq6x6XsjwRrHEtc+g9nCj8XB+
UrtDqRDVtcAiadiINgGwhzCV1SzfrkzoJQDcHw3AgC3AguCzzfyazF1PNxAoSRVTA6jwh/lvIfEd
K21qBn04eMjpZq6ycIxiZQV0cFyPX7C5JMr1dEqyXCy/HiGvTWjNbFH4UsE459IKuWwdiRL31Wcj
VPOHdXYdtQm4OUYCHrdgJew4FFD3V79H+SYJXQAX+P7eQKTXebjSpv6AQ8z3uGAMRyzkXC+jKyOs
6068vNJcOaKTgZSwFb9fJbZqZMnqTcPhMH0G5KdOlh6GCaxuKyCKRBKmve/FOGIKOP8dOottHt49
1L+k7hgPzXLILSNzecMdqwCJh2CF87GL+YjxqdhsnOf7ECeJRI7nrlFeESQUUCYSW1XTJ17XWI3s
0vuq2eB0V4btSl+qlLyotpfWI9ypF9Zntg9GsepbmApBeXNICnzpXFe1ihL15ftZkXIBjCRdvZsX
/rN1VL0moz/dOXUF2zTT0TMl7pgLPAVmO8vPr/FaK4GGwOxB2WndrpDMhk5wJCnQmn/I9u5ncjSH
jPU2SHBJ1fd7rtCm44lzwF8aqiZDQIsPt6H3cdTtN4Xue6BM3F1Uha2imOs4vtMOwES1/Ksgxpl+
DVAquBvGmhtBMB9iMIy4qEXEg6o2Aw+J3W/FltlViaI8Y1QXpEZeukf/HkmxbxSUwFel/UDPE6aR
nib83vDgzp3lVFwWexDFKxnaDqp6Q3K56RtyGI1NvAbZYTkxWNFrgIqXuQbFEu/PfjmXJ+lwe1wc
uhWIalq4Bsfif7IQOyfjrW3LbgrtYHMNG5GGRPGZPgVlS56pau+ohzYb+fKD1HuiqP/I73UgUVbO
fjpwPMHU3vghUMPgQDFM++TDu9CpNlHyXDR7Ts3yyYgVY1JJZze9wcRJf0YkI5sT0QFc+O6c476b
5pKVQi0gIOqhk/2E9l/VyBjPVF6flF2nIN1s/RugGvG3AecE3HxbV++8E9vNiSOA+8F8+vG0bbHZ
3yfJ4qprDkQmNiquabyUCJRB2wkvJRxfN1vXEDztuum/6Ci7Kl4ddLnkTRIGxevX9c6tlYAb0gI4
9+UTB+4l09aS4hHlbJxopTIzWdouLVo3YO1EkHZZgCYQL3kJH6AdxQ/4tLIB30gbMGA59u9PuYtW
aHijnCX2WzBCnXM1OWsWWxRDnjM+PstdX6Oi0SDjzvV5gMG4qTMqLK1H0a1+gOl592yhVlW0h8Us
ApLNh3dB0H1IOnYb9Cd2auVuPawVm8FO5pk61l2hcnyKjiIUpqS2okPQfvedlFuU7ki8gIL15QVw
QgAiRwkvyFe1bt8+gFmlaVQuRZbrqUdjE7iuazliHg9vZgvJ3Ot42xU6PTO/yALmOq/psqQpWn1H
n2gaDYkidiNHxFoy827v0+sD2NZeAs6ng0Orw9uRq3OxvH4+MCqePeWYbFg7ioqYG3r4/wB+3CKj
i1RgnytSqU/bZFPpQF6RAHeMqrPM+eeWeBcH4NiOI1Yr25nv14wo44g58qc1LbpB3UxjCXcaV61/
2OU0O0cdicfP+NnboMgDnuyddP/0nYR7jI5EbS2+p4wl/3hzuh5iwmCaQ6X+NpybCl3GOuDjL6Af
7+C744jmdL0EhPzV7o6gzCPQ4BaX9cE1G1szo3+pqRFHqMMCXey26fo9kWNl/szAxC3Yb2QrbviH
ru8HCTx4dftaA7J21ooeyVMgNAdgpaVwpevgSmyDju+MZLuR6LUtJaZAmTMIda1JQtmOsUeU2+yg
GJzIV35stgzOPWaTWMpugwCZCk8i2xYo15qTotw27cfjftmAUQ84l9+PpdQ9ORPY60BvFz0cGV/X
gbMSaCUZaBfb/QKhou6rXgF9r3hPcg5RxhnfJbohvnMP07UfTdl51DoxvkCb5jA29qgfdOGNJz+B
MBvickm99LLI33kBA54BwCzKgAVJijGFs1OQzk6GQtcF7RF5lOc668Dvmgz/2IRcYkdWAi53vHNP
er9yI6G7iqXuU+YYxmChSL5k4sZnXB3/NrwniIvKOwykbWo6DH1TbOhXbedvpok5LjV9kkEwKIK4
a8WG/XZDlhDCZ9Dyww3sxnXi5+ts4xT8KAsRcITby8O/LUhiWzvAbTyEzpw6OFFX66DuRd7mwVZS
YYWZFPj6D5sZShhRpujLm2VANdl04335TPUIMb7jhxSbgqVnhIEGY+FpCguDSo1uo/07hlbn4os6
q83NI40rWSJyrbgdWbHeQpbed6r5WUxauqj5Mb/fRITKlQnwRq3yaJbAryYm0p01tc39bE1aZ1/+
wCiwEnDs1gelQBJc0VT8NtCUeyvlShXM48eu55nEvyFjg4O5/ItNTlg195bdG5MSCS3X87JQw9da
BXU8DQ1wLRquyhV7pxVp78MezNYxetM4hzULVlzQ6SzH3TMje9aBUXl17S7xvlxzQCTNWSXfNP5k
bFmM/8s++cq8ZuRvO5g8wyW4Fzv5Q+4O5/LWAmOYl0L/lKKgEXLAqloUCh0Rn5oUzgmAqnm3eSL5
+fLybp1Tn+N4qgNest4AGtgj2YvA4eROE7/tnR06ulCYl6tcP8FCuz51W0vjcKnF+euUNH2D8eFt
frY+7D+DzWs+xRenq+D1K2W2FqPXkMjlRWRsSUWI/pxOjxyxKlVZNt0cF3DqEHSY5aznusaTNmXH
oJ8Ez8RjBD7cy6UR8YzDQt+D0Qfh0xt7ACK9yhomxrQR2CFlkZ4+SkLx8+ZvNOSiPnegsDHCHIvX
fS+HHr08A5VwGPDN29v6X8egnKMIiQY+2rprjbHeBiZAmfxa9VPmEM2WF/HDJ+DgywxGfAFddPPH
t/YafqpOwRHZcVGA9mZbcajMlqxP1Z0iQb4rn2BAYisOGLPPcNeEuHDl2MS0mCjzVi0DkRszMLEB
fHn03BU0muRTXt/LB7bBdeNztYrZ027rfByng8bWJAL4cj+janU3VeOnK2edm06YoXswd64kxZFN
/u4FMYdszcVzwYtBEOP0vJD8C4B+2ArzSExiwchpU0Oq2wVpkYwxLvU+k3AbF6SalCxArgcRpbJM
W0Fm94ynD4gYZeNY9nOsT5AZcULogxcHcFK112zkFr0A0zMSU0sn0rl5EQ7SObv2AizXVEAIeCd1
gsKcwP309KmBKMkvxSJGHIC2Ery8YQNMZvyFncud0HXOSNfOaOXLMnLV2Uve/UT6N0YRK0bIpuA9
DuInO1Nr5cBsX/ge00oA31YM/CuZ8DBo1UsfTildbVDgALVtzZIgPWxt4/VaOGXA2VmRKs8eV1PA
eN2C9aalM0tsP+eHb5zp5lbHyAsfz9kKgPYzoIgKNCXw7em33ThbBPxp4Qq577cvyFoBAbmpS3Lx
rpA59/E8hAycRXoC/poeeXH8mv1OGjMweiqhKVBlVD6J9tYorClw/OjubyZ4yNtyxnIZPrLaVYQ0
1ff6HpRyo6bwmHkmkVNmJUI+lDNog4i1C1YvEIoDBYjym9x17jaqU7kaj5XyG/GWQRq+i+rUBvzk
iyJgR9CY+w0WbEiQYc0W+8sIifd1pZ73VKcITz4EwWl4cy19tAbaPPIKzc702jJLVdfXPrFpV+l2
Sc/NYC+QSdCqWCAA+HrL1dfoktAats8vbNyVaH5Ok/85vZ/iXerNz69oUCLzRaHB431Z/rG/JNhW
N7Ki/1OHK3H+s0+p9ventKtfYiWLhsdsbEJMqopdfj8bm7SRgK85w2iU8rGjf72PhF+109FTDt/t
IQ7dimDUzfLgOayRNwhOP62fvwaw23HZOAWI0uylaEi3yw7mP4qXuyxUD3QUyId9YYa/FYTexS6w
K0poYX9hmPDsVq+FozhLYrKdL4/+jjAT2eWAk0kgIPTjkWkcI6KLLTMFevpfynqhJ1ZSuj2QnPh2
Tex7BhE2g4IG+jemoHNLQxw51d8S596tBUgZOP3FMCQrUS8BisDn0NLKiaZiQ07S9xuXRGHjq95L
13uBHm4HGyRGoCYRlRos7YGK3d388nd7dB5+vuaAe2Bh3ZcKCJUWxkHqrsWaZelkIbOn5jglu8m3
ZoQ7HWcKJZ1IqQiMK5O7KCPblHjcMpvsqN5JycElEAvQG8Q5nW9kqU8V9ADjGCUVxInQXgkz2qUg
7Eid02pxYZw4QAlHT55qBIdXmy8MvqcosPrdcZPcHdzx1yaok0j2isHi3ruPPVmQkNqOUs4HtoyK
C1wfKhlS7bgG0kv21Pacmq5TsGx6y+S6Ct1PqseAc1hXJSxT4ylFQUkXFvh6og2yvhx3iDORDHSh
NjiAH0+ErYHWGIvIRGLHlY9owy0ELBKGhG709poqQcNMuABURVBrMkuEbpE5HjBBnKjigB/w/meN
zMpNIgFhPR14Syg7Df4tGSs/bsWmbIaNSeZZUauH9p26h8ZczE/7FcDuW+9raU1Fr7KjXaa7QWNI
vCOHEt4JnIrCqEeNAyDc2UZMAqVV3QCSI/fiG/+w9B7oC5I6K1wjplXAuW2iiCarW0ZsNmqY/Bb9
bva78PFOuMOmFVyimhoDB3BEQrRn4Bi9R3Ii2TdJdnI1Gm1w0DOA3+4FucfizL31+S8obyheNJKe
y9yGY01qNF3Yvb31YgxMz23q2YEpOqFp2heA2TfwVD0qJFIYI0S3fDQiZ96nlHMq0aLjQ6oNC7qZ
v6IHf0pydd9jLpo9GryyXqKOM0Gg3xokqWV6k7z4zTtXWXrCRXh7m23nTeQp/wL0lYmXGfv5DXBJ
jEL3MklTHghEdlabOgqsaNKz31aBaEpFU7k7OJwHG4PKV3E2gsKRfS5ySwRZ4TOLpb13FE9GM0zM
4UjZ9ulZkdjkRwyOjhZVFSpQUBdR/B87uGxB4xxXf+mTYV9EMREk4nOUBhztRjLdYstU3ig1MWPh
FZKx+CqZsbqL+EzivIamrq+Q4bfjtEBbpts0qYIzF1dKDNV6y2JxdVEWn6k5EzaIGD+7Nr3/mR7l
Jx+1VNHJzEsnuXT6XwhLfFnVGtsvvQNcAvskwz84smrHyKVJ9JSWs/MNV9HVsUCWuf1zDsk/fXz1
TYOp6tYxkSW26Fj28bIbiub8aGC/psC0AyYKc2jnG4d7lgB+ujN+i3bivxofsedOGqf+hAmxSiKp
zUbrVXyhK3cSQJjh1A8hVR8mDQ6VE4DOoKKt3S9HdVt3FJNBX/52PHMw6qDndy2KEGPSuxoT2c6+
tXjjMeVXgISPC6vD3qeKo9GttPT3yYexpyLOukQ2Orb9uYNjY8ci/g9/zmJsbpv3tZWrK4WDbGAB
dDWMvAN9EVQrxRFSxMakYRy7JM9e28O3TU3zedn7QxuasO3foI9puHyGd0V+2cqogISw2E7duYaj
KsPIIevXZCAv9UldcwD2liQbSzmEm6XbXUAzsAS2jjhjGjJ2cWS6sTtXnYGTIhSguwtAhDChPu2A
5lDrWD9iV508wUZ07S4UW1bSEDn6LA+MskDcQxumCkCayCL484L2SwhycqFZWMe/ctSnUC6ccKwM
gQgvf8Dtkb9QcFFdqiYEKnIdGOy0ZKHEOujmmCW/RHI0oueYg6VkCPK8rxbI37svnwKlNnmCP0Iv
DQPhoaiHySn9+oWS7TOwojokr3dQL3GoHfCMF56axw5oqDLt8ZMktWyHftcQohDSVHm2sC07aX6N
fBOhgu3xXrTH4vVzdgZRqE/vzx8YqL9lg7tJ445AwWLVOmuSPMQ0vjOJ9mPPVmG+qjLHNSrwUWpu
TWvJKKkgtx0RpI9hhtbjg8XNzfJEGHtsTy9XllDcZcunSXU1lTJpmjsnBDPR/NodgbTWXl82Duuf
LAOy90p21GtQg8d7wcFe4d7OJL/J+v7kVH50nwOr34FdySriKSlT42OdqRH6RblSzg8nVgIgQo5L
AaFC18IEXQXJu30fCRPN6sc4uAoT2BNRNSShFUh+XKUG7YBE7SiOONUlURYvGu1x6qVvf+uVRckU
bUxnM/BTcMWFI4rU0Lcht6n2NHdLc6K5jqJxrS6sLI0kVf8y3dvQQsN6AtpvIFkFuV+sM1PbSrPW
aSjy2cTkaS3X9cI15SwJaO9AWXHfRq+d33BI4L+szu56KkVAar2ekptMbpEvkCDHe0Seuacg5jig
etRpdc33CRN/qH488z/Sagg9vove/F+9gyY0/RNsrc7QXuRzPg/9Rc5F39ZNcYNwraUN1ZNEacuK
J6ltlBu7AktIYmIUUKohDy81+deFciXpwOtYWP0XR4VHfSeKDmq4y+aI1BvnLy1pjUsnlO/wJ+pu
VhsW1Q+TAlRstw+QKliw0ka5ym/MMCqPNVnnnj2qxDaYjMwlEK76+4Vs45775gnifdYsO7N5fDrf
NbtOZpzN35l6Vy4Jf3y1jZidNbxTv/GyojLNAzl+cAxY1GzM9WpPobPLBghtcvniluJaOOWVKWhy
QG9C9mRE9sZ2vs2sCxOFl/0hgdbIZQsqxT19efK0q0uLJ0HWnF8Yv62UXcFxdB3L6Sg59sFINHT0
m3UhCuKdXSlH8uZBdgskvNC1TDW+cn9KQocm9jCIlZC0gIga7uYsoGU822naEYdtOrxLasHxn1iZ
CBVQfcsyrN/F7Df0HA7/ujeIywfPnzln/EqjxOBQ9vnumso/PNpnahpm3TonSxhaLztOdjTJTA47
3Xyb0T1hjbQWFQYYTct8BQIBtSXaQlFHT9WdvXJuJuNa0TKwtbgijBo3wLWwOXPGwEv011rw3WOc
IPRulKtimF6oo6izPSOAawdFQD+hL9O78eF59jwC5MqvS0+iun3ER+Xf99VJribUyqnUh63aUhuR
Mulom3IXIcXBYEy8zRCPfW16rmH7/VAMWUF/fmLc8XBDQo2c88E1rIktoBw5CXTeASGbHwvJd3/b
isE3/wFGi82tMwq+o0/iDab0S/VIXIEGJ278LTNINf9aL6e+RIV11DSU7f9a996Ktr79Pn9FxBzy
/XFB9u0gkmAodx/NlgFbGxN/LZbjtgV1SmHuRzAKqTFIuEVQ6i7WhJalEDifRPVKhlBTlKKDMfpa
1P7AYuOuSfPO64h4kMR43hqY2eX1P1jmdQ/dof8tG6NF6yapxb47zIQbSHCFZgQ9ZJELJGeTP4QF
qY/jRwH4inZDdJFI4elOO5O9LTxrVjPxYJTfISKMyiYOMELqJNBNLDmvjjBnbANVIXrIx0sMrTPM
imXJ+Wi1QfECwPYOwWee3b/uz/kaIIgPF4CW40SUkiZVJsC0mNhR7LoOMoDcZW2nutafP+fcRIz/
m4f/8I1ZatxV/b84yC3/DXL8FIQqX/CnegLt9yq0PcfEHdBCtjHstPmPB+39LeJCo22CwJ+7cBgl
n7drlBFGKoGANpQCEeveCVLehmoXzTF/3oKYr/VQWl1wzGWxRgLgjQl15UasfttGI/0k+63mn09G
jKNCU0rAUS49Ryb3hnFvOG11+U70ige+Fv5FmibIf3Bcndvif/RjGdMmWXKb+CvM0HiG7Mh3Ra8D
tHbhoemlSFTbFilqG39M0jKDBFIBa+6m+NDiTHiwXFb7sB9pb1OcmEkKoivscJ3WXOMXqyvOOggN
sSi2QhdAtUe4lWXX1J0Gbu7gS1IwGyKcmfecK9yUohQHffCFFznh/ll8GDOneswU2T+1BPh3AUwX
E629pF1EoFevICUycJ++TPjGFL6nQAwtZt6hmZwkK/uW6ke/iN2xCbTmPd6PKbSM0kjZevj6U8Ql
BaTrBYSgZgz177JZsNu0RHDhOq+FIisJNemlU/zmy+9/u9hSI5oWrrNXKhgH44YrnCWZdlSEbWk+
6B8wpOw0ODiEPFFYCGIqotYmjCOwE+jJVA5yoVp80gzVW4iZp9O8Q5Po2tBjvND3JLnSa8HuzRtN
6gpplGzsDJbQIeAgnyZsNOVhmVru0eWjvrq7Dt3ccj+Bb+wqkOyuxeGLRiTv6IC/dzSIfO6ax5I/
4An5O2fbxyLgvTvQdgbcbeoSOijb4GTh2HGlHlWBBTwsieyfmQuf4QGplTbz7apmUp66UwwyCu4q
vhBHdJoQm4/eTM0yuW8KAGF6LVck/zvxat9BizppNmJLvazGgTIzDv5/AzxvBzNtQ3MoMySncR8D
01zmXWpyD3IkVCi5hgG8WMxB1yLVBiUg8cIBcT+u32LMn7Iq72ZAT9Tr+gV4EGlENdA/srFuUKzR
0GUpaQD08ZUhEYq5A3e35AKIFizu2AMozBWJoQ0UcrdpcXTWxhkW9Qkwa0MKblWCSF4SrWk9BAEQ
6DFUkchRZkK/WvmeWWzBa/wqxXsRwz3HDNVPTPJWJkMIA4TlNEUzlk5eT5wJm3r8ckCkAdFxPaKq
k53eiiqYSdCZpGq5RjoPVuRHMFh+dEEXXVN0dOJYSSvH+Og0OVwin/Y2ok5CxCJZ9rEmlbKhFzcA
TrI73zYH7scR5wcAZZxfRXZRtMtYHLnUA3AqLKWhdDIvaBdSnSC9N8qSKV0WeamrI0wsdlmk4ONz
8p/Erv7yj+zm2772wa3bFTe5Wb+3kqjrHZlSktArCXbDbCUH/Wbe30GpVv+7xipyKqAriTR5Itr5
liVaggV8mxZ9pMsPk2uebLlgqIpCfce6+b/yYPYgtTuLNkR6YgPMivb9L0nCD7Ccnl9TV4kWq/Y/
edJ4d0juYAHqL72rbTY2i7d75US5Df6Tqj3CI1fybllQSrmGQw8jW43K21KWe4w1pO77vXj2cnOk
GBIu1ftIREyqT3IMFA1Yr2blEK0Gm8GOEspRtqM44ckb7NW2QBRVIgU9htBTHRGdr0K6FodX7jck
8ZvZ1ogeJygGgp6WF6i16QZdLsiNmpzq8K+g54ywQkyegDwFVE1vknlCg07yZ0EGz0y+oF34Olsb
TLEGWcBxuXMfTxRtl8cb/qGhUN2W2AiYUWNGtqr5ymT+XwIzmom3jM3h3IIQDvSq8FbwRl0jACOU
jyCpEliGPPEvBO/juyWlXo4jPEd7E6P7qGO4PPEsiWyBlrv1eKyzSyRvUTcYByjBpFqcw4bKEkr6
TZhzgV54kl9Mcqdmqu4hD2InVXWv5wpKfLlMMUqgVDQvI4xRHJTTZGDAbrkIVfyoIcjiaIgii/yF
qT3vzN+yJqa+o1KLQ6UZGQwWYe4z/Xu74uTgJLdJYCCgObx5okXDD0+hSPE/j2Y4uGCNA+cXZGq2
amjYzOLgKOChwAtQMuAHf5n7kgdAi/C4yo0rUW5I4dsLlUHgVg5ZSzH9bPV+bXh30Dg1ioT4eawi
2d3YLoVcUR4/vLy1f1fLX5D9eE7aHadCfcAkKR1lwIdNcCjfgFMNwEyQVMTGblhuaEbav5HBhJF8
cZOQ8SrBOa1Cr0iguB6YVV78bYdu4kV6G3cgdlepayMQltMWQRn7THvpEvrlf7S8kWOCYhuWXT7/
ws+4ZxdXx1Zsz75nwHoJxo+KIPl5KRsAEgb/QnxiJyE4F+M251UNqtWj9El17PLaVFhlKgrjRYY+
i6CdkEROqE6FlqYFoTAk7sKZMtLVr13UdZvVApULFuKziSbj17hlv9e+Ok26t5pTXNkFpmQjsUeg
3Ku2/RmIg5mNEqRpDKri8I8DrSdQC+2eHE6AhtgJOs3Lfm+jyiq0ychVhtIH5+jgWdyF9tWz/C0O
mbcjBtoOSRkc/e1dEGJ7kzJqEKIDawMUeUK7m0flZiLc0u1qzR8Rg2VkzCX6PxwJs2I6Llf9b97o
IHlMoRSe0zbs1mZuH9OFGt7pW6SBQexq6E6tUa4InsrNj/3NToeWSGm06Ko+146bv8NHipk3DkwH
9obqcuGC7jnbYP0tFKmrMWSxDBG8+LKaH7nE8a01Xmto/Qh6sWOhln1aZrErJwnz2LRyyjyV9Tv/
hUtg7a3hp8mt8IZSx+RkXfGz7IXGzwe0DzQAOj9QlAGzOq41B4dmqPffcXJOvQ1SUE0n/KNHEgb4
iGf/GA4+ewxPx+umdy+so/hahh+vO8kZc7a7gf1ArTsU+N15g0FL+ycTj5qMDSqbJ0X+AScId9iB
gTEO+c3xQAHUiU7gHTl7drohZWaNKoooT+DcKJJDjR8pK3F18Wy6Zelii+x857QkwkhIkIXwukI6
9b5c3jrvRJo5w8Tk3YrIRGqtbFUMRSbpKxgbVVef8tPijOVIbwNJrJBwNnEvaIvB/mwnfmlaYPJB
v2kwag/bcsL1YCcXAtMpqmXdtJJPFSlt6cSrOA7P2q45iFa2ahZXOK64o975ML+N85s7dStuvad8
0N+Ynp+X7FekoqryLLlGKA3yNNL7g1Vlb0Fa+kaMgjg1mJ/w2ccqzqWuih3mc9YGzse3+d5cFB8z
6TebON0xNB6Fs0PBFPooGYtSaFWSZH1St31gFnjuogm1QCO5CFtVp7Dof5Ox/WCRMf9aW/CsE2Pb
bx0Cbd0xEybLT2Ci6Ywazoedwecb/+Ggf/v1DXjCNCU7oI2va21X9ogAC0Z/Rgl2WrRYOkBuAEIF
FVjSFsqktAzx2Zj8sSrtHZOJnj6FfKWRMZlEecR5mMD6byGM0J0SAMeYJwwHNS7Xwd9QXFmJLsGd
Bnrn7aGMozeXITPfO5L1ns0kI5p3tRbePiB0yZ4WZKf38EDr7nenWrVU0FwMZg570ApAWokiZQE1
3ix9muMWcWtZkGRzBkA4WlRTiDtEVGsSbrDiou7/hgIZY2OkkykY9i7raqyEx5yH+iI21UPKze9O
OMInNWvuwArSLkgLwYH+Qk1qJjhLum9PnQuTEeGTFpTg9K8RYunpS6MOsjiwyVMh3XpdW0JB5s40
XwlQtcrOURDD98NlIJ2CYCqn0Vg9/3e7ntYeDXVH0uT8CV0Cu5AbiRe2Mp0sF91xqKegQ668kPF0
o83/z8tPQz/oHa/J65Q3E7GNmeAIguM6mJLkRKPMDwFCa0IZBmoXaGiBRgZj9DRcO0GILzPXd9jt
TSLnX/J/b76fLT4Lotee2sOL3enoQJPszIQ6IPsuf/Af4soXzAgkRzbAqONMPg2/psRawfFxzJJn
uCNlw/gwRJ+0qlG6jM2LmO9RRskZ43KserIGLeT0cYdxX9GVh3SYvGdwJ7rceo4Tcdo7LFBBXasw
Lp2gl9hccWl0U+69U0pRrk0pjJM9ofSpmIAW8m4cCoFb0bjpUvnVlJ2tBkJ4oON59HGL0lydS4VM
laIUcHor9iwu+9MB6UT0D5VcosipUIIonCh0F/D4tJBAWgJyHdTfHMQ2DJL/RU+7MtJKuvKxkfZ2
qly9kB1pOzlpaLVTaZ6PxjJm7sfPYewqymdHcW7fUkEtrmXl+Z9IfpiIiDv9wvJv2Pp99rng9RX4
QydbYuOpa29+GOouA+rS5aBuk6TZDbj7ngKYZgc0tuImBU0TCCiFEHjWhICyo1uh9jNv24tDOsYi
2Us4Ip5nJdg8G6RE+nznIIudrlgjvghbAaHrHsCDF3loXb5KfZ6i04LLWbvjaGnoMyYZ0nyrdtB2
QKZi1M/Xen2SUNG0nlJ4xtTx9015GfxtDNoV+6c6cY3jT5sdGWK0T30wBSCltmVvWM9cR1aJUeWV
yhNU362eXk5GZbGNu00qgQlDuQ8C2EdVzW5JTwEwhSyQV1iR6vBNBslGAadtL3FNlN5lMnAcE3/P
nmBeErKF9yA5u348aH1yTOC14aBl0oqLht2elOvTuZ7mq53B9oWG+5hsbWQAhvF0ZDvkPKYyDLCG
l3FAd/oJm8oOK6z5hBb8m+h9eX70AsR8fOB5HgYNmXeehpSWB2lsrvoiH672Egjn5q47Xf9lI0kj
CIspmv6srK5gGm4LastreSjtjfBfuBlMLzMEyt/U0s5sVYR1xVyxXQ8CJAVGQcf1akfAUCBctCU5
qGYNeaTzD8evl061Yw0+PxB8EdbycH+aZMYk2t5RrAOWxTqcg6XARtykCoyIWJo4CqQ5VUAZY/Z/
ghHh45jmEtQqZZ5Bwxi/CBr/v6DL9FhTXbBazbpLwEKVje0HX1z5oZum19QShPEe1Ql99vpcRo2c
hGHpuBNJkxyWVpbhsZW9p9mtYROAfaZkp7rLr5/I4hUlXGNOYZ1He9mbNpyNcGbjU6IOr5VVamry
evoOeAoGbbvbbEeNvbfceBsBNyJqLjFsRgZPZz37IBoEnhMgl9VyBr5+M/dnIPpv4y7KpeR3CpDo
xDuCK9xbu0kbZPXbhS09JwP8I95Vq8PalvZw1DcZ7wgGjlxD0NDxWoaqif1O76elIjkMeFe7cLNM
CoTcUgD64Hy7jQBqfTPYqogFFAwSnpQ/8VNTxvNiEsMcYviTZOFoMnShewL3Avm0IBvZTTpsCxW8
Ob44BPwVeex49kH8Ka9gYCJlvCGuKcnkNCyaik9vWzgeaGVKfDEBmBSmLjtLFuNXqqDixPNFdmeZ
5s4b/qPnewARX5t/rguHrytZfXgGvief7gyMpsgy8ibs8G0aZ2X7R3MDqdKlmBZH9EtFh6ZCBkKb
bZsGzxLOA0t7wz/Rfr4pZAdvTF8aMpGVsavFdzoAooTuvc0oMtKYxQt1XT4ojC6g5pLSKruyKyfL
WFjFP1GUuD2pWcJHTBXmFl86bZft8hJ6xZ6B/oeLITkfsWKKNMMm4opS4wmYp0b6FHmLcpGbomIW
8CJq3zARSG+5XXBFRNxWWD1I7xMVyWwmdXjsP8oWLNQDSows0eyXzYKxNRLa7OwGhjB2Eu7I0vkO
J9wiAO6LVPveSJvW+K9fkSOVY5rsUjfGkzcmz3dgxOTk3Mq7MoleYGLKrV77h84N41kfRZrLGxT9
FGzriGDc3YXwuXABwEQpyiBrwQw9b53UdtqyFcZmMfgOO4xjrhG8j/14CnZtBvl+fhxIUzHBH9Id
3fF+NWWIs5E4aCt60XHFo7Z1oqOz0zlqPnJ57aOmil7xEIHlAtbSfg0aMEFaoRnDGpzXIY5WSNmF
U4Tbn6w5ZL1zrS7WCG7H1YLfDU7wq3QuBXmALPS7lwmmW0mBDsYCFYHCtt9hAPtAOEOrUgV4dHE6
y58/MWq0yrgSPVxEd+zT193ILWqXBjrKFjVSWFpZyGlkNhqgDB53LZ90IFb+2w9aS5RcAyU+r3dP
PisesLofo9aQhfO8LfStdPzumaH9aQcBfQ6tA5ndkw+0feB+bhHgTHXAhO0PUBJLrhx6o0CIqJ/7
izeUXDK5oa4UwtSbwzqKciQsbSihyZgIcJpYwj5/AeNfmsO7ioNIhPWQeQlKgPxOc/XZoOw1P6BH
MKqL/3xJHwKNF6U3GTJbr0xUqsAadjcdumIqvKeT+rKxHDaujhGTvSeyFDWypXE+W9CBgVRd+/id
md/tJ2Q5lENQsNkO0cpUKGFJmQURMDoiH4klvH9b7iYALegOGC1mkNb3+6zTMGq40GvwRhW+3Ldm
332zrVRYpnkdT+OUjkxWeXng2IUuWusaIWIIIxXSA4aDy5tQ03gIs/sTncOzkI4ts+8JVDDyXu20
Mr3So85vd6kQpypDd2xaYy6PSWoTyP7rRWAKtFCyK5dpJXoIbtZjz+RM4tmwv+SDIwNnRWjFOqlZ
FtfVIreU0GaqBQehlo4FDIIG2Cn1b5gDerhRTm3jKTn7JiyOA1TcMiPEutL5a+UvcHPPpIcwyMPz
gRqx0a3YPygVbERgv1MNVu/7fEjEe7mTqrsP8AkQx03OGwvJulT5vnwsuLVEdL4eQRoDOnxpiBLq
2RIcXmXAicvuGZAAoBifegstvfpQC2Y6xphCpGXhtFM92NFjb9LeUHOmaMIPz++++u/I/8aAaBHH
ISjEz2QxNkzP3tJP8whqurrogbcsBN39O6+spFwi2DDSpqRKCIww2UxWU1RRtvuAqBIVDfGzI0zc
80W/JBxp6S36J3Gv5ZLDuxvGhTO2U6EfHHnxni8suozj3eawkkSoO8e61KVzLpjaT2+oadBtzT2w
nyP1rl4ydNkhXE6uX0B8u9uzG9NZlSt9mI/JSCJNU+ysZWvEQqu9xWBQ+u0O8G7dIqrdAgnbwjTS
JprnvcCAsAYBZ5SUrcFXUDD9pc9B48CBeu3Vfh+CIfAvEhQur2Www9cWXDkCXCBy4q1sFIU4tCXV
8U83Z7+O7VPFOpCkOVCqSv+TCjBdCpjTt93PJC9gvUSBrDdonQ5tYxJcisZfzphTJbzzUIQ71Ufc
8ZxSGpYYdn6Yr7/rUe3ToPA8AVCeJY9MXywOlCvNTNcNbdRNCbk0XKcrZAHwtd08Qyie4n4JMgnc
9bpEkiXCtR8tjOliw7ODMh57eMAs6zIUsC7ooUJWVAWJ+DEJ3GZNEUxA0vbvaN3kFAqQ135t5Vlb
Z1gVZo3ITZWhFUjxn38N9a3QNCMIKg8Ht5YaubMnCfp/2yU47S3On7I1V9tsiwff07VPuTj8d1Nz
W1VPRBozTE4WSHgla3jkynPgxcyBvCd/+gnhdZx8JNz6111vqKqghPTm9X85Gf8gAJ5qbQ0FaOJQ
nP0s1mzrQOKCWOo5+T/fQaipTLpjTiTaRYdR6IU9Oi8Fh68Uuvm9W6qYP5Z1dYkDrsJX658PlPVE
QrQVf1UUzxGvCkGkqwRYcT+Bzgd5XrR6CRmAN+nH/YYw1fIhTCBr7NeNmkwsjEsVFy8MDox03RBR
sal4fbQytLCuyFhS+c3j+hnRlvQddeakDx72+wErJvRddMWfDzrety39VRgDMzfu1GCZ7+YyNLNX
rmQDegnCzWAZ/6V6asu2AFWedmMoR0ahxaib+IZtWyGe2Sh1jQ6gSSdqo2LaLYOaa6WQnHjokkE8
f7sVYkSHYq+IdasFyvfb7yc2iYyEH0RaJ566EbTmfHFPIp06ZM/EqV+fYQ/4ihSnhSbfrnf+xcN1
6rhpBF6hWbA1pqq8sx4vZfBwdUKmJRMzOP3LFJtInMdvdGnxhRwRvXKHk4UrqUJz4JfZYx5T+QFh
r2Q8h43VUPMgWuey1OBw8124RVqPkx9nWv1JDZH7rxXMvef13DvAuq71Mw5lsJCksrVQ8X28cpT+
9TzHXqBMMw9za3SL46PkrHzWbUPGQng3jnUJcQvIQiVE5ic4wIc4PdNbFKJ/mtU1++QLAE6M+o3K
B0HX0HaXiyO/DI7WYCFyvIPx7MK3NnbamQCoNsoVQljgkFtOHxBf7XHiighjzVKe6lvYBBej8UPk
A1hUru8Qg430yr5O1vThWsT+tV52j6/I3bBGZxknwJ+6ZiHh0Yr7bkpMOB/QfxnLNEX5b2lS++nM
WUbOkbhCmE+hAKJ2AvuJAR+fRgGLmA0Pwp3CI4R69aJbnLY4VwzQzaHtutA5IrlMAhUK5rAWtbCr
XWoUvDfCokdEDtcmdhj7k7ODTk8cbo2v+VnyNIWYKYt/KovriCeB1s4gvDIs11yVRuJiKawXYLNc
reKh8faf6EeglbS10F7X91Kw464oPdN4Z99sSwB/Twud4FHv8igyWoGtC1j8B1l4nJxpW5Z1CXYT
SEmn4w47hKMidnB4oPC8JTIvdCgRkJCIHTstEbqo7BFPxRXdGTCYjRyKfS+TbY+9zIReju1LlVli
JAYXqODlgYn6TeXGWcYf51ygc7IAnPhcPc2ePr1WjYkfweszG1kY1OjGCUssqHyc9GkZHbPAaNkT
RehMtAvW8Q7qYZaDF+o2o79umucSCY+bxm+qN9lXh0CqHdDZ9qwnHd1tqgpibfbH8GsACY4UWUGF
lCq5Pmc2YQWrh0XAM9zec60LdphEXDNcClpM2Xz6/nzcRZCHO5vXX5hY33L2Psve0AKkxqwLh70I
5krHMVSHmat/JDhEBZ4hA5RF8moTeir/bNa9X0jiajzAFEn6qOcc5S1h1VH9ccs5w6loSOlCuoLp
y2PySp/i/VobQmR5PVA+4kDXt2s783l9m9ZLQp6DR6Z0uEyzA+QAaVw9jxlD7hsVX9pqY3uhaJ9N
Zxi23CJUOWkEjIC5wpPAKww6K/7CsUmMTyUj6MQcjX2o4areLw2ZERMc1f6qtUP5zHNvtRG46vx4
fwO1na1evUvtdNkhoPuECp91af5tOM35sblDHvtZvx2CvbwG29t16wKLpoZg12O/xOcY8bcSi673
GkpmeR+W5VbVYGxectv5w67ZOiCYEdqkslOuRMobwxjmU2m96xvF8FBvYeBwjTqcMhgCL5Q120nK
oYTZkPfFiF3buBhWFCQUU8niSFT87Yz16WtMulybdnNWggyv/x/FeyokIl7zeIDR00Ir5dsz85KP
6fFwgBgbheD5Huokc8qG0ZVuChzTo7WYsDlShsAXt2mkF5AA6BvFsYKcPwyw33ZHYpvQJ4Ni2h6F
yFBSEbU04LC0XuDn4MOr+cdu/uV0HKp6t1GjCq3Qiq9i91wJZWKUb9yg885t5U2CUwL8THE1ifVa
N43jrrSe6ncA2d//gRCX+y77o2bW7xUT/ESlNsIMwKS/SVSaKTl/0oypRDeZKEj20Kso0rbkt070
1vg6EOdmeCBeCwv2pFwmfYC90SpQqfPrzmb4QXkehIAcQAfLrDUi/LxBtdWmMAIS86jMq5CZQ55a
rNqhNHWKCPj24QT/TMXLSZPZs1I2A4Dg9y5NH1TV0LifSYklrc2zvq2xnMoCeb3jhUl4XgDJNBU0
eST+caVWGk0vHNsOfSObgK43r1H9YxvmGrBCf9TPp48EoUrtJKFlrZD4JqPB+mfCNfSII8keXJQP
c1VPoQK7TiYHwDjPjQg8BD8qGuyqa/W00XD0L61LGhcgzpW4NdrfFPHTdij5jmwVNuaQiiNUsp6X
UMBx3QoTtjDj1+9sKWrle9w2osm7xbkrIMe8Ltr5QERqlasdZETK86by8EoXIEcPz8QOA9GEHL0g
XklkeWcicNLasoTWzOv7igeKiizMbeHRn6ccNhR/xPRjQg/ErnVGos0zazgYg+Np/nVUx5ULSyKX
sOgmt/Hd8P47PvT/kJSWVl2k3TLSD2s1YzTvjwT35KWvytNSTesN6QqvqMiCgPsWh2MgFifDxAbY
Yy9cJeZfykQSG9sQvuWaOVipDnywlwbzJhP+mpHtQdNdrKtTPlO1QpNGeQorvfman/W60WOgttjZ
R10N/BT8UHGOyVnq6yKxLn1ThyTeG/Ec0tvvHoYnfNfNw98r8sYxpYnEOjvVNNGYnDXYHCZ3GPTA
snDVB+8lUGRdkAJpisf/JQPk2oFmGtQ+PfrB2fnPGS7cTOGp3/1+/iMA2L5SkpUB0/M/jp4J7qwj
wwWjh3/K/GEe0eiOA8pqCrKY4bRfhvRi0P2MOGDTo0T5NdqfQgEf2LI6uPC2h5e7is8TTdlCT2vW
sj4jrhq+XO1tiQONoajvOOtFf2QXra0isC1x/xYJMKAUT6spkS0YQW+01Akz3G1XqBRHTmrkWJKi
0CFKBrzPwAHFXA1nWbTtNvHUpd0WIB0LPE7mcQxfrx6TqKQdzZOFfkLXE7kjj8+GlxrWcn4Dy10J
vkX/sLu4YkcnCVyxsjyD4TsbVLLu+sa4Ji8hqF7E9d2pjEflcdSi0a+yitLNANZt8bvpBIGbPulj
qSGIvqY1ybR4Dky4InZhtnPyAALAaGxdGryr6NsAssLuF4O0XU+pUa74UgWiVdObGhXn50lWzkKp
yfjjCuMt8l0/J/4mfOkgtF2Vw+DP9rCdnifkPQ3W4VPIkcSx68RYjZIwqLdcB5fhWZ/IUgcYH7WI
3iVcX8irdyA4BiVYUwI9lj7DGRvz9P6AnhkHtyc0slFxQKVGeUeJ4KjTD3TJfdrN3LLQD5ZIczvT
LrD5cVPe0uztjPQAsZTrTe7Cb0AFb6LwnDgcfk/dcRD6x/9ePEmL5LKxK3fJCMP5Efn0s0KIU5kZ
8n7uxfC2eC14WuGITymmvy1ELXhY2FHsk6HN+VrsRsynN4zJj6miWsFcgxSKaR7z/rj8lQKpVt6z
vKYRnmCZVWVLlVfCpTPgZbi/1tfb5AOXnXJ+SaWppA00qrh9VfgHatnNyYNtCDGC/Kf8t7kf311Y
GZGsNC42KFq/Bp5EfG2iDh1A1wbGtgKAxkyJyMZ7lydAludnXw2o0ADWWl2fgWb9QCfvj7eNlodg
sz1SU3jUR8FXg+gkn/7TH4cbiUrRRw5lWMoOD8KanfDUJ90ga2KEUG38gTcm0msAAR3r0nrz+ZmL
bQnTTak0KROdPFPfZQG/0N7bqm5AZq+82s1JwU2b+M0ssXtDd0+xavajj/Ds84ddpS2IjdwFrhFM
Jge+kI3pDsZdVUOLOxBrrXbQy4ttf9Pqrrwt9gBTQR2AllZ6/6cfoUazJmRq8d2w6wIkFlWL8hSH
sSP1fbfDwc0miOTqFnqerDmG3s6zfpmHsuym1cZLchKbwiitQSWWMWZ5MUEdrC3T6hn7jYl35PWw
90fYEgY1+ZfjMZwBbMiJ7QSxgoJVC8wQhDnzUG9jIm4UYsXEPeGCBWlD6dfFhefFieDDPkLvWZB4
i221j9lENB2g2zTtjLfMl+/c06s0axa6Zv88TJDkziU9tsBC1YO7wUuWLLU9OKzcMpNdSwp2FuGd
wwTxToiUi3XKda189KLmipcKxaWKp5wLIGHbouroaJb7v9+X9iOF9wzoS3TEG9hQ5iEfDF9fVNw3
LypkvKy3s5JUwra6KTLufJizUi0U1O6R/I8wJbOY1yNWzow/Pjv31XD/bsKWRPVVUakxxiCS1r9N
yWoI+f08u0V5IqZIVHTJUFixtK6lBC+04rolm8M/7MNOnqBxwpNDvrOKIlE0JztmKtXJD2SuwHwA
QZVaqLNMVRBAHFGyjIAV1GVVZIxJSnmm47wyB8wuvNGPvpF1TECxjugYOpBUBFmSdqKicWx4ec78
gCoDvC0Hk+7FCAE16mERhgnO1Ykw9nEqxw8073g+Bz8OV+B1Lu1c/As4FWsaXiDNErE3kQKLg67L
ELvqZaUDkTW5vP8aHdra/KXZXfw0K9dd6GW4uB9ZaORWDTxwQkwQY9ZBoJ7UHj0ta1IlMOW1IUUR
osHhiC/+dhmRu4vW9cJooWu7vqSlSxdJx4lXhiBaGlDtfnYmMwdfPJTKvSUufZBoEDG3lD1wxDLF
iqK2HRmb785j58O68vP5jfnZfBHu3BLjG7v+SzBYIRczTJzeCywoWVbV/jv5QsXH3I0TpNrV315l
edyYNhpVbO/UR4I3iGCC/b6z3j1yw6qUeVDhOy+FS4fKX59/Je7w6wknlqTwo5pEDCXpgIOcwWd3
+txatIi4o9wnIUNg0HYtPvcOuYoN/LITpemiKD7GTT/aTFoRPUMA7ZOHivxmJRhaJZdQAVAo3bPp
7s03aLmbRKQYEIE8D/TV4LYwFDwsxAajQjACc3wtUJJNcxe+Vu7lGUHEX5e7w6dnwv7q8X0Z/pa0
3qlvmscj5hW8qlPGgPDGAP5olBKZE+3K4MvrOSdjgWkGpT6ObvrnUPYb8AXs41fYjH6L/kHc5U+u
lXk0N13hmDjSbH6iJOf60Wyni6GPafqmNyXvslwWIzsWa4L0hiM6xJ5y7ifpIIaEIBrtKKDSVcH/
U+nIaYo/7UaGDhjzwpCZ01cKfpYxLwnj+TJ1tS/4IqVKGNuc+ppB8HIvopl95empTpkc33eWdUt3
0v2d/zabcIeV6kvewcAVHR4EdV6q3F0Q83JjxoGwFRGIVPJNj0A9tikE1Mh6v6mIHWSjKq08xVP8
fi6rQWAvjXaWOvaXFg9uEIYbf3YYQtOq+ZOpeDREkarB3o/vHZrrN4CZtdXHO+CE45NUG1G/PwfU
FMIkQgK+LDm1tqqiLAkJYwBh7YQ1Jj/ltfpGd3y7BM8mjMrszf3VRqA0sD27015PUCeToefvNbN+
76jRi+TLimxcbdpOcSgeFDubyskzUUF2kvUJSoii63hy2csmg6YdHYHT4adoEmVO2kCD2EA5UKbJ
aCt1hCu9J0ZDg9/0ZflCf2JVlHuwZupkaigXu7EfNp/fEzJMT34IiekmXAoHXjmjz1aS8BBah3YM
MjkyV4nImXTiBtrcR9qBicsZGKw8wfptoKMsq7S7LrO8LUcB75NOxpvjaMoTJR1/nTjfHRhVr82Y
fPaB1+g2iaVs7rVYhtqh+0+KTbbmwEMIKQST024/tXSJ0lcakELmsqHiQwtOoE2FGPVlYIYRdIK8
bKt4lKZTRTuQ+C9WlQbBHFLaFhck0p+NKH2FR7uxJsfckk1cxfPnPKh6iGs2nDrqgXY+hGNz8PeX
CeI5avmtDqb6GNXR/ec2aBXOQXu30zJH4YvZxXp1U0M3CycmhgrzlLVbFEOsLkHGlTztObPeym07
k85jh7W+RGmk7wvMTwfFAjixf6G9nhpQTNH94DW9nYqwoWVrMaRDjPz2hEqMTQmkoPy1pXNdZE72
uG8tIYWPlkgAKwv5+yQhDMfzk1tNjs3KMrgGhF7S+o28a5q94/AA65n8pnLpfYfPfteU/wvvRk29
h7kNRQmcn9qSUZ9dPEcw9pC8gbgXefdDMO47NDiRNvzsPyYuHE6Of7IZuyx/IRuS4wa4OeP1k96q
N7tonDzE4ol6OWOH+tPcAsuAiPJbfGbtFR5INfxnvPNgt6B2sh1KwpO+wzo696mUfHBtwrYN58+D
Y0WYgfUrRX5CWkA4FLWggahHhfWZ+skydc6REIH8ZrAue+Fhv9OhkrakDyTZ4F+Es/JncXU4aPJn
9R+Gm8zvUovH9uZ4kVYO2WYUg3m2VLITGME9AVZJ5T2kOqMlo1dRnp30ZvOVcaGyoTQUmfpx2uMj
M7ljk+jD37gogE6q97xsqQxhL/bPLTWHiiUzMIZAQ7MhOpgwbFTNJjRQRa971j1kI1Kl84+oYtUC
8as/Gf0sOz18dQEYUwW6FX+U+tZAbrHGV78ZbcFQ2Fxc6KWESuYXyn9EikyNfLer1yX7gaWUg8la
3uqEgRjIHRDSI0klnFtirAM9taGL3XoJF8r+RkZXHPDNQf/ne1VLxCUya0a/WmCa7sKURPuIp8TY
w2AeJ5n+3UR2U53/gaATvzucm1IbtewwtwQzk7+abyg/VHEV71dfvkGwuHLWIlJgqEk1wSat/rqv
OjtagSsyeDR54fjlP8KaQVApBJS8sKsEe5CuHvGP8PIOWYlq9EdLvUO2ezBLt99rAgGwcJPQjsZO
nv/aQO/SUpEhqu8jLgSMMi7wMM7lVOzlIf1O5rSuPNTLVM4Rp3lKO/MX/9Au984n7cMYiLDgQvm/
JXMu8qYLvk8wdvbIbZ3bP00F34gq2qINSsEHVfdIMcJMfV9Mmr8z2YOYhNnTWhbopCGhHX8agN/1
qCpdnS4fLgLsr3mFSR6xYg+aFzbs+XYK3n+FrJ+YBxYW5AXMRUd80bkWvCAoExk5vJHuKstToSi/
Md3HcaFj7WPmgHrGyX8TilPYJMqNYISRM4kKuqtPBJLgOHW00bcJcxTaDUiF97x2bQPAL8GEswMR
TzyDJOBL0AauUUyaoupgTUf8m8DZqvSX5VhRgApl69yJS55/DwG3j3eIOhbCvYPUxVvtqJBkXqmd
mDJYlJs53hAQFmxje9OAvTqY/mpzy96WKaRXaOJDYDKGtPNmVg6I8QVCfcc1pDiGywBdsPGMkNlg
aXLSM7GRCyN557xfJC3BcU/rOi3TQTmoR0zbNy0xEAtIWLew6xkBK0qifRXJTzckMECdBlYOBhBy
OxfVva+u3bxqbzXWzGQaMfmrnLIyBoLW0brEZkv1OH2feEXsCXQT4g1NGntJ9Jo38QAiFOx5w52Y
8wyTkzml3xV1wnn/QMGynIetIC8wLo596HH4u97NkgHz74+tjMJabWWJElnRw95qKUbcajKoPlTV
7wYnUz1tIEZdMG+Rof9ynlvRvi2GlluLs/YLe4g+hEp1ghcxAx5HuP5O2r/xgijg8lfS5IjQ7RKg
rUIWyogB9cDilWXwO60ULYygtHoTlPE6V9CgWnryXBlac8kU89XbcplTVq5TBAJFs6oAk0ycK0NC
tI7gvhx2wnIEyfFTpJo/8SEBIWwYik6bf87ESWPopiAjN1PvUQoxu5PBjCn2hBW+WdSTqe8iMOR/
okzqqbiQk0TIAcdOxCLpMRX3KRrt4v8+TCgU7xXUQWbxR0OJJcY6k7TYjauxRuKyh3XXWI0+Eu1U
fIaS8iXGSCLzaIVSrXwJxwm3fQnWfFBwNA4Vs94l04wmnpRKGWR1iCUTQR9UwMuL9ck9oxCthStj
mUvTgXnpx/A8220C1/TqSIQh5U1u8mCO4HpprhoSaUUAN7QCh267a+rgpPcSVZq5hfFAkV7nMOg4
8fnuQIXuWMSveRV7irzvnirvHKxT9NboeceNdnUFkzqMI0agGyK22LFg9UiFK6FKUTtT87JxU+WI
ZispkLQp0Dz6GYVVOb/phXWewJiN1jCT4MkiZdc+hINtmju9XAT2BPoDLUrNSglv5ypr+qPh72Rp
RcFlgCWFBhU6ByD9FGh5gcF70E8jgI4ZjiXw83EU/mIjRH6KamMJTh0T8dLwwsJgARFd87Ugo/wG
z9ubFN521FQbM7S/HsL0NJD9Z3LFGHKSzs09Ed0QTms6NxoZtVzet4Oo9ioj17yii5SM3WcJtCGu
bzyCE6TMIyUG/Xn5nlpbavkoCUrWisqoc+JxoAu+70efYHpAqO+RLqWguHUbjtZF23PFO6iJfIh1
lsuFnAA+BYMrCfw/j/VpE8Pjm+wudvLtpr2+7xS8F69VdxJefNNnYxEHfWZ/lJDWzzYkSpHice/C
AlfUYDRRFxtFD3LSM7HiVg/mj8p6nrxJuoXR7aQyod8JP2H2nE+NIQRVZ4R5K7XTtkWgReOALS0F
7RndZaEG4U8H9GzvQPP6BRRSwg59hWrr76fEvrKRJBwu85KYscmf0s7ilPeLT9yYvJiMBCPVRQLV
CUSb84+62aMcXNooJaLw9z9Fgep+dULiNeKcAUr/Hqt90nlyfsUl7MEchHzgvV8Oe2LuLaa4XQvv
2cTipokDJIXUL3+V/5xbasWupTBs7XCRxyQCGOVpNHtdqBYlBQwl/6Y3lgGMyv4fhYfzFg4r05K4
S+RFn+G3YOyRkgEsHChC1luW0eH+RXPqOFSB0XDxsYvwzqRuRhlXQEXkskiOik3wFefPB6RleOXo
BObGcD73eXuJVd4xZcRnxOJbN0l6AYz6J1+eSq6WCLRCa/QnaGfOwUco14EZt6yQAPe/byAtJpMv
iXqq1Cj7kYWMykk3x9P82PdHvqq7+4vNZdu28XTN73HjRz9zFsgH4E1mtN35uIpyiDWbkkrgfozk
txugSgDKU2BzcPCjKg3hq8DQlMU2epKN8w3kNnL8TgJNPg32FB6uHuv9FrT//kbphHL6bhP8eVob
XMj38TyWwCi2KBUKe+kFdrpfKVnn8iqAo2rqp5Hjg0Sbrls+zfEBQxUNCKSfYwHmvvH13zs7W0XS
7i5b3H8YbAVMUVJAOxs/C0ug4CJzIX+Aga8TAJ4Wxjy/pH4VZT4iZSkulfUydJwHgcWHLBC/fNAy
/soOGEBmqNhWL/56GMxXzHSWuGCOz1y1D6T0AN7l7j6cuho9Dkm6iF6u4LuKAK0Z8XFpsBDVzc2t
nhVCjYdV3qO9998bXBSsnO0ugaFoEKNDqqrvMd6lD1xxqP6qQg+ESKoumvZKTb3WXGsv/9kaTaGb
XwDhUDn8JTie15sdukwiY4aABgvapq/vbYAvup9+VY4Ub3sQ/vWtlhHC/PasiDZxtaR6YUUS+pUU
zOeR4pC0l5yfq3M67+r8C8Vm6Hcw1BRgct3ud5WftEcT/RJsy5aSPhrQfmqS7c5/0dqMHF7qZJTf
ksJP/vdZIu1Q08AW/tGBDBEgupC1cjUy8wCxfZHCYjh4D4dlbp9dYRsNlLgQdRbsmjNuxf9fO/AF
JyEKHUGym+91gyS3ALtTGB8d/3YMoAhr8PbjTqWsI0OZrKyG09D5lbOLWrOj26XeyWieImDktu6m
SMnmd40dW9V1IiBLcey25O09AATtpaivkAIzbbMGsLthtAynhJVWsvKOYW4pENUdE6sfXQPG0wzj
1sV736oEwebsUzYq9WfoeHbPb8DbNbYGfR4JF84Z87M/eQ4T2+3Y7TVkk2XvM2unrDrmUHQAknmZ
kyLr24E8hTnlo/5SJCjCizBql1N46U+yCSMqkT9tM9yL8Qp7OzFHZkW5vp26NXPp8r0dYTv7Ps/7
wJcj4cdd3xxpQHfdgpW9GjQtoQJnXvy1stsc0s/6BnDkYJUsliRpjVnjw83VHdYtevmY6DNBlmMI
QcqErRnxrD9Jik+a9NZp/Vqymg4TpIaa4GXCUITqxujmHVOPoCupw/wsBgDKrt5JKqg6QKXOYzmi
j8jf7AqJ8glu5ujmoCMx2+r91vSCMsBLFAY1rKgDbizA0lRzwY0daQ5au3unfxhZ2JMF2zzk5ryl
bvGbH0xK5Xsh1qopZgJv0ReUGntnezlgG3k2dQq2OpjaDVA7yl4yVWtT0MnGMmHw2hxTY4q9ROWb
qtaJh0rh9sPk2wCpvtKlCTfR+Qhz6tdwtYQYuQMpbnGClVWbOcWxFC7M/KZBSw43Ny90EHwZCINz
bjR2G1mvb2HQ5Nhx5TQYPyk8oMzX1yLgcEI1BdcvXnRi4taH9xzyacZet4QMXr362/iDZ2eTgQMd
uey5T5qxs33kvijOyi17yUmhJP4rKL11FIxGBdqstUBS+2U2/JHfXF+ckXyhw4BzbZm6MvRz8q6a
h5DregfQItYhH+YeN/NssgXsWp+c06uNBJrGGglX5kvwSrxV8/TAoG0YKA41QvPe2vqmoKizoP2a
KykGle+CwIfvqYsm8dt37QPMfU3TfuevkFBIpX01h3Ev9OBvcAx632htpRYy2hMnplxgLXFKb4GS
sxl6HG+R6yXTcLoaFwIcSSet93XbNxD+jHks/dypTHrholgII2RYDl+BHY5aO3EqejDxcEazxXWm
dY+fxCsWmocljhUE/81OyMf2mzRTrqrm2Pjq2RBtJ9UX/SbwPMNV2PV8v8ErR6ZyShm1zStBXffv
ZCgLmjiYyg5ngzluvVxUwKiifA1MryWwPcBYM+tKwCYdoj8bFAz6mzsZ5m/dtG7BFRaUXuDUMdfR
ccultWjqBA4tTVHOZ34lpxtZsVBxNU4EnrbnltA5ozQso4+w/e92ih9VsCUt/fqEi3rfUQ++xO9g
bmcBFK1S3ps1TLXExVLrLvNIz2RCxYcRmPQoM0I+TLyiEJc1fDzQo9/Ea9b7ZUuLGgsyRVJ77pJl
LgBZvZExQrjrBrtn3DJkXqP/ZkRKdmXCeqKU9XWFw3aziOsAMrqKthcBrEIDLCqYvakkq8ytbMDW
g/E2ZeRVrV8UouyDHByxs4lTJ/qaAp+5fzorOabCPULXYcs1t8ftc0fDfnNQYWUmAe9JrSQKxWIt
CefyD4R6gmHunM2hsxm7M1ybhF0qXWSmJF5Q2bISDoKvvKMB/g9bT5t2kHRim3JmifBHypxA3dsj
4fLyh/fLrQ7Tgl0tAQAdN7lPNFo344TyA44qc27gl7c19pzL5iOboWt9OEvlGhUxrO74UwEWdhG2
10CJg4BZ6rHkck+ATng9L+uHK8OxvnxcdBaHu5dWE558ybUg4R8vOAYYoqeFmxXekK+fnKCucUCm
VhJdngaKhv83CSGtW75O816xIRD2eOi5+bNjzfOG6zaCRfRiqwco2eZb1rnQdZwm5DBC363evc1Z
l9PHZKqJ4IOJpzHahaPBOONhi900U5WjPDtH4SSUdp9nQhsTgWWICsRZaLxyOTiRAk+aSac9x2vT
Svx7LmsShqwdmBPbCmBxsGASspXm6mR4H54viUXYVqtg2RQAqrldxp9Th1F26c4aGElHUMepztp5
u6RhMH/l1WKrCexSO8lbcXRXTmn6OcYCW/ID7NeK7CcfIGcHbFSc/aWGi0rIrfdHXYZ9YKd0PlTO
O3PPVSRZkwMp9dhROCvlkzzlwm9+l7Obf5AosH+o0gUGKiuSquOCHDinT8zhF3HPYx0ORyE/khMB
5zcAxvQPo1/g0cYq+vMXv/P2IlqCRY+wuilr+nAkOCeMLafwWYzSUgFXEp5qNQSaLoYdQCNNfw91
Z4ZjtvbXDO7t7q47kgYj7MTcttjJt4ikNBN0mYdoAJszM7Df0CN65rhdflAP6FjP03ADAwN+iVSM
f/zE4t6uALIcpLfxTEtj5J/raifrOiCadoeh5xkqZpbJHNjBhcWw3ZUCNd680lSEUdMb5EaKOSvY
dWvsvHkCcp1WwjW16mNtBZTG3EwDlz5d2lK/gfH+D83kCMm8DsQzPgFJJJMCgjWd+y60sSL3RP4x
OilQvhEhElWtohAoxA/a34JBN3xaXYC1c6C7MBLTr4EO7lVN/jO150nx0ueHGGSP4C3M1cQSax/b
jZbh589Br1C+lsTx03g+kYRR+PDz0buPgVkbcFHQ+QkYCXD0cej47iXqlKe2a7lqHuBg839O+CGk
sOiDMjx7QhwxkRKAhDVnda9eSGzsfdr+lMjodg3fo1X/FS40vCJfL7urvk/dLvU14LxxAXpfBDll
NDkCXmuZx+k0GcbRx0cDjgrqN1T2CCl2FHpFKXyfqmjWfG3EhWk/YebR6lQEzYJw1Jq2/0vvmW51
7G4BHl3XmnH5uqwd7Y0ZLg0mb2i/k84pLElm+9t/Y0o432xTA+/2crvh9xqdoZIkPOLZWGPtRD05
oeyB5bItLlARBJ377AGUM9dEpuWv8S/24GF+/3Ca+/vmAVQ8KYuRCqXCZisSzxBsNz+oAF4tUQ3L
+CTiG+IjmTegYyDl3jACi3qupDHJMZ9PR7iVvWwJOLuVNPPUB/Ph2mgrm2wVanti6hnmj0vBsvUD
4Nmp17oY0QRYFKGw81kTx1Pp4soZ17OKrGkX52nOGseMvX8sw2tLW3UA9wcmyssoBuRVXhS5hzgy
677URSTOLAJFADa7TwKzEKR2mfQQ/IsNO5koMOVnOceDc1XJ0X+II0idNfNzUL80kt7AGT+d6wtA
MIoNolvGsrSnDbi4vn+XpphBU8s2f6TBbib6MeiSZI5D6oXJaqmKqs3CACzWzo/0ouBIFECMhlH2
E3m/KnNcYtH54yljOWDCHV7JMcrPGORAmLAaqensfaPo30Df0NAUFkxMNKo3m2PcVinRKfNvJN6u
p98vF1sjUEIr8lzNh8lCRZf8Jp1H/yMgoFGZaZV9XWb8lthUSgc2OlBpvv7ThEioS+XZ7Ex097Dd
t1yrvLo55EsPEOLsF+E9ncm5ikf5u5beSsLnZilirR/SgjV821K2kntvw9CLGm/Qv0WbBmHDv+/q
ErJ5YAwH+7+rXS4SV6TPzo24ciRg54Q6HYH2DT3NsBRdry/G6ypXRhZpVW3h2zgXIHvYROkRGsd8
DVckUkhAQBxdiJvC190HgDi2AynsChqpXwsn50R6Ew8qsw4Id43q8dzigkOBnqhdHPeGCmVdK/ao
z9NwQ1kBCyB9tSzNOGbI9MobWEpjMJt1Y5cmM2X7Xc0eR4HD5Z0rGmUEPgT8Icw8p7sIfQbVxfNT
SnmB4cLgg2qeX5MjyNgxjlb/lE56u8te5hWJd5f4rqN8VVkIXdVGpG3UoF1eJGtYekzzwXOqOwql
lvnJZUiSJPMAPzn9gI3dEQMdbFlJRmA1FSq9JLDUoztbAveQ3E4AIgm9kKfuN1gIfRIl//KMUpfq
vJbzC9M/fk53K05mw0rn/3XyPcT/ZZxmZnxUnrr11jGHqcCz3qBddfPx52EwCvT7feD/PSwnx36Z
otGwmENep/qOpRHYkHKtFlP2s3LMVuKcGyrtanhwHX+932x8YHo7nHIEcQwUs3RT2n0pwIGiH/YV
jb6+BLBhLGMXBFrplbum9EpchwvzEiM84PODD6Bkmbnr/8FaHoHYOPjxJdio675324BUUF9rxaeN
mDoMJwD9hE4YG0mkHf5H0ufNseytQZ9dgafmNHXHfFK+zlkTeaW3M+bsRIeElq+dX985lp3nlaVM
XXsf2uUDho4sFSnDcw1rl8a96tjpn86a3OWb2UYDoDiRsG185SQiPxDRvfA+eySGfGKKSIAvWSN1
JIbP6KXXS02+c8KsUNZ92mi/4+Ntil2zAptYkg+tNY4sUclEiSI4Wka9yyn5jKkdATzgsvlaFAGx
t0HhT5loD3g82dm7cwFKLKsMZ2EV52zanpWIIJc1kLcOrOrZk9pDvW+LluV8URzdUkiUARwqd6wa
pCpybs5eYMjsr2a3UxRR66nVh4R8oLECw0rp3dsi2749aUq7EWZlcyDFkpzbrUzh78BBqMFJ4wPh
yHmtBJyv8J08YoQlJcYaIzjxq/u1mBpQ6geCqHwQAIqjPl5knCCvbsgpIm9RXnoLrjnUtq0NAjVj
7FpKo6qGMSZ7BacmKNV0OqCaeHK5j4lmnrK6TMrftrNJptZMu0N+pLGllRSIUAsEf7w43f2l/hgi
48Hs2uclhuWXzwWEOeslhk+juMuKTQ//mmZNh4PiGzXSfbnn9hQwxX48vFyrOYlvfmtYgPi617wQ
lK3zxBpXrlKJbHG2vhgzU4yvYw/zAAtqbE6k3YYyiBb1a4ryJRvh7do0lFH1S4Trv4w7EVR5Krze
at320xIkc7CaWT/W7B9ogVZhaypF5EDEJwYgApKk4fNLeWB3Ss8rZMdSzum/5A7EjlH87Hj5qSNT
egKLhN5D1HNdJ+HbH/iuzsyuBp7xYdl80OYesFdoZs32+6PqqcDP6d7X4/dmtTpq1mG2wEjfKPC6
LHKNwhBNT9N85cvkpbPxKDcHZfliAzfQVEesybv7jhYBcTxaacgt2yolPpafULpo9ej74yLppX5/
j8intQG351/EwzHe4dD3TDEluRy0+4scFDwruZUz7+Z1fa0Q3JJlV8VQB6QHU7thND+A7XpPVsMZ
JJjCk+gC1wC7qMV7lzXrSQzA3Jqh2+u9dYGJ4wDAuyH8Uhh8S+wvJ1B8OxWJ7BGS7lDMtI8e7hJl
VtY8qqvtPsiU2MRuZEfnTVzIYacGlVyrmTAVuAO349iSXgn7Bx2YHvfrj3D12gcVRoN3n0NNrgq9
0IyK84Hc8kL2Zag8OVuO41CQWGThza6rmTaQNWMTQYE91EMUQ9yJNYszMTI0B1Vk0TIjsyxN2Ygt
eFX4kBXhpZbM5EbTfyi+NGTD1f3tSB9FyrGj16dFO7bGbSRWUr2RH5AxqqgFkq/MIc56CoDnvB8d
Xga2Lz+oyWTxxlRZcfsJ5etwx3Vbwsz+/aAJS5yP4zvfQ9quHYRZY0w60jvRIzabUT9C+AzMJG9P
++OOfhrvSP7BEPHq5sI408Jj+fuVvk1tAGd0jTg/jtyRfIHIPBnaVXbxHtaIV32TPvS1HqgFSJ8d
uyCUp0Bc03sCqhnod6usLois+2aUPiUhWi/uIp/cGHPfLE/jB52j75C7GTRz5UPCAAQSWUVRgdx2
+SungrQayDNqbkoSI5tisMViECSEZx7RjFS5WIRIbaKDmUbU3BDnfE6S1Hi0ecrneLnpc0Lpl2Qo
5pJAhz/XAKo/xD2Hy3KT1RH3izpFjF/WFSf3JzPXjUcVoSJBRa1q+tpMbvJGbpm7wcy7JDXaCyzd
6R1TWrzgV/RQ49lqqXVgiEHbek7Crwu2lFF9L+JjULDsvoPOCVlXmjp2vksAJ1QYTjckwRG11ZZP
sQxP0Uzc9h9FSA+BsmAqq3HARTXiBQ22k3pQsE8L+8kEqxgB/xQYSrqWtPQJyYWPtOtejm7l3xy8
Px93VR2sFPyiRvod9zBOkTwgcOiY0zRuLl6EVSJVQll3qhiqn8ZScgCEBevMOaVUkJHR+9kZvxdz
zPR9FHBv1bkatfQGvYolK1DF9OvJnYfuppqlL826JimP/X0wIArrgcOuHF5qZwJ+9XBQULmaCHp0
gU8mUEkZtdTJT3PBu6Wb8jzGez0BspASdNIfzu6RFLsuSgTqB+kQkh6woauWAdTOieMOV61kD1D6
2B9A8qpKnryAKY0GsMg88VwGZQkXwoz8JUe0bAx7DjgC3N+bu5C3WdjksAE+k+Ip4LoiLHM73eF2
DzXTs9Vy0sRbwSIrNcbaN7IavDW66QlI0zPdfefwvKMS6PEa514rE4pB/uQAQXLcrSGbtvUdzoSI
CYgv0BCw7jzYHEJfrfYX6y4AOpgXugUbyQ2KnMjPqz0MnFkLAwwDtwDEPu0gUjeM+hT3uRxEcNk2
SzgTZTN6YUyq0Q2gw5X4Vw7SawXA8fppUZ7Xdb4cfPUXYXQp+3pFJorBkFH8Iqxe8rXXjRq6fMUA
Bh+Mymj12/Heq47LtZWooOHAkCyxsekzKrzfPUCyqCXCxp2aqE/Ap6Z/Y2uWfiSY0fnqS4cwM2AK
Q2pPb/o4ngudQuzlWI+mchKBt9DBJ8msWIhZx+QZyTsKxhUroLwtKtSjKWhLrDes5Z/7mccLa+Bf
YpTjuG2ZnPmM8zXIkP3wek/lmwN3oBwvgS3qUOs6fkVkAps6lZW7ydz5W4hrA5lpxEZA2PGWsyoB
iJiPpwerj8gHhkg4/OBmnuRBA63yCy/fNFITnrqeW87XmwGxskGN4omsuQtFUorLkT3XKuHdlCV0
ZAdbysfTBFu+74175I+MyJUhspLbSm8KUsjg9KOrqteAwytbH6t8gwpSFWrsxJePTopn1QlNm672
CJv1Jfcyb5JvlJtUFyc8L5YQ6QEHPjahC0GonQO2hqNg7rBw1eR6KYUEi+QSCoNpyeTWtphNUFHD
mq23CF+lUKNwoeOloEV3SlVr+5ES5Y9KjYkQkYAnHMNy4W7DGv1wNzGIuFELExZfnSRGD9NDcoeE
1ZxRPeV3USdzomq+XoZrJHxYDaeYh6OaOzIkgWjU+bkth5PrAKVDLk+H7QYwLPBqyrDwtHzOjR8b
83Jbv5Jo3YGUXem2+YHfVB9EFWLgsLwUZaXq080DYBpYwYb94M5UbHkSrX/UH2ZtEM+gl5Ikae9T
/LPa9uLwMeaue3lMvE0qWXsoWdVGD7Yg7rOMYu/C3pcRSIyspaazzz+VuJcEMesMjtP7zCdc9C19
CWVr5L7hWH1OYbv51cq3lVrajehDlf6xOUVI159K7q2iCEBgsM4LV/dU9uEVsXSiW25xVyELU940
wZnRvs0gYS7W5z+Ye/08iCvpNk58kvF4BQhhse4xdFzyvagGHlhg8c7vaDY8sVUBPYZe7YVNelnn
v6wWuW+l+wq/D/acy58miqOA8w/NPnXoqmDYmxyuSuG2L0l73l80tLila+UIuZ7u5eMD+uKoAwvM
pDXA7cTchl4FwBFmnKUXfcDV+GJvE+xov7/sIkRwZsHKljXJVcHYRQppOT1PNlO1UujP75PhsWFy
IHPbDBSGTqzABnJO0j3zNzVny5KauUcjiuSHj+MQOJR1yyle9OakGgsRMIet2RI1KK8Aflvy2zO1
cL7OiR9BxuM6EMEc9O+EF444LjjSR2tP3ryPbKRkI4+1tThxGIfIz7EofK0+M7FjPSyMrYE657hD
vbaeCfWAsbn3pqO/epBUJd6Sf5mSFtaaC02C063UAEb86Kf5IvenfzbmYRyyMUPTcWYlfA/Dr4tm
M9aY0/mstlkykbxmQGsp7PE/8whG9V0NGGflgKJWQi/kojs5qcZ8pXYV0jmJAb9UNKMIyY4ijqp0
wQoC5l2zOYHuzdiuhWYx3bX9oGnLSi9GNGH0Mhldu2dlI2H2oYrQqDTmjLdMgTjo68FcQDEkkjuj
f5CrZ9v6cjIxtc1HVOYa1NAyKapteXsBeFyyHsUGQNbxhu2+qkEiWdddIK3M+J2h+nuNmxYkL7Qs
OqWnsvR7adCT9NBXs6TJrqGLizxE8SOpXgIFeth2G6V5BUYTKHLyMo5ZxPSmbnW9H+GXtNHZFaGZ
UJMQdpxUK+EAlSHp2zXS2LaPCBj86hmuTGpyZVZOSR7T21V8lz+cTUA6/YffwZI68Eorz/QgaV+G
jfeEhzNkS8eoAv3W0kZ+AWvB8rhEBZtJWWF23lNNUmG07Y06t0rbNBtQx+fOvVI4q29fYwWL1e/d
3UXDoJ8k1uxRS0k9X23iZRQaCwU+M+qhyrki/Li6fXHEN3642wJJguF8ScQ9/vRf0uRCEtujV1NM
0539xBE1MSjlddNUd79DB/ViXrGNxIhBnF08KWO0K6T4y6DEuQdap+ByIRGsXd621+ZaNZN+1HTn
ApitWK+e4L67Rno8LckpKRskqNCNU3kDuaGtz91CUJQaB2+wIzRaeFLNq5MjiYLAV3JiuMtuY7PF
DKHWNParPF+aVS0hd3afd55r5QB496ti0Dgga+gCoH1Ik+MOtYY4IhgHJMC/d2zpauuW5PgKY+95
cVZTEGsnIj5VBuRpwNrfAp1KqT953BhWwFqoZHgidc3mOahyG7iHfE3YPWh9x5tv+oH1yt9emuKy
dBx0WkSpjP5anKd7w7fPzLNBecCI+Uhnx80yb+1rkAR5imoiSgv9jXP3FcV+12v611JpeSUbnynI
A33kLrx0fdxEvn+qvhdIFhN6ioYDl6Rfan8B6Pqba6MUd119FeG8OPdFeRm/zlyWDWAnkt4ZipYB
FUusp5deaifNAprfB+zI580L+s8UNQmeutRFXZV1ymiAaaEr1VA5/qftDQxwvCn6FfPZmTe5YaZD
r6EaT+1RO8wJVyvgYm6+qBAs8jc9YToQDyUCJvL7hTCNz44Tfl6Kxjt8Yl3TwT9W/SFd2WGT0Vzh
UL7a4zTDrEywaGIrR+qboyWD+Kl5e6v6WK1HCmYNf0I/sdPX/x72UWpEMY6eXTjgpsBw63El3Vvx
cjvlSvygqnQZ7TLq4tq/SatyDtdaYflbZImtdVssQ2R8JDtuXBT/FWqsjyoCRVjrLSRAgp33gmu9
poBtjyhoTFoLSpSCpfXp4mwImjp0qNP7wDJ3wRtRp8AP9HFoncrxNsIJiDThp7MtRHv7kmHEizQE
fmNO8ZhI5aZogu4rw5KBPpnbSsD0Qv6VV2AhMz3o9OEi8WAUTIgyPIbehDzYqy0uad9z1fTgmwQk
ro4PmMGiZ8mlPhJYr6xYXx/nCjnEt4PbG1DBu52Xl6em+vbJvra9UTuxWKDCuqcKG4uaZ45ujKrF
Dds0ywbDt5Jq8jIicXBdPzawZXAZbl7bqzUVdOIJJkOaS6B9iNTcfPo1yG26v+rkwNz4bKy1OvCf
GKUhgx4lsmWY9k7C3rLfConQ8R9fvA7DIFBJX0tRlI515lf5pGiSvzXc6csVHykaJdHSjIlTA5kI
pfSvbVj4ZVc+1UK1vb9oSX3uxnpKWUnBl4ngOtDgihfj8Dy9HRyDXGK5idMrGHbXQHdHwV3+m86B
SLMN+kBJ03G2QsrUnObOu1W8rDT7V6vB2y31Kh6CjTyXEVQ3xUs6Zhdkw5UH+HjDYpvpV+Lucjp5
ruPdNubtrBzz7EVvru9STIAmdwdD6Ld6u23pP9pQNDYOC04cQw9hvL3Nw9K6gVKBipm1vYkTv+PX
kHRXT6znFvSL84M8swpy9SAnZEHtOOydwg+xcqNCkX/8NWvPAR5zIi0BNBcShBHLXb5ABnxWCDl4
HBsZNLoPnHYdKsimWvQMeStbHK9VJI2h8UWkyXbw0uuHY2DDeVDVTl/nCg/1CDdYLkbVS/i2hGCM
PkMsg6w8h4LNOJMvjRlHGuKDdjgh+z2xthxQ+i0fdrhKRw72yGunKwzmHEkueix1Xgq87twgqtNx
SarGrf+2phwOg0ua/2KCzGBLIDnGWtFldZd29iz4XRqMMJNulnVoyXXaHFL/riozkbugJhbM/tv4
R8yByolSSaOFouhQ0T2i/BVO+w00s9yflgG8BMqjbYFZ7vAnLrzRr2w6i7aI9ygQsQAtOPWwj2ch
bkssYPKArZX3sTaHhVGktRdEUJAHIPgUC16dTLgvad5AJQmp+J/YlCJilSeusl+J4U666Gumxwx0
GBjQvRbWx23T2ZUwEWxKExEI6yWADBA2f+UpBPpcczDUJYl4HXXdVp+ZiJYVKPmHosnq6gnVyBNw
mxAVg14V8wphpRZulQkJxUnEC/AMDjZax4/i/pVCLQwZqu9GCdTXBdDFsFZHpC5d/TbTa2YfOGMS
VyAXQfmhCAdKyWDsTRIMsZIiTCazDTaAntFVnrOY8IDdRX66niCmbsN7NOVgV27Zby1BuX1kPfow
u1hK/ZfarRNXYGPQx7CFw1VlBdzgjNIHFTkL7GjUMwsaQbbpMOsceRlHB6foM6BAmGFzhmOWZidZ
rKD/IzcORz1xidCrZBrXuXI9nzq5/94KtpaDvsVA5ZOBBFnEaN7VGCNIiq5N2qgs7OKE+UzlikID
bz7DxoXIUXxK7/ttNawAZ+wtZaoeLJEtx+HiiCA1FeZb0DQt2o3Jo1fG5KbmhkO7HJG5PElp4ljG
Fu3iUlWnPU+BgM8GVVLYg2wX+3mP0iktCc4kT+5k4DhAACs0YF4YjMnhypCuwLmAi6Wxxjv2uN5D
vPZvSOJGdMma+MFbck2nC/zsRAk9lITbLTWmowXKQepRh06HHuF9vaAkr2L2hroTQdrxynVpkCDB
RPgLpzCV+I+UDQd4wXf77Q+l2TTUhun5XreKX5z/ScXLe4nxC389wESo6SYH4URcXF9EG+fgV3i9
R5KN/wSTes5idKmvC0umbySEsDKffykZEDqbUZYsnz/3tm86tshvNXaJlRuVs2JoibnYGmor+Mg2
SKBGxOr4j/A/nYJytEv6FydAJqr1ZfGduulfse3sEEF/PfVsrQNU4aXPkVNJoFbiYwyxw/FixhwD
7E/M7DOttMUVC6aYFhkBm4Dd+q4CREXnj845zevXkxdjOPiALoD2KaE3YGSavDb1epg/A1TcndPs
GmtNwzE6RIpdysT6TAVtrGAnEJaDJstQWKzROFpmY7E3w7X4fw7mixFStYe5Vr5MGrFcYBaQnm5B
5ThiIfJ6jedXrcxHPyMl1K/LoY7cVK3PKCHyYIGKx/8w8AY880vTj11BB2H3ve0epmPPlcM+a2qe
ybdI3ZSZpVv7zgrHav05vwi8ats35a6GZvt3t021GHuiilgWj7CHH1nRB5EuMdbjbOWL0PbLyq7b
FcFSo7XcHFnV5s1dwv6Ci41cvltl2Dwu/OYCZRDbdXn0CXvEUetqZnEE5feJzzSUYObHq4ZgDsP2
sgq7BNHmzgtmw2AGegoj7/ewgnRIJim9JZbikSRVipKsT0XKZ5RYiVZdfZDF1N51oZ/mOGXTG7Ui
L6LEiN0BU55JjDu9o4l93UUhLV39uRMOOTZr4WfmuLfh1S21b0N6jCW5J1+hX3eiF0BHSlvgPZP2
dyqGu8L5FT31WWuiBLsx5HWjU1WpWVZMgngQZVnSWqN3A9BCX1az6I2HWq93kFo+Ke5b5y1sXp4q
/E/dyLY/8pSRt5Tdwvt5QDdTfieEBYfnD3eMXdKUmmRKfKLRoIzkcZlixD+p15ERK0IejEOYcId5
Uf1UwPmzEjdS1DhkLgOUuAuPOPe5pyR53ENUtue25XmJlWm2DdLMGeDDh7+KIvfiDJjmqg9GJg1M
X+7hcfU3LeD+QMxOufa1Fmv5u2IhGrZIhChRG6ec808Xo3QbBUBQE5pRkHOl/yiNgUXdplp4fq30
usFrM81rnPjSe0crhI+cP748bQK0ovrDvYwvFwKycATQ4zq2ac5aET/Bc43RHXAVYK6D4WSZB8OM
BNrp1mBO2ptIayE+aTGiF3FkypsH70eyvOVNk+LMKbhXE51NVWq67lJ49GZZhgrZmx5t/zQwvcoT
c4pR8EM8FM2wmlyOarhr9emJ2Yp3DThJKIPWtLu/V8zqUtklHI/8fGSx9R26521zubVWNfZw5CMp
QSbu5kLfDCvfYT4HNl5wR0oOs72Pibuee4id2mYkOwj+RxFEHmL7chgU4xXAKPf1FoQ70oQ3d73f
a7FyFnpFCt5C9ubxzEIYYsEj5FkrOarvDDvU4y0PiocYXLO4mVntVkNh118QCIHw/IBysavYT0So
QIapC6tnLdlwfke/8IGWva4SWQ5v98sZ+t+/RbsFVRW6CbAYnrbCXWi0L6b7ygXto0IsVF6YLdrj
Afoq/bir8sVpD+ou7gqgg/lTMg9bzt6/IeMo+t1dRio4lmTBCtFYzG74FDhmB83rjVaZb7b4X6yv
COCvqev09ioPXcn3rMuCvd2Wa/648Nx6DhhT93C4jzd2IYhjGW7LSYNmfzqZoHTh0iHZNcbETs/o
L8MKzAnSm+PVQxEidUbcU06CHanxAWVYUq0ucIQ3Fdqig+OdkWYuIPADzq488adX77akTxj2+pym
s58XHet1gDEVh6/8l/E8JKtlfu0wo9tvJHiGE1GsqyFQejOOVNzgzYhsxwqaokv5h5ljasgcw1ta
BvkXTpsVNPOM+g3IvXvLLcBfG5OPqsoxld78cd3+8LVnOGGIoKiqGhRFDA4VZKkvBm+0ihN0A/9f
z0WjjaNAY72yc9hlUb916mz6nxYH2gfc+72vjDrx3qIj0srgZlp2wEzcFUiMolXNPlFd87RyAizx
7xw37bOzDB8Es8erH+IGwOLYox3uj7NvW5G0X5vhg//9HRdc9bKTSs6b/4FRakCrg93fQ2AX/5XH
lNwNZYgo8d9KPEYETJhb9ywg85afBbTjVPDtquGjc6XWqH6z3qcM82b0j41a8DEt7Pl399ykalls
8LEbyD7MOe5S5PTnOfarkx9teaN3Oy3M6H+db5bUWge6H7UrGDj3meIfm7x/lV1t3alJwMpdakEN
u/eZiJNBVPvP7KWEH7zZsSCqvprngYFMW8y0Wd/TPBXQqJ5m3+MigeYaoXWAX9sSnVMddcWuGoLQ
jpP08KbgivYrWKY7lP3sWnhuB2DbKo9UvZzh13sej4cmBPM/XShUuW0rHu/+ExQI/yoqYh+jMx/1
YLlco9RHY07lT6Dz2FnV63AmKgBDBAPsJwHJYnie5TvZBgxos79j3cknyAJKNKwQZXpEMcbsw8np
R8mrTwwkp15SFC9pOZ/u0WRaUx2jFR/Yyv1jtjDCvq9f/tr8uXv/aoT8DK4bJVYPAX0T1PKdsMOy
vR8Dbd/C5rizhO6Pp32k2zicytXe3CexuvQ1GB1UrL9FU6dDl+/Wxmxj8s+Zl6nGBd3CnocGYqok
v5GoS3BqBcSSedqrn2B3o9lz4eovZMLwZM00qUjMrHfi+tOcNZG71B5Il/zTnAhizDFfelhw/4pA
l0qGeXgfRAR7G1gS3fv5+2l6hm01w7Vt3ZnZUj4+b5eD2wYHYC2QZtoA4RtxJskYxovx5s6OKLHA
WBp2/tvH8GhospueLHNy8aIa91gfVxXfdcHRzLGpVjQbiY6uop0+IHCnEEeSttLdcLoyuLKDlvuw
U77eZS9oh9RIK1iCy99Gp77jV/aYZFVlWDnJYBzkjXJ60wzjqD4Zw7PAaQfr0E4ZTLd94XfHN8/h
yhqfCMehu7eKmTJ2BloPk4ENEiWDJzTHk6pHpR9QvfRXGSOW9Zn89UlWfoKQPoWgrXGDlbLlffyn
5W8g2+AKu1jjwbgGX3XAWAfwSlT0KeWMK1a3QjoiSbTZ/3ckfprHxUv+SLrVXO1juK+l+ZBhP+WW
WUq/87ruotH0iWbGovEWaWyGkCZT3PvGyV2GpMd8Do1hVtN36gkCn8WpwPni/g8lP0svAKW9LUo2
/GgGkMiwSNNEz3uM6pix/lsT6yp9HSWDqWBwZ96rkdWKmj1FNoLKbeEwPoMpN4/kcC67/Feqw2CV
uShuiFVCNwd4D9JPCKbSW7tCi7vPLG4X4t0trELvv6zfBCwlc4KmHjnpZnikummu11/1bw++s0Sl
HKPGB0S7sW2nqzBIWyWKoB9Onda67+oO87VlZdqt8Fy0StmJ1tLJgnU4qHZ5eYZJ586rvozKAqJZ
G70s5oObs84UeHA/9+hx3EeRfnsQrGi/35iVymPPKRItfC9tIomayRhbPjuRYMSrl3c5mytpTkCu
Vx3cMBIt9TUEWSY7u5bf6fharc9aLPpRpc2F/iU5nyDEDSrG/3BGntudcDs++jDaz758pH8xPxB6
FWmmii+JLo7EcI1P/yiAv1Kb5oh85UnE3RM1IUo9VlTbjYAcxmLtoYdDNJ+W3A4SsK1gQb+D0dme
OKUh52gcxCOOpX4jYwP8qqhH5OsBSQztKzPETz87VVy7PK6UQdiJ5IejfFYPQ97qqpsGLySGtV3/
FIkaOhQg0WsanLT1kBfBtZGFgftARUYmGkg3YLLmuFKQb6Idyh5nJRLK61oBP80HIZXgRLTTRAJF
kFy7bmoCAHtjUq+xPeZ2WRFzFiL9zXNHGiS+rNZ4KjHd7h7QK41Nepxv7337/UKUYXVysz7PlfOq
7Qbl5yeJgpRLQgvETupBWQm8wLtuu3tuGYUIebcsNNY7praE2FR5VvL0mH64aA30xvnYBSyGpWdY
a18/Bk14kgdCqIHk4pPgovBaoBU2ygVa+53zyqHvYvASwJ4GV41XYOxfOQprCq0vs/+WdpjGfGoP
DHmZvTmOt+LZBonsOw0BuDeGY7tm6k5GANKX4R6da+P+4d9OrxW+eyIvmdhaaVuaGPp7SWLQ40aE
72U5XvQYtFeLLBquZ3leVhLWuG83CuAz6YKTDP6HKPJMkIWQ1GRpDCoGHYoG9y7ntMI3ixgZHZT2
EnrLJv74biSPusnV4d6BrypFldod9dRwe8qFZot3/KgkohFMnC5FgMebyPAIKSmkjCeS1av2I3+p
zk7rdyVbyi/Mx8zrA7HhTeCi+oKejeRaNaAfSmxWN+VO4LuEURVUtXVGLx/JykDo5yGG6FJeuIBg
X1YpDvH2gxDFGmr0/LKu/9n1m3H2vfID1AG6ysI1ANyiVOSfo0UOt3H9VlAXCw/VwRuxl6d7uKXu
3A4IoYyPAlfC2OEeNqpf4vPXGPYiZlWdfDurVCnUn4rYB5EBa4+UO/5HwiHAL05epv5CXtJCNrCP
ceII17eHwV8Tu0midBL9RpdoL+bVZB09UssFxkLajZRTj6LwCj3vtYmgOqu0eixwSQasylN4dGAM
l4RlFJrM6fWzFtSLMVEUDbL1a+63TaqK8teZrX90kx8bsXxGecBk9XorG/0Q8QWE5uTTe/C44Ed7
3ehK8IwBMAieUbxb7eiPiNJbQcBBg2a/4UBonTRv7fEotlllEjKgLhVP0t8MTy0dKX7jPgDiug3S
cOzGlFWDekOpacCzbg+9Phfq5N+hWpNtS87NLjt1raY1IwpJu1mWxID35951c6Y22+sXZeVrHV+Y
4W5D91ck+V0zFaW/SIUKos8jREUnBZxtK6GBCx6PMJwoBTc51clXPeHGYh+wl7MTcPj34aOkKfvQ
hKwew4DVJ4YwJlf/RsiXA7W7smXywViRct9rqAp9/CN3eSHrOMUvneJKFSq2YsEPK32Ufo/VaxnH
RgGpCHtgSjro5pk+n6D1PN7HuLYWYO8KkNAHC9DZS8Ja3X7BNFxvRa80A2ztIOsRlEts8FWgfTSW
S7PF1+ewqP6RNg26RIk84FSPMPPryg2dT+4hI1KUR3RiXGRF9GbcknxU871MTSzIVJBRJYi6dNQn
yHsPNXNCcuBXoonen5NWdtHCEYMmFu8VHlSSZaWkYNf5DUdPIC8sMcaN90cJ2S7K+w3qJmhYyVGB
2B1KqKNNBzKAnrmslBXUN9+cGFFmACixvgMWLQ2wJ5J3ikm4V8aN0HBcKMMV5nCwQgOuxoB6urw8
BaIs/QGjblXFg+co6PgAGpMl4kzjcRHBTN3Ol6mGV0gtryYyjSFj6tgbYEU01WFdkfnyJXqiFw8n
VOOoZscKCYRxbillkN3AuKxzCcFf/YOHczHoPqH5UX1ZvGsVjvSj9hskCAOCCEk/OPnoxZL68sqL
YyyFCkSSV0XIPsxpOOpnkoARh6xPYR+rIXVNehNNoSvqUukD/P0hSuAbuCpeQML5+wLhMhVy2Ej4
UalyGKF2YqVDCl5fpBvcl6cKtqs5mUydxlHycgSio4ZqH0041Px27I9AJ2qQXlciM/ZEFZkjxTxt
H00oPYF0VwwWFj1IRvDtJHxtPaJuNqDFcjEj5jQMCf+Zg+3iDqyYbk46n080tmJG4SZcphkGLqYy
0Uzks5hPwDCXOVoeop7OAs7sj1/5NdXNPfQXAE2F6nX/1CS98zQD3jE6rlvugEC1clsc8U+uaRtg
uxuP8hpDqXNVMZgo89ryAptoh8xGAh69kd1Dqe3e0fK+ezoWadQTQdbWIEH2J2fZm9WX8AO6vjZF
JuncEBpIPsUdxC42TJAmksXk9//BlmciGXSZHXJdt+usjQqcnCCSiq1RlBsta+JOI87eAIjGbZJC
xzPTXv8jJBgONs3dOghAHUpsSkJEN9fF2V+IL5iiWsUkzq9aKr6BM4OvC0EOt+vlOwZkhtstEF7f
xBDAPh29oFo5ewNzJQ3siHJkhnUHTnL6mV40UbdXHhS7Qg6uIcPJrk0WG3Z4J+2vxml0MhoQhBcN
vJZ+xqFyNlkCvggL/6jOd2aJKA2Gx5wiDWCk5oivEDcSehxOSO4rrZyXdoIGG0YNgPHjzpkNJ76a
+GBkZNM8H59og8ejifWncSsP+Fx3IXUzPbSSxPGBCUKdBqfAZceiwdAacVFZnU5jHBxUgXo/Lddw
zG8tuVlUF11Dk6BmLn9Bm4D+8dbjLaHrXp+qB8RQBYl7O1gVkxr4NkL2aP1naxUFOLZvPgkhWBTa
dgIvn/3+eWdPFRJr7rnL3T2rnG63sOU0HQwGBGAfHOJvLZJwQ75n37r8pem2UnpnOj/1h+kQOb9Y
WJj6IPXG2vr60t7VfQBhoPNUtqrcJEzhbzhzRZ4Ko8nK28OGXNfVAdFZDQYEVuoDMPmlar6AA+Hp
wXaj7RERy618PD+GBTu2Uas2UUSJ839DUM2Y1gZweWwhExp+y0AzXA7QZ3AicAVIzjkZBt2PTo3M
IovXI4DUy9bJC9NFLTcpqnyOLRdUSIeKcrJPWHvU6ERVrjz7gtDJcVUMDvNqhGPew7dCSZD1SfcT
w9rOvCS/qb/46bDVHBccoG06B3FJTSxQrTbx9qijhwNU/2SIq5Uodqn9NPOOgpEfpH6ZomlyyIjL
xOSIwH6qDzZ7hHuZ2v/u2DmP04XW62rT2UouyhcB/EoeRdYLyfECBbBkt7PlqFJ3LFD2pz6SqtiG
RDRcf2GqS09HSJVaMgtZX6X+hhBjyoJ0Nduxfs8JOrBQN7W++iQWcIIseGDlYW3LZzWlBsNYqjA7
F4TAlwfjIeSR+Us6q3G0GaSVyg0JfvsLNNphew0wCJzTeIENo4GdqSNxwmGmUZJhuADPJ3pQrqz2
28fGKVt0dgRoVhsZdbwXrfP+jEOWM0yQ5/sauPxU4kwdNg/HnJbgNq4jYoVh4W9+Tg/xa6QImiQI
OcM8I0KFhINpoT/o/dpIXDJXO+bYG/h1tb0qNcCLNmamwthkZwxz22XWcNPcFGfDhQMhpUwg0Vow
+JoPoxmvYHj7xVjR551oBy2fZawqBF6pNQ1Wv/Ip+dQpyULtn7jPDkIZ0jPnaOdhb0Hb6AAUEPwB
lcNPM7aUDndG6YwU7vfCG0AVQmIJXFVNTK51RpqLEpgzJ9Wv7d8HzU4gU9MYKQMWsVFBmvRR40SY
fMj74yfjNj6k8aNt3X4smWlXD9xOmN7fn4tUs8gZj2a3gfTjB6O0ODn6MQIiqprws5ON5fSuREj2
jqI/9e0uHU0QMOyjE/d67Ppqe5GBIMk0DpWP5evnFeYDMOcewxmrKxmgYgQ6ZNgoQvwCYudFFv0X
r54ZLrm8V7m1QmMP4o0qEcfKzruU1r8O3xwUyuPXexqtBNb2CGbykdFwR78EMsFkVkrAtKYiDo6n
k0dwo34xGTpAY1llLkliuJP2vRXPZdWUHiTdsTxTwrXHIj8caCgmXTQo2gMyIdZcif3aPjdRsMK5
rHKQ0ztTh60M/MuxOVPl70I/+VZbBRZvwpv5qnAMqIpGoXTwqdXvFomQE27wIFXyrpKe37NBh5iD
mFCXq/fpBi7E/SOK+C9A14I3hVV9tvSxTb9lNJk86ssg9Pj4NLaPBr9BCaI/ATJhnw4NMQM3R2rf
BU/N66s62CLq6RYj4EHJkzLL9weFP2Nn2a1jYPaHoWePrfZ+5zmKbrZrb2Ns7wxBE/OMkFv3/jIG
g59HwcfoM3iXN5R264SXXlT/E1weAAjnfL3wCK3S4PUE4vRIfKkTnIxOPfzXCEcffI9pnmsBxwlD
7UwsdmUXychEANYLOaSMbR5FltXUcEDeokK7iH39SVMhRhD6gZXpgTG1BM27xOi10ViRKmgQxCSK
+eAvs5Q0+jQE3xFQgQDKcBVQkDeHZSFGz1Z6yX+ODYAEmw4dwznFrWoWJbjMibALqZM7prKje8fw
CPSr3Ry3O3AhaLdZdsWkpUXsdvPsUD39wPYw9OPHvapqelRtpeei3QqhGZmEPVXk2txCYf1Bw9bU
myYz/rQUymQHkgPmfnTJIjh6KHf5+QJhlAH01+mUfl468K56Jy7PO70WN7g6urONsW4CLZ/Pfeqa
Mvty1Y1gOtGR8WInhw87O0nRaAPoUlMa/dmI2o80KepcV4rfIil9KiSv6kDJB5PhZ1wONL0fLjL0
xYNLkljRaQpRgeEPAJMdyRE6pQGiSHULbNxsP4M5iPyMWxXRZ9NDsnsjGZ/krmZY2TqWjrDBLeiy
BCwZz3dIwJ4FRYa58y3zBqfMb/lNNPITt3Mw8jnnjirGyeYYGzB2HLLVp8PTg7MtCUmyEQq1sGhq
fXUVoXKznczWtsVA382z7eG1Wlirq7j7S5xlUx2Ej/GCnEeRpfyLYUfJgqX2M0bA+kD2LjcIf1uo
3Zoex01YxFIauHWdcLf+xTDXFWGJeljJxVAIkrPQrPuZyE9qiys+qRWGQCAfFjvpg4AacGCnMgNF
EcKY2xMqqqjmDGpFi2uexejQLW/v2AnJH225sIssgIxWg+DdxRd+3eYy2sHHpZQX5XHKBgYbXOLH
mdUkZKUBHruSxzi4TuYtW16fqTNh7nZRhj8roMwl/rIzgl4XSjmjlxhx5rQAA6YcfdxoPVkjFmuZ
xbBJ/dX3pvdzgCdKfgqAnfnVfNpEU2R4yIZCj2AJeb7NuBrA7XeK3PwkXJZY6q184IDXK2f9KTlO
ksfYQPf7xqDhpHEILy8lIC0dXBYSSF2GosqXOLnnQUd1DJsie/qWm69cvv6kTffYs/aprzTBVrz1
cKel3FDbJsjklbCgMSXJfnqylrGNSzsa2uUSAg1K+udre9+Z1rHjKoRCF2d/8RF4wb3H714S/l3o
wtl3qn7+/8bpzcNZ5x+4uuKJcGD/0eek9G3sL/hs3+mtW9928uoPfdv//Lo6W3IAzLnVdR/4YXq2
gpE8i67+jzqOe+argxpJcs65QRU8ILE2vnJdszkwcpRcpRNP2KpTatxA/1QXE9QZyt2aqZuT03pL
gBzwTrCDusvpK51DF8LFXXbwCESByltBtjWolUCLA54bP1q3RBYb4FJD2UAdACJjncHFZn1vYv3k
eRSpZZXKTx5+IItGghKcCoOQg0DbwI4u2HujFwUJh9+sLrdynsXh7qxRqAPpV2CHBV+hdBRmIqu5
vCYntRICSQSDOcWKMI+lMoWDud+BfXcP/A+SSAxw7Sxxhb83fnmno492QKD0u6aZ0bP4Si5kGsNT
RXg4rw+e4JxaZoCqVv8Zo0fQrJvwBp9vVJHQLXysCKHeCYRk3SCGdOcEmNd02DStbVIbdCvPLs57
GSj3SkYk+MUOuK3EFqcM5nY2YfmRzwQQ3CbvjoWnYlrelkXF7zaCLhpiz4e9Hujk7Cqa+RoM2bJF
rXK2gKUVwXxtZs0bhrtDbeqPOA3yBRPMoYtuORTYQbu21aiJNc9PmzC9v/1vcmrzyxyY6W24SVNu
OLVlwVQrQzzrDywDPVJtev/jeDXltlqeerLDhRJO21RC8XPgroBmg4p8lVw1jbD0aQDm4uTckOn2
AF33FKi1sexq7BmszvUwbmWO5YjvnLQ4f/cmVXBTkbBgJDhP7hALg3I3xqWhK6j9sLyNSo9JeHRn
R3DbHE6qm+Le7lw2eCr8HrI4bmmf113ITO6L1+ioJ5PF5TL6UNu7u9YgYGF7pAmOBgxkMbaX25Q2
wOrbiIoOuAVF/LWKe0yJ50S9A2rVb73UIRlH5Crf4e0x7M2/0PMsgKUNZm7CpVijUWmHvHO5+7+q
qo6jFT7q2w1JOTToGPxicCl5t7adN5wIxYqh2uNCAUr0pwo/DhRi6116jZQS7SEjf0K4uEatm0e8
Oby6xL6dzfsxlkDTpjhp/JP2b+9EHUhGJmXVZWeI32GAkfJaYxMar6rLeOzvKX4KXQ1PIHdX0G6B
0Iol8PVNxa7tj4xcifMWayzH7WKnbIZ91vVAHNKuaHq71yD0BEGSXp3TVuuhxNnsQ4d+PscFpGId
pwxFUxyIlg6ZvRvObYDLKn77Ceeoy1e2D5G3QvyKuff2bZxaTr9aFqGMW7rQwRYUj0xLUhbBwwxC
Vrlv9u2fqFixpV4HdZfBxpNTqN9XToyofQ5xgU/2IqYckTjZSKXeyIEE6GsvMtcrOHW89FK/T2VL
VE4FBrKHbIxYIraDaB8p9LBiiCusmfujm7DG74UzhLOFF+X2l//NbA7kySzdGGgPztQZXoT0sdLz
3QRYL6+qSKJP37dsR3msPWq9SlqAarfZwrKmJ88Nznak1fugzdALzqynnLkMP7o3E6uzjV3bN3BR
mLQ6K9ytj/L5yWHBfb+09fJbMLlEiCmN/uaWd2GmKQRO2ROkaEmYMI2iepwz4Kf8e0FYtnjivYnT
2FeXv4YOcpMf27B+y9T34SOYsxjrUKHUbFV57bRJOvJV3w2Um9/UJgzKCFojpNFHRzUGIsvQ1T68
X4WWdVGZi8tJjFli7/G1l5mEL7NLC0UPWbqOss73rpcOZTxZL7ds94WhyVwBNUNONzAXKLnUgsQ4
SVfm5UmQWiekp9WiGQY1NVug/D2EisdSG6PGZC+oWNQXwUvlNqNVUjZX7Mz7e4c0Fb+uga6QpBum
DTRYSvJjzNhA4wXG4LQH/HXs9dm1DubnMPWZp2UT6rEY05AECLanF1PvYET+nPUn0iqpADSGGPLY
EqCLhQbivrhhy421LPfdLxG1nfx4Ur9UzooDoBa15hHQZWARkTKWH6DEAuVbyYHUMuvcbv5Ut0Vd
1/2X6vFWhEinjX72JC9/mP+2QVVc5psJz/4sOvybzAVYKLn6KRF21bYgOko9LfIZ/OBYRA+Fw1T5
ADQ0eo8w5HWSz6kiRdkKCijtlgphVEOznp2sXzjR2CU2JGxnm+XQl7BjpNZKkAY5Ax+81D4koQhk
ncmp3FxeUKZN8iWPu60snvavoWFcqMtY+DqWqaW0/Y6fXoxfVUdXsiPZmCXPlGah7HTPtMswrQui
eqXCuk2Rz1ToGEVyx84jS5VFr0UNwF686bmv+H4ztL8Pekro1TBphmBEqr/Im43ac2vjZtAP1h5i
HF83zG/dVJuiSaddpfLlpnF3+8bjKN5HsAqi+tiCH0kUtZhDcTAXDkdiv3skc97KFvWAHi0Y1Y5z
28UglltBC79t772doJaGYdrMZ8jUq0RrRoX4DnPtOufSrTGwDPkiS70FS/0GWirBG7qBERBdUjlr
p5n1fQ6SnFFwszLNWC4dvjYEWYCHvrEqJrG6K7/qb5PdNJDKY/IyR5FAz4L9F1Uop0Px5BZKCX0X
j3OY/ATkK7fFTL9AVSzHnpnppMKbuv6XyLWqs69BONJ3Ab5774ssON68jfT4K3eHtRfaJZtZZ28U
yVhNTECVszBIobZT8xSmxwbohu7x7HzopC/bOwTd2yo8HDq2E7hg4j709KD7ixweAuDLnT+eGJMg
1wy8iI6hym4YHydsSCr59fTU00zKCfjiUQ/ry1AkvHWF2nTJ7sO37iltkUYpN3V0XpsPJyUNFMy8
rZltiuHn750lxja1HOXTWnd1xyZsat0Chgqn2M2uM3vePY+qe6bNvmAyHHZehNp3DXXeeiZ3Y6Is
ogwKd3GCMoptQoWTW8qpb14umfJLKFHEWHxGvjl3KgPNRHKZ/p7FuQAmoOIcoc1D72mXD4u9+Bcn
MeLhVEeXYCIdEqfcjIvq3lQpHMsk9PfB2tsyPASza7INYKNZrspciwu58CF4uwtvh5PAgWeZWEUR
MBi0FXm7bGA4w+m7KrtybMA4qWU5SM0hyipmLicd6Bbc6e5QJ0pa3pOtSYSMjlUyAQfmw7Zru/4W
9AQWsXBwLf0fLP0tjH0khbk9qoC0ZRn4UToE0grOqM/MxvGsBeBSOyYeSHD9jjdjEitYvSqwmbTH
UP+VvdG8TWhK4YXM/qLPa4bPx1+WuMoakbqO7rEoOekwt3NfoEFrNOduLmpf51aHbr5zOjMCEwaR
dci+4BTU9EEUufQvKXF9I8SEL2EeWj8fl/A/I5c+G8GdPcSpmE8vgU2J3mij71WWbLqlCfeJgwVe
Uaqa/Pp4IRrz9LM7t+ECRRoyeubPIhNfKJIjzZzhjpYBPMGQeo2HonQlh6noY7nWhc24Jy3dA2A2
DqClPltNQq7sZKtnY3NxSN+ouJlo/K8og5Ayt59PNVxkYCxrElngGYCP5buONGZ73oAcsyLAilER
tfhgLzWHnpxueTKNpjkpwETq0pxAwCV1JiK98hlKnaXKEQNhFj9oFkjcFL1uC84H1SqiKcLEGcE3
cVgtP1aUfnozd3Spa8hkYk1Ow2Uvq8874mEKF72wK81/OnNYGIkFhDDEh8dFK+fIinILaOmXv8hJ
89RqA7FZwKEbxtfd8XxHREILDoj2eKAn+jogX3qcqdH4rt1ViixksZBVaduLD9n4ztojzpnU5CTK
xrVP38wpdGRw3Ex6mB6F10Mfaozw6iky1C3Hb9yEda5iiQfofnimstfShywiQ943PTkJDBCinhG9
xix+xynLKNBgK1L5t0a8Offeo/KD33YhudTXTjWBqOPMDjdbpzCRJyKhfv9IrF59DaKUcrpuLhF5
Jm4CKbzy6nJFNca9Nr4TZw9/ANvSwE494OILewH57/rLNK1jtiRnYM11XcpDQ7skznpn8JpurmC5
HBibYPrPNHoIIzoFWEsabwS+W9CbUAFo3ZEJCqU8e2fAZOGGeShxYvo7Ocq2PpGPTBPMsdPWNTh0
4uyEGdRXXc20YIQzzamdZc4IYP6WaGsU7gh4BMP6otIMeiFXHXnMWEO4b5wavk7+n9uilJcx/v+7
yULIb1oPoHGyfX2ITf1yXuYq3uadi1htqlGFwpQ7wlEiHcjixgNn0qSkZMeSMuuHPxPMwKj3ldMg
JVswhmAx71LiSsicSLY2WzGtpv6uxYqxAzCVYG4cV5rjr0XS1K0oByYkSBVMpUgRXBZd7uX/9oXY
YkaMOwhe8u6vhXa3bF5aUhrf93IlbuiMFkw4yl8fwrfyfToKrHkd0AQMAXeNO5GnBrlm5yfiOzUh
9vUfU/zkxpzwcU9z21SuNlqpt74uGjTqNnJu6X6WsPMAjR9omStGo0CysTJXxm21yVP9wUrLb24Z
fPFjziWHfRR2Z514aJ3O3amzZNBvTC5+/2kQ2RnHu7i1KZhO8i8unAOWjmRLXocA1EtMBchS5eBD
55HfwcciFM9pxtnjutPR0I6yw+yp1+wwlpdF6+l2hGHbyKxYHyNVsuKdZCruyLFAAeIHLkMAFYZm
do6QabaaVPLC0f+YvPVmS2TXfcMkWTbGE1gx3mWMsJI002Y0wLwEGSQh2KJeI26OnmwFPUcqhOJm
+e4FpdWDUVXoxRcUDg2BFGXBVnm7P60a580qw1p4z0sc1o/LZQpKtKeJx75KPPdH2QqEIxpzkHBj
gmVhFkEfbccjdYkN+nfNPAWJYloWRL0/c6cLzoBMxIyYUoAKQwCFuPNCOqt486SmjFy8kzB4suOz
pLc/LghSncpYTujPd3ovc59adZw/r0KlymIQ7DY9JD/apWgrR8zC3/MvMYutClmtL4lj+n1P1AQr
iqwGjBlRyVucnPNfcioURl9+gkrPBZkxEqc9UrZHuxqaC7X1doTZSaQsWk1uWuOnOctpq88mDhyi
z6jHTgiQwfYWU8/UdXX/tbW0qnjkLMuBzDRYqT2FrGx0R+U+p8yaj7uETcCVze/0uW146V+f11tW
8LBXSu0+dc2zj3lgkeDQptSuVDsYzawy2n/iJ3JJsHXysGPA4sRNgspNntGQuA+MmZgnDGQp2LPt
g/s7+mWNlA8fFypGPiCr4lr+ov8RkN55p4xYxsQIVU5okX5FOvv4oBNhd0Eb0j0EVK78gb1AN5p6
pOn0b35/QZ0KBHwcmu2Q+XLQRSv9xNyk9Dg7cCpxKWF0wt02WhHfZGFatjFYjF9GJETgLlq+4OYT
4GATa5pupY3P7PCa102t359JptDqPAUB/6DFhWOyVcG5CT+nDZjKQotze0pUd9uiuyJH787k4SkY
Zw7Zcx4zUO4KB7lmBP3sPBa10R9U3u8V0CutJx0E9IOd46rLyipbbY8eApCLDzyNWATFThTehRK0
8GvqT7TVBqUFxX8WlDvVA1pZ6eo+RXTub4YDS4O2xWdPAeZiUXENQx92NvSr8KxMHX8qkObuW6Ti
UkLy2wT5UFFykV0gEckSkWLqhgmVMF6kO/6g5JfR50Js1a9j8txo98d8woLMuDslIxoCQWr/kF43
CjJhP++OrWaQQBKUSQa19Wwtl1yoBMrky1XW5kden9GqCdNs2coIR8qq3SynUNCbpb2LcMWa55pV
y1V4YKDqicRd3+H5dQVw9ZnH+00QL9xAonwR56kcV8XDaw+uZV1DYfsDpvfLNVS7N5gM2gLjXXdK
RpOIEmhsGyY2CoBOV1Ijg61/QQQkTVBWugPuNIUu14l9VdZCuaBIm9OR4fed4EW826nND1YhcaBw
OFif//9ZAlUn3Nw//p1iqwZNJUItaXQG2DJt+uPjAtI436AoP/qMv1t3o1QECzpEGxLocx8mQxIz
ZAevYR1mpPfWEpz2J7MLDsButP0kQk5YHieuMNsPVdSxjD6gU15bYf326DpF1D2VTpBlXrU10ziR
dEsonEVGAcFvXtmZQbg3urHqVGLsk3fBIVrD0FQLFjYOZHLxyJA5VGhJf8CbD5m5gOnirNmPGibK
QXkutmUHV6Ig06gQQ9vH83sjQTgSVkdRkPrpjVSZxCBL+g6qtKo/p171rZPICeySIF65eroUSX5u
C5ClIRu5Taw8EX3fqMi9c2hACmBmzKVu8biug2Tizy0pePe097PhnAwvcTQ45Da8cQiVF8iNGSIN
MeB+LXBUbq6yWlm/vcp+EQwpsdbMbAiO58kfpiwN+272kj9uhI10IDDwT1FzK8VA7Vy1gqgBsiOt
AfGLEzqzw8ZilOp4YoDvBQun19up/QxnP+Kup4g4UZ3IzmIemRwvYI9EuA+/ZDAokcKZG/KvaaGg
LJhpLJhGbnca5jeQUr+hgND1mYDEhe1SPn55mH40SewkJrw6APiLwUxMZFjLRewMn6ezdj8x3cJK
4Oe6Qc622HOzLCXKrLvflSMSoxiIOEWkbu8BTMBERTr/cHfIe0ZBiV9hWZe91IzXomqf46qPIEIq
Yp+BiUeve8b3EoepDd3Gh61RcTXijJLnOl60AqTWEVrAgpWZILioqMZCDZbd+vh+bzIS1x9xfqbE
CSEAtbbd4J8zPLOus7SfduQEcUishAElgpK2+GL3FEVb98eWigJ4YKVC98XlZbCTixsKpZnlyNHg
JRi5/xepi8HiVqQ+5EjAarGq5nEccZgphcE+REonvxZ1NlU6SldA54zLgF6ZxYUFT97kNIEZOp8x
zjqdG7v3L31WBm1NaDFmR9G3FXrhkTeXz64RLNK6RI7oVGb6orZ8e/yv+ClEaOUC2Ju8yZP4a3ng
MU48U8lY+hbmAPSG8M5ANDq0zNV9f+GpfnUGjhhHIHBOD2jBQ9gtGusZrqeA+vMn5d9JGysXVBeq
GgDKrQJuv5B//hzYx6APubTMHwi39366bIS1YWM3p5Iqp0OEhw03LkcRQfNOEuZNNAsMJccecQL+
OviSYJXbtSUidjiqgLeah+Jq11XCpOlFgqIxRtIAOuvquYv/fPkMYDGfKytfu20o9niY5VlnC6NO
lfwuqRqck+NidfcGoyMj5aZRcbFoxx54bPHczITKxgxT8wFm+sDd6Py/dqwDxLZlDgBKTLxaoYRj
Ivig6I6J6DNAW/kXtyhz21Dps++izrfkWijoSw3GrQkzLiDTrrZSHlw1Eex1BjS9e+lQ4lfnJzs+
yTo7Sbmb7lHjN5Eqj/V/mgPS1z/HWwFqOywwyZ3cFHNE+cJpRXHYh44ualwX9u4Y6P/E55zTerUK
jVIM/MgjcUHp5mcyU4vycyeJoWbGTZ7DADJ8RbER8C807hnOrjzeGougHzDrMlngW9b6TdcWomnK
FXGscIEvOn15PGjoeGhriQUICrYu0UhI7MY2L47GqSpbdAfh0rk2Rj5aVz+UJW5DwhYKdhuFRM3S
xIGrc9rpLBKy4ChP90ngzZLSZNDr4qE7bD5XViwZ41VB+V8mln1Xlgspsgk4TJpCc/VqFddcMdB1
Vs4E//Mi3h3CVi1JdiE15/H9PGmQYJ5Oe2jq+qWo3+B0bGBpwki1RGfo79yT1JBKZbriKaQuHZuK
KKctbTVQXtkZN2h/37XnYSaugAZPrz+E0UmqJo5y1ZV5IQ3OuU0jpkOw7QzJ15o6sUNLCWQHvRAI
MzssKbbd6EAJA4rODVf5bHjRZXqhRl+nI36rG22cTtwLD9J54HZFDUujz0MMBRMl1xLLweWvaF7c
LSn2lgrYa535oEF3Ai11LGigLbjEgFCIcmGCkZuNXKFY1ZXnG0mZJE/xrxuxGfMYewteZSttcFog
b7OR7ljHiHUwkWMHCCZ/TlFCbZrbhNlmVNEgmBcEE7+spwgCFxFeoebPDccoIl91mIcuDYsONthO
MoDGLltIZoR5IueNXQnRXEEonbZmaWjcr2sHX2/s1G7cnUHzFyrGB2C3PL2NUfjvWBhHE5fr6Jje
TkL2wHknhxKlO5ou0274hCszZot4EFx/rT7oEQqGACQO5vGJo0VfjCDrFJi9W2rsEuwadLZ5BG2S
0TZnQUvgyszNxtaXl++t7yJzVP4ee8Tu08kbLHb31fLtrMqqr1W64bt/VbA318zFnKd3XteVHmAk
KmUMdN/GcDC1E/+9uD9NBiF5YqSrd6uLSfHGXcnqIZESu4/KDxKZDVigP/y6icXjwEuTd3B0gDYA
AUynh6WXBQRS4wrIOFW4QjgKfL8eVpkavm/7I1vnMUrB/8NHYFwsAFfGKBJ+3bmvdtps1FOSJMxN
DxB9YIm03Mk5vrYw1k4/Kude4RzR0RpIrBbgDqPG0IJZE8iDAaymLZj8+RjsW9XK/gVYbP+fNfjx
ymm6CxZh+wlGjOplP5iO2I8d3/fpXSWEOV+c5LIfJCkHPeNHIlG1n82CuQo+gMHQ/bTM5Excwnie
jRZPWGHSWvZs4pcc/fxFv7FOA9tIdMx21U4EgDy9WcEaFkGsLYsmvBhKXJJQafGY6Ld/bCaNq1Ov
TFJd1nsQGLxCvpdGd0x40azv8QSTqnvEH/QmfNYwmtkPDxBmD3hd19LYbyDkBDR6iHSnjo6yFGrS
iwji9TB06SF27ADm2OXRq66KSGihUdk3denVTwraN8Xt8L060k4sWA9zEszfLa7vEIOGrlbdZwwc
CZsX5Y94riN21cWdt+oZnuSIOC0IVZ1BB1ajvhLy+5PFIcgos2w+RS1vSa21vuUWoId/3UTdC8W7
ki7IZdQEHiuSuoXTaxZ6nayK5Fd/Et1102XEAFQf7k1K6pit4c0KFzffbukFmiHUdtK+YykNa+eO
KXjl47w9FL2mbYObBTmLBQDJJbIoZi7mCstqE0WysFl3krQ2L5Fb2aOH1lTYh5toFSNyrbUUksqf
/XMvOEr9bxaDyaIFi6rs/w6ozbjPN2k/+GH24y2RTarNx+NcHzXF8SI0jcggvmCRjNV9iFQ0m7wW
rXshy2OrK5Uf+ASNRIEGNCIIQekX5h5Wjvrase6d3Meql3pR4vL1BAL6/u4/LRday/b7zK5nhLZT
EZ71iRj/wmu4jegFHJKjukIGti1Sv9AKAuxZWHJLOnLz7HrnW4LpZAWUL5F/RDNuTz2NV0Gb9SPH
c1ivt/yNxjY+L18mtziH6W3/TXkfhxKp5l+Jf2JLRw2YUsFD2MEr194+zm/czVxgl28aIaL3kUZC
xrkgdLVOTrd0ZvguQNGOCkdcEVsS4gakobDvrLncxduzjDZ29eAf5IR01wdUvVmWzBBd7lmybrWw
hggNPXL2NdGvxS6jlqo+OhUQRs0e7nb6nGQCYyEqRxHDTgxG1D2HFkEj03G/imWDKDnxxcF7CxLr
PRNayVzCvJFerWnVHWjKicI6NyUksMiF2/U8w36pTMLmmVjC4kflQgflPRYzsDgUmfUk4TQazYv/
DwtB6Wy3+Qj15+LGcxJ+F5yy/aKcBynJwhf6BACt2NUNAOY977p4i5wgffQoyFkprmjOuCSnF7W9
M7G90ngN5A52p/d4GpRA8xduL7JTawHk7sjx3l7c2GZqGpwcVqazabnkMJ1k861Mv30p6pQFdeUd
b1BZgC94HvIbM+CcGTKKMYQ0Eva9kp1ork9jmX/nQxv4RhQa1N1+a/Bht3B3OqhGGXUJG/bdiMSQ
JAQDCBCNmdmY/YsOAET1ttUgECyt2TYRw8gLh6bgcaXPjQg7Iv8wICncj2gzDNQX6uPi/ykcfjbU
cHwqB6XLF28hnS97iqfZdeaX0Q9FK/GJkDdtAUTBbo71A0U6VX90DAIOlpIPlYt7lBUOgPK0ctLV
TTVT4851QyeYfqOQggRJ86pc+mHnxEb4F9mzUfR3hdXIQFDRnQ7YEHSDqFjhDYRUdtQNc6M6jAvt
yWQ0+XSnJ42XjenIJ4Ri2BJagGF8DfQlyRqUXhjevwR9jxcCNuJRyGANmfizwDtXqGQcZ9BsIKNv
YZZ7EoOeQNC49kopxZWgPHUxSpXR85tQxCh4xLFRXZ5WO+YNoNxoy6O0qzqh5IVrjbniDEaP1Wq/
F7j7yLVQTLhKE7pobxBTl6RHHV/E2u23wltBCxVfw3A9Iq/P4m6qrhwZSFiGk6p/CLD6u9r7MmK2
Rmp0G3DsYKPTrsj1COk0uVk+CRzKy/irz/JlwE+IYPR9GusdPqfLQc7nWadXGofyFgLTn0SSWKpt
WusrERs2SlGkCdMtL4Racwp2FT/SoCZrWqiyMremOK/+dB6Iu7IFaIZA6GFI/h0jt2nAF0gLKYgU
3T8FVZnxxLpxT1bU9JqmNqOvGHi9YaENooFhVmahrrPpDLtfXHCw1XUfkEzHW+myJJxf06lBlNFp
UvVC6b8tq2I7Tf3KL2JRTysBIzgrVaY34BPIWkBxNXfTuevAUMqxB2cqF5bT45MkOHdyVzXvhJZj
AJvqXXxcMRcA8r83/pLO1FLUeJLJBYPwCqgP2/ELtpQHa5mu1cNJdyzak2V3Tc1IOQguwz9ECoS7
nmBpFqDZz8zjcD5HBjQkS78H/0x1HpsZVefKKa8czZlSI3L3QGavdlp6Oy5FLb+YSr9H42h9Ojqc
BT7B9PeZxSTINVrE0utaidXOML4D4CAUSisXxkm3BVNwHm7LB+YgkKev7Nahq0vLxD65SrgTRs6i
LtRF/auYCKsy9LwdZ6QoOMJI4zzc3nfpqOumCrjlKyIpWDFvtKpALv8MCqurA0utBaeWKgKmlmhv
cAdAFZdoaOlhDeQL33eVQQVosJlsYBduCXQb63Tw/fJHFcywhSf8xK4uFxbhhIaJaitByik/IK2x
a3JjJ29wUBdEi0b+XZ9iPP8/xlY4p84dcTyCXy+bw9vRqvok7vNv6tOhpK9HnBNhiH1u4SIp8lEQ
HDzULs/UJPXiiV0iGVv0kd3La6BJIYFkd0mlC36tNP5Cx3J/nQX0vrjwsSJlDLVmFjjHB6IGv9nG
k5QusxpNP5tl0vf8qIIusa+QhHRPy+MtjrJSwmPlLbgB4CFnbGicGAnwj5enWUPd2g/v2JzJNYl2
/eIktzCJumz3H1ljjkoCUh/oTp96lKFRQdRFnyuaOC6aJAegbDUlO1U7O2BPbaPQ69Hs908c+IqZ
uUkmC9kGAS2scU77xiM9+yVRijyNd4LoHFmak1LH7qn9455XfPlyogPctH3zT5XOzPlxcB9FfZSu
PZAhlQwPrkkCH03Mkgw7rMwDP8aV2eKe/UZ2IxKQggrBF7kbHV4tcyIPvapPNma0qXhjuW8Zme8U
MNZfTC9agPDg5uBBsM1C3t4FSt/aC5XrEDpm7yqLdHYamCqWz6lNEjFRsxyHQn4h0FwyM2z18igT
HRrJ+x2o3jgp5g8BG/bj+zNFU5ndWmhGbbq0bmP+FxYmC2Ep9SDXDdqbM8+md1S4M0ZL+cOL06Ad
ZYy7vrI/yH3O9DRuxDrIT20n5RyamcTLQmkRGfxw+BFI3MX/T+fvs9OAbwrRcgmc+fP5y8m/Xxm/
6/PYEpT4ZBrMNmh6ZwpWuem1b+2bDUyaQMjvpstZZRVCKETUyKiQkFfv2Xx4N0Tryjw/W9wG7fmh
0vljektM22HRw89G2rA3OOO+pTD9nzNZXMcKOzlx5RMO9QL3AjEPQZwHavYQqWbsHg==
`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// nios_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_mm_interconnect_0 (
input wire mem_if_ddr2_emif_0_afi_clk_clk, // mem_if_ddr2_emif_0_afi_clk.clk
input wire mem32_to_avalon_0_reset_reset_bridge_in_reset_reset, // mem32_to_avalon_0_reset_reset_bridge_in_reset.reset
input wire mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset, // mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset.reset
input wire mem_if_ddr2_emif_0_soft_reset_reset_bridge_in_reset_reset, // mem_if_ddr2_emif_0_soft_reset_reset_bridge_in_reset.reset
input wire nios2_gen2_0_reset_reset_bridge_in_reset_reset, // nios2_gen2_0_reset_reset_bridge_in_reset.reset
input wire [25:0] mem32_to_avalon_0_avalon_master_address, // mem32_to_avalon_0_avalon_master.address
output wire mem32_to_avalon_0_avalon_master_waitrequest, // .waitrequest
input wire [3:0] mem32_to_avalon_0_avalon_master_byteenable, // .byteenable
input wire mem32_to_avalon_0_avalon_master_read, // .read
output wire [31:0] mem32_to_avalon_0_avalon_master_readdata, // .readdata
output wire mem32_to_avalon_0_avalon_master_readdatavalid, // .readdatavalid
input wire mem32_to_avalon_0_avalon_master_write, // .write
input wire [31:0] mem32_to_avalon_0_avalon_master_writedata, // .writedata
input wire [28:0] nios2_gen2_0_data_master_address, // nios2_gen2_0_data_master.address
output wire nios2_gen2_0_data_master_waitrequest, // .waitrequest
input wire [3:0] nios2_gen2_0_data_master_byteenable, // .byteenable
input wire nios2_gen2_0_data_master_read, // .read
output wire [31:0] nios2_gen2_0_data_master_readdata, // .readdata
input wire nios2_gen2_0_data_master_write, // .write
input wire [31:0] nios2_gen2_0_data_master_writedata, // .writedata
input wire nios2_gen2_0_data_master_debugaccess, // .debugaccess
input wire [28:0] nios2_gen2_0_instruction_master_address, // nios2_gen2_0_instruction_master.address
output wire nios2_gen2_0_instruction_master_waitrequest, // .waitrequest
input wire nios2_gen2_0_instruction_master_read, // .read
output wire [31:0] nios2_gen2_0_instruction_master_readdata, // .readdata
output wire [19:0] io_bridge_0_avalon_slave_0_address, // io_bridge_0_avalon_slave_0.address
output wire io_bridge_0_avalon_slave_0_write, // .write
output wire io_bridge_0_avalon_slave_0_read, // .read
input wire [7:0] io_bridge_0_avalon_slave_0_readdata, // .readdata
output wire [7:0] io_bridge_0_avalon_slave_0_writedata, // .writedata
input wire io_bridge_0_avalon_slave_0_readdatavalid, // .readdatavalid
input wire io_bridge_0_avalon_slave_0_waitrequest, // .waitrequest
output wire [23:0] mem_if_ddr2_emif_0_avl_address, // mem_if_ddr2_emif_0_avl.address
output wire mem_if_ddr2_emif_0_avl_write, // .write
output wire mem_if_ddr2_emif_0_avl_read, // .read
input wire [31:0] mem_if_ddr2_emif_0_avl_readdata, // .readdata
output wire [31:0] mem_if_ddr2_emif_0_avl_writedata, // .writedata
output wire mem_if_ddr2_emif_0_avl_beginbursttransfer, // .beginbursttransfer
output wire [2:0] mem_if_ddr2_emif_0_avl_burstcount, // .burstcount
output wire [3:0] mem_if_ddr2_emif_0_avl_byteenable, // .byteenable
input wire mem_if_ddr2_emif_0_avl_readdatavalid, // .readdatavalid
input wire mem_if_ddr2_emif_0_avl_waitrequest, // .waitrequest
output wire [8:0] nios2_gen2_0_debug_mem_slave_address, // nios2_gen2_0_debug_mem_slave.address
output wire nios2_gen2_0_debug_mem_slave_write, // .write
output wire nios2_gen2_0_debug_mem_slave_read, // .read
input wire [31:0] nios2_gen2_0_debug_mem_slave_readdata, // .readdata
output wire [31:0] nios2_gen2_0_debug_mem_slave_writedata, // .writedata
output wire [3:0] nios2_gen2_0_debug_mem_slave_byteenable, // .byteenable
input wire nios2_gen2_0_debug_mem_slave_waitrequest, // .waitrequest
output wire nios2_gen2_0_debug_mem_slave_debugaccess, // .debugaccess
output wire [2:0] pio_0_s1_address, // pio_0_s1.address
output wire pio_0_s1_write, // .write
input wire [31:0] pio_0_s1_readdata, // .readdata
output wire [31:0] pio_0_s1_writedata, // .writedata
output wire pio_0_s1_chipselect // .chipselect
);
wire mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_waitrequest; // mem32_to_avalon_0_avalon_master_agent:av_waitrequest -> mem32_to_avalon_0_avalon_master_translator:uav_waitrequest
wire [31:0] mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_readdata; // mem32_to_avalon_0_avalon_master_agent:av_readdata -> mem32_to_avalon_0_avalon_master_translator:uav_readdata
wire mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_debugaccess; // mem32_to_avalon_0_avalon_master_translator:uav_debugaccess -> mem32_to_avalon_0_avalon_master_agent:av_debugaccess
wire [28:0] mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_address; // mem32_to_avalon_0_avalon_master_translator:uav_address -> mem32_to_avalon_0_avalon_master_agent:av_address
wire mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_read; // mem32_to_avalon_0_avalon_master_translator:uav_read -> mem32_to_avalon_0_avalon_master_agent:av_read
wire [3:0] mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_byteenable; // mem32_to_avalon_0_avalon_master_translator:uav_byteenable -> mem32_to_avalon_0_avalon_master_agent:av_byteenable
wire mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_readdatavalid; // mem32_to_avalon_0_avalon_master_agent:av_readdatavalid -> mem32_to_avalon_0_avalon_master_translator:uav_readdatavalid
wire mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_lock; // mem32_to_avalon_0_avalon_master_translator:uav_lock -> mem32_to_avalon_0_avalon_master_agent:av_lock
wire mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_write; // mem32_to_avalon_0_avalon_master_translator:uav_write -> mem32_to_avalon_0_avalon_master_agent:av_write
wire [31:0] mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_writedata; // mem32_to_avalon_0_avalon_master_translator:uav_writedata -> mem32_to_avalon_0_avalon_master_agent:av_writedata
wire [2:0] mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_burstcount; // mem32_to_avalon_0_avalon_master_translator:uav_burstcount -> mem32_to_avalon_0_avalon_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> mem32_to_avalon_0_avalon_master_agent:rp_valid
wire [104:0] rsp_mux_src_data; // rsp_mux:src_data -> mem32_to_avalon_0_avalon_master_agent:rp_data
wire rsp_mux_src_ready; // mem32_to_avalon_0_avalon_master_agent:rp_ready -> rsp_mux:src_ready
wire [3:0] rsp_mux_src_channel; // rsp_mux:src_channel -> mem32_to_avalon_0_avalon_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> mem32_to_avalon_0_avalon_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> mem32_to_avalon_0_avalon_master_agent:rp_endofpacket
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_data_master_agent:av_waitrequest -> nios2_gen2_0_data_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_data_master_agent:av_readdata -> nios2_gen2_0_data_master_translator:uav_readdata
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_data_master_translator:uav_debugaccess -> nios2_gen2_0_data_master_agent:av_debugaccess
wire [28:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_data_master_translator:uav_address -> nios2_gen2_0_data_master_agent:av_address
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_data_master_translator:uav_read -> nios2_gen2_0_data_master_agent:av_read
wire [3:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_data_master_translator:uav_byteenable -> nios2_gen2_0_data_master_agent:av_byteenable
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_data_master_agent:av_readdatavalid -> nios2_gen2_0_data_master_translator:uav_readdatavalid
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_data_master_translator:uav_lock -> nios2_gen2_0_data_master_agent:av_lock
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_data_master_translator:uav_write -> nios2_gen2_0_data_master_agent:av_write
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_data_master_translator:uav_writedata -> nios2_gen2_0_data_master_agent:av_writedata
wire [2:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_data_master_translator:uav_burstcount -> nios2_gen2_0_data_master_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> nios2_gen2_0_data_master_agent:rp_valid
wire [104:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> nios2_gen2_0_data_master_agent:rp_data
wire rsp_mux_001_src_ready; // nios2_gen2_0_data_master_agent:rp_ready -> rsp_mux_001:src_ready
wire [3:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> nios2_gen2_0_data_master_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> nios2_gen2_0_data_master_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> nios2_gen2_0_data_master_agent:rp_endofpacket
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_instruction_master_agent:av_waitrequest -> nios2_gen2_0_instruction_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_instruction_master_agent:av_readdata -> nios2_gen2_0_instruction_master_translator:uav_readdata
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_instruction_master_translator:uav_debugaccess -> nios2_gen2_0_instruction_master_agent:av_debugaccess
wire [28:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_instruction_master_translator:uav_address -> nios2_gen2_0_instruction_master_agent:av_address
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_instruction_master_translator:uav_read -> nios2_gen2_0_instruction_master_agent:av_read
wire [3:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_instruction_master_translator:uav_byteenable -> nios2_gen2_0_instruction_master_agent:av_byteenable
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_instruction_master_agent:av_readdatavalid -> nios2_gen2_0_instruction_master_translator:uav_readdatavalid
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_instruction_master_translator:uav_lock -> nios2_gen2_0_instruction_master_agent:av_lock
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_instruction_master_translator:uav_write -> nios2_gen2_0_instruction_master_agent:av_write
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_instruction_master_translator:uav_writedata -> nios2_gen2_0_instruction_master_agent:av_writedata
wire [2:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_instruction_master_translator:uav_burstcount -> nios2_gen2_0_instruction_master_agent:av_burstcount
wire rsp_mux_002_src_valid; // rsp_mux_002:src_valid -> nios2_gen2_0_instruction_master_agent:rp_valid
wire [104:0] rsp_mux_002_src_data; // rsp_mux_002:src_data -> nios2_gen2_0_instruction_master_agent:rp_data
wire rsp_mux_002_src_ready; // nios2_gen2_0_instruction_master_agent:rp_ready -> rsp_mux_002:src_ready
wire [3:0] rsp_mux_002_src_channel; // rsp_mux_002:src_channel -> nios2_gen2_0_instruction_master_agent:rp_channel
wire rsp_mux_002_src_startofpacket; // rsp_mux_002:src_startofpacket -> nios2_gen2_0_instruction_master_agent:rp_startofpacket
wire rsp_mux_002_src_endofpacket; // rsp_mux_002:src_endofpacket -> nios2_gen2_0_instruction_master_agent:rp_endofpacket
wire [31:0] mem_if_ddr2_emif_0_avl_agent_m0_readdata; // mem_if_ddr2_emif_0_avl_translator:uav_readdata -> mem_if_ddr2_emif_0_avl_agent:m0_readdata
wire mem_if_ddr2_emif_0_avl_agent_m0_waitrequest; // mem_if_ddr2_emif_0_avl_translator:uav_waitrequest -> mem_if_ddr2_emif_0_avl_agent:m0_waitrequest
wire mem_if_ddr2_emif_0_avl_agent_m0_debugaccess; // mem_if_ddr2_emif_0_avl_agent:m0_debugaccess -> mem_if_ddr2_emif_0_avl_translator:uav_debugaccess
wire [28:0] mem_if_ddr2_emif_0_avl_agent_m0_address; // mem_if_ddr2_emif_0_avl_agent:m0_address -> mem_if_ddr2_emif_0_avl_translator:uav_address
wire [3:0] mem_if_ddr2_emif_0_avl_agent_m0_byteenable; // mem_if_ddr2_emif_0_avl_agent:m0_byteenable -> mem_if_ddr2_emif_0_avl_translator:uav_byteenable
wire mem_if_ddr2_emif_0_avl_agent_m0_read; // mem_if_ddr2_emif_0_avl_agent:m0_read -> mem_if_ddr2_emif_0_avl_translator:uav_read
wire mem_if_ddr2_emif_0_avl_agent_m0_readdatavalid; // mem_if_ddr2_emif_0_avl_translator:uav_readdatavalid -> mem_if_ddr2_emif_0_avl_agent:m0_readdatavalid
wire mem_if_ddr2_emif_0_avl_agent_m0_lock; // mem_if_ddr2_emif_0_avl_agent:m0_lock -> mem_if_ddr2_emif_0_avl_translator:uav_lock
wire [31:0] mem_if_ddr2_emif_0_avl_agent_m0_writedata; // mem_if_ddr2_emif_0_avl_agent:m0_writedata -> mem_if_ddr2_emif_0_avl_translator:uav_writedata
wire mem_if_ddr2_emif_0_avl_agent_m0_write; // mem_if_ddr2_emif_0_avl_agent:m0_write -> mem_if_ddr2_emif_0_avl_translator:uav_write
wire [4:0] mem_if_ddr2_emif_0_avl_agent_m0_burstcount; // mem_if_ddr2_emif_0_avl_agent:m0_burstcount -> mem_if_ddr2_emif_0_avl_translator:uav_burstcount
wire mem_if_ddr2_emif_0_avl_agent_rf_source_valid; // mem_if_ddr2_emif_0_avl_agent:rf_source_valid -> mem_if_ddr2_emif_0_avl_agent_rsp_fifo:in_valid
wire [105:0] mem_if_ddr2_emif_0_avl_agent_rf_source_data; // mem_if_ddr2_emif_0_avl_agent:rf_source_data -> mem_if_ddr2_emif_0_avl_agent_rsp_fifo:in_data
wire mem_if_ddr2_emif_0_avl_agent_rf_source_ready; // mem_if_ddr2_emif_0_avl_agent_rsp_fifo:in_ready -> mem_if_ddr2_emif_0_avl_agent:rf_source_ready
wire mem_if_ddr2_emif_0_avl_agent_rf_source_startofpacket; // mem_if_ddr2_emif_0_avl_agent:rf_source_startofpacket -> mem_if_ddr2_emif_0_avl_agent_rsp_fifo:in_startofpacket
wire mem_if_ddr2_emif_0_avl_agent_rf_source_endofpacket; // mem_if_ddr2_emif_0_avl_agent:rf_source_endofpacket -> mem_if_ddr2_emif_0_avl_agent_rsp_fifo:in_endofpacket
wire mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_valid; // mem_if_ddr2_emif_0_avl_agent_rsp_fifo:out_valid -> mem_if_ddr2_emif_0_avl_agent:rf_sink_valid
wire [105:0] mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_data; // mem_if_ddr2_emif_0_avl_agent_rsp_fifo:out_data -> mem_if_ddr2_emif_0_avl_agent:rf_sink_data
wire mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_ready; // mem_if_ddr2_emif_0_avl_agent:rf_sink_ready -> mem_if_ddr2_emif_0_avl_agent_rsp_fifo:out_ready
wire mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_startofpacket; // mem_if_ddr2_emif_0_avl_agent_rsp_fifo:out_startofpacket -> mem_if_ddr2_emif_0_avl_agent:rf_sink_startofpacket
wire mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_endofpacket; // mem_if_ddr2_emif_0_avl_agent_rsp_fifo:out_endofpacket -> mem_if_ddr2_emif_0_avl_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> mem_if_ddr2_emif_0_avl_agent:cp_valid
wire [104:0] cmd_mux_src_data; // cmd_mux:src_data -> mem_if_ddr2_emif_0_avl_agent:cp_data
wire cmd_mux_src_ready; // mem_if_ddr2_emif_0_avl_agent:cp_ready -> cmd_mux:src_ready
wire [3:0] cmd_mux_src_channel; // cmd_mux:src_channel -> mem_if_ddr2_emif_0_avl_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> mem_if_ddr2_emif_0_avl_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> mem_if_ddr2_emif_0_avl_agent:cp_endofpacket
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_readdata; // nios2_gen2_0_debug_mem_slave_translator:uav_readdata -> nios2_gen2_0_debug_mem_slave_agent:m0_readdata
wire nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest; // nios2_gen2_0_debug_mem_slave_translator:uav_waitrequest -> nios2_gen2_0_debug_mem_slave_agent:m0_waitrequest
wire nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess; // nios2_gen2_0_debug_mem_slave_agent:m0_debugaccess -> nios2_gen2_0_debug_mem_slave_translator:uav_debugaccess
wire [28:0] nios2_gen2_0_debug_mem_slave_agent_m0_address; // nios2_gen2_0_debug_mem_slave_agent:m0_address -> nios2_gen2_0_debug_mem_slave_translator:uav_address
wire [3:0] nios2_gen2_0_debug_mem_slave_agent_m0_byteenable; // nios2_gen2_0_debug_mem_slave_agent:m0_byteenable -> nios2_gen2_0_debug_mem_slave_translator:uav_byteenable
wire nios2_gen2_0_debug_mem_slave_agent_m0_read; // nios2_gen2_0_debug_mem_slave_agent:m0_read -> nios2_gen2_0_debug_mem_slave_translator:uav_read
wire nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid; // nios2_gen2_0_debug_mem_slave_translator:uav_readdatavalid -> nios2_gen2_0_debug_mem_slave_agent:m0_readdatavalid
wire nios2_gen2_0_debug_mem_slave_agent_m0_lock; // nios2_gen2_0_debug_mem_slave_agent:m0_lock -> nios2_gen2_0_debug_mem_slave_translator:uav_lock
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_writedata; // nios2_gen2_0_debug_mem_slave_agent:m0_writedata -> nios2_gen2_0_debug_mem_slave_translator:uav_writedata
wire nios2_gen2_0_debug_mem_slave_agent_m0_write; // nios2_gen2_0_debug_mem_slave_agent:m0_write -> nios2_gen2_0_debug_mem_slave_translator:uav_write
wire [2:0] nios2_gen2_0_debug_mem_slave_agent_m0_burstcount; // nios2_gen2_0_debug_mem_slave_agent:m0_burstcount -> nios2_gen2_0_debug_mem_slave_translator:uav_burstcount
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_valid; // nios2_gen2_0_debug_mem_slave_agent:rf_source_valid -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_valid
wire [105:0] nios2_gen2_0_debug_mem_slave_agent_rf_source_data; // nios2_gen2_0_debug_mem_slave_agent:rf_source_data -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_data
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_ready; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_ready -> nios2_gen2_0_debug_mem_slave_agent:rf_source_ready
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_startofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_endofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_valid -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_valid
wire [105:0] nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_data -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready; // nios2_gen2_0_debug_mem_slave_agent:rf_sink_ready -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_ready
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> nios2_gen2_0_debug_mem_slave_agent:cp_valid
wire [104:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> nios2_gen2_0_debug_mem_slave_agent:cp_data
wire cmd_mux_001_src_ready; // nios2_gen2_0_debug_mem_slave_agent:cp_ready -> cmd_mux_001:src_ready
wire [3:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> nios2_gen2_0_debug_mem_slave_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_endofpacket
wire [7:0] io_bridge_0_avalon_slave_0_agent_m0_readdata; // io_bridge_0_avalon_slave_0_translator:uav_readdata -> io_bridge_0_avalon_slave_0_agent:m0_readdata
wire io_bridge_0_avalon_slave_0_agent_m0_waitrequest; // io_bridge_0_avalon_slave_0_translator:uav_waitrequest -> io_bridge_0_avalon_slave_0_agent:m0_waitrequest
wire io_bridge_0_avalon_slave_0_agent_m0_debugaccess; // io_bridge_0_avalon_slave_0_agent:m0_debugaccess -> io_bridge_0_avalon_slave_0_translator:uav_debugaccess
wire [28:0] io_bridge_0_avalon_slave_0_agent_m0_address; // io_bridge_0_avalon_slave_0_agent:m0_address -> io_bridge_0_avalon_slave_0_translator:uav_address
wire [0:0] io_bridge_0_avalon_slave_0_agent_m0_byteenable; // io_bridge_0_avalon_slave_0_agent:m0_byteenable -> io_bridge_0_avalon_slave_0_translator:uav_byteenable
wire io_bridge_0_avalon_slave_0_agent_m0_read; // io_bridge_0_avalon_slave_0_agent:m0_read -> io_bridge_0_avalon_slave_0_translator:uav_read
wire io_bridge_0_avalon_slave_0_agent_m0_readdatavalid; // io_bridge_0_avalon_slave_0_translator:uav_readdatavalid -> io_bridge_0_avalon_slave_0_agent:m0_readdatavalid
wire io_bridge_0_avalon_slave_0_agent_m0_lock; // io_bridge_0_avalon_slave_0_agent:m0_lock -> io_bridge_0_avalon_slave_0_translator:uav_lock
wire [7:0] io_bridge_0_avalon_slave_0_agent_m0_writedata; // io_bridge_0_avalon_slave_0_agent:m0_writedata -> io_bridge_0_avalon_slave_0_translator:uav_writedata
wire io_bridge_0_avalon_slave_0_agent_m0_write; // io_bridge_0_avalon_slave_0_agent:m0_write -> io_bridge_0_avalon_slave_0_translator:uav_write
wire [0:0] io_bridge_0_avalon_slave_0_agent_m0_burstcount; // io_bridge_0_avalon_slave_0_agent:m0_burstcount -> io_bridge_0_avalon_slave_0_translator:uav_burstcount
wire io_bridge_0_avalon_slave_0_agent_rf_source_valid; // io_bridge_0_avalon_slave_0_agent:rf_source_valid -> io_bridge_0_avalon_slave_0_agent_rsp_fifo:in_valid
wire [78:0] io_bridge_0_avalon_slave_0_agent_rf_source_data; // io_bridge_0_avalon_slave_0_agent:rf_source_data -> io_bridge_0_avalon_slave_0_agent_rsp_fifo:in_data
wire io_bridge_0_avalon_slave_0_agent_rf_source_ready; // io_bridge_0_avalon_slave_0_agent_rsp_fifo:in_ready -> io_bridge_0_avalon_slave_0_agent:rf_source_ready
wire io_bridge_0_avalon_slave_0_agent_rf_source_startofpacket; // io_bridge_0_avalon_slave_0_agent:rf_source_startofpacket -> io_bridge_0_avalon_slave_0_agent_rsp_fifo:in_startofpacket
wire io_bridge_0_avalon_slave_0_agent_rf_source_endofpacket; // io_bridge_0_avalon_slave_0_agent:rf_source_endofpacket -> io_bridge_0_avalon_slave_0_agent_rsp_fifo:in_endofpacket
wire io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_valid; // io_bridge_0_avalon_slave_0_agent_rsp_fifo:out_valid -> io_bridge_0_avalon_slave_0_agent:rf_sink_valid
wire [78:0] io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_data; // io_bridge_0_avalon_slave_0_agent_rsp_fifo:out_data -> io_bridge_0_avalon_slave_0_agent:rf_sink_data
wire io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_ready; // io_bridge_0_avalon_slave_0_agent:rf_sink_ready -> io_bridge_0_avalon_slave_0_agent_rsp_fifo:out_ready
wire io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket; // io_bridge_0_avalon_slave_0_agent_rsp_fifo:out_startofpacket -> io_bridge_0_avalon_slave_0_agent:rf_sink_startofpacket
wire io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket; // io_bridge_0_avalon_slave_0_agent_rsp_fifo:out_endofpacket -> io_bridge_0_avalon_slave_0_agent:rf_sink_endofpacket
wire [31:0] pio_0_s1_agent_m0_readdata; // pio_0_s1_translator:uav_readdata -> pio_0_s1_agent:m0_readdata
wire pio_0_s1_agent_m0_waitrequest; // pio_0_s1_translator:uav_waitrequest -> pio_0_s1_agent:m0_waitrequest
wire pio_0_s1_agent_m0_debugaccess; // pio_0_s1_agent:m0_debugaccess -> pio_0_s1_translator:uav_debugaccess
wire [28:0] pio_0_s1_agent_m0_address; // pio_0_s1_agent:m0_address -> pio_0_s1_translator:uav_address
wire [3:0] pio_0_s1_agent_m0_byteenable; // pio_0_s1_agent:m0_byteenable -> pio_0_s1_translator:uav_byteenable
wire pio_0_s1_agent_m0_read; // pio_0_s1_agent:m0_read -> pio_0_s1_translator:uav_read
wire pio_0_s1_agent_m0_readdatavalid; // pio_0_s1_translator:uav_readdatavalid -> pio_0_s1_agent:m0_readdatavalid
wire pio_0_s1_agent_m0_lock; // pio_0_s1_agent:m0_lock -> pio_0_s1_translator:uav_lock
wire [31:0] pio_0_s1_agent_m0_writedata; // pio_0_s1_agent:m0_writedata -> pio_0_s1_translator:uav_writedata
wire pio_0_s1_agent_m0_write; // pio_0_s1_agent:m0_write -> pio_0_s1_translator:uav_write
wire [2:0] pio_0_s1_agent_m0_burstcount; // pio_0_s1_agent:m0_burstcount -> pio_0_s1_translator:uav_burstcount
wire pio_0_s1_agent_rf_source_valid; // pio_0_s1_agent:rf_source_valid -> pio_0_s1_agent_rsp_fifo:in_valid
wire [105:0] pio_0_s1_agent_rf_source_data; // pio_0_s1_agent:rf_source_data -> pio_0_s1_agent_rsp_fifo:in_data
wire pio_0_s1_agent_rf_source_ready; // pio_0_s1_agent_rsp_fifo:in_ready -> pio_0_s1_agent:rf_source_ready
wire pio_0_s1_agent_rf_source_startofpacket; // pio_0_s1_agent:rf_source_startofpacket -> pio_0_s1_agent_rsp_fifo:in_startofpacket
wire pio_0_s1_agent_rf_source_endofpacket; // pio_0_s1_agent:rf_source_endofpacket -> pio_0_s1_agent_rsp_fifo:in_endofpacket
wire pio_0_s1_agent_rsp_fifo_out_valid; // pio_0_s1_agent_rsp_fifo:out_valid -> pio_0_s1_agent:rf_sink_valid
wire [105:0] pio_0_s1_agent_rsp_fifo_out_data; // pio_0_s1_agent_rsp_fifo:out_data -> pio_0_s1_agent:rf_sink_data
wire pio_0_s1_agent_rsp_fifo_out_ready; // pio_0_s1_agent:rf_sink_ready -> pio_0_s1_agent_rsp_fifo:out_ready
wire pio_0_s1_agent_rsp_fifo_out_startofpacket; // pio_0_s1_agent_rsp_fifo:out_startofpacket -> pio_0_s1_agent:rf_sink_startofpacket
wire pio_0_s1_agent_rsp_fifo_out_endofpacket; // pio_0_s1_agent_rsp_fifo:out_endofpacket -> pio_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> pio_0_s1_agent:cp_valid
wire [104:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> pio_0_s1_agent:cp_data
wire cmd_mux_003_src_ready; // pio_0_s1_agent:cp_ready -> cmd_mux_003:src_ready
wire [3:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> pio_0_s1_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> pio_0_s1_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> pio_0_s1_agent:cp_endofpacket
wire mem32_to_avalon_0_avalon_master_agent_cp_valid; // mem32_to_avalon_0_avalon_master_agent:cp_valid -> router:sink_valid
wire [104:0] mem32_to_avalon_0_avalon_master_agent_cp_data; // mem32_to_avalon_0_avalon_master_agent:cp_data -> router:sink_data
wire mem32_to_avalon_0_avalon_master_agent_cp_ready; // router:sink_ready -> mem32_to_avalon_0_avalon_master_agent:cp_ready
wire mem32_to_avalon_0_avalon_master_agent_cp_startofpacket; // mem32_to_avalon_0_avalon_master_agent:cp_startofpacket -> router:sink_startofpacket
wire mem32_to_avalon_0_avalon_master_agent_cp_endofpacket; // mem32_to_avalon_0_avalon_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [104:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [3:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire nios2_gen2_0_data_master_agent_cp_valid; // nios2_gen2_0_data_master_agent:cp_valid -> router_001:sink_valid
wire [104:0] nios2_gen2_0_data_master_agent_cp_data; // nios2_gen2_0_data_master_agent:cp_data -> router_001:sink_data
wire nios2_gen2_0_data_master_agent_cp_ready; // router_001:sink_ready -> nios2_gen2_0_data_master_agent:cp_ready
wire nios2_gen2_0_data_master_agent_cp_startofpacket; // nios2_gen2_0_data_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire nios2_gen2_0_data_master_agent_cp_endofpacket; // nios2_gen2_0_data_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [104:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [3:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire nios2_gen2_0_instruction_master_agent_cp_valid; // nios2_gen2_0_instruction_master_agent:cp_valid -> router_002:sink_valid
wire [104:0] nios2_gen2_0_instruction_master_agent_cp_data; // nios2_gen2_0_instruction_master_agent:cp_data -> router_002:sink_data
wire nios2_gen2_0_instruction_master_agent_cp_ready; // router_002:sink_ready -> nios2_gen2_0_instruction_master_agent:cp_ready
wire nios2_gen2_0_instruction_master_agent_cp_startofpacket; // nios2_gen2_0_instruction_master_agent:cp_startofpacket -> router_002:sink_startofpacket
wire nios2_gen2_0_instruction_master_agent_cp_endofpacket; // nios2_gen2_0_instruction_master_agent:cp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> cmd_demux_002:sink_valid
wire [104:0] router_002_src_data; // router_002:src_data -> cmd_demux_002:sink_data
wire router_002_src_ready; // cmd_demux_002:sink_ready -> router_002:src_ready
wire [3:0] router_002_src_channel; // router_002:src_channel -> cmd_demux_002:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> cmd_demux_002:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> cmd_demux_002:sink_endofpacket
wire mem_if_ddr2_emif_0_avl_agent_rp_valid; // mem_if_ddr2_emif_0_avl_agent:rp_valid -> router_003:sink_valid
wire [104:0] mem_if_ddr2_emif_0_avl_agent_rp_data; // mem_if_ddr2_emif_0_avl_agent:rp_data -> router_003:sink_data
wire mem_if_ddr2_emif_0_avl_agent_rp_ready; // router_003:sink_ready -> mem_if_ddr2_emif_0_avl_agent:rp_ready
wire mem_if_ddr2_emif_0_avl_agent_rp_startofpacket; // mem_if_ddr2_emif_0_avl_agent:rp_startofpacket -> router_003:sink_startofpacket
wire mem_if_ddr2_emif_0_avl_agent_rp_endofpacket; // mem_if_ddr2_emif_0_avl_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux:sink_valid
wire [104:0] router_003_src_data; // router_003:src_data -> rsp_demux:sink_data
wire router_003_src_ready; // rsp_demux:sink_ready -> router_003:src_ready
wire [3:0] router_003_src_channel; // router_003:src_channel -> rsp_demux:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux:sink_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_valid; // nios2_gen2_0_debug_mem_slave_agent:rp_valid -> router_004:sink_valid
wire [104:0] nios2_gen2_0_debug_mem_slave_agent_rp_data; // nios2_gen2_0_debug_mem_slave_agent:rp_data -> router_004:sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rp_ready; // router_004:sink_ready -> nios2_gen2_0_debug_mem_slave_agent:rp_ready
wire nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_001:sink_valid
wire [104:0] router_004_src_data; // router_004:src_data -> rsp_demux_001:sink_data
wire router_004_src_ready; // rsp_demux_001:sink_ready -> router_004:src_ready
wire [3:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_001:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire io_bridge_0_avalon_slave_0_agent_rp_valid; // io_bridge_0_avalon_slave_0_agent:rp_valid -> router_005:sink_valid
wire [77:0] io_bridge_0_avalon_slave_0_agent_rp_data; // io_bridge_0_avalon_slave_0_agent:rp_data -> router_005:sink_data
wire io_bridge_0_avalon_slave_0_agent_rp_ready; // router_005:sink_ready -> io_bridge_0_avalon_slave_0_agent:rp_ready
wire io_bridge_0_avalon_slave_0_agent_rp_startofpacket; // io_bridge_0_avalon_slave_0_agent:rp_startofpacket -> router_005:sink_startofpacket
wire io_bridge_0_avalon_slave_0_agent_rp_endofpacket; // io_bridge_0_avalon_slave_0_agent:rp_endofpacket -> router_005:sink_endofpacket
wire pio_0_s1_agent_rp_valid; // pio_0_s1_agent:rp_valid -> router_006:sink_valid
wire [104:0] pio_0_s1_agent_rp_data; // pio_0_s1_agent:rp_data -> router_006:sink_data
wire pio_0_s1_agent_rp_ready; // router_006:sink_ready -> pio_0_s1_agent:rp_ready
wire pio_0_s1_agent_rp_startofpacket; // pio_0_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
wire pio_0_s1_agent_rp_endofpacket; // pio_0_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_003:sink_valid
wire [104:0] router_006_src_data; // router_006:src_data -> rsp_demux_003:sink_data
wire router_006_src_ready; // rsp_demux_003:sink_ready -> router_006:src_ready
wire [3:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_003:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire io_bridge_0_avalon_slave_0_burst_adapter_source0_valid; // io_bridge_0_avalon_slave_0_burst_adapter:source0_valid -> io_bridge_0_avalon_slave_0_agent:cp_valid
wire [77:0] io_bridge_0_avalon_slave_0_burst_adapter_source0_data; // io_bridge_0_avalon_slave_0_burst_adapter:source0_data -> io_bridge_0_avalon_slave_0_agent:cp_data
wire io_bridge_0_avalon_slave_0_burst_adapter_source0_ready; // io_bridge_0_avalon_slave_0_agent:cp_ready -> io_bridge_0_avalon_slave_0_burst_adapter:source0_ready
wire [3:0] io_bridge_0_avalon_slave_0_burst_adapter_source0_channel; // io_bridge_0_avalon_slave_0_burst_adapter:source0_channel -> io_bridge_0_avalon_slave_0_agent:cp_channel
wire io_bridge_0_avalon_slave_0_burst_adapter_source0_startofpacket; // io_bridge_0_avalon_slave_0_burst_adapter:source0_startofpacket -> io_bridge_0_avalon_slave_0_agent:cp_startofpacket
wire io_bridge_0_avalon_slave_0_burst_adapter_source0_endofpacket; // io_bridge_0_avalon_slave_0_burst_adapter:source0_endofpacket -> io_bridge_0_avalon_slave_0_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [104:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [3:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [104:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [3:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink0_valid
wire [104:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_001_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux_001:src1_ready
wire [3:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_002:sink0_valid
wire [104:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_001_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux_001:src2_ready
wire [3:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_001_src3_valid; // cmd_demux_001:src3_valid -> cmd_mux_003:sink0_valid
wire [104:0] cmd_demux_001_src3_data; // cmd_demux_001:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_001_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux_001:src3_ready
wire [3:0] cmd_demux_001_src3_channel; // cmd_demux_001:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_001_src3_startofpacket; // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_001_src3_endofpacket; // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_002_src0_valid; // cmd_demux_002:src0_valid -> cmd_mux:sink2_valid
wire [104:0] cmd_demux_002_src0_data; // cmd_demux_002:src0_data -> cmd_mux:sink2_data
wire cmd_demux_002_src0_ready; // cmd_mux:sink2_ready -> cmd_demux_002:src0_ready
wire [3:0] cmd_demux_002_src0_channel; // cmd_demux_002:src0_channel -> cmd_mux:sink2_channel
wire cmd_demux_002_src0_startofpacket; // cmd_demux_002:src0_startofpacket -> cmd_mux:sink2_startofpacket
wire cmd_demux_002_src0_endofpacket; // cmd_demux_002:src0_endofpacket -> cmd_mux:sink2_endofpacket
wire cmd_demux_002_src1_valid; // cmd_demux_002:src1_valid -> cmd_mux_001:sink1_valid
wire [104:0] cmd_demux_002_src1_data; // cmd_demux_002:src1_data -> cmd_mux_001:sink1_data
wire cmd_demux_002_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_002:src1_ready
wire [3:0] cmd_demux_002_src1_channel; // cmd_demux_002:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_002_src1_startofpacket; // cmd_demux_002:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_002_src1_endofpacket; // cmd_demux_002:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [104:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [3:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [104:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [3:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_src2_valid; // rsp_demux:src2_valid -> rsp_mux_002:sink0_valid
wire [104:0] rsp_demux_src2_data; // rsp_demux:src2_data -> rsp_mux_002:sink0_data
wire rsp_demux_src2_ready; // rsp_mux_002:sink0_ready -> rsp_demux:src2_ready
wire [3:0] rsp_demux_src2_channel; // rsp_demux:src2_channel -> rsp_mux_002:sink0_channel
wire rsp_demux_src2_startofpacket; // rsp_demux:src2_startofpacket -> rsp_mux_002:sink0_startofpacket
wire rsp_demux_src2_endofpacket; // rsp_demux:src2_endofpacket -> rsp_mux_002:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux_001:sink1_valid
wire [104:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux_001:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src0_ready
wire [3:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_002:sink1_valid
wire [104:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_002:sink1_data
wire rsp_demux_001_src1_ready; // rsp_mux_002:sink1_ready -> rsp_demux_001:src1_ready
wire [3:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_002:sink1_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_002:sink1_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_002:sink1_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux_001:sink2_valid
wire [104:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux_001:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux_001:sink2_ready -> rsp_demux_002:src0_ready
wire [3:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux_001:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux_001:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux_001:sink3_valid
wire [104:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux_001:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux_001:sink3_ready -> rsp_demux_003:src0_ready
wire [3:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux_001:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux_001:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux_001:sink3_endofpacket
wire router_005_src_valid; // router_005:src_valid -> io_bridge_0_avalon_slave_0_rsp_width_adapter:in_valid
wire [77:0] router_005_src_data; // router_005:src_data -> io_bridge_0_avalon_slave_0_rsp_width_adapter:in_data
wire router_005_src_ready; // io_bridge_0_avalon_slave_0_rsp_width_adapter:in_ready -> router_005:src_ready
wire [3:0] router_005_src_channel; // router_005:src_channel -> io_bridge_0_avalon_slave_0_rsp_width_adapter:in_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> io_bridge_0_avalon_slave_0_rsp_width_adapter:in_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> io_bridge_0_avalon_slave_0_rsp_width_adapter:in_endofpacket
wire io_bridge_0_avalon_slave_0_rsp_width_adapter_src_valid; // io_bridge_0_avalon_slave_0_rsp_width_adapter:out_valid -> rsp_demux_002:sink_valid
wire [104:0] io_bridge_0_avalon_slave_0_rsp_width_adapter_src_data; // io_bridge_0_avalon_slave_0_rsp_width_adapter:out_data -> rsp_demux_002:sink_data
wire io_bridge_0_avalon_slave_0_rsp_width_adapter_src_ready; // rsp_demux_002:sink_ready -> io_bridge_0_avalon_slave_0_rsp_width_adapter:out_ready
wire [3:0] io_bridge_0_avalon_slave_0_rsp_width_adapter_src_channel; // io_bridge_0_avalon_slave_0_rsp_width_adapter:out_channel -> rsp_demux_002:sink_channel
wire io_bridge_0_avalon_slave_0_rsp_width_adapter_src_startofpacket; // io_bridge_0_avalon_slave_0_rsp_width_adapter:out_startofpacket -> rsp_demux_002:sink_startofpacket
wire io_bridge_0_avalon_slave_0_rsp_width_adapter_src_endofpacket; // io_bridge_0_avalon_slave_0_rsp_width_adapter:out_endofpacket -> rsp_demux_002:sink_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> io_bridge_0_avalon_slave_0_cmd_width_adapter:in_valid
wire [104:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> io_bridge_0_avalon_slave_0_cmd_width_adapter:in_data
wire cmd_mux_002_src_ready; // io_bridge_0_avalon_slave_0_cmd_width_adapter:in_ready -> cmd_mux_002:src_ready
wire [3:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> io_bridge_0_avalon_slave_0_cmd_width_adapter:in_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> io_bridge_0_avalon_slave_0_cmd_width_adapter:in_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> io_bridge_0_avalon_slave_0_cmd_width_adapter:in_endofpacket
wire io_bridge_0_avalon_slave_0_cmd_width_adapter_src_valid; // io_bridge_0_avalon_slave_0_cmd_width_adapter:out_valid -> io_bridge_0_avalon_slave_0_burst_adapter:sink0_valid
wire [77:0] io_bridge_0_avalon_slave_0_cmd_width_adapter_src_data; // io_bridge_0_avalon_slave_0_cmd_width_adapter:out_data -> io_bridge_0_avalon_slave_0_burst_adapter:sink0_data
wire io_bridge_0_avalon_slave_0_cmd_width_adapter_src_ready; // io_bridge_0_avalon_slave_0_burst_adapter:sink0_ready -> io_bridge_0_avalon_slave_0_cmd_width_adapter:out_ready
wire [3:0] io_bridge_0_avalon_slave_0_cmd_width_adapter_src_channel; // io_bridge_0_avalon_slave_0_cmd_width_adapter:out_channel -> io_bridge_0_avalon_slave_0_burst_adapter:sink0_channel
wire io_bridge_0_avalon_slave_0_cmd_width_adapter_src_startofpacket; // io_bridge_0_avalon_slave_0_cmd_width_adapter:out_startofpacket -> io_bridge_0_avalon_slave_0_burst_adapter:sink0_startofpacket
wire io_bridge_0_avalon_slave_0_cmd_width_adapter_src_endofpacket; // io_bridge_0_avalon_slave_0_cmd_width_adapter:out_endofpacket -> io_bridge_0_avalon_slave_0_burst_adapter:sink0_endofpacket
wire mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_valid; // mem_if_ddr2_emif_0_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_data; // mem_if_ddr2_emif_0_avl_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> mem_if_ddr2_emif_0_avl_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> mem_if_ddr2_emif_0_avl_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> mem_if_ddr2_emif_0_avl_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // mem_if_ddr2_emif_0_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> mem_if_ddr2_emif_0_avl_agent:rdata_fifo_sink_error
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_error
wire io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_valid; // io_bridge_0_avalon_slave_0_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [9:0] io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_data; // io_bridge_0_avalon_slave_0_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> io_bridge_0_avalon_slave_0_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> io_bridge_0_avalon_slave_0_agent:rdata_fifo_sink_valid
wire [9:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> io_bridge_0_avalon_slave_0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // io_bridge_0_avalon_slave_0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> io_bridge_0_avalon_slave_0_agent:rdata_fifo_sink_error
wire pio_0_s1_agent_rdata_fifo_src_valid; // pio_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] pio_0_s1_agent_rdata_fifo_src_data; // pio_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
wire pio_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> pio_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> pio_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> pio_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // pio_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> pio_0_s1_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (26),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) mem32_to_avalon_0_avalon_master_translator (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_read), // .read
.uav_write (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (mem32_to_avalon_0_avalon_master_address), // avalon_anti_master_0.address
.av_waitrequest (mem32_to_avalon_0_avalon_master_waitrequest), // .waitrequest
.av_byteenable (mem32_to_avalon_0_avalon_master_byteenable), // .byteenable
.av_read (mem32_to_avalon_0_avalon_master_read), // .read
.av_readdata (mem32_to_avalon_0_avalon_master_readdata), // .readdata
.av_readdatavalid (mem32_to_avalon_0_avalon_master_readdatavalid), // .readdatavalid
.av_write (mem32_to_avalon_0_avalon_master_write), // .write
.av_writedata (mem32_to_avalon_0_avalon_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (29),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) nios2_gen2_0_data_master_translator (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.av_read (nios2_gen2_0_data_master_read), // .read
.av_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.av_write (nios2_gen2_0_data_master_write), // .write
.av_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.av_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (29),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_gen2_0_instruction_master_translator (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_gen2_0_instruction_master_read), // .read
.av_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (24),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (3),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (5),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) mem_if_ddr2_emif_0_avl_translator (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (mem_if_ddr2_emif_0_avl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (mem_if_ddr2_emif_0_avl_agent_m0_burstcount), // .burstcount
.uav_read (mem_if_ddr2_emif_0_avl_agent_m0_read), // .read
.uav_write (mem_if_ddr2_emif_0_avl_agent_m0_write), // .write
.uav_waitrequest (mem_if_ddr2_emif_0_avl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (mem_if_ddr2_emif_0_avl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (mem_if_ddr2_emif_0_avl_agent_m0_byteenable), // .byteenable
.uav_readdata (mem_if_ddr2_emif_0_avl_agent_m0_readdata), // .readdata
.uav_writedata (mem_if_ddr2_emif_0_avl_agent_m0_writedata), // .writedata
.uav_lock (mem_if_ddr2_emif_0_avl_agent_m0_lock), // .lock
.uav_debugaccess (mem_if_ddr2_emif_0_avl_agent_m0_debugaccess), // .debugaccess
.av_address (mem_if_ddr2_emif_0_avl_address), // avalon_anti_slave_0.address
.av_write (mem_if_ddr2_emif_0_avl_write), // .write
.av_read (mem_if_ddr2_emif_0_avl_read), // .read
.av_readdata (mem_if_ddr2_emif_0_avl_readdata), // .readdata
.av_writedata (mem_if_ddr2_emif_0_avl_writedata), // .writedata
.av_beginbursttransfer (mem_if_ddr2_emif_0_avl_beginbursttransfer), // .beginbursttransfer
.av_burstcount (mem_if_ddr2_emif_0_avl_burstcount), // .burstcount
.av_byteenable (mem_if_ddr2_emif_0_avl_byteenable), // .byteenable
.av_readdatavalid (mem_if_ddr2_emif_0_avl_readdatavalid), // .readdatavalid
.av_waitrequest (mem_if_ddr2_emif_0_avl_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_gen2_0_debug_mem_slave_translator (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.uav_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.uav_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.uav_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_debug_mem_slave_address), // avalon_anti_slave_0.address
.av_write (nios2_gen2_0_debug_mem_slave_write), // .write
.av_read (nios2_gen2_0_debug_mem_slave_read), // .read
.av_readdata (nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.av_writedata (nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.av_byteenable (nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.av_waitrequest (nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.av_debugaccess (nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (20),
.AV_DATA_W (8),
.UAV_DATA_W (8),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (1),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (1),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (1),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) io_bridge_0_avalon_slave_0_translator (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (io_bridge_0_avalon_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (io_bridge_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (io_bridge_0_avalon_slave_0_agent_m0_read), // .read
.uav_write (io_bridge_0_avalon_slave_0_agent_m0_write), // .write
.uav_waitrequest (io_bridge_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (io_bridge_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (io_bridge_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (io_bridge_0_avalon_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (io_bridge_0_avalon_slave_0_agent_m0_writedata), // .writedata
.uav_lock (io_bridge_0_avalon_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (io_bridge_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (io_bridge_0_avalon_slave_0_address), // avalon_anti_slave_0.address
.av_write (io_bridge_0_avalon_slave_0_write), // .write
.av_read (io_bridge_0_avalon_slave_0_read), // .read
.av_readdata (io_bridge_0_avalon_slave_0_readdata), // .readdata
.av_writedata (io_bridge_0_avalon_slave_0_writedata), // .writedata
.av_readdatavalid (io_bridge_0_avalon_slave_0_readdatavalid), // .readdatavalid
.av_waitrequest (io_bridge_0_avalon_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pio_0_s1_translator (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (pio_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pio_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (pio_0_s1_agent_m0_read), // .read
.uav_write (pio_0_s1_agent_m0_write), // .write
.uav_waitrequest (pio_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pio_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pio_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (pio_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (pio_0_s1_agent_m0_writedata), // .writedata
.uav_lock (pio_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (pio_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (pio_0_s1_address), // avalon_anti_slave_0.address
.av_write (pio_0_s1_write), // .write
.av_readdata (pio_0_s1_readdata), // .readdata
.av_writedata (pio_0_s1_writedata), // .writedata
.av_chipselect (pio_0_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_QOS_H (87),
.PKT_QOS_L (87),
.PKT_DATA_SIDEBAND_H (85),
.PKT_DATA_SIDEBAND_L (85),
.PKT_ADDR_SIDEBAND_H (84),
.PKT_ADDR_SIDEBAND_L (84),
.PKT_BURST_TYPE_H (83),
.PKT_BURST_TYPE_L (82),
.PKT_CACHE_H (99),
.PKT_CACHE_L (96),
.PKT_THREAD_ID_H (92),
.PKT_THREAD_ID_L (92),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_EXCLUSIVE (70),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (89),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (90),
.ST_DATA_W (105),
.ST_CHANNEL_W (4),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) mem32_to_avalon_0_avalon_master_agent (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_address), // av.address
.av_write (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_write), // .write
.av_read (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (mem32_to_avalon_0_avalon_master_agent_cp_valid), // cp.valid
.cp_data (mem32_to_avalon_0_avalon_master_agent_cp_data), // .data
.cp_startofpacket (mem32_to_avalon_0_avalon_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (mem32_to_avalon_0_avalon_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (mem32_to_avalon_0_avalon_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_QOS_H (87),
.PKT_QOS_L (87),
.PKT_DATA_SIDEBAND_H (85),
.PKT_DATA_SIDEBAND_L (85),
.PKT_ADDR_SIDEBAND_H (84),
.PKT_ADDR_SIDEBAND_L (84),
.PKT_BURST_TYPE_H (83),
.PKT_BURST_TYPE_L (82),
.PKT_CACHE_H (99),
.PKT_CACHE_L (96),
.PKT_THREAD_ID_H (92),
.PKT_THREAD_ID_L (92),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_EXCLUSIVE (70),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (89),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (90),
.ST_DATA_W (105),
.ST_CHANNEL_W (4),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_data_master_agent (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_data_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_QOS_H (87),
.PKT_QOS_L (87),
.PKT_DATA_SIDEBAND_H (85),
.PKT_DATA_SIDEBAND_L (85),
.PKT_ADDR_SIDEBAND_H (84),
.PKT_ADDR_SIDEBAND_L (84),
.PKT_BURST_TYPE_H (83),
.PKT_BURST_TYPE_L (82),
.PKT_CACHE_H (99),
.PKT_CACHE_L (96),
.PKT_THREAD_ID_H (92),
.PKT_THREAD_ID_L (92),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_EXCLUSIVE (70),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (89),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (90),
.ST_DATA_W (105),
.ST_CHANNEL_W (4),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (2),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_instruction_master_agent (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_002_src_valid), // rp.valid
.rp_data (rsp_mux_002_src_data), // .data
.rp_channel (rsp_mux_002_src_channel), // .channel
.rp_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_002_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (89),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (90),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (5),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) mem_if_ddr2_emif_0_avl_agent (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (mem_if_ddr2_emif_0_avl_agent_m0_address), // m0.address
.m0_burstcount (mem_if_ddr2_emif_0_avl_agent_m0_burstcount), // .burstcount
.m0_byteenable (mem_if_ddr2_emif_0_avl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (mem_if_ddr2_emif_0_avl_agent_m0_debugaccess), // .debugaccess
.m0_lock (mem_if_ddr2_emif_0_avl_agent_m0_lock), // .lock
.m0_readdata (mem_if_ddr2_emif_0_avl_agent_m0_readdata), // .readdata
.m0_readdatavalid (mem_if_ddr2_emif_0_avl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (mem_if_ddr2_emif_0_avl_agent_m0_read), // .read
.m0_waitrequest (mem_if_ddr2_emif_0_avl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (mem_if_ddr2_emif_0_avl_agent_m0_writedata), // .writedata
.m0_write (mem_if_ddr2_emif_0_avl_agent_m0_write), // .write
.rp_endofpacket (mem_if_ddr2_emif_0_avl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (mem_if_ddr2_emif_0_avl_agent_rp_ready), // .ready
.rp_valid (mem_if_ddr2_emif_0_avl_agent_rp_valid), // .valid
.rp_data (mem_if_ddr2_emif_0_avl_agent_rp_data), // .data
.rp_startofpacket (mem_if_ddr2_emif_0_avl_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (mem_if_ddr2_emif_0_avl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (mem_if_ddr2_emif_0_avl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (mem_if_ddr2_emif_0_avl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (mem_if_ddr2_emif_0_avl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (mem_if_ddr2_emif_0_avl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (33),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) mem_if_ddr2_emif_0_avl_agent_rsp_fifo (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (mem_if_ddr2_emif_0_avl_agent_rf_source_data), // in.data
.in_valid (mem_if_ddr2_emif_0_avl_agent_rf_source_valid), // .valid
.in_ready (mem_if_ddr2_emif_0_avl_agent_rf_source_ready), // .ready
.in_startofpacket (mem_if_ddr2_emif_0_avl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (mem_if_ddr2_emif_0_avl_agent_rf_source_endofpacket), // .endofpacket
.out_data (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_data), // out.data
.out_valid (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_valid), // .valid
.out_ready (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (89),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (90),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) nios2_gen2_0_debug_mem_slave_agent (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // m0.address
.m0_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.m0_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.m0_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.m0_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.rp_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // .ready
.rp_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.rp_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.rp_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_gen2_0_debug_mem_slave_agent_rsp_fifo (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // in.data
.in_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.in_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (77),
.PKT_ORI_BURST_SIZE_L (75),
.PKT_RESPONSE_STATUS_H (74),
.PKT_RESPONSE_STATUS_L (73),
.PKT_BURST_SIZE_H (54),
.PKT_BURST_SIZE_L (52),
.PKT_TRANS_LOCK (42),
.PKT_BEGIN_BURST (59),
.PKT_PROTECTION_H (68),
.PKT_PROTECTION_L (66),
.PKT_BURSTWRAP_H (51),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (44),
.PKT_ADDR_H (37),
.PKT_ADDR_L (9),
.PKT_TRANS_COMPRESSED_READ (38),
.PKT_TRANS_POSTED (39),
.PKT_TRANS_WRITE (40),
.PKT_TRANS_READ (41),
.PKT_DATA_H (7),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (8),
.PKT_BYTEEN_L (8),
.PKT_SRC_ID_H (62),
.PKT_SRC_ID_L (61),
.PKT_DEST_ID_H (64),
.PKT_DEST_ID_L (63),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (78),
.AVS_BURSTCOUNT_W (1),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) io_bridge_0_avalon_slave_0_agent (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (io_bridge_0_avalon_slave_0_agent_m0_address), // m0.address
.m0_burstcount (io_bridge_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (io_bridge_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (io_bridge_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (io_bridge_0_avalon_slave_0_agent_m0_lock), // .lock
.m0_readdata (io_bridge_0_avalon_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (io_bridge_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (io_bridge_0_avalon_slave_0_agent_m0_read), // .read
.m0_waitrequest (io_bridge_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (io_bridge_0_avalon_slave_0_agent_m0_writedata), // .writedata
.m0_write (io_bridge_0_avalon_slave_0_agent_m0_write), // .write
.rp_endofpacket (io_bridge_0_avalon_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (io_bridge_0_avalon_slave_0_agent_rp_ready), // .ready
.rp_valid (io_bridge_0_avalon_slave_0_agent_rp_valid), // .valid
.rp_data (io_bridge_0_avalon_slave_0_agent_rp_data), // .data
.rp_startofpacket (io_bridge_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (io_bridge_0_avalon_slave_0_burst_adapter_source0_ready), // cp.ready
.cp_valid (io_bridge_0_avalon_slave_0_burst_adapter_source0_valid), // .valid
.cp_data (io_bridge_0_avalon_slave_0_burst_adapter_source0_data), // .data
.cp_startofpacket (io_bridge_0_avalon_slave_0_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (io_bridge_0_avalon_slave_0_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (io_bridge_0_avalon_slave_0_burst_adapter_source0_channel), // .channel
.rf_sink_ready (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (io_bridge_0_avalon_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (io_bridge_0_avalon_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (io_bridge_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (io_bridge_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (io_bridge_0_avalon_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (79),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) io_bridge_0_avalon_slave_0_agent_rsp_fifo (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (io_bridge_0_avalon_slave_0_agent_rf_source_data), // in.data
.in_valid (io_bridge_0_avalon_slave_0_agent_rf_source_valid), // .valid
.in_ready (io_bridge_0_avalon_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (io_bridge_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (io_bridge_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (89),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (90),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) pio_0_s1_agent (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (pio_0_s1_agent_m0_address), // m0.address
.m0_burstcount (pio_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (pio_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pio_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (pio_0_s1_agent_m0_lock), // .lock
.m0_readdata (pio_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (pio_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pio_0_s1_agent_m0_read), // .read
.m0_waitrequest (pio_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pio_0_s1_agent_m0_writedata), // .writedata
.m0_write (pio_0_s1_agent_m0_write), // .write
.rp_endofpacket (pio_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pio_0_s1_agent_rp_ready), // .ready
.rp_valid (pio_0_s1_agent_rp_valid), // .valid
.rp_data (pio_0_s1_agent_rp_data), // .data
.rp_startofpacket (pio_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (pio_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pio_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pio_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pio_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pio_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pio_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pio_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pio_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pio_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pio_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (pio_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pio_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pio_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pio_0_s1_agent_rsp_fifo (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pio_0_s1_agent_rf_source_data), // in.data
.in_valid (pio_0_s1_agent_rf_source_valid), // .valid
.in_ready (pio_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (pio_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pio_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (pio_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (pio_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (pio_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pio_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pio_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
nios_mm_interconnect_0_router router (
.sink_ready (mem32_to_avalon_0_avalon_master_agent_cp_ready), // sink.ready
.sink_valid (mem32_to_avalon_0_avalon_master_agent_cp_valid), // .valid
.sink_data (mem32_to_avalon_0_avalon_master_agent_cp_data), // .data
.sink_startofpacket (mem32_to_avalon_0_avalon_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (mem32_to_avalon_0_avalon_master_agent_cp_endofpacket), // .endofpacket
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_router_001 router_001 (
.sink_ready (nios2_gen2_0_data_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_data_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_router_002 router_002 (
.sink_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_router_003 router_003 (
.sink_ready (mem_if_ddr2_emif_0_avl_agent_rp_ready), // sink.ready
.sink_valid (mem_if_ddr2_emif_0_avl_agent_rp_valid), // .valid
.sink_data (mem_if_ddr2_emif_0_avl_agent_rp_data), // .data
.sink_startofpacket (mem_if_ddr2_emif_0_avl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (mem_if_ddr2_emif_0_avl_agent_rp_endofpacket), // .endofpacket
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_router_004 router_004 (
.sink_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // sink.ready
.sink_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.sink_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // .endofpacket
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_router_005 router_005 (
.sink_ready (io_bridge_0_avalon_slave_0_agent_rp_ready), // sink.ready
.sink_valid (io_bridge_0_avalon_slave_0_agent_rp_valid), // .valid
.sink_data (io_bridge_0_avalon_slave_0_agent_rp_data), // .data
.sink_startofpacket (io_bridge_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (io_bridge_0_avalon_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_router_006 router_006 (
.sink_ready (pio_0_s1_agent_rp_ready), // sink.ready
.sink_valid (pio_0_s1_agent_rp_valid), // .valid
.sink_data (pio_0_s1_agent_rp_data), // .data
.sink_startofpacket (pio_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pio_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (37),
.PKT_ADDR_L (9),
.PKT_BEGIN_BURST (59),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (44),
.PKT_BYTEEN_H (8),
.PKT_BYTEEN_L (8),
.PKT_BURST_SIZE_H (54),
.PKT_BURST_SIZE_L (52),
.PKT_BURST_TYPE_H (56),
.PKT_BURST_TYPE_L (55),
.PKT_BURSTWRAP_H (51),
.PKT_BURSTWRAP_L (49),
.PKT_TRANS_COMPRESSED_READ (38),
.PKT_TRANS_WRITE (40),
.PKT_TRANS_READ (41),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (78),
.ST_CHANNEL_W (4),
.OUT_BYTE_CNT_H (44),
.OUT_BURSTWRAP_H (51),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (7),
.BURSTWRAP_CONST_VALUE (7),
.ADAPTER_VERSION ("13.1")
) io_bridge_0_avalon_slave_0_burst_adapter (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // cr0.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_valid), // sink0.valid
.sink0_data (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_data), // .data
.sink0_channel (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_channel), // .channel
.sink0_startofpacket (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_ready), // .ready
.source0_valid (io_bridge_0_avalon_slave_0_burst_adapter_source0_valid), // source0.valid
.source0_data (io_bridge_0_avalon_slave_0_burst_adapter_source0_data), // .data
.source0_channel (io_bridge_0_avalon_slave_0_burst_adapter_source0_channel), // .channel
.source0_startofpacket (io_bridge_0_avalon_slave_0_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (io_bridge_0_avalon_slave_0_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (io_bridge_0_avalon_slave_0_burst_adapter_source0_ready) // .ready
);
nios_mm_interconnect_0_cmd_demux cmd_demux (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_demux_001_src3_valid), // .valid
.src3_data (cmd_demux_001_src3_data), // .data
.src3_channel (cmd_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_001_src3_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_demux_002 cmd_demux_002 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (cmd_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_demux_002_src0_valid), // .valid
.src0_data (cmd_demux_002_src0_data), // .data
.src0_channel (cmd_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_002_src1_ready), // src1.ready
.src1_valid (cmd_demux_002_src1_valid), // .valid
.src1_data (cmd_demux_002_src1_data), // .data
.src1_channel (cmd_demux_002_src1_channel), // .channel
.src1_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_002_src1_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_mux cmd_mux (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (cmd_demux_002_src0_ready), // sink2.ready
.sink2_valid (cmd_demux_002_src0_valid), // .valid
.sink2_channel (cmd_demux_002_src0_channel), // .channel
.sink2_data (cmd_demux_002_src0_data), // .data
.sink2_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_demux_002_src0_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src1_valid), // .valid
.sink0_channel (cmd_demux_001_src1_channel), // .channel
.sink0_data (cmd_demux_001_src1_data), // .data
.sink0_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_002_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_002_src1_valid), // .valid
.sink1_channel (cmd_demux_002_src1_channel), // .channel
.sink1_data (cmd_demux_002_src1_data), // .data
.sink1_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_002_src1_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_mux_002 cmd_mux_002 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src2_valid), // .valid
.sink0_channel (cmd_demux_001_src2_channel), // .channel
.sink0_data (cmd_demux_001_src2_data), // .data
.sink0_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_mux_002 cmd_mux_003 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src3_valid), // .valid
.sink0_channel (cmd_demux_001_src3_channel), // .channel
.sink0_data (cmd_demux_001_src3_data), // .data
.sink0_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src3_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_rsp_demux rsp_demux (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_src2_ready), // src2.ready
.src2_valid (rsp_demux_src2_valid), // .valid
.src2_data (rsp_demux_src2_data), // .data
.src2_channel (rsp_demux_src2_channel), // .channel
.src2_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_src2_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_demux_002 rsp_demux_001 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_demux rsp_demux_002 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_channel), // .channel
.sink_data (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_data), // .data
.sink_startofpacket (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_demux rsp_demux_003 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_rsp_mux rsp_mux (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_rsp_mux_002 rsp_mux_002 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_002_src_ready), // src.ready
.src_valid (rsp_mux_002_src_valid), // .valid
.src_data (rsp_mux_002_src_data), // .data
.src_channel (rsp_mux_002_src_channel), // .channel
.src_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src2_ready), // sink0.ready
.sink0_valid (rsp_demux_src2_valid), // .valid
.sink0_channel (rsp_demux_src2_channel), // .channel
.sink0_data (rsp_demux_src2_data), // .data
.sink0_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src2_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (37),
.IN_PKT_ADDR_L (9),
.IN_PKT_DATA_H (7),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (8),
.IN_PKT_BYTEEN_L (8),
.IN_PKT_BYTE_CNT_H (48),
.IN_PKT_BYTE_CNT_L (44),
.IN_PKT_TRANS_COMPRESSED_READ (38),
.IN_PKT_TRANS_WRITE (40),
.IN_PKT_BURSTWRAP_H (51),
.IN_PKT_BURSTWRAP_L (49),
.IN_PKT_BURST_SIZE_H (54),
.IN_PKT_BURST_SIZE_L (52),
.IN_PKT_RESPONSE_STATUS_H (74),
.IN_PKT_RESPONSE_STATUS_L (73),
.IN_PKT_TRANS_EXCLUSIVE (43),
.IN_PKT_BURST_TYPE_H (56),
.IN_PKT_BURST_TYPE_L (55),
.IN_PKT_ORI_BURST_SIZE_L (75),
.IN_PKT_ORI_BURST_SIZE_H (77),
.IN_ST_DATA_W (78),
.OUT_PKT_ADDR_H (64),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (75),
.OUT_PKT_BYTE_CNT_L (71),
.OUT_PKT_TRANS_COMPRESSED_READ (65),
.OUT_PKT_BURST_SIZE_H (81),
.OUT_PKT_BURST_SIZE_L (79),
.OUT_PKT_RESPONSE_STATUS_H (101),
.OUT_PKT_RESPONSE_STATUS_L (100),
.OUT_PKT_TRANS_EXCLUSIVE (70),
.OUT_PKT_BURST_TYPE_H (83),
.OUT_PKT_BURST_TYPE_L (82),
.OUT_PKT_ORI_BURST_SIZE_L (102),
.OUT_PKT_ORI_BURST_SIZE_H (104),
.OUT_ST_DATA_W (105),
.ST_CHANNEL_W (4),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) io_bridge_0_avalon_slave_0_rsp_width_adapter (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_005_src_valid), // sink.valid
.in_channel (router_005_src_channel), // .channel
.in_startofpacket (router_005_src_startofpacket), // .startofpacket
.in_endofpacket (router_005_src_endofpacket), // .endofpacket
.in_ready (router_005_src_ready), // .ready
.in_data (router_005_src_data), // .data
.out_endofpacket (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_data), // .data
.out_channel (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_channel), // .channel
.out_valid (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_valid), // .valid
.out_ready (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (64),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (75),
.IN_PKT_BYTE_CNT_L (71),
.IN_PKT_TRANS_COMPRESSED_READ (65),
.IN_PKT_TRANS_WRITE (67),
.IN_PKT_BURSTWRAP_H (78),
.IN_PKT_BURSTWRAP_L (76),
.IN_PKT_BURST_SIZE_H (81),
.IN_PKT_BURST_SIZE_L (79),
.IN_PKT_RESPONSE_STATUS_H (101),
.IN_PKT_RESPONSE_STATUS_L (100),
.IN_PKT_TRANS_EXCLUSIVE (70),
.IN_PKT_BURST_TYPE_H (83),
.IN_PKT_BURST_TYPE_L (82),
.IN_PKT_ORI_BURST_SIZE_L (102),
.IN_PKT_ORI_BURST_SIZE_H (104),
.IN_ST_DATA_W (105),
.OUT_PKT_ADDR_H (37),
.OUT_PKT_ADDR_L (9),
.OUT_PKT_DATA_H (7),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (8),
.OUT_PKT_BYTEEN_L (8),
.OUT_PKT_BYTE_CNT_H (48),
.OUT_PKT_BYTE_CNT_L (44),
.OUT_PKT_TRANS_COMPRESSED_READ (38),
.OUT_PKT_BURST_SIZE_H (54),
.OUT_PKT_BURST_SIZE_L (52),
.OUT_PKT_RESPONSE_STATUS_H (74),
.OUT_PKT_RESPONSE_STATUS_L (73),
.OUT_PKT_TRANS_EXCLUSIVE (43),
.OUT_PKT_BURST_TYPE_H (56),
.OUT_PKT_BURST_TYPE_L (55),
.OUT_PKT_ORI_BURST_SIZE_L (75),
.OUT_PKT_ORI_BURST_SIZE_H (77),
.OUT_ST_DATA_W (78),
.ST_CHANNEL_W (4),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) io_bridge_0_avalon_slave_0_cmd_width_adapter (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_002_src_valid), // sink.valid
.in_channel (cmd_mux_002_src_channel), // .channel
.in_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_002_src_ready), // .ready
.in_data (cmd_mux_002_src_data), // .data
.out_endofpacket (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_data), // .data
.out_channel (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_channel), // .channel
.out_valid (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_valid), // .valid
.out_ready (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
nios_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (mem_if_ddr2_emif_0_afi_clk_clk), // in_clk_0.clk
.in_rst_0_reset (mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
nios_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (mem_if_ddr2_emif_0_afi_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
nios_mm_interconnect_0_avalon_st_adapter_002 #(
.inBitsPerSymbol (10),
.inUsePackets (0),
.inDataWidth (10),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (10),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (mem_if_ddr2_emif_0_afi_clk_clk), // in_clk_0.clk
.in_rst_0_reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
nios_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (mem_if_ddr2_emif_0_afi_clk_clk), // in_clk_0.clk
.in_rst_0_reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (pio_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (pio_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (pio_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_regs.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Registers of the uart 16550 core ////
//// ////
//// Known problems (limits): ////
//// Inserts 1 wait state in all WISHBONE transfers ////
//// ////
//// To Do: ////
//// Nothing or verification. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: (See log for the revision history ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_regs.v,v $
// Revision 1.42 2004/11/22 09:21:59 igorm
// Timeout interrupt should be generated only when there is at least ony
// character in the fifo.
//
// Revision 1.41 2004/05/21 11:44:41 tadejm
// Added synchronizer flops for RX input.
//
// Revision 1.40 2003/06/11 16:37:47 gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.39 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.38 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.37 2001/12/27 13:24:09 mohor
// lsr[7] was not showing overrun errors.
//
// Revision 1.36 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.35 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.34 2001/12/19 07:33:54 mohor
// Synplicity was having troubles with the comment.
//
// Revision 1.33 2001/12/17 10:14:43 mohor
// Things related to msr register changed. After THRE IRQ occurs, and one
// character is written to the transmit fifo, the detection of the THRE bit in the
// LSR is delayed for one character time.
//
// Revision 1.32 2001/12/14 13:19:24 mohor
// MSR register fixed.
//
// Revision 1.31 2001/12/14 10:06:58 mohor
// After reset modem status register MSR should be reset.
//
// Revision 1.30 2001/12/13 10:09:13 mohor
// thre irq should be cleared only when being source of interrupt.
//
// Revision 1.29 2001/12/12 09:05:46 mohor
// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).
//
// Revision 1.28 2001/12/10 19:52:41 gorban
// Scratch register added
//
// Revision 1.27 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.26 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.25 2001/11/28 19:36:39 gorban
// Fixed: timeout and break didn't pay attention to current data format when counting time
//
// Revision 1.24 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.23 2001/11/12 21:57:29 gorban
// fixed more typo bugs
//
// Revision 1.22 2001/11/12 15:02:28 mohor
// lsr1r error fixed.
//
// Revision 1.21 2001/11/12 14:57:27 mohor
// ti_int_pnd error fixed.
//
// Revision 1.20 2001/11/12 14:50:27 mohor
// ti_int_d error fixed.
//
// Revision 1.19 2001/11/10 12:43:21 gorban
// Logic Synthesis bugs fixed. Some other minor changes
//
// Revision 1.18 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.17 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.16 2001/11/02 09:55:16 mohor
// no message
//
// Revision 1.15 2001/10/31 15:19:22 gorban
// Fixes to break and timeout conditions
//
// Revision 1.14 2001/10/29 17:00:46 gorban
// fixed parity sending and tx_fifo resets over- and underrun
//
// Revision 1.13 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.12 2001/10/19 16:21:40 gorban
// Changes data_out to be synchronous again as it should have been.
//
// Revision 1.11 2001/10/18 20:35:45 gorban
// small fix
//
// Revision 1.10 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.9 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.10 2001/06/23 11:21:48 gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.9 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.8 2001/05/29 20:05:04 gorban
// Fixed some bugs and synthesis problems.
//
// Revision 1.7 2001/05/27 17:37:49 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.6 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.5 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:11+02 jacob
// Initial revision
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
`define UART_DL1 7:0
`define UART_DL2 15:8
module uart_regs (clk,
wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i,
// additional signals
modem_inputs,
stx_pad_o, srx_pad_i,
`ifdef DATA_BUS_WIDTH_8
`else
// debug interface signals enabled
ier, iir, fcr, mcr, lcr, msr, lsr, rf_count, tf_count, tstate, rstate,
`endif
rts_pad_o, dtr_pad_o, int_o
`ifdef UART_HAS_BAUDRATE_OUTPUT
, baud_o
`endif
);
input clk;
input wb_rst_i;
input [`UART_ADDR_WIDTH-1:0] wb_addr_i;
input [7:0] wb_dat_i;
output [7:0] wb_dat_o;
input wb_we_i;
input wb_re_i;
output stx_pad_o;
input srx_pad_i;
input [3:0] modem_inputs;
output rts_pad_o;
output dtr_pad_o;
output int_o;
`ifdef UART_HAS_BAUDRATE_OUTPUT
output baud_o;
`endif
`ifdef DATA_BUS_WIDTH_8
`else
// if 32-bit databus and debug interface are enabled
output [3:0] ier;
output [3:0] iir;
output [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
output [4:0] mcr;
output [7:0] lcr;
output [7:0] msr;
output [7:0] lsr;
output [`UART_FIFO_COUNTER_W-1:0] rf_count;
output [`UART_FIFO_COUNTER_W-1:0] tf_count;
output [2:0] tstate;
output [3:0] rstate;
`endif
wire [3:0] modem_inputs;
reg enable;
`ifdef UART_HAS_BAUDRATE_OUTPUT
assign baud_o = enable; // baud_o is actually the enable signal
`endif
wire stx_pad_o; // received from transmitter module
wire srx_pad_i;
wire srx_pad;
reg [7:0] wb_dat_o;
wire [`UART_ADDR_WIDTH-1:0] wb_addr_i;
wire [7:0] wb_dat_i;
reg [3:0] ier;
reg [3:0] iir;
reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
reg [4:0] mcr;
reg [7:0] lcr;
reg [7:0] msr;
reg [15:0] dl; // 32-bit divisor latch
reg [7:0] scratch; // UART scratch register
reg start_dlc; // activate dlc on writing to UART_DL1
reg lsr_mask_d; // delay for lsr_mask condition
reg msi_reset; // reset MSR 4 lower bits indicator
//reg threi_clear; // THRE interrupt clear flag
reg [15:0] dlc; // 32-bit divisor latch counter
reg int_o;
reg [3:0] trigger_level; // trigger level of the receiver FIFO
reg rx_reset;
reg tx_reset;
wire dlab; // divisor latch access bit
wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits
wire loopback; // loopback bit (MCR bit 4)
wire cts, dsr, ri, dcd; // effective signals
wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback)
wire rts_pad_o, dtr_pad_o; // modem control outputs
// LSR bits wires and regs
wire [7:0] lsr;
wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;
wire lsr_mask; // lsr_mask
//
// ASSINGS
//
assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
: {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign dlab = lcr[`UART_LC_DL];
assign loopback = mcr[4];
// assign modem outputs
assign rts_pad_o = mcr[`UART_MC_RTS];
assign dtr_pad_o = mcr[`UART_MC_DTR];
// Interrupt signals
wire rls_int; // receiver line status interrupt
wire rda_int; // receiver data available interrupt
wire ti_int; // timeout indicator interrupt
wire thre_int; // transmitter holding register empty interrupt
wire ms_int; // modem status interrupt
// FIFO signals
reg tf_push;
reg rf_pop;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_error_bit; // an error (parity or framing) is inside the fifo
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire [2:0] tstate;
wire [3:0] rstate;
wire [9:0] counter_t;
wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo.
reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle)
reg [7:0] block_value; // One character length minus stop bit
// Transmitter Instance
wire serial_out;
uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask);
// Synchronizing and sampling serial RX input
uart_sync_flops i_uart_sync_flops
(
.rst_i (wb_rst_i),
.clk_i (clk),
.stage1_rst_i (1'b0),
.stage1_clk_en_i (1'b1),
.async_dat_i (srx_pad_i),
.sync_dat_o (srx_pad)
);
defparam i_uart_sync_flops.width = 1;
defparam i_uart_sync_flops.init_value = 1'b1;
// handle loopback
wire serial_in = loopback ? serial_out : srx_pad;
assign stx_pad_o = loopback ? 1'b1 : serial_out;
// Receiver Instance
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
// Asynchronous reading here because the outputs are sampled in uart_wb.v file
always @(dl or dlab or ier or iir or scratch
or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading
begin
case (wb_addr_i)
`UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
`UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : ier;
`UART_REG_II : wb_dat_o = {4'b1100,iir};
`UART_REG_LC : wb_dat_o = lcr;
`UART_REG_LS : wb_dat_o = lsr;
`UART_REG_MS : wb_dat_o = msr;
`UART_REG_SR : wb_dat_o = scratch;
default: wb_dat_o = 8'b0; // ??
endcase // case(wb_addr_i)
end // always @ (dl or dlab or ier or iir or scratch...
// rf_pop signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
rf_pop <= #1 0;
else
if (rf_pop) // restore the signal to 0 after one clock cycle
rf_pop <= #1 0;
else
if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab)
rf_pop <= #1 1; // advance read pointer
end
wire lsr_mask_condition;
wire iir_read;
wire msr_read;
wire fifo_read;
wire fifo_write;
assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab);
assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab);
assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab);
assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab);
assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab);
// lsr_mask_d delayed signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
lsr_mask_d <= #1 0;
else // reset bits in the Line Status Register
lsr_mask_d <= #1 lsr_mask_condition;
end
// lsr_mask is rise detected
assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;
// msi_reset signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
msi_reset <= #1 1;
else
if (msi_reset)
msi_reset <= #1 0;
else
if (msr_read)
msi_reset <= #1 1; // reset bits in Modem Status Register
end
//
// WRITES AND RESETS //
//
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
lcr <= #1 8'b00000011; // 8n1 setting
else
if (wb_we_i && wb_addr_i==`UART_REG_LC)
lcr <= #1 wb_dat_i;
// Interrupt Enable Register or UART_DL2
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
begin
ier <= #1 4'b0000; // no interrupts after reset
dl[`UART_DL2] <= #1 8'b0;
end
else
if (wb_we_i && wb_addr_i==`UART_REG_IE)
if (dlab)
begin
dl[`UART_DL2] <= #1 wb_dat_i;
end
else
ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb
// FIFO Control Register and rx_reset, tx_reset signals
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
fcr <= #1 2'b11;
rx_reset <= #1 0;
tx_reset <= #1 0;
end else
if (wb_we_i && wb_addr_i==`UART_REG_FC) begin
fcr <= #1 wb_dat_i[7:6];
rx_reset <= #1 wb_dat_i[1];
tx_reset <= #1 wb_dat_i[2];
end else begin
rx_reset <= #1 0;
tx_reset <= #1 0;
end
// Modem Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
mcr <= #1 5'b0;
else
if (wb_we_i && wb_addr_i==`UART_REG_MC)
mcr <= #1 wb_dat_i[4:0];
// Scratch register
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
scratch <= #1 0; // 8n1 setting
else
if (wb_we_i && wb_addr_i==`UART_REG_SR)
scratch <= #1 wb_dat_i;
// TX_FIFO or UART_DL1
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
begin
dl[`UART_DL1] <= #1 8'b0;
tf_push <= #1 1'b0;
start_dlc <= #1 1'b0;
end
else
if (wb_we_i && wb_addr_i==`UART_REG_TR)
if (dlab)
begin
dl[`UART_DL1] <= #1 wb_dat_i;
start_dlc <= #1 1'b1; // enable DL counter
tf_push <= #1 1'b0;
end
else
begin
tf_push <= #1 1'b1;
start_dlc <= #1 1'b0;
end // else: !if(dlab)
else
begin
start_dlc <= #1 1'b0;
tf_push <= #1 1'b0;
end // else: !if(dlab)
// Receiver FIFO trigger level selection logic (asynchronous mux)
always @(fcr)
case (fcr[`UART_FC_TL])
2'b00 : trigger_level = 1;
2'b01 : trigger_level = 4;
2'b10 : trigger_level = 8;
2'b11 : trigger_level = 14;
endcase // case(fcr[`UART_FC_TL])
//
// STATUS REGISTERS //
//
// Modem Status Register
reg [3:0] delayed_modem_signals;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
msr <= #1 0;
delayed_modem_signals[3:0] <= #1 0;
end
else begin
msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 :
msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd_c, ri_c, dsr_c, cts_c};
delayed_modem_signals[3:0] <= #1 {dcd, ri, dsr, cts};
end
end
// Line Status Register
// activation conditions
assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition
assign lsr1 = rf_overrun; // Receiver overrun error
assign lsr2 = rf_data_out[1]; // parity error bit
assign lsr3 = rf_data_out[0]; // framing error bit
assign lsr4 = rf_data_out[2]; // break error in the character
assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty
assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty
assign lsr7 = rf_error_bit | rf_overrun;
// lsr bit0 (receiver data available)
reg lsr0_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr0_d <= #1 0;
else lsr0_d <= #1 lsr0;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr0r <= #1 0;
else lsr0r <= #1 (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 : // deassert condition
lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted
// lsr bit 1 (receiver overrun)
reg lsr1_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr1_d <= #1 0;
else lsr1_d <= #1 lsr1;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr1r <= #1 0;
else lsr1r <= #1 lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise
// lsr bit 2 (parity error)
reg lsr2_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr2_d <= #1 0;
else lsr2_d <= #1 lsr2;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr2r <= #1 0;
else lsr2r <= #1 lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise
// lsr bit 3 (framing error)
reg lsr3_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr3_d <= #1 0;
else lsr3_d <= #1 lsr3;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr3r <= #1 0;
else lsr3r <= #1 lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise
// lsr bit 4 (break indicator)
reg lsr4_d; // delayed
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr4_d <= #1 0;
else lsr4_d <= #1 lsr4;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr4r <= #1 0;
else lsr4r <= #1 lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d);
// lsr bit 5 (transmitter fifo is empty)
reg lsr5_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr5_d <= #1 1;
else lsr5_d <= #1 lsr5;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr5r <= #1 1;
else lsr5r <= #1 (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d);
// lsr bit 6 (transmitter empty indicator)
reg lsr6_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr6_d <= #1 1;
else lsr6_d <= #1 lsr6;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr6r <= #1 1;
else lsr6r <= #1 (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
// lsr bit 7 (error in fifo)
reg lsr7_d;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr7_d <= #1 0;
else lsr7_d <= #1 lsr7;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) lsr7r <= #1 0;
else lsr7r <= #1 lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d);
// Frequency divider
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
dlc <= #1 0;
else
if (start_dlc | ~ (|dlc))
dlc <= #1 dl - 1; // preset counter
else
dlc <= #1 dlc - 1; // decrement counter
end
// Enable signal generation logic
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
enable <= #1 1'b0;
else
if (|dl & ~(|dlc)) // dl>0 & dlc==0
enable <= #1 1'b1;
else
enable <= #1 1'b0;
end
// Delaying THRE status for one character cycle after a character is written to an empty fifo.
always @(lcr)
case (lcr[3:0])
4'b0000 : block_value = 95; // 6 bits
4'b0100 : block_value = 103; // 6.5 bits
4'b0001, 4'b1000 : block_value = 111; // 7 bits
4'b1100 : block_value = 119; // 7.5 bits
4'b0010, 4'b0101, 4'b1001 : block_value = 127; // 8 bits
4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; // 9 bits
4'b0111, 4'b1011, 4'b1110 : block_value = 159; // 10 bits
4'b1111 : block_value = 175; // 11 bits
endcase // case(lcr[3:0])
// Counting time of one character minus stop bit
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
block_cnt <= #1 8'd0;
else
if(lsr5r & fifo_write) // THRE bit set & write to fifo occured
block_cnt <= #1 block_value;
else
if (enable & block_cnt != 8'b0) // only work on enable times
block_cnt <= #1 block_cnt - 1; // decrement break counter
end // always of break condition detection
// Generating THRE status enable signal
assign thre_set_en = ~(|block_cnt);
//
// INTERRUPT LOGIC
//
assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
assign ms_int = ier[`UART_IE_MS] && (| msr[3:0]);
assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count);
reg rls_int_d;
reg thre_int_d;
reg ms_int_d;
reg ti_int_d;
reg rda_int_d;
// delay lines
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rls_int_d <= #1 0;
else rls_int_d <= #1 rls_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rda_int_d <= #1 0;
else rda_int_d <= #1 rda_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) thre_int_d <= #1 0;
else thre_int_d <= #1 thre_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ms_int_d <= #1 0;
else ms_int_d <= #1 ms_int;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ti_int_d <= #1 0;
else ti_int_d <= #1 ti_int;
// rise detection signals
wire rls_int_rise;
wire thre_int_rise;
wire ms_int_rise;
wire ti_int_rise;
wire rda_int_rise;
assign rda_int_rise = rda_int & ~rda_int_d;
assign rls_int_rise = rls_int & ~rls_int_d;
assign thre_int_rise = thre_int & ~thre_int_d;
assign ms_int_rise = ms_int & ~ms_int_d;
assign ti_int_rise = ti_int & ~ti_int_d;
// interrupt pending flags
reg rls_int_pnd;
reg rda_int_pnd;
reg thre_int_pnd;
reg ms_int_pnd;
reg ti_int_pnd;
// interrupt pending flags assignments
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rls_int_pnd <= #1 0;
else
rls_int_pnd <= #1 lsr_mask ? 0 : // reset condition
rls_int_rise ? 1 : // latch condition
rls_int_pnd && ier[`UART_IE_RLS]; // default operation: remove if masked
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) rda_int_pnd <= #1 0;
else
rda_int_pnd <= #1 ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 0 : // reset condition
rda_int_rise ? 1 : // latch condition
rda_int_pnd && ier[`UART_IE_RDA]; // default operation: remove if masked
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) thre_int_pnd <= #1 0;
else
thre_int_pnd <= #1 fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 :
thre_int_rise ? 1 :
thre_int_pnd && ier[`UART_IE_THRE];
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ms_int_pnd <= #1 0;
else
ms_int_pnd <= #1 msr_read ? 0 :
ms_int_rise ? 1 :
ms_int_pnd && ier[`UART_IE_MS];
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) ti_int_pnd <= #1 0;
else
ti_int_pnd <= #1 fifo_read ? 0 :
ti_int_rise ? 1 :
ti_int_pnd && ier[`UART_IE_RDA];
// end of pending flags
// INT_O logic
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
int_o <= #1 1'b0;
else
int_o <= #1
rls_int_pnd ? ~lsr_mask :
rda_int_pnd ? 1 :
ti_int_pnd ? ~fifo_read :
thre_int_pnd ? !(fifo_write & iir_read) :
ms_int_pnd ? ~msr_read :
0; // if no interrupt are pending
end
// Interrupt Identification register
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
iir <= #1 1;
else
if (rls_int_pnd) // interrupt is pending
begin
iir[`UART_II_II] <= #1 `UART_II_RLS; // set identification register to correct value
iir[`UART_II_IP] <= #1 1'b0; // and clear the IIR bit 0 (interrupt pending)
end else // the sequence of conditions determines priority of interrupt identification
if (rda_int)
begin
iir[`UART_II_II] <= #1 `UART_II_RDA;
iir[`UART_II_IP] <= #1 1'b0;
end
else if (ti_int_pnd)
begin
iir[`UART_II_II] <= #1 `UART_II_TI;
iir[`UART_II_IP] <= #1 1'b0;
end
else if (thre_int_pnd)
begin
iir[`UART_II_II] <= #1 `UART_II_THRE;
iir[`UART_II_IP] <= #1 1'b0;
end
else if (ms_int_pnd)
begin
iir[`UART_II_II] <= #1 `UART_II_MS;
iir[`UART_II_IP] <= #1 1'b0;
end else // no interrupt is pending
begin
iir[`UART_II_II] <= #1 0;
iir[`UART_II_IP] <= #1 1'b1;
end
end
endmodule
|
// soc_system.v
// Generated using ACDS version 14.1 186 at 2015.01.07.15:08:25
`timescale 1 ps / 1 ps
module soc_system (
input wire clk_clk, // clk.clk
input wire hps_0_f2h_cold_reset_req_reset_n, // hps_0_f2h_cold_reset_req.reset_n
input wire hps_0_f2h_debug_reset_req_reset_n, // hps_0_f2h_debug_reset_req.reset_n
input wire [27:0] hps_0_f2h_stm_hw_events_stm_hwevents, // hps_0_f2h_stm_hw_events.stm_hwevents
input wire hps_0_f2h_warm_reset_req_reset_n, // hps_0_f2h_warm_reset_req.reset_n
output wire hps_0_h2f_reset_reset_n, // hps_0_h2f_reset.reset_n
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CLK, // hps_0_hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_0_hps_io_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_0_hps_io_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_0_hps_io_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_0_hps_io_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_0_hps_io_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_0_hps_io_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_0_hps_io_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_0_hps_io_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_0_hps_io_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_0_hps_io_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_0_hps_io_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_0_hps_io_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_0_hps_io_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_0_hps_io_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_0_hps_io_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_0_hps_io_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_0_hps_io_hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_0_hps_io_hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_0_hps_io_hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_0_hps_io_hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_0_hps_io_hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_0_hps_io_hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_0_hps_io_hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_0_hps_io_hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_0_hps_io_hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_0_hps_io_hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_0_hps_io_hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_0_hps_io_hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_0_hps_io_hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_0_hps_io_hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_0_hps_io_hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_0_hps_io_hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_0_hps_io_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_0_hps_io_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_0_hps_io_hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_0_hps_io_hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_0_hps_io_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_0_hps_io_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO61, // .hps_io_gpio_inst_GPIO61
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
output wire [7:0] pio_led_external_connection_export, // pio_led_external_connection.export
input wire reset_reset_n // reset.reset_n
);
wire [1:0] hps_0_h2f_axi_master_awburst; // hps_0:h2f_AWBURST -> mm_interconnect_0:hps_0_h2f_axi_master_awburst
wire [3:0] hps_0_h2f_axi_master_arlen; // hps_0:h2f_ARLEN -> mm_interconnect_0:hps_0_h2f_axi_master_arlen
wire [7:0] hps_0_h2f_axi_master_wstrb; // hps_0:h2f_WSTRB -> mm_interconnect_0:hps_0_h2f_axi_master_wstrb
wire hps_0_h2f_axi_master_wready; // mm_interconnect_0:hps_0_h2f_axi_master_wready -> hps_0:h2f_WREADY
wire [11:0] hps_0_h2f_axi_master_rid; // mm_interconnect_0:hps_0_h2f_axi_master_rid -> hps_0:h2f_RID
wire hps_0_h2f_axi_master_rready; // hps_0:h2f_RREADY -> mm_interconnect_0:hps_0_h2f_axi_master_rready
wire [3:0] hps_0_h2f_axi_master_awlen; // hps_0:h2f_AWLEN -> mm_interconnect_0:hps_0_h2f_axi_master_awlen
wire [11:0] hps_0_h2f_axi_master_wid; // hps_0:h2f_WID -> mm_interconnect_0:hps_0_h2f_axi_master_wid
wire [3:0] hps_0_h2f_axi_master_arcache; // hps_0:h2f_ARCACHE -> mm_interconnect_0:hps_0_h2f_axi_master_arcache
wire hps_0_h2f_axi_master_wvalid; // hps_0:h2f_WVALID -> mm_interconnect_0:hps_0_h2f_axi_master_wvalid
wire [29:0] hps_0_h2f_axi_master_araddr; // hps_0:h2f_ARADDR -> mm_interconnect_0:hps_0_h2f_axi_master_araddr
wire [2:0] hps_0_h2f_axi_master_arprot; // hps_0:h2f_ARPROT -> mm_interconnect_0:hps_0_h2f_axi_master_arprot
wire [2:0] hps_0_h2f_axi_master_awprot; // hps_0:h2f_AWPROT -> mm_interconnect_0:hps_0_h2f_axi_master_awprot
wire [63:0] hps_0_h2f_axi_master_wdata; // hps_0:h2f_WDATA -> mm_interconnect_0:hps_0_h2f_axi_master_wdata
wire hps_0_h2f_axi_master_arvalid; // hps_0:h2f_ARVALID -> mm_interconnect_0:hps_0_h2f_axi_master_arvalid
wire [3:0] hps_0_h2f_axi_master_awcache; // hps_0:h2f_AWCACHE -> mm_interconnect_0:hps_0_h2f_axi_master_awcache
wire [11:0] hps_0_h2f_axi_master_arid; // hps_0:h2f_ARID -> mm_interconnect_0:hps_0_h2f_axi_master_arid
wire [1:0] hps_0_h2f_axi_master_arlock; // hps_0:h2f_ARLOCK -> mm_interconnect_0:hps_0_h2f_axi_master_arlock
wire [1:0] hps_0_h2f_axi_master_awlock; // hps_0:h2f_AWLOCK -> mm_interconnect_0:hps_0_h2f_axi_master_awlock
wire [29:0] hps_0_h2f_axi_master_awaddr; // hps_0:h2f_AWADDR -> mm_interconnect_0:hps_0_h2f_axi_master_awaddr
wire [1:0] hps_0_h2f_axi_master_bresp; // mm_interconnect_0:hps_0_h2f_axi_master_bresp -> hps_0:h2f_BRESP
wire hps_0_h2f_axi_master_arready; // mm_interconnect_0:hps_0_h2f_axi_master_arready -> hps_0:h2f_ARREADY
wire [63:0] hps_0_h2f_axi_master_rdata; // mm_interconnect_0:hps_0_h2f_axi_master_rdata -> hps_0:h2f_RDATA
wire hps_0_h2f_axi_master_awready; // mm_interconnect_0:hps_0_h2f_axi_master_awready -> hps_0:h2f_AWREADY
wire [1:0] hps_0_h2f_axi_master_arburst; // hps_0:h2f_ARBURST -> mm_interconnect_0:hps_0_h2f_axi_master_arburst
wire [2:0] hps_0_h2f_axi_master_arsize; // hps_0:h2f_ARSIZE -> mm_interconnect_0:hps_0_h2f_axi_master_arsize
wire hps_0_h2f_axi_master_bready; // hps_0:h2f_BREADY -> mm_interconnect_0:hps_0_h2f_axi_master_bready
wire hps_0_h2f_axi_master_rlast; // mm_interconnect_0:hps_0_h2f_axi_master_rlast -> hps_0:h2f_RLAST
wire hps_0_h2f_axi_master_wlast; // hps_0:h2f_WLAST -> mm_interconnect_0:hps_0_h2f_axi_master_wlast
wire [1:0] hps_0_h2f_axi_master_rresp; // mm_interconnect_0:hps_0_h2f_axi_master_rresp -> hps_0:h2f_RRESP
wire [11:0] hps_0_h2f_axi_master_awid; // hps_0:h2f_AWID -> mm_interconnect_0:hps_0_h2f_axi_master_awid
wire [11:0] hps_0_h2f_axi_master_bid; // mm_interconnect_0:hps_0_h2f_axi_master_bid -> hps_0:h2f_BID
wire hps_0_h2f_axi_master_bvalid; // mm_interconnect_0:hps_0_h2f_axi_master_bvalid -> hps_0:h2f_BVALID
wire [2:0] hps_0_h2f_axi_master_awsize; // hps_0:h2f_AWSIZE -> mm_interconnect_0:hps_0_h2f_axi_master_awsize
wire hps_0_h2f_axi_master_awvalid; // hps_0:h2f_AWVALID -> mm_interconnect_0:hps_0_h2f_axi_master_awvalid
wire hps_0_h2f_axi_master_rvalid; // mm_interconnect_0:hps_0_h2f_axi_master_rvalid -> hps_0:h2f_RVALID
wire [31:0] fpga_only_master_master_readdata; // mm_interconnect_0:fpga_only_master_master_readdata -> fpga_only_master:master_readdata
wire fpga_only_master_master_waitrequest; // mm_interconnect_0:fpga_only_master_master_waitrequest -> fpga_only_master:master_waitrequest
wire [31:0] fpga_only_master_master_address; // fpga_only_master:master_address -> mm_interconnect_0:fpga_only_master_master_address
wire fpga_only_master_master_read; // fpga_only_master:master_read -> mm_interconnect_0:fpga_only_master_master_read
wire [3:0] fpga_only_master_master_byteenable; // fpga_only_master:master_byteenable -> mm_interconnect_0:fpga_only_master_master_byteenable
wire fpga_only_master_master_readdatavalid; // mm_interconnect_0:fpga_only_master_master_readdatavalid -> fpga_only_master:master_readdatavalid
wire fpga_only_master_master_write; // fpga_only_master:master_write -> mm_interconnect_0:fpga_only_master_master_write
wire [31:0] fpga_only_master_master_writedata; // fpga_only_master:master_writedata -> mm_interconnect_0:fpga_only_master_master_writedata
wire [1:0] hps_0_h2f_lw_axi_master_awburst; // hps_0:h2f_lw_AWBURST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awburst
wire [3:0] hps_0_h2f_lw_axi_master_arlen; // hps_0:h2f_lw_ARLEN -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arlen
wire [3:0] hps_0_h2f_lw_axi_master_wstrb; // hps_0:h2f_lw_WSTRB -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wstrb
wire hps_0_h2f_lw_axi_master_wready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_wready -> hps_0:h2f_lw_WREADY
wire [11:0] hps_0_h2f_lw_axi_master_rid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rid -> hps_0:h2f_lw_RID
wire hps_0_h2f_lw_axi_master_rready; // hps_0:h2f_lw_RREADY -> mm_interconnect_0:hps_0_h2f_lw_axi_master_rready
wire [3:0] hps_0_h2f_lw_axi_master_awlen; // hps_0:h2f_lw_AWLEN -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awlen
wire [11:0] hps_0_h2f_lw_axi_master_wid; // hps_0:h2f_lw_WID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wid
wire [3:0] hps_0_h2f_lw_axi_master_arcache; // hps_0:h2f_lw_ARCACHE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arcache
wire hps_0_h2f_lw_axi_master_wvalid; // hps_0:h2f_lw_WVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wvalid
wire [20:0] hps_0_h2f_lw_axi_master_araddr; // hps_0:h2f_lw_ARADDR -> mm_interconnect_0:hps_0_h2f_lw_axi_master_araddr
wire [2:0] hps_0_h2f_lw_axi_master_arprot; // hps_0:h2f_lw_ARPROT -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arprot
wire [2:0] hps_0_h2f_lw_axi_master_awprot; // hps_0:h2f_lw_AWPROT -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awprot
wire [31:0] hps_0_h2f_lw_axi_master_wdata; // hps_0:h2f_lw_WDATA -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wdata
wire hps_0_h2f_lw_axi_master_arvalid; // hps_0:h2f_lw_ARVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arvalid
wire [3:0] hps_0_h2f_lw_axi_master_awcache; // hps_0:h2f_lw_AWCACHE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awcache
wire [11:0] hps_0_h2f_lw_axi_master_arid; // hps_0:h2f_lw_ARID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arid
wire [1:0] hps_0_h2f_lw_axi_master_arlock; // hps_0:h2f_lw_ARLOCK -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arlock
wire [1:0] hps_0_h2f_lw_axi_master_awlock; // hps_0:h2f_lw_AWLOCK -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awlock
wire [20:0] hps_0_h2f_lw_axi_master_awaddr; // hps_0:h2f_lw_AWADDR -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awaddr
wire [1:0] hps_0_h2f_lw_axi_master_bresp; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bresp -> hps_0:h2f_lw_BRESP
wire hps_0_h2f_lw_axi_master_arready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_arready -> hps_0:h2f_lw_ARREADY
wire [31:0] hps_0_h2f_lw_axi_master_rdata; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rdata -> hps_0:h2f_lw_RDATA
wire hps_0_h2f_lw_axi_master_awready; // mm_interconnect_0:hps_0_h2f_lw_axi_master_awready -> hps_0:h2f_lw_AWREADY
wire [1:0] hps_0_h2f_lw_axi_master_arburst; // hps_0:h2f_lw_ARBURST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arburst
wire [2:0] hps_0_h2f_lw_axi_master_arsize; // hps_0:h2f_lw_ARSIZE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_arsize
wire hps_0_h2f_lw_axi_master_bready; // hps_0:h2f_lw_BREADY -> mm_interconnect_0:hps_0_h2f_lw_axi_master_bready
wire hps_0_h2f_lw_axi_master_rlast; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rlast -> hps_0:h2f_lw_RLAST
wire hps_0_h2f_lw_axi_master_wlast; // hps_0:h2f_lw_WLAST -> mm_interconnect_0:hps_0_h2f_lw_axi_master_wlast
wire [1:0] hps_0_h2f_lw_axi_master_rresp; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rresp -> hps_0:h2f_lw_RRESP
wire [11:0] hps_0_h2f_lw_axi_master_awid; // hps_0:h2f_lw_AWID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awid
wire [11:0] hps_0_h2f_lw_axi_master_bid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bid -> hps_0:h2f_lw_BID
wire hps_0_h2f_lw_axi_master_bvalid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_bvalid -> hps_0:h2f_lw_BVALID
wire [2:0] hps_0_h2f_lw_axi_master_awsize; // hps_0:h2f_lw_AWSIZE -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awsize
wire hps_0_h2f_lw_axi_master_awvalid; // hps_0:h2f_lw_AWVALID -> mm_interconnect_0:hps_0_h2f_lw_axi_master_awvalid
wire hps_0_h2f_lw_axi_master_rvalid; // mm_interconnect_0:hps_0_h2f_lw_axi_master_rvalid -> hps_0:h2f_lw_RVALID
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire [63:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [12:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire [7:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [63:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
wire [31:0] mm_interconnect_0_intr_capturer_0_avalon_slave_0_readdata; // intr_capturer_0:rddata -> mm_interconnect_0:intr_capturer_0_avalon_slave_0_readdata
wire [0:0] mm_interconnect_0_intr_capturer_0_avalon_slave_0_address; // mm_interconnect_0:intr_capturer_0_avalon_slave_0_address -> intr_capturer_0:addr
wire mm_interconnect_0_intr_capturer_0_avalon_slave_0_read; // mm_interconnect_0:intr_capturer_0_avalon_slave_0_read -> intr_capturer_0:read
wire [31:0] mm_interconnect_0_sysid_qsys_control_slave_readdata; // sysid_qsys:readdata -> mm_interconnect_0:sysid_qsys_control_slave_readdata
wire [0:0] mm_interconnect_0_sysid_qsys_control_slave_address; // mm_interconnect_0:sysid_qsys_control_slave_address -> sysid_qsys:address
wire mm_interconnect_0_pio_led_s1_chipselect; // mm_interconnect_0:pio_led_s1_chipselect -> pio_led:chipselect
wire [31:0] mm_interconnect_0_pio_led_s1_readdata; // pio_led:readdata -> mm_interconnect_0:pio_led_s1_readdata
wire [1:0] mm_interconnect_0_pio_led_s1_address; // mm_interconnect_0:pio_led_s1_address -> pio_led:address
wire mm_interconnect_0_pio_led_s1_write; // mm_interconnect_0:pio_led_s1_write -> pio_led:write_n
wire [31:0] mm_interconnect_0_pio_led_s1_writedata; // mm_interconnect_0:pio_led_s1_writedata -> pio_led:writedata
wire [31:0] hps_only_master_master_readdata; // mm_interconnect_1:hps_only_master_master_readdata -> hps_only_master:master_readdata
wire hps_only_master_master_waitrequest; // mm_interconnect_1:hps_only_master_master_waitrequest -> hps_only_master:master_waitrequest
wire [31:0] hps_only_master_master_address; // hps_only_master:master_address -> mm_interconnect_1:hps_only_master_master_address
wire hps_only_master_master_read; // hps_only_master:master_read -> mm_interconnect_1:hps_only_master_master_read
wire [3:0] hps_only_master_master_byteenable; // hps_only_master:master_byteenable -> mm_interconnect_1:hps_only_master_master_byteenable
wire hps_only_master_master_readdatavalid; // mm_interconnect_1:hps_only_master_master_readdatavalid -> hps_only_master:master_readdatavalid
wire hps_only_master_master_write; // hps_only_master:master_write -> mm_interconnect_1:hps_only_master_master_write
wire [31:0] hps_only_master_master_writedata; // hps_only_master:master_writedata -> mm_interconnect_1:hps_only_master_master_writedata
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_awburst; // mm_interconnect_1:hps_0_f2h_axi_slave_awburst -> hps_0:f2h_AWBURST
wire [4:0] mm_interconnect_1_hps_0_f2h_axi_slave_awuser; // mm_interconnect_1:hps_0_f2h_axi_slave_awuser -> hps_0:f2h_AWUSER
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_arlen; // mm_interconnect_1:hps_0_f2h_axi_slave_arlen -> hps_0:f2h_ARLEN
wire [15:0] mm_interconnect_1_hps_0_f2h_axi_slave_wstrb; // mm_interconnect_1:hps_0_f2h_axi_slave_wstrb -> hps_0:f2h_WSTRB
wire mm_interconnect_1_hps_0_f2h_axi_slave_wready; // hps_0:f2h_WREADY -> mm_interconnect_1:hps_0_f2h_axi_slave_wready
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_rid; // hps_0:f2h_RID -> mm_interconnect_1:hps_0_f2h_axi_slave_rid
wire mm_interconnect_1_hps_0_f2h_axi_slave_rready; // mm_interconnect_1:hps_0_f2h_axi_slave_rready -> hps_0:f2h_RREADY
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_awlen; // mm_interconnect_1:hps_0_f2h_axi_slave_awlen -> hps_0:f2h_AWLEN
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_wid; // mm_interconnect_1:hps_0_f2h_axi_slave_wid -> hps_0:f2h_WID
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_arcache; // mm_interconnect_1:hps_0_f2h_axi_slave_arcache -> hps_0:f2h_ARCACHE
wire mm_interconnect_1_hps_0_f2h_axi_slave_wvalid; // mm_interconnect_1:hps_0_f2h_axi_slave_wvalid -> hps_0:f2h_WVALID
wire [31:0] mm_interconnect_1_hps_0_f2h_axi_slave_araddr; // mm_interconnect_1:hps_0_f2h_axi_slave_araddr -> hps_0:f2h_ARADDR
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_arprot; // mm_interconnect_1:hps_0_f2h_axi_slave_arprot -> hps_0:f2h_ARPROT
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_awprot; // mm_interconnect_1:hps_0_f2h_axi_slave_awprot -> hps_0:f2h_AWPROT
wire [127:0] mm_interconnect_1_hps_0_f2h_axi_slave_wdata; // mm_interconnect_1:hps_0_f2h_axi_slave_wdata -> hps_0:f2h_WDATA
wire mm_interconnect_1_hps_0_f2h_axi_slave_arvalid; // mm_interconnect_1:hps_0_f2h_axi_slave_arvalid -> hps_0:f2h_ARVALID
wire [3:0] mm_interconnect_1_hps_0_f2h_axi_slave_awcache; // mm_interconnect_1:hps_0_f2h_axi_slave_awcache -> hps_0:f2h_AWCACHE
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_arid; // mm_interconnect_1:hps_0_f2h_axi_slave_arid -> hps_0:f2h_ARID
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_arlock; // mm_interconnect_1:hps_0_f2h_axi_slave_arlock -> hps_0:f2h_ARLOCK
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_awlock; // mm_interconnect_1:hps_0_f2h_axi_slave_awlock -> hps_0:f2h_AWLOCK
wire [31:0] mm_interconnect_1_hps_0_f2h_axi_slave_awaddr; // mm_interconnect_1:hps_0_f2h_axi_slave_awaddr -> hps_0:f2h_AWADDR
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_bresp; // hps_0:f2h_BRESP -> mm_interconnect_1:hps_0_f2h_axi_slave_bresp
wire mm_interconnect_1_hps_0_f2h_axi_slave_arready; // hps_0:f2h_ARREADY -> mm_interconnect_1:hps_0_f2h_axi_slave_arready
wire [127:0] mm_interconnect_1_hps_0_f2h_axi_slave_rdata; // hps_0:f2h_RDATA -> mm_interconnect_1:hps_0_f2h_axi_slave_rdata
wire mm_interconnect_1_hps_0_f2h_axi_slave_awready; // hps_0:f2h_AWREADY -> mm_interconnect_1:hps_0_f2h_axi_slave_awready
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_arburst; // mm_interconnect_1:hps_0_f2h_axi_slave_arburst -> hps_0:f2h_ARBURST
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_arsize; // mm_interconnect_1:hps_0_f2h_axi_slave_arsize -> hps_0:f2h_ARSIZE
wire mm_interconnect_1_hps_0_f2h_axi_slave_bready; // mm_interconnect_1:hps_0_f2h_axi_slave_bready -> hps_0:f2h_BREADY
wire mm_interconnect_1_hps_0_f2h_axi_slave_rlast; // hps_0:f2h_RLAST -> mm_interconnect_1:hps_0_f2h_axi_slave_rlast
wire mm_interconnect_1_hps_0_f2h_axi_slave_wlast; // mm_interconnect_1:hps_0_f2h_axi_slave_wlast -> hps_0:f2h_WLAST
wire [1:0] mm_interconnect_1_hps_0_f2h_axi_slave_rresp; // hps_0:f2h_RRESP -> mm_interconnect_1:hps_0_f2h_axi_slave_rresp
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_awid; // mm_interconnect_1:hps_0_f2h_axi_slave_awid -> hps_0:f2h_AWID
wire [7:0] mm_interconnect_1_hps_0_f2h_axi_slave_bid; // hps_0:f2h_BID -> mm_interconnect_1:hps_0_f2h_axi_slave_bid
wire mm_interconnect_1_hps_0_f2h_axi_slave_bvalid; // hps_0:f2h_BVALID -> mm_interconnect_1:hps_0_f2h_axi_slave_bvalid
wire [2:0] mm_interconnect_1_hps_0_f2h_axi_slave_awsize; // mm_interconnect_1:hps_0_f2h_axi_slave_awsize -> hps_0:f2h_AWSIZE
wire mm_interconnect_1_hps_0_f2h_axi_slave_awvalid; // mm_interconnect_1:hps_0_f2h_axi_slave_awvalid -> hps_0:f2h_AWVALID
wire [4:0] mm_interconnect_1_hps_0_f2h_axi_slave_aruser; // mm_interconnect_1:hps_0_f2h_axi_slave_aruser -> hps_0:f2h_ARUSER
wire mm_interconnect_1_hps_0_f2h_axi_slave_rvalid; // hps_0:f2h_RVALID -> mm_interconnect_1:hps_0_f2h_axi_slave_rvalid
wire [31:0] hps_0_f2h_irq0_irq; // irq_mapper:sender_irq -> hps_0:f2h_irq_p0
wire [31:0] hps_0_f2h_irq1_irq; // irq_mapper_001:sender_irq -> hps_0:f2h_irq_p1
wire [31:0] intr_capturer_0_interrupt_receiver_irq; // irq_mapper_002:sender_irq -> intr_capturer_0:interrupt_in
wire irq_mapper_receiver0_irq; // jtag_uart:av_irq -> [irq_mapper:receiver0_irq, irq_mapper_002:receiver0_irq]
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [intr_capturer_0:rst_n, irq_mapper_002:reset, jtag_uart:rst_n, mm_interconnect_0:fpga_only_master_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_0:onchip_memory2_0_reset1_reset_bridge_in_reset_reset, mm_interconnect_1:hps_only_master_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:hps_only_master_master_translator_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, pio_led:reset_n, rst_translator:in_reset, sysid_qsys:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [onchip_memory2_0:reset_req, rst_translator:reset_req_in]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [mm_interconnect_0:hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset]
soc_system_fpga_only_master #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) fpga_only_master (
.clk_clk (clk_clk), // clk.clk
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
.master_address (fpga_only_master_master_address), // master.address
.master_readdata (fpga_only_master_master_readdata), // .readdata
.master_read (fpga_only_master_master_read), // .read
.master_write (fpga_only_master_master_write), // .write
.master_writedata (fpga_only_master_master_writedata), // .writedata
.master_waitrequest (fpga_only_master_master_waitrequest), // .waitrequest
.master_readdatavalid (fpga_only_master_master_readdatavalid), // .readdatavalid
.master_byteenable (fpga_only_master_master_byteenable), // .byteenable
.master_reset_reset () // master_reset.reset
);
soc_system_hps_0 #(
.F2S_Width (3),
.S2F_Width (2)
) hps_0 (
.f2h_cold_rst_req_n (hps_0_f2h_cold_reset_req_reset_n), // f2h_cold_reset_req.reset_n
.f2h_dbg_rst_req_n (hps_0_f2h_debug_reset_req_reset_n), // f2h_debug_reset_req.reset_n
.f2h_warm_rst_req_n (hps_0_f2h_warm_reset_req_reset_n), // f2h_warm_reset_req.reset_n
.f2h_stm_hwevents (hps_0_f2h_stm_hw_events_stm_hwevents), // f2h_stm_hw_events.stm_hwevents
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_0_hps_io_hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_0_hps_io_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_0_hps_io_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_0_hps_io_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_0_hps_io_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_0_hps_io_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_0_hps_io_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_0_hps_io_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_0_hps_io_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_0_hps_io_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_0_hps_io_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_0_hps_io_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_0_hps_io_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_0_hps_io_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (hps_0_hps_io_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_0_hps_io_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_0_hps_io_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_0_hps_io_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_0_hps_io_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_0_hps_io_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_0_hps_io_hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_0_hps_io_hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_0_hps_io_hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_0_hps_io_hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_0_hps_io_hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_0_hps_io_hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_0_hps_io_hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_0_hps_io_hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_0_hps_io_hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_0_hps_io_hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_0_hps_io_hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_0_hps_io_hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_0_hps_io_hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_0_hps_io_hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_0_hps_io_hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_0_hps_io_hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_0_hps_io_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_0_hps_io_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_0_hps_io_hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_0_hps_io_hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_0_hps_io_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_0_hps_io_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_0_hps_io_hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_0_hps_io_hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_0_hps_io_hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO53 (hps_0_hps_io_hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_0_hps_io_hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_0_hps_io_hps_io_gpio_inst_GPIO61), // .hps_io_gpio_inst_GPIO61
.h2f_rst_n (hps_0_h2f_reset_reset_n), // h2f_reset.reset_n
.h2f_axi_clk (clk_clk), // h2f_axi_clock.clk
.h2f_AWID (hps_0_h2f_axi_master_awid), // h2f_axi_master.awid
.h2f_AWADDR (hps_0_h2f_axi_master_awaddr), // .awaddr
.h2f_AWLEN (hps_0_h2f_axi_master_awlen), // .awlen
.h2f_AWSIZE (hps_0_h2f_axi_master_awsize), // .awsize
.h2f_AWBURST (hps_0_h2f_axi_master_awburst), // .awburst
.h2f_AWLOCK (hps_0_h2f_axi_master_awlock), // .awlock
.h2f_AWCACHE (hps_0_h2f_axi_master_awcache), // .awcache
.h2f_AWPROT (hps_0_h2f_axi_master_awprot), // .awprot
.h2f_AWVALID (hps_0_h2f_axi_master_awvalid), // .awvalid
.h2f_AWREADY (hps_0_h2f_axi_master_awready), // .awready
.h2f_WID (hps_0_h2f_axi_master_wid), // .wid
.h2f_WDATA (hps_0_h2f_axi_master_wdata), // .wdata
.h2f_WSTRB (hps_0_h2f_axi_master_wstrb), // .wstrb
.h2f_WLAST (hps_0_h2f_axi_master_wlast), // .wlast
.h2f_WVALID (hps_0_h2f_axi_master_wvalid), // .wvalid
.h2f_WREADY (hps_0_h2f_axi_master_wready), // .wready
.h2f_BID (hps_0_h2f_axi_master_bid), // .bid
.h2f_BRESP (hps_0_h2f_axi_master_bresp), // .bresp
.h2f_BVALID (hps_0_h2f_axi_master_bvalid), // .bvalid
.h2f_BREADY (hps_0_h2f_axi_master_bready), // .bready
.h2f_ARID (hps_0_h2f_axi_master_arid), // .arid
.h2f_ARADDR (hps_0_h2f_axi_master_araddr), // .araddr
.h2f_ARLEN (hps_0_h2f_axi_master_arlen), // .arlen
.h2f_ARSIZE (hps_0_h2f_axi_master_arsize), // .arsize
.h2f_ARBURST (hps_0_h2f_axi_master_arburst), // .arburst
.h2f_ARLOCK (hps_0_h2f_axi_master_arlock), // .arlock
.h2f_ARCACHE (hps_0_h2f_axi_master_arcache), // .arcache
.h2f_ARPROT (hps_0_h2f_axi_master_arprot), // .arprot
.h2f_ARVALID (hps_0_h2f_axi_master_arvalid), // .arvalid
.h2f_ARREADY (hps_0_h2f_axi_master_arready), // .arready
.h2f_RID (hps_0_h2f_axi_master_rid), // .rid
.h2f_RDATA (hps_0_h2f_axi_master_rdata), // .rdata
.h2f_RRESP (hps_0_h2f_axi_master_rresp), // .rresp
.h2f_RLAST (hps_0_h2f_axi_master_rlast), // .rlast
.h2f_RVALID (hps_0_h2f_axi_master_rvalid), // .rvalid
.h2f_RREADY (hps_0_h2f_axi_master_rready), // .rready
.f2h_axi_clk (clk_clk), // f2h_axi_clock.clk
.f2h_AWID (mm_interconnect_1_hps_0_f2h_axi_slave_awid), // f2h_axi_slave.awid
.f2h_AWADDR (mm_interconnect_1_hps_0_f2h_axi_slave_awaddr), // .awaddr
.f2h_AWLEN (mm_interconnect_1_hps_0_f2h_axi_slave_awlen), // .awlen
.f2h_AWSIZE (mm_interconnect_1_hps_0_f2h_axi_slave_awsize), // .awsize
.f2h_AWBURST (mm_interconnect_1_hps_0_f2h_axi_slave_awburst), // .awburst
.f2h_AWLOCK (mm_interconnect_1_hps_0_f2h_axi_slave_awlock), // .awlock
.f2h_AWCACHE (mm_interconnect_1_hps_0_f2h_axi_slave_awcache), // .awcache
.f2h_AWPROT (mm_interconnect_1_hps_0_f2h_axi_slave_awprot), // .awprot
.f2h_AWVALID (mm_interconnect_1_hps_0_f2h_axi_slave_awvalid), // .awvalid
.f2h_AWREADY (mm_interconnect_1_hps_0_f2h_axi_slave_awready), // .awready
.f2h_AWUSER (mm_interconnect_1_hps_0_f2h_axi_slave_awuser), // .awuser
.f2h_WID (mm_interconnect_1_hps_0_f2h_axi_slave_wid), // .wid
.f2h_WDATA (mm_interconnect_1_hps_0_f2h_axi_slave_wdata), // .wdata
.f2h_WSTRB (mm_interconnect_1_hps_0_f2h_axi_slave_wstrb), // .wstrb
.f2h_WLAST (mm_interconnect_1_hps_0_f2h_axi_slave_wlast), // .wlast
.f2h_WVALID (mm_interconnect_1_hps_0_f2h_axi_slave_wvalid), // .wvalid
.f2h_WREADY (mm_interconnect_1_hps_0_f2h_axi_slave_wready), // .wready
.f2h_BID (mm_interconnect_1_hps_0_f2h_axi_slave_bid), // .bid
.f2h_BRESP (mm_interconnect_1_hps_0_f2h_axi_slave_bresp), // .bresp
.f2h_BVALID (mm_interconnect_1_hps_0_f2h_axi_slave_bvalid), // .bvalid
.f2h_BREADY (mm_interconnect_1_hps_0_f2h_axi_slave_bready), // .bready
.f2h_ARID (mm_interconnect_1_hps_0_f2h_axi_slave_arid), // .arid
.f2h_ARADDR (mm_interconnect_1_hps_0_f2h_axi_slave_araddr), // .araddr
.f2h_ARLEN (mm_interconnect_1_hps_0_f2h_axi_slave_arlen), // .arlen
.f2h_ARSIZE (mm_interconnect_1_hps_0_f2h_axi_slave_arsize), // .arsize
.f2h_ARBURST (mm_interconnect_1_hps_0_f2h_axi_slave_arburst), // .arburst
.f2h_ARLOCK (mm_interconnect_1_hps_0_f2h_axi_slave_arlock), // .arlock
.f2h_ARCACHE (mm_interconnect_1_hps_0_f2h_axi_slave_arcache), // .arcache
.f2h_ARPROT (mm_interconnect_1_hps_0_f2h_axi_slave_arprot), // .arprot
.f2h_ARVALID (mm_interconnect_1_hps_0_f2h_axi_slave_arvalid), // .arvalid
.f2h_ARREADY (mm_interconnect_1_hps_0_f2h_axi_slave_arready), // .arready
.f2h_ARUSER (mm_interconnect_1_hps_0_f2h_axi_slave_aruser), // .aruser
.f2h_RID (mm_interconnect_1_hps_0_f2h_axi_slave_rid), // .rid
.f2h_RDATA (mm_interconnect_1_hps_0_f2h_axi_slave_rdata), // .rdata
.f2h_RRESP (mm_interconnect_1_hps_0_f2h_axi_slave_rresp), // .rresp
.f2h_RLAST (mm_interconnect_1_hps_0_f2h_axi_slave_rlast), // .rlast
.f2h_RVALID (mm_interconnect_1_hps_0_f2h_axi_slave_rvalid), // .rvalid
.f2h_RREADY (mm_interconnect_1_hps_0_f2h_axi_slave_rready), // .rready
.h2f_lw_axi_clk (clk_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (hps_0_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (hps_0_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (hps_0_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (hps_0_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (hps_0_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (hps_0_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (hps_0_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (hps_0_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (hps_0_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (hps_0_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (hps_0_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (hps_0_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (hps_0_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (hps_0_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (hps_0_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (hps_0_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (hps_0_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (hps_0_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (hps_0_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (hps_0_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (hps_0_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (hps_0_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (hps_0_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (hps_0_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (hps_0_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (hps_0_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (hps_0_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (hps_0_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (hps_0_h2f_lw_axi_master_rready), // .rready
.f2h_irq_p0 (hps_0_f2h_irq0_irq), // f2h_irq0.irq
.f2h_irq_p1 (hps_0_f2h_irq1_irq) // f2h_irq1.irq
);
soc_system_fpga_only_master #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) hps_only_master (
.clk_clk (clk_clk), // clk.clk
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
.master_address (hps_only_master_master_address), // master.address
.master_readdata (hps_only_master_master_readdata), // .readdata
.master_read (hps_only_master_master_read), // .read
.master_write (hps_only_master_master_write), // .write
.master_writedata (hps_only_master_master_writedata), // .writedata
.master_waitrequest (hps_only_master_master_waitrequest), // .waitrequest
.master_readdatavalid (hps_only_master_master_readdatavalid), // .readdatavalid
.master_byteenable (hps_only_master_master_byteenable), // .byteenable
.master_reset_reset () // master_reset.reset
);
intr_capturer #(
.NUM_INTR (32)
) intr_capturer_0 (
.clk (clk_clk), // clock.clk
.rst_n (~rst_controller_reset_out_reset), // reset_sink.reset_n
.addr (mm_interconnect_0_intr_capturer_0_avalon_slave_0_address), // avalon_slave_0.address
.read (mm_interconnect_0_intr_capturer_0_avalon_slave_0_read), // .read
.rddata (mm_interconnect_0_intr_capturer_0_avalon_slave_0_readdata), // .readdata
.interrupt_in (intr_capturer_0_interrupt_receiver_irq) // interrupt_receiver.irq
);
soc_system_jtag_uart jtag_uart (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver0_irq) // irq.irq
);
soc_system_onchip_memory2_0 onchip_memory2_0 (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
soc_system_pio_led pio_led (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_pio_led_s1_address), // s1.address
.write_n (~mm_interconnect_0_pio_led_s1_write), // .write_n
.writedata (mm_interconnect_0_pio_led_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_pio_led_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_pio_led_s1_readdata), // .readdata
.out_port (pio_led_external_connection_export) // external_connection.export
);
soc_system_sysid_qsys sysid_qsys (
.clock (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.readdata (mm_interconnect_0_sysid_qsys_control_slave_readdata), // control_slave.readdata
.address (mm_interconnect_0_sysid_qsys_control_slave_address) // .address
);
soc_system_mm_interconnect_0 mm_interconnect_0 (
.hps_0_h2f_axi_master_awid (hps_0_h2f_axi_master_awid), // hps_0_h2f_axi_master.awid
.hps_0_h2f_axi_master_awaddr (hps_0_h2f_axi_master_awaddr), // .awaddr
.hps_0_h2f_axi_master_awlen (hps_0_h2f_axi_master_awlen), // .awlen
.hps_0_h2f_axi_master_awsize (hps_0_h2f_axi_master_awsize), // .awsize
.hps_0_h2f_axi_master_awburst (hps_0_h2f_axi_master_awburst), // .awburst
.hps_0_h2f_axi_master_awlock (hps_0_h2f_axi_master_awlock), // .awlock
.hps_0_h2f_axi_master_awcache (hps_0_h2f_axi_master_awcache), // .awcache
.hps_0_h2f_axi_master_awprot (hps_0_h2f_axi_master_awprot), // .awprot
.hps_0_h2f_axi_master_awvalid (hps_0_h2f_axi_master_awvalid), // .awvalid
.hps_0_h2f_axi_master_awready (hps_0_h2f_axi_master_awready), // .awready
.hps_0_h2f_axi_master_wid (hps_0_h2f_axi_master_wid), // .wid
.hps_0_h2f_axi_master_wdata (hps_0_h2f_axi_master_wdata), // .wdata
.hps_0_h2f_axi_master_wstrb (hps_0_h2f_axi_master_wstrb), // .wstrb
.hps_0_h2f_axi_master_wlast (hps_0_h2f_axi_master_wlast), // .wlast
.hps_0_h2f_axi_master_wvalid (hps_0_h2f_axi_master_wvalid), // .wvalid
.hps_0_h2f_axi_master_wready (hps_0_h2f_axi_master_wready), // .wready
.hps_0_h2f_axi_master_bid (hps_0_h2f_axi_master_bid), // .bid
.hps_0_h2f_axi_master_bresp (hps_0_h2f_axi_master_bresp), // .bresp
.hps_0_h2f_axi_master_bvalid (hps_0_h2f_axi_master_bvalid), // .bvalid
.hps_0_h2f_axi_master_bready (hps_0_h2f_axi_master_bready), // .bready
.hps_0_h2f_axi_master_arid (hps_0_h2f_axi_master_arid), // .arid
.hps_0_h2f_axi_master_araddr (hps_0_h2f_axi_master_araddr), // .araddr
.hps_0_h2f_axi_master_arlen (hps_0_h2f_axi_master_arlen), // .arlen
.hps_0_h2f_axi_master_arsize (hps_0_h2f_axi_master_arsize), // .arsize
.hps_0_h2f_axi_master_arburst (hps_0_h2f_axi_master_arburst), // .arburst
.hps_0_h2f_axi_master_arlock (hps_0_h2f_axi_master_arlock), // .arlock
.hps_0_h2f_axi_master_arcache (hps_0_h2f_axi_master_arcache), // .arcache
.hps_0_h2f_axi_master_arprot (hps_0_h2f_axi_master_arprot), // .arprot
.hps_0_h2f_axi_master_arvalid (hps_0_h2f_axi_master_arvalid), // .arvalid
.hps_0_h2f_axi_master_arready (hps_0_h2f_axi_master_arready), // .arready
.hps_0_h2f_axi_master_rid (hps_0_h2f_axi_master_rid), // .rid
.hps_0_h2f_axi_master_rdata (hps_0_h2f_axi_master_rdata), // .rdata
.hps_0_h2f_axi_master_rresp (hps_0_h2f_axi_master_rresp), // .rresp
.hps_0_h2f_axi_master_rlast (hps_0_h2f_axi_master_rlast), // .rlast
.hps_0_h2f_axi_master_rvalid (hps_0_h2f_axi_master_rvalid), // .rvalid
.hps_0_h2f_axi_master_rready (hps_0_h2f_axi_master_rready), // .rready
.hps_0_h2f_lw_axi_master_awid (hps_0_h2f_lw_axi_master_awid), // hps_0_h2f_lw_axi_master.awid
.hps_0_h2f_lw_axi_master_awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.hps_0_h2f_lw_axi_master_awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.hps_0_h2f_lw_axi_master_awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.hps_0_h2f_lw_axi_master_awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.hps_0_h2f_lw_axi_master_awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.hps_0_h2f_lw_axi_master_awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.hps_0_h2f_lw_axi_master_awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.hps_0_h2f_lw_axi_master_awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.hps_0_h2f_lw_axi_master_awready (hps_0_h2f_lw_axi_master_awready), // .awready
.hps_0_h2f_lw_axi_master_wid (hps_0_h2f_lw_axi_master_wid), // .wid
.hps_0_h2f_lw_axi_master_wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.hps_0_h2f_lw_axi_master_wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.hps_0_h2f_lw_axi_master_wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.hps_0_h2f_lw_axi_master_wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.hps_0_h2f_lw_axi_master_wready (hps_0_h2f_lw_axi_master_wready), // .wready
.hps_0_h2f_lw_axi_master_bid (hps_0_h2f_lw_axi_master_bid), // .bid
.hps_0_h2f_lw_axi_master_bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.hps_0_h2f_lw_axi_master_bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.hps_0_h2f_lw_axi_master_bready (hps_0_h2f_lw_axi_master_bready), // .bready
.hps_0_h2f_lw_axi_master_arid (hps_0_h2f_lw_axi_master_arid), // .arid
.hps_0_h2f_lw_axi_master_araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.hps_0_h2f_lw_axi_master_arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.hps_0_h2f_lw_axi_master_arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.hps_0_h2f_lw_axi_master_arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.hps_0_h2f_lw_axi_master_arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.hps_0_h2f_lw_axi_master_arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.hps_0_h2f_lw_axi_master_arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.hps_0_h2f_lw_axi_master_arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.hps_0_h2f_lw_axi_master_arready (hps_0_h2f_lw_axi_master_arready), // .arready
.hps_0_h2f_lw_axi_master_rid (hps_0_h2f_lw_axi_master_rid), // .rid
.hps_0_h2f_lw_axi_master_rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.hps_0_h2f_lw_axi_master_rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.hps_0_h2f_lw_axi_master_rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.hps_0_h2f_lw_axi_master_rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.hps_0_h2f_lw_axi_master_rready (hps_0_h2f_lw_axi_master_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.fpga_only_master_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // fpga_only_master_clk_reset_reset_bridge_in_reset.reset
.hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // hps_0_h2f_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.onchip_memory2_0_reset1_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // onchip_memory2_0_reset1_reset_bridge_in_reset.reset
.fpga_only_master_master_address (fpga_only_master_master_address), // fpga_only_master_master.address
.fpga_only_master_master_waitrequest (fpga_only_master_master_waitrequest), // .waitrequest
.fpga_only_master_master_byteenable (fpga_only_master_master_byteenable), // .byteenable
.fpga_only_master_master_read (fpga_only_master_master_read), // .read
.fpga_only_master_master_readdata (fpga_only_master_master_readdata), // .readdata
.fpga_only_master_master_readdatavalid (fpga_only_master_master_readdatavalid), // .readdatavalid
.fpga_only_master_master_write (fpga_only_master_master_write), // .write
.fpga_only_master_master_writedata (fpga_only_master_master_writedata), // .writedata
.intr_capturer_0_avalon_slave_0_address (mm_interconnect_0_intr_capturer_0_avalon_slave_0_address), // intr_capturer_0_avalon_slave_0.address
.intr_capturer_0_avalon_slave_0_read (mm_interconnect_0_intr_capturer_0_avalon_slave_0_read), // .read
.intr_capturer_0_avalon_slave_0_readdata (mm_interconnect_0_intr_capturer_0_avalon_slave_0_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address
.jtag_uart_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write
.jtag_uart_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read
.jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.pio_led_s1_address (mm_interconnect_0_pio_led_s1_address), // pio_led_s1.address
.pio_led_s1_write (mm_interconnect_0_pio_led_s1_write), // .write
.pio_led_s1_readdata (mm_interconnect_0_pio_led_s1_readdata), // .readdata
.pio_led_s1_writedata (mm_interconnect_0_pio_led_s1_writedata), // .writedata
.pio_led_s1_chipselect (mm_interconnect_0_pio_led_s1_chipselect), // .chipselect
.sysid_qsys_control_slave_address (mm_interconnect_0_sysid_qsys_control_slave_address), // sysid_qsys_control_slave.address
.sysid_qsys_control_slave_readdata (mm_interconnect_0_sysid_qsys_control_slave_readdata) // .readdata
);
soc_system_mm_interconnect_1 mm_interconnect_1 (
.hps_0_f2h_axi_slave_awid (mm_interconnect_1_hps_0_f2h_axi_slave_awid), // hps_0_f2h_axi_slave.awid
.hps_0_f2h_axi_slave_awaddr (mm_interconnect_1_hps_0_f2h_axi_slave_awaddr), // .awaddr
.hps_0_f2h_axi_slave_awlen (mm_interconnect_1_hps_0_f2h_axi_slave_awlen), // .awlen
.hps_0_f2h_axi_slave_awsize (mm_interconnect_1_hps_0_f2h_axi_slave_awsize), // .awsize
.hps_0_f2h_axi_slave_awburst (mm_interconnect_1_hps_0_f2h_axi_slave_awburst), // .awburst
.hps_0_f2h_axi_slave_awlock (mm_interconnect_1_hps_0_f2h_axi_slave_awlock), // .awlock
.hps_0_f2h_axi_slave_awcache (mm_interconnect_1_hps_0_f2h_axi_slave_awcache), // .awcache
.hps_0_f2h_axi_slave_awprot (mm_interconnect_1_hps_0_f2h_axi_slave_awprot), // .awprot
.hps_0_f2h_axi_slave_awuser (mm_interconnect_1_hps_0_f2h_axi_slave_awuser), // .awuser
.hps_0_f2h_axi_slave_awvalid (mm_interconnect_1_hps_0_f2h_axi_slave_awvalid), // .awvalid
.hps_0_f2h_axi_slave_awready (mm_interconnect_1_hps_0_f2h_axi_slave_awready), // .awready
.hps_0_f2h_axi_slave_wid (mm_interconnect_1_hps_0_f2h_axi_slave_wid), // .wid
.hps_0_f2h_axi_slave_wdata (mm_interconnect_1_hps_0_f2h_axi_slave_wdata), // .wdata
.hps_0_f2h_axi_slave_wstrb (mm_interconnect_1_hps_0_f2h_axi_slave_wstrb), // .wstrb
.hps_0_f2h_axi_slave_wlast (mm_interconnect_1_hps_0_f2h_axi_slave_wlast), // .wlast
.hps_0_f2h_axi_slave_wvalid (mm_interconnect_1_hps_0_f2h_axi_slave_wvalid), // .wvalid
.hps_0_f2h_axi_slave_wready (mm_interconnect_1_hps_0_f2h_axi_slave_wready), // .wready
.hps_0_f2h_axi_slave_bid (mm_interconnect_1_hps_0_f2h_axi_slave_bid), // .bid
.hps_0_f2h_axi_slave_bresp (mm_interconnect_1_hps_0_f2h_axi_slave_bresp), // .bresp
.hps_0_f2h_axi_slave_bvalid (mm_interconnect_1_hps_0_f2h_axi_slave_bvalid), // .bvalid
.hps_0_f2h_axi_slave_bready (mm_interconnect_1_hps_0_f2h_axi_slave_bready), // .bready
.hps_0_f2h_axi_slave_arid (mm_interconnect_1_hps_0_f2h_axi_slave_arid), // .arid
.hps_0_f2h_axi_slave_araddr (mm_interconnect_1_hps_0_f2h_axi_slave_araddr), // .araddr
.hps_0_f2h_axi_slave_arlen (mm_interconnect_1_hps_0_f2h_axi_slave_arlen), // .arlen
.hps_0_f2h_axi_slave_arsize (mm_interconnect_1_hps_0_f2h_axi_slave_arsize), // .arsize
.hps_0_f2h_axi_slave_arburst (mm_interconnect_1_hps_0_f2h_axi_slave_arburst), // .arburst
.hps_0_f2h_axi_slave_arlock (mm_interconnect_1_hps_0_f2h_axi_slave_arlock), // .arlock
.hps_0_f2h_axi_slave_arcache (mm_interconnect_1_hps_0_f2h_axi_slave_arcache), // .arcache
.hps_0_f2h_axi_slave_arprot (mm_interconnect_1_hps_0_f2h_axi_slave_arprot), // .arprot
.hps_0_f2h_axi_slave_aruser (mm_interconnect_1_hps_0_f2h_axi_slave_aruser), // .aruser
.hps_0_f2h_axi_slave_arvalid (mm_interconnect_1_hps_0_f2h_axi_slave_arvalid), // .arvalid
.hps_0_f2h_axi_slave_arready (mm_interconnect_1_hps_0_f2h_axi_slave_arready), // .arready
.hps_0_f2h_axi_slave_rid (mm_interconnect_1_hps_0_f2h_axi_slave_rid), // .rid
.hps_0_f2h_axi_slave_rdata (mm_interconnect_1_hps_0_f2h_axi_slave_rdata), // .rdata
.hps_0_f2h_axi_slave_rresp (mm_interconnect_1_hps_0_f2h_axi_slave_rresp), // .rresp
.hps_0_f2h_axi_slave_rlast (mm_interconnect_1_hps_0_f2h_axi_slave_rlast), // .rlast
.hps_0_f2h_axi_slave_rvalid (mm_interconnect_1_hps_0_f2h_axi_slave_rvalid), // .rvalid
.hps_0_f2h_axi_slave_rready (mm_interconnect_1_hps_0_f2h_axi_slave_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset.reset
.hps_only_master_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // hps_only_master_clk_reset_reset_bridge_in_reset.reset
.hps_only_master_master_translator_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // hps_only_master_master_translator_reset_reset_bridge_in_reset.reset
.hps_only_master_master_address (hps_only_master_master_address), // hps_only_master_master.address
.hps_only_master_master_waitrequest (hps_only_master_master_waitrequest), // .waitrequest
.hps_only_master_master_byteenable (hps_only_master_master_byteenable), // .byteenable
.hps_only_master_master_read (hps_only_master_master_read), // .read
.hps_only_master_master_readdata (hps_only_master_master_readdata), // .readdata
.hps_only_master_master_readdatavalid (hps_only_master_master_readdatavalid), // .readdatavalid
.hps_only_master_master_write (hps_only_master_master_write), // .write
.hps_only_master_master_writedata (hps_only_master_master_writedata) // .writedata
);
soc_system_irq_mapper irq_mapper (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (hps_0_f2h_irq0_irq) // sender.irq
);
soc_system_irq_mapper_001 irq_mapper_001 (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.sender_irq (hps_0_f2h_irq1_irq) // sender.irq
);
soc_system_irq_mapper irq_mapper_002 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (intr_capturer_0_interrupt_receiver_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~hps_0_h2f_reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: tes_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module tes_pll (
areset,
inclk0,
c0,
c1,
c2,
c3,
c4);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output c3;
output c4;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "50.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "tes_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tes_pll_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*this module will let us set an initial time for the main clock to run
will also let us record the meal time the user gives
second2 and second1 will be defaulted to 0
if statements compare to one less than the limiting value b/c display time will instantly display the current value*/
module set_time (add, set_hour, set_minute, hour2, hour1, minute2, minute1, second2, second1);
input add, set_hour, set_minute;
output reg [3:0] hour2, hour1, minute2, minute1, second2, second1;
always @(posedge add)
begin
if(set_minute & ~set_hour)
begin
minute1 <= minute1 + 1;
if (minute1 > 8)
begin
minute2 <= minute2 + 1;
minute1 <= 0;
end
if (minute2 > 5)
minute2 <= 0;
//deal with transition from 59 to 00 separately
if((minute2 == 5)&(minute1 == 9))
begin
minute2 <= 0;
minute1 <= 0;
end
end
else if (~set_minute & set_hour)
begin
hour1 <= hour1 + 1;
if (hour1 > 8)
begin
hour2 <= hour2 + 1;
hour1 <= 0;
end
if (hour2 == 2)
//deal with transition from 23 to 00 separately
if (hour1 > 2)
begin
hour2 <= 0;
hour1 <= 0;
end
end
else ;
end
endmodule |
/************************
* Willard Wider
* 6-29-17
* ELEC3725
* cpu4.v
* building a 32 bit CPU
************************/
//cpu4 dut(.clk(clk),.ibus(ibus),.daddrbus(daddrbus),.databus(databus));
module cpu4(ibus,clk,daddrbus,databus);
//just a clock
input clk;
//the new bus things
output [31:0] daddrbus;
inout [31:0] databus;
//decoder tings
wire [5:0] opCode;//from IF_ID
wire [5:0] funktion;//from IF_ID
//ibus
input [31:0] ibus;//in for IF_ID
wire [31:0] ibusWire;//out for IF_ID
//Aselect
wire [31:0] AselectWire;//from rs, to regfile
wire [5:0] rs;//from ibusWire, to AselectWire
//Bselect
wire [31:0] BselectWire;//from rt, to regfile
wire [5:0] rt;//from ibsuWire, to BselectWire and mxu1
//imm select
reg immBit1;//from IF_ID(ibusWire), to mux1 and ID_EX
wire immBit2;//from ID_EX, to mux2
//load word save word flag
reg [1:0] lwSwFlag1;//from IF_ID, to ID_EX
wire [1:0] lwSwFlag2;//from ID_EX, to EX_MEM
wire [1:0] lwSwFlag3;//from EX_MEM, to MEM_WB
wire [1:0] lwSwFlag4;//from MEM_WB, to mux3
//Dselect
wire [31:0] DselectWire1;//from muxOut, to ID_EX
wire [5:0] rd;//from ID_EX, to mux1
wire [31:0] DselectWire2;//from ID_EX, to EX_MM
wire [31:0] DselectWire3;//from EX_MEM, to MEM_WB
wire [31:0] DselectWire3_5;//from MEM_WB, to mux3
wire [31:0] DselectWire4;//from mux3, to regfile
//abus
//output [31:0] abus;//from ID_EX, to SIM_OUT
wire [31:0] abusWire1;//from regOut, to ID_EX
wire [31:0] abusWire2;//from ID_EX, to ALU
//bbus
//output [31:0] bbus;//from mux2Out, to SIM_OUT
wire [31:0] bbusWire1;//from regOut, to ID_EX
wire [31:0] bbusWire2;//from ID_EX, to mux2/EX_MEM
wire [31:0] bbusWire3;//from EX_MEM, to memory logic
wire [31:0] bbusWire3_5;//from memory logic, to MEM_WB
wire [31:0] bbusWire4;//from MEM_WB, to mux3
//dbus
//output [31:0] dbus;//from EX_MEM, to SIM_OUT
wire [31:0] dbusWire1;//from ALU, to EX_MEM
wire [31:0] dbusWire2;//from EM_MEM, to MEM_WB
wire [31:0] dbusWire3;//from MEM_WB, to mux3
//mux3
wire [31:0] mux3Out;//from dbusWire3/bbusWire4, to regfile
//mux2
wire [31:0] mux2Out;//from bbusWire2/immWire2, to ALU
//immediate
wire [31:0] immWire1;//from IF_ID, to ID_EX
wire [31:0] immWire2;//from ID_EX, to mux2
//S
reg [2:0] SWire1;//from IF_ID, to ID_EX
wire [2:0] SWire2;//from ID_EX, to ALU
//Cin
reg CinWire1;//from IF_ID, to ID_EX
wire CinWire2;//form ID_EX, to ALU
//init
initial begin
immBit1 = 1'bx;
CinWire1 = 1'bx;
SWire1 = 3'bxxx;
lwSwFlag1 = 2'bxx;
end
//latch for pipeline 1(IF_ID)
//module pipeline_1_latch(clk, ibus, ibusWire);
pipeline_1_latch IF_ID(.clk(clk),.ibus(ibus),.ibusWire(ibusWire));
//PIPELINE_1_START
//decode the input command
assign opCode = ibusWire[31:26];
assign rs = ibusWire[25:21];
assign rt = ibusWire[20:16];
assign rd = ibusWire[15:11];
assign funktion = ibusWire[5:0];
assign immWire1 = ibusWire[15]? {16'b1111111111111111,ibusWire[15:0]} : {16'b0000000000000000,ibusWire[15:0]};
//for the change in the opcode which is like always
always @(ibusWire) begin
//first mux value is to assume 0
immBit1 = 1;
CinWire1 = 0;
//assume not doing anything with the load or save
lwSwFlag1 = 2'b00;
//write the cases for the opcode (immediate)
case (opCode)
6'b000011: begin
//addi
SWire1 = 3'b010;
end
6'b000010: begin
//subi
SWire1 = 3'b011;
CinWire1 = 1;
end
6'b000001: begin
//xori
SWire1 = 3'b000;
end
6'b001111: begin
//andi
SWire1 = 3'b110;
end
6'b001100: begin
//ori
SWire1 = 3'b100;
end
6'b011110: begin
//load word, but still addi
SWire1 = 3'b010;
lwSwFlag1 = 2'b01;
end
6'b011111: begin
//store word, but still addi
SWire1 = 3'b010;
lwSwFlag1 = 2'b10;
end
//if 00000
6'b000000: begin
//write the mux value here
immBit1= 0;
//then write the cases for the funct
case (funktion)
6'b000011: begin
//add
SWire1 = 3'b010;
end
6'b000010: begin
//sub
SWire1 = 3'b011;
CinWire1 = 1;
end
6'b000001: begin
//xor
SWire1 = 3'b000;
end
6'b000111: begin
//and
SWire1 = 3'b110;
end
6'b000100: begin
//or
SWire1 = 3'b100;
end
endcase
end
endcase
end
//write the select lines
assign AselectWire = 1 << rs;
//only write to Bselect for real if it's actually goign to use Bselect
//i don't think this line matters but i feel like it's good pratice
//assign BselectWire = immBit1? 32'hxxxxxxxx: 1 << rt;
assign BselectWire = 1 << rt;
//mux1
//Rd for R, imm = false
//Rt for I, imm = true
assign DselectWire1 = immBit1? 1<<rt : 1<<rd;
/*
module regfile(
input [31:0] Aselect,//select the register index to read from to store into abus
input [31:0] Bselect,//select the register index to read from to store into bbus
input [31:0] Dselect,//select the register to write to from dbus
input [31:0] dbus,//data in
output [31:0] abus,//data out
output [31:0] bbus,//data out
input clk
);
*/
regfile Reggie3(.clk(clk),.Aselect(AselectWire),.Bselect(BselectWire),.Dselect(DselectWire4),.abus(abusWire1),.bbus(bbusWire1),.dbus(mux3Out));
//PIPELINE_1_END
//latch for pipeline 2(ID_EX)
//module pipeline_2_latch(clk, abusWire1, bbusWire1, DselectWire1, immWire1, SWire1, CinWire1,immBit1,lwSwFlag1,abusWire2,bbusWire2,immWire2,SWire2,CinWire2,DselectWire2,immBit2,lwSwFlag2);
pipeline_2_latch ED_EX(.clk(clk),.abusWire1(abusWire1),.bbusWire1(bbusWire1),.DselectWire1(DselectWire1),.immWire1(immWire1),.SWire1(SWire1),.CinWire1(CinWire1),.immBit1(immBit1),.lwSwFlag1(lwSwFlag1),.abusWire2(abusWire2),.bbusWire2(bbusWire2),.immWire2(immWire2),.CinWire2(CinWire2),.DselectWire2(DselectWire2),.immBit2(immBit2),.SWire2,.lwSwFlag2(lwSwFlag2));
//PIPELINE_2_START
//assign abus output
//assign abus = abusWire2;
//mux2
//immWire for true, Bselet for false
assign mux2Out = immBit2? immWire2: bbusWire2;
//assign bbus output
//assign bbus = mux2Out;
//make the ALU
//module alu32 (d, Cout, V, a, b, Cin, S);
alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));
//PIPELINE_2_END
//latch for pipeline 3(EX_MEM)
//module pipeline_3_latch(clk, dbusWire1, DselectWire2, bbusWire2, lwSwFlag2, dbusWire2, DselectWire3,bbusWire3,lwSwFlag3);
pipeline_3_latch EX_MEME (.clk(clk),.dbusWire1(dbusWire1),.DselectWire2(DselectWire2),.bbusWire2(bbusWire2),.lwSwFlag2(lwSwFlag2),.dbusWire2(dbusWire2),.DselectWire3(DselectWire3),.bbusWire3(bbusWire3),.lwSwFlag3(lwSwFlag3));
//PIPELINE_3_SRART
//assign output values
//try again with ternary operators
//one for the databus and one for bbusWire3
assign bbusWire3_5 = (lwSwFlag3==2'b01)? databus: bbusWire3;
assign databus = (lwSwFlag3 == 2'b10)? bbusWire3: 32'hzzzzzzzz;
/*
case(lwSwFlag3)
2'b00:begin//none,
assign databus = 32'hzzzzzzzz;
end
2'b01:begin//LOAD,
assign bbusWire3 = databus;
assign databus = 32'hzzzzzzzz;
end
2'b10:begin//SAVE/STORE,
assign databus = bbusWire3;
end
endcase
*/
assign daddrbus = dbusWire2;
//PIPELINE_3_END
//latch for pipeline 4(MEM_WB)
//module pipeline_4_latch(clk, dbusWire2, DselectWire3, bbusWire3, lwSwFlag3, dbusWire3, DselectWire4,bbusWire4,lwSwFlag4);
pipeline_4_latch MEM_WB (.clk(clk),.dbusWire2(dbusWire2),.DselectWire3(DselectWire3),.bbusWire3(bbusWire3_5),.lwSwFlag3(lwSwFlag3),.dbusWire3(dbusWire3),.DselectWire4(DselectWire3_5),.bbusWire4(bbusWire4),.lwSwFlag4(lwSwFlag4));
//PIPELINE_4_START
//the "mux" for the data writeBack
assign mux3Out = (lwSwFlag4 == 2'b01)? bbusWire4:dbusWire3;
assign DselectWire4 = (lwSwFlag4 == 2'b10)? 32'h00000001: DselectWire3_5;
/*
case(lwSwFlag4)
2'b00:begin//none, use dbus
assign mux3Out = dbusWire3;
end
2'b01:begin//LOAD, use bbus
assign mux3Out = bbusWire4;
end
2'b10:begin//STORE, use dbus
assign mux3Out = dbusWire3;
//set send mux3out to R0
assign DselectWire4 = 32'h00000001;
end
endcase
*/
//PIPELINE_4_END
endmodule
//phase 1 pipeline latch(IF_ID)
module pipeline_1_latch(clk, ibus, ibusWire);
input [31:0] ibus;
input clk;
output [31:0] ibusWire;
reg [31:0] ibusWire;
always @(posedge clk) begin
ibusWire = ibus;
end
endmodule
//phase 2 pipeline latch(ID_EX)
module pipeline_2_latch(clk, abusWire1, bbusWire1, DselectWire1, immWire1, SWire1, CinWire1,immBit1,lwSwFlag1,abusWire2,bbusWire2,immWire2,SWire2,CinWire2,DselectWire2,immBit2,lwSwFlag2);
input clk, CinWire1,immBit1;
input [31:0] abusWire1, bbusWire1, DselectWire1, immWire1;
input [2:0] SWire1;
input [1:0] lwSwFlag1;
output CinWire2,immBit2;
output [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
output [2:0] SWire2;
output [1:0] lwSwFlag2;
reg CinWire2,immBit2;
reg [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
reg [2:0] SWire2;
reg [1:0] lwSwFlag2;
always @(posedge clk) begin
abusWire2 = abusWire1;
bbusWire2 = bbusWire1;
DselectWire2 = DselectWire1;
immWire2 = immWire1;
SWire2 = SWire1;
CinWire2 = CinWire1;
immBit2 = immBit1;
lwSwFlag2 = lwSwFlag1;
end
endmodule
//phase 3 pipeliune latch(EX_MEM)
module pipeline_3_latch(clk, dbusWire1, DselectWire2, bbusWire2, lwSwFlag2, dbusWire2, DselectWire3,bbusWire3,lwSwFlag3);
input clk;
input [31:0] dbusWire1, DselectWire2, bbusWire2;
input [1:0] lwSwFlag2;
output [31:0] dbusWire2, DselectWire3, bbusWire3;
output [1:0] lwSwFlag3;
reg [31:0] dbusWire2, DselectWire3, bbusWire3;
reg [1:0] lwSwFlag3;
always @(posedge clk) begin
dbusWire2 = dbusWire1;
DselectWire3 = DselectWire2;
bbusWire3 = bbusWire2;
lwSwFlag3 = lwSwFlag2;
end
endmodule
//phase 4 pipeline latch(MEM_WB)
module pipeline_4_latch(clk, dbusWire2, DselectWire3, bbusWire3, lwSwFlag3, dbusWire3, DselectWire4,bbusWire4,lwSwFlag4);
input clk;
input [31:0] dbusWire2, DselectWire3, bbusWire3;
input [1:0] lwSwFlag3;
output [31:0] dbusWire3, DselectWire4, bbusWire4;
output [1:0] lwSwFlag4;
reg [31:0] dbusWire3, DselectWire4, bbusWire4;
reg [1:0] lwSwFlag4;
always @(posedge clk) begin
dbusWire3 = dbusWire2;
DselectWire4 = DselectWire3;
bbusWire4 = bbusWire3;
lwSwFlag4 = lwSwFlag3;
end
endmodule
module regfile(
input [31:0] Aselect,//select the register index to read from to store into abus
input [31:0] Bselect,//select the register index to read from to store into bbus
input [31:0] Dselect,//select the register to write to from dbus
input [31:0] dbus,//data in
output [31:0] abus,//data out
output [31:0] bbus,//data out
input clk
);
assign abus = Aselect[0] ? 32'b0 : 32'bz;
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
DNegflipFlop myFlips[30:0](//32 wide register
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule
module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [31:0] dbus;
input Dselect;//the select write bit for this register
input Bselect;//the select read bit for this register
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
wire wireclk;
reg [31:0] data;
assign wireclk = clk & Dselect;
initial begin
data = 32'h00000000;
end
always @(negedge clk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect? data : 32'hzzzzzzzz;
assign bbus = Bselect? data : 32'hzzzzzzzz;
endmodule
//Below this point is code from assignment 1//
//The declaration of the entire ALU itself.
module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;//the output bus
output Cout, V;//Cout is the bit for it it needs to carry over to the next circuit/ V is the overflow bit.
input [31:0] a, b;//the two input buses
input Cin;//the bit for marking if it is carrying over from a previous circuit
input [2:0] S;//The select bus. It defines the operation to do with input busses a and b
wire [31:0] c, g, p;
wire gout, pout;
//The core ALU bus
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
//the top Look-Ahead-Carry module.
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
//the overflow module
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule
//The module to handle a single bit operation for the top ALU module
module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule
//The module to handle the overflow bit
module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule
//Look-Ahead Carry unit level 1. Used for the root (level 1) and first child leafs (level 2)
module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule
//Look-Ahead Carry unit level 2. Contains LACs for the root and level 1. Used in level 3
module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 3. Contains LACs for the root and level 2. Used in level 4
module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 4. Contains LACs for the root and level 3. Used in level 5
module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
//Look-Ahead Carry unit level 1. Caontains LACs for the root and level 4. Used in the core alu32 module
module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DLXTN_FUNCTIONAL_PP_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_pg/sky130_fd_sc_hs__u_dl_p_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxtn (
VPWR ,
VGND ,
Q ,
D ,
GATE_N
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input D ;
input GATE_N;
// Local signals
wire gate buf_Q ;
wire gate GATE_N_delayed;
wire gate D_delayed ;
wire GATE ;
// Name Output Other arguments
not not0 (GATE , GATE_N );
sky130_fd_sc_hs__u_dl_p_pg u_dl_p_pg0 (buf_Q , D, GATE, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTN_FUNCTIONAL_PP_V |
`include "hglobal.v"
`default_nettype none
`define NS_DBG_NXT_ADDR(adr) ((adr >= MAX_ADDR)?(MIN_ADDR):(adr + 1))
module io_fifo
#(parameter
MIN_ADDR=1,
MAX_ADDR=1,
ASZ=`NS_ADDRESS_SIZE,
DSZ=`NS_DATA_SIZE,
RSZ=`NS_REDUN_SIZE
)(
input wire src_clk,
input wire snk_clk,
input wire reset,
// SRC_0
`NS_DECLARE_OUT_CHNL(o0),
// SNK_0
`NS_DECLARE_IN_CHNL(i0),
`NS_DECLARE_DBG_CHNL(dbg)
);
parameter RCV_REQ_CKS = `NS_REQ_CKS;
parameter SND_ACK_CKS = `NS_ACK_CKS;
`NS_DEBOUNCER_ACK(src_clk, reset, o0)
`NS_DEBOUNCER_REQ(snk_clk, reset, i0)
`NS_DECLARE_REG_DBG(rg_dbg)
reg [3:0] cnt_0 = 0;
reg [3:0] cnt_1 = 0;
// SRC regs
reg [0:0] ro0_busy = `NS_OFF;
reg [ASZ-1:0] ro0_src = 0;
reg [ASZ-1:0] ro0_dst = MIN_ADDR;
reg [DSZ-1:0] ro0_dat = 0;
reg [RSZ-1:0] ro0_red = 0;
reg [0:0] ro0_req = `NS_OFF;
reg [0:0] ro0_err = `NS_OFF;
wire [RSZ-1:0] ro0_redun;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
ro0_c_red (ro0_src, ro0_dst, ro0_dat, ro0_redun);
// SNK_0 regs
reg [0:0] ri0_cks_done = `NS_OFF;
reg [0:0] ri0_ack = `NS_OFF;
reg [DSZ-1:0] ri0_ck_dat = 0;
// CHECK regs
reg [DSZ-1:0] r_0_ck_dat = 15;
reg [DSZ-1:0] r_1_ck_dat = 15;
wire [RSZ-1:0] i0_redun;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
ri0_c_red (i0_src, i0_dst, i0_dat, i0_redun);
//SRC_0
always @(posedge src_clk)
begin
if(! ro0_busy) begin
ro0_busy <= `NS_ON;
if(ro0_dat > 15) begin
ro0_err <= `NS_ON;
end
/*if(ro0_dat < 0) begin
ro0_err <= `NS_ON;
end*/
ro0_dat[3:0] <= cnt_0;
cnt_0 <= cnt_0 + 1;
end
if(ro0_busy) begin
if((! ro0_req) && (! o0_ckd_ack)) begin
ro0_red <= ro0_redun;
ro0_req <= `NS_ON;
end
if(ro0_req && o0_ckd_ack) begin
ro0_dst <= `NS_DBG_NXT_ADDR(ro0_dst);
ro0_busy <= `NS_OFF;
ro0_req <= `NS_OFF;
end
end
end
//SNK_0
always @(posedge snk_clk)
begin
//rg_dbg_leds[3:3] <= 1;
if(! ri0_cks_done && i0_ckd_req && (! ri0_ack)) begin
if(! rg_dbg_leds[2:2]) begin
if(i0_dat > 15) begin
rg_dbg_leds[2:2] <= `NS_ON;
end
/*if(i0_dat < 0) begin
rg_dbg_leds[2:2] <= `NS_ON;
end*/
end
if(! rg_dbg_leds[0:0] && (i0_src == 0)) begin
if(i0_red != i0_redun) begin
rg_dbg_leds[0:0] <= `NS_ON;
end
else
if((r_0_ck_dat <= 14) && ((r_0_ck_dat + 1) != i0_dat)) begin
rg_dbg_leds[0:0] <= `NS_ON;
rg_dbg_disp0 <= i0_dat[3:0];
rg_dbg_disp1 <= r_0_ck_dat[3:0];
end else begin
r_0_ck_dat <= i0_dat;
end
end
if(! rg_dbg_leds[1:1] && (i0_src == 1)) begin
if(i0_red != i0_redun) begin
rg_dbg_leds[1:1] <= `NS_ON;
end
else
if((r_1_ck_dat <= 14) && ((r_1_ck_dat + 1) != i0_dat)) begin
rg_dbg_leds[1:1] <= `NS_ON;
rg_dbg_disp0 <= i0_dat[3:0];
rg_dbg_disp1 <= r_1_ck_dat[3:0];
end else begin
r_1_ck_dat <= i0_dat;
end
end
ri0_cks_done <= `NS_ON;
ri0_ck_dat <= i0_dat;
end
if(ri0_cks_done && i0_ckd_req && (! ri0_ack)) begin
ri0_cks_done <= `NS_OFF;
ri0_ack <= `NS_ON;
end
if((! i0_ckd_req) && ri0_ack) begin
ri0_ack <= `NS_OFF;
end
end
//SRC_0
`NS_ASSIGN_MSG(o0, ro0)
assign o0_req_out = ro0_req;
//SNK_0
assign i0_ack_out = ri0_ack;
`NS_ASSIGN_OUT_DBG(dbg, rg_dbg)
endmodule
|
module clock_counter(
input clk_i, //often, "tags" are added to variables to denote what they do for the user
input reset_n, //here, 'i' is used for input and 'o' for the output, while 'n' specifies an active low signal ("not")
output reg clk_o
);
reg [18:0] count; //register stores the counter value so that it can be modified on a clock edge. register size needs to store as large of a number as the counter reaches
//for this implementation, count must reach 415999, so 2^n >= 415999, n = 19
always @ (posedge clk_i, negedge reset_n)
begin
count <= count + 1; //at every positive edge, the counter is increased by 1
if(!reset_n)
begin
clk_o <= 0;
count <= 0; //if reset (active low) is pushed, the counter is reset
end
else
if(count >= 415999) //count value of greater than or equal to this value causes the output clock to be inverted. the resulting frequency will be input_frequency/(1+count_value)
begin //for this implementation, a frequency of 5 Hz was desired, so 2.08e6/5 - 1 = 415999
clk_o <= ~clk_o;
count <= 0; //resets the counter after the output clock has been inverted
end
end
endmodule |
module ICAP_config
(
input fastclk,
output [7:0] test,
// DIP switches in and out
input [3:0] sw_in,
output [3:0] sw_out,
// Tube interface
input [2:0] h_addr,
input h_cs_b,
inout [7:0] h_data,
input h_phi2,
input h_rdnw,
input h_rst_b
);
reg reconfigure_sw_changed = 1'b0;
reg reconfigure_hw_changed = 1'b0;
reg reconfigure = 1'b0;
reg [4:0] design_num;
wire [3:0] pwr_out;
wire initialized;
reg p_rst_b = 1'b1;
reg h_cs_b1;
reg [2:0] h_addr1;
reg h_rdnw1;
ICAP_core instance_core
(
.fastclk(fastclk),
.design_num(design_num),
.reconfigure(reconfigure),
.powerup(1'b0),
.sw_in(sw_in),
.sw_out(sw_out),
.pwr_out(pwr_out),
.initialized(initialized),
.test(test)
);
always @(posedge fastclk) begin
if (!p_rst_b || !h_rst_b) begin
reconfigure <= reconfigure_sw_changed || reconfigure_hw_changed;
end
end
// Latch control signals on the rising egge of Phi2
// (avoids hold time issues, we do the same in the tube)
always @(posedge h_phi2) begin
h_cs_b1 <= h_cs_b;
h_addr1 <= h_addr;
h_rdnw1 <= h_rdnw;
end
always @(negedge h_phi2) begin
// Mirror the reset bit of register FEE0, and allow this to reconfigure
if (!h_cs_b1 && !h_rdnw1 && h_addr1 == 3'b000) begin
if (h_data[6] && h_data[7]) begin
// Setting the T bit (bit 6) clears all tube registers
p_rst_b <= 1'b1;
end else if (h_data[5]) begin
// Setting the S bit (bit 5) asserts the parasite reset
// Clearing the S bit (bit 5) de-asserts the parasite reset
p_rst_b <= !h_data[7];
end
end
// Implement a write only register at FEE6 to change the current design
if (!h_cs_b1 && !h_rdnw1 && h_addr1 == 3'b110) begin
design_num <= h_data[4:0];
reconfigure_sw_changed <= 1'b1;
end
// Detect changes in the DIP Switches, and invoke the multi boot loader as for a power up
if (initialized) begin
if (sw_in != pwr_out) begin
// Someone has moved the hardware DIP switches
design_num <= 5'b10000;
reconfigure_hw_changed <= 1'b1;
end else begin
// Someone has moved them back again
reconfigure_hw_changed <= 1'b0;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21A_1_V
`define SKY130_FD_SC_HS__O21A_1_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21a_1 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21a_1 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21A_1_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
// Closed loop solution
module cdc_reset_sync (
input wire clk_in,
input wire pulse_in,
input wire clk_out,
output wire pulse_out
);
wire aq_sync;
reg [1:0] in_pre_sync;
always@(posedge clk_in) begin
in_pre_sync[0] <= pulse_in;
in_pre_sync[1] <= in_pre_sync[0];
end
reg in_sync_pulse;
initial in_sync_pulse = 0; //works only in FPGA
always@(posedge clk_in) begin
if (in_pre_sync[1])
in_sync_pulse <= 1;
else if (aq_sync)
in_sync_pulse <= 0;
end
reg [2:0] out_sync;
always@(posedge clk_out) begin
out_sync[0] <= in_sync_pulse;
out_sync[1] <= out_sync[0];
out_sync[2] <= out_sync[1];
end
assign pulse_out = out_sync[2];
reg [1:0] aq_sync_ff;
always@(posedge clk_in) begin
aq_sync_ff[0] <= out_sync[2];
aq_sync_ff[1] <= aq_sync_ff[0];
end
assign aq_sync = aq_sync_ff[1];
endmodule
|
// File: Down_CounterTBV.v
// Generated by MyHDL 0.10
// Date: Tue Aug 14 06:51:23 2018
`timescale 1ns/10ps
module Down_CounterTBV (
);
// myHDL -> Verilog Testbench for `Down_Counter` module
reg clk = 0;
reg rst = 0;
reg Trig = 0;
wire [4:0] count;
reg [4:0] Down_Counter0_0_count_i = 17;
always @(rst, clk, Trig, count) begin: DOWN_COUNTERTBV_PRINT_DATA
$write("%h", clk);
$write(" ");
$write("%h", rst);
$write(" ");
$write("%h", Trig);
$write(" ");
$write("%h", count);
$write("\n");
end
always @(posedge clk, negedge rst) begin: DOWN_COUNTERTBV_DOWN_COUNTER0_0_LOGIC
if (rst) begin
Down_Counter0_0_count_i <= 17;
Trig <= 0;
end
else if ((Down_Counter0_0_count_i == 0)) begin
Trig <= 1;
Down_Counter0_0_count_i <= 17;
end
else begin
Down_Counter0_0_count_i <= (Down_Counter0_0_count_i - 1);
end
end
assign count = Down_Counter0_0_count_i;
initial begin: DOWN_COUNTERTBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: DOWN_COUNTERTBV_STIMULES
integer i;
i = 0;
while (1'b1) begin
case (i)
'h19: begin
rst <= 1;
end
(-'h1): begin
rst <= 0;
end
default: begin
// pass
end
endcase
if ((i == 42)) begin
$finish;
end
i = i + 1;
@(posedge clk);
end
end
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_lfsr12(
clk,
nrst,
ena,
word
);
input clk;
input nrst;
input ena;
output reg [11:0] word;
always @(posedge clk or negedge nrst) begin
if(~nrst) begin
word <= 12'b101001101011;
end
else if(ena) begin
word[11] <= word[0];
word[10] <= word[11];
word[9] <= word[10];
word[8] <= word[9];
word[7] <= word[8];
word[6] <= word[7];
word[5] <= word[6] ^ word[0];
word[4] <= word[5];
word[3] <= word[4] ^ word[0];
word[2] <= word[3];
word[1] <= word[2];
word[0] <= word[1] ^ word[0];
end
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2016.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / ISERDESE3
// /___/ /\ Filename : ISERDESE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module ISERDESE3 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer DATA_WIDTH = 8,
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE",
parameter FIFO_ENABLE = "FALSE",
parameter FIFO_SYNC_MODE = "FALSE",
parameter IDDR_MODE = "FALSE",
parameter [0:0] IS_CLK_B_INVERTED = 1'b0,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter SIM_DEVICE = "ULTRASCALE",
parameter real SIM_VERSION = 2.0
)(
output FIFO_EMPTY,
output INTERNAL_DIVCLK,
output [7:0] Q,
input CLK,
input CLKDIV,
input CLK_B,
input D,
input FIFO_RD_CLK,
input FIFO_RD_EN,
input RST
);
// define constants
localparam MODULE_NAME = "ISERDESE3";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "ISERDESE3_dr.v"
`else
localparam [3:0] DATA_WIDTH_REG = DATA_WIDTH;
localparam [152:1] DDR_CLK_EDGE_REG = DDR_CLK_EDGE;
localparam [40:1] FIFO_ENABLE_REG = FIFO_ENABLE;
localparam [40:1] FIFO_SYNC_MODE_REG = FIFO_SYNC_MODE;
localparam [40:1] IDDR_MODE_REG = IDDR_MODE;
localparam [0:0] IS_CLK_B_INVERTED_REG = IS_CLK_B_INVERTED;
localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE;
localparam real SIM_VERSION_REG = SIM_VERSION;
`endif
localparam [40:1] DDR_DIS_DQS_REG = "FALSE";
localparam [1:0] SPARE_REG = 2'b00;
wire IS_CLK_B_INVERTED_BIN;
wire IS_CLK_INVERTED_BIN;
wire IS_RST_INVERTED_BIN;
wire [63:0] SIM_VERSION_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire FIFO_EMPTY_out;
wire INTERNAL_DIVCLK_out;
wire [7:0] Q_out;
wire FIFO_EMPTY_delay;
wire INTERNAL_DIVCLK_delay;
wire [7:0] Q_delay;
wire CLKDIV_in;
wire CLK_B_in;
wire CLK_in;
wire D_in;
wire FIFO_RD_CLK_in;
wire FIFO_RD_EN_in;
wire IFD_CE_in;
wire RST_in;
wire CLKDIV_delay;
wire CLK_B_delay;
wire CLK_delay;
wire D_delay;
wire FIFO_RD_CLK_delay;
wire FIFO_RD_EN_delay;
wire RST_delay;
assign #(out_delay) FIFO_EMPTY = FIFO_EMPTY_delay;
assign #(out_delay) INTERNAL_DIVCLK = INTERNAL_DIVCLK_delay;
assign #(out_delay) Q = Q_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) CLKDIV_delay = CLKDIV;
assign #(inclk_delay) CLK_B_delay = CLK_B;
assign #(inclk_delay) CLK_delay = CLK;
assign #(inclk_delay) FIFO_RD_CLK_delay = FIFO_RD_CLK;
assign #(in_delay) D_delay = D;
assign #(in_delay) FIFO_RD_EN_delay = FIFO_RD_EN;
assign #(in_delay) RST_delay = RST;
`endif // `ifndef XIL_TIMING
assign FIFO_EMPTY_delay = FIFO_EMPTY_out;
assign INTERNAL_DIVCLK_delay = INTERNAL_DIVCLK_out;
assign Q_delay = Q_out;
assign CLKDIV_in = CLKDIV_delay;
assign CLK_B_in = CLK_B_delay ^ IS_CLK_B_INVERTED_BIN;
assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN;
assign D_in = D_delay;
assign FIFO_RD_CLK_in = FIFO_RD_CLK_delay;
assign FIFO_RD_EN_in = FIFO_RD_EN_delay;
assign RST_in = RST_delay ^ IS_RST_INVERTED_BIN;
assign IS_CLK_B_INVERTED_BIN = IS_CLK_B_INVERTED_REG;
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((DATA_WIDTH_REG != 8) &&
(DATA_WIDTH_REG != 4))) begin
$display("Error: [Unisim %s-101] DATA_WIDTH attribute is set to %d. Legal values for this attribute are 8 or 4. Instance: %m", MODULE_NAME, DATA_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DDR_CLK_EDGE_REG != "OPPOSITE_EDGE") &&
(DDR_CLK_EDGE_REG != "SAME_EDGE") &&
(DDR_CLK_EDGE_REG != "SAME_EDGE_PIPELINED"))) begin
$display("Error: [Unisim %s-102] DDR_CLK_EDGE attribute is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED. Instance: %m", MODULE_NAME, DDR_CLK_EDGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FIFO_ENABLE_REG != "FALSE") &&
(FIFO_ENABLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-104] FIFO_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FIFO_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FIFO_SYNC_MODE_REG != "FALSE") &&
(FIFO_SYNC_MODE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-105] FIFO_SYNC_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FIFO_SYNC_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IDDR_MODE_REG != "FALSE") &&
(IDDR_MODE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-106] IDDR_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, IDDR_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_DEVICE_REG != "ULTRASCALE") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin
$display("Error: [Unisim %s-110] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_VERSION_REG != 2.0) &&
(SIM_VERSION_REG != 1.0))) begin
$display("Error: [Unisim %s-111] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
assign IFD_CE_in = 1'b0; // tie off
generate
if ((SIM_DEVICE == "ULTRASCALE_PLUS") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES1") || (SIM_DEVICE == "ULTRASCALE_PLUS_ES2")) begin : generate_block1
SIP_ISERDESE3_D1 SIP_ISERDESE3_INST (
.DATA_WIDTH (DATA_WIDTH_REG),
.DDR_CLK_EDGE (DDR_CLK_EDGE_REG),
.DDR_DIS_DQS (DDR_DIS_DQS_REG),
.FIFO_ENABLE (FIFO_ENABLE_REG),
.FIFO_SYNC_MODE (FIFO_SYNC_MODE_REG),
.IDDR_MODE (IDDR_MODE_REG),
.SPARE (SPARE_REG),
.FIFO_EMPTY (FIFO_EMPTY_out),
.INTERNAL_DIVCLK (INTERNAL_DIVCLK_out),
.Q (Q_out),
.CLK (CLK_in),
.CLKDIV (CLKDIV_in),
.CLK_B (CLK_B_in),
.D (D_in),
.FIFO_RD_CLK (FIFO_RD_CLK_in),
.FIFO_RD_EN (FIFO_RD_EN_in),
.IFD_CE (IFD_CE_in),
.RST (RST_in),
.GSR (glblGSR)
);
end else begin : generate_block1
SIP_ISERDESE3 SIP_ISERDESE3_INST (
.DATA_WIDTH (DATA_WIDTH_REG),
.DDR_CLK_EDGE (DDR_CLK_EDGE_REG),
.DDR_DIS_DQS (DDR_DIS_DQS_REG),
.FIFO_ENABLE (FIFO_ENABLE_REG),
.FIFO_SYNC_MODE (FIFO_SYNC_MODE_REG),
.IDDR_MODE (IDDR_MODE_REG),
.SIM_VERSION (SIM_VERSION_BIN),
.FIFO_EMPTY (FIFO_EMPTY_out),
.INTERNAL_DIVCLK (INTERNAL_DIVCLK_out),
.Q (Q_out),
.CLK (CLK_in),
.CLKDIV (CLKDIV_in),
.CLK_B (CLK_B_in),
.D (D_in),
.FIFO_RD_CLK (FIFO_RD_CLK_in),
.FIFO_RD_EN (FIFO_RD_EN_in),
.IFD_CE (IFD_CE_in),
.RST (RST_in),
.GSR (glblGSR)
);
end
endgenerate
`ifdef XIL_TIMING
reg notifier;
wire clk_b_en_n;
wire clk_b_en_p;
wire clk_en_n;
wire clk_en_p;
assign clk_b_en_n = IS_CLK_B_INVERTED_BIN;
assign clk_b_en_p = ~IS_CLK_B_INVERTED_BIN;
assign clk_en_n = IS_CLK_INVERTED_BIN;
assign clk_en_p = ~IS_CLK_INVERTED_BIN;
`endif
specify
(CLK *> Q) = (100:100:100, 100:100:100);
(CLK => FIFO_EMPTY) = (100:100:100, 100:100:100);
(CLK => INTERNAL_DIVCLK) = (100:100:100, 100:100:100);
(CLK_B *> Q) = (100:100:100, 100:100:100);
(FIFO_RD_CLK *> Q) = (100:100:100, 100:100:100);
(FIFO_RD_CLK => FIFO_EMPTY) = (100:100:100, 100:100:100);
(negedge RST *> (Q +: 0)) = (100:100:100, 100:100:100);
(posedge RST *> (Q +: 0)) = (100:100:100, 100:100:100);
// (INTERNAL_DIVCLK *> Q) = (0:0:0, 0:0:0); // error prop output to output
`ifdef XIL_TIMING
$period (negedge CLK, 0:0:0, notifier);
$period (negedge CLKDIV, 0:0:0, notifier);
$period (negedge CLK_B, 0:0:0, notifier);
$period (negedge FIFO_RD_CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$period (posedge CLKDIV, 0:0:0, notifier);
$period (posedge CLK_B, 0:0:0, notifier);
$period (posedge FIFO_RD_CLK, 0:0:0, notifier);
$recrem (negedge RST, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_delay, CLK_delay);
$recrem (negedge RST, negedge CLK_B, 0:0:0, 0:0:0, notifier, clk_b_en_n, clk_b_en_n, RST_delay, CLK_B_delay);
$recrem (negedge RST, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_delay, CLK_delay);
$recrem (negedge RST, posedge CLK_B, 0:0:0, 0:0:0, notifier, clk_b_en_p, clk_b_en_p, RST_delay, CLK_B_delay);
$recrem (posedge RST, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_delay, CLK_delay);
$recrem (posedge RST, negedge CLK_B, 0:0:0, 0:0:0, notifier, clk_b_en_n, clk_b_en_n, RST_delay, CLK_B_delay);
$recrem (posedge RST, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_delay, CLK_delay);
$recrem (posedge RST, posedge CLK_B, 0:0:0, 0:0:0, notifier, clk_b_en_p, clk_b_en_p, RST_delay, CLK_B_delay);
$setuphold (negedge CLK, negedge D, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, D_delay);
$setuphold (negedge CLK, posedge D, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, D_delay);
$setuphold (negedge CLK_B, negedge D, 0:0:0, 0:0:0, notifier, clk_b_en_n, clk_b_en_n, CLK_B_delay, D_delay);
$setuphold (negedge CLK_B, posedge D, 0:0:0, 0:0:0, notifier, clk_b_en_n, clk_b_en_n, CLK_B_delay, D_delay);
$setuphold (posedge CLK, negedge D, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, D_delay);
$setuphold (posedge CLK, posedge D, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, D_delay);
$setuphold (posedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier, , , CLKDIV_delay, RST_delay);
$setuphold (posedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier, , , CLKDIV_delay, RST_delay);
$setuphold (posedge CLK_B, negedge D, 0:0:0, 0:0:0, notifier, clk_b_en_p, clk_b_en_p, CLK_B_delay, D_delay);
$setuphold (posedge CLK_B, posedge D, 0:0:0, 0:0:0, notifier, clk_b_en_p, clk_b_en_p, CLK_B_delay, D_delay);
$setuphold (posedge FIFO_RD_CLK, negedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier, , , FIFO_RD_CLK_delay, FIFO_RD_EN_delay);
$setuphold (posedge FIFO_RD_CLK, posedge FIFO_RD_EN, 0:0:0, 0:0:0, notifier, , , FIFO_RD_CLK_delay, FIFO_RD_EN_delay);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (negedge CLKDIV, 0:0:0, 0, notifier);
$width (negedge CLK_B, 0:0:0, 0, notifier);
$width (negedge FIFO_RD_CLK, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$width (posedge CLKDIV, 0:0:0, 0, notifier);
$width (posedge CLK_B, 0:0:0, 0, notifier);
$width (posedge FIFO_RD_CLK, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:31:09 05/12/2016
// Design Name:
// Module Name: controlador_teclado_ps2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module controlador_teclado_ps2
(
input wire clk, reset,
input wire ps2data, ps2clk,
input wire [7:0] port_id,
input wire read_strobe,
output wire [7:0] ascii_code
);
//Declaración de señales de conexión
wire [10:0] dout;
wire rx_done_tick;
wire gotten_code_flag;
wire [7:0] key_code;
reg [7:0] key_code_reg, key_code_next;
//Para la máquina de estados del registro de la tecla
reg [1:0] state_current, state_next;
localparam [1:0] hold_key_code = 2'b0, read_key_code = 2'b01, reset_key_code = 2'b10;
receptor_teclado_ps2 instancia_receptor_teclado_ps2
(
.clk(clk),
.reset(reset),
.ps2data(ps2data),
.ps2clk(ps2clk),
.rx_en(1'b1),
.rx_done_tick(rx_done_tick),
.dout(dout)
);
identificador_teclas instancia_identificador_teclas
(
.clk(clk),
.reset(reset),
.rx_done_tick(rx_done_tick),
.dout(dout[8:1]),//Utilizar solo los bits que realmente contienen el código de la tecla [8:1]
.gotten_code_flag(gotten_code_flag) //Bandera para actualizar el FIFO
);
keycode_to_ascii instancia_keycode_to_ascii
(
.key_code(key_code),
.ascii_code(ascii_code)
);
//===================================================
// Registro para conservar la última tecla presionada
//===================================================
//Secuencial
always@(posedge clk)
begin
if(reset) begin
key_code_reg <= 8'b0;
state_current <= hold_key_code;
end
else begin
key_code_reg <= key_code_next;
state_current <= state_next;
end
end
//Lógica de estado siguiente
always@*
begin
case(state_current)
hold_key_code://Hold
begin
key_code_next = key_code_reg;
if(gotten_code_flag) state_next = read_key_code;
else state_next = state_current;
end
read_key_code://Escribe registro/Espera lectura del micro
begin
key_code_next = dout[8:1]; //Utilizar solo los bits que realmente contienen el código de la tecla
if(port_id == 8'h02 && read_strobe == 1) state_next = reset_key_code;
else state_next = state_current;
end
reset_key_code:
begin
key_code_next = 8'b0;
state_next = hold_key_code;
end
default:
begin
key_code_next = key_code_reg;
state_next = state_current;
end
endcase
end
assign key_code = key_code_reg;
endmodule
/*//===================================================
// Registro para conservar la última tecla presionada
//===================================================
//Secuencial
always@(posedge clk)
begin
if(reset)
key_code_reg <= 8'b0;
else
key_code_reg <= key_code_next;
end
//Lógica de estado siguiente
always@*
begin
case(gotten_code_flag)
1'b0://Hold
key_code_next = key_code_reg;
1'b1://Escribe
key_code_next = dout[8:1]; //Utilizar solo los bits que realmente contienen el código de la tecla
endcase
end
assign key_code = key_code_reg;
endmodule
*/ |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FA_4_V
`define SKY130_FD_SC_LS__FA_4_V
/**
* fa: Full adder.
*
* Verilog wrapper for fa with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fa.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fa_4 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fa_4 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FA_4_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Oct 31 12:11:23 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top dbg_ila -prefix
// dbg_ila_ dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module dbg_ila(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[8:0],probe20[7:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[0:0],probe25[7:0],probe26[3:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [0:0]probe18;
input [8:0]probe19;
input [7:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
input [0:0]probe24;
input [7:0]probe25;
input [3:0]probe26;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 14 10:33:19 2017
// Host : PC4719 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_0_stub.v
// Design : vio_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "vio,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_in2)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[0:0],probe_in2[0:0]" */;
input clk;
input [0:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A222OI_PP_BLACKBOX_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222OI_PP_BLACKBOX_V
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(** In this chapter we continue our development of basic
concepts of functional programming. The critical new ideas are
_polymorphism_ (abstracting functions over the types of the data
they manipulate) and _higher-order functions_ (treating functions
as data).
*)
Require Export Lists.
(* ###################################################### *)
(** * Polymorphism *)
(* ###################################################### *)
(** ** Polymorphic Lists *)
(** For the last couple of chapters, we've been working just
with lists of numbers. Obviously, interesting programs also need
to be able to manipulate lists with elements from other types --
lists of strings, lists of booleans, lists of lists, etc. We
_could_ just define a new inductive datatype for each of these,
for example... *)
Inductive boollist : Type :=
| bool_nil : boollist
| bool_cons : bool -> boollist -> boollist.
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) for each
new datatype definition. *)
(** *** *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a _polymorphic
list_ datatype. *)
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the header, and the occurrences of
[natlist] in the types of the constructors have been replaced by
[list X]. (We can re-use the constructor names [nil] and [cons]
because the earlier definition of [natlist] was inside of a
[Module] definition that is now out of scope.) *)
(** What sort of thing is [list] itself? One good way to think
about it is that [list] is a _function_ from [Type]s to
[Inductive] definitions; or, to put it another way, [list] is a
function from [Type]s to [Type]s. For any particular type [X],
the type [list X] is an [Inductive]ly defined set of lists whose
elements are things of type [X]. *)
(** With this definition, when we use the constructors [nil] and
[cons] to build lists, we need to tell Coq the type of the
elements in the lists we are building -- that is, [nil] and [cons]
are now _polymorphic constructors_. Observe the types of these
constructors: *)
Check nil.
(* ===> nil : forall X : Type, list X *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** The "[forall X]" in these types can be read as an additional
argument to the constructors that determines the expected types of
the arguments that follow. When [nil] and [cons] are used, these
arguments are supplied in the same way as the others. For
example, the list containing [2] and [1] is written like this: *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(** (We've gone back to writing [nil] and [cons] explicitly here
because we haven't yet defined the [ [] ] and [::] notations for
the new version of lists. We'll do that in a bit.) *)
(** We can now go back and make polymorphic (or "generic")
versions of all the list-processing functions that we wrote
before. Here is [length], for example: *)
(** *** *)
Fixpoint length (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length X t)
end.
(** Note that the uses of [nil] and [cons] in [match] patterns
do not require any type annotations: Coq already knows that the list
[l] contains elements of type [X], so there's no reason to include
[X] in the pattern. (More precisely, the type [X] is a parameter
of the whole definition of [list], not of the individual
constructors. We'll come back to this point later.)
As with [nil] and [cons], we can use [length] by applying it first
to a type and then to its list argument: *)
Example test_length1 :
length nat (cons nat 1 (cons nat 2 (nil nat))) = 2.
Proof. reflexivity. Qed.
(** To use our length with other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_length2 :
length bool (cons bool true (nil bool)) = 1.
Proof. reflexivity. Qed.
(** *** *)
(** Let's close this subsection by re-implementing a few other
standard list functions on our new polymorphic lists: *)
Fixpoint app (X : Type) (l1 l2 : list X)
: (list X) :=
match l1 with
| nil => l2
| cons h t => cons X h (app X t l2)
end.
Fixpoint snoc (X:Type) (l:list X) (v:X) : (list X) :=
match l with
| nil => cons X v (nil X)
| cons h t => cons X h (snoc X t v)
end.
Fixpoint rev (X:Type) (l:list X) : list X :=
match l with
| nil => nil X
| cons h t => snoc X (rev X t) h
end.
Example test_rev1 :
rev nat (cons nat 1 (cons nat 2 (nil nat)))
= (cons nat 2 (cons nat 1 (nil nat))).
Proof. reflexivity. Qed.
Example test_rev2:
rev bool (nil bool) = nil bool.
Proof. reflexivity. Qed.
Module MumbleBaz.
(** **** Exercise: 2 stars (mumble_grumble) *)
(** Consider the following two inductively defined types. *)
Inductive mumble : Type :=
| a : mumble
| b : mumble -> nat -> mumble
| c : mumble.
Inductive grumble (X:Type) : Type :=
| d : mumble -> grumble X
| e : X -> grumble X.
(** Which of the following are well-typed elements of [grumble X] for
some type [X]?
- [d (b a 5)]
- [d mumble (b a 5)]
- [d bool (b a 5)]
- [e bool true]
- [e mumble (b c 0)]
- [e bool (b c 0)]
- [c]
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 2 stars (baz_num_elts) *)
(** Consider the following inductive definition: *)
Inductive baz : Type :=
| x : baz -> baz
| y : baz -> bool -> baz.
(** How _many_ elements does the type [baz] have?
(* FILL IN HERE *)
*)
(** [] *)
End MumbleBaz.
(* ###################################################### *)
(** *** Type Annotation Inference *)
(** Let's write the definition of [app] again, but this time we won't
specify the types of any of the arguments. Will Coq still accept
it? *)
Fixpoint app' X l1 l2 : list X :=
match l1 with
| nil => l2
| cons h t => cons X h (app' X t l2)
end.
(** Indeed it will. Let's see what type Coq has assigned to [app']: *)
Check app'.
(* ===> forall X : Type, list X -> list X -> list X *)
Check app.
(* ===> forall X : Type, list X -> list X -> list X *)
(** It has exactly the same type type as [app]. Coq was able to
use a process called _type inference_ to deduce what the types of
[X], [l1], and [l2] must be, based on how they are used. For
example, since [X] is used as an argument to [cons], it must be a
[Type], since [cons] expects a [Type] as its first argument;
matching [l1] with [nil] and [cons] means it must be a [list]; and
so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations are still quite useful as documentation and sanity
checks. You should try to find a balance in your own code between
too many type annotations (so many that they clutter and distract)
and too few (which forces readers to perform type inference in
their heads in order to understand your code). *)
(* ###################################################### *)
(** *** Type Argument Synthesis *)
(** Whenever we use a polymorphic function, we need to pass it
one or more types in addition to its other arguments. For
example, the recursive call in the body of the [length] function
above must pass along the type [X]. But just like providing
explicit type annotations everywhere, this is heavy and verbose.
Since the second argument to [length] is a list of [X]s, it seems
entirely obvious that the first argument can only be [X] -- why
should we have to write it explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write the "implicit argument"
[_], which can be read as "Please figure out for yourself what
type belongs here." More precisely, when Coq encounters a [_], it
will attempt to _unify_ all locally available information -- the
type of the function being applied, the types of the other
arguments, and the type expected by the context in which the
application appears -- to determine what concrete type should
replace the [_].
This may sound similar to type annotation inference -- and,
indeed, the two procedures rely on the same underlying mechanisms.
Instead of simply omitting the types of some arguments to a
function, like
app' X l1 l2 : list X :=
we can also replace the types with [_], like
app' (X : _) (l1 l2 : _) : list X :=
which tells Coq to attempt to infer the missing information, just
as with argument synthesis.
Using implicit arguments, the [length] function can be written
like this: *)
Fixpoint length' (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length' _ t)
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference can be significant. For
example, suppose we want to write down a list containing the
numbers [1], [2], and [3]. Instead of writing this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use argument synthesis to write this: *)
Definition list123' := cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ###################################################### *)
(** *** Implicit Arguments *)
(** In fact, we can go further. To avoid having to sprinkle [_]'s
throughout our programs, we can tell Coq _always_ to infer the
type argument(s) of a given function. The [Arguments] directive
specifies the name of the function or constructor, and then lists
its argument names, with curly braces around any arguments to be
treated as implicit.
*)
Arguments nil {X}.
Arguments cons {X} _ _. (* use underscore for argument position that has no name *)
Arguments length {X} l.
Arguments app {X} l1 l2.
Arguments rev {X} l.
Arguments snoc {X} l v.
(* note: no _ arguments required... *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
Check (length list123'').
(** *** *)
(** Alternatively, we can declare an argument to be implicit while
defining the function itself, by surrounding the argument in curly
braces. For example: *)
Fixpoint length'' {X:Type} (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length'' t)
end.
(** (Note that we didn't even have to provide a type argument to
the recursive call to [length'']; indeed, it is invalid to provide
one.) We will use this style whenever possible, although we will
continue to use use explicit [Argument] declarations for
[Inductive] constructors. *)
(** *** *)
(** One small problem with declaring arguments [Implicit] is
that, occasionally, Coq does not have enough local information to
determine a type argument; in such cases, we need to tell Coq that
we want to give the argument explicitly this time, even though
we've globally declared it to be [Implicit]. For example, suppose we
write this: *)
(* Definition mynil := nil. *)
(** If we uncomment this definition, Coq will give us an error,
because it doesn't know what type argument to supply to [nil]. We
can help it by providing an explicit type declaration (so that Coq
has more information available when it gets to the "application"
of [nil]): *)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil.
Definition mynil' := @nil nat.
(** *** *)
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1; 2; 3].
(* ###################################################### *)
(** *** Exercises: Polymorphic Lists *)
(** **** Exercise: 2 stars, optional (poly_exercises) *)
(** Here are a few simple exercises, just like ones in the [Lists]
chapter, for practice with polymorphism. Fill in the definitions
and complete the proofs below. *)
Fixpoint repeat {X : Type} (n : X) (count : nat) : list X :=
match count with
| 0 => []
| S count' => n::(repeat n count')
end.
Example test_repeat1:
repeat true 2 = cons true (cons true nil).
Proof. reflexivity. Qed.
Theorem nil_app : forall X:Type, forall l:list X,
app [] l = l.
Proof.
intros X l.
reflexivity.
Qed.
Theorem rev_snoc : forall X : Type,
forall v : X,
forall s : list X,
rev (snoc s v) = v :: (rev s).
Proof.
intros X v s.
induction s as [| x s'].
Case "s = []".
reflexivity.
Case "s = x::s'".
simpl.
rewrite IHs'.
reflexivity.
Qed.
Theorem rev_involutive : forall X : Type, forall l : list X,
rev (rev l) = l.
Proof.
intros X l.
induction l as [| x l'].
Case "l = []".
reflexivity.
Case "l = x::l'".
simpl.
rewrite rev_snoc.
rewrite IHl'.
reflexivity.
Qed.
Theorem snoc_with_append : forall X : Type,
forall l1 l2 : list X,
forall v : X,
snoc (l1 ++ l2) v = l1 ++ (snoc l2 v).
Proof.
intros X l1 l2 v.
induction l1 as [| x l1'].
Case "l1 = []".
reflexivity.
Case "l1 = x::l1'".
simpl.
rewrite IHl1'.
reflexivity.
Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the type definition we gave in
the last chapter for pairs of numbers can be generalized to
_polymorphic pairs_ (or _products_): *)
Inductive prod (X Y : Type) : Type :=
pair : X -> Y -> prod X Y.
Arguments pair {X} {Y} _ _.
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for pair _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should be used when parsing types. This avoids a clash with the
multiplication symbol.) *)
(** *** *)
(** A note of caution: it is easy at first to get [(x,y)] and
[X*Y] confused. Remember that [(x,y)] is a _value_ built from two
other values; [X*Y] is a _type_ built from two other types. If
[x] has type [X] and [y] has type [Y], then [(x,y)] has type
[X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with (x,y) => x end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with (x,y) => y end.
(** The following function takes two lists and combines them
into a list of pairs. In many functional programming languages,
it is called [zip]. We call it [combine] for consistency with
Coq's standard library. *)
(** Note that the pair notation can be used both in expressions and in
patterns... *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match (lx,ly) with
| ([],_) => []
| (_,[]) => []
| (x::tx, y::ty) => (x,y) :: (combine tx ty)
end.
(** **** Exercise: 1 star, optional (combine_checks) *)
(** Try answering the following questions on paper and
checking your answers in coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
- What does
Eval compute in (combine [1;2] [false;false;true;true]).
print? []
*)
(** **** Exercise: 2 stars (split) *)
(** The function [split] is the right inverse of combine: it takes a
list of pairs and returns a pair of lists. In many functional
programing languages, this function is called [unzip].
Uncomment the material below and fill in the definition of
[split]. Make sure it passes the given unit tests. *)
Fixpoint split
{X Y : Type} (l : list (X*Y))
: (list X) * (list Y) :=
match l with
| [] => ([], [])
| (x, y)::l =>
match split l with
| (xs, ys) => (x::xs, y::ys)
end
end.
Example test_split:
split [(1,false);(2,false)] = ([1;2],[false;false]).
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Options *)
(** One last polymorphic type for now: _polymorphic options_.
The type declaration generalizes the one for [natoption] in the
previous chapter: *)
Inductive option (X:Type) : Type :=
| Some : X -> option X
| None : option X.
Arguments Some {X} _.
Arguments None {X}.
(** *** *)
(** We can now rewrite the [index] function so that it works
with any type of lists. *)
Fixpoint index {X : Type} (n : nat)
(l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Example test_index1 : index 0 [4;5;6;7] = Some 4.
Proof. reflexivity. Qed.
Example test_index2 : index 1 [[1];[2]] = Some [2].
Proof. reflexivity. Qed.
Example test_index3 : index 2 [true] = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (hd_opt_poly) *)
(** Complete the definition of a polymorphic version of the
[hd_opt] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_opt {X : Type} (l : list X) : option X :=
match l with
| [] => None
| x::_ => Some x
end.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_opt.
Example test_hd_opt1 : hd_opt [1;2] = Some 1.
Proof. reflexivity. Qed.
Example test_hd_opt2 : hd_opt [[1];[2]] = Some [1].
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** * Functions as Data *)
(* ###################################################### *)
(** ** Higher-Order Functions *)
(** Like many other modern programming languages -- including
all _functional languages_ (ML, Haskell, Scheme, etc.) -- Coq
treats functions as first-class citizens, allowing functions to be
passed as arguments to other functions, returned as results,
stored in data structures, etc.
Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Partial Application *)
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall the type of [plus]. *)
Check plus.
(* ==> nat -> nat -> nat *)
(** Each [->] in this expression is actually a _binary_ operator
on types. (This is the same as saying that Coq primitively
supports only one-argument functions -- do you see why?) This
operator is _right-associative_, so the type of [plus] is really a
shorthand for [nat -> (nat -> nat)] -- i.e., it can be read as
saying that "[plus] is a one-argument function that takes a [nat]
and returns a one-argument function that takes another [nat] and
returns a [nat]." In the examples above, we have always applied
[plus] to both of its arguments at once, but if we like we can
supply just the first. This is called _partial application_. *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Digression: Currying *)
(** **** Exercise: 2 stars, advanced (currying) *)
(** In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z) (p : X * Y) : Z :=
let (x, y) := p in f x y.
(** (Thought exercise: before running these commands, can you
calculate the types of [prod_curry] and [prod_uncurry]?) *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type) (f : X -> Y -> Z) x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
intros X Y Z f x y.
reflexivity.
Qed.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
intros X Y Z f p.
destruct p as [x y].
reflexivity.
Qed.
(** [] *)
(* ###################################################### *)
(** ** Filter *)
(** Here is a useful higher-order function, which takes a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filters" the list, returning a new list containing just those
elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [evenb]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter evenb [1;2;3;4] = [2;4].
Proof. reflexivity. Qed.
(** *** *)
Definition length_is_1 {X : Type} (l : list X) : bool :=
beq_nat (length l) 1.
Example test_filter2:
filter length_is_1
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** *** *)
(** We can use [filter] to give a concise version of the
[countoddmembers] function from the [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1;0;3;1;4;5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0;2;4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Anonymous Functions *)
(** It is a little annoying to be forced to define the function
[length_is_1] and give it a name just to be able to pass it as an
argument to [filter], since we will probably never use it again.
Moreover, this is not an isolated example. When using
higher-order functions, we often want to pass as arguments
"one-off" functions that we will never use again; having to give
each of these functions a name would be tedious.
Fortunately, there is a better way. It is also possible to
construct a function "on the fly" without declaring it at the top
level or giving it a name; this is analogous to the notation we've
been using for writing down constant lists, natural numbers, and
so on. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** Here is the motivating example from before, rewritten to use
an anonymous function. *)
Example test_filter2':
filter (fun l => beq_nat (length l) 1)
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (filter_even_gt7) *)
(** Use [filter] (instead of [Fixpoint]) to write a Coq function
[filter_even_gt7] that takes a list of natural numbers as input
and returns a list of just those that are even and greater than
7. *)
Definition filter_even_gt7 (l : list nat) : list nat :=
filter (fun x => andb (evenb x) (negb (ble_nat x 7))) l.
Example test_filter_even_gt7_1 :
filter_even_gt7 [1;2;6;9;10;3;12;8] = [10;12;8].
Proof. reflexivity. Qed.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5;2;6;19;129] = [].
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (partition) *)
(** Use [filter] to write a Coq function [partition]:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given a set [X], a test function of type [X -> bool] and a [list
X], [partition] should return a pair of lists. The first member of
the pair is the sublist of the original list containing the
elements that satisfy the test, and the second is the sublist
containing those that fail the test. The order of elements in the
two sublists should be the same as their order in the original
list.
*)
Definition partition {X : Type} (test : X -> bool) (l : list X)
: list X * list X :=
(filter test l, filter (fun x => negb (test x)) l).
Example test_partition1: partition oddb [1;2;3;4;5] = ([1;3;5], [2;4]).
Proof. reflexivity. Qed.
Example test_partition2: partition (fun x => false) [5;9;0] = ([], [5;9;0]).
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y:Type} (f:X->Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** *** *)
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (plus 3) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same ([map] takes _two_ type arguments, [X] and [Y]). This
version of [map] can thus be applied to a list of numbers and a
function from numbers to booleans to yield a list of booleans: *)
Example test_map2: map oddb [2;1;2;5] = [false;true;false;true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a list of lists of booleans: *)
Example test_map3:
map (fun n => [evenb n;oddb n]) [2;1;2;5]
= [[true;false];[false;true];[true;false];[false;true]].
Proof. reflexivity. Qed.
(** ** Map for options *)
(** **** Exercise: 3 stars (map_rev) *)
(** Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Theorem map_snoc : forall (X Y : Type) (f : X -> Y) (l : list X) (x : X),
map f (snoc l x) = snoc (map f l) (f x).
Proof.
intros X Y f l x.
induction l as [| x' l'].
Case "l = []".
reflexivity.
Case "l = x::l'".
simpl.
rewrite IHl'.
reflexivity.
Qed.
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
intros X Y f l.
induction l as [| x l'].
Case "l = []".
reflexivity.
Case "l = x::l'".
simpl.
rewrite map_snoc.
rewrite IHl'.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (flat_map) *)
(** The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
flat_map (fun n => [n;n+1;n+2]) [1;5;10]
= [1; 2; 3; 5; 6; 7; 10; 11; 12].
*)
Fixpoint flatten {X: Type} (xs: list (list X)) : (list X) :=
match xs with
| [] => []
| x::xs => x ++ (flatten xs)
end.
Example flatten_1 : flatten [[1]; [2]; [3]] = [1; 2; 3].
Proof. reflexivity. Qed.
Example flatten_2 : flatten [[1; 2; 3]; [4; 5]; [6]] = [1; 2; 3; 4; 5; 6].
Proof. reflexivity. Qed.
Fixpoint flat_map {X Y:Type} (f:X -> list Y) (l:list X) : (list Y) :=
flatten (map f l).
Example test_flat_map1:
flat_map (fun n => [n;n;n]) [1;5;4]
= [1; 1; 1; 5; 5; 5; 4; 4; 4].
Proof. reflexivity. Qed.
(** [] *)
(** Lists are not the only inductive type that we can write a
[map] function for. Here is the definition of [map] for the
[option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, optional (implicit_args) *)
(** The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. (This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards.) [] *)
(* ###################################################### *)
(** ** Fold *)
(** An even more powerful higher-order function is called
[fold]. This function is the inspiration for the "[reduce]"
operation that lies at the heart of Google's map/reduce
distributed programming framework. *)
Fixpoint fold {X Y:Type} (f: X->Y->Y) (l:list X) (b:Y) : Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** *** *)
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1;2;3;4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
fold plus [1;2;3;4] 0
yields
1 + (2 + (3 + (4 + 0))).
Here are some more examples:
*)
Check (fold andb).
(* ===> fold andb : list bool -> bool -> bool *)
Example fold_example1 : fold mult [1;2;3;4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 : fold andb [true;true;false;true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 : fold app [[1];[];[2;3];[4]] [] = [1;2;3;4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, advanced (fold_types_different) *)
(** Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different? *)
(* ###################################################### *)
(** ** Functions For Constructing Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as _arguments_. Now let's look at some
examples involving _returning_ functions as the results of other
functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat->X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, but a bit more interestingly, here is a function
that takes a function [f] from numbers to some type [X], a number
[k], and a value [x], and constructs a function that behaves
exactly like [f] except that, when called with the argument [k],
it returns [x]. *)
Definition override {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if beq_nat k k' then x else f k'.
(** For example, we can apply [override] twice to obtain a
function from numbers to booleans that returns [false] on [1] and
[3] and returns [true] on all other arguments. *)
Definition fmostlytrue := override (override ftrue 1 false) 3 false.
(** *** *)
Example override_example1 : fmostlytrue 0 = true.
Proof. reflexivity. Qed.
Example override_example2 : fmostlytrue 1 = false.
Proof. reflexivity. Qed.
Example override_example3 : fmostlytrue 2 = true.
Proof. reflexivity. Qed.
Example override_example4 : fmostlytrue 3 = false.
Proof. reflexivity. Qed.
(** *** *)
(** **** Exercise: 1 star (override_example) *)
(** Before starting to work on the following proof, make sure you
understand exactly what the theorem is saying and can paraphrase
it in your own words. The proof itself is straightforward. *)
Theorem override_example : forall (b:bool),
(override (constfun b) 3 true) 2 = b.
Proof.
intros b.
reflexivity.
Qed.
(** [] *)
(** We'll use function overriding heavily in parts of the rest of the
course, and we will end up needing to know quite a bit about its
properties. To prove these properties, though, we need to know
about a few more of Coq's tactics; developing these is the main
topic of the next chapter. For now, though, let's introduce just
one very useful tactic that will also help us with proving
properties of some of the other functions we have introduced in
this chapter. *)
(* ###################################################### *)
(* ###################################################### *)
(** * The [unfold] Tactic *)
(** Sometimes, a proof will get stuck because Coq doesn't
automatically expand a function call into its definition. (This
is a feature, not a bug: if Coq automatically expanded everything
possible, our proof goals would quickly become enormous -- hard to
read and slow for Coq to manipulate!) *)
Theorem unfold_example_bad : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
(* At this point, we'd like to do [rewrite -> H], since
[plus3 n] is definitionally equal to [3 + n]. However,
Coq doesn't automatically expand [plus3 n] to its
definition. *)
Abort.
(** The [unfold] tactic can be used to explicitly replace a
defined name by the right-hand side of its definition. *)
Theorem unfold_example : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
unfold plus3.
rewrite -> H.
reflexivity. Qed.
(** Now we can prove a first property of [override]: If we
override a function at some argument [k] and then look up [k], we
get back the overridden value. *)
Theorem override_eq : forall {X:Type} x k (f:nat->X),
(override f k x) k = x.
Proof.
intros X x k f.
unfold override.
rewrite <- beq_nat_refl.
reflexivity. Qed.
(** This proof was straightforward, but note that it requires
[unfold] to expand the definition of [override]. *)
(** **** Exercise: 2 stars (override_neq) *)
Theorem override_neq : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
f k1 = x1 ->
beq_nat k2 k1 = false ->
(override f k2 x2) k1 = x1.
Proof.
intros X x1 x2 k1 k2 f H1 H2.
unfold override.
rewrite H2.
rewrite H1.
reflexivity.
Qed.
(** [] *)
(** As the inverse of [unfold], Coq also provides a tactic
[fold], which can be used to "unexpand" a definition. It is used
much less often. *)
(* ##################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars (fold_length) *)
(** Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternative definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4;7;0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
Proof.
intros X l.
induction l as [| x l'].
Case "l = []".
reflexivity.
Case "l = x::l'".
simpl.
unfold fold_length.
simpl.
fold (fold_length l').
rewrite IHl'.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (fold_map) *)
(** We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y:Type} (f : X -> Y) (l : list X) : list Y :=
fold (fun x a => f x::a) l [].
(** Write down a theorem [fold_map_correct] in Coq stating that
[fold_map] is correct, and prove it. *)
Theorem fold_map_correct : forall (X Y : Type) (f : X -> Y) (l : list X),
fold_map f l = map f l.
Proof.
intros X Y f l.
induction l as [| x l'].
Case "l = []".
reflexivity.
Case "l = x::l'".
unfold fold_map.
simpl.
rewrite <- IHl'.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (index_informal) *)
(** Recall the definition of the [index] function:
Fixpoint index {X : Type} (n : nat) (l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Write an informal proof of the following theorem:
forall X n l, length l = n -> @index X n l = None.
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 4 stars, advanced (church_numerals) *)
Module Church.
(** In this exercise, we will explore an alternative way of defining
natural numbers, using the so-called _Church numerals_, named
after mathematician Alonzo Church. We can represent a natural
number [n] as a function that takes a function [f] as a parameter
and returns [f] iterated [n] times. More formally, *)
Definition nat := forall X : Type, (X -> X) -> X -> X.
(** Let's see how to write some numbers with this notation. Any
function [f] iterated once shouldn't change. Thus, *)
Definition one : nat :=
fun (X : Type) (f : X -> X) (x : X) => f x.
(** [two] should apply [f] twice to its argument: *)
Definition two : nat :=
fun (X : Type) (f : X -> X) (x : X) => f (f x).
(** [zero] is somewhat trickier: how can we apply a function zero
times? The answer is simple: just leave the argument untouched. *)
Definition zero : nat :=
fun (X : Type) (f : X -> X) (x : X) => x.
(** More generally, a number [n] will be written as [fun X f x => f (f
... (f x) ...)], with [n] occurrences of [f]. Notice in particular
how the [doit3times] function we've defined previously is actually
just the representation of [3]. *)
Definition three : nat := @doit3times.
(** Complete the definitions of the following functions. Make sure
that the corresponding unit tests pass by proving them with
[reflexivity]. *)
(** Successor of a natural number *)
Definition succ (n : nat) : nat :=
fun X f x => f (n X f x).
Example succ_1 : succ zero = one.
Proof. reflexivity. Qed.
Example succ_2 : succ one = two.
Proof. reflexivity. Qed.
Example succ_3 : succ two = three.
Proof. reflexivity. Qed.
(** Addition of two natural numbers *)
Definition plus (n m : nat) : nat :=
fun X f x => n X f (m X f x).
Example plus_1 : plus zero one = one.
Proof. reflexivity. Qed.
Example plus_2 : plus two three = plus three two.
Proof. reflexivity. Qed.
Example plus_3 :
plus (plus two two) three = plus one (plus three three).
Proof. reflexivity. Qed.
(** Multiplication *)
Definition mult (n m : nat) : nat :=
fun X f x => n X (m X f) x.
Example mult_1 : mult one one = one.
Proof. reflexivity. Qed.
Example mult_2 : mult zero (plus three three) = zero.
Proof. reflexivity. Qed.
Example mult_3 : mult two three = plus three three.
Proof. reflexivity. Qed.
(** Exponentiation *)
(** Hint: Polymorphism plays a crucial role here. However, choosing
the right type to iterate over can be tricky. If you hit a
"Universe inconsistency" error, try iterating over a different
type: [nat] itself is usually problematic. *)
Definition exp (n m : nat) : nat :=
fun X f x => (m (X -> X) (fun f => (mult n (fun X f x => f x)) X f) (one X f)) x.
Example exp_1 : exp two two = plus two two.
Proof. reflexivity. Qed.
Example exp_2 : exp three two = plus (mult two (mult two two)) one.
Proof. reflexivity. Qed.
Example exp_3 : exp three zero = one.
Proof. reflexivity. Qed.
End Church.
(** [] *)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 14:48:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_vga_pll_0_0 -prefix
// system_vga_pll_0_0_ system_vga_pll_0_0_sim_netlist.v
// Design : system_vga_pll_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_pll_0_0,vga_pll,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_pll,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_pll_0_0
(clk_100,
clk_50,
clk_25,
clk_12_5,
clk_6_25);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_100 CLK" *) input clk_100;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_50 CLK" *) output clk_50;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_25 CLK" *) output clk_25;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_12_5 CLK" *) output clk_12_5;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_6_25 CLK" *) output clk_6_25;
wire clk_100;
wire clk_12_5;
wire clk_25;
wire clk_50;
wire clk_6_25;
system_vga_pll_0_0_vga_pll U0
(.clk_100(clk_100),
.clk_12_5(clk_12_5),
.clk_25(clk_25),
.clk_50(clk_50),
.clk_6_25(clk_6_25));
endmodule
module system_vga_pll_0_0_vga_pll
(clk_50,
clk_25,
clk_12_5,
clk_6_25,
clk_100);
output clk_50;
output clk_25;
output clk_12_5;
output clk_6_25;
input clk_100;
wire clk_100;
wire clk_12_5;
wire clk_12_5_s_i_1_n_0;
wire clk_25;
wire clk_25_s_i_1_n_0;
wire clk_50;
wire clk_6_25;
wire clk_6_25_s_i_1_n_0;
wire p_0_in;
LUT1 #(
.INIT(2'h1))
clk_12_5_s_i_1
(.I0(clk_12_5),
.O(clk_12_5_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_12_5_s_reg
(.C(clk_25),
.CE(1'b1),
.D(clk_12_5_s_i_1_n_0),
.Q(clk_12_5),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_25_s_i_1
(.I0(clk_25),
.O(clk_25_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_25_s_reg
(.C(clk_50),
.CE(1'b1),
.D(clk_25_s_i_1_n_0),
.Q(clk_25),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_50_s_i_1
(.I0(clk_50),
.O(p_0_in));
FDRE #(
.INIT(1'b0))
clk_50_s_reg
(.C(clk_100),
.CE(1'b1),
.D(p_0_in),
.Q(clk_50),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
clk_6_25_s_i_1
(.I0(clk_6_25),
.O(clk_6_25_s_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_6_25_s_reg
(.C(clk_6_25),
.CE(1'b1),
.D(clk_6_25_s_i_1_n_0),
.Q(clk_6_25),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCON_SYMBOL_V
`define SKY130_FD_SC_MS__FAHCON_SYMBOL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fahcon (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT_N,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCON_SYMBOL_V
|
// megafunction wizard: %DDR2 High Performance Controller v15.1%
// GENERATION: XML
// ============================================================
// Megafunction Name(s):
// nios_altmemddr_0_controller_phy
// ============================================================
// Generated by DDR2 High Performance Controller 15.1 [Altera, IP Toolbench 1.3.0 Build 185]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2016 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module nios_altmemddr_0 (
local_address,
local_write_req,
local_read_req,
local_burstbegin,
local_wdata,
local_be,
local_size,
pll_ref_clk,
soft_reset_n,
global_reset_n,
local_ready,
local_rdata,
local_rdata_valid,
local_refresh_ack,
local_init_done,
reset_phy_clk_n,
mem_odt,
mem_cs_n,
mem_cke,
mem_addr,
mem_ba,
mem_ras_n,
mem_cas_n,
mem_we_n,
mem_dm,
phy_clk,
aux_full_rate_clk,
aux_half_rate_clk,
reset_request_n,
mem_clk,
mem_clk_n,
mem_dq,
mem_dqs);
input [23:0] local_address;
input local_write_req;
input local_read_req;
input local_burstbegin;
input [31:0] local_wdata;
input [3:0] local_be;
input [2:0] local_size;
input pll_ref_clk;
input soft_reset_n;
input global_reset_n;
output local_ready;
output [31:0] local_rdata;
output local_rdata_valid;
output local_refresh_ack;
output local_init_done;
output reset_phy_clk_n;
output [0:0] mem_odt;
output [0:0] mem_cs_n;
output [0:0] mem_cke;
output [13:0] mem_addr;
output [1:0] mem_ba;
output mem_ras_n;
output mem_cas_n;
output mem_we_n;
output [0:0] mem_dm;
output phy_clk;
output aux_full_rate_clk;
output aux_half_rate_clk;
output reset_request_n;
inout [0:0] mem_clk;
inout [0:0] mem_clk_n;
inout [7:0] mem_dq;
inout [0:0] mem_dqs;
wire signal_wire0 = 1'b0;
wire [13:0] signal_wire1 = 14'b0;
wire [13:0] signal_wire2 = 14'b0;
wire [5:0] signal_wire3 = 6'b0;
wire [5:0] signal_wire4 = 6'b0;
wire signal_wire5 = 1'b0;
wire [7:0] signal_wire6 = 8'b0;
wire [0:0] signal_wire7 = 1'b0;
wire [0:0] signal_wire8 = 1'b0;
wire [0:0] signal_wire9 = 1'b0;
wire [0:0] signal_wire10 = 1'b0;
wire [0:0] signal_wire11 = 1'b0;
wire signal_wire12 = 1'b0;
wire signal_wire13 = 1'b0;
wire signal_wire14 = 1'b0;
wire signal_wire15 = 1'b0;
wire [3:0] signal_wire16 = 4'b0;
wire [2:0] signal_wire17 = 3'b0;
wire signal_wire18 = 1'b0;
wire [8:0] signal_wire19 = 9'b0;
wire [3:0] signal_wire20 = 4'b0;
wire signal_wire21 = 1'b0;
wire signal_wire22 = 1'b0;
wire signal_wire23 = 1'b0;
wire signal_wire24 = 1'b0;
wire signal_wire25 = 1'b0;
wire signal_wire26 = 1'b0;
wire signal_wire27 = 1'b0;
wire signal_wire28 = 1'b0;
nios_altmemddr_0_controller_phy nios_altmemddr_0_controller_phy_inst(
.local_address(local_address),
.local_write_req(local_write_req),
.local_read_req(local_read_req),
.local_burstbegin(local_burstbegin),
.local_wdata(local_wdata),
.local_be(local_be),
.local_size(local_size),
.local_refresh_req(signal_wire0),
.oct_ctl_rs_value(signal_wire1),
.oct_ctl_rt_value(signal_wire2),
.dqs_delay_ctrl_import(signal_wire3),
.dqs_offset_delay_ctrl(signal_wire4),
.hc_scan_enable_access(signal_wire5),
.hc_scan_enable_dq(signal_wire6),
.hc_scan_enable_dm(signal_wire7),
.hc_scan_enable_dqs(signal_wire8),
.hc_scan_enable_dqs_config(signal_wire9),
.hc_scan_din(signal_wire10),
.hc_scan_update(signal_wire11),
.hc_scan_ck(signal_wire12),
.pll_reconfig_write_param(signal_wire13),
.pll_reconfig_read_param(signal_wire14),
.pll_reconfig(signal_wire15),
.pll_reconfig_counter_type(signal_wire16),
.pll_reconfig_counter_param(signal_wire17),
.pll_reconfig_soft_reset_en_n(signal_wire18),
.pll_reconfig_data_in(signal_wire19),
.pll_phasecounterselect(signal_wire20),
.pll_phaseupdown(signal_wire21),
.pll_phasestep(signal_wire22),
.pll_reconfig_enable(signal_wire23),
.local_autopch_req(signal_wire24),
.local_self_rfsh_req(signal_wire25),
.local_self_rfsh_chip(signal_wire26),
.local_multicast_req(signal_wire27),
.local_refresh_chip(signal_wire28),
.pll_ref_clk(pll_ref_clk),
.soft_reset_n(soft_reset_n),
.global_reset_n(global_reset_n),
.local_ready(local_ready),
.local_rdata(local_rdata),
.local_rdata_valid(local_rdata_valid),
.local_refresh_ack(local_refresh_ack),
.local_init_done(local_init_done),
.reset_phy_clk_n(reset_phy_clk_n),
.dll_reference_clk(),
.dqs_delay_ctrl_export(),
.hc_scan_dout(),
.pll_reconfig_busy(),
.pll_reconfig_clk(),
.pll_reconfig_reset(),
.pll_reconfig_data_out(),
.pll_phase_done(),
.aux_scan_clk_reset_n(),
.aux_scan_clk(),
.local_self_rfsh_ack(),
.local_power_down_ack(),
.mem_odt(mem_odt),
.mem_cs_n(mem_cs_n),
.mem_cke(mem_cke),
.mem_addr(mem_addr),
.mem_ba(mem_ba),
.mem_ras_n(mem_ras_n),
.mem_cas_n(mem_cas_n),
.mem_we_n(mem_we_n),
.mem_dm(mem_dm),
.mem_reset_n(),
.phy_clk(phy_clk),
.aux_full_rate_clk(aux_full_rate_clk),
.aux_half_rate_clk(aux_half_rate_clk),
.reset_request_n(reset_request_n),
.mem_clk(mem_clk),
.mem_clk_n(mem_clk_n),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dqsn());
endmodule
// =========================================================
// DDR2 High Performance Controller Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, DDR2 High Performance Controller Wizard may not be able to reproduce your chosen configuration.
//
// Retrieval info: <?xml version="1.0"?>
// Retrieval info: <MEGACORE title="DDR2 SDRAM Controller with ALTMEMPHY" version="15.1" build="185" iptb_version="1.3.0 Build 185" format_version="120" >
// Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.DDRControllerMVCModel" active_core="nios_altmemddr_0_controller_phy" >
// Retrieval info: <STATIC_SECTION>
// Retrieval info: <PRIVATES>
// Retrieval info: <NAMESPACE name = "parameterization">
// Retrieval info: <PRIVATE name = "debug_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pipeline_commands" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "use_generated_memory_model" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "export_debug_port" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_clk_mhz_label" value="62.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_ref_clk_ps_label" value="(20000 ps)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_ref_clk_mhz" value="50.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_mhz" value="125.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_drate" value="Half" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "project_family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enable_v72_rsu" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_ps_label" value="(8000 ps)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_memtype" value="DDR2 SDRAM" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "new_variant" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "quartus_project_exists" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "speed_grade" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase_label" value="Dedicated memory clock phase:" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "avalon_burst_length" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_pchaddr_bit" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dm_pins_en" value="Yes" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dwidth" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_fmax" value="266.667" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pre_latency_label" value="Fix read latency at:" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_9" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_8" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_7" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dyn_deskew_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "chip_or_dimm" value="Discrete Device" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_bankaddr_width" value="2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dq_per_dqs" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "vendor" value="JEDEC" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_preset" value="JEDEC DDR2-533 512Mb x8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "fast_simulation_en" value="FAST" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_width" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_per_dimm" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_pair_count" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "post_latency_label" value="cycles (0 cycles=minimum latency, non-deterministic)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_13" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_dwidth_label" value="32" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_12" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_15" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_14" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_coladdr_width" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_11" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "WIDTH_RATIO" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_10" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_per_rank" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_rowaddr_width" value="14" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_2" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_1" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_0" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_size" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_6" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_5" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_preset_rlat" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_4" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mirror_addressing" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_3" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tras_ns" value="45.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_twr_ns" value="15.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdss_ck" value="0.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trefi_us" value="7.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdha_ps" value="350" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqsck_ps" value="450" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trfc_ns" value="105.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trp_ns" value="15.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqss_ck" value="0.25" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tfaw_ns" value="37.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqsq_ps" value="300" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdsh_ck" value="0.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tqhs_ps" value="400" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tinit_us" value="200.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tqh_ck" value="0.36" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_trrd_ns" value="7.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tiha_ps" value="500" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tac_ps" value="500" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tisa_ps" value="500" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tmrd_ns" value="7.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdsa_ps" value="350" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_twtr_ck" value="2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_trtp_ns" value="7.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trcd_ns" value="15.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_drv_str" value="Normal" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_50_fmax" value="266.667" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_25_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_reconfig_ports_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dqsn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_btype" value="Sequential" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DSS_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ac_phase" value="90" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_QH_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dll_en" value="Yes" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_IS_percent" value="0.7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSCK_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DSH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_odt" value="Disabled" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enable_mp_calibration" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DS_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_30_fmax" value="200.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DH_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSQ_percent" value="0.65" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_40_fmax" value="266.667" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_IH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_15_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_60_fmax" value="266.667" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_oct_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "input_period" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_WLS_percent" value="0.7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_bl" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_WLH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "export_bank_info" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_20_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSS_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dll_external" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_QHS_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl" value="4.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ac_clk_select" value="90" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_powerdn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_lookahead_depth" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_autopch_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_dynamic_bank_allocation" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "multicast_wr_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_hrb_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "controller_type" value="ngv110_ctl" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_dynamic_bank_num" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_ecc_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "phy_if_type_afi" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "qsys_mode" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "shared_sys_clk_source" value="XX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "auto_powerdn_cycles" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "user_refresh_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_self_refresh_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_auto_correct_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_type_avalon" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "burst_merge_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_data_reordering_type" value="INTER_BANK" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "tool_context" value="SOPC_BUILDER" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_addr_mapping" value="CHIP_ROW_BANK_COL" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_starve_limit" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "auto_powerdn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_latency" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ref_clk_source" value="clk_0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "clk_source_sharing_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_reorder_data" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "max_local_size" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "csr_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_rtt_nom" value="ODT Disabled" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_srtr" value="Normal" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_mpr_loc" value="Predefined Pattern" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_rtt_wr" value="Dynamic ODT off" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dss_tinit_rst_us" value="200.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_asrm" value="Manual SR Reference (SRT)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_80_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_mpr_oper" value="Predefined Pattern" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dll_pch" value="Fast Exit" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_90_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_atcl" value="Disabled" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_wtcl" value="5.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_drv_impedance" value="RZQ/7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_70_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_100_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_pasr" value="Full Array" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DS_calculated" value="0.350" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dq_slew_rate" value="1.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_minCK_DQS_skew" value="-0.01" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DS" value="0.35" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_maxCK_DQS_skew" value="0.01" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "num_slots_or_devices" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_inter_DQS_group_skew" value="0.02" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "addr_cmd_slew_rate" value="1.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IS_calculated" value="0.500" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DH" value="0.35" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IH_calculated" value="0.500" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_tpd_inter_DIMM" value="0.05" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_skew_ps" value="20" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dqs_dqsn_slew_rate" value="2.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IS" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_intra_DQS_group_skew" value="0.02" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DH_calculated" value="0.350" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_addresscmd_hold" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_addresscmd_setup" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ck_ckn_slew_rate" value="2.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "restore_default_toggle" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_settings_valid" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_DQS" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IH" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_addresscmd_CK_skew" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_DQ" value="0.0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen">
// Retrieval info: <PRIVATE name = "use_alt_top" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "alt_top" value="nios_altmemddr_0_alt_mem_ddrx_controller_top" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "nativelink_excludes" value="nios_altmemddr_0_phy_alt_mem_phy_seq.vhd,nios_altmemddr_0_phy_alt_mem_phy_seq_wrapper.vhd,nios_altmemddr_0_phy_alt_mem_phy_seq_wrapper.v" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "filename" value="nios_altmemddr_0_alt_mem_ddrx_controller_top.vo" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen2">
// Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "command" value="--simgen_arbitrary_blackbox=+nios_altmemddr_0_alt_mem_phy_seq_wrapper;+nios_altmemddr_0_alt_mem_phy_reconfig;+nios_altmemddr_0_alt_mem_phy_pll;+nios_altmemddr_0_phy_alt_mem_phy_delay --ini=simgen_tri_bus_opt=on" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "parameter" value="SIMGEN_INITIALIZATION_FILE=/tmp/alt6939_8123991092649822378.dir/0001_iptb_gen/nios_altmemddr_0_simgen_init.txt" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen_enable">
// Retrieval info: <PRIVATE name = "language" value="Verilog HDL" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enabled" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "qip">
// Retrieval info: <PRIVATE name = "gx_libs" value="1" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "greybox">
// Retrieval info: <PRIVATE name = "filename" value="nios_altmemddr_0_syn.v" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "serializer"/>
// Retrieval info: </PRIVATES>
// Retrieval info: <FILES/>
// Retrieval info: <PORTS/>
// Retrieval info: <LIBRARIES/>
// Retrieval info: </STATIC_SECTION>
// Retrieval info: </NETLIST_SECTION>
// Retrieval info: </MEGACORE>
// =========================================================
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 11:05:08 05/26/2016
// Design Name:
// Module Name: microcontrolador
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module microcontrolador
(
input wire clk, reset,
input wire interrupt,
input wire [7:0] in_port,
output wire write_strobe, k_write_strobe, read_strobe,
output wire interrupt_ack,
output wire [7:0] port_id,
output wire [7:0] out_port
);
//Conexiones entre la memoria de programa y el kcpsm6
wire [11:0] address;
wire [17:0] instruction;
wire bram_enable;
wire kcpsm6_sleep;
wire kcpsm6_reset;
wire rdl;
assign kcpsm6_reset = reset | rdl;
assign kcpsm6_sleep = 1'b0;
//Instanciaciones del procesador y la memoria de programa
kcpsm6 #(
.interrupt_vector (12'h3FF),
.scratch_pad_memory_size(64),
.hwbuild (8'h00))
instancia_processor(
.address (address),
.instruction (instruction),
.bram_enable (bram_enable),
.port_id (port_id),
.write_strobe (write_strobe),
.k_write_strobe (k_write_strobe),
.out_port (out_port),
.read_strobe (read_strobe),
.in_port (in_port),
.interrupt (interrupt),
.interrupt_ack (interrupt_ack),
.reset (kcpsm6_reset),
.sleep (kcpsm6_sleep),
.clk (clk));
ROM_programa #(
.C_FAMILY ("S6"), //Family 'S6' or 'V6'
.C_RAM_SIZE_KWORDS (2), //Program size '1', '2' or '4'
.C_JTAG_LOADER_ENABLE (0)) //Include JTAG Loader when set to '1'
instancia_ROM_programa ( //Name to match your PSM file
.rdl (rdl),
.enable (bram_enable),
.address (address),
.instruction (instruction),
.clk (clk));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__HA_BLACKBOX_V
`define SKY130_FD_SC_HD__HA_BLACKBOX_V
/**
* ha: Half adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__ha (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__HA_BLACKBOX_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pci_exp_4_lane_64b_ep.v
// Version : 1.7
module v6_pcie_v1_7 (
//-------------------------------------------------------
// 1. PCI Express (pci_exp) Interface
//-------------------------------------------------------
// Tx
pci_exp_txp,
pci_exp_txn,
// Rx
pci_exp_rxp,
pci_exp_rxn,
//-------------------------------------------------------
// 2. Transaction (TRN) Interface
//-------------------------------------------------------
// Common
trn_clk,
trn_reset_n,
trn_lnk_up_n,
// Tx
trn_tbuf_av,
trn_tcfg_req_n,
trn_terr_drop_n,
trn_tdst_rdy_n,
trn_td,
trn_trem_n,
trn_tsof_n,
trn_teof_n,
trn_tsrc_rdy_n,
trn_tsrc_dsc_n,
trn_terrfwd_n,
trn_tcfg_gnt_n,
trn_tstr_n,
// Rx
trn_rd,
trn_rrem_n,
trn_rsof_n,
trn_reof_n,
trn_rsrc_rdy_n,
trn_rsrc_dsc_n,
trn_rerrfwd_n,
trn_rbar_hit_n,
trn_rdst_rdy_n,
trn_rnp_ok_n,
// Flow Control
trn_fc_cpld,
trn_fc_cplh,
trn_fc_npd,
trn_fc_nph,
trn_fc_pd,
trn_fc_ph,
trn_fc_sel,
//-------------------------------------------------------
// 3. Configuration (CFG) Interface
//-------------------------------------------------------
cfg_do,
cfg_rd_wr_done_n,
cfg_di,
cfg_byte_en_n,
cfg_dwaddr,
cfg_wr_en_n,
cfg_rd_en_n,
cfg_err_cor_n,
cfg_err_ur_n,
cfg_err_ecrc_n,
cfg_err_cpl_timeout_n,
cfg_err_cpl_abort_n,
cfg_err_cpl_unexpect_n,
cfg_err_posted_n,
cfg_err_locked_n,
cfg_err_tlp_cpl_header,
cfg_err_cpl_rdy_n,
cfg_interrupt_n,
cfg_interrupt_rdy_n,
cfg_interrupt_assert_n,
cfg_interrupt_di,
cfg_interrupt_do,
cfg_interrupt_mmenable,
cfg_interrupt_msienable,
cfg_interrupt_msixenable,
cfg_interrupt_msixfm,
cfg_turnoff_ok_n,
cfg_to_turnoff_n,
cfg_trn_pending_n,
cfg_pm_wake_n,
cfg_bus_number,
cfg_device_number,
cfg_function_number,
cfg_status,
cfg_command,
cfg_dstatus,
cfg_dcommand,
cfg_lstatus,
cfg_lcommand,
cfg_dcommand2,
cfg_pcie_link_state_n,
cfg_dsn,
cfg_pmcsr_pme_en,
cfg_pmcsr_pme_status,
cfg_pmcsr_powerstate,
//-------------------------------------------------------
// 4. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
pl_initial_link_width,
pl_lane_reversal_mode,
pl_link_gen2_capable,
pl_link_partner_gen2_supported,
pl_link_upcfg_capable,
pl_ltssm_state,
pl_received_hot_rst,
pl_sel_link_rate,
pl_sel_link_width,
pl_directed_link_auton,
pl_directed_link_change,
pl_directed_link_speed,
pl_directed_link_width,
pl_upstream_prefer_deemph,
//-------------------------------------------------------
// 5. System (SYS) Interface
//-------------------------------------------------------
sys_clk,
sys_reset_n
); //synthesis syn_black_box
//-------------------------------------------------------
// 1. PCI Express (pci_exp) Interface
//-------------------------------------------------------
// Tx
output [(4 - 1):0] pci_exp_txp;
output [(4 - 1):0] pci_exp_txn;
// Rx
input [(4 - 1):0] pci_exp_rxp;
input [(4 - 1):0] pci_exp_rxn;
//-------------------------------------------------------
// 2. Transaction (TRN) Interface
//-------------------------------------------------------
// Common
output trn_clk;
output trn_reset_n;
output trn_lnk_up_n;
// Tx
output [5:0] trn_tbuf_av;
output trn_tcfg_req_n;
output trn_terr_drop_n;
output trn_tdst_rdy_n;
input [63:0] trn_td;
input trn_trem_n;
input trn_tsof_n;
input trn_teof_n;
input trn_tsrc_rdy_n;
input trn_tsrc_dsc_n;
input trn_terrfwd_n;
input trn_tcfg_gnt_n;
input trn_tstr_n;
// Rx
output [63:0] trn_rd;
output trn_rrem_n;
output trn_rsof_n;
output trn_reof_n;
output trn_rsrc_rdy_n;
output trn_rsrc_dsc_n;
output trn_rerrfwd_n;
output [6:0] trn_rbar_hit_n;
input trn_rdst_rdy_n;
input trn_rnp_ok_n;
// Flow Control
output [11:0] trn_fc_cpld;
output [7:0] trn_fc_cplh;
output [11:0] trn_fc_npd;
output [7:0] trn_fc_nph;
output [11:0] trn_fc_pd;
output [7:0] trn_fc_ph;
input [2:0] trn_fc_sel;
//-------------------------------------------------------
// 3. Configuration (CFG) Interface
//-------------------------------------------------------
output [31:0] cfg_do;
output cfg_rd_wr_done_n;
input [31:0] cfg_di;
input [3:0] cfg_byte_en_n;
input [9:0] cfg_dwaddr;
input cfg_wr_en_n;
input cfg_rd_en_n;
input cfg_err_cor_n;
input cfg_err_ur_n;
input cfg_err_ecrc_n;
input cfg_err_cpl_timeout_n;
input cfg_err_cpl_abort_n;
input cfg_err_cpl_unexpect_n;
input cfg_err_posted_n;
input cfg_err_locked_n;
input [47:0] cfg_err_tlp_cpl_header;
output cfg_err_cpl_rdy_n;
input cfg_interrupt_n;
output cfg_interrupt_rdy_n;
input cfg_interrupt_assert_n;
input [7:0] cfg_interrupt_di;
output [7:0] cfg_interrupt_do;
output [2:0] cfg_interrupt_mmenable;
output cfg_interrupt_msienable;
output cfg_interrupt_msixenable;
output cfg_interrupt_msixfm;
input cfg_turnoff_ok_n;
output cfg_to_turnoff_n;
input cfg_trn_pending_n;
input cfg_pm_wake_n;
output [7:0] cfg_bus_number;
output [4:0] cfg_device_number;
output [2:0] cfg_function_number;
output [15:0] cfg_status;
output [15:0] cfg_command;
output [15:0] cfg_dstatus;
output [15:0] cfg_dcommand;
output [15:0] cfg_lstatus;
output [15:0] cfg_lcommand;
output [15:0] cfg_dcommand2;
output [2:0] cfg_pcie_link_state_n;
input [63:0] cfg_dsn;
output cfg_pmcsr_pme_en;
output cfg_pmcsr_pme_status;
output [1:0] cfg_pmcsr_powerstate;
//-------------------------------------------------------
// 4. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
output [2:0] pl_initial_link_width;
output [1:0] pl_lane_reversal_mode;
output pl_link_gen2_capable;
output pl_link_partner_gen2_supported;
output pl_link_upcfg_capable;
output [5:0] pl_ltssm_state;
output pl_received_hot_rst;
output pl_sel_link_rate;
output [1:0] pl_sel_link_width;
input pl_directed_link_auton;
input [1:0] pl_directed_link_change;
input pl_directed_link_speed;
input [1:0] pl_directed_link_width;
input pl_upstream_prefer_deemph;
//-------------------------------------------------------
// 5. System (SYS) Interface
//-------------------------------------------------------
input sys_clk;
input sys_reset_n;
endmodule // v6_pcie_v1_7
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_MUX_2TO1_N_TB_V
`define SKY130_FD_SC_HS__UDP_MUX_2TO1_N_TB_V
/**
* udp_mux_2to1_N: Two to one multiplexer with inverting output
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_mux_2to1_n.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg S;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
S = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 S = 1'b0;
#80 A0 = 1'b1;
#100 A1 = 1'b1;
#120 S = 1'b1;
#140 A0 = 1'b0;
#160 A1 = 1'b0;
#180 S = 1'b0;
#200 S = 1'b1;
#220 A1 = 1'b1;
#240 A0 = 1'b1;
#260 S = 1'bx;
#280 A1 = 1'bx;
#300 A0 = 1'bx;
end
sky130_fd_sc_hs__udp_mux_2to1_N dut (.A0(A0), .A1(A1), .S(S), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_MUX_2TO1_N_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4B_SYMBOL_V
`define SKY130_FD_SC_HS__OR4B_SYMBOL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4B_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2B_TB_V
`define SKY130_FD_SC_HD__NOR2B_TB_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor2b.v"
module top();
// Inputs are registered
reg A;
reg B_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B_N = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B_N = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B_N = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B_N = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B_N = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__nor2b dut (.A(A), .B_N(B_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2B_TB_V
|
module Sec4(
input A,
input B,
input C,
input AnalogLDir,
input AnalogRDir,
output Len,
output Ldir,
output Ren,
output Rdir
);
wire Z_A;
wire Z_B;
wire Z_C;
wire Ldir_int;
wire Len_int;
wire Rdir_int;
wire Ren_int;
wire Analog_select;
supply0 GND;
assign Analog_select = AnalogLDir & AnalogRDir;
inv invA(.A(A), .Z(Z_A));
inv invB(.A(B), .Z(Z_B));
inv invC(.A(C), .Z(Z_C));
section2_schematic lab2Logic(.A(Z_A),
.B(Z_B),
.C(Z_C),
.Ld(Ldir_int),
.Le(Len_int),
.Rd(Rdir_int),
.Re(Ren_int)
);
mux2 mux_1(.d0(AnalogLDir), .d1(Ldir_int), .s(Analog_select), .y(Ldir));
mux2 mux_2(.d0(GND), .d1(Len_int), .s(Analog_select), .y(Len));
mux2 mux_3(.d0(AnalogRDir), .d1(Rdir_int), .s(Analog_select), .y(Rdir));
mux2 mux_4(.d0(GND), .d1(Ren_int), .s(Analog_select), .y(Ren));
endmodule
module mux2(
input d0,
input d1,
input s,
output y);
assign y = (s) ? d1 : d0;
endmodule
module inv (input A,
output Z);
assign Z = ~A;
endmodule
|
//date:2016/3/19
// engineer:ZhaiShaoMin
//module name:BTB module used to cache recent target of jumps and branches
module core_btb(//input
clk,
rst,
pc,
update_btb_tag,
update_btb_target,
btb_target_in,
btb_type_in,
PHT_pred_taken,
//output
btb_type_out,
btb_target_out,
btb_v,
en_btb_pred // only valid when both btb_v and PHT_pred_taken valid are vallid
);
//parameter
parameter pc_tag_width=11;
parameter btb_target_width=32;
parameter btb_depth=64;
parameter BTB_TARGET_INIT=32'h00000000;
parameter BTB_TAG_INIT=11'b00000000000;
//input
input clk;
input rst;
input [31:0] pc;
input [31:0] btb_target_in;
input update_btb_target;
input update_btb_tag;
input [1:0] btb_type_in;
input PHT_pred_taken;
//output
output btb_v;
output [31:0] btb_target_out;
output [1:0] btb_type_out;
output en_btb_pred;
//ram of btb
reg [pc_tag_width-1:0] btb_tag [btb_depth-1:0];
reg [btb_target_width-1:0] btb_target [btb_depth-1:0];
// gen btb_tag_in
wire [5:0] pc_index;
assign pc_index=pc[7:2];
wire [10:0] btb_tag_in;
assign btb_tag_in={pc[29]^pc[28],pc[27]^pc[26],pc[25]^pc[24],pc[23]^pc[22],
pc[21]^pc[20],pc[19]^pc[18],pc[17]^pc[16],pc[15]^pc[14],
pc[13]^pc[12],pc[11]^pc[10],pc[9]^pc[8]};
// write btb tag
always@(posedge clk)
begin
// if(rst)
// begin:tagblock
// integer i;
// for (i=0 ; i<btb_depth; i=i+1)
// begin
// btb_target[pc_index]<=BTB_TARGET_INIT;
// end
// end
//else
if(update_btb_target)
begin
btb_target[pc_index]<={btb_target_in[31:2],btb_type_in};
end
end
//write btb target btb
always@(posedge clk)
begin
// if(rst)
// begin:targetblock
// integer j;
// for (j=0 ; j<btb_depth; j=j+1)
// begin
// btb_tag[pc_index]<=BTB_TAG_INIT;
// end
// end
// else
if(update_btb_tag)
begin
btb_tag[pc_index]<=btb_tag_in;
end
end
reg [31:0] btb_temp;
always@(*)
begin
btb_temp=btb_target[pc_index];
end
reg [10:0] btb_tag_out;
always@(*)
begin
btb_tag_out=btb_tag[pc_index];
end
//read btb
//wire [31:0] btb_temp;
//wire [31:0] btb_target_out;
//wire [1:0] btb_type_out;
//wire [10:0] btb_tag_out;
wire btb_hit;
//assign btb_temp=btb_target[pc_index];
assign btb_target_out={btb_temp[31:2],2'b00};
assign btb_type_out=btb_temp[1:0];
//assign btb_tag_out=btb_tag[pc_index];
assign btb_hit=(btb_tag_out==btb_tag_in);//?1'b1:1'b0;
assign btb_v=btb_hit;
assign en_btb_pred=btb_v&&PHT_pred_taken;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22OI_1_V
`define SKY130_FD_SC_HS__A22OI_1_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22oi_1 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22OI_1_V
|
//=======================================================
// ECE3400 Fall 2017
// Lab 3: Template top-level module
//
// Top-level skeleton from Terasic
// Modified by Claire Chen for ECE3400 Fall 2017
//=======================================================
`define ONE_SEC 25000000
module DE0_NANO(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY,
//////////// SW //////////
SW,
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
GPIO_0_D,
GPIO_0_IN,
//////////// GPIO_0, GPIO_1 connect to GPIO Default //////////
GPIO_1_D,
GPIO_1_IN,
);
//=======================================================
// PARAMETER declarations
//=======================================================
localparam ONE_SEC = 25000000; // one second in 25MHz clock cycles
localparam white = 8'b11111111;
localparam black = 8'b0;
localparam pink = 8'b11110011;
localparam cyan = 8'b10011011;
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
/////////// KEY //////////
input [1:0] KEY;
//////////// SW //////////
input [3:0] SW;
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
inout [33:0] GPIO_0_D;
input [1:0] GPIO_0_IN;
//////////// GPIO_0, GPIO_1 connect to GPIO Default //////////
inout [33:0] GPIO_1_D;
input [1:0] GPIO_1_IN;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg CLOCK_25;
wire reset; // active high reset signal
wire [9:0] PIXEL_COORD_X; // current x-coord from VGA driver
wire [9:0] PIXEL_COORD_Y; // current y-coord from VGA driver
reg [7:0] PIXEL_COLOR; // input 8-bit pixel color for current coords
wire [2:0] GRID_X;
wire [2:0] GRID_Y;
reg grid [19:0][7:0];
reg visited [19:0];
GRID_SELECTOR gridSelector(
.CLOCK_50(CLOCK_50),
.PIXEL_COORD_X(PIXEL_COORD_X),
.PIXEL_COORD_Y(PIXEL_COORD_Y),
.GRID_X(GRID_X),
.GRID_Y(GRID_Y)
);
reg[7:0] grid1[3:0] [4:0];
reg[7:0] currentGrid;
reg[24:0] counter;
//state machine
always @(posedge CLOCK_25) begin
if (GRID_X > 3) begin //colors squares that aren't in the 4x5 grid black
PIXEL_COLOR <= black;
end
else begin
currentGrid <= grid1[GRID_X][GRID_Y];
if (currentGrid == 0) begin // if no input, current square white
PIXEL_COLOR <= white;
end
if (currentGrid[0] == 1) begin //if LSB is 1, current square pink
PIXEL_COLOR <= pink;
end
end
end
reg[2:0] x;
reg[2:0] y;
//demo
// always @(posedge CLOCK_25) begin
// if (reset) begin
// counter <= 25'b0;
// x <= 3'b0;
// y <= 3'b0;
// end
// if (counter == ONE_SEC) begin
// counter <= 25'b0;
// x <= x + 3'b1;
// y <= y + 3'b1;
//
// grid1[x][y] <= 8'b1;
// end
//
// else begin
// counter <= counter+ 25'b1;
// end
// end
//assign GPIO_0_D[31] = 1'd1;
//assign GPIO_0_D[33] = 1'd1;
reg [24:0] led_counter; // timer to keep track of when to toggle LED
reg led_state; // 1 is on, 0 is off
// Module outputs coordinates of next pixel to be written onto screen
VGA_DRIVER driver(
.RESET(reset),
.CLOCK(CLOCK_25),
.PIXEL_COLOR_IN(PIXEL_COLOR),
.PIXEL_X(PIXEL_COORD_X),
.PIXEL_Y(PIXEL_COORD_Y),
.PIXEL_COLOR_OUT({GPIO_0_D[9],GPIO_0_D[11],GPIO_0_D[13],GPIO_0_D[15],GPIO_0_D[17],GPIO_0_D[19],GPIO_0_D[21],GPIO_0_D[23]}),
.H_SYNC_NEG(GPIO_0_D[7]),
.V_SYNC_NEG(GPIO_0_D[5])
);
assign reset = ~KEY[0]; // reset when KEY0 is pressed
// assign PIXEL_COLOR = 8'b000_111_00; // Green
assign LED[0] = led_state;
//=======================================================
// Structural coding
//=======================================================
// Generate 25MHz clock for VGA, FPGA has 50 MHz clock
always @ (posedge CLOCK_50) begin
CLOCK_25 <= ~CLOCK_25;
end // always @ (posedge CLOCK_50)
// Simple state machine to toggle LED0 every one second
always @ (posedge CLOCK_25) begin
if (reset) begin
led_state <= 1'b0;
led_counter <= 25'b0;
x <= 3'b0;
y <= 3'b0;
grid1[0][0] = 8'b0;
grid1[0][1] = 8'b0;
grid1[0][2] = 8'b0;
grid1[0][3] = 8'b0;
grid1[0][4] = 8'b0;
grid1[1][0] = 8'b0;
grid1[1][1] = 8'b0;
grid1[1][2] = 8'b0;
grid1[1][3] = 8'b0;
grid1[1][4] = 8'b0;
grid1[2][0] = 8'b0;
grid1[2][1] = 8'b0;
grid1[2][2] = 8'b0;
grid1[2][3] = 8'b0;
grid1[2][4] = 8'b0;
grid1[3][0] = 8'b0;
grid1[3][1] = 8'b0;
grid1[3][2] = 8'b0;
grid1[3][3] = 8'b0;
grid1[3][4] = 8'b0;
end
if (led_counter == ONE_SEC) begin
led_state <= ~led_state;
led_counter <= 25'b0;
if (y==3'b100) begin // you're at the bottom of the grid
y<= 3'b0;
x<=x+3'b001;
end
else begin
y <= y + 3'b1;
end
grid1[x][y] <= 8'b1;
end
else begin
led_state <= led_state;
led_counter <= led_counter + 25'b1;
end // always @ (posedge CLOCK_25)
end
endmodule |
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description :
// / /
// /__/ /\ Filename : GTXE2_COMMON.uniprim.v
// \ \ / \
// \__\/\__ \
//
// Generated by : /home/chen/xfoundry/HEAD/env/Databases/CAEInterfaces/LibraryWriters/bin/ltw.pl
// Revision: 1.0
// 01/18/13 - 695630 - added drp monitor
// 08/29/14 - 821138 - add negedge specify section for IS_INVERTED*CLK*
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTXE2_COMMON (
DRPDO,
DRPRDY,
QPLLDMONITOR,
QPLLFBCLKLOST,
QPLLLOCK,
QPLLOUTCLK,
QPLLOUTREFCLK,
QPLLREFCLKLOST,
REFCLKOUTMONITOR,
BGBYPASSB,
BGMONITORENB,
BGPDB,
BGRCALOVRD,
DRPADDR,
DRPCLK,
DRPDI,
DRPEN,
DRPWE,
GTGREFCLK,
GTNORTHREFCLK0,
GTNORTHREFCLK1,
GTREFCLK0,
GTREFCLK1,
GTSOUTHREFCLK0,
GTSOUTHREFCLK1,
PMARSVD,
QPLLLOCKDETCLK,
QPLLLOCKEN,
QPLLOUTRESET,
QPLLPD,
QPLLREFCLKSEL,
QPLLRESET,
QPLLRSVD1,
QPLLRSVD2,
RCALENB
);
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED";
`endif
parameter [63:0] BIAS_CFG = 64'h0000040000001000;
parameter [31:0] COMMON_CFG = 32'h00000000;
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0;
parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0;
parameter [26:0] QPLL_CFG = 27'h0680181;
parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000;
parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000;
parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0;
parameter [9:0] QPLL_CP = 10'b0000011111;
parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0;
parameter [0:0] QPLL_DMONITOR_SEL = 1'b0;
parameter [9:0] QPLL_FBDIV = 10'b0000000000;
parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0;
parameter [0:0] QPLL_FBDIV_RATIO = 1'b0;
parameter [23:0] QPLL_INIT_CFG = 24'h000006;
parameter [15:0] QPLL_LOCK_CFG = 16'h21E8;
parameter [3:0] QPLL_LPF = 4'b1111;
parameter integer QPLL_REFCLK_DIV = 2;
parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001;
parameter SIM_RESET_SPEEDUP = "TRUE";
parameter SIM_VERSION = "4.0";
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
output DRPRDY;
output QPLLFBCLKLOST;
output QPLLLOCK;
output QPLLOUTCLK;
output QPLLOUTREFCLK;
output QPLLREFCLKLOST;
output REFCLKOUTMONITOR;
output [15:0] DRPDO;
output [7:0] QPLLDMONITOR;
input BGBYPASSB;
input BGMONITORENB;
input BGPDB;
input DRPCLK;
input DRPEN;
input DRPWE;
input GTGREFCLK;
input GTNORTHREFCLK0;
input GTNORTHREFCLK1;
input GTREFCLK0;
input GTREFCLK1;
input GTSOUTHREFCLK0;
input GTSOUTHREFCLK1;
input QPLLLOCKDETCLK;
input QPLLLOCKEN;
input QPLLOUTRESET;
input QPLLPD;
input QPLLRESET;
input RCALENB;
input [15:0] DRPDI;
input [15:0] QPLLRSVD1;
input [2:0] QPLLREFCLKSEL;
input [4:0] BGRCALOVRD;
input [4:0] QPLLRSVD2;
input [7:0] DRPADDR;
input [7:0] PMARSVD;
reg SIM_RESET_SPEEDUP_BINARY;
reg SIM_VERSION_BINARY;
reg [0:0] QPLL_COARSE_FREQ_OVRD_EN_BINARY;
reg [0:0] QPLL_CP_MONITOR_EN_BINARY;
reg [0:0] QPLL_DMONITOR_SEL_BINARY;
reg [0:0] QPLL_FBDIV_MONITOR_EN_BINARY;
reg [0:0] QPLL_FBDIV_RATIO_BINARY;
reg [2:0] SIM_QPLLREFCLK_SEL_BINARY;
reg [3:0] QPLL_CLKOUT_CFG_BINARY;
reg [3:0] QPLL_LPF_BINARY;
reg [4:0] QPLL_REFCLK_DIV_BINARY;
reg [5:0] QPLL_COARSE_FREQ_OVRD_BINARY;
reg [9:0] QPLL_CP_BINARY;
reg [9:0] QPLL_FBDIV_BINARY;
tri0 GSR = glbl.GSR;
reg notifier;
initial begin
case (QPLL_REFCLK_DIV)
2 : QPLL_REFCLK_DIV_BINARY = 5'b00000;
1 : QPLL_REFCLK_DIV_BINARY = 5'b10000;
3 : QPLL_REFCLK_DIV_BINARY = 5'b00001;
4 : QPLL_REFCLK_DIV_BINARY = 5'b00010;
5 : QPLL_REFCLK_DIV_BINARY = 5'b00011;
6 : QPLL_REFCLK_DIV_BINARY = 5'b00101;
8 : QPLL_REFCLK_DIV_BINARY = 5'b00110;
10 : QPLL_REFCLK_DIV_BINARY = 5'b00111;
12 : QPLL_REFCLK_DIV_BINARY = 5'b01101;
16 : QPLL_REFCLK_DIV_BINARY = 5'b01110;
20 : QPLL_REFCLK_DIV_BINARY = 5'b01111;
default : begin
$display("Attribute Syntax Error : The Attribute QPLL_REFCLK_DIV on X_GTXE2_COMMON instance %m is set to %d. Legal values for this attribute are 1 to 20.", QPLL_REFCLK_DIV, 2);
#1 $finish;
end
endcase
case (SIM_RESET_SPEEDUP)
"TRUE" : SIM_RESET_SPEEDUP_BINARY = 0;
"FALSE" : SIM_RESET_SPEEDUP_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_RESET_SPEEDUP on X_GTXE2_COMMON instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RESET_SPEEDUP);
#1 $finish;
end
endcase
case (SIM_VERSION)
"4.0" : SIM_VERSION_BINARY = 0;
"1.0" : SIM_VERSION_BINARY = 0;
"1.1" : SIM_VERSION_BINARY = 0;
"2.0" : SIM_VERSION_BINARY = 0;
"3.0" : SIM_VERSION_BINARY = 0;
"4.1" : SIM_VERSION_BINARY = 0;
"5.0" : SIM_VERSION_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_VERSION on X_GTXE2_COMMON instance %m is set to %s. Legal values for this attribute are 4.0, 1.0, 1.1, 2.0, 3.0, 4.1, or 5.0.", SIM_VERSION);
#1 $finish;
end
endcase
if ((QPLL_CLKOUT_CFG >= 4'b0000) && (QPLL_CLKOUT_CFG <= 4'b1111))
QPLL_CLKOUT_CFG_BINARY = QPLL_CLKOUT_CFG;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_CLKOUT_CFG on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", QPLL_CLKOUT_CFG);
#1 $finish;
end
if ((QPLL_COARSE_FREQ_OVRD >= 6'b000000) && (QPLL_COARSE_FREQ_OVRD <= 6'b111111))
QPLL_COARSE_FREQ_OVRD_BINARY = QPLL_COARSE_FREQ_OVRD;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_COARSE_FREQ_OVRD on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", QPLL_COARSE_FREQ_OVRD);
#1 $finish;
end
if ((QPLL_COARSE_FREQ_OVRD_EN >= 1'b0) && (QPLL_COARSE_FREQ_OVRD_EN <= 1'b1))
QPLL_COARSE_FREQ_OVRD_EN_BINARY = QPLL_COARSE_FREQ_OVRD_EN;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_COARSE_FREQ_OVRD_EN on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_COARSE_FREQ_OVRD_EN);
#1 $finish;
end
if ((QPLL_CP >= 10'b0000000000) && (QPLL_CP <= 10'b1111111111))
QPLL_CP_BINARY = QPLL_CP;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_CP on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", QPLL_CP);
#1 $finish;
end
if ((QPLL_CP_MONITOR_EN >= 1'b0) && (QPLL_CP_MONITOR_EN <= 1'b1))
QPLL_CP_MONITOR_EN_BINARY = QPLL_CP_MONITOR_EN;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_CP_MONITOR_EN on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_CP_MONITOR_EN);
#1 $finish;
end
if ((QPLL_DMONITOR_SEL >= 1'b0) && (QPLL_DMONITOR_SEL <= 1'b1))
QPLL_DMONITOR_SEL_BINARY = QPLL_DMONITOR_SEL;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_DMONITOR_SEL on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_DMONITOR_SEL);
#1 $finish;
end
if ((QPLL_FBDIV >= 10'b0000000000) && (QPLL_FBDIV <= 10'b1111111111))
QPLL_FBDIV_BINARY = QPLL_FBDIV;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_FBDIV on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", QPLL_FBDIV);
#1 $finish;
end
if ((QPLL_FBDIV_MONITOR_EN >= 1'b0) && (QPLL_FBDIV_MONITOR_EN <= 1'b1))
QPLL_FBDIV_MONITOR_EN_BINARY = QPLL_FBDIV_MONITOR_EN;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_FBDIV_MONITOR_EN on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_FBDIV_MONITOR_EN);
#1 $finish;
end
if ((QPLL_FBDIV_RATIO >= 1'b0) && (QPLL_FBDIV_RATIO <= 1'b1))
QPLL_FBDIV_RATIO_BINARY = QPLL_FBDIV_RATIO;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_FBDIV_RATIO on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_FBDIV_RATIO);
#1 $finish;
end
if ((QPLL_LPF >= 4'b0000) && (QPLL_LPF <= 4'b1111))
QPLL_LPF_BINARY = QPLL_LPF;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_LPF on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", QPLL_LPF);
#1 $finish;
end
if ((SIM_QPLLREFCLK_SEL >= 3'b0) && (SIM_QPLLREFCLK_SEL <= 3'b111))
SIM_QPLLREFCLK_SEL_BINARY = SIM_QPLLREFCLK_SEL;
else begin
$display("Attribute Syntax Error : The Attribute SIM_QPLLREFCLK_SEL on X_GTXE2_COMMON instance %m is set to %b. Legal values for this attribute are 3'b0 to 3'b111.", SIM_QPLLREFCLK_SEL);
#1 $finish;
end
end
wire [15:0] delay_DRPDO;
wire [7:0] delay_QPLLDMONITOR;
wire delay_DRPRDY;
wire delay_QPLLFBCLKLOST;
wire delay_QPLLLOCK;
wire delay_QPLLOUTCLK;
wire delay_QPLLOUTREFCLK;
wire delay_QPLLREFCLKLOST;
wire delay_REFCLKOUTMONITOR;
wire [15:0] delay_DRPDI;
wire [15:0] delay_QPLLRSVD1;
wire [2:0] delay_QPLLREFCLKSEL;
wire [4:0] delay_BGRCALOVRD;
wire [4:0] delay_QPLLRSVD2;
wire [7:0] delay_DRPADDR;
wire [7:0] delay_PMARSVD;
wire delay_BGBYPASSB;
wire delay_BGMONITORENB;
wire delay_BGPDB;
wire delay_DRPCLK;
wire delay_DRPEN;
wire delay_DRPWE;
wire delay_GTGREFCLK;
wire delay_GTNORTHREFCLK0;
wire delay_GTNORTHREFCLK1;
wire delay_GTREFCLK0;
wire delay_GTREFCLK1;
wire delay_GTSOUTHREFCLK0;
wire delay_GTSOUTHREFCLK1;
wire delay_QPLLLOCKDETCLK;
wire delay_QPLLLOCKEN;
wire delay_QPLLOUTRESET;
wire delay_QPLLPD;
wire delay_QPLLRESET;
wire delay_RCALENB;
//drp monitor
reg drpen_r1 = 1'b0;
reg drpen_r2 = 1'b0;
reg drpwe_r1 = 1'b0;
reg drpwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge delay_DRPCLK)
begin
// pipeline the DRPEN and DRPWE
drpen_r1 <= delay_DRPEN;
drpwe_r1 <= delay_DRPWE;
drpen_r2 <= drpen_r1;
drpwe_r2 <= drpwe_r1;
// Check - if DRPEN or DRPWE is more than 1 DCLK
if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1))
begin
$display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance");
$finish;
end
if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1))
begin
$display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance");
$finish;
end
//After the 1st DRPEN pulse, check the DRPEN and DRPRDY.
case (sfsm)
FSM_IDLE:
begin
if(delay_DRPEN == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DRPEN, 4 cases can happen
// DRPEN DRPRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRPRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRPRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0)
begin
$display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance");
$finish;
end
//Add the check for another DRPWE pulse
if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0))
begin
$display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance");
$finish;
end
if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM.");
$finish;
end
endcase
end // always @ (posedge delay_DRPCLK)
//end drp monitor
reg [0:0] IS_DRPCLK_INVERTED_REG = IS_DRPCLK_INVERTED;
reg [0:0] IS_GTGREFCLK_INVERTED_REG = IS_GTGREFCLK_INVERTED;
reg [0:0] IS_QPLLLOCKDETCLK_INVERTED_REG = IS_QPLLLOCKDETCLK_INVERTED;
assign #(OUTCLK_DELAY) QPLLOUTCLK = delay_QPLLOUTCLK;
assign #(OUTCLK_DELAY) REFCLKOUTMONITOR = delay_REFCLKOUTMONITOR;
assign #(out_delay) DRPDO = delay_DRPDO;
assign #(out_delay) DRPRDY = delay_DRPRDY;
assign #(out_delay) QPLLDMONITOR = delay_QPLLDMONITOR;
assign #(out_delay) QPLLFBCLKLOST = delay_QPLLFBCLKLOST;
assign #(out_delay) QPLLLOCK = delay_QPLLLOCK;
assign #(out_delay) QPLLOUTREFCLK = delay_QPLLOUTREFCLK;
assign #(out_delay) QPLLREFCLKLOST = delay_QPLLREFCLKLOST;
`ifndef XIL_TIMING // unisim
assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK ^ IS_DRPCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_GTGREFCLK = GTGREFCLK ^ IS_GTGREFCLK_INVERTED_REG;
assign #(INCLK_DELAY) delay_GTNORTHREFCLK0 = GTNORTHREFCLK0;
assign #(INCLK_DELAY) delay_GTNORTHREFCLK1 = GTNORTHREFCLK1;
assign #(INCLK_DELAY) delay_GTREFCLK0 = GTREFCLK0;
assign #(INCLK_DELAY) delay_GTREFCLK1 = GTREFCLK1;
assign #(INCLK_DELAY) delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0;
assign #(INCLK_DELAY) delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1;
assign #(INCLK_DELAY) delay_QPLLLOCKDETCLK = QPLLLOCKDETCLK ^ IS_QPLLLOCKDETCLK_INVERTED_REG;
assign #(in_delay) delay_BGBYPASSB = BGBYPASSB;
assign #(in_delay) delay_BGMONITORENB = BGMONITORENB;
assign #(in_delay) delay_BGPDB = BGPDB;
assign #(in_delay) delay_BGRCALOVRD = BGRCALOVRD;
assign #(in_delay) delay_DRPADDR = DRPADDR;
assign #(in_delay) delay_DRPDI = DRPDI;
assign #(in_delay) delay_DRPEN = DRPEN;
assign #(in_delay) delay_DRPWE = DRPWE;
assign #(in_delay) delay_PMARSVD = PMARSVD;
assign #(in_delay) delay_QPLLLOCKEN = QPLLLOCKEN;
assign #(in_delay) delay_QPLLOUTRESET = QPLLOUTRESET;
assign #(in_delay) delay_QPLLPD = QPLLPD;
assign #(in_delay) delay_QPLLREFCLKSEL = QPLLREFCLKSEL;
assign #(in_delay) delay_QPLLRESET = QPLLRESET;
assign #(in_delay) delay_QPLLRSVD1 = QPLLRSVD1;
assign #(in_delay) delay_QPLLRSVD2 = QPLLRSVD2;
assign #(in_delay) delay_RCALENB = RCALENB;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING //Simprim
assign delay_BGBYPASSB = BGBYPASSB;
assign delay_BGMONITORENB = BGMONITORENB;
assign delay_BGPDB = BGPDB;
assign delay_BGRCALOVRD = BGRCALOVRD;
assign delay_GTGREFCLK = GTGREFCLK;
assign delay_GTNORTHREFCLK0 = GTNORTHREFCLK0;
assign delay_GTNORTHREFCLK1 = GTNORTHREFCLK1;
assign delay_GTREFCLK0 = GTREFCLK0;
assign delay_GTREFCLK1 = GTREFCLK1;
assign delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0;
assign delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1;
assign delay_PMARSVD = PMARSVD;
assign delay_QPLLLOCKDETCLK = QPLLLOCKDETCLK;
assign delay_QPLLLOCKEN = QPLLLOCKEN;
assign delay_QPLLOUTRESET = QPLLOUTRESET;
assign delay_QPLLPD = QPLLPD;
assign delay_QPLLREFCLKSEL = QPLLREFCLKSEL;
assign delay_QPLLRESET = QPLLRESET;
assign delay_QPLLRSVD1 = QPLLRSVD1;
assign delay_QPLLRSVD2 = QPLLRSVD2;
assign delay_RCALENB = RCALENB;
wire drpclk_en_p;
wire drpclk_en_n;
assign drpclk_en_p = ~IS_DRPCLK_INVERTED;
assign drpclk_en_n = IS_DRPCLK_INVERTED;
`endif
B_GTXE2_COMMON #(
.BIAS_CFG (BIAS_CFG),
.COMMON_CFG (COMMON_CFG),
.QPLL_CFG (QPLL_CFG),
.QPLL_CLKOUT_CFG (QPLL_CLKOUT_CFG),
.QPLL_COARSE_FREQ_OVRD (QPLL_COARSE_FREQ_OVRD),
.QPLL_COARSE_FREQ_OVRD_EN (QPLL_COARSE_FREQ_OVRD_EN),
.QPLL_CP (QPLL_CP),
.QPLL_CP_MONITOR_EN (QPLL_CP_MONITOR_EN),
.QPLL_DMONITOR_SEL (QPLL_DMONITOR_SEL),
.QPLL_FBDIV (QPLL_FBDIV),
.QPLL_FBDIV_MONITOR_EN (QPLL_FBDIV_MONITOR_EN),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (QPLL_INIT_CFG),
.QPLL_LOCK_CFG (QPLL_LOCK_CFG),
.QPLL_LPF (QPLL_LPF),
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
.SIM_QPLLREFCLK_SEL (SIM_QPLLREFCLK_SEL),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP),
.SIM_VERSION (SIM_VERSION))
B_GTXE2_COMMON_INST (
.DRPDO (delay_DRPDO),
.DRPRDY (delay_DRPRDY),
.QPLLDMONITOR (delay_QPLLDMONITOR),
.QPLLFBCLKLOST (delay_QPLLFBCLKLOST),
.QPLLLOCK (delay_QPLLLOCK),
.QPLLOUTCLK (delay_QPLLOUTCLK),
.QPLLOUTREFCLK (delay_QPLLOUTREFCLK),
.QPLLREFCLKLOST (delay_QPLLREFCLKLOST),
.REFCLKOUTMONITOR (delay_REFCLKOUTMONITOR),
.BGBYPASSB (delay_BGBYPASSB),
.BGMONITORENB (delay_BGMONITORENB),
.BGPDB (delay_BGPDB),
.BGRCALOVRD (delay_BGRCALOVRD),
.DRPADDR (delay_DRPADDR),
.DRPCLK (delay_DRPCLK),
.DRPDI (delay_DRPDI),
.DRPEN (delay_DRPEN),
.DRPWE (delay_DRPWE),
.GTGREFCLK (delay_GTGREFCLK),
.GTNORTHREFCLK0 (delay_GTNORTHREFCLK0),
.GTNORTHREFCLK1 (delay_GTNORTHREFCLK1),
.GTREFCLK0 (delay_GTREFCLK0),
.GTREFCLK1 (delay_GTREFCLK1),
.GTSOUTHREFCLK0 (delay_GTSOUTHREFCLK0),
.GTSOUTHREFCLK1 (delay_GTSOUTHREFCLK1),
.PMARSVD (delay_PMARSVD),
.QPLLLOCKDETCLK (delay_QPLLLOCKDETCLK),
.QPLLLOCKEN (delay_QPLLLOCKEN),
.QPLLOUTRESET (delay_QPLLOUTRESET),
.QPLLPD (delay_QPLLPD),
.QPLLREFCLKSEL (delay_QPLLREFCLKSEL),
.QPLLRESET (delay_QPLLRESET),
.QPLLRSVD1 (delay_QPLLRSVD1),
.QPLLRSVD2 (delay_QPLLRSVD2),
.RCALENB (delay_RCALENB),
.GSR(GSR)
);
specify
`ifdef XIL_TIMING // Simprim
$period (posedge DRPCLK, 0:0:0, notifier);
$period (negedge DRPCLK, 0:0:0, notifier);
$period (posedge GTGREFCLK, 0:0:0, notifier);
$period (negedge GTGREFCLK, 0:0:0, notifier);
$period (posedge GTNORTHREFCLK0, 0:0:0, notifier);
$period (posedge GTNORTHREFCLK1, 0:0:0, notifier);
$period (posedge GTREFCLK0, 0:0:0, notifier);
$period (posedge GTREFCLK1, 0:0:0, notifier);
$period (posedge GTSOUTHREFCLK0, 0:0:0, notifier);
$period (posedge GTSOUTHREFCLK1, 0:0:0, notifier);
$period (posedge QPLLLOCKDETCLK, 0:0:0, notifier);
$period (negedge QPLLLOCKDETCLK, 0:0:0, notifier);
$period (posedge QPLLOUTCLK, 0:0:0, notifier);
$period (posedge REFCLKOUTMONITOR, 0:0:0, notifier);
$setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE);
$setuphold (negedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR);
$setuphold (negedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI);
$setuphold (negedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN);
$setuphold (negedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE);
$setuphold (negedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR);
$setuphold (negedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI);
$setuphold (negedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN);
$setuphold (negedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE);
`endif
( DRPCLK *> DRPDO) = (0, 0);
( DRPCLK *> DRPRDY) = (0, 0);
( GTGREFCLK *> REFCLKOUTMONITOR) = (0, 0);
( GTNORTHREFCLK0 *> REFCLKOUTMONITOR) = (0, 0);
( GTNORTHREFCLK1 *> REFCLKOUTMONITOR) = (0, 0);
( GTREFCLK0 *> REFCLKOUTMONITOR) = (0, 0);
( GTREFCLK1 *> REFCLKOUTMONITOR) = (0, 0);
( GTSOUTHREFCLK0 *> REFCLKOUTMONITOR) = (0, 0);
( GTSOUTHREFCLK1 *> REFCLKOUTMONITOR) = (0, 0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
// file: system_clk_wiz_1_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1___100.000______0.000______50.0______130.958_____98.575
// clk_out2___166.667______0.000______50.0______118.758_____98.575
// clk_out3___200.000______0.000______50.0______114.829_____98.575
// clk_out4____25.000______0.000______50.0______175.402_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "system_clk_wiz_1_0,clk_wiz_v5_3_3_0,{component_name=system_clk_wiz_1_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module system_clk_wiz_1_0
(
// Clock out ports
output clk_out1,
output clk_out2,
output clk_out3,
output clk_out4,
// Status and control signals
input resetn,
output locked,
// Clock in ports
input clk_in1
);
system_clk_wiz_1_0_clk_wiz inst
(
// Clock out ports
.clk_out1(clk_out1),
.clk_out2(clk_out2),
.clk_out3(clk_out3),
.clk_out4(clk_out4),
// Status and control signals
.resetn(resetn),
.locked(locked),
// Clock in ports
.clk_in1(clk_in1)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:13:50 06/19/2016
// Design Name:
// Module Name: boxmuller_tb
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module boxmuller_tb();
reg [47:0] u0_m[9999:0];
reg [15:0] u1_m[9999:0];
reg [47:0] u0;
reg [15:0] u1;
reg clk, reset;
wire [15:0]x0,x1;
reg [15:0]x0_m[9999:0];
reg [15:0]x1_m[9999:0];
parameter n=256;
integer A,i;
BM_dut bm_12( .clk(clk), .reset(reset),.u0(u0),.u1(u1),.x0(x0),.x1(x1));
initial
begin
clk=0;
reset=0;
$readmemh("taus_u0.txt",u0_m);
$readmemh("taus_u1.txt", u1_m);
$readmemb("x0_bm.txt",x0_m);
$readmemb("x1_bm.txt", x1_m);
end
initial
begin
A=$fopen("BM_tb_result.txt", "w");
for (i=0;i<10000;i=i+1)
begin
#2
u0<=u0_m[i];
u1<=u1_m[i];
#1
if(x0==x0_m[i]&&x1==x1_m[i])
begin
$fwrite( A, "x0: %b and x0_m:%b; ,x1: %b and x1_m: %b are equal \n",x0,x0_m[i],x1,x1_m[i]);
end
else
begin
$fwrite( A, "x0: %b and x0_m:%b; ,x1: %b and x1_m:%b are not equal \n",x0,x0_m[i],x1,x1_m[i]);
end
end
$fclose(A);
end
always
begin
#5
clk<=~clk;
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE DMA WISHBONE Interface ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_dma_wb_if.v,v 1.3 2002-02-01 01:54:45 rudi Exp $
//
// $Date: 2002-02-01 01:54:45 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/10/19 04:35:04 rudi
//
// - Made the core parameterized
//
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.2 2001/06/05 10:22:37 rudi
//
//
// - Added Support of up to 31 channels
// - Added support for 2,4 and 8 priority levels
// - Now can have up to 31 channels
// - Added many configuration items
// - Changed reset to async
//
// Revision 1.1.1.1 2001/03/19 13:10:54 rudi
// Initial Release
//
//
//
`include "wb_dma_defines.v"
module wb_dma_wb_if(clk, rst,
// Wishbone
wbs_data_i, wbs_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o,
wbm_data_i, wbm_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o,
wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i,
// Master
mast_go, mast_we, mast_adr, mast_sel, mast_din, mast_dout, mast_err,
mast_drdy, mast_wait, pt_sel_i, mast_pt_in, mast_pt_out,
// Slave
slv_adr, slv_din, slv_dout, slv_re, slv_we,
pt_sel_o, slv_pt_out, slv_pt_in
);
parameter rf_addr = 0;
input clk, rst;
// --------------------------------------
// WISHBONE INTERFACE
// Slave Interface
input [31:0] wbs_data_i;
output [31:0] wbs_data_o;
input [31:0] wb_addr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
output wb_rty_o;
// Master Interface
input [31:0] wbm_data_i;
output [31:0] wbm_data_o;
output [31:0] wb_addr_o;
output [3:0] wb_sel_o;
output wb_we_o;
output wb_cyc_o;
output wb_stb_o;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
// --------------------------------------
// MASTER INTERFACE
input mast_go; // Perform a Master Cycle (as long as this
// line is asserted)
input mast_we; // Read/Write
input [31:0] mast_adr; // Address for the transfer
input [3:0] mast_sel; // Byte select for DMA transfers
input [31:0] mast_din; // Internal Input Data
output [31:0] mast_dout; // Internal Output Data
output mast_err; // Indicates an error has occurred
output mast_drdy; // Indicated that either data is available
// during a read, or that the master can accept
// the next data during a write
input mast_wait; // Tells the master to insert wait cycles
// because data can not be accepted/provided
// Pass Through Interface
input pt_sel_i; // Pass Through Mode Selected
input [70:0] mast_pt_in; // Grouped WISHBONE inputs
output [34:0] mast_pt_out; // Grouped WISHBONE outputs
// --------------------------------------
// Slave INTERFACE
// This is the register File Interface
output [31:0] slv_adr; // Slave Address
input [31:0] slv_din; // Slave Input Data
output [31:0] slv_dout; // Slave Output Data
output slv_re; // Slave Read Enable
output slv_we; // Slave Write Enable
// Pass through Interface
output pt_sel_o; // Pass Through Mode Active
output [70:0] slv_pt_out; // Grouped WISHBONE out signals
input [34:0] slv_pt_in; // Grouped WISHBONE in signals
////////////////////////////////////////////////////////////////////
//
// Modules
//
wb_dma_wb_mast u0(
.clk( clk ),
.rst( rst ),
.wb_data_i( wbs_data_i ),
.wb_data_o( wbs_data_o ),
.wb_addr_o( wb_addr_o ),
.wb_sel_o( wb_sel_o ),
.wb_we_o( wb_we_o ),
.wb_cyc_o( wb_cyc_o ),
.wb_stb_o( wb_stb_o ),
.wb_ack_i( wb_ack_i ),
.wb_err_i( wb_err_i ),
.wb_rty_i( wb_rty_i ),
.mast_go( mast_go ),
.mast_we( mast_we ),
.mast_adr( mast_adr ),
.mast_sel( mast_sel ),
.mast_din( mast_din ),
.mast_dout( mast_dout ),
.mast_err( mast_err ),
.mast_drdy( mast_drdy ),
.mast_wait( mast_wait ),
.pt_sel( pt_sel_i ),
.mast_pt_in( mast_pt_in ),
.mast_pt_out( mast_pt_out )
);
wb_dma_wb_slv #(rf_addr) u1(
.clk( clk ),
.rst( rst ),
.wb_data_i( wbm_data_i ),
.wb_data_o( wbm_data_o ),
.wb_addr_i( wb_addr_i ),
.wb_sel_i( wb_sel_i ),
.wb_we_i( wb_we_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.wb_ack_o( wb_ack_o ),
.wb_err_o( wb_err_o ),
.wb_rty_o( wb_rty_o ),
.slv_adr( slv_adr ),
.slv_din( slv_din ),
.slv_dout( slv_dout ),
.slv_re( slv_re ),
.slv_we( slv_we ),
.pt_sel( pt_sel_o ),
.slv_pt_out( slv_pt_out ),
.slv_pt_in( slv_pt_in )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A31OI_FUNCTIONAL_PP_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a31oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
B1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
// Local signals
wire B1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31OI_FUNCTIONAL_PP_V |
// megafunction wizard: %ALTGX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt_c3gxb
// ============================================================
// File Name: amm_master_qsys_with_pcie_pcie_ip_altgx_internal.v
// Megafunction Name(s):
// alt_c3gxb
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
//alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="2500 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" equalization_setting=5 equalizer_dcgain_setting=1 gxb_powerdown_width=1 hip_enable="true" loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="auto" pll_control_width=1 pll_divide_by="2" pll_inclk_period=10000 pll_multiply_by="25" pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=1 protocol="pcie" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="indv" rx_channel_width=8 rx_common_mode="0.82v" rx_datapath_protocol="pipe" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_second_order_loop="false" rx_enable_self_test_mode="false" rx_force_signal_detect="false" rx_loop_1_digital_filter=8 rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name="amm_master_qsys_with_pcie_pcie_ip_altgx_internal" transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_bitslip_enable="false" tx_channel_bonding="indv" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="low" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk fixedclk gxb_powerdown hip_tx_clkout pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_areset pll_inclk pll_locked powerdn reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_elecidleinfersel rx_freqlocked rx_patterndetect rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle intended_device_family="Cyclone IV GX"
//VERSION_BEGIN 15.1 cbx_alt_c3gxb 2015:10:21:18:09:22:SJ cbx_altclkbuf 2015:10:21:18:09:22:SJ cbx_altiobuf_bidir 2015:10:21:18:09:22:SJ cbx_altiobuf_in 2015:10:21:18:09:22:SJ cbx_altiobuf_out 2015:10:21:18:09:22:SJ cbx_altpll 2015:10:21:18:09:23:SJ cbx_cycloneii 2015:10:21:18:09:23:SJ cbx_lpm_add_sub 2015:10:21:18:09:23:SJ cbx_lpm_compare 2015:10:21:18:09:23:SJ cbx_lpm_counter 2015:10:21:18:09:23:SJ cbx_lpm_decode 2015:10:21:18:09:23:SJ cbx_lpm_mux 2015:10:21:18:09:23:SJ cbx_mgl 2015:10:21:18:12:49:SJ cbx_nadder 2015:10:21:18:09:23:SJ cbx_stingray 2015:10:21:18:09:22:SJ cbx_stratix 2015:10:21:18:09:23:SJ cbx_stratixii 2015:10:21:18:09:23:SJ cbx_stratixiii 2015:10:21:18:09:23:SJ cbx_stratixv 2015:10:21:18:09:23:SJ cbx_util_mgl 2015:10:21:18:09:23:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=c104"} *)
module amm_master_qsys_with_pcie_pcie_ip_altgx_internal_alt_c3gxb_6ni8
(
cal_blk_clk,
fixedclk,
gxb_powerdown,
hip_tx_clkout,
pipe8b10binvpolarity,
pipedatavalid,
pipeelecidle,
pipephydonestatus,
pipestatus,
pll_areset,
pll_inclk,
pll_locked,
powerdn,
reconfig_clk,
reconfig_fromgxb,
reconfig_togxb,
rx_analogreset,
rx_ctrldetect,
rx_datain,
rx_dataout,
rx_digitalreset,
rx_elecidleinfersel,
rx_freqlocked,
rx_patterndetect,
rx_syncstatus,
tx_clkout,
tx_ctrlenable,
tx_datain,
tx_dataout,
tx_detectrxloop,
tx_digitalreset,
tx_forcedispcompliance,
tx_forceelecidle) /* synthesis synthesis_clearbox=2 */;
input cal_blk_clk;
input fixedclk;
input [0:0] gxb_powerdown;
output [0:0] hip_tx_clkout;
input [0:0] pipe8b10binvpolarity;
output [0:0] pipedatavalid;
output [0:0] pipeelecidle;
output [0:0] pipephydonestatus;
output [2:0] pipestatus;
input [0:0] pll_areset;
input [0:0] pll_inclk;
output [0:0] pll_locked;
input [1:0] powerdn;
input reconfig_clk;
output [4:0] reconfig_fromgxb;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
output [0:0] rx_ctrldetect;
input [0:0] rx_datain;
output [7:0] rx_dataout;
input [0:0] rx_digitalreset;
input [2:0] rx_elecidleinfersel;
output [0:0] rx_freqlocked;
output [0:0] rx_patterndetect;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
output [0:0] tx_dataout;
input [0:0] tx_detectrxloop;
input [0:0] tx_digitalreset;
input [0:0] tx_forcedispcompliance;
input [0:0] tx_forceelecidle;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 cal_blk_clk;
tri0 fixedclk;
tri0 [0:0] gxb_powerdown;
tri0 [0:0] pipe8b10binvpolarity;
tri0 [0:0] pll_areset;
tri0 [1:0] powerdn;
tri0 reconfig_clk;
tri0 [0:0] rx_analogreset;
tri0 [0:0] rx_digitalreset;
tri0 [2:0] rx_elecidleinfersel;
tri0 [0:0] tx_ctrlenable;
tri0 [7:0] tx_datain;
tri0 [0:0] tx_detectrxloop;
tri0 [0:0] tx_digitalreset;
tri0 [0:0] tx_forcedispcompliance;
tri0 [0:0] tx_forceelecidle;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
wire [5:0] wire_pll0_clk;
wire wire_pll0_fref;
wire wire_pll0_icdrclk;
wire wire_pll0_locked;
wire wire_cal_blk0_nonusertocmu;
wire wire_cent_unit0_dpriodisableout;
wire wire_cent_unit0_dprioout;
wire wire_cent_unit0_quadresetout;
wire [3:0] wire_cent_unit0_rxanalogresetout;
wire [3:0] wire_cent_unit0_rxcrupowerdown;
wire [3:0] wire_cent_unit0_rxdigitalresetout;
wire [3:0] wire_cent_unit0_rxibpowerdown;
wire [1599:0] wire_cent_unit0_rxpcsdprioout;
wire [1199:0] wire_cent_unit0_rxpmadprioout;
wire [3:0] wire_cent_unit0_txanalogresetout;
wire [3:0] wire_cent_unit0_txdetectrxpowerdown;
wire [3:0] wire_cent_unit0_txdigitalresetout;
wire [3:0] wire_cent_unit0_txdividerpowerdown;
wire [3:0] wire_cent_unit0_txobpowerdown;
wire [599:0] wire_cent_unit0_txpcsdprioout;
wire [1199:0] wire_cent_unit0_txpmadprioout;
wire wire_receive_pcs0_cdrctrlearlyeios;
wire wire_receive_pcs0_cdrctrllocktorefclkout;
wire [399:0] wire_receive_pcs0_dprioout;
wire [8:0] wire_receive_pcs0_hipdataout;
wire wire_receive_pcs0_hipdatavalid;
wire wire_receive_pcs0_hipelecidle;
wire wire_receive_pcs0_hipphydonestatus;
wire [2:0] wire_receive_pcs0_hipstatus;
wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
wire [7:0] wire_receive_pma0_analogtestbus;
wire wire_receive_pma0_clockout;
wire wire_receive_pma0_diagnosticlpbkout;
wire [299:0] wire_receive_pma0_dprioout;
wire wire_receive_pma0_freqlocked;
wire wire_receive_pma0_locktorefout;
wire [9:0] wire_receive_pma0_recoverdataout;
wire wire_receive_pma0_reverselpbkout;
wire wire_receive_pma0_signaldetect;
wire wire_transmit_pcs0_clkout;
wire [9:0] wire_transmit_pcs0_dataout;
wire [149:0] wire_transmit_pcs0_dprioout;
wire wire_transmit_pcs0_forceelecidleout;
wire [2:0] wire_transmit_pcs0_grayelecidleinferselout;
wire wire_transmit_pcs0_hiptxclkout;
wire wire_transmit_pcs0_pipeenrevparallellpbkout;
wire [1:0] wire_transmit_pcs0_pipepowerdownout;
wire [3:0] wire_transmit_pcs0_pipepowerstateout;
wire wire_transmit_pcs0_txdetectrx;
wire wire_transmit_pma0_clockout;
wire wire_transmit_pma0_dataout;
wire [299:0] wire_transmit_pma0_dprioout;
wire wire_transmit_pma0_rxdetectvalidout;
wire wire_transmit_pma0_rxfoundout;
wire wire_transmit_pma0_seriallpbkout;
reg [0:0] fixedclk_div;
reg [1:0] reconfig_togxb_busy_reg;
wire cal_blk_powerdown;
wire [0:0] cent_unit_quadresetout;
wire [3:0] cent_unit_rxcrupowerdn;
wire [3:0] cent_unit_rxibpowerdn;
wire [1599:0] cent_unit_rxpcsdprioin;
wire [1599:0] cent_unit_rxpcsdprioout;
wire [1199:0] cent_unit_rxpmadprioin;
wire [1199:0] cent_unit_rxpmadprioout;
wire [599:0] cent_unit_tx_dprioin;
wire [3:0] cent_unit_txdetectrxpowerdn;
wire [3:0] cent_unit_txdividerpowerdown;
wire [599:0] cent_unit_txdprioout;
wire [3:0] cent_unit_txobpowerdn;
wire [1199:0] cent_unit_txpmadprioin;
wire [1199:0] cent_unit_txpmadprioout;
wire [0:0] fixedclk_div_in;
wire [0:0] fixedclk_enable;
wire [3:0] fixedclk_fast;
wire [0:0] fixedclk_sel;
wire [3:0] fixedclk_to_cmu;
wire [0:0] int_pipeenrevparallellpbkfromtx;
wire [0:0] nonusertocmu_out;
wire [0:0] pipedatavalid_out;
wire [0:0] pipeelecidle_out;
wire [0:0] pll_powerdown;
wire [0:0] reconfig_togxb_busy;
wire [0:0] reconfig_togxb_disable;
wire [0:0] reconfig_togxb_in;
wire [0:0] reconfig_togxb_load;
wire [0:0] refclk_pma;
wire [3:0] rx_analogreset_in;
wire [3:0] rx_analogreset_out;
wire [0:0] rx_deserclock_in;
wire [3:0] rx_digitalreset_in;
wire [3:0] rx_digitalreset_out;
wire [0:0] rx_enapatternalign;
wire [0:0] rx_locktodata;
wire [0:0] rx_locktorefclk_wire;
wire [7:0] rx_out_wire;
wire [1:0] rx_pcs_rxfound_wire;
wire [1599:0] rx_pcsdprioin_wire;
wire [1599:0] rx_pcsdprioout;
wire [0:0] rx_phfifordenable;
wire [0:0] rx_phfiforeset;
wire [0:0] rx_phfifowrdisable;
wire [0:0] rx_pll_pfdrefclkout_wire;
wire [4:0] rx_pma_analogtestbus;
wire [0:0] rx_pma_clockout;
wire [9:0] rx_pma_recoverdataout_wire;
wire [1199:0] rx_pmadprioin_wire;
wire [1199:0] rx_pmadprioout;
wire [0:0] rx_powerdown;
wire [3:0] rx_powerdown_in;
wire [0:0] rx_prbscidenable;
wire [0:0] rx_reverselpbkout;
wire [19:0] rx_revparallelfdbkdata;
wire [0:0] rx_rmfiforeset;
wire [0:0] rx_signaldetect_wire;
wire [3:0] tx_analogreset_out;
wire [0:0] tx_clkout_int_wire;
wire [0:0] tx_core_clkout_wire;
wire [7:0] tx_datain_wire;
wire [9:0] tx_dataout_pcs_to_pma;
wire [0:0] tx_diagnosticlpbkin;
wire [3:0] tx_digitalreset_in;
wire [3:0] tx_digitalreset_out;
wire [599:0] tx_dprioin_wire;
wire [0:0] tx_invpolarity;
wire [0:0] tx_localrefclk;
wire [0:0] tx_pcs_forceelecidleout;
wire [0:0] tx_phfiforeset;
wire [1:0] tx_pipepowerdownout;
wire [3:0] tx_pipepowerstateout;
wire [0:0] tx_pma_fastrefclk0in;
wire [0:0] tx_pma_refclk0in;
wire [0:0] tx_pma_refclk0inpulse;
wire [1199:0] tx_pmadprioin_wire;
wire [1199:0] tx_pmadprioout;
wire [0:0] tx_revparallellpbken;
wire [0:0] tx_rxdetectvalidout;
wire [0:0] tx_rxfoundout;
wire [0:0] tx_serialloopbackout;
wire [599:0] tx_txdprioout;
wire [0:0] txdataout;
wire [0:0] txdetectrxout;
wire [0:0] w_cent_unit_dpriodisableout1w;
altpll pll0
(
.activeclock(),
.areset((pll_areset[0] | pll_powerdown[0])),
.clk(wire_pll0_clk),
.clkbad(),
.clkloss(),
.enable0(),
.enable1(),
.extclk(),
.fbout(),
.fref(wire_pll0_fref),
.icdrclk(wire_pll0_icdrclk),
.inclk({{1{1'b0}}, pll_inclk[0]}),
.locked(wire_pll0_locked),
.phasedone(),
.scandataout(),
.scandone(),
.sclkout0(),
.sclkout1(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkena({6{1'b1}}),
.clkswitch(1'b0),
.configupdate(1'b0),
.extclkena({4{1'b1}}),
.fbin(1'b1),
.pfdena(1'b1),
.phasecounterselect({4{1'b1}}),
.phasestep(1'b1),
.phaseupdown(1'b1),
.pllena(1'b1),
.scanaclr(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0),
.scanread(1'b0),
.scanwrite(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll0.bandwidth_type = "AUTO",
pll0.clk0_divide_by = 2,
pll0.clk0_multiply_by = 25,
pll0.clk1_divide_by = 10,
pll0.clk1_multiply_by = 25,
pll0.clk2_divide_by = 10,
pll0.clk2_duty_cycle = 20,
pll0.clk2_multiply_by = 25,
pll0.dpa_divide_by = 2,
pll0.dpa_multiply_by = 25,
pll0.inclk0_input_frequency = 10000,
pll0.operation_mode = "no_compensation",
pll0.intended_device_family = "Cyclone IV GX",
pll0.lpm_type = "altpll";
cycloneiv_hssi_calibration_block cal_blk0
(
.calibrationstatus(),
.clk(cal_blk_clk),
.nonusertocmu(wire_cal_blk0_nonusertocmu),
.powerdn(cal_blk_powerdown)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.testctrl(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
cycloneiv_hssi_cmu cent_unit0
(
.adet({4{1'b0}}),
.alignstatus(),
.coreclkout(),
.digitaltestout(),
.dpclk(reconfig_clk),
.dpriodisable(reconfig_togxb_disable),
.dpriodisableout(wire_cent_unit0_dpriodisableout),
.dprioin(reconfig_togxb_in),
.dprioload(reconfig_togxb_load),
.dpriooe(),
.dprioout(wire_cent_unit0_dprioout),
.enabledeskew(),
.fiforesetrd(),
.fixedclk({{3{1'b0}}, fixedclk_to_cmu[0]}),
.nonuserfromcal(nonusertocmu_out[0]),
.quadreset(gxb_powerdown[0]),
.quadresetout(wire_cent_unit0_quadresetout),
.rdalign({4{1'b0}}),
.rdenablesync(1'b0),
.recovclk(1'b0),
.refclkout(),
.rxanalogreset({rx_analogreset_in[3:0]}),
.rxanalogresetout(wire_cent_unit0_rxanalogresetout),
.rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
.rxctrl({4{1'b0}}),
.rxctrlout(),
.rxdatain({32{1'b0}}),
.rxdataout(),
.rxdatavalid({4{1'b0}}),
.rxdigitalreset({rx_digitalreset_in[3:0]}),
.rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
.rxibpowerdown(wire_cent_unit0_rxibpowerdown),
.rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
.rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
.rxphfifox4byteselout(),
.rxphfifox4rdenableout(),
.rxphfifox4wrclkout(),
.rxphfifox4wrenableout(),
.rxpmadprioin({cent_unit_rxpmadprioin[1199:0]}),
.rxpmadprioout(wire_cent_unit0_rxpmadprioout),
.rxpowerdown({rx_powerdown_in[3:0]}),
.rxrunningdisp({4{1'b0}}),
.syncstatus({4{1'b0}}),
.testout(),
.txanalogresetout(wire_cent_unit0_txanalogresetout),
.txctrl({4{1'b0}}),
.txctrlout(),
.txdatain({32{1'b0}}),
.txdataout(),
.txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
.txdigitalreset({tx_digitalreset_in[3:0]}),
.txdigitalresetout(wire_cent_unit0_txdigitalresetout),
.txdividerpowerdown(wire_cent_unit0_txdividerpowerdown),
.txobpowerdown(wire_cent_unit0_txobpowerdown),
.txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
.txpcsdprioout(wire_cent_unit0_txpcsdprioout),
.txphfifox4byteselout(),
.txphfifox4rdclkout(),
.txphfifox4rdenableout(),
.txphfifox4wrenableout(),
.txpmadprioin({cent_unit_txpmadprioin[1199:0]}),
.txpmadprioout(wire_cent_unit0_txpmadprioout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.pmacramtest(1'b0),
.refclkdig(1'b0),
.rxcoreclk(1'b0),
.rxphfifordenable(1'b1),
.rxphfiforeset(1'b0),
.rxphfifowrdisable(1'b0),
.scanclk(1'b0),
.scanmode(1'b0),
.scanshift(1'b0),
.testin({2000{1'b0}}),
.txclk(1'b0),
.txcoreclk(1'b0),
.txphfiforddisable(1'b0),
.txphfiforeset(1'b0),
.txphfifowrenable(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
cent_unit0.auto_spd_phystatus_notify_count = 14,
cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
cent_unit0.dprio_config_mode = 8'h01,
cent_unit0.in_xaui_mode = "false",
cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
cent_unit0.rx0_channel_bonding = "none",
cent_unit0.rx0_clk1_mux_select = "recovered clock",
cent_unit0.rx0_clk2_mux_select = "local reference clock",
cent_unit0.rx0_ph_fifo_reg_mode = "true",
cent_unit0.rx0_rd_clk_mux_select = "int clock",
cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.rx0_use_double_data_mode = "false",
cent_unit0.tx0_channel_bonding = "none",
cent_unit0.tx0_rd_clk_mux_select = "central",
cent_unit0.tx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.tx0_use_double_data_mode = "false",
cent_unit0.tx0_wr_clk_mux_select = "int_clk",
cent_unit0.use_coreclk_out_post_divider = "false",
cent_unit0.use_deskew_fifo = "false",
cent_unit0.lpm_type = "cycloneiv_hssi_cmu";
cycloneiv_hssi_rx_pcs receive_pcs0
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(wire_receive_pcs0_cdrctrlearlyeios),
.cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
.clkout(),
.coreclkout(),
.ctrldetect(),
.datain(rx_pma_recoverdataout_wire[9:0]),
.dataout(),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[0]),
.disperr(),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[399:0]),
.dprioout(wire_receive_pcs0_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[0]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hip8b10binvpolarity(pipe8b10binvpolarity[0]),
.hipdataout(wire_receive_pcs0_hipdataout),
.hipdatavalid(wire_receive_pcs0_hipdatavalid),
.hipelecidle(wire_receive_pcs0_hipelecidle),
.hipelecidleinfersel({3{1'b0}}),
.hipphydonestatus(wire_receive_pcs0_hipphydonestatus),
.hippowerdown(powerdn[1:0]),
.hipstatus(wire_receive_pcs0_hipstatus),
.invpol(1'b0),
.k1detect(),
.k2detect(),
.localrefclk(tx_localrefclk[0]),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(),
.phfifooverflow(),
.phfifordenable(rx_phfifordenable[0]),
.phfifordenableout(),
.phfiforeset(rx_phfiforeset[0]),
.phfiforesetout(),
.phfifounderflow(),
.phfifowrdisable(rx_phfifowrdisable[0]),
.phfifowrdisableout(),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipeenrevparallellpbkfromtx(int_pipeenrevparallellpbkfromtx[0]),
.pipephydonestatus(),
.pipepowerdown(tx_pipepowerdownout[1:0]),
.pipepowerstate(tx_pipepowerstateout[3:0]),
.pipestatetransdoneout(),
.pipestatus(),
.prbscidenable(rx_prbscidenable[0]),
.quadreset(cent_unit_quadresetout[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[0]),
.refclk(refclk_pma[0]),
.revbitorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
.rlv(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[0]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[0]),
.rxfound(rx_pcs_rxfound_wire[1:0]),
.signaldetect(),
.signaldetected(rx_signaldetect_wire[0]),
.syncstatus(),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.coreclk(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.pipe8b10binvpolarity(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.revbyteorderwa(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs0.align_pattern = "0101111100",
receive_pcs0.align_pattern_length = 10,
receive_pcs0.allow_align_polarity_inversion = "false",
receive_pcs0.allow_pipe_polarity_inversion = "true",
receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs0.auto_spd_phystatus_notify_count = 14,
receive_pcs0.bit_slip_enable = "false",
receive_pcs0.byte_order_invalid_code_or_run_disp_error = "true",
receive_pcs0.byte_order_mode = "none",
receive_pcs0.byte_order_pad_pattern = "0",
receive_pcs0.byte_order_pattern = "0",
receive_pcs0.byte_order_pld_ctrl_enable = "false",
receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs0.cdrctrl_cid_mode_enable = "true",
receive_pcs0.cdrctrl_enable = "true",
receive_pcs0.cdrctrl_mask_cycle = 800,
receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
receive_pcs0.cdrctrl_rxvalid_mask = "true",
receive_pcs0.channel_bonding = "none",
receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
receive_pcs0.channel_width = 8,
receive_pcs0.clk1_mux_select = "recovered clock",
receive_pcs0.clk2_mux_select = "local reference clock",
receive_pcs0.core_clock_0ppm = "false",
receive_pcs0.datapath_low_latency_mode = "false",
receive_pcs0.datapath_protocol = "pipe",
receive_pcs0.dec_8b_10b_compatibility_mode = "true",
receive_pcs0.dec_8b_10b_mode = "normal",
receive_pcs0.deskew_pattern = "0",
receive_pcs0.disable_auto_idle_insertion = "false",
receive_pcs0.disable_running_disp_in_word_align = "false",
receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs0.dprio_config_mode = 8'h01,
receive_pcs0.elec_idle_gen1_sigdet_enable = "true",
receive_pcs0.elec_idle_infer_enable = "false",
receive_pcs0.elec_idle_num_com_detect = 3,
receive_pcs0.enable_bit_reversal = "false",
receive_pcs0.enable_self_test_mode = "false",
receive_pcs0.force_signal_detect_dig = "true",
receive_pcs0.hip_enable = "true",
receive_pcs0.infiniband_invalid_code = 0,
receive_pcs0.insert_pad_on_underflow = "false",
receive_pcs0.num_align_code_groups_in_ordered_set = 0,
receive_pcs0.num_align_cons_good_data = 16,
receive_pcs0.num_align_cons_pat = 4,
receive_pcs0.num_align_loss_sync_error = 17,
receive_pcs0.ph_fifo_low_latency_enable = "true",
receive_pcs0.ph_fifo_reg_mode = "true",
receive_pcs0.protocol_hint = "pcie",
receive_pcs0.rate_match_back_to_back = "false",
receive_pcs0.rate_match_delete_threshold = 13,
receive_pcs0.rate_match_empty_threshold = 5,
receive_pcs0.rate_match_fifo_mode = "true",
receive_pcs0.rate_match_full_threshold = 20,
receive_pcs0.rate_match_insert_threshold = 11,
receive_pcs0.rate_match_ordered_set_based = "false",
receive_pcs0.rate_match_pattern1 = "11010000111010000011",
receive_pcs0.rate_match_pattern2 = "00101111000101111100",
receive_pcs0.rate_match_pattern_size = 20,
receive_pcs0.rate_match_pipe_enable = "true",
receive_pcs0.rate_match_reset_enable = "false",
receive_pcs0.rate_match_skip_set_based = "true",
receive_pcs0.rate_match_start_threshold = 7,
receive_pcs0.rd_clk_mux_select = "int clock",
receive_pcs0.recovered_clk_mux_select = "recovered clock",
receive_pcs0.run_length = 40,
receive_pcs0.run_length_enable = "true",
receive_pcs0.rx_detect_bypass = "false",
receive_pcs0.rx_phfifo_wait_cnt = 32,
receive_pcs0.rxstatus_error_report_mode = 1,
receive_pcs0.self_test_mode = "incremental",
receive_pcs0.use_alignment_state_machine = "true",
receive_pcs0.use_deskew_fifo = "false",
receive_pcs0.use_double_data_mode = "false",
receive_pcs0.use_parallel_loopback = "false",
receive_pcs0.lpm_type = "cycloneiv_hssi_rx_pcs";
cycloneiv_hssi_rx_pma receive_pma0
(
.analogtestbus(wire_receive_pma0_analogtestbus),
.clockout(wire_receive_pma0_clockout),
.crupowerdn(cent_unit_rxcrupowerdn[0]),
.datain(rx_datain[0]),
.datastrobeout(),
.deserclock(rx_deserclock_in[0]),
.diagnosticlpbkout(wire_receive_pma0_diagnosticlpbkout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[299:0]),
.dprioout(wire_receive_pma0_dprioout),
.freqlocked(wire_receive_pma0_freqlocked),
.locktodata(((~ reconfig_togxb_busy) & rx_locktodata[0])),
.locktoref(rx_locktorefclk_wire[0]),
.locktorefout(wire_receive_pma0_locktorefout),
.powerdn(cent_unit_rxibpowerdn[0]),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
.recoverdataout(wire_receive_pma0_recoverdataout),
.reverselpbkout(wire_receive_pma0_reverselpbkout),
.rxpmareset(rx_analogreset_out[0]),
.seriallpbkin(tx_serialloopbackout[0]),
.signaldetect(wire_receive_pma0_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dpashift(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma0.allow_serial_loopback = "false",
receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
receive_pma0.common_mode = "0.82V",
receive_pma0.deserialization_factor = 10,
receive_pma0.dprio_config_mode = 8'h01,
receive_pma0.effective_data_rate = "2500 Mbps",
receive_pma0.enable_local_divider = "false",
receive_pma0.enable_ltd = "false",
receive_pma0.enable_ltr = "false",
receive_pma0.enable_second_order_loop = "false",
receive_pma0.eq_dc_gain = 3,
receive_pma0.eq_setting = 5,
receive_pma0.force_signal_detect = "false",
receive_pma0.logical_channel_address = (starting_channel_number + 0),
receive_pma0.loop_1_digital_filter = 8,
receive_pma0.offset_cancellation = 1,
receive_pma0.ppm_gen1_2_xcnt_en = 1,
receive_pma0.ppm_post_eidle = 0,
receive_pma0.ppmselect = 8,
receive_pma0.protocol_hint = "pcie",
receive_pma0.signal_detect_hysteresis = 4,
receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
receive_pma0.signal_detect_loss_threshold = 3,
receive_pma0.termination = "OCT 100 Ohms",
receive_pma0.use_external_termination = "false",
receive_pma0.lpm_type = "cycloneiv_hssi_rx_pma";
cycloneiv_hssi_tx_pcs transmit_pcs0
(
.clkout(wire_transmit_pcs0_clkout),
.coreclkout(),
.ctrlenable({{1{1'b0}}, 1'b0}),
.datainfull({22{1'b0}}),
.dataout(wire_transmit_pcs0_dataout),
.digitalreset(tx_digitalreset_out[0]),
.dispval({{1{1'b0}}, 1'b0}),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[149:0]),
.dprioout(wire_transmit_pcs0_dprioout),
.enrevparallellpbk(tx_revparallellpbken[0]),
.forcedisp({{1{1'b0}}, 1'b0}),
.forceelecidleout(wire_transmit_pcs0_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
.hipdatain({tx_forcedispcompliance[0], tx_ctrlenable[0], tx_datain_wire[7:0]}),
.hipdetectrxloop(tx_detectrxloop[0]),
.hipelecidleinfersel(rx_elecidleinfersel[2:0]),
.hipforceelecidle(tx_forceelecidle[0]),
.hippowerdn(powerdn[1:0]),
.hiptxclkout(wire_transmit_pcs0_hiptxclkout),
.invpol(tx_invpolarity[0]),
.localrefclk(tx_localrefclk[0]),
.parallelfdbkout(),
.phfifooverflow(),
.phfiforddisable(1'b0),
.phfiforddisableout(),
.phfiforeset(tx_phfiforeset[0]),
.phfiforesetout(),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(),
.pipeenrevparallellpbkout(wire_transmit_pcs0_pipeenrevparallellpbkout),
.pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
.pipestatetransdone(1'b0),
.quadreset(cent_unit_quadresetout[0]),
.rdenablesync(),
.refclk(refclk_pma[0]),
.revparallelfdbk(rx_revparallelfdbkdata[19:0]),
.txdetectrx(wire_transmit_pcs0_txdetectrx),
.xgmctrlenable(),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.coreclk(1'b0),
.datain({20{1'b0}}),
.detectrxloop(1'b0),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.pipetxswing(1'b0),
.powerdn({2{1'b0}}),
.prbscidenable(1'b0),
.xgmctrl(1'b0),
.xgmdatain({8{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs0.allow_polarity_inversion = "false",
transmit_pcs0.bitslip_enable = "false",
transmit_pcs0.channel_bonding = "none",
transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pcs0.channel_width = 8,
transmit_pcs0.core_clock_0ppm = "false",
transmit_pcs0.datapath_low_latency_mode = "false",
transmit_pcs0.datapath_protocol = "pipe",
transmit_pcs0.disable_ph_low_latency_mode = "false",
transmit_pcs0.disparity_mode = "new",
transmit_pcs0.dprio_config_mode = 8'h01,
transmit_pcs0.elec_idle_delay = 4,
transmit_pcs0.enable_bit_reversal = "false",
transmit_pcs0.enable_idle_selection = "false",
transmit_pcs0.enable_reverse_parallel_loopback = "true",
transmit_pcs0.enable_self_test_mode = "false",
transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
transmit_pcs0.enc_8b_10b_mode = "normal",
transmit_pcs0.hip_enable = "true",
transmit_pcs0.ph_fifo_reg_mode = "true",
transmit_pcs0.prbs_cid_pattern = "false",
transmit_pcs0.protocol_hint = "pcie",
transmit_pcs0.refclk_select = "local",
transmit_pcs0.self_test_mode = "incremental",
transmit_pcs0.use_double_data_mode = "false",
transmit_pcs0.wr_clk_mux_select = "int_clk",
transmit_pcs0.lpm_type = "cycloneiv_hssi_tx_pcs";
cycloneiv_hssi_tx_pma transmit_pma0
(
.cgbpowerdn(cent_unit_txdividerpowerdown[0]),
.clockout(wire_transmit_pma0_clockout),
.datain({tx_dataout_pcs_to_pma[9:0]}),
.dataout(wire_transmit_pma0_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
.diagnosticlpbkin(tx_diagnosticlpbkin[0]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[299:0]),
.dprioout(wire_transmit_pma0_dprioout),
.fastrefclk0in(tx_pma_fastrefclk0in[0]),
.forceelecidle(tx_pcs_forceelecidleout[0]),
.powerdn(cent_unit_txobpowerdn[0]),
.refclk0in(tx_pma_refclk0in[0]),
.refclk0inpulse(tx_pma_refclk0inpulse[0]),
.reverselpbkin(rx_reverselpbkout[0]),
.rxdetecten(txdetectrxout[0]),
.rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
.rxfoundout(wire_transmit_pma0_rxfoundout),
.seriallpbkout(wire_transmit_pma0_seriallpbkout),
.txpmareset(tx_analogreset_out[0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pma0.common_mode = "0.65V",
transmit_pma0.dprio_config_mode = 8'h01,
transmit_pma0.effective_data_rate = "2500 Mbps",
transmit_pma0.enable_diagnostic_loopback = "false",
transmit_pma0.enable_reverse_serial_loopback = "false",
transmit_pma0.logical_channel_address = (starting_channel_number + 0),
transmit_pma0.preemp_tap_1 = 1,
transmit_pma0.protocol_hint = "pcie",
transmit_pma0.rx_detect = 0,
transmit_pma0.serialization_factor = 10,
transmit_pma0.slew_rate = "low",
transmit_pma0.termination = "OCT 100 Ohms",
transmit_pma0.use_external_termination = "false",
transmit_pma0.use_rx_detect = "true",
transmit_pma0.vod_selection = 4,
transmit_pma0.lpm_type = "cycloneiv_hssi_tx_pma";
// synopsys translate_off
initial
fixedclk_div = 0;
// synopsys translate_on
always @ ( posedge fixedclk)
fixedclk_div <= (~ fixedclk_div_in);
// synopsys translate_off
initial
reconfig_togxb_busy_reg = 0;
// synopsys translate_on
always @ ( negedge fixedclk)
reconfig_togxb_busy_reg <= {reconfig_togxb_busy_reg[0], reconfig_togxb_busy};
assign
cal_blk_powerdown = 1'b0,
cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[3:0]},
cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[3:0]},
cent_unit_rxpcsdprioin = {{1200{1'b0}}, rx_pcsdprioout[399:0]},
cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]},
cent_unit_rxpmadprioin = {{900{1'b0}}, rx_pmadprioout[299:0]},
cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1199:0]},
cent_unit_tx_dprioin = {{450{1'b0}}, tx_txdprioout[149:0]},
cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]},
cent_unit_txdividerpowerdown = {wire_cent_unit0_txdividerpowerdown[3:0]},
cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]},
cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[3:0]},
cent_unit_txpmadprioin = {{900{1'b0}}, tx_pmadprioout[299:0]},
cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1199:0]},
fixedclk_div_in = fixedclk_div,
fixedclk_enable = reconfig_togxb_busy_reg[0],
fixedclk_fast = {4{1'b1}},
fixedclk_sel = reconfig_togxb_busy_reg[1],
fixedclk_to_cmu = {((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[3]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk)), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[2]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk)), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[1]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk)), ((((fixedclk_sel & fixedclk_enable) & fixedclk_fast[0]) & fixedclk_div_in) | (((~ fixedclk_sel) & (~ fixedclk_enable)) & fixedclk))},
hip_tx_clkout = {wire_transmit_pcs0_hiptxclkout},
int_pipeenrevparallellpbkfromtx = {wire_transmit_pcs0_pipeenrevparallellpbkout},
nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
pipedatavalid = {pipedatavalid_out[0]},
pipedatavalid_out = {wire_receive_pcs0_hipdatavalid},
pipeelecidle = {pipeelecidle_out[0]},
pipeelecidle_out = {wire_receive_pcs0_hipelecidle},
pipephydonestatus = {wire_receive_pcs0_hipphydonestatus},
pipestatus = {wire_receive_pcs0_hipstatus},
pll_locked = {wire_pll0_locked},
pll_powerdown = 1'b0,
reconfig_fromgxb = {rx_pma_analogtestbus[4:1], wire_cent_unit0_dprioout},
reconfig_togxb_busy = reconfig_togxb[3],
reconfig_togxb_disable = reconfig_togxb[1],
reconfig_togxb_in = reconfig_togxb[0],
reconfig_togxb_load = reconfig_togxb[2],
rx_analogreset_in = {{3{1'b0}}, ((~ reconfig_togxb_busy) & rx_analogreset[0])},
rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[3:0]},
rx_ctrldetect = {wire_receive_pcs0_hipdataout[8]},
rx_dataout = {rx_out_wire[7:0]},
rx_deserclock_in = {wire_pll0_icdrclk},
rx_digitalreset_in = {{3{1'b0}}, rx_digitalreset[0]},
rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]},
rx_enapatternalign = 1'b0,
rx_freqlocked = {(wire_receive_pma0_freqlocked & (~ rx_analogreset[0]))},
rx_locktodata = 1'b0,
rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout},
rx_out_wire = {wire_receive_pcs0_hipdataout[7:0]},
rx_pcs_rxfound_wire = {txdetectrxout[0], tx_rxfoundout[0]},
rx_pcsdprioin_wire = {{1200{1'b0}}, cent_unit_rxpcsdprioout[399:0]},
rx_pcsdprioout = {{1200{1'b0}}, wire_receive_pcs0_dprioout},
rx_phfifordenable = 1'b1,
rx_phfiforeset = 1'b0,
rx_phfifowrdisable = 1'b0,
rx_pll_pfdrefclkout_wire = {wire_pll0_fref},
rx_pma_analogtestbus = {{4{1'b0}}, wire_receive_pma0_analogtestbus[6]},
rx_pma_clockout = {wire_receive_pma0_clockout},
rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[9:0]},
rx_pmadprioin_wire = {{900{1'b0}}, cent_unit_rxpmadprioout[299:0]},
rx_pmadprioout = {{900{1'b0}}, wire_receive_pma0_dprioout},
rx_powerdown = 1'b0,
rx_powerdown_in = {{3{1'b0}}, rx_powerdown[0]},
rx_prbscidenable = 1'b0,
rx_reverselpbkout = {wire_receive_pma0_reverselpbkout},
rx_revparallelfdbkdata = {wire_receive_pcs0_revparallelfdbkdata},
rx_rmfiforeset = 1'b0,
rx_signaldetect_wire = {wire_receive_pma0_signaldetect},
tx_analogreset_out = {wire_cent_unit0_txanalogresetout[3:0]},
tx_clkout = {tx_core_clkout_wire[0]},
tx_clkout_int_wire = {wire_transmit_pcs0_clkout},
tx_core_clkout_wire = {tx_clkout_int_wire[0]},
tx_datain_wire = {tx_datain[7:0]},
tx_dataout = {txdataout[0]},
tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout[9:0]},
tx_diagnosticlpbkin = {wire_receive_pma0_diagnosticlpbkout},
tx_digitalreset_in = {{3{1'b0}}, tx_digitalreset[0]},
tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
tx_dprioin_wire = {{450{1'b0}}, cent_unit_txdprioout[149:0]},
tx_invpolarity = 1'b0,
tx_localrefclk = {wire_transmit_pma0_clockout},
tx_pcs_forceelecidleout = {wire_transmit_pcs0_forceelecidleout},
tx_phfiforeset = 1'b0,
tx_pipepowerdownout = {wire_transmit_pcs0_pipepowerdownout},
tx_pipepowerstateout = {wire_transmit_pcs0_pipepowerstateout},
tx_pma_fastrefclk0in = {wire_pll0_clk[0]},
tx_pma_refclk0in = {wire_pll0_clk[1]},
tx_pma_refclk0inpulse = {wire_pll0_clk[2]},
tx_pmadprioin_wire = {{900{1'b0}}, cent_unit_txpmadprioout[299:0]},
tx_pmadprioout = {{900{1'b0}}, wire_transmit_pma0_dprioout},
tx_revparallellpbken = 1'b0,
tx_rxdetectvalidout = {wire_transmit_pma0_rxdetectvalidout},
tx_rxfoundout = {wire_transmit_pma0_rxfoundout},
tx_serialloopbackout = {wire_transmit_pma0_seriallpbkout},
tx_txdprioout = {{450{1'b0}}, wire_transmit_pcs0_dprioout},
txdataout = {wire_transmit_pma0_dataout},
txdetectrxout = {wire_transmit_pcs0_txdetectrx},
w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
endmodule //amm_master_qsys_with_pcie_pcie_ip_altgx_internal_alt_c3gxb_6ni8
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module amm_master_qsys_with_pcie_pcie_ip_altgx_internal (
cal_blk_clk,
fixedclk,
gxb_powerdown,
pipe8b10binvpolarity,
pll_areset,
pll_inclk,
powerdn,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_datain,
rx_digitalreset,
rx_elecidleinfersel,
tx_ctrlenable,
tx_datain,
tx_detectrxloop,
tx_digitalreset,
tx_forcedispcompliance,
tx_forceelecidle,
hip_tx_clkout,
pipedatavalid,
pipeelecidle,
pipephydonestatus,
pipestatus,
pll_locked,
reconfig_fromgxb,
rx_ctrldetect,
rx_dataout,
rx_freqlocked,
rx_patterndetect,
rx_syncstatus,
tx_clkout,
tx_dataout)/* synthesis synthesis_clearbox = 2 */;
input cal_blk_clk;
input fixedclk;
input [0:0] gxb_powerdown;
input [0:0] pipe8b10binvpolarity;
input [0:0] pll_areset;
input [0:0] pll_inclk;
input [1:0] powerdn;
input reconfig_clk;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [0:0] rx_datain;
input [0:0] rx_digitalreset;
input [2:0] rx_elecidleinfersel;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
input [0:0] tx_detectrxloop;
input [0:0] tx_digitalreset;
input [0:0] tx_forcedispcompliance;
input [0:0] tx_forceelecidle;
output [0:0] hip_tx_clkout;
output [0:0] pipedatavalid;
output [0:0] pipeelecidle;
output [0:0] pipephydonestatus;
output [2:0] pipestatus;
output [0:0] pll_locked;
output [4:0] reconfig_fromgxb;
output [0:0] rx_ctrldetect;
output [7:0] rx_dataout;
output [0:0] rx_freqlocked;
output [0:0] rx_patterndetect;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
output [0:0] tx_dataout;
parameter starting_channel_number = 0;
wire [0:0] sub_wire0;
wire [0:0] sub_wire1;
wire [0:0] sub_wire2;
wire [0:0] sub_wire3;
wire [2:0] sub_wire4;
wire [0:0] sub_wire5;
wire [4:0] sub_wire6;
wire [0:0] sub_wire7;
wire [7:0] sub_wire8;
wire [0:0] sub_wire9;
wire [0:0] sub_wire10;
wire [0:0] sub_wire11;
wire [0:0] sub_wire12;
wire [0:0] sub_wire13;
wire [0:0] hip_tx_clkout = sub_wire0[0:0];
wire [0:0] pipedatavalid = sub_wire1[0:0];
wire [0:0] pipeelecidle = sub_wire2[0:0];
wire [0:0] pipephydonestatus = sub_wire3[0:0];
wire [2:0] pipestatus = sub_wire4[2:0];
wire [0:0] pll_locked = sub_wire5[0:0];
wire [4:0] reconfig_fromgxb = sub_wire6[4:0];
wire [0:0] rx_ctrldetect = sub_wire7[0:0];
wire [7:0] rx_dataout = sub_wire8[7:0];
wire [0:0] rx_freqlocked = sub_wire9[0:0];
wire [0:0] rx_patterndetect = sub_wire10[0:0];
wire [0:0] rx_syncstatus = sub_wire11[0:0];
wire [0:0] tx_clkout = sub_wire12[0:0];
wire [0:0] tx_dataout = sub_wire13[0:0];
amm_master_qsys_with_pcie_pcie_ip_altgx_internal_alt_c3gxb_6ni8 amm_master_qsys_with_pcie_pcie_ip_altgx_internal_alt_c3gxb_6ni8_component (
.cal_blk_clk (cal_blk_clk),
.fixedclk (fixedclk),
.gxb_powerdown (gxb_powerdown),
.pipe8b10binvpolarity (pipe8b10binvpolarity),
.pll_areset (pll_areset),
.pll_inclk (pll_inclk),
.powerdn (powerdn),
.reconfig_clk (reconfig_clk),
.reconfig_togxb (reconfig_togxb),
.rx_analogreset (rx_analogreset),
.rx_datain (rx_datain),
.rx_digitalreset (rx_digitalreset),
.rx_elecidleinfersel (rx_elecidleinfersel),
.tx_ctrlenable (tx_ctrlenable),
.tx_datain (tx_datain),
.tx_detectrxloop (tx_detectrxloop),
.tx_digitalreset (tx_digitalreset),
.tx_forcedispcompliance (tx_forcedispcompliance),
.tx_forceelecidle (tx_forceelecidle),
.hip_tx_clkout (sub_wire0),
.pipedatavalid (sub_wire1),
.pipeelecidle (sub_wire2),
.pipephydonestatus (sub_wire3),
.pipestatus (sub_wire4),
.pll_locked (sub_wire5),
.reconfig_fromgxb (sub_wire6),
.rx_ctrldetect (sub_wire7),
.rx_dataout (sub_wire8),
.rx_freqlocked (sub_wire9),
.rx_patterndetect (sub_wire10),
.rx_syncstatus (sub_wire11),
.tx_clkout (sub_wire12),
.tx_dataout (sub_wire13))/* synthesis synthesis_clearbox=2
clearbox_macroname = alt_c3gxb
clearbox_defparam = "effective_data_rate=2500 Mbps;enable_lc_tx_pll=false;enable_pll_inclk_alt_drive_rx_cru=true;enable_pll_inclk_drive_rx_cru=true;equalizer_dcgain_setting=1;gen_reconfig_pll=false;gx_channel_type=;input_clock_frequency=100.0 MHz;intended_device_family=Cyclone IV GX;intended_device_speed_grade=6;intended_device_variant=ANY;loopback_mode=none;lpm_type=alt_c3gxb;number_of_channels=1;operation_mode=duplex;pll_bandwidth_type=Auto;pll_control_width=1;pll_inclk_period=10000;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=1;protocol=pcie;receiver_termination=oct_100_ohms;reconfig_dprio_mode=0;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=true;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_bonding=indv;rx_channel_width=8;rx_common_mode=0.82v;rx_cru_inclock0_period=10000;rx_datapath_protocol=pipe;rx_data_rate=2500;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=false;rx_ppmselect=8;rx_rate_match_fifo_mode=normal;rx_rate_match_pattern1=11010000111010000011;rx_rate_match_pattern2=00101111000101111100;rx_rate_match_pattern_size=20;rx_run_length=40;rx_run_length_enable=true;rx_signal_detect_threshold=4;rx_use_align_state_machine=true;rx_use_clkout=false;rx_use_coreclk=false;
rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=false;rx_use_pipe8b10binvpolarity=true;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_channel_bonding=indv;tx_channel_width=8;tx_clkout_width=1;tx_common_mode=0.65v;tx_data_rate=2500;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=Auto;tx_pll_inclk0_period=10000;tx_pll_type=CMU;tx_slew_rate=low;tx_transmit_protocol=pipe;tx_use_coreclk=false;tx_use_double_data_mode=false;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=4;elec_idle_infer_enable=false;enable_0ppm=false;equalization_setting=5;gxb_powerdown_width=1;hip_enable=true;iqtxrxclk_allowed=;number_of_quads=1;pll_divide_by=2;pll_multiply_by=25;reconfig_calibration=true;reconfig_fromgxb_port_width=5;reconfig_pll_control_width=1;reconfig_togxb_port_width=4;rx_cdrctrl_enable=true;rx_deskew_pattern=0;rx_dwidth_factor=1;rx_enable_second_order_loop=false;rx_loop_1_digital_filter=8;rx_signal_detect_loss_threshold=3;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;top_module_name=amm_master_qsys_with_pcie_pcie_ip_altgx_internal;tx_bitslip_enable=FALSE;tx_dwidth_factor=1;tx_use_external_termination=false;" */;
defparam
amm_master_qsys_with_pcie_pcie_ip_altgx_internal_alt_c3gxb_6ni8_component.starting_channel_number = starting_channel_number;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: IP_MODE STRING "PCIE_HIP_8"
// Retrieval info: PRIVATE: LOCKDOWN_EXCL STRING "PCIE"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "1"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "1"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0 125.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x1"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "2500 Mbps"
// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_ALT_DRIVE_RX_CRU STRING "true"
// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_DRIVE_RX_CRU STRING "true"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING ""
// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt_c3gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "Auto"
// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: PLL_INCLK_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "indv"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "false"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "8"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "4"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "indv"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "Auto"
// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "low"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
// Retrieval info: CONSTANT: enable_0ppm STRING "false"
// Retrieval info: CONSTANT: equalization_setting NUMERIC "5"
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
// Retrieval info: CONSTANT: hip_enable STRING "true"
// Retrieval info: CONSTANT: iqtxrxclk_allowed STRING ""
// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
// Retrieval info: CONSTANT: pll_divide_by STRING "2"
// Retrieval info: CONSTANT: pll_multiply_by STRING "25"
// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "5"
// Retrieval info: CONSTANT: reconfig_pll_control_width NUMERIC "1"
// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
// Retrieval info: CONSTANT: rx_deskew_pattern STRING "0"
// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: rx_enable_second_order_loop STRING "false"
// Retrieval info: CONSTANT: rx_loop_1_digital_filter NUMERIC "8"
// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
// Retrieval info: CONSTANT: top_module_name STRING "amm_master_qsys_with_pcie_pcie_ip_altgx_internal"
// Retrieval info: CONSTANT: tx_bitslip_enable STRING "FALSE"
// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: hip_tx_clkout 0 0 1 0 OUTPUT NODEFVAL "hip_tx_clkout[0..0]"
// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 1 0 INPUT NODEFVAL "pipe8b10binvpolarity[0..0]"
// Retrieval info: USED_PORT: pipedatavalid 0 0 1 0 OUTPUT NODEFVAL "pipedatavalid[0..0]"
// Retrieval info: USED_PORT: pipeelecidle 0 0 1 0 OUTPUT NODEFVAL "pipeelecidle[0..0]"
// Retrieval info: USED_PORT: pipephydonestatus 0 0 1 0 OUTPUT NODEFVAL "pipephydonestatus[0..0]"
// Retrieval info: USED_PORT: pipestatus 0 0 3 0 OUTPUT NODEFVAL "pipestatus[2..0]"
// Retrieval info: USED_PORT: pll_areset 0 0 1 0 INPUT NODEFVAL "pll_areset[0..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 1 0 INPUT NODEFVAL "pll_inclk[0..0]"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: powerdn 0 0 2 0 INPUT NODEFVAL "powerdn[1..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 OUTPUT NODEFVAL "reconfig_fromgxb[4..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_elecidleinfersel 0 0 3 0 INPUT NODEFVAL "rx_elecidleinfersel[2..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
// Retrieval info: USED_PORT: tx_detectrxloop 0 0 1 0 INPUT NODEFVAL "tx_detectrxloop[0..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 1 0 INPUT NODEFVAL "tx_forcedispcompliance[0..0]"
// Retrieval info: USED_PORT: tx_forceelecidle 0 0 1 0 INPUT NODEFVAL "tx_forceelecidle[0..0]"
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 1 0 pipe8b10binvpolarity 0 0 1 0
// Retrieval info: CONNECT: @pll_areset 0 0 1 0 pll_areset 0 0 1 0
// Retrieval info: CONNECT: @pll_inclk 0 0 1 0 pll_inclk 0 0 1 0
// Retrieval info: CONNECT: @powerdn 0 0 2 0 powerdn 0 0 2 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @rx_elecidleinfersel 0 0 3 0 rx_elecidleinfersel 0 0 3 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0
// Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0
// Retrieval info: CONNECT: @tx_detectrxloop 0 0 1 0 tx_detectrxloop 0 0 1 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 1 0 tx_forcedispcompliance 0 0 1 0
// Retrieval info: CONNECT: @tx_forceelecidle 0 0 1 0 tx_forceelecidle 0 0 1 0
// Retrieval info: CONNECT: hip_tx_clkout 0 0 1 0 @hip_tx_clkout 0 0 1 0
// Retrieval info: CONNECT: pipedatavalid 0 0 1 0 @pipedatavalid 0 0 1 0
// Retrieval info: CONNECT: pipeelecidle 0 0 1 0 @pipeelecidle 0 0 1 0
// Retrieval info: CONNECT: pipephydonestatus 0 0 1 0 @pipephydonestatus 0 0 1 0
// Retrieval info: CONNECT: pipestatus 0 0 3 0 @pipestatus 0 0 3 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 5 0 @reconfig_fromgxb 0 0 5 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0
// Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL amm_master_qsys_with_pcie_pcie_ip_altgx_internal.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL amm_master_qsys_with_pcie_pcie_ip_altgx_internal.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL amm_master_qsys_with_pcie_pcie_ip_altgx_internal.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL amm_master_qsys_with_pcie_pcie_ip_altgx_internal.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL amm_master_qsys_with_pcie_pcie_ip_altgx_internal.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL amm_master_qsys_with_pcie_pcie_ip_altgx_internal_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL amm_master_qsys_with_pcie_pcie_ip_altgx_internal_bb.v FALSE
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18.07.2017 10:30:15
// Design Name:
// Module Name: FPS_Testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPS_10;
integer i_count;
integer o_count;
//inputs
reg CLK;
reg RST;
reg enable;
//outputs
wire In_ack1, In_ack2, In_ack3;
wire In_rdy1, In_rdy2, In_rdy3;
wire Out_send1, Out_send2, Out_send3;
wire all_rdy, all_ack;
ProgNetwork uut
(
//-- XDF Network Input(s)
.In1_data (8'h0),
.In1_send (In_rdy1 & enable),
.In1_ack (In_ack1),
.In1_rdy (In_rdy1),
.In1_count (),
.In2_data (8'h0),
.In2_send (In_rdy2 & enable),
.In2_ack (In_ack2),
.In2_rdy (In_rdy2),
.In2_count (),
.In3_data (8'h0),
.In3_send (In_rdy3 & enable),
.In3_ack (In_ack3),
.In3_rdy (In_rdy3),
.In3_count (),
//-- XDF Network Output(s)
.Out1_data (),
.Out1_send (Out_send1),
.Out1_ack (Out_send1),
.Out1_rdy (enable),
.Out1_count (),
.Out2_data (),
.Out2_send (Out_send2),
.Out2_ack (Out_send2),
.Out2_rdy (enable),
.Out2_count (),
.Out3_data (),
.Out3_send (Out_send3),
.Out3_ack (Out_send3),
.Out3_rdy (enable),
.Out3_count (),
//-- Clock(s) and Reset
.CLK (CLK),
.RESET (RST)
);
initial begin
CLK = 0;
RST = 1;
enable = 0;
i_count = 0;
o_count = 0;
#500;
@(posedge CLK);
RST = 0;
#500;
@(posedge CLK);
enable=1;
end
assign all_rdy = In_rdy1 & In_rdy2 & In_rdy3;
assign all_ack = In_ack1 & In_ack2 & In_ack3;
always CLK = #1 ~CLK;
always@(posedge CLK)
begin
if(i_count == 10*10)
begin
$display("input frame at %d",$time);
i_count <= 0;
end
else
begin
if(all_rdy & all_ack & enable)
i_count <= i_count + 1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXBP_1_V
`define SKY130_FD_SC_MS__DLXBP_1_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog wrapper for dlxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlxbp_1 (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlxbp_1 (
Q ,
Q_N ,
D ,
GATE
);
output Q ;
output Q_N ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXBP_1_V
|
// file: clk_gen.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____50.000______0.000______50.0______123.073_____85.928
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________250.000____________0.010
`timescale 1ps/1ps
module clk_gen_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_clk_gen),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_gen;
wire clkfbout_buf_clk_gen;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (4.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (20.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (4.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_gen),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_clk_gen),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_gen),
.CLKIN1 (clk_in1_clk_gen),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = reset;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_gen),
.I (clkfbout_clk_gen));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_gen));
endmodule
|
(*
Copyright 2014 Cornell University
Copyright 2015 Cornell University
Copyright 2016 Cornell University
Copyright 2017 Cornell University
This file is part of VPrl (the Verified Nuprl project).
VPrl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
VPrl is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VPrl. If not, see <http://www.gnu.org/licenses/>.
Websites: http://nuprl.org/html/verification/
http://nuprl.org/html/Nuprl2Coq
https://github.com/vrahli/NuprlInCoq
Authors: Abhishek Anand & Vincent Rahli
*)
Require Export sequents2.
Require Export rules_useful.
Require Export sequents_useful.
Require Export sequents_tacs.
Require Export sequents_tacs2.
Require Export subst_tacs_aeq.
Require Export cequiv_tacs.
Require Export per_props_requality.
(*
We'll use == for the equality that's inhabited by refl terms as opposed to =,
which we use for the equality that's inhabited by axiom.
*)
(* !!MOVE that somewhere else *)
Definition mk_concl_req {o} (a b T : @NTerm o) : conclusion :=
mk_concl (mk_requality a b T) (mk_refl a).
(* !!MOVE that somewhere else *)
Definition mk_concl_rmem {o} (a T : @NTerm o) : conclusion :=
mk_concl (mk_rmember a T) (mk_refl a).
(**
The following rule says that to prove a conclusion [C] one can
always provide an evidence [t] for that type and prove instead that
[t] is a member of [C]:
<<
H |- C ext t
By introduction t
H |- t == t in C ext refl(t)
>>
*)
Definition rule_introduction_req_concl {o} (H : @bhyps o) C t :=
mk_baresequent H (mk_concl C t).
Definition rule_introduction_req_hyp {o} (H : @bhyps o) C t :=
mk_baresequent H (mk_concl_rmem t C).
Definition rule_introduction_req {o}
(H : @barehypotheses o)
(C t : NTerm) :=
mk_rule
(rule_introduction_req_concl H C t)
[ rule_introduction_req_hyp H C t ]
[ sarg_term t ].
Lemma rule_introduction_req_true3 {o} :
forall lib
(H : @barehypotheses o)
(C t : NTerm),
rule_true3 lib (rule_introduction_req H C t).
Proof.
intros.
unfold rule_introduction_req, rule_true3, wf_bseq, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
repnd.
unfold args_constraints in cargs; allsimpl.
generalize (cargs (sarg_term t) (inl eq_refl)); clear cargs; intro arg1.
unfold arg_constraints in arg1.
(* We prove the well-formedness of things *)
destseq; allsimpl.
dLin_hyp; exrepnd.
destruct Hyp as [ws1 hyp1].
destseq; allsimpl; clear_irr; GC.
assert (wf_csequent (rule_introduction_req_concl H C t)) as wfc.
{ clear hyp1.
unfold wf_csequent, wf_sequent, wf_concl; simpl; dands; auto.
allrw <- @wf_equality_iff; sp. }
exists wfc.
unfold wf_csequent, wf_sequent, wf_concl in wfc; repnd; allsimpl; proof_irr; GC.
vr_seq_true.
vr_seq_true in hyp1.
pose proof (hyp1 s1 s2) as hyp1.
repeat (autodimp hyp1 h).
exrepd.
lsubst_tac.
rw @tequality_mkc_rmember in t0; repnd.
apply equality_in_mkc_rmember in e; exrepnd; computes_to_value_isvalue.
Qed.
Lemma rule_introduction_req_true {o} :
forall lib
(H : @barehypotheses o)
(C t : NTerm),
rule_true lib (rule_introduction_req H C t).
Proof.
introv.
apply rule_true3_implies_rule_true.
apply rule_introduction_req_true3.
Qed.
Lemma rule_introduction_req_wf2 {o} :
forall (H : @barehypotheses o) (C t : NTerm),
wf_term t
-> covered t (vars_hyps H)
-> wf_rule2 (rule_introduction_req H C t).
Proof.
introv wt cov wf m; allsimpl.
repndors; subst; tcsp.
allunfold @wf_bseq; allsimpl; repnd; dands; auto.
- apply wf_equality; auto.
- allunfold @closed_type_baresequent; allsimpl.
allunfold @closed_type; allsimpl.
apply covered_equality; dands; auto.
Qed.
(**
<<
H |- a = b in C ext axiom
By introduction t
H |- a == b in C ext e
>>
*)
Definition rule_squash_equality_concl {o} (H : @bhyps o) a b C :=
mk_baresequent H (mk_conclax (mk_equality a b C)).
Definition rule_squash_equality_hyp {o} (H : @bhyps o) a b C e :=
mk_baresequent H (mk_concl (mk_requality a b C) e).
Definition rule_squash_equality {o}
(H : @barehypotheses o)
(a b C e : NTerm) :=
mk_rule
(rule_squash_equality_concl H a b C)
[ rule_squash_equality_hyp H a b C e ]
[ ].
Lemma rule_squash_equality_true3 {o} :
forall lib
(H : @barehypotheses o)
(a b C e : NTerm),
rule_true3 lib (rule_squash_equality H a b C e).
Proof.
intros.
unfold rule_squash_equality, rule_true3, wf_bseq, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
repnd.
clear cargs.
(* We prove the well-formedness of things *)
destseq; allsimpl.
dLin_hyp; exrepnd.
destruct Hyp as [ws1 hyp1].
destseq; allsimpl; clear_irr; GC.
assert (wf_csequent (rule_squash_equality_concl H a b C)) as wfc.
{ clear hyp1.
unfold wf_csequent, wf_sequent, wf_concl; simpl; dands; auto; eauto 3 with slow.
unfold closed_extract; simpl.
apply covered_axiom. }
exists wfc.
unfold wf_csequent, wf_sequent, wf_concl in wfc; repnd; allsimpl; proof_irr; GC.
vr_seq_true.
vr_seq_true in hyp1.
pose proof (hyp1 s1 s2) as hyp1.
repeat (autodimp hyp1 h).
exrepd.
lsubst_tac.
rw @tequality_mkc_requality in t; repnd.
rw @equality_in_mkc_requality in e0; exrepnd; computes_to_value_isvalue.
rw @tequality_mkc_equality.
rw <- @member_equality_iff.
dands; auto.
Qed.
(**
<<
H |- a == b in C ext refl(a)
By introduction t
H |- a = b in C ext e
>>
*)
Definition rule_unsquash_equality_concl {o} (H : @bhyps o) a b C :=
mk_baresequent H (mk_concl_req a b C).
Definition rule_unsquash_equality_hyp {o} (H : @bhyps o) a b C e :=
mk_baresequent H (mk_concl (mk_equality a b C) e).
Definition rule_unsquash_equality {o}
(H : @barehypotheses o)
(a b C e : NTerm) :=
mk_rule
(rule_unsquash_equality_concl H a b C)
[ rule_unsquash_equality_hyp H a b C e ]
[ sarg_term a ].
Lemma rule_unsquash_equality_true3 {o} :
forall lib
(H : @barehypotheses o)
(a b C e : NTerm),
rule_true3 lib (rule_unsquash_equality H a b C e).
Proof.
intros.
unfold rule_unsquash_equality, rule_true3, wf_bseq, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
repnd.
unfold args_constraints in cargs; allsimpl.
generalize (cargs (sarg_term a) (inl eq_refl)); clear cargs; intro arg1.
unfold arg_constraints in arg1.
(* We prove the well-formedness of things *)
destseq; allsimpl.
dLin_hyp; exrepnd.
destruct Hyp as [ws1 hyp1].
destseq; allsimpl; clear_irr; GC.
assert (wf_csequent (rule_unsquash_equality_concl H a b C)) as wfc.
{ clear hyp1.
allrw @wf_equality_iff2; repnd.
unfold wf_csequent, wf_sequent, wf_concl; simpl; dands; auto;
try (apply wf_requality); try (apply wf_refl); auto.
unfold closed_extract; simpl.
unfold covered; simpl; autorewrite with slow; auto. }
exists wfc.
unfold wf_csequent, wf_sequent, wf_concl in wfc; repnd; allsimpl; proof_irr; GC.
vr_seq_true.
vr_seq_true in hyp1.
pose proof (hyp1 s1 s2) as hyp1.
repeat (autodimp hyp1 h).
exrepd.
lsubst_tac.
rw @equality_in_mkc_equality in e0; exrepnd; computes_to_value_isvalue.
clear e0 e2.
apply tequality_mkc_equality_sp_eq in t; auto; repnd.
rw @tequality_mkc_requality.
rw @equality_in_mkc_requality.
dands; auto; try (complete (left; auto)).
eexists; eexists; dands; spcast;
try (complete (apply computes_to_valc_refl; eauto 3 with slow));
auto; try (complete (eapply equality_refl; eauto)).
eapply equality_trans;[|eauto].
apply equality_sym; auto.
Qed.
(**
<<
H [x : A] J |- t1 == t2 in C [ext refl(t1)]
By requalityUnhide
H x : A J |- t1 == t2 in C [ext e]
>>
*)
Definition rule_unhide_requality {o}
(H J : @barehypotheses o)
(A C t1 t2 e : NTerm)
(x : NVar) :=
mk_rule
(mk_baresequent
(snoc H (mk_hhyp x A) ++ J)
(mk_concl_req t1 t2 C))
[ mk_baresequent
(snoc H (mk_hyp x A) ++ J)
(mk_concl (mk_requality t1 t2 C) e) ]
[ sarg_term t1 ].
Lemma rule_unhide_equality_true3 {o} :
forall (lib : library)
(H J : @barehypotheses o)
(A C t1 t2 e : NTerm)
(x : NVar),
rule_true3 lib (rule_unhide_requality H J A C t1 t2 e x).
Proof.
intros.
unfold rule_unhide_requality, rule_true3, wf_bseq, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
repnd.
unfold args_constraints in cargs; allsimpl.
generalize (cargs (sarg_term t1) (inl eq_refl)); clear cargs; intro arg1.
unfold arg_constraints in arg1.
(* We prove the well-formedness of things *)
destseq; allsimpl.
dLin_hyp; exrepnd.
destruct Hyp as [ws1 hyp1].
destseq; allsimpl; clear_irr; GC.
match goal with
| [ |- sequent_true2 _ ?s ] => assert (wf_csequent s) as wfc
end.
{ clear hyp1.
allrw @wf_requality_iff2; repnd.
unfold wf_csequent, wf_sequent, wf_concl; simpl;
allrw @vswf_hypotheses_nil_eq;
allrw @wf_hypotheses_app; allrw @wf_hypotheses_snoc; allsimpl; repnd;
dands; auto; try (apply wf_requality); try (apply wf_refl); auto.
unfold closed_extract; simpl; auto.
unfold covered; simpl; autorewrite with slow; auto. }
exists wfc.
unfold wf_csequent, wf_sequent, wf_concl in wfc; repnd; allsimpl; proof_irr; GC.
vr_seq_true.
vr_seq_true in hyp1.
pose proof (hyp1 s1 s2) as hyp1.
repeat (autodimp hyp1 hyp).
{ intros s3 sim3.
rw @similarity_hhyp in sim3; rw @eq_hyps_hhyp.
apply eqh; sp. }
{ rw @similarity_hhyp; auto. }
exrepnd.
lsubst_tac.
allrw @tequality_mkc_requality.
allrw @equality_in_mkc_requality.
exrepnd; dands; auto.
eexists; eexists; dands; spcast;
try (complete (apply computes_to_valc_refl; eauto 3 with slow));
auto; try (complete (eapply equality_refl; eauto)).
eapply equality_trans;[apply equality_sym;eauto|].
eapply cequorsq_equality_trans2;[|eauto].
eauto 3 with nequality.
Qed.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41A_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O41A_PP_BLACKBOX_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41A_PP_BLACKBOX_V
|
//-----------------------------------------------------------------------------
// The way that we connect things in low-frequency simulation mode. In this
// case just pass everything through to the ARM, which can bit-bang this
// (because it is so slow).
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module lo_adc(
pck0,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
dbg, divisor,
lf_field
);
input pck0;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
output dbg;
input [7:0] divisor;
input lf_field;
reg [7:0] to_arm_shiftreg;
reg [7:0] pck_divider;
reg clk_state;
// Antenna logic, depending on "lf_field" (in arm defined as FPGA_LF_READER_FIELD)
wire tag_modulation = ssp_dout & !lf_field;
wire reader_modulation = !ssp_dout & lf_field & clk_state;
// always on (High Frequency outputs, unused)
assign pwr_oe1 = 1'b0;
assign pwr_hi = 1'b0;
// low frequency outputs
assign pwr_lo = reader_modulation;
assign pwr_oe2 = 1'b0; // 33 Ohms
assign pwr_oe3 = tag_modulation; // base antenna load = 33 Ohms
assign pwr_oe4 = 1'b0; // 10k Ohms
// Debug Output ADC clock
assign dbg = adc_clk;
// ADC clock out of phase with antenna driver
assign adc_clk = ~clk_state;
// serialized SSP data is gated by clk_state to suppress unwanted signal
assign ssp_din = to_arm_shiftreg[7] && !clk_state;
// SSP clock always runs at 24MHz
assign ssp_clk = pck0;
// SSP frame is gated by clk_state and goes high when pck_divider=8..15
assign ssp_frame = (pck_divider[7:3] == 5'd1) && !clk_state;
// divide 24mhz down to 3mhz
always @(posedge pck0)
begin
if (pck_divider == divisor[7:0])
begin
pck_divider <= 8'd0;
clk_state = !clk_state;
end
else
begin
pck_divider <= pck_divider + 1;
end
end
// this task also runs at pck0 frequency (24Mhz) and is used to serialize
// the ADC output which is then clocked into the ARM SSP.
always @(posedge pck0)
begin
if ((pck_divider == 8'd7) && !clk_state)
to_arm_shiftreg <= adc_d;
else begin
to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
// simulation showed a glitch occuring due to the LSB of the shifter
// not being set as we shift bits out
// this ensures the ssp_din remains low after a transfer and suppresses
// the glitch that would occur when the last data shifted out ended in
// a 1 bit and the next data shifted out started with a 0 bit
to_arm_shiftreg[0] <= 1'b0;
end
end
endmodule
|
`include "config.v"
module fx2_timetag(
fx2_clk,
fx2_flags,
fx2_slwr,
fx2_slrd,
fx2_sloe,
fx2_wu2,
fx2_pktend,
fx2_fd,
fx2_fifoadr,
ext_clk,
delta_chs,
strobe_in,
led
);
input fx2_clk;
input [2:0] fx2_flags;
output fx2_slwr;
output fx2_slrd;
output fx2_sloe;
output fx2_wu2;
output fx2_pktend;
inout [7:0] fx2_fd;
output [1:0] fx2_fifoadr;
input ext_clk;
input [3:0] strobe_in;
output [3:0] delta_chs;
output [1:0] led;
wire clk;
wire cmd_rdy;
wire [7:0] cmd;
wire sample_rdy;
wire [7:0] sample;
wire sample_ack;
wire reply_rdy;
wire [7:0] reply;
wire reply_ack;
wire reply_end;
`ifdef USE_EXT_CLK
wire pll_locked;
altpll0 b2v_inst2(
.inclk0(ext_clk),
.c0(clk),
.locked(pll_locked)
);
`else
assign clk = fx2_clk;
`endif
timetag tagger(
.fx2_clk(fx2_clk),
.data_rdy(sample_rdy),
.data(sample),
.data_ack(sample_ack),
.cmd_wr(cmd_rdy),
.cmd_in(cmd),
.reply_rdy(reply_rdy),
.reply(reply),
.reply_ack(reply_ack),
.reply_end(reply_end),
.clk(clk),
.strobe_in(strobe_in),
.delta_chs(delta_chs)
);
fx2_bidir fx2_if(
.fx2_clk(fx2_clk),
.fx2_fd(fx2_fd),
.fx2_flags(fx2_flags),
.fx2_slrd(fx2_slrd),
.fx2_slwr(fx2_slwr),
.fx2_sloe(fx2_sloe),
.fx2_wu2(fx2_wu2),
.fx2_pktend(fx2_pktend),
.fx2_fifoadr(fx2_fifoadr),
.sample(sample),
.sample_rdy(sample_rdy),
.sample_ack(sample_ack),
.cmd(cmd),
.cmd_wr(cmd_rdy),
.reply_rdy(reply_rdy),
.reply(reply),
.reply_ack(reply_ack),
.reply_end(reply_end)
);
led_blinker cmd_rdy_led(
.clk(fx2_clk),
.in(cmd_wr),
.out(led[0])
);
led_blinker sample_rdy_led(
.clk(fx2_clk),
.in(sample_rdy),
.out(led[1])
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DIODE_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DIODE_FUNCTIONAL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__diode (
DIODE
);
// Module ports
input DIODE;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DIODE_FUNCTIONAL_V |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Fri Oct 28 09:17:17 2016
/////////////////////////////////////////////////////////////
module RecursiveKOA_SW54 ( clk, rst, load_b_i, Data_A_i, Data_B_i,
sgf_result_o );
input [53:0] Data_A_i;
input [53:0] Data_B_i;
output [107:0] sgf_result_o;
input clk, rst, load_b_i;
wire EVEN1_left_RECURSIVE_ODD1_Q_left_17_,
EVEN1_right_RECURSIVE_ODD1_Q_left_17_, n84, n85, n86, n87, n88, n89,
n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102,
n103, n104, n105, n106, n107, n108, n109, n110, add_x_2_n303,
add_x_2_n299, add_x_2_n197, add_x_2_n190, add_x_2_n185, add_x_2_n184,
add_x_2_n179, add_x_2_n174, add_x_2_n172, add_x_2_n171, add_x_2_n169,
add_x_2_n166, add_x_2_n164, add_x_2_n158, add_x_2_n157, add_x_2_n144,
add_x_2_n143, add_x_2_n141, add_x_2_n138, add_x_2_n136, add_x_2_n131,
add_x_2_n125, add_x_2_n122, add_x_2_n118, add_x_2_n117, add_x_2_n109,
add_x_2_n99, add_x_2_n93, add_x_2_n88, add_x_2_n81, add_x_2_n70,
add_x_2_n64, add_x_2_n61, add_x_2_n52, add_x_2_n46, add_x_2_n17,
add_x_2_n16, add_x_2_n15, add_x_2_n14, add_x_2_n13, add_x_2_n12,
add_x_2_n11, add_x_2_n10, add_x_2_n9, add_x_2_n8, add_x_2_n6,
add_x_1_n799, add_x_1_n744, add_x_1_n739, add_x_1_n737, add_x_1_n732,
add_x_1_n725, add_x_1_n330, add_x_1_n322, add_x_1_n318, add_x_1_n310,
add_x_1_n70, add_x_1_n69, add_x_3_n307, add_x_3_n306, add_x_3_n303,
add_x_3_n197, add_x_3_n190, add_x_3_n185, add_x_3_n181, add_x_3_n178,
add_x_3_n174, add_x_3_n172, add_x_3_n171, add_x_3_n169, add_x_3_n166,
add_x_3_n164, add_x_3_n158, add_x_3_n157, add_x_3_n153, add_x_3_n146,
add_x_3_n144, add_x_3_n143, add_x_3_n141, add_x_3_n138, add_x_3_n136,
add_x_3_n132, add_x_3_n131, add_x_3_n125, add_x_3_n122, add_x_3_n109,
add_x_3_n106, add_x_3_n99, add_x_3_n97, add_x_3_n93, add_x_3_n88,
add_x_3_n81, add_x_3_n79, add_x_3_n70, add_x_3_n68, add_x_3_n64,
add_x_3_n61, add_x_3_n52, add_x_3_n50, add_x_3_n46, add_x_3_n41,
add_x_3_n17, add_x_3_n16, add_x_3_n15, add_x_3_n13, add_x_3_n12,
add_x_3_n11, add_x_3_n10, add_x_3_n9, add_x_3_n8, add_x_3_n7,
add_x_3_n6, add_x_3_n5, add_x_3_n4, DP_OP_62J6_125_4796_n697,
DP_OP_62J6_125_4796_n696, DP_OP_62J6_125_4796_n642,
DP_OP_62J6_125_4796_n641, DP_OP_62J6_125_4796_n640,
DP_OP_62J6_125_4796_n564, DP_OP_62J6_125_4796_n562,
DP_OP_62J6_125_4796_n561, DP_OP_62J6_125_4796_n560,
DP_OP_62J6_125_4796_n559, DP_OP_62J6_125_4796_n558,
DP_OP_62J6_125_4796_n555, DP_OP_62J6_125_4796_n551,
DP_OP_62J6_125_4796_n550, DP_OP_62J6_125_4796_n547,
DP_OP_62J6_125_4796_n546, DP_OP_62J6_125_4796_n543,
DP_OP_62J6_125_4796_n542, DP_OP_62J6_125_4796_n539,
DP_OP_62J6_125_4796_n538, DP_OP_62J6_125_4796_n409,
DP_OP_62J6_125_4796_n298, DP_OP_62J6_125_4796_n297,
DP_OP_62J6_125_4796_n294, DP_OP_62J6_125_4796_n287,
DP_OP_62J6_125_4796_n286, DP_OP_62J6_125_4796_n283,
DP_OP_62J6_125_4796_n282, DP_OP_62J6_125_4796_n280,
DP_OP_62J6_125_4796_n40, DP_OP_62J6_125_4796_n39,
DP_OP_59J6_122_190_n309, DP_OP_59J6_122_190_n308,
DP_OP_59J6_122_190_n306, DP_OP_59J6_122_190_n305,
DP_OP_59J6_122_190_n303, DP_OP_59J6_122_190_n232,
DP_OP_59J6_122_190_n224, DP_OP_59J6_122_190_n223,
DP_OP_59J6_122_190_n222, DP_OP_59J6_122_190_n212,
DP_OP_59J6_122_190_n210, DP_OP_59J6_122_190_n209,
DP_OP_59J6_122_190_n204, DP_OP_59J6_122_190_n201,
DP_OP_59J6_122_190_n200, DP_OP_59J6_122_190_n192,
DP_OP_59J6_122_190_n187, DP_OP_59J6_122_190_n183,
DP_OP_59J6_122_190_n182, DP_OP_59J6_122_190_n180,
DP_OP_59J6_122_190_n176, DP_OP_59J6_122_190_n170,
DP_OP_59J6_122_190_n167, DP_OP_59J6_122_190_n166,
DP_OP_59J6_122_190_n160, DP_OP_59J6_122_190_n158,
DP_OP_59J6_122_190_n153, DP_OP_59J6_122_190_n147,
DP_OP_59J6_122_190_n146, DP_OP_59J6_122_190_n136,
DP_OP_59J6_122_190_n135, DP_OP_59J6_122_190_n123,
DP_OP_59J6_122_190_n122, DP_OP_59J6_122_190_n112,
DP_OP_59J6_122_190_n111, DP_OP_59J6_122_190_n110,
DP_OP_59J6_122_190_n109, DP_OP_59J6_122_190_n103,
DP_OP_59J6_122_190_n65, DP_OP_59J6_122_190_n64,
DP_OP_59J6_122_190_n63, DP_OP_59J6_122_190_n62,
DP_OP_59J6_122_190_n60, DP_OP_59J6_122_190_n58,
DP_OP_59J6_122_190_n57, DP_OP_59J6_122_190_n55,
DP_OP_59J6_122_190_n54, DP_OP_59J6_122_190_n53,
DP_OP_59J6_122_190_n52, DP_OP_59J6_122_190_n51,
DP_OP_59J6_122_190_n50, DP_OP_59J6_122_190_n49, n112, n113, n114,
n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125,
n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137,
n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148,
n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159,
n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170,
n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181,
n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192,
n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203,
n204, n205, n206, n207, n208, n209, n210, n211, n212, n213, n214,
n215, n216, n217, n218, n219, n220, n221, n222, n223, n224, n225,
n226, n227, n228, n229, n230, n231, n232, n233, n234, n235, n236,
n237, n238, n239, n240, n241, n242, n243, n244, n245, n246, n247,
n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, n258,
n259, n260, n261, n262, n263, n264, n265, n266, n267, n268, n269,
n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, n280,
n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291,
n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302,
n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313,
n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324,
n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, n335,
n336, n337, n338, n339, n340, n341, n342, n343, n344, n345, n346,
n347, n348, n349, n350, n351, n352, n353, n354, n355, n356, n357,
n358, n359, n360, n361, n362, n363, n364, n365, n366, n367, n368,
n369, n370, n371, n372, n373, n374, n375, n376, n377, n378, n379,
n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, n390,
n391, n392, n393, n394, n395, n396, n397, n398, n399, n400, n401,
n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, n412,
n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423,
n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, n434,
n435, n436, n437, n438, n439, n440, n441, n442, n443, n444, n445,
n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456,
n457, n458, n459, n460, n461, n462, n463, n464, n465, n466, n467,
n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478,
n479, n480, n481, n482, n483, n484, n485, n486, n487, n488, n489,
n490, n491, n492, n493, n494, n495, n496, n497, n498, n499, n500,
n501, n502, n503, n504, n505, n506, n507, n508, n509, n510, n511,
n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, n522,
n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533,
n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544,
n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566,
n567, n568, n569, n570, n571, n572, n573, n574, n575, n576, n577,
n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, n588,
n589, n590, n591, n592, n593, n594, n595, n596, n597, n598, n599,
n600, n601, n602, n603, n604, n605, n606, n607, n608, n609, n610,
n611, n612, n613, n614, n615, n616, n617, n618, n619, n620, n621,
n622, n623, n624, n625, n626, n627, n628, n629, n630, n631, n632,
n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, n643,
n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654,
n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676,
n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698,
n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720,
n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731,
n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742,
n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753,
n754, n755, n756, n757, n758, n759, n760, n761, n762, n763, n764,
n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, n775,
n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786,
n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, n797,
n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808,
n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819,
n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, n830,
n831, n832, n833, n834, n835, n836, n837, n838, n839, n840, n841,
n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, n852,
n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863,
n864, n865, n866, n867, n868, n869, n870, n871, n872, n873, n874,
n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, n885,
n886, n887, n888, n889, n890, n891, n892, n893, n894, n895, n896,
n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918,
n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951,
n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962,
n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973,
n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984,
n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995,
n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005,
n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015,
n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025,
n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035,
n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045,
n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055,
n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065,
n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075,
n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085,
n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095,
n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105,
n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115,
n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125,
n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135,
n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145,
n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295,
n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305,
n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315,
n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325,
n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335,
n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345,
n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355,
n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365,
n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375,
n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385,
n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395,
n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405,
n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415,
n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425,
n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435,
n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445,
n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455,
n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465,
n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475,
n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635,
n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645,
n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655,
n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665,
n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675,
n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685,
n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695,
n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705,
n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715,
n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725,
n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735,
n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745,
n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755,
n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765,
n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775,
n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785,
n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795,
n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805,
n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815,
n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825,
n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835,
n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845,
n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855,
n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865,
n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875,
n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885,
n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895,
n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905,
n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915,
n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925,
n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935,
n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945,
n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955,
n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965,
n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975,
n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985,
n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995,
n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005,
n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015,
n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025,
n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035,
n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045,
n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055,
n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065,
n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075,
n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085,
n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095,
n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105,
n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115,
n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125,
n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135,
n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145,
n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155,
n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165,
n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175,
n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185,
n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195,
n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205,
n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215,
n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225,
n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235,
n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245,
n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255,
n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265,
n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275,
n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285,
n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295,
n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305,
n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315,
n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325,
n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335,
n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345,
n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355,
n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365,
n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375,
n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385,
n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395,
n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405,
n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415,
n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425,
n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435,
n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445,
n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455,
n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465,
n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475,
n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485,
n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495,
n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505,
n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515,
n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525,
n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535,
n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545,
n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555,
n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565,
n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575,
n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585,
n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595,
n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605,
n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615,
n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625,
n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635,
n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645,
n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655,
n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665,
n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675,
n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685,
n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695,
n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705,
n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715,
n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725,
n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735,
n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745,
n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755,
n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765,
n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775,
n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785,
n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795,
n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805,
n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815,
n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825,
n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835,
n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845,
n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855,
n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865,
n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875,
n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885,
n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895,
n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905,
n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915,
n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925,
n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935,
n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945,
n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955,
n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965,
n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975,
n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985,
n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995,
n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005,
n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015,
n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025,
n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035,
n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045,
n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055,
n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065,
n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075,
n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084, n3085,
n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095,
n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105,
n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115,
n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125,
n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134, n3135,
n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145,
n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155,
n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164, n3165,
n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174, n3175,
n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184, n3185,
n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195,
n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205,
n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214, n3215,
n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224, n3225,
n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234, n3235,
n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244, n3245,
n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254, n3255,
n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264, n3265,
n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274, n3275,
n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284, n3285,
n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294, n3295,
n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304, n3305,
n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314, n3315,
n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324, n3325,
n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334, n3335,
n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344, n3345,
n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354, n3355,
n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364, n3365,
n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374, n3375,
n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384, n3385,
n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394, n3395,
n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404, n3405,
n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414, n3415,
n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424, n3425,
n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434, n3435,
n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444, n3445,
n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454, n3455,
n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464, n3465,
n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474, n3475,
n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484, n3485,
n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494, n3495,
n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504, n3505,
n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514, n3515,
n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524, n3525,
n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534, n3535,
n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544, n3545,
n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554, n3555,
n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564, n3565,
n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574, n3575,
n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584, n3585,
n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594, n3595,
n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604, n3605,
n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614, n3615,
n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624, n3625,
n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634, n3635,
n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644, n3645,
n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654, n3655,
n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664, n3665,
n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674, n3675,
n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684, n3685,
n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694, n3695,
n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704, n3705,
n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714, n3715,
n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725,
n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735,
n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745,
n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755,
n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764, n3765,
n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774, n3775,
n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784, n3785,
n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794, n3795,
n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804, n3805,
n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814, n3815,
n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824, n3825,
n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834, n3835,
n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844, n3845,
n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854, n3855,
n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864, n3865,
n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874, n3875,
n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884, n3885,
n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894, n3895,
n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904, n3905,
n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914, n3915,
n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924, n3925,
n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935,
n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945,
n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955,
n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965,
n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975,
n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985,
n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994, n3995,
n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005,
n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015,
n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025,
n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035,
n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045,
n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055,
n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065,
n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075,
n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085,
n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095,
n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104, n4105,
n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115,
n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124, n4125,
n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135,
n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145,
n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155,
n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165,
n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175,
n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185,
n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195,
n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205,
n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215,
n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225,
n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235,
n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245,
n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255,
n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265,
n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275,
n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285,
n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295,
n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305,
n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315,
n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325,
n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335,
n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345,
n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355,
n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365,
n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375,
n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4385,
n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394, n4395,
n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405,
n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415,
n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425,
n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435,
n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445,
n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455,
n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465,
n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474, n4475,
n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485,
n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495,
n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505,
n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515,
n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525,
n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535,
n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545,
n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555,
n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565,
n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575,
n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585,
n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595,
n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605,
n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615,
n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625,
n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635,
n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645,
n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655,
n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665,
n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675,
n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685,
n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695,
n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705,
n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715,
n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725,
n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735,
n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745,
n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755,
n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765,
n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775,
n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785,
n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795,
n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805,
n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815,
n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825,
n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835,
n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845,
n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855,
n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865,
n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875,
n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885,
n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895,
n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905,
n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914, n4915,
n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925,
n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935,
n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945,
n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4955,
n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965,
n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975,
n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985,
n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994, n4995,
n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004, n5005,
n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014, n5015,
n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025,
n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034, n5035,
n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044, n5045,
n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054, n5055,
n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065,
n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075,
n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085,
n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094, n5095,
n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104, n5105,
n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114, n5115,
n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124, n5125,
n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134, n5135,
n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144, n5145,
n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154, n5155,
n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163, n5164, n5165,
n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173, n5174, n5175,
n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183, n5184, n5185,
n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193, n5194, n5195,
n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203, n5204, n5205,
n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213, n5214, n5215,
n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223, n5224, n5225,
n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233, n5234, n5235,
n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243, n5244, n5245,
n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253, n5254, n5255,
n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263, n5264, n5265,
n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273, n5274, n5275,
n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283, n5284, n5285,
n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293, n5294, n5295,
n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303, n5304, n5305,
n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313, n5314, n5315,
n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323, n5324, n5325,
n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333, n5334, n5335,
n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343, n5344, n5345,
n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353, n5354, n5355,
n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363, n5364, n5365,
n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373, n5374, n5375,
n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383, n5384, n5385,
n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393, n5394, n5395,
n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403, n5404, n5405,
n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413, n5414, n5415,
n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423, n5424, n5425,
n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433, n5434, n5435,
n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443, n5444, n5445,
n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453, n5454, n5455,
n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463, n5464, n5465,
n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473, n5474, n5475,
n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483, n5484, n5485,
n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493, n5494, n5495,
n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503, n5504, n5505,
n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513, n5514, n5515,
n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523, n5524, n5525,
n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533, n5534, n5535,
n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543, n5544, n5545,
n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553, n5554, n5555,
n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563, n5564, n5565,
n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573, n5574, n5575,
n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583, n5584, n5585,
n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593, n5594, n5595,
n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603, n5604, n5605,
n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613, n5614, n5615,
n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623, n5624, n5625,
n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633, n5634, n5635,
n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643, n5644, n5645,
n5646, n5647, n5648, n5649, n5650, n5651, n5652, n5653, n5654, n5655,
n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664, n5665,
n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674, n5675,
n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684, n5685,
n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694, n5695,
n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704, n5705,
n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713, n5714, n5715,
n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724, n5725,
n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733, n5734, n5735,
n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743, n5744, n5745,
n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5754, n5755,
n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764, n5765,
n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774, n5775,
n5776, n5777, n5778, n5779, n5780, n5781, n5782, n5783, n5784, n5785,
n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794, n5795,
n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804, n5805,
n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814, n5815,
n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824, n5825,
n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834, n5835,
n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844, n5845,
n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854, n5855,
n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863, n5864, n5865,
n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873, n5874, n5875,
n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884, n5885,
n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894, n5895,
n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904, n5905,
n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914, n5915,
n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925,
n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934, n5935,
n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944, n5945,
n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954, n5955,
n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964, n5965,
n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973, n5974, n5975,
n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984, n5985,
n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993, n5994, n5995,
n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003, n6004, n6005,
n6006, n6007, n6008, n6009, n6010, n6011, n6012, n6013, n6014, n6015,
n6016, n6017, n6018, n6019, n6020, n6021, n6022, n6023, n6024, n6025,
n6026, n6027, n6028, n6029, n6030, n6031, n6032, n6033, n6034, n6035,
n6036, n6037, n6038, n6039, n6040, n6041, n6042, n6043, n6044, n6045,
n6046, n6047, n6048, n6049, n6050, n6051, n6052, n6053, n6054, n6055,
n6056, n6057, n6058, n6059, n6060, n6061, n6062, n6063, n6064, n6065,
n6066, n6067, n6068, n6069, n6070, n6071, n6072, n6073, n6074, n6075,
n6076, n6077, n6078, n6079, n6080, n6081, n6082, n6083, n6084, n6085,
n6086, n6087, n6088, n6089, n6090, n6091, n6092, n6093, n6094, n6095,
n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104, n6105,
n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114, n6115,
n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124, n6125,
n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134, n6135,
n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6144, n6145,
n6146, n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154, n6155,
n6156, n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164, n6165,
n6166, n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174, n6175,
n6176, n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184, n6185,
n6186, n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194, n6195,
n6196, n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205,
n6206, n6207, n6208, n6209, n6210, n6211, n6212, n6213, n6214, n6215,
n6216, n6217, n6218, n6219, n6220, n6221, n6222, n6223, n6224, n6225,
n6226, n6227, n6228, n6229, n6230, n6231, n6232, n6233, n6234, n6235,
n6236, n6237, n6238, n6239, n6240, n6241, n6242, n6243, n6244, n6245,
n6246, n6247, n6248, n6249, n6250, n6251, n6252, n6253, n6254, n6255,
n6256, n6257, n6258, n6259, n6260, n6261, n6262, n6263, n6264, n6265,
n6266, n6267, n6268, n6269, n6270, n6271, n6272, n6273, n6274, n6275,
n6276, n6277, n6278, n6279, n6280, n6281, n6282, n6283, n6284, n6285,
n6286, n6287, n6288, n6289, n6290, n6291, n6292, n6293, n6294, n6295,
n6296, n6297, n6298, n6299, n6300, n6301, n6302, n6303, n6304, n6305,
n6306, n6307, n6308, n6309, n6310, n6311, n6312, n6313, n6314, n6315,
n6316, n6317, n6318, n6319, n6320, n6321, n6322, n6323, n6324, n6325,
n6326, n6327, n6328, n6329, n6330, n6331, n6332, n6333, n6334, n6335,
n6336, n6337, n6338, n6339, n6340, n6341, n6342, n6343, n6344, n6345,
n6346, n6347, n6348, n6349, n6350, n6351, n6352, n6353, n6354, n6355,
n6356, n6357, n6358, n6359, n6360, n6361, n6362, n6363, n6364, n6365,
n6366, n6367, n6368, n6369, n6370, n6371, n6372, n6373, n6374, n6375,
n6376, n6377, n6378, n6379, n6380, n6381, n6382, n6383, n6384, n6385,
n6386, n6387, n6388, n6389, n6390, n6391, n6392, n6393, n6394, n6395,
n6396, n6397, n6398, n6399, n6400, n6401, n6402, n6403, n6404, n6405,
n6406, n6407, n6408, n6409, n6410, n6411, n6412, n6413, n6414, n6415,
n6416, n6417, n6418, n6419, n6420, n6421, n6422, n6423, n6424, n6425,
n6426, n6427, n6428, n6429, n6430, n6431, n6432, n6433, n6434, n6435,
n6436, n6437, n6438, n6439, n6440, n6441, n6442, n6443, n6444, n6445,
n6446, n6447, n6448, n6449, n6450, n6451, n6452, n6453, n6454, n6455,
n6456, n6457, n6458, n6459, n6460, n6461, n6462, n6463, n6464, n6465,
n6466, n6467, n6468, n6469, n6470, n6471, n6472, n6473, n6474, n6475,
n6476, n6477, n6478, n6479, n6480, n6481, n6482, n6483, n6484, n6485,
n6486, n6487, n6488, n6489, n6490, n6491, n6492, n6493, n6494, n6495,
n6496, n6497, n6498, n6499, n6500, n6501, n6502, n6503, n6504, n6505,
n6506, n6507, n6508, n6509, n6510, n6511, n6512, n6513, n6514, n6515,
n6516, n6517, n6518, n6519, n6520, n6521, n6522, n6523, n6524, n6525,
n6526, n6527, n6528, n6529, n6530, n6531, n6532, n6533, n6534, n6535,
n6536, n6537, n6538, n6539, n6540, n6541, n6542, n6543, n6544, n6545,
n6546, n6547, n6548, n6549, n6550, n6551, n6552, n6553, n6554, n6555,
n6556, n6557, n6558, n6559, n6560, n6561, n6562, n6563, n6564, n6565,
n6566, n6567, n6568, n6569, n6570, n6571, n6572, n6573, n6574, n6575,
n6576, n6577, n6578, n6579, n6580, n6581, n6582, n6583, n6584, n6585,
n6586, n6587, n6588, n6589, n6590, n6591, n6592, n6593, n6594, n6595,
n6596, n6597, n6598, n6599, n6600, n6601, n6602, n6603, n6604, n6605,
n6606, n6607, n6608, n6609, n6610, n6611, n6612, n6613, n6614, n6615,
n6616, n6617, n6618, n6619, n6620, n6621, n6622, n6623, n6624, n6625,
n6626, n6627, n6628, n6629, n6630, n6631, n6632, n6633, n6634, n6635,
n6636, n6637, n6638, n6639, n6640, n6641, n6642, n6643, n6644, n6645,
n6646, n6647, n6648, n6649, n6650, n6651, n6652, n6653, n6654, n6655,
n6656, n6657, n6658, n6659, n6660, n6661, n6662, n6663, n6664, n6665,
n6666, n6667, n6668, n6669, n6670, n6671, n6672, n6673, n6674, n6675,
n6676, n6677, n6678, n6679, n6680, n6681, n6682, n6683, n6684, n6685,
n6686, n6687, n6688, n6689, n6690, n6691, n6692, n6693, n6694, n6695,
n6696, n6697, n6698, n6699, n6700, n6701, n6702, n6703, n6704, n6705,
n6706, n6707, n6708, n6709, n6710, n6711, n6712, n6713, n6714, n6715,
n6716, n6717, n6718, n6719, n6720, n6721, n6722, n6723, n6724, n6725,
n6726, n6727, n6728, n6729, n6730, n6731, n6732, n6733, n6734, n6735,
n6736, n6737, n6738, n6739, n6740, n6741, n6742, n6743, n6744, n6745,
n6746, n6747, n6748, n6749, n6750, n6751, n6752, n6753, n6754, n6755,
n6756, n6757, n6758, n6759, n6760, n6761, n6762, n6763, n6764, n6765,
n6766, n6767, n6768, n6769, n6770, n6771, n6772, n6773, n6774, n6775,
n6776, n6777, n6778, n6779, n6780, n6781, n6782, n6783, n6784, n6785,
n6786, n6787, n6788, n6789, n6790, n6791, n6792, n6793, n6794, n6795,
n6796, n6797, n6798, n6799, n6800, n6801, n6802, n6803, n6804, n6805,
n6806, n6807, n6808, n6809, n6810, n6811, n6812, n6813, n6814, n6815,
n6816, n6817, n6818, n6819, n6820, n6821, n6822, n6823, n6824, n6825,
n6826, n6827, n6828, n6829, n6830, n6831, n6832, n6833, n6834, n6835,
n6836, n6837, n6838, n6839, n6840, n6841, n6842, n6843, n6844, n6845,
n6846, n6847, n6848, n6849, n6850, n6851, n6852, n6853, n6854, n6855,
n6856, n6857, n6858, n6859, n6860, n6861, n6862, n6863, n6864, n6865,
n6866, n6867, n6868, n6869, n6870, n6871, n6872, n6873, n6874, n6875,
n6876, n6877, n6878, n6879, n6880, n6881, n6882, n6883, n6884, n6885,
n6886, n6887, n6888, n6889, n6890, n6891, n6892, n6893, n6894, n6895,
n6896, n6897, n6898, n6899, n6900, n6901, n6902, n6903, n6904, n6905,
n6906, n6907, n6908, n6909, n6910, n6911, n6912, n6913, n6914, n6915,
n6916, n6917, n6918, n6919, n6920, n6921, n6922, n6923, n6924, n6925,
n6926, n6927, n6928, n6929, n6930, n6931, n6932, n6933, n6934, n6935,
n6936, n6937, n6938, n6939, n6940, n6941, n6942, n6943, n6944, n6945,
n6946, n6947, n6948, n6949, n6950, n6951, n6952, n6953, n6954, n6955,
n6956, n6957, n6958, n6959, n6960, n6961, n6962, n6963, n6964, n6965,
n6966, n6967, n6968, n6969, n6970, n6971, n6972, n6973, n6974, n6975,
n6976, n6977, n6978, n6979, n6980, n6981, n6982, n6983, n6984, n6985,
n6986, n6987, n6988, n6989, n6990, n6991, n6992, n6993, n6994, n6995,
n6996, n6997, n6998, n6999, n7000, n7001, n7002, n7003, n7004, n7005,
n7006, n7007, n7008, n7009, n7010, n7011, n7012, n7013, n7014, n7015,
n7016, n7017, n7018, n7019, n7020, n7021, n7022, n7023, n7024, n7025,
n7026, n7027, n7028, n7029, n7030, n7031, n7032, n7033, n7034, n7035,
n7036, n7037, n7038, n7039, n7040, n7041, n7042, n7043, n7044, n7045,
n7046, n7047, n7048, n7049, n7050, n7051, n7052, n7053, n7054, n7055,
n7056, n7057, n7058, n7059, n7060, n7061, n7062, n7063, n7064, n7065,
n7066, n7067, n7068, n7069, n7070, n7071, n7072, n7073, n7074, n7075,
n7076, n7077, n7078, n7079, n7080, n7081, n7082, n7083, n7084, n7085,
n7086, n7087, n7088, n7089, n7090, n7091, n7092, n7093, n7094, n7095,
n7096, n7097, n7098, n7099, n7100, n7101, n7102, n7103, n7104, n7105,
n7106, n7107, n7108, n7109, n7110, n7111, n7112, n7113, n7114, n7115,
n7116, n7117, n7118, n7119, n7120, n7121, n7122, n7123, n7124, n7125,
n7126, n7127, n7128, n7129, n7130, n7131, n7132, n7133, n7134, n7135,
n7136, n7137, n7138, n7139, n7140, n7141, n7142, n7143, n7144, n7145,
n7146, n7147, n7148, n7149, n7150, n7151, n7152, n7153, n7154, n7155,
n7156, n7157, n7158, n7159, n7160, n7161, n7162, n7163, n7164, n7165,
n7166, n7167, n7168, n7169, n7170, n7171, n7172, n7173, n7174, n7175,
n7176, n7177, n7178, n7179, n7180, n7181, n7182, n7183, n7184, n7185,
n7186, n7187, n7188, n7189, n7190, n7191, n7192, n7193, n7194, n7195,
n7196, n7197, n7198, n7199, n7200, n7201, n7202, n7203, n7204, n7205,
n7206, n7207, n7208, n7209, n7210, n7211, n7212, n7213, n7214, n7215,
n7216, n7217, n7218, n7219, n7220, n7221, n7222, n7223, n7224, n7225,
n7226, n7227, n7228, n7229, n7230, n7231, n7232, n7233, n7234, n7235,
n7236, n7237, n7238, n7239, n7240, n7241, n7242, n7243, n7244, n7245,
n7246, n7247, n7248, n7249, n7250, n7251, n7252, n7253, n7254, n7255,
n7256, n7257, n7258, n7259, n7260, n7261, n7262, n7263, n7264, n7265,
n7266, n7267, n7268, n7269, n7270, n7271, n7272, n7273, n7274, n7275,
n7276, n7277, n7278, n7279, n7280, n7281, n7282, n7283, n7284, n7285,
n7286, n7287, n7288, n7289, n7290, n7291, n7292, n7293, n7294, n7295,
n7296, n7297, n7298, n7299, n7300, n7301, n7302, n7303, n7304, n7305,
n7306, n7307, n7308, n7309, n7310, n7311, n7312, n7313, n7314, n7315,
n7316, n7317, n7318, n7319, n7320, n7321, n7322, n7323, n7324, n7325,
n7326, n7327, n7328, n7329, n7330, n7331, n7332, n7333, n7334, n7335,
n7336, n7337, n7338, n7339, n7340, n7341, n7342, n7343, n7344, n7345,
n7346, n7347, n7348, n7349, n7350, n7351, n7352, n7353, n7354, n7355,
n7356, n7357, n7358, n7359, n7360, n7361, n7362, n7363, n7364, n7365,
n7366, n7367, n7368, n7369, n7370, n7371, n7372, n7373, n7374, n7375,
n7376, n7377, n7378, n7379, n7380, n7381, n7382, n7383, n7384, n7385,
n7386, n7387, n7388, n7389, n7390, n7391, n7392, n7393, n7394, n7395,
n7396, n7397, n7398, n7399, n7400, n7401, n7402, n7403, n7404, n7405,
n7406, n7407, n7408, n7409, n7410, n7411, n7412, n7413, n7414, n7415,
n7416, n7417, n7418, n7419, n7420, n7421, n7422, n7423, n7424, n7425,
n7426, n7427, n7428, n7429, n7430, n7431, n7432, n7433, n7434, n7435,
n7436, n7437, n7438, n7439, n7440, n7441, n7442, n7443, n7444, n7445,
n7446, n7447, n7448, n7449, n7450, n7451, n7452, n7453, n7454, n7455,
n7456, n7457, n7458, n7459, n7460, n7461, n7462, n7463, n7464, n7465,
n7466, n7467, n7468, n7469, n7470, n7471, n7472, n7473, n7474, n7475,
n7476, n7477, n7478, n7479, n7480, n7481, n7482, n7483, n7484, n7485,
n7486, n7487, n7488, n7489, n7490, n7491, n7492, n7493, n7494, n7495,
n7496, n7497, n7498, n7499, n7500, n7501, n7502, n7503, n7504, n7505,
n7506, n7507, n7508, n7509, n7510, n7511, n7512, n7513, n7514, n7515,
n7516, n7517, n7518, n7519, n7520, n7521, n7522, n7523, n7524, n7525,
n7526, n7527, n7528, n7529, n7530, n7531, n7532, n7533, n7534, n7535,
n7536, n7537, n7538, n7539, n7540, n7541, n7542, n7543, n7544, n7545,
n7546, n7547, n7548, n7549, n7550, n7551, n7552, n7553, n7554, n7555,
n7556, n7557, n7558, n7559, n7560, n7561, n7562, n7563, n7564, n7565,
n7566, n7567, n7568, n7569, n7570, n7571, n7572, n7573, n7574, n7575,
n7576, n7577, n7578, n7579, n7580, n7581, n7582, n7583, n7584, n7585,
n7586, n7587, n7588, n7589, n7590, n7591, n7592, n7593, n7594, n7595,
n7596, n7597, n7598, n7599, n7600, n7601, n7602, n7603, n7604, n7605,
n7606, n7607, n7608, n7609, n7610, n7611, n7612, n7613, n7614, n7615,
n7616, n7617, n7618, n7619, n7620, n7621, n7622, n7623, n7624, n7625,
n7626, n7627, n7628, n7629, n7630, n7631, n7632, n7633, n7634, n7635,
n7636, n7637, n7638, n7639, n7640, n7641, n7642, n7643, n7644, n7645,
n7646, n7647, n7648, n7649, n7650, n7651, n7652, n7653, n7654, n7655,
n7656, n7657, n7658, n7659, n7660, n7661, n7662, n7663, n7664, n7665,
n7666, n7667, n7668, n7669, n7670, n7671, n7672, n7673, n7674, n7675,
n7676, n7677, n7678, n7679, n7680, n7681, n7682, n7683, n7684, n7685,
n7686, n7687, n7688, n7689, n7690, n7691, n7692, n7693, n7694, n7695,
n7696, n7697, n7698, n7699, n7700, n7701, n7702, n7703, n7704, n7705,
n7706, n7707, n7708, n7709, n7710, n7711, n7712, n7713, n7714, n7715,
n7716, n7717, n7718, n7719, n7720, n7721, n7722, n7723, n7724, n7725,
n7726, n7727, n7728, n7729, n7730, n7731, n7732, n7733, n7734, n7735,
n7736, n7737, n7738, n7739, n7740, n7741, n7742, n7743, n7744, n7745,
n7746, n7747, n7748, n7749, n7750, n7751, n7752, n7753, n7754, n7755,
n7756, n7757, n7758, n7759, n7760, n7761, n7762, n7763, n7764, n7765,
n7766, n7767, n7768, n7769, n7770, n7771, n7772, n7773, n7774, n7775,
n7776, n7777, n7778, n7779, n7780, n7781, n7782, n7783, n7784, n7785,
n7786, n7787, n7788, n7789, n7790, n7791, n7792, n7793, n7794, n7795,
n7796, n7797, n7798, n7799, n7800, n7801, n7802, n7803, n7804, n7805,
n7806, n7807, n7808, n7809, n7810, n7811, n7812, n7813, n7814, n7815,
n7816, n7817, n7818, n7819, n7820, n7821, n7822, n7823, n7824, n7825,
n7826, n7827, n7828, n7829, n7830, n7831, n7832, n7833, n7834, n7835,
n7836, n7837, n7838, n7839, n7840, n7841, n7842, n7843, n7844, n7845,
n7846, n7847, n7848, n7849, n7850, n7851, n7852, n7853, n7854, n7855,
n7856, n7857, n7858, n7859, n7860, n7861, n7862, n7863, n7864, n7865,
n7866, n7867, n7868, n7869, n7870, n7871, n7872, n7873, n7874, n7875,
n7876, n7877, n7878, n7879, n7880, n7881, n7882, n7883, n7884, n7885,
n7886, n7887, n7888, n7889, n7890, n7891, n7892, n7893, n7894, n7895,
n7896, n7897, n7898, n7899, n7900, n7901, n7902, n7903, n7904, n7905,
n7906, n7907, n7908, n7909, n7910, n7911, n7912, n7913, n7914, n7915,
n7916, n7917, n7918, n7919, n7920, n7921, n7922, n7923, n7924, n7925,
n7926, n7927, n7928, n7929, n7930, n7931, n7932, n7933, n7934, n7935,
n7936, n7937, n7938, n7939, n7940, n7941, n7942, n7943, n7944, n7945,
n7946, n7947, n7948, n7949, n7950, n7951, n7952, n7953, n7954, n7955,
n7956, n7957, n7958, n7959, n7960, n7961, n7962, n7963, n7964, n7965,
n7966, n7967, n7968, n7969, n7970, n7971, n7972, n7973, n7974, n7975,
n7976, n7977, n7978, n7979, n7980, n7981, n7982, n7983, n7984, n7985,
n7986, n7987, n7988, n7989, n7990, n7991, n7992, n7993, n7994, n7995,
n7996, n7997, n7998, n7999, n8000, n8001, n8002, n8003, n8004, n8005,
n8006, n8007, n8008, n8009, n8010, n8011, n8012, n8013, n8014, n8015,
n8016, n8017, n8018, n8019, n8020, n8021, n8022, n8023, n8024, n8025,
n8026, n8027, n8028, n8029, n8030, n8031, n8032, n8033, n8034, n8035,
n8036, n8037, n8038, n8039, n8040, n8041, n8042, n8043, n8044, n8045,
n8046, n8047, n8048, n8049, n8050, n8051, n8052, n8053, n8054, n8055,
n8056, n8057, n8058, n8059, n8060, n8061, n8062, n8063, n8064, n8065,
n8066, n8067, n8068, n8069, n8070, n8071, n8072, n8073, n8074, n8075,
n8076, n8077, n8078, n8079, n8080, n8081, n8082, n8083, n8084, n8085,
n8086, n8087, n8088, n8089, n8090, n8091, n8092, n8093, n8094, n8095,
n8096, n8097, n8098, n8099, n8100, n8101, n8102, n8103, n8104, n8105,
n8106, n8107, n8108, n8109, n8110, n8111, n8112, n8113, n8114, n8115,
n8116, n8117, n8118, n8119, n8120, n8121, n8122, n8123, n8124, n8125,
n8126, n8127, n8128, n8129, n8130, n8131, n8132, n8133, n8134, n8135,
n8136, n8137, n8138, n8139, n8140, n8141, n8142, n8143, n8144, n8145,
n8146, n8147, n8148, n8149, n8150, n8151, n8152, n8153, n8154, n8155,
n8156, n8157, n8158, n8159, n8160, n8161, n8162, n8163, n8164, n8165,
n8166, n8167, n8168, n8169, n8170, n8171, n8172, n8173, n8174, n8175,
n8176, n8177, n8178, n8179, n8180, n8181, n8182, n8183, n8184, n8185,
n8186, n8187, n8188, n8189, n8190, n8191, n8192, n8193, n8194, n8195,
n8196, n8197, n8198, n8199, n8200, n8201, n8202, n8203, n8204, n8205,
n8206, n8207, n8208, n8209, n8210, n8211, n8212, n8213, n8214, n8215,
n8216, n8217, n8218, n8219, n8220, n8221, n8222, n8223, n8224, n8225,
n8226, n8227, n8228, n8229, n8230, n8231, n8232, n8233, n8234, n8235,
n8236, n8237, n8238, n8239, n8240, n8241, n8242, n8243, n8244, n8245,
n8246, n8247, n8248, n8249, n8250, n8251, n8252, n8253, n8254, n8255,
n8256, n8257, n8258, n8259, n8260, n8261, n8262, n8263, n8264, n8265,
n8266, n8267, n8268, n8269, n8270, n8271, n8272, n8273, n8274, n8275,
n8276, n8277, n8278, n8279, n8280, n8281, n8282, n8283, n8284, n8285,
n8286, n8287, n8288, n8289, n8290, n8291, n8292, n8293, n8294, n8295,
n8296, n8297, n8298, n8299, n8300, n8301, n8302, n8303, n8304, n8305,
n8306, n8307, n8308, n8309, n8310, n8311, n8312, n8313, n8314, n8315,
n8316, n8317, n8318, n8319, n8320, n8321, n8322, n8323, n8324, n8325,
n8326, n8327, n8328, n8329, n8330, n8331, n8332, n8333, n8334, n8335,
n8336, n8337, n8338, n8339, n8340, n8341, n8342, n8343, n8344, n8345,
n8346, n8347, n8348, n8349, n8350, n8351, n8352, n8353, n8354, n8355,
n8356, n8357, n8358, n8359, n8360, n8361, n8362, n8363, n8364, n8365,
n8366, n8367, n8368, n8369, n8370, n8371, n8372, n8373, n8374, n8375,
n8376, n8377, n8378, n8379, n8380, n8381, n8382, n8383, n8384, n8385,
n8386, n8387, n8388, n8389, n8390, n8391, n8392, n8393, n8394, n8395,
n8396, n8397, n8398, n8399, n8400, n8401, n8402, n8403, n8404, n8405,
n8406, n8407, n8408, n8409, n8410, n8411, n8412, n8413, n8414, n8415,
n8416, n8417, n8418, n8419, n8420, n8421, n8422, n8423, n8424, n8425,
n8426, n8427, n8428, n8429, n8430, n8431, n8432, n8433, n8434, n8435,
n8436, n8437, n8438, n8439, n8440, n8441, n8442, n8443, n8444, n8445,
n8446, n8447, n8448, n8449, n8450, n8451, n8452, n8453, n8454, n8455,
n8456, n8457, n8458, n8459, n8460, n8461, n8462, n8463, n8464, n8465,
n8466, n8467, n8468, n8469, n8470, n8471, n8472, n8473, n8474, n8475,
n8476, n8477, n8478, n8479, n8480, n8481, n8482, n8483, n8484, n8485,
n8486, n8487, n8488, n8489, n8490, n8491, n8492, n8493, n8494, n8495,
n8496, n8497, n8498, n8499, n8500, n8501, n8502, n8503, n8504, n8505,
n8506, n8507, n8508, n8509, n8510, n8511, n8512, n8513, n8514, n8515,
n8516, n8517, n8518, n8519, n8520, n8521, n8522, n8523, n8524, n8525,
n8526, n8527, n8528, n8529, n8530, n8531, n8532, n8533, n8534, n8535,
n8536, n8537, n8538, n8539, n8540, n8541, n8542, n8543, n8544, n8545,
n8546, n8547, n8548, n8549, n8550, n8551, n8552, n8553, n8554, n8555,
n8556, n8557, n8558, n8559, n8560, n8561, n8562, n8563, n8564, n8565,
n8566, n8567, n8568, n8569, n8570, n8571, n8572, n8573, n8574, n8575,
n8576, n8577, n8578, n8579, n8580, n8581, n8582, n8583, n8584, n8585,
n8586, n8587, n8588, n8589, n8590, n8591, n8592, n8593, n8594, n8595,
n8596, n8597, n8598, n8599, n8600, n8601, n8602, n8603, n8604, n8605,
n8606, n8607, n8608, n8609, n8610, n8611, n8612, n8613, n8614, n8615,
n8616, n8617, n8618, n8619, n8620, n8621, n8622, n8623, n8624, n8625,
n8626, n8627, n8628, n8629, n8630, n8631, n8632, n8633, n8634, n8635,
n8636, n8637, n8638, n8639, n8640, n8641, n8642, n8643, n8644, n8645,
n8646, n8647, n8648, n8649, n8650, n8651, n8652, n8653, n8654, n8655,
n8656, n8657, n8658, n8659, n8660, n8661, n8662, n8663, n8664, n8665,
n8666, n8667, n8668, n8669, n8670, n8671, n8672, n8673, n8674, n8675,
n8676, n8677, n8678, n8679, n8680, n8681, n8682, n8683, n8684, n8685,
n8686, n8687, n8688, n8689, n8690, n8691, n8692, n8693, n8694, n8695,
n8696, n8697, n8698, n8699, n8700, n8701, n8702, n8703, n8704, n8705,
n8706, n8707, n8708, n8709, n8710, n8711, n8712, n8713, n8714, n8715,
n8716, n8717, n8718, n8719, n8720, n8721, n8722, n8723, n8724, n8725,
n8726, n8727, n8728, n8729, n8730, n8731, n8732, n8733, n8734, n8735,
n8736, n8737, n8738, n8739, n8740, n8741, n8742, n8743, n8744, n8745,
n8746, n8747, n8748, n8749, n8750, n8751, n8752, n8753, n8754, n8755,
n8756, n8757, n8758, n8759, n8760, n8761, n8762, n8763, n8764, n8765,
n8766, n8767, n8768, n8769, n8770, n8771, n8772, n8773, n8774, n8775,
n8776, n8777, n8778, n8779, n8780, n8781, n8782, n8783, n8784, n8785,
n8786, n8787, n8788, n8789, n8790, n8791, n8792, n8793, n8794, n8795,
n8796, n8797, n8798, n8799, n8800, n8801, n8802, n8803, n8804, n8805,
n8806, n8807, n8808, n8809, n8810, n8811, n8812, n8813, n8814, n8815,
n8816, n8817, n8818, n8819, n8820, n8821, n8822, n8823, n8824, n8825,
n8826, n8827, n8828, n8829, n8830, n8831, n8832, n8833, n8834, n8835,
n8836, n8837, n8838, n8839, n8840, n8841, n8842, n8843, n8844, n8845,
n8846, n8847, n8848, n8849, n8850, n8851, n8852, n8853, n8854, n8855,
n8856, n8857, n8858, n8859, n8860, n8861, n8862, n8863, n8864, n8865,
n8866, n8867, n8868, n8869, n8870, n8871, n8872, n8873, n8874, n8875,
n8876, n8877, n8878, n8879, n8880, n8881, n8882, n8883, n8884, n8885,
n8886, n8887, n8888, n8889, n8890, n8891, n8892, n8893, n8894, n8895,
n8896, n8897, n8898, n8899, n8900, n8901, n8902, n8903, n8904, n8905,
n8906, n8907, n8908, n8909, n8910, n8911, n8912, n8913, n8914, n8915,
n8916, n8917, n8918, n8919, n8920, n8921, n8922, n8923, n8924, n8925,
n8926, n8927, n8928, n8929, n8930, n8931, n8932, n8933, n8934, n8935,
n8936, n8937, n8938, n8939, n8940, n8941, n8942, n8943, n8944, n8945,
n8946, n8947, n8948, n8949, n8950, n8951, n8952, n8953, n8954, n8955,
n8956, n8957, n8958, n8959, n8960, n8961, n8962, n8963, n8964, n8965,
n8966, n8967, n8968, n8969, n8970, n8971, n8972, n8973, n8974, n8975,
n8976, n8977, n8978, n8979, n8980, n8981, n8982, n8983, n8984, n8985,
n8986, n8987, n8988, n8989, n8990, n8991, n8992, n8993, n8994, n8995,
n8996, n8997, n8998, n8999, n9000, n9001, n9002, n9003, n9004, n9005,
n9006, n9007, n9008, n9009, n9010, n9011, n9012, n9013, n9014, n9015,
n9016, n9017, n9018, n9019, n9020, n9021, n9022, n9023, n9024, n9025,
n9026, n9027, n9028, n9029, n9030, n9031, n9032, n9033, n9034, n9035,
n9036, n9037, n9038, n9039, n9040, n9041, n9042, n9043, n9044, n9045,
n9046, n9047, n9048, n9049, n9050, n9051, n9052, n9053, n9054, n9055,
n9056, n9057, n9058, n9059, n9060, n9061, n9062, n9063, n9064, n9065,
n9066, n9067, n9068, n9069, n9070, n9071, n9072, n9073, n9074, n9075,
n9076, n9077, n9078, n9079, n9080, n9081, n9082, n9083, n9084, n9085,
n9086, n9087, n9088, n9089, n9090, n9091, n9092, n9093, n9094, n9095,
n9096, n9097, n9098, n9099, n9100, n9101, n9102, n9103, n9104, n9105,
n9106, n9107, n9108, n9109, n9110, n9111, n9112, n9113, n9114, n9115,
n9116, n9117, n9118, n9119, n9120, n9121, n9122, n9123, n9124, n9125,
n9126, n9127, n9128, n9129, n9130, n9131, n9132, n9133, n9134, n9135,
n9136, n9137, n9138, n9139, n9140, n9141, n9142, n9143, n9144, n9145,
n9146, n9147, n9148, n9149, n9150, n9151, n9152, n9153, n9154, n9155,
n9156, n9157, n9158, n9159, n9160, n9161, n9162, n9163, n9164, n9165,
n9166, n9167, n9168, n9169, n9170, n9171, n9172, n9173, n9174, n9175,
n9176, n9177, n9178, n9179, n9180, n9181, n9182, n9183, n9184, n9185,
n9186, n9187, n9188, n9189, n9190, n9191, n9192, n9193, n9194, n9195,
n9196, n9197, n9198, n9199, n9200, n9201, n9202, n9203, n9204, n9205,
n9206, n9207, n9208, n9209, n9210, n9211, n9212, n9213, n9214, n9215,
n9216, n9217, n9218, n9219, n9220, n9221, n9222, n9223, n9224, n9225,
n9226, n9227, n9228, n9229, n9230, n9231, n9232, n9233, n9234, n9235,
n9236, n9237, n9238, n9239, n9240, n9241, n9242, n9243, n9244, n9245,
n9246, n9247, n9248, n9249, n9250, n9251, n9252, n9253, n9254, n9255,
n9256, n9257, n9258, n9259, n9260, n9261, n9262, n9263, n9264, n9265,
n9266, n9267, n9268, n9269, n9270, n9271, n9272, n9273, n9274, n9275,
n9276, n9277, n9278, n9279, n9280, n9281, n9282, n9283, n9284, n9285,
n9286, n9287, n9288, n9289, n9290, n9291, n9292, n9293, n9294, n9295,
n9296, n9297, n9298, n9299, n9300, n9301, n9302, n9303, n9304, n9305,
n9306, n9307, n9308, n9309, n9310, n9311, n9312, n9313, n9314, n9315,
n9316, n9317, n9318, n9319, n9320, n9321, n9322, n9323, n9324, n9325,
n9326, n9327, n9328, n9329, n9330, n9331, n9332, n9333, n9334, n9335,
n9336, n9337, n9338, n9339, n9340, n9341, n9342, n9343, n9344, n9345,
n9346, n9347, n9348, n9349, n9350, n9351, n9352, n9353, n9354, n9355,
n9356, n9357, n9358, n9359, n9360, n9361, n9362, n9363, n9364, n9365,
n9366, n9367, n9368, n9369, n9370, n9371, n9372, n9373, n9374, n9375,
n9376, n9377, n9378, n9379, n9380, n9381, n9382, n9383, n9384, n9385,
n9386, n9387, n9388, n9389, n9390, n9391, n9392, n9393, n9394, n9395,
n9396, n9397, n9398, n9399, n9400, n9401, n9402, n9403, n9404, n9405,
n9406, n9407, n9408, n9409, n9410, n9411, n9412, n9413, n9414, n9415,
n9416, n9417, n9418, n9419, n9420, n9421, n9422, n9423, n9424, n9425,
n9426, n9427, n9428, n9429, n9430, n9431, n9432, n9433, n9434, n9435,
n9436, n9437, n9438, n9439, n9440, n9441, n9442, n9443, n9444, n9445,
n9446, n9447, n9448, n9449, n9450, n9451, n9452, n9453, n9454, n9455,
n9456, n9457, n9458, n9459, n9460, n9461, n9462, n9463, n9464, n9465,
n9466, n9467, n9468, n9469, n9470, n9471, n9472, n9473, n9474, n9475,
n9476, n9477, n9478, n9479, n9480, n9481, n9482, n9483, n9484, n9485,
n9486, n9487, n9488, n9489, n9490, n9491, n9492, n9493, n9494, n9495,
n9496, n9497, n9498, n9499, n9500, n9501, n9502, n9503, n9504, n9505,
n9506, n9507, n9508, n9509, n9510, n9511, n9512, n9513, n9514, n9515,
n9516, n9517, n9518, n9519, n9520, n9521, n9522, n9523, n9524, n9525,
n9526, n9527, n9528, n9529, n9530, n9531, n9532, n9533, n9534, n9535,
n9536, n9537, n9538, n9539, n9540, n9541, n9542, n9543, n9544, n9545,
n9546, n9547, n9548, n9549, n9550, n9551, n9552, n9553, n9554, n9555,
n9556, n9557, n9558, n9559, n9560, n9561, n9562, n9563, n9564, n9565,
n9566, n9567, n9568, n9569, n9570, n9571, n9572, n9573, n9574, n9575,
n9576, n9577, n9578, n9579, n9580, n9581, n9582, n9583, n9584, n9585,
n9586, n9587, n9588, n9589, n9590, n9591, n9592, n9593, n9594, n9595,
n9596, n9597, n9598, n9599, n9600, n9601, n9602, n9603, n9604, n9605,
n9606, n9607, n9608, n9609, n9610, n9611, n9612, n9613, n9614, n9615,
n9616, n9617, n9618, n9619, n9620, n9621, n9622, n9623, n9624, n9625,
n9626, n9627, n9628, n9629, n9630, n9631, n9632, n9633, n9634, n9635,
n9636, n9637, n9638, n9639, n9640, n9641, n9642, n9643, n9644, n9645,
n9646, n9647, n9648, n9649, n9650, n9651, n9652, n9653, n9654, n9655,
n9656, n9657, n9658, n9659, n9660, n9661, n9662, n9663, n9664, n9665,
n9666, n9667, n9668, n9669, n9670, n9671, n9672, n9673, n9674, n9675,
n9676, n9677, n9678, n9679, n9680, n9681, n9682, n9683, n9684, n9685,
n9686, n9687, n9688, n9689, n9690, n9691, n9692, n9693, n9694, n9695,
n9696, n9697, n9698, n9699, n9700, n9701, n9702, n9703, n9704, n9705,
n9706, n9707, n9708, n9709, n9710, n9711, n9712, n9713, n9714, n9715,
n9716, n9717, n9718, n9719, n9720, n9721, n9722, n9723, n9724, n9725,
n9726, n9727, n9728, n9729, n9730, n9731, n9732, n9733, n9734, n9735,
n9736, n9737, n9738, n9739, n9740, n9741, n9742, n9743, n9744, n9745,
n9746, n9747, n9748, n9749, n9750, n9751, n9752, n9753, n9754, n9755,
n9756, n9757, n9758, n9759, n9760, n9761, n9762, n9763, n9764, n9765,
n9766, n9767, n9768, n9769, n9770, n9771, n9772, n9773, n9774, n9775,
n9776, n9777, n9778, n9779, n9780, n9781, n9782, n9783, n9784, n9785,
n9786, n9787, n9788, n9789, n9790, n9791, n9792, n9793, n9794, n9795,
n9796, n9797, n9798, n9799, n9800, n9801, n9802, n9803, n9804, n9805,
n9806, n9807, n9808, n9809, n9810, n9811, n9812, n9813, n9814, n9815,
n9816, n9817, n9818, n9819, n9820, n9821, n9822, n9823, n9824, n9825,
n9826, n9827, n9828, n9829, n9830, n9831, n9832, n9833, n9834, n9835,
n9836, n9837, n9838, n9839, n9840, n9841, n9842, n9843, n9844, n9845,
n9846, n9847, n9848, n9849, n9850, n9851, n9852, n9853, n9854, n9855,
n9856, n9857, n9858, n9859, n9860, n9861, n9862, n9863, n9864, n9865,
n9866, n9867, n9868, n9869, n9870, n9871, n9872, n9873, n9874, n9875,
n9876, n9877, n9878, n9879, n9880, n9881, n9882, n9883, n9884, n9885,
n9886, n9887, n9888, n9889, n9890, n9891, n9892, n9893, n9894, n9895,
n9896, n9897, n9898, n9899, n9900, n9901, n9902, n9903, n9904, n9905,
n9906, n9907, n9908, n9909, n9910, n9911, n9912, n9913, n9914, n9915,
n9916, n9917, n9918, n9919, n9920, n9921, n9922, n9923, n9924, n9925,
n9926, n9927, n9928, n9929, n9930, n9931, n9932, n9933, n9934, n9935,
n9936, n9937, n9938, n9939, n9940, n9941, n9942, n9943, n9944, n9945,
n9946, n9947, n9948, n9949, n9950, n9951, n9952, n9953, n9954, n9955,
n9956, n9957, n9958, n9959, n9960, n9961, n9962, n9963, n9964, n9965,
n9966, n9967, n9968, n9969, n9970, n9971, n9972, n9973, n9974, n9975,
n9976, n9977, n9978, n9979, n9980, n9981, n9982, n9983, n9984, n9985,
n9986, n9987, n9988, n9989, n9990, n9991, n9992, n9993, n9994, n9995,
n9996, n9997, n9998, n9999, n10000, n10001, n10002, n10003, n10004,
n10005, n10006, n10007, n10008, n10009, n10010, n10011, n10012,
n10013, n10014, n10015, n10016, n10017, n10018, n10019, n10020,
n10021, n10022, n10023, n10024, n10025, n10026, n10027, n10028,
n10029, n10030, n10031, n10032, n10033, n10034, n10035, n10036,
n10037, n10038, n10039, n10040, n10041, n10042, n10043, n10044,
n10045, n10046, n10047, n10048, n10049, n10050, n10051, n10052,
n10053, n10054, n10055, n10056, n10057, n10058, n10059, n10060,
n10061, n10062, n10063, n10064, n10065, n10066, n10067, n10068,
n10069, n10070, n10071, n10072, n10073, n10074, n10075, n10076,
n10077, n10078, n10079, n10080, n10081, n10082, n10083, n10084,
n10085, n10086, n10087, n10088, n10089, n10090, n10091, n10092,
n10093, n10094, n10095, n10096, n10097, n10098, n10099, n10100,
n10101, n10102, n10103, n10104, n10105, n10106, n10107, n10108,
n10109, n10110, n10111, n10112, n10113, n10114, n10115, n10116,
n10117, n10118, n10119, n10120, n10121, n10122, n10123, n10124,
n10125, n10126, n10127, n10128, n10129, n10130, n10131, n10132,
n10133, n10134, n10135, n10136, n10137, n10138, n10139, n10140,
n10141, n10142, n10143, n10144, n10145, n10146, n10147, n10148,
n10149, n10150, n10151, n10152, n10153, n10154, n10155, n10156,
n10157, n10158, n10159, n10160, n10161, n10162, n10163, n10164,
n10165, n10166, n10167, n10168, n10169, n10170, n10171, n10172,
n10173, n10174, n10175, n10176, n10177, n10178, n10179, n10180,
n10181, n10182, n10183, n10184, n10185, n10186, n10187, n10188,
n10189, n10190, n10191, n10192, n10193, n10194, n10195, n10196,
n10197, n10198, n10199, n10200, n10201, n10202, n10203, n10204,
n10205, n10206, n10207, n10208, n10209, n10210, n10211, n10212,
n10213, n10214, n10215, n10216, n10217, n10218, n10219, n10220,
n10221, n10222, n10223, n10224, n10225, n10226, n10227, n10228,
n10229, n10230, n10231, n10232, n10233, n10234, n10235, n10236,
n10237, n10238, n10239, n10240, n10241, n10242, n10243, n10244,
n10245, n10246, n10247, n10248, n10249, n10250, n10251, n10252,
n10253, n10254, n10255, n10256, n10257, n10258, n10259, n10260,
n10261, n10262, n10263, n10264, n10265, n10266, n10267, n10268,
n10269, n10270, n10271, n10272, n10273, n10274, n10275, n10276,
n10277, n10278, n10279, n10280, n10281, n10282, n10283, n10284,
n10285, n10286, n10287, n10288, n10289, n10290, n10291, n10292,
n10293, n10294, n10295, n10296, n10297, n10298, n10299, n10300,
n10301, n10302, n10303, n10304, n10305, n10306, n10307, n10308,
n10309, n10310, n10311, n10312, n10313, n10314, n10315, n10316,
n10317, n10318, n10319, n10320, n10321, n10322, n10323, n10324,
n10325, n10326, n10327, n10328, n10329, n10330, n10331, n10332,
n10333, n10334, n10335, n10336, n10337, n10338, n10339, n10340,
n10341, n10342, n10343, n10344, n10345, n10346, n10347, n10348,
n10349, n10350, n10351, n10352, n10353, n10354, n10355, n10356,
n10357, n10358, n10359, n10360, n10361, n10362, n10363, n10364,
n10365, n10366, n10367, n10368, n10369, n10370, n10371, n10372,
n10373, n10374, n10375, n10376, n10377, n10378, n10379, n10380,
n10381, n10382, n10383, n10384, n10385, n10386, n10387, n10388,
n10389, n10390, n10391, n10392, n10393, n10394, n10395, n10396,
n10397, n10398, n10399, n10400, n10401, n10402, n10403, n10404,
n10405, n10406, n10407, n10408, n10409, n10410, n10411, n10412,
n10413, n10414, n10415, n10416, n10417, n10418, n10419, n10420,
n10421, n10422, n10423, n10424, n10425, n10426, n10427, n10428,
n10429, n10430, n10431, n10432, n10433, n10434, n10435, n10436,
n10437, n10438, n10439, n10440, n10441, n10442, n10443, n10444,
n10445, n10446, n10447, n10448, n10449, n10450, n10451, n10452,
n10453, n10454, n10455, n10456, n10457, n10458, n10459, n10460,
n10461, n10462, n10463, n10464, n10465, n10466, n10467, n10468,
n10469, n10470, n10471, n10472, n10473, n10474, n10475, n10476,
n10477, n10478, n10479, n10480, n10481, n10482, n10483, n10484,
n10485, n10486, n10487, n10488, n10489, n10490, n10491, n10492,
n10493, n10494, n10495, n10496, n10497, n10498, n10499, n10500,
n10501, n10502, n10503, n10504, n10505, n10506, n10507, n10508,
n10509, n10510, n10511, n10512, n10513, n10514, n10515, n10516,
n10517, n10518, n10519, n10520, n10521, n10522, n10523, n10524,
n10525, n10526, n10527, n10528, n10529, n10530, n10531, n10532,
n10533, n10534, n10535, n10536, n10537, n10538, n10539, n10540,
n10541, n10542, n10543, n10544, n10545, n10546, n10547, n10548,
n10549, n10550, n10551, n10552, n10553, n10554, n10555, n10556,
n10557, n10558, n10559, n10560, n10561, n10562, n10563, n10564,
n10565, n10566, n10567, n10568, n10569, n10570, n10571, n10572,
n10573, n10574, n10575, n10576, n10577, n10578, n10579, n10580,
n10581, n10582, n10583, n10584, n10585, n10586, n10587, n10588,
n10589, n10590, n10591, n10592, n10593, n10594, n10595, n10596,
n10597, n10598, n10599, n10600, n10601, n10602, n10603, n10604,
n10605, n10606, n10607, n10608, n10609, n10610, n10611, n10612,
n10613, n10614, n10615, n10616, n10617, n10618, n10619, n10620,
n10621, n10622, n10623, n10624, n10625, n10626, n10627, n10628,
n10629, n10630, n10631, n10632, n10633, n10634, n10635, n10636,
n10637, n10638, n10639, n10640, n10641, n10642, n10643, n10644,
n10645, n10646, n10647, n10648, n10649, n10650, n10651, n10652,
n10653, n10654, n10655, n10656, n10657, n10658, n10659, n10660,
n10661, n10662, n10663, n10664, n10665, n10666, n10667, n10668,
n10669, n10670, n10671, n10672, n10673, n10674, n10675, n10676,
n10677, n10678, n10679, n10680, n10681, n10682, n10683, n10684,
n10685, n10686, n10687, n10688, n10689, n10690, n10691, n10692,
n10693, n10694, n10695, n10696, n10697, n10698, n10699, n10700,
n10701, n10702, n10703, n10704, n10705, n10706, n10707, n10708,
n10709, n10710, n10711, n10712, n10713, n10714, n10715, n10716,
n10717, n10718, n10719, n10720, n10721, n10722, n10723, n10724,
n10725, n10726, n10727, n10728, n10729, n10730, n10731, n10732,
n10733, n10734, n10735, n10736, n10737, n10738, n10739, n10740,
n10741, n10742, n10743, n10744, n10745, n10746, n10747, n10748,
n10749, n10750, n10751, n10752, n10753, n10754, n10755, n10756,
n10757, n10758, n10759, n10760, n10761, n10762, n10763, n10764,
n10765, n10766, n10767, n10768, n10769, n10770, n10771, n10772,
n10773, n10774, n10775, n10776, n10777, n10778, n10779, n10780,
n10781, n10782, n10783, n10784, n10785, n10786, n10787, n10788,
n10789, n10790, n10791, n10792, n10793, n10794, n10795, n10796,
n10797, n10798, n10799, n10800, n10801, n10802, n10803, n10804,
n10805, n10806, n10807, n10808, n10809, n10810, n10811, n10812,
n10813, n10814, n10815, n10816, n10817, n10818, n10819, n10820,
n10821, n10822, n10823, n10824, n10825, n10826, n10827, n10828,
n10829, n10830, n10831, n10832, n10833, n10834, n10835, n10836,
n10837, n10838, n10839, n10840, n10841, n10842, n10843, n10844,
n10845, n10846, n10847, n10848, n10849, n10850, n10851, n10852,
n10853, n10854, n10855, n10856, n10857, n10858, n10859, n10860,
n10861, n10862, n10863, n10864, n10865, n10866, n10867, n10868,
n10869, n10870, n10871, n10872, n10873, n10874, n10875, n10876,
n10877, n10878, n10879, n10880, n10881, n10882, n10883, n10884,
n10885, n10886, n10887, n10888, n10889, n10890, n10891, n10892,
n10893, n10894, n10895, n10896, n10897, n10898, n10899, n10900,
n10901, n10902, n10903, n10904, n10905, n10906, n10907, n10908,
n10909, n10910, n10911, n10912, n10913, n10914, n10915, n10916,
n10917, n10918, n10919, n10920, n10921, n10922, n10923, n10924,
n10925, n10926, n10927, n10928, n10929, n10930, n10931, n10932,
n10933, n10934, n10935, n10936, n10937, n10938, n10939, n10940,
n10941, n10942, n10943, n10944, n10945, n10946, n10947, n10948,
n10949, n10950, n10951, n10952, n10953, n10954, n10955, n10956,
n10957, n10958, n10959, n10960, n10961, n10962, n10963, n10964,
n10965, n10966, n10967, n10968, n10969, n10970, n10971, n10972,
n10973, n10974, n10975, n10976, n10977, n10978, n10979, n10980,
n10981, n10982, n10983, n10984, n10985, n10986, n10987, n10988,
n10989, n10990, n10991, n10992, n10993, n10994, n10995, n10996,
n10997, n10998, n10999, n11000, n11001, n11002, n11003, n11004,
n11005, n11006, n11007, n11008, n11009, n11010, n11011, n11012,
n11013, n11014, n11015, n11016, n11017, n11018, n11019, n11020,
n11021, n11022, n11023, n11024, n11025, n11026, n11027, n11028,
n11029, n11030, n11031, n11032, n11033, n11034, n11035, n11036,
n11037, n11038, n11039, n11040, n11041, n11042, n11043, n11044,
n11045, n11046, n11047, n11048, n11049, n11050, n11051, n11052,
n11053, n11054, n11055, n11056, n11057, n11058, n11059, n11060,
n11061, n11062, n11063, n11064, n11065, n11066, n11067, n11068,
n11069, n11070, n11071, n11072, n11073, n11074, n11075, n11076,
n11077, n11078, n11079, n11080, n11081, n11082, n11083, n11084,
n11085, n11086, n11087, n11088, n11089, n11090, n11091, n11092,
n11093, n11094, n11095, n11096, n11097, n11098, n11099, n11100,
n11101, n11102, n11103, n11104, n11105, n11106, n11107, n11108,
n11109, n11110, n11111, n11112, n11113, n11114, n11115, n11116,
n11117, n11118, n11119, n11120, n11121, n11122, n11123, n11124,
n11125, n11126, n11127, n11128, n11129, n11130, n11131, n11132,
n11133, n11134, n11135, n11136, n11137, n11138, n11139, n11140,
n11141, n11142, n11143, n11144, n11145, n11146, n11147, n11148,
n11149, n11150, n11151, n11152, n11153, n11154, n11155, n11156,
n11157, n11158, n11159, n11160, n11161, n11162, n11163, n11164,
n11165, n11166, n11167, n11168, n11169, n11170, n11171, n11172,
n11173, n11174, n11175, n11176, n11177, n11178, n11179, n11180,
n11181, n11182, n11183, n11184, n11185, n11186, n11187, n11188,
n11189, n11190, n11191, n11192, n11193, n11194, n11195, n11196,
n11197, n11198, n11199, n11200, n11201, n11202, n11203, n11204,
n11205, n11206, n11207, n11208, n11209, n11210, n11211, n11212,
n11213, n11214, n11215, n11216, n11217, n11218, n11219, n11220,
n11221, n11222, n11223, n11224, n11225, n11226, n11227, n11228,
n11229, n11230, n11231, n11232, n11233, n11234, n11235, n11236,
n11237, n11238, n11239, n11240, n11241, n11242, n11243, n11244,
n11245, n11246, n11247, n11248, n11249, n11250, n11251, n11252,
n11253, n11254, n11255, n11256, n11257, n11258, n11259, n11260,
n11261, n11262, n11263, n11264, n11265, n11266, n11267, n11268,
n11269, n11270, n11271, n11272, n11273, n11274, n11275, n11276,
n11277, n11278, n11279, n11280, n11281, n11282, n11283, n11284,
n11285, n11286, n11287, n11288, n11289, n11290, n11291, n11292,
n11293, n11294, n11295, n11296, n11297, n11298, n11299, n11300,
n11301, n11302, n11303, n11304, n11305, n11306, n11307, n11308,
n11309, n11310, n11311, n11312, n11313, n11314, n11315, n11316,
n11317, n11318, n11319, n11320, n11321, n11322, n11323, n11324,
n11325, n11326, n11327, n11328, n11329, n11330, n11331, n11332,
n11333, n11334, n11335, n11336, n11337, n11338, n11339, n11340,
n11341, n11342, n11343, n11344, n11345, n11346, n11347, n11348,
n11349, n11350, n11351, n11352, n11353, n11354, n11355, n11356,
n11357, n11358, n11359, n11360, n11361, n11362, n11363, n11364,
n11365, n11366, n11367, n11368, n11369, n11370, n11371, n11372,
n11373, n11374, n11375, n11376, n11377, n11378, n11379, n11380,
n11381, n11382, n11383, n11384, n11385, n11386, n11387, n11388,
n11389, n11390, n11391, n11392, n11393, n11394, n11395, n11396,
n11397, n11398, n11399, n11400, n11401, n11402, n11403, n11404,
n11405, n11406, n11407, n11408, n11409, n11410, n11411, n11412,
n11413, n11414, n11415, n11416, n11417, n11418, n11419, n11420,
n11421, n11422, n11423, n11424, n11425, n11426, n11427, n11428,
n11429, n11430, n11431, n11432, n11433, n11434, n11435, n11436,
n11437, n11438, n11439, n11440, n11441, n11442, n11443, n11444,
n11445, n11446, n11447, n11448, n11449, n11450, n11451, n11452,
n11453, n11454, n11455, n11456, n11457, n11458, n11459, n11460,
n11461, n11462, n11463, n11464, n11465, n11466, n11467, n11468,
n11469, n11470, n11471, n11472, n11473, n11474, n11475, n11476,
n11477, n11478, n11479, n11480, n11481, n11482, n11483, n11484,
n11485, n11486, n11487, n11488, n11489, n11490, n11491, n11492,
n11493, n11494, n11495, n11496, n11497, n11498, n11499, n11500,
n11501, n11502, n11503, n11504, n11505, n11506, n11507, n11508,
n11509, n11510, n11511, n11512, n11513, n11514, n11515, n11516,
n11517, n11518, n11519, n11520, n11521, n11522, n11523, n11524,
n11525, n11526, n11527, n11528, n11529, n11530, n11531, n11532,
n11533, n11534, n11535, n11536, n11537, n11538, n11539, n11540,
n11541, n11542, n11543, n11544, n11545, n11546, n11547, n11548,
n11549, n11550, n11551, n11552, n11553, n11554, n11555, n11556,
n11557, n11558, n11559, n11560, n11561, n11562, n11563, n11564,
n11565, n11566, n11567, n11568, n11569, n11570, n11571, n11572,
n11573, n11574, n11575, n11576, n11577, n11578, n11579, n11580,
n11581, n11582, n11583, n11584, n11585, n11586, n11587, n11588,
n11589, n11590, n11591, n11592, n11593, n11594, n11595, n11596,
n11597, n11598, n11599, n11600, n11601, n11602, n11603, n11604,
n11605, n11606, n11607, n11608, n11609, n11610, n11611, n11612,
n11613, n11614, n11615, n11616, n11617, n11618, n11619, n11620,
n11621, n11622, n11623, n11624, n11625, n11626, n11627, n11628,
n11629, n11630, n11631, n11632, n11633, n11634, n11635, n11636,
n11637, n11638, n11639, n11640, n11641, n11642, n11643, n11644,
n11645, n11646, n11647, n11648, n11649, n11650, n11651, n11652,
n11653, n11654, n11655, n11656, n11657, n11658, n11659, n11660,
n11661, n11662, n11663, n11664, n11665, n11666, n11667, n11668,
n11669, n11670, n11671, n11672, n11673, n11674, n11675, n11676,
n11677, n11678, n11679, n11680, n11681, n11682, n11683, n11684,
n11685, n11686, n11687, n11688, n11689, n11690, n11691, n11692,
n11693, n11694, n11695, n11696, n11697, n11698, n11699, n11700,
n11701, n11702, n11703, n11704, n11705, n11706, n11707, n11708,
n11709, n11710, n11711, n11712, n11713, n11714, n11715, n11716,
n11717, n11718, n11719, n11720, n11721, n11722, n11723, n11724,
n11725, n11726, n11727, n11728, n11729, n11730, n11731, n11732,
n11733, n11734, n11735, n11736, n11737, n11738, n11739, n11740,
n11741, n11742, n11743, n11744, n11745, n11746, n11747, n11748,
n11749, n11750, n11751, n11752, n11753, n11754, n11755, n11756,
n11757, n11758, n11759, n11760, n11761, n11762, n11763, n11764,
n11765, n11766, n11767, n11768, n11769, n11770, n11771, n11772,
n11773, n11774, n11775, n11776, n11777, n11778, n11779, n11780,
n11781, n11782, n11783, n11784, n11785;
wire [32:0] EVEN1_Q_left;
wire [32:31] EVEN1_Q_right;
wire [17:4] EVEN1_S_B;
wire [12:8] EVEN1_middle_RECURSIVE_EVEN1_S_B;
wire [26:0] EVEN1_middle_RECURSIVE_EVEN1_Q_left;
DFFRXLTS R_147 ( .D(sgf_result_o[76]), .CK(clk), .RN(n11719), .Q(n11688) );
DFFRXLTS R_171 ( .D(sgf_result_o[72]), .CK(clk), .RN(n11723), .Q(n11684) );
DFFRXLTS R_187 ( .D(sgf_result_o[70]), .CK(clk), .RN(n11720), .Q(n11683) );
DFFRXLTS R_298 ( .D(sgf_result_o[71]), .CK(clk), .RN(n594), .Q(n11682) );
DFFRXLTS R_301 ( .D(sgf_result_o[69]), .CK(clk), .RN(n267), .Q(n11681) );
DFFRXLTS R_625 ( .D(sgf_result_o[66]), .CK(clk), .RN(n328), .Q(n11678) );
DFFRXLTS R_659 ( .D(sgf_result_o[65]), .CK(clk), .RN(n327), .Q(n11677) );
DFFRXLTS R_778 ( .D(sgf_result_o[61]), .CK(clk), .RN(n328), .Q(n11673) );
DFFRXLTS R_831 ( .D(sgf_result_o[59]), .CK(clk), .RN(n327), .Q(n11672) );
DFFRXLTS R_925 ( .D(sgf_result_o[60]), .CK(clk), .RN(n328), .Q(n11671) );
DFFRXLTS R_1062 ( .D(sgf_result_o[54]), .CK(clk), .RN(n267), .Q(n11666) );
DFFRXLTS R_1121 ( .D(sgf_result_o[53]), .CK(clk), .RN(n266), .Q(n11665) );
DFFRXLTS R_1124 ( .D(sgf_result_o[51]), .CK(clk), .RN(n267), .Q(n11664) );
DFFRXLTS R_1127 ( .D(sgf_result_o[50]), .CK(clk), .RN(n266), .Q(n11663) );
DFFRXLTS R_1130 ( .D(sgf_result_o[49]), .CK(clk), .RN(n267), .Q(n11662) );
DFFRXLTS R_1133 ( .D(sgf_result_o[52]), .CK(clk), .RN(n266), .Q(n11661) );
DFFRXLTS R_1295 ( .D(sgf_result_o[44]), .CK(clk), .RN(n11719), .Q(n11656) );
DFFRXLTS R_1382 ( .D(sgf_result_o[43]), .CK(clk), .RN(n11720), .Q(n11655) );
DFFRXLTS R_1385 ( .D(sgf_result_o[41]), .CK(clk), .RN(n594), .Q(n11654) );
DFFRXLTS R_1388 ( .D(sgf_result_o[42]), .CK(clk), .RN(n11629), .Q(n11653) );
DFFRXLTS R_1687 ( .D(sgf_result_o[37]), .CK(clk), .RN(n454), .Q(n11649) );
DFFRXLTS R_2066 ( .D(sgf_result_o[36]), .CK(clk), .RN(n11724), .Q(n11648) );
DFFRXLTS R_2069 ( .D(sgf_result_o[35]), .CK(clk), .RN(n11629), .Q(n11647) );
DFFRXLTS R_2683 ( .D(sgf_result_o[32]), .CK(clk), .RN(n11723), .Q(n11644) );
DFFRXLTS R_4056 ( .D(sgf_result_o[31]), .CK(clk), .RN(n11719), .Q(n11642) );
DFFRXLTS R_4924 ( .D(sgf_result_o[29]), .CK(clk), .RN(n11720), .Q(n11641) );
DFFRXLTS R_5610 ( .D(sgf_result_o[28]), .CK(clk), .RN(n594), .Q(n11640) );
DFFRXLTS R_6129 ( .D(sgf_result_o[27]), .CK(clk), .RN(n11719), .Q(n11639) );
DFFSX1TS R_6131 ( .D(n11732), .CK(clk), .SN(n11628), .Q(n11638) );
DFFSX1TS R_6325_RW_1 ( .D(EVEN1_Q_right[32]), .CK(clk), .SN(n326), .Q(n11636), .QN(n1708) );
DFFRXLTS R_6616 ( .D(sgf_result_o[86]), .CK(clk), .RN(n11628), .Q(n11632) );
DFFRXLTS R_6628 ( .D(n11731), .CK(clk), .RN(n326), .Q(n11631), .QN(n11627)
);
DFFRXLTS EVEN1_finalreg_Q_reg_0_ ( .D(n110), .CK(clk), .RN(n11629), .Q(
sgf_result_o[0]) );
DFFRXLTS EVEN1_finalreg_Q_reg_1_ ( .D(n109), .CK(clk), .RN(n595), .Q(
sgf_result_o[1]) );
DFFRXLTS EVEN1_finalreg_Q_reg_3_ ( .D(n107), .CK(clk), .RN(n278), .Q(
sgf_result_o[3]) );
DFFRXLTS EVEN1_finalreg_Q_reg_5_ ( .D(n105), .CK(clk), .RN(n11724), .Q(
sgf_result_o[5]) );
DFFRXLTS EVEN1_finalreg_Q_reg_6_ ( .D(n104), .CK(clk), .RN(n277), .Q(
sgf_result_o[6]) );
DFFRXLTS EVEN1_finalreg_Q_reg_9_ ( .D(n101), .CK(clk), .RN(n11724), .Q(
sgf_result_o[9]) );
DFFRXLTS EVEN1_finalreg_Q_reg_10_ ( .D(n100), .CK(clk), .RN(n11721), .Q(
sgf_result_o[10]) );
DFFRXLTS EVEN1_finalreg_Q_reg_13_ ( .D(n97), .CK(clk), .RN(n11719), .Q(
sgf_result_o[13]) );
DFFRXLTS EVEN1_finalreg_Q_reg_14_ ( .D(n96), .CK(clk), .RN(n11723), .Q(
sgf_result_o[14]) );
DFFRXLTS EVEN1_finalreg_Q_reg_17_ ( .D(n93), .CK(clk), .RN(n11720), .Q(
sgf_result_o[17]) );
DFFRXLTS EVEN1_finalreg_Q_reg_18_ ( .D(n92), .CK(clk), .RN(n11721), .Q(
sgf_result_o[18]) );
DFFRXLTS EVEN1_finalreg_Q_reg_22_ ( .D(n88), .CK(clk), .RN(n11722), .Q(
sgf_result_o[22]) );
DFFRXLTS EVEN1_finalreg_Q_reg_2_ ( .D(n108), .CK(clk), .RN(n11785), .Q(
sgf_result_o[2]) );
DFFRXLTS EVEN1_finalreg_Q_reg_4_ ( .D(n106), .CK(clk), .RN(n11785), .Q(
sgf_result_o[4]) );
DFFRXLTS EVEN1_finalreg_Q_reg_7_ ( .D(n103), .CK(clk), .RN(n11723), .Q(
sgf_result_o[7]) );
DFFRXLTS EVEN1_finalreg_Q_reg_8_ ( .D(n102), .CK(clk), .RN(n594), .Q(
sgf_result_o[8]) );
DFFRXLTS EVEN1_finalreg_Q_reg_11_ ( .D(n99), .CK(clk), .RN(n455), .Q(
sgf_result_o[11]) );
DFFRXLTS EVEN1_finalreg_Q_reg_12_ ( .D(n98), .CK(clk), .RN(n326), .Q(
sgf_result_o[12]) );
DFFRXLTS EVEN1_finalreg_Q_reg_15_ ( .D(n95), .CK(clk), .RN(n11724), .Q(
sgf_result_o[15]) );
DFFRXLTS EVEN1_finalreg_Q_reg_16_ ( .D(n94), .CK(clk), .RN(n11722), .Q(
sgf_result_o[16]) );
DFFRXLTS EVEN1_finalreg_Q_reg_19_ ( .D(n91), .CK(clk), .RN(n11724), .Q(
sgf_result_o[19]) );
DFFRXLTS EVEN1_finalreg_Q_reg_20_ ( .D(n90), .CK(clk), .RN(n11629), .Q(
sgf_result_o[20]) );
DFFRXLTS EVEN1_finalreg_Q_reg_23_ ( .D(n87), .CK(clk), .RN(n594), .Q(
sgf_result_o[23]) );
DFFRXLTS EVEN1_finalreg_Q_reg_24_ ( .D(n86), .CK(clk), .RN(n11720), .Q(
sgf_result_o[24]) );
DFFRXLTS EVEN1_finalreg_Q_reg_25_ ( .D(n85), .CK(clk), .RN(n11723), .Q(
sgf_result_o[25]) );
DFFRXLTS EVEN1_finalreg_Q_reg_26_ ( .D(n84), .CK(clk), .RN(n278), .Q(
sgf_result_o[26]) );
DFFSX1TS R_6314 ( .D(n11729), .CK(clk), .SN(n594), .Q(n11637) );
DFFRXLTS add_x_2_R_6326_RW_0 ( .D(add_x_2_n144), .CK(clk), .RN(n326), .Q(
n11593), .QN(n11623) );
DFFSX1TS add_x_2_R_5785_RW_2 ( .D(add_x_2_n15), .CK(clk), .SN(n11613), .QN(
n11621) );
DFFRXLTS add_x_2_R_4647_RW_0 ( .D(add_x_2_n10), .CK(clk), .RN(n267), .QN(
n11618) );
DFFSX1TS add_x_2_R_5614_RW_0 ( .D(add_x_2_n136), .CK(clk), .SN(n11612), .QN(
n11616) );
DFFSX1TS add_x_2_R_6638 ( .D(add_x_2_n125), .CK(clk), .SN(n11610), .Q(n11608) );
DFFRXLTS add_x_2_R_6117_RW_1 ( .D(add_x_2_n164), .CK(clk), .RN(n325), .Q(
n11585) );
DFFSX1TS add_x_2_R_5292_RW_1 ( .D(add_x_2_n122), .CK(clk), .SN(n11613), .QN(
n11607) );
DFFRXLTS add_x_2_R_6192_RW_0 ( .D(add_x_2_n299), .CK(clk), .RN(n327), .Q(
n11590) );
DFFSX1TS add_x_2_R_3089_RW_3 ( .D(add_x_2_n6), .CK(clk), .SN(n11613), .QN(
n11614) );
DFFSX1TS add_x_2_R_5273_RW_1 ( .D(add_x_2_n12), .CK(clk), .SN(n11613), .QN(
n11619) );
DFFRXLTS add_x_2_R_5784_RW_2 ( .D(add_x_2_n184), .CK(clk), .RN(n277), .QN(
n11625) );
DFFSX1TS add_x_2_R_5968_RW_1 ( .D(add_x_2_n190), .CK(clk), .SN(n11613), .QN(
n11626) );
DFFRXLTS add_x_2_R_5969_RW_1 ( .D(add_x_2_n16), .CK(clk), .RN(n278), .QN(
n11622) );
DFFRXLTS add_x_2_R_5707_RW_0 ( .D(add_x_2_n197), .CK(clk), .RN(n266), .Q(
n11577) );
DFFSX1TS add_x_2_R_5708_RW_0 ( .D(add_x_2_n17), .CK(clk), .SN(n11610), .Q(
n11578) );
DFFSX1TS add_x_2_R_6536 ( .D(add_x_2_n118), .CK(clk), .SN(n11610), .Q(n11606) );
DFFSX1TS add_x_2_R_6534 ( .D(add_x_2_n117), .CK(clk), .SN(n11610), .Q(n11605) );
DFFRXLTS add_x_2_R_6346_RW_0 ( .D(add_x_2_n122), .CK(clk), .RN(n328), .Q(
n11596) );
DFFRXLTS add_x_2_R_6158_RW_0 ( .D(add_x_2_n117), .CK(clk), .RN(n11785), .Q(
n11589) );
DFFSX1TS add_x_2_R_4269_RW_1 ( .D(add_x_2_n9), .CK(clk), .SN(n11613), .Q(
n11571) );
DFFSX1TS add_x_2_R_4505_RW_1 ( .D(add_x_2_n8), .CK(clk), .SN(n11613), .QN(
n11620) );
DFFSX1TS add_x_2_R_5761 ( .D(add_x_2_n141), .CK(clk), .SN(n11610), .Q(n11580) );
DFFSX1TS add_x_2_R_6348 ( .D(add_x_2_n143), .CK(clk), .SN(n11610), .Q(n11597), .QN(n11617) );
DFFSX1TS add_x_2_R_5760_RW_1 ( .D(add_x_2_n138), .CK(clk), .SN(n11613), .Q(
n11579) );
DFFSX1TS add_x_2_R_6353 ( .D(add_x_2_n131), .CK(clk), .SN(n326), .Q(n11599),
.QN(n11624) );
DFFSX1TS add_x_2_R_6239_RW_0 ( .D(add_x_2_n172), .CK(clk), .SN(n328), .Q(
n11592) );
DFFSX1TS add_x_2_R_6238_RW_0 ( .D(add_x_2_n171), .CK(clk), .SN(n327), .Q(
n11591) );
DFFRXLTS add_x_2_R_5304_RW_0 ( .D(add_x_2_n13), .CK(clk), .RN(n11721), .Q(
n11573) );
DFFSX1TS add_x_2_R_6121 ( .D(add_x_2_n169), .CK(clk), .SN(n11612), .Q(n11588) );
DFFSX1TS add_x_2_R_6120 ( .D(add_x_2_n166), .CK(clk), .SN(n278), .Q(n11587)
);
DFFSX1TS add_x_2_R_6119 ( .D(add_x_2_n174), .CK(clk), .SN(n266), .Q(n11586)
);
DFFSX1TS add_x_2_R_6075 ( .D(add_x_2_n158), .CK(clk), .SN(n11612), .Q(n11584) );
DFFSX1TS add_x_2_R_6074 ( .D(add_x_2_n157), .CK(clk), .SN(n11612), .Q(n11583) );
DFFSX1TS add_x_2_R_6073 ( .D(add_x_2_n185), .CK(clk), .SN(n11612), .Q(n11582) );
DFFSX1TS add_x_2_R_5297_RW_0 ( .D(add_x_2_n11), .CK(clk), .SN(n11613), .Q(
n11572) );
DFFSX1TS add_x_2_R_5609_RW_0 ( .D(n11561), .CK(clk), .SN(n11612), .Q(n11576)
);
DFFSX1TS add_x_2_R_5608_RW_0 ( .D(add_x_2_n303), .CK(clk), .SN(n11612), .QN(
n11615) );
DFFSX1TS add_x_2_R_5800 ( .D(n11560), .CK(clk), .SN(n11613), .Q(n11581) );
DFFSX1TS add_x_2_R_5468 ( .D(add_x_2_n14), .CK(clk), .SN(n11721), .Q(n11575)
);
DFFSX1TS add_x_2_R_5467 ( .D(add_x_2_n179), .CK(clk), .SN(n11612), .Q(n11574) );
DFFSX1TS add_x_1_R_6627 ( .D(add_x_1_n799), .CK(clk), .SN(n11535), .Q(n11529) );
DFFSX1TS add_x_1_R_1002_RW_0 ( .D(EVEN1_Q_left[22]), .CK(clk), .SN(n11537),
.Q(n11485) );
DFFSX1TS add_x_1_R_873_RW_0 ( .D(EVEN1_Q_left[23]), .CK(clk), .SN(n11721),
.Q(n11478) );
DFFSX1TS add_x_1_R_5689_RW_1 ( .D(add_x_1_n69), .CK(clk), .SN(n11538), .Q(
n11497) );
DFFSX1TS add_x_1_R_6248 ( .D(add_x_1_n744), .CK(clk), .SN(n594), .Q(n11504)
);
DFFRXLTS add_x_1_R_6098_RW_1 ( .D(add_x_1_n739), .CK(clk), .RN(n11540), .QN(
n11542) );
DFFSX1TS add_x_1_R_6370_RW_1 ( .D(EVEN1_S_B[14]), .CK(clk), .SN(n11535),
.QN(n11556) );
DFFSX1TS add_x_1_R_6367_RW_1 ( .D(EVEN1_S_B[11]), .CK(clk), .SN(n11535), .Q(
n11520), .QN(n11554) );
DFFSX1TS add_x_1_R_6375 ( .D(EVEN1_S_B[10]), .CK(clk), .SN(n11536), .Q(
n11524), .QN(n11553) );
DFFSX1TS add_x_1_R_6373 ( .D(EVEN1_S_B[13]), .CK(clk), .SN(n11536), .Q(
n11522), .QN(n11549) );
DFFSX1TS add_x_1_R_1866_RW_13 ( .D(EVEN1_Q_left[1]), .CK(clk), .SN(n11536),
.QN(n11546) );
DFFSX1TS add_x_1_R_6640 ( .D(EVEN1_Q_left[0]), .CK(clk), .SN(n11535), .Q(
n11530), .QN(n11545) );
DFFRXLTS add_x_1_R_2073_RW_13 ( .D(EVEN1_Q_left[2]), .CK(clk), .RN(n11539),
.QN(n11544) );
DFFRXLTS add_x_1_R_6533_RW_0 ( .D(add_x_1_n732), .CK(clk), .RN(n11539), .Q(
n11528) );
DFFRXLTS add_x_1_R_6525_RW_0 ( .D(n11557), .CK(clk), .RN(n11540), .Q(n11527)
);
DFFSX1TS add_x_1_R_6336_RW_1 ( .D(add_x_1_n725), .CK(clk), .SN(n11538), .Q(
n11508), .QN(n11541) );
DFFRXLTS add_x_1_R_6372_RW_0 ( .D(EVEN1_S_B[15]), .CK(clk), .RN(n11539),
.QN(n11551) );
DFFSX1TS add_x_1_R_5965_RW_1 ( .D(add_x_1_n739), .CK(clk), .SN(n11538), .QN(
n11558) );
DFFSX1TS add_x_1_R_5793_RW_2 ( .D(n11557), .CK(clk), .SN(n11535), .Q(n11499)
);
DFFSX1TS add_x_1_R_6374 ( .D(EVEN1_S_B[16]), .CK(clk), .SN(n11536), .Q(
n11523), .QN(n11552) );
DFFSX1TS add_x_1_R_6371 ( .D(EVEN1_S_B[17]), .CK(clk), .SN(n11537), .Q(
n11521), .QN(n11550) );
DFFSX1TS add_x_1_R_6337 ( .D(add_x_1_n330), .CK(clk), .SN(n11537), .Q(n11509) );
DFFSX1TS add_x_1_R_6335 ( .D(add_x_1_n310), .CK(clk), .SN(n11537), .Q(n11507) );
DFFSX1TS add_x_1_R_6323 ( .D(add_x_1_n318), .CK(clk), .SN(n11537), .Q(n11505) );
DFFSX1TS add_x_1_R_6247 ( .D(add_x_1_n70), .CK(clk), .SN(n11720), .Q(n11503)
);
DFFSX1TS add_x_1_R_6208 ( .D(EVEN1_Q_right[31]), .CK(clk), .SN(n11537), .Q(
n11501) );
DFFSX1TS add_x_1_R_6203 ( .D(add_x_1_n732), .CK(clk), .SN(n11537), .QN(
n11555) );
DFFRXLTS add_x_1_R_1028 ( .D(EVEN1_Q_left[22]), .CK(clk), .RN(n11540), .Q(
n11489) );
DFFRXLTS add_x_1_R_939 ( .D(EVEN1_Q_left[23]), .CK(clk), .RN(n455), .Q(
n11481) );
DFFSX1TS add_x_1_R_878 ( .D(EVEN1_Q_left[24]), .CK(clk), .SN(n11538), .Q(
n11479) );
DFFSX1TS add_x_1_R_859 ( .D(EVEN1_Q_left[26]), .CK(clk), .SN(n11538), .Q(
n11477) );
DFFSX1TS add_x_1_R_856 ( .D(EVEN1_Q_left[28]), .CK(clk), .SN(n11538), .Q(
n11476) );
DFFSX1TS add_x_1_R_851 ( .D(EVEN1_Q_left[27]), .CK(clk), .SN(n11538), .Q(
n11475) );
DFFSX1TS add_x_1_R_848 ( .D(EVEN1_Q_left[25]), .CK(clk), .SN(n11538), .Q(
n11474) );
DFFRXLTS add_x_1_R_787 ( .D(EVEN1_Q_left[28]), .CK(clk), .RN(n11540), .Q(
n11473) );
DFFRXLTS add_x_1_R_773_RW_0 ( .D(EVEN1_Q_left[25]), .CK(clk), .RN(n11540),
.Q(n11472) );
DFFRXLTS add_x_1_R_770_RW_0 ( .D(EVEN1_Q_left[24]), .CK(clk), .RN(n11540),
.Q(n11471) );
DFFRXLTS add_x_1_R_746_RW_0 ( .D(EVEN1_Q_left[27]), .CK(clk), .RN(n11540),
.Q(n11470) );
DFFRXLTS add_x_1_R_730_RW_0 ( .D(EVEN1_Q_left[26]), .CK(clk), .RN(n11540),
.Q(n11469) );
DFFSX1TS add_x_1_R_98 ( .D(add_x_1_n322), .CK(clk), .SN(n11719), .Q(n11468)
);
DFFSX1TS add_x_3_R_6631 ( .D(add_x_3_n185), .CK(clk), .SN(n11447), .Q(n11440), .QN(n11466) );
DFFSX1TS add_x_3_R_6168 ( .D(add_x_3_n157), .CK(clk), .SN(n11450), .Q(n11416) );
DFFRXLTS add_x_3_R_5734_RW_1 ( .D(add_x_3_n144), .CK(clk), .RN(n11447), .QN(
n11467) );
DFFRXLTS add_x_3_R_6637 ( .D(add_x_3_n68), .CK(clk), .RN(n11447), .Q(n11446)
);
DFFSX1TS add_x_3_R_6636 ( .D(add_x_3_n79), .CK(clk), .SN(n11450), .Q(n11445)
);
DFFSX1TS add_x_3_R_6635 ( .D(add_x_3_n143), .CK(clk), .SN(n11447), .Q(n11444), .QN(n11455) );
DFFSX1TS add_x_3_R_6634 ( .D(add_x_3_n131), .CK(clk), .SN(n11447), .Q(n11443) );
DFFSX1TS add_x_3_R_6630 ( .D(add_x_3_n5), .CK(clk), .SN(n11448), .Q(n11439)
);
DFFRXLTS add_x_3_R_6621 ( .D(add_x_3_n181), .CK(clk), .RN(n11447), .Q(n11438) );
DFFSX1TS add_x_3_R_6620 ( .D(add_x_3_n307), .CK(clk), .SN(n11448), .Q(n11437) );
DFFRXLTS add_x_3_R_6619 ( .D(add_x_3_n172), .CK(clk), .RN(n11447), .Q(n11436) );
DFFSX1TS add_x_3_R_6618 ( .D(add_x_3_n171), .CK(clk), .SN(n11448), .Q(n11435) );
DFFSX1TS add_x_3_R_5955 ( .D(add_x_3_n197), .CK(clk), .SN(n11451), .Q(n11404) );
DFFRXLTS add_x_3_R_6052_RW_1 ( .D(add_x_3_n16), .CK(clk), .RN(n325), .Q(
n11408) );
DFFRXLTS add_x_3_R_6340_RW_0 ( .D(add_x_3_n97), .CK(clk), .RN(n11452), .Q(
n11425), .QN(n11434) );
DFFRXLTS add_x_3_R_6339_RW_0 ( .D(add_x_3_n50), .CK(clk), .RN(n11452), .Q(
n11424) );
DFFSX1TS add_x_3_R_6051 ( .D(add_x_3_n190), .CK(clk), .SN(n11451), .QN(
n11433) );
DFFSX1TS add_x_3_R_5133_RW_1 ( .D(add_x_3_n9), .CK(clk), .SN(n11451), .QN(
n11457) );
DFFRXLTS add_x_3_R_6540 ( .D(add_x_3_n4), .CK(clk), .RN(n328), .Q(n11428) );
DFFRXLTS add_x_3_R_5535_RW_0 ( .D(add_x_3_n11), .CK(clk), .RN(n278), .Q(
n11399) );
DFFRXLTS add_x_3_R_5956_RW_0 ( .D(add_x_3_n17), .CK(clk), .RN(n326), .Q(
n11405) );
DFFRXLTS add_x_3_R_6342_RW_0 ( .D(add_x_3_n122), .CK(clk), .RN(n11452), .Q(
n11426) );
DFFRXLTS add_x_3_R_6226_RW_0 ( .D(add_x_3_n5), .CK(clk), .RN(n277), .Q(
n11423), .QN(n11464) );
DFFSX1TS add_x_3_R_4975_RW_2 ( .D(add_x_3_n13), .CK(clk), .SN(n11448), .QN(
n11461) );
DFFRXLTS add_x_3_R_4766_RW_2 ( .D(add_x_3_n10), .CK(clk), .RN(n11452), .Q(
n11398) );
DFFSX1TS add_x_3_R_3994_RW_5 ( .D(add_x_3_n6), .CK(clk), .SN(n11448), .QN(
n11456) );
DFFSX1TS add_x_3_R_5738_RW_2 ( .D(add_x_3_n153), .CK(clk), .SN(n11449), .Q(
n11402) );
DFFSX1TS add_x_3_R_6138_RW_0 ( .D(add_x_3_n164), .CK(clk), .SN(n11449), .Q(
n11412) );
DFFSX1TS add_x_3_R_5665_RW_0 ( .D(add_x_3_n125), .CK(clk), .SN(n11449), .Q(
n11400) );
DFFSX1TS add_x_3_R_6202 ( .D(add_x_3_n178), .CK(clk), .SN(n11449), .Q(n11421) );
DFFSX1TS add_x_3_R_6201 ( .D(add_x_3_n306), .CK(clk), .SN(n11449), .Q(n11420) );
DFFSX1TS add_x_3_R_6186 ( .D(add_x_3_n144), .CK(clk), .SN(n11451), .Q(n11418) );
DFFSX1TS add_x_3_R_6187 ( .D(add_x_3_n132), .CK(clk), .SN(n11452), .Q(n11419) );
DFFRXLTS add_x_3_R_4493_RW_3 ( .D(add_x_3_n7), .CK(clk), .RN(n11447), .QN(
n11458) );
DFFSX1TS add_x_3_R_6169 ( .D(add_x_3_n158), .CK(clk), .SN(n11450), .Q(n11417) );
DFFSX1TS add_x_3_R_6142 ( .D(add_x_3_n169), .CK(clk), .SN(n11450), .Q(n11415) );
DFFSX1TS add_x_3_R_6141 ( .D(add_x_3_n166), .CK(clk), .SN(n11450), .Q(n11414) );
DFFSX1TS add_x_3_R_6140 ( .D(add_x_3_n174), .CK(clk), .SN(n11450), .Q(n11413) );
DFFSX1TS add_x_3_R_6067 ( .D(add_x_3_n141), .CK(clk), .SN(n11450), .Q(n11411) );
DFFSX1TS add_x_3_R_6066 ( .D(add_x_3_n138), .CK(clk), .SN(n11450), .Q(n11410) );
DFFSX1TS add_x_3_R_6065 ( .D(add_x_3_n146), .CK(clk), .SN(n11450), .Q(n11409) );
DFFSX1TS add_x_3_R_5735 ( .D(add_x_3_n136), .CK(clk), .SN(n11452), .QN(
n11406) );
DFFSX1TS add_x_3_R_4855_RW_1 ( .D(add_x_3_n8), .CK(clk), .SN(n11451), .QN(
n11460) );
DFFSX1TS add_x_3_R_5770 ( .D(add_x_3_n15), .CK(clk), .SN(n11451), .Q(n11403)
);
DFFSX1TS add_x_3_R_5737 ( .D(add_x_3_n303), .CK(clk), .SN(n11452), .Q(n11407) );
DFFSX1TS add_x_3_R_5716_RW_0 ( .D(add_x_3_n12), .CK(clk), .SN(n11451), .Q(
n11401) );
DFFRXLTS DP_OP_62J6_125_4796_R_6224_RW_0 ( .D(DP_OP_62J6_125_4796_n555),
.CK(clk), .RN(n11384), .Q(n11363) );
DFFSX1TS DP_OP_62J6_125_4796_R_6538 ( .D(DP_OP_62J6_125_4796_n559), .CK(clk),
.SN(n11382), .Q(n11370) );
DFFSX1TS DP_OP_62J6_125_4796_R_6223 ( .D(DP_OP_62J6_125_4796_n558), .CK(clk),
.SN(n11377), .Q(n11362) );
DFFSX1TS DP_OP_62J6_125_4796_R_6537 ( .D(DP_OP_62J6_125_4796_n562), .CK(clk),
.SN(n11382), .Q(n11369) );
DFFSX1TS DP_OP_62J6_125_4796_R_6232_RW_1 ( .D(DP_OP_62J6_125_4796_n286),
.CK(clk), .SN(n11382), .QN(n11391) );
DFFSX1TS DP_OP_62J6_125_4796_R_6646 ( .D(DP_OP_62J6_125_4796_n282), .CK(clk),
.SN(n11378), .Q(n11376) );
DFFSX1TS DP_OP_62J6_125_4796_R_6644 ( .D(DP_OP_62J6_125_4796_n283), .CK(clk),
.SN(n11379), .Q(n11374), .QN(n11375) );
DFFSX1TS DP_OP_62J6_125_4796_R_6643 ( .D(DP_OP_62J6_125_4796_n280), .CK(clk),
.SN(n11379), .Q(n11373) );
DFFSX1TS DP_OP_62J6_125_4796_R_6369_RW_1 ( .D(DP_OP_62J6_125_4796_n297),
.CK(clk), .SN(n11382), .Q(n11368), .QN(n11385) );
DFFSX1TS DP_OP_62J6_125_4796_R_6233_RW_1 ( .D(DP_OP_62J6_125_4796_n298),
.CK(clk), .SN(n11379), .QN(n11387) );
DFFSX1TS DP_OP_62J6_125_4796_R_6110_RW_1 ( .D(DP_OP_62J6_125_4796_n551),
.CK(clk), .SN(n11382), .Q(n11352) );
DFFRXLTS DP_OP_62J6_125_4796_R_6212_RW_1 ( .D(n7384), .CK(clk), .RN(n11378),
.Q(n11358) );
DFFSX1TS DP_OP_62J6_125_4796_R_6215_RW_1 ( .D(n11307), .CK(clk), .SN(n11379),
.Q(n11359) );
DFFSX1TS DP_OP_62J6_125_4796_R_6228_RW_0 ( .D(n11389), .CK(clk), .SN(n11383),
.QN(n11372) );
DFFSX1TS DP_OP_62J6_125_4796_R_6240_RW_1 ( .D(DP_OP_62J6_125_4796_n409),
.CK(clk), .SN(n11383), .QN(n11386) );
DFFSX1TS DP_OP_62J6_125_4796_R_6236_RW_1 ( .D(EVEN1_Q_left[31]), .CK(clk),
.SN(n11383), .QN(n11388) );
DFFSX1TS DP_OP_62J6_125_4796_R_5671 ( .D(DP_OP_62J6_125_4796_n550), .CK(clk),
.SN(n11380), .Q(n11342) );
DFFRXLTS DP_OP_62J6_125_4796_R_6225_RW_1 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_S_B[9]), .CK(clk), .RN(n11384), .Q(n11364) );
DFFRXLTS DP_OP_62J6_125_4796_R_5696_RW_0 ( .D(DP_OP_62J6_125_4796_n40), .CK(
clk), .RN(n11384), .Q(n11345) );
DFFSX1TS DP_OP_62J6_125_4796_R_5672_RW_1 ( .D(DP_OP_62J6_125_4796_n547),
.CK(clk), .SN(n11381), .Q(n11343) );
DFFSX1TS DP_OP_62J6_125_4796_R_5673_RW_0 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_S_B[11]), .CK(clk), .SN(n11381), .Q(
n11344) );
DFFRXLTS DP_OP_62J6_125_4796_R_6539 ( .D(EVEN1_middle_RECURSIVE_EVEN1_S_B[8]), .CK(clk), .RN(n11378), .Q(n11371) );
DFFRXLTS DP_OP_62J6_125_4796_R_6207_RW_0 ( .D(DP_OP_62J6_125_4796_n564),
.CK(clk), .RN(n11384), .Q(n11355) );
DFFSX1TS DP_OP_62J6_125_4796_R_6211_RW_0 ( .D(DP_OP_62J6_125_4796_n697),
.CK(clk), .SN(n11383), .Q(n11357) );
DFFSX1TS DP_OP_62J6_125_4796_R_4970_RW_5 ( .D(DP_OP_62J6_125_4796_n538),
.CK(clk), .SN(n11383), .Q(n11332) );
DFFSX1TS DP_OP_62J6_125_4796_R_6229_RW_0 ( .D(DP_OP_62J6_125_4796_n294),
.CK(clk), .SN(n11383), .Q(n11365) );
DFFSX1TS DP_OP_62J6_125_4796_R_6234_RW_0 ( .D(DP_OP_62J6_125_4796_n287),
.CK(clk), .SN(n11383), .Q(n11366) );
DFFRXLTS DP_OP_62J6_125_4796_R_6206_RW_0 ( .D(DP_OP_62J6_125_4796_n561),
.CK(clk), .RN(n11378), .Q(n11354) );
DFFSX1TS DP_OP_62J6_125_4796_R_5446_RW_1 ( .D(DP_OP_62J6_125_4796_n542),
.CK(clk), .SN(n11382), .Q(n11334) );
DFFRXLTS DP_OP_62J6_125_4796_R_6069_RW_0 ( .D(DP_OP_62J6_125_4796_n560),
.CK(clk), .RN(n11378), .Q(n11350) );
DFFRXLTS DP_OP_62J6_125_4796_R_5447_RW_0 ( .D(DP_OP_62J6_125_4796_n539),
.CK(clk), .RN(n11378), .Q(n11335) );
DFFSX1TS DP_OP_62J6_125_4796_R_5495_RW_0 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_S_B[12]), .CK(clk), .SN(n11383), .Q(
n11338) );
DFFSX1TS DP_OP_62J6_125_4796_R_6111 ( .D(n11309), .CK(clk), .SN(n11381), .Q(
n11353) );
DFFSX1TS DP_OP_62J6_125_4796_R_6093 ( .D(DP_OP_62J6_125_4796_n560), .CK(clk),
.SN(n11381), .Q(n11351) );
DFFSX1TS DP_OP_62J6_125_4796_R_5558_RW_2 ( .D(DP_OP_62J6_125_4796_n640),
.CK(clk), .SN(n11382), .Q(n11340) );
DFFSX1TS DP_OP_62J6_125_4796_R_5947_RW_0 ( .D(DP_OP_62J6_125_4796_n641),
.CK(clk), .SN(n11382), .Q(n11349) );
DFFSX1TS DP_OP_62J6_125_4796_R_5493_RW_1 ( .D(DP_OP_62J6_125_4796_n546),
.CK(clk), .SN(n11381), .Q(n11336) );
DFFSX1TS DP_OP_62J6_125_4796_R_6216 ( .D(n11308), .CK(clk), .SN(n11383), .Q(
n11360) );
DFFSX1TS DP_OP_62J6_125_4796_R_6217 ( .D(n11306), .CK(clk), .SN(n11382), .Q(
n11361) );
DFFSX1TS DP_OP_62J6_125_4796_R_6096 ( .D(EVEN1_Q_left[32]), .CK(clk), .SN(
n11380), .QN(n11390) );
DFFRXLTS DP_OP_62J6_125_4796_R_5494 ( .D(DP_OP_62J6_125_4796_n543), .CK(clk),
.RN(n11384), .Q(n11337) );
DFFRXLTS DP_OP_62J6_125_4796_R_5791 ( .D(DP_OP_62J6_125_4796_n642), .CK(clk),
.RN(n11377), .Q(n11347) );
DFFSX1TS DP_OP_62J6_125_4796_R_5662_RW_0 ( .D(DP_OP_62J6_125_4796_n39), .CK(
clk), .SN(n11379), .Q(n11341) );
DFFSX1TS DP_OP_59J6_122_190_R_6652 ( .D(DP_OP_59J6_122_190_n212), .CK(clk),
.SN(n11282), .Q(n11279), .QN(n11297) );
DFFSX1TS DP_OP_59J6_122_190_R_6648 ( .D(DP_OP_59J6_122_190_n122), .CK(clk),
.SN(n11282), .Q(n11275), .QN(n11287) );
DFFSX1TS DP_OP_59J6_122_190_R_4267_RW_4 ( .D(DP_OP_59J6_122_190_n58), .CK(
clk), .SN(n11283), .QN(n11293) );
DFFSX1TS DP_OP_59J6_122_190_R_2806_RW_11 ( .D(DP_OP_59J6_122_190_n53), .CK(
clk), .SN(n11283), .QN(n11291) );
DFFSX1TS DP_OP_59J6_122_190_R_5307_RW_3 ( .D(DP_OP_59J6_122_190_n123), .CK(
clk), .SN(n595), .QN(n11304) );
DFFSX1TS DP_OP_59J6_122_190_R_3176_RW_3 ( .D(DP_OP_59J6_122_190_n54), .CK(
clk), .SN(n11283), .QN(n11289) );
DFFSX1TS DP_OP_59J6_122_190_R_5553_RW_2 ( .D(DP_OP_59J6_122_190_n110), .CK(
clk), .SN(n455), .QN(n11286) );
DFFRXLTS DP_OP_59J6_122_190_R_6383 ( .D(DP_OP_59J6_122_190_n109), .CK(clk),
.RN(n11284), .Q(n11266), .QN(n11303) );
DFFSX1TS DP_OP_59J6_122_190_R_3346_RW_7 ( .D(DP_OP_59J6_122_190_n57), .CK(
clk), .SN(n11283), .QN(n11294) );
DFFRXLTS DP_OP_59J6_122_190_R_3167_RW_10 ( .D(DP_OP_59J6_122_190_n52), .CK(
clk), .RN(n11284), .QN(n11288) );
DFFSX1TS DP_OP_59J6_122_190_R_6654 ( .D(n11300), .CK(clk), .SN(n11283), .Q(
n11281) );
DFFSX1TS DP_OP_59J6_122_190_R_6653 ( .D(DP_OP_59J6_122_190_n200), .CK(clk),
.SN(n11282), .Q(n11280), .QN(n11305) );
DFFSX1TS DP_OP_59J6_122_190_R_6651 ( .D(DP_OP_59J6_122_190_n160), .CK(clk),
.SN(n11282), .Q(n11278), .QN(n11296) );
DFFSX1TS DP_OP_59J6_122_190_R_6650 ( .D(DP_OP_59J6_122_190_n192), .CK(clk),
.SN(n11282), .Q(n11277) );
DFFSX1TS DP_OP_59J6_122_190_R_6649 ( .D(DP_OP_59J6_122_190_n183), .CK(clk),
.SN(n11282), .Q(n11276) );
DFFSX1TS DP_OP_59J6_122_190_R_6622 ( .D(DP_OP_59J6_122_190_n182), .CK(clk),
.SN(n11282), .Q(n11274) );
DFFSX1TS DP_OP_59J6_122_190_R_6613 ( .D(DP_OP_59J6_122_190_n232), .CK(clk),
.SN(n11282), .Q(n11272) );
DFFSX1TS DP_OP_59J6_122_190_R_6614 ( .D(DP_OP_59J6_122_190_n65), .CK(clk),
.SN(n11628), .Q(n11273) );
DFFRXLTS DP_OP_59J6_122_190_R_6162_RW_0 ( .D(DP_OP_59J6_122_190_n308), .CK(
clk), .RN(n11284), .Q(n11255) );
DFFRXLTS DP_OP_59J6_122_190_R_6191_RW_0 ( .D(DP_OP_59J6_122_190_n223), .CK(
clk), .RN(n11284), .Q(n11260) );
DFFSX1TS DP_OP_59J6_122_190_R_6165 ( .D(DP_OP_59J6_122_190_n210), .CK(clk),
.SN(n11283), .Q(n11257) );
DFFSX1TS DP_OP_59J6_122_190_R_6144 ( .D(DP_OP_59J6_122_190_n176), .CK(clk),
.SN(n9551), .Q(n11253) );
DFFSX1TS DP_OP_59J6_122_190_R_6143 ( .D(DP_OP_59J6_122_190_n166), .CK(clk),
.SN(n9551), .Q(n11252) );
DFFSX1TS DP_OP_59J6_122_190_R_6389_RW_0 ( .D(DP_OP_59J6_122_190_n209), .CK(
clk), .SN(n11282), .QN(n11298) );
DFFSX1TS DP_OP_59J6_122_190_R_6190 ( .D(DP_OP_59J6_122_190_n222), .CK(clk),
.SN(n11610), .Q(n11259) );
DFFRXLTS DP_OP_59J6_122_190_R_6384_RW_0 ( .D(DP_OP_59J6_122_190_n224), .CK(
clk), .RN(n11284), .Q(n11267) );
DFFSX1TS DP_OP_59J6_122_190_R_6163 ( .D(DP_OP_59J6_122_190_n201), .CK(clk),
.SN(n11283), .Q(n11256) );
DFFSX1TS DP_OP_59J6_122_190_R_5750_RW_2 ( .D(DP_OP_59J6_122_190_n63), .CK(
clk), .SN(n11377), .Q(n11243) );
DFFSX1TS DP_OP_59J6_122_190_R_6145_RW_2 ( .D(DP_OP_59J6_122_190_n167), .CK(
clk), .SN(n11283), .Q(n11254) );
DFFRXLTS DP_OP_59J6_122_190_R_5620_RW_0 ( .D(DP_OP_59J6_122_190_n187), .CK(
clk), .RN(n11284), .QN(n11301) );
DFFRXLTS DP_OP_59J6_122_190_R_5801_RW_0 ( .D(DP_OP_59J6_122_190_n180), .CK(
clk), .RN(n11284), .Q(n11245) );
DFFRXLTS DP_OP_59J6_122_190_R_6382_RW_0 ( .D(DP_OP_59J6_122_190_n158), .CK(
clk), .RN(n11284), .Q(n11265) );
DFFRXLTS DP_OP_59J6_122_190_R_6380_RW_0 ( .D(DP_OP_59J6_122_190_n135), .CK(
clk), .RN(n11284), .Q(n11263), .QN(n11295) );
DFFSX1TS DP_OP_59J6_122_190_R_6378 ( .D(DP_OP_59J6_122_190_n111), .CK(clk),
.SN(n11724), .Q(n11261) );
DFFSX1TS DP_OP_59J6_122_190_R_6381 ( .D(DP_OP_59J6_122_190_n153), .CK(clk),
.SN(n11382), .Q(n11264) );
DFFSX1TS DP_OP_59J6_122_190_R_6390 ( .D(DP_OP_59J6_122_190_n180), .CK(clk),
.SN(n11283), .Q(n11270) );
DFFSX1TS DP_OP_59J6_122_190_R_6387 ( .D(DP_OP_59J6_122_190_n146), .CK(clk),
.SN(n278), .Q(n11269) );
DFFSX1TS DP_OP_59J6_122_190_R_6385 ( .D(n11299), .CK(clk), .SN(n11628), .Q(
n11268) );
DFFSX1TS DP_OP_59J6_122_190_R_6379 ( .D(DP_OP_59J6_122_190_n112), .CK(clk),
.SN(n277), .Q(n11262) );
DFFSX1TS DP_OP_59J6_122_190_R_3344_RW_13 ( .D(DP_OP_59J6_122_190_n55), .CK(
clk), .SN(n11722), .QN(n11292) );
DFFSX1TS DP_OP_59J6_122_190_R_6127 ( .D(DP_OP_59J6_122_190_n303), .CK(clk),
.SN(n11381), .Q(n11251) );
DFFSX1TS DP_OP_59J6_122_190_R_6123 ( .D(DP_OP_59J6_122_190_n64), .CK(clk),
.SN(n11721), .Q(n11250) );
DFFSX1TS DP_OP_59J6_122_190_R_6114 ( .D(DP_OP_59J6_122_190_n306), .CK(clk),
.SN(n594), .Q(n11249) );
DFFSX1TS DP_OP_59J6_122_190_R_6078_RW_0 ( .D(DP_OP_59J6_122_190_n204), .CK(
clk), .SN(n11720), .Q(n11248) );
DFFSX1TS DP_OP_59J6_122_190_R_6077_RW_0 ( .D(DP_OP_59J6_122_190_n309), .CK(
clk), .SN(n11720), .Q(n11247) );
DFFSX1TS DP_OP_59J6_122_190_R_6060 ( .D(DP_OP_59J6_122_190_n103), .CK(clk),
.SN(n11785), .Q(n11246) );
DFFSX1TS DP_OP_59J6_122_190_R_2809_RW_1 ( .D(DP_OP_59J6_122_190_n51), .CK(
clk), .SN(n455), .QN(n11290) );
DFFSX1TS DP_OP_59J6_122_190_R_2762_RW_3 ( .D(DP_OP_59J6_122_190_n50), .CK(
clk), .SN(n455), .Q(n11237) );
DFFSX1TS DP_OP_59J6_122_190_R_5797 ( .D(n132), .CK(clk), .SN(n11283), .Q(
n11244) );
DFFSX1TS DP_OP_59J6_122_190_R_5714 ( .D(DP_OP_59J6_122_190_n62), .CK(clk),
.SN(n11719), .Q(n11242) );
DFFSX1TS DP_OP_59J6_122_190_R_5653 ( .D(DP_OP_59J6_122_190_n147), .CK(clk),
.SN(n9551), .Q(n11240) );
DFFSX1TS DP_OP_59J6_122_190_R_5600_RW_0 ( .D(DP_OP_59J6_122_190_n136), .CK(
clk), .SN(n11282), .QN(n11241) );
DFFSX1TS DP_OP_59J6_122_190_R_5565_RW_0 ( .D(DP_OP_59J6_122_190_n60), .CK(
clk), .SN(n455), .Q(n11239) );
DFFSX1TS DP_OP_59J6_122_190_R_4498_RW_1 ( .D(DP_OP_59J6_122_190_n305), .CK(
clk), .SN(n11610), .QN(n11285) );
DFFSX1TS DP_OP_59J6_122_190_R_4499_RW_3 ( .D(DP_OP_59J6_122_190_n170), .CK(
clk), .SN(n11610), .QN(n11302) );
DFFRXLTS R_6333 ( .D(n11730), .CK(clk), .RN(n325), .Q(n11634) );
DFFRXLTS DP_OP_62J6_125_4796_R_2877_RW_8 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[17]), .CK(clk), .RN(n11378), .Q(
n11328) );
DFFRHQX1TS EVEN1_finalreg_Q_reg_21_ ( .D(n89), .CK(clk), .RN(n11785), .Q(
sgf_result_o[21]) );
DFFRXLTS DP_OP_62J6_125_4796_R_2395_RW_9 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[18]), .CK(clk), .RN(n11378), .Q(
n11318) );
DFFRXLTS DP_OP_62J6_125_4796_R_2713_RW_16 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[20]), .CK(clk), .RN(n11384), .Q(
n11324) );
DFFRXLTS DP_OP_62J6_125_4796_R_1941_RW_6 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[26]), .CK(clk), .RN(n11384), .Q(
n11310) );
DFFSX1TS DP_OP_62J6_125_4796_R_2508_RW_9 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[21]), .CK(clk), .SN(n11380), .Q(
n11321) );
DFFSX1TS DP_OP_62J6_125_4796_R_2182_RW_0 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[19]), .CK(clk), .SN(n595), .Q(
n11314) );
DFFSX1TS DP_OP_62J6_125_4796_R_2421_RW_7 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[22]), .CK(clk), .SN(n11380), .Q(
n11320) );
DFFSX1TS DP_OP_62J6_125_4796_R_2403_RW_15 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[23]), .CK(clk), .SN(n11380), .Q(
n11319) );
DFFSX1TS DP_OP_62J6_125_4796_R_2307_RW_9 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[25]), .CK(clk), .SN(n11379), .Q(
n11315) );
DFFSX1TS DP_OP_62J6_125_4796_R_2051_RW_13 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[24]), .CK(clk), .SN(n11379), .Q(
n11312) );
DFFSX1TS DP_OP_62J6_125_4796_R_6368 ( .D(n1710), .CK(clk), .SN(n11380), .Q(
n11367) );
DFFSX1TS DP_OP_59J6_122_190_R_3169_RW_5 ( .D(DP_OP_59J6_122_190_n49), .CK(
clk), .SN(n11628), .Q(n11238) );
DFFSX1TS add_x_1_R_6376 ( .D(EVEN1_S_B[12]), .CK(clk), .SN(n11536), .Q(
n11525) );
DFFSX1TS R_89 ( .D(n11756), .CK(clk), .SN(n11720), .Q(n11690) );
DFFSX1TS R_705 ( .D(n11747), .CK(clk), .SN(n327), .Q(n11675) );
DFFSX1TS R_1146 ( .D(n11742), .CK(clk), .SN(n266), .Q(n11660) );
DFFSX1TS R_2146 ( .D(n11734), .CK(clk), .SN(n11629), .Q(n11645) );
DFFSX1TS R_6629 ( .D(n11731), .CK(clk), .SN(n325), .Q(n11630) );
DFFSX1TS add_x_2_R_6639 ( .D(add_x_2_n61), .CK(clk), .SN(n11612), .Q(n11609)
);
DFFSX1TS add_x_2_R_6355 ( .D(add_x_2_n81), .CK(clk), .SN(n11785), .Q(n11600)
);
DFFSX1TS add_x_2_R_2589_RW_1 ( .D(n1725), .CK(clk), .SN(n11612), .Q(n11562)
);
DFFSX1TS add_x_1_R_6107 ( .D(add_x_1_n737), .CK(clk), .SN(n11536), .QN(
n11559) );
DFFSX1TS add_x_1_R_6641 ( .D(EVEN1_Q_left[12]), .CK(clk), .SN(n11535), .Q(
n11531) );
DFFSX1TS add_x_1_R_6377 ( .D(EVEN1_S_B[8]), .CK(clk), .SN(n11536), .Q(n11526) );
DFFSX1TS add_x_1_R_4272_RW_1 ( .D(EVEN1_S_B[9]), .CK(clk), .SN(n11538), .Q(
n11495) );
DFFRXLTS add_x_1_R_897 ( .D(EVEN1_Q_left[20]), .CK(clk), .RN(n454), .Q(
n11480) );
DFFSX1TS add_x_3_R_4265_RW_1 ( .D(n1715), .CK(clk), .SN(n11449), .QN(n11453)
);
DFFSX1TS add_x_3_R_6632 ( .D(add_x_3_n61), .CK(clk), .SN(n11447), .Q(n11441)
);
DFFSX1TS add_x_3_R_6527 ( .D(add_x_3_n70), .CK(clk), .SN(n11448), .Q(n11427)
);
DFFSX1TS add_x_3_R_6214_RW_0 ( .D(EVEN1_right_RECURSIVE_ODD1_Q_left_17_),
.CK(clk), .SN(n11449), .Q(n11422) );
DFFSX1TS add_x_3_R_4261_RW_5 ( .D(add_x_3_n64), .CK(clk), .SN(n11451), .Q(
n11397) );
DFFSX1TS DP_OP_62J6_125_4796_R_2798_RW_17 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[8]), .CK(clk), .SN(n11380), .Q(
n11327) );
DFFRXLTS DP_OP_62J6_125_4796_R_2033_RW_8 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[12]), .CK(clk), .RN(n11384), .Q(
n11311) );
DFFSX1TS DP_OP_62J6_125_4796_R_2314_RW_7 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[13]), .CK(clk), .SN(n11381), .Q(
n11316) );
DFFSX1TS add_x_2_R_3339_RW_1 ( .D(add_x_2_n93), .CK(clk), .SN(n11611), .Q(
n11568) );
DFFRXLTS add_x_1_R_1038 ( .D(EVEN1_Q_left[18]), .CK(clk), .RN(n11724), .Q(
n11490) );
DFFRXLTS add_x_1_R_962 ( .D(EVEN1_Q_left[19]), .CK(clk), .RN(n277), .Q(
n11482) );
DFFSX1TS R_161 ( .D(n11753), .CK(clk), .SN(n11628), .Q(n11686) );
DFFSX1TS R_164 ( .D(n11752), .CK(clk), .SN(n11628), .Q(n11685) );
DFFSX1TS R_158 ( .D(n11754), .CK(clk), .SN(n11629), .Q(n11687) );
DFFSX1TS add_x_1_R_6332 ( .D(EVEN1_Q_left[15]), .CK(clk), .SN(n11628), .Q(
n11506) );
DFFSX1TS R_80 ( .D(n11755), .CK(clk), .SN(n11629), .Q(n11693) );
DFFSX1TS add_x_1_R_1018_RW_0 ( .D(EVEN1_Q_left[18]), .CK(clk), .SN(n11628),
.Q(n11488) );
DFFSX1TS add_x_1_R_1016 ( .D(EVEN1_Q_left[19]), .CK(clk), .SN(n11722), .Q(
n11487) );
DFFSX1TS R_351 ( .D(n11751), .CK(clk), .SN(n266), .Q(n11680) );
DFFSX1TS R_2 ( .D(n11759), .CK(clk), .SN(n11719), .Q(n11718) );
DFFSX1TS R_5 ( .D(n11777), .CK(clk), .SN(n11785), .Q(n11717) );
DFFSX1TS R_8 ( .D(n11774), .CK(clk), .SN(n277), .Q(n11716) );
DFFSX1TS R_11 ( .D(n11773), .CK(clk), .SN(n326), .Q(n11715) );
DFFSX1TS R_14 ( .D(n11772), .CK(clk), .SN(n325), .Q(n11714) );
DFFSX1TS R_17 ( .D(n11771), .CK(clk), .SN(n325), .Q(n11713) );
DFFSX1TS R_20 ( .D(n11769), .CK(clk), .SN(n326), .Q(n11712) );
DFFSX1TS R_23 ( .D(n11766), .CK(clk), .SN(n278), .Q(n11711) );
DFFSX1TS R_26 ( .D(n11765), .CK(clk), .SN(n277), .Q(n11710) );
DFFSX1TS R_32 ( .D(n11761), .CK(clk), .SN(n325), .Q(n11709) );
DFFSX1TS R_35 ( .D(n11760), .CK(clk), .SN(n11724), .Q(n11708) );
DFFSX1TS R_38 ( .D(n11776), .CK(clk), .SN(n594), .Q(n11707) );
DFFSX1TS R_41 ( .D(n11775), .CK(clk), .SN(n455), .Q(n11706) );
DFFSX1TS R_44 ( .D(n11763), .CK(clk), .SN(n11721), .Q(n11705) );
DFFSX1TS R_47 ( .D(n11783), .CK(clk), .SN(n594), .Q(n11704) );
DFFSX1TS R_50 ( .D(n11782), .CK(clk), .SN(n326), .Q(n11703) );
DFFSX1TS R_53 ( .D(n11784), .CK(clk), .SN(n595), .Q(n11702) );
DFFSX1TS R_56 ( .D(n11781), .CK(clk), .SN(n278), .Q(n11701) );
DFFSX1TS R_59 ( .D(n11778), .CK(clk), .SN(n325), .Q(n11700) );
DFFSX1TS R_62 ( .D(n11767), .CK(clk), .SN(n278), .Q(n11699) );
DFFSX1TS R_65 ( .D(n11762), .CK(clk), .SN(n11723), .Q(n11698) );
DFFSX1TS R_68 ( .D(n11768), .CK(clk), .SN(n277), .Q(n11697) );
DFFSX1TS R_71 ( .D(n11764), .CK(clk), .SN(n11723), .Q(n11696) );
DFFSX1TS R_74 ( .D(n11757), .CK(clk), .SN(n11719), .Q(n11695) );
DFFSX1TS R_77 ( .D(n11758), .CK(clk), .SN(n11721), .Q(n11694) );
DFFSX1TS R_83 ( .D(n11770), .CK(clk), .SN(n278), .Q(n11692) );
DFFSX1TS R_86 ( .D(n11779), .CK(clk), .SN(n11785), .Q(n11691) );
DFFSX1TS R_92 ( .D(n11780), .CK(clk), .SN(n325), .Q(n11689) );
DFFSX1TS R_392 ( .D(n11750), .CK(clk), .SN(n327), .Q(n11679) );
DFFSX1TS R_692 ( .D(n11749), .CK(clk), .SN(n327), .Q(n11676) );
DFFSX1TS R_708 ( .D(n11748), .CK(clk), .SN(n328), .Q(n11674) );
DFFSX1TS R_932 ( .D(n11746), .CK(clk), .SN(n327), .Q(n11670) );
DFFSX1TS R_935 ( .D(n11745), .CK(clk), .SN(n266), .Q(n11669) );
DFFSX1TS R_947 ( .D(n11744), .CK(clk), .SN(n267), .Q(n11668) );
DFFSX1TS R_950 ( .D(n11743), .CK(clk), .SN(n266), .Q(n11667) );
DFFSX1TS R_1179 ( .D(n11740), .CK(clk), .SN(n11719), .Q(n11659) );
DFFSX1TS R_1182 ( .D(n11739), .CK(clk), .SN(n11785), .Q(n11658) );
DFFSX1TS R_1185 ( .D(n11741), .CK(clk), .SN(n11723), .Q(n11657) );
DFFSX1TS R_1437 ( .D(n11738), .CK(clk), .SN(n11628), .Q(n11652) );
DFFSX1TS R_1486 ( .D(n11736), .CK(clk), .SN(n11724), .Q(n11651) );
DFFSX1TS R_1489 ( .D(n11737), .CK(clk), .SN(n11721), .Q(n11650) );
DFFSX1TS R_2111 ( .D(n11735), .CK(clk), .SN(n11722), .Q(n11646) );
DFFSX1TS R_3636 ( .D(n11733), .CK(clk), .SN(n11723), .Q(n11643) );
DFFSX1TS R_6331 ( .D(n11728), .CK(clk), .SN(n267), .Q(n11635) );
DFFSX1TS R_6615 ( .D(n11725), .CK(clk), .SN(n11720), .Q(n11633) );
DFFSX1TS add_x_2_R_2965_RW_5 ( .D(n1721), .CK(clk), .SN(n11610), .Q(n11565)
);
DFFSX1TS add_x_2_R_3196_RW_5 ( .D(n1726), .CK(clk), .SN(n11611), .Q(n11567)
);
DFFSX1TS add_x_2_R_2766_RW_3 ( .D(add_x_2_n64), .CK(clk), .SN(n11611), .Q(
n11563) );
DFFSX1TS add_x_2_R_3022_RW_3 ( .D(add_x_2_n109), .CK(clk), .SN(n11611), .Q(
n11566) );
DFFSX1TS add_x_2_R_3530_RW_1 ( .D(n1722), .CK(clk), .SN(n11611), .Q(n11570)
);
DFFSX1TS add_x_2_R_3375_RW_1 ( .D(n1723), .CK(clk), .SN(n11611), .Q(n11569)
);
DFFSX1TS add_x_2_R_2771_RW_1 ( .D(add_x_2_n46), .CK(clk), .SN(n11611), .Q(
n11564) );
DFFSX1TS add_x_2_R_6359 ( .D(EVEN1_left_RECURSIVE_ODD1_Q_left_17_), .CK(clk),
.SN(n326), .Q(n11604) );
DFFSX1TS add_x_2_R_6357 ( .D(n1724), .CK(clk), .SN(n11611), .Q(n11602) );
DFFSX1TS add_x_2_R_6356 ( .D(add_x_2_n52), .CK(clk), .SN(n11611), .Q(n11601)
);
DFFSX1TS add_x_2_R_6352 ( .D(add_x_2_n88), .CK(clk), .SN(n267), .Q(n11598)
);
DFFSX1TS add_x_2_R_6345 ( .D(add_x_2_n99), .CK(clk), .SN(n328), .Q(n11595)
);
DFFSX1TS add_x_2_R_6344 ( .D(add_x_2_n70), .CK(clk), .SN(n277), .Q(n11594)
);
DFFSX1TS add_x_1_R_1831_RW_15 ( .D(EVEN1_Q_left[2]), .CK(clk), .SN(n11536),
.QN(n11548) );
DFFSX1TS add_x_1_R_1622_RW_8 ( .D(EVEN1_Q_left[3]), .CK(clk), .SN(n11536),
.QN(n11547) );
DFFSX1TS add_x_1_R_6360 ( .D(EVEN1_Q_left[5]), .CK(clk), .SN(n11537), .QN(
n11543) );
DFFSX1TS add_x_1_R_6647 ( .D(EVEN1_S_B[6]), .CK(clk), .SN(n11538), .Q(n11534) );
DFFSX1TS add_x_1_R_6645 ( .D(EVEN1_S_B[7]), .CK(clk), .SN(n11535), .Q(n11533) );
DFFSX1TS add_x_1_R_6642 ( .D(EVEN1_Q_left[9]), .CK(clk), .SN(n11535), .Q(
n11532) );
DFFSX1TS add_x_1_R_6365_RW_1 ( .D(EVEN1_Q_left[7]), .CK(clk), .SN(n11535),
.Q(n11519) );
DFFSX1TS add_x_1_R_5808_RW_3 ( .D(EVEN1_S_B[5]), .CK(clk), .SN(n11535), .Q(
n11500) );
DFFRXLTS add_x_1_R_5691_RW_2 ( .D(EVEN1_S_B[5]), .CK(clk), .RN(n11539), .Q(
n11498) );
DFFRXLTS add_x_1_R_5454_RW_3 ( .D(EVEN1_S_B[9]), .CK(clk), .RN(n11539), .Q(
n11496) );
DFFRXLTS add_x_1_R_6362_RW_0 ( .D(EVEN1_Q_left[6]), .CK(clk), .RN(n11540),
.Q(n11516) );
DFFRXLTS add_x_1_R_6361_RW_0 ( .D(EVEN1_Q_left[4]), .CK(clk), .RN(n11539),
.Q(n11515) );
DFFRXLTS add_x_1_R_1586_RW_7 ( .D(EVEN1_Q_left[3]), .CK(clk), .RN(n11540),
.Q(n11493) );
DFFRXLTS add_x_1_R_6364_RW_0 ( .D(EVEN1_Q_left[10]), .CK(clk), .RN(n11539),
.Q(n11518) );
DFFRXLTS add_x_1_R_6363_RW_0 ( .D(EVEN1_Q_left[8]), .CK(clk), .RN(n11539),
.Q(n11517) );
DFFSX1TS add_x_1_R_1140_RW_5 ( .D(EVEN1_Q_left[11]), .CK(clk), .SN(n11536),
.Q(n11492) );
DFFRXLTS add_x_1_R_1091_RW_2 ( .D(EVEN1_Q_left[11]), .CK(clk), .RN(n11539),
.Q(n11491) );
DFFRXLTS add_x_1_R_2092_RW_4 ( .D(EVEN1_Q_left[1]), .CK(clk), .RN(n11539),
.Q(n11494) );
DFFSX1TS add_x_1_R_6354 ( .D(EVEN1_Q_left[16]), .CK(clk), .SN(n454), .Q(
n11514) );
DFFSX1TS add_x_1_R_6351 ( .D(EVEN1_Q_left[14]), .CK(clk), .SN(n455), .Q(
n11513) );
DFFSX1TS add_x_1_R_6350 ( .D(EVEN1_Q_left[17]), .CK(clk), .SN(n455), .Q(
n11512) );
DFFSX1TS add_x_1_R_6349 ( .D(EVEN1_Q_left[21]), .CK(clk), .SN(n454), .Q(
n11510), .QN(n11511) );
DFFSX1TS add_x_1_R_6209 ( .D(EVEN1_S_B[4]), .CK(clk), .SN(n11537), .Q(n11502) );
DFFSX1TS add_x_1_R_1004_RW_0 ( .D(EVEN1_Q_left[13]), .CK(clk), .SN(n328),
.Q(n11486) );
DFFRXLTS add_x_1_R_970_RW_0 ( .D(EVEN1_Q_left[13]), .CK(clk), .RN(n327), .Q(
n11483) );
DFFSX1TS add_x_1_R_987 ( .D(EVEN1_Q_left[20]), .CK(clk), .SN(n454), .Q(
n11484) );
DFFRXLTS add_x_3_R_6341_RW_0 ( .D(add_x_3_n106), .CK(clk), .RN(n11452), .QN(
n11463) );
DFFSX1TS add_x_3_R_3812_RW_9 ( .D(add_x_3_n109), .CK(clk), .SN(n11449), .QN(
n11462) );
DFFSX1TS add_x_3_R_4122_RW_9 ( .D(n1717), .CK(clk), .SN(n11450), .QN(n11459)
);
DFFRXLTS add_x_3_R_6338_RW_0 ( .D(add_x_3_n41), .CK(clk), .RN(n11452), .QN(
n11454) );
DFFSX1TS add_x_3_R_6633 ( .D(add_x_3_n88), .CK(clk), .SN(n11447), .Q(n11442)
);
DFFRXLTS add_x_3_R_3576_RW_6 ( .D(n1718), .CK(clk), .RN(n11452), .Q(n11393)
);
DFFSX1TS add_x_3_R_6544 ( .D(add_x_3_n99), .CK(clk), .SN(n11448), .Q(n11432)
);
DFFSX1TS add_x_3_R_6543 ( .D(add_x_3_n81), .CK(clk), .SN(n11448), .Q(n11431)
);
DFFSX1TS add_x_3_R_6542 ( .D(add_x_3_n52), .CK(clk), .SN(n11448), .Q(n11430)
);
DFFSX1TS add_x_3_R_6541 ( .D(n11465), .CK(clk), .SN(n11448), .Q(n11429) );
DFFSX1TS add_x_3_R_3471_RW_13 ( .D(add_x_3_n93), .CK(clk), .SN(n11449), .Q(
n11392) );
DFFSX1TS add_x_3_R_3997_RW_9 ( .D(n1714), .CK(clk), .SN(n11449), .Q(n11395)
);
DFFSX1TS add_x_3_R_4187_RW_6 ( .D(add_x_3_n46), .CK(clk), .SN(n11451), .Q(
n11396) );
DFFSX1TS add_x_3_R_3991_RW_11 ( .D(n1716), .CK(clk), .SN(n11451), .Q(n11394)
);
DFFSX1TS DP_OP_62J6_125_4796_R_6210_RW_0 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[0]), .CK(clk), .SN(n11383), .Q(
n11356) );
DFFSX1TS DP_OP_62J6_125_4796_R_5945_RW_1 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[2]), .CK(clk), .SN(n11381), .Q(
n11348) );
DFFRXLTS DP_OP_62J6_125_4796_R_5040_RW_3 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[4]), .CK(clk), .RN(n11384), .Q(
n11333) );
DFFSX1TS DP_OP_62J6_125_4796_R_5557_RW_1 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[3]), .CK(clk), .SN(n11381), .Q(
n11339) );
DFFRXLTS DP_OP_62J6_125_4796_R_2521_RW_20 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[9]), .CK(clk), .RN(n11378), .Q(
n11323) );
DFFSX1TS DP_OP_62J6_125_4796_R_3808_RW_13 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[7]), .CK(clk), .SN(n11381), .Q(
n11331) );
DFFSX1TS DP_OP_62J6_125_4796_R_3701_RW_13 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[5]), .CK(clk), .SN(n11380), .Q(
n11330) );
DFFSX1TS DP_OP_62J6_125_4796_R_2757_RW_20 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[10]), .CK(clk), .SN(n11380), .Q(
n11326) );
DFFSX1TS DP_OP_62J6_125_4796_R_5789_RW_1 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[1]), .CK(clk), .SN(n11380), .Q(
n11346) );
DFFSX1TS DP_OP_62J6_125_4796_R_2715_RW_6 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[16]), .CK(clk), .SN(n11379), .Q(
n11325) );
DFFRXLTS DP_OP_62J6_125_4796_R_3697_RW_8 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[6]), .CK(clk), .RN(n11384), .Q(
n11329) );
DFFSX1TS DP_OP_62J6_125_4796_R_2124_RW_7 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[11]), .CK(clk), .SN(n11379), .Q(
n11313) );
DFFSX1TS DP_OP_62J6_125_4796_R_2514_RW_11 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[14]), .CK(clk), .SN(n11379), .Q(
n11322) );
DFFSX1TS DP_OP_62J6_125_4796_R_2348_RW_7 ( .D(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[15]), .CK(clk), .SN(n11378), .Q(
n11317) );
DFFRXLTS DP_OP_59J6_122_190_R_6166_RW_0 ( .D(DP_OP_59J6_122_190_n201), .CK(
clk), .RN(n11284), .Q(n11258) );
DFFSX1TS DP_OP_59J6_122_190_R_6391 ( .D(DP_OP_59J6_122_190_n187), .CK(clk),
.SN(n9551), .Q(n11271) );
DFFSX2TS R_6655 ( .D(n11731), .CK(clk), .SN(n277), .Q(n150) );
DFFSX2TS R_6656 ( .D(n11727), .CK(clk), .SN(n11785), .Q(n149) );
DFFSX2TS R_6657 ( .D(n11726), .CK(clk), .SN(n328), .Q(n148) );
DFFSX2TS R_6658 ( .D(n11730), .CK(clk), .SN(n11629), .Q(n147) );
DFFSX2TS R_6660 ( .D(n1720), .CK(clk), .SN(n11723), .Q(n145) );
DFFSX1TS R_6659 ( .D(DP_OP_62J6_125_4796_n696), .CK(clk), .SN(n11537), .Q(
n146) );
DFFSX1TS add_x_2_R_6358 ( .D(add_x_2_n184), .CK(clk), .SN(n11611), .Q(n11603) );
NAND2X1TS U113 ( .A(EVEN1_Q_right[31]), .B(EVEN1_S_B[4]), .Y(add_x_1_n725)
);
NOR2X1TS U114 ( .A(n8684), .B(add_x_3_n138), .Y(add_x_3_n136) );
XNOR2X1TS U115 ( .A(n8771), .B(n7880), .Y(
EVEN1_middle_RECURSIVE_EVEN1_S_B[12]) );
XOR2X2TS U116 ( .A(n9514), .B(n8129), .Y(EVEN1_Q_right[32]) );
NOR2X1TS U117 ( .A(n8899), .B(n8898), .Y(DP_OP_59J6_122_190_n200) );
NAND2X1TS U118 ( .A(n8745), .B(n8744), .Y(DP_OP_59J6_122_190_n158) );
NOR2X1TS U119 ( .A(n9627), .B(n9626), .Y(add_x_2_n122) );
NAND2X1TS U120 ( .A(n7403), .B(n7402), .Y(add_x_3_n141) );
NOR2X4TS U121 ( .A(add_x_3_n122), .B(n9508), .Y(add_x_3_n5) );
INVX2TS U122 ( .A(n9628), .Y(add_x_2_n138) );
NOR2X1TS U123 ( .A(n9549), .B(n9548), .Y(n9550) );
NAND2X2TS U124 ( .A(n1430), .B(n9371), .Y(n1429) );
XOR2X2TS U125 ( .A(n11190), .B(n8007), .Y(n1455) );
AOI21X1TS U126 ( .A0(n9376), .A1(n9375), .B0(n9374), .Y(n9380) );
OAI21X1TS U127 ( .A0(n8904), .A1(n8903), .B0(n8902), .Y(n8909) );
NOR2X1TS U128 ( .A(n9624), .B(n9623), .Y(add_x_2_n117) );
OR2X2TS U129 ( .A(n8886), .B(n8885), .Y(n11300) );
OR2X6TS U130 ( .A(n8729), .B(n1013), .Y(n9711) );
NAND2X1TS U131 ( .A(n8500), .B(n8499), .Y(n8678) );
NAND2X1TS U132 ( .A(n7906), .B(n7905), .Y(add_x_2_n169) );
NAND2X1TS U133 ( .A(n9443), .B(n9442), .Y(add_x_3_n178) );
OAI21X2TS U134 ( .A0(n8838), .A1(n8837), .B0(n8836), .Y(n9396) );
NOR2X6TS U135 ( .A(n8471), .B(n8470), .Y(add_x_3_n122) );
NAND2X1TS U136 ( .A(n9504), .B(n9483), .Y(n9511) );
NOR2X2TS U137 ( .A(n7403), .B(n7402), .Y(add_x_3_n138) );
NAND2X2TS U138 ( .A(n8498), .B(n8497), .Y(n9502) );
NOR2X2TS U139 ( .A(n9647), .B(n9646), .Y(n9649) );
AOI2BB1X1TS U140 ( .A0N(n10772), .A1N(n10771), .B0(n10770), .Y(n10773) );
OAI2BB1X2TS U141 ( .A0N(n8365), .A1N(n8364), .B0(n647), .Y(n8107) );
OAI2BB1X1TS U142 ( .A0N(n8876), .A1N(n8877), .B0(n740), .Y(n8766) );
NAND2X2TS U143 ( .A(n7182), .B(n7181), .Y(n8851) );
NAND2BXLTS U144 ( .AN(n11188), .B(n7705), .Y(n873) );
OA21XLTS U145 ( .A0(n10771), .A1(n10672), .B0(n10769), .Y(n10591) );
NAND2BX1TS U146 ( .AN(n7263), .B(n7262), .Y(n7265) );
OAI21X2TS U147 ( .A0(n7976), .A1(n7378), .B0(n7978), .Y(n792) );
NOR2X2TS U148 ( .A(n8202), .B(n8201), .Y(n9666) );
AOI21X1TS U149 ( .A0(n8813), .A1(n8812), .B0(n8811), .Y(n8837) );
ADDFHX2TS U150 ( .A(n8880), .B(n8879), .CI(n8878), .CO(n8881), .S(n8182) );
XOR2X1TS U151 ( .A(n7285), .B(n7284), .Y(n8675) );
NAND2X1TS U152 ( .A(n3248), .B(n3247), .Y(n8916) );
NAND2X1TS U153 ( .A(n8748), .B(n8747), .Y(n171) );
NAND2X1TS U154 ( .A(n7372), .B(n1273), .Y(n7373) );
NAND2X1TS U155 ( .A(n1547), .B(n7987), .Y(n8533) );
NAND2X1TS U156 ( .A(n7376), .B(n7978), .Y(n7377) );
CLKBUFX2TS U157 ( .A(n10695), .Y(n11179) );
NAND2X1TS U158 ( .A(n7913), .B(n7912), .Y(n7914) );
CLKBUFX2TS U159 ( .A(n10695), .Y(n10807) );
CLKBUFX2TS U160 ( .A(n10695), .Y(n11158) );
NAND2XLTS U161 ( .A(n8373), .B(n8372), .Y(n8374) );
INVX2TS U162 ( .A(n9376), .Y(n1485) );
XNOR2X2TS U163 ( .A(n1225), .B(n8644), .Y(n8763) );
AO21X1TS U164 ( .A0(n10805), .A1(n10785), .B0(n10784), .Y(n10786) );
AO21X1TS U165 ( .A0(n10805), .A1(n10804), .B0(n10803), .Y(n10806) );
NOR2X1TS U166 ( .A(n9506), .B(n1693), .Y(add_x_3_n70) );
CLKAND2X2TS U167 ( .A(n7943), .B(n7767), .Y(n232) );
NAND2BX1TS U168 ( .AN(n9632), .B(n1360), .Y(n1359) );
NOR2X4TS U169 ( .A(n7841), .B(n7840), .Y(n8905) );
AOI21X1TS U170 ( .A0(n7953), .A1(n8183), .B0(n8184), .Y(n1357) );
INVX2TS U171 ( .A(n10805), .Y(n10744) );
INVX1TS U172 ( .A(n10805), .Y(n10769) );
OAI2BB1X2TS U173 ( .A0N(n7839), .A1N(n1095), .B0(n1094), .Y(n7840) );
NAND2X1TS U174 ( .A(n8544), .B(n8543), .Y(n8545) );
OAI21X1TS U175 ( .A0(n7903), .A1(n7904), .B0(n7902), .Y(n1476) );
NOR2X1TS U176 ( .A(n8189), .B(n9631), .Y(n8191) );
NAND2X1TS U177 ( .A(add_x_3_n99), .B(n9493), .Y(n9506) );
CLKINVX2TS U178 ( .A(n8518), .Y(n8565) );
INVX2TS U179 ( .A(EVEN1_Q_left[20]), .Y(n7705) );
NAND2BX1TS U180 ( .AN(n1211), .B(n8554), .Y(n8555) );
INVX4TS U181 ( .A(n9541), .Y(n769) );
OAI21X1TS U182 ( .A0(n11121), .A1(n10498), .B0(n10497), .Y(n10695) );
OAI21X1TS U183 ( .A0(n7979), .A1(n7978), .B0(n7977), .Y(n7980) );
AOI21X1TS U184 ( .A0(n7768), .A1(n7943), .B0(n7949), .Y(n1443) );
NOR2X1TS U185 ( .A(n7976), .B(n7979), .Y(n7981) );
XNOR2X1TS U186 ( .A(n885), .B(n1573), .Y(n8128) );
XOR2X1TS U187 ( .A(n9478), .B(n9477), .Y(n9484) );
NAND2X1TS U188 ( .A(n3064), .B(n3063), .Y(n7262) );
BUFX3TS U189 ( .A(n7267), .Y(n641) );
NAND2X1TS U190 ( .A(n5089), .B(n5090), .Y(n7977) );
NAND2X1TS U191 ( .A(n7688), .B(n3705), .Y(n9430) );
NAND2X1TS U192 ( .A(n6005), .B(n6745), .Y(n6006) );
OAI21X1TS U193 ( .A0(n8604), .A1(n8605), .B0(n8603), .Y(n1117) );
NAND2X1TS U194 ( .A(n8093), .B(n8092), .Y(n8104) );
NAND2X1TS U195 ( .A(n9436), .B(n191), .Y(n8711) );
NAND2X1TS U196 ( .A(n8183), .B(n7945), .Y(n8189) );
NOR2X1TS U197 ( .A(add_x_3_n109), .B(n1718), .Y(add_x_3_n99) );
NAND2X2TS U198 ( .A(n6613), .B(n8541), .Y(n9448) );
AOI21X1TS U199 ( .A0(n9473), .A1(n9469), .B0(n9470), .Y(n885) );
AO21X1TS U200 ( .A0(n10504), .A1(n11176), .B0(n10503), .Y(n10805) );
AOI21X1TS U201 ( .A0(n9473), .A1(n1304), .B0(n1302), .Y(n9478) );
CMPR32X2TS U202 ( .A(n8458), .B(n9397), .C(n8457), .CO(n8862), .S(n8462) );
NOR2BX1TS U203 ( .AN(n10504), .B(n10268), .Y(n10556) );
XNOR2X1TS U204 ( .A(n9473), .B(n1311), .Y(n1547) );
OAI2BB1X2TS U205 ( .A0N(n8348), .A1N(n8347), .B0(n1460), .Y(n7024) );
INVX2TS U206 ( .A(n10547), .Y(n10761) );
BUFX3TS U207 ( .A(n8367), .Y(n8540) );
NOR2XLTS U208 ( .A(n11172), .B(n11180), .Y(n10504) );
NOR2X1TS U209 ( .A(n7712), .B(n7714), .Y(n7688) );
OAI21X2TS U210 ( .A0(n4893), .A1(n4892), .B0(n1009), .Y(n7243) );
AND2X2TS U211 ( .A(n7965), .B(n7964), .Y(n1719) );
OAI21X2TS U212 ( .A0(n8187), .A1(n7944), .B0(n7951), .Y(n7768) );
INVX2TS U213 ( .A(n10594), .Y(n10780) );
INVX2TS U214 ( .A(n10594), .Y(n10799) );
NOR2X2TS U215 ( .A(n7944), .B(n7952), .Y(n8183) );
AOI21X1TS U216 ( .A0(n9314), .A1(n9313), .B0(n9312), .Y(n9319) );
ADDFHX2TS U217 ( .A(n8832), .B(n8641), .CI(n8640), .CO(n8686), .S(n8642) );
ADDFX1TS U218 ( .A(n8419), .B(n8418), .CI(n8417), .CO(n8446), .S(n8441) );
NOR2X2TS U219 ( .A(n9337), .B(n9403), .Y(n9265) );
XOR2X2TS U220 ( .A(n8175), .B(n8174), .Y(n9329) );
XOR2X2TS U221 ( .A(n7899), .B(n7901), .Y(n787) );
NAND2X1TS U222 ( .A(n6842), .B(n6841), .Y(n7951) );
NAND2X1TS U223 ( .A(n6621), .B(n6620), .Y(n7912) );
INVX3TS U224 ( .A(n8833), .Y(n8641) );
OAI2BB1X1TS U225 ( .A0N(n1461), .A1N(n8925), .B0(n8346), .Y(n1460) );
NAND2X1TS U226 ( .A(n5086), .B(n6266), .Y(n5087) );
INVX2TS U227 ( .A(n4937), .Y(n1275) );
XNOR2X1TS U228 ( .A(n1522), .B(n8596), .Y(n8640) );
OA21XLTS U229 ( .A0(n10414), .A1(n11074), .B0(n11083), .Y(n10415) );
OA21XLTS U230 ( .A0(n11066), .A1(n10399), .B0(n10398), .Y(n11082) );
AND2X2TS U231 ( .A(n6639), .B(n6638), .Y(n1711) );
INVX2TS U232 ( .A(n10547), .Y(n10794) );
AOI21X2TS U233 ( .A0(n7710), .A1(n208), .B0(n3057), .Y(n7702) );
NAND2BX2TS U234 ( .AN(n889), .B(n6267), .Y(n5020) );
OAI21X1TS U235 ( .A0(n7308), .A1(n7307), .B0(n7306), .Y(n9530) );
AOI21X1TS U236 ( .A0(n8170), .A1(n9314), .B0(n8169), .Y(n8175) );
NAND2X2TS U237 ( .A(n8073), .B(n8074), .Y(n9362) );
ADDFHX2TS U238 ( .A(n8702), .B(n8701), .CI(n8700), .CO(n8335), .S(n8736) );
AND2X2TS U239 ( .A(n10507), .B(n11476), .Y(n10594) );
OAI21X1TS U240 ( .A0(n10540), .A1(n10588), .B0(n10541), .Y(n10783) );
XOR2X1TS U241 ( .A(n9300), .B(n9299), .Y(n9323) );
CMPR32X2TS U242 ( .A(n7097), .B(n7096), .C(n8930), .CO(n7138), .S(n7079) );
INVX2TS U243 ( .A(n8832), .Y(n8704) );
NAND2X1TS U244 ( .A(n6275), .B(n6274), .Y(n9471) );
NAND2X1TS U245 ( .A(n6277), .B(n6276), .Y(n9475) );
INVX2TS U246 ( .A(n8224), .Y(n8344) );
INVX2TS U247 ( .A(n8839), .Y(n8705) );
INVX2TS U248 ( .A(n8609), .Y(n8631) );
OAI2BB1X2TS U249 ( .A0N(n7868), .A1N(n7867), .B0(n708), .Y(n7899) );
AO21XLTS U250 ( .A0(n411), .A1(n612), .B0(n7504), .Y(n8432) );
CLKINVX3TS U251 ( .A(n7617), .Y(n8607) );
OAI2BB1X2TS U252 ( .A0N(n7856), .A1N(n7855), .B0(n809), .Y(n7901) );
NAND2X2TS U253 ( .A(n6606), .B(n6605), .Y(n6609) );
OR2X2TS U254 ( .A(n7788), .B(n7787), .Y(n7948) );
XNOR2X1TS U255 ( .A(n1535), .B(n7098), .Y(n7060) );
CLKXOR2X2TS U256 ( .A(n7531), .B(n1085), .Y(n7568) );
OAI21X1TS U257 ( .A0(n8934), .A1(n1579), .B0(n1577), .Y(n7170) );
XOR2X2TS U258 ( .A(n718), .B(n8298), .Y(n8349) );
AOI21X2TS U259 ( .A0(n9314), .A1(n9295), .B0(n9294), .Y(n9300) );
ADDFHX1TS U260 ( .A(n8232), .B(n8231), .CI(n8230), .CO(n8343), .S(n8702) );
INVX2TS U261 ( .A(n10626), .Y(n10547) );
CMPR32X2TS U262 ( .A(n7019), .B(n7018), .C(n8924), .CO(n7042), .S(n8337) );
XOR2X2TS U263 ( .A(n8347), .B(n8348), .Y(n1462) );
NOR2BX1TS U264 ( .AN(n10493), .B(n11511), .Y(n10494) );
XOR2X1TS U265 ( .A(n893), .B(n4754), .Y(n4935) );
XOR2X1TS U266 ( .A(n7511), .B(n7512), .Y(n1611) );
XOR2X1TS U267 ( .A(n8594), .B(n1165), .Y(n1522) );
XOR2X2TS U268 ( .A(n8022), .B(n8021), .Y(n8074) );
XNOR2X1TS U269 ( .A(n1677), .B(n1676), .Y(n9264) );
CMPR32X2TS U270 ( .A(n6994), .B(n6993), .C(n6992), .CO(n7056), .S(n8347) );
NAND2X1TS U271 ( .A(n6791), .B(n6790), .Y(n6805) );
CLKINVX2TS U272 ( .A(n7416), .Y(n7608) );
NAND2X1TS U273 ( .A(n7752), .B(n7753), .Y(n7767) );
NAND2X1TS U274 ( .A(n9249), .B(n9248), .Y(n9414) );
CLKINVX3TS U275 ( .A(n8924), .Y(n7057) );
OAI2BB1X1TS U276 ( .A0N(n8282), .A1N(n8281), .B0(n1583), .Y(n8923) );
OAI21X2TS U277 ( .A0(n7867), .A1(n7868), .B0(n7866), .Y(n708) );
XOR2X1TS U278 ( .A(n9135), .B(n9134), .Y(n1677) );
INVX2TS U279 ( .A(n8929), .Y(n7045) );
CMPR32X2TS U280 ( .A(n7012), .B(n7011), .C(n7010), .CO(n7019), .S(n8327) );
NAND2X1TS U281 ( .A(n8020), .B(n8019), .Y(n8021) );
NAND2X1TS U282 ( .A(n4538), .B(n4537), .Y(n4888) );
NAND2XLTS U283 ( .A(n4942), .B(n1181), .Y(n4754) );
OAI2BB1X2TS U284 ( .A0N(n8009), .A1N(n8020), .B0(n8019), .Y(n8014) );
OAI21X1TS U285 ( .A0(n7855), .A1(n7856), .B0(n7854), .Y(n809) );
NAND2X1TS U286 ( .A(n4451), .B(n4450), .Y(n9427) );
NAND2X2TS U287 ( .A(n6271), .B(n6270), .Y(n8109) );
INVX2TS U288 ( .A(n779), .Y(n886) );
NAND2XLTS U289 ( .A(n1578), .B(n7127), .Y(n1577) );
NOR2X6TS U290 ( .A(n7223), .B(n7222), .Y(n8066) );
CLKAND2X2TS U291 ( .A(n8012), .B(n8011), .Y(n8013) );
NOR2X1TS U292 ( .A(n10506), .B(n11470), .Y(n10540) );
NOR2X1TS U293 ( .A(n10505), .B(n11469), .Y(n10536) );
NAND2BX1TS U294 ( .AN(n4945), .B(n4944), .Y(n1179) );
OAI21X1TS U295 ( .A0(n8596), .A1(n8595), .B0(n8594), .Y(n1521) );
XOR2X2TS U296 ( .A(n6996), .B(n719), .Y(n718) );
OAI22X1TS U297 ( .A0(n7129), .A1(n537), .B0(n7154), .B1(n369), .Y(n7167) );
ADDFHX1TS U298 ( .A(n7415), .B(n7414), .CI(n7413), .CO(n7622), .S(n7609) );
ADDFX1TS U299 ( .A(n7502), .B(n7501), .CI(n7500), .CO(n7499), .S(n7668) );
NAND2X2TS U300 ( .A(n888), .B(n6269), .Y(n887) );
CMPR32X2TS U301 ( .A(n178), .B(n8314), .C(n8313), .CO(n8623), .S(n8611) );
AO22XLTS U302 ( .A0(n7148), .A1(n677), .B0(n7149), .B1(n7150), .Y(n8429) );
NOR2X1TS U303 ( .A(n6684), .B(n6683), .Y(n7298) );
NAND2X1TS U304 ( .A(n6684), .B(n6683), .Y(n7301) );
AO21X1TS U305 ( .A0(n559), .A1(n471), .B0(n7092), .Y(n7121) );
INVX2TS U306 ( .A(n6271), .Y(n1043) );
OAI2BB1X1TS U307 ( .A0N(n7132), .A1N(n7131), .B0(n845), .Y(n8937) );
OAI21X1TS U308 ( .A0(n8282), .A1(n8281), .B0(n8280), .Y(n1583) );
OAI2BB1X2TS U309 ( .A0N(n3703), .A1N(n3702), .B0(n1466), .Y(n7015) );
OAI22X1TS U310 ( .A0(n690), .A1(n7147), .B0(n417), .B1(n501), .Y(n8430) );
XOR2X1TS U311 ( .A(n7160), .B(n1588), .Y(n7162) );
NAND2BX1TS U312 ( .AN(n7531), .B(n7522), .Y(n7525) );
ADDFHX1TS U313 ( .A(n6568), .B(n6567), .CI(n6566), .CO(n6623), .S(n6620) );
NAND3BX2TS U314 ( .AN(n9141), .B(n9130), .C(n9133), .Y(n1511) );
ADDFHX1TS U315 ( .A(n7728), .B(n7727), .CI(n7726), .CO(n7753), .S(n6841) );
ADDFHX2TS U316 ( .A(n6991), .B(n6990), .CI(n6989), .CO(n8929), .S(n8924) );
XOR2X1TS U317 ( .A(n8451), .B(n438), .Y(n7082) );
ADDFHX2TS U318 ( .A(n7862), .B(n7861), .CI(n7860), .CO(n7888), .S(n7855) );
ADDFHX1TS U319 ( .A(n7771), .B(n7769), .CI(n7770), .CO(n7788), .S(n7752) );
ADDFHX2TS U320 ( .A(n7859), .B(n7858), .CI(n7857), .CO(n7889), .S(n7867) );
CMPR32X2TS U321 ( .A(n7575), .B(n7574), .C(n7573), .CO(n7601), .S(n7676) );
CMPR32X2TS U322 ( .A(n2968), .B(n2967), .C(n2966), .CO(n2829), .S(n3020) );
OAI2BB1X1TS U323 ( .A0N(n3031), .A1N(n3030), .B0(n1056), .Y(n3022) );
NAND2X1TS U324 ( .A(n4359), .B(n4358), .Y(n7696) );
OAI2BB1X1TS U325 ( .A0N(n6265), .A1N(n6264), .B0(n1299), .Y(n6270) );
OAI21X2TS U326 ( .A0(n3703), .A1(n3702), .B0(n3701), .Y(n1466) );
OAI2BB1X1TS U327 ( .A0N(n847), .A1N(n846), .B0(n7130), .Y(n845) );
NAND2X1TS U328 ( .A(n7191), .B(n7206), .Y(n7192) );
NAND2X2TS U329 ( .A(n5019), .B(n5018), .Y(n6267) );
OR2X1TS U330 ( .A(n3047), .B(n3046), .Y(n9283) );
NAND2BX1TS U331 ( .AN(n7209), .B(n7210), .Y(n1330) );
XOR2X1TS U332 ( .A(n6584), .B(n1623), .Y(n1622) );
ADDFHX2TS U333 ( .A(n8297), .B(n8296), .CI(n8295), .CO(n8282), .S(n8579) );
ADDFHX2TS U334 ( .A(n8590), .B(n8589), .CI(n8588), .CO(n8580), .S(n8598) );
ADDFHX1TS U335 ( .A(n7052), .B(n7051), .CI(n7050), .CO(n8931), .S(n8928) );
NAND2BXLTS U336 ( .AN(n1194), .B(n4419), .Y(n1193) );
ADDFX1TS U337 ( .A(n2990), .B(n2989), .CI(n2988), .CO(n2991), .S(n3025) );
XNOR2X1TS U338 ( .A(n8225), .B(n440), .Y(n8312) );
ADDFHX1TS U339 ( .A(n3034), .B(n3033), .CI(n3032), .CO(n3024), .S(n3052) );
ADDFHX1TS U340 ( .A(n8572), .B(n8571), .CI(n8570), .CO(n8569), .S(n8596) );
ADDFX1TS U341 ( .A(n8275), .B(n8274), .CI(n8273), .CO(n8301), .S(n8602) );
CMPR32X2TS U342 ( .A(n2971), .B(n2970), .C(n2969), .CO(n2972), .S(n3019) );
XNOR2X1TS U343 ( .A(n1057), .B(n3029), .Y(n3053) );
CMPR32X2TS U344 ( .A(n3621), .B(n3620), .C(n3619), .CO(n3646), .S(n3641) );
OAI2BB1X2TS U345 ( .A0N(n5345), .A1N(n5346), .B0(n728), .Y(n5396) );
OAI2BB1X2TS U346 ( .A0N(n6703), .A1N(n6702), .B0(n977), .Y(n6752) );
OAI2BB1X2TS U347 ( .A0N(n3452), .A1N(n3451), .B0(n1523), .Y(n8609) );
OAI2BB1X1TS U348 ( .A0N(n5765), .A1N(n5764), .B0(n951), .Y(n5846) );
INVX2TS U349 ( .A(n10254), .Y(n10483) );
ADDHXLTS U350 ( .A(n6632), .B(n6631), .CO(n6637), .S(n6635) );
ADDHXLTS U351 ( .A(n7958), .B(n7957), .CO(n7963), .S(n7961) );
CLKBUFX2TS U352 ( .A(n8855), .Y(n537) );
OAI2BB1X1TS U353 ( .A0N(n5017), .A1N(n5016), .B0(n731), .Y(n5018) );
NOR2X2TS U354 ( .A(n7494), .B(n7496), .Y(n9131) );
XNOR2X2TS U355 ( .A(n3030), .B(n3031), .Y(n1057) );
OAI22X1TS U356 ( .A0(n411), .A1(n7649), .B0(n612), .B1(n7648), .Y(n7833) );
ADDFHX1TS U357 ( .A(n6516), .B(n6515), .CI(n6514), .CO(n6565), .S(n6539) );
XNOR2X1TS U358 ( .A(n358), .B(n7505), .Y(n7407) );
ADDFHX2TS U359 ( .A(n8294), .B(n8293), .CI(n8292), .CO(n8588), .S(n8584) );
ADDFHX2TS U360 ( .A(n6235), .B(n6234), .CI(n6233), .CO(n6227), .S(n6250) );
OAI22X1TS U361 ( .A0(n8318), .A1(n613), .B0(n8324), .B1(n411), .Y(n8567) );
NAND2X2TS U362 ( .A(n1434), .B(n9269), .Y(n9291) );
XOR2X1TS U363 ( .A(n2401), .B(n930), .Y(n929) );
XOR2X1TS U364 ( .A(n2396), .B(n2395), .Y(n2402) );
ADDFHX2TS U365 ( .A(n3709), .B(n3710), .CI(n3708), .CO(n7055), .S(n6988) );
XOR2X1TS U366 ( .A(n5393), .B(n1450), .Y(n1449) );
OAI2BB1X2TS U367 ( .A0N(n5719), .A1N(n5718), .B0(n1214), .Y(n5916) );
ADDFX1TS U368 ( .A(n7478), .B(n7477), .CI(n7476), .CO(n8292), .S(n7491) );
OAI2BB1X2TS U369 ( .A0N(n3588), .A1N(n3587), .B0(n1672), .Y(n3589) );
NAND2X1TS U370 ( .A(n10303), .B(n10302), .Y(n10308) );
OAI2BB1X1TS U371 ( .A0N(n1626), .A1N(n6433), .B0(n6487), .Y(n1625) );
INVX2TS U372 ( .A(n8459), .Y(n506) );
NOR2X1TS U373 ( .A(n10303), .B(n10302), .Y(n10309) );
OAI2BB1X2TS U374 ( .A0N(n1525), .A1N(n1524), .B0(n3450), .Y(n1523) );
NAND2X1TS U375 ( .A(n4755), .B(n1705), .Y(n4920) );
AO21XLTS U376 ( .A0(n420), .A1(n251), .B0(n434), .Y(n6631) );
CMPR32X2TS U377 ( .A(n8269), .B(n8268), .C(n8267), .CO(n6956), .S(n8283) );
NOR2X2TS U378 ( .A(n4515), .B(n4514), .Y(n4728) );
XOR2X2TS U379 ( .A(n3479), .B(n3480), .Y(n1171) );
XOR2X2TS U380 ( .A(n3452), .B(n3451), .Y(n1252) );
ADDFHX1TS U381 ( .A(n7534), .B(n7533), .CI(n7532), .CO(n7604), .S(n7572) );
OAI21X2TS U382 ( .A0(n7209), .A1(n7206), .B0(n7210), .Y(n5837) );
ADDHX1TS U383 ( .A(n2865), .B(n2864), .CO(n2916), .S(n2788) );
AOI21X2TS U384 ( .A0(n9156), .A1(n1671), .B0(n3568), .Y(n3569) );
ADDFHX1TS U385 ( .A(n6536), .B(n6535), .CI(n6534), .CO(n6543), .S(n6513) );
NAND2X2TS U386 ( .A(n1671), .B(n9165), .Y(n3570) );
XOR2X2TS U387 ( .A(n3637), .B(n3656), .Y(n3661) );
ADDFHX1TS U388 ( .A(n7552), .B(n7553), .CI(n7554), .CO(n7606), .S(n7603) );
ADDFHX2TS U389 ( .A(n7293), .B(n6198), .CI(n6197), .CO(n6208), .S(n6235) );
ADDFX1TS U390 ( .A(n8266), .B(n8265), .CI(n8264), .CO(n8284), .S(n8585) );
XOR2X2TS U391 ( .A(n1484), .B(n3583), .Y(n7646) );
XOR2X1TS U392 ( .A(n8228), .B(n7092), .Y(n8326) );
ADDFHX1TS U393 ( .A(n6528), .B(n6527), .CI(n6526), .CO(n6545), .S(n6514) );
CMPR32X2TS U394 ( .A(n3627), .B(n3626), .C(n3625), .CO(n3665), .S(n3623) );
ADDFHX1TS U395 ( .A(n7119), .B(n7118), .CI(n7117), .CO(n7161), .S(n7131) );
ADDFHX1TS U396 ( .A(n7069), .B(n7068), .CI(n7067), .CO(n7132), .S(n7073) );
XNOR2X2TS U397 ( .A(n4347), .B(n1004), .Y(n1434) );
ADDFHX2TS U398 ( .A(n3573), .B(n3572), .CI(n3571), .CO(n7416), .S(n7496) );
CMPR32X2TS U399 ( .A(n7731), .B(n7730), .C(n7729), .CO(n7771), .S(n7749) );
ADDFHX1TS U400 ( .A(n2965), .B(n2964), .CI(n2963), .CO(n8779), .S(n8778) );
CMPR32X2TS U401 ( .A(n3692), .B(n3691), .C(n3690), .CO(n3721), .S(n3700) );
INVX2TS U402 ( .A(n5896), .Y(n5911) );
CMPR32X2TS U403 ( .A(n3045), .B(n3044), .C(n3043), .CO(n3040), .S(n3046) );
OAI2BB1X2TS U404 ( .A0N(n3582), .A1N(n3581), .B0(n637), .Y(n3572) );
ADDHXLTS U405 ( .A(n11310), .B(n10314), .CO(n10315), .S(n10302) );
OAI21X2TS U406 ( .A0(n3587), .A1(n3588), .B0(n3586), .Y(n1672) );
OAI2BB1X1TS U407 ( .A0N(n5827), .A1N(n5825), .B0(n5810), .Y(n5839) );
OAI2BB1X2TS U408 ( .A0N(n5350), .A1N(n1345), .B0(n1344), .Y(n5856) );
NAND2X2TS U409 ( .A(n5834), .B(n5833), .Y(n7206) );
OAI2BB1X1TS U410 ( .A0N(n6448), .A1N(n1662), .B0(n1660), .Y(n6479) );
OAI21X1TS U411 ( .A0(n3584), .A1(n3585), .B0(n3583), .Y(n1483) );
INVX3TS U412 ( .A(n8459), .Y(n505) );
AOI21X2TS U413 ( .A0(n7002), .A1(n7001), .B0(n7000), .Y(n7007) );
NOR2X1TS U414 ( .A(n10252), .B(n10234), .Y(n10292) );
OAI22X1TS U415 ( .A0(n8258), .A1(n135), .B0(n8257), .B1(n462), .Y(n8265) );
ADDHX1TS U416 ( .A(n3112), .B(n3111), .CO(n3219), .S(n3106) );
OAI22X1TS U417 ( .A0(n7471), .A1(n8255), .B0(n8256), .B1(n457), .Y(n8252) );
OAI22X1TS U418 ( .A0(n8257), .A1(n135), .B0(n6949), .B1(n462), .Y(n8268) );
ADDFHX1TS U419 ( .A(n7544), .B(n7543), .CI(n7542), .CO(n7532), .S(n7586) );
ADDFHX2TS U420 ( .A(n5480), .B(n5479), .CI(n5478), .CO(n5941), .S(n5448) );
ADDFHX1TS U421 ( .A(n7444), .B(n7443), .CI(n7442), .CO(n7481), .S(n7605) );
CMPR32X2TS U422 ( .A(n1692), .B(n6556), .C(n6555), .CO(n6571), .S(n6553) );
CMPR32X2TS U423 ( .A(n134), .B(n7490), .C(n7489), .CO(n8286), .S(n7482) );
ADDHXLTS U424 ( .A(n7455), .B(n7454), .CO(n7444), .S(n7555) );
INVX2TS U425 ( .A(n5426), .Y(n5480) );
NOR2X1TS U426 ( .A(n10217), .B(n10216), .Y(n10252) );
NAND2X1TS U427 ( .A(n10288), .B(n10287), .Y(n10293) );
NOR2X1TS U428 ( .A(n6934), .B(n197), .Y(n7069) );
NOR2X1TS U429 ( .A(n6905), .B(n453), .Y(n6946) );
CMPR32X2TS U430 ( .A(n5461), .B(n5460), .C(n5459), .CO(n5952), .S(n5462) );
CMPR32X2TS U431 ( .A(n6289), .B(n6288), .C(n7313), .CO(n6389), .S(n6285) );
NAND2BXLTS U432 ( .AN(n6182), .B(n7310), .Y(n1047) );
NOR2X1TS U433 ( .A(n10288), .B(n10287), .Y(n10295) );
NAND2X1TS U434 ( .A(n10248), .B(n10247), .Y(n10294) );
NOR2X2TS U435 ( .A(n3971), .B(n3970), .Y(n4293) );
NOR2X1TS U436 ( .A(n10248), .B(n10247), .Y(n10291) );
NAND2X1TS U437 ( .A(n2467), .B(n2472), .Y(n8051) );
XOR2X1TS U438 ( .A(n6921), .B(n405), .Y(n8254) );
NAND2BX2TS U439 ( .AN(n855), .B(n3887), .Y(n4454) );
OAI21X1TS U440 ( .A0(n3582), .A1(n3581), .B0(n3580), .Y(n637) );
OAI21X1TS U441 ( .A0(n5350), .A1(n1345), .B0(n5349), .Y(n1344) );
NOR2X2TS U442 ( .A(n6902), .B(n453), .Y(n6937) );
NAND2X1TS U443 ( .A(n7193), .B(n189), .Y(n8029) );
ADDFHX1TS U444 ( .A(n5333), .B(n5332), .CI(n5331), .CO(n5391), .S(n5351) );
OAI22X1TS U445 ( .A0(n7453), .A1(n8255), .B0(n7452), .B1(n458), .Y(n7556) );
BUFX4TS U446 ( .A(n827), .Y(n8459) );
XOR2X1TS U447 ( .A(n3523), .B(n3524), .Y(n775) );
XOR2X2TS U448 ( .A(n4867), .B(n4865), .Y(n752) );
NAND2BX1TS U449 ( .AN(n2866), .B(n1254), .Y(n1253) );
ADDFHX1TS U450 ( .A(n5957), .B(n5956), .CI(n5955), .CO(n6700), .S(n5942) );
XNOR2X1TS U451 ( .A(n8241), .B(n139), .Y(n2958) );
XNOR2X1TS U452 ( .A(n7470), .B(n404), .Y(n8256) );
XNOR2X1TS U453 ( .A(n7547), .B(n405), .Y(n6907) );
ADDFHX2TS U454 ( .A(n3449), .B(n3448), .CI(n3447), .CO(n3451), .S(n3478) );
ADDFHX1TS U455 ( .A(n6724), .B(n6723), .CI(n6722), .CO(n6756), .S(n6719) );
AOI21X1TS U456 ( .A0(n9238), .A1(n9237), .B0(n3538), .Y(n9215) );
CLKXOR2X2TS U457 ( .A(n2644), .B(n2643), .Y(n7507) );
CMPR32X2TS U458 ( .A(n6423), .B(n6422), .C(n7324), .CO(n6447), .S(n6425) );
CMPR32X2TS U459 ( .A(n6068), .B(n6067), .C(n6066), .CO(n6291), .S(n6184) );
NAND2X1TS U460 ( .A(n2343), .B(n2342), .Y(n2398) );
NOR2X1TS U461 ( .A(n6193), .B(n6111), .Y(n4299) );
OAI2BB1X2TS U462 ( .A0N(n3483), .A1N(n3482), .B0(n1249), .Y(n3447) );
AO21XLTS U463 ( .A0(n6494), .A1(n479), .B0(n6397), .Y(n6532) );
AO21XLTS U464 ( .A0(n6410), .A1(n472), .B0(n6293), .Y(n6452) );
OR2X1TS U465 ( .A(n6960), .B(n8423), .Y(n6959) );
NOR2X1TS U466 ( .A(n436), .B(n3648), .Y(n3692) );
CLKBUFX2TS U467 ( .A(n8255), .Y(n554) );
NOR2X1TS U468 ( .A(n436), .B(n1516), .Y(n3658) );
NAND2X1TS U469 ( .A(n2792), .B(n2791), .Y(n2793) );
CLKBUFX2TS U470 ( .A(n8259), .Y(n553) );
NAND2X1TS U471 ( .A(n1322), .B(n2103), .Y(n1321) );
NOR2BX1TS U472 ( .AN(n10229), .B(n10228), .Y(n10230) );
XNOR2X2TS U473 ( .A(n2800), .B(n2799), .Y(n8278) );
NAND2BX1TS U474 ( .AN(n10229), .B(n10228), .Y(n10227) );
NAND2BX1TS U475 ( .AN(n1062), .B(n2597), .Y(n1061) );
OAI22X1TS U476 ( .A0(n6112), .A1(n589), .B0(n6048), .B1(n488), .Y(n6173) );
AOI21X1TS U477 ( .A0(n3283), .A1(n6855), .B0(n6858), .Y(n3206) );
OAI2BB1X1TS U478 ( .A0N(n10409), .A1N(n10406), .B0(n10408), .Y(n10401) );
ADDFX2TS U479 ( .A(n5467), .B(n5466), .CI(n9590), .CO(n5959), .S(n5479) );
ADDFHX1TS U480 ( .A(n3430), .B(n3429), .CI(n3428), .CO(n3425), .S(n3497) );
XOR2X2TS U481 ( .A(n774), .B(n5667), .Y(n5677) );
XOR2X1TS U482 ( .A(n3134), .B(n3133), .Y(n1135) );
OAI21X1TS U483 ( .A0(n9220), .A1(n9223), .B0(n9221), .Y(n9238) );
AOI21X1TS U484 ( .A0(n2794), .A1(n2792), .B0(n2640), .Y(n2644) );
NOR2X1TS U485 ( .A(n436), .B(n3610), .Y(n3659) );
OAI21X1TS U486 ( .A0(n2369), .A1(n2368), .B0(n2367), .Y(n2473) );
ADDFHX1TS U487 ( .A(n4789), .B(n4788), .CI(n4787), .CO(n6546), .S(n6524) );
XNOR2X2TS U488 ( .A(n753), .B(n362), .Y(n7433) );
XNOR2X2TS U489 ( .A(n6558), .B(n383), .Y(n6188) );
AOI21X1TS U490 ( .A0(n6858), .A1(n1161), .B0(n1116), .Y(n1160) );
NOR2X1TS U491 ( .A(n5340), .B(n5250), .Y(n2369) );
CMPR32X2TS U492 ( .A(n3494), .B(n3493), .C(n3492), .CO(n3501), .S(n3574) );
INVX2TS U493 ( .A(n5056), .Y(n6223) );
INVX2TS U494 ( .A(n3608), .Y(n3454) );
ADDFX1TS U495 ( .A(n5343), .B(n5342), .CI(n5341), .CO(n5354), .S(n5308) );
OAI2BB1X2TS U496 ( .A0N(n5865), .A1N(n5864), .B0(n733), .Y(n5891) );
INVX2TS U497 ( .A(n5315), .Y(n5880) );
AO21XLTS U498 ( .A0(n4773), .A1(n574), .B0(n1631), .Y(n4789) );
NOR2X1TS U499 ( .A(n10200), .B(n10199), .Y(n10265) );
NAND2X1TS U500 ( .A(n10485), .B(n10484), .Y(n10486) );
INVX2TS U501 ( .A(n456), .Y(n457) );
ADDHXLTS U502 ( .A(n11315), .B(n1702), .CO(n10314), .S(n10301) );
NOR2X1TS U503 ( .A(n3535), .B(n3534), .Y(n9220) );
NAND2X1TS U504 ( .A(n6862), .B(n6861), .Y(n6999) );
AO21XLTS U505 ( .A0(n3474), .A1(n607), .B0(n3439), .Y(n3606) );
AO21XLTS U506 ( .A0(n579), .A1(n1316), .B0(n5639), .Y(n5964) );
OAI2BB1X2TS U507 ( .A0N(n4861), .A1N(n891), .B0(n890), .Y(n4998) );
OAI21X1TS U508 ( .A0(n4724), .A1(n4725), .B0(n4723), .Y(n990) );
OAI2BB1X1TS U509 ( .A0N(n3143), .A1N(n3142), .B0(n3141), .Y(n3240) );
NOR2X1TS U510 ( .A(n10084), .B(n10083), .Y(n10429) );
NOR2X1TS U511 ( .A(n2077), .B(n2075), .Y(n2103) );
NAND2BX1TS U512 ( .AN(n1001), .B(n6056), .Y(n4307) );
BUFX3TS U513 ( .A(n7547), .Y(n753) );
XNOR2X1TS U514 ( .A(n5660), .B(n5668), .Y(n774) );
NAND2BX1TS U515 ( .AN(n10179), .B(n10178), .Y(n10438) );
OAI22X1TS U516 ( .A0(n5428), .A1(n580), .B0(n5686), .B1(n5639), .Y(n5466) );
OAI2BB1X2TS U517 ( .A0N(n1251), .A1N(n1250), .B0(n3481), .Y(n1249) );
NAND3X1TS U518 ( .A(n3518), .B(n3517), .C(n3516), .Y(n3581) );
NAND2BXLTS U519 ( .AN(n353), .B(n1738), .Y(n7425) );
OAI22X1TS U520 ( .A0(n7105), .A1(n3416), .B0(n3405), .B1(n539), .Y(n3394) );
XOR2X1TS U521 ( .A(n5324), .B(n5350), .Y(n1346) );
XOR2X2TS U522 ( .A(n754), .B(n3104), .Y(n7474) );
XNOR2X2TS U523 ( .A(n3317), .B(n3316), .Y(n7487) );
XOR2X2TS U524 ( .A(n919), .B(n6297), .Y(n918) );
ADDFHX1TS U525 ( .A(n5649), .B(n5648), .CI(n5647), .CO(n5879), .S(n5886) );
XOR2X1TS U526 ( .A(n7470), .B(n392), .Y(n7437) );
XNOR2X2TS U527 ( .A(n6895), .B(n6894), .Y(n7485) );
ADDFHX1TS U528 ( .A(n6819), .B(n6818), .CI(n6817), .CO(n8034), .S(n7217) );
ADDFX1TS U529 ( .A(n8662), .B(n8661), .CI(n8660), .CO(n9201), .S(n8000) );
ADDFHX2TS U530 ( .A(n3966), .B(n3965), .CI(n3964), .CO(n3886), .S(n3971) );
CMPR32X2TS U531 ( .A(n6769), .B(n6768), .C(n6767), .CO(n6817), .S(n6778) );
BUFX6TS U532 ( .A(n7105), .Y(n140) );
OAI2BB1X1TS U533 ( .A0N(n3957), .A1N(n3958), .B0(n1191), .Y(n3966) );
INVX2TS U534 ( .A(n197), .Y(n380) );
ADDFX1TS U535 ( .A(n6419), .B(n6418), .CI(n6417), .CO(n6458), .S(n6396) );
ADDHXLTS U536 ( .A(n11319), .B(n9903), .CO(n10285), .S(n10245) );
INVX4TS U537 ( .A(n1097), .Y(n6921) );
OAI2BB1X2TS U538 ( .A0N(n2132), .A1N(n2131), .B0(n1615), .Y(n5116) );
NAND2X1TS U539 ( .A(n2734), .B(n2733), .Y(n2735) );
CMPR32X2TS U540 ( .A(n3184), .B(n3185), .C(n3183), .CO(n3299), .S(n3239) );
NOR2X2TS U541 ( .A(n2230), .B(n2229), .Y(n2235) );
NAND2BX1TS U542 ( .AN(n1382), .B(n2230), .Y(n2236) );
OAI2BB1X1TS U543 ( .A0N(n6093), .A1N(n6094), .B0(n6076), .Y(n6143) );
OAI21X2TS U544 ( .A0(n1531), .A1(n190), .B0(n6901), .Y(n8428) );
NOR2X1TS U545 ( .A(n9076), .B(n9081), .Y(n1973) );
INVX2TS U546 ( .A(n1738), .Y(n360) );
INVX2TS U547 ( .A(n1598), .Y(n539) );
OAI21X1TS U548 ( .A0(n6962), .A1(n6967), .B0(n6966), .Y(n833) );
XNOR2X2TS U549 ( .A(n6966), .B(n6968), .Y(n6980) );
CMPR32X2TS U550 ( .A(n735), .B(Data_B_i[53]), .C(n6865), .CO(n6866), .S(
n6863) );
XOR2X2TS U551 ( .A(n5803), .B(n5802), .Y(n1263) );
OAI21X2TS U552 ( .A0(n2953), .A1(n2708), .B0(n2707), .Y(n2711) );
OAI21X2TS U553 ( .A0(n754), .A1(n3315), .B0(n3314), .Y(n3317) );
XNOR2X2TS U554 ( .A(n6964), .B(n6977), .Y(n3272) );
XNOR2X2TS U555 ( .A(n5313), .B(n658), .Y(n9559) );
ADDFHX2TS U556 ( .A(n4733), .B(n4732), .CI(n4731), .CO(n4723), .S(n4744) );
ADDFHX1TS U557 ( .A(n5381), .B(n5380), .CI(n5379), .CO(n5417), .S(n5368) );
NOR2X2TS U558 ( .A(n3198), .B(n3200), .Y(n6855) );
XOR2X1TS U559 ( .A(n682), .B(n1395), .Y(n5034) );
NOR2X2TS U560 ( .A(n6854), .B(n1124), .Y(n1123) );
ADDFHX2TS U561 ( .A(n4509), .B(n4510), .CI(n4508), .CO(n4734), .S(n4512) );
OAI21X1TS U562 ( .A0(n6857), .A1(n1124), .B0(n6856), .Y(n1120) );
ADDFHX2TS U563 ( .A(n2338), .B(n2337), .CI(n2336), .CO(n2329), .S(n2343) );
OAI21X1TS U564 ( .A0(n1531), .A1(n6896), .B0(n6899), .Y(n6895) );
AOI21X1TS U565 ( .A0(n2698), .A1(n2947), .B0(n2951), .Y(n650) );
ADDFHX1TS U566 ( .A(n6824), .B(n6823), .CI(n6822), .CO(n7738), .S(n6818) );
CMPR32X2TS U567 ( .A(n7999), .B(n7998), .C(n7997), .CO(n8660), .S(n5103) );
CMPR32X2TS U568 ( .A(n5276), .B(n131), .C(n5275), .CO(n5206), .S(n5283) );
CMPR32X2TS U569 ( .A(n3489), .B(n3488), .C(n3487), .CO(n3483), .S(n3523) );
CMPR32X2TS U570 ( .A(n5666), .B(n5665), .C(n5664), .CO(n5667), .S(n5669) );
NAND2X1TS U571 ( .A(n5517), .B(n5660), .Y(n2087) );
NAND2X1TS U572 ( .A(n3946), .B(n3945), .Y(n4322) );
INVX2TS U573 ( .A(n5517), .Y(n5673) );
ADDHXLTS U574 ( .A(n11320), .B(n9888), .CO(n10244), .S(n10224) );
NOR2X1TS U575 ( .A(n3944), .B(n3943), .Y(n4331) );
NOR2X1TS U576 ( .A(n4594), .B(n4595), .Y(n9136) );
OAI2BB1X2TS U577 ( .A0N(n4694), .A1N(n994), .B0(n993), .Y(n4717) );
NAND2BXLTS U578 ( .AN(n5668), .B(n5660), .Y(n772) );
ADDHXLTS U579 ( .A(n11321), .B(n9905), .CO(n10223), .S(n10214) );
OAI2BB1X1TS U580 ( .A0N(n5314), .A1N(n5313), .B0(n657), .Y(n9574) );
NAND2X1TS U581 ( .A(n2781), .B(n2780), .Y(n2799) );
INVX3TS U582 ( .A(n8424), .Y(n7108) );
NOR2X2TS U583 ( .A(n3122), .B(n3121), .Y(n3200) );
NAND2X1TS U584 ( .A(n2633), .B(n2632), .Y(n2734) );
NAND2BX1TS U585 ( .AN(n1121), .B(n3204), .Y(n6857) );
OAI2BB1X1TS U586 ( .A0N(n1409), .A1N(n1408), .B0(n4231), .Y(n1407) );
BUFX3TS U587 ( .A(n5311), .Y(n768) );
OAI21X2TS U588 ( .A0(n2132), .A1(n2131), .B0(n2130), .Y(n1615) );
OAI2BB1X1TS U589 ( .A0N(n342), .A1N(n345), .B0(n907), .Y(n6977) );
AO21X1TS U590 ( .A0(n10026), .A1(n10339), .B0(n10025), .Y(n10336) );
XOR2X1TS U591 ( .A(n3958), .B(n1192), .Y(n3967) );
NAND2BX1TS U592 ( .AN(n2657), .B(n1259), .Y(n1255) );
XOR2X2TS U593 ( .A(n6115), .B(n6116), .Y(n1269) );
CLKBUFX2TS U594 ( .A(n7106), .Y(n790) );
XNOR2X1TS U595 ( .A(n265), .B(n2743), .Y(n2733) );
OAI2BB1X1TS U596 ( .A0N(n340), .A1N(n343), .B0(n1144), .Y(n3157) );
ADDFHX1TS U597 ( .A(n2328), .B(n2327), .CI(n2326), .CO(n2458), .S(n2336) );
XOR2X1TS U598 ( .A(n6096), .B(n6095), .Y(n6150) );
OAI22X1TS U599 ( .A0(n5557), .A1(n584), .B0(n5556), .B1(n504), .Y(n5594) );
NAND2BX2TS U600 ( .AN(n4976), .B(n1040), .Y(n4346) );
OAI22X1TS U601 ( .A0(n5274), .A1(n576), .B0(n5278), .B1(n493), .Y(n5284) );
XOR2X1TS U602 ( .A(n4223), .B(n1200), .Y(n1199) );
XOR2X1TS U603 ( .A(n706), .B(n5558), .Y(n5593) );
ADDFHX1TS U604 ( .A(n2457), .B(n2456), .CI(n2455), .CO(n2508), .S(n2460) );
NAND2BX2TS U605 ( .AN(n1257), .B(n2700), .Y(n1256) );
ADDFX1TS U606 ( .A(n3961), .B(n3960), .CI(n3959), .CO(n3962), .S(n3949) );
XOR2X2TS U607 ( .A(n5312), .B(n659), .Y(n658) );
ADDFHX1TS U608 ( .A(n3552), .B(n3551), .CI(n3550), .CO(n3579), .S(n3559) );
ADDFHX2TS U609 ( .A(n2142), .B(n2141), .CI(n2140), .CO(n2364), .S(n2134) );
ADDFX1TS U610 ( .A(n5477), .B(n5476), .CI(n5475), .CO(n5970), .S(n5455) );
ADDFHX1TS U611 ( .A(n2910), .B(n2909), .CI(n2908), .CO(n3069), .S(n2886) );
CMPR32X2TS U612 ( .A(n3190), .B(n3189), .C(n3188), .CO(n3256), .S(n3241) );
ADDFX1TS U613 ( .A(n3269), .B(n3268), .CI(n3267), .CO(n3558), .S(n3300) );
ADDFHX1TS U614 ( .A(n3403), .B(n3402), .CI(n3401), .CO(n3395), .S(n3482) );
CMPR32X2TS U615 ( .A(n4438), .B(n4437), .C(n4436), .CO(n4522), .S(n4433) );
ADDFHX1TS U616 ( .A(n5652), .B(n5651), .CI(n5650), .CO(n5325), .S(n5865) );
AOI21X1TS U617 ( .A0(n2698), .A1(n2671), .B0(n2670), .Y(n2676) );
XOR2X1TS U618 ( .A(n2738), .B(n928), .Y(n1738) );
CMPR32X2TS U619 ( .A(n6073), .B(n6072), .C(n6071), .CO(n6096), .S(n6149) );
CMPR32X2TS U620 ( .A(n2354), .B(n2353), .C(n2352), .CO(n2386), .S(n2361) );
CMPR32X2TS U621 ( .A(n2482), .B(n2481), .C(n2480), .CO(n2572), .S(n2491) );
NOR2X1TS U622 ( .A(n5056), .B(n5075), .Y(n4336) );
ADDHXLTS U623 ( .A(n11318), .B(n10167), .CO(n10172), .S(n10175) );
ADDHXLTS U624 ( .A(n11325), .B(n9808), .CO(n10169), .S(n10135) );
NOR2X1TS U625 ( .A(n620), .B(n4446), .Y(n4761) );
OAI2BB1X1TS U626 ( .A0N(n1971), .A1N(n1970), .B0(n1127), .Y(n5561) );
ADDHXLTS U627 ( .A(n11314), .B(n10151), .CO(n10159), .S(n10173) );
CMPR32X2TS U628 ( .A(n2380), .B(n2379), .C(n2378), .CO(n2490), .S(n2387) );
CLKBUFX2TS U629 ( .A(n6494), .Y(n588) );
OAI2BB1X2TS U630 ( .A0N(n4859), .A1N(n4858), .B0(n4857), .Y(n5005) );
OAI21X1TS U631 ( .A0(n5313), .A1(n5314), .B0(n5312), .Y(n657) );
NOR2BX2TS U632 ( .AN(n2408), .B(n1317), .Y(n2534) );
OAI2BB1X1TS U633 ( .A0N(n759), .A1N(n758), .B0(n4381), .Y(n757) );
NAND2BX1TS U634 ( .AN(n1386), .B(n2051), .Y(n2226) );
CLKBUFX2TS U635 ( .A(n5194), .Y(n363) );
XOR2X1TS U636 ( .A(n6340), .B(n4125), .Y(n3954) );
XNOR2X1TS U637 ( .A(n2316), .B(n934), .Y(n2340) );
CLKXOR2X2TS U638 ( .A(n5512), .B(n5511), .Y(n5520) );
OAI22X1TS U639 ( .A0(n357), .A1(n6301), .B0(n598), .B1(n6374), .Y(n6378) );
OAI22X1TS U640 ( .A0(n5732), .A1(n582), .B0(n5689), .B1(n498), .Y(n5743) );
OAI22X1TS U641 ( .A0(n3265), .A1(n355), .B0(n3444), .B1(n391), .Y(n3551) );
XOR2X2TS U642 ( .A(n2131), .B(n2132), .Y(n1347) );
ADDFHX2TS U643 ( .A(n2322), .B(n2321), .CI(n2320), .CO(n2338), .S(n2339) );
OAI22X1TS U644 ( .A0(n4831), .A1(n586), .B0(n4950), .B1(n472), .Y(n4953) );
XNOR2X2TS U645 ( .A(n640), .B(n5735), .Y(n6003) );
XNOR2X1TS U646 ( .A(n1498), .B(n3140), .Y(n1514) );
ADDFHX1TS U647 ( .A(n4277), .B(n4276), .CI(n4275), .CO(n4434), .S(n4284) );
ADDFX2TS U648 ( .A(n4257), .B(n4256), .CI(n4255), .CO(n4283), .S(n4264) );
CMPR32X2TS U649 ( .A(n6089), .B(n6088), .C(n6087), .CO(n6152), .S(n6144) );
XOR2X1TS U650 ( .A(n4492), .B(n4493), .Y(n1549) );
ADDFX1TS U651 ( .A(n4272), .B(n4271), .CI(n4270), .CO(n4432), .S(n4282) );
XNOR2X1TS U652 ( .A(n2681), .B(n2680), .Y(n2653) );
XOR2X1TS U653 ( .A(n3675), .B(n820), .Y(n3167) );
XOR2X1TS U654 ( .A(n3695), .B(n908), .Y(n3169) );
XOR2X1TS U655 ( .A(n3647), .B(n1145), .Y(n2859) );
CMPR32X2TS U656 ( .A(n4262), .B(n4261), .C(n4260), .CO(n4270), .S(n4250) );
CMPR32X2TS U657 ( .A(n4246), .B(n4245), .C(n4244), .CO(n4249), .S(n4228) );
NAND2XLTS U658 ( .A(n1999), .B(n1997), .Y(n152) );
NAND2X1TS U659 ( .A(n4659), .B(n4644), .Y(n9151) );
INVX3TS U660 ( .A(n3102), .Y(n2953) );
INVX2TS U661 ( .A(n1464), .Y(n609) );
INVX2TS U662 ( .A(n1598), .Y(n540) );
NOR2X1TS U663 ( .A(n2525), .B(n2497), .Y(n9097) );
OAI2BB1X1TS U664 ( .A0N(n5753), .A1N(n5752), .B0(n784), .Y(n5797) );
OAI2BB1X1TS U665 ( .A0N(n1684), .A1N(n4644), .B0(n4680), .Y(n1681) );
AO21XLTS U666 ( .A0(n9896), .A1(n9895), .B0(n9894), .Y(n9897) );
NAND2X1TS U667 ( .A(n3467), .B(n2596), .Y(n2920) );
AOI2BB1XLTS U668 ( .A0N(n10141), .A1N(n10155), .B0(n10140), .Y(n10142) );
OAI21X1TS U669 ( .A0(n1793), .A1(n1794), .B0(n1792), .Y(n1571) );
INVX2TS U670 ( .A(n6826), .Y(n577) );
OAI2BB1X1TS U671 ( .A0N(n5737), .A1N(n5736), .B0(n1416), .Y(n6795) );
XOR2X1TS U672 ( .A(n5600), .B(n5601), .Y(n667) );
NAND2BX2TS U673 ( .AN(n1154), .B(n2806), .Y(n2919) );
XOR2X1TS U674 ( .A(n1820), .B(n912), .Y(n1833) );
XNOR2X2TS U675 ( .A(n5736), .B(n5737), .Y(n640) );
XOR2X2TS U676 ( .A(n4068), .B(n4069), .Y(n925) );
OAI22X1TS U677 ( .A0(n4619), .A1(n592), .B0(n4618), .B1(n6162), .Y(n4696) );
BUFX4TS U678 ( .A(n8424), .Y(n436) );
AOI21X1TS U679 ( .A0(n4992), .A1(n4842), .B0(n4841), .Y(n4843) );
OAI22X1TS U680 ( .A0(n2485), .A1(n2484), .B0(n603), .B1(n268), .Y(n2569) );
ADDFHX1TS U681 ( .A(n4627), .B(n4626), .CI(n4625), .CO(n4591), .S(n4704) );
ADDFHX2TS U682 ( .A(n2111), .B(n2110), .CI(n2109), .CO(n2136), .S(n2131) );
XOR2X2TS U683 ( .A(n1453), .B(n2128), .Y(n2132) );
OAI21XLTS U684 ( .A0(n344), .A1(n341), .B0(n3675), .Y(n819) );
XNOR2X1TS U685 ( .A(n5532), .B(n403), .Y(n5323) );
ADDFHX2TS U686 ( .A(n4193), .B(n4192), .CI(n4191), .CO(n4803), .S(n4594) );
XNOR2X1TS U687 ( .A(n6757), .B(n415), .Y(n5316) );
ADDHX1TS U688 ( .A(n2960), .B(n2959), .CO(n3531), .S(n3529) );
XOR2X1TS U689 ( .A(n3609), .B(n723), .Y(n2779) );
CMPR32X2TS U690 ( .A(n2211), .B(n2210), .C(n2209), .CO(n2222), .S(n2223) );
NOR2X1TS U691 ( .A(n6340), .B(n4125), .Y(n3828) );
CMPR32X2TS U692 ( .A(n4218), .B(n4217), .C(n4216), .CO(n4232), .S(n4211) );
OAI2BB1X2TS U693 ( .A0N(n5592), .A1N(n5591), .B0(n1377), .Y(n5634) );
OAI2BB1X1TS U694 ( .A0N(n4007), .A1N(n4006), .B0(n1022), .Y(n4032) );
NOR2X1TS U695 ( .A(n623), .B(n2483), .Y(n6710) );
BUFX3TS U696 ( .A(n3473), .Y(n607) );
INVX2TS U697 ( .A(n8424), .Y(n500) );
INVX2TS U698 ( .A(n7783), .Y(n6833) );
NOR2X1TS U699 ( .A(n624), .B(n2349), .Y(n2482) );
AO21XLTS U700 ( .A0(n9876), .A1(n9895), .B0(n9875), .Y(n9877) );
CLKBUFX2TS U701 ( .A(n6732), .Y(n581) );
AO21XLTS U702 ( .A0(n9866), .A1(n9895), .B0(n9865), .Y(n9867) );
AO21XLTS U703 ( .A0(n9856), .A1(n9895), .B0(n9855), .Y(n9857) );
NAND2XLTS U704 ( .A(n3090), .B(n3097), .Y(n3100) );
OAI2BB1X1TS U705 ( .A0N(n1858), .A1N(n1857), .B0(n1270), .Y(n2497) );
OAI2BB1X2TS U706 ( .A0N(n1504), .A1N(n5552), .B0(n1503), .Y(n5558) );
OAI2BB1X2TS U707 ( .A0N(n722), .A1N(n6079), .B0(n3609), .Y(n721) );
XOR2X1TS U708 ( .A(n1821), .B(n1822), .Y(n912) );
OAI21X1TS U709 ( .A0(n5736), .A1(n5737), .B0(n5735), .Y(n1416) );
OAI21X2TS U710 ( .A0(n2609), .A1(n2738), .B0(n2608), .Y(n2715) );
XOR2X1TS U711 ( .A(n2127), .B(n2129), .Y(n1453) );
XOR2X2TS U712 ( .A(n5591), .B(n5592), .Y(n1378) );
OAI22X1TS U713 ( .A0(n2454), .A1(n498), .B0(n2299), .B1(n583), .Y(n2427) );
OAI22X1TS U714 ( .A0(n582), .A1(n972), .B0(n2298), .B1(n499), .Y(n2305) );
XNOR2X1TS U715 ( .A(n1271), .B(n1856), .Y(n2423) );
ADDFHX1TS U716 ( .A(n4828), .B(n4827), .CI(n4826), .CO(n4964), .S(n4802) );
NAND2X1TS U717 ( .A(Data_B_i[41]), .B(Data_B_i[14]), .Y(n2654) );
ADDFHX1TS U718 ( .A(n1950), .B(n1949), .CI(n1948), .CO(n5738), .S(n2525) );
ADDFHX1TS U719 ( .A(n2163), .B(n2162), .CI(n2161), .CO(n2216), .S(n2224) );
XOR2X2TS U720 ( .A(n915), .B(n4174), .Y(n4485) );
NAND3X1TS U721 ( .A(n1140), .B(n1139), .C(n229), .Y(n2655) );
OAI22X1TS U722 ( .A0(n4461), .A1(n593), .B0(n4619), .B1(n481), .Y(n4693) );
ADDFHX1TS U723 ( .A(n5246), .B(n5245), .CI(n5244), .CO(n5380), .S(n5240) );
ADDFHX1TS U724 ( .A(n4205), .B(n4204), .CI(n4203), .CO(n4229), .S(n4219) );
XNOR2X1TS U725 ( .A(n3437), .B(n7145), .Y(n3438) );
ADDFHX2TS U726 ( .A(n1996), .B(n1995), .CI(n1994), .CO(n2109), .S(n2002) );
CMPR32X2TS U727 ( .A(n5231), .B(n5230), .C(n5229), .CO(n5241), .S(n5300) );
ADDFHX1TS U728 ( .A(n6103), .B(n6102), .CI(n6101), .CO(n6310), .S(n6109) );
ADDFX1TS U729 ( .A(n5249), .B(n5248), .CI(n5247), .CO(n5379), .S(n5242) );
XNOR2X1TS U730 ( .A(n6038), .B(n297), .Y(n6039) );
ADDFHX2TS U731 ( .A(n3924), .B(n3923), .CI(n3922), .CO(n3914), .S(n3932) );
XNOR2X1TS U732 ( .A(n519), .B(Data_A_i[40]), .Y(n6712) );
ADDFHX2TS U733 ( .A(n2297), .B(n2296), .CI(n2295), .CO(n2416), .S(n2318) );
CMPR32X2TS U734 ( .A(n2044), .B(n2043), .C(n2042), .CO(n2162), .S(n2054) );
INVX6TS U735 ( .A(n1217), .Y(n8424) );
INVX2TS U736 ( .A(n6826), .Y(n576) );
XOR2X1TS U737 ( .A(n3858), .B(n1288), .Y(n6341) );
AO21XLTS U738 ( .A0(n9806), .A1(n9895), .B0(n9805), .Y(n9807) );
AO21XLTS U739 ( .A0(n9815), .A1(n9895), .B0(n9814), .Y(n9816) );
OAI2BB1X1TS U740 ( .A0N(n672), .A1N(n671), .B0(n5696), .Y(n670) );
NAND2X1TS U741 ( .A(n1736), .B(n1737), .Y(n1139) );
OAI21X1TS U742 ( .A0(n5591), .A1(n5592), .B0(n5590), .Y(n1377) );
NAND2X2TS U743 ( .A(n2817), .B(n2818), .Y(n3634) );
XOR2X1TS U744 ( .A(n4023), .B(n4024), .Y(n1552) );
NOR2BX1TS U745 ( .AN(n2159), .B(n5984), .Y(n2207) );
NOR2X1TS U746 ( .A(Data_A_i[52]), .B(n297), .Y(n6915) );
NAND2BXLTS U747 ( .AN(n974), .B(n1643), .Y(n973) );
OAI21X1TS U748 ( .A0(n1857), .A1(n1858), .B0(n1856), .Y(n1270) );
XNOR2X2TS U749 ( .A(n4506), .B(n4507), .Y(n1209) );
AO21X1TS U750 ( .A0(n9845), .A1(n9751), .B0(n9842), .Y(n9763) );
OAI22X1TS U751 ( .A0(n5575), .A1(n5221), .B0(n600), .B1(n5220), .Y(n5230) );
NOR2X1TS U752 ( .A(Data_A_i[50]), .B(Data_A_i[23]), .Y(n3313) );
OAI22X1TS U753 ( .A0(n6520), .A1(n4813), .B0(n533), .B1(n4970), .Y(n4959) );
XOR2X2TS U754 ( .A(n2259), .B(n2258), .Y(n5640) );
XOR2X2TS U755 ( .A(n2251), .B(n2250), .Y(n5688) );
ADDFHX1TS U756 ( .A(n5259), .B(n5258), .CI(n1338), .CO(n5252), .S(n5504) );
ADDFHX1TS U757 ( .A(n5135), .B(n5134), .CI(n5133), .CO(n5303), .S(n5267) );
NAND2X1TS U758 ( .A(Data_A_i[49]), .B(Data_A_i[22]), .Y(n3312) );
ADDFHX1TS U759 ( .A(n5138), .B(n5255), .CI(n5137), .CO(n5297), .S(n5253) );
XNOR2X1TS U760 ( .A(n4856), .B(n4855), .Y(n1309) );
ADDFX1TS U761 ( .A(n2120), .B(n2119), .CI(n2118), .CO(n2137), .S(n2127) );
CMPR32X2TS U762 ( .A(n1987), .B(n1986), .C(n1985), .CO(n2111), .S(n1999) );
CMPR32X2TS U763 ( .A(n1931), .B(n1930), .C(n1929), .CO(n1963), .S(n1971) );
NAND2X1TS U764 ( .A(n3903), .B(n4823), .Y(n5024) );
CMPR32X2TS U765 ( .A(n1902), .B(n1901), .C(n1900), .CO(n2173), .S(n2169) );
INVX2TS U766 ( .A(n6491), .Y(n534) );
BUFX3TS U767 ( .A(n2815), .Y(n3635) );
OAI2BB1X1TS U768 ( .A0N(n4189), .A1N(n4190), .B0(n1035), .Y(n1034) );
OAI2BB1X1TS U769 ( .A0N(n4054), .A1N(n871), .B0(n869), .Y(n4051) );
NOR2BX1TS U770 ( .AN(n5497), .B(n5581), .Y(n2290) );
NAND2X1TS U771 ( .A(n3130), .B(n3160), .Y(n3131) );
NAND2X1TS U772 ( .A(n3389), .B(n3388), .Y(n3390) );
OAI2BB1X1TS U773 ( .A0N(n1766), .A1N(n1765), .B0(n703), .Y(n1796) );
OAI2BB1X1TS U774 ( .A0N(n712), .A1N(Data_B_i[43]), .B0(n1069), .Y(n2626) );
OR2X1TS U775 ( .A(n2035), .B(n2034), .Y(n2189) );
INVX4TS U776 ( .A(n1464), .Y(n3715) );
XNOR2X2TS U777 ( .A(n4112), .B(n4111), .Y(n860) );
OAI2BB1X2TS U778 ( .A0N(n1292), .A1N(n1293), .B0(n1291), .Y(n6331) );
XNOR2X1TS U779 ( .A(n4195), .B(n4196), .Y(n1260) );
BUFX3TS U780 ( .A(n5686), .Y(n1316) );
OAI22X1TS U781 ( .A0(n249), .A1(n5142), .B0(n600), .B1(n5141), .Y(n5258) );
XOR2X1TS U782 ( .A(n3779), .B(n1441), .Y(n4128) );
XNOR2X1TS U783 ( .A(n866), .B(n4113), .Y(n4129) );
INVX2TS U784 ( .A(n6313), .Y(n590) );
ADDFHX1TS U785 ( .A(n1992), .B(n1813), .CI(n1812), .CO(n1996), .S(n1832) );
AOI21X1TS U786 ( .A0(n2256), .A1(n2255), .B0(n2254), .Y(n2259) );
ADDFHX1TS U787 ( .A(n1855), .B(n1854), .CI(n1853), .CO(n1949), .S(n1856) );
NAND2X1TS U788 ( .A(Data_A_i[48]), .B(Data_A_i[21]), .Y(n3092) );
NOR2X2TS U789 ( .A(n1737), .B(n3120), .Y(n1138) );
AOI21X1TS U790 ( .A0(n2256), .A1(n2439), .B0(n2444), .Y(n2251) );
AOI21X1TS U791 ( .A0(n5186), .A1(n5185), .B0(n5184), .Y(n979) );
ADDFHX1TS U792 ( .A(n3810), .B(n3809), .CI(n3808), .CO(n4125), .S(n4123) );
CMPR32X2TS U793 ( .A(n1942), .B(n1943), .C(n1941), .CO(n1965), .S(n1960) );
XNOR2X1TS U794 ( .A(n523), .B(Data_A_i[17]), .Y(n4969) );
ADDFX1TS U795 ( .A(n1899), .B(n1898), .CI(n1897), .CO(n2281), .S(n2198) );
XOR2X1TS U796 ( .A(Data_B_i[18]), .B(Data_B_i[45]), .Y(n2684) );
NOR2X1TS U797 ( .A(n4813), .B(n604), .Y(n3838) );
CMPR32X2TS U798 ( .A(n5502), .B(n5501), .C(n5500), .CO(n5534), .S(n5565) );
NAND2X1TS U799 ( .A(n4852), .B(n4851), .Y(n4977) );
NAND2X1TS U800 ( .A(n1133), .B(n3380), .Y(n1132) );
NAND2X1TS U801 ( .A(n2772), .B(n2770), .Y(n2754) );
NAND2XLTS U802 ( .A(n2852), .B(n2851), .Y(n2853) );
BUFX4TS U803 ( .A(n6416), .Y(n6300) );
INVX4TS U804 ( .A(n5639), .Y(n446) );
NAND2X1TS U805 ( .A(n811), .B(n1060), .Y(n1472) );
OAI2BB1X1TS U806 ( .A0N(n1439), .A1N(n1070), .B0(n2616), .Y(n1069) );
BUFX4TS U807 ( .A(n3437), .Y(n1063) );
OAI2BB1X2TS U808 ( .A0N(n1287), .A1N(n233), .B0(n3858), .Y(n1291) );
OAI2BB1X1TS U809 ( .A0N(n5265), .A1N(n5264), .B0(n799), .Y(n5483) );
NOR2X1TS U810 ( .A(n3349), .B(n3355), .Y(n1731) );
OAI22X1TS U811 ( .A0(n4444), .A1(n4002), .B0(n4531), .B1(n3992), .Y(n3977)
);
NAND2X1TS U812 ( .A(Data_A_i[41]), .B(Data_A_i[14]), .Y(n2669) );
OAI22X1TS U813 ( .A0(n4240), .A1(n4091), .B0(n599), .B1(n4090), .Y(n4108) );
NOR2X1TS U814 ( .A(Data_A_i[46]), .B(Data_A_i[19]), .Y(n2875) );
AOI21X2TS U815 ( .A0(n2256), .A1(n2185), .B0(n2181), .Y(n2184) );
XNOR2X2TS U816 ( .A(n2256), .B(n2186), .Y(n5627) );
XNOR2X2TS U817 ( .A(n2721), .B(n2720), .Y(n2813) );
XNOR2X2TS U818 ( .A(n3814), .B(n3799), .Y(n6057) );
OAI22X1TS U819 ( .A0(n4823), .A1(n4556), .B0(n4599), .B1(n4821), .Y(n4598)
);
ADDFHX1TS U820 ( .A(n1928), .B(n1927), .CI(n1926), .CO(n1932), .S(n1950) );
NAND2X1TS U821 ( .A(Data_A_i[43]), .B(Data_A_i[16]), .Y(n2693) );
ADDFHX1TS U822 ( .A(n4484), .B(n4483), .CI(n4482), .CO(n4635), .S(n4507) );
NOR2BX1TS U823 ( .AN(n5497), .B(n5568), .Y(n8073) );
NOR2X2TS U824 ( .A(Data_A_i[42]), .B(Data_A_i[15]), .Y(n2672) );
CMPR32X2TS U825 ( .A(n11346), .B(n146), .C(n11347), .CO(n10014), .S(n9935)
);
INVX2TS U826 ( .A(n1172), .Y(n571) );
BUFX6TS U827 ( .A(n2576), .Y(n2485) );
INVX2TS U828 ( .A(n522), .Y(n523) );
NAND2X1TS U829 ( .A(n11597), .B(n11599), .Y(n10275) );
NOR2X1TS U830 ( .A(n624), .B(n1825), .Y(n1993) );
INVX4TS U831 ( .A(n1727), .Y(n3387) );
NOR2X1TS U832 ( .A(n4497), .B(n4496), .Y(n4498) );
NOR2X1TS U833 ( .A(n620), .B(n3973), .Y(n4202) );
INVX4TS U834 ( .A(n1431), .Y(n3629) );
CLKINVX2TS U835 ( .A(n4812), .Y(n6491) );
AOI2BB1X1TS U836 ( .A0N(n3380), .A1N(n3339), .B0(n3341), .Y(n3342) );
NOR2BX1TS U837 ( .AN(n4096), .B(n4531), .Y(n4106) );
INVX2TS U838 ( .A(n3792), .Y(n6047) );
CLKAND2X2TS U839 ( .A(n3761), .B(n3760), .Y(n158) );
AOI21X1TS U840 ( .A0(n11443), .A1(n11418), .B0(n11419), .Y(n9873) );
OAI21X1TS U841 ( .A0(n11582), .A1(n11583), .B0(n11584), .Y(n10281) );
AND2X2TS U842 ( .A(n2603), .B(n2602), .Y(n2761) );
OAI22X1TS U843 ( .A0(n351), .A1(n2435), .B0(n555), .B1(n2515), .Y(n2517) );
NOR2BX1TS U844 ( .AN(n4096), .B(n259), .Y(n4117) );
NAND2BX1TS U845 ( .AN(n3361), .B(n1131), .Y(n1130) );
XNOR2X2TS U846 ( .A(n4403), .B(n4404), .Y(n3775) );
CLKAND2X2TS U847 ( .A(n3359), .B(n3362), .Y(n180) );
AOI21X1TS U848 ( .A0(n4992), .A1(n4655), .B0(n4654), .Y(n4658) );
NAND2XLTS U849 ( .A(Data_B_i[26]), .B(Data_B_i[12]), .Y(n4851) );
NAND2BXLTS U850 ( .AN(n5497), .B(n665), .Y(n2007) );
AND2X2TS U851 ( .A(n3340), .B(n3382), .Y(n3343) );
CMPR32X2TS U852 ( .A(n1788), .B(n1787), .C(n1786), .CO(n1827), .S(n1791) );
XOR2X2TS U853 ( .A(n2728), .B(n2727), .Y(n3398) );
NOR2X1TS U854 ( .A(Data_A_i[40]), .B(Data_A_i[13]), .Y(n3355) );
OAI21X1TS U855 ( .A0(Data_B_i[26]), .A1(Data_B_i[12]), .B0(Data_B_i[11]),
.Y(n4852) );
NOR2X1TS U856 ( .A(n11596), .B(n11589), .Y(n10274) );
INVX2TS U857 ( .A(n5577), .Y(n555) );
BUFX3TS U858 ( .A(n5041), .Y(n6040) );
BUFX3TS U859 ( .A(n6764), .Y(n143) );
INVX2TS U860 ( .A(n373), .Y(n374) );
NOR2X1TS U861 ( .A(n622), .B(n1770), .Y(n2114) );
NAND2XLTS U862 ( .A(n2726), .B(n2725), .Y(n2728) );
NAND2X1TS U863 ( .A(n4403), .B(n4404), .Y(n1566) );
INVX4TS U864 ( .A(n619), .Y(n620) );
BUFX4TS U865 ( .A(n4209), .Y(n144) );
CLKBUFX2TS U866 ( .A(n174), .Y(n275) );
INVX2TS U867 ( .A(n1454), .Y(n596) );
NAND2X1TS U868 ( .A(n4667), .B(n4673), .Y(n4984) );
NOR2BX1TS U869 ( .AN(n4096), .B(n4881), .Y(n4061) );
AND2X2TS U870 ( .A(n6825), .B(n1374), .Y(n6826) );
BUFX3TS U871 ( .A(n5583), .Y(n634) );
AOI21X2TS U872 ( .A0(n1734), .A1(n3363), .B0(n1213), .Y(n3380) );
AOI21X2TS U873 ( .A0(n2445), .A1(n2444), .B0(n2443), .Y(n980) );
NOR2X1TS U874 ( .A(n298), .B(Data_A_i[12]), .Y(n4983) );
NAND2X1TS U875 ( .A(n315), .B(Data_A_i[37]), .Y(n5188) );
NOR2X1TS U876 ( .A(Data_A_i[39]), .B(Data_A_i[12]), .Y(n3349) );
NOR2BX1TS U877 ( .AN(n1188), .B(n1205), .Y(n1187) );
OR2X2TS U878 ( .A(n4570), .B(n276), .Y(n185) );
NAND2BXLTS U879 ( .AN(n2039), .B(n2659), .Y(n2040) );
XOR2X1TS U880 ( .A(n4662), .B(n4847), .Y(n1308) );
XNOR2X1TS U881 ( .A(n5530), .B(n425), .Y(n5563) );
OAI22X1TS U882 ( .A0(n250), .A1(n5486), .B0(n601), .B1(n5142), .Y(n5263) );
XNOR2X2TS U883 ( .A(n4664), .B(n4663), .Y(n4582) );
XNOR2X2TS U884 ( .A(n2902), .B(n2587), .Y(n936) );
INVX2TS U885 ( .A(Data_B_i[27]), .Y(n541) );
INVX6TS U886 ( .A(n1454), .Y(n2148) );
BUFX3TS U887 ( .A(n6760), .Y(n983) );
INVX2TS U888 ( .A(Data_B_i[14]), .Y(n4821) );
INVX2TS U889 ( .A(n346), .Y(n347) );
BUFX4TS U890 ( .A(n5581), .Y(n1367) );
INVX2TS U891 ( .A(n1607), .Y(n6303) );
INVX4TS U892 ( .A(n335), .Y(n336) );
INVX2TS U893 ( .A(n7735), .Y(n624) );
INVX4TS U894 ( .A(n913), .Y(n6415) );
INVX4TS U895 ( .A(n1557), .Y(n4881) );
INVX2TS U896 ( .A(n1205), .Y(n532) );
INVX2TS U897 ( .A(n1740), .Y(n2383) );
INVX2TS U898 ( .A(n7735), .Y(n623) );
CLKAND2X2TS U899 ( .A(n4576), .B(n4575), .Y(n231) );
NOR2XLTS U900 ( .A(n4666), .B(n4670), .Y(n4673) );
NAND2X1TS U901 ( .A(n329), .B(n1565), .Y(n1564) );
NOR2X1TS U902 ( .A(Data_B_i[1]), .B(Data_B_i[15]), .Y(n3801) );
BUFX4TS U903 ( .A(n6725), .Y(n686) );
NAND2X2TS U904 ( .A(n992), .B(n1025), .Y(n4531) );
BUFX4TS U905 ( .A(Data_B_i[21]), .Y(n238) );
AOI21X2TS U906 ( .A0(n2902), .A1(n2894), .B0(n2896), .Y(n1493) );
AOI21X2TS U907 ( .A0(n2843), .A1(n1090), .B0(n1088), .Y(n1087) );
NAND2X2TS U908 ( .A(n4581), .B(n1312), .Y(n4663) );
OAI21X2TS U909 ( .A0(n3162), .A1(n3160), .B0(n3163), .Y(n3372) );
OAI21X1TS U910 ( .A0(n1568), .A1(n1567), .B0(n3767), .Y(n4403) );
NAND2X2TS U911 ( .A(n1090), .B(n2841), .Y(n1089) );
XNOR2X2TS U912 ( .A(Data_B_i[7]), .B(Data_B_i[21]), .Y(n4404) );
XNOR2X2TS U913 ( .A(n4578), .B(n4574), .Y(n4577) );
XNOR2X2TS U914 ( .A(Data_B_i[11]), .B(Data_B_i[25]), .Y(n4664) );
INVX4TS U915 ( .A(Data_B_i[25]), .Y(n522) );
XOR2X2TS U916 ( .A(Data_B_i[32]), .B(Data_B_i[31]), .Y(n1744) );
INVX2TS U917 ( .A(n508), .Y(n509) );
BUFX2TS U918 ( .A(Data_B_i[48]), .Y(n5223) );
BUFX2TS U919 ( .A(Data_A_i[2]), .Y(n746) );
INVX2TS U920 ( .A(n303), .Y(n304) );
INVX2TS U921 ( .A(Data_B_i[41]), .Y(n5568) );
INVX2TS U922 ( .A(n258), .Y(n259) );
INVX4TS U923 ( .A(n906), .Y(n7736) );
INVX2TS U924 ( .A(n4813), .Y(n4600) );
CLKBUFX2TS U925 ( .A(Data_A_i[3]), .Y(n282) );
NAND2X1TS U926 ( .A(n2622), .B(n2621), .Y(n2623) );
INVX4TS U927 ( .A(n1436), .Y(n524) );
NAND2XLTS U928 ( .A(n2028), .B(n2179), .Y(n2029) );
INVX4TS U929 ( .A(n335), .Y(n4967) );
NOR2X1TS U930 ( .A(n3175), .B(n3177), .Y(n3359) );
BUFX3TS U931 ( .A(n4156), .Y(n1389) );
NOR2X1TS U932 ( .A(Data_B_i[9]), .B(Data_B_i[23]), .Y(n4574) );
NAND2X2TS U933 ( .A(n992), .B(n1025), .Y(n573) );
NOR2X1TS U934 ( .A(Data_A_i[50]), .B(Data_A_i[36]), .Y(n5157) );
NAND2X1TS U935 ( .A(Data_B_i[37]), .B(Data_B_i[10]), .Y(n3360) );
NAND2BXLTS U936 ( .AN(n971), .B(n2020), .Y(n970) );
CLKBUFX2TS U937 ( .A(Data_A_i[15]), .Y(n290) );
NOR2X1TS U938 ( .A(Data_A_i[25]), .B(Data_A_i[11]), .Y(n4670) );
NOR2X1TS U939 ( .A(Data_B_i[20]), .B(Data_B_i[6]), .Y(n1568) );
BUFX6TS U940 ( .A(Data_A_i[42]), .Y(n685) );
CLKINVX3TS U941 ( .A(n508), .Y(n619) );
NAND2X1TS U942 ( .A(Data_B_i[24]), .B(Data_B_i[10]), .Y(n4581) );
NOR2X2TS U943 ( .A(n3364), .B(n1169), .Y(n1734) );
NOR2X2TS U944 ( .A(n2753), .B(n2773), .Y(n2841) );
NAND2X1TS U945 ( .A(Data_A_i[37]), .B(Data_A_i[10]), .Y(n3369) );
INVX2TS U946 ( .A(Data_B_i[23]), .Y(n513) );
NOR2X6TS U947 ( .A(Data_A_i[36]), .B(Data_A_i[9]), .Y(n3162) );
BUFX3TS U948 ( .A(Data_A_i[0]), .Y(n4096) );
NOR2X1TS U949 ( .A(Data_A_i[49]), .B(Data_A_i[35]), .Y(n5154) );
INVX4TS U950 ( .A(Data_B_i[21]), .Y(n329) );
NOR2X4TS U951 ( .A(Data_A_i[35]), .B(Data_A_i[8]), .Y(n3161) );
OAI21X1TS U952 ( .A0(n4648), .A1(n4647), .B0(n4646), .Y(n4672) );
XNOR2X1TS U953 ( .A(n256), .B(Data_A_i[1]), .Y(n4144) );
NAND2X2TS U954 ( .A(Data_A_i[8]), .B(Data_A_i[35]), .Y(n3160) );
XNOR2X2TS U955 ( .A(Data_B_i[1]), .B(Data_B_i[15]), .Y(n3802) );
NOR2X2TS U956 ( .A(Data_A_i[38]), .B(Data_A_i[11]), .Y(n3375) );
OAI21X1TS U957 ( .A0(Data_B_i[16]), .A1(Data_B_i[2]), .B0(n241), .Y(n3748)
);
XNOR2X2TS U958 ( .A(n1268), .B(Data_B_i[30]), .Y(n1267) );
NAND4X2TS U959 ( .A(n959), .B(n958), .C(n956), .D(n955), .Y(n961) );
XOR2X1TS U960 ( .A(Data_B_i[24]), .B(Data_B_i[10]), .Y(n4578) );
XNOR2X1TS U961 ( .A(Data_B_i[30]), .B(Data_B_i[44]), .Y(n2166) );
CLKXOR2X2TS U962 ( .A(Data_B_i[46]), .B(Data_B_i[45]), .Y(n2201) );
XOR2X1TS U963 ( .A(Data_B_i[12]), .B(Data_B_i[13]), .Y(n1558) );
INVX2TS U964 ( .A(n1565), .Y(n322) );
INVX2TS U965 ( .A(n4772), .Y(n575) );
INVX6TS U966 ( .A(n1438), .Y(n476) );
BUFX6TS U967 ( .A(Data_B_i[16]), .Y(n712) );
INVX3TS U968 ( .A(n4031), .Y(n512) );
CLKINVX6TS U969 ( .A(Data_B_i[43]), .Y(n1439) );
CLKINVX2TS U970 ( .A(n1027), .Y(n992) );
INVX4TS U971 ( .A(n5042), .Y(n254) );
NOR2X1TS U972 ( .A(n3798), .B(n3815), .Y(n4394) );
INVX2TS U973 ( .A(n4444), .Y(n364) );
CLKINVX3TS U974 ( .A(Data_B_i[35]), .Y(n1614) );
CLKINVX6TS U975 ( .A(Data_B_i[17]), .Y(n335) );
INVX2TS U976 ( .A(Data_B_i[14]), .Y(n3728) );
CLKBUFX2TS U977 ( .A(Data_A_i[6]), .Y(n284) );
BUFX3TS U978 ( .A(Data_A_i[31]), .Y(n694) );
NOR2X1TS U979 ( .A(Data_A_i[48]), .B(Data_A_i[34]), .Y(n2442) );
NOR2X4TS U980 ( .A(Data_A_i[30]), .B(Data_A_i[3]), .Y(n2717) );
NAND2X1TS U981 ( .A(Data_A_i[43]), .B(Data_A_i[29]), .Y(n2179) );
NAND2X1TS U982 ( .A(Data_A_i[34]), .B(Data_A_i[7]), .Y(n2851) );
INVX2TS U983 ( .A(Data_B_i[41]), .Y(n2031) );
INVX4TS U984 ( .A(Data_B_i[44]), .Y(n1436) );
NAND2X4TS U985 ( .A(Data_A_i[29]), .B(Data_A_i[2]), .Y(n2725) );
INVX4TS U986 ( .A(n510), .Y(n511) );
INVX2TS U987 ( .A(Data_B_i[30]), .Y(n1982) );
OAI21X1TS U988 ( .A0(n2903), .A1(n2897), .B0(n2904), .Y(n1593) );
NOR2X2TS U989 ( .A(Data_B_i[38]), .B(Data_B_i[11]), .Y(n3364) );
NAND2X2TS U990 ( .A(Data_A_i[30]), .B(Data_A_i[3]), .Y(n2718) );
NOR2X2TS U991 ( .A(Data_B_i[36]), .B(Data_B_i[9]), .Y(n3177) );
BUFX4TS U992 ( .A(Data_B_i[40]), .Y(n7735) );
XNOR2X1TS U993 ( .A(Data_B_i[36]), .B(Data_B_i[50]), .Y(n5200) );
NOR2X2TS U994 ( .A(Data_A_i[23]), .B(Data_A_i[9]), .Y(n4648) );
NAND2X1TS U995 ( .A(Data_A_i[22]), .B(Data_A_i[8]), .Y(n4647) );
INVX2TS U996 ( .A(Data_B_i[13]), .Y(n508) );
NOR2X2TS U997 ( .A(Data_A_i[45]), .B(Data_A_i[31]), .Y(n2245) );
NOR2X1TS U998 ( .A(Data_B_i[35]), .B(Data_B_i[8]), .Y(n3175) );
NOR2X1TS U999 ( .A(n3751), .B(n3739), .Y(n1641) );
INVX4TS U1000 ( .A(Data_B_i[19]), .Y(n6083) );
NAND2X1TS U1001 ( .A(Data_B_i[33]), .B(Data_B_i[6]), .Y(n2897) );
BUFX3TS U1002 ( .A(Data_A_i[0]), .Y(n276) );
NOR2X1TS U1003 ( .A(Data_A_i[18]), .B(Data_A_i[4]), .Y(n3798) );
INVX2TS U1004 ( .A(Data_B_i[18]), .Y(n2588) );
INVX2TS U1005 ( .A(Data_B_i[27]), .Y(n1920) );
NOR2X2TS U1006 ( .A(Data_A_i[19]), .B(Data_A_i[5]), .Y(n3815) );
INVX2TS U1007 ( .A(Data_A_i[25]), .Y(n296) );
BUFX3TS U1008 ( .A(Data_B_i[50]), .Y(n5203) );
BUFX3TS U1009 ( .A(Data_A_i[8]), .Y(n4445) );
NAND2X2TS U1010 ( .A(Data_A_i[28]), .B(Data_A_i[42]), .Y(n2023) );
NOR2X2TS U1011 ( .A(Data_A_i[20]), .B(Data_A_i[6]), .Y(n4393) );
INVX4TS U1012 ( .A(Data_B_i[42]), .Y(n1438) );
XOR2X1TS U1013 ( .A(Data_B_i[51]), .B(Data_B_i[37]), .Y(n5204) );
CLKINVX6TS U1014 ( .A(Data_B_i[2]), .Y(n1391) );
CLKINVX6TS U1015 ( .A(Data_B_i[4]), .Y(n1545) );
NAND2X1TS U1016 ( .A(Data_A_i[16]), .B(Data_A_i[2]), .Y(n3752) );
INVX8TS U1017 ( .A(Data_B_i[28]), .Y(n510) );
NAND2X2TS U1018 ( .A(n1025), .B(n1026), .Y(n1024) );
NAND2X2TS U1019 ( .A(n4087), .B(Data_A_i[15]), .Y(n3771) );
NOR2X2TS U1020 ( .A(n1026), .B(Data_B_i[11]), .Y(n1632) );
INVX4TS U1021 ( .A(Data_B_i[1]), .Y(n252) );
INVX4TS U1022 ( .A(Data_B_i[0]), .Y(n542) );
NOR2X2TS U1023 ( .A(Data_A_i[17]), .B(Data_A_i[3]), .Y(n3739) );
BUFX6TS U1024 ( .A(Data_A_i[1]), .Y(n4087) );
INVX12TS U1025 ( .A(Data_B_i[5]), .Y(n1567) );
INVX4TS U1026 ( .A(n4813), .Y(n4570) );
CLKINVX3TS U1027 ( .A(Data_B_i[10]), .Y(n1633) );
INVX4TS U1028 ( .A(Data_B_i[11]), .Y(n1631) );
NAND2X4TS U1029 ( .A(Data_B_i[7]), .B(Data_B_i[8]), .Y(n1025) );
INVX6TS U1030 ( .A(Data_A_i[14]), .Y(n4813) );
INVX2TS U1031 ( .A(n147), .Y(n112) );
INVX2TS U1032 ( .A(n112), .Y(n113) );
INVX2TS U1033 ( .A(n112), .Y(n114) );
INVX2TS U1034 ( .A(n148), .Y(n115) );
INVX2TS U1035 ( .A(n115), .Y(n116) );
INVX2TS U1036 ( .A(n115), .Y(n117) );
INVX2TS U1037 ( .A(n150), .Y(n118) );
INVX2TS U1038 ( .A(n118), .Y(n119) );
INVX2TS U1039 ( .A(n118), .Y(n120) );
INVX2TS U1040 ( .A(n118), .Y(n121) );
INVX2TS U1041 ( .A(n149), .Y(n122) );
INVX2TS U1042 ( .A(n122), .Y(n123) );
INVX2TS U1043 ( .A(n122), .Y(n124) );
INVX2TS U1044 ( .A(n122), .Y(n125) );
INVX2TS U1045 ( .A(n662), .Y(n2589) );
OAI2BB1X1TS U1046 ( .A0N(n2588), .A1N(n2589), .B0(n936), .Y(n811) );
INVX2TS U1047 ( .A(n5184), .Y(n5166) );
INVX2TS U1048 ( .A(n2180), .Y(n2025) );
INVX2TS U1049 ( .A(n2773), .Y(n2775) );
INVX2TS U1050 ( .A(n2438), .Y(n2249) );
INVX2TS U1051 ( .A(n4382), .Y(n759) );
INVX2TS U1052 ( .A(n9999), .Y(n9992) );
INVX2TS U1053 ( .A(n2586), .Y(n2591) );
INVX2TS U1054 ( .A(n3375), .Y(n3377) );
INVX2TS U1055 ( .A(n4670), .Y(n4656) );
XNOR2X1TS U1056 ( .A(n3764), .B(n3762), .Y(n3763) );
INVX2TS U1057 ( .A(n5068), .Y(n5069) );
OAI22X1TS U1058 ( .A0(n5564), .A1(n576), .B0(n494), .B1(n5563), .Y(n5622) );
OAI2BB1X1TS U1059 ( .A0N(Data_B_i[47]), .A1N(Data_B_i[33]), .B0(n1328), .Y(
n2449) );
NOR2X2TS U1060 ( .A(n2177), .B(n2180), .Y(n955) );
INVX2TS U1061 ( .A(n5532), .Y(n5195) );
OAI22X1TS U1062 ( .A0(n4586), .A1(n479), .B0(n6494), .B1(n4585), .Y(n4626)
);
INVX2TS U1063 ( .A(n6642), .Y(n4379) );
NOR2XLTS U1064 ( .A(n9992), .B(n11271), .Y(n9994) );
OAI21XLTS U1065 ( .A0(n11280), .A1(n11257), .B0(n11258), .Y(n9998) );
INVX2TS U1066 ( .A(n2598), .Y(n2600) );
XNOR2X1TS U1067 ( .A(n331), .B(Data_A_i[31]), .Y(n1771) );
INVX2TS U1068 ( .A(n2038), .Y(n2159) );
INVX2TS U1069 ( .A(n6653), .Y(n4714) );
NOR2X1TS U1070 ( .A(n2761), .B(n2604), .Y(n2737) );
INVX2TS U1071 ( .A(n3368), .Y(n3262) );
INVX2TS U1072 ( .A(n6312), .Y(n486) );
NOR2X2TS U1073 ( .A(Data_A_i[21]), .B(Data_A_i[7]), .Y(n4397) );
NOR2XLTS U1074 ( .A(n4848), .B(n4847), .Y(n4849) );
NOR2XLTS U1075 ( .A(n5069), .B(n535), .Y(n6170) );
INVX2TS U1076 ( .A(n6411), .Y(n6412) );
XOR2X2TS U1077 ( .A(n1413), .B(n1412), .Y(n1411) );
INVX2TS U1078 ( .A(n5174), .Y(n5175) );
OAI22X1TS U1079 ( .A0(n5278), .A1(n577), .B0(n5277), .B1(n494), .Y(n5295) );
INVX2TS U1080 ( .A(n6651), .Y(n4702) );
OAI22X1TS U1081 ( .A0(n589), .A1(n3852), .B0(n3851), .B1(n487), .Y(n3872) );
OAI21XLTS U1082 ( .A0(n4054), .A1(n871), .B0(n4053), .Y(n869) );
OAI21XLTS U1083 ( .A0(n11252), .A1(n11253), .B0(n11254), .Y(n10059) );
BUFX6TS U1084 ( .A(Data_B_i[45]), .Y(n662) );
NAND2X2TS U1085 ( .A(Data_B_i[1]), .B(Data_B_i[28]), .Y(n2599) );
NAND2X2TS U1086 ( .A(n2600), .B(n2599), .Y(n1065) );
INVX2TS U1087 ( .A(n2009), .Y(n5624) );
NAND2X2TS U1088 ( .A(n1421), .B(n502), .Y(n584) );
INVX2TS U1089 ( .A(n3313), .Y(n3232) );
INVX2TS U1090 ( .A(n2693), .Y(n2662) );
NOR2XLTS U1091 ( .A(n623), .B(n301), .Y(n2113) );
NAND2X1TS U1092 ( .A(Data_A_i[51]), .B(n295), .Y(n6909) );
NOR2XLTS U1093 ( .A(n2840), .B(n2839), .Y(n2855) );
NOR2XLTS U1094 ( .A(n2646), .B(n2645), .Y(n2647) );
INVX2TS U1095 ( .A(n3201), .Y(n3116) );
NOR2X2TS U1096 ( .A(n3204), .B(n3203), .Y(n6854) );
CLKBUFX2TS U1097 ( .A(n2813), .Y(n3471) );
XOR2X2TS U1098 ( .A(n4724), .B(n4725), .Y(n991) );
NOR2XLTS U1099 ( .A(n142), .B(n2743), .Y(n2732) );
INVX2TS U1100 ( .A(n6314), .Y(n6315) );
INVX2TS U1101 ( .A(Data_B_i[12]), .Y(n1559) );
INVX2TS U1102 ( .A(n1021), .Y(n1557) );
OAI2BB1X1TS U1103 ( .A0N(n6125), .A1N(n1561), .B0(n6220), .Y(n1560) );
ADDFX1TS U1104 ( .A(n5741), .B(n5740), .CI(n5739), .CO(n5708), .S(n5783) );
INVX2TS U1105 ( .A(n5999), .Y(n2533) );
NOR2XLTS U1106 ( .A(n624), .B(n2376), .Y(n2481) );
INVX2TS U1107 ( .A(n5688), .Y(n5383) );
OAI21XLTS U1108 ( .A0(n5676), .A1(n5677), .B0(n5675), .Y(n1371) );
INVX2TS U1109 ( .A(n5311), .Y(n5348) );
NOR2XLTS U1110 ( .A(Data_B_i[38]), .B(Data_B_i[52]), .Y(n5146) );
AO21X1TS U1111 ( .A0(n4444), .A1(n4531), .B0(n133), .Y(n4767) );
INVX2TS U1112 ( .A(n6334), .Y(n3909) );
INVX2TS U1113 ( .A(n9878), .Y(n9738) );
INVX2TS U1114 ( .A(n9980), .Y(n9981) );
OAI21X1TS U1115 ( .A0(n662), .A1(Data_B_i[18]), .B0(n336), .Y(n2678) );
NAND2X2TS U1116 ( .A(Data_B_i[35]), .B(Data_B_i[8]), .Y(n3176) );
OAI21X1TS U1117 ( .A0(n3375), .A1(n3369), .B0(n3376), .Y(n1728) );
OAI2BB1X2TS U1118 ( .A0N(n711), .A1N(n3102), .B0(n2876), .Y(n1237) );
OAI2BB1X1TS U1119 ( .A0N(n2129), .A1N(n2128), .B0(n1452), .Y(n2140) );
XNOR2X2TS U1120 ( .A(n1574), .B(Data_B_i[38]), .Y(n1314) );
CLKBUFX2TS U1121 ( .A(Data_B_i[26]), .Y(n735) );
OAI21X2TS U1122 ( .A0(n754), .A1(n6914), .B0(n6913), .Y(n6918) );
NOR2XLTS U1123 ( .A(n3159), .B(n3158), .Y(n3166) );
XOR2X1TS U1124 ( .A(n3582), .B(n3581), .Y(n638) );
INVX2TS U1125 ( .A(n7003), .Y(n7005) );
CLKXOR2X2TS U1126 ( .A(n3467), .B(n936), .Y(n2818) );
INVX2TS U1127 ( .A(n8774), .Y(n3010) );
NOR2XLTS U1128 ( .A(n6315), .B(n536), .Y(n6367) );
NOR2XLTS U1129 ( .A(n6371), .B(n536), .Y(n6423) );
XNOR2X1TS U1130 ( .A(n239), .B(Data_A_i[19]), .Y(n4608) );
NAND2X1TS U1131 ( .A(n4663), .B(n4664), .Y(n1307) );
INVX2TS U1132 ( .A(n6175), .Y(n943) );
NOR2XLTS U1133 ( .A(n6438), .B(n535), .Y(n6501) );
INVX2TS U1134 ( .A(n8061), .Y(n8035) );
INVX2TS U1135 ( .A(n1335), .Y(n1334) );
NOR2XLTS U1136 ( .A(n5471), .B(n5194), .Y(n5963) );
AO21X1TS U1137 ( .A0(n6732), .A1(n484), .B0(n6730), .Y(n6782) );
XNOR2X1TS U1138 ( .A(n1346), .B(n5349), .Y(n5893) );
INVX2TS U1139 ( .A(n5129), .Y(n5130) );
OR2X1TS U1140 ( .A(n5177), .B(n7734), .Y(n5162) );
INVX2TS U1141 ( .A(n4779), .Y(n4782) );
OAI2BB1X1TS U1142 ( .A0N(n4232), .A1N(n4233), .B0(n1407), .Y(n714) );
BUFX6TS U1143 ( .A(Data_A_i[5]), .Y(n674) );
OAI22X1TS U1144 ( .A0(n549), .A1(n4020), .B0(n1389), .B1(n4009), .Y(n4056)
);
OAI21XLTS U1145 ( .A0(n9859), .A1(n11374), .B0(n11373), .Y(n9733) );
INVX2TS U1146 ( .A(n9898), .Y(n9831) );
INVX2TS U1147 ( .A(n10340), .Y(n10024) );
INVX2TS U1148 ( .A(n10177), .Y(n10179) );
ADDHXLTS U1149 ( .A(n11324), .B(n9908), .CO(n10213), .S(n10160) );
ADDHXLTS U1150 ( .A(n11312), .B(n10284), .CO(n10300), .S(n10286) );
NAND2X1TS U1151 ( .A(Data_A_i[39]), .B(Data_A_i[12]), .Y(n3388) );
INVX2TS U1152 ( .A(n522), .Y(n330) );
INVX2TS U1153 ( .A(n906), .Y(n468) );
INVX4TS U1154 ( .A(n517), .Y(n408) );
XNOR2X1TS U1155 ( .A(n8428), .B(n139), .Y(n7429) );
NOR2XLTS U1156 ( .A(Data_B_i[17]), .B(Data_B_i[44]), .Y(n2679) );
INVX2TS U1157 ( .A(Data_B_i[15]), .Y(n5042) );
INVX2TS U1158 ( .A(n513), .Y(n320) );
INVX4TS U1159 ( .A(n5474), .Y(n5485) );
OAI21XLTS U1160 ( .A0(Data_B_i[53]), .A1(n735), .B0(n330), .Y(n6875) );
OAI22X1TS U1161 ( .A0(n465), .A1(n7432), .B0(n7437), .B1(n551), .Y(n7454) );
XNOR2X1TS U1162 ( .A(n7436), .B(n381), .Y(n8257) );
INVX2TS U1163 ( .A(n7420), .Y(n824) );
INVX2TS U1164 ( .A(n6963), .Y(n7087) );
NOR2XLTS U1165 ( .A(n6529), .B(n6524), .Y(n4908) );
OAI21XLTS U1166 ( .A0(n3218), .A1(n1149), .B0(n3217), .Y(n1147) );
NOR2XLTS U1167 ( .A(n8424), .B(n3676), .Y(n3691) );
OAI22X1TS U1168 ( .A0(n140), .A1(n3649), .B0(n3683), .B1(n540), .Y(n3679) );
XOR2X1TS U1169 ( .A(n6488), .B(n6489), .Y(n1627) );
INVX2TS U1170 ( .A(n6550), .Y(n6551) );
INVX2TS U1171 ( .A(n7195), .Y(n7196) );
CLKBUFX2TS U1172 ( .A(n3514), .Y(n3511) );
ADDFX2TS U1173 ( .A(n2375), .B(n2374), .CI(n2373), .CO(n2478), .S(n2385) );
NOR2XLTS U1174 ( .A(n5949), .B(n363), .Y(n6724) );
NOR2XLTS U1175 ( .A(n6718), .B(n363), .Y(n6774) );
OAI2BB1X1TS U1176 ( .A0N(n4181), .A1N(n1034), .B0(n1031), .Y(n4947) );
XNOR2X1TS U1177 ( .A(n4185), .B(n4187), .Y(n839) );
INVX2TS U1178 ( .A(n4918), .Y(n4429) );
INVX2TS U1179 ( .A(n9895), .Y(n9796) );
NAND2X1TS U1180 ( .A(n11444), .B(n11443), .Y(n9889) );
NOR2XLTS U1181 ( .A(n9747), .B(n9748), .Y(n9843) );
INVX2TS U1182 ( .A(n9779), .Y(n9776) );
NOR2BX1TS U1183 ( .AN(n10087), .B(n10086), .Y(n10088) );
OAI21XLTS U1184 ( .A0(n10423), .A1(n10438), .B0(n10422), .Y(n10456) );
OR2X1TS U1185 ( .A(n10485), .B(n10484), .Y(n10487) );
NOR2XLTS U1186 ( .A(n10307), .B(n10309), .Y(n10312) );
CLKXOR2X2TS U1187 ( .A(n2871), .B(n2870), .Y(n8237) );
INVX2TS U1188 ( .A(n2672), .Y(n2674) );
OAI21X1TS U1189 ( .A0(n6109), .A1(n6110), .B0(n6108), .Y(n1220) );
INVX2TS U1190 ( .A(n2761), .Y(n390) );
INVX2TS U1191 ( .A(n2107), .Y(n1974) );
INVX2TS U1192 ( .A(n981), .Y(n603) );
OAI22X1TS U1193 ( .A0(n6729), .A1(n5125), .B0(n6728), .B1(n5124), .Y(n5256)
);
OR2X1TS U1194 ( .A(Data_A_i[41]), .B(n1887), .Y(n2008) );
OAI22X1TS U1195 ( .A0(n7535), .A1(n551), .B0(n7437), .B1(n465), .Y(n7566) );
INVX2TS U1196 ( .A(n464), .Y(n465) );
OAI21XLTS U1197 ( .A0(n257), .A1(n1205), .B0(n4967), .Y(n6071) );
NAND2X2TS U1198 ( .A(n2148), .B(n1744), .Y(n1989) );
NOR2X1TS U1199 ( .A(n6906), .B(n197), .Y(n6948) );
OAI22X1TS U1200 ( .A0(n8238), .A1(n552), .B0(n6954), .B1(n465), .Y(n8246) );
OAI22X1TS U1201 ( .A0(n8569), .A1(n649), .B0(n8568), .B1(n8567), .Y(n1106)
);
XNOR2X1TS U1202 ( .A(n8225), .B(n438), .Y(n8318) );
INVX2TS U1203 ( .A(n815), .Y(n812) );
XOR2X1TS U1204 ( .A(n7671), .B(n7670), .Y(n7673) );
OAI2BB1X2TS U1205 ( .A0N(n3585), .A1N(n3584), .B0(n1483), .Y(n7494) );
CLKBUFX2TS U1206 ( .A(n8308), .Y(n485) );
INVX2TS U1207 ( .A(n4942), .Y(n1182) );
INVX2TS U1208 ( .A(n8790), .Y(n3155) );
OAI2BB1X2TS U1209 ( .A0N(n3480), .A1N(n3479), .B0(n1170), .Y(n7617) );
INVX2TS U1210 ( .A(n6596), .Y(n4885) );
INVX2TS U1211 ( .A(n9296), .Y(n9298) );
OAI21XLTS U1212 ( .A0(n2411), .A1(n2412), .B0(n2409), .Y(n2410) );
OAI22X1TS U1213 ( .A0(n332), .A1(n2167), .B0(n2203), .B1(n5568), .Y(n2171)
);
XOR2X2TS U1214 ( .A(n5399), .B(n5400), .Y(n661) );
OAI21XLTS U1215 ( .A0(n4921), .A1(n4920), .B0(n4919), .Y(n4922) );
NAND2BX1TS U1216 ( .AN(n1183), .B(n3971), .Y(n4294) );
AOI21X1TS U1217 ( .A0(n207), .A1(n4323), .B0(n3947), .Y(n4313) );
CLKINVX3TS U1218 ( .A(n1015), .Y(n4239) );
NAND2X1TS U1219 ( .A(n4156), .B(n1390), .Y(n550) );
INVX2TS U1220 ( .A(n10846), .Y(n9720) );
NAND2X1TS U1221 ( .A(n10903), .B(n11552), .Y(n9800) );
INVX2TS U1222 ( .A(n9881), .Y(n9886) );
INVX2TS U1223 ( .A(n10384), .Y(n10374) );
INVX2TS U1224 ( .A(n10078), .Y(n10409) );
OR2X1TS U1225 ( .A(n10198), .B(n10197), .Y(n10473) );
NAND2X1TS U1226 ( .A(n10217), .B(n10216), .Y(n10251) );
OR2X1TS U1227 ( .A(n10317), .B(n10316), .Y(n10318) );
NAND2X1TS U1228 ( .A(n10685), .B(n10660), .Y(n10661) );
OAI21XLTS U1229 ( .A0(n11605), .A1(n11608), .B0(n11606), .Y(n10276) );
OAI22X1TS U1230 ( .A0(n2892), .A1(n352), .B0(n2880), .B1(n7558), .Y(n2864)
);
INVX2TS U1231 ( .A(n270), .Y(n271) );
INVX2TS U1232 ( .A(n9518), .Y(n9519) );
OAI22X1TS U1233 ( .A0(n355), .A1(n3003), .B0(n2766), .B1(n390), .Y(n3527) );
INVX2TS U1234 ( .A(n2085), .Y(n2064) );
INVX2TS U1235 ( .A(n8663), .Y(n3533) );
OAI21X1TS U1236 ( .A0(n9076), .A1(n9082), .B0(n9077), .Y(n1972) );
INVX2TS U1237 ( .A(n2345), .Y(n2233) );
OAI21X1TS U1238 ( .A0(n2936), .A1(n271), .B0(n1253), .Y(n2935) );
INVX2TS U1239 ( .A(n2466), .Y(n2394) );
XOR2X1TS U1240 ( .A(n1964), .B(n1965), .Y(n696) );
AO21X1TS U1241 ( .A0(n8259), .A1(n467), .B0(n175), .Y(n7068) );
INVX2TS U1242 ( .A(n7485), .Y(n7158) );
INVX2TS U1243 ( .A(n7015), .Y(n7029) );
CLKXOR2X2TS U1244 ( .A(n822), .B(n821), .Y(n7861) );
NOR2XLTS U1245 ( .A(n8393), .B(n8396), .Y(n8710) );
ADDFHX2TS U1246 ( .A(n3618), .B(n3617), .CI(n3616), .CO(n8305), .S(n8610) );
XNOR2X1TS U1247 ( .A(n1012), .B(n4289), .Y(n998) );
OAI21X1TS U1248 ( .A0(n4801), .A1(n4802), .B0(n4800), .Y(n837) );
XNOR2X2TS U1249 ( .A(n717), .B(n6468), .Y(n6607) );
OAI21XLTS U1250 ( .A0(n1619), .A1(n7907), .B0(n1618), .Y(n1617) );
NAND2X2TS U1251 ( .A(n5847), .B(n5846), .Y(n8019) );
OAI21XLTS U1252 ( .A0(n8057), .A1(n8029), .B0(n8037), .Y(n7198) );
INVX2TS U1253 ( .A(n7982), .Y(n7984) );
OR2X1TS U1254 ( .A(n5110), .B(n11193), .Y(n7998) );
INVX2TS U1255 ( .A(n11220), .Y(n9273) );
INVX2TS U1256 ( .A(n6021), .Y(n5996) );
OAI2BB1X1TS U1257 ( .A0N(n1656), .A1N(n1655), .B0(n5515), .Y(n1654) );
XOR2X1TS U1258 ( .A(n2409), .B(n2293), .Y(n5995) );
OAI21XLTS U1259 ( .A0(n4195), .A1(n4196), .B0(n4194), .Y(n854) );
AO21X1TS U1260 ( .A0(n9811), .A1(n9848), .B0(n9810), .Y(n9812) );
OAI21XLTS U1261 ( .A0(n10921), .A1(n9825), .B0(n10919), .Y(n9826) );
INVX2TS U1262 ( .A(n9916), .Y(n9918) );
OA21XLTS U1263 ( .A0(n9772), .A1(n9771), .B0(n9770), .Y(n9931) );
NAND2X1TS U1264 ( .A(n10374), .B(n10383), .Y(n10375) );
INVX2TS U1265 ( .A(n11095), .Y(n10443) );
INVX2TS U1266 ( .A(n10313), .Y(n10299) );
NOR2XLTS U1267 ( .A(n10761), .B(n11509), .Y(n10549) );
NOR2XLTS U1268 ( .A(n10780), .B(n10728), .Y(n10729) );
NOR2XLTS U1269 ( .A(n10799), .B(n10686), .Y(n10687) );
NAND2X1TS U1270 ( .A(n10274), .B(n11598), .Y(n10139) );
NOR2XLTS U1271 ( .A(n10799), .B(n10606), .Y(n10607) );
NOR2XLTS U1272 ( .A(n10536), .B(n10540), .Y(n10671) );
INVX2TS U1273 ( .A(n9521), .Y(n7363) );
AOI21X1TS U1274 ( .A0(n2090), .A1(n2103), .B0(n2107), .Y(n2070) );
NAND2X4TS U1275 ( .A(Data_B_i[53]), .B(Data_B_i[52]), .Y(n6760) );
INVX2TS U1276 ( .A(n9043), .Y(n8786) );
NOR2X1TS U1277 ( .A(n1315), .B(n2242), .Y(n2232) );
XOR2X1TS U1278 ( .A(n7131), .B(n7132), .Y(n848) );
NOR2XLTS U1279 ( .A(n7158), .B(n453), .Y(n8422) );
XOR2X2TS U1280 ( .A(n7664), .B(n7665), .Y(n1126) );
NOR2X2TS U1281 ( .A(n8304), .B(n8300), .Y(n7714) );
NOR2XLTS U1282 ( .A(n7277), .B(n7689), .Y(n7280) );
INVX2TS U1283 ( .A(n8377), .Y(n9457) );
INVX2TS U1284 ( .A(n8207), .Y(n7387) );
OAI2BB1X1TS U1285 ( .A0N(n6470), .A1N(n6469), .B0(n736), .Y(n6610) );
OR2X1TS U1286 ( .A(n6341), .B(n6340), .Y(n9480) );
INVX2TS U1287 ( .A(n1305), .Y(n9469) );
NAND2X1TS U1288 ( .A(n8046), .B(n8047), .Y(n8048) );
NAND2X1TS U1289 ( .A(n8111), .B(n8109), .Y(n1311) );
INVX8TS U1290 ( .A(n510), .Y(n245) );
INVX2TS U1291 ( .A(n7755), .Y(n7758) );
INVX2TS U1292 ( .A(n8098), .Y(n8100) );
OR2X1TS U1293 ( .A(n5995), .B(n5994), .Y(n6022) );
OAI21X1TS U1294 ( .A0(n9632), .A1(n7942), .B0(n8187), .Y(n6809) );
OR2X2TS U1295 ( .A(n4451), .B(n4450), .Y(n9428) );
NOR2XLTS U1296 ( .A(n4123), .B(n4122), .Y(n8655) );
NAND2X1TS U1297 ( .A(n10032), .B(n11533), .Y(n10840) );
INVX2TS U1298 ( .A(n9722), .Y(n10853) );
NOR2XLTS U1299 ( .A(n9783), .B(n10875), .Y(n9789) );
INVX2TS U1300 ( .A(n10986), .Y(n10983) );
NOR2XLTS U1301 ( .A(n10445), .B(n11512), .Y(n11107) );
NOR2XLTS U1302 ( .A(n10499), .B(n11489), .Y(n11154) );
NOR2XLTS U1303 ( .A(n10507), .B(n11473), .Y(n10626) );
OAI21XLTS U1304 ( .A0(n11586), .A1(n11587), .B0(n11588), .Y(n9969) );
OAI21XLTS U1305 ( .A0(n10279), .A1(n10163), .B0(n10162), .Y(n10164) );
AOI2BB1X1TS U1306 ( .A0N(n10156), .A1N(n10155), .B0(n10154), .Y(n10157) );
OAI21XLTS U1307 ( .A0(n10279), .A1(n10240), .B0(n10239), .Y(n10241) );
INVX2TS U1308 ( .A(n8075), .Y(n964) );
NOR2XLTS U1309 ( .A(n8792), .B(n8791), .Y(n8818) );
BUFX8TS U1310 ( .A(n3102), .Y(n2698) );
OAI21XLTS U1311 ( .A0(n7302), .A1(n7301), .B0(n7300), .Y(n7303) );
OAI21XLTS U1312 ( .A0(n9097), .A1(n9103), .B0(n9098), .Y(n1907) );
OR2X1TS U1313 ( .A(n6760), .B(n6759), .Y(n1697) );
NOR2XLTS U1314 ( .A(n9574), .B(n9575), .Y(n9577) );
INVX2TS U1315 ( .A(n7683), .Y(n6689) );
NOR2XLTS U1316 ( .A(n7349), .B(n7348), .Y(n7361) );
NOR2XLTS U1317 ( .A(n8935), .B(n8934), .Y(n8946) );
NOR2XLTS U1318 ( .A(n9021), .B(n9005), .Y(n8835) );
NOR2BX1TS U1319 ( .AN(n4600), .B(n4821), .Y(n5021) );
AOI21X1TS U1320 ( .A0(n9434), .A1(n7280), .B0(n7279), .Y(n7285) );
INVX2TS U1321 ( .A(n7397), .Y(n7399) );
OR2X1TS U1322 ( .A(n6648), .B(n6647), .Y(n8548) );
NAND3X1TS U1323 ( .A(n1445), .B(n1444), .C(n1443), .Y(n1442) );
INVX2TS U1324 ( .A(n8194), .Y(n7966) );
NAND2X1TS U1325 ( .A(n8408), .B(n8407), .Y(n8409) );
OAI21XLTS U1326 ( .A0(n8658), .A1(n8655), .B0(n8656), .Y(n9199) );
NAND2X1TS U1327 ( .A(n9991), .B(n11534), .Y(n10832) );
INVX2TS U1328 ( .A(n10928), .Y(n10930) );
OAI21XLTS U1329 ( .A0(n10937), .A1(n9829), .B0(n9828), .Y(n10973) );
OAI21XLTS U1330 ( .A0(n10352), .A1(n10351), .B0(n10350), .Y(n11017) );
INVX2TS U1331 ( .A(n11065), .Y(n11061) );
NOR2XLTS U1332 ( .A(n10441), .B(n11513), .Y(n11088) );
OAI21XLTS U1333 ( .A0(n11129), .A1(n11126), .B0(n11130), .Y(n11141) );
NOR2XLTS U1334 ( .A(n11166), .B(n11154), .Y(n11173) );
OAI21XLTS U1335 ( .A0(n10756), .A1(n10546), .B0(n10530), .Y(n10531) );
NOR2XLTS U1336 ( .A(n10763), .B(n10574), .Y(n10576) );
OAI21XLTS U1337 ( .A0(n10756), .A1(n10654), .B0(n10653), .Y(n10655) );
OAI21XLTS U1338 ( .A0(n10769), .A1(n10677), .B0(n10676), .Y(n10678) );
NOR2XLTS U1339 ( .A(n10672), .B(n10564), .Y(n10566) );
INVX2TS U1340 ( .A(n9021), .Y(n9023) );
OR2X1TS U1341 ( .A(n8783), .B(n8782), .Y(n1706) );
CLKXOR2X2TS U1342 ( .A(n2698), .B(n1733), .Y(n7537) );
INVX2TS U1343 ( .A(n7320), .Y(n7336) );
INVX2TS U1344 ( .A(n7973), .Y(n1890) );
NOR2XLTS U1345 ( .A(n2423), .B(n2413), .Y(n9102) );
INVX2TS U1346 ( .A(n9567), .Y(n9560) );
INVX2TS U1347 ( .A(n9585), .Y(n9601) );
AOI21X1TS U1348 ( .A0(n7686), .A1(n7684), .B0(n6689), .Y(n6692) );
INVX2TS U1349 ( .A(n7302), .Y(n7295) );
INVX2TS U1350 ( .A(n9413), .Y(n9415) );
OR2X1TS U1351 ( .A(n9398), .B(n9397), .Y(n9400) );
INVX2TS U1352 ( .A(n8959), .Y(n8974) );
INVX2TS U1353 ( .A(n8984), .Y(n8977) );
OR2X4TS U1354 ( .A(n948), .B(n730), .Y(n9541) );
AOI21X1TS U1355 ( .A0(n7390), .A1(n529), .B0(n7389), .Y(n7393) );
INVX2TS U1356 ( .A(n9485), .Y(n1648) );
NAND2X2TS U1357 ( .A(n8068), .B(n8067), .Y(n8389) );
NAND2X1TS U1358 ( .A(n6807), .B(n6805), .Y(n6792) );
OAI21XLTS U1359 ( .A0(n9632), .A1(n8189), .B0(n8188), .Y(n8190) );
INVX2TS U1360 ( .A(n10902), .Y(n10880) );
INVX2TS U1361 ( .A(n10973), .Y(n10990) );
OA21XLTS U1362 ( .A0(n11040), .A1(n10382), .B0(n10381), .Y(n11066) );
OR2X1TS U1363 ( .A(n11172), .B(n11174), .Y(n11160) );
NAND2X1TS U1364 ( .A(n11182), .B(n11181), .Y(n11183) );
INVX2TS U1365 ( .A(n8849), .Y(n9042) );
OAI21XLTS U1366 ( .A0(n9040), .A1(n9036), .B0(n9037), .Y(n8822) );
INVX2TS U1367 ( .A(n8130), .Y(n8140) );
OAI21XLTS U1368 ( .A0(n9106), .A1(n9102), .B0(n9103), .Y(n9101) );
OAI21X1TS U1369 ( .A0(n9573), .A1(n9572), .B0(n9571), .Y(n9704) );
INVX2TS U1370 ( .A(n7252), .Y(n7260) );
OR2X1TS U1371 ( .A(n8871), .B(n8870), .Y(n215) );
NAND3X1TS U1372 ( .A(n4543), .B(n4542), .C(n4541), .Y(n9074) );
XOR2X1TS U1373 ( .A(n1006), .B(n9067), .Y(n8180) );
INVX2TS U1374 ( .A(n11235), .Y(n9441) );
NAND2BX1TS U1375 ( .AN(n6345), .B(n916), .Y(n6346) );
NOR2BX2TS U1376 ( .AN(n9351), .B(n9352), .Y(n1427) );
OAI21X2TS U1377 ( .A0(n9416), .A1(n9413), .B0(n9414), .Y(n9344) );
INVX2TS U1378 ( .A(n9657), .Y(n7802) );
XOR2X2TS U1379 ( .A(n975), .B(n232), .Y(n8386) );
NAND2X1TS U1380 ( .A(n11222), .B(n11730), .Y(n11223) );
INVX2TS U1381 ( .A(EVEN1_left_RECURSIVE_ODD1_Q_left_17_), .Y(add_x_2_n109)
);
NAND2X1TS U1382 ( .A(n11186), .B(sgf_result_o[33]), .Y(n11734) );
CLKBUFX2TS U1383 ( .A(load_b_i), .Y(n11730) );
INVX2TS U1384 ( .A(DP_OP_59J6_122_190_n210), .Y(DP_OP_59J6_122_190_n204) );
INVX2TS U1385 ( .A(n1150), .Y(DP_OP_59J6_122_190_n224) );
XNOR2X1TS U1386 ( .A(n1455), .B(n8008), .Y(DP_OP_62J6_125_4796_n555) );
INVX2TS U1387 ( .A(n9501), .Y(add_x_3_n306) );
INVX2TS U1388 ( .A(n9547), .Y(add_x_1_n330) );
NAND2X1TS U1389 ( .A(n8386), .B(n8385), .Y(add_x_2_n141) );
OAI21XLTS U1390 ( .A0(n11627), .A1(n1700), .B0(n11643), .Y(sgf_result_o[30])
);
OAI2BB1X1TS U1391 ( .A0N(n114), .A1N(n10592), .B0(n11694), .Y(
sgf_result_o[80]) );
OAI2BB1X1TS U1392 ( .A0N(n121), .A1N(n10811), .B0(n11717), .Y(
sgf_result_o[100]) );
INVX2TS U1393 ( .A(n197), .Y(n381) );
AND2X2TS U1394 ( .A(n6875), .B(n6874), .Y(n197) );
XOR2X1TS U1395 ( .A(n3273), .B(n3272), .Y(n127) );
OAI21X2TS U1396 ( .A0(n9296), .A1(n9293), .B0(n9297), .Y(n9312) );
XOR2X2TS U1397 ( .A(n1439), .B(Data_B_i[42]), .Y(n5585) );
CLKINVX6TS U1398 ( .A(n1172), .Y(n6084) );
OR2X1TS U1399 ( .A(Data_A_i[27]), .B(Data_A_i[0]), .Y(n128) );
INVX6TS U1400 ( .A(n1026), .Y(n256) );
OA21X2TS U1401 ( .A0(n9125), .A1(n9137), .B0(n9126), .Y(n129) );
INVX2TS U1402 ( .A(n398), .Y(n399) );
CLKINVX3TS U1403 ( .A(n1218), .Y(n598) );
CLKBUFX2TS U1404 ( .A(load_b_i), .Y(n11731) );
INVX2TS U1405 ( .A(n3439), .Y(n618) );
INVX2TS U1406 ( .A(n2762), .Y(n3439) );
XNOR2X1TS U1407 ( .A(n2012), .B(n2011), .Y(n130) );
CLKBUFX2TS U1408 ( .A(Data_B_i[42]), .Y(n665) );
XOR2X1TS U1409 ( .A(n2030), .B(n224), .Y(n131) );
NAND2X4TS U1410 ( .A(n961), .B(n960), .Y(n2256) );
AO21X2TS U1411 ( .A0(DP_OP_59J6_122_190_n103), .A1(n8910), .B0(n8469), .Y(
n132) );
INVX2TS U1412 ( .A(n9546), .Y(n7386) );
CLKINVX1TS U1413 ( .A(add_x_3_n144), .Y(add_x_3_n146) );
CLKINVX1TS U1414 ( .A(add_x_3_n172), .Y(add_x_3_n174) );
INVX2TS U1415 ( .A(n9468), .Y(add_x_3_n307) );
CLKINVX2TS U1416 ( .A(add_x_3_n138), .Y(n7404) );
INVX1TS U1417 ( .A(n9537), .Y(n8220) );
INVX2TS U1418 ( .A(EVEN1_Q_left[31]), .Y(add_x_1_n322) );
INVX1TS U1419 ( .A(n9057), .Y(n8494) );
OR2X4TS U1420 ( .A(n8180), .B(n8179), .Y(n11389) );
OR2X4TS U1421 ( .A(n8386), .B(n8385), .Y(n9628) );
CLKINVX1TS U1422 ( .A(DP_OP_59J6_122_190_n153), .Y(DP_OP_59J6_122_190_n303)
);
XOR2XLTS U1423 ( .A(n10735), .B(n1703), .Y(n10736) );
INVX2TS U1424 ( .A(n9484), .Y(n1649) );
INVX2TS U1425 ( .A(n527), .Y(n528) );
INVX4TS U1426 ( .A(EVEN1_Q_left[27]), .Y(n8730) );
INVX1TS U1427 ( .A(EVEN1_Q_left[24]), .Y(n8489) );
AO21X1TS U1428 ( .A0(n10802), .A1(n10801), .B0(n10800), .Y(n10803) );
XOR2X1TS U1429 ( .A(n9000), .B(n8999), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[19]) );
XOR2X1TS U1430 ( .A(n8976), .B(n8975), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[22]) );
XOR2X1TS U1431 ( .A(n8964), .B(n8963), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[23]) );
INVX1TS U1432 ( .A(n9408), .Y(n9410) );
XOR2X1TS U1433 ( .A(n8958), .B(n8957), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[25]) );
XOR2X1TS U1434 ( .A(n8970), .B(n8969), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[24]) );
INVX1TS U1435 ( .A(EVEN1_Q_left[22]), .Y(n9440) );
XOR2X1TS U1436 ( .A(n8992), .B(n8991), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[21]) );
NAND2X2TS U1437 ( .A(n8882), .B(n8881), .Y(n8893) );
AO21X1TS U1438 ( .A0(n10783), .A1(n10782), .B0(n10781), .Y(n10784) );
INVX1TS U1439 ( .A(n11094), .Y(n11114) );
INVX1TS U1440 ( .A(n9365), .Y(n9369) );
XOR2X2TS U1441 ( .A(n7260), .B(n7254), .Y(EVEN1_Q_left[20]) );
CLKINVX1TS U1442 ( .A(n10536), .Y(n10589) );
CLKAND2X2TS U1443 ( .A(n11150), .B(n11149), .Y(n11151) );
CLKINVX2TS U1444 ( .A(n11082), .Y(n11076) );
NOR2X2TS U1445 ( .A(n9249), .B(n9248), .Y(n9413) );
CLKINVX2TS U1446 ( .A(n8813), .Y(n9030) );
INVX1TS U1447 ( .A(EVEN1_Q_left[16]), .Y(n9320) );
NAND2X2TS U1448 ( .A(n4943), .B(n4942), .Y(n4946) );
CLKINVX2TS U1449 ( .A(n11107), .Y(n10447) );
NAND2X1TS U1450 ( .A(n11091), .B(sgf_result_o[58]), .Y(n11746) );
INVX1TS U1451 ( .A(n9431), .Y(n9432) );
CMPR22X2TS U1452 ( .A(n9287), .B(n9286), .CO(n9310), .S(n9302) );
XOR2X1TS U1453 ( .A(n9281), .B(n9280), .Y(EVEN1_Q_left[15]) );
INVX1TS U1454 ( .A(n7255), .Y(n7257) );
NAND2X4TS U1455 ( .A(n1043), .B(n1644), .Y(n8111) );
INVX2TS U1456 ( .A(n8109), .Y(n8110) );
CLKINVX1TS U1457 ( .A(n9005), .Y(n9007) );
CLKINVX2TS U1458 ( .A(n11222), .Y(n9286) );
CLKINVX2TS U1459 ( .A(n7259), .Y(n7253) );
OAI21X1TS U1460 ( .A0(n7882), .A1(n7883), .B0(n7881), .Y(n1083) );
INVX1TS U1461 ( .A(n9208), .Y(n1495) );
INVX2TS U1462 ( .A(n7911), .Y(n7913) );
NAND2X2TS U1463 ( .A(n2241), .B(n2240), .Y(n7683) );
NAND2X2TS U1464 ( .A(n2097), .B(n2096), .Y(n8137) );
INVX2TS U1465 ( .A(EVEN1_right_RECURSIVE_ODD1_Q_left_17_), .Y(add_x_3_n109)
);
NAND2X1TS U1466 ( .A(n11726), .B(sgf_result_o[56]), .Y(n11744) );
NAND2X1TS U1467 ( .A(n11726), .B(sgf_result_o[55]), .Y(n11743) );
CLKINVX2TS U1468 ( .A(n8848), .Y(n9041) );
INVX1TS U1469 ( .A(n8825), .Y(n9031) );
INVX1TS U1470 ( .A(n4726), .Y(n1651) );
INVX1TS U1471 ( .A(EVEN1_Q_left[13]), .Y(n9272) );
NAND2X2TS U1472 ( .A(n9122), .B(n9121), .Y(n9280) );
CLKINVX1TS U1473 ( .A(n8988), .Y(n8990) );
OR2X2TS U1474 ( .A(n9122), .B(n9121), .Y(n236) );
OAI21X1TS U1475 ( .A0(n6264), .A1(n6265), .B0(n6263), .Y(n1299) );
ADDFHX2TS U1476 ( .A(n8599), .B(n8598), .CI(n8597), .CO(n8839), .S(n8833) );
INVX2TS U1477 ( .A(n10402), .Y(n10432) );
INVX1TS U1478 ( .A(n4453), .Y(n1194) );
AOI21X2TS U1479 ( .A0(n10373), .A1(n10077), .B0(n10076), .Y(n10402) );
INVX2TS U1480 ( .A(n10373), .Y(n10385) );
CLKINVX1TS U1481 ( .A(n8480), .Y(n7233) );
CLKINVX2TS U1482 ( .A(n1711), .Y(n1618) );
INVX1TS U1483 ( .A(n7943), .Y(n1447) );
XOR2X2TS U1484 ( .A(n6246), .B(n6247), .Y(n941) );
NAND2X2TS U1485 ( .A(n7943), .B(n7948), .Y(n7952) );
INVX2TS U1486 ( .A(n2557), .Y(n2463) );
ADDFHX1TS U1487 ( .A(n7493), .B(n7492), .CI(n7491), .CO(n8591), .S(n7512) );
OAI2BB1X2TS U1488 ( .A0N(n10361), .A1N(n10054), .B0(n10053), .Y(n10373) );
NAND2BX1TS U1489 ( .AN(n4299), .B(n1000), .Y(n999) );
OAI2BB1X2TS U1490 ( .A0N(n4725), .A1N(n4724), .B0(n990), .Y(n4865) );
CLKINVX2TS U1491 ( .A(n7394), .Y(n7930) );
INVX1TS U1492 ( .A(n3452), .Y(n1524) );
CLKINVX1TS U1493 ( .A(n556), .Y(n1112) );
XOR2X1TS U1494 ( .A(n3218), .B(n1149), .Y(n1148) );
ADDFHX2TS U1495 ( .A(n6196), .B(n6195), .CI(n6194), .CO(n6279), .S(n6228) );
OR2X2TS U1496 ( .A(n8775), .B(n8774), .Y(n1688) );
INVX2TS U1497 ( .A(n4345), .Y(n4335) );
OR2X4TS U1498 ( .A(n7753), .B(n7752), .Y(n7943) );
INVX1TS U1499 ( .A(n6258), .Y(n1398) );
INVX2TS U1500 ( .A(n2106), .Y(n2003) );
INVX2TS U1501 ( .A(n7795), .Y(n7760) );
XNOR2X2TS U1502 ( .A(n5451), .B(n5452), .Y(n1340) );
AOI21X1TS U1503 ( .A0(n4135), .A1(n9168), .B0(n4134), .Y(n9149) );
ADDFHX2TS U1504 ( .A(n4416), .B(n4415), .CI(n4414), .CO(n4417), .S(n3887) );
INVX1TS U1505 ( .A(n6344), .Y(n916) );
NAND2X1TS U1506 ( .A(n10292), .B(n10270), .Y(n10272) );
INVX1TS U1507 ( .A(n10292), .Y(n10236) );
CLKINVX1TS U1508 ( .A(n8195), .Y(n7970) );
CLKINVX1TS U1509 ( .A(n4318), .Y(n4320) );
AO21X1TS U1510 ( .A0(n10339), .A1(n9932), .B0(n10020), .Y(n9941) );
NOR2XLTS U1511 ( .A(n7396), .B(n7397), .Y(n6665) );
XOR2X1TS U1512 ( .A(n4334), .B(n183), .Y(n4353) );
INVX2TS U1513 ( .A(n5075), .Y(n6209) );
NAND2BX1TS U1514 ( .AN(n632), .B(n376), .Y(n3014) );
INVX2TS U1515 ( .A(n6027), .Y(n1001) );
AO21X1TS U1516 ( .A0(n9687), .A1(n9686), .B0(n9685), .Y(n9688) );
INVX1TS U1517 ( .A(n10309), .Y(n10304) );
INVX2TS U1518 ( .A(n10401), .Y(n10428) );
CLKINVX1TS U1519 ( .A(n10400), .Y(n10426) );
AOI2BB1XLTS U1520 ( .A0N(n10937), .A1N(n10936), .B0(n10935), .Y(n10941) );
OAI2BB1X2TS U1521 ( .A0N(n4069), .A1N(n4068), .B0(n923), .Y(n5075) );
INVX2TS U1522 ( .A(EVEN1_middle_RECURSIVE_EVEN1_Q_left[0]), .Y(n9266) );
OAI21X1TS U1523 ( .A0(n714), .A1(n4248), .B0(n4247), .Y(n713) );
CLKINVX2TS U1524 ( .A(n6846), .Y(n7754) );
CLKINVX1TS U1525 ( .A(n4423), .Y(n4288) );
INVX1TS U1526 ( .A(n7751), .Y(n1355) );
CLKINVX1TS U1527 ( .A(n7331), .Y(n7333) );
NAND2BXLTS U1528 ( .AN(n10460), .B(n10459), .Y(n10461) );
NAND2BXLTS U1529 ( .AN(n10423), .B(n10422), .Y(n10424) );
NAND2X1TS U1530 ( .A(n9696), .B(n9706), .Y(n9683) );
INVX2TS U1531 ( .A(n6848), .Y(n5714) );
INVX2TS U1532 ( .A(n6684), .Y(n6220) );
INVX2TS U1533 ( .A(n8241), .Y(n8242) );
INVX2TS U1534 ( .A(n9696), .Y(n9700) );
INVX1TS U1535 ( .A(n7987), .Y(n1666) );
INVX1TS U1536 ( .A(n7916), .Y(n7928) );
INVX1TS U1537 ( .A(n6437), .Y(n6438) );
CLKINVX1TS U1538 ( .A(n6421), .Y(n1662) );
CLKINVX1TS U1539 ( .A(n8043), .Y(n8044) );
INVX1TS U1540 ( .A(n6572), .Y(n6573) );
INVX1TS U1541 ( .A(n10429), .Y(n10403) );
INVX2TS U1542 ( .A(n10934), .Y(n10936) );
OR2X1TS U1543 ( .A(n9918), .B(n9917), .Y(n10946) );
NAND2BXLTS U1544 ( .AN(n10329), .B(n10328), .Y(n10330) );
CLKINVX1TS U1545 ( .A(n10370), .Y(n10050) );
XOR2X1TS U1546 ( .A(n996), .B(n4231), .Y(n4225) );
INVX1TS U1547 ( .A(n9603), .Y(n9604) );
NOR2X1TS U1548 ( .A(n9673), .B(n9677), .Y(n9696) );
INVX1TS U1549 ( .A(n9673), .Y(n9620) );
INVX1TS U1550 ( .A(n9113), .Y(n9108) );
INVX1TS U1551 ( .A(n3528), .Y(n2961) );
NOR2X4TS U1552 ( .A(n3348), .B(n8424), .Y(n3608) );
CLKINVX1TS U1553 ( .A(n7310), .Y(n1048) );
INVX2TS U1554 ( .A(n10085), .Y(n10086) );
CLKINVX2TS U1555 ( .A(n10079), .Y(n10082) );
XOR2X2TS U1556 ( .A(n1780), .B(n1781), .Y(n702) );
OR2X2TS U1557 ( .A(n6000), .B(n5999), .Y(n6009) );
CLKINVX2TS U1558 ( .A(n8522), .Y(n6020) );
CLKINVX2TS U1559 ( .A(n611), .Y(n3684) );
NAND2X1TS U1560 ( .A(n4195), .B(n4196), .Y(n853) );
CLKINVX1TS U1561 ( .A(n4855), .Y(n707) );
CLKINVX2TS U1562 ( .A(n5757), .Y(n5795) );
INVX1TS U1563 ( .A(n6370), .Y(n6371) );
NOR2X1TS U1564 ( .A(n9610), .B(n9609), .Y(n9673) );
NAND2X1TS U1565 ( .A(n9590), .B(n9589), .Y(n9603) );
OR2X2TS U1566 ( .A(n9589), .B(n9590), .Y(n9606) );
INVX1TS U1567 ( .A(n9677), .Y(n9615) );
NAND2BXLTS U1568 ( .AN(n11728), .B(n11198), .Y(n11199) );
CLKINVX1TS U1569 ( .A(n6589), .Y(n4886) );
INVX2TS U1570 ( .A(n4224), .Y(n1200) );
CLKINVX2TS U1571 ( .A(n10073), .Y(n10074) );
OR2X1TS U1572 ( .A(n10905), .B(n10904), .Y(n10906) );
OR2X1TS U1573 ( .A(n9908), .B(n9907), .Y(n10951) );
NOR2X1TS U1574 ( .A(n9614), .B(n9613), .Y(n9677) );
ADDFHX2TS U1575 ( .A(n4817), .B(n4816), .CI(n4815), .CO(n5009), .S(n4800) );
INVX1TS U1576 ( .A(n5640), .Y(n5427) );
NOR2XLTS U1577 ( .A(n9798), .B(n11556), .Y(n10889) );
NAND2XLTS U1578 ( .A(n9795), .B(n11549), .Y(n10888) );
BUFX3TS U1579 ( .A(n8233), .Y(n463) );
INVX2TS U1580 ( .A(n5987), .Y(n2208) );
INVX1TS U1581 ( .A(n2877), .Y(n711) );
INVX3TS U1582 ( .A(n8427), .Y(n135) );
NOR2X1TS U1583 ( .A(n5988), .B(n5987), .Y(n8098) );
CLKINVX1TS U1584 ( .A(n5698), .Y(n671) );
INVX4TS U1585 ( .A(n272), .Y(n273) );
NAND2BX1TS U1586 ( .AN(n631), .B(n382), .Y(n3850) );
NAND2XLTS U1587 ( .A(n5546), .B(n5548), .Y(n5490) );
NAND2XLTS U1588 ( .A(n5545), .B(n5548), .Y(n5491) );
OAI21X2TS U1589 ( .A0(n3100), .A1(n3099), .B0(n3098), .Y(n840) );
INVX1TS U1590 ( .A(n5627), .Y(n5197) );
CLKINVX1TS U1591 ( .A(n3647), .Y(n3648) );
AND2X2TS U1592 ( .A(n10145), .B(n10144), .Y(n10149) );
CLKINVX1TS U1593 ( .A(n1327), .Y(n1325) );
INVX2TS U1594 ( .A(n6912), .Y(n3314) );
CLKINVX1TS U1595 ( .A(n6456), .Y(n6417) );
AO21X1TS U1596 ( .A0(n6729), .A1(n6728), .B0(n6727), .Y(n6761) );
CLKINVX1TS U1597 ( .A(n5482), .Y(n5128) );
INVX2TS U1598 ( .A(n675), .Y(n2279) );
INVX1TS U1599 ( .A(n4794), .Y(n4778) );
INVX2TS U1600 ( .A(n3738), .Y(n3754) );
XNOR2X2TS U1601 ( .A(n1146), .B(n2796), .Y(n3647) );
OR2X1TS U1602 ( .A(n9879), .B(n9878), .Y(n9868) );
INVX2TS U1603 ( .A(n10822), .Y(n9718) );
INVX1TS U1604 ( .A(n10840), .Y(n10844) );
NOR2X1TS U1605 ( .A(n1694), .B(n10036), .Y(n10321) );
NOR2X1TS U1606 ( .A(n2685), .B(n2684), .Y(n2686) );
INVX1TS U1607 ( .A(n2702), .Y(n1259) );
INVX1TS U1608 ( .A(n2748), .Y(n2607) );
NAND2X2TS U1609 ( .A(n2652), .B(n2651), .Y(n2680) );
CLKINVX1TS U1610 ( .A(n4667), .Y(n4652) );
INVX1TS U1611 ( .A(n5041), .Y(n257) );
NAND2BX1TS U1612 ( .AN(n531), .B(n260), .Y(n1761) );
INVX4TS U1613 ( .A(n2659), .Y(n323) );
INVX2TS U1614 ( .A(n8073), .Y(n2092) );
NAND2XLTS U1615 ( .A(n10274), .B(n11609), .Y(n10219) );
OAI21X1TS U1616 ( .A0(n9873), .A1(n11426), .B0(n11400), .Y(n9805) );
NAND2X1TS U1617 ( .A(n2674), .B(n2673), .Y(n2675) );
CLKINVX1TS U1618 ( .A(n4672), .Y(n4653) );
NOR2X1TS U1619 ( .A(n622), .B(n303), .Y(n2358) );
NAND2BXLTS U1620 ( .AN(n4570), .B(n475), .Y(n3777) );
CLKINVX1TS U1621 ( .A(n3090), .Y(n2946) );
INVX3TS U1622 ( .A(n622), .Y(n260) );
NOR2X1TS U1623 ( .A(n6886), .B(n6885), .Y(n6888) );
XOR2X1TS U1624 ( .A(n2537), .B(n5200), .Y(n2538) );
NAND2BXLTS U1625 ( .AN(n4600), .B(n238), .Y(n3835) );
CLKINVX1TS U1626 ( .A(n5185), .Y(n5165) );
OAI21X1TS U1627 ( .A0(n2694), .A1(n2693), .B0(n2692), .Y(n2695) );
NAND2X1TS U1628 ( .A(n2761), .B(n2604), .Y(n2748) );
NAND2BX1TS U1629 ( .AN(Data_A_i[27]), .B(n408), .Y(n1838) );
NAND2BX1TS U1630 ( .AN(n531), .B(n280), .Y(n1885) );
NAND2XLTS U1631 ( .A(n11200), .B(sgf_result_o[4]), .Y(n11201) );
NAND2X1TS U1632 ( .A(n11217), .B(sgf_result_o[7]), .Y(n11207) );
OR2X2TS U1633 ( .A(n11296), .B(n11264), .Y(n9979) );
XOR2X1TS U1634 ( .A(Data_B_i[51]), .B(Data_B_i[24]), .Y(n6885) );
NOR2X1TS U1635 ( .A(n1415), .B(n3225), .Y(n3226) );
INVX1TS U1636 ( .A(n2669), .Y(n2670) );
INVX4TS U1637 ( .A(n256), .Y(n133) );
INVX2TS U1638 ( .A(n282), .Y(n4025) );
INVX4TS U1639 ( .A(n7735), .Y(n622) );
XOR2X1TS U1640 ( .A(n5203), .B(Data_B_i[51]), .Y(n6886) );
CLKINVX2TS U1641 ( .A(n176), .Y(n450) );
NOR2X1TS U1642 ( .A(Data_B_i[25]), .B(Data_B_i[52]), .Y(n6876) );
BUFX3TS U1643 ( .A(Data_A_i[27]), .Y(n531) );
OR2X2TS U1644 ( .A(Data_B_i[41]), .B(Data_B_i[14]), .Y(n229) );
NAND2X1TS U1645 ( .A(n1019), .B(n9546), .Y(add_x_1_n70) );
NAND2X1TS U1646 ( .A(add_x_3_n171), .B(n9492), .Y(add_x_3_n157) );
INVX1TS U1647 ( .A(n9500), .Y(add_x_3_n181) );
INVX2TS U1648 ( .A(n9465), .Y(n9467) );
NAND2X2TS U1649 ( .A(n9359), .B(n7385), .Y(n9546) );
INVX2TS U1650 ( .A(n9711), .Y(add_x_1_n744) );
NOR2X1TS U1651 ( .A(add_x_2_n138), .B(n9695), .Y(add_x_2_n131) );
INVX1TS U1652 ( .A(n9508), .Y(n9498) );
NAND2X2TS U1653 ( .A(n8471), .B(n8470), .Y(add_x_3_n125) );
XOR2X1TS U1654 ( .A(n10790), .B(n10789), .Y(n10791) );
NAND3X2TS U1655 ( .A(n1359), .B(n1358), .C(n1357), .Y(n1356) );
NAND2X2TS U1656 ( .A(n8534), .B(n8533), .Y(n7988) );
XOR2X1TS U1657 ( .A(n10528), .B(n146), .Y(n10529) );
XOR2X1TS U1658 ( .A(n10522), .B(n145), .Y(n10523) );
NAND2X2TS U1659 ( .A(n8191), .B(n528), .Y(n1358) );
NAND2X2TS U1660 ( .A(n6852), .B(n6851), .Y(n8495) );
NAND2X4TS U1661 ( .A(n1487), .B(n1486), .Y(n9376) );
NAND2X2TS U1662 ( .A(n1546), .B(n1666), .Y(n8534) );
INVX2TS U1663 ( .A(n8119), .Y(n1540) );
INVX2TS U1664 ( .A(n9336), .Y(n9406) );
NOR2X1TS U1665 ( .A(n10763), .B(n10519), .Y(n10521) );
NOR2X1TS U1666 ( .A(n10796), .B(n10525), .Y(n10527) );
NAND2X2TS U1667 ( .A(n9327), .B(n9326), .Y(n9371) );
NAND2X1TS U1668 ( .A(n10795), .B(n10517), .Y(n10519) );
XOR2X1TS U1669 ( .A(n9017), .B(n9016), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[15]) );
XOR2X1TS U1670 ( .A(n9025), .B(n9024), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[16]) );
AOI21X2TS U1671 ( .A0(n8911), .A1(n8913), .B0(n3153), .Y(n1068) );
NAND2X2TS U1672 ( .A(n8886), .B(n8885), .Y(n8887) );
NAND2X2TS U1673 ( .A(n9260), .B(n9259), .Y(n9409) );
NOR2X1TS U1674 ( .A(n10794), .B(n146), .Y(n10517) );
AND2X2TS U1675 ( .A(n7276), .B(n7275), .Y(n222) );
OAI21X1TS U1676 ( .A0(n9431), .A1(n7235), .B0(n7234), .Y(n7236) );
CLKINVX1TS U1677 ( .A(n9505), .Y(add_x_3_n61) );
INVX1TS U1678 ( .A(n8353), .Y(n1458) );
NOR2X1TS U1679 ( .A(n1617), .B(n6675), .Y(n6676) );
INVX1TS U1680 ( .A(EVEN1_Q_left[18]), .Y(n8153) );
NOR2X1TS U1681 ( .A(n10799), .B(n10616), .Y(n10617) );
NOR2X1TS U1682 ( .A(n10799), .B(n10798), .Y(n10800) );
NOR2X1TS U1683 ( .A(n10780), .B(n10779), .Y(n10781) );
CLKINVX1TS U1684 ( .A(n11113), .Y(n11101) );
CLKINVX1TS U1685 ( .A(n11112), .Y(n11103) );
NOR2X1TS U1686 ( .A(n10780), .B(n10649), .Y(n10508) );
NOR2X1TS U1687 ( .A(n10780), .B(n146), .Y(n10516) );
NAND2X1TS U1688 ( .A(n10547), .B(n10751), .Y(n10533) );
CLKINVX1TS U1689 ( .A(n10588), .Y(n10537) );
INVX2TS U1690 ( .A(n11173), .Y(n10268) );
CLKINVX1TS U1691 ( .A(n10540), .Y(n10542) );
CLKINVX1TS U1692 ( .A(n11172), .Y(n11175) );
CLKINVX1TS U1693 ( .A(n11139), .Y(n11140) );
CLKINVX1TS U1694 ( .A(n11180), .Y(n11182) );
CLKINVX1TS U1695 ( .A(n11141), .Y(n11144) );
NOR2X1TS U1696 ( .A(n10799), .B(n10673), .Y(n10674) );
NAND2X1TS U1697 ( .A(n11131), .B(n11130), .Y(n11132) );
CLKINVX1TS U1698 ( .A(n9668), .Y(add_x_2_n61) );
INVX2TS U1699 ( .A(n4536), .Y(n4891) );
XOR2X1TS U1700 ( .A(n11066), .B(n11062), .Y(n11063) );
CLKINVX1TS U1701 ( .A(n11148), .Y(n11150) );
INVX2TS U1702 ( .A(n10494), .Y(n11149) );
CLKINVX1TS U1703 ( .A(n11166), .Y(n11168) );
XOR2X1TS U1704 ( .A(n11059), .B(n11058), .Y(n11060) );
CLKINVX1TS U1705 ( .A(n11129), .Y(n11131) );
CLKINVX1TS U1706 ( .A(n11143), .Y(n11135) );
INVX2TS U1707 ( .A(n10594), .Y(n10751) );
CLKINVX1TS U1708 ( .A(n9383), .Y(n8972) );
CLKINVX1TS U1709 ( .A(n9393), .Y(n8971) );
OAI21X2TS U1710 ( .A0(n6268), .A1(n6267), .B0(n6266), .Y(n779) );
XOR2X2TS U1711 ( .A(n1084), .B(n7881), .Y(n8880) );
OR2X2TS U1712 ( .A(n8718), .B(n8711), .Y(n8720) );
CLKINVX1TS U1713 ( .A(n9506), .Y(add_x_3_n88) );
NAND2X2TS U1714 ( .A(n7205), .B(n7204), .Y(n8474) );
XNOR2X2TS U1715 ( .A(n8605), .B(n8604), .Y(n1118) );
INVX1TS U1716 ( .A(n6746), .Y(n5935) );
CLKINVX2TS U1717 ( .A(n8817), .Y(n9040) );
XOR2X1TS U1718 ( .A(n4535), .B(n4534), .Y(n4537) );
CLKINVX1TS U1719 ( .A(n6674), .Y(n1619) );
CLKINVX1TS U1720 ( .A(n9019), .Y(n9001) );
CLKINVX1TS U1721 ( .A(n8980), .Y(n8981) );
INVX2TS U1722 ( .A(n8542), .Y(n8544) );
INVX2TS U1723 ( .A(n8553), .Y(n8554) );
CLKINVX1TS U1724 ( .A(n9672), .Y(add_x_2_n88) );
INVX1TS U1725 ( .A(n6014), .Y(n6016) );
INVX1TS U1726 ( .A(n9474), .Y(n9476) );
INVX1TS U1727 ( .A(n7687), .Y(n7278) );
XNOR2X4TS U1728 ( .A(n10319), .B(n10318), .Y(n10507) );
CLKINVX1TS U1729 ( .A(n9435), .Y(n7230) );
CLKINVX1TS U1730 ( .A(n9123), .Y(EVEN1_Q_left[14]) );
INVX2TS U1731 ( .A(n8371), .Y(n8373) );
INVX1TS U1732 ( .A(n8150), .Y(n7713) );
NOR2X4TS U1733 ( .A(n5931), .B(n5932), .Y(n6014) );
NOR2X2TS U1734 ( .A(n1620), .B(n7911), .Y(n6674) );
CLKINVX1TS U1735 ( .A(n8330), .Y(n1103) );
XOR3X2TS U1736 ( .A(n8869), .B(n8868), .C(n8867), .Y(n8870) );
OR2X2TS U1737 ( .A(n9382), .B(n9389), .Y(n9392) );
AOI21X1TS U1738 ( .A0(n9174), .A1(n1496), .B0(n1495), .Y(n1494) );
NAND2X2TS U1739 ( .A(n1652), .B(n1651), .Y(n4942) );
CLKINVX1TS U1740 ( .A(n8996), .Y(n8998) );
CLKINVX2TS U1741 ( .A(n8162), .Y(n1003) );
AO21X4TS U1742 ( .A0(n10313), .A1(n10312), .B0(n10311), .Y(n10319) );
OAI2BB1X2TS U1743 ( .A0N(n6476), .A1N(n6477), .B0(n1628), .Y(n6615) );
XNOR2X1TS U1744 ( .A(n1195), .B(n1193), .Y(n4451) );
CLKINVX1TS U1745 ( .A(n9495), .Y(add_x_3_n64) );
XOR2X2TS U1746 ( .A(n8616), .B(n8615), .Y(n1102) );
CLKINVX1TS U1747 ( .A(n9494), .Y(add_x_3_n46) );
NAND2X2TS U1748 ( .A(n4352), .B(n4351), .Y(n9289) );
NAND2X2TS U1749 ( .A(n6612), .B(n6611), .Y(n8372) );
NAND2X1TS U1750 ( .A(n9028), .B(n9027), .Y(n9029) );
OAI2BB1X2TS U1751 ( .A0N(n5400), .A1N(n5399), .B0(n1451), .Y(n5932) );
CLKINVX1TS U1752 ( .A(n9493), .Y(add_x_3_n93) );
NAND2X2TS U1753 ( .A(n1653), .B(n4726), .Y(n984) );
INVX1TS U1754 ( .A(n6996), .Y(n1243) );
CLKINVX1TS U1755 ( .A(n9709), .Y(add_x_2_n46) );
XOR2X2TS U1756 ( .A(n6673), .B(n6672), .Y(n8470) );
CLKINVX1TS U1757 ( .A(n9659), .Y(add_x_2_n93) );
CLKINVX1TS U1758 ( .A(n9660), .Y(add_x_2_n64) );
ADDFHX2TS U1759 ( .A(n3115), .B(n3114), .CI(n3113), .CO(n3209), .S(n3149) );
OAI21X2TS U1760 ( .A0(n10092), .A1(n10402), .B0(n10091), .Y(n10254) );
NAND2X2TS U1761 ( .A(n6843), .B(n7951), .Y(n6844) );
CLKINVX1TS U1762 ( .A(n8973), .Y(n8933) );
OR2X4TS U1763 ( .A(n6625), .B(n6624), .Y(n6603) );
NAND2X1TS U1764 ( .A(n8803), .B(n8802), .Y(n9027) );
AOI21X1TS U1765 ( .A0(n7949), .A1(n7948), .B0(n7947), .Y(n7950) );
OR2X2TS U1766 ( .A(n8780), .B(n8779), .Y(n8845) );
OAI2BB1X1TS U1767 ( .A0N(n6586), .A1N(n6585), .B0(n1621), .Y(n6625) );
OAI21X1TS U1768 ( .A0(n8057), .A1(n2562), .B0(n7194), .Y(n2563) );
INVX2TS U1769 ( .A(n8780), .Y(n2992) );
XNOR2X1TS U1770 ( .A(n1640), .B(n5078), .Y(n5083) );
XOR2X1TS U1771 ( .A(n3217), .B(n1148), .Y(n3211) );
XOR2X1TS U1772 ( .A(n9704), .B(n9576), .Y(n1722) );
ADDFHX2TS U1773 ( .A(n7600), .B(n7599), .CI(n7598), .CO(n7479), .S(n7621) );
CLKINVX1TS U1774 ( .A(n8931), .Y(n1533) );
INVX1TS U1775 ( .A(n9175), .Y(n9177) );
NAND2X2TS U1776 ( .A(n2553), .B(n2552), .Y(n5811) );
CLKINVX1TS U1777 ( .A(n11030), .Y(n10355) );
OAI21X1TS U1778 ( .A0(n9149), .A1(n4179), .B0(n4178), .Y(n9124) );
OAI2BB1X2TS U1779 ( .A0N(n5077), .A1N(n1040), .B0(n1039), .Y(n6236) );
OAI21X1TS U1780 ( .A0(n7760), .A1(n6846), .B0(n7755), .Y(n6850) );
OAI2BB1X1TS U1781 ( .A0N(n5677), .A1N(n5676), .B0(n1371), .Y(n5905) );
OR2X2TS U1782 ( .A(n8724), .B(n8723), .Y(n8726) );
CLKINVX1TS U1783 ( .A(n2473), .Y(n2370) );
CLKINVX1TS U1784 ( .A(n2467), .Y(n2366) );
OAI21X1TS U1785 ( .A0(n6585), .A1(n6586), .B0(n6584), .Y(n1621) );
OAI2BB1X2TS U1786 ( .A0N(n1010), .A1N(n1682), .B0(n1681), .Y(n806) );
CLKINVX1TS U1787 ( .A(n4421), .Y(n4266) );
XNOR2X1TS U1788 ( .A(n944), .B(n6225), .Y(n6251) );
CLKINVX1TS U1789 ( .A(n9569), .Y(n9554) );
XOR2X2TS U1790 ( .A(n1537), .B(n3298), .Y(n3544) );
NOR2X4TS U1791 ( .A(n1384), .B(n1383), .Y(n2238) );
CLKINVX1TS U1792 ( .A(n9564), .Y(n9553) );
NAND2X1TS U1793 ( .A(n9570), .B(n9564), .Y(n9573) );
INVX1TS U1794 ( .A(n8376), .Y(n9459) );
INVX1TS U1795 ( .A(n4512), .Y(n795) );
INVX1TS U1796 ( .A(n4513), .Y(n794) );
AO21X1TS U1797 ( .A0(n10336), .A1(n10327), .B0(n10326), .Y(n10331) );
CLKINVX1TS U1798 ( .A(n10298), .Y(n10235) );
XOR2X1TS U1799 ( .A(n10336), .B(n10335), .Y(n10354) );
CLKINVX1TS U1800 ( .A(n10478), .Y(n10258) );
OAI21X2TS U1801 ( .A0(n6702), .A1(n6703), .B0(n6701), .Y(n977) );
INVX2TS U1802 ( .A(n2087), .Y(n2076) );
XOR2X2TS U1803 ( .A(n4955), .B(n884), .Y(n883) );
INVX2TS U1804 ( .A(n4298), .Y(n4308) );
NOR2X1TS U1805 ( .A(n7790), .B(n7792), .Y(n7796) );
INVX1TS U1806 ( .A(n6488), .Y(n1626) );
ADDFHX2TS U1807 ( .A(n5674), .B(n5673), .CI(n5672), .CO(n5888), .S(n5675) );
OAI21X1TS U1808 ( .A0(n9567), .A1(n9566), .B0(n9565), .Y(n9568) );
NOR2X1TS U1809 ( .A(n9563), .B(n9567), .Y(n9570) );
OAI21X1TS U1810 ( .A0(n7395), .A1(n7397), .B0(n7398), .Y(n6664) );
OAI2BB1X2TS U1811 ( .A0N(n4799), .A1N(n4798), .B0(n1541), .Y(n5014) );
CLKINVX1TS U1812 ( .A(n10467), .Y(n10480) );
CLKINVX1TS U1813 ( .A(n10479), .Y(n10255) );
INVX1TS U1814 ( .A(n7298), .Y(n6685) );
CLKINVX1TS U1815 ( .A(n9675), .Y(n9584) );
CLKINVX1TS U1816 ( .A(n9687), .Y(n9586) );
CLKINVX1TS U1817 ( .A(n6448), .Y(n1661) );
XOR2X1TS U1818 ( .A(n7750), .B(n1355), .Y(n1354) );
BUFX3TS U1819 ( .A(n8244), .Y(n545) );
INVX4TS U1820 ( .A(n5340), .Y(n5355) );
CLKINVX1TS U1821 ( .A(n9517), .Y(n7319) );
CLKINVX1TS U1822 ( .A(n7299), .Y(n7289) );
CLKINVX1TS U1823 ( .A(n9527), .Y(n7321) );
CLKINVX1TS U1824 ( .A(n1590), .Y(n1587) );
XOR2X2TS U1825 ( .A(n5057), .B(n5058), .Y(n681) );
INVX1TS U1826 ( .A(n6125), .Y(n716) );
CLKINVX1TS U1827 ( .A(n7337), .Y(n7340) );
ADDFHX1TS U1828 ( .A(n6554), .B(n6553), .CI(n6552), .CO(n6582), .S(n6564) );
CLKINVX1TS U1829 ( .A(n10452), .Y(n10418) );
CLKINVX1TS U1830 ( .A(n10456), .Y(n10417) );
CLKINVX1TS U1831 ( .A(n10263), .Y(n10264) );
INVX2TS U1832 ( .A(n10230), .Y(n10233) );
AOI2BB1X1TS U1833 ( .A0N(n10987), .A1N(n10986), .B0(n10985), .Y(n10988) );
CLKINVX1TS U1834 ( .A(n10673), .Y(n10593) );
INVX2TS U1835 ( .A(n5862), .Y(n782) );
NAND2X2TS U1836 ( .A(n4594), .B(n4595), .Y(n9137) );
INVX1TS U1837 ( .A(n9160), .Y(n9150) );
CLKINVX1TS U1838 ( .A(n7194), .Y(n7197) );
CLKINVX1TS U1839 ( .A(n2469), .Y(n2391) );
INVX1TS U1840 ( .A(n372), .Y(n1497) );
OAI21X1TS U1841 ( .A0(n5992), .A1(n2277), .B0(n1342), .Y(n2455) );
NAND2BX1TS U1842 ( .AN(n10252), .B(n10251), .Y(n10253) );
AOI2BB1X1TS U1843 ( .A0N(n10970), .A1N(n10969), .B0(n10968), .Y(n10971) );
INVX2TS U1844 ( .A(n10088), .Y(n10434) );
CLKINVX1TS U1845 ( .A(n10386), .Y(n10388) );
NAND2X2TS U1846 ( .A(n360), .B(n2704), .Y(n7560) );
INVX4TS U1847 ( .A(n4659), .Y(n4680) );
XNOR2X2TS U1848 ( .A(n1309), .B(n4858), .Y(n4840) );
INVX2TS U1849 ( .A(n5470), .Y(n5956) );
INVX1TS U1850 ( .A(n4383), .Y(n758) );
NOR2X1TS U1851 ( .A(n6801), .B(n6802), .Y(n6846) );
AND2X2TS U1852 ( .A(n4467), .B(n4492), .Y(n9182) );
XOR2X2TS U1853 ( .A(n1032), .B(n1034), .Y(n872) );
INVX2TS U1854 ( .A(n5561), .Y(n5716) );
INVX1TS U1855 ( .A(n7447), .Y(n7448) );
OAI21X1TS U1856 ( .A0(n4494), .A1(n4493), .B0(n4492), .Y(n1548) );
INVX4TS U1857 ( .A(n353), .Y(n134) );
NAND2X4TS U1858 ( .A(n3384), .B(n416), .Y(n8425) );
OAI21X2TS U1859 ( .A0(n4068), .A1(n4069), .B0(n924), .Y(n923) );
NOR2X1TS U1860 ( .A(n6663), .B(n6662), .Y(n7397) );
CLKINVX1TS U1861 ( .A(n7927), .Y(n6661) );
OAI21X1TS U1862 ( .A0(n8653), .A1(n8650), .B0(n8651), .Y(n9119) );
NAND2XLTS U1863 ( .A(n10393), .B(n10392), .Y(n10394) );
CLKINVX2TS U1864 ( .A(n10072), .Y(n10075) );
AND2X2TS U1865 ( .A(n10117), .B(n10116), .Y(n10423) );
CLKINVX1TS U1866 ( .A(n10433), .Y(n10435) );
CLKINVX1TS U1867 ( .A(n10368), .Y(n10369) );
NAND2XLTS U1868 ( .A(n1704), .B(n9851), .Y(n10992) );
NAND2X2TS U1869 ( .A(n854), .B(n853), .Y(n4595) );
INVX2TS U1870 ( .A(n9515), .Y(n7364) );
CLKINVX1TS U1871 ( .A(n9602), .Y(n9605) );
XOR2X2TS U1872 ( .A(n5599), .B(n667), .Y(n6848) );
CLKINVX1TS U1873 ( .A(n5106), .Y(n3045) );
XOR2X2TS U1874 ( .A(n1556), .B(n4065), .Y(n924) );
INVX1TS U1875 ( .A(n3527), .Y(n2987) );
XOR2X1TS U1876 ( .A(n8659), .B(n8658), .Y(n11202) );
OAI2BB1X2TS U1877 ( .A0N(n4024), .A1N(n4023), .B0(n1551), .Y(n4045) );
INVX2TS U1878 ( .A(n6796), .Y(n5796) );
NAND2XLTS U1879 ( .A(n9888), .B(n9887), .Y(n10965) );
INVX1TS U1880 ( .A(n10951), .Y(n10952) );
AND2X2TS U1881 ( .A(n10315), .B(n11367), .Y(n10316) );
AO21XLTS U1882 ( .A0(n10341), .A1(n10337), .B0(n10024), .Y(n10025) );
AND2X2TS U1883 ( .A(n10029), .B(n10001), .Y(n10329) );
INVX2TS U1884 ( .A(n6186), .Y(n6187) );
INVX2TS U1885 ( .A(n4130), .Y(n4409) );
CLKINVX1TS U1886 ( .A(n1589), .Y(n1586) );
OAI21X2TS U1887 ( .A0(n4023), .A1(n4024), .B0(n4022), .Y(n1551) );
OAI21XLTS U1888 ( .A0(n1958), .A1(n1959), .B0(n1957), .Y(n1238) );
OAI21X1TS U1889 ( .A0(n2128), .A1(n2129), .B0(n2127), .Y(n1452) );
NAND2X1TS U1890 ( .A(n1507), .B(n5553), .Y(n1503) );
OAI21X1TS U1891 ( .A0(n2859), .A1(n2858), .B0(n2857), .Y(n2861) );
XOR2X1TS U1892 ( .A(n1957), .B(n1239), .Y(n1968) );
INVX1TS U1893 ( .A(n1658), .Y(n1656) );
XOR2X2TS U1894 ( .A(n696), .B(n1963), .Y(n1966) );
OAI21X1TS U1895 ( .A0(n4111), .A1(n4112), .B0(n4110), .Y(n859) );
XNOR2X1TS U1896 ( .A(n4190), .B(n4189), .Y(n654) );
OAI21X1TS U1897 ( .A0(n4189), .A1(n4190), .B0(n4188), .Y(n1035) );
INVX2TS U1898 ( .A(n6331), .Y(n3824) );
ADDFHX2TS U1899 ( .A(n4086), .B(n4085), .CI(n4084), .CO(n4068), .S(n4180) );
INVX1TS U1900 ( .A(n2277), .Y(n2319) );
NAND2BXLTS U1901 ( .AN(n10333), .B(n10332), .Y(n10334) );
CLKINVX1TS U1902 ( .A(n10725), .Y(n10727) );
NAND2XLTS U1903 ( .A(n10168), .B(n1698), .Y(n10928) );
OAI2BB1X2TS U1904 ( .A0N(n3781), .A1N(n3780), .B0(n1440), .Y(n4130) );
NAND2X6TS U1905 ( .A(n1045), .B(n1044), .Y(n4992) );
CLKINVX2TS U1906 ( .A(n9613), .Y(n6775) );
INVX4TS U1907 ( .A(n591), .Y(n593) );
INVX2TS U1908 ( .A(n663), .Y(n5172) );
XOR2X1TS U1909 ( .A(n2488), .B(n162), .Y(n2489) );
XOR2X1TS U1910 ( .A(n5696), .B(n673), .Y(n5754) );
INVX2TS U1911 ( .A(n7349), .Y(n6483) );
XOR2X1TS U1912 ( .A(n1958), .B(n1959), .Y(n1239) );
XNOR2X1TS U1913 ( .A(n6597), .B(n4885), .Y(n6589) );
XOR2X1TS U1914 ( .A(n851), .B(n4136), .Y(n4196) );
XOR2X1TS U1915 ( .A(n1764), .B(n704), .Y(n1957) );
INVX2TS U1916 ( .A(n3157), .Y(n1153) );
ADDFHX2TS U1917 ( .A(n4052), .B(n4051), .CI(n4050), .CO(n4022), .S(n4069) );
INVX2TS U1918 ( .A(n6529), .Y(n6562) );
INVX2TS U1919 ( .A(n10645), .Y(n10161) );
NAND2XLTS U1920 ( .A(n10648), .B(n10657), .Y(n10683) );
XOR2X1TS U1921 ( .A(n1689), .B(n10042), .Y(n9997) );
NOR2X1TS U1922 ( .A(n10017), .B(n10016), .Y(n10338) );
AND2X2TS U1923 ( .A(n10007), .B(n10324), .Y(n10333) );
INVX2TS U1924 ( .A(n10657), .Y(n10136) );
NAND2XLTS U1925 ( .A(n9808), .B(n11550), .Y(n10926) );
NOR2X1TS U1926 ( .A(n10016), .B(n10020), .Y(n9780) );
INVX1TS U1927 ( .A(n11193), .Y(n11194) );
INVX2TS U1928 ( .A(n3471), .Y(n3472) );
XOR2X2TS U1929 ( .A(n870), .B(n4053), .Y(n4086) );
XNOR2X1TS U1930 ( .A(n2487), .B(n1335), .Y(n162) );
INVX1TS U1931 ( .A(n6050), .Y(n6051) );
INVX2TS U1932 ( .A(n1736), .Y(n1137) );
NAND2BX1TS U1933 ( .AN(n629), .B(n446), .Y(n2270) );
CLKINVX1TS U1934 ( .A(n3675), .Y(n3676) );
XOR2X1TS U1935 ( .A(n1405), .B(n4027), .Y(n4041) );
CLKINVX1TS U1936 ( .A(n4757), .Y(n1635) );
NAND2BX1TS U1937 ( .AN(n5624), .B(n385), .Y(n2047) );
XOR2X1TS U1938 ( .A(n2411), .B(n2412), .Y(n2293) );
XOR2X1TS U1939 ( .A(n5548), .B(n5547), .Y(n5590) );
XOR2X1TS U1940 ( .A(n5697), .B(n5698), .Y(n673) );
CLKINVX1TS U1941 ( .A(n5023), .Y(n3938) );
INVX2TS U1942 ( .A(n5637), .Y(n5337) );
NAND2X4TS U1943 ( .A(n3814), .B(n225), .Y(n1045) );
INVX1TS U1944 ( .A(n5697), .Y(n672) );
INVX2TS U1945 ( .A(n130), .Y(n502) );
INVX2TS U1946 ( .A(n10776), .Y(n9960) );
AND2X2TS U1947 ( .A(n9776), .B(n9775), .Y(n10016) );
NAND2BX1TS U1948 ( .AN(n9766), .B(n9765), .Y(n9772) );
OR2X2TS U1949 ( .A(n9939), .B(n9938), .Y(n10018) );
INVX2TS U1950 ( .A(n10660), .Y(n10114) );
NAND2BXLTS U1951 ( .AN(n630), .B(n3775), .Y(n3769) );
INVX2TS U1952 ( .A(n3398), .Y(n272) );
INVX1TS U1953 ( .A(n4122), .Y(n3898) );
INVX1TS U1954 ( .A(n6333), .Y(n3878) );
ADDFX1TS U1955 ( .A(n4202), .B(n4201), .CI(n4200), .CO(n4230), .S(n4221) );
NAND2XLTS U1956 ( .A(n9531), .B(n1692), .Y(n9532) );
ADDFHX1TS U1957 ( .A(n4778), .B(n4777), .CI(n4776), .CO(n4787), .S(n4770) );
INVX2TS U1958 ( .A(n936), .Y(n935) );
XNOR2X1TS U1959 ( .A(n163), .B(n2432), .Y(n2409) );
NAND2X2TS U1960 ( .A(n8253), .B(n6889), .Y(n8255) );
OR2X2TS U1961 ( .A(n4120), .B(n4119), .Y(n213) );
AO21X1TS U1962 ( .A0(n10109), .A1(n10095), .B0(n10094), .Y(n10096) );
AO21X1TS U1963 ( .A0(n10109), .A1(n10108), .B0(n10107), .Y(n10110) );
AO21X1TS U1964 ( .A0(n10109), .A1(n11303), .B0(n11286), .Y(n9949) );
AOI2BB1XLTS U1965 ( .A0N(n9880), .A1N(n9879), .B0(n9878), .Y(n9881) );
AND2X2TS U1966 ( .A(n9758), .B(n9757), .Y(n9766) );
OR2X2TS U1967 ( .A(n2614), .B(n2763), .Y(n2713) );
INVX1TS U1968 ( .A(n4761), .Y(n4528) );
INVX4TS U1969 ( .A(n1286), .Y(n1289) );
OAI21X1TS U1970 ( .A0(n4237), .A1(n144), .B0(n899), .Y(n4257) );
NOR2X1TS U1971 ( .A(n143), .B(n2382), .Y(n1336) );
NAND2X1TS U1972 ( .A(n2869), .B(n2868), .Y(n2870) );
XOR2XLTS U1973 ( .A(n2942), .B(n3085), .Y(n2943) );
NAND2BX1TS U1974 ( .AN(n4096), .B(n240), .Y(n4095) );
CLKINVX1TS U1975 ( .A(n6093), .Y(n6074) );
CLKINVX1TS U1976 ( .A(n6094), .Y(n6075) );
INVX1TS U1977 ( .A(n4984), .Y(n4675) );
CLKINVX1TS U1978 ( .A(n3768), .Y(n4980) );
OAI21X1TS U1979 ( .A0(n9796), .A1(n9889), .B0(n9873), .Y(n9790) );
CLKINVX1TS U1980 ( .A(n9809), .Y(n9810) );
AND2X2TS U1981 ( .A(n9755), .B(n9754), .Y(n9768) );
AND2X2TS U1982 ( .A(n9760), .B(n9759), .Y(n9767) );
NAND2XLTS U1983 ( .A(n9959), .B(n11525), .Y(n10873) );
OR2X2TS U1984 ( .A(n4983), .B(n4985), .Y(n4988) );
AO21X1TS U1985 ( .A0(n5117), .A1(n5585), .B0(n1436), .Y(n5215) );
CLKINVX3TS U1986 ( .A(n6086), .Y(n1286) );
NAND2X4TS U1987 ( .A(n1078), .B(n3771), .Y(n3738) );
XOR2X2TS U1988 ( .A(n5150), .B(n5149), .Y(n7779) );
NOR2X1TS U1989 ( .A(n621), .B(n4025), .Y(n4201) );
OAI22X1TS U1990 ( .A0(n4444), .A1(n4443), .B0(n573), .B1(n133), .Y(n4529) );
NOR2X1TS U1991 ( .A(n2659), .B(n2658), .Y(n2660) );
NAND2X2TS U1992 ( .A(n185), .B(n3773), .Y(n3768) );
XOR2X1TS U1993 ( .A(n1375), .B(n5205), .Y(n1374) );
INVX2TS U1994 ( .A(n6710), .Y(n2570) );
OR2X2TS U1995 ( .A(n6882), .B(n6881), .Y(n6883) );
AO21X1TS U1996 ( .A0(n2384), .A1(n562), .B0(n517), .Y(n2487) );
NAND2X2TS U1997 ( .A(n2008), .B(n2024), .Y(n2009) );
BUFX6TS U1998 ( .A(n5571), .Y(n332) );
OAI21X2TS U1999 ( .A0(n3364), .A1(n3360), .B0(n3365), .Y(n1213) );
NAND2XLTS U2000 ( .A(n10033), .B(n11526), .Y(n10846) );
INVX2TS U2001 ( .A(n9889), .Y(n9871) );
XOR3X2TS U2002 ( .A(n11332), .B(n9778), .C(n9777), .Y(n9760) );
XNOR2X2TS U2003 ( .A(n3761), .B(n3760), .Y(n3792) );
INVX4TS U2004 ( .A(n619), .Y(n621) );
NAND2X4TS U2005 ( .A(n1301), .B(n6084), .Y(n6086) );
CLKINVX2TS U2006 ( .A(n6908), .Y(n3315) );
NAND2X4TS U2007 ( .A(n1646), .B(n1290), .Y(n5041) );
NAND2X2TS U2008 ( .A(n3729), .B(n449), .Y(n3730) );
INVX2TS U2009 ( .A(n526), .Y(n6727) );
NAND2BXLTS U2010 ( .AN(n276), .B(n521), .Y(n4060) );
XOR2X1TS U2011 ( .A(n524), .B(Data_B_i[45]), .Y(n2685) );
CLKINVX1TS U2012 ( .A(n3096), .Y(n2948) );
INVX2TS U2013 ( .A(n1697), .Y(n1351) );
INVX1TS U2014 ( .A(n3803), .Y(n1188) );
NAND2BXLTS U2015 ( .AN(n276), .B(n509), .Y(n4004) );
AND2X2TS U2016 ( .A(n11305), .B(n11298), .Y(n9999) );
OAI21X1TS U2017 ( .A0(n11623), .A1(n11579), .B0(n11580), .Y(n10100) );
AO21X1TS U2018 ( .A0(n11466), .A1(n11435), .B0(n11436), .Y(n9727) );
OAI21X2TS U2019 ( .A0(n11440), .A1(n11416), .B0(n11417), .Y(n9895) );
INVX2TS U2020 ( .A(n2845), .Y(n2795) );
INVX2TS U2021 ( .A(n2850), .Y(n2852) );
NAND2X1TS U2022 ( .A(Data_B_i[18]), .B(n662), .Y(n1060) );
OAI21X1TS U2023 ( .A0(Data_B_i[49]), .A1(Data_B_i[22]), .B0(n238), .Y(n3224)
);
INVX1TS U2024 ( .A(n3344), .Y(n3346) );
XOR2X1TS U2025 ( .A(Data_B_i[43]), .B(n712), .Y(n2658) );
NOR2X2TS U2026 ( .A(n3739), .B(n3752), .Y(n1054) );
INVX2TS U2027 ( .A(n4397), .Y(n3735) );
INVX3TS U2028 ( .A(n1565), .Y(n520) );
INVX1TS U2029 ( .A(n2177), .Y(n2028) );
XNOR2X1TS U2030 ( .A(n3755), .B(n3746), .Y(n3750) );
INVX2TS U2031 ( .A(n7734), .Y(n1642) );
INVX2TS U2032 ( .A(n3815), .Y(n3817) );
INVX2TS U2033 ( .A(n4393), .Y(n3725) );
XOR2X1TS U2034 ( .A(Data_B_i[53]), .B(Data_B_i[26]), .Y(n6881) );
NAND2X2TS U2035 ( .A(Data_B_i[30]), .B(Data_B_i[3]), .Y(n2621) );
INVX4TS U2036 ( .A(Data_B_i[38]), .Y(n518) );
AOI21X1TS U2037 ( .A0(add_x_1_n744), .A1(n1019), .B0(n7386), .Y(add_x_1_n739) );
INVX1TS U2038 ( .A(n9550), .Y(add_x_1_n799) );
NAND2X1TS U2039 ( .A(n1381), .B(n9350), .Y(DP_OP_62J6_125_4796_n287) );
NAND2X1TS U2040 ( .A(n226), .B(n11730), .Y(n11732) );
XOR2X2TS U2041 ( .A(n792), .B(n5092), .Y(DP_OP_62J6_125_4796_n642) );
INVX1TS U2042 ( .A(DP_OP_62J6_125_4796_n282), .Y(DP_OP_62J6_125_4796_n409)
);
INVX1TS U2043 ( .A(add_x_3_n166), .Y(n9499) );
OAI21X1TS U2044 ( .A0(add_x_3_n125), .A1(n9508), .B0(n9507), .Y(add_x_3_n4)
);
OAI21X1TS U2045 ( .A0(n9465), .A1(add_x_3_n169), .B0(n9466), .Y(n9464) );
OAI21X1TS U2046 ( .A0(n9510), .A1(n9488), .B0(n9487), .Y(n9489) );
OAI21X1TS U2047 ( .A0(n9671), .A1(n9670), .B0(n9669), .Y(add_x_2_n190) );
CLKINVX1TS U2048 ( .A(add_x_2_n117), .Y(n9625) );
NAND2BX1TS U2049 ( .AN(n11729), .B(n10815), .Y(n10816) );
INVX1TS U2050 ( .A(n9063), .Y(DP_OP_62J6_125_4796_n294) );
NOR2X2TS U2051 ( .A(n8219), .B(n8218), .Y(n9537) );
INVX1TS U2052 ( .A(add_x_2_n141), .Y(n7803) );
INVX3TS U2053 ( .A(n8532), .Y(n9670) );
INVX1TS U2054 ( .A(n9503), .Y(n1647) );
XOR2X2TS U2055 ( .A(n8213), .B(n8212), .Y(n8219) );
XOR2X2TS U2056 ( .A(n7393), .B(n7392), .Y(n7403) );
INVX4TS U2057 ( .A(n1173), .Y(n7378) );
NAND2X2TS U2058 ( .A(n1649), .B(n1648), .Y(n9504) );
NOR2X2TS U2059 ( .A(n1720), .B(DP_OP_62J6_125_4796_n696), .Y(n9547) );
CLKINVX1TS U2060 ( .A(DP_OP_59J6_122_190_n111), .Y(DP_OP_59J6_122_190_n109)
);
XOR2X2TS U2061 ( .A(n7248), .B(n7247), .Y(n7250) );
OAI21X1TS U2062 ( .A0(n1029), .A1(n8676), .B0(n8675), .Y(n1028) );
INVX1TS U2063 ( .A(n8534), .Y(n683) );
NAND2X4TS U2064 ( .A(n1313), .B(n1219), .Y(n8532) );
NOR2X2TS U2065 ( .A(n9629), .B(n8496), .Y(add_x_2_n143) );
XOR2X1TS U2066 ( .A(n10591), .B(n10590), .Y(n10592) );
XOR2X1TS U2067 ( .A(n11184), .B(n11183), .Y(n11185) );
XOR2X1TS U2068 ( .A(n11161), .B(n11160), .Y(n11162) );
XOR2X1TS U2069 ( .A(n10544), .B(n10543), .Y(n10545) );
XOR2X1TS U2070 ( .A(n11170), .B(n11169), .Y(n11171) );
NAND2BX1TS U2071 ( .AN(n116), .B(n11156), .Y(n11157) );
XOR2X1TS U2072 ( .A(n10534), .B(n10533), .Y(n10535) );
XOR2X1TS U2073 ( .A(n10554), .B(n11468), .Y(n10555) );
XOR2X1TS U2074 ( .A(n10773), .B(n11507), .Y(n10775) );
XOR2X1TS U2075 ( .A(n10723), .B(n10036), .Y(n10724) );
XOR2X1TS U2076 ( .A(n10577), .B(n1694), .Y(n10578) );
XOR2X1TS U2077 ( .A(n10759), .B(n1699), .Y(n10760) );
XOR2X1TS U2078 ( .A(n10586), .B(n10062), .Y(n10587) );
XOR2X1TS U2079 ( .A(n10681), .B(n10215), .Y(n10682) );
XOR2X1TS U2080 ( .A(n10748), .B(n9983), .Y(n10749) );
XOR2X1TS U2081 ( .A(n10693), .B(n10171), .Y(n10694) );
XOR2X1TS U2082 ( .A(n9059), .B(n9060), .Y(n802) );
INVX1TS U2083 ( .A(n1216), .Y(n1029) );
NAND2X4TS U2084 ( .A(n9540), .B(n220), .Y(n1313) );
NOR2X2TS U2085 ( .A(n8744), .B(n8745), .Y(DP_OP_59J6_122_190_n153) );
INVX2TS U2086 ( .A(n9666), .Y(n136) );
XOR2X1TS U2087 ( .A(n9407), .B(n9406), .Y(EVEN1_S_B[12]) );
XNOR2X2TS U2088 ( .A(n1442), .B(n7789), .Y(n7801) );
XOR2X1TS U2089 ( .A(n11137), .B(n11136), .Y(n11138) );
XOR2X1TS U2090 ( .A(n11133), .B(n11132), .Y(n11134) );
NAND2BX1TS U2091 ( .AN(n123), .B(n11124), .Y(n11125) );
XOR2X2TS U2092 ( .A(n4540), .B(n4539), .Y(n11190) );
XOR2X1TS U2093 ( .A(n9438), .B(n9437), .Y(n9439) );
XOR2X1TS U2094 ( .A(n8483), .B(n8482), .Y(n8491) );
XOR2X1TS U2095 ( .A(n9412), .B(n9411), .Y(EVEN1_S_B[11]) );
NAND2BX1TS U2096 ( .AN(n11727), .B(n11235), .Y(n11236) );
INVX1TS U2097 ( .A(n676), .Y(n11299) );
INVX1TS U2098 ( .A(n9370), .Y(n9372) );
NAND2X4TS U2099 ( .A(n9336), .B(n9265), .Y(n1487) );
XNOR2X2TS U2100 ( .A(n932), .B(n931), .Y(n8119) );
XOR2X1TS U2101 ( .A(n9364), .B(n9363), .Y(EVEN1_Q_left[28]) );
OAI21X1TS U2102 ( .A0(n10769), .A1(n10710), .B0(n10709), .Y(n10711) );
OAI21X1TS U2103 ( .A0(n10744), .A1(n10642), .B0(n10641), .Y(n10643) );
NOR2X1TS U2104 ( .A(n10672), .B(n10620), .Y(n10622) );
NOR2X1TS U2105 ( .A(n10796), .B(n10778), .Y(n10787) );
OAI21X1TS U2106 ( .A0(n10744), .A1(n10631), .B0(n10630), .Y(n10632) );
NOR2X1TS U2107 ( .A(n10672), .B(n10642), .Y(n10644) );
INVX1TS U2108 ( .A(n10778), .Y(n10785) );
NOR2X1TS U2109 ( .A(n10796), .B(n10511), .Y(n10513) );
OAI21X1TS U2110 ( .A0(n10756), .A1(n10511), .B0(n10510), .Y(n10512) );
OAI21X1TS U2111 ( .A0(n10756), .A1(n10610), .B0(n10609), .Y(n10611) );
NOR2X1TS U2112 ( .A(n10796), .B(n10665), .Y(n10667) );
OAI21X1TS U2113 ( .A0(n10744), .A1(n10665), .B0(n10664), .Y(n10666) );
NOR2X1TS U2114 ( .A(n10796), .B(n10654), .Y(n10656) );
NOR2X1TS U2115 ( .A(n10796), .B(n10690), .Y(n10692) );
OAI21X1TS U2116 ( .A0(n10744), .A1(n10690), .B0(n10689), .Y(n10691) );
NOR2X1TS U2117 ( .A(n10796), .B(n10797), .Y(n10808) );
OAI21X1TS U2118 ( .A0(n10744), .A1(n10599), .B0(n10598), .Y(n10600) );
INVX1TS U2119 ( .A(n10797), .Y(n10804) );
OAI21X1TS U2120 ( .A0(n10769), .A1(n10620), .B0(n10619), .Y(n10621) );
NAND2BX1TS U2121 ( .AN(n117), .B(n11110), .Y(n11111) );
NAND2BX1TS U2122 ( .AN(n123), .B(n11119), .Y(n11120) );
NOR2X1TS U2123 ( .A(n10763), .B(n10551), .Y(n10553) );
NOR2X1TS U2124 ( .A(n10763), .B(n10755), .Y(n10758) );
OAI21X1TS U2125 ( .A0(n10756), .A1(n10525), .B0(n10524), .Y(n10526) );
OAI21X1TS U2126 ( .A0(n10756), .A1(n10574), .B0(n10573), .Y(n10575) );
OAI21X1TS U2127 ( .A0(n10769), .A1(n10583), .B0(n10582), .Y(n10584) );
OAI21X1TS U2128 ( .A0(n10744), .A1(n10551), .B0(n10550), .Y(n10552) );
NOR2X1TS U2129 ( .A(n10763), .B(n10743), .Y(n10746) );
OAI21X1TS U2130 ( .A0(n10769), .A1(n10755), .B0(n10754), .Y(n10757) );
OAI21X1TS U2131 ( .A0(n10769), .A1(n10519), .B0(n10518), .Y(n10520) );
OAI21X1TS U2132 ( .A0(n10756), .A1(n10743), .B0(n10742), .Y(n10745) );
NOR2X1TS U2133 ( .A(n10763), .B(n10583), .Y(n10585) );
OAI21X1TS U2134 ( .A0(n10744), .A1(n10720), .B0(n10719), .Y(n10721) );
OAI21X1TS U2135 ( .A0(n10756), .A1(n10564), .B0(n10563), .Y(n10565) );
NOR2X1TS U2136 ( .A(n10763), .B(n10720), .Y(n10722) );
NOR2X1TS U2137 ( .A(n10763), .B(n10699), .Y(n10701) );
NOR2X1TS U2138 ( .A(n10763), .B(n10732), .Y(n10734) );
OAI21X1TS U2139 ( .A0(n10744), .A1(n10768), .B0(n10767), .Y(n10770) );
OAI21X1TS U2140 ( .A0(n10744), .A1(n10699), .B0(n10698), .Y(n10700) );
NOR2X1TS U2141 ( .A(n10796), .B(n10710), .Y(n10712) );
OAI21X1TS U2142 ( .A0(n10769), .A1(n10732), .B0(n10731), .Y(n10733) );
INVX2TS U2143 ( .A(n7976), .Y(n7376) );
NAND2X2TS U2144 ( .A(n8767), .B(n8766), .Y(DP_OP_59J6_122_190_n210) );
AOI2BB1X2TS U2145 ( .A0N(n1203), .A1N(n4893), .B0(n4890), .Y(n4540) );
XOR2X1TS U2146 ( .A(n9429), .B(n4893), .Y(n11235) );
INVX6TS U2147 ( .A(n8564), .Y(n137) );
INVX1TS U2148 ( .A(DP_OP_59J6_122_190_n222), .Y(n8768) );
NOR2X1TS U2149 ( .A(n10672), .B(n10631), .Y(n10633) );
NOR2X1TS U2150 ( .A(n10672), .B(n10610), .Y(n10612) );
NAND2XLTS U2151 ( .A(n10795), .B(n10547), .Y(n10525) );
NAND2BX1TS U2152 ( .AN(n117), .B(n11099), .Y(n11100) );
CLKINVX2TS U2153 ( .A(n11121), .Y(n11146) );
NOR2X1TS U2154 ( .A(n10672), .B(n10677), .Y(n10679) );
NOR2X1TS U2155 ( .A(n10672), .B(n10599), .Y(n10601) );
ADDFHX2TS U2156 ( .A(n8762), .B(n8761), .CI(n8760), .CO(n8680), .S(n8899) );
INVX1TS U2157 ( .A(n9329), .Y(n765) );
INVX1TS U2158 ( .A(n9403), .Y(n9405) );
NAND2X6TS U2159 ( .A(n887), .B(n886), .Y(n9473) );
XOR2X1TS U2160 ( .A(n9417), .B(n9416), .Y(EVEN1_S_B[9]) );
NAND2XLTS U2161 ( .A(n10671), .B(n10675), .Y(n10677) );
AO21X1TS U2162 ( .A0(n10805), .A1(n10589), .B0(n10537), .Y(n10538) );
OAI21X1TS U2163 ( .A0(n11114), .A1(n11105), .B0(n11104), .Y(n11109) );
OAI21X1TS U2164 ( .A0(n11114), .A1(n11113), .B0(n11112), .Y(n11118) );
XOR2X1TS U2165 ( .A(n11114), .B(n11089), .Y(n11090) );
INVX1TS U2166 ( .A(n8823), .Y(n8469) );
OAI2BB1X2TS U2167 ( .A0N(n1458), .A1N(n1457), .B0(n8352), .Y(n1456) );
INVX1TS U2168 ( .A(n8155), .Y(n1554) );
AND2X2TS U2169 ( .A(add_x_3_n52), .B(n9494), .Y(n11465) );
INVX1TS U2170 ( .A(n9330), .Y(n764) );
INVX2TS U2171 ( .A(n7720), .Y(EVEN1_Q_left[19]) );
NOR2X1TS U2172 ( .A(n10761), .B(n10716), .Y(n10718) );
NOR2X1TS U2173 ( .A(n10794), .B(n10638), .Y(n10640) );
NOR2X1TS U2174 ( .A(n10794), .B(n10673), .Y(n10675) );
NOR2X1TS U2175 ( .A(n10794), .B(n10649), .Y(n10509) );
NOR2X1TS U2176 ( .A(n10761), .B(n10739), .Y(n10741) );
AO21X1TS U2177 ( .A0(n11094), .A1(n11093), .B0(n11092), .Y(n11098) );
NOR2X1TS U2178 ( .A(n10761), .B(n10570), .Y(n10572) );
NOR2X1TS U2179 ( .A(n10794), .B(n10798), .Y(n10801) );
NAND2XLTS U2180 ( .A(n10671), .B(n10597), .Y(n10599) );
NOR2X1TS U2181 ( .A(n10794), .B(n10661), .Y(n10663) );
XOR2X1TS U2182 ( .A(n11086), .B(n11085), .Y(n11087) );
NOR2X1TS U2183 ( .A(n10794), .B(n10686), .Y(n10688) );
NAND2BX1TS U2184 ( .AN(n123), .B(n11072), .Y(n11073) );
NOR2X1TS U2185 ( .A(n10761), .B(n10750), .Y(n10753) );
NOR2X1TS U2186 ( .A(n10761), .B(n10725), .Y(n10697) );
NAND2XLTS U2187 ( .A(n10671), .B(n10629), .Y(n10631) );
NOR2X1TS U2188 ( .A(n10761), .B(n10579), .Y(n10581) );
NAND2XLTS U2189 ( .A(n10671), .B(n10562), .Y(n10564) );
NOR2X1TS U2190 ( .A(n10794), .B(n10779), .Y(n10782) );
NOR2X1TS U2191 ( .A(n10761), .B(n10728), .Y(n10730) );
NAND2XLTS U2192 ( .A(n10542), .B(n10541), .Y(n10543) );
NOR2X1TS U2193 ( .A(n10794), .B(n10616), .Y(n10618) );
AO21X1TS U2194 ( .A0(n11176), .A1(n11175), .B0(n11174), .Y(n11177) );
NOR2X1TS U2195 ( .A(n10449), .B(n11113), .Y(n10451) );
NOR2X1TS U2196 ( .A(n10794), .B(n10650), .Y(n10652) );
NAND2XLTS U2197 ( .A(n10671), .B(n10608), .Y(n10610) );
NOR2X1TS U2198 ( .A(n10761), .B(n10706), .Y(n10708) );
OAI21X1TS U2199 ( .A0(n11112), .A1(n10449), .B0(n10448), .Y(n10450) );
OAI21X1TS U2200 ( .A0(n11144), .A1(n11143), .B0(n11142), .Y(n11145) );
NOR2X1TS U2201 ( .A(n10761), .B(n11505), .Y(n10765) );
NOR2X1TS U2202 ( .A(n9430), .B(n7235), .Y(n7237) );
XOR2X1TS U2203 ( .A(n7703), .B(n7702), .Y(n7719) );
OAI21X1TS U2204 ( .A0(n8876), .A1(n8877), .B0(n8875), .Y(n740) );
NOR2X1TS U2205 ( .A(n9430), .B(n8399), .Y(n8401) );
NAND2BX2TS U2206 ( .AN(n964), .B(n965), .Y(n8381) );
NOR2X6TS U2207 ( .A(n965), .B(n8075), .Y(n8380) );
CLKINVX2TS U2208 ( .A(n8204), .Y(n7388) );
NAND2X2TS U2209 ( .A(n4935), .B(n4934), .Y(n8407) );
NAND2X2TS U2210 ( .A(n6604), .B(n6674), .Y(n6677) );
XOR2X1TS U2211 ( .A(n9030), .B(n9029), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[12]) );
INVX1TS U2212 ( .A(n7244), .Y(n7246) );
OAI21X1TS U2213 ( .A0(n9030), .A1(n9026), .B0(n9027), .Y(n8808) );
XOR2X1TS U2214 ( .A(n9035), .B(n9034), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[11]) );
NOR2X1TS U2215 ( .A(n10780), .B(n10716), .Y(n10717) );
NOR2X1TS U2216 ( .A(n10780), .B(n11509), .Y(n10548) );
NOR2X1TS U2217 ( .A(n10780), .B(n10570), .Y(n10571) );
NOR2X1TS U2218 ( .A(n10799), .B(n10627), .Y(n10628) );
NOR2X1TS U2219 ( .A(n10780), .B(n11505), .Y(n10764) );
NOR2X1TS U2220 ( .A(n10751), .B(n10750), .Y(n10752) );
NOR2X1TS U2221 ( .A(n10799), .B(n10595), .Y(n10596) );
NOR2X1TS U2222 ( .A(n10751), .B(n10579), .Y(n10580) );
NOR2X1TS U2223 ( .A(n10799), .B(n10638), .Y(n10639) );
NOR2X1TS U2224 ( .A(n10751), .B(n10739), .Y(n10740) );
NOR2X1TS U2225 ( .A(n10751), .B(n10725), .Y(n10696) );
INVX1TS U2226 ( .A(n11159), .Y(n11174) );
NOR2X1TS U2227 ( .A(n10799), .B(n10650), .Y(n10651) );
NOR2X1TS U2228 ( .A(n10799), .B(n10706), .Y(n10707) );
NOR2X1TS U2229 ( .A(n10780), .B(n10661), .Y(n10662) );
NOR2X1TS U2230 ( .A(n10780), .B(n10560), .Y(n10561) );
OAI21X1TS U2231 ( .A0(n11180), .A1(n11159), .B0(n11181), .Y(n10503) );
AOI2BB1X1TS U2232 ( .A0N(n11082), .A1N(n11081), .B0(n11080), .Y(n11086) );
OAI21X1TS U2233 ( .A0(n11148), .A1(n11142), .B0(n11149), .Y(n10495) );
INVX1TS U2234 ( .A(EVEN1_Q_left[15]), .Y(n9325) );
CLKINVX1TS U2235 ( .A(n11225), .Y(n9309) );
INVX1TS U2236 ( .A(n9448), .Y(n9451) );
INVX1TS U2237 ( .A(n9449), .Y(n9450) );
INVX1TS U2238 ( .A(n8484), .Y(n8486) );
INVX1TS U2239 ( .A(n7273), .Y(n7266) );
INVX2TS U2240 ( .A(n9427), .Y(n4890) );
NOR2X1TS U2241 ( .A(n9668), .B(n1725), .Y(add_x_2_n52) );
INVX1TS U2242 ( .A(n7907), .Y(n6627) );
NOR2X1TS U2243 ( .A(n8366), .B(n8542), .Y(n8370) );
INVX1TS U2244 ( .A(n8915), .Y(n8917) );
NOR2X1TS U2245 ( .A(n9430), .B(n8720), .Y(n8722) );
INVX1TS U2246 ( .A(n8354), .Y(n1457) );
NAND2BX1TS U2247 ( .AN(n11726), .B(n11228), .Y(n11229) );
XNOR2X2TS U2248 ( .A(n7711), .B(n208), .Y(n8154) );
INVX1TS U2249 ( .A(n7274), .Y(n7276) );
OAI2BB1X2TS U2250 ( .A0N(n8605), .A1N(n8604), .B0(n1117), .Y(n8649) );
OAI21X1TS U2251 ( .A0(n11066), .A1(n11065), .B0(n11064), .Y(n11071) );
XOR2X1TS U2252 ( .A(n11051), .B(n11050), .Y(n11052) );
NAND2BX1TS U2253 ( .AN(n11107), .B(n11106), .Y(n11108) );
NAND2BX1TS U2254 ( .AN(n116), .B(n11038), .Y(n11039) );
CLKINVX2TS U2255 ( .A(n11115), .Y(n11102) );
NAND2BX1TS U2256 ( .AN(n123), .B(n11028), .Y(n11029) );
NOR2X1TS U2257 ( .A(n10502), .B(n11472), .Y(n11180) );
INVX1TS U2258 ( .A(n11106), .Y(n10446) );
OAI21X1TS U2259 ( .A0(n11166), .A1(n11163), .B0(n11167), .Y(n11176) );
NAND2BX1TS U2260 ( .AN(n116), .B(n11044), .Y(n11045) );
NOR2X1TS U2261 ( .A(n10501), .B(n11471), .Y(n11172) );
INVX1TS U2262 ( .A(n11163), .Y(n11164) );
INVX1TS U2263 ( .A(n11126), .Y(n11127) );
NOR2X1TS U2264 ( .A(n11122), .B(n11129), .Y(n11139) );
INVX1TS U2265 ( .A(n11122), .Y(n11128) );
INVX1TS U2266 ( .A(n11154), .Y(n11165) );
NOR2X1TS U2267 ( .A(n11143), .B(n11148), .Y(n10496) );
CLKINVX2TS U2268 ( .A(n4936), .Y(n1274) );
INVX1TS U2269 ( .A(n9430), .Y(n9433) );
NOR2X1TS U2270 ( .A(n9430), .B(n8711), .Y(n8479) );
CLKINVX2TS U2271 ( .A(n9346), .Y(n9247) );
ADDFHX1TS U2272 ( .A(n8854), .B(n8853), .CI(n8852), .CO(n8871), .S(n8467) );
INVX1TS U2273 ( .A(n4934), .Y(n862) );
INVX1TS U2274 ( .A(n8717), .Y(n8397) );
NOR2X1TS U2275 ( .A(n9506), .B(n1717), .Y(add_x_3_n81) );
XOR2X1TS U2276 ( .A(n9422), .B(n9421), .Y(EVEN1_S_B[7]) );
OAI21X1TS U2277 ( .A0(n9393), .A1(n8939), .B0(n8938), .Y(n8940) );
OAI21X1TS U2278 ( .A0(n8985), .A1(n8984), .B0(n8983), .Y(n8986) );
NOR2X2TS U2279 ( .A(n4538), .B(n4537), .Y(n4536) );
XOR2X1TS U2280 ( .A(n9045), .B(n9044), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[7]) );
XOR2X1TS U2281 ( .A(n9040), .B(n9039), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[8]) );
OAI21X1TS U2282 ( .A0(n9393), .A1(n9392), .B0(n9391), .Y(n9394) );
INVX1TS U2283 ( .A(n8824), .Y(n9032) );
INVX1TS U2284 ( .A(n8541), .Y(n8366) );
OAI21X1TS U2285 ( .A0(n9393), .A1(n9382), .B0(n9390), .Y(n8965) );
OAI21X2TS U2286 ( .A0(n6688), .A1(n2244), .B0(n2243), .Y(n7252) );
OAI21X1TS U2287 ( .A0(n9393), .A1(n8951), .B0(n8950), .Y(n8952) );
OAI21X1TS U2288 ( .A0(n9002), .A1(n9021), .B0(n9022), .Y(n9003) );
OAI21X1TS U2289 ( .A0(n9393), .A1(n8959), .B0(n8973), .Y(n8960) );
OAI21X1TS U2290 ( .A0(n9431), .A1(n7227), .B0(n9435), .Y(n3706) );
ADDFHX2TS U2291 ( .A(n7170), .B(n7169), .CI(n7168), .CO(n8415), .S(n7171) );
NOR2X1TS U2292 ( .A(n10492), .B(n11480), .Y(n11143) );
NOR2X1TS U2293 ( .A(n10490), .B(n11490), .Y(n11122) );
INVX1TS U2294 ( .A(n11088), .Y(n11093) );
OR2X2TS U2295 ( .A(n11088), .B(n11092), .Y(n11089) );
OR2X2TS U2296 ( .A(n10444), .B(n11514), .Y(n11116) );
INVX1TS U2297 ( .A(n11079), .Y(n11081) );
NOR2X1TS U2298 ( .A(n10493), .B(n11510), .Y(n11148) );
NOR2X1TS U2299 ( .A(n10500), .B(n11481), .Y(n11166) );
NOR2X1TS U2300 ( .A(n10491), .B(n11482), .Y(n11129) );
XOR2X2TS U2301 ( .A(n7208), .B(n7192), .Y(n7205) );
INVX1TS U2302 ( .A(n9315), .Y(n9317) );
XOR2X1TS U2303 ( .A(n4796), .B(n4795), .Y(n4934) );
NAND2X1TS U2304 ( .A(n9298), .B(n9297), .Y(n9299) );
INVX1TS U2305 ( .A(n1210), .Y(n1211) );
INVX1TS U2306 ( .A(n9313), .Y(n8166) );
CLKINVX2TS U2307 ( .A(n8023), .Y(n8049) );
XNOR2X2TS U2308 ( .A(n7898), .B(n7897), .Y(n826) );
OAI21X1TS U2309 ( .A0(n9005), .A1(n9022), .B0(n9006), .Y(n8834) );
INVX1TS U2310 ( .A(n1106), .Y(n1104) );
XOR2X1TS U2311 ( .A(n4917), .B(n4916), .Y(n4929) );
XOR2X1TS U2312 ( .A(n4912), .B(n4911), .Y(n4930) );
XOR2X1TS U2313 ( .A(n9426), .B(n221), .Y(EVEN1_S_B[5]) );
XOR2X1TS U2314 ( .A(n9178), .B(n1494), .Y(n9179) );
OAI21X1TS U2315 ( .A0(n9418), .A1(n9421), .B0(n9419), .Y(n9348) );
XOR2X1TS U2316 ( .A(n4887), .B(n4886), .Y(n4936) );
INVX1TS U2317 ( .A(n7688), .Y(n7277) );
OAI2BB1X2TS U2318 ( .A0N(n8299), .A1N(n1243), .B0(n1242), .Y(n8339) );
AND2X2TS U2319 ( .A(n10412), .B(n11531), .Y(n11080) );
OAI21X1TS U2320 ( .A0(n10299), .A1(n10307), .B0(n10310), .Y(n10306) );
OAI21X1TS U2321 ( .A0(n10299), .A1(n10236), .B0(n10235), .Y(n10250) );
OR2X2TS U2322 ( .A(n10412), .B(n11531), .Y(n11079) );
OAI21X1TS U2323 ( .A0(n11032), .A1(n11022), .B0(n11021), .Y(n11027) );
OAI21X1TS U2324 ( .A0(n10299), .A1(n10252), .B0(n10251), .Y(n10232) );
OR2X2TS U2325 ( .A(n10442), .B(n11506), .Y(n11096) );
AND2X2TS U2326 ( .A(n10441), .B(n11513), .Y(n11092) );
XOR2X1TS U2327 ( .A(n10299), .B(n10253), .Y(n10500) );
OAI21X1TS U2328 ( .A0(n11032), .A1(n11031), .B0(n11030), .Y(n11037) );
XOR2X1TS U2329 ( .A(n11032), .B(n11019), .Y(n11020) );
INVX1TS U2330 ( .A(n11067), .Y(n11069) );
INVX1TS U2331 ( .A(n10414), .Y(n11084) );
NOR2X1TS U2332 ( .A(n9272), .B(n9273), .Y(n1675) );
INVX1TS U2333 ( .A(n7712), .Y(n8151) );
INVX3TS U2334 ( .A(n8830), .Y(n8635) );
INVX1TS U2335 ( .A(n8141), .Y(n3054) );
OAI21X2TS U2336 ( .A0(n8146), .A1(n8162), .B0(n8147), .Y(n946) );
INVX2TS U2337 ( .A(n7714), .Y(n7716) );
INVX1TS U2338 ( .A(n9418), .Y(n9420) );
XOR2X1TS U2339 ( .A(n9210), .B(n9209), .Y(n9245) );
INVX1TS U2340 ( .A(n8919), .Y(n8995) );
NOR2X4TS U2341 ( .A(n5934), .B(n5933), .Y(n6693) );
INVX1TS U2342 ( .A(n8131), .Y(n8133) );
INVX1TS U2343 ( .A(n8993), .Y(n8994) );
INVX1TS U2344 ( .A(n9013), .Y(n9015) );
ADDFHX2TS U2345 ( .A(n3293), .B(n3292), .CI(n3291), .CO(n7818), .S(n3334) );
NOR2X1TS U2346 ( .A(n8984), .B(n8988), .Y(n8927) );
OAI21X1TS U2347 ( .A0(n8983), .A1(n8988), .B0(n8989), .Y(n8926) );
INVX1TS U2348 ( .A(n8136), .Y(n8138) );
NOR2X6TS U2349 ( .A(n6607), .B(n6608), .Y(n8553) );
NAND2X2TS U2350 ( .A(n6610), .B(n901), .Y(n8543) );
OAI21X1TS U2351 ( .A0(n8788), .A1(n8849), .B0(n8787), .Y(n8817) );
ADDFHX2TS U2352 ( .A(n7816), .B(n7815), .CI(n7814), .CO(n7869), .S(n7839) );
NAND2X2TS U2353 ( .A(n6615), .B(n6614), .Y(n9454) );
AND2X2TS U2354 ( .A(n6606), .B(n6605), .Y(n8551) );
INVX1TS U2355 ( .A(n11048), .Y(n10380) );
XOR2X1TS U2356 ( .A(n10437), .B(n10436), .Y(n10441) );
NOR2X1TS U2357 ( .A(n10396), .B(n11518), .Y(n11065) );
XOR2X1TS U2358 ( .A(n10411), .B(n10410), .Y(n10412) );
NOR2X1TS U2359 ( .A(n10413), .B(n11483), .Y(n10414) );
AOI21X1TS U2360 ( .A0(n10358), .A1(n11017), .B0(n10357), .Y(n11040) );
OAI21X1TS U2361 ( .A0(n10483), .A1(n10262), .B0(n10261), .Y(n10267) );
OAI21X1TS U2362 ( .A0(n10483), .A1(n10482), .B0(n10481), .Y(n10489) );
OAI21X1TS U2363 ( .A0(n10483), .A1(n10472), .B0(n10471), .Y(n10476) );
OAI21X1TS U2364 ( .A0(n10483), .A1(n10463), .B0(n10467), .Y(n10466) );
OAI21X1TS U2365 ( .A0(n10483), .A1(n10458), .B0(n10457), .Y(n10462) );
OAI21X1TS U2366 ( .A0(n10483), .A1(n10418), .B0(n10417), .Y(n10421) );
OAI21X1TS U2367 ( .A0(n10483), .A1(n10439), .B0(n10438), .Y(n10425) );
XOR2X1TS U2368 ( .A(n10483), .B(n10440), .Y(n10442) );
XOR2X1TS U2369 ( .A(n8064), .B(n8063), .Y(n8067) );
NOR2X1TS U2370 ( .A(add_x_2_n109), .B(n1722), .Y(add_x_2_n99) );
INVX1TS U2371 ( .A(n4895), .Y(n4897) );
INVX1TS U2372 ( .A(n9423), .Y(n9425) );
INVX1TS U2373 ( .A(n7689), .Y(n7691) );
OR2X2TS U2374 ( .A(n1717), .B(n1716), .Y(n1693) );
NOR2BX1TS U2375 ( .AN(n495), .B(n8576), .Y(n1168) );
INVX1TS U2376 ( .A(n9293), .Y(n9294) );
OAI2BB1X2TS U2377 ( .A0N(n2974), .A1N(n2973), .B0(n926), .Y(n3067) );
NAND2BX1TS U2378 ( .AN(n11726), .B(n11220), .Y(n11221) );
INVX1TS U2379 ( .A(n9010), .Y(n9011) );
INVX1TS U2380 ( .A(n8827), .Y(n9012) );
INVX1TS U2381 ( .A(n7128), .Y(n1579) );
OAI21X1TS U2382 ( .A0(n5016), .A1(n5017), .B0(n5015), .Y(n731) );
XOR2X1TS U2383 ( .A(n8045), .B(n8044), .Y(n8069) );
INVX1TS U2384 ( .A(n9382), .Y(n8947) );
NAND2BX2TS U2385 ( .AN(n4517), .B(n4516), .Y(n864) );
INVX1TS U2386 ( .A(n9390), .Y(n8949) );
NAND2X6TS U2387 ( .A(n697), .B(n1020), .Y(n868) );
NAND2BX1TS U2388 ( .AN(n5911), .B(n5912), .Y(n5900) );
OR2X2TS U2389 ( .A(n10379), .B(n11532), .Y(n11049) );
XOR2X1TS U2390 ( .A(n10405), .B(n10404), .Y(n10413) );
NOR2X4TS U2391 ( .A(n5977), .B(n5978), .Y(n6744) );
OAI21X2TS U2392 ( .A0(n3479), .A1(n3480), .B0(n3478), .Y(n1170) );
INVX1TS U2393 ( .A(n8810), .Y(n8806) );
XOR2X2TS U2394 ( .A(n1611), .B(n7510), .Y(n8829) );
XOR2X1TS U2395 ( .A(n7371), .B(n7370), .Y(n9494) );
NOR2X1TS U2396 ( .A(n1434), .B(n9269), .Y(n1432) );
CLKINVX2TS U2397 ( .A(n3451), .Y(n1525) );
INVX1TS U2398 ( .A(n8818), .Y(n8820) );
INVX1TS U2399 ( .A(n8156), .Y(n8158) );
INVX1TS U2400 ( .A(n8211), .Y(n6626) );
INVX1TS U2401 ( .A(n7391), .Y(n8205) );
XOR2X2TS U2402 ( .A(n4339), .B(n4338), .Y(n4352) );
INVX1TS U2403 ( .A(n9141), .Y(n9143) );
XOR2X1TS U2404 ( .A(n6687), .B(n6686), .Y(n9496) );
XOR2X1TS U2405 ( .A(n7297), .B(n7296), .Y(
EVEN1_right_RECURSIVE_ODD1_Q_left_17_) );
OR2X2TS U2406 ( .A(n1726), .B(n1721), .Y(n1696) );
XOR2X1TS U2407 ( .A(n9050), .B(n9049), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[4]) );
OAI21X1TS U2408 ( .A0(n7671), .A1(n7670), .B0(n7672), .Y(n7509) );
OAI21X1TS U2409 ( .A0(n4921), .A1(n4518), .B0(n4779), .Y(n4519) );
XOR2X1TS U2410 ( .A(n7357), .B(n7356), .Y(n9495) );
CLKINVX2TS U2411 ( .A(n4727), .Y(n4517) );
INVX1TS U2412 ( .A(n9036), .Y(n9038) );
INVX1TS U2413 ( .A(n9026), .Y(n9028) );
OAI21X2TS U2414 ( .A0(n6477), .A1(n6476), .B0(n6475), .Y(n1628) );
INVX1TS U2415 ( .A(n8183), .Y(n8186) );
INVX1TS U2416 ( .A(n8954), .Y(n8956) );
OAI21X1TS U2417 ( .A0(n3212), .A1(n3213), .B0(n3211), .Y(n1515) );
NOR2X1TS U2418 ( .A(n8810), .B(n9026), .Y(n8812) );
INVX1TS U2419 ( .A(n9033), .Y(n8799) );
OAI21X1TS U2420 ( .A0(n8967), .A1(n8954), .B0(n8955), .Y(n9387) );
NOR2X1TS U2421 ( .A(n11041), .B(n10376), .Y(n11047) );
INVX1TS U2422 ( .A(n10376), .Y(n11057) );
OAI21X1TS U2423 ( .A0(n11023), .A1(n11021), .B0(n11024), .Y(n10357) );
NOR2X1TS U2424 ( .A(n11023), .B(n11022), .Y(n10358) );
INVX1TS U2425 ( .A(n11042), .Y(n11053) );
OAI21X1TS U2426 ( .A0(n10385), .A1(n10384), .B0(n10383), .Y(n10390) );
XOR2X1TS U2427 ( .A(n10385), .B(n10375), .Y(n10379) );
OR2X2TS U2428 ( .A(n8796), .B(n8795), .Y(n1687) );
OAI2BB1X2TS U2429 ( .A0N(n4347), .A1N(n4317), .B0(n1037), .Y(n1036) );
INVX1TS U2430 ( .A(n9282), .Y(n3048) );
XOR2X1TS U2431 ( .A(n8200), .B(n8199), .Y(n9623) );
INVX2TS U2432 ( .A(n8277), .Y(n7154) );
XOR2X1TS U2433 ( .A(n9622), .B(n9621), .Y(n9660) );
ADDFX1TS U2434 ( .A(n3290), .B(n3289), .CI(n3288), .CO(n7820), .S(n3276) );
INVX1TS U2435 ( .A(n4427), .Y(n4267) );
XOR2X1TS U2436 ( .A(n8674), .B(n9230), .Y(EVEN1_S_B[4]) );
OR2X2TS U2437 ( .A(n9241), .B(n9240), .Y(n223) );
NOR2X1TS U2438 ( .A(n8937), .B(n8936), .Y(n8954) );
AND2X2TS U2439 ( .A(n191), .B(n7228), .Y(n3723) );
NAND2X1TS U2440 ( .A(n9214), .B(n9213), .Y(n9216) );
INVX1TS U2441 ( .A(n8962), .Y(n8932) );
XOR2X1TS U2442 ( .A(n4297), .B(n4296), .Y(n4363) );
INVX1TS U2443 ( .A(n8967), .Y(n8948) );
XOR2X1TS U2444 ( .A(n9708), .B(n9707), .Y(n9709) );
INVX1TS U2445 ( .A(n8844), .Y(n8781) );
ADDFHX2TS U2446 ( .A(n5722), .B(n5721), .CI(n5720), .CO(n5848), .S(n5847) );
OAI2BB1X4TS U2447 ( .A0N(n750), .A1N(n749), .B0(n4833), .Y(n748) );
OR2X4TS U2448 ( .A(n5840), .B(n5839), .Y(n8047) );
OAI21X1TS U2449 ( .A0(n8943), .A1(n8942), .B0(n1581), .Y(n8447) );
ADDFHX2TS U2450 ( .A(n8863), .B(n8862), .CI(n8861), .CO(n8868), .S(n8865) );
INVX1TS U2451 ( .A(n7228), .Y(n7229) );
XOR2X1TS U2452 ( .A(n9530), .B(n7311), .Y(n1718) );
NAND2BX1TS U2453 ( .AN(n11727), .B(n11213), .Y(n11214) );
XOR2X1TS U2454 ( .A(n9154), .B(n9153), .Y(n11216) );
XOR2X1TS U2455 ( .A(n9140), .B(n9139), .Y(n11219) );
XOR2X1TS U2456 ( .A(n9562), .B(n9561), .Y(
EVEN1_left_RECURSIVE_ODD1_Q_left_17_) );
XOR2X1TS U2457 ( .A(n7972), .B(n7971), .Y(n9626) );
INVX1TS U2458 ( .A(n6259), .Y(n1399) );
OR2X2TS U2459 ( .A(n8785), .B(n8784), .Y(n210) );
NAND2BX1TS U2460 ( .AN(n11727), .B(n11211), .Y(n11212) );
OAI21X2TS U2461 ( .A0(n7480), .A1(n7481), .B0(n7479), .Y(n1226) );
NOR2X1TS U2462 ( .A(n10347), .B(n11013), .Y(n10349) );
INVX1TS U2463 ( .A(n11023), .Y(n11025) );
NOR2X1TS U2464 ( .A(n10377), .B(n11519), .Y(n11041) );
OAI21X1TS U2465 ( .A0(n10347), .A1(n10346), .B0(n10345), .Y(n10348) );
NOR2X1TS U2466 ( .A(n10378), .B(n11517), .Y(n10376) );
NAND2BX1TS U2467 ( .AN(n123), .B(n11000), .Y(n11001) );
XOR2X1TS U2468 ( .A(n9085), .B(n9084), .Y(EVEN1_Q_left[12]) );
XOR2X1TS U2469 ( .A(n9462), .B(n9461), .Y(n9463) );
INVX1TS U2470 ( .A(n8889), .Y(n8776) );
XNOR2X2TS U2471 ( .A(n4730), .B(n4729), .Y(n904) );
INVX1TS U2472 ( .A(n7529), .Y(n7522) );
NOR2X4TS U2473 ( .A(n4418), .B(n4417), .Y(n4455) );
NOR2X1TS U2474 ( .A(n4918), .B(n4878), .Y(n4880) );
OAI21X1TS U2475 ( .A0(n4729), .A1(n4730), .B0(n903), .Y(n902) );
INVX1TS U2476 ( .A(n7944), .Y(n6843) );
XNOR2X2TS U2477 ( .A(n1622), .B(n6585), .Y(n6622) );
INVX1TS U2478 ( .A(n9384), .Y(n9385) );
INVX1TS U2479 ( .A(n8393), .Y(n8481) );
OAI21X1TS U2480 ( .A0(n7930), .A1(n7396), .B0(n7395), .Y(n7401) );
NAND2X2TS U2481 ( .A(n6747), .B(n6748), .Y(n9636) );
NOR2X1TS U2482 ( .A(n4918), .B(n4905), .Y(n4907) );
OAI21X1TS U2483 ( .A0(n7365), .A1(n7358), .B0(n7362), .Y(n7346) );
XOR2X1TS U2484 ( .A(n9091), .B(n9090), .Y(EVEN1_Q_left[11]) );
INVX1TS U2485 ( .A(n7365), .Y(n7353) );
INVX1TS U2486 ( .A(n7359), .Y(n7354) );
INVX1TS U2487 ( .A(n8396), .Y(n7240) );
INVX1TS U2488 ( .A(n7946), .Y(n7947) );
OAI21X1TS U2489 ( .A0(n8480), .A1(n8396), .B0(n8395), .Y(n8715) );
NOR2X1TS U2490 ( .A(n7359), .B(n7364), .Y(n7367) );
OAI21X1TS U2491 ( .A0(n7365), .A1(n7364), .B0(n7363), .Y(n7366) );
NAND2X2TS U2492 ( .A(n999), .B(n4300), .Y(n4427) );
INVX1TS U2493 ( .A(n8057), .Y(n2474) );
INVX1TS U2494 ( .A(n8712), .Y(n8713) );
OR2X2TS U2495 ( .A(n7055), .B(n7054), .Y(n191) );
OAI21X1TS U2496 ( .A0(n8057), .A1(n8056), .B0(n8055), .Y(n8058) );
NOR2X1TS U2497 ( .A(n8051), .B(n8029), .Y(n7199) );
NOR2X1TS U2498 ( .A(n8051), .B(n8056), .Y(n8059) );
NOR2X1TS U2499 ( .A(n8051), .B(n7214), .Y(n7216) );
OAI21X1TS U2500 ( .A0(n8057), .A1(n7214), .B0(n7213), .Y(n7215) );
CLKINVX2TS U2501 ( .A(n967), .Y(n966) );
INVX1TS U2502 ( .A(n9124), .Y(n9140) );
ADDFHX2TS U2503 ( .A(n3082), .B(n3081), .CI(n3080), .CO(n8790), .S(n8785) );
OAI21X1TS U2504 ( .A0(n8057), .A1(n8040), .B0(n8039), .Y(n8041) );
OAI21X1TS U2505 ( .A0(n7930), .A1(n7916), .B0(n7927), .Y(n7919) );
ADDFHX2TS U2506 ( .A(n9219), .B(n9218), .CI(n9217), .CO(n9204), .S(n9243) );
NOR2X1TS U2507 ( .A(n8051), .B(n8040), .Y(n8042) );
INVX1TS U2508 ( .A(n1109), .Y(n1111) );
NOR2X1TS U2509 ( .A(n4918), .B(n4784), .Y(n4786) );
INVX1TS U2510 ( .A(n9046), .Y(n9048) );
INVX1TS U2511 ( .A(n9212), .Y(n9214) );
XOR2X1TS U2512 ( .A(n10372), .B(n10371), .Y(n10378) );
NAND2BX1TS U2513 ( .AN(n123), .B(n10995), .Y(n10996) );
INVX1TS U2514 ( .A(n11033), .Y(n11034) );
NAND2X1TS U2515 ( .A(n11726), .B(sgf_result_o[48]), .Y(n11742) );
INVX1TS U2516 ( .A(n10344), .Y(n10347) );
NAND2XLTS U2517 ( .A(n11091), .B(sgf_result_o[45]), .Y(n11739) );
NOR2X1TS U2518 ( .A(n10356), .B(n11516), .Y(n11023) );
OAI21X1TS U2519 ( .A0(n9928), .A1(n11013), .B0(n10346), .Y(n9929) );
INVX1TS U2520 ( .A(n11031), .Y(n11018) );
XOR2X1TS U2521 ( .A(n7760), .B(n6803), .Y(n9655) );
INVX1TS U2522 ( .A(n9236), .Y(n3538) );
OAI21X1TS U2523 ( .A0(n6243), .A1(n6244), .B0(n6242), .Y(n921) );
INVX1TS U2524 ( .A(n9149), .Y(n9163) );
OAI2BB1X2TS U2525 ( .A0N(n3524), .A1N(n3523), .B0(n1134), .Y(n3499) );
OAI21X2TS U2526 ( .A0(n5393), .A1(n5394), .B0(n5392), .Y(n1448) );
INVX1TS U2527 ( .A(n9229), .Y(n8669) );
ADDFHX2TS U2528 ( .A(n6253), .B(n6252), .CI(n6251), .CO(n6245), .S(n6262) );
OAI21X2TS U2529 ( .A0(n5889), .A1(n5888), .B0(n5887), .Y(n1363) );
INVX1TS U2530 ( .A(n9075), .Y(n9085) );
OAI21X1TS U2531 ( .A0(n6393), .A1(n6392), .B0(n6391), .Y(n738) );
OAI21X1TS U2532 ( .A0(n806), .A1(n4837), .B0(n4836), .Y(n805) );
XOR2X2TS U2533 ( .A(n775), .B(n3522), .Y(n3571) );
ADDFHX2TS U2534 ( .A(n4712), .B(n4711), .CI(n4710), .CO(n4833), .S(n4730) );
OAI21X1TS U2535 ( .A0(n9186), .A1(n9182), .B0(n9183), .Y(n9173) );
INVX1TS U2536 ( .A(n8670), .Y(n8671) );
XOR2X1TS U2537 ( .A(n9186), .B(n9185), .Y(n11210) );
OAI21X1TS U2538 ( .A0(n7760), .A1(n7790), .B0(n7793), .Y(n7765) );
XOR2X1TS U2539 ( .A(n5115), .B(n8004), .Y(n9545) );
ADDFHX2TS U2540 ( .A(n3037), .B(n3036), .CI(n3035), .CO(n3029), .S(n3051) );
XOR2X2TS U2541 ( .A(n3584), .B(n3585), .Y(n1484) );
XNOR2X2TS U2542 ( .A(n922), .B(n6242), .Y(n6265) );
OAI21X1TS U2543 ( .A0(n5013), .A1(n5014), .B0(n5012), .Y(n1596) );
OAI2BB1X2TS U2544 ( .A0N(n6182), .A1N(n1048), .B0(n1046), .Y(n6323) );
XOR2X1TS U2545 ( .A(n9645), .B(n9644), .Y(n9646) );
XOR2X1TS U2546 ( .A(n4314), .B(n4313), .Y(n4356) );
OAI21X1TS U2547 ( .A0(n2996), .A1(n377), .B0(n1141), .Y(n3026) );
OAI21X2TS U2548 ( .A0(n3282), .A1(n1162), .B0(n1160), .Y(n1159) );
ADDFHX2TS U2549 ( .A(n3624), .B(n3623), .CI(n3622), .CO(n3645), .S(n3642) );
NOR2X1TS U2550 ( .A(n7238), .B(n7239), .Y(n8396) );
OAI21X1TS U2551 ( .A0(n9554), .A1(n9563), .B0(n9566), .Y(n9555) );
OR2X2TS U2552 ( .A(n8943), .B(n8942), .Y(n9386) );
INVX1TS U2553 ( .A(n9051), .Y(n9053) );
OR2X2TS U2554 ( .A(n8403), .B(n8402), .Y(n8714) );
INVX1TS U2555 ( .A(n8317), .Y(n6987) );
OAI21X1TS U2556 ( .A0(n2809), .A1(n7828), .B0(n1142), .Y(n2993) );
NOR2X1TS U2557 ( .A(n10353), .B(n11515), .Y(n11031) );
AOI2BB1X1TS U2558 ( .A0N(n10367), .A1N(n10366), .B0(n10365), .Y(n10372) );
INVX1TS U2559 ( .A(n10367), .Y(n10361) );
OAI21X1TS U2560 ( .A0(n10467), .A1(n10204), .B0(n10203), .Y(n10205) );
INVX1TS U2561 ( .A(n10256), .Y(n10260) );
NAND2BX1TS U2562 ( .AN(n9942), .B(n11547), .Y(n10344) );
OAI21X1TS U2563 ( .A0(n10310), .A1(n10309), .B0(n10308), .Y(n10311) );
NAND2BX1TS U2564 ( .AN(n10354), .B(n11543), .Y(n11035) );
NAND2BX1TS U2565 ( .AN(n125), .B(n10981), .Y(n10982) );
NAND2BX1TS U2566 ( .AN(n124), .B(n10949), .Y(n10950) );
NAND2X1TS U2567 ( .A(n11726), .B(sgf_result_o[46]), .Y(n11740) );
INVX1TS U2568 ( .A(n11009), .Y(n9928) );
NAND2XLTS U2569 ( .A(n11091), .B(sgf_result_o[47]), .Y(n11741) );
NAND2BX1TS U2570 ( .AN(n116), .B(n10963), .Y(n10964) );
NAND2BX1TS U2571 ( .AN(n117), .B(n10958), .Y(n10959) );
NOR2X1TS U2572 ( .A(n9782), .B(n11013), .Y(n9930) );
INVX1TS U2573 ( .A(n4420), .Y(n4290) );
NAND2X1TS U2574 ( .A(n4301), .B(n4300), .Y(n4302) );
INVX1TS U2575 ( .A(n2077), .Y(n2079) );
OR2X2TS U2576 ( .A(n8001), .B(n8000), .Y(n8673) );
INVX1TS U2577 ( .A(n8773), .Y(n3038) );
XOR2X1TS U2578 ( .A(n9106), .B(n9105), .Y(EVEN1_Q_left[8]) );
XOR2X2TS U2579 ( .A(n7457), .B(n7456), .Y(n7458) );
INVX1TS U2580 ( .A(n7385), .Y(n7383) );
XOR2X1TS U2581 ( .A(n8563), .B(n8562), .Y(n9444) );
XOR2X1TS U2582 ( .A(n9112), .B(n9111), .Y(EVEN1_Q_left[7]) );
INVX1TS U2583 ( .A(n9524), .Y(n7342) );
XOR2X2TS U2584 ( .A(n6487), .B(n1627), .Y(n6507) );
OAI21X1TS U2585 ( .A0(n8004), .A1(n8003), .B0(n8002), .Y(n8672) );
INVX1TS U2586 ( .A(n2368), .Y(n2133) );
ADDFHX1TS U2587 ( .A(n3042), .B(n3041), .CI(n8896), .CO(n3035), .S(n3047) );
ADDFHX2TS U2588 ( .A(n9227), .B(n9226), .CI(n9225), .CO(n9233), .S(n9231) );
OAI21X1TS U2589 ( .A0(n2106), .A1(n2105), .B0(n2104), .Y(n1320) );
OAI21X2TS U2590 ( .A0(n3523), .A1(n3524), .B0(n3522), .Y(n1134) );
OAI21X1TS U2591 ( .A0(n6226), .A1(n943), .B0(n6225), .Y(n942) );
ADDFHX2TS U2592 ( .A(n6201), .B(n6200), .CI(n6199), .CO(n6207), .S(n6234) );
INVX1TS U2593 ( .A(n1514), .Y(n1513) );
OR2X2TS U2594 ( .A(n3537), .B(n3536), .Y(n9237) );
INVX1TS U2595 ( .A(n7132), .Y(n846) );
INVX1TS U2596 ( .A(n7131), .Y(n847) );
NOR2X1TS U2597 ( .A(n8668), .B(n8667), .Y(n9229) );
OAI21X1TS U2598 ( .A0(n6464), .A1(n6463), .B0(n6462), .Y(n863) );
INVX1TS U2599 ( .A(n8895), .Y(n3043) );
OAI2BB1X2TS U2600 ( .A0N(n6286), .A1N(n6285), .B0(n1235), .Y(n6348) );
INVX2TS U2601 ( .A(n3588), .Y(n1674) );
NOR2X1TS U2602 ( .A(n10463), .B(n10204), .Y(n10206) );
NAND2BX1TS U2603 ( .AN(n116), .B(n10912), .Y(n10913) );
INVX1TS U2604 ( .A(n11012), .Y(n10346) );
XOR2X1TS U2605 ( .A(n9941), .B(n9940), .Y(n9942) );
INVX1TS U2606 ( .A(n11010), .Y(n9782) );
NOR2X1TS U2607 ( .A(n10255), .B(n10257), .Y(n10256) );
NAND2XLTS U2608 ( .A(n10477), .B(n10479), .Y(n10482) );
NAND2XLTS U2609 ( .A(n10477), .B(n10470), .Y(n10472) );
OAI21X1TS U2610 ( .A0(n10990), .A1(n10989), .B0(n10988), .Y(n10994) );
OR2X2TS U2611 ( .A(n10998), .B(n11002), .Y(n10999) );
XOR2X1TS U2612 ( .A(n6226), .B(n6175), .Y(n944) );
OAI2BB1X2TS U2613 ( .A0N(n4721), .A1N(n4720), .B0(n1206), .Y(n4739) );
OAI21X1TS U2614 ( .A0(n7793), .A1(n7792), .B0(n7791), .Y(n7794) );
XOR2X1TS U2615 ( .A(n9192), .B(n9191), .Y(n11208) );
OAI21X1TS U2616 ( .A0(n9701), .A1(n9700), .B0(n9699), .Y(n9702) );
INVX1TS U2617 ( .A(n9125), .Y(n9127) );
INVX1TS U2618 ( .A(n7792), .Y(n7763) );
OAI21X1TS U2619 ( .A0(n4956), .A1(n884), .B0(n4955), .Y(n882) );
INVX1TS U2620 ( .A(n4327), .Y(n4329) );
INVX1TS U2621 ( .A(n4328), .Y(n1038) );
NOR2X1TS U2622 ( .A(n9697), .B(n9700), .Y(n9703) );
OAI21X1TS U2623 ( .A0(n7321), .A1(n7320), .B0(n7337), .Y(n7322) );
OAI21X1TS U2624 ( .A0(n4318), .A1(n4328), .B0(n4319), .Y(n4198) );
INVX1TS U2625 ( .A(n9697), .Y(n9619) );
XNOR2X2TS U2626 ( .A(n7749), .B(n1354), .Y(n7727) );
OAI21X1TS U2627 ( .A0(n9586), .A1(n9585), .B0(n9602), .Y(n9587) );
INVX1TS U2628 ( .A(n8037), .Y(n8054) );
INVX1TS U2629 ( .A(n4919), .Y(n4903) );
INVX1TS U2630 ( .A(n9701), .Y(n9618) );
OAI21X1TS U2631 ( .A0(n9701), .A1(n9673), .B0(n9678), .Y(n9611) );
INVX1TS U2632 ( .A(n9076), .Y(n9078) );
ADDFHX1TS U2633 ( .A(n7462), .B(n7461), .CI(n7460), .CO(n7492), .S(n7598) );
XOR2X1TS U2634 ( .A(n7382), .B(n7381), .Y(n7385) );
INVX2TS U2635 ( .A(n2075), .Y(n2088) );
XOR2X1TS U2636 ( .A(n7993), .B(n7992), .Y(n8001) );
INVX1TS U2637 ( .A(n9284), .Y(n3049) );
INVX1TS U2638 ( .A(n1385), .Y(n2228) );
INVX1TS U2639 ( .A(n1684), .Y(n1682) );
INVX1TS U2640 ( .A(n8003), .Y(n5105) );
OAI2BB1X1TS U2641 ( .A0N(n6421), .A1N(n1661), .B0(n6447), .Y(n1660) );
INVX1TS U2642 ( .A(n9563), .Y(n8198) );
INVX1TS U2643 ( .A(n9096), .Y(n9106) );
INVX1TS U2644 ( .A(n2102), .Y(n2068) );
OAI21X1TS U2645 ( .A0(n2470), .A1(n2469), .B0(n2468), .Y(n2471) );
OAI21X1TS U2646 ( .A0(n8195), .A1(n8194), .B0(n8193), .Y(n9569) );
XOR2X2TS U2647 ( .A(n6447), .B(n1663), .Y(n6463) );
NOR2X1TS U2648 ( .A(n8195), .B(n8192), .Y(n9564) );
ADDFHX2TS U2649 ( .A(n5356), .B(n5355), .CI(n5354), .CO(n5403), .S(n5389) );
ADDFHX2TS U2650 ( .A(n6173), .B(n6172), .CI(n6171), .CO(n6202), .S(n6200) );
OAI2BB1X1TS U2651 ( .A0N(n5803), .A1N(n5802), .B0(n1262), .Y(n5819) );
XOR2X2TS U2652 ( .A(n6286), .B(n6284), .Y(n1236) );
NAND2BX1TS U2653 ( .AN(n632), .B(n358), .Y(n7422) );
ADDFHX2TS U2654 ( .A(n9203), .B(n9202), .CI(n9201), .CO(n9225), .S(n8668) );
INVX1TS U2655 ( .A(n2369), .Y(n2154) );
INVX1TS U2656 ( .A(n6800), .Y(n9641) );
INVX1TS U2657 ( .A(n4299), .Y(n4301) );
ADDFHX2TS U2658 ( .A(n5943), .B(n5942), .CI(n5941), .CO(n6697), .S(n5974) );
XOR2X1TS U2659 ( .A(n3300), .B(n3299), .Y(n1537) );
OAI21X1TS U2660 ( .A0(n10474), .A1(n10468), .B0(n10473), .Y(n10478) );
OAI21X1TS U2661 ( .A0(n10429), .A1(n10428), .B0(n10427), .Y(n10430) );
NAND2BX1TS U2662 ( .AN(n10234), .B(n10233), .Y(n10231) );
INVX1TS U2663 ( .A(n10463), .Y(n10477) );
OR2X2TS U2664 ( .A(n10265), .B(n10264), .Y(n10266) );
NAND2BX1TS U2665 ( .AN(n10474), .B(n10473), .Y(n10475) );
NAND2XLTS U2666 ( .A(n10593), .B(n10680), .Y(n10595) );
INVX1TS U2667 ( .A(n11003), .Y(n10998) );
INVX1TS U2668 ( .A(n10605), .Y(n10606) );
CLKAND2X2TS U2669 ( .A(n11005), .B(n11003), .Y(n11010) );
NAND2X1TS U2670 ( .A(n11091), .B(sgf_result_o[40]), .Y(n11738) );
NAND2XLTS U2671 ( .A(n10605), .B(n10613), .Y(n10627) );
NAND2XLTS U2672 ( .A(n11186), .B(sgf_result_o[39]), .Y(n11737) );
INVX1TS U2673 ( .A(n11005), .Y(n9926) );
NAND2BX1TS U2674 ( .AN(n123), .B(n10908), .Y(n10909) );
OAI21X1TS U2675 ( .A0(n9921), .A1(n10987), .B0(n9920), .Y(n9922) );
OAI21X1TS U2676 ( .A0(n10234), .A1(n10251), .B0(n10233), .Y(n10298) );
NOR2X1TS U2677 ( .A(n7761), .B(n7762), .Y(n7792) );
INVX1TS U2678 ( .A(n9397), .Y(n8857) );
OAI21X2TS U2679 ( .A0(n4798), .A1(n4799), .B0(n1542), .Y(n1541) );
XOR2X1TS U2680 ( .A(n3143), .B(n3142), .Y(n1498) );
NOR2X1TS U2681 ( .A(n8197), .B(n8196), .Y(n9563) );
INVX1TS U2682 ( .A(n6221), .Y(n1561) );
NOR2X1TS U2683 ( .A(n7968), .B(n7969), .Y(n8195) );
NOR2X1TS U2684 ( .A(n7037), .B(n197), .Y(n7067) );
ADDFHX2TS U2685 ( .A(n4470), .B(n4469), .CI(n4468), .CO(n4746), .S(n4511) );
INVX1TS U2686 ( .A(n7379), .Y(n5113) );
NOR2X1TS U2687 ( .A(n5104), .B(n5103), .Y(n8003) );
OAI21X2TS U2688 ( .A0(n891), .A1(n4861), .B0(n4860), .Y(n890) );
NAND2BX1TS U2689 ( .AN(n11727), .B(n11205), .Y(n11206) );
XOR2X1TS U2690 ( .A(n442), .B(n7409), .Y(n3137) );
INVX1TS U2691 ( .A(n9136), .Y(n9138) );
OAI2BB1X2TS U2692 ( .A0N(n4248), .A1N(n714), .B0(n713), .Y(n6287) );
OAI21X1TS U2693 ( .A0(n7989), .A1(n7992), .B0(n7990), .Y(n8665) );
NAND2XLTS U2694 ( .A(n8215), .B(n8214), .Y(n8216) );
INVX1TS U2695 ( .A(n6645), .Y(n8559) );
OAI21X1TS U2696 ( .A0(n6646), .A1(n6645), .B0(n6644), .Y(n8550) );
AOI21X1TS U2697 ( .A0(n9152), .A1(n9150), .B0(n4177), .Y(n4178) );
NAND2BX1TS U2698 ( .AN(n116), .B(n10893), .Y(n10894) );
NAND2BX1TS U2699 ( .AN(n116), .B(n10885), .Y(n10886) );
OAI21X1TS U2700 ( .A0(n10433), .A1(n10427), .B0(n10434), .Y(n10089) );
INVX1TS U2701 ( .A(n10468), .Y(n10469) );
NAND2XLTS U2702 ( .A(n10452), .B(n10455), .Y(n10458) );
NOR2X1TS U2703 ( .A(n10673), .B(n10559), .Y(n10605) );
NOR2X1TS U2704 ( .A(n10257), .B(n10265), .Y(n10202) );
NOR2X1TS U2705 ( .A(n9921), .B(n10945), .Y(n9923) );
OAI21X1TS U2706 ( .A0(n10386), .A1(n10383), .B0(n10387), .Y(n10076) );
NOR2X1TS U2707 ( .A(n10464), .B(n10474), .Y(n10479) );
INVX1TS U2708 ( .A(n10937), .Y(n10927) );
INVX1TS U2709 ( .A(n10945), .Y(n10984) );
OAI21X1TS U2710 ( .A0(n10265), .A1(n10486), .B0(n10263), .Y(n10201) );
NAND2BX1TS U2711 ( .AN(n9924), .B(n11545), .Y(n11003) );
OAI21X1TS U2712 ( .A0(n10295), .A1(n10294), .B0(n10293), .Y(n10296) );
NAND2X1TS U2713 ( .A(n11091), .B(sgf_result_o[38]), .Y(n11736) );
INVX1TS U2714 ( .A(n10294), .Y(n10269) );
NOR2X1TS U2715 ( .A(n10291), .B(n10295), .Y(n10297) );
INVX1TS U2716 ( .A(n7756), .Y(n7757) );
INVX1TS U2717 ( .A(n9189), .Y(n4131) );
NOR2X1TS U2718 ( .A(n9577), .B(n9596), .Y(n9675) );
INVX1TS U2719 ( .A(n8192), .Y(n7967) );
INVX2TS U2720 ( .A(n8450), .Y(n138) );
INVX1TS U2721 ( .A(n6019), .Y(n8524) );
OAI21X1TS U2722 ( .A0(n9593), .A1(n9596), .B0(n9597), .Y(n9687) );
INVX1TS U2723 ( .A(n7917), .Y(n6660) );
ADDFHX2TS U2724 ( .A(n4380), .B(n4379), .CI(n4378), .CO(n4509), .S(n4370) );
XOR2X1TS U2725 ( .A(n3658), .B(n3659), .Y(n3637) );
ADDFHX2TS U2726 ( .A(n3885), .B(n3884), .CI(n3883), .CO(n4415), .S(n3964) );
OAI2BB1X2TS U2727 ( .A0N(n4493), .A1N(n4494), .B0(n1548), .Y(n4708) );
INVX1TS U2728 ( .A(n9684), .Y(n9607) );
ADDFHX2TS U2729 ( .A(n5797), .B(n5796), .CI(n5795), .CO(n5805), .S(n5821) );
NOR2X1TS U2730 ( .A(n6682), .B(n6680), .Y(n7299) );
INVX1TS U2731 ( .A(n7487), .Y(n7070) );
INVX1TS U2732 ( .A(n7989), .Y(n7991) );
NOR2X1TS U2733 ( .A(n7315), .B(n7316), .Y(n7320) );
NOR2X1TS U2734 ( .A(n4900), .B(n4908), .Y(n4870) );
NOR2X1TS U2735 ( .A(n6518), .B(n536), .Y(n6554) );
ADDFHX2TS U2736 ( .A(n5007), .B(n5006), .CI(n5005), .CO(n5057), .S(n5001) );
INVX1TS U2737 ( .A(n4924), .Y(n4902) );
OR2X2TS U2738 ( .A(n5112), .B(n5111), .Y(n7380) );
OAI21X1TS U2739 ( .A0(n7328), .A1(n7331), .B0(n7332), .Y(n9527) );
OAI21X1TS U2740 ( .A0(n6682), .A1(n8214), .B0(n6681), .Y(n7304) );
OAI2BB1X2TS U2741 ( .A0N(n4224), .A1N(n4223), .B0(n1198), .Y(n6027) );
NOR2X1TS U2742 ( .A(n6486), .B(n535), .Y(n6526) );
INVX1TS U2743 ( .A(n8456), .Y(n8421) );
NOR2X1TS U2744 ( .A(n7312), .B(n7331), .Y(n9517) );
INVX1TS U2745 ( .A(n5668), .Y(n773) );
INVX1TS U2746 ( .A(n9081), .Y(n9083) );
OAI21X1TS U2747 ( .A0(n4924), .A1(n4908), .B0(n4909), .Y(n4874) );
INVX1TS U2748 ( .A(n8214), .Y(n6668) );
INVX1TS U2749 ( .A(n6680), .Y(n8215) );
INVX1TS U2750 ( .A(n9577), .Y(n9595) );
INVX1TS U2751 ( .A(n9593), .Y(n9594) );
INVX1TS U2752 ( .A(n6682), .Y(n6671) );
INVX1TS U2753 ( .A(n9169), .Y(n9171) );
INVX1TS U2754 ( .A(n10637), .Y(n10638) );
INVX1TS U2755 ( .A(n10195), .Y(n10198) );
OR2X2TS U2756 ( .A(n10075), .B(n10074), .Y(n10387) );
NOR2X1TS U2757 ( .A(n10386), .B(n10384), .Y(n10077) );
OAI21X1TS U2758 ( .A0(n10453), .A1(n10460), .B0(n10459), .Y(n10189) );
NAND2BX1TS U2759 ( .AN(n10966), .B(n9915), .Y(n10945) );
NOR2X1TS U2760 ( .A(n10485), .B(n10484), .Y(n10257) );
NOR2X1TS U2761 ( .A(n10423), .B(n10439), .Y(n10452) );
INVX1TS U2762 ( .A(n10991), .Y(n9919) );
NOR2X1TS U2763 ( .A(n10391), .B(n10078), .Y(n10400) );
OR2X2TS U2764 ( .A(n10969), .B(n10968), .Y(n10961) );
INVX1TS U2765 ( .A(n10362), .Y(n10366) );
INVX1TS U2766 ( .A(n10978), .Y(n10979) );
OR2X2TS U2767 ( .A(n10370), .B(n10369), .Y(n10371) );
INVX1TS U2768 ( .A(n10967), .Y(n10972) );
INVX1TS U2769 ( .A(n10391), .Y(n10407) );
XOR2X1TS U2770 ( .A(n10884), .B(n10883), .Y(n10885) );
XOR2X1TS U2771 ( .A(n10892), .B(n10891), .Y(n10893) );
XOR2X1TS U2772 ( .A(n9762), .B(n9761), .Y(n9925) );
INVX1TS U2773 ( .A(n10464), .Y(n10470) );
NAND2BX1TS U2774 ( .AN(n10439), .B(n10438), .Y(n10440) );
NOR2X1TS U2775 ( .A(n10195), .B(n10196), .Y(n10474) );
NOR2X1TS U2776 ( .A(n10419), .B(n10460), .Y(n10190) );
INVX1TS U2777 ( .A(n9479), .Y(n6342) );
OAI21X1TS U2778 ( .A0(n8125), .A1(n8122), .B0(n8123), .Y(n9481) );
INVX2TS U2779 ( .A(n4595), .Y(n891) );
OAI2BB1X2TS U2780 ( .A0N(n1658), .A1N(n5516), .B0(n1654), .Y(n7969) );
ADDFHX2TS U2781 ( .A(n5744), .B(n5743), .CI(n5742), .CO(n5746), .S(n5777) );
NAND2X2TS U2782 ( .A(n6961), .B(n6971), .Y(n651) );
ADDFHX2TS U2783 ( .A(n3921), .B(n3920), .CI(n3919), .CO(n3948), .S(n3946) );
NOR2X1TS U2784 ( .A(n6421), .B(n6409), .Y(n4518) );
NOR2X1TS U2785 ( .A(n7733), .B(n363), .Y(n7786) );
OAI2BB1X1TS U2786 ( .A0N(n2277), .A1N(n5992), .B0(n2318), .Y(n1342) );
OR2X2TS U2787 ( .A(n6866), .B(n500), .Y(n193) );
INVX1TS U2788 ( .A(n7338), .Y(n7339) );
INVX1TS U2789 ( .A(n1034), .Y(n1033) );
INVX6TS U2790 ( .A(n353), .Y(n139) );
NOR2X1TS U2791 ( .A(n6758), .B(n363), .Y(n6831) );
INVX1TS U2792 ( .A(n9596), .Y(n9598) );
INVX1TS U2793 ( .A(n7085), .Y(n3712) );
INVX1TS U2794 ( .A(EVEN1_Q_left[2]), .Y(n7997) );
INVX1TS U2795 ( .A(n8103), .Y(n949) );
NOR2X1TS U2796 ( .A(n6412), .B(n536), .Y(n6451) );
OR2X2TS U2797 ( .A(n6848), .B(n6847), .Y(n7759) );
NAND2X1TS U2798 ( .A(n3134), .B(n3133), .Y(n3135) );
INVX1TS U2799 ( .A(n8032), .Y(n7211) );
NAND2XLTS U2800 ( .A(n1707), .B(n9460), .Y(n9461) );
INVX1TS U2801 ( .A(n9698), .Y(n9699) );
INVX1TS U2802 ( .A(n8547), .Y(n6649) );
OR2X2TS U2803 ( .A(n6651), .B(n6650), .Y(n9458) );
NOR2X1TS U2804 ( .A(n5468), .B(n5470), .Y(n2562) );
NOR2X1TS U2805 ( .A(n8028), .B(n8031), .Y(n8053) );
OR2X2TS U2806 ( .A(n5944), .B(n5950), .Y(n189) );
OAI21X1TS U2807 ( .A0(n8032), .A1(n8031), .B0(n8030), .Y(n8052) );
NOR2X1TS U2808 ( .A(n6666), .B(n6667), .Y(n6680) );
INVX1TS U2809 ( .A(n9460), .Y(n6654) );
NOR2X1TS U2810 ( .A(n6490), .B(n6484), .Y(n4900) );
INVX1TS U2811 ( .A(n6517), .Y(n6518) );
NAND2BX1TS U2812 ( .AN(n11729), .B(n11203), .Y(n11204) );
INVX1TS U2813 ( .A(n6485), .Y(n6486) );
INVX1TS U2814 ( .A(n4780), .Y(n4781) );
XOR2X1TS U2815 ( .A(n8126), .B(n8125), .Y(n8127) );
OAI21X2TS U2816 ( .A0(n4223), .A1(n4224), .B0(n4222), .Y(n1198) );
INVX1TS U2817 ( .A(n2921), .Y(n2807) );
NOR2X1TS U2818 ( .A(n7293), .B(n7294), .Y(n7302) );
NOR2X1TS U2819 ( .A(n6670), .B(n6669), .Y(n6682) );
INVX1TS U2820 ( .A(n9642), .Y(n6797) );
AND2X2TS U2821 ( .A(n5109), .B(n5108), .Y(n5112) );
INVX1TS U2822 ( .A(n5108), .Y(n5093) );
INVX1TS U2823 ( .A(n6794), .Y(n9639) );
INVX1TS U2824 ( .A(n3525), .Y(n3526) );
INVX1TS U2825 ( .A(n8118), .Y(n1539) );
INVX1TS U2826 ( .A(n7328), .Y(n7329) );
INVX1TS U2827 ( .A(n7312), .Y(n7330) );
NOR2X1TS U2828 ( .A(n7797), .B(n7798), .Y(n8192) );
NAND2XLTS U2829 ( .A(n10793), .B(n10792), .Y(n10798) );
NOR2X1TS U2830 ( .A(n10072), .B(n10073), .Y(n10386) );
NOR2X1TS U2831 ( .A(n10191), .B(n10192), .Y(n10464) );
INVX1TS U2832 ( .A(n10192), .Y(n10193) );
INVX1TS U2833 ( .A(n10453), .Y(n10454) );
INVX1TS U2834 ( .A(n10419), .Y(n10455) );
INVX1TS U2835 ( .A(n10191), .Y(n10194) );
NOR2X1TS U2836 ( .A(n10329), .B(n10333), .Y(n10031) );
OR2X2TS U2837 ( .A(n10082), .B(n10081), .Y(n10408) );
INVX1TS U2838 ( .A(n10966), .Y(n10960) );
INVX1TS U2839 ( .A(n10970), .Y(n9914) );
NOR2X1TS U2840 ( .A(n10393), .B(n10392), .Y(n10391) );
OAI21X1TS U2841 ( .A0(n10329), .A1(n10332), .B0(n10328), .Y(n10030) );
NOR2X1TS U2842 ( .A(n10188), .B(n10187), .Y(n10460) );
AND2X2TS U2843 ( .A(n10393), .B(n10392), .Y(n10406) );
INVX1TS U2844 ( .A(n10965), .Y(n10969) );
NAND2BX1TS U2845 ( .AN(n10649), .B(n10648), .Y(n10650) );
OR2X2TS U2846 ( .A(n10364), .B(n10363), .Y(n10362) );
NOR2X1TS U2847 ( .A(n10433), .B(n10429), .Y(n10090) );
INVX1TS U2848 ( .A(n10196), .Y(n10197) );
NOR2X1TS U2849 ( .A(n10616), .B(n10151), .Y(n10637) );
OAI2BB1X1TS U2850 ( .A0N(n1959), .A1N(n1958), .B0(n1238), .Y(n1809) );
NOR2X1TS U2851 ( .A(n6657), .B(n6658), .Y(n7916) );
OR2X2TS U2852 ( .A(n6796), .B(n6795), .Y(n9643) );
INVX1TS U2853 ( .A(n7732), .Y(n7733) );
XOR2X1TS U2854 ( .A(n7986), .B(n7985), .Y(n7987) );
INVX1TS U2855 ( .A(n6008), .Y(n6001) );
NOR2X1TS U2856 ( .A(n7309), .B(n7310), .Y(n7312) );
OAI2BB1X2TS U2857 ( .A0N(n1965), .A1N(n1964), .B0(n695), .Y(n1955) );
XNOR2X2TS U2858 ( .A(n654), .B(n4188), .Y(n4191) );
OAI21X1TS U2859 ( .A0(n5600), .A1(n5601), .B0(n5599), .Y(n666) );
INVX3TS U2860 ( .A(n6658), .Y(n4689) );
NAND2BX1TS U2861 ( .AN(n453), .B(n8428), .Y(n1604) );
INVX1TS U2862 ( .A(n5107), .Y(n3044) );
NOR2X1TS U2863 ( .A(n2063), .B(n2062), .Y(n2082) );
NOR2X1TS U2864 ( .A(n7200), .B(n7201), .Y(n8028) );
INVX1TS U2865 ( .A(n8031), .Y(n7219) );
XNOR2X1TS U2866 ( .A(n3159), .B(n3132), .Y(n3136) );
INVX1TS U2867 ( .A(n9102), .Y(n9104) );
NOR2X1TS U2868 ( .A(n9579), .B(n9578), .Y(n9596) );
OAI21X1TS U2869 ( .A0(n8101), .A1(n8098), .B0(n8099), .Y(n8516) );
ADDFHX2TS U2870 ( .A(n3825), .B(n3824), .CI(n3823), .CO(n4383), .S(n3820) );
INVX1TS U2871 ( .A(n8560), .Y(n6643) );
INVX1TS U2872 ( .A(n9097), .Y(n9099) );
OAI21X1TS U2873 ( .A0(n9678), .A1(n9677), .B0(n9676), .Y(n9698) );
OAI21X1TS U2874 ( .A0(n2316), .A1(n2317), .B0(n2315), .Y(n933) );
NOR2X1TS U2875 ( .A(n6828), .B(n363), .Y(n7746) );
INVX1TS U2876 ( .A(n9109), .Y(n1904) );
OR2X2TS U2877 ( .A(n6433), .B(n6439), .Y(n1705) );
XOR2X1TS U2878 ( .A(n2800), .B(n2786), .Y(n2787) );
INVX1TS U2879 ( .A(n9117), .Y(n1903) );
NOR2X1TS U2880 ( .A(n6187), .B(n535), .Y(n6319) );
ADDFHX2TS U2881 ( .A(n6128), .B(n6127), .CI(n6126), .CO(n7293), .S(n6684) );
INVX1TS U2882 ( .A(n6757), .Y(n6758) );
OR2X2TS U2883 ( .A(n7325), .B(n7324), .Y(n7341) );
XOR2X1TS U2884 ( .A(n4551), .B(n4550), .Y(EVEN1_Q_left[2]) );
INVX1TS U2885 ( .A(n2065), .Y(n1387) );
NOR2X1TS U2886 ( .A(n9799), .B(n10882), .Y(n9804) );
NOR2X1TS U2887 ( .A(n10087), .B(n10085), .Y(n10433) );
NAND2BX1TS U2888 ( .AN(n117), .B(n10850), .Y(n10851) );
INVX1TS U2889 ( .A(n9799), .Y(n9802) );
NOR2X1TS U2890 ( .A(n10315), .B(n11367), .Y(n10317) );
AO21X1TS U2891 ( .A0(n10871), .A1(n9789), .B0(n9788), .Y(n10902) );
NOR2X1TS U2892 ( .A(n10052), .B(n10051), .Y(n10370) );
INVX1TS U2893 ( .A(n10334), .Y(n10335) );
NAND2XLTS U2894 ( .A(n11186), .B(sgf_result_o[34]), .Y(n11735) );
INVX1TS U2895 ( .A(n10184), .Y(n10117) );
NAND2BX1TS U2896 ( .AN(n10029), .B(n10028), .Y(n10328) );
INVX1TS U2897 ( .A(n10685), .Y(n10649) );
NOR2X1TS U2898 ( .A(n10079), .B(n10080), .Y(n10078) );
INVX1TS U2899 ( .A(n10777), .Y(n10706) );
INVX1TS U2900 ( .A(n10080), .Y(n10081) );
INVX1TS U2901 ( .A(n10882), .Y(n10896) );
NOR2X1TS U2902 ( .A(n10186), .B(n10185), .Y(n10419) );
NAND2BX1TS U2903 ( .AN(n10955), .B(n10954), .Y(n10956) );
AOI2BB1X1TS U2904 ( .A0N(n10955), .A1N(n10951), .B0(n9910), .Y(n10970) );
NAND2XLTS U2905 ( .A(n9903), .B(n9902), .Y(n10977) );
NAND2XLTS U2906 ( .A(n10777), .B(n10776), .Y(n10779) );
NAND2BX1TS U2907 ( .AN(n125), .B(n10860), .Y(n10861) );
AO21X1TS U2908 ( .A0(n10928), .A1(n10925), .B0(n10929), .Y(n10935) );
XOR2X1TS U2909 ( .A(n9845), .B(n9844), .Y(n1704) );
NAND2XLTS U2910 ( .A(n10727), .B(n10726), .Y(n10728) );
NOR2X1TS U2911 ( .A(n10121), .B(n10178), .Y(n10439) );
NOR2X1TS U2912 ( .A(n10071), .B(n10070), .Y(n10384) );
NOR2X1TS U2913 ( .A(n9581), .B(n9580), .Y(n9585) );
INVX1TS U2914 ( .A(n9705), .Y(n9681) );
NOR2X1TS U2915 ( .A(n6058), .B(n536), .Y(n6067) );
INVX1TS U2916 ( .A(n7361), .Y(n7350) );
OAI2BB1X2TS U2917 ( .A0N(n5292), .A1N(n5291), .B0(n1425), .Y(n9579) );
XOR2X1TS U2918 ( .A(n4114), .B(n867), .Y(n866) );
ADDFHX2TS U2919 ( .A(n6160), .B(n6159), .CI(n6158), .CO(n7309), .S(n7294) );
INVX1TS U2920 ( .A(n7358), .Y(n7355) );
OAI2BB1X2TS U2921 ( .A0N(n6110), .A1N(n6109), .B0(n1220), .Y(n6296) );
INVX1TS U2922 ( .A(n8122), .Y(n8124) );
INVX1TS U2923 ( .A(n5948), .Y(n5949) );
INVX1TS U2924 ( .A(n6717), .Y(n6718) );
ADDFX1TS U2925 ( .A(n4521), .B(n4522), .CI(n4523), .CO(n6433), .S(n6409) );
XOR2X2TS U2926 ( .A(n4175), .B(n4176), .Y(n915) );
OR2X2TS U2927 ( .A(n6332), .B(n6331), .Y(n8558) );
OAI2BB1X1TS U2928 ( .A0N(n4115), .A1N(n4114), .B0(n865), .Y(n4377) );
INVX1TS U2929 ( .A(n8114), .Y(n6337) );
AO21X1TS U2930 ( .A0(n551), .A1(n465), .B0(n392), .Y(n6938) );
ADDFHX2TS U2931 ( .A(n6364), .B(n6365), .CI(n6363), .CO(n7325), .S(n7315) );
NOR2X1TS U2932 ( .A(n5427), .B(n363), .Y(n5467) );
XOR2X1TS U2933 ( .A(n7217), .B(n1352), .Y(n6830) );
OAI21X1TS U2934 ( .A0(n7362), .A1(n7361), .B0(n7360), .Y(n9521) );
XOR2X2TS U2935 ( .A(n4247), .B(n4248), .Y(n715) );
INVX1TS U2936 ( .A(n4908), .Y(n4910) );
NOR2X1TS U2937 ( .A(n7358), .B(n7361), .Y(n9515) );
INVX1TS U2938 ( .A(n2985), .Y(n2986) );
XOR2X1TS U2939 ( .A(n2858), .B(n3635), .Y(n2840) );
ADDFHX2TS U2940 ( .A(n3894), .B(n3893), .CI(n3892), .CO(n3896), .S(n3916) );
NOR2X1TS U2941 ( .A(n7782), .B(n7781), .Y(n7960) );
AO21X1TS U2942 ( .A0(n423), .A1(n490), .B0(n7778), .Y(n7957) );
INVX2TS U2943 ( .A(n790), .Y(n7107) );
OR2X2TS U2944 ( .A(n8034), .B(n8033), .Y(n8062) );
NOR2X1TS U2945 ( .A(n7218), .B(n7217), .Y(n8031) );
XOR2X1TS U2946 ( .A(n6977), .B(n6976), .Y(n6979) );
INVX1TS U2947 ( .A(n6827), .Y(n6828) );
INVX1TS U2948 ( .A(n5516), .Y(n1655) );
OAI21X1TS U2949 ( .A0(n7217), .A1(n1350), .B0(n1349), .Y(n7731) );
OR2X2TS U2950 ( .A(n2277), .B(n2281), .Y(n9114) );
NOR2X1TS U2951 ( .A(n3168), .B(n3169), .Y(n1081) );
XOR2X1TS U2952 ( .A(n3157), .B(n3168), .Y(n3158) );
INVX1TS U2953 ( .A(n8650), .Y(n8652) );
INVX1TS U2954 ( .A(n4871), .Y(n4872) );
ADDFX1TS U2955 ( .A(n330), .B(n526), .CI(n6860), .CO(n6864), .S(n6862) );
INVX1TS U2956 ( .A(n4232), .Y(n1409) );
NAND2BXLTS U2957 ( .AN(n3514), .B(n611), .Y(n2907) );
INVX1TS U2958 ( .A(n10974), .Y(n9902) );
NOR2X1TS U2959 ( .A(n10725), .B(n10705), .Y(n10777) );
NAND2XLTS U2960 ( .A(n10975), .B(n10974), .Y(n9912) );
INVX1TS U2961 ( .A(n10868), .Y(n10869) );
INVX1TS U2962 ( .A(n10898), .Y(n10895) );
INVX1TS U2963 ( .A(n10919), .Y(n10920) );
XOR2X1TS U2964 ( .A(n9981), .B(n11292), .Y(n10057) );
NOR2X1TS U2965 ( .A(n10323), .B(n10725), .Y(n10685) );
OAI21X1TS U2966 ( .A0(n9746), .A1(n9745), .B0(n9744), .Y(n9845) );
INVX1TS U2967 ( .A(n10938), .Y(n9825) );
INVX1TS U2968 ( .A(n10683), .Y(n10684) );
XOR2X1TS U2969 ( .A(n10044), .B(n9997), .Y(n10029) );
NOR2X1TS U2970 ( .A(n10683), .B(n10557), .Y(n10558) );
NAND2BX1TS U2971 ( .AN(n10158), .B(n9904), .Y(n9870) );
NAND2XLTS U2972 ( .A(n10680), .B(n10602), .Y(n10559) );
OAI21X1TS U2973 ( .A0(n9726), .A1(n9725), .B0(n9724), .Y(n10871) );
INVX1TS U2974 ( .A(n9911), .Y(n9887) );
INVX1TS U2975 ( .A(n10045), .Y(n10048) );
INVX1TS U2976 ( .A(n10954), .Y(n9910) );
INVX1TS U2977 ( .A(n7381), .Y(n5114) );
OAI21X1TS U2978 ( .A0(n4283), .A1(n4284), .B0(n4282), .Y(n699) );
AND2X2TS U2979 ( .A(n5025), .B(n7985), .Y(n5089) );
OR2X2TS U2980 ( .A(n9680), .B(n9679), .Y(n9706) );
OAI21X1TS U2981 ( .A0(n2488), .A1(n1334), .B0(n2487), .Y(n1333) );
OAI21X1TS U2982 ( .A0(n247), .A1(n475), .B0(n1472), .Y(n1470) );
OAI21X2TS U2983 ( .A0(n5291), .A1(n5292), .B0(n5290), .Y(n1425) );
NOR2X1TS U2984 ( .A(n6051), .B(n535), .Y(n6061) );
OR2X2TS U2985 ( .A(n4124), .B(n4125), .Y(n9198) );
AO21X1TS U2986 ( .A0(n589), .A1(n488), .B0(n6047), .Y(n6368) );
NOR2X1TS U2987 ( .A(n5195), .B(n363), .Y(n5208) );
INVX1TS U2988 ( .A(n6338), .Y(n777) );
XOR2X1TS U2989 ( .A(n8091), .B(n8090), .Y(n8092) );
OAI2BB1X2TS U2990 ( .A0N(n341), .A1N(n344), .B0(n819), .Y(n3168) );
INVX1TS U2991 ( .A(n7744), .Y(n7745) );
OR2X2TS U2992 ( .A(n5992), .B(n5993), .Y(n8523) );
INVX3TS U2993 ( .A(n8239), .Y(n551) );
INVX1TS U2994 ( .A(n8079), .Y(n5986) );
NOR2X1TS U2995 ( .A(n7345), .B(n7344), .Y(n7358) );
INVX1TS U2996 ( .A(n8514), .Y(n5991) );
INVX1TS U2997 ( .A(n4547), .Y(n4549) );
INVX1TS U2998 ( .A(n2924), .Y(n1113) );
OAI21X1TS U2999 ( .A0(n7982), .A1(n7985), .B0(n7983), .Y(n8116) );
INVX1TS U3000 ( .A(n3167), .Y(n1082) );
OR2X2TS U3001 ( .A(n6546), .B(n6576), .Y(n4873) );
INVX1TS U3002 ( .A(n8655), .Y(n8657) );
NOR2X1TS U3003 ( .A(n5337), .B(n363), .Y(n5387) );
INVX1TS U3004 ( .A(n4343), .Y(n3942) );
NOR2X1TS U3005 ( .A(n6597), .B(n6596), .Y(n6634) );
INVX2TS U3006 ( .A(n2413), .Y(n2532) );
INVX1TS U3007 ( .A(n4233), .Y(n1408) );
INVX1TS U3008 ( .A(n2294), .Y(n2417) );
ADDFHX2TS U3009 ( .A(n4221), .B(n4220), .CI(n4219), .CO(n4231), .S(n4224) );
INVX1TS U3010 ( .A(n2160), .Y(n2206) );
NAND2X1TS U3011 ( .A(n11194), .B(n11730), .Y(n11195) );
XOR2X2TS U3012 ( .A(n4282), .B(n4284), .Y(n700) );
INVX1TS U3013 ( .A(n6575), .Y(n6577) );
XOR2X2TS U3014 ( .A(n1472), .B(n1471), .Y(n2596) );
NOR2X1TS U3015 ( .A(n6338), .B(n6339), .Y(n8122) );
INVX4TS U3016 ( .A(n1490), .Y(n3685) );
ADDFHX1TS U3017 ( .A(n3938), .B(n3937), .CI(n3936), .CO(n3930), .S(n3941) );
NAND2BX1TS U3018 ( .AN(n1689), .B(n10044), .Y(n10045) );
XOR2X1TS U3019 ( .A(n10243), .B(n11564), .Y(n10634) );
NAND2BX1TS U3020 ( .AN(n117), .B(n10828), .Y(n10829) );
INVX1TS U3021 ( .A(n10925), .Y(n10910) );
XOR2X1TS U3022 ( .A(n10113), .B(n11237), .Y(n10182) );
XOR2X1TS U3023 ( .A(n10098), .B(n11238), .Y(n10124) );
INVX1TS U3024 ( .A(n10016), .Y(n9932) );
NAND2XLTS U3025 ( .A(n10809), .B(n10792), .Y(n10557) );
XOR2X1TS U3026 ( .A(n10150), .B(n11568), .Y(n10623) );
INVX1TS U3027 ( .A(n10018), .Y(n10019) );
XOR2X1TS U3028 ( .A(n9901), .B(n9900), .Y(n10974) );
INVX1TS U3029 ( .A(n9909), .Y(n9904) );
NAND2XLTS U3030 ( .A(n10158), .B(n9909), .Y(n10954) );
XOR2X1TS U3031 ( .A(n9886), .B(n9885), .Y(n9911) );
INVX1TS U3032 ( .A(n10704), .Y(n10705) );
INVX1TS U3033 ( .A(n10738), .Y(n10579) );
NAND2XLTS U3034 ( .A(n10738), .B(n10737), .Y(n10739) );
XOR2X1TS U3035 ( .A(n10157), .B(n11565), .Y(n10680) );
XOR2X1TS U3036 ( .A(n9966), .B(n11291), .Y(n9987) );
INVX1TS U3037 ( .A(n9901), .Y(n9745) );
INVX1TS U3038 ( .A(n10332), .Y(n10326) );
AND2X2TS U3039 ( .A(n8017), .B(n8090), .Y(n8075) );
OAI21X1TS U3040 ( .A0(n345), .A1(n342), .B0(n3695), .Y(n907) );
OAI21X2TS U3041 ( .A0(n4186), .A1(n4187), .B0(n4185), .Y(n838) );
INVX1TS U3042 ( .A(n3695), .Y(n3696) );
OAI2BB1X1TS U3043 ( .A0N(n6075), .A1N(n6074), .B0(n6096), .Y(n6076) );
NAND2XLTS U3044 ( .A(n9690), .B(n1697), .Y(n9691) );
NAND3X1TS U3045 ( .A(n5491), .B(n5490), .C(n5489), .Y(n5551) );
INVX1TS U3046 ( .A(n7375), .Y(n9268) );
INVX1TS U3047 ( .A(n5095), .Y(n5097) );
INVX1TS U3048 ( .A(n1822), .Y(n910) );
INVX1TS U3049 ( .A(n1821), .Y(n911) );
ADDFHX2TS U3050 ( .A(n4771), .B(n4770), .CI(n4769), .CO(n6529), .S(n6484) );
NOR2X1TS U3051 ( .A(n2778), .B(n2782), .Y(n2755) );
AO21X1TS U3052 ( .A0(n578), .A1(n469), .B0(n6547), .Y(n6575) );
NAND2XLTS U3053 ( .A(n461), .B(n380), .Y(n1609) );
INVX1TS U3054 ( .A(n2014), .Y(n2042) );
OR2X2TS U3055 ( .A(n7369), .B(n7368), .Y(n9520) );
OAI21X1TS U3056 ( .A0(n8087), .A1(n8090), .B0(n8088), .Y(n8081) );
INVX1TS U3057 ( .A(n4545), .Y(n2048) );
ADDFHX1TS U3058 ( .A(n2284), .B(n2283), .CI(n2282), .CO(n5994), .S(n5992) );
OAI22X1TS U3059 ( .A0(n587), .A1(n3776), .B0(n4405), .B1(n473), .Y(n4372) );
INVX1TS U3060 ( .A(n6053), .Y(n6054) );
OAI21X1TS U3061 ( .A0(n2779), .A1(n2783), .B0(n2778), .Y(n2781) );
INVX2TS U3062 ( .A(n8423), .Y(n141) );
OAI21X1TS U3063 ( .A0(n6310), .A1(n6311), .B0(n6308), .Y(n6309) );
OAI2BB1X2TS U3064 ( .A0N(n338), .A1N(n248), .B0(n721), .Y(n2797) );
INVX1TS U3065 ( .A(n5509), .Y(n5269) );
OR2X2TS U3066 ( .A(n3910), .B(n3909), .Y(n3894) );
OR2X2TS U3067 ( .A(n5990), .B(n5989), .Y(n8515) );
XOR2X1TS U3068 ( .A(n10222), .B(n11562), .Y(n10613) );
NOR2X1TS U3069 ( .A(n9975), .B(n1703), .Y(n10704) );
XOR2X1TS U3070 ( .A(n10211), .B(n11563), .Y(n10602) );
XOR2X1TS U3071 ( .A(n10166), .B(n11570), .Y(n10809) );
XOR2X1TS U3072 ( .A(n10132), .B(n11566), .Y(n10792) );
NOR2X1TS U3073 ( .A(n10750), .B(n1699), .Y(n10738) );
XOR2X1TS U3074 ( .A(n10142), .B(n11567), .Y(n10645) );
XOR2X1TS U3075 ( .A(n9850), .B(n11395), .Y(n10273) );
XOR2X1TS U3076 ( .A(n9897), .B(n11453), .Y(n10975) );
INVX1TS U3077 ( .A(n10325), .Y(n10007) );
XOR2X1TS U3078 ( .A(n9812), .B(n11462), .Y(n10133) );
INVX1TS U3079 ( .A(n10043), .Y(n10049) );
XOR2X1TS U3080 ( .A(n9857), .B(n11459), .Y(n10143) );
AOI2BB1X1TS U3081 ( .A0N(n10034), .A1N(n9979), .B0(n9978), .Y(n9980) );
OR2X2TS U3082 ( .A(n10023), .B(n10022), .Y(n10340) );
NAND2BX1TS U3083 ( .AN(n9954), .B(n11556), .Y(n10890) );
INVX1TS U3084 ( .A(n9906), .Y(n9907) );
INVX1TS U3085 ( .A(n9784), .Y(n9785) );
INVX1TS U3086 ( .A(n10028), .Y(n10001) );
XOR2X1TS U3087 ( .A(n798), .B(n5263), .Y(n5533) );
OR2X2TS U3088 ( .A(n6896), .B(n6898), .Y(n190) );
INVX1TS U3089 ( .A(n5620), .Y(n5196) );
XOR2X1TS U3090 ( .A(n4040), .B(n187), .Y(n1202) );
NAND2BX1TS U3091 ( .AN(n631), .B(n396), .Y(n3927) );
XOR2X2TS U3092 ( .A(n2165), .B(n1420), .Y(n5702) );
NAND2BX1TS U3093 ( .AN(n1979), .B(n1325), .Y(n1324) );
INVX1TS U3094 ( .A(n5984), .Y(n2041) );
ADDFHX1TS U3095 ( .A(n5228), .B(n5227), .CI(n5226), .CO(n5301), .S(n5296) );
INVX1TS U3096 ( .A(n8015), .Y(n2060) );
NAND2BX1TS U3097 ( .AN(n628), .B(n425), .Y(n5562) );
ADDFX1TS U3098 ( .A(n2359), .B(n2358), .CI(n2357), .CO(n2373), .S(n2348) );
INVX1TS U3099 ( .A(n8087), .Y(n8089) );
AND2X6TS U3100 ( .A(n6312), .B(n3757), .Y(n6313) );
OAI21X1TS U3101 ( .A0(n5174), .A1(n5177), .B0(n5178), .Y(n974) );
NAND2X1TS U3102 ( .A(n880), .B(n852), .Y(n879) );
XOR2X1TS U3103 ( .A(n4054), .B(n871), .Y(n870) );
OAI21X1TS U3104 ( .A0(n3843), .A1(n898), .B0(n1177), .Y(n4092) );
NAND2X4TS U3105 ( .A(n664), .B(n980), .Y(n5186) );
ADDFHX2TS U3106 ( .A(n2290), .B(n2289), .CI(n2288), .CO(n2411), .S(n2282) );
ADDFHX2TS U3107 ( .A(n2280), .B(n2279), .CI(n2278), .CO(n5993), .S(n5990) );
NAND2X1TS U3108 ( .A(n8016), .B(n8015), .Y(n8090) );
ADDFHX1TS U3109 ( .A(n2524), .B(n2523), .CI(n2522), .CO(n5693), .S(n2545) );
ADDFX1TS U3110 ( .A(n4529), .B(n4528), .CI(n4527), .CO(n4757), .S(n4524) );
CLKINVX2TS U3111 ( .A(n3609), .Y(n3610) );
ADDFHX1TS U3112 ( .A(n3982), .B(n3981), .CI(n3980), .CO(n3989), .S(n4052) );
NAND2X6TS U3113 ( .A(n1055), .B(n1052), .Y(n3814) );
NAND2BX1TS U3114 ( .AN(n10046), .B(n10044), .Y(n10043) );
INVX1TS U3115 ( .A(n9880), .Y(n9869) );
NAND2BX1TS U3116 ( .AN(n9968), .B(n11554), .Y(n9786) );
NAND2XLTS U3117 ( .A(n9968), .B(n11520), .Y(n9784) );
XOR2X1TS U3118 ( .A(n9955), .B(n11571), .Y(n10788) );
XOR2X1TS U3119 ( .A(n10112), .B(n11293), .Y(n10040) );
XOR2X1TS U3120 ( .A(n9794), .B(n11398), .Y(n9952) );
XOR2X1TS U3121 ( .A(n9807), .B(n11456), .Y(n10128) );
XOR2X1TS U3122 ( .A(n9790), .B(n11458), .Y(n10104) );
XOR2X1TS U3123 ( .A(n9792), .B(n11460), .Y(n10099) );
OAI21X1TS U3124 ( .A0(n10279), .A1(n10153), .B0(n10152), .Y(n10154) );
INVX1TS U3125 ( .A(n10112), .Y(n10034) );
INVX1TS U3126 ( .A(n10027), .Y(n10324) );
INVX1TS U3127 ( .A(n10862), .Y(n10863) );
NAND2XLTS U3128 ( .A(n11186), .B(sgf_result_o[30]), .Y(n11733) );
NAND2BX1TS U3129 ( .AN(n123), .B(n10824), .Y(n10825) );
INVX1TS U3130 ( .A(n10857), .Y(n9723) );
OAI21X1TS U3131 ( .A0(n9718), .A1(n10821), .B0(n11508), .Y(n10839) );
XOR2X1TS U3132 ( .A(n9841), .B(n11396), .Y(n10237) );
INVX1TS U3133 ( .A(n10873), .Y(n10874) );
XOR2X1TS U3134 ( .A(n4978), .B(n509), .Y(n4979) );
INVX2TS U3135 ( .A(n5099), .Y(n3929) );
INVX1TS U3136 ( .A(n5100), .Y(n3928) );
CLKINVX2TS U3137 ( .A(n4442), .Y(n4277) );
NAND2X4TS U3138 ( .A(n6493), .B(n4499), .Y(n6494) );
NOR2X1TS U3139 ( .A(n4652), .B(n4666), .Y(n4655) );
INVX1TS U3140 ( .A(n4262), .Y(n4246) );
NOR2X2TS U3141 ( .A(n1414), .B(n1420), .Y(n1413) );
XOR2X1TS U3142 ( .A(n3322), .B(n3323), .Y(n8253) );
INVX1TS U3143 ( .A(n6763), .Y(n6734) );
INVX1TS U3144 ( .A(n5246), .Y(n5229) );
INVX1TS U3145 ( .A(n4118), .Y(n3922) );
AND2X2TS U3146 ( .A(n6917), .B(n6916), .Y(n196) );
INVX1TS U3147 ( .A(n8016), .Y(n2043) );
INVX1TS U3148 ( .A(n5983), .Y(n2044) );
NAND2X4TS U3149 ( .A(n3738), .B(n1641), .Y(n1055) );
INVX1TS U3150 ( .A(n6592), .Y(n4884) );
INVX1TS U3151 ( .A(n6523), .Y(n6496) );
INVX1TS U3152 ( .A(n5530), .Y(n5321) );
XNOR2X1TS U3153 ( .A(n5068), .B(n3775), .Y(n4405) );
INVX1TS U3154 ( .A(n6103), .Y(n6090) );
XOR2X1TS U3155 ( .A(n6094), .B(n6093), .Y(n6095) );
XOR2X1TS U3156 ( .A(n6879), .B(n6880), .Y(n8426) );
XOR2XLTS U3157 ( .A(n2686), .B(n2869), .Y(n2687) );
NOR2X1TS U3158 ( .A(n10275), .B(n10278), .Y(n10282) );
OAI21X1TS U3159 ( .A0(n10279), .A1(n10278), .B0(n10277), .Y(n10280) );
INVX1TS U3160 ( .A(n9760), .Y(n9758) );
XOR2X1TS U3161 ( .A(n10000), .B(n11239), .Y(n10003) );
INVX1TS U3162 ( .A(n9759), .Y(n9757) );
NOR2X1TS U3163 ( .A(n9750), .B(n9749), .Y(n9842) );
INVX1TS U3164 ( .A(n9843), .Y(n9751) );
INVX1TS U3165 ( .A(n9755), .Y(n9753) );
XOR2X1TS U3166 ( .A(n9729), .B(n11401), .Y(n9968) );
INVX1TS U3167 ( .A(n9864), .Y(n9865) );
OAI21X1TS U3168 ( .A0(n9858), .A1(n11376), .B0(n11374), .Y(n9862) );
INVX1TS U3169 ( .A(n9882), .Y(n9884) );
NAND2BX1TS U3170 ( .AN(n10238), .B(n11600), .Y(n10152) );
INVX1TS U3171 ( .A(n9874), .Y(n9875) );
INVX1TS U3172 ( .A(n10832), .Y(n9719) );
NAND2BX1TS U3173 ( .AN(n10238), .B(n11601), .Y(n10239) );
INVX1TS U3174 ( .A(n9854), .Y(n9855) );
AOI2BB1X1TS U3175 ( .A0N(n10155), .A1N(n11617), .B0(n11593), .Y(n9955) );
NOR2X1TS U3176 ( .A(n10275), .B(n10240), .Y(n10242) );
INVX1TS U3177 ( .A(n10841), .Y(n10845) );
INVX1TS U3178 ( .A(n9721), .Y(n10847) );
AOI2BB1X1TS U3179 ( .A0N(n10155), .A1N(n11616), .B0(n10100), .Y(n10101) );
INVX1TS U3180 ( .A(n10914), .Y(n9824) );
INVX1TS U3181 ( .A(n10147), .Y(n10144) );
OAI21X1TS U3182 ( .A0(n10279), .A1(n10147), .B0(n10146), .Y(n10148) );
OAI21X1TS U3183 ( .A0(n10279), .A1(n10139), .B0(n10138), .Y(n10140) );
OAI21X1TS U3184 ( .A0(n10279), .A1(n10208), .B0(n10207), .Y(n10209) );
CLKINVX2TS U3185 ( .A(n9971), .Y(n10109) );
OAI21X1TS U3186 ( .A0(n9796), .A1(n11406), .B0(n9791), .Y(n9792) );
OAI21X1TS U3187 ( .A0(n10279), .A1(n10219), .B0(n10218), .Y(n10220) );
AO21X1TS U3188 ( .A0(n357), .A1(n598), .B0(n522), .Y(n6521) );
XOR2X2TS U3189 ( .A(n1566), .B(n1563), .Y(n6493) );
INVX1TS U3190 ( .A(n5021), .Y(n4349) );
INVX1TS U3191 ( .A(n5982), .Y(n2034) );
INVX1TS U3192 ( .A(n2006), .Y(n2035) );
INVX1TS U3193 ( .A(n6915), .Y(n6917) );
INVX1TS U3194 ( .A(n7776), .Y(n7740) );
INVX1TS U3195 ( .A(n6909), .Y(n6910) );
OAI21X1TS U3196 ( .A0(n3313), .A1(n3312), .B0(n3311), .Y(n6912) );
XOR2X1TS U3197 ( .A(n3226), .B(n3321), .Y(n3227) );
INVX1TS U3198 ( .A(n5433), .Y(n5372) );
INVX2TS U3199 ( .A(n188), .Y(n142) );
NAND2BX1TS U3200 ( .AN(n4253), .B(n4071), .Y(n899) );
OAI22X1TS U3201 ( .A0(n6086), .A1(n6039), .B0(n6084), .B1(n6085), .Y(n6072)
);
INVX1TS U3202 ( .A(n6824), .Y(n6769) );
INVX1TS U3203 ( .A(n6898), .Y(n6893) );
OAI21X1TS U3204 ( .A0(n6915), .A1(n6909), .B0(n6916), .Y(n6891) );
AO21X1TS U3205 ( .A0(n550), .A1(n1389), .B0(n4031), .Y(n4203) );
INVX1TS U3206 ( .A(n4983), .Y(n4676) );
XOR2X1TS U3207 ( .A(n4849), .B(n620), .Y(n4850) );
NOR2X1TS U3208 ( .A(n2842), .B(n2845), .Y(n2848) );
NOR2X1TS U3209 ( .A(n5173), .B(n5177), .Y(n5160) );
INVX1TS U3210 ( .A(n5173), .Y(n5176) );
NOR2X1TS U3211 ( .A(n3731), .B(n4393), .Y(n3734) );
INVX1TS U3212 ( .A(n3379), .Y(n3340) );
NOR2X1TS U3213 ( .A(n620), .B(n4206), .Y(n4262) );
NAND2X4TS U3214 ( .A(n2575), .B(n982), .Y(n2576) );
INVX1TS U3215 ( .A(n5968), .Y(n5475) );
AND2X2TS U3216 ( .A(n3362), .B(n3360), .Y(n179) );
OAI21X1TS U3217 ( .A0(n9977), .A1(n11264), .B0(n11265), .Y(n9978) );
AOI2BB1X1TS U3218 ( .A0N(n9873), .A1N(n11446), .B0(n9872), .Y(n9874) );
AOI2BB1X1TS U3219 ( .A0N(n9873), .A1N(n9853), .B0(n9852), .Y(n9854) );
XOR2X1TS U3220 ( .A(n9715), .B(n9714), .Y(n9982) );
INVX1TS U3221 ( .A(n9859), .Y(n9860) );
AOI2BB1X1TS U3222 ( .A0N(n9873), .A1N(n11445), .B0(n9863), .Y(n9864) );
INVX1TS U3223 ( .A(n9873), .Y(n9893) );
NAND2XLTS U3224 ( .A(n10274), .B(n11604), .Y(n10163) );
NOR2X1TS U3225 ( .A(n9735), .B(n11350), .Y(n9879) );
NAND2XLTS U3226 ( .A(n10276), .B(n11604), .Y(n10162) );
XOR2X1TS U3227 ( .A(n9974), .B(n11573), .Y(n10747) );
NOR2X1TS U3228 ( .A(n9737), .B(n9736), .Y(n9882) );
XOR2X1TS U3229 ( .A(n9817), .B(n11341), .Y(n10914) );
XOR2X1TS U3230 ( .A(n10281), .B(n11572), .Y(n1703) );
NOR2X1TS U3231 ( .A(n9742), .B(n9741), .Y(n9830) );
INVX1TS U3232 ( .A(n10275), .Y(n10145) );
NAND2XLTS U3233 ( .A(n10276), .B(n11595), .Y(n10146) );
INVX1TS U3234 ( .A(n9754), .Y(n9752) );
NAND2XLTS U3235 ( .A(n10276), .B(n11598), .Y(n10138) );
INVX1TS U3236 ( .A(n9890), .Y(n9892) );
NAND2XLTS U3237 ( .A(n10274), .B(n11594), .Y(n10208) );
XOR2X1TS U3238 ( .A(n9727), .B(n11461), .Y(n9973) );
INVX1TS U3239 ( .A(n10093), .Y(n10095) );
NAND2XLTS U3240 ( .A(n10276), .B(n11594), .Y(n10207) );
NAND2XLTS U3241 ( .A(n10715), .B(n10569), .Y(n10570) );
NAND2XLTS U3242 ( .A(n10276), .B(n11609), .Y(n10218) );
INVX1TS U3243 ( .A(n10715), .Y(n10716) );
XOR2X1TS U3244 ( .A(n10006), .B(n10005), .Y(n10008) );
NAND2BX1TS U3245 ( .AN(n117), .B(n10817), .Y(n10818) );
INVX1TS U3246 ( .A(n10106), .Y(n10108) );
NAND2BX1TS U3247 ( .AN(n123), .B(n10819), .Y(n10820) );
INVX1TS U3248 ( .A(n10276), .Y(n10238) );
NAND2XLTS U3249 ( .A(n10274), .B(n11600), .Y(n10153) );
OR2X2TS U3250 ( .A(n243), .B(n6519), .Y(n1692) );
INVX4TS U3251 ( .A(n981), .Y(n2575) );
NOR2X1TS U3252 ( .A(n275), .B(n2486), .Y(n1337) );
ADDFX1TS U3253 ( .A(n291), .B(n312), .CI(n2723), .CO(n2782), .S(n2731) );
NAND2X1TS U3254 ( .A(n2706), .B(n2874), .Y(n2699) );
XOR2X1TS U3255 ( .A(n343), .B(n340), .Y(n1145) );
XOR2X1TS U3256 ( .A(n409), .B(Data_B_i[53]), .Y(n6882) );
NOR2X1TS U3257 ( .A(n320), .B(n5203), .Y(n3319) );
AND2X2TS U3258 ( .A(n3357), .B(n3356), .Y(n194) );
NAND2X2TS U3259 ( .A(n2262), .B(n2263), .Y(n2264) );
NAND2X1TS U3260 ( .A(n3725), .B(n4396), .Y(n3726) );
AND2X2TS U3261 ( .A(n3179), .B(n3178), .Y(n3180) );
INVX1TS U3262 ( .A(n4394), .Y(n3731) );
NOR2X1TS U3263 ( .A(n624), .B(n7734), .Y(n7775) );
NOR2X1TS U3264 ( .A(n623), .B(n6820), .Y(n7776) );
AND2X2TS U3265 ( .A(n3164), .B(n3163), .Y(n3165) );
XOR2X2TS U3266 ( .A(n4496), .B(n1564), .Y(n1563) );
INVX1TS U3267 ( .A(n4645), .Y(n4487) );
INVX1TS U3268 ( .A(n2894), .Y(n2895) );
AND2X2TS U3269 ( .A(n4394), .B(n4400), .Y(n225) );
NAND2BX1TS U3270 ( .AN(n4570), .B(n514), .Y(n4480) );
NAND2X1TS U3271 ( .A(n2249), .B(n2441), .Y(n2250) );
NAND2BX1TS U3272 ( .AN(n4600), .B(n336), .Y(n3863) );
NAND2BX1TS U3273 ( .AN(n276), .B(n279), .Y(n3864) );
NOR2X4TS U3274 ( .A(n1054), .B(n1053), .Y(n1052) );
INVX1TS U3275 ( .A(n2439), .Y(n2252) );
NOR2X1TS U3276 ( .A(Data_A_i[53]), .B(n298), .Y(n6898) );
AND2X2TS U3277 ( .A(n3371), .B(n3369), .Y(n1691) );
OAI21X2TS U3278 ( .A0(Data_B_i[24]), .A1(Data_B_i[10]), .B0(Data_B_i[9]),
.Y(n1312) );
XOR2X1TS U3279 ( .A(n11433), .B(n11408), .Y(n10032) );
OAI21X1TS U3280 ( .A0(n11413), .A1(n11414), .B0(n11415), .Y(n9728) );
XOR2X1TS U3281 ( .A(n11368), .B(n11345), .Y(n1698) );
NOR2X1TS U3282 ( .A(n11354), .B(n11355), .Y(n9859) );
XOR2X1TS U3283 ( .A(n11352), .B(n11353), .Y(n9742) );
NOR2X1TS U3284 ( .A(n11501), .B(n11502), .Y(n10821) );
NAND3X1TS U3285 ( .A(n11359), .B(n11360), .C(n11361), .Y(n9832) );
XOR2X1TS U3286 ( .A(n11272), .B(n11273), .Y(n9756) );
XOR2X1TS U3287 ( .A(n11267), .B(n11250), .Y(n9777) );
OAI21X1TS U3288 ( .A0(n11267), .A1(n11259), .B0(n11260), .Y(n9773) );
NAND2XLTS U3289 ( .A(n11428), .B(n11429), .Y(n9846) );
XOR2X1TS U3290 ( .A(n11574), .B(n11575), .Y(n10737) );
OAI21X1TS U3291 ( .A0(n11274), .A1(n11277), .B0(n11276), .Y(n9946) );
NAND2XLTS U3292 ( .A(n11428), .B(n11441), .Y(n9891) );
NAND2XLTS U3293 ( .A(n11200), .B(sgf_result_o[2]), .Y(n11196) );
NAND2XLTS U3294 ( .A(n11428), .B(n11430), .Y(n9838) );
NAND2XLTS U3295 ( .A(n11428), .B(n11422), .Y(n9813) );
NAND2XLTS U3296 ( .A(n11428), .B(n11432), .Y(n9818) );
OAI21X1TS U3297 ( .A0(n11624), .A1(n11623), .B0(n11581), .Y(n10137) );
NOR2X1TS U3298 ( .A(n11505), .B(n11507), .Y(n10715) );
XOR2X1TS U3299 ( .A(n11626), .B(n11622), .Y(n1694) );
XOR2X1TS U3300 ( .A(n11625), .B(n11621), .Y(n1699) );
OAI21X1TS U3301 ( .A0(n3355), .A1(n3388), .B0(n3356), .Y(n1730) );
INVX1TS U3302 ( .A(n3339), .Y(n3382) );
NAND2BX2TS U3303 ( .AN(n235), .B(n2196), .Y(n2262) );
INVX1TS U3304 ( .A(n3360), .Y(n3361) );
INVX1TS U3305 ( .A(n3381), .Y(n3341) );
INVX2TS U3306 ( .A(n3355), .Y(n3357) );
OR2X2TS U3307 ( .A(n4986), .B(n4985), .Y(n4987) );
OR2X2TS U3308 ( .A(n5178), .B(n7734), .Y(n5161) );
INVX1TS U3309 ( .A(n2442), .Y(n2257) );
INVX1TS U3310 ( .A(n3388), .Y(n3351) );
INVX1TS U3311 ( .A(n3369), .Y(n3370) );
INVX1TS U3312 ( .A(n3811), .Y(n3812) );
INVX2TS U3313 ( .A(n4666), .Y(n4649) );
NOR2X4TS U3314 ( .A(n2850), .B(n2845), .Y(n1090) );
OAI21X2TS U3315 ( .A0(n2850), .A1(n2844), .B0(n2851), .Y(n1088) );
INVX2TS U3316 ( .A(n4647), .Y(n4486) );
INVX2TS U3317 ( .A(n3739), .Y(n3741) );
INVX1TS U3318 ( .A(n2874), .Y(n2705) );
NOR2X1TS U3319 ( .A(n238), .B(n5223), .Y(n3083) );
INVX1TS U3320 ( .A(n712), .Y(n1070) );
INVX1TS U3321 ( .A(n2694), .Y(n2666) );
INVX1TS U3322 ( .A(n5157), .Y(n2528) );
INVX1TS U3323 ( .A(n3310), .Y(n3103) );
INVX1TS U3324 ( .A(n3089), .Y(n2878) );
INVX1TS U3325 ( .A(n5156), .Y(n2526) );
INVX1TS U3326 ( .A(n3094), .Y(n2954) );
INVX1TS U3327 ( .A(n2875), .Y(n2709) );
INVX1TS U3328 ( .A(n5177), .Y(n5179) );
INVX1TS U3329 ( .A(n5204), .Y(n1376) );
INVX1TS U3330 ( .A(n5168), .Y(n5170) );
INVX1TS U3331 ( .A(n5187), .Y(n5189) );
INVX4TS U3332 ( .A(n406), .Y(n407) );
INVX4TS U3333 ( .A(Data_B_i[50]), .Y(n5474) );
NOR2X1TS U3334 ( .A(Data_A_i[49]), .B(Data_A_i[22]), .Y(n3310) );
NOR2X1TS U3335 ( .A(Data_B_i[19]), .B(Data_B_i[46]), .Y(n2867) );
NOR2X1TS U3336 ( .A(Data_A_i[45]), .B(Data_A_i[18]), .Y(n2872) );
OR2X2TS U3337 ( .A(Data_B_i[27]), .B(Data_B_i[0]), .Y(n2603) );
NOR2X1TS U3338 ( .A(Data_A_i[51]), .B(Data_A_i[24]), .Y(n6890) );
NAND2X1TS U3339 ( .A(n2554), .B(n5811), .Y(n2561) );
AND2X4TS U3340 ( .A(n5686), .B(n2268), .Y(n5684) );
OAI22X2TS U3341 ( .A0(n7105), .A1(n3491), .B0(n3417), .B1(n7104), .Y(n3489)
);
XOR2X2TS U3342 ( .A(n3483), .B(n1251), .Y(n1234) );
NAND2X4TS U3343 ( .A(n1599), .B(n7104), .Y(n7105) );
NOR2BX4TS U3344 ( .AN(n1261), .B(n2553), .Y(n5812) );
CLKINVX6TS U3345 ( .A(n1669), .Y(n6728) );
ADDFHX2TS U3346 ( .A(n6697), .B(n6696), .CI(n6695), .CO(n6748), .S(n5977) );
XOR2X2TS U3347 ( .A(n1999), .B(n1998), .Y(n151) );
XOR2X2TS U3348 ( .A(n1997), .B(n151), .Y(n2000) );
NAND2X1TS U3349 ( .A(n1998), .B(n1997), .Y(n153) );
NAND2X1TS U3350 ( .A(n1998), .B(n1999), .Y(n154) );
NAND3X2TS U3351 ( .A(n153), .B(n152), .C(n154), .Y(n2130) );
OAI21X1TS U3352 ( .A0(n2001), .A1(n2002), .B0(n2000), .Y(n1228) );
ADDFHX2TS U3353 ( .A(n7142), .B(n7141), .CI(n7140), .CO(n7174), .S(n7178) );
OAI21X4TS U3354 ( .A0(n1272), .A1(n5812), .B0(n5811), .Y(n7190) );
OAI21X2TS U3355 ( .A0(n8643), .A1(n1157), .B0(n8642), .Y(n1155) );
NAND2BX4TS U3356 ( .AN(n8769), .B(n8770), .Y(n7880) );
OAI22X2TS U3357 ( .A0(n3088), .A1(n8244), .B0(n3230), .B1(n8243), .Y(n3237)
);
OAI21X1TS U3358 ( .A0(n9449), .A1(n6677), .B0(n1624), .Y(n986) );
AOI21X2TS U3359 ( .A0(n6679), .A1(n9452), .B0(n986), .Y(n985) );
XOR2X2TS U3360 ( .A(n864), .B(n1276), .Y(n4538) );
AOI21X2TS U3361 ( .A0(n4939), .A1(n1273), .B0(n4938), .Y(n4940) );
XNOR2X1TS U3362 ( .A(n262), .B(n288), .Y(n3975) );
AOI21X2TS U3363 ( .A0(add_x_2_n184), .A1(n136), .B0(n9552), .Y(add_x_2_n179)
);
NAND2X4TS U3364 ( .A(n8531), .B(n8532), .Y(n1638) );
OAI22X2TS U3365 ( .A0(n3399), .A1(n390), .B0(n3438), .B1(n354), .Y(n3413) );
OAI21X1TS U3366 ( .A0(n3780), .A1(n3781), .B0(n3779), .Y(n1440) );
CLKBUFX2TS U3367 ( .A(n8203), .Y(n155) );
CLKINVX6TS U3368 ( .A(n9652), .Y(n8203) );
AND2X4TS U3369 ( .A(n3685), .B(n2906), .Y(n156) );
XNOR2X4TS U3370 ( .A(n783), .B(n7261), .Y(EVEN1_Q_left[21]) );
XNOR2X1TS U3371 ( .A(n5532), .B(n384), .Y(n2191) );
XOR2X1TS U3372 ( .A(n2239), .B(n2238), .Y(n2240) );
AOI21X4TS U3373 ( .A0(n9665), .A1(n137), .B0(n8528), .Y(n157) );
AOI21X1TS U3374 ( .A0(n9665), .A1(n137), .B0(n8528), .Y(n9669) );
OAI21X2TS U3375 ( .A0(n3732), .A1(n4393), .B0(n4396), .Y(n3733) );
OAI22X2TS U3376 ( .A0(n6492), .A1(n4969), .B0(n597), .B1(n5052), .Y(n5048)
);
OAI21X4TS U3377 ( .A0(n157), .A1(n9661), .B0(n9663), .Y(n8530) );
OAI22X2TS U3378 ( .A0(n5704), .A1(n585), .B0(n5557), .B1(n503), .Y(n5700) );
OAI21X2TS U3379 ( .A0(n8616), .A1(n8615), .B0(n8614), .Y(n1101) );
XOR2X2TS U3380 ( .A(n6475), .B(n6476), .Y(n1629) );
OAI2BB1X1TS U3381 ( .A0N(n3218), .A1N(n1149), .B0(n1147), .Y(n3278) );
XNOR2X1TS U3382 ( .A(n241), .B(Data_A_i[7]), .Y(n4098) );
OAI2BB1X1TS U3383 ( .A0N(n3300), .A1N(n3299), .B0(n1536), .Y(n3564) );
OAI21XLTS U3384 ( .A0(n3299), .A1(n3300), .B0(n3298), .Y(n1536) );
OAI21X1TS U3385 ( .A0(n5752), .A1(n5753), .B0(n5751), .Y(n784) );
ADDFHX2TS U3386 ( .A(n4147), .B(n4146), .CI(n4145), .CO(n4168), .S(n4176) );
OAI22X2TS U3387 ( .A0(n348), .A1(n3865), .B0(n3796), .B1(n542), .Y(n3809) );
ADDFHX2TS U3388 ( .A(n7557), .B(n7556), .CI(n7555), .CO(n7600), .S(n7602) );
ADDFHX2TS U3389 ( .A(n4037), .B(n4036), .CI(n4035), .CO(n4212), .S(n4033) );
OAI22X2TS U3390 ( .A0(n4764), .A1(n3984), .B0(n574), .B1(n3974), .Y(n3996)
);
OAI2BB1X2TS U3391 ( .A0N(n3499), .A1N(n1233), .B0(n1231), .Y(n7412) );
OAI21X1TS U3392 ( .A0(n3499), .A1(n1233), .B0(n3498), .Y(n1231) );
ADDFHX2TS U3393 ( .A(n3976), .B(n3977), .CI(n252), .CO(n4042), .S(n4024) );
OAI21X1TS U3394 ( .A0(n1082), .A1(n1081), .B0(n3170), .Y(n3273) );
OAI22X2TS U3395 ( .A0(n140), .A1(n3719), .B0(n7086), .B1(n540), .Y(n7083) );
NOR2X2TS U3396 ( .A(n6012), .B(n6014), .Y(n6694) );
OAI21X2TS U3397 ( .A0(n1095), .A1(n7839), .B0(n7838), .Y(n1094) );
INVX4TS U3398 ( .A(n2752), .Y(n2849) );
XNOR2X1TS U3399 ( .A(n2839), .B(n2798), .Y(n2802) );
OAI22X1TS U3400 ( .A0(n413), .A1(n3192), .B0(n614), .B1(n3275), .Y(n3301) );
XNOR2X1TS U3401 ( .A(n6370), .B(n4502), .Y(n6120) );
ADDFHX4TS U3402 ( .A(n8360), .B(n8359), .CI(n8358), .CO(n8364), .S(n8361) );
INVX2TS U3403 ( .A(n8896), .Y(n3039) );
XOR2X1TS U3404 ( .A(n7470), .B(n388), .Y(n3230) );
ADDFHX2TS U3405 ( .A(n8351), .B(n8350), .CI(n8349), .CO(n8355), .S(n8334) );
OAI21X2TS U3406 ( .A0(n7255), .A1(n7258), .B0(n7256), .Y(n2405) );
OAI22X2TS U3407 ( .A0(n584), .A1(n2190), .B0(n2205), .B1(n503), .Y(n2213) );
ADDFHX4TS U3408 ( .A(n5899), .B(n5898), .CI(n5897), .CO(n5881), .S(n5914) );
NAND2X2TS U3409 ( .A(n4417), .B(n4418), .Y(n4453) );
NOR2X4TS U3410 ( .A(n3886), .B(n3887), .Y(n4452) );
OAI21X1TS U3411 ( .A0(n4368), .A1(n4452), .B0(n4454), .Y(n1195) );
ADDFHX2TS U3412 ( .A(n8285), .B(n8284), .CI(n8283), .CO(n8281), .S(n8581) );
OAI21X2TS U3413 ( .A0(n5027), .A1(n5028), .B0(n5026), .Y(n1297) );
OAI21X1TS U3414 ( .A0(n4506), .A1(n4507), .B0(n4505), .Y(n1208) );
OAI2BB1X2TS U3415 ( .A0N(n4507), .A1N(n4506), .B0(n1208), .Y(n6650) );
OAI21X2TS U3416 ( .A0(n6115), .A1(n6116), .B0(n6114), .Y(n1650) );
NOR2BX2TS U3417 ( .AN(n276), .B(n574), .Y(n4150) );
INVX2TS U3418 ( .A(n3385), .Y(n3352) );
OAI21X2TS U3419 ( .A0(n3387), .A1(n3386), .B0(n3385), .Y(n3391) );
XNOR2X1TS U3420 ( .A(n6437), .B(n451), .Y(n6137) );
INVX4TS U3421 ( .A(n1218), .Y(n597) );
NAND2X4TS U3422 ( .A(n1362), .B(n1361), .Y(n8502) );
OAI2BB1X2TS U3423 ( .A0N(n1794), .A1N(n1793), .B0(n1571), .Y(n5659) );
OAI21X2TS U3424 ( .A0(n7818), .A1(n7819), .B0(n7817), .Y(n1527) );
OAI22X1TS U3425 ( .A0(n422), .A1(n7778), .B0(n491), .B1(n5527), .Y(n5654) );
NAND2BX1TS U3426 ( .AN(n629), .B(n403), .Y(n5527) );
INVX2TS U3427 ( .A(n421), .Y(n422) );
OAI21X2TS U3428 ( .A0(n8742), .A1(n8743), .B0(n8741), .Y(n1608) );
ADDFHX4TS U3429 ( .A(n8336), .B(n8335), .CI(n8334), .CO(n8734), .S(n8741) );
OAI21X1TS U3430 ( .A0(Data_B_i[43]), .A1(Data_B_i[16]), .B0(n254), .Y(n2652)
);
INVX2TS U3431 ( .A(n7768), .Y(n7722) );
ADDFHX2TS U3432 ( .A(n6710), .B(n6709), .CI(n6708), .CO(n6779), .S(n6714) );
OAI21X4TS U3433 ( .A0(n7178), .A1(n7179), .B0(n7177), .Y(n1528) );
XNOR2X1TS U3434 ( .A(n6370), .B(n4582), .Y(n6134) );
OR2X2TS U3435 ( .A(n6549), .B(n4661), .Y(n216) );
XNOR2X1TS U3436 ( .A(n6050), .B(n4582), .Y(n4982) );
INVX2TS U3437 ( .A(n6409), .Y(n6445) );
NAND2X1TS U3438 ( .A(n8219), .B(n8218), .Y(n9509) );
OAI22X2TS U3439 ( .A0(n2453), .A1(n1316), .B0(n579), .B1(n2271), .Y(n1318)
);
OAI21X1TS U3440 ( .A0(n777), .A1(n3899), .B0(n3898), .Y(n776) );
NAND2X2TS U3441 ( .A(n1186), .B(n6162), .Y(n6164) );
XOR2X1TS U3442 ( .A(n1187), .B(n3804), .Y(n1186) );
XNOR2X2TS U3443 ( .A(n660), .B(n5902), .Y(n5920) );
OAI22X2TS U3444 ( .A0(n2485), .A1(n1990), .B0(n603), .B1(n2123), .Y(n2125)
);
XNOR2X1TS U3445 ( .A(n7470), .B(n362), .Y(n7441) );
INVX4TS U3446 ( .A(n160), .Y(n161) );
NOR2X4TS U3447 ( .A(n8542), .B(n8371), .Y(n6613) );
XNOR2X1TS U3448 ( .A(n402), .B(n628), .Y(n5529) );
NOR2X4TS U3449 ( .A(n8066), .B(n8473), .Y(n1266) );
OAI21X1TS U3450 ( .A0(n5803), .A1(n5802), .B0(n5801), .Y(n1262) );
NAND2BX4TS U3451 ( .AN(n1550), .B(n3766), .Y(n586) );
XOR2X4TS U3452 ( .A(n158), .B(n3763), .Y(n1550) );
NAND2BX2TS U3453 ( .AN(n4687), .B(n4705), .Y(n9161) );
XOR2X1TS U3454 ( .A(n9292), .B(n9291), .Y(n11225) );
ADDFHX2TS U3455 ( .A(n7176), .B(n7175), .CI(n7174), .CO(n7183), .S(n7181) );
OAI22X2TS U3456 ( .A0(n7488), .A1(n552), .B0(n8240), .B1(n8237), .Y(n8287)
);
XOR2X4TS U3457 ( .A(n1373), .B(n1372), .Y(n5722) );
XOR2X1TS U3458 ( .A(n6921), .B(n389), .Y(n3325) );
NAND2X4TS U3459 ( .A(n4473), .B(n6415), .Y(n6416) );
OAI22X2TS U3460 ( .A0(n6416), .A1(n4474), .B0(n6415), .B1(n4559), .Y(n4561)
);
ADDFHX4TS U3461 ( .A(n7102), .B(n7101), .CI(n7100), .CO(n7177), .S(n8363) );
OAI22X2TS U3462 ( .A0(n140), .A1(n3697), .B0(n3719), .B1(n539), .Y(n3711) );
NAND2X2TS U3463 ( .A(n1164), .B(n1163), .Y(n6853) );
NAND2X4TS U3464 ( .A(Data_B_i[0]), .B(Data_B_i[27]), .Y(n2602) );
NAND2BX1TS U3465 ( .AN(n1550), .B(n3766), .Y(n6410) );
ADDFHX4TS U3466 ( .A(n6149), .B(n6148), .CI(n6147), .CO(n6159), .S(n6126) );
XNOR2X1TS U3467 ( .A(n286), .B(n253), .Y(n4142) );
NAND2BX1TS U3468 ( .AN(n4096), .B(n253), .Y(n3912) );
INVX4TS U3469 ( .A(n252), .Y(n253) );
OR2X4TS U3470 ( .A(n1315), .B(n2242), .Y(n159) );
NAND2X2TS U3471 ( .A(n8511), .B(n8510), .Y(n8512) );
NOR2X4TS U3472 ( .A(n2592), .B(n2586), .Y(n2894) );
OR2X4TS U3473 ( .A(n2241), .B(n2240), .Y(n7684) );
XNOR2X2TS U3474 ( .A(n6558), .B(n396), .Y(n5071) );
CLKINVX6TS U3475 ( .A(n6599), .Y(n6558) );
ADDFHX2TS U3476 ( .A(n2306), .B(n2305), .CI(n2304), .CO(n2325), .S(n2321) );
CLKINVX1TS U3477 ( .A(n8509), .Y(n8510) );
AOI21X2TS U3478 ( .A0(n2740), .A1(n2607), .B0(n2606), .Y(n2608) );
ADDFHX2TS U3479 ( .A(n5396), .B(n5397), .CI(n5395), .CO(n5398), .S(n5852) );
AOI21X2TS U3480 ( .A0(n1076), .A1(n1077), .B0(n1075), .Y(n1074) );
NOR2X4TS U3481 ( .A(Data_A_i[16]), .B(Data_A_i[2]), .Y(n3751) );
ADDFHX2TS U3482 ( .A(n6043), .B(n6042), .CI(n6041), .CO(n6148), .S(n6036) );
XNOR2X2TS U3483 ( .A(n5675), .B(n5677), .Y(n1373) );
NOR2X4TS U3484 ( .A(Data_A_i[32]), .B(Data_A_i[5]), .Y(n2773) );
ADDFHX2TS U3485 ( .A(n6542), .B(n6541), .CI(n6540), .CO(n6621), .S(n6616) );
OAI21X1TS U3486 ( .A0(n4758), .A1(n4757), .B0(n4756), .Y(n1636) );
XNOR2X4TS U3487 ( .A(n5904), .B(n5903), .Y(n660) );
INVX4TS U3488 ( .A(n5993), .Y(n2296) );
OAI22X2TS U3489 ( .A0(n244), .A1(n3986), .B0(n4881), .B1(n3993), .Y(n3976)
);
OAI22X1TS U3490 ( .A0(n244), .A1(n3983), .B0(n4881), .B1(n3987), .Y(n4054)
);
OAI21X4TS U3491 ( .A0(n2717), .A1(n2725), .B0(n2718), .Y(n1079) );
XNOR2X1TS U3492 ( .A(n6050), .B(n382), .Y(n4406) );
XOR2X1TS U3493 ( .A(n3780), .B(n3781), .Y(n1441) );
OAI22X2TS U3494 ( .A0(n4764), .A1(n4073), .B0(n575), .B1(n4072), .Y(n4160)
);
NOR2X2TS U3495 ( .A(n2903), .B(n2898), .Y(n1595) );
ADDFHX2TS U3496 ( .A(n8463), .B(n8462), .CI(n8461), .CO(n8864), .S(n8466) );
XOR2X2TS U3497 ( .A(n7148), .B(n678), .Y(n7152) );
ADDFHX2TS U3498 ( .A(n2477), .B(n2478), .CI(n2476), .CO(n5468), .S(n5412) );
XNOR2X1TS U3499 ( .A(n616), .B(n747), .Y(n3415) );
OAI21X2TS U3500 ( .A0(n5580), .A1(n5583), .B0(n1368), .Y(n5589) );
NAND2X4TS U3501 ( .A(n5581), .B(n1369), .Y(n5583) );
NOR2X1TS U3502 ( .A(n6970), .B(n6969), .Y(n6972) );
NAND2BX2TS U3503 ( .AN(n7652), .B(n495), .Y(n818) );
NOR2X2TS U3504 ( .A(Data_A_i[15]), .B(Data_A_i[1]), .Y(n3770) );
INVX1TS U3505 ( .A(n3770), .Y(n3772) );
XNOR2X1TS U3506 ( .A(n6186), .B(n6052), .Y(n4407) );
XNOR2X1TS U3507 ( .A(n6186), .B(n435), .Y(n6133) );
OAI21X2TS U3508 ( .A0(n7511), .A1(n7512), .B0(n7510), .Y(n1610) );
OAI22X2TS U3509 ( .A0(n2302), .A1(n504), .B0(n2205), .B1(n585), .Y(n2310) );
OAI22X2TS U3510 ( .A0(n2424), .A1(n585), .B0(n2501), .B1(n504), .Y(n2506) );
NAND2X4TS U3511 ( .A(n182), .B(n2256), .Y(n664) );
AND2X2TS U3512 ( .A(n2439), .B(n2445), .Y(n182) );
ADDFHX4TS U3513 ( .A(n5310), .B(n5309), .CI(n5308), .CO(n5394), .S(n5344) );
ADDFHX2TS U3514 ( .A(n3576), .B(n3575), .CI(n3574), .CO(n3522), .S(n3585) );
NAND2X4TS U3515 ( .A(Data_B_i[31]), .B(Data_B_i[4]), .Y(n2590) );
OAI21X2TS U3516 ( .A0(n3387), .A1(n3161), .B0(n3160), .Y(n1526) );
OAI21X2TS U3517 ( .A0(n3387), .A1(n3374), .B0(n3373), .Y(n3378) );
XOR2X2TS U3518 ( .A(n878), .B(n4075), .Y(n4189) );
XOR2X1TS U3519 ( .A(n4292), .B(n4291), .Y(n4364) );
NAND2X2TS U3520 ( .A(n5849), .B(n5848), .Y(n8011) );
OAI22X2TS U3521 ( .A0(n243), .A1(n4970), .B0(n534), .B1(n5039), .Y(n6073) );
OAI2BB1X2TS U3522 ( .A0N(n8595), .A1N(n8596), .B0(n1521), .Y(n8698) );
AOI21X1TS U3523 ( .A0(n3283), .A1(n3117), .B0(n3116), .Y(n3125) );
NAND2X1TS U3524 ( .A(n3117), .B(n3201), .Y(n2926) );
OA21X4TS U3525 ( .A0(n2232), .A1(n7683), .B0(n6690), .Y(n2243) );
OAI22X1TS U3526 ( .A0(n532), .A1(n3784), .B0(n3795), .B1(n5041), .Y(n1292)
);
NAND2BX2TS U3527 ( .AN(n3782), .B(n1172), .Y(n1294) );
XOR2X1TS U3528 ( .A(n6921), .B(n381), .Y(n6904) );
OAI22X2TS U3529 ( .A0(n6304), .A1(n3840), .B0(n604), .B1(n4385), .Y(n4387)
);
INVX4TS U3530 ( .A(n329), .Y(n239) );
XNOR2X1TS U3531 ( .A(n7467), .B(n395), .Y(n7546) );
OAI22X2TS U3532 ( .A0(n549), .A1(n3847), .B0(n1389), .B1(n4089), .Y(n4103)
);
XNOR2X4TS U3533 ( .A(n808), .B(n618), .Y(n3410) );
ADDFHX2TS U3534 ( .A(n9206), .B(n9205), .CI(n9204), .CO(n9248), .S(n9246) );
XOR2X1TS U3535 ( .A(n5098), .B(n5101), .Y(n11197) );
XOR2X4TS U3536 ( .A(n1552), .B(n4022), .Y(n4047) );
AOI21X4TS U3537 ( .A0(n2560), .A1(n2559), .B0(n2558), .Y(n1272) );
ADDFHX2TS U3538 ( .A(n2935), .B(n2934), .CI(n2933), .CO(n3081), .S(n2915) );
NOR2X1TS U3539 ( .A(n2690), .B(n2694), .Y(n2697) );
NAND2X2TS U3540 ( .A(n2691), .B(n2697), .Y(n3091) );
OAI22X2TS U3541 ( .A0(n3318), .A1(n7558), .B0(n3235), .B1(n7560), .Y(n3308)
);
OAI22X2TS U3542 ( .A0(n6166), .A1(n586), .B0(n6049), .B1(n472), .Y(n6172) );
XOR2X4TS U3543 ( .A(n648), .B(n8363), .Y(n8492) );
ADDFHX2TS U3544 ( .A(n6146), .B(n6145), .CI(n6144), .CO(n6160), .S(n6128) );
NOR2X6TS U3545 ( .A(n5925), .B(n5926), .Y(n8503) );
OAI2BB1X2TS U3546 ( .A0N(n5901), .A1N(n5914), .B0(n5900), .Y(n5925) );
NAND2BX1TS U3547 ( .AN(n5912), .B(n5911), .Y(n5901) );
XOR2X4TS U3548 ( .A(n920), .B(n6308), .Y(n919) );
XOR2X2TS U3549 ( .A(n6310), .B(n6311), .Y(n920) );
INVX4TS U3550 ( .A(n199), .Y(n430) );
XOR2X4TS U3551 ( .A(n2757), .B(n2756), .Y(n199) );
INVX2TS U3552 ( .A(n513), .Y(n514) );
ADDFHX2TS U3553 ( .A(n8734), .B(n8733), .CI(n8732), .CO(n8745), .S(n8755) );
OAI22X2TS U3554 ( .A0(n6907), .A1(n458), .B0(n6950), .B1(n554), .Y(n6952) );
XNOR2X2TS U3555 ( .A(Data_B_i[5]), .B(Data_B_i[19]), .Y(n3761) );
ADDFHX2TS U3556 ( .A(n8449), .B(n8448), .CI(n8447), .CO(n8854), .S(n8465) );
OAI22X1TS U3557 ( .A0(n7428), .A1(n135), .B0(n7473), .B1(n8426), .Y(n7477)
);
ADDFHX2TS U3558 ( .A(n4643), .B(n4642), .CI(n4641), .CO(n4837), .S(n4698) );
OAI22X2TS U3559 ( .A0(n4823), .A1(n4384), .B0(n4479), .B1(n3728), .Y(n4483)
);
INVX2TS U3560 ( .A(n6648), .Y(n4464) );
XNOR2X1TS U3561 ( .A(n241), .B(Data_A_i[3]), .Y(n3865) );
INVX2TS U3562 ( .A(n4105), .Y(n160) );
NAND2X2TS U3563 ( .A(n8529), .B(n894), .Y(n9663) );
ADDFHX2TS U3564 ( .A(n5960), .B(n5959), .CI(n5958), .CO(n6699), .S(n5943) );
OAI21X2TS U3565 ( .A0(n4175), .A1(n4176), .B0(n4174), .Y(n914) );
XOR2X4TS U3566 ( .A(n745), .B(n5444), .Y(n5931) );
OAI21X1TS U3567 ( .A0(n5998), .A1(n6019), .B0(n5997), .Y(n6011) );
NOR2X1TS U3568 ( .A(n9672), .B(n1696), .Y(add_x_2_n70) );
XOR2X1TS U3569 ( .A(n9600), .B(n9599), .Y(n9659) );
NOR2X4TS U3570 ( .A(n8753), .B(n8752), .Y(n9058) );
ADDFHX4TS U3571 ( .A(n8708), .B(n8707), .CI(n8706), .CO(n8758), .S(n8681) );
AOI21X2TS U3572 ( .A0(n3814), .A1(n4394), .B0(n4399), .Y(n3727) );
OAI22X2TS U3573 ( .A0(n6167), .A1(n587), .B0(n6166), .B1(n472), .Y(n6180) );
NAND3X1TS U3574 ( .A(n166), .B(n165), .C(n167), .Y(n2547) );
XOR2X4TS U3575 ( .A(n9544), .B(n9543), .Y(EVEN1_Q_left[31]) );
AOI21X4TS U3576 ( .A0(n9540), .A1(n9539), .B0(n9538), .Y(n9544) );
NOR2X2TS U3577 ( .A(n2620), .B(n2618), .Y(n1423) );
AO21X2TS U3578 ( .A0(n9434), .A1(n3707), .B0(n3706), .Y(n3724) );
XOR2X2TS U3579 ( .A(n9540), .B(n8105), .Y(n1720) );
NOR2X4TS U3580 ( .A(n1281), .B(n1280), .Y(n1279) );
OAI22X2TS U3581 ( .A0(n372), .A1(n2911), .B0(n572), .B1(n3144), .Y(n3143) );
OAI22X2TS U3582 ( .A0(n4823), .A1(n3778), .B0(n3833), .B1(n3728), .Y(n3837)
);
INVX4TS U3583 ( .A(n418), .Y(n420) );
CLKINVX3TS U3584 ( .A(n6595), .Y(n418) );
ADDFHX2TS U3585 ( .A(n6061), .B(n6059), .CI(n6060), .CO(n6183), .S(n6171) );
XOR2X4TS U3586 ( .A(n2005), .B(n2004), .Y(n2099) );
AOI21X2TS U3587 ( .A0(n1976), .A1(n2090), .B0(n1975), .Y(n2005) );
XNOR2X4TS U3588 ( .A(n6692), .B(n6691), .Y(n7720) );
OAI22X1TS U3589 ( .A0(n348), .A1(n276), .B0(n3911), .B1(n542), .Y(n5099) );
ADDFHX2TS U3590 ( .A(n5024), .B(n3929), .CI(n3928), .CO(n3934), .S(n3936) );
OAI21X1TS U3591 ( .A0(n4331), .A1(n183), .B0(n4332), .Y(n4323) );
XNOR2X1TS U3592 ( .A(n253), .B(n4087), .Y(n3911) );
XNOR2X4TS U3593 ( .A(n4006), .B(n4007), .Y(n1023) );
XOR2X1TS U3594 ( .A(n1272), .B(n2561), .Y(n1400) );
NOR2X1TS U3595 ( .A(n2685), .B(n2193), .Y(n2194) );
XOR2X1TS U3596 ( .A(n3436), .B(n2645), .Y(n2646) );
XNOR2X2TS U3597 ( .A(Data_B_i[46]), .B(Data_B_i[32]), .Y(n2263) );
XNOR2X1TS U3598 ( .A(n2430), .B(n2433), .Y(n163) );
INVX2TS U3599 ( .A(n8795), .Y(n7822) );
NAND2X4TS U3600 ( .A(n8243), .B(n2661), .Y(n8244) );
XOR2X4TS U3601 ( .A(n2736), .B(n2735), .Y(n8308) );
INVX4TS U3602 ( .A(n517), .Y(n337) );
OAI2BB1X1TS U3603 ( .A0N(n7457), .A1N(n7456), .B0(n7426), .Y(n7493) );
ADDFHX2TS U3604 ( .A(n7597), .B(n7596), .CI(n7595), .CO(n7631), .S(n7677) );
OAI22X1TS U3605 ( .A0(n410), .A1(n7648), .B0(n613), .B1(n7592), .Y(n7641) );
INVX2TS U3606 ( .A(n184), .Y(n437) );
INVX6TS U3607 ( .A(n3566), .Y(n7858) );
NAND2X1TS U3608 ( .A(add_x_3_n5), .B(EVEN1_right_RECURSIVE_ODD1_Q_left_17_),
.Y(add_x_3_n106) );
ADDFHX4TS U3609 ( .A(n4715), .B(n4714), .CI(n4713), .CO(n4711), .S(n4737) );
NAND2X2TS U3610 ( .A(n4600), .B(n4096), .Y(n3773) );
OAI21X4TS U3611 ( .A0(n8509), .A1(n8504), .B0(n8511), .Y(n1613) );
XNOR2X4TS U3612 ( .A(n4576), .B(n4575), .Y(n4502) );
XNOR2X4TS U3613 ( .A(Data_B_i[9]), .B(Data_B_i[23]), .Y(n4576) );
OAI22X2TS U3614 ( .A0(n7105), .A1(n7103), .B0(n540), .B1(n3515), .Y(n1680)
);
OAI22X1TS U3615 ( .A0(n372), .A1(n3510), .B0(n3509), .B1(n572), .Y(n3555) );
NOR2X1TS U3616 ( .A(n9505), .B(n1715), .Y(add_x_3_n52) );
XOR2X1TS U3617 ( .A(n7335), .B(n7334), .Y(n9493) );
XOR2X2TS U3618 ( .A(n4383), .B(n4382), .Y(n760) );
OAI21X1TS U3619 ( .A0(n6677), .A1(n9449), .B0(n6676), .Y(n6678) );
OAI21X1TS U3620 ( .A0(n4989), .A1(n4988), .B0(n4987), .Y(n4990) );
CLKINVX1TS U3621 ( .A(n4989), .Y(n4674) );
XNOR2X1TS U3622 ( .A(n430), .B(n7591), .Y(n2983) );
INVX4TS U3623 ( .A(n8502), .Y(n8501) );
OAI21X1TS U3624 ( .A0(n9069), .A1(n9068), .B0(n9067), .Y(n1005) );
XNOR2X4TS U3625 ( .A(n9434), .B(n8152), .Y(n9068) );
XOR2X2TS U3626 ( .A(n2734), .B(n2733), .Y(n178) );
ADDFHX4TS U3627 ( .A(n7056), .B(n7057), .CI(n7058), .CO(n7059), .S(n7023) );
NOR2X1TS U3628 ( .A(n6890), .B(n6915), .Y(n6892) );
OAI22X1TS U3629 ( .A0(n469), .A1(n5030), .B0(n4982), .B1(n6549), .Y(n1395)
);
OAI2BB1X2TS U3630 ( .A0N(n5029), .A1N(n1393), .B0(n1392), .Y(n6119) );
OAI21X1TS U3631 ( .A0(n5029), .A1(n1393), .B0(n1395), .Y(n1392) );
ADDFHX2TS U3632 ( .A(n6119), .B(n6118), .CI(n6117), .CO(n6212), .S(n6215) );
ADDFHX2TS U3633 ( .A(n3807), .B(n3806), .CI(n3805), .CO(n6340), .S(n6339) );
NOR2X4TS U3634 ( .A(n5849), .B(n5848), .Y(n8010) );
OAI21X2TS U3635 ( .A0(n5762), .A1(n5763), .B0(n5761), .Y(n1501) );
ADDFHX4TS U3636 ( .A(n5680), .B(n5679), .CI(n5678), .CO(n5719), .S(n5763) );
NAND2BX4TS U3637 ( .AN(n895), .B(n5927), .Y(n8511) );
ADDFHX4TS U3638 ( .A(n5854), .B(n5853), .CI(n5852), .CO(n5929), .S(n5927) );
NAND2X4TS U3639 ( .A(n1007), .B(n4199), .Y(n697) );
NAND2X2TS U3640 ( .A(n1018), .B(n7272), .Y(n1017) );
ADDFHX2TS U3641 ( .A(n4562), .B(n4561), .CI(n4560), .CO(n4638), .S(n4623) );
ADDFHX4TS U3642 ( .A(n4700), .B(n4699), .CI(n4698), .CO(n4835), .S(n4724) );
ADDFHX2TS U3643 ( .A(n4109), .B(n4108), .CI(n4107), .CO(n4175), .S(n4110) );
ADDFHX2TS U3644 ( .A(n4864), .B(n4863), .CI(n4862), .CO(n4995), .S(n4867) );
OAI22X1TS U3645 ( .A0(n4154), .A1(n368), .B0(n4153), .B1(n599), .Y(n4163) );
XNOR2X1TS U3646 ( .A(n262), .B(n284), .Y(n4153) );
ADDFHX2TS U3647 ( .A(n7836), .B(n7835), .CI(n7834), .CO(n7845), .S(n7805) );
XOR2X1TS U3648 ( .A(n442), .B(n824), .Y(n3192) );
INVX2TS U3649 ( .A(n2841), .Y(n2842) );
OAI22X2TS U3650 ( .A0(n3440), .A1(n3474), .B0(n3400), .B1(n607), .Y(n3412)
);
OAI21X4TS U3651 ( .A0(n7634), .A1(n7633), .B0(n7632), .Y(n1591) );
INVX4TS U3652 ( .A(n228), .Y(n417) );
OAI22X1TS U3653 ( .A0(n586), .A1(n6293), .B0(n472), .B1(n3769), .Y(n4373) );
OAI22X2TS U3654 ( .A0(n6188), .A1(n590), .B0(n487), .B1(n6047), .Y(n6318) );
XNOR2X4TS U3655 ( .A(n1492), .B(n1491), .Y(n1490) );
NOR2X1TS U3656 ( .A(n2252), .B(n2438), .Y(n2255) );
AOI21X4TS U3657 ( .A0(n9635), .A1(n8520), .B0(n6013), .Y(n6018) );
ADDFHX2TS U3658 ( .A(n3832), .B(n3831), .CI(n3830), .CO(n6641), .S(n6332) );
NAND2X4TS U3659 ( .A(n4552), .B(n598), .Y(n357) );
OAI2BB1X2TS U3660 ( .A0N(n6489), .A1N(n6488), .B0(n1625), .Y(n6538) );
NOR2X2TS U3661 ( .A(n2106), .B(n2102), .Y(n1322) );
ADDFHX2TS U3662 ( .A(n4967), .B(n524), .CI(n2626), .CO(n2628), .S(n2627) );
XOR2X1TS U3663 ( .A(n7593), .B(n178), .Y(n2809) );
XNOR2X4TS U3664 ( .A(n1061), .B(n1067), .Y(n7593) );
OAI2BB1X2TS U3665 ( .A0N(n4867), .A1N(n4866), .B0(n1670), .Y(n4868) );
ADDFHX4TS U3666 ( .A(n8584), .B(n8583), .CI(n8582), .CO(n8832), .S(n8831) );
XNOR2X2TS U3667 ( .A(n7467), .B(n405), .Y(n7453) );
XNOR2X4TS U3668 ( .A(n2668), .B(n2667), .Y(n8241) );
XOR2X4TS U3669 ( .A(n5013), .B(n5014), .Y(n1597) );
XOR2X4TS U3670 ( .A(n6110), .B(n6109), .Y(n1221) );
XOR2X2TS U3671 ( .A(n1236), .B(n6285), .Y(n6324) );
NAND2X2TS U3672 ( .A(n8753), .B(n8752), .Y(DP_OP_59J6_122_190_n176) );
ADDFHX2TS U3673 ( .A(n8247), .B(n8246), .CI(n8245), .CO(n8271), .S(n8296) );
ADDFHX2TS U3674 ( .A(n6216), .B(n6215), .CI(n6214), .CO(n6239), .S(n6244) );
NAND2X2TS U3675 ( .A(n8182), .B(n8181), .Y(DP_OP_59J6_122_190_n223) );
OAI21X1TS U3676 ( .A0(n7897), .A1(n7898), .B0(n7896), .Y(n825) );
ADDFHX4TS U3677 ( .A(n7679), .B(n7678), .CI(n7677), .CO(n7882), .S(n7896) );
XNOR2X2TS U3678 ( .A(n3234), .B(n3233), .Y(n7547) );
NOR2X4TS U3679 ( .A(n7205), .B(n7204), .Y(n8473) );
XOR2X4TS U3680 ( .A(n662), .B(Data_B_i[31]), .Y(n2193) );
OAI21X4TS U3681 ( .A0(n2400), .A1(n2397), .B0(n2398), .Y(n2559) );
XOR2X2TS U3682 ( .A(n941), .B(n6245), .Y(n6248) );
OAI2BB1X2TS U3683 ( .A0N(n4067), .A1N(n4066), .B0(n1555), .Y(n4048) );
OAI21X2TS U3684 ( .A0(n4066), .A1(n4067), .B0(n4065), .Y(n1555) );
NOR2X4TS U3685 ( .A(n8380), .B(n9361), .Y(n1283) );
NOR2X4TS U3686 ( .A(n8380), .B(n9362), .Y(n1281) );
OAI21X1TS U3687 ( .A0(n5747), .A1(n5746), .B0(n5745), .Y(n803) );
OAI2BB1X1TS U3688 ( .A0N(n5746), .A1N(n5747), .B0(n803), .Y(n5762) );
OAI22X2TS U3689 ( .A0(n5769), .A1(n387), .B0(n5682), .B1(n445), .Y(n5749) );
XOR2X4TS U3690 ( .A(n6007), .B(n6006), .Y(n6026) );
NAND2X4TS U3691 ( .A(n1275), .B(n1274), .Y(n1273) );
ADDFHX2TS U3692 ( .A(n4388), .B(n4387), .CI(n4386), .CO(n4506), .S(n4374) );
NAND2X4TS U3693 ( .A(n3834), .B(n6303), .Y(n6304) );
XOR2X1TS U3694 ( .A(n2393), .B(n2392), .Y(n2403) );
NOR2X4TS U3695 ( .A(n2555), .B(n2557), .Y(n2560) );
OAI21X4TS U3696 ( .A0(n8066), .A1(n8474), .B0(n8065), .Y(n1265) );
NAND2X2TS U3697 ( .A(n7223), .B(n7222), .Y(n8065) );
XNOR2X1TS U3698 ( .A(n5688), .B(n428), .Y(n2501) );
ADDHX1TS U3699 ( .A(n4080), .B(n4079), .CO(n4183), .S(n4136) );
OAI21X1TS U3700 ( .A0(n9046), .A1(n9049), .B0(n9047), .Y(n8846) );
OAI21X1TS U3701 ( .A0(n9051), .A1(n9054), .B0(n9052), .Y(n8890) );
NOR2X2TS U3702 ( .A(n8905), .B(n8903), .Y(n7844) );
OAI21X2TS U3703 ( .A0(n8905), .A1(n8902), .B0(n8906), .Y(n7842) );
NAND2X2TS U3704 ( .A(n3336), .B(n3335), .Y(n8902) );
OAI22X2TS U3705 ( .A0(n2956), .A1(n7560), .B0(n3105), .B1(n7558), .Y(n3111)
);
ADDFHX4TS U3706 ( .A(n4049), .B(n4048), .CI(n4047), .CO(n6125), .S(n5056) );
NOR2X1TS U3707 ( .A(n4984), .B(n4988), .Y(n4991) );
OAI22X1TS U3708 ( .A0(n5041), .A1(n3839), .B0(n4389), .B1(n1290), .Y(n4388)
);
OAI21X2TS U3709 ( .A0(n3642), .A1(n3643), .B0(n3641), .Y(n1605) );
ADDFHX2TS U3710 ( .A(n3829), .B(n3828), .CI(n3827), .CO(n4381), .S(n3885) );
NOR2X4TS U3711 ( .A(n7942), .B(n7944), .Y(n7766) );
OR2X4TS U3712 ( .A(n1289), .B(n3783), .Y(n233) );
NOR2X2TS U3713 ( .A(n9062), .B(n9061), .Y(DP_OP_62J6_125_4796_n282) );
NOR2X4TS U3714 ( .A(n6277), .B(n6276), .Y(n9474) );
NAND2X2TS U3715 ( .A(n7841), .B(n7840), .Y(n8906) );
OAI21X2TS U3716 ( .A0(n2620), .A1(n2617), .B0(n2621), .Y(n1422) );
OAI22X2TS U3717 ( .A0(n4100), .A1(n858), .B0(n3848), .B1(n4209), .Y(n4102)
);
NAND2BX4TS U3718 ( .AN(n3152), .B(n1500), .Y(n8911) );
OAI22X2TS U3719 ( .A0(n7558), .A1(n2892), .B0(n2958), .B1(n7560), .Y(n2964)
);
NOR2X4TS U3720 ( .A(n4895), .B(n4913), .Y(n4753) );
INVX4TS U3721 ( .A(n8921), .Y(n8701) );
XNOR2X1TS U3722 ( .A(n7436), .B(n389), .Y(n3088) );
AOI21X1TS U3723 ( .A0(n2691), .A1(n2698), .B0(n2696), .Y(n2650) );
ADDHX1TS U3724 ( .A(n3413), .B(n3412), .CO(n3433), .S(n3487) );
ADDFHX2TS U3725 ( .A(n3432), .B(n3433), .CI(n3431), .CO(n3427), .S(n3496) );
OAI21X2TS U3726 ( .A0(n3387), .A1(n3262), .B0(n3261), .Y(n3264) );
NAND2X1TS U3727 ( .A(n7701), .B(n7700), .Y(n7703) );
INVX2TS U3728 ( .A(n6047), .Y(n382) );
OAI22X2TS U3729 ( .A0(n4406), .A1(n488), .B0(n3793), .B1(n590), .Y(n4410) );
XOR2X4TS U3730 ( .A(n4370), .B(n4371), .Y(n1278) );
NAND2X4TS U3731 ( .A(n7736), .B(n905), .Y(n7737) );
XOR2X2TS U3732 ( .A(n802), .B(n801), .Y(n9062) );
NAND2X1TS U3733 ( .A(n7253), .B(n7258), .Y(n7254) );
XOR2X2TS U3734 ( .A(n7480), .B(n7481), .Y(n1227) );
ADDFHX2TS U3735 ( .A(n7484), .B(n7483), .CI(n7482), .CO(n8593), .S(n7480) );
OAI21X2TS U3736 ( .A0(n3811), .A1(n3815), .B0(n3816), .Y(n4399) );
XNOR2X1TS U3737 ( .A(n6314), .B(n6052), .Y(n4461) );
OAI22X2TS U3738 ( .A0(n481), .A1(n3859), .B0(n3874), .B1(n592), .Y(n3869) );
AOI21X2TS U3739 ( .A0(n5937), .A1(n9635), .B0(n5936), .Y(n5981) );
NAND2X8TS U3740 ( .A(n1612), .B(n726), .Y(n9635) );
NOR2X1TS U3741 ( .A(n5481), .B(n6693), .Y(n5937) );
XOR2X4TS U3742 ( .A(n2416), .B(n2415), .Y(n164) );
ADDHX1TS U3743 ( .A(n4392), .B(n4391), .CO(n4476), .S(n4376) );
ADDFHX4TS U3744 ( .A(n3668), .B(n3667), .CI(n3666), .CO(n6985), .S(n6996) );
XOR2X1TS U3745 ( .A(n1393), .B(n5029), .Y(n682) );
XOR2X4TS U3746 ( .A(n3774), .B(n3773), .Y(n5068) );
XNOR2X4TS U3747 ( .A(n1300), .B(n6263), .Y(n5085) );
ADDFHX2TS U3748 ( .A(n4106), .B(n161), .CI(n4104), .CO(n4165), .S(n4111) );
NAND2X2TS U3749 ( .A(n6272), .B(n6273), .Y(n8113) );
OAI21X4TS U3750 ( .A0(n8112), .A1(n8109), .B0(n8113), .Y(n9470) );
OAI21X1TS U3751 ( .A0(n5079), .A1(n5080), .B0(n5078), .Y(n1639) );
ADDFHX4TS U3752 ( .A(n5037), .B(n5036), .CI(n5035), .CO(n6243), .S(n5078) );
ADDFHX2TS U3753 ( .A(n4057), .B(n4056), .CI(n4055), .CO(n4067), .S(n4085) );
XOR2X2TS U3754 ( .A(n8456), .B(n1602), .Y(n9397) );
XNOR2X4TS U3755 ( .A(n1356), .B(n1719), .Y(n9627) );
CLKINVX1TS U3756 ( .A(add_x_2_n122), .Y(add_x_2_n299) );
ADDFHX2TS U3757 ( .A(n5464), .B(n5463), .CI(n5462), .CO(n5975), .S(n5451) );
OAI21X2TS U3758 ( .A0(n5451), .A1(n5452), .B0(n5450), .Y(n1339) );
XNOR2X2TS U3759 ( .A(n1418), .B(n1417), .Y(DP_OP_62J6_125_4796_n696) );
XNOR2X4TS U3760 ( .A(n511), .B(Data_B_i[42]), .Y(n2030) );
NAND2X6TS U3761 ( .A(n1282), .B(n1279), .Y(n9540) );
OAI22X2TS U3762 ( .A0(n8310), .A1(n568), .B0(n485), .B1(n8307), .Y(n8625) );
XNOR2X2TS U3763 ( .A(n8227), .B(n431), .Y(n8310) );
NAND2X2TS U3764 ( .A(n7384), .B(n7383), .Y(n1019) );
XOR2X4TS U3765 ( .A(n6469), .B(n737), .Y(n717) );
ADDFHX2TS U3766 ( .A(n6958), .B(n6957), .CI(n6956), .CO(n8222), .S(n8270) );
OAI21X1TS U3767 ( .A0(n939), .A1(n8362), .B0(n8361), .Y(n937) );
NAND2X2TS U3768 ( .A(n9656), .B(n9655), .Y(n9630) );
XNOR2X2TS U3769 ( .A(n681), .B(n6666), .Y(n5063) );
ADDFHX4TS U3770 ( .A(n3427), .B(n3426), .CI(n3425), .CO(n3462), .S(n3480) );
NAND2X4TS U3771 ( .A(Data_A_i[4]), .B(Data_A_i[31]), .Y(n2770) );
XNOR2X2TS U3772 ( .A(n8423), .B(n3437), .Y(n3399) );
XNOR2X4TS U3773 ( .A(n6264), .B(n6265), .Y(n1300) );
OAI21X2TS U3774 ( .A0(n5070), .A1(n6594), .B0(n1394), .Y(n1393) );
OAI22X2TS U3775 ( .A0(n348), .A1(n3759), .B0(n3842), .B1(n543), .Y(n3845) );
ADDFHX2TS U3776 ( .A(n3846), .B(n3845), .CI(n3844), .CO(n4114), .S(n3779) );
NOR2X4TS U3777 ( .A(Data_A_i[24]), .B(Data_A_i[10]), .Y(n4666) );
NAND2X4TS U3778 ( .A(n360), .B(n2704), .Y(n352) );
NOR2X2TS U3779 ( .A(n8767), .B(n8766), .Y(DP_OP_59J6_122_190_n209) );
NOR2X2TS U3780 ( .A(n6964), .B(n6977), .Y(n1093) );
ADDFHX2TS U3781 ( .A(n294), .B(n314), .CI(n3717), .CO(n6976), .S(n6964) );
OAI21X4TS U3782 ( .A0(n4895), .A1(n4914), .B0(n4896), .Y(n4752) );
NAND2X4TS U3783 ( .A(n4749), .B(n4748), .Y(n4914) );
NAND2BXLTS U3784 ( .AN(n631), .B(n451), .Y(n4503) );
AOI21X2TS U3785 ( .A0(n9347), .A1(n9348), .B0(n9247), .Y(n9416) );
AOI21X4TS U3786 ( .A0(n9344), .A1(n9343), .B0(n9252), .Y(n9411) );
NOR2X1TS U3787 ( .A(n9246), .B(n9245), .Y(n9211) );
NOR2X1TS U3788 ( .A(n7689), .B(n7281), .Y(n3705) );
NOR2X2TS U3789 ( .A(n8224), .B(n6996), .Y(n7689) );
NOR2X4TS U3790 ( .A(n894), .B(n8529), .Y(n9661) );
XNOR2X2TS U3791 ( .A(n9635), .B(n8521), .Y(n894) );
XNOR2X4TS U3792 ( .A(n5186), .B(n2446), .Y(n5703) );
XOR2X4TS U3793 ( .A(n938), .B(n8361), .Y(n8744) );
NAND2BX2TS U3794 ( .AN(DP_OP_62J6_125_4796_n642), .B(n9545), .Y(add_x_1_n737) );
NAND2X2TS U3795 ( .A(n8408), .B(n1273), .Y(n4941) );
XNOR2X4TS U3796 ( .A(n1543), .B(n4594), .Y(n4863) );
XOR2X4TS U3797 ( .A(n4798), .B(n4799), .Y(n1543) );
ADDFHX2TS U3798 ( .A(n6816), .B(n6815), .CI(n6814), .CO(n7728), .S(n6838) );
OAI22X1TS U3799 ( .A0(n1751), .A1(n275), .B0(n6764), .B1(n518), .Y(n1807) );
OAI22X1TS U3800 ( .A0(n6764), .A1(n1771), .B0(n1818), .B1(n174), .Y(n1813)
);
XOR2X2TS U3801 ( .A(n6125), .B(n6221), .Y(n1562) );
AOI21X2TS U3802 ( .A0(n3814), .A1(n3734), .B0(n3733), .Y(n3737) );
OAI21X2TS U3803 ( .A0(n9471), .A1(n9474), .B0(n9475), .Y(n988) );
OAI2BB1X2TS U3804 ( .A0N(n4802), .A1N(n4801), .B0(n837), .Y(n6662) );
OAI2BB1X1TS U3805 ( .A0N(n6662), .A1N(n4803), .B0(n5011), .Y(n835) );
OAI21X1TS U3806 ( .A0(n4803), .A1(n6662), .B0(n835), .Y(n5062) );
XNOR2X2TS U3807 ( .A(Data_A_i[24]), .B(n242), .Y(n4556) );
NAND2X2TS U3808 ( .A(n3337), .B(n8902), .Y(n3338) );
OAI21X1TS U3809 ( .A0(n2846), .A1(n2845), .B0(n2844), .Y(n2847) );
CLKINVX1TS U3810 ( .A(n2843), .Y(n2846) );
ADDHX1TS U3811 ( .A(n3147), .B(n3146), .CO(n3183), .S(n3140) );
NAND2X2TS U3812 ( .A(n9549), .B(n9548), .Y(add_x_1_n732) );
NAND2X2TS U3813 ( .A(n4937), .B(n4936), .Y(n7372) );
AO21X4TS U3814 ( .A0(n868), .A1(n4269), .B0(n4268), .Y(n1012) );
NAND2X2TS U3815 ( .A(n8747), .B(n8746), .Y(n169) );
XNOR2X2TS U3816 ( .A(n1180), .B(n1179), .Y(n4937) );
XOR2X4TS U3817 ( .A(Data_B_i[20]), .B(Data_B_i[6]), .Y(n3764) );
NOR2X2TS U3818 ( .A(n8182), .B(n8181), .Y(DP_OP_59J6_122_190_n222) );
INVX2TS U3819 ( .A(n4737), .Y(n4738) );
NOR2X4TS U3820 ( .A(n4749), .B(n4748), .Y(n4913) );
XOR2X4TS U3821 ( .A(Data_B_i[22]), .B(Data_B_i[8]), .Y(n4496) );
XOR2X2TS U3822 ( .A(n6203), .B(n6202), .Y(n6204) );
OAI21X1TS U3823 ( .A0(n9449), .A1(n7908), .B0(n7907), .Y(n7909) );
OAI21X1TS U3824 ( .A0(n3958), .A1(n3957), .B0(n3956), .Y(n1191) );
NAND2X2TS U3825 ( .A(n233), .B(n1294), .Y(n1293) );
XOR2X4TS U3826 ( .A(n3750), .B(n3749), .Y(n6312) );
XOR2X4TS U3827 ( .A(n2885), .B(n756), .Y(n3535) );
XOR2X2TS U3828 ( .A(n2884), .B(n2883), .Y(n756) );
ADDHX1TS U3829 ( .A(n2835), .B(n2834), .CO(n2888), .S(n2884) );
OR2X4TS U3830 ( .A(n3946), .B(n3945), .Y(n207) );
INVX2TS U3831 ( .A(n4322), .Y(n3947) );
XOR2X4TS U3832 ( .A(n7818), .B(n7819), .Y(n1463) );
NAND2X2TS U3833 ( .A(n1729), .B(n3368), .Y(n3386) );
NOR2X2TS U3834 ( .A(n3263), .B(n3375), .Y(n1729) );
XOR2X1TS U3835 ( .A(n4861), .B(n4595), .Y(n892) );
CLKINVX1TS U3836 ( .A(n9549), .Y(DP_OP_62J6_125_4796_n641) );
AOI21X2TS U3837 ( .A0(n9486), .A1(n9504), .B0(n1647), .Y(n9510) );
AOI21X2TS U3838 ( .A0(n1173), .A1(n7981), .B0(n7980), .Y(n8120) );
NOR2X2TS U3839 ( .A(n9474), .B(n9472), .Y(n1678) );
OAI21X1TS U3840 ( .A0(n9632), .A1(n7723), .B0(n7722), .Y(n7724) );
XNOR2X4TS U3841 ( .A(n7002), .B(n6984), .Y(n8277) );
OAI21X2TS U3842 ( .A0(n8575), .A1(n412), .B0(n1166), .Y(n8595) );
ADDFHX2TS U3843 ( .A(n2993), .B(n2992), .CI(n2991), .CO(n2977), .S(n3017) );
OAI21X2TS U3844 ( .A0(n1068), .A1(n8915), .B0(n8916), .Y(n7843) );
NAND2X4TS U3845 ( .A(n1042), .B(n8111), .Y(n1305) );
OAI2BB1X2TS U3846 ( .A0N(n6259), .A1N(n6258), .B0(n1397), .Y(n6249) );
XNOR2X1TS U3847 ( .A(n5068), .B(n6557), .Y(n4981) );
XNOR2X4TS U3848 ( .A(n4977), .B(n620), .Y(n6557) );
XNOR2X4TS U3849 ( .A(n8535), .B(n7988), .Y(n9549) );
XOR2X4TS U3850 ( .A(n991), .B(n4723), .Y(n903) );
XNOR2X1TS U3851 ( .A(n6370), .B(n6052), .Y(n4619) );
XNOR2X4TS U3852 ( .A(n1051), .B(n6278), .Y(n6327) );
NOR2X2TS U3853 ( .A(n8493), .B(n8492), .Y(n9057) );
OAI22X2TS U3854 ( .A0(n8258), .A1(n462), .B0(n7473), .B1(n548), .Y(n8251) );
OAI21X4TS U3855 ( .A0(n8406), .A1(n4941), .B0(n4940), .Y(n1173) );
XOR2X4TS U3856 ( .A(n4577), .B(n231), .Y(n1204) );
NOR2X4TS U3857 ( .A(n9501), .B(n9468), .Y(add_x_3_n171) );
INVX2TS U3858 ( .A(n6174), .Y(n6199) );
OAI21X2TS U3859 ( .A0(n9652), .A1(n9667), .B0(n9653), .Y(add_x_2_n172) );
NAND2X2TS U3860 ( .A(n6731), .B(n2538), .Y(n6732) );
XOR2X2TS U3861 ( .A(n2452), .B(n2451), .Y(n6731) );
XOR2X2TS U3862 ( .A(n4694), .B(n4693), .Y(n995) );
NOR2X4TS U3863 ( .A(n6273), .B(n6272), .Y(n8112) );
ADDFHX2TS U3864 ( .A(n6131), .B(n6130), .CI(n6129), .CO(n6155), .S(n6221) );
ADDFHX2TS U3865 ( .A(n4013), .B(n4012), .CI(n4011), .CO(n4005), .S(n4066) );
ADDFHX2TS U3866 ( .A(n4083), .B(n4082), .CI(n4081), .CO(n4065), .S(n4181) );
CLKINVX1TS U3867 ( .A(n10695), .Y(n10771) );
XNOR2X4TS U3868 ( .A(n6279), .B(n6280), .Y(n1051) );
XOR2X4TS U3869 ( .A(n4490), .B(n4489), .Y(n6437) );
XOR2X2TS U3870 ( .A(n9456), .B(n9455), .Y(n1196) );
XOR2X2TS U3871 ( .A(n5016), .B(n5017), .Y(n732) );
XOR2X2TS U3872 ( .A(n1597), .B(n5012), .Y(n5017) );
ADDFHX2TS U3873 ( .A(n2567), .B(n2566), .CI(n2565), .CO(n5944), .S(n5470) );
XOR2X4TS U3874 ( .A(n6845), .B(n6844), .Y(n6852) );
AOI21X2TS U3875 ( .A0(n9635), .A1(n6810), .B0(n6809), .Y(n6845) );
NOR2X2TS U3876 ( .A(n6677), .B(n9448), .Y(n6679) );
XNOR2X2TS U3877 ( .A(n1199), .B(n4222), .Y(n6174) );
NOR2X1TS U3878 ( .A(n6174), .B(n6161), .Y(n4318) );
OAI21X1TS U3879 ( .A0(n1182), .A1(n893), .B0(n1181), .Y(n1180) );
AOI21X4TS U3880 ( .A0(n4894), .A1(n4753), .B0(n4752), .Y(n893) );
OAI22X1TS U3881 ( .A0(n2576), .A1(n1782), .B0(n2575), .B1(n1823), .Y(n1816)
);
XOR2X4TS U3882 ( .A(n9670), .B(n8566), .Y(EVEN1_Q_left[32]) );
AOI21X4TS U3883 ( .A0(n9538), .A1(n9542), .B0(n769), .Y(n1219) );
OAI21X4TS U3884 ( .A0(n9411), .A1(n9408), .B0(n9409), .Y(n9336) );
XNOR2X4TS U3885 ( .A(n689), .B(n9328), .Y(n9335) );
XNOR2X4TS U3886 ( .A(n9329), .B(n9330), .Y(n689) );
XNOR2X4TS U3887 ( .A(n1245), .B(n3347), .Y(n1217) );
OAI2BB1X2TS U3888 ( .A0N(n3343), .A1N(n1594), .B0(n3342), .Y(n1245) );
OAI21X1TS U3889 ( .A0(n5903), .A1(n5904), .B0(n5902), .Y(n1222) );
NOR2X4TS U3890 ( .A(n7906), .B(n7905), .Y(add_x_2_n166) );
XOR2X4TS U3891 ( .A(n5981), .B(n5980), .Y(n7906) );
XOR2X4TS U3892 ( .A(n1424), .B(n5882), .Y(n5926) );
XOR2X4TS U3893 ( .A(n5883), .B(n5881), .Y(n1424) );
XOR2X4TS U3894 ( .A(n9069), .B(n9068), .Y(n1006) );
NOR2X4TS U3895 ( .A(Data_A_i[33]), .B(Data_A_i[6]), .Y(n2845) );
ADDFHX2TS U3896 ( .A(n6262), .B(n6261), .CI(n6260), .CO(n6272), .S(n6271) );
XNOR2X4TS U3897 ( .A(n529), .B(n6330), .Y(n6345) );
NAND2X6TS U3898 ( .A(n987), .B(n989), .Y(n529) );
XNOR2X2TS U3899 ( .A(n7310), .B(n6182), .Y(n1049) );
XNOR2X2TS U3900 ( .A(n4899), .B(n4898), .Y(n4931) );
OAI21X2TS U3901 ( .A0(n4917), .A1(n4913), .B0(n4914), .Y(n4899) );
CMPR22X2TS U3902 ( .A(n3791), .B(n3790), .CO(n3780), .S(n3853) );
NOR2X2TS U3903 ( .A(n8108), .B(DP_OP_59J6_122_190_n135), .Y(
DP_OP_59J6_122_190_n111) );
NOR2X4TS U3904 ( .A(n7183), .B(n7184), .Y(n834) );
XOR2X4TS U3905 ( .A(n8746), .B(n168), .Y(n8753) );
XOR2X4TS U3906 ( .A(n8747), .B(n8748), .Y(n168) );
NAND2BX2TS U3907 ( .AN(n7724), .B(n976), .Y(n975) );
NAND2X2TS U3908 ( .A(n8128), .B(n8127), .Y(n9512) );
NOR2X2TS U3909 ( .A(n4393), .B(n4397), .Y(n4400) );
NOR2X4TS U3910 ( .A(n8500), .B(n8499), .Y(n8677) );
XOR2X4TS U3911 ( .A(n7915), .B(n7914), .Y(n8500) );
AOI21X2TS U3912 ( .A0(n7910), .A1(n529), .B0(n7909), .Y(n7915) );
XOR2X1TS U3913 ( .A(n9073), .B(n9074), .Y(n11309) );
XOR2X4TS U3914 ( .A(n8904), .B(n3338), .Y(n9073) );
XOR2X4TS U3915 ( .A(n7926), .B(n7925), .Y(n8498) );
XOR2X4TS U3916 ( .A(n925), .B(n924), .Y(n4976) );
OAI22X2TS U3917 ( .A0(n6048), .A1(n590), .B0(n6188), .B1(n488), .Y(n6191) );
ADDFHX2TS U3918 ( .A(n6192), .B(n6191), .CI(n6190), .CO(n6282), .S(n6156) );
XOR2X4TS U3919 ( .A(n985), .B(n1711), .Y(n8471) );
NAND2X4TS U3920 ( .A(n4552), .B(n598), .Y(n6492) );
XNOR2X4TS U3921 ( .A(n5026), .B(n1298), .Y(n6667) );
XNOR2X4TS U3922 ( .A(n5027), .B(n5028), .Y(n1298) );
NOR2X2TS U3923 ( .A(n8128), .B(n8127), .Y(n9513) );
OAI21X1TS U3924 ( .A0(n9948), .A1(n11279), .B0(n9947), .Y(n10112) );
XOR2X1TS U3925 ( .A(n2016), .B(n2166), .Y(n1421) );
INVX2TS U3926 ( .A(n5225), .Y(n255) );
NAND2X1TS U3927 ( .A(n1175), .B(n520), .Y(n4436) );
NAND2X4TS U3928 ( .A(n1073), .B(n1072), .Y(n1067) );
OAI2BB2X1TS U3929 ( .B0(n8855), .B1(n7409), .A0N(n138), .A1N(n7420), .Y(
n8314) );
INVX2TS U3930 ( .A(n8856), .Y(n8227) );
AO21XLTS U3931 ( .A0(n143), .A1(n275), .B0(n518), .Y(n6819) );
NOR2XLTS U3932 ( .A(n10105), .B(n10093), .Y(n10097) );
CLKAND2X2TS U3933 ( .A(n10660), .B(n10668), .Y(n10648) );
CLKAND2X2TS U3934 ( .A(n10776), .B(n10788), .Y(n10320) );
AOI21X2TS U3935 ( .A0(n8060), .A1(n2233), .B0(n2133), .Y(n2156) );
INVX2TS U3936 ( .A(n8610), .Y(n8630) );
NOR2XLTS U3937 ( .A(n9859), .B(n11376), .Y(n9734) );
AO21XLTS U3938 ( .A0(n10833), .A1(n10830), .B0(n9719), .Y(n10837) );
CLKAND2X2TS U3939 ( .A(n10831), .B(n10833), .Y(n10838) );
AOI2BB1XLTS U3940 ( .A0N(n9721), .A1N(n10840), .B0(n9720), .Y(n9722) );
AO21XLTS U3941 ( .A0(n10890), .A1(n10887), .B0(n10889), .Y(n10899) );
CLKAND2X2TS U3942 ( .A(n9952), .B(n11522), .Y(n10887) );
NAND2X4TS U3943 ( .A(n9360), .B(n1283), .Y(n1282) );
INVX2TS U3944 ( .A(n8381), .Y(n1280) );
OAI22X1TS U3945 ( .A0(n576), .A1(n424), .B0(n493), .B1(n5562), .Y(n5623) );
NOR2X1TS U3946 ( .A(n1172), .B(n3755), .Y(n3756) );
XNOR2X1TS U3947 ( .A(n448), .B(n628), .Y(n2542) );
INVX4TS U3948 ( .A(n5684), .Y(n579) );
ADDFHX2TS U3949 ( .A(n5212), .B(n5211), .CI(n5210), .CO(n5364), .S(n5332) );
XNOR2X1TS U3950 ( .A(n3635), .B(n618), .Y(n3138) );
INVX2TS U3951 ( .A(n6663), .Y(n4956) );
AOI21X2TS U3952 ( .A0(n1729), .A1(n3372), .B0(n1728), .Y(n3385) );
NAND2X1TS U3953 ( .A(n3362), .B(n3363), .Y(n1131) );
XOR2X1TS U3954 ( .A(n3629), .B(n1491), .Y(n2906) );
INVX2TS U3955 ( .A(n5659), .Y(n5863) );
INVX2TS U3956 ( .A(n7797), .Y(n5596) );
XNOR2X1TS U3957 ( .A(n429), .B(n5530), .Y(n2190) );
OAI22X1TS U3958 ( .A0(n6764), .A1(n1818), .B0(n1980), .B1(n275), .Y(n1327)
);
INVX2TS U3959 ( .A(n5995), .Y(n2418) );
XNOR2X1TS U3960 ( .A(n5151), .B(n5146), .Y(n5150) );
NAND2X1TS U3961 ( .A(n5205), .B(n5198), .Y(n5149) );
ADDFHX2TS U3962 ( .A(n3952), .B(n3951), .CI(n3950), .CO(n3969), .S(n3959) );
XNOR2X1TS U3963 ( .A(n778), .B(n3899), .Y(n3952) );
XOR2X1TS U3964 ( .A(n3898), .B(n6338), .Y(n778) );
NAND2BX1TS U3965 ( .AN(n4019), .B(n4071), .Y(n852) );
NAND2X1TS U3966 ( .A(n1178), .B(n881), .Y(n880) );
INVX2TS U3967 ( .A(n4070), .Y(n881) );
XNOR2X1TS U3968 ( .A(n523), .B(Data_B_i[52]), .Y(n6887) );
BUFX6TS U3969 ( .A(n1531), .Y(n754) );
NOR2X1TS U3970 ( .A(n3635), .B(n2857), .Y(n2798) );
XOR2XLTS U3971 ( .A(n273), .B(n2743), .Y(n2744) );
NAND2X1TS U3972 ( .A(n3273), .B(n3272), .Y(n3274) );
OAI21X2TS U3973 ( .A0(n1099), .A1(n2953), .B0(n2952), .Y(n1098) );
NOR2XLTS U3974 ( .A(n2941), .B(n2940), .Y(n2942) );
NAND2X2TS U3975 ( .A(n1595), .B(n2894), .Y(n1520) );
AOI21X2TS U3976 ( .A0(n2896), .A1(n1595), .B0(n1593), .Y(n1519) );
INVX2TS U3977 ( .A(n7647), .Y(n633) );
ADDFHX2TS U3978 ( .A(n5880), .B(n5879), .CI(n5878), .CO(n5894), .S(n5902) );
OAI22X1TS U3979 ( .A0(n143), .A1(n2578), .B0(n6712), .B1(n275), .Y(n6708) );
INVX2TS U3980 ( .A(n5988), .Y(n2175) );
INVX4TS U3981 ( .A(n525), .Y(n409) );
INVX2TS U3982 ( .A(n5324), .Y(n1345) );
AND2X2TS U3983 ( .A(n5543), .B(n5544), .Y(n5566) );
INVX2TS U3984 ( .A(n7104), .Y(n1598) );
OAI22X1TS U3985 ( .A0(n6520), .A1(n6079), .B0(n533), .B1(n6078), .Y(n6103)
);
NAND2BX1TS U3986 ( .AN(n1351), .B(n6832), .Y(n1349) );
OAI2BB1X2TS U3987 ( .A0N(n5445), .A1N(n5446), .B0(n744), .Y(n5934) );
INVX2TS U3988 ( .A(n4894), .Y(n4917) );
INVX2TS U3989 ( .A(n4303), .Y(n1184) );
INVX2TS U3990 ( .A(n3886), .Y(n855) );
INVX2TS U3991 ( .A(n1653), .Y(n1652) );
NOR2XLTS U3992 ( .A(n10105), .B(n11263), .Y(n9965) );
CLKAND2X2TS U3993 ( .A(n8568), .B(n8567), .Y(n649) );
INVX2TS U3994 ( .A(n8306), .Y(n8633) );
INVX2TS U3995 ( .A(n6586), .Y(n1623) );
NAND2X2TS U3996 ( .A(n6603), .B(n8206), .Y(n1620) );
AOI21X2TS U3997 ( .A0(n2473), .A1(n2472), .B0(n2471), .Y(n8057) );
ADDFHX2TS U3998 ( .A(n9311), .B(n9310), .CI(n9309), .CO(n9333), .S(n9324) );
OAI21X1TS U3999 ( .A0(n4114), .A1(n4115), .B0(n4113), .Y(n865) );
OAI21X1TS U4000 ( .A0(n4133), .A1(n9187), .B0(n4132), .Y(n9168) );
AOI21X2TS U4001 ( .A0(n4891), .A1(n4890), .B0(n4889), .Y(n1009) );
INVX2TS U4002 ( .A(n4888), .Y(n4889) );
OR2X1TS U4003 ( .A(n9882), .B(n9879), .Y(n9740) );
NOR2XLTS U4004 ( .A(n9889), .B(n9853), .Y(n9856) );
CLKAND2X2TS U4005 ( .A(n10145), .B(n10274), .Y(n10131) );
AO21XLTS U4006 ( .A0(n10137), .A1(n10274), .B0(n10276), .Y(n10130) );
OR2X1TS U4007 ( .A(n10275), .B(n10153), .Y(n10156) );
XOR2X1TS U4008 ( .A(n1590), .B(n1589), .Y(n1588) );
OAI21X2TS U4009 ( .A0(n8371), .A1(n8543), .B0(n8372), .Y(n900) );
NAND2BX2TS U4010 ( .AN(n8084), .B(n8085), .Y(n8086) );
AOI21X1TS U4011 ( .A0(n1908), .A1(n9096), .B0(n1907), .Y(n9086) );
NOR2XLTS U4012 ( .A(n9097), .B(n9102), .Y(n1908) );
OAI22X1TS U4013 ( .A0(n1677), .A1(n1675), .B0(n11220), .B1(EVEN1_Q_left[13]),
.Y(n9274) );
INVX2TS U4014 ( .A(n5314), .Y(n659) );
ADDFHX2TS U4015 ( .A(n5370), .B(n5369), .CI(n5368), .CO(n9581), .S(n9578) );
CLKAND2X2TS U4016 ( .A(n9884), .B(n9883), .Y(n9885) );
OR2X1TS U4017 ( .A(n9843), .B(n9842), .Y(n9844) );
NOR2XLTS U4018 ( .A(n9916), .B(n10237), .Y(n10986) );
AO21XLTS U4019 ( .A0(n10839), .A1(n10838), .B0(n10837), .Y(n10855) );
OR2X1TS U4020 ( .A(n10143), .B(n9906), .Y(n10953) );
AOI2BB1X1TS U4021 ( .A0N(n10155), .A1N(n11615), .B0(n11576), .Y(n9953) );
NOR2XLTS U4022 ( .A(n10275), .B(n10219), .Y(n10221) );
NOR2XLTS U4023 ( .A(n9559), .B(n9558), .Y(n9567) );
OR2X1TS U4024 ( .A(n10857), .B(n10852), .Y(n9726) );
CLKAND2X2TS U4025 ( .A(n9905), .B(n9904), .Y(n10955) );
CLKAND2X2TS U4026 ( .A(n10212), .B(n9911), .Y(n10968) );
NAND2X1TS U4027 ( .A(n2540), .B(n2539), .Y(n5199) );
XNOR2X1TS U4028 ( .A(n4582), .B(n5068), .Y(n4661) );
OAI22X1TS U4029 ( .A0(n1389), .A1(n4031), .B0(n4158), .B1(n3994), .Y(n997)
);
INVX2TS U4030 ( .A(n2724), .Y(n2726) );
XNOR2X1TS U4031 ( .A(n7108), .B(n273), .Y(n3422) );
XOR2X1TS U4032 ( .A(n2267), .B(n2450), .Y(n2268) );
XOR2X1TS U4033 ( .A(n5864), .B(n5865), .Y(n734) );
NOR2BX1TS U4034 ( .AN(n1376), .B(n6886), .Y(n1375) );
INVX2TS U4035 ( .A(n4485), .Y(n4701) );
XOR2X1TS U4036 ( .A(n6053), .B(n459), .Y(n3874) );
OAI22X1TS U4037 ( .A0(n599), .A1(n4038), .B0(n4240), .B1(n3975), .Y(n1406)
);
NOR2XLTS U4038 ( .A(n5058), .B(n5057), .Y(n680) );
NOR2BX1TS U4039 ( .AN(n3436), .B(n7104), .Y(n3552) );
NOR2X2TS U4040 ( .A(Data_A_i[37]), .B(Data_A_i[10]), .Y(n3263) );
NOR2X2TS U4041 ( .A(n3161), .B(n3162), .Y(n3368) );
OAI21X2TS U4042 ( .A0(n3177), .A1(n3176), .B0(n3178), .Y(n3363) );
NAND2BXLTS U4043 ( .AN(n632), .B(n440), .Y(n3242) );
XNOR2X1TS U4044 ( .A(n3677), .B(n6963), .Y(n3636) );
ADDFHX2TS U4045 ( .A(n7348), .B(n6483), .CI(n6482), .CO(n6515), .S(n6502) );
OAI2BB1X1TS U4046 ( .A0N(n6164), .A1N(n481), .B0(n6052), .Y(n6068) );
INVX2TS U4047 ( .A(n4594), .Y(n1542) );
OAI21X1TS U4048 ( .A0(n5805), .A1(n5806), .B0(n5804), .Y(n668) );
OAI21X1TS U4049 ( .A0(n5778), .A1(n5779), .B0(n5777), .Y(n1410) );
INVX2TS U4050 ( .A(n2023), .Y(n971) );
OAI22X1TS U4051 ( .A0(n609), .A1(n3508), .B0(n3694), .B1(n3253), .Y(n1482)
);
OAI22X1TS U4052 ( .A0(n3444), .A1(n354), .B0(n3443), .B1(n390), .Y(n3504) );
OAI22X1TS U4053 ( .A0(n3443), .A1(n354), .B0(n3438), .B1(n391), .Y(n3493) );
NOR2BX1TS U4054 ( .AN(n3436), .B(n417), .Y(n3494) );
XNOR2X1TS U4055 ( .A(n5620), .B(n428), .Y(n2205) );
INVX2TS U4056 ( .A(n130), .Y(n504) );
XNOR2X1TS U4057 ( .A(n414), .B(n5530), .Y(n2298) );
INVX4TS U4058 ( .A(n5733), .Y(n583) );
XOR2X1TS U4059 ( .A(n5992), .B(n2319), .Y(n1343) );
ADDFHX2TS U4060 ( .A(n4435), .B(n4434), .CI(n4433), .CO(n4523), .S(n4431) );
ADDFHX2TS U4061 ( .A(n4212), .B(n4211), .CI(n4210), .CO(n4226), .S(n4222) );
OAI22X1TS U4062 ( .A0(n4020), .A1(n1389), .B0(n4074), .B1(n4158), .Y(n4076)
);
INVX4TS U4063 ( .A(n4762), .Y(n287) );
NOR2X4TS U4064 ( .A(Data_B_i[7]), .B(Data_B_i[8]), .Y(n1027) );
NOR2BX1TS U4065 ( .AN(n3514), .B(n3715), .Y(n3189) );
NOR2X1TS U4066 ( .A(n2596), .B(n616), .Y(n2918) );
NOR2X2TS U4067 ( .A(n2806), .B(n2805), .Y(n2921) );
INVX2TS U4068 ( .A(n2805), .Y(n1154) );
INVX2TS U4069 ( .A(n201), .Y(n405) );
XNOR2X1TS U4070 ( .A(n7423), .B(n358), .Y(n831) );
XNOR2X1TS U4071 ( .A(n7485), .B(n361), .Y(n8236) );
NAND2X1TS U4072 ( .A(n3103), .B(n3312), .Y(n3104) );
OAI21X2TS U4073 ( .A0(n2672), .A1(n2669), .B0(n2673), .Y(n2696) );
NOR2X1TS U4074 ( .A(n234), .B(n2672), .Y(n2691) );
NAND2X1TS U4075 ( .A(n3120), .B(n1736), .Y(n1140) );
XOR2X1TS U4076 ( .A(n7507), .B(n375), .Y(n1143) );
XNOR2X1TS U4077 ( .A(n7505), .B(n375), .Y(n2996) );
NAND2BXLTS U4078 ( .AN(n4570), .B(n330), .Y(n4553) );
XNOR2X1TS U4079 ( .A(n6421), .B(n6448), .Y(n1663) );
INVX4TS U4080 ( .A(n6083), .Y(n6038) );
NAND2BX2TS U4081 ( .AN(n7309), .B(n1047), .Y(n1046) );
OAI2BB1X2TS U4082 ( .A0N(n2002), .A1N(n2001), .B0(n1228), .Y(n5311) );
OAI2BB2XLTS U4083 ( .B0(n572), .B1(n2907), .A0N(n3629), .A1N(n1497), .Y(
n3070) );
OAI22X2TS U4084 ( .A0(n2838), .A1(n355), .B0(n391), .B1(n2914), .Y(n2909) );
XNOR2X1TS U4085 ( .A(n665), .B(Data_A_i[49]), .Y(n2520) );
NAND2BX1TS U4086 ( .AN(n5536), .B(n2941), .Y(n1368) );
NAND2X2TS U4087 ( .A(n7779), .B(n5153), .Y(n7780) );
ADDFHX2TS U4088 ( .A(n5406), .B(n5405), .CI(n5404), .CO(n5445), .S(n5399) );
OAI2BB1X2TS U4089 ( .A0N(n5394), .A1N(n5393), .B0(n1448), .Y(n5404) );
NAND2X2TS U4090 ( .A(n945), .B(n4346), .Y(n4316) );
OAI2BB1X1TS U4091 ( .A0N(n1033), .A1N(n1032), .B0(n4180), .Y(n1031) );
XOR2X1TS U4092 ( .A(n4066), .B(n4067), .Y(n1556) );
INVX2TS U4093 ( .A(Data_B_i[6]), .Y(n1686) );
NAND2X4TS U4094 ( .A(Data_A_i[27]), .B(Data_A_i[0]), .Y(n2637) );
CLKAND2X2TS U4095 ( .A(n11249), .B(n11276), .Y(n9995) );
AO21XLTS U4096 ( .A0(n9994), .A1(n11297), .B0(n9993), .Y(n9996) );
NAND2X1TS U4097 ( .A(n317), .B(n298), .Y(n6897) );
XNOR2X1TS U4098 ( .A(n5080), .B(n5079), .Y(n1640) );
OAI22X1TS U4099 ( .A0(n7469), .A1(n8244), .B0(n271), .B1(n388), .Y(n8248) );
INVX2TS U4100 ( .A(n1730), .Y(n841) );
NAND2BXLTS U4101 ( .AN(n633), .B(n443), .Y(n2928) );
OAI21X2TS U4102 ( .A0(n2830), .A1(n2831), .B0(n2829), .Y(n1517) );
NOR2XLTS U4103 ( .A(n4266), .B(n4420), .Y(n4269) );
AO21X1TS U4104 ( .A0(n372), .A1(n3685), .B0(n3684), .Y(n3686) );
NAND2X1TS U4105 ( .A(n1205), .B(n4967), .Y(n1645) );
INVX2TS U4106 ( .A(n913), .Y(n563) );
NOR2BX1TS U4107 ( .AN(n1294), .B(n1292), .Y(n1287) );
OAI21X2TS U4108 ( .A0(n6229), .A1(n6228), .B0(n6227), .Y(n1569) );
OAI22X1TS U4109 ( .A0(n7737), .A1(n623), .B0(n1761), .B1(n468), .Y(n1762) );
NAND2X4TS U4110 ( .A(n1314), .B(n174), .Y(n6764) );
INVX2TS U4111 ( .A(Data_B_i[37]), .Y(n1574) );
XNOR2X1TS U4112 ( .A(n2315), .B(n2317), .Y(n934) );
INVX4TS U4113 ( .A(Data_B_i[29]), .Y(n1268) );
OAI22X1TS U4114 ( .A0(n5117), .A1(n2199), .B0(n323), .B1(n2272), .Y(n2280)
);
OA22X2TS U4115 ( .A0(n351), .A1(n2202), .B0(n555), .B1(n2276), .Y(n675) );
INVX2TS U4116 ( .A(n3970), .Y(n1183) );
INVX2TS U4117 ( .A(n4316), .Y(n4326) );
OAI21X1TS U4118 ( .A0(n4345), .A1(n4336), .B0(n4337), .Y(n4325) );
INVX2TS U4119 ( .A(n4797), .Y(n1181) );
INVX2TS U4120 ( .A(n984), .Y(n4797) );
NOR2XLTS U4121 ( .A(n10105), .B(n11266), .Y(n9950) );
INVX2TS U4122 ( .A(n2226), .Y(n1383) );
INVX2TS U4123 ( .A(n2229), .Y(n1382) );
NAND2BX2TS U4124 ( .AN(n1489), .B(n3542), .Y(n9208) );
INVX2TS U4125 ( .A(n6971), .Y(n832) );
INVX2TS U4126 ( .A(n3283), .Y(n1478) );
NAND2X2TS U4127 ( .A(n6855), .B(n1123), .Y(n1122) );
AOI21X2TS U4128 ( .A0(n6858), .A1(n1123), .B0(n1120), .Y(n1119) );
OAI2BB1X2TS U4129 ( .A0N(n6996), .A1N(n719), .B0(n8298), .Y(n1242) );
INVX2TS U4130 ( .A(n8922), .Y(n8345) );
NAND2BX1TS U4131 ( .AN(n470), .B(n1475), .Y(n1473) );
INVX2TS U4132 ( .A(n7494), .Y(n7645) );
INVX2TS U4133 ( .A(n7424), .Y(n7498) );
INVX2TS U4134 ( .A(n8936), .Y(n8437) );
XOR2X1TS U4135 ( .A(n8451), .B(n359), .Y(n7164) );
NOR2X2TS U4136 ( .A(n5019), .B(n5018), .Y(n889) );
AOI2BB1X2TS U4137 ( .A0N(n4945), .A1N(n984), .B0(n636), .Y(n635) );
NOR2X4TS U4138 ( .A(n5085), .B(n5084), .Y(n6268) );
NAND2BX1TS U4139 ( .AN(n889), .B(n6269), .Y(n1212) );
NOR2XLTS U4140 ( .A(n2701), .B(Data_B_i[41]), .Y(n2703) );
XOR2X1TS U4141 ( .A(Data_B_i[41]), .B(Data_B_i[14]), .Y(n2701) );
NOR2XLTS U4142 ( .A(n7232), .B(n7231), .Y(n8393) );
NOR2X2TS U4143 ( .A(n6606), .B(n6605), .Y(n6474) );
INVX2TS U4144 ( .A(n6430), .Y(n1402) );
INVX2TS U4145 ( .A(n6432), .Y(n1665) );
NAND2X2TS U4146 ( .A(n9453), .B(n7924), .Y(n7908) );
OAI21X1TS U4147 ( .A0(n9449), .A1(n7920), .B0(n9454), .Y(n7921) );
INVX1TS U4148 ( .A(n6474), .Y(n8552) );
NOR2X4TS U4149 ( .A(n5921), .B(n5922), .Y(n8084) );
NOR2XLTS U4150 ( .A(n5983), .B(n5982), .Y(n8087) );
INVX4TS U4151 ( .A(n525), .Y(n526) );
NOR2XLTS U4152 ( .A(n4918), .B(n4518), .Y(n4520) );
INVX1TS U4153 ( .A(n4340), .Y(n4342) );
INVX2TS U4154 ( .A(n4194), .Y(n1011) );
INVX2TS U4155 ( .A(n4115), .Y(n867) );
CLKAND2X2TS U4156 ( .A(n9786), .B(n10864), .Y(n10870) );
OR2X1TS U4157 ( .A(n9959), .B(n11525), .Y(n9787) );
CLKAND2X2TS U4158 ( .A(n9871), .B(n11423), .Y(n9811) );
CLKAND2X2TS U4159 ( .A(n9871), .B(n11463), .Y(n9815) );
AOI2BB1XLTS U4160 ( .A0N(n11385), .A1N(n11372), .B0(n11365), .Y(n9817) );
CLKAND2X2TS U4161 ( .A(n10926), .B(n10928), .Y(n10934) );
OR2X1TS U4162 ( .A(n11386), .B(n11375), .Y(n9823) );
NOR2XLTS U4163 ( .A(n9889), .B(n11425), .Y(n9820) );
OR2X1TS U4164 ( .A(n1701), .B(n1695), .Y(n10919) );
AO21XLTS U4165 ( .A0(n9763), .A1(n9765), .B0(n9768), .Y(n9762) );
CLKAND2X2TS U4166 ( .A(n10021), .B(n10018), .Y(n9940) );
CLKAND2X2TS U4167 ( .A(n10341), .B(n10340), .Y(n10342) );
INVX1TS U4168 ( .A(n2082), .Y(n2084) );
ADDFHX2TS U4169 ( .A(n7078), .B(n7077), .CI(n7076), .CO(n8935), .S(n8930) );
XOR2X1TS U4170 ( .A(n7099), .B(n8931), .Y(n1535) );
ADDFHX2TS U4171 ( .A(n8342), .B(n8341), .CI(n8340), .CO(n8353), .S(n8742) );
OAI2BB1X2TS U4172 ( .A0N(n1103), .A1N(n1106), .B0(n8920), .Y(n692) );
OAI2BB1X2TS U4173 ( .A0N(n1157), .A1N(n8643), .B0(n1155), .Y(n8688) );
OAI21XLTS U4174 ( .A0(n7690), .A1(n7281), .B0(n7282), .Y(n3704) );
NOR2XLTS U4175 ( .A(n9516), .B(n9523), .Y(n9526) );
OAI2BB1X2TS U4176 ( .A0N(n6297), .A1N(n919), .B0(n917), .Y(n7316) );
OAI21X1TS U4177 ( .A0(n919), .A1(n6297), .B0(n6296), .Y(n917) );
OAI2BB1X1TS U4178 ( .A0N(n6311), .A1N(n6310), .B0(n6309), .Y(n6363) );
INVX2TS U4179 ( .A(n7206), .Y(n1332) );
OAI21X1TS U4180 ( .A0(n1970), .A1(n1971), .B0(n1969), .Y(n1127) );
XNOR2X1TS U4181 ( .A(n2090), .B(n2089), .Y(n9122) );
INVX1TS U4182 ( .A(n2071), .Y(n2073) );
XOR2X1TS U4183 ( .A(n9272), .B(n9273), .Y(n1676) );
NOR2XLTS U4184 ( .A(n8051), .B(n2562), .Y(n2564) );
XNOR2X1TS U4185 ( .A(n2465), .B(n2464), .Y(n2495) );
OAI21X1TS U4186 ( .A0(n2407), .A1(n2555), .B0(n967), .Y(n2465) );
INVX2TS U4187 ( .A(n9636), .Y(n6808) );
INVX2TS U4188 ( .A(n9635), .Y(n527) );
XOR2X1TS U4189 ( .A(n7963), .B(n7962), .Y(n7964) );
OAI21X1TS U4190 ( .A0(n7952), .A1(n7951), .B0(n7950), .Y(n8184) );
NAND2X2TS U4191 ( .A(n4680), .B(n1010), .Y(n9152) );
OAI21X2TS U4192 ( .A0(n7274), .A1(n7272), .B0(n7275), .Y(n4366) );
NAND2X1TS U4193 ( .A(n4346), .B(n4345), .Y(n1004) );
NAND2X1TS U4194 ( .A(n856), .B(n4377), .Y(n9183) );
OA21XLTS U4195 ( .A0(n9796), .A1(n11455), .B0(n11467), .Y(n9797) );
CLKAND2X2TS U4196 ( .A(n9871), .B(n11454), .Y(n9849) );
NOR2XLTS U4197 ( .A(n10032), .B(n11533), .Y(n10841) );
CLKAND2X2TS U4198 ( .A(n10128), .B(n11521), .Y(n10925) );
CLKAND2X2TS U4199 ( .A(n1701), .B(n1695), .Y(n10921) );
OR2X1TS U4200 ( .A(n11065), .B(n11067), .Y(n10399) );
NOR2XLTS U4201 ( .A(n11140), .B(n11143), .Y(n11147) );
CLKAND2X2TS U4202 ( .A(n11173), .B(n11175), .Y(n11178) );
NOR2XLTS U4203 ( .A(n10796), .B(n10536), .Y(n10539) );
NOR2XLTS U4204 ( .A(n10796), .B(n10546), .Y(n10532) );
CLKAND2X2TS U4205 ( .A(n11590), .B(n11608), .Y(n10102) );
NOR2XLTS U4206 ( .A(n10275), .B(n11596), .Y(n10126) );
NOR2XLTS U4207 ( .A(n10275), .B(n10163), .Y(n10165) );
NOR2XLTS U4208 ( .A(n10275), .B(n10208), .Y(n10210) );
NOR2XLTS U4209 ( .A(n7359), .B(n7358), .Y(n7347) );
XOR2X1TS U4210 ( .A(n1604), .B(n1603), .Y(n1602) );
OAI2BB1X1TS U4211 ( .A0N(n1587), .A1N(n1586), .B0(n1585), .Y(n8420) );
NOR2XLTS U4212 ( .A(n9383), .B(n8951), .Y(n8953) );
NOR2XLTS U4213 ( .A(n8981), .B(n8984), .Y(n8987) );
NOR2XLTS U4214 ( .A(n9001), .B(n9021), .Y(n9004) );
ADDFHX2TS U4215 ( .A(n8416), .B(n8415), .CI(n8414), .CO(n8886), .S(n7184) );
NOR2XLTS U4216 ( .A(n8778), .B(n8777), .Y(n9046) );
NOR2XLTS U4217 ( .A(n8773), .B(n8772), .Y(n9051) );
NOR2XLTS U4218 ( .A(n7319), .B(n7320), .Y(n7323) );
NAND2X1TS U4219 ( .A(n8206), .B(n7391), .Y(n7392) );
NOR2X4TS U4220 ( .A(n9497), .B(n9496), .Y(n9508) );
INVX2TS U4221 ( .A(n8389), .Y(n8072) );
INVX2TS U4222 ( .A(n9361), .Y(n8379) );
NOR2XLTS U4223 ( .A(n9553), .B(n9563), .Y(n9557) );
XOR2X1TS U4224 ( .A(n1002), .B(n8149), .Y(n11228) );
AOI21X1TS U4225 ( .A0(n8145), .A1(n8163), .B0(n1003), .Y(n1002) );
XNOR2X1TS U4226 ( .A(n7996), .B(n7995), .Y(n11198) );
NAND2X1TS U4227 ( .A(n213), .B(n7994), .Y(n7996) );
OR2X1TS U4228 ( .A(n5100), .B(n5099), .Y(n5102) );
CLKAND2X2TS U4229 ( .A(n11529), .B(n11527), .Y(n9717) );
OR2X1TS U4230 ( .A(n11636), .B(n11500), .Y(n10831) );
CLKAND2X2TS U4231 ( .A(n9982), .B(n11496), .Y(n10856) );
AO21XLTS U4232 ( .A0(n10855), .A1(n10854), .B0(n10853), .Y(n10859) );
OR2X1TS U4233 ( .A(n9973), .B(n11524), .Y(n10864) );
AO21XLTS U4234 ( .A0(n10902), .A1(n10896), .B0(n10899), .Y(n10884) );
AO21XLTS U4235 ( .A0(n10902), .A1(n10888), .B0(n10887), .Y(n10892) );
CLKAND2X2TS U4236 ( .A(n10104), .B(n11523), .Y(n10904) );
AO21XLTS U4237 ( .A0(n10902), .A1(n10901), .B0(n10900), .Y(n10907) );
AO21XLTS U4238 ( .A0(n10899), .A1(n10898), .B0(n10897), .Y(n10900) );
AO21XLTS U4239 ( .A0(n10973), .A1(n10953), .B0(n10952), .Y(n10957) );
CLKAND2X2TS U4240 ( .A(n10975), .B(n10974), .Y(n10976) );
NAND2BXLTS U4241 ( .AN(n10966), .B(n10965), .Y(n10967) );
NAND2BXLTS U4242 ( .AN(n1704), .B(n10273), .Y(n10991) );
INVX2TS U4243 ( .A(EVEN1_Q_left[32]), .Y(add_x_1_n310) );
NAND2X1TS U4244 ( .A(add_x_1_n737), .B(n11557), .Y(add_x_1_n69) );
XNOR2X1TS U4245 ( .A(n6053), .B(n4582), .Y(n4846) );
NAND2BX1TS U4246 ( .AN(n4856), .B(n707), .Y(n4859) );
INVX2TS U4247 ( .A(n3752), .Y(n1075) );
INVX2TS U4248 ( .A(n3771), .Y(n1076) );
XOR2X1TS U4249 ( .A(Data_B_i[18]), .B(Data_B_i[4]), .Y(n3755) );
NAND2BXLTS U4250 ( .AN(n631), .B(n4582), .Y(n4583) );
NAND2X2TS U4251 ( .A(n216), .B(n1310), .Y(n4856) );
NAND2BX1TS U4252 ( .AN(n4846), .B(n1204), .Y(n1310) );
NOR2BX1TS U4253 ( .AN(n630), .B(n6594), .Y(n4855) );
NAND2X1TS U4254 ( .A(Data_A_i[17]), .B(Data_A_i[3]), .Y(n3740) );
INVX2TS U4255 ( .A(n4399), .Y(n3732) );
XOR2X1TS U4256 ( .A(n5510), .B(n5509), .Y(n5511) );
INVX2TS U4257 ( .A(n2770), .Y(n2771) );
NAND2BXLTS U4258 ( .AN(n629), .B(n447), .Y(n2541) );
XNOR2X1TS U4259 ( .A(n5530), .B(n447), .Y(n5625) );
INVX2TS U4260 ( .A(n2247), .Y(n2181) );
XNOR2X2TS U4261 ( .A(n408), .B(Data_B_i[48]), .Y(n2450) );
XOR2X1TS U4262 ( .A(Data_B_i[49]), .B(Data_B_i[35]), .Y(n2536) );
XNOR2X1TS U4263 ( .A(n2448), .B(n2536), .Y(n2452) );
NAND2X1TS U4264 ( .A(n2450), .B(n2449), .Y(n2451) );
NOR2XLTS U4265 ( .A(Data_B_i[34]), .B(Data_B_i[48]), .Y(n2448) );
NAND2X1TS U4266 ( .A(n5200), .B(n5199), .Y(n5201) );
XNOR2X1TS U4267 ( .A(n5204), .B(n1502), .Y(n5202) );
NOR2XLTS U4268 ( .A(Data_B_i[50]), .B(Data_B_i[36]), .Y(n1502) );
ADDHX1TS U4269 ( .A(n4617), .B(n4616), .CO(n4697), .S(n4682) );
OAI22X1TS U4270 ( .A0(n6494), .A1(n6397), .B0(n478), .B1(n4503), .Y(n4617)
);
NAND2BXLTS U4271 ( .AN(n4980), .B(n6557), .Y(n4853) );
NAND2BX1TS U4272 ( .AN(n4981), .B(n418), .Y(n1394) );
CLKAND2X2TS U4273 ( .A(Data_B_i[14]), .B(Data_B_i[0]), .Y(n211) );
XOR2X1TS U4274 ( .A(n936), .B(n2684), .Y(n2629) );
XOR2X1TS U4275 ( .A(n2616), .B(n1071), .Y(n2614) );
XOR2X1TS U4276 ( .A(Data_B_i[43]), .B(n712), .Y(n1071) );
XNOR2X1TS U4277 ( .A(n6485), .B(n460), .Y(n4845) );
NOR2X2TS U4278 ( .A(Data_A_i[31]), .B(Data_A_i[4]), .Y(n2753) );
NAND2X1TS U4279 ( .A(Data_A_i[32]), .B(Data_A_i[5]), .Y(n2774) );
ADDHXLTS U4280 ( .A(Data_B_i[14]), .B(Data_B_i[41]), .CO(n2610), .S(n2604)
);
INVX2TS U4281 ( .A(n3176), .Y(n789) );
INVX2TS U4282 ( .A(n2898), .Y(n2803) );
OAI21XLTS U4283 ( .A0(n4653), .A1(n4666), .B0(n4669), .Y(n4654) );
INVX2TS U4284 ( .A(n6057), .Y(n6058) );
INVX2TS U4285 ( .A(n4648), .Y(n4488) );
NOR2X1TS U4286 ( .A(Data_A_i[22]), .B(n4445), .Y(n4645) );
NAND2X1TS U4287 ( .A(Data_A_i[19]), .B(n674), .Y(n3816) );
NAND2X1TS U4288 ( .A(Data_A_i[18]), .B(Data_A_i[4]), .Y(n3811) );
INVX2TS U4289 ( .A(n3740), .Y(n1053) );
XOR2X1TS U4290 ( .A(n5559), .B(n5560), .Y(n706) );
XOR2X1TS U4291 ( .A(Data_B_i[43]), .B(Data_B_i[29]), .Y(n2015) );
CLKAND2X2TS U4292 ( .A(Data_B_i[41]), .B(Data_B_i[27]), .Y(n224) );
NOR2X2TS U4293 ( .A(Data_A_i[42]), .B(Data_A_i[28]), .Y(n2022) );
NOR2X4TS U4294 ( .A(Data_B_i[30]), .B(Data_B_i[3]), .Y(n2620) );
NAND2X1TS U4295 ( .A(n2612), .B(n2617), .Y(n2613) );
NAND2BXLTS U4296 ( .AN(n3436), .B(n500), .Y(n3404) );
XNOR2X1TS U4297 ( .A(n5530), .B(n2269), .Y(n2453) );
OAI22X1TS U4298 ( .A0(n579), .A1(n5639), .B0(n5686), .B1(n2270), .Y(n2408)
);
XNOR2X1TS U4299 ( .A(n2269), .B(n5624), .Y(n2271) );
XNOR2X1TS U4300 ( .A(n5620), .B(n414), .Y(n2299) );
XOR2X1TS U4301 ( .A(Data_B_i[47]), .B(Data_B_i[33]), .Y(n2266) );
NOR2XLTS U4302 ( .A(n1415), .B(n2536), .Y(n2537) );
XOR2X1TS U4303 ( .A(n7732), .B(n5382), .Y(n5183) );
NOR2X1TS U4304 ( .A(n2245), .B(n2248), .Y(n2439) );
NAND2X2TS U4305 ( .A(n694), .B(Data_A_i[45]), .Y(n2247) );
NAND2X2TS U4306 ( .A(n957), .B(n2023), .Y(n956) );
INVX2TS U4307 ( .A(Data_A_i[27]), .Y(n957) );
NAND2X2TS U4308 ( .A(n1096), .B(n2023), .Y(n959) );
NAND2X2TS U4309 ( .A(n2022), .B(n2023), .Y(n958) );
NOR2X2TS U4310 ( .A(Data_A_i[30]), .B(Data_A_i[44]), .Y(n2180) );
NOR2X2TS U4311 ( .A(Data_A_i[29]), .B(Data_A_i[43]), .Y(n2177) );
NAND2X1TS U4312 ( .A(Data_A_i[44]), .B(Data_A_i[30]), .Y(n2178) );
NAND2X1TS U4313 ( .A(Data_A_i[35]), .B(Data_A_i[49]), .Y(n5156) );
NOR2X1TS U4314 ( .A(Data_A_i[51]), .B(Data_A_i[37]), .Y(n5187) );
NAND2X1TS U4315 ( .A(Data_B_i[51]), .B(Data_B_i[37]), .Y(n5147) );
XOR2X1TS U4316 ( .A(n6485), .B(n6123), .Y(n4691) );
INVX2TS U4317 ( .A(n4457), .Y(n994) );
XNOR2X1TS U4318 ( .A(n382), .B(n630), .Y(n3852) );
NAND2X1TS U4319 ( .A(n4071), .B(n520), .Y(n1176) );
NOR2X1TS U4320 ( .A(n621), .B(n4252), .Y(n4442) );
OAI21XLTS U4321 ( .A0(n4040), .A1(n187), .B0(n997), .Y(n1201) );
XOR2X1TS U4322 ( .A(n997), .B(n1202), .Y(n4035) );
INVX2TS U4323 ( .A(Data_A_i[7]), .Y(n4273) );
XNOR2X1TS U4324 ( .A(n6370), .B(n3775), .Y(n4950) );
NAND2BX2TS U4325 ( .AN(n1204), .B(n4580), .Y(n6549) );
XNOR2X1TS U4326 ( .A(n6314), .B(n452), .Y(n6135) );
XNOR2X1TS U4327 ( .A(n6572), .B(n383), .Y(n6048) );
AOI2BB1X2TS U4328 ( .A0N(n3730), .A1N(n4691), .B0(n1685), .Y(n1684) );
NOR2BX1TS U4329 ( .AN(n176), .B(n4679), .Y(n1685) );
OR2X4TS U4330 ( .A(n2629), .B(n2628), .Y(n2642) );
NAND2X1TS U4331 ( .A(n2627), .B(n618), .Y(n2791) );
INVX2TS U4332 ( .A(n2639), .Y(n2794) );
NOR2X1TS U4333 ( .A(n2627), .B(n618), .Y(n2625) );
OAI21XLTS U4334 ( .A0(n2731), .A1(n3398), .B0(n142), .Y(n2730) );
XOR2X1TS U4335 ( .A(n2859), .B(n2858), .Y(n2839) );
XNOR2X1TS U4336 ( .A(n2778), .B(n2782), .Y(n2757) );
XOR2X1TS U4337 ( .A(n2779), .B(n2783), .Y(n2785) );
ADDHXLTS U4338 ( .A(Data_A_i[14]), .B(Data_A_i[41]), .CO(n2722), .S(n2645)
);
INVX2TS U4339 ( .A(n3285), .Y(n1163) );
INVX2TS U4340 ( .A(n3284), .Y(n1164) );
INVX2TS U4341 ( .A(n6854), .Y(n1161) );
INVX2TS U4342 ( .A(n6857), .Y(n1116) );
INVX2TS U4343 ( .A(n6855), .Y(n3282) );
NAND2X1TS U4344 ( .A(n2861), .B(n2860), .Y(n3134) );
XOR2X1TS U4345 ( .A(n344), .B(n341), .Y(n820) );
OAI21XLTS U4346 ( .A0(n343), .A1(n340), .B0(n3647), .Y(n1144) );
INVX2TS U4347 ( .A(n4829), .Y(n884) );
OAI21XLTS U4348 ( .A0(n2948), .A1(n3089), .B0(n3093), .Y(n2949) );
AOI21X1TS U4349 ( .A0(n2951), .A1(n2706), .B0(n2705), .Y(n2707) );
AOI21X1TS U4350 ( .A0(n2697), .A1(n2696), .B0(n2695), .Y(n3099) );
OAI21X2TS U4351 ( .A0(n2773), .A1(n2770), .B0(n2774), .Y(n2843) );
NOR2X4TS U4352 ( .A(Data_A_i[7]), .B(Data_A_i[34]), .Y(n2850) );
NOR2X2TS U4353 ( .A(n2724), .B(n2717), .Y(n1080) );
OAI21X2TS U4354 ( .A0(n2592), .A1(n2590), .B0(n2593), .Y(n2896) );
ADDHX1TS U4355 ( .A(n3525), .B(n2961), .CO(n2824), .S(n2998) );
INVX2TS U4356 ( .A(n3162), .Y(n3164) );
INVX2TS U4357 ( .A(n2903), .Y(n2905) );
OAI21X1TS U4358 ( .A0(n3511), .A1(n2645), .B0(n2698), .Y(n2633) );
XOR2X1TS U4359 ( .A(n2731), .B(n3398), .Y(n2745) );
XNOR2X1TS U4360 ( .A(n3677), .B(n790), .Y(n1241) );
INVX2TS U4361 ( .A(n7313), .Y(n6359) );
XOR2X2TS U4362 ( .A(Data_B_i[26]), .B(Data_B_i[12]), .Y(n4847) );
NAND2X1TS U4363 ( .A(Data_A_i[24]), .B(n287), .Y(n4669) );
NAND2X1TS U4364 ( .A(Data_A_i[26]), .B(Data_A_i[12]), .Y(n4986) );
ADDFHX2TS U4365 ( .A(n1001), .B(n6156), .CI(n6157), .CO(n6326), .S(n6194) );
INVX2TS U4366 ( .A(n7293), .Y(n6157) );
NOR2XLTS U4367 ( .A(n5321), .B(n5194), .Y(n5652) );
INVX2TS U4368 ( .A(Data_B_i[39]), .Y(n1348) );
INVX2TS U4369 ( .A(n7761), .Y(n5632) );
ADDFHX2TS U4370 ( .A(n5671), .B(n5670), .CI(n5669), .CO(n5676), .S(n5723) );
INVX2TS U4371 ( .A(n7762), .Y(n5671) );
INVX2TS U4372 ( .A(n5636), .Y(n5670) );
INVX2TS U4373 ( .A(n2359), .Y(n2153) );
ADDFX2TS U4374 ( .A(n2126), .B(n2125), .CI(n2124), .CO(n2141), .S(n2110) );
AO21XLTS U4375 ( .A0(n544), .A1(n693), .B0(n1982), .Y(n2118) );
OAI22X1TS U4376 ( .A0(n7737), .A1(n1743), .B0(n1783), .B1(n7736), .Y(n1774)
);
NOR2X2TS U4377 ( .A(Data_B_i[31]), .B(Data_B_i[4]), .Y(n2586) );
INVX2TS U4378 ( .A(n3482), .Y(n1251) );
OAI2BB1X1TS U4379 ( .A0N(n3485), .A1N(n3486), .B0(n724), .Y(n3481) );
OAI21XLTS U4380 ( .A0(n3486), .A1(n3485), .B0(n3484), .Y(n724) );
OAI22X1TS U4381 ( .A0(n8425), .A1(n3434), .B0(n3422), .B1(n416), .Y(n3429)
);
XNOR2X1TS U4382 ( .A(n3677), .B(n3609), .Y(n3441) );
XNOR2X2TS U4383 ( .A(n725), .B(n3486), .Y(n3524) );
XNOR2X1TS U4384 ( .A(n3485), .B(n3484), .Y(n725) );
XOR2X1TS U4385 ( .A(n785), .B(n5751), .Y(n5786) );
XOR2X1TS U4386 ( .A(n5752), .B(n5753), .Y(n785) );
AO21X1TS U4387 ( .A0(n1989), .A1(n596), .B0(n406), .Y(n2352) );
OAI22X1TS U4388 ( .A0(n2485), .A1(n2377), .B0(n603), .B1(n2484), .Y(n2480)
);
INVX2TS U4389 ( .A(n9614), .Y(n6707) );
ADDFHX2TS U4390 ( .A(n5508), .B(n5507), .CI(n5506), .CO(n5861), .S(n5867) );
INVX2TS U4391 ( .A(n9579), .Y(n5363) );
OAI21X2TS U4392 ( .A0(n5157), .A1(n5156), .B0(n5155), .Y(n5184) );
XOR2X1TS U4393 ( .A(Data_B_i[53]), .B(Data_B_i[39]), .Y(n5151) );
INVX2TS U4394 ( .A(n8196), .Y(n5305) );
ADDFX2TS U4395 ( .A(n4467), .B(n4466), .CI(n4465), .CO(n4719), .S(n4469) );
OAI2BB1X1TS U4396 ( .A0N(n3899), .A1N(n777), .B0(n776), .Y(n3868) );
INVX2TS U4397 ( .A(n4117), .Y(n3910) );
OAI2BB1X1TS U4398 ( .A0N(n4028), .A1N(n1406), .B0(n1404), .Y(n4220) );
OAI21XLTS U4399 ( .A0(n4028), .A1(n1406), .B0(n4027), .Y(n1404) );
NAND2BXLTS U4400 ( .AN(n630), .B(n460), .Y(n3905) );
INVX4TS U4401 ( .A(Data_B_i[7]), .Y(n1565) );
OAI21XLTS U4402 ( .A0(n680), .A1(n6666), .B0(n679), .Y(n6222) );
AO21XLTS U4403 ( .A0(n11262), .A1(n11281), .B0(n11246), .Y(n10107) );
OAI2BB1X1TS U4404 ( .A0N(n3070), .A1N(n3069), .B0(n1512), .Y(n3541) );
OAI21XLTS U4405 ( .A0(n3069), .A1(n3070), .B0(n1513), .Y(n1512) );
INVX2TS U4406 ( .A(n3203), .Y(n1121) );
INVX2TS U4407 ( .A(n6853), .Y(n1124) );
NAND2X1TS U4408 ( .A(n1114), .B(n1113), .Y(n3117) );
INVX2TS U4409 ( .A(n2925), .Y(n1114) );
NAND2X1TS U4410 ( .A(n2925), .B(n2924), .Y(n3201) );
NOR2X1TS U4411 ( .A(n2872), .B(n2875), .Y(n3090) );
OAI21XLTS U4412 ( .A0(n3094), .A1(n3093), .B0(n3092), .Y(n3095) );
NAND2X1TS U4413 ( .A(n316), .B(n297), .Y(n6916) );
NAND2X1TS U4414 ( .A(n1112), .B(n1111), .Y(n1110) );
XOR2X1TS U4415 ( .A(n7507), .B(n1135), .Y(n7651) );
XNOR2X1TS U4416 ( .A(n7423), .B(n8278), .Y(n7652) );
XOR2X1TS U4417 ( .A(n439), .B(n823), .Y(n7508) );
OAI2BB1X1TS U4418 ( .A0N(n3554), .A1N(n1482), .B0(n1480), .Y(n3578) );
OAI21X1TS U4419 ( .A0(n3554), .A1(n1482), .B0(n3553), .Y(n1480) );
INVX2TS U4420 ( .A(n6999), .Y(n7000) );
ADDHXLTS U4421 ( .A(n7541), .B(n7540), .CO(n7542), .S(n7582) );
NAND2BXLTS U4422 ( .AN(n627), .B(n405), .Y(n7439) );
OAI21X1TS U4423 ( .A0(n1531), .A1(n3310), .B0(n3312), .Y(n3234) );
OAI2BB1X2TS U4424 ( .A0N(n4835), .A1N(n4834), .B0(n748), .Y(n5016) );
INVX2TS U4425 ( .A(n4835), .Y(n749) );
INVX2TS U4426 ( .A(n4834), .Y(n750) );
INVX2TS U4427 ( .A(n6667), .Y(n5037) );
XOR2X1TS U4428 ( .A(n1041), .B(n5076), .Y(n5080) );
XNOR2X1TS U4429 ( .A(n5077), .B(n4947), .Y(n1041) );
OAI2BB1X1TS U4430 ( .A0N(n884), .A1N(n4956), .B0(n882), .Y(n5079) );
OAI2BB1X1TS U4431 ( .A0N(n4837), .A1N(n806), .B0(n805), .Y(n4997) );
XOR2X1TS U4432 ( .A(n6921), .B(n393), .Y(n7432) );
XOR2X1TS U4433 ( .A(Data_B_i[49]), .B(Data_B_i[22]), .Y(n3225) );
INVX2TS U4434 ( .A(n3091), .Y(n2947) );
NAND2X1TS U4435 ( .A(n3350), .B(n1731), .Y(n1732) );
INVX2TS U4436 ( .A(n1731), .Y(n843) );
NAND2X1TS U4437 ( .A(n3359), .B(n1734), .Y(n3379) );
OR2X2TS U4438 ( .A(n3344), .B(n3339), .Y(n218) );
INVX2TS U4439 ( .A(n3386), .Y(n3350) );
NAND2X1TS U4440 ( .A(Data_B_i[39]), .B(Data_B_i[12]), .Y(n3381) );
XNOR2X1TS U4441 ( .A(n817), .B(n815), .Y(n814) );
INVX2TS U4442 ( .A(n3364), .Y(n3366) );
INVX2TS U4443 ( .A(n3161), .Y(n3130) );
INVX2TS U4444 ( .A(n3363), .Y(n3260) );
NAND2BXLTS U4445 ( .AN(n633), .B(n433), .Y(n2889) );
XNOR2X1TS U4446 ( .A(n7423), .B(n376), .Y(n2927) );
OAI22X1TS U4447 ( .A0(n2927), .A1(n441), .B0(n378), .B1(n2809), .Y(n2830) );
INVX2TS U4448 ( .A(n3539), .Y(n3071) );
OAI22X2TS U4449 ( .A0(n274), .A1(n3636), .B0(n609), .B1(n1241), .Y(n3656) );
INVX2TS U4450 ( .A(n7348), .Y(n6528) );
INVX2TS U4451 ( .A(n6287), .Y(n6390) );
AOI21X1TS U4452 ( .A0(n4673), .A1(n4672), .B0(n4671), .Y(n4989) );
OAI21XLTS U4453 ( .A0(n4670), .A1(n4669), .B0(n4668), .Y(n4671) );
INVX2TS U4454 ( .A(Data_A_i[13]), .Y(n4985) );
XNOR2X1TS U4455 ( .A(n4967), .B(Data_A_i[26]), .Y(n5040) );
INVX2TS U4456 ( .A(n290), .Y(n4970) );
XNOR2X1TS U4457 ( .A(n1348), .B(Data_B_i[40]), .Y(n905) );
OAI2BB1X1TS U4458 ( .A0N(n5014), .A1N(n5013), .B0(n1596), .Y(n5059) );
XNOR2X1TS U4459 ( .A(n6243), .B(n6244), .Y(n922) );
ADDFHX2TS U4460 ( .A(n6256), .B(n6255), .CI(n6254), .CO(n6261), .S(n6263) );
OAI2BB1X1TS U4461 ( .A0N(n5080), .A1N(n5079), .B0(n1639), .Y(n6254) );
ADDFHX2TS U4462 ( .A(n5877), .B(n5876), .CI(n5875), .CO(n5903), .S(n5887) );
INVX2TS U4463 ( .A(n5524), .Y(n5876) );
OAI2BB1X1TS U4464 ( .A0N(n5779), .A1N(n5778), .B0(n1410), .Y(n5791) );
OAI2BB1X1TS U4465 ( .A0N(n5806), .A1N(n5805), .B0(n668), .Y(n5789) );
INVX2TS U4466 ( .A(n5676), .Y(n1372) );
ADDFHX2TS U4467 ( .A(n2217), .B(n2216), .CI(n2215), .CO(n2341), .S(n2220) );
NAND2X1TS U4468 ( .A(n969), .B(n1887), .Y(n2024) );
OAI2BB1X2TS U4469 ( .A0N(n1822), .A1N(n1821), .B0(n909), .Y(n2001) );
OAI2BB1X1TS U4470 ( .A0N(n911), .A1N(n910), .B0(n1820), .Y(n909) );
XOR2X1TS U4471 ( .A(n1327), .B(n1978), .Y(n1326) );
ADDFX1TS U4472 ( .A(n1778), .B(n1777), .CI(n1776), .CO(n1830), .S(n1780) );
ADDFHX2TS U4473 ( .A(n3464), .B(n3463), .CI(n3462), .CO(n3617), .S(n3450) );
XNOR2X1TS U4474 ( .A(Data_B_i[28]), .B(Data_A_i[37]), .Y(n1921) );
OAI22X1TS U4475 ( .A0(n3634), .A1(n2819), .B0(n2836), .B1(n570), .Y(n2883)
);
XOR2X1TS U4476 ( .A(n1481), .B(n3553), .Y(n3563) );
XOR2X1TS U4477 ( .A(n3554), .B(n1482), .Y(n1481) );
ADDFHX2TS U4478 ( .A(n3502), .B(n3501), .CI(n3500), .CO(n3495), .S(n3573) );
NAND2BX1TS U4479 ( .AN(n1679), .B(n3557), .Y(n3517) );
INVX2TS U4480 ( .A(n2497), .Y(n5776) );
INVX2TS U4481 ( .A(n6000), .Y(n2504) );
OAI2BB1X1TS U4482 ( .A0N(n2317), .A1N(n2316), .B0(n933), .Y(n2327) );
XNOR2X1TS U4483 ( .A(n1343), .B(n2318), .Y(n2326) );
NOR2X1TS U4484 ( .A(n1337), .B(n1336), .Y(n1335) );
INVX2TS U4485 ( .A(n5468), .Y(n5958) );
ADDFHX2TS U4486 ( .A(n5415), .B(n5414), .CI(n5413), .CO(n5463), .S(n5408) );
INVX2TS U4487 ( .A(n9580), .Y(n5414) );
XNOR2X1TS U4488 ( .A(Data_B_i[44]), .B(Data_A_i[52]), .Y(n5129) );
INVX2TS U4489 ( .A(Data_B_i[47]), .Y(n1370) );
INVX2TS U4490 ( .A(Data_B_i[46]), .Y(n5225) );
INVX2TS U4491 ( .A(n7200), .Y(n6785) );
NOR2BX1TS U4492 ( .AN(n1351), .B(n6832), .Y(n1350) );
XNOR2X1TS U4493 ( .A(n6832), .B(n1697), .Y(n1352) );
OAI2BB2X1TS U4494 ( .B0(n5539), .B1(n6727), .A0N(n1669), .A1N(n5499), .Y(
n5543) );
NAND2BXLTS U4495 ( .AN(n5497), .B(n526), .Y(n5498) );
OAI22X1TS U4496 ( .A0(n332), .A1(n5569), .B0(n5496), .B1(n5568), .Y(n5544)
);
OAI22X1TS U4497 ( .A0(n5571), .A1(n5496), .B0(n5261), .B1(n2031), .Y(n5501)
);
OAI2BB1X1TS U4498 ( .A0N(n5903), .A1N(n5904), .B0(n1222), .Y(n5897) );
INVX2TS U4499 ( .A(n5394), .Y(n1450) );
INVX2TS U4500 ( .A(n5182), .Y(n5353) );
INVX2TS U4501 ( .A(n5860), .Y(n643) );
INVX2TS U4502 ( .A(n5859), .Y(n644) );
INVX2TS U4503 ( .A(Data_A_i[40]), .Y(n7734) );
NAND2BXLTS U4504 ( .AN(n969), .B(n281), .Y(n2292) );
NAND2X1TS U4505 ( .A(n1636), .B(n1634), .Y(n6490) );
NAND2BX1TS U4506 ( .AN(n1635), .B(n4758), .Y(n1634) );
OAI2BB1X1TS U4507 ( .A0N(n795), .A1N(n794), .B0(n4511), .Y(n793) );
XOR2X1TS U4508 ( .A(n1637), .B(n4758), .Y(n6439) );
XOR2X1TS U4509 ( .A(n4756), .B(n4757), .Y(n1637) );
INVX2TS U4510 ( .A(n3962), .Y(n1185) );
OAI2BB1X1TS U4511 ( .A0N(n4284), .A1N(n4283), .B0(n699), .Y(n4430) );
ADDFHX2TS U4512 ( .A(n4227), .B(n4226), .CI(n4225), .CO(n6193), .S(n6056) );
XOR2X1TS U4513 ( .A(n4233), .B(n4232), .Y(n996) );
OAI22X2TS U4514 ( .A0(n898), .A1(n4001), .B0(n144), .B1(n4019), .Y(n871) );
OAI2BB1X1TS U4515 ( .A0N(n4076), .A1N(n879), .B0(n877), .Y(n4081) );
OAI2BB1X1TS U4516 ( .A0N(n4061), .A1N(n4062), .B0(n4018), .Y(n4082) );
OAI21XLTS U4517 ( .A0(n4076), .A1(n879), .B0(n4075), .Y(n877) );
XOR2X1TS U4518 ( .A(n4076), .B(n879), .Y(n878) );
NAND2X1TS U4519 ( .A(n1178), .B(n520), .Y(n1177) );
OAI2BB1X1TS U4520 ( .A0N(n6244), .A1N(n6243), .B0(n921), .Y(n6257) );
OAI2BB1X2TS U4521 ( .A0N(n716), .A1N(n6221), .B0(n1560), .Y(n6218) );
OAI2BB1X1TS U4522 ( .A0N(n6226), .A1N(n943), .B0(n942), .Y(n6233) );
OAI2BB1X1TS U4523 ( .A0N(n4730), .A1N(n4729), .B0(n902), .Y(n4726) );
AO21XLTS U4524 ( .A0(n11262), .A1(n11268), .B0(n11244), .Y(n10094) );
CLKAND2X2TS U4525 ( .A(n11251), .B(n11265), .Y(n10060) );
OA21XLTS U4526 ( .A0(n10370), .A1(n10359), .B0(n10368), .Y(n10053) );
CLKAND2X2TS U4527 ( .A(n10050), .B(n10362), .Y(n10054) );
OR2X1TS U4528 ( .A(n10105), .B(n11275), .Y(n9957) );
AND2X2TS U4529 ( .A(n11328), .B(n10168), .Y(n10174) );
ADDFHX2TS U4530 ( .A(n297), .B(n316), .CI(n7106), .CO(n6967), .S(n6966) );
NOR2X2TS U4531 ( .A(n6966), .B(n6968), .Y(n829) );
XOR2X2TS U4532 ( .A(n6962), .B(n6967), .Y(n6970) );
INVX2TS U4533 ( .A(n3117), .Y(n3198) );
OAI21X2TS U4534 ( .A0(n3201), .A1(n3200), .B0(n3199), .Y(n6858) );
OAI21X1TS U4535 ( .A0(n2921), .A1(n2920), .B0(n2919), .Y(n2922) );
OAI2BB1X2TS U4536 ( .A0N(n6962), .A1N(n6967), .B0(n833), .Y(n6961) );
NOR2XLTS U4537 ( .A(n6921), .B(n453), .Y(n6936) );
XNOR2X1TS U4538 ( .A(n7550), .B(n380), .Y(n7072) );
XOR2X1TS U4539 ( .A(n6887), .B(n6884), .Y(n201) );
XOR2X1TS U4540 ( .A(n8451), .B(n440), .Y(n7013) );
OAI21X2TS U4541 ( .A0(n8326), .A1(n470), .B0(n1474), .Y(n8568) );
NAND2X1TS U4542 ( .A(n8325), .B(n1475), .Y(n1474) );
XNOR2X1TS U4543 ( .A(n8276), .B(n439), .Y(n7014) );
XOR2X1TS U4544 ( .A(n8451), .B(n443), .Y(n8315) );
INVX2TS U4545 ( .A(n3564), .Y(n7835) );
NAND2X1TS U4546 ( .A(n8323), .B(n2751), .Y(n815) );
OAI21X1TS U4547 ( .A0(n3271), .A1(n564), .B0(n818), .Y(n817) );
NAND2BX2TS U4548 ( .AN(n817), .B(n815), .Y(n813) );
NAND2BXLTS U4549 ( .AN(n633), .B(n438), .Y(n7503) );
ADDFHX2TS U4550 ( .A(n8303), .B(n8302), .CI(n8301), .CO(n8298), .S(n8332) );
OAI22X1TS U4551 ( .A0(n1109), .A1(n506), .B0(n557), .B1(n831), .Y(n8302) );
OAI22X1TS U4552 ( .A0(n8316), .A1(n615), .B0(n8574), .B1(n412), .Y(n8601) );
XOR2X1TS U4553 ( .A(n8311), .B(n440), .Y(n1475) );
XNOR2X1TS U4554 ( .A(n8451), .B(n432), .Y(n8576) );
NAND2BX1TS U4555 ( .AN(n8574), .B(n8573), .Y(n1166) );
CLKAND2X2TS U4556 ( .A(n822), .B(n821), .Y(n7671) );
XOR2X1TS U4557 ( .A(n7530), .B(n7529), .Y(n1085) );
XOR2X1TS U4558 ( .A(n8451), .B(n376), .Y(n7528) );
XOR2X1TS U4559 ( .A(n8451), .B(n431), .Y(n7514) );
XNOR2X1TS U4560 ( .A(n8317), .B(n439), .Y(n7406) );
XNOR2X1TS U4561 ( .A(n440), .B(n7423), .Y(n7516) );
INVX2TS U4562 ( .A(n4944), .Y(n636) );
XNOR2X1TS U4563 ( .A(n7474), .B(n2939), .Y(n7445) );
XNOR2X1TS U4564 ( .A(n7550), .B(n362), .Y(n7486) );
XNOR2X1TS U4565 ( .A(n254), .B(n665), .Y(n2702) );
ADDHXLTS U4566 ( .A(n3306), .B(n3305), .CO(n7579), .S(n3326) );
NAND2BXLTS U4567 ( .AN(n625), .B(n395), .Y(n3229) );
NAND2BXLTS U4568 ( .AN(n627), .B(n393), .Y(n2945) );
OAI21X2TS U4569 ( .A0(n2953), .A1(n2665), .B0(n2664), .Y(n2668) );
NAND2X1TS U4570 ( .A(n2663), .B(n2693), .Y(n2649) );
NAND2BX1TS U4571 ( .AN(n1259), .B(n2657), .Y(n1257) );
CLKAND2X2TS U4572 ( .A(n4813), .B(n1096), .Y(n234) );
NAND2X1TS U4573 ( .A(Data_A_i[40]), .B(Data_A_i[13]), .Y(n3356) );
OAI22X1TS U4574 ( .A0(n2821), .A1(n8308), .B0(n567), .B1(n2820), .Y(n2967)
);
INVX2TS U4575 ( .A(n3535), .Y(n2968) );
ADDFHX2TS U4576 ( .A(n3002), .B(n3001), .CI(n3000), .CO(n3021), .S(n3023) );
NAND2BX1TS U4577 ( .AN(n377), .B(n1143), .Y(n1142) );
ADDFHX2TS U4578 ( .A(n2977), .B(n2976), .CI(n2975), .CO(n3150), .S(n2978) );
XNOR2X1TS U4579 ( .A(n2829), .B(n1518), .Y(n2975) );
XNOR2X1TS U4580 ( .A(n2830), .B(n2831), .Y(n1518) );
INVX2TS U4581 ( .A(n3372), .Y(n3261) );
NAND2BX1TS U4582 ( .AN(n7828), .B(n1143), .Y(n1141) );
ADDFHX2TS U4583 ( .A(n6583), .B(n6582), .CI(n6581), .CO(n6584), .S(n6567) );
OAI2BB1X1TS U4584 ( .A0N(n6464), .A1N(n6463), .B0(n863), .Y(n6476) );
OAI2BB1X1TS U4585 ( .A0N(n6393), .A1N(n6392), .B0(n738), .Y(n6432) );
XOR2X1TS U4586 ( .A(n1293), .B(n1292), .Y(n1288) );
INVX2TS U4587 ( .A(n6470), .Y(n737) );
INVX2TS U4588 ( .A(Data_B_i[19]), .Y(n474) );
ADDFHX2TS U4589 ( .A(n6046), .B(n6045), .CI(n6044), .CO(n6147), .S(n6116) );
OAI2BB1X2TS U4590 ( .A0N(n6279), .A1N(n6280), .B0(n1050), .Y(n6473) );
OAI21X2TS U4591 ( .A0(n6279), .A1(n6280), .B0(n6278), .Y(n1050) );
ADDFHX2TS U4592 ( .A(n5832), .B(n5831), .CI(n5830), .CO(n5835), .S(n5834) );
NOR2X2TS U4593 ( .A(n5834), .B(n5833), .Y(n7207) );
ADDFHX2TS U4594 ( .A(n6779), .B(n6778), .CI(n6777), .CO(n7218), .S(n7201) );
ADDFX2TS U4595 ( .A(n1756), .B(n1755), .CI(n1754), .CO(n1781), .S(n1810) );
OAI22X1TS U4596 ( .A0(n379), .A1(n2765), .B0(n606), .B1(n2769), .Y(n2959) );
XOR2X1TS U4597 ( .A(n6257), .B(n1295), .Y(n6260) );
XOR2X1TS U4598 ( .A(n6258), .B(n6259), .Y(n1295) );
OAI21XLTS U4599 ( .A0(n5765), .A1(n5764), .B0(n952), .Y(n951) );
NAND2X1TS U4600 ( .A(n2219), .B(n2218), .Y(n2332) );
INVX2TS U4601 ( .A(n2050), .Y(n1386) );
NAND2BXLTS U4602 ( .AN(n3511), .B(n616), .Y(n2822) );
INVX2TS U4603 ( .A(n2384), .Y(n373) );
XOR2X1TS U4604 ( .A(n1499), .B(n1514), .Y(n3540) );
XNOR2X1TS U4605 ( .A(n3069), .B(n3070), .Y(n1499) );
OAI2BB1X1TS U4606 ( .A0N(n2884), .A1N(n2885), .B0(n755), .Y(n3536) );
OAI21XLTS U4607 ( .A0(n2885), .A1(n2884), .B0(n2883), .Y(n755) );
NAND2X1TS U4608 ( .A(n3565), .B(n3564), .Y(n9164) );
NAND2X4TS U4609 ( .A(n7858), .B(n7860), .Y(n1671) );
OAI2BB1X1TS U4610 ( .A0N(n2488), .A1N(n1334), .B0(n1333), .Y(n2566) );
NAND2BXLTS U4611 ( .AN(Data_A_i[41]), .B(n5485), .Y(n2521) );
ADDFHX2TS U4612 ( .A(n6700), .B(n6699), .CI(n6698), .CO(n6753), .S(n6701) );
XOR2X1TS U4613 ( .A(n5412), .B(n1341), .Y(n5464) );
XNOR2X1TS U4614 ( .A(n5457), .B(n5458), .Y(n1341) );
ADDFHX2TS U4615 ( .A(n5976), .B(n5975), .CI(n5974), .CO(n6695), .S(n5938) );
OAI2BB1X1TS U4616 ( .A0N(n2412), .A1N(n2411), .B0(n2410), .Y(n5999) );
ADDFHX2TS U4617 ( .A(n6840), .B(n6839), .CI(n6838), .CO(n7726), .S(n6812) );
OAI2BB1X1TS U4618 ( .A0N(n5601), .A1N(n5600), .B0(n666), .Y(n7761) );
NOR2BX2TS U4619 ( .AN(n7766), .B(n1447), .Y(n1446) );
INVX2TS U4620 ( .A(n8084), .Y(n1362) );
OAI21X1TS U4621 ( .A0(n5399), .A1(n5400), .B0(n5398), .Y(n1451) );
NAND2BX2TS U4622 ( .AN(n1185), .B(n3963), .Y(n4303) );
INVX2TS U4623 ( .A(n4455), .Y(n4419) );
INVX2TS U4624 ( .A(n4921), .Y(n4428) );
AOI21X1TS U4625 ( .A0(n4325), .A1(n4329), .B0(n1038), .Y(n1037) );
NOR2XLTS U4626 ( .A(n4316), .B(n4327), .Y(n4317) );
XOR2X1TS U4627 ( .A(n4138), .B(n4137), .Y(n851) );
OAI22X1TS U4628 ( .A0(n4209), .A1(n4151), .B0(n4070), .B1(n858), .Y(n4161)
);
OAI2BB1X1TS U4629 ( .A0N(n4138), .A1N(n4137), .B0(n850), .Y(n4188) );
OAI21XLTS U4630 ( .A0(n4137), .A1(n4138), .B0(n4136), .Y(n850) );
ADDFX2TS U4631 ( .A(n4164), .B(n4163), .CI(n4162), .CO(n4186), .S(n4173) );
NAND2BXLTS U4632 ( .AN(Data_A_i[0]), .B(n262), .Y(n3758) );
NAND2X2TS U4633 ( .A(n1544), .B(n4239), .Y(n367) );
NOR2X2TS U4634 ( .A(n6274), .B(n6275), .Y(n9472) );
ADDFHX2TS U4635 ( .A(n6250), .B(n6249), .CI(n6248), .CO(n6274), .S(n6273) );
OAI2BB1X2TS U4636 ( .A0N(n1399), .A1N(n1398), .B0(n6257), .Y(n1397) );
INVX2TS U4637 ( .A(n8112), .Y(n1042) );
NOR2X2TS U4638 ( .A(n4869), .B(n4868), .Y(n4945) );
OR3X1TS U4639 ( .A(n10049), .B(n10048), .C(n10047), .Y(n10363) );
NOR2XLTS U4640 ( .A(n10046), .B(n1689), .Y(n10047) );
XOR2X1TS U4641 ( .A(n11328), .B(n10168), .Y(n10170) );
AOI2BB1XLTS U4642 ( .A0N(n9873), .A1N(n11464), .B0(n11428), .Y(n9809) );
CLKAND2X2TS U4643 ( .A(n11428), .B(n11442), .Y(n9852) );
CLKAND2X2TS U4644 ( .A(n10364), .B(n10363), .Y(n10365) );
NOR2XLTS U4645 ( .A(n10426), .B(n10429), .Y(n10431) );
CLKAND2X2TS U4646 ( .A(n10685), .B(n10684), .Y(n10793) );
OAI2BB1X1TS U4647 ( .A0N(n8943), .A1N(n8942), .B0(n8437), .Y(n1581) );
AND2X2TS U4648 ( .A(n8426), .B(n6883), .Y(n8427) );
NAND2X1TS U4649 ( .A(Data_B_i[53]), .B(n735), .Y(n6874) );
INVX2TS U4650 ( .A(n753), .Y(n7037) );
OAI22X1TS U4651 ( .A0(n554), .A1(n7071), .B0(n457), .B1(n201), .Y(n7160) );
AOI21X1TS U4652 ( .A0(n8255), .A1(n458), .B0(n201), .Y(n1589) );
ADDFHX2TS U4653 ( .A(n7049), .B(n7048), .CI(n7047), .CO(n7099), .S(n7058) );
AO21X1TS U4654 ( .A0(n412), .A1(n615), .B0(n6986), .Y(n7049) );
INVX2TS U4655 ( .A(n6988), .Y(n7047) );
OAI22X1TS U4656 ( .A0(n557), .A1(n8320), .B0(n507), .B1(n8319), .Y(n8571) );
INVX2TS U4657 ( .A(n8595), .Y(n1165) );
ADDFHX2TS U4658 ( .A(n8608), .B(n8607), .CI(n8606), .CO(n8622), .S(n8604) );
INVX2TS U4659 ( .A(n7618), .Y(n8606) );
INVX2TS U4660 ( .A(n7412), .Y(n7417) );
INVX2TS U4661 ( .A(n8828), .Y(n7628) );
NAND2BX1TS U4662 ( .AN(n7128), .B(n8934), .Y(n1578) );
INVX2TS U4663 ( .A(n8930), .Y(n7136) );
ADDFHX2TS U4664 ( .A(n8440), .B(n8439), .CI(n8438), .CO(n8464), .S(n8443) );
ADDFHX2TS U4665 ( .A(n7139), .B(n7138), .CI(n7137), .CO(n7175), .S(n7140) );
OAI21X1TS U4666 ( .A0(n8931), .A1(n1534), .B0(n1532), .Y(n7137) );
INVX2TS U4667 ( .A(n7099), .Y(n1534) );
OAI21X1TS U4668 ( .A0(n1533), .A1(n7099), .B0(n7098), .Y(n1532) );
ADDFHX2TS U4669 ( .A(n7587), .B(n7586), .CI(n7585), .CO(n7571), .S(n7674) );
NAND2BXLTS U4670 ( .AN(Data_A_i[14]), .B(n254), .Y(n3903) );
NAND2BXLTS U4671 ( .AN(n627), .B(n361), .Y(n2689) );
XOR2XLTS U4672 ( .A(n2660), .B(n2681), .Y(n2661) );
XNOR2X1TS U4673 ( .A(n7472), .B(n139), .Y(n2892) );
ADDFHX2TS U4674 ( .A(n3021), .B(n3020), .CI(n3019), .CO(n2980), .S(n3058) );
INVX2TS U4675 ( .A(n747), .Y(n3718) );
XNOR2X1TS U4676 ( .A(n710), .B(n3211), .Y(n3208) );
XNOR2X1TS U4677 ( .A(n3212), .B(n3213), .Y(n710) );
OAI2BB1X1TS U4678 ( .A0N(n3213), .A1N(n3212), .B0(n1515), .Y(n3331) );
OR2X1TS U4679 ( .A(n5985), .B(n5984), .Y(n8080) );
XOR2X1TS U4680 ( .A(n3972), .B(n4368), .Y(n4365) );
AO21X1TS U4681 ( .A0(n356), .A1(n605), .B0(n329), .Y(n6376) );
OAI2BB1X2TS U4682 ( .A0N(n6432), .A1N(n6431), .B0(n1664), .Y(n6612) );
OAI21X1TS U4683 ( .A0(n6431), .A1(n6432), .B0(n6430), .Y(n1664) );
NOR2XLTS U4684 ( .A(n6599), .B(n535), .Y(n6633) );
OAI2BB1X2TS U4685 ( .A0N(n5028), .A1N(n5027), .B0(n1297), .Y(n6669) );
NAND2X1TS U4686 ( .A(n1303), .B(n9471), .Y(n1302) );
NAND2BX1TS U4687 ( .AN(n9472), .B(n9470), .Y(n1303) );
NOR2X1TS U4688 ( .A(n1305), .B(n9472), .Y(n1304) );
OAI21XLTS U4689 ( .A0(n9449), .A1(n8209), .B0(n8208), .Y(n791) );
NOR2X4TS U4690 ( .A(n5836), .B(n5835), .Y(n7209) );
OAI21XLTS U4691 ( .A0(n1765), .A1(n1766), .B0(n1764), .Y(n703) );
XOR2X1TS U4692 ( .A(n1766), .B(n1765), .Y(n704) );
INVX2TS U4693 ( .A(n6270), .Y(n1644) );
NOR2X4TS U4694 ( .A(n5324), .B(n768), .Y(n2106) );
NOR2BX2TS U4695 ( .AN(n2103), .B(n2102), .Y(n1976) );
NAND2X1TS U4696 ( .A(n5324), .B(n768), .Y(n2104) );
OAI21X1TS U4697 ( .A0(n2071), .A1(n181), .B0(n2072), .Y(n2227) );
NOR2X2TS U4698 ( .A(n5286), .B(n5315), .Y(n2102) );
NOR2BX1TS U4699 ( .AN(n1387), .B(n2066), .Y(n2071) );
ADDFX2TS U4700 ( .A(n1940), .B(n1939), .CI(n1938), .CO(n1961), .S(n1947) );
ADDHXLTS U4701 ( .A(n1860), .B(n1859), .CO(n1853), .S(n1868) );
OAI22X1TS U4702 ( .A0(n2384), .A1(n1848), .B0(n562), .B1(n1847), .Y(n1864)
);
NAND2BXLTS U4703 ( .AN(n1887), .B(n516), .Y(n1871) );
NAND2X2TS U4704 ( .A(n2148), .B(n1744), .Y(n370) );
NAND2X1TS U4705 ( .A(n9143), .B(n9142), .Y(n9144) );
NAND2X1TS U4706 ( .A(n9157), .B(n1671), .Y(n9158) );
NAND2X2TS U4707 ( .A(n1488), .B(n9142), .Y(n9135) );
NAND2BX2TS U4708 ( .AN(n9141), .B(n9130), .Y(n1488) );
INVX2TS U4709 ( .A(n2552), .Y(n1261) );
NOR2X4TS U4710 ( .A(n2462), .B(n2461), .Y(n2557) );
ADDFX2TS U4711 ( .A(n5298), .B(n5297), .CI(n5296), .CO(n5314), .S(n5289) );
OAI2BB1X1TS U4712 ( .A0N(n7751), .A1N(n7750), .B0(n1353), .Y(n7769) );
OAI21X1TS U4713 ( .A0(n7750), .A1(n7751), .B0(n7749), .Y(n1353) );
NAND2BX2TS U4714 ( .AN(n9632), .B(n1446), .Y(n1444) );
NAND2X2TS U4715 ( .A(n767), .B(n8504), .Y(n8506) );
NAND2X2TS U4716 ( .A(n8505), .B(n8095), .Y(n767) );
INVX2TS U4717 ( .A(n8503), .Y(n8095) );
NAND2X2TS U4718 ( .A(n5925), .B(n5926), .Y(n8504) );
NOR2XLTS U4719 ( .A(n7783), .B(n363), .Y(n7959) );
INVX2TS U4720 ( .A(n7767), .Y(n7949) );
INVX2TS U4721 ( .A(n8519), .Y(n6013) );
AOI21X1TS U4722 ( .A0(n868), .A1(n4421), .B0(n4427), .Y(n4292) );
NAND2X1TS U4723 ( .A(n4308), .B(n4307), .Y(n4309) );
INVX2TS U4724 ( .A(n4310), .Y(n4312) );
XOR2X1TS U4725 ( .A(n1244), .B(n4330), .Y(n4354) );
AOI21X1TS U4726 ( .A0(n4347), .A1(n4326), .B0(n4325), .Y(n1244) );
INVX2TS U4727 ( .A(n4331), .Y(n4333) );
NAND2BX2TS U4728 ( .AN(n1040), .B(n4976), .Y(n4345) );
OAI2BB1X2TS U4729 ( .A0N(n4112), .A1N(n4111), .B0(n859), .Y(n4457) );
CLKBUFX2TS U4730 ( .A(n3514), .Y(n3436) );
CLKAND2X2TS U4731 ( .A(n11428), .B(n11431), .Y(n9863) );
CLKAND2X2TS U4732 ( .A(n11428), .B(n11427), .Y(n9872) );
CLKAND2X2TS U4733 ( .A(n9735), .B(n11351), .Y(n9878) );
OR2X1TS U4734 ( .A(n9743), .B(n9830), .Y(n9746) );
CLKAND2X2TS U4735 ( .A(n10965), .B(n10977), .Y(n9915) );
NOR2XLTS U4736 ( .A(n9889), .B(n11424), .Y(n9840) );
OAI21XLTS U4737 ( .A0(n9873), .A1(n11424), .B0(n9838), .Y(n9839) );
NAND2BXLTS U4738 ( .AN(n10325), .B(n10324), .Y(n10327) );
CLKAND2X2TS U4739 ( .A(n10341), .B(n10338), .Y(n10026) );
AO21XLTS U4740 ( .A0(n9786), .A1(n10862), .B0(n9785), .Y(n10868) );
CLKAND2X2TS U4741 ( .A(n10737), .B(n10747), .Y(n10322) );
OR2X1TS U4742 ( .A(n10627), .B(n10284), .Y(n10560) );
INVX2TS U4743 ( .A(n2235), .Y(n2237) );
OAI2BB1X2TS U4744 ( .A0N(n6871), .A1N(n193), .B0(n6870), .Y(n6872) );
OAI2BB1X1TS U4745 ( .A0N(n1589), .A1N(n1590), .B0(n7160), .Y(n1585) );
OAI2BB1X1TS U4746 ( .A0N(n8362), .A1N(n939), .B0(n937), .Y(n8493) );
OAI2BB1X2TS U4747 ( .A0N(n8696), .A1N(n8695), .B0(n655), .Y(n8743) );
INVX2TS U4748 ( .A(n8815), .Y(n7630) );
XOR2X1TS U4749 ( .A(n7882), .B(n7883), .Y(n1084) );
ADDFHX2TS U4750 ( .A(n7889), .B(n7888), .CI(n7887), .CO(n7903), .S(n7900) );
OAI2BB1X1TS U4751 ( .A0N(n7898), .A1N(n7897), .B0(n825), .Y(n7893) );
OAI2BB1X1TS U4752 ( .A0N(n7886), .A1N(n7885), .B0(n687), .Y(n7895) );
OAI2BB1X1TS U4753 ( .A0N(n7901), .A1N(n7900), .B0(n786), .Y(n7934) );
OAI21X1TS U4754 ( .A0(n7900), .A1(n7901), .B0(n7899), .Y(n786) );
OAI2BB1X2TS U4755 ( .A0N(n8637), .A1N(n8636), .B0(n1469), .Y(n8693) );
ADDFHX2TS U4756 ( .A(n8830), .B(n8639), .CI(n8638), .CO(n8643), .S(n8617) );
XNOR2X2TS U4757 ( .A(n1158), .B(n8635), .Y(n1157) );
XNOR2X1TS U4758 ( .A(n8636), .B(n8637), .Y(n1158) );
OAI21X2TS U4759 ( .A0(n8645), .A1(n8646), .B0(n8644), .Y(n1224) );
OAI2BB1X1TS U4760 ( .A0N(n7665), .A1N(n7664), .B0(n1125), .Y(n7682) );
OAI2BB1X1TS U4761 ( .A0N(n7883), .A1N(n7882), .B0(n1083), .Y(n7680) );
OAI21X1TS U4762 ( .A0(n7664), .A1(n7665), .B0(n7663), .Y(n1125) );
XNOR2X1TS U4763 ( .A(n1582), .B(n8437), .Y(n8419) );
XNOR2X1TS U4764 ( .A(n8942), .B(n8943), .Y(n1582) );
XNOR2X1TS U4765 ( .A(n1580), .B(n7127), .Y(n7124) );
XOR2X1TS U4766 ( .A(n8934), .B(n7128), .Y(n1580) );
ADDFHX2TS U4767 ( .A(n7157), .B(n7156), .CI(n7155), .CO(n8442), .S(n7173) );
NAND2X2TS U4768 ( .A(n1212), .B(n6267), .Y(n5088) );
INVX2TS U4769 ( .A(n6268), .Y(n5086) );
OR2X1TS U4770 ( .A(n5024), .B(n5023), .Y(n5025) );
ADDFHX2TS U4771 ( .A(n3195), .B(n3194), .CI(n3193), .CO(n8791), .S(n8789) );
NAND2X1TS U4772 ( .A(n2671), .B(n2669), .Y(n1733) );
INVX2TS U4773 ( .A(n2701), .Y(n928) );
XOR2X1TS U4774 ( .A(n787), .B(n7900), .Y(n7932) );
NAND2X1TS U4775 ( .A(n7873), .B(n7872), .Y(n7876) );
AOI21X2TS U4776 ( .A0(n7844), .A1(n7843), .B0(n7842), .Y(n7940) );
NAND2BX2TS U4777 ( .AN(n3061), .B(n1136), .Y(n7269) );
INVX2TS U4778 ( .A(n3060), .Y(n1136) );
AO21X1TS U4779 ( .A0(n8425), .A1(n417), .B0(n501), .Y(n8452) );
NAND2X1TS U4780 ( .A(n3059), .B(n3058), .Y(n7700) );
AO21XLTS U4781 ( .A0(n140), .A1(n539), .B0(n7103), .Y(n7153) );
XOR2X1TS U4782 ( .A(n7149), .B(n7150), .Y(n678) );
CLKAND2X2TS U4783 ( .A(n1361), .B(n8077), .Y(n219) );
INVX2TS U4784 ( .A(n8085), .Y(n766) );
NAND2X1TS U4785 ( .A(n4365), .B(n998), .Y(n7275) );
NOR2X2TS U4786 ( .A(n4365), .B(n998), .Y(n7274) );
NOR2XLTS U4787 ( .A(n6985), .B(n6974), .Y(n7281) );
NAND2X1TS U4788 ( .A(n6623), .B(n6622), .Y(n7391) );
NOR2X4TS U4789 ( .A(n6612), .B(n6611), .Y(n8371) );
OAI21X1TS U4790 ( .A0(n8368), .A1(n8542), .B0(n8543), .Y(n8369) );
NOR2X4TS U4791 ( .A(n901), .B(n6610), .Y(n8542) );
XOR2X1TS U4792 ( .A(n6637), .B(n6636), .Y(n6638) );
OAI21X1TS U4793 ( .A0(n1620), .A1(n7912), .B0(n1616), .Y(n6675) );
AOI21X1TS U4794 ( .A0(n8205), .A1(n6603), .B0(n6626), .Y(n1616) );
XOR2X1TS U4795 ( .A(n7930), .B(n7929), .Y(n8497) );
INVX2TS U4796 ( .A(n8047), .Y(n720) );
INVX2TS U4797 ( .A(n8407), .Y(n4939) );
OR2X1TS U4798 ( .A(n8016), .B(n8015), .Y(n8017) );
NAND2X1TS U4799 ( .A(n2399), .B(n2398), .Y(n2401) );
INVX2TS U4800 ( .A(n2397), .Y(n2399) );
INVX2TS U4801 ( .A(n2555), .Y(n2331) );
ADDFHX2TS U4802 ( .A(n9235), .B(n9234), .CI(n9233), .CO(n9217), .S(n9241) );
OAI22X1TS U4803 ( .A0(n1923), .A1(n1892), .B0(n1891), .B1(n1920), .Y(n1901)
);
NAND2X1TS U4804 ( .A(n9295), .B(n9293), .Y(n9271) );
OAI21X1TS U4805 ( .A0(n9632), .A1(n6804), .B0(n9636), .Y(n6749) );
OR2X1TS U4806 ( .A(n6003), .B(n6002), .Y(n9640) );
INVX2TS U4807 ( .A(n6693), .Y(n6005) );
INVX2TS U4808 ( .A(n8189), .Y(n1360) );
NOR2X2TS U4809 ( .A(n4931), .B(n4930), .Y(n7244) );
NAND2X1TS U4810 ( .A(n4931), .B(n4930), .Y(n7245) );
NAND2X1TS U4811 ( .A(n4364), .B(n4363), .Y(n7272) );
NAND2X2TS U4812 ( .A(n4354), .B(n4353), .Y(n8162) );
NAND2X1TS U4813 ( .A(n1396), .B(n4355), .Y(n8147) );
INVX2TS U4814 ( .A(n8146), .Y(n8148) );
NAND2X1TS U4815 ( .A(n4803), .B(n4829), .Y(n9126) );
NOR2X1TS U4816 ( .A(n4485), .B(n4457), .Y(n9169) );
NOR2BX1TS U4817 ( .AN(n9471), .B(n9472), .Y(n1573) );
NAND2BX2TS U4818 ( .AN(n4935), .B(n862), .Y(n8408) );
CLKAND2X2TS U4819 ( .A(n9835), .B(n9834), .Y(n9836) );
OR2X1TS U4820 ( .A(n9833), .B(n9832), .Y(n9835) );
NOR2XLTS U4821 ( .A(n9889), .B(n9890), .Y(n9896) );
CLKAND2X2TS U4822 ( .A(n9899), .B(n9898), .Y(n9900) );
NAND2X1TS U4823 ( .A(n9246), .B(n9245), .Y(n9346) );
NOR2XLTS U4824 ( .A(n9697), .B(n9673), .Y(n9612) );
INVX2TS U4825 ( .A(n834), .Y(n8843) );
INVX2TS U4826 ( .A(DP_OP_59J6_122_190_n135), .Y(n8888) );
NAND2X2TS U4827 ( .A(n5022), .B(n5021), .Y(n7978) );
NAND2X1TS U4828 ( .A(n8775), .B(n8774), .Y(n8889) );
NAND2BX2TS U4829 ( .AN(n1380), .B(n9071), .Y(n9072) );
NAND2X1TS U4830 ( .A(n8180), .B(n8179), .Y(n9063) );
OAI2BB1X1TS U4831 ( .A0N(n9330), .A1N(n9329), .B0(n763), .Y(n8179) );
OAI2BB1X1TS U4832 ( .A0N(n765), .A1N(n764), .B0(n9328), .Y(n763) );
NOR2XLTS U4833 ( .A(n9430), .B(n7227), .Y(n3707) );
NAND2X1TS U4834 ( .A(n1196), .B(n9463), .Y(n9466) );
AO21XLTS U4835 ( .A0(n9527), .A1(n9526), .B0(n9525), .Y(n9528) );
OAI21XLTS U4836 ( .A0(n9524), .A1(n9523), .B0(n9522), .Y(n9525) );
AOI21X1TS U4837 ( .A0(n6627), .A1(n6674), .B0(n6675), .Y(n1624) );
NAND2X1TS U4838 ( .A(n9484), .B(n9485), .Y(n9503) );
NAND2X2TS U4839 ( .A(n9445), .B(n9444), .Y(n9500) );
INVX2TS U4840 ( .A(n6346), .Y(n9488) );
INVX2TS U4841 ( .A(n9512), .Y(n9486) );
OR2X4TS U4842 ( .A(n8068), .B(n8067), .Y(n8390) );
NAND2X2TS U4843 ( .A(n1540), .B(n1539), .Y(n8537) );
INVX2TS U4844 ( .A(n1547), .Y(n1546) );
NAND2BX2TS U4845 ( .AN(n929), .B(n2402), .Y(n7258) );
NOR2X2TS U4846 ( .A(n9335), .B(n9334), .Y(n9352) );
NAND2BX2TS U4847 ( .AN(n1428), .B(n9335), .Y(n9351) );
INVX2TS U4848 ( .A(n9334), .Y(n1428) );
NAND2X1TS U4849 ( .A(n9305), .B(n9304), .Y(n9377) );
OR2X4TS U4850 ( .A(n9305), .B(n9304), .Y(n9378) );
OR2X1TS U4851 ( .A(n2198), .B(n2173), .Y(n9118) );
INVX2TS U4852 ( .A(n8120), .Y(n8535) );
NOR2X1TS U4853 ( .A(n9649), .B(add_x_2_n166), .Y(n9654) );
NAND2X1TS U4854 ( .A(n6026), .B(n6025), .Y(n9653) );
OAI21XLTS U4855 ( .A0(n9684), .A1(n9683), .B0(n9682), .Y(n9685) );
OR2X1TS U4856 ( .A(n9690), .B(n1697), .Y(n9692) );
OA21XLTS U4857 ( .A0(n8187), .A1(n8186), .B0(n8185), .Y(n8188) );
INVX2TS U4858 ( .A(n9664), .Y(n8528) );
NAND2X1TS U4859 ( .A(n7696), .B(n1197), .Y(n7697) );
XOR2X1TS U4860 ( .A(n8165), .B(n8164), .Y(n11227) );
INVX2TS U4861 ( .A(n8145), .Y(n8165) );
NAND2X1TS U4862 ( .A(n8163), .B(n8162), .Y(n8164) );
INVX2TS U4863 ( .A(n9288), .Y(n9290) );
NOR2X1TS U4864 ( .A(n1433), .B(n1432), .Y(n11222) );
INVX2TS U4865 ( .A(n9291), .Y(n1433) );
INVX2TS U4866 ( .A(n9513), .Y(n9483) );
INVX2TS U4867 ( .A(n9710), .Y(n1013) );
CLKAND2X2TS U4868 ( .A(n10903), .B(n11552), .Y(n10905) );
CLKAND2X2TS U4869 ( .A(n10833), .B(n10832), .Y(n10834) );
XOR2XLTS U4870 ( .A(n10855), .B(n10842), .Y(n10843) );
NOR2XLTS U4871 ( .A(n10841), .B(n10844), .Y(n10842) );
XOR2XLTS U4872 ( .A(n9731), .B(n9730), .Y(n9732) );
CLKAND2X2TS U4873 ( .A(n9786), .B(n9784), .Y(n9730) );
AO21XLTS U4874 ( .A0(n10871), .A1(n10864), .B0(n10862), .Y(n9731) );
XOR2XLTS U4875 ( .A(n10877), .B(n10876), .Y(n10878) );
OR2X1TS U4876 ( .A(n10875), .B(n10874), .Y(n10876) );
OR2X1TS U4877 ( .A(n10930), .B(n10929), .Y(n10931) );
AO21XLTS U4878 ( .A0(n10927), .A1(n10926), .B0(n10925), .Y(n10932) );
XOR2XLTS U4879 ( .A(n10941), .B(n10940), .Y(n10942) );
OR2X1TS U4880 ( .A(n10939), .B(n10938), .Y(n10940) );
XOR2XLTS U4881 ( .A(n10923), .B(n10922), .Y(n10924) );
OR2X1TS U4882 ( .A(n10921), .B(n10920), .Y(n10922) );
CLKAND2X2TS U4883 ( .A(n10953), .B(n10951), .Y(n10943) );
XOR2XLTS U4884 ( .A(n11007), .B(n11006), .Y(n11008) );
XOR2XLTS U4885 ( .A(n11015), .B(n11014), .Y(n11016) );
OR2X1TS U4886 ( .A(n11013), .B(n11012), .Y(n11014) );
XOR2XLTS U4887 ( .A(n9944), .B(n9943), .Y(n9945) );
XOR2XLTS U4888 ( .A(n10567), .B(n1702), .Y(n10568) );
NAND2X1TS U4889 ( .A(n9279), .B(n9278), .Y(n9281) );
NOR2XLTS U4890 ( .A(n9672), .B(n1726), .Y(add_x_2_n81) );
NAND2X1TS U4891 ( .A(n9398), .B(n9397), .Y(n9399) );
NOR2XLTS U4892 ( .A(n9383), .B(n9382), .Y(n8966) );
NOR2XLTS U4893 ( .A(n9383), .B(n8959), .Y(n8961) );
XOR2XLTS U4894 ( .A(n8945), .B(n8944), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[26]) );
NOR2XLTS U4895 ( .A(n9383), .B(n8939), .Y(n8941) );
XOR2XLTS U4896 ( .A(n8979), .B(n8978), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[20]) );
NAND2X1TS U4897 ( .A(n1216), .B(n1553), .Y(n11234) );
XOR2XLTS U4898 ( .A(n9009), .B(n9008), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[17]) );
INVX2TS U4899 ( .A(DP_OP_59J6_122_190_n176), .Y(DP_OP_59J6_122_190_n170) );
OAI21X1TS U4900 ( .A0(DP_OP_59J6_122_190_n158), .A1(n9057), .B0(n9056), .Y(
DP_OP_59J6_122_190_n147) );
NAND2X1TS U4901 ( .A(n11300), .B(n8910), .Y(n676) );
NOR2XLTS U4902 ( .A(DP_OP_59J6_122_190_n153), .B(n9057), .Y(
DP_OP_59J6_122_190_n146) );
INVX2TS U4903 ( .A(n8892), .Y(n8894) );
NAND2X1TS U4904 ( .A(DP_OP_59J6_122_190_n167), .B(n8756), .Y(
DP_OP_59J6_122_190_n57) );
NAND2X1TS U4905 ( .A(DP_OP_59J6_122_190_n305), .B(DP_OP_59J6_122_190_n176),
.Y(DP_OP_59J6_122_190_n58) );
NAND2X1TS U4906 ( .A(n7977), .B(n5091), .Y(n5092) );
INVX2TS U4907 ( .A(n7979), .Y(n5091) );
XOR2XLTS U4908 ( .A(n9055), .B(n9054), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[2]) );
OAI21XLTS U4909 ( .A0(n9059), .A1(n9060), .B0(n801), .Y(n800) );
XNOR2X1TS U4910 ( .A(n8909), .B(n8908), .Y(
EVEN1_middle_RECURSIVE_EVEN1_S_B[11]) );
NAND2X1TS U4911 ( .A(n8907), .B(n8906), .Y(n8908) );
INVX2TS U4912 ( .A(n8905), .Y(n8907) );
XOR2XLTS U4913 ( .A(n8918), .B(n1068), .Y(
EVEN1_middle_RECURSIVE_EVEN1_S_B[9]) );
NAND2X1TS U4914 ( .A(n8917), .B(n8916), .Y(n8918) );
INVX2TS U4915 ( .A(n9359), .Y(n7384) );
OAI2BB1X1TS U4916 ( .A0N(n8676), .A1N(n1029), .B0(n1028), .Y(
DP_OP_62J6_125_4796_n562) );
NAND2X1TS U4917 ( .A(n8220), .B(n9509), .Y(add_x_3_n8) );
NOR2XLTS U4918 ( .A(n9536), .B(add_x_3_n166), .Y(add_x_3_n164) );
INVX2TS U4919 ( .A(n9502), .Y(add_x_3_n153) );
NAND2X1TS U4920 ( .A(n8679), .B(n8678), .Y(add_x_3_n10) );
INVX2TS U4921 ( .A(n8677), .Y(n8679) );
NAND2X1TS U4922 ( .A(n9504), .B(n9503), .Y(add_x_3_n17) );
NAND2X1TS U4923 ( .A(n7404), .B(add_x_3_n141), .Y(add_x_3_n9) );
INVX2TS U4924 ( .A(n8684), .Y(add_x_3_n143) );
OAI21X2TS U4925 ( .A0(n9502), .A1(n8677), .B0(n8678), .Y(add_x_3_n144) );
NAND2X1TS U4926 ( .A(n7224), .B(n8065), .Y(n7225) );
INVX2TS U4927 ( .A(n8066), .Y(n7224) );
INVX2TS U4928 ( .A(n9360), .Y(n9364) );
INVX2TS U4929 ( .A(n8473), .Y(n8475) );
OAI21XLTS U4930 ( .A0(n9085), .A1(n9081), .B0(n9082), .Y(n9080) );
NAND2BX1TS U4931 ( .AN(n8380), .B(n8381), .Y(n1417) );
INVX2TS U4932 ( .A(n9362), .Y(n1419) );
NAND2X1TS U4933 ( .A(n8133), .B(n8132), .Y(n8134) );
XOR2XLTS U4934 ( .A(n8654), .B(n8653), .Y(EVEN1_Q_left[4]) );
NAND2BX1TS U4935 ( .AN(n9545), .B(DP_OP_62J6_125_4796_n642), .Y(n11557) );
AND2X2TS U4936 ( .A(n4546), .B(n4550), .Y(EVEN1_Q_left[1]) );
XNOR2X1TS U4937 ( .A(n7975), .B(n7974), .Y(EVEN1_Q_left[3]) );
NAND2X1TS U4938 ( .A(n212), .B(n7973), .Y(n7975) );
OAI21XLTS U4939 ( .A0(n9406), .A1(n9403), .B0(n9404), .Y(n9341) );
INVX2TS U4940 ( .A(n9337), .Y(n9339) );
INVX2TS U4941 ( .A(n9366), .Y(n7187) );
INVX2TS U4942 ( .A(n9667), .Y(n9552) );
INVX2TS U4943 ( .A(n9629), .Y(add_x_2_n303) );
CLKAND2X2TS U4944 ( .A(n9656), .B(n9655), .Y(n11561) );
INVX2TS U4945 ( .A(add_x_2_n172), .Y(add_x_2_n174) );
NAND2BX1TS U4946 ( .AN(add_x_2_n166), .B(add_x_2_n169), .Y(add_x_2_n13) );
CLKAND2X2TS U4947 ( .A(add_x_2_n52), .B(n9709), .Y(n1724) );
NOR2XLTS U4948 ( .A(n9584), .B(n9585), .Y(n9588) );
NAND2X1TS U4949 ( .A(n9663), .B(n9662), .Y(add_x_2_n16) );
INVX2TS U4950 ( .A(n9661), .Y(n9662) );
NAND2X1TS U4951 ( .A(n9651), .B(n9650), .Y(add_x_2_n12) );
NAND2X1TS U4952 ( .A(n9625), .B(add_x_2_n118), .Y(add_x_2_n6) );
OAI21X1TS U4953 ( .A0(n9630), .A1(n8496), .B0(n8495), .Y(add_x_2_n144) );
NAND2BX2TS U4954 ( .AN(n7250), .B(n1553), .Y(n10814) );
NAND2X1TS U4955 ( .A(n1554), .B(n1553), .Y(n11230) );
CLKAND2X2TS U4956 ( .A(n10847), .B(n10846), .Y(n10848) );
OR2X1TS U4957 ( .A(n10857), .B(n10856), .Y(n10858) );
XOR2X4TS U4958 ( .A(n2414), .B(n164), .Y(n2421) );
NAND2X1TS U4959 ( .A(n2416), .B(n2414), .Y(n165) );
NAND2X1TS U4960 ( .A(n2415), .B(n2414), .Y(n166) );
NAND2X1TS U4961 ( .A(n2415), .B(n2416), .Y(n167) );
BUFX3TS U4962 ( .A(n5117), .Y(n538) );
OAI2BB1X1TS U4963 ( .A0N(n9069), .A1N(n9068), .B0(n1005), .Y(n9070) );
INVX2TS U4964 ( .A(n8729), .Y(n1014) );
NAND2X1TS U4965 ( .A(n8748), .B(n8746), .Y(n170) );
NAND3X2TS U4966 ( .A(n170), .B(n169), .C(n171), .Y(n8754) );
ADDFHX2TS U4967 ( .A(n3024), .B(n3023), .CI(n3022), .CO(n3016), .S(n3056) );
ADDFX2TS U4968 ( .A(n3615), .B(n3614), .CI(n3613), .CO(n3619), .S(n3596) );
OAI22X1TS U4969 ( .A0(n372), .A1(n3466), .B0(n572), .B1(n3601), .Y(n3614) );
INVX2TS U4970 ( .A(n8228), .Y(n7129) );
ADDFHX2TS U4971 ( .A(n8466), .B(n8465), .CI(n8464), .CO(n8852), .S(n8445) );
OAI2BB1X1TS U4972 ( .A0N(n1603), .A1N(n1604), .B0(n8456), .Y(n1601) );
XNOR2X1TS U4973 ( .A(n8428), .B(n404), .Y(n7071) );
XNOR2X1TS U4974 ( .A(n8428), .B(n380), .Y(n7159) );
NOR2X2TS U4975 ( .A(n9260), .B(n9259), .Y(n9408) );
NOR2X4TS U4976 ( .A(n172), .B(n8168), .Y(n173) );
NOR2X4TS U4977 ( .A(n173), .B(n3590), .Y(n3592) );
INVX2TS U4978 ( .A(n3591), .Y(n172) );
NAND2X2TS U4979 ( .A(n6975), .B(n6980), .Y(n830) );
OAI21X1TS U4980 ( .A0(n9352), .A1(n9371), .B0(n9351), .Y(n9353) );
NOR2XLTS U4981 ( .A(n9352), .B(n9370), .Y(n9355) );
AOI21X2TS U4982 ( .A0(n3546), .A1(n9174), .B0(n3545), .Y(n9155) );
NAND2BX1TS U4983 ( .AN(n5497), .B(n247), .Y(n2204) );
XOR2X1TS U4984 ( .A(n1506), .B(n5552), .Y(n5701) );
OAI2BB1X2TS U4985 ( .A0N(n7819), .A1N(n7818), .B0(n1527), .Y(n7873) );
INVX2TS U4986 ( .A(n8724), .Y(n8457) );
ADDFHX2TS U4987 ( .A(n3955), .B(n3954), .CI(n3953), .CO(n3884), .S(n3968) );
OR2X8TS U4988 ( .A(n6791), .B(n6790), .Y(n6807) );
OAI2BB1X2TS U4989 ( .A0N(n5271), .A1N(n5512), .B0(n5270), .Y(n5508) );
NAND2BXLTS U4990 ( .AN(n5510), .B(n5269), .Y(n5271) );
AND2X4TS U4991 ( .A(n954), .B(n2023), .Y(n214) );
NAND3BX1TS U4992 ( .AN(n2022), .B(n969), .C(n531), .Y(n954) );
OAI21X2TS U4993 ( .A0(n423), .A1(n5528), .B0(n1365), .Y(n5510) );
NAND2BX2TS U4994 ( .AN(n5322), .B(n489), .Y(n1365) );
INVX4TS U4995 ( .A(n6003), .Y(n5781) );
OAI22X1TS U4996 ( .A0(n5279), .A1(n490), .B0(n5323), .B1(n423), .Y(n5275) );
OAI2BB1X2TS U4997 ( .A0N(n6976), .A1N(n6965), .B0(n1108), .Y(n6975) );
ADDFHX2TS U4998 ( .A(n1993), .B(n1992), .CI(n1991), .CO(n2124), .S(n1985) );
OAI22X1TS U4999 ( .A0(n1984), .A1(n1826), .B0(n693), .B1(n1982), .Y(n1991)
);
INVX2TS U5000 ( .A(n5825), .Y(n5826) );
XOR2X1TS U5001 ( .A(n8856), .B(n433), .Y(n8279) );
NAND2X1TS U5002 ( .A(n1594), .B(n3340), .Y(n1133) );
OAI2BB1X2TS U5003 ( .A0N(n3359), .A1N(n1594), .B0(n3260), .Y(n1600) );
XNOR2X4TS U5004 ( .A(n2266), .B(n2261), .Y(n2265) );
XNOR2X1TS U5005 ( .A(n5620), .B(n5145), .Y(n5322) );
XOR2X4TS U5006 ( .A(n3677), .B(n3202), .Y(n3181) );
NAND2X4TS U5007 ( .A(n8382), .B(n8390), .Y(n1285) );
INVX4TS U5008 ( .A(n7517), .Y(n358) );
XNOR2X1TS U5009 ( .A(n9314), .B(n9271), .Y(n9301) );
NAND2X4TS U5010 ( .A(n1511), .B(n1510), .Y(n9314) );
INVX4TS U5011 ( .A(n1492), .Y(n3467) );
XOR2X1TS U5012 ( .A(n4064), .B(n4063), .Y(n4182) );
NOR2X2TS U5013 ( .A(n4829), .B(n4803), .Y(n9125) );
OAI21X2TS U5014 ( .A0(n1437), .A1(n1439), .B0(n1435), .Y(n5117) );
OAI21X4TS U5015 ( .A0(n6014), .A1(n8519), .B0(n6015), .Y(n6746) );
ADDHX1TS U5016 ( .A(n3878), .B(n3877), .CO(n3899), .S(n3892) );
ADDFHX2TS U5017 ( .A(n3897), .B(n3896), .CI(n3895), .CO(n3956), .S(n3960) );
AO21X1TS U5018 ( .A0(n4279), .A1(n1021), .B0(n621), .Y(n6590) );
OAI22X1TS U5019 ( .A0(n4279), .A1(n3987), .B0(n1021), .B1(n3986), .Y(n3998)
);
OAI22X1TS U5020 ( .A0(n4279), .A1(n4775), .B0(n4881), .B1(n4791), .Y(n4792)
);
OAI22X1TS U5021 ( .A0(n4279), .A1(n621), .B0(n4881), .B1(n4004), .Y(n4014)
);
OAI21XLTS U5022 ( .A0(n7934), .A1(n7935), .B0(n1152), .Y(n1151) );
XNOR2X1TS U5023 ( .A(n8277), .B(n443), .Y(n8574) );
XNOR2X2TS U5024 ( .A(n8228), .B(n443), .Y(n8575) );
XNOR2X1TS U5025 ( .A(n7593), .B(n443), .Y(n7650) );
XNOR2X4TS U5026 ( .A(n8049), .B(n8048), .Y(n8068) );
NAND2X4TS U5027 ( .A(n857), .B(n858), .Y(n4209) );
ADDFHX4TS U5028 ( .A(n7871), .B(n7870), .CI(n7869), .CO(n7931), .S(n7872) );
NOR2X2TS U5029 ( .A(n1468), .B(n217), .Y(n8325) );
INVX2TS U5030 ( .A(n7709), .Y(n3057) );
XNOR2X2TS U5031 ( .A(n7271), .B(n7270), .Y(n7704) );
XNOR2X1TS U5032 ( .A(n7591), .B(n375), .Y(n3015) );
XNOR2X2TS U5033 ( .A(n2742), .B(n2741), .Y(n7591) );
OAI21X1TS U5034 ( .A0(n2738), .A1(n2737), .B0(n2748), .Y(n2742) );
ADDFHX2TS U5035 ( .A(n3882), .B(n3881), .CI(n3880), .CO(n4369), .S(n3965) );
OR2X4TS U5036 ( .A(n4359), .B(n4358), .Y(n1197) );
XNOR2X4TS U5037 ( .A(n7705), .B(n11188), .Y(n875) );
ADDFHX2TS U5038 ( .A(n3822), .B(n3821), .CI(n3820), .CO(n4411), .S(n3883) );
OAI21X2TS U5039 ( .A0(n8739), .A1(n8740), .B0(n8738), .Y(n1223) );
OAI21X1TS U5040 ( .A0(n8695), .A1(n8696), .B0(n8694), .Y(n655) );
INVX2TS U5041 ( .A(n4913), .Y(n4915) );
XOR2X4TS U5042 ( .A(n8539), .B(n8538), .Y(EVEN1_Q_right[31]) );
ADDFHX2TS U5043 ( .A(n5074), .B(n5073), .CI(n5072), .CO(n6210), .S(n5077) );
NOR2X4TS U5044 ( .A(n8107), .B(n8106), .Y(DP_OP_59J6_122_190_n135) );
INVX2TS U5045 ( .A(n7179), .Y(n1530) );
CLKXOR2X2TS U5046 ( .A(n2683), .B(n2682), .Y(n8233) );
ADDFHX4TS U5047 ( .A(n7637), .B(n7636), .CI(n7635), .CO(n8644), .S(n8877) );
ADDFHX2TS U5048 ( .A(n7626), .B(n7627), .CI(n7628), .CO(n8603), .S(n7637) );
INVX6TS U5049 ( .A(n8323), .Y(n612) );
XNOR2X4TS U5050 ( .A(n3274), .B(n816), .Y(n8323) );
OAI2BB1X1TS U5051 ( .A0N(n7935), .A1N(n7934), .B0(n1151), .Y(n8181) );
XNOR2X4TS U5052 ( .A(Data_B_i[36]), .B(Data_B_i[37]), .Y(n174) );
INVX4TS U5053 ( .A(n228), .Y(n416) );
INVX4TS U5054 ( .A(n6313), .Y(n589) );
INVX4TS U5055 ( .A(n7517), .Y(n359) );
INVX4TS U5056 ( .A(n7405), .Y(n7517) );
INVX2TS U5057 ( .A(n459), .Y(n460) );
NAND2X2TS U5058 ( .A(n2032), .B(n444), .Y(n2033) );
XOR2X1TS U5059 ( .A(n3321), .B(n3320), .Y(n175) );
INVX2TS U5060 ( .A(n693), .Y(n1846) );
INVX4TS U5061 ( .A(n7549), .Y(n353) );
XOR2X1TS U5062 ( .A(Data_B_i[14]), .B(Data_B_i[0]), .Y(n176) );
XOR2X1TS U5063 ( .A(n2738), .B(n2750), .Y(n2751) );
INVX2TS U5064 ( .A(n424), .Y(n426) );
INVX2TS U5065 ( .A(n8299), .Y(n719) );
INVX2TS U5066 ( .A(n518), .Y(n519) );
INVX4TS U5067 ( .A(Data_A_i[41]), .Y(n1096) );
INVX2TS U5068 ( .A(n858), .Y(n4071) );
XOR2X1TS U5069 ( .A(n2262), .B(n2263), .Y(n177) );
INVX4TS U5070 ( .A(Data_B_i[34]), .Y(n517) );
INVX4TS U5071 ( .A(n1631), .Y(n263) );
CLKINVX6TS U5072 ( .A(n318), .Y(n319) );
INVX2TS U5073 ( .A(n2760), .Y(n495) );
INVX2TS U5074 ( .A(n5145), .Y(n401) );
INVX2TS U5075 ( .A(n6493), .Y(n477) );
INVX2TS U5076 ( .A(n480), .Y(n481) );
INVX2TS U5077 ( .A(n2918), .Y(n2597) );
XNOR2X1TS U5078 ( .A(n2646), .B(n2953), .Y(n1058) );
INVX2TS U5079 ( .A(n2200), .Y(n5577) );
OA21XLTS U5080 ( .A0(n2082), .A1(n2064), .B0(n2083), .Y(n181) );
INVX2TS U5081 ( .A(n339), .Y(n340) );
INVX2TS U5082 ( .A(Data_A_i[20]), .Y(n339) );
OA21XLTS U5083 ( .A0(n4340), .A1(n3942), .B0(n4341), .Y(n183) );
XOR2X1TS U5084 ( .A(n6975), .B(n6980), .Y(n184) );
INVX2TS U5085 ( .A(n7780), .Y(n421) );
XNOR2X1TS U5086 ( .A(n2715), .B(n2714), .Y(n7420) );
INVX4TS U5087 ( .A(n1248), .Y(n610) );
AND2X4TS U5088 ( .A(n5731), .B(n2195), .Y(n5733) );
OA21XLTS U5089 ( .A0(n5166), .A1(n5187), .B0(n5188), .Y(n186) );
INVX2TS U5090 ( .A(n1567), .Y(n261) );
AND2X2TS U5091 ( .A(n746), .B(Data_B_i[13]), .Y(n187) );
XNOR2X1TS U5092 ( .A(n2638), .B(n2637), .Y(n188) );
INVX2TS U5093 ( .A(n1738), .Y(n7558) );
OAI2BB1X2TS U5094 ( .A0N(n4176), .A1N(n4175), .B0(n914), .Y(n4624) );
INVX2TS U5095 ( .A(n4624), .Y(n4705) );
XOR2X1TS U5096 ( .A(n5200), .B(n5199), .Y(n192) );
AND2X2TS U5097 ( .A(n193), .B(n6870), .Y(n195) );
XNOR2X1TS U5098 ( .A(n3087), .B(n3086), .Y(n198) );
XOR2X1TS U5099 ( .A(n2869), .B(n2868), .Y(n200) );
AND2X2TS U5100 ( .A(n1063), .B(n390), .Y(n202) );
AND2X2TS U5101 ( .A(n542), .B(Data_B_i[1]), .Y(n203) );
XOR2X1TS U5102 ( .A(Data_B_i[41]), .B(Data_B_i[27]), .Y(n204) );
XNOR2X1TS U5103 ( .A(n3136), .B(n3135), .Y(n1468) );
AND2X2TS U5104 ( .A(n7828), .B(n2648), .Y(n205) );
AND2X2TS U5105 ( .A(n614), .B(n2856), .Y(n206) );
AO21X4TS U5106 ( .A0(n8142), .A1(n8143), .B0(n3054), .Y(n208) );
OR2X1TS U5107 ( .A(n8798), .B(n8797), .Y(n209) );
INVX2TS U5108 ( .A(n1204), .Y(n6548) );
OR2X1TS U5109 ( .A(n2013), .B(n2038), .Y(n212) );
INVX2TS U5110 ( .A(n2166), .Y(n1420) );
INVX2TS U5111 ( .A(n7505), .Y(n823) );
XNOR2X1TS U5112 ( .A(n3166), .B(n3272), .Y(n217) );
NOR2X1TS U5113 ( .A(n3542), .B(n3541), .Y(n9207) );
INVX2TS U5114 ( .A(n9207), .Y(n1496) );
NAND3X6TS U5115 ( .A(n1258), .B(n1255), .C(n1256), .Y(n8243) );
NAND2X2TS U5116 ( .A(n1329), .B(n6694), .Y(n9631) );
INVX2TS U5117 ( .A(n9631), .Y(n9634) );
BUFX4TS U5118 ( .A(n1983), .Y(n693) );
AND2X4TS U5119 ( .A(n9542), .B(n9539), .Y(n220) );
INVX2TS U5120 ( .A(n4644), .Y(n1010) );
INVX4TS U5121 ( .A(n1064), .Y(n3437) );
OA21XLTS U5122 ( .A0(n9230), .A1(n9229), .B0(n9228), .Y(n221) );
INVX2TS U5123 ( .A(n6397), .Y(n451) );
NOR2X4TS U5124 ( .A(n1138), .B(n1137), .Y(n2738) );
BUFX3TS U5125 ( .A(n7145), .Y(n808) );
INVX2TS U5126 ( .A(n6164), .Y(n591) );
OA21X2TS U5127 ( .A0(n9710), .A1(n1014), .B0(n9711), .Y(n226) );
INVX2TS U5128 ( .A(n4947), .Y(n1040) );
OA21XLTS U5129 ( .A0(n1603), .A1(n1604), .B0(n1601), .Y(n227) );
NOR2X2TS U5130 ( .A(n4354), .B(n4353), .Y(n8161) );
XNOR2X4TS U5131 ( .A(n6865), .B(n1248), .Y(n228) );
AND2X4TS U5132 ( .A(n612), .B(n6982), .Y(n8322) );
INVX2TS U5133 ( .A(n8322), .Y(n411) );
INVX2TS U5134 ( .A(n8322), .Y(n410) );
XOR2X1TS U5135 ( .A(n3802), .B(n211), .Y(n230) );
INVX2TS U5136 ( .A(n4181), .Y(n1032) );
INVX2TS U5137 ( .A(n3677), .Y(n318) );
INVX2TS U5138 ( .A(n9131), .Y(n9133) );
INVX2TS U5139 ( .A(n3635), .Y(n1516) );
NOR2X1TS U5140 ( .A(Data_B_i[39]), .B(Data_B_i[12]), .Y(n3339) );
AND2X2TS U5141 ( .A(Data_B_i[45]), .B(Data_B_i[31]), .Y(n235) );
INVX2TS U5142 ( .A(n3730), .Y(n398) );
NAND2BX2TS U5143 ( .AN(n1306), .B(n4850), .Y(n6595) );
INVX2TS U5144 ( .A(n4209), .Y(n1178) );
INVX2TS U5145 ( .A(n6825), .Y(n492) );
XOR2X1TS U5146 ( .A(n5202), .B(n5201), .Y(n6825) );
INVX2TS U5147 ( .A(Data_A_i[30]), .Y(n301) );
INVX2TS U5148 ( .A(n4336), .Y(n945) );
INVX2TS U5149 ( .A(n4307), .Y(n1000) );
INVX2TS U5150 ( .A(n1096), .Y(n969) );
INVX2TS U5151 ( .A(n3541), .Y(n1489) );
NAND2X1TS U5152 ( .A(n2905), .B(n2904), .Y(n237) );
NOR2X2TS U5153 ( .A(n5846), .B(n5847), .Y(n8018) );
INVX2TS U5154 ( .A(n8018), .Y(n8020) );
INVX2TS U5155 ( .A(n9070), .Y(n1380) );
NOR2X1TS U5156 ( .A(n6175), .B(n6125), .Y(n4327) );
INVX2TS U5157 ( .A(n1169), .Y(n3362) );
NOR2X2TS U5158 ( .A(Data_B_i[37]), .B(Data_B_i[10]), .Y(n1169) );
INVX2TS U5159 ( .A(n2920), .Y(n1062) );
XNOR2X1TS U5160 ( .A(n8317), .B(n359), .Y(n1109) );
INVX2TS U5161 ( .A(n3751), .Y(n1077) );
INVX2TS U5162 ( .A(n1058), .Y(n7828) );
OR2X1TS U5163 ( .A(n10915), .B(n10914), .Y(n10916) );
INVX2TS U5164 ( .A(n11727), .Y(n1553) );
OA21X4TS U5165 ( .A0(n8120), .A1(n683), .B0(n8533), .Y(n8539) );
NAND2X1TS U5166 ( .A(n7257), .B(n7256), .Y(n7261) );
OAI21X1TS U5167 ( .A0(n8140), .A1(n8136), .B0(n8137), .Y(n8135) );
NAND2X2TS U5168 ( .A(n2495), .B(n2494), .Y(n9366) );
INVX2TS U5169 ( .A(n4544), .Y(n2049) );
OAI22X2TS U5170 ( .A0(n1887), .A1(n1923), .B0(n1889), .B1(n541), .Y(n4544)
);
INVX2TS U5171 ( .A(EVEN1_Q_left[25]), .Y(n7249) );
AOI21X2TS U5172 ( .A0(n7190), .A1(n7191), .B0(n1332), .Y(n1331) );
CLKINVX1TS U5173 ( .A(n7190), .Y(n7208) );
INVX2TS U5174 ( .A(n133), .Y(n240) );
BUFX8TS U5175 ( .A(Data_B_i[1]), .Y(n241) );
BUFX4TS U5176 ( .A(Data_B_i[15]), .Y(n242) );
NAND2X2TS U5177 ( .A(n4812), .B(Data_B_i[26]), .Y(n243) );
NAND2X2TS U5178 ( .A(n4812), .B(Data_B_i[26]), .Y(n6520) );
NAND2X2TS U5179 ( .A(n1021), .B(n1558), .Y(n244) );
NAND2X2TS U5180 ( .A(n1021), .B(n1558), .Y(n4279) );
AOI21X4TS U5181 ( .A0(n7270), .A1(n7269), .B0(n3062), .Y(n7264) );
ADDFHX4TS U5182 ( .A(n5815), .B(n5814), .CI(n5813), .CO(n5807), .S(n5832) );
INVX2TS U5183 ( .A(n5681), .Y(n5750) );
NOR2X1TS U5184 ( .A(n5681), .B(n5683), .Y(n1944) );
BUFX4TS U5185 ( .A(n2108), .Y(n762) );
OAI22X2TS U5186 ( .A0(n6907), .A1(n554), .B0(n6920), .B1(n458), .Y(n6927) );
OAI21XLTS U5187 ( .A0(n7172), .A1(n7173), .B0(n7171), .Y(n1575) );
OAI2BB1X1TS U5188 ( .A0N(n7173), .A1N(n7172), .B0(n1575), .Y(n8414) );
XNOR2X2TS U5189 ( .A(n1106), .B(n8330), .Y(n1105) );
OAI2BB1X2TS U5190 ( .A0N(n8330), .A1N(n1104), .B0(n692), .Y(n8341) );
ADDFHX2TS U5191 ( .A(n5567), .B(n5566), .CI(n5565), .CO(n5549), .S(n5601) );
OAI2BB1X2TS U5192 ( .A0N(n5560), .A1N(n5559), .B0(n705), .Y(n5597) );
NAND2X1TS U5193 ( .A(n5667), .B(n772), .Y(n771) );
NAND2X4TS U5194 ( .A(n987), .B(n989), .Y(n9452) );
NAND3X4TS U5195 ( .A(n9473), .B(n9469), .C(n1678), .Y(n989) );
NOR2BX1TS U5196 ( .AN(n8113), .B(n8112), .Y(n931) );
INVX2TS U5197 ( .A(n8383), .Y(n8071) );
ADDFHX2TS U5198 ( .A(n5857), .B(n5856), .CI(n5855), .CO(n5395), .S(n5883) );
INVX2TS U5199 ( .A(n6804), .Y(n9637) );
ADDFHX2TS U5200 ( .A(n8329), .B(n8328), .CI(n8327), .CO(n8338), .S(n8342) );
OAI22X2TS U5201 ( .A0(n8240), .A1(n552), .B0(n8238), .B1(n465), .Y(n8290) );
AOI21X2TS U5202 ( .A0(n7252), .A1(n2406), .B0(n2405), .Y(n9365) );
OAI21X1TS U5203 ( .A0(n2324), .A1(n2325), .B0(n2323), .Y(n962) );
OAI2BB1X1TS U5204 ( .A0N(n2325), .A1N(n2324), .B0(n962), .Y(n2420) );
XOR2X2TS U5205 ( .A(n2325), .B(n2324), .Y(n963) );
NOR2X4TS U5206 ( .A(n6474), .B(n8553), .Y(n8541) );
CLKINVX1TS U5207 ( .A(n5498), .Y(n5499) );
INVX2TS U5208 ( .A(n9130), .Y(n9145) );
OAI21X1TS U5209 ( .A0(n3142), .A1(n3143), .B0(n3140), .Y(n3141) );
XNOR2X2TS U5210 ( .A(n1063), .B(n2763), .Y(n3473) );
OAI21X1TS U5211 ( .A0(n6469), .A1(n6470), .B0(n6468), .Y(n736) );
AOI21X2TS U5212 ( .A0(n7687), .A1(n3705), .B0(n3704), .Y(n9431) );
XNOR2X4TS U5213 ( .A(n246), .B(n9638), .Y(n9647) );
AO21X4TS U5214 ( .A0(n9635), .A1(n9634), .B0(n9633), .Y(n246) );
OAI21X2TS U5215 ( .A0(n7941), .A1(n7940), .B0(n7939), .Y(n1150) );
AND2X4TS U5216 ( .A(n7879), .B(n7878), .Y(n8769) );
ADDFHX2TS U5217 ( .A(n3197), .B(n1489), .CI(n3196), .CO(n3250), .S(n3216) );
XOR2X2TS U5218 ( .A(n8569), .B(n1115), .Y(n8699) );
INVX2TS U5219 ( .A(n6657), .Y(n4641) );
CLKINVX1TS U5220 ( .A(DP_OP_59J6_122_190_n187), .Y(n8682) );
OAI22X2TS U5221 ( .A0(n7408), .A1(n8460), .B0(n506), .B1(n7407), .Y(n7465)
);
INVX4TS U5222 ( .A(n8573), .Y(n614) );
XOR2X2TS U5223 ( .A(n7265), .B(n7264), .Y(n7288) );
XNOR2X2TS U5224 ( .A(n2802), .B(n2801), .Y(n8573) );
OAI21X2TS U5225 ( .A0(n1538), .A1(n8533), .B0(n8536), .Y(n1712) );
OAI22X2TS U5226 ( .A0(n4665), .A1(n593), .B0(n4845), .B1(n481), .Y(n4839) );
OAI22X2TS U5227 ( .A0(n372), .A1(n3406), .B0(n3685), .B1(n3466), .Y(n3457)
);
OAI21X1TS U5228 ( .A0(n7907), .A1(n7911), .B0(n7912), .Y(n8207) );
NAND2BX2TS U5229 ( .AN(n7705), .B(n11188), .Y(n874) );
NOR2X2TS U5230 ( .A(n2097), .B(n2096), .Y(n8136) );
ADDFHX2TS U5231 ( .A(n5242), .B(n5241), .CI(n5240), .CO(n5369), .S(n5291) );
XOR2X4TS U5232 ( .A(n661), .B(n5398), .Y(n5930) );
OAI21X2TS U5233 ( .A0(n861), .A1(n8406), .B0(n8407), .Y(n7374) );
INVX2TS U5234 ( .A(n4728), .Y(n4516) );
INVX2TS U5235 ( .A(n6111), .Y(n6284) );
OAI21X1TS U5236 ( .A0(n6285), .A1(n6286), .B0(n6284), .Y(n1235) );
NOR2X1TS U5237 ( .A(n620), .B(n4242), .Y(n4261) );
ADDFHX2TS U5238 ( .A(n2225), .B(n2224), .CI(n2223), .CO(n2229), .S(n2051) );
ADDFHX4TS U5239 ( .A(n8649), .B(n8648), .CI(n8647), .CO(n8707), .S(n8760) );
ADDFHX4TS U5240 ( .A(n8622), .B(n8620), .CI(n8621), .CO(n8690), .S(n8648) );
ADDFHX4TS U5241 ( .A(n8619), .B(n8618), .CI(n8617), .CO(n8647), .S(n8765) );
NOR2X4TS U5242 ( .A(n5090), .B(n5089), .Y(n7979) );
XOR2X4TS U5243 ( .A(n935), .B(n617), .Y(n2817) );
XOR2X1TS U5244 ( .A(n8568), .B(n8567), .Y(n1115) );
INVX2TS U5245 ( .A(n1168), .Y(n1167) );
ACHCINX2TS U5246 ( .CIN(n5412), .A(n5457), .B(n5458), .CO(n5953) );
ADDFHX2TS U5247 ( .A(n5403), .B(n5402), .CI(n5401), .CO(n5446), .S(n5400) );
NAND2BX1TS U5248 ( .AN(n6854), .B(n3283), .Y(n1162) );
XNOR2X2TS U5249 ( .A(n3283), .B(n2926), .Y(n8317) );
NAND3X2TS U5250 ( .A(n1446), .B(n9635), .C(n9634), .Y(n1445) );
OAI22X2TS U5251 ( .A0(n5689), .A1(n583), .B0(n5642), .B1(n499), .Y(n5604) );
ADDFHX2TS U5252 ( .A(n8705), .B(n8704), .CI(n8703), .CO(n8735), .S(n8685) );
XOR2X2TS U5253 ( .A(n8375), .B(n8374), .Y(n9447) );
ADDFHX2TS U5254 ( .A(n4840), .B(n4839), .CI(n4838), .CO(n5000), .S(n4836) );
OAI21X1TS U5255 ( .A0(n4866), .A1(n4867), .B0(n4865), .Y(n1670) );
INVX2TS U5256 ( .A(n5225), .Y(n247) );
NOR2X4TS U5257 ( .A(n407), .B(Data_B_i[46]), .Y(n2261) );
INVX2TS U5258 ( .A(n722), .Y(n248) );
INVX2TS U5259 ( .A(Data_A_i[45]), .Y(n722) );
XOR2X1TS U5260 ( .A(n248), .B(n338), .Y(n723) );
NAND2X2TS U5261 ( .A(n2513), .B(n5573), .Y(n249) );
NAND2X2TS U5262 ( .A(n2513), .B(n5573), .Y(n250) );
OAI22X1TS U5263 ( .A0(n250), .A1(n2514), .B0(n601), .B1(n5574), .Y(n5615) );
NAND2X2TS U5264 ( .A(n2513), .B(n5573), .Y(n5575) );
INVX2TS U5265 ( .A(n1306), .Y(n251) );
OAI22X1TS U5266 ( .A0(n6132), .A1(n6594), .B0(n6055), .B1(n420), .Y(n6122)
);
INVX2TS U5267 ( .A(n1306), .Y(n6594) );
XNOR2X2TS U5268 ( .A(n245), .B(Data_A_i[28]), .Y(n1889) );
XNOR2X1TS U5269 ( .A(Data_B_i[1]), .B(Data_A_i[13]), .Y(n4003) );
NOR2X4TS U5270 ( .A(Data_B_i[28]), .B(Data_B_i[1]), .Y(n2598) );
XNOR2X1TS U5271 ( .A(n241), .B(Data_A_i[8]), .Y(n4097) );
NOR2XLTS U5272 ( .A(n254), .B(n665), .Y(n2656) );
INVX12TS U5273 ( .A(Data_B_i[9]), .Y(n1026) );
OAI22X2TS U5274 ( .A0(n5041), .A1(n4609), .B0(n1290), .B1(n4824), .Y(n4819)
);
OAI22X1TS U5275 ( .A0(n5041), .A1(n4968), .B0(n1290), .B1(n5040), .Y(n5049)
);
OAI21X2TS U5276 ( .A0(n5040), .A1(n5041), .B0(n1645), .Y(n6030) );
INVX2TS U5277 ( .A(n4156), .Y(n258) );
BUFX3TS U5278 ( .A(Data_B_i[48]), .Y(n281) );
INVX2TS U5279 ( .A(n1567), .Y(n262) );
XNOR2X1TS U5280 ( .A(n238), .B(n5223), .Y(n3085) );
INVX2TS U5281 ( .A(n1982), .Y(n515) );
INVX2TS U5282 ( .A(n1631), .Y(n521) );
INVX2TS U5283 ( .A(n1436), .Y(n264) );
INVX2TS U5284 ( .A(n188), .Y(n265) );
INVX2TS U5285 ( .A(n324), .Y(n266) );
INVX2TS U5286 ( .A(n324), .Y(n267) );
NAND2X1TS U5287 ( .A(Data_B_i[32]), .B(Data_B_i[5]), .Y(n2593) );
XOR2X4TS U5288 ( .A(Data_B_i[23]), .B(Data_B_i[22]), .Y(n4473) );
INVX2TS U5289 ( .A(Data_B_i[36]), .Y(n268) );
INVX2TS U5290 ( .A(n268), .Y(n269) );
INVX2TS U5291 ( .A(n8243), .Y(n270) );
INVX2TS U5292 ( .A(n3694), .Y(n3716) );
INVX2TS U5293 ( .A(n3716), .Y(n274) );
OAI22X2TS U5294 ( .A0(n3694), .A1(n1241), .B0(n3715), .B1(n3678), .Y(n3680)
);
NAND2X1TS U5295 ( .A(n4096), .B(n4071), .Y(n1174) );
INVX2TS U5296 ( .A(n324), .Y(n277) );
INVX2TS U5297 ( .A(n324), .Y(n278) );
INVX2TS U5298 ( .A(n4031), .Y(n279) );
INVX4TS U5299 ( .A(Data_B_i[3]), .Y(n4031) );
INVX2TS U5300 ( .A(n1982), .Y(n280) );
XNOR2X2TS U5301 ( .A(n1370), .B(Data_B_i[48]), .Y(n1369) );
INVX2TS U5302 ( .A(n4206), .Y(n283) );
INVX2TS U5303 ( .A(n4273), .Y(n285) );
BUFX3TS U5304 ( .A(Data_A_i[9]), .Y(n286) );
INVX2TS U5305 ( .A(n4774), .Y(n288) );
INVX2TS U5306 ( .A(n4790), .Y(n289) );
NAND2X1TS U5307 ( .A(Data_A_i[42]), .B(Data_A_i[15]), .Y(n2673) );
INVX2TS U5308 ( .A(n5039), .Y(n291) );
INVX2TS U5309 ( .A(n6032), .Y(n292) );
INVX2TS U5310 ( .A(n6078), .Y(n293) );
INVX2TS U5311 ( .A(n6413), .Y(n294) );
NAND2X1TS U5312 ( .A(n314), .B(Data_A_i[23]), .Y(n3311) );
NAND2X1TS U5313 ( .A(Data_A_i[23]), .B(Data_A_i[9]), .Y(n4646) );
INVX2TS U5314 ( .A(n6454), .Y(n295) );
INVX4TS U5315 ( .A(n296), .Y(n297) );
INVX2TS U5316 ( .A(n6519), .Y(n298) );
INVX2TS U5317 ( .A(n1770), .Y(n299) );
NOR2X4TS U5318 ( .A(Data_A_i[28]), .B(Data_A_i[1]), .Y(n2634) );
NAND2X2TS U5319 ( .A(Data_A_i[1]), .B(Data_A_i[28]), .Y(n2635) );
INVX2TS U5320 ( .A(n1825), .Y(n300) );
NOR2X4TS U5321 ( .A(Data_A_i[29]), .B(Data_A_i[2]), .Y(n2724) );
INVX2TS U5322 ( .A(n301), .Y(n302) );
INVX2TS U5323 ( .A(Data_A_i[32]), .Y(n303) );
INVX2TS U5324 ( .A(n2349), .Y(n305) );
INVX2TS U5325 ( .A(n2376), .Y(n306) );
INVX2TS U5326 ( .A(n2483), .Y(n307) );
XNOR2X1TS U5327 ( .A(Data_B_i[28]), .B(Data_A_i[35]), .Y(n1841) );
INVX2TS U5328 ( .A(n2577), .Y(n308) );
NAND2X2TS U5329 ( .A(Data_A_i[36]), .B(Data_A_i[9]), .Y(n3163) );
NAND2X1TS U5330 ( .A(Data_A_i[36]), .B(Data_A_i[50]), .Y(n5155) );
INVX2TS U5331 ( .A(n6711), .Y(n309) );
INVX2TS U5332 ( .A(n6765), .Y(n310) );
NAND2X1TS U5333 ( .A(Data_A_i[52]), .B(Data_A_i[38]), .Y(n5169) );
NOR2X1TS U5334 ( .A(Data_A_i[52]), .B(Data_A_i[38]), .Y(n5168) );
XNOR2X1TS U5335 ( .A(n511), .B(Data_A_i[38]), .Y(n1752) );
NAND2X1TS U5336 ( .A(Data_A_i[38]), .B(Data_A_i[11]), .Y(n3376) );
INVX2TS U5337 ( .A(n6820), .Y(n311) );
NAND2X1TS U5338 ( .A(Data_A_i[53]), .B(Data_A_i[39]), .Y(n5178) );
NOR2X1TS U5339 ( .A(Data_A_i[53]), .B(Data_A_i[39]), .Y(n5177) );
INVX2TS U5340 ( .A(n5118), .Y(n312) );
INVX2TS U5341 ( .A(n5222), .Y(n313) );
XOR2X1TS U5342 ( .A(n1338), .B(Data_A_i[46]), .Y(n2275) );
NAND2X1TS U5343 ( .A(Data_A_i[46]), .B(Data_A_i[19]), .Y(n2873) );
NAND2X1TS U5344 ( .A(Data_A_i[46]), .B(Data_A_i[32]), .Y(n2246) );
NOR2X4TS U5345 ( .A(Data_A_i[46]), .B(Data_A_i[32]), .Y(n2248) );
INVX2TS U5346 ( .A(n5472), .Y(n314) );
INVX2TS U5347 ( .A(n5966), .Y(n315) );
INVX2TS U5348 ( .A(n6726), .Y(n316) );
INVX2TS U5349 ( .A(n6759), .Y(n317) );
INVX2TS U5350 ( .A(n268), .Y(n321) );
NAND2BXLTS U5351 ( .AN(n531), .B(n321), .Y(n1839) );
OAI22X1TS U5352 ( .A0(n538), .A1(n5129), .B0(n323), .B1(n5121), .Y(n5257) );
INVX2TS U5353 ( .A(n11629), .Y(n324) );
INVX2TS U5354 ( .A(n324), .Y(n325) );
INVX2TS U5355 ( .A(n324), .Y(n326) );
INVX2TS U5356 ( .A(n324), .Y(n327) );
INVX2TS U5357 ( .A(n324), .Y(n328) );
INVX2TS U5358 ( .A(n518), .Y(n331) );
NAND2X4TS U5359 ( .A(n476), .B(n2031), .Y(n5571) );
CLKINVX1TS U5360 ( .A(n4823), .Y(n333) );
INVX2TS U5361 ( .A(n333), .Y(n334) );
OAI22X2TS U5362 ( .A0(n4823), .A1(n4599), .B0(n4822), .B1(n3728), .Y(n4810)
);
XNOR2X2TS U5363 ( .A(Data_B_i[3]), .B(Data_B_i[17]), .Y(n3804) );
NOR2X1TS U5364 ( .A(Data_B_i[3]), .B(Data_B_i[17]), .Y(n3746) );
XNOR2X1TS U5365 ( .A(n337), .B(Data_A_i[39]), .Y(n2147) );
OAI21X1TS U5366 ( .A0(Data_B_i[49]), .A1(Data_B_i[35]), .B0(Data_B_i[34]),
.Y(n2540) );
XOR2X2TS U5367 ( .A(Data_B_i[34]), .B(Data_B_i[33]), .Y(n1739) );
INVX2TS U5368 ( .A(n6079), .Y(n338) );
NAND2X1TS U5369 ( .A(Data_A_i[45]), .B(Data_A_i[18]), .Y(n2874) );
NAND2X1TS U5370 ( .A(Data_A_i[6]), .B(Data_A_i[20]), .Y(n4396) );
INVX2TS U5371 ( .A(n6302), .Y(n341) );
NAND2X1TS U5372 ( .A(Data_A_i[21]), .B(Data_A_i[7]), .Y(n4395) );
INVX2TS U5373 ( .A(n6375), .Y(n342) );
INVX2TS U5374 ( .A(n5239), .Y(n343) );
XOR2X1TS U5375 ( .A(n1338), .B(Data_A_i[47]), .Y(n2291) );
NAND2X1TS U5376 ( .A(Data_A_i[47]), .B(Data_A_i[20]), .Y(n3093) );
NOR2X1TS U5377 ( .A(Data_A_i[47]), .B(Data_A_i[20]), .Y(n3089) );
NAND2X1TS U5378 ( .A(Data_A_i[47]), .B(Data_A_i[33]), .Y(n2441) );
NOR2X2TS U5379 ( .A(Data_A_i[47]), .B(Data_A_i[33]), .Y(n2438) );
INVX2TS U5380 ( .A(n5375), .Y(n344) );
NAND2X1TS U5381 ( .A(Data_A_i[48]), .B(Data_A_i[34]), .Y(n2440) );
NOR2X1TS U5382 ( .A(Data_A_i[48]), .B(Data_A_i[21]), .Y(n3094) );
INVX2TS U5383 ( .A(n5431), .Y(n345) );
XOR2X1TS U5384 ( .A(n345), .B(n342), .Y(n908) );
INVX2TS U5385 ( .A(n1923), .Y(n346) );
INVX2TS U5386 ( .A(n203), .Y(n348) );
INVX2TS U5387 ( .A(n203), .Y(n349) );
NAND2X2TS U5388 ( .A(n2201), .B(n2200), .Y(n350) );
NAND2X2TS U5389 ( .A(n2201), .B(n2200), .Y(n351) );
NAND2X1TS U5390 ( .A(n2201), .B(n2200), .Y(n5579) );
INVX2TS U5391 ( .A(n202), .Y(n354) );
INVX2TS U5392 ( .A(n202), .Y(n355) );
NAND2X4TS U5393 ( .A(n3834), .B(n6303), .Y(n356) );
OAI22X2TS U5394 ( .A0(n6492), .A1(n4811), .B0(n597), .B1(n4969), .Y(n4960)
);
INVX2TS U5395 ( .A(n200), .Y(n361) );
INVX2TS U5396 ( .A(n200), .Y(n362) );
INVX4TS U5397 ( .A(n364), .Y(n365) );
NAND2X2TS U5398 ( .A(n2817), .B(n2818), .Y(n366) );
NAND2X2TS U5399 ( .A(n1544), .B(n4239), .Y(n368) );
NAND2X2TS U5400 ( .A(n1544), .B(n4239), .Y(n4240) );
INVX2TS U5401 ( .A(n138), .Y(n369) );
INVX2TS U5402 ( .A(n156), .Y(n371) );
INVX2TS U5403 ( .A(n156), .Y(n372) );
OAI22X2TS U5404 ( .A0(n2384), .A1(n2116), .B0(n561), .B1(n2147), .Y(n2152)
);
OAI22X1TS U5405 ( .A0(n2384), .A1(n1912), .B0(n561), .B1(n1911), .Y(n1939)
);
INVX2TS U5406 ( .A(n178), .Y(n375) );
INVX2TS U5407 ( .A(n178), .Y(n376) );
INVX2TS U5408 ( .A(n205), .Y(n377) );
INVX2TS U5409 ( .A(n205), .Y(n378) );
NAND2X2TS U5410 ( .A(n2764), .B(n3473), .Y(n379) );
NAND2X2TS U5411 ( .A(n2764), .B(n3473), .Y(n3474) );
INVX2TS U5412 ( .A(n6047), .Y(n383) );
INVX2TS U5413 ( .A(n131), .Y(n384) );
INVX2TS U5414 ( .A(n131), .Y(n385) );
INVX2TS U5415 ( .A(n2033), .Y(n386) );
INVX2TS U5416 ( .A(n386), .Y(n387) );
INVX2TS U5417 ( .A(n2653), .Y(n388) );
INVX2TS U5418 ( .A(n388), .Y(n389) );
INVX2TS U5419 ( .A(n2761), .Y(n391) );
INVX2TS U5420 ( .A(n2939), .Y(n392) );
INVX2TS U5421 ( .A(n392), .Y(n393) );
INVX2TS U5422 ( .A(n175), .Y(n394) );
INVX2TS U5423 ( .A(n175), .Y(n395) );
INVX2TS U5424 ( .A(n230), .Y(n396) );
INVX2TS U5425 ( .A(n230), .Y(n397) );
INVX2TS U5426 ( .A(n3775), .Y(n6293) );
INVX2TS U5427 ( .A(n6293), .Y(n400) );
INVX2TS U5428 ( .A(n401), .Y(n402) );
INVX2TS U5429 ( .A(n401), .Y(n403) );
INVX2TS U5430 ( .A(n201), .Y(n404) );
INVX2TS U5431 ( .A(Data_B_i[32]), .Y(n406) );
OAI21X4TS U5432 ( .A0(Data_B_i[53]), .A1(Data_B_i[52]), .B0(n6760), .Y(n6725) );
INVX2TS U5433 ( .A(n206), .Y(n412) );
INVX2TS U5434 ( .A(n206), .Y(n413) );
OAI22X2TS U5435 ( .A0(n7503), .A1(n613), .B0(n7504), .B1(n410), .Y(n821) );
INVX2TS U5436 ( .A(n177), .Y(n414) );
INVX2TS U5437 ( .A(n177), .Y(n415) );
INVX2TS U5438 ( .A(n418), .Y(n419) );
INVX2TS U5439 ( .A(n421), .Y(n423) );
INVX2TS U5440 ( .A(n6704), .Y(n424) );
INVX2TS U5441 ( .A(n424), .Y(n425) );
INVX2TS U5442 ( .A(n5702), .Y(n427) );
INVX2TS U5443 ( .A(n427), .Y(n428) );
INVX2TS U5444 ( .A(n427), .Y(n429) );
INVX2TS U5445 ( .A(n199), .Y(n431) );
INVX2TS U5446 ( .A(n8278), .Y(n432) );
INVX2TS U5447 ( .A(n432), .Y(n433) );
INVX2TS U5448 ( .A(n6557), .Y(n434) );
INVX2TS U5449 ( .A(n434), .Y(n435) );
INVX2TS U5450 ( .A(n184), .Y(n438) );
INVX2TS U5451 ( .A(n127), .Y(n439) );
INVX2TS U5452 ( .A(n127), .Y(n440) );
INVX2TS U5453 ( .A(n1058), .Y(n441) );
INVX2TS U5454 ( .A(n1135), .Y(n442) );
INVX2TS U5455 ( .A(n1135), .Y(n443) );
INVX2TS U5456 ( .A(n204), .Y(n444) );
INVX2TS U5457 ( .A(n204), .Y(n445) );
INVX2TS U5458 ( .A(n2269), .Y(n5639) );
INVX2TS U5459 ( .A(n192), .Y(n447) );
INVX2TS U5460 ( .A(n192), .Y(n448) );
INVX2TS U5461 ( .A(n176), .Y(n449) );
INVX2TS U5462 ( .A(n4502), .Y(n6397) );
INVX2TS U5463 ( .A(n6547), .Y(n452) );
INVX2TS U5464 ( .A(n380), .Y(n453) );
INVX2TS U5465 ( .A(n324), .Y(n454) );
INVX2TS U5466 ( .A(n324), .Y(n455) );
INVX2TS U5467 ( .A(n8253), .Y(n456) );
INVX2TS U5468 ( .A(n456), .Y(n458) );
INVX2TS U5469 ( .A(n6052), .Y(n459) );
INVX2TS U5470 ( .A(n8426), .Y(n461) );
INVX2TS U5471 ( .A(n461), .Y(n462) );
INVX2TS U5472 ( .A(n8237), .Y(n464) );
INVX2TS U5473 ( .A(n198), .Y(n466) );
INVX2TS U5474 ( .A(n198), .Y(n467) );
INVX2TS U5475 ( .A(n1204), .Y(n469) );
INVX2TS U5476 ( .A(n1468), .Y(n470) );
INVX2TS U5477 ( .A(n1468), .Y(n471) );
INVX2TS U5478 ( .A(n1550), .Y(n472) );
INVX2TS U5479 ( .A(n1550), .Y(n473) );
NOR2BX2TS U5480 ( .AN(n630), .B(n472), .Y(n3825) );
OAI22X2TS U5481 ( .A0(n4950), .A1(n586), .B0(n5065), .B1(n473), .Y(n5073) );
INVX2TS U5482 ( .A(n474), .Y(n475) );
OAI2BB1X2TS U5483 ( .A0N(n475), .A1N(n247), .B0(n1470), .Y(n2805) );
XOR2X1TS U5484 ( .A(n247), .B(n475), .Y(n1471) );
OAI2BB1X1TS U5485 ( .A0N(n6086), .A1N(n6084), .B0(n475), .Y(n6101) );
OAI21XLTS U5486 ( .A0(Data_B_i[47]), .A1(Data_B_i[20]), .B0(n475), .Y(n2938)
);
XNOR2X1TS U5487 ( .A(Data_B_i[19]), .B(Data_B_i[46]), .Y(n2869) );
INVX2TS U5488 ( .A(Data_B_i[42]), .Y(n1338) );
ADDFHX2TS U5489 ( .A(Data_B_i[15]), .B(Data_B_i[42]), .CI(n2610), .CO(n2616),
.S(n2605) );
OAI21X2TS U5490 ( .A0(n1436), .A1(Data_B_i[42]), .B0(n1439), .Y(n1435) );
NOR2X1TS U5491 ( .A(Data_B_i[28]), .B(Data_B_i[42]), .Y(n2010) );
INVX2TS U5492 ( .A(n477), .Y(n478) );
INVX2TS U5493 ( .A(n477), .Y(n479) );
INVX2TS U5494 ( .A(n6162), .Y(n480) );
INVX2TS U5495 ( .A(n6731), .Y(n482) );
INVX2TS U5496 ( .A(n482), .Y(n483) );
INVX2TS U5497 ( .A(n482), .Y(n484) );
INVX2TS U5498 ( .A(n486), .Y(n487) );
INVX2TS U5499 ( .A(n486), .Y(n488) );
INVX2TS U5500 ( .A(n7779), .Y(n489) );
INVX2TS U5501 ( .A(n489), .Y(n490) );
INVX2TS U5502 ( .A(n489), .Y(n491) );
INVX2TS U5503 ( .A(n492), .Y(n493) );
INVX2TS U5504 ( .A(n492), .Y(n494) );
INVX2TS U5505 ( .A(n495), .Y(n496) );
INVX2TS U5506 ( .A(n495), .Y(n497) );
INVX2TS U5507 ( .A(n1411), .Y(n498) );
INVX2TS U5508 ( .A(n1411), .Y(n499) );
OAI22X1TS U5509 ( .A0(n2299), .A1(n498), .B0(n583), .B1(n2298), .Y(n2314) );
INVX2TS U5510 ( .A(n1411), .Y(n5731) );
INVX2TS U5511 ( .A(n500), .Y(n501) );
INVX2TS U5512 ( .A(n130), .Y(n503) );
INVX2TS U5513 ( .A(n8459), .Y(n507) );
OAI22X2TS U5514 ( .A0(n556), .A1(n7518), .B0(n506), .B1(n7408), .Y(n7414) );
NAND2X1TS U5515 ( .A(Data_B_i[40]), .B(Data_B_i[13]), .Y(n3345) );
NOR2X1TS U5516 ( .A(Data_B_i[40]), .B(Data_B_i[13]), .Y(n3344) );
XNOR2X2TS U5517 ( .A(n245), .B(Data_A_i[36]), .Y(n1922) );
XNOR2X2TS U5518 ( .A(n1545), .B(Data_B_i[5]), .Y(n1544) );
INVX2TS U5519 ( .A(n406), .Y(n516) );
NOR2X4TS U5520 ( .A(Data_B_i[32]), .B(Data_B_i[5]), .Y(n2592) );
OAI21X1TS U5521 ( .A0(Data_B_i[33]), .A1(Data_B_i[47]), .B0(Data_B_i[32]),
.Y(n1328) );
NAND2X1TS U5522 ( .A(Data_B_i[9]), .B(Data_B_i[36]), .Y(n3178) );
OAI21X1TS U5523 ( .A0(Data_B_i[51]), .A1(Data_B_i[37]), .B0(Data_B_i[36]),
.Y(n5148) );
XNOR2X2TS U5524 ( .A(n1614), .B(Data_B_i[36]), .Y(n982) );
XNOR2X1TS U5525 ( .A(Data_B_i[38]), .B(Data_A_i[32]), .Y(n1818) );
XNOR2X2TS U5526 ( .A(Data_B_i[52]), .B(Data_B_i[38]), .Y(n5205) );
OAI21X1TS U5527 ( .A0(Data_B_i[53]), .A1(Data_B_i[39]), .B0(Data_B_i[38]),
.Y(n5144) );
NAND2X1TS U5528 ( .A(Data_B_i[34]), .B(Data_B_i[7]), .Y(n2904) );
NOR2X4TS U5529 ( .A(Data_B_i[34]), .B(Data_B_i[7]), .Y(n2903) );
NAND2BX1TS U5530 ( .AN(n5497), .B(n524), .Y(n2039) );
NOR2X2TS U5531 ( .A(n1438), .B(Data_B_i[44]), .Y(n1437) );
XNOR2X1TS U5532 ( .A(Data_B_i[44]), .B(Data_B_i[17]), .Y(n2681) );
INVX2TS U5533 ( .A(Data_B_i[52]), .Y(n525) );
AOI21X1TS U5534 ( .A0(n8191), .A1(n528), .B0(n8190), .Y(n9624) );
AOI21X2TS U5535 ( .A0(n9635), .A1(n6694), .B0(n6746), .Y(n6007) );
AOI21X1TS U5536 ( .A0(n529), .A1(n8210), .B0(n791), .Y(n8213) );
AOI21X1TS U5537 ( .A0(n9452), .A1(n9451), .B0(n9450), .Y(n9456) );
AOI21X2TS U5538 ( .A0(n529), .A1(n8552), .B0(n8551), .Y(n8556) );
AOI21X2TS U5539 ( .A0(n7922), .A1(n529), .B0(n7921), .Y(n7926) );
AOI21X1TS U5540 ( .A0(n9452), .A1(n8370), .B0(n8369), .Y(n8375) );
AOI21X2TS U5541 ( .A0(n9452), .A1(n8541), .B0(n8540), .Y(n8546) );
INVX2TS U5542 ( .A(n10155), .Y(n530) );
OAI22X1TS U5543 ( .A0(n4151), .A1(n898), .B0(n4152), .B1(n4209), .Y(n4164)
);
BUFX3TS U5544 ( .A(n858), .Y(n898) );
BUFX3TS U5545 ( .A(Data_A_i[27]), .Y(n1887) );
OAI22X1TS U5546 ( .A0(n6764), .A1(n6712), .B0(n518), .B1(n174), .Y(n6768) );
INVX2TS U5547 ( .A(n1290), .Y(n1205) );
INVX2TS U5548 ( .A(n6491), .Y(n533) );
OA22X1TS U5549 ( .A0(n243), .A1(n339), .B0(n534), .B1(n6302), .Y(n6305) );
INVX2TS U5550 ( .A(n4979), .Y(n6598) );
INVX2TS U5551 ( .A(n6598), .Y(n535) );
INVX2TS U5552 ( .A(n6598), .Y(n536) );
OAI22X1TS U5553 ( .A0(n8855), .A1(n7647), .B0(n8450), .B1(n7409), .Y(n7464)
);
OAI22X1TS U5554 ( .A0(n8855), .A1(n823), .B0(n8450), .B1(n6997), .Y(n8274)
);
NAND2X4TS U5555 ( .A(n8450), .B(n6960), .Y(n8855) );
OAI21X1TS U5556 ( .A0(n5117), .A1(n1436), .B0(n2040), .Y(n5984) );
OAI2BB2X1TS U5557 ( .B0(n5117), .B1(n5487), .A0N(n2659), .A1N(n5130), .Y(
n5493) );
OAI22X1TS U5558 ( .A0(n5117), .A1(n2287), .B0(n5585), .B1(n2434), .Y(n2432)
);
OAI22X1TS U5559 ( .A0(n1923), .A1(n1759), .B0(n1814), .B1(n541), .Y(n1787)
);
OAI22X1TS U5560 ( .A0(n1923), .A1(n1922), .B0(n1921), .B1(n541), .Y(n1936)
);
NAND2X4TS U5561 ( .A(n1920), .B(n245), .Y(n1923) );
INVX2TS U5562 ( .A(Data_B_i[0]), .Y(n543) );
OAI22X1TS U5563 ( .A0(n349), .A1(n3911), .B0(n3904), .B1(n542), .Y(n4118) );
OAI22X1TS U5564 ( .A0(n348), .A1(n4003), .B0(n252), .B1(n543), .Y(n3981) );
OAI22X1TS U5565 ( .A0(n348), .A1(n4098), .B0(n4097), .B1(n543), .Y(n4105) );
NAND2X2TS U5566 ( .A(n1983), .B(n1267), .Y(n544) );
OAI22X1TS U5567 ( .A0(n1984), .A1(n1801), .B0(n1983), .B1(n1768), .Y(n1803)
);
NAND2X2TS U5568 ( .A(n1983), .B(n1267), .Y(n1984) );
INVX2TS U5569 ( .A(n8244), .Y(n1254) );
CLKAND2X2TS U5570 ( .A(n8233), .B(n2687), .Y(n8235) );
INVX2TS U5571 ( .A(n8235), .Y(n546) );
INVX2TS U5572 ( .A(n8235), .Y(n547) );
AO21X2TS U5573 ( .A0(n546), .A1(n463), .B0(n200), .Y(n6947) );
INVX2TS U5574 ( .A(n8427), .Y(n548) );
OAI22X1TS U5575 ( .A0(n7159), .A1(n548), .B0(n462), .B1(n453), .Y(n8456) );
OAI22X1TS U5576 ( .A0(n6919), .A1(n462), .B0(n6904), .B1(n548), .Y(n6923) );
AOI21X1TS U5577 ( .A0(n462), .A1(n135), .B0(n197), .Y(n1603) );
NAND2X2TS U5578 ( .A(n4156), .B(n1390), .Y(n549) );
NAND2X1TS U5579 ( .A(n4156), .B(n1390), .Y(n4158) );
AND2X2TS U5580 ( .A(n8237), .B(n2943), .Y(n8239) );
INVX2TS U5581 ( .A(n8239), .Y(n552) );
NAND2X2TS U5582 ( .A(n466), .B(n3227), .Y(n8259) );
AO21X1TS U5583 ( .A0(n350), .A1(n2200), .B0(n5225), .Y(n5244) );
OAI22X1TS U5584 ( .A0(n350), .A1(n5219), .B0(n555), .B1(n5225), .Y(n5231) );
OAI22X1TS U5585 ( .A0(n351), .A1(n5578), .B0(n555), .B1(n5576), .Y(n5692) );
OAI22X1TS U5586 ( .A0(n5579), .A1(n5225), .B0(n555), .B1(n2204), .Y(n2273)
);
NAND2X2TS U5587 ( .A(n505), .B(n6973), .Y(n556) );
NAND2X2TS U5588 ( .A(n505), .B(n6973), .Y(n557) );
OAI22X1TS U5589 ( .A0(n7009), .A1(n556), .B0(n7016), .B1(n506), .Y(n6993) );
OAI22X1TS U5590 ( .A0(n8319), .A1(n556), .B0(n507), .B1(n831), .Y(n8273) );
NAND2X1TS U5591 ( .A(n505), .B(n6973), .Y(n8460) );
INVX2TS U5592 ( .A(n1669), .Y(n558) );
OAI22X1TS U5593 ( .A0(n5539), .A1(n5218), .B0(n558), .B1(n5238), .Y(n5249)
);
INVX2TS U5594 ( .A(n8325), .Y(n559) );
INVX2TS U5595 ( .A(n8325), .Y(n560) );
OAI21X1TS U5596 ( .A0(n8312), .A1(n560), .B0(n1473), .Y(n8624) );
OAI22X1TS U5597 ( .A0(n560), .A1(n7520), .B0(n471), .B1(n7516), .Y(n7529) );
OAI22X1TS U5598 ( .A0(n560), .A1(n7516), .B0(n471), .B1(n7406), .Y(n7623) );
OAI22X1TS U5599 ( .A0(n3242), .A1(n471), .B0(n7092), .B1(n560), .Y(n3289) );
OAI22X1TS U5600 ( .A0(n559), .A1(n7506), .B0(n470), .B1(n7508), .Y(n822) );
OAI22X1TS U5601 ( .A0(n8312), .A1(n471), .B0(n7406), .B1(n559), .Y(n8612) );
OAI22X1TS U5602 ( .A0(n559), .A1(n7521), .B0(n7520), .B1(n470), .Y(n7588) );
INVX2TS U5603 ( .A(n2383), .Y(n561) );
INVX2TS U5604 ( .A(n2383), .Y(n562) );
AND2X4TS U5605 ( .A(n2787), .B(n2760), .Y(n8577) );
INVX2TS U5606 ( .A(n8577), .Y(n564) );
INVX2TS U5607 ( .A(n8577), .Y(n565) );
OAI21X2TS U5608 ( .A0(n8578), .A1(n565), .B0(n1167), .Y(n8594) );
OAI22X1TS U5609 ( .A0(n8279), .A1(n565), .B0(n496), .B1(n432), .Y(n8231) );
AO21X1TS U5610 ( .A0(n565), .A1(n497), .B0(n432), .Y(n7012) );
AND2X4TS U5611 ( .A(n8308), .B(n2747), .Y(n8309) );
INVX2TS U5612 ( .A(n8309), .Y(n566) );
INVX2TS U5613 ( .A(n8309), .Y(n567) );
INVX2TS U5614 ( .A(n8309), .Y(n568) );
OAI22X1TS U5615 ( .A0(n566), .A1(n8307), .B0(n8308), .B1(n2962), .Y(n2997)
);
INVX2TS U5616 ( .A(n2817), .Y(n3633) );
INVX2TS U5617 ( .A(n3633), .Y(n569) );
INVX2TS U5618 ( .A(n3633), .Y(n570) );
AO21X1TS U5619 ( .A0(n366), .A1(n569), .B0(n1492), .Y(n3662) );
OAI22X1TS U5620 ( .A0(n3634), .A1(n3442), .B0(n3415), .B1(n570), .Y(n3488)
);
INVX2TS U5621 ( .A(n1490), .Y(n572) );
XNOR2X1TS U5622 ( .A(n500), .B(n6963), .Y(n3714) );
XNOR2X4TS U5623 ( .A(n1633), .B(Data_B_i[9]), .Y(n4772) );
INVX2TS U5624 ( .A(n4772), .Y(n574) );
OAI22X1TS U5625 ( .A0(n4773), .A1(n4214), .B0(n574), .B1(n4238), .Y(n4235)
);
NAND2BX1TS U5626 ( .AN(n1204), .B(n4580), .Y(n578) );
OAI22X1TS U5627 ( .A0(n6549), .A1(n6547), .B0(n6548), .B1(n4583), .Y(n4615)
);
XOR2X1TS U5628 ( .A(n4579), .B(n4664), .Y(n4580) );
INVX2TS U5629 ( .A(n5684), .Y(n580) );
OAI22X1TS U5630 ( .A0(n6732), .A1(n6730), .B0(n483), .B1(n2541), .Y(n5730)
);
OAI22X1TS U5631 ( .A0(n5626), .A1(n484), .B0(n6732), .B1(n5625), .Y(n5740)
);
INVX2TS U5632 ( .A(n5733), .Y(n582) );
NAND2X2TS U5633 ( .A(n1421), .B(n502), .Y(n585) );
OAI22X1TS U5634 ( .A0(n5317), .A1(n584), .B0(n504), .B1(n427), .Y(n5207) );
AO21X1TS U5635 ( .A0(n5727), .A1(n503), .B0(n427), .Y(n5211) );
NAND2X1TS U5636 ( .A(n1421), .B(n504), .Y(n5727) );
NAND2BX2TS U5637 ( .AN(n1550), .B(n3766), .Y(n587) );
INVX2TS U5638 ( .A(n591), .Y(n592) );
CLKBUFX2TS U5639 ( .A(n595), .Y(n594) );
INVX2TS U5640 ( .A(rst), .Y(n595) );
OAI22X1TS U5641 ( .A0(n357), .A1(n6077), .B0(n598), .B1(n6100), .Y(n6107) );
NOR2BX1TS U5642 ( .AN(Data_A_i[14]), .B(n597), .Y(n4565) );
INVX2TS U5643 ( .A(n1015), .Y(n599) );
AO21X1TS U5644 ( .A0(n368), .A1(n4239), .B0(n1567), .Y(n4255) );
OAI22X1TS U5645 ( .A0(n4240), .A1(n4207), .B0(n599), .B1(n1567), .Y(n4245)
);
NOR2BX1TS U5646 ( .AN(n4096), .B(n599), .Y(n3810) );
OAI22X1TS U5647 ( .A0(n368), .A1(n3988), .B0(n599), .B1(n3975), .Y(n3995) );
INVX2TS U5648 ( .A(n1415), .Y(n600) );
INVX2TS U5649 ( .A(n1415), .Y(n601) );
INVX2TS U5650 ( .A(n1415), .Y(n5573) );
CLKBUFX2TS U5651 ( .A(n603), .Y(n602) );
OAI22X1TS U5652 ( .A0(n2576), .A1(n268), .B0(n2575), .B1(n1839), .Y(n1918)
);
INVX2TS U5653 ( .A(n1607), .Y(n604) );
INVX2TS U5654 ( .A(n1607), .Y(n605) );
CLKBUFX2TS U5655 ( .A(n3473), .Y(n606) );
XOR2X2TS U5656 ( .A(n2619), .B(n2613), .Y(n2763) );
INVX2TS U5657 ( .A(n1064), .Y(n608) );
NOR2X1TS U5658 ( .A(n2605), .B(n3437), .Y(n2601) );
XNOR2X1TS U5659 ( .A(n3609), .B(n1063), .Y(n2816) );
XOR2X2TS U5660 ( .A(n6859), .B(n610), .Y(n1599) );
INVX2TS U5661 ( .A(n1248), .Y(n6860) );
INVX2TS U5662 ( .A(n1431), .Y(n611) );
INVX2TS U5663 ( .A(n8323), .Y(n613) );
INVX2TS U5664 ( .A(n8573), .Y(n615) );
INVX2TS U5665 ( .A(n1492), .Y(n616) );
INVX4TS U5666 ( .A(n3439), .Y(n617) );
INVX2TS U5667 ( .A(n7537), .Y(n625) );
INVX2TS U5668 ( .A(n7537), .Y(n626) );
INVX2TS U5669 ( .A(n7537), .Y(n627) );
OAI22X1TS U5670 ( .A0(n627), .A1(n1609), .B0(n548), .B1(n197), .Y(n7455) );
INVX2TS U5671 ( .A(n2009), .Y(n628) );
INVX2TS U5672 ( .A(n2009), .Y(n629) );
XNOR2X1TS U5673 ( .A(n628), .B(n414), .Y(n972) );
INVX2TS U5674 ( .A(n3768), .Y(n630) );
INVX2TS U5675 ( .A(n3768), .Y(n631) );
INVX2TS U5676 ( .A(n2751), .Y(n7647) );
INVX2TS U5677 ( .A(n7647), .Y(n632) );
NOR2BX1TS U5678 ( .AN(n632), .B(n614), .Y(n2831) );
INVX2TS U5679 ( .A(n8094), .Y(n730) );
XOR2X4TS U5680 ( .A(n8696), .B(n8694), .Y(n656) );
OAI21X4TS U5681 ( .A0(n4946), .A1(n893), .B0(n635), .Y(n6269) );
XOR2X4TS U5682 ( .A(n732), .B(n5015), .Y(n4869) );
XOR2X4TS U5683 ( .A(n1683), .B(n4680), .Y(n4712) );
XOR2X4TS U5684 ( .A(n638), .B(n3580), .Y(n3583) );
XNOR2X4TS U5685 ( .A(n639), .B(n1095), .Y(n3336) );
XNOR2X4TS U5686 ( .A(n7838), .B(n7839), .Y(n639) );
ADDHX1TS U5687 ( .A(n3504), .B(n3503), .CO(n3519), .S(n3549) );
ADDFHX2TS U5688 ( .A(n4167), .B(n4166), .CI(n4165), .CO(n4172), .S(n4174) );
OAI21X1TS U5689 ( .A0(n4062), .A1(n4061), .B0(n4063), .Y(n4018) );
INVX2TS U5690 ( .A(n7696), .Y(n4360) );
OAI21X2TS U5691 ( .A0(n6745), .A1(n6744), .B0(n6743), .Y(n684) );
ADDFX2TS U5692 ( .A(n5947), .B(n5946), .CI(n5945), .CO(n6720), .S(n5954) );
OAI2BB1X4TS U5693 ( .A0N(n5860), .A1N(n5859), .B0(n642), .Y(n5853) );
OAI2BB1X4TS U5694 ( .A0N(n644), .A1N(n643), .B0(n5858), .Y(n642) );
OAI21X4TS U5695 ( .A0(n5882), .A1(n5883), .B0(n5881), .Y(n897) );
XOR2X4TS U5696 ( .A(n5858), .B(n645), .Y(n5882) );
XOR2X4TS U5697 ( .A(n5859), .B(n5860), .Y(n645) );
ADDFHX2TS U5698 ( .A(n5434), .B(n5433), .CI(n5432), .CO(n5454), .S(n5435) );
BUFX6TS U5699 ( .A(Data_A_i[44]), .Y(n646) );
ADDFHX2TS U5700 ( .A(n6928), .B(n6927), .CI(n6926), .CO(n6939), .S(n6942) );
OAI21X4TS U5701 ( .A0(n8364), .A1(n8365), .B0(n8363), .Y(n647) );
XOR2X4TS U5702 ( .A(n8364), .B(n8365), .Y(n648) );
OAI21X4TS U5703 ( .A0(n5909), .A1(n5910), .B0(n5908), .Y(n1667) );
XOR2X4TS U5704 ( .A(n650), .B(n2699), .Y(n7472) );
XOR2X4TS U5705 ( .A(n651), .B(n6959), .Y(n8450) );
XOR2X4TS U5706 ( .A(n652), .B(n6464), .Y(n6465) );
XOR2X4TS U5707 ( .A(n6462), .B(n6463), .Y(n652) );
NOR2X4TS U5708 ( .A(n5924), .B(n5923), .Y(n8076) );
ADDFHX2TS U5709 ( .A(n4526), .B(n4525), .CI(n4524), .CO(n4758), .S(n4521) );
INVX2TS U5710 ( .A(n6795), .Y(n5785) );
XOR2X4TS U5711 ( .A(n653), .B(n5778), .Y(n5808) );
XOR2X4TS U5712 ( .A(n5777), .B(n5779), .Y(n653) );
XOR2X4TS U5713 ( .A(n656), .B(n8695), .Y(n8739) );
CLKINVX6TS U5714 ( .A(n8305), .Y(n8634) );
ADDFHX2TS U5715 ( .A(n5285), .B(n5284), .CI(n5283), .CO(n5307), .S(n5874) );
OAI21X4TS U5716 ( .A0(n2238), .A1(n2235), .B0(n2236), .Y(n2335) );
NOR2BX2TS U5717 ( .AN(n4600), .B(n571), .Y(n3806) );
INVX2TS U5718 ( .A(n3200), .Y(n3123) );
ADDFX2TS U5719 ( .A(n5233), .B(n5234), .CI(n5232), .CO(n5292), .S(n5299) );
OAI2BB1X2TS U5720 ( .A0N(n5186), .A1N(n5167), .B0(n186), .Y(n663) );
AOI2BB1X4TS U5721 ( .A0N(n1219), .A1N(n8518), .B0(n137), .Y(n1388) );
XOR2X4TS U5722 ( .A(n669), .B(n5804), .Y(n5825) );
XOR2X4TS U5723 ( .A(n5805), .B(n5806), .Y(n669) );
OAI2BB1X2TS U5724 ( .A0N(n5698), .A1N(n5697), .B0(n670), .Y(n5706) );
INVX2TS U5725 ( .A(n8009), .Y(n8022) );
ADDFHX2TS U5726 ( .A(n5605), .B(n5604), .CI(n5603), .CO(n5630), .S(n5715) );
ADDFHX2TS U5727 ( .A(n7850), .B(n7849), .CI(n7848), .CO(n7884), .S(n7891) );
ADDFHX2TS U5728 ( .A(n6944), .B(n6943), .CI(n6942), .CO(n6991), .S(n8223) );
OAI2BB1X4TS U5729 ( .A0N(n3643), .A1N(n3642), .B0(n1605), .Y(n8300) );
XNOR2X4TS U5730 ( .A(n3202), .B(n1431), .Y(n1464) );
XOR2X4TS U5731 ( .A(n3120), .B(n3119), .Y(n3202) );
BUFX8TS U5732 ( .A(n8425), .Y(n690) );
OR2X1TS U5733 ( .A(n7149), .B(n7150), .Y(n677) );
INVX2TS U5734 ( .A(n7699), .Y(n7701) );
ADDFHX2TS U5735 ( .A(n8434), .B(n8433), .CI(n8432), .CO(n8461), .S(n8439) );
NAND2X1TS U5736 ( .A(n5058), .B(n5057), .Y(n679) );
XOR2X2TS U5737 ( .A(n712), .B(Data_B_i[2]), .Y(n3803) );
AOI21X4TS U5738 ( .A0(n1379), .A1(n1266), .B0(n1265), .Y(n8388) );
OAI21X4TS U5739 ( .A0(n7189), .A1(n9365), .B0(n727), .Y(n1379) );
INVX2TS U5740 ( .A(n2581), .Y(n7188) );
AOI21X4TS U5741 ( .A0(n6746), .A1(n1329), .B0(n684), .Y(n9632) );
INVX2TS U5742 ( .A(n3483), .Y(n1250) );
INVX2TS U5743 ( .A(n9312), .Y(n8168) );
OAI21X1TS U5744 ( .A0(n7885), .A1(n7886), .B0(n7884), .Y(n687) );
XOR2X4TS U5745 ( .A(n7904), .B(n7903), .Y(n1477) );
XNOR2X4TS U5746 ( .A(n688), .B(n7884), .Y(n7904) );
XNOR2X4TS U5747 ( .A(n7885), .B(n7886), .Y(n688) );
XNOR2X4TS U5748 ( .A(n1247), .B(n3594), .Y(n3616) );
XNOR2X4TS U5749 ( .A(n691), .B(n8384), .Y(EVEN1_Q_left[27]) );
OAI21X4TS U5750 ( .A0(n8388), .A1(n1264), .B0(n8389), .Y(n691) );
OAI21X1TS U5751 ( .A0(n1964), .A1(n1965), .B0(n1963), .Y(n695) );
OA21X4TS U5752 ( .A0(n2581), .A1(n9366), .B0(n7186), .Y(n727) );
INVX4TS U5753 ( .A(n2585), .Y(n2902) );
INVX2TS U5754 ( .A(n2641), .Y(n2630) );
OAI22X1TS U5755 ( .A0(n3230), .A1(n8244), .B0(n3325), .B1(n8243), .Y(n3305)
);
INVX2TS U5756 ( .A(n8802), .Y(n7848) );
INVX2TS U5757 ( .A(n2657), .Y(n698) );
NAND2BX4TS U5758 ( .AN(n2700), .B(n698), .Y(n1258) );
XOR2X4TS U5759 ( .A(n700), .B(n4283), .Y(n4286) );
OA21X4TS U5760 ( .A0(n3380), .A1(n218), .B0(n1735), .Y(n1736) );
ADDFHX2TS U5761 ( .A(n6401), .B(n6400), .CI(n6399), .CO(n6442), .S(n6407) );
OAI2BB1X2TS U5762 ( .A0N(n1781), .A1N(n1780), .B0(n701), .Y(n1834) );
OAI21X1TS U5763 ( .A0(n1780), .A1(n1781), .B0(n1779), .Y(n701) );
XOR2X4TS U5764 ( .A(n1779), .B(n702), .Y(n1792) );
OAI21X1TS U5765 ( .A0(n5559), .A1(n5560), .B0(n5558), .Y(n705) );
XNOR2X4TS U5766 ( .A(n6970), .B(n829), .Y(n828) );
ADDFHX2TS U5767 ( .A(n3309), .B(n3308), .CI(n3307), .CO(n7826), .S(n3279) );
XNOR2X4TS U5768 ( .A(n709), .B(n7866), .Y(n7874) );
XNOR2X4TS U5769 ( .A(n7868), .B(n7867), .Y(n709) );
XOR2X4TS U5770 ( .A(n715), .B(n714), .Y(n6111) );
XNOR2X4TS U5771 ( .A(n8741), .B(n1100), .Y(n8746) );
ADDFHX2TS U5772 ( .A(n8223), .B(n8222), .CI(n8221), .CO(n8925), .S(n8922) );
INVX4TS U5773 ( .A(n7294), .Y(n6198) );
ADDHX1TS U5774 ( .A(n7589), .B(n7588), .CO(n7531), .S(n7597) );
INVX2TS U5775 ( .A(n2896), .Y(n2899) );
OAI21X2TS U5776 ( .A0(n2899), .A1(n2898), .B0(n2897), .Y(n2900) );
AOI21X2TS U5777 ( .A0(n2849), .A1(n2848), .B0(n2847), .Y(n2854) );
NOR2X2TS U5778 ( .A(n3543), .B(n3544), .Y(n9175) );
INVX2TS U5779 ( .A(n5683), .Y(n5748) );
CLKINVX2TS U5780 ( .A(n8347), .Y(n1461) );
XOR2X2TS U5781 ( .A(n1378), .B(n5590), .Y(n5599) );
ADDFHX2TS U5782 ( .A(n5716), .B(n5715), .CI(n5714), .CO(n5678), .S(n5766) );
ADDFHX2TS U5783 ( .A(n3681), .B(n3680), .CI(n3679), .CO(n3699), .S(n3671) );
NAND2X2TS U5784 ( .A(n8390), .B(n8389), .Y(n8391) );
AOI21X4TS U5785 ( .A0(n4427), .A1(n4426), .B0(n4425), .Y(n4921) );
XOR2X1TS U5786 ( .A(n4028), .B(n1406), .Y(n1405) );
OA21X4TS U5787 ( .A0(n720), .A1(n8023), .B0(n8046), .Y(n8027) );
INVX2TS U5788 ( .A(n5994), .Y(n2419) );
AOI21X4TS U5789 ( .A0(n5928), .A1(n8505), .B0(n1613), .Y(n726) );
OAI21X4TS U5790 ( .A0(n5345), .A1(n5346), .B0(n5344), .Y(n728) );
XNOR2X4TS U5791 ( .A(n729), .B(n5344), .Y(n5859) );
XNOR2X4TS U5792 ( .A(n5346), .B(n5345), .Y(n729) );
OAI22X2TS U5793 ( .A0(n634), .A1(n5136), .B0(n1367), .B1(n5213), .Y(n5227)
);
ADDFHX2TS U5794 ( .A(n5701), .B(n5700), .CI(n5699), .CO(n5680), .S(n5745) );
NAND2BX2TS U5795 ( .AN(n5531), .B(n492), .Y(n1508) );
OAI21X1TS U5796 ( .A0(n5864), .A1(n5865), .B0(n5863), .Y(n733) );
XOR2X4TS U5797 ( .A(n734), .B(n5863), .Y(n5885) );
NAND2X4TS U5798 ( .A(n9637), .B(n6807), .Y(n7942) );
INVX2TS U5799 ( .A(n2022), .Y(n2020) );
XOR2X4TS U5800 ( .A(n739), .B(n6391), .Y(n6427) );
XOR2X4TS U5801 ( .A(n6393), .B(n6392), .Y(n739) );
OAI21X4TS U5802 ( .A0(n2752), .A1(n1089), .B0(n1087), .Y(n1727) );
XOR2X2TS U5803 ( .A(Data_B_i[52]), .B(Data_B_i[51]), .Y(n5120) );
OAI21X2TS U5804 ( .A0(n6976), .A1(n6965), .B0(n6964), .Y(n1108) );
OAI22X1TS U5805 ( .A0(n410), .A1(n7592), .B0(n613), .B1(n7421), .Y(n7502) );
NOR2X4TS U5806 ( .A(n8882), .B(n8881), .Y(n8892) );
XNOR2X4TS U5807 ( .A(n741), .B(n8875), .Y(n8882) );
XNOR2X4TS U5808 ( .A(n8876), .B(n8877), .Y(n741) );
XOR2X4TS U5809 ( .A(n782), .B(n8196), .Y(n781) );
OAI2BB1X4TS U5810 ( .A0N(n5523), .A1N(n5522), .B0(n742), .Y(n8196) );
OAI21X4TS U5811 ( .A0(n5522), .A1(n5523), .B0(n5521), .Y(n742) );
XOR2X4TS U5812 ( .A(n743), .B(n5522), .Y(n7968) );
XOR2X4TS U5813 ( .A(n5521), .B(n5523), .Y(n743) );
OAI21X1TS U5814 ( .A0(n5445), .A1(n5446), .B0(n5444), .Y(n744) );
XOR2X4TS U5815 ( .A(n5445), .B(n5446), .Y(n745) );
BUFX6TS U5816 ( .A(n5539), .Y(n6729) );
BUFX6TS U5817 ( .A(n3717), .Y(n747) );
CLKINVX6TS U5818 ( .A(n7182), .Y(n7180) );
XOR2X4TS U5819 ( .A(n752), .B(n4866), .Y(n1653) );
XNOR2X4TS U5820 ( .A(n4833), .B(n751), .Y(n4866) );
XNOR2X4TS U5821 ( .A(n4834), .B(n4835), .Y(n751) );
AOI21X4TS U5822 ( .A0(n9378), .A1(n9374), .B0(n9306), .Y(n9307) );
XNOR2X1TS U5823 ( .A(n9373), .B(n9354), .Y(EVEN1_S_B[16]) );
NAND2X2TS U5824 ( .A(n159), .B(n7684), .Y(n2244) );
XNOR2X1TS U5825 ( .A(n892), .B(n4860), .Y(n4862) );
NAND2X1TS U5826 ( .A(n9133), .B(n9132), .Y(n9134) );
OA21X4TS U5827 ( .A0(n2586), .A1(n2585), .B0(n2590), .Y(n1059) );
OAI2BB1X1TS U5828 ( .A0N(n4383), .A1N(n4382), .B0(n757), .Y(n4508) );
XOR2X4TS U5829 ( .A(n4381), .B(n760), .Y(n4371) );
AOI21X4TS U5830 ( .A0(n849), .A1(n4456), .B0(n761), .Y(n1276) );
OAI21X4TS U5831 ( .A0(n4454), .A1(n4455), .B0(n4453), .Y(n761) );
ADDFHX2TS U5832 ( .A(n3991), .B(n3990), .CI(n3989), .CO(n4034), .S(n4023) );
ADDFHX2TS U5833 ( .A(n1832), .B(n1831), .CI(n1830), .CO(n1997), .S(n1835) );
AOI2BB1X4TS U5834 ( .A0N(n8083), .A1N(n8084), .B0(n766), .Y(n8078) );
AOI21X4TS U5835 ( .A0(n8009), .A1(n5851), .B0(n5850), .Y(n8083) );
OAI22X2TS U5836 ( .A0(n4823), .A1(n4557), .B0(n4556), .B1(n4821), .Y(n4564)
);
BUFX6TS U5837 ( .A(n7737), .Y(n770) );
OAI21X1TS U5838 ( .A0(n5660), .A1(n773), .B0(n771), .Y(n5884) );
NOR2X2TS U5839 ( .A(n4452), .B(n4455), .Y(n849) );
NAND3X8TS U5840 ( .A(n844), .B(n842), .C(n841), .Y(n3102) );
NOR2X4TS U5841 ( .A(n8681), .B(n8680), .Y(DP_OP_59J6_122_190_n187) );
INVX4TS U5842 ( .A(n5286), .Y(n5873) );
XOR2X4TS U5843 ( .A(Data_B_i[50]), .B(Data_B_i[51]), .Y(n1669) );
AOI21X2TS U5844 ( .A0(n5159), .A1(n5184), .B0(n5158), .Y(n5174) );
OAI21X2TS U5845 ( .A0(n8636), .A1(n8637), .B0(n8635), .Y(n1469) );
XOR2X4TS U5846 ( .A(n1227), .B(n7479), .Y(n7510) );
OAI22X2TS U5847 ( .A0(n7105), .A1(n3405), .B0(n3465), .B1(n539), .Y(n3458)
);
NAND2X2TS U5848 ( .A(n3802), .B(n211), .Y(n1190) );
OAI21X4TS U5849 ( .A0(n2634), .A1(n2637), .B0(n2635), .Y(n2716) );
OAI21X4TS U5850 ( .A0(n2727), .A1(n2724), .B0(n2725), .Y(n2721) );
NOR2X8TS U5851 ( .A(n5927), .B(n896), .Y(n8509) );
ADDFX2TS U5852 ( .A(n3461), .B(n3459), .CI(n3460), .CO(n3603), .S(n3463) );
OAI2BB1X2TS U5853 ( .A0N(n5862), .A1N(n8196), .B0(n780), .Y(n5871) );
OAI21X1TS U5854 ( .A0(n8196), .A1(n5862), .B0(n5861), .Y(n780) );
XNOR2X4TS U5855 ( .A(n781), .B(n5861), .Y(n5892) );
XOR2X1TS U5856 ( .A(n5543), .B(n5544), .Y(n5606) );
OAI22X2TS U5857 ( .A0(n770), .A1(n1741), .B0(n468), .B1(n1743), .Y(n1746) );
OAI21X4TS U5858 ( .A0(n1321), .A1(n762), .B0(n1319), .Y(n8060) );
OAI21X4TS U5859 ( .A0(n7260), .A1(n7259), .B0(n7258), .Y(n783) );
OAI21X1TS U5860 ( .A0(n3652), .A1(n3653), .B0(n3650), .Y(n3651) );
ADDFHX2TS U5861 ( .A(n3671), .B(n3670), .CI(n3669), .CO(n3703), .S(n3668) );
OAI22X2TS U5862 ( .A0(n332), .A1(n5570), .B0(n5569), .B1(n5568), .Y(n5612)
);
XOR2X2TS U5863 ( .A(Data_B_i[25]), .B(Data_B_i[24]), .Y(n4552) );
ADDFHX2TS U5864 ( .A(n5760), .B(n5759), .CI(n5758), .CO(n5768), .S(n5804) );
AOI21X4TS U5865 ( .A0(n2335), .A1(n2334), .B0(n2333), .Y(n2400) );
NAND2BX4TS U5866 ( .AN(n8094), .B(n948), .Y(n9542) );
XNOR2X1TS U5867 ( .A(n5620), .B(n426), .Y(n5531) );
INVX4TS U5868 ( .A(EVEN1_Q_left[26]), .Y(n8412) );
NAND2X2TS U5869 ( .A(n9378), .B(n9375), .Y(n9308) );
XNOR2X4TS U5870 ( .A(n788), .B(n3180), .Y(n3677) );
AOI21X4TS U5871 ( .A0(n1594), .A1(n3118), .B0(n789), .Y(n788) );
INVX2TS U5872 ( .A(n9270), .Y(n9295) );
NOR2X2TS U5873 ( .A(n8610), .B(n8609), .Y(n8171) );
XNOR2X2TS U5874 ( .A(n1030), .B(n8675), .Y(n7286) );
NAND2X4TS U5875 ( .A(n8843), .B(n8757), .Y(n8108) );
OAI2BB1X1TS U5876 ( .A0N(n4513), .A1N(n4512), .B0(n793), .Y(n4514) );
XNOR2X4TS U5877 ( .A(n796), .B(n4511), .Y(n4418) );
XNOR2X4TS U5878 ( .A(n4512), .B(n4513), .Y(n796) );
INVX2TS U5879 ( .A(n2900), .Y(n797) );
OAI2BB1X4TS U5880 ( .A0N(n2901), .A1N(n2902), .B0(n797), .Y(n1465) );
NAND2X2TS U5881 ( .A(n3748), .B(n3747), .Y(n3800) );
INVX4TS U5882 ( .A(n1594), .Y(n3120) );
OAI21X2TS U5883 ( .A0(n7699), .A1(n7702), .B0(n7700), .Y(n7270) );
ADDFHX2TS U5884 ( .A(n7813), .B(n7812), .CI(n7811), .CO(n7854), .S(n7815) );
XOR2X4TS U5885 ( .A(n5485), .B(Data_B_i[49]), .Y(n2513) );
XOR2X1TS U5886 ( .A(n5265), .B(n5264), .Y(n798) );
NAND2BX2TS U5887 ( .AN(n5483), .B(n5128), .Y(n5131) );
OAI21X1TS U5888 ( .A0(n5264), .A1(n5265), .B0(n5263), .Y(n799) );
OAI2BB1X1TS U5889 ( .A0N(n9060), .A1N(n9059), .B0(n800), .Y(
DP_OP_62J6_125_4796_n564) );
XOR2X4TS U5890 ( .A(n7704), .B(n875), .Y(n801) );
ADDFHX2TS U5891 ( .A(n4150), .B(n4148), .CI(n4149), .CO(n4187), .S(n4169) );
NAND2X1TS U5892 ( .A(n7272), .B(n7266), .Y(n876) );
OAI2BB1X4TS U5893 ( .A0N(n4326), .A1N(n4347), .B0(n1008), .Y(n1007) );
XNOR2X4TS U5894 ( .A(n6269), .B(n5020), .Y(n5022) );
INVX2TS U5895 ( .A(n7218), .Y(n6837) );
NAND2X2TS U5896 ( .A(n4869), .B(n4868), .Y(n4944) );
NAND2X4TS U5897 ( .A(n2654), .B(n2655), .Y(n2700) );
XOR2X4TS U5898 ( .A(n804), .B(n5747), .Y(n5790) );
XOR2X4TS U5899 ( .A(n5745), .B(n5746), .Y(n804) );
XOR2X4TS U5900 ( .A(n807), .B(n806), .Y(n4834) );
XOR2X4TS U5901 ( .A(n4836), .B(n4837), .Y(n807) );
AOI21X2TS U5902 ( .A0(n8379), .A1(n9360), .B0(n1419), .Y(n1418) );
CMPR22X2TS U5903 ( .A(n2301), .B(n2300), .CO(n2313), .S(n2317) );
XNOR2X4TS U5904 ( .A(n1128), .B(n1969), .Y(n5683) );
NAND2BX4TS U5905 ( .AN(n7181), .B(n7180), .Y(n8757) );
ADDFHX2TS U5906 ( .A(n7061), .B(n7059), .CI(n7060), .CO(n7179), .S(n7100) );
XOR2X4TS U5907 ( .A(n810), .B(n7854), .Y(n7870) );
XOR2X4TS U5908 ( .A(n7855), .B(n7856), .Y(n810) );
AO22X4TS U5909 ( .A0(n7810), .A1(n813), .B0(n812), .B1(n817), .Y(n7862) );
XOR2X1TS U5910 ( .A(n7810), .B(n814), .Y(n7811) );
XNOR2X4TS U5911 ( .A(n6978), .B(n1093), .Y(n816) );
XOR2X4TS U5912 ( .A(n1066), .B(n2808), .Y(n7423) );
XOR2X4TS U5913 ( .A(n2854), .B(n2853), .Y(n3675) );
XOR2X1TS U5914 ( .A(n439), .B(n824), .Y(n7506) );
XNOR2X4TS U5915 ( .A(n826), .B(n7896), .Y(n7935) );
XNOR2X4TS U5916 ( .A(n830), .B(n828), .Y(n827) );
XOR2X4TS U5917 ( .A(n6961), .B(n832), .Y(n7405) );
XOR2X4TS U5918 ( .A(n6960), .B(n141), .Y(n6971) );
XOR2X4TS U5919 ( .A(n3358), .B(n194), .Y(n8423) );
OA21X4TS U5920 ( .A0(n834), .A1(n8851), .B0(n8842), .Y(n7185) );
XOR2X4TS U5921 ( .A(n5011), .B(n836), .Y(n5013) );
XOR2X4TS U5922 ( .A(n4803), .B(n6662), .Y(n836) );
OAI2BB1X4TS U5923 ( .A0N(n4187), .A1N(n4186), .B0(n838), .Y(n4192) );
XNOR2X4TS U5924 ( .A(n839), .B(n4186), .Y(n4194) );
AOI21X4TS U5925 ( .A0(n3102), .A1(n3101), .B0(n840), .Y(n1531) );
NAND2BX4TS U5926 ( .AN(n843), .B(n3352), .Y(n842) );
NAND2BX4TS U5927 ( .AN(n1732), .B(n1727), .Y(n844) );
XOR2X4TS U5928 ( .A(n7130), .B(n848), .Y(n8934) );
XOR2X4TS U5929 ( .A(Data_B_i[18]), .B(Data_B_i[17]), .Y(n1172) );
OAI21X4TS U5930 ( .A0(n4296), .A1(n4293), .B0(n4294), .Y(n4456) );
XOR2X4TS U5931 ( .A(n1567), .B(Data_B_i[6]), .Y(n858) );
OAI21X4TS U5932 ( .A0(n1276), .A1(n4728), .B0(n4727), .Y(n4894) );
INVX2TS U5933 ( .A(n4467), .Y(n856) );
XOR2X4TS U5934 ( .A(n860), .B(n4110), .Y(n4467) );
XNOR2X4TS U5935 ( .A(n1686), .B(Data_B_i[7]), .Y(n857) );
INVX2TS U5936 ( .A(n8408), .Y(n861) );
XOR2X4TS U5937 ( .A(n1629), .B(n6477), .Y(n6611) );
XOR2X4TS U5938 ( .A(n1403), .B(n1402), .Y(n901) );
AOI21X4TS U5939 ( .A0(n868), .A1(n4308), .B0(n1000), .Y(n1016) );
XNOR2X2TS U5940 ( .A(n868), .B(n4309), .Y(n4357) );
AOI21X1TS U5941 ( .A0(n4429), .A1(n868), .B0(n4428), .Y(n4449) );
AOI21X1TS U5942 ( .A0(n4520), .A1(n868), .B0(n4519), .Y(n4535) );
AOI21X1TS U5943 ( .A0(n4907), .A1(n868), .B0(n4906), .Y(n4912) );
AOI21X1TS U5944 ( .A0(n4923), .A1(n868), .B0(n4922), .Y(n4927) );
AOI21X1TS U5945 ( .A0(n4880), .A1(n868), .B0(n4879), .Y(n4887) );
AOI21X1TS U5946 ( .A0(n4786), .A1(n868), .B0(n4785), .Y(n4796) );
XNOR2X4TS U5947 ( .A(n872), .B(n4180), .Y(n4829) );
OAI2BB1X4TS U5948 ( .A0N(n874), .A1N(n7704), .B0(n873), .Y(n7287) );
XNOR2X4TS U5949 ( .A(n876), .B(n641), .Y(n11188) );
XOR2X4TS U5950 ( .A(n883), .B(n4956), .Y(n5012) );
NOR2X2TS U5951 ( .A(n889), .B(n6268), .Y(n888) );
XOR2X2TS U5952 ( .A(n4281), .B(n674), .Y(n4070) );
INVX2TS U5953 ( .A(n896), .Y(n895) );
OAI2BB1X4TS U5954 ( .A0N(n5883), .A1N(n5882), .B0(n897), .Y(n896) );
NAND2X1TS U5955 ( .A(n144), .B(n898), .Y(n1175) );
OAI22X1TS U5956 ( .A0(n4152), .A1(n898), .B0(n4099), .B1(n4209), .Y(n4147)
);
OAI22X1TS U5957 ( .A0(n4026), .A1(n898), .B0(n3978), .B1(n144), .Y(n4027) );
OAI22X1TS U5958 ( .A0(n4000), .A1(n898), .B0(n4001), .B1(n4209), .Y(n4013)
);
OAI22X1TS U5959 ( .A0(n4000), .A1(n144), .B0(n3978), .B1(n898), .Y(n3990) );
OAI22X1TS U5960 ( .A0(n4208), .A1(n898), .B0(n4026), .B1(n144), .Y(n4200) );
OAI22X1TS U5961 ( .A0(n4208), .A1(n144), .B0(n4237), .B1(n898), .Y(n4244) );
OAI22X1TS U5962 ( .A0(n4100), .A1(n4209), .B0(n4099), .B1(n858), .Y(n4104)
);
AOI21X4TS U5963 ( .A0(n8367), .A1(n6613), .B0(n900), .Y(n9449) );
OAI21X4TS U5964 ( .A0(n8553), .A1(n6609), .B0(n1210), .Y(n8367) );
NAND2X2TS U5965 ( .A(n6607), .B(n6608), .Y(n1210) );
XNOR2X4TS U5966 ( .A(n904), .B(n903), .Y(n4751) );
XNOR2X4TS U5967 ( .A(n1348), .B(Data_B_i[38]), .Y(n906) );
XOR2X4TS U5968 ( .A(n3387), .B(n3131), .Y(n3695) );
XOR2X4TS U5969 ( .A(Data_B_i[21]), .B(Data_B_i[22]), .Y(n913) );
XOR2X4TS U5970 ( .A(n918), .B(n6296), .Y(n7313) );
OAI21X2TS U5971 ( .A0(n2973), .A1(n2974), .B0(n2972), .Y(n926) );
XNOR2X4TS U5972 ( .A(n2972), .B(n927), .Y(n2979) );
XOR2X4TS U5973 ( .A(n2973), .B(n8783), .Y(n927) );
XNOR2X4TS U5974 ( .A(n2700), .B(n2702), .Y(n7549) );
NOR2BX4TS U5975 ( .AN(n929), .B(n2402), .Y(n7259) );
INVX2TS U5976 ( .A(n2400), .Y(n930) );
NAND2X1TS U5977 ( .A(n8119), .B(n8118), .Y(n8536) );
AOI21X4TS U5978 ( .A0(n9473), .A1(n8111), .B0(n8110), .Y(n932) );
XOR2X4TS U5979 ( .A(n939), .B(n8362), .Y(n938) );
OAI2BB1X4TS U5980 ( .A0N(n8353), .A1N(n8354), .B0(n1456), .Y(n939) );
OAI2BB1X4TS U5981 ( .A0N(n6247), .A1N(n6246), .B0(n940), .Y(n6231) );
OAI21X2TS U5982 ( .A0(n6246), .A1(n6247), .B0(n6245), .Y(n940) );
NOR2BX2TS U5983 ( .AN(n7707), .B(n7694), .Y(n1401) );
AOI21X4TS U5984 ( .A0(n8145), .A1(n947), .B0(n946), .Y(n7694) );
NOR2X2TS U5985 ( .A(n8146), .B(n8161), .Y(n947) );
NOR2X4TS U5986 ( .A(n1396), .B(n4355), .Y(n8146) );
XOR2X4TS U5987 ( .A(n8078), .B(n219), .Y(n948) );
NAND2BX4TS U5988 ( .AN(n949), .B(n950), .Y(n8564) );
NOR2X4TS U5989 ( .A(n950), .B(n8103), .Y(n8518) );
XOR2X4TS U5990 ( .A(n8097), .B(n8096), .Y(n950) );
XOR2X4TS U5991 ( .A(n953), .B(n952), .Y(n5842) );
XOR2X4TS U5992 ( .A(n1366), .B(n5761), .Y(n952) );
XOR2X4TS U5993 ( .A(n5764), .B(n5765), .Y(n953) );
OA21X4TS U5994 ( .A0(n2179), .A1(n2180), .B0(n2178), .Y(n960) );
XOR2X4TS U5995 ( .A(n2323), .B(n963), .Y(n2337) );
XOR2X4TS U5996 ( .A(n8014), .B(n8013), .Y(n965) );
OAI21X4TS U5997 ( .A0(n2557), .A1(n967), .B0(n2556), .Y(n2558) );
NAND2BX2TS U5998 ( .AN(n966), .B(n2331), .Y(n2344) );
NAND2BX4TS U5999 ( .AN(n968), .B(n2330), .Y(n967) );
INVX2TS U6000 ( .A(n2329), .Y(n968) );
XOR2X4TS U6001 ( .A(n970), .B(n2024), .Y(n5530) );
XOR2X4TS U6002 ( .A(n973), .B(n1642), .Y(n7732) );
NAND2X1TS U6003 ( .A(n7725), .B(n9635), .Y(n976) );
XNOR2X4TS U6004 ( .A(n978), .B(n6701), .Y(n6696) );
XNOR2X4TS U6005 ( .A(n6702), .B(n6703), .Y(n978) );
XOR2X4TS U6006 ( .A(n979), .B(n5190), .Y(n6717) );
INVX2TS U6007 ( .A(n9590), .Y(n5947) );
OAI22X2TS U6008 ( .A0(n1836), .A1(n2576), .B0(n1925), .B1(n603), .Y(n1927)
);
XNOR2X4TS U6009 ( .A(n1614), .B(Data_B_i[34]), .Y(n981) );
OAI21X2TS U6010 ( .A0(n9500), .A1(n9501), .B0(add_x_3_n178), .Y(add_x_3_n172) );
AOI21X1TS U6011 ( .A0(n9492), .A1(add_x_3_n172), .B0(n9464), .Y(add_x_3_n158) );
AOI21X4TS U6012 ( .A0(n9470), .A1(n1678), .B0(n988), .Y(n987) );
OAI21X2TS U6013 ( .A0(n994), .A1(n4694), .B0(n4693), .Y(n993) );
XNOR2X4TS U6014 ( .A(n995), .B(n4457), .Y(n4721) );
XOR2X4TS U6015 ( .A(n1559), .B(Data_B_i[11]), .Y(n1021) );
OAI21X4TS U6016 ( .A0(n9291), .A1(n9288), .B0(n9289), .Y(n8145) );
INVX2TS U6017 ( .A(n4325), .Y(n1008) );
OAI2BB1X4TS U6018 ( .A0N(n9124), .A1N(n4197), .B0(n129), .Y(n4347) );
AOI21X4TS U6019 ( .A0(n7243), .A1(n4933), .B0(n4932), .Y(n8406) );
AOI21X4TS U6020 ( .A0(n7267), .A1(n4367), .B0(n4366), .Y(n4893) );
NAND2X1TS U6021 ( .A(n9152), .B(n9161), .Y(n4179) );
XOR2X4TS U6022 ( .A(n1260), .B(n1011), .Y(n4659) );
XNOR2X4TS U6023 ( .A(n1545), .B(Data_B_i[3]), .Y(n1015) );
XOR2X4TS U6024 ( .A(n1016), .B(n4302), .Y(n4359) );
XOR2X4TS U6025 ( .A(n222), .B(n1017), .Y(n1216) );
NAND2BX2TS U6026 ( .AN(n7273), .B(n7267), .Y(n1018) );
OAI21X4TS U6027 ( .A0(n4362), .A1(n7694), .B0(n4361), .Y(n7267) );
INVX2TS U6028 ( .A(n4198), .Y(n1020) );
OAI21X1TS U6029 ( .A0(n4006), .A1(n4007), .B0(n4005), .Y(n1022) );
XNOR2X4TS U6030 ( .A(n1023), .B(n4005), .Y(n4049) );
OAI21X4TS U6031 ( .A0(n1027), .A1(n1026), .B0(n1024), .Y(n4444) );
XOR2X4TS U6032 ( .A(n8676), .B(n1216), .Y(n1030) );
XNOR2X4TS U6033 ( .A(n1036), .B(n4321), .Y(n1396) );
OAI21X2TS U6034 ( .A0(n5077), .A1(n1040), .B0(n5076), .Y(n1039) );
XNOR2X4TS U6035 ( .A(n4992), .B(n4401), .Y(n6411) );
AOI21X4TS U6036 ( .A0(n4399), .A1(n4400), .B0(n4398), .Y(n1044) );
XNOR2X4TS U6037 ( .A(n1049), .B(n7309), .Y(n6196) );
OAI21X1TS U6038 ( .A0(n3030), .A1(n3031), .B0(n3029), .Y(n1056) );
XNOR2X4TS U6039 ( .A(n1059), .B(n2595), .Y(n1492) );
XNOR2X4TS U6040 ( .A(n1065), .B(n2602), .Y(n1064) );
AOI21X2TS U6041 ( .A0(n1067), .A1(n2597), .B0(n1062), .Y(n1066) );
AOI21X4TS U6042 ( .A0(n2640), .A1(n2642), .B0(n2630), .Y(n1072) );
NAND3BX4TS U6043 ( .AN(n2639), .B(n2642), .C(n2792), .Y(n1073) );
AOI21X2TS U6044 ( .A0(n2715), .A1(n2713), .B0(n2615), .Y(n2639) );
INVX2TS U6045 ( .A(n3151), .Y(n1500) );
NAND3BX4TS U6046 ( .AN(n3770), .B(n4570), .C(Data_A_i[0]), .Y(n1078) );
OAI21X2TS U6047 ( .A0(n1078), .A1(n3751), .B0(n1074), .Y(n3743) );
AOI21X4TS U6048 ( .A0(n2716), .A1(n1080), .B0(n1079), .Y(n2752) );
XOR2X1TS U6049 ( .A(n440), .B(n1086), .Y(n7520) );
INVX2TS U6050 ( .A(n7593), .Y(n1086) );
NAND2BX4TS U6051 ( .AN(n7936), .B(n1091), .Y(n8901) );
INVX3TS U6052 ( .A(n7937), .Y(n1091) );
XNOR2X4TS U6053 ( .A(n1092), .B(n1152), .Y(n7937) );
XOR2X4TS U6054 ( .A(n1477), .B(n7902), .Y(n1152) );
XNOR2X4TS U6055 ( .A(n7934), .B(n7935), .Y(n1092) );
XOR2X4TS U6056 ( .A(n6965), .B(n6976), .Y(n6978) );
XOR2X4TS U6057 ( .A(n1463), .B(n7817), .Y(n1095) );
XOR2X1TS U6058 ( .A(n134), .B(n6921), .Y(n3105) );
XNOR2X4TS U6059 ( .A(n1098), .B(n2955), .Y(n1097) );
NAND2X1TS U6060 ( .A(n2947), .B(n2950), .Y(n1099) );
XNOR2X4TS U6061 ( .A(n8742), .B(n8743), .Y(n1100) );
OAI2BB1X4TS U6062 ( .A0N(n8616), .A1N(n8615), .B0(n1101), .Y(n8620) );
XOR2X4TS U6063 ( .A(n1102), .B(n8614), .Y(n8619) );
XOR2X4TS U6064 ( .A(n1105), .B(n8920), .Y(n8694) );
XOR2X4TS U6065 ( .A(n8738), .B(n1107), .Y(n8749) );
XOR2X4TS U6066 ( .A(n8739), .B(n8740), .Y(n1107) );
OAI21X1TS U6067 ( .A0(n7009), .A1(n507), .B0(n1110), .Y(n7010) );
XNOR2X4TS U6068 ( .A(n1118), .B(n8603), .Y(n8645) );
XOR2X4TS U6069 ( .A(n6867), .B(n195), .Y(n8451) );
OAI21X4TS U6070 ( .A0(n1478), .A1(n1122), .B0(n1119), .Y(n7002) );
XOR2X4TS U6071 ( .A(n1126), .B(n7663), .Y(n7894) );
XNOR2X4TS U6072 ( .A(n1970), .B(n1971), .Y(n1128) );
XNOR2X4TS U6073 ( .A(n1129), .B(n3367), .Y(n1248) );
AOI21X4TS U6074 ( .A0(n1594), .A1(n180), .B0(n1130), .Y(n1129) );
XNOR2X4TS U6075 ( .A(n1132), .B(n3383), .Y(n6865) );
XOR2X4TS U6076 ( .A(n3167), .B(n1153), .Y(n3133) );
OAI21X1TS U6077 ( .A0(n2842), .A1(n2752), .B0(n2846), .Y(n1146) );
OAI22X2TS U6078 ( .A0(n412), .A1(n3137), .B0(n614), .B1(n3192), .Y(n1149) );
AOI21X1TS U6079 ( .A0(n8884), .A1(n1150), .B0(n8883), .Y(
DP_OP_59J6_122_190_n212) );
OAI22X2TS U6080 ( .A0(n413), .A1(n7651), .B0(n614), .B1(n7650), .Y(n7832) );
XOR2X4TS U6081 ( .A(n1156), .B(n8642), .Y(n8762) );
XOR2X4TS U6082 ( .A(n8643), .B(n1157), .Y(n1156) );
XNOR2X4TS U6083 ( .A(n1159), .B(n3286), .Y(n8228) );
OAI2BB1X4TS U6084 ( .A0N(n1067), .A1N(n2923), .B0(n1479), .Y(n3283) );
XOR2X4TS U6085 ( .A(n1493), .B(n2804), .Y(n1491) );
XOR2X4TS U6086 ( .A(n1171), .B(n3478), .Y(n7625) );
AOI21X1TS U6087 ( .A0(n9490), .A1(n9491), .B0(n9489), .Y(add_x_3_n185) );
XOR2X4TS U6088 ( .A(n7374), .B(n7373), .Y(n8729) );
INVX2TS U6089 ( .A(n1174), .Y(n3846) );
OAI21X2TS U6090 ( .A0(n4253), .A1(n144), .B0(n1176), .Y(n4276) );
INVX2TS U6091 ( .A(n4945), .Y(n4943) );
AOI21X4TS U6092 ( .A0(n4305), .A1(n4304), .B0(n1184), .Y(n4296) );
NAND2BX4TS U6093 ( .AN(n3963), .B(n1185), .Y(n4304) );
XNOR2X4TS U6094 ( .A(n3804), .B(n3800), .Y(n6052) );
XNOR2X4TS U6095 ( .A(n1189), .B(n3803), .Y(n6162) );
XOR2X4TS U6096 ( .A(n1190), .B(n3801), .Y(n1189) );
XOR2X4TS U6097 ( .A(n3956), .B(n3957), .Y(n1192) );
XNOR2X4TS U6098 ( .A(Data_B_i[15]), .B(Data_B_i[16]), .Y(n1290) );
NOR2X4TS U6099 ( .A(n1196), .B(n9463), .Y(n9465) );
NAND2X1TS U6100 ( .A(n7707), .B(n1197), .Y(n4362) );
AOI21X2TS U6101 ( .A0(n7695), .A1(n1197), .B0(n4360), .Y(n4361) );
OAI2BB1X1TS U6102 ( .A0N(n187), .A1N(n4040), .B0(n1201), .Y(n4216) );
INVX2TS U6103 ( .A(n9428), .Y(n1203) );
NOR2BX1TS U6104 ( .AN(n4600), .B(n1290), .Y(n6334) );
OAI22X1TS U6105 ( .A0(n5041), .A1(n3861), .B0(n3795), .B1(n1290), .Y(n3805)
);
OAI22X1TS U6106 ( .A0(n6040), .A1(n4569), .B0(n4573), .B1(n532), .Y(n4632)
);
OAI22X1TS U6107 ( .A0(n6040), .A1(n4573), .B0(n4609), .B1(n532), .Y(n4605)
);
OAI22X2TS U6108 ( .A0(n6040), .A1(n4481), .B0(n4569), .B1(n532), .Y(n4636)
);
OAI22X1TS U6109 ( .A0(n6040), .A1(n3784), .B0(n3839), .B1(n532), .Y(n3832)
);
OAI21X2TS U6110 ( .A0(n4720), .A1(n4721), .B0(n4719), .Y(n1206) );
XOR2X4TS U6111 ( .A(n1207), .B(n4719), .Y(n4747) );
XOR2X4TS U6112 ( .A(n4720), .B(n4721), .Y(n1207) );
XNOR2X4TS U6113 ( .A(n1209), .B(n4505), .Y(n6648) );
NAND2X4TS U6114 ( .A(n5922), .B(n5921), .Y(n8085) );
OAI22X1TS U6115 ( .A0(n143), .A1(n1753), .B0(n1742), .B1(n275), .Y(n1745) );
OAI22X1TS U6116 ( .A0(n143), .A1(n2146), .B0(n2355), .B1(n275), .Y(n2354) );
OAI21X2TS U6117 ( .A0(n5718), .A1(n5719), .B0(n5717), .Y(n1214) );
XNOR2X4TS U6118 ( .A(n1215), .B(n5717), .Y(n5720) );
XNOR2X4TS U6119 ( .A(n5718), .B(n5719), .Y(n1215) );
XNOR2X4TS U6120 ( .A(n8424), .B(n6865), .Y(n3384) );
XOR2X4TS U6121 ( .A(Data_B_i[23]), .B(Data_B_i[24]), .Y(n1218) );
XOR2X4TS U6122 ( .A(n1221), .B(n6108), .Y(n6142) );
OAI2BB1X4TS U6123 ( .A0N(n8740), .A1N(n8739), .B0(n1223), .Y(n8747) );
OAI2BB1X4TS U6124 ( .A0N(n8646), .A1N(n8645), .B0(n1224), .Y(n8761) );
XNOR2X4TS U6125 ( .A(n8645), .B(n8646), .Y(n1225) );
OAI2BB1X4TS U6126 ( .A0N(n7481), .A1N(n7480), .B0(n1226), .Y(n8583) );
XNOR2X4TS U6127 ( .A(n1229), .B(n2000), .Y(n5315) );
XOR2X4TS U6128 ( .A(n2001), .B(n1230), .Y(n1229) );
INVX2TS U6129 ( .A(n2002), .Y(n1230) );
XOR2X4TS U6130 ( .A(n3498), .B(n1232), .Y(n7424) );
XOR2X4TS U6131 ( .A(n3499), .B(n1233), .Y(n1232) );
XNOR2X4TS U6132 ( .A(n1234), .B(n3481), .Y(n1233) );
XNOR2X4TS U6133 ( .A(n1237), .B(n2879), .Y(n7470) );
OAI22X2TS U6134 ( .A0(n571), .A1(n4567), .B0(n4568), .B1(n6086), .Y(n4633)
);
NAND2X1TS U6135 ( .A(n1240), .B(n6659), .Y(n7917) );
INVX2TS U6136 ( .A(n4861), .Y(n1240) );
NAND2BX1TS U6137 ( .AN(n6659), .B(n4861), .Y(n1713) );
XNOR2X4TS U6138 ( .A(n1296), .B(n4800), .Y(n4861) );
XOR2X4TS U6139 ( .A(n8354), .B(n8353), .Y(n1459) );
OAI2BB1X4TS U6140 ( .A0N(n3596), .A1N(n3595), .B0(n1246), .Y(n3643) );
OAI21X2TS U6141 ( .A0(n3595), .A1(n3596), .B0(n3594), .Y(n1246) );
XNOR2X4TS U6142 ( .A(n3595), .B(n3596), .Y(n1247) );
XOR2X4TS U6143 ( .A(n1252), .B(n3450), .Y(n7618) );
XOR2X4TS U6144 ( .A(n1263), .B(n5801), .Y(n5824) );
INVX2TS U6145 ( .A(n8390), .Y(n1264) );
XOR2X4TS U6146 ( .A(n1268), .B(Data_B_i[28]), .Y(n1983) );
INVX2TS U6147 ( .A(add_x_3_n171), .Y(n9536) );
XOR2X4TS U6148 ( .A(n1269), .B(n6114), .Y(n6670) );
XNOR2X4TS U6149 ( .A(n1858), .B(n1857), .Y(n1271) );
NOR2X4TS U6150 ( .A(n2330), .B(n2329), .Y(n2555) );
OAI2BB1X4TS U6151 ( .A0N(n4371), .A1N(n4370), .B0(n1277), .Y(n4513) );
OAI21X2TS U6152 ( .A0(n4370), .A1(n4371), .B0(n4369), .Y(n1277) );
XOR2X4TS U6153 ( .A(n1278), .B(n4369), .Y(n4414) );
OAI21X4TS U6154 ( .A0(n8388), .A1(n1285), .B0(n1284), .Y(n9360) );
AOI21X4TS U6155 ( .A0(n8382), .A1(n8072), .B0(n8071), .Y(n1284) );
NOR2X2TS U6156 ( .A(n2099), .B(n2098), .Y(n8131) );
OAI21X2TS U6157 ( .A0(n2077), .A1(n2087), .B0(n2078), .Y(n2107) );
ADDFHX2TS U6158 ( .A(n7034), .B(n7033), .CI(n7032), .CO(n7078), .S(n7038) );
INVX2TS U6159 ( .A(DP_OP_59J6_122_190_n136), .Y(n8874) );
ADDFHX2TS U6160 ( .A(n7046), .B(n7045), .CI(n7044), .CO(n7061), .S(n7025) );
ADDFHX2TS U6161 ( .A(n2507), .B(n2506), .CI(n2505), .CO(n5801), .S(n2510) );
OAI21X2TS U6162 ( .A0(n4310), .A1(n4313), .B0(n4311), .Y(n4305) );
INVX2TS U6163 ( .A(n4456), .Y(n4368) );
ADDFHX2TS U6164 ( .A(n3918), .B(n3917), .CI(n3916), .CO(n3961), .S(n3919) );
NOR2X2TS U6165 ( .A(n9296), .B(n9270), .Y(n9313) );
ADDFHX2TS U6166 ( .A(n4820), .B(n4819), .CI(n4818), .CO(n4966), .S(n4816) );
ADDFHX2TS U6167 ( .A(n5425), .B(n5424), .CI(n5423), .CO(n5449), .S(n5407) );
NAND2X2TS U6168 ( .A(n5932), .B(n5931), .Y(n6015) );
ADDFHX2TS U6169 ( .A(n2387), .B(n2386), .CI(n2385), .CO(n2476), .S(n2389) );
OAI22X2TS U6170 ( .A0(n4444), .A1(n4144), .B0(n573), .B1(n4143), .Y(n4148)
);
CLKINVX3TS U6171 ( .A(n6652), .Y(n4706) );
ADDFHX2TS U6172 ( .A(n5710), .B(n5709), .CI(n5708), .CO(n5712), .S(n5758) );
ADDFHX2TS U6173 ( .A(n1747), .B(n1746), .CI(n1745), .CO(n1790), .S(n1811) );
NOR2X4TS U6174 ( .A(n9671), .B(n9661), .Y(n8531) );
NAND2X2TS U6175 ( .A(n8383), .B(n8382), .Y(n8384) );
ADDFX2TS U6176 ( .A(n2139), .B(n2138), .CI(n2137), .CO(n2365), .S(n2135) );
OAI21X2TS U6177 ( .A0(Data_B_i[18]), .A1(Data_B_i[4]), .B0(Data_B_i[3]), .Y(
n3745) );
NAND2X2TS U6178 ( .A(n3745), .B(n3744), .Y(n3760) );
ADDFHX2TS U6179 ( .A(n8431), .B(n8430), .CI(n8429), .CO(n8724), .S(n8402) );
NAND2BX2TS U6180 ( .AN(DP_OP_62J6_125_4796_n294), .B(n9072), .Y(n1381) );
OAI21X4TS U6181 ( .A0(Data_B_i[22]), .A1(Data_B_i[8]), .B0(Data_B_i[7]), .Y(
n4501) );
NAND2X4TS U6182 ( .A(n4501), .B(n4500), .Y(n4575) );
ADDFHX2TS U6183 ( .A(n6562), .B(n6561), .CI(n6560), .CO(n6569), .S(n6544) );
ADDFHX2TS U6184 ( .A(n6387), .B(n6386), .CI(n6385), .CO(n6392), .S(n6353) );
NAND3X2TS U6185 ( .A(n6064), .B(n6063), .C(n6062), .Y(n6325) );
OAI22X1TS U6186 ( .A0(n589), .A1(n6047), .B0(n488), .B1(n3850), .Y(n3873) );
ADDFHX2TS U6187 ( .A(Data_B_i[22]), .B(Data_B_i[49]), .CI(n3202), .CO(n3203),
.S(n3121) );
OAI22X2TS U6188 ( .A0(n3694), .A1(n3611), .B0(n3715), .B1(n3636), .Y(n3639)
);
OAI21X2TS U6189 ( .A0(n7714), .A1(n8150), .B0(n7715), .Y(n7687) );
ADDFHX2TS U6190 ( .A(n8765), .B(n8764), .CI(n8763), .CO(n8898), .S(n8767) );
ADDFHX2TS U6191 ( .A(n293), .B(n313), .CI(n2797), .CO(n2858), .S(n2857) );
ADDFHX4TS U6192 ( .A(n8631), .B(n8629), .CI(n8630), .CO(n8692), .S(n8621) );
OAI21X2TS U6193 ( .A0(n3387), .A1(n3354), .B0(n3353), .Y(n3358) );
OAI22X2TS U6194 ( .A0(n5656), .A1(n580), .B0(n5655), .B1(n1316), .Y(n5662)
);
OAI22X2TS U6195 ( .A0(n1289), .A1(n4390), .B0(n571), .B1(n4475), .Y(n4477)
);
ADDFHX4TS U6196 ( .A(n4706), .B(n4705), .CI(n4704), .CO(n4699), .S(n4732) );
ADDFHX2TS U6197 ( .A(n7827), .B(n7826), .CI(n7825), .CO(n8797), .S(n8796) );
ADDFHX4TS U6198 ( .A(n8581), .B(n8580), .CI(n8579), .CO(n8920), .S(n8840) );
NAND2X2TS U6199 ( .A(n5836), .B(n5835), .Y(n7210) );
ADDFHX4TS U6200 ( .A(n8690), .B(n8689), .CI(n8688), .CO(n8750), .S(n8706) );
NAND2X2TS U6201 ( .A(n5924), .B(n5923), .Y(n8077) );
ADDFHX2TS U6202 ( .A(n5874), .B(n5873), .CI(n5872), .CO(n5869), .S(n5904) );
NOR2X2TS U6203 ( .A(n5636), .B(n5602), .Y(n9076) );
AOI21X4TS U6204 ( .A0(n2090), .A1(n2088), .B0(n2076), .Y(n2081) );
XOR2X4TS U6205 ( .A(n2081), .B(n2080), .Y(n2095) );
ADDFHX2TS U6206 ( .A(n4251), .B(n4250), .CI(n4249), .CO(n4287), .S(n4263) );
XOR2X4TS U6207 ( .A(n4801), .B(n4802), .Y(n1296) );
XOR2X4TS U6208 ( .A(n6083), .B(n2588), .Y(n1301) );
OAI22X2TS U6209 ( .A0(n4968), .A1(n1290), .B0(n6040), .B1(n4824), .Y(n4962)
);
XOR2X4TS U6210 ( .A(n1308), .B(n1307), .Y(n1306) );
OAI21X1TS U6211 ( .A0(n8518), .A1(n1313), .B0(n1388), .Y(add_x_2_n197) );
XOR2X4TS U6212 ( .A(n2156), .B(n2155), .Y(n1315) );
NAND2X1TS U6213 ( .A(n1315), .B(n2242), .Y(n6690) );
INVX2TS U6214 ( .A(n1318), .Y(n1317) );
XOR2X1TS U6215 ( .A(n2408), .B(n1318), .Y(n2425) );
AOI21X2TS U6216 ( .A0(n2107), .A1(n1322), .B0(n1320), .Y(n1319) );
OAI2BB1X1TS U6217 ( .A0N(n1979), .A1N(n1327), .B0(n1323), .Y(n2128) );
NAND2X1TS U6218 ( .A(n1324), .B(n1978), .Y(n1323) );
XOR2X1TS U6219 ( .A(n1979), .B(n1326), .Y(n1994) );
XNOR2X4TS U6220 ( .A(n2450), .B(n2449), .Y(n2269) );
NAND2X2TS U6221 ( .A(n2462), .B(n2461), .Y(n2556) );
NOR2X4TS U6222 ( .A(n6693), .B(n6744), .Y(n1329) );
XOR2X4TS U6223 ( .A(n1331), .B(n1330), .Y(n7223) );
OAI22X2TS U6224 ( .A0(n332), .A1(n2275), .B0(n2291), .B1(n5568), .Y(n2289)
);
OAI2BB1X4TS U6225 ( .A0N(n5452), .A1N(n5451), .B0(n1339), .Y(n5939) );
XNOR2X4TS U6226 ( .A(n5450), .B(n1340), .Y(n5444) );
XOR2X4TS U6227 ( .A(n1347), .B(n2130), .Y(n5324) );
OAI22X2TS U6228 ( .A0(n7737), .A1(n1783), .B0(n1824), .B1(n468), .Y(n1815)
);
INVX2TS U6229 ( .A(n8076), .Y(n1361) );
XNOR2X4TS U6230 ( .A(n5914), .B(n5913), .Y(n5924) );
OAI2BB1X4TS U6231 ( .A0N(n5889), .A1N(n5888), .B0(n1363), .Y(n5909) );
XNOR2X4TS U6232 ( .A(n1364), .B(n5887), .Y(n5917) );
XNOR2X4TS U6233 ( .A(n5889), .B(n5888), .Y(n1364) );
XOR2X4TS U6234 ( .A(n5763), .B(n5762), .Y(n1366) );
XOR2X4TS U6235 ( .A(n1370), .B(Data_B_i[46]), .Y(n5581) );
XNOR2X4TS U6236 ( .A(n5205), .B(n5198), .Y(n6704) );
CLKINVX1TS U6237 ( .A(n1379), .Y(n8477) );
NAND2BX4TS U6238 ( .AN(n9071), .B(n1380), .Y(n9350) );
NOR2BX4TS U6239 ( .AN(n2227), .B(n1385), .Y(n1384) );
NOR2BX2TS U6240 ( .AN(n1386), .B(n2051), .Y(n1385) );
XNOR2X4TS U6241 ( .A(n1391), .B(Data_B_i[3]), .Y(n1390) );
XOR2X4TS U6242 ( .A(n1391), .B(Data_B_i[1]), .Y(n4156) );
NAND2X1TS U6243 ( .A(n1400), .B(n2582), .Y(n7186) );
NOR2X2TS U6244 ( .A(n1400), .B(n2582), .Y(n2581) );
NOR2X1TS U6245 ( .A(n1401), .B(n7695), .Y(n7698) );
XNOR2X2TS U6246 ( .A(n7708), .B(n7694), .Y(n8155) );
XOR2X4TS U6247 ( .A(n6431), .B(n1665), .Y(n1403) );
INVX2TS U6248 ( .A(n1414), .Y(n2165) );
XNOR2X4TS U6249 ( .A(n2164), .B(n2193), .Y(n1412) );
AND2X4TS U6250 ( .A(n2018), .B(n2017), .Y(n1414) );
XOR2X4TS U6251 ( .A(Data_B_i[48]), .B(Data_B_i[49]), .Y(n1415) );
AOI21X4TS U6252 ( .A0(n2611), .A1(n1423), .B0(n1422), .Y(n2585) );
NAND2X4TS U6253 ( .A(Data_B_i[29]), .B(Data_B_i[2]), .Y(n2617) );
NOR2X8TS U6254 ( .A(Data_B_i[29]), .B(Data_B_i[2]), .Y(n2618) );
OAI21X4TS U6255 ( .A0(n2598), .A1(n2602), .B0(n2599), .Y(n2611) );
XOR2X4TS U6256 ( .A(n1426), .B(n5290), .Y(n9575) );
XOR2X4TS U6257 ( .A(n5291), .B(n5292), .Y(n1426) );
XOR2X4TS U6258 ( .A(n1429), .B(n1427), .Y(EVEN1_S_B[17]) );
NAND2BX4TS U6259 ( .AN(n9370), .B(n9354), .Y(n1430) );
OAI21X4TS U6260 ( .A0(n1485), .A1(n9308), .B0(n9307), .Y(n9354) );
XOR2X4TS U6261 ( .A(n1465), .B(n237), .Y(n1431) );
AOI21X4TS U6262 ( .A0(n7002), .A1(n6873), .B0(n6872), .Y(n8856) );
XNOR2X4TS U6263 ( .A(n1449), .B(n5392), .Y(n5854) );
XOR2X4TS U6264 ( .A(Data_B_i[30]), .B(Data_B_i[31]), .Y(n1454) );
INVX2TS U6265 ( .A(n11190), .Y(n8006) );
XOR2X4TS U6266 ( .A(n8352), .B(n1459), .Y(n8732) );
XOR2X4TS U6267 ( .A(n8346), .B(n1462), .Y(n8356) );
XOR2X4TS U6268 ( .A(n1467), .B(n3701), .Y(n6974) );
XOR2X4TS U6269 ( .A(n3703), .B(n3702), .Y(n1467) );
OAI2BB1X4TS U6270 ( .A0N(n7904), .A1N(n7903), .B0(n1476), .Y(n8879) );
INVX2TS U6271 ( .A(n2922), .Y(n1479) );
OA21X4TS U6272 ( .A0(n9337), .A1(n9404), .B0(n9338), .Y(n1486) );
OAI21X4TS U6273 ( .A0(n9155), .A1(n3570), .B0(n3569), .Y(n9130) );
INVX2TS U6274 ( .A(n9174), .Y(n9210) );
OAI21X2TS U6275 ( .A0(n9215), .A1(n9212), .B0(n9213), .Y(n9174) );
CLKINVX1TS U6276 ( .A(add_x_2_n184), .Y(add_x_2_n185) );
NAND2BX4TS U6277 ( .AN(n8530), .B(n1638), .Y(add_x_2_n184) );
NAND2BX2TS U6278 ( .AN(n1500), .B(n3152), .Y(n8912) );
OAI2BB1X4TS U6279 ( .A0N(n5762), .A1N(n5763), .B0(n1501), .Y(n5721) );
NAND2BX1TS U6280 ( .AN(n5553), .B(n1505), .Y(n1504) );
INVX1TS U6281 ( .A(n1507), .Y(n1505) );
XOR2X1TS U6282 ( .A(n1507), .B(n5553), .Y(n1506) );
NAND2X2TS U6283 ( .A(n1509), .B(n1508), .Y(n1507) );
NAND2BX2TS U6284 ( .AN(n5563), .B(n6826), .Y(n1509) );
INVX2TS U6285 ( .A(n9314), .Y(n8167) );
OA21X4TS U6286 ( .A0(n9131), .A1(n9142), .B0(n9132), .Y(n1510) );
XOR2X4TS U6287 ( .A(n2857), .B(n1516), .Y(n2800) );
OAI2BB1X4TS U6288 ( .A0N(n2831), .A1N(n2830), .B0(n1517), .Y(n3114) );
XNOR2X1TS U6289 ( .A(n3647), .B(n608), .Y(n2914) );
INVX1TS U6290 ( .A(DP_OP_59J6_122_190_n112), .Y(DP_OP_59J6_122_190_n110) );
OAI21X2TS U6291 ( .A0(DP_OP_59J6_122_190_n136), .A1(n8108), .B0(n7185), .Y(
DP_OP_59J6_122_190_n112) );
OAI21X4TS U6292 ( .A0(n2585), .A1(n1520), .B0(n1519), .Y(n1594) );
XNOR2X1TS U6293 ( .A(n3717), .B(n608), .Y(n3265) );
XOR2X4TS U6294 ( .A(n1526), .B(n3165), .Y(n3717) );
OAI2BB1X4TS U6295 ( .A0N(n7179), .A1N(n7178), .B0(n1528), .Y(n7182) );
XNOR2X4TS U6296 ( .A(n1529), .B(n7177), .Y(n8106) );
XOR2X4TS U6297 ( .A(n7178), .B(n1530), .Y(n1529) );
INVX2TS U6298 ( .A(n8537), .Y(n1538) );
XOR2X4TS U6299 ( .A(n1549), .B(n4494), .Y(n4510) );
XNOR2X4TS U6300 ( .A(n6220), .B(n1562), .Y(n6253) );
OAI2BB1X4TS U6301 ( .A0N(n6229), .A1N(n6228), .B0(n1569), .Y(n6328) );
XOR2X4TS U6302 ( .A(n1570), .B(n6227), .Y(n6230) );
XOR2X4TS U6303 ( .A(n6228), .B(n6229), .Y(n1570) );
XOR2X4TS U6304 ( .A(n1572), .B(n1793), .Y(n5517) );
XOR2X4TS U6305 ( .A(n1792), .B(n1794), .Y(n1572) );
XOR2X4TS U6306 ( .A(n1576), .B(n7171), .Y(n7176) );
XOR2X4TS U6307 ( .A(n7172), .B(n7173), .Y(n1576) );
XOR2X1TS U6308 ( .A(n6921), .B(n395), .Y(n7475) );
XNOR2X1TS U6309 ( .A(n6921), .B(n200), .Y(n7440) );
XOR2X4TS U6310 ( .A(n8280), .B(n1584), .Y(n8921) );
XOR2X4TS U6311 ( .A(n8282), .B(n8281), .Y(n1584) );
NAND2X1TS U6312 ( .A(n7550), .B(n381), .Y(n1590) );
XOR2X4TS U6313 ( .A(n6918), .B(n196), .Y(n7550) );
OAI2BB1X4TS U6314 ( .A0N(n7633), .A1N(n7634), .B0(n1591), .Y(n8618) );
XOR2X4TS U6315 ( .A(n1592), .B(n7632), .Y(n7635) );
XOR2X4TS U6316 ( .A(n7634), .B(n7633), .Y(n1592) );
XNOR2X4TS U6317 ( .A(n3677), .B(n6859), .Y(n7104) );
XOR2X4TS U6318 ( .A(n1600), .B(n179), .Y(n6859) );
XOR2X4TS U6319 ( .A(n3642), .B(n1606), .Y(n8306) );
XOR2X4TS U6320 ( .A(n3641), .B(n3643), .Y(n1606) );
XOR2X4TS U6321 ( .A(Data_B_i[19]), .B(Data_B_i[20]), .Y(n1607) );
OAI2BB1X4TS U6322 ( .A0N(n8743), .A1N(n8742), .B0(n1608), .Y(n8733) );
OAI2BB1X4TS U6323 ( .A0N(n7512), .A1N(n7511), .B0(n1610), .Y(n8830) );
NAND3BX4TS U6324 ( .AN(n8083), .B(n5928), .C(n8501), .Y(n1612) );
OAI21X4TS U6325 ( .A0(n1632), .A1(n1633), .B0(n1630), .Y(n4764) );
OAI21X4TS U6326 ( .A0(n1631), .A1(Data_B_i[9]), .B0(n1633), .Y(n1630) );
NAND2X1TS U6327 ( .A(n5186), .B(n5160), .Y(n1643) );
XNOR2X4TS U6328 ( .A(n335), .B(n712), .Y(n1646) );
OAI2BB1X4TS U6329 ( .A0N(n6116), .A1N(n6115), .B0(n1650), .Y(n6683) );
XOR2X4TS U6330 ( .A(n5515), .B(n1657), .Y(n7798) );
XOR2X4TS U6331 ( .A(n5516), .B(n1658), .Y(n1657) );
XOR2X4TS U6332 ( .A(n1659), .B(n5483), .Y(n1658) );
XOR2X2TS U6333 ( .A(n5484), .B(n5482), .Y(n1659) );
OAI2BB1X4TS U6334 ( .A0N(n5910), .A1N(n5909), .B0(n1667), .Y(n5912) );
XOR2X4TS U6335 ( .A(n1668), .B(n5908), .Y(n5918) );
XOR2X4TS U6336 ( .A(n5909), .B(n5910), .Y(n1668) );
XNOR2X4TS U6337 ( .A(n1673), .B(n3587), .Y(n3566) );
XOR2X4TS U6338 ( .A(n3586), .B(n1674), .Y(n1673) );
NAND2BXLTS U6339 ( .AN(n1679), .B(n3555), .Y(n3516) );
INVX2TS U6340 ( .A(n1680), .Y(n1679) );
XOR2X1TS U6341 ( .A(n3555), .B(n1680), .Y(n3556) );
XOR2X4TS U6342 ( .A(n4644), .B(n1684), .Y(n1683) );
XOR2X4TS U6343 ( .A(n4651), .B(n4650), .Y(n6485) );
ADDHX1TS U6344 ( .A(n4373), .B(n4372), .CO(n4494), .S(n4408) );
ADDFHX2TS U6345 ( .A(n7615), .B(n7614), .CI(n7613), .CO(n8605), .S(n7611) );
ADDFHX2TS U6346 ( .A(n3397), .B(n3396), .CI(n3395), .CO(n3475), .S(n3448) );
XOR2X2TS U6347 ( .A(n9319), .B(n9318), .Y(n9332) );
ADDFHX2TS U6348 ( .A(n4460), .B(n4459), .CI(n4458), .CO(n4694), .S(n4462) );
OAI22X2TS U6349 ( .A0(n4495), .A1(n473), .B0(n6410), .B1(n4405), .Y(n4459)
);
ADDFHX2TS U6350 ( .A(n3662), .B(n3661), .CI(n3660), .CO(n3667), .S(n3663) );
ADDFHX2TS U6351 ( .A(n2888), .B(n2887), .CI(n2886), .CO(n3539), .S(n3537) );
ADDFHX2TS U6352 ( .A(n7566), .B(n7565), .CI(n7564), .CO(n7533), .S(n7573) );
ADDFHX2TS U6353 ( .A(n5756), .B(n5755), .CI(n5754), .CO(n6801), .S(n6796) );
INVX4TS U6354 ( .A(n8300), .Y(n8333) );
ADDFHX2TS U6355 ( .A(n3278), .B(n3277), .CI(n3276), .CO(n7814), .S(n3329) );
ADDFHX2TS U6356 ( .A(n4686), .B(n4685), .CI(n4684), .CO(n6657), .S(n6653) );
ADDFHX2TS U6357 ( .A(n3040), .B(n3039), .CI(n3038), .CO(n3031), .S(n3050) );
ADDFHX2TS U6358 ( .A(n1829), .B(n1828), .CI(n1827), .CO(n1998), .S(n1821) );
ADDFHX2TS U6359 ( .A(n3241), .B(n3240), .CI(n3239), .CO(n3543), .S(n3542) );
XOR2X4TS U6360 ( .A(n7007), .B(n7006), .Y(n8276) );
NAND2X2TS U6361 ( .A(n8202), .B(n8201), .Y(n9667) );
OAI21X1TS U6362 ( .A0(n8488), .A1(n8484), .B0(n8485), .Y(n7248) );
ADDFHX2TS U6363 ( .A(n5330), .B(n5329), .CI(n5328), .CO(n5352), .S(n5349) );
ADDFHX2TS U6364 ( .A(n6533), .B(n6532), .CI(n6531), .CO(n6560), .S(n6535) );
NOR2X4TS U6365 ( .A(n6026), .B(n6025), .Y(n9652) );
ADDFHX2TS U6366 ( .A(n7822), .B(n7821), .CI(n7820), .CO(n7868), .S(n7819) );
ADDFHX4TS U6367 ( .A(n5871), .B(n5870), .CI(n5869), .CO(n5860), .S(n5898) );
ADDFHX2TS U6368 ( .A(n1868), .B(n1867), .CI(n1866), .CO(n2413), .S(n2294) );
ADDFHX2TS U6369 ( .A(n3018), .B(n3017), .CI(n3016), .CO(n3060), .S(n3059) );
ADDFHX4TS U6370 ( .A(n8693), .B(n8692), .CI(n8691), .CO(n8740), .S(n8689) );
ADDFHX2TS U6371 ( .A(n2314), .B(n2313), .CI(n2312), .CO(n2414), .S(n2328) );
OR2X1TS U6372 ( .A(n4545), .B(n4544), .Y(n4546) );
NOR2X1TS U6373 ( .A(n4364), .B(n4363), .Y(n7273) );
ADDFHX2TS U6374 ( .A(n2917), .B(n2916), .CI(n2915), .CO(n8784), .S(n8783) );
ADDFHX2TS U6375 ( .A(n3838), .B(n3837), .CI(n3836), .CO(n4375), .S(n3830) );
XOR2X4TS U6376 ( .A(n5172), .B(n5171), .Y(n6757) );
INVX4TS U6377 ( .A(n2108), .Y(n2090) );
NOR2X2TS U6378 ( .A(n9315), .B(n8171), .Y(n3591) );
NOR2X2TS U6379 ( .A(n7618), .B(n7617), .Y(n9315) );
NOR2X4TS U6380 ( .A(n9443), .B(n9442), .Y(n9501) );
ADDFHX2TS U6381 ( .A(n7095), .B(n7094), .CI(n7093), .CO(n7232), .S(n7054) );
ADDFHX2TS U6382 ( .A(n7091), .B(n7090), .CI(n7089), .CO(n7113), .S(n7094) );
ADDFHX2TS U6383 ( .A(n4761), .B(n4760), .CI(n4759), .CO(n4771), .S(n4766) );
NOR2X2TS U6384 ( .A(n9445), .B(n9444), .Y(n9468) );
ADDFHX2TS U6385 ( .A(n5419), .B(n5418), .CI(n5417), .CO(n9589), .S(n9580) );
ADDFHX2TS U6386 ( .A(n3296), .B(n3295), .CI(n3294), .CO(n7806), .S(n3292) );
OR2X4TS U6387 ( .A(n3053), .B(n3052), .Y(n8142) );
ADDFHX2TS U6388 ( .A(n3700), .B(n3699), .CI(n3698), .CO(n3708), .S(n3701) );
OR2X1TS U6389 ( .A(n8896), .B(n8895), .Y(n8897) );
ADDFHX4TS U6390 ( .A(n8333), .B(n8332), .CI(n8331), .CO(n8340), .S(n8696) );
ADDFHX2TS U6391 ( .A(n5713), .B(n5712), .CI(n5711), .CO(n5725), .S(n5767) );
INVX2TS U6392 ( .A(n11233), .Y(n7721) );
NAND2X1TS U6393 ( .A(add_x_3_n125), .B(n8472), .Y(add_x_3_n7) );
XOR2X2TS U6394 ( .A(n2070), .B(n2069), .Y(n2097) );
ADDFHX2TS U6395 ( .A(n9322), .B(n9321), .CI(n9320), .CO(n9330), .S(n9331) );
INVX2TS U6396 ( .A(n11227), .Y(n9321) );
ADDFHX2TS U6397 ( .A(n3394), .B(n3393), .CI(n3392), .CO(n3476), .S(n3449) );
ADDFHX2TS U6398 ( .A(n5440), .B(n5439), .CI(n5438), .CO(n5478), .S(n5409) );
INVX2TS U6399 ( .A(n9581), .Y(n5438) );
ADDFHX2TS U6400 ( .A(n6786), .B(n6785), .CI(n6784), .CO(n6814), .S(n6755) );
ADDFHX2TS U6401 ( .A(n6783), .B(n6782), .CI(n6781), .CO(n6835), .S(n6786) );
ADDFHX2TS U6402 ( .A(n3251), .B(n3250), .CI(n3249), .CO(n7816), .S(n3291) );
INVX2TS U6403 ( .A(n7969), .Y(n5868) );
ADDFHX2TS U6404 ( .A(n3969), .B(n3968), .CI(n3967), .CO(n3970), .S(n3963) );
ADDFHX2TS U6405 ( .A(n2534), .B(n2532), .CI(n2533), .CO(n5787), .S(n2548) );
ADDFHX2TS U6406 ( .A(n134), .B(n8249), .CI(n8248), .CO(n8587), .S(n8294) );
ADDFHX2TS U6407 ( .A(n2365), .B(n2364), .CI(n2363), .CO(n5360), .S(n5250) );
ADDFHX2TS U6408 ( .A(n2504), .B(n2503), .CI(n2502), .CO(n5802), .S(n2509) );
ADDFHX2TS U6409 ( .A(n3915), .B(n3914), .CI(n3913), .CO(n3951), .S(n3920) );
ADDFHX2TS U6410 ( .A(n8252), .B(n8251), .CI(n8250), .CO(n8586), .S(n8293) );
XOR2X4TS U6411 ( .A(n4843), .B(n4985), .Y(n6572) );
ADDFHX2TS U6412 ( .A(Data_A_i[15]), .B(n685), .CI(n2722), .CO(n2723), .S(
n2743) );
OAI22X2TS U6413 ( .A0(n2535), .A1(n5686), .B0(n579), .B1(n2453), .Y(n2499)
);
ADDFHX2TS U6414 ( .A(n3258), .B(n3257), .CI(n3256), .CO(n3562), .S(n3298) );
ADDFHX4TS U6415 ( .A(n7631), .B(n7630), .CI(n7629), .CO(n7636), .S(n7881) );
ADDFHX2TS U6416 ( .A(n8291), .B(n8290), .CI(n8289), .CO(n8297), .S(n8589) );
OR2X4TS U6417 ( .A(n9251), .B(n9250), .Y(n9343) );
OAI21X2TS U6418 ( .A0(n6999), .A1(n7003), .B0(n7004), .Y(n6871) );
ADDFHX2TS U6419 ( .A(n3646), .B(n3644), .CI(n3645), .CO(n8224), .S(n8304) );
ADDFHX2TS U6420 ( .A(n2825), .B(n2824), .CI(n2823), .CO(n2881), .S(n2988) );
CLKINVX2TS U6421 ( .A(n3532), .Y(n2823) );
OAI22X1TS U6422 ( .A0(n690), .A1(n7109), .B0(n7147), .B1(n417), .Y(n7148) );
ADDFHX2TS U6423 ( .A(n3873), .B(n3872), .CI(n3871), .CO(n3882), .S(n3957) );
ADDFHX2TS U6424 ( .A(n4184), .B(n4183), .CI(n4182), .CO(n4084), .S(n4193) );
XNOR2X4TS U6425 ( .A(n2027), .B(n2026), .Y(n5532) );
NAND2X2TS U6426 ( .A(n8901), .B(n8770), .Y(n7941) );
ADDFHX2TS U6427 ( .A(n6155), .B(n6154), .CI(n6153), .CO(n6195), .S(n6217) );
INVX2TS U6428 ( .A(n6683), .Y(n6153) );
ADDFHX2TS U6429 ( .A(n6292), .B(n6291), .CI(n6290), .CO(n6388), .S(n6286) );
ADDFHX2TS U6430 ( .A(Data_B_i[20]), .B(Data_B_i[47]), .CI(n1491), .CO(n2924),
.S(n2806) );
ADDFHX2TS U6431 ( .A(n3855), .B(n3854), .CI(n3853), .CO(n4127), .S(n4124) );
ADDFHX2TS U6432 ( .A(n7809), .B(n7808), .CI(n7807), .CO(n8802), .S(n8798) );
ADDFHX2TS U6433 ( .A(n7659), .B(n7658), .CI(n7657), .CO(n7808), .S(n7825) );
ADDFHX4TS U6434 ( .A(n5892), .B(n5891), .CI(n5890), .CO(n5899), .S(n5908) );
ADDFHX2TS U6435 ( .A(n292), .B(n646), .CI(n2813), .CO(n2783), .S(n2778) );
ADDFHX2TS U6436 ( .A(n6426), .B(n6425), .CI(n6424), .CO(n6462), .S(n6393) );
ADDFHX2TS U6437 ( .A(n3908), .B(n3907), .CI(n3906), .CO(n3955), .S(n3950) );
ADDFHX2TS U6438 ( .A(n6185), .B(n6184), .CI(n6183), .CO(n6322), .S(n6203) );
INVX2TS U6439 ( .A(n7268), .Y(n3062) );
ADDFHX2TS U6440 ( .A(n8178), .B(n8177), .CI(n8176), .CO(n9069), .S(n9328) );
ADDFHX2TS U6441 ( .A(n2311), .B(n2310), .CI(n2309), .CO(n2323), .S(n2320) );
ADDFHX2TS U6442 ( .A(n7668), .B(n7667), .CI(n7666), .CO(n7663), .S(n7898) );
ADDFHX2TS U6443 ( .A(n7167), .B(n7166), .CI(n7165), .CO(n8417), .S(n7169) );
ADDFHX2TS U6444 ( .A(n6396), .B(n6395), .CI(n6394), .CO(n7345), .S(n7324) );
ADDFHX2TS U6445 ( .A(Data_B_i[24]), .B(Data_B_i[51]), .CI(n6859), .CO(n6861),
.S(n3284) );
ADDFHX2TS U6446 ( .A(n5519), .B(n5520), .CI(n5518), .CO(n5866), .S(n5672) );
OAI2BB1X2TS U6447 ( .A0N(n3653), .A1N(n3652), .B0(n3651), .Y(n3670) );
ADDFHX2TS U6448 ( .A(n6721), .B(n6720), .CI(n6719), .CO(n6788), .S(n6703) );
AOI21X2TS U6449 ( .A0(n7002), .A1(n6868), .B0(n6871), .Y(n6867) );
ADDFHX2TS U6450 ( .A(n2419), .B(n2418), .CI(n2417), .CO(n2546), .S(n2422) );
ADDFHX2TS U6451 ( .A(n7806), .B(n7805), .CI(n7804), .CO(n7871), .S(n7817) );
ADDFHX2TS U6452 ( .A(n8593), .B(n8592), .CI(n8591), .CO(n8597), .S(n8582) );
ADDFHX2TS U6453 ( .A(n7499), .B(n7498), .CI(n7497), .CO(n7632), .S(n7664) );
OAI22X1TS U6454 ( .A0(n7441), .A1(n546), .B0(n8233), .B1(n7440), .Y(n7540)
);
ADDFHX2TS U6455 ( .A(n6181), .B(n6180), .CI(n6179), .CO(n6201), .S(n6225) );
NOR2X2TS U6456 ( .A(n3949), .B(n3948), .Y(n4310) );
ADDFHX2TS U6457 ( .A(n7043), .B(n7041), .CI(n7042), .CO(n7101), .S(n8359) );
ADDFHX2TS U6458 ( .A(n5535), .B(n5534), .CI(n5533), .CO(n5503), .S(n5635) );
NOR2X4TS U6459 ( .A(n3336), .B(n3335), .Y(n8903) );
XOR2X4TS U6460 ( .A(n7872), .B(n7837), .Y(n7841) );
XOR2X4TS U6461 ( .A(n7873), .B(n7874), .Y(n7837) );
ADDFHX2TS U6462 ( .A(n4703), .B(n4702), .CI(n4701), .CO(n4733), .S(n4736) );
ADDFHX2TS U6463 ( .A(n5494), .B(n5493), .CI(n5492), .CO(n5484), .S(n5550) );
NOR2X4TS U6464 ( .A(n5022), .B(n5021), .Y(n7976) );
ADDFHX2TS U6465 ( .A(n3688), .B(n3687), .CI(n3686), .CO(n3710), .S(n3698) );
ADDFHX2TS U6466 ( .A(n2222), .B(n2221), .CI(n2220), .CO(n2218), .S(n2230) );
OAI22X1TS U6467 ( .A0(n2384), .A1(n2350), .B0(n562), .B1(n517), .Y(n2379) );
ADDFHX2TS U6468 ( .A(n4161), .B(n4160), .CI(n4159), .CO(n4190), .S(n4185) );
ADDFHX2TS U6469 ( .A(n3216), .B(n3215), .CI(n3214), .CO(n3330), .S(n3245) );
ADDFHX2TS U6470 ( .A(n3075), .B(n3074), .CI(n3073), .CO(n3215), .S(n3066) );
ADDFHX2TS U6471 ( .A(n3078), .B(n3077), .CI(n3076), .CO(n3214), .S(n3065) );
ADDFHX2TS U6472 ( .A(n5954), .B(n5953), .CI(n5952), .CO(n6702), .S(n5976) );
ADDFHX2TS U6473 ( .A(n6443), .B(n6442), .CI(n6441), .CO(n6506), .S(n6467) );
ADDFHX4TS U6474 ( .A(n6436), .B(n6435), .CI(n6434), .CO(n6488), .S(n6443) );
ADDFHX2TS U6475 ( .A(n5725), .B(n5724), .CI(n5723), .CO(n5717), .S(n5765) );
ADDFHX2TS U6476 ( .A(n7645), .B(n7644), .CI(n7643), .CO(n7665), .S(n7885) );
INVX2TS U6477 ( .A(n7496), .Y(n7643) );
ADDFHX2TS U6478 ( .A(n3563), .B(n3562), .CI(n3561), .CO(n3567), .S(n3565) );
ADDFHX2TS U6479 ( .A(n3560), .B(n3559), .CI(n3558), .CO(n3586), .S(n3561) );
ADDFHX2TS U6480 ( .A(n5208), .B(n5207), .CI(n5206), .CO(n5331), .S(n5328) );
ADDFHX2TS U6481 ( .A(n9181), .B(n9180), .CI(n9179), .CO(n9250), .S(n9249) );
ADDFHX2TS U6482 ( .A(n6208), .B(n6207), .CI(n6206), .CO(n6278), .S(n6232) );
ADDFHX2TS U6483 ( .A(n7853), .B(n7852), .CI(n7851), .CO(n7897), .S(n7890) );
ADDFHX2TS U6484 ( .A(n9123), .B(n9302), .CI(n9301), .CO(n9304), .S(n9275) );
ADDFHX2TS U6485 ( .A(n2214), .B(n2213), .CI(n2212), .CO(n2322), .S(n2221) );
NAND2X2TS U6486 ( .A(n5085), .B(n5084), .Y(n6266) );
ADDFHX2TS U6487 ( .A(n8454), .B(n8453), .CI(n8452), .CO(n8455), .S(n8723) );
ADDFHX2TS U6488 ( .A(n4034), .B(n4033), .CI(n4032), .CO(n4223), .S(n4044) );
ADDFHX2TS U6489 ( .A(n7584), .B(n7583), .CI(n7582), .CO(n7587), .S(n7660) );
ADDFHX2TS U6490 ( .A(n7022), .B(n7021), .CI(n7020), .CO(n7041), .S(n8346) );
NAND2X2TS U6491 ( .A(n4929), .B(n4928), .Y(n8485) );
NAND2X1TS U6492 ( .A(n9056), .B(n8494), .Y(DP_OP_59J6_122_190_n55) );
ADDFHX2TS U6493 ( .A(n9255), .B(n9254), .CI(n9253), .CO(n9261), .S(n9260) );
ADDFHX2TS U6494 ( .A(n8345), .B(n8344), .CI(n8343), .CO(n8357), .S(n8336) );
ADDFHX2TS U6495 ( .A(n5359), .B(n5358), .CI(n5357), .CO(n5402), .S(n5392) );
ADDFHX2TS U6496 ( .A(n5362), .B(n5361), .CI(n9578), .CO(n5442), .S(n5358) );
ADDFHX2TS U6497 ( .A(n5365), .B(n5364), .CI(n5363), .CO(n5441), .S(n5359) );
ADDFHX2TS U6498 ( .A(n4809), .B(n4810), .CI(n4808), .CO(n4974), .S(n4826) );
ADDFHX2TS U6499 ( .A(n6326), .B(n6325), .CI(n6324), .CO(n6350), .S(n6329) );
ADDFHX2TS U6500 ( .A(n7609), .B(n7608), .CI(n7607), .CO(n7634), .S(n7629) );
ADDFHX2TS U6501 ( .A(n8625), .B(n8624), .CI(n8623), .CO(n8632), .S(n8637) );
AO21X1TS U6502 ( .A0(n582), .A1(n498), .B0(n5382), .Y(n5422) );
ADDFHX2TS U6503 ( .A(n5821), .B(n5820), .CI(n5819), .CO(n5827), .S(n5830) );
ADDFHX2TS U6504 ( .A(n238), .B(n281), .CI(n3629), .CO(n3122), .S(n2925) );
ADDFHX2TS U6505 ( .A(n5972), .B(n5971), .CI(n5970), .CO(n9614), .S(n9609) );
ADDFHX2TS U6506 ( .A(n5969), .B(n5968), .CI(n5967), .CO(n6733), .S(n5971) );
NOR2X1TS U6507 ( .A(n6054), .B(n535), .Y(n6124) );
ADDFHX2TS U6508 ( .A(n6460), .B(n6459), .CI(n6458), .CO(n7349), .S(n7344) );
ADDFHX2TS U6509 ( .A(n6457), .B(n6455), .CI(n6456), .CO(n6495), .S(n6459) );
ADDFHX2TS U6510 ( .A(n5917), .B(n5916), .CI(n5915), .CO(n5921), .S(n5849) );
AOI21X4TS U6511 ( .A0(n9075), .A1(n1973), .B0(n1972), .Y(n2108) );
ADDFHX2TS U6512 ( .A(n1791), .B(n1790), .CI(n1789), .CO(n1820), .S(n1794) );
ADDFHX2TS U6513 ( .A(n3238), .B(n3237), .CI(n3236), .CO(n3307), .S(n3195) );
ADDFHX2TS U6514 ( .A(n7572), .B(n7571), .CI(n7570), .CO(n8814), .S(n8805) );
ADDFHX2TS U6515 ( .A(n5049), .B(n5048), .CI(n6029), .CO(n6037), .S(n5047) );
AOI21X2TS U6516 ( .A0(n4992), .A1(n4991), .B0(n4990), .Y(n6599) );
INVX2TS U6517 ( .A(n6339), .Y(n3907) );
ADDFHX2TS U6518 ( .A(n7624), .B(n7623), .CI(n7622), .CO(n8615), .S(n7627) );
ADDFHX2TS U6519 ( .A(n5455), .B(n5454), .CI(n5453), .CO(n9610), .S(n9590) );
ADDFHX2TS U6520 ( .A(n2790), .B(n2789), .CI(n2788), .CO(n8782), .S(n8780) );
ADDFHX2TS U6521 ( .A(n9325), .B(n9324), .CI(n9323), .CO(n9326), .S(n9305) );
ADDFHX2TS U6522 ( .A(n5289), .B(n5288), .CI(n5287), .CO(n9558), .S(n8197) );
ADDFHX2TS U6523 ( .A(n4432), .B(n4431), .CI(n4430), .CO(n6421), .S(n6358) );
ADDFHX2TS U6524 ( .A(n6323), .B(n6322), .CI(n6321), .CO(n6351), .S(n6280) );
ADDFHX2TS U6525 ( .A(n6283), .B(n6282), .CI(n6281), .CO(n6349), .S(n6321) );
ADDFHX2TS U6526 ( .A(n1835), .B(n1834), .CI(n1833), .CO(n5286), .S(n5524) );
ADDFHX4TS U6527 ( .A(n5305), .B(n5306), .CI(n5307), .CO(n5345), .S(n5870) );
ADDFHX2TS U6528 ( .A(n5295), .B(n5294), .CI(n5293), .CO(n5335), .S(n5306) );
ADDFHX2TS U6529 ( .A(n3674), .B(n3673), .CI(n3672), .CO(n3702), .S(n3669) );
ADDFHX2TS U6530 ( .A(n6738), .B(n6737), .CI(n6736), .CO(n7200), .S(n5950) );
ADDFHX2TS U6531 ( .A(n2573), .B(n2572), .CI(n2571), .CO(n6737), .S(n2567) );
AOI21X2TS U6532 ( .A0(n5186), .A1(n5164), .B0(n5163), .Y(n7783) );
ADDFHX2TS U6533 ( .A(n6124), .B(n6123), .CI(n6122), .CO(n6059), .S(n6129) );
ADDFHX2TS U6534 ( .A(n5663), .B(n5662), .CI(n5661), .CO(n5864), .S(n5668) );
ADDFHX2TS U6535 ( .A(n9333), .B(n9332), .CI(n9331), .CO(n9334), .S(n9327) );
ADDFHX2TS U6536 ( .A(n5646), .B(n5645), .CI(n5644), .CO(n5907), .S(n5718) );
ADDFHX2TS U6537 ( .A(n5632), .B(n5631), .CI(n5630), .CO(n5644), .S(n5724) );
ADDFHX2TS U6538 ( .A(n3605), .B(n3604), .CI(n3603), .CO(n3622), .S(n3618) );
NOR2X2TS U6539 ( .A(n6842), .B(n6841), .Y(n7944) );
ADDFHX2TS U6540 ( .A(n5595), .B(n5594), .CI(n5593), .CO(n5646), .S(n5679) );
ADDFHX2TS U6541 ( .A(n6513), .B(n6512), .CI(n6511), .CO(n6542), .S(n6537) );
ADDFHX2TS U6542 ( .A(n5055), .B(n5054), .CI(n5053), .CO(n6035), .S(n5028) );
ADDFHX2TS U6543 ( .A(n7144), .B(n7143), .CI(n8936), .CO(n8440), .S(n7157) );
ADDFHX2TS U6544 ( .A(n6092), .B(n6091), .CI(n6090), .CO(n6108), .S(n6151) );
ADDFHX2TS U6545 ( .A(n3549), .B(n3548), .CI(n3547), .CO(n3582), .S(n3588) );
ADDFHX2TS U6546 ( .A(n4747), .B(n4746), .CI(n4745), .CO(n4748), .S(n4515) );
ADDFHX2TS U6547 ( .A(n4963), .B(n4962), .CI(n4961), .CO(n5053), .S(n4965) );
ADDFHX2TS U6548 ( .A(n1962), .B(n1961), .CI(n1960), .CO(n1967), .S(n1969) );
ADDFHX2TS U6549 ( .A(n2189), .B(n2188), .CI(n2187), .CO(n2214), .S(n2209) );
ADDFHX2TS U6550 ( .A(n4637), .B(n4636), .CI(n4635), .CO(n4685), .S(n4621) );
ADDFHX2TS U6551 ( .A(n3640), .B(n3639), .CI(n3638), .CO(n3660), .S(n3620) );
ADDFHX2TS U6552 ( .A(n7847), .B(n7846), .CI(n7845), .CO(n7892), .S(n7866) );
ADDFHX2TS U6553 ( .A(n2460), .B(n2459), .CI(n2458), .CO(n2461), .S(n2330) );
ADDFHX2TS U6554 ( .A(n7126), .B(n7125), .CI(n7124), .CO(n7172), .S(n7142) );
ADDFHX2TS U6555 ( .A(n3419), .B(n3454), .CI(n3418), .CO(n3459), .S(n3426) );
ADDFHX2TS U6556 ( .A(n2510), .B(n2509), .CI(n2508), .CO(n5823), .S(n2549) );
ADDFHX2TS U6557 ( .A(n5695), .B(n5694), .CI(n5693), .CO(n5755), .S(n5735) );
ADDFHX2TS U6558 ( .A(n320), .B(n5203), .CI(n3677), .CO(n3285), .S(n3204) );
ADDFHX2TS U6559 ( .A(n7419), .B(n7418), .CI(n7417), .CO(n8614), .S(n7633) );
ADDFHX2TS U6560 ( .A(n4690), .B(n4689), .CI(n4688), .CO(n4864), .S(n4710) );
ADDFHX2TS U6561 ( .A(n4593), .B(n4592), .CI(n4591), .CO(n4798), .S(n4688) );
NOR2X4TS U6562 ( .A(n4352), .B(n4351), .Y(n9288) );
ADDFHX2TS U6563 ( .A(n6219), .B(n6218), .CI(n6217), .CO(n6229), .S(n6246) );
ADDFHX2TS U6564 ( .A(n4959), .B(n4960), .CI(n4958), .CO(n5054), .S(n4973) );
ADDFHX2TS U6565 ( .A(n7612), .B(n7611), .CI(n7610), .CO(n8646), .S(n7681) );
ADDFHX2TS U6566 ( .A(n7569), .B(n7568), .CI(n7567), .CO(n7610), .S(n7883) );
ADDFHX2TS U6567 ( .A(n7081), .B(n7080), .CI(n7079), .CO(n7141), .S(n7102) );
ADDFHX2TS U6568 ( .A(n4230), .B(n4229), .CI(n4228), .CO(n4248), .S(n4227) );
NOR2X2TS U6569 ( .A(n7625), .B(n7412), .Y(n9296) );
ADDFHX2TS U6570 ( .A(n1878), .B(n1877), .CI(n1876), .CO(n2260), .S(n2277) );
ADDHX1TS U6571 ( .A(n1883), .B(n1882), .CO(n1877), .S(n1897) );
ADDFHX2TS U6572 ( .A(n6407), .B(n6406), .CI(n6405), .CO(n6466), .S(n6428) );
ADDFHX2TS U6573 ( .A(n6361), .B(n6360), .CI(n6359), .CO(n6406), .S(n6354) );
ADDFHX2TS U6574 ( .A(n3331), .B(n3330), .CI(n3329), .CO(n7838), .S(n3332) );
ADDFHX2TS U6575 ( .A(n3281), .B(n3279), .CI(n3280), .CO(n8795), .S(n8792) );
ADDFHX2TS U6576 ( .A(n3221), .B(n3220), .CI(n3219), .CO(n3281), .S(n3193) );
ADDFHX2TS U6577 ( .A(n7676), .B(n7675), .CI(n7674), .CO(n8804), .S(n8803) );
ADDFHX2TS U6578 ( .A(n7662), .B(n7660), .CI(n7661), .CO(n7675), .S(n7807) );
ADDFHX2TS U6579 ( .A(n7465), .B(n7464), .CI(n7463), .CO(n8628), .S(n7418) );
INVX2TS U6580 ( .A(n2559), .Y(n2407) );
OAI21X2TS U6581 ( .A0(n9086), .A1(n1953), .B0(n1952), .Y(n9075) );
XOR2X4TS U6582 ( .A(n3206), .B(n3205), .Y(n8311) );
ADDFHX2TS U6583 ( .A(n5409), .B(n5408), .CI(n5407), .CO(n5452), .S(n5406) );
ADDFHX2TS U6584 ( .A(n5619), .B(n5618), .CI(n5617), .CO(n5600), .S(n5705) );
ADDFHX2TS U6585 ( .A(n2548), .B(n2546), .CI(n2547), .CO(n5816), .S(n2551) );
ADDFHX2TS U6586 ( .A(n5818), .B(n5817), .CI(n5816), .CO(n5831), .S(n5822) );
ADDFHX2TS U6587 ( .A(n5788), .B(n5787), .CI(n5786), .CO(n5813), .S(n5817) );
ADDFHX2TS U6588 ( .A(n5800), .B(n5799), .CI(n5798), .CO(n5809), .S(n5820) );
ADDFHX2TS U6589 ( .A(n5773), .B(n5772), .CI(n5771), .CO(n5779), .S(n5799) );
ADDFHX2TS U6590 ( .A(n4640), .B(n4639), .CI(n4638), .CO(n4589), .S(n4684) );
ADDFHX2TS U6591 ( .A(n4565), .B(n4564), .CI(n4563), .CO(n4604), .S(n4639) );
ADDFHX2TS U6592 ( .A(n5353), .B(n5352), .CI(n5351), .CO(n5393), .S(n5855) );
XOR2X4TS U6593 ( .A(n2530), .B(n2529), .Y(n5948) );
ADDFHX2TS U6594 ( .A(n1816), .B(n1815), .CI(n1814), .CO(n1995), .S(n1822) );
ADDFHX2TS U6595 ( .A(n3870), .B(n3869), .CI(n3868), .CO(n3880), .S(n3958) );
ADDFHX2TS U6596 ( .A(n7122), .B(n7121), .CI(n7120), .CO(n7156), .S(n7134) );
XOR2X4TS U6597 ( .A(n3727), .B(n3726), .Y(n6314) );
ADDFHX2TS U6598 ( .A(n5635), .B(n5634), .CI(n5633), .CO(n7797), .S(n7762) );
ADDFHX2TS U6599 ( .A(n5551), .B(n5550), .CI(n5549), .CO(n5516), .S(n5633) );
ADDFHX2TS U6600 ( .A(n3458), .B(n3457), .CI(n3456), .CO(n3604), .S(n3464) );
ADDFHX2TS U6601 ( .A(n5000), .B(n4998), .CI(n4999), .CO(n5061), .S(n4996) );
ADDFHX2TS U6602 ( .A(n8272), .B(n8271), .CI(n8270), .CO(n8221), .S(n8280) );
ADDFHX2TS U6603 ( .A(n5768), .B(n5767), .CI(n5766), .CO(n5761), .S(n5794) );
ADDFHX2TS U6604 ( .A(n9258), .B(n9257), .CI(n9256), .CO(n9259), .S(n9251) );
XOR2X4TS U6605 ( .A(n214), .B(n2029), .Y(n5620) );
ADDFHX2TS U6606 ( .A(n7865), .B(n7864), .CI(n7863), .CO(n7886), .S(n7887) );
ADDFHX2TS U6607 ( .A(n3246), .B(n3245), .CI(n3244), .CO(n3247), .S(n3152) );
ADDFHX2TS U6608 ( .A(n3067), .B(n3066), .CI(n3065), .CO(n3246), .S(n3148) );
OR2X8TS U6609 ( .A(n8070), .B(n8069), .Y(n8382) );
NAND2X2TS U6610 ( .A(n8070), .B(n8069), .Y(n8383) );
ADDFHX2TS U6611 ( .A(n8687), .B(n8686), .CI(n8685), .CO(n8751), .S(n8708) );
ADDFHX2TS U6612 ( .A(n8699), .B(n8698), .CI(n8697), .CO(n8737), .S(n8687) );
ADDFHX2TS U6613 ( .A(n1937), .B(n1936), .CI(n1935), .CO(n1962), .S(n1933) );
ADDFHX2TS U6614 ( .A(n9148), .B(n9147), .CI(n9146), .CO(n9263), .S(n9262) );
ADDFHX2TS U6615 ( .A(n7029), .B(n7028), .CI(n7027), .CO(n7080), .S(n7043) );
XOR2X4TS U6616 ( .A(n3819), .B(n3818), .Y(n6186) );
AOI21X2TS U6617 ( .A0(n3814), .A1(n3813), .B0(n3812), .Y(n3819) );
ADDFHX2TS U6618 ( .A(n8155), .B(n8154), .CI(n8153), .CO(n9066), .S(n9067) );
ADDFHX2TS U6619 ( .A(n3108), .B(n3107), .CI(n3106), .CO(n3194), .S(n3080) );
ADDFHX2TS U6620 ( .A(n7933), .B(n7931), .CI(n7932), .CO(n7936), .S(n7879) );
ADDFHX2TS U6621 ( .A(n2390), .B(n2389), .CI(n2388), .CO(n5426), .S(n5388) );
ADDFHX2TS U6622 ( .A(n2362), .B(n2361), .CI(n2360), .CO(n2388), .S(n2363) );
XOR2X4TS U6623 ( .A(n3125), .B(n3124), .Y(n8225) );
ADDFHX2TS U6624 ( .A(n8339), .B(n8338), .CI(n8337), .CO(n8360), .S(n8354) );
ADDFHX2TS U6625 ( .A(n6152), .B(n6151), .CI(n6150), .CO(n6141), .S(n6158) );
ADDFHX2TS U6626 ( .A(n1852), .B(n1851), .CI(n1850), .CO(n1915), .S(n1857) );
ADDFHX2TS U6627 ( .A(n1968), .B(n1967), .CI(n1966), .CO(n5602), .S(n5629) );
ADDFHX2TS U6628 ( .A(n2500), .B(n2499), .CI(n2498), .CO(n5775), .S(n2502) );
ADDFHX2TS U6629 ( .A(n4478), .B(n4477), .CI(n4476), .CO(n4622), .S(n4505) );
ADDFHX2TS U6630 ( .A(n2828), .B(n2827), .CI(n2826), .CO(n3115), .S(n2976) );
ADDFHX2TS U6631 ( .A(n3129), .B(n3128), .CI(n3127), .CO(n3212), .S(n3113) );
ADDFHX2TS U6632 ( .A(n7621), .B(n7620), .CI(n7619), .CO(n8828), .S(n8815) );
ADDFHX2TS U6633 ( .A(n7603), .B(n7602), .CI(n7601), .CO(n7620), .S(n7570) );
ADDFHX2TS U6634 ( .A(n4287), .B(n4286), .CI(n4285), .CO(n6369), .S(n6320) );
ADDFHX2TS U6635 ( .A(n4265), .B(n4264), .CI(n4263), .CO(n4285), .S(n4247) );
ADDFHX2TS U6636 ( .A(n5061), .B(n5060), .CI(n5059), .CO(n6264), .S(n5081) );
ADDFHX2TS U6637 ( .A(n5064), .B(n5063), .CI(n5062), .CO(n6256), .S(n5060) );
ADDFHX2TS U6638 ( .A(n5750), .B(n5749), .CI(n5748), .CO(n5747), .S(n5806) );
ADDFHX2TS U6639 ( .A(n6947), .B(n6946), .CI(n6948), .CO(n6928), .S(n6957) );
ADDFHX2TS U6640 ( .A(n5613), .B(n5612), .CI(n5611), .CO(n5619), .S(n5697) );
ADDFHX2TS U6641 ( .A(n7112), .B(n7111), .CI(n7110), .CO(n7151), .S(n7114) );
ADDFHX2TS U6642 ( .A(n8491), .B(n8490), .CI(n8489), .CO(
DP_OP_62J6_125_4796_n550), .S(DP_OP_62J6_125_4796_n551) );
XOR2X4TS U6643 ( .A(n3754), .B(n3753), .Y(n6053) );
ADDFHX2TS U6644 ( .A(n6953), .B(n6952), .CI(n6951), .CO(n6944), .S(n8272) );
ADDFHX2TS U6645 ( .A(n4103), .B(n4102), .CI(n4101), .CO(n4112), .S(n4113) );
ADDFHX2TS U6646 ( .A(n6773), .B(n6772), .CI(n6771), .CO(n6839), .S(n6789) );
ADDFHX2TS U6647 ( .A(n3497), .B(n3496), .CI(n3495), .CO(n3479), .S(n3498) );
NAND2X1TS U6648 ( .A(n3772), .B(n3771), .Y(n3774) );
XOR2X4TS U6649 ( .A(n3724), .B(n3723), .Y(n8007) );
ADDFHX2TS U6650 ( .A(n5824), .B(n5823), .CI(n5822), .CO(n5833), .S(n2553) );
ADDFHX2TS U6651 ( .A(n1956), .B(n1955), .CI(n1954), .CO(n5660), .S(n5636) );
ADDFHX2TS U6652 ( .A(n5791), .B(n5790), .CI(n5789), .CO(n5764), .S(n5792) );
ADDFHX2TS U6653 ( .A(n7163), .B(n7162), .CI(n7161), .CO(n8943), .S(n8936) );
ADDFHX2TS U6654 ( .A(n6938), .B(n6937), .CI(n6936), .CO(n7032), .S(n6929) );
ADDFHX2TS U6655 ( .A(n5895), .B(n5894), .CI(n5893), .CO(n5858), .S(n5896) );
ADDFHX2TS U6656 ( .A(n7606), .B(n7605), .CI(n7604), .CO(n7511), .S(n7619) );
XNOR2X2TS U6657 ( .A(n245), .B(Data_A_i[33]), .Y(n1861) );
ADDFHX2TS U6658 ( .A(n6238), .B(n6236), .CI(n6237), .CO(n6259), .S(n6255) );
OAI21X1TS U6659 ( .A0(n3658), .A1(n3659), .B0(n3656), .Y(n3657) );
OAI2BB1X1TS U6660 ( .A0N(n3659), .A1N(n3658), .B0(n3657), .Y(n3672) );
ADDFHX2TS U6661 ( .A(n4718), .B(n4717), .CI(n4716), .CO(n4725), .S(n4740) );
ADDFHX2TS U6662 ( .A(n6565), .B(n6564), .CI(n6563), .CO(n6566), .S(n6541) );
XOR2X4TS U6663 ( .A(n2184), .B(n2183), .Y(n5637) );
ADDFHX2TS U6664 ( .A(n2172), .B(n2171), .CI(n2170), .CO(n5989), .S(n5988) );
ADDFHX2TS U6665 ( .A(n6753), .B(n6752), .CI(n6751), .CO(n6791), .S(n6747) );
ADDFHX2TS U6666 ( .A(n6789), .B(n6788), .CI(n6787), .CO(n6811), .S(n6751) );
ADDFHX4TS U6667 ( .A(n2136), .B(n2135), .CI(n2134), .CO(n5340), .S(n5182) );
ADDFHX2TS U6668 ( .A(n6329), .B(n6328), .CI(n6327), .CO(n6605), .S(n6277) );
ADDFHX2TS U6669 ( .A(n5809), .B(n5808), .CI(n5807), .CO(n5793), .S(n5828) );
OAI22X1TS U6670 ( .A0(n7105), .A1(n7086), .B0(n539), .B1(n7103), .Y(n7112)
);
XOR2X4TS U6671 ( .A(n3737), .B(n3736), .Y(n6370) );
ADDFHX2TS U6672 ( .A(n2427), .B(n2426), .CI(n2425), .CO(n2505), .S(n2456) );
ADDFHX2TS U6673 ( .A(n6232), .B(n6231), .CI(n6230), .CO(n6276), .S(n6275) );
ADDFHX2TS U6674 ( .A(n4709), .B(n4708), .CI(n4707), .CO(n4731), .S(n4735) );
ADDFHX2TS U6675 ( .A(n5254), .B(n5253), .CI(n5252), .CO(n5302), .S(n5523) );
OAI22X1TS U6676 ( .A0(n5539), .A1(n5262), .B0(n558), .B1(n5125), .Y(n5265)
);
NAND2X4TS U6677 ( .A(n5120), .B(n6728), .Y(n5539) );
ADDFHX2TS U6678 ( .A(n4043), .B(n4042), .CI(n4041), .CO(n4210), .S(n4046) );
NOR2X2TS U6679 ( .A(n3248), .B(n3247), .Y(n8915) );
ADDFHX2TS U6680 ( .A(n3334), .B(n3333), .CI(n3332), .CO(n3335), .S(n3248) );
ADDFHX2TS U6681 ( .A(n2153), .B(n2152), .CI(n2151), .CO(n2346), .S(n2138) );
ADDFHX2TS U6682 ( .A(n6107), .B(n6106), .CI(n6105), .CO(n6308), .S(n6110) );
ADDFHX2TS U6683 ( .A(n5616), .B(n5615), .CI(n5614), .CO(n5696), .S(n5737) );
ADDFHX2TS U6684 ( .A(n295), .B(n315), .CI(n6963), .CO(n6968), .S(n6965) );
ADDFHX2TS U6685 ( .A(n5268), .B(n5267), .CI(n5266), .CO(n5288), .S(n5521) );
ADDFHX2TS U6686 ( .A(n5304), .B(n5303), .CI(n5302), .CO(n5312), .S(n5287) );
NOR2BX2TS U6687 ( .AN(n625), .B(n8243), .Y(n8772) );
XOR2X4TS U6688 ( .A(n2676), .B(n2675), .Y(n7447) );
ADDFHX2TS U6689 ( .A(n2545), .B(n2544), .CI(n2543), .CO(n6002), .S(n6000) );
ADDFHX2TS U6690 ( .A(n2518), .B(n2517), .CI(n2516), .CO(n5736), .S(n2543) );
ADDFHX2TS U6691 ( .A(n6378), .B(n6377), .CI(n6376), .CO(n6395), .S(n6379) );
ADDFHX2TS U6692 ( .A(n6510), .B(n6509), .CI(n6508), .CO(n6617), .S(n6614) );
ADDFHX2TS U6693 ( .A(n6539), .B(n6538), .CI(n6537), .CO(n6540), .S(n6509) );
XOR2X2TS U6694 ( .A(n7718), .B(n7717), .Y(n9065) );
ADDFHX4TS U6695 ( .A(n8634), .B(n8632), .CI(n8633), .CO(n8695), .S(n8691) );
ADDFHX2TS U6696 ( .A(n5608), .B(n5607), .CI(n5606), .CO(n5591), .S(n5707) );
XOR2X4TS U6697 ( .A(n2650), .B(n2649), .Y(n7467) );
ADDFHX2TS U6698 ( .A(n4590), .B(n4589), .CI(n4588), .CO(n6659), .S(n6658) );
ADDFHX2TS U6699 ( .A(n4604), .B(n4603), .CI(n4602), .CO(n4801), .S(n4588) );
XNOR2X4TS U6700 ( .A(n3742), .B(n3743), .Y(n6050) );
INVX2TS U6701 ( .A(n2716), .Y(n2727) );
ADDFHX2TS U6702 ( .A(n5588), .B(n5589), .CI(n5587), .CO(n5592), .S(n5617) );
NAND2X2TS U6703 ( .A(n5934), .B(n5933), .Y(n6745) );
ADDFHX2TS U6704 ( .A(n5940), .B(n5939), .CI(n5938), .CO(n5978), .S(n5933) );
ADDFHX2TS U6705 ( .A(n4634), .B(n4633), .CI(n4632), .CO(n4603), .S(n4686) );
INVX1TS U6706 ( .A(n7470), .Y(n6902) );
XNOR2X1TS U6707 ( .A(n7470), .B(n134), .Y(n2956) );
ADDFHX2TS U6708 ( .A(n1947), .B(n1946), .CI(n1945), .CO(n5681), .S(n5757) );
ADDFHX2TS U6709 ( .A(n1917), .B(n1916), .CI(n1915), .CO(n1946), .S(n1948) );
ADDFHX2TS U6710 ( .A(n5692), .B(n5691), .CI(n5690), .CO(n5618), .S(n5756) );
ADDFHX2TS U6711 ( .A(n5301), .B(n5300), .CI(n5299), .CO(n5290), .S(n5313) );
ADDFHX2TS U6712 ( .A(n4607), .B(n4606), .CI(n4605), .CO(n4817), .S(n4602) );
NOR2X1TS U6713 ( .A(n2941), .B(n2266), .Y(n2267) );
ADDFHX2TS U6714 ( .A(n6349), .B(n6348), .CI(n6347), .CO(n6470), .S(n6472) );
ADDFHX2TS U6715 ( .A(n6390), .B(n6389), .CI(n6388), .CO(n6391), .S(n6347) );
XNOR2X1TS U6716 ( .A(n9996), .B(n9995), .Y(n1689) );
INVX2TS U6717 ( .A(n10975), .Y(n9903) );
INVX2TS U6718 ( .A(n10212), .Y(n9888) );
INVX2TS U6719 ( .A(n10143), .Y(n9908) );
INVX2TS U6720 ( .A(n10128), .Y(n9808) );
AND2X2TS U6721 ( .A(n3377), .B(n3376), .Y(n1690) );
XNOR2X1TS U6722 ( .A(n9858), .B(n9823), .Y(n1695) );
INVX2TS U6723 ( .A(n3175), .Y(n3118) );
XNOR2X1TS U6724 ( .A(n9713), .B(n9712), .Y(n1700) );
INVX2TS U6725 ( .A(n9954), .Y(n9798) );
INVX2TS U6726 ( .A(n9952), .Y(n9795) );
XNOR2X1TS U6727 ( .A(n9821), .B(n11392), .Y(n1701) );
INVX2TS U6728 ( .A(n10099), .Y(n9793) );
XNOR2X1TS U6729 ( .A(n10283), .B(n11569), .Y(n1702) );
INVX2TS U6730 ( .A(n10788), .Y(n10789) );
OR2X1TS U6731 ( .A(n6653), .B(n6652), .Y(n1707) );
OR2X2TS U6732 ( .A(n8931), .B(n8930), .Y(n1709) );
XNOR2X1TS U6733 ( .A(n9402), .B(n9401), .Y(n1710) );
XNOR2X1TS U6734 ( .A(n9535), .B(n9534), .Y(n1714) );
XNOR2X1TS U6735 ( .A(n7352), .B(n7351), .Y(n1715) );
XNOR2X1TS U6736 ( .A(n7327), .B(n7326), .Y(n1716) );
XNOR2X1TS U6737 ( .A(n7318), .B(n7317), .Y(n1717) );
XNOR2X1TS U6738 ( .A(n9592), .B(n9591), .Y(n1721) );
XNOR2X1TS U6739 ( .A(n9694), .B(n9693), .Y(n1723) );
XNOR2X1TS U6740 ( .A(n9617), .B(n9616), .Y(n1725) );
XNOR2X1TS U6741 ( .A(n9583), .B(n9582), .Y(n1726) );
NOR2XLTS U6742 ( .A(n5165), .B(n5187), .Y(n5167) );
NOR2XLTS U6743 ( .A(n5196), .B(n5194), .Y(n5276) );
NOR2XLTS U6744 ( .A(n10105), .B(n10106), .Y(n10111) );
ADDFHX2TS U6745 ( .A(n4410), .B(n4409), .CI(n4408), .CO(n4465), .S(n4412) );
NOR2XLTS U6746 ( .A(n9833), .B(n9832), .Y(n9743) );
NOR2XLTS U6747 ( .A(n2785), .B(n2784), .Y(n2786) );
INVX2TS U6748 ( .A(n7324), .Y(n6436) );
ADDFHX2TS U6749 ( .A(n5782), .B(n5781), .CI(n5780), .CO(n5815), .S(n5818) );
NOR2XLTS U6750 ( .A(n9889), .B(n11445), .Y(n9866) );
AO21X1TS U6751 ( .A0(n568), .A1(n8308), .B0(n8307), .Y(n8275) );
OAI21X1TS U6752 ( .A0(n7457), .A1(n7456), .B0(n7459), .Y(n7426) );
OAI22X1TS U6753 ( .A0(n7539), .A1(n8255), .B0(n7453), .B1(n457), .Y(n7543)
);
ADDHXLTS U6754 ( .A(n3302), .B(n3301), .CO(n7834), .S(n3294) );
ADDFHX2TS U6755 ( .A(n2341), .B(n2340), .CI(n2339), .CO(n2342), .S(n2219) );
NOR2XLTS U6756 ( .A(n9889), .B(n11426), .Y(n9806) );
AO21X1TS U6757 ( .A0(n10021), .A1(n10020), .B0(n10019), .Y(n10337) );
INVX2TS U6758 ( .A(n7231), .Y(n7122) );
ADDFHX2TS U6759 ( .A(n3156), .B(n3155), .CI(n3154), .CO(n3293), .S(n3210) );
ADDFHX2TS U6760 ( .A(n3665), .B(n3664), .CI(n3663), .CO(n3666), .S(n3644) );
NOR2XLTS U6761 ( .A(n6335), .B(n6334), .Y(n7982) );
OAI22X1TS U6762 ( .A0(n1989), .A1(n1849), .B0(n2148), .B1(n1837), .Y(n1854)
);
OR2X1TS U6763 ( .A(n5107), .B(n5106), .Y(n5109) );
NOR2XLTS U6764 ( .A(n10033), .B(n11526), .Y(n9721) );
INVX2TS U6765 ( .A(n10158), .Y(n9905) );
OR2X1TS U6766 ( .A(n6336), .B(n6333), .Y(n8115) );
NOR2XLTS U6767 ( .A(n9674), .B(n9683), .Y(n9686) );
NOR2XLTS U6768 ( .A(n9982), .B(n11495), .Y(n10857) );
OR2X1TS U6769 ( .A(n10275), .B(n10139), .Y(n10141) );
NOR2XLTS U6770 ( .A(n9383), .B(n9392), .Y(n9395) );
NOR2XLTS U6771 ( .A(n8818), .B(n9036), .Y(n8794) );
INVX2TS U6772 ( .A(n6744), .Y(n5979) );
OR2X1TS U6773 ( .A(n10821), .B(n11541), .Y(n10823) );
OR2X1TS U6774 ( .A(n9991), .B(n11534), .Y(n10833) );
INVX2TS U6775 ( .A(n9649), .Y(n9651) );
NAND2X1TS U6776 ( .A(n8682), .B(DP_OP_59J6_122_190_n192), .Y(
DP_OP_59J6_122_190_n60) );
AOI21X1TS U6777 ( .A0(n9658), .A1(n7803), .B0(n7802), .Y(n11560) );
INVX2TS U6778 ( .A(rst), .Y(n11785) );
NAND2X2TS U6779 ( .A(Data_A_i[6]), .B(Data_A_i[33]), .Y(n2844) );
INVX2TS U6780 ( .A(n234), .Y(n2671) );
NOR2X4TS U6781 ( .A(Data_B_i[33]), .B(Data_B_i[6]), .Y(n2898) );
OR2X2TS U6782 ( .A(n3379), .B(n218), .Y(n1737) );
NAND2X2TS U6783 ( .A(n331), .B(n521), .Y(n3365) );
OA21XLTS U6784 ( .A0(n3344), .A1(n3381), .B0(n3345), .Y(n1735) );
NOR2BX1TS U6785 ( .AN(n626), .B(n360), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[0]) );
NOR2BX1TS U6786 ( .AN(n1887), .B(n541), .Y(EVEN1_Q_left[0]) );
NOR2BX1TS U6787 ( .AN(Data_A_i[27]), .B(n623), .Y(n1788) );
XNOR2X1TS U6788 ( .A(Data_A_i[40]), .B(Data_B_i[28]), .Y(n1759) );
INVX2TS U6789 ( .A(n511), .Y(n1814) );
XNOR2X1TS U6790 ( .A(n515), .B(Data_A_i[38]), .Y(n1748) );
XNOR2X1TS U6791 ( .A(n280), .B(n311), .Y(n1784) );
OAI22X1TS U6792 ( .A0(n544), .A1(n1748), .B0(n693), .B1(n1784), .Y(n1786) );
XNOR2X4TS U6793 ( .A(Data_B_i[32]), .B(Data_B_i[33]), .Y(n1740) );
NAND2X4TS U6794 ( .A(n1739), .B(n1740), .Y(n2384) );
XNOR2X1TS U6795 ( .A(n408), .B(n305), .Y(n1767) );
XNOR2X1TS U6796 ( .A(n337), .B(n306), .Y(n1757) );
OAI22X1TS U6797 ( .A0(n374), .A1(n1767), .B0(n562), .B1(n1757), .Y(n1747) );
XNOR2X1TS U6798 ( .A(n260), .B(n1887), .Y(n1741) );
XNOR2X1TS U6799 ( .A(Data_B_i[40]), .B(Data_A_i[28]), .Y(n1743) );
XNOR2X1TS U6800 ( .A(n519), .B(n300), .Y(n1753) );
XNOR2X1TS U6801 ( .A(n519), .B(n302), .Y(n1742) );
OAI22X1TS U6802 ( .A0(n143), .A1(n1742), .B0(n174), .B1(n1771), .Y(n1775) );
XNOR2X1TS U6803 ( .A(Data_B_i[40]), .B(Data_A_i[29]), .Y(n1783) );
XNOR2X1TS U6804 ( .A(n407), .B(Data_A_i[36]), .Y(n1749) );
XNOR2X1TS U6805 ( .A(n407), .B(Data_A_i[37]), .Y(n1772) );
OAI22X1TS U6806 ( .A0(n370), .A1(n1749), .B0(n596), .B1(n1772), .Y(n1773) );
XNOR2X1TS U6807 ( .A(n321), .B(n694), .Y(n1769) );
XNOR2X1TS U6808 ( .A(n269), .B(n304), .Y(n1758) );
OAI22X1TS U6809 ( .A0(n2576), .A1(n1769), .B0(n603), .B1(n1758), .Y(n1756)
);
XNOR2X1TS U6810 ( .A(n515), .B(n309), .Y(n1768) );
OAI22X1TS U6811 ( .A0(n1984), .A1(n1768), .B0(n1983), .B1(n1748), .Y(n1755)
);
XNOR2X1TS U6812 ( .A(Data_B_i[32]), .B(Data_A_i[35]), .Y(n1750) );
OAI22X1TS U6813 ( .A0(n370), .A1(n1750), .B0(n596), .B1(n1749), .Y(n1754) );
XNOR2X1TS U6814 ( .A(n407), .B(Data_A_i[34]), .Y(n1805) );
OAI22X1TS U6815 ( .A0(n1989), .A1(n1805), .B0(n2148), .B1(n1750), .Y(n1959)
);
OAI22X1TS U6816 ( .A0(n347), .A1(n1921), .B0(n1752), .B1(n1920), .Y(n1808)
);
NAND2BX1TS U6817 ( .AN(n531), .B(n519), .Y(n1751) );
NOR2BX1TS U6818 ( .AN(Data_A_i[27]), .B(n468), .Y(n1766) );
XNOR2X1TS U6819 ( .A(Data_A_i[39]), .B(n245), .Y(n1760) );
OAI22X1TS U6820 ( .A0(n347), .A1(n1752), .B0(n1760), .B1(n541), .Y(n1765) );
XNOR2X1TS U6821 ( .A(n519), .B(n299), .Y(n1799) );
OAI22X1TS U6822 ( .A0(n6764), .A1(n1799), .B0(n174), .B1(n1753), .Y(n1764)
);
XNOR2X1TS U6823 ( .A(n408), .B(Data_A_i[35]), .Y(n1785) );
OAI22X1TS U6824 ( .A0(n374), .A1(n1757), .B0(n562), .B1(n1785), .Y(n1778) );
XNOR2X1TS U6825 ( .A(n269), .B(Data_A_i[33]), .Y(n1782) );
OAI22X1TS U6826 ( .A0(n2576), .A1(n1758), .B0(n603), .B1(n1782), .Y(n1777)
);
OAI22X1TS U6827 ( .A0(n347), .A1(n1760), .B0(n1759), .B1(n1920), .Y(n1763)
);
ADDHX1TS U6828 ( .A(n1763), .B(n1762), .CO(n1776), .S(n1797) );
XNOR2X1TS U6829 ( .A(n408), .B(n304), .Y(n1798) );
OAI22X1TS U6830 ( .A0(n374), .A1(n1798), .B0(n562), .B1(n1767), .Y(n1804) );
XNOR2X1TS U6831 ( .A(n280), .B(n308), .Y(n1801) );
XNOR2X1TS U6832 ( .A(n269), .B(Data_A_i[30]), .Y(n1806) );
OAI22X1TS U6833 ( .A0(n2485), .A1(n1806), .B0(n603), .B1(n1769), .Y(n1802)
);
INVX2TS U6834 ( .A(Data_A_i[28]), .Y(n1770) );
INVX2TS U6835 ( .A(n2114), .Y(n1992) );
XNOR2X1TS U6836 ( .A(n516), .B(n310), .Y(n1817) );
OAI22X1TS U6837 ( .A0(n1989), .A1(n1772), .B0(n2148), .B1(n1817), .Y(n1812)
);
CMPR32X2TS U6838 ( .A(n1773), .B(n1774), .C(n1775), .CO(n1831), .S(n1789) );
XNOR2X1TS U6839 ( .A(n269), .B(Data_A_i[34]), .Y(n1823) );
XNOR2X1TS U6840 ( .A(Data_B_i[40]), .B(Data_A_i[30]), .Y(n1824) );
XNOR2X1TS U6841 ( .A(Data_B_i[30]), .B(Data_A_i[40]), .Y(n1826) );
OAI22X1TS U6842 ( .A0(n544), .A1(n1784), .B0(n693), .B1(n1826), .Y(n1829) );
XNOR2X1TS U6843 ( .A(n408), .B(n308), .Y(n1819) );
OAI22X1TS U6844 ( .A0(n374), .A1(n1785), .B0(n562), .B1(n1819), .Y(n1828) );
NOR2X2TS U6845 ( .A(n5659), .B(n5524), .Y(n2077) );
ADDFHX2TS U6846 ( .A(n1797), .B(n1796), .CI(n1795), .CO(n1779), .S(n1956) );
XNOR2X1TS U6847 ( .A(n337), .B(Data_A_i[31]), .Y(n1911) );
OAI22X1TS U6848 ( .A0(n2384), .A1(n1911), .B0(n561), .B1(n1798), .Y(n1943)
);
XNOR2X1TS U6849 ( .A(n519), .B(n1887), .Y(n1800) );
OAI22X1TS U6850 ( .A0(n6764), .A1(n1800), .B0(n174), .B1(n1799), .Y(n1942)
);
XNOR2X1TS U6851 ( .A(n280), .B(n307), .Y(n1913) );
OAI22X1TS U6852 ( .A0(n544), .A1(n1913), .B0(n693), .B1(n1801), .Y(n1941) );
ADDFHX1TS U6853 ( .A(n1804), .B(n1803), .CI(n1802), .CO(n1795), .S(n1964) );
XNOR2X1TS U6854 ( .A(Data_B_i[32]), .B(Data_A_i[33]), .Y(n1909) );
OAI22X1TS U6855 ( .A0(n1989), .A1(n1909), .B0(n596), .B1(n1805), .Y(n1931)
);
XNOR2X1TS U6856 ( .A(n269), .B(n300), .Y(n1924) );
OAI22X1TS U6857 ( .A0(n2576), .A1(n1924), .B0(n2575), .B1(n1806), .Y(n1930)
);
ADDHX1TS U6858 ( .A(n1808), .B(n1807), .CO(n1958), .S(n1929) );
ADDFHX2TS U6859 ( .A(n1811), .B(n1810), .CI(n1809), .CO(n1793), .S(n1954) );
NOR2X1TS U6860 ( .A(n5517), .B(n5660), .Y(n2075) );
XNOR2X1TS U6861 ( .A(n516), .B(Data_A_i[39]), .Y(n1988) );
OAI22X1TS U6862 ( .A0(n370), .A1(n1817), .B0(n596), .B1(n1988), .Y(n1979) );
XNOR2X1TS U6863 ( .A(n331), .B(Data_A_i[33]), .Y(n1980) );
XNOR2X1TS U6864 ( .A(n337), .B(Data_A_i[37]), .Y(n1977) );
OAI22X1TS U6865 ( .A0(n2384), .A1(n1819), .B0(n561), .B1(n1977), .Y(n1978)
);
XNOR2X1TS U6866 ( .A(n321), .B(Data_A_i[35]), .Y(n1990) );
OAI22X1TS U6867 ( .A0(n2485), .A1(n1823), .B0(n603), .B1(n1990), .Y(n1987)
);
XNOR2X1TS U6868 ( .A(Data_B_i[40]), .B(n694), .Y(n1981) );
OAI22X1TS U6869 ( .A0(n7737), .A1(n1824), .B0(n468), .B1(n1981), .Y(n1986)
);
INVX2TS U6870 ( .A(Data_A_i[29]), .Y(n1825) );
XNOR2X1TS U6871 ( .A(n408), .B(Data_A_i[29]), .Y(n1843) );
XNOR2X1TS U6872 ( .A(Data_B_i[34]), .B(Data_A_i[30]), .Y(n1912) );
OAI22X1TS U6873 ( .A0(n2384), .A1(n1843), .B0(n561), .B1(n1912), .Y(n1928)
);
XNOR2X1TS U6874 ( .A(n321), .B(n531), .Y(n1836) );
XNOR2X1TS U6875 ( .A(n321), .B(n299), .Y(n1925) );
XNOR2X1TS U6876 ( .A(n407), .B(n694), .Y(n1837) );
XNOR2X1TS U6877 ( .A(n407), .B(n304), .Y(n1910) );
OAI22X1TS U6878 ( .A0(n1989), .A1(n1837), .B0(n2148), .B1(n1910), .Y(n1926)
);
XNOR2X1TS U6879 ( .A(Data_B_i[30]), .B(n304), .Y(n1844) );
XNOR2X1TS U6880 ( .A(n515), .B(n305), .Y(n1840) );
OAI22X1TS U6881 ( .A0(n1984), .A1(n1844), .B0(n1983), .B1(n1840), .Y(n1855)
);
XNOR2X1TS U6882 ( .A(n516), .B(n302), .Y(n1849) );
XNOR2X1TS U6883 ( .A(Data_B_i[28]), .B(Data_A_i[34]), .Y(n1842) );
OAI22X1TS U6884 ( .A0(n1923), .A1(n1861), .B0(n1842), .B1(n541), .Y(n1860)
);
OAI22X1TS U6885 ( .A0(n2384), .A1(n517), .B0(n561), .B1(n1838), .Y(n1859) );
OAI22X1TS U6886 ( .A0(n1923), .A1(n1841), .B0(n1922), .B1(n1920), .Y(n1919)
);
XNOR2X1TS U6887 ( .A(n515), .B(Data_A_i[34]), .Y(n1914) );
OAI22X1TS U6888 ( .A0(n1984), .A1(n1840), .B0(n1983), .B1(n1914), .Y(n1916)
);
NOR2BX1TS U6889 ( .AN(n531), .B(n2575), .Y(n1852) );
OAI22X1TS U6890 ( .A0(n1923), .A1(n1842), .B0(n1841), .B1(n541), .Y(n1851)
);
XNOR2X1TS U6891 ( .A(Data_B_i[34]), .B(Data_A_i[28]), .Y(n1847) );
OAI22X1TS U6892 ( .A0(n374), .A1(n1847), .B0(n562), .B1(n1843), .Y(n1850) );
XNOR2X1TS U6893 ( .A(n515), .B(n694), .Y(n1869) );
INVX1TS U6894 ( .A(n1844), .Y(n1845) );
OAI2BB2X2TS U6895 ( .B0(n544), .B1(n1869), .A0N(n1846), .A1N(n1845), .Y(
n1865) );
XNOR2X1TS U6896 ( .A(n408), .B(Data_A_i[27]), .Y(n1848) );
XNOR2X1TS U6897 ( .A(n516), .B(n300), .Y(n1862) );
OAI22X1TS U6898 ( .A0(n370), .A1(n1862), .B0(n2148), .B1(n1849), .Y(n1863)
);
NOR2BX1TS U6899 ( .AN(n1887), .B(n561), .Y(n1874) );
XNOR2X1TS U6900 ( .A(Data_B_i[28]), .B(Data_A_i[32]), .Y(n1870) );
OAI22X1TS U6901 ( .A0(n1923), .A1(n1870), .B0(n1861), .B1(n541), .Y(n1873)
);
XNOR2X1TS U6902 ( .A(n407), .B(n299), .Y(n1880) );
OAI22X1TS U6903 ( .A0(n1989), .A1(n1880), .B0(n2148), .B1(n1862), .Y(n1872)
);
ADDFHX2TS U6904 ( .A(n1864), .B(n1865), .CI(n1863), .CO(n1858), .S(n1866) );
XNOR2X1TS U6905 ( .A(n280), .B(n302), .Y(n1879) );
OAI22X1TS U6906 ( .A0(n544), .A1(n1879), .B0(n693), .B1(n1869), .Y(n1878) );
XNOR2X1TS U6907 ( .A(n245), .B(Data_A_i[31]), .Y(n1891) );
OAI22X1TS U6908 ( .A0(n347), .A1(n1891), .B0(n1870), .B1(n541), .Y(n1883) );
OAI22X1TS U6909 ( .A0(n1989), .A1(n406), .B0(n2148), .B1(n1871), .Y(n1882)
);
ADDFHX2TS U6910 ( .A(n1874), .B(n1873), .CI(n1872), .CO(n1867), .S(n1876) );
NOR2X1TS U6911 ( .A(n2294), .B(n2260), .Y(n1875) );
INVX2TS U6912 ( .A(n1875), .Y(n9110) );
XNOR2X1TS U6913 ( .A(n280), .B(n300), .Y(n1893) );
OAI22X1TS U6914 ( .A0(n544), .A1(n1893), .B0(n693), .B1(n1879), .Y(n1899) );
XNOR2X1TS U6915 ( .A(n516), .B(n531), .Y(n1881) );
OAI22X1TS U6916 ( .A0(n370), .A1(n1881), .B0(n2148), .B1(n1880), .Y(n1898)
);
NAND2X1TS U6917 ( .A(n9110), .B(n9114), .Y(n1906) );
XNOR2X1TS U6918 ( .A(n511), .B(n300), .Y(n1886) );
XNOR2X1TS U6919 ( .A(Data_A_i[30]), .B(n245), .Y(n1892) );
OAI22X1TS U6920 ( .A0(n347), .A1(n1886), .B0(n1892), .B1(n541), .Y(n1896) );
XNOR2X1TS U6921 ( .A(n280), .B(n1887), .Y(n1884) );
XNOR2X1TS U6922 ( .A(n280), .B(n299), .Y(n1894) );
OAI22X1TS U6923 ( .A0(n544), .A1(n1884), .B0(n693), .B1(n1894), .Y(n1895) );
OAI22X1TS U6924 ( .A0(n1984), .A1(n1982), .B0(n1885), .B1(n1983), .Y(n2038)
);
OAI22X1TS U6925 ( .A0(n347), .A1(n1889), .B0(n1886), .B1(n1920), .Y(n2014)
);
NOR2BX1TS U6926 ( .AN(n1887), .B(n1983), .Y(n2006) );
NOR2X1TS U6927 ( .A(n2014), .B(n2006), .Y(n4547) );
NAND2BX1TS U6928 ( .AN(n531), .B(n511), .Y(n1888) );
NAND2X1TS U6929 ( .A(n1888), .B(n347), .Y(n4545) );
NAND2X1TS U6930 ( .A(n4545), .B(n4544), .Y(n4550) );
NAND2X1TS U6931 ( .A(n2014), .B(n2006), .Y(n4548) );
OAI21X1TS U6932 ( .A0(n4547), .A1(n4550), .B0(n4548), .Y(n7974) );
NAND2X1TS U6933 ( .A(n2013), .B(n2038), .Y(n7973) );
AOI21X1TS U6934 ( .A0(n212), .A1(n7974), .B0(n1890), .Y(n8653) );
NOR2BX1TS U6935 ( .AN(Data_A_i[27]), .B(n596), .Y(n1902) );
OAI22X1TS U6936 ( .A0(n544), .A1(n1894), .B0(n1983), .B1(n1893), .Y(n1900)
);
ADDHX1TS U6937 ( .A(n1896), .B(n1895), .CO(n2160), .S(n2013) );
NOR2X1TS U6938 ( .A(n2169), .B(n2160), .Y(n8650) );
NAND2X1TS U6939 ( .A(n2169), .B(n2160), .Y(n8651) );
NAND2X1TS U6940 ( .A(n2198), .B(n2173), .Y(n9117) );
AOI21X1TS U6941 ( .A0(n9119), .A1(n9118), .B0(n1903), .Y(n9107) );
NAND2X1TS U6942 ( .A(n2277), .B(n2281), .Y(n9113) );
NAND2X1TS U6943 ( .A(n2294), .B(n2260), .Y(n9109) );
AOI21X1TS U6944 ( .A0(n9110), .A1(n9108), .B0(n1904), .Y(n1905) );
OAI21X1TS U6945 ( .A0(n1906), .A1(n9107), .B0(n1905), .Y(n9096) );
NAND2X1TS U6946 ( .A(n2423), .B(n2413), .Y(n9103) );
NAND2X1TS U6947 ( .A(n2525), .B(n2497), .Y(n9098) );
OAI22X1TS U6948 ( .A0(n370), .A1(n1910), .B0(n596), .B1(n1909), .Y(n1940) );
OAI22X1TS U6949 ( .A0(n544), .A1(n1914), .B0(n693), .B1(n1913), .Y(n1938) );
ADDHX1TS U6950 ( .A(n1919), .B(n1918), .CO(n1934), .S(n1917) );
NOR2BX1TS U6951 ( .AN(n531), .B(n174), .Y(n1937) );
OAI22X1TS U6952 ( .A0(n2576), .A1(n1925), .B0(n603), .B1(n1924), .Y(n1935)
);
ADDFHX2TS U6953 ( .A(n1934), .B(n1933), .CI(n1932), .CO(n1970), .S(n1945) );
INVX2TS U6954 ( .A(n1944), .Y(n9089) );
OR2X2TS U6955 ( .A(n5757), .B(n5738), .Y(n9093) );
NAND2X1TS U6956 ( .A(n9089), .B(n9093), .Y(n1953) );
NAND2X1TS U6957 ( .A(n5757), .B(n5738), .Y(n9092) );
INVX2TS U6958 ( .A(n9092), .Y(n9087) );
NAND2X1TS U6959 ( .A(n5681), .B(n5683), .Y(n9088) );
INVX1TS U6960 ( .A(n9088), .Y(n1951) );
AOI21X1TS U6961 ( .A0(n9089), .A1(n9087), .B0(n1951), .Y(n1952) );
NOR2X1TS U6962 ( .A(n5629), .B(n5561), .Y(n9081) );
NAND2X1TS U6963 ( .A(n5629), .B(n5561), .Y(n9082) );
NAND2X1TS U6964 ( .A(n5636), .B(n5602), .Y(n9077) );
NAND2X1TS U6965 ( .A(n5524), .B(n5659), .Y(n2078) );
NAND2X1TS U6966 ( .A(n5315), .B(n5286), .Y(n2105) );
OAI21X1TS U6967 ( .A0(n1974), .A1(n2102), .B0(n2105), .Y(n1975) );
XNOR2X1TS U6968 ( .A(n337), .B(Data_A_i[38]), .Y(n2116) );
OAI22X1TS U6969 ( .A0(n374), .A1(n1977), .B0(n562), .B1(n2116), .Y(n2112) );
XNOR2X1TS U6970 ( .A(n519), .B(n306), .Y(n2122) );
OAI22X1TS U6971 ( .A0(n6764), .A1(n1980), .B0(n174), .B1(n2122), .Y(n2120)
);
XNOR2X1TS U6972 ( .A(Data_B_i[40]), .B(n304), .Y(n2121) );
OAI22X1TS U6973 ( .A0(n7737), .A1(n1981), .B0(n468), .B1(n2121), .Y(n2119)
);
XNOR2X1TS U6974 ( .A(n516), .B(Data_A_i[40]), .Y(n2117) );
OAI22X1TS U6975 ( .A0(n370), .A1(n1988), .B0(n596), .B1(n2117), .Y(n2126) );
XNOR2X1TS U6976 ( .A(n269), .B(n308), .Y(n2123) );
NAND2X1TS U6977 ( .A(n2003), .B(n2104), .Y(n2004) );
INVX2TS U6978 ( .A(n1096), .Y(n5497) );
NOR2BX1TS U6979 ( .AN(n5497), .B(n5585), .Y(n5982) );
XNOR2X1TS U6980 ( .A(n2035), .B(n2034), .Y(n2057) );
NAND2X1TS U6981 ( .A(n2007), .B(n5571), .Y(n8016) );
XNOR2X1TS U6982 ( .A(n2015), .B(n2010), .Y(n2012) );
NAND2X1TS U6983 ( .A(n2030), .B(n224), .Y(n2011) );
NOR2BX1TS U6984 ( .AN(n629), .B(n503), .Y(n2055) );
INVX2TS U6985 ( .A(n2013), .Y(n2163) );
XNOR2X1TS U6986 ( .A(n476), .B(n685), .Y(n2046) );
XNOR2X1TS U6987 ( .A(n476), .B(Data_A_i[43]), .Y(n2036) );
OAI22X1TS U6988 ( .A0(n5571), .A1(n2046), .B0(n2036), .B1(n2031), .Y(n5983)
);
INVX2TS U6989 ( .A(n5585), .Y(n2659) );
NOR2X1TS U6990 ( .A(n2659), .B(n2015), .Y(n2016) );
OAI21X1TS U6991 ( .A0(Data_B_i[43]), .A1(Data_B_i[29]), .B0(n245), .Y(n2018)
);
NAND2X1TS U6992 ( .A(Data_B_i[43]), .B(Data_B_i[29]), .Y(n2017) );
NAND2BX1TS U6993 ( .AN(n629), .B(n429), .Y(n2019) );
OAI22X1TS U6994 ( .A0(n584), .A1(n427), .B0(n504), .B1(n2019), .Y(n2161) );
XNOR2X1TS U6995 ( .A(n428), .B(n628), .Y(n2021) );
OAI22X1TS U6996 ( .A0(n585), .A1(n2021), .B0(n2190), .B1(n503), .Y(n2211) );
OAI21X2TS U6997 ( .A0(n214), .A1(n2177), .B0(n2179), .Y(n2027) );
NAND2X1TS U6998 ( .A(n2025), .B(n2178), .Y(n2026) );
XNOR2X1TS U6999 ( .A(n5620), .B(n384), .Y(n2045) );
XOR2X1TS U7000 ( .A(n5568), .B(n2030), .Y(n2032) );
OAI22X1TS U7001 ( .A0(n2191), .A1(n445), .B0(n2045), .B1(n387), .Y(n2210) );
XNOR2X1TS U7002 ( .A(n476), .B(Data_A_i[44]), .Y(n2167) );
OAI22X1TS U7003 ( .A0(n5571), .A1(n2036), .B0(n2167), .B1(n2031), .Y(n2158)
);
XNOR2X1TS U7004 ( .A(n264), .B(Data_A_i[41]), .Y(n2037) );
XNOR2X1TS U7005 ( .A(n524), .B(n685), .Y(n2168) );
OAI22X1TS U7006 ( .A0(n5117), .A1(n2037), .B0(n323), .B1(n2168), .Y(n2157)
);
INVX2TS U7007 ( .A(n5985), .Y(n2188) );
XOR2X1TS U7008 ( .A(n2159), .B(n2041), .Y(n2187) );
XNOR2X1TS U7009 ( .A(n5530), .B(n384), .Y(n2061) );
OAI22X1TS U7010 ( .A0(n2045), .A1(n445), .B0(n2061), .B1(n387), .Y(n2053) );
OAI22X1TS U7011 ( .A0(n969), .A1(n332), .B0(n2046), .B1(n5568), .Y(n8015) );
NAND2X1TS U7012 ( .A(n2047), .B(n387), .Y(n2059) );
CMPR32X2TS U7013 ( .A(n8016), .B(n2049), .C(n2048), .CO(n2056), .S(n2058) );
NAND2X1TS U7014 ( .A(n2228), .B(n2226), .Y(n2067) );
CMPR32X2TS U7015 ( .A(n2054), .B(n2053), .C(n2052), .CO(n2050), .S(n2066) );
CMPR32X2TS U7016 ( .A(n2057), .B(n2056), .C(n2055), .CO(n2225), .S(n2065) );
CMPR32X2TS U7017 ( .A(n2060), .B(n2059), .C(n2058), .CO(n2052), .S(n2063) );
OAI22X1TS U7018 ( .A0(n2061), .A1(n444), .B0(n2033), .B1(n629), .Y(n2062) );
INVX2TS U7019 ( .A(EVEN1_Q_left[0]), .Y(n2093) );
NOR2BX1TS U7020 ( .AN(n628), .B(n445), .Y(n2091) );
NAND2X1TS U7021 ( .A(n2063), .B(n2062), .Y(n2083) );
NAND2X1TS U7022 ( .A(n2066), .B(n2065), .Y(n2072) );
XNOR2X1TS U7023 ( .A(n2067), .B(n2227), .Y(n2098) );
NAND2X1TS U7024 ( .A(n2068), .B(n2105), .Y(n2069) );
NAND2X1TS U7025 ( .A(n2073), .B(n2072), .Y(n2074) );
XOR2X1TS U7026 ( .A(n2074), .B(n181), .Y(n2096) );
NOR2X1TS U7027 ( .A(n8131), .B(n8136), .Y(n2101) );
NAND2X1TS U7028 ( .A(n2079), .B(n2078), .Y(n2080) );
NAND2X1TS U7029 ( .A(n2084), .B(n2083), .Y(n2086) );
XNOR2X1TS U7030 ( .A(n2086), .B(n2085), .Y(n2094) );
NOR2X1TS U7031 ( .A(n2095), .B(n2094), .Y(n9277) );
NAND2X1TS U7032 ( .A(n2088), .B(n2087), .Y(n2089) );
CMPR32X2TS U7033 ( .A(n2093), .B(n2092), .C(n2091), .CO(n2085), .S(n9121) );
NAND2X1TS U7034 ( .A(n2095), .B(n2094), .Y(n9278) );
OAI21X1TS U7035 ( .A0(n9277), .A1(n9280), .B0(n9278), .Y(n8130) );
NAND2X1TS U7036 ( .A(n2099), .B(n2098), .Y(n8132) );
OAI21X1TS U7037 ( .A0(n8131), .A1(n8137), .B0(n8132), .Y(n2100) );
AOI21X2TS U7038 ( .A0(n8130), .A1(n2101), .B0(n2100), .Y(n6688) );
CMPR32X2TS U7039 ( .A(n2114), .B(n2113), .C(n2112), .CO(n2139), .S(n2129) );
INVX2TS U7040 ( .A(n694), .Y(n2115) );
NOR2X1TS U7041 ( .A(n624), .B(n2115), .Y(n2359) );
OAI22X1TS U7042 ( .A0(n370), .A1(n2117), .B0(n596), .B1(n406), .Y(n2151) );
XNOR2X1TS U7043 ( .A(n7735), .B(n305), .Y(n2150) );
OAI22X1TS U7044 ( .A0(n7737), .A1(n2121), .B0(n468), .B1(n2150), .Y(n2145)
);
XNOR2X1TS U7045 ( .A(n519), .B(Data_A_i[35]), .Y(n2146) );
OAI22X1TS U7046 ( .A0(n6764), .A1(n2122), .B0(n174), .B1(n2146), .Y(n2144)
);
XNOR2X1TS U7047 ( .A(n321), .B(Data_A_i[37]), .Y(n2149) );
OAI22X1TS U7048 ( .A0(n2485), .A1(n2123), .B0(n602), .B1(n2149), .Y(n2143)
);
NOR2X1TS U7049 ( .A(n5182), .B(n5116), .Y(n2345) );
NAND2X1TS U7050 ( .A(n5116), .B(n5182), .Y(n2368) );
CMPR32X2TS U7051 ( .A(n2145), .B(n2144), .C(n2143), .CO(n2362), .S(n2142) );
XNOR2X1TS U7052 ( .A(n331), .B(n308), .Y(n2355) );
XNOR2X1TS U7053 ( .A(n337), .B(Data_A_i[40]), .Y(n2350) );
OAI22X1TS U7054 ( .A0(n374), .A1(n2147), .B0(n562), .B1(n2350), .Y(n2353) );
XNOR2X1TS U7055 ( .A(n321), .B(Data_A_i[38]), .Y(n2351) );
OAI22X1TS U7056 ( .A0(n2576), .A1(n2149), .B0(n2575), .B1(n2351), .Y(n2357)
);
XNOR2X1TS U7057 ( .A(n260), .B(n306), .Y(n2356) );
OAI22X1TS U7058 ( .A0(n770), .A1(n2150), .B0(n468), .B1(n2356), .Y(n2347) );
NAND2X1TS U7059 ( .A(n5250), .B(n5340), .Y(n2367) );
NAND2X1TS U7060 ( .A(n2154), .B(n2367), .Y(n2155) );
ADDHX1TS U7061 ( .A(n2158), .B(n2157), .CO(n5987), .S(n5985) );
NOR2X1TS U7062 ( .A(Data_B_i[30]), .B(Data_B_i[44]), .Y(n2164) );
NOR2BX1TS U7063 ( .AN(n628), .B(n498), .Y(n2176) );
XNOR2X4TS U7064 ( .A(Data_B_i[44]), .B(Data_B_i[45]), .Y(n2200) );
NOR2BX1TS U7065 ( .AN(n5497), .B(n555), .Y(n2172) );
XNOR2X1TS U7066 ( .A(n476), .B(Data_A_i[45]), .Y(n2203) );
XNOR2X1TS U7067 ( .A(n524), .B(Data_A_i[43]), .Y(n2199) );
OAI22X1TS U7068 ( .A0(n538), .A1(n2168), .B0(n323), .B1(n2199), .Y(n2170) );
INVX2TS U7069 ( .A(n2169), .Y(n2174) );
INVX2TS U7070 ( .A(n5989), .Y(n2301) );
INVX2TS U7071 ( .A(n2173), .Y(n2300) );
ADDFHX2TS U7072 ( .A(n2176), .B(n2175), .CI(n2174), .CO(n2316), .S(n2215) );
INVX2TS U7073 ( .A(n2245), .Y(n2185) );
CLKINVX1TS U7074 ( .A(n2248), .Y(n2182) );
NAND2X1TS U7075 ( .A(n2182), .B(n2246), .Y(n2183) );
XNOR2X1TS U7076 ( .A(n5637), .B(n385), .Y(n2308) );
NAND2X1TS U7077 ( .A(n2185), .B(n2247), .Y(n2186) );
XNOR2X1TS U7078 ( .A(n5627), .B(n385), .Y(n2192) );
OAI22X1TS U7079 ( .A0(n2308), .A1(n444), .B0(n2192), .B1(n387), .Y(n2315) );
OAI22X1TS U7080 ( .A0(n2192), .A1(n444), .B0(n2191), .B1(n2033), .Y(n2212)
);
XOR2X1TS U7081 ( .A(n2194), .B(n2263), .Y(n2195) );
OAI21X1TS U7082 ( .A0(Data_B_i[45]), .A1(Data_B_i[31]), .B0(Data_B_i[30]),
.Y(n2196) );
INVX2TS U7083 ( .A(n415), .Y(n5382) );
NAND2BX1TS U7084 ( .AN(n629), .B(n415), .Y(n2197) );
OAI22X1TS U7085 ( .A0(n583), .A1(n5382), .B0(n499), .B1(n2197), .Y(n2306) );
INVX2TS U7086 ( .A(n2198), .Y(n2304) );
XNOR2X1TS U7087 ( .A(n524), .B(n646), .Y(n2272) );
XNOR2X1TS U7088 ( .A(n247), .B(Data_A_i[41]), .Y(n2202) );
XNOR2X1TS U7089 ( .A(n255), .B(Data_A_i[42]), .Y(n2276) );
OAI22X1TS U7090 ( .A0(n5571), .A1(n2203), .B0(n2275), .B1(n2031), .Y(n2274)
);
INVX2TS U7091 ( .A(n5990), .Y(n2311) );
XNOR2X1TS U7092 ( .A(n5532), .B(n428), .Y(n2302) );
CMPR32X2TS U7093 ( .A(n2208), .B(n2207), .C(n2206), .CO(n2309), .S(n2217) );
OR2X4TS U7094 ( .A(n2219), .B(n2218), .Y(n2334) );
NAND2X1TS U7095 ( .A(n2334), .B(n2332), .Y(n2231) );
XNOR2X1TS U7096 ( .A(n2231), .B(n2335), .Y(n2242) );
NAND2X1TS U7097 ( .A(n2233), .B(n2368), .Y(n2234) );
XNOR2X1TS U7098 ( .A(n8060), .B(n2234), .Y(n2241) );
NAND2X1TS U7099 ( .A(n2237), .B(n2236), .Y(n2239) );
OAI21X4TS U7100 ( .A0(n2248), .A1(n2247), .B0(n2246), .Y(n2444) );
XNOR2X1TS U7101 ( .A(n5688), .B(n385), .Y(n2307) );
INVX2TS U7102 ( .A(n2444), .Y(n2253) );
OAI21X1TS U7103 ( .A0(n2253), .A1(n2438), .B0(n2441), .Y(n2254) );
NAND2X1TS U7104 ( .A(n2257), .B(n2440), .Y(n2258) );
XNOR2X1TS U7105 ( .A(n5640), .B(n384), .Y(n2447) );
OAI22X1TS U7106 ( .A0(n2307), .A1(n2033), .B0(n2447), .B1(n444), .Y(n2457)
);
XNOR2X1TS U7107 ( .A(n5532), .B(n414), .Y(n2454) );
INVX2TS U7108 ( .A(n2260), .Y(n2426) );
XOR2X4TS U7109 ( .A(n2265), .B(n2264), .Y(n5686) );
INVX2TS U7110 ( .A(n5581), .Y(n2941) );
XNOR2X1TS U7111 ( .A(n524), .B(Data_A_i[45]), .Y(n2287) );
OAI22X1TS U7112 ( .A0(n538), .A1(n2272), .B0(n323), .B1(n2287), .Y(n2284) );
ADDHX1TS U7113 ( .A(n2274), .B(n2273), .CO(n2283), .S(n2278) );
XNOR2X1TS U7114 ( .A(Data_B_i[46]), .B(Data_A_i[43]), .Y(n2285) );
OAI22X1TS U7115 ( .A0(n5579), .A1(n2276), .B0(n555), .B1(n2285), .Y(n2288)
);
NOR2BX1TS U7116 ( .AN(n628), .B(n5686), .Y(n2297) );
INVX2TS U7117 ( .A(n2281), .Y(n2295) );
XNOR2X1TS U7118 ( .A(n255), .B(n646), .Y(n2435) );
OAI22X1TS U7119 ( .A0(n351), .A1(n2285), .B0(n2200), .B1(n2435), .Y(n2430)
);
XNOR2X1TS U7120 ( .A(n5223), .B(Data_A_i[41]), .Y(n2286) );
XNOR2X1TS U7121 ( .A(Data_B_i[48]), .B(n685), .Y(n2429) );
OAI22X1TS U7122 ( .A0(n5583), .A1(n2286), .B0(n5581), .B1(n2429), .Y(n2433)
);
XNOR2X1TS U7123 ( .A(Data_B_i[44]), .B(Data_A_i[46]), .Y(n2434) );
XNOR2X1TS U7124 ( .A(n476), .B(Data_A_i[48]), .Y(n2428) );
OAI22X1TS U7125 ( .A0(n332), .A1(n2291), .B0(n2428), .B1(n5568), .Y(n2437)
);
INVX2TS U7126 ( .A(n281), .Y(n5378) );
OAI22X1TS U7127 ( .A0(n5583), .A1(n5378), .B0(n1367), .B1(n2292), .Y(n2436)
);
XNOR2X1TS U7128 ( .A(n5637), .B(n429), .Y(n2424) );
XNOR2X1TS U7129 ( .A(n5627), .B(n429), .Y(n2303) );
OAI22X1TS U7130 ( .A0(n2424), .A1(n503), .B0(n2303), .B1(n584), .Y(n2415) );
OAI22X1TS U7131 ( .A0(n2303), .A1(n504), .B0(n2302), .B1(n585), .Y(n2312) );
OAI22X1TS U7132 ( .A0(n2308), .A1(n387), .B0(n2307), .B1(n444), .Y(n2324) );
INVX2TS U7133 ( .A(n2332), .Y(n2333) );
NOR2X2TS U7134 ( .A(n2343), .B(n2342), .Y(n2397) );
XOR2X4TS U7135 ( .A(n2344), .B(n2407), .Y(n2404) );
NOR2X1TS U7136 ( .A(n2345), .B(n2369), .Y(n2467) );
CMPR32X2TS U7137 ( .A(n2346), .B(n2347), .C(n2348), .CO(n2390), .S(n2360) );
INVX2TS U7138 ( .A(Data_A_i[33]), .Y(n2349) );
INVX2TS U7139 ( .A(n2482), .Y(n2380) );
XNOR2X1TS U7140 ( .A(n321), .B(Data_A_i[39]), .Y(n2377) );
OAI22X1TS U7141 ( .A0(n2485), .A1(n2351), .B0(n602), .B1(n2377), .Y(n2378)
);
XNOR2X1TS U7142 ( .A(Data_B_i[38]), .B(Data_A_i[37]), .Y(n2382) );
OAI22X1TS U7143 ( .A0(n143), .A1(n2355), .B0(n275), .B1(n2382), .Y(n2375) );
XNOR2X1TS U7144 ( .A(n260), .B(n307), .Y(n2381) );
OAI22X1TS U7145 ( .A0(n770), .A1(n2356), .B0(n7736), .B1(n2381), .Y(n2374)
);
NOR2X1TS U7146 ( .A(n5388), .B(n5360), .Y(n2466) );
NOR2X1TS U7147 ( .A(n2366), .B(n2466), .Y(n2372) );
NAND2X1TS U7148 ( .A(n5360), .B(n5388), .Y(n2470) );
OAI21X1TS U7149 ( .A0(n2370), .A1(n2466), .B0(n2470), .Y(n2371) );
AOI21X1TS U7150 ( .A0(n8060), .A1(n2372), .B0(n2371), .Y(n2393) );
INVX2TS U7151 ( .A(Data_A_i[34]), .Y(n2376) );
XNOR2X1TS U7152 ( .A(n321), .B(Data_A_i[40]), .Y(n2484) );
XNOR2X1TS U7153 ( .A(n7735), .B(n308), .Y(n2479) );
OAI22X1TS U7154 ( .A0(n770), .A1(n2381), .B0(n7736), .B1(n2479), .Y(n2488)
);
XNOR2X1TS U7155 ( .A(Data_B_i[38]), .B(Data_A_i[38]), .Y(n2486) );
NOR2X1TS U7156 ( .A(n5412), .B(n5426), .Y(n2469) );
NAND2X1TS U7157 ( .A(n5426), .B(n5412), .Y(n2468) );
NAND2X1TS U7158 ( .A(n2391), .B(n2468), .Y(n2392) );
NOR2X2TS U7159 ( .A(n2404), .B(n2403), .Y(n7255) );
AOI21X1TS U7160 ( .A0(n8060), .A1(n2467), .B0(n2473), .Y(n2396) );
NAND2X1TS U7161 ( .A(n2394), .B(n2470), .Y(n2395) );
NOR2X1TS U7162 ( .A(n7255), .B(n7259), .Y(n2406) );
NAND2X1TS U7163 ( .A(n2404), .B(n2403), .Y(n7256) );
ADDFHX2TS U7164 ( .A(n2422), .B(n2421), .CI(n2420), .CO(n2550), .S(n2459) );
INVX2TS U7165 ( .A(n2423), .Y(n2507) );
NOR2BX1TS U7166 ( .AN(n5497), .B(n5573), .Y(n2524) );
OAI22X2TS U7167 ( .A0(n332), .A1(n2428), .B0(n2520), .B1(n2031), .Y(n2523)
);
XNOR2X1TS U7168 ( .A(n5223), .B(n312), .Y(n2512) );
OAI22X1TS U7169 ( .A0(n5583), .A1(n2429), .B0(n1367), .B1(n2512), .Y(n2522)
);
OAI21XLTS U7170 ( .A0(n2432), .A1(n2433), .B0(n2430), .Y(n2431) );
OAI2BB1X1TS U7171 ( .A0N(n2433), .A1N(n2432), .B0(n2431), .Y(n2544) );
XNOR2X1TS U7172 ( .A(n524), .B(Data_A_i[47]), .Y(n2519) );
OAI22X1TS U7173 ( .A0(n5117), .A1(n2434), .B0(n323), .B1(n2519), .Y(n2518)
);
XNOR2X1TS U7174 ( .A(n255), .B(Data_A_i[45]), .Y(n2515) );
ADDHX1TS U7175 ( .A(n2437), .B(n2436), .CO(n2516), .S(n2412) );
NOR2X2TS U7176 ( .A(n2438), .B(n2442), .Y(n2445) );
OAI21X1TS U7177 ( .A0(n2442), .A1(n2441), .B0(n2440), .Y(n2443) );
INVX2TS U7178 ( .A(n5154), .Y(n2527) );
NAND2X1TS U7179 ( .A(n2527), .B(n5156), .Y(n2446) );
XNOR2X1TS U7180 ( .A(n5703), .B(n384), .Y(n2531) );
OAI22X1TS U7181 ( .A0(n2447), .A1(n2033), .B0(n2531), .B1(n445), .Y(n2503)
);
NOR2BX1TS U7182 ( .AN(n629), .B(n484), .Y(n2500) );
XNOR2X1TS U7183 ( .A(n5620), .B(n446), .Y(n2535) );
XNOR2X1TS U7184 ( .A(n5627), .B(n415), .Y(n2511) );
OAI22X1TS U7185 ( .A0(n2511), .A1(n499), .B0(n2454), .B1(n583), .Y(n2498) );
NAND2X1TS U7186 ( .A(n2463), .B(n2556), .Y(n2464) );
NOR2X1TS U7187 ( .A(n2466), .B(n2469), .Y(n2472) );
INVX1TS U7188 ( .A(n8051), .Y(n2475) );
AOI21X1TS U7189 ( .A0(n8060), .A1(n2475), .B0(n2474), .Y(n2493) );
XNOR2X1TS U7190 ( .A(n260), .B(n309), .Y(n2574) );
OAI22X1TS U7191 ( .A0(n770), .A1(n2479), .B0(n7736), .B1(n2574), .Y(n2573)
);
INVX2TS U7192 ( .A(Data_A_i[35]), .Y(n2483) );
XNOR2X1TS U7193 ( .A(n519), .B(Data_A_i[39]), .Y(n2578) );
OAI22X1TS U7194 ( .A0(n143), .A1(n2486), .B0(n275), .B1(n2578), .Y(n2568) );
ADDFHX2TS U7195 ( .A(n2491), .B(n2490), .CI(n2489), .CO(n2565), .S(n2477) );
INVX2TS U7196 ( .A(n2562), .Y(n7193) );
NAND2X1TS U7197 ( .A(n5468), .B(n5470), .Y(n7194) );
NAND2X1TS U7198 ( .A(n7193), .B(n7194), .Y(n2492) );
XOR2X1TS U7199 ( .A(n2493), .B(n2492), .Y(n2494) );
OR2X4TS U7200 ( .A(n2494), .B(n2495), .Y(n9367) );
INVX2TS U7201 ( .A(n9367), .Y(n2496) );
AOI2BB1X2TS U7202 ( .A0N(n9365), .A1N(n2496), .B0(n7187), .Y(n2584) );
XNOR2X1TS U7203 ( .A(n5640), .B(n429), .Y(n5728) );
OAI22X1TS U7204 ( .A0(n2501), .A1(n585), .B0(n5728), .B1(n503), .Y(n5774) );
XNOR2X1TS U7205 ( .A(n5637), .B(n415), .Y(n5734) );
OAI22X1TS U7206 ( .A0(n5734), .A1(n498), .B0(n2511), .B1(n582), .Y(n5782) );
XNOR2X1TS U7207 ( .A(Data_B_i[48]), .B(n646), .Y(n5582) );
OAI22X1TS U7208 ( .A0(n5583), .A1(n2512), .B0(n1367), .B1(n5582), .Y(n5616)
);
XNOR2X1TS U7209 ( .A(Data_B_i[50]), .B(Data_A_i[41]), .Y(n2514) );
XNOR2X1TS U7210 ( .A(n5485), .B(n685), .Y(n5574) );
XNOR2X1TS U7211 ( .A(n255), .B(Data_A_i[46]), .Y(n5578) );
OAI22X1TS U7212 ( .A0(n351), .A1(n2515), .B0(n2200), .B1(n5578), .Y(n5614)
);
XNOR2X1TS U7213 ( .A(n264), .B(n344), .Y(n5586) );
OAI22X1TS U7214 ( .A0(n538), .A1(n2519), .B0(n323), .B1(n5586), .Y(n5695) );
XNOR2X1TS U7215 ( .A(n476), .B(Data_A_i[50]), .Y(n5570) );
OAI22X1TS U7216 ( .A0(n332), .A1(n2520), .B0(n5570), .B1(n5568), .Y(n5610)
);
OAI22X1TS U7217 ( .A0(n249), .A1(n5474), .B0(n601), .B1(n2521), .Y(n5609) );
INVX2TS U7218 ( .A(n2525), .Y(n5780) );
AOI21X1TS U7219 ( .A0(n5186), .A1(n2527), .B0(n2526), .Y(n2530) );
NAND2X1TS U7220 ( .A(n2528), .B(n5155), .Y(n2529) );
XNOR2X1TS U7221 ( .A(n5948), .B(n384), .Y(n5770) );
OAI22X1TS U7222 ( .A0(n5770), .A1(n445), .B0(n2531), .B1(n387), .Y(n5788) );
XNOR2X1TS U7223 ( .A(n5532), .B(n2269), .Y(n5628) );
OAI22X1TS U7224 ( .A0(n5628), .A1(n1316), .B0(n2535), .B1(n579), .Y(n5753)
);
NAND2X1TS U7225 ( .A(Data_B_i[49]), .B(Data_B_i[35]), .Y(n2539) );
INVX2TS U7226 ( .A(n447), .Y(n6730) );
OAI22X1TS U7227 ( .A0(n6732), .A1(n2542), .B0(n5625), .B1(n483), .Y(n5729)
);
INVX2TS U7228 ( .A(n6002), .Y(n5751) );
ADDFHX2TS U7229 ( .A(n2551), .B(n2550), .CI(n2549), .CO(n2552), .S(n2462) );
INVX2TS U7230 ( .A(n5812), .Y(n2554) );
AOI21X1TS U7231 ( .A0(n8060), .A1(n2564), .B0(n2563), .Y(n2580) );
ADDFHX1TS U7232 ( .A(n2570), .B(n2569), .CI(n2568), .CO(n6738), .S(n2571) );
XNOR2X1TS U7233 ( .A(n260), .B(n310), .Y(n6713) );
OAI22X1TS U7234 ( .A0(n770), .A1(n2574), .B0(n7736), .B1(n6713), .Y(n6716)
);
AO21X2TS U7235 ( .A0(n2576), .A1(n602), .B0(n268), .Y(n6715) );
INVX2TS U7236 ( .A(Data_A_i[36]), .Y(n2577) );
NOR2X1TS U7237 ( .A(n623), .B(n2577), .Y(n6709) );
NAND2X1TS U7238 ( .A(n5944), .B(n5950), .Y(n7195) );
NAND2X1TS U7239 ( .A(n189), .B(n7195), .Y(n2579) );
XOR2X1TS U7240 ( .A(n2580), .B(n2579), .Y(n2582) );
NAND2X1TS U7241 ( .A(n7188), .B(n7186), .Y(n2583) );
XOR2X1TS U7242 ( .A(n2584), .B(n2583), .Y(EVEN1_Q_left[23]) );
NAND2X1TS U7243 ( .A(n2591), .B(n2590), .Y(n2587) );
CLKINVX1TS U7244 ( .A(n2592), .Y(n2594) );
NAND2X1TS U7245 ( .A(n2594), .B(n2593), .Y(n2595) );
INVX2TS U7246 ( .A(n2601), .Y(n2740) );
INVX2TS U7247 ( .A(n2737), .Y(n2749) );
NAND2X1TS U7248 ( .A(n2740), .B(n2749), .Y(n2609) );
NAND2X1TS U7249 ( .A(n3437), .B(n2605), .Y(n2739) );
INVX1TS U7250 ( .A(n2739), .Y(n2606) );
INVX4TS U7251 ( .A(n2611), .Y(n2619) );
INVX2TS U7252 ( .A(n2618), .Y(n2612) );
NAND2X1TS U7253 ( .A(n2614), .B(n2763), .Y(n2712) );
INVX1TS U7254 ( .A(n2712), .Y(n2615) );
OAI21X4TS U7255 ( .A0(n2619), .A1(n2618), .B0(n2617), .Y(n2624) );
INVX2TS U7256 ( .A(n2620), .Y(n2622) );
XNOR2X4TS U7257 ( .A(n2624), .B(n2623), .Y(n2762) );
INVX2TS U7258 ( .A(n2625), .Y(n2792) );
INVX2TS U7259 ( .A(n2791), .Y(n2640) );
NAND2X1TS U7260 ( .A(n2629), .B(n2628), .Y(n2641) );
NAND2X1TS U7261 ( .A(n2637), .B(n128), .Y(n2631) );
INVX2TS U7262 ( .A(n2631), .Y(n3514) );
NAND2X1TS U7263 ( .A(n3511), .B(n2645), .Y(n2632) );
CLKINVX1TS U7264 ( .A(n2634), .Y(n2636) );
NAND2X1TS U7265 ( .A(n2636), .B(n2635), .Y(n2638) );
NAND2X1TS U7266 ( .A(n2642), .B(n2641), .Y(n2643) );
XOR2X1TS U7267 ( .A(n2733), .B(n2647), .Y(n2648) );
NOR2X2TS U7268 ( .A(Data_A_i[43]), .B(Data_A_i[16]), .Y(n2690) );
INVX2TS U7269 ( .A(n2690), .Y(n2663) );
NAND2X1TS U7270 ( .A(Data_B_i[43]), .B(Data_B_i[16]), .Y(n2651) );
XNOR2X1TS U7271 ( .A(n7467), .B(n2653), .Y(n2893) );
XNOR2X1TS U7272 ( .A(n2658), .B(n2656), .Y(n2657) );
NAND2X1TS U7273 ( .A(n2691), .B(n2663), .Y(n2665) );
AOI21X1TS U7274 ( .A0(n2696), .A1(n2663), .B0(n2662), .Y(n2664) );
NOR2X2TS U7275 ( .A(Data_A_i[44]), .B(Data_A_i[17]), .Y(n2694) );
NAND2X2TS U7276 ( .A(n646), .B(Data_A_i[17]), .Y(n2692) );
NAND2X1TS U7277 ( .A(n2666), .B(n2692), .Y(n2667) );
XNOR2X1TS U7278 ( .A(n8241), .B(n389), .Y(n2866) );
OAI22X1TS U7279 ( .A0(n2893), .A1(n545), .B0(n2866), .B1(n8243), .Y(n2790)
);
NAND2X1TS U7280 ( .A(n662), .B(Data_B_i[18]), .Y(n2677) );
NAND2X1TS U7281 ( .A(n2678), .B(n2677), .Y(n2868) );
XNOR2X1TS U7282 ( .A(n7447), .B(n362), .Y(n2863) );
XNOR2X1TS U7283 ( .A(n2684), .B(n2679), .Y(n2683) );
NAND2X1TS U7284 ( .A(n2681), .B(n2680), .Y(n2682) );
XNOR2X1TS U7285 ( .A(n626), .B(n362), .Y(n2688) );
OAI22X1TS U7286 ( .A0(n2863), .A1(n8233), .B0(n2688), .B1(n547), .Y(n2789)
);
OAI22X1TS U7287 ( .A0(n2689), .A1(n463), .B0(n546), .B1(n200), .Y(n2865) );
INVX2TS U7288 ( .A(n3099), .Y(n2951) );
INVX2TS U7289 ( .A(n2872), .Y(n2706) );
XOR2X1TS U7290 ( .A(n2703), .B(n2702), .Y(n2704) );
NAND2X1TS U7291 ( .A(n2947), .B(n2706), .Y(n2708) );
NAND2X1TS U7292 ( .A(n2709), .B(n2873), .Y(n2710) );
XNOR2X4TS U7293 ( .A(n2711), .B(n2710), .Y(n7436) );
XNOR2X1TS U7294 ( .A(n7436), .B(n139), .Y(n2880) );
NAND2X1TS U7295 ( .A(n2713), .B(n2712), .Y(n2714) );
CLKINVX1TS U7296 ( .A(n2717), .Y(n2719) );
NAND2X1TS U7297 ( .A(n2719), .B(n2718), .Y(n2720) );
NAND2X1TS U7298 ( .A(n2731), .B(n273), .Y(n2729) );
NAND2X1TS U7299 ( .A(n2730), .B(n2729), .Y(n2756) );
XNOR2X1TS U7300 ( .A(n7420), .B(n430), .Y(n2820) );
XNOR2X1TS U7301 ( .A(n2745), .B(n2732), .Y(n2736) );
NAND2X1TS U7302 ( .A(n2740), .B(n2739), .Y(n2741) );
NOR2X1TS U7303 ( .A(n2745), .B(n2744), .Y(n2746) );
XOR2X1TS U7304 ( .A(n2757), .B(n2746), .Y(n2747) );
OAI22X1TS U7305 ( .A0(n2820), .A1(n8308), .B0(n2983), .B1(n568), .Y(n2990)
);
NAND2X1TS U7306 ( .A(n2749), .B(n2748), .Y(n2750) );
INVX2TS U7307 ( .A(n2753), .Y(n2772) );
XNOR2X4TS U7308 ( .A(n2849), .B(n2754), .Y(n3609) );
XNOR2X1TS U7309 ( .A(n2785), .B(n2755), .Y(n2759) );
NAND2X1TS U7310 ( .A(n2757), .B(n2756), .Y(n2758) );
XOR2X1TS U7311 ( .A(n2759), .B(n2758), .Y(n2760) );
NOR2BX1TS U7312 ( .AN(n633), .B(n2760), .Y(n2989) );
XNOR2X1TS U7313 ( .A(n273), .B(n1063), .Y(n2766) );
XNOR2X1TS U7314 ( .A(n608), .B(n2813), .Y(n2768) );
OAI22X1TS U7315 ( .A0(n355), .A1(n2766), .B0(n2768), .B1(n391), .Y(n2960) );
XOR2X1TS U7316 ( .A(n2762), .B(n2763), .Y(n2764) );
XNOR2X1TS U7317 ( .A(n617), .B(n3511), .Y(n2765) );
XNOR2X1TS U7318 ( .A(n617), .B(n142), .Y(n2769) );
INVX2TS U7319 ( .A(n3531), .Y(n2825) );
XNOR2X1TS U7320 ( .A(n608), .B(n142), .Y(n3003) );
NOR2BX1TS U7321 ( .AN(n3514), .B(n3473), .Y(n2985) );
NAND2X1TS U7322 ( .A(n3527), .B(n2985), .Y(n3525) );
NAND2BX1TS U7323 ( .AN(n3514), .B(n618), .Y(n2767) );
OAI22X1TS U7324 ( .A0(n3474), .A1(n3439), .B0(n607), .B1(n2767), .Y(n3528)
);
OAI22X1TS U7325 ( .A0(n354), .A1(n2768), .B0(n2816), .B1(n391), .Y(n2812) );
NOR2BX1TS U7326 ( .AN(n3436), .B(n2817), .Y(n2811) );
XNOR2X1TS U7327 ( .A(n273), .B(n617), .Y(n2814) );
OAI22X1TS U7328 ( .A0(n3474), .A1(n2769), .B0(n2814), .B1(n607), .Y(n2810)
);
AOI21X1TS U7329 ( .A0(n2849), .A1(n2772), .B0(n2771), .Y(n2777) );
NAND2X1TS U7330 ( .A(n2775), .B(n2774), .Y(n2776) );
XOR2X1TS U7331 ( .A(n2777), .B(n2776), .Y(n2815) );
NAND2X1TS U7332 ( .A(n2779), .B(n2783), .Y(n2780) );
XNOR2X1TS U7333 ( .A(n8278), .B(n7591), .Y(n2890) );
XOR2X1TS U7334 ( .A(n2783), .B(n2782), .Y(n2784) );
XNOR2X1TS U7335 ( .A(n8278), .B(n7420), .Y(n2833) );
OAI22X1TS U7336 ( .A0(n2890), .A1(n564), .B0(n2833), .B1(n497), .Y(n2828) );
INVX2TS U7337 ( .A(n8782), .Y(n2827) );
XNOR2X1TS U7338 ( .A(n7507), .B(n430), .Y(n2832) );
XNOR2X4TS U7339 ( .A(n2794), .B(n2793), .Y(n7505) );
XNOR2X1TS U7340 ( .A(n7505), .B(n430), .Y(n2821) );
OAI22X1TS U7341 ( .A0(n2832), .A1(n485), .B0(n2821), .B1(n567), .Y(n2826) );
NAND2X1TS U7342 ( .A(n2795), .B(n2844), .Y(n2796) );
NAND2X1TS U7343 ( .A(n2800), .B(n2799), .Y(n2801) );
NAND2X1TS U7344 ( .A(n2803), .B(n2897), .Y(n2804) );
NAND2X1TS U7345 ( .A(n2807), .B(n2919), .Y(n2808) );
CMPR32X2TS U7346 ( .A(n2812), .B(n2811), .C(n2810), .CO(n2885), .S(n3532) );
XNOR2X1TS U7347 ( .A(n617), .B(n3471), .Y(n2837) );
OAI22X1TS U7348 ( .A0(n3474), .A1(n2814), .B0(n606), .B1(n2837), .Y(n2835)
);
XNOR2X1TS U7349 ( .A(n2815), .B(n608), .Y(n2838) );
OAI22X1TS U7350 ( .A0(n2838), .A1(n391), .B0(n354), .B1(n2816), .Y(n2834) );
XNOR2X1TS U7351 ( .A(n3467), .B(n3511), .Y(n2819) );
XNOR2X1TS U7352 ( .A(n616), .B(n265), .Y(n2836) );
OAI22X1TS U7353 ( .A0(n366), .A1(n1492), .B0(n2822), .B1(n570), .Y(n3534) );
INVX2TS U7354 ( .A(n3534), .Y(n2882) );
XNOR2X1TS U7355 ( .A(n7593), .B(n431), .Y(n3079) );
OAI22X1TS U7356 ( .A0(n3079), .A1(n8308), .B0(n2832), .B1(n568), .Y(n3129)
);
XNOR2X1TS U7357 ( .A(n8278), .B(n7505), .Y(n3068) );
OAI22X1TS U7358 ( .A0(n2833), .A1(n565), .B0(n3068), .B1(n497), .Y(n3072) );
XNOR2X1TS U7359 ( .A(n616), .B(n273), .Y(n2912) );
OAI22X1TS U7360 ( .A0(n366), .A1(n2836), .B0(n2912), .B1(n569), .Y(n2887) );
XNOR2X1TS U7361 ( .A(n3609), .B(n617), .Y(n2913) );
OAI22X1TS U7362 ( .A0(n3474), .A1(n2837), .B0(n2913), .B1(n606), .Y(n2910)
);
NOR2BX1TS U7363 ( .AN(n3514), .B(n3685), .Y(n2908) );
XOR2X1TS U7364 ( .A(n2855), .B(n3133), .Y(n2856) );
NAND2X1TS U7365 ( .A(n2859), .B(n2858), .Y(n2860) );
XNOR2X1TS U7366 ( .A(n443), .B(n633), .Y(n2862) );
OAI22X1TS U7367 ( .A0(n413), .A1(n2862), .B0(n615), .B1(n3137), .Y(n3127) );
XNOR2X1TS U7368 ( .A(n7467), .B(n361), .Y(n2932) );
OAI22X1TS U7369 ( .A0(n2863), .A1(n547), .B0(n2932), .B1(n463), .Y(n2917) );
XNOR2X1TS U7370 ( .A(n7472), .B(n389), .Y(n2936) );
XOR2X1TS U7371 ( .A(Data_B_i[47]), .B(Data_B_i[20]), .Y(n2940) );
XNOR2X1TS U7372 ( .A(n2940), .B(n2867), .Y(n2871) );
NOR2BX1TS U7373 ( .AN(n627), .B(n465), .Y(n2934) );
NAND2X1TS U7374 ( .A(n2947), .B(n3090), .Y(n2877) );
OAI21X1TS U7375 ( .A0(n2875), .A1(n2874), .B0(n2873), .Y(n3096) );
AOI21X1TS U7376 ( .A0(n2951), .A1(n3090), .B0(n3096), .Y(n2876) );
NAND2X1TS U7377 ( .A(n2878), .B(n3093), .Y(n2879) );
OAI22X1TS U7378 ( .A0(n2880), .A1(n352), .B0(n2956), .B1(n7558), .Y(n2933)
);
INVX2TS U7379 ( .A(n8783), .Y(n2974) );
CMPR22X2TS U7380 ( .A(n2882), .B(n2881), .CO(n2931), .S(n2966) );
INVX2TS U7381 ( .A(n3536), .Y(n2930) );
INVX2TS U7382 ( .A(n3537), .Y(n2929) );
OAI22X1TS U7383 ( .A0(n565), .A1(n432), .B0(n2889), .B1(n497), .Y(n2971) );
XNOR2X1TS U7384 ( .A(n8278), .B(n632), .Y(n2891) );
OAI22X1TS U7385 ( .A0(n2891), .A1(n564), .B0(n2890), .B1(n497), .Y(n2970) );
NOR2BX1TS U7386 ( .AN(n626), .B(n8233), .Y(n2965) );
XNOR2X1TS U7387 ( .A(n7447), .B(n389), .Y(n2982) );
OAI22X1TS U7388 ( .A0(n2982), .A1(n545), .B0(n2893), .B1(n271), .Y(n2963) );
INVX2TS U7389 ( .A(n8779), .Y(n2969) );
NOR2X1TS U7390 ( .A(n2895), .B(n2898), .Y(n2901) );
XNOR2X1TS U7391 ( .A(n3629), .B(n3511), .Y(n2911) );
XNOR2X1TS U7392 ( .A(n611), .B(n142), .Y(n3144) );
XNOR2X1TS U7393 ( .A(n3467), .B(n3471), .Y(n3145) );
OAI22X1TS U7394 ( .A0(n3634), .A1(n2912), .B0(n3145), .B1(n569), .Y(n3142)
);
OAI22X1TS U7395 ( .A0(n3138), .A1(n606), .B0(n379), .B1(n2913), .Y(n3147) );
XNOR2X1TS U7396 ( .A(n3675), .B(n608), .Y(n3139) );
OAI22X1TS U7397 ( .A0(n2914), .A1(n355), .B0(n3139), .B1(n390), .Y(n3146) );
INVX2TS U7398 ( .A(n3540), .Y(n3075) );
INVX2TS U7399 ( .A(n8784), .Y(n3074) );
NOR2X1TS U7400 ( .A(n2918), .B(n2921), .Y(n2923) );
XNOR2X1TS U7401 ( .A(n8317), .B(n375), .Y(n3126) );
OAI22X1TS U7402 ( .A0(n3126), .A1(n441), .B0(n2927), .B1(n377), .Y(n3073) );
INVX2TS U7403 ( .A(n443), .Y(n6986) );
OAI22X1TS U7404 ( .A0(n413), .A1(n6986), .B0(n615), .B1(n2928), .Y(n3078) );
ADDFHX2TS U7405 ( .A(n2931), .B(n2930), .CI(n2929), .CO(n3077), .S(n2973) );
XNOR2X1TS U7406 ( .A(n8241), .B(n361), .Y(n3109) );
OAI22X1TS U7407 ( .A0(n2932), .A1(n547), .B0(n3109), .B1(n8233), .Y(n3082)
);
OAI22X1TS U7408 ( .A0(n2936), .A1(n8244), .B0(n3088), .B1(n271), .Y(n3108)
);
NAND2X1TS U7409 ( .A(Data_B_i[47]), .B(Data_B_i[20]), .Y(n2937) );
NAND2X1TS U7410 ( .A(n2938), .B(n2937), .Y(n3084) );
XNOR2X1TS U7411 ( .A(n3085), .B(n3084), .Y(n2939) );
XNOR2X1TS U7412 ( .A(n7447), .B(n393), .Y(n3110) );
XNOR2X1TS U7413 ( .A(n627), .B(n393), .Y(n2944) );
OAI22X1TS U7414 ( .A0(n3110), .A1(n465), .B0(n2944), .B1(n551), .Y(n3107) );
OAI22X1TS U7415 ( .A0(n2945), .A1(n8237), .B0(n552), .B1(n392), .Y(n3112) );
NOR2X1TS U7416 ( .A(n2946), .B(n3089), .Y(n2950) );
AOI21X1TS U7417 ( .A0(n2951), .A1(n2950), .B0(n2949), .Y(n2952) );
NAND2X1TS U7418 ( .A(n2954), .B(n3092), .Y(n2955) );
INVX2TS U7419 ( .A(n8785), .Y(n3076) );
NAND2BX1TS U7420 ( .AN(n626), .B(n389), .Y(n2957) );
OAI22X1TS U7421 ( .A0(n545), .A1(n388), .B0(n271), .B1(n2957), .Y(n2995) );
XNOR2X1TS U7422 ( .A(n7467), .B(n134), .Y(n3006) );
OAI22X1TS U7423 ( .A0(n3006), .A1(n352), .B0(n2958), .B1(n7558), .Y(n2994)
);
INVX2TS U7424 ( .A(n8777), .Y(n3002) );
INVX2TS U7425 ( .A(n3529), .Y(n2999) );
INVX2TS U7426 ( .A(n430), .Y(n8307) );
NAND2BX1TS U7427 ( .AN(n632), .B(n430), .Y(n2962) );
INVX2TS U7428 ( .A(n8778), .Y(n3000) );
NOR2X2TS U7429 ( .A(n3064), .B(n3063), .Y(n7263) );
ADDFHX2TS U7430 ( .A(n2980), .B(n2979), .CI(n2978), .CO(n3063), .S(n3061) );
XNOR2X1TS U7431 ( .A(n626), .B(n2653), .Y(n2981) );
OAI22X1TS U7432 ( .A0(n2982), .A1(n8243), .B0(n8244), .B1(n2981), .Y(n8774)
);
XNOR2X1TS U7433 ( .A(n430), .B(n633), .Y(n2984) );
OAI22X1TS U7434 ( .A0(n2984), .A1(n566), .B0(n2983), .B1(n8308), .Y(n3009)
);
XNOR2X1TS U7435 ( .A(n2987), .B(n2986), .Y(n5094) );
INVX2TS U7436 ( .A(n8772), .Y(n3013) );
NOR2BX1TS U7437 ( .AN(n633), .B(n8308), .Y(n3012) );
ADDHX1TS U7438 ( .A(n2995), .B(n2994), .CO(n8777), .S(n8775) );
INVX2TS U7439 ( .A(n8775), .Y(n3034) );
XNOR2X1TS U7440 ( .A(n7420), .B(n376), .Y(n3011) );
OAI22X1TS U7441 ( .A0(n2996), .A1(n7828), .B0(n3011), .B1(n378), .Y(n3033)
);
CMPR32X2TS U7442 ( .A(n2999), .B(n2998), .C(n2997), .CO(n3001), .S(n3032) );
OAI22X1TS U7443 ( .A0(n354), .A1(n3511), .B0(n3003), .B1(n390), .Y(n5106) );
NAND2BX1TS U7444 ( .AN(n3514), .B(n608), .Y(n3004) );
NAND2X1TS U7445 ( .A(n3004), .B(n355), .Y(n5107) );
NAND2BX1TS U7446 ( .AN(n626), .B(n139), .Y(n3005) );
NAND2X1TS U7447 ( .A(n352), .B(n3005), .Y(n8895) );
XNOR2X1TS U7448 ( .A(n7447), .B(n134), .Y(n3007) );
OAI22X1TS U7449 ( .A0(n3007), .A1(n7558), .B0(n627), .B1(n7560), .Y(n8896)
);
OAI22X1TS U7450 ( .A0(n3007), .A1(n352), .B0(n3006), .B1(n7558), .Y(n8773)
);
ADDFHX1TS U7451 ( .A(n3010), .B(n3009), .CI(n3008), .CO(n3027), .S(n3030) );
OAI22X1TS U7452 ( .A0(n3011), .A1(n7828), .B0(n3015), .B1(n377), .Y(n3037)
);
CMPR32X2TS U7453 ( .A(n5094), .B(n3013), .C(n3012), .CO(n3008), .S(n3036) );
NAND2X1TS U7454 ( .A(n378), .B(n3014), .Y(n3042) );
OAI22X1TS U7455 ( .A0(n3015), .A1(n7828), .B0(n633), .B1(n377), .Y(n3041) );
NOR2X2TS U7456 ( .A(n3059), .B(n3058), .Y(n7699) );
CMPR32X2TS U7457 ( .A(n3027), .B(n3026), .C(n3025), .CO(n3018), .S(n3055) );
NOR2X2TS U7458 ( .A(n3056), .B(n3055), .Y(n3028) );
INVX2TS U7459 ( .A(n3028), .Y(n7710) );
NOR2X1TS U7460 ( .A(n3051), .B(n3050), .Y(n8156) );
NOR2BX1TS U7461 ( .AN(n3436), .B(n391), .Y(n7375) );
NOR2BX1TS U7462 ( .AN(n632), .B(n7828), .Y(n9267) );
NAND2X1TS U7463 ( .A(n3047), .B(n3046), .Y(n9282) );
AOI21X1TS U7464 ( .A0(n9283), .A1(n3049), .B0(n3048), .Y(n8159) );
NAND2X1TS U7465 ( .A(n3051), .B(n3050), .Y(n8157) );
OAI21X1TS U7466 ( .A0(n8156), .A1(n8159), .B0(n8157), .Y(n8143) );
NAND2X1TS U7467 ( .A(n3053), .B(n3052), .Y(n8141) );
NAND2X1TS U7468 ( .A(n3056), .B(n3055), .Y(n7709) );
NAND2X1TS U7469 ( .A(n3061), .B(n3060), .Y(n7268) );
OAI21X2TS U7470 ( .A0(n7263), .A1(n7264), .B0(n7262), .Y(n8913) );
XNOR2X1TS U7471 ( .A(n7507), .B(n8278), .Y(n3191) );
OAI22X1TS U7472 ( .A0(n3191), .A1(n497), .B0(n3068), .B1(n564), .Y(n3197) );
ADDHX1TS U7473 ( .A(n3071), .B(n3072), .CO(n3196), .S(n3128) );
XNOR2X1TS U7474 ( .A(n7423), .B(n431), .Y(n3243) );
OAI22X1TS U7475 ( .A0(n3243), .A1(n8308), .B0(n3079), .B1(n567), .Y(n3156)
);
XNOR2X1TS U7476 ( .A(n3225), .B(n3083), .Y(n3087) );
NAND2X1TS U7477 ( .A(n3085), .B(n3084), .Y(n3086) );
NOR2BX1TS U7478 ( .AN(n626), .B(n467), .Y(n3238) );
NOR2X1TS U7479 ( .A(n3089), .B(n3094), .Y(n3097) );
NOR2X2TS U7480 ( .A(n3091), .B(n3100), .Y(n3101) );
AOI21X1TS U7481 ( .A0(n3097), .A1(n3096), .B0(n3095), .Y(n3098) );
XNOR2X1TS U7482 ( .A(n134), .B(n7474), .Y(n3235) );
OAI22X1TS U7483 ( .A0(n3235), .A1(n360), .B0(n3105), .B1(n352), .Y(n3236) );
XNOR2X1TS U7484 ( .A(n7472), .B(n361), .Y(n3231) );
OAI22X1TS U7485 ( .A0(n3231), .A1(n8233), .B0(n3109), .B1(n547), .Y(n3221)
);
XNOR2X1TS U7486 ( .A(n7467), .B(n2939), .Y(n3222) );
OAI22X1TS U7487 ( .A0(n3110), .A1(n552), .B0(n3222), .B1(n465), .Y(n3220) );
INVX2TS U7488 ( .A(n8789), .Y(n3154) );
NAND2X1TS U7489 ( .A(n3118), .B(n3176), .Y(n3119) );
NAND2X1TS U7490 ( .A(n3122), .B(n3121), .Y(n3199) );
NAND2X1TS U7491 ( .A(n3123), .B(n3199), .Y(n3124) );
XNOR2X1TS U7492 ( .A(n8225), .B(n376), .Y(n3207) );
OAI22X1TS U7493 ( .A0(n3207), .A1(n441), .B0(n3126), .B1(n378), .Y(n3213) );
XOR2X1TS U7494 ( .A(n3169), .B(n3168), .Y(n3159) );
NOR2X1TS U7495 ( .A(n3167), .B(n3157), .Y(n3132) );
NOR2BX1TS U7496 ( .AN(n632), .B(n471), .Y(n3218) );
XNOR2X1TS U7497 ( .A(n3647), .B(n618), .Y(n3172) );
OAI22X1TS U7498 ( .A0(n3138), .A1(n379), .B0(n3172), .B1(n607), .Y(n3190) );
XNOR2X1TS U7499 ( .A(n3695), .B(n608), .Y(n3173) );
OAI22X1TS U7500 ( .A0(n3173), .A1(n390), .B0(n3139), .B1(n354), .Y(n3188) );
XNOR2X1TS U7501 ( .A(n611), .B(n273), .Y(n3187) );
OAI22X1TS U7502 ( .A0(n371), .A1(n3144), .B0(n572), .B1(n3187), .Y(n3185) );
XNOR2X1TS U7503 ( .A(n3467), .B(n3609), .Y(n3174) );
OAI22X1TS U7504 ( .A0(n366), .A1(n3145), .B0(n3174), .B1(n570), .Y(n3184) );
INVX2TS U7505 ( .A(n3542), .Y(n3217) );
ADDFHX2TS U7506 ( .A(n3150), .B(n3149), .CI(n3148), .CO(n3151), .S(n3064) );
INVX2TS U7507 ( .A(n8912), .Y(n3153) );
NAND2X1TS U7508 ( .A(n3169), .B(n3168), .Y(n3170) );
XNOR2X1TS U7509 ( .A(n440), .B(n2751), .Y(n3171) );
XNOR2X1TS U7510 ( .A(n440), .B(n7591), .Y(n3297) );
OAI22X1TS U7511 ( .A0(n559), .A1(n3171), .B0(n470), .B1(n3297), .Y(n3296) );
XNOR2X1TS U7512 ( .A(n3675), .B(n618), .Y(n3266) );
OAI22X1TS U7513 ( .A0(n3172), .A1(n379), .B0(n3266), .B1(n607), .Y(n3255) );
OAI22X1TS U7514 ( .A0(n3173), .A1(n355), .B0(n3265), .B1(n390), .Y(n3254) );
XNOR2X1TS U7515 ( .A(n616), .B(n3635), .Y(n3252) );
OAI22X1TS U7516 ( .A0(n3634), .A1(n3174), .B0(n3252), .B1(n569), .Y(n3268)
);
INVX2TS U7517 ( .A(n3177), .Y(n3179) );
NAND2X4TS U7518 ( .A(n3181), .B(n3715), .Y(n3694) );
XNOR2X1TS U7519 ( .A(n319), .B(n3511), .Y(n3182) );
XNOR2X1TS U7520 ( .A(n3677), .B(n142), .Y(n3253) );
OAI22X1TS U7521 ( .A0(n3694), .A1(n3182), .B0(n609), .B1(n3253), .Y(n3267)
);
NAND2BX1TS U7522 ( .AN(n3514), .B(n319), .Y(n3186) );
OAI22X1TS U7523 ( .A0(n274), .A1(n318), .B0(n609), .B1(n3186), .Y(n3258) );
XNOR2X1TS U7524 ( .A(n3629), .B(n3471), .Y(n3259) );
OAI22X1TS U7525 ( .A0(n372), .A1(n3187), .B0(n572), .B1(n3259), .Y(n3257) );
INVX2TS U7526 ( .A(n3544), .Y(n3295) );
XNOR2X1TS U7527 ( .A(n7593), .B(n8278), .Y(n3271) );
OAI22X1TS U7528 ( .A0(n3271), .A1(n496), .B0(n3191), .B1(n565), .Y(n3302) );
XNOR2X1TS U7529 ( .A(n442), .B(n7505), .Y(n3275) );
INVX2TS U7530 ( .A(n8791), .Y(n3251) );
NAND2X1TS U7531 ( .A(n1161), .B(n6857), .Y(n3205) );
XNOR2X1TS U7532 ( .A(n8311), .B(n375), .Y(n3287) );
OAI22X1TS U7533 ( .A0(n3207), .A1(n377), .B0(n3287), .B1(n441), .Y(n3249) );
ADDFHX2TS U7534 ( .A(n3210), .B(n3209), .CI(n3208), .CO(n3333), .S(n3244) );
XNOR2X1TS U7535 ( .A(n8241), .B(n393), .Y(n3303) );
OAI22X1TS U7536 ( .A0(n3222), .A1(n552), .B0(n3303), .B1(n8237), .Y(n3328)
);
XNOR2X1TS U7537 ( .A(n320), .B(n5203), .Y(n3321) );
NAND2X1TS U7538 ( .A(Data_B_i[49]), .B(Data_B_i[22]), .Y(n3223) );
NAND2X1TS U7539 ( .A(n3224), .B(n3223), .Y(n3320) );
XNOR2X1TS U7540 ( .A(n7447), .B(n395), .Y(n3304) );
XNOR2X1TS U7541 ( .A(n626), .B(n394), .Y(n3228) );
OAI22X1TS U7542 ( .A0(n3304), .A1(n466), .B0(n3228), .B1(n8259), .Y(n3327)
);
OAI22X1TS U7543 ( .A0(n3229), .A1(n466), .B0(n8259), .B1(n175), .Y(n3306) );
XNOR2X1TS U7544 ( .A(n7436), .B(n361), .Y(n3324) );
OAI22X1TS U7545 ( .A0(n3231), .A1(n547), .B0(n3324), .B1(n463), .Y(n3309) );
NAND2X1TS U7546 ( .A(n3232), .B(n3311), .Y(n3233) );
XNOR2X1TS U7547 ( .A(n753), .B(n139), .Y(n3318) );
INVX2TS U7548 ( .A(n8792), .Y(n3277) );
INVX2TS U7549 ( .A(n3543), .Y(n3290) );
INVX2TS U7550 ( .A(n440), .Y(n7092) );
XNOR2X1TS U7551 ( .A(n8317), .B(n431), .Y(n3270) );
OAI22X1TS U7552 ( .A0(n3270), .A1(n485), .B0(n3243), .B1(n568), .Y(n3288) );
INVX2TS U7553 ( .A(n7843), .Y(n8904) );
XNOR2X1TS U7554 ( .A(n616), .B(n3647), .Y(n3506) );
OAI22X1TS U7555 ( .A0(n3634), .A1(n3252), .B0(n3506), .B1(n569), .Y(n3554)
);
XNOR2X1TS U7556 ( .A(n319), .B(n273), .Y(n3508) );
ADDHX1TS U7557 ( .A(n3254), .B(n3255), .CO(n3553), .S(n3269) );
XNOR2X1TS U7558 ( .A(n611), .B(n3609), .Y(n3510) );
OAI22X1TS U7559 ( .A0(n371), .A1(n3259), .B0(n572), .B1(n3510), .Y(n3560) );
INVX2TS U7560 ( .A(n3263), .Y(n3371) );
XOR2X4TS U7561 ( .A(n3264), .B(n1691), .Y(n6963) );
XNOR2X1TS U7562 ( .A(n6963), .B(n608), .Y(n3444) );
XNOR2X1TS U7563 ( .A(n3695), .B(n618), .Y(n3446) );
OAI22X1TS U7564 ( .A0(n3446), .A1(n606), .B0(n3266), .B1(n379), .Y(n3550) );
INVX2TS U7565 ( .A(n3565), .Y(n7813) );
XNOR2X1TS U7566 ( .A(n8225), .B(n431), .Y(n7824) );
OAI22X1TS U7567 ( .A0(n7824), .A1(n485), .B0(n3270), .B1(n567), .Y(n7812) );
OAI22X1TS U7568 ( .A0(n412), .A1(n3275), .B0(n7651), .B1(n614), .Y(n7810) );
NAND2X1TS U7569 ( .A(n3285), .B(n3284), .Y(n6856) );
NAND2X1TS U7570 ( .A(n6853), .B(n6856), .Y(n3286) );
XNOR2X1TS U7571 ( .A(n8228), .B(n376), .Y(n7830) );
OAI22X1TS U7572 ( .A0(n7830), .A1(n441), .B0(n3287), .B1(n377), .Y(n7821) );
OAI22X1TS U7573 ( .A0(n559), .A1(n3297), .B0(n470), .B1(n7506), .Y(n7836) );
XNOR2X1TS U7574 ( .A(n7472), .B(n2939), .Y(n7536) );
OAI22X1TS U7575 ( .A0(n7536), .A1(n8237), .B0(n3303), .B1(n552), .Y(n7581)
);
OAI22X1TS U7576 ( .A0(n3304), .A1(n8259), .B0(n7546), .B1(n467), .Y(n7580)
);
NOR2X1TS U7577 ( .A(n3310), .B(n3313), .Y(n6908) );
INVX2TS U7578 ( .A(n6890), .Y(n6911) );
NAND2X1TS U7579 ( .A(n6911), .B(n6909), .Y(n3316) );
XNOR2X1TS U7580 ( .A(n7487), .B(n134), .Y(n7551) );
OAI22X1TS U7581 ( .A0(n3318), .A1(n352), .B0(n7551), .B1(n7558), .Y(n7659)
);
XNOR2X1TS U7582 ( .A(n6885), .B(n3319), .Y(n3323) );
NAND2X1TS U7583 ( .A(n3321), .B(n3320), .Y(n3322) );
NOR2BX1TS U7584 ( .AN(n627), .B(n457), .Y(n7578) );
OAI22X1TS U7585 ( .A0(n3324), .A1(n546), .B0(n7441), .B1(n463), .Y(n7577) );
XNOR2X1TS U7586 ( .A(n7474), .B(n2653), .Y(n7548) );
OAI22X1TS U7587 ( .A0(n7548), .A1(n271), .B0(n3325), .B1(n8244), .Y(n7576)
);
CMPR32X2TS U7588 ( .A(n3328), .B(n3327), .C(n3326), .CO(n7657), .S(n3280) );
INVX2TS U7589 ( .A(n8796), .Y(n7804) );
INVX2TS U7590 ( .A(n8903), .Y(n3337) );
INVX2TS U7591 ( .A(EVEN1_Q_left[23]), .Y(n8008) );
NAND2X1TS U7592 ( .A(n3346), .B(n3345), .Y(n3347) );
NOR2X1TS U7593 ( .A(n436), .B(n272), .Y(n3455) );
INVX2TS U7594 ( .A(n265), .Y(n3348) );
INVX2TS U7595 ( .A(n3349), .Y(n3389) );
NAND2X1TS U7596 ( .A(n3350), .B(n3389), .Y(n3354) );
AOI21X1TS U7597 ( .A0(n3352), .A1(n3389), .B0(n3351), .Y(n3353) );
XNOR2X1TS U7598 ( .A(n8423), .B(n617), .Y(n3411) );
OAI22X1TS U7599 ( .A0(n3411), .A1(n379), .B0(n607), .B1(n3439), .Y(n3453) );
NAND2X1TS U7600 ( .A(n3366), .B(n3365), .Y(n3367) );
XNOR2X1TS U7601 ( .A(n610), .B(n3609), .Y(n3416) );
XNOR2X1TS U7602 ( .A(n610), .B(n3635), .Y(n3405) );
XNOR2X1TS U7603 ( .A(n611), .B(n3695), .Y(n3423) );
XNOR2X1TS U7604 ( .A(n611), .B(n747), .Y(n3406) );
OAI22X1TS U7605 ( .A0(n371), .A1(n3423), .B0(n572), .B1(n3406), .Y(n3393) );
XNOR2X1TS U7606 ( .A(n3467), .B(n6963), .Y(n3414) );
NAND2X1TS U7607 ( .A(n3368), .B(n3371), .Y(n3374) );
AOI21X1TS U7608 ( .A0(n3372), .A1(n3371), .B0(n3370), .Y(n3373) );
XOR2X4TS U7609 ( .A(n3378), .B(n1690), .Y(n7106) );
XNOR2X1TS U7610 ( .A(n3467), .B(n790), .Y(n3407) );
OAI22X1TS U7611 ( .A0(n366), .A1(n3414), .B0(n3407), .B1(n570), .Y(n3392) );
XNOR2X1TS U7612 ( .A(n319), .B(n3647), .Y(n3420) );
XNOR2X1TS U7613 ( .A(n319), .B(n3675), .Y(n3408) );
OAI22X1TS U7614 ( .A0(n274), .A1(n3420), .B0(n3408), .B1(n3715), .Y(n3397)
);
NAND2X1TS U7615 ( .A(n3382), .B(n3381), .Y(n3383) );
XNOR2X1TS U7616 ( .A(n7108), .B(n3471), .Y(n3409) );
OAI22X1TS U7617 ( .A0(n8425), .A1(n3422), .B0(n3409), .B1(n417), .Y(n3396)
);
NOR2BX1TS U7618 ( .AN(n3436), .B(n436), .Y(n3403) );
INVX2TS U7619 ( .A(n3437), .Y(n3419) );
OAI22X1TS U7620 ( .A0(n3399), .A1(n354), .B0(n3419), .B1(n391), .Y(n3402) );
XNOR2X1TS U7621 ( .A(n7106), .B(n617), .Y(n3400) );
XNOR2X4TS U7622 ( .A(n3391), .B(n3390), .Y(n7145) );
OAI22X1TS U7623 ( .A0(n3400), .A1(n379), .B0(n3410), .B1(n606), .Y(n3401) );
XNOR2X1TS U7624 ( .A(n610), .B(n273), .Y(n3491) );
XNOR2X1TS U7625 ( .A(n610), .B(n3471), .Y(n3417) );
XNOR2X1TS U7626 ( .A(n616), .B(n3695), .Y(n3442) );
XNOR2X1TS U7627 ( .A(n6963), .B(n617), .Y(n3440) );
XNOR2X1TS U7628 ( .A(n319), .B(n3635), .Y(n3421) );
OAI22X1TS U7629 ( .A0(n274), .A1(n3441), .B0(n3421), .B1(n3715), .Y(n3486)
);
OAI22X1TS U7630 ( .A0(n8425), .A1(n501), .B0(n417), .B1(n3404), .Y(n3485) );
XNOR2X1TS U7631 ( .A(n3629), .B(n3647), .Y(n3490) );
XNOR2X1TS U7632 ( .A(n611), .B(n3675), .Y(n3424) );
OAI22X1TS U7633 ( .A0(n372), .A1(n3490), .B0(n3424), .B1(n572), .Y(n3484) );
XNOR2X1TS U7634 ( .A(n610), .B(n3647), .Y(n3465) );
XNOR2X1TS U7635 ( .A(n611), .B(n6963), .Y(n3466) );
XNOR2X1TS U7636 ( .A(n616), .B(n808), .Y(n3468) );
OAI22X1TS U7637 ( .A0(n366), .A1(n3407), .B0(n3468), .B1(n570), .Y(n3456) );
XNOR2X1TS U7638 ( .A(n3695), .B(n319), .Y(n3469) );
OAI22X1TS U7639 ( .A0(n3694), .A1(n3408), .B0(n3469), .B1(n609), .Y(n3461)
);
XNOR2X1TS U7640 ( .A(n7108), .B(n3609), .Y(n3470) );
OAI22X1TS U7641 ( .A0(n690), .A1(n3409), .B0(n3470), .B1(n416), .Y(n3460) );
OAI22X1TS U7642 ( .A0(n3411), .A1(n606), .B0(n3410), .B1(n379), .Y(n3418) );
OAI22X1TS U7643 ( .A0(n3634), .A1(n3415), .B0(n3414), .B1(n570), .Y(n3432)
);
OAI22X1TS U7644 ( .A0(n140), .A1(n3417), .B0(n3416), .B1(n540), .Y(n3431) );
OAI22X1TS U7645 ( .A0(n3694), .A1(n3421), .B0(n3420), .B1(n3715), .Y(n3430)
);
XNOR2X1TS U7646 ( .A(n7108), .B(n142), .Y(n3434) );
OAI22X1TS U7647 ( .A0(n372), .A1(n3424), .B0(n3423), .B1(n3685), .Y(n3428)
);
XNOR2X1TS U7648 ( .A(n500), .B(n3511), .Y(n3435) );
OAI22X1TS U7649 ( .A0(n690), .A1(n3435), .B0(n3434), .B1(n416), .Y(n3502) );
XNOR2X1TS U7650 ( .A(n7106), .B(n608), .Y(n3443) );
XNOR2X1TS U7651 ( .A(n747), .B(n618), .Y(n3445) );
OAI22X1TS U7652 ( .A0(n3445), .A1(n379), .B0(n3440), .B1(n607), .Y(n3492) );
XNOR2X1TS U7653 ( .A(n3677), .B(n3471), .Y(n3507) );
OAI22X1TS U7654 ( .A0(n3507), .A1(n3694), .B0(n609), .B1(n3441), .Y(n3521)
);
XNOR2X1TS U7655 ( .A(n3467), .B(n3675), .Y(n3505) );
OAI22X1TS U7656 ( .A0(n366), .A1(n3505), .B0(n3442), .B1(n570), .Y(n3520) );
OAI22X1TS U7657 ( .A0(n3446), .A1(n379), .B0(n3445), .B1(n607), .Y(n3503) );
CMPR32X2TS U7658 ( .A(n3455), .B(n3454), .C(n3453), .CO(n3605), .S(n3477) );
XNOR2X1TS U7659 ( .A(n6860), .B(n3675), .Y(n3612) );
OAI22X1TS U7660 ( .A0(n140), .A1(n3465), .B0(n3612), .B1(n540), .Y(n3615) );
XNOR2X1TS U7661 ( .A(n3629), .B(n790), .Y(n3601) );
XNOR2X1TS U7662 ( .A(n616), .B(n8423), .Y(n3602) );
OAI22X1TS U7663 ( .A0(n366), .A1(n3468), .B0(n3602), .B1(n569), .Y(n3613) );
XNOR2X1TS U7664 ( .A(n319), .B(n747), .Y(n3611) );
OAI22X1TS U7665 ( .A0(n274), .A1(n3469), .B0(n609), .B1(n3611), .Y(n3599) );
XNOR2X1TS U7666 ( .A(n7108), .B(n3635), .Y(n3600) );
OAI22X1TS U7667 ( .A0(n8425), .A1(n3470), .B0(n3600), .B1(n417), .Y(n3598)
);
NOR2X1TS U7668 ( .A(n3472), .B(n8424), .Y(n3607) );
ADDFHX2TS U7669 ( .A(n3477), .B(n3476), .CI(n3475), .CO(n3594), .S(n3452) );
XNOR2X1TS U7670 ( .A(n3629), .B(n3635), .Y(n3509) );
OAI22X1TS U7671 ( .A0(n372), .A1(n3509), .B0(n3490), .B1(n3685), .Y(n3576)
);
XNOR2X1TS U7672 ( .A(n610), .B(n265), .Y(n3512) );
OAI22X1TS U7673 ( .A0(n7105), .A1(n3512), .B0(n3491), .B1(n540), .Y(n3575)
);
OAI22X1TS U7674 ( .A0(n366), .A1(n3506), .B0(n3505), .B1(n569), .Y(n3548) );
OAI22X1TS U7675 ( .A0(n274), .A1(n3508), .B0(n3715), .B1(n3507), .Y(n3547)
);
XNOR2X1TS U7676 ( .A(n6860), .B(n3511), .Y(n3513) );
OAI22X1TS U7677 ( .A0(n7105), .A1(n3513), .B0(n3512), .B1(n540), .Y(n3557)
);
NAND2X1TS U7678 ( .A(n3555), .B(n3557), .Y(n3518) );
INVX2TS U7679 ( .A(n6860), .Y(n7103) );
NAND2BX1TS U7680 ( .AN(n3514), .B(n6860), .Y(n3515) );
CMPR32X2TS U7681 ( .A(n3521), .B(n3520), .C(n3519), .CO(n3500), .S(n3580) );
NOR2X1TS U7682 ( .A(n7424), .B(n7416), .Y(n9270) );
NAND2X1TS U7683 ( .A(n3591), .B(n9313), .Y(n3593) );
NOR2X1TS U7684 ( .A(n9175), .B(n9207), .Y(n3546) );
NOR2X1TS U7685 ( .A(n3529), .B(n3528), .Y(n7989) );
NAND2X1TS U7686 ( .A(n5107), .B(n5106), .Y(n5108) );
AOI21X1TS U7687 ( .A0(n3527), .A1(n5093), .B0(n3526), .Y(n7992) );
NAND2XLTS U7688 ( .A(n3529), .B(n3528), .Y(n7990) );
NOR2X1TS U7689 ( .A(n3532), .B(n3531), .Y(n3530) );
INVX2TS U7690 ( .A(n3530), .Y(n8664) );
NAND2X1TS U7691 ( .A(n3532), .B(n3531), .Y(n8663) );
AOI21X1TS U7692 ( .A0(n8665), .A1(n8664), .B0(n3533), .Y(n9223) );
NAND2X1TS U7693 ( .A(n3535), .B(n3534), .Y(n9221) );
NAND2X1TS U7694 ( .A(n3537), .B(n3536), .Y(n9236) );
NOR2X1TS U7695 ( .A(n3540), .B(n3539), .Y(n9212) );
NAND2X1TS U7696 ( .A(n3540), .B(n3539), .Y(n9213) );
NAND2X1TS U7697 ( .A(n3544), .B(n3543), .Y(n9176) );
OAI21X1TS U7698 ( .A0(n9175), .A1(n9208), .B0(n9176), .Y(n3545) );
XOR2X1TS U7699 ( .A(n3557), .B(n3556), .Y(n3577) );
INVX2TS U7700 ( .A(n3567), .Y(n7860) );
OR2X2TS U7701 ( .A(n3565), .B(n3564), .Y(n9165) );
INVX2TS U7702 ( .A(n9164), .Y(n9156) );
NAND2X1TS U7703 ( .A(n3567), .B(n3566), .Y(n9157) );
INVX2TS U7704 ( .A(n9157), .Y(n3568) );
ADDFHX2TS U7705 ( .A(n3579), .B(n3578), .CI(n3577), .CO(n3584), .S(n3587) );
INVX2TS U7706 ( .A(n3589), .Y(n7672) );
NOR2X1TS U7707 ( .A(n7646), .B(n3589), .Y(n9141) );
NAND2X1TS U7708 ( .A(n7646), .B(n3589), .Y(n9142) );
NAND2X1TS U7709 ( .A(n7496), .B(n7494), .Y(n9132) );
NAND2X1TS U7710 ( .A(n7424), .B(n7416), .Y(n9293) );
NAND2X1TS U7711 ( .A(n7625), .B(n7412), .Y(n9297) );
NAND2X1TS U7712 ( .A(n7617), .B(n7618), .Y(n9316) );
NAND2X1TS U7713 ( .A(n8609), .B(n8610), .Y(n8172) );
OAI21X1TS U7714 ( .A0(n8171), .A1(n9316), .B0(n8172), .Y(n3590) );
OAI21X4TS U7715 ( .A0(n3593), .A1(n8167), .B0(n3592), .Y(n9434) );
CMPR32X2TS U7716 ( .A(n3599), .B(n3598), .C(n3597), .CO(n3624), .S(n3595) );
XNOR2X1TS U7717 ( .A(n500), .B(n3647), .Y(n3628) );
OAI22X1TS U7718 ( .A0(n8425), .A1(n3600), .B0(n3628), .B1(n417), .Y(n3627)
);
XNOR2X1TS U7719 ( .A(n3629), .B(n808), .Y(n3630) );
OAI22X1TS U7720 ( .A0(n371), .A1(n3601), .B0(n3685), .B1(n3630), .Y(n3626)
);
OAI22X1TS U7721 ( .A0(n366), .A1(n3602), .B0(n1492), .B1(n569), .Y(n3625) );
CMPR32X2TS U7722 ( .A(n3607), .B(n3608), .C(n3606), .CO(n3621), .S(n3597) );
INVX2TS U7723 ( .A(n3659), .Y(n3640) );
XNOR2X1TS U7724 ( .A(n3695), .B(n6860), .Y(n3631) );
OAI22X1TS U7725 ( .A0(n140), .A1(n3612), .B0(n3631), .B1(n539), .Y(n3638) );
NOR2X1TS U7726 ( .A(n8306), .B(n8305), .Y(n7712) );
XNOR2X1TS U7727 ( .A(n500), .B(n3675), .Y(n3654) );
OAI22X1TS U7728 ( .A0(n8425), .A1(n3628), .B0(n3654), .B1(n416), .Y(n3653)
);
XNOR2X1TS U7729 ( .A(n611), .B(n8423), .Y(n3655) );
OAI22X1TS U7730 ( .A0(n371), .A1(n3630), .B0(n572), .B1(n3655), .Y(n3650) );
XNOR2X1TS U7731 ( .A(n3653), .B(n3650), .Y(n3632) );
XNOR2X1TS U7732 ( .A(n610), .B(n747), .Y(n3649) );
OAI22X1TS U7733 ( .A0(n140), .A1(n3631), .B0(n3649), .B1(n539), .Y(n3652) );
XNOR2X2TS U7734 ( .A(n3632), .B(n3652), .Y(n3664) );
INVX2TS U7735 ( .A(n3692), .Y(n3681) );
XNOR2X1TS U7736 ( .A(n319), .B(n808), .Y(n3678) );
XNOR2X1TS U7737 ( .A(n6860), .B(n6963), .Y(n3683) );
XNOR2X1TS U7738 ( .A(n3695), .B(n7108), .Y(n3682) );
OAI22X1TS U7739 ( .A0(n8425), .A1(n3654), .B0(n3682), .B1(n416), .Y(n3674)
);
OAI22X1TS U7740 ( .A0(n371), .A1(n3655), .B0(n3685), .B1(n3684), .Y(n3673)
);
XNOR2X1TS U7741 ( .A(n3677), .B(n8423), .Y(n3693) );
OAI22X1TS U7742 ( .A0(n3694), .A1(n3678), .B0(n3693), .B1(n609), .Y(n3690)
);
XNOR2X1TS U7743 ( .A(n500), .B(n747), .Y(n3689) );
OAI22X1TS U7744 ( .A0(n690), .A1(n3682), .B0(n3689), .B1(n416), .Y(n3688) );
XNOR2X1TS U7745 ( .A(n6860), .B(n790), .Y(n3697) );
OAI22X1TS U7746 ( .A0(n7105), .A1(n3683), .B0(n3697), .B1(n539), .Y(n3687)
);
OAI22X1TS U7747 ( .A0(n690), .A1(n3689), .B0(n3714), .B1(n417), .Y(n3722) );
OAI22X1TS U7748 ( .A0(n3693), .A1(n3694), .B0(n609), .B1(n318), .Y(n3713) );
NOR2X1TS U7749 ( .A(n3696), .B(n8424), .Y(n7085) );
XNOR2X1TS U7750 ( .A(n6860), .B(n808), .Y(n3719) );
NOR2X1TS U7751 ( .A(n6988), .B(n7015), .Y(n7227) );
NAND2X1TS U7752 ( .A(n8306), .B(n8305), .Y(n8150) );
NAND2X1TS U7753 ( .A(n8300), .B(n8304), .Y(n7715) );
NAND2X1TS U7754 ( .A(n6996), .B(n8224), .Y(n7690) );
NAND2X1TS U7755 ( .A(n6985), .B(n6974), .Y(n7282) );
NAND2X1TS U7756 ( .A(n7015), .B(n6988), .Y(n9435) );
CMPR32X2TS U7757 ( .A(n3713), .B(n3712), .C(n3711), .CO(n7095), .S(n3720) );
XNOR2X1TS U7758 ( .A(n500), .B(n790), .Y(n7088) );
OAI22X1TS U7759 ( .A0(n690), .A1(n3714), .B0(n7088), .B1(n417), .Y(n7091) );
AO21X2TS U7760 ( .A0(n274), .A1(n3715), .B0(n318), .Y(n7090) );
NOR2X1TS U7761 ( .A(n436), .B(n3718), .Y(n7084) );
XNOR2X1TS U7762 ( .A(n6860), .B(n8423), .Y(n7086) );
ADDFHX2TS U7763 ( .A(n3722), .B(n3721), .CI(n3720), .CO(n7093), .S(n3709) );
NAND2X1TS U7764 ( .A(n7055), .B(n7054), .Y(n7228) );
NAND2X1TS U7765 ( .A(n8008), .B(n8007), .Y(n4543) );
XNOR2X1TS U7766 ( .A(n6314), .B(n397), .Y(n3856) );
XOR2X1TS U7767 ( .A(n4821), .B(n3802), .Y(n3729) );
NAND2X1TS U7768 ( .A(n3735), .B(n4395), .Y(n3736) );
XNOR2X1TS U7769 ( .A(n6370), .B(n397), .Y(n4402) );
OAI22X1TS U7770 ( .A0(n3856), .A1(n399), .B0(n4402), .B1(n450), .Y(n4413) );
NAND2X1TS U7771 ( .A(n3741), .B(n3740), .Y(n3742) );
NAND2X1TS U7772 ( .A(Data_B_i[18]), .B(Data_B_i[4]), .Y(n3744) );
NAND2X1TS U7773 ( .A(Data_B_i[16]), .B(Data_B_i[2]), .Y(n3747) );
NAND2X2TS U7774 ( .A(n3804), .B(n3800), .Y(n3749) );
NAND2X1TS U7775 ( .A(n1077), .B(n3752), .Y(n3753) );
XNOR2X1TS U7776 ( .A(n6053), .B(n382), .Y(n3793) );
XOR2X1TS U7777 ( .A(n3756), .B(n3761), .Y(n3757) );
XNOR2X1TS U7778 ( .A(n512), .B(n282), .Y(n3787) );
XNOR2X1TS U7779 ( .A(n279), .B(n283), .Y(n3847) );
OAI22X1TS U7780 ( .A0(n549), .A1(n3787), .B0(n1389), .B1(n3847), .Y(n3781)
);
XNOR2X1TS U7781 ( .A(Data_A_i[4]), .B(n241), .Y(n3796) );
XNOR2X1TS U7782 ( .A(Data_B_i[1]), .B(Data_A_i[5]), .Y(n3759) );
OAI22X1TS U7783 ( .A0(n349), .A1(n3796), .B0(n3759), .B1(n543), .Y(n3791) );
OAI22X1TS U7784 ( .A0(n367), .A1(n1567), .B0(n4239), .B1(n3758), .Y(n3790)
);
XNOR2X1TS U7785 ( .A(n241), .B(Data_A_i[6]), .Y(n3842) );
XNOR2X1TS U7786 ( .A(n261), .B(n4087), .Y(n3788) );
XNOR2X1TS U7787 ( .A(n261), .B(n746), .Y(n3849) );
OAI22X1TS U7788 ( .A0(n367), .A1(n3788), .B0(n599), .B1(n3849), .Y(n3844) );
NOR2X1TS U7789 ( .A(Data_B_i[5]), .B(Data_B_i[19]), .Y(n3762) );
NOR2X1TS U7790 ( .A(n1607), .B(n3764), .Y(n3765) );
XOR2X1TS U7791 ( .A(n3765), .B(n4404), .Y(n3766) );
NAND2X1TS U7792 ( .A(Data_B_i[20]), .B(Data_B_i[6]), .Y(n3767) );
XNOR2X1TS U7793 ( .A(n3775), .B(n631), .Y(n3776) );
XNOR2X1TS U7794 ( .A(n4967), .B(n292), .Y(n3784) );
XNOR2X1TS U7795 ( .A(n336), .B(Data_A_i[18]), .Y(n3839) );
NAND2X4TS U7796 ( .A(n254), .B(n3728), .Y(n4823) );
XNOR2X1TS U7797 ( .A(Data_B_i[15]), .B(Data_A_i[18]), .Y(n3794) );
XNOR2X1TS U7798 ( .A(n242), .B(Data_A_i[19]), .Y(n3778) );
OAI22X1TS U7799 ( .A0(n4823), .A1(n3794), .B0(n3778), .B1(n4821), .Y(n3786)
);
OAI22X1TS U7800 ( .A0(n6086), .A1(n6083), .B0(n6084), .B1(n3777), .Y(n3785)
);
XNOR2X1TS U7801 ( .A(Data_B_i[15]), .B(Data_A_i[20]), .Y(n3833) );
XNOR2X1TS U7802 ( .A(n475), .B(n290), .Y(n3782) );
XNOR2X1TS U7803 ( .A(n475), .B(Data_A_i[16]), .Y(n3841) );
OAI22X1TS U7804 ( .A0(n1289), .A1(n3782), .B0(n6084), .B1(n3841), .Y(n3836)
);
INVX2TS U7805 ( .A(n6332), .Y(n3822) );
INVX2TS U7806 ( .A(n4128), .Y(n3821) );
XNOR2X1TS U7807 ( .A(Data_B_i[19]), .B(n4570), .Y(n3783) );
XNOR2X1TS U7808 ( .A(Data_A_i[16]), .B(Data_B_i[17]), .Y(n3795) );
ADDHX1TS U7809 ( .A(n3786), .B(n3785), .CO(n3831), .S(n3858) );
XNOR2X1TS U7810 ( .A(n512), .B(n746), .Y(n3797) );
OAI22X1TS U7811 ( .A0(n549), .A1(n3797), .B0(n259), .B1(n3787), .Y(n3855) );
XNOR2X1TS U7812 ( .A(n262), .B(Data_A_i[0]), .Y(n3789) );
OAI22X1TS U7813 ( .A0(n367), .A1(n3789), .B0(n4239), .B1(n3788), .Y(n3854)
);
INVX2TS U7814 ( .A(n4127), .Y(n3823) );
XNOR2X1TS U7815 ( .A(n5068), .B(n3792), .Y(n3851) );
OAI22X1TS U7816 ( .A0(n3793), .A1(n487), .B0(n590), .B1(n3851), .Y(n3829) );
XNOR2X1TS U7817 ( .A(Data_A_i[17]), .B(Data_B_i[15]), .Y(n3860) );
OAI22X1TS U7818 ( .A0(n4823), .A1(n3860), .B0(n3794), .B1(n3728), .Y(n3807)
);
XNOR2X1TS U7819 ( .A(n336), .B(n290), .Y(n3861) );
XNOR2X1TS U7820 ( .A(n512), .B(n4087), .Y(n3866) );
OAI22X1TS U7821 ( .A0(n550), .A1(n3866), .B0(n259), .B1(n3797), .Y(n3808) );
INVX2TS U7822 ( .A(n3798), .Y(n3813) );
NAND2X1TS U7823 ( .A(n3813), .B(n3811), .Y(n3799) );
XNOR2X1TS U7824 ( .A(n6057), .B(n6052), .Y(n3826) );
XNOR2X1TS U7825 ( .A(n6050), .B(n6052), .Y(n3859) );
OAI22X1TS U7826 ( .A0(n3826), .A1(n6162), .B0(n593), .B1(n3859), .Y(n3827)
);
NOR2BX1TS U7827 ( .AN(n630), .B(n6312), .Y(n3908) );
INVX2TS U7828 ( .A(n4123), .Y(n3906) );
NAND2XLTS U7829 ( .A(n3817), .B(n3816), .Y(n3818) );
XNOR2X1TS U7830 ( .A(n6186), .B(n397), .Y(n3857) );
XNOR2X1TS U7831 ( .A(n6057), .B(n397), .Y(n3879) );
OAI22X1TS U7832 ( .A0(n3857), .A1(n450), .B0(n3879), .B1(n3730), .Y(n3953)
);
OAI22X1TS U7833 ( .A0(n4407), .A1(n6162), .B0(n3826), .B1(n593), .Y(n4382)
);
INVX2TS U7834 ( .A(n6641), .Y(n4380) );
XNOR2X1TS U7835 ( .A(n242), .B(Data_A_i[21]), .Y(n4384) );
OAI22X1TS U7836 ( .A0(n334), .A1(n3833), .B0(n4384), .B1(n4821), .Y(n4392)
);
XOR2X4TS U7837 ( .A(Data_B_i[21]), .B(Data_B_i[20]), .Y(n3834) );
OAI22X1TS U7838 ( .A0(n356), .A1(n329), .B0(n605), .B1(n3835), .Y(n4391) );
XNOR2X1TS U7839 ( .A(n336), .B(Data_A_i[19]), .Y(n4389) );
XNOR2X1TS U7840 ( .A(n239), .B(n4570), .Y(n3840) );
XNOR2X1TS U7841 ( .A(Data_B_i[21]), .B(Data_A_i[15]), .Y(n4385) );
XNOR2X1TS U7842 ( .A(n6038), .B(n292), .Y(n4390) );
OAI22X1TS U7843 ( .A0(n1289), .A1(n3841), .B0(n571), .B1(n4390), .Y(n4386)
);
OAI22X1TS U7844 ( .A0(n349), .A1(n3842), .B0(n4098), .B1(n542), .Y(n4093) );
INVX2TS U7845 ( .A(Data_B_i[7]), .Y(n4281) );
NAND2BX1TS U7846 ( .AN(n276), .B(n322), .Y(n3843) );
XNOR2X1TS U7847 ( .A(n512), .B(n674), .Y(n4089) );
XNOR2X1TS U7848 ( .A(n276), .B(n322), .Y(n3848) );
XNOR2X1TS U7849 ( .A(n322), .B(n4087), .Y(n4100) );
XNOR2X1TS U7850 ( .A(n261), .B(n282), .Y(n4091) );
OAI22X1TS U7851 ( .A0(n368), .A1(n3849), .B0(n4239), .B1(n4091), .Y(n4101)
);
INVX2TS U7852 ( .A(n4129), .Y(n4378) );
INVX2TS U7853 ( .A(n4124), .Y(n3871) );
OAI22X1TS U7854 ( .A0(n3857), .A1(n399), .B0(n3856), .B1(n450), .Y(n3881) );
INVX2TS U7855 ( .A(n6341), .Y(n3870) );
XNOR2X1TS U7856 ( .A(n254), .B(n291), .Y(n3902) );
OAI22X1TS U7857 ( .A0(n334), .A1(n3902), .B0(n3860), .B1(n4821), .Y(n3876)
);
XNOR2X1TS U7858 ( .A(n336), .B(n4600), .Y(n3862) );
OAI22X1TS U7859 ( .A0(n5041), .A1(n3862), .B0(n1290), .B1(n3861), .Y(n3875)
);
OAI22X1TS U7860 ( .A0(n6040), .A1(n335), .B0(n532), .B1(n3863), .Y(n6333) );
OAI22X1TS U7861 ( .A0(n549), .A1(n4031), .B0(n1389), .B1(n3864), .Y(n4119)
);
INVX1TS U7862 ( .A(n4119), .Y(n3877) );
XNOR2X1TS U7863 ( .A(n241), .B(n746), .Y(n3904) );
OAI22X1TS U7864 ( .A0(n349), .A1(n3904), .B0(n3865), .B1(n543), .Y(n3901) );
XNOR2X1TS U7865 ( .A(n512), .B(n276), .Y(n3867) );
OAI22X1TS U7866 ( .A0(n550), .A1(n3867), .B0(n1389), .B1(n3866), .Y(n3900)
);
XNOR2X1TS U7867 ( .A(n5068), .B(n6052), .Y(n3889) );
OAI22X1TS U7868 ( .A0(n3874), .A1(n481), .B0(n6164), .B1(n3889), .Y(n3897)
);
ADDHX1TS U7869 ( .A(n3876), .B(n3875), .CO(n6338), .S(n6336) );
INVX2TS U7870 ( .A(n6336), .Y(n3893) );
XNOR2X1TS U7871 ( .A(n6050), .B(n396), .Y(n3891) );
OAI22X1TS U7872 ( .A0(n3879), .A1(n449), .B0(n3891), .B1(n399), .Y(n3895) );
INVX2TS U7873 ( .A(n4452), .Y(n3888) );
NAND2X1TS U7874 ( .A(n3888), .B(n4454), .Y(n3972) );
XNOR2X1TS U7875 ( .A(n460), .B(n631), .Y(n3890) );
OAI22X1TS U7876 ( .A0(n593), .A1(n3890), .B0(n3889), .B1(n481), .Y(n3918) );
XNOR2X1TS U7877 ( .A(n6053), .B(n396), .Y(n3925) );
OAI22X1TS U7878 ( .A0(n3891), .A1(n450), .B0(n3925), .B1(n3730), .Y(n3917)
);
ADDHX1TS U7879 ( .A(n3901), .B(n3900), .CO(n4122), .S(n4120) );
INVX2TS U7880 ( .A(n4120), .Y(n3915) );
XNOR2X1TS U7881 ( .A(n254), .B(n290), .Y(n3926) );
OAI22X1TS U7882 ( .A0(n334), .A1(n3926), .B0(n3902), .B1(n4821), .Y(n6335)
);
INVX2TS U7883 ( .A(n6335), .Y(n3924) );
INVX2TS U7884 ( .A(n5024), .Y(n3923) );
OAI22X1TS U7885 ( .A0(n593), .A1(n459), .B0(n481), .B1(n3905), .Y(n3913) );
XNOR2X1TS U7886 ( .A(n3910), .B(n3909), .Y(n3935) );
NAND2X1TS U7887 ( .A(n3912), .B(n349), .Y(n5100) );
NOR2BX1TS U7888 ( .AN(n630), .B(n481), .Y(n3933) );
XNOR2X1TS U7889 ( .A(n5068), .B(n396), .Y(n3939) );
OAI22X1TS U7890 ( .A0(n3925), .A1(n449), .B0(n3939), .B1(n3730), .Y(n3931)
);
OAI22X1TS U7891 ( .A0(n334), .A1(n4600), .B0(n3926), .B1(n4821), .Y(n5023)
);
NAND2X1TS U7892 ( .A(n3927), .B(n399), .Y(n3937) );
CMPR32X2TS U7893 ( .A(n3932), .B(n3931), .C(n3930), .CO(n3945), .S(n3944) );
CMPR32X2TS U7894 ( .A(n3935), .B(n3934), .C(n3933), .CO(n3921), .S(n3943) );
OAI22X1TS U7895 ( .A0(n3939), .A1(n449), .B0(n3730), .B1(n631), .Y(n3940) );
NOR2X1TS U7896 ( .A(n3941), .B(n3940), .Y(n4340) );
NOR2BX1TS U7897 ( .AN(n4096), .B(n542), .Y(n11191) );
INVX2TS U7898 ( .A(n11191), .Y(n4350) );
NOR2BX1TS U7899 ( .AN(n630), .B(n449), .Y(n4348) );
NAND2X1TS U7900 ( .A(n3941), .B(n3940), .Y(n4341) );
NAND2X1TS U7901 ( .A(n3944), .B(n3943), .Y(n4332) );
NAND2X1TS U7902 ( .A(n3949), .B(n3948), .Y(n4311) );
INVX2TS U7903 ( .A(n4087), .Y(n3973) );
INVX2TS U7904 ( .A(n4202), .Y(n4040) );
XNOR2X1TS U7905 ( .A(n263), .B(Data_A_i[4]), .Y(n3984) );
XNOR2X1TS U7906 ( .A(Data_B_i[11]), .B(n674), .Y(n3974) );
XNOR2X1TS U7907 ( .A(n262), .B(n287), .Y(n3988) );
XNOR2X1TS U7908 ( .A(n256), .B(Data_A_i[6]), .Y(n4002) );
XNOR2X1TS U7909 ( .A(Data_B_i[9]), .B(Data_A_i[7]), .Y(n3992) );
XNOR2X1TS U7910 ( .A(Data_B_i[13]), .B(n746), .Y(n3986) );
XNOR2X1TS U7911 ( .A(Data_B_i[13]), .B(Data_A_i[3]), .Y(n3993) );
XNOR2X1TS U7912 ( .A(Data_B_i[11]), .B(Data_A_i[6]), .Y(n4029) );
OAI22X1TS U7913 ( .A0(n4764), .A1(n3974), .B0(n574), .B1(n4029), .Y(n4028)
);
XNOR2X1TS U7914 ( .A(n262), .B(Data_A_i[12]), .Y(n4038) );
XNOR2X1TS U7915 ( .A(n322), .B(n286), .Y(n3978) );
XNOR2X1TS U7916 ( .A(n322), .B(n287), .Y(n4026) );
XNOR2X1TS U7917 ( .A(n512), .B(Data_A_i[12]), .Y(n3979) );
XNOR2X1TS U7918 ( .A(n279), .B(Data_A_i[13]), .Y(n3994) );
OAI22X1TS U7919 ( .A0(n549), .A1(n3979), .B0(n1389), .B1(n3994), .Y(n3991)
);
XNOR2X1TS U7920 ( .A(n322), .B(n4445), .Y(n4000) );
NOR2BX1TS U7921 ( .AN(n276), .B(n621), .Y(n3982) );
XNOR2X1TS U7922 ( .A(n512), .B(n288), .Y(n4009) );
OAI22X1TS U7923 ( .A0(n550), .A1(n4009), .B0(n3979), .B1(n259), .Y(n3980) );
XNOR2X1TS U7924 ( .A(Data_B_i[7]), .B(Data_A_i[6]), .Y(n4019) );
XNOR2X1TS U7925 ( .A(n520), .B(Data_A_i[7]), .Y(n4001) );
XNOR2X1TS U7926 ( .A(n619), .B(Data_A_i[0]), .Y(n3983) );
XNOR2X1TS U7927 ( .A(Data_B_i[13]), .B(n4087), .Y(n3987) );
BUFX8TS U7928 ( .A(n4764), .Y(n4773) );
XNOR2X1TS U7929 ( .A(n263), .B(n746), .Y(n4017) );
XNOR2X1TS U7930 ( .A(n263), .B(n282), .Y(n3985) );
OAI22X1TS U7931 ( .A0(n4773), .A1(n4017), .B0(n575), .B1(n3985), .Y(n4053)
);
OAI22X1TS U7932 ( .A0(n4764), .A1(n3985), .B0(n575), .B1(n3984), .Y(n3999)
);
XNOR2X1TS U7933 ( .A(n262), .B(n286), .Y(n4010) );
OAI22X1TS U7934 ( .A0(n367), .A1(n4010), .B0(n599), .B1(n3988), .Y(n3997) );
XNOR2X1TS U7935 ( .A(n240), .B(n4445), .Y(n4039) );
OAI22X1TS U7936 ( .A0(n365), .A1(n3992), .B0(n4531), .B1(n4039), .Y(n4037)
);
XNOR2X1TS U7937 ( .A(n509), .B(n283), .Y(n4030) );
OAI22X1TS U7938 ( .A0(n4279), .A1(n3993), .B0(n1021), .B1(n4030), .Y(n4036)
);
ADDFHX1TS U7939 ( .A(n4040), .B(n3996), .CI(n3995), .CO(n4043), .S(n4007) );
ADDFHX2TS U7940 ( .A(n3999), .B(n3998), .CI(n3997), .CO(n4006), .S(n4050) );
XNOR2X1TS U7941 ( .A(n256), .B(n674), .Y(n4008) );
OAI22X1TS U7942 ( .A0(n365), .A1(n4008), .B0(n573), .B1(n4002), .Y(n4012) );
XNOR2X1TS U7943 ( .A(Data_A_i[12]), .B(n253), .Y(n4016) );
OAI22X1TS U7944 ( .A0(n349), .A1(n4016), .B0(n4003), .B1(n543), .Y(n4015) );
XNOR2X1TS U7945 ( .A(n240), .B(Data_A_i[4]), .Y(n4021) );
OAI22X1TS U7946 ( .A0(n4444), .A1(n4021), .B0(n573), .B1(n4008), .Y(n4057)
);
XNOR2X1TS U7947 ( .A(n279), .B(n287), .Y(n4020) );
XNOR2X1TS U7948 ( .A(n262), .B(n4445), .Y(n4058) );
OAI22X1TS U7949 ( .A0(n367), .A1(n4058), .B0(n599), .B1(n4010), .Y(n4055) );
ADDHX1TS U7950 ( .A(n4015), .B(n4014), .CO(n4011), .S(n4083) );
XNOR2X1TS U7951 ( .A(Data_A_i[11]), .B(n253), .Y(n4059) );
OAI22X1TS U7952 ( .A0(n349), .A1(n4059), .B0(n4016), .B1(n543), .Y(n4062) );
XNOR2X1TS U7953 ( .A(n4087), .B(Data_B_i[11]), .Y(n4072) );
OAI22X1TS U7954 ( .A0(n4773), .A1(n4072), .B0(n575), .B1(n4017), .Y(n4063)
);
XNOR2X1TS U7955 ( .A(Data_B_i[3]), .B(Data_A_i[9]), .Y(n4074) );
XNOR2X1TS U7956 ( .A(n256), .B(Data_A_i[3]), .Y(n4078) );
OAI22X1TS U7957 ( .A0(n4444), .A1(n4078), .B0(n4531), .B1(n4021), .Y(n4075)
);
XNOR2X1TS U7958 ( .A(n322), .B(n288), .Y(n4208) );
XNOR2X1TS U7959 ( .A(n263), .B(n285), .Y(n4214) );
OAI22X1TS U7960 ( .A0(n4773), .A1(n4029), .B0(n575), .B1(n4214), .Y(n4205)
);
XNOR2X1TS U7961 ( .A(n509), .B(n674), .Y(n4213) );
OAI22X1TS U7962 ( .A0(n4279), .A1(n4030), .B0(n4881), .B1(n4213), .Y(n4204)
);
XNOR2X1TS U7963 ( .A(n261), .B(Data_A_i[13]), .Y(n4207) );
OAI22X1TS U7964 ( .A0(n368), .A1(n4038), .B0(n4239), .B1(n4207), .Y(n4218)
);
XNOR2X1TS U7965 ( .A(n256), .B(n286), .Y(n4215) );
OAI22X1TS U7966 ( .A0(n365), .A1(n4039), .B0(n573), .B1(n4215), .Y(n4217) );
ADDFHX2TS U7967 ( .A(n4046), .B(n4045), .CI(n4044), .CO(n6161), .S(n6175) );
NOR2X1TS U7968 ( .A(n4327), .B(n4318), .Y(n4199) );
XNOR2X1TS U7969 ( .A(n262), .B(Data_A_i[7]), .Y(n4077) );
OAI22X1TS U7970 ( .A0(n368), .A1(n4077), .B0(n4239), .B1(n4058), .Y(n4184)
);
XNOR2X1TS U7971 ( .A(n287), .B(n253), .Y(n4141) );
OAI22X1TS U7972 ( .A0(n349), .A1(n4141), .B0(n4059), .B1(n542), .Y(n4080) );
OAI22X1TS U7973 ( .A0(n4773), .A1(n1631), .B0(n575), .B1(n4060), .Y(n4079)
);
XOR2X1TS U7974 ( .A(n4062), .B(n4061), .Y(n4064) );
XNOR2X1TS U7975 ( .A(n520), .B(Data_A_i[4]), .Y(n4151) );
XNOR2X1TS U7976 ( .A(n263), .B(Data_A_i[0]), .Y(n4073) );
XNOR2X1TS U7977 ( .A(n512), .B(n4445), .Y(n4155) );
OAI22X1TS U7978 ( .A0(n549), .A1(n4155), .B0(n259), .B1(n4074), .Y(n4159) );
OAI22X1TS U7979 ( .A0(n367), .A1(n4153), .B0(n4239), .B1(n4077), .Y(n4138)
);
XNOR2X1TS U7980 ( .A(Data_B_i[9]), .B(Data_A_i[2]), .Y(n4143) );
OAI22X1TS U7981 ( .A0(n365), .A1(n4143), .B0(n573), .B1(n4078), .Y(n4137) );
XNOR2X1TS U7982 ( .A(n520), .B(n746), .Y(n4099) );
XNOR2X1TS U7983 ( .A(n322), .B(n282), .Y(n4152) );
XNOR2X1TS U7984 ( .A(n256), .B(n4096), .Y(n4088) );
OAI22X1TS U7985 ( .A0(n4444), .A1(n4088), .B0(n573), .B1(n4144), .Y(n4146)
);
XNOR2X1TS U7986 ( .A(n261), .B(n283), .Y(n4090) );
XNOR2X1TS U7987 ( .A(n261), .B(n674), .Y(n4154) );
OAI22X1TS U7988 ( .A0(n367), .A1(n4090), .B0(n599), .B1(n4154), .Y(n4145) );
XNOR2X1TS U7989 ( .A(n512), .B(n284), .Y(n4094) );
OAI22X1TS U7990 ( .A0(n550), .A1(n4089), .B0(n1389), .B1(n4094), .Y(n4109)
);
ADDHX1TS U7991 ( .A(n4093), .B(n4092), .CO(n4107), .S(n4115) );
XNOR2X1TS U7992 ( .A(n512), .B(n285), .Y(n4157) );
OAI22X1TS U7993 ( .A0(n550), .A1(n4094), .B0(n259), .B1(n4157), .Y(n4167) );
OAI22X1TS U7994 ( .A0(n349), .A1(n4097), .B0(n4142), .B1(n542), .Y(n4140) );
OAI22X1TS U7995 ( .A0(n365), .A1(n133), .B0(n4531), .B1(n4095), .Y(n4139) );
NOR2X1TS U7996 ( .A(n9169), .B(n9182), .Y(n4135) );
NOR2X1TS U7997 ( .A(n4129), .B(n4130), .Y(n4116) );
INVX2TS U7998 ( .A(n4116), .Y(n9190) );
OR2X2TS U7999 ( .A(n4128), .B(n4127), .Y(n9194) );
NAND2X1TS U8000 ( .A(n9190), .B(n9194), .Y(n4133) );
NOR2X1TS U8001 ( .A(n4118), .B(n4117), .Y(n5095) );
NAND2X1TS U8002 ( .A(n5100), .B(n5099), .Y(n5101) );
NAND2X1TS U8003 ( .A(n4118), .B(n4117), .Y(n5096) );
OAI21X1TS U8004 ( .A0(n5095), .A1(n5101), .B0(n5096), .Y(n7995) );
NAND2X1TS U8005 ( .A(n4120), .B(n4119), .Y(n7994) );
INVX1TS U8006 ( .A(n7994), .Y(n4121) );
AOI21X1TS U8007 ( .A0(n213), .A1(n7995), .B0(n4121), .Y(n8658) );
NAND2X1TS U8008 ( .A(n4123), .B(n4122), .Y(n8656) );
NAND2X1TS U8009 ( .A(n4125), .B(n4124), .Y(n9197) );
INVX1TS U8010 ( .A(n9197), .Y(n4126) );
AOI21X1TS U8011 ( .A0(n9199), .A1(n9198), .B0(n4126), .Y(n9187) );
NAND2X1TS U8012 ( .A(n4128), .B(n4127), .Y(n9193) );
INVX2TS U8013 ( .A(n9193), .Y(n9188) );
NAND2X1TS U8014 ( .A(n4130), .B(n4129), .Y(n9189) );
AOI21X1TS U8015 ( .A0(n9190), .A1(n9188), .B0(n4131), .Y(n4132) );
NAND2X1TS U8016 ( .A(n4485), .B(n4457), .Y(n9170) );
OAI21X1TS U8017 ( .A0(n9169), .A1(n9183), .B0(n9170), .Y(n4134) );
ADDHX1TS U8018 ( .A(n4140), .B(n4139), .CO(n4170), .S(n4166) );
OAI22X1TS U8019 ( .A0(n349), .A1(n4142), .B0(n4141), .B1(n543), .Y(n4149) );
OAI22X1TS U8020 ( .A0(n550), .A1(n4157), .B0(n259), .B1(n4155), .Y(n4162) );
ADDFHX2TS U8021 ( .A(n4170), .B(n4169), .CI(n4168), .CO(n4195), .S(n4171) );
ADDFHX2TS U8022 ( .A(n4173), .B(n4172), .CI(n4171), .CO(n4644), .S(n4687) );
NAND2X1TS U8023 ( .A(n4687), .B(n4624), .Y(n9160) );
INVX2TS U8024 ( .A(n9151), .Y(n4177) );
NOR2X1TS U8025 ( .A(n9125), .B(n9136), .Y(n4197) );
NAND2X1TS U8026 ( .A(n5075), .B(n5056), .Y(n4337) );
NAND2X1TS U8027 ( .A(n6125), .B(n6175), .Y(n4328) );
NAND2X1TS U8028 ( .A(n6174), .B(n6161), .Y(n4319) );
INVX2TS U8029 ( .A(Data_A_i[4]), .Y(n4206) );
XNOR2X1TS U8030 ( .A(n322), .B(n289), .Y(n4237) );
XNOR2X1TS U8031 ( .A(n509), .B(n284), .Y(n4241) );
OAI22X1TS U8032 ( .A0(n244), .A1(n4213), .B0(n1021), .B1(n4241), .Y(n4236)
);
XNOR2X1TS U8033 ( .A(n521), .B(n4445), .Y(n4238) );
XNOR2X1TS U8034 ( .A(n256), .B(n287), .Y(n4243) );
OAI22X1TS U8035 ( .A0(n365), .A1(n4215), .B0(n4531), .B1(n4243), .Y(n4234)
);
NOR2X1TS U8036 ( .A(n6056), .B(n6027), .Y(n4298) );
CMPR32X2TS U8037 ( .A(n4236), .B(n4235), .C(n4234), .CO(n4265), .S(n4233) );
XNOR2X1TS U8038 ( .A(n322), .B(Data_A_i[13]), .Y(n4253) );
XNOR2X1TS U8039 ( .A(n263), .B(n286), .Y(n4258) );
OAI22X1TS U8040 ( .A0(n4764), .A1(n4238), .B0(n574), .B1(n4258), .Y(n4256)
);
XNOR2X1TS U8041 ( .A(n509), .B(n285), .Y(n4259) );
OAI22X1TS U8042 ( .A0(n244), .A1(n4241), .B0(n4881), .B1(n4259), .Y(n4251)
);
INVX2TS U8043 ( .A(n674), .Y(n4242) );
XNOR2X1TS U8044 ( .A(n256), .B(Data_A_i[11]), .Y(n4254) );
OAI22X1TS U8045 ( .A0(n4444), .A1(n4243), .B0(n4531), .B1(n4254), .Y(n4260)
);
NOR2X1TS U8046 ( .A(n4298), .B(n4299), .Y(n4421) );
INVX2TS U8047 ( .A(n284), .Y(n4252) );
XNOR2X1TS U8048 ( .A(n240), .B(n289), .Y(n4274) );
OAI22X1TS U8049 ( .A0(n365), .A1(n4254), .B0(n573), .B1(n4274), .Y(n4275) );
XNOR2X1TS U8050 ( .A(n263), .B(n287), .Y(n4280) );
OAI22X1TS U8051 ( .A0(n4773), .A1(n4258), .B0(n575), .B1(n4280), .Y(n4272)
);
XNOR2X1TS U8052 ( .A(n509), .B(n4445), .Y(n4278) );
OAI22X1TS U8053 ( .A0(n4279), .A1(n4259), .B0(n4881), .B1(n4278), .Y(n4271)
);
NOR2X1TS U8054 ( .A(n6287), .B(n6320), .Y(n4420) );
NAND2X1TS U8055 ( .A(n6111), .B(n6193), .Y(n4300) );
NAND2X1TS U8056 ( .A(n6287), .B(n6320), .Y(n4424) );
OAI21X1TS U8057 ( .A0(n4267), .A1(n4420), .B0(n4424), .Y(n4268) );
NOR2X1TS U8058 ( .A(n621), .B(n4273), .Y(n4441) );
XNOR2X1TS U8059 ( .A(n256), .B(Data_A_i[13]), .Y(n4443) );
OAI22X1TS U8060 ( .A0(n365), .A1(n4274), .B0(n4531), .B1(n4443), .Y(n4440)
);
XNOR2X1TS U8061 ( .A(n509), .B(n286), .Y(n4439) );
OAI22X1TS U8062 ( .A0(n4279), .A1(n4278), .B0(n4881), .B1(n4439), .Y(n4438)
);
XNOR2X1TS U8063 ( .A(n263), .B(n288), .Y(n4447) );
OAI22X1TS U8064 ( .A0(n4764), .A1(n4280), .B0(n575), .B1(n4447), .Y(n4437)
);
NOR2X1TS U8065 ( .A(n6358), .B(n6369), .Y(n4423) );
NAND2X1TS U8066 ( .A(n6369), .B(n6358), .Y(n4422) );
NAND2X1TS U8067 ( .A(n4288), .B(n4422), .Y(n4289) );
NAND2X1TS U8068 ( .A(n4290), .B(n4424), .Y(n4291) );
INVX2TS U8069 ( .A(n4293), .Y(n4295) );
NAND2X1TS U8070 ( .A(n4295), .B(n4294), .Y(n4297) );
NOR2X2TS U8071 ( .A(n7274), .B(n7273), .Y(n4367) );
NAND2X1TS U8072 ( .A(n4304), .B(n4303), .Y(n4306) );
XNOR2X1TS U8073 ( .A(n4306), .B(n4305), .Y(n4358) );
NAND2X1TS U8074 ( .A(n4312), .B(n4311), .Y(n4314) );
NOR2X1TS U8075 ( .A(n4357), .B(n4356), .Y(n4315) );
INVX2TS U8076 ( .A(n4315), .Y(n7707) );
NAND2X1TS U8077 ( .A(n4320), .B(n4319), .Y(n4321) );
NAND2X1TS U8078 ( .A(n207), .B(n4322), .Y(n4324) );
XNOR2X1TS U8079 ( .A(n4324), .B(n4323), .Y(n4355) );
NAND2X1TS U8080 ( .A(n4329), .B(n4328), .Y(n4330) );
NAND2X1TS U8081 ( .A(n4333), .B(n4332), .Y(n4334) );
AOI21X2TS U8082 ( .A0(n4347), .A1(n4346), .B0(n4335), .Y(n4339) );
NAND2X1TS U8083 ( .A(n945), .B(n4337), .Y(n4338) );
NAND2X1TS U8084 ( .A(n4342), .B(n4341), .Y(n4344) );
XNOR2X1TS U8085 ( .A(n4344), .B(n4343), .Y(n4351) );
CMPR32X2TS U8086 ( .A(n4350), .B(n4349), .C(n4348), .CO(n4343), .S(n9269) );
NAND2X1TS U8087 ( .A(n4357), .B(n4356), .Y(n7706) );
INVX2TS U8088 ( .A(n7706), .Y(n7695) );
ADDFHX2TS U8089 ( .A(n4376), .B(n4375), .CI(n4374), .CO(n6647), .S(n6642) );
INVX2TS U8090 ( .A(n6647), .Y(n4493) );
INVX2TS U8091 ( .A(n4377), .Y(n4492) );
NOR2BX1TS U8092 ( .AN(n4600), .B(n6415), .Y(n4484) );
XNOR2X1TS U8093 ( .A(Data_B_i[15]), .B(Data_A_i[22]), .Y(n4479) );
XNOR2X1TS U8094 ( .A(n239), .B(Data_A_i[16]), .Y(n4472) );
OAI22X1TS U8095 ( .A0(n356), .A1(n4385), .B0(n604), .B1(n4472), .Y(n4482) );
XNOR2X1TS U8096 ( .A(Data_B_i[17]), .B(n340), .Y(n4481) );
OAI22X1TS U8097 ( .A0(n5041), .A1(n4389), .B0(n1290), .B1(n4481), .Y(n4478)
);
XNOR2X1TS U8098 ( .A(n475), .B(n338), .Y(n4475) );
OAI21X1TS U8099 ( .A0(n4397), .A1(n4396), .B0(n4395), .Y(n4398) );
NAND2X1TS U8100 ( .A(n4487), .B(n4647), .Y(n4401) );
XNOR2X1TS U8101 ( .A(n6411), .B(n396), .Y(n4491) );
OAI22X1TS U8102 ( .A0(n4402), .A1(n3730), .B0(n4491), .B1(n449), .Y(n4463)
);
NOR2BX1TS U8103 ( .AN(n630), .B(n478), .Y(n4460) );
XNOR2X1TS U8104 ( .A(n6053), .B(n3775), .Y(n4495) );
XNOR2X1TS U8105 ( .A(n6057), .B(n383), .Y(n4471) );
OAI22X1TS U8106 ( .A0(n4471), .A1(n487), .B0(n4406), .B1(n590), .Y(n4458) );
OAI22X1TS U8107 ( .A0(n4407), .A1(n592), .B0(n4461), .B1(n481), .Y(n4466) );
ADDFHX2TS U8108 ( .A(n4413), .B(n4412), .CI(n4411), .CO(n4468), .S(n4416) );
NOR2X1TS U8109 ( .A(n4420), .B(n4423), .Y(n4426) );
NAND2X2TS U8110 ( .A(n4421), .B(n4426), .Y(n4918) );
OAI21X1TS U8111 ( .A0(n4424), .A1(n4423), .B0(n4422), .Y(n4425) );
XNOR2X1TS U8112 ( .A(n509), .B(n287), .Y(n4530) );
OAI22X1TS U8113 ( .A0(n244), .A1(n4439), .B0(n1021), .B1(n4530), .Y(n4526)
);
ADDFHX1TS U8114 ( .A(n4442), .B(n4441), .CI(n4440), .CO(n4525), .S(n4435) );
INVX2TS U8115 ( .A(n4445), .Y(n4446) );
XNOR2X1TS U8116 ( .A(n263), .B(Data_A_i[12]), .Y(n4533) );
OAI22X1TS U8117 ( .A0(n4773), .A1(n4447), .B0(n575), .B1(n4533), .Y(n4527)
);
INVX2TS U8118 ( .A(n4518), .Y(n4755) );
NAND2X1TS U8119 ( .A(n6421), .B(n6409), .Y(n4779) );
NAND2X1TS U8120 ( .A(n4755), .B(n4779), .Y(n4448) );
XOR2X1TS U8121 ( .A(n4449), .B(n4448), .Y(n4450) );
ADDFHX2TS U8122 ( .A(n4464), .B(n4463), .CI(n4462), .CO(n4720), .S(n4470) );
XNOR2X1TS U8123 ( .A(n6186), .B(n383), .Y(n4620) );
OAI22X1TS U8124 ( .A0(n4620), .A1(n488), .B0(n4471), .B1(n590), .Y(n4703) );
XNOR2X1TS U8125 ( .A(n239), .B(Data_A_i[17]), .Y(n4566) );
OAI22X1TS U8126 ( .A0(n6304), .A1(n4472), .B0(n605), .B1(n4566), .Y(n4562)
);
XNOR2X1TS U8127 ( .A(n514), .B(n4570), .Y(n4474) );
XNOR2X1TS U8128 ( .A(Data_B_i[23]), .B(Data_A_i[15]), .Y(n4559) );
XNOR2X1TS U8129 ( .A(Data_B_i[19]), .B(Data_A_i[19]), .Y(n4568) );
OAI22X1TS U8130 ( .A0(n1289), .A1(n4475), .B0(n6084), .B1(n4568), .Y(n4560)
);
XNOR2X1TS U8131 ( .A(n242), .B(Data_A_i[23]), .Y(n4557) );
OAI22X1TS U8132 ( .A0(n4823), .A1(n4479), .B0(n4557), .B1(n3728), .Y(n4555)
);
OAI22X1TS U8133 ( .A0(n6416), .A1(n513), .B0(n563), .B1(n4480), .Y(n4554) );
XNOR2X1TS U8134 ( .A(n4967), .B(Data_A_i[21]), .Y(n4569) );
AOI21X1TS U8135 ( .A0(n4992), .A1(n4487), .B0(n4486), .Y(n4490) );
NAND2X1TS U8136 ( .A(n4488), .B(n4646), .Y(n4489) );
XNOR2X1TS U8137 ( .A(n6437), .B(n397), .Y(n4692) );
OAI22X1TS U8138 ( .A0(n4692), .A1(n449), .B0(n4491), .B1(n399), .Y(n4709) );
XNOR2X1TS U8139 ( .A(n6050), .B(n3775), .Y(n4587) );
OAI22X1TS U8140 ( .A0(n4587), .A1(n472), .B0(n587), .B1(n4495), .Y(n4683) );
XOR2X1TS U8141 ( .A(n238), .B(Data_B_i[22]), .Y(n4497) );
XOR2X1TS U8142 ( .A(n4498), .B(n4576), .Y(n4499) );
NAND2X2TS U8143 ( .A(Data_B_i[22]), .B(Data_B_i[8]), .Y(n4500) );
XNOR2X1TS U8144 ( .A(n451), .B(n631), .Y(n4504) );
XNOR2X1TS U8145 ( .A(n5068), .B(n4502), .Y(n4585) );
OAI22X1TS U8146 ( .A0(n6494), .A1(n4504), .B0(n4585), .B1(n478), .Y(n4616)
);
INVX2TS U8147 ( .A(n6650), .Y(n4681) );
NAND2X2TS U8148 ( .A(n4515), .B(n4514), .Y(n4727) );
XNOR2X1TS U8149 ( .A(n509), .B(n288), .Y(n4765) );
OAI22X1TS U8150 ( .A0(n244), .A1(n4530), .B0(n1021), .B1(n4765), .Y(n4768)
);
INVX2TS U8151 ( .A(n286), .Y(n4532) );
NOR2X1TS U8152 ( .A(n620), .B(n4532), .Y(n4760) );
XNOR2X1TS U8153 ( .A(n521), .B(Data_A_i[13]), .Y(n4763) );
OAI22X1TS U8154 ( .A0(n4764), .A1(n4533), .B0(n575), .B1(n4763), .Y(n4759)
);
NAND2X1TS U8155 ( .A(n6439), .B(n6433), .Y(n4780) );
NAND2X1TS U8156 ( .A(n1705), .B(n4780), .Y(n4534) );
NAND2X1TS U8157 ( .A(n4891), .B(n4888), .Y(n4539) );
NAND2X1TS U8158 ( .A(n8006), .B(n8007), .Y(n4542) );
NAND2X1TS U8159 ( .A(n8008), .B(n8006), .Y(n4541) );
NAND2X1TS U8160 ( .A(n4549), .B(n4548), .Y(n4551) );
XNOR2X1TS U8161 ( .A(n6437), .B(n460), .Y(n4665) );
XNOR2X1TS U8162 ( .A(n6411), .B(n460), .Y(n4618) );
OAI22X1TS U8163 ( .A0(n4665), .A1(n6162), .B0(n4618), .B1(n592), .Y(n4690)
);
XNOR2X1TS U8164 ( .A(Data_B_i[19]), .B(n340), .Y(n4567) );
XNOR2X1TS U8165 ( .A(n6038), .B(Data_A_i[21]), .Y(n4596) );
OAI22X1TS U8166 ( .A0(n1289), .A1(n4567), .B0(n571), .B1(n4596), .Y(n4613)
);
XNOR2X1TS U8167 ( .A(Data_B_i[23]), .B(Data_A_i[16]), .Y(n4558) );
XNOR2X1TS U8168 ( .A(Data_B_i[23]), .B(Data_A_i[17]), .Y(n4610) );
OAI22X1TS U8169 ( .A0(n6416), .A1(n4558), .B0(n563), .B1(n4610), .Y(n4612)
);
XNOR2X1TS U8170 ( .A(n254), .B(Data_A_i[25]), .Y(n4599) );
OAI22X1TS U8171 ( .A0(n6492), .A1(n522), .B0(n598), .B1(n4553), .Y(n4597) );
ADDHX1TS U8172 ( .A(n4555), .B(n4554), .CO(n4640), .S(n4637) );
OAI22X1TS U8173 ( .A0(n6416), .A1(n4559), .B0(n6415), .B1(n4558), .Y(n4563)
);
XNOR2X1TS U8174 ( .A(Data_B_i[21]), .B(Data_A_i[18]), .Y(n4572) );
OAI22X1TS U8175 ( .A0(n6304), .A1(n4566), .B0(n604), .B1(n4572), .Y(n4634)
);
XNOR2X1TS U8176 ( .A(n4967), .B(n342), .Y(n4573) );
XNOR2X1TS U8177 ( .A(n523), .B(n4570), .Y(n4571) );
XNOR2X1TS U8178 ( .A(Data_B_i[25]), .B(Data_A_i[15]), .Y(n4601) );
OAI22X1TS U8179 ( .A0(n6492), .A1(n4571), .B0(n597), .B1(n4601), .Y(n4607)
);
OAI22X1TS U8180 ( .A0(n6304), .A1(n4572), .B0(n605), .B1(n4608), .Y(n4606)
);
XNOR2X1TS U8181 ( .A(n4967), .B(Data_A_i[23]), .Y(n4609) );
XNOR2X1TS U8182 ( .A(n6050), .B(n451), .Y(n4660) );
XNOR2X1TS U8183 ( .A(n6053), .B(n4502), .Y(n4586) );
OAI22X1TS U8184 ( .A0(n4660), .A1(n479), .B0(n4586), .B1(n6494), .Y(n4593)
);
NOR2X1TS U8185 ( .A(n1218), .B(n4578), .Y(n4579) );
INVX2TS U8186 ( .A(n4582), .Y(n6547) );
XNOR2X1TS U8187 ( .A(n4582), .B(n630), .Y(n4584) );
OAI22X1TS U8188 ( .A0(n6549), .A1(n4584), .B0(n4661), .B1(n6548), .Y(n4614)
);
NOR2BX1TS U8189 ( .AN(n631), .B(n469), .Y(n4627) );
XNOR2X1TS U8190 ( .A(n6057), .B(n3775), .Y(n4628) );
OAI22X1TS U8191 ( .A0(n4628), .A1(n473), .B0(n4587), .B1(n587), .Y(n4625) );
INVX2TS U8192 ( .A(n6659), .Y(n4799) );
XNOR2X1TS U8193 ( .A(n6038), .B(n342), .Y(n4807) );
OAI22X1TS U8194 ( .A0(n1289), .A1(n4596), .B0(n571), .B1(n4807), .Y(n4828)
);
ADDHX1TS U8195 ( .A(n4598), .B(n4597), .CO(n4827), .S(n4611) );
XNOR2X1TS U8196 ( .A(n254), .B(Data_A_i[26]), .Y(n4822) );
XNOR2X4TS U8197 ( .A(Data_B_i[25]), .B(Data_B_i[26]), .Y(n4812) );
NOR2BX1TS U8198 ( .AN(n4570), .B(n533), .Y(n4809) );
XNOR2X1TS U8199 ( .A(n330), .B(Data_A_i[16]), .Y(n4811) );
OAI22X1TS U8200 ( .A0(n357), .A1(n4601), .B0(n597), .B1(n4811), .Y(n4808) );
XNOR2X1TS U8201 ( .A(n239), .B(Data_A_i[20]), .Y(n4825) );
OAI22X1TS U8202 ( .A0(n356), .A1(n4608), .B0(n604), .B1(n4825), .Y(n4820) );
XNOR2X1TS U8203 ( .A(n4967), .B(Data_A_i[24]), .Y(n4824) );
XNOR2X1TS U8204 ( .A(n320), .B(n338), .Y(n4814) );
OAI22X1TS U8205 ( .A0(n6300), .A1(n4610), .B0(n6415), .B1(n4814), .Y(n4818)
);
ADDFX1TS U8206 ( .A(n4613), .B(n4612), .CI(n4611), .CO(n4815), .S(n4590) );
ADDHX1TS U8207 ( .A(n4615), .B(n4614), .CO(n4806), .S(n4592) );
XNOR2X1TS U8208 ( .A(n6370), .B(n383), .Y(n4630) );
XNOR2X1TS U8209 ( .A(n6411), .B(n382), .Y(n4832) );
OAI22X1TS U8210 ( .A0(n4630), .A1(n590), .B0(n4832), .B1(n488), .Y(n4805) );
XNOR2X1TS U8211 ( .A(n6186), .B(n400), .Y(n4629) );
XNOR2X1TS U8212 ( .A(n6314), .B(n400), .Y(n4831) );
OAI22X1TS U8213 ( .A0(n4629), .A1(n587), .B0(n4831), .B1(n473), .Y(n4804) );
XNOR2X1TS U8214 ( .A(n6314), .B(n383), .Y(n4631) );
OAI22X1TS U8215 ( .A0(n4620), .A1(n590), .B0(n4631), .B1(n487), .Y(n4695) );
ADDFHX2TS U8216 ( .A(n4623), .B(n4622), .CI(n4621), .CO(n6652), .S(n6651) );
OAI22X1TS U8217 ( .A0(n4629), .A1(n472), .B0(n4628), .B1(n586), .Y(n4643) );
OAI22X1TS U8218 ( .A0(n4631), .A1(n589), .B0(n4630), .B1(n488), .Y(n4642) );
NOR2X1TS U8219 ( .A(n4645), .B(n4648), .Y(n4667) );
AOI21X1TS U8220 ( .A0(n4992), .A1(n4667), .B0(n4672), .Y(n4651) );
NAND2X1TS U8221 ( .A(n4649), .B(n4669), .Y(n4650) );
NAND2X1TS U8222 ( .A(n297), .B(n288), .Y(n4668) );
NAND2X1TS U8223 ( .A(n4656), .B(n4668), .Y(n4657) );
XOR2X4TS U8224 ( .A(n4658), .B(n4657), .Y(n6517) );
XNOR2X1TS U8225 ( .A(n6517), .B(n397), .Y(n4679) );
XNOR2X1TS U8226 ( .A(n6057), .B(n451), .Y(n4830) );
OAI22X1TS U8227 ( .A0(n4830), .A1(n479), .B0(n4660), .B1(n6494), .Y(n4858)
);
NOR2X1TS U8228 ( .A(Data_B_i[11]), .B(Data_B_i[25]), .Y(n4662) );
AOI21X1TS U8229 ( .A0(n4992), .A1(n4675), .B0(n4674), .Y(n4678) );
NAND2X1TS U8230 ( .A(n4676), .B(n4986), .Y(n4677) );
XOR2X2TS U8231 ( .A(n4678), .B(n4677), .Y(n6550) );
XNOR2X1TS U8232 ( .A(n6550), .B(n397), .Y(n4844) );
OAI22X1TS U8233 ( .A0(n4679), .A1(n399), .B0(n4844), .B1(n449), .Y(n4838) );
ADDFHX2TS U8234 ( .A(n4683), .B(n4682), .CI(n4681), .CO(n4715), .S(n4707) );
INVX2TS U8235 ( .A(n4687), .Y(n4713) );
OAI22X1TS U8236 ( .A0(n4692), .A1(n399), .B0(n4691), .B1(n450), .Y(n4718) );
ADDFHX1TS U8237 ( .A(n4697), .B(n4696), .CI(n4695), .CO(n4700), .S(n4716) );
OAI21X1TS U8238 ( .A0(n4740), .A1(n4737), .B0(n4739), .Y(n4722) );
OAI2BB1X2TS U8239 ( .A0N(n4737), .A1N(n4740), .B0(n4722), .Y(n4729) );
ADDFHX2TS U8240 ( .A(n4736), .B(n4735), .CI(n4734), .CO(n4743), .S(n4745) );
XOR2X4TS U8241 ( .A(n4739), .B(n4738), .Y(n4741) );
XNOR2X4TS U8242 ( .A(n4741), .B(n4740), .Y(n4742) );
NOR2X4TS U8243 ( .A(n4751), .B(n4750), .Y(n4895) );
ADDFHX2TS U8244 ( .A(n4744), .B(n4743), .CI(n4742), .CO(n4750), .S(n4749) );
NAND2X2TS U8245 ( .A(n4751), .B(n4750), .Y(n4896) );
INVX2TS U8246 ( .A(n4920), .Y(n4901) );
INVX2TS U8247 ( .A(Data_A_i[10]), .Y(n4762) );
NOR2X1TS U8248 ( .A(n621), .B(n4762), .Y(n4794) );
OAI22X1TS U8249 ( .A0(n4764), .A1(n4763), .B0(n574), .B1(n1631), .Y(n4777)
);
XNOR2X1TS U8250 ( .A(Data_B_i[13]), .B(Data_A_i[12]), .Y(n4775) );
OAI22X1TS U8251 ( .A0(n244), .A1(n4765), .B0(n1021), .B1(n4775), .Y(n4776)
);
CMPR32X2TS U8252 ( .A(n4768), .B(n4767), .C(n4766), .CO(n4769), .S(n4756) );
INVX2TS U8253 ( .A(Data_A_i[11]), .Y(n4774) );
NOR2X1TS U8254 ( .A(n620), .B(n4774), .Y(n4793) );
XNOR2X1TS U8255 ( .A(Data_B_i[13]), .B(Data_A_i[13]), .Y(n4791) );
NAND2X1TS U8256 ( .A(n4901), .B(n4870), .Y(n4784) );
AOI21X1TS U8257 ( .A0(n1705), .A1(n4782), .B0(n4781), .Y(n4919) );
NAND2X1TS U8258 ( .A(n6490), .B(n6484), .Y(n4924) );
NAND2X1TS U8259 ( .A(n6524), .B(n6529), .Y(n4909) );
AOI21X1TS U8260 ( .A0(n4903), .A1(n4870), .B0(n4874), .Y(n4783) );
OAI21X1TS U8261 ( .A0(n4921), .A1(n4784), .B0(n4783), .Y(n4785) );
INVX2TS U8262 ( .A(Data_A_i[12]), .Y(n4790) );
NOR2X1TS U8263 ( .A(n621), .B(n4790), .Y(n6592) );
OAI22X1TS U8264 ( .A0(n4279), .A1(n4791), .B0(n4881), .B1(n621), .Y(n4883)
);
CMPR32X2TS U8265 ( .A(n4794), .B(n4793), .C(n4792), .CO(n4882), .S(n4788) );
NAND2X1TS U8266 ( .A(n6546), .B(n6576), .Y(n4871) );
NAND2X1TS U8267 ( .A(n4873), .B(n4871), .Y(n4795) );
ADDFHX1TS U8268 ( .A(n4806), .B(n4805), .CI(n4804), .CO(n5011), .S(n4860) );
XNOR2X1TS U8269 ( .A(n6038), .B(n294), .Y(n4957) );
OAI22X1TS U8270 ( .A0(n6086), .A1(n4807), .B0(n571), .B1(n4957), .Y(n4975)
);
XNOR2X1TS U8271 ( .A(n514), .B(n293), .Y(n4972) );
OAI22X1TS U8272 ( .A0(n6300), .A1(n4814), .B0(n6415), .B1(n4972), .Y(n4958)
);
OAI22X1TS U8273 ( .A0(n4822), .A1(n334), .B0(n5042), .B1(n4821), .Y(n4963)
);
XNOR2X1TS U8274 ( .A(n4967), .B(n297), .Y(n4968) );
XNOR2X1TS U8275 ( .A(n238), .B(Data_A_i[21]), .Y(n4971) );
OAI22X1TS U8276 ( .A0(n356), .A1(n4825), .B0(n605), .B1(n4971), .Y(n4961) );
XNOR2X1TS U8277 ( .A(n6186), .B(n451), .Y(n4951) );
OAI22X1TS U8278 ( .A0(n4951), .A1(n479), .B0(n6494), .B1(n4830), .Y(n4954)
);
XNOR2X1TS U8279 ( .A(n6437), .B(n383), .Y(n5004) );
OAI22X1TS U8280 ( .A0(n5004), .A1(n488), .B0(n4832), .B1(n590), .Y(n4952) );
NOR2X1TS U8281 ( .A(n4984), .B(n4983), .Y(n4842) );
OAI21X1TS U8282 ( .A0(n4989), .A1(n4983), .B0(n4986), .Y(n4841) );
XNOR2X1TS U8283 ( .A(n6572), .B(n397), .Y(n4993) );
OAI22X1TS U8284 ( .A0(n4844), .A1(n3730), .B0(n4993), .B1(n449), .Y(n5003)
);
XNOR2X1TS U8285 ( .A(n6517), .B(n6052), .Y(n4994) );
OAI22X1TS U8286 ( .A0(n4845), .A1(n593), .B0(n4994), .B1(n6162), .Y(n5002)
);
OAI22X1TS U8287 ( .A0(n4982), .A1(n469), .B0(n4846), .B1(n6549), .Y(n5007)
);
XOR2X1TS U8288 ( .A(Data_B_i[25]), .B(Data_B_i[26]), .Y(n4848) );
OAI22X1TS U8289 ( .A0(n6595), .A1(n434), .B0(n6594), .B1(n4853), .Y(n4949)
);
XNOR2X1TS U8290 ( .A(n6557), .B(n631), .Y(n4854) );
OAI22X1TS U8291 ( .A0(n6595), .A1(n4854), .B0(n4981), .B1(n6594), .Y(n4948)
);
NAND2X1TS U8292 ( .A(n4856), .B(n4855), .Y(n4857) );
NAND2X1TS U8293 ( .A(n4870), .B(n4873), .Y(n4876) );
OR2X2TS U8294 ( .A(n4876), .B(n4920), .Y(n4878) );
AOI21X1TS U8295 ( .A0(n4874), .A1(n4873), .B0(n4872), .Y(n4875) );
OA21XLTS U8296 ( .A0(n4876), .A1(n4919), .B0(n4875), .Y(n4877) );
OAI21X1TS U8297 ( .A0(n4921), .A1(n4878), .B0(n4877), .Y(n4879) );
NOR2X1TS U8298 ( .A(n621), .B(n4985), .Y(n6591) );
CMPR32X2TS U8299 ( .A(n4884), .B(n4883), .C(n4882), .CO(n6597), .S(n6576) );
NAND2X2TS U8300 ( .A(n4891), .B(n9428), .Y(n4892) );
NAND2X1TS U8301 ( .A(n4897), .B(n4896), .Y(n4898) );
INVX2TS U8302 ( .A(n4900), .Y(n4925) );
NAND2X1TS U8303 ( .A(n4901), .B(n4925), .Y(n4905) );
AOI21X1TS U8304 ( .A0(n4903), .A1(n4925), .B0(n4902), .Y(n4904) );
OAI21X1TS U8305 ( .A0(n4921), .A1(n4905), .B0(n4904), .Y(n4906) );
NAND2X1TS U8306 ( .A(n4910), .B(n4909), .Y(n4911) );
NAND2X1TS U8307 ( .A(n4915), .B(n4914), .Y(n4916) );
NOR2X1TS U8308 ( .A(n4918), .B(n4920), .Y(n4923) );
NAND2X1TS U8309 ( .A(n4925), .B(n4924), .Y(n4926) );
XOR2X1TS U8310 ( .A(n4927), .B(n4926), .Y(n4928) );
NOR2X2TS U8311 ( .A(n4929), .B(n4928), .Y(n8484) );
NOR2X2TS U8312 ( .A(n7244), .B(n8484), .Y(n4933) );
OAI21X2TS U8313 ( .A0(n7244), .A1(n8485), .B0(n7245), .Y(n4932) );
INVX2TS U8314 ( .A(n7372), .Y(n4938) );
ADDHX1TS U8315 ( .A(n4949), .B(n4948), .CO(n5074), .S(n5006) );
XNOR2X1TS U8316 ( .A(n6411), .B(n400), .Y(n5065) );
XNOR2X1TS U8317 ( .A(n6314), .B(n4502), .Y(n5031) );
OAI22X1TS U8318 ( .A0(n4951), .A1(n588), .B0(n5031), .B1(n478), .Y(n5072) );
ADDFX1TS U8319 ( .A(n4954), .B(n4953), .CI(n4952), .CO(n5076), .S(n4955) );
XNOR2X1TS U8320 ( .A(n6038), .B(Data_A_i[24]), .Y(n5051) );
OAI22X1TS U8321 ( .A0(n1289), .A1(n4957), .B0(n571), .B1(n5051), .Y(n5055)
);
ADDFHX2TS U8322 ( .A(n4966), .B(n4965), .CI(n4964), .CO(n5027), .S(n5008) );
XNOR2X1TS U8323 ( .A(Data_B_i[25]), .B(Data_A_i[18]), .Y(n5052) );
INVX2TS U8324 ( .A(Data_A_i[16]), .Y(n5039) );
INVX2TS U8325 ( .A(n6073), .Y(n6029) );
XNOR2X1TS U8326 ( .A(n238), .B(Data_A_i[22]), .Y(n5038) );
OAI22X1TS U8327 ( .A0(n356), .A1(n4971), .B0(n605), .B1(n5038), .Y(n5044) );
XNOR2X1TS U8328 ( .A(Data_B_i[23]), .B(n340), .Y(n5050) );
OAI22X1TS U8329 ( .A0(n6416), .A1(n4972), .B0(n563), .B1(n5050), .Y(n5043)
);
ADDFHX2TS U8330 ( .A(n4975), .B(n4974), .CI(n4973), .CO(n5045), .S(n5010) );
INVX2TS U8331 ( .A(n4976), .Y(n5036) );
NAND2X1TS U8332 ( .A(n4977), .B(n620), .Y(n4978) );
NOR2BX1TS U8333 ( .AN(n4980), .B(n4979), .Y(n5029) );
XNOR2X1TS U8334 ( .A(n6053), .B(n6557), .Y(n5070) );
XNOR2X1TS U8335 ( .A(n6057), .B(n4582), .Y(n5030) );
OAI22X1TS U8336 ( .A0(n4993), .A1(n3730), .B0(n5071), .B1(n450), .Y(n5033)
);
XNOR2X1TS U8337 ( .A(n6550), .B(n460), .Y(n5067) );
OAI22X1TS U8338 ( .A0(n4994), .A1(n593), .B0(n5067), .B1(n6162), .Y(n5032)
);
ADDFHX2TS U8339 ( .A(n4997), .B(n4996), .CI(n4995), .CO(n5082), .S(n5015) );
ADDFHX2TS U8340 ( .A(n5003), .B(n5002), .CI(n5001), .CO(n5064), .S(n4999) );
XNOR2X1TS U8341 ( .A(n6485), .B(n383), .Y(n5066) );
OAI22X1TS U8342 ( .A0(n5004), .A1(n590), .B0(n5066), .B1(n487), .Y(n5058) );
ADDFHX2TS U8343 ( .A(n5010), .B(n5009), .CI(n5008), .CO(n6666), .S(n6663) );
NAND2X1TS U8344 ( .A(n5024), .B(n5023), .Y(n7985) );
INVX2TS U8345 ( .A(n6669), .Y(n6216) );
XNOR2X1TS U8346 ( .A(n6186), .B(n452), .Y(n6121) );
OAI22X1TS U8347 ( .A0(n6121), .A1(n469), .B0(n5030), .B1(n578), .Y(n6118) );
OAI22X1TS U8348 ( .A0(n5031), .A1(n588), .B0(n6120), .B1(n479), .Y(n6117) );
ADDFHX1TS U8349 ( .A(n5034), .B(n5033), .CI(n5032), .CO(n6214), .S(n5035) );
XNOR2X1TS U8350 ( .A(n238), .B(Data_A_i[23]), .Y(n6033) );
OAI22X1TS U8351 ( .A0(n356), .A1(n5038), .B0(n604), .B1(n6033), .Y(n6046) );
INVX2TS U8352 ( .A(Data_A_i[17]), .Y(n6032) );
OAI22X1TS U8353 ( .A0(n6520), .A1(n5039), .B0(n533), .B1(n6032), .Y(n6031)
);
ADDFHX1TS U8354 ( .A(n5044), .B(n5043), .CI(n5042), .CO(n6044), .S(n5046) );
ADDFHX2TS U8355 ( .A(n5047), .B(n5046), .CI(n5045), .CO(n6115), .S(n5026) );
XNOR2X1TS U8356 ( .A(n320), .B(n341), .Y(n6028) );
OAI22X1TS U8357 ( .A0(n6300), .A1(n5050), .B0(n563), .B1(n6028), .Y(n6043)
);
OAI22X1TS U8358 ( .A0(n1289), .A1(n5051), .B0(n571), .B1(n6039), .Y(n6042)
);
XNOR2X1TS U8359 ( .A(n330), .B(n293), .Y(n6034) );
OAI22X1TS U8360 ( .A0(n357), .A1(n5052), .B0(n597), .B1(n6034), .Y(n6041) );
INVX2TS U8361 ( .A(n6670), .Y(n6224) );
XNOR2X1TS U8362 ( .A(n6437), .B(n400), .Y(n6167) );
OAI22X1TS U8363 ( .A0(n6167), .A1(n472), .B0(n5065), .B1(n586), .Y(n6178) );
XNOR2X1TS U8364 ( .A(n6517), .B(n383), .Y(n6113) );
OAI22X1TS U8365 ( .A0(n5066), .A1(n589), .B0(n6113), .B1(n487), .Y(n6177) );
XNOR2X1TS U8366 ( .A(n6572), .B(n460), .Y(n6165) );
OAI22X1TS U8367 ( .A0(n5067), .A1(n592), .B0(n6165), .B1(n6162), .Y(n6176)
);
XNOR2X1TS U8368 ( .A(n6050), .B(n6557), .Y(n6055) );
OAI22X1TS U8369 ( .A0(n6055), .A1(n6594), .B0(n5070), .B1(n420), .Y(n6169)
);
INVX2TS U8370 ( .A(n397), .Y(n6123) );
OAI22X1TS U8371 ( .A0(n5071), .A1(n3730), .B0(n6123), .B1(n450), .Y(n6168)
);
ADDFHX2TS U8372 ( .A(n5083), .B(n5082), .CI(n5081), .CO(n5084), .S(n5019) );
XNOR2X4TS U8373 ( .A(n5088), .B(n5087), .Y(n5090) );
XNOR2X1TS U8374 ( .A(n5093), .B(n5094), .Y(n5104) );
NAND2X1TS U8375 ( .A(n5097), .B(n5096), .Y(n5098) );
INVX2TS U8376 ( .A(n11197), .Y(n7999) );
INVX2TS U8377 ( .A(EVEN1_Q_left[1]), .Y(n5110) );
NAND2X1TS U8378 ( .A(n5102), .B(n5101), .Y(n11193) );
NAND2X1TS U8379 ( .A(n5104), .B(n5103), .Y(n8002) );
NAND2X1TS U8380 ( .A(n5105), .B(n8002), .Y(n5115) );
XNOR2X1TS U8381 ( .A(n5110), .B(n11193), .Y(n5111) );
NAND2X1TS U8382 ( .A(n5112), .B(n5111), .Y(n7379) );
AOI21X1TS U8383 ( .A0(n7380), .A1(n5114), .B0(n5113), .Y(n8004) );
INVX2TS U8384 ( .A(n5116), .Y(n5310) );
XNOR2X1TS U8385 ( .A(n5485), .B(Data_A_i[48]), .Y(n5122) );
XNOR2X1TS U8386 ( .A(n5485), .B(Data_A_i[49]), .Y(n5221) );
OAI22X1TS U8387 ( .A0(n249), .A1(n5122), .B0(n601), .B1(n5221), .Y(n5298) );
INVX2TS U8388 ( .A(Data_A_i[43]), .Y(n5118) );
INVX2TS U8389 ( .A(n646), .Y(n5119) );
OAI22X1TS U8390 ( .A0(n983), .A1(n5118), .B0(n6725), .B1(n5119), .Y(n5138)
);
XNOR2X1TS U8391 ( .A(n264), .B(Data_A_i[53]), .Y(n5121) );
OAI22X1TS U8392 ( .A0(n5117), .A1(n5121), .B0(n323), .B1(n1436), .Y(n5137)
);
INVX2TS U8393 ( .A(n685), .Y(n5126) );
OAI22X2TS U8394 ( .A0(n983), .A1(n5126), .B0(n6725), .B1(n5118), .Y(n5217)
);
INVX2TS U8395 ( .A(n5217), .Y(n5255) );
OAI22X1TS U8396 ( .A0(n6760), .A1(n5119), .B0(n686), .B1(n722), .Y(n5228) );
XNOR2X1TS U8397 ( .A(n281), .B(Data_A_i[50]), .Y(n5136) );
XNOR2X1TS U8398 ( .A(n5223), .B(Data_A_i[51]), .Y(n5213) );
XNOR2X1TS U8399 ( .A(n526), .B(n313), .Y(n5123) );
XNOR2X1TS U8400 ( .A(n526), .B(n343), .Y(n5214) );
OAI22X1TS U8401 ( .A0(n6729), .A1(n5123), .B0(n6728), .B1(n5214), .Y(n5226)
);
XNOR2X1TS U8402 ( .A(n409), .B(Data_A_i[44]), .Y(n5125) );
XNOR2X1TS U8403 ( .A(n526), .B(n248), .Y(n5124) );
XNOR2X1TS U8404 ( .A(Data_B_i[50]), .B(Data_A_i[47]), .Y(n5141) );
OAI22X1TS U8405 ( .A0(n250), .A1(n5141), .B0(n600), .B1(n5122), .Y(n5135) );
XNOR2X1TS U8406 ( .A(n255), .B(n315), .Y(n5127) );
XNOR2X1TS U8407 ( .A(Data_B_i[46]), .B(Data_A_i[52]), .Y(n5132) );
OAI22X1TS U8408 ( .A0(n5579), .A1(n5127), .B0(n555), .B1(n5132), .Y(n5134)
);
OAI22X1TS U8409 ( .A0(n6729), .A1(n5124), .B0(n558), .B1(n5123), .Y(n5133)
);
XNOR2X1TS U8410 ( .A(n409), .B(Data_A_i[43]), .Y(n5262) );
OAI22X1TS U8411 ( .A0(n983), .A1(n1096), .B0(n686), .B1(n5126), .Y(n5264) );
XNOR2X1TS U8412 ( .A(Data_B_i[50]), .B(Data_A_i[45]), .Y(n5486) );
XNOR2X1TS U8413 ( .A(Data_B_i[50]), .B(Data_A_i[46]), .Y(n5142) );
XNOR2X1TS U8414 ( .A(n247), .B(Data_A_i[50]), .Y(n5260) );
OAI22X1TS U8415 ( .A0(n351), .A1(n5260), .B0(n2200), .B1(n5127), .Y(n5482)
);
XNOR2X1TS U8416 ( .A(Data_A_i[53]), .B(Data_B_i[42]), .Y(n5261) );
OAI22X1TS U8417 ( .A0(n332), .A1(n5261), .B0(n1338), .B1(n5568), .Y(n5494)
);
XNOR2X1TS U8418 ( .A(Data_B_i[44]), .B(Data_A_i[51]), .Y(n5487) );
XNOR2X1TS U8419 ( .A(n5223), .B(Data_A_i[47]), .Y(n5488) );
XNOR2X1TS U8420 ( .A(n281), .B(Data_A_i[48]), .Y(n5140) );
OAI22X1TS U8421 ( .A0(n634), .A1(n5488), .B0(n5581), .B1(n5140), .Y(n5492)
);
AO22X4TS U8422 ( .A0(n5131), .A1(n5484), .B0(n5483), .B1(n5482), .Y(n5266)
);
XNOR2X1TS U8423 ( .A(Data_B_i[46]), .B(Data_A_i[53]), .Y(n5219) );
OAI22X2TS U8424 ( .A0(n350), .A1(n5132), .B0(n555), .B1(n5219), .Y(n5216) );
XNOR2X1TS U8425 ( .A(n5223), .B(Data_A_i[49]), .Y(n5139) );
OAI22X1TS U8426 ( .A0(n634), .A1(n5139), .B0(n1367), .B1(n5136), .Y(n5254)
);
OAI22X1TS U8427 ( .A0(n5583), .A1(n5140), .B0(n5581), .B1(n5139), .Y(n5259)
);
INVX2TS U8428 ( .A(n9558), .Y(n5309) );
NAND2X1TS U8429 ( .A(Data_B_i[53]), .B(Data_B_i[39]), .Y(n5143) );
NAND2X1TS U8430 ( .A(n5144), .B(n5143), .Y(n5192) );
XNOR2X1TS U8431 ( .A(n5192), .B(n622), .Y(n5145) );
XNOR2X1TS U8432 ( .A(n5637), .B(n402), .Y(n5280) );
NAND2X2TS U8433 ( .A(n5148), .B(n5147), .Y(n5198) );
NOR2X1TS U8434 ( .A(n6882), .B(n5151), .Y(n5152) );
XOR2X1TS U8435 ( .A(n5152), .B(n624), .Y(n5153) );
XNOR2X1TS U8436 ( .A(n5688), .B(n403), .Y(n5339) );
OAI22X1TS U8437 ( .A0(n5280), .A1(n423), .B0(n5339), .B1(n491), .Y(n5343) );
NOR2X1TS U8438 ( .A(n5154), .B(n5157), .Y(n5185) );
NOR2X1TS U8439 ( .A(n5187), .B(n5168), .Y(n5159) );
NAND2X1TS U8440 ( .A(n5185), .B(n5159), .Y(n5173) );
OAI21X1TS U8441 ( .A0(n5168), .A1(n5188), .B0(n5169), .Y(n5158) );
NOR2X1TS U8442 ( .A(n5173), .B(n5162), .Y(n5164) );
OAI21X1TS U8443 ( .A0(n5174), .A1(n5162), .B0(n5161), .Y(n5163) );
XNOR2X1TS U8444 ( .A(n6833), .B(n414), .Y(n5338) );
OAI22X1TS U8445 ( .A0(n5183), .A1(n583), .B0(n5338), .B1(n499), .Y(n5342) );
NAND2X1TS U8446 ( .A(n5170), .B(n5169), .Y(n5171) );
XNOR2X1TS U8447 ( .A(n6757), .B(n2269), .Y(n5191) );
AOI21X1TS U8448 ( .A0(n5186), .A1(n5176), .B0(n5175), .Y(n5181) );
NAND2X1TS U8449 ( .A(n5179), .B(n5178), .Y(n5180) );
XOR2X2TS U8450 ( .A(n5181), .B(n5180), .Y(n6827) );
XNOR2X1TS U8451 ( .A(n6827), .B(n2269), .Y(n5209) );
OAI22X1TS U8452 ( .A0(n5191), .A1(n580), .B0(n5209), .B1(n1316), .Y(n5341)
);
XNOR2X1TS U8453 ( .A(n6827), .B(n415), .Y(n5251) );
OAI22X1TS U8454 ( .A0(n5251), .A1(n583), .B0(n5183), .B1(n499), .Y(n5330) );
NAND2X1TS U8455 ( .A(n5189), .B(n5188), .Y(n5190) );
XNOR2X1TS U8456 ( .A(n6717), .B(n446), .Y(n5319) );
OAI22X1TS U8457 ( .A0(n5319), .A1(n580), .B0(n5191), .B1(n5686), .Y(n5329)
);
NAND2X1TS U8458 ( .A(n5192), .B(n624), .Y(n5193) );
XOR2X1TS U8459 ( .A(n5193), .B(n260), .Y(n5194) );
XNOR2X1TS U8460 ( .A(n6833), .B(n428), .Y(n5317) );
XNOR2X1TS U8461 ( .A(n5627), .B(n402), .Y(n5279) );
XNOR2X1TS U8462 ( .A(n5948), .B(n448), .Y(n5282) );
XNOR2X1TS U8463 ( .A(n6717), .B(n447), .Y(n5236) );
OAI22X1TS U8464 ( .A0(n5282), .A1(n581), .B0(n5236), .B1(n484), .Y(n5333) );
NOR2X1TS U8465 ( .A(n5197), .B(n5194), .Y(n5212) );
XNOR2X1TS U8466 ( .A(n5640), .B(n6704), .Y(n5277) );
XNOR2X1TS U8467 ( .A(n5703), .B(n6704), .Y(n5235) );
OAI22X1TS U8468 ( .A0(n5277), .A1(n577), .B0(n5235), .B1(n494), .Y(n5210) );
XNOR2X1TS U8469 ( .A(n7732), .B(n446), .Y(n5366) );
OAI22X1TS U8470 ( .A0(n5209), .A1(n580), .B0(n5366), .B1(n1316), .Y(n5365)
);
XNOR2X1TS U8471 ( .A(n5223), .B(Data_A_i[52]), .Y(n5224) );
OAI22X1TS U8472 ( .A0(n5583), .A1(n5213), .B0(n5581), .B1(n5224), .Y(n5234)
);
XNOR2X1TS U8473 ( .A(n409), .B(Data_A_i[48]), .Y(n5218) );
OAI22X1TS U8474 ( .A0(n6729), .A1(n5214), .B0(n558), .B1(n5218), .Y(n5233)
);
ADDFHX2TS U8475 ( .A(n5217), .B(n5216), .CI(n5215), .CO(n5232), .S(n5304) );
XNOR2X1TS U8476 ( .A(n409), .B(Data_A_i[49]), .Y(n5238) );
INVX2TS U8477 ( .A(Data_A_i[46]), .Y(n5222) );
INVX2TS U8478 ( .A(Data_A_i[47]), .Y(n5239) );
OAI22X1TS U8479 ( .A0(n983), .A1(n5222), .B0(n6725), .B1(n5239), .Y(n5248)
);
XNOR2X1TS U8480 ( .A(n5485), .B(Data_A_i[50]), .Y(n5220) );
XNOR2X1TS U8481 ( .A(n5485), .B(Data_A_i[51]), .Y(n5237) );
OAI22X1TS U8482 ( .A0(n250), .A1(n5220), .B0(n600), .B1(n5237), .Y(n5247) );
OAI22X1TS U8483 ( .A0(n6760), .A1(n722), .B0(n686), .B1(n5222), .Y(n5246) );
XNOR2X1TS U8484 ( .A(n281), .B(Data_A_i[53]), .Y(n5243) );
OAI22X2TS U8485 ( .A0(n634), .A1(n5224), .B0(n1367), .B1(n5243), .Y(n5245)
);
XNOR2X1TS U8486 ( .A(n5948), .B(n426), .Y(n5367) );
OAI22X1TS U8487 ( .A0(n5367), .A1(n494), .B0(n5235), .B1(n577), .Y(n5362) );
XNOR2X1TS U8488 ( .A(n6757), .B(n448), .Y(n5371) );
OAI22X1TS U8489 ( .A0(n5236), .A1(n581), .B0(n5371), .B1(n484), .Y(n5361) );
XNOR2X1TS U8490 ( .A(n5485), .B(Data_A_i[52]), .Y(n5376) );
OAI22X1TS U8491 ( .A0(n250), .A1(n5237), .B0(n600), .B1(n5376), .Y(n5374) );
XNOR2X1TS U8492 ( .A(n526), .B(Data_A_i[50]), .Y(n5377) );
OAI22X1TS U8493 ( .A0(n6729), .A1(n5238), .B0(n6728), .B1(n5377), .Y(n5373)
);
INVX2TS U8494 ( .A(Data_A_i[48]), .Y(n5375) );
OAI22X1TS U8495 ( .A0(n983), .A1(n5239), .B0(n6725), .B1(n5375), .Y(n5433)
);
OAI22X1TS U8496 ( .A0(n634), .A1(n5243), .B0(n1367), .B1(n5378), .Y(n5381)
);
INVX2TS U8497 ( .A(n5250), .Y(n5357) );
OAI22X1TS U8498 ( .A0(n5316), .A1(n582), .B0(n5251), .B1(n498), .Y(n5862) );
ADDFHX1TS U8499 ( .A(n5255), .B(n5256), .CI(n5257), .CO(n5268), .S(n5505) );
XNOR2X1TS U8500 ( .A(n247), .B(Data_A_i[49]), .Y(n5495) );
OAI22X1TS U8501 ( .A0(n350), .A1(n5495), .B0(n555), .B1(n5260), .Y(n5535) );
NOR2BX1TS U8502 ( .AN(n5497), .B(n6725), .Y(n5502) );
XNOR2X1TS U8503 ( .A(Data_A_i[52]), .B(Data_B_i[42]), .Y(n5496) );
XNOR2X1TS U8504 ( .A(n409), .B(n685), .Y(n5537) );
OAI22X1TS U8505 ( .A0(n5539), .A1(n5537), .B0(n558), .B1(n5262), .Y(n5500)
);
XNOR2X1TS U8506 ( .A(n5530), .B(n5145), .Y(n5528) );
NOR2BX1TS U8507 ( .AN(n628), .B(n5194), .Y(n5509) );
XNOR2X1TS U8508 ( .A(n5627), .B(n425), .Y(n5272) );
XNOR2X1TS U8509 ( .A(n5532), .B(n425), .Y(n5526) );
OAI22X1TS U8510 ( .A0(n5272), .A1(n494), .B0(n5526), .B1(n576), .Y(n5512) );
NAND2BX1TS U8511 ( .AN(n5269), .B(n5510), .Y(n5270) );
XNOR2X1TS U8512 ( .A(n5637), .B(n426), .Y(n5274) );
OAI22X1TS U8513 ( .A0(n5274), .A1(n493), .B0(n5272), .B1(n577), .Y(n5507) );
XNOR2X1TS U8514 ( .A(n5688), .B(n448), .Y(n5657) );
XNOR2X1TS U8515 ( .A(n5640), .B(n447), .Y(n5273) );
OAI22X1TS U8516 ( .A0(n5657), .A1(n581), .B0(n5273), .B1(n483), .Y(n5506) );
XNOR2X1TS U8517 ( .A(n5703), .B(n448), .Y(n5281) );
OAI22X1TS U8518 ( .A0(n5273), .A1(n6732), .B0(n5281), .B1(n483), .Y(n5285)
);
XNOR2X1TS U8519 ( .A(n5688), .B(n426), .Y(n5278) );
OAI22X1TS U8520 ( .A0(n5280), .A1(n491), .B0(n5279), .B1(n423), .Y(n5294) );
OAI22X1TS U8521 ( .A0(n5282), .A1(n484), .B0(n5281), .B1(n6732), .Y(n5293)
);
INVX2TS U8522 ( .A(n8197), .Y(n5872) );
INVX2TS U8523 ( .A(n9575), .Y(n5336) );
INVX2TS U8524 ( .A(n9574), .Y(n5334) );
INVX2TS U8525 ( .A(n9559), .Y(n5347) );
XNOR2X1TS U8526 ( .A(n5948), .B(n2269), .Y(n5320) );
XNOR2X1TS U8527 ( .A(n5703), .B(n2269), .Y(n5655) );
OAI22X1TS U8528 ( .A0(n5320), .A1(n5686), .B0(n5655), .B1(n580), .Y(n5649)
);
XNOR2X1TS U8529 ( .A(n6717), .B(n415), .Y(n5525) );
OAI22X1TS U8530 ( .A0(n5525), .A1(n582), .B0(n5316), .B1(n499), .Y(n5648) );
XNOR2X1TS U8531 ( .A(n6827), .B(n428), .Y(n5514) );
XNOR2X1TS U8532 ( .A(n7732), .B(n428), .Y(n5318) );
OAI22X1TS U8533 ( .A0(n5514), .A1(n585), .B0(n5318), .B1(n503), .Y(n5647) );
OAI22X1TS U8534 ( .A0(n5318), .A1(n584), .B0(n5317), .B1(n503), .Y(n5327) );
OAI22X1TS U8535 ( .A0(n5320), .A1(n580), .B0(n5319), .B1(n1316), .Y(n5326)
);
OAI22X1TS U8536 ( .A0(n5323), .A1(n491), .B0(n5322), .B1(n422), .Y(n5651) );
XNOR2X1TS U8537 ( .A(n6833), .B(n384), .Y(n5513) );
OAI22X1TS U8538 ( .A0(n5513), .A1(n387), .B0(n131), .B1(n444), .Y(n5650) );
CMPR32X2TS U8539 ( .A(n5327), .B(n5326), .C(n5325), .CO(n5350), .S(n5878) );
ADDFHX2TS U8540 ( .A(n5336), .B(n5335), .CI(n5334), .CO(n5390), .S(n5346) );
OAI22X1TS U8541 ( .A0(n5338), .A1(n583), .B0(n499), .B1(n5382), .Y(n5386) );
XNOR2X1TS U8542 ( .A(n5640), .B(n402), .Y(n5384) );
OAI22X1TS U8543 ( .A0(n5339), .A1(n423), .B0(n5384), .B1(n490), .Y(n5385) );
ADDFHX2TS U8544 ( .A(n9558), .B(n5348), .CI(n5347), .CO(n5857), .S(n5895) );
INVX2TS U8545 ( .A(n5360), .Y(n5443) );
XNOR2X1TS U8546 ( .A(n6833), .B(n446), .Y(n5428) );
OAI22X1TS U8547 ( .A0(n5366), .A1(n580), .B0(n5428), .B1(n5686), .Y(n5440)
);
XNOR2X1TS U8548 ( .A(n6717), .B(n426), .Y(n5411) );
OAI22X1TS U8549 ( .A0(n5367), .A1(n577), .B0(n5411), .B1(n493), .Y(n5439) );
XNOR2X1TS U8550 ( .A(n6827), .B(n447), .Y(n5416) );
OAI22X1TS U8551 ( .A0(n5371), .A1(n581), .B0(n5416), .B1(n483), .Y(n5415) );
CMPR32X2TS U8552 ( .A(n5374), .B(n5373), .C(n5372), .CO(n5419), .S(n5370) );
INVX2TS U8553 ( .A(Data_A_i[49]), .Y(n5431) );
OAI22X1TS U8554 ( .A0(n6760), .A1(n5375), .B0(n686), .B1(n5431), .Y(n5437)
);
XNOR2X1TS U8555 ( .A(n5485), .B(Data_A_i[53]), .Y(n5429) );
OAI22X1TS U8556 ( .A0(n249), .A1(n5376), .B0(n601), .B1(n5429), .Y(n5436) );
XNOR2X1TS U8557 ( .A(n526), .B(Data_A_i[51]), .Y(n5430) );
OAI22X1TS U8558 ( .A0(n5539), .A1(n5377), .B0(n558), .B1(n5430), .Y(n5434)
);
AO21X2TS U8559 ( .A0(n634), .A1(n1367), .B0(n5378), .Y(n5432) );
INVX2TS U8560 ( .A(n9578), .Y(n5413) );
NOR2X1TS U8561 ( .A(n5383), .B(n363), .Y(n5421) );
XNOR2X1TS U8562 ( .A(n5703), .B(n402), .Y(n5410) );
OAI22X1TS U8563 ( .A0(n5384), .A1(n7780), .B0(n5410), .B1(n490), .Y(n5420)
);
CMPR32X2TS U8564 ( .A(n5387), .B(n5386), .C(n5385), .CO(n5424), .S(n5356) );
INVX2TS U8565 ( .A(n5388), .Y(n5423) );
ADDFHX2TS U8566 ( .A(n5391), .B(n5390), .CI(n5389), .CO(n5405), .S(n5397) );
NOR2X2TS U8567 ( .A(n5929), .B(n5930), .Y(n6012) );
XNOR2X1TS U8568 ( .A(n5948), .B(n403), .Y(n5465) );
OAI22X1TS U8569 ( .A0(n5465), .A1(n491), .B0(n5410), .B1(n423), .Y(n5458) );
XNOR2X1TS U8570 ( .A(n6757), .B(n6704), .Y(n5469) );
OAI22X1TS U8571 ( .A0(n5411), .A1(n577), .B0(n5469), .B1(n493), .Y(n5457) );
XNOR2X1TS U8572 ( .A(n7732), .B(n448), .Y(n5456) );
OAI22X1TS U8573 ( .A0(n5416), .A1(n581), .B0(n5456), .B1(n483), .Y(n5461) );
INVX2TS U8574 ( .A(n9589), .Y(n5460) );
CMPR32X2TS U8575 ( .A(n5422), .B(n5421), .C(n5420), .CO(n5459), .S(n5425) );
OAI22X1TS U8576 ( .A0(n249), .A1(n5429), .B0(n600), .B1(n5474), .Y(n5477) );
XNOR2X1TS U8577 ( .A(n409), .B(Data_A_i[52]), .Y(n5473) );
OAI22X1TS U8578 ( .A0(n5539), .A1(n5430), .B0(n558), .B1(n5473), .Y(n5476)
);
INVX2TS U8579 ( .A(Data_A_i[50]), .Y(n5472) );
OAI22X1TS U8580 ( .A0(n983), .A1(n5431), .B0(n6725), .B1(n5472), .Y(n5968)
);
ADDFHX2TS U8581 ( .A(n5437), .B(n5436), .CI(n5435), .CO(n5453), .S(n5418) );
ADDFHX2TS U8582 ( .A(n5443), .B(n5442), .CI(n5441), .CO(n5447), .S(n5401) );
INVX1TS U8583 ( .A(n6694), .Y(n5481) );
ADDFHX2TS U8584 ( .A(n5449), .B(n5448), .CI(n5447), .CO(n5940), .S(n5450) );
INVX2TS U8585 ( .A(n9610), .Y(n5946) );
XNOR2X1TS U8586 ( .A(n6833), .B(n448), .Y(n5973) );
OAI22X1TS U8587 ( .A0(n5456), .A1(n581), .B0(n5973), .B1(n484), .Y(n5945) );
XNOR2X1TS U8588 ( .A(n6717), .B(n402), .Y(n5961) );
OAI22X1TS U8589 ( .A0(n5465), .A1(n7780), .B0(n5961), .B1(n490), .Y(n5960)
);
XNOR2X1TS U8590 ( .A(n6827), .B(n426), .Y(n5951) );
OAI22X1TS U8591 ( .A0(n5469), .A1(n577), .B0(n5951), .B1(n493), .Y(n5957) );
CLKINVX1TS U8592 ( .A(n5703), .Y(n5471) );
INVX2TS U8593 ( .A(Data_A_i[51]), .Y(n5966) );
OAI22X1TS U8594 ( .A0(n6760), .A1(n5472), .B0(n686), .B1(n5966), .Y(n5972)
);
XNOR2X1TS U8595 ( .A(Data_B_i[52]), .B(Data_A_i[53]), .Y(n5965) );
OAI22X1TS U8596 ( .A0(n5539), .A1(n5473), .B0(n558), .B1(n5965), .Y(n5969)
);
AO21X2TS U8597 ( .A0(n250), .A1(n600), .B0(n5474), .Y(n5967) );
INVX2TS U8598 ( .A(n9609), .Y(n5962) );
XNOR2X1TS U8599 ( .A(n5485), .B(n646), .Y(n5542) );
OAI22X1TS U8600 ( .A0(n5575), .A1(n5542), .B0(n600), .B1(n5486), .Y(n5545)
);
XNOR2X1TS U8601 ( .A(n264), .B(Data_A_i[50]), .Y(n5540) );
OAI22X1TS U8602 ( .A0(n5117), .A1(n5540), .B0(n323), .B1(n5487), .Y(n5548)
);
XNOR2X1TS U8603 ( .A(Data_B_i[48]), .B(Data_A_i[46]), .Y(n5536) );
OAI22X1TS U8604 ( .A0(n5583), .A1(n5536), .B0(n1367), .B1(n5488), .Y(n5546)
);
NAND2X1TS U8605 ( .A(n5545), .B(n5546), .Y(n5489) );
XNOR2X1TS U8606 ( .A(n255), .B(Data_A_i[48]), .Y(n5541) );
OAI22X1TS U8607 ( .A0(n350), .A1(n5541), .B0(n2200), .B1(n5495), .Y(n5567)
);
XNOR2X1TS U8608 ( .A(n476), .B(Data_A_i[51]), .Y(n5569) );
ADDFHX2TS U8609 ( .A(n5505), .B(n5504), .CI(n5503), .CO(n5522), .S(n5515) );
XNOR2X1TS U8610 ( .A(n7732), .B(n384), .Y(n5554) );
OAI22X1TS U8611 ( .A0(n5554), .A1(n387), .B0(n5513), .B1(n445), .Y(n5519) );
XNOR2X1TS U8612 ( .A(n6757), .B(n429), .Y(n5556) );
OAI22X1TS U8613 ( .A0(n5556), .A1(n584), .B0(n5514), .B1(n504), .Y(n5518) );
INVX2TS U8614 ( .A(n7798), .Y(n5674) );
INVX2TS U8615 ( .A(n7968), .Y(n5877) );
XNOR2X1TS U8616 ( .A(n5948), .B(n415), .Y(n5643) );
OAI22X1TS U8617 ( .A0(n5643), .A1(n582), .B0(n5525), .B1(n498), .Y(n5598) );
OAI22X1TS U8618 ( .A0(n5526), .A1(n494), .B0(n5531), .B1(n576), .Y(n5560) );
INVX2TS U8619 ( .A(n403), .Y(n7778) );
OAI22X1TS U8620 ( .A0(n422), .A1(n5529), .B0(n5528), .B1(n491), .Y(n5653) );
NOR2BX1TS U8621 ( .AN(n628), .B(n491), .Y(n5553) );
XNOR2X1TS U8622 ( .A(n5627), .B(n448), .Y(n5638) );
XNOR2X1TS U8623 ( .A(n5532), .B(n448), .Y(n5621) );
OAI22X1TS U8624 ( .A0(n5638), .A1(n483), .B0(n5621), .B1(n6732), .Y(n5552)
);
XNOR2X1TS U8625 ( .A(Data_B_i[48]), .B(Data_A_i[45]), .Y(n5580) );
XNOR2X1TS U8626 ( .A(n526), .B(Data_A_i[41]), .Y(n5538) );
OAI22X1TS U8627 ( .A0(n5539), .A1(n5538), .B0(n6728), .B1(n5537), .Y(n5588)
);
XNOR2X1TS U8628 ( .A(n264), .B(n345), .Y(n5584) );
OAI22X1TS U8629 ( .A0(n538), .A1(n5584), .B0(n5585), .B1(n5540), .Y(n5587)
);
XNOR2X1TS U8630 ( .A(n255), .B(Data_A_i[47]), .Y(n5576) );
OAI22X1TS U8631 ( .A0(n350), .A1(n5576), .B0(n2200), .B1(n5541), .Y(n5608)
);
XNOR2X1TS U8632 ( .A(Data_B_i[50]), .B(Data_A_i[43]), .Y(n5572) );
OAI22X1TS U8633 ( .A0(n5575), .A1(n5572), .B0(n601), .B1(n5542), .Y(n5607)
);
XOR2X1TS U8634 ( .A(n5546), .B(n5545), .Y(n5547) );
XNOR2X1TS U8635 ( .A(n5948), .B(n428), .Y(n5704) );
XNOR2X1TS U8636 ( .A(n6717), .B(n428), .Y(n5557) );
XNOR2X1TS U8637 ( .A(n6757), .B(n384), .Y(n5682) );
XNOR2X1TS U8638 ( .A(n6827), .B(n385), .Y(n5555) );
OAI22X1TS U8639 ( .A0(n5682), .A1(n387), .B0(n5555), .B1(n445), .Y(n5699) );
OAI22X1TS U8640 ( .A0(n5555), .A1(n2033), .B0(n5554), .B1(n444), .Y(n5595)
);
XNOR2X1TS U8641 ( .A(n425), .B(n629), .Y(n5564) );
XNOR2X1TS U8642 ( .A(n5640), .B(n414), .Y(n5689) );
XNOR2X1TS U8643 ( .A(n5703), .B(n414), .Y(n5642) );
XNOR2X1TS U8644 ( .A(n5637), .B(n446), .Y(n5687) );
XNOR2X1TS U8645 ( .A(n5688), .B(n446), .Y(n5641) );
OAI22X1TS U8646 ( .A0(n5687), .A1(n580), .B0(n5641), .B1(n1316), .Y(n5603)
);
NOR2BX1TS U8647 ( .AN(n969), .B(n558), .Y(n5613) );
OAI22X1TS U8648 ( .A0(n249), .A1(n5574), .B0(n601), .B1(n5572), .Y(n5611) );
OAI22X2TS U8649 ( .A0(n5583), .A1(n5582), .B0(n1367), .B1(n5580), .Y(n5691)
);
OAI22X1TS U8650 ( .A0(n538), .A1(n5586), .B0(n323), .B1(n5584), .Y(n5690) );
ADDFHX2TS U8651 ( .A(n5598), .B(n5597), .CI(n5596), .CO(n5875), .S(n5645) );
INVX2TS U8652 ( .A(n5602), .Y(n5631) );
ADDHX1TS U8653 ( .A(n5610), .B(n5609), .CO(n5698), .S(n5694) );
INVX2TS U8654 ( .A(n6847), .Y(n5713) );
XNOR2X1TS U8655 ( .A(n5620), .B(n447), .Y(n5626) );
OAI22X1TS U8656 ( .A0(n5621), .A1(n483), .B0(n5626), .B1(n6732), .Y(n5710)
);
ADDHX1TS U8657 ( .A(n5623), .B(n5622), .CO(n5605), .S(n5709) );
NOR2BX1TS U8658 ( .AN(n629), .B(n493), .Y(n5741) );
XNOR2X1TS U8659 ( .A(n5627), .B(n2269), .Y(n5685) );
OAI22X1TS U8660 ( .A0(n5685), .A1(n1316), .B0(n5628), .B1(n579), .Y(n5739)
);
INVX2TS U8661 ( .A(n5629), .Y(n5711) );
XNOR2X1TS U8662 ( .A(n5637), .B(n448), .Y(n5658) );
OAI22X1TS U8663 ( .A0(n5658), .A1(n484), .B0(n5638), .B1(n6732), .Y(n5666)
);
XNOR2X1TS U8664 ( .A(n5640), .B(n446), .Y(n5656) );
OAI22X1TS U8665 ( .A0(n5641), .A1(n579), .B0(n5656), .B1(n1316), .Y(n5665)
);
OAI22X1TS U8666 ( .A0(n5643), .A1(n499), .B0(n5642), .B1(n583), .Y(n5664) );
ADDHX1TS U8667 ( .A(n5654), .B(n5653), .CO(n5663), .S(n5559) );
OAI22X1TS U8668 ( .A0(n5658), .A1(n581), .B0(n5657), .B1(n484), .Y(n5661) );
XNOR2X1TS U8669 ( .A(n6717), .B(n385), .Y(n5769) );
OAI22X1TS U8670 ( .A0(n5687), .A1(n5686), .B0(n5685), .B1(n580), .Y(n5744)
);
XNOR2X1TS U8671 ( .A(n5688), .B(n415), .Y(n5732) );
INVX2TS U8672 ( .A(n6801), .Y(n5742) );
XNOR2X1TS U8673 ( .A(n5703), .B(n428), .Y(n5726) );
OAI22X1TS U8674 ( .A0(n5704), .A1(n504), .B0(n5726), .B1(n585), .Y(n5760) );
ADDFHX2TS U8675 ( .A(n5707), .B(n5706), .CI(n5705), .CO(n6847), .S(n6802) );
INVX2TS U8676 ( .A(n6802), .Y(n5759) );
OAI22X1TS U8677 ( .A0(n5728), .A1(n584), .B0(n5726), .B1(n503), .Y(n5773) );
ADDHX1TS U8678 ( .A(n5730), .B(n5729), .CO(n5772), .S(n5752) );
OAI22X1TS U8679 ( .A0(n5734), .A1(n583), .B0(n5732), .B1(n498), .Y(n5771) );
INVX2TS U8680 ( .A(n5738), .Y(n5784) );
NOR2X2TS U8681 ( .A(n8018), .B(n8010), .Y(n5851) );
OAI22X1TS U8682 ( .A0(n5770), .A1(n2033), .B0(n5769), .B1(n444), .Y(n5800)
);
ADDFHX2TS U8683 ( .A(n5776), .B(n5775), .CI(n5774), .CO(n5798), .S(n5803) );
ADDFHX2TS U8684 ( .A(n5785), .B(n5784), .CI(n5783), .CO(n5778), .S(n5814) );
NOR2X2TS U8685 ( .A(n5842), .B(n5841), .Y(n5843) );
INVX2TS U8686 ( .A(n5843), .Y(n8025) );
ADDFHX2TS U8687 ( .A(n5794), .B(n5793), .CI(n5792), .CO(n5841), .S(n5840) );
OAI21X1TS U8688 ( .A0(n5825), .A1(n5827), .B0(n5828), .Y(n5810) );
NAND2X2TS U8689 ( .A(n8025), .B(n8047), .Y(n5845) );
XOR2X4TS U8690 ( .A(n5827), .B(n5826), .Y(n5829) );
XNOR2X4TS U8691 ( .A(n5829), .B(n5828), .Y(n5836) );
NOR2X2TS U8692 ( .A(n7207), .B(n7209), .Y(n5838) );
AOI21X4TS U8693 ( .A0(n7190), .A1(n5838), .B0(n5837), .Y(n8023) );
NAND2X2TS U8694 ( .A(n5840), .B(n5839), .Y(n8046) );
NAND2X1TS U8695 ( .A(n5842), .B(n5841), .Y(n8024) );
OA21X4TS U8696 ( .A0(n5843), .A1(n8046), .B0(n8024), .Y(n5844) );
OAI21X4TS U8697 ( .A0(n5845), .A1(n8023), .B0(n5844), .Y(n8009) );
OAI21X2TS U8698 ( .A0(n8010), .A1(n8019), .B0(n8011), .Y(n5850) );
ADDFHX2TS U8699 ( .A(n5868), .B(n5867), .CI(n5866), .CO(n5890), .S(n5889) );
ADDFHX2TS U8700 ( .A(n5886), .B(n5885), .CI(n5884), .CO(n5910), .S(n5906) );
NOR2X4TS U8701 ( .A(n8509), .B(n8503), .Y(n5928) );
ADDFHX2TS U8702 ( .A(n5907), .B(n5906), .CI(n5905), .CO(n5919), .S(n5915) );
XOR2X4TS U8703 ( .A(n5911), .B(n5912), .Y(n5913) );
ADDFHX2TS U8704 ( .A(n5920), .B(n5919), .CI(n5918), .CO(n5923), .S(n5922) );
OAI21X4TS U8705 ( .A0(n8085), .A1(n8076), .B0(n8077), .Y(n8505) );
NAND2X2TS U8706 ( .A(n5930), .B(n5929), .Y(n8519) );
OAI21X1TS U8707 ( .A0(n5935), .A1(n6693), .B0(n6745), .Y(n5936) );
INVX2TS U8708 ( .A(n5944), .Y(n6721) );
INVX2TS U8709 ( .A(n5950), .Y(n6723) );
XNOR2X1TS U8710 ( .A(n7732), .B(n6704), .Y(n6705) );
OAI22X1TS U8711 ( .A0(n5951), .A1(n577), .B0(n6705), .B1(n494), .Y(n6722) );
XNOR2X1TS U8712 ( .A(n6757), .B(n403), .Y(n6739) );
OAI22X1TS U8713 ( .A0(n5961), .A1(n423), .B0(n6739), .B1(n491), .Y(n6742) );
CMPR32X2TS U8714 ( .A(n5964), .B(n5963), .C(n5962), .CO(n6741), .S(n5955) );
OAI22X1TS U8715 ( .A0(n6729), .A1(n5965), .B0(n558), .B1(n6727), .Y(n6735)
);
INVX2TS U8716 ( .A(Data_A_i[52]), .Y(n6726) );
OAI22X1TS U8717 ( .A0(n6760), .A1(n5966), .B0(n686), .B1(n6726), .Y(n6763)
);
OAI22X1TS U8718 ( .A0(n5973), .A1(n581), .B0(n483), .B1(n6730), .Y(n6706) );
NAND2X1TS U8719 ( .A(n5977), .B(n5978), .Y(n6743) );
NAND2X1TS U8720 ( .A(n5979), .B(n6743), .Y(n5980) );
NAND2X1TS U8721 ( .A(n6022), .B(n8523), .Y(n5998) );
NAND2X1TS U8722 ( .A(n5983), .B(n5982), .Y(n8088) );
NAND2X1TS U8723 ( .A(n5985), .B(n5984), .Y(n8079) );
AOI21X1TS U8724 ( .A0(n8080), .A1(n8081), .B0(n5986), .Y(n8101) );
NAND2X1TS U8725 ( .A(n5988), .B(n5987), .Y(n8099) );
NAND2X1TS U8726 ( .A(n5990), .B(n5989), .Y(n8514) );
AOI21X1TS U8727 ( .A0(n8516), .A1(n8515), .B0(n5991), .Y(n6019) );
NAND2X1TS U8728 ( .A(n5993), .B(n5992), .Y(n8522) );
NAND2X1TS U8729 ( .A(n5995), .B(n5994), .Y(n6021) );
AOI21X1TS U8730 ( .A0(n6022), .A1(n6020), .B0(n5996), .Y(n5997) );
NAND2X1TS U8731 ( .A(n6000), .B(n5999), .Y(n6008) );
AOI21X1TS U8732 ( .A0(n6011), .A1(n6009), .B0(n6001), .Y(n6800) );
NAND2X1TS U8733 ( .A(n6003), .B(n6002), .Y(n6794) );
NAND2X1TS U8734 ( .A(n9640), .B(n6794), .Y(n6004) );
XNOR2X1TS U8735 ( .A(n9641), .B(n6004), .Y(n7905) );
NAND2X1TS U8736 ( .A(n6009), .B(n6008), .Y(n6010) );
XNOR2X1TS U8737 ( .A(n6011), .B(n6010), .Y(n6025) );
INVX2TS U8738 ( .A(n6012), .Y(n8520) );
NAND2X1TS U8739 ( .A(n6016), .B(n6015), .Y(n6017) );
XOR2X4TS U8740 ( .A(n6018), .B(n6017), .Y(n8202) );
AOI21X1TS U8741 ( .A0(n8524), .A1(n8523), .B0(n6020), .Y(n6024) );
NAND2X1TS U8742 ( .A(n6022), .B(n6021), .Y(n6023) );
XOR2X1TS U8743 ( .A(n6024), .B(n6023), .Y(n8201) );
XNOR2X1TS U8744 ( .A(n320), .B(n342), .Y(n6082) );
OAI22X1TS U8745 ( .A0(n6300), .A1(n6028), .B0(n6415), .B1(n6082), .Y(n6146)
);
ADDFHX2TS U8746 ( .A(n6031), .B(n6030), .CI(n6029), .CO(n6145), .S(n6045) );
INVX2TS U8747 ( .A(Data_A_i[18]), .Y(n6079) );
OAI22X1TS U8748 ( .A0(n243), .A1(n6032), .B0(n534), .B1(n6079), .Y(n6089) );
XNOR2X1TS U8749 ( .A(n239), .B(Data_A_i[24]), .Y(n6069) );
OAI22X1TS U8750 ( .A0(n356), .A1(n6033), .B0(n605), .B1(n6069), .Y(n6088) );
XNOR2X1TS U8751 ( .A(n330), .B(n340), .Y(n6070) );
OAI22X1TS U8752 ( .A0(n357), .A1(n6034), .B0(n598), .B1(n6070), .Y(n6087) );
ADDFHX2TS U8753 ( .A(n6037), .B(n6036), .CI(n6035), .CO(n6127), .S(n6114) );
XNOR2X1TS U8754 ( .A(n6038), .B(Data_A_i[26]), .Y(n6085) );
XNOR2X1TS U8755 ( .A(n6314), .B(n435), .Y(n6189) );
OAI22X1TS U8756 ( .A0(n6133), .A1(n419), .B0(n6189), .B1(n6594), .Y(n6192)
);
XNOR2X1TS U8757 ( .A(n6517), .B(n400), .Y(n6049) );
XNOR2X1TS U8758 ( .A(n6550), .B(n400), .Y(n6065) );
OAI22X1TS U8759 ( .A0(n6049), .A1(n586), .B0(n6065), .B1(n473), .Y(n6190) );
XNOR2X1TS U8760 ( .A(n6550), .B(n383), .Y(n6112) );
XNOR2X1TS U8761 ( .A(n6485), .B(n400), .Y(n6166) );
XNOR2X1TS U8762 ( .A(n6558), .B(n6052), .Y(n6163) );
OAI22X1TS U8763 ( .A0(n6163), .A1(n593), .B0(n6162), .B1(n459), .Y(n6060) );
XNOR2X1TS U8764 ( .A(n6057), .B(n6557), .Y(n6132) );
INVX2TS U8765 ( .A(n6056), .Y(n6205) );
NAND2X1TS U8766 ( .A(n6202), .B(n6205), .Y(n6064) );
XNOR2X1TS U8767 ( .A(n451), .B(n6485), .Y(n6098) );
OAI22X1TS U8768 ( .A0(n6137), .A1(n588), .B0(n6098), .B1(n479), .Y(n6185) );
XNOR2X1TS U8769 ( .A(n6411), .B(n4582), .Y(n6097) );
OAI22X1TS U8770 ( .A0(n6134), .A1(n578), .B0(n6097), .B1(n6548), .Y(n6066)
);
NAND2X1TS U8771 ( .A(n6203), .B(n6205), .Y(n6063) );
NAND2X1TS U8772 ( .A(n6203), .B(n6202), .Y(n6062) );
XNOR2X1TS U8773 ( .A(n6572), .B(n400), .Y(n6294) );
OAI22X1TS U8774 ( .A0(n6065), .A1(n586), .B0(n6294), .B1(n473), .Y(n6292) );
XNOR2X1TS U8775 ( .A(Data_B_i[21]), .B(Data_A_i[25]), .Y(n6080) );
OAI22X1TS U8776 ( .A0(n356), .A1(n6069), .B0(n605), .B1(n6080), .Y(n6093) );
XNOR2X1TS U8777 ( .A(n330), .B(Data_A_i[21]), .Y(n6077) );
OAI22X1TS U8778 ( .A0(n357), .A1(n6070), .B0(n597), .B1(n6077), .Y(n6094) );
XNOR2X1TS U8779 ( .A(n342), .B(n330), .Y(n6100) );
INVX2TS U8780 ( .A(Data_A_i[19]), .Y(n6078) );
OAI22X1TS U8781 ( .A0(n243), .A1(n6078), .B0(n534), .B1(n339), .Y(n6106) );
XNOR2X1TS U8782 ( .A(n320), .B(Data_A_i[23]), .Y(n6081) );
XNOR2X1TS U8783 ( .A(n320), .B(Data_A_i[24]), .Y(n6099) );
OAI22X1TS U8784 ( .A0(n6300), .A1(n6081), .B0(n563), .B1(n6099), .Y(n6105)
);
XNOR2X1TS U8785 ( .A(Data_B_i[21]), .B(Data_A_i[26]), .Y(n6104) );
OAI22X1TS U8786 ( .A0(n6304), .A1(n6080), .B0(n605), .B1(n6104), .Y(n6102)
);
OAI22X1TS U8787 ( .A0(n6300), .A1(n6082), .B0(n6415), .B1(n6081), .Y(n6092)
);
OAI22X1TS U8788 ( .A0(n1289), .A1(n6085), .B0(n6084), .B1(n6083), .Y(n6091)
);
INVX2TS U8789 ( .A(n7314), .Y(n6290) );
XNOR2X1TS U8790 ( .A(n6437), .B(n452), .Y(n6295) );
OAI22X1TS U8791 ( .A0(n6295), .A1(n6548), .B0(n6097), .B1(n578), .Y(n6289)
);
XNOR2X1TS U8792 ( .A(n6517), .B(n4502), .Y(n6298) );
OAI22X1TS U8793 ( .A0(n6098), .A1(n588), .B0(n6298), .B1(n479), .Y(n6288) );
XNOR2X1TS U8794 ( .A(n320), .B(n297), .Y(n6299) );
OAI22X1TS U8795 ( .A0(n6300), .A1(n6099), .B0(n563), .B1(n6299), .Y(n6307)
);
XNOR2X1TS U8796 ( .A(n330), .B(Data_A_i[23]), .Y(n6301) );
OAI22X1TS U8797 ( .A0(n357), .A1(n6100), .B0(n597), .B1(n6301), .Y(n6306) );
INVX2TS U8798 ( .A(Data_A_i[21]), .Y(n6302) );
OAI22X1TS U8799 ( .A0(n356), .A1(n6104), .B0(n604), .B1(n329), .Y(n6311) );
OAI22X1TS U8800 ( .A0(n6113), .A1(n589), .B0(n6112), .B1(n487), .Y(n6213) );
XNOR2X1TS U8801 ( .A(n6411), .B(n451), .Y(n6136) );
OAI22X1TS U8802 ( .A0(n6120), .A1(n6494), .B0(n6136), .B1(n478), .Y(n6131)
);
OAI22X1TS U8803 ( .A0(n6121), .A1(n6549), .B0(n6135), .B1(n469), .Y(n6130)
);
OAI22X1TS U8804 ( .A0(n6133), .A1(n6594), .B0(n6132), .B1(n420), .Y(n6140)
);
OAI22X1TS U8805 ( .A0(n6135), .A1(n6549), .B0(n6134), .B1(n469), .Y(n6139)
);
OAI22X1TS U8806 ( .A0(n6137), .A1(n479), .B0(n6136), .B1(n588), .Y(n6138) );
ADDFHX1TS U8807 ( .A(n6140), .B(n6139), .CI(n6138), .CO(n6182), .S(n6154) );
ADDFHX2TS U8808 ( .A(n6143), .B(n6142), .CI(n6141), .CO(n7314), .S(n7310) );
INVX2TS U8809 ( .A(n6161), .Y(n6197) );
OAI22X1TS U8810 ( .A0(n6165), .A1(n592), .B0(n6163), .B1(n481), .Y(n6181) );
ADDFHX1TS U8811 ( .A(n6170), .B(n6169), .CI(n6168), .CO(n6179), .S(n6211) );
ADDFHX1TS U8812 ( .A(n6178), .B(n6177), .CI(n6176), .CO(n6226), .S(n6238) );
XNOR2X1TS U8813 ( .A(n6370), .B(n435), .Y(n6316) );
OAI22X1TS U8814 ( .A0(n6189), .A1(n420), .B0(n6316), .B1(n251), .Y(n6317) );
INVX2TS U8815 ( .A(n6193), .Y(n6281) );
XOR2X1TS U8816 ( .A(n6205), .B(n6204), .Y(n6206) );
ADDFHX2TS U8817 ( .A(n6211), .B(n6210), .CI(n6209), .CO(n6241), .S(n6237) );
ADDFHX2TS U8818 ( .A(n6213), .B(n6683), .CI(n6212), .CO(n6219), .S(n6240) );
ADDFHX2TS U8819 ( .A(n6224), .B(n6223), .CI(n6222), .CO(n6252), .S(n6242) );
ADDFHX2TS U8820 ( .A(n6241), .B(n6240), .CI(n6239), .CO(n6247), .S(n6258) );
XNOR2X1TS U8821 ( .A(n6558), .B(n400), .Y(n6372) );
OAI22X1TS U8822 ( .A0(n6294), .A1(n587), .B0(n6372), .B1(n472), .Y(n6384) );
XNOR2X1TS U8823 ( .A(n6485), .B(n452), .Y(n6357) );
OAI22X1TS U8824 ( .A0(n6295), .A1(n578), .B0(n6357), .B1(n469), .Y(n6383) );
INVX2TS U8825 ( .A(n7316), .Y(n6382) );
XNOR2X1TS U8826 ( .A(n6550), .B(n451), .Y(n6362) );
OAI22X1TS U8827 ( .A0(n6298), .A1(n588), .B0(n6362), .B1(n478), .Y(n6361) );
INVX2TS U8828 ( .A(Data_A_i[22]), .Y(n6375) );
OAI22X1TS U8829 ( .A0(n243), .A1(n6302), .B0(n534), .B1(n6375), .Y(n6381) );
XNOR2X1TS U8830 ( .A(n320), .B(n298), .Y(n6373) );
OAI22X1TS U8831 ( .A0(n6300), .A1(n6299), .B0(n563), .B1(n6373), .Y(n6380)
);
XNOR2X1TS U8832 ( .A(n523), .B(Data_A_i[24]), .Y(n6374) );
OAI22X1TS U8833 ( .A0(n6520), .A1(n339), .B0(n533), .B1(n6302), .Y(n6377) );
CMPR32X2TS U8834 ( .A(n6307), .B(n6306), .C(n6305), .CO(n6364), .S(n6297) );
INVX2TS U8835 ( .A(n7315), .Y(n6360) );
XNOR2X1TS U8836 ( .A(n6411), .B(n435), .Y(n6356) );
OAI22X1TS U8837 ( .A0(n6316), .A1(n420), .B0(n6356), .B1(n251), .Y(n6366) );
CMPR32X2TS U8838 ( .A(n6319), .B(n6318), .C(n6317), .CO(n6386), .S(n6283) );
INVX2TS U8839 ( .A(n6320), .Y(n6385) );
NAND2X1TS U8840 ( .A(n8552), .B(n6609), .Y(n6330) );
NAND2X1TS U8841 ( .A(n6332), .B(n6331), .Y(n6640) );
NAND2X1TS U8842 ( .A(n8558), .B(n6640), .Y(n6343) );
NAND2X1TS U8843 ( .A(n6335), .B(n6334), .Y(n7983) );
NAND2X1TS U8844 ( .A(n6336), .B(n6333), .Y(n8114) );
AOI21X1TS U8845 ( .A0(n8115), .A1(n8116), .B0(n6337), .Y(n8125) );
NAND2X1TS U8846 ( .A(n6339), .B(n6338), .Y(n8123) );
NAND2X1TS U8847 ( .A(n6341), .B(n6340), .Y(n9479) );
AOI21X1TS U8848 ( .A0(n9481), .A1(n9480), .B0(n6342), .Y(n6645) );
XNOR2X1TS U8849 ( .A(n6343), .B(n8559), .Y(n6344) );
NAND2X1TS U8850 ( .A(n6345), .B(n6344), .Y(n9487) );
NAND2X1TS U8851 ( .A(n6346), .B(n9487), .Y(add_x_3_n16) );
ADDFHX2TS U8852 ( .A(n6352), .B(n6351), .CI(n6350), .CO(n6469), .S(n6471) );
ADDFHX2TS U8853 ( .A(n6355), .B(n6354), .CI(n6353), .CO(n6429), .S(n6352) );
XNOR2X1TS U8854 ( .A(n6437), .B(n435), .Y(n6420) );
OAI22X1TS U8855 ( .A0(n6420), .A1(n251), .B0(n6356), .B1(n420), .Y(n6401) );
XNOR2X1TS U8856 ( .A(n6517), .B(n452), .Y(n6408) );
OAI22X1TS U8857 ( .A0(n6357), .A1(n578), .B0(n6408), .B1(n469), .Y(n6400) );
INVX2TS U8858 ( .A(n6358), .Y(n6399) );
XNOR2X1TS U8859 ( .A(n6572), .B(n4502), .Y(n6398) );
OAI22X1TS U8860 ( .A0(n6362), .A1(n588), .B0(n6398), .B1(n478), .Y(n6404) );
INVX2TS U8861 ( .A(n7325), .Y(n6403) );
CMPR32X2TS U8862 ( .A(n6368), .B(n6367), .C(n6366), .CO(n6402), .S(n6387) );
INVX2TS U8863 ( .A(n6369), .Y(n6426) );
OAI22X1TS U8864 ( .A0(n6372), .A1(n587), .B0(n473), .B1(n6293), .Y(n6422) );
OAI22X1TS U8865 ( .A0(n6416), .A1(n6373), .B0(n563), .B1(n513), .Y(n6419) );
XNOR2X1TS U8866 ( .A(n523), .B(n297), .Y(n6414) );
OAI22X1TS U8867 ( .A0(n357), .A1(n6374), .B0(n597), .B1(n6414), .Y(n6418) );
INVX2TS U8868 ( .A(Data_A_i[23]), .Y(n6413) );
OAI22X1TS U8869 ( .A0(n243), .A1(n6375), .B0(n534), .B1(n6413), .Y(n6456) );
ADDFHX2TS U8870 ( .A(n6381), .B(n6380), .CI(n6379), .CO(n6394), .S(n6365) );
CMPR32X2TS U8871 ( .A(n6384), .B(n6383), .C(n6382), .CO(n6424), .S(n6355) );
INVX2TS U8872 ( .A(n7345), .Y(n6435) );
XNOR2X1TS U8873 ( .A(n6558), .B(n4502), .Y(n6461) );
OAI22X1TS U8874 ( .A0(n6398), .A1(n588), .B0(n6461), .B1(n479), .Y(n6434) );
CMPR32X2TS U8875 ( .A(n6404), .B(n6403), .C(n6402), .CO(n6441), .S(n6405) );
XNOR2X1TS U8876 ( .A(n6550), .B(n452), .Y(n6440) );
OAI22X1TS U8877 ( .A0(n6408), .A1(n578), .B0(n6440), .B1(n6548), .Y(n6446)
);
INVX2TS U8878 ( .A(Data_A_i[24]), .Y(n6454) );
OAI22X1TS U8879 ( .A0(n243), .A1(n6413), .B0(n534), .B1(n6454), .Y(n6460) );
XNOR2X1TS U8880 ( .A(n523), .B(n298), .Y(n6453) );
OAI22X1TS U8881 ( .A0(n6492), .A1(n6414), .B0(n598), .B1(n6453), .Y(n6457)
);
AO21X2TS U8882 ( .A0(n6416), .A1(n6415), .B0(n513), .Y(n6455) );
INVX2TS U8883 ( .A(n7344), .Y(n6450) );
XNOR2X1TS U8884 ( .A(n6485), .B(n435), .Y(n6449) );
OAI22X1TS U8885 ( .A0(n6420), .A1(n420), .B0(n6449), .B1(n251), .Y(n6448) );
ADDFHX2TS U8886 ( .A(n6429), .B(n6428), .CI(n6427), .CO(n6430), .S(n6468) );
INVX2TS U8887 ( .A(n6433), .Y(n6489) );
INVX2TS U8888 ( .A(n6439), .Y(n6500) );
XNOR2X1TS U8889 ( .A(n6572), .B(n452), .Y(n6481) );
OAI22X1TS U8890 ( .A0(n6440), .A1(n578), .B0(n6481), .B1(n6548), .Y(n6499)
);
ADDFHX2TS U8891 ( .A(n6446), .B(n6445), .CI(n6444), .CO(n6480), .S(n6464) );
XNOR2X1TS U8892 ( .A(n6517), .B(n435), .Y(n6498) );
OAI22X1TS U8893 ( .A0(n6449), .A1(n420), .B0(n6498), .B1(n251), .Y(n6504) );
ADDFHX1TS U8894 ( .A(n6452), .B(n6451), .CI(n6450), .CO(n6503), .S(n6444) );
OAI22X1TS U8895 ( .A0(n357), .A1(n6453), .B0(n598), .B1(n522), .Y(n6497) );
OAI22X1TS U8896 ( .A0(n243), .A1(n6454), .B0(n534), .B1(n296), .Y(n6523) );
OAI22X1TS U8897 ( .A0(n6461), .A1(n588), .B0(n478), .B1(n6397), .Y(n6482) );
ADDFHX2TS U8898 ( .A(n6467), .B(n6466), .CI(n6465), .CO(n6475), .S(n6431) );
ADDFHX4TS U8899 ( .A(n6473), .B(n6472), .CI(n6471), .CO(n6608), .S(n6606) );
ADDFHX2TS U8900 ( .A(n6480), .B(n6479), .CI(n6478), .CO(n6510), .S(n6505) );
XNOR2X1TS U8901 ( .A(n6558), .B(n452), .Y(n6530) );
OAI22X1TS U8902 ( .A0(n6481), .A1(n578), .B0(n6530), .B1(n469), .Y(n6516) );
INVX2TS U8903 ( .A(n6484), .Y(n6527) );
INVX2TS U8904 ( .A(n6490), .Y(n6536) );
INVX2TS U8905 ( .A(Data_A_i[26]), .Y(n6519) );
OAI22X1TS U8906 ( .A0(n243), .A1(n296), .B0(n534), .B1(n6519), .Y(n6522) );
INVX2TS U8907 ( .A(n7368), .Y(n6533) );
CMPR32X2TS U8908 ( .A(n6497), .B(n6496), .C(n6495), .CO(n7369), .S(n7348) );
INVX2TS U8909 ( .A(n7369), .Y(n6531) );
XNOR2X1TS U8910 ( .A(n6550), .B(n435), .Y(n6525) );
OAI22X1TS U8911 ( .A0(n6498), .A1(n419), .B0(n6525), .B1(n251), .Y(n6534) );
ADDFHX2TS U8912 ( .A(n6501), .B(n6500), .CI(n6499), .CO(n6512), .S(n6487) );
CMPR32X2TS U8913 ( .A(n6504), .B(n6503), .C(n6502), .CO(n6511), .S(n6478) );
ADDFHX2TS U8914 ( .A(n6507), .B(n6506), .CI(n6505), .CO(n6508), .S(n6477) );
NOR2X2TS U8915 ( .A(n6615), .B(n6614), .Y(n7920) );
INVX2TS U8916 ( .A(n7920), .Y(n9453) );
CMPR32X2TS U8917 ( .A(n6523), .B(n6522), .C(n6521), .CO(n9531), .S(n7368) );
INVX2TS U8918 ( .A(n9531), .Y(n6556) );
INVX2TS U8919 ( .A(n6524), .Y(n6555) );
XNOR2X1TS U8920 ( .A(n6572), .B(n435), .Y(n6559) );
OAI22X1TS U8921 ( .A0(n6525), .A1(n419), .B0(n6559), .B1(n251), .Y(n6552) );
OAI22X1TS U8922 ( .A0(n6530), .A1(n578), .B0(n6548), .B1(n6547), .Y(n6561)
);
OR2X4TS U8923 ( .A(n6617), .B(n6616), .Y(n7924) );
INVX2TS U8924 ( .A(n7908), .Y(n6604) );
ADDFX1TS U8925 ( .A(n6545), .B(n6544), .CI(n6543), .CO(n6568), .S(n6563) );
INVX2TS U8926 ( .A(n6546), .Y(n6580) );
XOR2X1TS U8927 ( .A(n6576), .B(n6575), .Y(n6579) );
NOR2X1TS U8928 ( .A(n6551), .B(n536), .Y(n6578) );
XNOR2X1TS U8929 ( .A(n6558), .B(n435), .Y(n6574) );
OAI22X1TS U8930 ( .A0(n6559), .A1(n420), .B0(n6574), .B1(n251), .Y(n6570) );
NOR2X2TS U8931 ( .A(n6621), .B(n6620), .Y(n7911) );
CMPR32X2TS U8932 ( .A(n6571), .B(n6570), .C(n6569), .CO(n6586), .S(n6581) );
NOR2X1TS U8933 ( .A(n6573), .B(n536), .Y(n6602) );
OAI22X1TS U8934 ( .A0(n6574), .A1(n419), .B0(n251), .B1(n434), .Y(n6588) );
NAND2X1TS U8935 ( .A(n6577), .B(n6576), .Y(n6587) );
CMPR32X2TS U8936 ( .A(n6580), .B(n6579), .C(n6578), .CO(n6600), .S(n6583) );
OR2X4TS U8937 ( .A(n6623), .B(n6622), .Y(n8206) );
CMPR32X2TS U8938 ( .A(n6589), .B(n6588), .C(n6587), .CO(n6630), .S(n6601) );
CMPR32X2TS U8939 ( .A(n6592), .B(n6591), .C(n6590), .CO(n6593), .S(n6596) );
INVX2TS U8940 ( .A(n6593), .Y(n6632) );
CMPR32X2TS U8941 ( .A(n6602), .B(n6601), .C(n6600), .CO(n6628), .S(n6585) );
INVX2TS U8942 ( .A(n9454), .Y(n6619) );
NAND2X1TS U8943 ( .A(n6617), .B(n6616), .Y(n7923) );
INVX2TS U8944 ( .A(n7923), .Y(n6618) );
AOI21X4TS U8945 ( .A0(n6619), .A1(n7924), .B0(n6618), .Y(n7907) );
NAND2X1TS U8946 ( .A(n6625), .B(n6624), .Y(n8211) );
CMPR32X2TS U8947 ( .A(n6630), .B(n6629), .C(n6628), .CO(n6639), .S(n6624) );
CMPR32X2TS U8948 ( .A(n6635), .B(n6634), .C(n6633), .CO(n6636), .S(n6629) );
NAND2X1TS U8949 ( .A(n1713), .B(n7928), .Y(n7396) );
OR2X2TS U8950 ( .A(n6642), .B(n6641), .Y(n8561) );
NAND2X1TS U8951 ( .A(n8561), .B(n8558), .Y(n6646) );
INVX2TS U8952 ( .A(n6640), .Y(n8557) );
NAND2X1TS U8953 ( .A(n6642), .B(n6641), .Y(n8560) );
AOI21X1TS U8954 ( .A0(n8561), .A1(n8557), .B0(n6643), .Y(n6644) );
NAND2X1TS U8955 ( .A(n6648), .B(n6647), .Y(n8547) );
AOI21X1TS U8956 ( .A0(n8550), .A1(n8548), .B0(n6649), .Y(n8376) );
NAND2X1TS U8957 ( .A(n1707), .B(n9458), .Y(n6656) );
NAND2X1TS U8958 ( .A(n6651), .B(n6650), .Y(n8377) );
NAND2X1TS U8959 ( .A(n6653), .B(n6652), .Y(n9460) );
AOI21X1TS U8960 ( .A0(n1707), .A1(n9457), .B0(n6654), .Y(n6655) );
OAI21X1TS U8961 ( .A0(n8376), .A1(n6656), .B0(n6655), .Y(n7394) );
NAND2X1TS U8962 ( .A(n6658), .B(n6657), .Y(n7927) );
AOI21X1TS U8963 ( .A0(n1713), .A1(n6661), .B0(n6660), .Y(n7395) );
NAND2X1TS U8964 ( .A(n6663), .B(n6662), .Y(n7398) );
AOI21X1TS U8965 ( .A0(n6665), .A1(n7394), .B0(n6664), .Y(n7307) );
INVX2TS U8966 ( .A(n7307), .Y(n8217) );
NAND2X1TS U8967 ( .A(n6667), .B(n6666), .Y(n8214) );
AOI21X1TS U8968 ( .A0(n8217), .A1(n8215), .B0(n6668), .Y(n6673) );
NAND2X1TS U8969 ( .A(n6670), .B(n6669), .Y(n6681) );
NAND2X1TS U8970 ( .A(n6671), .B(n6681), .Y(n6672) );
AOI21X2TS U8971 ( .A0(n529), .A1(n6679), .B0(n6678), .Y(n9497) );
AOI21X1TS U8972 ( .A0(n8217), .A1(n7299), .B0(n7304), .Y(n6687) );
NAND2X1TS U8973 ( .A(n6685), .B(n7301), .Y(n6686) );
INVX2TS U8974 ( .A(n6688), .Y(n7686) );
NAND2X1TS U8975 ( .A(n159), .B(n6690), .Y(n6691) );
XNOR2X1TS U8976 ( .A(n6833), .B(n6704), .Y(n6780) );
OAI22X1TS U8977 ( .A0(n6705), .A1(n577), .B0(n6780), .B1(n493), .Y(n6773) );
CMPR32X2TS U8978 ( .A(n9613), .B(n6707), .C(n6706), .CO(n6772), .S(n6740) );
INVX2TS U8979 ( .A(Data_A_i[37]), .Y(n6711) );
NOR2X1TS U8980 ( .A(n624), .B(n6711), .Y(n6824) );
XNOR2X1TS U8981 ( .A(n260), .B(n311), .Y(n6766) );
OAI22X1TS U8982 ( .A0(n770), .A1(n6713), .B0(n468), .B1(n6766), .Y(n6767) );
CMPR32X2TS U8983 ( .A(n6716), .B(n6715), .C(n6714), .CO(n6777), .S(n6736) );
INVX2TS U8984 ( .A(n7201), .Y(n6776) );
INVX2TS U8985 ( .A(Data_A_i[53]), .Y(n6759) );
OAI22X1TS U8986 ( .A0(n6760), .A1(n6726), .B0(n686), .B1(n6759), .Y(n6762)
);
INVX2TS U8987 ( .A(n9679), .Y(n6783) );
CMPR32X2TS U8988 ( .A(n6735), .B(n6734), .C(n6733), .CO(n9680), .S(n9613) );
INVX2TS U8989 ( .A(n9680), .Y(n6781) );
XNOR2X1TS U8990 ( .A(n6827), .B(n402), .Y(n6770) );
OAI22X1TS U8991 ( .A0(n6739), .A1(n7780), .B0(n6770), .B1(n490), .Y(n6784)
);
CMPR32X2TS U8992 ( .A(n6742), .B(n6741), .C(n6740), .CO(n6754), .S(n6698) );
NOR2X2TS U8993 ( .A(n6748), .B(n6747), .Y(n6804) );
NOR2X1TS U8994 ( .A(n9631), .B(n6804), .Y(n6750) );
AOI21X2TS U8995 ( .A0(n6750), .A1(n9635), .B0(n6749), .Y(n6793) );
ADDFX1TS U8996 ( .A(n6756), .B(n6755), .CI(n6754), .CO(n6813), .S(n6787) );
CMPR32X2TS U8997 ( .A(n6763), .B(n6762), .C(n6761), .CO(n9690), .S(n9679) );
INVX2TS U8998 ( .A(n9690), .Y(n6832) );
INVX2TS U8999 ( .A(Data_A_i[38]), .Y(n6765) );
NOR2X1TS U9000 ( .A(n623), .B(n6765), .Y(n6823) );
XNOR2X1TS U9001 ( .A(n260), .B(Data_A_i[40]), .Y(n6821) );
OAI22X1TS U9002 ( .A0(n770), .A1(n6766), .B0(n7736), .B1(n6821), .Y(n6822)
);
XNOR2X1TS U9003 ( .A(n7732), .B(n403), .Y(n6834) );
OAI22X1TS U9004 ( .A0(n6770), .A1(n423), .B0(n6834), .B1(n491), .Y(n6829) );
CMPR32X2TS U9005 ( .A(n6776), .B(n6775), .C(n6774), .CO(n6816), .S(n6771) );
OAI22X1TS U9006 ( .A0(n6780), .A1(n577), .B0(n494), .B1(n424), .Y(n6836) );
XOR2X4TS U9007 ( .A(n6793), .B(n6792), .Y(n9656) );
NAND2X1TS U9008 ( .A(n9643), .B(n9640), .Y(n6799) );
NAND2X1TS U9009 ( .A(n6796), .B(n6795), .Y(n9642) );
AOI21X1TS U9010 ( .A0(n9643), .A1(n9639), .B0(n6797), .Y(n6798) );
OAI21X1TS U9011 ( .A0(n6800), .A1(n6799), .B0(n6798), .Y(n7795) );
NAND2X1TS U9012 ( .A(n6802), .B(n6801), .Y(n7755) );
NAND2X1TS U9013 ( .A(n7754), .B(n7755), .Y(n6803) );
NOR2X1TS U9014 ( .A(n9631), .B(n7942), .Y(n6810) );
INVX2TS U9015 ( .A(n6805), .Y(n6806) );
AOI21X4TS U9016 ( .A0(n6808), .A1(n6807), .B0(n6806), .Y(n8187) );
ADDFHX2TS U9017 ( .A(n6813), .B(n6812), .CI(n6811), .CO(n6842), .S(n6790) );
INVX2TS U9018 ( .A(n8034), .Y(n7748) );
INVX2TS U9019 ( .A(Data_A_i[39]), .Y(n6820) );
OAI22X1TS U9020 ( .A0(n770), .A1(n6821), .B0(n468), .B1(n624), .Y(n7739) );
AO21X1TS U9021 ( .A0(n576), .A1(n493), .B0(n424), .Y(n7744) );
XOR2X1TS U9022 ( .A(n8033), .B(n7744), .Y(n7747) );
CMPR32X2TS U9023 ( .A(n6831), .B(n6830), .C(n6829), .CO(n7750), .S(n6840) );
XNOR2X1TS U9024 ( .A(n6833), .B(n402), .Y(n7743) );
OAI22X1TS U9025 ( .A0(n6834), .A1(n423), .B0(n7743), .B1(n491), .Y(n7730) );
CMPR32X2TS U9026 ( .A(n6837), .B(n6836), .C(n6835), .CO(n7729), .S(n6815) );
NAND2X1TS U9027 ( .A(n6848), .B(n6847), .Y(n7756) );
NAND2X1TS U9028 ( .A(n7759), .B(n7756), .Y(n6849) );
XNOR2X1TS U9029 ( .A(n6850), .B(n6849), .Y(n6851) );
NOR2X4TS U9030 ( .A(n6852), .B(n6851), .Y(n8496) );
NOR2X2TS U9031 ( .A(n6862), .B(n6861), .Y(n6983) );
NOR2X2TS U9032 ( .A(n6864), .B(n6863), .Y(n7003) );
NOR2X1TS U9033 ( .A(n6983), .B(n7003), .Y(n6868) );
NAND2X1TS U9034 ( .A(n6864), .B(n6863), .Y(n7004) );
NAND2X1TS U9035 ( .A(n6866), .B(n1217), .Y(n6870) );
NAND2X1TS U9036 ( .A(n6868), .B(n193), .Y(n6869) );
INVX2TS U9037 ( .A(n6869), .Y(n6873) );
XNOR2X1TS U9038 ( .A(n8227), .B(n439), .Y(n7030) );
OAI22X1TS U9039 ( .A0(n7013), .A1(n560), .B0(n7030), .B1(n471), .Y(n7046) );
XNOR2X1TS U9040 ( .A(n7470), .B(n380), .Y(n6949) );
XNOR2X1TS U9041 ( .A(n6881), .B(n6876), .Y(n6880) );
OAI21X1TS U9042 ( .A0(Data_B_i[51]), .A1(Data_B_i[24]), .B0(Data_B_i[23]),
.Y(n6878) );
NAND2X1TS U9043 ( .A(Data_B_i[51]), .B(Data_B_i[24]), .Y(n6877) );
NAND2X1TS U9044 ( .A(n6878), .B(n6877), .Y(n6884) );
NAND2X1TS U9045 ( .A(n6887), .B(n6884), .Y(n6879) );
OAI22X1TS U9046 ( .A0(n6949), .A1(n135), .B0(n6904), .B1(n8426), .Y(n6953)
);
XNOR2X1TS U9047 ( .A(n7474), .B(n405), .Y(n6950) );
XOR2X1TS U9048 ( .A(n6888), .B(n6887), .Y(n6889) );
NAND2X1TS U9049 ( .A(n6908), .B(n6892), .Y(n6896) );
AOI21X1TS U9050 ( .A0(n6892), .A1(n6912), .B0(n6891), .Y(n6899) );
NAND2X1TS U9051 ( .A(n6893), .B(n6897), .Y(n6894) );
XNOR2X1TS U9052 ( .A(n7485), .B(n2939), .Y(n6954) );
OAI21X1TS U9053 ( .A0(n6899), .A1(n6898), .B0(n6897), .Y(n6900) );
INVX2TS U9054 ( .A(n6900), .Y(n6901) );
XNOR2X1TS U9055 ( .A(n8428), .B(n393), .Y(n6903) );
OAI22X1TS U9056 ( .A0(n6954), .A1(n552), .B0(n6903), .B1(n8237), .Y(n6951)
);
INVX2TS U9057 ( .A(n6937), .Y(n6925) );
OAI22X1TS U9058 ( .A0(n6903), .A1(n551), .B0(n8237), .B1(n392), .Y(n6924) );
XNOR2X1TS U9059 ( .A(n7474), .B(n381), .Y(n6919) );
INVX2TS U9060 ( .A(n7436), .Y(n6905) );
INVX2TS U9061 ( .A(n7472), .Y(n6906) );
XNOR2X1TS U9062 ( .A(n7487), .B(n404), .Y(n6920) );
NAND2X1TS U9063 ( .A(n6908), .B(n6911), .Y(n6914) );
AOI21X1TS U9064 ( .A0(n6912), .A1(n6911), .B0(n6910), .Y(n6913) );
XNOR2X1TS U9065 ( .A(n7550), .B(n395), .Y(n6945) );
XNOR2X1TS U9066 ( .A(n7485), .B(n395), .Y(n6922) );
OAI22X1TS U9067 ( .A0(n6945), .A1(n553), .B0(n6922), .B1(n467), .Y(n6926) );
XNOR2X1TS U9068 ( .A(n753), .B(n380), .Y(n6933) );
OAI22X1TS U9069 ( .A0(n6933), .A1(n462), .B0(n6919), .B1(n548), .Y(n6931) );
XNOR2X1TS U9070 ( .A(n7550), .B(n405), .Y(n6932) );
OAI22X1TS U9071 ( .A0(n6920), .A1(n554), .B0(n6932), .B1(n457), .Y(n6930) );
XNOR2X1TS U9072 ( .A(n8428), .B(n394), .Y(n6935) );
OAI22X1TS U9073 ( .A0(n6922), .A1(n553), .B0(n6935), .B1(n467), .Y(n6941) );
ADDFHX1TS U9074 ( .A(n6925), .B(n6924), .CI(n6923), .CO(n6940), .S(n6943) );
CMPR32X2TS U9075 ( .A(n6931), .B(n6930), .C(n6929), .CO(n7052), .S(n6990) );
XNOR2X1TS U9076 ( .A(n7485), .B(n404), .Y(n7035) );
OAI22X1TS U9077 ( .A0(n6932), .A1(n554), .B0(n7035), .B1(n457), .Y(n7040) );
XNOR2X1TS U9078 ( .A(n7487), .B(n381), .Y(n7036) );
OAI22X1TS U9079 ( .A0(n6933), .A1(n135), .B0(n7036), .B1(n462), .Y(n7039) );
INVX2TS U9080 ( .A(n7474), .Y(n6934) );
INVX2TS U9081 ( .A(n7069), .Y(n7034) );
OAI22X1TS U9082 ( .A0(n6935), .A1(n8259), .B0(n466), .B1(n175), .Y(n7033) );
CMPR32X2TS U9083 ( .A(n6941), .B(n6940), .C(n6939), .CO(n7050), .S(n6989) );
INVX2TS U9084 ( .A(n8928), .Y(n7044) );
XNOR2X1TS U9085 ( .A(n7487), .B(n394), .Y(n6955) );
OAI22X1TS U9086 ( .A0(n6955), .A1(n553), .B0(n6945), .B1(n466), .Y(n6958) );
INVX2TS U9087 ( .A(n6948), .Y(n8269) );
OAI22X1TS U9088 ( .A0(n6950), .A1(n458), .B0(n8254), .B1(n554), .Y(n8267) );
XNOR2X1TS U9089 ( .A(n8428), .B(n362), .Y(n8234) );
OAI22X1TS U9090 ( .A0(n8234), .A1(n547), .B0(n8233), .B1(n200), .Y(n8247) );
XNOR2X1TS U9091 ( .A(n7550), .B(n393), .Y(n8238) );
XNOR2X1TS U9092 ( .A(n753), .B(n394), .Y(n8261) );
OAI22X1TS U9093 ( .A0(n8261), .A1(n553), .B0(n6955), .B1(n466), .Y(n8245) );
INVX2TS U9094 ( .A(n8925), .Y(n8348) );
ADDFHX2TS U9095 ( .A(Data_A_i[26]), .B(n317), .CI(n7145), .CO(n6960), .S(
n6962) );
INVX2TS U9096 ( .A(n7423), .Y(n7008) );
OAI22X1TS U9097 ( .A0(n6987), .A1(n369), .B0(n7008), .B1(n8855), .Y(n6994)
);
XNOR2X1TS U9098 ( .A(n8225), .B(n359), .Y(n7009) );
XOR2X1TS U9099 ( .A(n6968), .B(n6967), .Y(n6969) );
XOR2X1TS U9100 ( .A(n6972), .B(n6971), .Y(n6973) );
XNOR2X1TS U9101 ( .A(n8311), .B(n358), .Y(n7016) );
XNOR2X1TS U9102 ( .A(n8227), .B(n443), .Y(n6998) );
OAI22X1TS U9103 ( .A0(n6998), .A1(n413), .B0(n615), .B1(n6986), .Y(n6992) );
INVX2TS U9104 ( .A(n6974), .Y(n7022) );
XNOR2X1TS U9105 ( .A(n8228), .B(n438), .Y(n6995) );
NOR2X1TS U9106 ( .A(n6979), .B(n6978), .Y(n6981) );
XOR2X1TS U9107 ( .A(n6981), .B(n6980), .Y(n6982) );
INVX2TS U9108 ( .A(n6983), .Y(n7001) );
NAND2X1TS U9109 ( .A(n7001), .B(n6999), .Y(n6984) );
XNOR2X1TS U9110 ( .A(n8277), .B(n438), .Y(n7017) );
OAI22X1TS U9111 ( .A0(n6995), .A1(n411), .B0(n7017), .B1(n612), .Y(n7021) );
INVX2TS U9112 ( .A(n6985), .Y(n7020) );
INVX2TS U9113 ( .A(n8225), .Y(n7053) );
OAI22X1TS U9114 ( .A0(n7053), .A1(n8450), .B0(n6987), .B1(n8855), .Y(n7048)
);
XNOR2X1TS U9115 ( .A(n8311), .B(n438), .Y(n8226) );
OAI22X1TS U9116 ( .A0(n6995), .A1(n612), .B0(n410), .B1(n8226), .Y(n8299) );
INVX2TS U9117 ( .A(n7507), .Y(n6997) );
OAI22X1TS U9118 ( .A0(n8855), .A1(n6997), .B0(n1086), .B1(n369), .Y(n8303)
);
XNOR2X1TS U9119 ( .A(n7593), .B(n7405), .Y(n8319) );
OAI22X1TS U9120 ( .A0(n8315), .A1(n413), .B0(n6998), .B1(n615), .Y(n8329) );
NAND2X1TS U9121 ( .A(n7005), .B(n7004), .Y(n7006) );
XNOR2X1TS U9122 ( .A(n8277), .B(n440), .Y(n8229) );
OAI22X1TS U9123 ( .A0(n7014), .A1(n471), .B0(n8229), .B1(n560), .Y(n8328) );
OAI22X1TS U9124 ( .A0(n7008), .A1(n369), .B0(n8855), .B1(n1086), .Y(n7011)
);
OAI22X1TS U9125 ( .A0(n7014), .A1(n560), .B0(n7013), .B1(n470), .Y(n7018) );
XNOR2X1TS U9126 ( .A(n8228), .B(n359), .Y(n7031) );
OAI22X1TS U9127 ( .A0(n7031), .A1(n506), .B0(n7016), .B1(n556), .Y(n7028) );
XNOR2X1TS U9128 ( .A(n8276), .B(n438), .Y(n7026) );
OAI22X1TS U9129 ( .A0(n7026), .A1(n612), .B0(n7017), .B1(n411), .Y(n7027) );
ADDFHX2TS U9130 ( .A(n7025), .B(n7024), .CI(n7023), .CO(n8365), .S(n8358) );
OAI22X1TS U9131 ( .A0(n7026), .A1(n410), .B0(n7082), .B1(n613), .Y(n7081) );
OAI22X1TS U9132 ( .A0(n7030), .A1(n560), .B0(n471), .B1(n7092), .Y(n7097) );
XNOR2X1TS U9133 ( .A(n8277), .B(n359), .Y(n7062) );
OAI22X1TS U9134 ( .A0(n7031), .A1(n557), .B0(n7062), .B1(n507), .Y(n7096) );
OAI22X1TS U9135 ( .A0(n7035), .A1(n554), .B0(n7071), .B1(n457), .Y(n7075) );
OAI22X1TS U9136 ( .A0(n7036), .A1(n135), .B0(n7072), .B1(n8426), .Y(n7074)
);
ADDFHX2TS U9137 ( .A(n7040), .B(n7039), .CI(n7038), .CO(n7076), .S(n7051) );
INVX2TS U9138 ( .A(n8311), .Y(n7066) );
OAI22X1TS U9139 ( .A0(n7053), .A1(n537), .B0(n7066), .B1(n369), .Y(n7065) );
INVX2TS U9140 ( .A(n7054), .Y(n7064) );
INVX2TS U9141 ( .A(n7055), .Y(n7063) );
XNOR2X1TS U9142 ( .A(n8276), .B(n359), .Y(n7123) );
OAI22X1TS U9143 ( .A0(n7123), .A1(n507), .B0(n7062), .B1(n556), .Y(n7126) );
ADDFHX2TS U9144 ( .A(n7065), .B(n7064), .CI(n7063), .CO(n7125), .S(n7098) );
OAI22X1TS U9145 ( .A0(n7129), .A1(n369), .B0(n7066), .B1(n8855), .Y(n7128)
);
NOR2X1TS U9146 ( .A(n7070), .B(n197), .Y(n7119) );
INVX2TS U9147 ( .A(n7160), .Y(n7118) );
XNOR2X1TS U9148 ( .A(n7485), .B(n381), .Y(n7116) );
OAI22X1TS U9149 ( .A0(n7072), .A1(n135), .B0(n7116), .B1(n8426), .Y(n7117)
);
ADDFHX2TS U9150 ( .A(n7075), .B(n7074), .CI(n7073), .CO(n7130), .S(n7077) );
INVX2TS U9151 ( .A(n8935), .Y(n7127) );
XNOR2X1TS U9152 ( .A(n8227), .B(n438), .Y(n7133) );
OAI22X1TS U9153 ( .A0(n7082), .A1(n411), .B0(n7133), .B1(n613), .Y(n7135) );
ADDFHX2TS U9154 ( .A(n7085), .B(n7084), .CI(n7083), .CO(n7115), .S(n7089) );
NOR2X1TS U9155 ( .A(n8424), .B(n7087), .Y(n7150) );
INVX2TS U9156 ( .A(n7150), .Y(n7111) );
XNOR2X1TS U9157 ( .A(n500), .B(n808), .Y(n7109) );
OAI22X1TS U9158 ( .A0(n690), .A1(n7088), .B0(n7109), .B1(n416), .Y(n7110) );
INVX2TS U9159 ( .A(n7232), .Y(n7120) );
NAND2X2TS U9160 ( .A(n8107), .B(n8106), .Y(DP_OP_59J6_122_190_n136) );
NOR2X1TS U9161 ( .A(n8424), .B(n7107), .Y(n7149) );
XNOR2X1TS U9162 ( .A(n7108), .B(n8423), .Y(n7147) );
INVX2TS U9163 ( .A(n7238), .Y(n7144) );
ADDFHX2TS U9164 ( .A(n7115), .B(n7114), .CI(n7113), .CO(n7239), .S(n7231) );
INVX2TS U9165 ( .A(n7239), .Y(n7143) );
OAI22X1TS U9166 ( .A0(n7116), .A1(n548), .B0(n7159), .B1(n8426), .Y(n7163)
);
OAI22X1TS U9167 ( .A0(n7123), .A1(n557), .B0(n7164), .B1(n506), .Y(n7155) );
INVX2TS U9168 ( .A(n8937), .Y(n7166) );
INVX2TS U9169 ( .A(n438), .Y(n7504) );
OAI22X1TS U9170 ( .A0(n7133), .A1(n411), .B0(n613), .B1(n7504), .Y(n7165) );
ADDFHX2TS U9171 ( .A(n7136), .B(n7135), .CI(n7134), .CO(n7168), .S(n7139) );
CLKINVX1TS U9172 ( .A(n808), .Y(n7146) );
NOR2X1TS U9173 ( .A(n436), .B(n7146), .Y(n8454) );
INVX2TS U9174 ( .A(n8454), .Y(n8431) );
INVX2TS U9175 ( .A(n8402), .Y(n8434) );
ADDFHX2TS U9176 ( .A(n7153), .B(n7152), .CI(n7151), .CO(n8403), .S(n7238) );
INVX2TS U9177 ( .A(n8403), .Y(n8433) );
CLKINVX1TS U9178 ( .A(n8276), .Y(n8436) );
OAI22X1TS U9179 ( .A0(n8436), .A1(n369), .B0(n7154), .B1(n537), .Y(n8438) );
XNOR2X1TS U9180 ( .A(n8227), .B(n359), .Y(n8435) );
OAI22X1TS U9181 ( .A0(n7164), .A1(n556), .B0(n8435), .B1(n506), .Y(n8418) );
NAND2X1TS U9182 ( .A(n7184), .B(n7183), .Y(n8842) );
NAND2X2TS U9183 ( .A(n7188), .B(n9367), .Y(n7189) );
INVX2TS U9184 ( .A(n7207), .Y(n7191) );
AOI21X1TS U9185 ( .A0(n189), .A1(n7197), .B0(n7196), .Y(n8037) );
AOI21X1TS U9186 ( .A0(n8060), .A1(n7199), .B0(n7198), .Y(n7203) );
INVX2TS U9187 ( .A(n8028), .Y(n7212) );
NAND2X1TS U9188 ( .A(n7201), .B(n7200), .Y(n8032) );
NAND2X1TS U9189 ( .A(n7212), .B(n8032), .Y(n7202) );
XOR2X1TS U9190 ( .A(n7203), .B(n7202), .Y(n7204) );
OAI21X1TS U9191 ( .A0(n8477), .A1(n8473), .B0(n8474), .Y(n7226) );
INVX2TS U9192 ( .A(n8029), .Y(n8050) );
NAND2X1TS U9193 ( .A(n8050), .B(n7212), .Y(n7214) );
AOI21X1TS U9194 ( .A0(n8054), .A1(n7212), .B0(n7211), .Y(n7213) );
AOI21X1TS U9195 ( .A0(n8060), .A1(n7216), .B0(n7215), .Y(n7221) );
NAND2X1TS U9196 ( .A(n7218), .B(n7217), .Y(n8030) );
NAND2X1TS U9197 ( .A(n7219), .B(n8030), .Y(n7220) );
XOR2X1TS U9198 ( .A(n7221), .B(n7220), .Y(n7222) );
XNOR2X1TS U9199 ( .A(n7226), .B(n7225), .Y(EVEN1_Q_left[25]) );
INVX2TS U9200 ( .A(n7227), .Y(n9436) );
INVX2TS U9201 ( .A(n8711), .Y(n8394) );
NAND2X1TS U9202 ( .A(n8394), .B(n8481), .Y(n7235) );
AOI21X1TS U9203 ( .A0(n191), .A1(n7230), .B0(n7229), .Y(n8717) );
NAND2X1TS U9204 ( .A(n7232), .B(n7231), .Y(n8480) );
AOI21X1TS U9205 ( .A0(n8397), .A1(n8481), .B0(n7233), .Y(n7234) );
AOI21X1TS U9206 ( .A0(n9434), .A1(n7237), .B0(n7236), .Y(n7242) );
NAND2X1TS U9207 ( .A(n7239), .B(n7238), .Y(n8395) );
NAND2X1TS U9208 ( .A(n7240), .B(n8395), .Y(n7241) );
XOR2X1TS U9209 ( .A(n7242), .B(n7241), .Y(n7251) );
INVX2TS U9210 ( .A(n7243), .Y(n8488) );
NAND2X1TS U9211 ( .A(n7246), .B(n7245), .Y(n7247) );
ADDFHX2TS U9212 ( .A(n7251), .B(n7250), .CI(n7249), .CO(
DP_OP_62J6_125_4796_n546), .S(DP_OP_62J6_125_4796_n547) );
NAND2X1TS U9213 ( .A(n7269), .B(n7268), .Y(n7271) );
INVX2TS U9214 ( .A(EVEN1_Q_left[21]), .Y(n8676) );
OAI21X1TS U9215 ( .A0(n7278), .A1(n7689), .B0(n7690), .Y(n7279) );
CLKINVX1TS U9216 ( .A(n7281), .Y(n7283) );
NAND2X1TS U9217 ( .A(n7283), .B(n7282), .Y(n7284) );
ADDFHX2TS U9218 ( .A(n7288), .B(n7287), .CI(n7286), .CO(
DP_OP_62J6_125_4796_n560), .S(DP_OP_62J6_125_4796_n561) );
NOR2X1TS U9219 ( .A(n7289), .B(n7298), .Y(n7292) );
CLKINVX1TS U9220 ( .A(n7304), .Y(n7290) );
OAI21X1TS U9221 ( .A0(n7290), .A1(n7298), .B0(n7301), .Y(n7291) );
AOI21X1TS U9222 ( .A0(n7292), .A1(n8217), .B0(n7291), .Y(n7297) );
NAND2X1TS U9223 ( .A(n7294), .B(n7293), .Y(n7300) );
NAND2X1TS U9224 ( .A(n7295), .B(n7300), .Y(n7296) );
NOR2X1TS U9225 ( .A(n7298), .B(n7302), .Y(n7305) );
NAND2X1TS U9226 ( .A(n7305), .B(n7299), .Y(n7308) );
AOI21X1TS U9227 ( .A0(n7305), .A1(n7304), .B0(n7303), .Y(n7306) );
NAND2X1TS U9228 ( .A(n7310), .B(n7309), .Y(n7328) );
NAND2X1TS U9229 ( .A(n7330), .B(n7328), .Y(n7311) );
NOR2X1TS U9230 ( .A(n7313), .B(n7314), .Y(n7331) );
NAND2X1TS U9231 ( .A(n7314), .B(n7313), .Y(n7332) );
AOI21X1TS U9232 ( .A0(n9530), .A1(n9517), .B0(n9527), .Y(n7318) );
NAND2X1TS U9233 ( .A(n7316), .B(n7315), .Y(n7337) );
NAND2X1TS U9234 ( .A(n7336), .B(n7337), .Y(n7317) );
AOI21X1TS U9235 ( .A0(n9530), .A1(n7323), .B0(n7322), .Y(n7327) );
NAND2X1TS U9236 ( .A(n7325), .B(n7324), .Y(n7338) );
NAND2X1TS U9237 ( .A(n7341), .B(n7338), .Y(n7326) );
AOI21X1TS U9238 ( .A0(n9530), .A1(n7330), .B0(n7329), .Y(n7335) );
NAND2X1TS U9239 ( .A(n7333), .B(n7332), .Y(n7334) );
NAND2X1TS U9240 ( .A(n7336), .B(n7341), .Y(n9516) );
INVX2TS U9241 ( .A(n9516), .Y(n7343) );
NAND2X1TS U9242 ( .A(n9517), .B(n7343), .Y(n7359) );
AOI21X1TS U9243 ( .A0(n7341), .A1(n7340), .B0(n7339), .Y(n9524) );
AOI21X1TS U9244 ( .A0(n9527), .A1(n7343), .B0(n7342), .Y(n7365) );
NAND2X1TS U9245 ( .A(n7345), .B(n7344), .Y(n7362) );
AOI21X1TS U9246 ( .A0(n9530), .A1(n7347), .B0(n7346), .Y(n7352) );
NAND2X1TS U9247 ( .A(n7349), .B(n7348), .Y(n7360) );
NAND2X1TS U9248 ( .A(n7350), .B(n7360), .Y(n7351) );
AOI21X1TS U9249 ( .A0(n9530), .A1(n7354), .B0(n7353), .Y(n7357) );
NAND2X1TS U9250 ( .A(n7355), .B(n7362), .Y(n7356) );
NAND2X1TS U9251 ( .A(add_x_3_n70), .B(n9495), .Y(n9505) );
AOI21X1TS U9252 ( .A0(n9530), .A1(n7367), .B0(n7366), .Y(n7371) );
NAND2X1TS U9253 ( .A(n7369), .B(n7368), .Y(n9518) );
NAND2X1TS U9254 ( .A(n9520), .B(n9518), .Y(n7370) );
NAND2X1TS U9255 ( .A(add_x_3_n5), .B(n11465), .Y(add_x_3_n41) );
AFHCONX2TS U9256 ( .A(n4350), .B(n2093), .CI(n7375), .CON(n7381), .S(n9710)
);
XOR2X4TS U9257 ( .A(n7378), .B(n7377), .Y(n9359) );
NAND2X1TS U9258 ( .A(n7380), .B(n7379), .Y(n7382) );
NOR2X1TS U9259 ( .A(n7908), .B(n7911), .Y(n8204) );
NOR2X1TS U9260 ( .A(n9448), .B(n7388), .Y(n7390) );
OAI21X1TS U9261 ( .A0(n7388), .A1(n9449), .B0(n7387), .Y(n7389) );
NAND2X1TS U9262 ( .A(n7399), .B(n7398), .Y(n7400) );
XNOR2X1TS U9263 ( .A(n7401), .B(n7400), .Y(n7402) );
XNOR2X1TS U9264 ( .A(n7593), .B(n437), .Y(n7410) );
XNOR2X1TS U9265 ( .A(n7423), .B(n437), .Y(n8321) );
OAI22X1TS U9266 ( .A0(n410), .A1(n7410), .B0(n8321), .B1(n612), .Y(n8613) );
INVX2TS U9267 ( .A(n7591), .Y(n7409) );
XNOR2X1TS U9268 ( .A(n7507), .B(n359), .Y(n8320) );
OAI22X1TS U9269 ( .A0(n556), .A1(n7407), .B0(n507), .B1(n8320), .Y(n8313) );
XNOR2X1TS U9270 ( .A(n8225), .B(n442), .Y(n7524) );
XNOR2X1TS U9271 ( .A(n8311), .B(n442), .Y(n7466) );
OAI22X1TS U9272 ( .A0(n7524), .A1(n413), .B0(n7466), .B1(n614), .Y(n7624) );
NOR2BX1TS U9273 ( .AN(n633), .B(n8450), .Y(n7415) );
XNOR2X1TS U9274 ( .A(n359), .B(n7591), .Y(n7518) );
XNOR2X1TS U9275 ( .A(n358), .B(n7420), .Y(n7408) );
XNOR2X1TS U9276 ( .A(n7505), .B(n437), .Y(n7421) );
XNOR2X1TS U9277 ( .A(n7507), .B(n437), .Y(n7411) );
OAI22X1TS U9278 ( .A0(n411), .A1(n7421), .B0(n7411), .B1(n613), .Y(n7413) );
XNOR2X1TS U9279 ( .A(n8227), .B(n375), .Y(n7527) );
OAI22X1TS U9280 ( .A0(n7527), .A1(n378), .B0(n178), .B1(n441), .Y(n7419) );
OAI22X1TS U9281 ( .A0(n411), .A1(n7411), .B0(n7410), .B1(n612), .Y(n7463) );
XNOR2X1TS U9282 ( .A(n8228), .B(n433), .Y(n7513) );
XNOR2X1TS U9283 ( .A(n8311), .B(n433), .Y(n7590) );
OAI22X1TS U9284 ( .A0(n7513), .A1(n496), .B0(n7590), .B1(n564), .Y(n7607) );
XNOR2X1TS U9285 ( .A(n437), .B(n7420), .Y(n7592) );
OAI22X1TS U9286 ( .A0(n557), .A1(n7517), .B0(n506), .B1(n7422), .Y(n7501) );
XNOR2X1TS U9287 ( .A(n8317), .B(n443), .Y(n7523) );
XNOR2X1TS U9288 ( .A(n7423), .B(n442), .Y(n7594) );
OAI22X1TS U9289 ( .A0(n7523), .A1(n615), .B0(n412), .B1(n7594), .Y(n7500) );
XNOR2X1TS U9290 ( .A(n8276), .B(n431), .Y(n7515) );
XNOR2X1TS U9291 ( .A(n8277), .B(n431), .Y(n7495) );
OAI22X1TS U9292 ( .A0(n7515), .A1(n485), .B0(n7495), .B1(n568), .Y(n7497) );
NOR2BX1TS U9293 ( .AN(n626), .B(n197), .Y(n7457) );
OAI21X2TS U9294 ( .A0(n7429), .A1(n7560), .B0(n7425), .Y(n7456) );
XNOR2X1TS U9295 ( .A(n7436), .B(n394), .Y(n7450) );
XNOR2X1TS U9296 ( .A(n7470), .B(n394), .Y(n7449) );
OAI22X1TS U9297 ( .A0(n7450), .A1(n553), .B0(n7449), .B1(n467), .Y(n7459) );
XNOR2X1TS U9298 ( .A(n7472), .B(n404), .Y(n7427) );
XNOR2X1TS U9299 ( .A(n8241), .B(n404), .Y(n7452) );
OAI22X1TS U9300 ( .A0(n7427), .A1(n457), .B0(n7452), .B1(n8255), .Y(n7462)
);
OAI22X1TS U9301 ( .A0(n7445), .A1(n8237), .B0(n7432), .B1(n551), .Y(n7461)
);
XNOR2X1TS U9302 ( .A(n7447), .B(n381), .Y(n7431) );
XNOR2X1TS U9303 ( .A(n7467), .B(n381), .Y(n7428) );
OAI22X1TS U9304 ( .A0(n7431), .A1(n548), .B0(n7428), .B1(n8426), .Y(n7460)
);
XNOR2X1TS U9305 ( .A(n7436), .B(n405), .Y(n7471) );
OAI22X1TS U9306 ( .A0(n7427), .A1(n8255), .B0(n7471), .B1(n458), .Y(n7478)
);
XNOR2X1TS U9307 ( .A(n8241), .B(n381), .Y(n7473) );
XNOR2X1TS U9308 ( .A(n7485), .B(n2653), .Y(n7434) );
XNOR2X1TS U9309 ( .A(n8428), .B(n389), .Y(n7469) );
OAI22X1TS U9310 ( .A0(n7434), .A1(n545), .B0(n7469), .B1(n8243), .Y(n7476)
);
XNOR2X1TS U9311 ( .A(n7485), .B(n139), .Y(n7559) );
OAI22X1TS U9312 ( .A0(n7559), .A1(n352), .B0(n7429), .B1(n360), .Y(n7554) );
XNOR2X1TS U9313 ( .A(n626), .B(n380), .Y(n7430) );
OAI22X1TS U9314 ( .A0(n7431), .A1(n462), .B0(n7430), .B1(n548), .Y(n7553) );
XNOR2X1TS U9315 ( .A(n7474), .B(n362), .Y(n7438) );
OAI22X1TS U9316 ( .A0(n7433), .A1(n463), .B0(n7438), .B1(n547), .Y(n7552) );
XNOR2X1TS U9317 ( .A(n7487), .B(n361), .Y(n7446) );
OAI22X1TS U9318 ( .A0(n7433), .A1(n547), .B0(n7446), .B1(n8233), .Y(n7443)
);
XNOR2X1TS U9319 ( .A(n7550), .B(n2653), .Y(n7435) );
OAI22X1TS U9320 ( .A0(n7435), .A1(n545), .B0(n7434), .B1(n271), .Y(n7442) );
XNOR2X1TS U9321 ( .A(n7487), .B(n389), .Y(n7562) );
OAI22X1TS U9322 ( .A0(n7562), .A1(n545), .B0(n7435), .B1(n271), .Y(n7534) );
XNOR2X1TS U9323 ( .A(n7436), .B(n393), .Y(n7535) );
NOR2BX1TS U9324 ( .AN(n625), .B(n462), .Y(n7565) );
OAI22X1TS U9325 ( .A0(n7438), .A1(n463), .B0(n7440), .B1(n546), .Y(n7564) );
XNOR2X1TS U9326 ( .A(n7472), .B(n395), .Y(n7451) );
XNOR2X1TS U9327 ( .A(n8241), .B(n394), .Y(n7545) );
OAI22X1TS U9328 ( .A0(n7451), .A1(n467), .B0(n7545), .B1(n8259), .Y(n7544)
);
XNOR2X1TS U9329 ( .A(n7447), .B(n404), .Y(n7539) );
OAI22X1TS U9330 ( .A0(n7439), .A1(n457), .B0(n8255), .B1(n201), .Y(n7541) );
XNOR2X1TS U9331 ( .A(n753), .B(n393), .Y(n7488) );
OAI22X1TS U9332 ( .A0(n7488), .A1(n465), .B0(n7445), .B1(n552), .Y(n7484) );
OAI22X1TS U9333 ( .A0(n7446), .A1(n547), .B0(n7486), .B1(n463), .Y(n7483) );
NOR2X1TS U9334 ( .A(n7448), .B(n453), .Y(n7490) );
OAI22X1TS U9335 ( .A0(n7449), .A1(n8259), .B0(n7475), .B1(n466), .Y(n7489)
);
OAI22X1TS U9336 ( .A0(n7451), .A1(n8259), .B0(n7450), .B1(n467), .Y(n7557)
);
XOR2X4TS U9337 ( .A(n7459), .B(n7458), .Y(n7599) );
OAI22X1TS U9338 ( .A0(n8575), .A1(n614), .B0(n7466), .B1(n412), .Y(n8627) );
OAI22X1TS U9339 ( .A0(n7514), .A1(n568), .B0(n8310), .B1(n485), .Y(n8626) );
INVX2TS U9340 ( .A(n7467), .Y(n7468) );
NOR2X1TS U9341 ( .A(n7468), .B(n453), .Y(n8249) );
XNOR2X2TS U9342 ( .A(n7472), .B(n380), .Y(n8258) );
XNOR2X1TS U9343 ( .A(n7474), .B(n395), .Y(n8260) );
OAI22X1TS U9344 ( .A0(n8260), .A1(n466), .B0(n7475), .B1(n8259), .Y(n8250)
);
OAI22X1TS U9345 ( .A0(n7486), .A1(n546), .B0(n8236), .B1(n463), .Y(n8288) );
XNOR2X1TS U9346 ( .A(n7487), .B(n393), .Y(n8240) );
INVX2TS U9347 ( .A(n8831), .Y(n8638) );
XNOR2X1TS U9348 ( .A(n8228), .B(n431), .Y(n7642) );
OAI22X1TS U9349 ( .A0(n7642), .A1(n567), .B0(n7495), .B1(n485), .Y(n7644) );
XNOR2X1TS U9350 ( .A(n8276), .B(n375), .Y(n7669) );
OAI22X1TS U9351 ( .A0(n7669), .A1(n378), .B0(n7528), .B1(n441), .Y(n7667) );
XNOR2X1TS U9352 ( .A(n439), .B(n7507), .Y(n7521) );
OAI22X1TS U9353 ( .A0(n559), .A1(n7508), .B0(n470), .B1(n7521), .Y(n7670) );
OAI2BB1X1TS U9354 ( .A0N(n7671), .A1N(n7670), .B0(n7509), .Y(n7666) );
INVX2TS U9355 ( .A(n8829), .Y(n7612) );
XNOR2X1TS U9356 ( .A(n8277), .B(n433), .Y(n7616) );
OAI22X1TS U9357 ( .A0(n7513), .A1(n565), .B0(n7616), .B1(n496), .Y(n7615) );
OAI22X1TS U9358 ( .A0(n7515), .A1(n567), .B0(n7514), .B1(n485), .Y(n7614) );
XNOR2X1TS U9359 ( .A(n359), .B(n633), .Y(n7519) );
OAI22X1TS U9360 ( .A0(n557), .A1(n7519), .B0(n506), .B1(n7518), .Y(n7589) );
OAI22X1TS U9361 ( .A0(n7524), .A1(n615), .B0(n7523), .B1(n413), .Y(n7530) );
NAND2X1TS U9362 ( .A(n7525), .B(n7530), .Y(n7526) );
OAI2BB1X1TS U9363 ( .A0N(n7529), .A1N(n7531), .B0(n7526), .Y(n7613) );
OAI22X1TS U9364 ( .A0(n7528), .A1(n378), .B0(n7527), .B1(n441), .Y(n7569) );
OAI22X1TS U9365 ( .A0(n7536), .A1(n552), .B0(n7535), .B1(n465), .Y(n7584) );
XNOR2X1TS U9366 ( .A(n627), .B(n404), .Y(n7538) );
OAI22X1TS U9367 ( .A0(n7539), .A1(n458), .B0(n7538), .B1(n8255), .Y(n7583)
);
OAI22X1TS U9368 ( .A0(n7546), .A1(n553), .B0(n7545), .B1(n466), .Y(n7656) );
XNOR2X1TS U9369 ( .A(n7547), .B(n2653), .Y(n7563) );
OAI22X1TS U9370 ( .A0(n7563), .A1(n8243), .B0(n7548), .B1(n8244), .Y(n7655)
);
XNOR2X1TS U9371 ( .A(n7550), .B(n139), .Y(n7561) );
OAI22X1TS U9372 ( .A0(n7551), .A1(n352), .B0(n7561), .B1(n360), .Y(n7654) );
OAI22X1TS U9373 ( .A0(n7561), .A1(n352), .B0(n7559), .B1(n360), .Y(n7575) );
OAI22X1TS U9374 ( .A0(n7563), .A1(n545), .B0(n7562), .B1(n271), .Y(n7574) );
INVX2TS U9375 ( .A(n8814), .Y(n7567) );
CLKINVX3TS U9376 ( .A(n8805), .Y(n7679) );
ADDFHX1TS U9377 ( .A(n7578), .B(n7577), .CI(n7576), .CO(n7662), .S(n7658) );
CMPR32X2TS U9378 ( .A(n7581), .B(n7580), .C(n7579), .CO(n7661), .S(n7827) );
INVX2TS U9379 ( .A(n8804), .Y(n7678) );
XNOR2X1TS U9380 ( .A(n8225), .B(n433), .Y(n7638) );
OAI22X1TS U9381 ( .A0(n7638), .A1(n565), .B0(n7590), .B1(n496), .Y(n7596) );
XNOR2X1TS U9382 ( .A(n437), .B(n7591), .Y(n7648) );
NOR2BX1TS U9383 ( .AN(n2751), .B(n507), .Y(n7640) );
OAI22X1TS U9384 ( .A0(n412), .A1(n7650), .B0(n7594), .B1(n614), .Y(n7639) );
XNOR2X1TS U9385 ( .A(n8276), .B(n433), .Y(n8578) );
OAI22X1TS U9386 ( .A0(n8578), .A1(n496), .B0(n7616), .B1(n564), .Y(n8608) );
INVX2TS U9387 ( .A(n7625), .Y(n7626) );
XNOR2X1TS U9388 ( .A(n8317), .B(n433), .Y(n7653) );
OAI22X1TS U9389 ( .A0(n7638), .A1(n496), .B0(n7653), .B1(n565), .Y(n7865) );
ADDFHX2TS U9390 ( .A(n7641), .B(n7640), .CI(n7639), .CO(n7595), .S(n7864) );
XNOR2X1TS U9391 ( .A(n8311), .B(n431), .Y(n7823) );
OAI22X1TS U9392 ( .A0(n7642), .A1(n485), .B0(n7823), .B1(n567), .Y(n7863) );
INVX2TS U9393 ( .A(n7646), .Y(n7850) );
XNOR2X1TS U9394 ( .A(n438), .B(n2751), .Y(n7649) );
OAI22X1TS U9395 ( .A0(n7653), .A1(n496), .B0(n7652), .B1(n565), .Y(n7831) );
CMPR32X2TS U9396 ( .A(n7656), .B(n7655), .C(n7654), .CO(n7585), .S(n7809) );
XNOR2X1TS U9397 ( .A(n8277), .B(n376), .Y(n7829) );
OAI22X1TS U9398 ( .A0(n7669), .A1(n441), .B0(n7829), .B1(n378), .Y(n7853) );
XOR2X4TS U9399 ( .A(n7673), .B(n7672), .Y(n7852) );
INVX2TS U9400 ( .A(n8803), .Y(n7851) );
ADDFHX2TS U9401 ( .A(n7682), .B(n7681), .CI(n7680), .CO(n8764), .S(n8875) );
INVX2TS U9402 ( .A(DP_OP_59J6_122_190_n209), .Y(DP_OP_59J6_122_190_n309) );
NAND2X1TS U9403 ( .A(n7684), .B(n7683), .Y(n7685) );
XNOR2X1TS U9404 ( .A(n7686), .B(n7685), .Y(EVEN1_Q_left[18]) );
AOI21X1TS U9405 ( .A0(n9434), .A1(n7688), .B0(n7687), .Y(n7693) );
NAND2X1TS U9406 ( .A(n7691), .B(n7690), .Y(n7692) );
XOR2X1TS U9407 ( .A(n7693), .B(n7692), .Y(n9060) );
XOR2X1TS U9408 ( .A(n7698), .B(n7697), .Y(n11233) );
NAND2X1TS U9409 ( .A(n7707), .B(n7706), .Y(n7708) );
NAND2X1TS U9410 ( .A(n7710), .B(n7709), .Y(n7711) );
AOI21X1TS U9411 ( .A0(n9434), .A1(n8151), .B0(n7713), .Y(n7718) );
NAND2X1TS U9412 ( .A(n7716), .B(n7715), .Y(n7717) );
ADDFHX2TS U9413 ( .A(n7721), .B(n7720), .CI(n7719), .CO(n9059), .S(n9064) );
INVX2TS U9414 ( .A(n7766), .Y(n7723) );
NOR2X1TS U9415 ( .A(n9631), .B(n7723), .Y(n7725) );
AO21X1TS U9416 ( .A0(n770), .A1(n7736), .B0(n623), .Y(n7774) );
INVX2TS U9417 ( .A(n7781), .Y(n7742) );
CMPR32X2TS U9418 ( .A(n7740), .B(n7739), .C(n7738), .CO(n7782), .S(n8033) );
INVX2TS U9419 ( .A(n7782), .Y(n7741) );
XOR2X1TS U9420 ( .A(n7742), .B(n7741), .Y(n8043) );
OAI22X1TS U9421 ( .A0(n7743), .A1(n7780), .B0(n490), .B1(n7778), .Y(n7773)
);
NAND2X1TS U9422 ( .A(n7745), .B(n8033), .Y(n7772) );
CMPR32X2TS U9423 ( .A(n7748), .B(n7747), .C(n7746), .CO(n7784), .S(n7751) );
NAND2X1TS U9424 ( .A(n7759), .B(n7754), .Y(n7790) );
AOI21X1TS U9425 ( .A0(n7759), .A1(n7758), .B0(n7757), .Y(n7793) );
NAND2X1TS U9426 ( .A(n7762), .B(n7761), .Y(n7791) );
NAND2X1TS U9427 ( .A(n7763), .B(n7791), .Y(n7764) );
XNOR2X1TS U9428 ( .A(n7765), .B(n7764), .Y(n8385) );
CMPR32X2TS U9429 ( .A(n8043), .B(n7773), .C(n7772), .CO(n7956), .S(n7785) );
CMPR32X2TS U9430 ( .A(n7776), .B(n7775), .C(n7774), .CO(n7777), .S(n7781) );
INVX2TS U9431 ( .A(n7777), .Y(n7958) );
CMPR32X2TS U9432 ( .A(n7786), .B(n7785), .C(n7784), .CO(n7954), .S(n7770) );
NAND2X1TS U9433 ( .A(n7788), .B(n7787), .Y(n7946) );
NAND2X1TS U9434 ( .A(n7948), .B(n7946), .Y(n7789) );
AOI21X1TS U9435 ( .A0(n7796), .A1(n7795), .B0(n7794), .Y(n9572) );
INVX2TS U9436 ( .A(n9572), .Y(n9556) );
NAND2X1TS U9437 ( .A(n7798), .B(n7797), .Y(n8194) );
NAND2X1TS U9438 ( .A(n7967), .B(n8194), .Y(n7799) );
XNOR2X1TS U9439 ( .A(n9556), .B(n7799), .Y(n7800) );
NOR2X2TS U9440 ( .A(n7801), .B(n7800), .Y(n9695) );
INVX2TS U9441 ( .A(n9695), .Y(n9658) );
NAND2X1TS U9442 ( .A(n7801), .B(n7800), .Y(n9657) );
INVX2TS U9443 ( .A(n8798), .Y(n7856) );
OAI22X1TS U9444 ( .A0(n7824), .A1(n568), .B0(n7823), .B1(n485), .Y(n7859) );
INVX2TS U9445 ( .A(n8797), .Y(n7857) );
OAI22X1TS U9446 ( .A0(n7830), .A1(n377), .B0(n7829), .B1(n441), .Y(n7847) );
ADDFHX2TS U9447 ( .A(n7833), .B(n7832), .CI(n7831), .CO(n7849), .S(n7846) );
INVX2TS U9448 ( .A(n7940), .Y(n8771) );
NAND2X1TS U9449 ( .A(n7874), .B(n7872), .Y(n7877) );
NAND2X1TS U9450 ( .A(n7874), .B(n7873), .Y(n7875) );
NAND3X1TS U9451 ( .A(n7877), .B(n7876), .C(n7875), .Y(n7878) );
OR2X4TS U9452 ( .A(n7879), .B(n7878), .Y(n8770) );
ADDFHX2TS U9453 ( .A(n7891), .B(n7892), .CI(n7890), .CO(n7902), .S(n7933) );
ADDFHX2TS U9454 ( .A(n7895), .B(n7894), .CI(n7893), .CO(n8876), .S(n8878) );
NOR2X1TS U9455 ( .A(n9448), .B(n7908), .Y(n7910) );
NAND2X1TS U9456 ( .A(n1713), .B(n7917), .Y(n7918) );
XNOR2X1TS U9457 ( .A(n7919), .B(n7918), .Y(n8499) );
NOR2X1TS U9458 ( .A(n9448), .B(n7920), .Y(n7922) );
NAND2X1TS U9459 ( .A(n7924), .B(n7923), .Y(n7925) );
NAND2X1TS U9460 ( .A(n7928), .B(n7927), .Y(n7929) );
NOR2X2TS U9461 ( .A(n8498), .B(n8497), .Y(n8683) );
OR2X4TS U9462 ( .A(n8677), .B(n8683), .Y(n8684) );
NAND2X2TS U9463 ( .A(n7937), .B(n7936), .Y(n8900) );
INVX2TS U9464 ( .A(n8900), .Y(n7938) );
AOI21X4TS U9465 ( .A0(n8901), .A1(n8769), .B0(n7938), .Y(n7939) );
INVX2TS U9466 ( .A(n7942), .Y(n7945) );
INVX2TS U9467 ( .A(n8187), .Y(n7953) );
CMPR32X2TS U9468 ( .A(n7956), .B(n7955), .C(n7954), .CO(n7965), .S(n7787) );
CMPR32X2TS U9469 ( .A(n7961), .B(n7960), .C(n7959), .CO(n7962), .S(n7955) );
AOI21X1TS U9470 ( .A0(n9556), .A1(n7967), .B0(n7966), .Y(n7972) );
NAND2X1TS U9471 ( .A(n7969), .B(n7968), .Y(n8193) );
NAND2X1TS U9472 ( .A(n7970), .B(n8193), .Y(n7971) );
NAND2X1TS U9473 ( .A(n7984), .B(n7983), .Y(n7986) );
NAND2X1TS U9474 ( .A(n7991), .B(n7990), .Y(n7993) );
INVX2TS U9475 ( .A(n11198), .Y(n8662) );
INVX2TS U9476 ( .A(EVEN1_Q_left[3]), .Y(n8661) );
NAND2X1TS U9477 ( .A(n8001), .B(n8000), .Y(n8670) );
NAND2X1TS U9478 ( .A(n8673), .B(n8670), .Y(n8005) );
XNOR2X1TS U9479 ( .A(n8005), .B(n8672), .Y(n9548) );
CLKINVX1TS U9480 ( .A(n8010), .Y(n8012) );
NOR2X2TS U9481 ( .A(n8074), .B(n8073), .Y(n9361) );
NAND2X1TS U9482 ( .A(n8025), .B(n8024), .Y(n8026) );
XOR2X4TS U9483 ( .A(n8027), .B(n8026), .Y(n8070) );
NAND2X1TS U9484 ( .A(n8053), .B(n8062), .Y(n8038) );
OR2X2TS U9485 ( .A(n8038), .B(n8029), .Y(n8040) );
NAND2X1TS U9486 ( .A(n8034), .B(n8033), .Y(n8061) );
AOI21X1TS U9487 ( .A0(n8052), .A1(n8062), .B0(n8035), .Y(n8036) );
OA21XLTS U9488 ( .A0(n8038), .A1(n8037), .B0(n8036), .Y(n8039) );
AOI21X1TS U9489 ( .A0(n8060), .A1(n8042), .B0(n8041), .Y(n8045) );
NAND2X1TS U9490 ( .A(n8050), .B(n8053), .Y(n8056) );
AOI21X1TS U9491 ( .A0(n8054), .A1(n8053), .B0(n8052), .Y(n8055) );
AOI21X1TS U9492 ( .A0(n8060), .A1(n8059), .B0(n8058), .Y(n8064) );
NAND2X1TS U9493 ( .A(n8062), .B(n8061), .Y(n8063) );
NAND2X1TS U9494 ( .A(n8080), .B(n8079), .Y(n8082) );
XNOR2X1TS U9495 ( .A(n8082), .B(n8081), .Y(n8094) );
INVX4TS U9496 ( .A(n8083), .Y(n8507) );
XNOR2X4TS U9497 ( .A(n8507), .B(n8086), .Y(n8093) );
NAND2X1TS U9498 ( .A(n8089), .B(n8088), .Y(n8091) );
OR2X4TS U9499 ( .A(n8093), .B(n8092), .Y(n9539) );
INVX2TS U9500 ( .A(n8104), .Y(n9538) );
AOI21X4TS U9501 ( .A0(n8507), .A1(n8501), .B0(n8505), .Y(n8097) );
NAND2X1TS U9502 ( .A(n8095), .B(n8504), .Y(n8096) );
NAND2X1TS U9503 ( .A(n8100), .B(n8099), .Y(n8102) );
XOR2X1TS U9504 ( .A(n8102), .B(n8101), .Y(n8103) );
NAND2X1TS U9505 ( .A(n8104), .B(n9539), .Y(n8105) );
NAND2X1TS U9506 ( .A(n8115), .B(n8114), .Y(n8117) );
XNOR2X1TS U9507 ( .A(n8117), .B(n8116), .Y(n8118) );
NAND2X1TS U9508 ( .A(n8537), .B(n8534), .Y(n8121) );
AOI2BB1X4TS U9509 ( .A0N(n8120), .A1N(n8121), .B0(n1712), .Y(n9514) );
NAND2X1TS U9510 ( .A(n8124), .B(n8123), .Y(n8126) );
NAND2X1TS U9511 ( .A(n9512), .B(n9483), .Y(n8129) );
XNOR2X1TS U9512 ( .A(n8135), .B(n8134), .Y(EVEN1_Q_left[17]) );
NAND2X1TS U9513 ( .A(n8138), .B(n8137), .Y(n8139) );
XOR2X1TS U9514 ( .A(n8140), .B(n8139), .Y(EVEN1_Q_left[16]) );
NAND2X1TS U9515 ( .A(n8142), .B(n8141), .Y(n8144) );
XNOR2X1TS U9516 ( .A(n8144), .B(n8143), .Y(n8178) );
NAND2X1TS U9517 ( .A(n8148), .B(n8147), .Y(n8149) );
INVX2TS U9518 ( .A(n11228), .Y(n8177) );
INVX2TS U9519 ( .A(EVEN1_Q_left[17]), .Y(n8176) );
NAND2X1TS U9520 ( .A(n8151), .B(n8150), .Y(n8152) );
NAND2X1TS U9521 ( .A(n8158), .B(n8157), .Y(n8160) );
XOR2X1TS U9522 ( .A(n8160), .B(n8159), .Y(n9322) );
INVX2TS U9523 ( .A(n8161), .Y(n8163) );
NOR2X1TS U9524 ( .A(n8166), .B(n9315), .Y(n8170) );
OAI21X1TS U9525 ( .A0(n8168), .A1(n9315), .B0(n9316), .Y(n8169) );
CLKINVX1TS U9526 ( .A(n8171), .Y(n8173) );
NAND2X1TS U9527 ( .A(n8173), .B(n8172), .Y(n8174) );
NAND2X1TS U9528 ( .A(n11389), .B(n9063), .Y(DP_OP_62J6_125_4796_n40) );
NOR2X1TS U9529 ( .A(n8184), .B(n1719), .Y(n8185) );
AOI21X1TS U9530 ( .A0(n9556), .A1(n9564), .B0(n9569), .Y(n8200) );
NAND2X1TS U9531 ( .A(n8197), .B(n8196), .Y(n9566) );
NAND2X1TS U9532 ( .A(n8198), .B(n9566), .Y(n8199) );
NAND2BX4TS U9533 ( .AN(n9666), .B(n8203), .Y(n8709) );
INVX2TS U9534 ( .A(n8709), .Y(add_x_2_n171) );
NAND2X1TS U9535 ( .A(n8204), .B(n8206), .Y(n8209) );
NOR2X1TS U9536 ( .A(n9448), .B(n8209), .Y(n8210) );
AOI21X1TS U9537 ( .A0(n8207), .A1(n8206), .B0(n8205), .Y(n8208) );
NAND2X1TS U9538 ( .A(n6603), .B(n8211), .Y(n8212) );
XNOR2X1TS U9539 ( .A(n8217), .B(n8216), .Y(n8218) );
OAI22X1TS U9540 ( .A0(n8318), .A1(n410), .B0(n8226), .B1(n612), .Y(n8232) );
OAI22X1TS U9541 ( .A0(n8326), .A1(n560), .B0(n8229), .B1(n470), .Y(n8230) );
OAI22X1TS U9542 ( .A0(n8236), .A1(n547), .B0(n8234), .B1(n463), .Y(n8291) );
NOR2X1TS U9543 ( .A(n8242), .B(n453), .Y(n8263) );
AO21X2TS U9544 ( .A0(n8244), .A1(n271), .B0(n388), .Y(n8262) );
OAI22X1TS U9545 ( .A0(n8256), .A1(n8255), .B0(n8254), .B1(n457), .Y(n8266)
);
OAI22X1TS U9546 ( .A0(n8261), .A1(n467), .B0(n8260), .B1(n553), .Y(n8264) );
ADDFHX2TS U9547 ( .A(n353), .B(n8263), .CI(n8262), .CO(n8285), .S(n8289) );
XNOR2X1TS U9548 ( .A(n8276), .B(n443), .Y(n8316) );
OAI22X1TS U9549 ( .A0(n8576), .A1(n564), .B0(n497), .B1(n8279), .Y(n8600) );
INVX2TS U9550 ( .A(n8923), .Y(n8351) );
ADDFHX1TS U9551 ( .A(n8288), .B(n8287), .CI(n8286), .CO(n8590), .S(n8592) );
INVX2TS U9552 ( .A(n8920), .Y(n8350) );
INVX2TS U9553 ( .A(n8304), .Y(n8331) );
OAI22X1TS U9554 ( .A0(n8316), .A1(n412), .B0(n8315), .B1(n615), .Y(n8330) );
XNOR2X1TS U9555 ( .A(n8317), .B(n437), .Y(n8324) );
OAI22X1TS U9556 ( .A0(n8855), .A1(n824), .B0(n369), .B1(n823), .Y(n8572) );
OAI22X1TS U9557 ( .A0(n8324), .A1(n613), .B0(n411), .B1(n8321), .Y(n8570) );
ADDFHX2TS U9558 ( .A(n8357), .B(n8356), .CI(n8355), .CO(n8362), .S(n8352) );
INVX2TS U9559 ( .A(n8540), .Y(n8368) );
NAND2X1TS U9560 ( .A(n9458), .B(n8377), .Y(n8378) );
XNOR2X1TS U9561 ( .A(n9459), .B(n8378), .Y(n9446) );
NAND2X2TS U9562 ( .A(n9447), .B(n9446), .Y(add_x_3_n169) );
NOR2X2TS U9563 ( .A(n9656), .B(n9655), .Y(n9629) );
INVX2TS U9564 ( .A(add_x_2_n143), .Y(n8387) );
NOR2X2TS U9565 ( .A(n8387), .B(add_x_2_n138), .Y(add_x_2_n136) );
INVX2TS U9566 ( .A(n8388), .Y(n8392) );
XNOR2X4TS U9567 ( .A(n8392), .B(n8391), .Y(EVEN1_Q_left[26]) );
NAND2X1TS U9568 ( .A(n8394), .B(n8710), .Y(n8399) );
AOI21X1TS U9569 ( .A0(n8397), .A1(n8710), .B0(n8715), .Y(n8398) );
OAI21X1TS U9570 ( .A0(n9431), .A1(n8399), .B0(n8398), .Y(n8400) );
AOI21X1TS U9571 ( .A0(n9434), .A1(n8401), .B0(n8400), .Y(n8405) );
NAND2X1TS U9572 ( .A(n8403), .B(n8402), .Y(n8712) );
NAND2X1TS U9573 ( .A(n8714), .B(n8712), .Y(n8404) );
XOR2X1TS U9574 ( .A(n8405), .B(n8404), .Y(n8413) );
INVX2TS U9575 ( .A(n8406), .Y(n8410) );
XNOR2X4TS U9576 ( .A(n8410), .B(n8409), .Y(n10815) );
INVX2TS U9577 ( .A(n10815), .Y(n8411) );
ADDFHX2TS U9578 ( .A(n8413), .B(n8412), .CI(n8411), .CO(
DP_OP_62J6_125_4796_n542), .S(DP_OP_62J6_125_4796_n543) );
CMPR32X2TS U9579 ( .A(n8422), .B(n8421), .C(n8420), .CO(n9398), .S(n8942) );
INVX2TS U9580 ( .A(n9398), .Y(n8463) );
NOR2X1TS U9581 ( .A(n436), .B(n141), .Y(n8453) );
INVX2TS U9582 ( .A(n8723), .Y(n8458) );
OAI22X1TS U9583 ( .A0(n8435), .A1(n557), .B0(n507), .B1(n7517), .Y(n8449) );
OAI22X1TS U9584 ( .A0(n8436), .A1(n537), .B0(n8451), .B1(n369), .Y(n8448) );
ADDFHX2TS U9585 ( .A(n8443), .B(n8442), .CI(n8441), .CO(n8444), .S(n8416) );
INVX2TS U9586 ( .A(n8887), .Y(DP_OP_59J6_122_190_n103) );
CMPR32X2TS U9587 ( .A(n8446), .B(n8445), .C(n8444), .CO(n8468), .S(n8885) );
OAI22X1TS U9588 ( .A0(n8451), .A1(n537), .B0(n8856), .B1(n369), .Y(n8866) );
INVX2TS U9589 ( .A(n8455), .Y(n8858) );
AO21X1TS U9590 ( .A0(n556), .A1(n506), .B0(n7517), .Y(n8861) );
OR2X4TS U9591 ( .A(n8468), .B(n8467), .Y(n8910) );
NAND2X1TS U9592 ( .A(n8468), .B(n8467), .Y(n8823) );
INVX2TS U9593 ( .A(add_x_3_n122), .Y(n8472) );
NAND2X1TS U9594 ( .A(n8475), .B(n8474), .Y(n8476) );
XOR2X1TS U9595 ( .A(n8477), .B(n8476), .Y(EVEN1_Q_left[24]) );
OAI21X1TS U9596 ( .A0(n9431), .A1(n8711), .B0(n8717), .Y(n8478) );
AOI21X1TS U9597 ( .A0(n9434), .A1(n8479), .B0(n8478), .Y(n8483) );
NAND2X1TS U9598 ( .A(n8481), .B(n8480), .Y(n8482) );
NAND2X1TS U9599 ( .A(n8486), .B(n8485), .Y(n8487) );
XOR2X1TS U9600 ( .A(n8488), .B(n8487), .Y(n10813) );
INVX2TS U9601 ( .A(n10813), .Y(n8490) );
NAND2X1TS U9602 ( .A(n8493), .B(n8492), .Y(n9056) );
NAND2BX2TS U9603 ( .AN(n8496), .B(n8495), .Y(add_x_2_n10) );
NOR2X2TS U9604 ( .A(n8502), .B(n8503), .Y(n8508) );
AOI21X4TS U9605 ( .A0(n8507), .A1(n8508), .B0(n8506), .Y(n8513) );
XOR2X4TS U9606 ( .A(n8513), .B(n8512), .Y(n8527) );
NAND2X1TS U9607 ( .A(n8515), .B(n8514), .Y(n8517) );
XNOR2X1TS U9608 ( .A(n8517), .B(n8516), .Y(n8526) );
OR2X8TS U9609 ( .A(n8527), .B(n8526), .Y(n9665) );
NAND2X2TS U9610 ( .A(n9665), .B(n8565), .Y(n9671) );
NAND2X1TS U9611 ( .A(n8520), .B(n8519), .Y(n8521) );
NAND2X1TS U9612 ( .A(n8523), .B(n8522), .Y(n8525) );
XNOR2X1TS U9613 ( .A(n8525), .B(n8524), .Y(n8529) );
NAND2X2TS U9614 ( .A(n8527), .B(n8526), .Y(n9664) );
NAND2X1TS U9615 ( .A(n8537), .B(n8536), .Y(n8538) );
INVX2TS U9616 ( .A(EVEN1_Q_right[31]), .Y(DP_OP_62J6_125_4796_n640) );
XOR2X4TS U9617 ( .A(n8546), .B(n8545), .Y(n9443) );
NAND2X1TS U9618 ( .A(n8548), .B(n8547), .Y(n8549) );
XNOR2X1TS U9619 ( .A(n8550), .B(n8549), .Y(n9442) );
XOR2X4TS U9620 ( .A(n8556), .B(n8555), .Y(n9445) );
AOI21X1TS U9621 ( .A0(n8559), .A1(n8558), .B0(n8557), .Y(n8563) );
NAND2X1TS U9622 ( .A(n8561), .B(n8560), .Y(n8562) );
NAND2X1TS U9623 ( .A(n8565), .B(n8564), .Y(n8566) );
INVX2TS U9624 ( .A(n8840), .Y(n8697) );
ADDFHX2TS U9625 ( .A(n8587), .B(n8586), .CI(n8585), .CO(n8295), .S(n8599) );
CMPR32X2TS U9626 ( .A(n8602), .B(n8601), .C(n8600), .CO(n8700), .S(n8703) );
ADDFHX2TS U9627 ( .A(n8613), .B(n8612), .CI(n8611), .CO(n8629), .S(n8616) );
ADDFHX2TS U9628 ( .A(n8628), .B(n8627), .CI(n8626), .CO(n8636), .S(n8639) );
NAND2X1TS U9629 ( .A(n8652), .B(n8651), .Y(n8654) );
NAND2X1TS U9630 ( .A(n8657), .B(n8656), .Y(n8659) );
INVX2TS U9631 ( .A(n11202), .Y(n9203) );
INVX2TS U9632 ( .A(EVEN1_Q_left[4]), .Y(n9202) );
NAND2X1TS U9633 ( .A(n8664), .B(n8663), .Y(n8666) );
XNOR2X1TS U9634 ( .A(n8666), .B(n8665), .Y(n8667) );
NAND2X1TS U9635 ( .A(n8668), .B(n8667), .Y(n9228) );
NAND2X1TS U9636 ( .A(n8669), .B(n9228), .Y(n8674) );
AOI21X1TS U9637 ( .A0(n8673), .A1(n8672), .B0(n8671), .Y(n9230) );
NAND2X1TS U9638 ( .A(n8681), .B(n8680), .Y(DP_OP_59J6_122_190_n192) );
INVX2TS U9639 ( .A(n8683), .Y(add_x_3_n303) );
NOR2X2TS U9640 ( .A(n8759), .B(n8758), .Y(DP_OP_59J6_122_190_n182) );
NOR2X2TS U9641 ( .A(DP_OP_59J6_122_190_n182), .B(DP_OP_59J6_122_190_n187),
.Y(DP_OP_59J6_122_190_n180) );
NOR2X2TS U9642 ( .A(n8709), .B(add_x_2_n166), .Y(add_x_2_n164) );
NAND2X1TS U9643 ( .A(n8710), .B(n8714), .Y(n8718) );
AOI21X1TS U9644 ( .A0(n8715), .A1(n8714), .B0(n8713), .Y(n8716) );
OA21XLTS U9645 ( .A0(n8718), .A1(n8717), .B0(n8716), .Y(n8719) );
OAI21X1TS U9646 ( .A0(n9431), .A1(n8720), .B0(n8719), .Y(n8721) );
AOI21X1TS U9647 ( .A0(n9434), .A1(n8722), .B0(n8721), .Y(n8728) );
NAND2X1TS U9648 ( .A(n8724), .B(n8723), .Y(n8725) );
NAND2X1TS U9649 ( .A(n8726), .B(n8725), .Y(n8727) );
XOR2X1TS U9650 ( .A(n8728), .B(n8727), .Y(n8731) );
ADDFHX2TS U9651 ( .A(n8731), .B(n8730), .CI(n8729), .CO(
DP_OP_62J6_125_4796_n538), .S(DP_OP_62J6_125_4796_n539) );
ADDFHX2TS U9652 ( .A(n8737), .B(n8736), .CI(n8735), .CO(n8748), .S(n8738) );
NOR2X4TS U9653 ( .A(n8755), .B(n8754), .Y(DP_OP_59J6_122_190_n166) );
ADDFHX2TS U9654 ( .A(n8751), .B(n8750), .CI(n8749), .CO(n8752), .S(n8759) );
INVX2TS U9655 ( .A(n9058), .Y(DP_OP_59J6_122_190_n305) );
NAND2X1TS U9656 ( .A(n8755), .B(n8754), .Y(DP_OP_59J6_122_190_n167) );
INVX2TS U9657 ( .A(DP_OP_59J6_122_190_n166), .Y(n8756) );
NAND2X1TS U9658 ( .A(n8888), .B(n8757), .Y(DP_OP_59J6_122_190_n122) );
NAND2X1TS U9659 ( .A(n8759), .B(n8758), .Y(DP_OP_59J6_122_190_n183) );
NAND2X1TS U9660 ( .A(n8899), .B(n8898), .Y(DP_OP_59J6_122_190_n201) );
NAND2X1TS U9661 ( .A(DP_OP_59J6_122_190_n309), .B(DP_OP_59J6_122_190_n210),
.Y(DP_OP_59J6_122_190_n62) );
NAND2X1TS U9662 ( .A(n8768), .B(DP_OP_59J6_122_190_n223), .Y(
DP_OP_59J6_122_190_n64) );
AOI21X1TS U9663 ( .A0(n8771), .A1(n8770), .B0(n8769), .Y(
DP_OP_59J6_122_190_n232) );
NOR2X1TS U9664 ( .A(n8789), .B(n8790), .Y(n9036) );
NAND2X1TS U9665 ( .A(n210), .B(n1706), .Y(n8788) );
NAND2X1TS U9666 ( .A(n8896), .B(n8895), .Y(n9054) );
NAND2X1TS U9667 ( .A(n8772), .B(n8773), .Y(n9052) );
AOI21X1TS U9668 ( .A0(n8890), .A1(n1688), .B0(n8776), .Y(n9049) );
NAND2X1TS U9669 ( .A(n8778), .B(n8777), .Y(n9047) );
NAND2X1TS U9670 ( .A(n8780), .B(n8779), .Y(n8844) );
AOI21X1TS U9671 ( .A0(n8846), .A1(n8845), .B0(n8781), .Y(n8849) );
NAND2X1TS U9672 ( .A(n8783), .B(n8782), .Y(n8848) );
NAND2X1TS U9673 ( .A(n8785), .B(n8784), .Y(n9043) );
AOI21X1TS U9674 ( .A0(n210), .A1(n9041), .B0(n8786), .Y(n8787) );
NAND2X1TS U9675 ( .A(n8790), .B(n8789), .Y(n9037) );
NAND2X1TS U9676 ( .A(n8792), .B(n8791), .Y(n8819) );
OAI21X1TS U9677 ( .A0(n8818), .A1(n9037), .B0(n8819), .Y(n8793) );
AOI21X1TS U9678 ( .A0(n8794), .A1(n8817), .B0(n8793), .Y(n8824) );
NAND2X1TS U9679 ( .A(n209), .B(n1687), .Y(n8801) );
NAND2X1TS U9680 ( .A(n8796), .B(n8795), .Y(n8825) );
NAND2X1TS U9681 ( .A(n8798), .B(n8797), .Y(n9033) );
AOI21X1TS U9682 ( .A0(n209), .A1(n9031), .B0(n8799), .Y(n8800) );
OAI21X1TS U9683 ( .A0(n8824), .A1(n8801), .B0(n8800), .Y(n8813) );
NOR2X1TS U9684 ( .A(n8803), .B(n8802), .Y(n9026) );
NOR2X1TS U9685 ( .A(n8804), .B(n8805), .Y(n8810) );
NAND2X1TS U9686 ( .A(n8805), .B(n8804), .Y(n8809) );
NAND2X1TS U9687 ( .A(n8806), .B(n8809), .Y(n8807) );
XNOR2X1TS U9688 ( .A(n8808), .B(n8807), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[13]) );
OAI21X1TS U9689 ( .A0(n8810), .A1(n9027), .B0(n8809), .Y(n8811) );
INVX2TS U9690 ( .A(n8837), .Y(n9020) );
NOR2X1TS U9691 ( .A(n8814), .B(n8815), .Y(n8827) );
NAND2X1TS U9692 ( .A(n8815), .B(n8814), .Y(n9010) );
NAND2X1TS U9693 ( .A(n9012), .B(n9010), .Y(n8816) );
XNOR2X1TS U9694 ( .A(n9020), .B(n8816), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[14]) );
NAND2X1TS U9695 ( .A(n8820), .B(n8819), .Y(n8821) );
XNOR2X1TS U9696 ( .A(n8822), .B(n8821), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[9]) );
NAND2X1TS U9697 ( .A(n8910), .B(n8823), .Y(DP_OP_59J6_122_190_n50) );
NAND2X1TS U9698 ( .A(n1687), .B(n8825), .Y(n8826) );
XNOR2X1TS U9699 ( .A(n9032), .B(n8826), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[10]) );
NOR2X1TS U9700 ( .A(n8829), .B(n8828), .Y(n9013) );
NOR2X1TS U9701 ( .A(n9013), .B(n8827), .Y(n9019) );
NOR2X1TS U9702 ( .A(n8831), .B(n8830), .Y(n9021) );
NOR2X1TS U9703 ( .A(n8833), .B(n8832), .Y(n9005) );
NAND2X1TS U9704 ( .A(n9019), .B(n8835), .Y(n8838) );
NAND2X1TS U9705 ( .A(n8828), .B(n8829), .Y(n9014) );
OAI21X1TS U9706 ( .A0(n9013), .A1(n9010), .B0(n9014), .Y(n9018) );
NAND2X1TS U9707 ( .A(n8831), .B(n8830), .Y(n9022) );
NAND2X1TS U9708 ( .A(n8833), .B(n8832), .Y(n9006) );
AOI21X1TS U9709 ( .A0(n9018), .A1(n8835), .B0(n8834), .Y(n8836) );
NOR2X1TS U9710 ( .A(n8840), .B(n8839), .Y(n8919) );
NAND2X1TS U9711 ( .A(n8839), .B(n8840), .Y(n8993) );
NAND2X1TS U9712 ( .A(n8995), .B(n8993), .Y(n8841) );
XNOR2X1TS U9713 ( .A(n9396), .B(n8841), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[18]) );
NAND2X1TS U9714 ( .A(n8843), .B(n8842), .Y(DP_OP_59J6_122_190_n52) );
NAND2X1TS U9715 ( .A(n8845), .B(n8844), .Y(n8847) );
XNOR2X1TS U9716 ( .A(n8847), .B(n8846), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[5]) );
NAND2X1TS U9717 ( .A(n1706), .B(n8848), .Y(n8850) );
XNOR2X1TS U9718 ( .A(n8850), .B(n9042), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[6]) );
NAND2X1TS U9719 ( .A(n8851), .B(n8757), .Y(DP_OP_59J6_122_190_n53) );
NOR2XLTS U9720 ( .A(n8856), .B(n537), .Y(n8860) );
CMPR32X2TS U9721 ( .A(n8858), .B(n227), .C(n8857), .CO(n8859), .S(n8863) );
XNOR2X1TS U9722 ( .A(n8860), .B(n8859), .Y(n8869) );
CMPR32X2TS U9723 ( .A(n8866), .B(n8865), .C(n8864), .CO(n8867), .S(n8853) );
NAND2X1TS U9724 ( .A(n8871), .B(n8870), .Y(n8872) );
NAND2X1TS U9725 ( .A(n215), .B(n8872), .Y(DP_OP_59J6_122_190_n49) );
CLKINVX1TS U9726 ( .A(n8851), .Y(n8873) );
AOI21X1TS U9727 ( .A0(n8874), .A1(n8757), .B0(n8873), .Y(
DP_OP_59J6_122_190_n123) );
NOR2X1TS U9728 ( .A(DP_OP_59J6_122_190_n222), .B(n8892), .Y(n8884) );
OAI21X1TS U9729 ( .A0(n8892), .A1(DP_OP_59J6_122_190_n223), .B0(n8893), .Y(
n8883) );
NAND2X1TS U9730 ( .A(n8887), .B(n11300), .Y(DP_OP_59J6_122_190_n51) );
NAND2X1TS U9731 ( .A(n8888), .B(DP_OP_59J6_122_190_n136), .Y(
DP_OP_59J6_122_190_n54) );
NAND2X1TS U9732 ( .A(n1688), .B(n8889), .Y(n8891) );
XNOR2X1TS U9733 ( .A(n8891), .B(n8890), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[3]) );
NAND2X1TS U9734 ( .A(n8894), .B(n8893), .Y(DP_OP_59J6_122_190_n63) );
CLKAND2X2TS U9735 ( .A(n8897), .B(n9054), .Y(
EVEN1_middle_RECURSIVE_EVEN1_Q_left[1]) );
CLKINVX1TS U9736 ( .A(DP_OP_59J6_122_190_n182), .Y(DP_OP_59J6_122_190_n306)
);
CLKINVX1TS U9737 ( .A(DP_OP_59J6_122_190_n200), .Y(DP_OP_59J6_122_190_n308)
);
NAND2X1TS U9738 ( .A(n8901), .B(n8900), .Y(DP_OP_59J6_122_190_n65) );
NAND2X1TS U9739 ( .A(n8912), .B(n8911), .Y(n8914) );
XNOR2X1TS U9740 ( .A(n8914), .B(n8913), .Y(
EVEN1_middle_RECURSIVE_EVEN1_S_B[8]) );
NOR2X1TS U9741 ( .A(n8921), .B(n8920), .Y(n8996) );
NOR2X1TS U9742 ( .A(n8919), .B(n8996), .Y(n8980) );
NOR2X1TS U9743 ( .A(n8923), .B(n8922), .Y(n8984) );
NOR2X1TS U9744 ( .A(n8925), .B(n8924), .Y(n8988) );
NAND2X1TS U9745 ( .A(n8980), .B(n8927), .Y(n9383) );
NOR2X1TS U9746 ( .A(n8929), .B(n8928), .Y(n8959) );
NAND2X1TS U9747 ( .A(n8974), .B(n1709), .Y(n9382) );
NOR2X1TS U9748 ( .A(n8946), .B(n8954), .Y(n9381) );
NAND2X1TS U9749 ( .A(n8947), .B(n9381), .Y(n8939) );
NAND2X1TS U9750 ( .A(n8921), .B(n8920), .Y(n8997) );
OAI21X1TS U9751 ( .A0(n8996), .A1(n8993), .B0(n8997), .Y(n8982) );
NAND2X1TS U9752 ( .A(n8923), .B(n8922), .Y(n8983) );
NAND2X1TS U9753 ( .A(n8925), .B(n8924), .Y(n8989) );
AOI21X1TS U9754 ( .A0(n8982), .A1(n8927), .B0(n8926), .Y(n9393) );
NAND2X1TS U9755 ( .A(n8929), .B(n8928), .Y(n8973) );
NAND2X1TS U9756 ( .A(n8931), .B(n8930), .Y(n8962) );
AOI21X1TS U9757 ( .A0(n1709), .A1(n8933), .B0(n8932), .Y(n9390) );
NAND2X1TS U9758 ( .A(n8935), .B(n8934), .Y(n8967) );
NAND2X1TS U9759 ( .A(n8937), .B(n8936), .Y(n8955) );
AOI21X1TS U9760 ( .A0(n8949), .A1(n9381), .B0(n9387), .Y(n8938) );
AOI21X1TS U9761 ( .A0(n9396), .A1(n8941), .B0(n8940), .Y(n8945) );
NAND2X1TS U9762 ( .A(n8943), .B(n8942), .Y(n9384) );
NAND2X1TS U9763 ( .A(n9386), .B(n9384), .Y(n8944) );
INVX2TS U9764 ( .A(n8946), .Y(n8968) );
NAND2X1TS U9765 ( .A(n8947), .B(n8968), .Y(n8951) );
AOI21X1TS U9766 ( .A0(n8949), .A1(n8968), .B0(n8948), .Y(n8950) );
AOI21X1TS U9767 ( .A0(n9396), .A1(n8953), .B0(n8952), .Y(n8958) );
NAND2X1TS U9768 ( .A(n8956), .B(n8955), .Y(n8957) );
AOI21X1TS U9769 ( .A0(n9396), .A1(n8961), .B0(n8960), .Y(n8964) );
NAND2X1TS U9770 ( .A(n1709), .B(n8962), .Y(n8963) );
AOI21X1TS U9771 ( .A0(n9396), .A1(n8966), .B0(n8965), .Y(n8970) );
NAND2X1TS U9772 ( .A(n8968), .B(n8967), .Y(n8969) );
AOI21X1TS U9773 ( .A0(n9396), .A1(n8972), .B0(n8971), .Y(n8976) );
NAND2X1TS U9774 ( .A(n8974), .B(n8973), .Y(n8975) );
AOI21X1TS U9775 ( .A0(n9396), .A1(n8980), .B0(n8982), .Y(n8979) );
NAND2X1TS U9776 ( .A(n8977), .B(n8983), .Y(n8978) );
CLKINVX1TS U9777 ( .A(n8982), .Y(n8985) );
AOI21X1TS U9778 ( .A0(n9396), .A1(n8987), .B0(n8986), .Y(n8992) );
NAND2X1TS U9779 ( .A(n8990), .B(n8989), .Y(n8991) );
AOI21X1TS U9780 ( .A0(n9396), .A1(n8995), .B0(n8994), .Y(n9000) );
NAND2X1TS U9781 ( .A(n8998), .B(n8997), .Y(n8999) );
CLKINVX1TS U9782 ( .A(n9018), .Y(n9002) );
AOI21X1TS U9783 ( .A0(n9004), .A1(n9020), .B0(n9003), .Y(n9009) );
NAND2X1TS U9784 ( .A(n9007), .B(n9006), .Y(n9008) );
AOI21X1TS U9785 ( .A0(n9020), .A1(n9012), .B0(n9011), .Y(n9017) );
NAND2X1TS U9786 ( .A(n9015), .B(n9014), .Y(n9016) );
AOI21X1TS U9787 ( .A0(n9020), .A1(n9019), .B0(n9018), .Y(n9025) );
NAND2X1TS U9788 ( .A(n9023), .B(n9022), .Y(n9024) );
AOI21X1TS U9789 ( .A0(n9032), .A1(n1687), .B0(n9031), .Y(n9035) );
NAND2X1TS U9790 ( .A(n209), .B(n9033), .Y(n9034) );
NAND2X1TS U9791 ( .A(n9038), .B(n9037), .Y(n9039) );
AOI21X1TS U9792 ( .A0(n9042), .A1(n1706), .B0(n9041), .Y(n9045) );
NAND2X1TS U9793 ( .A(n210), .B(n9043), .Y(n9044) );
NAND2X1TS U9794 ( .A(n9048), .B(n9047), .Y(n9050) );
NAND2X1TS U9795 ( .A(n9053), .B(n9052), .Y(n9055) );
CLKBUFX2TS U9796 ( .A(n595), .Y(n11719) );
CLKBUFX2TS U9797 ( .A(n11722), .Y(n11628) );
CLKBUFX2TS U9798 ( .A(n11722), .Y(n11284) );
CLKBUFX2TS U9799 ( .A(n11722), .Y(n11283) );
CLKBUFX2TS U9800 ( .A(n11722), .Y(n11282) );
NOR2X1TS U9801 ( .A(n9058), .B(DP_OP_59J6_122_190_n166), .Y(
DP_OP_59J6_122_190_n160) );
NAND2X1TS U9802 ( .A(DP_OP_62J6_125_4796_n561), .B(DP_OP_62J6_125_4796_n564),
.Y(DP_OP_62J6_125_4796_n280) );
NAND2X1TS U9803 ( .A(n9062), .B(n9061), .Y(DP_OP_62J6_125_4796_n283) );
ADDFHX2TS U9804 ( .A(n9066), .B(n9065), .CI(n9064), .CO(n9061), .S(n9071) );
NAND2X1TS U9805 ( .A(n9350), .B(n9072), .Y(DP_OP_62J6_125_4796_n39) );
NAND2X1TS U9806 ( .A(n9073), .B(n9074), .Y(n11306) );
NAND2X1TS U9807 ( .A(n9073), .B(DP_OP_62J6_125_4796_n551), .Y(n11307) );
NAND2X1TS U9808 ( .A(n9074), .B(DP_OP_62J6_125_4796_n551), .Y(n11308) );
NAND2X1TS U9809 ( .A(n9078), .B(n9077), .Y(n9079) );
XNOR2X1TS U9810 ( .A(n9080), .B(n9079), .Y(EVEN1_Q_left[13]) );
NAND2X1TS U9811 ( .A(n9083), .B(n9082), .Y(n9084) );
CLKINVX1TS U9812 ( .A(n9086), .Y(n9095) );
AOI21X1TS U9813 ( .A0(n9095), .A1(n9093), .B0(n9087), .Y(n9091) );
NAND2X1TS U9814 ( .A(n9089), .B(n9088), .Y(n9090) );
NAND2X1TS U9815 ( .A(n9093), .B(n9092), .Y(n9094) );
XNOR2X1TS U9816 ( .A(n9095), .B(n9094), .Y(EVEN1_Q_left[10]) );
NAND2X1TS U9817 ( .A(n9099), .B(n9098), .Y(n9100) );
XNOR2X1TS U9818 ( .A(n9101), .B(n9100), .Y(EVEN1_Q_left[9]) );
NAND2X1TS U9819 ( .A(n9104), .B(n9103), .Y(n9105) );
INVX1TS U9820 ( .A(n9107), .Y(n9115) );
AOI21X1TS U9821 ( .A0(n9115), .A1(n9114), .B0(n9108), .Y(n9112) );
NAND2X1TS U9822 ( .A(n9110), .B(n9109), .Y(n9111) );
NAND2X1TS U9823 ( .A(n9114), .B(n9113), .Y(n9116) );
XNOR2X1TS U9824 ( .A(n9116), .B(n9115), .Y(EVEN1_Q_left[6]) );
NAND2X1TS U9825 ( .A(n9118), .B(n9117), .Y(n9120) );
XNOR2X1TS U9826 ( .A(n9120), .B(n9119), .Y(EVEN1_Q_left[5]) );
NAND2X1TS U9827 ( .A(n236), .B(n9280), .Y(n9123) );
OAI21X1TS U9828 ( .A0(n9140), .A1(n9136), .B0(n9137), .Y(n9129) );
NAND2X1TS U9829 ( .A(n9127), .B(n9126), .Y(n9128) );
XNOR2X1TS U9830 ( .A(n9129), .B(n9128), .Y(n11220) );
NAND2X1TS U9831 ( .A(n9138), .B(n9137), .Y(n9139) );
INVX2TS U9832 ( .A(n11219), .Y(n9148) );
INVX2TS U9833 ( .A(EVEN1_Q_left[12]), .Y(n9147) );
XOR2X1TS U9834 ( .A(n9145), .B(n9144), .Y(n9146) );
NOR2X2TS U9835 ( .A(n9264), .B(n9263), .Y(n9337) );
AOI21X1TS U9836 ( .A0(n9163), .A1(n9161), .B0(n9150), .Y(n9154) );
NAND2X1TS U9837 ( .A(n9152), .B(n9151), .Y(n9153) );
INVX2TS U9838 ( .A(n11216), .Y(n9255) );
INVX2TS U9839 ( .A(EVEN1_Q_left[11]), .Y(n9254) );
INVX2TS U9840 ( .A(n9155), .Y(n9167) );
AOI21X1TS U9841 ( .A0(n9167), .A1(n9165), .B0(n9156), .Y(n9159) );
XOR2X1TS U9842 ( .A(n9159), .B(n9158), .Y(n9253) );
NOR2X1TS U9843 ( .A(n9262), .B(n9261), .Y(n9403) );
NAND2X1TS U9844 ( .A(n9161), .B(n9160), .Y(n9162) );
XNOR2X1TS U9845 ( .A(n9163), .B(n9162), .Y(n11213) );
INVX2TS U9846 ( .A(n11213), .Y(n9258) );
INVX2TS U9847 ( .A(EVEN1_Q_left[10]), .Y(n9257) );
NAND2X1TS U9848 ( .A(n9165), .B(n9164), .Y(n9166) );
XNOR2X1TS U9849 ( .A(n9167), .B(n9166), .Y(n9256) );
INVX1TS U9850 ( .A(n9168), .Y(n9186) );
NAND2X1TS U9851 ( .A(n9171), .B(n9170), .Y(n9172) );
XNOR2X1TS U9852 ( .A(n9173), .B(n9172), .Y(n11211) );
INVX2TS U9853 ( .A(n11211), .Y(n9181) );
INVX2TS U9854 ( .A(EVEN1_Q_left[9]), .Y(n9180) );
NAND2X1TS U9855 ( .A(n9177), .B(n9176), .Y(n9178) );
INVX2TS U9856 ( .A(n9182), .Y(n9184) );
NAND2X1TS U9857 ( .A(n9184), .B(n9183), .Y(n9185) );
INVX2TS U9858 ( .A(n11210), .Y(n9206) );
INVX2TS U9859 ( .A(EVEN1_Q_left[8]), .Y(n9205) );
INVX1TS U9860 ( .A(n9187), .Y(n9195) );
AOI21X1TS U9861 ( .A0(n9195), .A1(n9194), .B0(n9188), .Y(n9192) );
NAND2X1TS U9862 ( .A(n9190), .B(n9189), .Y(n9191) );
INVX2TS U9863 ( .A(n11208), .Y(n9219) );
INVX2TS U9864 ( .A(EVEN1_Q_left[7]), .Y(n9218) );
NAND2X1TS U9865 ( .A(n9194), .B(n9193), .Y(n9196) );
XNOR2X1TS U9866 ( .A(n9196), .B(n9195), .Y(n11205) );
INVX2TS U9867 ( .A(n11205), .Y(n9235) );
INVX2TS U9868 ( .A(EVEN1_Q_left[6]), .Y(n9234) );
NAND2X1TS U9869 ( .A(n9198), .B(n9197), .Y(n9200) );
XNOR2X1TS U9870 ( .A(n9200), .B(n9199), .Y(n11203) );
INVX2TS U9871 ( .A(n11203), .Y(n9227) );
INVX2TS U9872 ( .A(EVEN1_Q_left[5]), .Y(n9226) );
NAND2X1TS U9873 ( .A(n1496), .B(n9208), .Y(n9209) );
INVX2TS U9874 ( .A(n9211), .Y(n9347) );
XOR2X1TS U9875 ( .A(n9216), .B(n9215), .Y(n9244) );
NOR2X1TS U9876 ( .A(n9244), .B(n9243), .Y(n9418) );
INVX2TS U9877 ( .A(n9220), .Y(n9222) );
NAND2X1TS U9878 ( .A(n9222), .B(n9221), .Y(n9224) );
XOR2X1TS U9879 ( .A(n9224), .B(n9223), .Y(n9232) );
NOR2X1TS U9880 ( .A(n9232), .B(n9231), .Y(n9423) );
NAND2X1TS U9881 ( .A(n9232), .B(n9231), .Y(n9424) );
OAI21X1TS U9882 ( .A0(n9423), .A1(n221), .B0(n9424), .Y(n9357) );
NAND2X1TS U9883 ( .A(n9237), .B(n9236), .Y(n9239) );
XNOR2X1TS U9884 ( .A(n9239), .B(n9238), .Y(n9240) );
NAND2X1TS U9885 ( .A(n9241), .B(n9240), .Y(n9356) );
INVX1TS U9886 ( .A(n9356), .Y(n9242) );
AOI21X1TS U9887 ( .A0(n9357), .A1(n223), .B0(n9242), .Y(n9421) );
NAND2X1TS U9888 ( .A(n9244), .B(n9243), .Y(n9419) );
NAND2X1TS U9889 ( .A(n9251), .B(n9250), .Y(n9342) );
INVX2TS U9890 ( .A(n9342), .Y(n9252) );
NAND2X1TS U9891 ( .A(n9262), .B(n9261), .Y(n9404) );
NAND2X1TS U9892 ( .A(n9264), .B(n9263), .Y(n9338) );
AFHCONX2TS U9893 ( .A(n9268), .B(n9267), .CI(n9266), .CON(n9284), .S(n9287)
);
OR2X2TS U9894 ( .A(n9275), .B(n9274), .Y(n9375) );
NAND2X1TS U9895 ( .A(n9275), .B(n9274), .Y(n9303) );
NAND2X1TS U9896 ( .A(n9375), .B(n9303), .Y(n9276) );
XNOR2X1TS U9897 ( .A(n9376), .B(n9276), .Y(EVEN1_S_B[14]) );
CLKINVX1TS U9898 ( .A(n9277), .Y(n9279) );
NAND2X1TS U9899 ( .A(n9283), .B(n9282), .Y(n9285) );
XOR2X1TS U9900 ( .A(n9285), .B(n9284), .Y(n9311) );
NAND2X1TS U9901 ( .A(n9290), .B(n9289), .Y(n9292) );
INVX2TS U9902 ( .A(n9303), .Y(n9374) );
INVX2TS U9903 ( .A(n9377), .Y(n9306) );
NAND2X1TS U9904 ( .A(n9317), .B(n9316), .Y(n9318) );
NOR2X2TS U9905 ( .A(n9327), .B(n9326), .Y(n9370) );
NAND2X1TS U9906 ( .A(n9339), .B(n9338), .Y(n9340) );
XNOR2X1TS U9907 ( .A(n9341), .B(n9340), .Y(EVEN1_S_B[13]) );
NAND2X1TS U9908 ( .A(n9343), .B(n9342), .Y(n9345) );
XNOR2X1TS U9909 ( .A(n9345), .B(n9344), .Y(EVEN1_S_B[10]) );
NAND2X1TS U9910 ( .A(n9347), .B(n9346), .Y(n9349) );
XNOR2X1TS U9911 ( .A(n9349), .B(n9348), .Y(EVEN1_S_B[8]) );
NAND2X1TS U9912 ( .A(n9350), .B(n11389), .Y(DP_OP_62J6_125_4796_n286) );
AOI21X1TS U9913 ( .A0(n9355), .A1(n9354), .B0(n9353), .Y(
DP_OP_62J6_125_4796_n298) );
NAND2X1TS U9914 ( .A(n223), .B(n9356), .Y(n9358) );
XNOR2X1TS U9915 ( .A(n9358), .B(n9357), .Y(EVEN1_S_B[6]) );
NAND2X1TS U9916 ( .A(n8379), .B(n9362), .Y(n9363) );
CLKINVX1TS U9917 ( .A(EVEN1_Q_left[28]), .Y(DP_OP_62J6_125_4796_n697) );
CLKINVX1TS U9918 ( .A(DP_OP_62J6_125_4796_n298), .Y(DP_OP_62J6_125_4796_n297) );
NAND2X1TS U9919 ( .A(n9367), .B(n9366), .Y(n9368) );
XNOR2X1TS U9920 ( .A(n9369), .B(n9368), .Y(EVEN1_Q_left[22]) );
NAND2X1TS U9921 ( .A(n9372), .B(n9371), .Y(n9373) );
NAND2X1TS U9922 ( .A(n9377), .B(n9378), .Y(n9379) );
XOR2X1TS U9923 ( .A(n9380), .B(n9379), .Y(EVEN1_S_B[15]) );
NAND2X1TS U9924 ( .A(n9381), .B(n9386), .Y(n9389) );
AOI21X1TS U9925 ( .A0(n9387), .A1(n9386), .B0(n9385), .Y(n9388) );
OA21XLTS U9926 ( .A0(n9390), .A1(n9389), .B0(n9388), .Y(n9391) );
AOI21X1TS U9927 ( .A0(n9396), .A1(n9395), .B0(n9394), .Y(n9402) );
NAND2X1TS U9928 ( .A(n9400), .B(n9399), .Y(n9401) );
NAND2X1TS U9929 ( .A(n9405), .B(n9404), .Y(n9407) );
NAND2X1TS U9930 ( .A(n9410), .B(n9409), .Y(n9412) );
NAND2X1TS U9931 ( .A(n9415), .B(n9414), .Y(n9417) );
NAND2X1TS U9932 ( .A(n9420), .B(n9419), .Y(n9422) );
NAND2X1TS U9933 ( .A(n9425), .B(n9424), .Y(n9426) );
CLKBUFX2TS U9934 ( .A(n454), .Y(n11377) );
CLKBUFX2TS U9935 ( .A(n11377), .Y(n11378) );
CLKBUFX2TS U9936 ( .A(n11377), .Y(n11384) );
CLKBUFX2TS U9937 ( .A(n11377), .Y(n11383) );
CLKBUFX2TS U9938 ( .A(n11377), .Y(n11382) );
CLKBUFX2TS U9939 ( .A(n11377), .Y(n11380) );
CLKBUFX2TS U9940 ( .A(n11377), .Y(n11381) );
CLKBUFX2TS U9941 ( .A(n11377), .Y(n11379) );
NAND2X1TS U9942 ( .A(n9428), .B(n9427), .Y(n9429) );
AOI21X1TS U9943 ( .A0(n9434), .A1(n9433), .B0(n9432), .Y(n9438) );
NAND2X1TS U9944 ( .A(n9436), .B(n9435), .Y(n9437) );
CMPR32X2TS U9945 ( .A(n9440), .B(n9441), .C(n9439), .CO(
DP_OP_62J6_125_4796_n558), .S(DP_OP_62J6_125_4796_n559) );
NAND2X1TS U9946 ( .A(add_x_3_n5), .B(add_x_3_n52), .Y(add_x_3_n50) );
NAND2X1TS U9947 ( .A(add_x_3_n5), .B(add_x_3_n99), .Y(add_x_3_n97) );
NOR2X2TS U9948 ( .A(n9447), .B(n9446), .Y(add_x_3_n166) );
NAND2X1TS U9949 ( .A(n9454), .B(n9453), .Y(n9455) );
AOI21X1TS U9950 ( .A0(n9459), .A1(n9458), .B0(n9457), .Y(n9462) );
NOR2X2TS U9951 ( .A(add_x_3_n166), .B(n9465), .Y(n9492) );
NAND2X1TS U9952 ( .A(n9467), .B(n9466), .Y(add_x_3_n12) );
NAND2X1TS U9953 ( .A(add_x_3_n307), .B(n9500), .Y(add_x_3_n15) );
NAND2X1TS U9954 ( .A(n9476), .B(n9475), .Y(n9477) );
NAND2X1TS U9955 ( .A(n9480), .B(n9479), .Y(n9482) );
XNOR2X1TS U9956 ( .A(n9482), .B(n9481), .Y(n9485) );
NOR2X1TS U9957 ( .A(n9511), .B(n9488), .Y(n9491) );
INVX2TS U9958 ( .A(n9514), .Y(n9490) );
NAND2X1TS U9959 ( .A(n9497), .B(n9496), .Y(n9507) );
NAND2X1TS U9960 ( .A(n9498), .B(n9507), .Y(add_x_3_n6) );
NAND2X1TS U9961 ( .A(n9499), .B(add_x_3_n169), .Y(add_x_3_n13) );
NAND2X1TS U9962 ( .A(add_x_3_n5), .B(add_x_3_n81), .Y(add_x_3_n79) );
NAND2X1TS U9963 ( .A(add_x_3_n5), .B(add_x_3_n70), .Y(add_x_3_n68) );
NAND2X1TS U9964 ( .A(add_x_3_n303), .B(n9502), .Y(add_x_3_n11) );
OAI21X1TS U9965 ( .A0(n9537), .A1(add_x_3_n141), .B0(n9509), .Y(add_x_3_n132) );
OAI21X1TS U9966 ( .A0(n9514), .A1(n9511), .B0(n9510), .Y(add_x_3_n190) );
OAI21X1TS U9967 ( .A0(n9514), .A1(n9513), .B0(n9512), .Y(add_x_3_n197) );
NAND2X1TS U9968 ( .A(n9515), .B(n9520), .Y(n9523) );
CLKAND2X2TS U9969 ( .A(n9517), .B(n9526), .Y(n9529) );
AOI21X1TS U9970 ( .A0(n9521), .A1(n9520), .B0(n9519), .Y(n9522) );
AOI21X1TS U9971 ( .A0(n9530), .A1(n9529), .B0(n9528), .Y(n9535) );
OR2X1TS U9972 ( .A(n9531), .B(n1692), .Y(n9533) );
NAND2X1TS U9973 ( .A(n9533), .B(n9532), .Y(n9534) );
NOR2X1TS U9974 ( .A(add_x_3_n138), .B(n9537), .Y(add_x_3_n131) );
CLKBUFX2TS U9975 ( .A(n267), .Y(n11447) );
CLKBUFX2TS U9976 ( .A(n11721), .Y(n11452) );
CLKBUFX2TS U9977 ( .A(n266), .Y(n11451) );
CLKBUFX2TS U9978 ( .A(n327), .Y(n11448) );
CLKBUFX2TS U9979 ( .A(n454), .Y(n11450) );
CLKBUFX2TS U9980 ( .A(n267), .Y(n11449) );
NAND2X1TS U9981 ( .A(n9542), .B(n9541), .Y(n9543) );
NAND2X1TS U9982 ( .A(n9547), .B(EVEN1_Q_left[31]), .Y(add_x_1_n318) );
CLKBUFX2TS U9983 ( .A(n11724), .Y(n11629) );
CLKBUFX2TS U9984 ( .A(n325), .Y(n9551) );
CLKBUFX2TS U9985 ( .A(n9551), .Y(n11540) );
CLKBUFX2TS U9986 ( .A(n9551), .Y(n11539) );
CLKBUFX2TS U9987 ( .A(n9551), .Y(n11535) );
CLKBUFX2TS U9988 ( .A(n9551), .Y(n11536) );
CLKBUFX2TS U9989 ( .A(n9551), .Y(n11537) );
CLKBUFX2TS U9990 ( .A(n9551), .Y(n11538) );
AOI21X1TS U9991 ( .A0(n9557), .A1(n9556), .B0(n9555), .Y(n9562) );
NAND2X1TS U9992 ( .A(n9558), .B(n9559), .Y(n9565) );
NAND2X1TS U9993 ( .A(n9560), .B(n9565), .Y(n9561) );
AOI21X1TS U9994 ( .A0(n9570), .A1(n9569), .B0(n9568), .Y(n9571) );
NAND2X1TS U9995 ( .A(n9575), .B(n9574), .Y(n9593) );
NAND2X1TS U9996 ( .A(n9595), .B(n9593), .Y(n9576) );
NAND2X1TS U9997 ( .A(n9579), .B(n9578), .Y(n9597) );
AOI21X1TS U9998 ( .A0(n9704), .A1(n9675), .B0(n9687), .Y(n9583) );
NAND2X1TS U9999 ( .A(n9581), .B(n9580), .Y(n9602) );
NAND2X1TS U10000 ( .A(n9601), .B(n9602), .Y(n9582) );
AOI21X1TS U10001 ( .A0(n9704), .A1(n9588), .B0(n9587), .Y(n9592) );
NAND2X1TS U10002 ( .A(n9606), .B(n9603), .Y(n9591) );
AOI21X1TS U10003 ( .A0(n9704), .A1(n9595), .B0(n9594), .Y(n9600) );
NAND2X1TS U10004 ( .A(n9598), .B(n9597), .Y(n9599) );
NAND2X1TS U10005 ( .A(add_x_2_n99), .B(n9659), .Y(n9672) );
NAND2X1TS U10006 ( .A(n9601), .B(n9606), .Y(n9674) );
INVX2TS U10007 ( .A(n9674), .Y(n9608) );
NAND2X1TS U10008 ( .A(n9675), .B(n9608), .Y(n9697) );
AOI21X1TS U10009 ( .A0(n9606), .A1(n9605), .B0(n9604), .Y(n9684) );
AOI21X1TS U10010 ( .A0(n9687), .A1(n9608), .B0(n9607), .Y(n9701) );
NAND2X1TS U10011 ( .A(n9610), .B(n9609), .Y(n9678) );
AOI21X1TS U10012 ( .A0(n9704), .A1(n9612), .B0(n9611), .Y(n9617) );
NAND2X1TS U10013 ( .A(n9614), .B(n9613), .Y(n9676) );
NAND2X1TS U10014 ( .A(n9615), .B(n9676), .Y(n9616) );
AOI21X1TS U10015 ( .A0(n9704), .A1(n9619), .B0(n9618), .Y(n9622) );
NAND2X1TS U10016 ( .A(n9620), .B(n9678), .Y(n9621) );
NAND2X1TS U10017 ( .A(add_x_2_n70), .B(n9660), .Y(n9668) );
NAND2X1TS U10018 ( .A(n9624), .B(n9623), .Y(add_x_2_n118) );
NAND2X1TS U10019 ( .A(n9627), .B(n9626), .Y(add_x_2_n125) );
NAND2X1TS U10020 ( .A(n9628), .B(add_x_2_n141), .Y(add_x_2_n9) );
NAND2X1TS U10021 ( .A(add_x_2_n303), .B(n9630), .Y(add_x_2_n11) );
INVX2TS U10022 ( .A(n9632), .Y(n9633) );
NAND2X1TS U10023 ( .A(n9637), .B(n9636), .Y(n9638) );
AOI21X1TS U10024 ( .A0(n9641), .A1(n9640), .B0(n9639), .Y(n9645) );
NAND2X1TS U10025 ( .A(n9643), .B(n9642), .Y(n9644) );
NAND2X1TS U10026 ( .A(n9647), .B(n9646), .Y(n9650) );
OAI21X1TS U10027 ( .A0(n9649), .A1(add_x_2_n169), .B0(n9650), .Y(n9648) );
AOI21X1TS U10028 ( .A0(n9654), .A1(add_x_2_n172), .B0(n9648), .Y(
add_x_2_n158) );
NAND2X1TS U10029 ( .A(n155), .B(n9653), .Y(add_x_2_n14) );
NAND2X1TS U10030 ( .A(add_x_2_n171), .B(n9654), .Y(add_x_2_n157) );
NAND2X1TS U10031 ( .A(n9658), .B(n9657), .Y(add_x_2_n8) );
NAND2X1TS U10032 ( .A(n9665), .B(n9664), .Y(add_x_2_n17) );
NAND2X1TS U10033 ( .A(n136), .B(n9667), .Y(add_x_2_n15) );
CLKAND2X2TS U10034 ( .A(n9675), .B(n9686), .Y(n9689) );
NAND2X1TS U10035 ( .A(n9680), .B(n9679), .Y(n9705) );
AOI21X1TS U10036 ( .A0(n9698), .A1(n9706), .B0(n9681), .Y(n9682) );
AOI21X1TS U10037 ( .A0(n9704), .A1(n9689), .B0(n9688), .Y(n9694) );
NAND2X1TS U10038 ( .A(n9692), .B(n9691), .Y(n9693) );
AOI21X1TS U10039 ( .A0(n9704), .A1(n9703), .B0(n9702), .Y(n9708) );
NAND2X1TS U10040 ( .A(n9706), .B(n9705), .Y(n9707) );
CLKBUFX2TS U10041 ( .A(n454), .Y(n11612) );
CLKBUFX2TS U10042 ( .A(n454), .Y(n11613) );
CLKBUFX2TS U10043 ( .A(n455), .Y(n11611) );
CLKBUFX2TS U10044 ( .A(n454), .Y(n11610) );
INVX2TS U10045 ( .A(n11731), .Y(n11725) );
CLKBUFX2TS U10046 ( .A(n11629), .Y(n11722) );
CLKBUFX2TS U10047 ( .A(n595), .Y(n11723) );
CLKBUFX2TS U10048 ( .A(n595), .Y(n11721) );
CLKBUFX2TS U10049 ( .A(n595), .Y(n11720) );
CLKBUFX2TS U10050 ( .A(n595), .Y(n11724) );
AOI21X1TS U10051 ( .A0(n11542), .A1(n11499), .B0(n11559), .Y(n9713) );
NAND2X1TS U10052 ( .A(n11529), .B(n11528), .Y(n9712) );
INVX2TS U10053 ( .A(n11731), .Y(n11726) );
INVX2TS U10054 ( .A(n11731), .Y(n11727) );
INVX2TS U10055 ( .A(n11730), .Y(n11728) );
INVX2TS U10056 ( .A(n11730), .Y(n11729) );
INVX2TS U10057 ( .A(n11730), .Y(n11186) );
AOI21X1TS U10058 ( .A0(n11466), .A1(n11437), .B0(n11438), .Y(n9715) );
NAND2X1TS U10059 ( .A(n11420), .B(n11421), .Y(n9714) );
XNOR2X1TS U10060 ( .A(n11466), .B(n11403), .Y(n10033) );
NAND2X1TS U10061 ( .A(n10847), .B(n10845), .Y(n10852) );
AOI21X1TS U10062 ( .A0(n11529), .A1(n11559), .B0(n11555), .Y(n9716) );
OAI2BB1X1TS U10063 ( .A0N(n11558), .A1N(n9717), .B0(n9716), .Y(n10822) );
XNOR2X1TS U10064 ( .A(n11404), .B(n11405), .Y(n9991) );
NAND2X1TS U10065 ( .A(n11636), .B(n11498), .Y(n10826) );
INVX2TS U10066 ( .A(n10826), .Y(n10830) );
AOI21X1TS U10067 ( .A0(n10839), .A1(n10838), .B0(n10837), .Y(n9725) );
AOI21X1TS U10068 ( .A0(n9723), .A1(n10853), .B0(n10856), .Y(n9724) );
NOR2BX1TS U10069 ( .AN(n9973), .B(n11553), .Y(n10862) );
AOI21X1TS U10070 ( .A0(n11466), .A1(n11412), .B0(n9728), .Y(n9729) );
OAI2BB1X1TS U10071 ( .A0N(n11631), .A1N(n9732), .B0(n11651), .Y(
sgf_result_o[38]) );
INVX2TS U10072 ( .A(load_b_i), .Y(n11091) );
OAI2BB1X1TS U10073 ( .A0N(n11391), .A1N(n11387), .B0(n11366), .Y(n9822) );
AOI21X1TS U10074 ( .A0(n9734), .A1(n9822), .B0(n9733), .Y(n9880) );
CMPR32X2TS U10075 ( .A(n11362), .B(n11363), .C(n11364), .CO(n9741), .S(n9737) );
CMPR32X2TS U10076 ( .A(n11369), .B(n11370), .C(n11371), .CO(n9736), .S(n9735) );
NAND2X1TS U10077 ( .A(n9737), .B(n9736), .Y(n9883) );
OA21XLTS U10078 ( .A0(n9882), .A1(n9738), .B0(n9883), .Y(n9739) );
OAI21X1TS U10079 ( .A0(n9880), .A1(n9740), .B0(n9739), .Y(n9901) );
NAND2X1TS U10080 ( .A(n9742), .B(n9741), .Y(n9898) );
NAND2X1TS U10081 ( .A(n9833), .B(n9832), .Y(n9834) );
OA21XLTS U10082 ( .A0(n9743), .A1(n9898), .B0(n9834), .Y(n9744) );
CMPR32X2TS U10083 ( .A(n11342), .B(n11343), .C(n11344), .CO(n9748), .S(n9833) );
INVX2TS U10084 ( .A(n9747), .Y(n9750) );
INVX2TS U10085 ( .A(n9748), .Y(n9749) );
CMPR32X2TS U10086 ( .A(n11336), .B(n11337), .C(n11338), .CO(n9754), .S(n9747) );
NAND2X1TS U10087 ( .A(n9753), .B(n9752), .Y(n9765) );
CMPR32X2TS U10088 ( .A(n11334), .B(n11335), .C(n9756), .CO(n9759), .S(n9755)
);
INVX2TS U10089 ( .A(n9766), .Y(n9769) );
NOR2BX1TS U10090 ( .AN(n9769), .B(n9767), .Y(n9761) );
NAND2BX1TS U10091 ( .AN(n9925), .B(n11546), .Y(n11005) );
NOR2BX1TS U10092 ( .AN(n9765), .B(n9768), .Y(n9764) );
INVX2TS U10093 ( .A(n9763), .Y(n9771) );
XNOR2X1TS U10094 ( .A(n9764), .B(n9771), .Y(n9924) );
AOI21X1TS U10095 ( .A0(n9769), .A1(n9768), .B0(n9767), .Y(n9770) );
CMPR32X2TS U10096 ( .A(n11356), .B(n11357), .C(n11358), .CO(n9936), .S(n9778) );
XNOR2X1TS U10097 ( .A(n9773), .B(n11243), .Y(n9934) );
CMPR32X2TS U10098 ( .A(n11332), .B(n9778), .C(n9777), .CO(n9774) );
INVX2TS U10099 ( .A(n9774), .Y(n9775) );
NOR2BX1TS U10100 ( .AN(n9779), .B(n9775), .Y(n10020) );
XNOR2X1TS U10101 ( .A(n9931), .B(n9780), .Y(n9927) );
NAND2BX1TS U10102 ( .AN(n9927), .B(n11548), .Y(n9781) );
INVX2TS U10103 ( .A(n9781), .Y(n11013) );
INVX2TS U10104 ( .A(n10870), .Y(n9783) );
XNOR2X1TS U10105 ( .A(n9895), .B(n11399), .Y(n9959) );
INVX2TS U10106 ( .A(n9787), .Y(n10875) );
OAI2BB1X1TS U10107 ( .A0N(n10868), .A1N(n9787), .B0(n10873), .Y(n9788) );
INVX2TS U10108 ( .A(n10104), .Y(n10903) );
OA21XLTS U10109 ( .A0(n11409), .A1(n11410), .B0(n11411), .Y(n9791) );
NAND2X1TS U10110 ( .A(n9793), .B(n11551), .Y(n10898) );
NAND2X1TS U10111 ( .A(n9800), .B(n10898), .Y(n9799) );
CLKBUFX2TS U10112 ( .A(n9895), .Y(n9848) );
AOI21X1TS U10113 ( .A0(n9848), .A1(n11407), .B0(n11402), .Y(n9794) );
XNOR2X1TS U10114 ( .A(n9797), .B(n11457), .Y(n9954) );
NAND2X1TS U10115 ( .A(n10888), .B(n10890), .Y(n10882) );
NOR2BX1TS U10116 ( .AN(n10099), .B(n11551), .Y(n10897) );
AOI21X1TS U10117 ( .A0(n9800), .A1(n10897), .B0(n10904), .Y(n9801) );
OAI2BB1X1TS U10118 ( .A0N(n10899), .A1N(n9802), .B0(n9801), .Y(n9803) );
AOI21X1TS U10119 ( .A0(n10902), .A1(n9804), .B0(n9803), .Y(n10937) );
OAI2BB1X1TS U10120 ( .A0N(n9893), .A1N(n11463), .B0(n9813), .Y(n9814) );
XNOR2X1TS U10121 ( .A(n9816), .B(n11393), .Y(n10915) );
NOR2XLTS U10122 ( .A(n10915), .B(n10914), .Y(n10939) );
OAI2BB1X1TS U10123 ( .A0N(n9893), .A1N(n11434), .B0(n9818), .Y(n9819) );
AOI21X1TS U10124 ( .A0(n9820), .A1(n9848), .B0(n9819), .Y(n9821) );
INVX2TS U10125 ( .A(n9822), .Y(n9858) );
NOR2BX1TS U10126 ( .AN(n10916), .B(n10921), .Y(n9827) );
NAND2X1TS U10127 ( .A(n10934), .B(n9827), .Y(n9829) );
NOR2BX1TS U10128 ( .AN(n10133), .B(n1698), .Y(n10929) );
NOR2BX1TS U10129 ( .AN(n10915), .B(n9824), .Y(n10938) );
AOI21X1TS U10130 ( .A0(n10935), .A1(n9827), .B0(n9826), .Y(n9828) );
INVX2TS U10131 ( .A(n9830), .Y(n9899) );
AOI21X1TS U10132 ( .A0(n9901), .A1(n9899), .B0(n9831), .Y(n9837) );
XNOR2X1TS U10133 ( .A(n9837), .B(n9836), .Y(n9916) );
AOI21X1TS U10134 ( .A0(n9840), .A1(n9848), .B0(n9839), .Y(n9841) );
OAI2BB1X1TS U10135 ( .A0N(n9893), .A1N(n11454), .B0(n9846), .Y(n9847) );
AOI21X1TS U10136 ( .A0(n9849), .A1(n9848), .B0(n9847), .Y(n9850) );
INVX2TS U10137 ( .A(n10273), .Y(n9851) );
NAND2X1TS U10138 ( .A(n10983), .B(n10992), .Y(n9921) );
NAND2X1TS U10139 ( .A(n11439), .B(n11442), .Y(n9853) );
NAND2X1TS U10140 ( .A(n9860), .B(n11373), .Y(n9861) );
XNOR2X1TS U10141 ( .A(n9862), .B(n9861), .Y(n9906) );
XNOR2X1TS U10142 ( .A(n9867), .B(n11394), .Y(n10158) );
XNOR2X1TS U10143 ( .A(n9869), .B(n9868), .Y(n9909) );
NAND2X1TS U10144 ( .A(n10953), .B(n9870), .Y(n10966) );
NOR2BX1TS U10145 ( .AN(n9871), .B(n11446), .Y(n9876) );
XNOR2X1TS U10146 ( .A(n9877), .B(n11397), .Y(n10212) );
NAND2X1TS U10147 ( .A(n11439), .B(n11441), .Y(n9890) );
OAI2BB1X1TS U10148 ( .A0N(n9893), .A1N(n9892), .B0(n9891), .Y(n9894) );
OAI2BB1X1TS U10149 ( .A0N(n10977), .A1N(n10968), .B0(n9912), .Y(n9913) );
AOI21X1TS U10150 ( .A0(n9915), .A1(n9914), .B0(n9913), .Y(n10987) );
INVX2TS U10151 ( .A(n10237), .Y(n9917) );
INVX2TS U10152 ( .A(n10946), .Y(n10985) );
AOI21X1TS U10153 ( .A0(n10992), .A1(n10985), .B0(n9919), .Y(n9920) );
AOI21X1TS U10154 ( .A0(n10973), .A1(n9923), .B0(n9922), .Y(n10351) );
INVX2TS U10155 ( .A(n10351), .Y(n11011) );
NAND2X1TS U10156 ( .A(n9924), .B(n11530), .Y(n10997) );
NAND2X1TS U10157 ( .A(n9925), .B(n11494), .Y(n11004) );
OAI21X1TS U10158 ( .A0(n9926), .A1(n10997), .B0(n11004), .Y(n11009) );
NOR2BX1TS U10159 ( .AN(n9927), .B(n11544), .Y(n11012) );
AOI21X1TS U10160 ( .A0(n9930), .A1(n11011), .B0(n9929), .Y(n9944) );
INVX2TS U10161 ( .A(n9931), .Y(n10339) );
XNOR2X1TS U10162 ( .A(n11297), .B(n11242), .Y(n10012) );
INVX2TS U10163 ( .A(n9933), .Y(n9939) );
CMPR32X2TS U10164 ( .A(n9936), .B(n9935), .C(n9934), .CO(n9937), .S(n9779)
);
INVX2TS U10165 ( .A(n9937), .Y(n9938) );
AND2X2TS U10166 ( .A(n9939), .B(n9938), .Y(n10017) );
INVX2TS U10167 ( .A(n10017), .Y(n10021) );
NAND2X1TS U10168 ( .A(n9942), .B(n11493), .Y(n10345) );
NAND2X1TS U10169 ( .A(n10344), .B(n10345), .Y(n9943) );
OAI2BB1X1TS U10170 ( .A0N(n11630), .A1N(n9945), .B0(n11669), .Y(
sgf_result_o[57]) );
NAND2X1TS U10171 ( .A(n11726), .B(sgf_result_o[57]), .Y(n11745) );
NAND2X1TS U10172 ( .A(n11270), .B(n9999), .Y(n9948) );
AOI21X1TS U10173 ( .A0(n11245), .A1(n9998), .B0(n9946), .Y(n9947) );
NAND2X1TS U10174 ( .A(n11278), .B(n11269), .Y(n10105) );
AOI21X1TS U10175 ( .A0(n10059), .A1(n11269), .B0(n11240), .Y(n9971) );
AOI21X1TS U10176 ( .A0(n10112), .A1(n9950), .B0(n9949), .Y(n9951) );
XNOR2X1TS U10177 ( .A(n9951), .B(n11290), .Y(n10120) );
INVX2TS U10178 ( .A(n10281), .Y(n10155) );
XNOR2X1TS U10179 ( .A(n9953), .B(n11618), .Y(n10776) );
AOI21X1TS U10180 ( .A0(n10109), .A1(n11287), .B0(n11304), .Y(n9956) );
OA21XLTS U10181 ( .A0(n10034), .A1(n9957), .B0(n9956), .Y(n9958) );
XNOR2X1TS U10182 ( .A(n9958), .B(n11288), .Y(n9963) );
INVX2TS U10183 ( .A(n9959), .Y(n9967) );
CMPR32X2TS U10184 ( .A(n11311), .B(n9795), .C(n9960), .CO(n10119), .S(n9961)
);
CMPR32X2TS U10185 ( .A(n9963), .B(n9962), .C(n9961), .CO(n10085), .S(n10084)
);
AOI21X1TS U10186 ( .A0(n10109), .A1(n11295), .B0(n11241), .Y(n9964) );
OAI2BB1X1TS U10187 ( .A0N(n10112), .A1N(n9965), .B0(n9964), .Y(n9966) );
CMPR32X2TS U10188 ( .A(n11313), .B(n1703), .C(n9967), .CO(n9962), .S(n9986)
);
INVX2TS U10189 ( .A(n9968), .Y(n9976) );
AOI21X1TS U10190 ( .A0(n11603), .A1(n11585), .B0(n9969), .Y(n9970) );
XNOR2X1TS U10191 ( .A(n9970), .B(n11619), .Y(n10726) );
INVX2TS U10192 ( .A(n10726), .Y(n9975) );
OA21XLTS U10193 ( .A0(n10034), .A1(n10105), .B0(n9971), .Y(n9972) );
XNOR2X1TS U10194 ( .A(n9972), .B(n11289), .Y(n9990) );
INVX2TS U10195 ( .A(n9973), .Y(n9984) );
AOI21X1TS U10196 ( .A0(n11603), .A1(n11591), .B0(n11592), .Y(n9974) );
INVX2TS U10197 ( .A(n10747), .Y(n9983) );
CMPR32X2TS U10198 ( .A(n11326), .B(n9976), .C(n9975), .CO(n9985), .S(n9988)
);
OA21XLTS U10199 ( .A0(n11252), .A1(n11253), .B0(n11254), .Y(n9977) );
INVX2TS U10200 ( .A(n9982), .Y(n10063) );
INVX2TS U10201 ( .A(n10737), .Y(n10062) );
CMPR32X2TS U10202 ( .A(n11323), .B(n9984), .C(n9983), .CO(n9989), .S(n10055)
);
CMPR32X2TS U10203 ( .A(n9987), .B(n9986), .C(n9985), .CO(n10083), .S(n10079)
);
CMPR32X2TS U10204 ( .A(n9990), .B(n9989), .C(n9988), .CO(n10080), .S(n10393)
);
NAND2X1TS U10205 ( .A(n10090), .B(n10400), .Y(n10092) );
INVX2TS U10206 ( .A(n9991), .Y(n10037) );
XNOR2X1TS U10207 ( .A(n11577), .B(n11578), .Y(n10569) );
INVX2TS U10208 ( .A(n10569), .Y(n10036) );
OAI2BB1X1TS U10209 ( .A0N(n9998), .A1N(n11301), .B0(n11277), .Y(n9993) );
AOI21X1TS U10210 ( .A0(n11297), .A1(n9999), .B0(n9998), .Y(n10000) );
CMPR32X2TS U10211 ( .A(n11333), .B(n11390), .C(n1708), .CO(n10042), .S(
n10002) );
CMPR32X2TS U10212 ( .A(n10004), .B(n10003), .C(n10002), .CO(n10028), .S(
n10325) );
CMPR32X2TS U10213 ( .A(n11348), .B(n145), .C(n11349), .CO(n10010), .S(n10013) );
CMPR32X2TS U10214 ( .A(n11339), .B(n11340), .C(n11388), .CO(n10004), .S(
n10009) );
AOI21X1TS U10215 ( .A0(n11297), .A1(n11247), .B0(n11248), .Y(n10006) );
NAND2X1TS U10216 ( .A(n11255), .B(n11256), .Y(n10005) );
CMPR32X2TS U10217 ( .A(n10010), .B(n10009), .C(n10008), .CO(n10027), .S(
n10011) );
INVX2TS U10218 ( .A(n10011), .Y(n10023) );
CMPR32X2TS U10219 ( .A(n10014), .B(n10013), .C(n10012), .CO(n10015), .S(
n9933) );
INVX2TS U10220 ( .A(n10015), .Y(n10022) );
NAND2X1TS U10221 ( .A(n10023), .B(n10022), .Y(n10341) );
NAND2X1TS U10222 ( .A(n10325), .B(n10027), .Y(n10332) );
AOI21X1TS U10223 ( .A0(n10031), .A1(n10336), .B0(n10030), .Y(n10367) );
INVX2TS U10224 ( .A(n10032), .Y(n10038) );
INVX2TS U10225 ( .A(n10033), .Y(n10058) );
OA21XLTS U10226 ( .A0(n10034), .A1(n11285), .B0(n11302), .Y(n10035) );
XNOR2X1TS U10227 ( .A(n10035), .B(n11294), .Y(n10067) );
CMPR32X2TS U10228 ( .A(n11330), .B(n10037), .C(n10036), .CO(n10041), .S(
n10044) );
CMPR32X2TS U10229 ( .A(n11329), .B(n10038), .C(n1694), .CO(n10069), .S(
n10039) );
CMPR32X2TS U10230 ( .A(n10041), .B(n10040), .C(n10039), .CO(n10051), .S(
n10364) );
INVX2TS U10231 ( .A(n10042), .Y(n10046) );
NAND2X1TS U10232 ( .A(n10364), .B(n10363), .Y(n10359) );
NAND2X1TS U10233 ( .A(n10052), .B(n10051), .Y(n10368) );
CMPR32X2TS U10234 ( .A(n10057), .B(n10056), .C(n10055), .CO(n10392), .S(
n10072) );
CMPR32X2TS U10235 ( .A(n11331), .B(n1699), .C(n10058), .CO(n10066), .S(
n10068) );
AOI21X1TS U10236 ( .A0(n10112), .A1(n11278), .B0(n10059), .Y(n10061) );
XNOR2X1TS U10237 ( .A(n10061), .B(n10060), .Y(n10065) );
CMPR32X2TS U10238 ( .A(n11327), .B(n10063), .C(n10062), .CO(n10056), .S(
n10064) );
CMPR32X2TS U10239 ( .A(n10066), .B(n10065), .C(n10064), .CO(n10073), .S(
n10071) );
CMPR32X2TS U10240 ( .A(n10069), .B(n10068), .C(n10067), .CO(n10070), .S(
n10052) );
NAND2X1TS U10241 ( .A(n10071), .B(n10070), .Y(n10383) );
NAND2X1TS U10242 ( .A(n10084), .B(n10083), .Y(n10427) );
AOI21X1TS U10243 ( .A0(n10090), .A1(n10401), .B0(n10089), .Y(n10091) );
NAND2X1TS U10244 ( .A(n11261), .B(n11268), .Y(n10093) );
AOI21X1TS U10245 ( .A0(n10112), .A1(n10097), .B0(n10096), .Y(n10098) );
XNOR2X1TS U10246 ( .A(n10101), .B(n11620), .Y(n10660) );
AOI21X1TS U10247 ( .A0(n10281), .A1(n10145), .B0(n10137), .Y(n10103) );
XNOR2X1TS U10248 ( .A(n10103), .B(n10102), .Y(n10668) );
INVX2TS U10249 ( .A(n10668), .Y(n10129) );
NAND2X1TS U10250 ( .A(n11261), .B(n11281), .Y(n10106) );
AOI21X1TS U10251 ( .A0(n10112), .A1(n10111), .B0(n10110), .Y(n10113) );
CMPR32X2TS U10252 ( .A(n11316), .B(n9798), .C(n10789), .CO(n10181), .S(
n10118) );
CMPR32X2TS U10253 ( .A(n11322), .B(n9793), .C(n10114), .CO(n10123), .S(
n10180) );
INVX2TS U10254 ( .A(n10115), .Y(n10116) );
CMPR32X2TS U10255 ( .A(n10182), .B(n10181), .C(n10180), .CO(n10115), .S(
n10121) );
CMPR32X2TS U10256 ( .A(n10120), .B(n10119), .C(n10118), .CO(n10178), .S(
n10087) );
CMPR32X2TS U10257 ( .A(n10124), .B(n10123), .C(n10122), .CO(n10186), .S(
n10184) );
OAI2BB1X1TS U10258 ( .A0N(n10137), .A1N(n11607), .B0(n11608), .Y(n10125) );
AOI21X1TS U10259 ( .A0(n10126), .A1(n530), .B0(n10125), .Y(n10127) );
XNOR2X1TS U10260 ( .A(n10127), .B(n11614), .Y(n10657) );
CMPR32X2TS U10261 ( .A(n11317), .B(n10129), .C(n10903), .CO(n10134), .S(
n10122) );
AOI21X1TS U10262 ( .A0(n10131), .A1(n10281), .B0(n10130), .Y(n10132) );
INVX2TS U10263 ( .A(n10792), .Y(n10171) );
INVX2TS U10264 ( .A(n10133), .Y(n10168) );
CMPR32X2TS U10265 ( .A(n10136), .B(n10135), .C(n10134), .CO(n10187), .S(
n10185) );
NAND2X1TS U10266 ( .A(n10452), .B(n10190), .Y(n10463) );
INVX2TS U10267 ( .A(n10137), .Y(n10279) );
NAND2X1TS U10268 ( .A(n10274), .B(n11595), .Y(n10147) );
AOI21X1TS U10269 ( .A0(n10149), .A1(n10281), .B0(n10148), .Y(n10150) );
INVX2TS U10270 ( .A(n10623), .Y(n10151) );
INVX2TS U10271 ( .A(n10915), .Y(n10167) );
INVX2TS U10272 ( .A(n10680), .Y(n10215) );
CMPR32X2TS U10273 ( .A(n10161), .B(n10160), .C(n10159), .CO(n10199), .S(
n10485) );
AOI21X1TS U10274 ( .A0(n10165), .A1(n530), .B0(n10164), .Y(n10166) );
INVX2TS U10275 ( .A(n10809), .Y(n10176) );
CMPR32X2TS U10276 ( .A(n10171), .B(n10170), .C(n10169), .CO(n10192), .S(
n10188) );
CMPR32X2TS U10277 ( .A(n1701), .B(n10173), .C(n10172), .CO(n10484), .S(
n10195) );
CMPR32X2TS U10278 ( .A(n10176), .B(n10175), .C(n10174), .CO(n10196), .S(
n10191) );
NAND2X1TS U10279 ( .A(n10202), .B(n10479), .Y(n10204) );
CMPR32X2TS U10280 ( .A(n10182), .B(n10181), .C(n10180), .CO(n10183), .S(
n10177) );
NAND2X1TS U10281 ( .A(n10184), .B(n10183), .Y(n10422) );
NAND2X1TS U10282 ( .A(n10186), .B(n10185), .Y(n10453) );
NAND2X1TS U10283 ( .A(n10188), .B(n10187), .Y(n10459) );
AOI21X1TS U10284 ( .A0(n10456), .A1(n10190), .B0(n10189), .Y(n10467) );
OR2X2TS U10285 ( .A(n10194), .B(n10193), .Y(n10468) );
NAND2X1TS U10286 ( .A(n10200), .B(n10199), .Y(n10263) );
AOI21X1TS U10287 ( .A0(n10202), .A1(n10478), .B0(n10201), .Y(n10203) );
AO21X4TS U10288 ( .A0(n10254), .A1(n10206), .B0(n10205), .Y(n10313) );
AOI21X1TS U10289 ( .A0(n10210), .A1(n530), .B0(n10209), .Y(n10211) );
INVX2TS U10290 ( .A(n10602), .Y(n10225) );
CMPR32X2TS U10291 ( .A(n10215), .B(n10214), .C(n10213), .CO(n10216), .S(
n10200) );
AOI21X1TS U10292 ( .A0(n10221), .A1(n530), .B0(n10220), .Y(n10222) );
INVX2TS U10293 ( .A(n10613), .Y(n10246) );
CMPR32X2TS U10294 ( .A(n10225), .B(n10224), .C(n10223), .CO(n10226), .S(
n10217) );
INVX2TS U10295 ( .A(n10226), .Y(n10228) );
INVX2TS U10296 ( .A(n10227), .Y(n10234) );
XNOR2X1TS U10297 ( .A(n10232), .B(n10231), .Y(n10501) );
NAND2X1TS U10298 ( .A(n10274), .B(n11601), .Y(n10240) );
AOI21X1TS U10299 ( .A0(n10242), .A1(n530), .B0(n10241), .Y(n10243) );
INVX2TS U10300 ( .A(n10634), .Y(n10284) );
CMPR32X2TS U10301 ( .A(n10246), .B(n10245), .C(n10244), .CO(n10247), .S(
n10229) );
INVX2TS U10302 ( .A(n10291), .Y(n10270) );
NAND2X1TS U10303 ( .A(n10270), .B(n10294), .Y(n10249) );
XNOR2X1TS U10304 ( .A(n10250), .B(n10249), .Y(n10502) );
NAND2X1TS U10305 ( .A(n10477), .B(n10256), .Y(n10262) );
OA21XLTS U10306 ( .A0(n10258), .A1(n10257), .B0(n10486), .Y(n10259) );
OA21XLTS U10307 ( .A0(n10467), .A1(n10260), .B0(n10259), .Y(n10261) );
XNOR2X1TS U10308 ( .A(n10267), .B(n10266), .Y(n10499) );
INVX2TS U10309 ( .A(n10556), .Y(n10796) );
AOI21X1TS U10310 ( .A0(n10298), .A1(n10270), .B0(n10269), .Y(n10271) );
OAI21X1TS U10311 ( .A0(n10299), .A1(n10272), .B0(n10271), .Y(n10290) );
NAND2X1TS U10312 ( .A(n10274), .B(n11602), .Y(n10278) );
NAND2X1TS U10313 ( .A(n10276), .B(n11602), .Y(n10277) );
AOI21X1TS U10314 ( .A0(n10282), .A1(n530), .B0(n10280), .Y(n10283) );
CMPR32X2TS U10315 ( .A(n9917), .B(n10286), .C(n10285), .CO(n10287), .S(
n10248) );
NAND2BX1TS U10316 ( .AN(n10295), .B(n10293), .Y(n10289) );
XNOR2X1TS U10317 ( .A(n10290), .B(n10289), .Y(n10505) );
NAND2X1TS U10318 ( .A(n10292), .B(n10297), .Y(n10307) );
AOI21X1TS U10319 ( .A0(n10298), .A1(n10297), .B0(n10296), .Y(n10310) );
CMPR32X2TS U10320 ( .A(n9851), .B(n10301), .C(n10300), .CO(n10303), .S(
n10288) );
NAND2X1TS U10321 ( .A(n10304), .B(n10308), .Y(n10305) );
XNOR2X1TS U10322 ( .A(n10306), .B(n10305), .Y(n10506) );
INVX2TS U10323 ( .A(n10671), .Y(n10546) );
INVX2TS U10324 ( .A(n10546), .Y(n10795) );
NAND2X1TS U10325 ( .A(n10320), .B(n10704), .Y(n10323) );
NAND2X1TS U10326 ( .A(n10715), .B(n10321), .Y(n10750) );
NAND2X1TS U10327 ( .A(n10322), .B(n10738), .Y(n10725) );
NAND2X1TS U10328 ( .A(n10795), .B(n10509), .Y(n10511) );
XNOR2X1TS U10329 ( .A(n10331), .B(n10330), .Y(n10356) );
AOI21X1TS U10330 ( .A0(n10339), .A1(n10338), .B0(n10337), .Y(n10343) );
XNOR2X1TS U10331 ( .A(n10343), .B(n10342), .Y(n10353) );
NAND2X1TS U10332 ( .A(n11035), .B(n11018), .Y(n11022) );
NAND2X1TS U10333 ( .A(n10349), .B(n11010), .Y(n10352) );
AOI21X1TS U10334 ( .A0(n10349), .A1(n11009), .B0(n10348), .Y(n10350) );
NAND2X1TS U10335 ( .A(n10353), .B(n11515), .Y(n11030) );
NOR2BX1TS U10336 ( .AN(n10354), .B(n11543), .Y(n11033) );
AOI21X1TS U10337 ( .A0(n11035), .A1(n10355), .B0(n11033), .Y(n11021) );
NAND2X1TS U10338 ( .A(n10356), .B(n11516), .Y(n11024) );
NAND2X1TS U10339 ( .A(n10362), .B(n10359), .Y(n10360) );
XNOR2X1TS U10340 ( .A(n10361), .B(n10360), .Y(n10377) );
NAND2X1TS U10341 ( .A(n11047), .B(n11049), .Y(n10382) );
NAND2X1TS U10342 ( .A(n10377), .B(n11519), .Y(n11042) );
NAND2X1TS U10343 ( .A(n10378), .B(n11517), .Y(n11056) );
OAI2BB1X1TS U10344 ( .A0N(n11057), .A1N(n11053), .B0(n11056), .Y(n11046) );
NAND2X1TS U10345 ( .A(n10379), .B(n11532), .Y(n11048) );
AOI21X1TS U10346 ( .A0(n11046), .A1(n11049), .B0(n10380), .Y(n10381) );
NAND2X1TS U10347 ( .A(n10388), .B(n10387), .Y(n10389) );
XNOR2X1TS U10348 ( .A(n10390), .B(n10389), .Y(n10396) );
NAND2X1TS U10349 ( .A(n10407), .B(n10394), .Y(n10395) );
XNOR2X1TS U10350 ( .A(n10432), .B(n10395), .Y(n10397) );
NOR2X1TS U10351 ( .A(n10397), .B(n11491), .Y(n11067) );
NAND2X1TS U10352 ( .A(n10396), .B(n11518), .Y(n11064) );
NAND2X1TS U10353 ( .A(n10397), .B(n11492), .Y(n11068) );
OA21XLTS U10354 ( .A0(n11067), .A1(n11064), .B0(n11068), .Y(n10398) );
OA21XLTS U10355 ( .A0(n10402), .A1(n10426), .B0(n10428), .Y(n10405) );
NAND2X1TS U10356 ( .A(n10403), .B(n10427), .Y(n10404) );
AOI21X1TS U10357 ( .A0(n10432), .A1(n10407), .B0(n10406), .Y(n10411) );
NAND2X1TS U10358 ( .A(n10409), .B(n10408), .Y(n10410) );
NAND2X1TS U10359 ( .A(n11084), .B(n11079), .Y(n10416) );
INVX2TS U10360 ( .A(n11080), .Y(n11074) );
NAND2X1TS U10361 ( .A(n10413), .B(n11486), .Y(n11083) );
OAI21X1TS U10362 ( .A0(n11082), .A1(n10416), .B0(n10415), .Y(n11094) );
NAND2X1TS U10363 ( .A(n10455), .B(n10453), .Y(n10420) );
XNOR2X1TS U10364 ( .A(n10421), .B(n10420), .Y(n10445) );
XNOR2X1TS U10365 ( .A(n10425), .B(n10424), .Y(n10444) );
NAND2X1TS U10366 ( .A(n10447), .B(n11116), .Y(n10449) );
AOI21X1TS U10367 ( .A0(n10432), .A1(n10431), .B0(n10430), .Y(n10437) );
NAND2X1TS U10368 ( .A(n10435), .B(n10434), .Y(n10436) );
NAND2X1TS U10369 ( .A(n11093), .B(n11096), .Y(n11113) );
NAND2X1TS U10370 ( .A(n10442), .B(n11506), .Y(n11095) );
AOI21X1TS U10371 ( .A0(n11096), .A1(n11092), .B0(n10443), .Y(n11112) );
NAND2X1TS U10372 ( .A(n10444), .B(n11514), .Y(n11115) );
NAND2X1TS U10373 ( .A(n10445), .B(n11512), .Y(n11106) );
AOI21X1TS U10374 ( .A0(n10447), .A1(n11102), .B0(n10446), .Y(n10448) );
AOI21X1TS U10375 ( .A0(n11094), .A1(n10451), .B0(n10450), .Y(n11121) );
AOI21X1TS U10376 ( .A0(n10456), .A1(n10455), .B0(n10454), .Y(n10457) );
XNOR2X1TS U10377 ( .A(n10462), .B(n10461), .Y(n10490) );
NAND2X1TS U10378 ( .A(n10470), .B(n10468), .Y(n10465) );
XNOR2X1TS U10379 ( .A(n10466), .B(n10465), .Y(n10491) );
AOI21X1TS U10380 ( .A0(n10480), .A1(n10470), .B0(n10469), .Y(n10471) );
XNOR2X1TS U10381 ( .A(n10476), .B(n10475), .Y(n10492) );
AOI21X1TS U10382 ( .A0(n10480), .A1(n10479), .B0(n10478), .Y(n10481) );
NAND2X1TS U10383 ( .A(n10487), .B(n10486), .Y(n10488) );
XNOR2X1TS U10384 ( .A(n10489), .B(n10488), .Y(n10493) );
NAND2X1TS U10385 ( .A(n11139), .B(n10496), .Y(n10498) );
NAND2X1TS U10386 ( .A(n10490), .B(n11488), .Y(n11126) );
NAND2X1TS U10387 ( .A(n10491), .B(n11487), .Y(n11130) );
NAND2X1TS U10388 ( .A(n10492), .B(n11484), .Y(n11142) );
AOI21X1TS U10389 ( .A0(n10496), .A1(n11141), .B0(n10495), .Y(n10497) );
NAND2X1TS U10390 ( .A(n10499), .B(n11485), .Y(n11163) );
NAND2X1TS U10391 ( .A(n10500), .B(n11478), .Y(n11167) );
NAND2X1TS U10392 ( .A(n10501), .B(n11479), .Y(n11159) );
NAND2X1TS U10393 ( .A(n10502), .B(n11474), .Y(n11181) );
INVX2TS U10394 ( .A(n10805), .Y(n10756) );
NAND2X1TS U10395 ( .A(n10505), .B(n11477), .Y(n10588) );
NAND2X1TS U10396 ( .A(n10506), .B(n11475), .Y(n10541) );
INVX2TS U10397 ( .A(n10783), .Y(n10530) );
INVX2TS U10398 ( .A(n10530), .Y(n10802) );
AOI21X1TS U10399 ( .A0(n10802), .A1(n10509), .B0(n10508), .Y(n10510) );
AOI21X1TS U10400 ( .A0(n10513), .A1(n11158), .B0(n10512), .Y(n10514) );
XNOR2X1TS U10401 ( .A(n10514), .B(n10660), .Y(n10515) );
OAI2BB1X1TS U10402 ( .A0N(n119), .A1N(n10515), .B0(n11715), .Y(
sgf_result_o[96]) );
INVX2TS U10403 ( .A(n10556), .Y(n10763) );
AOI21X1TS U10404 ( .A0(n10802), .A1(n10517), .B0(n10516), .Y(n10518) );
AOI21X1TS U10405 ( .A0(n10521), .A1(n11158), .B0(n10520), .Y(n10522) );
OAI2BB1X1TS U10406 ( .A0N(n121), .A1N(n10523), .B0(n11698), .Y(
sgf_result_o[84]) );
INVX2TS U10407 ( .A(n10530), .Y(n10766) );
AOI21X1TS U10408 ( .A0(n10766), .A1(n10547), .B0(n10594), .Y(n10524) );
AOI21X1TS U10409 ( .A0(n10527), .A1(n11158), .B0(n10526), .Y(n10528) );
OAI2BB1X1TS U10410 ( .A0N(n120), .A1N(n10529), .B0(n11709), .Y(
sgf_result_o[83]) );
AOI21X1TS U10411 ( .A0(n10532), .A1(n11158), .B0(n10531), .Y(n10534) );
OAI2BB1X1TS U10412 ( .A0N(n113), .A1N(n10535), .B0(n11708), .Y(
sgf_result_o[82]) );
AOI21X1TS U10413 ( .A0(n10539), .A1(n11158), .B0(n10538), .Y(n10544) );
OAI2BB1X1TS U10414 ( .A0N(n113), .A1N(n10545), .B0(n11718), .Y(
sgf_result_o[81]) );
INVX2TS U10415 ( .A(n10546), .Y(n10762) );
NAND2X1TS U10416 ( .A(n10762), .B(n10549), .Y(n10551) );
AOI21X1TS U10417 ( .A0(n10766), .A1(n10549), .B0(n10548), .Y(n10550) );
AOI21X1TS U10418 ( .A0(n10553), .A1(n11158), .B0(n10552), .Y(n10554) );
OAI2BB1X1TS U10419 ( .A0N(n121), .A1N(n10555), .B0(n11705), .Y(
sgf_result_o[85]) );
INVX2TS U10420 ( .A(n10556), .Y(n10672) );
NAND2X1TS U10421 ( .A(n10685), .B(n10558), .Y(n10616) );
NAND2X1TS U10422 ( .A(n10637), .B(n10645), .Y(n10673) );
NOR2XLTS U10423 ( .A(n10626), .B(n10560), .Y(n10562) );
AOI21X1TS U10424 ( .A0(n10802), .A1(n10562), .B0(n10561), .Y(n10563) );
AOI21X1TS U10425 ( .A0(n10566), .A1(n11158), .B0(n10565), .Y(n10567) );
OAI2BB1X1TS U10426 ( .A0N(n113), .A1N(n10568), .B0(n11702), .Y(
sgf_result_o[107]) );
NAND2X1TS U10427 ( .A(n10762), .B(n10572), .Y(n10574) );
AOI21X1TS U10428 ( .A0(n10783), .A1(n10572), .B0(n10571), .Y(n10573) );
AOI21X1TS U10429 ( .A0(n10576), .A1(n11158), .B0(n10575), .Y(n10577) );
OAI2BB1X1TS U10430 ( .A0N(n120), .A1N(n10578), .B0(n11710), .Y(
sgf_result_o[88]) );
NAND2X1TS U10431 ( .A(n10762), .B(n10581), .Y(n10583) );
AOI21X1TS U10432 ( .A0(n10766), .A1(n10581), .B0(n10580), .Y(n10582) );
AOI21X1TS U10433 ( .A0(n10585), .A1(n11158), .B0(n10584), .Y(n10586) );
OAI2BB1X1TS U10434 ( .A0N(n121), .A1N(n10587), .B0(n11699), .Y(
sgf_result_o[90]) );
NAND2X1TS U10435 ( .A(n10589), .B(n10588), .Y(n10590) );
NOR2XLTS U10436 ( .A(n10626), .B(n10595), .Y(n10597) );
AOI21X1TS U10437 ( .A0(n10802), .A1(n10597), .B0(n10596), .Y(n10598) );
AOI21X1TS U10438 ( .A0(n10601), .A1(n10807), .B0(n10600), .Y(n10603) );
XNOR2X1TS U10439 ( .A(n10603), .B(n10602), .Y(n10604) );
OAI2BB1X1TS U10440 ( .A0N(n120), .A1N(n10604), .B0(n11701), .Y(
sgf_result_o[104]) );
NOR2XLTS U10441 ( .A(n10626), .B(n10606), .Y(n10608) );
AOI21X1TS U10442 ( .A0(n10802), .A1(n10608), .B0(n10607), .Y(n10609) );
AOI21X1TS U10443 ( .A0(n10612), .A1(n10807), .B0(n10611), .Y(n10614) );
XNOR2X1TS U10444 ( .A(n10614), .B(n10613), .Y(n10615) );
OAI2BB1X1TS U10445 ( .A0N(n121), .A1N(n10615), .B0(n11703), .Y(
sgf_result_o[105]) );
NAND2X1TS U10446 ( .A(n10795), .B(n10618), .Y(n10620) );
AOI21X1TS U10447 ( .A0(n10766), .A1(n10618), .B0(n10617), .Y(n10619) );
AOI21X1TS U10448 ( .A0(n10622), .A1(n10807), .B0(n10621), .Y(n10624) );
XNOR2X1TS U10449 ( .A(n10624), .B(n10623), .Y(n10625) );
OAI2BB1X1TS U10450 ( .A0N(n120), .A1N(n10625), .B0(n11700), .Y(
sgf_result_o[101]) );
NOR2XLTS U10451 ( .A(n10626), .B(n10627), .Y(n10629) );
AOI21X1TS U10452 ( .A0(n10802), .A1(n10629), .B0(n10628), .Y(n10630) );
AOI21X1TS U10453 ( .A0(n10633), .A1(n10807), .B0(n10632), .Y(n10635) );
XNOR2X1TS U10454 ( .A(n10635), .B(n10634), .Y(n10636) );
OAI2BB1X1TS U10455 ( .A0N(n113), .A1N(n10636), .B0(n11704), .Y(
sgf_result_o[106]) );
NAND2X1TS U10456 ( .A(n10795), .B(n10640), .Y(n10642) );
AOI21X1TS U10457 ( .A0(n10783), .A1(n10640), .B0(n10639), .Y(n10641) );
AOI21X1TS U10458 ( .A0(n10644), .A1(n10807), .B0(n10643), .Y(n10646) );
XNOR2X1TS U10459 ( .A(n10646), .B(n10645), .Y(n10647) );
OAI2BB1X1TS U10460 ( .A0N(n120), .A1N(n10647), .B0(n11691), .Y(
sgf_result_o[102]) );
NAND2X1TS U10461 ( .A(n10795), .B(n10652), .Y(n10654) );
AOI21X1TS U10462 ( .A0(n10802), .A1(n10652), .B0(n10651), .Y(n10653) );
AOI21X1TS U10463 ( .A0(n10656), .A1(n10807), .B0(n10655), .Y(n10658) );
XNOR2X1TS U10464 ( .A(n10658), .B(n10657), .Y(n10659) );
OAI2BB1X1TS U10465 ( .A0N(n121), .A1N(n10659), .B0(n11706), .Y(
sgf_result_o[98]) );
NAND2X1TS U10466 ( .A(n10795), .B(n10663), .Y(n10665) );
AOI21X1TS U10467 ( .A0(n10783), .A1(n10663), .B0(n10662), .Y(n10664) );
AOI21X1TS U10468 ( .A0(n10667), .A1(n10807), .B0(n10666), .Y(n10669) );
XNOR2X1TS U10469 ( .A(n10669), .B(n10668), .Y(n10670) );
OAI2BB1X1TS U10470 ( .A0N(n119), .A1N(n10670), .B0(n11716), .Y(
sgf_result_o[97]) );
AOI21X1TS U10471 ( .A0(n10802), .A1(n10675), .B0(n10674), .Y(n10676) );
AOI21X1TS U10472 ( .A0(n10679), .A1(n10807), .B0(n10678), .Y(n10681) );
OAI2BB1X1TS U10473 ( .A0N(n121), .A1N(n10682), .B0(n11689), .Y(
sgf_result_o[103]) );
INVX2TS U10474 ( .A(n10793), .Y(n10686) );
NAND2X1TS U10475 ( .A(n10795), .B(n10688), .Y(n10690) );
AOI21X1TS U10476 ( .A0(n10802), .A1(n10688), .B0(n10687), .Y(n10689) );
AOI21X1TS U10477 ( .A0(n10692), .A1(n10807), .B0(n10691), .Y(n10693) );
OAI2BB1X1TS U10478 ( .A0N(n120), .A1N(n10694), .B0(n11707), .Y(
sgf_result_o[99]) );
NAND2X1TS U10479 ( .A(n10762), .B(n10697), .Y(n10699) );
AOI21X1TS U10480 ( .A0(n10766), .A1(n10697), .B0(n10696), .Y(n10698) );
AOI21X1TS U10481 ( .A0(n10701), .A1(n11179), .B0(n10700), .Y(n10702) );
XNOR2X1TS U10482 ( .A(n10702), .B(n10726), .Y(n10703) );
OAI2BB1X1TS U10483 ( .A0N(n120), .A1N(n10703), .B0(n11712), .Y(
sgf_result_o[92]) );
NAND2X1TS U10484 ( .A(n10762), .B(n10708), .Y(n10710) );
AOI21X1TS U10485 ( .A0(n10766), .A1(n10708), .B0(n10707), .Y(n10709) );
AOI21X1TS U10486 ( .A0(n10712), .A1(n11179), .B0(n10711), .Y(n10713) );
XNOR2X1TS U10487 ( .A(n10713), .B(n10776), .Y(n10714) );
OAI2BB1X1TS U10488 ( .A0N(n119), .A1N(n10714), .B0(n11713), .Y(
sgf_result_o[94]) );
NAND2X1TS U10489 ( .A(n10762), .B(n10718), .Y(n10720) );
AOI21X1TS U10490 ( .A0(n10766), .A1(n10718), .B0(n10717), .Y(n10719) );
AOI21X1TS U10491 ( .A0(n10722), .A1(n11179), .B0(n10721), .Y(n10723) );
OAI2BB1X1TS U10492 ( .A0N(n119), .A1N(n10724), .B0(n11696), .Y(
sgf_result_o[87]) );
NAND2X1TS U10493 ( .A(n10762), .B(n10730), .Y(n10732) );
AOI21X1TS U10494 ( .A0(n10766), .A1(n10730), .B0(n10729), .Y(n10731) );
AOI21X1TS U10495 ( .A0(n10734), .A1(n11179), .B0(n10733), .Y(n10735) );
OAI2BB1X1TS U10496 ( .A0N(n119), .A1N(n10736), .B0(n11692), .Y(
sgf_result_o[93]) );
NAND2X1TS U10497 ( .A(n10762), .B(n10741), .Y(n10743) );
AOI21X1TS U10498 ( .A0(n10766), .A1(n10741), .B0(n10740), .Y(n10742) );
AOI21X1TS U10499 ( .A0(n10746), .A1(n11179), .B0(n10745), .Y(n10748) );
OAI2BB1X1TS U10500 ( .A0N(n119), .A1N(n10749), .B0(n11697), .Y(
sgf_result_o[91]) );
NAND2X1TS U10501 ( .A(n10762), .B(n10753), .Y(n10755) );
AOI21X1TS U10502 ( .A0(n10766), .A1(n10753), .B0(n10752), .Y(n10754) );
AOI21X1TS U10503 ( .A0(n10758), .A1(n11179), .B0(n10757), .Y(n10759) );
OAI2BB1X1TS U10504 ( .A0N(n119), .A1N(n10760), .B0(n11711), .Y(
sgf_result_o[89]) );
NAND2X1TS U10505 ( .A(n10762), .B(n10765), .Y(n10768) );
OR2X2TS U10506 ( .A(n10763), .B(n10768), .Y(n10772) );
AOI21X1TS U10507 ( .A0(n10783), .A1(n10765), .B0(n10764), .Y(n10767) );
NAND2X1TS U10508 ( .A(n11633), .B(n11632), .Y(n10774) );
OAI2BB1X1TS U10509 ( .A0N(n120), .A1N(n10775), .B0(n10774), .Y(
sgf_result_o[86]) );
NAND2X1TS U10510 ( .A(n10795), .B(n10782), .Y(n10778) );
AOI21X1TS U10511 ( .A0(n10787), .A1(n11179), .B0(n10786), .Y(n10790) );
OAI2BB1X1TS U10512 ( .A0N(n119), .A1N(n10791), .B0(n11714), .Y(
sgf_result_o[95]) );
NAND2X1TS U10513 ( .A(n10795), .B(n10801), .Y(n10797) );
AOI21X1TS U10514 ( .A0(n10808), .A1(n10807), .B0(n10806), .Y(n10810) );
XNOR2X1TS U10515 ( .A(n10810), .B(n10809), .Y(n10811) );
NAND2X1TS U10516 ( .A(n11725), .B(sgf_result_o[24]), .Y(n10812) );
OAI2BB1X1TS U10517 ( .A0N(n1553), .A1N(n10813), .B0(n10812), .Y(n86) );
OAI2BB1X1TS U10518 ( .A0N(sgf_result_o[25]), .A1N(n11728), .B0(n10814), .Y(
n85) );
OAI2BB1X1TS U10519 ( .A0N(sgf_result_o[26]), .A1N(n11729), .B0(n10816), .Y(
n84) );
OAI2BB1X1TS U10520 ( .A0N(n11639), .A1N(n11637), .B0(n11638), .Y(
sgf_result_o[27]) );
XNOR2X1TS U10521 ( .A(n11503), .B(n11504), .Y(n10817) );
OAI2BB1X1TS U10522 ( .A0N(n11640), .A1N(n11637), .B0(n10818), .Y(
sgf_result_o[28]) );
XNOR2X1TS U10523 ( .A(n11542), .B(n11497), .Y(n10819) );
OAI2BB1X1TS U10524 ( .A0N(n11641), .A1N(n11637), .B0(n10820), .Y(
sgf_result_o[29]) );
XNOR2X1TS U10525 ( .A(n10823), .B(n10822), .Y(n10824) );
OAI2BB1X1TS U10526 ( .A0N(n11642), .A1N(n11637), .B0(n10825), .Y(
sgf_result_o[31]) );
NAND2X1TS U10527 ( .A(n10831), .B(n10826), .Y(n10827) );
XNOR2X1TS U10528 ( .A(n10839), .B(n10827), .Y(n10828) );
OAI2BB1X1TS U10529 ( .A0N(n11644), .A1N(n125), .B0(n10829), .Y(
sgf_result_o[32]) );
AOI21X1TS U10530 ( .A0(n10839), .A1(n10831), .B0(n10830), .Y(n10835) );
XNOR2X1TS U10531 ( .A(n10835), .B(n10834), .Y(n10836) );
OAI2BB1X1TS U10532 ( .A0N(n11631), .A1N(n10836), .B0(n11645), .Y(
sgf_result_o[33]) );
OAI2BB1X1TS U10533 ( .A0N(n11631), .A1N(n10843), .B0(n11646), .Y(
sgf_result_o[34]) );
AOI21X1TS U10534 ( .A0(n10855), .A1(n10845), .B0(n10844), .Y(n10849) );
XNOR2X1TS U10535 ( .A(n10849), .B(n10848), .Y(n10850) );
OAI2BB1X1TS U10536 ( .A0N(n11647), .A1N(n124), .B0(n10851), .Y(
sgf_result_o[35]) );
INVX2TS U10537 ( .A(n10852), .Y(n10854) );
XNOR2X1TS U10538 ( .A(n10859), .B(n10858), .Y(n10860) );
OAI2BB1X1TS U10539 ( .A0N(n11648), .A1N(n125), .B0(n10861), .Y(
sgf_result_o[36]) );
NAND2X1TS U10540 ( .A(n10864), .B(n10863), .Y(n10865) );
XNOR2X1TS U10541 ( .A(n10871), .B(n10865), .Y(n10866) );
NAND2X1TS U10542 ( .A(n10866), .B(n11634), .Y(n10867) );
OAI2BB1X1TS U10543 ( .A0N(n11649), .A1N(n11637), .B0(n10867), .Y(
sgf_result_o[37]) );
OAI2BB1X1TS U10544 ( .A0N(n10871), .A1N(n10870), .B0(n10869), .Y(n10872) );
INVX2TS U10545 ( .A(n10872), .Y(n10877) );
OAI2BB1X1TS U10546 ( .A0N(n11631), .A1N(n10878), .B0(n11650), .Y(
sgf_result_o[39]) );
NOR2BX1TS U10547 ( .AN(n10888), .B(n10887), .Y(n10879) );
XNOR2X1TS U10548 ( .A(n10880), .B(n10879), .Y(n10881) );
OAI2BB1X1TS U10549 ( .A0N(n11631), .A1N(n10881), .B0(n11652), .Y(
sgf_result_o[40]) );
NOR2BX1TS U10550 ( .AN(n10898), .B(n10897), .Y(n10883) );
OAI2BB1X1TS U10551 ( .A0N(n11653), .A1N(n124), .B0(n10886), .Y(
sgf_result_o[42]) );
NOR2BX1TS U10552 ( .AN(n10890), .B(n10889), .Y(n10891) );
OAI2BB1X1TS U10553 ( .A0N(n11654), .A1N(n125), .B0(n10894), .Y(
sgf_result_o[41]) );
NOR2BX1TS U10554 ( .AN(n10896), .B(n10895), .Y(n10901) );
XNOR2X1TS U10555 ( .A(n10907), .B(n10906), .Y(n10908) );
OAI2BB1X1TS U10556 ( .A0N(n11655), .A1N(n11637), .B0(n10909), .Y(
sgf_result_o[43]) );
NAND2X1TS U10557 ( .A(n10926), .B(n10910), .Y(n10911) );
XNOR2X1TS U10558 ( .A(n10927), .B(n10911), .Y(n10912) );
OAI2BB1X1TS U10559 ( .A0N(n11656), .A1N(n124), .B0(n10913), .Y(
sgf_result_o[44]) );
NAND2X1TS U10560 ( .A(n10934), .B(n10916), .Y(n10918) );
AOI21X1TS U10561 ( .A0(n10935), .A1(n10916), .B0(n10938), .Y(n10917) );
OA21XLTS U10562 ( .A0(n10937), .A1(n10918), .B0(n10917), .Y(n10923) );
OAI2BB1X1TS U10563 ( .A0N(n11631), .A1N(n10924), .B0(n11657), .Y(
sgf_result_o[47]) );
XNOR2X1TS U10564 ( .A(n10932), .B(n10931), .Y(n10933) );
OAI2BB1X1TS U10565 ( .A0N(n11631), .A1N(n10933), .B0(n11658), .Y(
sgf_result_o[45]) );
OAI2BB1X1TS U10566 ( .A0N(n11631), .A1N(n10942), .B0(n11659), .Y(
sgf_result_o[46]) );
XNOR2X1TS U10567 ( .A(n10990), .B(n10943), .Y(n10944) );
OAI2BB1X1TS U10568 ( .A0N(n11630), .A1N(n10944), .B0(n11660), .Y(
sgf_result_o[48]) );
OAI2BB1X1TS U10569 ( .A0N(n10973), .A1N(n10984), .B0(n10987), .Y(n10948) );
NAND2X1TS U10570 ( .A(n10983), .B(n10946), .Y(n10947) );
XNOR2X1TS U10571 ( .A(n10948), .B(n10947), .Y(n10949) );
OAI2BB1X1TS U10572 ( .A0N(n11661), .A1N(n124), .B0(n10950), .Y(
sgf_result_o[52]) );
XNOR2X1TS U10573 ( .A(n10957), .B(n10956), .Y(n10958) );
OAI2BB1X1TS U10574 ( .A0N(n11662), .A1N(n11635), .B0(n10959), .Y(
sgf_result_o[49]) );
OAI2BB1X1TS U10575 ( .A0N(n10973), .A1N(n10960), .B0(n10970), .Y(n10962) );
XNOR2X1TS U10576 ( .A(n10962), .B(n10961), .Y(n10963) );
OAI2BB1X1TS U10577 ( .A0N(n11663), .A1N(n125), .B0(n10964), .Y(
sgf_result_o[50]) );
OAI2BB1X1TS U10578 ( .A0N(n10973), .A1N(n10972), .B0(n10971), .Y(n10980) );
NOR2BX1TS U10579 ( .AN(n10977), .B(n10976), .Y(n10978) );
XNOR2X1TS U10580 ( .A(n10980), .B(n10979), .Y(n10981) );
OAI2BB1X1TS U10581 ( .A0N(n11664), .A1N(n124), .B0(n10982), .Y(
sgf_result_o[51]) );
NAND2X1TS U10582 ( .A(n10984), .B(n10983), .Y(n10989) );
NAND2X1TS U10583 ( .A(n10992), .B(n10991), .Y(n10993) );
XNOR2X1TS U10584 ( .A(n10994), .B(n10993), .Y(n10995) );
OAI2BB1X1TS U10585 ( .A0N(n11665), .A1N(n125), .B0(n10996), .Y(
sgf_result_o[53]) );
INVX2TS U10586 ( .A(n10997), .Y(n11002) );
XNOR2X1TS U10587 ( .A(n11011), .B(n10999), .Y(n11000) );
OAI2BB1X1TS U10588 ( .A0N(n11666), .A1N(n125), .B0(n11001), .Y(
sgf_result_o[54]) );
AOI21X1TS U10589 ( .A0(n11011), .A1(n11003), .B0(n11002), .Y(n11007) );
NAND2X1TS U10590 ( .A(n11005), .B(n11004), .Y(n11006) );
OAI2BB1X1TS U10591 ( .A0N(n11630), .A1N(n11008), .B0(n11667), .Y(
sgf_result_o[55]) );
AOI21X1TS U10592 ( .A0(n11011), .A1(n11010), .B0(n11009), .Y(n11015) );
OAI2BB1X1TS U10593 ( .A0N(n11630), .A1N(n11016), .B0(n11668), .Y(
sgf_result_o[56]) );
INVX2TS U10594 ( .A(n11017), .Y(n11032) );
NAND2X1TS U10595 ( .A(n11018), .B(n11030), .Y(n11019) );
OAI2BB1X1TS U10596 ( .A0N(n11630), .A1N(n11020), .B0(n11670), .Y(
sgf_result_o[58]) );
NAND2X1TS U10597 ( .A(n11025), .B(n11024), .Y(n11026) );
XNOR2X1TS U10598 ( .A(n11027), .B(n11026), .Y(n11028) );
OAI2BB1X1TS U10599 ( .A0N(n11671), .A1N(n124), .B0(n11029), .Y(
sgf_result_o[60]) );
NAND2X1TS U10600 ( .A(n11035), .B(n11034), .Y(n11036) );
XNOR2X1TS U10601 ( .A(n11037), .B(n11036), .Y(n11038) );
OAI2BB1X1TS U10602 ( .A0N(n11672), .A1N(n125), .B0(n11039), .Y(
sgf_result_o[59]) );
INVX2TS U10603 ( .A(n11040), .Y(n11055) );
INVX2TS U10604 ( .A(n11041), .Y(n11054) );
NAND2X1TS U10605 ( .A(n11054), .B(n11042), .Y(n11043) );
XNOR2X1TS U10606 ( .A(n11055), .B(n11043), .Y(n11044) );
OAI2BB1X1TS U10607 ( .A0N(n11673), .A1N(n124), .B0(n11045), .Y(
sgf_result_o[61]) );
AOI21X1TS U10608 ( .A0(n11055), .A1(n11047), .B0(n11046), .Y(n11051) );
NAND2X1TS U10609 ( .A(n11049), .B(n11048), .Y(n11050) );
OAI2BB1X1TS U10610 ( .A0N(n11630), .A1N(n11052), .B0(n11674), .Y(
sgf_result_o[63]) );
NAND2X1TS U10611 ( .A(n11091), .B(sgf_result_o[63]), .Y(n11748) );
AOI21X1TS U10612 ( .A0(n11055), .A1(n11054), .B0(n11053), .Y(n11059) );
NAND2X1TS U10613 ( .A(n11057), .B(n11056), .Y(n11058) );
OAI2BB1X1TS U10614 ( .A0N(n11630), .A1N(n11060), .B0(n11675), .Y(
sgf_result_o[62]) );
NAND2X1TS U10615 ( .A(n11091), .B(sgf_result_o[62]), .Y(n11747) );
NAND2X1TS U10616 ( .A(n11061), .B(n11064), .Y(n11062) );
OAI2BB1X1TS U10617 ( .A0N(n11630), .A1N(n11063), .B0(n11676), .Y(
sgf_result_o[64]) );
NAND2X1TS U10618 ( .A(n11091), .B(sgf_result_o[64]), .Y(n11749) );
NAND2X1TS U10619 ( .A(n11069), .B(n11068), .Y(n11070) );
XNOR2X1TS U10620 ( .A(n11071), .B(n11070), .Y(n11072) );
OAI2BB1X1TS U10621 ( .A0N(n11677), .A1N(n124), .B0(n11073), .Y(
sgf_result_o[65]) );
NAND2X1TS U10622 ( .A(n11079), .B(n11074), .Y(n11075) );
XNOR2X1TS U10623 ( .A(n11076), .B(n11075), .Y(n11077) );
NAND2X1TS U10624 ( .A(n11077), .B(n11634), .Y(n11078) );
OAI2BB1X1TS U10625 ( .A0N(n11678), .A1N(n125), .B0(n11078), .Y(
sgf_result_o[66]) );
NAND2X1TS U10626 ( .A(n11084), .B(n11083), .Y(n11085) );
OAI2BB1X1TS U10627 ( .A0N(n11630), .A1N(n11087), .B0(n11679), .Y(
sgf_result_o[67]) );
NAND2X1TS U10628 ( .A(n11091), .B(sgf_result_o[67]), .Y(n11750) );
OAI2BB1X1TS U10629 ( .A0N(n11630), .A1N(n11090), .B0(n11680), .Y(
sgf_result_o[68]) );
NAND2X1TS U10630 ( .A(n11091), .B(sgf_result_o[68]), .Y(n11751) );
NAND2X1TS U10631 ( .A(n11096), .B(n11095), .Y(n11097) );
XNOR2X1TS U10632 ( .A(n11098), .B(n11097), .Y(n11099) );
OAI2BB1X1TS U10633 ( .A0N(n11681), .A1N(n11637), .B0(n11100), .Y(
sgf_result_o[69]) );
NAND2X1TS U10634 ( .A(n11101), .B(n11116), .Y(n11105) );
AOI21X1TS U10635 ( .A0(n11103), .A1(n11116), .B0(n11102), .Y(n11104) );
XNOR2X1TS U10636 ( .A(n11109), .B(n11108), .Y(n11110) );
OAI2BB1X1TS U10637 ( .A0N(n11682), .A1N(n11637), .B0(n11111), .Y(
sgf_result_o[71]) );
NAND2X1TS U10638 ( .A(n11116), .B(n11115), .Y(n11117) );
XNOR2X1TS U10639 ( .A(n11118), .B(n11117), .Y(n11119) );
OAI2BB1X1TS U10640 ( .A0N(n11683), .A1N(n11635), .B0(n11120), .Y(
sgf_result_o[70]) );
NAND2X1TS U10641 ( .A(n11128), .B(n11126), .Y(n11123) );
XNOR2X1TS U10642 ( .A(n11146), .B(n11123), .Y(n11124) );
OAI2BB1X1TS U10643 ( .A0N(n11684), .A1N(n11637), .B0(n11125), .Y(
sgf_result_o[72]) );
AOI21X1TS U10644 ( .A0(n11146), .A1(n11128), .B0(n11127), .Y(n11133) );
OAI2BB1X1TS U10645 ( .A0N(n114), .A1N(n11134), .B0(n11685), .Y(
sgf_result_o[73]) );
NAND2X1TS U10646 ( .A(n11186), .B(sgf_result_o[73]), .Y(n11752) );
AOI21X1TS U10647 ( .A0(n11146), .A1(n11139), .B0(n11141), .Y(n11137) );
NAND2X1TS U10648 ( .A(n11135), .B(n11142), .Y(n11136) );
OAI2BB1X1TS U10649 ( .A0N(n114), .A1N(n11138), .B0(n11686), .Y(
sgf_result_o[74]) );
NAND2X1TS U10650 ( .A(n11186), .B(sgf_result_o[74]), .Y(n11753) );
AOI21X1TS U10651 ( .A0(n11147), .A1(n11146), .B0(n11145), .Y(n11152) );
XNOR2X1TS U10652 ( .A(n11152), .B(n11151), .Y(n11153) );
OAI2BB1X1TS U10653 ( .A0N(n114), .A1N(n11153), .B0(n11687), .Y(
sgf_result_o[75]) );
NAND2X1TS U10654 ( .A(n11186), .B(sgf_result_o[75]), .Y(n11754) );
NAND2X1TS U10655 ( .A(n11165), .B(n11163), .Y(n11155) );
XNOR2X1TS U10656 ( .A(n11179), .B(n11155), .Y(n11156) );
OAI2BB1X1TS U10657 ( .A0N(n11688), .A1N(n124), .B0(n11157), .Y(
sgf_result_o[76]) );
INVX2TS U10658 ( .A(load_b_i), .Y(n11200) );
NAND2X1TS U10659 ( .A(n11200), .B(sgf_result_o[103]), .Y(n11780) );
AOI21X1TS U10660 ( .A0(n11158), .A1(n11173), .B0(n11176), .Y(n11161) );
OAI2BB1X1TS U10661 ( .A0N(n114), .A1N(n11162), .B0(n11690), .Y(
sgf_result_o[78]) );
NAND2X1TS U10662 ( .A(n11186), .B(sgf_result_o[78]), .Y(n11756) );
NAND2X1TS U10663 ( .A(n11200), .B(sgf_result_o[102]), .Y(n11779) );
INVX2TS U10664 ( .A(load_b_i), .Y(n11231) );
NAND2X1TS U10665 ( .A(n11231), .B(sgf_result_o[93]), .Y(n11770) );
AOI21X1TS U10666 ( .A0(n11179), .A1(n11165), .B0(n11164), .Y(n11170) );
NAND2X1TS U10667 ( .A(n11168), .B(n11167), .Y(n11169) );
OAI2BB1X1TS U10668 ( .A0N(n113), .A1N(n11171), .B0(n11693), .Y(
sgf_result_o[77]) );
NAND2X1TS U10669 ( .A(n11186), .B(sgf_result_o[77]), .Y(n11755) );
NAND2X1TS U10670 ( .A(n11725), .B(sgf_result_o[80]), .Y(n11758) );
AOI21X1TS U10671 ( .A0(n11179), .A1(n11178), .B0(n11177), .Y(n11184) );
OAI2BB1X1TS U10672 ( .A0N(n113), .A1N(n11185), .B0(n11695), .Y(
sgf_result_o[79]) );
NAND2X1TS U10673 ( .A(n11186), .B(sgf_result_o[79]), .Y(n11757) );
NAND2X1TS U10674 ( .A(n11725), .B(sgf_result_o[87]), .Y(n11764) );
NAND2X1TS U10675 ( .A(n11231), .B(sgf_result_o[91]), .Y(n11768) );
NAND2X1TS U10676 ( .A(n11725), .B(sgf_result_o[84]), .Y(n11762) );
NAND2X1TS U10677 ( .A(n11231), .B(sgf_result_o[90]), .Y(n11767) );
NAND2X1TS U10678 ( .A(n11200), .B(sgf_result_o[101]), .Y(n11778) );
NAND2X1TS U10679 ( .A(n11200), .B(sgf_result_o[104]), .Y(n11781) );
NAND2X1TS U10680 ( .A(n11200), .B(sgf_result_o[107]), .Y(n11784) );
NAND2X1TS U10681 ( .A(n11200), .B(sgf_result_o[105]), .Y(n11782) );
NAND2X1TS U10682 ( .A(n11200), .B(sgf_result_o[106]), .Y(n11783) );
NAND2X1TS U10683 ( .A(n11725), .B(sgf_result_o[85]), .Y(n11763) );
INVX2TS U10684 ( .A(load_b_i), .Y(n11217) );
NAND2X1TS U10685 ( .A(n11217), .B(sgf_result_o[98]), .Y(n11775) );
NAND2X1TS U10686 ( .A(n11217), .B(sgf_result_o[99]), .Y(n11776) );
NAND2X1TS U10687 ( .A(n11725), .B(sgf_result_o[82]), .Y(n11760) );
NAND2X1TS U10688 ( .A(n11725), .B(sgf_result_o[83]), .Y(n11761) );
NAND2X1TS U10689 ( .A(n11231), .B(sgf_result_o[88]), .Y(n11765) );
NAND2X1TS U10690 ( .A(n11231), .B(sgf_result_o[89]), .Y(n11766) );
NAND2X1TS U10691 ( .A(n11231), .B(sgf_result_o[92]), .Y(n11769) );
NAND2X1TS U10692 ( .A(n11217), .B(sgf_result_o[94]), .Y(n11771) );
NAND2X1TS U10693 ( .A(n11217), .B(sgf_result_o[95]), .Y(n11772) );
NAND2X1TS U10694 ( .A(n11217), .B(sgf_result_o[96]), .Y(n11773) );
NAND2X1TS U10695 ( .A(n11217), .B(sgf_result_o[97]), .Y(n11774) );
NAND2X1TS U10696 ( .A(n11200), .B(sgf_result_o[100]), .Y(n11777) );
NAND2X1TS U10697 ( .A(n11725), .B(sgf_result_o[81]), .Y(n11759) );
NAND2X1TS U10698 ( .A(n11231), .B(sgf_result_o[20]), .Y(n11187) );
OAI2BB1X1TS U10699 ( .A0N(load_b_i), .A1N(n11188), .B0(n11187), .Y(n90) );
NAND2X1TS U10700 ( .A(n11725), .B(sgf_result_o[23]), .Y(n11189) );
OAI2BB1X1TS U10701 ( .A0N(load_b_i), .A1N(n11190), .B0(n11189), .Y(n87) );
NAND2BXLTS U10702 ( .AN(n11726), .B(n11191), .Y(n11192) );
OAI2BB1X1TS U10703 ( .A0N(sgf_result_o[0]), .A1N(n11729), .B0(n11192), .Y(
n110) );
OAI2BB1X1TS U10704 ( .A0N(sgf_result_o[1]), .A1N(n11729), .B0(n11195), .Y(
n109) );
OAI2BB1X1TS U10705 ( .A0N(n11730), .A1N(n11197), .B0(n11196), .Y(n108) );
OAI2BB1X1TS U10706 ( .A0N(sgf_result_o[3]), .A1N(n11729), .B0(n11199), .Y(
n107) );
OAI2BB1X1TS U10707 ( .A0N(load_b_i), .A1N(n11202), .B0(n11201), .Y(n106) );
OAI2BB1X1TS U10708 ( .A0N(sgf_result_o[5]), .A1N(n11729), .B0(n11204), .Y(
n105) );
OAI2BB1X1TS U10709 ( .A0N(sgf_result_o[6]), .A1N(n11728), .B0(n11206), .Y(
n104) );
OAI2BB1X1TS U10710 ( .A0N(n1553), .A1N(n11208), .B0(n11207), .Y(n103) );
NAND2X1TS U10711 ( .A(n11217), .B(sgf_result_o[8]), .Y(n11209) );
OAI2BB1X1TS U10712 ( .A0N(n1553), .A1N(n11210), .B0(n11209), .Y(n102) );
OAI2BB1X1TS U10713 ( .A0N(sgf_result_o[9]), .A1N(n11728), .B0(n11212), .Y(
n101) );
OAI2BB1X1TS U10714 ( .A0N(sgf_result_o[10]), .A1N(n11728), .B0(n11214), .Y(
n100) );
NAND2X1TS U10715 ( .A(n11217), .B(sgf_result_o[11]), .Y(n11215) );
OAI2BB1X1TS U10716 ( .A0N(n1553), .A1N(n11216), .B0(n11215), .Y(n99) );
NAND2X1TS U10717 ( .A(n11217), .B(sgf_result_o[12]), .Y(n11218) );
OAI2BB1X1TS U10718 ( .A0N(n1553), .A1N(n11219), .B0(n11218), .Y(n98) );
OAI2BB1X1TS U10719 ( .A0N(sgf_result_o[13]), .A1N(n11728), .B0(n11221), .Y(
n97) );
OAI2BB1X1TS U10720 ( .A0N(sgf_result_o[14]), .A1N(n11729), .B0(n11223), .Y(
n96) );
NAND2X1TS U10721 ( .A(n11231), .B(sgf_result_o[15]), .Y(n11224) );
OAI2BB1X1TS U10722 ( .A0N(n1553), .A1N(n11225), .B0(n11224), .Y(n95) );
NAND2X1TS U10723 ( .A(n11231), .B(sgf_result_o[16]), .Y(n11226) );
OAI2BB1X1TS U10724 ( .A0N(n1553), .A1N(n11227), .B0(n11226), .Y(n94) );
OAI2BB1X1TS U10725 ( .A0N(sgf_result_o[17]), .A1N(n11728), .B0(n11229), .Y(
n93) );
OAI2BB1X1TS U10726 ( .A0N(sgf_result_o[18]), .A1N(n11728), .B0(n11230), .Y(
n92) );
NAND2X1TS U10727 ( .A(n11231), .B(sgf_result_o[19]), .Y(n11232) );
OAI2BB1X1TS U10728 ( .A0N(load_b_i), .A1N(n11233), .B0(n11232), .Y(n91) );
OAI2BB1X1TS U10729 ( .A0N(sgf_result_o[21]), .A1N(n11729), .B0(n11234), .Y(
n89) );
OAI2BB1X1TS U10730 ( .A0N(sgf_result_o[22]), .A1N(n11728), .B0(n11236), .Y(
n88) );
initial $sdf_annotate("RecursiveKOA_syn.sdf");
endmodule
|
`ifndef __DEFINE__
`define __DEFINE__
`ifndef intN
`define intN 32
`endif
`ifndef symN
`define symN 1
`endif
`ifndef anyN
`define anyN `intN
`endif
`ifndef addrN
`define addrN 16
`endif
`define intT [`intN-1:0]
`define symT [`symN-1:0]
`define anyT [`anyN-1:0]
`define addrT [`addrN-1:0]
`define sync_ports \
input wire clk, input wire nrst, \
input wire in_valid, output wire in_ready, \
output wire out_valid, input wire out_ready
`define id(x) x
`define concat_(a, b) `id(a)``_``b
`define stringify(x) `"x`"
`define rename(dst, src) wire src; assign dst = src
`define top_sync(ready) \
assign in_ready = ready
`define loop_sync(ready) \
reg active = `false; \
assign in_ready = ~active & ready
`define sync_wire(name) `concat_(`current_inst, name)
`define inst(t, n, p) \
`define current_inst n \
t p t``_``n
`define inst_sync(t, n, p) \
`define current_inst n \
wire `sync_wire(out_valid); \
t p t``_``n
`define apply(f, x) `f x
`define start_block(name) \
`define block name \
`define end_block(name) \
`undef block \
`define sync(valid, ready) \
.clk(clk), \
.nrst(nrst), \
.in_valid(valid), \
.out_valid(`sync_wire(out_valid)), \
.in_ready(`sync_wire(in_ready)), \
.out_ready(ready)
`define fst_(x, y) (x)
`define snd_(x, y) (y)
`define fst(p) `fst_``p
`define snd(p) `snd_``p
`define input(type, N, index) `input_``type(N, index)
`define input_simple(N, index) input wire [N-1:0] `id(in)``index
`define output(type, N, index) `output_``type(N, index)
`define output_simple(N, index) output wire [N-1:0] `id(out)``index
`define in(type, index, name) `in_``type(index, name)
`define out(type, index, name) `out_``type(index, name)
`define in_simple(index, name) .`id(in)``index(name)
`define out_simple(index, name) .`id(out)``index(name)
`define alias(type, N, name, index) `alias_``type(N, name, index)
`define alias_simple(N, name, other) wire [N-1:0] name = other
`define variable(type, N, name, in) `variable_``type(N, name, in)
`define variable_simple(N, name, in) reg [N-1:0] name
`define wire(type, N, name) `wire_``type(N, name)
`define wire_simple(N, name) wire [N-1:0] name
`define reg(type, N, name) `reg_``type(N, name)
`define reg_simple(N, name) reg [N-1:0] name
`define const(type, N, name, val) `const_``type(N, name, val)
`define const_simple(N, name, val) localparam [N-1:0] name = val
`define input_stream(N, index) input wire [N-1:0] in``index, input wire in``index``_valid, output wire in``index``_ready
`define output_stream(N, index) output wire [N-1:0] out``index, output wire out``index``_valid, input wire out``index``_ready
`define output_null_stream(N, index) output wire out``index``_valid, input wire out``index``_ready
`define in_stream(index, name) .in``index(name), .in``index``_valid(name``_valid), .in``index``_ready(name``_ready)
`define in_dup_stream(index, name) .in``index(name), .in``index``_valid(`concat_(`current_inst, name``_valid)), .in``index``_ready(`concat_(`current_inst, name``_ready))
`define in_null_stream(index, name) .in``index``_valid(name``_valid), .in``index``_ready(name``_ready)
`define in_dup_null_stream(index, name) .in``index``_valid(`concat_(`current_inst, name``_valid)), .in``index``_ready(`concat_(`current_inst, name``_ready))
`define out_stream(index, name) .out``index(name), .out``index``_valid(name``_valid), .out``index``_ready(name``_ready)
`define out_null_stream(index, name) .out``index``_valid(name``_valid), .out``index``_ready(name``_ready)
`define alias_stream(N, name, other) \
wire [N-1:0] name = other; \
wire name``_valid = other``_valid; wire name``_ready; \
assign other``_ready = name``_ready
`define variable_stream(N, name, in) \
wire [N-1:0] name = in; \
reg name``_valid_reg; \
wire name``_valid = in``_valid; \
`rename(in``_ready, name``_ready)
`define wire_stream(N, name) wire [N-1:0] name; wire name``_valid; wire name``_ready
`define wire_null_stream(N, name) wire name``_valid; wire name``_ready
`define reg_stream(N, name) reg [N-1:0] name; reg name``_valid; wire name``_ready
`define const_stream(N, name, val) localparam [N-1:0] name = val; localparam name``_valid = `true
`define const_nil(name) localparam name = 0; localparam name``_valid = `true; wire name``_ready
`define null_const_nil(name) localparam name``_valid = `true; wire name``_ready
`define in_alias(name, other) wire name; assign other = name
`define in_alias_vec(name, other) wire [$bits(other)-1:0] name; assign other = name
`define assign_stream(inst, name) \
`in_alias(inst``_``name``_ready, name``_ready); \
wire inst``_``name``_valid = name``_valid
`define assign_Array(inst, name) \
`assign_stream(inst, name); \
`in_alias_vec(inst``_``name``_addr, name``_addr); \
`in_alias_vec(inst``_``name``_di, name``_di); \
`in_alias(inst``_``name``_we, name``_we)
/* ------------------------------------------------------ *
ARRAY BUS
* ------------------------------------------------------ *
addr: address (*)
we: write enable (*)
di: data in (*)
(no suffix): data out
valid: data out is valid
ready: ready for data
NOTES:
-> when not ready, pass back signals:
addr, we, di, and ready
-> (*) => must be valid when ready
-> addr, we & di must be terminated low
to allow OR'ing and selecting with valid
* ------------------------------------------------------ */
// master
`define input_Array(N, index) \
output wire [`fst(N)-1:0] in``index``_addr, \
output wire in``index``_we, \
output wire [`snd(N)-1:0] in``index``_di, \
input wire [`snd(N)-1:0] in``index, \
input wire in``index``_valid, \
output wire in``index``_ready
// slave
`define output_Array(N, index) \
input wire [`fst(N)-1:0] out``index``_addr, \
input wire out``index``_we, \
input wire [`snd(N)-1:0] out``index``_di, \
output wire [`snd(N)-1:0] out``index, \
output wire out``index``_valid, \
input wire out``index``_ready
`define in_Array(index, name) \
.in``index``_addr(name``_addr), \
.in``index``_we(name``_we), \
.in``index``_di(name``_di), \
.in``index(name), \
.in``index``_valid(name``_valid), \
.in``index``_ready(name``_ready)
`define in_dup_Array(index, name) \
.in``index``_addr(`concat_(`current_inst, name``_addr)), \
.in``index``_we(`concat_(`current_inst, name``_we)), \
.in``index``_di(`concat_(`current_inst, name``_di)), \
.in``index(name), \
.in``index``_valid(`concat_(`current_inst, name``_valid)), \
.in``index``_ready(`concat_(`current_inst, name``_ready))
`define out_Array(index, name) \
.out``index``_addr(name``_addr), \
.out``index``_we(name``_we), \
.out``index``_di(name``_di), \
.out``index(name), \
.out``index``_valid(name``_valid), \
.out``index``_ready(name``_ready)
`define wire_Array(N, name) \
wire [`fst(N)-1:0] name``_addr; \
wire name``_we; \
wire [`snd(N)-1:0] name``_di; \
wire [`snd(N)-1:0] name; \
wire name``_valid; \
wire name``_ready
`define alias_Array(N, name, other) \
wire [`fst(N)-1:0] name``_addr; \
assign other``_addr = name``_addr; \
wire name``_we; \
assign other``_we = name``_we; \
wire [`snd(N)-1:0] name``_di; \
assign other``_di = name``_di; \
wire [`snd(N)-1:0] name = other; \
wire name``_valid = other``_valid; \
wire name``_ready; \
assign other``_ready = name``_ready
`define to_bus(name) {name``_addr, name``_we, name``_di, name``_ready}
`define true 1'b1
`define false 1'b0
`define nil (~(`intN'd0))
`define assert(n, x) \
`define current_inst n \
wire `sync_wire(out_valid) = (x)
`define set(x) x <= `true
`define reset(x) x <= `false
`define valid(x) (! (& x))
`define returned_to(name) (returned && return_addr == label_``name)
// make sure all labels are declared
`default_nettype none
`define testbench(tb_name, timeout) \
reg in_valid = 0; \
reg out_ready = 1; \
reg nrst = 0; \
reg clk = 0; \
reg start = 0; \
always begin \
#0.5 clk = !clk; \
end \
initial begin \
$dumpfile(`dumpfile); \
$dumpvars(0, tb_name); \
# timeout; \
$display("timed out"); \
$finish; \
end \
always @(posedge clk) begin \
if(in_ready & in_valid) begin \
`reset(in_valid); \
end \
end
`define wait_for(valid) \
@(posedge clk); \
while(!(valid)) @(posedge clk)
`define in_ready(inst) \
wire inst``_in_ready; \
wire in_ready = inst``_in_ready
`define start \
@(posedge clk); \
nrst = `false; \
@(posedge clk); \
nrst = `true; \
@(posedge clk); \
#0.01 in_valid = `true
`endif
`define dup_signals_stream(N, inst, name) \
wire inst``_``name``_valid; \
wire inst``_``name``_ready
`define dup_signals_Array(N, inst, name) \
wire inst``_``name``_valid; \
wire inst``_``name``_ready; \
wire [`fst(N)-1:0] inst``_``name``_addr; \
wire [`snd(N)-1:0] inst``_``name``_di; \
wire inst``_``name``_we
`define dup_signals(type, N, inst, name) `dup_signals_``type(N, inst, name)
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8)
`timescale 1ps/1ps
module ad_serdes_out #(
parameter DEVICE_TYPE = 0,
parameter DDR_OR_SDR_N = 1,
parameter SERDES_FACTOR = 8,
parameter DATA_WIDTH = 16) (
// reset and clocks
input rst,
input clk,
input div_clk,
input loaden,
// data interface
input [(DATA_WIDTH-1):0] data_s0,
input [(DATA_WIDTH-1):0] data_s1,
input [(DATA_WIDTH-1):0] data_s2,
input [(DATA_WIDTH-1):0] data_s3,
input [(DATA_WIDTH-1):0] data_s4,
input [(DATA_WIDTH-1):0] data_s5,
input [(DATA_WIDTH-1):0] data_s6,
input [(DATA_WIDTH-1):0] data_s7,
output [(DATA_WIDTH-1):0] data_out_se,
output [(DATA_WIDTH-1):0] data_out_p,
output [(DATA_WIDTH-1):0] data_out_n);
localparam DEVICE_7SERIES = 0;
localparam DR_OQ_DDR = DDR_OR_SDR_N == 1'b1 ? "DDR": "SDR";
// internal signals
wire [(DATA_WIDTH-1):0] data_out_s;
wire [(DATA_WIDTH-1):0] serdes_shift1_s;
wire [(DATA_WIDTH-1):0] serdes_shift2_s;
assign data_out_se = data_out_s;
// instantiations
genvar l_inst;
generate
for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
if (DEVICE_TYPE == DEVICE_7SERIES) begin
OSERDESE2 #(
.DATA_RATE_OQ (DR_OQ_DDR),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (SERDES_FACTOR),
.TRISTATE_WIDTH (1),
.SERDES_MODE ("MASTER"))
i_serdes (
.D1 (data_s0[l_inst]),
.D2 (data_s1[l_inst]),
.D3 (data_s2[l_inst]),
.D4 (data_s3[l_inst]),
.D5 (data_s4[l_inst]),
.D6 (data_s5[l_inst]),
.D7 (data_s6[l_inst]),
.D8 (data_s7[l_inst]),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.OCE (1'b1),
.CLK (clk),
.CLKDIV (div_clk),
.OQ (data_out_s[l_inst]),
.TQ (),
.OFB (),
.TFB (),
.TBYTEIN (1'b0),
.TBYTEOUT (),
.TCE (1'b0),
.RST (rst));
end
OBUFDS i_obuf (
.I (data_out_s[l_inst]),
.O (data_out_p[l_inst]),
.OB (data_out_n[l_inst]));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream Ethernet FCS checker
*/
module axis_eth_fcs_check
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [7:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire s_axis_tuser,
/*
* AXI output
*/
output wire [7:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire m_axis_tuser,
/*
* Status
*/
output wire busy,
output wire error_bad_fcs
);
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_PAYLOAD = 2'd1;
reg [1:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg shift_in;
reg shift_reset;
reg [7:0] s_axis_tdata_d0 = 8'd0;
reg [7:0] s_axis_tdata_d1 = 8'd0;
reg [7:0] s_axis_tdata_d2 = 8'd0;
reg [7:0] s_axis_tdata_d3 = 8'd0;
reg s_axis_tvalid_d0 = 1'b0;
reg s_axis_tvalid_d1 = 1'b0;
reg s_axis_tvalid_d2 = 1'b0;
reg s_axis_tvalid_d3 = 1'b0;
reg busy_reg = 1'b0;
reg error_bad_fcs_reg = 1'b0, error_bad_fcs_next;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg [31:0] crc_state = 32'hFFFFFFFF;
wire [31:0] crc_next;
// internal datapath
reg [7:0] m_axis_tdata_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg m_axis_tuser_int;
wire m_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg;
assign busy = busy_reg;
assign error_bad_fcs = error_bad_fcs_reg;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(s_axis_tdata_d3),
.state_in(crc_state),
.data_out(),
.state_out(crc_next)
);
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
shift_in = 1'b0;
shift_reset = 1'b0;
s_axis_tready_next = 1'b0;
m_axis_tdata_int = 8'd0;
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
error_bad_fcs_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
s_axis_tready_next = m_axis_tready_int_early;
reset_crc = 1'b1;
m_axis_tdata_int = s_axis_tdata_d3;
m_axis_tvalid_int = s_axis_tvalid_d3 && s_axis_tvalid;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
if (s_axis_tready && s_axis_tvalid) begin
shift_in = 1'b1;
if (s_axis_tvalid_d3) begin
reset_crc = 1'b0;
update_crc = 1'b1;
if (s_axis_tlast) begin
shift_reset = 1'b1;
reset_crc = 1'b1;
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = s_axis_tuser;
if ({s_axis_tdata, s_axis_tdata_d0, s_axis_tdata_d1, s_axis_tdata_d2} != ~crc_next) begin
m_axis_tuser_int = 1'b1;
error_bad_fcs_next = 1'b1;
end
s_axis_tready_next = m_axis_tready_int_early;
state_next = STATE_IDLE;
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// transfer payload
s_axis_tready_next = m_axis_tready_int_early;
m_axis_tdata_int = s_axis_tdata_d3;
m_axis_tvalid_int = s_axis_tvalid_d3 && s_axis_tvalid;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
if (s_axis_tready && s_axis_tvalid) begin
shift_in = 1'b1;
update_crc = 1'b1;
if (s_axis_tlast) begin
shift_reset = 1'b1;
reset_crc = 1'b1;
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = s_axis_tuser;
if ({s_axis_tdata, s_axis_tdata_d0, s_axis_tdata_d1, s_axis_tdata_d2} != ~crc_next) begin
m_axis_tuser_int = 1'b1;
error_bad_fcs_next = 1'b1;
end
s_axis_tready_next = m_axis_tready_int_early;
state_next = STATE_IDLE;
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
state_next = STATE_PAYLOAD;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_axis_tready_reg <= 1'b0;
busy_reg <= 1'b0;
error_bad_fcs_reg <= 1'b0;
s_axis_tvalid_d0 <= 1'b0;
s_axis_tvalid_d1 <= 1'b0;
s_axis_tvalid_d2 <= 1'b0;
s_axis_tvalid_d3 <= 1'b0;
crc_state <= 32'hFFFFFFFF;
end else begin
state_reg <= state_next;
s_axis_tready_reg <= s_axis_tready_next;
busy_reg <= state_next != STATE_IDLE;
error_bad_fcs_reg <= error_bad_fcs_next;
// datapath
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
end else if (update_crc) begin
crc_state <= crc_next;
end
if (shift_reset) begin
s_axis_tvalid_d0 <= 1'b0;
s_axis_tvalid_d1 <= 1'b0;
s_axis_tvalid_d2 <= 1'b0;
s_axis_tvalid_d3 <= 1'b0;
end else if (shift_in) begin
s_axis_tvalid_d0 <= s_axis_tvalid;
s_axis_tvalid_d1 <= s_axis_tvalid_d0;
s_axis_tvalid_d2 <= s_axis_tvalid_d1;
s_axis_tvalid_d3 <= s_axis_tvalid_d2;
end
end
if (shift_in) begin
s_axis_tdata_d0 <= s_axis_tdata;
s_axis_tdata_d1 <= s_axis_tdata_d0;
s_axis_tdata_d2 <= s_axis_tdata_d1;
s_axis_tdata_d3 <= s_axis_tdata_d2;
end
end
// output datapath logic
reg [7:0] m_axis_tdata_reg = 8'd0;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg m_axis_tuser_reg = 1'b0;
reg [7:0] temp_m_axis_tdata_reg = 8'd0;
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg temp_m_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tuser = m_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule
|
/*
* Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
* Don't remove this header.
* When you use this source, there is a need to inherit this header.
*
* This software is released under the MIT License.
* http://opensource.org/licenses/mit-license.php
*
* For further information please contact.
* URI: http://www.aquaxis.com/
* E-Mail: info(at)aquaxis.com
*/
module aq_axi_memcpy32
(
input ARESETN,
// --------------------------------------------------
// AXI4 Master
// --------------------------------------------------
// Reset, Clock
input M_AXI_ACLK,
// Master Write Address
output [0:0] M_AXI_AWID,
output [31:0] M_AXI_AWADDR,
output [7:0] M_AXI_AWLEN,
output [2:0] M_AXI_AWSIZE,
output [1:0] M_AXI_AWBURST,
output M_AXI_AWLOCK,
output [3:0] M_AXI_AWCACHE,
output [2:0] M_AXI_AWPROT,
output [3:0] M_AXI_AWQOS,
output [0:0] M_AXI_AWUSER,
output M_AXI_AWVALID,
input M_AXI_AWREADY,
// Master Write Data
output [63:0] M_AXI_WDATA,
output [7:0] M_AXI_WSTRB,
output M_AXI_WLAST,
output [0:0] M_AXI_WUSER,
output M_AXI_WVALID,
input M_AXI_WREADY,
// Master Write Response
input [0:0] M_AXI_BID,
input [1:0] M_AXI_BRESP,
input [0:0] M_AXI_BUSER,
input M_AXI_BVALID,
output M_AXI_BREADY,
// Master Read Address
output [0:0] M_AXI_ARID,
output [31:0] M_AXI_ARADDR,
output [7:0] M_AXI_ARLEN,
output [2:0] M_AXI_ARSIZE,
output [1:0] M_AXI_ARBURST,
output [1:0] M_AXI_ARLOCK,
output [3:0] M_AXI_ARCACHE,
output [2:0] M_AXI_ARPROT,
output [3:0] M_AXI_ARQOS,
output [0:0] M_AXI_ARUSER,
output M_AXI_ARVALID,
input M_AXI_ARREADY,
// Master Read Data
input [0:0] M_AXI_RID,
input [63:0] M_AXI_RDATA,
input [1:0] M_AXI_RRESP,
input M_AXI_RLAST,
input [0:0] M_AXI_RUSER,
input M_AXI_RVALID,
output M_AXI_RREADY,
// Command I/F
input CMD_REQ,
output CMD_READY,
output CMD_DONE,
input [31:0] CMD_DST,
input [31:0] CMD_SRC,
input [31:0] CMD_LEN
);
wire local_cs;
wire local_rnw;
wire local_ack;
wire [31:0] local_addr;
wire [3:0] local_be;
wire [31:0] local_wdata;
wire [31:0] local_rdata;
wire wr_start;
wire [31:0] wr_adrs;
wire [31:0] wr_len;
wire wr_ready;
wire wr_fifo_re;
wire wr_fifo_empty;
wire wr_fifo_aempty;
wire [63:0] wr_fifo_data;
wire rd_start;
wire [31:0] rd_adrs;
wire [31:0] rd_len;
wire rd_ready;
wire rd_fifo_we;
wire rd_fifo_full;
wire rd_fifo_afull;
wire [63:0] rd_fifo_data;
wire rd_start_fsync;
wire [31:0] master_status;
reg [31:0] wr_fifo_wrcnt, wr_fifo_rdcnt, rd_fifo_wrcnt, rd_fifo_rdcnt;
wire [31:0] debug_slave, debug_ctl, debug_master;
wire fifo_rst_w;
aq_axi_master32 u_aq_axi_master32
(
.ARESETN(ARESETN),
.ACLK(M_AXI_ACLK),
.M_AXI_AWID(M_AXI_AWID),
.M_AXI_AWADDR(M_AXI_AWADDR),
.M_AXI_AWLEN(M_AXI_AWLEN),
.M_AXI_AWSIZE(M_AXI_AWSIZE),
.M_AXI_AWBURST(M_AXI_AWBURST),
.M_AXI_AWLOCK(M_AXI_AWLOCK),
.M_AXI_AWCACHE(M_AXI_AWCACHE),
.M_AXI_AWPROT(M_AXI_AWPROT),
.M_AXI_AWQOS(M_AXI_AWQOS),
.M_AXI_AWUSER(M_AXI_AWUSER),
.M_AXI_AWVALID(M_AXI_AWVALID),
.M_AXI_AWREADY(M_AXI_AWREADY),
.M_AXI_WDATA(M_AXI_WDATA),
.M_AXI_WSTRB(M_AXI_WSTRB),
.M_AXI_WLAST(M_AXI_WLAST),
.M_AXI_WUSER(M_AXI_WUSER),
.M_AXI_WVALID(M_AXI_WVALID),
.M_AXI_WREADY(M_AXI_WREADY),
.M_AXI_BID(M_AXI_BID),
.M_AXI_BRESP(M_AXI_BRESP),
.M_AXI_BUSER(M_AXI_BUSER),
.M_AXI_BVALID(M_AXI_BVALID),
.M_AXI_BREADY(M_AXI_BREADY),
.M_AXI_ARID(M_AXI_ARID),
.M_AXI_ARADDR(M_AXI_ARADDR),
.M_AXI_ARLEN(M_AXI_ARLEN),
.M_AXI_ARSIZE(M_AXI_ARSIZE),
.M_AXI_ARBURST(M_AXI_ARBURST),
.M_AXI_ARLOCK(M_AXI_ARLOCK),
.M_AXI_ARCACHE(M_AXI_ARCACHE),
.M_AXI_ARPROT(M_AXI_ARPROT),
.M_AXI_ARQOS(M_AXI_ARQOS),
.M_AXI_ARUSER(M_AXI_ARUSER),
.M_AXI_ARVALID(M_AXI_ARVALID),
.M_AXI_ARREADY(M_AXI_ARREADY),
.M_AXI_RID(M_AXI_RID),
.M_AXI_RDATA(M_AXI_RDATA),
.M_AXI_RRESP(M_AXI_RRESP),
.M_AXI_RLAST(M_AXI_RLAST),
.M_AXI_RUSER(M_AXI_RUSER),
.M_AXI_RVALID(M_AXI_RVALID),
.M_AXI_RREADY(M_AXI_RREADY),
.MASTER_RST(FIFO_RST),
.WR_START(wr_start_fsync),
.WR_ADRS(wr_adrs),
.WR_LEN(wr_len),
.WR_READY(wr_ready),
.WR_FIFO_RE(wr_fifo_re),
.WR_FIFO_EMPTY(wr_fifo_empty),
.WR_FIFO_AEMPTY(wr_fifo_aempty),
.WR_FIFO_DATA(wr_fifo_data),
.RD_START(rd_start_fsync),
.RD_ADRS(rd_adrs),
.RD_LEN(rd_len),
.RD_READY(rd_ready),
.RD_FIFO_WE(rd_fifo_we),
.RD_FIFO_FULL(rd_fifo_full),
.RD_FIFO_AFULL(rd_fifo_afull),
.RD_FIFO_DATA(rd_fifo_data)
);
aq_fifo
#(
.FIFO_DEPTH(12),
.FIFO_WIDTH(32)
)
u_aq_fifo(
.RST_N ( ~fifo_rst_w ),
.FIFO_WR_CLK (M_AXI_ACLK),
.FIFO_WR_ENA (rd_fifo_we),
.FIFO_WR_DATA (rd_fifo_data),
.FIFO_WR_LAST (1'b1),
.FIFO_WR_FULL (rd_fifo_full),
.FIFO_WR_ALM_FULL (rd_fifo_afull),
.FIFO_WR_ALM_COUNT (12'h102),
.FIFO_RD_CLK (M_AXI_ACLK),
.FIFO_RD_ENA (wr_fifo_re),
.FIFO_RD_DATA (wr_fifo_data),
.FIFO_RD_EMPTY (wr_fifo_empty),
.FIFO_RD_ALM_EMPTY (wr_fifo_aempty),
.FIFO_RD_ALM_COUNT (12'h102)
);
aq_axi_memcpy32_ctl u_aq_axi_memcpy32_ctl
(
.RST_N(ARESETN),
.CLK(S_AXI_ACLK),
.CMD_REQ(CMD_REQ),
.CMD_READY(CMD_READY),
.CMD_DONE(CMD_DONE),
.CMD_DST(CMD_DST),
.CMD_SRC(CMD_SRC),
.CMD_LEN(CMD_LEN),
.CMD_CLK(M_AXI_ACLK),
.WR_START(wr_start),
.WR_ADRS(wr_adrs),
.WR_COUNT(wr_len),
.WR_READY(wr_ready),
.RD_START(rd_start),
.RD_ADRS(rd_adrs),
.RD_COUNT(rd_len),
.RD_READY(rd_ready),
.FIFO_RST(fifo_rst_w)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXBP_TB_V
`define SKY130_FD_SC_LP__SDFXBP_TB_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfxbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 SCD = 1'b0;
#340 SCE = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SCE = 1'b1;
#540 SCD = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SCE = 1'bx;
#680 SCD = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__sdfxbp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXBP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4_4_V
`define SKY130_FD_SC_LP__AND4_4_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4_4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4_4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4_4_V
|
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 1.3
// \ \ Application : Spartan-6 FPGA GTP Transceiver Wizard
// / / Filename : gtpa1_dual_wrapper.v
// /___/ /\ Timestamp :
// \ \ / \
// \___\/\___\
//
//
// Module GTPA1_DUAL_WRAPPER (a GTP Wrapper)
// Generated by Xilinx Spartan-6 FPGA GTP Transceiver Wizard
//
//
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of,
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`timescale 1ns / 1ps
//***************************** Entity Declaration ****************************
(* CORE_GENERATION_INFO = "GTPA1_DUAL_WRAPPER,s6_gtpwizard_v1_3,{gtp0_protocol_file=pcie,gtp1_protocol_file=Use_GTP0_settings}" *)
module GTPA1_DUAL_WRAPPER #
(
// Simulation attributes
parameter WRAPPER_SIM_GTPRESET_SPEEDUP = 0, // Set to 1 to speed up sim reset
parameter WRAPPER_SIMULATION = 0 // Set to 1 for simulation
)
(
//_________________________________________________________________________
//_________________________________________________________________________
//TILE0 (X0_Y0)
//---------------------- Loopback and Powerdown Ports ----------------------
input [1:0] TILE0_RXPOWERDOWN0_IN,
input [1:0] TILE0_RXPOWERDOWN1_IN,
input [1:0] TILE0_TXPOWERDOWN0_IN,
input [1:0] TILE0_TXPOWERDOWN1_IN,
//------------------------------- PLL Ports --------------------------------
input TILE0_CLK00_IN,
input TILE0_CLK01_IN,
input TILE0_GTPRESET0_IN,
input TILE0_GTPRESET1_IN,
output TILE0_PLLLKDET0_OUT,
output TILE0_PLLLKDET1_OUT,
output TILE0_RESETDONE0_OUT,
output TILE0_RESETDONE1_OUT,
//--------------------- Receive Ports - 8b10b Decoder ----------------------
output [1:0] TILE0_RXCHARISK0_OUT,
output [1:0] TILE0_RXCHARISK1_OUT,
output [1:0] TILE0_RXDISPERR0_OUT,
output [1:0] TILE0_RXDISPERR1_OUT,
output [1:0] TILE0_RXNOTINTABLE0_OUT,
output [1:0] TILE0_RXNOTINTABLE1_OUT,
//-------------------- Receive Ports - Clock Correction --------------------
output [2:0] TILE0_RXCLKCORCNT0_OUT,
output [2:0] TILE0_RXCLKCORCNT1_OUT,
//------------- Receive Ports - Comma Detection and Alignment --------------
input TILE0_RXENMCOMMAALIGN0_IN,
input TILE0_RXENMCOMMAALIGN1_IN,
input TILE0_RXENPCOMMAALIGN0_IN,
input TILE0_RXENPCOMMAALIGN1_IN,
//----------------- Receive Ports - RX Data Path interface -----------------
output [15:0] TILE0_RXDATA0_OUT,
output [15:0] TILE0_RXDATA1_OUT,
input TILE0_RXRESET0_IN,
input TILE0_RXRESET1_IN,
input TILE0_RXUSRCLK0_IN,
input TILE0_RXUSRCLK1_IN,
input TILE0_RXUSRCLK20_IN,
input TILE0_RXUSRCLK21_IN,
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
input TILE0_GATERXELECIDLE0_IN,
input TILE0_GATERXELECIDLE1_IN,
input TILE0_IGNORESIGDET0_IN,
input TILE0_IGNORESIGDET1_IN,
output TILE0_RXELECIDLE0_OUT,
output TILE0_RXELECIDLE1_OUT,
input TILE0_RXN0_IN,
input TILE0_RXN1_IN,
input TILE0_RXP0_IN,
input TILE0_RXP1_IN,
//--------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
output [2:0] TILE0_RXSTATUS0_OUT,
output [2:0] TILE0_RXSTATUS1_OUT,
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
output TILE0_PHYSTATUS0_OUT,
output TILE0_PHYSTATUS1_OUT,
output TILE0_RXVALID0_OUT,
output TILE0_RXVALID1_OUT,
//------------------ Receive Ports - RX Polarity Control -------------------
input TILE0_RXPOLARITY0_IN,
input TILE0_RXPOLARITY1_IN,
//-------------------------- TX/RX Datapath Ports --------------------------
output [1:0] TILE0_GTPCLKOUT0_OUT,
output [1:0] TILE0_GTPCLKOUT1_OUT,
//----------------- Transmit Ports - 8b10b Encoder Control -----------------
input [1:0] TILE0_TXCHARDISPMODE0_IN,
input [1:0] TILE0_TXCHARDISPMODE1_IN,
input [1:0] TILE0_TXCHARISK0_IN,
input [1:0] TILE0_TXCHARISK1_IN,
//---------------- Transmit Ports - TX Data Path interface -----------------
input [15:0] TILE0_TXDATA0_IN,
input [15:0] TILE0_TXDATA1_IN,
input TILE0_TXUSRCLK0_IN,
input TILE0_TXUSRCLK1_IN,
input TILE0_TXUSRCLK20_IN,
input TILE0_TXUSRCLK21_IN,
//------------- Transmit Ports - TX Driver and OOB signalling --------------
output TILE0_TXN0_OUT,
output TILE0_TXN1_OUT,
output TILE0_TXP0_OUT,
output TILE0_TXP1_OUT,
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
input TILE0_TXDETECTRX0_IN,
input TILE0_TXDETECTRX1_IN,
input TILE0_TXELECIDLE0_IN,
input TILE0_TXELECIDLE1_IN
);
//***************************** Wire Declarations *****************************
// ground and vcc signals
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [63:0] tied_to_vcc_vec_i;
wire tile0_plllkdet0_i;
wire tile0_plllkdet1_i;
reg tile0_plllkdet0_i2;
reg tile0_plllkdet1_i2;
//********************************* Main Body of Code**************************
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
generate
if (WRAPPER_SIMULATION==1)
begin : simulation
assign TILE0_PLLLKDET0_OUT = tile0_plllkdet0_i2;
assign TILE0_PLLLKDET1_OUT = tile0_plllkdet1_i2;
always@(tile0_plllkdet0_i)
begin
if (tile0_plllkdet0_i) begin
#100
tile0_plllkdet0_i2 <= tile0_plllkdet0_i;
end
else
begin
tile0_plllkdet0_i2 <= tile0_plllkdet0_i;
end
end
always@(tile0_plllkdet1_i)
begin
if (tile0_plllkdet1_i) begin
#100
tile0_plllkdet1_i2 <= tile0_plllkdet1_i;
end
else
begin
tile0_plllkdet1_i2 <= tile0_plllkdet1_i;
end
end
end //end WRAPPER_SIMULATION =1 generate section
else
begin: implementation
assign TILE0_PLLLKDET0_OUT = tile0_plllkdet0_i;
assign TILE0_PLLLKDET1_OUT = tile0_plllkdet1_i;
end
endgenerate //End generate for WRAPPER_SIMULATION
//------------------------- Tile Instances -------------------------------
//_________________________________________________________________________
//_________________________________________________________________________
//TILE0 (X0_Y0)
GTPA1_DUAL_WRAPPER_TILE #
(
// Simulation attributes
.TILE_SIM_GTPRESET_SPEEDUP (WRAPPER_SIM_GTPRESET_SPEEDUP),
//
.TILE_CLKINDC_B_0 ("TRUE"),
.TILE_CLKINDC_B_1 ("TRUE"),
//
.TILE_PLL_SOURCE_0 ("PLL0"),
.TILE_PLL_SOURCE_1 ("PLL1")
)
tile0_gtpa1_dual_wrapper_i
(
//---------------------- Loopback and Powerdown Ports ----------------------
.RXPOWERDOWN0_IN (TILE0_RXPOWERDOWN0_IN),
.RXPOWERDOWN1_IN (TILE0_RXPOWERDOWN1_IN),
.TXPOWERDOWN0_IN (TILE0_TXPOWERDOWN0_IN),
.TXPOWERDOWN1_IN (TILE0_TXPOWERDOWN1_IN),
//------------------------------- PLL Ports --------------------------------
.CLK00_IN (TILE0_CLK00_IN),
.CLK01_IN (TILE0_CLK01_IN),
.GTPRESET0_IN (TILE0_GTPRESET0_IN),
.GTPRESET1_IN (TILE0_GTPRESET1_IN),
.PLLLKDET0_OUT (tile0_plllkdet0_i),
.PLLLKDET1_OUT (tile0_plllkdet1_i),
.RESETDONE0_OUT (TILE0_RESETDONE0_OUT),
.RESETDONE1_OUT (TILE0_RESETDONE1_OUT),
//--------------------- Receive Ports - 8b10b Decoder ----------------------
.RXCHARISK0_OUT (TILE0_RXCHARISK0_OUT),
.RXCHARISK1_OUT (TILE0_RXCHARISK1_OUT),
.RXDISPERR0_OUT (TILE0_RXDISPERR0_OUT),
.RXDISPERR1_OUT (TILE0_RXDISPERR1_OUT),
.RXNOTINTABLE0_OUT (TILE0_RXNOTINTABLE0_OUT),
.RXNOTINTABLE1_OUT (TILE0_RXNOTINTABLE1_OUT),
//-------------------- Receive Ports - Clock Correction --------------------
.RXCLKCORCNT0_OUT (TILE0_RXCLKCORCNT0_OUT),
.RXCLKCORCNT1_OUT (TILE0_RXCLKCORCNT1_OUT),
//------------- Receive Ports - Comma Detection and Alignment --------------
.RXENMCOMMAALIGN0_IN (TILE0_RXENMCOMMAALIGN0_IN),
.RXENMCOMMAALIGN1_IN (TILE0_RXENMCOMMAALIGN1_IN),
.RXENPCOMMAALIGN0_IN (TILE0_RXENPCOMMAALIGN0_IN),
.RXENPCOMMAALIGN1_IN (TILE0_RXENPCOMMAALIGN1_IN),
//----------------- Receive Ports - RX Data Path interface -----------------
.RXDATA0_OUT (TILE0_RXDATA0_OUT),
.RXDATA1_OUT (TILE0_RXDATA1_OUT),
.RXRESET0_IN (TILE0_RXRESET0_IN),
.RXRESET1_IN (TILE0_RXRESET1_IN),
.RXUSRCLK0_IN (TILE0_RXUSRCLK0_IN),
.RXUSRCLK1_IN (TILE0_RXUSRCLK1_IN),
.RXUSRCLK20_IN (TILE0_RXUSRCLK20_IN),
.RXUSRCLK21_IN (TILE0_RXUSRCLK21_IN),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GATERXELECIDLE0_IN (TILE0_GATERXELECIDLE0_IN),
.GATERXELECIDLE1_IN (TILE0_GATERXELECIDLE1_IN),
.IGNORESIGDET0_IN (TILE0_IGNORESIGDET0_IN),
.IGNORESIGDET1_IN (TILE0_IGNORESIGDET1_IN),
.RXELECIDLE0_OUT (TILE0_RXELECIDLE0_OUT),
.RXELECIDLE1_OUT (TILE0_RXELECIDLE1_OUT),
.RXN0_IN (TILE0_RXN0_IN),
.RXN1_IN (TILE0_RXN1_IN),
.RXP0_IN (TILE0_RXP0_IN),
.RXP1_IN (TILE0_RXP1_IN),
//--------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
.RXSTATUS0_OUT (TILE0_RXSTATUS0_OUT),
.RXSTATUS1_OUT (TILE0_RXSTATUS1_OUT),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.PHYSTATUS0_OUT (TILE0_PHYSTATUS0_OUT),
.PHYSTATUS1_OUT (TILE0_PHYSTATUS1_OUT),
.RXVALID0_OUT (TILE0_RXVALID0_OUT),
.RXVALID1_OUT (TILE0_RXVALID1_OUT),
//------------------ Receive Ports - RX Polarity Control -------------------
.RXPOLARITY0_IN (TILE0_RXPOLARITY0_IN),
.RXPOLARITY1_IN (TILE0_RXPOLARITY1_IN),
//-------------------------- TX/RX Datapath Ports --------------------------
.GTPCLKOUT0_OUT (TILE0_GTPCLKOUT0_OUT),
.GTPCLKOUT1_OUT (TILE0_GTPCLKOUT1_OUT),
//----------------- Transmit Ports - 8b10b Encoder Control -----------------
.TXCHARDISPMODE0_IN (TILE0_TXCHARDISPMODE0_IN),
.TXCHARDISPMODE1_IN (TILE0_TXCHARDISPMODE1_IN),
.TXCHARISK0_IN (TILE0_TXCHARISK0_IN),
.TXCHARISK1_IN (TILE0_TXCHARISK1_IN),
//---------------- Transmit Ports - TX Data Path interface -----------------
.TXDATA0_IN (TILE0_TXDATA0_IN),
.TXDATA1_IN (TILE0_TXDATA1_IN),
.TXUSRCLK0_IN (TILE0_TXUSRCLK0_IN),
.TXUSRCLK1_IN (TILE0_TXUSRCLK1_IN),
.TXUSRCLK20_IN (TILE0_TXUSRCLK20_IN),
.TXUSRCLK21_IN (TILE0_TXUSRCLK21_IN),
//------------- Transmit Ports - TX Driver and OOB signalling --------------
.TXN0_OUT (TILE0_TXN0_OUT),
.TXN1_OUT (TILE0_TXN1_OUT),
.TXP0_OUT (TILE0_TXP0_OUT),
.TXP1_OUT (TILE0_TXP1_OUT),
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
.TXDETECTRX0_IN (TILE0_TXDETECTRX0_IN),
.TXDETECTRX1_IN (TILE0_TXDETECTRX1_IN),
.TXELECIDLE0_IN (TILE0_TXELECIDLE0_IN),
.TXELECIDLE1_IN (TILE0_TXELECIDLE1_IN)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1N_FUNCTIONAL_V
`define SKY130_FD_SC_LP__INPUTISO1N_FUNCTIONAL_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__inputiso1n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Local signals
wire SLEEP;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
or or0 (X , A, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1N_FUNCTIONAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_clsp_synch_cljl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
// Unit Name: ctu_clsp_dramif
//
//-----------------------------------------------------------------------------
`include "sys.h"
module ctu_clsp_synch_cljl(/*AUTOARG*/
// Outputs
jbi_ctu_tr_jl, iob_ctu_tr_jl, iob_ctu_l2_tr_jl, dram13_ctu_tr_jl,
dram02_ctu_tr_jl, ctu_misc_cken_jl, ctu_jbusr_cken_jl,
ctu_jbusl_cken_jl, ctu_jbi_cken_jl, ctu_iob_cken_jl, ctu_efc_cken_jl,
ctu_dram13_cken_jl, ctu_dram02_cken_jl, ctu_dbg_cken_jl,
clsp_ctrl_srarm_jl,
// Inputs
jbus_clk, jbi_ctu_tr, iob_ctu_tr, iob_ctu_l2_tr, io_pwron_rst_l,
dram13_ctu_tr, dram02_ctu_tr, ctu_jbi_cken_pre_jl,
ctu_iob_cken_pre_jl, ctu_efc_cken_pre_jl, ctu_dram13_cken_pre_jl,
ctu_dram02_cken_pre_jl, clsp_ctrl_srarm_pre_jl, start_clk_jl,
ctu_jbusl_cken_pre_jl, ctu_jbusr_cken_pre_jl, ctu_misc_cken_pre_jl,
ctu_dbg_cken_pre_jl
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input clsp_ctrl_srarm_pre_jl; // To u_clsp_ctrl_srarm_jl of dffrl_ns.v
input ctu_dram02_cken_pre_jl; // To u_ctu_dram02_cken_jl of dffrl_ns.v
input ctu_dram13_cken_pre_jl; // To u_ctu_dram13_cken_jl of dffrl_ns.v
input ctu_efc_cken_pre_jl; // To u_ctu_efc_cken_jl of dffrl_ns.v
input ctu_iob_cken_pre_jl; // To u_ctu_iob_cken_jl of dffrl_ns.v
input ctu_jbi_cken_pre_jl; // To u_ctu_jbi_cken_jl of dffrl_ns.v
input dram02_ctu_tr; // To u_dram02_ctu_tr_jl of dff_ns.v
input dram13_ctu_tr; // To u_dram13_ctu_tr_jl of dff_ns.v
input io_pwron_rst_l; // To u_ctu_jbusl_cken_jl of dffsl_async_ns.v, ...
input iob_ctu_l2_tr; // To u_iob_ctu_l2_tr_jl of dff_ns.v
input iob_ctu_tr; // To u_iob_ctu_tr_jl of dff_ns.v
input jbi_ctu_tr; // To u_jbi_ctu_tr_jl of dff_ns.v
input jbus_clk; // To u_clsp_ctrl_srarm_jl of dffrl_ns.v, ...
// End of automatics
input start_clk_jl;
input ctu_jbusl_cken_pre_jl;
input ctu_jbusr_cken_pre_jl;
input ctu_misc_cken_pre_jl;
input ctu_dbg_cken_pre_jl;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output clsp_ctrl_srarm_jl; // From u_clsp_ctrl_srarm_jl of dffrl_ns.v
output ctu_dbg_cken_jl; // From u_ctu_dbg_cken_jl of dffsl_async_ns.v
output ctu_dram02_cken_jl; // From u_ctu_dram02_cken_jl of dffrl_ns.v
output ctu_dram13_cken_jl; // From u_ctu_dram13_cken_jl of dffrl_ns.v
output ctu_efc_cken_jl; // From u_ctu_efc_cken_jl of dffrl_ns.v
output ctu_iob_cken_jl; // From u_ctu_iob_cken_jl of dffrl_ns.v
output ctu_jbi_cken_jl; // From u_ctu_jbi_cken_jl of dffrl_ns.v
output ctu_jbusl_cken_jl; // From u_ctu_jbusl_cken_jl of dffsl_async_ns.v
output ctu_jbusr_cken_jl; // From u_ctu_jbusr_cken_jl of dffsl_async_ns.v
output ctu_misc_cken_jl; // From u_ctu_misc_cken_jl of dffsl_async_ns.v
output dram02_ctu_tr_jl; // From u_dram02_ctu_tr_jl of dff_ns.v
output dram13_ctu_tr_jl; // From u_dram13_ctu_tr_jl of dff_ns.v
output iob_ctu_l2_tr_jl; // From u_iob_ctu_l2_tr_jl of dff_ns.v
output iob_ctu_tr_jl; // From u_iob_ctu_tr_jl of dff_ns.v
output jbi_ctu_tr_jl; // From u_jbi_ctu_tr_jl of dff_ns.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
wire ctu_jbusl_cken_jl_nxt;
wire ctu_jbusr_cken_jl_nxt;
wire ctu_misc_cken_jl_nxt;
wire ctu_dbg_cken_jl_nxt;
/* dffrl_ns AUTO_TEMPLATE (
.din(clsp_ctrl_srarm_pre_jl),
.q (clsp_ctrl_srarm_jl),
.rst_l(start_clk_jl),
.clk (jbus_clk),
);
*/
dffrl_ns u_clsp_ctrl_srarm_jl( .rst_l (start_clk_jl), /*AUTOINST*/
// Outputs
.q (clsp_ctrl_srarm_jl), // Templated
// Inputs
.din (clsp_ctrl_srarm_pre_jl), // Templated
.clk (jbus_clk)); // Templated
/* dffrl_ns AUTO_TEMPLATE (
.din(ctu_dram@_cken_pre_jl),
.q (ctu_dram@_cken_jl),
.rst_l(start_clk_jl),
.clk (jbus_clk),
);
*/
dffrl_ns u_ctu_dram02_cken_jl( .rst_l (start_clk_jl), /*AUTOINST*/
// Outputs
.q (ctu_dram02_cken_jl), // Templated
// Inputs
.din (ctu_dram02_cken_pre_jl), // Templated
.clk (jbus_clk)); // Templated
dffrl_ns u_ctu_dram13_cken_jl( .rst_l (start_clk_jl), /*AUTOINST*/
// Outputs
.q (ctu_dram13_cken_jl), // Templated
// Inputs
.din (ctu_dram13_cken_pre_jl), // Templated
.clk (jbus_clk)); // Templated
/* dffrl_ns AUTO_TEMPLATE (
.din(ctu_iob_cken_pre_jl),
.q (ctu_iob_cken_jl),
.rst_l(start_clk_jl),
.clk (jbus_clk),
);
*/
dffrl_ns u_ctu_iob_cken_jl( .rst_l (start_clk_jl), /*AUTOINST*/
// Outputs
.q (ctu_iob_cken_jl), // Templated
// Inputs
.din (ctu_iob_cken_pre_jl), // Templated
.clk (jbus_clk)); // Templated
/* dffrl_ns AUTO_TEMPLATE (
.din(ctu_efc_cken_pre_jl),
.q (ctu_efc_cken_jl),
.rst_l(start_clk_jl),
.clk (jbus_clk),
);
*/
dffrl_ns u_ctu_efc_cken_jl( .rst_l (start_clk_jl), /*AUTOINST*/
// Outputs
.q (ctu_efc_cken_jl), // Templated
// Inputs
.din (ctu_efc_cken_pre_jl), // Templated
.clk (jbus_clk)); // Templated
/* dffsl_async_ns AUTO_TEMPLATE (
.din(ctu_jbusl_cken_jl_nxt),
.q (ctu_jbusl_cken_jl),
.set_l(io_pwron_rst_l),
.clk (jbus_clk),
);
*/
assign ctu_jbusl_cken_jl_nxt = start_clk_jl ? ctu_jbusl_cken_pre_jl : 1'b1;
dffsl_async_ns u_ctu_jbusl_cken_jl(
.din (ctu_jbusl_cken_jl_nxt),
/*AUTOINST*/
// Outputs
.q(ctu_jbusl_cken_jl), // Templated
// Inputs
.clk(jbus_clk), // Templated
.set_l(io_pwron_rst_l)); // Templated
/* dffsl_async_ns AUTO_TEMPLATE (
.din(ctu_jbusr_cken_jl_nxt),
.q (ctu_jbusr_cken_jl),
.set_l(io_pwron_rst_l),
.clk (jbus_clk),
);
*/
assign ctu_jbusr_cken_jl_nxt = start_clk_jl ? ctu_jbusr_cken_pre_jl: 1'b1;
dffsl_async_ns u_ctu_jbusr_cken_jl(
.din (ctu_jbusr_cken_jl_nxt),
/*AUTOINST*/
// Outputs
.q(ctu_jbusr_cken_jl), // Templated
// Inputs
.clk(jbus_clk), // Templated
.set_l(io_pwron_rst_l)); // Templated
/* dffrl_ns AUTO_TEMPLATE (
.din(ctu_jbi_cken_pre_jl),
.q (ctu_jbi_cken_jl),
.rst_l(start_clk_jl),
.clk (jbus_clk),
);
*/
dffrl_ns u_ctu_jbi_cken_jl( .rst_l (start_clk_jl), /*AUTOINST*/
// Outputs
.q (ctu_jbi_cken_jl), // Templated
// Inputs
.din (ctu_jbi_cken_pre_jl), // Templated
.clk (jbus_clk)); // Templated
/* dffsl_async_ns AUTO_TEMPLATE (
.din(ctu_dbg_cken_jl_nxt),
.q (ctu_dbg_cken_jl),
.set_l(io_pwron_rst_l),
.clk (jbus_clk),
);
*/
assign ctu_dbg_cken_jl_nxt = start_clk_jl ? ctu_dbg_cken_pre_jl: 1'b1;
dffsl_async_ns u_ctu_dbg_cken_jl( .set_l (io_pwron_rst_l), /*AUTOINST*/
// Outputs
.q(ctu_dbg_cken_jl), // Templated
// Inputs
.din(ctu_dbg_cken_jl_nxt), // Templated
.clk(jbus_clk)); // Templated
/* dffsl_async_ns AUTO_TEMPLATE (
.din(ctu_misc_cken_jl_nxt),
.q (ctu_misc_cken_jl),
.set_l(io_pwron_rst_l),
.clk (jbus_clk),
);
*/
assign ctu_misc_cken_jl_nxt = start_clk_jl ? ctu_misc_cken_pre_jl: 1'b1;
dffsl_async_ns u_ctu_misc_cken_jl( .set_l (io_pwron_rst_l), /*AUTOINST*/
// Outputs
.q(ctu_misc_cken_jl), // Templated
// Inputs
.din(ctu_misc_cken_jl_nxt), // Templated
.clk(jbus_clk)); // Templated
/* dff_ns AUTO_TEMPLATE (
.din(iob_ctu_l2_tr),
.q (iob_ctu_l2_tr_jl),
.clk (jbus_clk),
);
*/
dff_ns u_iob_ctu_l2_tr_jl(/*AUTOINST*/
// Outputs
.q (iob_ctu_l2_tr_jl), // Templated
// Inputs
.din (iob_ctu_l2_tr), // Templated
.clk (jbus_clk)); // Templated
/* dff_ns AUTO_TEMPLATE (
.din(iob_ctu_tr),
.q (iob_ctu_tr_jl),
.clk (jbus_clk),
);
*/
dff_ns u_iob_ctu_tr_jl(/*AUTOINST*/
// Outputs
.q (iob_ctu_tr_jl), // Templated
// Inputs
.din (iob_ctu_tr), // Templated
.clk (jbus_clk)); // Templated
/* dff_ns AUTO_TEMPLATE (
.din(jbi_ctu_tr),
.q (jbi_ctu_tr_jl),
.clk (jbus_clk),
);
*/
dff_ns u_jbi_ctu_tr_jl(/*AUTOINST*/
// Outputs
.q (jbi_ctu_tr_jl), // Templated
// Inputs
.din (jbi_ctu_tr), // Templated
.clk (jbus_clk)); // Templated
/* dff_ns AUTO_TEMPLATE (
.din(dram@_ctu_tr),
.q (dram@_ctu_tr_jl),
.clk (jbus_clk),
);
*/
dff_ns u_dram02_ctu_tr_jl (/*AUTOINST*/
// Outputs
.q (dram02_ctu_tr_jl), // Templated
// Inputs
.din (dram02_ctu_tr), // Templated
.clk (jbus_clk)); // Templated
dff_ns u_dram13_ctu_tr_jl (/*AUTOINST*/
// Outputs
.q (dram13_ctu_tr_jl), // Templated
// Inputs
.din (dram13_ctu_tr), // Templated
.clk (jbus_clk)); // Templated
endmodule // ctu_clsp_cl_jg
// Local Variables:
// verilog-library-directories:("." "../common/rtl")
// verilog-library-files:("../common/rtl/ctu_lib.v" "../../common/rtl/swrvr_clib.v")
// verilog-auto-sense-defines-constant:t
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFBUF_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__BUFBUF_PP_BLACKBOX_V
/**
* bufbuf: Double buffer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__bufbuf (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFBUF_PP_BLACKBOX_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ebc_e
//
// Generated
// by: wig
// on: Mon Apr 10 13:27:22 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ebc_e.v,v 1.1 2006/04/10 15:42:07 wig Exp $
// $Date: 2006/04/10 15:42:07 $
// $Log: inst_ebc_e.v,v $
// Revision 1.1 2006/04/10 15:42:07 wig
// Updated testcase (__TOP__)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_ebc_e
//
// No user `defines in this module
module inst_ebc_e
//
// Generated module inst_ebc
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ebc_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* @Author: tmh
* @Date: 2017-07-25 20:47:53
* @File Name: PIC16C55.v
*/
`include "define.v"
module PIC16C55 (
input clk , // Clock
input rst_n, // Asynchronous reset active low
inout [`IO_A_WIDTH - 1:0] portAIO,
inout [`IO_B_WIDTH - 1:0] portBIO,
inout [`IO_C_WIDTH - 1:0] portCIO
);
// wire clk;
// wire rst_n;
wire [`INST_WIDTH-1:0] IR;
wire [`EX_STATE_BITS-1:0] executeState;
wire [`FE_STATE_BITS-1:0] fetchState;
wire [`DATA_WIDTH-1:0] aluResult;
wire [`ALU_STATUS_WIDTH-1:0] aluStatus;
wire [`DATA_WIDTH-1:0] gprStatus;
wire [`DATA_WIDTH-1:0] gpr;
wire [`PC_WIDTH-1:0] stack;
wire [2:0] writeCommand;
wire [`DATA_WIDTH-1:0] gprFSR;
wire [`PC_WIDTH-1:0] PC;
wire [`DATA_WIDTH-1:0] W;
wire [`INST_WIDTH - 1:0] programMem;
wire [`ALU_FUNC_WIDTH-1:0] aluFunc;
wire [`DATA_WIDTH-1:0] gprWriteData;
wire [`DATA_WIDTH-1:0] statusWriteData;
wire [`IO_A_WIDTH - 1:0] portA;
wire [`IO_B_WIDTH - 1:0] portB;
wire [`IO_C_WIDTH - 1:0] portC;
wire [`IO_A_WIDTH-1:0] trisAReg;
wire [`IO_B_WIDTH-1:0] trisBReg;
wire [`IO_C_WIDTH-1:0] trisCReg;
wire [1:0] stackCommand;
wire goto;
wire skip;
assign portAIO = {
trisAReg[3] ? 1'bz : portA[3],
trisAReg[2] ? 1'bz : portA[2],
trisAReg[1] ? 1'bz : portA[1],
trisAReg[0] ? 1'bz : portA[0]
};
assign portBIO = {
trisBReg[7] ? 1'bz : portB[7],
trisBReg[6] ? 1'bz : portB[6],
trisBReg[5] ? 1'bz : portB[5],
trisBReg[4] ? 1'bz : portB[4],
trisBReg[3] ? 1'bz : portB[3],
trisBReg[2] ? 1'bz : portB[2],
trisBReg[1] ? 1'bz : portB[1],
trisBReg[0] ? 1'bz : portB[0]
};
assign portCIO = {
trisCReg[7] ? 1'bz : portC[7],
trisCReg[6] ? 1'bz : portC[6],
trisCReg[5] ? 1'bz : portC[5],
trisCReg[4] ? 1'bz : portC[4],
trisCReg[3] ? 1'bz : portC[3],
trisCReg[2] ? 1'bz : portC[2],
trisCReg[1] ? 1'bz : portC[1],
trisCReg[0] ? 1'bz : portC[0]
};
port port_I(
// IN
.clk (clk),
.rst_n (rst_n),
.executeState(executeState),
.IR (IR[2:0]),
.WRIn (W),
// OUT
.trisAReg (trisAReg),
.trisBReg (trisBReg),
.trisCReg (trisCReg)
);
PC PC_I(
// IN
.clk (clk),
.rst_n (rst_n),
.IR (IR[8:0]),
.executeState(executeState),
.fetchState (fetchState),
.aluStatusIn (aluStatus),
.gprIn (gpr),
.stackIn (stack),
.writeCommand(writeCommand),
.gprFSRIn (gprFSR[4:0]),
// OUT
.PC (PC),
.goto (goto),
.skip (skip)
);
programMem Mem_I(
// IN
.PCIn(PC),
// OUT
.programMemOut(programMem)
);
IR IR_I(
// IN
.clk (clk),
.rst_n (rst_n),
.fetchState (fetchState),
.executeState(executeState),
.programMemIn(programMem),
.goto (goto),
.skip (skip),
// OUT
.IR (IR)
);
ControlUnit CU_I(
// IN
.clk (clk),
.rst_n (rst_n),
.instIn (IR),
// OUR
.fetchState (fetchState),
.executeState(executeState),
.aluFuncOut (aluFunc),
.stackCommand(stackCommand)
);
ALU ALU_I (
// IN
.wIn (W),
.fIn (gpr),
.lIn (IR[7:0]),
.funcIn (aluFunc),
.bitSel (IR[7:5]),
.cFlag (gprStatus[0]),
.statusIn (gprStatus[2:0]),
// OUT
.aluStatusOut(aluStatus),
.aluResultOut(aluResult)
);
RegFileWriteControl RegFileWC_I(
// IN
.executeState (executeState),
.aluResultIn (aluResult),
.wRIn (W),
.IR (IR[5:0]),
.gprStatusIn (gprStatus),
.aluStatusIn (aluStatus),
// OUT
.writeCommand (writeCommand),
.gprWriteDataOut (gprWriteData),
.statusWriteDataOut(statusWriteData)
);
RegisterFile RegFile_I(
// IN
.clk (clk),
.rst (rst_n),
.writeCommand(writeCommand),
.fileAddr (IR[4:0]),
.writeDataIn (gprWriteData),
.statusIn (statusWriteData),
.portAIn (portAIO),
.portBIn (portBIO),
.portCIn (portCIO),
.pcIn (PC),
// OUT
.fsrOut (gprFSR),
.regfileOut (gpr),
.statusOut (gprStatus),
.portAOut (portA),
.portBOut (portB),
.portCOut (portC)
);
wRegWriteControl wRegWC_I(
// IN
.clk (clk),
.rst_n (rst_n),
.IR (IR[7:0]),
.executeState(executeState),
.aluResultIn (aluResult),
.gprIn (gpr),
// OUT
.wROut (W)
);
stack stack_I(
// IN
.clk (clk),
.rst_n (rst_n),
.commandIn(stackCommand),
.in (PC),
// OUT
.topOut (stack)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUF_PP_SYMBOL_V
`define SKY130_FD_SC_MS__BUF_PP_SYMBOL_V
/**
* buf: Buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__buf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUF_PP_SYMBOL_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file txreg.v when simulating
// the core, txreg. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module txreg(
clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input clk;
input rst;
input [7 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output empty;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(5),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(8),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(8),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("spartan3"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(14),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(5),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(16),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.RST(rst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.BACKUP(),
.BACKUP_MARKER(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221O_1_V
`define SKY130_FD_SC_LS__A221O_1_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a221o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a221o_1 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221O_1_V
|
`timescale 1ns / 1ps
`define FLASH 2'b00
`define READ 2'b01
`define WRITE 2'b10
`define INVALID 2'b11
`define MISS 1'b0
`define HIT 1'b1
`define CACHE_ENABLE 1'b0
`define CACHE_DISABLE 1'b1
`define TAG_ENTRY_INVALID 1'b0
`define TAG_ENTRY_VALID 1'b1
`define LINE_DATA_CLEAN 1'b0
`define LINE_DATA_DIRTY 1'b1
`define LINE_RW_NOT_ALLOWED 1'b0
`define LINE_RW_ALLOWED 1'b1
`define L1_CACHE_ACCESS 0
`define L2_CACHE_ACCESS 1
`define CACHE_SWAP 3
`define CACHE_SWAP_WAIT 4
`define NON_CACHED_DATA 5
`define LOG2(width) (width<=2)?1:\
(width<=4)?2:\
(width<=8)?3:\
(width<=16)?4:\
(width<=32)?5:\
(width<=64)?6:\
(width<=128)?7:\
(width<=256)?8:\
-1
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:39:36 03/01/2015
// Design Name: cache
// Module Name: D:/Modelsim Projects/Xilinx/cache_implementation/top_tb.v
// Project Name: cache_implementation
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: cache
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cacheblock_tb;
parameter TAG_WIDTH = 8; // width of the tag
parameter DATA_WIDTH = 16; // width of the data
parameter ENTRIES_WIDTH = 64; // # of entries
parameter OPCODE_WIDTH = 2; // width of opcode
parameter LINE_WIDTH = TAG_WIDTH+DATA_WIDTH+OPCODE_WIDTH; // length of the input vector
// Inputs
reg [LINE_WIDTH-1:0]vector_in;
reg clk;
reg enable;
reg reset;
reg [TAG_WIDTH-1:0]tag_count;
reg [DATA_WIDTH-1:0]data_test;
// Outputs
wire [DATA_WIDTH-1:0]data_out;
wire hit_miss_out;
// Instantiate the Unit Under Test (UUT)
cache #(TAG_WIDTH,DATA_WIDTH,ENTRIES_WIDTH) cacheblock (
.data_out(data_out),
.hit_miss_out(hit_miss_out),
.vector_in(vector_in),
.enable(enable),
.reset(reset),
.clk(clk)
);
initial begin
// Initialize Inputs
// data_in = 0;
clk = 0;
enable = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#2 reset = 0;
// Fill up cache
tag_count = {TAG_WIDTH{1'b0}};
data_test = {DATA_WIDTH{1'b1}};
// This loop fills up the cache
repeat(ENTRIES_WIDTH)begin: bench1
#2 vector_in = {`WRITE,tag_count,data_test}; // write to a new tag entry every time
// #2 vector_in = {2'b01,tag_count,data_test}; // read such tag entry
tag_count = tag_count + 8'b1;
data_test = data_test + 16'b1;
end // end repeat loop
// This loop reads all the data that has been written in the cache previously
#2 tag_count = {TAG_WIDTH{1'b0}};
#2 data_test = {DATA_WIDTH{1'b1}};
repeat(ENTRIES_WIDTH)begin: bench2
#2 vector_in = {`READ,tag_count,data_test}; // write to a new tag entry every time
// #2 vector_in = {`READ,8'b111,data_test}; // read a new tag entry every time
// #2 vector_in = {`READ,8'b1010,data_test}; // read a new tag entry every time
// #2 vector_in = {`READ,8'b1111,data_test}; // read a new tag entry every time
// #2 vector_in = {2'b01,tag_count,data_test}; // read such tag entry
tag_count = tag_count + 1'b1;
data_test = data_test + 1'b1;
end // end repeat loop
#2 vector_in = 26'b10_11111111_0001000100010001; // write to a different tag entry
#2 vector_in = 26'b01_11111111_0001000100010001; // read the above tag entry
#2 vector_in = 26'b01_00001111_0001000100010001; // read the above tag entry
repeat(4)begin: bench3
#2 vector_in = {`READ,8'b00001010,data_test}; // read same tag entry every time
// #2 vector_in = {2'b01,tag_count,data_test}; // read such tag entry
end // end repeat loop
#2 vector_in = 26'b00_00110001_0000000000000001; // flashes entire cache
// reads entire cache to confirm that has been flashed
tag_count = {TAG_WIDTH{1'b0}};
data_test = {DATA_WIDTH{1'b1}};
repeat(8)begin: bench4
#2 vector_in = {`READ,tag_count,data_test}; // read a new tag entry every time
// #2 vector_in = {2'b01,tag_count,data_test}; // read such tag entry
tag_count = tag_count + 1'b1;
data_test = data_test + 1'b1;
end // end repeat loop
end
always begin
#1 clk = ~clk; // Toggle clock every 1 ticks
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BO_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A21BO_FUNCTIONAL_PP_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X , B1_N, nand0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BO_FUNCTIONAL_PP_V |
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.0
// \ \ Application : MIG
// / / Filename : sim_tb_top.v
// /___/ /\ Date Last Modified : $Date: 2011/06/07 13:45:16 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM
// Purpose :
// Top-level testbench for testing DDR3.
// Instantiates:
// 1. IP_TOP (top-level representing FPGA, contains core,
// clocking, built-in testbench/memory checker and other
// support structures)
// 2. DDR3 Memory
// 3. Miscellaneous clock generation and reset logic
// 4. For ECC ON case inserts error on LSB bit
// of data from DRAM to FPGA.
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/100fs
module sim_tb_top;
//***************************************************************************
// Traffic Gen related parameters
//***************************************************************************
parameter SIMULATION = "TRUE";
// parameter BL_WIDTH = 10;
parameter PORT_MODE = "BI_MODE";
parameter DATA_MODE = 4'b0010;
parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE";
parameter EYE_TEST = "FALSE";
// set EYE_TEST = "TRUE" to probe memory
// signals. Traffic Generator will only
// write to one single location and no
// read transactions will be generated.
parameter DATA_PATTERN = "DGEN_ALL";
// For small devices, choose one only.
// For large device, choose "DGEN_ALL"
// "DGEN_HAMMER", "DGEN_WALKING1",
// "DGEN_WALKING0","DGEN_ADDR","
// "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter CMD_PATTERN = "CGEN_ALL";
// "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
// "CGEN_SEQUENTIAL", "CGEN_ALL"
// parameter SEL_VICTIM_LINE = 11;
// parameter ADDR_MODE = 4'b0011;
parameter BEGIN_ADDRESS = 32'h00000000;
parameter END_ADDRESS = 32'h00000fff;
parameter PRBS_EADDR_MASK_POS = 32'hff000000;
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter BANK_WIDTH = 3;
// # of memory Bank Address bits.
parameter CK_WIDTH = 1;
// # of CK/CK# outputs to memory.
parameter COL_WIDTH = 10;
// # of memory Column Address bits.
parameter CS_WIDTH = 1;
// # of unique CS outputs to memory.
parameter nCS_PER_RANK = 1;
// # of unique CS outputs per rank for phy
parameter CKE_WIDTH = 1;
// # of CKE outputs to memory.
// parameter DATA_BUF_ADDR_WIDTH = 5;
// parameter DQ_CNT_WIDTH = 4;
// = ceil(log2(DQ_WIDTH))
// parameter DQ_PER_DM = 8;
parameter DM_WIDTH = 2;
// # of DM (data mask)
parameter DQ_WIDTH = 16;
// # of DQ (data)
parameter DQS_WIDTH = 2;
parameter DQS_CNT_WIDTH = 1;
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8;
// # of DQ per DQS
parameter ECC = "OFF";
// parameter nBANK_MACHS = 4;
parameter RANKS = 1;
// # of Ranks.
parameter ODT_WIDTH = 1;
// # of ODT outputs to memory.
parameter ROW_WIDTH = 13;
// # of memory Row Address bits.
parameter ADDR_WIDTH = 27;
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices
// parameter USE_CS_PORT = 1;
// # = 1, When CS output is enabled
// = 0, When CS output is disabled
// If CS_N disabled, user must connect
// DRAM CS_N input(s) to ground
// parameter USE_DM_PORT = 1;
// # = 1, When Data Mask option is enabled
// = 0, When Data Mask option is disbaled
// When Data Mask option is disabled in
// MIG Controller Options page, the logic
// related to Data Mask should not get
// synthesized
// parameter USE_ODT_PORT = 1;
// # = 1, When ODT output is enabled
// = 0, When ODT output is disabled
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
// parameter AL = "0";
// DDR3 SDRAM:
// Additive Latency (Mode Register 1).
// # = "0", "CL-1", "CL-2".
// DDR2 SDRAM:
// Additive Latency (Extended Mode Register).
// parameter nAL = 0;
// # Additive Latency in number of clock
// cycles.
parameter BURST_MODE = "8";
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
// parameter BURST_TYPE = "SEQ";
// DDR3 SDRAM: Burst Type (Mode Register 0).
// DDR2 SDRAM: Burst Type (Mode Register).
// # = "SEQ" - (Sequential),
// = "INT" - (Interleaved).
// parameter CL = 3;
// in number of clock cycles
// DDR3 SDRAM: CAS Latency (Mode Register 0).
// DDR2 SDRAM: CAS Latency (Mode Register).
// parameter OUTPUT_DRV = "HIGH";
// Output Drive Strength (Extended Mode Register).
// # = "HIGH" - FULL,
// = "LOW" - REDUCED.
// parameter RTT_NOM = "50";
// RTT (Nominal) (Extended Mode Register).
// = "150" - 150 Ohms,
// = "75" - 75 Ohms,
// = "50" - 50 Ohms.
// parameter ADDR_CMD_MODE = "1T" ;
// # = "1T", "2T".
// parameter REG_CTRL = "OFF";
// # = "ON" - RDIMMs,
// = "OFF" - Components, SODIMMs, UDIMMs.
//***************************************************************************
// The following parameters are multiplier and divisor factors for PLLE2.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 5000;
// Input Clock Period
// parameter CLKFBOUT_MULT = 4;
// write PLL VCO multiplier
// parameter DIVCLK_DIVIDE = 1;
// write PLL VCO divisor
// parameter CLKOUT0_DIVIDE = 2;
// VCO output divisor for PLL output clock (CLKOUT0)
// parameter CLKOUT1_DIVIDE = 4;
// VCO output divisor for PLL output clock (CLKOUT1)
// parameter CLKOUT2_DIVIDE = 64;
// VCO output divisor for PLL output clock (CLKOUT2)
// parameter CLKOUT3_DIVIDE = 16;
// VCO output divisor for PLL output clock (CLKOUT3)
//***************************************************************************
// Memory Timing Parameters. These parameters varies based on the selected
// memory part.
//***************************************************************************
// parameter tCKE = 7500;
// memory tCKE paramter in pS
// parameter tFAW = 45000;
// memory tRAW paramter in pS.
// parameter tRAS = 40000;
// memory tRAS paramter in pS.
// parameter tRCD = 15000;
// memory tRCD paramter in pS.
// parameter tREFI = 7800000;
// memory tREFI paramter in pS.
// parameter tRFC = 127500;
// memory tRFC paramter in pS.
// parameter tRP = 12500;
// memory tRP paramter in pS.
// parameter tRRD = 10000;
// memory tRRD paramter in pS.
// parameter tRTP = 7500;
// memory tRTP paramter in pS.
// parameter tWTR = 7500;
// memory tWTR paramter in pS.
// parameter tZQI = 128_000_000;
// memory tZQI paramter in nS.
// parameter tZQCS = 64;
// memory tZQCS paramter in clock cycles.
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "FAST";
// # = "SIM_INIT_CAL_FULL" - Complete
// memory init &
// calibration sequence
// # = "SKIP" - Not supported
// # = "FAST" - Complete memory init & use
// abbreviated calib sequence
//***************************************************************************
// The following parameters varies based on the pin out entered in MIG GUI.
// Do not change any of these parameters directly by editing the RTL.
// Any changes required should be done through GUI and the design regenerated.
//***************************************************************************
// parameter BYTE_LANES_B0 = 4'b1111;
// // Byte lanes used in an IO column.
// parameter BYTE_LANES_B1 = 4'b0000;
// // Byte lanes used in an IO column.
// parameter BYTE_LANES_B2 = 4'b0000;
// // Byte lanes used in an IO column.
// parameter BYTE_LANES_B3 = 4'b0000;
// // Byte lanes used in an IO column.
// parameter BYTE_LANES_B4 = 4'b0000;
// // Byte lanes used in an IO column.
// parameter DATA_CTL_B0 = 4'b0101;
// // Indicates Byte lane is data byte lane
// // or control Byte lane. '1' in a bit
// // position indicates a data byte lane and
// // a '0' indicates a control byte lane
// parameter DATA_CTL_B1 = 4'b0000;
// // Indicates Byte lane is data byte lane
// // or control Byte lane. '1' in a bit
// // position indicates a data byte lane and
// // a '0' indicates a control byte lane
// parameter DATA_CTL_B2 = 4'b0000;
// // Indicates Byte lane is data byte lane
// // or control Byte lane. '1' in a bit
// // position indicates a data byte lane and
// // a '0' indicates a control byte lane
// parameter DATA_CTL_B3 = 4'b0000;
// // Indicates Byte lane is data byte lane
// // or control Byte lane. '1' in a bit
// // position indicates a data byte lane and
// // a '0' indicates a control byte lane
// parameter DATA_CTL_B4 = 4'b0000;
// // Indicates Byte lane is data byte lane
// // or control Byte lane. '1' in a bit
// // position indicates a data byte lane and
// // a '0' indicates a control byte lane
// parameter PHY_0_BITLANES = 48'hFFC_3F7_FFF_3FE;
// parameter PHY_1_BITLANES = 48'h000_000_000_000;
// parameter PHY_2_BITLANES = 48'h000_000_000_000;
//
// // control/address/data pin mapping parameters
// parameter CK_BYTE_MAP
// = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_03;
// parameter ADDR_MAP
// = 192'h000_000_000_010_033_01A_019_032_03A_034_018_036_012_011_017_015;
// parameter BANK_MAP = 36'h013_016_01B;
// parameter CAS_MAP = 12'h039;
// parameter CKE_ODT_BYTE_MAP = 8'h00;
// parameter CKE_MAP = 96'h000_000_000_000_000_000_000_038;
// parameter ODT_MAP = 96'h000_000_000_000_000_000_000_035;
// parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_037;
// parameter PARITY_MAP = 12'h000;
// parameter RAS_MAP = 12'h014;
// parameter WE_MAP = 12'h03B;
// parameter DQS_BYTE_MAP
// = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02_00;
// parameter DATA0_MAP = 96'h008_004_009_007_005_001_006_003;
// parameter DATA1_MAP = 96'h022_028_020_024_027_025_026_021;
// parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000;
// parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000;
// parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000;
// parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000;
// parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000;
// parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000;
// parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000;
// parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000;
// parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000;
// parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000;
// parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000;
// parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000;
// parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000;
// parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000;
// parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000;
// parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000;
// parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_029_002;
// parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000;
//
// parameter SLOT_0_CONFIG = 8'b0000_0001;
// // Mapping of Ranks.
// parameter SLOT_1_CONFIG = 8'b0000_0000;
// // Mapping of Ranks.
// parameter MEM_ADDR_ORDER = "ROW_BANK_COLUMN";
// //Possible Parameters
// //1.BANK_ROW_COLUMN : Address mapping is
// // in form of Bank Row Column.
// //2.ROW_BANK_COLUMN : Address mapping is
// // in the form of Row Bank Column.
// //3.TG_TEST : Scrambles Address bits
// // for distributed Addressing.
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
// parameter IBUF_LPWR_MODE = "OFF";
// // to phy_top
// parameter DATA_IO_IDLE_PWRDWN = "ON";
// // # = "ON", "OFF"
// parameter DATA_IO_PRIM_TYPE = "HR_LP";
// // # = "HP_LP", "HR_LP", "DEFAULT"
// parameter USER_REFRESH = "OFF";
// parameter WRLVL = "OFF";
// // # = "ON" - DDR3 SDRAM
// // = "OFF" - DDR2 SDRAM.
// parameter ORDERING = "STRICT";
// // # = "NORM", "STRICT", "RELAXED".
// parameter CALIB_ROW_ADD = 16'h0000;
// // Calibration row address will be used for
// // calibration read and write operations
// parameter CALIB_COL_ADD = 12'h000;
// // Calibration column address will be used for
// // calibration read and write operations
// parameter CALIB_BA_ADD = 3'h0;
// // Calibration bank address will be used for
// // calibration read and write operations
parameter TCQ = 100;
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
// parameter IODELAY_GRP = "MIG_IODELAY_MIG";
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency.
// parameter SYSCLK_TYPE = "NO_BUFFER";
// System clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
// parameter REFCLK_TYPE = "USE_SYSTEM_CLOCK";
// Reference clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER, USE_SYSTEM_CLOCK
parameter RST_ACT_LOW = 0;
// =1 for active low reset,
// =0 for active high.
// parameter CAL_WIDTH = "HALF";
// parameter STARVE_LIMIT = 2;
// # = 2,3,4.
//***************************************************************************
// Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0;
// IODELAYCTRL reference clock frequency
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter tCK = 5000;
// memory tCK paramter.
// # = Clock Period in pS.
// parameter nCK_PER_CLK = 4;
// # of memory CKs per fabric CLK
//***************************************************************************
// Debug and Internal parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF";
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
//***************************************************************************
// Debug and Internal parameters
//***************************************************************************
parameter DRAM_TYPE = "DDR2";
//**************************************************************************//
// Local parameters Declarations
//**************************************************************************//
localparam real TPROP_DQS = 0.00;
// Delay for DQS signal during Write Operation
localparam real TPROP_DQS_RD = 0.00;
// Delay for DQS signal during Read Operation
localparam real TPROP_PCB_CTRL = 0.00;
// Delay for Address and Ctrl signals
localparam real TPROP_PCB_DATA = 0.00;
// Delay for data signal during Write operation
localparam real TPROP_PCB_DATA_RD = 0.00;
// Delay for data signal during Read operation
localparam MEMORY_WIDTH = 16;
localparam NUM_COMP = DQ_WIDTH/MEMORY_WIDTH;
localparam ECC_TEST = "OFF" ;
localparam ERR_INSERT = (ECC_TEST == "ON") ? "OFF" : ECC ;
localparam real REFCLK_PERIOD = (1000000.0/(2*REFCLK_FREQ));
localparam RESET_PERIOD = 200000; //in pSec
localparam real SYSCLK_PERIOD = tCK;
//**************************************************************************//
// Wire Declarations
//**************************************************************************//
reg sys_rst_n;
wire sys_rst;
reg sys_clk_i;
reg clk_ref_i;
wire ddr2_reset_n;
wire [DQ_WIDTH-1:0] ddr2_dq_fpga;
wire [DQS_WIDTH-1:0] ddr2_dqs_p_fpga;
wire [DQS_WIDTH-1:0] ddr2_dqs_n_fpga;
wire [ROW_WIDTH-1:0] ddr2_addr_fpga;
wire [BANK_WIDTH-1:0] ddr2_ba_fpga;
wire ddr2_ras_n_fpga;
wire ddr2_cas_n_fpga;
wire ddr2_we_n_fpga;
wire [CKE_WIDTH-1:0] ddr2_cke_fpga;
wire [CK_WIDTH-1:0] ddr2_ck_p_fpga;
wire [CK_WIDTH-1:0] ddr2_ck_n_fpga;
wire init_calib_complete;
wire tg_compare_error;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr2_cs_n_fpga;
wire [DM_WIDTH-1:0] ddr2_dm_fpga;
wire [ODT_WIDTH-1:0] ddr2_odt_fpga;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr2_cs_n_sdram_tmp;
reg [DM_WIDTH-1:0] ddr2_dm_sdram_tmp;
reg [ODT_WIDTH-1:0] ddr2_odt_sdram_tmp;
wire [DQ_WIDTH-1:0] ddr2_dq_sdram;
reg [ROW_WIDTH-1:0] ddr2_addr_sdram;
reg [BANK_WIDTH-1:0] ddr2_ba_sdram;
reg ddr2_ras_n_sdram;
reg ddr2_cas_n_sdram;
reg ddr2_we_n_sdram;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr2_cs_n_sdram;
wire [ODT_WIDTH-1:0] ddr2_odt_sdram;
reg [CKE_WIDTH-1:0] ddr2_cke_sdram;
wire [DM_WIDTH-1:0] ddr2_dm_sdram;
wire [DQS_WIDTH-1:0] ddr2_dqs_p_sdram;
wire [DQS_WIDTH-1:0] ddr2_dqs_n_sdram;
reg [CK_WIDTH-1:0] ddr2_ck_p_sdram;
reg [CK_WIDTH-1:0] ddr2_ck_n_sdram;
//**************************************************************************//
//**************************************************************************//
// Reset Generation
//**************************************************************************//
initial begin
sys_rst_n = 1'b0;
#RESET_PERIOD
sys_rst_n = 1'b1;
end
assign sys_rst = RST_ACT_LOW ? sys_rst_n : ~sys_rst_n;
//**************************************************************************//
// Clock Generation
//**************************************************************************//
initial
sys_clk_i = 1'b0;
always
sys_clk_i = #(CLKIN_PERIOD/2.0) ~sys_clk_i;
initial
clk_ref_i = 1'b0;
always
clk_ref_i = #REFCLK_PERIOD ~clk_ref_i;
always @( * ) begin
ddr2_ck_p_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_p_fpga;
ddr2_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_n_fpga;
ddr2_addr_sdram <= #(TPROP_PCB_CTRL) ddr2_addr_fpga;
ddr2_ba_sdram <= #(TPROP_PCB_CTRL) ddr2_ba_fpga;
ddr2_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ras_n_fpga;
ddr2_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cas_n_fpga;
ddr2_we_n_sdram <= #(TPROP_PCB_CTRL) ddr2_we_n_fpga;
ddr2_cke_sdram <= #(TPROP_PCB_CTRL) ddr2_cke_fpga;
end
always @( * )
ddr2_cs_n_sdram_tmp <= #(TPROP_PCB_CTRL) ddr2_cs_n_fpga;
assign ddr2_cs_n_sdram = ddr2_cs_n_sdram_tmp;
always @( * )
ddr2_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr2_dm_fpga;//DM signal generation
assign ddr2_dm_sdram = ddr2_dm_sdram_tmp;
always @( * )
ddr2_odt_sdram_tmp <= #(TPROP_PCB_CTRL) ddr2_odt_fpga;
assign ddr2_odt_sdram = ddr2_odt_sdram_tmp;
// Controlling the bi-directional BUS
genvar dqwd;
generate
for (dqwd = 1;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD),
.ERR_INSERT ("OFF")
)
u_delay_dq
(
.A (ddr2_dq_fpga[dqwd]),
.B (ddr2_dq_sdram[dqwd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
end
// For ECC ON case error is inserted on LSB bit from DRAM to FPGA
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD),
.ERR_INSERT (ERR_INSERT)
)
u_delay_dq_0
(
.A (ddr2_dq_fpga[0]),
.B (ddr2_dq_sdram[0]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
endgenerate
genvar dqswd;
generate
for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD),
.ERR_INSERT ("OFF")
)
u_delay_dqs_p
(
.A (ddr2_dqs_p_fpga[dqswd]),
.B (ddr2_dqs_p_sdram[dqswd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD),
.ERR_INSERT ("OFF")
)
u_delay_dqs_n
(
.A (ddr2_dqs_n_fpga[dqswd]),
.B (ddr2_dqs_n_sdram[dqswd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
end
endgenerate
//===========================================================================
// FPGA Memory Controller
//===========================================================================
example_top #
(
.SIMULATION (SIMULATION),
// .BL_WIDTH (BL_WIDTH),
.PORT_MODE (PORT_MODE),
.DATA_MODE (DATA_MODE),
.TST_MEM_INSTR_MODE (TST_MEM_INSTR_MODE),
.EYE_TEST (EYE_TEST),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN),
// .SEL_VICTIM_LINE (SEL_VICTIM_LINE),
// .ADDR_MODE (ADDR_MODE),
.BEGIN_ADDRESS (BEGIN_ADDRESS),
.END_ADDRESS (END_ADDRESS),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.BANK_WIDTH (BANK_WIDTH),
// .CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
// .nCS_PER_RANK (nCS_PER_RANK),
// .CKE_WIDTH (CKE_WIDTH),
// .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
// .DQ_CNT_WIDTH (DQ_CNT_WIDTH),
// .DQ_PER_DM (DQ_PER_DM),
// .DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
// .ECC (ECC),
.ECC_TEST (ECC_TEST),
// .nBANK_MACHS (nBANK_MACHS),
.RANKS (RANKS),
// .ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
// .USE_CS_PORT (USE_CS_PORT),
// .USE_DM_PORT (USE_DM_PORT),
// .USE_ODT_PORT (USE_ODT_PORT),
// .AL (AL),
// .nAL (nAL),
.BURST_MODE (BURST_MODE),
// .BURST_TYPE (BURST_TYPE),
// .CL (CL),
// .OUTPUT_DRV (OUTPUT_DRV),
// .RTT_NOM (RTT_NOM),
// .ADDR_CMD_MODE (ADDR_CMD_MODE),
// .REG_CTRL (REG_CTRL),
// .CLKIN_PERIOD (CLKIN_PERIOD),
// .CLKFBOUT_MULT (CLKFBOUT_MULT),
// .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
// .CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
// .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
// .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
// .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
// .tCKE (tCKE),
// .tFAW (tFAW),
// .tRAS (tRAS),
// .tRCD (tRCD),
// .tREFI (tREFI),
// .tRFC (tRFC),
// .tRP (tRP),
// .tRRD (tRRD),
// .tRTP (tRTP),
// .tWTR (tWTR),
// .tZQI (tZQI),
// .tZQCS (tZQCS),
// .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
// .BYTE_LANES_B0 (BYTE_LANES_B0),
// .BYTE_LANES_B1 (BYTE_LANES_B1),
// .BYTE_LANES_B2 (BYTE_LANES_B2),
// .BYTE_LANES_B3 (BYTE_LANES_B3),
// .BYTE_LANES_B4 (BYTE_LANES_B4),
// .DATA_CTL_B0 (DATA_CTL_B0),
// .DATA_CTL_B1 (DATA_CTL_B1),
// .DATA_CTL_B2 (DATA_CTL_B2),
// .DATA_CTL_B3 (DATA_CTL_B3),
// .DATA_CTL_B4 (DATA_CTL_B4),
// .PHY_0_BITLANES (PHY_0_BITLANES),
// .PHY_1_BITLANES (PHY_1_BITLANES),
// .PHY_2_BITLANES (PHY_2_BITLANES),
// .CK_BYTE_MAP (CK_BYTE_MAP),
// .ADDR_MAP (ADDR_MAP),
// .BANK_MAP (BANK_MAP),
// .CAS_MAP (CAS_MAP),
// .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
// .CKE_MAP (CKE_MAP),
// .ODT_MAP (ODT_MAP),
// .CS_MAP (CS_MAP),
// .PARITY_MAP (PARITY_MAP),
// .RAS_MAP (RAS_MAP),
// .WE_MAP (WE_MAP),
// .DQS_BYTE_MAP (DQS_BYTE_MAP),
// .DATA0_MAP (DATA0_MAP),
// .DATA1_MAP (DATA1_MAP),
// .DATA2_MAP (DATA2_MAP),
// .DATA3_MAP (DATA3_MAP),
// .DATA4_MAP (DATA4_MAP),
// .DATA5_MAP (DATA5_MAP),
// .DATA6_MAP (DATA6_MAP),
// .DATA7_MAP (DATA7_MAP),
// .DATA8_MAP (DATA8_MAP),
// .DATA9_MAP (DATA9_MAP),
// .DATA10_MAP (DATA10_MAP),
// .DATA11_MAP (DATA11_MAP),
// .DATA12_MAP (DATA12_MAP),
// .DATA13_MAP (DATA13_MAP),
// .DATA14_MAP (DATA14_MAP),
// .DATA15_MAP (DATA15_MAP),
// .DATA16_MAP (DATA16_MAP),
// .DATA17_MAP (DATA17_MAP),
// .MASK0_MAP (MASK0_MAP),
// .MASK1_MAP (MASK1_MAP),
// .SLOT_0_CONFIG (SLOT_0_CONFIG),
// .SLOT_1_CONFIG (SLOT_1_CONFIG),
// .MEM_ADDR_ORDER (MEM_ADDR_ORDER),
// .IBUF_LPWR_MODE (IBUF_LPWR_MODE),
// .DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
// .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
// .USER_REFRESH (USER_REFRESH),
// .WRLVL (WRLVL),
// .ORDERING (ORDERING),
// .CALIB_ROW_ADD (CALIB_ROW_ADD),
// .CALIB_COL_ADD (CALIB_COL_ADD),
// .CALIB_BA_ADD (CALIB_BA_ADD),
.TCQ (TCQ),
// .IODELAY_GRP (IODELAY_GRP),
// .SYSCLK_TYPE (SYSCLK_TYPE),
// .REFCLK_TYPE (REFCLK_TYPE),
// .DRAM_TYPE (DRAM_TYPE),
// .CAL_WIDTH (CAL_WIDTH),
// .STARVE_LIMIT (STARVE_LIMIT),
// .REFCLK_FREQ (REFCLK_FREQ),
// .tCK (tCK),
// .nCK_PER_CLK (nCK_PER_CLK),
.DEBUG_PORT (DEBUG_PORT)//,
// .RST_ACT_LOW (RST_ACT_LOW)
)
u_ip_top
(
.ddr2_dq (ddr2_dq_fpga),
.ddr2_dqs_n (ddr2_dqs_n_fpga),
.ddr2_dqs_p (ddr2_dqs_p_fpga),
.ddr2_addr (ddr2_addr_fpga),
.ddr2_ba (ddr2_ba_fpga),
.ddr2_ras_n (ddr2_ras_n_fpga),
.ddr2_cas_n (ddr2_cas_n_fpga),
.ddr2_we_n (ddr2_we_n_fpga),
.ddr2_ck_p (ddr2_ck_p_fpga),
.ddr2_ck_n (ddr2_ck_n_fpga),
.ddr2_cke (ddr2_cke_fpga),
.ddr2_cs_n (ddr2_cs_n_fpga),
.ddr2_dm (ddr2_dm_fpga),
.ddr2_odt (ddr2_odt_fpga),
.sys_clk_i (sys_clk_i),
.init_calib_complete (init_calib_complete),
.tg_compare_error (tg_compare_error),
.sys_rst (sys_rst)
);
//**************************************************************************//
// Memory Models instantiations
//**************************************************************************//
genvar r,i;
generate
for (r = 0; r < CS_WIDTH; r = r + 1) begin: mem_rnk
if(DQ_WIDTH/16) begin: mem
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr2_model u_comp_ddr2
(
.ck (ddr2_ck_p_sdram[0+(NUM_COMP*r)]),
.ck_n (ddr2_ck_n_sdram[0+(NUM_COMP*r)]),
.cke (ddr2_cke_sdram[0+(NUM_COMP*r)]),
.cs_n (ddr2_cs_n_sdram[0+(NUM_COMP*r)]),
.ras_n (ddr2_ras_n_sdram),
.cas_n (ddr2_cas_n_sdram),
.we_n (ddr2_we_n_sdram),
.dm_rdqs (ddr2_dm_sdram[(2*(i+1)-1):(2*i)]),
.ba (ddr2_ba_sdram),
.addr (ddr2_addr_sdram),
.dq (ddr2_dq_sdram[16*(i+1)-1:16*(i)]),
.dqs (ddr2_dqs_p_sdram[(2*(i+1)-1):(2*i)]),
.dqs_n (ddr2_dqs_n_sdram[(2*(i+1)-1):(2*i)]),
.rdqs_n (),
.odt (ddr2_odt_sdram[0+(NUM_COMP*r)])
);
end
end
if (DQ_WIDTH%16) begin: gen_mem_extrabits
ddr2_model u_comp_ddr2
(
.ck (ddr2_ck_p_sdram[0+(NUM_COMP*r)]),
.ck_n (ddr2_ck_n_sdram[0+(NUM_COMP*r)]),
.cke (ddr2_cke_sdram[0+(NUM_COMP*r)]),
.cs_n (ddr2_cs_n_sdram[0+(NUM_COMP*r)]),
.ras_n (ddr2_ras_n_sdram),
.cas_n (ddr2_cas_n_sdram),
.we_n (ddr2_we_n_sdram),
.dm_rdqs ({ddr2_dm_sdram[DM_WIDTH-1],ddr2_dm_sdram[DM_WIDTH-1]}),
.ba (ddr2_ba_sdram),
.addr (ddr2_addr_sdram),
.dq ({ddr2_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)],
ddr2_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),
.dqs ({ddr2_dqs_p_sdram[DQS_WIDTH-1],
ddr2_dqs_p_sdram[DQS_WIDTH-1]}),
.dqs_n ({ddr2_dqs_n_sdram[DQS_WIDTH-1],
ddr2_dqs_n_sdram[DQS_WIDTH-1]}),
.rdqs_n (),
.odt (ddr2_odt_sdram[0+(NUM_COMP*r)])
);
end
end
endgenerate
//***************************************************************************
// Reporting the test case status
// Status reporting logic exists both in simulation test bench (sim_tb_top)
// and sim.do file for ModelSim. Any update in simulation run time or time out
// in this file need to be updated in sim.do file as well.
//***************************************************************************
initial
begin : Logging
fork
begin : calibration_done
wait (init_calib_complete);
$display("Calibration Done");
#50000000.0;
if (!tg_compare_error) begin
$display("TEST PASSED");
end
else begin
$display("TEST FAILED: DATA ERROR");
end
disable calib_not_done;
$finish;
end
begin : calib_not_done
if (SIM_BYPASS_INIT_CAL == "SIM_INIT_CAL_FULL")
#2500000000.0;
else
#1000000000.0;
if (!init_calib_complete) begin
$display("TEST FAILED: INITIALIZATION DID NOT COMPLETE");
end
disable calibration_done;
$finish;
end
join
end
endmodule
|
//wb_i2c.v
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE revB.2 compliant I2C Master controller Top-level ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
/*
Adapted from OpenCores I2C project
Author: [email protected]
*/
/*
Self Defining Bus (SDB)
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x00000000
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: (19 UNICODE characters)
SDB_NAME:wb_i2c
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x04
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0x01
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/01/07
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:7
*/
`include "project_defines.v"
`include "timescale.v"
`define CLK_DIVIDE_100KHZ (`CLOCK_RATE/(5 * 100000) - 1)
`define CLK_DIVIDE_400KHZ (`CLOCK_RATE/(5 * 400000) - 1)
module wb_i2c (
input clk,
input rst,
//wishbone slave signals
input i_wbs_we,
input i_wbs_stb,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_adr,
input [31:0] i_wbs_dat,
output reg [31:0] o_wbs_dat,
output reg o_wbs_ack,
output reg o_wbs_int,
inout scl,
inout sda
);
localparam ADDR_CONTROL = 32'h00000000;
localparam ADDR_STATUS = 32'h00000001;
localparam ADDR_CLOCK_RATE = 32'h00000002;
localparam ADDR_CLOCK_DIVIDER = 32'h00000003;
localparam ADDR_COMMAND = 32'h00000004;
localparam ADDR_TRANSMIT = 32'h00000005;
localparam ADDR_RECEIVE = 32'h00000006;
//Registers/Wires
reg [15:0] clock_divider;
reg [7:0] control;
reg [7:0] transmit;
wire [7:0] receive;
reg [7:0] command;
wire [7:0] status;
wire done;
//core enable signal
wire core_en;
wire ien;
//Control Register bits
wire start;
wire stop;
wire read;
wire write;
wire ack;
reg iack;
wire core_reset;
//Status Register
wire irxack;
reg rxack; //Received acknowledge from slave
reg tip; //Tranfer in progress
reg irq_flag; //interrupt pending flag
wire i2c_busy; //busy (start sigal detected)
wire i2c_al; //arbitration lost
reg al; //arbitration lost
//Assigns
//Command
assign start = command[0];
assign stop = command[1];
assign read = command[2];
assign write = command[3];
assign ack = command[4];
// Control
assign core_en = control[0];
assign ien = control[1];
assign set_100khz = control[2];
assign set_400khz = control[3];
assign core_reset = control[7];
// assign status register bits
assign status[7] = rxack;
assign status[6] = i2c_busy;
assign status[5] = al;
assign status[4:2] = 3'h0; // reserved
assign status[1] = tip;
assign status[0] = irq_flag;
assign scl = scl_oen ? 1'hZ : scl_out;
assign sda = sda_oen ? 1'hZ : sda_out;
i2c_master_byte_ctrl byte_controller (
.clk (clk ),
.rst (rst | core_reset ),
.nReset (1 ),
.ena (core_en ),
.clk_cnt (clock_divider ),
.start (start ),
.stop (stop ),
.read (read ),
.write (write ),
.ack_in (ack ),
.din (transmit ),
.cmd_ack (done ),
.ack_out (irxack ),
.dout (receive ),
.i2c_busy (i2c_busy ),
.i2c_al (i2c_al ),
.scl_i (scl ),
.scl_o (scl_out ),
.scl_oen (scl_oen ),
.sda_i (sda ),
.sda_o (sda_out ),
.sda_oen (sda_oen )
);
//blocks
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
clock_divider <= `CLK_DIVIDE_100KHZ;
control <= 8'h01;
transmit <= 8'h00;
command <= 8'h00;
al <= 0;
rxack <= 0;
tip <= 0;
irq_flag <= 0;
iack <= 0;
end
else begin
iack <= 0;
//when the master acks our ack, then put our ack down
if (o_wbs_ack & ~ i_wbs_stb)begin
o_wbs_ack <= 0;
//clear IRQ ACK bit
command[0] <= 0;
end
if (i_wbs_stb & i_wbs_cyc) begin
//master is requesting something
o_wbs_int <= 0;
//acknowledge an interrupt
iack <= 1;
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
ADDR_CONTROL: begin
control <= i_wbs_dat[7:0];
end
ADDR_CLOCK_DIVIDER: begin
clock_divider <= i_wbs_dat[15:0];
end
ADDR_COMMAND: begin
command <= i_wbs_dat[7:0];
end
ADDR_TRANSMIT: begin
transmit <= i_wbs_dat[7:0];
end
default: begin
end
endcase
end
else begin
//reset the interrupt when the user reads anything
//read request
case (i_wbs_adr)
ADDR_CONTROL: begin
o_wbs_dat <= {24'h000000, control};
end
ADDR_STATUS: begin
o_wbs_dat <= {24'h000000, status};
end
ADDR_CLOCK_RATE: begin
o_wbs_dat <= `CLOCK_RATE;
end
ADDR_CLOCK_DIVIDER: begin
o_wbs_dat <= {16'h0000, clock_divider};
end
ADDR_COMMAND: begin
o_wbs_dat <= {24'h000000, command};
end
ADDR_TRANSMIT: begin
o_wbs_dat <= {24'h000000, transmit};
end
ADDR_RECEIVE: begin
o_wbs_dat <= {24'h000000, receive};
end
default: begin
o_wbs_dat <= 32'h0000000;
end
endcase
end
o_wbs_ack <= 1;
end
//clear the reserved bits
command[7:5] <= 2'b00;
if (set_100khz) begin
clock_divider <= `CLK_DIVIDE_100KHZ;
//reset the control so they don't keep firing off
control[2] <= 0;
control[3] <= 0;
end
if (set_400khz) begin
//reset the control so they don't keep firing off
clock_divider <= `CLK_DIVIDE_400KHZ;
control[2] <= 0;
control[3] <= 0;
end
if (core_reset) begin
control[7] <= 0;
end
//control/status
al <= i2c_al | (al & ~start);
rxack <= irxack;
tip <= (read | write);
irq_flag <= (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
if (irq_flag && ien) begin
//interrupt enable and irq_flag fired off
o_wbs_int <= 1;
end
//Handle Status/Control oneshots
if (done | i2c_al) begin
command[3:0] <= 4'h0;
end
end
end
endmodule
|
// HeaderTrailer.v
//
// Author Beat Meier PSI
// Date Nov 10 2014
//
module HeaderTrailer
(
input Sdat,
input CLK,
input Trailer_OLD_NEW_0_1,
output reg TBM_HEADER,
output reg ROC_HEADER,
output reg TBM_TRAILER,
output reg gate,
output sdo
);
reg start;
reg [4:0]delay;
wire veto = delay != 0;
reg [14:0]shift;
// --- shift register (shift <- Sdat)
always @(posedge CLK) shift <= {shift[13:0], Sdat};
wire [8:0]leader = shift[11:3]; // 9 bit leader (011111111)
wire [2:0]id = shift[3:1]; // 3 bit header id (1 CLK cycle delayed)
assign sdo = shift[14]; // serial data output
// --- 9 bit start marker detector 011111111
always @(posedge CLK) start <= (leader == 9'b011111111) && !veto;
// --- veto counter to skip TBM header/trailer data
always @(posedge CLK)
begin
if (TBM_HEADER || TBM_TRAILER) delay <= 22;
else if (veto) delay <= delay - 1;
end
// --- header/trailer type separation
always @(posedge CLK)
begin
TBM_HEADER <= start && (id == 3'b100);
TBM_TRAILER <= start && (id == {2'b11, ~Trailer_OLD_NEW_0_1});
ROC_HEADER <= start && !id[2];
end
// --- data gate
always @(posedge CLK)
begin
if (TBM_HEADER) gate <= 1;
else if (TBM_TRAILER) gate <= 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4BB_2_V
`define SKY130_FD_SC_HD__NAND4BB_2_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4bb_2 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4bb_2 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4BB_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD1_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD1_FUNCTIONAL_PP_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__dlygate4sd1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD1_FUNCTIONAL_PP_V |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.