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stringlengths 938
1.05M
|
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module BufferIn(
input wire Clk,
input wire InputBuffer,
output reg [17:0] oBufferIn,
output reg EndOfFile
);
reg [17:0] tmpChar;
integer i;
initial
begin
i = $fopen("original.txt");
EndOfFile = 1'b0;
end
always @ (posedge Clk)
begin
if(InputBuffer)
begin
tmpChar = $fgetc(i);
if($feof(i))
EndOfFile = 1'b1;
else
oBufferIn = tmpChar;
end
end
endmodule
module BufferOut(
input wire Clk,
input wire OutputBuffer,
input wire CloseBuffer,
input wire [11:0] iBufferOut
);
integer f;
initial
f = $fopen("compressed.txt");
always @ (posedge Clk)
begin
if(OutputBuffer)
$fwrite(f,"%b", iBufferOut);
if(CloseBuffer)
begin
$fflush(f);
$fclose(f);
$finish;
end
end
endmodule
module RAMBuffer(
input wire RAMread,
input wire RAMZeroData,
input wire InitRAMCode,
input wire WriteString,
input wire [7:0] ramCode,
input wire [15:0] ramString,
input wire [17:0] ramDicPointer,
output reg [15:0] oRAMBuffer
);
reg [15:0] RAM [262143:0];
always @ (*)
begin
if(RAMZeroData)
RAM[ramDicPointer] = 16'b0;
else if(InitRAMCode)
RAM[ramDicPointer] = {8'b0, ramCode};
else if(WriteString)
RAM[ramDicPointer] = ramString;
else if(RAMread)
oRAMBuffer = RAM[ramDicPointer];
end
endmodule
|
`timescale 1ns/1ns
module axi_ms_tb;
reg clk, rst;
wire [31:0] ARADDR;
wire ARVALID;
wire ARREADY;
wire [7:0] ARLEN;
wire [2:0] ARSIZE;
wire RVALID;
wire [31:0] RDATA;
wire RREADY;
wire RLAST;
wire [31:0] AWADDR;
wire AWVALID;
wire AWREADY;
wire [7:0] AWLEN;
wire [2:0] AWSIZE;
wire WVALID;
wire WREADY;
wire [31:0] WDATA;
wire WLAST;
wire BVALID;
wire BREADY;
wire [1:0] BRESP;
initial begin
clk <= 0;
rst <= 1;
#15
rst <= ~rst;
#10000
$finish;
end
always begin
#10 clk = ~clk;
end
mod_main main_inst(.clk(clk), .rst(rst),
.a_ARADDR(ARADDR), .b_ARADDR(ARADDR),
.a_ARVALID(ARVALID),. b_ARVALID(ARVALID),
.a_ARREADY(ARREADY), .b_ARREADY(ARREADY),
.a_ARLEN(ARLEN), .b_ARLEN(ARLEN),
.a_ARSIZE(ARSIZE), .b_ARSIZE(ARSIZE),
.a_RVALID(RVALID), .b_RVALID(RVALID),
.a_RDATA(RDATA), .b_RDATA(RDATA),
.a_RREADY(RREADY), .b_RREADY(RREADY),
.a_RLAST(RLAST), .b_RLAST(RLAST),
.a_AWADDR(AWADDR), .b_AWADDR(AWADDR),
.a_AWVALID(AWVALID), .b_AWVALID(AWVALID),
.a_AWREADY(AWREADY), .b_AWREADY(AWREADY),
.a_AWLEN(AWLEN), .b_AWLEN(AWLEN),
.a_AWSIZE(AWSIZE), .b_AWSIZE(AWSIZE),
.a_WVALID(WVALID), .b_WVALID(WVALID),
.a_WREADY(WREADY), .b_WREADY(WREADY),
.a_WDATA(WDATA), .b_WDATA(WDATA),
.a_WLAST(WLAST), .b_WLAST(WLAST),
.a_BVALID(BVALID), .b_BVALID(BVALID),
.a_BREADY(BREADY), .b_BREADY(BREADY),
.a_BRESP(BRESP), .b_BRESP(BRESP)
);
endmodule // axi_ms_tb
|
//======================================================================
//
// online_tester.v
// ---------------
// Top level module in online random number generator tester.
// The module is basically a framework for instatiating and using
// specific test modules.
//
// The tests implemented are basically AIS31 with some additions.
// For more info, see the specific test modules.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module online_tester(
// Clock and reset.
input wire clk,
input wire reset_n,
// Control.
input wire cs,
input wire we,
// Data ports.
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire ready,
output wire warning,
output wire error
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam CORE_NAME0 = 32'h6f6c5f74; // "ol_t"
localparam CORE_NAME1 = 32'h65737420; // "est "
localparam CORE_VERSION = 32'h302e3130; // "0.10"
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Instantiations.
//----------------------------------------------------------------
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
end
else
begin
end
end // reg_update
endmodule // online_tester
//======================================================================
// EOF online_tester.v
//======================================================================
|
///////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.i (O.4)
// \ \ Description :
// / /
// /__/ /\ Filename : PLLE2_BASE.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// 12/09/09 - Initial version
// 03/23/10 - Change CLKFBOUT_MULT default from 1 to 5.
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PLLE2_BASE (
CLKFBOUT,
CLKOUT0,
CLKOUT1,
CLKOUT2,
CLKOUT3,
CLKOUT4,
CLKOUT5,
LOCKED,
CLKFBIN,
CLKIN1,
PWRDWN,
RST
);
parameter BANDWIDTH = "OPTIMIZED";
parameter integer CLKFBOUT_MULT = 5;
parameter real CLKFBOUT_PHASE = 0.000;
parameter real CLKIN1_PERIOD = 0.000;
parameter integer CLKOUT0_DIVIDE = 1;
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
parameter real CLKOUT0_PHASE = 0.000;
parameter integer CLKOUT1_DIVIDE = 1;
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
parameter real CLKOUT1_PHASE = 0.000;
parameter integer CLKOUT2_DIVIDE = 1;
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
parameter real CLKOUT2_PHASE = 0.000;
parameter integer CLKOUT3_DIVIDE = 1;
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
parameter real CLKOUT3_PHASE = 0.000;
parameter integer CLKOUT4_DIVIDE = 1;
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
parameter real CLKOUT4_PHASE = 0.000;
parameter integer CLKOUT5_DIVIDE = 1;
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
parameter real CLKOUT5_PHASE = 0.000;
parameter integer DIVCLK_DIVIDE = 1;
parameter real REF_JITTER1 = 0.010;
parameter STARTUP_WAIT = "FALSE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif //
output CLKFBOUT;
output CLKOUT0;
output CLKOUT1;
output CLKOUT2;
output CLKOUT3;
output CLKOUT4;
output CLKOUT5;
output LOCKED;
input CLKFBIN;
input CLKIN1;
input PWRDWN;
input RST;
wire OPEN_DRDY;
wire OPEN_PSDONE;
wire OPEN_FBS;
wire OPEN_INS;
wire [15:0] OPEN_DO;
PLLE2_ADV #(
.BANDWIDTH(BANDWIDTH),
.STARTUP_WAIT(STARTUP_WAIT),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.CLKFBOUT_MULT(CLKFBOUT_MULT),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.CLKIN2_PERIOD(10),
.CLKOUT0_DIVIDE(CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.REF_JITTER1(REF_JITTER1)
)
plle2_adv_1 (
.CLKFBIN (CLKFBIN),
.CLKFBOUT (CLKFBOUT),
.CLKIN1 (CLKIN1),
.CLKIN2 (1'b0),
.CLKOUT0 (CLKOUT0),
.CLKOUT1 (CLKOUT1),
.CLKOUT2 (CLKOUT2),
.CLKOUT3 (CLKOUT3),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DO (OPEN_DO),
.DRDY (OPEN_DRDY),
.DWE (1'b0),
.LOCKED (LOCKED),
.CLKINSEL(1'b1),
.PWRDWN(PWRDWN),
.RST (RST)
);
endmodule
`endcelldefine
|
`timescale 1ns / 1ps
`include "asserts.vh"
module tx_top_v();
reg [11:0] story_tb;
reg clk, reset;
reg [7:0] dat_i;
reg lchar_i, valid_i;
wire d_o, s_o, ready_o;
tx_top top(
.txClk(clk),
.txReset(reset),
.dat_i(dat_i),
.lchar_i(lchar_i),
.valid_i(valid_i),
.d(d_o),
.s(s_o),
.ready_o(ready_o)
);
`DEFIO(clk,H,L)
`DEFASSERT0(d,o)
`DEFASSERT0(s,o)
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
// Make sure that the S signal is stable between characters.
story_tb <= 12'h000;
{clk, valid_i, lchar_i, dat_i} <= 0;
reset <= 1;
clkL(); clkH();
reset <= 0;
clkL(); clkH();
dat_i <= 8'h02;
lchar_i <= 1;
valid_i <= 1;
clkL(); clkH();
assert_d(0); assert_s(0);
story_tb <= 12'h001;
valid_i <= 0;
clkL(); clkH(); // Drives Tx pins during this cycle...
story_tb <= 12'hFFF;
clkL(); clkH(); // ... which should appear at D/S now.
assert_d(0); assert_s(1); // Parity
story_tb <= 12'hFFE;
clkL(); clkH();
assert_d(1); assert_s(1); // LChar flag
story_tb <= 12'h002;
clkL(); clkH();
assert_d(0); assert_s(1); // D0a
story_tb <= 12'h003;
clkL(); clkH();
assert_d(1); assert_s(1); // D1a
story_tb <= 12'h004;
dat_i <= 8'h00;
valid_i <= 1;
lchar_i <= 1;
clkL(); clkH();
assert_d(1); assert_s(1); // D/S stable
story_tb <= 12'h005;
valid_i <= 0;
lchar_i <= 0;
clkL(); clkH();
clkL(); clkH();
assert_d(1); assert_s(0); // Parity
story_tb <= 12'h006;
clkL(); clkH();
assert_d(1); assert_s(1); // LChar flag
story_tb <= 12'h007;
clkL(); clkH();
assert_d(0); assert_s(1); // D0b
story_tb <= 12'h008;
clkL(); clkH();
assert_d(0); assert_s(0); // D1b
$display("@I Done.");
$stop;
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* rom_style = "block" *) module Loop_loop_height_bkb_rom (
addr0, ce0, q0, addr1, ce1, q1, addr2, ce2, q2, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input[AWIDTH-1:0] addr2;
input ce2;
output reg[DWIDTH-1:0] q2;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram0[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram1[0:MEM_SIZE-1];
initial begin
$readmemh("./Loop_loop_height_bkb_rom.dat", ram0);
$readmemh("./Loop_loop_height_bkb_rom.dat", ram1);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram0[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram0[addr1];
end
end
always @(posedge clk)
begin
if (ce2)
begin
q2 <= ram1[addr2];
end
end
endmodule
`timescale 1 ns / 1 ps
module Loop_loop_height_bkb(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
input[AddressWidth - 1:0] address2;
input ce2;
output[DataWidth - 1:0] q2;
Loop_loop_height_bkb_rom Loop_loop_height_bkb_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ),
.addr2( address2 ),
.ce2( ce2 ),
.q2( q2 ));
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:52:03 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_inverter_2_0/system_inverter_2_0_sim_netlist.v
// Design : system_inverter_2_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_inverter_2_0,inverter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "inverter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_inverter_2_0
(x,
x_not);
input x;
output x_not;
wire x;
wire x_not;
LUT1 #(
.INIT(2'h1))
x_not_INST_0
(.I0(x),
.O(x_not));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* bsg_cache_to_test_dram_rx_reorder.v
*
* This module reorders dram data arriving out of order, and serializes them before feeding into vcache.
*
*/
`include "bsg_defines.v"
module bsg_cache_to_test_dram_rx_reorder
#(parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(dma_data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(dram_data_width_p)
, parameter `BSG_INV_PARAM(dram_channel_addr_width_p)
, parameter num_req_lp = (block_size_in_words_p*data_width_p/dram_data_width_p)
, parameter lg_num_req_lp = `BSG_SAFE_CLOG2(num_req_lp)
, parameter dram_data_byte_offset_width_lp = `BSG_SAFE_CLOG2(dram_data_width_p>>3)
)
(
input core_clk_i
, input core_reset_i
, input dram_v_i
, input [dram_data_width_p-1:0] dram_data_i
, input [dram_channel_addr_width_p-1:0] dram_ch_addr_i
, output logic [dma_data_width_p-1:0] dma_data_o
, output logic dma_data_v_o
, input dma_data_ready_i
);
logic piso_ready_lo;
logic piso_v_li;
logic [dram_data_width_p-1:0] piso_data_li;
bsg_parallel_in_serial_out #(
.width_p(dma_data_width_p)
,.els_p(dram_data_width_p/dma_data_width_p)
) piso (
.clk_i(core_clk_i)
,.reset_i(core_reset_i)
,.valid_i(piso_v_li)
,.data_i(piso_data_li)
,.ready_and_o(piso_ready_lo)
,.valid_o(dma_data_v_o)
,.data_o(dma_data_o)
,.yumi_i(dma_data_v_o & dma_data_ready_i)
);
if (num_req_lp == 1) begin: req1
// if there is only one DRAM request, there is no need to reorder.
assign piso_data_li = dram_data_i;
assign piso_v_li = dram_v_i;
wire unused = |dram_ch_addr_i;
// synopsys translate_off
always_ff @ (negedge core_clk_i) begin
if (~core_reset_i & dram_v_i) begin
assert(piso_ready_lo) else $fatal("piso is not ready!");
end
end
// synopsys translate_on
end
else begin: reqn
// reordering logic
// when the data arrives during its turn, go into the piso, if the piso is ready. Then, increment the counter.
// If the piso is not ready, then go into the buffer.
// If the piso is ready, and the data is available in the buffer, put that in piso and increment the counter.
// when the data arrives and it's not its turn, then wait in the buffer.
wire [lg_num_req_lp-1:0] req_num = dram_ch_addr_i[dram_data_byte_offset_width_lp+:lg_num_req_lp];
// data that is not ready to go into piso is buffered here.
logic [dram_data_width_p-1:0] data_buffer_r [num_req_lp-1:0];
logic [num_req_lp-1:0] data_buffer_v_r;
logic counter_clear;
logic counter_up;
logic [lg_num_req_lp-1:0] count_r;
// this counts the number of DRAM data that have arrived and been fed into the piso.
// the data is fed into the piso sequentially in address order.
bsg_counter_clear_up #(
.max_val_p(num_req_lp-1)
,.init_val_p(0)
) c0 (
.clk_i(core_clk_i)
,.reset_i(core_reset_i)
,.clear_i(counter_clear)
,.up_i(counter_up)
,.count_o(count_r)
);
logic clear_buffer;
logic write_buffer;
always_comb begin
piso_v_li = 1'b0;
piso_data_li = dram_data_i;
counter_clear = 1'b0;
counter_up = 1'b0;
clear_buffer = 1'b0;
write_buffer = 1'b0;
if (count_r == num_req_lp-1) begin
piso_v_li = data_buffer_v_r[count_r] | ((req_num == count_r) & dram_v_i);
piso_data_li = data_buffer_v_r[count_r]
? data_buffer_r[count_r]
: dram_data_i;
counter_clear = piso_ready_lo & (data_buffer_v_r[count_r] | ((req_num == count_r) & dram_v_i));
write_buffer = ~piso_ready_lo & dram_v_i;
clear_buffer = piso_ready_lo & (data_buffer_v_r[count_r] | ((req_num == count_r) & dram_v_i));
end
else begin
piso_v_li = data_buffer_v_r[count_r] | ((req_num == count_r) & dram_v_i);
piso_data_li = data_buffer_v_r[count_r]
? data_buffer_r[count_r]
: dram_data_i;
counter_up = piso_ready_lo & (data_buffer_v_r[count_r] | ((req_num == count_r) & dram_v_i));
write_buffer = (dram_v_i & ((req_num != count_r) | ~piso_ready_lo));
end
end
always_ff @ (posedge core_clk_i) begin
if (core_reset_i) begin
data_buffer_v_r <= '0;
end
else begin
if (clear_buffer) begin
data_buffer_v_r <= '0;
end
else if (write_buffer) begin
data_buffer_v_r[req_num] <= 1'b1;
data_buffer_r[req_num] <= dram_data_i;
end
end
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_to_test_dram_rx_reorder)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41AI_0_V
`define SKY130_FD_SC_LP__O41AI_0_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41ai_0 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41ai_0 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41AI_0_V
|
`include "minsoc_defines.v"
`include "or1200_defines.v"
module minsoc_top (
clk,reset
//JTAG ports
`ifdef GENERIC_TAP
, jtag_tdi,jtag_tms,jtag_tck,
jtag_tdo,jtag_vref,jtag_gnd
`endif
//SPI ports
`ifdef START_UP
, spi_flash_mosi, spi_flash_miso, spi_flash_sclk, spi_flash_ss
`endif
//UART ports
`ifdef UART
, uart_stx,uart_srx
`endif
// Ethernet ports
`ifdef ETHERNET
, eth_col, eth_crs, eth_trste, eth_tx_clk,
eth_tx_en, eth_tx_er, eth_txd, eth_rx_clk,
eth_rx_dv, eth_rx_er, eth_rxd, eth_fds_mdint,
eth_mdc, eth_mdio
`endif
);
//
// I/O Ports
//
input clk;
input reset;
//
// SPI controller external i/f wires
//
`ifdef START_UP
output spi_flash_mosi;
input spi_flash_miso;
output spi_flash_sclk;
output [1:0] spi_flash_ss;
`endif
//
// UART
//
`ifdef UART
output uart_stx;
input uart_srx;
`endif
//
// Ethernet
//
`ifdef ETHERNET
output eth_tx_er;
input eth_tx_clk;
output eth_tx_en;
output [3:0] eth_txd;
input eth_rx_er;
input eth_rx_clk;
input eth_rx_dv;
input [3:0] eth_rxd;
input eth_col;
input eth_crs;
output eth_trste;
input eth_fds_mdint;
inout eth_mdio;
output eth_mdc;
`endif
//
// JTAG
//
`ifdef GENERIC_TAP
input jtag_tdi;
input jtag_tms;
input jtag_tck;
output jtag_tdo;
output jtag_vref;
output jtag_gnd;
assign jtag_vref = 1'b1;
assign jtag_gnd = 1'b0;
`endif
wire rstn;
`ifdef POSITIVE_RESET
assign rstn = ~reset;
`elsif NEGATIVE_RESET
assign rstn = reset;
`endif
//
// Internal wires
//
//
// Debug core master i/f wires
//
wire [31:0] wb_dm_adr_o;
wire [31:0] wb_dm_dat_i;
wire [31:0] wb_dm_dat_o;
wire [3:0] wb_dm_sel_o;
wire wb_dm_we_o;
wire wb_dm_stb_o;
wire wb_dm_cyc_o;
wire wb_dm_ack_i;
wire wb_dm_err_i;
//
// Debug core JSP slave i/f wires
//
wire [31:0] wb_jsp_dat_i;
wire [31:0] wb_jsp_dat_o;
wire [31:0] wb_jsp_adr_i;
wire [3:0] wb_jsp_sel_i;
wire wb_jsp_we_i;
wire wb_jsp_cyc_i;
wire wb_jsp_stb_i;
wire wb_jsp_ack_o;
wire wb_jsp_err_o;
//
// Debug <-> RISC wires
//
wire [3:0] dbg_lss;
wire [1:0] dbg_is;
wire [10:0] dbg_wp;
wire dbg_bp;
wire [31:0] dbg_dat_dbg;
wire [31:0] dbg_dat_risc;
wire [31:0] dbg_adr;
wire dbg_ewt;
wire dbg_stall;
wire dbg_we;
wire dbg_stb;
wire dbg_ack;
//
// RISC instruction master i/f wires
//
wire [31:0] wb_rim_adr_o;
wire wb_rim_cyc_o;
wire [31:0] wb_rim_dat_i;
wire [31:0] wb_rim_dat_o;
wire [3:0] wb_rim_sel_o;
wire wb_rim_ack_i;
wire wb_rim_err_i;
wire wb_rim_rty_i = 1'b0;
wire wb_rim_we_o;
wire wb_rim_stb_o;
wire [31:0] wb_rif_dat_i;
wire wb_rif_ack_i;
//
// RISC data master i/f wires
//
wire [31:0] wb_rdm_adr_o;
wire wb_rdm_cyc_o;
wire [31:0] wb_rdm_dat_i;
wire [31:0] wb_rdm_dat_o;
wire [3:0] wb_rdm_sel_o;
wire wb_rdm_ack_i;
wire wb_rdm_err_i;
wire wb_rdm_rty_i = 1'b0;
wire wb_rdm_we_o;
wire wb_rdm_stb_o;
//
// RISC misc
//
wire [`OR1200_PIC_INTS-1:0] pic_ints;
//
// Flash controller slave i/f wires
//
wire [31:0] wb_fs_dat_i;
wire [31:0] wb_fs_dat_o;
wire [31:0] wb_fs_adr_i;
wire [3:0] wb_fs_sel_i;
wire wb_fs_we_i;
wire wb_fs_cyc_i;
wire wb_fs_stb_i;
wire wb_fs_ack_o;
wire wb_fs_err_o;
//
// SPI controller slave i/f wires
//
wire [31:0] wb_sp_dat_i;
wire [31:0] wb_sp_dat_o;
wire [31:0] wb_sp_adr_i;
wire [3:0] wb_sp_sel_i;
wire wb_sp_we_i;
wire wb_sp_cyc_i;
wire wb_sp_stb_i;
wire wb_sp_ack_o;
wire wb_sp_err_o;
//
// SPI controller external i/f wires
//
wire spi_flash_mosi;
wire spi_flash_miso;
wire spi_flash_sclk;
wire [1:0] spi_flash_ss;
//
// SRAM controller slave i/f wires
//
wire [31:0] wb_ss_dat_i;
wire [31:0] wb_ss_dat_o;
wire [31:0] wb_ss_adr_i;
wire [3:0] wb_ss_sel_i;
wire wb_ss_we_i;
wire wb_ss_cyc_i;
wire wb_ss_stb_i;
wire wb_ss_ack_o;
wire wb_ss_err_o;
//
// Ethernet core master i/f wires
//
wire [31:0] wb_em_adr_o;
wire [31:0] wb_em_dat_i;
wire [31:0] wb_em_dat_o;
wire [3:0] wb_em_sel_o;
wire wb_em_we_o;
wire wb_em_stb_o;
wire wb_em_cyc_o;
wire wb_em_ack_i;
wire wb_em_err_i;
//
// Ethernet core slave i/f wires
//
wire [31:0] wb_es_dat_i;
wire [31:0] wb_es_dat_o;
wire [31:0] wb_es_adr_i;
wire [3:0] wb_es_sel_i;
wire wb_es_we_i;
wire wb_es_cyc_i;
wire wb_es_stb_i;
wire wb_es_ack_o;
wire wb_es_err_o;
//
// Ethernet external i/f wires
//
wire eth_mdo;
wire eth_mdoe;
//
// UART16550 core slave i/f wires
//
wire [31:0] wb_us_dat_i;
wire [31:0] wb_us_dat_o;
wire [31:0] wb_us_adr_i;
wire [3:0] wb_us_sel_i;
wire wb_us_we_i;
wire wb_us_cyc_i;
wire wb_us_stb_i;
wire wb_us_ack_o;
wire wb_us_err_o;
//
// UART external i/f wires
//
wire uart_stx;
wire uart_srx;
//
// Reset debounce
//
reg rst_r;
reg wb_rst;
//
// Global clock
//
wire wb_clk;
//
// Reset debounce
//
always @(posedge wb_clk or negedge rstn)
if (~rstn)
rst_r <= 1'b1;
else
rst_r <= #1 1'b0;
//
// Reset debounce
//
always @(posedge wb_clk)
wb_rst <= #1 rst_r;
//
// Clock Divider
//
minsoc_clock_manager #
(
.divisor(`CLOCK_DIVISOR)
)
clk_adjust (
.clk_i(clk),
.clk_o(wb_clk)
);
//
// Unused WISHBONE signals
//
assign wb_us_err_o = 1'b0;
assign wb_fs_err_o = 1'b0;
assign wb_sp_err_o = 1'b0;
//
// Unused interrupts
//
assign pic_ints[`APP_INT_RES1] = 'b0;
assign pic_ints[`APP_INT_RES2] = 'b0;
assign pic_ints[`APP_INT_RES3] = 'b0;
assign pic_ints[`APP_INT_PS2] = 'b0;
//
// Ethernet tri-state
//
`ifdef ETHERNET
assign eth_mdio = eth_mdoe ? eth_mdo : 1'bz;
assign eth_trste = `ETH_RESET;
`endif
//
// RISC Instruction address for Flash
//
// Until first access to real Flash area,
// CPU instruction is fixed to jump to the Flash area.
// After Flash area is accessed, CPU instructions
// come from the tc_top (wishbone "switch").
//
`ifdef START_UP
reg jump_flash;
reg [3:0] rif_counter;
reg [31:0] rif_dat_int;
reg rif_ack_int;
always @(posedge wb_clk or negedge rstn)
begin
if (!rstn) begin
jump_flash <= #1 1'b1;
rif_counter <= 4'h0;
rif_ack_int <= 1'b0;
end
else begin
rif_ack_int <= 1'b0;
if (wb_rim_cyc_o && (wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH))
jump_flash <= #1 1'b0;
if ( jump_flash == 1'b1 ) begin
if ( wb_rim_cyc_o && wb_rim_stb_o && ~wb_rim_we_o )
rif_ack_int <= 1'b1;
if ( rif_ack_int == 1'b1 ) begin
rif_counter <= rif_counter + 1'b1;
rif_ack_int <= 1'b0;
end
end
end
end
always @ (rif_counter)
begin
case ( rif_counter )
4'h0: rif_dat_int = { `OR1200_OR32_MOVHI , 5'h01 , 4'h0 , 1'b0 , `APP_ADDR_FLASH , 8'h00 };
4'h1: rif_dat_int = { `OR1200_OR32_ORI , 5'h01 , 5'h01 , 16'h0000 };
4'h2: rif_dat_int = { `OR1200_OR32_JR , 10'h000 , 5'h01 , 11'h000 };
4'h3: rif_dat_int = { `OR1200_OR32_NOP , 10'h000 , 16'h0000 };
default: rif_dat_int = 32'h0000_0000;
endcase
end
assign wb_rif_dat_i = jump_flash ? rif_dat_int : wb_rim_dat_i;
assign wb_rif_ack_i = jump_flash ? rif_ack_int : wb_rim_ack_i;
`else
assign wb_rif_dat_i = wb_rim_dat_i;
assign wb_rif_ack_i = wb_rim_ack_i;
`endif
//
// TAP<->dbg_interface
//
wire jtag_tck;
wire debug_tdi;
wire debug_tdo;
wire capture_dr;
wire shift_dr;
wire pause_dr;
wire update_dr;
wire debug_select;
wire test_logic_reset;
//
// Instantiation of the development i/f
//
adbg_top dbg_top (
// JTAG pins
.tck_i ( jtag_tck ),
.tdi_i ( debug_tdi ),
.tdo_o ( debug_tdo ),
.rst_i ( test_logic_reset ), //cable without rst
// Boundary Scan signals
.capture_dr_i ( capture_dr ),
.shift_dr_i ( shift_dr ),
.pause_dr_i ( pause_dr ),
.update_dr_i ( update_dr ),
.debug_select_i( debug_select ),
// WISHBONE common
.wb_clk_i ( wb_clk ),
// WISHBONE master interface
.wb_adr_o ( wb_dm_adr_o ),
.wb_dat_i ( wb_dm_dat_i ),
.wb_dat_o ( wb_dm_dat_o ),
.wb_sel_o ( wb_dm_sel_o ),
.wb_we_o ( wb_dm_we_o ),
.wb_stb_o ( wb_dm_stb_o ),
.wb_cyc_o ( wb_dm_cyc_o ),
.wb_ack_i ( wb_dm_ack_i ),
.wb_err_i ( wb_dm_err_i ),
.wb_cti_o ( ),
.wb_bte_o ( ),
// RISC signals
.cpu0_clk_i ( wb_clk ),
.cpu0_addr_o ( dbg_adr ),
.cpu0_data_i ( dbg_dat_risc ),
.cpu0_data_o ( dbg_dat_dbg ),
.cpu0_bp_i ( dbg_bp ),
.cpu0_stall_o( dbg_stall ),
.cpu0_stb_o ( dbg_stb ),
.cpu0_we_o ( dbg_we ),
.cpu0_ack_i ( dbg_ack ),
.cpu0_rst_o ( ),
.wb_jsp_adr_i ( wb_jsp_adr_i[31:0] ),
.wb_jsp_dat_i ( wb_jsp_dat_i[31:0] ),
.wb_jsp_dat_o ( wb_jsp_dat_o[31:0] ),
.wb_jsp_we_i ( wb_jsp_we_i ),
.wb_jsp_stb_i ( wb_jsp_stb_i ),
.wb_jsp_cyc_i ( wb_jsp_cyc_i ),
.wb_jsp_ack_o ( wb_jsp_ack_o ),
.wb_jsp_sel_i ( wb_jsp_sel_i[3:0] ),
.wb_jsp_cab_i ( 1'b0 ),
.wb_jsp_cti_i ( 3'b0 ),
.wb_jsp_bte_i ( 2'b0 ),
// Interrupt request
.int_o ( pic_ints[`APP_INT_JSP] )
);
assign wb_jsp_err_o = 1'b0;
//
// JTAG TAP controller instantiation
//
`ifdef GENERIC_TAP
tap_top tap_top(
// JTAG pads
.tms_pad_i(jtag_tms),
.tck_pad_i(jtag_tck),
.trstn_pad_i(rstn),
.tdi_pad_i(jtag_tdi),
.tdo_pad_o(jtag_tdo),
.tdo_padoe_o( ),
// TAP states
.test_logic_reset_o( test_logic_reset ),
.run_test_idle_o(),
.shift_dr_o(shift_dr),
.pause_dr_o(pause_dr),
.update_dr_o(update_dr),
.capture_dr_o(capture_dr),
// Select signals for boundary scan or mbist
.extest_select_o(),
.sample_preload_select_o(),
.mbist_select_o(),
.debug_select_o(debug_select),
// TDO signal that is connected to TDI of sub-modules.
.tdi_o(debug_tdi),
// TDI signals from sub-modules
.debug_tdo_i(debug_tdo), // from debug module
.bs_chain_tdo_i(1'b0), // from Boundary Scan Chain
.mbist_tdo_i(1'b0) // from Mbist Chain
);
`elsif FPGA_TAP
`ifdef ALTERA_FPGA
altera_virtual_jtag tap_top(
.tck_o(jtag_tck),
.debug_tdo_i(debug_tdo),
.tdi_o(debug_tdi),
.test_logic_reset_o(test_logic_reset),
.run_test_idle_o(),
.shift_dr_o(shift_dr),
.capture_dr_o(capture_dr),
.pause_dr_o(pause_dr),
.update_dr_o(update_dr),
.debug_select_o(debug_select)
);
`elsif XILINX_FPGA
minsoc_xilinx_internal_jtag tap_top(
.tck_o( jtag_tck ),
.debug_tdo_i( debug_tdo ),
.tdi_o( debug_tdi ),
.test_logic_reset_o( test_logic_reset ),
.run_test_idle_o( ),
.shift_dr_o( shift_dr ),
.capture_dr_o( capture_dr ),
.pause_dr_o( pause_dr ),
.update_dr_o( update_dr ),
.debug_select_o( debug_select )
);
`endif // !FPGA_TAP
`endif // !GENERIC_TAP
//
// Instantiation of the OR1200 RISC
//
or1200_top or1200_top (
// Common
.rst_i ( wb_rst ),
.clk_i ( wb_clk ),
`ifdef OR1200_CLMODE_1TO2
.clmode_i ( 2'b01 ),
`else
`ifdef OR1200_CLMODE_1TO4
.clmode_i ( 2'b11 ),
`else
.clmode_i ( 2'b00 ),
`endif
`endif
// WISHBONE Instruction Master
.iwb_clk_i ( wb_clk ),
.iwb_rst_i ( wb_rst ),
.iwb_cyc_o ( wb_rim_cyc_o ),
.iwb_adr_o ( wb_rim_adr_o ),
.iwb_dat_i ( wb_rif_dat_i ),
.iwb_dat_o ( wb_rim_dat_o ),
.iwb_sel_o ( wb_rim_sel_o ),
.iwb_ack_i ( wb_rif_ack_i ),
.iwb_err_i ( wb_rim_err_i ),
.iwb_rty_i ( wb_rim_rty_i ),
.iwb_we_o ( wb_rim_we_o ),
.iwb_stb_o ( wb_rim_stb_o ),
// WISHBONE Data Master
.dwb_clk_i ( wb_clk ),
.dwb_rst_i ( wb_rst ),
.dwb_cyc_o ( wb_rdm_cyc_o ),
.dwb_adr_o ( wb_rdm_adr_o ),
.dwb_dat_i ( wb_rdm_dat_i ),
.dwb_dat_o ( wb_rdm_dat_o ),
.dwb_sel_o ( wb_rdm_sel_o ),
.dwb_ack_i ( wb_rdm_ack_i ),
.dwb_err_i ( wb_rdm_err_i ),
.dwb_rty_i ( wb_rdm_rty_i ),
.dwb_we_o ( wb_rdm_we_o ),
.dwb_stb_o ( wb_rdm_stb_o ),
// Debug
.dbg_stall_i ( dbg_stall ),
.dbg_dat_i ( dbg_dat_dbg ),
.dbg_adr_i ( dbg_adr ),
.dbg_ewt_i ( 1'b0 ),
.dbg_lss_o ( dbg_lss ),
.dbg_is_o ( dbg_is ),
.dbg_wp_o ( dbg_wp ),
.dbg_bp_o ( dbg_bp ),
.dbg_dat_o ( dbg_dat_risc ),
.dbg_ack_o ( dbg_ack ),
.dbg_stb_i ( dbg_stb ),
.dbg_we_i ( dbg_we ),
// Power Management
.pm_clksd_o ( ),
.pm_cpustall_i ( 1'b0 ),
.pm_dc_gate_o ( ),
.pm_ic_gate_o ( ),
.pm_dmmu_gate_o ( ),
.pm_immu_gate_o ( ),
.pm_tt_gate_o ( ),
.pm_cpu_gate_o ( ),
.pm_wakeup_o ( ),
.pm_lvolt_o ( ),
// Interrupts
.pic_ints_i ( pic_ints )
);
//
// Startup OR1k
//
`ifdef START_UP
OR1K_startup OR1K_startup0
(
.wb_adr_i(wb_fs_adr_i[6:2]),
.wb_stb_i(wb_fs_stb_i),
.wb_cyc_i(wb_fs_cyc_i),
.wb_dat_o(wb_fs_dat_o),
.wb_ack_o(wb_fs_ack_o),
.wb_clk(wb_clk),
.wb_rst(wb_rst)
);
spi_flash_top #
(
.divider(0),
.divider_len(2)
)
spi_flash_top0
(
.wb_clk_i(wb_clk),
.wb_rst_i(wb_rst),
.wb_adr_i(wb_sp_adr_i[4:2]),
.wb_dat_i(wb_sp_dat_i),
.wb_dat_o(wb_sp_dat_o),
.wb_sel_i(wb_sp_sel_i),
.wb_we_i(wb_sp_we_i),
.wb_stb_i(wb_sp_stb_i),
.wb_cyc_i(wb_sp_cyc_i),
.wb_ack_o(wb_sp_ack_o),
.mosi_pad_o(spi_flash_mosi),
.miso_pad_i(spi_flash_miso),
.sclk_pad_o(spi_flash_sclk),
.ss_pad_o(spi_flash_ss)
);
`else
assign wb_fs_dat_o = 32'h0000_0000;
assign wb_fs_ack_o = 1'b0;
assign wb_sp_dat_o = 32'h0000_0000;
assign wb_sp_ack_o = 1'b0;
`endif
//
// Instantiation of the SRAM controller
//
`ifdef MEMORY_MODEL
minsoc_memory_model #
`else
minsoc_onchip_ram_top #
`endif
(
.adr_width(`MEMORY_ADR_WIDTH) //16 blocks of 2048 bytes memory 32768
)
onchip_ram_top (
// WISHBONE common
.wb_clk_i ( wb_clk ),
.wb_rst_i ( wb_rst ),
// WISHBONE slave
.wb_dat_i ( wb_ss_dat_i ),
.wb_dat_o ( wb_ss_dat_o ),
.wb_adr_i ( wb_ss_adr_i ),
.wb_sel_i ( wb_ss_sel_i ),
.wb_we_i ( wb_ss_we_i ),
.wb_cyc_i ( wb_ss_cyc_i ),
.wb_stb_i ( wb_ss_stb_i ),
.wb_ack_o ( wb_ss_ack_o ),
.wb_err_o ( wb_ss_err_o )
);
//
// Instantiation of the UART16550
//
`ifdef UART
uart_top uart_top (
// WISHBONE common
.wb_clk_i ( wb_clk ),
.wb_rst_i ( wb_rst ),
// WISHBONE slave
.wb_adr_i ( wb_us_adr_i[4:0] ),
.wb_dat_i ( wb_us_dat_i ),
.wb_dat_o ( wb_us_dat_o ),
.wb_we_i ( wb_us_we_i ),
.wb_stb_i ( wb_us_stb_i ),
.wb_cyc_i ( wb_us_cyc_i ),
.wb_ack_o ( wb_us_ack_o ),
.wb_sel_i ( wb_us_sel_i ),
// Interrupt request
.int_o ( pic_ints[`APP_INT_UART] ),
// UART signals
// serial input/output
.stx_pad_o ( uart_stx ),
.srx_pad_i ( uart_srx ),
// modem signals
.rts_pad_o ( ),
.cts_pad_i ( 1'b0 ),
.dtr_pad_o ( ),
.dsr_pad_i ( 1'b0 ),
.ri_pad_i ( 1'b0 ),
.dcd_pad_i ( 1'b0 )
);
`else
assign wb_us_dat_o = 32'h0000_0000;
assign wb_us_ack_o = 1'b0;
assign pic_ints[`APP_INT_UART] = 1'b0;
`endif
//
// Instantiation of the Ethernet 10/100 MAC
//
`ifdef ETHERNET
ethmac ethmac (
// WISHBONE common
.wb_clk_i ( wb_clk ),
.wb_rst_i ( wb_rst ),
// WISHBONE slave
.wb_dat_i ( wb_es_dat_i ),
.wb_dat_o ( wb_es_dat_o ),
.wb_adr_i ( wb_es_adr_i[11:2] ),
.wb_sel_i ( wb_es_sel_i ),
.wb_we_i ( wb_es_we_i ),
.wb_cyc_i ( wb_es_cyc_i ),
.wb_stb_i ( wb_es_stb_i ),
.wb_ack_o ( wb_es_ack_o ),
.wb_err_o ( wb_es_err_o ),
// WISHBONE master
.m_wb_adr_o ( wb_em_adr_o ),
.m_wb_sel_o ( wb_em_sel_o ),
.m_wb_we_o ( wb_em_we_o ),
.m_wb_dat_o ( wb_em_dat_o ),
.m_wb_dat_i ( wb_em_dat_i ),
.m_wb_cyc_o ( wb_em_cyc_o ),
.m_wb_stb_o ( wb_em_stb_o ),
.m_wb_ack_i ( wb_em_ack_i ),
.m_wb_err_i ( wb_em_err_i ),
// TX
.mtx_clk_pad_i ( eth_tx_clk ),
.mtxd_pad_o ( eth_txd ),
.mtxen_pad_o ( eth_tx_en ),
.mtxerr_pad_o ( eth_tx_er ),
// RX
.mrx_clk_pad_i ( eth_rx_clk ),
.mrxd_pad_i ( eth_rxd ),
.mrxdv_pad_i ( eth_rx_dv ),
.mrxerr_pad_i ( eth_rx_er ),
.mcoll_pad_i ( eth_col ),
.mcrs_pad_i ( eth_crs ),
// MIIM
.mdc_pad_o ( eth_mdc ),
.md_pad_i ( eth_mdio ),
.md_pad_o ( eth_mdo ),
.md_padoe_o ( eth_mdoe ),
// Interrupt
.int_o ( pic_ints[`APP_INT_ETH] )
);
`else
assign wb_es_dat_o = 32'h0000_0000;
assign wb_es_ack_o = 1'b0;
assign wb_es_err_o = 1'b0;
assign wb_em_adr_o = 32'h0000_0000;
assign wb_em_sel_o = 4'h0;
assign wb_em_we_o = 1'b0;
assign wb_em_dat_o = 32'h0000_0000;
assign wb_em_cyc_o = 1'b0;
assign wb_em_stb_o = 1'b0;
assign pic_ints[`APP_INT_ETH] = 1'b0;
`endif
//
// Instantiation of the Traffic COP
//
minsoc_tc_top #(`APP_ADDR_DEC_W,
`APP_ADDR_SRAM,
`APP_ADDR_DEC_W,
`APP_ADDR_FLASH,
`APP_ADDR_DECP_W,
`APP_ADDR_PERIP,
`APP_ADDR_DEC_W,
`APP_ADDR_SPI,
`APP_ADDR_ETH,
`APP_ADDR_AUDIO,
`APP_ADDR_UART,
`APP_ADDR_JSP,
`APP_ADDR_PS2,
// `APP_ADDR_RES1,
`APP_ADDR_RES2
) tc_top (
// WISHBONE common
.wb_clk_i ( wb_clk ),
.wb_rst_i ( wb_rst ),
// WISHBONE Initiator 0
.i0_wb_cyc_i ( 1'b0 ),
.i0_wb_stb_i ( 1'b0 ),
.i0_wb_adr_i ( 32'h0000_0000 ),
.i0_wb_sel_i ( 4'b0000 ),
.i0_wb_we_i ( 1'b0 ),
.i0_wb_dat_i ( 32'h0000_0000 ),
.i0_wb_dat_o ( ),
.i0_wb_ack_o ( ),
.i0_wb_err_o ( ),
// WISHBONE Initiator 1
.i1_wb_cyc_i ( wb_em_cyc_o ),
.i1_wb_stb_i ( wb_em_stb_o ),
.i1_wb_adr_i ( wb_em_adr_o ),
.i1_wb_sel_i ( wb_em_sel_o ),
.i1_wb_we_i ( wb_em_we_o ),
.i1_wb_dat_i ( wb_em_dat_o ),
.i1_wb_dat_o ( wb_em_dat_i ),
.i1_wb_ack_o ( wb_em_ack_i ),
.i1_wb_err_o ( wb_em_err_i ),
// WISHBONE Initiator 2
.i2_wb_cyc_i ( 1'b0 ),
.i2_wb_stb_i ( 1'b0 ),
.i2_wb_adr_i ( 32'h0000_0000 ),
.i2_wb_sel_i ( 4'b0000 ),
.i2_wb_we_i ( 1'b0 ),
.i2_wb_dat_i ( 32'h0000_0000 ),
.i2_wb_dat_o ( ),
.i2_wb_ack_o ( ),
.i2_wb_err_o ( ),
// WISHBONE Initiator 3
.i3_wb_cyc_i ( wb_dm_cyc_o ),
.i3_wb_stb_i ( wb_dm_stb_o ),
.i3_wb_adr_i ( wb_dm_adr_o ),
.i3_wb_sel_i ( wb_dm_sel_o ),
.i3_wb_we_i ( wb_dm_we_o ),
.i3_wb_dat_i ( wb_dm_dat_o ),
.i3_wb_dat_o ( wb_dm_dat_i ),
.i3_wb_ack_o ( wb_dm_ack_i ),
.i3_wb_err_o ( wb_dm_err_i ),
// WISHBONE Initiator 4
.i4_wb_cyc_i ( wb_rdm_cyc_o ),
.i4_wb_stb_i ( wb_rdm_stb_o ),
.i4_wb_adr_i ( wb_rdm_adr_o ),
.i4_wb_sel_i ( wb_rdm_sel_o ),
.i4_wb_we_i ( wb_rdm_we_o ),
.i4_wb_dat_i ( wb_rdm_dat_o ),
.i4_wb_dat_o ( wb_rdm_dat_i ),
.i4_wb_ack_o ( wb_rdm_ack_i ),
.i4_wb_err_o ( wb_rdm_err_i ),
// WISHBONE Initiator 5
.i5_wb_cyc_i ( wb_rim_cyc_o ),
.i5_wb_stb_i ( wb_rim_stb_o ),
.i5_wb_adr_i ( wb_rim_adr_o ),
.i5_wb_sel_i ( wb_rim_sel_o ),
.i5_wb_we_i ( wb_rim_we_o ),
.i5_wb_dat_i ( wb_rim_dat_o ),
.i5_wb_dat_o ( wb_rim_dat_i ),
.i5_wb_ack_o ( wb_rim_ack_i ),
.i5_wb_err_o ( wb_rim_err_i ),
// WISHBONE Initiator 6
.i6_wb_cyc_i ( 1'b0 ),
.i6_wb_stb_i ( 1'b0 ),
.i6_wb_adr_i ( 32'h0000_0000 ),
.i6_wb_sel_i ( 4'b0000 ),
.i6_wb_we_i ( 1'b0 ),
.i6_wb_dat_i ( 32'h0000_0000 ),
.i6_wb_dat_o ( ),
.i6_wb_ack_o ( ),
.i6_wb_err_o ( ),
// WISHBONE Initiator 7
.i7_wb_cyc_i ( 1'b0 ),
.i7_wb_stb_i ( 1'b0 ),
.i7_wb_adr_i ( 32'h0000_0000 ),
.i7_wb_sel_i ( 4'b0000 ),
.i7_wb_we_i ( 1'b0 ),
.i7_wb_dat_i ( 32'h0000_0000 ),
.i7_wb_dat_o ( ),
.i7_wb_ack_o ( ),
.i7_wb_err_o ( ),
// WISHBONE Target 0
.t0_wb_cyc_o ( wb_ss_cyc_i ),
.t0_wb_stb_o ( wb_ss_stb_i ),
.t0_wb_adr_o ( wb_ss_adr_i ),
.t0_wb_sel_o ( wb_ss_sel_i ),
.t0_wb_we_o ( wb_ss_we_i ),
.t0_wb_dat_o ( wb_ss_dat_i ),
.t0_wb_dat_i ( wb_ss_dat_o ),
.t0_wb_ack_i ( wb_ss_ack_o ),
.t0_wb_err_i ( wb_ss_err_o ),
// WISHBONE Target 1
.t1_wb_cyc_o ( wb_fs_cyc_i ),
.t1_wb_stb_o ( wb_fs_stb_i ),
.t1_wb_adr_o ( wb_fs_adr_i ),
.t1_wb_sel_o ( wb_fs_sel_i ),
.t1_wb_we_o ( wb_fs_we_i ),
.t1_wb_dat_o ( wb_fs_dat_i ),
.t1_wb_dat_i ( wb_fs_dat_o ),
.t1_wb_ack_i ( wb_fs_ack_o ),
.t1_wb_err_i ( wb_fs_err_o ),
// WISHBONE Target 2
.t2_wb_cyc_o ( wb_sp_cyc_i ),
.t2_wb_stb_o ( wb_sp_stb_i ),
.t2_wb_adr_o ( wb_sp_adr_i ),
.t2_wb_sel_o ( wb_sp_sel_i ),
.t2_wb_we_o ( wb_sp_we_i ),
.t2_wb_dat_o ( wb_sp_dat_i ),
.t2_wb_dat_i ( wb_sp_dat_o ),
.t2_wb_ack_i ( wb_sp_ack_o ),
.t2_wb_err_i ( wb_sp_err_o ),
// WISHBONE Target 3
.t3_wb_cyc_o ( wb_es_cyc_i ),
.t3_wb_stb_o ( wb_es_stb_i ),
.t3_wb_adr_o ( wb_es_adr_i ),
.t3_wb_sel_o ( wb_es_sel_i ),
.t3_wb_we_o ( wb_es_we_i ),
.t3_wb_dat_o ( wb_es_dat_i ),
.t3_wb_dat_i ( wb_es_dat_o ),
.t3_wb_ack_i ( wb_es_ack_o ),
.t3_wb_err_i ( wb_es_err_o ),
// WISHBONE Target 4
.t4_wb_cyc_o ( ),
.t4_wb_stb_o ( ),
.t4_wb_adr_o ( ),
.t4_wb_sel_o ( ),
.t4_wb_we_o ( ),
.t4_wb_dat_o ( ),
.t4_wb_dat_i ( 32'h0000_0000 ),
.t4_wb_ack_i ( 1'b0 ),
.t4_wb_err_i ( 1'b1 ),
// WISHBONE Target 5
.t5_wb_cyc_o ( wb_us_cyc_i ),
.t5_wb_stb_o ( wb_us_stb_i ),
.t5_wb_adr_o ( wb_us_adr_i ),
.t5_wb_sel_o ( wb_us_sel_i ),
.t5_wb_we_o ( wb_us_we_i ),
.t5_wb_dat_o ( wb_us_dat_i ),
.t5_wb_dat_i ( wb_us_dat_o ),
.t5_wb_ack_i ( wb_us_ack_o ),
.t5_wb_err_i ( wb_us_err_o ),
// WISHBONE Target 6
.t6_wb_cyc_o ( ),
.t6_wb_stb_o ( ),
.t6_wb_adr_o ( ),
.t6_wb_sel_o ( ),
.t6_wb_we_o ( ),
.t6_wb_dat_o ( ),
.t6_wb_dat_i ( 32'h0000_0000 ),
.t6_wb_ack_i ( 1'b0 ),
.t6_wb_err_i ( 1'b1 ),
// WISHBONE Target 7
.t7_wb_cyc_o (wb_jsp_cyc_i ),
.t7_wb_stb_o (wb_jsp_stb_i ),
.t7_wb_adr_o (wb_jsp_adr_i ),
.t7_wb_sel_o (wb_jsp_sel_i ),
.t7_wb_we_o ( wb_jsp_we_i ),
.t7_wb_dat_o (wb_jsp_dat_i ),
.t7_wb_dat_i ( wb_jsp_dat_o ),
.t7_wb_ack_i (wb_jsp_ack_o ),
.t7_wb_err_i ( wb_jsp_err_o ),
// WISHBONE Target 8
.t8_wb_cyc_o ( ),
.t8_wb_stb_o ( ),
.t8_wb_adr_o ( ),
.t8_wb_sel_o ( ),
.t8_wb_we_o ( ),
.t8_wb_dat_o ( ),
.t8_wb_dat_i ( 32'h0000_0000 ),
.t8_wb_ack_i ( 1'b0 ),
.t8_wb_err_i ( 1'b1 )
);
//initial begin
// $dumpvars(0);
// $dumpfile("dump.vcd");
//end
endmodule
|
(*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*)
Require Import String.
Require Import List.
Require Import Arith.
Require Import Peano_dec.
Require Import EquivDec.
Require Import Decidable.
Require Import Utils.
Require Import DataSystem.
Require Import cNNRC.
Require Import cNNRCShadow.
Require Import TcNNRC.
Section TcNNRCShadow.
Hint Constructors nnrc_core_type : qcert.
Context {m:basic_model}.
Lemma nnrc_core_type_remove_duplicate_env {τcenv} l v x l' x' l'' e τ:
nnrc_core_type τcenv (l ++ (v,x)::l' ++ (v,x')::l'') e τ <->
nnrc_core_type τcenv (l ++ (v,x)::l' ++ l'') e τ.
Proof.
apply nnrc_core_type_lookup_equiv_prop; trivial.
apply lookup_remove_duplicate.
Qed.
Lemma nnrc_core_type_remove_free_env {τcenv} l v x l' e τ :
~ In v (nnrc_free_vars e) ->
(nnrc_core_type τcenv (l ++ (v,x)::l') e τ <-> nnrc_core_type τcenv (l ++ l') e τ).
Proof.
split; revert l v x l' τ H;
induction e; simpl; inversion 2; subst; intuition; eauto 3 with qcert.
- constructor. erewrite <- lookup_remove_nin; eauto.
- apply nin_app_or in H. intuition. qeauto.
- apply nin_app_or in H. intuition.
econstructor; eauto.
destruct (equiv_dec v v0); unfold Equivalence.equiv in *; subst.
+ apply (nnrc_core_type_remove_duplicate_env nil v0 τ₁ l) in H7; eauto.
+ eapply (IHe2 ((v, τ₁) :: l)); eauto.
intro; elim H2; apply remove_in_neq; eauto.
- apply nin_app_or in H. intuition.
econstructor; eauto.
destruct (equiv_dec v v0); unfold Equivalence.equiv in *; subst.
+ apply (nnrc_core_type_remove_duplicate_env nil v0 τ₁ l) in H7; eauto.
+ eapply (IHe2 ((v, τ₁) :: l)); eauto.
intro; elim H2; apply remove_in_neq; eauto.
- apply nin_app_or in H; destruct H as [? HH]; apply nin_app_or in HH.
intuition. qeauto.
- apply nin_app_or in H. destruct H as [neq1 neq2].
apply nin_app_or in neq2. destruct neq2 as [neq2 neq3].
econstructor; eauto.
+ destruct (equiv_dec v v1); unfold Equivalence.equiv in *; subst.
* apply (nnrc_core_type_remove_duplicate_env nil v1 τl l) in H9; eauto.
* eapply (IHe2 ((v, τl) :: l)); eauto.
rewrite <- remove_in_neq in neq2; intuition.
+ destruct (equiv_dec v0 v1); unfold Equivalence.equiv in *; subst.
* apply (nnrc_core_type_remove_duplicate_env nil v1 τr l) in H10; eauto.
* eapply (IHe3 ((v0, τr) :: l)); eauto.
rewrite <- remove_in_neq in neq3; intuition.
- constructor. erewrite lookup_remove_nin; eauto.
- apply nin_app_or in H. intuition. qeauto.
- apply nin_app_or in H. intuition.
econstructor; eauto.
destruct (equiv_dec v v0); unfold Equivalence.equiv in *; subst.
+ apply (nnrc_core_type_remove_duplicate_env nil v0 τ₁ l); eauto.
+ eapply (IHe2 ((v, τ₁) :: l)); eauto.
intro; elim H2; apply remove_in_neq; eauto.
- apply nin_app_or in H. intuition.
econstructor; eauto.
destruct (equiv_dec v v0); unfold Equivalence.equiv in *; subst.
+ apply (nnrc_core_type_remove_duplicate_env nil v0 τ₁ l); eauto.
+ eapply (IHe2 ((v, τ₁) :: l)); eauto.
intro; elim H2; apply remove_in_neq; eauto.
- apply nin_app_or in H; destruct H as [? HH]; apply nin_app_or in HH.
intuition.
- apply nin_app_or in H. destruct H as [neq1 neq2].
apply nin_app_or in neq2; destruct neq2 as [neq2 neq3].
econstructor; eauto.
+ destruct (equiv_dec v v1); unfold Equivalence.equiv in *; subst.
* apply (nnrc_core_type_remove_duplicate_env nil v1 τl l); simpl; trivial.
* eapply (IHe2 ((v, τl) :: l)); eauto.
rewrite <- remove_in_neq in neq2; intuition.
+ destruct (equiv_dec v0 v1); unfold Equivalence.equiv in *; subst.
* apply (nnrc_core_type_remove_duplicate_env nil v1 τr l); simpl; trivial.
* eapply (IHe3 ((v0, τr) :: l)); eauto.
rewrite <- remove_in_neq in neq3; intuition.
Qed.
Lemma nnrc_core_type_remove_disjoint_env {τcenv} l1 l2 l3 e τ :
disjoint (domain l2) (nnrc_free_vars e) ->
(nnrc_core_type τcenv (l1 ++ l2 ++ l3) e τ <-> nnrc_core_type τcenv (l1 ++ l3) e τ).
Proof.
revert l1 l3.
induction l2; intros l1 l3 disj; simpl.
- tauto.
- simpl in disj.
apply disjoint_cons_inv1 in disj.
destruct disj as [disj nin].
destruct a; simpl in *.
rewrite nnrc_core_type_remove_free_env; trivial.
eauto.
Qed.
Lemma nnrc_core_type_remove_almost_free_env {τcenv} l v x l' e τ :
(In v (nnrc_free_vars e) -> In v (domain l)) ->
(nnrc_core_type τcenv (l ++ (v,x)::l') e τ <-> nnrc_core_type τcenv (l ++ l') e τ).
Proof.
intros Hinn.
destruct (in_dec string_dec v (nnrc_free_vars e)) as [inn|inn].
- apply Hinn in inn.
apply in_domain_in in inn.
destruct inn as [? inn].
destruct (in_split _ _ inn) as [? [? ?]]; subst.
repeat rewrite app_ass; simpl.
apply nnrc_core_type_remove_duplicate_env.
- apply nnrc_core_type_remove_free_env; trivial.
Qed.
Lemma nnrc_core_type_remove_almost_disjoint_env {τcenv} l1 l2 l3 e τ :
(forall x,
In x (domain l2) ->
In x (nnrc_free_vars e) -> In x (domain l1)) ->
(nnrc_core_type τcenv (l1 ++ l2 ++ l3) e τ <-> nnrc_core_type τcenv (l1 ++ l3) e τ).
Proof.
revert l1 l3.
induction l2; intros l1 l3 disj; simpl.
- tauto.
- simpl in disj.
destruct a; simpl in *.
rewrite nnrc_core_type_remove_almost_free_env; trivial.
+ eauto.
+ intuition.
Qed.
Lemma nnrc_core_type_swap_neq {τcenv} l1 v1 x1 v2 x2 l2 e τ :
v1 <> v2 ->
(nnrc_core_type τcenv (l1++(v1,x1)::(v2,x2)::l2) e τ <->
nnrc_core_type τcenv (l1++(v2,x2)::(v1,x1)::l2) e τ).
Proof.
intros.
apply nnrc_core_type_lookup_equiv_prop; trivial.
apply lookup_swap_neq; trivial.
Qed.
Lemma nnrc_core_type_cons_subst {τcenv} e Γ v τ₀ v' τ :
~ (In v' (nnrc_free_vars e)) ->
~ (In v' (nnrc_bound_vars e)) ->
(nnrc_core_type τcenv ((v',τ₀)::Γ) (nnrc_subst e v (NNRCVar v')) τ <->
nnrc_core_type τcenv ((v,τ₀)::Γ) e τ).
Proof.
split; revert Γ v τ₀ v' τ H H0;
induction e; simpl in *; unfold equiv_dec, string_eqdec;
trivial; intros Γ v₀ τ₀ v' τ nfree nbound.
- intuition.
constructor.
destruct (string_dec v v₀); simpl; subst; intuition; inversion H; subst; simpl in *; repeat dest_eqdec; intuition.
- intuition.
constructor.
destruct (string_dec v v₀); simpl; subst; intuition; inversion H; subst; simpl in *; repeat dest_eqdec; intuition.
- inversion 1; subst. qeauto.
- inversion 1; subst.
rewrite nin_app_or in nfree, nbound.
intuition; qeauto.
- inversion 1; subst. qeauto.
- inversion 1; subst.
rewrite nin_app_or in nfree. intuition.
apply nin_app_or in H3. intuition.
match_destr_in H; subst.
+ econstructor; eauto.
apply (nnrc_core_type_remove_duplicate_env nil v₀ τ₁ nil); simpl.
generalize (@nnrc_core_type_remove_free_env τcenv ((v₀,τ₁)::nil)); simpl; intros HH.
apply HH in H6; eauto.
intro; elim H1. apply remove_in_neq; eauto.
+ econstructor; eauto.
apply (nnrc_core_type_swap_neq nil); eauto; simpl.
eapply IHe2; eauto.
* intro; elim H1.
apply remove_in_neq; eauto.
* apply (nnrc_core_type_swap_neq nil); eauto; simpl.
- inversion 1; subst.
rewrite nin_app_or in nfree. intuition.
apply nin_app_or in H3. intuition.
match_destr_in H6; subst.
+ econstructor; eauto.
apply (nnrc_core_type_remove_duplicate_env nil v₀ τ₁ nil); simpl.
generalize (@nnrc_core_type_remove_free_env τcenv ((v₀,τ₁)::nil)); simpl; intros HH.
apply HH in H6; eauto.
intro; elim H1. apply remove_in_neq; eauto.
+ econstructor; eauto.
apply (nnrc_core_type_swap_neq nil); eauto; simpl.
eapply IHe2; eauto.
* intro; elim H1.
apply remove_in_neq; eauto.
* apply (nnrc_core_type_swap_neq nil); eauto; simpl.
- inversion 1; subst.
apply nin_app_or in nfree; destruct nfree as [? HH]; apply nin_app_or in HH.
apply nin_app_or in nbound; destruct nbound as [? HHH]; apply nin_app_or in HHH.
intuition; qeauto.
- intro HH; inversion HH; subst; clear HH.
apply not_or in nbound; destruct nbound as [nb1 nb2].
apply not_or in nb2; destruct nb2 as [nb2 nb3].
repeat rewrite nin_app_or in nb3, nfree.
rewrite <- (remove_in_neq _ _ v) in nfree by congruence.
rewrite <- (remove_in_neq _ _ v0) in nfree by congruence.
econstructor.
+ eapply IHe1; eauto 2; intuition.
+ match_destr_in H7; subst.
* generalize (@nnrc_core_type_remove_free_env τcenv ((v₀,τl)::nil)); simpl;
intros re1; rewrite re1 in H7 by intuition.
generalize (@nnrc_core_type_remove_duplicate_env τcenv nil v₀ τl nil); simpl;
intros re2; rewrite re2 by intuition.
trivial.
* apply (nnrc_core_type_swap_neq nil); eauto 2; simpl.
apply (nnrc_core_type_swap_neq nil) in H7; eauto 2; simpl in *.
eapply IHe2; eauto 2; intuition.
+ match_destr_in H8; subst.
* generalize (@nnrc_core_type_remove_free_env τcenv ((v₀,τr)::nil)); simpl;
intros re1; rewrite re1 in H8 by intuition.
generalize (@nnrc_core_type_remove_duplicate_env τcenv nil v₀ τr nil); simpl;
intros re2; rewrite re2 by intuition.
trivial.
* apply (nnrc_core_type_swap_neq nil); eauto 2; simpl.
apply (nnrc_core_type_swap_neq nil) in H8; eauto 2; simpl in *.
eapply IHe3; eauto 2; intuition.
- (* GroupBy Case: always fails for core? *)
intros.
inversion H.
- intuition.
destruct (string_dec v v₀); simpl; subst; intuition;
inversion H; subst; simpl in *; repeat dest_eqdec; intuition;
inversion H4; subst; constructor; simpl;
repeat dest_eqdec; intuition.
- intuition.
destruct (string_dec v v₀); simpl; subst; intuition;
inversion H; subst; simpl in *; repeat dest_eqdec; intuition;
inversion H4; subst; constructor; simpl;
repeat dest_eqdec; intuition.
- inversion 1; subst. qeauto.
- inversion 1; subst.
rewrite nin_app_or in nfree, nbound.
intuition; qeauto.
- inversion 1; subst. qeauto.
- inversion 1; subst.
rewrite nin_app_or in nfree. intuition.
apply nin_app_or in H3. intuition.
match_destr; subst.
+ econstructor; eauto.
apply (nnrc_core_type_remove_duplicate_env nil v₀ τ₁ nil) in H6;
simpl in H6.
generalize (@nnrc_core_type_remove_free_env τcenv ((v₀,τ₁)::nil)); simpl; intros HH.
apply HH; eauto.
intro; elim H1. apply remove_in_neq; eauto.
+ econstructor; eauto.
apply (nnrc_core_type_swap_neq nil); eauto; simpl.
eapply IHe2; eauto.
* intro; elim H1.
apply remove_in_neq; eauto.
* apply (nnrc_core_type_swap_neq nil); eauto; simpl.
- inversion 1; subst.
rewrite nin_app_or in nfree. intuition.
apply nin_app_or in H3. intuition.
match_destr; subst.
+ econstructor; eauto.
apply (nnrc_core_type_remove_duplicate_env nil v₀ τ₁ nil) in H6;
simpl in H6.
generalize (@nnrc_core_type_remove_free_env τcenv ((v₀,τ₁)::nil)); simpl; intros HH.
apply HH; eauto.
intro; elim H1. apply remove_in_neq; eauto.
+ econstructor; eauto.
apply (nnrc_core_type_swap_neq nil); eauto; simpl.
eapply IHe2; eauto.
* intro; elim H1.
apply remove_in_neq; eauto.
* apply (nnrc_core_type_swap_neq nil); eauto; simpl.
- inversion 1; subst.
apply nin_app_or in nfree; destruct nfree as [? HH]; apply nin_app_or in HH.
apply nin_app_or in nbound; destruct nbound as [? HHH]; apply nin_app_or in HHH.
intuition; eauto.
- apply not_or in nbound; destruct nbound as [nb1 nb2].
apply not_or in nb2; destruct nb2 as [nb2 nb3].
repeat rewrite nin_app_or in nb3, nfree.
rewrite <- (remove_in_neq _ _ v) in nfree by congruence.
rewrite <- (remove_in_neq _ _ v0) in nfree by congruence.
intro HH; inversion HH; clear HH; subst.
econstructor.
+ apply IHe1; eauto 2; intuition.
+ match_destr; subst.
* generalize (@nnrc_core_type_remove_duplicate_env τcenv nil v₀ τl nil); simpl;
intros re1; rewrite re1 in H7.
apply (nnrc_core_type_remove_free_env ((v₀,τl)::nil)); intuition.
* apply (nnrc_core_type_swap_neq nil); eauto; simpl.
apply IHe2; eauto 2; intuition.
apply (nnrc_core_type_swap_neq nil); eauto; simpl.
+ match_destr; subst.
* generalize (@nnrc_core_type_remove_duplicate_env τcenv nil v₀ τr nil); simpl;
intros re1; rewrite re1 in H8.
apply (nnrc_core_type_remove_free_env ((v₀,τr)::nil)); intuition.
* apply (nnrc_core_type_swap_neq nil); eauto; simpl.
apply IHe3; eauto 2; intuition.
apply (nnrc_core_type_swap_neq nil); eauto; simpl.
- (* GroupBy Case: always fails for core? *)
intros.
inversion H.
Qed.
Lemma nnrc_core_type_cons_subst_disjoint {τcenv} e e' Γ v τ₀ τ :
disjoint (nnrc_bound_vars e) (nnrc_free_vars e') ->
nnrc_core_type τcenv Γ e' τ₀ ->
nnrc_core_type τcenv ((v,τ₀)::Γ) e τ ->
nnrc_core_type τcenv Γ (nnrc_subst e v e') τ.
Proof.
intros disj typ'.
revert Γ e' v τ₀ τ disj typ'.
nnrc_cases (induction e) Case; simpl in *;
trivial; intros Γ v₀ τ₀ v' τ nfree nbound; simpl;
intros typ; inversion typ; clear typ; subst;
unfold equiv_dec in *; simpl in * .
- Case "NNRCGetConstant"%string.
qeauto.
- Case "NNRCVar"%string.
match_destr.
+ congruence.
+ qauto.
- Case "NNRCConst"%string.
econstructor; trivial.
- Case "NNRCBinop"%string.
apply disjoint_app_l in nfree.
destruct nfree.
econstructor; eauto 2.
- Case "NNRCUnop"%string.
econstructor; eauto.
- Case "NNRCLet"%string.
apply disjoint_cons_inv1 in nfree.
destruct nfree as [disj nin].
apply disjoint_app_l in disj.
destruct disj as [disj1 disj2].
econstructor; eauto 2.
match_destr.
+ red in e; subst.
generalize (@nnrc_core_type_remove_duplicate_env τcenv nil τ₀ τ₁ nil v' Γ);
simpl; intros re1; apply re1; eauto.
+ eapply IHe2; eauto 2.
* generalize (@nnrc_core_type_remove_free_env τcenv nil v τ₁ Γ v₀);
simpl; intros re1; apply re1; eauto.
* generalize (@nnrc_core_type_swap_neq τcenv nil τ₀ v' v τ₁ Γ e2 τ);
simpl; intros re1; apply re1; eauto.
- Case "NNRCFor"%string.
apply disjoint_cons_inv1 in nfree.
destruct nfree as [disj nin].
apply disjoint_app_l in disj.
destruct disj as [disj1 disj2].
econstructor; eauto 2.
match_destr.
+ red in e; subst.
generalize (@nnrc_core_type_remove_duplicate_env τcenv nil τ₀ τ₁ nil v' Γ);
simpl; intros re1; apply re1; eauto.
+ eapply IHe2; eauto 2.
* generalize (@nnrc_core_type_remove_free_env τcenv nil v τ₁ Γ v₀);
simpl; intros re1; apply re1; eauto.
* generalize (@nnrc_core_type_swap_neq τcenv nil τ₀ v' v τ₁ Γ e2 τ₂);
simpl; intros re1; apply re1; eauto.
- Case "NNRCIf"%string.
apply disjoint_app_l in nfree.
destruct nfree as [disj1 disj2].
apply disjoint_app_l in disj2.
destruct disj2 as [disj2 disj3].
econstructor; eauto 2.
- Case "NNRCEither"%string.
apply disjoint_cons_inv1 in nfree.
destruct nfree as [disj nin].
apply disjoint_cons_inv1 in disj.
destruct disj as [disj nin2].
apply disjoint_app_l in disj.
destruct disj as [disj1 disj2].
apply disjoint_app_l in disj2.
destruct disj2 as [disj2 disj3].
econstructor; eauto 2.
+ {
match_destr.
+ red in e; subst.
generalize (@nnrc_core_type_remove_duplicate_env τcenv nil τ₀ τl nil v' Γ);
simpl; intros re1; apply re1; eauto.
+ eapply IHe2; eauto 2.
* generalize (@nnrc_core_type_remove_free_env τcenv nil v τl Γ v₀);
simpl; intros re1; apply re1; eauto.
* generalize (@nnrc_core_type_swap_neq τcenv nil τ₀ v' v τl Γ e2 τ);
simpl; intros re1; apply re1; eauto.
}
+ {
match_destr.
+ red in e; subst.
generalize (@nnrc_core_type_remove_duplicate_env τcenv nil τ₀ τr nil v' Γ);
simpl; intros re1; apply re1; eauto.
+ eapply IHe3; eauto 2.
* generalize (@nnrc_core_type_remove_free_env τcenv nil v0 τr Γ v₀);
simpl; intros re1; apply re1; eauto.
* generalize (@nnrc_core_type_swap_neq τcenv nil τ₀ v' v0 τr Γ e3 τ);
simpl; intros re1; apply re1; eauto.
}
Qed.
Lemma nnrc_core_type_rename_pick_subst {τcenv} sep renamer avoid e Γ v τ₀ τ :
(nnrc_core_type τcenv
((nnrc_pick_name sep renamer avoid v e,τ₀)::Γ)
(nnrc_rename_lazy e v (nnrc_pick_name sep renamer avoid v e)) τ
<->
nnrc_core_type τcenv ((v,τ₀)::Γ) e τ).
Proof.
unfold nnrc_rename_lazy.
match_destr.
- rewrite <- e0.
tauto.
- rewrite nnrc_core_type_cons_subst; trivial.
+ tauto.
+ apply nnrc_pick_name_neq_nfree; trivial.
+ apply nnrc_pick_name_bound.
Qed.
Theorem nnrc_core_unshadow_type {τcenv} sep renamer avoid Γ n τ :
nnrc_core_type τcenv Γ n τ <-> nnrc_core_type τcenv Γ (unshadow sep renamer avoid n) τ.
Proof.
Hint Resolve really_fresh_from_free really_fresh_from_bound : qcert.
split; revert Γ τ; induction n; simpl in *; inversion 1; subst; qeauto; simpl.
- econstructor; [eauto|..].
apply nnrc_core_type_rename_pick_subst.
eauto.
- econstructor; [eauto|..].
apply nnrc_core_type_rename_pick_subst.
eauto.
- econstructor; [eauto|..].
apply nnrc_core_type_rename_pick_subst.
+ eauto.
+ apply nnrc_core_type_rename_pick_subst.
eauto.
- econstructor; [eauto|..].
apply nnrc_core_type_rename_pick_subst in H6.
eauto.
- econstructor; [eauto|..].
apply nnrc_core_type_rename_pick_subst in H6.
eauto.
- econstructor; [eauto|..].
+ apply nnrc_core_type_rename_pick_subst in H8.
eauto.
+ apply nnrc_core_type_rename_pick_subst in H9.
eauto.
Qed.
End TcNNRCShadow.
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:41:25 07/13/2009
// Design Name:
// Module Name: slign_mon
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
//
// Finalised 20/08/09. The same as testVA version with added data paths
// **************** ADC_BLOCK **********************************************
//
// This module deals with the io delays on the adc clock and the adc data+drdy
// The data and data ready come from the adc directly and are fed through idelay
// The data idelay has a nominal value set by calibration and passed to this module
//
// This module takes the input (logic) 357 clock and puts it through an odelay
// to clock the adc
//
// The phase of the ADC clock is changed by varying scan_delay. This is added to the adc
// clock delay and subtracted from the data delays to maintain the data phase wrt
// logic 357 clock
//
// Sending delay_trig high synchronous to 40MHz causes a change in data_offset_delay or
// scan_delay to be registered
//
// This module also implements the align_monitor module
// Works only when align_en is taken high
// This monitors the phase of the first drdy signal wrt logic 357, and if it drifts
// a correction is applied to the data idelays
//
// Saturated goes high if one of the delays tries to move beyond its limit
//
// Monitoring signals are exposed, along with a strobe delay_mod_changed
//
// Three ADCs are clocked by a single adc clock, so there are 3 data I/Os and
// 3 drdy inputs. align_ch_sel can be used to select which drdy to pass to the
// alignment monitor, but all data paths are given the same delay
module adc_block(
input clk357,
input clk40,
input rst,
input align_en,
input [1:0] align_ch_sel,
//input [12:0] ch1_data_in_del,
//input [12:0] ch2_data_in_del,
//input [12:0] ch3_data_in_del,
input [6:0] data_offset_delay,
input [5:0] scan_delay,
input delay_trig,
input IDDR_Q1,
input IDDR_Q2,
//output [12:0] ch1_data_out,
//output [12:0] ch2_data_out,
//output [12:0] ch3_data_out,
output saturated,
//output reg [5:0] adc_drdy_delay_out, //Monitoring
//output reg [5:0] adc_data_delay_out, //Monitoring
output [5:0] adc_drdy_delay, //Monitoring
output [5:0] adc_data_delay, //Monitoring
output [6:0] delay_modifier, //Monitoring
output reg monitor_strb, //Monitoring
//output reg [6:0] count1_out, //Monitoring
//output reg [6:0] count2_out, //Monitoring
//output reg [6:0] count3_out, //Monitoring
//output reg [5:0] adc_clk_delay_mon_out, //Monitoring
output [6:0] count1, //Monitoring
output [6:0] count2, //Monitoring
output [6:0] count3, //Monitoring
output [5:0] adc_clk_delay_mon, //Monitoring
output delay_calc_strb,
output adc_drdy_delay_ce,
output adc_clk_delay_ce,
output adc_data_delay_ce
);
//(* IOB = "TRUE" *) reg [12:0] ch1_data_in_reg, ch2_data_in_reg, ch3_data_in_reg;
//Pipeline stage
//reg [12:0] ch1_data_in_a, ch2_data_in_a, ch3_data_in_a;
reg align_en_a;
// ***** Register the delayed signals in the IOB registers and pipeline *****
always @(posedge clk357) begin
/*ch1_data_in_reg <= ch1_data_in_del;
ch2_data_in_reg <= ch2_data_in_del;
ch3_data_in_reg <= ch3_data_in_del;
ch1_data_in_a <= ch1_data_in_reg;
ch2_data_in_a <= ch2_data_in_reg;
ch3_data_in_a <= ch3_data_in_reg;*/
align_en_a <= align_en;
end
// ***** Assign the delayed, registered and pipelined signals to outputs *****
// Invert data MSB to convert from offset binary to 2's complement
/*assign ch1_data_out = {~ch1_data_in_a[12], ch1_data_in_a[11:0]};
assign ch2_data_out = {~ch2_data_in_a[12], ch2_data_in_a[11:0]};
assign ch3_data_out = {~ch3_data_in_a[12], ch3_data_in_a[11:0]};*/
//DON'T FOR NOW
// ***** Multiplex the DRDY signals *****
// sel = 0,1,2 => ch1,ch2,ch3
//wire drdy;
//assign drdy = (align_ch_sel == 0) ? ch1_drdy_out : ( (align_ch_sel == 1) ? ch2_drdy_out : ch3_drdy_out);
//assign drdy = ch1_drdy_out;
//The delay calculator takes one 40MHz cycle to register the result
//of its calculation. Register its strobe, and use it to trigger the
//delay incrementors after a cycle. Also accept the delay_trig
reg iodelay_cnt_trig;
always @(posedge clk40) iodelay_cnt_trig <= (delay_calc_strb | delay_trig);
//Do the same for the monitor strobe
wire monitor_strb_in;
//wire align_end;
//wire [6:0] count1, count2, count3;
//wire [5:0] adc_drdy_delay, adc_clk_delay_mon, adc_data_delay;
always @(posedge clk40) begin
monitor_strb <= monitor_strb_in;
// count1_out <= (align_end) ? count1 : count1_out;
// count2_out <= (align_end) ? count2 : count2_out;
// count3_out <= (align_end) ? count3 : count3_out;
// adc_drdy_delay_out <= (align_end) ? adc_drdy_delay : adc_drdy_delay_out;
// adc_clk_delay_mon_out <= (align_end) ? adc_clk_delay_mon : adc_clk_delay_mon_out;
// adc_data_delay_out <= (align_end) ? adc_data_delay : adc_data_delay_out;
end
// ***** Instantiate the drdy delay incrementor *****
//wire [5:0] adc_drdy_delay;
iodelay_incrementor drdy_idelay_inc(
.clk40(clk40),
.rst(delay_calc_strb | delay_trig), //This reset line goes high one cycle before the strb
.count_trig(iodelay_cnt_trig),
.spec_delay(adc_drdy_delay),
.inc_en(adc_drdy_delay_ce),
.actual_delay()
);
// ***** Instantiate the adc_clk odelay incrementor *****
wire [5:0] adc_clk_delay;
iodelay_incrementor adc_clk_delay_inc(
.clk40(clk40),
.rst(delay_calc_strb | delay_trig), //This reset line goes high one cycle before the strb
.count_trig(iodelay_cnt_trig),
.spec_delay(adc_clk_delay),
.inc_en(adc_clk_delay_ce),
.actual_delay(adc_clk_delay_mon)
);
//Instantiate the delay calculator
//wire [5:0] adc_data_delay;
//wire [6:0] delay_modifier;
delay_calc delay_calc1(
.clk40(clk40),
.rst(rst),
.data_offset_delay(data_offset_delay),
.delay_modifier(delay_modifier),
.scan_delay(scan_delay),
.strb(delay_calc_strb | delay_trig),
.adc_clock_delay(adc_clk_delay),
.adc_data_delay(adc_data_delay),
.adc_drdy_delay(adc_drdy_delay),
.saturated(saturated)
);
//Instantiate the alignment monitor
align_monitor align_mon1(
.clk357(clk357),
.clk40(clk40),
.rst(rst),
.align_en(align_en_a),
.Q1(IDDR_Q1),
.Q2(IDDR_Q2),
//.align_end(align_end),
.delay_modifier(delay_modifier),
.delay_mod_strb(delay_calc_strb),
.count1(count1),
.count2(count2),
.count3(count3),
.monitor_strb(monitor_strb_in)
);
// Output the delay modifier for monitoring
//assign delay_mod = delay_modifier;
// Output actual data delay for monitoring
//assign total_data_delay = adc_data_delay;
// Output drdy delay for monitoring
//assign total_drdy_delay = adc_drdy_delay;
// ***** Instantiate the data delay incrementor *****
iodelay_incrementor data_idelay_inc(
.clk40(clk40),
.rst(delay_calc_strb | delay_trig), //This reset line goes high one cycle before the strb
.count_trig(iodelay_cnt_trig),
.spec_delay(adc_data_delay),
.inc_en(adc_data_delay_ce),
.actual_delay()
);
endmodule
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 16.1 cbx_altiobuf_out 2016:10:24:15:04:16:SJ cbx_mgl 2016:10:24:15:05:03:SJ cbx_stratixiii 2016:10:24:15:04:16:SJ cbx_stratixv 2016:10:24:15:04:16:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Intel and sold by Intel or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module hps_sdram_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule //hps_sdram_p0_clock_pair_generator
//VALID FILE
|
// DelayWorker.v - DelayWorker with parmeterization
// Copyright (c) 2010,2011 Atomic Rules LLC - ALL RIGHTS RESERVED
module DelayWorker # (
parameter integer WSI_S0_DATAPATH_WIDTH = 32,
parameter integer WSI_M0_DATAPATH_WIDTH = 32,
parameter integer WORKER_CTRL_INIT = 1,
parameter integer HAS_DEBUG_LOGIC = 1 )
(
input wciS0_Clk,
input wciS0_MReset_n,
input [ 2:0] wciS0_MCmd,
input wciS0_MAddrSpace,
input [ 3:0] wciS0_MByteEn,
input [31:0] wciS0_MAddr,
input [31:0] wciS0_MData,
output [ 1:0] wciS0_SResp,
output [31:0] wciS0_SData,
output wciS0_SThreadBusy,
output [ 1:0] wciS0_SFlag,
input [ 1:0] wciS0_MFlag,
output [ 2:0] wsiM0_MCmd,
output wsiM0_MReqLast,
output wsiM0_MBurstPrecise,
output [11:0] wsiM0_MBurstLength,
output [WSI_M0_DATAPATH_WIDTH-1 :0] wsiM0_MData,
output [WSI_M0_DATAPATH_WIDTH/4-1:0] wsiM0_MByteEn,
output [ 7:0] wsiM0_MReqInfo,
input wsiM0_SThreadBusy,
output wsiM0_MReset_n,
input wsiM0_SReset_n,
input [ 2:0] wsiS0_MCmd,
input wsiS0_MReqLast,
input wsiS0_MBurstPrecise,
input [11:0] wsiS0_MBurstLength,
input [WSI_S0_DATAPATH_WIDTH-1 :0] wsiS0_MData,
input [WSI_S0_DATAPATH_WIDTH/4-1:0] wsiS0_MByteEn,
input [ 7:0] wsiS0_MReqInfo,
output wsiS0_SThreadBusy,
output wsiS0_SReset_n,
input wsiS0_MReset_n,
output [ 2:0] wmemiM0_MCmd,
output wmemiM0_MReqLast,
output [ 35:0] wmemiM0_MAddr,
output [ 11:0] wmemiM0_MBurstLength,
output wmemiM0_MDataValid,
output wmemiM0_MDataLast,
output [127:0] wmemiM0_MData,
output [ 15:0] wmemiM0_MDataByteEn,
input [ 1:0] wmemiM0_SResp,
input wmemiM0_SRespLast,
input [127:0] wmemiM0_SData,
input wmemiM0_SCmdAccept,
input wmemiM0_SDataAccept,
output wmemiM0_MReset_n
);
// Compile time check for expected parameters...
initial begin
if ( (WSI_M0_DATAPATH_WIDTH != 32) && (WSI_M0_DATAPATH_WIDTH != 64) && (WSI_M0_DATAPATH_WIDTH != 128) && (WSI_M0_DATAPATH_WIDTH != 256) ) begin
$display("Unsupported WSI_M0_DATAPATH width"); $finish; end
if ( (WSI_S0_DATAPATH_WIDTH != 32) && (WSI_S0_DATAPATH_WIDTH != 64) && (WSI_S0_DATAPATH_WIDTH != 128) && (WSI_S0_DATAPATH_WIDTH != 256) ) begin
$display("Unsupported WSI_S0_DATAPATH width"); $finish; end
if ( WSI_M0_DATAPATH_WIDTH != WSI_S0_DATAPATH_WIDTH ) begin
$display("Width Mismatch, WSI_M0 WSI_S0_ DATAPATH widths must match"); $finish; end
end
// Instance the correct variant...
generate
//genvar byteWidth;
//byteWidth = WMI_M0_DATAPATH_WIDTH/8;
case (WSI_M0_DATAPATH_WIDTH/8)
4:
mkDelayWorker4B #(
.dlyCtrlInit (WORKER_CTRL_INIT),
.hasDebugLogic (HAS_DEBUG_LOGIC))
DelayWorker4B_i (
.wciS0_Clk (wciS0_Clk),
.wciS0_MReset_n (wciS0_MReset_n),
.wciS0_MAddr (wciS0_MAddr),
.wciS0_MAddrSpace (wciS0_MAddrSpace),
.wciS0_MByteEn (wciS0_MByteEn),
.wciS0_MCmd (wciS0_MCmd),
.wciS0_MData (wciS0_MData),
.wciS0_MFlag (wciS0_MFlag),
.wciS0_SResp (wciS0_SResp),
.wciS0_SData (wciS0_SData),
.wciS0_SThreadBusy (wciS0_SThreadBusy),
.wciS0_SFlag (wciS0_SFlag),
.wsiS0_MBurstLength (wsiS0_MBurstLength),
.wsiS0_MByteEn (wsiS0_MByteEn),
.wsiS0_MCmd (wsiS0_MCmd),
.wsiS0_MData (wsiS0_MData),
.wsiS0_MReqInfo (wsiS0_MReqInfo),
.wsiS0_MReqLast (wsiS0_MReqLast),
.wsiS0_MBurstPrecise (wsiS0_MBurstPrecise),
.wsiS0_MReset_n (wsiS0_MReset_n),
.wsiS0_SThreadBusy (wsiS0_SThreadBusy),
.wsiS0_SReset_n (wsiS0_SReset_n),
.wsiM0_SThreadBusy (wsiM0_SThreadBusy),
.wsiM0_SReset_n (wsiM0_SReset_n),
.wsiM0_MCmd (wsiM0_MCmd),
.wsiM0_MReqLast (wsiM0_MReqLast),
.wsiM0_MBurstPrecise (wsiM0_MBurstPrecise),
.wsiM0_MBurstLength (wsiM0_MBurstLength),
.wsiM0_MData (wsiM0_MData),
.wsiM0_MByteEn (wsiM0_MByteEn),
.wsiM0_MReqInfo (wsiM0_MReqInfo),
.wsiM0_MReset_n (wsiM0_MReset_n),
.wmemiM0_MCmd (wmemiM0_MCmd),
.wmemiM0_MReqLast (wmemiM0_MReqLast),
.wmemiM0_MAddr (wmemiM0_MAddr),
.wmemiM0_MBurstLength (wmemiM0_MBurstLength),
.wmemiM0_MDataValid (wmemiM0_MDataValid),
.wmemiM0_MDataLast (wmemiM0_MDataLast),
.wmemiM0_MData (wmemiM0_MData),
.wmemiM0_MDataByteEn (wmemiM0_MDataByteEn),
.wmemiM0_SResp (wmemiM0_SResp),
.wmemiM0_SRespLast (wmemiM0_SRespLast),
.wmemiM0_SData (wmemiM0_SData),
.wmemiM0_SCmdAccept (wmemiM0_SCmdAccept),
.wmemiM0_SDataAccept (wmemiM0_SDataAccept),
.wmemiM0_MReset_n (wmemiM0_MReset_n)
);
8:
mkDelayWorker8B #(
.dlyCtrlInit (WORKER_CTRL_INIT),
.hasDebugLogic (HAS_DEBUG_LOGIC))
DelayWorker8B_i (
.wciS0_Clk (wciS0_Clk),
.wciS0_MReset_n (wciS0_MReset_n),
.wciS0_MAddr (wciS0_MAddr),
.wciS0_MAddrSpace (wciS0_MAddrSpace),
.wciS0_MByteEn (wciS0_MByteEn),
.wciS0_MCmd (wciS0_MCmd),
.wciS0_MData (wciS0_MData),
.wciS0_MFlag (wciS0_MFlag),
.wciS0_SResp (wciS0_SResp),
.wciS0_SData (wciS0_SData),
.wciS0_SThreadBusy (wciS0_SThreadBusy),
.wciS0_SFlag (wciS0_SFlag),
.wsiS0_MBurstLength (wsiS0_MBurstLength),
.wsiS0_MByteEn (wsiS0_MByteEn),
.wsiS0_MCmd (wsiS0_MCmd),
.wsiS0_MData (wsiS0_MData),
.wsiS0_MReqInfo (wsiS0_MReqInfo),
.wsiS0_MReqLast (wsiS0_MReqLast),
.wsiS0_MBurstPrecise (wsiS0_MBurstPrecise),
.wsiS0_MReset_n (wsiS0_MReset_n),
.wsiS0_SThreadBusy (wsiS0_SThreadBusy),
.wsiS0_SReset_n (wsiS0_SReset_n),
.wsiM0_SThreadBusy (wsiM0_SThreadBusy),
.wsiM0_SReset_n (wsiM0_SReset_n),
.wsiM0_MCmd (wsiM0_MCmd),
.wsiM0_MReqLast (wsiM0_MReqLast),
.wsiM0_MBurstPrecise (wsiM0_MBurstPrecise),
.wsiM0_MBurstLength (wsiM0_MBurstLength),
.wsiM0_MData (wsiM0_MData),
.wsiM0_MByteEn (wsiM0_MByteEn),
.wsiM0_MReqInfo (wsiM0_MReqInfo),
.wsiM0_MReset_n (wsiM0_MReset_n),
.wmemiM0_MCmd (wmemiM0_MCmd),
.wmemiM0_MReqLast (wmemiM0_MReqLast),
.wmemiM0_MAddr (wmemiM0_MAddr),
.wmemiM0_MBurstLength (wmemiM0_MBurstLength),
.wmemiM0_MDataValid (wmemiM0_MDataValid),
.wmemiM0_MDataLast (wmemiM0_MDataLast),
.wmemiM0_MData (wmemiM0_MData),
.wmemiM0_MDataByteEn (wmemiM0_MDataByteEn),
.wmemiM0_SResp (wmemiM0_SResp),
.wmemiM0_SRespLast (wmemiM0_SRespLast),
.wmemiM0_SData (wmemiM0_SData),
.wmemiM0_SCmdAccept (wmemiM0_SCmdAccept),
.wmemiM0_SDataAccept (wmemiM0_SDataAccept),
.wmemiM0_MReset_n (wmemiM0_MReset_n)
);
16:
mkDelayWorker16B #(
.dlyCtrlInit (WORKER_CTRL_INIT),
.hasDebugLogic (HAS_DEBUG_LOGIC))
DelayWorker16B_i (
.wciS0_Clk (wciS0_Clk),
.wciS0_MReset_n (wciS0_MReset_n),
.wciS0_MAddr (wciS0_MAddr),
.wciS0_MAddrSpace (wciS0_MAddrSpace),
.wciS0_MByteEn (wciS0_MByteEn),
.wciS0_MCmd (wciS0_MCmd),
.wciS0_MData (wciS0_MData),
.wciS0_MFlag (wciS0_MFlag),
.wciS0_SResp (wciS0_SResp),
.wciS0_SData (wciS0_SData),
.wciS0_SThreadBusy (wciS0_SThreadBusy),
.wciS0_SFlag (wciS0_SFlag),
.wsiS0_MBurstLength (wsiS0_MBurstLength),
.wsiS0_MByteEn (wsiS0_MByteEn),
.wsiS0_MCmd (wsiS0_MCmd),
.wsiS0_MData (wsiS0_MData),
.wsiS0_MReqInfo (wsiS0_MReqInfo),
.wsiS0_MReqLast (wsiS0_MReqLast),
.wsiS0_MBurstPrecise (wsiS0_MBurstPrecise),
.wsiS0_MReset_n (wsiS0_MReset_n),
.wsiS0_SThreadBusy (wsiS0_SThreadBusy),
.wsiS0_SReset_n (wsiS0_SReset_n),
.wsiM0_SThreadBusy (wsiM0_SThreadBusy),
.wsiM0_SReset_n (wsiM0_SReset_n),
.wsiM0_MCmd (wsiM0_MCmd),
.wsiM0_MReqLast (wsiM0_MReqLast),
.wsiM0_MBurstPrecise (wsiM0_MBurstPrecise),
.wsiM0_MBurstLength (wsiM0_MBurstLength),
.wsiM0_MData (wsiM0_MData),
.wsiM0_MByteEn (wsiM0_MByteEn),
.wsiM0_MReqInfo (wsiM0_MReqInfo),
.wsiM0_MReset_n (wsiM0_MReset_n),
.wmemiM0_MCmd (wmemiM0_MCmd),
.wmemiM0_MReqLast (wmemiM0_MReqLast),
.wmemiM0_MAddr (wmemiM0_MAddr),
.wmemiM0_MBurstLength (wmemiM0_MBurstLength),
.wmemiM0_MDataValid (wmemiM0_MDataValid),
.wmemiM0_MDataLast (wmemiM0_MDataLast),
.wmemiM0_MData (wmemiM0_MData),
.wmemiM0_MDataByteEn (wmemiM0_MDataByteEn),
.wmemiM0_SResp (wmemiM0_SResp),
.wmemiM0_SRespLast (wmemiM0_SRespLast),
.wmemiM0_SData (wmemiM0_SData),
.wmemiM0_SCmdAccept (wmemiM0_SCmdAccept),
.wmemiM0_SDataAccept (wmemiM0_SDataAccept),
.wmemiM0_MReset_n (wmemiM0_MReset_n)
);
32:
mkDelayWorker32B #(
.dlyCtrlInit (WORKER_CTRL_INIT),
.hasDebugLogic (HAS_DEBUG_LOGIC))
DelayWorker32B_i (
.wciS0_Clk (wciS0_Clk),
.wciS0_MReset_n (wciS0_MReset_n),
.wciS0_MAddr (wciS0_MAddr),
.wciS0_MAddrSpace (wciS0_MAddrSpace),
.wciS0_MByteEn (wciS0_MByteEn),
.wciS0_MCmd (wciS0_MCmd),
.wciS0_MData (wciS0_MData),
.wciS0_MFlag (wciS0_MFlag),
.wciS0_SResp (wciS0_SResp),
.wciS0_SData (wciS0_SData),
.wciS0_SThreadBusy (wciS0_SThreadBusy),
.wciS0_SFlag (wciS0_SFlag),
.wsiS0_MBurstLength (wsiS0_MBurstLength),
.wsiS0_MByteEn (wsiS0_MByteEn),
.wsiS0_MCmd (wsiS0_MCmd),
.wsiS0_MData (wsiS0_MData),
.wsiS0_MReqInfo (wsiS0_MReqInfo),
.wsiS0_MReqLast (wsiS0_MReqLast),
.wsiS0_MBurstPrecise (wsiS0_MBurstPrecise),
.wsiS0_MReset_n (wsiS0_MReset_n),
.wsiS0_SThreadBusy (wsiS0_SThreadBusy),
.wsiS0_SReset_n (wsiS0_SReset_n),
.wsiM0_SThreadBusy (wsiM0_SThreadBusy),
.wsiM0_SReset_n (wsiM0_SReset_n),
.wsiM0_MCmd (wsiM0_MCmd),
.wsiM0_MReqLast (wsiM0_MReqLast),
.wsiM0_MBurstPrecise (wsiM0_MBurstPrecise),
.wsiM0_MBurstLength (wsiM0_MBurstLength),
.wsiM0_MData (wsiM0_MData),
.wsiM0_MByteEn (wsiM0_MByteEn),
.wsiM0_MReqInfo (wsiM0_MReqInfo),
.wsiM0_MReset_n (wsiM0_MReset_n),
.wmemiM0_MCmd (wmemiM0_MCmd),
.wmemiM0_MReqLast (wmemiM0_MReqLast),
.wmemiM0_MAddr (wmemiM0_MAddr),
.wmemiM0_MBurstLength (wmemiM0_MBurstLength),
.wmemiM0_MDataValid (wmemiM0_MDataValid),
.wmemiM0_MDataLast (wmemiM0_MDataLast),
.wmemiM0_MData (wmemiM0_MData),
.wmemiM0_MDataByteEn (wmemiM0_MDataByteEn),
.wmemiM0_SResp (wmemiM0_SResp),
.wmemiM0_SRespLast (wmemiM0_SRespLast),
.wmemiM0_SData (wmemiM0_SData),
.wmemiM0_SCmdAccept (wmemiM0_SCmdAccept),
.wmemiM0_SDataAccept (wmemiM0_SDataAccept),
.wmemiM0_MReset_n (wmemiM0_MReset_n)
);
//default: begin $display("Illegal case arm"); $finish; end
endcase
endgenerate
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="HLS_accel,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.690000,HLS_SYN_LAT=924676,HLS_SYN_TPT=none,HLS_SYN_MEM=6,HLS_SYN_DSP=19,HLS_SYN_FF=3165,HLS_SYN_LUT=5679}" *)
module HLS_accel (
s_axi_CONTROL_BUS_AWVALID,
s_axi_CONTROL_BUS_AWREADY,
s_axi_CONTROL_BUS_AWADDR,
s_axi_CONTROL_BUS_WVALID,
s_axi_CONTROL_BUS_WREADY,
s_axi_CONTROL_BUS_WDATA,
s_axi_CONTROL_BUS_WSTRB,
s_axi_CONTROL_BUS_ARVALID,
s_axi_CONTROL_BUS_ARREADY,
s_axi_CONTROL_BUS_ARADDR,
s_axi_CONTROL_BUS_RVALID,
s_axi_CONTROL_BUS_RREADY,
s_axi_CONTROL_BUS_RDATA,
s_axi_CONTROL_BUS_RRESP,
s_axi_CONTROL_BUS_BVALID,
s_axi_CONTROL_BUS_BREADY,
s_axi_CONTROL_BUS_BRESP,
ap_clk,
ap_rst_n,
INPUT_STREAM_TDATA,
INPUT_STREAM_TVALID,
INPUT_STREAM_TREADY,
INPUT_STREAM_TKEEP,
INPUT_STREAM_TSTRB,
INPUT_STREAM_TUSER,
INPUT_STREAM_TLAST,
INPUT_STREAM_TID,
INPUT_STREAM_TDEST,
OUTPUT_STREAM_TDATA,
OUTPUT_STREAM_TVALID,
OUTPUT_STREAM_TREADY,
OUTPUT_STREAM_TKEEP,
OUTPUT_STREAM_TSTRB,
OUTPUT_STREAM_TUSER,
OUTPUT_STREAM_TLAST,
OUTPUT_STREAM_TID,
OUTPUT_STREAM_TDEST,
interrupt
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 95'b1;
parameter ap_ST_st2_fsm_1 = 95'b10;
parameter ap_ST_st3_fsm_2 = 95'b100;
parameter ap_ST_st4_fsm_3 = 95'b1000;
parameter ap_ST_st5_fsm_4 = 95'b10000;
parameter ap_ST_st6_fsm_5 = 95'b100000;
parameter ap_ST_st7_fsm_6 = 95'b1000000;
parameter ap_ST_st8_fsm_7 = 95'b10000000;
parameter ap_ST_st9_fsm_8 = 95'b100000000;
parameter ap_ST_st10_fsm_9 = 95'b1000000000;
parameter ap_ST_st11_fsm_10 = 95'b10000000000;
parameter ap_ST_st12_fsm_11 = 95'b100000000000;
parameter ap_ST_st13_fsm_12 = 95'b1000000000000;
parameter ap_ST_st14_fsm_13 = 95'b10000000000000;
parameter ap_ST_st15_fsm_14 = 95'b100000000000000;
parameter ap_ST_st16_fsm_15 = 95'b1000000000000000;
parameter ap_ST_st17_fsm_16 = 95'b10000000000000000;
parameter ap_ST_st18_fsm_17 = 95'b100000000000000000;
parameter ap_ST_st19_fsm_18 = 95'b1000000000000000000;
parameter ap_ST_st20_fsm_19 = 95'b10000000000000000000;
parameter ap_ST_st21_fsm_20 = 95'b100000000000000000000;
parameter ap_ST_st22_fsm_21 = 95'b1000000000000000000000;
parameter ap_ST_st23_fsm_22 = 95'b10000000000000000000000;
parameter ap_ST_st24_fsm_23 = 95'b100000000000000000000000;
parameter ap_ST_st25_fsm_24 = 95'b1000000000000000000000000;
parameter ap_ST_st26_fsm_25 = 95'b10000000000000000000000000;
parameter ap_ST_st27_fsm_26 = 95'b100000000000000000000000000;
parameter ap_ST_st28_fsm_27 = 95'b1000000000000000000000000000;
parameter ap_ST_st29_fsm_28 = 95'b10000000000000000000000000000;
parameter ap_ST_st30_fsm_29 = 95'b100000000000000000000000000000;
parameter ap_ST_st31_fsm_30 = 95'b1000000000000000000000000000000;
parameter ap_ST_st32_fsm_31 = 95'b10000000000000000000000000000000;
parameter ap_ST_st33_fsm_32 = 95'b100000000000000000000000000000000;
parameter ap_ST_st34_fsm_33 = 95'b1000000000000000000000000000000000;
parameter ap_ST_st35_fsm_34 = 95'b10000000000000000000000000000000000;
parameter ap_ST_st36_fsm_35 = 95'b100000000000000000000000000000000000;
parameter ap_ST_st37_fsm_36 = 95'b1000000000000000000000000000000000000;
parameter ap_ST_st38_fsm_37 = 95'b10000000000000000000000000000000000000;
parameter ap_ST_st39_fsm_38 = 95'b100000000000000000000000000000000000000;
parameter ap_ST_st40_fsm_39 = 95'b1000000000000000000000000000000000000000;
parameter ap_ST_st41_fsm_40 = 95'b10000000000000000000000000000000000000000;
parameter ap_ST_st42_fsm_41 = 95'b100000000000000000000000000000000000000000;
parameter ap_ST_st43_fsm_42 = 95'b1000000000000000000000000000000000000000000;
parameter ap_ST_st44_fsm_43 = 95'b10000000000000000000000000000000000000000000;
parameter ap_ST_st45_fsm_44 = 95'b100000000000000000000000000000000000000000000;
parameter ap_ST_st46_fsm_45 = 95'b1000000000000000000000000000000000000000000000;
parameter ap_ST_st47_fsm_46 = 95'b10000000000000000000000000000000000000000000000;
parameter ap_ST_st48_fsm_47 = 95'b100000000000000000000000000000000000000000000000;
parameter ap_ST_st49_fsm_48 = 95'b1000000000000000000000000000000000000000000000000;
parameter ap_ST_st50_fsm_49 = 95'b10000000000000000000000000000000000000000000000000;
parameter ap_ST_st51_fsm_50 = 95'b100000000000000000000000000000000000000000000000000;
parameter ap_ST_st52_fsm_51 = 95'b1000000000000000000000000000000000000000000000000000;
parameter ap_ST_st53_fsm_52 = 95'b10000000000000000000000000000000000000000000000000000;
parameter ap_ST_st54_fsm_53 = 95'b100000000000000000000000000000000000000000000000000000;
parameter ap_ST_st55_fsm_54 = 95'b1000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st56_fsm_55 = 95'b10000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st57_fsm_56 = 95'b100000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st58_fsm_57 = 95'b1000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st59_fsm_58 = 95'b10000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st60_fsm_59 = 95'b100000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st61_fsm_60 = 95'b1000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st62_fsm_61 = 95'b10000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st63_fsm_62 = 95'b100000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st64_fsm_63 = 95'b1000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st65_fsm_64 = 95'b10000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st66_fsm_65 = 95'b100000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st67_fsm_66 = 95'b1000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st68_fsm_67 = 95'b10000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st69_fsm_68 = 95'b100000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st70_fsm_69 = 95'b1000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st71_fsm_70 = 95'b10000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st72_fsm_71 = 95'b100000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st73_fsm_72 = 95'b1000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st74_fsm_73 = 95'b10000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st75_fsm_74 = 95'b100000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st76_fsm_75 = 95'b1000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st77_fsm_76 = 95'b10000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st78_fsm_77 = 95'b100000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st79_fsm_78 = 95'b1000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st80_fsm_79 = 95'b10000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st81_fsm_80 = 95'b100000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st82_fsm_81 = 95'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st83_fsm_82 = 95'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st84_fsm_83 = 95'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st85_fsm_84 = 95'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st86_fsm_85 = 95'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st87_fsm_86 = 95'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st88_fsm_87 = 95'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st89_fsm_88 = 95'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st90_fsm_89 = 95'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st91_fsm_90 = 95'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st92_fsm_91 = 95'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st93_fsm_92 = 95'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_pp3_stg0_fsm_93 = 95'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st96_fsm_94 = 95'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter C_S_AXI_CONTROL_BUS_DATA_WIDTH = 32;
parameter ap_const_int64_8 = 8;
parameter C_S_AXI_CONTROL_BUS_ADDR_WIDTH = 5;
parameter C_DATA_WIDTH = 32;
parameter ap_const_lv32_5 = 32'b101;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_18 = 32'b11000;
parameter ap_const_lv32_29 = 32'b101001;
parameter ap_const_lv32_35 = 32'b110101;
parameter ap_const_lv32_4F = 32'b1001111;
parameter ap_const_lv32_9 = 32'b1001;
parameter ap_const_lv32_B = 32'b1011;
parameter ap_const_lv32_C = 32'b1100;
parameter ap_const_lv32_D = 32'b1101;
parameter ap_const_lv32_E = 32'b1110;
parameter ap_const_lv32_55 = 32'b1010101;
parameter ap_const_lv32_49 = 32'b1001001;
parameter ap_const_lv32_4E = 32'b1001110;
parameter ap_const_lv32_F = 32'b1111;
parameter ap_const_lv32_17 = 32'b10111;
parameter ap_const_lv32_28 = 32'b101000;
parameter ap_const_lv32_34 = 32'b110100;
parameter ap_const_lv32_40 = 32'b1000000;
parameter ap_const_lv32_11 = 32'b10001;
parameter ap_const_lv32_1D = 32'b11101;
parameter ap_const_lv32_2E = 32'b101110;
parameter ap_const_lv32_3A = 32'b111010;
parameter ap_const_lv32_5A = 32'b1011010;
parameter ap_const_lv32_3B = 32'b111011;
parameter ap_const_lv32_5B = 32'b1011011;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv32_4 = 32'b100;
parameter ap_const_lv32_6 = 32'b110;
parameter ap_const_lv32_7 = 32'b111;
parameter ap_const_lv32_8 = 32'b1000;
parameter ap_const_lv32_A = 32'b1010;
parameter ap_const_lv32_10 = 32'b10000;
parameter ap_const_lv32_12 = 32'b10010;
parameter ap_const_lv32_13 = 32'b10011;
parameter ap_const_lv32_14 = 32'b10100;
parameter ap_const_lv32_1E = 32'b11110;
parameter ap_const_lv32_1F = 32'b11111;
parameter ap_const_lv32_23 = 32'b100011;
parameter ap_const_lv32_24 = 32'b100100;
parameter ap_const_lv32_2F = 32'b101111;
parameter ap_const_lv32_30 = 32'b110000;
parameter ap_const_lv32_44 = 32'b1000100;
parameter ap_const_lv32_5C = 32'b1011100;
parameter ap_const_lv32_5D = 32'b1011101;
parameter ap_const_lv11_0 = 11'b00000000000;
parameter ap_const_lv6_0 = 6'b000000;
parameter ap_const_lv4_1 = 4'b1;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv12_0 = 12'b000000000000;
parameter ap_const_lv14_0 = 14'b00000000000000;
parameter ap_const_lv4_F = 4'b1111;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv32_3F800000 = 32'b111111100000000000000000000000;
parameter ap_const_lv32_3C = 32'b111100;
parameter ap_const_lv32_45 = 32'b1000101;
parameter ap_const_lv32_4A = 32'b1001010;
parameter ap_const_lv32_41200000 = 32'b1000001001000000000000000000000;
parameter ap_const_lv32_41 = 32'b1000001;
parameter ap_const_lv32_40E00000 = 32'b1000000111000000000000000000000;
parameter ap_const_lv32_40800000 = 32'b1000000100000000000000000000000;
parameter ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv32_19 = 32'b11001;
parameter ap_const_lv32_2A = 32'b101010;
parameter ap_const_lv32_36 = 32'b110110;
parameter ap_const_lv32_56 = 32'b1010110;
parameter ap_const_lv64_3FE6A09EDBF8B9BB = 64'b11111111100110101000001001111011011011111110001011100110111011;
parameter ap_const_lv64_3F847AE147AE147B = 64'b11111110000100011110101110000101000111101011100001010001111011;
parameter ap_const_lv32_50 = 32'b1010000;
parameter ap_const_lv11_400 = 11'b10000000000;
parameter ap_const_lv11_1 = 11'b1;
parameter ap_const_lv6_20 = 6'b100000;
parameter ap_const_lv6_1 = 6'b1;
parameter ap_const_lv6_3F = 6'b111111;
parameter ap_const_lv4_9 = 4'b1001;
parameter ap_const_lv8_FF = 8'b11111111;
parameter ap_const_lv23_0 = 23'b00000000000000000000000;
parameter ap_const_lv32_C2C80000 = 32'b11000010110010000000000000000000;
parameter ap_const_lv32_42C80000 = 32'b1000010110010000000000000000000;
parameter ap_const_lv14_1 = 14'b1;
parameter ap_const_lv12_1 = 12'b1;
parameter ap_const_lv12_400 = 12'b10000000000;
parameter ap_const_lv14_27FF = 14'b10011111111111;
parameter ap_const_lv10_3FF = 10'b1111111111;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv2_1 = 2'b1;
parameter ap_const_lv5_2 = 5'b10;
parameter ap_const_lv5_1 = 5'b1;
parameter ap_const_lv32_5E = 32'b1011110;
parameter ap_true = 1'b1;
parameter C_S_AXI_CONTROL_BUS_WSTRB_WIDTH = (C_S_AXI_CONTROL_BUS_DATA_WIDTH / ap_const_int64_8);
parameter C_WSTRB_WIDTH = (C_DATA_WIDTH / ap_const_int64_8);
input s_axi_CONTROL_BUS_AWVALID;
output s_axi_CONTROL_BUS_AWREADY;
input [C_S_AXI_CONTROL_BUS_ADDR_WIDTH - 1 : 0] s_axi_CONTROL_BUS_AWADDR;
input s_axi_CONTROL_BUS_WVALID;
output s_axi_CONTROL_BUS_WREADY;
input [C_S_AXI_CONTROL_BUS_DATA_WIDTH - 1 : 0] s_axi_CONTROL_BUS_WDATA;
input [C_S_AXI_CONTROL_BUS_WSTRB_WIDTH - 1 : 0] s_axi_CONTROL_BUS_WSTRB;
input s_axi_CONTROL_BUS_ARVALID;
output s_axi_CONTROL_BUS_ARREADY;
input [C_S_AXI_CONTROL_BUS_ADDR_WIDTH - 1 : 0] s_axi_CONTROL_BUS_ARADDR;
output s_axi_CONTROL_BUS_RVALID;
input s_axi_CONTROL_BUS_RREADY;
output [C_S_AXI_CONTROL_BUS_DATA_WIDTH - 1 : 0] s_axi_CONTROL_BUS_RDATA;
output [1:0] s_axi_CONTROL_BUS_RRESP;
output s_axi_CONTROL_BUS_BVALID;
input s_axi_CONTROL_BUS_BREADY;
output [1:0] s_axi_CONTROL_BUS_BRESP;
input ap_clk;
input ap_rst_n;
input [31:0] INPUT_STREAM_TDATA;
input INPUT_STREAM_TVALID;
output INPUT_STREAM_TREADY;
input [3:0] INPUT_STREAM_TKEEP;
input [3:0] INPUT_STREAM_TSTRB;
input [3:0] INPUT_STREAM_TUSER;
input [0:0] INPUT_STREAM_TLAST;
input [4:0] INPUT_STREAM_TID;
input [4:0] INPUT_STREAM_TDEST;
output [31:0] OUTPUT_STREAM_TDATA;
output OUTPUT_STREAM_TVALID;
input OUTPUT_STREAM_TREADY;
output [3:0] OUTPUT_STREAM_TKEEP;
output [3:0] OUTPUT_STREAM_TSTRB;
output [3:0] OUTPUT_STREAM_TUSER;
output [0:0] OUTPUT_STREAM_TLAST;
output [4:0] OUTPUT_STREAM_TID;
output [4:0] OUTPUT_STREAM_TDEST;
output interrupt;
reg INPUT_STREAM_TREADY;
reg OUTPUT_STREAM_TVALID;
reg ap_rst_n_inv;
wire ap_start;
reg ap_done;
reg ap_idle;
(* fsm_encoding = "none" *) reg [94:0] ap_CS_fsm = 95'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_136;
reg ap_ready;
wire HLS_accel_CONTROL_BUS_s_axi_U_ap_dummy_ce;
reg [10:0] indvar_flatten3_reg_486;
reg [5:0] i4_0_i_reg_497;
reg [5:0] j5_0_i_reg_508;
wire [63:0] grp_fu_535_p1;
reg [63:0] reg_562;
reg ap_sig_cseq_ST_st6_fsm_5;
reg ap_sig_bdd_187;
reg [0:0] tmp_11_reg_1778;
reg ap_sig_cseq_ST_st25_fsm_24;
reg ap_sig_bdd_198;
reg [0:0] tmp_23_reg_1793;
reg ap_sig_cseq_ST_st42_fsm_41;
reg ap_sig_bdd_209;
reg [0:0] tmp_52_reg_1810;
reg ap_sig_cseq_ST_st54_fsm_53;
reg ap_sig_bdd_220;
reg ap_sig_cseq_ST_st80_fsm_79;
reg ap_sig_bdd_228;
reg [0:0] tmp_32_reg_1995;
reg [63:0] reg_568;
reg ap_sig_cseq_ST_st10_fsm_9;
reg ap_sig_bdd_243;
wire [0:0] tmp_32_fu_1013_p2;
wire [63:0] grp_fu_552_p2;
reg [63:0] reg_573;
reg ap_sig_cseq_ST_st12_fsm_11;
reg ap_sig_bdd_258;
reg ap_sig_cseq_ST_st13_fsm_12;
reg ap_sig_bdd_266;
reg ap_sig_cseq_ST_st14_fsm_13;
reg ap_sig_bdd_275;
reg ap_sig_cseq_ST_st15_fsm_14;
reg ap_sig_bdd_284;
reg ap_sig_cseq_ST_st86_fsm_85;
reg ap_sig_bdd_292;
wire [31:0] grp_fu_520_p2;
reg [31:0] reg_578;
reg ap_sig_cseq_ST_st74_fsm_73;
reg ap_sig_bdd_305;
reg ap_sig_cseq_ST_st79_fsm_78;
reg ap_sig_bdd_313;
reg [31:0] reg_585;
reg ap_sig_cseq_ST_st16_fsm_15;
reg ap_sig_bdd_322;
reg ap_sig_cseq_ST_st24_fsm_23;
reg ap_sig_bdd_329;
reg ap_sig_cseq_ST_st41_fsm_40;
reg ap_sig_bdd_338;
reg ap_sig_cseq_ST_st53_fsm_52;
reg ap_sig_bdd_346;
reg ap_sig_cseq_ST_st65_fsm_64;
reg ap_sig_bdd_354;
wire [63:0] grp_fu_547_p2;
reg [63:0] reg_592;
reg ap_sig_cseq_ST_st18_fsm_17;
reg ap_sig_bdd_364;
reg ap_sig_cseq_ST_st30_fsm_29;
reg ap_sig_bdd_372;
reg ap_sig_cseq_ST_st47_fsm_46;
reg ap_sig_bdd_381;
reg ap_sig_cseq_ST_st59_fsm_58;
reg ap_sig_bdd_390;
reg ap_sig_cseq_ST_st91_fsm_90;
reg ap_sig_bdd_398;
wire [31:0] grp_fu_532_p1;
reg [31:0] reg_597;
reg ap_sig_cseq_ST_st60_fsm_59;
reg ap_sig_bdd_411;
reg ap_sig_cseq_ST_st92_fsm_91;
reg ap_sig_bdd_418;
wire [0:0] exitcond_flatten_fu_604_p2;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_431;
reg ap_sig_bdd_436;
wire [10:0] indvar_flatten_next_fu_610_p2;
wire [5:0] i_0_i_mid2_fu_636_p3;
wire [5:0] j_fu_676_p2;
wire [0:0] exitcond_flatten8_fu_682_p2;
reg ap_sig_cseq_ST_st3_fsm_2;
reg ap_sig_bdd_453;
reg ap_sig_bdd_457;
wire [10:0] indvar_flatten_next7_fu_688_p2;
wire [5:0] i1_0_i_mid2_fu_714_p3;
wire [5:0] j_1_fu_754_p2;
wire [0:0] exitcond2_i_i_mid_fu_774_p2;
reg [0:0] exitcond2_i_i_mid_reg_1755;
reg ap_sig_cseq_ST_st4_fsm_3;
reg ap_sig_bdd_474;
wire [5:0] p_0_i_i_mid2_fu_786_p3;
reg [5:0] p_0_i_i_mid2_reg_1760;
wire [5:0] q_0_i_i_mid2_fu_799_p3;
reg [5:0] q_0_i_i_mid2_reg_1768;
reg ap_sig_cseq_ST_st5_fsm_4;
reg ap_sig_bdd_485;
wire [5:0] y_assign_fu_812_p2;
reg [5:0] y_assign_reg_1773;
wire signed [11:0] p_addr4_cast_fu_844_p1;
reg signed [11:0] p_addr4_cast_reg_1783;
wire [11:0] tmp_52_0_1_trn_cast_fu_867_p1;
reg [11:0] tmp_52_0_1_trn_cast_reg_1799;
wire signed [12:0] tmp_16_trn_cast1_fu_890_p1;
reg signed [12:0] tmp_16_trn_cast1_reg_1816;
wire [31:0] a_q0;
reg [31:0] a_load_1_reg_1821;
wire [31:0] a_q1;
reg [31:0] a_load_2_reg_1827;
wire [5:0] q_fu_893_p2;
reg [5:0] q_reg_1834;
wire [11:0] tmp_46_0_2_trn_cast_fu_898_p1;
reg [11:0] tmp_46_0_2_trn_cast_reg_1840;
wire [10:0] tmp_53_fu_912_p3;
reg [10:0] tmp_53_reg_1851;
wire [0:0] grp_fu_540_p2;
reg [0:0] tmp_18_reg_1861;
reg ap_sig_cseq_ST_st7_fsm_6;
reg ap_sig_bdd_525;
reg [31:0] a_load_3_reg_1866;
reg [63:0] tmp_48_0_2_reg_1872;
reg [31:0] a_load_4_reg_1877;
wire [11:0] p_addr4_fu_978_p2;
reg [11:0] p_addr4_reg_1894;
wire [11:0] p_addr8_fu_983_p2;
reg [11:0] p_addr8_reg_1899;
wire [11:0] p_addr10_fu_988_p2;
reg [11:0] p_addr10_reg_1904;
reg [0:0] tmp_44_reg_1909;
reg ap_sig_cseq_ST_st8_fsm_7;
reg ap_sig_bdd_549;
reg [31:0] a_load_5_reg_1914;
reg [31:0] a_load_6_reg_1921;
reg [63:0] tmp_48_2_reg_1927;
reg [0:0] tmp_50_reg_1942;
reg ap_sig_cseq_ST_st9_fsm_8;
reg ap_sig_bdd_566;
reg [31:0] a_load_7_reg_1947;
reg [31:0] a_load_8_reg_1954;
reg [63:0] tmp_48_2_2_reg_1960;
wire [63:0] tmp_89_fu_1001_p1;
reg [63:0] tmp_89_reg_1965;
reg [9:0] a_addr_1_reg_1971;
wire [3:0] speed_0_i_i_mid2_fu_1005_p3;
reg [3:0] speed_0_i_i_mid2_reg_1977;
reg [0:0] tmp_57_reg_1983;
reg [31:0] a_load_reg_1988;
reg [0:0] tmp_62_reg_1999;
reg ap_sig_cseq_ST_st11_fsm_10;
reg ap_sig_bdd_587;
reg [0:0] tmp_67_reg_2004;
wire [63:0] tmp_21_fu_1059_p3;
reg [63:0] tmp_21_reg_2009;
reg [0:0] tmp_72_reg_2014;
wire [31:0] grp_fu_526_p2;
reg [31:0] tmp_14_reg_2019;
wire [63:0] tmp_49_0_2_fu_1107_p3;
reg [63:0] tmp_49_0_2_reg_2029;
reg [0:0] tmp_77_reg_2034;
wire [31:0] b_q0;
reg [31:0] b_load_reg_2039;
wire [63:0] tmp_49_2_fu_1155_p3;
reg [63:0] tmp_49_2_reg_2045;
reg [0:0] tmp_82_reg_2050;
wire [63:0] tmp_49_2_2_fu_1203_p3;
reg [63:0] tmp_49_2_2_reg_2055;
wire [0:0] tmp_91_fu_1211_p2;
reg [0:0] tmp_91_reg_2060;
wire [0:0] or_cond_i12_i_i_fu_1251_p2;
reg [0:0] or_cond_i12_i_i_reg_2065;
reg ap_sig_cseq_ST_st17_fsm_16;
reg ap_sig_bdd_620;
wire [0:0] tmp_93_fu_1256_p2;
reg [0:0] tmp_93_reg_2071;
wire [31:0] x_assign_1_fu_1285_p3;
reg [31:0] x_assign_1_reg_2077;
wire [31:0] output_0_i13_i_i_fu_1293_p3;
wire [31:0] sum_4_i_i_fu_1301_p3;
reg [31:0] sum_4_i_i_reg_2089;
reg ap_sig_cseq_ST_st19_fsm_18;
reg ap_sig_bdd_635;
wire [0:0] tmp_45_fu_1343_p2;
reg [0:0] tmp_45_reg_2096;
reg [0:0] tmp_99_reg_2101;
wire [31:0] x_assign_6_0_1_fu_1348_p3;
reg ap_sig_cseq_ST_st20_fsm_19;
reg ap_sig_bdd_648;
wire [31:0] x_assign_2_fu_1395_p3;
reg [31:0] x_assign_2_reg_2111;
reg [31:0] tmp_31_reg_2116;
reg ap_sig_cseq_ST_st21_fsm_20;
reg ap_sig_bdd_659;
wire [31:0] sum_4_i_i_0_2_fu_1409_p3;
reg [31:0] sum_4_i_i_0_2_reg_2121;
reg ap_sig_cseq_ST_st31_fsm_30;
reg ap_sig_bdd_668;
wire [0:0] tmp_58_fu_1450_p2;
reg [0:0] tmp_58_reg_2127;
wire [31:0] x_assign_6_1_fu_1455_p3;
reg ap_sig_cseq_ST_st32_fsm_31;
reg ap_sig_bdd_680;
wire [31:0] sum_4_i_i_1_fu_1462_p3;
reg [31:0] sum_4_i_i_1_reg_2137;
reg ap_sig_cseq_ST_st36_fsm_35;
reg ap_sig_bdd_690;
wire [0:0] tmp_63_fu_1503_p2;
reg [0:0] tmp_63_reg_2142;
wire [31:0] x_assign_6_1_2_fu_1508_p3;
reg ap_sig_cseq_ST_st37_fsm_36;
reg ap_sig_bdd_701;
wire [31:0] sum_4_i_i_2_fu_1515_p3;
reg [31:0] sum_4_i_i_2_reg_2152;
reg ap_sig_cseq_ST_st48_fsm_47;
reg ap_sig_bdd_710;
wire [0:0] tmp_73_fu_1557_p2;
reg [0:0] tmp_73_reg_2157;
wire [31:0] x_assign_6_2_1_fu_1562_p3;
reg ap_sig_cseq_ST_st49_fsm_48;
reg ap_sig_bdd_721;
reg [31:0] tmp_27_reg_2167;
reg ap_sig_cseq_ST_st69_fsm_68;
reg ap_sig_bdd_729;
wire [13:0] indvar_flatten_next3_fu_1569_p2;
reg ap_sig_cseq_ST_st93_fsm_92;
reg ap_sig_bdd_738;
wire [11:0] indvar_flatten_next2_fu_1581_p3;
wire [0:0] exitcond2_i_i_fu_1589_p2;
wire [0:0] exitcond_flatten1_fu_1594_p2;
wire [3:0] speed_fu_1600_p2;
wire [0:0] exitcond_flatten2_fu_1605_p2;
wire [0:0] exitcond_flatten3_fu_1611_p2;
reg [0:0] exitcond_flatten3_reg_2201;
reg ap_sig_cseq_ST_pp3_stg0_fsm_93;
reg ap_sig_bdd_757;
reg ap_reg_ppiten_pp3_it0 = 1'b0;
reg ap_sig_ioackin_OUTPUT_STREAM_TREADY;
reg ap_reg_ppiten_pp3_it1 = 1'b0;
wire [10:0] indvar_flatten_next1_fu_1617_p2;
wire [5:0] i4_0_i_mid2_fu_1643_p3;
reg [5:0] i4_0_i_mid2_reg_2210;
wire [0:0] last_assign_fu_1700_p2;
reg [0:0] last_assign_reg_2220;
wire [5:0] j_2_fu_1706_p2;
reg [9:0] a_address0;
reg a_ce0;
reg a_we0;
reg [31:0] a_d0;
reg [9:0] a_address1;
reg a_ce1;
reg [9:0] b_address0;
reg b_ce0;
reg b_we0;
wire [31:0] b_d0;
reg [9:0] out_address0;
reg out_ce0;
reg out_we0;
wire [31:0] out_d0;
wire [31:0] out_q0;
reg [10:0] indvar_flatten_reg_331;
reg [5:0] i_0_i_reg_342;
reg [5:0] j_0_i_reg_353;
reg [10:0] indvar_flatten6_reg_364;
reg [5:0] i1_0_i_reg_375;
reg [5:0] j2_0_i_reg_386;
reg [0:0] exitcond_flatten4_reg_397;
reg [0:0] exitcond2_i_i1_reg_409;
reg [5:0] p_0_i_i_reg_420;
reg [5:0] q_0_i_i_reg_431;
reg [3:0] speed1_reg_442;
reg [3:0] speed_0_i_i_reg_453;
reg [11:0] indvar_flatten1_reg_464;
reg [13:0] indvar_flatten2_reg_475;
reg [5:0] i4_0_i_phi_fu_501_p4;
wire [63:0] tmp_3_fu_671_p1;
wire [63:0] tmp_6_fu_749_p1;
wire signed [63:0] tmp_13_fu_854_p1;
wire signed [63:0] tmp_24_fu_877_p1;
wire signed [63:0] tmp_46_fu_907_p1;
wire signed [63:0] tmp_55_fu_929_p1;
wire [63:0] tmp_65_fu_942_p1;
wire signed [63:0] tmp_80_fu_973_p1;
wire [63:0] tmp_84_fu_993_p1;
wire [63:0] tmp_86_fu_997_p1;
wire [63:0] tmp_103_fu_1695_p1;
reg ap_reg_ioackin_OUTPUT_STREAM_TREADY = 1'b0;
wire [31:0] ret_fu_644_p1;
reg [31:0] grp_fu_520_p0;
reg [31:0] grp_fu_520_p1;
reg ap_sig_cseq_ST_st61_fsm_60;
reg ap_sig_bdd_931;
reg ap_sig_cseq_ST_st70_fsm_69;
reg ap_sig_bdd_938;
reg ap_sig_cseq_ST_st75_fsm_74;
reg ap_sig_bdd_945;
reg [31:0] grp_fu_526_p0;
reg [31:0] grp_fu_526_p1;
reg ap_sig_cseq_ST_st66_fsm_65;
reg ap_sig_bdd_955;
wire [63:0] grp_fu_532_p0;
reg [31:0] grp_fu_535_p0;
wire [31:0] sum_4_i_i_0_1_fu_1402_p3;
reg [31:0] grp_fu_540_p0;
reg [31:0] grp_fu_540_p1;
reg [63:0] grp_fu_547_p0;
reg [63:0] grp_fu_547_p1;
reg ap_sig_cseq_ST_st26_fsm_25;
reg ap_sig_bdd_994;
reg ap_sig_cseq_ST_st43_fsm_42;
reg ap_sig_bdd_1001;
reg ap_sig_cseq_ST_st55_fsm_54;
reg ap_sig_bdd_1009;
reg ap_sig_cseq_ST_st87_fsm_86;
reg ap_sig_bdd_1017;
reg [63:0] grp_fu_552_p0;
reg [63:0] grp_fu_552_p1;
reg ap_sig_cseq_ST_st81_fsm_80;
reg ap_sig_bdd_1031;
wire [0:0] exitcond4_i_fu_616_p2;
wire [5:0] i_fu_630_p2;
wire [5:0] j_0_i_mid2_fu_622_p3;
wire [10:0] tmp_1_fu_653_p3;
wire [11:0] p_addr_cast_fu_661_p1;
wire [11:0] tmp_7_trn_cast_fu_649_p1;
wire [11:0] p_addr1_fu_665_p2;
wire [0:0] exitcond2_i_fu_694_p2;
wire [5:0] i_s_fu_708_p2;
wire [5:0] j2_0_i_mid2_fu_700_p3;
wire [10:0] tmp_5_fu_731_p3;
wire [11:0] p_addr2_cast_fu_739_p1;
wire [11:0] tmp_6_trn_cast_fu_727_p1;
wire [11:0] p_addr3_fu_743_p2;
wire [0:0] not_exitcond_flatten_fu_768_p2;
wire [5:0] p_0_i_i_mid_fu_760_p3;
wire [5:0] p_fu_780_p2;
wire [0:0] tmp_7_fu_794_p2;
wire [5:0] x_assign_fu_807_p2;
wire [5:0] tmp_10_fu_818_p2;
wire [10:0] tmp_12_fu_836_p3;
wire signed [11:0] tmp_16_trn_cast_fu_832_p1;
wire signed [11:0] p_addr5_fu_848_p2;
wire signed [11:0] p_addr6_fu_871_p2;
wire signed [11:0] p_addr7_fu_902_p2;
wire [12:0] p_addr8_cast_fu_919_p1;
wire signed [12:0] p_addr9_fu_923_p2;
wire [11:0] p_addr8_cast1_fu_934_p1;
wire [11:0] p_addr_fu_937_p2;
wire [5:0] x_assign_s_fu_947_p2;
wire [10:0] tmp_75_fu_952_p3;
wire [12:0] p_addr11_cast_fu_964_p1;
wire signed [12:0] p_addr2_fu_968_p2;
wire [11:0] p_addr11_cast1_fu_960_p1;
wire [31:0] a_load_1_to_int_fu_1019_p1;
wire [7:0] tmp_fu_1022_p4;
wire [22:0] tmp_16_fu_1032_p1;
wire [0:0] notrhs_fu_1042_p2;
wire [0:0] notlhs_fu_1036_p2;
wire [0:0] tmp_17_fu_1048_p2;
wire [0:0] tmp_19_fu_1054_p2;
wire [31:0] a_load_3_to_int_fu_1067_p1;
wire [7:0] tmp_47_fu_1070_p4;
wire [22:0] tmp_48_fu_1080_p1;
wire [0:0] notrhs2_fu_1090_p2;
wire [0:0] notlhs2_fu_1084_p2;
wire [0:0] tmp_49_fu_1096_p2;
wire [0:0] tmp_51_fu_1102_p2;
wire [31:0] a_load_6_to_int_fu_1115_p1;
wire [7:0] tmp_64_fu_1118_p4;
wire [22:0] tmp_83_fu_1128_p1;
wire [0:0] notrhs5_fu_1138_p2;
wire [0:0] notlhs5_fu_1132_p2;
wire [0:0] tmp_66_fu_1144_p2;
wire [0:0] tmp_68_fu_1150_p2;
wire [31:0] a_load_8_to_int_fu_1163_p1;
wire [7:0] tmp_74_fu_1166_p4;
wire [22:0] tmp_88_fu_1176_p1;
wire [0:0] notrhs7_fu_1186_p2;
wire [0:0] notlhs7_fu_1180_p2;
wire [0:0] tmp_76_fu_1192_p2;
wire [0:0] tmp_78_fu_1198_p2;
wire [31:0] m_assign_to_int_fu_1216_p1;
wire [7:0] tmp_79_fu_1219_p4;
wire [22:0] tmp_90_fu_1229_p1;
wire [0:0] notrhs8_fu_1239_p2;
wire [0:0] notlhs8_fu_1233_p2;
wire [0:0] tmp_81_fu_1245_p2;
wire [0:0] sel_tmp1_fu_1262_p2;
wire [0:0] sel_tmp2_fu_1267_p2;
wire [0:0] tmp_95_fu_1280_p2;
wire [31:0] tmp_94_fu_1272_p3;
wire [31:0] a_load_2_to_int_fu_1308_p1;
wire [7:0] tmp_25_fu_1311_p4;
wire [22:0] tmp_30_fu_1321_p1;
wire [0:0] notrhs1_fu_1331_p2;
wire [0:0] notlhs1_fu_1325_p2;
wire [0:0] tmp_33_fu_1337_p2;
wire [31:0] x_assign_1_to_int_fu_1355_p1;
wire [7:0] tmp_96_fu_1358_p4;
wire [22:0] tmp_97_fu_1368_p1;
wire [0:0] notrhs9_fu_1378_p2;
wire [0:0] notlhs9_fu_1372_p2;
wire [0:0] tmp_98_fu_1384_p2;
wire [0:0] tmp_100_fu_1390_p2;
wire [31:0] a_load_4_to_int_fu_1415_p1;
wire [7:0] tmp_54_fu_1418_p4;
wire [22:0] tmp_60_fu_1428_p1;
wire [0:0] notrhs3_fu_1438_p2;
wire [0:0] notlhs3_fu_1432_p2;
wire [0:0] tmp_56_fu_1444_p2;
wire [31:0] a_load_5_to_int_fu_1468_p1;
wire [7:0] tmp_59_fu_1471_p4;
wire [22:0] tmp_70_fu_1481_p1;
wire [0:0] notrhs4_fu_1491_p2;
wire [0:0] notlhs4_fu_1485_p2;
wire [0:0] tmp_61_fu_1497_p2;
wire [31:0] a_load_7_to_int_fu_1522_p1;
wire [7:0] tmp_69_fu_1525_p4;
wire [22:0] tmp_85_fu_1535_p1;
wire [0:0] notrhs6_fu_1545_p2;
wire [0:0] notlhs6_fu_1539_p2;
wire [0:0] tmp_71_fu_1551_p2;
wire [11:0] indvar_flatten13_op_fu_1575_p2;
wire [0:0] exitcond_i_fu_1623_p2;
wire [5:0] i_1_fu_1637_p2;
wire [4:0] tmp_101_fu_1651_p1;
wire [5:0] j5_0_i_mid2_fu_1629_p3;
wire [9:0] j5_0_i_cast5_fu_1663_p1;
wire [9:0] tmp_8_fu_1655_p3;
wire [10:0] tmp_102_fu_1677_p3;
wire [11:0] p_addr16_cast_fu_1685_p1;
wire [11:0] tmp_5_trn_cast_fu_1673_p1;
wire [11:0] p_addr11_fu_1689_p2;
wire [9:0] k_fu_1667_p2;
reg [1:0] grp_fu_520_opcode;
wire grp_fu_520_ce;
wire grp_fu_526_ce;
reg [4:0] grp_fu_540_opcode;
wire grp_fu_547_ce;
wire grp_fu_552_ce;
reg ap_sig_cseq_ST_st96_fsm_94;
reg ap_sig_bdd_1778;
reg [94:0] ap_NS_fsm;
HLS_accel_CONTROL_BUS_s_axi #(
.C_ADDR_WIDTH( C_S_AXI_CONTROL_BUS_ADDR_WIDTH ),
.C_DATA_WIDTH( C_S_AXI_CONTROL_BUS_DATA_WIDTH ))
HLS_accel_CONTROL_BUS_s_axi_U(
.AWVALID( s_axi_CONTROL_BUS_AWVALID ),
.AWREADY( s_axi_CONTROL_BUS_AWREADY ),
.AWADDR( s_axi_CONTROL_BUS_AWADDR ),
.WVALID( s_axi_CONTROL_BUS_WVALID ),
.WREADY( s_axi_CONTROL_BUS_WREADY ),
.WDATA( s_axi_CONTROL_BUS_WDATA ),
.WSTRB( s_axi_CONTROL_BUS_WSTRB ),
.ARVALID( s_axi_CONTROL_BUS_ARVALID ),
.ARREADY( s_axi_CONTROL_BUS_ARREADY ),
.ARADDR( s_axi_CONTROL_BUS_ARADDR ),
.RVALID( s_axi_CONTROL_BUS_RVALID ),
.RREADY( s_axi_CONTROL_BUS_RREADY ),
.RDATA( s_axi_CONTROL_BUS_RDATA ),
.RRESP( s_axi_CONTROL_BUS_RRESP ),
.BVALID( s_axi_CONTROL_BUS_BVALID ),
.BREADY( s_axi_CONTROL_BUS_BREADY ),
.BRESP( s_axi_CONTROL_BUS_BRESP ),
.ACLK( ap_clk ),
.ARESET( ap_rst_n_inv ),
.ACLK_EN( HLS_accel_CONTROL_BUS_s_axi_U_ap_dummy_ce ),
.ap_start( ap_start ),
.interrupt( interrupt ),
.ap_ready( ap_ready ),
.ap_done( ap_done ),
.ap_idle( ap_idle )
);
HLS_accel_a #(
.DataWidth( 32 ),
.AddressRange( 1024 ),
.AddressWidth( 10 ))
a_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.address0( a_address0 ),
.ce0( a_ce0 ),
.we0( a_we0 ),
.d0( a_d0 ),
.q0( a_q0 ),
.address1( a_address1 ),
.ce1( a_ce1 ),
.q1( a_q1 )
);
HLS_accel_b #(
.DataWidth( 32 ),
.AddressRange( 1024 ),
.AddressWidth( 10 ))
b_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.address0( b_address0 ),
.ce0( b_ce0 ),
.we0( b_we0 ),
.d0( b_d0 ),
.q0( b_q0 )
);
HLS_accel_b #(
.DataWidth( 32 ),
.AddressRange( 1024 ),
.AddressWidth( 10 ))
out_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.address0( out_address0 ),
.ce0( out_ce0 ),
.we0( out_we0 ),
.d0( out_d0 ),
.q0( out_q0 )
);
HLS_accel_faddfsub_32ns_32ns_32_5_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
HLS_accel_faddfsub_32ns_32ns_32_5_full_dsp_U0(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_520_p0 ),
.din1( grp_fu_520_p1 ),
.opcode( grp_fu_520_opcode ),
.ce( grp_fu_520_ce ),
.dout( grp_fu_520_p2 )
);
HLS_accel_fmul_32ns_32ns_32_4_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
HLS_accel_fmul_32ns_32ns_32_4_max_dsp_U1(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_526_p0 ),
.din1( grp_fu_526_p1 ),
.ce( grp_fu_526_ce ),
.dout( grp_fu_526_p2 )
);
HLS_accel_fptrunc_64ns_32_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 64 ),
.dout_WIDTH( 32 ))
HLS_accel_fptrunc_64ns_32_1_U2(
.din0( grp_fu_532_p0 ),
.dout( grp_fu_532_p1 )
);
HLS_accel_fpext_32ns_64_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
HLS_accel_fpext_32ns_64_1_U3(
.din0( grp_fu_535_p0 ),
.dout( grp_fu_535_p1 )
);
HLS_accel_fcmp_32ns_32ns_1_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
HLS_accel_fcmp_32ns_32ns_1_1_U4(
.din0( grp_fu_540_p0 ),
.din1( grp_fu_540_p1 ),
.opcode( grp_fu_540_opcode ),
.dout( grp_fu_540_p2 )
);
HLS_accel_dadd_64ns_64ns_64_5_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
HLS_accel_dadd_64ns_64ns_64_5_full_dsp_U5(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_547_p0 ),
.din1( grp_fu_547_p1 ),
.ce( grp_fu_547_ce ),
.dout( grp_fu_547_p2 )
);
HLS_accel_dmul_64ns_64ns_64_6_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 6 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
HLS_accel_dmul_64ns_64ns_64_6_max_dsp_U6(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_552_p0 ),
.din1( grp_fu_552_p1 ),
.ce( grp_fu_552_ce ),
.dout( grp_fu_552_p2 )
);
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst_n_inv == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ioackin_OUTPUT_STREAM_TREADY assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ioackin_OUTPUT_STREAM_TREADY
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_93) & (ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & ~((ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)))) begin
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_93) & (ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_logic_1 == OUTPUT_STREAM_TREADY))) begin
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp3_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it0
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_93) & ~((ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & ~(ap_const_lv1_0 == exitcond_flatten3_fu_1611_p2))) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92) & ~(ap_const_lv1_0 == exitcond_flatten2_fu_1605_p2))) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp3_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it1
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_93) & ~((ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & (ap_const_lv1_0 == exitcond_flatten3_fu_1611_p2))) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92) & ~(ap_const_lv1_0 == exitcond_flatten2_fu_1605_p2)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_93) & ~((ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & ~(ap_const_lv1_0 == exitcond_flatten3_fu_1611_p2)))) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_457 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_682_p2))) begin
exitcond2_i_i1_reg_409 <= ap_const_lv1_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92) & (ap_const_lv1_0 == exitcond_flatten2_fu_1605_p2))) begin
exitcond2_i_i1_reg_409 <= exitcond2_i_i_fu_1589_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_457 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_682_p2))) begin
exitcond_flatten4_reg_397 <= ap_const_lv1_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92) & (ap_const_lv1_0 == exitcond_flatten2_fu_1605_p2))) begin
exitcond_flatten4_reg_397 <= exitcond_flatten1_fu_1594_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~ap_sig_bdd_436 & ~(ap_const_lv1_0 == exitcond_flatten_fu_604_p2))) begin
i1_0_i_reg_375 <= ap_const_lv6_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == exitcond_flatten8_fu_682_p2) & ~ap_sig_bdd_457)) begin
i1_0_i_reg_375 <= i1_0_i_mid2_fu_714_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92) & ~(ap_const_lv1_0 == exitcond_flatten2_fu_1605_p2))) begin
i4_0_i_reg_497 <= ap_const_lv6_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_93) & (ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & ~((ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)))) begin
i4_0_i_reg_497 <= i4_0_i_mid2_reg_2210;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond_flatten_fu_604_p2) & ~ap_sig_bdd_436)) begin
i_0_i_reg_342 <= i_0_i_mid2_fu_636_p3;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
i_0_i_reg_342 <= ap_const_lv6_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_457 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_682_p2))) begin
indvar_flatten1_reg_464 <= ap_const_lv12_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92) & (ap_const_lv1_0 == exitcond_flatten2_fu_1605_p2))) begin
indvar_flatten1_reg_464 <= indvar_flatten_next2_fu_1581_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_457 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_682_p2))) begin
indvar_flatten2_reg_475 <= ap_const_lv14_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92) & (ap_const_lv1_0 == exitcond_flatten2_fu_1605_p2))) begin
indvar_flatten2_reg_475 <= indvar_flatten_next3_fu_1569_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92) & ~(ap_const_lv1_0 == exitcond_flatten2_fu_1605_p2))) begin
indvar_flatten3_reg_486 <= ap_const_lv11_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_93) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & ~((ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & (ap_const_lv1_0 == exitcond_flatten3_fu_1611_p2))) begin
indvar_flatten3_reg_486 <= indvar_flatten_next1_fu_1617_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~ap_sig_bdd_436 & ~(ap_const_lv1_0 == exitcond_flatten_fu_604_p2))) begin
indvar_flatten6_reg_364 <= ap_const_lv11_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == exitcond_flatten8_fu_682_p2) & ~ap_sig_bdd_457)) begin
indvar_flatten6_reg_364 <= indvar_flatten_next7_fu_688_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond_flatten_fu_604_p2) & ~ap_sig_bdd_436)) begin
indvar_flatten_reg_331 <= indvar_flatten_next_fu_610_p2;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
indvar_flatten_reg_331 <= ap_const_lv11_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~ap_sig_bdd_436 & ~(ap_const_lv1_0 == exitcond_flatten_fu_604_p2))) begin
j2_0_i_reg_386 <= ap_const_lv6_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == exitcond_flatten8_fu_682_p2) & ~ap_sig_bdd_457)) begin
j2_0_i_reg_386 <= j_1_fu_754_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92) & ~(ap_const_lv1_0 == exitcond_flatten2_fu_1605_p2))) begin
j5_0_i_reg_508 <= ap_const_lv6_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_93) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & ~((ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & (ap_const_lv1_0 == exitcond_flatten3_fu_1611_p2))) begin
j5_0_i_reg_508 <= j_2_fu_1706_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond_flatten_fu_604_p2) & ~ap_sig_bdd_436)) begin
j_0_i_reg_353 <= j_fu_676_p2;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
j_0_i_reg_353 <= ap_const_lv6_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_457 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_682_p2))) begin
p_0_i_i_reg_420 <= ap_const_lv6_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92) & (ap_const_lv1_0 == exitcond_flatten2_fu_1605_p2))) begin
p_0_i_i_reg_420 <= p_0_i_i_mid2_reg_1760;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_457 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_682_p2))) begin
q_0_i_i_reg_431 <= ap_const_lv6_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92) & (ap_const_lv1_0 == exitcond_flatten2_fu_1605_p2))) begin
q_0_i_i_reg_431 <= q_reg_1834;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_457 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_682_p2))) begin
speed1_reg_442 <= ap_const_lv4_1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92) & (ap_const_lv1_0 == exitcond_flatten2_fu_1605_p2))) begin
speed1_reg_442 <= speed_fu_1600_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_457 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_682_p2))) begin
speed_0_i_i_reg_453 <= ap_const_lv4_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92) & (ap_const_lv1_0 == exitcond_flatten2_fu_1605_p2))) begin
speed_0_i_i_reg_453 <= speed_0_i_i_mid2_reg_1977;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_8)) begin
a_addr_1_reg_1971 <= tmp_89_fu_1001_p1;
a_load_7_reg_1947 <= a_q1;
a_load_8_reg_1954 <= a_q0;
tmp_48_2_2_reg_1960 <= grp_fu_535_p1;
tmp_89_reg_1965[0] <= tmp_89_fu_1001_p1[0];
tmp_89_reg_1965[1] <= tmp_89_fu_1001_p1[1];
tmp_89_reg_1965[2] <= tmp_89_fu_1001_p1[2];
tmp_89_reg_1965[3] <= tmp_89_fu_1001_p1[3];
tmp_89_reg_1965[4] <= tmp_89_fu_1001_p1[4];
tmp_89_reg_1965[5] <= tmp_89_fu_1001_p1[5];
tmp_89_reg_1965[6] <= tmp_89_fu_1001_p1[6];
tmp_89_reg_1965[7] <= tmp_89_fu_1001_p1[7];
tmp_89_reg_1965[8] <= tmp_89_fu_1001_p1[8];
tmp_89_reg_1965[9] <= tmp_89_fu_1001_p1[9];
tmp_89_reg_1965[10] <= tmp_89_fu_1001_p1[10];
tmp_89_reg_1965[11] <= tmp_89_fu_1001_p1[11];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
a_load_1_reg_1821 <= a_q0;
a_load_2_reg_1827 <= a_q1;
q_reg_1834 <= q_fu_893_p2;
tmp_16_trn_cast1_reg_1816 <= tmp_16_trn_cast1_fu_890_p1;
tmp_46_0_2_trn_cast_reg_1840[0] <= tmp_46_0_2_trn_cast_fu_898_p1[0];
tmp_46_0_2_trn_cast_reg_1840[1] <= tmp_46_0_2_trn_cast_fu_898_p1[1];
tmp_46_0_2_trn_cast_reg_1840[2] <= tmp_46_0_2_trn_cast_fu_898_p1[2];
tmp_46_0_2_trn_cast_reg_1840[3] <= tmp_46_0_2_trn_cast_fu_898_p1[3];
tmp_46_0_2_trn_cast_reg_1840[4] <= tmp_46_0_2_trn_cast_fu_898_p1[4];
tmp_46_0_2_trn_cast_reg_1840[5] <= tmp_46_0_2_trn_cast_fu_898_p1[5];
tmp_53_reg_1851[5] <= tmp_53_fu_912_p3[5];
tmp_53_reg_1851[6] <= tmp_53_fu_912_p3[6];
tmp_53_reg_1851[7] <= tmp_53_fu_912_p3[7];
tmp_53_reg_1851[8] <= tmp_53_fu_912_p3[8];
tmp_53_reg_1851[9] <= tmp_53_fu_912_p3[9];
tmp_53_reg_1851[10] <= tmp_53_fu_912_p3[10];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_lv1_0 == tmp_23_reg_1793) & (ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6))) begin
a_load_3_reg_1866 <= a_q1;
tmp_48_0_2_reg_1872 <= grp_fu_535_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_lv1_0 == tmp_52_reg_1810) & (ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6))) begin
a_load_4_reg_1877 <= a_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7)) begin
a_load_5_reg_1914 <= a_q1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_lv1_0 == tmp_52_reg_1810) & (ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7))) begin
a_load_6_reg_1921 <= a_q0;
tmp_48_2_reg_1927 <= grp_fu_535_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9)) begin
a_load_reg_1988 <= a_q1;
speed_0_i_i_mid2_reg_1977 <= speed_0_i_i_mid2_fu_1005_p3;
tmp_32_reg_1995 <= tmp_32_fu_1013_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st14_fsm_13)) begin
b_load_reg_2039 <= b_q0;
tmp_77_reg_2034 <= grp_fu_540_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3)) begin
exitcond2_i_i_mid_reg_1755 <= exitcond2_i_i_mid_fu_774_p2;
p_0_i_i_mid2_reg_1760 <= p_0_i_i_mid2_fu_786_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_93) & ~((ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)))) begin
exitcond_flatten3_reg_2201 <= exitcond_flatten3_fu_1611_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_93) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & ~((ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & (ap_const_lv1_0 == exitcond_flatten3_fu_1611_p2))) begin
i4_0_i_mid2_reg_2210 <= i4_0_i_mid2_fu_1643_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_93) & ~((ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & (ap_const_lv1_0 == exitcond_flatten3_fu_1611_p2))) begin
last_assign_reg_2220 <= last_assign_fu_1700_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st17_fsm_16)) begin
or_cond_i12_i_i_reg_2065 <= or_cond_i12_i_i_fu_1251_p2;
tmp_93_reg_2071 <= tmp_93_fu_1256_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6)) begin
p_addr10_reg_1904 <= p_addr10_fu_988_p2;
p_addr4_reg_1894 <= p_addr4_fu_978_p2;
p_addr8_reg_1899 <= p_addr8_fu_983_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
p_addr4_cast_reg_1783[5] <= p_addr4_cast_fu_844_p1[5];
p_addr4_cast_reg_1783[6] <= p_addr4_cast_fu_844_p1[6];
p_addr4_cast_reg_1783[7] <= p_addr4_cast_fu_844_p1[7];
p_addr4_cast_reg_1783[8] <= p_addr4_cast_fu_844_p1[8];
p_addr4_cast_reg_1783[9] <= p_addr4_cast_fu_844_p1[9];
p_addr4_cast_reg_1783[10] <= p_addr4_cast_fu_844_p1[10];
p_addr4_cast_reg_1783[11] <= p_addr4_cast_fu_844_p1[11];
q_0_i_i_mid2_reg_1768 <= q_0_i_i_mid2_fu_799_p3;
tmp_11_reg_1778 <= tmp_10_fu_818_p2[ap_const_lv32_5];
tmp_23_reg_1793 <= x_assign_fu_807_p2[ap_const_lv32_5];
tmp_52_0_1_trn_cast_reg_1799[0] <= tmp_52_0_1_trn_cast_fu_867_p1[0];
tmp_52_0_1_trn_cast_reg_1799[1] <= tmp_52_0_1_trn_cast_fu_867_p1[1];
tmp_52_0_1_trn_cast_reg_1799[2] <= tmp_52_0_1_trn_cast_fu_867_p1[2];
tmp_52_0_1_trn_cast_reg_1799[3] <= tmp_52_0_1_trn_cast_fu_867_p1[3];
tmp_52_0_1_trn_cast_reg_1799[4] <= tmp_52_0_1_trn_cast_fu_867_p1[4];
tmp_52_0_1_trn_cast_reg_1799[5] <= tmp_52_0_1_trn_cast_fu_867_p1[5];
tmp_52_reg_1810 <= y_assign_fu_812_p2[ap_const_lv32_5];
y_assign_reg_1773 <= y_assign_fu_812_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5) & (tmp_11_reg_1778 == ap_const_lv1_0)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st25_fsm_24) & (ap_const_lv1_0 == tmp_23_reg_1793)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st42_fsm_41) & (ap_const_lv1_0 == tmp_52_reg_1810)) | (ap_const_logic_1 == ap_sig_cseq_ST_st54_fsm_53) | ((ap_const_logic_1 == ap_sig_cseq_ST_st80_fsm_79) & (ap_const_lv1_0 == tmp_32_reg_1995)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st80_fsm_79) & ~(ap_const_lv1_0 == tmp_32_reg_1995)))) begin
reg_562 <= grp_fu_535_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9) & (ap_const_lv1_0 == tmp_32_fu_1013_p2)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9) & ~(ap_const_lv1_0 == tmp_32_fu_1013_p2)))) begin
reg_568 <= grp_fu_535_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((tmp_11_reg_1778 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_11)) | ((ap_const_lv1_0 == tmp_23_reg_1793) & (ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_12)) | ((ap_const_lv1_0 == tmp_52_reg_1810) & (ap_const_logic_1 == ap_sig_cseq_ST_st14_fsm_13)) | (ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14) | ((ap_const_lv1_0 == tmp_32_reg_1995) & (ap_const_logic_1 == ap_sig_cseq_ST_st86_fsm_85)) | (~(ap_const_lv1_0 == tmp_32_reg_1995) & (ap_const_logic_1 == ap_sig_cseq_ST_st86_fsm_85)))) begin
reg_573 <= grp_fu_552_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14) | (ap_const_logic_1 == ap_sig_cseq_ST_st74_fsm_73) | (ap_const_logic_1 == ap_sig_cseq_ST_st79_fsm_78))) begin
reg_578 <= grp_fu_520_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st16_fsm_15) | ((ap_const_lv1_0 == tmp_23_reg_1793) & (ap_const_logic_1 == ap_sig_cseq_ST_st24_fsm_23)) | (ap_const_logic_1 == ap_sig_cseq_ST_st41_fsm_40) | (ap_const_logic_1 == ap_sig_cseq_ST_st53_fsm_52) | (ap_const_logic_1 == ap_sig_cseq_ST_st65_fsm_64))) begin
reg_585 <= grp_fu_520_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((tmp_11_reg_1778 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st18_fsm_17)) | ((ap_const_lv1_0 == tmp_23_reg_1793) & (ap_const_logic_1 == ap_sig_cseq_ST_st30_fsm_29)) | ((ap_const_lv1_0 == tmp_52_reg_1810) & (ap_const_logic_1 == ap_sig_cseq_ST_st47_fsm_46)) | (ap_const_logic_1 == ap_sig_cseq_ST_st59_fsm_58) | ((ap_const_lv1_0 == tmp_32_reg_1995) & (ap_const_logic_1 == ap_sig_cseq_ST_st91_fsm_90)) | (~(ap_const_lv1_0 == tmp_32_reg_1995) & (ap_const_logic_1 == ap_sig_cseq_ST_st91_fsm_90)))) begin
reg_592 <= grp_fu_547_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st60_fsm_59) | ((ap_const_lv1_0 == tmp_32_reg_1995) & (ap_const_logic_1 == ap_sig_cseq_ST_st92_fsm_91)) | (~(ap_const_lv1_0 == tmp_32_reg_1995) & (ap_const_logic_1 == ap_sig_cseq_ST_st92_fsm_91)))) begin
reg_597 <= grp_fu_532_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st31_fsm_30)) begin
sum_4_i_i_0_2_reg_2121 <= sum_4_i_i_0_2_fu_1409_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st36_fsm_35)) begin
sum_4_i_i_1_reg_2137 <= sum_4_i_i_1_fu_1462_p3;
tmp_63_reg_2142 <= tmp_63_fu_1503_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st48_fsm_47)) begin
sum_4_i_i_2_reg_2152 <= sum_4_i_i_2_fu_1515_p3;
tmp_73_reg_2157 <= tmp_73_fu_1557_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st19_fsm_18)) begin
sum_4_i_i_reg_2089 <= sum_4_i_i_fu_1301_p3;
tmp_99_reg_2101 <= grp_fu_540_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_12)) begin
tmp_14_reg_2019 <= grp_fu_526_p2;
tmp_72_reg_2014 <= grp_fu_540_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_11_reg_1778 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6))) begin
tmp_18_reg_1861 <= grp_fu_540_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_11_reg_1778 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_12))) begin
tmp_21_reg_2009 <= tmp_21_fu_1059_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st69_fsm_68)) begin
tmp_27_reg_2167 <= grp_fu_526_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st21_fsm_20)) begin
tmp_31_reg_2116 <= grp_fu_526_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_lv1_0 == tmp_23_reg_1793) & (ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7))) begin
tmp_44_reg_1909 <= grp_fu_540_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_lv1_0 == tmp_23_reg_1793) & (ap_const_logic_1 == ap_sig_cseq_ST_st19_fsm_18))) begin
tmp_45_reg_2096 <= tmp_45_fu_1343_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_lv1_0 == tmp_23_reg_1793) & (ap_const_logic_1 == ap_sig_cseq_ST_st14_fsm_13))) begin
tmp_49_0_2_reg_2029 <= tmp_49_0_2_fu_1107_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st16_fsm_15)) begin
tmp_49_2_2_reg_2055 <= tmp_49_2_2_fu_1203_p3;
tmp_91_reg_2060 <= tmp_91_fu_1211_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_lv1_0 == tmp_52_reg_1810) & (ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14))) begin
tmp_49_2_reg_2045 <= tmp_49_2_fu_1155_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_lv1_0 == tmp_23_reg_1793) & (ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_8))) begin
tmp_50_reg_1942 <= grp_fu_540_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_lv1_0 == tmp_52_reg_1810) & (ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9))) begin
tmp_57_reg_1983 <= grp_fu_540_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_lv1_0 == tmp_52_reg_1810) & (ap_const_logic_1 == ap_sig_cseq_ST_st31_fsm_30))) begin
tmp_58_reg_2127 <= tmp_58_fu_1450_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_10)) begin
tmp_62_reg_1999 <= grp_fu_540_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_lv1_0 == tmp_52_reg_1810) & (ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_11))) begin
tmp_67_reg_2004 <= grp_fu_540_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14)) begin
tmp_82_reg_2050 <= grp_fu_540_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st18_fsm_17)) begin
x_assign_1_reg_2077[19] <= x_assign_1_fu_1285_p3[19];
x_assign_1_reg_2077[22] <= x_assign_1_fu_1285_p3[22];
x_assign_1_reg_2077[23] <= x_assign_1_fu_1285_p3[23];
x_assign_1_reg_2077[25] <= x_assign_1_fu_1285_p3[25];
x_assign_1_reg_2077[30] <= x_assign_1_fu_1285_p3[30];
x_assign_1_reg_2077[31] <= x_assign_1_fu_1285_p3[31];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st20_fsm_19)) begin
x_assign_2_reg_2111[19] <= x_assign_2_fu_1395_p3[19];
x_assign_2_reg_2111[22] <= x_assign_2_fu_1395_p3[22];
x_assign_2_reg_2111[23] <= x_assign_2_fu_1395_p3[23];
x_assign_2_reg_2111[25] <= x_assign_2_fu_1395_p3[25];
x_assign_2_reg_2111[30] <= x_assign_2_fu_1395_p3[30];
x_assign_2_reg_2111[31] <= x_assign_2_fu_1395_p3[31];
end
end
/// INPUT_STREAM_TREADY assign process. ///
always @ (exitcond_flatten_fu_604_p2 or ap_sig_cseq_ST_st2_fsm_1 or ap_sig_bdd_436 or exitcond_flatten8_fu_682_p2 or ap_sig_cseq_ST_st3_fsm_2 or ap_sig_bdd_457)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond_flatten_fu_604_p2) & ~ap_sig_bdd_436) | ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == exitcond_flatten8_fu_682_p2) & ~ap_sig_bdd_457))) begin
INPUT_STREAM_TREADY = ap_const_logic_1;
end else begin
INPUT_STREAM_TREADY = ap_const_logic_0;
end
end
/// OUTPUT_STREAM_TVALID assign process. ///
always @ (exitcond_flatten3_reg_2201 or ap_sig_cseq_ST_pp3_stg0_fsm_93 or ap_reg_ppiten_pp3_it1 or ap_reg_ioackin_OUTPUT_STREAM_TREADY)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_93) & (ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_logic_0 == ap_reg_ioackin_OUTPUT_STREAM_TREADY))) begin
OUTPUT_STREAM_TVALID = ap_const_logic_1;
end else begin
OUTPUT_STREAM_TVALID = ap_const_logic_0;
end
end
/// a_address0 assign process. ///
always @ (ap_sig_cseq_ST_st6_fsm_5 or ap_sig_cseq_ST_st2_fsm_1 or ap_sig_cseq_ST_st5_fsm_4 or ap_sig_cseq_ST_st7_fsm_6 or ap_sig_cseq_ST_st8_fsm_7 or a_addr_1_reg_1971 or ap_sig_cseq_ST_st93_fsm_92 or tmp_3_fu_671_p1 or tmp_13_fu_854_p1 or tmp_55_fu_929_p1 or tmp_80_fu_973_p1 or tmp_86_fu_997_p1)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92)) begin
a_address0 = a_addr_1_reg_1971;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
a_address0 = tmp_3_fu_671_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7)) begin
a_address0 = tmp_86_fu_997_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6)) begin
a_address0 = tmp_80_fu_973_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
a_address0 = tmp_55_fu_929_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
a_address0 = tmp_13_fu_854_p1;
end else begin
a_address0 = 'bx;
end
end
/// a_address1 assign process. ///
always @ (ap_sig_cseq_ST_st6_fsm_5 or ap_sig_cseq_ST_st5_fsm_4 or ap_sig_cseq_ST_st7_fsm_6 or ap_sig_cseq_ST_st8_fsm_7 or ap_sig_cseq_ST_st9_fsm_8 or tmp_89_fu_1001_p1 or tmp_24_fu_877_p1 or tmp_46_fu_907_p1 or tmp_65_fu_942_p1 or tmp_84_fu_993_p1)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_8)) begin
a_address1 = tmp_89_fu_1001_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7)) begin
a_address1 = tmp_84_fu_993_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6)) begin
a_address1 = tmp_65_fu_942_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
a_address1 = tmp_46_fu_907_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
a_address1 = tmp_24_fu_877_p1;
end else begin
a_address1 = 'bx;
end
end
/// a_ce0 assign process. ///
always @ (ap_sig_cseq_ST_st6_fsm_5 or ap_sig_cseq_ST_st2_fsm_1 or ap_sig_bdd_436 or ap_sig_cseq_ST_st5_fsm_4 or ap_sig_cseq_ST_st7_fsm_6 or ap_sig_cseq_ST_st8_fsm_7 or ap_sig_cseq_ST_st93_fsm_92)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5) | ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~ap_sig_bdd_436) | (ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) | (ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6) | (ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7) | (ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92))) begin
a_ce0 = ap_const_logic_1;
end else begin
a_ce0 = ap_const_logic_0;
end
end
/// a_ce1 assign process. ///
always @ (ap_sig_cseq_ST_st6_fsm_5 or ap_sig_cseq_ST_st5_fsm_4 or ap_sig_cseq_ST_st7_fsm_6 or ap_sig_cseq_ST_st8_fsm_7 or ap_sig_cseq_ST_st9_fsm_8)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5) | (ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) | (ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6) | (ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7) | (ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_8))) begin
a_ce1 = ap_const_logic_1;
end else begin
a_ce1 = ap_const_logic_0;
end
end
/// a_d0 assign process. ///
always @ (reg_597 or ap_sig_cseq_ST_st2_fsm_1 or ap_sig_cseq_ST_st93_fsm_92 or ret_fu_644_p1)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92)) begin
a_d0 = reg_597;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
a_d0 = ret_fu_644_p1;
end else begin
a_d0 = 'bx;
end
end
/// a_we0 assign process. ///
always @ (tmp_32_reg_1995 or exitcond_flatten_fu_604_p2 or ap_sig_cseq_ST_st2_fsm_1 or ap_sig_bdd_436 or ap_sig_cseq_ST_st93_fsm_92)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond_flatten_fu_604_p2) & ~ap_sig_bdd_436) | ((ap_const_lv1_0 == tmp_32_reg_1995) & (ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92)))) begin
a_we0 = ap_const_logic_1;
end else begin
a_we0 = ap_const_logic_0;
end
end
/// ap_done assign process. ///
always @ (ap_sig_cseq_ST_st96_fsm_94)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st96_fsm_94)) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_sig_cseq_ST_st96_fsm_94)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st96_fsm_94)) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp3_stg0_fsm_93 assign process. ///
always @ (ap_sig_bdd_757)
begin
if (ap_sig_bdd_757) begin
ap_sig_cseq_ST_pp3_stg0_fsm_93 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp3_stg0_fsm_93 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st10_fsm_9 assign process. ///
always @ (ap_sig_bdd_243)
begin
if (ap_sig_bdd_243) begin
ap_sig_cseq_ST_st10_fsm_9 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st10_fsm_9 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st11_fsm_10 assign process. ///
always @ (ap_sig_bdd_587)
begin
if (ap_sig_bdd_587) begin
ap_sig_cseq_ST_st11_fsm_10 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st11_fsm_10 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st12_fsm_11 assign process. ///
always @ (ap_sig_bdd_258)
begin
if (ap_sig_bdd_258) begin
ap_sig_cseq_ST_st12_fsm_11 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st12_fsm_11 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st13_fsm_12 assign process. ///
always @ (ap_sig_bdd_266)
begin
if (ap_sig_bdd_266) begin
ap_sig_cseq_ST_st13_fsm_12 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st13_fsm_12 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st14_fsm_13 assign process. ///
always @ (ap_sig_bdd_275)
begin
if (ap_sig_bdd_275) begin
ap_sig_cseq_ST_st14_fsm_13 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st14_fsm_13 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st15_fsm_14 assign process. ///
always @ (ap_sig_bdd_284)
begin
if (ap_sig_bdd_284) begin
ap_sig_cseq_ST_st15_fsm_14 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st15_fsm_14 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st16_fsm_15 assign process. ///
always @ (ap_sig_bdd_322)
begin
if (ap_sig_bdd_322) begin
ap_sig_cseq_ST_st16_fsm_15 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st16_fsm_15 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st17_fsm_16 assign process. ///
always @ (ap_sig_bdd_620)
begin
if (ap_sig_bdd_620) begin
ap_sig_cseq_ST_st17_fsm_16 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st17_fsm_16 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st18_fsm_17 assign process. ///
always @ (ap_sig_bdd_364)
begin
if (ap_sig_bdd_364) begin
ap_sig_cseq_ST_st18_fsm_17 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st18_fsm_17 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st19_fsm_18 assign process. ///
always @ (ap_sig_bdd_635)
begin
if (ap_sig_bdd_635) begin
ap_sig_cseq_ST_st19_fsm_18 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st19_fsm_18 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_136)
begin
if (ap_sig_bdd_136) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st20_fsm_19 assign process. ///
always @ (ap_sig_bdd_648)
begin
if (ap_sig_bdd_648) begin
ap_sig_cseq_ST_st20_fsm_19 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st20_fsm_19 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st21_fsm_20 assign process. ///
always @ (ap_sig_bdd_659)
begin
if (ap_sig_bdd_659) begin
ap_sig_cseq_ST_st21_fsm_20 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st21_fsm_20 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st24_fsm_23 assign process. ///
always @ (ap_sig_bdd_329)
begin
if (ap_sig_bdd_329) begin
ap_sig_cseq_ST_st24_fsm_23 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st24_fsm_23 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st25_fsm_24 assign process. ///
always @ (ap_sig_bdd_198)
begin
if (ap_sig_bdd_198) begin
ap_sig_cseq_ST_st25_fsm_24 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st25_fsm_24 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st26_fsm_25 assign process. ///
always @ (ap_sig_bdd_994)
begin
if (ap_sig_bdd_994) begin
ap_sig_cseq_ST_st26_fsm_25 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st26_fsm_25 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_431)
begin
if (ap_sig_bdd_431) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st30_fsm_29 assign process. ///
always @ (ap_sig_bdd_372)
begin
if (ap_sig_bdd_372) begin
ap_sig_cseq_ST_st30_fsm_29 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st30_fsm_29 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st31_fsm_30 assign process. ///
always @ (ap_sig_bdd_668)
begin
if (ap_sig_bdd_668) begin
ap_sig_cseq_ST_st31_fsm_30 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st31_fsm_30 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st32_fsm_31 assign process. ///
always @ (ap_sig_bdd_680)
begin
if (ap_sig_bdd_680) begin
ap_sig_cseq_ST_st32_fsm_31 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st32_fsm_31 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st36_fsm_35 assign process. ///
always @ (ap_sig_bdd_690)
begin
if (ap_sig_bdd_690) begin
ap_sig_cseq_ST_st36_fsm_35 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st36_fsm_35 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st37_fsm_36 assign process. ///
always @ (ap_sig_bdd_701)
begin
if (ap_sig_bdd_701) begin
ap_sig_cseq_ST_st37_fsm_36 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st37_fsm_36 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st3_fsm_2 assign process. ///
always @ (ap_sig_bdd_453)
begin
if (ap_sig_bdd_453) begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st41_fsm_40 assign process. ///
always @ (ap_sig_bdd_338)
begin
if (ap_sig_bdd_338) begin
ap_sig_cseq_ST_st41_fsm_40 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st41_fsm_40 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st42_fsm_41 assign process. ///
always @ (ap_sig_bdd_209)
begin
if (ap_sig_bdd_209) begin
ap_sig_cseq_ST_st42_fsm_41 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st42_fsm_41 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st43_fsm_42 assign process. ///
always @ (ap_sig_bdd_1001)
begin
if (ap_sig_bdd_1001) begin
ap_sig_cseq_ST_st43_fsm_42 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st43_fsm_42 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st47_fsm_46 assign process. ///
always @ (ap_sig_bdd_381)
begin
if (ap_sig_bdd_381) begin
ap_sig_cseq_ST_st47_fsm_46 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st47_fsm_46 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st48_fsm_47 assign process. ///
always @ (ap_sig_bdd_710)
begin
if (ap_sig_bdd_710) begin
ap_sig_cseq_ST_st48_fsm_47 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st48_fsm_47 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st49_fsm_48 assign process. ///
always @ (ap_sig_bdd_721)
begin
if (ap_sig_bdd_721) begin
ap_sig_cseq_ST_st49_fsm_48 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st49_fsm_48 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st4_fsm_3 assign process. ///
always @ (ap_sig_bdd_474)
begin
if (ap_sig_bdd_474) begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st53_fsm_52 assign process. ///
always @ (ap_sig_bdd_346)
begin
if (ap_sig_bdd_346) begin
ap_sig_cseq_ST_st53_fsm_52 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st53_fsm_52 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st54_fsm_53 assign process. ///
always @ (ap_sig_bdd_220)
begin
if (ap_sig_bdd_220) begin
ap_sig_cseq_ST_st54_fsm_53 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st54_fsm_53 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st55_fsm_54 assign process. ///
always @ (ap_sig_bdd_1009)
begin
if (ap_sig_bdd_1009) begin
ap_sig_cseq_ST_st55_fsm_54 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st55_fsm_54 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st59_fsm_58 assign process. ///
always @ (ap_sig_bdd_390)
begin
if (ap_sig_bdd_390) begin
ap_sig_cseq_ST_st59_fsm_58 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st59_fsm_58 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st5_fsm_4 assign process. ///
always @ (ap_sig_bdd_485)
begin
if (ap_sig_bdd_485) begin
ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st60_fsm_59 assign process. ///
always @ (ap_sig_bdd_411)
begin
if (ap_sig_bdd_411) begin
ap_sig_cseq_ST_st60_fsm_59 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st60_fsm_59 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st61_fsm_60 assign process. ///
always @ (ap_sig_bdd_931)
begin
if (ap_sig_bdd_931) begin
ap_sig_cseq_ST_st61_fsm_60 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st61_fsm_60 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st65_fsm_64 assign process. ///
always @ (ap_sig_bdd_354)
begin
if (ap_sig_bdd_354) begin
ap_sig_cseq_ST_st65_fsm_64 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st65_fsm_64 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st66_fsm_65 assign process. ///
always @ (ap_sig_bdd_955)
begin
if (ap_sig_bdd_955) begin
ap_sig_cseq_ST_st66_fsm_65 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st66_fsm_65 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st69_fsm_68 assign process. ///
always @ (ap_sig_bdd_729)
begin
if (ap_sig_bdd_729) begin
ap_sig_cseq_ST_st69_fsm_68 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st69_fsm_68 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st6_fsm_5 assign process. ///
always @ (ap_sig_bdd_187)
begin
if (ap_sig_bdd_187) begin
ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st70_fsm_69 assign process. ///
always @ (ap_sig_bdd_938)
begin
if (ap_sig_bdd_938) begin
ap_sig_cseq_ST_st70_fsm_69 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st70_fsm_69 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st74_fsm_73 assign process. ///
always @ (ap_sig_bdd_305)
begin
if (ap_sig_bdd_305) begin
ap_sig_cseq_ST_st74_fsm_73 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st74_fsm_73 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st75_fsm_74 assign process. ///
always @ (ap_sig_bdd_945)
begin
if (ap_sig_bdd_945) begin
ap_sig_cseq_ST_st75_fsm_74 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st75_fsm_74 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st79_fsm_78 assign process. ///
always @ (ap_sig_bdd_313)
begin
if (ap_sig_bdd_313) begin
ap_sig_cseq_ST_st79_fsm_78 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st79_fsm_78 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st7_fsm_6 assign process. ///
always @ (ap_sig_bdd_525)
begin
if (ap_sig_bdd_525) begin
ap_sig_cseq_ST_st7_fsm_6 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st7_fsm_6 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st80_fsm_79 assign process. ///
always @ (ap_sig_bdd_228)
begin
if (ap_sig_bdd_228) begin
ap_sig_cseq_ST_st80_fsm_79 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st80_fsm_79 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st81_fsm_80 assign process. ///
always @ (ap_sig_bdd_1031)
begin
if (ap_sig_bdd_1031) begin
ap_sig_cseq_ST_st81_fsm_80 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st81_fsm_80 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st86_fsm_85 assign process. ///
always @ (ap_sig_bdd_292)
begin
if (ap_sig_bdd_292) begin
ap_sig_cseq_ST_st86_fsm_85 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st86_fsm_85 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st87_fsm_86 assign process. ///
always @ (ap_sig_bdd_1017)
begin
if (ap_sig_bdd_1017) begin
ap_sig_cseq_ST_st87_fsm_86 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st87_fsm_86 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st8_fsm_7 assign process. ///
always @ (ap_sig_bdd_549)
begin
if (ap_sig_bdd_549) begin
ap_sig_cseq_ST_st8_fsm_7 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st8_fsm_7 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st91_fsm_90 assign process. ///
always @ (ap_sig_bdd_398)
begin
if (ap_sig_bdd_398) begin
ap_sig_cseq_ST_st91_fsm_90 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st91_fsm_90 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st92_fsm_91 assign process. ///
always @ (ap_sig_bdd_418)
begin
if (ap_sig_bdd_418) begin
ap_sig_cseq_ST_st92_fsm_91 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st92_fsm_91 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st93_fsm_92 assign process. ///
always @ (ap_sig_bdd_738)
begin
if (ap_sig_bdd_738) begin
ap_sig_cseq_ST_st93_fsm_92 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st93_fsm_92 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st96_fsm_94 assign process. ///
always @ (ap_sig_bdd_1778)
begin
if (ap_sig_bdd_1778) begin
ap_sig_cseq_ST_st96_fsm_94 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st96_fsm_94 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st9_fsm_8 assign process. ///
always @ (ap_sig_bdd_566)
begin
if (ap_sig_bdd_566) begin
ap_sig_cseq_ST_st9_fsm_8 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st9_fsm_8 = ap_const_logic_0;
end
end
/// ap_sig_ioackin_OUTPUT_STREAM_TREADY assign process. ///
always @ (OUTPUT_STREAM_TREADY or ap_reg_ioackin_OUTPUT_STREAM_TREADY)
begin
if ((ap_const_logic_0 == ap_reg_ioackin_OUTPUT_STREAM_TREADY)) begin
ap_sig_ioackin_OUTPUT_STREAM_TREADY = OUTPUT_STREAM_TREADY;
end else begin
ap_sig_ioackin_OUTPUT_STREAM_TREADY = ap_const_logic_1;
end
end
/// b_address0 assign process. ///
always @ (ap_sig_cseq_ST_st13_fsm_12 or ap_sig_cseq_ST_st3_fsm_2 or tmp_89_reg_1965 or tmp_6_fu_749_p1)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
b_address0 = tmp_6_fu_749_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_12)) begin
b_address0 = tmp_89_reg_1965;
end else begin
b_address0 = 'bx;
end
end
/// b_ce0 assign process. ///
always @ (ap_sig_cseq_ST_st13_fsm_12 or ap_sig_cseq_ST_st3_fsm_2 or ap_sig_bdd_457)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_12) | ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_457))) begin
b_ce0 = ap_const_logic_1;
end else begin
b_ce0 = ap_const_logic_0;
end
end
/// b_we0 assign process. ///
always @ (exitcond_flatten8_fu_682_p2 or ap_sig_cseq_ST_st3_fsm_2 or ap_sig_bdd_457)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == exitcond_flatten8_fu_682_p2) & ~ap_sig_bdd_457)) begin
b_we0 = ap_const_logic_1;
end else begin
b_we0 = ap_const_logic_0;
end
end
/// grp_fu_520_opcode assign process. ///
always @ (tmp_23_reg_1793 or tmp_52_reg_1810 or ap_sig_cseq_ST_st12_fsm_11 or ap_sig_cseq_ST_st11_fsm_10 or ap_sig_cseq_ST_st20_fsm_19 or ap_sig_cseq_ST_st32_fsm_31 or ap_sig_cseq_ST_st37_fsm_36 or ap_sig_cseq_ST_st49_fsm_48 or ap_sig_cseq_ST_st61_fsm_60 or ap_sig_cseq_ST_st70_fsm_69 or ap_sig_cseq_ST_st75_fsm_74)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_10) | (ap_const_logic_1 == ap_sig_cseq_ST_st70_fsm_69) | (ap_const_logic_1 == ap_sig_cseq_ST_st75_fsm_74))) begin
grp_fu_520_opcode = ap_const_lv2_1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_11) | ((ap_const_lv1_0 == tmp_23_reg_1793) & (ap_const_logic_1 == ap_sig_cseq_ST_st20_fsm_19)) | ((ap_const_lv1_0 == tmp_52_reg_1810) & (ap_const_logic_1 == ap_sig_cseq_ST_st32_fsm_31)) | (ap_const_logic_1 == ap_sig_cseq_ST_st37_fsm_36) | (ap_const_logic_1 == ap_sig_cseq_ST_st49_fsm_48) | (ap_const_logic_1 == ap_sig_cseq_ST_st61_fsm_60))) begin
grp_fu_520_opcode = ap_const_lv2_0;
end else begin
grp_fu_520_opcode = 'bx;
end
end
/// grp_fu_520_p0 assign process. ///
always @ (ap_sig_cseq_ST_st12_fsm_11 or reg_578 or a_load_reg_1988 or ap_sig_cseq_ST_st11_fsm_10 or sum_4_i_i_reg_2089 or ap_sig_cseq_ST_st20_fsm_19 or x_assign_2_reg_2111 or sum_4_i_i_0_2_reg_2121 or ap_sig_cseq_ST_st32_fsm_31 or sum_4_i_i_1_reg_2137 or ap_sig_cseq_ST_st37_fsm_36 or sum_4_i_i_2_reg_2152 or ap_sig_cseq_ST_st49_fsm_48 or tmp_27_reg_2167 or ap_sig_cseq_ST_st61_fsm_60 or ap_sig_cseq_ST_st70_fsm_69 or ap_sig_cseq_ST_st75_fsm_74)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st75_fsm_74)) begin
grp_fu_520_p0 = reg_578;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st70_fsm_69)) begin
grp_fu_520_p0 = tmp_27_reg_2167;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st61_fsm_60)) begin
grp_fu_520_p0 = x_assign_2_reg_2111;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st49_fsm_48)) begin
grp_fu_520_p0 = sum_4_i_i_2_reg_2152;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st37_fsm_36)) begin
grp_fu_520_p0 = sum_4_i_i_1_reg_2137;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st32_fsm_31)) begin
grp_fu_520_p0 = sum_4_i_i_0_2_reg_2121;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st20_fsm_19)) begin
grp_fu_520_p0 = sum_4_i_i_reg_2089;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_11)) begin
grp_fu_520_p0 = a_load_reg_1988;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_10)) begin
grp_fu_520_p0 = ap_const_lv32_3F800000;
end else begin
grp_fu_520_p0 = 'bx;
end
end
/// grp_fu_520_p1 assign process. ///
always @ (ap_sig_cseq_ST_st12_fsm_11 or reg_597 or a_load_reg_1988 or ap_sig_cseq_ST_st11_fsm_10 or tmp_14_reg_2019 or x_assign_6_0_1_fu_1348_p3 or ap_sig_cseq_ST_st20_fsm_19 or tmp_31_reg_2116 or x_assign_6_1_fu_1455_p3 or ap_sig_cseq_ST_st32_fsm_31 or x_assign_6_1_2_fu_1508_p3 or ap_sig_cseq_ST_st37_fsm_36 or x_assign_6_2_1_fu_1562_p3 or ap_sig_cseq_ST_st49_fsm_48 or ap_sig_cseq_ST_st61_fsm_60 or ap_sig_cseq_ST_st70_fsm_69 or ap_sig_cseq_ST_st75_fsm_74)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st75_fsm_74)) begin
grp_fu_520_p1 = tmp_31_reg_2116;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st70_fsm_69)) begin
grp_fu_520_p1 = tmp_14_reg_2019;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st61_fsm_60)) begin
grp_fu_520_p1 = reg_597;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st49_fsm_48)) begin
grp_fu_520_p1 = x_assign_6_2_1_fu_1562_p3;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st37_fsm_36)) begin
grp_fu_520_p1 = x_assign_6_1_2_fu_1508_p3;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st32_fsm_31)) begin
grp_fu_520_p1 = x_assign_6_1_fu_1455_p3;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st20_fsm_19)) begin
grp_fu_520_p1 = x_assign_6_0_1_fu_1348_p3;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_11)) begin
grp_fu_520_p1 = ap_const_lv32_3F800000;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_10)) begin
grp_fu_520_p1 = a_load_reg_1988;
end else begin
grp_fu_520_p1 = 'bx;
end
end
/// grp_fu_526_p0 assign process. ///
always @ (ap_sig_cseq_ST_st10_fsm_9 or reg_578 or reg_585 or ap_sig_cseq_ST_st18_fsm_17 or a_q1 or ap_sig_cseq_ST_st66_fsm_65)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st66_fsm_65)) begin
grp_fu_526_p0 = reg_578;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st18_fsm_17)) begin
grp_fu_526_p0 = reg_585;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9)) begin
grp_fu_526_p0 = a_q1;
end else begin
grp_fu_526_p0 = 'bx;
end
end
/// grp_fu_526_p1 assign process. ///
always @ (ap_sig_cseq_ST_st10_fsm_9 or reg_585 or ap_sig_cseq_ST_st18_fsm_17 or output_0_i13_i_i_fu_1293_p3 or ap_sig_cseq_ST_st66_fsm_65)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st66_fsm_65)) begin
grp_fu_526_p1 = reg_585;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st18_fsm_17)) begin
grp_fu_526_p1 = output_0_i13_i_i_fu_1293_p3;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9)) begin
grp_fu_526_p1 = ap_const_lv32_41200000;
end else begin
grp_fu_526_p1 = 'bx;
end
end
/// grp_fu_535_p0 assign process. ///
always @ (ap_sig_cseq_ST_st6_fsm_5 or ap_sig_cseq_ST_st25_fsm_24 or ap_sig_cseq_ST_st42_fsm_41 or ap_sig_cseq_ST_st54_fsm_53 or ap_sig_cseq_ST_st80_fsm_79 or tmp_32_reg_1995 or ap_sig_cseq_ST_st10_fsm_9 or tmp_32_fu_1013_p2 or reg_578 or reg_585 or a_q0 or a_q1 or ap_sig_cseq_ST_st7_fsm_6 or ap_sig_cseq_ST_st8_fsm_7 or ap_sig_cseq_ST_st9_fsm_8 or sum_4_i_i_0_1_fu_1402_p3)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st80_fsm_79) & (ap_const_lv1_0 == tmp_32_reg_1995)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st80_fsm_79) & ~(ap_const_lv1_0 == tmp_32_reg_1995)))) begin
grp_fu_535_p0 = reg_578;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st42_fsm_41) | (ap_const_logic_1 == ap_sig_cseq_ST_st54_fsm_53))) begin
grp_fu_535_p0 = reg_585;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st25_fsm_24)) begin
grp_fu_535_p0 = sum_4_i_i_0_1_fu_1402_p3;
end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9) & (ap_const_lv1_0 == tmp_32_fu_1013_p2)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9) & ~(ap_const_lv1_0 == tmp_32_fu_1013_p2)) | (ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6))) begin
grp_fu_535_p0 = a_q1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5) | (ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7) | (ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_8))) begin
grp_fu_535_p0 = a_q0;
end else begin
grp_fu_535_p0 = 'bx;
end
end
/// grp_fu_540_opcode assign process. ///
always @ (tmp_11_reg_1778 or tmp_23_reg_1793 or tmp_52_reg_1810 or ap_sig_cseq_ST_st10_fsm_9 or ap_sig_cseq_ST_st12_fsm_11 or ap_sig_cseq_ST_st13_fsm_12 or ap_sig_cseq_ST_st14_fsm_13 or ap_sig_cseq_ST_st15_fsm_14 or ap_sig_cseq_ST_st16_fsm_15 or ap_sig_cseq_ST_st7_fsm_6 or ap_sig_cseq_ST_st8_fsm_7 or ap_sig_cseq_ST_st9_fsm_8 or ap_sig_cseq_ST_st11_fsm_10 or ap_sig_cseq_ST_st17_fsm_16 or ap_sig_cseq_ST_st19_fsm_18)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14) | (ap_const_logic_1 == ap_sig_cseq_ST_st16_fsm_15) | (ap_const_logic_1 == ap_sig_cseq_ST_st17_fsm_16))) begin
grp_fu_540_opcode = ap_const_lv5_1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_12) | (ap_const_logic_1 == ap_sig_cseq_ST_st14_fsm_13) | ((tmp_11_reg_1778 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6)) | ((ap_const_lv1_0 == tmp_23_reg_1793) & (ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7)) | ((ap_const_lv1_0 == tmp_23_reg_1793) & (ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_8)) | ((ap_const_lv1_0 == tmp_52_reg_1810) & (ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9)) | (ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_10) | ((ap_const_lv1_0 == tmp_52_reg_1810) & (ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_11)) | (ap_const_logic_1 == ap_sig_cseq_ST_st19_fsm_18))) begin
grp_fu_540_opcode = ap_const_lv5_2;
end else begin
grp_fu_540_opcode = 'bx;
end
end
/// grp_fu_540_p0 assign process. ///
always @ (ap_sig_cseq_ST_st10_fsm_9 or ap_sig_cseq_ST_st12_fsm_11 or ap_sig_cseq_ST_st13_fsm_12 or ap_sig_cseq_ST_st14_fsm_13 or ap_sig_cseq_ST_st15_fsm_14 or ap_sig_cseq_ST_st16_fsm_15 or a_load_1_reg_1821 or a_load_2_reg_1827 or ap_sig_cseq_ST_st7_fsm_6 or a_load_3_reg_1866 or a_load_4_reg_1877 or ap_sig_cseq_ST_st8_fsm_7 or a_load_5_reg_1914 or a_load_6_reg_1921 or ap_sig_cseq_ST_st9_fsm_8 or a_load_7_reg_1947 or a_load_8_reg_1954 or ap_sig_cseq_ST_st11_fsm_10 or b_load_reg_2039 or ap_sig_cseq_ST_st17_fsm_16 or x_assign_1_reg_2077 or ap_sig_cseq_ST_st19_fsm_18)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st19_fsm_18)) begin
grp_fu_540_p0 = x_assign_1_reg_2077;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14) | (ap_const_logic_1 == ap_sig_cseq_ST_st16_fsm_15) | (ap_const_logic_1 == ap_sig_cseq_ST_st17_fsm_16))) begin
grp_fu_540_p0 = b_load_reg_2039;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st14_fsm_13)) begin
grp_fu_540_p0 = a_load_8_reg_1954;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_12)) begin
grp_fu_540_p0 = a_load_7_reg_1947;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_11)) begin
grp_fu_540_p0 = a_load_6_reg_1921;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_10)) begin
grp_fu_540_p0 = a_load_5_reg_1914;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9)) begin
grp_fu_540_p0 = a_load_4_reg_1877;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_8)) begin
grp_fu_540_p0 = a_load_3_reg_1866;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7)) begin
grp_fu_540_p0 = a_load_2_reg_1827;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6)) begin
grp_fu_540_p0 = a_load_1_reg_1821;
end else begin
grp_fu_540_p0 = 'bx;
end
end
/// grp_fu_540_p1 assign process. ///
always @ (ap_sig_cseq_ST_st10_fsm_9 or ap_sig_cseq_ST_st12_fsm_11 or ap_sig_cseq_ST_st13_fsm_12 or ap_sig_cseq_ST_st14_fsm_13 or ap_sig_cseq_ST_st15_fsm_14 or ap_sig_cseq_ST_st16_fsm_15 or ap_sig_cseq_ST_st7_fsm_6 or ap_sig_cseq_ST_st8_fsm_7 or ap_sig_cseq_ST_st9_fsm_8 or ap_sig_cseq_ST_st11_fsm_10 or ap_sig_cseq_ST_st17_fsm_16 or ap_sig_cseq_ST_st19_fsm_18)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st17_fsm_16)) begin
grp_fu_540_p1 = ap_const_lv32_40800000;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st16_fsm_15)) begin
grp_fu_540_p1 = ap_const_lv32_40E00000;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9) | (ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_11) | (ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_12) | (ap_const_logic_1 == ap_sig_cseq_ST_st14_fsm_13) | (ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14) | (ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6) | (ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7) | (ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_8) | (ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_10) | (ap_const_logic_1 == ap_sig_cseq_ST_st19_fsm_18))) begin
grp_fu_540_p1 = ap_const_lv32_0;
end else begin
grp_fu_540_p1 = 'bx;
end
end
/// grp_fu_547_p0 assign process. ///
always @ (reg_562 or tmp_32_reg_1995 or reg_568 or ap_sig_cseq_ST_st14_fsm_13 or tmp_21_reg_2009 or ap_sig_cseq_ST_st26_fsm_25 or ap_sig_cseq_ST_st43_fsm_42 or ap_sig_cseq_ST_st55_fsm_54 or ap_sig_cseq_ST_st87_fsm_86)
begin
if ((((ap_const_lv1_0 == tmp_32_reg_1995) & (ap_const_logic_1 == ap_sig_cseq_ST_st87_fsm_86)) | (~(ap_const_lv1_0 == tmp_32_reg_1995) & (ap_const_logic_1 == ap_sig_cseq_ST_st87_fsm_86)))) begin
grp_fu_547_p0 = reg_568;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st26_fsm_25) | (ap_const_logic_1 == ap_sig_cseq_ST_st43_fsm_42) | (ap_const_logic_1 == ap_sig_cseq_ST_st55_fsm_54))) begin
grp_fu_547_p0 = reg_562;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st14_fsm_13)) begin
grp_fu_547_p0 = tmp_21_reg_2009;
end else begin
grp_fu_547_p0 = 'bx;
end
end
/// grp_fu_547_p1 assign process. ///
always @ (tmp_32_reg_1995 or reg_573 or ap_sig_cseq_ST_st14_fsm_13 or tmp_49_0_2_reg_2029 or tmp_49_2_reg_2045 or tmp_49_2_2_reg_2055 or ap_sig_cseq_ST_st26_fsm_25 or ap_sig_cseq_ST_st43_fsm_42 or ap_sig_cseq_ST_st55_fsm_54 or ap_sig_cseq_ST_st87_fsm_86)
begin
if ((((ap_const_lv1_0 == tmp_32_reg_1995) & (ap_const_logic_1 == ap_sig_cseq_ST_st87_fsm_86)) | (~(ap_const_lv1_0 == tmp_32_reg_1995) & (ap_const_logic_1 == ap_sig_cseq_ST_st87_fsm_86)))) begin
grp_fu_547_p1 = reg_573;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st55_fsm_54)) begin
grp_fu_547_p1 = tmp_49_2_2_reg_2055;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st43_fsm_42)) begin
grp_fu_547_p1 = tmp_49_2_reg_2045;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st26_fsm_25)) begin
grp_fu_547_p1 = tmp_49_0_2_reg_2029;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st14_fsm_13)) begin
grp_fu_547_p1 = ap_const_lv64_0;
end else begin
grp_fu_547_p1 = 'bx;
end
end
/// grp_fu_552_p0 assign process. ///
always @ (reg_562 or tmp_32_reg_1995 or ap_sig_cseq_ST_st10_fsm_9 or ap_sig_cseq_ST_st7_fsm_6 or tmp_48_0_2_reg_1872 or ap_sig_cseq_ST_st8_fsm_7 or tmp_48_2_reg_1927 or ap_sig_cseq_ST_st9_fsm_8 or tmp_48_2_2_reg_1960 or ap_sig_cseq_ST_st81_fsm_80)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9)) begin
grp_fu_552_p0 = tmp_48_2_2_reg_1960;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_8)) begin
grp_fu_552_p0 = tmp_48_2_reg_1927;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7)) begin
grp_fu_552_p0 = tmp_48_0_2_reg_1872;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6) | ((ap_const_lv1_0 == tmp_32_reg_1995) & (ap_const_logic_1 == ap_sig_cseq_ST_st81_fsm_80)) | (~(ap_const_lv1_0 == tmp_32_reg_1995) & (ap_const_logic_1 == ap_sig_cseq_ST_st81_fsm_80)))) begin
grp_fu_552_p0 = reg_562;
end else begin
grp_fu_552_p0 = 'bx;
end
end
/// grp_fu_552_p1 assign process. ///
always @ (tmp_32_reg_1995 or ap_sig_cseq_ST_st10_fsm_9 or ap_sig_cseq_ST_st7_fsm_6 or ap_sig_cseq_ST_st8_fsm_7 or ap_sig_cseq_ST_st9_fsm_8 or ap_sig_cseq_ST_st81_fsm_80)
begin
if ((((ap_const_lv1_0 == tmp_32_reg_1995) & (ap_const_logic_1 == ap_sig_cseq_ST_st81_fsm_80)) | (~(ap_const_lv1_0 == tmp_32_reg_1995) & (ap_const_logic_1 == ap_sig_cseq_ST_st81_fsm_80)))) begin
grp_fu_552_p1 = ap_const_lv64_3F847AE147AE147B;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9) | (ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6) | (ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7) | (ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_8))) begin
grp_fu_552_p1 = ap_const_lv64_3FE6A09EDBF8B9BB;
end else begin
grp_fu_552_p1 = 'bx;
end
end
/// i4_0_i_phi_fu_501_p4 assign process. ///
always @ (i4_0_i_reg_497 or exitcond_flatten3_reg_2201 or ap_sig_cseq_ST_pp3_stg0_fsm_93 or ap_reg_ppiten_pp3_it1 or i4_0_i_mid2_reg_2210)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_93) & (ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1))) begin
i4_0_i_phi_fu_501_p4 = i4_0_i_mid2_reg_2210;
end else begin
i4_0_i_phi_fu_501_p4 = i4_0_i_reg_497;
end
end
/// out_address0 assign process. ///
always @ (tmp_89_reg_1965 or ap_sig_cseq_ST_st93_fsm_92 or ap_sig_cseq_ST_pp3_stg0_fsm_93 or ap_reg_ppiten_pp3_it0 or tmp_103_fu_1695_p1)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92)) begin
out_address0 = tmp_89_reg_1965;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_93) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0))) begin
out_address0 = tmp_103_fu_1695_p1;
end else begin
out_address0 = 'bx;
end
end
/// out_ce0 assign process. ///
always @ (ap_sig_cseq_ST_st93_fsm_92 or exitcond_flatten3_reg_2201 or ap_sig_cseq_ST_pp3_stg0_fsm_93 or ap_reg_ppiten_pp3_it0 or ap_sig_ioackin_OUTPUT_STREAM_TREADY or ap_reg_ppiten_pp3_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_93) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & ~((ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1))))) begin
out_ce0 = ap_const_logic_1;
end else begin
out_ce0 = ap_const_logic_0;
end
end
/// out_we0 assign process. ///
always @ (tmp_32_reg_1995 or ap_sig_cseq_ST_st93_fsm_92)
begin
if ((~(ap_const_lv1_0 == tmp_32_reg_1995) & (ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92))) begin
out_we0 = ap_const_logic_1;
end else begin
out_we0 = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_start or ap_CS_fsm or exitcond_flatten_fu_604_p2 or ap_sig_bdd_436 or exitcond_flatten8_fu_682_p2 or ap_sig_bdd_457 or exitcond_flatten2_fu_1605_p2 or exitcond_flatten3_fu_1611_p2 or exitcond_flatten3_reg_2201 or ap_reg_ppiten_pp3_it0 or ap_sig_ioackin_OUTPUT_STREAM_TREADY or ap_reg_ppiten_pp3_it1)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~(ap_start == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if (((ap_const_lv1_0 == exitcond_flatten_fu_604_p2) & ~ap_sig_bdd_436)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else if ((~ap_sig_bdd_436 & ~(ap_const_lv1_0 == exitcond_flatten_fu_604_p2))) begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end else begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
end
ap_ST_st3_fsm_2 :
begin
if (((ap_const_lv1_0 == exitcond_flatten8_fu_682_p2) & ~ap_sig_bdd_457)) begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end else if ((~ap_sig_bdd_457 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_682_p2))) begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end else begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
end
ap_ST_st4_fsm_3 :
begin
ap_NS_fsm = ap_ST_st5_fsm_4;
end
ap_ST_st5_fsm_4 :
begin
ap_NS_fsm = ap_ST_st6_fsm_5;
end
ap_ST_st6_fsm_5 :
begin
ap_NS_fsm = ap_ST_st7_fsm_6;
end
ap_ST_st7_fsm_6 :
begin
ap_NS_fsm = ap_ST_st8_fsm_7;
end
ap_ST_st8_fsm_7 :
begin
ap_NS_fsm = ap_ST_st9_fsm_8;
end
ap_ST_st9_fsm_8 :
begin
ap_NS_fsm = ap_ST_st10_fsm_9;
end
ap_ST_st10_fsm_9 :
begin
ap_NS_fsm = ap_ST_st11_fsm_10;
end
ap_ST_st11_fsm_10 :
begin
ap_NS_fsm = ap_ST_st12_fsm_11;
end
ap_ST_st12_fsm_11 :
begin
ap_NS_fsm = ap_ST_st13_fsm_12;
end
ap_ST_st13_fsm_12 :
begin
ap_NS_fsm = ap_ST_st14_fsm_13;
end
ap_ST_st14_fsm_13 :
begin
ap_NS_fsm = ap_ST_st15_fsm_14;
end
ap_ST_st15_fsm_14 :
begin
ap_NS_fsm = ap_ST_st16_fsm_15;
end
ap_ST_st16_fsm_15 :
begin
ap_NS_fsm = ap_ST_st17_fsm_16;
end
ap_ST_st17_fsm_16 :
begin
ap_NS_fsm = ap_ST_st18_fsm_17;
end
ap_ST_st18_fsm_17 :
begin
ap_NS_fsm = ap_ST_st19_fsm_18;
end
ap_ST_st19_fsm_18 :
begin
ap_NS_fsm = ap_ST_st20_fsm_19;
end
ap_ST_st20_fsm_19 :
begin
ap_NS_fsm = ap_ST_st21_fsm_20;
end
ap_ST_st21_fsm_20 :
begin
ap_NS_fsm = ap_ST_st22_fsm_21;
end
ap_ST_st22_fsm_21 :
begin
ap_NS_fsm = ap_ST_st23_fsm_22;
end
ap_ST_st23_fsm_22 :
begin
ap_NS_fsm = ap_ST_st24_fsm_23;
end
ap_ST_st24_fsm_23 :
begin
ap_NS_fsm = ap_ST_st25_fsm_24;
end
ap_ST_st25_fsm_24 :
begin
ap_NS_fsm = ap_ST_st26_fsm_25;
end
ap_ST_st26_fsm_25 :
begin
ap_NS_fsm = ap_ST_st27_fsm_26;
end
ap_ST_st27_fsm_26 :
begin
ap_NS_fsm = ap_ST_st28_fsm_27;
end
ap_ST_st28_fsm_27 :
begin
ap_NS_fsm = ap_ST_st29_fsm_28;
end
ap_ST_st29_fsm_28 :
begin
ap_NS_fsm = ap_ST_st30_fsm_29;
end
ap_ST_st30_fsm_29 :
begin
ap_NS_fsm = ap_ST_st31_fsm_30;
end
ap_ST_st31_fsm_30 :
begin
ap_NS_fsm = ap_ST_st32_fsm_31;
end
ap_ST_st32_fsm_31 :
begin
ap_NS_fsm = ap_ST_st33_fsm_32;
end
ap_ST_st33_fsm_32 :
begin
ap_NS_fsm = ap_ST_st34_fsm_33;
end
ap_ST_st34_fsm_33 :
begin
ap_NS_fsm = ap_ST_st35_fsm_34;
end
ap_ST_st35_fsm_34 :
begin
ap_NS_fsm = ap_ST_st36_fsm_35;
end
ap_ST_st36_fsm_35 :
begin
ap_NS_fsm = ap_ST_st37_fsm_36;
end
ap_ST_st37_fsm_36 :
begin
ap_NS_fsm = ap_ST_st38_fsm_37;
end
ap_ST_st38_fsm_37 :
begin
ap_NS_fsm = ap_ST_st39_fsm_38;
end
ap_ST_st39_fsm_38 :
begin
ap_NS_fsm = ap_ST_st40_fsm_39;
end
ap_ST_st40_fsm_39 :
begin
ap_NS_fsm = ap_ST_st41_fsm_40;
end
ap_ST_st41_fsm_40 :
begin
ap_NS_fsm = ap_ST_st42_fsm_41;
end
ap_ST_st42_fsm_41 :
begin
ap_NS_fsm = ap_ST_st43_fsm_42;
end
ap_ST_st43_fsm_42 :
begin
ap_NS_fsm = ap_ST_st44_fsm_43;
end
ap_ST_st44_fsm_43 :
begin
ap_NS_fsm = ap_ST_st45_fsm_44;
end
ap_ST_st45_fsm_44 :
begin
ap_NS_fsm = ap_ST_st46_fsm_45;
end
ap_ST_st46_fsm_45 :
begin
ap_NS_fsm = ap_ST_st47_fsm_46;
end
ap_ST_st47_fsm_46 :
begin
ap_NS_fsm = ap_ST_st48_fsm_47;
end
ap_ST_st48_fsm_47 :
begin
ap_NS_fsm = ap_ST_st49_fsm_48;
end
ap_ST_st49_fsm_48 :
begin
ap_NS_fsm = ap_ST_st50_fsm_49;
end
ap_ST_st50_fsm_49 :
begin
ap_NS_fsm = ap_ST_st51_fsm_50;
end
ap_ST_st51_fsm_50 :
begin
ap_NS_fsm = ap_ST_st52_fsm_51;
end
ap_ST_st52_fsm_51 :
begin
ap_NS_fsm = ap_ST_st53_fsm_52;
end
ap_ST_st53_fsm_52 :
begin
ap_NS_fsm = ap_ST_st54_fsm_53;
end
ap_ST_st54_fsm_53 :
begin
ap_NS_fsm = ap_ST_st55_fsm_54;
end
ap_ST_st55_fsm_54 :
begin
ap_NS_fsm = ap_ST_st56_fsm_55;
end
ap_ST_st56_fsm_55 :
begin
ap_NS_fsm = ap_ST_st57_fsm_56;
end
ap_ST_st57_fsm_56 :
begin
ap_NS_fsm = ap_ST_st58_fsm_57;
end
ap_ST_st58_fsm_57 :
begin
ap_NS_fsm = ap_ST_st59_fsm_58;
end
ap_ST_st59_fsm_58 :
begin
ap_NS_fsm = ap_ST_st60_fsm_59;
end
ap_ST_st60_fsm_59 :
begin
ap_NS_fsm = ap_ST_st61_fsm_60;
end
ap_ST_st61_fsm_60 :
begin
ap_NS_fsm = ap_ST_st62_fsm_61;
end
ap_ST_st62_fsm_61 :
begin
ap_NS_fsm = ap_ST_st63_fsm_62;
end
ap_ST_st63_fsm_62 :
begin
ap_NS_fsm = ap_ST_st64_fsm_63;
end
ap_ST_st64_fsm_63 :
begin
ap_NS_fsm = ap_ST_st65_fsm_64;
end
ap_ST_st65_fsm_64 :
begin
ap_NS_fsm = ap_ST_st66_fsm_65;
end
ap_ST_st66_fsm_65 :
begin
ap_NS_fsm = ap_ST_st67_fsm_66;
end
ap_ST_st67_fsm_66 :
begin
ap_NS_fsm = ap_ST_st68_fsm_67;
end
ap_ST_st68_fsm_67 :
begin
ap_NS_fsm = ap_ST_st69_fsm_68;
end
ap_ST_st69_fsm_68 :
begin
ap_NS_fsm = ap_ST_st70_fsm_69;
end
ap_ST_st70_fsm_69 :
begin
ap_NS_fsm = ap_ST_st71_fsm_70;
end
ap_ST_st71_fsm_70 :
begin
ap_NS_fsm = ap_ST_st72_fsm_71;
end
ap_ST_st72_fsm_71 :
begin
ap_NS_fsm = ap_ST_st73_fsm_72;
end
ap_ST_st73_fsm_72 :
begin
ap_NS_fsm = ap_ST_st74_fsm_73;
end
ap_ST_st74_fsm_73 :
begin
ap_NS_fsm = ap_ST_st75_fsm_74;
end
ap_ST_st75_fsm_74 :
begin
ap_NS_fsm = ap_ST_st76_fsm_75;
end
ap_ST_st76_fsm_75 :
begin
ap_NS_fsm = ap_ST_st77_fsm_76;
end
ap_ST_st77_fsm_76 :
begin
ap_NS_fsm = ap_ST_st78_fsm_77;
end
ap_ST_st78_fsm_77 :
begin
ap_NS_fsm = ap_ST_st79_fsm_78;
end
ap_ST_st79_fsm_78 :
begin
ap_NS_fsm = ap_ST_st80_fsm_79;
end
ap_ST_st80_fsm_79 :
begin
ap_NS_fsm = ap_ST_st81_fsm_80;
end
ap_ST_st81_fsm_80 :
begin
ap_NS_fsm = ap_ST_st82_fsm_81;
end
ap_ST_st82_fsm_81 :
begin
ap_NS_fsm = ap_ST_st83_fsm_82;
end
ap_ST_st83_fsm_82 :
begin
ap_NS_fsm = ap_ST_st84_fsm_83;
end
ap_ST_st84_fsm_83 :
begin
ap_NS_fsm = ap_ST_st85_fsm_84;
end
ap_ST_st85_fsm_84 :
begin
ap_NS_fsm = ap_ST_st86_fsm_85;
end
ap_ST_st86_fsm_85 :
begin
ap_NS_fsm = ap_ST_st87_fsm_86;
end
ap_ST_st87_fsm_86 :
begin
ap_NS_fsm = ap_ST_st88_fsm_87;
end
ap_ST_st88_fsm_87 :
begin
ap_NS_fsm = ap_ST_st89_fsm_88;
end
ap_ST_st89_fsm_88 :
begin
ap_NS_fsm = ap_ST_st90_fsm_89;
end
ap_ST_st90_fsm_89 :
begin
ap_NS_fsm = ap_ST_st91_fsm_90;
end
ap_ST_st91_fsm_90 :
begin
ap_NS_fsm = ap_ST_st92_fsm_91;
end
ap_ST_st92_fsm_91 :
begin
ap_NS_fsm = ap_ST_st93_fsm_92;
end
ap_ST_st93_fsm_92 :
begin
if ((ap_const_lv1_0 == exitcond_flatten2_fu_1605_p2)) begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end else begin
ap_NS_fsm = ap_ST_pp3_stg0_fsm_93;
end
end
ap_ST_pp3_stg0_fsm_93 :
begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & ~((ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & ~(ap_const_lv1_0 == exitcond_flatten3_fu_1611_p2))) begin
ap_NS_fsm = ap_ST_pp3_stg0_fsm_93;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & ~((ap_const_lv1_0 == exitcond_flatten3_reg_2201) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & ~(ap_const_lv1_0 == exitcond_flatten3_fu_1611_p2))) begin
ap_NS_fsm = ap_ST_st96_fsm_94;
end else begin
ap_NS_fsm = ap_ST_pp3_stg0_fsm_93;
end
end
ap_ST_st96_fsm_94 :
begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign HLS_accel_CONTROL_BUS_s_axi_U_ap_dummy_ce = ap_const_logic_1;
assign OUTPUT_STREAM_TDATA = out_q0;
assign OUTPUT_STREAM_TDEST = ap_const_lv5_0;
assign OUTPUT_STREAM_TID = ap_const_lv5_0;
assign OUTPUT_STREAM_TKEEP = ap_const_lv4_F;
assign OUTPUT_STREAM_TLAST = last_assign_reg_2220;
assign OUTPUT_STREAM_TSTRB = ap_const_lv4_F;
assign OUTPUT_STREAM_TUSER = ap_const_lv4_0;
assign a_load_1_to_int_fu_1019_p1 = a_load_1_reg_1821;
assign a_load_2_to_int_fu_1308_p1 = a_load_2_reg_1827;
assign a_load_3_to_int_fu_1067_p1 = a_load_3_reg_1866;
assign a_load_4_to_int_fu_1415_p1 = a_load_4_reg_1877;
assign a_load_5_to_int_fu_1468_p1 = a_load_5_reg_1914;
assign a_load_6_to_int_fu_1115_p1 = a_load_6_reg_1921;
assign a_load_7_to_int_fu_1522_p1 = a_load_7_reg_1947;
assign a_load_8_to_int_fu_1163_p1 = a_load_8_reg_1954;
/// ap_rst_n_inv assign process. ///
always @ (ap_rst_n)
begin
ap_rst_n_inv = ~ap_rst_n;
end
/// ap_sig_bdd_1001 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1001 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2A]);
end
/// ap_sig_bdd_1009 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1009 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_36]);
end
/// ap_sig_bdd_1017 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1017 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_56]);
end
/// ap_sig_bdd_1031 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1031 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_50]);
end
/// ap_sig_bdd_136 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_136 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_1778 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1778 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5E]);
end
/// ap_sig_bdd_187 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_187 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5]);
end
/// ap_sig_bdd_198 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_198 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_18]);
end
/// ap_sig_bdd_209 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_209 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_29]);
end
/// ap_sig_bdd_220 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_220 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_35]);
end
/// ap_sig_bdd_228 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_228 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4F]);
end
/// ap_sig_bdd_243 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_243 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9]);
end
/// ap_sig_bdd_258 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_258 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_B]);
end
/// ap_sig_bdd_266 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_266 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_C]);
end
/// ap_sig_bdd_275 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_275 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_D]);
end
/// ap_sig_bdd_284 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_284 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_E]);
end
/// ap_sig_bdd_292 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_292 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_55]);
end
/// ap_sig_bdd_305 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_305 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_49]);
end
/// ap_sig_bdd_313 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_313 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4E]);
end
/// ap_sig_bdd_322 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_322 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_F]);
end
/// ap_sig_bdd_329 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_329 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_17]);
end
/// ap_sig_bdd_338 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_338 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_28]);
end
/// ap_sig_bdd_346 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_346 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_34]);
end
/// ap_sig_bdd_354 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_354 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_40]);
end
/// ap_sig_bdd_364 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_364 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_11]);
end
/// ap_sig_bdd_372 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_372 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1D]);
end
/// ap_sig_bdd_381 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_381 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2E]);
end
/// ap_sig_bdd_390 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_390 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3A]);
end
/// ap_sig_bdd_398 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_398 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5A]);
end
/// ap_sig_bdd_411 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_411 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3B]);
end
/// ap_sig_bdd_418 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_418 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5B]);
end
/// ap_sig_bdd_431 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_431 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
/// ap_sig_bdd_436 assign process. ///
always @ (INPUT_STREAM_TVALID or exitcond_flatten_fu_604_p2)
begin
ap_sig_bdd_436 = ((INPUT_STREAM_TVALID == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_flatten_fu_604_p2));
end
/// ap_sig_bdd_453 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_453 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
/// ap_sig_bdd_457 assign process. ///
always @ (INPUT_STREAM_TVALID or exitcond_flatten8_fu_682_p2)
begin
ap_sig_bdd_457 = ((INPUT_STREAM_TVALID == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_flatten8_fu_682_p2));
end
/// ap_sig_bdd_474 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_474 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
/// ap_sig_bdd_485 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_485 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4]);
end
/// ap_sig_bdd_525 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_525 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6]);
end
/// ap_sig_bdd_549 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_549 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_7]);
end
/// ap_sig_bdd_566 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_566 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8]);
end
/// ap_sig_bdd_587 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_587 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A]);
end
/// ap_sig_bdd_620 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_620 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_10]);
end
/// ap_sig_bdd_635 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_635 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_12]);
end
/// ap_sig_bdd_648 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_648 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_13]);
end
/// ap_sig_bdd_659 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_659 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_14]);
end
/// ap_sig_bdd_668 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_668 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1E]);
end
/// ap_sig_bdd_680 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_680 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1F]);
end
/// ap_sig_bdd_690 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_690 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_23]);
end
/// ap_sig_bdd_701 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_701 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_24]);
end
/// ap_sig_bdd_710 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_710 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2F]);
end
/// ap_sig_bdd_721 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_721 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_30]);
end
/// ap_sig_bdd_729 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_729 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_44]);
end
/// ap_sig_bdd_738 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_738 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5C]);
end
/// ap_sig_bdd_757 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_757 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5D]);
end
/// ap_sig_bdd_931 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_931 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3C]);
end
/// ap_sig_bdd_938 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_938 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_45]);
end
/// ap_sig_bdd_945 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_945 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4A]);
end
/// ap_sig_bdd_955 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_955 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_41]);
end
/// ap_sig_bdd_994 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_994 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_19]);
end
assign b_d0 = INPUT_STREAM_TDATA;
assign exitcond2_i_fu_694_p2 = (j2_0_i_reg_386 == ap_const_lv6_20? 1'b1: 1'b0);
assign exitcond2_i_i_fu_1589_p2 = (q_reg_1834 == ap_const_lv6_20? 1'b1: 1'b0);
assign exitcond2_i_i_mid_fu_774_p2 = (exitcond2_i_i1_reg_409 & not_exitcond_flatten_fu_768_p2);
assign exitcond4_i_fu_616_p2 = (j_0_i_reg_353 == ap_const_lv6_20? 1'b1: 1'b0);
assign exitcond_flatten1_fu_1594_p2 = (indvar_flatten_next2_fu_1581_p3 == ap_const_lv12_400? 1'b1: 1'b0);
assign exitcond_flatten2_fu_1605_p2 = (indvar_flatten2_reg_475 == ap_const_lv14_27FF? 1'b1: 1'b0);
assign exitcond_flatten3_fu_1611_p2 = (indvar_flatten3_reg_486 == ap_const_lv11_400? 1'b1: 1'b0);
assign exitcond_flatten8_fu_682_p2 = (indvar_flatten6_reg_364 == ap_const_lv11_400? 1'b1: 1'b0);
assign exitcond_flatten_fu_604_p2 = (indvar_flatten_reg_331 == ap_const_lv11_400? 1'b1: 1'b0);
assign exitcond_i_fu_1623_p2 = (j5_0_i_reg_508 == ap_const_lv6_20? 1'b1: 1'b0);
assign grp_fu_520_ce = ap_const_logic_1;
assign grp_fu_526_ce = ap_const_logic_1;
assign grp_fu_532_p0 = reg_592;
assign grp_fu_547_ce = ap_const_logic_1;
assign grp_fu_552_ce = ap_const_logic_1;
assign i1_0_i_mid2_fu_714_p3 = ((exitcond2_i_fu_694_p2)? i_s_fu_708_p2: i1_0_i_reg_375);
assign i4_0_i_mid2_fu_1643_p3 = ((exitcond_i_fu_1623_p2)? i_1_fu_1637_p2: i4_0_i_phi_fu_501_p4);
assign i_0_i_mid2_fu_636_p3 = ((exitcond4_i_fu_616_p2)? i_fu_630_p2: i_0_i_reg_342);
assign i_1_fu_1637_p2 = (i4_0_i_phi_fu_501_p4 + ap_const_lv6_1);
assign i_fu_630_p2 = (i_0_i_reg_342 + ap_const_lv6_1);
assign i_s_fu_708_p2 = (i1_0_i_reg_375 + ap_const_lv6_1);
assign indvar_flatten13_op_fu_1575_p2 = (indvar_flatten1_reg_464 + ap_const_lv12_1);
assign indvar_flatten_next1_fu_1617_p2 = (indvar_flatten3_reg_486 + ap_const_lv11_1);
assign indvar_flatten_next2_fu_1581_p3 = ((exitcond_flatten4_reg_397)? ap_const_lv12_1: indvar_flatten13_op_fu_1575_p2);
assign indvar_flatten_next3_fu_1569_p2 = (indvar_flatten2_reg_475 + ap_const_lv14_1);
assign indvar_flatten_next7_fu_688_p2 = (indvar_flatten6_reg_364 + ap_const_lv11_1);
assign indvar_flatten_next_fu_610_p2 = (indvar_flatten_reg_331 + ap_const_lv11_1);
assign j2_0_i_mid2_fu_700_p3 = ((exitcond2_i_fu_694_p2)? ap_const_lv6_0: j2_0_i_reg_386);
assign j5_0_i_cast5_fu_1663_p1 = j5_0_i_mid2_fu_1629_p3;
assign j5_0_i_mid2_fu_1629_p3 = ((exitcond_i_fu_1623_p2)? ap_const_lv6_0: j5_0_i_reg_508);
assign j_0_i_mid2_fu_622_p3 = ((exitcond4_i_fu_616_p2)? ap_const_lv6_0: j_0_i_reg_353);
assign j_1_fu_754_p2 = (j2_0_i_mid2_fu_700_p3 + ap_const_lv6_1);
assign j_2_fu_1706_p2 = (j5_0_i_mid2_fu_1629_p3 + ap_const_lv6_1);
assign j_fu_676_p2 = (j_0_i_mid2_fu_622_p3 + ap_const_lv6_1);
assign k_fu_1667_p2 = (j5_0_i_cast5_fu_1663_p1 + tmp_8_fu_1655_p3);
assign last_assign_fu_1700_p2 = (k_fu_1667_p2 == ap_const_lv10_3FF? 1'b1: 1'b0);
assign m_assign_to_int_fu_1216_p1 = b_load_reg_2039;
assign not_exitcond_flatten_fu_768_p2 = (exitcond_flatten4_reg_397 ^ ap_const_lv1_1);
assign notlhs1_fu_1325_p2 = (tmp_25_fu_1311_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs2_fu_1084_p2 = (tmp_47_fu_1070_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs3_fu_1432_p2 = (tmp_54_fu_1418_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs4_fu_1485_p2 = (tmp_59_fu_1471_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs5_fu_1132_p2 = (tmp_64_fu_1118_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs6_fu_1539_p2 = (tmp_69_fu_1525_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs7_fu_1180_p2 = (tmp_74_fu_1166_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs8_fu_1233_p2 = (tmp_79_fu_1219_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs9_fu_1372_p2 = (tmp_96_fu_1358_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs_fu_1036_p2 = (tmp_fu_1022_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notrhs1_fu_1331_p2 = (tmp_30_fu_1321_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs2_fu_1090_p2 = (tmp_48_fu_1080_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs3_fu_1438_p2 = (tmp_60_fu_1428_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs4_fu_1491_p2 = (tmp_70_fu_1481_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs5_fu_1138_p2 = (tmp_83_fu_1128_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs6_fu_1545_p2 = (tmp_85_fu_1535_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs7_fu_1186_p2 = (tmp_88_fu_1176_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs8_fu_1239_p2 = (tmp_90_fu_1229_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs9_fu_1378_p2 = (tmp_97_fu_1368_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs_fu_1042_p2 = (tmp_16_fu_1032_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign or_cond_i12_i_i_fu_1251_p2 = (tmp_81_fu_1245_p2 & tmp_91_reg_2060);
assign out_d0 = reg_597;
assign output_0_i13_i_i_fu_1293_p3 = ((tmp_93_reg_2071)? ap_const_lv32_42C80000: ap_const_lv32_0);
assign p_0_i_i_mid2_fu_786_p3 = ((exitcond2_i_i_mid_fu_774_p2)? p_fu_780_p2: p_0_i_i_mid_fu_760_p3);
assign p_0_i_i_mid_fu_760_p3 = ((exitcond_flatten4_reg_397)? ap_const_lv6_0: p_0_i_i_reg_420);
assign p_addr10_fu_988_p2 = (p_addr8_cast1_fu_934_p1 + tmp_52_0_1_trn_cast_reg_1799);
assign p_addr11_cast1_fu_960_p1 = tmp_75_fu_952_p3;
assign p_addr11_cast_fu_964_p1 = tmp_75_fu_952_p3;
assign p_addr11_fu_1689_p2 = (p_addr16_cast_fu_1685_p1 + tmp_5_trn_cast_fu_1673_p1);
assign p_addr16_cast_fu_1685_p1 = tmp_102_fu_1677_p3;
assign p_addr1_fu_665_p2 = (p_addr_cast_fu_661_p1 + tmp_7_trn_cast_fu_649_p1);
assign p_addr2_cast_fu_739_p1 = tmp_5_fu_731_p3;
assign p_addr2_fu_968_p2 = ($signed(p_addr11_cast_fu_964_p1) + $signed(tmp_16_trn_cast1_reg_1816));
assign p_addr3_fu_743_p2 = (p_addr2_cast_fu_739_p1 + tmp_6_trn_cast_fu_727_p1);
assign p_addr4_cast_fu_844_p1 = $signed(tmp_12_fu_836_p3);
assign p_addr4_fu_978_p2 = (p_addr11_cast1_fu_960_p1 + tmp_52_0_1_trn_cast_reg_1799);
assign p_addr5_fu_848_p2 = ($signed(p_addr4_cast_fu_844_p1) + $signed(tmp_16_trn_cast_fu_832_p1));
assign p_addr6_fu_871_p2 = ($signed(p_addr4_cast_fu_844_p1) + $signed(tmp_52_0_1_trn_cast_fu_867_p1));
assign p_addr7_fu_902_p2 = ($signed(p_addr4_cast_reg_1783) + $signed(tmp_46_0_2_trn_cast_fu_898_p1));
assign p_addr8_cast1_fu_934_p1 = tmp_53_reg_1851;
assign p_addr8_cast_fu_919_p1 = tmp_53_fu_912_p3;
assign p_addr8_fu_983_p2 = (p_addr11_cast1_fu_960_p1 + tmp_46_0_2_trn_cast_reg_1840);
assign p_addr9_fu_923_p2 = ($signed(p_addr8_cast_fu_919_p1) + $signed(tmp_16_trn_cast1_fu_890_p1));
assign p_addr_cast_fu_661_p1 = tmp_1_fu_653_p3;
assign p_addr_fu_937_p2 = (p_addr8_cast1_fu_934_p1 + tmp_46_0_2_trn_cast_reg_1840);
assign p_fu_780_p2 = (p_0_i_i_mid_fu_760_p3 + ap_const_lv6_1);
assign q_0_i_i_mid2_fu_799_p3 = ((tmp_7_fu_794_p2)? ap_const_lv6_0: q_0_i_i_reg_431);
assign q_fu_893_p2 = (q_0_i_i_mid2_reg_1768 + ap_const_lv6_1);
assign ret_fu_644_p1 = INPUT_STREAM_TDATA;
assign sel_tmp1_fu_1262_p2 = (or_cond_i12_i_i_reg_2065 ^ ap_const_lv1_1);
assign sel_tmp2_fu_1267_p2 = (tmp_93_reg_2071 & sel_tmp1_fu_1262_p2);
assign speed_0_i_i_mid2_fu_1005_p3 = ((exitcond_flatten4_reg_397)? speed1_reg_442: speed_0_i_i_reg_453);
assign speed_fu_1600_p2 = (speed_0_i_i_mid2_reg_1977 + ap_const_lv4_1);
assign sum_4_i_i_0_1_fu_1402_p3 = ((tmp_23_reg_1793)? sum_4_i_i_reg_2089: reg_585);
assign sum_4_i_i_0_2_fu_1409_p3 = ((tmp_23_reg_1793)? sum_4_i_i_reg_2089: grp_fu_532_p1);
assign sum_4_i_i_1_fu_1462_p3 = ((tmp_52_reg_1810)? sum_4_i_i_0_2_reg_2121: grp_fu_520_p2);
assign sum_4_i_i_2_fu_1515_p3 = ((tmp_52_reg_1810)? reg_585: grp_fu_532_p1);
assign sum_4_i_i_fu_1301_p3 = ((tmp_11_reg_1778)? ap_const_lv32_0: grp_fu_532_p1);
assign tmp_100_fu_1390_p2 = (tmp_98_fu_1384_p2 & tmp_99_reg_2101);
assign tmp_101_fu_1651_p1 = i4_0_i_mid2_fu_1643_p3[4:0];
assign tmp_102_fu_1677_p3 = {{i4_0_i_mid2_fu_1643_p3}, {ap_const_lv5_0}};
assign tmp_103_fu_1695_p1 = p_addr11_fu_1689_p2;
assign tmp_10_fu_818_p2 = (x_assign_fu_807_p2 | y_assign_fu_812_p2);
assign tmp_12_fu_836_p3 = {{x_assign_fu_807_p2}, {ap_const_lv5_0}};
assign tmp_13_fu_854_p1 = p_addr5_fu_848_p2;
assign tmp_16_fu_1032_p1 = a_load_1_to_int_fu_1019_p1[22:0];
assign tmp_16_trn_cast1_fu_890_p1 = $signed(y_assign_reg_1773);
assign tmp_16_trn_cast_fu_832_p1 = $signed(y_assign_fu_812_p2);
assign tmp_17_fu_1048_p2 = (notrhs_fu_1042_p2 | notlhs_fu_1036_p2);
assign tmp_19_fu_1054_p2 = (tmp_17_fu_1048_p2 & tmp_18_reg_1861);
assign tmp_1_fu_653_p3 = {{i_0_i_mid2_fu_636_p3}, {ap_const_lv5_0}};
assign tmp_21_fu_1059_p3 = ((tmp_19_fu_1054_p2)? reg_573: ap_const_lv64_0);
assign tmp_24_fu_877_p1 = p_addr6_fu_871_p2;
assign tmp_25_fu_1311_p4 = {{a_load_2_to_int_fu_1308_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_30_fu_1321_p1 = a_load_2_to_int_fu_1308_p1[22:0];
assign tmp_32_fu_1013_p2 = (speed_0_i_i_mid2_fu_1005_p3 == ap_const_lv4_9? 1'b1: 1'b0);
assign tmp_33_fu_1337_p2 = (notrhs1_fu_1331_p2 | notlhs1_fu_1325_p2);
assign tmp_3_fu_671_p1 = p_addr1_fu_665_p2;
assign tmp_45_fu_1343_p2 = (tmp_33_fu_1337_p2 & tmp_44_reg_1909);
assign tmp_46_0_2_trn_cast_fu_898_p1 = q_fu_893_p2;
assign tmp_46_fu_907_p1 = p_addr7_fu_902_p2;
assign tmp_47_fu_1070_p4 = {{a_load_3_to_int_fu_1067_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_48_fu_1080_p1 = a_load_3_to_int_fu_1067_p1[22:0];
assign tmp_49_0_2_fu_1107_p3 = ((tmp_51_fu_1102_p2)? reg_573: ap_const_lv64_0);
assign tmp_49_2_2_fu_1203_p3 = ((tmp_78_fu_1198_p2)? reg_573: ap_const_lv64_0);
assign tmp_49_2_fu_1155_p3 = ((tmp_68_fu_1150_p2)? reg_573: ap_const_lv64_0);
assign tmp_49_fu_1096_p2 = (notrhs2_fu_1090_p2 | notlhs2_fu_1084_p2);
assign tmp_51_fu_1102_p2 = (tmp_49_fu_1096_p2 & tmp_50_reg_1942);
assign tmp_52_0_1_trn_cast_fu_867_p1 = q_0_i_i_mid2_fu_799_p3;
assign tmp_53_fu_912_p3 = {{p_0_i_i_mid2_reg_1760}, {ap_const_lv5_0}};
assign tmp_54_fu_1418_p4 = {{a_load_4_to_int_fu_1415_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_55_fu_929_p1 = p_addr9_fu_923_p2;
assign tmp_56_fu_1444_p2 = (notrhs3_fu_1438_p2 | notlhs3_fu_1432_p2);
assign tmp_58_fu_1450_p2 = (tmp_56_fu_1444_p2 & tmp_57_reg_1983);
assign tmp_59_fu_1471_p4 = {{a_load_5_to_int_fu_1468_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_5_fu_731_p3 = {{i1_0_i_mid2_fu_714_p3}, {ap_const_lv5_0}};
assign tmp_5_trn_cast_fu_1673_p1 = j5_0_i_mid2_fu_1629_p3;
assign tmp_60_fu_1428_p1 = a_load_4_to_int_fu_1415_p1[22:0];
assign tmp_61_fu_1497_p2 = (notrhs4_fu_1491_p2 | notlhs4_fu_1485_p2);
assign tmp_63_fu_1503_p2 = (tmp_61_fu_1497_p2 & tmp_62_reg_1999);
assign tmp_64_fu_1118_p4 = {{a_load_6_to_int_fu_1115_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_65_fu_942_p1 = p_addr_fu_937_p2;
assign tmp_66_fu_1144_p2 = (notrhs5_fu_1138_p2 | notlhs5_fu_1132_p2);
assign tmp_68_fu_1150_p2 = (tmp_66_fu_1144_p2 & tmp_67_reg_2004);
assign tmp_69_fu_1525_p4 = {{a_load_7_to_int_fu_1522_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_6_fu_749_p1 = p_addr3_fu_743_p2;
assign tmp_6_trn_cast_fu_727_p1 = j2_0_i_mid2_fu_700_p3;
assign tmp_70_fu_1481_p1 = a_load_5_to_int_fu_1468_p1[22:0];
assign tmp_71_fu_1551_p2 = (notrhs6_fu_1545_p2 | notlhs6_fu_1539_p2);
assign tmp_73_fu_1557_p2 = (tmp_71_fu_1551_p2 & tmp_72_reg_2014);
assign tmp_74_fu_1166_p4 = {{a_load_8_to_int_fu_1163_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_75_fu_952_p3 = {{x_assign_s_fu_947_p2}, {ap_const_lv5_0}};
assign tmp_76_fu_1192_p2 = (notrhs7_fu_1186_p2 | notlhs7_fu_1180_p2);
assign tmp_78_fu_1198_p2 = (tmp_76_fu_1192_p2 & tmp_77_reg_2034);
assign tmp_79_fu_1219_p4 = {{m_assign_to_int_fu_1216_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_7_fu_794_p2 = (exitcond2_i_i_mid_reg_1755 | exitcond_flatten4_reg_397);
assign tmp_7_trn_cast_fu_649_p1 = j_0_i_mid2_fu_622_p3;
assign tmp_80_fu_973_p1 = p_addr2_fu_968_p2;
assign tmp_81_fu_1245_p2 = (notrhs8_fu_1239_p2 | notlhs8_fu_1233_p2);
assign tmp_83_fu_1128_p1 = a_load_6_to_int_fu_1115_p1[22:0];
assign tmp_84_fu_993_p1 = p_addr4_reg_1894;
assign tmp_85_fu_1535_p1 = a_load_7_to_int_fu_1522_p1[22:0];
assign tmp_86_fu_997_p1 = p_addr8_reg_1899;
assign tmp_88_fu_1176_p1 = a_load_8_to_int_fu_1163_p1[22:0];
assign tmp_89_fu_1001_p1 = p_addr10_reg_1904;
assign tmp_8_fu_1655_p3 = {{tmp_101_fu_1651_p1}, {ap_const_lv5_0}};
assign tmp_90_fu_1229_p1 = m_assign_to_int_fu_1216_p1[22:0];
assign tmp_91_fu_1211_p2 = (tmp_82_reg_2050 | grp_fu_540_p2);
assign tmp_93_fu_1256_p2 = (tmp_81_fu_1245_p2 & grp_fu_540_p2);
assign tmp_94_fu_1272_p3 = ((sel_tmp2_fu_1267_p2)? ap_const_lv32_C2C80000: ap_const_lv32_0);
assign tmp_95_fu_1280_p2 = (sel_tmp2_fu_1267_p2 | or_cond_i12_i_i_reg_2065);
assign tmp_96_fu_1358_p4 = {{x_assign_1_to_int_fu_1355_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_97_fu_1368_p1 = x_assign_1_to_int_fu_1355_p1[22:0];
assign tmp_98_fu_1384_p2 = (notrhs9_fu_1378_p2 | notlhs9_fu_1372_p2);
assign tmp_fu_1022_p4 = {{a_load_1_to_int_fu_1019_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign x_assign_1_fu_1285_p3 = ((tmp_95_fu_1280_p2)? tmp_94_fu_1272_p3: ap_const_lv32_42C80000);
assign x_assign_1_to_int_fu_1355_p1 = x_assign_1_reg_2077;
assign x_assign_2_fu_1395_p3 = ((tmp_100_fu_1390_p2)? x_assign_1_reg_2077: ap_const_lv32_0);
assign x_assign_6_0_1_fu_1348_p3 = ((tmp_45_reg_2096)? a_load_2_reg_1827: ap_const_lv32_0);
assign x_assign_6_1_2_fu_1508_p3 = ((tmp_63_reg_2142)? a_load_5_reg_1914: ap_const_lv32_0);
assign x_assign_6_1_fu_1455_p3 = ((tmp_58_reg_2127)? a_load_4_reg_1877: ap_const_lv32_0);
assign x_assign_6_2_1_fu_1562_p3 = ((tmp_73_reg_2157)? a_load_7_reg_1947: ap_const_lv32_0);
assign x_assign_fu_807_p2 = ($signed(p_0_i_i_mid2_reg_1760) + $signed(ap_const_lv6_3F));
assign x_assign_s_fu_947_p2 = (p_0_i_i_mid2_reg_1760 + ap_const_lv6_1);
assign y_assign_fu_812_p2 = ($signed(q_0_i_i_mid2_fu_799_p3) + $signed(ap_const_lv6_3F));
always @ (posedge ap_clk)
begin
p_addr4_cast_reg_1783[4:0] <= 5'b00000;
tmp_52_0_1_trn_cast_reg_1799[11:6] <= 6'b000000;
tmp_46_0_2_trn_cast_reg_1840[11:6] <= 6'b000000;
tmp_53_reg_1851[4:0] <= 5'b00000;
tmp_89_reg_1965[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
x_assign_1_reg_2077[18:0] <= 19'b0000000000000000000;
x_assign_1_reg_2077[21:20] <= 2'b00;
x_assign_1_reg_2077[24:24] <= 1'b0;
x_assign_1_reg_2077[29:26] <= 4'b0000;
x_assign_2_reg_2111[18:0] <= 19'b0000000000000000000;
x_assign_2_reg_2111[21:20] <= 2'b00;
x_assign_2_reg_2111[24:24] <= 1'b0;
x_assign_2_reg_2111[29:26] <= 4'b0000;
end
endmodule //HLS_accel
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:04:51 EST 2014
//
//
// Ports:
// Name I/O size props
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 128 reg
// wsiM0_MByteEn O 16 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// CLK I 1 clock
// RST_N I 1 reset
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 32
// wsiS0_MByteEn I 4
// wsiS0_MReqInfo I 8
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkWsiAdapter4B16B(CLK,
RST_N,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n);
input CLK;
input RST_N;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [31 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [3 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [127 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [15 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// signals for module outputs
wire [127 : 0] wsiM0_MData;
wire [15 : 0] wsiM0_MByteEn;
wire [11 : 0] wsiM0_MBurstLength;
wire [7 : 0] wsiM0_MReqInfo;
wire [2 : 0] wsiM0_MCmd;
wire wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy;
// inlined wires
wire [168 : 0] wsiM_reqFifo_x_wire_wget;
wire [95 : 0] wsiM_extStatusW_wget, wsiS_extStatusW_wget;
wire [60 : 0] wsiS_wsiReq_wget;
wire [31 : 0] wsi_Es_mData_w_wget;
wire [11 : 0] wsi_Es_mBurstLength_w_wget;
wire [7 : 0] wsi_Es_mReqInfo_w_wget;
wire [3 : 0] wsi_Es_mByteEn_w_wget;
wire [2 : 0] wsi_Es_mCmd_w_wget;
wire wsiM_operateD_1_wget,
wsiM_operateD_1_whas,
wsiM_peerIsReady_1_wget,
wsiM_peerIsReady_1_whas,
wsiM_reqFifo_dequeueing_whas,
wsiM_reqFifo_enqueueing_whas,
wsiM_reqFifo_x_wire_whas,
wsiM_sThreadBusy_pw_whas,
wsiS_operateD_1_wget,
wsiS_operateD_1_whas,
wsiS_peerIsReady_1_wget,
wsiS_peerIsReady_1_whas,
wsiS_reqFifo_doResetClr_whas,
wsiS_reqFifo_doResetDeq_whas,
wsiS_reqFifo_doResetEnq_whas,
wsiS_reqFifo_r_clr_whas,
wsiS_reqFifo_r_deq_whas,
wsiS_reqFifo_r_enq_whas,
wsiS_sThreadBusy_dw_wget,
wsiS_sThreadBusy_dw_whas,
wsiS_wsiReq_whas,
wsi_Es_mBurstLength_w_whas,
wsi_Es_mBurstPrecise_w_whas,
wsi_Es_mByteEn_w_whas,
wsi_Es_mCmd_w_whas,
wsi_Es_mDataInfo_w_whas,
wsi_Es_mData_w_whas,
wsi_Es_mReqInfo_w_whas,
wsi_Es_mReqLast_w_whas;
// register isFull
reg isFull;
wire isFull_D_IN, isFull_EN;
// register isLast
reg isLast;
wire isLast_D_IN, isLast_EN;
// register pos
reg [1 : 0] pos;
wire [1 : 0] pos_D_IN;
wire pos_EN;
// register stage_0
reg [60 : 0] stage_0;
wire [60 : 0] stage_0_D_IN;
wire stage_0_EN;
// register stage_1
reg [60 : 0] stage_1;
wire [60 : 0] stage_1_D_IN;
wire stage_1_EN;
// register stage_2
reg [60 : 0] stage_2;
wire [60 : 0] stage_2_D_IN;
wire stage_2_EN;
// register stage_3
reg [60 : 0] stage_3;
wire [60 : 0] stage_3_D_IN;
wire stage_3_EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind_D_IN;
wire wsiM_burstKind_EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky_D_IN, wsiM_errorSticky_EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount_D_IN;
wire wsiM_iMesgCount_EN;
// register wsiM_isReset_isInReset
reg wsiM_isReset_isInReset;
wire wsiM_isReset_isInReset_D_IN, wsiM_isReset_isInReset_EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD_D_IN, wsiM_operateD_EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount_D_IN;
wire wsiM_pMesgCount_EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady_D_IN, wsiM_peerIsReady_EN;
// register wsiM_reqFifo_cntr_r
reg [1 : 0] wsiM_reqFifo_cntr_r;
wire [1 : 0] wsiM_reqFifo_cntr_r_D_IN;
wire wsiM_reqFifo_cntr_r_EN;
// register wsiM_reqFifo_q_0
reg [168 : 0] wsiM_reqFifo_q_0;
reg [168 : 0] wsiM_reqFifo_q_0_D_IN;
wire wsiM_reqFifo_q_0_EN;
// register wsiM_reqFifo_q_1
reg [168 : 0] wsiM_reqFifo_q_1;
reg [168 : 0] wsiM_reqFifo_q_1_D_IN;
wire wsiM_reqFifo_q_1_EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d_D_IN, wsiM_sThreadBusy_d_EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR_D_IN;
wire wsiM_statusR_EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount_D_IN;
wire wsiM_tBusyCount_EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky_D_IN, wsiM_trafficSticky_EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind_D_IN;
wire wsiS_burstKind_EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky_D_IN, wsiS_errorSticky_EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount_D_IN;
wire wsiS_iMesgCount_EN;
// register wsiS_isReset_isInReset
reg wsiS_isReset_isInReset;
wire wsiS_isReset_isInReset_D_IN, wsiS_isReset_isInReset_EN;
// register wsiS_mesgWordLength
reg [11 : 0] wsiS_mesgWordLength;
wire [11 : 0] wsiS_mesgWordLength_D_IN;
wire wsiS_mesgWordLength_EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD_D_IN, wsiS_operateD_EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount_D_IN;
wire wsiS_pMesgCount_EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady_D_IN, wsiS_peerIsReady_EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg_D_IN;
wire wsiS_reqFifo_countReg_EN;
// register wsiS_reqFifo_levelsValid
reg wsiS_reqFifo_levelsValid;
wire wsiS_reqFifo_levelsValid_D_IN, wsiS_reqFifo_levelsValid_EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR_D_IN;
wire wsiS_statusR_EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount_D_IN;
wire wsiS_tBusyCount_EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky_D_IN, wsiS_trafficSticky_EN;
// register wsiS_wordCount
reg [11 : 0] wsiS_wordCount;
wire [11 : 0] wsiS_wordCount_D_IN;
wire wsiS_wordCount_EN;
// ports of submodule wsiS_reqFifo
wire [60 : 0] wsiS_reqFifo_D_IN, wsiS_reqFifo_D_OUT;
wire wsiS_reqFifo_CLR,
wsiS_reqFifo_DEQ,
wsiS_reqFifo_EMPTY_N,
wsiS_reqFifo_ENQ,
wsiS_reqFifo_FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_reqFifo_reset;
// inputs to muxes for submodule ports
wire [168 : 0] MUX_wsiM_reqFifo_q_0_write_1__VAL_1,
MUX_wsiM_reqFifo_q_0_write_1__VAL_2,
MUX_wsiM_reqFifo_q_1_write_1__VAL_1;
wire [1 : 0] MUX_pos_write_1__VAL_1,
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1,
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2;
wire MUX_isFull_write_1__VAL_1,
MUX_wsiM_reqFifo_q_0_write_1__SEL_1,
MUX_wsiM_reqFifo_q_0_write_1__SEL_2,
MUX_wsiM_reqFifo_q_1_write_1__SEL_1,
MUX_wsiM_reqFifo_q_1_write_1__SEL_2,
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3;
// remaining internal signals
reg [15 : 0] x_byteEn__h6493;
wire [127 : 0] x_data__h6492;
wire [15 : 0] be__h7294, be__h7313, be__h7354, be__h7410;
wire [11 : 0] x__h7358, x_burstLength__h6491;
wire [7 : 0] x__h7317;
wire _dfoo1, _dfoo3;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ;
// value method wsiM0_mCmd
assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[168:166] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[165] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[164] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[163:152] ;
// value method wsiM0_mData
assign wsiM0_MData = wsiM_reqFifo_q_0[151:24] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsiM_reqFifo_q_0[23:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ;
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd61),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST(RST_N),
.CLK(CLK),
.D_IN(wsiS_reqFifo_D_IN),
.ENQ(wsiS_reqFifo_ENQ),
.DEQ(wsiS_reqFifo_DEQ),
.CLR(wsiS_reqFifo_CLR),
.D_OUT(wsiS_reqFifo_D_OUT),
.FULL_N(wsiS_reqFifo_FULL_N),
.EMPTY_N(wsiS_reqFifo_EMPTY_N));
// rule RL_wsiM_reqFifo_deq
assign WILL_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ;
// rule RL_wsiM_reqFifo_incCtr
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr =
wsiM_reqFifo_enqueueing_whas && wsiM_reqFifo_enqueueing_whas &&
!WILL_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_reqFifo_decCtr
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr =
WILL_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing_whas ;
// rule RL_wsiM_reqFifo_both
assign WILL_FIRE_RL_wsiM_reqFifo_both =
wsiM_reqFifo_enqueueing_whas && WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_enqueueing_whas ;
// rule RL_wsiS_reqFifo_enq
assign WILL_FIRE_RL_wsiS_reqFifo_enq =
wsiS_reqFifo_FULL_N && wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq_wget[60:58] == 3'd1 ;
// rule RL_wsiS_reqFifo_reset
assign WILL_FIRE_RL_wsiS_reqFifo_reset =
WILL_FIRE_RL_wsiS_reqFifo_enq ||
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// inputs to muxes for submodule ports
assign MUX_wsiM_reqFifo_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo3 ;
assign MUX_wsiM_reqFifo_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo1 ;
assign MUX_wsiM_reqFifo_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ;
assign MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 =
wsiS_reqFifo_EMPTY_N && !isFull ;
assign MUX_isFull_write_1__VAL_1 = pos == 2'd3 || wsiS_reqFifo_D_OUT[57] ;
assign MUX_pos_write_1__VAL_1 = pos + 2'd1 ;
assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ;
assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 =
(wsiM_reqFifo_cntr_r == 2'd1) ?
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__VAL_2 =
{ 3'd1,
isLast,
stage_0[56],
x_burstLength__h6491,
x_data__h6492,
x_byteEn__h6493,
stage_0[7:0] } ;
assign MUX_wsiM_reqFifo_q_1_write_1__VAL_1 =
(wsiM_reqFifo_cntr_r == 2'd2) ?
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 :
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ;
// inlined wires
assign wsiS_wsiReq_wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsiS_wsiReq_whas = 1'd1 ;
assign wsiS_operateD_1_wget = 1'd1 ;
assign wsiS_operateD_1_whas = 1'd1 ;
assign wsiS_peerIsReady_1_wget = 1'd1 ;
assign wsiS_peerIsReady_1_whas = wsiS0_MReset_n ;
assign wsiS_sThreadBusy_dw_wget = wsiS_reqFifo_countReg > 2'd1 ;
assign wsiS_sThreadBusy_dw_whas =
wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ;
assign wsiM_reqFifo_x_wire_wget = MUX_wsiM_reqFifo_q_0_write_1__VAL_2 ;
assign wsiM_reqFifo_x_wire_whas = wsiM_reqFifo_enqueueing_whas ;
assign wsiM_operateD_1_wget = 1'd1 ;
assign wsiM_operateD_1_whas = 1'd1 ;
assign wsiM_peerIsReady_1_wget = 1'd1 ;
assign wsiM_peerIsReady_1_whas = wsiM0_SReset_n ;
assign wsi_Es_mCmd_w_wget = wsiS0_MCmd ;
assign wsi_Es_mCmd_w_whas = 1'd1 ;
assign wsi_Es_mBurstLength_w_wget = wsiS0_MBurstLength ;
assign wsi_Es_mBurstLength_w_whas = 1'd1 ;
assign wsi_Es_mData_w_wget = wsiS0_MData ;
assign wsi_Es_mData_w_whas = 1'd1 ;
assign wsi_Es_mByteEn_w_wget = wsiS0_MByteEn ;
assign wsi_Es_mByteEn_w_whas = 1'd1 ;
assign wsi_Es_mReqInfo_w_wget = wsiS0_MReqInfo ;
assign wsi_Es_mReqInfo_w_whas = 1'd1 ;
assign wsiS_reqFifo_r_enq_whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_r_deq_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_r_clr_whas = 1'b0 ;
assign wsiS_reqFifo_doResetEnq_whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_doResetDeq_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_doResetClr_whas = 1'b0 ;
assign wsiM_reqFifo_enqueueing_whas =
wsiM_reqFifo_cntr_r != 2'd2 && isFull ;
assign wsiM_reqFifo_dequeueing_whas = WILL_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_sThreadBusy_pw_whas = wsiM0_SThreadBusy ;
assign wsi_Es_mReqLast_w_whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w_whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mDataInfo_w_whas = 1'd1 ;
assign wsiS_extStatusW_wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
assign wsiM_extStatusW_wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
// register isFull
assign isFull_D_IN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
MUX_isFull_write_1__VAL_1 ;
assign isFull_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ||
wsiM_reqFifo_enqueueing_whas ;
// register isLast
assign isLast_D_IN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
wsiS_reqFifo_D_OUT[57] ;
assign isLast_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ||
wsiM_reqFifo_enqueueing_whas ;
// register pos
assign pos_D_IN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ?
MUX_pos_write_1__VAL_1 :
2'd0 ;
assign pos_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ||
wsiM_reqFifo_enqueueing_whas ;
// register stage_0
assign stage_0_D_IN = wsiS_reqFifo_D_OUT ;
assign stage_0_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 && pos == 2'd0 ;
// register stage_1
assign stage_1_D_IN = wsiS_reqFifo_D_OUT ;
assign stage_1_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 && pos == 2'd1 ;
// register stage_2
assign stage_2_D_IN = wsiS_reqFifo_D_OUT ;
assign stage_2_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 && pos == 2'd2 ;
// register stage_3
assign stage_3_D_IN = wsiS_reqFifo_D_OUT ;
assign stage_3_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 && pos == 2'd3 ;
// register wsiM_burstKind
assign wsiM_burstKind_D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[164] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
(wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
wsiM_reqFifo_q_0[165]) ;
// register wsiM_errorSticky
assign wsiM_errorSticky_D_IN = 1'b0 ;
assign wsiM_errorSticky_EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount_D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[165] ;
// register wsiM_isReset_isInReset
assign wsiM_isReset_isInReset_D_IN = 1'd0 ;
assign wsiM_isReset_isInReset_EN = wsiM_isReset_isInReset ;
// register wsiM_operateD
assign wsiM_operateD_D_IN = 1'b1 ;
assign wsiM_operateD_EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount_D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[165] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady_D_IN = wsiM0_SReset_n ;
assign wsiM_peerIsReady_EN = 1'd1 ;
// register wsiM_reqFifo_cntr_r
assign wsiM_reqFifo_cntr_r_D_IN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ?
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 :
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 ;
assign wsiM_reqFifo_cntr_r_EN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr ;
// register wsiM_reqFifo_q_0
always@(MUX_wsiM_reqFifo_q_0_write_1__SEL_1 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_1 or
MUX_wsiM_reqFifo_q_0_write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_0_write_1__SEL_1:
wsiM_reqFifo_q_0_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_1;
MUX_wsiM_reqFifo_q_0_write_1__SEL_2:
wsiM_reqFifo_q_0_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0_D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0_D_IN =
169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_0_EN =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo3 ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr &&
wsiM_reqFifo_cntr_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_1
always@(MUX_wsiM_reqFifo_q_1_write_1__SEL_1 or
MUX_wsiM_reqFifo_q_1_write_1__VAL_1 or
MUX_wsiM_reqFifo_q_1_write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_1_write_1__SEL_1:
wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_1_write_1__VAL_1;
MUX_wsiM_reqFifo_q_1_write_1__SEL_2:
wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1_D_IN =
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
default: wsiM_reqFifo_q_1_D_IN =
169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_1_EN =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo1 ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr &&
wsiM_reqFifo_cntr_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d_D_IN = wsiM0_SThreadBusy ;
assign wsiM_sThreadBusy_d_EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR_D_IN =
{ wsiM_isReset_isInReset,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR_EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount_D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount_EN =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky_D_IN = 1'd1 ;
assign wsiM_trafficSticky_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 ;
// register wsiS_burstKind
assign wsiS_burstKind_D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq_wget[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
(wsiS_burstKind == 2'd0 ||
(wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) &&
wsiS_wsiReq_wget[57]) ;
// register wsiS_errorSticky
assign wsiS_errorSticky_D_IN = 1'b0 ;
assign wsiS_errorSticky_EN = 1'b0 ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount_D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 &&
wsiS_wsiReq_wget[57] ;
// register wsiS_isReset_isInReset
assign wsiS_isReset_isInReset_D_IN = 1'd0 ;
assign wsiS_isReset_isInReset_EN = wsiS_isReset_isInReset ;
// register wsiS_mesgWordLength
assign wsiS_mesgWordLength_D_IN = wsiS_wordCount ;
assign wsiS_mesgWordLength_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq_wget[57] ;
// register wsiS_operateD
assign wsiS_operateD_D_IN = 1'b1 ;
assign wsiS_operateD_EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount_D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 &&
wsiS_wsiReq_wget[57] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady_D_IN = wsiS0_MReset_n ;
assign wsiS_peerIsReady_EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg_D_IN =
WILL_FIRE_RL_wsiS_reqFifo_enq ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq !=
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// register wsiS_reqFifo_levelsValid
assign wsiS_reqFifo_levelsValid_D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ;
assign wsiS_reqFifo_levelsValid_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ||
WILL_FIRE_RL_wsiS_reqFifo_enq ||
WILL_FIRE_RL_wsiS_reqFifo_reset ;
// register wsiS_statusR
assign wsiS_statusR_D_IN =
{ wsiS_isReset_isInReset,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget,
1'd0,
wsiS_trafficSticky } ;
assign wsiS_statusR_EN = 1'd1 ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount_D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount_EN =
wsiS_operateD && wsiS_peerIsReady &&
(!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget) ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky_D_IN = 1'd1 ;
assign wsiS_trafficSticky_EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// register wsiS_wordCount
assign wsiS_wordCount_D_IN =
wsiS_wsiReq_wget[57] ? 12'd1 : wsiS_wordCount + 12'd1 ;
assign wsiS_wordCount_EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo_D_IN = wsiS_wsiReq_wget ;
assign wsiS_reqFifo_ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_DEQ = MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_CLR = 1'b0 ;
// remaining internal signals
assign _dfoo1 =
wsiM_reqFifo_cntr_r != 2'd2 ||
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd1 ;
assign _dfoo3 =
wsiM_reqFifo_cntr_r != 2'd1 ||
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd0 ;
assign be__h7294 = { 12'd0, stage_0[11:8] } ;
assign be__h7313 = { 8'd0, x__h7317 } ;
assign be__h7354 = { 4'd0, x__h7358 } ;
assign be__h7410 = { stage_3[11:8], x__h7358 } ;
assign x__h7317 = { stage_1[11:8], stage_0[11:8] } ;
assign x__h7358 = { stage_2[11:8], x__h7317 } ;
assign x_burstLength__h6491 = stage_0[55:44] >> 2 ;
assign x_data__h6492 =
{ stage_3[43:12],
stage_2[43:12],
stage_1[43:12],
stage_0[43:12] } ;
always@(pos or
stage_3 or
stage_2 or
stage_1 or
stage_0 or be__h7294 or be__h7313 or be__h7354 or be__h7410)
begin
case (pos)
2'd0: x_byteEn__h6493 = be__h7294;
2'd1: x_byteEn__h6493 = be__h7313;
2'd2: x_byteEn__h6493 = be__h7354;
2'd3: x_byteEn__h6493 = be__h7410;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
isFull <= `BSV_ASSIGNMENT_DELAY 1'd0;
isLast <= `BSV_ASSIGNMENT_DELAY 1'd0;
pos <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (isFull_EN) isFull <= `BSV_ASSIGNMENT_DELAY isFull_D_IN;
if (isLast_EN) isLast <= `BSV_ASSIGNMENT_DELAY isLast_D_IN;
if (pos_EN) pos <= `BSV_ASSIGNMENT_DELAY pos_D_IN;
if (wsiM_burstKind_EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind_D_IN;
if (wsiM_errorSticky_EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky_D_IN;
if (wsiM_iMesgCount_EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount_D_IN;
if (wsiM_operateD_EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD_D_IN;
if (wsiM_pMesgCount_EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount_D_IN;
if (wsiM_peerIsReady_EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady_D_IN;
if (wsiM_reqFifo_cntr_r_EN)
wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY
wsiM_reqFifo_cntr_r_D_IN;
if (wsiM_reqFifo_q_0_EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0_D_IN;
if (wsiM_reqFifo_q_1_EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1_D_IN;
if (wsiM_sThreadBusy_d_EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d_D_IN;
if (wsiM_tBusyCount_EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount_D_IN;
if (wsiM_trafficSticky_EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky_D_IN;
if (wsiS_burstKind_EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind_D_IN;
if (wsiS_errorSticky_EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky_D_IN;
if (wsiS_iMesgCount_EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount_D_IN;
if (wsiS_operateD_EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD_D_IN;
if (wsiS_pMesgCount_EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount_D_IN;
if (wsiS_peerIsReady_EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady_D_IN;
if (wsiS_reqFifo_countReg_EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg_D_IN;
if (wsiS_reqFifo_levelsValid_EN)
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_levelsValid_D_IN;
if (wsiS_tBusyCount_EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount_D_IN;
if (wsiS_trafficSticky_EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky_D_IN;
if (wsiS_wordCount_EN)
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount_D_IN;
end
if (stage_0_EN) stage_0 <= `BSV_ASSIGNMENT_DELAY stage_0_D_IN;
if (stage_1_EN) stage_1 <= `BSV_ASSIGNMENT_DELAY stage_1_D_IN;
if (stage_2_EN) stage_2 <= `BSV_ASSIGNMENT_DELAY stage_2_D_IN;
if (stage_3_EN) stage_3 <= `BSV_ASSIGNMENT_DELAY stage_3_D_IN;
if (wsiM_statusR_EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR_D_IN;
if (wsiS_mesgWordLength_EN)
wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength_D_IN;
if (wsiS_statusR_EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR_D_IN;
end
always@(posedge CLK or `BSV_RESET_EDGE RST_N)
if (RST_N == `BSV_RESET_VALUE)
begin
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wsiM_isReset_isInReset_EN)
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiM_isReset_isInReset_D_IN;
if (wsiS_isReset_isInReset_EN)
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiS_isReset_isInReset_D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
isFull = 1'h0;
isLast = 1'h0;
pos = 2'h2;
stage_0 = 61'h0AAAAAAAAAAAAAAA;
stage_1 = 61'h0AAAAAAAAAAAAAAA;
stage_2 = 61'h0AAAAAAAAAAAAAAA;
stage_3 = 61'h0AAAAAAAAAAAAAAA;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_isReset_isInReset = 1'h0;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_cntr_r = 2'h2;
wsiM_reqFifo_q_0 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_isReset_isInReset = 1'h0;
wsiS_mesgWordLength = 12'hAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_reqFifo_levelsValid = 1'h0;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
wsiS_wordCount = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkWsiAdapter4B16B
|
`timescale 1ns/1ns
module udp_outbound_chain
(input clk_50,
input clk_100,
input [7:0] rxd,
input rxdv,
input rxlast,
output [7:0] txd,
output txdv,
output [15:0] hop_count,
output [7:0] submsg_rxd,
output submsg_rxdv,
output submsg_rxlast);
udp_outbound_chain_rx rx_inst
(.clk_50(clk_50), .clk_100(clk_100),
.rxd(rxd), .rxdv(rxdv), .rxlast(rxlast),
.hop_count(hop_count),
.submsg_rxd(submsg_rxd),
.submsg_rxdv(submsg_rxdv),
.submsg_rxlast(submsg_rxlast));
udp_outbound_chain_tx tx_inst
(.c(clk_50), .rxd(rxd), .rxdv(rxdv), .txd(txd), .txdv(txdv));
endmodule
`ifdef test_udp_outbound_chain
module udp_outbound_chain_tb();
wire c;
sim_clk #(125) clk_125(c);
reg [7:0] rxd;
reg rxdv, rxlast;
wire [7:0] submsg_rxd, txd;
wire submsg_rxdv, txdv;
udp_outbound_chain dut(.*);
wire [7:0] node2_txd, node2_submsg_rxd;
wire node2_txdv, node2_submsg_rxdv;
reg node2_rxlast;
udp_outbound_chain dut2
(.c(c),
.rxd(txd), .rxdv(txdv), .rxlast(node2_rxlast),
.txd(node2_txd), .txdv(node2_txdv),
.submsg_rxd(node2_submsg_rxd), .submsg_rxdv(node2_submsg_rxdv));
wire [7:0] node3_txd, node3_submsg_rxd;
wire node3_txdv, node3_submsg_rxdv;
reg node3_rxlast;
udp_outbound_chain dut3
(.c(c),
.rxd(node2_txd), .rxdv(node2_txdv), .rxlast(node3_rxlast),
.txd(node3_txd), .txdv(node3_txdv),
.submsg_rxd(node3_submsg_rxd), .submsg_rxdv(node3_submsg_rxdv));
localparam PKT_LEN = 24;
reg [7:0] pkt [PKT_LEN-1:0];
integer i;
initial begin
$dumpfile("udp_outbound_chain.lxt");
$dumpvars();
pkt[0] = 8'h1; // protocol low
pkt[1] = 8'h0; // protocol high
pkt[2] = 8'h0; // hop count low
pkt[3] = 8'h0; // hop count high
pkt[4] = 8'h0; // submsg addr low
pkt[5] = 8'h0; // submsg addr high
pkt[6] = 8'h2; // submsg len low
pkt[7] = 8'h0; // submsg len high
pkt[8] = 8'h12; // payload byte 0
pkt[9] = 8'h34; // payload byte 1
////
pkt[10] = 8'h1; // submsg addr low
pkt[11] = 8'h0; // submsg addr high
pkt[12] = 8'h2; // submsg len low
pkt[13] = 8'h0; // submsg len high
pkt[14] = 8'h56; // payload byte 0
pkt[15] = 8'h78; // payload byte 1
////
pkt[16] = 8'h2; // submsg addr low
pkt[17] = 8'h0; // submsg addr high
pkt[18] = 8'h4; // submsg len low
pkt[19] = 8'h0; // submsg len high
pkt[20] = 8'hab; // payload byte 0
pkt[21] = 8'hcd; // payload byte 1
pkt[22] = 8'hef; // payload byte 0
pkt[23] = 8'h42; // payload byte 1
////
rxd = 1'b0;
rxdv = 8'h0;
rxlast = 1'b0;
#100;
for (i = 0; i < PKT_LEN; i = i + 1) begin
wait(~c);
wait(c);
rxd <= pkt[i];
rxdv <= 1'b1;
end
wait(~c);
wait(c);
rxdv <= 1'b0;
rxd <= 8'h0;
for (i = 0; i < 20; i = i + 1) begin
wait(~c);
wait(c);
end
rxlast <= 1'b1;
node2_rxlast <= 1'b1;
node3_rxlast <= 1'b1;
wait(~c);
wait(c);
rxlast <= 1'b0;
node2_rxlast <= 1'b0;
node3_rxlast <= 1'b0;
#1000;
$finish();
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:22:28 05/15/2015
// Design Name:
// Module Name: cpu_behav
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cpu_behav
(
output [15:0] prog_cnt, // Program Counter
output [15:0] reg0, // Register 0.
input clk,
input rst
);
reg [15:0] pc; // Program Counter
reg [15:0] pc_next;
wire [15:0] inst_reg; // Instruction Register.
reg [15:0] reg_wdat;
wire [15:0] regA; // Register A out.
wire [15:0] regB; // Register B out.
wire [15:0] aluBIn;
wire [15:0] aluOut;
wire [4:0] shftIn;
wire [15:0] shftOut;
wire [15:0] dRamOut;
wire [15:0] psrOut;
wire [15:0] psrIn;
wire [15:0] extR;
wire [3:0] aluCmd; // ALU Command In.
wire [15:0] inst_out; // Instruction Register Output. Contains current opcode.
wire ext_signed; // Sign Extend Select
wire bSelect; // ALU B input select
wire shftSelect; // Shifter Input Select
wire aluSelect; // ALU OpCode Select
wire [1:0] wregSelect; // Register File Input Select
wire jmp; // Jump Select
wire branch; // Branch Select
wire rwren; // Register File Write Enable
wire dwren; // Data Memory Write Enable
assign prog_cnt = pc; // Program Counter Output.
// Instruction Memory - Read Only, Asynch Read
// Always Disabled Write Enable
// Connect 0 to din.
spinstram instr_mem(.dout(inst_reg), .din({(16){1'b0}}), .add(pc[7:0]), .clk(clk), .we(1'b0));
// Instruction Register
regparam #(.SIZE(16)) inst_register (.Q(inst_out), .D(inst_reg), .clk(clk), .rst(rst), .clken(1'b1));
// Data Memory - Read and Write, Asynch Read, Synch Write
spdataram data_mem(.dout(dRamOut), .din(regA), .add(regB[7:0]), .clk(clk), .we(dwren));
// Register File
regfileparam_behav #(.BITSIZE(16), .ADDSIZE(4)) reg_file
(.adat(regA),
.bdat(regB),
.zeroDat(reg0), // Register 0 output.
.ra(inst_out[11:8]), // Read A Address
.rb(inst_out[3:0]), // Read B Address
.rw(inst_out[11:8]), // Write Address
.wdat(reg_wdat),
.wren(rwren),
.clk(clk),
.rst(rst)
);
// Sign Extender with SIGN/UNSIGN Select
signex_param #(.EXTSIZE(16), .CURSIZE(8)) sign_extender (.extended(extR), .in(inst_out[7:0]), .sign(ext_signed));
assign aluBIn = (bSelect)?(regB):(extR);
assign aluCmd = (aluSelect)?(inst_out[15:12]):(inst_out[7:4]);
// ALU
alu_behav my_alu( .Y(aluOut), .flags(psrIn), .A(regA), .B(aluBIn), .sel(aluCmd));
assign shftIn = (shftSelect)?(inst_out[4:0]):(regB[4:0]);
// Shifter
shifter shft_unit(.yout(shftOut), .ain(regA), .bin(shftIn));
// Program Status Registers
regparam #(.SIZE(16)) psr (.Q(psrOut), .D(psrIn), .clk(clk), .rst(rst), .clken(1'b1));
// PC Next Logic
always @(*)
begin
if(jmp) begin
pc_next = regB; // Read from register.
end
else if(branch) begin
pc_next = pc + {{(8){inst_out[7]}},inst_out[7:0]}; // Sign Extended displacement.
end
else begin
pc_next = pc + 1'b1; // Default increment by 1.
end
end
// Control Unit
control_unit myControl(
.ext_signed(ext_signed), // Sign Extend Select
.bSelect(bSelect), // ALU B input select
.shftSelect(shftSelect), // Shifter Input Select
.aluSelect(aluSelect), // ALU OpCode Select
.wregSelect(wregSelect), // Register File Input Select
.jmp(jmp), // Jump Select
.branch(branch), // Branch Select
.rwren(rwren), // Register File Write Enable
.dwren(dwren), // Data Memory Write Enable
.instr(inst_out), // Instruction
.psr(psrOut) // Program Status Registers (Flags)
);
// Write Register File select
always @(*)
begin
case( wregSelect )
2'b11 : reg_wdat <= shftOut;
2'b10 : reg_wdat <= aluOut;
2'b01 : reg_wdat <= pc;
2'b00 : reg_wdat <= dRamOut;
endcase
end
// Program Counter
always @(posedge clk, negedge rst) begin
if(~rst) begin
pc <= 0;
end
else begin
pc <= pc_next;
end
end
endmodule
|
module dataMem(opcode,Rt,addr,clk,out);
input [5:0] opcode;
input [31:0] addr, Rt;
input clk;
output [31:0] out;
reg [31:0] memdata [255:0];
initial begin
memdata[0] = 32'b00000000000000000000000000000000;
memdata[1] = 32'b00000000000000000000000000000000;
memdata[2] = 32'b00000000000000000000000000000000;
memdata[3] = 32'b00000000000000000000000000000000;
memdata[4] = 32'b00000000000000000000000000000000;
memdata[5] = 32'b00000000000000000000000000000000;
memdata[6] = 32'b00000000000000000000000000000000;
memdata[7] = 32'b00000000000000000000000000000000;
memdata[8] = 32'b00000000000000000000000000000000;
memdata[9] = 32'b00000000000000000000000000000000;
memdata[10] = 32'b00000000000000000000000000000000;
memdata[11] = 32'b00000000000000000000000000000000;
memdata[12] = 32'b00000000000000000000000000000000;
memdata[13] = 32'b00000000000000000000000000000000;
memdata[14] = 32'b00000000000000000000000000000000;
memdata[15] = 32'b00000000000000000000000000000000;
memdata[16] = 32'b00000000000000000000000000000000;
memdata[17] = 32'b00000000000000000000000000000000;
memdata[18] = 32'b00000000000000000000000000000000;
memdata[19] = 32'b00000000000000000000000000000000;
end
assign out = memdata[addr];
always @(negedge clk)
begin
if(opcode==6'b101011)
begin
memdata[addr] = Rt;
end
end
endmodule
|
// ======================================================================
// FindMeHW.v generated from TopDesign.cysch
// 09/24/2016 at 13:10
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4G 2
`define CYDEV_CHIP_REVISION_4G_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4G_ES 17
`define CYDEV_CHIP_REVISION_4G_ES2 33
`define CYDEV_CHIP_MEMBER_4U 3
`define CYDEV_CHIP_REVISION_4U_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4E 4
`define CYDEV_CHIP_REVISION_4E_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4O 5
`define CYDEV_CHIP_REVISION_4O_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4N 6
`define CYDEV_CHIP_REVISION_4N_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4D 7
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4J 8
`define CYDEV_CHIP_REVISION_4J_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4K 9
`define CYDEV_CHIP_REVISION_4K_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4H 10
`define CYDEV_CHIP_REVISION_4H_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4A 11
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4F 12
`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0
`define CYDEV_CHIP_MEMBER_4F 13
`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0
`define CYDEV_CHIP_MEMBER_4M 14
`define CYDEV_CHIP_REVISION_4M_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4L 15
`define CYDEV_CHIP_REVISION_4L_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4I 16
`define CYDEV_CHIP_REVISION_4I_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4C 17
`define CYDEV_CHIP_REVISION_4C_PRODUCTION 0
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5B 18
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_MEMBER_5A 19
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_FAMILY_USED 2
`define CYDEV_CHIP_MEMBER_USED 12
`define CYDEV_CHIP_REVISION_USED 0
// Component: or_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`endif
// Component: cy_constant_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`endif
// BLE_v3_10(AutopopulateWhitelist=true, EnableExternalPAcontrol=false, EnableExternalPrepWriteBuff=false, EnableL2capLogicalChannels=true, EnableLinkLayerPrivacy=false, GapConfig=<?xml version="1.0" encoding="utf-16"?>\r\n<CyGapConfiguration xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema">\r\n <DevAddress>00A050000000</DevAddress>\r\n <SiliconGeneratedAddress>true</SiliconGeneratedAddress>\r\n <MtuSize>23</MtuSize>\r\n <MaxTxPayloadSize>27</MaxTxPayloadSize>\r\n <MaxRxPayloadSize>27</MaxRxPayloadSize>\r\n <TxPowerLevel>0</TxPowerLevel>\r\n <TxPowerLevelConnection>0</TxPowerLevelConnection>\r\n <TxPowerLevelAdvScan>0</TxPowerLevelAdvScan>\r\n <SecurityConfig>\r\n <SecurityMode>SECURITY_MODE_1</SecurityMode>\r\n <SecurityLevel>NO_SECURITY</SecurityLevel>\r\n <StrictPairing>false</StrictPairing>\r\n <KeypressNotifications>false</KeypressNotifications>\r\n <IOCapability>DISPLAY</IOCapability>\r\n <PairingMethod>JUST_WORKS</PairingMethod>\r\n <Bonding>BOND</Bonding>\r\n <MaxBondedDevices>4</MaxBondedDevices>\r\n <AutoPopWhitelistBondedDev>true</AutoPopWhitelistBondedDev>\r\n <MaxWhitelistSize>8</MaxWhitelistSize>\r\n <EnableLinkLayerPrivacy>false</EnableLinkLayerPrivacy>\r\n <MaxResolvableDevices>8</MaxResolvableDevices>\r\n <EncryptionKeySize>16</EncryptionKeySize>\r\n </SecurityConfig>\r\n <AdvertisementConfig>\r\n <AdvScanMode>FAST_CONNECTION</AdvScanMode>\r\n <AdvFastScanInterval>\r\n <Minimum>20</Minimum>\r\n <Maximum>30</Maximum>\r\n </AdvFastScanInterval>\r\n <AdvReducedScanInterval>\r\n <Minimum>1000</Minimum>\r\n <Maximum>10240</Maximum>\r\n </AdvReducedScanInterval>\r\n <AdvDiscoveryMode>GENERAL</AdvDiscoveryMode>\r\n <AdvType>CONNECTABLE_UNDIRECTED</AdvType>\r\n <AdvFilterPolicy>SCAN_REQUEST_ANY_CONNECT_REQUEST_ANY</AdvFilterPolicy>\r\n <AdvChannelMap>ALL</AdvChannelMap>\r\n <AdvFastTimeout>30</AdvFastTimeout>\r\n <AdvReducedTimeout>150</AdvReducedTimeout>\r\n <ConnectionInterval>\r\n <Minimum>7.5</Minimum>\r\n <Maximum>50</Maximum>\r\n </ConnectionInterval>\r\n <ConnectionSlaveLatency>0</ConnectionSlaveLatency>\r\n <ConnectionTimeout>10000</ConnectionTimeout>\r\n </AdvertisementConfig>\r\n <ScanConfig>\r\n <ScanFastWindow>30</ScanFastWindow>\r\n <ScanFastInterval>30</ScanFastInterval>\r\n <ScanTimeout>30</ScanTimeout>\r\n <ScanReducedWindow>1125</ScanReducedWindow>\r\n <ScanReducedInterval>1280</ScanReducedInterval>\r\n <ScanReducedTimeout>150</ScanReducedTimeout>\r\n <EnableReducedScan>true</EnableReducedScan>\r\n <ScanDiscoveryMode>GENERAL</ScanDiscoveryMode>\r\n <ScanningState>ACTIVE</ScanningState>\r\n <ScanFilterPolicy>ACCEPT_ALL_ADV_PACKETS</ScanFilterPolicy>\r\n <DuplicateFiltering>false</DuplicateFiltering>\r\n <ConnectionInterval>\r\n <Minimum>7.5</Minimum>\r\n <Maximum>50</Maximum>\r\n </ConnectionInterval>\r\n <ConnectionSlaveLatency>0</ConnectionSlaveLatency>\r\n <ConnectionTimeout>10000</ConnectionTimeout>\r\n </ScanConfig>\r\n <AdvertisementPacket>\r\n <PacketType>ADVERTISEMENT</PacketType>\r\n <Items>\r\n <CyADStructure>\r\n <ADType>1</ADType>\r\n <ADData>06</ADData>\r\n </CyADStructure>\r\n <CyADStructure>\r\n <ADType>9</ADType>\r\n <ADData>4D:4D:5F:42:4C:45</ADData>\r\n </CyADStructure>\r\n <CyADStructure>\r\n <ADType>3</ADType>\r\n <ADData>02:18</ADData>\r\n </CyADStructure>\r\n </Items>\r\n <IncludedServicesServiceUuid>\r\n <int>11</int>\r\n </IncludedServicesServiceUuid>\r\n <IncludedServicesServiceSolicitation />\r\n <IncludedServicesServiceData />\r\n </AdvertisementPacket>\r\n <ScanResponsePacket>\r\n <PacketType>SCAN_RESPONSE</PacketType>\r\n <Items />\r\n <IncludedServicesServiceUuid />\r\n <IncludedServicesServiceSolicitation />\r\n <IncludedServicesServiceData />\r\n </ScanResponsePacket>\r\n</CyGapConfiguration>, HalBaudRate=115200, ImportFilePath=, KeypressNotifications=false, L2capMpsSize=23, L2capMtuSize=23, L2capNumChannels=1, L2capNumPsm=1, LLMaxRxPayloadSize=27, LLMaxTxPayloadSize=27, MaxAttrNoOfBuffer=1, MaxBondedDevices=4, MaxResolvableDevices=8, MaxWhitelistSize=8, Mode=0, ProfileConfig=<?xml version="1.0" encoding="utf-16"?>\r\n<Profile xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema" ID="1" DisplayName="Find Me" Name="Find Me" Type="org.bluetooth.profile.find_me">\r\n <CyProfileRole ID="2" DisplayName="Find Me Target" Name="Find Me Target">\r\n <CyService ID="3" DisplayName="Generic Access" Name="Generic Access" Type="org.bluetooth.service.generic_access" UUID="1800">\r\n <CyCharacteristic ID="4" DisplayName="Device Name" Name="Device Name" Type="org.bluetooth.characteristic.gap.device_name" UUID="2A00">\r\n <Field Name="Name">\r\n <DataFormat>utf8s</DataFormat>\r\n <ByteLength>6</ByteLength>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>MM_BLE</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <CyCharacteristic ID="5" DisplayName="Appearance" Name="Appearance" Type="org.bluetooth.characteristic.gap.appearance" UUID="2A01">\r\n <Field Name="Category">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>ENUM</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <CyCharacteristic ID="6" DisplayName="Peripheral Preferred Connection Parameters" Name="Peripheral Preferred Connection Parameters" Type="org.bluetooth.characteristic.gap.peripheral_preferred_connection_parameters" UUID="2A04">\r\n <Field Name="Minimum Connection Interval">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>6</Minimum>\r\n <Maximum>3200</Maximum>\r\n </Range>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>0x0006</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="Maximum Connection Interval">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>6</Minimum>\r\n <Maximum>3200</Maximum>\r\n </Range>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>0x0028</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="Slave Latency">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>0</Minimum>\r\n <Maximum>1000</Maximum>\r\n </Range>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>0</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="Connection Supervision Timeout Multiplier">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>10</Minimum>\r\n <Maximum>3200</Maximum>\r\n </Range>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>0x03E8</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <CyCharacteristic ID="7" DisplayName="Central Address Resolution" Name="Central Address Resolution" Type="org.bluetooth.characteristic.gap.central_address_resolution" UUID="2AA6">\r\n <Field Name="Central Address Resolution Support">\r\n <DataFormat>uint8</DataFormat>\r\n <ByteLength>1</ByteLength>\r\n <ValueType>ENUM</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <CyService ID="8" DisplayName="Generic Attribute" Name="Generic Attribute" Type="org.bluetooth.service.generic_attribute" UUID="1801">\r\n <CyCharacteristic ID="9" DisplayName="Service Changed" Name="Service Changed" Type="org.bluetooth.characteristic.gatt.service_changed" UUID="2A05">\r\n <CyDescriptor ID="10" DisplayName="Client Characteristic Configuration" Name="Client Characteristic Configuration" Type="org.bluetooth.descriptor.gatt.client_characteristic_configuration" UUID="2902">\r\n <Field Name="Properties">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>0</Minimum>\r\n <Maximum>3</Maximum>\r\n </Range>\r\n <ValueType>BITFIELD</ValueType>\r\n <Bit>\r\n <Index>0</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Notifications disabled" />\r\n <Enumeration key="1" value="Notifications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <Bit>\r\n <Index>1</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Indications disabled" />\r\n <Enumeration key="1" value="Indications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="WRITE" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>READ_WRITE</AccessPermission>\r\n </Permission>\r\n </CyDescriptor>\r\n <Field Name="Start of Affected Attribute Handle Range">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>1</Minimum>\r\n <Maximum>65535</Maximum>\r\n </Range>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="End of Affected Attribute Handle Range">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>1</Minimum>\r\n <Maximum>65535</Maximum>\r\n </Range>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="INDICATE" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>NONE</AccessPermission>\r\n </Permission>\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <CyService ID="11" DisplayName="Immediate Alert" Name="Immediate Alert" Type="org.bluetooth.service.immediate_alert" UUID="1802">\r\n <CyCharacteristic ID="12" DisplayName="Alert Level" Name="Alert Level" Type="org.bluetooth.characteristic.alert_level" UUID="2A06">\r\n <Field Name="Alert Level">\r\n <DataFormat>uint8</DataFormat>\r\n <ByteLength>1</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>0</Minimum>\r\n <Maximum>2</Maximum>\r\n </Range>\r\n <ValueType>ENUM</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="WRITE_WITHOUT_RESPONSE" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>WRITE</AccessPermission>\r\n </Permission>\r\n </CyCharacteristic>\r\n <Declaration>PrimarySingleInstance</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <CyService ID="28" DisplayName="Custom Alert" Name="Custom Service" Type="org.bluetooth.service.custom" UUID="0000000000001000800000805F9B34FB">\r\n <CyCharacteristic ID="29" DisplayName="Custom Alert Level" Name="Custom Characteristic" Type="org.bluetooth.characteristic.custom" UUID="0000000000001000800000805F9B34FB">\r\n <CyDescriptor ID="30" DisplayName="Characteristic User Description" Name="Characteristic User Description" Type="org.bluetooth.descriptor.gatt.characteristic_user_description" UUID="2901">\r\n <Field Name="User Description">\r\n <DataFormat>utf8s</DataFormat>\r\n <ByteLength>12</ByteLength>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>Custom Alert</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="false" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyDescriptor>\r\n <Field Name="Alert_Lvl">\r\n <DataFormat>uint8</DataFormat>\r\n <ByteLength>1</ByteLength>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>0xAF</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="BROADCAST" Present="false" Mandatory="false" />\r\n <Property Type="READ" Present="true" Mandatory="false" />\r\n <Property Type="WRITE" Present="true" Mandatory="false" />\r\n <Property Type="WRITE_WITHOUT_RESPONSE" Present="false" Mandatory="false" />\r\n <Property Type="NOTIFY" Present="false" Mandatory="false" />\r\n <Property Type="INDICATE" Present="false" Mandatory="false" />\r\n <Property Type="AUTHENTICATED_SIGNED_WRITES" Present="false" Mandatory="false" />\r\n <Property Type="RELIABLE_WRITE" Present="false" Mandatory="false" />\r\n <Property Type="WRITABLE_AUXILIARIES" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>READ_WRITE</AccessPermission>\r\n </Permission>\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <ProfileRoleIndex>0</ProfileRoleIndex>\r\n <RoleType>SERVER</RoleType>\r\n </CyProfileRole>\r\n <GapRole>PERIPHERAL</GapRole>\r\n</Profile>, SharingMode=0, StackMode=3, StrictPairing=false, UseDeepSleep=true, CY_API_CALLBACK_HEADER_INCLUDE=#include "cyapicallbacks.h", CY_COMPONENT_NAME=BLE_v3_10, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=BLE_v3_10.pdf, CY_FITTER_NAME=BLE, CY_INSTANCE_SHORT_NAME=BLE, CY_MAJOR_VERSION=3, CY_MINOR_VERSION=10, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 3.3 CP3, INSTANCE_NAME=BLE, )
module BLE_v3_10_0 (
clk,
pa_en);
output clk;
output pa_en;
wire Net_55;
wire Net_60;
wire Net_53;
wire Net_72;
wire Net_71;
wire Net_70;
wire Net_15;
wire Net_14;
cy_m0s8_ble_v1_0 cy_m0s8_ble (
.interrupt(Net_15),
.rf_ext_pa_en(pa_en));
cy_isr_v1_0
#(.int_type(2'b10))
bless_isr
(.int_signal(Net_15));
cy_clock_v1_0
#(.id("576a6461-7d35-4999-9200-fb53119930bc/5ae6fa4d-f41a-4a35-8821-7ce70389cb0c"),
.source_clock_id("9A908CA6-5BB3-4db0-B098-959E5D90882B"),
.divisor(0),
.period("0"),
.is_direct(1),
.is_digital(0))
LFCLK
(.clock_out(Net_53));
assign clk = Net_53 | Net_55;
assign Net_55 = 1'h0;
endmodule
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// TCPWM_P4_v2_10(Clock_CheckTolerance=true, Clock_desired_freq=12, Clock_desired_freq_unit=6, Clock_divisor=1, Clock_FractDividerDenominator=0, Clock_FractDividerNumerator=0, Clock_FractDividerUsed=false, Clock_is_direct=false, Clock_is_divider=false, Clock_is_freq=true, Clock_minus_tolerance=5, Clock_ph_align_clock_id=, Clock_ph_align_clock_name=, Clock_plus_tolerance=5, Clock_source_clock_id=, Clock_source_clock_name=, PinVisibility_index=false, PinVisibility_kill=false, PinVisibility_phiA=false, PinVisibility_phiB=false, PinVisibility_switch=false, PWMCompare=0, PWMCompareBuf=65535, PWMCompareSwap=0, PWMCountMode=3, PWMCountPresent=false, PWMDeadTimeCycle=0, PWMInterruptMask=1, PWMKillEvent=0, PWMLinenSignal=0, PWMLineSignal=0, PWMMode=4, PWMPeriod=1000, PWMPeriodBuf=65535, PWMPeriodSwap=0, PWMPrescaler=0, PWMReloadMode=0, PWMReloadPresent=false, PWMRunMode=0, PWMSetAlign=0, PWMStartMode=0, PWMStartPresent=false, PWMStopEvent=0, PWMStopMode=0, PWMStopPresent=false, PWMSwitchMode=0, PWMSwitchPresent=false, QuadAutoStart=true, QuadEncodingModes=0, QuadIndexMode=0, QuadIndexPresent=false, QuadInterruptMask=1, QuadPhiAMode=3, QuadPhiBMode=3, QuadStopMode=0, QuadStopPresent=false, TCCaptureMode=0, TCCapturePresent=false, TCCompare=65535, TCCompareBuf=65535, TCCompareSwap=0, TCCompCapMode=2, TCCountingModes=0, TCCountMode=3, TCCountPresent=false, TCInterruptMask=1, TCPeriod=65535, TCPrescaler=0, TCPWMCapturePresent=false, TCPWMConfig=7, TCPWMCountPresent=false, TCPWMReloadPresent=false, TCPWMStartPresent=false, TCPWMStopPresent=false, TCReloadMode=0, TCReloadPresent=false, TCRunMode=0, TCStartMode=0, TCStartPresent=false, TCStopMode=0, TCStopPresent=false, TermMode_capture=0, TermMode_cc=0, TermMode_clock=0, TermMode_count=0, TermMode_interrupt=0, TermMode_line=0, TermMode_line_n=0, TermMode_ov=0, TermMode_reload=0, TermMode_start=0, TermMode_stop=0, TermMode_un=0, TermModeStates=, TermVisibility_capture=false, TermVisibility_cc=true, TermVisibility_clock=true, TermVisibility_count=false, TermVisibility_interrupt=true, TermVisibility_line=true, TermVisibility_line_n=true, TermVisibility_ov=true, TermVisibility_reload=false, TermVisibility_start=false, TermVisibility_stop=false, TermVisibility_un=true, CY_API_CALLBACK_HEADER_INCLUDE=#include "cyapicallbacks.h", CY_COMPONENT_NAME=TCPWM_P4_v2_10, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=<:default:>, CY_FITTER_NAME=PWM, CY_INSTANCE_SHORT_NAME=PWM, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=10, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 3.3 CP3, INSTANCE_NAME=PWM, )
module TCPWM_P4_v2_10_1 (
stop,
count,
reload,
start,
capture,
interrupt,
ov,
un,
cc,
clock,
line,
line_n);
input stop;
input count;
input reload;
input start;
input capture;
output interrupt;
output ov;
output un;
output cc;
input clock;
output line;
output line_n;
wire Net_64;
wire Net_63;
wire Net_85;
wire Net_62;
wire Net_110;
wire Net_95;
wire Net_106;
wire Net_104;
wire Net_109;
wire Net_98;
wire Net_108;
wire Net_101;
wire Net_66;
wire Net_81;
wire Net_75;
wire Net_69;
wire Net_82;
wire Net_72;
cy_m0s8_tcpwm_v1_0 cy_m0s8_tcpwm_1 (
.capture(Net_75),
.underflow(un),
.overflow(ov),
.line_out_compl(line_n),
.line_out(line),
.compare_match(cc),
.interrupt(interrupt),
.count(Net_69),
.reload(Net_66),
.stop(Net_82),
.start(Net_72),
.clock(Net_81));
// VMux_reload (cy_virtualmux_v1_0)
assign Net_66 = reload;
// VMux_count (cy_virtualmux_v1_0)
assign Net_69 = count;
// VMux_start (cy_virtualmux_v1_0)
assign Net_72 = start;
// VMux_capture (cy_virtualmux_v1_0)
assign Net_75 = capture;
// VMux_stop (cy_virtualmux_v1_0)
assign Net_82 = stop;
// VMux_clock (cy_virtualmux_v1_0)
assign Net_81 = clock;
endmodule
// top
module top ;
wire Net_41;
wire Net_26;
wire Net_25;
wire Net_24;
wire Net_23;
wire Net_22;
wire Net_21;
wire Net_20;
wire Net_19;
wire Net_18;
wire Net_17;
wire Net_62;
wire Net_61;
wire Net_42;
wire Net_28;
BLE_v3_10_0 BLE (
.clk(Net_61),
.pa_en(Net_62));
wire [0:0] tmpOE__RED_LED_net;
wire [0:0] tmpFB_0__RED_LED_net;
wire [0:0] tmpIO_0__RED_LED_net;
wire [0:0] tmpINTERRUPT_0__RED_LED_net;
electrical [0:0] tmpSIOVREF__RED_LED_net;
cy_psoc3_pins_v1_10
#(.id("e851a3b9-efb8-48be-bbb8-b303b216c393"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
RED_LED
(.oe(tmpOE__RED_LED_net),
.y({Net_42}),
.fb({tmpFB_0__RED_LED_net[0:0]}),
.io({tmpIO_0__RED_LED_net[0:0]}),
.siovref(tmpSIOVREF__RED_LED_net),
.interrupt({tmpINTERRUPT_0__RED_LED_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__RED_LED_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
TCPWM_P4_v2_10_1 PWM (
.stop(1'b0),
.reload(1'b0),
.start(1'b0),
.count(1'b1),
.capture(1'b0),
.interrupt(Net_22),
.ov(Net_23),
.un(Net_24),
.cc(Net_25),
.line(Net_26),
.line_n(Net_42),
.clock(Net_28));
cy_clock_v1_0
#(.id("b27a5c0b-41c3-4e65-9953-4f275842d78c"),
.source_clock_id(""),
.divisor(0),
.period("1000000000000"),
.is_direct(0),
.is_digital(0))
Clock
(.clock_out(Net_28));
endmodule
|
// system_acl_iface_mm_interconnect_2.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module system_acl_iface_mm_interconnect_2 (
input wire pll_outclk0_clk, // pll_outclk0.clk
input wire address_span_extender_kernel_reset_reset_bridge_in_reset_reset, // address_span_extender_kernel_reset_reset_bridge_in_reset.reset
input wire hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset, // hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset.reset
input wire [31:0] address_span_extender_kernel_expanded_master_address, // address_span_extender_kernel_expanded_master.address
output wire address_span_extender_kernel_expanded_master_waitrequest, // .waitrequest
input wire [4:0] address_span_extender_kernel_expanded_master_burstcount, // .burstcount
input wire [31:0] address_span_extender_kernel_expanded_master_byteenable, // .byteenable
input wire address_span_extender_kernel_expanded_master_read, // .read
output wire [255:0] address_span_extender_kernel_expanded_master_readdata, // .readdata
output wire address_span_extender_kernel_expanded_master_readdatavalid, // .readdatavalid
input wire address_span_extender_kernel_expanded_master_write, // .write
input wire [255:0] address_span_extender_kernel_expanded_master_writedata, // .writedata
output wire [26:0] hps_f2h_sdram0_data_address, // hps_f2h_sdram0_data.address
output wire hps_f2h_sdram0_data_write, // .write
output wire hps_f2h_sdram0_data_read, // .read
input wire [255:0] hps_f2h_sdram0_data_readdata, // .readdata
output wire [255:0] hps_f2h_sdram0_data_writedata, // .writedata
output wire [7:0] hps_f2h_sdram0_data_burstcount, // .burstcount
output wire [31:0] hps_f2h_sdram0_data_byteenable, // .byteenable
input wire hps_f2h_sdram0_data_readdatavalid, // .readdatavalid
input wire hps_f2h_sdram0_data_waitrequest // .waitrequest
);
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_waitrequest; // address_span_extender_kernel_expanded_master_agent:av_waitrequest -> address_span_extender_kernel_expanded_master_translator:uav_waitrequest
wire [255:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdata; // address_span_extender_kernel_expanded_master_agent:av_readdata -> address_span_extender_kernel_expanded_master_translator:uav_readdata
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_debugaccess; // address_span_extender_kernel_expanded_master_translator:uav_debugaccess -> address_span_extender_kernel_expanded_master_agent:av_debugaccess
wire [31:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_address; // address_span_extender_kernel_expanded_master_translator:uav_address -> address_span_extender_kernel_expanded_master_agent:av_address
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_read; // address_span_extender_kernel_expanded_master_translator:uav_read -> address_span_extender_kernel_expanded_master_agent:av_read
wire [31:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_byteenable; // address_span_extender_kernel_expanded_master_translator:uav_byteenable -> address_span_extender_kernel_expanded_master_agent:av_byteenable
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdatavalid; // address_span_extender_kernel_expanded_master_agent:av_readdatavalid -> address_span_extender_kernel_expanded_master_translator:uav_readdatavalid
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_lock; // address_span_extender_kernel_expanded_master_translator:uav_lock -> address_span_extender_kernel_expanded_master_agent:av_lock
wire address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_write; // address_span_extender_kernel_expanded_master_translator:uav_write -> address_span_extender_kernel_expanded_master_agent:av_write
wire [255:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_writedata; // address_span_extender_kernel_expanded_master_translator:uav_writedata -> address_span_extender_kernel_expanded_master_agent:av_writedata
wire [9:0] address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_burstcount; // address_span_extender_kernel_expanded_master_translator:uav_burstcount -> address_span_extender_kernel_expanded_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> address_span_extender_kernel_expanded_master_agent:rp_valid
wire [363:0] rsp_mux_src_data; // rsp_mux:src_data -> address_span_extender_kernel_expanded_master_agent:rp_data
wire rsp_mux_src_ready; // address_span_extender_kernel_expanded_master_agent:rp_ready -> rsp_mux:src_ready
wire [0:0] rsp_mux_src_channel; // rsp_mux:src_channel -> address_span_extender_kernel_expanded_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> address_span_extender_kernel_expanded_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> address_span_extender_kernel_expanded_master_agent:rp_endofpacket
wire [255:0] hps_f2h_sdram0_data_agent_m0_readdata; // hps_f2h_sdram0_data_translator:uav_readdata -> hps_f2h_sdram0_data_agent:m0_readdata
wire hps_f2h_sdram0_data_agent_m0_waitrequest; // hps_f2h_sdram0_data_translator:uav_waitrequest -> hps_f2h_sdram0_data_agent:m0_waitrequest
wire hps_f2h_sdram0_data_agent_m0_debugaccess; // hps_f2h_sdram0_data_agent:m0_debugaccess -> hps_f2h_sdram0_data_translator:uav_debugaccess
wire [31:0] hps_f2h_sdram0_data_agent_m0_address; // hps_f2h_sdram0_data_agent:m0_address -> hps_f2h_sdram0_data_translator:uav_address
wire [31:0] hps_f2h_sdram0_data_agent_m0_byteenable; // hps_f2h_sdram0_data_agent:m0_byteenable -> hps_f2h_sdram0_data_translator:uav_byteenable
wire hps_f2h_sdram0_data_agent_m0_read; // hps_f2h_sdram0_data_agent:m0_read -> hps_f2h_sdram0_data_translator:uav_read
wire hps_f2h_sdram0_data_agent_m0_readdatavalid; // hps_f2h_sdram0_data_translator:uav_readdatavalid -> hps_f2h_sdram0_data_agent:m0_readdatavalid
wire hps_f2h_sdram0_data_agent_m0_lock; // hps_f2h_sdram0_data_agent:m0_lock -> hps_f2h_sdram0_data_translator:uav_lock
wire [255:0] hps_f2h_sdram0_data_agent_m0_writedata; // hps_f2h_sdram0_data_agent:m0_writedata -> hps_f2h_sdram0_data_translator:uav_writedata
wire hps_f2h_sdram0_data_agent_m0_write; // hps_f2h_sdram0_data_agent:m0_write -> hps_f2h_sdram0_data_translator:uav_write
wire [12:0] hps_f2h_sdram0_data_agent_m0_burstcount; // hps_f2h_sdram0_data_agent:m0_burstcount -> hps_f2h_sdram0_data_translator:uav_burstcount
wire hps_f2h_sdram0_data_agent_rf_source_valid; // hps_f2h_sdram0_data_agent:rf_source_valid -> hps_f2h_sdram0_data_agent_rsp_fifo:in_valid
wire [364:0] hps_f2h_sdram0_data_agent_rf_source_data; // hps_f2h_sdram0_data_agent:rf_source_data -> hps_f2h_sdram0_data_agent_rsp_fifo:in_data
wire hps_f2h_sdram0_data_agent_rf_source_ready; // hps_f2h_sdram0_data_agent_rsp_fifo:in_ready -> hps_f2h_sdram0_data_agent:rf_source_ready
wire hps_f2h_sdram0_data_agent_rf_source_startofpacket; // hps_f2h_sdram0_data_agent:rf_source_startofpacket -> hps_f2h_sdram0_data_agent_rsp_fifo:in_startofpacket
wire hps_f2h_sdram0_data_agent_rf_source_endofpacket; // hps_f2h_sdram0_data_agent:rf_source_endofpacket -> hps_f2h_sdram0_data_agent_rsp_fifo:in_endofpacket
wire hps_f2h_sdram0_data_agent_rsp_fifo_out_valid; // hps_f2h_sdram0_data_agent_rsp_fifo:out_valid -> hps_f2h_sdram0_data_agent:rf_sink_valid
wire [364:0] hps_f2h_sdram0_data_agent_rsp_fifo_out_data; // hps_f2h_sdram0_data_agent_rsp_fifo:out_data -> hps_f2h_sdram0_data_agent:rf_sink_data
wire hps_f2h_sdram0_data_agent_rsp_fifo_out_ready; // hps_f2h_sdram0_data_agent:rf_sink_ready -> hps_f2h_sdram0_data_agent_rsp_fifo:out_ready
wire hps_f2h_sdram0_data_agent_rsp_fifo_out_startofpacket; // hps_f2h_sdram0_data_agent_rsp_fifo:out_startofpacket -> hps_f2h_sdram0_data_agent:rf_sink_startofpacket
wire hps_f2h_sdram0_data_agent_rsp_fifo_out_endofpacket; // hps_f2h_sdram0_data_agent_rsp_fifo:out_endofpacket -> hps_f2h_sdram0_data_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> hps_f2h_sdram0_data_agent:cp_valid
wire [363:0] cmd_mux_src_data; // cmd_mux:src_data -> hps_f2h_sdram0_data_agent:cp_data
wire cmd_mux_src_ready; // hps_f2h_sdram0_data_agent:cp_ready -> cmd_mux:src_ready
wire [0:0] cmd_mux_src_channel; // cmd_mux:src_channel -> hps_f2h_sdram0_data_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> hps_f2h_sdram0_data_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> hps_f2h_sdram0_data_agent:cp_endofpacket
wire address_span_extender_kernel_expanded_master_agent_cp_valid; // address_span_extender_kernel_expanded_master_agent:cp_valid -> router:sink_valid
wire [363:0] address_span_extender_kernel_expanded_master_agent_cp_data; // address_span_extender_kernel_expanded_master_agent:cp_data -> router:sink_data
wire address_span_extender_kernel_expanded_master_agent_cp_ready; // router:sink_ready -> address_span_extender_kernel_expanded_master_agent:cp_ready
wire address_span_extender_kernel_expanded_master_agent_cp_startofpacket; // address_span_extender_kernel_expanded_master_agent:cp_startofpacket -> router:sink_startofpacket
wire address_span_extender_kernel_expanded_master_agent_cp_endofpacket; // address_span_extender_kernel_expanded_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [363:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [0:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire hps_f2h_sdram0_data_agent_rp_valid; // hps_f2h_sdram0_data_agent:rp_valid -> router_001:sink_valid
wire [363:0] hps_f2h_sdram0_data_agent_rp_data; // hps_f2h_sdram0_data_agent:rp_data -> router_001:sink_data
wire hps_f2h_sdram0_data_agent_rp_ready; // router_001:sink_ready -> hps_f2h_sdram0_data_agent:rp_ready
wire hps_f2h_sdram0_data_agent_rp_startofpacket; // hps_f2h_sdram0_data_agent:rp_startofpacket -> router_001:sink_startofpacket
wire hps_f2h_sdram0_data_agent_rp_endofpacket; // hps_f2h_sdram0_data_agent:rp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> rsp_demux:sink_valid
wire [363:0] router_001_src_data; // router_001:src_data -> rsp_demux:sink_data
wire router_001_src_ready; // rsp_demux:sink_ready -> router_001:src_ready
wire [0:0] router_001_src_channel; // router_001:src_channel -> rsp_demux:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [363:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [0:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [363:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [0:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire hps_f2h_sdram0_data_agent_rdata_fifo_src_valid; // hps_f2h_sdram0_data_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [257:0] hps_f2h_sdram0_data_agent_rdata_fifo_src_data; // hps_f2h_sdram0_data_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire hps_f2h_sdram0_data_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> hps_f2h_sdram0_data_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> hps_f2h_sdram0_data_agent:rdata_fifo_sink_valid
wire [257:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> hps_f2h_sdram0_data_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // hps_f2h_sdram0_data_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> hps_f2h_sdram0_data_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (256),
.AV_BURSTCOUNT_W (5),
.AV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (10),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) address_span_extender_kernel_expanded_master_translator (
.clk (pll_outclk0_clk), // clk.clk
.reset (address_span_extender_kernel_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_read), // .read
.uav_write (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (address_span_extender_kernel_expanded_master_address), // avalon_anti_master_0.address
.av_waitrequest (address_span_extender_kernel_expanded_master_waitrequest), // .waitrequest
.av_burstcount (address_span_extender_kernel_expanded_master_burstcount), // .burstcount
.av_byteenable (address_span_extender_kernel_expanded_master_byteenable), // .byteenable
.av_read (address_span_extender_kernel_expanded_master_read), // .read
.av_readdata (address_span_extender_kernel_expanded_master_readdata), // .readdata
.av_readdatavalid (address_span_extender_kernel_expanded_master_readdatavalid), // .readdatavalid
.av_write (address_span_extender_kernel_expanded_master_write), // .write
.av_writedata (address_span_extender_kernel_expanded_master_writedata), // .writedata
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (27),
.AV_DATA_W (256),
.UAV_DATA_W (256),
.AV_BURSTCOUNT_W (8),
.AV_BYTEENABLE_W (32),
.UAV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (13),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hps_f2h_sdram0_data_translator (
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hps_f2h_sdram0_data_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hps_f2h_sdram0_data_agent_m0_burstcount), // .burstcount
.uav_read (hps_f2h_sdram0_data_agent_m0_read), // .read
.uav_write (hps_f2h_sdram0_data_agent_m0_write), // .write
.uav_waitrequest (hps_f2h_sdram0_data_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hps_f2h_sdram0_data_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hps_f2h_sdram0_data_agent_m0_byteenable), // .byteenable
.uav_readdata (hps_f2h_sdram0_data_agent_m0_readdata), // .readdata
.uav_writedata (hps_f2h_sdram0_data_agent_m0_writedata), // .writedata
.uav_lock (hps_f2h_sdram0_data_agent_m0_lock), // .lock
.uav_debugaccess (hps_f2h_sdram0_data_agent_m0_debugaccess), // .debugaccess
.av_address (hps_f2h_sdram0_data_address), // avalon_anti_slave_0.address
.av_write (hps_f2h_sdram0_data_write), // .write
.av_read (hps_f2h_sdram0_data_read), // .read
.av_readdata (hps_f2h_sdram0_data_readdata), // .readdata
.av_writedata (hps_f2h_sdram0_data_writedata), // .writedata
.av_burstcount (hps_f2h_sdram0_data_burstcount), // .burstcount
.av_byteenable (hps_f2h_sdram0_data_byteenable), // .byteenable
.av_readdatavalid (hps_f2h_sdram0_data_readdatavalid), // .readdatavalid
.av_waitrequest (hps_f2h_sdram0_data_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (363),
.PKT_ORI_BURST_SIZE_L (361),
.PKT_RESPONSE_STATUS_H (360),
.PKT_RESPONSE_STATUS_L (359),
.PKT_QOS_H (348),
.PKT_QOS_L (348),
.PKT_DATA_SIDEBAND_H (346),
.PKT_DATA_SIDEBAND_L (346),
.PKT_ADDR_SIDEBAND_H (345),
.PKT_ADDR_SIDEBAND_L (345),
.PKT_BURST_TYPE_H (344),
.PKT_BURST_TYPE_L (343),
.PKT_CACHE_H (358),
.PKT_CACHE_L (355),
.PKT_THREAD_ID_H (351),
.PKT_THREAD_ID_L (351),
.PKT_BURST_SIZE_H (342),
.PKT_BURST_SIZE_L (340),
.PKT_TRANS_EXCLUSIVE (325),
.PKT_TRANS_LOCK (324),
.PKT_BEGIN_BURST (347),
.PKT_PROTECTION_H (354),
.PKT_PROTECTION_L (352),
.PKT_BURSTWRAP_H (339),
.PKT_BURSTWRAP_L (339),
.PKT_BYTE_CNT_H (338),
.PKT_BYTE_CNT_L (326),
.PKT_ADDR_H (319),
.PKT_ADDR_L (288),
.PKT_TRANS_COMPRESSED_READ (320),
.PKT_TRANS_POSTED (321),
.PKT_TRANS_WRITE (322),
.PKT_TRANS_READ (323),
.PKT_DATA_H (255),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (287),
.PKT_BYTEEN_L (256),
.PKT_SRC_ID_H (349),
.PKT_SRC_ID_L (349),
.PKT_DEST_ID_H (350),
.PKT_DEST_ID_L (350),
.ST_DATA_W (364),
.ST_CHANNEL_W (1),
.AV_BURSTCOUNT_W (10),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_kernel_expanded_master_agent (
.clk (pll_outclk0_clk), // clk.clk
.reset (address_span_extender_kernel_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_address), // av.address
.av_write (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_write), // .write
.av_read (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (address_span_extender_kernel_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (address_span_extender_kernel_expanded_master_agent_cp_valid), // cp.valid
.cp_data (address_span_extender_kernel_expanded_master_agent_cp_data), // .data
.cp_startofpacket (address_span_extender_kernel_expanded_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_kernel_expanded_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (address_span_extender_kernel_expanded_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (363),
.PKT_ORI_BURST_SIZE_L (361),
.PKT_RESPONSE_STATUS_H (360),
.PKT_RESPONSE_STATUS_L (359),
.PKT_BURST_SIZE_H (342),
.PKT_BURST_SIZE_L (340),
.PKT_TRANS_LOCK (324),
.PKT_BEGIN_BURST (347),
.PKT_PROTECTION_H (354),
.PKT_PROTECTION_L (352),
.PKT_BURSTWRAP_H (339),
.PKT_BURSTWRAP_L (339),
.PKT_BYTE_CNT_H (338),
.PKT_BYTE_CNT_L (326),
.PKT_ADDR_H (319),
.PKT_ADDR_L (288),
.PKT_TRANS_COMPRESSED_READ (320),
.PKT_TRANS_POSTED (321),
.PKT_TRANS_WRITE (322),
.PKT_TRANS_READ (323),
.PKT_DATA_H (255),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (287),
.PKT_BYTEEN_L (256),
.PKT_SRC_ID_H (349),
.PKT_SRC_ID_L (349),
.PKT_DEST_ID_H (350),
.PKT_DEST_ID_L (350),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (1),
.ST_DATA_W (364),
.AVS_BURSTCOUNT_W (13),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) hps_f2h_sdram0_data_agent (
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hps_f2h_sdram0_data_agent_m0_address), // m0.address
.m0_burstcount (hps_f2h_sdram0_data_agent_m0_burstcount), // .burstcount
.m0_byteenable (hps_f2h_sdram0_data_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hps_f2h_sdram0_data_agent_m0_debugaccess), // .debugaccess
.m0_lock (hps_f2h_sdram0_data_agent_m0_lock), // .lock
.m0_readdata (hps_f2h_sdram0_data_agent_m0_readdata), // .readdata
.m0_readdatavalid (hps_f2h_sdram0_data_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hps_f2h_sdram0_data_agent_m0_read), // .read
.m0_waitrequest (hps_f2h_sdram0_data_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hps_f2h_sdram0_data_agent_m0_writedata), // .writedata
.m0_write (hps_f2h_sdram0_data_agent_m0_write), // .write
.rp_endofpacket (hps_f2h_sdram0_data_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hps_f2h_sdram0_data_agent_rp_ready), // .ready
.rp_valid (hps_f2h_sdram0_data_agent_rp_valid), // .valid
.rp_data (hps_f2h_sdram0_data_agent_rp_data), // .data
.rp_startofpacket (hps_f2h_sdram0_data_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (hps_f2h_sdram0_data_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hps_f2h_sdram0_data_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hps_f2h_sdram0_data_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hps_f2h_sdram0_data_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hps_f2h_sdram0_data_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hps_f2h_sdram0_data_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hps_f2h_sdram0_data_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hps_f2h_sdram0_data_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hps_f2h_sdram0_data_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hps_f2h_sdram0_data_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (hps_f2h_sdram0_data_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hps_f2h_sdram0_data_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hps_f2h_sdram0_data_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (365),
.FIFO_DEPTH (15),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hps_f2h_sdram0_data_agent_rsp_fifo (
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hps_f2h_sdram0_data_agent_rf_source_data), // in.data
.in_valid (hps_f2h_sdram0_data_agent_rf_source_valid), // .valid
.in_ready (hps_f2h_sdram0_data_agent_rf_source_ready), // .ready
.in_startofpacket (hps_f2h_sdram0_data_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hps_f2h_sdram0_data_agent_rf_source_endofpacket), // .endofpacket
.out_data (hps_f2h_sdram0_data_agent_rsp_fifo_out_data), // out.data
.out_valid (hps_f2h_sdram0_data_agent_rsp_fifo_out_valid), // .valid
.out_ready (hps_f2h_sdram0_data_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hps_f2h_sdram0_data_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hps_f2h_sdram0_data_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_mm_interconnect_2_router router (
.sink_ready (address_span_extender_kernel_expanded_master_agent_cp_ready), // sink.ready
.sink_valid (address_span_extender_kernel_expanded_master_agent_cp_valid), // .valid
.sink_data (address_span_extender_kernel_expanded_master_agent_cp_data), // .data
.sink_startofpacket (address_span_extender_kernel_expanded_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_kernel_expanded_master_agent_cp_endofpacket), // .endofpacket
.clk (pll_outclk0_clk), // clk.clk
.reset (address_span_extender_kernel_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_2_router_001 router_001 (
.sink_ready (hps_f2h_sdram0_data_agent_rp_ready), // sink.ready
.sink_valid (hps_f2h_sdram0_data_agent_rp_valid), // .valid
.sink_data (hps_f2h_sdram0_data_agent_rp_data), // .data
.sink_startofpacket (hps_f2h_sdram0_data_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hps_f2h_sdram0_data_agent_rp_endofpacket), // .endofpacket
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_2_cmd_demux cmd_demux (
.clk (pll_outclk0_clk), // clk.clk
.reset (address_span_extender_kernel_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_2_cmd_mux cmd_mux (
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_2_cmd_demux rsp_demux (
.clk (pll_outclk0_clk), // clk.clk
.reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_2_rsp_mux rsp_mux (
.clk (pll_outclk0_clk), // clk.clk
.reset (address_span_extender_kernel_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_2_avalon_st_adapter #(
.inBitsPerSymbol (258),
.inUsePackets (0),
.inDataWidth (258),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (258),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (pll_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (hps_f2h_sdram0_data_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (hps_f2h_sdram0_data_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (hps_f2h_sdram0_data_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Odintsov Oleg
//
// Create Date: 11:15:41 02/24/2012
// Design Name:
// Module Name: ag_ram
// Project Name: Agat Hardware Project
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Enable the following define to use synchronous memory instead of
// asynchronous (which has been used in real Agats).
// The use of the synchronous memory will improve hardware design on FPGA
`define AG_RAM_SYNCHRONOUS
`ifdef AG_RAM_SYNCHRONOUS
module RAM16Kx1(input CLK1, input[13:0] AB1, input CS1, input READ,
output DO1, input DI1,
input CLK2, input[13:0] AB2, input CS2, output DO2);
parameter
D_00 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_01 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_02 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_03 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_04 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_05 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_06 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_07 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_08 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_09 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_0A = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_0B = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_0C = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_0D = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_0E = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_0F = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
// Address 4096 to 8191
D_10 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_11 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_12 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_13 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_14 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_15 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_16 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_17 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_18 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_19 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_1A = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_1B = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_1C = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_1D = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_1E = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_1F = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
// Address 8192 to 12287
D_20 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_21 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_22 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_23 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_24 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_25 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_26 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_27 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_28 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_29 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_2A = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_2B = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_2C = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_2D = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_2E = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_2F = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
// Address 12288 to 16383
D_30 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_31 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_32 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_33 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_34 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_35 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_36 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_37 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_38 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_39 = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_3A = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_3B = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_3C = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_3D = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_3E = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC,
D_3F = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC;
wire DO1x, DO2x;
assign DO1 = CS1? DO1x: 1'bZ;
assign DO2 = CS2? DO2x: 1'bZ;
// RAMB16_S1_S1: 16k x 1 Dual-Port RAM
// Spartan-3E
// Xilinx HDL Language Template, version 13.3
RAMB16_S1_S1 #(
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
.INIT_B(1'b0), // Value of output RAM registers on Port B at startup
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
.SRVAL_B(1'b0), // Port B output value upon SSR assertion
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
// The following INIT_xx declarations specify the initial contents of the RAM
// Address 0 to 4095
.INIT_00(D_00), .INIT_01(D_01), .INIT_02(D_02), .INIT_03(D_03),
.INIT_04(D_04), .INIT_05(D_05), .INIT_06(D_06), .INIT_07(D_07),
.INIT_08(D_08), .INIT_09(D_09), .INIT_0A(D_0A), .INIT_0B(D_0B),
.INIT_0C(D_0C), .INIT_0D(D_0D), .INIT_0E(D_0E), .INIT_0F(D_0F),
// Address 4096 to 8191
.INIT_10(D_10), .INIT_11(D_11), .INIT_12(D_12), .INIT_13(D_13),
.INIT_14(D_14), .INIT_15(D_15), .INIT_16(D_16), .INIT_17(D_17),
.INIT_18(D_18), .INIT_19(D_19), .INIT_1A(D_1A), .INIT_1B(D_1B),
.INIT_1C(D_1C), .INIT_1D(D_1D), .INIT_1E(D_1E), .INIT_1F(D_1F),
// Address 8192 to 12287
.INIT_20(D_20), .INIT_21(D_21), .INIT_22(D_22), .INIT_23(D_23),
.INIT_24(D_24), .INIT_25(D_25), .INIT_26(D_26), .INIT_27(D_27),
.INIT_28(D_28), .INIT_29(D_29), .INIT_2A(D_2A), .INIT_2B(D_2B),
.INIT_2C(D_2C), .INIT_2D(D_2D), .INIT_2E(D_2E), .INIT_2F(D_2F),
// Address 12288 to 16383
.INIT_30(D_30), .INIT_31(D_31), .INIT_32(D_32), .INIT_33(D_33),
.INIT_34(D_34), .INIT_35(D_35), .INIT_36(D_36), .INIT_37(D_37),
.INIT_38(D_38), .INIT_39(D_39), .INIT_3A(D_3A), .INIT_3B(D_3B),
.INIT_3C(D_3C), .INIT_3D(D_3D), .INIT_3E(D_3E), .INIT_3F(D_3F)
) RAMB16_S1_S1_inst (
.DOA(DO1x), // Port A 1-bit Data Output
.DOB(DO2x), // Port B 1-bit Data Output
.ADDRA(AB1), // Port A 14-bit Address Input
.ADDRB(AB2), // Port B 14-bit Address Input
.CLKA(CLK1), // Port A Clock
.CLKB(CLK2), // Port B Clock
.DIA(DI1), // Port A 1-bit Data Input
.DIB(1'bZ), // Port B 1-bit Data Input
.ENA(CS1), // Port A RAM Enable Input
.ENB(CS2), // Port B RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEA(~READ), // Port A Write Enable Input
.WEB(1'b0) // Port B Write Enable Input
);
endmodule
`else
module RAM1Kx1(input CLK1, input[9:0] AB1, input CS1, input READ,
output DO1, input DI1,
input CLK2, input[9:0] AB2, input CS2, output DO2);
parameter FILL = 256'h33333333333333333333333333333333CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC;
reg mem[0:'h3FF];
integer i;
initial
for (i = 0; i < 'h400; i = i + 1)
mem[i] = (FILL&(256'b01<<(i&'hFF)))?1'b1:1'b0;
assign DO1 = (CS1 && READ)? mem[AB1]: 1'bZ;
assign DO2 = CS2? mem[AB2]: 1'bZ;
always @(posedge CLK1) if (CS1 && !READ) mem[AB1] <= DI1;
endmodule
module RAM16Kx1(input CLK1, input[13:0] AB1, input CS1, input READ,
output DO1, input DI1,
input CLK2, input[13:0] AB2, input CS2, output DO2);
wire[3:0] SEL1 = AB1[13:10];
wire[3:0] SEL2 = AB2[13:10];
RAM1Kx1 ram0(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h0), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h0), DO2);
RAM1Kx1 ram1(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h1), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h1), DO2);
RAM1Kx1 ram2(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h2), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h2), DO2);
RAM1Kx1 ram3(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h3), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h3), DO2);
RAM1Kx1 ram4(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h4), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h4), DO2);
RAM1Kx1 ram5(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h5), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h5), DO2);
RAM1Kx1 ram6(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h6), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h6), DO2);
RAM1Kx1 ram7(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h7), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h7), DO2);
RAM1Kx1 ram8(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h8), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h8), DO2);
RAM1Kx1 ram9(CLK1, AB1[9:0], CS1 && (SEL1 == 4'h9), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'h9), DO2);
RAM1Kx1 ramA(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hA), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hA), DO2);
RAM1Kx1 ramB(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hB), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hB), DO2);
RAM1Kx1 ramC(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hC), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hC), DO2);
RAM1Kx1 ramD(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hD), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hD), DO2);
RAM1Kx1 ramE(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hE), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hE), DO2);
RAM1Kx1 ramF(CLK1, AB1[9:0], CS1 && (SEL1 == 4'hF), READ, DO1, DI1,
CLK2, AB2[9:0], CS2 && (SEL2 == 4'hF), DO2);
endmodule
`endif // synchronous
/*
Data bus for video controller:
A0=0, DO2: A0=1, DO2:
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Data bus for processor:
A0=0, DO1/DI1: A0=1, DO1/DI1:
07 06 05 04 03 02 01 00 07 06 05 04 03 02 01 00
*/
module RAM32Kx8x16(input CLK1, input[14:0] AB1, input CS1,
input READ, output[7:0] DO1, input[7:0] DI1,
input CLK2, input[13:0] AB2, input CS2, output[15:0] DO2);
wire[1:0] CSM = {(~AB1[0]) & CS1, AB1[0] & CS1}; // CS for modules
wire[13:0] AB1x = AB1[14:1];
`include "fighter.v"
/* RAM16Kx1 ram0(CLK1, AB1x, CSM[0], READ, DO1[0], DI1[0], CLK2, AB2, CS2, DO2[0]);
RAM16Kx1 ram1(CLK1, AB1x, CSM[0], READ, DO1[1], DI1[1], CLK2, AB2, CS2, DO2[1]);
RAM16Kx1 ram2(CLK1, AB1x, CSM[0], READ, DO1[2], DI1[2], CLK2, AB2, CS2, DO2[2]);
RAM16Kx1 ram3(CLK1, AB1x, CSM[0], READ, DO1[3], DI1[3], CLK2, AB2, CS2, DO2[3]);
RAM16Kx1 ram4(CLK1, AB1x, CSM[0], READ, DO1[4], DI1[4], CLK2, AB2, CS2, DO2[4]);
RAM16Kx1 ram5(CLK1, AB1x, CSM[0], READ, DO1[5], DI1[5], CLK2, AB2, CS2, DO2[5]);
RAM16Kx1 ram6(CLK1, AB1x, CSM[0], READ, DO1[6], DI1[6], CLK2, AB2, CS2, DO2[6]);
RAM16Kx1 ram7(CLK1, AB1x, CSM[0], READ, DO1[7], DI1[7], CLK2, AB2, CS2, DO2[7]);
RAM16Kx1 ram8(CLK1, AB1x, CSM[1], READ, DO1[0], DI1[0], CLK2, AB2, CS2, DO2[8]);
RAM16Kx1 ram9(CLK1, AB1x, CSM[1], READ, DO1[1], DI1[1], CLK2, AB2, CS2, DO2[9]);
RAM16Kx1 ramA(CLK1, AB1x, CSM[1], READ, DO1[2], DI1[2], CLK2, AB2, CS2, DO2[10]);
RAM16Kx1 ramB(CLK1, AB1x, CSM[1], READ, DO1[3], DI1[3], CLK2, AB2, CS2, DO2[11]);
RAM16Kx1 ramC(CLK1, AB1x, CSM[1], READ, DO1[4], DI1[4], CLK2, AB2, CS2, DO2[12]);
RAM16Kx1 ramD(CLK1, AB1x, CSM[1], READ, DO1[5], DI1[5], CLK2, AB2, CS2, DO2[13]);
RAM16Kx1 ramE(CLK1, AB1x, CSM[1], READ, DO1[6], DI1[6], CLK2, AB2, CS2, DO2[14]);
RAM16Kx1 ramF(CLK1, AB1x, CSM[1], READ, DO1[7], DI1[7], CLK2, AB2, CS2, DO2[15]);*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22A_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O22A_PP_BLACKBOX_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22A_PP_BLACKBOX_V
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module VOICE_ROM_INIT (
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [5 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [15 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [5 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [15 : 0] doutb;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(1),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("VOICE_ROM_INIT.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_READ_WIDTH_A(16),
.C_WRITE_DEPTH_A(64),
.C_READ_DEPTH_A(64),
.C_ADDRA_WIDTH(6),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(16),
.C_READ_WIDTH_B(16),
.C_WRITE_DEPTH_B(64),
.C_READ_DEPTH_B(64),
.C_ADDRB_WIDTH(6),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("0"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 3.01735 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(),
.clkb(clkb),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(addrb),
.dinb(16'B0),
.doutb(doutb),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(16'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Sun Sep 22 03:32:35 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd/gcd.srcs/sources_1/bd/gcd_block_design/ip/gcd_block_design_rst_ps7_0_100M_0/gcd_block_design_rst_ps7_0_100M_0_stub.v
// Design : gcd_block_design_rst_ps7_0_100M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2018.2" *)
module gcd_block_design_rst_ps7_0_100M_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Tue Sep 17 15:49:29 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_gcd_0_0_stub.v
// Design : gcd_block_design_gcd_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "gcd,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_gcd_bus_AWADDR,
s_axi_gcd_bus_AWVALID, s_axi_gcd_bus_AWREADY, s_axi_gcd_bus_WDATA, s_axi_gcd_bus_WSTRB,
s_axi_gcd_bus_WVALID, s_axi_gcd_bus_WREADY, s_axi_gcd_bus_BRESP, s_axi_gcd_bus_BVALID,
s_axi_gcd_bus_BREADY, s_axi_gcd_bus_ARADDR, s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_ARREADY, s_axi_gcd_bus_RDATA, s_axi_gcd_bus_RRESP, s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_RREADY, ap_clk, ap_rst_n, interrupt)
/* synthesis syn_black_box black_box_pad_pin="s_axi_gcd_bus_AWADDR[5:0],s_axi_gcd_bus_AWVALID,s_axi_gcd_bus_AWREADY,s_axi_gcd_bus_WDATA[31:0],s_axi_gcd_bus_WSTRB[3:0],s_axi_gcd_bus_WVALID,s_axi_gcd_bus_WREADY,s_axi_gcd_bus_BRESP[1:0],s_axi_gcd_bus_BVALID,s_axi_gcd_bus_BREADY,s_axi_gcd_bus_ARADDR[5:0],s_axi_gcd_bus_ARVALID,s_axi_gcd_bus_ARREADY,s_axi_gcd_bus_RDATA[31:0],s_axi_gcd_bus_RRESP[1:0],s_axi_gcd_bus_RVALID,s_axi_gcd_bus_RREADY,ap_clk,ap_rst_n,interrupt" */;
input [5:0]s_axi_gcd_bus_AWADDR;
input s_axi_gcd_bus_AWVALID;
output s_axi_gcd_bus_AWREADY;
input [31:0]s_axi_gcd_bus_WDATA;
input [3:0]s_axi_gcd_bus_WSTRB;
input s_axi_gcd_bus_WVALID;
output s_axi_gcd_bus_WREADY;
output [1:0]s_axi_gcd_bus_BRESP;
output s_axi_gcd_bus_BVALID;
input s_axi_gcd_bus_BREADY;
input [5:0]s_axi_gcd_bus_ARADDR;
input s_axi_gcd_bus_ARVALID;
output s_axi_gcd_bus_ARREADY;
output [31:0]s_axi_gcd_bus_RDATA;
output [1:0]s_axi_gcd_bus_RRESP;
output s_axi_gcd_bus_RVALID;
input s_axi_gcd_bus_RREADY;
input ap_clk;
input ap_rst_n;
output interrupt;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Gigabit Transceiver Buffer
// /___/ /\ Filename : IBUFDS_GTE4.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/27/2015 - Initial version from E3
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_GTE4 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00,
parameter [1:0] REFCLK_ICNTL_RX = 2'b00
)(
output O,
output ODIV2,
input CEB,
input I,
input IB
);
// define constants
localparam MODULE_NAME = "IBUFDS_GTE4";
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "IBUFDS_GTE4_dr.v"
`else
reg [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH;
reg [1:0] REFCLK_HROW_CK_SEL_REG = REFCLK_HROW_CK_SEL;
reg [1:0] REFCLK_ICNTL_RX_REG = REFCLK_ICNTL_RX;
`endif
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
// wire CEB_in;
// wire IB_in;
// wire I_in;
// assign CEB_in = (CEB !== 1'bz) && CEB; // rv 0
// assign IB_in = IB;
// assign I_in = I;
reg ODIV2_out = 1'b0;
assign ODIV2 = ODIV2_out;
reg [2:0] ce_count = 3'b001;
reg [2:0] edge_count = 3'b000;
reg allEqual = 1'b0;
// =====================
// Count the rising edges of the clk
// =====================
always @(posedge I) begin
if (allEqual)
edge_count <= 3'b000;
else
if ((CEB === 1'b0) || (CEB === 1'bz)) // rv = 0
edge_count <= edge_count + 1;
end
// Generate synchronous reset after DIVIDE number of counts
always @(edge_count)
if (edge_count == ce_count)
allEqual = 1;
else
allEqual = 0;
// =====================
// Generate ODIV2
// =====================
always @(*) begin
case (REFCLK_HROW_CK_SEL_REG)
2'b00: ODIV2_out <= ~(REFCLK_EN_TX_PATH_REG | (CEB === 1'b1)) && I;
2'b01: ODIV2_out <= allEqual;
2'b10: ODIV2_out <= 1'b0;
2'b11: ODIV2_out <= 1'b0;
default : ODIV2_out <= ~(REFCLK_EN_TX_PATH_REG | (CEB === 1'b1)) && I;
endcase
end
// =====================
// Generate O
// =====================
assign O = ~(REFCLK_EN_TX_PATH_REG | (CEB === 1'b1)) && I;
`ifndef XIL_XECLIB
//`ifdef XIL_TIMING
// "I" is actually a CLK so need I -> O/ODIV2 delays in functional as well.
// IB to O/ODIV2 delay added because this was creating confusion in some tools
// even though IB input behavior is not modeled.
specify
(I => O) = (100:100:100, 100:100:100);
(I => ODIV2) = (100:100:100, 100:100:100);
(IB => O) = (100:100:100, 100:100:100);
(IB => ODIV2) = (100:100:100, 100:100:100);
specparam PATHPULSE$ = 0;
endspecify
//`endif
`endif
endmodule
`endcelldefine
|
//////////////////////////////////////////////////////////////////////
//// ////
//// can_crc.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2003/07/16 13:16:51 mohor
// Fixed according to the linter.
//
// Revision 1.3 2003/02/10 16:02:11 mohor
// CAN is working according to the specification. WB interface and more
// registers (status, IRQ, ...) needs to be added.
//
// Revision 1.2 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.1 2003/01/08 02:10:54 mohor
// Acceptance filter added.
//
//
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module can_crc (clk, data, enable, initialize, crc);
parameter Tp = 1;
input clk;
input data;
input enable;
input initialize;
output [14:0] crc;
reg [14:0] crc;
wire crc_next;
wire [14:0] crc_tmp;
assign crc_next = data ^ crc[14];
assign crc_tmp = {crc[13:0], 1'b0};
always @ (posedge clk)
begin
if(initialize)
crc <= #Tp 15'h0;
else if (enable)
begin
if (crc_next)
crc <= #Tp crc_tmp ^ 15'h4599;
else
crc <= #Tp crc_tmp;
end
end
endmodule
|
(* Copyright (c) 2011-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import FunctionalExtensionality List.
Require Import CpdtTactics DepList.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(** %\chapter{A Taste of Reasoning About Programming Language Syntax}% *)
(** Reasoning about the syntax and semantics of programming languages is a popular application of proof assistants. Before proving the first theorem of this kind, it is necessary to choose a formal encoding of the informal notions of syntax, dealing with such issues as %\index{variable binding}%variable binding conventions. I believe the pragmatic questions in this domain are far from settled and remain as important open research problems. However, in this chapter, I will demonstrate two underused encoding approaches. Note that I am not recommending either approach as a silver bullet! Mileage will vary across concrete problems, and I expect there to be significant future advances in our knowledge of encoding techniques. For a broader introduction to programming language formalization, using more elementary techniques, see %\emph{%{{http://www.cis.upenn.edu/~bcpierce/sf/}Software Foundations}%}% by Pierce et al.
This chapter is also meant as a case study, bringing together what we have learned in the previous chapters. We will see a concrete example of the importance of representation choices; translating mathematics from paper to Coq is not a deterministic process, and different creative choices can have big impacts. We will also see dependent types and scripted proof automation in action, applied to solve a particular problem as well as possible, rather than to demonstrate new Coq concepts.
I apologize in advance to those readers not familiar with the theory of programming language semantics. I will make a few remarks intended to relate the material here with common ideas in semantics, but these remarks should be safe for others to skip.
We will define a small programming language and reason about its semantics, expressed as an interpreter into Coq terms, much as we have done in examples throughout the book. It will be helpful to build a slight extension of [crush] that tries to apply %\index{functional extensionality}%functional extensionality, an axiom we met in Chapter 12, which says that two functions are equal if they map equal inputs to equal outputs. We also use [f_equal] to simplify goals of a particular form that will come up with the term denotation function that we define shortly. *)
Ltac ext := let x := fresh "x" in extensionality x.
Ltac pl := crush; repeat (match goal with
| [ |- (fun x => _) = (fun y => _) ] => ext
| [ |- _ _ _ ?E _ = _ _ _ ?E _ ] => f_equal
| [ |- ?E ::: _ = ?E ::: _ ] => f_equal
| [ |- hmap _ ?E = hmap _ ?E ] => f_equal
end; crush).
(** At this point in the book source, some auxiliary proofs also appear. *)
(* begin hide *)
Section hmap.
Variable A : Type.
Variables B1 B2 B3 : A -> Type.
Variable f1 : forall x, B1 x -> B2 x.
Variable f2 : forall x, B2 x -> B3 x.
Theorem hmap_hmap : forall ls (hl : hlist B1 ls), hmap f2 (hmap f1 hl) = hmap (fun i (x : B1 i) => f2 (f1 x)) hl.
induction hl; crush.
Qed.
End hmap.
Section Forall.
Variable A : Type.
Variable P : A -> Prop.
Theorem Forall_In : forall ls, Forall P ls -> forall x, In x ls -> P x.
induction 1; crush.
Qed.
Theorem Forall_In' : forall ls, (forall x, In x ls -> P x) -> Forall P ls.
induction ls; crush.
Qed.
Variable P' : A -> Prop.
Theorem Forall_weaken : forall ls, Forall P ls
-> (forall x, P x -> P' x)
-> Forall P' ls.
induction 1; crush.
Qed.
End Forall.
(* end hide *)
(** Here is a definition of the type system we will use throughout the chapter. It is for simply typed lambda calculus with natural numbers as the base type. *)
Inductive type : Type :=
| Nat : type
| Func : type -> type -> type.
Fixpoint typeDenote (t : type) : Type :=
match t with
| Nat => nat
| Func t1 t2 => typeDenote t1 -> typeDenote t2
end.
(** Now we have some choices as to how we represent the syntax of programs. The two sections of the chapter explore two such choices, demonstrating the effect the choice has on proof complexity. *)
(** * Dependent de Bruijn Indices *)
(** The first encoding is one we met first in Chapter 9, the _dependent de Bruijn index_ encoding. We represent program syntax terms in a type family parameterized by a list of types, representing the _typing context_, or information on which free variables are in scope and what their types are. Variables are represented in a way isomorphic to the natural numbers, where number 0 represents the first element in the context, number 1 the second element, and so on. Actually, instead of numbers, we use the [member] dependent type family from Chapter 9. *)
Module FirstOrder.
(** Here is the definition of the [term] type, including variables, constants, addition, function abstraction and application, and let binding of local variables. *)
Inductive term : list type -> type -> Type :=
| Var : forall G t, member t G -> term G t
| Const : forall G, nat -> term G Nat
| Plus : forall G, term G Nat -> term G Nat -> term G Nat
| Abs : forall G dom ran, term (dom :: G) ran -> term G (Func dom ran)
| App : forall G dom ran, term G (Func dom ran) -> term G dom -> term G ran
| Let : forall G t1 t2, term G t1 -> term (t1 :: G) t2 -> term G t2.
Implicit Arguments Const [G].
(** Here are two example term encodings, the first of addition packaged as a two-argument curried function, and the second of a sample application of addition to constants. *)
Example add : term nil (Func Nat (Func Nat Nat)) :=
Abs (Abs (Plus (Var (HNext HFirst)) (Var HFirst))).
Example three_the_hard_way : term nil Nat :=
App (App add (Const 1)) (Const 2).
(** Since dependent typing ensures that any term is well-formed in its context and has a particular type, it is easy to translate syntactic terms into Coq values. *)
Fixpoint termDenote G t (e : term G t) : hlist typeDenote G -> typeDenote t :=
match e with
| Var _ _ x => fun s => hget s x
| Const _ n => fun _ => n
| Plus _ e1 e2 => fun s => termDenote e1 s + termDenote e2 s
| Abs _ _ _ e1 => fun s => fun x => termDenote e1 (x ::: s)
| App _ _ _ e1 e2 => fun s => (termDenote e1 s) (termDenote e2 s)
| Let _ _ _ e1 e2 => fun s => termDenote e2 (termDenote e1 s ::: s)
end.
(** With this term representation, some program transformations are easy to implement and prove correct. Certainly we would be worried if this were not the the case for the _identity_ transformation, which takes a term apart and reassembles it. *)
Fixpoint ident G t (e : term G t) : term G t :=
match e with
| Var _ _ x => Var x
| Const _ n => Const n
| Plus _ e1 e2 => Plus (ident e1) (ident e2)
| Abs _ _ _ e1 => Abs (ident e1)
| App _ _ _ e1 e2 => App (ident e1) (ident e2)
| Let _ _ _ e1 e2 => Let (ident e1) (ident e2)
end.
Theorem identSound : forall G t (e : term G t) s,
termDenote (ident e) s = termDenote e s.
induction e; pl.
Qed.
(** A slightly more ambitious transformation belongs to the family of _constant folding_ optimizations we have used as examples in other chapters. *)
Fixpoint cfold G t (e : term G t) : term G t :=
match e with
| Plus G e1 e2 =>
let e1' := cfold e1 in
let e2' := cfold e2 in
let maybeOpt := match e1' return _ with
| Const _ n1 =>
match e2' return _ with
| Const _ n2 => Some (Const (n1 + n2))
| _ => None
end
| _ => None
end in
match maybeOpt with
| None => Plus e1' e2'
| Some e' => e'
end
| Abs _ _ _ e1 => Abs (cfold e1)
| App _ _ _ e1 e2 => App (cfold e1) (cfold e2)
| Let _ _ _ e1 e2 => Let (cfold e1) (cfold e2)
| e => e
end.
(** The correctness proof is more complex, but only slightly so. *)
Theorem cfoldSound : forall G t (e : term G t) s,
termDenote (cfold e) s = termDenote e s.
induction e; pl;
repeat (match goal with
| [ |- context[match ?E with Var _ _ _ => _ | _ => _ end] ] =>
dep_destruct E
end; pl).
Qed.
(** The transformations we have tried so far have been straightforward because they do not have interesting effects on the variable binding structure of terms. The dependent de Bruijn representation is called%\index{first-order syntax}% _first-order_ because it encodes variable identity explicitly; all such representations incur bookkeeping overheads in transformations that rearrange binding structure.
As an example of a tricky transformation, consider one that removes all uses of "[let x = e1 in e2]" by substituting [e1] for [x] in [e2]. We will implement the translation by pairing the "compile-time" typing environment with a "run-time" value environment or _substitution_, mapping each variable to a value to be substituted for it. Such a substitute term may be placed within a program in a position with a larger typing environment than applied at the point where the substitute term was chosen. To support such context transplantation, we need _lifting_, a standard de Bruijn indices operation. With dependent typing, lifting corresponds to weakening for typing judgments.
The fundamental goal of lifting is to add a new variable to a typing context, maintaining the validity of a term in the expanded context. To express the operation of adding a type to a context, we use a helper function [insertAt]. *)
Fixpoint insertAt (t : type) (G : list type) (n : nat) {struct n} : list type :=
match n with
| O => t :: G
| S n' => match G with
| nil => t :: G
| t' :: G' => t' :: insertAt t G' n'
end
end.
(** Another function lifts bound variable instances, which we represent with [member] values. *)
Fixpoint liftVar t G (x : member t G) t' n : member t (insertAt t' G n) :=
match x with
| HFirst G' => match n return member t (insertAt t' (t :: G') n) with
| O => HNext HFirst
| _ => HFirst
end
| HNext t'' G' x' => match n return member t (insertAt t' (t'' :: G') n) with
| O => HNext (HNext x')
| S n' => HNext (liftVar x' t' n')
end
end.
(** The final helper function for lifting allows us to insert a new variable anywhere in a typing context. *)
Fixpoint lift' G t' n t (e : term G t) : term (insertAt t' G n) t :=
match e with
| Var _ _ x => Var (liftVar x t' n)
| Const _ n => Const n
| Plus _ e1 e2 => Plus (lift' t' n e1) (lift' t' n e2)
| Abs _ _ _ e1 => Abs (lift' t' (S n) e1)
| App _ _ _ e1 e2 => App (lift' t' n e1) (lift' t' n e2)
| Let _ _ _ e1 e2 => Let (lift' t' n e1) (lift' t' (S n) e2)
end.
(** In the [Let] removal transformation, we only need to apply lifting to add a new variable at the _beginning_ of a typing context, so we package lifting into this final, simplified form. *)
Definition lift G t' t (e : term G t) : term (t' :: G) t :=
lift' t' O e.
(** Finally, we can implement [Let] removal. The argument of type [hlist (term G') G] represents a substitution mapping each variable from context [G] into a term that is valid in context [G']. Note how the [Abs] case (1) extends via lifting the substitution [s] to hold in the broader context of the abstraction body [e1] and (2) maps the new first variable to itself. It is only the [Let] case that maps a variable to any substitute beside itself. *)
Fixpoint unlet G t (e : term G t) G' : hlist (term G') G -> term G' t :=
match e with
| Var _ _ x => fun s => hget s x
| Const _ n => fun _ => Const n
| Plus _ e1 e2 => fun s => Plus (unlet e1 s) (unlet e2 s)
| Abs _ _ _ e1 => fun s => Abs (unlet e1 (Var HFirst ::: hmap (lift _) s))
| App _ _ _ e1 e2 => fun s => App (unlet e1 s) (unlet e2 s)
| Let _ t1 _ e1 e2 => fun s => unlet e2 (unlet e1 s ::: s)
end.
(** We have finished defining the transformation, but the parade of helper functions is not over. To prove correctness, we will use one more helper function and a few lemmas. First, we need an operation to insert a new value into a substitution at a particular position. *)
Fixpoint insertAtS (t : type) (x : typeDenote t) (G : list type) (n : nat) {struct n}
: hlist typeDenote G -> hlist typeDenote (insertAt t G n) :=
match n with
| O => fun s => x ::: s
| S n' => match G return hlist typeDenote G
-> hlist typeDenote (insertAt t G (S n')) with
| nil => fun s => x ::: s
| t' :: G' => fun s => hhd s ::: insertAtS t x n' (htl s)
end
end.
Implicit Arguments insertAtS [t G].
(** Next we prove that [liftVar] is correct. That is, a lifted variable retains its value with respect to a substitution when we perform an analogue to lifting by inserting a new mapping into the substitution. *)
Lemma liftVarSound : forall t' (x : typeDenote t') t G (m : member t G) s n,
hget s m = hget (insertAtS x n s) (liftVar m t' n).
induction m; destruct n; dep_destruct s; pl.
Qed.
Hint Resolve liftVarSound.
(** An analogous lemma establishes correctness of [lift']. *)
Lemma lift'Sound : forall G t' (x : typeDenote t') t (e : term G t) n s,
termDenote e s = termDenote (lift' t' n e) (insertAtS x n s).
induction e; pl;
repeat match goal with
| [ IH : forall n s, _ = termDenote (lift' _ n ?E) _
|- context[lift' _ (S ?N) ?E] ] => specialize (IH (S N))
end; pl.
Qed.
(** Correctness of [lift] itself is an easy corollary. *)
Lemma liftSound : forall G t' (x : typeDenote t') t (e : term G t) s,
termDenote (lift t' e) (x ::: s) = termDenote e s.
unfold lift; intros; rewrite (lift'Sound _ x e O); trivial.
Qed.
Hint Rewrite hget_hmap hmap_hmap liftSound.
(** Finally, we can prove correctness of [unletSound] for terms in arbitrary typing environments. *)
Lemma unletSound' : forall G t (e : term G t) G' (s : hlist (term G') G) s1,
termDenote (unlet e s) s1
= termDenote e (hmap (fun t' (e' : term G' t') => termDenote e' s1) s).
induction e; pl.
Qed.
(** The lemma statement is a mouthful, with all its details of typing contexts and substitutions. It is usually prudent to state a final theorem in as simple a way as possible, to help your readers believe that you have proved what they expect. We follow that advice here for the simple case of terms with empty typing contexts. *)
Theorem unletSound : forall t (e : term nil t),
termDenote (unlet e HNil) HNil = termDenote e HNil.
intros; apply unletSound'.
Qed.
End FirstOrder.
(** The [Let] removal optimization is a good case study of a simple transformation that may turn out to be much more work than expected, based on representation choices. In the second part of this chapter, we consider an alternate choice that produces a more pleasant experience. *)
(** * Parametric Higher-Order Abstract Syntax *)
(** In contrast to first-order encodings,%\index{higher-order syntax}% _higher-order_ encodings avoid explicit modeling of variable identity. Instead, the binding constructs of an%\index{object language}% _object language_ (the language being formalized) can be represented using the binding constructs of the%\index{meta language}% _meta language_ (the language in which the formalization is done). The best known higher-order encoding is called%\index{higher-order abstract syntax}% _higher-order abstract syntax_ (HOAS) %\cite{HOAS}%, and we can start by attempting to apply it directly in Coq. *)
Module HigherOrder.
(** With HOAS, each object language binding construct is represented with a _function_ of the meta language. Here is what we get if we apply that idea within an inductive definition of term syntax. *)
(** %\vspace{-.15in}%[[
Inductive term : type -> Type :=
| Const : nat -> term Nat
| Plus : term Nat -> term Nat -> term Nat
| Abs : forall dom ran, (term dom -> term ran) -> term (Func dom ran)
| App : forall dom ran, term (Func dom ran) -> term dom -> term ran
| Let : forall t1 t2, term t1 -> (term t1 -> term t2) -> term t2.
]]
However, Coq rejects this definition for failing to meet the %\index{strict positivity requirement}%strict positivity restriction. For instance, the constructor [Abs] takes an argument that is a function over the same type family [term] that we are defining. Inductive definitions of this kind can be used to write non-terminating Gallina programs, which breaks the consistency of Coq's logic.
An alternate higher-order encoding is%\index{parametric higher-order abstract syntax}\index{PHOAS|see{parametric higher-order abstract syntax}}% _parametric HOAS_, as introduced by Washburn and Weirich%~\cite{BGB}% for Haskell and tweaked by me%~\cite{PhoasICFP08}% for use in Coq. Here the idea is to parameterize the syntax type by a type family standing for a _representation of variables_. *)
Section var.
Variable var : type -> Type.
Inductive term : type -> Type :=
| Var : forall t, var t -> term t
| Const : nat -> term Nat
| Plus : term Nat -> term Nat -> term Nat
| Abs : forall dom ran, (var dom -> term ran) -> term (Func dom ran)
| App : forall dom ran, term (Func dom ran) -> term dom -> term ran
| Let : forall t1 t2, term t1 -> (var t1 -> term t2) -> term t2.
End var.
Implicit Arguments Var [var t].
Implicit Arguments Const [var].
Implicit Arguments Abs [var dom ran].
(** Coq accepts this definition because our embedded functions now merely take _variables_ as arguments, instead of arbitrary terms. One might wonder whether there is an easy loophole to exploit here, instantiating the parameter [var] as [term] itself. However, to do that, we would need to choose a variable representation for this nested mention of [term], and so on through an infinite descent into [term] arguments.
We write the final type of a closed term using polymorphic quantification over all possible choices of [var] type family. *)
Definition Term t := forall var, term var t.
(** Here are the new representations of the example terms from the last section. Note how each is written as a function over a [var] choice, such that the specific choice has no impact on the _structure_ of the term. *)
Example add : Term (Func Nat (Func Nat Nat)) := fun var =>
Abs (fun x => Abs (fun y => Plus (Var x) (Var y))).
Example three_the_hard_way : Term Nat := fun var =>
App (App (add var) (Const 1)) (Const 2).
(** The argument [var] does not even appear in the function body for [add]. How can that be? By giving our terms expressive types, we allow Coq to infer many arguments for us. In fact, we do not even need to name the [var] argument! *)
Example add' : Term (Func Nat (Func Nat Nat)) := fun _ =>
Abs (fun x => Abs (fun y => Plus (Var x) (Var y))).
Example three_the_hard_way' : Term Nat := fun _ =>
App (App (add' _) (Const 1)) (Const 2).
(** Even though the [var] formal parameters appear as underscores, they _are_ mentioned in the function bodies that type inference calculates. *)
(** ** Functional Programming with PHOAS *)
(** It may not be at all obvious that the PHOAS representation admits the crucial computable operations. The key to effective deconstruction of PHOAS terms is one principle: treat the [var] parameter as an unconstrained choice of _which data should be annotated on each variable_. We will begin with a simple example, that of counting how many variable nodes appear in a PHOAS term. This operation requires no data annotated on variables, so we simply annotate variables with [unit] values. Note that, when we go under binders in the cases for [Abs] and [Let], we must provide the data value to annotate on the new variable we pass beneath. For our current choice of [unit] data, we always pass [tt]. *)
Fixpoint countVars t (e : term (fun _ => unit) t) : nat :=
match e with
| Var _ _ => 1
| Const _ => 0
| Plus e1 e2 => countVars e1 + countVars e2
| Abs _ _ e1 => countVars (e1 tt)
| App _ _ e1 e2 => countVars e1 + countVars e2
| Let _ _ e1 e2 => countVars e1 + countVars (e2 tt)
end.
(** The above definition may seem a bit peculiar. What gave us the right to represent variables as [unit] values? Recall that our final representation of closed terms is as polymorphic functions. We merely specialize a closed term to exactly the right variable representation for the transformation we wish to perform. *)
Definition CountVars t (E : Term t) := countVars (E (fun _ => unit)).
(** It is easy to test that [CountVars] operates properly. *)
Eval compute in CountVars three_the_hard_way.
(** %\vspace{-.15in}%[[
= 2
]]
*)
(** In fact, PHOAS can be used anywhere that first-order representations can. We will not go into all the details here, but the intuition is that it is possible to interconvert between PHOAS and any reasonable first-order representation. Here is a suggestive example, translating PHOAS terms into strings giving a first-order rendering. To implement this translation, the key insight is to tag variables with strings, giving their names. The function takes as an additional input a string giving the name to be assigned to the next variable introduced. We evolve this name by adding a prime to its end. To avoid getting bogged down in orthogonal details, we render all constants as the string ["N"]. *)
Require Import String.
Open Scope string_scope.
Fixpoint pretty t (e : term (fun _ => string) t) (x : string) : string :=
match e with
| Var _ s => s
| Const _ => "N"
| Plus e1 e2 => "(" ++ pretty e1 x ++ " + " ++ pretty e2 x ++ ")"
| Abs _ _ e1 => "(fun " ++ x ++ " => " ++ pretty (e1 x) (x ++ "'") ++ ")"
| App _ _ e1 e2 => "(" ++ pretty e1 x ++ " " ++ pretty e2 x ++ ")"
| Let _ _ e1 e2 => "(let " ++ x ++ " = " ++ pretty e1 x ++ " in "
++ pretty (e2 x) (x ++ "'") ++ ")"
end.
Definition Pretty t (E : Term t) := pretty (E (fun _ => string)) "x".
Eval compute in Pretty three_the_hard_way.
(** %\vspace{-.15in}%[[
= "(((fun x => (fun x' => (x + x'))) N) N)"
]]
*)
(** However, it is not necessary to convert to first-order form to support many common operations on terms. For instance, we can implement substitution of terms for variables. The key insight here is to _tag variables with terms_, so that, on encountering a variable, we can simply replace it by the term in its tag. We will call this function initially on a term with exactly one free variable, tagged with the appropriate substitute. During recursion, new variables are added, but they are only tagged with their own term equivalents. Note that this function [squash] is parameterized over a specific [var] choice. *)
Fixpoint squash var t (e : term (term var) t) : term var t :=
match e with
| Var _ e1 => e1
| Const n => Const n
| Plus e1 e2 => Plus (squash e1) (squash e2)
| Abs _ _ e1 => Abs (fun x => squash (e1 (Var x)))
| App _ _ e1 e2 => App (squash e1) (squash e2)
| Let _ _ e1 e2 => Let (squash e1) (fun x => squash (e2 (Var x)))
end.
(** To define the final substitution function over terms with single free variables, we define [Term1], an analogue to [Term] that we defined before for closed terms. *)
Definition Term1 (t1 t2 : type) := forall var, var t1 -> term var t2.
(** Substitution is defined by (1) instantiating a [Term1] to tag variables with terms and (2) applying the result to a specific term to be substituted. Note how the parameter [var] of [squash] is instantiated: the body of [Subst] is itself a polymorphic quantification over [var], standing for a variable tag choice in the output term; and we use that input to compute a tag choice for the input term. *)
Definition Subst (t1 t2 : type) (E : Term1 t1 t2) (E' : Term t1) : Term t2 :=
fun var => squash (E (term var) (E' var)).
Eval compute in Subst (fun _ x => Plus (Var x) (Const 3)) three_the_hard_way.
(** %\vspace{-.15in}%[[
= fun var : type -> Type =>
Plus
(App
(App
(Abs
(fun x : var Nat =>
Abs (fun y : var Nat => Plus (Var x) (Var y))))
(Const 1)) (Const 2)) (Const 3)
]]
One further development, which may seem surprising at first, is that we can also implement a usual term denotation function, when we _tag variables with their denotations_. *)
Fixpoint termDenote t (e : term typeDenote t) : typeDenote t :=
match e with
| Var _ v => v
| Const n => n
| Plus e1 e2 => termDenote e1 + termDenote e2
| Abs _ _ e1 => fun x => termDenote (e1 x)
| App _ _ e1 e2 => (termDenote e1) (termDenote e2)
| Let _ _ e1 e2 => termDenote (e2 (termDenote e1))
end.
Definition TermDenote t (E : Term t) : typeDenote t :=
termDenote (E typeDenote).
Eval compute in TermDenote three_the_hard_way.
(** %\vspace{-.15in}%[[
= 3
]]
To summarize, the PHOAS representation has all the expressive power of more standard first-order encodings, and a variety of translations are actually much more pleasant to implement than usual, thanks to the novel ability to tag variables with data. *)
(** ** Verifying Program Transformations *)
(** Let us now revisit the three example program transformations from the last section. Each is easy to implement with PHOAS, and the last is substantially easier than with first-order representations.
First, we have the recursive identity function, following the same pattern as in the previous subsection, with a helper function, polymorphic in a tag choice; and a final function that instantiates the choice appropriately. *)
Fixpoint ident var t (e : term var t) : term var t :=
match e with
| Var _ x => Var x
| Const n => Const n
| Plus e1 e2 => Plus (ident e1) (ident e2)
| Abs _ _ e1 => Abs (fun x => ident (e1 x))
| App _ _ e1 e2 => App (ident e1) (ident e2)
| Let _ _ e1 e2 => Let (ident e1) (fun x => ident (e2 x))
end.
Definition Ident t (E : Term t) : Term t := fun var =>
ident (E var).
(** Proving correctness is both easier and harder than in the last section, easier because we do not need to manipulate substitutions, and harder because we do the induction in an extra lemma about [ident], to establish the correctness theorem for [Ident]. *)
Lemma identSound : forall t (e : term typeDenote t),
termDenote (ident e) = termDenote e.
induction e; pl.
Qed.
Theorem IdentSound : forall t (E : Term t),
TermDenote (Ident E) = TermDenote E.
intros; apply identSound.
Qed.
(** The translation of the constant-folding function and its proof work more or less the same way. *)
Fixpoint cfold var t (e : term var t) : term var t :=
match e with
| Plus e1 e2 =>
let e1' := cfold e1 in
let e2' := cfold e2 in
match e1', e2' with
| Const n1, Const n2 => Const (n1 + n2)
| _, _ => Plus e1' e2'
end
| Abs _ _ e1 => Abs (fun x => cfold (e1 x))
| App _ _ e1 e2 => App (cfold e1) (cfold e2)
| Let _ _ e1 e2 => Let (cfold e1) (fun x => cfold (e2 x))
| e => e
end.
Definition Cfold t (E : Term t) : Term t := fun var =>
cfold (E var).
Lemma cfoldSound : forall t (e : term typeDenote t),
termDenote (cfold e) = termDenote e.
induction e; pl;
repeat (match goal with
| [ |- context[match ?E with Var _ _ => _ | _ => _ end] ] =>
dep_destruct E
end; pl).
Qed.
Theorem CfoldSound : forall t (E : Term t),
TermDenote (Cfold E) = TermDenote E.
intros; apply cfoldSound.
Qed.
(** Things get more interesting in the [Let]-removal optimization. Our recursive helper function adapts the key idea from our earlier definitions of [squash] and [Subst]: tag variables with terms. We have a straightforward generalization of [squash], where only the [Let] case has changed, to tag the new variable with the term it is bound to, rather than just tagging the variable with itself as a term. *)
Fixpoint unlet var t (e : term (term var) t) : term var t :=
match e with
| Var _ e1 => e1
| Const n => Const n
| Plus e1 e2 => Plus (unlet e1) (unlet e2)
| Abs _ _ e1 => Abs (fun x => unlet (e1 (Var x)))
| App _ _ e1 e2 => App (unlet e1) (unlet e2)
| Let _ _ e1 e2 => unlet (e2 (unlet e1))
end.
Definition Unlet t (E : Term t) : Term t := fun var =>
unlet (E (term var)).
(** We can test [Unlet] first on an uninteresting example, [three_the_hard_way], which does not use [Let]. *)
Eval compute in Unlet three_the_hard_way.
(** %\vspace{-.15in}%[[
= fun var : type -> Type =>
App
(App
(Abs
(fun x : var Nat =>
Abs (fun x0 : var Nat => Plus (Var x) (Var x0))))
(Const 1)) (Const 2)
]]
Next, we try a more interesting example, with some extra [Let]s introduced in [three_the_hard_way]. *)
Definition three_a_harder_way : Term Nat := fun _ =>
Let (Const 1) (fun x => Let (Const 2) (fun y => App (App (add _) (Var x)) (Var y))).
Eval compute in Unlet three_a_harder_way.
(** %\vspace{-.15in}%[[
= fun var : type -> Type =>
App
(App
(Abs
(fun x : var Nat =>
Abs (fun x0 : var Nat => Plus (Var x) (Var x0))))
(Const 1)) (Const 2)
]]
The output is the same as in the previous test, confirming that [Unlet] operates properly here.
Now we need to state a correctness theorem for [Unlet], based on an inductively proved lemma about [unlet]. It is not at all obvious how to arrive at a proper induction principle for the lemma. The problem is that we want to relate two instantiations of the same [Term], in a way where we know they share the same structure. Note that, while [Unlet] is defined to consider all possible [var] choices in the output term, the correctness proof conveniently only depends on the case of [var := typeDenote]. Thus, one parallel instantiation will set [var := typeDenote], to take the denotation of the original term. The other parallel instantiation will set [var := term typeDenote], to perform the [unlet] transformation in the original term.
Here is a relation formalizing the idea that two terms are structurally the same, differing only by replacing the variable data of one with another isomorphic set of variable data in some possibly different type family. *)
Section wf.
Variables var1 var2 : type -> Type.
(** To formalize the tag isomorphism, we will use lists of values with the following record type. Each entry has an object language type and an appropriate tag for that type, in each of the two tag families [var1] and [var2]. *)
Record varEntry := {
Ty : type;
First : var1 Ty;
Second : var2 Ty
}.
(** Here is the inductive relation definition. An instance [wf G e1 e2] asserts that terms [e1] and [e2] are equivalent up to the variable tag isomorphism [G]. Note how the [Var] rule looks up an entry in [G], and the [Abs] and [Let] rules include recursive [wf] invocations inside the scopes of quantifiers to introduce parallel tag values to be considered as isomorphic. *)
Inductive wf : list varEntry -> forall t, term var1 t -> term var2 t -> Prop :=
| WfVar : forall G t x x', In {| Ty := t; First := x; Second := x' |} G
-> wf G (Var x) (Var x')
| WfConst : forall G n, wf G (Const n) (Const n)
| WfPlus : forall G e1 e2 e1' e2', wf G e1 e1'
-> wf G e2 e2'
-> wf G (Plus e1 e2) (Plus e1' e2')
| WfAbs : forall G dom ran (e1 : _ dom -> term _ ran) e1',
(forall x1 x2, wf ({| First := x1; Second := x2 |} :: G) (e1 x1) (e1' x2))
-> wf G (Abs e1) (Abs e1')
| WfApp : forall G dom ran (e1 : term _ (Func dom ran)) (e2 : term _ dom) e1' e2',
wf G e1 e1'
-> wf G e2 e2'
-> wf G (App e1 e2) (App e1' e2')
| WfLet : forall G t1 t2 e1 e1' (e2 : _ t1 -> term _ t2) e2', wf G e1 e1'
-> (forall x1 x2, wf ({| First := x1; Second := x2 |} :: G) (e2 x1) (e2' x2))
-> wf G (Let e1 e2) (Let e1' e2').
End wf.
(** We can state a well-formedness condition for closed terms: for any two choices of tag type families, the parallel instantiations belong to the [wf] relation, starting from an empty variable isomorphism. *)
Definition Wf t (E : Term t) := forall var1 var2, wf nil (E var1) (E var2).
(** After digesting the syntactic details of [Wf], it is probably not hard to see that reasonable term encodings will satisfy it. For example: *)
Theorem three_the_hard_way_Wf : Wf three_the_hard_way.
red; intros; repeat match goal with
| [ |- wf _ _ _ ] => constructor; intros
end; intuition.
Qed.
(** Now we are ready to give a nice simple proof of correctness for [unlet]. First, we add one hint to apply a small variant of a standard library theorem connecting [Forall], a higher-order predicate asserting that every element of a list satisfies some property; and [In], the list membership predicate. *)
Hint Extern 1 => match goal with
| [ H1 : Forall _ _, H2 : In _ _ |- _ ] => apply (Forall_In H1 _ H2)
end.
(** The rest of the proof is about as automated as we could hope for. *)
Lemma unletSound : forall G t (e1 : term _ t) e2,
wf G e1 e2
-> Forall (fun ve => termDenote (First ve) = Second ve) G
-> termDenote (unlet e1) = termDenote e2.
induction 1; pl.
Qed.
Theorem UnletSound : forall t (E : Term t), Wf E
-> TermDenote (Unlet E) = TermDenote E.
intros; eapply unletSound; eauto.
Qed.
(** With this example, it is not obvious that the PHOAS encoding is more tractable than dependent de Bruijn. Where the de Bruijn version had [lift] and its helper functions, here we have [Wf] and its auxiliary definitions. In practice, [Wf] is defined once per object language, while such operations as [lift] often need to operate differently for different examples, forcing new implementations for new transformations.
The reader may also have come up with another objection: via Curry-Howard, [wf] proofs may be thought of as first-order encodings of term syntax! For instance, the [In] hypothesis of rule [WfVar] is equivalent to a [member] value. There is some merit to this objection. However, as the proofs above show, we are able to reason about transformations using first-order representation only for their inputs, not their outputs. Furthermore, explicit numbering of variables remains absent from the proofs.
Have we really avoided first-order reasoning about the output terms of translations? The answer depends on some subtle issues, which deserve a subsection of their own. *)
(** ** Establishing Term Well-Formedness *)
(** Can there be values of type [Term t] that are not well-formed according to [Wf]? We expect that Gallina satisfies key%\index{parametricity}% _parametricity_ %\cite{parametricity}% properties, which indicate how polymorphic types may only be inhabited by specific values. We omit details of parametricity theorems here, but [forall t (E : Term t), Wf E] follows the flavor of such theorems. One option would be to assert that fact as an axiom, "proving" that any output of any of our translations is well-formed. We could even prove the soundness of the theorem on paper meta-theoretically, say by considering some particular model of CIC.
To be more cautious, we could prove [Wf] for every term that interests us, threading such proofs through all transformations. Here is an example exercise of that kind, for [Unlet].
First, we prove that [wf] is _monotone_, in that a given instance continues to hold as we add new variable pairs to the variable isomorphism. *)
Hint Constructors wf.
Hint Extern 1 (In _ _) => simpl; tauto.
Hint Extern 1 (Forall _ _) => eapply Forall_weaken; [ eassumption | simpl ].
Lemma wf_monotone : forall var1 var2 G t (e1 : term var1 t) (e2 : term var2 t),
wf G e1 e2
-> forall G', Forall (fun x => In x G') G
-> wf G' e1 e2.
induction 1; pl; auto 6.
Qed.
Hint Resolve wf_monotone Forall_In'.
(** Now we are ready to prove that [unlet] preserves any [wf] instance. The key invariant has to do with the parallel execution of [unlet] on two different [var] instantiations of a particular term. Since [unlet] uses [term] as the type of variable data, our variable isomorphism context [G] contains pairs of terms, which, conveniently enough, allows us to state the invariant that any pair of terms in the context is also related by [wf]. *)
Hint Extern 1 (wf _ _ _) => progress simpl.
Lemma unletWf : forall var1 var2 G t (e1 : term (term var1) t) (e2 : term (term var2) t),
wf G e1 e2
-> forall G', Forall (fun ve => wf G' (First ve) (Second ve)) G
-> wf G' (unlet e1) (unlet e2).
induction 1; pl; eauto 9.
Qed.
(** Repackaging [unletWf] into a theorem about [Wf] and [Unlet] is straightforward. *)
Theorem UnletWf : forall t (E : Term t), Wf E
-> Wf (Unlet E).
red; intros; apply unletWf with nil; auto.
Qed.
(** This example demonstrates how we may need to use reasoning reminiscent of that associated with first-order representations, though the bookkeeping details are generally easier to manage, and bookkeeping theorems may generally be proved separately from the independently interesting theorems about program transformations. *)
(** ** A Few More Remarks *)
(** Higher-order encodings derive their strength from reuse of the meta language's binding constructs. As a result, we can write encoded terms so that they look very similar to their informal counterparts, without variable numbering schemes like for de Bruijn indices. The example encodings above have demonstrated this fact, but modulo the clunkiness of explicit use of the constructors of [term]. After defining a few new Coq syntax notations, we can work with terms in an even more standard form. *)
Infix "-->" := Func (right associativity, at level 52).
Notation "^" := Var.
Notation "#" := Const.
Infix "@" := App (left associativity, at level 50).
Infix "@+" := Plus (left associativity, at level 50).
Notation "\ x : t , e" := (Abs (dom := t) (fun x => e))
(no associativity, at level 51, x at level 0).
Notation "[ e ]" := (fun _ => e).
Example Add : Term (Nat --> Nat --> Nat) :=
[\x : Nat, \y : Nat, ^x @+ ^y].
Example Three_the_hard_way : Term Nat :=
[Add _ @ #1 @ #2].
Eval compute in TermDenote Three_the_hard_way.
(** %\vspace{-.15in}%[[
= 3
]]
*)
End HigherOrder.
(** The PHOAS approach shines here because we are working with an object language that has an easy embedding into Coq. That is, there is a straightforward recursive function translating object terms into terms of Gallina. All Gallina programs terminate, so clearly we cannot hope to find such embeddings for Turing-complete languages; and non-Turing-complete languages may still require much more involved translations. I have some work%~\cite{CompilerPOPL10}% on modeling semantics of Turing-complete languages with PHOAS, but my impression is that there are many more advances left to be made in this field, possibly with completely new term representations that we have not yet been clever enough to think up. *)
|
module FIFO_four(
input wire clk,
input wire reset,
input wire write,
input wire read,
input wire [7:0] data_in,
output reg [7:0] data_out,
output wire full,
output wire empty
);
reg [4:0] write_pointer;
reg [4:0] read_pointer;
reg [7:0] memory [0:15];
wire upper;
wire [3:0] lower;
assign empty = (read_pointer == write_pointer) ? 1'b1 : 1'b0;
assign full = ((read_pointer[3:0] == write_pointer[3:0]) &&(read_pointer[4] != write_pointer[4]));
always@(posedge clk or negedge reset)
begin
if( !reset )
begin
read_pointer <= 0;
data_out <= 8'bz;
end
else
begin
case( read_pointer[3:0] )
0:
begin
if( !empty && read )
begin
if( ( read_pointer + 1 ) < 32 )
begin
read_pointer <= read_pointer + 1;
data_out <= memory[read_pointer[3:0]];
end
else
begin
read_pointer <= 0;
data_out <= memory[read_pointer[3:0]];
end
end
else
begin
read_pointer <= read_pointer;
data_out <= 8'bz;
end
end
1:
begin
if( !empty && read )
begin
if( ( read_pointer + 1 ) < 32 )
begin
read_pointer <= read_pointer + 1;
data_out <= memory[read_pointer[3:0]];
end
else
begin
read_pointer <= 0;
data_out <= memory[read_pointer[3:0]];
end
end
else
begin
read_pointer <= read_pointer;
data_out <= 8'bz;
end
end
2:
begin
if( !empty && read )
begin
if( ( read_pointer + 1 ) < 32 )
begin
read_pointer <= read_pointer + 1;
data_out <= memory[read_pointer[3:0]];
end
else
begin
read_pointer <= 0;
data_out <= memory[read_pointer[3:0]];
end
end
else
begin
read_pointer <= read_pointer;
data_out <= 8'bz;
end
end
3:
begin
if( !empty && read )
begin
if( ( read_pointer + 1 ) < 32 )
begin
read_pointer <= read_pointer + 1;
data_out <= memory[read_pointer[3:0]];
end
else
begin
read_pointer <= 0;
data_out <= memory[read_pointer[3:0]];
end
end
else
begin
read_pointer <= read_pointer;
data_out <= 8'bz;
end
end
4:
begin
if( !empty && read )
begin
if( ( read_pointer + 1 ) < 32 )
begin
read_pointer <= read_pointer + 1;
data_out <= memory[read_pointer[3:0]];
end
else
begin
read_pointer <= 0;
data_out <= memory[read_pointer[3:0]];
end
end
else
begin
read_pointer <= read_pointer;
data_out <= 8'bz;
end
end
5:
begin
if( !empty && read )
begin
if( ( read_pointer + 1 ) < 32 )
begin
read_pointer <= read_pointer + 1;
data_out <= memory[read_pointer[3:0]];
end
else
begin
read_pointer <= 0;
data_out <= memory[read_pointer[3:0]];
end
end
else
begin
read_pointer <= read_pointer;
data_out <= 8'bz;
end
end
6:
begin
if( !empty && read )
begin
if( ( read_pointer + 1 ) < 32 )
begin
read_pointer <= read_pointer + 1;
data_out <= memory[read_pointer[3:0]];
end
else
begin
read_pointer <= 0;
data_out <= memory[read_pointer[3:0]];
end
end
else
begin
read_pointer <= read_pointer;
data_out <= 8'bz;
end
end
7:
begin
if( !empty && read )
begin
if( ( read_pointer + 1 ) < 32 )
begin
read_pointer <= read_pointer + 1;
data_out <= memory[read_pointer[3:0]];
end
else
begin
read_pointer <= 0;
data_out <= memory[read_pointer[3:0]];
end
end
else
begin
read_pointer <= read_pointer;
data_out <= 8'bz;
end
end
8:
begin
if( !empty && read )
begin
if( ( read_pointer + 1 ) < 32 )
begin
read_pointer <= read_pointer + 1;
data_out <= memory[read_pointer[3:0]];
end
else
begin
read_pointer <= 0;
data_out <= memory[read_pointer[3:0]];
end
end
else
begin
read_pointer <= read_pointer;
data_out <= 8'bz;
end
end
9:
begin
if( !empty && read )
begin
if( ( read_pointer + 1 ) < 32 )
begin
read_pointer <= read_pointer + 1;
data_out <= memory[read_pointer[3:0]];
end
else
begin
read_pointer <= 0;
data_out <= memory[read_pointer[3:0]];
end
end
else
begin
read_pointer <= read_pointer;
data_out <= 8'bz;
end
end
10:
begin
if( !empty && read )
begin
if( ( read_pointer + 1 ) < 32 )
begin
read_pointer <= read_pointer + 1;
data_out <= memory[read_pointer[3:0]];
end
else
begin
read_pointer <= 0;
data_out <= memory[read_pointer[3:0]];
end
end
else
begin
read_pointer <= read_pointer;
data_out <= 8'bz;
end
end
11:
begin
if( !empty && read )
begin
if( ( read_pointer + 1 ) < 32 )
begin
read_pointer <= read_pointer + 1;
data_out <= memory[read_pointer[3:0]];
end
else
begin
read_pointer <= 0;
data_out <= memory[read_pointer[3:0]];
end
end
else
begin
read_pointer <= read_pointer;
data_out <= 8'bz;
end
end
12:
begin
if( !empty && read )
begin
if( ( read_pointer + 1 ) < 32 )
begin
read_pointer <= read_pointer + 1;
data_out <= memory[read_pointer[3:0]];
end
else
begin
read_pointer <= 0;
data_out <= memory[read_pointer[3:0]];
end
end
else
begin
read_pointer <= read_pointer;
data_out <= 8'bz;
end
end
13:
begin
if( !empty && read )
begin
if( ( read_pointer + 1 ) < 32 )
begin
read_pointer <= read_pointer + 1;
data_out <= memory[read_pointer[3:0]];
end
else
begin
read_pointer <= 0;
data_out <= memory[read_pointer[3:0]];
end
end
else
begin
read_pointer <= read_pointer;
data_out <= 8'bz;
end
end
14:
begin
if( !empty && read )
begin
if( ( read_pointer + 1 ) < 32 )
begin
read_pointer <= read_pointer + 1;
data_out <= memory[read_pointer[3:0]];
end
else
begin
read_pointer <= 0;
data_out <= memory[read_pointer[3:0]];
end
end
else
begin
read_pointer <= read_pointer;
data_out <= 8'bz;
end
end
15:
begin
if( !empty && read )
begin
if( ( read_pointer + 1 ) < 32 )
begin
read_pointer <= read_pointer + 1;
data_out <= memory[read_pointer[3:0]];
end
else
begin
read_pointer <= 0;
data_out <= memory[read_pointer[3:0]];
end
end
else
begin
read_pointer <= read_pointer;
data_out <= 8'bz;
end
end
endcase
end
end
always@(posedge clk or negedge reset)
begin
if( !reset )
begin
write_pointer <= 0;
end
else
begin
case( write_pointer[3:0] )
0:
begin
if( !full && write )
begin
if( ( write_pointer + 1 ) < 32 )
begin
write_pointer <= write_pointer + 1;
memory[write_pointer[3:0]] <= data_in;
end
else
begin
write_pointer <= 0;
memory[write_pointer[3:0]] <= data_in;
end
end
else
begin
write_pointer <= write_pointer;
end
end
1:
begin
if( !full && write )
begin
if( ( write_pointer + 1 ) < 32 )
begin
write_pointer <= write_pointer + 1;
memory[write_pointer[3:0]] <= data_in;
end
else
begin
write_pointer <= 0;
memory[write_pointer[3:0]] <= data_in;
end
end
else
begin
write_pointer <= write_pointer;
end
end
2:
begin
if( !full && write )
begin
if( ( write_pointer + 1 ) < 32 )
begin
write_pointer <= write_pointer + 1;
memory[write_pointer[3:0]] <= data_in;
end
else
begin
write_pointer <= 0;
memory[write_pointer[3:0]] <= data_in;
end
end
else
begin
write_pointer <= write_pointer;
end
end
3:
begin
if( !full && write )
begin
if( ( write_pointer + 1 ) < 32 )
begin
write_pointer <= write_pointer + 1;
memory[write_pointer[3:0]] <= data_in;
end
else
begin
write_pointer <= 0;
memory[write_pointer[3:0]] <= data_in;
end
end
else
begin
write_pointer <= write_pointer;
end
end
4:
begin
if( !full && write )
begin
if( ( write_pointer + 1 ) < 32 )
begin
write_pointer <= write_pointer + 1;
memory[write_pointer[3:0]] <= data_in;
end
else
begin
write_pointer <= 0;
memory[write_pointer[3:0]] <= data_in;
end
end
else
begin
write_pointer <= write_pointer;
end
end
5:
begin
if( !full && write )
begin
if( ( write_pointer + 1 ) < 32 )
begin
write_pointer <= write_pointer + 1;
memory[write_pointer[3:0]] <= data_in;
end
else
begin
write_pointer <= 0;
memory[write_pointer[3:0]] <= data_in;
end
end
else
begin
write_pointer <= write_pointer;
end
end
6:
begin
if( !full && write )
begin
if( ( write_pointer + 1 ) < 32 )
begin
write_pointer <= write_pointer + 1;
memory[write_pointer[3:0]] <= data_in;
end
else
begin
write_pointer <= 0;
memory[write_pointer[3:0]] <= data_in;
end
end
else
begin
write_pointer <= write_pointer;
end
end
7:
begin
if( !full && write )
begin
if( ( write_pointer + 1 ) < 32 )
begin
write_pointer <= write_pointer + 1;
memory[write_pointer[3:0]] <= data_in;
end
else
begin
write_pointer <= 0;
memory[write_pointer[3:0]] <= data_in;
end
end
else
begin
write_pointer <= write_pointer;
end
end
8:
begin
if( !full && write )
begin
if( ( write_pointer + 1 ) < 32 )
begin
write_pointer <= write_pointer + 1;
memory[write_pointer[3:0]] <= data_in;
end
else
begin
write_pointer <= 0;
memory[write_pointer[3:0]] <= data_in;
end
end
else
begin
write_pointer <= write_pointer;
end
end
9:
begin
if( !full && write )
begin
if( ( write_pointer + 1 ) < 32 )
begin
write_pointer <= write_pointer + 1;
memory[write_pointer[3:0]] <= data_in;
end
else
begin
write_pointer <= 0;
memory[write_pointer[3:0]] <= data_in;
end
end
else
begin
write_pointer <= write_pointer;
end
end
10:
begin
if( !full && write )
begin
if( ( write_pointer + 1 ) < 32 )
begin
write_pointer <= write_pointer + 1;
memory[write_pointer[3:0]] <= data_in;
end
else
begin
write_pointer <= 0;
memory[write_pointer[3:0]] <= data_in;
end
end
else
begin
write_pointer <= write_pointer;
end
end
11:
begin
if( !full && write )
begin
if( ( write_pointer + 1 ) < 32 )
begin
write_pointer <= write_pointer + 1;
memory[write_pointer[3:0]] <= data_in;
end
else
begin
write_pointer <= 0;
memory[write_pointer[3:0]] <= data_in;
end
end
else
begin
write_pointer <= write_pointer;
end
end
12:
begin
if( !full && write )
begin
if( ( write_pointer + 1 ) < 32 )
begin
write_pointer <= write_pointer + 1;
memory[write_pointer[3:0]] <= data_in;
end
else
begin
write_pointer <= 0;
memory[write_pointer[3:0]] <= data_in;
end
end
else
begin
write_pointer <= write_pointer;
end
end
13:
begin
if( !full && write )
begin
if( ( write_pointer + 1 ) < 32 )
begin
write_pointer <= write_pointer + 1;
memory[write_pointer[3:0]] <= data_in;
end
else
begin
write_pointer <= 0;
memory[write_pointer[3:0]] <= data_in;
end
end
else
begin
write_pointer <= write_pointer;
end
end
14:
begin
if( !full && write )
begin
if( ( write_pointer + 1 ) < 32 )
begin
write_pointer <= write_pointer + 1;
memory[write_pointer[3:0]] <= data_in;
end
else
begin
write_pointer <= 0;
memory[write_pointer[3:0]] <= data_in;
end
end
else
begin
write_pointer <= write_pointer;
end
end
15:
begin
if( !full && write )
begin
if( ( write_pointer + 1 ) < 32 )
begin
write_pointer <= write_pointer + 1;
memory[write_pointer[3:0]] <= data_in;
end
else
begin
write_pointer <= 0;
memory[write_pointer[3:0]] <= data_in;
end
end
else
begin
write_pointer <= write_pointer;
end
end
endcase
end
end
endmodule
/*
module FIFO_testbench();
reg clk;
reg reset;
reg write;
reg read;
reg [7:0] data_in;
wire [7:0] data_out;
wire full;
wire empty;
FIFO_four u1 (clk, reset, write, read, data_in, data_out, full, empty);
always
begin
#5 clk <= ~clk;
end
initial
begin
clk = 1;
#20
reset = 0;
write = 0;
read = 0;
data_in = 0;
#20
reset = 1;
#20
repeat(18)
begin
#10
write = 1;
data_in = data_in + 2;
#10
write = 0;
end
$finish;
end
endmodule
*/
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_aa_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_aa_e.v,v 1.3 2006/06/26 08:39:43 wig Exp $
// $Date: 2006/06/26 08:39:43 $
// $Log: inst_aa_e.v,v $
// Revision 1.3 2006/06/26 08:39:43 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_aa_e
//
// No `defines in this module
module inst_aa_e
//
// Generated Module inst_aa
//
(
);
// Module parameters:
parameter NO_DEFAULT; // = __W_NODEFAULT;
parameter NO_NAME; // = __W_NODEFAULT;
parameter PRE_GENERIC = 7;
parameter WIDTH = 7;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_aa_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="zbroji,hls_ip_2013_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.440000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}" *)
module zbroji (
ap_start,
ap_done,
ap_idle,
ap_ready,
a,
b,
ap_return
);
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [31:0] a;
input [31:0] b;
output [31:0] ap_return;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
assign ap_done = ap_start;
assign ap_idle = ap_const_logic_1;
assign ap_ready = ap_start;
assign ap_return = (b + a);
endmodule //zbroji
|
/////////////////////////////////////////////////////////////////////
//// ////
//// OpenCores Simple Programmable Interrupt Controller ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: simple_pic.v,v 1.3 2002-12-24 10:26:51 rherveille Exp $
//
// $Date: 2002-12-24 10:26:51 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/12/22 16:11:03 rherveille
// *** empty log message ***
//
//
//
// This is a simple Programmable Interrupt Controller.
// The number of interrupts is depending on the databus size.
// There's one interrupt input per databit (i.e. 16 interrupts for a 16
// bit databus).
// All attached devices share the same CPU priority level.
//
//
//
// Registers:
//
// 0x00: EdgeEnable Register
// bits 7:0 R/W Edge Enable '1' = edge triggered interrupt source
// '0' = level triggered interrupt source
// 0x01: PolarityRegister
// bits 7:0 R/W Polarity '1' = high level / rising edge
// '0' = low level / falling edge
// 0x02: MaskRegister
// bits 7:0 R/W Mask '1' = interrupt masked (disabled)
// '0' = interrupt not masked (enabled)
// 0x03: PendingRegister
// bits 7:0 R/W Pending '1' = interrupt pending
// '0' = no interrupt pending
//
// A CPU interrupt is generated when an interrupt is pending and its
// MASK bit is cleared.
//
//
//
// HOWTO:
//
// Clearing pending interrupts:
// Writing a '1' to a bit in the interrupt pending register clears the
// interrupt. Make sure to clear the interrupt at the source before
// writing to the interrupt pending register. Otherwise the interrupt
// will be set again.
//
// Priority based interrupts:
// Upon reception of an interrupt, check the interrupt register and
// determine the highest priority interrupt. Mask all interrupts from the
// current level to the lowest level. This negates the interrupt line, and
// makes sure only interrupts with a higher level are triggered. After
// completion of the interrupt service routine, clear the interrupt source,
// the interrupt bit in the pending register, and restore the MASK register
// to it's previous state.
//
// Addapt the core for fewer interrupt sources:
// If less than 8 interrupt sources are required, than the 'is' parameter
// can be set to the amount of required interrupts. Interrupts are mapped
// starting at the LSBs. So only the 'is' LSBs per register are valid. All
// other bits (i.e. the 8-'is' MSBs) are set to zero '0'.
// Codesize is approximately linear to the amount of interrupts. I.e. using
// 4 instead of 8 interrupt sources reduces the size by approx. half.
//
// synopsys translate_off
//`include "timescale.v"
// synopsys translate_on
module simple_pic #(parameter int NUM_IRQ=32) (
clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o, int_o,
irq
);
//
// Inputs & outputs
//
// 8bit WISHBONE bus slave interface
input clk_i; // clock
input rst_i; // reset (asynchronous active low)
input cyc_i; // cycle
input stb_i; // strobe (cycle and strobe are the same signal)
input [ 2:1] adr_i; // address
input we_i; // write enable
input [ 31:0] dat_i; // data output
output [ 31:0] dat_o; // data input
output ack_o; // normal bus termination
output int_o; // interrupt output
//
// Interrupt sources
//
input [NUM_IRQ:1] irq; // interrupt request inputs
//
// Module body
//
reg [NUM_IRQ:1] pol, edgen, pending, mask; // register bank
reg [NUM_IRQ:1] lirq, dirq; // latched irqs, delayed latched irqs
//
// perform parameter checks
//
// synopsys translate_off
initial
begin
if(NUM_IRQ > 32)
$display("simple_pic: max. 32 interrupt sources supported.");
end
// synopsys translate_on
//
// latch interrupt inputs
always @(posedge clk_i)
lirq <= irq;
//
// generate delayed latched irqs
always @(posedge clk_i)
dirq <= lirq;
//
// generate actual triggers
function trigger;
input edgen, pol, lirq, dirq;
reg edge_irq, level_irq;
begin
edge_irq = pol ? (lirq & ~dirq) : (dirq & ~lirq);
level_irq = pol ? lirq : ~lirq;
trigger = edgen ? edge_irq : level_irq;
end
endfunction
reg [NUM_IRQ:1] irq_event;
integer n;
always @(posedge clk_i)
for(n=1; n<=NUM_IRQ; n=n+1)
irq_event[n] <= trigger(edgen[n], pol[n], lirq[n], dirq[n]);
//
// generate wishbone register bank writes
wire wb_acc = cyc_i & stb_i; // WISHBONE access
wire wb_wr = wb_acc & we_i; // WISHBONE write access
always @(posedge clk_i or negedge rst_i)
if (~rst_i)
begin
pol <= {{NUM_IRQ}{1'b0}}; // clear polarity register
edgen <= {{NUM_IRQ}{1'b0}}; // clear edge enable register
mask <= {{NUM_IRQ}{1'b1}}; // mask all interrupts
end
else if(wb_wr) // wishbone write cycle??
case (adr_i) // synopsys full_case parallel_case
2'b00: edgen <= dat_i[NUM_IRQ-1:0]; // EDGE-ENABLE register
2'b01: pol <= dat_i[NUM_IRQ-1:0]; // POLARITY register
2'b10: mask <= dat_i[NUM_IRQ-1:0]; // MASK register
2'b11: ; // PENDING register is a special case (see below)
endcase
// pending register is a special case
always @(posedge clk_i or negedge rst_i)
if (~rst_i)
pending <= {{NUM_IRQ}{1'b0}}; // clear all pending interrupts
else if ( wb_wr & (&adr_i) )
pending <= (pending & ~dat_i[NUM_IRQ-1:0]) | irq_event;
else
pending <= pending | irq_event;
//
// generate dat_o
reg [31:0] dat_o;
always @(posedge clk_i)
case (adr_i) // synopsys full_case parallel_case
2'b00: dat_o <= { {{32-NUM_IRQ}{1'b0}}, edgen};
2'b01: dat_o <= { {{32-NUM_IRQ}{1'b0}}, pol};
2'b10: dat_o <= { {{32-NUM_IRQ}{1'b0}}, mask};
2'b11: dat_o <= { {{32-NUM_IRQ}{1'b0}}, pending};
endcase
//
// generate ack_o
reg ack_o;
always @(posedge clk_i)
ack_o <= wb_acc & !ack_o;
//
// generate CPU interrupt signal
reg int_o;
always @(posedge clk_i)
int_o <= |(pending & ~mask);
endmodule
|
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// CLK I 1 clock
// RST_N I 1 reset
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkTop_HW_Side(CLK,
RST_N);
input CLK;
input RST_N;
// register rg_banner_printed
reg rg_banner_printed;
wire rg_banner_printed$D_IN, rg_banner_printed$EN;
// register rg_console_in_poll
reg [11 : 0] rg_console_in_poll;
wire [11 : 0] rg_console_in_poll$D_IN;
wire rg_console_in_poll$EN;
// ports of submodule mem_model
wire [352 : 0] mem_model$mem_server_request_put;
wire [255 : 0] mem_model$mem_server_response_get;
wire mem_model$EN_mem_server_request_put,
mem_model$EN_mem_server_response_get,
mem_model$RDY_mem_server_request_put,
mem_model$RDY_mem_server_response_get;
// ports of submodule soc_top
wire [352 : 0] soc_top$to_raw_mem_request_get;
wire [255 : 0] soc_top$to_raw_mem_response_put;
wire [63 : 0] soc_top$set_verbosity_logdelay,
soc_top$set_watch_tohost_tohost_addr;
wire [7 : 0] soc_top$get_to_console_get,
soc_top$put_from_console_put,
soc_top$status;
wire [3 : 0] soc_top$set_verbosity_verbosity;
wire soc_top$EN_get_to_console_get,
soc_top$EN_put_from_console_put,
soc_top$EN_set_verbosity,
soc_top$EN_set_watch_tohost,
soc_top$EN_to_raw_mem_request_get,
soc_top$EN_to_raw_mem_response_put,
soc_top$RDY_get_to_console_get,
soc_top$RDY_put_from_console_put,
soc_top$RDY_to_raw_mem_request_get,
soc_top$RDY_to_raw_mem_response_put,
soc_top$set_watch_tohost_watch_tohost;
// rule scheduling signals
wire CAN_FIRE_RL_memCnx_ClientServerRequest,
CAN_FIRE_RL_memCnx_ClientServerResponse,
CAN_FIRE_RL_rl_relay_console_in,
CAN_FIRE_RL_rl_relay_console_out,
CAN_FIRE_RL_rl_step0,
CAN_FIRE_RL_rl_terminate,
WILL_FIRE_RL_memCnx_ClientServerRequest,
WILL_FIRE_RL_memCnx_ClientServerResponse,
WILL_FIRE_RL_rl_relay_console_in,
WILL_FIRE_RL_rl_relay_console_out,
WILL_FIRE_RL_rl_step0,
WILL_FIRE_RL_rl_terminate;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h702;
reg [31 : 0] v__h743;
reg TASK_testplusargs___d12;
reg TASK_testplusargs___d11;
reg TASK_testplusargs___d15;
reg [63 : 0] tohost_addr__h571;
reg [31 : 0] v__h633;
reg [7 : 0] v__h941;
reg [31 : 0] v__h627;
reg [31 : 0] v__h737;
reg [31 : 0] v__h696;
// synopsys translate_on
// submodule mem_model
mkMem_Model mem_model(.CLK(CLK),
.RST_N(RST_N),
.mem_server_request_put(mem_model$mem_server_request_put),
.EN_mem_server_request_put(mem_model$EN_mem_server_request_put),
.EN_mem_server_response_get(mem_model$EN_mem_server_response_get),
.RDY_mem_server_request_put(mem_model$RDY_mem_server_request_put),
.mem_server_response_get(mem_model$mem_server_response_get),
.RDY_mem_server_response_get(mem_model$RDY_mem_server_response_get));
// submodule soc_top
mkSoC_Top soc_top(.CLK(CLK),
.RST_N(RST_N),
.put_from_console_put(soc_top$put_from_console_put),
.set_verbosity_logdelay(soc_top$set_verbosity_logdelay),
.set_verbosity_verbosity(soc_top$set_verbosity_verbosity),
.set_watch_tohost_tohost_addr(soc_top$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(soc_top$set_watch_tohost_watch_tohost),
.to_raw_mem_response_put(soc_top$to_raw_mem_response_put),
.EN_set_verbosity(soc_top$EN_set_verbosity),
.EN_to_raw_mem_request_get(soc_top$EN_to_raw_mem_request_get),
.EN_to_raw_mem_response_put(soc_top$EN_to_raw_mem_response_put),
.EN_get_to_console_get(soc_top$EN_get_to_console_get),
.EN_put_from_console_put(soc_top$EN_put_from_console_put),
.EN_set_watch_tohost(soc_top$EN_set_watch_tohost),
.RDY_set_verbosity(),
.to_raw_mem_request_get(soc_top$to_raw_mem_request_get),
.RDY_to_raw_mem_request_get(soc_top$RDY_to_raw_mem_request_get),
.RDY_to_raw_mem_response_put(soc_top$RDY_to_raw_mem_response_put),
.get_to_console_get(soc_top$get_to_console_get),
.RDY_get_to_console_get(soc_top$RDY_get_to_console_get),
.RDY_put_from_console_put(soc_top$RDY_put_from_console_put),
.status(soc_top$status),
.RDY_set_watch_tohost());
// rule RL_rl_terminate
assign CAN_FIRE_RL_rl_terminate = soc_top$status != 8'd0 ;
assign WILL_FIRE_RL_rl_terminate = CAN_FIRE_RL_rl_terminate ;
// rule RL_rl_step0
assign CAN_FIRE_RL_rl_step0 = !rg_banner_printed ;
assign WILL_FIRE_RL_rl_step0 = CAN_FIRE_RL_rl_step0 ;
// rule RL_rl_relay_console_out
assign CAN_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ;
assign WILL_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ;
// rule RL_rl_relay_console_in
assign CAN_FIRE_RL_rl_relay_console_in =
rg_console_in_poll != 12'd0 || soc_top$RDY_put_from_console_put ;
assign WILL_FIRE_RL_rl_relay_console_in = CAN_FIRE_RL_rl_relay_console_in ;
// rule RL_memCnx_ClientServerRequest
assign CAN_FIRE_RL_memCnx_ClientServerRequest =
soc_top$RDY_to_raw_mem_request_get &&
mem_model$RDY_mem_server_request_put ;
assign WILL_FIRE_RL_memCnx_ClientServerRequest =
CAN_FIRE_RL_memCnx_ClientServerRequest ;
// rule RL_memCnx_ClientServerResponse
assign CAN_FIRE_RL_memCnx_ClientServerResponse =
soc_top$RDY_to_raw_mem_response_put &&
mem_model$RDY_mem_server_response_get ;
assign WILL_FIRE_RL_memCnx_ClientServerResponse =
CAN_FIRE_RL_memCnx_ClientServerResponse ;
// register rg_banner_printed
assign rg_banner_printed$D_IN = 1'd1 ;
assign rg_banner_printed$EN = CAN_FIRE_RL_rl_step0 ;
// register rg_console_in_poll
assign rg_console_in_poll$D_IN = rg_console_in_poll + 12'd1 ;
assign rg_console_in_poll$EN = CAN_FIRE_RL_rl_relay_console_in ;
// submodule mem_model
assign mem_model$mem_server_request_put = soc_top$to_raw_mem_request_get ;
assign mem_model$EN_mem_server_request_put =
CAN_FIRE_RL_memCnx_ClientServerRequest ;
assign mem_model$EN_mem_server_response_get =
CAN_FIRE_RL_memCnx_ClientServerResponse ;
// submodule soc_top
assign soc_top$put_from_console_put = v__h941 ;
assign soc_top$set_verbosity_logdelay = 64'd0 ;
assign soc_top$set_verbosity_verbosity =
TASK_testplusargs___d11 ?
4'd2 :
(TASK_testplusargs___d12 ? 4'd1 : 4'd0) ;
assign soc_top$set_watch_tohost_tohost_addr = tohost_addr__h571 ;
assign soc_top$set_watch_tohost_watch_tohost = TASK_testplusargs___d15 ;
assign soc_top$to_raw_mem_response_put = mem_model$mem_server_response_get ;
assign soc_top$EN_set_verbosity = CAN_FIRE_RL_rl_step0 ;
assign soc_top$EN_to_raw_mem_request_get =
CAN_FIRE_RL_memCnx_ClientServerRequest ;
assign soc_top$EN_to_raw_mem_response_put =
CAN_FIRE_RL_memCnx_ClientServerResponse ;
assign soc_top$EN_get_to_console_get = soc_top$RDY_get_to_console_get ;
assign soc_top$EN_put_from_console_put =
WILL_FIRE_RL_rl_relay_console_in &&
rg_console_in_poll == 12'd0 &&
v__h941 != 8'd0 ;
assign soc_top$EN_set_watch_tohost = CAN_FIRE_RL_rl_step0 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_banner_printed <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_console_in_poll <= `BSV_ASSIGNMENT_DELAY 12'd0;
end
else
begin
if (rg_banner_printed$EN)
rg_banner_printed <= `BSV_ASSIGNMENT_DELAY rg_banner_printed$D_IN;
if (rg_console_in_poll$EN)
rg_console_in_poll <= `BSV_ASSIGNMENT_DELAY rg_console_in_poll$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_banner_printed = 1'h0;
rg_console_in_poll = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate)
begin
v__h702 = $stime;
#0;
end
v__h696 = v__h702 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate)
$display("%0d: %m:.rl_terminate: soc_top status is 0x%0h (= 0d%0d)",
v__h696,
soc_top$status,
soc_top$status);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate)
begin
v__h743 = $stime;
#0;
end
v__h737 = v__h743 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate)
$imported_c_end_timing({ 32'd0, v__h737 });
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate) $finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("Bluespec RISC-V standalone system simulation v1.2");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
TASK_testplusargs___d12 = $test$plusargs("v1");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
TASK_testplusargs___d11 = $test$plusargs("v2");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
TASK_testplusargs___d15 = $test$plusargs("tohost");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
tohost_addr__h571 = $imported_c_get_symbol_val("tohost");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("INFO: watch_tohost = %0d, tohost_addr = 0x%0h",
TASK_testplusargs___d15,
tohost_addr__h571);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
v__h633 = $stime;
#0;
end
v__h627 = v__h633 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0) $imported_c_start_timing({ 32'd0, v__h627 });
if (RST_N != `BSV_RESET_VALUE)
if (soc_top$RDY_get_to_console_get)
$write("%c", soc_top$get_to_console_get);
if (RST_N != `BSV_RESET_VALUE)
if (soc_top$RDY_get_to_console_get) $fflush(32'h80000001);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_relay_console_in && rg_console_in_poll == 12'd0)
begin
v__h941 = $imported_c_trygetchar(8'hAA);
#0;
end
end
// synopsys translate_on
endmodule // mkTop_HW_Side
|
/****************************************
MIST1032ISA Processor
****************************************/
`default_nettype none
`include "processor.h"
`include "common.h"
module mist1032isa(
/****************************************
System
****************************************/
input wire iCORE_CLOCK,
input wire iBUS_CLOCK,
input wire iDPS_CLOCK,
input wire inRESET,
/****************************************
SCI
****************************************/
output wire oSCI_TXD,
input wire iSCI_RXD,
/****************************************
Memory BUS
****************************************/
//Req
output wire oMEMORY_REQ,
input wire iMEMORY_LOCK,
output wire [1:0] oMEMORY_ORDER, //00=Byte Order 01=2Byte Order 10= Word Order 11= None
output wire [3:0] oMEMORY_MASK,
output wire oMEMORY_RW, //1:Write | 0:Read
output wire [31:0] oMEMORY_ADDR,
//This -> Data RAM
output wire [31:0] oMEMORY_DATA,
//Data RAM -> This
input wire iMEMORY_VALID,
output wire oMEMORY_BUSY,
input wire [63:0] iMEMORY_DATA,
/****************************************
GCI BUS
****************************************/
//Request
output wire oGCI_REQ, //Input
input wire iGCI_BUSY,
output wire oGCI_RW, //0=Read : 1=Write
output wire [31:0] oGCI_ADDR,
output wire [31:0] oGCI_DATA,
//Return
input wire iGCI_REQ, //Output
output wire oGCI_BUSY,
input wire [31:0] iGCI_DATA,
//Interrupt
input wire iGCI_IRQ_REQ,
input wire [5:0] iGCI_IRQ_NUM,
output wire oGCI_IRQ_ACK,
//Interrupt Controll
output wire oIO_IRQ_CONFIG_TABLE_REQ,
output wire [5:0] oIO_IRQ_CONFIG_TABLE_ENTRY,
output wire oIO_IRQ_CONFIG_TABLE_FLAG_MASK,
output wire oIO_IRQ_CONFIG_TABLE_FLAG_VALID,
output wire [1:0] oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL,
output wire [31:0] oDEBUG_PC,
output wire [31:0] oDEBUG0,
/****************************************
Debug
****************************************/
input wire iDEBUG_UART_RXD,
output wire oDEBUG_UART_TXD,
input wire iDEBUG_PARA_REQ,
output wire oDEBUG_PARA_BUSY,
input wire [7:0] iDEBUG_PARA_CMD,
input wire [31:0] iDEBUG_PARA_DATA,
output wire oDEBUG_PARA_VALID,
input wire iDEBUG_PARA_BUSY,
output wire oDEBUG_PARA_ERROR,
output wire [31:0] oDEBUG_PARA_DATA
);
/****************************************
Register and Wire
****************************************/
//Core 2 This
wire free_tlb_flush;
//Memory
wire core2mem_inst_req;
wire mem2core_inst_lock;
wire [1:0] core2mem_inst_mmumod;
wire [2:0] core2mem_inst_mmups;
wire [31:0] core2mem_inst_pdt;
wire [13:0] core2mem_inst_asid;
wire [31:0] core2mem_inst_addr;
wire mem2core_inst_valid;
wire core2mem_inst_lock;
wire [63:0] mem2core_inst_data;
wire [23:0] mem2core_inst_mmu_flags;
wire core2mem_data_req;
wire mem2core_data_lock;
wire [1:0] core2mem_data_order;
wire [3:0] core2mem_data_mask;
wire core2mem_data_rw; //0=Read | 1=Write
wire [13:0] core2mem_data_asid;
wire [1:0] core2mem_data_mmumod;
wire [2:0] core2mem_data_mmups;
wire [31:0] core2mem_data_pdt;
wire [31:0] core2mem_data_addr;
wire [31:0] core2mem_data_data;
wire mem2core_data_valid;
wire core2mem_data_lock;
wire [63:0] mem2core_data_data;
wire [23:0] mem2core_data_flags;
//IO
wire io2cpu_sysinfo_iosr_valid;
wire [31:0] io2cpu_sysinfo_iosr;
wire cpu2io_req;
wire io2cpu_busy;
wire [1:0] cpu2io_order;
wire cpu2io_rw;
wire [31:0] cpu2io_addr;
wire [31:0] cpu2io_data;
wire io2cpu_valid;
wire [31:0] io2cpu_data;
wire io2cpu_interrupt_valid;
wire cpu2io_interrupt_ack;
wire [5:0] io2cpu_interrupt_num;
//DPS
wire pic2dps_req;
wire dps2pic_busy;
wire pic2dps_rw;
wire [31:0] pic2dps_addr;
wire [31:0] pic2dps_data;
wire dps2pic_req;
wire [31:0] dps2pic_data;
wire dps2pic_irq_valid;
wire [5:0] dps2pic_irq_num;
wire pic2dps_irq_ack;
//Memory Port
wire processor2memory_req;
wire memory2processor_lock;
wire [1:0] processor2memory_order;
wire [3:0] processor2memory_mask;
wire processor2memory_rw;
wire [31:0] processor2memory_addr;
wire [31:0] processor2memory_data;
wire memory2processor_req;
wire processor2memory_busy;
wire [63:0] memory2processor_data;
wire mmu_lock = memory2processor_lock;
wire debuger2processor_cmd_req;
wire processor2debuger_cmd_busy;
wire [3:0] debuger2processor_cmd_command;
wire [7:0] debuger2processor_cmd_target;
wire [31:0] debuger2processor_cmd_data;
wire processor2debuger_cmd_valid;
wire processor2debuger_cmd_error;
wire [31:0] processor2debuger_cmd_data;
reg b_io_write_ack;
/********************************************************************************
Memory Out
********************************************************************************/
//Processor -> Memory
assign oMEMORY_REQ = processor2memory_req;
assign oMEMORY_ORDER = processor2memory_order;
assign oMEMORY_MASK = processor2memory_mask;
assign oMEMORY_RW = processor2memory_rw;
assign oMEMORY_ADDR = processor2memory_addr;
assign oMEMORY_DATA = processor2memory_data;
assign oMEMORY_BUSY = processor2memory_busy;
//Memory -> Processor
assign memory2processor_lock = iMEMORY_LOCK;
assign memory2processor_req = iMEMORY_VALID;
assign memory2processor_data = iMEMORY_DATA;
/********************************************************************************
Processor Core
********************************************************************************/
wire core2io_irq_tables_req;
wire [5:0] core2io_irq_tables_entry;
wire core2io_irq_tables_flag_mask;
wire core2io_irq_tables_flag_valid;
wire [1:0] core2io_irq_tables_flag_level;
assign oIO_IRQ_CONFIG_TABLE_REQ = core2io_irq_tables_req;
assign oIO_IRQ_CONFIG_TABLE_ENTRY = core2io_irq_tables_entry;
assign oIO_IRQ_CONFIG_TABLE_FLAG_MASK = core2io_irq_tables_flag_mask;
assign oIO_IRQ_CONFIG_TABLE_FLAG_VALID = core2io_irq_tables_flag_valid;
assign oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL = core2io_irq_tables_flag_level;
core #(32'h0) CORE(
/****************************************
System
****************************************/
.iCLOCK(iCORE_CLOCK),
.inRESET(inRESET),
/****************************************
System
****************************************/
.oFREE_TLB_FLUSH(free_tlb_flush),
/****************************************
GCI Controll
****************************************/
//Interrupt Control
.oIO_IRQ_CONFIG_TABLE_REQ(core2io_irq_tables_req),
.oIO_IRQ_CONFIG_TABLE_ENTRY(core2io_irq_tables_entry),
.oIO_IRQ_CONFIG_TABLE_FLAG_MASK(core2io_irq_tables_flag_mask),
.oIO_IRQ_CONFIG_TABLE_FLAG_VALID(core2io_irq_tables_flag_valid),
.oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL(core2io_irq_tables_flag_level),
/****************************************
Instruction Memory
****************************************/
//Req
.oINST_REQ(core2mem_inst_req),
.iINST_LOCK(mem2core_inst_lock),
.oINST_MMUMOD(core2mem_inst_mmumod),
.oINST_MMUPS(core2mem_inst_mmups),
.oINST_PDT(core2mem_inst_pdt),
.oINST_ASID(core2mem_inst_asid),
.oINST_ADDR(core2mem_inst_addr),
//Data RAM -> This
.iINST_VALID(mem2core_inst_valid),
.oINST_BUSY(core2mem_inst_lock),
.iINST_DATA(mem2core_inst_data),
.iINST_MMU_FLAGS(mem2core_inst_mmu_flags),
/****************************************
Data Memory
****************************************/
//Req
.oDATA_REQ(core2mem_data_req),
.iDATA_LOCK(mem2core_data_lock),
.oDATA_ORDER(core2mem_data_order), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oDATA_MASK(core2mem_data_mask),
.oDATA_RW(core2mem_data_rw), //1=Write 0=Read
.oDATA_ASID(core2mem_data_asid),
.oDATA_MMUMOD(core2mem_data_mmumod),
.oDATA_MMUPS(core2mem_data_mmups),
.oDATA_PDT(core2mem_data_pdt),
.oDATA_ADDR(core2mem_data_addr),
//This -> Data RAM
.oDATA_DATA(core2mem_data_data),
//Data RAM -> This
.iDATA_VALID(mem2core_data_valid),
.iDATA_DATA(mem2core_data_data),
.iDATA_MMU_FLAGS(mem2core_data_flags),
/****************************************
IO
****************************************/
//Req
.oIO_REQ(cpu2io_req),
.iIO_BUSY(io2cpu_busy),
.oIO_ORDER(cpu2io_order), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oIO_RW(cpu2io_rw), //0=Write 1=Read
.oIO_ADDR(cpu2io_addr),
//Write
.oIO_DATA(cpu2io_data),
//Rec
.iIO_VALID(io2cpu_valid || b_io_write_ack),
.iIO_DATA(io2cpu_data),
/****************************************
Interrupt
****************************************/
.iINTERRUPT_VALID(io2cpu_interrupt_valid),
.oINTERRUPT_ACK(cpu2io_interrupt_ack),
.iINTERRUPT_NUM(io2cpu_interrupt_num),
/****************************************
System Infomation
****************************************/
.iSYSINFO_IOSR_VALID(io2cpu_sysinfo_iosr_valid),
.iSYSINFO_IOSR(io2cpu_sysinfo_iosr),
.oDEBUG_PC(oDEBUG_PC),
/****************************************
Debug
****************************************/
.iDEBUG_CMD_REQ(debuger2processor_cmd_req),
.oDEBUG_CMD_BUSY(processor2debuger_cmd_busy),
.iDEBUG_CMD_COMMAND(debuger2processor_cmd_command),
.iDEBUG_CMD_TARGET(debuger2processor_cmd_target),
.iDEBUG_CMD_DATA(debuger2processor_cmd_data),
.oDEBUG_CMD_VALID(processor2debuger_cmd_valid),
.oDEBUG_CMD_ERROR(processor2debuger_cmd_error),
.oDEBUG_CMD_DATA(processor2debuger_cmd_data)
);
assign oDEBUG0 = 32'h0;
sdi_debugger SDI_DEBUGGER(
//Clock
.iCLOCK(iCORE_CLOCK),
.inRESET(inRESET),
//To Core
.oDEBUG_CMD_REQ(debuger2processor_cmd_req),
.iDEBUG_CMD_BUSY(processor2debuger_cmd_busy),
.oDEBUG_CMD_COMMAND(debuger2processor_cmd_command),
.oDEBUG_CMD_TARGET(debuger2processor_cmd_target),
.oDEBUG_CMD_DATA(debuger2processor_cmd_data),
.iDEBUG_CMD_VALID(processor2debuger_cmd_valid),
.iDEBUG_CMD_ERROR(processor2debuger_cmd_error),
.iDEBUG_CMD_DATA(processor2debuger_cmd_data),
//To Uart
.iDEBUG_UART_RXD(iDEBUG_UART_RXD),
.oDEBUG_UART_TXD(oDEBUG_UART_TXD),
.iDEBUG_PARA_REQ(iDEBUG_PARA_REQ),
.oDEBUG_PARA_BUSY(oDEBUG_PARA_BUSY),
.iDEBUG_PARA_CMD(iDEBUG_PARA_CMD),
.iDEBUG_PARA_DATA(iDEBUG_PARA_DATA),
.oDEBUG_PARA_VALID(oDEBUG_PARA_VALID),
.iDEBUG_PARA_BUSY(iDEBUG_PARA_BUSY),
.oDEBUG_PARA_ERROR(oDEBUG_PARA_ERROR),
.oDEBUG_PARA_DATA(oDEBUG_PARA_DATA)
);
/********************************************************************************
Memory Interface
********************************************************************************/
//Arbiter to MMU
wire m_arbiter2mmu_req;
wire mmu2m_arbiter_lock;
wire m_arbiter2mmu_data_store_ack;
wire [1:0] m_arbiter2mmu_mmu_mode;
wire [2:0] m_arbiter2mmu_mmu_ps;
wire [31:0] m_arbiter2mmu_pdt;
wire [13:0] m_arbiter2mmu_asid;
wire [1:0] m_arbiter2mmu_order;
wire [3:0] m_arbiter2mmu_mask;
wire m_arbiter2mmu_rw;
wire [31:0] m_arbiter2mmu_addr;
wire [31:0] m_arbiter2mmu_data;
wire mmu2m_arbiter_req;
wire m_arbiter2mmu_lock;
wire mmu2m_arbiter_store_ack;
wire [63:0] mmu2m_arbiter_data;
wire [23:0] mmu2m_arbiter_mmu_flags;
//Memory Pipe Arbiter
memory_pipe_arbiter MEM_ARBITER(
.iCLOCK(iBUS_CLOCK),
.inRESET(inRESET),
//Data(Core -> Memory)
.iDATA_REQ(core2mem_data_req),
.oDATA_LOCK(mem2core_data_lock),
.iDATA_ORDER(core2mem_data_order),
.iDATA_MASK(core2mem_data_mask),
.iDATA_RW(core2mem_data_rw),
.iDATA_ASID(core2mem_data_asid),
.iDATA_MMUMOD(core2mem_data_mmumod),
.iDATA_MMUPS(core2mem_data_mmups),
.iDATA_PDT(core2mem_data_pdt),
.iDATA_ADDR(core2mem_data_addr),
.iDATA_DATA(core2mem_data_data),
//Data(Memory -> Core)
.oDATA_REQ(mem2core_data_valid),
.iDATA_BUSY(1'b0),
.oDATA_DATA(mem2core_data_data),
.oDATA_MMU_FLAGS(mem2core_data_flags),
//Inst(Core -> Memory)
.iINST_REQ(core2mem_inst_req),
.oINST_LOCK(mem2core_inst_lock),
.iINST_MMUMOD(core2mem_inst_mmumod),
.iINST_MMUPS(core2mem_inst_mmups),
.iINST_PDT(core2mem_inst_pdt),
.iINST_ASID(core2mem_inst_asid),
.iINST_ADDR(core2mem_inst_addr),
//Inst(Memory -> Core)
.oINST_REQ(mem2core_inst_valid),
.iINST_BUSY(core2mem_inst_lock),
.oINST_DATA(mem2core_inst_data),
.oINST_MMU_FLAGS(mem2core_inst_mmu_flags),
//Memory(OutPort)
.oMEMORY_REQ(m_arbiter2mmu_req),
.iMEMORY_LOCK(mmu2m_arbiter_lock),
.oMEMORY_DATA_STORE_ACK(m_arbiter2mmu_data_store_ack),
.oMEMORY_MMU_MODE(m_arbiter2mmu_mmu_mode),
.oMEMORY_MMU_PS(m_arbiter2mmu_mmu_ps),
.oMEMORY_PDT(m_arbiter2mmu_pdt),
.oMEMORY_ASID(m_arbiter2mmu_asid),
.oMEMORY_ORDER(m_arbiter2mmu_order),
.oMEMORY_MASK(m_arbiter2mmu_mask),
.oMEMORY_RW(m_arbiter2mmu_rw),
.oMEMORY_ADDR(m_arbiter2mmu_addr),
.oMEMORY_DATA(m_arbiter2mmu_data),
//Memory(InPort)
.iMEMORY_VALID(mmu2m_arbiter_req),
.oMEMORY_BUSY(m_arbiter2mmu_lock),
.iMEMORY_STORE_ACK(mmu2m_arbiter_store_ack),
.iMEMORY_DATA(mmu2m_arbiter_data),
.iMEMORY_MMU_FLAGS(mmu2m_arbiter_mmu_flags)
);
//MMU
wire [3:0] processor2endian_mask;
wire [31:0] processor2endian_data;
wire [63:0] endian2processor_data;
mmu_if MMU_IF(
.iCLOCK(iBUS_CLOCK),
.inRESET(inRESET),
.iFREE_TLB_FLUSH(free_tlb_flush),
/*************************
To Core
*************************/
//Core -> This
.iCORE_REQ(m_arbiter2mmu_req),
.oCORE_LOCK(mmu2m_arbiter_lock),
.iCORE_DATA_STORE_ACK(m_arbiter2mmu_data_store_ack),
.iCORE_MMUMOD(m_arbiter2mmu_mmu_mode), //0=NoConvertion 1=none 2=1LevelConvertion 3=2LevelConvertion
.iCORE_MMUPS(m_arbiter2mmu_mmu_ps),
.iCORE_PDT(m_arbiter2mmu_pdt), //Page Table Register
.iCORE_ASID(m_arbiter2mmu_asid),
.iCORE_ORDER(m_arbiter2mmu_order),
.iCORE_MASK(m_arbiter2mmu_mask),
.iCORE_RW(m_arbiter2mmu_rw),
.iCORE_ADDR(m_arbiter2mmu_addr),
.iCORE_DATA(m_arbiter2mmu_data),
//This -> Core
.oCORE_REQ(mmu2m_arbiter_req),
.iCORE_LOCK(m_arbiter2mmu_lock),
.oCORE_STORE_ACK(mmu2m_arbiter_store_ack),
.oCORE_DATA(mmu2m_arbiter_data),
.oCORE_MMU_FLAGS(mmu2m_arbiter_mmu_flags),
/************************
To Memory
************************/
//This -> Memory
.oMEMORY_REQ(processor2memory_req),
.iMEMORY_LOCK(memory2processor_lock),
.oMEMORY_ORDER(processor2memory_order),
.oMEMORY_MASK(processor2endian_mask),
.oMEMORY_RW(processor2memory_rw),
.oMEMORY_ADDR(processor2memory_addr),
.oMEMORY_DATA(processor2endian_data),
//Memory -> This
.iMEMORY_REQ(memory2processor_req),
.oMEMORY_LOCK(processor2memory_busy),
.iMEMORY_DATA(endian2processor_data)
);
//Endian Control
endian_controller ENDIAN_TO_MEM(
//Source
.iSRC_MASK(processor2endian_mask),
.iSRC_DATA(processor2endian_data),
//Destnation
.oDEST_MASK(processor2memory_mask),
.oDEST_DATA(processor2memory_data)
);
endian_controller ENDIAN_TO_CPU_L(
//Source
.iSRC_MASK(4'hf),
.iSRC_DATA(memory2processor_data[31:0]),
//Destnation
.oDEST_MASK(),
.oDEST_DATA(endian2processor_data[31:0])
);
endian_controller ENDIAN_TO_CPU_H(
//Source
.iSRC_MASK(4'hf),
.iSRC_DATA(memory2processor_data[63:32]),
//Destnation
.oDEST_MASK(),
.oDEST_DATA(endian2processor_data[63:32])
);
/********************************************************************************
IO Interface
********************************************************************************/
//Peripheral Interface Controller
pic PIC( //peripheral_interface_controller
/****************************************
System
****************************************/
.iCLOCK(iBUS_CLOCK),
.inRESET(inRESET),
/****************************************
System Infomation
****************************************/
.oSYSINFO_IOSR_VALID(io2cpu_sysinfo_iosr_valid),
.oSYSINFO_IOSR(io2cpu_sysinfo_iosr), //IO Start Address
/****************************************
IO - CPU Connection
****************************************/
//Req
.iIO_REQ(cpu2io_req),
.oIO_BUSY(io2cpu_busy),
.iIO_ORDER(cpu2io_order), //if (!iIO_RW && iIO_ORDER!=2'h2) then Alignment Fault
.iIO_RW(cpu2io_rw), //0=Write 1=Read
.iIO_ADDR(cpu2io_addr),
.iIO_DATA(cpu2io_data),
//Output
.oIO_VALID(io2cpu_valid),
.iIO_BUSY(1'b0),
.oIO_DATA(io2cpu_data),
//Interrupt
.oIO_INTERRUPT_VALID(io2cpu_interrupt_valid),
.iIO_INTERRUPT_ACK(cpu2io_interrupt_ack),
.oIO_INTERRUPT_NUM(io2cpu_interrupt_num),
/****************************************
To DPS Connection (Not Use)
****************************************/
//Request
.oDPS_REQ(pic2dps_req), //Input
.iDPS_BUSY(dps2pic_busy),
.oDPS_RW(pic2dps_rw), //0=Read : 1=Write
.oDPS_ADDR(pic2dps_addr),
.oDPS_DATA(pic2dps_data),
//Return
.iDPS_REQ(dps2pic_req),
.oDPS_BUSY(),
.iDPS_DATA(dps2pic_data),
//Interrupt
.iDPS_IRQ_REQ(dps2pic_irq_valid),
.iDPS_IRQ_NUM(dps2pic_irq_num),
.oDPS_IRQ_ACK(pic2dps_irq_ack),
/****************************************
To GCI Connection
****************************************/
//Request
.oGCI_REQ(oGCI_REQ),
.iGCI_BUSY(iGCI_BUSY),
.oGCI_RW(oGCI_RW), //0=Read : 1=Write
.oGCI_ADDR(oGCI_ADDR),
.oGCI_DATA(oGCI_DATA),
//Return
.iGCI_REQ(iGCI_REQ),
.oGCI_BUSY(oGCI_BUSY),
.iGCI_DATA(iGCI_DATA),
//Interrupt
.iGCI_IRQ_REQ(iGCI_IRQ_REQ),
.iGCI_IRQ_NUM(iGCI_IRQ_NUM),
.oGCI_IRQ_ACK(oGCI_IRQ_ACK)
);
/********************************************************************************
DPS
********************************************************************************/
wire [5:0] core2dps_irq_tables_entry_dps = core2io_irq_tables_entry - 6'd36;
dps DPS( //default_peripheral_system
.iCLOCK(iBUS_CLOCK),
.iDPS_BASE_CLOCK(iDPS_CLOCK), //49.5120MHz
.inRESET(inRESET),
/****************************************
IO
****************************************/
//IRQ Tables
.iDPS_IRQ_CONFIG_TABLE_REQ(core2io_irq_tables_req && (core2io_irq_tables_entry == 6'd36 || core2io_irq_tables_entry == 6'd37)),
.iDPS_IRQ_CONFIG_TABLE_ENTRY(core2dps_irq_tables_entry_dps[1:0]),
.iDPS_IRQ_CONFIG_TABLE_FLAG_MASK(core2io_irq_tables_flag_mask),
.iDPS_IRQ_CONFIG_TABLE_FLAG_VALID(core2io_irq_tables_flag_valid),
.iDPS_IRQ_CONFIG_TABLE_FLAG_LEVEL(core2io_irq_tables_flag_level),
//Req
.iDPS_REQ(pic2dps_req),
.oDPS_BUSY(dps2pic_busy),
.iDPS_RW(pic2dps_rw), //1:Write
.iDPS_ADDR(pic2dps_addr),
.iDPS_DATA(pic2dps_data),
//Output
.oDPS_VALID(dps2pic_req),
.oDPS_DATA(dps2pic_data),
/****************************************
Interrupt
****************************************/
.oDPS_IRQ_REQ(dps2pic_irq_valid),
.oDPS_IRQ_NUM(dps2pic_irq_num),
.iDPS_IRQ_ACK(pic2dps_irq_ack),
/****************************************
Device
****************************************/
.oSCI_TXD(oSCI_TXD),
.iSCI_RXD(iSCI_RXD)
);
/*********************************************************
Write Ack(Data Pipe)
*********************************************************/
//IO
always@(posedge iBUS_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_io_write_ack <= 1'b0;
end
else begin
case(b_io_write_ack)
1'b0:
begin
if(!io2cpu_busy && cpu2io_req && cpu2io_rw)begin
b_io_write_ack <= 1'b1;
end
end
1'b1:
begin
b_io_write_ack <= 1'b0;
end
endcase
end
end
endmodule
`default_nettype wire
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// A pulse based clock domain synchronization scheme.
// When a sEN is asserted, a pulse is eventually sent to dPulse in the
// destination clock domain.
// Close and Multiple asserts of sEN may not be seen at the destination side.
// Reset signal is not needed since it a pulse-based, rather than
// level-based protocol
// Delay is 2 dCLK cycle.
// dPulse is not registered.
module SyncPulse(
sCLK,
sRST_N,
dCLK,
sEN,
dPulse
);
// source clock ports
input sCLK ;
input sRST_N ;
input sEN ;
// destination clock ports
input dCLK ;
output dPulse ;
// Flops to hold data
reg sSyncReg;
reg dSyncReg1, dSyncReg2;
reg dSyncPulse;
assign dPulse = dSyncReg2 != dSyncPulse ;
always @(posedge sCLK or negedge sRST_N)
begin
if (sRST_N == 0)
sSyncReg <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
else
begin
if ( sEN )
begin
sSyncReg <= `BSV_ASSIGNMENT_DELAY ! sSyncReg ;
end
end // else: !if(sRST_N == 0)
end // always @ (posedge sCLK or negedge sRST_N)
always @(posedge dCLK or negedge sRST_N )
begin
if (sRST_N == 0)
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
dSyncPulse <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
end // if (sRST_N == 0)
else
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sSyncReg ;// domain crossing
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ;
dSyncPulse <= `BSV_ASSIGNMENT_DELAY dSyncReg2 ;
end // else: !if(sRST_N == 0)
end // always @ (posedge dCLK or negedge sRST_N )
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
sSyncReg = 1'b0 ;
dSyncReg1 = 1'b0 ;
dSyncReg2 = 1'b0 ;
dSyncPulse = 1'b0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // PulseSync
|
// part of NeoGS project (c) 2007-2008 NedoPC
//
// ports $00-$3f are in FPGA, $40-$ff are in CPLD
module ports(
din, // NGS z80 cpu DATA BUS inputs
dout, // NGS z80 cpu DATA BUS outputs
busin, // direction of bus: =1 - input, =0 - output
a, // NSG z80 cpu ADDRESS BUS
iorq_n,mreq_n,rd_n,wr_n, // NGS z80 cpu control signals
data_port_input, // data_port input from zxbus module (async)
data_port_output, // data_port output to zxbus module (async to zxbus, sync here)
command_port_input, // command_port input from zxbus (async)
data_bit_input, // data_bit from zxbus module (sync)
command_bit_input, // --//-- (sync)
data_bit_output, // output to zxbus module
command_bit_output,
data_bit_wr, // strobes (positive) to zxbus module, synchronous
command_bit_wr,
mode_8chans, // mode outputs for sound_main module
mode_pan4ch, //
mode_inv7b, //
mode_ramro, // mode outputs for memmap module
mode_norom,
mode_pg0, // page registers for memmap module
mode_pg1,
clksel0, // clock select (output from FPGA)
clksel1,
snd_wrtoggle, // toggle to write sound data to sound system memory
snd_datnvol, // whether it's for volume (=0) or for samples (=1)
snd_addr, // address: which channel to be written (0-7)
snd_data, // actual 8-bit data to be written
md_din, // mp3 data interface
md_start,
md_dreq,
md_halfspeed,
mc_ncs, // mp3 control interface
mc_xrst,
mc_dout,
mc_din,
mc_start,
mc_speed,
mc_rdy,
sd_ncs, // SD card interface
sd_dout,
sd_din,
sd_start,
sd_det,
sd_wp,
led, // LED control
led_toggle,
dma_din_modules, // DMA control
//
dma_select_zx,
dma_dout_zx,
//
dma_wrstb,
dma_regsel,
rst_n,
cpu_clock // Z80 CPU clock (clk_fpga on schematics)
);
localparam MPAG = 6'h00;
localparam MPAGEX = 6'h10;
localparam ZXCMD = 6'h01;
localparam ZXDATRD = 6'h02;
localparam ZXDATWR = 6'h03;
localparam ZXSTAT = 6'h04;
localparam CLRCBIT = 6'h05;
localparam VOL1 = 6'h06;
localparam VOL2 = 6'h07;
localparam VOL3 = 6'h08;
localparam VOL4 = 6'h09;
localparam VOL5 = 6'h16;
localparam VOL6 = 6'h17;
localparam VOL7 = 6'h18;
localparam VOL8 = 6'h19;
localparam DAMNPORT1 = 6'h0a;
localparam DAMNPORT2 = 6'h0b;
localparam LEDCTR = 6'h01;
localparam GSCFG0 = 6'h0f;
localparam SCTRL = 6'h11;
localparam SSTAT = 6'h12;
localparam SD_SEND = 6'h13;
localparam SD_READ = 6'h13;
localparam SD_RSTR = 6'h14;
localparam MD_SEND = 6'h14; // same as SD_RSTR!!!
localparam MC_SEND = 6'h15;
localparam MC_READ = 6'h15;
localparam DMA_MOD = 6'h1b; // read/write
localparam DMA_HAD = 6'h1c; // LSB bits 1:0 are 00 // read/write all
localparam DMA_MAD = 6'h1d; // 01
localparam DMA_LAD = 6'h1e; // 10
localparam DMA_CST = 6'h1f; // 11
localparam DMA_PORTS = 6'h1c; // mask for _HAD, _MAD, _LAD and _CST ports, two LSBs must be zero
// FREE PORT ADDRESSES: $0C-$0E, $1A, $20-$3F
// inputs/outputs description
input [7:0] din;
output reg [7:0] dout;
output reg busin; // =1 - dbus ins, =0 - dbus outs
input [15:0] a;
input iorq_n,mreq_n,rd_n,wr_n;
input [7:0] data_port_input;
input [7:0] command_port_input;
output reg [7:0] data_port_output;
input data_bit_input;
input command_bit_input;
output reg data_bit_output;
output reg command_bit_output;
output reg data_bit_wr;
output reg command_bit_wr;
output reg mode_inv7b,
mode_8chans,
mode_pan4ch;
output reg mode_ramro;
output reg mode_norom;
output reg [6:0] mode_pg0;
output reg [6:0] mode_pg1;
output reg clksel0;
output reg clksel1;
output reg snd_wrtoggle;
output reg snd_datnvol;
output reg [2:0] snd_addr;
output reg [7:0] snd_data;
input rst_n;
input cpu_clock;
// SPI interfaces related
// MP3 data interface
output [7:0] md_din; // data to MP3 data SPI interface
output md_start; // start toggle for mp3 data spi
input md_dreq; // data request from mp3 decoder
output reg md_halfspeed;
// MP3 control interface
output reg mc_ncs; // nCS signal
output reg mc_xrst; // xRESET signal
output mc_start; // start toggle
output reg [1:0] mc_speed;
input mc_rdy;
output [7:0] mc_din; // data to send
input [7:0] mc_dout; // received data
// SDcard interface
output reg sd_ncs;
output sd_start;
output [7:0] sd_din;
input [7:0] sd_dout;
input sd_det;
input sd_wp;
// DMA modules control
//
output reg [7:0] dma_din_modules;
//
input [7:0] dma_dout_zx;
output reg dma_select_zx;
//
output reg dma_wrstb;
output reg [1:0] dma_regsel;
// LED control register
output reg led;
input led_toggle;
// internal regs & wires
reg mode_expag; // extended paging mode register
reg port09_bit5;
wire port_enabled; // =1 when port address is in enabled region ($00-$3f)
wire mem_enabled; // =1 when memory mapped sound regs are addressed ($6000-$7FFF)
reg volports_enabled; // when volume ports are addressed (6-9 and $16-$19)
reg iowrn_reg; // registered io write signal (all positive edge!)
reg iordn_reg; // --//--
reg merdn_reg; // --//--
reg port_wr; // synchronous positive write pulse (write from z80 to fpga regs)
reg port_rd; // synchronous positive read pulse (read done from fpga regs to z80)
reg memreg_rd; // when memory-mapped sound regs are read
wire port00_wr; // specific write and read strobes (1 clock cycle long positive)
wire p_ledctr_wr;
wire port02_rd;
wire port03_wr;
wire port05_wrrd;
wire port09_wr;
wire port0a_wrrd;
wire port0b_wrrd;
wire port0f_wr;
wire port10_wr;
// wire p_sstat_rd;
// wire p_sctrl_rd;
wire p_sctrl_wr;
wire p_sdsnd_wr;
// wire p_sdrd_rd;
wire p_sdrst_rd;
wire p_mdsnd_wr;
wire p_mcsnd_wr;
// wire p_mcrd_rd;
wire p_dmamod_wr;
wire p_dmaports_wr;
reg [2:0] volnum; // volume register number from port address
reg [2:0] dma_module_select; // which dma module selected: zero - none selected
localparam DMA_NONE_SELECTED = 3'd0;
localparam DMA_MODULE_ZX = 3'd1;
// localparam DMA_MODULE_... = 3'd2;
reg [7:0] dma_dout_modules; // select in data from different modules
// actual code
//enabled ports
assign port_enabled = ~(a[7] | a[6]); // $00-$3F
//enabled mem
assign mem_enabled = (~a[15]) & a[14] & a[13]; // $6000-$7FFF
// volume ports enabled
always @*
begin
if( a[5:0]==VOL1 ||
a[5:0]==VOL2 ||
a[5:0]==VOL3 ||
a[5:0]==VOL4 ||
a[5:0]==VOL5 ||
a[5:0]==VOL6 ||
a[5:0]==VOL7 ||
a[5:0]==VOL8 )
volports_enabled <= 1'b1;
else
volports_enabled <= 1'b0;
end
//when data bus outputs
always @*
begin
if( port_enabled && (!iorq_n) && (!rd_n) )
busin <= 1'b0; // bus outputs
else
busin <= 1'b1; // bus inputs
end
// rd/wr/iorq syncing in and pulses
always @(posedge cpu_clock)
begin
iowrn_reg <= iorq_n | wr_n;
iordn_reg <= iorq_n | rd_n;
if( port_enabled && (!iorq_n) && (!wr_n) && iowrn_reg )
port_wr <= 1'b1;
else
port_wr <= 1'b0;
if( port_enabled && (!iorq_n) && (!rd_n) && iordn_reg )
port_rd <= 1'b1;
else
port_rd <= 1'b0;
end
// mreq syncing and mem read pulse
always @(negedge cpu_clock)
begin
merdn_reg <= mreq_n | rd_n;
if( mem_enabled && (!mreq_n) && (!rd_n) && merdn_reg )
memreg_rd <= 1'b1;
else
memreg_rd <= 1'b0;
end
// specific ports strobes
assign port00_wr = ( a[5:0]==MPAG && port_wr );
assign port02_rd = ( a[5:0]==ZXDATRD && port_rd );
assign port03_wr = ( a[5:0]==ZXDATWR && port_wr );
assign port05_wrrd = ( a[5:0]==CLRCBIT && (port_wr||port_rd) );
assign port09_wr = ( a[5:0]==VOL4 && port_wr );
assign port0a_wrrd = ( a[5:0]==DAMNPORT1 && (port_wr||port_rd) );
assign port0b_wrrd = ( a[5:0]==DAMNPORT2 && (port_wr||port_rd) );
assign port0f_wr = ( a[5:0]==GSCFG0 && port_wr );
assign port10_wr = ( a[5:0]==MPAGEX && port_wr );
// assign p_sctrl_rd = ( a[5:0]==SCTRL && port_rd );
assign p_sctrl_wr = ( a[5:0]==SCTRL && port_wr );
// assign p_sstat_rd = ( a[5:0]==SSTAT && port_rd );
assign p_sdsnd_wr = ( a[5:0]==SD_SEND && port_wr );
// assign p_sdrd_rd = ( a[5:0]==SD_READ && port_rd );
assign p_sdrst_rd = ( a[5:0]==SD_RSTR && port_rd );
assign p_mdsnd_wr = ( a[5:0]==MD_SEND && port_wr );
assign p_mcsnd_wr = ( a[5:0]==MC_SEND && port_wr );
// assign p_mcrd_rd = ( a[5:0]==MC_READ && port_rd );
assign p_ledctr_wr = ( a[5:0]==LEDCTR && port_wr );
assign p_dmamod_wr = ( a[5:0]==DMA_MOD && port_wr );
assign p_dmaports_wr = ( {a[5:2],2'b00}==DMA_PORTS && port_wr );
// read from fpga to Z80
always @*
begin
case( a[5:0] )
ZXCMD: // command register
dout <= command_port_input;
ZXDATRD: // data register
dout <= data_port_input;
ZXSTAT: // status bits
dout <= { data_bit_input, 6'bXXXXXX, command_bit_input };
GSCFG0: // config register #0F
dout <= { mode_inv7b, mode_pan4ch, clksel1, clksel0, mode_expag, mode_8chans, mode_ramro, mode_norom };
SSTAT:
dout <= { 4'd0, mc_rdy, sd_wp, sd_det, md_dreq };
SCTRL:
dout <= { 2'd0, mc_speed[1], md_halfspeed, mc_speed[0], mc_xrst, mc_ncs, sd_ncs };
SD_READ:
dout <= sd_dout;
SD_RSTR:
dout <= sd_dout;
MC_READ:
dout <= mc_dout;
DMA_MOD:
dout <= { 5'd0, dma_module_select };
DMA_HAD:
dout <= dma_dout_modules;
DMA_MAD:
dout <= dma_dout_modules;
DMA_LAD:
dout <= dma_dout_modules;
DMA_CST:
dout <= dma_dout_modules;
default:
dout <= 8'bXXXXXXXX;
endcase
end
// write to $00 and $10 ports ++
always @(posedge cpu_clock)
begin
if( port00_wr==1'b1 ) // port 00
begin
if( mode_expag==1'b0 ) // normal paging
mode_pg0[6:0] <= { din[5:0], 1'b0 };
else // extended paging
mode_pg0[6:0] <= { din[5:0], din[7] };
end
if( mode_expag==1'b0 && port00_wr==1'b1 ) // port 10 (when in normal mode, part of port 00)
mode_pg1[6:0] <= { din[5:0], 1'b1 };
else if( mode_expag==1'b1 && port10_wr==1'b1 )
mode_pg1[6:0] <= { din[5:0], din[7] };
end
// port $03 write ++
always @(posedge cpu_clock)
begin
if( port03_wr==1'b1 )
data_port_output <= din;
end
// port $09 bit tracing
always @(posedge cpu_clock)
begin
if( port09_wr==1'b1 )
port09_bit5 <= din[5];
end
// write and reset of port $0F ++
always @(posedge cpu_clock,negedge rst_n)
begin
if( rst_n==1'b0 ) // reset!
{ mode_inv7b, mode_pan4ch, clksel1, clksel0, mode_expag, mode_8chans, mode_ramro, mode_norom } <= 8'b00110000;
else // write to port
begin
if( port0f_wr == 1'b1 )
begin
{ mode_inv7b, mode_pan4ch, clksel1, clksel0, mode_expag, mode_8chans, mode_ramro, mode_norom } <= din[7:0];
end
end
end
// data bit handling
always @*
begin
case( {port02_rd,port03_wr,port0a_wrrd} )
3'b100:
begin
data_bit_output <= 1'b0;
data_bit_wr <= 1'b1;
end
3'b010:
begin
data_bit_output <= 1'b1; // ++
data_bit_wr <= 1'b1;
end
3'b001:
begin
data_bit_output <= ~mode_pg0[0];
data_bit_wr <= 1'b1;
end
default:
begin
data_bit_output <= 1'bX;
data_bit_wr <= 1'b0;
end
endcase
end
// command bit handling
always @*
begin
casex( {port05_wrrd,port0b_wrrd} )
2'b10:
begin
command_bit_output <= 1'b0;
command_bit_wr <= 1'b1;
end
2'b01:
begin
command_bit_output <= port09_bit5;
command_bit_wr <= 1'b1;
end
default:
begin
command_bit_output <= 1'bX;
command_bit_wr <= 1'b0;
end
endcase
end
// handle data going to sound module (volume and samples values)
always @*
begin
case( a[5:0] ) // port addresses to volume register numbers
VOL1:
volnum <= 3'd0;
VOL2:
volnum <= 3'd1;
VOL3:
volnum <= 3'd2;
VOL4:
volnum <= 3'd3;
VOL5:
volnum <= 3'd4;
VOL6:
volnum <= 3'd5;
VOL7:
volnum <= 3'd6;
VOL8:
volnum <= 3'd7;
default:
volnum <= 3'bXXX;
endcase
end
// handling itself (sending data to sound module)
always @(posedge cpu_clock)
begin
if( memreg_rd ) // memory read - sample data write
begin
snd_wrtoggle <= ~snd_wrtoggle;
snd_datnvol <= 1'b1; // sample data
if( !mode_8chans ) // 4 channel mode
snd_addr <= { 1'b0, a[9:8] };
else // 8 channel mode
snd_addr <= a[10:8];
snd_data <= din;
end
else if( volports_enabled && port_wr )
begin
snd_wrtoggle <= ~snd_wrtoggle;
snd_datnvol <= 1'b0; // volume data
snd_addr <= volnum;
snd_data <= din;
end
end
//SPI (mp3, SD) interfaces
assign sd_din = (a[5:0]==SD_RSTR) ? 8'hFF : din;
assign mc_din = din;
assign md_din = din;
assign sd_start = p_sdsnd_wr | p_sdrst_rd;
assign mc_start = p_mcsnd_wr;
assign md_start = p_mdsnd_wr;
always @(posedge cpu_clock, negedge rst_n)
begin
if( !rst_n ) // async reset
begin
md_halfspeed <= 1'b0;
mc_speed <= 2'b01;
mc_xrst <= 1'b0;
mc_ncs <= 1'b1;
sd_ncs <= 1'b1;
end
else // clock
begin
if( p_sctrl_wr )
begin
if( din[0] )
sd_ncs <= din[7];
if( din[1] )
mc_ncs <= din[7];
if( din[2] )
mc_xrst <= din[7];
if( din[3] )
mc_speed[0] <= din[7];
if( din[4] )
md_halfspeed <= din[7];
if( din[5] )
mc_speed[1] <= din[7];
end
end
end
// LED control
always @(posedge cpu_clock, negedge rst_n)
begin
if( !rst_n )
led <= 1'b0;
else
begin
if( p_ledctr_wr )
led <= din[0];
else if( led_toggle )
led <= ~led;
end
end
// DMA control
//
always @(posedge cpu_clock, negedge rst_n) // selection of modules
begin
if( !rst_n )
dma_module_select <= DMA_NONE_SELECTED;
else if( p_dmamod_wr )
dma_module_select <= din[2:0];
end
//
always @* dma_din_modules = din; // translate Z80 bus out to all DMA modules
//
always @* // select modules by individual signals
begin
dma_select_zx = 1'b0;
//dma_select_... = 1'b0;
case( dma_module_select )
DMA_MODULE_ZX:
dma_select_zx = 1'b1;
//DMA_MODULE_...:
// dma_select_... = 1'b1;
endcase
end
//
always @* dma_wrstb = p_dmaports_wr; // translate dma write strobe
//
always @* dma_regsel = a[1:0];
//
always @* // route data from modules to the common module bus
begin
case( dma_regsel )
DMA_MODULE_ZX:
dma_dout_modules <= dma_dout_zx;
//DMA_MODULE_...:
// dma_dout_modules <= dma_dout_...;
default:
dma_dout_modules <= 8'bxxxxxxxx;
endcase
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cmp_mem.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module cmp_mem (/*AUTOARG*/);
integer handle;
reg [29:0] data;
reg [1023:0] file;
integer suc;
task fail;
input [1023:0] comment;
begin
$display("%d : Simulation -> FAIL(%0s)", $time, comment);
`TOP_MOD.fail_flag = 1'b1;
$finish;
end
endtask // fail
task check_counter;
begin
`ifdef RTL_SCTAG
if(`SCPATH0.mbctl.mb_count_c4 != 0)begin
$display("Error: BANK(0) mb_count_c4 = %d",`SCPATH0.mbctl.mb_count_c4);
fail("MB counter Not zero");
end
if(`SCPATH1.mbctl.mb_count_c4 != 0)begin
$display("Error: BANK(1) mb_count_c4 = %d", `SCPATH1.mbctl.mb_count_c4);
fail("MB counter Not zero");
end
if(`SCPATH2.mbctl.mb_count_c4 != 0)begin
$display("Error: BANK(2) mb_count_c4 = %d", `SCPATH2.mbctl.mb_count_c4);
fail("MB counter Not zero");
end // if (`SCPATH2.mbctl.mb_count_c4 != 0)
if(`SCPATH3.mbctl.mb_count_c4 != 0)begin
$display("Error: BANK(3) mb_count_c4 = %d", `SCPATH3.mbctl.mb_count_c4);
fail("MB counter Not zero");
end
if(`SCPATH0.wbctl.wb_count != 0)begin
$display("Error: BANK(0) wb_count = %d",`SCPATH0.wbctl.wb_count);
fail("WB counter Not zero");
end
if(`SCPATH1.wbctl.wb_count != 0)begin
$display("Error: BANK(1) wb_count = %d", `SCPATH1.wbctl.wb_count);
fail("WB counter Not zero");
end
if(`SCPATH2.wbctl.wb_count != 0)begin
$display("Error: BANK(2) wb_count = %d", `SCPATH2.wbctl.wb_count);
fail("WB counter Not zero");
end // if (`SCPATH2.mbctl.mb_count_c4 != 0)
if(`SCPATH3.wbctl.wb_count != 0)begin
$display("Error: BANK(3) wb_count = %d", `SCPATH3.wbctl.wb_count);
fail("WB counter Not zero");
end
if(`SCPATH0.fbctl.fb_count != 0)begin
$display("Error: BANK(0) fb_count = %d",`SCPATH0.fbctl.fb_count);
fail("FB counter Not zero");
end
if(`SCPATH1.fbctl.fb_count != 0)begin
$display("Error: BANK(1) fb_count = %d", `SCPATH1.fbctl.fb_count);
fail("FB counter Not zero");
end
if(`SCPATH2.fbctl.fb_count != 0)begin
$display("Error: BANK(2) fb_count = %d", `SCPATH2.fbctl.fb_count);
fail("FB counter Not zero");
end // if (`SCPATH2.mbctl.mb_count_c4 != 0)
if(`SCPATH3.fbctl.fb_count != 0)begin
$display("Error: BANK(3) fb_count = %d", `SCPATH3.fbctl.fb_count);
fail("FB counter Not zero");
end
`endif // ifdef SCTAG
end
endtask // check_counter
////////////////////////////////////////
// Create & Initialize the DIMM Modules
reg [31:0] dimm_config;
reg [6:0] mem_dat_load_config;
initial begin
`ifdef RTL_SPARC0
file = "mem.image";
`else
if ($test$plusargs("RANK_DIMM"))
mem_dat_load_config[0] = 1;
else
mem_dat_load_config[0] = 0;
if ($test$plusargs("STACK_DIMM"))
mem_dat_load_config[1] = 1;
else
mem_dat_load_config[1] = 0;
if ($test$plusargs("DIMM_SIZE_256"))
mem_dat_load_config[2] = 1;
else
mem_dat_load_config[2] = 0;
if ($test$plusargs("DIMM_SIZE_512"))
mem_dat_load_config[3] = 1;
else
mem_dat_load_config[3] = 0;
if ($test$plusargs("DIMM_SIZE_1G"))
mem_dat_load_config[4] = 1;
else
mem_dat_load_config[4] = 0;
if ($test$plusargs("DIMM_SIZE_2G"))
mem_dat_load_config[5] = 1;
else
mem_dat_load_config[5] = 0;
if ($test$plusargs("MEM_PARTIAL"))
mem_dat_load_config[6] = 1;
else
mem_dat_load_config[6] = 0;
//$display("\n%d: Info->Mem_dat_load_config in cmp_mem : %0x\n", $time, mem_dat_load_config);
case(mem_dat_load_config)
7'b0000001 : file = "mem1.data";
7'b0000010 : file = "mem1.data";
7'b0000011 : file = "mem2.data";
7'b1000001 : file = "mem1_partial.data";
7'b1000010 : file = "mem1_partial.data";
7'b0000011 : file = "mem2_partial.data";
7'b0000101 : file = "mem1_256Mb.data";
7'b0000110 : file = "mem1_256Mb.data";
7'b0000111 : file = "mem2_256Mb.data";
7'b0001001 : file = "mem1_512Mb.data";
7'b0001010 : file = "mem1_512Mb.data";
7'b0001011 : file = "mem2_512Mb.data";
7'b0010001 : file = "mem1_1G.data";
7'b0010010 : file = "mem1_1G.data";
7'b0010011 : file = "mem2_1G.data";
7'b0100001 : file = "mem1.data";
7'b0100010 : file = "mem1.data";
7'b0100011 : file = "mem2.data";
default : file = "mem.data";
endcase
`endif
`ifdef DENALI_ON
`ifdef DRAM_SAT
`else
// Load only at cmp and above levels
//rekesh will add the config for denali.
dimm_config = 32'h0;
file = "mem.image";
$init_dram(file, dimm_config);
`endif // DRAM_SAT
`else
dimm_config = 32'h0;
if ($test$plusargs("2CHANNEL_01")) dimm_config = dimm_config | 32'h10; // 2ch_01 bit 4
else if ($test$plusargs("2CHANNEL_23")) dimm_config = dimm_config | 32'h20; // 2ch_23 bit 5
else if ($test$plusargs("2CHANNEL_03")) dimm_config = dimm_config | 32'h8000; // 2ch_03 bit 31
else if ($test$plusargs("2CHANNEL_21") || $test$plusargs("2CHANNEL_12") )
dimm_config = dimm_config | 32'h4000; // 2ch_21 bit 30
`ifdef DRAM_SAT
if ($test$plusargs("DIMM_SIZE_2G")) dimm_config = dimm_config | 32'h1003;
else if ($test$plusargs("DIMM_SIZE_1G")) dimm_config = dimm_config | 32'h1002;
else if ($test$plusargs("DIMM_SIZE_512")) dimm_config = dimm_config | 32'h0001;
else if ($test$plusargs("DIMM_SIZE_256")) dimm_config = dimm_config | 32'h0000;
else dimm_config = dimm_config | 32'h1003;
if ($test$plusargs("STACK_DIMM")) dimm_config = dimm_config | 32'h40;
if ($test$plusargs("RANK_DIMM")) dimm_config = dimm_config | 32'h80;
if ($test$plusargs("LO_STACK_RANK_BIT")) dimm_config = dimm_config | 32'h100;
`else // DRAM_SAT
if ($test$plusargs("DIMM_SIZE_2G")) dimm_config = dimm_config | 32'h1005;
else if ($test$plusargs("DIMM_SIZE_1G")) dimm_config = dimm_config | 32'h1004;
else if ($test$plusargs("DIMM_SIZE_512")) dimm_config = dimm_config | 32'h0003;
else if ($test$plusargs("DIMM_SIZE_256")) dimm_config = dimm_config | 32'h0002;
else dimm_config = dimm_config | 32'h1005;
`endif // DRAM_SAT
`ifdef INFINEON
`DRAMPATH0.dimm0.U00.handle = 0;//$config_mem(40, 4);
`DRAMPATH0.dimm0.U01.handle = 1;//$config_mem(40, 4);
`DRAMPATH0.dimm0.U02.handle = 2;//$config_mem(40, 4);
`DRAMPATH0.dimm0.U03.handle = 3;//$config_mem(40, 4);
`DRAMPATH0.dimm0.U05.handle = 4;//$config_mem(40, 4);
`DRAMPATH0.dimm0.U06.handle = 5;//$config_mem(40, 4);
`DRAMPATH0.dimm0.U07.handle = 6;//$config_mem(40, 4);
`DRAMPATH0.dimm0.U08.handle = 7;//$config_mem(40, 4);
`DRAMPATH0.dimm0.U09.handle = 8;//$config_mem(40, 4);
`DRAMPATH0.dimm0.U10.handle = 9;//$config_mem(40, 4);
`DRAMPATH0.dimm0.U11.handle = 10;//$config_mem(40, 4);
`DRAMPATH0.dimm0.U12.handle = 11;//$config_mem(40, 4);
`DRAMPATH0.dimm0.U14.handle = 12;//$config_mem(40, 4);
`DRAMPATH0.dimm0.U15.handle = 13;//$config_mem(40, 4);
`DRAMPATH0.dimm0.U16.handle = 14;//$config_mem(40, 4);
`DRAMPATH0.dimm0.U17.handle = 15;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U00.handle = 16;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U01.handle = 17;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U02.handle = 18;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U03.handle = 19;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U05.handle = 20;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U06.handle = 21;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U07.handle = 22;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U08.handle = 23;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U09.handle = 24;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U10.handle = 25;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U11.handle = 26;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U12.handle = 27;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U14.handle = 28;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U15.handle = 29;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U16.handle = 30;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U17.handle = 31;//$config_mem(40, 4);
//channel 1
`DRAMPATH1.dimm0.U00.handle = 32;//$config_mem(40, 4);
`DRAMPATH1.dimm0.U01.handle = 33;//$config_mem(40, 4);
`DRAMPATH1.dimm0.U02.handle = 34;//$config_mem(40, 4);
`DRAMPATH1.dimm0.U03.handle = 35;// $config_mem(40, 4);
`DRAMPATH1.dimm0.U05.handle = 36;//$config_mem(40, 4);
`DRAMPATH1.dimm0.U06.handle = 37;//$config_mem(40, 4);
`DRAMPATH1.dimm0.U07.handle = 38;// $config_mem(40, 4);
`DRAMPATH1.dimm0.U08.handle = 39;//$config_mem(40, 4);
`DRAMPATH1.dimm0.U09.handle = 40;//$config_mem(40, 4);
`DRAMPATH1.dimm0.U10.handle = 41;//$config_mem(40, 4);
`DRAMPATH1.dimm0.U11.handle = 42;//$config_mem(40, 4);
`DRAMPATH1.dimm0.U12.handle = 43;// $config_mem(40, 4);
`DRAMPATH1.dimm0.U14.handle = 44;//$config_mem(40, 4);
`DRAMPATH1.dimm0.U15.handle = 45;//$config_mem(40, 4);
`DRAMPATH1.dimm0.U16.handle = 46;//$config_mem(40, 4);
`DRAMPATH1.dimm0.U17.handle = 47;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U00.handle = 48;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U01.handle = 49;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U02.handle = 50;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U03.handle = 51;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U05.handle = 52;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U06.handle = 53;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U07.handle = 54;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U08.handle = 55;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U09.handle = 56;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U10.handle = 57;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U11.handle = 58;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U12.handle = 59;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U14.handle = 60;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U15.handle = 61;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U16.handle = 62;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U17.handle = 63;// $config_mem(40, 4);
//channel 2
`DRAMPATH2.dimm0.U00.handle = 64;//$config_mem(40, 4);
`DRAMPATH2.dimm0.U01.handle = 65;//$config_mem(40, 4);
`DRAMPATH2.dimm0.U02.handle = 66;// $config_mem(40, 4);
`DRAMPATH2.dimm0.U03.handle = 67;//$config_mem(40, 4);
`DRAMPATH2.dimm0.U05.handle = 68;//$config_mem(40, 4);
`DRAMPATH2.dimm0.U06.handle = 69;//$config_mem(40, 4);
`DRAMPATH2.dimm0.U07.handle = 70;//$config_mem(40, 4);
`DRAMPATH2.dimm0.U08.handle = 71;//$config_mem(40, 4);
`DRAMPATH2.dimm0.U09.handle = 72;//$config_mem(40, 4);
`DRAMPATH2.dimm0.U10.handle = 73;//$config_mem(40, 4);
`DRAMPATH2.dimm0.U11.handle = 74;//$config_mem(40, 4);
`DRAMPATH2.dimm0.U12.handle = 75;//$config_mem(40, 4);
`DRAMPATH2.dimm0.U14.handle = 76;//$config_mem(40, 4);
`DRAMPATH2.dimm0.U15.handle = 77;//$config_mem(40, 4);
`DRAMPATH2.dimm0.U16.handle = 78;//$config_mem(40, 4);
`DRAMPATH2.dimm0.U17.handle = 79;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U00.handle = 80;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U01.handle = 81;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U02.handle = 82;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U03.handle = 83;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U05.handle = 84;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U06.handle = 85;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U07.handle = 86;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U08.handle = 87;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U09.handle = 88;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U10.handle = 89;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U11.handle = 90;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U12.handle = 91;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U14.handle = 92;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U15.handle = 93;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U16.handle = 94;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U17.handle = 95;//$config_mem(40, 4);
//channel 3
`DRAMPATH3.dimm0.U00.handle = 96;//$config_mem(40, 4);
`DRAMPATH3.dimm0.U01.handle = 97;//$config_mem(40, 4);
`DRAMPATH3.dimm0.U02.handle = 98;//$config_mem(40, 4);
`DRAMPATH3.dimm0.U03.handle = 99;//$config_mem(40, 4);
`DRAMPATH3.dimm0.U05.handle = 100;//$config_mem(40, 4);
`DRAMPATH3.dimm0.U06.handle = 101;//$config_mem(40, 4);
`DRAMPATH3.dimm0.U07.handle = 102;//$config_mem(40, 4);
`DRAMPATH3.dimm0.U08.handle = 103;//$config_mem(40, 4);
`DRAMPATH3.dimm0.U09.handle = 104;//$config_mem(40, 4);
`DRAMPATH3.dimm0.U10.handle = 105;//$config_mem(40, 4);
`DRAMPATH3.dimm0.U11.handle = 106;//$config_mem(40, 4);
`DRAMPATH3.dimm0.U12.handle = 107;//$config_mem(40, 4);
`DRAMPATH3.dimm0.U14.handle = 108;//$config_mem(40, 4);
`DRAMPATH3.dimm0.U15.handle = 109;//$config_mem(40, 4);
`DRAMPATH3.dimm0.U16.handle = 110;//$config_mem(40, 4);
`DRAMPATH3.dimm0.U17.handle = 111;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U00.handle = 112;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U01.handle = 113;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U02.handle = 114;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U03.handle = 115;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U05.handle = 116;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U06.handle = 117;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U07.handle = 118;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U08.handle = 119;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U09.handle = 120;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U10.handle = 121;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U11.handle = 122;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U12.handle = 123;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U14.handle = 124;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U15.handle = 125;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U16.handle = 126;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U17.handle = 127;//$config_mem(40, 4);
//ecc
`DRAMPATH0.dimm0.U04.handle = 128;//$config_mem(40, 4);
`DRAMPATH0.dimm0.U13.handle = 129;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U04.handle = 130;//$config_mem(40, 4);
`DRAMPATH0.dimm1.U13.handle = 131;//$config_mem(40, 4);
`DRAMPATH1.dimm0.U04.handle = 132;//$config_mem(40, 4);
`DRAMPATH1.dimm0.U13.handle = 133;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U04.handle = 134;//$config_mem(40, 4);
`DRAMPATH1.dimm1.U13.handle = 135;//$config_mem(40, 4);
`DRAMPATH2.dimm0.U04.handle = 136;//$config_mem(40, 4);
`DRAMPATH2.dimm0.U13.handle = 137;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U04.handle = 138;//$config_mem(40, 4);
`DRAMPATH2.dimm1.U13.handle = 139;//$config_mem(40, 4);
`DRAMPATH3.dimm0.U04.handle = 140;//$config_mem(40, 4);
`DRAMPATH3.dimm0.U13.handle = 141;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U04.handle = 142;//$config_mem(40, 4);
`DRAMPATH3.dimm1.U13.handle = 143;//$config_mem(40, 4);
`else // INFINEON
`DRAMPATH0.dimm0.datah = 0;
`DRAMPATH0.dimm0.ecch = 128;
`DRAMPATH0.dimm1.datah = 16;
`DRAMPATH0.dimm1.ecch = 130;
`DRAMPATH1.dimm0.datah = 32;
`DRAMPATH1.dimm0.ecch = 132;
`DRAMPATH1.dimm1.datah = 48;
`DRAMPATH1.dimm1.ecch = 134;
`DRAMPATH2.dimm0.datah = 64;
`DRAMPATH2.dimm0.ecch = 136;
`DRAMPATH2.dimm1.datah = 80;
`DRAMPATH2.dimm1.ecch = 138;
`DRAMPATH3.dimm0.datah = 96;
`DRAMPATH3.dimm0.ecch = 140;
`DRAMPATH3.dimm1.datah = 112;
`DRAMPATH3.dimm1.ecch = 142;
`endif // INFINEON
`ifdef DRAM_SAT
`ifdef STACK_DIMM
//stack dimm
`DRAMPATH0.dimms0.U00.handle = 0+144;//`DRAMPATH0.dimm0.U00.handle;
`DRAMPATH0.dimms0.U01.handle = 1+144;//`DRAMPATH0.dimm0.U01.handle;
`DRAMPATH0.dimms0.U02.handle = 2+144;//`DRAMPATH0.dimm0.U02.handle;
`DRAMPATH0.dimms0.U03.handle = 3+144;//`DRAMPATH0.dimm0.U03.handle;
`DRAMPATH0.dimms0.U05.handle = 4+144;//`DRAMPATH0.dimm0.U05.handle;
`DRAMPATH0.dimms0.U06.handle = 5+144;//`DRAMPATH0.dimm0.U06.handle;
`DRAMPATH0.dimms0.U07.handle = 6+144;//`DRAMPATH0.dimm0.U07.handle;
`DRAMPATH0.dimms0.U08.handle = 7+144;//`DRAMPATH0.dimm0.U08.handle;
`DRAMPATH0.dimms0.U09.handle = 8+144;//`DRAMPATH0.dimm0.U09.handle;
`DRAMPATH0.dimms0.U10.handle = 9+144;//`DRAMPATH0.dimm0.U10.handle;
`DRAMPATH0.dimms0.U11.handle = 10+144;//`DRAMPATH0.dimm0.U11.handle;
`DRAMPATH0.dimms0.U12.handle = 11+144;//`DRAMPATH0.dimm0.U12.handle;
`DRAMPATH0.dimms0.U14.handle = 12+144;//`DRAMPATH0.dimm0.U14.handle;
`DRAMPATH0.dimms0.U15.handle = 13+144;//`DRAMPATH0.dimm0.U15.handle;
`DRAMPATH0.dimms0.U16.handle = 14+144;//`DRAMPATH0.dimm0.U16.handle;
`DRAMPATH0.dimms0.U17.handle = 15+144;//`DRAMPATH0.dimm0.U17.handle;
`DRAMPATH0.dimms1.U00.handle = 16+144;//`DRAMPATH0.dimm1.U00.handle;
`DRAMPATH0.dimms1.U01.handle = 17+144;//`DRAMPATH0.dimm1.U01.handle;
`DRAMPATH0.dimms1.U02.handle = 18+144;//`DRAMPATH0.dimm1.U02.handle;
`DRAMPATH0.dimms1.U03.handle = 19+144;//`DRAMPATH0.dimm1.U03.handle;
`DRAMPATH0.dimms1.U05.handle = 20+144;//`DRAMPATH0.dimm1.U05.handle;
`DRAMPATH0.dimms1.U06.handle = 21+144;//`DRAMPATH0.dimm1.U06.handle;
`DRAMPATH0.dimms1.U07.handle = 22+144;//`DRAMPATH0.dimm1.U07.handle;
`DRAMPATH0.dimms1.U08.handle = 23+144;//`DRAMPATH0.dimm1.U08.handle;
`DRAMPATH0.dimms1.U09.handle = 24+144;//`DRAMPATH0.dimm1.U09.handle;
`DRAMPATH0.dimms1.U10.handle = 25+144;//`DRAMPATH0.dimm1.U10.handle;
`DRAMPATH0.dimms1.U11.handle = 26+144;//`DRAMPATH0.dimm1.U11.handle;
`DRAMPATH0.dimms1.U12.handle = 27+144;//`DRAMPATH0.dimm1.U12.handle;
`DRAMPATH0.dimms1.U14.handle = 28+144;//`DRAMPATH0.dimm1.U14.handle;
`DRAMPATH0.dimms1.U15.handle = 29+144;//`DRAMPATH0.dimm1.U15.handle;
`DRAMPATH0.dimms1.U16.handle = 30+144;//`DRAMPATH0.dimm1.U16.handle;
`DRAMPATH0.dimms1.U17.handle = 31+144;//`DRAMPATH0.dimm1.U17.handle;
//channel 1
`DRAMPATH1.dimms0.U00.handle = 32+144;//`DRAMPATH1.dimm0.U00.handle;
`DRAMPATH1.dimms0.U01.handle = 33+144;//`DRAMPATH1.dimm0.U01.handle;
`DRAMPATH1.dimms0.U02.handle = 34+144;//`DRAMPATH1.dimm0.U02.handle;
`DRAMPATH1.dimms0.U03.handle = 35+144;//`DRAMPATH1.dimm0.U03.handle;
`DRAMPATH1.dimms0.U05.handle = 36+144;//`DRAMPATH1.dimm0.U05.handle;
`DRAMPATH1.dimms0.U06.handle = 37+144;//`DRAMPATH1.dimm0.U06.handle;
`DRAMPATH1.dimms0.U07.handle = 38+144;//`DRAMPATH1.dimm0.U07.handle;
`DRAMPATH1.dimms0.U08.handle = 39+144;//`DRAMPATH1.dimm0.U08.handle;
`DRAMPATH1.dimms0.U09.handle = 40+144;//`DRAMPATH1.dimm0.U09.handle;
`DRAMPATH1.dimms0.U10.handle = 41+144;//`DRAMPATH1.dimm0.U10.handle;
`DRAMPATH1.dimms0.U11.handle = 42+144;//`DRAMPATH1.dimm0.U11.handle;
`DRAMPATH1.dimms0.U12.handle = 43+144;//`DRAMPATH1.dimm0.U12.handle;
`DRAMPATH1.dimms0.U14.handle = 44+144;//`DRAMPATH1.dimm0.U14.handle;
`DRAMPATH1.dimms0.U15.handle = 45+144;//`DRAMPATH1.dimm0.U15.handle;
`DRAMPATH1.dimms0.U16.handle = 46+144;//`DRAMPATH1.dimm0.U16.handle;
`DRAMPATH1.dimms0.U17.handle = 47+144;//`DRAMPATH1.dimm0.U17.handle;
`DRAMPATH1.dimms1.U00.handle = 48+144;//`DRAMPATH1.dimm1.U00.handle;
`DRAMPATH1.dimms1.U01.handle = 49+144;//`DRAMPATH1.dimm1.U01.handle;
`DRAMPATH1.dimms1.U02.handle = 50+144;//`DRAMPATH1.dimm1.U02.handle;
`DRAMPATH1.dimms1.U03.handle = 51+144;//`DRAMPATH1.dimm1.U03.handle;
`DRAMPATH1.dimms1.U05.handle = 52+144;//`DRAMPATH1.dimm1.U05.handle;
`DRAMPATH1.dimms1.U06.handle = 53+144;//`DRAMPATH1.dimm1.U06.handle;
`DRAMPATH1.dimms1.U07.handle = 54+144;//`DRAMPATH1.dimm1.U07.handle;
`DRAMPATH1.dimms1.U08.handle = 55+144;//`DRAMPATH1.dimm1.U08.handle;
`DRAMPATH1.dimms1.U09.handle = 56+144;//`DRAMPATH1.dimm1.U09.handle;
`DRAMPATH1.dimms1.U10.handle = 57+144;//`DRAMPATH1.dimm1.U10.handle;
`DRAMPATH1.dimms1.U11.handle = 58+144;//`DRAMPATH1.dimm1.U11.handle;
`DRAMPATH1.dimms1.U12.handle = 59+144;//`DRAMPATH1.dimm1.U12.handle;
`DRAMPATH1.dimms1.U14.handle = 60+144;//`DRAMPATH1.dimm1.U14.handle;
`DRAMPATH1.dimms1.U15.handle = 61+144;//`DRAMPATH1.dimm1.U15.handle;
`DRAMPATH1.dimms1.U16.handle = 62+144;//`DRAMPATH1.dimm1.U16.handle;
`DRAMPATH1.dimms1.U17.handle = 63+144;//`DRAMPATH1.dimm1.U17.handle;
//channel 2
`DRAMPATH2.dimms0.U00.handle = 64+144;//`DRAMPATH2.dimm0.U00.handle;
`DRAMPATH2.dimms0.U01.handle = 65+144;//`DRAMPATH2.dimm0.U01.handle;
`DRAMPATH2.dimms0.U02.handle = 66+144;//`DRAMPATH2.dimm0.U02.handle;
`DRAMPATH2.dimms0.U03.handle = 67+144;//`DRAMPATH2.dimm0.U03.handle;
`DRAMPATH2.dimms0.U05.handle = 68+144;//`DRAMPATH2.dimm0.U05.handle;
`DRAMPATH2.dimms0.U06.handle = 69+144;//`DRAMPATH2.dimm0.U06.handle;
`DRAMPATH2.dimms0.U07.handle = 70+144;//`DRAMPATH2.dimm0.U07.handle;
`DRAMPATH2.dimms0.U08.handle = 71+144;//`DRAMPATH2.dimm0.U08.handle;
`DRAMPATH2.dimms0.U09.handle = 72+144;//`DRAMPATH2.dimm0.U09.handle;
`DRAMPATH2.dimms0.U10.handle = 73+144;//`DRAMPATH2.dimm0.U10.handle;
`DRAMPATH2.dimms0.U11.handle = 74+144;//`DRAMPATH2.dimm0.U11.handle;
`DRAMPATH2.dimms0.U12.handle = 75+144;//`DRAMPATH2.dimm0.U12.handle;
`DRAMPATH2.dimms0.U14.handle = 76+144;//`DRAMPATH2.dimm0.U14.handle;
`DRAMPATH2.dimms0.U15.handle = 77+144;//`DRAMPATH2.dimm0.U15.handle;
`DRAMPATH2.dimms0.U16.handle = 78+144;//`DRAMPATH2.dimm0.U16.handle;
`DRAMPATH2.dimms0.U17.handle = 79+144;//`DRAMPATH2.dimm0.U17.handle;
`DRAMPATH2.dimms1.U00.handle = 80+144;//`DRAMPATH2.dimm1.U00.handle;
`DRAMPATH2.dimms1.U01.handle = 81+144;//`DRAMPATH2.dimm1.U01.handle;
`DRAMPATH2.dimms1.U02.handle = 82+144;//`DRAMPATH2.dimm1.U02.handle;
`DRAMPATH2.dimms1.U03.handle = 83+144;//`DRAMPATH2.dimm1.U03.handle;
`DRAMPATH2.dimms1.U05.handle = 84+144;//`DRAMPATH2.dimm1.U05.handle;
`DRAMPATH2.dimms1.U06.handle = 85+144;//`DRAMPATH2.dimm1.U06.handle;
`DRAMPATH2.dimms1.U07.handle = 86+144;//`DRAMPATH2.dimm1.U07.handle;
`DRAMPATH2.dimms1.U08.handle = 87+144;//`DRAMPATH2.dimm1.U08.handle;
`DRAMPATH2.dimms1.U09.handle = 88+144;//`DRAMPATH2.dimm1.U09.handle;
`DRAMPATH2.dimms1.U10.handle = 89+144;//`DRAMPATH2.dimm1.U10.handle;
`DRAMPATH2.dimms1.U11.handle = 90+144;//`DRAMPATH2.dimm1.U11.handle;
`DRAMPATH2.dimms1.U12.handle = 91+144;//`DRAMPATH2.dimm1.U12.handle;
`DRAMPATH2.dimms1.U14.handle = 92+144;//`DRAMPATH2.dimm1.U14.handle;
`DRAMPATH2.dimms1.U15.handle = 93+144;//`DRAMPATH2.dimm1.U15.handle;
`DRAMPATH2.dimms1.U16.handle = 94+144;//`DRAMPATH2.dimm1.U16.handle;
`DRAMPATH2.dimms1.U17.handle = 95+144;//`DRAMPATH2.dimm1.U17.handle;
//channel 3
`DRAMPATH3.dimms0.U00.handle = 96+144;//`DRAMPATH3.dimm0.U00.handle;
`DRAMPATH3.dimms0.U01.handle = 97+144;//`DRAMPATH3.dimm0.U01.handle;
`DRAMPATH3.dimms0.U02.handle = 98+144;//`DRAMPATH3.dimm0.U02.handle;
`DRAMPATH3.dimms0.U03.handle = 99+144;//`DRAMPATH3.dimm0.U03.handle;
`DRAMPATH3.dimms0.U05.handle = 100+144;//`DRAMPATH3.dimm0.U05.handle;
`DRAMPATH3.dimms0.U06.handle = 101+144;//`DRAMPATH3.dimm0.U06.handle;
`DRAMPATH3.dimms0.U07.handle = 102+144;//`DRAMPATH3.dimm0.U07.handle;
`DRAMPATH3.dimms0.U08.handle = 103+144;//`DRAMPATH3.dimm0.U08.handle;
`DRAMPATH3.dimms0.U09.handle = 104+144;//`DRAMPATH3.dimm0.U09.handle;
`DRAMPATH3.dimms0.U10.handle = 105+144;//`DRAMPATH3.dimm0.U10.handle;
`DRAMPATH3.dimms0.U11.handle = 106+144;//`DRAMPATH3.dimm0.U11.handle;
`DRAMPATH3.dimms0.U12.handle = 107+144;//`DRAMPATH3.dimm0.U12.handle;
`DRAMPATH3.dimms0.U14.handle = 108+144;//`DRAMPATH3.dimm0.U14.handle;
`DRAMPATH3.dimms0.U15.handle = 109+144;//`DRAMPATH3.dimm0.U15.handle;
`DRAMPATH3.dimms0.U16.handle = 110+144;//`DRAMPATH3.dimm0.U16.handle;
`DRAMPATH3.dimms0.U17.handle = 111+144;//`DRAMPATH3.dimm0.U17.handle;
`DRAMPATH3.dimms1.U00.handle = 112+144;//`DRAMPATH3.dimm1.U00.handle;
`DRAMPATH3.dimms1.U01.handle = 113+144;//`DRAMPATH3.dimm1.U01.handle;
`DRAMPATH3.dimms1.U02.handle = 114+144;//`DRAMPATH3.dimm1.U02.handle;
`DRAMPATH3.dimms1.U03.handle = 115+144;//`DRAMPATH3.dimm1.U03.handle;
`DRAMPATH3.dimms1.U05.handle = 116+144;//`DRAMPATH3.dimm1.U05.handle;
`DRAMPATH3.dimms1.U06.handle = 117+144;//`DRAMPATH3.dimm1.U06.handle;
`DRAMPATH3.dimms1.U07.handle = 118+144;//`DRAMPATH3.dimm1.U07.handle;
`DRAMPATH3.dimms1.U08.handle = 119+144;//`DRAMPATH3.dimm1.U08.handle;
`DRAMPATH3.dimms1.U09.handle = 120+144;//`DRAMPATH3.dimm1.U09.handle;
`DRAMPATH3.dimms1.U10.handle = 121+144;//`DRAMPATH3.dimm1.U10.handle;
`DRAMPATH3.dimms1.U11.handle = 122+144;//`DRAMPATH3.dimm1.U11.handle;
`DRAMPATH3.dimms1.U12.handle = 123+144;//`DRAMPATH3.dimm1.U12.handle;
`DRAMPATH3.dimms1.U14.handle = 124+144;//`DRAMPATH3.dimm1.U14.handle;
`DRAMPATH3.dimms1.U15.handle = 125+144;//`DRAMPATH3.dimm1.U15.handle;
`DRAMPATH3.dimms1.U16.handle = 126+144;//`DRAMPATH3.dimm1.U16.handle;
`DRAMPATH3.dimms1.U17.handle = 127+144;//`DRAMPATH3.dimm1.U17.handle;
//ecc
`DRAMPATH0.dimms0.U04.handle = 128+144;//`DRAMPATH0.dimm0.U04.handle;
`DRAMPATH0.dimms0.U13.handle = 129+144;//`DRAMPATH0.dimm0.U13.handle;
`DRAMPATH0.dimms1.U04.handle = 130+144;//`DRAMPATH0.dimm1.U04.handle;
`DRAMPATH0.dimms1.U13.handle = 131+144;//`DRAMPATH0.dimm1.U13.handle;
`DRAMPATH1.dimms0.U04.handle = 132+144;//`DRAMPATH1.dimm0.U04.handle;
`DRAMPATH1.dimms0.U13.handle = 133+144;//`DRAMPATH1.dimm0.U13.handle;
`DRAMPATH1.dimms1.U04.handle = 134+144;//`DRAMPATH1.dimm1.U04.handle;
`DRAMPATH1.dimms1.U13.handle = 135+144;//`DRAMPATH1.dimm1.U13.handle;
`DRAMPATH2.dimms0.U04.handle = 136+144;//`DRAMPATH2.dimm0.U04.handle;
`DRAMPATH2.dimms0.U13.handle = 137+144;//`DRAMPATH2.dimm0.U13.handle;
`DRAMPATH2.dimms1.U04.handle = 138+144;//`DRAMPATH2.dimm1.U04.handle;
`DRAMPATH2.dimms1.U13.handle = 139+144;//`DRAMPATH2.dimm1.U13.handle;
`DRAMPATH3.dimms0.U04.handle = 140+144;//`DRAMPATH3.dimm0.U04.handle;
`DRAMPATH3.dimms0.U13.handle = 141+144;//`DRAMPATH3.dimm0.U13.handle;
`DRAMPATH3.dimms1.U04.handle = 142+144;//`DRAMPATH3.dimm1.U04.handle;
`DRAMPATH3.dimms1.U13.handle = 143+144;//`DRAMPATH3.dimm1.U13.handle;
`endif
`ifdef RANK_DIMM
//rank dimm 0 & 1
`DRAMPATH0.dimmr0.U00.handle = 0+288;//`DRAMPATH0.dimm0.U00.handle;
`DRAMPATH0.dimmr0.U01.handle = 1+288;//`DRAMPATH0.dimm0.U01.handle;
`DRAMPATH0.dimmr0.U02.handle = 2+288;//`DRAMPATH0.dimm0.U02.handle;
`DRAMPATH0.dimmr0.U03.handle = 3+288;//`DRAMPATH0.dimm0.U03.handle;
`DRAMPATH0.dimmr0.U05.handle = 4+288;//`DRAMPATH0.dimm0.U05.handle;
`DRAMPATH0.dimmr0.U06.handle = 5+288;//`DRAMPATH0.dimm0.U06.handle;
`DRAMPATH0.dimmr0.U07.handle = 6+288;//`DRAMPATH0.dimm0.U07.handle;
`DRAMPATH0.dimmr0.U08.handle = 7+288;//`DRAMPATH0.dimm0.U08.handle;
`DRAMPATH0.dimmr0.U09.handle = 8+288;//`DRAMPATH0.dimm0.U09.handle;
`DRAMPATH0.dimmr0.U10.handle = 9+288;//`DRAMPATH0.dimm0.U10.handle;
`DRAMPATH0.dimmr0.U11.handle = 10+288;//`DRAMPATH0.dimm0.U11.handle;
`DRAMPATH0.dimmr0.U12.handle = 11+288;//`DRAMPATH0.dimm0.U12.handle;
`DRAMPATH0.dimmr0.U14.handle = 12+288;//`DRAMPATH0.dimm0.U14.handle;
`DRAMPATH0.dimmr0.U15.handle = 13+288;//`DRAMPATH0.dimm0.U15.handle;
`DRAMPATH0.dimmr0.U16.handle = 14+288;//`DRAMPATH0.dimm0.U16.handle;
`DRAMPATH0.dimmr0.U17.handle = 15+288;//`DRAMPATH0.dimm0.U17.handle;
`DRAMPATH0.dimmr1.U00.handle = 16+288;//`DRAMPATH0.dimm1.U00.handle;
`DRAMPATH0.dimmr1.U01.handle = 17+288;//`DRAMPATH0.dimm1.U01.handle;
`DRAMPATH0.dimmr1.U02.handle = 18+288;//`DRAMPATH0.dimm1.U02.handle;
`DRAMPATH0.dimmr1.U03.handle = 19+288;//`DRAMPATH0.dimm1.U03.handle;
`DRAMPATH0.dimmr1.U05.handle = 20+288;//`DRAMPATH0.dimm1.U05.handle;
`DRAMPATH0.dimmr1.U06.handle = 21+288;//`DRAMPATH0.dimm1.U06.handle;
`DRAMPATH0.dimmr1.U07.handle = 22+288;//`DRAMPATH0.dimm1.U07.handle;
`DRAMPATH0.dimmr1.U08.handle = 23+288;//`DRAMPATH0.dimm1.U08.handle;
`DRAMPATH0.dimmr1.U09.handle = 24+288;//`DRAMPATH0.dimm1.U09.handle;
`DRAMPATH0.dimmr1.U10.handle = 25+288;//`DRAMPATH0.dimm1.U10.handle;
`DRAMPATH0.dimmr1.U11.handle = 26+288;//`DRAMPATH0.dimm1.U11.handle;
`DRAMPATH0.dimmr1.U12.handle = 27+288;//`DRAMPATH0.dimm1.U12.handle;
`DRAMPATH0.dimmr1.U14.handle = 28+288;//`DRAMPATH0.dimm1.U14.handle;
`DRAMPATH0.dimmr1.U15.handle = 29+288;//`DRAMPATH0.dimm1.U15.handle;
`DRAMPATH0.dimmr1.U16.handle = 30+288;//`DRAMPATH0.dimm1.U16.handle;
`DRAMPATH0.dimmr1.U17.handle = 31+288;//`DRAMPATH0.dimm1.U17.handle;
//channel 1
`DRAMPATH1.dimmr0.U00.handle = 32+288;//`DRAMPATH1.dimm0.U00.handle;
`DRAMPATH1.dimmr0.U01.handle = 33+288;//`DRAMPATH1.dimm0.U01.handle;
`DRAMPATH1.dimmr0.U02.handle = 34+288;//`DRAMPATH1.dimm0.U02.handle;
`DRAMPATH1.dimmr0.U03.handle = 35+288;//`DRAMPATH1.dimm0.U03.handle;
`DRAMPATH1.dimmr0.U05.handle = 36+288;//`DRAMPATH1.dimm0.U05.handle;
`DRAMPATH1.dimmr0.U06.handle = 37+288;//`DRAMPATH1.dimm0.U06.handle;
`DRAMPATH1.dimmr0.U07.handle = 38+288;//`DRAMPATH1.dimm0.U07.handle;
`DRAMPATH1.dimmr0.U08.handle = 39+288;//`DRAMPATH1.dimm0.U08.handle;
`DRAMPATH1.dimmr0.U09.handle = 40+288;//`DRAMPATH1.dimm0.U09.handle;
`DRAMPATH1.dimmr0.U10.handle = 41+288;//`DRAMPATH1.dimm0.U10.handle;
`DRAMPATH1.dimmr0.U11.handle = 42+288;//`DRAMPATH1.dimm0.U11.handle;
`DRAMPATH1.dimmr0.U12.handle = 43+288;//`DRAMPATH1.dimm0.U12.handle;
`DRAMPATH1.dimmr0.U14.handle = 44+288;//`DRAMPATH1.dimm0.U14.handle;
`DRAMPATH1.dimmr0.U15.handle = 45+288;//`DRAMPATH1.dimm0.U15.handle;
`DRAMPATH1.dimmr0.U16.handle = 46+288;//`DRAMPATH1.dimm0.U16.handle;
`DRAMPATH1.dimmr0.U17.handle = 47+288;//`DRAMPATH1.dimm0.U17.handle;
`DRAMPATH1.dimmr1.U00.handle = 48+288;//`DRAMPATH1.dimm1.U00.handle;
`DRAMPATH1.dimmr1.U01.handle = 49+288;//`DRAMPATH1.dimm1.U01.handle;
`DRAMPATH1.dimmr1.U02.handle = 50+288;//`DRAMPATH1.dimm1.U02.handle;
`DRAMPATH1.dimmr1.U03.handle = 51+288;//`DRAMPATH1.dimm1.U03.handle;
`DRAMPATH1.dimmr1.U05.handle = 52+288;//`DRAMPATH1.dimm1.U05.handle;
`DRAMPATH1.dimmr1.U06.handle = 53+288;//`DRAMPATH1.dimm1.U06.handle;
`DRAMPATH1.dimmr1.U07.handle = 54+288;//`DRAMPATH1.dimm1.U07.handle;
`DRAMPATH1.dimmr1.U08.handle = 55+288;//`DRAMPATH1.dimm1.U08.handle;
`DRAMPATH1.dimmr1.U09.handle = 56+288;//`DRAMPATH1.dimm1.U09.handle;
`DRAMPATH1.dimmr1.U10.handle = 57+288;//`DRAMPATH1.dimm1.U10.handle;
`DRAMPATH1.dimmr1.U11.handle = 58+288;//`DRAMPATH1.dimm1.U11.handle;
`DRAMPATH1.dimmr1.U12.handle = 59+288;//`DRAMPATH1.dimm1.U12.handle;
`DRAMPATH1.dimmr1.U14.handle = 60+288;//`DRAMPATH1.dimm1.U14.handle;
`DRAMPATH1.dimmr1.U15.handle = 61+288;//`DRAMPATH1.dimm1.U15.handle;
`DRAMPATH1.dimmr1.U16.handle = 62+288;//`DRAMPATH1.dimm1.U16.handle;
`DRAMPATH1.dimmr1.U17.handle = 63+288;//`DRAMPATH1.dimm1.U17.handle;
//channel 2
`DRAMPATH2.dimmr0.U00.handle = 64+288;//`DRAMPATH2.dimm0.U00.handle;
`DRAMPATH2.dimmr0.U01.handle = 65+288;//`DRAMPATH2.dimm0.U01.handle;
`DRAMPATH2.dimmr0.U02.handle = 66+288;//`DRAMPATH2.dimm0.U02.handle;
`DRAMPATH2.dimmr0.U03.handle = 67+288;//`DRAMPATH2.dimm0.U03.handle;
`DRAMPATH2.dimmr0.U05.handle = 68+288;//`DRAMPATH2.dimm0.U05.handle;
`DRAMPATH2.dimmr0.U06.handle = 69+288;//`DRAMPATH2.dimm0.U06.handle;
`DRAMPATH2.dimmr0.U07.handle = 70+288;//`DRAMPATH2.dimm0.U07.handle;
`DRAMPATH2.dimmr0.U08.handle = 71+288;//`DRAMPATH2.dimm0.U08.handle;
`DRAMPATH2.dimmr0.U09.handle = 72+288;//`DRAMPATH2.dimm0.U09.handle;
`DRAMPATH2.dimmr0.U10.handle = 73+288;//`DRAMPATH2.dimm0.U10.handle;
`DRAMPATH2.dimmr0.U11.handle = 74+288;//`DRAMPATH2.dimm0.U11.handle;
`DRAMPATH2.dimmr0.U12.handle = 75+288;//`DRAMPATH2.dimm0.U12.handle;
`DRAMPATH2.dimmr0.U14.handle = 76+288;//`DRAMPATH2.dimm0.U14.handle;
`DRAMPATH2.dimmr0.U15.handle = 77+288;//`DRAMPATH2.dimm0.U15.handle;
`DRAMPATH2.dimmr0.U16.handle = 78+288;//`DRAMPATH2.dimm0.U16.handle;
`DRAMPATH2.dimmr0.U17.handle = 79+288;//`DRAMPATH2.dimm0.U17.handle;
`DRAMPATH2.dimmr1.U00.handle = 80+288;//`DRAMPATH2.dimm1.U00.handle;
`DRAMPATH2.dimmr1.U01.handle = 81+288;//`DRAMPATH2.dimm1.U01.handle;
`DRAMPATH2.dimmr1.U02.handle = 82+288;//`DRAMPATH2.dimm1.U02.handle;
`DRAMPATH2.dimmr1.U03.handle = 83+288;//`DRAMPATH2.dimm1.U03.handle;
`DRAMPATH2.dimmr1.U05.handle = 84+288;//`DRAMPATH2.dimm1.U05.handle;
`DRAMPATH2.dimmr1.U06.handle = 85+288;//`DRAMPATH2.dimm1.U06.handle;
`DRAMPATH2.dimmr1.U07.handle = 86+288;//`DRAMPATH2.dimm1.U07.handle;
`DRAMPATH2.dimmr1.U08.handle = 87+288;//`DRAMPATH2.dimm1.U08.handle;
`DRAMPATH2.dimmr1.U09.handle = 88+288;//`DRAMPATH2.dimm1.U09.handle;
`DRAMPATH2.dimmr1.U10.handle = 89+288;//`DRAMPATH2.dimm1.U10.handle;
`DRAMPATH2.dimmr1.U11.handle = 90+288;//`DRAMPATH2.dimm1.U11.handle;
`DRAMPATH2.dimmr1.U12.handle = 91+288;//`DRAMPATH2.dimm1.U12.handle;
`DRAMPATH2.dimmr1.U14.handle = 92+288;//`DRAMPATH2.dimm1.U14.handle;
`DRAMPATH2.dimmr1.U15.handle = 93+288;//`DRAMPATH2.dimm1.U15.handle;
`DRAMPATH2.dimmr1.U16.handle = 94+288;//`DRAMPATH2.dimm1.U16.handle;
`DRAMPATH2.dimmr1.U17.handle = 95+288;//`DRAMPATH2.dimm1.U17.handle;
//channel 3
`DRAMPATH3.dimmr0.U00.handle = 96+288;//`DRAMPATH3.dimm0.U00.handle;
`DRAMPATH3.dimmr0.U01.handle = 97+288;//`DRAMPATH3.dimm0.U01.handle;
`DRAMPATH3.dimmr0.U02.handle = 98+288;//`DRAMPATH3.dimm0.U02.handle;
`DRAMPATH3.dimmr0.U03.handle = 99+288;//`DRAMPATH3.dimm0.U03.handle;
`DRAMPATH3.dimmr0.U05.handle = 100+288;//`DRAMPATH3.dimm0.U05.handle;
`DRAMPATH3.dimmr0.U06.handle = 101+288;//`DRAMPATH3.dimm0.U06.handle;
`DRAMPATH3.dimmr0.U07.handle = 102+288;//`DRAMPATH3.dimm0.U07.handle;
`DRAMPATH3.dimmr0.U08.handle = 103+288;//`DRAMPATH3.dimm0.U08.handle;
`DRAMPATH3.dimmr0.U09.handle = 104+288;//`DRAMPATH3.dimm0.U09.handle;
`DRAMPATH3.dimmr0.U10.handle = 105+288;//`DRAMPATH3.dimm0.U10.handle;
`DRAMPATH3.dimmr0.U11.handle = 106+288;//`DRAMPATH3.dimm0.U11.handle;
`DRAMPATH3.dimmr0.U12.handle = 107+288;//`DRAMPATH3.dimm0.U12.handle;
`DRAMPATH3.dimmr0.U14.handle = 108+288;//`DRAMPATH3.dimm0.U14.handle;
`DRAMPATH3.dimmr0.U15.handle = 109+288;//`DRAMPATH3.dimm0.U15.handle;
`DRAMPATH3.dimmr0.U16.handle = 110+288;//`DRAMPATH3.dimm0.U16.handle;
`DRAMPATH3.dimmr0.U17.handle = 111+288;//`DRAMPATH3.dimm0.U17.handle;
`DRAMPATH3.dimmr1.U00.handle = 112+288;//`DRAMPATH3.dimm1.U00.handle;
`DRAMPATH3.dimmr1.U01.handle = 113+288;//`DRAMPATH3.dimm1.U01.handle;
`DRAMPATH3.dimmr1.U02.handle = 114+288;//`DRAMPATH3.dimm1.U02.handle;
`DRAMPATH3.dimmr1.U03.handle = 115+288;//`DRAMPATH3.dimm1.U03.handle;
`DRAMPATH3.dimmr1.U05.handle = 116+288;//`DRAMPATH3.dimm1.U05.handle;
`DRAMPATH3.dimmr1.U06.handle = 117+288;//`DRAMPATH3.dimm1.U06.handle;
`DRAMPATH3.dimmr1.U07.handle = 118+288;//`DRAMPATH3.dimm1.U07.handle;
`DRAMPATH3.dimmr1.U08.handle = 119+288;//`DRAMPATH3.dimm1.U08.handle;
`DRAMPATH3.dimmr1.U09.handle = 120+288;//`DRAMPATH3.dimm1.U09.handle;
`DRAMPATH3.dimmr1.U10.handle = 121+288;//`DRAMPATH3.dimm1.U10.handle;
`DRAMPATH3.dimmr1.U11.handle = 122+288;//`DRAMPATH3.dimm1.U11.handle;
`DRAMPATH3.dimmr1.U12.handle = 123+288;//`DRAMPATH3.dimm1.U12.handle;
`DRAMPATH3.dimmr1.U14.handle = 124+288;//`DRAMPATH3.dimm1.U14.handle;
`DRAMPATH3.dimmr1.U15.handle = 125+288;//`DRAMPATH3.dimm1.U15.handle;
`DRAMPATH3.dimmr1.U16.handle = 126+288;//`DRAMPATH3.dimm1.U16.handle;
`DRAMPATH3.dimmr1.U17.handle = 127+288;//`DRAMPATH3.dimm1.U17.handle;
//ecc
`DRAMPATH0.dimmr0.U04.handle = 128+288;//`DRAMPATH0.dimm0.U04.handle;
`DRAMPATH0.dimmr0.U13.handle = 129+288;//`DRAMPATH0.dimm0.U13.handle;
`DRAMPATH0.dimmr1.U04.handle = 130+288;//`DRAMPATH0.dimm1.U04.handle;
`DRAMPATH0.dimmr1.U13.handle = 131+288;//`DRAMPATH0.dimm1.U13.handle;
`DRAMPATH1.dimmr0.U04.handle = 132+288;//`DRAMPATH1.dimm0.U04.handle;
`DRAMPATH1.dimmr0.U13.handle = 133+288;//`DRAMPATH1.dimm0.U13.handle;
`DRAMPATH1.dimmr1.U04.handle = 134+288;//`DRAMPATH1.dimm1.U04.handle;
`DRAMPATH1.dimmr1.U13.handle = 135+288;//`DRAMPATH1.dimm1.U13.handle;
`DRAMPATH2.dimmr0.U04.handle = 136+288;//`DRAMPATH2.dimm0.U04.handle;
`DRAMPATH2.dimmr0.U13.handle = 137+288;//`DRAMPATH2.dimm0.U13.handle;
`DRAMPATH2.dimmr1.U04.handle = 138+288;//`DRAMPATH2.dimm1.U04.handle;
`DRAMPATH2.dimmr1.U13.handle = 139+288;//`DRAMPATH2.dimm1.U13.handle;
`DRAMPATH3.dimmr0.U04.handle = 140+288;//`DRAMPATH3.dimm0.U04.handle;
`DRAMPATH3.dimmr0.U13.handle = 141+288;//`DRAMPATH3.dimm0.U13.handle;
`DRAMPATH3.dimmr1.U04.handle = 142+288;//`DRAMPATH3.dimm1.U04.handle;
`DRAMPATH3.dimmr1.U13.handle = 143+288;//`DRAMPATH3.dimm1.U13.handle;
`ifdef STACK_DIMM
//rank dimm 2 & 3
`DRAMPATH0.dimmr2.U00.handle = 0+432;//`DRAMPATH0.dimm0.U00.handle;
`DRAMPATH0.dimmr2.U01.handle = 1+432;//`DRAMPATH0.dimm0.U01.handle;
`DRAMPATH0.dimmr2.U02.handle = 2+432;//`DRAMPATH0.dimm0.U02.handle;
`DRAMPATH0.dimmr2.U03.handle = 3+432;//`DRAMPATH0.dimm0.U03.handle;
`DRAMPATH0.dimmr2.U05.handle = 4+432;//`DRAMPATH0.dimm0.U05.handle;
`DRAMPATH0.dimmr2.U06.handle = 5+432;//`DRAMPATH0.dimm0.U06.handle;
`DRAMPATH0.dimmr2.U07.handle = 6+432;//`DRAMPATH0.dimm0.U07.handle;
`DRAMPATH0.dimmr2.U08.handle = 7+432;//`DRAMPATH0.dimm0.U08.handle;
`DRAMPATH0.dimmr2.U09.handle = 8+432;//`DRAMPATH0.dimm0.U09.handle;
`DRAMPATH0.dimmr2.U10.handle = 9+432;//`DRAMPATH0.dimm0.U10.handle;
`DRAMPATH0.dimmr2.U11.handle = 10+432;//`DRAMPATH0.dimm0.U11.handle;
`DRAMPATH0.dimmr2.U12.handle = 11+432;//`DRAMPATH0.dimm0.U12.handle;
`DRAMPATH0.dimmr2.U14.handle = 12+432;//`DRAMPATH0.dimm0.U14.handle;
`DRAMPATH0.dimmr2.U15.handle = 13+432;//`DRAMPATH0.dimm0.U15.handle;
`DRAMPATH0.dimmr2.U16.handle = 14+432;//`DRAMPATH0.dimm0.U16.handle;
`DRAMPATH0.dimmr2.U17.handle = 15+432;//`DRAMPATH0.dimm0.U17.handle;
`DRAMPATH0.dimmr3.U00.handle = 16+432;//`DRAMPATH0.dimm1.U00.handle;
`DRAMPATH0.dimmr3.U01.handle = 17+432;//`DRAMPATH0.dimm1.U01.handle;
`DRAMPATH0.dimmr3.U02.handle = 18+432;//`DRAMPATH0.dimm1.U02.handle;
`DRAMPATH0.dimmr3.U03.handle = 19+432;//`DRAMPATH0.dimm1.U03.handle;
`DRAMPATH0.dimmr3.U05.handle = 20+432;//`DRAMPATH0.dimm1.U05.handle;
`DRAMPATH0.dimmr3.U06.handle = 21+432;//`DRAMPATH0.dimm1.U06.handle;
`DRAMPATH0.dimmr3.U07.handle = 22+432;//`DRAMPATH0.dimm1.U07.handle;
`DRAMPATH0.dimmr3.U08.handle = 23+432;//`DRAMPATH0.dimm1.U08.handle;
`DRAMPATH0.dimmr3.U09.handle = 24+432;//`DRAMPATH0.dimm1.U09.handle;
`DRAMPATH0.dimmr3.U10.handle = 25+432;//`DRAMPATH0.dimm1.U10.handle;
`DRAMPATH0.dimmr3.U11.handle = 26+432;//`DRAMPATH0.dimm1.U11.handle;
`DRAMPATH0.dimmr3.U12.handle = 27+432;//`DRAMPATH0.dimm1.U12.handle;
`DRAMPATH0.dimmr3.U14.handle = 28+432;//`DRAMPATH0.dimm1.U14.handle;
`DRAMPATH0.dimmr3.U15.handle = 29+432;//`DRAMPATH0.dimm1.U15.handle;
`DRAMPATH0.dimmr3.U16.handle = 30+432;//`DRAMPATH0.dimm1.U16.handle;
`DRAMPATH0.dimmr3.U17.handle = 31+432;//`DRAMPATH0.dimm1.U17.handle;
//channel 1
`DRAMPATH1.dimmr2.U00.handle = 32+432;//`DRAMPATH1.dimm0.U00.handle;
`DRAMPATH1.dimmr2.U01.handle = 33+432;//`DRAMPATH1.dimm0.U01.handle;
`DRAMPATH1.dimmr2.U02.handle = 34+432;//`DRAMPATH1.dimm0.U02.handle;
`DRAMPATH1.dimmr2.U03.handle = 35+432;//`DRAMPATH1.dimm0.U03.handle;
`DRAMPATH1.dimmr2.U05.handle = 36+432;//`DRAMPATH1.dimm0.U05.handle;
`DRAMPATH1.dimmr2.U06.handle = 37+432;//`DRAMPATH1.dimm0.U06.handle;
`DRAMPATH1.dimmr2.U07.handle = 38+432;//`DRAMPATH1.dimm0.U07.handle;
`DRAMPATH1.dimmr2.U08.handle = 39+432;//`DRAMPATH1.dimm0.U08.handle;
`DRAMPATH1.dimmr2.U09.handle = 40+432;//`DRAMPATH1.dimm0.U09.handle;
`DRAMPATH1.dimmr2.U10.handle = 41+432;//`DRAMPATH1.dimm0.U10.handle;
`DRAMPATH1.dimmr2.U11.handle = 42+432;//`DRAMPATH1.dimm0.U11.handle;
`DRAMPATH1.dimmr2.U12.handle = 43+432;//`DRAMPATH1.dimm0.U12.handle;
`DRAMPATH1.dimmr2.U14.handle = 44+432;//`DRAMPATH1.dimm0.U14.handle;
`DRAMPATH1.dimmr2.U15.handle = 45+432;//`DRAMPATH1.dimm0.U15.handle;
`DRAMPATH1.dimmr2.U16.handle = 46+432;//`DRAMPATH1.dimm0.U16.handle;
`DRAMPATH1.dimmr2.U17.handle = 47+432;//`DRAMPATH1.dimm0.U17.handle;
`DRAMPATH1.dimmr3.U00.handle = 48+432;//`DRAMPATH1.dimm1.U00.handle;
`DRAMPATH1.dimmr3.U01.handle = 49+432;//`DRAMPATH1.dimm1.U01.handle;
`DRAMPATH1.dimmr3.U02.handle = 50+432;//`DRAMPATH1.dimm1.U02.handle;
`DRAMPATH1.dimmr3.U03.handle = 51+432;//`DRAMPATH1.dimm1.U03.handle;
`DRAMPATH1.dimmr3.U05.handle = 52+432;//`DRAMPATH1.dimm1.U05.handle;
`DRAMPATH1.dimmr3.U06.handle = 53+432;//`DRAMPATH1.dimm1.U06.handle;
`DRAMPATH1.dimmr3.U07.handle = 54+432;//`DRAMPATH1.dimm1.U07.handle;
`DRAMPATH1.dimmr3.U08.handle = 55+432;//`DRAMPATH1.dimm1.U08.handle;
`DRAMPATH1.dimmr3.U09.handle = 56+432;//`DRAMPATH1.dimm1.U09.handle;
`DRAMPATH1.dimmr3.U10.handle = 57+432;//`DRAMPATH1.dimm1.U10.handle;
`DRAMPATH1.dimmr3.U11.handle = 58+432;//`DRAMPATH1.dimm1.U11.handle;
`DRAMPATH1.dimmr3.U12.handle = 59+432;//`DRAMPATH1.dimm1.U12.handle;
`DRAMPATH1.dimmr3.U14.handle = 60+432;//`DRAMPATH1.dimm1.U14.handle;
`DRAMPATH1.dimmr3.U15.handle = 61+432;//`DRAMPATH1.dimm1.U15.handle;
`DRAMPATH1.dimmr3.U16.handle = 62+432;//`DRAMPATH1.dimm1.U16.handle;
`DRAMPATH1.dimmr3.U17.handle = 63+432;//`DRAMPATH1.dimm1.U17.handle;
//channel 2
`DRAMPATH2.dimmr2.U00.handle = 64+432;//`DRAMPATH2.dimm0.U00.handle;
`DRAMPATH2.dimmr2.U01.handle = 65+432;//`DRAMPATH2.dimm0.U01.handle;
`DRAMPATH2.dimmr2.U02.handle = 66+432;//`DRAMPATH2.dimm0.U02.handle;
`DRAMPATH2.dimmr2.U03.handle = 67+432;//`DRAMPATH2.dimm0.U03.handle;
`DRAMPATH2.dimmr2.U05.handle = 68+432;//`DRAMPATH2.dimm0.U05.handle;
`DRAMPATH2.dimmr2.U06.handle = 69+432;//`DRAMPATH2.dimm0.U06.handle;
`DRAMPATH2.dimmr2.U07.handle = 70+432;//`DRAMPATH2.dimm0.U07.handle;
`DRAMPATH2.dimmr2.U08.handle = 71+432;//`DRAMPATH2.dimm0.U08.handle;
`DRAMPATH2.dimmr2.U09.handle = 72+432;//`DRAMPATH2.dimm0.U09.handle;
`DRAMPATH2.dimmr2.U10.handle = 73+432;//`DRAMPATH2.dimm0.U10.handle;
`DRAMPATH2.dimmr2.U11.handle = 74+432;//`DRAMPATH2.dimm0.U11.handle;
`DRAMPATH2.dimmr2.U12.handle = 75+432;//`DRAMPATH2.dimm0.U12.handle;
`DRAMPATH2.dimmr2.U14.handle = 76+432;//`DRAMPATH2.dimm0.U14.handle;
`DRAMPATH2.dimmr2.U15.handle = 77+432;//`DRAMPATH2.dimm0.U15.handle;
`DRAMPATH2.dimmr2.U16.handle = 78+432;//`DRAMPATH2.dimm0.U16.handle;
`DRAMPATH2.dimmr2.U17.handle = 79+432;//`DRAMPATH2.dimm0.U17.handle;
`DRAMPATH2.dimmr3.U00.handle = 80+432;//`DRAMPATH2.dimm1.U00.handle;
`DRAMPATH2.dimmr3.U01.handle = 81+432;//`DRAMPATH2.dimm1.U01.handle;
`DRAMPATH2.dimmr3.U02.handle = 82+432;//`DRAMPATH2.dimm1.U02.handle;
`DRAMPATH2.dimmr3.U03.handle = 83+432;//`DRAMPATH2.dimm1.U03.handle;
`DRAMPATH2.dimmr3.U05.handle = 84+432;//`DRAMPATH2.dimm1.U05.handle;
`DRAMPATH2.dimmr3.U06.handle = 85+432;//`DRAMPATH2.dimm1.U06.handle;
`DRAMPATH2.dimmr3.U07.handle = 86+432;//`DRAMPATH2.dimm1.U07.handle;
`DRAMPATH2.dimmr3.U08.handle = 87+432;//`DRAMPATH2.dimm1.U08.handle;
`DRAMPATH2.dimmr3.U09.handle = 88+432;//`DRAMPATH2.dimm1.U09.handle;
`DRAMPATH2.dimmr3.U10.handle = 89+432;//`DRAMPATH2.dimm1.U10.handle;
`DRAMPATH2.dimmr3.U11.handle = 90+432;//`DRAMPATH2.dimm1.U11.handle;
`DRAMPATH2.dimmr3.U12.handle = 91+432;//`DRAMPATH2.dimm1.U12.handle;
`DRAMPATH2.dimmr3.U14.handle = 92+432;//`DRAMPATH2.dimm1.U14.handle;
`DRAMPATH2.dimmr3.U15.handle = 93+432;//`DRAMPATH2.dimm1.U15.handle;
`DRAMPATH2.dimmr3.U16.handle = 94+432;//`DRAMPATH2.dimm1.U16.handle;
`DRAMPATH2.dimmr3.U17.handle = 95+432;//`DRAMPATH2.dimm1.U17.handle;
//channel 3
`DRAMPATH3.dimmr2.U00.handle = 96+432;//`DRAMPATH3.dimm0.U00.handle;
`DRAMPATH3.dimmr2.U01.handle = 97+432;//`DRAMPATH3.dimm0.U01.handle;
`DRAMPATH3.dimmr2.U02.handle = 98+432;//`DRAMPATH3.dimm0.U02.handle;
`DRAMPATH3.dimmr2.U03.handle = 99+432;//`DRAMPATH3.dimm0.U03.handle;
`DRAMPATH3.dimmr2.U05.handle = 100+432;//`DRAMPATH3.dimm0.U05.handle;
`DRAMPATH3.dimmr2.U06.handle = 101+432;//`DRAMPATH3.dimm0.U06.handle;
`DRAMPATH3.dimmr2.U07.handle = 102+432;//`DRAMPATH3.dimm0.U07.handle;
`DRAMPATH3.dimmr2.U08.handle = 103+432;//`DRAMPATH3.dimm0.U08.handle;
`DRAMPATH3.dimmr2.U09.handle = 104+432;//`DRAMPATH3.dimm0.U09.handle;
`DRAMPATH3.dimmr2.U10.handle = 105+432;//`DRAMPATH3.dimm0.U10.handle;
`DRAMPATH3.dimmr2.U11.handle = 106+432;//`DRAMPATH3.dimm0.U11.handle;
`DRAMPATH3.dimmr2.U12.handle = 107+432;//`DRAMPATH3.dimm0.U12.handle;
`DRAMPATH3.dimmr2.U14.handle = 108+432;//`DRAMPATH3.dimm0.U14.handle;
`DRAMPATH3.dimmr2.U15.handle = 109+432;//`DRAMPATH3.dimm0.U15.handle;
`DRAMPATH3.dimmr2.U16.handle = 110+432;//`DRAMPATH3.dimm0.U16.handle;
`DRAMPATH3.dimmr2.U17.handle = 111+432;//`DRAMPATH3.dimm0.U17.handle;
`DRAMPATH3.dimmr3.U00.handle = 112+432;//`DRAMPATH3.dimm1.U00.handle;
`DRAMPATH3.dimmr3.U01.handle = 113+432;//`DRAMPATH3.dimm1.U01.handle;
`DRAMPATH3.dimmr3.U02.handle = 114+432;//`DRAMPATH3.dimm1.U02.handle;
`DRAMPATH3.dimmr3.U03.handle = 115+432;//`DRAMPATH3.dimm1.U03.handle;
`DRAMPATH3.dimmr3.U05.handle = 116+432;//`DRAMPATH3.dimm1.U05.handle;
`DRAMPATH3.dimmr3.U06.handle = 117+432;//`DRAMPATH3.dimm1.U06.handle;
`DRAMPATH3.dimmr3.U07.handle = 118+432;//`DRAMPATH3.dimm1.U07.handle;
`DRAMPATH3.dimmr3.U08.handle = 119+432;//`DRAMPATH3.dimm1.U08.handle;
`DRAMPATH3.dimmr3.U09.handle = 120+432;//`DRAMPATH3.dimm1.U09.handle;
`DRAMPATH3.dimmr3.U10.handle = 121+432;//`DRAMPATH3.dimm1.U10.handle;
`DRAMPATH3.dimmr3.U11.handle = 122+432;//`DRAMPATH3.dimm1.U11.handle;
`DRAMPATH3.dimmr3.U12.handle = 123+432;//`DRAMPATH3.dimm1.U12.handle;
`DRAMPATH3.dimmr3.U14.handle = 124+432;//`DRAMPATH3.dimm1.U14.handle;
`DRAMPATH3.dimmr3.U15.handle = 125+432;//`DRAMPATH3.dimm1.U15.handle;
`DRAMPATH3.dimmr3.U16.handle = 126+432;//`DRAMPATH3.dimm1.U16.handle;
`DRAMPATH3.dimmr3.U17.handle = 127+432;//`DRAMPATH3.dimm1.U17.handle;
//ecc
`DRAMPATH0.dimmr2.U04.handle = 128+432;//`DRAMPATH0.dimm0.U04.handle;
`DRAMPATH0.dimmr2.U13.handle = 129+432;//`DRAMPATH0.dimm0.U13.handle;
`DRAMPATH0.dimmr3.U04.handle = 130+432;//`DRAMPATH0.dimm1.U04.handle;
`DRAMPATH0.dimmr3.U13.handle = 131+432;//`DRAMPATH0.dimm1.U13.handle;
`DRAMPATH1.dimmr2.U04.handle = 132+432;//`DRAMPATH1.dimm0.U04.handle;
`DRAMPATH1.dimmr2.U13.handle = 133+432;//`DRAMPATH1.dimm0.U13.handle;
`DRAMPATH1.dimmr3.U04.handle = 134+432;//`DRAMPATH1.dimm1.U04.handle;
`DRAMPATH1.dimmr3.U13.handle = 135+432;//`DRAMPATH1.dimm1.U13.handle;
`DRAMPATH2.dimmr2.U04.handle = 136+432;//`DRAMPATH2.dimm0.U04.handle;
`DRAMPATH2.dimmr2.U13.handle = 137+432;//`DRAMPATH2.dimm0.U13.handle;
`DRAMPATH2.dimmr3.U04.handle = 138+432;//`DRAMPATH2.dimm1.U04.handle;
`DRAMPATH2.dimmr3.U13.handle = 139+432;//`DRAMPATH2.dimm1.U13.handle;
`DRAMPATH3.dimmr2.U04.handle = 140+432;//`DRAMPATH3.dimm0.U04.handle;
`DRAMPATH3.dimmr2.U13.handle = 141+432;//`DRAMPATH3.dimm0.U13.handle;
`DRAMPATH3.dimmr3.U04.handle = 142+432;//`DRAMPATH3.dimm1.U04.handle;
`DRAMPATH3.dimmr3.U13.handle = 143+432;//`DRAMPATH3.dimm1.U13.handle;
`endif
`endif
`endif // DRAM_SAT
#1
$display("\n(%0d): Info->Initializing Sparse Memory from: %0s\n", $time, file);
/*$init_dram(file,
//channel 0
`DRAMPATH0.dimm0.U00.handle,
`DRAMPATH0.dimm0.U01.handle,
`DRAMPATH0.dimm0.U02.handle,
`DRAMPATH0.dimm0.U03.handle,
`DRAMPATH0.dimm0.U05.handle,
`DRAMPATH0.dimm0.U06.handle,
`DRAMPATH0.dimm0.U07.handle,
`DRAMPATH0.dimm0.U08.handle,
`DRAMPATH0.dimm0.U09.handle,
`DRAMPATH0.dimm0.U10.handle,
`DRAMPATH0.dimm0.U11.handle,
`DRAMPATH0.dimm0.U12.handle,
`DRAMPATH0.dimm0.U14.handle,
`DRAMPATH0.dimm0.U15.handle,
`DRAMPATH0.dimm0.U16.handle,
`DRAMPATH0.dimm0.U17.handle,
`DRAMPATH0.dimm1.U00.handle,
`DRAMPATH0.dimm1.U01.handle,
`DRAMPATH0.dimm1.U02.handle,
`DRAMPATH0.dimm1.U03.handle,
`DRAMPATH0.dimm1.U05.handle,
`DRAMPATH0.dimm1.U06.handle,
`DRAMPATH0.dimm1.U07.handle,
`DRAMPATH0.dimm1.U08.handle,
`DRAMPATH0.dimm1.U09.handle,
`DRAMPATH0.dimm1.U10.handle,
`DRAMPATH0.dimm1.U11.handle,
`DRAMPATH0.dimm1.U12.handle,
`DRAMPATH0.dimm1.U14.handle,
`DRAMPATH0.dimm1.U15.handle,
`DRAMPATH0.dimm1.U16.handle,
`DRAMPATH0.dimm1.U17.handle,
//channel 1
`DRAMPATH1.dimm0.U00.handle,
`DRAMPATH1.dimm0.U01.handle,
`DRAMPATH1.dimm0.U02.handle,
`DRAMPATH1.dimm0.U03.handle,
`DRAMPATH1.dimm0.U05.handle,
`DRAMPATH1.dimm0.U06.handle,
`DRAMPATH1.dimm0.U07.handle,
`DRAMPATH1.dimm0.U08.handle,
`DRAMPATH1.dimm0.U09.handle,
`DRAMPATH1.dimm0.U10.handle,
`DRAMPATH1.dimm0.U11.handle,
`DRAMPATH1.dimm0.U12.handle,
`DRAMPATH1.dimm0.U14.handle,
`DRAMPATH1.dimm0.U15.handle,
`DRAMPATH1.dimm0.U16.handle,
`DRAMPATH1.dimm0.U17.handle,
`DRAMPATH1.dimm1.U00.handle,
`DRAMPATH1.dimm1.U01.handle,
`DRAMPATH1.dimm1.U02.handle,
`DRAMPATH1.dimm1.U03.handle,
`DRAMPATH1.dimm1.U05.handle,
`DRAMPATH1.dimm1.U06.handle,
`DRAMPATH1.dimm1.U07.handle,
`DRAMPATH1.dimm1.U08.handle,
`DRAMPATH1.dimm1.U09.handle,
`DRAMPATH1.dimm1.U10.handle,
`DRAMPATH1.dimm1.U11.handle,
`DRAMPATH1.dimm1.U12.handle,
`DRAMPATH1.dimm1.U14.handle,
`DRAMPATH1.dimm1.U15.handle,
`DRAMPATH1.dimm1.U16.handle,
`DRAMPATH1.dimm1.U17.handle,
//channel 2
`DRAMPATH2.dimm0.U00.handle,
`DRAMPATH2.dimm0.U01.handle,
`DRAMPATH2.dimm0.U02.handle,
`DRAMPATH2.dimm0.U03.handle,
`DRAMPATH2.dimm0.U05.handle,
`DRAMPATH2.dimm0.U06.handle,
`DRAMPATH2.dimm0.U07.handle,
`DRAMPATH2.dimm0.U08.handle,
`DRAMPATH2.dimm0.U09.handle,
`DRAMPATH2.dimm0.U10.handle,
`DRAMPATH2.dimm0.U11.handle,
`DRAMPATH2.dimm0.U12.handle,
`DRAMPATH2.dimm0.U14.handle,
`DRAMPATH2.dimm0.U15.handle,
`DRAMPATH2.dimm0.U16.handle,
`DRAMPATH2.dimm0.U17.handle,
`DRAMPATH2.dimm1.U00.handle,
`DRAMPATH2.dimm1.U01.handle,
`DRAMPATH2.dimm1.U02.handle,
`DRAMPATH2.dimm1.U03.handle,
`DRAMPATH2.dimm1.U05.handle,
`DRAMPATH2.dimm1.U06.handle,
`DRAMPATH2.dimm1.U07.handle,
`DRAMPATH2.dimm1.U08.handle,
`DRAMPATH2.dimm1.U09.handle,
`DRAMPATH2.dimm1.U10.handle,
`DRAMPATH2.dimm1.U11.handle,
`DRAMPATH2.dimm1.U12.handle,
`DRAMPATH2.dimm1.U14.handle,
`DRAMPATH2.dimm1.U15.handle,
`DRAMPATH2.dimm1.U16.handle,
`DRAMPATH2.dimm1.U17.handle,
// channel 3
`DRAMPATH3.dimm0.U00.handle,
`DRAMPATH3.dimm0.U01.handle,
`DRAMPATH3.dimm0.U02.handle,
`DRAMPATH3.dimm0.U03.handle,
`DRAMPATH3.dimm0.U05.handle,
`DRAMPATH3.dimm0.U06.handle,
`DRAMPATH3.dimm0.U07.handle,
`DRAMPATH3.dimm0.U08.handle,
`DRAMPATH3.dimm0.U09.handle,
`DRAMPATH3.dimm0.U10.handle,
`DRAMPATH3.dimm0.U11.handle,
`DRAMPATH3.dimm0.U12.handle,
`DRAMPATH3.dimm0.U14.handle,
`DRAMPATH3.dimm0.U15.handle,
`DRAMPATH3.dimm0.U16.handle,
`DRAMPATH3.dimm0.U17.handle,
`DRAMPATH3.dimm1.U00.handle,
`DRAMPATH3.dimm1.U01.handle,
`DRAMPATH3.dimm1.U02.handle,
`DRAMPATH3.dimm1.U03.handle,
`DRAMPATH3.dimm1.U05.handle,
`DRAMPATH3.dimm1.U06.handle,
`DRAMPATH3.dimm1.U07.handle,
`DRAMPATH3.dimm1.U08.handle,
`DRAMPATH3.dimm1.U09.handle,
`DRAMPATH3.dimm1.U10.handle,
`DRAMPATH3.dimm1.U11.handle,
`DRAMPATH3.dimm1.U12.handle,
`DRAMPATH3.dimm1.U14.handle,
`DRAMPATH3.dimm1.U15.handle,
`DRAMPATH3.dimm1.U16.handle,
`DRAMPATH3.dimm1.U17.handle,
//ecc
`DRAMPATH0.dimm0.U04.handle,
`DRAMPATH0.dimm0.U13.handle,
`DRAMPATH0.dimm1.U04.handle,
`DRAMPATH0.dimm1.U13.handle,
`DRAMPATH1.dimm0.U04.handle,
`DRAMPATH1.dimm0.U13.handle,
`DRAMPATH1.dimm1.U04.handle,
`DRAMPATH1.dimm1.U13.handle,
`DRAMPATH2.dimm0.U04.handle,
`DRAMPATH2.dimm0.U13.handle,
`DRAMPATH2.dimm1.U04.handle,
`DRAMPATH2.dimm1.U13.handle,
`DRAMPATH3.dimm0.U04.handle,
`DRAMPATH3.dimm0.U13.handle,
`DRAMPATH3.dimm1.U04.handle,
`DRAMPATH3.dimm1.U13.handle,
dimm_config);
*/
$display("$time, init_dram dimm_config=%b, file=%s\n", dimm_config,file);
$init_dram(file, dimm_config);
`endif // else
end // initial begin
endmodule // cmp_mem
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_PP_SYMBOL_V
/**
* lsbufhv2lv: Level-shift buffer, low voltage-to-low voltage.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbufhv2lv (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input LVPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_PP_SYMBOL_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:45:49 08/25/2014
// Design Name: Counter_x
// Module Name: E:/Summer Course/Top_Computer_IOBUS_VGA_PS2_N3/test_counter.v
// Project Name: Top_Computer_IOBUS_VGA_PS2_N3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Counter_x
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_counter;
// Inputs
reg clk;
reg rst;
reg clk0;
reg clk1;
reg clk2;
reg counter_we;
reg [31:0] counter_val;
reg [1:0] counter_ch;
// Outputs
wire counter0_OUT;
wire counter1_OUT;
wire counter2_OUT;
wire [31:0] counter_out;
// Instantiate the Unit Under Test (UUT)
Counter_x uut (
.clk(clk),
.rst(rst),
.clk0(clk0),
.clk1(clk1),
.clk2(clk2),
.counter_we(counter_we),
.counter_val(counter_val),
.counter_ch(counter_ch),
.counter0_OUT(counter0_OUT),
.counter1_OUT(counter1_OUT),
.counter2_OUT(counter2_OUT),
.counter_out(counter_out)
);
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
initial forever begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
initial forever begin
clk0 = 1'b0;
#(10*PERIOD-(10*PERIOD*DUTY_CYCLE)) clk0 = 1'b1;
#(10*PERIOD*DUTY_CYCLE);
end
initial forever begin
clk1 = 1'b0;
#(10*PERIOD-(10*PERIOD*DUTY_CYCLE)) clk1 = 1'b1;
#(10*PERIOD*DUTY_CYCLE);
end
initial forever begin
clk2 = 1'b0;
#(10*PERIOD-(10*PERIOD*DUTY_CYCLE)) clk2 = 1'b1;
#(10*PERIOD*DUTY_CYCLE);
end
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
clk0 = 0;
clk1 = 0;
clk2 = 0;
counter_we = 0;
counter_val = 16'h10;
counter_ch = 0;
// Wait 100 ns for global reset to finish
#100;
//#100 rst = 1;
//#100 rst = 0;
// Add stimulus here
#100 counter_we = 1;
//counter_ch = 1;
//counter_val = 10;
#100 counter_we = 0;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ff_jbi_sc2_2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ff_jbi_sc2_2(/*AUTOARG*/
// Outputs
jbi_sctag_req_d1, scbuf_jbi_data_d1, jbi_scbuf_ecc_d1,
jbi_sctag_req_vld_d1, scbuf_jbi_ctag_vld_d1, scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1, sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1, so,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req, rclk, si, se
);
output [31:0] jbi_sctag_req_d1;
output [31:0] scbuf_jbi_data_d1;
output [6:0] jbi_scbuf_ecc_d1;
output jbi_sctag_req_vld_d1;
output scbuf_jbi_ctag_vld_d1;
output scbuf_jbi_ue_err_d1;
output sctag_jbi_iq_dequeue_d1;
output sctag_jbi_wib_dequeue_d1;
output sctag_jbi_por_req_d1;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
input rclk;
input si, se;
output so;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
dff_s #(32) ff_flop_row0 (.q(jbi_sctag_req_d1[31:0]),
.din(jbi_sctag_req[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(32) ff_flop_row1 (.q(scbuf_jbi_data_d1[31:0]),
.din(scbuf_jbi_data[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(13) ff_flop_row2 (.q({ jbi_scbuf_ecc_d1[6:0],
jbi_sctag_req_vld_d1,
scbuf_jbi_ctag_vld_d1,
scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1,
sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1}),
.din({ jbi_scbuf_ecc[6:0],
jbi_sctag_req_vld,
scbuf_jbi_ctag_vld,
scbuf_jbi_ue_err,
sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue,
sctag_jbi_por_req}),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:39:17 02/21/2015
// Design Name:
// Module Name: SpecialCases
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SpecialCases(
input [31:0] ain_Special,
input [31:0] bin_Special,
input [31:0] cin_Special,
input [1:0] mode_Special,
input operation_Special,
input NatLogFlag_Special,
input [7:0] InsTagFSMOut,
input reset,
input clock,
output reg [1:0] idle_Special = 1'b00,
output reg [32:0] aout_Special,
output reg [32:0] bout_Special,
output reg [35:0] cout_Special,
output reg [35:0] zout_Special,
output reg [31:0] sout_Special,
output reg [1:0] modeout_Special,
output reg operationout_Special,
output reg NatLogFlagout_Special,
output reg [7:0] InsTag_Special
);
wire a_sign;
wire [7:0] a_exponent;
wire [23:0] a_mantissa;
wire b_sign;
wire [7:0] b_exponent;
wire [23:0] b_mantissa;
wire c_sign;
wire [7:0] c_exponent;
wire [26:0] c_mantissa;
assign a_sign = ain_Special[31];
assign a_exponent = {ain_Special[30:23] - 127};
assign a_mantissa = {1'b0, ain_Special[22:0]};
assign b_sign = {bin_Special[31]};
assign b_exponent = {bin_Special[30:23] - 127};
assign b_mantissa = {1'b0, bin_Special[22:0]};
assign c_sign = {cin_Special[31]};
assign c_exponent = {cin_Special[30:23] - 127};
assign c_mantissa = {cin_Special[22:0],3'd0};
parameter no_idle = 2'b00,
allign_idle = 2'b01,
put_idle = 2'b10;
always @ (posedge clock)
begin
if(reset == 1'b1) begin
idle_Special <= 1'b00;
end
else begin
InsTag_Special <= InsTagFSMOut;
modeout_Special <= mode_Special;
operationout_Special <= operation_Special;
NatLogFlagout_Special <= NatLogFlag_Special;
//if a is NaN or b is NaN return NaN
if ((a_exponent == 128 && a_mantissa != 0) || (b_exponent == 128 && b_mantissa != 0)) begin
idle_Special <= allign_idle;
aout_Special <= {a_sign,a_exponent+127,a_mantissa};
bout_Special <= {b_sign,b_exponent+127,b_mantissa};
cout_Special <= {c_sign,c_exponent+127,c_mantissa};
zout_Special <= {1'b1,8'd255,1'b1,26'd0};
sout_Special <= 0;
//if a is inf return inf
end else if (a_exponent == 128) begin
idle_Special <= allign_idle;
//if b is zero return NaN
if ($signed(b_exponent == -127) && (b_mantissa == 0)) begin
idle_Special <= allign_idle;
aout_Special <= {a_sign,a_exponent,a_mantissa};
bout_Special <= {b_sign,b_exponent,b_mantissa};
cout_Special <= {c_sign,c_exponent,c_mantissa};
zout_Special <= {1'b1,8'd255,1'b1,26'd0};
sout_Special <= 0;
end
else begin
aout_Special <= {a_sign,a_exponent,a_mantissa};
bout_Special <= {b_sign,b_exponent,b_mantissa};
cout_Special <= {c_sign,c_exponent,c_mantissa};
zout_Special <= {a_sign ^ b_sign,8'd255,27'd0};
sout_Special <= 0;
end
//if b is inf return inf
end else if (b_exponent == 128) begin
idle_Special <= allign_idle;
aout_Special <= {a_sign,a_exponent,a_mantissa};
bout_Special <= {b_sign,b_exponent,b_mantissa};
cout_Special <= {c_sign,c_exponent,c_mantissa};
zout_Special <= {a_sign ^ b_sign,8'd255,27'd0};
sout_Special <= 0;
//if a is zero return zero
end else if (($signed(a_exponent) == -127) && (a_mantissa == 0)) begin
idle_Special <= put_idle;
aout_Special[32] <= a_sign;
aout_Special[31:24] <= a_exponent+127;
aout_Special[23] <= 1'b1;
aout_Special[22:0] <= a_mantissa[22:0];
bout_Special[32] <= b_sign;
bout_Special[31:24] <= b_exponent+127;
bout_Special[23] <= 1'b1;
bout_Special[22:0] <= b_mantissa[22:0];
cout_Special[35] <= c_sign;
cout_Special[34:27] <= c_exponent+127;
cout_Special[26:0] <= c_mantissa[26:0];
zout_Special <= {a_sign ^ b_sign,8'd0,27'd0};
sout_Special <= {c_sign,c_exponent + 127,c_mantissa[25:3]};
//if b is zero return zero
end else if (($signed(b_exponent) == -127) && (b_mantissa == 0)) begin
aout_Special[32] <= a_sign;
aout_Special[31:24] <= a_exponent+127;
aout_Special[23] <= 1'b1;
aout_Special[22:0] <= a_mantissa[22:0];
bout_Special[32] <= b_sign;
bout_Special[31:24] <= b_exponent+127;
bout_Special[23] <= 1'b1;
bout_Special[22:0] <= b_mantissa[22:0];
cout_Special[35] <= c_sign;
cout_Special[35] <= c_sign;
cout_Special[34:27] <= c_exponent+127;
cout_Special[26:0] <= c_mantissa[26:0];
zout_Special <= {a_sign ^ b_sign,8'd0,27'd0};
sout_Special <= {c_sign,c_exponent + 127,c_mantissa[25:3]};
idle_Special <= put_idle;
// If mode is linear, return 0 for product
end else if (mode_Special == 2'b00) begin
idle_Special <= put_idle;
aout_Special[32] <= a_sign;
aout_Special[31:24] <= a_exponent+127;
aout_Special[23] <= 1'b1;
aout_Special[22:0] <= a_mantissa[22:0];
bout_Special[32] <= b_sign;
bout_Special[31:24] <= b_exponent+127;
bout_Special[23] <= 1'b1;
bout_Special[22:0] <= b_mantissa[22:0];
cout_Special[35] <= c_sign;
cout_Special[34:27] <= c_exponent+127;
cout_Special[26:0] <= c_mantissa[26:0];
zout_Special <= {a_sign ^ b_sign,8'd0,27'd0};
sout_Special <= {c_sign,c_exponent + 127,c_mantissa[25:3]};
end else begin
//Denormalised Number
cout_Special[35] <= c_sign;
cout_Special[34:27] <= c_exponent+127;
cout_Special[26:0] <= c_mantissa[26:0];
zout_Special <= 0;
sout_Special <= 0;
idle_Special <= no_idle;
if ($signed(a_exponent) == -127) begin
aout_Special <= {a_sign,-126,a_mantissa};
end else begin
aout_Special[32] <= a_sign;
aout_Special[31:24] <= a_exponent+127;
aout_Special[23] <= 1'b1;
aout_Special[22:0] <= a_mantissa[22:0];
end
//Denormalised Number
if ($signed(b_exponent) == -127) begin
bout_Special <= {b_sign,-126,b_mantissa};
end else begin
bout_Special[32] <= b_sign;
bout_Special[31:24] <= b_exponent+127;
bout_Special[23] <= 1'b1;
bout_Special[22:0] <= b_mantissa[22:0];
end
end
end
end
endmodule
|
module top;
typedef reg [4:0] T1;
typedef T1 [7:0] T2;
T2 q_tst [$:2];
T2 q_tmp [$];
bit passed;
task automatic check_size(integer size,
string fname,
integer lineno);
if (q_tst.size !== size) begin
$display("%s:%0d: Failed: queue size != %0d (%0d)",
fname, lineno, size, q_tst.size);
passed = 1'b0;
end
endtask
task automatic check_idx_value(integer idx,
T2 expected,
string fname,
integer lineno);
if (q_tst[idx] != expected) begin
$display("%s:%0d: Failed: element [%0d] != %0d (%0d)",
fname, lineno, idx, expected, q_tst[idx]);
passed = 1'b0;
end
endtask
initial begin
passed = 1'b1;
check_size(0, `__FILE__, `__LINE__);
q_tst.push_back(2);
q_tst.push_front(1);
q_tst.push_back(3);
q_tst.push_back(100); // Warning: item not added.
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 1, `__FILE__, `__LINE__);
check_idx_value(1, 2, `__FILE__, `__LINE__);
check_idx_value(2, 3, `__FILE__, `__LINE__);
q_tst.push_front(5); // Warning: back item removed.
q_tst[3] = 3; // Warning: item not added.
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 5, `__FILE__, `__LINE__);
check_idx_value(1, 1, `__FILE__, `__LINE__);
check_idx_value(2, 2, `__FILE__, `__LINE__);
q_tst.insert(3, 10); // Warning: item not added.
q_tst.insert(1, 2); // Warning: back item removed.
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 5, `__FILE__, `__LINE__);
check_idx_value(1, 2, `__FILE__, `__LINE__);
check_idx_value(2, 1, `__FILE__, `__LINE__);
q_tst = '{1, 2, 3, 4}; // Warning: items not added.
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 1, `__FILE__, `__LINE__);
check_idx_value(1, 2, `__FILE__, `__LINE__);
check_idx_value(2, 3, `__FILE__, `__LINE__);
q_tmp = '{4, 3, 2, 1};
q_tst = q_tmp; // Warning not all items copied
q_tmp[0] = 5;
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 4, `__FILE__, `__LINE__);
check_idx_value(1, 3, `__FILE__, `__LINE__);
check_idx_value(2, 2, `__FILE__, `__LINE__);
if (passed) $display("PASSED");
end
endmodule : top
|
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:156];
wire [63:0] iaddrbus, daddrbus;
reg [63:0] iaddrbusout[0:156], daddrbusout[0:156];
wire [63:0] databus;
reg [63:0] databusk, databusin[0:156], databusout[0:156];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [24*8:1] iname[0:156];
integer error, k, ntests;
//all opcode parameters to be used
parameter ADD = 11'b10001011000;
parameter ADDI = 10'b1001000100;
parameter ADDIS = 10'b1011000100;
parameter ADDS = 11'b10101011000;
parameter AND = 11'b10001010000;
parameter ANDI = 10'b1001001000;
parameter ANDIS = 10'b1111001000;
parameter ANDS = 11'b11101010000;
parameter CBNZ = 8'b10110101;
parameter CBZ = 8'b10110100;
parameter EOR = 11'b11001010000;
parameter EORI = 10'b1101001000;
parameter LDUR = 11'b11111000010;
parameter LSL = 11'b11010011011;
parameter LSR = 11'b11010011010;
parameter MOVZ = 9'b110100101;
parameter ORR = 11'b10101010000;
parameter ORRI = 10'b1011001000;
parameter STUR = 11'b11111000000;
parameter SUB = 11'b11001011000;
parameter SUBI = 10'b1101000100;
parameter SUBIS = 10'b1111000100;
parameter SUBS = 11'b11101011000;
parameter B = 6'b000101;
parameter B_EQ = 8'b01010101;
parameter B_NE = 8'b01010110;
parameter B_LT = 8'b01010111;
parameter B_GE = 8'b01011000;
//register parameters
parameter R0 = 5'b00000;
parameter R15 = 5'b01111;
parameter R16 = 5'b10000;
parameter R17 = 5'b10001;
parameter R18 = 5'b10010;
parameter R19 = 5'b10011;
parameter R20 = 5'b10100;
parameter R21 = 5'b10101;
parameter R22 = 5'b10110;
parameter R23 = 5'b10111;
parameter R24 = 5'b11000;
parameter R25 = 5'b11001;
parameter R26 = 5'b11010;
parameter R27 = 5'b11011;
parameter R28 = 5'b11100;
parameter R29 = 5'b11101;
parameter R30 = 5'b11110;
parameter R31 = 5'b11111;
//other parameterz to be used
parameter zeroSham = 6'b000000;
parameter RX = 5'b11111;
parameter oneShamt = 6'b000001;//shifts 1 bit
parameter twoShamt = 6'b000010;
parameter threeShamt = 6'b000011;
parameter fourShamt = 6'b000100;//moves 1 hex place
parameter eightShamt = 6'b001000;//moves 2 hex place
parameter move_0 = 2'b00;
parameter move_1 = 2'b01;
parameter move_2 = 2'b10;
parameter move_3 = 2'b11;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
dontcare = 64'hx;
//phase 1: testing basic op commands
// op, rd, rn, rm
iname[0] ="ADDI, R20, R31, #AAA";//testing addi, result in R20 = 0000000000000AAA
iaddrbusout[0] = 64'h00000000;
// opcode rm/ALUImm rn rd
instrbusin[0] ={ADDI, 12'hAAA, R31, R20};
daddrbusout[0] = dontcare;
databusin[0] = 64'bz;
databusout[0] = dontcare;
// op, rd, rn, rm
iname[1] ="ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 0000000000000000
iaddrbusout[1] = 64'h00000004;
// opcode rm/ALUImm rn rd
instrbusin[1] ={ADDI, 12'h002, R23, R31};
daddrbusout[1] = dontcare;
databusin[1] = 64'bz;
databusout[1] = dontcare;
// op, rd, rn, rm
iname[2] ="ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 0000000000000002
iaddrbusout[2] = 64'h00000008;
// opcode rm/ALUImm rn rd
instrbusin[2] ={ADDI, 12'h002, R23, R0};
daddrbusout[2] = dontcare;
databusin[2] = 64'bz;
databusout[2] = dontcare;
// op, rd, rn, rm
iname[3] ="ORRI, R21, R24, #001";//testing ori, result in R21 = 0000000000000001
iaddrbusout[3] = 64'h0000000C;
// opcode rm/ALUImm rn rd
instrbusin[3] ={ORRI, 12'h001, R24, R21};
daddrbusout[3] = dontcare;
databusin[3] = 64'bz;
databusout[3] = dontcare;
// op, rd, rn, rm
iname[4] ="EORI, R22, R20, #000";//testing xori, result in R22 = 0000000000000AAA
iaddrbusout[4] = 64'h00000010;
// opcode rm/ALUImm rn rd
instrbusin[4] ={EORI, 12'h000, R20, R22};
daddrbusout[4] = dontcare;
databusin[4] = 64'bz;
databusout[4] = dontcare;
// op, rd, rn, rm
iname[5] ="ANDI, R23, R0, #003";//testing andi, result in R23 = 0000000000000002
iaddrbusout[5] = 64'h00000014;
// opcode rm/ALUImm rn rd
instrbusin[5] ={ANDI, 12'h003, R0, R23};
daddrbusout[5] = dontcare;
databusin[5] = 64'bz;
databusout[5] = dontcare;
// op, rd, rn, rm
iname[6] ="SUBI, R24, R20, #00A";//testing subi, result in R24 = 0000000000000AA0
iaddrbusout[6] = 64'h00000018;
// opcode rm/ALUImm rn rd
instrbusin[6] ={SUBI, 12'h00A, R20, R24};
daddrbusout[6] = dontcare;
databusin[6] = 64'bz;
databusout[6] = dontcare;
// op, rd, rn, rm
iname[7] ="ADD, R25, R20, R0";//testing add, result in R25 = 0000000000000AAC
iaddrbusout[7] = 64'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7] ={ADD, R0, zeroSham, R20, R25};
daddrbusout[7] = dontcare;
databusin[7] = 64'bz;
databusout[7] = dontcare;
// op, rd, rn, rm
iname[8] ="AND, R26, R20, R22";//testing and, result in R26 = 0000000000000AAA
iaddrbusout[8] = 64'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8] ={AND, R22, zeroSham, R20, R26};
daddrbusout[8] = dontcare;
databusin[8] = 64'bz;
databusout[8] = dontcare;
// op, rd, rn, rm
iname[9] ="EOR, R27, R23, R21";//testing xor, result in R27 = 0000000000000003
iaddrbusout[9] = 64'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9] ={EOR, R21, zeroSham, R23, R27};
daddrbusout[9] = dontcare;
databusin[9] = 64'bz;
databusout[9] = dontcare;
// op, rd, rn, rm
iname[10] ="ORR, R28, R25, R23";//testing or, result in R28 = 0000000000000AAE
iaddrbusout[10] = 64'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10] ={ORR, R23, zeroSham, R25, R28};
daddrbusout[10] = dontcare;
databusin[10] = 64'bz;
databusout[10] = dontcare;
// op, rd, rn, rm
iname[11] ="SUB, R29, R20, R22";//testing sub, result in R29 = 0000000000000000
iaddrbusout[11] = 64'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11] ={SUB, R22, zeroSham, R20, R29};
daddrbusout[11] = dontcare;
databusin[11] = 64'bz;
databusout[11] = dontcare;
// op, rd, rn, aluImm
iname[12] ="ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 0000000000000000
iaddrbusout[12] = 64'h00000030;
// opcode rm/ALUImm rn rd
instrbusin[12] ={ADDI, 12'h000, R31, R30};
daddrbusout[12] = dontcare;
databusin[12] = 64'bz;
databusout[12] = dontcare;
//phase 2: testing basic op codes with the set flags
// op, rd, rn, aluImm
iname[13] ="SUBIS,R20, R0, #003";//testing subis, n flag, result in R20 = FFFFFFFFFFFFFFFF
iaddrbusout[13] = 64'h00000034;
// opcode rm/ALUImm rn rd
instrbusin[13] ={SUBIS, 12'h003, R0, R20};
daddrbusout[13] = dontcare;
databusin[13] = 64'bz;
databusout[13] = dontcare;
// op, rd, rn, rm
iname[14] ="SUBS, R21, R25, R28";//testing subs, n flag, result in R21 = FFFFFFFFFFFFFFFE
iaddrbusout[14] = 64'h00000038;
// op, rm, shamt, rn, rd
instrbusin[14] ={SUBS,R28,zeroSham, R25, R21};
daddrbusout[14] = dontcare;
databusin[14] = 64'bz;
databusout[14] = dontcare;
// op, rd, rn, aluImm
iname[15] ="ADDIS,R22, R31, #000";//testing addis, z flag, result in R22 = 0000000000000000
iaddrbusout[15] = 64'h0000003C;
// opcode rm/ALUImm rn rd
instrbusin[15] ={ADDIS, 12'h000, R31, R22};
daddrbusout[15] = dontcare;
databusin[15] = 64'bz;
databusout[15] = dontcare;
// op, rd, rn, rm
iname[16] ="ADDS R23, R20, R23";//testing adds, c flag, result in R23 = 0000000000000001
iaddrbusout[16] = 64'h00000040;
// op, rm, shamt, rn, rd
instrbusin[16] ={ADDS,R23,zeroSham, R20, R23};
daddrbusout[16] = dontcare;
databusin[16] = 64'bz;
databusout[16] = dontcare;
// op, rd, rn, aluImm
iname[17] ="ANDIS,R24, R20, #002";//testing andis, reseting n,z flags to low, result in R24 = 0000000000000002
iaddrbusout[17] = 64'h00000044;
// opcode rm/ALUImm rn rd
instrbusin[17] ={ANDIS, 12'h002, R20, R24};
daddrbusout[17] = dontcare;
databusin[17] = 64'bz;
databusout[17] = dontcare;
// op, rd, rn, rm
iname[18] ="ANDS, R25, R21, R20";//testing ands, n flag, result in R25 = FFFFFFFFFFFFFFFE
iaddrbusout[18] = 64'h00000048;
// op, rm, shamt, rn, rd
instrbusin[18] ={ANDS, R20, zeroSham, R21, R25};
daddrbusout[18] = dontcare;
databusin[18] = 64'bz;
databusout[18] = dontcare;
//phase 3: testing LSL, LSR
//setting up the register R20 for a test of the LSL
// op, rd, rn, rm
iname[19] ="ADDI, R20, R31, #007";//setting up for left shift, result in R20 = 0000000000000007
iaddrbusout[19] = 64'h0000004C;
// opcode rm/ALUImm rn rd
instrbusin[19] ={ADDI, 12'h007, R31, R20};
daddrbusout[19] = dontcare;
databusin[19] = 64'bz;
databusout[19] = dontcare;
// op, rd, rn, rm
iname[20] ="ADDI, R21, R31, #700";//setting up for right shift, n flag, result in R21 = 0000000000000700
iaddrbusout[20] = 64'h00000050;
// opcode rm/ALUImm rn rd
instrbusin[20] ={ADDI, 12'h700, R31, R21};
daddrbusout[20] = dontcare;
databusin[20] = 64'bz;
databusout[20] = dontcare;
// op, rd, rn, rm
iname[21] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[21] = 64'h00000054;
// op, rm, shamt, rn, rd
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
daddrbusout[21] = dontcare;
databusin[21] = 64'bz;
databusout[21] = dontcare;
// op, rd, rn, rm
iname[22] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[22] = 64'h00000058;
// op, rm, shamt, rn, rd
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
daddrbusout[22] = dontcare;
databusin[22] = 64'bz;
databusout[22] = dontcare;
// op, rd, rn, shamt
iname[23] ="LSL, R20, R20, #2";//testing left shift, result in R20 = 0000000000000700
iaddrbusout[23] = 64'h0000005C;
// op, rm, shamt, rn, rd
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
daddrbusout[23] = dontcare;
databusin[23] = 64'bz;
databusout[23] = dontcare;
// op, rd, rn, shamt
iname[24] ="LSR, R21, R21, #2";//testing right shift, result in R21 = 0000000000000007
iaddrbusout[24] = 64'h00000060;
// op, rm, shamt, rn, rd
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
daddrbusout[24] = dontcare;
databusin[24] = 64'bz;
databusout[24] = dontcare;
//phase 4: testing load and store and overflow bit
// op, rt, rn, DT_adr
iname[25] ="LDUR, R22, R31, #1";//testing load, result in R22 = 42069 (from memory,databusin) [yes, really]
iaddrbusout[25] = 64'h00000064;
// op, DT_ADDR, ?, rn, rt
instrbusin[25] ={LDUR, 9'b000000001, 2'b00, R31, R22};
daddrbusout[25] = 64'h0000000000000001;//used for LDUR
databusin[25] = 64'h0000000000042069;//used for LDUR
databusout[25] = dontcare;
// op, rn, DT_adr, rt
iname[26] ="STUR, R23, #068, R24";//testing story, result for databusout in R24 = 0000000000000002 (to memory)
//address is calculated from imm or 68, and R23, which is currently 1
iaddrbusout[26] = 64'h00000068;
// op, DT_ADDR, ?, rn, rt
instrbusin[26] ={STUR, 9'b001101000, 2'b00, R23, R24};
daddrbusout[26] = 64'h0000000000000069;//used for STUR
databusin[26] = 64'bz;
databusout[26] = 64'h0000000000000002;//used for STUR
// op, rd, rn, rm
iname[27] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[27] = 64'h0000006C;
// op, rm, shamt, rn, rd
instrbusin[27] ={AND, R31, zeroSham, R31, R19};
daddrbusout[27] = dontcare;
databusin[27] = 64'bz;
databusout[27] = dontcare;
// op, rd, rn, rm
iname[28] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[28] = 64'h00000070;
// op, rm, shamt, rn, rd
instrbusin[28] ={AND, R31, zeroSham, R31, R19};
daddrbusout[28] = dontcare;
databusin[28] = 64'bz;
databusout[28] = dontcare;
// op, rd, rn, rm
iname[29] ="AND, R17, R31, R31";//delay, result in R17 = 0000000000000000
iaddrbusout[29] = 64'h00000074;
// op, rm, shamt, rn, rd
instrbusin[29] ={AND, R31, zeroSham, R31, R19};
daddrbusout[29] = dontcare;
databusin[29] = 64'bz;
databusout[29] = dontcare;
//phase 5: testing B branch
// op, BR_address
iname[30] ="B, #EA";//testing branch, calculated branch address should be
// (64'h0000000000000078 + 64'h000000000000003A8 = 64'h0000000000000420)
iaddrbusout[30] = 64'h00000078;
// op, BR_address
instrbusin[30] ={B, 26'b00000000000000000011101010};
daddrbusout[30] = dontcare;
databusin[30] = 64'bz;
databusout[30] = dontcare;
// op, rd, rn, rm
iname[31] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[31] = 64'h0000007C;
// op, rm, shamt, rn, rd
instrbusin[31] ={AND, R31, zeroSham, R31, R19};
daddrbusout[31] = dontcare;
databusin[31] = 64'bz;
databusout[31] = dontcare;
// op, rd, rn, rm
iname[32] ="ADD, R20, R21, R20";//testing branch address result in R20 = 0000000000000707
iaddrbusout[32] = 64'h00000420;
// op, rm, shamt, rn, rd
instrbusin[32] ={ADD, R20, zeroSham, R21, R20};
daddrbusout[32] = dontcare;
databusin[32] = 64'bz;
databusout[32] = dontcare;
//phase 6: testing B.EQ and B.NE branch
// op, rd, rn, rm
iname[33] ="ADDI, R21, R31, #AAA";//testing addi, result in R21 = 0000000000000AAA
iaddrbusout[33] = 64'h00000424;
// opcode rm/ALUImm rn rd
instrbusin[33] ={ADDI, 12'hAAA, R31, R21};
daddrbusout[33] = dontcare;
databusin[33] = 64'bz;
databusout[33] = dontcare;
// op, rd, rn, rm
iname[34] ="ADDI, R22, R31, #AAA";//testing addi, result in R22 = 0000000000000AAA
iaddrbusout[34] = 64'h00000428;
// opcode rm/ALUImm rn rd
instrbusin[34] ={ADDI, 12'hAAA, R31, R22};
daddrbusout[34] = dontcare;
databusin[34] = 64'bz;
databusout[34] = dontcare;
//ADDIS for FAKE BRANCH
// op, rd, rn, aluImm
iname[35] ="ADDIS,R31, R31, #420";//testing fake branch, this should NOT set the Z high
iaddrbusout[35] = 64'h0000042C;
// opcode rm/ALUImm rn rd
instrbusin[35] ={ADDIS, 12'h420, R31, R31};
daddrbusout[35] = dontcare;
databusin[35] = 64'bz;
databusout[35] = dontcare;
//FAKE BRANCH
// op, COND_addr, rt
iname[36] ="B_EQ, #69420, RX";//testing to NOT take the branch, Z should be LOW
iaddrbusout[36] = 64'h00000430;
// op, COND_addr, rt
instrbusin[36] ={B_EQ, 19'b1101001010000100000, RX};
daddrbusout[36] = dontcare;
databusin[36] = 64'bz;
databusout[36] = dontcare;
iname[37] = "NOP";//nada
iaddrbusout[37] = 64'h00000434;
instrbusin[37] = 64'b0;
daddrbusout[37] = dontcare;
databusin[37] = 64'bz;
databusout[37] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[38] ="SUBS, R31, R21, R22";//set z flag for BEQ,
iaddrbusout[38] = 64'h00000438;
// op, rm, shamt, rn, rd
instrbusin[38] ={SUBS, R22, zeroSham, R21, R31};
daddrbusout[38] = dontcare;
databusin[38] = 64'bz;
databusout[38] = dontcare;
//real branch for B.EQ (I have the best branches)
// op, COND_addr, rt
iname[39] ="B_EQ, #69, RX";//take the branch to instruction count 440
iaddrbusout[39] = 64'h0000043C;
// op, COND_addr, rt
instrbusin[39] ={B_EQ, 19'b0000000000001101001, RX};
//19'b
daddrbusout[39] = dontcare;
databusin[39] = 64'bz;
databusout[39] = dontcare;
iname[40] = "NOP";//nada
iaddrbusout[40] = 64'h00000440;
instrbusin[40] = 64'b0;
daddrbusout[40] = dontcare;
databusin[40] = 64'bz;
databusout[40] = dontcare;
iname[41] = "NOP";//nada
iaddrbusout[41] = 64'h000005E0;
instrbusin[41] = 64'b0;
daddrbusout[41] = dontcare;
databusin[41] = 64'bz;
databusout[41] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[42] ="SUBS, R31, R21, R20";//set z flag of NOT for BNE
iaddrbusout[42] = 64'h000005E4;
// op, rm, shamt, rn, rd
instrbusin[42] ={SUBS, R20, zeroSham, R21, R31};
daddrbusout[42] = dontcare;
databusin[42] = 64'bz;
databusout[42] = dontcare;
//test B.NE
// op, COND_addr, rt
iname[43] ="B_NE, #96, RX";//take the branch to instruction count 840
iaddrbusout[43] = 64'h000005E8;
// op, COND_addr, rt
instrbusin[43] ={B_NE, 19'b0000000000010010110, RX};
daddrbusout[43] = dontcare;
databusin[43] = 64'bz;
databusout[43] = dontcare;
iname[44] = "NOP";//nada
iaddrbusout[44] = 64'h000005EC;
instrbusin[44] = 64'b0;
daddrbusout[44] = dontcare;
databusin[44] = 64'bz;
databusout[44] = dontcare;
iname[45] = "NOP";//nada
iaddrbusout[45] = 64'h00000840;
instrbusin[45] = 64'b0;
daddrbusout[45] = dontcare;
databusin[45] = 64'bz;
databusout[45] = dontcare;
//phase 7: testing CBNZ and CBZ branch
//DONT take the CBZ
// op, COND_addr, rt
iname[46] ="CBZ, #F, R22";//take the branch to instruction count
iaddrbusout[46] = 64'h00000844;
// op, COND_addr, rt
instrbusin[46] ={CBZ, 19'b0000000000000001111, R22};
daddrbusout[46] = dontcare;
databusin[46] = 64'bz;
databusout[46] = dontcare;
iname[47] = "NOP";//nada
iaddrbusout[47] = 64'h00000848;
instrbusin[47] = 64'b0;
daddrbusout[47] = dontcare;
databusin[47] = 64'bz;
databusout[47] = dontcare;
iname[48] = "NOP";//nada
iaddrbusout[48] = 64'h0000084C;
instrbusin[48] = 64'b0;
daddrbusout[48] = dontcare;
databusin[48] = 64'bz;
databusout[48] = dontcare;
//TAKE the CBZ
// op, COND_addr, rt
iname[49] ="CBZ, #21, R19";//take the branch to instruction count
iaddrbusout[49] = 64'h00000850;
// op, COND_addr, rt
instrbusin[49] ={CBZ, 19'b0000000000000100001, R19};
daddrbusout[49] = dontcare;
databusin[49] = 64'bz;
databusout[49] = dontcare;
iname[50] = "NOP";//nada
iaddrbusout[50] = 64'h00000854;
instrbusin[50] = 64'b0;
daddrbusout[50] = dontcare;
databusin[50] = 64'bz;
databusout[50] = dontcare;
iname[51] = "NOP";//nada
iaddrbusout[51] = 64'h000008D4;
instrbusin[51] = 64'b0;
daddrbusout[51] = dontcare;
databusin[51] = 64'bz;
databusout[51] = dontcare;
//DONT take the CBNZ
// op, COND_addr, rt
iname[52] ="CBNZ, #FF, R31";//take the branch to instruction count
iaddrbusout[52] = 64'h000008D8;
// op, COND_addr, rt
instrbusin[52] ={CBNZ, 19'b0000000000011111111, R31};
daddrbusout[52] = dontcare;
databusin[52] = 64'bz;
databusout[52] = dontcare;
iname[53] = "NOP";//nada
iaddrbusout[53] = 64'h000008DC;
instrbusin[53] = 64'b0;
daddrbusout[53] = dontcare;
databusin[53] = 64'bz;
databusout[53] = dontcare;
iname[54] = "NOP";//nada
iaddrbusout[54] = 64'h000008E0;
instrbusin[54] = 64'b0;
daddrbusout[54] = dontcare;
databusin[54] = 64'bz;
databusout[54] = dontcare;
//TAKE the CBNZ
// op, COND_addr, rt
iname[55] ="CBNZ, #22, R20";//take the branch to instruction count
iaddrbusout[55] = 64'h000008E4;
// op, COND_addr, rt
instrbusin[55] ={CBNZ, 19'b0000000000000100010, R20};
daddrbusout[55] = dontcare;
databusin[55] = 64'bz;
databusout[55] = dontcare;
iname[56] = "NOP";//nada
iaddrbusout[56] = 64'h000008E8;
instrbusin[56] = 64'b0;
daddrbusout[56] = dontcare;
databusin[56] = 64'bz;
databusout[56] = dontcare;
iname[57] = "NOP";//nada
iaddrbusout[57] = 64'h0000096C;
instrbusin[57] = 64'b0;
daddrbusout[57] = dontcare;
databusin[57] = 64'bz;
databusout[57] = dontcare;
//phase 8: testing MOVEZ and overflow bit
//4 instructions to set registers to 0
// op, rd, rn, rm
iname[58] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[58] = 64'h00000970;
// op, rm, shamt, rn, rd
instrbusin[58] ={AND, R31, zeroSham, R31, R19};
daddrbusout[58] = dontcare;
databusin[58] = 64'bz;
databusout[58] = dontcare;
// op, rd, rn, rm
iname[59] ="AND, R20, R31, R31";//delay, result in R20 = 0000000000000000
iaddrbusout[59] = 64'h00000974;
// op, rm, shamt, rn, rd
instrbusin[59] ={AND, R31, zeroSham, R31, R20};
daddrbusout[59] = dontcare;
databusin[59] = 64'bz;
databusout[59] = dontcare;
// op, rd, rn, rm
iname[60] ="AND, R21, R31, R31";//delay, result in R21 = 0000000000000000
iaddrbusout[60] = 64'h00000978;
// op, rm, shamt, rn, rd
instrbusin[60] ={AND, R31, zeroSham, R31, R21};
daddrbusout[60] = dontcare;
databusin[60] = 64'bz;
databusout[60] = dontcare;
// op, rd, rn, rm
iname[61] ="AND, R22, R31, R31";//delay, result in R22 = 0000000000000000
iaddrbusout[61] = 64'h0000097C;
// op, rm, shamt, rn, rd
instrbusin[61] ={AND, R31, zeroSham, R31, R22};
daddrbusout[61] = dontcare;
databusin[61] = 64'bz;
databusout[61] = dontcare;
//4 MOVZ commands
//move 0 amt
// op, move_amt, MOV_imm, rd
iname[62] ="MOVZ, move_0, #FFFF, R19";//testing move, result in R19 = 000000000000FFFF
iaddrbusout[62] = 64'h00000980;
// op, move_amt, MOV_imm, rd
instrbusin[62] ={MOVZ, move_0, 16'hFFFF, R19};
daddrbusout[62] = dontcare;
databusin[62] = 64'bz;
databusout[62] = dontcare;
//move 1 amt
// op, move_amt, MOV_imm, rd
iname[63] ="MOVZ, move_1, #FFFF, R20";//testing move, result in R20 = 00000000FFFF0000
iaddrbusout[63] = 64'h00000984;
// op, move_amt, MOV_imm, rd
instrbusin[63] ={MOVZ, move_1, 16'hFFFF, R20};
daddrbusout[63] = dontcare;
databusin[63] = 64'bz;
databusout[63] = dontcare;
//move 2 amt
// op, move_amt, MOV_imm, rd
iname[64] ="MOVZ, move_2, #FFFF, R21";//testing move, result in R21 = 0000FFFF00000000
iaddrbusout[64] = 64'h00000988;
// op, move_amt, MOV_imm, rd
instrbusin[64] ={MOVZ, move_2, 16'hFFFF, R21};
daddrbusout[64] = dontcare;
databusin[64] = 64'bz;
databusout[64] = dontcare;
//move 3 amt
// op, move_amt, MOV_imm, rd
iname[65] ="MOVZ, move_3, #7FFF, R22";//testing move, result in R22 = 7FFF000000000000
iaddrbusout[65] = 64'h0000098C;
// op, move_amt, MOV_imm, rd
instrbusin[65] ={MOVZ, move_3, 16'h7FFF, R22};
daddrbusout[65] = dontcare;
databusin[65] = 64'bz;
databusout[65] = dontcare;
//have or for move 0 and move 1
// op, rd, rn, rm
iname[66] ="ORR, R23, R19, R20";//testing xor, result in R23 = 00000000FFFFFFFF
iaddrbusout[66] = 64'h00000990;
// op, rm, shamt, rn, rd
instrbusin[66] ={ORR, R20, zeroSham, R19, R23};
daddrbusout[66] = dontcare;
databusin[66] = 64'bz;
databusout[66] = dontcare;
//delay
iname[67] = "NOP";//nada
iaddrbusout[67] = 64'h00000994;
instrbusin[67] = 64'b0;
daddrbusout[67] = dontcare;
databusin[67] = 64'bz;
databusout[67] = dontcare;
//have or for move 2 and move 3
// op, rd, rn, rm
iname[68] ="ORR, R24, R21, R22";//testing xor, result in R27 = 7FFFFFFF00000000
iaddrbusout[68] = 64'h00000998;
// op, rm, shamt, rn, rd
instrbusin[68] ={ORR, R22, zeroSham, R21, R24};
daddrbusout[68] = dontcare;
databusin[68] = 64'bz;
databusout[68] = dontcare;
//delay
iname[69] = "NOP";//nada
iaddrbusout[69] = 64'h0000099C;
instrbusin[69] = 64'b0;
daddrbusout[69] = dontcare;
databusin[69] = 64'bz;
databusout[69] = dontcare;
//delay
iname[70] = "NOP";//nada
iaddrbusout[70] = 64'h000009A0;
instrbusin[70] = 64'b0;
daddrbusout[70] = dontcare;
databusin[70] = 64'bz;
databusout[70] = dontcare;
//have or for move(0|1) and move(2|3)
// op, rd, rn, rm
iname[71] ="ORR, R25, R23, R24";//testing xor, result in R25 = 7FFFFFFFFFFFFFFF
iaddrbusout[71] = 64'h000009A4;
// op, rm, shamt, rn, rd
instrbusin[71] ={ORR, R24, zeroSham, R23, R25};
daddrbusout[71] = dontcare;
databusin[71] = 64'bz;
databusout[71] = dontcare;
//dealy
iname[72] = "NOP";//nada
iaddrbusout[72] = 64'h000009A8;
instrbusin[72] = 64'b0;
daddrbusout[72] = dontcare;
databusin[72] = 64'bz;
databusout[72] = dontcare;
//delay
iname[73] = "NOP";//nada
iaddrbusout[73] = 64'h000009AC;
instrbusin[73] = 64'b0;
daddrbusout[73] = dontcare;
databusin[73] = 64'bz;
databusout[73] = dontcare;
//addis command to trigger the V bit
// op, rd, rn, aluImm
iname[74] ="ADDIS,R26, R25, #001";//testing xor and V bit and N bit, result in R26 = 8000000000000000
iaddrbusout[74] = 64'h000009B0;
// opcode rm/ALUImm rn rd
instrbusin[74] ={ADDIS, 12'h001, R25, R26};
daddrbusout[74] = dontcare;
databusin[74] = 64'bz;
databusout[74] = dontcare;
iname[75] = "NOP";//nada
iaddrbusout[75] = 64'h000009B4;
instrbusin[75] = 64'b0;
daddrbusout[75] = dontcare;
databusin[75] = 64'bz;
databusout[75] = dontcare;
iname[76] = "NOP";//nada
iaddrbusout[76] = 64'h000009B8;
instrbusin[76] = 64'b0;
daddrbusout[76] = dontcare;
databusin[76] = 64'bz;
databusout[76] = dontcare;
//phase 9: testing B.LT and B.GE branch
//7FFF+1 = N and V, 8000-1 = V
//use SUBIS for the branch condition test (B.LT test)
// op, rd, rn, aluImm
iname[77] ="SUBIS,R26, R26, #001";//result in R26 = 7FFFFFFFFFFFFFFF
iaddrbusout[77] = 64'h000009BC;
// opcode rm/ALUImm rn rd
instrbusin[77] ={SUBIS, 12'h001, R26, R26};
daddrbusout[77] = dontcare;
databusin[77] = 64'bz;
databusout[77] = dontcare;
//TAKE branch
// op, COND_addr, rt
iname[78] ="B_LT, #42, RX";//new branch address is AC8
iaddrbusout[78] = 64'h000009C0;
// op, COND_addr, rt
instrbusin[78] ={B_LT, 19'b0000000000001000010, RX};
daddrbusout[78] = dontcare;
databusin[78] = 64'bz;
databusout[78] = dontcare;
//delay
iname[79] = "NOP";//nada
iaddrbusout[79] = 64'h000009C4;
instrbusin[79] = 64'b0;
daddrbusout[79] = dontcare;
databusin[79] = 64'bz;
databusout[79] = dontcare;
//delay
iname[80] = "NOP";//nada
iaddrbusout[80] = 64'h00000AC8;
instrbusin[80] = 64'b0;
daddrbusout[80] = dontcare;
databusin[80] = 64'bz;
databusout[80] = dontcare;
//use ADDIS for the branch condition test B.GE test
// op, rd, rn, aluImm
iname[81] ="ADDIS,R26, R26, #001";//result in R26 = 8000000000000000
iaddrbusout[81] = 64'h00000ACC;
// opcode rm/ALUImm rn rd
instrbusin[81] ={ADDIS, 12'h001, R26, R26};
daddrbusout[81] = dontcare;
databusin[81] = 64'bz;
databusout[81] = dontcare;
//TAKE branch
// op, COND_addr, rt
iname[82] ="B_GE, #24, RX";//new branch address is B60
iaddrbusout[82] = 64'h00000AD0;
// op, COND_addr, rt
instrbusin[82] ={B_GE, 19'b0000000000000100100, RX};
daddrbusout[82] = dontcare;
databusin[82] = 64'bz;
databusout[82] = dontcare;
//delay
iname[83] = "NOP";//nada
iaddrbusout[83] = 64'h00000AD4;
instrbusin[83] = 64'b0;
daddrbusout[83] = dontcare;
databusin[83] = 64'bz;
databusout[83] = dontcare;
//delay
iname[84] = "NOP";//nada
iaddrbusout[84] = 64'h00000B60;
instrbusin[84] = 64'b0;
daddrbusout[84] = dontcare;
databusin[84] = 64'bz;
databusout[84] = dontcare;
//finishing up
iname[85] = "NOP";//nada
iaddrbusout[85] = 64'h00000B64;
instrbusin[85] = 64'b0;
daddrbusout[85] = dontcare;
databusin[85] = 64'bz;
databusout[85] = dontcare;
iname[86] = "NOP";//nada
iaddrbusout[86] = 64'h00000B68;
instrbusin[86] = 64'b0;
daddrbusout[86] = dontcare;
databusin[86] = 64'bz;
databusout[86] = dontcare;
iname[87] = "NOP";//nada
iaddrbusout[87] = 64'h00000B6C;
instrbusin[87] = 64'b0;
daddrbusout[87] = dontcare;
databusin[87] = 64'bz;
databusout[87] = dontcare;
//done with testing: 88 instructions
//bonus round
//copy of phase 3
//phase 3: testing LSL, LSR
//setting up the register R20 for a test of the LSL
// op, rd, rn, rm
iname[88] ="ADDI, R20, R31, #640";//setting up for left shift, result in R20 = 0000000000000640
iaddrbusout[88] = 64'h00000B70;
// opcode rm/ALUImm rn rd
instrbusin[88] ={ADDI, 12'h007, R31, R20};
daddrbusout[88] = dontcare;
databusin[88] = 64'bz;
databusout[88] = dontcare;
// op, rd, rn, rm
iname[89] ="ADDI, R21, R31, #480";//setting up for right shift, n flag, result in R21 = 0000000000000480
iaddrbusout[89] = 64'h00000B74;
// opcode rm/ALUImm rn rd
instrbusin[89] ={ADDI, 12'h700, R31, R21};
daddrbusout[89] = dontcare;
databusin[89] = 64'bz;
databusout[89] = dontcare;
// op, rd, rn, rm
iname[90] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[90] = 64'h00000B78;
// op, rm, shamt, rn, rd
instrbusin[90] ={AND, R31, zeroSham, R31, R19};
daddrbusout[90] = dontcare;
databusin[90] = 64'bz;
databusout[90] = dontcare;
// op, rd, rn, rm
iname[91] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[91] = 64'h00000B7C;
// op, rm, shamt, rn, rd
instrbusin[91] ={AND, R31, zeroSham, R31, R18};
daddrbusout[91] = dontcare;
databusin[91] = 64'bz;
databusout[91] = dontcare;
// op, rd, rn, rm
iname[92] ="LSL, R20, R20, #1";//testing left shift, result in R20 = 0000000000006400
iaddrbusout[92] = 64'h00000B80;
// op, rm, shamt, rn, rd
instrbusin[92] ={LSL, RX, fourShamt, R20, R20};
daddrbusout[92] = dontcare;
databusin[92] = 64'bz;
databusout[92] = dontcare;
// op, rd, rn, rm
iname[93] ="LSR, R21, R21, #1";//testing right shift, result in R21 = 0000000000000048
iaddrbusout[93] = 64'h00000B84;
// op, rm, shamt, rn, rd
instrbusin[93] ={LSR, RX, fourShamt, R21, R21};
daddrbusout[93] = dontcare;
databusin[93] = 64'bz;
databusout[93] = dontcare;
//phase 4: testing load and store
// op, rt, rn, DT_adr
iname[94] ="LDUR, R22, R31, #27";//testing load, result in R22 = 666 (from memory,databusin)
iaddrbusout[94] = 64'h00000B88;
// op, DT_ADDR, ?, rn, rt
instrbusin[94] ={LDUR, 9'b000100111, 2'b00, R31, R22};
daddrbusout[94] = 64'h0000000000000027;//used for LDUR
databusin[94] = 64'h0000000000000666;//used for LDUR
databusout[94] = dontcare;
// op, rn, DT_adr, rt
iname[95] ="STUR, R26, #21, R26";//testing store, result for databusout in R26 = 8000000000000000 (to memory)
//R20, + 21 = 6421
iaddrbusout[95] = 64'h00000B8C;
// op, DT_ADDR, ?, rn, rt
instrbusin[95] ={STUR, 9'b000100001, 2'b00, R26, R26};
daddrbusout[95] = 64'h8000000000000021;//used for STUR
databusin[95] = 64'bz;
databusout[95] = 64'h8000000000000000;//used for STUR
// op, rd, rn, rm
iname[96] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[96] = 64'h00000B90;
// op, rm, shamt, rn, rd
instrbusin[96] ={AND, R31, zeroSham, R31, R19};
daddrbusout[96] = dontcare;
databusin[96] = 64'bz;
databusout[96] = dontcare;
// op, rd, rn, rm
iname[97] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[97] = 64'h00000B94;
// op, rm, shamt, rn, rd
instrbusin[97] ={AND, R31, zeroSham, R31, R19};
daddrbusout[97] = dontcare;
databusin[97] = 64'bz;
databusout[97] = dontcare;
// op, rd, rn, rm
iname[98] ="AND, R17, R31, R31";//delay, result in R17 = 0000000000000000
iaddrbusout[98] = 64'h00000B98;
// op, rm, shamt, rn, rd
instrbusin[98] ={AND, R31, zeroSham, R31, R19};
daddrbusout[98] = dontcare;
databusin[98] = 64'bz;
databusout[98] = dontcare;
//phase 5: testing B branch
// op, BR_address
iname[99] ="B, #BEEF";//testing branch, calculated branch address should be
// (64'h? + 64'h0000000000000BEEF = 64'h?)
iaddrbusout[99] = 64'h00000B9C;
// op, BR_address
instrbusin[99] ={B, 26'b00000000001011111011101111};
daddrbusout[99] = dontcare;
databusin[99] = 64'bz;
databusout[99] = dontcare;
// op, rd, rn, rm
iname[100] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[100] = 64'h00000BA0;
// op, rm, shamt, rn, rd
instrbusin[100] ={AND, R31, zeroSham, R31, R19};
daddrbusout[100] = dontcare;
databusin[100] = 64'bz;
databusout[100] = dontcare;
// op, rd, rn, rm
iname[101] ="ADD, R20, R21, R20";//testing branch address result in R20 = 0000000000006448
iaddrbusout[101] = 64'h00030758;
// op, rm, shamt, rn, rd
instrbusin[101] ={ADD, R20, zeroSham, R21, R20};
daddrbusout[101] = dontcare;
databusin[101] = 64'bz;
databusout[101] = dontcare;
//copy of branch testing(@101)
//phase 5: testing B branch
// op, BR_address
iname[102] ="B, #1337";//testing branch, calculated branch address should be
// (64'h? + 64'h00000000000001337 = 64'h?)
iaddrbusout[102] = 64'h0003075C;
// op, BR_address
instrbusin[102] ={B, 26'b00000000000001001100110111};
daddrbusout[102] = dontcare;
databusin[102] = 64'bz;
databusout[102] = dontcare;
// op, rd, rn, rm
iname[103] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[103] = 64'h00030760;
// op, rm, shamt, rn, rd
instrbusin[103] ={AND, R31, zeroSham, R31, R19};
daddrbusout[103] = dontcare;
databusin[103] = 64'bz;
databusout[103] = dontcare;
// op, rd, rn, rm
iname[104] ="ADD, R17, R31, R31";//testing branch address result in R17 = 0000000000000000
iaddrbusout[104] = 64'h00035438;
// op, rm, shamt, rn, rd
instrbusin[104] ={ADD, R31, zeroSham, R31, R17};
daddrbusout[104] = dontcare;
databusin[104] = 64'bz;
databusout[104] = dontcare;
//phase 6: testing B.EQ and B.NE branch
// op, rd, rn, imm
iname[105] ="ADDI, R21, R31, #002";//testing addi, result in R21 = 0000000000000002
iaddrbusout[105] = 64'h0003543C;
// opcode rm/ALUImm rn rd
instrbusin[105] ={ADDI, 12'h002, R31, R21};
daddrbusout[105] = dontcare;
databusin[105] = 64'bz;
databusout[105] = dontcare;
// op, rd, rn, imm
iname[106] ="ADDI, R22, R31, #002";//testing addi, result in R22 = 0000000000000002
iaddrbusout[106] = 64'h00035440;
// opcode rm/ALUImm rn rd
instrbusin[106] ={ADDI, 12'h002, R31, R22};
daddrbusout[106] = dontcare;
databusin[106] = 64'bz;
databusout[106] = dontcare;
iname[107] = "NOP";//nada
iaddrbusout[107] = 64'h00035444;
instrbusin[107] = 64'b0;
daddrbusout[107] = dontcare;
databusin[107] = 64'bz;
databusout[107] = dontcare;
iname[108] = "NOP";//nada
iaddrbusout[108] = 64'h00035448;
instrbusin[108] = 64'b0;
daddrbusout[108] = dontcare;
databusin[108] = 64'bz;
databusout[108] = dontcare;
//TODO: find register to make this a fake branch for N bit
//SUBIS for FAKE BRANCH
// op, rd, rn, aluImm
iname[109] ="SUBIS,R31, R22, #001";//testing fake branch, this should NOT set the N high
iaddrbusout[109] = 64'h0003544C;
// opcode rm/ALUImm rn rd
instrbusin[109] ={SUBIS, 12'h001, R22, R31};
daddrbusout[109] = dontcare;
databusin[109] = 64'bz;
databusout[109] = dontcare;
//FAKE BRANCH
// op, COND_addr, rt
iname[110] ="B_EQ, #69420, RX";//testing to NOT take the branch, N should be LOW
iaddrbusout[110] = 64'h00035450;
// op, COND_addr, rt
instrbusin[110] ={B_EQ, 19'b1101001010000100000, RX};
daddrbusout[110] = dontcare;
databusin[110] = 64'bz;
databusout[110] = dontcare;
iname[111] = "NOP";//nada
iaddrbusout[111] = 64'h00035454;
instrbusin[111] = 64'b0;
daddrbusout[111] = dontcare;
databusin[111] = 64'bz;
databusout[111] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[112] ="ADDS, R31, R31, R31";//set z flag for BEQ,
iaddrbusout[112] = 64'h00035458;
// op, rm, shamt, rn, rd
instrbusin[112] ={ADDS, R31, zeroSham, R31, R31};
daddrbusout[112] = dontcare;
databusin[112] = 64'bz;
databusout[112] = dontcare;
//real branch for B.EQ (I have more of the best branches)
// op, COND_addr, rt
iname[113] ="B_EQ, #AE, RX";//take the branch to instruction count 35714
iaddrbusout[113] = 64'h0003545C;
// op, COND_addr, rt
instrbusin[113] ={B_EQ, 19'b0000000000010101110, RX};
daddrbusout[113] = dontcare;
databusin[113] = 64'bz;
databusout[113] = dontcare;
iname[114] = "NOP";//nada
iaddrbusout[114] = 64'h00035460;
instrbusin[114] = 64'b0;
daddrbusout[114] = dontcare;
databusin[114] = 64'bz;
databusout[114] = dontcare;
iname[115] = "NOP";//nada
iaddrbusout[115] = 64'h00035714;
instrbusin[115] = 64'b0;
daddrbusout[115] = dontcare;
databusin[115] = 64'bz;
databusout[115] = dontcare;
//use ADDS for branch test
// op, rd, rn, rm
iname[116] ="ADDS, R31, R21, R20";//DONT set Z bit to high
iaddrbusout[116] = 64'h00035718;
// op, rm, shamt, rn, rd
instrbusin[116] ={ADDS, R20, zeroSham, R21, R31};
daddrbusout[116] = dontcare;
databusin[116] = 64'bz;
databusout[116] = dontcare;
//test B.EQ
// op, COND_addr, rt
iname[117] ="B_EQ, #96, RX";//DONT take the branch to instruction count
iaddrbusout[117] = 64'h0003571C;
// op, COND_addr, rt
instrbusin[117] ={B_EQ, 19'b0000000000010010110, RX};
daddrbusout[117] = dontcare;
databusin[117] = 64'bz;
databusout[117] = dontcare;
iname[118] = "NOP";//nada
iaddrbusout[118] = 64'h00035720;
instrbusin[118] = 64'b0;
daddrbusout[118] = dontcare;
databusin[118] = 64'bz;
databusout[118] = dontcare;
iname[119] = "NOP";//nada
iaddrbusout[119] = 64'h00035724;
instrbusin[119] = 64'b0;
daddrbusout[119] = dontcare;
databusin[119] = 64'bz;
databusout[119] = dontcare;
//copy of move and more branch testing(@117)
//phase 8: testing MOVEZ and overflow bit
//4 instructions to set registers to 0
// op, rd, rn, rm
iname[120] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[120] = 64'h00035728;
// op, rm, shamt, rn, rd
instrbusin[120] ={AND, R31, zeroSham, R31, R19};
daddrbusout[120] = dontcare;
databusin[120] = 64'bz;
databusout[120] = dontcare;
// op, rd, rn, rm
iname[121] ="AND, R20, R31, R31";//delay, result in R20 = 0000000000000000
iaddrbusout[121] = 64'h0003572C;
// op, rm, shamt, rn, rd
instrbusin[121] ={AND, R31, zeroSham, R31, R20};
daddrbusout[121] = dontcare;
databusin[121] = 64'bz;
databusout[121] = dontcare;
// op, rd, rn, rm
iname[122] ="AND, R21, R31, R31";//delay, result in R21 = 0000000000000000
iaddrbusout[122] = 64'h00035730;
// op, rm, shamt, rn, rd
instrbusin[122] ={AND, R31, zeroSham, R31, R21};
daddrbusout[122] = dontcare;
databusin[122] = 64'bz;
databusout[122] = dontcare;
// op, rd, rn, rm
iname[123] ="AND, R22, R31, R31";//delay, result in R22 = 0000000000000000
iaddrbusout[123] = 64'h00035734;
// op, rm, shamt, rn, rd
instrbusin[123] ={AND, R31, zeroSham, R31, R22};
daddrbusout[123] = dontcare;
databusin[123] = 64'bz;
databusout[123] = dontcare;
//4 MOVZ commands
//move 0 amt
// op, move_amt, MOV_imm, rd
iname[124] ="MOVZ, move_0, #FFFF, R19";//testing move, result in R19 = 000000000000FFFF
iaddrbusout[124] = 64'h00035738;
// op, move_amt, MOV_imm, rd
instrbusin[124] ={MOVZ, move_0, 16'hFFFF, R19};
daddrbusout[124] = dontcare;
databusin[124] = 64'bz;
databusout[124] = dontcare;
//move 1 amt
// op, move_amt, MOV_imm, rd
iname[125] ="MOVZ, move_1, #FFFF, R20";//testing move, result in R20 = 00000000FFFF0000
iaddrbusout[125] = 64'h0003573C;
// op, move_amt, MOV_imm, rd
instrbusin[125] ={MOVZ, move_1, 16'hFFFF, R20};
daddrbusout[125] = dontcare;
databusin[125] = 64'bz;
databusout[125] = dontcare;
//move 2 amt
// op, move_amt, MOV_imm, rd
iname[126] ="MOVZ, move_2, #FFFF, R21";//testing move, result in R21 = 0000FFFF00000000
iaddrbusout[126] = 64'h00035740;
// op, move_amt, MOV_imm, rd
instrbusin[126] ={MOVZ, move_2, 16'hFFFF, R21};
daddrbusout[126] = dontcare;
databusin[126] = 64'bz;
databusout[126] = dontcare;
//move 3 amt
// op, move_amt, MOV_imm, rd
iname[127] ="MOVZ, move_3, #6FFF, R22";//testing move, result in R22 = 6FFF000000000000
iaddrbusout[127] = 64'h00035744;
// op, move_amt, MOV_imm, rd
instrbusin[127] ={MOVZ, move_3, 16'h6FFF, R22};
daddrbusout[127] = dontcare;
databusin[127] = 64'bz;
databusout[127] = dontcare;
//have or for move 0 and move 1
// op, rd, rn, rm
iname[128] ="ORR, R23, R19, R20";//testing xor, result in R23 = 00000000FFFFFFFF
iaddrbusout[128] = 64'h00035748;
// op, rm, shamt, rn, rd
instrbusin[128] ={ORR, R20, zeroSham, R19, R23};
daddrbusout[128] = dontcare;
databusin[128] = 64'bz;
databusout[128] = dontcare;
//delay
iname[129] = "NOP";//nada
iaddrbusout[129] = 64'h0003574C;
instrbusin[129] = 64'b0;
daddrbusout[129] = dontcare;
databusin[129] = 64'bz;
databusout[129] = dontcare;
//have or for move 2 and move 3
// op, rd, rn, rm
iname[130] ="ORR, R24, R21, R22";//testing xor, result in R27 = 6FFFFFFF00000000
iaddrbusout[130] = 64'h00035750;
// op, rm, shamt, rn, rd
instrbusin[130] ={ORR, R22, zeroSham, R21, R24};
daddrbusout[130] = dontcare;
databusin[130] = 64'bz;
databusout[130] = dontcare;
//delay
iname[131] = "NOP";//nada
iaddrbusout[131] = 64'h00035754;
instrbusin[131] = 64'b0;
daddrbusout[131] = dontcare;
databusin[131] = 64'bz;
databusout[131] = dontcare;
//delay
iname[132] = "NOP";//nada
iaddrbusout[132] = 64'h00035758;
instrbusin[132] = 64'b0;
daddrbusout[132] = dontcare;
databusin[132] = 64'bz;
databusout[132] = dontcare;
//have or for move(0|1) and move(2|3)
// op, rd, rn, rm
iname[133] ="ORR, R25, R23, R24";//testing or, result in R25 = 6FFFFFFFFFFFFFFF
iaddrbusout[133] = 64'h0003575C;
// op, rm, shamt, rn, rd
instrbusin[133] ={ORR, R24, zeroSham, R23, R25};
daddrbusout[133] = dontcare;
databusin[133] = 64'bz;
databusout[133] = dontcare;
//dealy
iname[134] = "NOP";//nada
iaddrbusout[134] = 64'h00035760;
instrbusin[134] = 64'b0;
daddrbusout[134] = dontcare;
databusin[134] = 64'bz;
databusout[134] = dontcare;
//delay
iname[135] = "NOP";//nada
iaddrbusout[135] = 64'h00035764;
instrbusin[135] = 64'b0;
daddrbusout[135] = dontcare;
databusin[135] = 64'bz;
databusout[135] = dontcare;
//addis command to NOT trigger the V bit
// op, rd, rn, aluImm
iname[136] ="ADDIS,R26, R25, #001";//for not V bit set, result in R26 = 7000000000000000
iaddrbusout[136] = 64'h00035768;
// opcode rm/ALUImm rn rd
instrbusin[136] ={ADDIS, 12'h001, R25, R26};
daddrbusout[136] = dontcare;
databusin[136] = 64'bz;
databusout[136] = dontcare;
iname[137] = "NOP";//nada
iaddrbusout[137] = 64'h0003576C;
instrbusin[137] = 64'b0;
daddrbusout[137] = dontcare;
databusin[137] = 64'bz;
databusout[137] = dontcare;
iname[138] = "NOP";//nada
iaddrbusout[138] = 64'h00035770;
instrbusin[138] = 64'b0;
daddrbusout[138] = dontcare;
databusin[138] = 64'bz;
databusout[138] = dontcare;
//phase 9: testing B.LT and B.GE branch
//7FFF+1 = N and V, 8000-1 = V
//use SUBIS for the branch condition test (B.LT test)
//DONT take branch
// op, rd, rn, aluImm
iname[139] ="SUBIS,R26, R26, #001";//result in R26 = 6FFFFFFFFFFFFFFF
iaddrbusout[139] = 64'h00035774;
// opcode rm/ALUImm rn rd
instrbusin[139] ={SUBIS, 12'h001, R26, R26};
daddrbusout[139] = dontcare;
databusin[139] = 64'bz;
databusout[139] = dontcare;
//NOT TAKE branch
// op, COND_addr, rt
iname[140] ="B_LT, #42, RX";//new branch address is
iaddrbusout[140] = 64'h00035778;
// op, COND_addr, rt
instrbusin[140] ={B_LT, 19'b0000000000001000010, RX};
daddrbusout[140] = dontcare;
databusin[140] = 64'bz;
databusout[140] = dontcare;
//delay
iname[141] = "NOP";//nada
iaddrbusout[141] = 64'h0003577C;
instrbusin[141] = 64'b0;
daddrbusout[141] = dontcare;
databusin[141] = 64'bz;
databusout[141] = dontcare;
//delay
iname[142] = "NOP";//nada
iaddrbusout[142] = 64'h00035780;
instrbusin[142] = 64'b0;
daddrbusout[142] = dontcare;
databusin[142] = 64'bz;
databusout[142] = dontcare;
//use ADDIS for the branch condition test B.GE test
// op, rd, rn, aluImm
iname[143] ="ADDIS,R26, R26, #001";//result in R26 = 7000000000000000
iaddrbusout[143] = 64'h00035784;
// opcode rm/ALUImm rn rd
instrbusin[143] ={ADDIS, 12'h001, R26, R26};
daddrbusout[143] = dontcare;
databusin[143] = 64'bz;
databusout[143] = dontcare;
//NOT TAKE branch
// op, COND_addr, rt
iname[144] ="B_LT, #24, RX";//new branch address is B60
iaddrbusout[144] = 64'h00035788;
// op, COND_addr, rt
instrbusin[144] ={B_LT, 19'b0000000000000100100, RX};
daddrbusout[144] = dontcare;
databusin[144] = 64'bz;
databusout[144] = dontcare;
//delay
iname[145] = "NOP";//nada
iaddrbusout[145] = 64'h0003578C;
instrbusin[145] = 64'b0;
daddrbusout[145] = dontcare;
databusin[145] = 64'bz;
databusout[145] = dontcare;
//delay
iname[146] = "NOP";//nada
iaddrbusout[146] = 64'h00035790;
instrbusin[146] = 64'b0;
daddrbusout[146] = dontcare;
databusin[146] = 64'bz;
databusout[146] = dontcare;
//finishing up
iname[147] = "NOP";//nada
iaddrbusout[147] = 64'h00035794;
instrbusin[147] = 64'b0;
daddrbusout[147] = dontcare;
databusin[147] = 64'bz;
databusout[147] = dontcare;
iname[148] = "NOP";//nada
iaddrbusout[148] = 64'h00035798;
instrbusin[148] = 64'b0;
daddrbusout[148] = dontcare;
databusin[148] = 64'bz;
databusout[148] = dontcare;
iname[149] = "NOP";//nada
iaddrbusout[149] = 64'h0003579C;
instrbusin[149] = 64'b0;
daddrbusout[149] = dontcare;
databusin[149] = 64'bz;
databusout[149] = dontcare;
//Random(@147)//TODO: test what the registers actually are
// op, rd, rn, rm
iname[150] ="ORRI, R21, R24, #AAA";//testing ori, result in R21 = 0000000000000001//TODO
iaddrbusout[150] = 64'h000357A0;
// opcode rm/ALUImm rn rd
instrbusin[150] ={ORRI, 12'h001, R24, R21};
daddrbusout[150] = dontcare;
databusin[150] = 64'bz;
databusout[150] = dontcare;
// op, rd, rn, rm
iname[151] ="EORI, R22, R20, #CCC";//testing xori, result in R22 = 0000000000000AAA//TODO
iaddrbusout[151] = 64'h000357A4;
// opcode rm/ALUImm rn rd
instrbusin[151] ={EORI, 12'h000, R20, R22};
daddrbusout[151] = dontcare;
databusin[151] = 64'bz;
databusout[151] = dontcare;
// op, rd, rn, rm
iname[152] ="ANDI, R23, R0, #321";//testing andi, result in R23 = 0000000000000002//TODO
iaddrbusout[152] = 64'h000357A8;
// opcode rm/ALUImm rn rd
instrbusin[152] ={ANDI, 12'h003, R0, R23};
daddrbusout[152] = dontcare;
databusin[152] = 64'bz;
databusout[152] = dontcare;
// op, rd, rn, rm
iname[153] ="SUBI, R24, R20, #123";//testing subi, result in R24 = 0000000000000AA0//TODO
iaddrbusout[153] = 64'h000357AC;
// opcode rm/ALUImm rn rd
instrbusin[153] ={SUBI, 12'h00A, R20, R24};
daddrbusout[153] = dontcare;
databusin[153] = 64'bz;
databusout[153] = dontcare;
//delay
iname[154] = "NOP";//nada
iaddrbusout[154] = 64'h000357B0;
instrbusin[154] = 64'b0;
daddrbusout[154] = dontcare;
databusin[154] = 64'bz;
databusout[154] = dontcare;
//delay
iname[155] = "NOP";//nada
iaddrbusout[155] = 64'h000357B4;
instrbusin[155] = 64'b0;
daddrbusout[155] = dontcare;
databusin[155] = 64'bz;
databusout[155] = dontcare;
//finishing up
iname[156] = "NOP";//nada
iaddrbusout[156] = 64'h000357B8;
instrbusin[156] = 64'b0;
daddrbusout[156] = dontcare;
databusin[156] = 64'bz;
databusout[156] = dontcare;
//Done. 157 instructions
//this number will be inacurate for a while(the number below)
//also remember to set k down below to ntests - 1
// (no. instructions) + (no. loads) + 2*(no. stores) = 35 + 2 + 2*7 = 51
ntests = 157;//?
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
assign databus = clkd ? 64'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
databusk = 64'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 156; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set load data for 3rd previous instruction
if (k >=3)
databusk = databusin[k-3];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check data address from 3rd previous instruction
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check store data from 3rd previous instruction
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Tue Jan 22 07:33:04 EST 2013
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// wsiS1_SThreadBusy O 1
// wsiS1_SReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 64 reg
// wsiM0_MByteEn O 8 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// wsiM1_MCmd O 3
// wsiM1_MReqLast O 1
// wsiM1_MBurstPrecise O 1
// wsiM1_MBurstLength O 12
// wsiM1_MData O 64 reg
// wsiM1_MByteEn O 8 reg
// wsiM1_MReqInfo O 8
// wsiM1_MReset_n O 1
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 32
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 64
// wsiS0_MByteEn I 8
// wsiS0_MReqInfo I 8
// wsiS1_MCmd I 3
// wsiS1_MBurstLength I 12
// wsiS1_MData I 64
// wsiS1_MByteEn I 8
// wsiS1_MReqInfo I 8
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
// wsiS1_MReqLast I 1
// wsiS1_MBurstPrecise I 1
// wsiS1_MReset_n I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
// wsiM1_SThreadBusy I 1 reg
// wsiM1_SReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkWsiSplitter2x28B(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n,
wsiS1_MCmd,
wsiS1_MReqLast,
wsiS1_MBurstPrecise,
wsiS1_MBurstLength,
wsiS1_MData,
wsiS1_MByteEn,
wsiS1_MReqInfo,
wsiS1_SThreadBusy,
wsiS1_SReset_n,
wsiS1_MReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n,
wsiM1_MCmd,
wsiM1_MReqLast,
wsiM1_MBurstPrecise,
wsiM1_MBurstLength,
wsiM1_MData,
wsiM1_MByteEn,
wsiM1_MReqInfo,
wsiM1_SThreadBusy,
wsiM1_MReset_n,
wsiM1_SReset_n);
parameter [31 : 0] ctrlInit = 32'b0;
parameter [0 : 0] hasDebugLogic = 1'b0;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [31 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [63 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [7 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// action method wsiS1_mCmd
input [2 : 0] wsiS1_MCmd;
// action method wsiS1_mReqLast
input wsiS1_MReqLast;
// action method wsiS1_mBurstPrecise
input wsiS1_MBurstPrecise;
// action method wsiS1_mBurstLength
input [11 : 0] wsiS1_MBurstLength;
// action method wsiS1_mData
input [63 : 0] wsiS1_MData;
// action method wsiS1_mByteEn
input [7 : 0] wsiS1_MByteEn;
// action method wsiS1_mReqInfo
input [7 : 0] wsiS1_MReqInfo;
// action method wsiS1_mDataInfo
// value method wsiS1_sThreadBusy
output wsiS1_SThreadBusy;
// value method wsiS1_sReset_n
output wsiS1_SReset_n;
// action method wsiS1_mReset_n
input wsiS1_MReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [63 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [7 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// value method wsiM1_mCmd
output [2 : 0] wsiM1_MCmd;
// value method wsiM1_mReqLast
output wsiM1_MReqLast;
// value method wsiM1_mBurstPrecise
output wsiM1_MBurstPrecise;
// value method wsiM1_mBurstLength
output [11 : 0] wsiM1_MBurstLength;
// value method wsiM1_mData
output [63 : 0] wsiM1_MData;
// value method wsiM1_mByteEn
output [7 : 0] wsiM1_MByteEn;
// value method wsiM1_mReqInfo
output [7 : 0] wsiM1_MReqInfo;
// value method wsiM1_mDataInfo
// action method wsiM1_sThreadBusy
input wsiM1_SThreadBusy;
// value method wsiM1_mReset_n
output wsiM1_MReset_n;
// action method wsiM1_sReset_n
input wsiM1_SReset_n;
// signals for module outputs
wire [63 : 0] wsiM0_MData, wsiM1_MData;
wire [31 : 0] wciS0_SData;
wire [11 : 0] wsiM0_MBurstLength, wsiM1_MBurstLength;
wire [7 : 0] wsiM0_MByteEn, wsiM0_MReqInfo, wsiM1_MByteEn, wsiM1_MReqInfo;
wire [2 : 0] wsiM0_MCmd, wsiM1_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiM1_MBurstPrecise,
wsiM1_MReqLast,
wsiM1_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy,
wsiS1_SReset_n,
wsiS1_SThreadBusy;
// inlined wires
wire [96 : 0] wsi_M0_reqFifo_x_wire$wget,
wsi_M1_reqFifo_x_wire$wget,
wsi_S0_wsiReq$wget,
wsi_S1_wsiReq$wget;
wire [95 : 0] wsi_M0_extStatusW$wget,
wsi_M1_extStatusW$wget,
wsi_S0_extStatusW$wget,
wsi_S1_extStatusW$wget;
wire [71 : 0] wci_wciReq$wget;
wire [63 : 0] wsi_Es0_mData_w$wget, wsi_Es1_mData_w$wget;
wire [33 : 0] wci_respF_x_wire$wget;
wire [31 : 0] wci_Es_mAddr_w$wget, wci_Es_mData_w$wget;
wire [11 : 0] wsi_Es0_mBurstLength_w$wget, wsi_Es1_mBurstLength_w$wget;
wire [7 : 0] wsi_Es0_mByteEn_w$wget,
wsi_Es0_mReqInfo_w$wget,
wsi_Es1_mByteEn_w$wget,
wsi_Es1_mReqInfo_w$wget;
wire [3 : 0] wci_Es_mByteEn_w$wget;
wire [2 : 0] wci_Es_mCmd_w$wget,
wci_wEdge$wget,
wsi_Es0_mCmd_w$wget,
wsi_Es1_mCmd_w$wget;
wire wci_Es_mAddrSpace_w$wget,
wci_Es_mAddrSpace_w$whas,
wci_Es_mAddr_w$whas,
wci_Es_mByteEn_w$whas,
wci_Es_mCmd_w$whas,
wci_Es_mData_w$whas,
wci_ctlAckReg_1$wget,
wci_ctlAckReg_1$whas,
wci_reqF_r_clr$whas,
wci_reqF_r_deq$whas,
wci_reqF_r_enq$whas,
wci_respF_dequeueing$whas,
wci_respF_enqueueing$whas,
wci_respF_x_wire$whas,
wci_sFlagReg_1$wget,
wci_sFlagReg_1$whas,
wci_sThreadBusy_pw$whas,
wci_wEdge$whas,
wci_wciReq$whas,
wci_wci_cfrd_pw$whas,
wci_wci_cfwr_pw$whas,
wci_wci_ctrl_pw$whas,
wsi_Es0_mBurstLength_w$whas,
wsi_Es0_mBurstPrecise_w$whas,
wsi_Es0_mByteEn_w$whas,
wsi_Es0_mCmd_w$whas,
wsi_Es0_mDataInfo_w$whas,
wsi_Es0_mData_w$whas,
wsi_Es0_mReqInfo_w$whas,
wsi_Es0_mReqLast_w$whas,
wsi_Es1_mBurstLength_w$whas,
wsi_Es1_mBurstPrecise_w$whas,
wsi_Es1_mByteEn_w$whas,
wsi_Es1_mCmd_w$whas,
wsi_Es1_mDataInfo_w$whas,
wsi_Es1_mData_w$whas,
wsi_Es1_mReqInfo_w$whas,
wsi_Es1_mReqLast_w$whas,
wsi_M0_operateD_1$wget,
wsi_M0_operateD_1$whas,
wsi_M0_peerIsReady_1$wget,
wsi_M0_peerIsReady_1$whas,
wsi_M0_reqFifo_dequeueing$whas,
wsi_M0_reqFifo_enqueueing$whas,
wsi_M0_reqFifo_x_wire$whas,
wsi_M0_sThreadBusy_pw$whas,
wsi_M1_operateD_1$wget,
wsi_M1_operateD_1$whas,
wsi_M1_peerIsReady_1$wget,
wsi_M1_peerIsReady_1$whas,
wsi_M1_reqFifo_dequeueing$whas,
wsi_M1_reqFifo_enqueueing$whas,
wsi_M1_reqFifo_x_wire$whas,
wsi_M1_sThreadBusy_pw$whas,
wsi_S0_operateD_1$wget,
wsi_S0_operateD_1$whas,
wsi_S0_peerIsReady_1$wget,
wsi_S0_peerIsReady_1$whas,
wsi_S0_reqFifo_doResetClr$whas,
wsi_S0_reqFifo_doResetDeq$whas,
wsi_S0_reqFifo_doResetEnq$whas,
wsi_S0_reqFifo_r_clr$whas,
wsi_S0_reqFifo_r_deq$whas,
wsi_S0_reqFifo_r_enq$whas,
wsi_S0_sThreadBusy_dw$wget,
wsi_S0_sThreadBusy_dw$whas,
wsi_S0_wsiReq$whas,
wsi_S1_operateD_1$wget,
wsi_S1_operateD_1$whas,
wsi_S1_peerIsReady_1$wget,
wsi_S1_peerIsReady_1$whas,
wsi_S1_reqFifo_doResetClr$whas,
wsi_S1_reqFifo_doResetDeq$whas,
wsi_S1_reqFifo_doResetEnq$whas,
wsi_S1_reqFifo_r_clr$whas,
wsi_S1_reqFifo_r_deq$whas,
wsi_S1_reqFifo_r_enq$whas,
wsi_S1_sThreadBusy_dw$wget,
wsi_S1_sThreadBusy_dw$whas,
wsi_S1_wsiReq$whas;
// register splitCtrl
reg [31 : 0] splitCtrl;
wire [31 : 0] splitCtrl$D_IN;
wire splitCtrl$EN;
// register wci_cEdge
reg [2 : 0] wci_cEdge;
wire [2 : 0] wci_cEdge$D_IN;
wire wci_cEdge$EN;
// register wci_cState
reg [2 : 0] wci_cState;
wire [2 : 0] wci_cState$D_IN;
wire wci_cState$EN;
// register wci_ctlAckReg
reg wci_ctlAckReg;
wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN;
// register wci_ctlOpActive
reg wci_ctlOpActive;
wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN;
// register wci_illegalEdge
reg wci_illegalEdge;
wire wci_illegalEdge$D_IN, wci_illegalEdge$EN;
// register wci_isReset_isInReset
reg wci_isReset_isInReset;
wire wci_isReset_isInReset$D_IN, wci_isReset_isInReset$EN;
// register wci_nState
reg [2 : 0] wci_nState;
reg [2 : 0] wci_nState$D_IN;
wire wci_nState$EN;
// register wci_reqF_countReg
reg [1 : 0] wci_reqF_countReg;
wire [1 : 0] wci_reqF_countReg$D_IN;
wire wci_reqF_countReg$EN;
// register wci_respF_c_r
reg [1 : 0] wci_respF_c_r;
wire [1 : 0] wci_respF_c_r$D_IN;
wire wci_respF_c_r$EN;
// register wci_respF_q_0
reg [33 : 0] wci_respF_q_0;
reg [33 : 0] wci_respF_q_0$D_IN;
wire wci_respF_q_0$EN;
// register wci_respF_q_1
reg [33 : 0] wci_respF_q_1;
reg [33 : 0] wci_respF_q_1$D_IN;
wire wci_respF_q_1$EN;
// register wci_sFlagReg
reg wci_sFlagReg;
wire wci_sFlagReg$D_IN, wci_sFlagReg$EN;
// register wci_sThreadBusy_d
reg wci_sThreadBusy_d;
wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN;
// register wsi_M0_burstKind
reg [1 : 0] wsi_M0_burstKind;
wire [1 : 0] wsi_M0_burstKind$D_IN;
wire wsi_M0_burstKind$EN;
// register wsi_M0_errorSticky
reg wsi_M0_errorSticky;
wire wsi_M0_errorSticky$D_IN, wsi_M0_errorSticky$EN;
// register wsi_M0_iMesgCount
reg [31 : 0] wsi_M0_iMesgCount;
wire [31 : 0] wsi_M0_iMesgCount$D_IN;
wire wsi_M0_iMesgCount$EN;
// register wsi_M0_isReset_isInReset
reg wsi_M0_isReset_isInReset;
wire wsi_M0_isReset_isInReset$D_IN, wsi_M0_isReset_isInReset$EN;
// register wsi_M0_operateD
reg wsi_M0_operateD;
wire wsi_M0_operateD$D_IN, wsi_M0_operateD$EN;
// register wsi_M0_pMesgCount
reg [31 : 0] wsi_M0_pMesgCount;
wire [31 : 0] wsi_M0_pMesgCount$D_IN;
wire wsi_M0_pMesgCount$EN;
// register wsi_M0_peerIsReady
reg wsi_M0_peerIsReady;
wire wsi_M0_peerIsReady$D_IN, wsi_M0_peerIsReady$EN;
// register wsi_M0_reqFifo_c_r
reg [1 : 0] wsi_M0_reqFifo_c_r;
wire [1 : 0] wsi_M0_reqFifo_c_r$D_IN;
wire wsi_M0_reqFifo_c_r$EN;
// register wsi_M0_reqFifo_q_0
reg [96 : 0] wsi_M0_reqFifo_q_0;
reg [96 : 0] wsi_M0_reqFifo_q_0$D_IN;
wire wsi_M0_reqFifo_q_0$EN;
// register wsi_M0_reqFifo_q_1
reg [96 : 0] wsi_M0_reqFifo_q_1;
reg [96 : 0] wsi_M0_reqFifo_q_1$D_IN;
wire wsi_M0_reqFifo_q_1$EN;
// register wsi_M0_sThreadBusy_d
reg wsi_M0_sThreadBusy_d;
wire wsi_M0_sThreadBusy_d$D_IN, wsi_M0_sThreadBusy_d$EN;
// register wsi_M0_statusR
reg [7 : 0] wsi_M0_statusR;
wire [7 : 0] wsi_M0_statusR$D_IN;
wire wsi_M0_statusR$EN;
// register wsi_M0_tBusyCount
reg [31 : 0] wsi_M0_tBusyCount;
wire [31 : 0] wsi_M0_tBusyCount$D_IN;
wire wsi_M0_tBusyCount$EN;
// register wsi_M0_trafficSticky
reg wsi_M0_trafficSticky;
wire wsi_M0_trafficSticky$D_IN, wsi_M0_trafficSticky$EN;
// register wsi_M1_burstKind
reg [1 : 0] wsi_M1_burstKind;
wire [1 : 0] wsi_M1_burstKind$D_IN;
wire wsi_M1_burstKind$EN;
// register wsi_M1_errorSticky
reg wsi_M1_errorSticky;
wire wsi_M1_errorSticky$D_IN, wsi_M1_errorSticky$EN;
// register wsi_M1_iMesgCount
reg [31 : 0] wsi_M1_iMesgCount;
wire [31 : 0] wsi_M1_iMesgCount$D_IN;
wire wsi_M1_iMesgCount$EN;
// register wsi_M1_isReset_isInReset
reg wsi_M1_isReset_isInReset;
wire wsi_M1_isReset_isInReset$D_IN, wsi_M1_isReset_isInReset$EN;
// register wsi_M1_operateD
reg wsi_M1_operateD;
wire wsi_M1_operateD$D_IN, wsi_M1_operateD$EN;
// register wsi_M1_pMesgCount
reg [31 : 0] wsi_M1_pMesgCount;
wire [31 : 0] wsi_M1_pMesgCount$D_IN;
wire wsi_M1_pMesgCount$EN;
// register wsi_M1_peerIsReady
reg wsi_M1_peerIsReady;
wire wsi_M1_peerIsReady$D_IN, wsi_M1_peerIsReady$EN;
// register wsi_M1_reqFifo_c_r
reg [1 : 0] wsi_M1_reqFifo_c_r;
wire [1 : 0] wsi_M1_reqFifo_c_r$D_IN;
wire wsi_M1_reqFifo_c_r$EN;
// register wsi_M1_reqFifo_q_0
reg [96 : 0] wsi_M1_reqFifo_q_0;
reg [96 : 0] wsi_M1_reqFifo_q_0$D_IN;
wire wsi_M1_reqFifo_q_0$EN;
// register wsi_M1_reqFifo_q_1
reg [96 : 0] wsi_M1_reqFifo_q_1;
reg [96 : 0] wsi_M1_reqFifo_q_1$D_IN;
wire wsi_M1_reqFifo_q_1$EN;
// register wsi_M1_sThreadBusy_d
reg wsi_M1_sThreadBusy_d;
wire wsi_M1_sThreadBusy_d$D_IN, wsi_M1_sThreadBusy_d$EN;
// register wsi_M1_statusR
reg [7 : 0] wsi_M1_statusR;
wire [7 : 0] wsi_M1_statusR$D_IN;
wire wsi_M1_statusR$EN;
// register wsi_M1_tBusyCount
reg [31 : 0] wsi_M1_tBusyCount;
wire [31 : 0] wsi_M1_tBusyCount$D_IN;
wire wsi_M1_tBusyCount$EN;
// register wsi_M1_trafficSticky
reg wsi_M1_trafficSticky;
wire wsi_M1_trafficSticky$D_IN, wsi_M1_trafficSticky$EN;
// register wsi_S0_burstKind
reg [1 : 0] wsi_S0_burstKind;
wire [1 : 0] wsi_S0_burstKind$D_IN;
wire wsi_S0_burstKind$EN;
// register wsi_S0_errorSticky
reg wsi_S0_errorSticky;
wire wsi_S0_errorSticky$D_IN, wsi_S0_errorSticky$EN;
// register wsi_S0_iMesgCount
reg [31 : 0] wsi_S0_iMesgCount;
wire [31 : 0] wsi_S0_iMesgCount$D_IN;
wire wsi_S0_iMesgCount$EN;
// register wsi_S0_isReset_isInReset
reg wsi_S0_isReset_isInReset;
wire wsi_S0_isReset_isInReset$D_IN, wsi_S0_isReset_isInReset$EN;
// register wsi_S0_mesgWordLength
reg [11 : 0] wsi_S0_mesgWordLength;
wire [11 : 0] wsi_S0_mesgWordLength$D_IN;
wire wsi_S0_mesgWordLength$EN;
// register wsi_S0_operateD
reg wsi_S0_operateD;
wire wsi_S0_operateD$D_IN, wsi_S0_operateD$EN;
// register wsi_S0_pMesgCount
reg [31 : 0] wsi_S0_pMesgCount;
wire [31 : 0] wsi_S0_pMesgCount$D_IN;
wire wsi_S0_pMesgCount$EN;
// register wsi_S0_peerIsReady
reg wsi_S0_peerIsReady;
wire wsi_S0_peerIsReady$D_IN, wsi_S0_peerIsReady$EN;
// register wsi_S0_reqFifo_countReg
reg [1 : 0] wsi_S0_reqFifo_countReg;
wire [1 : 0] wsi_S0_reqFifo_countReg$D_IN;
wire wsi_S0_reqFifo_countReg$EN;
// register wsi_S0_reqFifo_levelsValid
reg wsi_S0_reqFifo_levelsValid;
wire wsi_S0_reqFifo_levelsValid$D_IN, wsi_S0_reqFifo_levelsValid$EN;
// register wsi_S0_statusR
reg [7 : 0] wsi_S0_statusR;
wire [7 : 0] wsi_S0_statusR$D_IN;
wire wsi_S0_statusR$EN;
// register wsi_S0_tBusyCount
reg [31 : 0] wsi_S0_tBusyCount;
wire [31 : 0] wsi_S0_tBusyCount$D_IN;
wire wsi_S0_tBusyCount$EN;
// register wsi_S0_trafficSticky
reg wsi_S0_trafficSticky;
wire wsi_S0_trafficSticky$D_IN, wsi_S0_trafficSticky$EN;
// register wsi_S0_wordCount
reg [11 : 0] wsi_S0_wordCount;
wire [11 : 0] wsi_S0_wordCount$D_IN;
wire wsi_S0_wordCount$EN;
// register wsi_S1_burstKind
reg [1 : 0] wsi_S1_burstKind;
wire [1 : 0] wsi_S1_burstKind$D_IN;
wire wsi_S1_burstKind$EN;
// register wsi_S1_errorSticky
reg wsi_S1_errorSticky;
wire wsi_S1_errorSticky$D_IN, wsi_S1_errorSticky$EN;
// register wsi_S1_iMesgCount
reg [31 : 0] wsi_S1_iMesgCount;
wire [31 : 0] wsi_S1_iMesgCount$D_IN;
wire wsi_S1_iMesgCount$EN;
// register wsi_S1_isReset_isInReset
reg wsi_S1_isReset_isInReset;
wire wsi_S1_isReset_isInReset$D_IN, wsi_S1_isReset_isInReset$EN;
// register wsi_S1_mesgWordLength
reg [11 : 0] wsi_S1_mesgWordLength;
wire [11 : 0] wsi_S1_mesgWordLength$D_IN;
wire wsi_S1_mesgWordLength$EN;
// register wsi_S1_operateD
reg wsi_S1_operateD;
wire wsi_S1_operateD$D_IN, wsi_S1_operateD$EN;
// register wsi_S1_pMesgCount
reg [31 : 0] wsi_S1_pMesgCount;
wire [31 : 0] wsi_S1_pMesgCount$D_IN;
wire wsi_S1_pMesgCount$EN;
// register wsi_S1_peerIsReady
reg wsi_S1_peerIsReady;
wire wsi_S1_peerIsReady$D_IN, wsi_S1_peerIsReady$EN;
// register wsi_S1_reqFifo_countReg
reg [1 : 0] wsi_S1_reqFifo_countReg;
wire [1 : 0] wsi_S1_reqFifo_countReg$D_IN;
wire wsi_S1_reqFifo_countReg$EN;
// register wsi_S1_reqFifo_levelsValid
reg wsi_S1_reqFifo_levelsValid;
wire wsi_S1_reqFifo_levelsValid$D_IN, wsi_S1_reqFifo_levelsValid$EN;
// register wsi_S1_statusR
reg [7 : 0] wsi_S1_statusR;
wire [7 : 0] wsi_S1_statusR$D_IN;
wire wsi_S1_statusR$EN;
// register wsi_S1_tBusyCount
reg [31 : 0] wsi_S1_tBusyCount;
wire [31 : 0] wsi_S1_tBusyCount$D_IN;
wire wsi_S1_tBusyCount$EN;
// register wsi_S1_trafficSticky
reg wsi_S1_trafficSticky;
wire wsi_S1_trafficSticky$D_IN, wsi_S1_trafficSticky$EN;
// register wsi_S1_wordCount
reg [11 : 0] wsi_S1_wordCount;
wire [11 : 0] wsi_S1_wordCount$D_IN;
wire wsi_S1_wordCount$EN;
// ports of submodule wci_reqF
wire [71 : 0] wci_reqF$D_IN, wci_reqF$D_OUT;
wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ;
// ports of submodule wsi_S0_reqFifo
wire [96 : 0] wsi_S0_reqFifo$D_IN, wsi_S0_reqFifo$D_OUT;
wire wsi_S0_reqFifo$CLR,
wsi_S0_reqFifo$DEQ,
wsi_S0_reqFifo$EMPTY_N,
wsi_S0_reqFifo$ENQ,
wsi_S0_reqFifo$FULL_N;
// ports of submodule wsi_S1_reqFifo
wire [96 : 0] wsi_S1_reqFifo$D_IN, wsi_S1_reqFifo$D_OUT;
wire wsi_S1_reqFifo$CLR,
wsi_S1_reqFifo$DEQ,
wsi_S1_reqFifo$EMPTY_N,
wsi_S1_reqFifo$ENQ,
wsi_S1_reqFifo$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_doMessageConsume_S1,
WILL_FIRE_RL_doMessageConsume_S0,
WILL_FIRE_RL_doMessageConsume_S1,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctl_op_complete,
WILL_FIRE_RL_wci_ctl_op_start,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_respF_both,
WILL_FIRE_RL_wci_respF_decCtr,
WILL_FIRE_RL_wci_respF_incCtr,
WILL_FIRE_RL_wsi_M0_reqFifo_both,
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr,
WILL_FIRE_RL_wsi_M0_reqFifo_deq,
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr,
WILL_FIRE_RL_wsi_M1_reqFifo_both,
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr,
WILL_FIRE_RL_wsi_M1_reqFifo_deq,
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr,
WILL_FIRE_RL_wsi_S0_reqFifo_enq,
WILL_FIRE_RL_wsi_S0_reqFifo_reset,
WILL_FIRE_RL_wsi_S1_reqFifo_enq,
WILL_FIRE_RL_wsi_S1_reqFifo_reset;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2;
wire [96 : 0] MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1,
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2,
MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1,
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1,
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2,
MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1;
wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1,
MUX_wci_respF_q_1$write_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_2;
wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1,
MUX_wci_respF_c_r$write_1__VAL_2,
MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1,
MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2,
MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1,
MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2;
wire MUX_wci_illegalEdge$write_1__SEL_1,
MUX_wci_illegalEdge$write_1__VAL_1,
MUX_wci_respF_q_0$write_1__SEL_2,
MUX_wci_respF_q_1$write_1__SEL_2,
MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2,
MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2,
MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1,
MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2,
MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2,
MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1;
// remaining internal signals
reg [63 : 0] v__h16289, v__h16444, v__h3698, v__h3873, v__h4017;
reg [31 : 0] _theResult____h16428;
wire [31 : 0] rdat__h16512,
rdat__h16701,
rdat__h16715,
rdat__h16723,
rdat__h16737,
rdat__h16745,
rdat__h16759,
rdat__h16767,
rdat__h16781;
// value method wciS0_sResp
assign wciS0_SResp = wci_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_reqF_countReg > 2'd1 || wci_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsi_S0_isReset_isInReset && wsi_S0_operateD ;
// value method wsiS1_sThreadBusy
assign wsiS1_SThreadBusy =
!wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget ;
// value method wsiS1_sReset_n
assign wsiS1_SReset_n = !wsi_S1_isReset_isInReset && wsi_S1_operateD ;
// value method wsiM0_mCmd
assign wsiM0_MCmd =
wsi_M0_sThreadBusy_d ? 3'd0 : wsi_M0_reqFifo_q_0[96:94] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsi_M0_sThreadBusy_d && wsi_M0_reqFifo_q_0[93] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise =
!wsi_M0_sThreadBusy_d && wsi_M0_reqFifo_q_0[92] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsi_M0_sThreadBusy_d ? 12'd0 : wsi_M0_reqFifo_q_0[91:80] ;
// value method wsiM0_mData
assign wsiM0_MData = wsi_M0_reqFifo_q_0[79:16] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsi_M0_reqFifo_q_0[15:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo =
wsi_M0_sThreadBusy_d ? 8'd0 : wsi_M0_reqFifo_q_0[7:0] ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsi_M0_isReset_isInReset && wsi_M0_operateD ;
// value method wsiM1_mCmd
assign wsiM1_MCmd =
wsi_M1_sThreadBusy_d ? 3'd0 : wsi_M1_reqFifo_q_0[96:94] ;
// value method wsiM1_mReqLast
assign wsiM1_MReqLast = !wsi_M1_sThreadBusy_d && wsi_M1_reqFifo_q_0[93] ;
// value method wsiM1_mBurstPrecise
assign wsiM1_MBurstPrecise =
!wsi_M1_sThreadBusy_d && wsi_M1_reqFifo_q_0[92] ;
// value method wsiM1_mBurstLength
assign wsiM1_MBurstLength =
wsi_M1_sThreadBusy_d ? 12'd0 : wsi_M1_reqFifo_q_0[91:80] ;
// value method wsiM1_mData
assign wsiM1_MData = wsi_M1_reqFifo_q_0[79:16] ;
// value method wsiM1_mByteEn
assign wsiM1_MByteEn = wsi_M1_reqFifo_q_0[15:8] ;
// value method wsiM1_mReqInfo
assign wsiM1_MReqInfo =
wsi_M1_sThreadBusy_d ? 8'd0 : wsi_M1_reqFifo_q_0[7:0] ;
// value method wsiM1_mReset_n
assign wsiM1_MReset_n = !wsi_M1_isReset_isInReset && wsi_M1_operateD ;
// submodule wci_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_reqF$D_IN),
.ENQ(wci_reqF$ENQ),
.DEQ(wci_reqF$DEQ),
.CLR(wci_reqF$CLR),
.D_OUT(wci_reqF$D_OUT),
.FULL_N(),
.EMPTY_N(wci_reqF$EMPTY_N));
// submodule wsi_S0_reqFifo
SizedFIFO #(.p1width(32'd97),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsi_S0_reqFifo(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsi_S0_reqFifo$D_IN),
.ENQ(wsi_S0_reqFifo$ENQ),
.DEQ(wsi_S0_reqFifo$DEQ),
.CLR(wsi_S0_reqFifo$CLR),
.D_OUT(wsi_S0_reqFifo$D_OUT),
.FULL_N(wsi_S0_reqFifo$FULL_N),
.EMPTY_N(wsi_S0_reqFifo$EMPTY_N));
// submodule wsi_S1_reqFifo
SizedFIFO #(.p1width(32'd97),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsi_S1_reqFifo(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsi_S1_reqFifo$D_IN),
.ENQ(wsi_S1_reqFifo$ENQ),
.DEQ(wsi_S1_reqFifo$DEQ),
.CLR(wsi_S1_reqFifo$CLR),
.D_OUT(wsi_S1_reqFifo$D_OUT),
.FULL_N(wsi_S1_reqFifo$FULL_N),
.EMPTY_N(wsi_S1_reqFifo$EMPTY_N));
// rule RL_wci_ctl_op_start
assign WILL_FIRE_RL_wci_ctl_op_start =
wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctrl_EiI
assign WILL_FIRE_RL_wci_ctrl_EiI =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd0 &&
wci_reqF$D_OUT[36:34] == 3'd0 ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd1 &&
wci_reqF$D_OUT[36:34] == 3'd1 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd2 &&
wci_reqF$D_OUT[36:34] == 3'd3 ;
// rule RL_doMessageConsume_S0
assign WILL_FIRE_RL_doMessageConsume_S0 =
wsi_S0_reqFifo$EMPTY_N &&
(splitCtrl[0] || splitCtrl[7] || wsi_M0_reqFifo_c_r != 2'd2) &&
(splitCtrl[8] || splitCtrl[15] || wsi_M1_reqFifo_c_r != 2'd2) &&
wci_cState == 3'd2 ;
// rule RL_doMessageConsume_S1
assign CAN_FIRE_RL_doMessageConsume_S1 =
wsi_S1_reqFifo$EMPTY_N &&
(!splitCtrl[0] || splitCtrl[7] || wsi_M0_reqFifo_c_r != 2'd2) &&
(!splitCtrl[8] || splitCtrl[15] || wsi_M1_reqFifo_c_r != 2'd2) &&
wci_cState == 3'd2 ;
assign WILL_FIRE_RL_doMessageConsume_S1 =
CAN_FIRE_RL_doMessageConsume_S1 &&
!WILL_FIRE_RL_doMessageConsume_S0 ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N &&
wci_wci_cfwr_pw$whas &&
!WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctl_op_complete
assign WILL_FIRE_RL_wci_ctl_op_complete =
wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ;
// rule RL_wsi_M0_reqFifo_deq
assign WILL_FIRE_RL_wsi_M0_reqFifo_deq =
wsi_M0_reqFifo_c_r != 2'd0 && !wsi_M0_sThreadBusy_d ;
// rule RL_wsi_M0_reqFifo_incCtr
assign WILL_FIRE_RL_wsi_M0_reqFifo_incCtr =
((wsi_M0_reqFifo_c_r == 2'd0) ?
wsi_M0_reqFifo_enqueueing$whas :
wsi_M0_reqFifo_c_r != 2'd1 ||
wsi_M0_reqFifo_enqueueing$whas) &&
wsi_M0_reqFifo_enqueueing$whas &&
!WILL_FIRE_RL_wsi_M0_reqFifo_deq ;
// rule RL_wsi_M0_reqFifo_decCtr
assign WILL_FIRE_RL_wsi_M0_reqFifo_decCtr =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
!wsi_M0_reqFifo_enqueueing$whas ;
// rule RL_wsi_M0_reqFifo_both
assign WILL_FIRE_RL_wsi_M0_reqFifo_both =
((wsi_M0_reqFifo_c_r == 2'd1) ?
wsi_M0_reqFifo_enqueueing$whas :
wsi_M0_reqFifo_c_r != 2'd2 ||
wsi_M0_reqFifo_enqueueing$whas) &&
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_enqueueing$whas ;
// rule RL_wci_cfrd
assign WILL_FIRE_RL_wci_cfrd =
wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N &&
wci_wci_cfrd_pw$whas &&
!WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_respF_incCtr
assign WILL_FIRE_RL_wci_respF_incCtr =
((wci_respF_c_r == 2'd0) ?
wci_respF_enqueueing$whas :
wci_respF_c_r != 2'd1 || wci_respF_enqueueing$whas) &&
wci_respF_enqueueing$whas &&
!(wci_respF_c_r != 2'd0) ;
// rule RL_wci_respF_decCtr
assign WILL_FIRE_RL_wci_respF_decCtr =
wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ;
// rule RL_wci_respF_both
assign WILL_FIRE_RL_wci_respF_both =
((wci_respF_c_r == 2'd1) ?
wci_respF_enqueueing$whas :
wci_respF_c_r != 2'd2 || wci_respF_enqueueing$whas) &&
wci_respF_c_r != 2'd0 &&
wci_respF_enqueueing$whas ;
// rule RL_wsi_M1_reqFifo_deq
assign WILL_FIRE_RL_wsi_M1_reqFifo_deq =
wsi_M1_reqFifo_c_r != 2'd0 && !wsi_M1_sThreadBusy_d ;
// rule RL_wsi_M1_reqFifo_incCtr
assign WILL_FIRE_RL_wsi_M1_reqFifo_incCtr =
((wsi_M1_reqFifo_c_r == 2'd0) ?
wsi_M1_reqFifo_enqueueing$whas :
wsi_M1_reqFifo_c_r != 2'd1 ||
wsi_M1_reqFifo_enqueueing$whas) &&
wsi_M1_reqFifo_enqueueing$whas &&
!WILL_FIRE_RL_wsi_M1_reqFifo_deq ;
// rule RL_wsi_M1_reqFifo_decCtr
assign WILL_FIRE_RL_wsi_M1_reqFifo_decCtr =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
!wsi_M1_reqFifo_enqueueing$whas ;
// rule RL_wsi_M1_reqFifo_both
assign WILL_FIRE_RL_wsi_M1_reqFifo_both =
((wsi_M1_reqFifo_c_r == 2'd1) ?
wsi_M1_reqFifo_enqueueing$whas :
wsi_M1_reqFifo_c_r != 2'd2 ||
wsi_M1_reqFifo_enqueueing$whas) &&
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_enqueueing$whas ;
// rule RL_wsi_S0_reqFifo_enq
assign WILL_FIRE_RL_wsi_S0_reqFifo_enq =
wsi_S0_reqFifo$FULL_N && wsi_S0_operateD && wsi_S0_peerIsReady &&
wsi_S0_wsiReq$wget[96:94] == 3'd1 ;
// rule RL_wsi_S0_reqFifo_reset
assign WILL_FIRE_RL_wsi_S0_reqFifo_reset =
WILL_FIRE_RL_wsi_S0_reqFifo_enq ||
WILL_FIRE_RL_doMessageConsume_S0 ;
// rule RL_wsi_S1_reqFifo_enq
assign WILL_FIRE_RL_wsi_S1_reqFifo_enq =
wsi_S1_reqFifo$FULL_N && wsi_S1_operateD && wsi_S1_peerIsReady &&
wsi_S1_wsiReq$wget[96:94] == 3'd1 ;
// rule RL_wsi_S1_reqFifo_reset
assign WILL_FIRE_RL_wsi_S1_reqFifo_reset =
WILL_FIRE_RL_wsi_S1_reqFifo_enq ||
WILL_FIRE_RL_doMessageConsume_S1 ;
// inputs to muxes for submodule ports
assign MUX_wci_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 &&
wci_cState != 3'd3 ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 &&
wci_cState != 3'd2 &&
wci_cState != 3'd1 ||
wci_reqF$D_OUT[36:34] == 3'd4 ||
wci_reqF$D_OUT[36:34] == 3'd5 ||
wci_reqF$D_OUT[36:34] == 3'd6 ||
wci_reqF$D_OUT[36:34] == 3'd7) ;
assign MUX_wci_respF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ;
assign MUX_wci_respF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ;
assign MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr &&
wsi_M0_reqFifo_c_r == 2'd0 ;
assign MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr &&
wsi_M0_reqFifo_c_r == 2'd1 ;
assign MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1 =
WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[0] &&
!splitCtrl[7] ;
assign MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr &&
wsi_M1_reqFifo_c_r == 2'd0 ;
assign MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr &&
wsi_M1_reqFifo_c_r == 2'd1 ;
assign MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1 =
WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[8] &&
!splitCtrl[15] ;
assign MUX_wci_illegalEdge$write_1__VAL_1 =
wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 &&
wci_reqF$D_OUT[36:34] != 3'd6 ;
assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r + 2'd1 ;
assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r - 2'd1 ;
assign MUX_wci_respF_q_0$write_1__VAL_1 =
(wci_respF_c_r == 2'd1) ?
MUX_wci_respF_q_0$write_1__VAL_2 :
wci_respF_q_1 ;
always@(WILL_FIRE_RL_wci_ctl_op_complete or
MUX_wci_respF_x_wire$wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_ctl_op_complete:
MUX_wci_respF_q_0$write_1__VAL_2 =
MUX_wci_respF_x_wire$wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_respF_q_0$write_1__VAL_2 =
MUX_wci_respF_x_wire$wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_respF_q_0$write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_respF_q_1$write_1__VAL_1 =
(wci_respF_c_r == 2'd2) ?
MUX_wci_respF_q_0$write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_respF_x_wire$wset_1__VAL_1 =
wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, _theResult____h16428 } ;
assign MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1 = wsi_M0_reqFifo_c_r + 2'd1 ;
assign MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2 = wsi_M0_reqFifo_c_r - 2'd1 ;
assign MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1 =
(wsi_M0_reqFifo_c_r == 2'd1) ?
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 :
wsi_M0_reqFifo_q_1 ;
assign MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 =
MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1 ?
wsi_S0_reqFifo$D_OUT :
wsi_S1_reqFifo$D_OUT ;
assign MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1 =
(wsi_M0_reqFifo_c_r == 2'd2) ?
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 :
97'h00000AAAAAAAAAAAAAAAAAA00 ;
assign MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1 = wsi_M1_reqFifo_c_r + 2'd1 ;
assign MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2 = wsi_M1_reqFifo_c_r - 2'd1 ;
assign MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1 =
(wsi_M1_reqFifo_c_r == 2'd1) ?
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 :
wsi_M1_reqFifo_q_1 ;
assign MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 =
MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1 ?
wsi_S0_reqFifo$D_OUT :
wsi_S1_reqFifo$D_OUT ;
assign MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1 =
(wsi_M1_reqFifo_c_r == 2'd2) ?
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 :
97'h00000AAAAAAAAAAAAAAAAAA00 ;
// inlined wires
assign wci_wciReq$wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wciReq$whas = 1'd1 ;
assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ;
assign wci_respF_x_wire$whas = wci_respF_enqueueing$whas ;
assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ;
assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ;
assign wci_sFlagReg_1$wget = 1'b0 ;
assign wci_sFlagReg_1$whas = 1'b0 ;
assign wci_ctlAckReg_1$wget = 1'd1 ;
assign wci_ctlAckReg_1$whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
WILL_FIRE_RL_wci_ctrl_EiI ;
assign wsi_S0_wsiReq$wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsi_S0_wsiReq$whas = 1'd1 ;
assign wsi_S0_operateD_1$wget = 1'd1 ;
assign wsi_S0_operateD_1$whas = wci_cState == 3'd2 ;
assign wsi_S0_peerIsReady_1$wget = 1'd1 ;
assign wsi_S0_peerIsReady_1$whas = wsiS0_MReset_n ;
assign wsi_S0_sThreadBusy_dw$wget = wsi_S0_reqFifo_countReg > 2'd1 ;
assign wsi_S0_sThreadBusy_dw$whas =
wsi_S0_reqFifo_levelsValid && wsi_S0_operateD &&
wsi_S0_peerIsReady ;
assign wsi_S1_wsiReq$wget =
{ wsiS1_MCmd,
wsiS1_MReqLast,
wsiS1_MBurstPrecise,
wsiS1_MBurstLength,
wsiS1_MData,
wsiS1_MByteEn,
wsiS1_MReqInfo } ;
assign wsi_S1_wsiReq$whas = 1'd1 ;
assign wsi_S1_operateD_1$wget = 1'd1 ;
assign wsi_S1_operateD_1$whas = wci_cState == 3'd2 ;
assign wsi_S1_peerIsReady_1$wget = 1'd1 ;
assign wsi_S1_peerIsReady_1$whas = wsiS1_MReset_n ;
assign wsi_S1_sThreadBusy_dw$wget = wsi_S1_reqFifo_countReg > 2'd1 ;
assign wsi_S1_sThreadBusy_dw$whas =
wsi_S1_reqFifo_levelsValid && wsi_S1_operateD &&
wsi_S1_peerIsReady ;
assign wsi_M0_reqFifo_x_wire$wget = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 ;
assign wsi_M0_reqFifo_x_wire$whas = wsi_M0_reqFifo_enqueueing$whas ;
assign wsi_M0_operateD_1$wget = 1'd1 ;
assign wsi_M0_operateD_1$whas = wci_cState == 3'd2 ;
assign wsi_M0_peerIsReady_1$wget = 1'd1 ;
assign wsi_M0_peerIsReady_1$whas = wsiM0_SReset_n ;
assign wsi_M1_reqFifo_x_wire$wget = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 ;
assign wsi_M1_reqFifo_x_wire$whas = wsi_M1_reqFifo_enqueueing$whas ;
assign wsi_M1_operateD_1$wget = 1'd1 ;
assign wsi_M1_operateD_1$whas = wci_cState == 3'd2 ;
assign wsi_M1_peerIsReady_1$wget = 1'd1 ;
assign wsi_M1_peerIsReady_1$whas = wsiM1_SReset_n ;
assign wci_Es_mCmd_w$wget = wciS0_MCmd ;
assign wci_Es_mCmd_w$whas = 1'd1 ;
assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ;
assign wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ;
assign wci_Es_mByteEn_w$whas = 1'd1 ;
assign wci_Es_mAddr_w$wget = wciS0_MAddr ;
assign wci_Es_mAddr_w$whas = 1'd1 ;
assign wci_Es_mData_w$wget = wciS0_MData ;
assign wci_Es_mData_w$whas = 1'd1 ;
assign wsi_Es0_mCmd_w$wget = wsiS0_MCmd ;
assign wsi_Es0_mCmd_w$whas = 1'd1 ;
assign wsi_Es0_mBurstLength_w$wget = wsiS0_MBurstLength ;
assign wsi_Es0_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es0_mData_w$wget = wsiS0_MData ;
assign wsi_Es0_mData_w$whas = 1'd1 ;
assign wsi_Es0_mByteEn_w$wget = wsiS0_MByteEn ;
assign wsi_Es0_mByteEn_w$whas = 1'd1 ;
assign wsi_Es0_mReqInfo_w$wget = wsiS0_MReqInfo ;
assign wsi_Es0_mReqInfo_w$whas = 1'd1 ;
assign wsi_Es1_mCmd_w$wget = wsiS1_MCmd ;
assign wsi_Es1_mCmd_w$whas = 1'd1 ;
assign wsi_Es1_mBurstLength_w$wget = wsiS1_MBurstLength ;
assign wsi_Es1_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es1_mData_w$wget = wsiS1_MData ;
assign wsi_Es1_mData_w$whas = 1'd1 ;
assign wsi_Es1_mByteEn_w$wget = wsiS1_MByteEn ;
assign wsi_Es1_mByteEn_w$whas = 1'd1 ;
assign wsi_Es1_mReqInfo_w$wget = wsiS1_MReqInfo ;
assign wsi_Es1_mReqInfo_w$whas = 1'd1 ;
assign wci_reqF_r_enq$whas = wci_wciReq$wget[71:69] != 3'd0 ;
assign wci_reqF_r_deq$whas =
WILL_FIRE_RL_wci_ctl_op_start || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_reqF_r_clr$whas = 1'b0 ;
assign wci_respF_enqueueing$whas =
WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ;
assign wci_sThreadBusy_pw$whas = 1'b0 ;
assign wci_wci_cfwr_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] &&
wci_reqF$D_OUT[71:69] == 3'd1 ;
assign wci_wci_cfrd_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] &&
wci_reqF$D_OUT[71:69] == 3'd2 ;
assign wci_wci_ctrl_pw$whas =
wci_reqF$EMPTY_N && !wci_reqF$D_OUT[68] &&
wci_reqF$D_OUT[71:69] == 3'd2 ;
assign wsi_S0_reqFifo_r_enq$whas = WILL_FIRE_RL_wsi_S0_reqFifo_enq ;
assign wsi_S0_reqFifo_r_deq$whas = WILL_FIRE_RL_doMessageConsume_S0 ;
assign wsi_S0_reqFifo_r_clr$whas = 1'b0 ;
assign wsi_S0_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsi_S0_reqFifo_enq ;
assign wsi_S0_reqFifo_doResetDeq$whas = WILL_FIRE_RL_doMessageConsume_S0 ;
assign wsi_S0_reqFifo_doResetClr$whas = 1'b0 ;
assign wsi_S1_reqFifo_r_enq$whas = WILL_FIRE_RL_wsi_S1_reqFifo_enq ;
assign wsi_S1_reqFifo_r_deq$whas = WILL_FIRE_RL_doMessageConsume_S1 ;
assign wsi_S1_reqFifo_r_clr$whas = 1'b0 ;
assign wsi_S1_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsi_S1_reqFifo_enq ;
assign wsi_S1_reqFifo_doResetDeq$whas = WILL_FIRE_RL_doMessageConsume_S1 ;
assign wsi_S1_reqFifo_doResetClr$whas = 1'b0 ;
assign wsi_M0_reqFifo_enqueueing$whas =
WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[0] &&
!splitCtrl[7] ||
WILL_FIRE_RL_doMessageConsume_S1 && splitCtrl[0] &&
!splitCtrl[7] ;
assign wsi_M0_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsi_M0_reqFifo_deq ;
assign wsi_M0_sThreadBusy_pw$whas = wsiM0_SThreadBusy ;
assign wsi_M1_reqFifo_enqueueing$whas =
WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[8] &&
!splitCtrl[15] ||
WILL_FIRE_RL_doMessageConsume_S1 && splitCtrl[8] &&
!splitCtrl[15] ;
assign wsi_M1_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsi_M1_reqFifo_deq ;
assign wsi_M1_sThreadBusy_pw$whas = wsiM1_SThreadBusy ;
assign wsi_Es0_mReqLast_w$whas = wsiS0_MReqLast ;
assign wsi_Es0_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ;
assign wsi_Es0_mDataInfo_w$whas = 1'd1 ;
assign wsi_Es1_mReqLast_w$whas = wsiS1_MReqLast ;
assign wsi_Es1_mBurstPrecise_w$whas = wsiS1_MBurstPrecise ;
assign wsi_Es1_mDataInfo_w$whas = 1'd1 ;
assign wsi_S0_extStatusW$wget =
{ wsi_S0_pMesgCount, wsi_S0_iMesgCount, wsi_S0_tBusyCount } ;
assign wsi_S1_extStatusW$wget =
{ wsi_S1_pMesgCount, wsi_S1_iMesgCount, wsi_S1_tBusyCount } ;
assign wsi_M0_extStatusW$wget =
{ wsi_M0_pMesgCount, wsi_M0_iMesgCount, wsi_M0_tBusyCount } ;
assign wsi_M1_extStatusW$wget =
{ wsi_M1_pMesgCount, wsi_M1_iMesgCount, wsi_M1_tBusyCount } ;
// register splitCtrl
assign splitCtrl$D_IN = wci_reqF$D_OUT[31:0] ;
assign splitCtrl$EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[39:32] == 8'h04 ;
// register wci_cEdge
assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ;
assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_cState
assign wci_cState$D_IN = wci_nState ;
assign wci_cState$EN =
WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ;
// register wci_ctlAckReg
assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ;
assign wci_ctlAckReg$EN = 1'd1 ;
// register wci_ctlOpActive
assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_ctlOpActive$EN =
WILL_FIRE_RL_wci_ctl_op_complete ||
WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_illegalEdge
assign wci_illegalEdge$D_IN =
MUX_wci_illegalEdge$write_1__SEL_1 &&
MUX_wci_illegalEdge$write_1__VAL_1 ;
assign wci_illegalEdge$EN =
MUX_wci_illegalEdge$write_1__SEL_1 ||
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ;
// register wci_isReset_isInReset
assign wci_isReset_isInReset$D_IN = 1'd0 ;
assign wci_isReset_isInReset$EN = wci_isReset_isInReset ;
// register wci_nState
always@(wci_reqF$D_OUT)
begin
case (wci_reqF$D_OUT[36:34])
3'd0: wci_nState$D_IN = 3'd1;
3'd1: wci_nState$D_IN = 3'd2;
3'd2: wci_nState$D_IN = 3'd3;
default: wci_nState$D_IN = 3'd0;
endcase
end
assign wci_nState$EN =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 &&
(wci_cState == 3'd1 || wci_cState == 3'd3) ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 &&
(wci_cState == 3'd3 || wci_cState == 3'd2 ||
wci_cState == 3'd1)) ;
// register wci_reqF_countReg
assign wci_reqF_countReg$D_IN =
(wci_wciReq$wget[71:69] != 3'd0) ?
wci_reqF_countReg + 2'd1 :
wci_reqF_countReg - 2'd1 ;
assign wci_reqF_countReg$EN =
(wci_wciReq$wget[71:69] != 3'd0) != wci_reqF_r_deq$whas ;
// register wci_respF_c_r
assign wci_respF_c_r$D_IN =
WILL_FIRE_RL_wci_respF_incCtr ?
MUX_wci_respF_c_r$write_1__VAL_1 :
MUX_wci_respF_c_r$write_1__VAL_2 ;
assign wci_respF_c_r$EN =
WILL_FIRE_RL_wci_respF_incCtr || WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_respF_q_0
always@(WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_0$write_1__VAL_1 or
MUX_wci_respF_q_0$write_1__SEL_2 or
MUX_wci_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1;
MUX_wci_respF_q_0$write_1__SEL_2:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1;
default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_respF_q_0$EN =
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ||
WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_respF_q_1
always@(WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_1$write_1__VAL_1 or
MUX_wci_respF_q_1$write_1__SEL_2 or
MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1;
MUX_wci_respF_q_1$write_1__SEL_2:
wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA;
default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_respF_q_1$EN =
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ||
WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_sFlagReg
assign wci_sFlagReg$D_IN = 1'b0 ;
assign wci_sFlagReg$EN = 1'd1 ;
// register wci_sThreadBusy_d
assign wci_sThreadBusy_d$D_IN = 1'b0 ;
assign wci_sThreadBusy_d$EN = 1'd1 ;
// register wsi_M0_burstKind
assign wsi_M0_burstKind$D_IN =
(wsi_M0_burstKind == 2'd0) ?
(wsi_M0_reqFifo_q_0[92] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsi_M0_burstKind$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_q_0[96:94] == 3'd1 &&
(wsi_M0_burstKind == 2'd0 ||
(wsi_M0_burstKind == 2'd1 || wsi_M0_burstKind == 2'd2) &&
wsi_M0_reqFifo_q_0[93]) ;
// register wsi_M0_errorSticky
assign wsi_M0_errorSticky$D_IN = 1'b0 ;
assign wsi_M0_errorSticky$EN = 1'b0 ;
// register wsi_M0_iMesgCount
assign wsi_M0_iMesgCount$D_IN = wsi_M0_iMesgCount + 32'd1 ;
assign wsi_M0_iMesgCount$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_q_0[96:94] == 3'd1 &&
wsi_M0_burstKind == 2'd2 &&
wsi_M0_reqFifo_q_0[93] ;
// register wsi_M0_isReset_isInReset
assign wsi_M0_isReset_isInReset$D_IN = 1'd0 ;
assign wsi_M0_isReset_isInReset$EN = wsi_M0_isReset_isInReset ;
// register wsi_M0_operateD
assign wsi_M0_operateD$D_IN = wci_cState == 3'd2 ;
assign wsi_M0_operateD$EN = 1'd1 ;
// register wsi_M0_pMesgCount
assign wsi_M0_pMesgCount$D_IN = wsi_M0_pMesgCount + 32'd1 ;
assign wsi_M0_pMesgCount$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_q_0[96:94] == 3'd1 &&
wsi_M0_burstKind == 2'd1 &&
wsi_M0_reqFifo_q_0[93] ;
// register wsi_M0_peerIsReady
assign wsi_M0_peerIsReady$D_IN = wsiM0_SReset_n ;
assign wsi_M0_peerIsReady$EN = 1'd1 ;
// register wsi_M0_reqFifo_c_r
assign wsi_M0_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr ?
MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1 :
MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2 ;
assign wsi_M0_reqFifo_c_r$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr ||
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ;
// register wsi_M0_reqFifo_q_0
always@(WILL_FIRE_RL_wsi_M0_reqFifo_both or
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1 or
MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2 or
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr or wsi_M0_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsi_M0_reqFifo_both:
wsi_M0_reqFifo_q_0$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1;
MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2:
wsi_M0_reqFifo_q_0$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr:
wsi_M0_reqFifo_q_0$D_IN = wsi_M0_reqFifo_q_1;
default: wsi_M0_reqFifo_q_0$D_IN =
97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsi_M0_reqFifo_q_0$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_both ||
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr &&
wsi_M0_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ;
// register wsi_M0_reqFifo_q_1
always@(WILL_FIRE_RL_wsi_M0_reqFifo_both or
MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1 or
MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2 or
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsi_M0_reqFifo_both:
wsi_M0_reqFifo_q_1$D_IN = MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1;
MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2:
wsi_M0_reqFifo_q_1$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr:
wsi_M0_reqFifo_q_1$D_IN = 97'h00000AAAAAAAAAAAAAAAAAA00;
default: wsi_M0_reqFifo_q_1$D_IN =
97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsi_M0_reqFifo_q_1$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_both ||
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr &&
wsi_M0_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ;
// register wsi_M0_sThreadBusy_d
assign wsi_M0_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ;
assign wsi_M0_sThreadBusy_d$EN = 1'd1 ;
// register wsi_M0_statusR
assign wsi_M0_statusR$D_IN =
{ wsi_M0_isReset_isInReset,
!wsi_M0_peerIsReady,
!wsi_M0_operateD,
wsi_M0_errorSticky,
wsi_M0_burstKind != 2'd0,
wsi_M0_sThreadBusy_d,
1'd0,
wsi_M0_trafficSticky } ;
assign wsi_M0_statusR$EN = 1'd1 ;
// register wsi_M0_tBusyCount
assign wsi_M0_tBusyCount$D_IN = wsi_M0_tBusyCount + 32'd1 ;
assign wsi_M0_tBusyCount$EN =
wsi_M0_operateD && wsi_M0_peerIsReady && wsi_M0_sThreadBusy_d ;
// register wsi_M0_trafficSticky
assign wsi_M0_trafficSticky$D_IN = 1'd1 ;
assign wsi_M0_trafficSticky$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_q_0[96:94] == 3'd1 ;
// register wsi_M1_burstKind
assign wsi_M1_burstKind$D_IN =
(wsi_M1_burstKind == 2'd0) ?
(wsi_M1_reqFifo_q_0[92] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsi_M1_burstKind$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_q_0[96:94] == 3'd1 &&
(wsi_M1_burstKind == 2'd0 ||
(wsi_M1_burstKind == 2'd1 || wsi_M1_burstKind == 2'd2) &&
wsi_M1_reqFifo_q_0[93]) ;
// register wsi_M1_errorSticky
assign wsi_M1_errorSticky$D_IN = 1'b0 ;
assign wsi_M1_errorSticky$EN = 1'b0 ;
// register wsi_M1_iMesgCount
assign wsi_M1_iMesgCount$D_IN = wsi_M1_iMesgCount + 32'd1 ;
assign wsi_M1_iMesgCount$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_q_0[96:94] == 3'd1 &&
wsi_M1_burstKind == 2'd2 &&
wsi_M1_reqFifo_q_0[93] ;
// register wsi_M1_isReset_isInReset
assign wsi_M1_isReset_isInReset$D_IN = 1'd0 ;
assign wsi_M1_isReset_isInReset$EN = wsi_M1_isReset_isInReset ;
// register wsi_M1_operateD
assign wsi_M1_operateD$D_IN = wci_cState == 3'd2 ;
assign wsi_M1_operateD$EN = 1'd1 ;
// register wsi_M1_pMesgCount
assign wsi_M1_pMesgCount$D_IN = wsi_M1_pMesgCount + 32'd1 ;
assign wsi_M1_pMesgCount$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_q_0[96:94] == 3'd1 &&
wsi_M1_burstKind == 2'd1 &&
wsi_M1_reqFifo_q_0[93] ;
// register wsi_M1_peerIsReady
assign wsi_M1_peerIsReady$D_IN = wsiM1_SReset_n ;
assign wsi_M1_peerIsReady$EN = 1'd1 ;
// register wsi_M1_reqFifo_c_r
assign wsi_M1_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr ?
MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1 :
MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2 ;
assign wsi_M1_reqFifo_c_r$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr ||
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ;
// register wsi_M1_reqFifo_q_0
always@(WILL_FIRE_RL_wsi_M1_reqFifo_both or
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1 or
MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2 or
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr or wsi_M1_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsi_M1_reqFifo_both:
wsi_M1_reqFifo_q_0$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1;
MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2:
wsi_M1_reqFifo_q_0$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr:
wsi_M1_reqFifo_q_0$D_IN = wsi_M1_reqFifo_q_1;
default: wsi_M1_reqFifo_q_0$D_IN =
97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsi_M1_reqFifo_q_0$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_both ||
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr &&
wsi_M1_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ;
// register wsi_M1_reqFifo_q_1
always@(WILL_FIRE_RL_wsi_M1_reqFifo_both or
MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1 or
MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2 or
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsi_M1_reqFifo_both:
wsi_M1_reqFifo_q_1$D_IN = MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1;
MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2:
wsi_M1_reqFifo_q_1$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr:
wsi_M1_reqFifo_q_1$D_IN = 97'h00000AAAAAAAAAAAAAAAAAA00;
default: wsi_M1_reqFifo_q_1$D_IN =
97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsi_M1_reqFifo_q_1$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_both ||
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr &&
wsi_M1_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ;
// register wsi_M1_sThreadBusy_d
assign wsi_M1_sThreadBusy_d$D_IN = wsiM1_SThreadBusy ;
assign wsi_M1_sThreadBusy_d$EN = 1'd1 ;
// register wsi_M1_statusR
assign wsi_M1_statusR$D_IN =
{ wsi_M1_isReset_isInReset,
!wsi_M1_peerIsReady,
!wsi_M1_operateD,
wsi_M1_errorSticky,
wsi_M1_burstKind != 2'd0,
wsi_M1_sThreadBusy_d,
1'd0,
wsi_M1_trafficSticky } ;
assign wsi_M1_statusR$EN = 1'd1 ;
// register wsi_M1_tBusyCount
assign wsi_M1_tBusyCount$D_IN = wsi_M1_tBusyCount + 32'd1 ;
assign wsi_M1_tBusyCount$EN =
wsi_M1_operateD && wsi_M1_peerIsReady && wsi_M1_sThreadBusy_d ;
// register wsi_M1_trafficSticky
assign wsi_M1_trafficSticky$D_IN = 1'd1 ;
assign wsi_M1_trafficSticky$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_q_0[96:94] == 3'd1 ;
// register wsi_S0_burstKind
assign wsi_S0_burstKind$D_IN =
(wsi_S0_burstKind == 2'd0) ?
(wsi_S0_wsiReq$wget[92] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsi_S0_burstKind$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq &&
(wsi_S0_burstKind == 2'd0 ||
(wsi_S0_burstKind == 2'd1 || wsi_S0_burstKind == 2'd2) &&
wsi_S0_wsiReq$wget[93]) ;
// register wsi_S0_errorSticky
assign wsi_S0_errorSticky$D_IN = 1'b0 ;
assign wsi_S0_errorSticky$EN = 1'b0 ;
// register wsi_S0_iMesgCount
assign wsi_S0_iMesgCount$D_IN = wsi_S0_iMesgCount + 32'd1 ;
assign wsi_S0_iMesgCount$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_burstKind == 2'd2 &&
wsi_S0_wsiReq$wget[93] ;
// register wsi_S0_isReset_isInReset
assign wsi_S0_isReset_isInReset$D_IN = 1'd0 ;
assign wsi_S0_isReset_isInReset$EN = wsi_S0_isReset_isInReset ;
// register wsi_S0_mesgWordLength
assign wsi_S0_mesgWordLength$D_IN = wsi_S0_wordCount ;
assign wsi_S0_mesgWordLength$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_wsiReq$wget[93] ;
// register wsi_S0_operateD
assign wsi_S0_operateD$D_IN = wci_cState == 3'd2 ;
assign wsi_S0_operateD$EN = 1'd1 ;
// register wsi_S0_pMesgCount
assign wsi_S0_pMesgCount$D_IN = wsi_S0_pMesgCount + 32'd1 ;
assign wsi_S0_pMesgCount$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_burstKind == 2'd1 &&
wsi_S0_wsiReq$wget[93] ;
// register wsi_S0_peerIsReady
assign wsi_S0_peerIsReady$D_IN = wsiS0_MReset_n ;
assign wsi_S0_peerIsReady$EN = 1'd1 ;
// register wsi_S0_reqFifo_countReg
assign wsi_S0_reqFifo_countReg$D_IN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq ?
wsi_S0_reqFifo_countReg + 2'd1 :
wsi_S0_reqFifo_countReg - 2'd1 ;
assign wsi_S0_reqFifo_countReg$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq !=
WILL_FIRE_RL_doMessageConsume_S0 ;
// register wsi_S0_reqFifo_levelsValid
assign wsi_S0_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsi_S0_reqFifo_reset ;
assign wsi_S0_reqFifo_levelsValid$EN =
WILL_FIRE_RL_doMessageConsume_S0 ||
WILL_FIRE_RL_wsi_S0_reqFifo_enq ||
WILL_FIRE_RL_wsi_S0_reqFifo_reset ;
// register wsi_S0_statusR
assign wsi_S0_statusR$D_IN =
{ wsi_S0_isReset_isInReset,
!wsi_S0_peerIsReady,
!wsi_S0_operateD,
wsi_S0_errorSticky,
wsi_S0_burstKind != 2'd0,
!wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget,
1'd0,
wsi_S0_trafficSticky } ;
assign wsi_S0_statusR$EN = 1'd1 ;
// register wsi_S0_tBusyCount
assign wsi_S0_tBusyCount$D_IN = wsi_S0_tBusyCount + 32'd1 ;
assign wsi_S0_tBusyCount$EN =
wsi_S0_operateD && wsi_S0_peerIsReady &&
(!wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget) ;
// register wsi_S0_trafficSticky
assign wsi_S0_trafficSticky$D_IN = 1'd1 ;
assign wsi_S0_trafficSticky$EN = WILL_FIRE_RL_wsi_S0_reqFifo_enq ;
// register wsi_S0_wordCount
assign wsi_S0_wordCount$D_IN =
wsi_S0_wsiReq$wget[93] ? 12'd1 : wsi_S0_wordCount + 12'd1 ;
assign wsi_S0_wordCount$EN = WILL_FIRE_RL_wsi_S0_reqFifo_enq ;
// register wsi_S1_burstKind
assign wsi_S1_burstKind$D_IN =
(wsi_S1_burstKind == 2'd0) ?
(wsi_S1_wsiReq$wget[92] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsi_S1_burstKind$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq &&
(wsi_S1_burstKind == 2'd0 ||
(wsi_S1_burstKind == 2'd1 || wsi_S1_burstKind == 2'd2) &&
wsi_S1_wsiReq$wget[93]) ;
// register wsi_S1_errorSticky
assign wsi_S1_errorSticky$D_IN = 1'b0 ;
assign wsi_S1_errorSticky$EN = 1'b0 ;
// register wsi_S1_iMesgCount
assign wsi_S1_iMesgCount$D_IN = wsi_S1_iMesgCount + 32'd1 ;
assign wsi_S1_iMesgCount$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_burstKind == 2'd2 &&
wsi_S1_wsiReq$wget[93] ;
// register wsi_S1_isReset_isInReset
assign wsi_S1_isReset_isInReset$D_IN = 1'd0 ;
assign wsi_S1_isReset_isInReset$EN = wsi_S1_isReset_isInReset ;
// register wsi_S1_mesgWordLength
assign wsi_S1_mesgWordLength$D_IN = wsi_S1_wordCount ;
assign wsi_S1_mesgWordLength$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_wsiReq$wget[93] ;
// register wsi_S1_operateD
assign wsi_S1_operateD$D_IN = wci_cState == 3'd2 ;
assign wsi_S1_operateD$EN = 1'd1 ;
// register wsi_S1_pMesgCount
assign wsi_S1_pMesgCount$D_IN = wsi_S1_pMesgCount + 32'd1 ;
assign wsi_S1_pMesgCount$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_burstKind == 2'd1 &&
wsi_S1_wsiReq$wget[93] ;
// register wsi_S1_peerIsReady
assign wsi_S1_peerIsReady$D_IN = wsiS1_MReset_n ;
assign wsi_S1_peerIsReady$EN = 1'd1 ;
// register wsi_S1_reqFifo_countReg
assign wsi_S1_reqFifo_countReg$D_IN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq ?
wsi_S1_reqFifo_countReg + 2'd1 :
wsi_S1_reqFifo_countReg - 2'd1 ;
assign wsi_S1_reqFifo_countReg$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq !=
WILL_FIRE_RL_doMessageConsume_S1 ;
// register wsi_S1_reqFifo_levelsValid
assign wsi_S1_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsi_S1_reqFifo_reset ;
assign wsi_S1_reqFifo_levelsValid$EN =
WILL_FIRE_RL_doMessageConsume_S1 ||
WILL_FIRE_RL_wsi_S1_reqFifo_enq ||
WILL_FIRE_RL_wsi_S1_reqFifo_reset ;
// register wsi_S1_statusR
assign wsi_S1_statusR$D_IN =
{ wsi_S1_isReset_isInReset,
!wsi_S1_peerIsReady,
!wsi_S1_operateD,
wsi_S1_errorSticky,
wsi_S1_burstKind != 2'd0,
!wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget,
1'd0,
wsi_S1_trafficSticky } ;
assign wsi_S1_statusR$EN = 1'd1 ;
// register wsi_S1_tBusyCount
assign wsi_S1_tBusyCount$D_IN = wsi_S1_tBusyCount + 32'd1 ;
assign wsi_S1_tBusyCount$EN =
wsi_S1_operateD && wsi_S1_peerIsReady &&
(!wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget) ;
// register wsi_S1_trafficSticky
assign wsi_S1_trafficSticky$D_IN = 1'd1 ;
assign wsi_S1_trafficSticky$EN = WILL_FIRE_RL_wsi_S1_reqFifo_enq ;
// register wsi_S1_wordCount
assign wsi_S1_wordCount$D_IN =
wsi_S1_wsiReq$wget[93] ? 12'd1 : wsi_S1_wordCount + 12'd1 ;
assign wsi_S1_wordCount$EN = WILL_FIRE_RL_wsi_S1_reqFifo_enq ;
// submodule wci_reqF
assign wci_reqF$D_IN = wci_wciReq$wget ;
assign wci_reqF$ENQ = wci_wciReq$wget[71:69] != 3'd0 ;
assign wci_reqF$DEQ = wci_reqF_r_deq$whas ;
assign wci_reqF$CLR = 1'b0 ;
// submodule wsi_S0_reqFifo
assign wsi_S0_reqFifo$D_IN = wsi_S0_wsiReq$wget ;
assign wsi_S0_reqFifo$ENQ = WILL_FIRE_RL_wsi_S0_reqFifo_enq ;
assign wsi_S0_reqFifo$DEQ = WILL_FIRE_RL_doMessageConsume_S0 ;
assign wsi_S0_reqFifo$CLR = 1'b0 ;
// submodule wsi_S1_reqFifo
assign wsi_S1_reqFifo$D_IN = wsi_S1_wsiReq$wget ;
assign wsi_S1_reqFifo$ENQ = WILL_FIRE_RL_wsi_S1_reqFifo_enq ;
assign wsi_S1_reqFifo$DEQ = WILL_FIRE_RL_doMessageConsume_S1 ;
assign wsi_S1_reqFifo$CLR = 1'b0 ;
// remaining internal signals
assign rdat__h16512 =
hasDebugLogic ?
{ wsi_S0_statusR,
wsi_S1_statusR,
wsi_M0_statusR,
wsi_M1_statusR } :
32'd0 ;
assign rdat__h16701 =
hasDebugLogic ? wsi_S0_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h16715 =
hasDebugLogic ? wsi_S0_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h16723 =
hasDebugLogic ? wsi_S1_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h16737 =
hasDebugLogic ? wsi_S1_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h16745 =
hasDebugLogic ? wsi_M0_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h16759 =
hasDebugLogic ? wsi_M0_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h16767 =
hasDebugLogic ? wsi_M1_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h16781 =
hasDebugLogic ? wsi_M1_extStatusW$wget[63:32] : 32'd0 ;
always@(wci_reqF$D_OUT or
splitCtrl or
rdat__h16512 or
rdat__h16701 or
rdat__h16715 or
rdat__h16723 or
rdat__h16737 or
rdat__h16745 or rdat__h16759 or rdat__h16767 or rdat__h16781)
begin
case (wci_reqF$D_OUT[39:32])
8'h04: _theResult____h16428 = splitCtrl;
8'h1C: _theResult____h16428 = rdat__h16512;
8'h20: _theResult____h16428 = rdat__h16701;
8'h24: _theResult____h16428 = rdat__h16715;
8'h28: _theResult____h16428 = rdat__h16723;
8'h2C: _theResult____h16428 = rdat__h16737;
8'h30: _theResult____h16428 = rdat__h16745;
8'h34: _theResult____h16428 = rdat__h16759;
8'h38: _theResult____h16428 = rdat__h16767;
8'h3C: _theResult____h16428 = rdat__h16781;
default: _theResult____h16428 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
splitCtrl <= `BSV_ASSIGNMENT_DELAY ctrlInit;
wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M0_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_M0_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M0_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M0_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M0_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M0_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_M0_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY
97'h00000AAAAAAAAAAAAAAAAAA00;
wsi_M0_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY
97'h00000AAAAAAAAAAAAAAAAAA00;
wsi_M0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M0_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M0_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M1_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_M1_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M1_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M1_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M1_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M1_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_M1_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY
97'h00000AAAAAAAAAAAAAAAAAA00;
wsi_M1_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY
97'h00000AAAAAAAAAAAAAAAAAA00;
wsi_M1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M1_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M1_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_S0_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S0_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_S0_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_S0_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S0_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
wsi_S1_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_S1_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S1_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S1_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S1_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S1_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_S1_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_S1_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S1_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S1_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (splitCtrl$EN) splitCtrl <= `BSV_ASSIGNMENT_DELAY splitCtrl$D_IN;
if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN;
if (wci_cState$EN)
wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN;
if (wci_ctlAckReg$EN)
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN;
if (wci_ctlOpActive$EN)
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN;
if (wci_illegalEdge$EN)
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN;
if (wci_nState$EN)
wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN;
if (wci_reqF_countReg$EN)
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN;
if (wci_respF_c_r$EN)
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN;
if (wci_respF_q_0$EN)
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN;
if (wci_respF_q_1$EN)
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN;
if (wci_sFlagReg$EN)
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN;
if (wci_sThreadBusy_d$EN)
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN;
if (wsi_M0_burstKind$EN)
wsi_M0_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_M0_burstKind$D_IN;
if (wsi_M0_errorSticky$EN)
wsi_M0_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_M0_errorSticky$D_IN;
if (wsi_M0_iMesgCount$EN)
wsi_M0_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_iMesgCount$D_IN;
if (wsi_M0_operateD$EN)
wsi_M0_operateD <= `BSV_ASSIGNMENT_DELAY wsi_M0_operateD$D_IN;
if (wsi_M0_pMesgCount$EN)
wsi_M0_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_pMesgCount$D_IN;
if (wsi_M0_peerIsReady$EN)
wsi_M0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_M0_peerIsReady$D_IN;
if (wsi_M0_reqFifo_c_r$EN)
wsi_M0_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_c_r$D_IN;
if (wsi_M0_reqFifo_q_0$EN)
wsi_M0_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_q_0$D_IN;
if (wsi_M0_reqFifo_q_1$EN)
wsi_M0_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_q_1$D_IN;
if (wsi_M0_sThreadBusy_d$EN)
wsi_M0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wsi_M0_sThreadBusy_d$D_IN;
if (wsi_M0_tBusyCount$EN)
wsi_M0_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_tBusyCount$D_IN;
if (wsi_M0_trafficSticky$EN)
wsi_M0_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wsi_M0_trafficSticky$D_IN;
if (wsi_M1_burstKind$EN)
wsi_M1_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_M1_burstKind$D_IN;
if (wsi_M1_errorSticky$EN)
wsi_M1_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_M1_errorSticky$D_IN;
if (wsi_M1_iMesgCount$EN)
wsi_M1_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_iMesgCount$D_IN;
if (wsi_M1_operateD$EN)
wsi_M1_operateD <= `BSV_ASSIGNMENT_DELAY wsi_M1_operateD$D_IN;
if (wsi_M1_pMesgCount$EN)
wsi_M1_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_pMesgCount$D_IN;
if (wsi_M1_peerIsReady$EN)
wsi_M1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_M1_peerIsReady$D_IN;
if (wsi_M1_reqFifo_c_r$EN)
wsi_M1_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_c_r$D_IN;
if (wsi_M1_reqFifo_q_0$EN)
wsi_M1_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_q_0$D_IN;
if (wsi_M1_reqFifo_q_1$EN)
wsi_M1_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_q_1$D_IN;
if (wsi_M1_sThreadBusy_d$EN)
wsi_M1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wsi_M1_sThreadBusy_d$D_IN;
if (wsi_M1_tBusyCount$EN)
wsi_M1_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_tBusyCount$D_IN;
if (wsi_M1_trafficSticky$EN)
wsi_M1_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wsi_M1_trafficSticky$D_IN;
if (wsi_S0_burstKind$EN)
wsi_S0_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_S0_burstKind$D_IN;
if (wsi_S0_errorSticky$EN)
wsi_S0_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_S0_errorSticky$D_IN;
if (wsi_S0_iMesgCount$EN)
wsi_S0_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_iMesgCount$D_IN;
if (wsi_S0_operateD$EN)
wsi_S0_operateD <= `BSV_ASSIGNMENT_DELAY wsi_S0_operateD$D_IN;
if (wsi_S0_pMesgCount$EN)
wsi_S0_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_pMesgCount$D_IN;
if (wsi_S0_peerIsReady$EN)
wsi_S0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_S0_peerIsReady$D_IN;
if (wsi_S0_reqFifo_countReg$EN)
wsi_S0_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsi_S0_reqFifo_countReg$D_IN;
if (wsi_S0_reqFifo_levelsValid$EN)
wsi_S0_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsi_S0_reqFifo_levelsValid$D_IN;
if (wsi_S0_tBusyCount$EN)
wsi_S0_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_tBusyCount$D_IN;
if (wsi_S0_trafficSticky$EN)
wsi_S0_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wsi_S0_trafficSticky$D_IN;
if (wsi_S0_wordCount$EN)
wsi_S0_wordCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_wordCount$D_IN;
if (wsi_S1_burstKind$EN)
wsi_S1_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_S1_burstKind$D_IN;
if (wsi_S1_errorSticky$EN)
wsi_S1_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_S1_errorSticky$D_IN;
if (wsi_S1_iMesgCount$EN)
wsi_S1_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_iMesgCount$D_IN;
if (wsi_S1_operateD$EN)
wsi_S1_operateD <= `BSV_ASSIGNMENT_DELAY wsi_S1_operateD$D_IN;
if (wsi_S1_pMesgCount$EN)
wsi_S1_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_pMesgCount$D_IN;
if (wsi_S1_peerIsReady$EN)
wsi_S1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_S1_peerIsReady$D_IN;
if (wsi_S1_reqFifo_countReg$EN)
wsi_S1_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsi_S1_reqFifo_countReg$D_IN;
if (wsi_S1_reqFifo_levelsValid$EN)
wsi_S1_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsi_S1_reqFifo_levelsValid$D_IN;
if (wsi_S1_tBusyCount$EN)
wsi_S1_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_tBusyCount$D_IN;
if (wsi_S1_trafficSticky$EN)
wsi_S1_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wsi_S1_trafficSticky$D_IN;
if (wsi_S1_wordCount$EN)
wsi_S1_wordCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_wordCount$D_IN;
end
if (wsi_M0_statusR$EN)
wsi_M0_statusR <= `BSV_ASSIGNMENT_DELAY wsi_M0_statusR$D_IN;
if (wsi_M1_statusR$EN)
wsi_M1_statusR <= `BSV_ASSIGNMENT_DELAY wsi_M1_statusR$D_IN;
if (wsi_S0_mesgWordLength$EN)
wsi_S0_mesgWordLength <= `BSV_ASSIGNMENT_DELAY
wsi_S0_mesgWordLength$D_IN;
if (wsi_S0_statusR$EN)
wsi_S0_statusR <= `BSV_ASSIGNMENT_DELAY wsi_S0_statusR$D_IN;
if (wsi_S1_mesgWordLength$EN)
wsi_S1_mesgWordLength <= `BSV_ASSIGNMENT_DELAY
wsi_S1_mesgWordLength$D_IN;
if (wsi_S1_statusR$EN)
wsi_S1_statusR <= `BSV_ASSIGNMENT_DELAY wsi_S1_statusR$D_IN;
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_S0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_S1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wci_isReset_isInReset$EN)
wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_isReset_isInReset$D_IN;
if (wsi_M0_isReset_isInReset$EN)
wsi_M0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsi_M0_isReset_isInReset$D_IN;
if (wsi_M1_isReset_isInReset$EN)
wsi_M1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsi_M1_isReset_isInReset$D_IN;
if (wsi_S0_isReset_isInReset$EN)
wsi_S0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsi_S0_isReset_isInReset$D_IN;
if (wsi_S1_isReset_isInReset$EN)
wsi_S1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsi_S1_isReset_isInReset$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
splitCtrl = 32'hAAAAAAAA;
wci_cEdge = 3'h2;
wci_cState = 3'h2;
wci_ctlAckReg = 1'h0;
wci_ctlOpActive = 1'h0;
wci_illegalEdge = 1'h0;
wci_isReset_isInReset = 1'h0;
wci_nState = 3'h2;
wci_reqF_countReg = 2'h2;
wci_respF_c_r = 2'h2;
wci_respF_q_0 = 34'h2AAAAAAAA;
wci_respF_q_1 = 34'h2AAAAAAAA;
wci_sFlagReg = 1'h0;
wci_sThreadBusy_d = 1'h0;
wsi_M0_burstKind = 2'h2;
wsi_M0_errorSticky = 1'h0;
wsi_M0_iMesgCount = 32'hAAAAAAAA;
wsi_M0_isReset_isInReset = 1'h0;
wsi_M0_operateD = 1'h0;
wsi_M0_pMesgCount = 32'hAAAAAAAA;
wsi_M0_peerIsReady = 1'h0;
wsi_M0_reqFifo_c_r = 2'h2;
wsi_M0_reqFifo_q_0 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
wsi_M0_reqFifo_q_1 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
wsi_M0_sThreadBusy_d = 1'h0;
wsi_M0_statusR = 8'hAA;
wsi_M0_tBusyCount = 32'hAAAAAAAA;
wsi_M0_trafficSticky = 1'h0;
wsi_M1_burstKind = 2'h2;
wsi_M1_errorSticky = 1'h0;
wsi_M1_iMesgCount = 32'hAAAAAAAA;
wsi_M1_isReset_isInReset = 1'h0;
wsi_M1_operateD = 1'h0;
wsi_M1_pMesgCount = 32'hAAAAAAAA;
wsi_M1_peerIsReady = 1'h0;
wsi_M1_reqFifo_c_r = 2'h2;
wsi_M1_reqFifo_q_0 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
wsi_M1_reqFifo_q_1 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
wsi_M1_sThreadBusy_d = 1'h0;
wsi_M1_statusR = 8'hAA;
wsi_M1_tBusyCount = 32'hAAAAAAAA;
wsi_M1_trafficSticky = 1'h0;
wsi_S0_burstKind = 2'h2;
wsi_S0_errorSticky = 1'h0;
wsi_S0_iMesgCount = 32'hAAAAAAAA;
wsi_S0_isReset_isInReset = 1'h0;
wsi_S0_mesgWordLength = 12'hAAA;
wsi_S0_operateD = 1'h0;
wsi_S0_pMesgCount = 32'hAAAAAAAA;
wsi_S0_peerIsReady = 1'h0;
wsi_S0_reqFifo_countReg = 2'h2;
wsi_S0_reqFifo_levelsValid = 1'h0;
wsi_S0_statusR = 8'hAA;
wsi_S0_tBusyCount = 32'hAAAAAAAA;
wsi_S0_trafficSticky = 1'h0;
wsi_S0_wordCount = 12'hAAA;
wsi_S1_burstKind = 2'h2;
wsi_S1_errorSticky = 1'h0;
wsi_S1_iMesgCount = 32'hAAAAAAAA;
wsi_S1_isReset_isInReset = 1'h0;
wsi_S1_mesgWordLength = 12'hAAA;
wsi_S1_operateD = 1'h0;
wsi_S1_pMesgCount = 32'hAAAAAAAA;
wsi_S1_peerIsReady = 1'h0;
wsi_S1_reqFifo_countReg = 2'h2;
wsi_S1_reqFifo_levelsValid = 1'h0;
wsi_S1_statusR = 8'hAA;
wsi_S1_tBusyCount = 32'hAAAAAAAA;
wsi_S1_trafficSticky = 1'h0;
wsi_S1_wordCount = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_start)
begin
v__h3698 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3698,
wci_reqF$D_OUT[36:34],
wci_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
begin
v__h16289 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
$display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h16289,
wci_reqF$D_OUT[63:32],
wci_reqF$D_OUT[67:64],
wci_reqF$D_OUT[31:0]);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
begin
v__h4017 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h4017,
wci_cEdge,
wci_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
begin
v__h3873 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3873,
wci_cEdge,
wci_cState,
wci_nState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
begin
v__h16444 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
$display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x",
v__h16444,
wci_reqF$D_OUT[63:32],
wci_reqF$D_OUT[67:64],
_theResult____h16428);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
end
// synopsys translate_on
endmodule // mkWsiSplitter2x28B
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/07/2015 06:38:17 PM
// Design Name:
// Module Name: m_port_ultra
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module m_port_ultra_processor_array (
input clk,
input reset_n,
input processorEnable,
input divideEnable,
input divideFinished,
input [32767:0] convexCloud,
output [4095:0] convexHull1,
output [4095:0] convexHull2,
output [4095:0] convexHull3,
output [4095:0] convexHull4,
output [4095:0] convexHull5,
output [4095:0] convexHull6,
output [4095:0] convexHull7,
output [4095:0] convexHull8,
output [8:0] convexHullSize1,
output [8:0] convexHullSize2,
output [8:0] convexHullSize3,
output [8:0] convexHullSize4,
output [8:0] convexHullSize5,
output [8:0] convexHullSize6,
output [8:0] convexHullSize7,
output [8:0] convexHullSize8,
output processorDone1,
output processorDone2,
output processorDone3,
output processorDone4,
output processorDone5,
output processorDone6,
output processorDone7,
output processorDone8
);
// Wires -- processor inputs
wire [4095:0] processorConvexCloud1;
wire [4095:0] processorConvexCloud2;
wire [4095:0] processorConvexCloud3;
wire [4095:0] processorConvexCloud4;
wire [4095:0] processorConvexCloud5;
wire [4095:0] processorConvexCloud6;
wire [4095:0] processorConvexCloud7;
wire [4095:0] processorConvexCloud8;
wire [8:0] processorConvexCloudSize1;
wire [8:0] processorConvexCloudSize2;
wire [8:0] processorConvexCloudSize3;
wire [8:0] processorConvexCloudSize4;
wire [8:0] processorConvexCloudSize5;
wire [8:0] processorConvexCloudSize6;
wire [8:0] processorConvexCloudSize7;
wire [8:0] processorConvexCloudSize8;
// Assign wires
assign processorConvexCloud1 = convexCloud[4095:0];
assign processorConvexCloud2 = convexCloud[8191:4096];
assign processorConvexCloud3 = convexCloud[12287:8192];
assign processorConvexCloud4 = convexCloud[16383:12288];
assign processorConvexCloud5 = convexCloud[20479:16384];
assign processorConvexCloud6 = convexCloud[24575:20480];
assign processorConvexCloud7 = convexCloud[28671:24576];
assign processorConvexCloud8 = convexCloud[32767:28672];
assign processorConvexCloudSize1 = 9'b100000000;
assign processorConvexCloudSize2 = 9'b100000000;
assign processorConvexCloudSize3 = 9'b100000000;
assign processorConvexCloudSize4 = 9'b100000000;
assign processorConvexCloudSize5 = 9'b100000000;
assign processorConvexCloudSize6 = 9'b100000000;
assign processorConvexCloudSize7 = 9'b100000000;
assign processorConvexCloudSize8 = 9'b100000000;
// Declare processor unit 1
m_port_ultra_quickhull quickhullProcessor1 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.convexCloud (processorConvexCloud1),
.convexCloudSize (processorConvexCloudSize1),
.convexPointsOutput (convexHull1),
.convexSetSizeOutput (convexHullSize1),
.processorDone (processorDone1)
);
// Declare processor unit 2
m_port_ultra_quickhull quickhullProcessor2 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.convexCloud (processorConvexCloud2),
.convexCloudSize (processorConvexCloudSize2),
.convexPointsOutput (convexHull2),
.convexSetSizeOutput (convexHullSize2),
.processorDone (processorDone2)
);
// Declare processor unit 3
m_port_ultra_quickhull quickhullProcessor3 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.convexCloud (processorConvexCloud3),
.convexCloudSize (processorConvexCloudSize3),
.convexPointsOutput (convexHull3),
.convexSetSizeOutput (convexHullSize3),
.processorDone (processorDone3)
);
// Declare processor unit 4
m_port_ultra_quickhull quickhullProcessor4 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.convexCloud (processorConvexCloud4),
.convexCloudSize (processorConvexCloudSize4),
.convexPointsOutput (convexHull4),
.convexSetSizeOutput (convexHullSize4),
.processorDone (processorDone4)
);
// Declare processor unit 5
m_port_ultra_quickhull quickhullProcessor5 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.convexCloud (processorConvexCloud5),
.convexCloudSize (processorConvexCloudSize5),
.convexPointsOutput (convexHull5),
.convexSetSizeOutput (convexHullSize5),
.processorDone (processorDone5)
);
// Declare processor unit 6
m_port_ultra_quickhull quickhullProcessor6 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.convexCloud (processorConvexCloud6),
.convexCloudSize (processorConvexCloudSize6),
.convexPointsOutput (convexHull6),
.convexSetSizeOutput (convexHullSize6),
.processorDone (processorDone6)
);
// Declare processor unit 7
m_port_ultra_quickhull quickhullProcessor7 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.convexCloud (processorConvexCloud7),
.convexCloudSize (processorConvexCloudSize7),
.convexPointsOutput (convexHull7),
.convexSetSizeOutput (convexHullSize7),
.processorDone (processorDone7)
);
// Declare processor unit 8
m_port_ultra_quickhull quickhullProcessor8 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.convexCloud (processorConvexCloud8),
.convexCloudSize (processorConvexCloudSize8),
.convexPointsOutput (convexHull8),
.convexSetSizeOutput (convexHullSize8),
.processorDone (processorDone8)
);
endmodule
|
//#############################################################################
//# Function: Parallel to Serial Converter #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE in OH! repositpory) #
//#############################################################################
module oh_par2ser #(parameter PW = 64, // parallel packet width
parameter SW = 1, // serial packet width
parameter CW = $clog2(PW/SW) // serialization factor
)
(
input clk, // sampling clock
input nreset, // async active low reset
input [PW-1:0] din, // parallel data
output [SW-1:0] dout, // serial output data
output access_out,// output data valid
input load, // load parallel data (priority)
input shift, // shift data
input [7:0] datasize, // size of data to shift
input lsbfirst, // lsb first order
input fill, // fill bit
input wait_in, // wait input
output wait_out // wait output (wait in | serial wait)
);
// local wires
reg [PW-1:0] shiftreg;
reg [CW-1:0] count;
wire start_transfer;
wire busy;
// start serialization
assign start_transfer = load & ~wait_in & ~busy;
//transfer counter
always @ (posedge clk or negedge nreset)
if(!nreset)
count[CW-1:0] <= 'b0;
else if(start_transfer)
count[CW-1:0] <= datasize[CW-1:0]; //one "SW sized" transfers
else if(shift & busy)
count[CW-1:0] <= count[CW-1:0] - 1'b1;
//output data is valid while count > 0
assign busy = |count[CW-1:0];
//data valid while shifter is busy
assign access_out = busy;
//wait until valid data is finished
assign wait_out = wait_in | busy;
// shift register
always @ (posedge clk)
if(start_transfer)
shiftreg[PW-1:0] = din[PW-1:0];
else if(shift & lsbfirst)
shiftreg[PW-1:0] = {{(SW){fill}}, shiftreg[PW-1:SW]};
else if(shift)
shiftreg[PW-1:0] = {shiftreg[PW-SW-1:0],{(SW){fill}}};
assign dout[SW-1:0] = lsbfirst ? shiftreg[SW-1:0] :
shiftreg[PW-1:PW-SW];
endmodule // oh_par2ser
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Todd Strader.
interface foo_intf;
logic a;
modport source (
output a
);
modport sink (
input a
);
endinterface
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam N = 4;
logic [N-1:0] a_in;
logic [N-1:0] a_out;
logic [N-1:0] ack_out;
foo_intf foos [N-1:0] ();
generate
genvar i;
for (i = 0; i < N; i++) begin : someLoop
assign ack_out[i] = a_in[i];
assign foos[i].a = a_in[i];
assign a_out[i] = foos[i].a;
end
endgenerate
always @(posedge clk) begin
if (ack_out != a_out) begin
$display("%%Error: Interface and non-interface paths do not match: 0b%b 0b%b",
ack_out, a_out);
$stop;
end
end
initial a_in = '0;
always @(posedge clk) begin
a_in <= a_in + { {N-1 {1'b0}}, 1'b1 };
if (& a_in) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__OR3B_BEHAVIORAL_PP_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X , B, A, not0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3B_BEHAVIORAL_PP_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_out_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// FPU output control logic.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_out_ctl (
d8stg_fdiv_in,
m6stg_fmul_in,
a6stg_fadd_in,
div_id_out_in,
m6stg_id_in,
add_id_out_in,
arst_l,
grst_l,
rclk,
fp_cpx_req_cq,
req_thread,
dest_rdy,
add_dest_rdy,
mul_dest_rdy,
div_dest_rdy,
se,
si,
so
);
input d8stg_fdiv_in; // div pipe output request next cycle
input m6stg_fmul_in; // mul pipe output request next cycle
input a6stg_fadd_in; // add pipe output request next cycle
input [9:0] div_id_out_in; // div pipe output ID next cycle
input [9:0] m6stg_id_in; // mul pipe output ID next cycle
input [9:0] add_id_out_in; // add pipe output ID next cycle
input arst_l; // global async. reset- asserted low
input grst_l; // global sync. reset- asserted low
input rclk; // global clock
output [7:0] fp_cpx_req_cq; // FPU result request to CPX
output [1:0] req_thread; // thread ID of result req this cycle
output [2:0] dest_rdy; // pipe with result request this cycle
output add_dest_rdy; // add pipe result request this cycle
output mul_dest_rdy; // mul pipe result request this cycle
output div_dest_rdy; // div pipe result request this cycle
input se; // scan_enable
input si; // scan in
output so; // scan out
wire reset;
wire add_req_in;
wire add_req_step;
wire add_req;
wire div_req_sel;
wire mul_req_sel;
wire add_req_sel;
wire [9:0] out_id;
wire [7:0] fp_cpx_req_cq;
wire [1:0] req_thread;
wire [2:0] dest_rdy_in;
wire [2:0] dest_rdy;
wire add_dest_rdy;
wire mul_dest_rdy;
wire div_dest_rdy;
dffrl_async #(1) dffrl_out_ctl (
.din (grst_l),
.clk (rclk),
.rst_l(arst_l),
.q (out_ctl_rst_l),
.se (se),
.si (),
.so ()
);
assign reset= (!out_ctl_rst_l);
///////////////////////////////////////////////////////////////////////////////
//
// Arbitrate for the output.
//
// Top priority- divide.
// Low priority- round robin arbitration between the add and multiply
// pipes.
//
///////////////////////////////////////////////////////////////////////////////
assign add_req_in= (!add_req);
assign add_req_step= add_req_sel || mul_req_sel;
dffre #(1) i_add_req (
.din (add_req_in),
.en (add_req_step),
.rst (reset),
.clk (rclk),
.q (add_req),
.se (se),
.si (),
.so ()
);
assign div_req_sel= d8stg_fdiv_in;
assign mul_req_sel= m6stg_fmul_in
&& ((!add_req) || (!a6stg_fadd_in))
&& (!div_req_sel);
assign add_req_sel= a6stg_fadd_in
&& (add_req || (!m6stg_fmul_in))
&& (!div_req_sel);
///////////////////////////////////////////////////////////////////////////////
//
// Generate the request.
//
// Input to the output request (CQ) stage.
//
///////////////////////////////////////////////////////////////////////////////
assign out_id[9:0]= ({10{div_req_sel}}
& div_id_out_in[9:0])
| ({10{mul_req_sel}}
& m6stg_id_in[9:0])
| ({10{add_req_sel}}
& add_id_out_in[9:0]);
dff #(8) i_fp_cpx_req_cq (
.din (out_id[9:2]),
.clk (rclk),
.q (fp_cpx_req_cq[7:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Capture the thread.
//
// Input to the output request (CQ) stage.
//
///////////////////////////////////////////////////////////////////////////////
dff #(2) i_req_thread (
.din (out_id[1:0]),
.clk (rclk),
.q (req_thread[1:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Capture the pipe that wins the output request.
//
// Input to the output request (CQ) stage.
//
///////////////////////////////////////////////////////////////////////////////
assign dest_rdy_in[2:0]= {div_req_sel, mul_req_sel, add_req_sel};
dff #(3) i_dest_rdy (
.din (dest_rdy_in[2:0]),
.clk (rclk),
.q (dest_rdy[2:0]),
.se (se),
.si (),
.so ()
);
dff i_add_dest_rdy (
.din (add_req_sel),
.clk (rclk),
.q (add_dest_rdy),
.se (se),
.si (),
.so ()
);
dff i_mul_dest_rdy (
.din (mul_req_sel),
.clk (rclk),
.q (mul_dest_rdy),
.se (se),
.si (),
.so ()
);
dff i_div_dest_rdy (
.din (div_req_sel),
.clk (rclk),
.q (div_dest_rdy),
.se (se),
.si (),
.so ()
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S6S_1_V
`define SKY130_FD_SC_HS__DLYMETAL6S6S_1_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog wrapper for dlymetal6s6s with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlymetal6s6s.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlymetal6s6s_1 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__dlymetal6s6s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlymetal6s6s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlymetal6s6s base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S6S_1_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tb_navre();
reg sys_clk;
initial sys_clk = 1'b1;
always #5 sys_clk = ~sys_clk;
reg sys_rst;
wire pmem_ce;
wire [9:0] pmem_a;
reg [15:0] pmem_d;
reg [15:0] pmem[0:1023];
always @(posedge sys_clk) begin
if(pmem_ce)
pmem_d <= pmem[pmem_a];
end
wire dmem_we;
wire [9:0] dmem_a;
reg [7:0] dmem_di;
wire [7:0] dmem_do;
reg [7:0] dmem[0:1023];
always @(posedge sys_clk) begin
if(dmem_we) begin
//$display("DMEM WRITE: adr=%d dat=%d", dmem_a, dmem_do);
dmem[dmem_a] <= dmem_do;
end
dmem_di <= dmem[dmem_a];
end
wire io_re;
wire io_we;
wire [5:0] io_a;
wire [7:0] io_do;
reg [7:0] io_di;
reg end_of_test;
always @(posedge sys_clk) begin
end_of_test <= 1'b0;
if(~sys_rst) begin
if(io_re) begin
$display("IO READ adr=%x", io_a);
if((io_a == 6'h11)|(io_a == 6'h12))
io_di <= 8'hff;
else
io_di <= io_a;
end
if(io_we) begin
$display("IO WRITE adr=%x dat=%x", io_a, io_do);
if((io_a == 0) && (io_do == 254))
end_of_test <= 1'b1;
end
end
end
softusb_navre #(
.pmem_width(10),
.dmem_width(10)
) dut (
.clk(sys_clk),
.rst(sys_rst),
.pmem_ce(pmem_ce),
.pmem_a(pmem_a),
.pmem_d(pmem_d),
.dmem_we(dmem_we),
.dmem_a(dmem_a),
.dmem_di(dmem_di),
.dmem_do(dmem_do),
.io_re(io_re),
.io_we(io_we),
.io_a(io_a),
.io_do(io_do),
.io_di(io_di)
);
initial begin
$display("Test: Fibonacci (assembler)");
$readmemh("fib.rom", pmem);
sys_rst = 1'b1;
#15;
sys_rst = 1'b0;
@(posedge end_of_test);
$display("Test: Fibonacci (C)");
$readmemh("fibc.rom", pmem);
sys_rst = 1'b1;
#15;
sys_rst = 1'b0;
@(posedge end_of_test);
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EBUFN_TB_V
`define SKY130_FD_SC_MS__EBUFN_TB_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__ebufn.v"
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ms__ebufn dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EBUFN_TB_V
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1
// RDY_server_reset_response_get O 1 reg
// imem_valid O 1
// imem_is_i32_not_i16 O 1 const
// imem_pc O 64
// imem_instr O 32
// imem_exc O 1
// imem_exc_code O 4
// imem_tval O 64
// imem_master_awvalid O 1 reg
// imem_master_awid O 16 reg
// imem_master_awaddr O 64 reg
// imem_master_awlen O 8 reg
// imem_master_awsize O 3 reg
// imem_master_awburst O 2 reg
// imem_master_awlock O 1 reg
// imem_master_awcache O 4 reg
// imem_master_awprot O 3 reg
// imem_master_awqos O 4 reg
// imem_master_awregion O 4 reg
// imem_master_wvalid O 1 reg
// imem_master_wdata O 64 reg
// imem_master_wstrb O 8 reg
// imem_master_wlast O 1 reg
// imem_master_bready O 1 reg
// imem_master_arvalid O 1 reg
// imem_master_arid O 16 reg
// imem_master_araddr O 64 reg
// imem_master_arlen O 8 reg
// imem_master_arsize O 3 reg
// imem_master_arburst O 2 reg
// imem_master_arlock O 1 reg
// imem_master_arcache O 4 reg
// imem_master_arprot O 3 reg
// imem_master_arqos O 4 reg
// imem_master_arregion O 4 reg
// imem_master_rready O 1 reg
// dmem_valid O 1
// dmem_word64 O 64
// dmem_st_amo_val O 64
// dmem_exc O 1
// dmem_exc_code O 4
// mem_master_awvalid O 1
// mem_master_awid O 16 reg
// mem_master_awaddr O 64 reg
// mem_master_awlen O 8 reg
// mem_master_awsize O 3 reg
// mem_master_awburst O 2 reg
// mem_master_awlock O 1 reg
// mem_master_awcache O 4 reg
// mem_master_awprot O 3 reg
// mem_master_awqos O 4 reg
// mem_master_awregion O 4 reg
// mem_master_wvalid O 1
// mem_master_wdata O 64 reg
// mem_master_wstrb O 8 reg
// mem_master_wlast O 1 reg
// mem_master_bready O 1
// mem_master_arvalid O 1
// mem_master_arid O 16 reg
// mem_master_araddr O 64 reg
// mem_master_arlen O 8 reg
// mem_master_arsize O 3 reg
// mem_master_arburst O 2 reg
// mem_master_arlock O 1 reg
// mem_master_arcache O 4 reg
// mem_master_arprot O 3 reg
// mem_master_arqos O 4 reg
// mem_master_arregion O 4 reg
// mem_master_rready O 1
// RDY_server_fence_i_request_put O 1 const
// RDY_server_fence_i_response_get O 1 const
// RDY_server_fence_request_put O 1 const
// RDY_server_fence_response_get O 1 const
// RDY_sfence_vma_server_request_put O 1 const
// RDY_sfence_vma_server_response_get O 1 const
// dma_server_awready O 1 reg
// dma_server_wready O 1 reg
// dma_server_bvalid O 1 reg
// dma_server_bid O 16 reg
// dma_server_bresp O 2 reg
// dma_server_arready O 1 reg
// dma_server_rvalid O 1 reg
// dma_server_rid O 16 reg
// dma_server_rdata O 512 reg
// dma_server_rresp O 2 reg
// dma_server_rlast O 1 reg
// RDY_set_watch_tohost O 1 const
// mv_tohost_value O 64 reg
// RDY_mv_tohost_value O 1 const
// RDY_ma_ddr4_ready O 1 const
// mv_status O 8
// CLK I 1 clock
// RST_N I 1 reset
// imem_req_f3 I 3 unused
// imem_req_addr I 64
// imem_req_priv I 2
// imem_req_sstatus_SUM I 1
// imem_req_mstatus_MXR I 1
// imem_req_satp I 64
// imem_master_awready I 1
// imem_master_wready I 1
// imem_master_bvalid I 1
// imem_master_bid I 16 reg
// imem_master_bresp I 2 reg
// imem_master_arready I 1
// imem_master_rvalid I 1
// imem_master_rid I 16 reg
// imem_master_rdata I 64 reg
// imem_master_rresp I 2 reg
// imem_master_rlast I 1 reg
// dmem_req_op I 2
// dmem_req_f3 I 3
// dmem_req_amo_funct7 I 7
// dmem_req_addr I 64
// dmem_req_store_value I 64
// dmem_req_priv I 2
// dmem_req_sstatus_SUM I 1
// dmem_req_mstatus_MXR I 1
// dmem_req_satp I 64
// mem_master_awready I 1
// mem_master_wready I 1
// mem_master_bvalid I 1
// mem_master_bid I 16 reg
// mem_master_bresp I 2 reg
// mem_master_arready I 1
// mem_master_rvalid I 1
// mem_master_rid I 16 reg
// mem_master_rdata I 64 reg
// mem_master_rresp I 2 reg
// mem_master_rlast I 1 reg
// server_fence_request_put I 8 unused
// dma_server_awvalid I 1
// dma_server_awid I 16 reg
// dma_server_awaddr I 64 reg
// dma_server_awlen I 8 reg
// dma_server_awsize I 3 reg
// dma_server_awburst I 2 reg
// dma_server_awlock I 1 reg
// dma_server_awcache I 4 reg
// dma_server_awprot I 3 reg
// dma_server_awqos I 4 reg
// dma_server_awregion I 4 reg
// dma_server_wvalid I 1
// dma_server_wdata I 512 reg
// dma_server_wstrb I 64 reg
// dma_server_wlast I 1 reg
// dma_server_bready I 1
// dma_server_arvalid I 1
// dma_server_arid I 16 reg
// dma_server_araddr I 64 reg
// dma_server_arlen I 8 reg
// dma_server_arsize I 3 reg
// dma_server_arburst I 2 reg
// dma_server_arlock I 1 reg
// dma_server_arcache I 4 reg
// dma_server_arprot I 3 reg
// dma_server_arqos I 4 reg
// dma_server_arregion I 4 reg
// dma_server_rready I 1
// set_watch_tohost_watch_tohost I 1 reg
// set_watch_tohost_tohost_addr I 64 reg
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_imem_req I 1
// EN_dmem_req I 1
// EN_server_fence_i_request_put I 1 unused
// EN_server_fence_i_response_get I 1 unused
// EN_server_fence_request_put I 1 unused
// EN_server_fence_response_get I 1 unused
// EN_sfence_vma_server_request_put I 1
// EN_sfence_vma_server_response_get I 1 unused
// EN_set_watch_tohost I 1
// EN_ma_ddr4_ready I 1
//
// Combinational paths from inputs to outputs:
// (mem_master_awready, mem_master_wready) -> mem_master_bready
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkNear_Mem(CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
imem_req_f3,
imem_req_addr,
imem_req_priv,
imem_req_sstatus_SUM,
imem_req_mstatus_MXR,
imem_req_satp,
EN_imem_req,
imem_valid,
imem_is_i32_not_i16,
imem_pc,
imem_instr,
imem_exc,
imem_exc_code,
imem_tval,
imem_master_awvalid,
imem_master_awid,
imem_master_awaddr,
imem_master_awlen,
imem_master_awsize,
imem_master_awburst,
imem_master_awlock,
imem_master_awcache,
imem_master_awprot,
imem_master_awqos,
imem_master_awregion,
imem_master_awready,
imem_master_wvalid,
imem_master_wdata,
imem_master_wstrb,
imem_master_wlast,
imem_master_wready,
imem_master_bvalid,
imem_master_bid,
imem_master_bresp,
imem_master_bready,
imem_master_arvalid,
imem_master_arid,
imem_master_araddr,
imem_master_arlen,
imem_master_arsize,
imem_master_arburst,
imem_master_arlock,
imem_master_arcache,
imem_master_arprot,
imem_master_arqos,
imem_master_arregion,
imem_master_arready,
imem_master_rvalid,
imem_master_rid,
imem_master_rdata,
imem_master_rresp,
imem_master_rlast,
imem_master_rready,
dmem_req_op,
dmem_req_f3,
dmem_req_amo_funct7,
dmem_req_addr,
dmem_req_store_value,
dmem_req_priv,
dmem_req_sstatus_SUM,
dmem_req_mstatus_MXR,
dmem_req_satp,
EN_dmem_req,
dmem_valid,
dmem_word64,
dmem_st_amo_val,
dmem_exc,
dmem_exc_code,
mem_master_awvalid,
mem_master_awid,
mem_master_awaddr,
mem_master_awlen,
mem_master_awsize,
mem_master_awburst,
mem_master_awlock,
mem_master_awcache,
mem_master_awprot,
mem_master_awqos,
mem_master_awregion,
mem_master_awready,
mem_master_wvalid,
mem_master_wdata,
mem_master_wstrb,
mem_master_wlast,
mem_master_wready,
mem_master_bvalid,
mem_master_bid,
mem_master_bresp,
mem_master_bready,
mem_master_arvalid,
mem_master_arid,
mem_master_araddr,
mem_master_arlen,
mem_master_arsize,
mem_master_arburst,
mem_master_arlock,
mem_master_arcache,
mem_master_arprot,
mem_master_arqos,
mem_master_arregion,
mem_master_arready,
mem_master_rvalid,
mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast,
mem_master_rready,
EN_server_fence_i_request_put,
RDY_server_fence_i_request_put,
EN_server_fence_i_response_get,
RDY_server_fence_i_response_get,
server_fence_request_put,
EN_server_fence_request_put,
RDY_server_fence_request_put,
EN_server_fence_response_get,
RDY_server_fence_response_get,
EN_sfence_vma_server_request_put,
RDY_sfence_vma_server_request_put,
EN_sfence_vma_server_response_get,
RDY_sfence_vma_server_response_get,
dma_server_awvalid,
dma_server_awid,
dma_server_awaddr,
dma_server_awlen,
dma_server_awsize,
dma_server_awburst,
dma_server_awlock,
dma_server_awcache,
dma_server_awprot,
dma_server_awqos,
dma_server_awregion,
dma_server_awready,
dma_server_wvalid,
dma_server_wdata,
dma_server_wstrb,
dma_server_wlast,
dma_server_wready,
dma_server_bvalid,
dma_server_bid,
dma_server_bresp,
dma_server_bready,
dma_server_arvalid,
dma_server_arid,
dma_server_araddr,
dma_server_arlen,
dma_server_arsize,
dma_server_arburst,
dma_server_arlock,
dma_server_arcache,
dma_server_arprot,
dma_server_arqos,
dma_server_arregion,
dma_server_arready,
dma_server_rvalid,
dma_server_rid,
dma_server_rdata,
dma_server_rresp,
dma_server_rlast,
dma_server_rready,
set_watch_tohost_watch_tohost,
set_watch_tohost_tohost_addr,
EN_set_watch_tohost,
RDY_set_watch_tohost,
mv_tohost_value,
RDY_mv_tohost_value,
EN_ma_ddr4_ready,
RDY_ma_ddr4_ready,
mv_status);
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method imem_req
input [2 : 0] imem_req_f3;
input [63 : 0] imem_req_addr;
input [1 : 0] imem_req_priv;
input imem_req_sstatus_SUM;
input imem_req_mstatus_MXR;
input [63 : 0] imem_req_satp;
input EN_imem_req;
// value method imem_valid
output imem_valid;
// value method imem_is_i32_not_i16
output imem_is_i32_not_i16;
// value method imem_pc
output [63 : 0] imem_pc;
// value method imem_instr
output [31 : 0] imem_instr;
// value method imem_exc
output imem_exc;
// value method imem_exc_code
output [3 : 0] imem_exc_code;
// value method imem_tval
output [63 : 0] imem_tval;
// value method imem_master_m_awvalid
output imem_master_awvalid;
// value method imem_master_m_awid
output [15 : 0] imem_master_awid;
// value method imem_master_m_awaddr
output [63 : 0] imem_master_awaddr;
// value method imem_master_m_awlen
output [7 : 0] imem_master_awlen;
// value method imem_master_m_awsize
output [2 : 0] imem_master_awsize;
// value method imem_master_m_awburst
output [1 : 0] imem_master_awburst;
// value method imem_master_m_awlock
output imem_master_awlock;
// value method imem_master_m_awcache
output [3 : 0] imem_master_awcache;
// value method imem_master_m_awprot
output [2 : 0] imem_master_awprot;
// value method imem_master_m_awqos
output [3 : 0] imem_master_awqos;
// value method imem_master_m_awregion
output [3 : 0] imem_master_awregion;
// value method imem_master_m_awuser
// action method imem_master_m_awready
input imem_master_awready;
// value method imem_master_m_wvalid
output imem_master_wvalid;
// value method imem_master_m_wdata
output [63 : 0] imem_master_wdata;
// value method imem_master_m_wstrb
output [7 : 0] imem_master_wstrb;
// value method imem_master_m_wlast
output imem_master_wlast;
// value method imem_master_m_wuser
// action method imem_master_m_wready
input imem_master_wready;
// action method imem_master_m_bvalid
input imem_master_bvalid;
input [15 : 0] imem_master_bid;
input [1 : 0] imem_master_bresp;
// value method imem_master_m_bready
output imem_master_bready;
// value method imem_master_m_arvalid
output imem_master_arvalid;
// value method imem_master_m_arid
output [15 : 0] imem_master_arid;
// value method imem_master_m_araddr
output [63 : 0] imem_master_araddr;
// value method imem_master_m_arlen
output [7 : 0] imem_master_arlen;
// value method imem_master_m_arsize
output [2 : 0] imem_master_arsize;
// value method imem_master_m_arburst
output [1 : 0] imem_master_arburst;
// value method imem_master_m_arlock
output imem_master_arlock;
// value method imem_master_m_arcache
output [3 : 0] imem_master_arcache;
// value method imem_master_m_arprot
output [2 : 0] imem_master_arprot;
// value method imem_master_m_arqos
output [3 : 0] imem_master_arqos;
// value method imem_master_m_arregion
output [3 : 0] imem_master_arregion;
// value method imem_master_m_aruser
// action method imem_master_m_arready
input imem_master_arready;
// action method imem_master_m_rvalid
input imem_master_rvalid;
input [15 : 0] imem_master_rid;
input [63 : 0] imem_master_rdata;
input [1 : 0] imem_master_rresp;
input imem_master_rlast;
// value method imem_master_m_rready
output imem_master_rready;
// action method dmem_req
input [1 : 0] dmem_req_op;
input [2 : 0] dmem_req_f3;
input [6 : 0] dmem_req_amo_funct7;
input [63 : 0] dmem_req_addr;
input [63 : 0] dmem_req_store_value;
input [1 : 0] dmem_req_priv;
input dmem_req_sstatus_SUM;
input dmem_req_mstatus_MXR;
input [63 : 0] dmem_req_satp;
input EN_dmem_req;
// value method dmem_valid
output dmem_valid;
// value method dmem_word64
output [63 : 0] dmem_word64;
// value method dmem_st_amo_val
output [63 : 0] dmem_st_amo_val;
// value method dmem_exc
output dmem_exc;
// value method dmem_exc_code
output [3 : 0] dmem_exc_code;
// value method mem_master_m_awvalid
output mem_master_awvalid;
// value method mem_master_m_awid
output [15 : 0] mem_master_awid;
// value method mem_master_m_awaddr
output [63 : 0] mem_master_awaddr;
// value method mem_master_m_awlen
output [7 : 0] mem_master_awlen;
// value method mem_master_m_awsize
output [2 : 0] mem_master_awsize;
// value method mem_master_m_awburst
output [1 : 0] mem_master_awburst;
// value method mem_master_m_awlock
output mem_master_awlock;
// value method mem_master_m_awcache
output [3 : 0] mem_master_awcache;
// value method mem_master_m_awprot
output [2 : 0] mem_master_awprot;
// value method mem_master_m_awqos
output [3 : 0] mem_master_awqos;
// value method mem_master_m_awregion
output [3 : 0] mem_master_awregion;
// value method mem_master_m_awuser
// action method mem_master_m_awready
input mem_master_awready;
// value method mem_master_m_wvalid
output mem_master_wvalid;
// value method mem_master_m_wdata
output [63 : 0] mem_master_wdata;
// value method mem_master_m_wstrb
output [7 : 0] mem_master_wstrb;
// value method mem_master_m_wlast
output mem_master_wlast;
// value method mem_master_m_wuser
// action method mem_master_m_wready
input mem_master_wready;
// action method mem_master_m_bvalid
input mem_master_bvalid;
input [15 : 0] mem_master_bid;
input [1 : 0] mem_master_bresp;
// value method mem_master_m_bready
output mem_master_bready;
// value method mem_master_m_arvalid
output mem_master_arvalid;
// value method mem_master_m_arid
output [15 : 0] mem_master_arid;
// value method mem_master_m_araddr
output [63 : 0] mem_master_araddr;
// value method mem_master_m_arlen
output [7 : 0] mem_master_arlen;
// value method mem_master_m_arsize
output [2 : 0] mem_master_arsize;
// value method mem_master_m_arburst
output [1 : 0] mem_master_arburst;
// value method mem_master_m_arlock
output mem_master_arlock;
// value method mem_master_m_arcache
output [3 : 0] mem_master_arcache;
// value method mem_master_m_arprot
output [2 : 0] mem_master_arprot;
// value method mem_master_m_arqos
output [3 : 0] mem_master_arqos;
// value method mem_master_m_arregion
output [3 : 0] mem_master_arregion;
// value method mem_master_m_aruser
// action method mem_master_m_arready
input mem_master_arready;
// action method mem_master_m_rvalid
input mem_master_rvalid;
input [15 : 0] mem_master_rid;
input [63 : 0] mem_master_rdata;
input [1 : 0] mem_master_rresp;
input mem_master_rlast;
// value method mem_master_m_rready
output mem_master_rready;
// action method server_fence_i_request_put
input EN_server_fence_i_request_put;
output RDY_server_fence_i_request_put;
// action method server_fence_i_response_get
input EN_server_fence_i_response_get;
output RDY_server_fence_i_response_get;
// action method server_fence_request_put
input [7 : 0] server_fence_request_put;
input EN_server_fence_request_put;
output RDY_server_fence_request_put;
// action method server_fence_response_get
input EN_server_fence_response_get;
output RDY_server_fence_response_get;
// action method sfence_vma_server_request_put
input EN_sfence_vma_server_request_put;
output RDY_sfence_vma_server_request_put;
// action method sfence_vma_server_response_get
input EN_sfence_vma_server_response_get;
output RDY_sfence_vma_server_response_get;
// action method dma_server_m_awvalid
input dma_server_awvalid;
input [15 : 0] dma_server_awid;
input [63 : 0] dma_server_awaddr;
input [7 : 0] dma_server_awlen;
input [2 : 0] dma_server_awsize;
input [1 : 0] dma_server_awburst;
input dma_server_awlock;
input [3 : 0] dma_server_awcache;
input [2 : 0] dma_server_awprot;
input [3 : 0] dma_server_awqos;
input [3 : 0] dma_server_awregion;
// value method dma_server_m_awready
output dma_server_awready;
// action method dma_server_m_wvalid
input dma_server_wvalid;
input [511 : 0] dma_server_wdata;
input [63 : 0] dma_server_wstrb;
input dma_server_wlast;
// value method dma_server_m_wready
output dma_server_wready;
// value method dma_server_m_bvalid
output dma_server_bvalid;
// value method dma_server_m_bid
output [15 : 0] dma_server_bid;
// value method dma_server_m_bresp
output [1 : 0] dma_server_bresp;
// value method dma_server_m_buser
// action method dma_server_m_bready
input dma_server_bready;
// action method dma_server_m_arvalid
input dma_server_arvalid;
input [15 : 0] dma_server_arid;
input [63 : 0] dma_server_araddr;
input [7 : 0] dma_server_arlen;
input [2 : 0] dma_server_arsize;
input [1 : 0] dma_server_arburst;
input dma_server_arlock;
input [3 : 0] dma_server_arcache;
input [2 : 0] dma_server_arprot;
input [3 : 0] dma_server_arqos;
input [3 : 0] dma_server_arregion;
// value method dma_server_m_arready
output dma_server_arready;
// value method dma_server_m_rvalid
output dma_server_rvalid;
// value method dma_server_m_rid
output [15 : 0] dma_server_rid;
// value method dma_server_m_rdata
output [511 : 0] dma_server_rdata;
// value method dma_server_m_rresp
output [1 : 0] dma_server_rresp;
// value method dma_server_m_rlast
output dma_server_rlast;
// value method dma_server_m_ruser
// action method dma_server_m_rready
input dma_server_rready;
// action method set_watch_tohost
input set_watch_tohost_watch_tohost;
input [63 : 0] set_watch_tohost_tohost_addr;
input EN_set_watch_tohost;
output RDY_set_watch_tohost;
// value method mv_tohost_value
output [63 : 0] mv_tohost_value;
output RDY_mv_tohost_value;
// action method ma_ddr4_ready
input EN_ma_ddr4_ready;
output RDY_ma_ddr4_ready;
// value method mv_status
output [7 : 0] mv_status;
// signals for module outputs
wire [511 : 0] dma_server_rdata;
wire [63 : 0] dmem_st_amo_val,
dmem_word64,
imem_master_araddr,
imem_master_awaddr,
imem_master_wdata,
imem_pc,
imem_tval,
mem_master_araddr,
mem_master_awaddr,
mem_master_wdata,
mv_tohost_value;
wire [31 : 0] imem_instr;
wire [15 : 0] dma_server_bid,
dma_server_rid,
imem_master_arid,
imem_master_awid,
mem_master_arid,
mem_master_awid;
wire [7 : 0] imem_master_arlen,
imem_master_awlen,
imem_master_wstrb,
mem_master_arlen,
mem_master_awlen,
mem_master_wstrb,
mv_status;
wire [3 : 0] dmem_exc_code,
imem_exc_code,
imem_master_arcache,
imem_master_arqos,
imem_master_arregion,
imem_master_awcache,
imem_master_awqos,
imem_master_awregion,
mem_master_arcache,
mem_master_arqos,
mem_master_arregion,
mem_master_awcache,
mem_master_awqos,
mem_master_awregion;
wire [2 : 0] imem_master_arprot,
imem_master_arsize,
imem_master_awprot,
imem_master_awsize,
mem_master_arprot,
mem_master_arsize,
mem_master_awprot,
mem_master_awsize;
wire [1 : 0] dma_server_bresp,
dma_server_rresp,
imem_master_arburst,
imem_master_awburst,
mem_master_arburst,
mem_master_awburst;
wire RDY_ma_ddr4_ready,
RDY_mv_tohost_value,
RDY_server_fence_i_request_put,
RDY_server_fence_i_response_get,
RDY_server_fence_request_put,
RDY_server_fence_response_get,
RDY_server_reset_request_put,
RDY_server_reset_response_get,
RDY_set_watch_tohost,
RDY_sfence_vma_server_request_put,
RDY_sfence_vma_server_response_get,
dma_server_arready,
dma_server_awready,
dma_server_bvalid,
dma_server_rlast,
dma_server_rvalid,
dma_server_wready,
dmem_exc,
dmem_valid,
imem_exc,
imem_is_i32_not_i16,
imem_master_arlock,
imem_master_arvalid,
imem_master_awlock,
imem_master_awvalid,
imem_master_bready,
imem_master_rready,
imem_master_wlast,
imem_master_wvalid,
imem_valid,
mem_master_arlock,
mem_master_arvalid,
mem_master_awlock,
mem_master_awvalid,
mem_master_bready,
mem_master_rready,
mem_master_wlast,
mem_master_wvalid;
// inlined wires
wire [581 : 0] enqDst_1_0_lat_0$wget;
wire [580 : 0] propDstData_1_0_lat_0$wget,
propDstData_1_1_lat_0$wget,
propDstData_1_2_lat_0$wget;
wire [74 : 0] enqDst_0_lat_0$wget;
wire [73 : 0] propDstData_0_lat_0$wget,
propDstData_1_lat_0$wget,
propDstData_2_lat_0$wget;
wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1,
llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1,
llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read;
wire llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write,
llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read,
llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read,
llc_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write,
llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read,
llc_axi4_adapter_master_xactor_crg_rd_data_full$port3__read,
llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write,
llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read,
llc_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read,
llc_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write,
llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read,
llc_axi4_adapter_master_xactor_crg_wr_data_full$port3__read,
llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write,
llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read,
llc_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read,
propDstIdx_0_lat_1$whas,
propDstIdx_1_0_lat_1$whas,
propDstIdx_1_1_lat_1$whas,
propDstIdx_1_2_lat_1$whas,
propDstIdx_1_lat_1$whas,
propDstIdx_2_lat_1$whas;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register enqDst_0_rl
reg [74 : 0] enqDst_0_rl;
wire [74 : 0] enqDst_0_rl$D_IN;
wire enqDst_0_rl$EN;
// register enqDst_1_0_rl
reg [581 : 0] enqDst_1_0_rl;
wire [581 : 0] enqDst_1_0_rl$D_IN;
wire enqDst_1_0_rl$EN;
// register llc_axi4_adapter_ctr_wr_rsps_pending_crg
reg [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg;
wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN;
wire llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN;
// register llc_axi4_adapter_master_xactor_crg_rd_addr_full
reg llc_axi4_adapter_master_xactor_crg_rd_addr_full;
wire llc_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN,
llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN;
// register llc_axi4_adapter_master_xactor_crg_rd_data_full
reg llc_axi4_adapter_master_xactor_crg_rd_data_full;
wire llc_axi4_adapter_master_xactor_crg_rd_data_full$D_IN,
llc_axi4_adapter_master_xactor_crg_rd_data_full$EN;
// register llc_axi4_adapter_master_xactor_crg_wr_addr_full
reg llc_axi4_adapter_master_xactor_crg_wr_addr_full;
wire llc_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN,
llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN;
// register llc_axi4_adapter_master_xactor_crg_wr_data_full
reg llc_axi4_adapter_master_xactor_crg_wr_data_full;
wire llc_axi4_adapter_master_xactor_crg_wr_data_full$D_IN,
llc_axi4_adapter_master_xactor_crg_wr_data_full$EN;
// register llc_axi4_adapter_master_xactor_crg_wr_resp_full
reg llc_axi4_adapter_master_xactor_crg_wr_resp_full;
wire llc_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN,
llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN;
// register llc_axi4_adapter_master_xactor_rg_rd_addr
reg [108 : 0] llc_axi4_adapter_master_xactor_rg_rd_addr;
wire [108 : 0] llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN;
wire llc_axi4_adapter_master_xactor_rg_rd_addr$EN;
// register llc_axi4_adapter_master_xactor_rg_rd_data
reg [82 : 0] llc_axi4_adapter_master_xactor_rg_rd_data;
wire [82 : 0] llc_axi4_adapter_master_xactor_rg_rd_data$D_IN;
wire llc_axi4_adapter_master_xactor_rg_rd_data$EN;
// register llc_axi4_adapter_master_xactor_rg_wr_addr
reg [108 : 0] llc_axi4_adapter_master_xactor_rg_wr_addr;
wire [108 : 0] llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN;
wire llc_axi4_adapter_master_xactor_rg_wr_addr$EN;
// register llc_axi4_adapter_master_xactor_rg_wr_data
reg [72 : 0] llc_axi4_adapter_master_xactor_rg_wr_data;
wire [72 : 0] llc_axi4_adapter_master_xactor_rg_wr_data$D_IN;
wire llc_axi4_adapter_master_xactor_rg_wr_data$EN;
// register llc_axi4_adapter_master_xactor_rg_wr_resp
reg [17 : 0] llc_axi4_adapter_master_xactor_rg_wr_resp;
wire [17 : 0] llc_axi4_adapter_master_xactor_rg_wr_resp$D_IN;
wire llc_axi4_adapter_master_xactor_rg_wr_resp$EN;
// register llc_axi4_adapter_rg_AXI4_error
reg llc_axi4_adapter_rg_AXI4_error;
wire llc_axi4_adapter_rg_AXI4_error$D_IN, llc_axi4_adapter_rg_AXI4_error$EN;
// register llc_axi4_adapter_rg_cline
reg [511 : 0] llc_axi4_adapter_rg_cline;
wire [511 : 0] llc_axi4_adapter_rg_cline$D_IN;
wire llc_axi4_adapter_rg_cline$EN;
// register llc_axi4_adapter_rg_ddr4_ready
reg llc_axi4_adapter_rg_ddr4_ready;
wire llc_axi4_adapter_rg_ddr4_ready$D_IN, llc_axi4_adapter_rg_ddr4_ready$EN;
// register llc_axi4_adapter_rg_rd_req_beat
reg [2 : 0] llc_axi4_adapter_rg_rd_req_beat;
wire [2 : 0] llc_axi4_adapter_rg_rd_req_beat$D_IN;
wire llc_axi4_adapter_rg_rd_req_beat$EN;
// register llc_axi4_adapter_rg_rd_rsp_beat
reg [2 : 0] llc_axi4_adapter_rg_rd_rsp_beat;
wire [2 : 0] llc_axi4_adapter_rg_rd_rsp_beat$D_IN;
wire llc_axi4_adapter_rg_rd_rsp_beat$EN;
// register llc_axi4_adapter_rg_wr_req_beat
reg [2 : 0] llc_axi4_adapter_rg_wr_req_beat;
wire [2 : 0] llc_axi4_adapter_rg_wr_req_beat$D_IN;
wire llc_axi4_adapter_rg_wr_req_beat$EN;
// register llc_axi4_adapter_rg_wr_rsp_beat
reg [2 : 0] llc_axi4_adapter_rg_wr_rsp_beat;
wire [2 : 0] llc_axi4_adapter_rg_wr_rsp_beat$D_IN;
wire llc_axi4_adapter_rg_wr_rsp_beat$EN;
// register propDstData_0_rl
reg [73 : 0] propDstData_0_rl;
wire [73 : 0] propDstData_0_rl$D_IN;
wire propDstData_0_rl$EN;
// register propDstData_1_0_rl
reg [580 : 0] propDstData_1_0_rl;
wire [580 : 0] propDstData_1_0_rl$D_IN;
wire propDstData_1_0_rl$EN;
// register propDstData_1_1_rl
reg [580 : 0] propDstData_1_1_rl;
wire [580 : 0] propDstData_1_1_rl$D_IN;
wire propDstData_1_1_rl$EN;
// register propDstData_1_2_rl
reg [580 : 0] propDstData_1_2_rl;
wire [580 : 0] propDstData_1_2_rl$D_IN;
wire propDstData_1_2_rl$EN;
// register propDstData_1_rl
reg [73 : 0] propDstData_1_rl;
wire [73 : 0] propDstData_1_rl$D_IN;
wire propDstData_1_rl$EN;
// register propDstData_2_rl
reg [73 : 0] propDstData_2_rl;
wire [73 : 0] propDstData_2_rl$D_IN;
wire propDstData_2_rl$EN;
// register propDstIdx_0_rl
reg propDstIdx_0_rl;
wire propDstIdx_0_rl$D_IN, propDstIdx_0_rl$EN;
// register propDstIdx_1_0_rl
reg propDstIdx_1_0_rl;
wire propDstIdx_1_0_rl$D_IN, propDstIdx_1_0_rl$EN;
// register propDstIdx_1_1_rl
reg propDstIdx_1_1_rl;
wire propDstIdx_1_1_rl$D_IN, propDstIdx_1_1_rl$EN;
// register propDstIdx_1_2_rl
reg propDstIdx_1_2_rl;
wire propDstIdx_1_2_rl$D_IN, propDstIdx_1_2_rl$EN;
// register propDstIdx_1_rl
reg propDstIdx_1_rl;
wire propDstIdx_1_rl$D_IN, propDstIdx_1_rl$EN;
// register propDstIdx_2_rl
reg propDstIdx_2_rl;
wire propDstIdx_2_rl$D_IN, propDstIdx_2_rl$EN;
// register rg_state
reg [1 : 0] rg_state;
reg [1 : 0] rg_state$D_IN;
wire rg_state$EN;
// register srcRR_0
reg [1 : 0] srcRR_0;
wire [1 : 0] srcRR_0$D_IN;
wire srcRR_0$EN;
// register srcRR_1_0
reg [1 : 0] srcRR_1_0;
wire [1 : 0] srcRR_1_0$D_IN;
wire srcRR_1_0$EN;
// ports of submodule d_mmu_cache
wire [578 : 0] d_mmu_cache$l1_to_l2_client_response_enq_x,
d_mmu_cache$l2_to_l1_server_response_first;
wire [131 : 0] d_mmu_cache$imem_ptw_server_response_get;
wire [130 : 0] d_mmu_cache$mmio_client_request_get;
wire [127 : 0] d_mmu_cache$imem_pte_writeback_p_put,
d_mmu_cache$imem_ptw_server_request_put;
wire [68 : 0] d_mmu_cache$l1_to_l2_client_request_first;
wire [65 : 0] d_mmu_cache$l2_to_l1_server_request_enq_x;
wire [64 : 0] d_mmu_cache$mmio_client_response_put;
wire [63 : 0] d_mmu_cache$ma_req_satp,
d_mmu_cache$ma_req_st_value,
d_mmu_cache$ma_req_va,
d_mmu_cache$mv_tohost_value,
d_mmu_cache$set_watch_tohost_tohost_addr,
d_mmu_cache$st_amo_val,
d_mmu_cache$word64;
wire [6 : 0] d_mmu_cache$ma_req_amo_funct7;
wire [3 : 0] d_mmu_cache$exc_code;
wire [2 : 0] d_mmu_cache$ma_req_f3;
wire [1 : 0] d_mmu_cache$ma_req_op, d_mmu_cache$ma_req_priv;
wire d_mmu_cache$EN_flush_server_request_put,
d_mmu_cache$EN_flush_server_response_get,
d_mmu_cache$EN_imem_pte_writeback_p_put,
d_mmu_cache$EN_imem_ptw_server_request_put,
d_mmu_cache$EN_imem_ptw_server_response_get,
d_mmu_cache$EN_l1_to_l2_client_request_deq,
d_mmu_cache$EN_l1_to_l2_client_response_enq,
d_mmu_cache$EN_l2_to_l1_server_request_enq,
d_mmu_cache$EN_l2_to_l1_server_response_deq,
d_mmu_cache$EN_ma_req,
d_mmu_cache$EN_mmio_client_request_get,
d_mmu_cache$EN_mmio_client_response_put,
d_mmu_cache$EN_set_watch_tohost,
d_mmu_cache$EN_tlb_flush,
d_mmu_cache$RDY_imem_pte_writeback_p_put,
d_mmu_cache$RDY_imem_ptw_server_request_put,
d_mmu_cache$RDY_imem_ptw_server_response_get,
d_mmu_cache$RDY_l1_to_l2_client_request_deq,
d_mmu_cache$RDY_l1_to_l2_client_request_first,
d_mmu_cache$RDY_l1_to_l2_client_response_enq,
d_mmu_cache$RDY_l2_to_l1_server_request_enq,
d_mmu_cache$RDY_l2_to_l1_server_response_deq,
d_mmu_cache$RDY_l2_to_l1_server_response_first,
d_mmu_cache$RDY_mmio_client_request_get,
d_mmu_cache$RDY_mmio_client_response_put,
d_mmu_cache$exc,
d_mmu_cache$flush_server_request_put,
d_mmu_cache$ma_req_mstatus_MXR,
d_mmu_cache$ma_req_sstatus_SUM,
d_mmu_cache$set_watch_tohost_watch_tohost,
d_mmu_cache$valid;
// ports of submodule dma_cache
wire [578 : 0] dma_cache$l1_to_l2_client_response_enq_x,
dma_cache$l2_to_l1_server_response_first;
wire [511 : 0] dma_cache$axi4_s_rdata, dma_cache$axi4_s_wdata;
wire [130 : 0] dma_cache$mmio_client_request_get;
wire [68 : 0] dma_cache$l1_to_l2_client_request_first;
wire [65 : 0] dma_cache$l2_to_l1_server_request_enq_x;
wire [64 : 0] dma_cache$mmio_client_response_put;
wire [63 : 0] dma_cache$axi4_s_araddr,
dma_cache$axi4_s_awaddr,
dma_cache$axi4_s_wstrb;
wire [15 : 0] dma_cache$axi4_s_arid,
dma_cache$axi4_s_awid,
dma_cache$axi4_s_bid,
dma_cache$axi4_s_rid;
wire [7 : 0] dma_cache$axi4_s_arlen, dma_cache$axi4_s_awlen;
wire [3 : 0] dma_cache$axi4_s_arcache,
dma_cache$axi4_s_arqos,
dma_cache$axi4_s_arregion,
dma_cache$axi4_s_awcache,
dma_cache$axi4_s_awqos,
dma_cache$axi4_s_awregion;
wire [2 : 0] dma_cache$axi4_s_arprot,
dma_cache$axi4_s_arsize,
dma_cache$axi4_s_awprot,
dma_cache$axi4_s_awsize;
wire [1 : 0] dma_cache$axi4_s_arburst,
dma_cache$axi4_s_awburst,
dma_cache$axi4_s_bresp,
dma_cache$axi4_s_rresp;
wire dma_cache$EN_l1_to_l2_client_request_deq,
dma_cache$EN_l1_to_l2_client_response_enq,
dma_cache$EN_l2_to_l1_server_request_enq,
dma_cache$EN_l2_to_l1_server_response_deq,
dma_cache$EN_mmio_client_request_get,
dma_cache$EN_mmio_client_response_put,
dma_cache$RDY_l1_to_l2_client_request_deq,
dma_cache$RDY_l1_to_l2_client_request_first,
dma_cache$RDY_l1_to_l2_client_response_enq,
dma_cache$RDY_l2_to_l1_server_request_enq,
dma_cache$RDY_l2_to_l1_server_response_deq,
dma_cache$RDY_l2_to_l1_server_response_first,
dma_cache$RDY_mmio_client_request_get,
dma_cache$RDY_mmio_client_response_put,
dma_cache$axi4_s_arlock,
dma_cache$axi4_s_arready,
dma_cache$axi4_s_arvalid,
dma_cache$axi4_s_awlock,
dma_cache$axi4_s_awready,
dma_cache$axi4_s_awvalid,
dma_cache$axi4_s_bready,
dma_cache$axi4_s_bvalid,
dma_cache$axi4_s_rlast,
dma_cache$axi4_s_rready,
dma_cache$axi4_s_rvalid,
dma_cache$axi4_s_wlast,
dma_cache$axi4_s_wready,
dma_cache$axi4_s_wvalid;
// ports of submodule enqDst_0_dummy2_0
wire enqDst_0_dummy2_0$D_IN, enqDst_0_dummy2_0$EN, enqDst_0_dummy2_0$Q_OUT;
// ports of submodule enqDst_0_dummy2_1
wire enqDst_0_dummy2_1$D_IN, enqDst_0_dummy2_1$EN, enqDst_0_dummy2_1$Q_OUT;
// ports of submodule enqDst_1_0_dummy2_0
wire enqDst_1_0_dummy2_0$D_IN,
enqDst_1_0_dummy2_0$EN,
enqDst_1_0_dummy2_0$Q_OUT;
// ports of submodule enqDst_1_0_dummy2_1
wire enqDst_1_0_dummy2_1$D_IN,
enqDst_1_0_dummy2_1$EN,
enqDst_1_0_dummy2_1$Q_OUT;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule i_mmu_cache
wire [578 : 0] i_mmu_cache$l1_to_l2_client_response_enq_x,
i_mmu_cache$l2_to_l1_server_response_first;
wire [131 : 0] i_mmu_cache$ptw_client_response_put;
wire [130 : 0] i_mmu_cache$mmio_client_request_get;
wire [127 : 0] i_mmu_cache$pte_writeback_g_get,
i_mmu_cache$ptw_client_request_get;
wire [68 : 0] i_mmu_cache$l1_to_l2_client_request_first;
wire [65 : 0] i_mmu_cache$l2_to_l1_server_request_enq_x;
wire [64 : 0] i_mmu_cache$mmio_client_response_put;
wire [63 : 0] i_mmu_cache$addr,
i_mmu_cache$ma_req_satp,
i_mmu_cache$ma_req_va,
i_mmu_cache$word64;
wire [3 : 0] i_mmu_cache$exc_code;
wire [1 : 0] i_mmu_cache$ma_req_priv;
wire i_mmu_cache$EN_flush_server_request_put,
i_mmu_cache$EN_flush_server_response_get,
i_mmu_cache$EN_l1_to_l2_client_request_deq,
i_mmu_cache$EN_l1_to_l2_client_response_enq,
i_mmu_cache$EN_l2_to_l1_server_request_enq,
i_mmu_cache$EN_l2_to_l1_server_response_deq,
i_mmu_cache$EN_ma_req,
i_mmu_cache$EN_mmio_client_request_get,
i_mmu_cache$EN_mmio_client_response_put,
i_mmu_cache$EN_pte_writeback_g_get,
i_mmu_cache$EN_ptw_client_request_get,
i_mmu_cache$EN_ptw_client_response_put,
i_mmu_cache$EN_tlb_flush,
i_mmu_cache$RDY_l1_to_l2_client_request_deq,
i_mmu_cache$RDY_l1_to_l2_client_request_first,
i_mmu_cache$RDY_l1_to_l2_client_response_enq,
i_mmu_cache$RDY_l2_to_l1_server_request_enq,
i_mmu_cache$RDY_l2_to_l1_server_response_deq,
i_mmu_cache$RDY_l2_to_l1_server_response_first,
i_mmu_cache$RDY_mmio_client_request_get,
i_mmu_cache$RDY_mmio_client_response_put,
i_mmu_cache$RDY_pte_writeback_g_get,
i_mmu_cache$RDY_ptw_client_request_get,
i_mmu_cache$RDY_ptw_client_response_put,
i_mmu_cache$exc,
i_mmu_cache$flush_server_request_put,
i_mmu_cache$ma_req_mstatus_MXR,
i_mmu_cache$ma_req_sstatus_SUM,
i_mmu_cache$valid;
// ports of submodule llc
wire [655 : 0] llc$dma_memReq_enq_x;
wire [640 : 0] llc$to_mem_toM_first;
wire [584 : 0] llc$to_child_toC_first;
wire [580 : 0] llc$to_child_rsFromC_enq_x;
wire [516 : 0] llc$to_mem_rsFromM_enq_x;
wire [73 : 0] llc$to_child_rqFromC_enq_x;
wire [3 : 0] llc$perf_req_r;
wire llc$EN_cRqStuck_get,
llc$EN_dma_memReq_enq,
llc$EN_dma_respLd_deq,
llc$EN_dma_respSt_deq,
llc$EN_perf_req,
llc$EN_perf_resp,
llc$EN_perf_setStatus,
llc$EN_to_child_rqFromC_enq,
llc$EN_to_child_rsFromC_enq,
llc$EN_to_child_toC_deq,
llc$EN_to_mem_rsFromM_enq,
llc$EN_to_mem_toM_deq,
llc$RDY_dma_respLd_deq,
llc$RDY_dma_respSt_deq,
llc$RDY_to_child_rqFromC_enq,
llc$RDY_to_child_rsFromC_enq,
llc$RDY_to_child_toC_deq,
llc$RDY_to_child_toC_first,
llc$RDY_to_mem_rsFromM_enq,
llc$RDY_to_mem_toM_deq,
llc$RDY_to_mem_toM_first,
llc$perf_setStatus_doStats;
// ports of submodule llc_axi4_adapter_f_pending_reads
wire [68 : 0] llc_axi4_adapter_f_pending_reads$D_IN,
llc_axi4_adapter_f_pending_reads$D_OUT;
wire llc_axi4_adapter_f_pending_reads$CLR,
llc_axi4_adapter_f_pending_reads$DEQ,
llc_axi4_adapter_f_pending_reads$EMPTY_N,
llc_axi4_adapter_f_pending_reads$ENQ,
llc_axi4_adapter_f_pending_reads$FULL_N;
// ports of submodule llc_axi4_adapter_f_pending_writes
wire [639 : 0] llc_axi4_adapter_f_pending_writes$D_IN;
wire llc_axi4_adapter_f_pending_writes$CLR,
llc_axi4_adapter_f_pending_writes$DEQ,
llc_axi4_adapter_f_pending_writes$EMPTY_N,
llc_axi4_adapter_f_pending_writes$ENQ,
llc_axi4_adapter_f_pending_writes$FULL_N;
// ports of submodule mmio_axi4_adapter
wire [130 : 0] mmio_axi4_adapter$v_mmio_server_0_request_put,
mmio_axi4_adapter$v_mmio_server_1_request_put,
mmio_axi4_adapter$v_mmio_server_2_request_put;
wire [64 : 0] mmio_axi4_adapter$v_mmio_server_0_response_get,
mmio_axi4_adapter$v_mmio_server_1_response_get,
mmio_axi4_adapter$v_mmio_server_2_response_get;
wire [63 : 0] mmio_axi4_adapter$mem_master_araddr,
mmio_axi4_adapter$mem_master_awaddr,
mmio_axi4_adapter$mem_master_rdata,
mmio_axi4_adapter$mem_master_wdata;
wire [15 : 0] mmio_axi4_adapter$mem_master_arid,
mmio_axi4_adapter$mem_master_awid,
mmio_axi4_adapter$mem_master_bid,
mmio_axi4_adapter$mem_master_rid;
wire [7 : 0] mmio_axi4_adapter$mem_master_arlen,
mmio_axi4_adapter$mem_master_awlen,
mmio_axi4_adapter$mem_master_wstrb;
wire [3 : 0] mmio_axi4_adapter$mem_master_arcache,
mmio_axi4_adapter$mem_master_arqos,
mmio_axi4_adapter$mem_master_arregion,
mmio_axi4_adapter$mem_master_awcache,
mmio_axi4_adapter$mem_master_awqos,
mmio_axi4_adapter$mem_master_awregion;
wire [2 : 0] mmio_axi4_adapter$mem_master_arprot,
mmio_axi4_adapter$mem_master_arsize,
mmio_axi4_adapter$mem_master_awprot,
mmio_axi4_adapter$mem_master_awsize;
wire [1 : 0] mmio_axi4_adapter$mem_master_arburst,
mmio_axi4_adapter$mem_master_awburst,
mmio_axi4_adapter$mem_master_bresp,
mmio_axi4_adapter$mem_master_rresp;
wire mmio_axi4_adapter$EN_v_mmio_server_0_request_put,
mmio_axi4_adapter$EN_v_mmio_server_0_response_get,
mmio_axi4_adapter$EN_v_mmio_server_1_request_put,
mmio_axi4_adapter$EN_v_mmio_server_1_response_get,
mmio_axi4_adapter$EN_v_mmio_server_2_request_put,
mmio_axi4_adapter$EN_v_mmio_server_2_response_get,
mmio_axi4_adapter$RDY_v_mmio_server_0_request_put,
mmio_axi4_adapter$RDY_v_mmio_server_0_response_get,
mmio_axi4_adapter$RDY_v_mmio_server_1_request_put,
mmio_axi4_adapter$RDY_v_mmio_server_1_response_get,
mmio_axi4_adapter$RDY_v_mmio_server_2_request_put,
mmio_axi4_adapter$RDY_v_mmio_server_2_response_get,
mmio_axi4_adapter$mem_master_arlock,
mmio_axi4_adapter$mem_master_arready,
mmio_axi4_adapter$mem_master_arvalid,
mmio_axi4_adapter$mem_master_awlock,
mmio_axi4_adapter$mem_master_awready,
mmio_axi4_adapter$mem_master_awvalid,
mmio_axi4_adapter$mem_master_bready,
mmio_axi4_adapter$mem_master_bvalid,
mmio_axi4_adapter$mem_master_rlast,
mmio_axi4_adapter$mem_master_rready,
mmio_axi4_adapter$mem_master_rvalid,
mmio_axi4_adapter$mem_master_wlast,
mmio_axi4_adapter$mem_master_wready,
mmio_axi4_adapter$mem_master_wvalid;
// ports of submodule propDstData_0_dummy2_0
wire propDstData_0_dummy2_0$D_IN, propDstData_0_dummy2_0$EN;
// ports of submodule propDstData_0_dummy2_1
wire propDstData_0_dummy2_1$D_IN,
propDstData_0_dummy2_1$EN,
propDstData_0_dummy2_1$Q_OUT;
// ports of submodule propDstData_1_0_dummy2_0
wire propDstData_1_0_dummy2_0$D_IN, propDstData_1_0_dummy2_0$EN;
// ports of submodule propDstData_1_0_dummy2_1
wire propDstData_1_0_dummy2_1$D_IN,
propDstData_1_0_dummy2_1$EN,
propDstData_1_0_dummy2_1$Q_OUT;
// ports of submodule propDstData_1_1_dummy2_0
wire propDstData_1_1_dummy2_0$D_IN, propDstData_1_1_dummy2_0$EN;
// ports of submodule propDstData_1_1_dummy2_1
wire propDstData_1_1_dummy2_1$D_IN,
propDstData_1_1_dummy2_1$EN,
propDstData_1_1_dummy2_1$Q_OUT;
// ports of submodule propDstData_1_2_dummy2_0
wire propDstData_1_2_dummy2_0$D_IN, propDstData_1_2_dummy2_0$EN;
// ports of submodule propDstData_1_2_dummy2_1
wire propDstData_1_2_dummy2_1$D_IN,
propDstData_1_2_dummy2_1$EN,
propDstData_1_2_dummy2_1$Q_OUT;
// ports of submodule propDstData_1_dummy2_0
wire propDstData_1_dummy2_0$D_IN, propDstData_1_dummy2_0$EN;
// ports of submodule propDstData_1_dummy2_1
wire propDstData_1_dummy2_1$D_IN,
propDstData_1_dummy2_1$EN,
propDstData_1_dummy2_1$Q_OUT;
// ports of submodule propDstData_2_dummy2_0
wire propDstData_2_dummy2_0$D_IN, propDstData_2_dummy2_0$EN;
// ports of submodule propDstData_2_dummy2_1
wire propDstData_2_dummy2_1$D_IN,
propDstData_2_dummy2_1$EN,
propDstData_2_dummy2_1$Q_OUT;
// ports of submodule propDstIdx_0_dummy2_0
wire propDstIdx_0_dummy2_0$D_IN,
propDstIdx_0_dummy2_0$EN,
propDstIdx_0_dummy2_0$Q_OUT;
// ports of submodule propDstIdx_0_dummy2_1
wire propDstIdx_0_dummy2_1$D_IN,
propDstIdx_0_dummy2_1$EN,
propDstIdx_0_dummy2_1$Q_OUT;
// ports of submodule propDstIdx_1_0_dummy2_0
wire propDstIdx_1_0_dummy2_0$D_IN,
propDstIdx_1_0_dummy2_0$EN,
propDstIdx_1_0_dummy2_0$Q_OUT;
// ports of submodule propDstIdx_1_0_dummy2_1
wire propDstIdx_1_0_dummy2_1$D_IN,
propDstIdx_1_0_dummy2_1$EN,
propDstIdx_1_0_dummy2_1$Q_OUT;
// ports of submodule propDstIdx_1_1_dummy2_0
wire propDstIdx_1_1_dummy2_0$D_IN,
propDstIdx_1_1_dummy2_0$EN,
propDstIdx_1_1_dummy2_0$Q_OUT;
// ports of submodule propDstIdx_1_1_dummy2_1
wire propDstIdx_1_1_dummy2_1$D_IN,
propDstIdx_1_1_dummy2_1$EN,
propDstIdx_1_1_dummy2_1$Q_OUT;
// ports of submodule propDstIdx_1_2_dummy2_0
wire propDstIdx_1_2_dummy2_0$D_IN,
propDstIdx_1_2_dummy2_0$EN,
propDstIdx_1_2_dummy2_0$Q_OUT;
// ports of submodule propDstIdx_1_2_dummy2_1
wire propDstIdx_1_2_dummy2_1$D_IN,
propDstIdx_1_2_dummy2_1$EN,
propDstIdx_1_2_dummy2_1$Q_OUT;
// ports of submodule propDstIdx_1_dummy2_0
wire propDstIdx_1_dummy2_0$D_IN,
propDstIdx_1_dummy2_0$EN,
propDstIdx_1_dummy2_0$Q_OUT;
// ports of submodule propDstIdx_1_dummy2_1
wire propDstIdx_1_dummy2_1$D_IN,
propDstIdx_1_dummy2_1$EN,
propDstIdx_1_dummy2_1$Q_OUT;
// ports of submodule propDstIdx_2_dummy2_0
wire propDstIdx_2_dummy2_0$D_IN,
propDstIdx_2_dummy2_0$EN,
propDstIdx_2_dummy2_0$Q_OUT;
// ports of submodule propDstIdx_2_dummy2_1
wire propDstIdx_2_dummy2_1$D_IN,
propDstIdx_2_dummy2_1$EN,
propDstIdx_2_dummy2_1$Q_OUT;
// rule scheduling signals
wire CAN_FIRE_RL_ClientServerRequest,
CAN_FIRE_RL_ClientServerRequest_1,
CAN_FIRE_RL_ClientServerRequest_2,
CAN_FIRE_RL_ClientServerRequest_3,
CAN_FIRE_RL_ClientServerResponse,
CAN_FIRE_RL_ClientServerResponse_1,
CAN_FIRE_RL_ClientServerResponse_2,
CAN_FIRE_RL_ClientServerResponse_3,
CAN_FIRE_RL_doEnq,
CAN_FIRE_RL_doEnq_1,
CAN_FIRE_RL_dstSelectSrc,
CAN_FIRE_RL_dstSelectSrc_1,
CAN_FIRE_RL_enqDst_0_canon,
CAN_FIRE_RL_enqDst_1_0_canon,
CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp,
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req,
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps,
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req,
CAN_FIRE_RL_mkConnectionGetPut_1,
CAN_FIRE_RL_mkConnectionGetPut_2,
CAN_FIRE_RL_mkConnectionGetPut_3,
CAN_FIRE_RL_propDstData_0_canon,
CAN_FIRE_RL_propDstData_1_0_canon,
CAN_FIRE_RL_propDstData_1_1_canon,
CAN_FIRE_RL_propDstData_1_2_canon,
CAN_FIRE_RL_propDstData_1_canon,
CAN_FIRE_RL_propDstData_2_canon,
CAN_FIRE_RL_propDstIdx_0_canon,
CAN_FIRE_RL_propDstIdx_1_0_canon,
CAN_FIRE_RL_propDstIdx_1_1_canon,
CAN_FIRE_RL_propDstIdx_1_2_canon,
CAN_FIRE_RL_propDstIdx_1_canon,
CAN_FIRE_RL_propDstIdx_2_canon,
CAN_FIRE_RL_rl_reset,
CAN_FIRE_RL_rl_reset_complete,
CAN_FIRE_RL_sendPRq,
CAN_FIRE_RL_sendPRq_1,
CAN_FIRE_RL_sendPRq_2,
CAN_FIRE_RL_sendPRs,
CAN_FIRE_RL_sendPRs_1,
CAN_FIRE_RL_sendPRs_2,
CAN_FIRE_RL_srcPropose,
CAN_FIRE_RL_srcPropose_1,
CAN_FIRE_RL_srcPropose_2,
CAN_FIRE_RL_srcPropose_3,
CAN_FIRE_RL_srcPropose_4,
CAN_FIRE_RL_srcPropose_5,
CAN_FIRE_dma_server_m_arvalid,
CAN_FIRE_dma_server_m_awvalid,
CAN_FIRE_dma_server_m_bready,
CAN_FIRE_dma_server_m_rready,
CAN_FIRE_dma_server_m_wvalid,
CAN_FIRE_dmem_req,
CAN_FIRE_imem_master_m_arready,
CAN_FIRE_imem_master_m_awready,
CAN_FIRE_imem_master_m_bvalid,
CAN_FIRE_imem_master_m_rvalid,
CAN_FIRE_imem_master_m_wready,
CAN_FIRE_imem_req,
CAN_FIRE_ma_ddr4_ready,
CAN_FIRE_mem_master_m_arready,
CAN_FIRE_mem_master_m_awready,
CAN_FIRE_mem_master_m_bvalid,
CAN_FIRE_mem_master_m_rvalid,
CAN_FIRE_mem_master_m_wready,
CAN_FIRE_server_fence_i_request_put,
CAN_FIRE_server_fence_i_response_get,
CAN_FIRE_server_fence_request_put,
CAN_FIRE_server_fence_response_get,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_set_watch_tohost,
CAN_FIRE_sfence_vma_server_request_put,
CAN_FIRE_sfence_vma_server_response_get,
WILL_FIRE_RL_ClientServerRequest,
WILL_FIRE_RL_ClientServerRequest_1,
WILL_FIRE_RL_ClientServerRequest_2,
WILL_FIRE_RL_ClientServerRequest_3,
WILL_FIRE_RL_ClientServerResponse,
WILL_FIRE_RL_ClientServerResponse_1,
WILL_FIRE_RL_ClientServerResponse_2,
WILL_FIRE_RL_ClientServerResponse_3,
WILL_FIRE_RL_doEnq,
WILL_FIRE_RL_doEnq_1,
WILL_FIRE_RL_dstSelectSrc,
WILL_FIRE_RL_dstSelectSrc_1,
WILL_FIRE_RL_enqDst_0_canon,
WILL_FIRE_RL_enqDst_1_0_canon,
WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp,
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req,
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps,
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req,
WILL_FIRE_RL_mkConnectionGetPut_1,
WILL_FIRE_RL_mkConnectionGetPut_2,
WILL_FIRE_RL_mkConnectionGetPut_3,
WILL_FIRE_RL_propDstData_0_canon,
WILL_FIRE_RL_propDstData_1_0_canon,
WILL_FIRE_RL_propDstData_1_1_canon,
WILL_FIRE_RL_propDstData_1_2_canon,
WILL_FIRE_RL_propDstData_1_canon,
WILL_FIRE_RL_propDstData_2_canon,
WILL_FIRE_RL_propDstIdx_0_canon,
WILL_FIRE_RL_propDstIdx_1_0_canon,
WILL_FIRE_RL_propDstIdx_1_1_canon,
WILL_FIRE_RL_propDstIdx_1_2_canon,
WILL_FIRE_RL_propDstIdx_1_canon,
WILL_FIRE_RL_propDstIdx_2_canon,
WILL_FIRE_RL_rl_reset,
WILL_FIRE_RL_rl_reset_complete,
WILL_FIRE_RL_sendPRq,
WILL_FIRE_RL_sendPRq_1,
WILL_FIRE_RL_sendPRq_2,
WILL_FIRE_RL_sendPRs,
WILL_FIRE_RL_sendPRs_1,
WILL_FIRE_RL_sendPRs_2,
WILL_FIRE_RL_srcPropose,
WILL_FIRE_RL_srcPropose_1,
WILL_FIRE_RL_srcPropose_2,
WILL_FIRE_RL_srcPropose_3,
WILL_FIRE_RL_srcPropose_4,
WILL_FIRE_RL_srcPropose_5,
WILL_FIRE_dma_server_m_arvalid,
WILL_FIRE_dma_server_m_awvalid,
WILL_FIRE_dma_server_m_bready,
WILL_FIRE_dma_server_m_rready,
WILL_FIRE_dma_server_m_wvalid,
WILL_FIRE_dmem_req,
WILL_FIRE_imem_master_m_arready,
WILL_FIRE_imem_master_m_awready,
WILL_FIRE_imem_master_m_bvalid,
WILL_FIRE_imem_master_m_rvalid,
WILL_FIRE_imem_master_m_wready,
WILL_FIRE_imem_req,
WILL_FIRE_ma_ddr4_ready,
WILL_FIRE_mem_master_m_arready,
WILL_FIRE_mem_master_m_awready,
WILL_FIRE_mem_master_m_bvalid,
WILL_FIRE_mem_master_m_rvalid,
WILL_FIRE_mem_master_m_wready,
WILL_FIRE_server_fence_i_request_put,
WILL_FIRE_server_fence_i_response_get,
WILL_FIRE_server_fence_request_put,
WILL_FIRE_server_fence_response_get,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_set_watch_tohost,
WILL_FIRE_sfence_vma_server_request_put,
WILL_FIRE_sfence_vma_server_response_get;
// inputs to muxes for submodule ports
wire MUX_rg_state$write_1__SEL_3;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h84135;
reg [31 : 0] v__h84241;
reg [31 : 0] v__h13951;
reg [31 : 0] v__h85786;
reg [31 : 0] v__h31896;
reg [31 : 0] v__h13945;
reg [31 : 0] v__h31890;
reg [31 : 0] v__h84129;
reg [31 : 0] v__h84235;
reg [31 : 0] v__h85780;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q10,
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q11,
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q13,
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q5,
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q6,
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q7,
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q8,
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q9,
CASE_x1624_0_n__read_addr1844_1_n__read_addr19_ETC__q15,
CASE_x5600_0_n__read_addr5824_1_n__read_addr59_ETC__q4,
data64__h15525;
reg [7 : 0] strb8__h15526;
reg [2 : 0] x__h46058;
reg [1 : 0] CASE_x1624_0_IF_propDstData_1_0_dummy2_1_read__ETC__q14,
CASE_x5600_0_IF_propDstData_0_dummy2_1_read__5_ETC__q2,
CASE_x5600_0_IF_propDstData_0_dummy2_1_read__5_ETC__q3,
x__h46068,
x__h74996;
reg CASE_x1624_0_propDstData_1_0_dummy2_1_read__87_ETC__q12,
CASE_x5600_0_propDstData_0_dummy2_1_read__54_A_ETC__q1,
SEL_ARR_propDstIdx_0_dummy2_1_read__95_AND_IF__ETC___d242,
SEL_ARR_propDstIdx_1_0_dummy2_1_read__28_AND_I_ETC___d475;
wire [516 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__87_T_ETC___d642;
wire [512 : 0] SEL_ARR_propDstData_1_0_dummy2_1_read__87_AND__ETC___d627;
wire [511 : 0] new_cline__h14098;
wire [447 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__97_THEN_ETC___d615;
wire [319 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__97_THEN_ETC___d592;
wire [191 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__97_THEN_ETC___d569;
wire [63 : 0] mem_req_rd_addr_araddr__h13577,
mem_req_wr_addr_awaddr__h15613,
n__read_addr__h45824,
n__read_addr__h45909,
n__read_addr__h45994,
n__read_addr__h71844,
n__read_addr__h71923,
n__read_addr__h72002;
wire [9 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__54_THE_ETC___d346;
wire [5 : 0] SEL_ARR_propDstData_0_dummy2_1_read__54_AND_IF_ETC___d345,
x__h13627,
x__h15647;
wire [3 : 0] b__h13463;
wire [2 : 0] n__read_id__h45828, n__read_id__h45913, n__read_id__h45998;
wire [1 : 0] IF_propDstData_0_dummy2_1_read__54_THEN_IF_pro_ETC___d278,
IF_propDstData_0_dummy2_1_read__54_THEN_IF_pro_ETC___d292,
IF_propDstData_1_0_dummy2_1_read__87_THEN_IF_p_ETC___d511,
IF_propDstData_1_1_dummy2_1_read__92_THEN_IF_p_ETC___d515,
IF_propDstData_1_2_dummy2_1_read__97_THEN_IF_p_ETC___d519,
IF_propDstData_1_dummy2_1_read__59_THEN_IF_pro_ETC___d282,
IF_propDstData_1_dummy2_1_read__59_THEN_IF_pro_ETC___d296,
IF_propDstData_2_dummy2_1_read__64_THEN_IF_pro_ETC___d286,
IF_propDstData_2_dummy2_1_read__64_THEN_IF_pro_ETC___d300,
n__read_child__h45829,
n__read_child__h45914,
n__read_child__h45999,
n__read_child__h71847,
n__read_child__h71926,
n__read_child__h72005,
x__h45600,
x__h71624;
wire IF_NOT_propDstIdx_0_dummy2_1_read__95_96_OR_IF_ETC___d250,
IF_NOT_propDstIdx_0_dummy2_1_read__95_96_OR_IF_ETC___d251,
IF_NOT_propDstIdx_1_0_dummy2_1_read__28_29_OR__ETC___d483,
IF_NOT_propDstIdx_1_0_dummy2_1_read__28_29_OR__ETC___d484,
IF_propDstIdx_0_lat_0_whas__43_THEN_propDstIdx_ETC___d146,
IF_propDstIdx_1_0_lat_0_whas__76_THEN_propDstI_ETC___d379,
IF_propDstIdx_1_1_lat_0_whas__83_THEN_propDstI_ETC___d386,
IF_propDstIdx_1_2_lat_0_whas__90_THEN_propDstI_ETC___d393,
IF_propDstIdx_1_lat_0_whas__50_THEN_propDstIdx_ETC___d153,
IF_propDstIdx_2_lat_0_whas__57_THEN_propDstIdx_ETC___d160,
NOT_cfg_verbosity_read__38_ULE_1_39___d740,
NOT_enqDst_0_dummy2_0_read__29_30_OR_NOT_enqDs_ETC___d253,
NOT_enqDst_1_0_dummy2_0_read__62_63_OR_NOT_enq_ETC___d486,
NOT_llc_axi4_adapter_master_xactor_crg_wr_addr_ETC___d80,
NOT_propDstIdx_0_dummy2_1_read__95_96_OR_IF_pr_ETC___d245,
NOT_propDstIdx_1_0_dummy2_1_read__28_29_OR_IF__ETC___d478,
NOT_propDstIdx_1_1_dummy2_1_read__41_42_OR_IF__ETC___d481,
NOT_propDstIdx_1_2_dummy2_1_read__54_55_OR_IF__ETC___d659,
NOT_propDstIdx_1_dummy2_1_read__08_09_OR_IF_pr_ETC___d248,
NOT_propDstIdx_2_dummy2_1_read__21_22_OR_IF_pr_ETC___d363,
enqDst_0_dummy2_1_read__31_AND_IF_enqDst_0_lat_ETC___d368,
enqDst_1_0_dummy2_1_read__64_AND_IF_enqDst_1_0_ETC___d664,
propDstData_0_dummy2_1_read__54_AND_IF_propDst_ETC___d306,
propDstData_1_0_dummy2_1_read__87_AND_IF_propD_ETC___d525,
propDstData_1_1_dummy2_1_read__92_AND_IF_propD_ETC___d529,
propDstData_1_2_dummy2_1_read__97_AND_IF_propD_ETC___d533,
propDstData_1_dummy2_1_read__59_AND_IF_propDst_ETC___d310,
propDstData_2_dummy2_1_read__64_AND_IF_propDst_ETC___d314;
// action method server_reset_request_put
assign RDY_server_reset_request_put = rg_state == 2'd2 ;
assign CAN_FIRE_server_reset_request_put = rg_state == 2'd2 ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method imem_req
assign CAN_FIRE_imem_req = 1'd1 ;
assign WILL_FIRE_imem_req = EN_imem_req ;
// value method imem_valid
assign imem_valid = i_mmu_cache$valid ;
// value method imem_is_i32_not_i16
assign imem_is_i32_not_i16 = 1'd1 ;
// value method imem_pc
assign imem_pc = i_mmu_cache$addr ;
// value method imem_instr
assign imem_instr = i_mmu_cache$word64[31:0] ;
// value method imem_exc
assign imem_exc = i_mmu_cache$exc ;
// value method imem_exc_code
assign imem_exc_code = i_mmu_cache$exc_code ;
// value method imem_tval
assign imem_tval = i_mmu_cache$addr ;
// value method imem_master_m_awvalid
assign imem_master_awvalid = mmio_axi4_adapter$mem_master_awvalid ;
// value method imem_master_m_awid
assign imem_master_awid = mmio_axi4_adapter$mem_master_awid ;
// value method imem_master_m_awaddr
assign imem_master_awaddr = mmio_axi4_adapter$mem_master_awaddr ;
// value method imem_master_m_awlen
assign imem_master_awlen = mmio_axi4_adapter$mem_master_awlen ;
// value method imem_master_m_awsize
assign imem_master_awsize = mmio_axi4_adapter$mem_master_awsize ;
// value method imem_master_m_awburst
assign imem_master_awburst = mmio_axi4_adapter$mem_master_awburst ;
// value method imem_master_m_awlock
assign imem_master_awlock = mmio_axi4_adapter$mem_master_awlock ;
// value method imem_master_m_awcache
assign imem_master_awcache = mmio_axi4_adapter$mem_master_awcache ;
// value method imem_master_m_awprot
assign imem_master_awprot = mmio_axi4_adapter$mem_master_awprot ;
// value method imem_master_m_awqos
assign imem_master_awqos = mmio_axi4_adapter$mem_master_awqos ;
// value method imem_master_m_awregion
assign imem_master_awregion = mmio_axi4_adapter$mem_master_awregion ;
// action method imem_master_m_awready
assign CAN_FIRE_imem_master_m_awready = 1'd1 ;
assign WILL_FIRE_imem_master_m_awready = 1'd1 ;
// value method imem_master_m_wvalid
assign imem_master_wvalid = mmio_axi4_adapter$mem_master_wvalid ;
// value method imem_master_m_wdata
assign imem_master_wdata = mmio_axi4_adapter$mem_master_wdata ;
// value method imem_master_m_wstrb
assign imem_master_wstrb = mmio_axi4_adapter$mem_master_wstrb ;
// value method imem_master_m_wlast
assign imem_master_wlast = mmio_axi4_adapter$mem_master_wlast ;
// action method imem_master_m_wready
assign CAN_FIRE_imem_master_m_wready = 1'd1 ;
assign WILL_FIRE_imem_master_m_wready = 1'd1 ;
// action method imem_master_m_bvalid
assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ;
// value method imem_master_m_bready
assign imem_master_bready = mmio_axi4_adapter$mem_master_bready ;
// value method imem_master_m_arvalid
assign imem_master_arvalid = mmio_axi4_adapter$mem_master_arvalid ;
// value method imem_master_m_arid
assign imem_master_arid = mmio_axi4_adapter$mem_master_arid ;
// value method imem_master_m_araddr
assign imem_master_araddr = mmio_axi4_adapter$mem_master_araddr ;
// value method imem_master_m_arlen
assign imem_master_arlen = mmio_axi4_adapter$mem_master_arlen ;
// value method imem_master_m_arsize
assign imem_master_arsize = mmio_axi4_adapter$mem_master_arsize ;
// value method imem_master_m_arburst
assign imem_master_arburst = mmio_axi4_adapter$mem_master_arburst ;
// value method imem_master_m_arlock
assign imem_master_arlock = mmio_axi4_adapter$mem_master_arlock ;
// value method imem_master_m_arcache
assign imem_master_arcache = mmio_axi4_adapter$mem_master_arcache ;
// value method imem_master_m_arprot
assign imem_master_arprot = mmio_axi4_adapter$mem_master_arprot ;
// value method imem_master_m_arqos
assign imem_master_arqos = mmio_axi4_adapter$mem_master_arqos ;
// value method imem_master_m_arregion
assign imem_master_arregion = mmio_axi4_adapter$mem_master_arregion ;
// action method imem_master_m_arready
assign CAN_FIRE_imem_master_m_arready = 1'd1 ;
assign WILL_FIRE_imem_master_m_arready = 1'd1 ;
// action method imem_master_m_rvalid
assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ;
// value method imem_master_m_rready
assign imem_master_rready = mmio_axi4_adapter$mem_master_rready ;
// action method dmem_req
assign CAN_FIRE_dmem_req = 1'd1 ;
assign WILL_FIRE_dmem_req = EN_dmem_req ;
// value method dmem_valid
assign dmem_valid = d_mmu_cache$valid ;
// value method dmem_word64
assign dmem_word64 = d_mmu_cache$word64 ;
// value method dmem_st_amo_val
assign dmem_st_amo_val = d_mmu_cache$st_amo_val ;
// value method dmem_exc
assign dmem_exc = d_mmu_cache$exc ;
// value method dmem_exc_code
assign dmem_exc_code = d_mmu_cache$exc_code ;
// value method mem_master_m_awvalid
assign mem_master_awvalid =
llc_axi4_adapter_master_xactor_crg_wr_addr_full ;
// value method mem_master_m_awid
assign mem_master_awid = llc_axi4_adapter_master_xactor_rg_wr_addr[108:93] ;
// value method mem_master_m_awaddr
assign mem_master_awaddr =
llc_axi4_adapter_master_xactor_rg_wr_addr[92:29] ;
// value method mem_master_m_awlen
assign mem_master_awlen = llc_axi4_adapter_master_xactor_rg_wr_addr[28:21] ;
// value method mem_master_m_awsize
assign mem_master_awsize =
llc_axi4_adapter_master_xactor_rg_wr_addr[20:18] ;
// value method mem_master_m_awburst
assign mem_master_awburst =
llc_axi4_adapter_master_xactor_rg_wr_addr[17:16] ;
// value method mem_master_m_awlock
assign mem_master_awlock = llc_axi4_adapter_master_xactor_rg_wr_addr[15] ;
// value method mem_master_m_awcache
assign mem_master_awcache =
llc_axi4_adapter_master_xactor_rg_wr_addr[14:11] ;
// value method mem_master_m_awprot
assign mem_master_awprot = llc_axi4_adapter_master_xactor_rg_wr_addr[10:8] ;
// value method mem_master_m_awqos
assign mem_master_awqos = llc_axi4_adapter_master_xactor_rg_wr_addr[7:4] ;
// value method mem_master_m_awregion
assign mem_master_awregion =
llc_axi4_adapter_master_xactor_rg_wr_addr[3:0] ;
// action method mem_master_m_awready
assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
assign WILL_FIRE_mem_master_m_awready = 1'd1 ;
// value method mem_master_m_wvalid
assign mem_master_wvalid = llc_axi4_adapter_master_xactor_crg_wr_data_full ;
// value method mem_master_m_wdata
assign mem_master_wdata = llc_axi4_adapter_master_xactor_rg_wr_data[72:9] ;
// value method mem_master_m_wstrb
assign mem_master_wstrb = llc_axi4_adapter_master_xactor_rg_wr_data[8:1] ;
// value method mem_master_m_wlast
assign mem_master_wlast = llc_axi4_adapter_master_xactor_rg_wr_data[0] ;
// action method mem_master_m_wready
assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
assign WILL_FIRE_mem_master_m_wready = 1'd1 ;
// action method mem_master_m_bvalid
assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;
// value method mem_master_m_bready
assign mem_master_bready =
!llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
// value method mem_master_m_arvalid
assign mem_master_arvalid =
llc_axi4_adapter_master_xactor_crg_rd_addr_full ;
// value method mem_master_m_arid
assign mem_master_arid = llc_axi4_adapter_master_xactor_rg_rd_addr[108:93] ;
// value method mem_master_m_araddr
assign mem_master_araddr =
llc_axi4_adapter_master_xactor_rg_rd_addr[92:29] ;
// value method mem_master_m_arlen
assign mem_master_arlen = llc_axi4_adapter_master_xactor_rg_rd_addr[28:21] ;
// value method mem_master_m_arsize
assign mem_master_arsize =
llc_axi4_adapter_master_xactor_rg_rd_addr[20:18] ;
// value method mem_master_m_arburst
assign mem_master_arburst =
llc_axi4_adapter_master_xactor_rg_rd_addr[17:16] ;
// value method mem_master_m_arlock
assign mem_master_arlock = llc_axi4_adapter_master_xactor_rg_rd_addr[15] ;
// value method mem_master_m_arcache
assign mem_master_arcache =
llc_axi4_adapter_master_xactor_rg_rd_addr[14:11] ;
// value method mem_master_m_arprot
assign mem_master_arprot = llc_axi4_adapter_master_xactor_rg_rd_addr[10:8] ;
// value method mem_master_m_arqos
assign mem_master_arqos = llc_axi4_adapter_master_xactor_rg_rd_addr[7:4] ;
// value method mem_master_m_arregion
assign mem_master_arregion =
llc_axi4_adapter_master_xactor_rg_rd_addr[3:0] ;
// action method mem_master_m_arready
assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
assign WILL_FIRE_mem_master_m_arready = 1'd1 ;
// action method mem_master_m_rvalid
assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;
// value method mem_master_m_rready
assign mem_master_rready =
!llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;
// action method server_fence_i_request_put
assign RDY_server_fence_i_request_put = 1'd1 ;
assign CAN_FIRE_server_fence_i_request_put = 1'd1 ;
assign WILL_FIRE_server_fence_i_request_put =
EN_server_fence_i_request_put ;
// action method server_fence_i_response_get
assign RDY_server_fence_i_response_get = 1'd1 ;
assign CAN_FIRE_server_fence_i_response_get = 1'd1 ;
assign WILL_FIRE_server_fence_i_response_get =
EN_server_fence_i_response_get ;
// action method server_fence_request_put
assign RDY_server_fence_request_put = 1'd1 ;
assign CAN_FIRE_server_fence_request_put = 1'd1 ;
assign WILL_FIRE_server_fence_request_put = EN_server_fence_request_put ;
// action method server_fence_response_get
assign RDY_server_fence_response_get = 1'd1 ;
assign CAN_FIRE_server_fence_response_get = 1'd1 ;
assign WILL_FIRE_server_fence_response_get = EN_server_fence_response_get ;
// action method sfence_vma_server_request_put
assign RDY_sfence_vma_server_request_put = 1'd1 ;
assign CAN_FIRE_sfence_vma_server_request_put = 1'd1 ;
assign WILL_FIRE_sfence_vma_server_request_put =
EN_sfence_vma_server_request_put ;
// action method sfence_vma_server_response_get
assign RDY_sfence_vma_server_response_get = 1'd1 ;
assign CAN_FIRE_sfence_vma_server_response_get = 1'd1 ;
assign WILL_FIRE_sfence_vma_server_response_get =
EN_sfence_vma_server_response_get ;
// action method dma_server_m_awvalid
assign CAN_FIRE_dma_server_m_awvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_awvalid = 1'd1 ;
// value method dma_server_m_awready
assign dma_server_awready = dma_cache$axi4_s_awready ;
// action method dma_server_m_wvalid
assign CAN_FIRE_dma_server_m_wvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_wvalid = 1'd1 ;
// value method dma_server_m_wready
assign dma_server_wready = dma_cache$axi4_s_wready ;
// value method dma_server_m_bvalid
assign dma_server_bvalid = dma_cache$axi4_s_bvalid ;
// value method dma_server_m_bid
assign dma_server_bid = dma_cache$axi4_s_bid ;
// value method dma_server_m_bresp
assign dma_server_bresp = dma_cache$axi4_s_bresp ;
// action method dma_server_m_bready
assign CAN_FIRE_dma_server_m_bready = 1'd1 ;
assign WILL_FIRE_dma_server_m_bready = 1'd1 ;
// action method dma_server_m_arvalid
assign CAN_FIRE_dma_server_m_arvalid = 1'd1 ;
assign WILL_FIRE_dma_server_m_arvalid = 1'd1 ;
// value method dma_server_m_arready
assign dma_server_arready = dma_cache$axi4_s_arready ;
// value method dma_server_m_rvalid
assign dma_server_rvalid = dma_cache$axi4_s_rvalid ;
// value method dma_server_m_rid
assign dma_server_rid = dma_cache$axi4_s_rid ;
// value method dma_server_m_rdata
assign dma_server_rdata = dma_cache$axi4_s_rdata ;
// value method dma_server_m_rresp
assign dma_server_rresp = dma_cache$axi4_s_rresp ;
// value method dma_server_m_rlast
assign dma_server_rlast = dma_cache$axi4_s_rlast ;
// action method dma_server_m_rready
assign CAN_FIRE_dma_server_m_rready = 1'd1 ;
assign WILL_FIRE_dma_server_m_rready = 1'd1 ;
// action method set_watch_tohost
assign RDY_set_watch_tohost = 1'd1 ;
assign CAN_FIRE_set_watch_tohost = 1'd1 ;
assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ;
// value method mv_tohost_value
assign mv_tohost_value = d_mmu_cache$mv_tohost_value ;
assign RDY_mv_tohost_value = 1'd1 ;
// action method ma_ddr4_ready
assign RDY_ma_ddr4_ready = 1'd1 ;
assign CAN_FIRE_ma_ddr4_ready = 1'd1 ;
assign WILL_FIRE_ma_ddr4_ready = EN_ma_ddr4_ready ;
// value method mv_status
assign mv_status = llc_axi4_adapter_rg_AXI4_error ? 8'd1 : 8'd0 ;
// submodule d_mmu_cache
mkD_MMU_Cache d_mmu_cache(.CLK(CLK),
.RST_N(RST_N),
.flush_server_request_put(d_mmu_cache$flush_server_request_put),
.imem_pte_writeback_p_put(d_mmu_cache$imem_pte_writeback_p_put),
.imem_ptw_server_request_put(d_mmu_cache$imem_ptw_server_request_put),
.l1_to_l2_client_response_enq_x(d_mmu_cache$l1_to_l2_client_response_enq_x),
.l2_to_l1_server_request_enq_x(d_mmu_cache$l2_to_l1_server_request_enq_x),
.ma_req_amo_funct7(d_mmu_cache$ma_req_amo_funct7),
.ma_req_f3(d_mmu_cache$ma_req_f3),
.ma_req_mstatus_MXR(d_mmu_cache$ma_req_mstatus_MXR),
.ma_req_op(d_mmu_cache$ma_req_op),
.ma_req_priv(d_mmu_cache$ma_req_priv),
.ma_req_satp(d_mmu_cache$ma_req_satp),
.ma_req_sstatus_SUM(d_mmu_cache$ma_req_sstatus_SUM),
.ma_req_st_value(d_mmu_cache$ma_req_st_value),
.ma_req_va(d_mmu_cache$ma_req_va),
.mmio_client_response_put(d_mmu_cache$mmio_client_response_put),
.set_watch_tohost_tohost_addr(d_mmu_cache$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(d_mmu_cache$set_watch_tohost_watch_tohost),
.EN_ma_req(d_mmu_cache$EN_ma_req),
.EN_flush_server_request_put(d_mmu_cache$EN_flush_server_request_put),
.EN_flush_server_response_get(d_mmu_cache$EN_flush_server_response_get),
.EN_tlb_flush(d_mmu_cache$EN_tlb_flush),
.EN_imem_ptw_server_request_put(d_mmu_cache$EN_imem_ptw_server_request_put),
.EN_imem_ptw_server_response_get(d_mmu_cache$EN_imem_ptw_server_response_get),
.EN_imem_pte_writeback_p_put(d_mmu_cache$EN_imem_pte_writeback_p_put),
.EN_l1_to_l2_client_request_deq(d_mmu_cache$EN_l1_to_l2_client_request_deq),
.EN_l1_to_l2_client_response_enq(d_mmu_cache$EN_l1_to_l2_client_response_enq),
.EN_l2_to_l1_server_request_enq(d_mmu_cache$EN_l2_to_l1_server_request_enq),
.EN_l2_to_l1_server_response_deq(d_mmu_cache$EN_l2_to_l1_server_response_deq),
.EN_mmio_client_request_get(d_mmu_cache$EN_mmio_client_request_get),
.EN_mmio_client_response_put(d_mmu_cache$EN_mmio_client_response_put),
.EN_set_watch_tohost(d_mmu_cache$EN_set_watch_tohost),
.valid(d_mmu_cache$valid),
.addr(),
.word64(d_mmu_cache$word64),
.st_amo_val(d_mmu_cache$st_amo_val),
.exc(d_mmu_cache$exc),
.exc_code(d_mmu_cache$exc_code),
.RDY_flush_server_request_put(),
.RDY_flush_server_response_get(),
.RDY_tlb_flush(),
.RDY_imem_ptw_server_request_put(d_mmu_cache$RDY_imem_ptw_server_request_put),
.imem_ptw_server_response_get(d_mmu_cache$imem_ptw_server_response_get),
.RDY_imem_ptw_server_response_get(d_mmu_cache$RDY_imem_ptw_server_response_get),
.RDY_imem_pte_writeback_p_put(d_mmu_cache$RDY_imem_pte_writeback_p_put),
.l1_to_l2_client_request_first(d_mmu_cache$l1_to_l2_client_request_first),
.RDY_l1_to_l2_client_request_first(d_mmu_cache$RDY_l1_to_l2_client_request_first),
.RDY_l1_to_l2_client_request_deq(d_mmu_cache$RDY_l1_to_l2_client_request_deq),
.l1_to_l2_client_request_notEmpty(),
.RDY_l1_to_l2_client_request_notEmpty(),
.RDY_l1_to_l2_client_response_enq(d_mmu_cache$RDY_l1_to_l2_client_response_enq),
.l1_to_l2_client_response_notFull(),
.RDY_l1_to_l2_client_response_notFull(),
.RDY_l2_to_l1_server_request_enq(d_mmu_cache$RDY_l2_to_l1_server_request_enq),
.l2_to_l1_server_request_notFull(),
.RDY_l2_to_l1_server_request_notFull(),
.l2_to_l1_server_response_first(d_mmu_cache$l2_to_l1_server_response_first),
.RDY_l2_to_l1_server_response_first(d_mmu_cache$RDY_l2_to_l1_server_response_first),
.RDY_l2_to_l1_server_response_deq(d_mmu_cache$RDY_l2_to_l1_server_response_deq),
.l2_to_l1_server_response_notEmpty(),
.RDY_l2_to_l1_server_response_notEmpty(),
.mmio_client_request_get(d_mmu_cache$mmio_client_request_get),
.RDY_mmio_client_request_get(d_mmu_cache$RDY_mmio_client_request_get),
.RDY_mmio_client_response_put(d_mmu_cache$RDY_mmio_client_response_put),
.RDY_set_watch_tohost(),
.mv_tohost_value(d_mmu_cache$mv_tohost_value),
.RDY_mv_tohost_value());
// submodule dma_cache
mkDMA_Cache dma_cache(.CLK(CLK),
.RST_N(RST_N),
.axi4_s_araddr(dma_cache$axi4_s_araddr),
.axi4_s_arburst(dma_cache$axi4_s_arburst),
.axi4_s_arcache(dma_cache$axi4_s_arcache),
.axi4_s_arid(dma_cache$axi4_s_arid),
.axi4_s_arlen(dma_cache$axi4_s_arlen),
.axi4_s_arlock(dma_cache$axi4_s_arlock),
.axi4_s_arprot(dma_cache$axi4_s_arprot),
.axi4_s_arqos(dma_cache$axi4_s_arqos),
.axi4_s_arregion(dma_cache$axi4_s_arregion),
.axi4_s_arsize(dma_cache$axi4_s_arsize),
.axi4_s_arvalid(dma_cache$axi4_s_arvalid),
.axi4_s_awaddr(dma_cache$axi4_s_awaddr),
.axi4_s_awburst(dma_cache$axi4_s_awburst),
.axi4_s_awcache(dma_cache$axi4_s_awcache),
.axi4_s_awid(dma_cache$axi4_s_awid),
.axi4_s_awlen(dma_cache$axi4_s_awlen),
.axi4_s_awlock(dma_cache$axi4_s_awlock),
.axi4_s_awprot(dma_cache$axi4_s_awprot),
.axi4_s_awqos(dma_cache$axi4_s_awqos),
.axi4_s_awregion(dma_cache$axi4_s_awregion),
.axi4_s_awsize(dma_cache$axi4_s_awsize),
.axi4_s_awvalid(dma_cache$axi4_s_awvalid),
.axi4_s_bready(dma_cache$axi4_s_bready),
.axi4_s_rready(dma_cache$axi4_s_rready),
.axi4_s_wdata(dma_cache$axi4_s_wdata),
.axi4_s_wlast(dma_cache$axi4_s_wlast),
.axi4_s_wstrb(dma_cache$axi4_s_wstrb),
.axi4_s_wvalid(dma_cache$axi4_s_wvalid),
.l1_to_l2_client_response_enq_x(dma_cache$l1_to_l2_client_response_enq_x),
.l2_to_l1_server_request_enq_x(dma_cache$l2_to_l1_server_request_enq_x),
.mmio_client_response_put(dma_cache$mmio_client_response_put),
.EN_l1_to_l2_client_request_deq(dma_cache$EN_l1_to_l2_client_request_deq),
.EN_l1_to_l2_client_response_enq(dma_cache$EN_l1_to_l2_client_response_enq),
.EN_l2_to_l1_server_request_enq(dma_cache$EN_l2_to_l1_server_request_enq),
.EN_l2_to_l1_server_response_deq(dma_cache$EN_l2_to_l1_server_response_deq),
.EN_mmio_client_request_get(dma_cache$EN_mmio_client_request_get),
.EN_mmio_client_response_put(dma_cache$EN_mmio_client_response_put),
.axi4_s_awready(dma_cache$axi4_s_awready),
.axi4_s_wready(dma_cache$axi4_s_wready),
.axi4_s_bvalid(dma_cache$axi4_s_bvalid),
.axi4_s_bid(dma_cache$axi4_s_bid),
.axi4_s_bresp(dma_cache$axi4_s_bresp),
.axi4_s_arready(dma_cache$axi4_s_arready),
.axi4_s_rvalid(dma_cache$axi4_s_rvalid),
.axi4_s_rid(dma_cache$axi4_s_rid),
.axi4_s_rdata(dma_cache$axi4_s_rdata),
.axi4_s_rresp(dma_cache$axi4_s_rresp),
.axi4_s_rlast(dma_cache$axi4_s_rlast),
.l1_to_l2_client_request_first(dma_cache$l1_to_l2_client_request_first),
.RDY_l1_to_l2_client_request_first(dma_cache$RDY_l1_to_l2_client_request_first),
.RDY_l1_to_l2_client_request_deq(dma_cache$RDY_l1_to_l2_client_request_deq),
.l1_to_l2_client_request_notEmpty(),
.RDY_l1_to_l2_client_request_notEmpty(),
.RDY_l1_to_l2_client_response_enq(dma_cache$RDY_l1_to_l2_client_response_enq),
.l1_to_l2_client_response_notFull(),
.RDY_l1_to_l2_client_response_notFull(),
.RDY_l2_to_l1_server_request_enq(dma_cache$RDY_l2_to_l1_server_request_enq),
.l2_to_l1_server_request_notFull(),
.RDY_l2_to_l1_server_request_notFull(),
.l2_to_l1_server_response_first(dma_cache$l2_to_l1_server_response_first),
.RDY_l2_to_l1_server_response_first(dma_cache$RDY_l2_to_l1_server_response_first),
.RDY_l2_to_l1_server_response_deq(dma_cache$RDY_l2_to_l1_server_response_deq),
.l2_to_l1_server_response_notEmpty(),
.RDY_l2_to_l1_server_response_notEmpty(),
.mmio_client_request_get(dma_cache$mmio_client_request_get),
.RDY_mmio_client_request_get(dma_cache$RDY_mmio_client_request_get),
.RDY_mmio_client_response_put(dma_cache$RDY_mmio_client_response_put));
// submodule enqDst_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) enqDst_0_dummy2_0(.CLK(CLK),
.D_IN(enqDst_0_dummy2_0$D_IN),
.EN(enqDst_0_dummy2_0$EN),
.Q_OUT(enqDst_0_dummy2_0$Q_OUT));
// submodule enqDst_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) enqDst_0_dummy2_1(.CLK(CLK),
.D_IN(enqDst_0_dummy2_1$D_IN),
.EN(enqDst_0_dummy2_1$EN),
.Q_OUT(enqDst_0_dummy2_1$Q_OUT));
// submodule enqDst_1_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) enqDst_1_0_dummy2_0(.CLK(CLK),
.D_IN(enqDst_1_0_dummy2_0$D_IN),
.EN(enqDst_1_0_dummy2_0$EN),
.Q_OUT(enqDst_1_0_dummy2_0$Q_OUT));
// submodule enqDst_1_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) enqDst_1_0_dummy2_1(.CLK(CLK),
.D_IN(enqDst_1_0_dummy2_1$D_IN),
.EN(enqDst_1_0_dummy2_1$EN),
.Q_OUT(enqDst_1_0_dummy2_1$Q_OUT));
// submodule f_reset_rsps
FIFO20 #(.guarded(1'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule i_mmu_cache
mkI_MMU_Cache i_mmu_cache(.CLK(CLK),
.RST_N(RST_N),
.flush_server_request_put(i_mmu_cache$flush_server_request_put),
.l1_to_l2_client_response_enq_x(i_mmu_cache$l1_to_l2_client_response_enq_x),
.l2_to_l1_server_request_enq_x(i_mmu_cache$l2_to_l1_server_request_enq_x),
.ma_req_mstatus_MXR(i_mmu_cache$ma_req_mstatus_MXR),
.ma_req_priv(i_mmu_cache$ma_req_priv),
.ma_req_satp(i_mmu_cache$ma_req_satp),
.ma_req_sstatus_SUM(i_mmu_cache$ma_req_sstatus_SUM),
.ma_req_va(i_mmu_cache$ma_req_va),
.mmio_client_response_put(i_mmu_cache$mmio_client_response_put),
.ptw_client_response_put(i_mmu_cache$ptw_client_response_put),
.EN_ma_req(i_mmu_cache$EN_ma_req),
.EN_flush_server_request_put(i_mmu_cache$EN_flush_server_request_put),
.EN_flush_server_response_get(i_mmu_cache$EN_flush_server_response_get),
.EN_tlb_flush(i_mmu_cache$EN_tlb_flush),
.EN_ptw_client_request_get(i_mmu_cache$EN_ptw_client_request_get),
.EN_ptw_client_response_put(i_mmu_cache$EN_ptw_client_response_put),
.EN_pte_writeback_g_get(i_mmu_cache$EN_pte_writeback_g_get),
.EN_l1_to_l2_client_request_deq(i_mmu_cache$EN_l1_to_l2_client_request_deq),
.EN_l1_to_l2_client_response_enq(i_mmu_cache$EN_l1_to_l2_client_response_enq),
.EN_l2_to_l1_server_request_enq(i_mmu_cache$EN_l2_to_l1_server_request_enq),
.EN_l2_to_l1_server_response_deq(i_mmu_cache$EN_l2_to_l1_server_response_deq),
.EN_mmio_client_request_get(i_mmu_cache$EN_mmio_client_request_get),
.EN_mmio_client_response_put(i_mmu_cache$EN_mmio_client_response_put),
.valid(i_mmu_cache$valid),
.addr(i_mmu_cache$addr),
.word64(i_mmu_cache$word64),
.exc(i_mmu_cache$exc),
.exc_code(i_mmu_cache$exc_code),
.RDY_flush_server_request_put(),
.RDY_flush_server_response_get(),
.RDY_tlb_flush(),
.ptw_client_request_get(i_mmu_cache$ptw_client_request_get),
.RDY_ptw_client_request_get(i_mmu_cache$RDY_ptw_client_request_get),
.RDY_ptw_client_response_put(i_mmu_cache$RDY_ptw_client_response_put),
.pte_writeback_g_get(i_mmu_cache$pte_writeback_g_get),
.RDY_pte_writeback_g_get(i_mmu_cache$RDY_pte_writeback_g_get),
.l1_to_l2_client_request_first(i_mmu_cache$l1_to_l2_client_request_first),
.RDY_l1_to_l2_client_request_first(i_mmu_cache$RDY_l1_to_l2_client_request_first),
.RDY_l1_to_l2_client_request_deq(i_mmu_cache$RDY_l1_to_l2_client_request_deq),
.l1_to_l2_client_request_notEmpty(),
.RDY_l1_to_l2_client_request_notEmpty(),
.RDY_l1_to_l2_client_response_enq(i_mmu_cache$RDY_l1_to_l2_client_response_enq),
.l1_to_l2_client_response_notFull(),
.RDY_l1_to_l2_client_response_notFull(),
.RDY_l2_to_l1_server_request_enq(i_mmu_cache$RDY_l2_to_l1_server_request_enq),
.l2_to_l1_server_request_notFull(),
.RDY_l2_to_l1_server_request_notFull(),
.l2_to_l1_server_response_first(i_mmu_cache$l2_to_l1_server_response_first),
.RDY_l2_to_l1_server_response_first(i_mmu_cache$RDY_l2_to_l1_server_response_first),
.RDY_l2_to_l1_server_response_deq(i_mmu_cache$RDY_l2_to_l1_server_response_deq),
.l2_to_l1_server_response_notEmpty(),
.RDY_l2_to_l1_server_response_notEmpty(),
.mmio_client_request_get(i_mmu_cache$mmio_client_request_get),
.RDY_mmio_client_request_get(i_mmu_cache$RDY_mmio_client_request_get),
.RDY_mmio_client_response_put(i_mmu_cache$RDY_mmio_client_response_put));
// submodule llc
mkLLCache llc(.CLK(CLK),
.RST_N(RST_N),
.dma_memReq_enq_x(llc$dma_memReq_enq_x),
.perf_req_r(llc$perf_req_r),
.perf_setStatus_doStats(llc$perf_setStatus_doStats),
.to_child_rqFromC_enq_x(llc$to_child_rqFromC_enq_x),
.to_child_rsFromC_enq_x(llc$to_child_rsFromC_enq_x),
.to_mem_rsFromM_enq_x(llc$to_mem_rsFromM_enq_x),
.EN_to_child_rsFromC_enq(llc$EN_to_child_rsFromC_enq),
.EN_to_child_rqFromC_enq(llc$EN_to_child_rqFromC_enq),
.EN_to_child_toC_deq(llc$EN_to_child_toC_deq),
.EN_dma_memReq_enq(llc$EN_dma_memReq_enq),
.EN_dma_respLd_deq(llc$EN_dma_respLd_deq),
.EN_dma_respSt_deq(llc$EN_dma_respSt_deq),
.EN_to_mem_toM_deq(llc$EN_to_mem_toM_deq),
.EN_to_mem_rsFromM_enq(llc$EN_to_mem_rsFromM_enq),
.EN_cRqStuck_get(llc$EN_cRqStuck_get),
.EN_perf_setStatus(llc$EN_perf_setStatus),
.EN_perf_req(llc$EN_perf_req),
.EN_perf_resp(llc$EN_perf_resp),
.to_child_rsFromC_notFull(),
.RDY_to_child_rsFromC_notFull(),
.RDY_to_child_rsFromC_enq(llc$RDY_to_child_rsFromC_enq),
.to_child_rqFromC_notFull(),
.RDY_to_child_rqFromC_notFull(),
.RDY_to_child_rqFromC_enq(llc$RDY_to_child_rqFromC_enq),
.to_child_toC_notEmpty(),
.RDY_to_child_toC_notEmpty(),
.RDY_to_child_toC_deq(llc$RDY_to_child_toC_deq),
.to_child_toC_first(llc$to_child_toC_first),
.RDY_to_child_toC_first(llc$RDY_to_child_toC_first),
.dma_memReq_notFull(),
.RDY_dma_memReq_notFull(),
.RDY_dma_memReq_enq(),
.dma_respLd_notEmpty(),
.RDY_dma_respLd_notEmpty(),
.RDY_dma_respLd_deq(llc$RDY_dma_respLd_deq),
.dma_respLd_first(),
.RDY_dma_respLd_first(),
.dma_respSt_notEmpty(),
.RDY_dma_respSt_notEmpty(),
.RDY_dma_respSt_deq(llc$RDY_dma_respSt_deq),
.dma_respSt_first(),
.RDY_dma_respSt_first(),
.to_mem_toM_notEmpty(),
.RDY_to_mem_toM_notEmpty(),
.RDY_to_mem_toM_deq(llc$RDY_to_mem_toM_deq),
.to_mem_toM_first(llc$to_mem_toM_first),
.RDY_to_mem_toM_first(llc$RDY_to_mem_toM_first),
.to_mem_rsFromM_notFull(),
.RDY_to_mem_rsFromM_notFull(),
.RDY_to_mem_rsFromM_enq(llc$RDY_to_mem_rsFromM_enq),
.cRqStuck_get(),
.RDY_cRqStuck_get(),
.RDY_perf_setStatus(),
.RDY_perf_req(),
.perf_resp(),
.RDY_perf_resp(),
.perf_respValid(),
.RDY_perf_respValid());
// submodule llc_axi4_adapter_f_pending_reads
FIFO2 #(.width(32'd69),
.guarded(1'd1)) llc_axi4_adapter_f_pending_reads(.RST(RST_N),
.CLK(CLK),
.D_IN(llc_axi4_adapter_f_pending_reads$D_IN),
.ENQ(llc_axi4_adapter_f_pending_reads$ENQ),
.DEQ(llc_axi4_adapter_f_pending_reads$DEQ),
.CLR(llc_axi4_adapter_f_pending_reads$CLR),
.D_OUT(llc_axi4_adapter_f_pending_reads$D_OUT),
.FULL_N(llc_axi4_adapter_f_pending_reads$FULL_N),
.EMPTY_N(llc_axi4_adapter_f_pending_reads$EMPTY_N));
// submodule llc_axi4_adapter_f_pending_writes
FIFO2 #(.width(32'd640),
.guarded(1'd1)) llc_axi4_adapter_f_pending_writes(.RST(RST_N),
.CLK(CLK),
.D_IN(llc_axi4_adapter_f_pending_writes$D_IN),
.ENQ(llc_axi4_adapter_f_pending_writes$ENQ),
.DEQ(llc_axi4_adapter_f_pending_writes$DEQ),
.CLR(llc_axi4_adapter_f_pending_writes$CLR),
.D_OUT(),
.FULL_N(llc_axi4_adapter_f_pending_writes$FULL_N),
.EMPTY_N(llc_axi4_adapter_f_pending_writes$EMPTY_N));
// submodule mmio_axi4_adapter
mkMMIO_AXI4_Adapter_2 #(.verbosity(3'd0)) mmio_axi4_adapter(.CLK(CLK),
.RST_N(RST_N),
.mem_master_arready(mmio_axi4_adapter$mem_master_arready),
.mem_master_awready(mmio_axi4_adapter$mem_master_awready),
.mem_master_bid(mmio_axi4_adapter$mem_master_bid),
.mem_master_bresp(mmio_axi4_adapter$mem_master_bresp),
.mem_master_bvalid(mmio_axi4_adapter$mem_master_bvalid),
.mem_master_rdata(mmio_axi4_adapter$mem_master_rdata),
.mem_master_rid(mmio_axi4_adapter$mem_master_rid),
.mem_master_rlast(mmio_axi4_adapter$mem_master_rlast),
.mem_master_rresp(mmio_axi4_adapter$mem_master_rresp),
.mem_master_rvalid(mmio_axi4_adapter$mem_master_rvalid),
.mem_master_wready(mmio_axi4_adapter$mem_master_wready),
.v_mmio_server_0_request_put(mmio_axi4_adapter$v_mmio_server_0_request_put),
.v_mmio_server_1_request_put(mmio_axi4_adapter$v_mmio_server_1_request_put),
.v_mmio_server_2_request_put(mmio_axi4_adapter$v_mmio_server_2_request_put),
.EN_v_mmio_server_0_request_put(mmio_axi4_adapter$EN_v_mmio_server_0_request_put),
.EN_v_mmio_server_0_response_get(mmio_axi4_adapter$EN_v_mmio_server_0_response_get),
.EN_v_mmio_server_1_request_put(mmio_axi4_adapter$EN_v_mmio_server_1_request_put),
.EN_v_mmio_server_1_response_get(mmio_axi4_adapter$EN_v_mmio_server_1_response_get),
.EN_v_mmio_server_2_request_put(mmio_axi4_adapter$EN_v_mmio_server_2_request_put),
.EN_v_mmio_server_2_response_get(mmio_axi4_adapter$EN_v_mmio_server_2_response_get),
.RDY_v_mmio_server_0_request_put(mmio_axi4_adapter$RDY_v_mmio_server_0_request_put),
.v_mmio_server_0_response_get(mmio_axi4_adapter$v_mmio_server_0_response_get),
.RDY_v_mmio_server_0_response_get(mmio_axi4_adapter$RDY_v_mmio_server_0_response_get),
.RDY_v_mmio_server_1_request_put(mmio_axi4_adapter$RDY_v_mmio_server_1_request_put),
.v_mmio_server_1_response_get(mmio_axi4_adapter$v_mmio_server_1_response_get),
.RDY_v_mmio_server_1_response_get(mmio_axi4_adapter$RDY_v_mmio_server_1_response_get),
.RDY_v_mmio_server_2_request_put(mmio_axi4_adapter$RDY_v_mmio_server_2_request_put),
.v_mmio_server_2_response_get(mmio_axi4_adapter$v_mmio_server_2_response_get),
.RDY_v_mmio_server_2_response_get(mmio_axi4_adapter$RDY_v_mmio_server_2_response_get),
.mem_master_awvalid(mmio_axi4_adapter$mem_master_awvalid),
.mem_master_awid(mmio_axi4_adapter$mem_master_awid),
.mem_master_awaddr(mmio_axi4_adapter$mem_master_awaddr),
.mem_master_awlen(mmio_axi4_adapter$mem_master_awlen),
.mem_master_awsize(mmio_axi4_adapter$mem_master_awsize),
.mem_master_awburst(mmio_axi4_adapter$mem_master_awburst),
.mem_master_awlock(mmio_axi4_adapter$mem_master_awlock),
.mem_master_awcache(mmio_axi4_adapter$mem_master_awcache),
.mem_master_awprot(mmio_axi4_adapter$mem_master_awprot),
.mem_master_awqos(mmio_axi4_adapter$mem_master_awqos),
.mem_master_awregion(mmio_axi4_adapter$mem_master_awregion),
.mem_master_wvalid(mmio_axi4_adapter$mem_master_wvalid),
.mem_master_wdata(mmio_axi4_adapter$mem_master_wdata),
.mem_master_wstrb(mmio_axi4_adapter$mem_master_wstrb),
.mem_master_wlast(mmio_axi4_adapter$mem_master_wlast),
.mem_master_bready(mmio_axi4_adapter$mem_master_bready),
.mem_master_arvalid(mmio_axi4_adapter$mem_master_arvalid),
.mem_master_arid(mmio_axi4_adapter$mem_master_arid),
.mem_master_araddr(mmio_axi4_adapter$mem_master_araddr),
.mem_master_arlen(mmio_axi4_adapter$mem_master_arlen),
.mem_master_arsize(mmio_axi4_adapter$mem_master_arsize),
.mem_master_arburst(mmio_axi4_adapter$mem_master_arburst),
.mem_master_arlock(mmio_axi4_adapter$mem_master_arlock),
.mem_master_arcache(mmio_axi4_adapter$mem_master_arcache),
.mem_master_arprot(mmio_axi4_adapter$mem_master_arprot),
.mem_master_arqos(mmio_axi4_adapter$mem_master_arqos),
.mem_master_arregion(mmio_axi4_adapter$mem_master_arregion),
.mem_master_rready(mmio_axi4_adapter$mem_master_rready),
.mv_write_error());
// submodule propDstData_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_0_dummy2_0(.CLK(CLK),
.D_IN(propDstData_0_dummy2_0$D_IN),
.EN(propDstData_0_dummy2_0$EN),
.Q_OUT());
// submodule propDstData_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_0_dummy2_1(.CLK(CLK),
.D_IN(propDstData_0_dummy2_1$D_IN),
.EN(propDstData_0_dummy2_1$EN),
.Q_OUT(propDstData_0_dummy2_1$Q_OUT));
// submodule propDstData_1_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_0_dummy2_0(.CLK(CLK),
.D_IN(propDstData_1_0_dummy2_0$D_IN),
.EN(propDstData_1_0_dummy2_0$EN),
.Q_OUT());
// submodule propDstData_1_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_0_dummy2_1(.CLK(CLK),
.D_IN(propDstData_1_0_dummy2_1$D_IN),
.EN(propDstData_1_0_dummy2_1$EN),
.Q_OUT(propDstData_1_0_dummy2_1$Q_OUT));
// submodule propDstData_1_1_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_1_dummy2_0(.CLK(CLK),
.D_IN(propDstData_1_1_dummy2_0$D_IN),
.EN(propDstData_1_1_dummy2_0$EN),
.Q_OUT());
// submodule propDstData_1_1_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_1_dummy2_1(.CLK(CLK),
.D_IN(propDstData_1_1_dummy2_1$D_IN),
.EN(propDstData_1_1_dummy2_1$EN),
.Q_OUT(propDstData_1_1_dummy2_1$Q_OUT));
// submodule propDstData_1_2_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_2_dummy2_0(.CLK(CLK),
.D_IN(propDstData_1_2_dummy2_0$D_IN),
.EN(propDstData_1_2_dummy2_0$EN),
.Q_OUT());
// submodule propDstData_1_2_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_2_dummy2_1(.CLK(CLK),
.D_IN(propDstData_1_2_dummy2_1$D_IN),
.EN(propDstData_1_2_dummy2_1$EN),
.Q_OUT(propDstData_1_2_dummy2_1$Q_OUT));
// submodule propDstData_1_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_dummy2_0(.CLK(CLK),
.D_IN(propDstData_1_dummy2_0$D_IN),
.EN(propDstData_1_dummy2_0$EN),
.Q_OUT());
// submodule propDstData_1_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_dummy2_1(.CLK(CLK),
.D_IN(propDstData_1_dummy2_1$D_IN),
.EN(propDstData_1_dummy2_1$EN),
.Q_OUT(propDstData_1_dummy2_1$Q_OUT));
// submodule propDstData_2_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_2_dummy2_0(.CLK(CLK),
.D_IN(propDstData_2_dummy2_0$D_IN),
.EN(propDstData_2_dummy2_0$EN),
.Q_OUT());
// submodule propDstData_2_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_2_dummy2_1(.CLK(CLK),
.D_IN(propDstData_2_dummy2_1$D_IN),
.EN(propDstData_2_dummy2_1$EN),
.Q_OUT(propDstData_2_dummy2_1$Q_OUT));
// submodule propDstIdx_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_0_dummy2_0(.CLK(CLK),
.D_IN(propDstIdx_0_dummy2_0$D_IN),
.EN(propDstIdx_0_dummy2_0$EN),
.Q_OUT(propDstIdx_0_dummy2_0$Q_OUT));
// submodule propDstIdx_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_0_dummy2_1(.CLK(CLK),
.D_IN(propDstIdx_0_dummy2_1$D_IN),
.EN(propDstIdx_0_dummy2_1$EN),
.Q_OUT(propDstIdx_0_dummy2_1$Q_OUT));
// submodule propDstIdx_1_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_0_dummy2_0(.CLK(CLK),
.D_IN(propDstIdx_1_0_dummy2_0$D_IN),
.EN(propDstIdx_1_0_dummy2_0$EN),
.Q_OUT(propDstIdx_1_0_dummy2_0$Q_OUT));
// submodule propDstIdx_1_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_0_dummy2_1(.CLK(CLK),
.D_IN(propDstIdx_1_0_dummy2_1$D_IN),
.EN(propDstIdx_1_0_dummy2_1$EN),
.Q_OUT(propDstIdx_1_0_dummy2_1$Q_OUT));
// submodule propDstIdx_1_1_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_1_dummy2_0(.CLK(CLK),
.D_IN(propDstIdx_1_1_dummy2_0$D_IN),
.EN(propDstIdx_1_1_dummy2_0$EN),
.Q_OUT(propDstIdx_1_1_dummy2_0$Q_OUT));
// submodule propDstIdx_1_1_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_1_dummy2_1(.CLK(CLK),
.D_IN(propDstIdx_1_1_dummy2_1$D_IN),
.EN(propDstIdx_1_1_dummy2_1$EN),
.Q_OUT(propDstIdx_1_1_dummy2_1$Q_OUT));
// submodule propDstIdx_1_2_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_2_dummy2_0(.CLK(CLK),
.D_IN(propDstIdx_1_2_dummy2_0$D_IN),
.EN(propDstIdx_1_2_dummy2_0$EN),
.Q_OUT(propDstIdx_1_2_dummy2_0$Q_OUT));
// submodule propDstIdx_1_2_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_2_dummy2_1(.CLK(CLK),
.D_IN(propDstIdx_1_2_dummy2_1$D_IN),
.EN(propDstIdx_1_2_dummy2_1$EN),
.Q_OUT(propDstIdx_1_2_dummy2_1$Q_OUT));
// submodule propDstIdx_1_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_dummy2_0(.CLK(CLK),
.D_IN(propDstIdx_1_dummy2_0$D_IN),
.EN(propDstIdx_1_dummy2_0$EN),
.Q_OUT(propDstIdx_1_dummy2_0$Q_OUT));
// submodule propDstIdx_1_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_dummy2_1(.CLK(CLK),
.D_IN(propDstIdx_1_dummy2_1$D_IN),
.EN(propDstIdx_1_dummy2_1$EN),
.Q_OUT(propDstIdx_1_dummy2_1$Q_OUT));
// submodule propDstIdx_2_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_2_dummy2_0(.CLK(CLK),
.D_IN(propDstIdx_2_dummy2_0$D_IN),
.EN(propDstIdx_2_dummy2_0$EN),
.Q_OUT(propDstIdx_2_dummy2_0$Q_OUT));
// submodule propDstIdx_2_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_2_dummy2_1(.CLK(CLK),
.D_IN(propDstIdx_2_dummy2_1$D_IN),
.EN(propDstIdx_2_dummy2_1$EN),
.Q_OUT(propDstIdx_2_dummy2_1$Q_OUT));
// rule RL_mkConnectionGetPut_1
assign CAN_FIRE_RL_mkConnectionGetPut_1 = llc$RDY_dma_respLd_deq ;
assign WILL_FIRE_RL_mkConnectionGetPut_1 = llc$RDY_dma_respLd_deq ;
// rule RL_mkConnectionGetPut_2
assign CAN_FIRE_RL_mkConnectionGetPut_2 = llc$RDY_dma_respSt_deq ;
assign WILL_FIRE_RL_mkConnectionGetPut_2 = llc$RDY_dma_respSt_deq ;
// rule RL_ClientServerRequest
assign CAN_FIRE_RL_ClientServerRequest =
d_mmu_cache$RDY_imem_ptw_server_request_put &&
i_mmu_cache$RDY_ptw_client_request_get ;
assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ;
// rule RL_ClientServerResponse
assign CAN_FIRE_RL_ClientServerResponse =
d_mmu_cache$RDY_imem_ptw_server_response_get &&
i_mmu_cache$RDY_ptw_client_response_put ;
assign WILL_FIRE_RL_ClientServerResponse =
CAN_FIRE_RL_ClientServerResponse ;
// rule RL_mkConnectionGetPut_3
assign CAN_FIRE_RL_mkConnectionGetPut_3 =
d_mmu_cache$RDY_imem_pte_writeback_p_put &&
i_mmu_cache$RDY_pte_writeback_g_get ;
assign WILL_FIRE_RL_mkConnectionGetPut_3 =
CAN_FIRE_RL_mkConnectionGetPut_3 ;
// rule RL_srcPropose
assign CAN_FIRE_RL_srcPropose =
i_mmu_cache$RDY_l1_to_l2_client_request_deq &&
i_mmu_cache$RDY_l1_to_l2_client_request_first &&
(!propDstIdx_0_dummy2_0$Q_OUT || !propDstIdx_0_dummy2_1$Q_OUT ||
!propDstIdx_0_rl) ;
assign WILL_FIRE_RL_srcPropose = CAN_FIRE_RL_srcPropose ;
// rule RL_srcPropose_1
assign CAN_FIRE_RL_srcPropose_1 =
d_mmu_cache$RDY_l1_to_l2_client_request_deq &&
d_mmu_cache$RDY_l1_to_l2_client_request_first &&
(!propDstIdx_1_dummy2_0$Q_OUT || !propDstIdx_1_dummy2_1$Q_OUT ||
!propDstIdx_1_rl) ;
assign WILL_FIRE_RL_srcPropose_1 = CAN_FIRE_RL_srcPropose_1 ;
// rule RL_srcPropose_2
assign CAN_FIRE_RL_srcPropose_2 =
dma_cache$RDY_l1_to_l2_client_request_deq &&
dma_cache$RDY_l1_to_l2_client_request_first &&
(!propDstIdx_2_dummy2_0$Q_OUT || !propDstIdx_2_dummy2_1$Q_OUT ||
!propDstIdx_2_rl) ;
assign WILL_FIRE_RL_srcPropose_2 = CAN_FIRE_RL_srcPropose_2 ;
// rule RL_dstSelectSrc
assign CAN_FIRE_RL_dstSelectSrc = 1'd1 ;
assign WILL_FIRE_RL_dstSelectSrc = 1'd1 ;
// rule RL_doEnq
assign CAN_FIRE_RL_doEnq =
llc$RDY_to_child_rqFromC_enq &&
enqDst_0_dummy2_1_read__31_AND_IF_enqDst_0_lat_ETC___d368 ;
assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ;
// rule RL_srcPropose_3
assign CAN_FIRE_RL_srcPropose_3 =
i_mmu_cache$RDY_l2_to_l1_server_response_deq &&
i_mmu_cache$RDY_l2_to_l1_server_response_first &&
(!propDstIdx_1_0_dummy2_0$Q_OUT ||
!propDstIdx_1_0_dummy2_1$Q_OUT ||
!propDstIdx_1_0_rl) ;
assign WILL_FIRE_RL_srcPropose_3 = CAN_FIRE_RL_srcPropose_3 ;
// rule RL_srcPropose_4
assign CAN_FIRE_RL_srcPropose_4 =
d_mmu_cache$RDY_l2_to_l1_server_response_deq &&
d_mmu_cache$RDY_l2_to_l1_server_response_first &&
(!propDstIdx_1_1_dummy2_0$Q_OUT ||
!propDstIdx_1_1_dummy2_1$Q_OUT ||
!propDstIdx_1_1_rl) ;
assign WILL_FIRE_RL_srcPropose_4 = CAN_FIRE_RL_srcPropose_4 ;
// rule RL_srcPropose_5
assign CAN_FIRE_RL_srcPropose_5 =
dma_cache$RDY_l2_to_l1_server_response_deq &&
dma_cache$RDY_l2_to_l1_server_response_first &&
(!propDstIdx_1_2_dummy2_0$Q_OUT ||
!propDstIdx_1_2_dummy2_1$Q_OUT ||
!propDstIdx_1_2_rl) ;
assign WILL_FIRE_RL_srcPropose_5 = CAN_FIRE_RL_srcPropose_5 ;
// rule RL_dstSelectSrc_1
assign CAN_FIRE_RL_dstSelectSrc_1 = 1'd1 ;
assign WILL_FIRE_RL_dstSelectSrc_1 = 1'd1 ;
// rule RL_doEnq_1
assign CAN_FIRE_RL_doEnq_1 =
llc$RDY_to_child_rsFromC_enq &&
enqDst_1_0_dummy2_1_read__64_AND_IF_enqDst_1_0_ETC___d664 ;
assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ;
// rule RL_sendPRq
assign CAN_FIRE_RL_sendPRq =
i_mmu_cache$RDY_l2_to_l1_server_request_enq &&
llc$RDY_to_child_toC_first &&
llc$RDY_to_child_toC_deq &&
!llc$to_child_toC_first[584] &&
llc$to_child_toC_first[1:0] == 2'd0 ;
assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ;
// rule RL_sendPRs
assign CAN_FIRE_RL_sendPRs =
i_mmu_cache$RDY_l1_to_l2_client_response_enq &&
llc$RDY_to_child_toC_first &&
llc$RDY_to_child_toC_deq &&
llc$to_child_toC_first[584] &&
llc$to_child_toC_first[517:516] == 2'd0 ;
assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ;
// rule RL_sendPRq_1
assign CAN_FIRE_RL_sendPRq_1 =
d_mmu_cache$RDY_l2_to_l1_server_request_enq &&
llc$RDY_to_child_toC_first &&
llc$RDY_to_child_toC_deq &&
!llc$to_child_toC_first[584] &&
llc$to_child_toC_first[1:0] == 2'd1 ;
assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ;
// rule RL_sendPRs_1
assign CAN_FIRE_RL_sendPRs_1 =
d_mmu_cache$RDY_l1_to_l2_client_response_enq &&
llc$RDY_to_child_toC_first &&
llc$RDY_to_child_toC_deq &&
llc$to_child_toC_first[584] &&
llc$to_child_toC_first[517:516] == 2'd1 ;
assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ;
// rule RL_sendPRq_2
assign CAN_FIRE_RL_sendPRq_2 =
dma_cache$RDY_l2_to_l1_server_request_enq &&
llc$RDY_to_child_toC_first &&
llc$RDY_to_child_toC_deq &&
!llc$to_child_toC_first[584] &&
llc$to_child_toC_first[1:0] == 2'd2 ;
assign WILL_FIRE_RL_sendPRq_2 = CAN_FIRE_RL_sendPRq_2 ;
// rule RL_sendPRs_2
assign CAN_FIRE_RL_sendPRs_2 =
dma_cache$RDY_l1_to_l2_client_response_enq &&
llc$RDY_to_child_toC_first &&
llc$RDY_to_child_toC_deq &&
llc$to_child_toC_first[584] &&
llc$to_child_toC_first[517:516] == 2'd2 ;
assign WILL_FIRE_RL_sendPRs_2 = CAN_FIRE_RL_sendPRs_2 ;
// rule RL_ClientServerRequest_1
assign CAN_FIRE_RL_ClientServerRequest_1 =
mmio_axi4_adapter$RDY_v_mmio_server_0_request_put &&
i_mmu_cache$RDY_mmio_client_request_get ;
assign WILL_FIRE_RL_ClientServerRequest_1 =
CAN_FIRE_RL_ClientServerRequest_1 ;
// rule RL_ClientServerResponse_1
assign CAN_FIRE_RL_ClientServerResponse_1 =
mmio_axi4_adapter$RDY_v_mmio_server_0_response_get &&
i_mmu_cache$RDY_mmio_client_response_put ;
assign WILL_FIRE_RL_ClientServerResponse_1 =
CAN_FIRE_RL_ClientServerResponse_1 ;
// rule RL_ClientServerRequest_2
assign CAN_FIRE_RL_ClientServerRequest_2 =
mmio_axi4_adapter$RDY_v_mmio_server_1_request_put &&
d_mmu_cache$RDY_mmio_client_request_get ;
assign WILL_FIRE_RL_ClientServerRequest_2 =
CAN_FIRE_RL_ClientServerRequest_2 ;
// rule RL_ClientServerResponse_2
assign CAN_FIRE_RL_ClientServerResponse_2 =
mmio_axi4_adapter$RDY_v_mmio_server_1_response_get &&
d_mmu_cache$RDY_mmio_client_response_put ;
assign WILL_FIRE_RL_ClientServerResponse_2 =
CAN_FIRE_RL_ClientServerResponse_2 ;
// rule RL_ClientServerRequest_3
assign CAN_FIRE_RL_ClientServerRequest_3 =
mmio_axi4_adapter$RDY_v_mmio_server_2_request_put &&
dma_cache$RDY_mmio_client_request_get ;
assign WILL_FIRE_RL_ClientServerRequest_3 =
CAN_FIRE_RL_ClientServerRequest_3 ;
// rule RL_ClientServerResponse_3
assign CAN_FIRE_RL_ClientServerResponse_3 =
mmio_axi4_adapter$RDY_v_mmio_server_2_response_get &&
dma_cache$RDY_mmio_client_response_put ;
assign WILL_FIRE_RL_ClientServerResponse_3 =
CAN_FIRE_RL_ClientServerResponse_3 ;
// rule RL_rl_reset
assign CAN_FIRE_RL_rl_reset = rg_state == 2'd0 ;
assign WILL_FIRE_RL_rl_reset = rg_state == 2'd0 ;
// rule RL_rl_reset_complete
assign CAN_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ;
assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_3 ;
// rule RL_llc_axi4_adapter_rl_handle_read_rsps
assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps =
llc_axi4_adapter_master_xactor_crg_rd_data_full &&
(llc_axi4_adapter_rg_rd_rsp_beat != 3'd7 ||
llc$RDY_to_mem_rsFromM_enq &&
llc_axi4_adapter_f_pending_reads$EMPTY_N) ;
assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ;
// rule RL_llc_axi4_adapter_rl_handle_write_req
assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req =
NOT_llc_axi4_adapter_master_xactor_crg_wr_addr_ETC___d80 &&
llc$to_mem_toM_first[640] &&
llc_axi4_adapter_rg_ddr4_ready ;
assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;
// rule RL_llc_axi4_adapter_rl_handle_read_req
assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req =
!llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read &&
llc$RDY_to_mem_toM_first &&
(llc_axi4_adapter_rg_rd_req_beat != 3'd0 ||
llc_axi4_adapter_f_pending_reads$FULL_N) &&
(llc_axi4_adapter_rg_rd_req_beat != 3'd7 ||
llc$RDY_to_mem_toM_deq) &&
!llc$to_mem_toM_first[640] &&
b__h13463 == 4'd0 &&
llc_axi4_adapter_rg_ddr4_ready ;
assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ;
// rule RL_llc_axi4_adapter_rl_discard_write_rsp
assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp =
b__h13463 != 4'd0 &&
llc_axi4_adapter_master_xactor_crg_wr_resp_full &&
(llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 ||
llc_axi4_adapter_f_pending_writes$EMPTY_N) ;
assign WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp =
CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ;
// rule RL_propDstIdx_0_canon
assign CAN_FIRE_RL_propDstIdx_0_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstIdx_0_canon = 1'd1 ;
// rule RL_propDstIdx_1_canon
assign CAN_FIRE_RL_propDstIdx_1_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstIdx_1_canon = 1'd1 ;
// rule RL_propDstIdx_2_canon
assign CAN_FIRE_RL_propDstIdx_2_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstIdx_2_canon = 1'd1 ;
// rule RL_propDstData_0_canon
assign CAN_FIRE_RL_propDstData_0_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstData_0_canon = 1'd1 ;
// rule RL_propDstData_1_canon
assign CAN_FIRE_RL_propDstData_1_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstData_1_canon = 1'd1 ;
// rule RL_propDstData_2_canon
assign CAN_FIRE_RL_propDstData_2_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstData_2_canon = 1'd1 ;
// rule RL_enqDst_0_canon
assign CAN_FIRE_RL_enqDst_0_canon = 1'd1 ;
assign WILL_FIRE_RL_enqDst_0_canon = 1'd1 ;
// rule RL_propDstIdx_1_0_canon
assign CAN_FIRE_RL_propDstIdx_1_0_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstIdx_1_0_canon = 1'd1 ;
// rule RL_propDstIdx_1_1_canon
assign CAN_FIRE_RL_propDstIdx_1_1_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstIdx_1_1_canon = 1'd1 ;
// rule RL_propDstIdx_1_2_canon
assign CAN_FIRE_RL_propDstIdx_1_2_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstIdx_1_2_canon = 1'd1 ;
// rule RL_propDstData_1_0_canon
assign CAN_FIRE_RL_propDstData_1_0_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstData_1_0_canon = 1'd1 ;
// rule RL_propDstData_1_1_canon
assign CAN_FIRE_RL_propDstData_1_1_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstData_1_1_canon = 1'd1 ;
// rule RL_propDstData_1_2_canon
assign CAN_FIRE_RL_propDstData_1_2_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstData_1_2_canon = 1'd1 ;
// rule RL_enqDst_1_0_canon
assign CAN_FIRE_RL_enqDst_1_0_canon = 1'd1 ;
assign WILL_FIRE_RL_enqDst_1_0_canon = 1'd1 ;
// inputs to muxes for submodule ports
assign MUX_rg_state$write_1__SEL_3 =
f_reset_rsps$FULL_N && rg_state == 2'd1 ;
// inlined wires
assign propDstIdx_0_lat_1$whas =
NOT_enqDst_0_dummy2_0_read__29_30_OR_NOT_enqDs_ETC___d253 &&
x__h45600 == 2'd0 ;
assign propDstIdx_1_lat_1$whas =
NOT_enqDst_0_dummy2_0_read__29_30_OR_NOT_enqDs_ETC___d253 &&
x__h45600 == 2'd1 ;
assign propDstIdx_2_lat_1$whas =
NOT_enqDst_0_dummy2_0_read__29_30_OR_NOT_enqDs_ETC___d253 &&
x__h45600 == 2'd2 ;
assign propDstData_0_lat_0$wget =
{ i_mmu_cache$l1_to_l2_client_request_first, 5'h08 } ;
assign propDstData_1_lat_0$wget =
{ d_mmu_cache$l1_to_l2_client_request_first, 5'h09 } ;
assign propDstData_2_lat_0$wget =
{ dma_cache$l1_to_l2_client_request_first, 5'h0A } ;
assign enqDst_0_lat_0$wget =
{ 1'd1,
CASE_x5600_0_n__read_addr5824_1_n__read_addr59_ETC__q4,
SEL_ARR_IF_propDstData_0_dummy2_1_read__54_THE_ETC___d346 } ;
assign propDstIdx_1_0_lat_1$whas =
NOT_enqDst_1_0_dummy2_0_read__62_63_OR_NOT_enq_ETC___d486 &&
x__h71624 == 2'd0 ;
assign propDstIdx_1_1_lat_1$whas =
NOT_enqDst_1_0_dummy2_0_read__62_63_OR_NOT_enq_ETC___d486 &&
x__h71624 == 2'd1 ;
assign propDstIdx_1_2_lat_1$whas =
NOT_enqDst_1_0_dummy2_0_read__62_63_OR_NOT_enq_ETC___d486 &&
x__h71624 == 2'd2 ;
assign propDstData_1_0_lat_0$wget =
{ i_mmu_cache$l2_to_l1_server_response_first, 2'd0 } ;
assign propDstData_1_1_lat_0$wget =
{ d_mmu_cache$l2_to_l1_server_response_first, 2'd1 } ;
assign propDstData_1_2_lat_0$wget =
{ dma_cache$l2_to_l1_server_response_first, 2'd2 } ;
assign enqDst_1_0_lat_0$wget =
{ 1'd1,
CASE_x1624_0_n__read_addr1844_1_n__read_addr19_ETC__q15,
SEL_ARR_IF_propDstData_1_0_dummy2_1_read__87_T_ETC___d642 } ;
assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write =
llc_axi4_adapter_master_xactor_crg_wr_addr_full &&
mem_master_awready ;
assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read =
!llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write &&
llc_axi4_adapter_master_xactor_crg_wr_addr_full ;
assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ||
llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read ;
assign llc_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write =
llc_axi4_adapter_master_xactor_crg_wr_data_full &&
mem_master_wready ;
assign llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read =
!llc_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write &&
llc_axi4_adapter_master_xactor_crg_wr_data_full ;
assign llc_axi4_adapter_master_xactor_crg_wr_data_full$port3__read =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ||
llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read ;
assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read =
!CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_crg_wr_resp_full ;
assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write =
mem_master_bvalid &&
!llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read =
llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write ||
llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write =
llc_axi4_adapter_master_xactor_crg_rd_addr_full &&
mem_master_arready ;
assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read =
!llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write &&
llc_axi4_adapter_master_xactor_crg_rd_addr_full ;
assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ||
llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read ;
assign llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read =
!CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_crg_rd_data_full ;
assign llc_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write =
mem_master_rvalid &&
!llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;
assign llc_axi4_adapter_master_xactor_crg_rd_data_full$port3__read =
llc_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write ||
llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;
assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 =
llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ;
assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 =
b__h13463 - 4'd1 ;
assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read =
CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ?
llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 :
b__h13463 ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = 4'h0 ;
assign cfg_verbosity$EN = 1'b0 ;
// register enqDst_0_rl
assign enqDst_0_rl$D_IN =
CAN_FIRE_RL_doEnq ?
75'h2AAAAAAAAAAAAAAAAAA :
(NOT_enqDst_0_dummy2_0_read__29_30_OR_NOT_enqDs_ETC___d253 ?
enqDst_0_lat_0$wget :
enqDst_0_rl) ;
assign enqDst_0_rl$EN = 1'd1 ;
// register enqDst_1_0_rl
assign enqDst_1_0_rl$D_IN =
CAN_FIRE_RL_doEnq_1 ?
582'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
(NOT_enqDst_1_0_dummy2_0_read__62_63_OR_NOT_enq_ETC___d486 ?
enqDst_1_0_lat_0$wget :
enqDst_1_0_rl) ;
assign enqDst_1_0_rl$EN = 1'd1 ;
// register llc_axi4_adapter_ctr_wr_rsps_pending_crg
assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN =
llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ;
assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ;
// register llc_axi4_adapter_master_xactor_crg_rd_addr_full
assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN =
llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read ;
assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN = 1'b1 ;
// register llc_axi4_adapter_master_xactor_crg_rd_data_full
assign llc_axi4_adapter_master_xactor_crg_rd_data_full$D_IN =
llc_axi4_adapter_master_xactor_crg_rd_data_full$port3__read ;
assign llc_axi4_adapter_master_xactor_crg_rd_data_full$EN = 1'b1 ;
// register llc_axi4_adapter_master_xactor_crg_wr_addr_full
assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN =
llc_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read ;
assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN = 1'b1 ;
// register llc_axi4_adapter_master_xactor_crg_wr_data_full
assign llc_axi4_adapter_master_xactor_crg_wr_data_full$D_IN =
llc_axi4_adapter_master_xactor_crg_wr_data_full$port3__read ;
assign llc_axi4_adapter_master_xactor_crg_wr_data_full$EN = 1'b1 ;
// register llc_axi4_adapter_master_xactor_crg_wr_resp_full
assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN =
llc_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read ;
assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN = 1'b1 ;
// register llc_axi4_adapter_master_xactor_rg_rd_addr
assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN =
{ 16'd0, mem_req_rd_addr_araddr__h13577, 29'd851968 } ;
assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ;
// register llc_axi4_adapter_master_xactor_rg_rd_data
assign llc_axi4_adapter_master_xactor_rg_rd_data$D_IN =
{ mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast } ;
assign llc_axi4_adapter_master_xactor_rg_rd_data$EN = 1'd1 ;
// register llc_axi4_adapter_master_xactor_rg_wr_addr
assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN =
{ 16'd0, mem_req_wr_addr_awaddr__h15613, 29'd851968 } ;
assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;
// register llc_axi4_adapter_master_xactor_rg_wr_data
assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN =
{ data64__h15525, strb8__h15526, 1'd1 } ;
assign llc_axi4_adapter_master_xactor_rg_wr_data$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;
// register llc_axi4_adapter_master_xactor_rg_wr_resp
assign llc_axi4_adapter_master_xactor_rg_wr_resp$D_IN =
{ mem_master_bid, mem_master_bresp } ;
assign llc_axi4_adapter_master_xactor_rg_wr_resp$EN =
mem_master_bvalid &&
!llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
// register llc_axi4_adapter_rg_AXI4_error
assign llc_axi4_adapter_rg_AXI4_error$D_IN = 1'd1 ;
assign llc_axi4_adapter_rg_AXI4_error$EN =
WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 ;
// register llc_axi4_adapter_rg_cline
assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h14098 ;
assign llc_axi4_adapter_rg_cline$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ;
// register llc_axi4_adapter_rg_ddr4_ready
assign llc_axi4_adapter_rg_ddr4_ready$D_IN = 1'd1 ;
assign llc_axi4_adapter_rg_ddr4_ready$EN = EN_ma_ddr4_ready ;
// register llc_axi4_adapter_rg_rd_req_beat
assign llc_axi4_adapter_rg_rd_req_beat$D_IN =
llc_axi4_adapter_rg_rd_req_beat + 3'd1 ;
assign llc_axi4_adapter_rg_rd_req_beat$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ;
// register llc_axi4_adapter_rg_rd_rsp_beat
assign llc_axi4_adapter_rg_rd_rsp_beat$D_IN =
llc_axi4_adapter_rg_rd_rsp_beat + 3'd1 ;
assign llc_axi4_adapter_rg_rd_rsp_beat$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ;
// register llc_axi4_adapter_rg_wr_req_beat
assign llc_axi4_adapter_rg_wr_req_beat$D_IN =
llc_axi4_adapter_rg_wr_req_beat + 3'd1 ;
assign llc_axi4_adapter_rg_wr_req_beat$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;
// register llc_axi4_adapter_rg_wr_rsp_beat
assign llc_axi4_adapter_rg_wr_rsp_beat$D_IN =
llc_axi4_adapter_rg_wr_rsp_beat + 3'd1 ;
assign llc_axi4_adapter_rg_wr_rsp_beat$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ;
// register propDstData_0_rl
assign propDstData_0_rl$D_IN =
CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget :
propDstData_0_rl ;
assign propDstData_0_rl$EN = 1'd1 ;
// register propDstData_1_0_rl
assign propDstData_1_0_rl$D_IN =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_0_lat_0$wget :
propDstData_1_0_rl ;
assign propDstData_1_0_rl$EN = 1'd1 ;
// register propDstData_1_1_rl
assign propDstData_1_1_rl$D_IN =
CAN_FIRE_RL_srcPropose_4 ?
propDstData_1_1_lat_0$wget :
propDstData_1_1_rl ;
assign propDstData_1_1_rl$EN = 1'd1 ;
// register propDstData_1_2_rl
assign propDstData_1_2_rl$D_IN =
CAN_FIRE_RL_srcPropose_5 ?
propDstData_1_2_lat_0$wget :
propDstData_1_2_rl ;
assign propDstData_1_2_rl$EN = 1'd1 ;
// register propDstData_1_rl
assign propDstData_1_rl$D_IN =
CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget :
propDstData_1_rl ;
assign propDstData_1_rl$EN = 1'd1 ;
// register propDstData_2_rl
assign propDstData_2_rl$D_IN =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_2_lat_0$wget :
propDstData_2_rl ;
assign propDstData_2_rl$EN = 1'd1 ;
// register propDstIdx_0_rl
assign propDstIdx_0_rl$D_IN =
!propDstIdx_0_lat_1$whas &&
IF_propDstIdx_0_lat_0_whas__43_THEN_propDstIdx_ETC___d146 ;
assign propDstIdx_0_rl$EN = 1'd1 ;
// register propDstIdx_1_0_rl
assign propDstIdx_1_0_rl$D_IN =
!propDstIdx_1_0_lat_1$whas &&
IF_propDstIdx_1_0_lat_0_whas__76_THEN_propDstI_ETC___d379 ;
assign propDstIdx_1_0_rl$EN = 1'd1 ;
// register propDstIdx_1_1_rl
assign propDstIdx_1_1_rl$D_IN =
!propDstIdx_1_1_lat_1$whas &&
IF_propDstIdx_1_1_lat_0_whas__83_THEN_propDstI_ETC___d386 ;
assign propDstIdx_1_1_rl$EN = 1'd1 ;
// register propDstIdx_1_2_rl
assign propDstIdx_1_2_rl$D_IN =
!propDstIdx_1_2_lat_1$whas &&
IF_propDstIdx_1_2_lat_0_whas__90_THEN_propDstI_ETC___d393 ;
assign propDstIdx_1_2_rl$EN = 1'd1 ;
// register propDstIdx_1_rl
assign propDstIdx_1_rl$D_IN =
!propDstIdx_1_lat_1$whas &&
IF_propDstIdx_1_lat_0_whas__50_THEN_propDstIdx_ETC___d153 ;
assign propDstIdx_1_rl$EN = 1'd1 ;
// register propDstIdx_2_rl
assign propDstIdx_2_rl$D_IN =
!propDstIdx_2_lat_1$whas &&
IF_propDstIdx_2_lat_0_whas__57_THEN_propDstIdx_ETC___d160 ;
assign propDstIdx_2_rl$EN = 1'd1 ;
// register rg_state
always@(EN_server_reset_request_put or
WILL_FIRE_RL_rl_reset or WILL_FIRE_RL_rl_reset_complete)
begin
case (1'b1) // synopsys parallel_case
EN_server_reset_request_put: rg_state$D_IN = 2'd0;
WILL_FIRE_RL_rl_reset: rg_state$D_IN = 2'd1;
WILL_FIRE_RL_rl_reset_complete: rg_state$D_IN = 2'd2;
default: rg_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign rg_state$EN =
EN_server_reset_request_put || WILL_FIRE_RL_rl_reset ||
WILL_FIRE_RL_rl_reset_complete ;
// register srcRR_0
assign srcRR_0$D_IN = (srcRR_0 == 2'd2) ? 2'd0 : srcRR_0 + 2'd1 ;
assign srcRR_0$EN =
NOT_enqDst_0_dummy2_0_read__29_30_OR_NOT_enqDs_ETC___d253 ;
// register srcRR_1_0
assign srcRR_1_0$D_IN = (srcRR_1_0 == 2'd2) ? 2'd0 : srcRR_1_0 + 2'd1 ;
assign srcRR_1_0$EN =
NOT_enqDst_1_0_dummy2_0_read__62_63_OR_NOT_enq_ETC___d486 ;
// submodule d_mmu_cache
assign d_mmu_cache$flush_server_request_put = 1'b0 ;
assign d_mmu_cache$imem_pte_writeback_p_put =
i_mmu_cache$pte_writeback_g_get ;
assign d_mmu_cache$imem_ptw_server_request_put =
i_mmu_cache$ptw_client_request_get ;
assign d_mmu_cache$l1_to_l2_client_response_enq_x =
{ llc$to_child_toC_first[583:518],
llc$to_child_toC_first[515:3] } ;
assign d_mmu_cache$l2_to_l1_server_request_enq_x =
llc$to_child_toC_first[67:2] ;
assign d_mmu_cache$ma_req_amo_funct7 = dmem_req_amo_funct7 ;
assign d_mmu_cache$ma_req_f3 = dmem_req_f3 ;
assign d_mmu_cache$ma_req_mstatus_MXR = dmem_req_mstatus_MXR ;
assign d_mmu_cache$ma_req_op = dmem_req_op ;
assign d_mmu_cache$ma_req_priv = dmem_req_priv ;
assign d_mmu_cache$ma_req_satp = dmem_req_satp ;
assign d_mmu_cache$ma_req_sstatus_SUM = dmem_req_sstatus_SUM ;
assign d_mmu_cache$ma_req_st_value = dmem_req_store_value ;
assign d_mmu_cache$ma_req_va = dmem_req_addr ;
assign d_mmu_cache$mmio_client_response_put =
mmio_axi4_adapter$v_mmio_server_1_response_get ;
assign d_mmu_cache$set_watch_tohost_tohost_addr =
set_watch_tohost_tohost_addr ;
assign d_mmu_cache$set_watch_tohost_watch_tohost =
set_watch_tohost_watch_tohost ;
assign d_mmu_cache$EN_ma_req = EN_dmem_req ;
assign d_mmu_cache$EN_flush_server_request_put = 1'b0 ;
assign d_mmu_cache$EN_flush_server_response_get = 1'b0 ;
assign d_mmu_cache$EN_tlb_flush = EN_sfence_vma_server_request_put ;
assign d_mmu_cache$EN_imem_ptw_server_request_put =
CAN_FIRE_RL_ClientServerRequest ;
assign d_mmu_cache$EN_imem_ptw_server_response_get =
CAN_FIRE_RL_ClientServerResponse ;
assign d_mmu_cache$EN_imem_pte_writeback_p_put =
CAN_FIRE_RL_mkConnectionGetPut_3 ;
assign d_mmu_cache$EN_l1_to_l2_client_request_deq =
CAN_FIRE_RL_srcPropose_1 ;
assign d_mmu_cache$EN_l1_to_l2_client_response_enq = CAN_FIRE_RL_sendPRs_1 ;
assign d_mmu_cache$EN_l2_to_l1_server_request_enq = CAN_FIRE_RL_sendPRq_1 ;
assign d_mmu_cache$EN_l2_to_l1_server_response_deq =
CAN_FIRE_RL_srcPropose_4 ;
assign d_mmu_cache$EN_mmio_client_request_get =
CAN_FIRE_RL_ClientServerRequest_2 ;
assign d_mmu_cache$EN_mmio_client_response_put =
CAN_FIRE_RL_ClientServerResponse_2 ;
assign d_mmu_cache$EN_set_watch_tohost = EN_set_watch_tohost ;
// submodule dma_cache
assign dma_cache$axi4_s_araddr = dma_server_araddr ;
assign dma_cache$axi4_s_arburst = dma_server_arburst ;
assign dma_cache$axi4_s_arcache = dma_server_arcache ;
assign dma_cache$axi4_s_arid = dma_server_arid ;
assign dma_cache$axi4_s_arlen = dma_server_arlen ;
assign dma_cache$axi4_s_arlock = dma_server_arlock ;
assign dma_cache$axi4_s_arprot = dma_server_arprot ;
assign dma_cache$axi4_s_arqos = dma_server_arqos ;
assign dma_cache$axi4_s_arregion = dma_server_arregion ;
assign dma_cache$axi4_s_arsize = dma_server_arsize ;
assign dma_cache$axi4_s_arvalid = dma_server_arvalid ;
assign dma_cache$axi4_s_awaddr = dma_server_awaddr ;
assign dma_cache$axi4_s_awburst = dma_server_awburst ;
assign dma_cache$axi4_s_awcache = dma_server_awcache ;
assign dma_cache$axi4_s_awid = dma_server_awid ;
assign dma_cache$axi4_s_awlen = dma_server_awlen ;
assign dma_cache$axi4_s_awlock = dma_server_awlock ;
assign dma_cache$axi4_s_awprot = dma_server_awprot ;
assign dma_cache$axi4_s_awqos = dma_server_awqos ;
assign dma_cache$axi4_s_awregion = dma_server_awregion ;
assign dma_cache$axi4_s_awsize = dma_server_awsize ;
assign dma_cache$axi4_s_awvalid = dma_server_awvalid ;
assign dma_cache$axi4_s_bready = dma_server_bready ;
assign dma_cache$axi4_s_rready = dma_server_rready ;
assign dma_cache$axi4_s_wdata = dma_server_wdata ;
assign dma_cache$axi4_s_wlast = dma_server_wlast ;
assign dma_cache$axi4_s_wstrb = dma_server_wstrb ;
assign dma_cache$axi4_s_wvalid = dma_server_wvalid ;
assign dma_cache$l1_to_l2_client_response_enq_x =
d_mmu_cache$l1_to_l2_client_response_enq_x ;
assign dma_cache$l2_to_l1_server_request_enq_x =
llc$to_child_toC_first[67:2] ;
assign dma_cache$mmio_client_response_put =
mmio_axi4_adapter$v_mmio_server_2_response_get ;
assign dma_cache$EN_l1_to_l2_client_request_deq = CAN_FIRE_RL_srcPropose_2 ;
assign dma_cache$EN_l1_to_l2_client_response_enq = CAN_FIRE_RL_sendPRs_2 ;
assign dma_cache$EN_l2_to_l1_server_request_enq = CAN_FIRE_RL_sendPRq_2 ;
assign dma_cache$EN_l2_to_l1_server_response_deq =
CAN_FIRE_RL_srcPropose_5 ;
assign dma_cache$EN_mmio_client_request_get =
CAN_FIRE_RL_ClientServerRequest_3 ;
assign dma_cache$EN_mmio_client_response_put =
CAN_FIRE_RL_ClientServerResponse_3 ;
// submodule enqDst_0_dummy2_0
assign enqDst_0_dummy2_0$D_IN = 1'd1 ;
assign enqDst_0_dummy2_0$EN =
NOT_enqDst_0_dummy2_0_read__29_30_OR_NOT_enqDs_ETC___d253 ;
// submodule enqDst_0_dummy2_1
assign enqDst_0_dummy2_1$D_IN = 1'd1 ;
assign enqDst_0_dummy2_1$EN = CAN_FIRE_RL_doEnq ;
// submodule enqDst_1_0_dummy2_0
assign enqDst_1_0_dummy2_0$D_IN = 1'd1 ;
assign enqDst_1_0_dummy2_0$EN =
NOT_enqDst_1_0_dummy2_0_read__62_63_OR_NOT_enq_ETC___d486 ;
// submodule enqDst_1_0_dummy2_1
assign enqDst_1_0_dummy2_1$D_IN = 1'd1 ;
assign enqDst_1_0_dummy2_1$EN = CAN_FIRE_RL_doEnq_1 ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_3 ;
assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule i_mmu_cache
assign i_mmu_cache$flush_server_request_put = 1'b0 ;
assign i_mmu_cache$l1_to_l2_client_response_enq_x =
d_mmu_cache$l1_to_l2_client_response_enq_x ;
assign i_mmu_cache$l2_to_l1_server_request_enq_x =
llc$to_child_toC_first[67:2] ;
assign i_mmu_cache$ma_req_mstatus_MXR = imem_req_mstatus_MXR ;
assign i_mmu_cache$ma_req_priv = imem_req_priv ;
assign i_mmu_cache$ma_req_satp = imem_req_satp ;
assign i_mmu_cache$ma_req_sstatus_SUM = imem_req_sstatus_SUM ;
assign i_mmu_cache$ma_req_va = imem_req_addr ;
assign i_mmu_cache$mmio_client_response_put =
mmio_axi4_adapter$v_mmio_server_0_response_get ;
assign i_mmu_cache$ptw_client_response_put =
d_mmu_cache$imem_ptw_server_response_get ;
assign i_mmu_cache$EN_ma_req = EN_imem_req ;
assign i_mmu_cache$EN_flush_server_request_put = 1'b0 ;
assign i_mmu_cache$EN_flush_server_response_get = 1'b0 ;
assign i_mmu_cache$EN_tlb_flush = EN_sfence_vma_server_request_put ;
assign i_mmu_cache$EN_ptw_client_request_get =
CAN_FIRE_RL_ClientServerRequest ;
assign i_mmu_cache$EN_ptw_client_response_put =
CAN_FIRE_RL_ClientServerResponse ;
assign i_mmu_cache$EN_pte_writeback_g_get =
CAN_FIRE_RL_mkConnectionGetPut_3 ;
assign i_mmu_cache$EN_l1_to_l2_client_request_deq = CAN_FIRE_RL_srcPropose ;
assign i_mmu_cache$EN_l1_to_l2_client_response_enq = CAN_FIRE_RL_sendPRs ;
assign i_mmu_cache$EN_l2_to_l1_server_request_enq = CAN_FIRE_RL_sendPRq ;
assign i_mmu_cache$EN_l2_to_l1_server_response_deq =
CAN_FIRE_RL_srcPropose_3 ;
assign i_mmu_cache$EN_mmio_client_request_get =
CAN_FIRE_RL_ClientServerRequest_1 ;
assign i_mmu_cache$EN_mmio_client_response_put =
CAN_FIRE_RL_ClientServerResponse_1 ;
// submodule llc
assign llc$dma_memReq_enq_x = 656'h0 ;
assign llc$perf_req_r = 4'h0 ;
assign llc$perf_setStatus_doStats = 1'b0 ;
assign llc$to_child_rqFromC_enq_x =
NOT_enqDst_0_dummy2_0_read__29_30_OR_NOT_enqDs_ETC___d253 ?
enqDst_0_lat_0$wget[73:0] :
enqDst_0_rl[73:0] ;
assign llc$to_child_rsFromC_enq_x =
NOT_enqDst_1_0_dummy2_0_read__62_63_OR_NOT_enq_ETC___d486 ?
enqDst_1_0_lat_0$wget[580:0] :
enqDst_1_0_rl[580:0] ;
assign llc$to_mem_rsFromM_enq_x =
{ new_cline__h14098,
llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ;
assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ;
assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ;
assign llc$EN_to_child_toC_deq =
WILL_FIRE_RL_sendPRs_2 || WILL_FIRE_RL_sendPRq_2 ||
WILL_FIRE_RL_sendPRs_1 ||
WILL_FIRE_RL_sendPRq_1 ||
WILL_FIRE_RL_sendPRs ||
WILL_FIRE_RL_sendPRq ;
assign llc$EN_dma_memReq_enq = 1'b0 ;
assign llc$EN_dma_respLd_deq = llc$RDY_dma_respLd_deq ;
assign llc$EN_dma_respSt_deq = llc$RDY_dma_respSt_deq ;
assign llc$EN_to_mem_toM_deq =
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_rg_rd_req_beat == 3'd7 ||
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_rg_wr_req_beat == 3'd7 ;
assign llc$EN_to_mem_rsFromM_enq =
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ;
assign llc$EN_cRqStuck_get = 1'b0 ;
assign llc$EN_perf_setStatus = 1'b0 ;
assign llc$EN_perf_req = 1'b0 ;
assign llc$EN_perf_resp = 1'b0 ;
// submodule llc_axi4_adapter_f_pending_reads
assign llc_axi4_adapter_f_pending_reads$D_IN = llc$to_mem_toM_first[68:0] ;
assign llc_axi4_adapter_f_pending_reads$ENQ =
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0 ;
assign llc_axi4_adapter_f_pending_reads$DEQ =
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ;
assign llc_axi4_adapter_f_pending_reads$CLR = 1'b0 ;
// submodule llc_axi4_adapter_f_pending_writes
assign llc_axi4_adapter_f_pending_writes$D_IN =
llc$to_mem_toM_first[639:0] ;
assign llc_axi4_adapter_f_pending_writes$ENQ =
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 ;
assign llc_axi4_adapter_f_pending_writes$DEQ =
WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_rg_wr_rsp_beat == 3'd7 ;
assign llc_axi4_adapter_f_pending_writes$CLR = 1'b0 ;
// submodule mmio_axi4_adapter
assign mmio_axi4_adapter$mem_master_arready = imem_master_arready ;
assign mmio_axi4_adapter$mem_master_awready = imem_master_awready ;
assign mmio_axi4_adapter$mem_master_bid = imem_master_bid ;
assign mmio_axi4_adapter$mem_master_bresp = imem_master_bresp ;
assign mmio_axi4_adapter$mem_master_bvalid = imem_master_bvalid ;
assign mmio_axi4_adapter$mem_master_rdata = imem_master_rdata ;
assign mmio_axi4_adapter$mem_master_rid = imem_master_rid ;
assign mmio_axi4_adapter$mem_master_rlast = imem_master_rlast ;
assign mmio_axi4_adapter$mem_master_rresp = imem_master_rresp ;
assign mmio_axi4_adapter$mem_master_rvalid = imem_master_rvalid ;
assign mmio_axi4_adapter$mem_master_wready = imem_master_wready ;
assign mmio_axi4_adapter$v_mmio_server_0_request_put =
i_mmu_cache$mmio_client_request_get ;
assign mmio_axi4_adapter$v_mmio_server_1_request_put =
d_mmu_cache$mmio_client_request_get ;
assign mmio_axi4_adapter$v_mmio_server_2_request_put =
dma_cache$mmio_client_request_get ;
assign mmio_axi4_adapter$EN_v_mmio_server_0_request_put =
CAN_FIRE_RL_ClientServerRequest_1 ;
assign mmio_axi4_adapter$EN_v_mmio_server_0_response_get =
CAN_FIRE_RL_ClientServerResponse_1 ;
assign mmio_axi4_adapter$EN_v_mmio_server_1_request_put =
CAN_FIRE_RL_ClientServerRequest_2 ;
assign mmio_axi4_adapter$EN_v_mmio_server_1_response_get =
CAN_FIRE_RL_ClientServerResponse_2 ;
assign mmio_axi4_adapter$EN_v_mmio_server_2_request_put =
CAN_FIRE_RL_ClientServerRequest_3 ;
assign mmio_axi4_adapter$EN_v_mmio_server_2_response_get =
CAN_FIRE_RL_ClientServerResponse_3 ;
// submodule propDstData_0_dummy2_0
assign propDstData_0_dummy2_0$D_IN = 1'd1 ;
assign propDstData_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose ;
// submodule propDstData_0_dummy2_1
assign propDstData_0_dummy2_1$D_IN = 1'b0 ;
assign propDstData_0_dummy2_1$EN = 1'b0 ;
// submodule propDstData_1_0_dummy2_0
assign propDstData_1_0_dummy2_0$D_IN = 1'd1 ;
assign propDstData_1_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose_3 ;
// submodule propDstData_1_0_dummy2_1
assign propDstData_1_0_dummy2_1$D_IN = 1'b0 ;
assign propDstData_1_0_dummy2_1$EN = 1'b0 ;
// submodule propDstData_1_1_dummy2_0
assign propDstData_1_1_dummy2_0$D_IN = 1'd1 ;
assign propDstData_1_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_4 ;
// submodule propDstData_1_1_dummy2_1
assign propDstData_1_1_dummy2_1$D_IN = 1'b0 ;
assign propDstData_1_1_dummy2_1$EN = 1'b0 ;
// submodule propDstData_1_2_dummy2_0
assign propDstData_1_2_dummy2_0$D_IN = 1'd1 ;
assign propDstData_1_2_dummy2_0$EN = CAN_FIRE_RL_srcPropose_5 ;
// submodule propDstData_1_2_dummy2_1
assign propDstData_1_2_dummy2_1$D_IN = 1'b0 ;
assign propDstData_1_2_dummy2_1$EN = 1'b0 ;
// submodule propDstData_1_dummy2_0
assign propDstData_1_dummy2_0$D_IN = 1'd1 ;
assign propDstData_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_1 ;
// submodule propDstData_1_dummy2_1
assign propDstData_1_dummy2_1$D_IN = 1'b0 ;
assign propDstData_1_dummy2_1$EN = 1'b0 ;
// submodule propDstData_2_dummy2_0
assign propDstData_2_dummy2_0$D_IN = 1'd1 ;
assign propDstData_2_dummy2_0$EN = CAN_FIRE_RL_srcPropose_2 ;
// submodule propDstData_2_dummy2_1
assign propDstData_2_dummy2_1$D_IN = 1'b0 ;
assign propDstData_2_dummy2_1$EN = 1'b0 ;
// submodule propDstIdx_0_dummy2_0
assign propDstIdx_0_dummy2_0$D_IN = 1'd1 ;
assign propDstIdx_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose ;
// submodule propDstIdx_0_dummy2_1
assign propDstIdx_0_dummy2_1$D_IN = 1'd1 ;
assign propDstIdx_0_dummy2_1$EN = propDstIdx_0_lat_1$whas ;
// submodule propDstIdx_1_0_dummy2_0
assign propDstIdx_1_0_dummy2_0$D_IN = 1'd1 ;
assign propDstIdx_1_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose_3 ;
// submodule propDstIdx_1_0_dummy2_1
assign propDstIdx_1_0_dummy2_1$D_IN = 1'd1 ;
assign propDstIdx_1_0_dummy2_1$EN = propDstIdx_1_0_lat_1$whas ;
// submodule propDstIdx_1_1_dummy2_0
assign propDstIdx_1_1_dummy2_0$D_IN = 1'd1 ;
assign propDstIdx_1_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_4 ;
// submodule propDstIdx_1_1_dummy2_1
assign propDstIdx_1_1_dummy2_1$D_IN = 1'd1 ;
assign propDstIdx_1_1_dummy2_1$EN = propDstIdx_1_1_lat_1$whas ;
// submodule propDstIdx_1_2_dummy2_0
assign propDstIdx_1_2_dummy2_0$D_IN = 1'd1 ;
assign propDstIdx_1_2_dummy2_0$EN = CAN_FIRE_RL_srcPropose_5 ;
// submodule propDstIdx_1_2_dummy2_1
assign propDstIdx_1_2_dummy2_1$D_IN = 1'd1 ;
assign propDstIdx_1_2_dummy2_1$EN = propDstIdx_1_2_lat_1$whas ;
// submodule propDstIdx_1_dummy2_0
assign propDstIdx_1_dummy2_0$D_IN = 1'd1 ;
assign propDstIdx_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_1 ;
// submodule propDstIdx_1_dummy2_1
assign propDstIdx_1_dummy2_1$D_IN = 1'd1 ;
assign propDstIdx_1_dummy2_1$EN = propDstIdx_1_lat_1$whas ;
// submodule propDstIdx_2_dummy2_0
assign propDstIdx_2_dummy2_0$D_IN = 1'd1 ;
assign propDstIdx_2_dummy2_0$EN = CAN_FIRE_RL_srcPropose_2 ;
// submodule propDstIdx_2_dummy2_1
assign propDstIdx_2_dummy2_1$D_IN = 1'd1 ;
assign propDstIdx_2_dummy2_1$EN = propDstIdx_2_lat_1$whas ;
// remaining internal signals
assign IF_NOT_propDstIdx_0_dummy2_1_read__95_96_OR_IF_ETC___d250 =
NOT_propDstIdx_0_dummy2_1_read__95_96_OR_IF_pr_ETC___d245 ?
propDstIdx_1_dummy2_1$Q_OUT &&
IF_propDstIdx_1_lat_0_whas__50_THEN_propDstIdx_ETC___d153 :
propDstIdx_0_dummy2_1$Q_OUT &&
IF_propDstIdx_0_lat_0_whas__43_THEN_propDstIdx_ETC___d146 ;
assign IF_NOT_propDstIdx_0_dummy2_1_read__95_96_OR_IF_ETC___d251 =
(NOT_propDstIdx_0_dummy2_1_read__95_96_OR_IF_pr_ETC___d245 &&
NOT_propDstIdx_1_dummy2_1_read__08_09_OR_IF_pr_ETC___d248) ?
propDstIdx_2_dummy2_1$Q_OUT &&
IF_propDstIdx_2_lat_0_whas__57_THEN_propDstIdx_ETC___d160 :
IF_NOT_propDstIdx_0_dummy2_1_read__95_96_OR_IF_ETC___d250 ;
assign IF_NOT_propDstIdx_1_0_dummy2_1_read__28_29_OR__ETC___d483 =
NOT_propDstIdx_1_0_dummy2_1_read__28_29_OR_IF__ETC___d478 ?
propDstIdx_1_1_dummy2_1$Q_OUT &&
IF_propDstIdx_1_1_lat_0_whas__83_THEN_propDstI_ETC___d386 :
propDstIdx_1_0_dummy2_1$Q_OUT &&
IF_propDstIdx_1_0_lat_0_whas__76_THEN_propDstI_ETC___d379 ;
assign IF_NOT_propDstIdx_1_0_dummy2_1_read__28_29_OR__ETC___d484 =
(NOT_propDstIdx_1_0_dummy2_1_read__28_29_OR_IF__ETC___d478 &&
NOT_propDstIdx_1_1_dummy2_1_read__41_42_OR_IF__ETC___d481) ?
propDstIdx_1_2_dummy2_1$Q_OUT &&
IF_propDstIdx_1_2_lat_0_whas__90_THEN_propDstI_ETC___d393 :
IF_NOT_propDstIdx_1_0_dummy2_1_read__28_29_OR__ETC___d483 ;
assign IF_propDstData_0_dummy2_1_read__54_THEN_IF_pro_ETC___d278 =
propDstData_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[9:8] :
propDstData_0_rl[9:8]) :
2'd0 ;
assign IF_propDstData_0_dummy2_1_read__54_THEN_IF_pro_ETC___d292 =
propDstData_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[7:6] :
propDstData_0_rl[7:6]) :
2'd0 ;
assign IF_propDstData_1_0_dummy2_1_read__87_THEN_IF_p_ETC___d511 =
propDstData_1_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_0_lat_0$wget[516:515] :
propDstData_1_0_rl[516:515]) :
2'd0 ;
assign IF_propDstData_1_1_dummy2_1_read__92_THEN_IF_p_ETC___d515 =
propDstData_1_1_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_4 ?
propDstData_1_1_lat_0$wget[516:515] :
propDstData_1_1_rl[516:515]) :
2'd0 ;
assign IF_propDstData_1_2_dummy2_1_read__97_THEN_IF_p_ETC___d519 =
propDstData_1_2_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_5 ?
propDstData_1_2_lat_0$wget[516:515] :
propDstData_1_2_rl[516:515]) :
2'd0 ;
assign IF_propDstData_1_dummy2_1_read__59_THEN_IF_pro_ETC___d282 =
propDstData_1_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[9:8] :
propDstData_1_rl[9:8]) :
2'd0 ;
assign IF_propDstData_1_dummy2_1_read__59_THEN_IF_pro_ETC___d296 =
propDstData_1_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[7:6] :
propDstData_1_rl[7:6]) :
2'd0 ;
assign IF_propDstData_2_dummy2_1_read__64_THEN_IF_pro_ETC___d286 =
propDstData_2_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_2 ?
propDstData_2_lat_0$wget[9:8] :
propDstData_2_rl[9:8]) :
2'd0 ;
assign IF_propDstData_2_dummy2_1_read__64_THEN_IF_pro_ETC___d300 =
propDstData_2_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_2 ?
propDstData_2_lat_0$wget[7:6] :
propDstData_2_rl[7:6]) :
2'd0 ;
assign IF_propDstIdx_0_lat_0_whas__43_THEN_propDstIdx_ETC___d146 =
CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ;
assign IF_propDstIdx_1_0_lat_0_whas__76_THEN_propDstI_ETC___d379 =
CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_0_rl ;
assign IF_propDstIdx_1_1_lat_0_whas__83_THEN_propDstI_ETC___d386 =
CAN_FIRE_RL_srcPropose_4 || propDstIdx_1_1_rl ;
assign IF_propDstIdx_1_2_lat_0_whas__90_THEN_propDstI_ETC___d393 =
CAN_FIRE_RL_srcPropose_5 || propDstIdx_1_2_rl ;
assign IF_propDstIdx_1_lat_0_whas__50_THEN_propDstIdx_ETC___d153 =
CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ;
assign IF_propDstIdx_2_lat_0_whas__57_THEN_propDstIdx_ETC___d160 =
CAN_FIRE_RL_srcPropose_2 || propDstIdx_2_rl ;
assign NOT_cfg_verbosity_read__38_ULE_1_39___d740 = cfg_verbosity > 4'd1 ;
assign NOT_enqDst_0_dummy2_0_read__29_30_OR_NOT_enqDs_ETC___d253 =
(!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT ||
!enqDst_0_rl[74]) &&
(SEL_ARR_propDstIdx_0_dummy2_1_read__95_AND_IF__ETC___d242 ||
IF_NOT_propDstIdx_0_dummy2_1_read__95_96_OR_IF_ETC___d251) ;
assign NOT_enqDst_1_0_dummy2_0_read__62_63_OR_NOT_enq_ETC___d486 =
(!enqDst_1_0_dummy2_0$Q_OUT || !enqDst_1_0_dummy2_1$Q_OUT ||
!enqDst_1_0_rl[581]) &&
(SEL_ARR_propDstIdx_1_0_dummy2_1_read__28_AND_I_ETC___d475 ||
IF_NOT_propDstIdx_1_0_dummy2_1_read__28_29_OR__ETC___d484) ;
assign NOT_llc_axi4_adapter_master_xactor_crg_wr_addr_ETC___d80 =
!llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read &&
!llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read &&
llc_axi4_adapter_ctr_wr_rsps_pending_crg != 4'd15 &&
llc$RDY_to_mem_toM_first &&
(llc_axi4_adapter_rg_wr_req_beat != 3'd0 ||
llc_axi4_adapter_f_pending_writes$FULL_N) &&
(llc_axi4_adapter_rg_wr_req_beat != 3'd7 ||
llc$RDY_to_mem_toM_deq) ;
assign NOT_propDstIdx_0_dummy2_1_read__95_96_OR_IF_pr_ETC___d245 =
!propDstIdx_0_dummy2_1$Q_OUT ||
!CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ;
assign NOT_propDstIdx_1_0_dummy2_1_read__28_29_OR_IF__ETC___d478 =
!propDstIdx_1_0_dummy2_1$Q_OUT ||
!CAN_FIRE_RL_srcPropose_3 && !propDstIdx_1_0_rl ;
assign NOT_propDstIdx_1_1_dummy2_1_read__41_42_OR_IF__ETC___d481 =
!propDstIdx_1_1_dummy2_1$Q_OUT ||
!CAN_FIRE_RL_srcPropose_4 && !propDstIdx_1_1_rl ;
assign NOT_propDstIdx_1_2_dummy2_1_read__54_55_OR_IF__ETC___d659 =
!propDstIdx_1_2_dummy2_1$Q_OUT ||
!CAN_FIRE_RL_srcPropose_5 && !propDstIdx_1_2_rl ;
assign NOT_propDstIdx_1_dummy2_1_read__08_09_OR_IF_pr_ETC___d248 =
!propDstIdx_1_dummy2_1$Q_OUT ||
!CAN_FIRE_RL_srcPropose_1 && !propDstIdx_1_rl ;
assign NOT_propDstIdx_2_dummy2_1_read__21_22_OR_IF_pr_ETC___d363 =
!propDstIdx_2_dummy2_1$Q_OUT ||
!CAN_FIRE_RL_srcPropose_2 && !propDstIdx_2_rl ;
assign SEL_ARR_IF_propDstData_0_dummy2_1_read__54_THE_ETC___d346 =
{ CASE_x5600_0_IF_propDstData_0_dummy2_1_read__5_ETC__q2,
CASE_x5600_0_IF_propDstData_0_dummy2_1_read__5_ETC__q3,
SEL_ARR_propDstData_0_dummy2_1_read__54_AND_IF_ETC___d345 } ;
assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__87_T_ETC___d642 =
{ CASE_x1624_0_IF_propDstData_1_0_dummy2_1_read__ETC__q14,
SEL_ARR_propDstData_1_0_dummy2_1_read__87_AND__ETC___d627,
x__h74996 } ;
assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__97_THEN_ETC___d569 =
{ CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q5,
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q6,
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q7 } ;
assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__97_THEN_ETC___d592 =
{ SEL_ARR_IF_propDstData_1_0_lat_0_whas__97_THEN_ETC___d569,
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q8,
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q9 } ;
assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__97_THEN_ETC___d615 =
{ SEL_ARR_IF_propDstData_1_0_lat_0_whas__97_THEN_ETC___d592,
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q10,
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q11 } ;
assign SEL_ARR_propDstData_0_dummy2_1_read__54_AND_IF_ETC___d345 =
{ CASE_x5600_0_propDstData_0_dummy2_1_read__54_A_ETC__q1,
x__h46058,
x__h46068 } ;
assign SEL_ARR_propDstData_1_0_dummy2_1_read__87_AND__ETC___d627 =
{ CASE_x1624_0_propDstData_1_0_dummy2_1_read__87_ETC__q12,
SEL_ARR_IF_propDstData_1_0_lat_0_whas__97_THEN_ETC___d615,
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q13 } ;
assign b__h13463 =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ?
llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 :
llc_axi4_adapter_ctr_wr_rsps_pending_crg ;
assign enqDst_0_dummy2_1_read__31_AND_IF_enqDst_0_lat_ETC___d368 =
enqDst_0_dummy2_1$Q_OUT &&
(NOT_enqDst_0_dummy2_0_read__29_30_OR_NOT_enqDs_ETC___d253 ?
enqDst_0_lat_0$wget[74] :
enqDst_0_rl[74]) ;
assign enqDst_1_0_dummy2_1_read__64_AND_IF_enqDst_1_0_ETC___d664 =
enqDst_1_0_dummy2_1$Q_OUT &&
(NOT_enqDst_1_0_dummy2_0_read__62_63_OR_NOT_enq_ETC___d486 ?
enqDst_1_0_lat_0$wget[581] :
enqDst_1_0_rl[581]) ;
assign mem_req_rd_addr_araddr__h13577 =
{ llc$to_mem_toM_first[68:11], x__h13627 } ;
assign mem_req_wr_addr_awaddr__h15613 =
{ llc$to_mem_toM_first[639:582], x__h15647 } ;
assign n__read_addr__h45824 =
propDstData_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[73:10] :
propDstData_0_rl[73:10]) :
64'd0 ;
assign n__read_addr__h45909 =
propDstData_1_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[73:10] :
propDstData_1_rl[73:10]) :
64'd0 ;
assign n__read_addr__h45994 =
propDstData_2_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_2 ?
propDstData_2_lat_0$wget[73:10] :
propDstData_2_rl[73:10]) :
64'd0 ;
assign n__read_addr__h71844 =
propDstData_1_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_0_lat_0$wget[580:517] :
propDstData_1_0_rl[580:517]) :
64'd0 ;
assign n__read_addr__h71923 =
propDstData_1_1_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_4 ?
propDstData_1_1_lat_0$wget[580:517] :
propDstData_1_1_rl[580:517]) :
64'd0 ;
assign n__read_addr__h72002 =
propDstData_1_2_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_5 ?
propDstData_1_2_lat_0$wget[580:517] :
propDstData_1_2_rl[580:517]) :
64'd0 ;
assign n__read_child__h45829 =
propDstData_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[1:0] :
propDstData_0_rl[1:0]) :
2'd0 ;
assign n__read_child__h45914 =
propDstData_1_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[1:0] :
propDstData_1_rl[1:0]) :
2'd0 ;
assign n__read_child__h45999 =
propDstData_2_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_2 ?
propDstData_2_lat_0$wget[1:0] :
propDstData_2_rl[1:0]) :
2'd0 ;
assign n__read_child__h71847 =
propDstData_1_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_0_lat_0$wget[1:0] :
propDstData_1_0_rl[1:0]) :
2'd0 ;
assign n__read_child__h71926 =
propDstData_1_1_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_4 ?
propDstData_1_1_lat_0$wget[1:0] :
propDstData_1_1_rl[1:0]) :
2'd0 ;
assign n__read_child__h72005 =
propDstData_1_2_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_5 ?
propDstData_1_2_lat_0$wget[1:0] :
propDstData_1_2_rl[1:0]) :
2'd0 ;
assign n__read_id__h45828 =
propDstData_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[4:2] :
propDstData_0_rl[4:2]) :
3'd0 ;
assign n__read_id__h45913 =
propDstData_1_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[4:2] :
propDstData_1_rl[4:2]) :
3'd0 ;
assign n__read_id__h45998 =
propDstData_2_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_2 ?
propDstData_2_lat_0$wget[4:2] :
propDstData_2_rl[4:2]) :
3'd0 ;
assign new_cline__h14098 =
{ llc_axi4_adapter_master_xactor_rg_rd_data[66:3],
llc_axi4_adapter_rg_cline[511:64] } ;
assign propDstData_0_dummy2_1_read__54_AND_IF_propDst_ETC___d306 =
propDstData_0_dummy2_1$Q_OUT &&
(CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[5] :
propDstData_0_rl[5]) ;
assign propDstData_1_0_dummy2_1_read__87_AND_IF_propD_ETC___d525 =
propDstData_1_0_dummy2_1$Q_OUT &&
(CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_0_lat_0$wget[514] :
propDstData_1_0_rl[514]) ;
assign propDstData_1_1_dummy2_1_read__92_AND_IF_propD_ETC___d529 =
propDstData_1_1_dummy2_1$Q_OUT &&
(CAN_FIRE_RL_srcPropose_4 ?
propDstData_1_1_lat_0$wget[514] :
propDstData_1_1_rl[514]) ;
assign propDstData_1_2_dummy2_1_read__97_AND_IF_propD_ETC___d533 =
propDstData_1_2_dummy2_1$Q_OUT &&
(CAN_FIRE_RL_srcPropose_5 ?
propDstData_1_2_lat_0$wget[514] :
propDstData_1_2_rl[514]) ;
assign propDstData_1_dummy2_1_read__59_AND_IF_propDst_ETC___d310 =
propDstData_1_dummy2_1$Q_OUT &&
(CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[5] :
propDstData_1_rl[5]) ;
assign propDstData_2_dummy2_1_read__64_AND_IF_propDst_ETC___d314 =
propDstData_2_dummy2_1$Q_OUT &&
(CAN_FIRE_RL_srcPropose_2 ?
propDstData_2_lat_0$wget[5] :
propDstData_2_rl[5]) ;
assign x__h13627 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ;
assign x__h15647 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ;
assign x__h45600 =
SEL_ARR_propDstIdx_0_dummy2_1_read__95_AND_IF__ETC___d242 ?
srcRR_0 :
((NOT_propDstIdx_0_dummy2_1_read__95_96_OR_IF_pr_ETC___d245 &&
NOT_propDstIdx_1_dummy2_1_read__08_09_OR_IF_pr_ETC___d248) ?
2'd2 :
(NOT_propDstIdx_0_dummy2_1_read__95_96_OR_IF_pr_ETC___d245 ?
2'd1 :
2'd0)) ;
assign x__h71624 =
SEL_ARR_propDstIdx_1_0_dummy2_1_read__28_AND_I_ETC___d475 ?
srcRR_1_0 :
((NOT_propDstIdx_1_0_dummy2_1_read__28_29_OR_IF__ETC___d478 &&
NOT_propDstIdx_1_1_dummy2_1_read__41_42_OR_IF__ETC___d481) ?
2'd2 :
(NOT_propDstIdx_1_0_dummy2_1_read__28_29_OR_IF__ETC___d478 ?
2'd1 :
2'd0)) ;
always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first)
begin
case (llc_axi4_adapter_rg_wr_req_beat)
3'd0: data64__h15525 = llc$to_mem_toM_first[63:0];
3'd1: data64__h15525 = llc$to_mem_toM_first[127:64];
3'd2: data64__h15525 = llc$to_mem_toM_first[191:128];
3'd3: data64__h15525 = llc$to_mem_toM_first[255:192];
3'd4: data64__h15525 = llc$to_mem_toM_first[319:256];
3'd5: data64__h15525 = llc$to_mem_toM_first[383:320];
3'd6: data64__h15525 = llc$to_mem_toM_first[447:384];
3'd7: data64__h15525 = llc$to_mem_toM_first[511:448];
endcase
end
always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first)
begin
case (llc_axi4_adapter_rg_wr_req_beat)
3'd0: strb8__h15526 = llc$to_mem_toM_first[519:512];
3'd1: strb8__h15526 = llc$to_mem_toM_first[527:520];
3'd2: strb8__h15526 = llc$to_mem_toM_first[535:528];
3'd3: strb8__h15526 = llc$to_mem_toM_first[543:536];
3'd4: strb8__h15526 = llc$to_mem_toM_first[551:544];
3'd5: strb8__h15526 = llc$to_mem_toM_first[559:552];
3'd6: strb8__h15526 = llc$to_mem_toM_first[567:560];
3'd7: strb8__h15526 = llc$to_mem_toM_first[575:568];
endcase
end
always@(srcRR_0 or
propDstIdx_0_dummy2_1$Q_OUT or
IF_propDstIdx_0_lat_0_whas__43_THEN_propDstIdx_ETC___d146 or
propDstIdx_1_dummy2_1$Q_OUT or
IF_propDstIdx_1_lat_0_whas__50_THEN_propDstIdx_ETC___d153 or
propDstIdx_2_dummy2_1$Q_OUT or
IF_propDstIdx_2_lat_0_whas__57_THEN_propDstIdx_ETC___d160)
begin
case (srcRR_0)
2'd0:
SEL_ARR_propDstIdx_0_dummy2_1_read__95_AND_IF__ETC___d242 =
propDstIdx_0_dummy2_1$Q_OUT &&
IF_propDstIdx_0_lat_0_whas__43_THEN_propDstIdx_ETC___d146;
2'd1:
SEL_ARR_propDstIdx_0_dummy2_1_read__95_AND_IF__ETC___d242 =
propDstIdx_1_dummy2_1$Q_OUT &&
IF_propDstIdx_1_lat_0_whas__50_THEN_propDstIdx_ETC___d153;
2'd2:
SEL_ARR_propDstIdx_0_dummy2_1_read__95_AND_IF__ETC___d242 =
propDstIdx_2_dummy2_1$Q_OUT &&
IF_propDstIdx_2_lat_0_whas__57_THEN_propDstIdx_ETC___d160;
2'd3:
SEL_ARR_propDstIdx_0_dummy2_1_read__95_AND_IF__ETC___d242 =
1'b0 /* unspecified value */ ;
endcase
end
always@(srcRR_1_0 or
propDstIdx_1_0_dummy2_1$Q_OUT or
IF_propDstIdx_1_0_lat_0_whas__76_THEN_propDstI_ETC___d379 or
propDstIdx_1_1_dummy2_1$Q_OUT or
IF_propDstIdx_1_1_lat_0_whas__83_THEN_propDstI_ETC___d386 or
propDstIdx_1_2_dummy2_1$Q_OUT or
IF_propDstIdx_1_2_lat_0_whas__90_THEN_propDstI_ETC___d393)
begin
case (srcRR_1_0)
2'd0:
SEL_ARR_propDstIdx_1_0_dummy2_1_read__28_AND_I_ETC___d475 =
propDstIdx_1_0_dummy2_1$Q_OUT &&
IF_propDstIdx_1_0_lat_0_whas__76_THEN_propDstI_ETC___d379;
2'd1:
SEL_ARR_propDstIdx_1_0_dummy2_1_read__28_AND_I_ETC___d475 =
propDstIdx_1_1_dummy2_1$Q_OUT &&
IF_propDstIdx_1_1_lat_0_whas__83_THEN_propDstI_ETC___d386;
2'd2:
SEL_ARR_propDstIdx_1_0_dummy2_1_read__28_AND_I_ETC___d475 =
propDstIdx_1_2_dummy2_1$Q_OUT &&
IF_propDstIdx_1_2_lat_0_whas__90_THEN_propDstI_ETC___d393;
2'd3:
SEL_ARR_propDstIdx_1_0_dummy2_1_read__28_AND_I_ETC___d475 =
1'b0 /* unspecified value */ ;
endcase
end
always@(x__h45600 or
n__read_id__h45828 or n__read_id__h45913 or n__read_id__h45998)
begin
case (x__h45600)
2'd0: x__h46058 = n__read_id__h45828;
2'd1: x__h46058 = n__read_id__h45913;
2'd2: x__h46058 = n__read_id__h45998;
2'd3: x__h46058 = 3'b010 /* unspecified value */ ;
endcase
end
always@(x__h45600 or
n__read_child__h45829 or
n__read_child__h45914 or n__read_child__h45999)
begin
case (x__h45600)
2'd0: x__h46068 = n__read_child__h45829;
2'd1: x__h46068 = n__read_child__h45914;
2'd2: x__h46068 = n__read_child__h45999;
2'd3: x__h46068 = 2'b10 /* unspecified value */ ;
endcase
end
always@(x__h45600 or
propDstData_0_dummy2_1_read__54_AND_IF_propDst_ETC___d306 or
propDstData_1_dummy2_1_read__59_AND_IF_propDst_ETC___d310 or
propDstData_2_dummy2_1_read__64_AND_IF_propDst_ETC___d314)
begin
case (x__h45600)
2'd0:
CASE_x5600_0_propDstData_0_dummy2_1_read__54_A_ETC__q1 =
propDstData_0_dummy2_1_read__54_AND_IF_propDst_ETC___d306;
2'd1:
CASE_x5600_0_propDstData_0_dummy2_1_read__54_A_ETC__q1 =
propDstData_1_dummy2_1_read__59_AND_IF_propDst_ETC___d310;
2'd2:
CASE_x5600_0_propDstData_0_dummy2_1_read__54_A_ETC__q1 =
propDstData_2_dummy2_1_read__64_AND_IF_propDst_ETC___d314;
2'd3:
CASE_x5600_0_propDstData_0_dummy2_1_read__54_A_ETC__q1 =
1'b0 /* unspecified value */ ;
endcase
end
always@(x__h45600 or
IF_propDstData_0_dummy2_1_read__54_THEN_IF_pro_ETC___d278 or
IF_propDstData_1_dummy2_1_read__59_THEN_IF_pro_ETC___d282 or
IF_propDstData_2_dummy2_1_read__64_THEN_IF_pro_ETC___d286)
begin
case (x__h45600)
2'd0:
CASE_x5600_0_IF_propDstData_0_dummy2_1_read__5_ETC__q2 =
IF_propDstData_0_dummy2_1_read__54_THEN_IF_pro_ETC___d278;
2'd1:
CASE_x5600_0_IF_propDstData_0_dummy2_1_read__5_ETC__q2 =
IF_propDstData_1_dummy2_1_read__59_THEN_IF_pro_ETC___d282;
2'd2:
CASE_x5600_0_IF_propDstData_0_dummy2_1_read__5_ETC__q2 =
IF_propDstData_2_dummy2_1_read__64_THEN_IF_pro_ETC___d286;
2'd3:
CASE_x5600_0_IF_propDstData_0_dummy2_1_read__5_ETC__q2 =
2'b10 /* unspecified value */ ;
endcase
end
always@(x__h45600 or
IF_propDstData_0_dummy2_1_read__54_THEN_IF_pro_ETC___d292 or
IF_propDstData_1_dummy2_1_read__59_THEN_IF_pro_ETC___d296 or
IF_propDstData_2_dummy2_1_read__64_THEN_IF_pro_ETC___d300)
begin
case (x__h45600)
2'd0:
CASE_x5600_0_IF_propDstData_0_dummy2_1_read__5_ETC__q3 =
IF_propDstData_0_dummy2_1_read__54_THEN_IF_pro_ETC___d292;
2'd1:
CASE_x5600_0_IF_propDstData_0_dummy2_1_read__5_ETC__q3 =
IF_propDstData_1_dummy2_1_read__59_THEN_IF_pro_ETC___d296;
2'd2:
CASE_x5600_0_IF_propDstData_0_dummy2_1_read__5_ETC__q3 =
IF_propDstData_2_dummy2_1_read__64_THEN_IF_pro_ETC___d300;
2'd3:
CASE_x5600_0_IF_propDstData_0_dummy2_1_read__5_ETC__q3 =
2'b10 /* unspecified value */ ;
endcase
end
always@(x__h45600 or
n__read_addr__h45824 or
n__read_addr__h45909 or n__read_addr__h45994)
begin
case (x__h45600)
2'd0:
CASE_x5600_0_n__read_addr5824_1_n__read_addr59_ETC__q4 =
n__read_addr__h45824;
2'd1:
CASE_x5600_0_n__read_addr5824_1_n__read_addr59_ETC__q4 =
n__read_addr__h45909;
2'd2:
CASE_x5600_0_n__read_addr5824_1_n__read_addr59_ETC__q4 =
n__read_addr__h45994;
2'd3:
CASE_x5600_0_n__read_addr5824_1_n__read_addr59_ETC__q4 =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(x__h71624 or
n__read_child__h71847 or
n__read_child__h71926 or n__read_child__h72005)
begin
case (x__h71624)
2'd0: x__h74996 = n__read_child__h71847;
2'd1: x__h74996 = n__read_child__h71926;
2'd2: x__h74996 = n__read_child__h72005;
2'd3: x__h74996 = 2'b10 /* unspecified value */ ;
endcase
end
always@(x__h71624 or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_4 or
propDstData_1_1_lat_0$wget or
propDstData_1_1_rl or
CAN_FIRE_RL_srcPropose_5 or
propDstData_1_2_lat_0$wget or propDstData_1_2_rl)
begin
case (x__h71624)
2'd0:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q5 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_0_lat_0$wget[513:450] :
propDstData_1_0_rl[513:450];
2'd1:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q5 =
CAN_FIRE_RL_srcPropose_4 ?
propDstData_1_1_lat_0$wget[513:450] :
propDstData_1_1_rl[513:450];
2'd2:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q5 =
CAN_FIRE_RL_srcPropose_5 ?
propDstData_1_2_lat_0$wget[513:450] :
propDstData_1_2_rl[513:450];
2'd3:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q5 =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(x__h71624 or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_4 or
propDstData_1_1_lat_0$wget or
propDstData_1_1_rl or
CAN_FIRE_RL_srcPropose_5 or
propDstData_1_2_lat_0$wget or propDstData_1_2_rl)
begin
case (x__h71624)
2'd0:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q6 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_0_lat_0$wget[449:386] :
propDstData_1_0_rl[449:386];
2'd1:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q6 =
CAN_FIRE_RL_srcPropose_4 ?
propDstData_1_1_lat_0$wget[449:386] :
propDstData_1_1_rl[449:386];
2'd2:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q6 =
CAN_FIRE_RL_srcPropose_5 ?
propDstData_1_2_lat_0$wget[449:386] :
propDstData_1_2_rl[449:386];
2'd3:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q6 =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(x__h71624 or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_4 or
propDstData_1_1_lat_0$wget or
propDstData_1_1_rl or
CAN_FIRE_RL_srcPropose_5 or
propDstData_1_2_lat_0$wget or propDstData_1_2_rl)
begin
case (x__h71624)
2'd0:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q7 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_0_lat_0$wget[385:322] :
propDstData_1_0_rl[385:322];
2'd1:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q7 =
CAN_FIRE_RL_srcPropose_4 ?
propDstData_1_1_lat_0$wget[385:322] :
propDstData_1_1_rl[385:322];
2'd2:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q7 =
CAN_FIRE_RL_srcPropose_5 ?
propDstData_1_2_lat_0$wget[385:322] :
propDstData_1_2_rl[385:322];
2'd3:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q7 =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(x__h71624 or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_4 or
propDstData_1_1_lat_0$wget or
propDstData_1_1_rl or
CAN_FIRE_RL_srcPropose_5 or
propDstData_1_2_lat_0$wget or propDstData_1_2_rl)
begin
case (x__h71624)
2'd0:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q8 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_0_lat_0$wget[321:258] :
propDstData_1_0_rl[321:258];
2'd1:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q8 =
CAN_FIRE_RL_srcPropose_4 ?
propDstData_1_1_lat_0$wget[321:258] :
propDstData_1_1_rl[321:258];
2'd2:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q8 =
CAN_FIRE_RL_srcPropose_5 ?
propDstData_1_2_lat_0$wget[321:258] :
propDstData_1_2_rl[321:258];
2'd3:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q8 =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(x__h71624 or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_4 or
propDstData_1_1_lat_0$wget or
propDstData_1_1_rl or
CAN_FIRE_RL_srcPropose_5 or
propDstData_1_2_lat_0$wget or propDstData_1_2_rl)
begin
case (x__h71624)
2'd0:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q9 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_0_lat_0$wget[257:194] :
propDstData_1_0_rl[257:194];
2'd1:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q9 =
CAN_FIRE_RL_srcPropose_4 ?
propDstData_1_1_lat_0$wget[257:194] :
propDstData_1_1_rl[257:194];
2'd2:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q9 =
CAN_FIRE_RL_srcPropose_5 ?
propDstData_1_2_lat_0$wget[257:194] :
propDstData_1_2_rl[257:194];
2'd3:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q9 =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(x__h71624 or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_4 or
propDstData_1_1_lat_0$wget or
propDstData_1_1_rl or
CAN_FIRE_RL_srcPropose_5 or
propDstData_1_2_lat_0$wget or propDstData_1_2_rl)
begin
case (x__h71624)
2'd0:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q10 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_0_lat_0$wget[193:130] :
propDstData_1_0_rl[193:130];
2'd1:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q10 =
CAN_FIRE_RL_srcPropose_4 ?
propDstData_1_1_lat_0$wget[193:130] :
propDstData_1_1_rl[193:130];
2'd2:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q10 =
CAN_FIRE_RL_srcPropose_5 ?
propDstData_1_2_lat_0$wget[193:130] :
propDstData_1_2_rl[193:130];
2'd3:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q10 =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(x__h71624 or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_4 or
propDstData_1_1_lat_0$wget or
propDstData_1_1_rl or
CAN_FIRE_RL_srcPropose_5 or
propDstData_1_2_lat_0$wget or propDstData_1_2_rl)
begin
case (x__h71624)
2'd0:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q11 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_0_lat_0$wget[129:66] :
propDstData_1_0_rl[129:66];
2'd1:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q11 =
CAN_FIRE_RL_srcPropose_4 ?
propDstData_1_1_lat_0$wget[129:66] :
propDstData_1_1_rl[129:66];
2'd2:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q11 =
CAN_FIRE_RL_srcPropose_5 ?
propDstData_1_2_lat_0$wget[129:66] :
propDstData_1_2_rl[129:66];
2'd3:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q11 =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(x__h71624 or
propDstData_1_0_dummy2_1_read__87_AND_IF_propD_ETC___d525 or
propDstData_1_1_dummy2_1_read__92_AND_IF_propD_ETC___d529 or
propDstData_1_2_dummy2_1_read__97_AND_IF_propD_ETC___d533)
begin
case (x__h71624)
2'd0:
CASE_x1624_0_propDstData_1_0_dummy2_1_read__87_ETC__q12 =
propDstData_1_0_dummy2_1_read__87_AND_IF_propD_ETC___d525;
2'd1:
CASE_x1624_0_propDstData_1_0_dummy2_1_read__87_ETC__q12 =
propDstData_1_1_dummy2_1_read__92_AND_IF_propD_ETC___d529;
2'd2:
CASE_x1624_0_propDstData_1_0_dummy2_1_read__87_ETC__q12 =
propDstData_1_2_dummy2_1_read__97_AND_IF_propD_ETC___d533;
2'd3:
CASE_x1624_0_propDstData_1_0_dummy2_1_read__87_ETC__q12 =
1'b0 /* unspecified value */ ;
endcase
end
always@(x__h71624 or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_4 or
propDstData_1_1_lat_0$wget or
propDstData_1_1_rl or
CAN_FIRE_RL_srcPropose_5 or
propDstData_1_2_lat_0$wget or propDstData_1_2_rl)
begin
case (x__h71624)
2'd0:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q13 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_0_lat_0$wget[65:2] :
propDstData_1_0_rl[65:2];
2'd1:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q13 =
CAN_FIRE_RL_srcPropose_4 ?
propDstData_1_1_lat_0$wget[65:2] :
propDstData_1_1_rl[65:2];
2'd2:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q13 =
CAN_FIRE_RL_srcPropose_5 ?
propDstData_1_2_lat_0$wget[65:2] :
propDstData_1_2_rl[65:2];
2'd3:
CASE_x1624_0_IF_CAN_FIRE_RL_srcPropose_3_THEN__ETC__q13 =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(x__h71624 or
IF_propDstData_1_0_dummy2_1_read__87_THEN_IF_p_ETC___d511 or
IF_propDstData_1_1_dummy2_1_read__92_THEN_IF_p_ETC___d515 or
IF_propDstData_1_2_dummy2_1_read__97_THEN_IF_p_ETC___d519)
begin
case (x__h71624)
2'd0:
CASE_x1624_0_IF_propDstData_1_0_dummy2_1_read__ETC__q14 =
IF_propDstData_1_0_dummy2_1_read__87_THEN_IF_p_ETC___d511;
2'd1:
CASE_x1624_0_IF_propDstData_1_0_dummy2_1_read__ETC__q14 =
IF_propDstData_1_1_dummy2_1_read__92_THEN_IF_p_ETC___d515;
2'd2:
CASE_x1624_0_IF_propDstData_1_0_dummy2_1_read__ETC__q14 =
IF_propDstData_1_2_dummy2_1_read__97_THEN_IF_p_ETC___d519;
2'd3:
CASE_x1624_0_IF_propDstData_1_0_dummy2_1_read__ETC__q14 =
2'b10 /* unspecified value */ ;
endcase
end
always@(x__h71624 or
n__read_addr__h71844 or
n__read_addr__h71923 or n__read_addr__h72002)
begin
case (x__h71624)
2'd0:
CASE_x1624_0_n__read_addr1844_1_n__read_addr19_ETC__q15 =
n__read_addr__h71844;
2'd1:
CASE_x1624_0_n__read_addr1844_1_n__read_addr19_ETC__q15 =
n__read_addr__h71923;
2'd2:
CASE_x1624_0_n__read_addr1844_1_n__read_addr19_ETC__q15 =
n__read_addr__h72002;
2'd3:
CASE_x1624_0_n__read_addr1844_1_n__read_addr19_ETC__q15 =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY 75'h2AAAAAAAAAAAAAAAAAA;
enqDst_1_0_rl <= `BSV_ASSIGNMENT_DELAY
582'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
4'd0;
llc_axi4_adapter_master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
llc_axi4_adapter_master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
llc_axi4_adapter_master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
llc_axi4_adapter_master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
llc_axi4_adapter_master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
llc_axi4_adapter_rg_AXI4_error <= `BSV_ASSIGNMENT_DELAY 1'd0;
llc_axi4_adapter_rg_ddr4_ready <= `BSV_ASSIGNMENT_DELAY 1'd0;
llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
llc_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
llc_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
llc_axi4_adapter_rg_wr_rsp_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY 74'h2AAAAAAAAAAAAAAAAAA;
propDstData_1_0_rl <= `BSV_ASSIGNMENT_DELAY
581'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
propDstData_1_1_rl <= `BSV_ASSIGNMENT_DELAY
581'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
propDstData_1_2_rl <= `BSV_ASSIGNMENT_DELAY
581'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
propDstData_1_rl <= `BSV_ASSIGNMENT_DELAY 74'h2AAAAAAAAAAAAAAAAAA;
propDstData_2_rl <= `BSV_ASSIGNMENT_DELAY 74'h2AAAAAAAAAAAAAAAAAA;
propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
propDstIdx_1_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
propDstIdx_1_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
propDstIdx_1_2_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
propDstIdx_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
propDstIdx_2_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 2'd2;
srcRR_0 <= `BSV_ASSIGNMENT_DELAY 2'd0;
srcRR_1_0 <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (enqDst_0_rl$EN)
enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY enqDst_0_rl$D_IN;
if (enqDst_1_0_rl$EN)
enqDst_1_0_rl <= `BSV_ASSIGNMENT_DELAY enqDst_1_0_rl$D_IN;
if (llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN)
llc_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN;
if (llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN)
llc_axi4_adapter_master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN;
if (llc_axi4_adapter_master_xactor_crg_rd_data_full$EN)
llc_axi4_adapter_master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_crg_rd_data_full$D_IN;
if (llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN)
llc_axi4_adapter_master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN;
if (llc_axi4_adapter_master_xactor_crg_wr_data_full$EN)
llc_axi4_adapter_master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_crg_wr_data_full$D_IN;
if (llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN)
llc_axi4_adapter_master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN;
if (llc_axi4_adapter_rg_AXI4_error$EN)
llc_axi4_adapter_rg_AXI4_error <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_rg_AXI4_error$D_IN;
if (llc_axi4_adapter_rg_ddr4_ready$EN)
llc_axi4_adapter_rg_ddr4_ready <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_rg_ddr4_ready$D_IN;
if (llc_axi4_adapter_rg_rd_req_beat$EN)
llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_rg_rd_req_beat$D_IN;
if (llc_axi4_adapter_rg_rd_rsp_beat$EN)
llc_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_rg_rd_rsp_beat$D_IN;
if (llc_axi4_adapter_rg_wr_req_beat$EN)
llc_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_rg_wr_req_beat$D_IN;
if (llc_axi4_adapter_rg_wr_rsp_beat$EN)
llc_axi4_adapter_rg_wr_rsp_beat <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_rg_wr_rsp_beat$D_IN;
if (propDstData_0_rl$EN)
propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY propDstData_0_rl$D_IN;
if (propDstData_1_0_rl$EN)
propDstData_1_0_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_0_rl$D_IN;
if (propDstData_1_1_rl$EN)
propDstData_1_1_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_1_rl$D_IN;
if (propDstData_1_2_rl$EN)
propDstData_1_2_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_2_rl$D_IN;
if (propDstData_1_rl$EN)
propDstData_1_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_rl$D_IN;
if (propDstData_2_rl$EN)
propDstData_2_rl <= `BSV_ASSIGNMENT_DELAY propDstData_2_rl$D_IN;
if (propDstIdx_0_rl$EN)
propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_0_rl$D_IN;
if (propDstIdx_1_0_rl$EN)
propDstIdx_1_0_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_1_0_rl$D_IN;
if (propDstIdx_1_1_rl$EN)
propDstIdx_1_1_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_1_1_rl$D_IN;
if (propDstIdx_1_2_rl$EN)
propDstIdx_1_2_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_1_2_rl$D_IN;
if (propDstIdx_1_rl$EN)
propDstIdx_1_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_1_rl$D_IN;
if (propDstIdx_2_rl$EN)
propDstIdx_2_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_2_rl$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
if (srcRR_0$EN) srcRR_0 <= `BSV_ASSIGNMENT_DELAY srcRR_0$D_IN;
if (srcRR_1_0$EN) srcRR_1_0 <= `BSV_ASSIGNMENT_DELAY srcRR_1_0$D_IN;
end
if (llc_axi4_adapter_master_xactor_rg_rd_addr$EN)
llc_axi4_adapter_master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN;
if (llc_axi4_adapter_master_xactor_rg_rd_data$EN)
llc_axi4_adapter_master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_rg_rd_data$D_IN;
if (llc_axi4_adapter_master_xactor_rg_wr_addr$EN)
llc_axi4_adapter_master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN;
if (llc_axi4_adapter_master_xactor_rg_wr_data$EN)
llc_axi4_adapter_master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_rg_wr_data$D_IN;
if (llc_axi4_adapter_master_xactor_rg_wr_resp$EN)
llc_axi4_adapter_master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_rg_wr_resp$D_IN;
if (llc_axi4_adapter_rg_cline$EN)
llc_axi4_adapter_rg_cline <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_rg_cline$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
enqDst_0_rl = 75'h2AAAAAAAAAAAAAAAAAA;
enqDst_1_0_rl =
582'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_ctr_wr_rsps_pending_crg = 4'hA;
llc_axi4_adapter_master_xactor_crg_rd_addr_full = 1'h0;
llc_axi4_adapter_master_xactor_crg_rd_data_full = 1'h0;
llc_axi4_adapter_master_xactor_crg_wr_addr_full = 1'h0;
llc_axi4_adapter_master_xactor_crg_wr_data_full = 1'h0;
llc_axi4_adapter_master_xactor_crg_wr_resp_full = 1'h0;
llc_axi4_adapter_master_xactor_rg_rd_addr =
109'h0AAAAAAAAAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_master_xactor_rg_rd_data = 83'h2AAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_master_xactor_rg_wr_addr =
109'h0AAAAAAAAAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_master_xactor_rg_wr_data = 73'h0AAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_master_xactor_rg_wr_resp = 18'h2AAAA;
llc_axi4_adapter_rg_AXI4_error = 1'h0;
llc_axi4_adapter_rg_cline =
512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_rg_ddr4_ready = 1'h0;
llc_axi4_adapter_rg_rd_req_beat = 3'h2;
llc_axi4_adapter_rg_rd_rsp_beat = 3'h2;
llc_axi4_adapter_rg_wr_req_beat = 3'h2;
llc_axi4_adapter_rg_wr_rsp_beat = 3'h2;
propDstData_0_rl = 74'h2AAAAAAAAAAAAAAAAAA;
propDstData_1_0_rl =
581'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
propDstData_1_1_rl =
581'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
propDstData_1_2_rl =
581'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
propDstData_1_rl = 74'h2AAAAAAAAAAAAAAAAAA;
propDstData_2_rl = 74'h2AAAAAAAAAAAAAAAAAA;
propDstIdx_0_rl = 1'h0;
propDstIdx_1_0_rl = 1'h0;
propDstIdx_1_1_rl = 1'h0;
propDstIdx_1_2_rl = 1'h0;
propDstIdx_1_rl = 1'h0;
propDstIdx_2_rl = 1'h0;
rg_state = 2'h2;
srcRR_0 = 2'h2;
srcRR_1_0 = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (NOT_enqDst_0_dummy2_0_read__29_30_OR_NOT_enqDs_ETC___d253 &&
x__h45600 == 2'd0 &&
NOT_propDstIdx_0_dummy2_1_read__95_96_OR_IF_pr_ETC___d245)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing");
if (RST_N != `BSV_RESET_VALUE)
if (NOT_enqDst_0_dummy2_0_read__29_30_OR_NOT_enqDs_ETC___d253 &&
x__h45600 == 2'd0 &&
NOT_propDstIdx_0_dummy2_1_read__95_96_OR_IF_pr_ETC___d245)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_enqDst_0_dummy2_0_read__29_30_OR_NOT_enqDs_ETC___d253 &&
x__h45600 == 2'd1 &&
NOT_propDstIdx_1_dummy2_1_read__08_09_OR_IF_pr_ETC___d248)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing");
if (RST_N != `BSV_RESET_VALUE)
if (NOT_enqDst_0_dummy2_0_read__29_30_OR_NOT_enqDs_ETC___d253 &&
x__h45600 == 2'd1 &&
NOT_propDstIdx_1_dummy2_1_read__08_09_OR_IF_pr_ETC___d248)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_enqDst_0_dummy2_0_read__29_30_OR_NOT_enqDs_ETC___d253 &&
x__h45600 == 2'd2 &&
NOT_propDstIdx_2_dummy2_1_read__21_22_OR_IF_pr_ETC___d363)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing");
if (RST_N != `BSV_RESET_VALUE)
if (NOT_enqDst_0_dummy2_0_read__29_30_OR_NOT_enqDs_ETC___d253 &&
x__h45600 == 2'd2 &&
NOT_propDstIdx_2_dummy2_1_read__21_22_OR_IF_pr_ETC___d363)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_enqDst_1_0_dummy2_0_read__62_63_OR_NOT_enq_ETC___d486 &&
x__h71624 == 2'd0 &&
NOT_propDstIdx_1_0_dummy2_1_read__28_29_OR_IF__ETC___d478)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing");
if (RST_N != `BSV_RESET_VALUE)
if (NOT_enqDst_1_0_dummy2_0_read__62_63_OR_NOT_enq_ETC___d486 &&
x__h71624 == 2'd0 &&
NOT_propDstIdx_1_0_dummy2_1_read__28_29_OR_IF__ETC___d478)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_enqDst_1_0_dummy2_0_read__62_63_OR_NOT_enq_ETC___d486 &&
x__h71624 == 2'd1 &&
NOT_propDstIdx_1_1_dummy2_1_read__41_42_OR_IF__ETC___d481)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing");
if (RST_N != `BSV_RESET_VALUE)
if (NOT_enqDst_1_0_dummy2_0_read__62_63_OR_NOT_enq_ETC___d486 &&
x__h71624 == 2'd1 &&
NOT_propDstIdx_1_1_dummy2_1_read__41_42_OR_IF__ETC___d481)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_enqDst_1_0_dummy2_0_read__62_63_OR_NOT_enq_ETC___d486 &&
x__h71624 == 2'd2 &&
NOT_propDstIdx_1_2_dummy2_1_read__54_55_OR_IF__ETC___d659)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/CrossBar.bsv\", line 123, column 53\nsrc must be proposing");
if (RST_N != `BSV_RESET_VALUE)
if (NOT_enqDst_1_0_dummy2_0_read__62_63_OR_NOT_enq_ETC___d486 &&
x__h71624 == 2'd2 &&
NOT_propDstIdx_1_2_dummy2_1_read__54_55_OR_IF__ETC___d659)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read__38_ULE_1_39___d740)
begin
v__h84135 = $stime;
#0;
end
v__h84129 = v__h84135 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && NOT_cfg_verbosity_read__38_ULE_1_39___d740)
$display("%0d: Near_Mem.rl_reset", v__h84129);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete &&
NOT_cfg_verbosity_read__38_ULE_1_39___d740)
begin
v__h84241 = $stime;
#0;
end
v__h84235 = v__h84241 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete &&
NOT_cfg_verbosity_read__38_ULE_1_39___d740)
$display("%0d: Near_Mem.rl_reset_complete", v__h84235);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
begin
v__h13951 = $stime;
#0;
end
v__h13945 = v__h13951 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit",
v__h13945);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 &&
llc_axi4_adapter_master_xactor_rg_rd_data[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 &&
!llc_axi4_adapter_master_xactor_rg_rd_data[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_ddr4_ready)
begin
v__h85786 = $stime;
#0;
end
v__h85780 = v__h85786 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_ddr4_ready)
$display("%0d: %m.LLC_AXI4_Adapter.ma_ddr4_ready: enabling all rules",
v__h85780);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
begin
v__h31896 = $stime;
#0;
end
v__h31890 = v__h31896 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$display("%0d: %m.LLC_AXI4_Adapter.rl_discard_write_rsp", v__h31890);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$display(" ERROR: fabric response error: exit");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$finish(32'd1);
end
// synopsys translate_on
endmodule // mkNear_Mem
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_hdmi_tx (
// hdmi interface
hdmi_clk,
hdmi_rst,
hdmi_full_range,
hdmi_csc_bypass,
hdmi_ss_bypass,
hdmi_srcsel,
hdmi_const_rgb,
hdmi_hl_active,
hdmi_hl_width,
hdmi_hs_width,
hdmi_he_max,
hdmi_he_min,
hdmi_vf_active,
hdmi_vf_width,
hdmi_vs_width,
hdmi_ve_max,
hdmi_ve_min,
hdmi_status,
hdmi_tpm_oos,
hdmi_clk_ratio,
// vdma interface
vdma_clk,
vdma_rst,
vdma_ovf,
vdma_unf,
vdma_tpm_oos,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00040063;
parameter ID = 0;
// hdmi interface
input hdmi_clk;
output hdmi_rst;
output hdmi_full_range;
output hdmi_csc_bypass;
output hdmi_ss_bypass;
output [ 1:0] hdmi_srcsel;
output [23:0] hdmi_const_rgb;
output [15:0] hdmi_hl_active;
output [15:0] hdmi_hl_width;
output [15:0] hdmi_hs_width;
output [15:0] hdmi_he_max;
output [15:0] hdmi_he_min;
output [15:0] hdmi_vf_active;
output [15:0] hdmi_vf_width;
output [15:0] hdmi_vs_width;
output [15:0] hdmi_ve_max;
output [15:0] hdmi_ve_min;
input hdmi_status;
input hdmi_tpm_oos;
input [31:0] hdmi_clk_ratio;
// vdma interface
input vdma_clk;
output vdma_rst;
input vdma_ovf;
input vdma_unf;
input vdma_tpm_oos;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_core_preset = 'd0;
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg up_full_range = 'd0;
reg up_csc_bypass = 'd0;
reg up_ss_bypass = 'd0;
reg [ 1:0] up_srcsel = 'd1;
reg [23:0] up_const_rgb = 'd0;
reg up_vdma_ovf = 'd0;
reg up_vdma_unf = 'd0;
reg up_hdmi_tpm_oos = 'd0;
reg up_vdma_tpm_oos = 'd0;
reg [15:0] up_hl_active = 'd0;
reg [15:0] up_hl_width = 'd0;
reg [15:0] up_hs_width = 'd0;
reg [15:0] up_he_max = 'd0;
reg [15:0] up_he_min = 'd0;
reg [15:0] up_vf_active = 'd0;
reg [15:0] up_vf_width = 'd0;
reg [15:0] up_vs_width = 'd0;
reg [15:0] up_ve_max = 'd0;
reg [15:0] up_ve_min = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_hdmi_status_s;
wire up_hdmi_tpm_oos_s;
wire [31:0] up_hdmi_clk_count_s;
wire up_vdma_ovf_s;
wire up_vdma_unf_s;
wire up_vdma_tpm_oos_s;
// decode block select
assign up_wreq_s = (up_waddr[13:12] == 2'd0) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:12] == 2'd0) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_core_preset <= 1'd1;
up_wack <= 'd0;
up_scratch <= 'd0;
up_resetn <= 'd0;
up_full_range <= 'd0;
up_csc_bypass <= 'd0;
up_ss_bypass <= 'd0;
up_srcsel <= 'd1;
up_const_rgb <= 'd0;
up_vdma_ovf <= 'd0;
up_vdma_unf <= 'd0;
up_hdmi_tpm_oos <= 'd0;
up_vdma_tpm_oos <= 'd0;
up_hl_active <= 'd0;
up_hl_width <= 'd0;
up_hs_width <= 'd0;
up_he_max <= 'd0;
up_he_min <= 'd0;
up_vf_active <= 'd0;
up_vf_width <= 'd0;
up_vs_width <= 'd0;
up_ve_max <= 'd0;
up_ve_min <= 'd0;
end else begin
up_core_preset <= ~up_resetn;
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h002)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h010)) begin
up_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin
up_ss_bypass <= up_wdata[2];
up_full_range <= up_wdata[1];
up_csc_bypass <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h012)) begin
up_srcsel <= up_wdata[1:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h013)) begin
up_const_rgb <= up_wdata[23:0];
end
if (up_vdma_ovf_s == 1'b1) begin
up_vdma_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin
up_vdma_ovf <= up_vdma_ovf & ~up_wdata[1];
end
if (up_vdma_unf_s == 1'b1) begin
up_vdma_unf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin
up_vdma_unf <= up_vdma_unf & ~up_wdata[0];
end
if (up_hdmi_tpm_oos_s == 1'b1) begin
up_hdmi_tpm_oos <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin
up_hdmi_tpm_oos <= up_hdmi_tpm_oos & ~up_wdata[1];
end
if (up_vdma_tpm_oos_s == 1'b1) begin
up_vdma_tpm_oos <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin
up_vdma_tpm_oos <= up_vdma_tpm_oos & ~up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin
up_hl_active <= up_wdata[31:16];
up_hl_width <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h101)) begin
up_hs_width <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h102)) begin
up_he_max <= up_wdata[31:16];
up_he_min <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h110)) begin
up_vf_active <= up_wdata[31:16];
up_vf_width <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h111)) begin
up_vs_width <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h112)) begin
up_ve_max <= up_wdata[31:16];
up_ve_min <= up_wdata[15:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[11:0])
12'h000: up_rdata <= PCORE_VERSION;
12'h001: up_rdata <= ID;
12'h002: up_rdata <= up_scratch;
12'h010: up_rdata <= {31'd0, up_resetn};
12'h011: up_rdata <= {29'd0, up_ss_bypass, up_full_range, up_csc_bypass};
12'h012: up_rdata <= {30'd0, up_srcsel};
12'h013: up_rdata <= {8'd0, up_const_rgb};
12'h015: up_rdata <= up_hdmi_clk_count_s;
12'h016: up_rdata <= hdmi_clk_ratio;
12'h017: up_rdata <= {31'd0, up_hdmi_status_s};
12'h018: up_rdata <= {30'd0, up_vdma_ovf, up_vdma_unf};
12'h019: up_rdata <= {30'd0, up_hdmi_tpm_oos, up_vdma_tpm_oos};
12'h100: up_rdata <= {up_hl_active, up_hl_width};
12'h101: up_rdata <= {16'd0, up_hs_width};
12'h102: up_rdata <= {up_he_max, up_he_min};
12'h110: up_rdata <= {up_vf_active, up_vf_width};
12'h111: up_rdata <= {16'd0, up_vs_width};
12'h112: up_rdata <= {up_ve_max, up_ve_min};
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
ad_rst i_core_rst_reg (.preset(up_core_preset), .clk(hdmi_clk), .rst(hdmi_rst));
ad_rst i_vdma_rst_reg (.preset(up_core_preset), .clk(vdma_clk), .rst(vdma_rst));
// hdmi control & status
up_xfer_cntrl #(.DATA_WIDTH(189)) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_ss_bypass,
up_full_range,
up_csc_bypass,
up_srcsel,
up_const_rgb,
up_hl_active,
up_hl_width,
up_hs_width,
up_he_max,
up_he_min,
up_vf_active,
up_vf_width,
up_vs_width,
up_ve_max,
up_ve_min}),
.up_xfer_done (),
.d_rst (hdmi_rst),
.d_clk (hdmi_clk),
.d_data_cntrl ({ hdmi_ss_bypass,
hdmi_full_range,
hdmi_csc_bypass,
hdmi_srcsel,
hdmi_const_rgb,
hdmi_hl_active,
hdmi_hl_width,
hdmi_hs_width,
hdmi_he_max,
hdmi_he_min,
hdmi_vf_active,
hdmi_vf_width,
hdmi_vs_width,
hdmi_ve_max,
hdmi_ve_min}));
up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_hdmi_status_s,
up_hdmi_tpm_oos_s}),
.d_rst (hdmi_rst),
.d_clk (hdmi_clk),
.d_data_status ({ hdmi_status,
hdmi_tpm_oos}));
// hdmi clock monitor
up_clock_mon i_clock_mon (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_d_count (up_hdmi_clk_count_s),
.d_rst (hdmi_rst),
.d_clk (hdmi_clk));
// vdma control & status
up_xfer_status #(.DATA_WIDTH(3)) i_vdma_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_vdma_ovf_s,
up_vdma_unf_s,
up_vdma_tpm_oos_s}),
.d_rst (vdma_rst),
.d_clk (vdma_clk),
.d_data_status ({ vdma_ovf,
vdma_unf,
vdma_tpm_oos}));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : axi_basic_top.v
// Version : 2.3
//----------------------------------------------------------------------------//
// File: axi_basic_top.v //
// //
// Description: //
// TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_top #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // TSTRB width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [STRB_WIDTH-1:0] s_axis_tx_tstrb, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [STRB_WIDTH-1:0] m_axis_rx_tstrb, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
axi_basic_rx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) rx_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tstrb( m_axis_rx_tstrb ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
axi_basic_tx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) tx_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tstrb( s_axis_tx_tstrb ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tbuf_av( trn_tbuf_av ),
.trn_tecrc_gen( trn_tecrc_gen ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Series/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
// Date : Fri Sep 22 17:41:20 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_stub.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_bram_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_6,Vivado 2017.2.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, rsta, ena, wea, addra, dina, douta, clkb, rstb, enb,
web, addrb, dinb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,rsta,ena,wea[3:0],addra[31:0],dina[31:0],douta[31:0],clkb,rstb,enb,web[3:0],addrb[31:0],dinb[31:0],doutb[31:0]" */;
input clka;
input rsta;
input ena;
input [3:0]wea;
input [31:0]addra;
input [31:0]dina;
output [31:0]douta;
input clkb;
input rstb;
input enb;
input [3:0]web;
input [31:0]addrb;
input [31:0]dinb;
output [31:0]doutb;
endmodule
|
module xyz (/*AUTOARG*/
// Inputs
signal_e3, signal_e, signal_b
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [2:0] signal_b; // To u_abc of abc.v
input signal_e; // To u_def of def.v
input signal_e3; // To u_def of def.v
// End of automatics
/*AUTOOUTPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire signal_c; // From u_abc of abc.v
wire signal_f; // From u_def of def.v
// End of automatics
/* abc AUTO_TEMPLATE
(
// Outputs
.signal_c (signal_c),
// Inputs
.signal_a ({1'b0, signal_f}),
.signal_b (signal_b[2:0]));
*/
abc u_abc
(/*AUTOINST*/
// Outputs
.signal_c (signal_c), // Templated
// Inputs
.signal_a ({1'b0, signal_f}), // Templated
.signal_b (signal_b[2:0])); // Templated
/* def AUTO_TEMPLATE
(// Outputs
.signal_f (signal_f),
// Inputs
.signal_d ({1'b1, signal_c}),
.signal_e ({2'b11, signal_e}),
.signal_e2 (({2'b11, signal_e2})),
.signal_e3 ((signal_e3)) );
*/
def u_def
(/*AUTOINST*/
// Outputs
.signal_f (signal_f), // Templated
// Inputs
.signal_d ({1'b1, signal_c}), // Templated
.signal_e ({2'b11, signal_e}), // Templated
.signal_e2 (({2'b11, signal_e2})), // Templated
.signal_e3 ((signal_e3))); // Templated
endmodule // xyz
module abc (/*AUTOARG*/
// Outputs
signal_c,
// Inputs
signal_a, signal_b
);
input [1:0] signal_a;
input [2:0] signal_b;
output signal_c;
endmodule // abc
module def (/*AUTOARG*/
// Outputs
signal_f,
// Inputs
signal_d, signal_e, signal_e2, signal_e3
);
input [1:0] signal_d;
input [2:0] signal_e;
input [3:0] signal_e2;
input [3:0] signal_e3;
output signal_f;
endmodule // def
// Local Variables:
// verilog-auto-ignore-concat: t
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2A_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__O2BB2A_FUNCTIONAL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X, nand0_out, or0_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2A_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S25KAPWR_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DLYBUF4S25KAPWR_PP_SYMBOL_V
/**
* dlybuf4s25kapwr: Delay Buffer 4-stage 0.25um length inner stage
* gates on keep-alive power rail.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlybuf4s25kapwr (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input KAPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S25KAPWR_PP_SYMBOL_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file rom_8x2k_lo.v when simulating
// the core, rom_8x2k_lo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module rom_8x2k_lo(
addr,
clk,
din,
dout,
en,
we);
input [10 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input we;
// synthesis translate_off
BLKMEMSP_V6_2 #(
.c_addr_width(11),
.c_default_data("0"),
.c_depth(2048),
.c_enable_rlocs(0),
.c_has_default_data(1),
.c_has_din(1),
.c_has_en(1),
.c_has_limit_data_pitch(0),
.c_has_nd(0),
.c_has_rdy(0),
.c_has_rfd(0),
.c_has_sinit(0),
.c_has_we(1),
.c_limit_data_pitch(18),
.c_mem_init_file("mif_file_16_1"),
.c_pipe_stages(0),
.c_reg_inputs(0),
.c_sinit_value("0"),
.c_width(8),
.c_write_mode(0),
.c_ybottom_addr("0"),
.c_yclk_is_rising(1),
.c_yen_is_high(0),
.c_yhierarchy("hierarchy1"),
.c_ymake_bmm(0),
.c_yprimitive_type("16kx1"),
.c_ysinit_is_high(1),
.c_ytop_addr("1024"),
.c_yuse_single_primitive(0),
.c_ywe_is_high(0),
.c_yydisable_warnings(1))
inst (
.ADDR(addr),
.CLK(clk),
.DIN(din),
.DOUT(dout),
.EN(en),
.WE(we),
.ND(),
.RFD(),
.RDY(),
.SINIT());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of rom_8x2k_lo is "black_box"
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.13)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Dual Data Rate Input D Flip-Flop
// /___/ /\ Filename : IDDR.v
// \ \ / \ Timestamp : Thu Mar 11 16:44:06 PST 2005
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus.
// 12/20/05 - Fixed setup and hold checks.
// 04/28/06 - Added c_in into the sensitivity list (CR 219840).
// 05/29/07 - Added wire declaration for internal signals
// 04/16/08 - CR 468871 Negative SetupHold fix
// 05/06/08 - CR 455447 add XON MSGON property to support async reg
// 12/03/08 - CR 498674 added pulldown on R/S.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 08/23/13 - PR683925 - add invertible pin support.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IDDR (Q1, Q2, C, CE, D, R, S);
output Q1;
output Q2;
input C;
input CE;
input D;
input R;
input S;
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT_Q1 = 1'b0;
parameter INIT_Q2 = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter SRTYPE = "SYNC";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
parameter MSGON = "TRUE";
parameter XON = "TRUE";
`endif
pulldown P1 (R);
pulldown P2 (S);
reg q1_out = INIT_Q1, q2_out = INIT_Q2;
reg q1_out_int, q2_out_int;
reg q1_out_pipelined, q2_out_same_edge_int;
reg notifier, notifier1, notifier2;
wire notifier1x, notifier2x;
wire c_in,delay_c;
wire ce_in,delay_ce;
wire d_in,delay_d;
wire gsr_in;
wire r_in,delay_r;
wire s_in,delay_s;
tri0 GSR = glbl.GSR;
assign gsr_in = GSR;
assign Q1 = q1_out;
assign Q2 = q2_out;
wire nr, ns, ngsr;
wire ce_c_enable, d_c_enable, r_c_enable, s_c_enable;
wire ce_c_enable1, d_c_enable1, r_c_enable1, s_c_enable1;
not (nr, R);
not (ns, S);
not (ngsr, GSR);
and (ce_c_enable, ngsr, nr, ns);
and (d_c_enable, ngsr, nr, ns, CE);
and (s_c_enable, ngsr, nr);
`ifdef XIL_TIMING
assign notifier1x = (XON == "FALSE") ? 1'bx : notifier1;
assign notifier2x = (XON == "FALSE") ? 1'bx : notifier2;
assign ce_c_enable1 = (MSGON =="FALSE") ? 1'b0 : ce_c_enable;
assign d_c_enable1 = (MSGON =="FALSE") ? 1'b0 : d_c_enable;
assign r_c_enable1 = (MSGON =="FALSE") ? 1'b0 : ngsr;
assign s_c_enable1 = (MSGON =="FALSE") ? 1'b0 : s_c_enable;
`endif
initial begin
if ((INIT_Q1 != 0) && (INIT_Q1 != 1)) begin
$display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q1);
#1 $finish;
end
if ((INIT_Q2 != 0) && (INIT_Q2 != 1)) begin
$display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q2);
#1 $finish;
end
if ((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE_PIPELINED")) begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE);
#1 $finish;
end
if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
$display("Attribute Syntax Error : The attribute SRTYPE on IDDR instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
#1 $finish;
end
end // initial begin
always @(gsr_in or r_in or s_in) begin
if (gsr_in == 1'b1) begin
assign q1_out_int = INIT_Q1;
assign q1_out_pipelined = INIT_Q1;
assign q2_out_same_edge_int = INIT_Q2;
assign q2_out_int = INIT_Q2;
end
else if (gsr_in == 1'b0) begin
if (r_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q1_out_int = 1'b0;
assign q1_out_pipelined = 1'b0;
assign q2_out_same_edge_int = 1'b0;
assign q2_out_int = 1'b0;
end
else if (r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q1_out_int = 1'b1;
assign q1_out_pipelined = 1'b1;
assign q2_out_same_edge_int = 1'b1;
assign q2_out_int = 1'b1;
end
else if ((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin
deassign q1_out_int;
deassign q1_out_pipelined;
deassign q2_out_same_edge_int;
deassign q2_out_int;
end
else if (r_in == 1'b0 && s_in == 1'b0) begin
deassign q1_out_int;
deassign q1_out_pipelined;
deassign q2_out_same_edge_int;
deassign q2_out_int;
end
end // if (gsr_in == 1'b0)
end // always @ (gsr_in or r_in or s_in)
always @(posedge c_in) begin
if (r_in == 1'b1) begin
q1_out_int <= 1'b0;
q1_out_pipelined <= 1'b0;
q2_out_same_edge_int <= 1'b0;
end
else if (r_in == 1'b0 && s_in == 1'b1) begin
q1_out_int <= 1'b1;
q1_out_pipelined <= 1'b1;
q2_out_same_edge_int <= 1'b1;
end
else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
q1_out_int <= d_in;
q1_out_pipelined <= q1_out_int;
q2_out_same_edge_int <= q2_out_int;
end
end // always @ (posedge c_in)
always @(negedge c_in) begin
if (r_in == 1'b1)
q2_out_int <= 1'b0;
else if (r_in == 1'b0 && s_in == 1'b1)
q2_out_int <= 1'b1;
else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0)
q2_out_int <= d_in;
end
always @(c_in or q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined) begin
case (DDR_CLK_EDGE)
"OPPOSITE_EDGE" : begin
q1_out <= q1_out_int;
q2_out <= q2_out_int;
end
"SAME_EDGE" : begin
q1_out <= q1_out_int;
q2_out <= q2_out_same_edge_int;
end
"SAME_EDGE_PIPELINED" : begin
q1_out <= q1_out_pipelined;
q2_out <= q2_out_same_edge_int;
end
default : begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE);
$finish;
end
endcase // case(DDR_CLK_EDGE)
end // always @ (q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined or q2_out_pipelined)
`ifndef XIL_TIMING
assign delay_c = C;
assign delay_ce = CE;
assign delay_d = D;
assign delay_r = R;
assign delay_s = S;
`endif
assign c_in = IS_C_INVERTED ^ delay_c;
assign ce_in = delay_ce;
assign d_in = IS_D_INVERTED ^ delay_d;
assign r_in = delay_r;
assign s_in = delay_s;
//*** Timing Checks Start here
`ifdef XIL_TIMING
always @(notifier or notifier1x) begin
q1_out <= 1'bx;
end
always @(notifier or notifier2x) begin
q2_out <= 1'bx;
end
`endif
`ifdef XIL_TIMING
wire c_en_n;
wire c_en_p;
wire ce_c_enable1_n,d_c_enable1_n,r_c_enable1_n,s_c_enable1_n;
wire ce_c_enable1_p,d_c_enable1_p,r_c_enable1_p,s_c_enable1_p;
assign c_en_n = IS_C_INVERTED;
assign c_en_p = ~IS_C_INVERTED;
assign ce_c_enable1_n = ce_c_enable1 && c_en_n;
assign ce_c_enable1_p = ce_c_enable1 && c_en_p;
assign d_c_enable1_n = d_c_enable1 && c_en_n;
assign d_c_enable1_p = d_c_enable1 && c_en_p;
assign r_c_enable1_n = r_c_enable1 && c_en_n;
assign r_c_enable1_p = r_c_enable1 && c_en_p;
assign s_c_enable1_p = s_c_enable1 && c_en_p;
assign s_c_enable1_n = s_c_enable1 && c_en_n;
`endif
specify
(C => Q1) = (100:100:100, 100:100:100);
(C => Q2) = (100:100:100, 100:100:100);
(posedge R => (Q1 +: 0)) = (0:0:0, 0:0:0);
(posedge R => (Q2 +: 0)) = (0:0:0, 0:0:0);
(posedge S => (Q1 +: 0)) = (0:0:0, 0:0:0);
(posedge S => (Q2 +: 0)) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
(R => Q1) = (0:0:0, 0:0:0);
(R => Q2) = (0:0:0, 0:0:0);
(S => Q1) = (0:0:0, 0:0:0);
(S => Q2) = (0:0:0, 0:0:0);
$period (negedge C, 0:0:0, notifier);
$period (posedge C, 0:0:0, notifier);
$recrem (negedge R, negedge C, 0:0:0, 0:0:0, notifier2, c_en_n, c_en_n);
$recrem (negedge R, posedge C, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p);
$recrem (negedge S, negedge C, 0:0:0, 0:0:0, notifier2, c_en_n, c_en_n);
$recrem (negedge S, posedge C, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p);
$recrem ( posedge R, negedge C, 0:0:0, 0:0:0, notifier2, c_en_n, c_en_n);
$recrem ( posedge R, posedge C, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p);
$recrem ( posedge S, negedge C, 0:0:0, 0:0:0, notifier2, c_en_n, c_en_n);
$recrem ( posedge S, posedge C, 0:0:0, 0:0:0, notifier1, c_en_p, c_en_p);
$setuphold (negedge C, negedge CE &&& (ce_c_enable1_n!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_ce);
$setuphold (negedge C, negedge D &&& (d_c_enable1_n!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_d);
$setuphold (negedge C, negedge R &&& (r_c_enable1_n!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_r);
$setuphold (negedge C, negedge S &&& (s_c_enable1_n!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_s);
$setuphold (negedge C, posedge CE &&& (ce_c_enable1_n!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_ce);
$setuphold (negedge C, posedge D &&& (d_c_enable1_n!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_d);
$setuphold (negedge C, posedge R &&& (r_c_enable1_n!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_r);
$setuphold (negedge C, posedge S &&& (s_c_enable1_n!=0), 0:0:0, 0:0:0, notifier2, , , delay_c, delay_s);
$setuphold (posedge C, negedge CE &&& (ce_c_enable1_p!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_ce);
$setuphold (posedge C, negedge D &&& (d_c_enable1_p!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_d);
$setuphold (posedge C, negedge R &&& (r_c_enable1_p!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_r);
$setuphold (posedge C, negedge S &&& (s_c_enable1_p!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_s);
$setuphold (posedge C, posedge CE &&& (ce_c_enable1_p!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_ce);
$setuphold (posedge C, posedge D &&& (d_c_enable1_p!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_d);
$setuphold (posedge C, posedge R &&& (r_c_enable1_p!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_r);
$setuphold (posedge C, posedge S &&& (s_c_enable1_p!=0), 0:0:0, 0:0:0, notifier1, , , delay_c, delay_s);
$width (negedge C, 0:0:0, 0, notifier);
$width (negedge R, 0:0:0, 0, notifier);
$width (negedge S, 0:0:0, 0, notifier);
$width (posedge C, 0:0:0, 0, notifier);
$width (posedge R, 0:0:0, 0, notifier);
$width (posedge S, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule // IDDR
`endcelldefine
|
/*
Copyright (c) 2015-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream XGMII frame receiver (XGMII in, AXI out)
*/
module axis_xgmii_rx_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_WIDTH = 96,
parameter USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1
)
(
input wire clk,
input wire rst,
/*
* XGMII input
*/
input wire [DATA_WIDTH-1:0] xgmii_rxd,
input wire [CTRL_WIDTH-1:0] xgmii_rxc,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
output wire m_axis_tlast,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* PTP
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
/*
* Status
*/
output wire [1:0] start_packet,
output wire error_bad_frame,
output wire error_bad_fcs
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH || CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
end
localparam [7:0]
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
localparam [7:0]
XGMII_IDLE = 8'h07,
XGMII_START = 8'hfb,
XGMII_TERM = 8'hfd,
XGMII_ERROR = 8'hfe;
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_PAYLOAD = 2'd1,
STATE_LAST = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg update_crc_last;
reg [7:0] last_cycle_tkeep_reg = 8'd0, last_cycle_tkeep_next;
reg lanes_swapped = 1'b0;
reg [31:0] swap_rxd = 32'd0;
reg [3:0] swap_rxc = 4'd0;
reg [DATA_WIDTH-1:0] xgmii_rxd_d0 = {DATA_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] xgmii_rxd_d1 = {DATA_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] xgmii_rxd_crc = {DATA_WIDTH{1'b0}};
reg [CTRL_WIDTH-1:0] xgmii_rxc_d0 = {CTRL_WIDTH{1'b0}};
reg [CTRL_WIDTH-1:0] xgmii_rxc_d1 = {CTRL_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}, m_axis_tdata_next;
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}, m_axis_tkeep_next;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0, m_axis_tlast_next;
reg m_axis_tuser_reg = 1'b0, m_axis_tuser_next;
reg [1:0] start_packet_reg = 2'b00;
reg error_bad_frame_reg = 1'b0, error_bad_frame_next;
reg error_bad_fcs_reg = 1'b0, error_bad_fcs_next;
reg [PTP_TS_WIDTH-1:0] ptp_ts_reg = 0;
reg [31:0] crc_state = 32'hFFFFFFFF;
reg [31:0] crc_state3 = 32'hFFFFFFFF;
wire [31:0] crc_next0;
wire [31:0] crc_next1;
wire [31:0] crc_next2;
wire [31:0] crc_next3;
wire [31:0] crc_next7;
wire crc_valid0 = crc_next0 == ~32'h2144df1c;
wire crc_valid1 = crc_next1 == ~32'h2144df1c;
wire crc_valid2 = crc_next2 == ~32'h2144df1c;
wire crc_valid3 = crc_next3 == ~32'h2144df1c;
wire crc_valid7 = crc_next7 == ~32'h2144df1c;
reg crc_valid7_save = 1'b0;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = m_axis_tkeep_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tuser = PTP_TS_ENABLE ? {ptp_ts_reg, m_axis_tuser_reg} : m_axis_tuser_reg;
assign start_packet = start_packet_reg;
assign error_bad_frame = error_bad_frame_reg;
assign error_bad_fcs = error_bad_fcs_reg;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(xgmii_rxd_crc[7:0]),
.state_in(crc_state3),
.data_out(),
.state_out(crc_next0)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(16),
.STYLE("AUTO")
)
eth_crc_16 (
.data_in(xgmii_rxd_crc[15:0]),
.state_in(crc_state3),
.data_out(),
.state_out(crc_next1)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(24),
.STYLE("AUTO")
)
eth_crc_24 (
.data_in(xgmii_rxd_crc[23:0]),
.state_in(crc_state3),
.data_out(),
.state_out(crc_next2)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_32 (
.data_in(xgmii_rxd_crc[31:0]),
.state_in(crc_state3),
.data_out(),
.state_out(crc_next3)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(64),
.STYLE("AUTO")
)
eth_crc_64 (
.data_in(xgmii_rxd_crc[63:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next7)
);
// detect control characters
reg [7:0] detect_term = 8'd0;
reg [7:0] detect_term_save = 8'd0;
integer i;
// mask errors to within packet
reg [7:0] control_masked;
reg [7:0] tkeep_mask;
always @* begin
casez (detect_term)
8'b00000000: begin
control_masked = xgmii_rxc_d0;
tkeep_mask = 8'b11111111;
end
8'bzzzzzzz1: begin
control_masked = 0;
tkeep_mask = 8'b00000000;
end
8'bzzzzzz10: begin
control_masked = xgmii_rxc_d0[0];
tkeep_mask = 8'b00000001;
end
8'bzzzzz100: begin
control_masked = xgmii_rxc_d0[1:0];
tkeep_mask = 8'b00000011;
end
8'bzzzz1000: begin
control_masked = xgmii_rxc_d0[2:0];
tkeep_mask = 8'b00000111;
end
8'bzzz10000: begin
control_masked = xgmii_rxc_d0[3:0];
tkeep_mask = 8'b00001111;
end
8'bzz100000: begin
control_masked = xgmii_rxc_d0[4:0];
tkeep_mask = 8'b00011111;
end
8'bz1000000: begin
control_masked = xgmii_rxc_d0[5:0];
tkeep_mask = 8'b00111111;
end
8'b10000000: begin
control_masked = xgmii_rxc_d0[6:0];
tkeep_mask = 8'b01111111;
end
default: begin
control_masked = xgmii_rxc_d0;
tkeep_mask = 8'b11111111;
end
endcase
end
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc_last = 1'b0;
last_cycle_tkeep_next = last_cycle_tkeep_reg;
m_axis_tdata_next = {DATA_WIDTH{1'b0}};
m_axis_tkeep_next = {KEEP_WIDTH{1'b1}};
m_axis_tvalid_next = 1'b0;
m_axis_tlast_next = 1'b0;
m_axis_tuser_next = 1'b0;
error_bad_frame_next = 1'b0;
error_bad_fcs_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for packet
reset_crc = 1'b1;
if (xgmii_rxc_d1[0] && xgmii_rxd_d1[7:0] == XGMII_START) begin
// start condition
if (control_masked) begin
// control or error characters in first data word
m_axis_tdata_next = {DATA_WIDTH{1'b0}};
m_axis_tkeep_next = 8'h01;
m_axis_tvalid_next = 1'b1;
m_axis_tlast_next = 1'b1;
m_axis_tuser_next = 1'b1;
error_bad_frame_next = 1'b1;
state_next = STATE_IDLE;
end else begin
reset_crc = 1'b0;
state_next = STATE_PAYLOAD;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// read payload
m_axis_tdata_next = xgmii_rxd_d1;
m_axis_tkeep_next = {KEEP_WIDTH{1'b1}};
m_axis_tvalid_next = 1'b1;
m_axis_tlast_next = 1'b0;
m_axis_tuser_next = 1'b0;
last_cycle_tkeep_next = {4'b0000, tkeep_mask[7:4]};
if (control_masked) begin
// control or error characters in packet
m_axis_tlast_next = 1'b1;
m_axis_tuser_next = 1'b1;
error_bad_frame_next = 1'b1;
reset_crc = 1'b1;
state_next = STATE_IDLE;
end else if (detect_term) begin
if (detect_term[4:0]) begin
// end this cycle
reset_crc = 1'b1;
m_axis_tkeep_next = {tkeep_mask[3:0], 4'b1111};
m_axis_tlast_next = 1'b1;
if ((detect_term[0] && crc_valid7_save) ||
(detect_term[1] && crc_valid0) ||
(detect_term[2] && crc_valid1) ||
(detect_term[3] && crc_valid2) ||
(detect_term[4] && crc_valid3)) begin
// CRC valid
end else begin
m_axis_tuser_next = 1'b1;
error_bad_frame_next = 1'b1;
error_bad_fcs_next = 1'b1;
end
state_next = STATE_IDLE;
end else begin
// need extra cycle
update_crc_last = 1'b1;
state_next = STATE_LAST;
end
end else begin
state_next = STATE_PAYLOAD;
end
end
STATE_LAST: begin
// last cycle of packet
m_axis_tdata_next = xgmii_rxd_d1;
m_axis_tkeep_next = last_cycle_tkeep_reg;
m_axis_tvalid_next = 1'b1;
m_axis_tlast_next = 1'b1;
m_axis_tuser_next = 1'b0;
reset_crc = 1'b1;
if ((detect_term_save[5] && crc_valid0) ||
(detect_term_save[6] && crc_valid1) ||
(detect_term_save[7] && crc_valid2)) begin
// CRC valid
end else begin
m_axis_tuser_next = 1'b1;
error_bad_frame_next = 1'b1;
error_bad_fcs_next = 1'b1;
end
if (xgmii_rxc_d1[0] && xgmii_rxd_d1[7:0] == XGMII_START) begin
// start condition
if (control_masked) begin
// control or error characters in first data word
m_axis_tdata_next = {DATA_WIDTH{1'b0}};
m_axis_tkeep_next = 8'h01;
m_axis_tvalid_next = 1'b1;
m_axis_tlast_next = 1'b1;
m_axis_tuser_next = 1'b1;
error_bad_frame_next = 1'b1;
state_next = STATE_IDLE;
end else begin
reset_crc = 1'b0;
state_next = STATE_PAYLOAD;
end
end else begin
state_next = STATE_IDLE;
end
end
endcase
end
always @(posedge clk) begin
state_reg <= state_next;
m_axis_tdata_reg <= m_axis_tdata_next;
m_axis_tkeep_reg <= m_axis_tkeep_next;
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tlast_reg <= m_axis_tlast_next;
m_axis_tuser_reg <= m_axis_tuser_next;
start_packet_reg <= 2'b00;
error_bad_frame_reg <= error_bad_frame_next;
error_bad_fcs_reg <= error_bad_fcs_next;
last_cycle_tkeep_reg <= last_cycle_tkeep_next;
detect_term_save <= detect_term;
swap_rxd <= xgmii_rxd[63:32];
swap_rxc <= xgmii_rxc[7:4];
if (PTP_TS_WIDTH == 96 && $signed({1'b0, ptp_ts_reg[45:16]}) - $signed(31'd1000000000) > 0) begin
// ns field rollover
ptp_ts_reg[45:16] <= $signed({1'b0, ptp_ts_reg[45:16]}) - $signed(31'd1000000000);
ptp_ts_reg[95:48] <= ptp_ts_reg[95:48] + 1;
end
if (xgmii_rxc[0] && xgmii_rxd[7:0] == XGMII_START) begin
lanes_swapped <= 1'b0;
start_packet_reg <= 2'b01;
xgmii_rxd_d0 <= xgmii_rxd;
xgmii_rxd_crc <= xgmii_rxd;
xgmii_rxc_d0 <= xgmii_rxc;
for (i = 0; i < 8; i = i + 1) begin
detect_term[i] <= xgmii_rxc[i] && (xgmii_rxd[i*8 +: 8] == XGMII_TERM);
end
if (PTP_TS_WIDTH == 96) begin
ptp_ts_reg[45:0] <= ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
ptp_ts_reg[95:48] <= ptp_ts[95:48];
end else begin
ptp_ts_reg <= ptp_ts + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
end
end else if (xgmii_rxc[4] && xgmii_rxd[39:32] == XGMII_START) begin
lanes_swapped <= 1'b1;
start_packet_reg <= 2'b10;
xgmii_rxd_d0 <= {xgmii_rxd[31:0], swap_rxd};
xgmii_rxd_crc <= {xgmii_rxd[31:0], swap_rxd};
xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc};
for (i = 0; i < 4; i = i + 1) begin
detect_term[i] <= swap_rxc[i] && (swap_rxd[i*8 +: 8] == XGMII_TERM);
detect_term[i+4] <= xgmii_rxc[i] && (xgmii_rxd[i*8 +: 8] == XGMII_TERM);
end
if (PTP_TS_WIDTH == 96) begin
ptp_ts_reg[45:0] <= ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
ptp_ts_reg[95:48] <= ptp_ts[95:48];
end else begin
ptp_ts_reg <= ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
end
end else if (lanes_swapped) begin
xgmii_rxd_d0 <= {xgmii_rxd[31:0], swap_rxd};
xgmii_rxd_crc <= {xgmii_rxd[31:0], swap_rxd};
xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc};
for (i = 0; i < 4; i = i + 1) begin
detect_term[i] <= swap_rxc[i] && (swap_rxd[i*8 +: 8] == XGMII_TERM);
detect_term[i+4] <= xgmii_rxc[i] && (xgmii_rxd[i*8 +: 8] == XGMII_TERM);
end
end else begin
xgmii_rxd_d0 <= xgmii_rxd;
xgmii_rxd_crc <= xgmii_rxd;
xgmii_rxc_d0 <= xgmii_rxc;
for (i = 0; i < 8; i = i + 1) begin
detect_term[i] <= xgmii_rxc[i] && (xgmii_rxd[i*8 +: 8] == XGMII_TERM);
end
end
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
end else begin
crc_state <= crc_next7;
end
if (update_crc_last) begin
crc_state3 <= crc_next3;
end else begin
crc_state3 <= crc_next7;
end
crc_valid7_save <= crc_valid7;
if (state_next == STATE_LAST) begin
xgmii_rxd_crc[31:0] <= xgmii_rxd_crc[63:32];
end
xgmii_rxd_d1 <= xgmii_rxd_d0;
xgmii_rxc_d1 <= xgmii_rxc_d0;
if (rst) begin
state_reg <= STATE_IDLE;
m_axis_tvalid_reg <= 1'b0;
start_packet_reg <= 2'b00;
error_bad_frame_reg <= 1'b0;
error_bad_fcs_reg <= 1'b0;
crc_state <= 32'hFFFFFFFF;
crc_state3 <= 32'hFFFFFFFF;
xgmii_rxc_d0 <= {CTRL_WIDTH{1'b0}};
xgmii_rxc_d1 <= {CTRL_WIDTH{1'b0}};
lanes_swapped <= 1'b0;
end
end
endmodule
`resetall
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_s_w_channel.v
// Version : v1.0
// Description: slave interface write channel.Write requests are processed
// to write to target location.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
//Specific WARNINGs moved to INFO by Vivado Synthesis Tool
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_s_w_channel #(
parameter C_BASEADDR = 32'hffffffff,
parameter C_HIGHADDR = 32'h00000000,
parameter C_S_AXI_ID_WIDTH = 1 ,
parameter C_S_AXI_DATA_WIDTH = 32 ,
parameter C_S_AXI_AWUSER_WIDTH = 8 ,
parameter C_ZERO_INVALID = 1 ,
parameter C_NO_EXCL = 0 ,
parameter C_ATG_BASIC_AXI4 = 1 ,
parameter C_ATG_AXI4LITE = 0
) (
// system
input Clk ,
input rst_l ,
// AW
input [C_S_AXI_ID_WIDTH-1:0] awid_s ,
input [31:0] awaddr_s ,
input [7:0] awlen_s ,
input [2:0] awsize_s ,
input [1:0] awburst_s ,
input [0:0] awlock_s ,
input [3:0] awcache_s ,
input [2:0] awprot_s ,
input [3:0] awqos_s ,
input [C_S_AXI_AWUSER_WIDTH-1:0] awuser_s ,
input awvalid_s ,
output awready_s ,
// W
input wlast_s ,
input [C_S_AXI_DATA_WIDTH-1:0] wdata_s ,
input [C_S_AXI_DATA_WIDTH/8-1:0] wstrb_s ,
input wvalid_s ,
output wready_s ,
//B
output [C_S_AXI_ID_WIDTH-1:0] bid_s ,
output [1:0] bresp_s ,
output bvalid_s ,
input bready_s ,
// Register module
input reg1_disallow_excl ,
input reg1_sgl_slv_wr ,
input reg1_wrs_block_rds ,
output [15:0] err_new_slv ,
output [15:0] wr_reg_decode ,
output [31:0] wr_reg_data ,
// sr channel
input [71:0] slv_ex_info0_ff ,
output reg slv_ex_valid0_ff ,
input[71:0] slv_ex_info1_ff ,
output reg slv_ex_valid1_ff ,
input slv_ex_new_valid0 ,
input slv_ex_new_valid1 ,
input [15:0] ar_agen_addr ,
output [C_S_AXI_DATA_WIDTH-1:0] slvram_rd_out ,
//slvram
input [63:0] sram_rd_data_a ,
output [10:0] slvram_waddr_ff ,
output [7:0] slvram_we_ff ,
output [63:0] slvram_write_data_ff,
//axi_traffic_gen_v2_0_cmdram
output [15:0] aw_agen_addr ,
output [15:0] cmdram_we ,
output [64-1:0] slvram_wr_data ,
//paramram
output awfifo_valid ,
output [71:0] awfifo_out ,
output wfifo_valid ,
output [C_S_AXI_DATA_WIDTH*9/8+1-1:0] wfifo_out
);
wire [31:0] base_addr = C_BASEADDR;
wire [31:0] high_addr = C_HIGHADDR;
wire [31:0] addr_mask = base_addr[31:0] ^ high_addr[31:0];
//wire [7:0] awlen8_s = awlen_s[7:0] | { 4'h0, awlen3_s[3:0] };
wire [7:0] awlen8_s = awlen_s[7:0] | { 4'h0, 4'h0 };
wire [15:0] awbuf_id = awid_s[C_S_AXI_ID_WIDTH-1:0];
wire [31:0] aw_addr_masked = awaddr_s[31:0] & addr_mask[31:0];
//Address re-mapped
//wire aw_isslvram = ((aw_addr_masked[22:16] != 'h0 ));
wire aw_isslvram = ((aw_addr_masked[15:14]==2'b11));
wire aw_iscmd = ~aw_isslvram && awaddr_s[15];
wire [71:0] awbuf_rawdata = {
awbuf_id[15:0], //71:56
aw_isslvram, aw_iscmd, awprot_s[2:0], awsize_s[2:0], //55:48
awburst_s[1:0], 1'b0,awlock_s[0:0], awcache_s[3:0], //47:40 //awlock made 1-bit
awlen8_s[7:0], //39:32
awaddr_s[31:0] }; //31:0
wire awbuf_valid = awvalid_s && awready_s;
wire awfifo_notfull;
wire aw_agen_write;
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (72),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.FULL_LEVEL(6 )
) Awfifo (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (awbuf_rawdata[71:0]),
.in_push (awbuf_valid ),
.in_pop (aw_agen_write ),
.out_data (awfifo_out[71:0] ),
.is_full ( ),
.is_notfull (awfifo_notfull ),
.is_empty ( ),
.out_valid (awfifo_valid ),
.ex_fifo_dbgout ( )
);
assign awready_s = awfifo_notfull;
wire [15:0] aw_agen_id;
wire [C_S_AXI_DATA_WIDTH/8-1:0] aw_agen_be;
wire aw_agen_pop;
wire aw_agen_done;
wire aw_agen_valid;
wire awfifo_out_is_excl ;
wire aw_agen_pause = awfifo_valid && awfifo_out_is_excl && aw_agen_valid;
assign aw_agen_write = awfifo_valid && ~aw_agen_valid && ~aw_agen_pause;
wire [71:0] slv_ex_wr_info ;
wire slv_ex_addr_matches0 ;
wire slv_ex_id_matches0 ;
wire slv_ex_wr_matches0 ;
wire slv_ex_addr_matches1 ;
wire slv_ex_id_matches1 ;
wire slv_ex_wr_matches1 ;
wire slv_ex_wr_matches ;
wire [1:0] awfifo_out_excl ;
wire awfifo_out_null ;
wire aw_err ;
generate if(C_NO_EXCL == 0 ) begin : S_W_EXCL_0
assign awfifo_out_is_excl = (awfifo_out[45:44] == 2'b01);
assign slv_ex_wr_info = awfifo_out[71:0];
assign slv_ex_addr_matches0 = (slv_ex_wr_info[19:7] == slv_ex_info0_ff[19:7]);
assign slv_ex_id_matches0 = (slv_ex_wr_info[71:56] == slv_ex_info0_ff[71:56]);
assign slv_ex_wr_matches0 = (slv_ex_wr_info[55:20] ==slv_ex_info0_ff[55:20]) &&
(slv_ex_wr_info[6:0] == slv_ex_info0_ff[6:0]) &&
slv_ex_addr_matches0 && slv_ex_id_matches0 &&
slv_ex_valid0_ff;
assign slv_ex_addr_matches1 = (slv_ex_wr_info[19:7] == slv_ex_info1_ff[19:7]);
assign slv_ex_id_matches1 = (slv_ex_wr_info[71:56] == slv_ex_info1_ff[71:56]);
assign slv_ex_wr_matches1 = (slv_ex_wr_info[55:20] ==slv_ex_info1_ff[55:20]) &&
(slv_ex_wr_info[6:0] == slv_ex_info1_ff[6:0]) &&
slv_ex_addr_matches1 && slv_ex_id_matches1 &&
slv_ex_valid1_ff;
assign slv_ex_wr_matches = (C_NO_EXCL) ? 1'b0 :
slv_ex_wr_matches0 || slv_ex_wr_matches1;
assign awfifo_out_excl = (awfifo_out_is_excl && slv_ex_wr_matches) ? 2'b01 :
2'b00;
assign awfifo_out_null = aw_err ||
(awfifo_out_is_excl && ~reg1_disallow_excl &&
~slv_ex_wr_matches && (C_NO_EXCL == 0));
end
endgenerate
generate if(C_NO_EXCL == 1) begin : S_W_EXCL_1
assign awfifo_out_is_excl = 2'b00;
assign slv_ex_wr_matches = 1'b0 ;
assign awfifo_out_excl = 2'b00;
assign awfifo_out_null = aw_err ;
end
endgenerate
assign aw_err = (awfifo_out[55:54] == 2'b00) && (awfifo_out[5:2] == 4'hd) &&
awfifo_out[7] && ~awfifo_out[12];
// writing to reg13, at 0xb4
// and not 0x1XXX (for special queue ops)
wire [1:0] awfifo_out_resp = (reg1_disallow_excl) ? 2'b00 :
(aw_err) ? 2'b10 : awfifo_out_excl[1:0];
axi_traffic_gen_v2_0_addrgen #(
.USE_ADDR_OFFSET (0) ,
.C_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.IS_READ (0) ,
.C_ATG_BASIC_AXI4(C_ATG_BASIC_AXI4) ,
.C_ATG_AXI4LITE (C_ATG_AXI4LITE)
) Aw_agen (
.Clk (Clk ),
.rst_l (rst_l ),
.in_addr ({awfifo_out[55:54], awfifo_out[13:0]} ),
.in_addr_offset(awfifo_out[8:0] ),
.in_id ({ awfifo_out_resp[1:0], awfifo_out_null, awfifo_out[68:56]}),
.in_len (awfifo_out[39:32] ),
.in_size (awfifo_out[50:48] ),
.in_lastaddr (6'b000000 ),
.in_burst (awfifo_out[47:46] ),
.in_push (aw_agen_write ),
.in_pop (aw_agen_pop ),
.in_user (1'b0 ),
.out_user ( ),
.out_addr (aw_agen_addr[15:0] ),
.out_id (aw_agen_id[15:0] ),
.out_be (aw_agen_be[C_S_AXI_DATA_WIDTH/8-1:0] ),
.out_done (aw_agen_done ),
.out_valid (aw_agen_valid )
);
wire slv_ex_agen_id_matches0 ;
wire slv_ex_clr_valid0 ;
wire slv_ex_valid0 ;
wire slv_ex_agen_id_matches1 ;
wire slv_ex_clr_valid1 ;
wire slv_ex_valid1 ;
generate if(C_NO_EXCL == 0 ) begin : S_W1_EXCL_0
assign slv_ex_agen_id_matches0 = (aw_agen_id[13:0] == slv_ex_info0_ff[69:56]);
assign slv_ex_clr_valid0 = aw_agen_valid &&
(aw_agen_addr[13:3] == slv_ex_info0_ff[13:3]) &&
~slv_ex_agen_id_matches0 && ~aw_agen_id[13];
// Don't clear if its from the ex master, or if the write is
// nullified (aw_agen_id[13]).
assign slv_ex_valid0 = (C_NO_EXCL) ? 1'b0 :
slv_ex_new_valid0 || (~slv_ex_clr_valid0 && slv_ex_valid0_ff);
assign slv_ex_agen_id_matches1 = (aw_agen_id[13:0] == slv_ex_info1_ff[69:56]);
assign slv_ex_clr_valid1 = aw_agen_valid &&
(aw_agen_addr[13:3] == slv_ex_info1_ff[13:3]) &&
~slv_ex_agen_id_matches1 && ~aw_agen_id[13];
// Don't clear if its from the ex master, or if the write is
// nullified (aw_agen_id[13]).
assign slv_ex_valid1 = (C_NO_EXCL) ? 1'b0 :
slv_ex_new_valid1 || (~slv_ex_clr_valid1 && slv_ex_valid1_ff);
end
endgenerate
generate if(C_NO_EXCL == 1 ) begin : S_W1_EXCL_1
assign slv_ex_valid0 = 1'b0 ;
assign slv_ex_valid1 = 1'b0 ;
end
endgenerate
// Buffer write data in a fifo
wire wbuf_valid = wvalid_s && wready_s;
wire wbuf_pop;
wire wfifo_notfull;
//wire wfifo_valid;
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (C_S_AXI_DATA_WIDTH*9/8+1),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.FULL_LEVEL(6 )
) Wfifo (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data({ wlast_s, wstrb_s[C_S_AXI_DATA_WIDTH/8-1:0],
wdata_s[C_S_AXI_DATA_WIDTH-1:0] }),
.in_push (wbuf_valid ),
.in_pop (wbuf_pop ),
.out_data (wfifo_out[C_S_AXI_DATA_WIDTH*9/8+1-1:0] ),
.is_full ( ),
.is_notfull (wfifo_notfull ),
.is_empty ( ),
.out_valid (wfifo_valid ),
.ex_fifo_dbgout ( )
);
assign wready_s = wfifo_notfull;
// Buffer bresps in fifos as well
wire [15:0] bbuf_id = aw_agen_id[15:0];
wire [1:0] bbuf_resp = aw_agen_id[15:14];
wire [19:0] bbuf_rawdata = {
bbuf_id[15:0], //19:4
2'b00, bbuf_resp[1:0] }; //3:0
wire [3:0] btrk_fifo_num, btrk_free;
wire bfifo0_pop, bfifo1_pop, bfifo2_pop, bfifo3_pop;
wire bfifo0_notfull, bfifo1_notfull, bfifo2_notfull, bfifo3_notfull;
wire bfifo0_valid, bfifo1_valid, bfifo2_valid, bfifo3_valid;
wire [19:0] bfifo0_out, bfifo1_out, bfifo2_out, bfifo3_out;
wire [C_S_AXI_ID_WIDTH-1:0] btrk_in_push_id = bbuf_rawdata[19:0];
wire [3:0] b_fifo_valid = { bfifo3_valid, bfifo2_valid,
bfifo1_valid, bfifo0_valid };
wire [3:0] b_fifo_push = ~b_fifo_valid[3:0] & btrk_fifo_num[3:0];
wire [3:0] btrk_clear_pos = ~b_fifo_valid[3:0];
wire btrk_push = aw_agen_pop && aw_agen_done;
wire [C_S_AXI_ID_WIDTH-1:0] dummy_search_id = 32'h0;
wire dis_dis_out_of_order;
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_S_W_OOO_YES
assign dis_dis_out_of_order = 1'b0;
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_S_W_OOO_NO
assign dis_dis_out_of_order = 1'b1;
end
endgenerate
axi_traffic_gen_v2_0_id_track #(
.ID_WIDTH(C_S_AXI_ID_WIDTH)
) B_track (
.Clk (Clk ),
.rst_l (rst_l ),
.in_push_id (btrk_in_push_id[C_S_AXI_ID_WIDTH-1:0]),
.in_push (btrk_push ),
.in_search_id (dummy_search_id[C_S_AXI_ID_WIDTH-1:0]),
.in_clear_pos (btrk_clear_pos[3:0] ),
.in_only_entry0(dis_dis_out_of_order ),
.out_push_pos (btrk_fifo_num[3:0] ),
.out_search_hit( ),
.out_free (btrk_free[3:0] )
);
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (20),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (0 ),
.FULL_LEVEL(6 )
) B_fifo0 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (bbuf_rawdata[19:0]),
.in_push (btrk_fifo_num[0] ),
.in_pop (bfifo0_pop ),
.out_data (bfifo0_out[19:0] ),
.is_full ( ),
.is_notfull (bfifo0_notfull ),
.is_empty ( ),
.out_valid (bfifo0_valid ),
.ex_fifo_dbgout ( )
);
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_S_W_OOO_F_NO
assign bfifo1_notfull = 1'b1;
assign bfifo1_valid = 1'b0;
assign bfifo2_notfull = 1'b1;
assign bfifo2_valid = 1'b0;
assign bfifo3_notfull = 1'b1;
assign bfifo3_valid = 1'b0;
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_S_W_OOO_F_YES
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (20),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (0 ),
.FULL_LEVEL(6 )
) B_fifo1 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (bbuf_rawdata[19:0]),
.in_push (btrk_fifo_num[1] ),
.in_pop (bfifo1_pop ),
.out_data (bfifo1_out[19:0] ),
.is_full ( ),
.is_notfull (bfifo1_notfull ),
.is_empty ( ),
.out_valid (bfifo1_valid ),
.ex_fifo_dbgout ( )
);
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (20),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (0 ),
.FULL_LEVEL(6 )
) B_fifo2 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (bbuf_rawdata[19:0]),
.in_push (btrk_fifo_num[2] ),
.in_pop (bfifo2_pop ),
.out_data (bfifo2_out[19:0] ),
.is_full ( ),
.is_notfull (bfifo2_notfull ),
.is_empty ( ),
.out_valid (bfifo2_valid ),
.ex_fifo_dbgout ( )
);
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (20),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (0 ),
.FULL_LEVEL(6 )
) B_fifo3 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (bbuf_rawdata[19:0]),
.in_push (btrk_fifo_num[3] ),
.in_pop (bfifo3_pop ),
.out_data (bfifo3_out[19:0] ),
.is_full ( ),
.is_notfull (bfifo3_notfull ),
.is_empty ( ),
.out_valid (bfifo3_valid ),
.ex_fifo_dbgout ( )
);
end
endgenerate
wire [19:0] bfifo_out;
wire bfifo_valid;
wire bfifo_notfull;
wire [3:0] bfifo_sel = (bfifo3_valid) ? 4'h8 :
(bfifo2_valid) ? 4'h4 :
(bfifo1_valid) ? 4'h2 :
(bfifo0_valid) ? 4'h1 : 4'h0;
assign bfifo0_pop = bfifo_notfull && bfifo_sel[0];
assign bfifo1_pop = bfifo_notfull && bfifo_sel[1];
assign bfifo2_pop = bfifo_notfull && bfifo_sel[2];
assign bfifo3_pop = bfifo_notfull && bfifo_sel[3];
wire [19:0] bfifo_in_data ;
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_S_W1_OOO_YES
assign bfifo_in_data = ((bfifo_sel[0]) ? bfifo0_out[19:0] : 20'h0) |
((bfifo_sel[1]) ? bfifo1_out[19:0] : 20'h0) |
((bfifo_sel[2]) ? bfifo2_out[19:0] : 20'h0) |
((bfifo_sel[3]) ? bfifo3_out[19:0] : 20'h0);
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_S_W1_OOO_NO
assign bfifo_in_data = ((bfifo_sel[0]) ? bfifo0_out[19:0] : 20'h0) ;
end
endgenerate
wire bfifo_pop = bfifo_valid && bready_s;
wire bfifo_push = bfifo_notfull && (bfifo_sel[3:0] != 4'h0);
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (20 ),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.ZERO_INVALID(C_ZERO_INVALID),
.FULL_LEVEL (6 )
) Bfifo (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (bfifo_in_data[19:0]),
.in_push (bfifo_push ),
.in_pop (bfifo_pop ),
.out_data (bfifo_out[19:0] ),
.is_full ( ),
.is_notfull (bfifo_notfull ),
.is_empty ( ),
.out_valid (bfifo_valid ),
.ex_fifo_dbgout ( )
);
assign wbuf_pop = wfifo_valid && aw_agen_valid &&
bfifo0_notfull && bfifo1_notfull && bfifo2_notfull &&
bfifo3_notfull && (btrk_free[3:0] != 4'h0);
assign aw_agen_pop = wbuf_pop;
wire wfifo_bad_last = wbuf_pop && (aw_agen_done != wfifo_out[C_S_AXI_DATA_WIDTH*9/8]);
wire [C_S_AXI_DATA_WIDTH/8-1:0] wfifo_out_be =
wfifo_out[C_S_AXI_DATA_WIDTH*9/8-1:C_S_AXI_DATA_WIDTH];
wire wfifo_bad_be_pre = (~aw_agen_be[C_S_AXI_DATA_WIDTH/8-1:0] &
wfifo_out_be[C_S_AXI_DATA_WIDTH/8-1:0]) != 8'h0;
wire wfifo_bad_be = wbuf_pop && wfifo_bad_be_pre;
assign bresp_s[1:0] = bfifo_out[1:0];
assign bid_s[C_S_AXI_ID_WIDTH-1:0] = bfifo_out[19:4];
assign bvalid_s = bfifo_valid;
wire slv_wr_pending = awfifo_valid || aw_agen_valid;
always @(posedge Clk) begin
slv_ex_valid0_ff <= (rst_l) ? slv_ex_valid0 : 1'b0;
slv_ex_valid1_ff <= (rst_l) ? slv_ex_valid1 : 1'b0;
end
//register interface information
wire wr_reg_isreg = (aw_agen_addr[15:14] == 2'b00) && aw_agen_pop &&
~aw_agen_addr[7]
&& ~aw_agen_addr[12]; // adding this for special_queue
assign wr_reg_decode = { 15'h0, wr_reg_isreg } << aw_agen_addr[5:2];
wire [11:0] wr_reg_shift = (C_S_AXI_DATA_WIDTH == 32) ? 12'h0 :
(C_S_AXI_DATA_WIDTH == 64) ? { 6'h0, aw_agen_addr[2], 5'h0 } :
(C_S_AXI_DATA_WIDTH == 128) ? { 5'h0, aw_agen_addr[3:2], 5'h0 }:
{ 4'h0, aw_agen_addr[4:2], 5'h0 };
assign wr_reg_data = wfifo_out[C_S_AXI_DATA_WIDTH-1:0] >>
wr_reg_shift[11:0];
//slv/mst ram decode
wire slvram_do_write = wbuf_pop && aw_agen_addr[15] && ~aw_agen_id[13];
wire [7:0] slvram_we = (slvram_do_write) ?
{4'h0,wfifo_out_be[C_S_AXI_DATA_WIDTH/8-1:0]} : 'h0;
assign slvram_wr_data = (C_S_AXI_DATA_WIDTH == 64) ? wfifo_out[C_S_AXI_DATA_WIDTH-1:0] :
{2{wfifo_out[C_S_AXI_DATA_WIDTH-1:0]}};
wire [63:0] slvram_rd_out_pre;
assign slvram_rd_out_pre[63:0] = sram_rd_data_a;
reg [63:0] slvram_wr_data64_ff;
reg [7:0] slvram_rdwr_mask8_ff;
reg [C_S_AXI_DATA_WIDTH-1:0] slvram_wr_datareg_ff;
reg [31:0] slvram_rdwr_mask_ff;
wire [13:0] rdwr_match_mask =
(C_S_AXI_DATA_WIDTH == 256) ? 14'h3fe0 :
(C_S_AXI_DATA_WIDTH == 128) ? 14'h1ff0 :
(C_S_AXI_DATA_WIDTH == 64) ? 14'h1ffe : 14'h1ffc;
wire slvram_rdwr_match = slvram_do_write &&
((ar_agen_addr[13:0] & rdwr_match_mask[13:0]) ==
(aw_agen_addr[13:0] & rdwr_match_mask[13:0]));
wire [C_S_AXI_DATA_WIDTH-1:0] slvram_wr_datareg = (slvram_rdwr_match) ?
slvram_wr_data[C_S_AXI_DATA_WIDTH-1:0] :
slvram_wr_datareg_ff[C_S_AXI_DATA_WIDTH-1:0];
wire [31:0] slvram_rdwr_mask = (slvram_rdwr_match) ?
wfifo_out_be[C_S_AXI_DATA_WIDTH/8-1:0] : 'h0;
wire [C_S_AXI_DATA_WIDTH-1:0] slvram_rdwr_mask_exp = {
{ 8 { slvram_rdwr_mask_ff[31] } }, { 8 { slvram_rdwr_mask_ff[30] } },
{ 8 { slvram_rdwr_mask_ff[29] } }, { 8 { slvram_rdwr_mask_ff[28] } },
{ 8 { slvram_rdwr_mask_ff[27] } }, { 8 { slvram_rdwr_mask_ff[26] } },
{ 8 { slvram_rdwr_mask_ff[25] } }, { 8 { slvram_rdwr_mask_ff[24] } },
{ 8 { slvram_rdwr_mask_ff[23] } }, { 8 { slvram_rdwr_mask_ff[22] } },
{ 8 { slvram_rdwr_mask_ff[21] } }, { 8 { slvram_rdwr_mask_ff[20] } },
{ 8 { slvram_rdwr_mask_ff[19] } }, { 8 { slvram_rdwr_mask_ff[18] } },
{ 8 { slvram_rdwr_mask_ff[17] } }, { 8 { slvram_rdwr_mask_ff[16] } },
{ 8 { slvram_rdwr_mask_ff[15] } }, { 8 { slvram_rdwr_mask_ff[14] } },
{ 8 { slvram_rdwr_mask_ff[13] } }, { 8 { slvram_rdwr_mask_ff[12] } },
{ 8 { slvram_rdwr_mask_ff[11] } }, { 8 { slvram_rdwr_mask_ff[10] } },
{ 8 { slvram_rdwr_mask_ff[9] } }, { 8 { slvram_rdwr_mask_ff[8] } },
{ 8 { slvram_rdwr_mask_ff[7] } }, { 8 { slvram_rdwr_mask_ff[6] } },
{ 8 { slvram_rdwr_mask_ff[5] } }, { 8 { slvram_rdwr_mask_ff[4] } },
{ 8 { slvram_rdwr_mask_ff[3] } }, { 8 { slvram_rdwr_mask_ff[2] } },
{ 8 { slvram_rdwr_mask_ff[1] } }, { 8 { slvram_rdwr_mask_ff[0] } } };
assign slvram_rd_out[C_S_AXI_DATA_WIDTH-1:0] =
(slvram_rdwr_mask_exp[C_S_AXI_DATA_WIDTH-1:0] &
slvram_wr_datareg_ff[C_S_AXI_DATA_WIDTH-1:0]) |
(~slvram_rdwr_mask_exp[C_S_AXI_DATA_WIDTH-1:0] &
slvram_rd_out_pre[C_S_AXI_DATA_WIDTH-1:0]);
always @(posedge Clk) begin
slvram_wr_datareg_ff[C_S_AXI_DATA_WIDTH-1:0] <= (rst_l) ?
slvram_wr_datareg[C_S_AXI_DATA_WIDTH-1:0] : 'h0;
slvram_rdwr_mask_ff[31:0] <= (rst_l) ? slvram_rdwr_mask[31:0] : 32'h0;
end
assign err_new_slv[15:0] = { 14'h0, wfifo_bad_be, wfifo_bad_last };
// adding sram regslice for timing closure
wire [82:0] sram_slvramwr_ff;
axi_traffic_gen_v2_0_regslice
#(
.DWIDTH (83),
.IDWIDTH (1) ,
.DATADEPTH(1 )
)
sram_slvramwr_regslice
(
.din ({aw_agen_addr[12:2],slvram_we,slvram_wr_data}),
.dout (sram_slvramwr_ff ),
.dout_early ( ),
.idin (1'b0 ),
.idout ( ),
.id_stable ( ),
.id_stable_ff( ),
.data_stable ( ),
.clk (Clk ),
.reset (~rst_l )
);
assign slvram_waddr_ff = sram_slvramwr_ff[82:72];
assign slvram_we_ff = sram_slvramwr_ff[71:64];
assign slvram_write_data_ff = sram_slvramwr_ff[63:0];
//cmdram decode
// sent out aw_agen_addr as output also.
// this is used along with ar_agen0_addr,maw_ptr_new,mar_ptr_new
// to select address to cmdram based on reg0_m_enable_ff
wire [31:0] cmdram_we32 = wfifo_out_be[C_S_AXI_DATA_WIDTH/8-1:0];
wire [3:0] cmdram_we4 ;
wire [7:0] cmdram_we8 ;
wire [7:0] cmdram_we_pre ;
generate if(C_S_AXI_DATA_WIDTH == 32) begin :CMD_WE_32
assign cmdram_we4 = cmdram_we32[31:28] | cmdram_we32[27:24] |
cmdram_we32[23:20] | cmdram_we32[19:16] |
cmdram_we32[15:12] | cmdram_we32[11:8] |
cmdram_we32[7:4] | cmdram_we32[3:0];
assign cmdram_we_pre = (wbuf_pop && aw_agen_addr[14]) ? cmdram_we4[3:0] :
4'h0;
assign cmdram_we =
(aw_agen_addr[3:2] == 2'b11) ? { cmdram_we_pre[3:0], 12'h0 } :
(aw_agen_addr[3:2] == 2'b10) ? { 4'h0, cmdram_we_pre[3:0], 8'h0 } :
(aw_agen_addr[3:2] == 2'b01) ? { 8'h0, cmdram_we_pre[3:0], 4'h0 } :
{ 12'h0, cmdram_we_pre[3:0] };
end
endgenerate
generate if(C_S_AXI_DATA_WIDTH == 64) begin :CMD_WE_64
assign cmdram_we8 = cmdram_we32[31:24] |
cmdram_we32[23:16] |
cmdram_we32[15:8] |
cmdram_we32[7:0] ;
assign cmdram_we_pre = (wbuf_pop && aw_agen_addr[14]) ? cmdram_we8[7:0] :
8'h0;
assign cmdram_we =
(aw_agen_addr[3] == 1'b1) ? { cmdram_we_pre[7:0], 8'h0 } :
{ 8'h0, cmdram_we_pre[7:0] };
end
endgenerate
endmodule
|
Require Import Verdi.Verdi.
Require Import Verdi.HandlerMonad.
Require Import StructTact.Fin.
Local Arguments update {_} {_} _ _ _ _ _ : simpl never.
Require Import Verdi.StatePacketPacketDecomposition.
Require Import Verdi.LabeledNet.
Require Import InfSeqExt.infseq.
Require Import InfSeqExt.classical.
Set Implicit Arguments.
Section LockServ.
Variable num_Clients : nat.
Definition Client_index := (fin num_Clients).
Inductive Name :=
| Client : Client_index -> Name
| Server : Name.
Definition list_Clients := map Client (all_fin num_Clients).
Definition Name_eq_dec : forall a b : Name, {a = b} + {a <> b}.
decide equality. apply fin_eq_dec.
Qed.
Inductive Msg :=
| Lock : Msg
| Unlock : Msg
| Locked : Msg.
Definition Msg_eq_dec : forall a b : Msg, {a = b} + {a <> b}.
decide equality.
Qed.
Definition Input := Msg.
Definition Output := Msg.
Record Data := mkData { queue : list Client_index ; held : bool }.
Definition init_data (n : Name) : Data := mkData [] false.
Inductive Label :=
| InputLock : Client_index -> Label
| InputUnlock : Client_index -> Label
| MsgUnlock : Label
| MsgLock : Client_index -> Label
| MsgLocked : Client_index -> Label
| Nop
| Silent.
Definition Handler (S : Type) := GenHandler (Name * Msg) S Output Label.
Definition ClientNetHandler (i : Client_index) (m : Msg) : Handler Data :=
match m with
| Locked => (put (mkData [] true)) ;; write_output Locked ;; ret (MsgLocked i)
| _ => ret Nop
end.
Definition ClientIOHandler (i : Client_index) (m : Msg) : Handler Data :=
match m with
| Lock => send (Server, Lock) ;; ret (InputLock i)
| Unlock => data <- get ;;
when (held data)
(put (mkData [] false) >>
send (Server, Unlock));;
ret (InputUnlock i)
| _ => ret Nop
end.
Definition ServerNetHandler (src : Name) (m : Msg) : Handler Data :=
st <- get ;;
let q := queue st in
match m with
| Lock =>
match src with
| Server => ret Nop
| Client c =>
when (null q) (send (src, Locked)) >> put (mkData (q++[c]) (held st)) >> ret (MsgLock c)
end
| Unlock => match q with
| _ :: x :: xs => put (mkData (x :: xs) (held st)) >> send (Client x, Locked)
| _ => put (mkData [] (held st))
end ;;
ret MsgUnlock
| _ => ret Nop
end.
Definition ServerIOHandler (m : Msg) : Handler Data := ret Nop.
Definition NetHandler (nm src : Name) (m : Msg) : Handler Data :=
match nm with
| Client c => ClientNetHandler c m
| Server => ServerNetHandler src m
end.
Definition InputHandler (nm : Name) (m : Msg) : Handler Data :=
match nm with
| Client c => ClientIOHandler c m
| Server => ServerIOHandler m
end.
Ltac handler_unfold :=
repeat (monad_unfold; unfold NetHandler,
InputHandler,
ServerNetHandler,
ClientNetHandler,
ClientIOHandler,
ServerIOHandler in *).
Definition Nodes := Server :: list_Clients.
Theorem In_n_Nodes :
forall n : Name, In n Nodes.
Proof using.
intros.
unfold Nodes, list_Clients.
simpl.
destruct n.
- right.
apply in_map.
apply all_fin_all.
- left.
reflexivity.
Qed.
Theorem nodup :
NoDup Nodes.
Proof using.
unfold Nodes, list_Clients.
apply NoDup_cons.
- in_crush. discriminate.
- apply NoDup_map_injective.
+ intros. congruence.
+ apply all_fin_NoDup.
Qed.
Global Instance LockServ_BaseParams : BaseParams :=
{
data := Data ;
input := Input ;
output := Output
}.
Global Instance LockServ_LabeledParams : LabeledMultiParams LockServ_BaseParams :=
{
lb_name := Name ;
lb_msg := Msg ;
lb_msg_eq_dec := Msg_eq_dec ;
lb_name_eq_dec := Name_eq_dec ;
lb_nodes := Nodes ;
lb_all_names_nodes := In_n_Nodes ;
lb_no_dup_nodes := nodup ;
label := Label ;
label_silent := Silent;
lb_init_handlers := init_data ;
lb_net_handlers := fun dst src msg s =>
runGenHandler s (NetHandler dst src msg) ;
lb_input_handlers := fun nm msg s =>
runGenHandler s (InputHandler nm msg)
}.
Global Instance LockServ_MultiParams : MultiParams LockServ_BaseParams :=
unlabeled_multi_params.
(* This is the fundamental safety property of the system:
No two different clients can (think they) hold
the lock at once.
*)
Definition mutual_exclusion (sigma : name -> data) : Prop :=
forall m n,
held (sigma (Client m)) = true ->
held (sigma (Client n)) = true ->
m = n.
(* The system enforces mutual exclusion at the server. Whenever a
client believs it holds the lock, that client is at the head of the
server's queue. *)
Definition locks_correct (sigma : name -> data) : Prop :=
forall n,
held (sigma (Client n)) = true ->
exists t,
queue (sigma Server) = n :: t.
(* We first show that this actually implies mutual exclusion. *)
Lemma locks_correct_implies_mutex :
forall sigma,
locks_correct sigma ->
mutual_exclusion sigma.
Proof using.
unfold locks_correct, mutual_exclusion.
intros.
repeat find_apply_hyp_hyp.
break_exists.
find_rewrite. find_inversion.
auto.
Qed.
Definition valid_unlock q h c p :=
pSrc p = Client c /\
(exists t, q = c :: t) /\
h = false.
Definition locks_correct_unlock (sigma : name -> data) (p : packet) : Prop :=
pBody p = Unlock ->
exists c, valid_unlock (queue (sigma Server)) (held (sigma (Client c))) c p.
Definition valid_locked q h c p :=
pDst p = Client c /\
(exists t, q = c :: t) /\
h = false.
Definition locks_correct_locked (sigma : name -> data) (p : packet) : Prop :=
pBody p = Locked ->
exists c, valid_locked (queue (sigma Server)) (held (sigma (Client c))) c p.
Definition LockServ_network_invariant (sigma : name -> data) (p : packet) : Prop :=
locks_correct_unlock sigma p /\
locks_correct_locked sigma p.
Definition LockServ_network_network_invariant (p q : packet) : Prop :=
(pBody p = Unlock -> pBody q = Unlock -> False) /\
(pBody p = Locked -> pBody q = Unlock -> False) /\
(pBody p = Unlock -> pBody q = Locked -> False) /\
(pBody p = Locked -> pBody q = Locked -> False).
Lemma nwnw_sym :
forall p q,
LockServ_network_network_invariant p q ->
LockServ_network_network_invariant q p.
Proof using.
unfold LockServ_network_network_invariant.
intuition.
Qed.
Lemma locks_correct_init :
locks_correct init_handlers.
Proof using.
unfold locks_correct. simpl. discriminate.
Qed.
Lemma InputHandler_cases :
forall h i st u out st' ms,
InputHandler h i st = (u, out, st', ms) ->
(exists c, h = Client c /\
((i = Lock /\ out = [] /\ st' = st /\ ms = [(Server, Lock)]) \/
(i = Unlock /\ out = [] /\ held st' = false /\
((held st = true /\ ms = [(Server, Unlock)]) \/
(st' = st /\ ms = []))))) \/
(out = [] /\ st' = st /\ ms = []).
Proof using.
handler_unfold.
intros.
repeat break_match; repeat tuple_inversion;
subst; simpl in *; subst; simpl in *.
- left. eexists. intuition.
- left. eexists. intuition.
- left. eexists. intuition.
- auto.
- auto.
Qed.
Lemma locks_correct_update_false :
forall sigma st' x,
locks_correct sigma ->
held st' = false ->
locks_correct (update name_eq_dec sigma (Client x) st').
Proof using.
unfold locks_correct.
intuition.
destruct (Name_eq_dec (Client x) (Client n)).
- find_inversion. exfalso.
rewrite_update.
congruence.
- rewrite_update.
auto.
Qed.
Ltac set_up_input_handlers :=
intros;
find_apply_lem_hyp InputHandler_cases;
intuition idtac; try break_exists; intuition idtac; subst;
repeat find_rewrite;
simpl in *; intuition idtac; repeat find_inversion;
try now rewrite update_nop_ext.
Lemma locks_correct_input_handlers :
forall h i sigma u st' out ms,
InputHandler h i (sigma h) = (u, out, st', ms) ->
locks_correct sigma ->
locks_correct (update name_eq_dec sigma h st').
Proof using.
set_up_input_handlers;
auto using locks_correct_update_false.
Qed.
Lemma ClientNetHandler_cases :
forall c m st u out st' ms,
ClientNetHandler c m st = (u, out, st', ms) ->
ms = [] /\
((st' = st /\ out = [] /\ m <> Locked) \/
(m = Locked /\ out = [Locked] /\ held st' = true)).
Proof using.
handler_unfold.
intros.
repeat break_match; repeat tuple_inversion; subst; intuition (auto; congruence).
Qed.
Lemma ServerNetHandler_cases :
forall src m st u out st' ms,
ServerNetHandler src m st = (u, out, st', ms) ->
out = [] /\
((exists c, src = Client c /\
(m = Lock /\
queue st' = queue st ++ [c] /\
((queue st = [] /\ ms = [(Client c, Locked)]) \/
(queue st <> [] /\ ms = [])))) \/
((m = Unlock /\
queue st' = tail (queue st) /\
((queue st' = [] /\ ms = []) \/
(exists next t, queue st' = next :: t /\ ms = [(Client next, Locked)])))) \/
ms = [] /\ st' = st /\ m <> Unlock).
Proof using.
handler_unfold.
intros.
repeat break_match; repeat tuple_inversion; subst.
- find_apply_lem_hyp null_sound. find_rewrite. simpl.
intuition. left. eexists. intuition.
- simpl. find_apply_lem_hyp null_false_neq_nil.
intuition. left. eexists. intuition.
- simpl. intuition (auto; congruence).
- simpl. destruct st; simpl in *; subst; intuition (auto; congruence).
- simpl in *. intuition.
- simpl in *. intuition eauto.
- simpl. intuition (auto; congruence).
Qed.
Definition at_head_of_queue sigma c := (exists t, queue (sigma Server) = c :: t).
Lemma at_head_of_queue_intro :
forall sigma c t,
queue (sigma Server) = c :: t ->
at_head_of_queue sigma c.
Proof using.
unfold at_head_of_queue.
firstorder.
Qed.
Lemma locks_correct_update_true :
forall sigma c st',
held st' = true ->
at_head_of_queue sigma c ->
locks_correct sigma ->
locks_correct (update name_eq_dec sigma (Client c) st').
Proof using.
unfold locks_correct.
intros.
destruct (Name_eq_dec (Client c) (Client n)); rewrite_update; try find_inversion; auto.
Qed.
Lemma locks_correct_locked_at_head :
forall sigma p c,
pDst p = Client c ->
pBody p = Locked ->
locks_correct_locked sigma p ->
at_head_of_queue sigma c.
Proof using.
unfold locks_correct_locked.
firstorder.
repeat find_rewrite. find_inversion.
eauto using at_head_of_queue_intro.
Qed.
Lemma all_clients_false_locks_correct_server_update :
forall sigma st,
(forall c, held (sigma (Client c)) = false) ->
locks_correct (update name_eq_dec sigma Server st).
Proof using.
unfold locks_correct.
intros.
rewrite_update.
now find_higher_order_rewrite.
Qed.
Lemma locks_correct_true_at_head_of_queue :
forall sigma x,
locks_correct sigma ->
held (sigma (Client x)) = true ->
at_head_of_queue sigma x.
Proof using.
unfold locks_correct.
intros.
find_apply_hyp_hyp. break_exists.
eauto using at_head_of_queue_intro.
Qed.
Lemma at_head_of_nil :
forall sigma c,
at_head_of_queue sigma c ->
queue (sigma Server) = [] ->
False.
Proof using.
unfold at_head_of_queue.
firstorder.
congruence.
Qed.
Lemma empty_queue_all_clients_false :
forall sigma,
locks_correct sigma ->
queue (sigma Server) = [] ->
(forall c, held (sigma (Client c)) = false).
Proof using.
intuition.
destruct (held (sigma (Client c))) eqn:?; auto.
exfalso. eauto using at_head_of_nil, locks_correct_true_at_head_of_queue.
Qed.
Lemma unlock_in_flight_all_clients_false :
forall sigma p,
pBody p = Unlock ->
locks_correct_unlock sigma p ->
locks_correct sigma ->
(forall c, held (sigma (Client c)) = false).
Proof using.
intros.
destruct (held (sigma (Client c))) eqn:?; auto.
firstorder.
find_copy_apply_lem_hyp locks_correct_true_at_head_of_queue; auto.
unfold at_head_of_queue in *. break_exists.
congruence.
Qed.
Lemma locks_correct_at_head_preserved :
forall sigma st',
locks_correct sigma ->
(forall c, at_head_of_queue sigma c -> at_head_of_queue (update name_eq_dec sigma Server st') c) ->
locks_correct (update name_eq_dec sigma Server st').
Proof using.
unfold locks_correct, at_head_of_queue.
firstorder.
rewrite_update.
eauto.
Qed.
Lemma snoc_at_head_of_queue_preserved :
forall sigma st' x,
queue st' = queue (sigma Server) ++ [x] ->
(forall c, at_head_of_queue sigma c -> at_head_of_queue (update name_eq_dec sigma Server st') c).
Proof using.
unfold at_head_of_queue.
intuition. break_exists.
rewrite_update.
find_rewrite.
eauto.
Qed.
Ltac set_up_net_handlers :=
intros;
match goal with
| [ H : context [ NetHandler (pDst ?p) _ _ _ ] |- _ ] =>
destruct (pDst p) eqn:?
end; simpl in *;
[find_apply_lem_hyp ClientNetHandler_cases |
find_apply_lem_hyp ServerNetHandler_cases; intuition; try break_exists ];
intuition; subst;
simpl in *; intuition;
repeat find_rewrite;
repeat find_inversion;
simpl in *;
try now rewrite update_nop_ext.
Lemma locks_correct_net_handlers :
forall p sigma u st' out ms,
NetHandler (pDst p) (pSrc p) (pBody p) (sigma (pDst p)) = (u, out, st', ms) ->
locks_correct sigma ->
locks_correct_unlock sigma p ->
locks_correct_locked sigma p ->
locks_correct (update name_eq_dec sigma (pDst p) st').
Proof using.
set_up_net_handlers;
eauto using
locks_correct_update_true, locks_correct_locked_at_head,
all_clients_false_locks_correct_server_update, empty_queue_all_clients_false,
locks_correct_at_head_preserved, snoc_at_head_of_queue_preserved,
all_clients_false_locks_correct_server_update, unlock_in_flight_all_clients_false.
Qed.
Lemma locks_correct_unlock_sent_lock :
forall sigma p,
pBody p = Lock ->
locks_correct_unlock sigma p.
Proof using.
unfold locks_correct_unlock.
intuition. congruence.
Qed.
Lemma locks_correct_unlock_sent_locked :
forall sigma p,
pBody p = Locked ->
locks_correct_unlock sigma p.
Proof using.
unfold locks_correct_unlock.
intuition. congruence.
Qed.
Lemma locks_correct_unlock_input_handlers_old :
forall h i sigma u st' out ms p,
InputHandler h i (sigma h) = (u, out, st', ms) ->
locks_correct sigma ->
locks_correct_unlock sigma p ->
locks_correct_unlock (update name_eq_dec sigma h st') p.
Proof using.
set_up_input_handlers.
destruct (pBody p) eqn:?.
- auto using locks_correct_unlock_sent_lock.
- now erewrite unlock_in_flight_all_clients_false in * by eauto.
- auto using locks_correct_unlock_sent_locked.
Qed.
Lemma locked_in_flight_all_clients_false :
forall sigma p,
pBody p = Locked ->
locks_correct_locked sigma p ->
locks_correct sigma ->
(forall c, held (sigma (Client c)) = false).
Proof using.
intros.
destruct (held (sigma (Client c))) eqn:?; auto.
firstorder.
find_copy_apply_lem_hyp locks_correct_true_at_head_of_queue; auto.
unfold at_head_of_queue in *. break_exists.
congruence.
Qed.
Lemma locks_correct_locked_sent_lock :
forall sigma p,
pBody p = Lock ->
locks_correct_locked sigma p.
Proof using.
unfold locks_correct_locked.
intuition. congruence.
Qed.
Lemma locks_correct_locked_sent_unlock :
forall sigma p,
pBody p = Unlock ->
locks_correct_locked sigma p.
Proof using.
unfold locks_correct_locked.
intuition. congruence.
Qed.
Lemma locks_correct_locked_input_handlers_old :
forall h i sigma u st' out ms p,
InputHandler h i (sigma h) = (u, out, st', ms) ->
locks_correct sigma ->
locks_correct_locked sigma p ->
locks_correct_locked (update name_eq_dec sigma h st') p.
Proof using.
set_up_input_handlers.
destruct (pBody p) eqn:?.
- auto using locks_correct_locked_sent_lock.
- auto using locks_correct_locked_sent_unlock.
- now erewrite locked_in_flight_all_clients_false in * by eauto.
Qed.
Lemma locks_correct_unlock_true_to_false :
forall sigma p x st',
at_head_of_queue sigma x ->
held st' = false ->
pSrc p = Client x ->
locks_correct_unlock (update name_eq_dec sigma (Client x) st') p.
Proof using.
unfold locks_correct_unlock, valid_unlock.
intros.
exists x.
intuition; now rewrite_update.
Qed.
Lemma locks_correct_unlock_input_handlers_new :
forall h i sigma u st' out ms p,
InputHandler h i (sigma h) = (u, out, st', ms) ->
locks_correct sigma ->
In (pDst p, pBody p) ms ->
pSrc p = h ->
locks_correct_unlock (update name_eq_dec sigma h st') p.
Proof using.
set_up_input_handlers;
auto using locks_correct_unlock_sent_lock,
locks_correct_unlock_true_to_false,
locks_correct_true_at_head_of_queue.
Qed.
Lemma locks_correct_locked_input_handlers_new :
forall h i sigma u st' out ms p,
InputHandler h i (sigma h) = (u, out, st', ms) ->
In (pDst p, pBody p) ms ->
locks_correct_locked (update name_eq_dec sigma h st') p.
Proof using.
set_up_input_handlers;
auto using locks_correct_locked_sent_lock, locks_correct_locked_sent_unlock.
Qed.
Lemma nwnw_locked_lock :
forall p q,
LockServ_network_network_invariant p q ->
pBody p = Locked ->
pBody q = Lock.
Proof using.
unfold LockServ_network_network_invariant.
intros.
destruct (pBody q); intuition; try discriminate.
Qed.
Lemma nwnw_unlock_lock :
forall p q,
LockServ_network_network_invariant p q ->
pBody p = Unlock ->
pBody q = Lock.
Proof using.
unfold LockServ_network_network_invariant.
intros.
destruct (pBody q); intuition; try discriminate.
Qed.
Lemma locks_correct_unlock_at_head :
forall sigma p c,
pSrc p = Client c ->
pBody p = Unlock ->
locks_correct_unlock sigma p ->
at_head_of_queue sigma c.
Proof using.
unfold locks_correct_unlock.
intros.
find_apply_hyp_hyp. clear H1.
break_exists.
unfold valid_unlock in *. intuition.
break_exists.
repeat find_rewrite. repeat find_inversion.
eauto using at_head_of_queue_intro.
Qed.
Lemma locks_correct_unlock_at_head_preserved :
forall sigma st' p,
locks_correct_unlock sigma p ->
(forall c, at_head_of_queue sigma c -> at_head_of_queue (update name_eq_dec sigma Server st') c) ->
locks_correct_unlock (update name_eq_dec sigma Server st') p.
Proof using.
unfold locks_correct_unlock, valid_unlock.
intuition.
break_exists.
exists x.
intuition.
- firstorder.
- now rewrite_update.
Qed.
Lemma nil_at_head_of_queue_preserved :
forall c sigma sigma',
queue (sigma Server) = [] ->
at_head_of_queue sigma c ->
at_head_of_queue sigma' c.
Proof using.
unfold at_head_of_queue.
firstorder.
congruence.
Qed.
Lemma locks_correct_unlock_net_handlers_old :
forall p sigma u st' out ms q,
NetHandler (pDst p) (pSrc p) (pBody p) (sigma (pDst p)) = (u, out, st', ms) ->
locks_correct sigma ->
locks_correct_unlock sigma q ->
LockServ_network_network_invariant p q ->
locks_correct_unlock (update name_eq_dec sigma (pDst p) st') q.
Proof using.
set_up_net_handlers;
eauto using locks_correct_unlock_sent_lock, nwnw_locked_lock,
locks_correct_unlock_at_head_preserved, snoc_at_head_of_queue_preserved,
nwnw_unlock_lock, nil_at_head_of_queue_preserved.
Qed.
Lemma locks_correct_locked_at_head_preserved :
forall sigma st' p,
locks_correct_locked sigma p ->
(forall c, at_head_of_queue sigma c -> at_head_of_queue (update name_eq_dec sigma Server st') c) ->
locks_correct_locked (update name_eq_dec sigma Server st') p.
Proof using.
unfold locks_correct_locked, valid_locked.
intuition.
break_exists.
exists x.
intuition.
- firstorder.
- now rewrite_update.
Qed.
Lemma locks_correct_locked_net_handlers_old :
forall p sigma u st' out ms q,
NetHandler (pDst p) (pSrc p) (pBody p) (sigma (pDst p)) = (u, out, st', ms) ->
locks_correct sigma ->
locks_correct_locked sigma q ->
LockServ_network_network_invariant p q ->
locks_correct_locked (update name_eq_dec sigma (pDst p) st') q.
Proof using.
set_up_net_handlers;
eauto using locks_correct_locked_sent_lock, nwnw_locked_lock,
locks_correct_locked_at_head_preserved, snoc_at_head_of_queue_preserved,
nwnw_unlock_lock, nil_at_head_of_queue_preserved.
Qed.
Lemma locks_correct_unlock_net_handlers_new :
forall p sigma u st' out ms q,
NetHandler (pDst p) (pSrc p) (pBody p) (sigma (pDst p)) = (u, out, st', ms) ->
locks_correct sigma ->
In (pDst q, pBody q) ms ->
locks_correct_unlock (update name_eq_dec sigma (pDst p) st') q.
Proof using.
set_up_net_handlers;
auto using locks_correct_unlock_sent_locked.
Qed.
Lemma locks_correct_locked_intro :
forall sigma p c t st',
pDst p = Client c ->
held (sigma (Client c)) = false ->
queue st' = c :: t ->
locks_correct_locked (update name_eq_dec sigma Server st') p.
Proof using.
unfold locks_correct_locked, valid_locked.
intros.
exists c.
intuition.
- exists t. now rewrite_update.
- now rewrite_update.
Qed.
Lemma locks_correct_locked_net_handlers_new :
forall p sigma u st' out ms q,
NetHandler (pDst p) (pSrc p) (pBody p) (sigma (pDst p)) = (u, out, st', ms) ->
locks_correct sigma ->
locks_correct_unlock sigma p ->
In (pDst q, pBody q) ms ->
locks_correct_locked (update name_eq_dec sigma (pDst p) st') q.
Proof using.
set_up_net_handlers;
eauto using locks_correct_locked_intro,
empty_queue_all_clients_false,
unlock_in_flight_all_clients_false.
Qed.
Lemma nwnw_lock :
forall p p',
pBody p = Lock ->
LockServ_network_network_invariant p p'.
Proof using.
unfold LockServ_network_network_invariant.
intuition; simpl in *; congruence.
Qed.
Lemma LockServ_nwnw_input_handlers_old_new :
forall h i sigma u st' out ms p p',
InputHandler h i (sigma h) = (u, out, st', ms) ->
locks_correct sigma ->
LockServ_network_invariant sigma p ->
In (pDst p', pBody p') ms ->
pSrc p' = h ->
LockServ_network_network_invariant p p'.
Proof using.
unfold LockServ_network_invariant.
set_up_input_handlers.
- auto using nwnw_sym, nwnw_lock.
- destruct (pBody p) eqn:?.
+ auto using nwnw_lock.
+ now erewrite unlock_in_flight_all_clients_false in * by eauto.
+ now erewrite locked_in_flight_all_clients_false in * by eauto.
Qed.
Lemma LockServ_nwnw_input_handlers_new_new :
forall h i sigma u st' out ms,
InputHandler h i (sigma h) = (u, out, st', ms) ->
distinct_pairs_and LockServ_network_network_invariant
(map (fun m => mkPacket h (fst m) (snd m)) ms).
Proof using.
set_up_input_handlers.
Qed.
Lemma nw_empty_queue_lock :
forall sigma p,
LockServ_network_invariant sigma p ->
queue (sigma Server) = [] ->
pBody p = Lock.
Proof using.
unfold LockServ_network_invariant,
locks_correct_unlock, locks_correct_locked,
valid_unlock, valid_locked.
intuition.
destruct (pBody p) eqn:?; intuition; break_exists; intuition; break_exists;
congruence.
Qed.
Lemma LockServ_nwnw_net_handlers_old_new :
forall p sigma u st' out ms q p',
NetHandler (pDst p) (pSrc p) (pBody p) (sigma (pDst p)) = (u, out, st', ms) ->
locks_correct sigma ->
LockServ_network_invariant sigma p ->
LockServ_network_invariant sigma q ->
LockServ_network_network_invariant p q ->
In (pDst p', pBody p') ms ->
LockServ_network_network_invariant p' q.
Proof using.
set_up_net_handlers;
eauto using nwnw_sym, nwnw_lock, nw_empty_queue_lock, nwnw_unlock_lock.
Qed.
Lemma LockServ_nwnw_net_handlers_new_new :
forall p sigma u st' out ms,
NetHandler (pDst p) (pSrc p) (pBody p) (sigma (pDst p)) = (u, out, st', ms) ->
locks_correct sigma ->
LockServ_network_invariant sigma p ->
distinct_pairs_and LockServ_network_network_invariant
(map (fun m => mkPacket (pDst p) (fst m) (snd m)) ms).
Proof using.
set_up_net_handlers.
Qed.
Ltac unlabeled_unfold :=
unfold unlabeled_net_handlers, unlabeled_input_handlers in *.
Instance LockServ_Decompositition : Decomposition _ LockServ_MultiParams.
apply Build_Decomposition with (state_invariant := locks_correct)
(network_invariant := LockServ_network_invariant)
(network_network_invariant := LockServ_network_network_invariant);
simpl; intros; monad_unfold; unlabeled_unfold; repeat break_let; repeat find_inversion.
- auto using nwnw_sym.
- auto using locks_correct_init.
- eauto using locks_correct_input_handlers.
- unfold LockServ_network_invariant in *. intuition.
eauto using locks_correct_net_handlers.
- unfold LockServ_network_invariant in *.
intuition eauto using locks_correct_unlock_input_handlers_old,
locks_correct_locked_input_handlers_old.
- unfold LockServ_network_invariant in *.
intuition eauto using locks_correct_unlock_input_handlers_new,
locks_correct_locked_input_handlers_new.
- unfold LockServ_network_invariant in *.
intuition eauto using locks_correct_unlock_net_handlers_old,
locks_correct_locked_net_handlers_old.
- unfold LockServ_network_invariant in *.
intuition eauto using locks_correct_unlock_net_handlers_new,
locks_correct_locked_net_handlers_new.
- eauto using LockServ_nwnw_input_handlers_old_new.
- eauto using LockServ_nwnw_input_handlers_new_new.
- eauto using LockServ_nwnw_net_handlers_old_new.
- eauto using LockServ_nwnw_net_handlers_new_new.
Defined.
Theorem true_in_reachable_mutual_exclusion :
true_in_reachable step_async step_async_init (fun net => mutual_exclusion (nwState net)).
Proof using.
pose proof decomposition_invariant.
find_apply_lem_hyp inductive_invariant_true_in_reachable.
unfold true_in_reachable in *.
intros.
apply locks_correct_implies_mutex.
match goal with
| [ H : _ |- _ ] => apply H
end.
auto.
Qed.
Fixpoint last_holder' (holder : option Client_index) (trace : list (name * (input + list output))) : option Client_index :=
match trace with
| [] => holder
| (Client n, inl Unlock) :: tr => match holder with
| None => last_holder' holder tr
| Some m => if fin_eq_dec _ n m
then last_holder' None tr
else last_holder' holder tr
end
| (Client n, inr [Locked]) :: tr => last_holder' (Some n) tr
| (n, _) :: tr => last_holder' holder tr
end.
Fixpoint trace_mutual_exclusion' (holder : option Client_index) (trace : list (name * (input + list output))) : Prop :=
match trace with
| [] => True
| (Client n, (inl Unlock)) :: tr' => match holder with
| Some m => if fin_eq_dec _ n m
then trace_mutual_exclusion' None tr'
else trace_mutual_exclusion' holder tr'
| _ => trace_mutual_exclusion' holder tr'
end
| (n, (inl _)) :: tr' => trace_mutual_exclusion' holder tr'
| (Client n, (inr [Locked])) :: tr' => match holder with
| None => trace_mutual_exclusion' (Some n) tr'
| Some _ => False
end
| (_, (inr [])) :: tr' => trace_mutual_exclusion' holder tr'
| (_, (inr _)) :: tr' => False
end.
Definition trace_mutual_exclusion (trace : list (name * (input + list output))) : Prop :=
trace_mutual_exclusion' None trace.
Definition last_holder (trace : list (name * (input + list output))) : option Client_index :=
last_holder' None trace.
Lemma cross_relation :
forall (P : network -> list (name * (input + list output)) -> Prop),
P step_async_init [] ->
(forall st st' tr ev,
step_async_star step_async_init st tr ->
P st tr ->
step_async st st' ev ->
P st' (tr ++ ev)) ->
forall st tr,
step_async_star step_async_init st tr ->
P st tr.
Proof using.
intros.
find_apply_lem_hyp refl_trans_1n_n1_trace.
prep_induction H1.
induction H1; intros; subst; eauto.
eapply H3; eauto.
- apply refl_trans_n1_1n_trace. auto.
- apply IHrefl_trans_n1_trace; auto.
Qed.
Lemma trace_mutex'_no_out_extend :
forall tr n h,
trace_mutual_exclusion' h tr ->
trace_mutual_exclusion' h (tr ++ [(n, inr [])]).
Proof using.
induction tr; intuition; unfold trace_mutual_exclusion in *; simpl in *;
repeat break_match; subst; intuition.
Qed.
Lemma last_holder'_no_out_inv :
forall tr h c n,
last_holder' h (tr ++ [(c, inr [])]) = Some n ->
last_holder' h tr = Some n.
Proof using.
induction tr; intros; simpl in *; repeat break_match; subst; intuition; eauto.
Qed.
Lemma last_holder'_no_out_extend :
forall tr h c n,
last_holder' h tr = Some n ->
last_holder' h (tr ++ [(c, inr [])]) = Some n.
Proof using.
induction tr; intros; simpl in *; repeat break_match; subst; intuition.
Qed.
Lemma decomposition_reachable_nw_invariant :
forall st tr p,
step_async_star step_async_init st tr ->
In p (nwPackets st) ->
network_invariant (nwState st) p.
Proof using.
pose proof decomposition_invariant.
find_apply_lem_hyp inductive_invariant_true_in_reachable.
unfold true_in_reachable, reachable in *.
intuition.
unfold composed_invariant in *.
apply H; eauto.
Qed.
Lemma trace_mutex'_locked_extend :
forall tr h n,
trace_mutual_exclusion' h tr ->
last_holder' h tr = None ->
trace_mutual_exclusion' h (tr ++ [(Client n, inr [Locked])]).
Proof using.
induction tr; intros; simpl in *.
- subst. auto.
- simpl in *. repeat break_match; subst; intuition.
Qed.
Lemma reachable_intro :
forall a tr,
step_async_star step_async_init a tr ->
reachable step_async step_async_init a.
Proof using.
unfold reachable.
intros. eauto.
Qed.
Lemma locks_correct_locked_invariant :
forall st p,
reachable step_async step_async_init st ->
In p (nwPackets st) ->
locks_correct_locked (nwState st) p.
Proof using.
intros.
pose proof decomposition_invariant.
find_apply_lem_hyp inductive_invariant_true_in_reachable.
unfold true_in_reachable in *. apply H1; auto.
Qed.
Lemma locks_correct_invariant :
forall st,
reachable step_async step_async_init st ->
locks_correct (nwState st).
Proof using.
intros.
pose proof decomposition_invariant.
find_apply_lem_hyp inductive_invariant_true_in_reachable.
unfold true_in_reachable in *. apply H0; auto.
Qed.
Lemma mutual_exclusion_invariant :
forall st,
reachable step_async step_async_init st ->
mutual_exclusion (nwState st).
Proof using.
intros.
apply locks_correct_implies_mutex.
auto using locks_correct_invariant.
Qed.
Lemma last_holder'_locked_some_eq :
forall tr h c n,
last_holder' h (tr ++ [(Client c, inr [Locked])]) = Some n ->
c = n.
Proof using.
induction tr; intros; simpl in *; repeat break_match; subst; eauto.
congruence.
Qed.
Ltac my_update_destruct :=
match goal with
| [H : context [ update _ _ ?x _ ?y ] |- _ ] => destruct (Name_eq_dec x y)
| [ |- context [ update _ _ ?x _ ?y ] ] => destruct (Name_eq_dec x y)
end.
Lemma last_holder'_server_extend :
forall tr h i,
last_holder' h (tr ++ [(Server, inl i)]) = last_holder' h tr.
Proof using.
induction tr; intros; simpl in *; repeat break_match; auto.
Qed.
Lemma last_holder'_locked_extend :
forall tr h n,
last_holder' h (tr ++ [(Client n, inr [Locked])]) = Some n.
Proof using.
induction tr; intros; simpl in *; repeat break_match; auto.
Qed.
Lemma trace_mutual_exclusion'_extend_input :
forall tr h c i,
i <> Unlock ->
trace_mutual_exclusion' h tr ->
trace_mutual_exclusion' h (tr ++ [(Client c, inl i)]).
Proof using.
induction tr; intros; simpl in *; repeat break_match; intuition.
Qed.
Lemma trace_mutual_exclusion'_extend_input_server :
forall tr h i,
trace_mutual_exclusion' h tr ->
trace_mutual_exclusion' h (tr ++ [(Server, inl i)]).
Proof using.
induction tr; intros; simpl in *; repeat break_match; intuition.
Qed.
Lemma last_holder'_input_inv :
forall tr h c i n,
i <> Unlock ->
last_holder' h (tr ++ [(Client c, inl i)]) = Some n ->
last_holder' h tr = Some n.
Proof using.
induction tr; intros; simpl in *; repeat break_match; auto; try congruence; subst; eauto.
Qed.
Lemma last_holder'_input_inv_server :
forall tr h i n,
last_holder' h (tr ++ [(Server, inl i)]) = Some n ->
last_holder' h tr = Some n.
Proof using.
induction tr; intros; simpl in *; repeat break_match; auto; try congruence; subst; eauto.
Qed.
Lemma last_holder'_input_extend :
forall tr h c i n,
i <> Unlock ->
last_holder' h tr = Some n ->
last_holder' h (tr ++ [(Client c, inl i)]) = Some n.
Proof using.
induction tr; intros; simpl in *; repeat break_match; auto.
congruence.
Qed.
Lemma trace_mutex'_unlock_extend :
forall tr h c,
trace_mutual_exclusion' h tr ->
trace_mutual_exclusion' h (tr ++ [(Client c, inl Unlock)]).
Proof using.
induction tr; intros; simpl in *; repeat break_match; intuition (auto; try congruence).
Qed.
Lemma last_holder'_unlock_none :
forall tr h c,
last_holder' h tr = Some c ->
last_holder' h (tr ++ [(Client c, inl Unlock)]) = None.
Proof using.
induction tr; intros; simpl in *; repeat break_match; intuition.
congruence.
Qed.
Lemma last_holder_unlock_none :
forall tr c,
last_holder tr = Some c ->
last_holder (tr ++ [(Client c, inl Unlock)]) = None.
Proof using.
intros.
apply last_holder'_unlock_none. auto.
Qed.
Lemma last_holder_some_unlock_inv :
forall tr h c n,
last_holder' h (tr ++ [(Client c, inl Unlock)]) = Some n ->
last_holder' h tr = Some n.
Proof using.
induction tr; intros; simpl in *; repeat break_match; subst;
intuition; try congruence; eauto.
Qed.
Lemma last_holder'_neq_unlock_extend :
forall tr h n c,
last_holder' h tr = Some n ->
n <> c ->
last_holder' h (tr ++ [(Client c, inl Unlock)]) = Some n.
Proof using.
induction tr; intros; simpl in *; repeat break_match; subst; try congruence; intuition.
Qed.
Lemma LockServ_mutual_exclusion_trace :
forall st tr,
step_async_star step_async_init st tr ->
trace_mutual_exclusion tr /\
(forall n, last_holder tr = Some n -> held (nwState st (Client n)) = true) /\
(forall n, held (nwState st (Client n)) = true -> last_holder tr = Some n).
Proof using.
apply cross_relation; intros.
- intuition.
+ red. red. auto.
+ unfold last_holder in *. simpl in *. discriminate.
+ unfold last_holder in *. simpl in *. discriminate.
- match goal with
| [ H : step_async _ _ _ |- _ ] => invcs H
end; monad_unfold; unlabeled_unfold;
unfold lb_net_handlers, lb_input_handlers in *; simpl in *;
repeat break_let; repeat find_inversion.
+ unfold NetHandler in *. break_match.
* find_apply_lem_hyp ClientNetHandler_cases; eauto.
break_and.
{ break_or_hyp.
- intuition; subst.
+ apply trace_mutex'_no_out_extend; auto.
+ rewrite update_nop_ext.
find_apply_lem_hyp last_holder'_no_out_inv.
auto.
+ match goal with
| [ H : _ |- _ ] => rewrite update_nop in H
end.
find_apply_hyp_hyp.
apply last_holder'_no_out_extend. auto.
- intuition; subst.
+ apply trace_mutex'_locked_extend. auto.
destruct (last_holder' None tr) eqn:?; auto.
find_apply_hyp_hyp.
erewrite locked_in_flight_all_clients_false in * by
eauto using locks_correct_locked_invariant, reachable_intro,
locks_correct_invariant.
discriminate.
+ my_update_destruct; try find_inversion; rewrite_update; auto.
find_apply_lem_hyp last_holder'_locked_some_eq. congruence.
+ my_update_destruct; try find_inversion; rewrite_update.
* apply last_holder'_locked_extend.
* erewrite locked_in_flight_all_clients_false in * by
eauto using locks_correct_locked_invariant, reachable_intro,
locks_correct_invariant.
discriminate.
}
* { find_apply_lem_hyp ServerNetHandler_cases. break_and. subst.
repeat split.
- apply trace_mutex'_no_out_extend. auto.
- intros. my_update_destruct; try discriminate.
rewrite_update.
find_apply_lem_hyp last_holder'_no_out_inv.
auto.
- intros. my_update_destruct; try discriminate; rewrite_update.
apply last_holder'_no_out_extend. auto.
}
+ unfold InputHandler in *. break_match.
* unfold ClientIOHandler in *.
{ monad_unfold.
repeat break_match; repeat find_inversion; intuition;
repeat rewrite snoc_assoc in *;
try apply trace_mutex'_no_out_extend;
try find_apply_lem_hyp last_holder'_no_out_inv;
try (apply last_holder'_no_out_extend; auto).
- apply trace_mutual_exclusion'_extend_input; auto. congruence.
- rewrite update_nop_ext.
find_apply_lem_hyp last_holder'_input_inv; try congruence.
auto.
- match goal with
| [ H : _ |- _ ] => rewrite update_nop in H
end.
apply last_holder'_input_extend; auto. congruence.
- apply trace_mutex'_unlock_extend; auto.
- rewrite last_holder_unlock_none in *; auto. discriminate.
- my_update_destruct; try find_inversion; rewrite_update.
+ discriminate.
+ assert (mutual_exclusion (nwState st))
by eauto using mutual_exclusion_invariant, reachable_intro.
unfold mutual_exclusion in *.
assert (c = n) by eauto. congruence.
- apply trace_mutex'_unlock_extend. auto.
- rewrite update_nop.
find_apply_lem_hyp last_holder_some_unlock_inv.
auto.
- match goal with
| [ H : _ |- _ ] => rewrite update_nop in H
end.
assert (n <> c) by congruence.
find_apply_hyp_hyp.
apply last_holder'_neq_unlock_extend; auto.
- apply trace_mutual_exclusion'_extend_input; auto. congruence.
- rewrite update_nop_ext. find_apply_lem_hyp last_holder'_input_inv; try congruence.
auto.
- match goal with
| [ H : _ |- _ ] => rewrite update_nop in H
end.
apply last_holder'_input_extend; auto. congruence.
}
* unfold ServerIOHandler in *.
monad_unfold. find_inversion.
{ intuition;
repeat rewrite snoc_assoc in *.
- apply trace_mutex'_no_out_extend.
apply trace_mutual_exclusion'_extend_input_server. auto.
- find_apply_lem_hyp last_holder'_no_out_inv.
rewrite update_nop. find_apply_lem_hyp last_holder'_input_inv_server. auto.
- apply last_holder'_no_out_extend; auto.
rewrite_update. unfold last_holder. rewrite last_holder'_server_extend.
auto.
}
Qed.
Lemma head_grant_state_unlock :
forall st tr c t,
step_async_star step_async_init st tr ->
queue (nwState st Server) = c :: t ->
(In (mkPacket Server (Client c) Locked) (nwPackets st)) \/
(held (nwState st (Client c)) = true) \/
(In (mkPacket (Client c) Server Unlock) (nwPackets st)).
Proof using.
intros.
find_apply_lem_hyp refl_trans_1n_n1_trace.
prep_induction H.
induction H; intros; subst.
- discriminate.
- match goal with
| [ H : step_async _ _ _ |- _ ] => invcs H
end; unlabeled_unfold;
unfold lb_net_handlers, lb_input_handlers in *; simpl in *;
monad_unfold;
repeat break_let; repeat find_inversion.
+ unfold NetHandler in *.
break_match; rewrite_update.
* find_apply_lem_hyp ClientNetHandler_cases.
intuition.
-- subst. rewrite update_nop_ext.
find_apply_lem_hyp IHrefl_trans_n1_trace; auto; [idtac].
repeat find_rewrite.
simpl.
in_crush.
discriminate.
-- subst.
find_apply_lem_hyp refl_trans_n1_1n_trace.
find_apply_lem_hyp reachable_intro.
match goal with
| [ H : reachable _ _ _ |- _ ] =>
let H' := fresh H in
pose H as H';
eapply locks_correct_locked_invariant with (p := p) in H';
[| now repeat find_rewrite; in_crush];
eapply locks_correct_locked_at_head in H'; eauto
end.
unfold at_head_of_queue in *. break_exists. find_rewrite. find_inversion.
rewrite_update. auto.
* find_apply_lem_hyp ServerNetHandler_cases. intuition.
-- break_exists. intuition.
++ subst. repeat find_rewrite. simpl in *.
find_inversion. auto.
++ subst. repeat find_rewrite.
destruct (queue (nwState x' Server)); try congruence.
simpl in *. find_inversion.
do 2 insterU IHrefl_trans_n1_trace.
repeat conclude_using eauto.
intuition.
** in_crush. discriminate.
** in_crush. discriminate.
-- congruence.
-- break_exists. intuition. subst. simpl.
repeat find_rewrite. find_inversion. auto.
-- subst. simpl.
find_apply_hyp_hyp. intuition.
++ repeat find_rewrite. in_crush. discriminate.
++ repeat find_rewrite. in_crush.
+ find_apply_lem_hyp InputHandler_cases.
intuition.
* break_exists. break_and. subst.
rewrite_update.
find_apply_hyp_hyp.
intuition.
-- subst. rewrite update_nop_ext. auto.
-- find_apply_lem_hyp refl_trans_n1_1n_trace.
find_apply_lem_hyp reachable_intro.
match goal with
| [ H : reachable _ _ _ |- _ ] =>
pose H as Hmutex;
eapply mutual_exclusion_invariant in Hmutex
end.
unfold mutual_exclusion in *.
assert (c = x) by auto. clear Hmutex.
subst. simpl. auto.
-- subst. rewrite_update. auto.
* subst. simpl. rewrite update_nop_ext in *.
match goal with
| [ H : _ |- _ ] => apply IHrefl_trans_n1_trace in H; auto
end.
Qed.
(* LIVENESS *)
Lemma InputHandler_lbcases :
forall h i st l out st' ms,
InputHandler h i st = (l, out, st', ms) ->
(exists c, h = Client c /\
((i = Lock /\ out = [] /\ st' = st /\ ms = [(Server, Lock)] /\ l = InputLock c) \/
(l = InputUnlock c /\ i = Unlock /\ out = [] /\ held st' = false /\
((held st = true /\ ms = [(Server, Unlock)]) \/
(st' = st /\ ms = []))))) \/
(out = [] /\ st' = st /\ ms = [] /\ l = Nop).
Proof using.
handler_unfold.
intros.
repeat break_match; repeat tuple_inversion;
subst; simpl in *; subst; simpl in *.
- left. eexists. intuition.
- left. eexists. intuition.
- left. eexists. intuition.
- auto.
- auto.
Qed.
Lemma ClientNetHandler_lbcases :
forall c m st l out st' ms,
ClientNetHandler c m st = (l, out, st', ms) ->
ms = [] /\
((st' = st /\ out = [] /\ l = Nop) \/
(m = Locked /\ out = [Locked] /\ held st' = true /\ l = MsgLocked c)).
Proof using.
handler_unfold.
intros.
repeat break_match; repeat tuple_inversion; subst; intuition.
Qed.
Lemma ServerNetHandler_lbcases :
forall src m st l out st' ms,
ServerNetHandler src m st = (l, out, st', ms) ->
out = [] /\
((exists c, src = Client c /\
(m = Lock /\
l = MsgLock c /\
queue st' = queue st ++ [c] /\
((queue st = [] /\ ms = [(Client c, Locked)]) \/
(queue st <> [] /\ ms = [])))) \/
((m = Unlock /\ l = MsgUnlock /\
queue st' = tail (queue st) /\
((queue st' = [] /\ ms = []) \/
(exists next t, queue st' = next :: t /\ ms = [(Client next, Locked)])))) \/
ms = [] /\ st' = st /\ l = Nop).
Proof using.
handler_unfold.
intros.
repeat break_match; repeat tuple_inversion; subst.
- find_apply_lem_hyp null_sound. find_rewrite. simpl.
intuition. left. eexists. intuition.
- simpl. find_apply_lem_hyp null_false_neq_nil.
intuition. left. eexists. intuition.
- simpl. intuition.
- simpl. destruct st; simpl in *; subst; intuition.
- simpl in *. intuition.
- simpl in *. intuition eauto.
- simpl. intuition.
Qed.
Definition message_enables_label p l :=
forall net,
In p (nwPackets net) ->
lb_step_ex lb_step_async l net.
Lemma Lock_enables_MsgLock :
forall i,
message_enables_label (mkPacket (Client i) Server Lock) (MsgLock i).
Proof using.
unfold message_enables_label.
intros.
find_apply_lem_hyp in_split.
break_exists_name xs. break_exists_name ys.
unfold enabled.
destruct (ServerNetHandler (Client i) Lock (nwState net Server)) eqn:?.
destruct p. destruct p.
cut (l0 = MsgLock i); intros.
subst.
- repeat eexists. econstructor; eauto.
- handler_unfold. repeat break_match; repeat find_inversion; auto.
Qed.
Definition message_delivered_label p l :=
forall l' net net' tr,
lb_step_async net l' net' tr ->
In p (nwPackets net) ->
~ In p (nwPackets net') ->
l = l'.
Lemma In_split_not_In :
forall A (p : A) p' xs ys zs,
In p (xs ++ p' :: ys) ->
~ In p (zs ++ xs ++ ys) ->
p = p'.
Proof using.
intros.
find_apply_lem_hyp in_app_iff.
simpl in *; intuition;
find_false; apply in_app_iff; right; apply in_app_iff; auto.
Qed.
Lemma Lock_delivered_MsgLock :
forall i,
message_delivered_label (mkPacket (Client i) Server Lock) (MsgLock i).
Proof using.
unfold message_delivered_label.
intros.
invcs H.
- repeat find_rewrite.
find_eapply_lem_hyp In_split_not_In; eauto. subst.
monad_unfold. simpl in *.
handler_unfold. repeat break_match; repeat find_inversion; auto.
- unfold not in *. find_false.
apply in_app_iff; auto.
- intuition.
Qed.
Definition label_eq_dec :
forall x y : label,
{x = y} + {x <> y}.
Proof using.
decide equality; apply fin_eq_dec.
Qed.
Lemma messages_trigger_labels :
forall l p,
message_enables_label p l ->
message_delivered_label p l ->
forall s,
lb_step_execution lb_step_async s ->
In p (nwPackets (evt_a (hd s))) ->
weak_until (now (enabled lb_step_async l))
(now (occurred l))
s.
Proof using.
intros l p Henabled Hdelivered.
cofix c.
destruct s. destruct e.
simpl.
intros Hexec Hin.
invcs Hexec.
destruct (label_eq_dec l evt_l).
- subst evt_l.
apply W0. simpl. reflexivity.
- apply W_tl.
+ simpl.
unfold message_enables_label in *.
unfold enabled. simpl. now auto.
+ simpl.
apply c; auto.
simpl.
match goal with
| |- In ?p ?ps =>
destruct (In_dec packet_eq_dec p ps)
end; auto.
unfold message_delivered_label in *.
now find_apply_hyp_hyp.
Qed.
Lemma message_labels_eventually_occur :
forall l p,
l <> label_silent ->
message_enables_label p l ->
message_delivered_label p l ->
forall s,
weak_fairness lb_step_async label_silent s ->
lb_step_execution lb_step_async s ->
In p (nwPackets (evt_a (hd s))) ->
eventually (now (occurred l)) s.
Proof using.
intros.
find_eapply_lem_hyp messages_trigger_labels; eauto.
find_apply_lem_hyp weak_until_until_or_always.
intuition.
- now eauto using until_eventually.
- find_apply_lem_hyp always_continuously.
eapply_prop_hyp weak_fairness continuously; auto.
destruct s.
now find_apply_lem_hyp always_now.
Qed.
Ltac coinductive_case CIH :=
apply W_tl; simpl in *; auto;
apply CIH; simpl in *; auto.
Lemma Nth_app :
forall A (l : list A) l' a n,
Nth l n a ->
Nth (l ++ l') n a.
Proof using.
induction l; intros; simpl in *; try solve_by_inversion.
invcs H.
- constructor.
- constructor. auto.
Qed.
Lemma Nth_tl :
forall A (l : list A) a n,
Nth l (S n) a ->
Nth (List.tl l) n a.
Proof using.
induction l; intros; solve_by_inversion.
Qed.
Lemma clients_only_move_up_in_queue :
forall n c s,
lb_step_execution lb_step_async s ->
Nth (queue (nwState (evt_a (hd s)) Server)) (S n) c ->
weak_until (fun s => Nth (queue (nwState (evt_a (hd s)) Server)) (S n) c)
(next (fun s => Nth (queue (nwState (evt_a (hd s)) Server)) n c
/\ (n = 0 -> In (mkPacket Server (Client c) Locked)
(nwPackets (evt_a (hd s))))))
s.
Proof using.
intros n c.
cofix CIH.
destruct s.
destruct e.
intros Hexec HNth.
invcs Hexec.
invcs H1.
- unfold runGenHandler, NetHandler in *.
break_match.
+ coinductive_case CIH.
find_rewrite. simpl.
now rewrite_update.
+ find_apply_lem_hyp ServerNetHandler_lbcases.
intuition.
* coinductive_case CIH.
repeat find_rewrite. simpl.
rewrite_update.
break_exists.
intuition; repeat find_rewrite; try solve_by_inversion.
now eauto using Nth_app.
* exfalso. clear CIH.
subst.
invcs HNth.
repeat find_reverse_rewrite. simpl in *.
repeat find_rewrite. now solve_by_inversion.
* clear CIH.
apply W0. simpl.
fold LockServ_MultiParams in *. (* typeclass stuff *)
repeat find_rewrite. simpl.
rewrite_update. repeat find_rewrite.
intuition eauto using Nth_tl.
break_exists.
intuition. subst.
find_apply_lem_hyp Nth_tl.
repeat find_rewrite.
invcs HNth. auto.
* coinductive_case CIH.
repeat find_rewrite. simpl.
now rewrite_update.
- unfold runGenHandler in *.
find_apply_lem_hyp InputHandler_cases.
intuition.
+ break_exists. break_and. subst.
coinductive_case CIH.
repeat find_rewrite. simpl.
now rewrite_update.
+ coinductive_case CIH.
repeat find_rewrite. simpl.
update_destruct; subst; now rewrite_update.
- coinductive_case CIH.
Qed.
Lemma MsgUnlock_moves_client :
forall n c s,
lb_step_execution lb_step_async s ->
Nth (queue (nwState (evt_a (hd s)) Server)) (S n) c ->
now (occurred MsgUnlock) s ->
next (fun s => Nth (queue (nwState (evt_a (hd s)) Server)) n c
/\ (n = 0 -> In (mkPacket Server (Client c) Locked)
(nwPackets (evt_a (hd s))))) s.
Proof using.
intros n c s Hexec HNth Hlabel.
destruct s. simpl.
invcs Hexec.
match goal with
| H : lb_step_async _ _ _ _ |- _ => invcs H
end.
- unfold occurred in *.
match goal with
| H : MsgUnlock = _ |- _ => symmetry in H; repeat find_rewrite; clear H
end.
monad_unfold. unfold NetHandler in *.
break_match.
+ find_apply_lem_hyp ClientNetHandler_lbcases.
intuition; congruence.
+ find_apply_lem_hyp ServerNetHandler_lbcases.
(* not using intuition because i don't want to break
or in the goal *)
repeat (break_and; try break_or_hyp);
break_exists;
repeat (break_and; try break_or_hyp);
try congruence.
* exfalso.
repeat find_rewrite.
invcs HNth.
repeat find_reverse_rewrite.
simpl in *. subst. solve_by_inversion.
* fold LockServ_MultiParams in *. (* typeclass stuff *)
repeat find_rewrite.
simpl in *.
find_apply_lem_hyp Nth_tl.
repeat find_rewrite.
intuition; [|intros; subst; solve_by_inversion].
rewrite_update. congruence.
- unfold occurred in *.
match goal with
| H : MsgUnlock = _ |- _ => symmetry in H; repeat find_rewrite; clear H
end.
monad_unfold. find_apply_lem_hyp InputHandler_lbcases.
intuition; break_exists; intuition; congruence.
- unfold occurred in *. congruence.
Qed.
Lemma Unlock_enables_MsgUnlock :
forall n,
message_enables_label (mkPacket n Server Unlock) MsgUnlock.
Proof using.
unfold message_enables_label.
intros.
find_apply_lem_hyp in_split.
break_exists_name xs. break_exists_name ys.
unfold enabled.
destruct (ServerNetHandler n Unlock (nwState net Server)) eqn:?.
destruct p. destruct p.
cut (l0 = MsgUnlock); intros.
subst.
- repeat eexists. econstructor; eauto.
- handler_unfold. repeat break_match; repeat find_inversion; auto.
Qed.
Lemma Unlock_delivered_MsgUnlock :
forall n,
message_delivered_label (mkPacket n Server Unlock) MsgUnlock.
Proof using.
unfold message_delivered_label.
intros.
invcs H.
- repeat find_rewrite.
find_eapply_lem_hyp In_split_not_In; eauto. subst.
monad_unfold. simpl in *.
handler_unfold. repeat break_match; repeat find_inversion; auto.
- unfold not in *. find_false.
apply in_app_iff; auto.
- intuition.
Qed.
Lemma Unlock_in_network_eventually_MsgUnlock :
forall c s,
lb_step_execution lb_step_async s ->
weak_fairness lb_step_async label_silent s ->
In (mkPacket c Server Unlock) (nwPackets (evt_a (hd s))) ->
eventually (now (occurred MsgUnlock)) s.
Proof using.
intros.
eapply message_labels_eventually_occur;
eauto using Unlock_enables_MsgUnlock, Unlock_delivered_MsgUnlock.
unfold label_silent. simpl. congruence.
Qed.
Lemma Nth_something_at_head :
forall A (l : list A) n x,
Nth l n x ->
exists y l',
l = y :: l'.
Proof using.
intros.
solve_by_inversion' eauto.
Qed.
Lemma InputUnlock_held :
forall s c,
lb_step_execution lb_step_async s ->
held (nwState (evt_a (hd s)) (Client c)) = true ->
now (occurred (InputUnlock c)) s ->
next (fun s => In (mkPacket (Client c) Server Unlock) (nwPackets (evt_a (hd s)))) s.
Proof using.
intros.
invcs H.
invcs H2.
- monad_unfold.
unfold NetHandler in *.
break_match_hyp.
+ unfold occurred in *.
find_apply_lem_hyp ClientNetHandler_lbcases; intuition; congruence.
+ unfold occurred in *.
find_apply_lem_hyp ServerNetHandler_lbcases; intuition;
break_exists; intuition; congruence.
- monad_unfold.
find_apply_lem_hyp InputHandler_lbcases.
intuition; try congruence.
break_exists. intuition; try congruence.
fold LockServ_MultiParams in *. (* typeclass stuff *)
repeat find_rewrite.
simpl. left. unfold occurred in *.
congruence.
- unfold occurred in *. congruence.
Qed.
Lemma InputHandler_Client_Unlock :
forall c sigma,
exists sigma' os ms,
InputHandler (Client c) Unlock sigma = (InputUnlock c, os, sigma', ms).
Proof using.
intros.
unfold InputHandler. unfold ClientIOHandler.
monad_unfold. repeat break_let.
find_inversion. eauto.
Qed.
Lemma InputUnlock_enabled :
forall s c,
lb_step_execution lb_step_async s ->
now (enabled lb_step_async (InputUnlock c)) s.
Proof using.
intros.
destruct s. simpl.
unfold enabled, enabled.
pose proof (InputHandler_Client_Unlock c (nwState (evt_a e) (Client c))).
break_exists.
repeat eexists.
unfold InputHandler in *. unfold ClientIOHandler in *.
eapply LabeledStepAsync_input with (h := (Client c)) (inp := Unlock); eauto.
Qed.
Lemma InputUnlock_continuously_enabled :
forall s c,
lb_step_execution lb_step_async s ->
cont_enabled lb_step_async (InputUnlock c) s.
Proof using.
unfold cont_enabled.
intros.
apply always_continuously.
eapply always_monotonic;
[|eapply always_inv; eauto; eauto using lb_step_execution_invar];
eauto using InputUnlock_enabled.
Qed.
Lemma held_until_Unlock :
forall c s,
lb_step_execution lb_step_async s ->
held (nwState (evt_a (hd s)) (Client c)) = true ->
weak_until (fun s => held (nwState (evt_a (hd s)) (Client c)) = true)
(next (fun s => In (mkPacket (Client c) Server Unlock) (nwPackets (evt_a (hd s)))))
s.
Proof using.
intros c.
cofix CIH.
destruct s. simpl.
intros.
invcs H.
invcs H3.
- coinductive_case CIH.
monad_unfold.
unfold NetHandler in *.
break_match_hyp.
+ find_apply_lem_hyp ClientNetHandler_cases.
repeat find_rewrite. simpl.
intuition;
update_destruct_max_simplify; repeat find_rewrite; auto.
+ find_apply_lem_hyp ServerNetHandler_cases.
repeat find_rewrite. simpl.
intuition; break_exists; intuition;
rewrite_update; repeat find_rewrite; auto.
- monad_unfold.
find_apply_lem_hyp InputHandler_lbcases.
intuition; break_exists; intuition.
+ coinductive_case CIH.
repeat find_rewrite.
simpl.
update_destruct_max_simplify; repeat find_rewrite; auto.
+ subst.
destruct (fin_eq_dec _ c x).
* clear CIH. subst.
apply W0; simpl.
fold LockServ_MultiParams in *. (* typeclass stuff *)
repeat find_rewrite.
simpl. auto.
* coinductive_case CIH.
repeat find_rewrite.
simpl. now rewrite_update.
+ coinductive_case CIH.
clear CIH.
repeat find_rewrite.
simpl.
update_destruct_max_simplify; repeat find_rewrite; auto.
+ coinductive_case CIH. clear CIH.
repeat find_rewrite.
simpl.
update_destruct_max_simplify; repeat find_rewrite; auto.
- coinductive_case CIH.
congruence.
Qed.
Lemma held_eventually_InputUnlock :
forall c s,
lb_step_execution lb_step_async s ->
weak_fairness lb_step_async label_silent s ->
eventually (now (occurred (InputUnlock c))) s.
Proof using.
intros.
pose proof (@InputUnlock_continuously_enabled s c). intuition.
eapply_prop_hyp weak_fairness cont_enabled; [|now unfold label_silent].
solve_by_inversion.
Qed.
Lemma held_eventually_Unlock :
forall s c,
lb_step_execution lb_step_async s ->
weak_fairness lb_step_async label_silent s ->
held (nwState (evt_a (hd s)) (Client c)) = true ->
eventually (fun s => In (mkPacket (Client c) Server Unlock)
(nwPackets (evt_a (hd s)))) s.
Proof using.
intros. apply eventually_next.
match goal with
| H : context [held] |- _ =>
pattern s in H
end.
match goal with
| H1 : ?J1 s, H2 : ?J2 s, H3 : ?J3 s |- _ =>
assert ((J1 /\_ J2 /\_ J3) s) by (now unfold and_tl);
eapply weak_until_eventually with (J := (and_tl J1 (and_tl J2 J3)))
end; simpl in *.
2:now unfold and_tl.
3:eauto using held_eventually_InputUnlock.
- intros. unfold and_tl in *. intuition.
eapply InputUnlock_held; eauto.
- apply weak_until_always; eauto using lb_step_execution_invar, always_inv.
apply weak_until_always; eauto using weak_fairness_invar, always_inv.
eauto using held_until_Unlock.
Qed.
Lemma Locked_enables_MsgLocked :
forall i, message_enables_label
{| pSrc := Server; pDst := Client i; pBody := Locked |}
(MsgLocked i).
Proof using.
unfold message_enables_label, enabled.
intros.
find_apply_lem_hyp in_split.
break_exists_name xs. break_exists_name ys.
do 2 eexists.
eapply LabeledStepAsync_deliver; eauto.
simpl. monad_unfold. simpl. eauto.
Qed.
Lemma Locked_delivered_MsgLocked :
forall i, message_delivered_label
{| pSrc := Server; pDst := Client i; pBody := Locked |}
(MsgLocked i).
Proof using.
unfold message_delivered_label.
intros.
invcs H.
- repeat find_rewrite.
find_eapply_lem_hyp In_split_not_In; eauto. subst.
monad_unfold. simpl in *.
handler_unfold. repeat break_match; repeat find_inversion; auto.
- unfold not in *. find_false.
apply in_app_iff; auto.
- intuition.
Qed.
Lemma Locked_in_network_eventually_MsgLocked :
forall i s,
lb_step_execution lb_step_async s ->
weak_fairness lb_step_async label_silent s ->
In (mkPacket Server (Client i) Locked) (nwPackets (evt_a (hd s))) ->
eventually (now (occurred (MsgLocked i))) s.
Proof using.
intros.
eapply message_labels_eventually_occur;
eauto using Locked_enables_MsgLocked, Locked_delivered_MsgLocked.
unfold label_silent. simpl. congruence.
Qed.
Lemma MsgLocked_held :
forall s c,
lb_step_execution lb_step_async s ->
now (occurred (MsgLocked c)) s ->
next (fun s => held (nwState (evt_a (hd s)) (Client c)) = true) s.
Proof using.
intros.
invcs H.
invcs H1.
- monad_unfold.
unfold NetHandler in *.
break_match_hyp.
+ unfold occurred in *.
fold LockServ_MultiParams in *. (* typeclass stuff *)
repeat find_rewrite. simpl.
find_apply_lem_hyp ClientNetHandler_lbcases; intuition; subst;
update_destruct_max_simplify; congruence.
+ unfold occurred in *.
find_apply_lem_hyp ServerNetHandler_lbcases; intuition;
break_exists; intuition; congruence.
- monad_unfold.
find_apply_lem_hyp InputHandler_lbcases.
intuition; break_exists; intuition; congruence.
- congruence.
Qed.
Lemma eventually_Unlock :
forall n c s,
event_step_star step_async step_async_init (hd s) ->
lb_step_execution lb_step_async s ->
weak_fairness lb_step_async label_silent s ->
Nth (queue (nwState (evt_a (hd s)) Server)) (S n) c ->
exists c,
eventually (fun s => In (mkPacket c Server Unlock) (nwPackets (evt_a (hd s)))) s.
Proof using.
intros.
find_apply_lem_hyp Nth_something_at_head.
break_exists_name holder. break_exists.
exists (Client holder).
remember H0 as Hlbs; clear HeqHlbs.
invcs H0.
find_eapply_lem_hyp head_grant_state_unlock; eauto.
intuition.
- (* eventually the Locked message is delivered, after which this is
the same as the next case. *)
eapply eventually_trans
with (inv := lb_step_execution lb_step_async /\_
weak_fairness
(lb_step_async(labeled_multi_params := LockServ_LabeledParams))
Silent)
(P := now (occurred (MsgLocked holder))).
all:unfold and_tl in *; intuition.
+ eauto using lb_step_execution_invar.
+ eauto using weak_fairness_invar.
+ (* need `now (MsgLocked i) -> held i = true`, then identical to next case below. *)
find_apply_lem_hyp MsgLocked_held; eauto.
destruct s.
simpl in *.
eauto using lb_step_execution_invar, weak_fairness_invar,
E_next, held_eventually_Unlock.
+ apply Locked_in_network_eventually_MsgLocked; auto.
- eauto using held_eventually_Unlock.
- eauto using E0.
Qed.
Lemma eventually_MsgUnlock :
forall n c s,
event_step_star step_async step_async_init (hd s) ->
lb_step_execution lb_step_async s ->
weak_fairness lb_step_async label_silent s ->
Nth (queue (nwState (evt_a (hd s)) Server)) (S n) c ->
eventually (now (occurred MsgUnlock)) s.
Proof using.
intros n c s Hstar Hexec Hfair HNth.
pattern s in Hexec. pattern s in Hfair.
find_copy_eapply_lem_hyp eventually_Unlock; eauto.
break_exists.
match goal with
| H1 : (fun x => ?J1) s, H2 : (fun x => ?J2) s |- _ =>
assert (and_tl (fun x => J1) (fun x => J2) s) as Hand by (now unfold and_tl);
clear H1; clear H2
end; simpl in *.
eapply eventually_trans.
4:eauto. 3:apply Hand.
2:intros; eapply Unlock_in_network_eventually_MsgUnlock.
all:unfold and_tl in *; intuition eauto.
- eauto using lb_step_execution_invar.
- simpl. eauto using weak_fairness_invar.
Qed.
(* Sketch: eventually an Unlock happens, so eventually a MsgUnlock
happens, so eventually a client moves up the queue. when this
happens, the server will send it a Locked msg if it's at the
head.
Gonna use weak_until_eventually and probs eventually_next
*)
Lemma clients_move_up_in_queue :
forall n c s,
event_step_star step_async step_async_init (hd s) ->
lb_step_execution lb_step_async s ->
weak_fairness lb_step_async label_silent s ->
Nth (queue (nwState (evt_a (hd s)) Server)) (S n) c ->
eventually (fun s => Nth (queue (nwState (evt_a (hd s)) Server)) n c
/\ (n = 0 -> In (mkPacket Server (Client c) Locked)
(nwPackets (evt_a (hd s)))))
s.
Proof using.
intros n c s Hstar Hexec Hfair HNth.
apply eventually_next.
pattern s in HNth.
match goal with
| H1 : ?J1 s, H2 : ?J2 s, H3 : ?J3 s |- _ =>
assert ((J1 /\_ J2 /\_ J3) s) by (now unfold and_tl);
eapply weak_until_eventually with (J := (and_tl J1 (and_tl J2 J3)))
end; simpl in *.
2:now unfold and_tl.
3:eauto using eventually_MsgUnlock.
- intros. unfold and_tl in *. intuition.
eapply MsgUnlock_moves_client; eauto.
- apply weak_until_always; eauto using lb_step_execution_invar, always_inv.
apply weak_until_always; eauto using weak_fairness_invar, always_inv.
eauto using clients_only_move_up_in_queue.
Qed.
Lemma clients_move_way_up_in_queue :
forall n n' c s,
n' <= n ->
event_step_star step_async step_async_init (hd s) ->
lb_step_execution lb_step_async s ->
weak_fairness lb_step_async label_silent s ->
(Nth (queue (nwState (evt_a (hd s)) Server)) (S n) c
/\ (S n = 0 -> In (mkPacket Server (Client c) Locked)
(nwPackets (evt_a (hd s))))) ->
eventually (fun s => Nth (queue (nwState (evt_a (hd s)) Server)) n' c
/\ (n' = 0 -> In (mkPacket Server (Client c) Locked)
(nwPackets (evt_a (hd s)))))
s.
Proof using.
induction n; intros; simpl in *; auto.
- intuition.
assert (n' = 0) by lia. subst.
eauto using clients_move_up_in_queue.
- match goal with
| H : _ (hd s) |- _ =>
pattern s in H
end.
match goal with
| H1 : ?J1 s, H2 : ?J2 s, H3 : ?J3 s |- _ =>
assert ((J1 /\_ J2 /\_ J3) s) as Hand by (now unfold and_tl);
clear H1; clear H2; clear H3
end; simpl in *.
find_apply_lem_hyp le_lt_eq_dec. intuition.
+ assert (n' <= n) by lia.
find_eapply_lem_hyp clients_move_up_in_queue; eauto;
try solve [unfold and_tl in *; intuition]; [idtac].
eapply eventually_trans. 4:eauto.
3:apply Hand. all:unfold and_tl in *.
all:intuition eauto using lb_step_execution_invar, weak_fairness_invar.
find_apply_lem_hyp step_async_star_lb_step_execution; auto.
destruct s0. simpl in *.
find_apply_lem_hyp always_Cons.
intuition.
find_apply_lem_hyp always_Cons.
intuition.
+ subst. unfold and_tl in *. intuition.
eauto using clients_move_up_in_queue.
Qed.
Lemma clients_get_lock_messages :
forall n c s,
event_step_star step_async step_async_init (hd s) ->
lb_step_execution lb_step_async s ->
weak_fairness lb_step_async label_silent s ->
Nth (queue (nwState (evt_a (hd s)) Server)) (S n) c ->
eventually (fun s =>
In (mkPacket Server (Client c) Locked)
(nwPackets (evt_a (hd s)))) s.
Proof using.
intros.
pose proof (@clients_move_way_up_in_queue n 0 c s).
pose proof (Nat.le_0_l n).
repeat concludes. conclude_using ltac:(intuition; congruence).
eapply eventually_monotonic_simple; [|eauto].
intros. simpl in *. intuition.
Qed.
Lemma InputLock_Lock :
forall s c,
lb_step_execution lb_step_async s ->
now (occurred (InputLock c)) s ->
next (fun s => In (mkPacket (Client c) Server Lock) (nwPackets (evt_a (hd s)))) s.
Proof using.
intros.
invcs H.
invcs H1.
- monad_unfold.
unfold NetHandler in *.
break_match_hyp.
+ unfold occurred in *.
find_apply_lem_hyp ClientNetHandler_lbcases; intuition; congruence.
+ unfold occurred in *.
find_apply_lem_hyp ServerNetHandler_lbcases; intuition;
break_exists; intuition; congruence.
- monad_unfold.
find_apply_lem_hyp InputHandler_lbcases.
intuition; try congruence.
break_exists. intuition; try congruence.
fold LockServ_MultiParams in *. (* typeclass stuff *)
repeat find_rewrite.
simpl. left. unfold occurred in *.
congruence.
- unfold occurred in *. congruence.
Qed.
Lemma Lock_in_network_eventually_MsgLock :
forall c s,
lb_step_execution lb_step_async s ->
weak_fairness lb_step_async label_silent s ->
In (mkPacket (Client c) Server Lock) (nwPackets (evt_a (hd s))) ->
eventually (now (occurred (MsgLock c))) s.
Proof using.
intros.
eapply message_labels_eventually_occur;
eauto using Lock_enables_MsgLock, Lock_delivered_MsgLock.
unfold label_silent. simpl. congruence.
Qed.
Lemma InputLock_eventually_MsgLock :
forall c s,
lb_step_execution lb_step_async s ->
weak_fairness lb_step_async label_silent s ->
now (occurred (InputLock c)) s ->
eventually (now (occurred (MsgLock c))) s.
Proof using.
intros.
find_apply_lem_hyp InputLock_Lock; auto.
destruct s.
simpl in *.
eauto using E_next, Lock_in_network_eventually_MsgLock,
lb_step_execution_invar, weak_fairness_invar.
Qed.
Lemma Nth_snoc :
forall A (l : list A) x,
Nth (l ++ [x]) (length l) x.
Proof using.
intros.
induction l; simpl in *; constructor; auto.
Qed.
Lemma MsgLock_in_queue_or_Locked :
forall c s,
lb_step_execution lb_step_async s ->
weak_fairness lb_step_async label_silent s ->
now (occurred (MsgLock c)) s ->
next (fun s =>
In (mkPacket Server (Client c) Locked)
(nwPackets (evt_a (hd s)))) s \/
exists n,
next (fun s =>
Nth (queue (nwState (evt_a (hd s)) Server)) (S n) c) s.
Proof using.
intros.
invcs H.
invcs H2.
- monad_unfold.
unfold NetHandler in *.
break_match_hyp.
+ unfold occurred in *.
find_apply_lem_hyp ClientNetHandler_lbcases; intuition; congruence.
+ unfold occurred in *.
find_apply_lem_hyp ServerNetHandler_lbcases; intuition;
break_exists; intuition; try congruence; [left|right];
fold LockServ_MultiParams in *; (* typeclass stuff *)
repeat find_rewrite; simpl.
* left. congruence.
* update_destruct_max_simplify; try congruence.
find_inversion.
repeat find_rewrite.
destruct (queue (nwState (evt_a e) Server)) eqn:?; try congruence.
exists (length l). simpl.
constructor.
apply Nth_snoc.
- monad_unfold.
find_apply_lem_hyp InputHandler_lbcases.
intuition; try congruence.
break_exists. intuition; congruence.
- unfold occurred in *. congruence.
Qed.
Lemma MsgLock_Locked :
forall c s,
event_step_star step_async step_async_init (hd s) ->
lb_step_execution lb_step_async s ->
weak_fairness lb_step_async label_silent s ->
now (occurred (MsgLock c)) s ->
eventually
(fun s => In (mkPacket Server (Client c) Locked)
(nwPackets (evt_a (hd s)))) s.
Proof using.
intros.
find_apply_lem_hyp MsgLock_in_queue_or_Locked; auto.
intuition.
- destruct s; simpl in *; eauto using E_next, E0.
- break_exists.
destruct s; simpl in *.
apply E_next.
eapply clients_get_lock_messages;
eauto using lb_step_execution_invar,
weak_fairness_invar.
find_apply_lem_hyp step_async_star_lb_step_execution; auto.
destruct s. simpl.
do 2 (find_apply_lem_hyp always_Cons; intuition).
Qed.
Lemma MsgLock_eventually_MsgLocked :
forall c s,
event_step_star step_async step_async_init (hd s) ->
lb_step_execution lb_step_async s ->
weak_fairness lb_step_async label_silent s ->
now (occurred (MsgLock c)) s ->
eventually (now (occurred (MsgLocked c))) s.
Proof using.
intros c s Hss Hlbs Hfair.
match goal with
| H : _ (hd s) |- _ =>
pattern s in H
end.
match goal with
| H1 : ?J1 s, H2 : ?J2 s, H3 : ?J3 s |- _ =>
assert ((J1 /\_ J2 /\_ J3) s) as Hand by (now unfold and_tl);
clear H1; clear H2; clear H3
end; simpl in *. intros.
eapply eventually_trans.
4:eapply MsgLock_Locked; eauto; unfold and_tl in *; intuition.
3:apply Hand. all:unfold and_tl in *.
all:intuition eauto using lb_step_execution_invar, weak_fairness_invar.
- find_apply_lem_hyp step_async_star_lb_step_execution; auto.
destruct s0. simpl in *.
find_apply_lem_hyp always_Cons.
intuition.
find_apply_lem_hyp always_Cons.
intuition.
- eauto using Locked_in_network_eventually_MsgLocked.
Qed.
(* label-based correctness theorem *)
Theorem locking_clients_eventually_receive_lock_lb :
forall c s,
event_step_star step_async step_async_init (hd s) ->
lb_step_execution lb_step_async s ->
weak_fairness lb_step_async label_silent s ->
now (occurred (InputLock c)) s ->
eventually (now (occurred (MsgLocked c))) s.
Proof using.
intros c s Hss Hlbs Hfair.
match goal with
| H : _ (hd s) |- _ =>
pattern s in H
end.
match goal with
| H1 : ?J1 s, H2 : ?J2 s, H3 : ?J3 s |- _ =>
assert ((J1 /\_ J2 /\_ J3) s) as Hand by (now unfold and_tl);
clear H1; clear H2; clear H3
end; simpl in *. intros.
eapply eventually_trans.
4:eapply InputLock_eventually_MsgLock; eauto; unfold and_tl in *; intuition.
3:apply Hand. all:unfold and_tl in *.
all:intuition eauto using lb_step_execution_invar, weak_fairness_invar.
- find_apply_lem_hyp step_async_star_lb_step_execution; auto.
destruct s0. simpl in *.
find_apply_lem_hyp always_Cons.
intuition.
find_apply_lem_hyp always_Cons.
intuition.
- eauto using MsgLock_eventually_MsgLocked.
Qed.
(* label + state-based correctness theorem *)
Theorem locking_clients_eventually_receive_lock_st :
forall c s,
event_step_star step_async step_async_init (hd s) ->
lb_step_execution lb_step_async s ->
weak_fairness lb_step_async label_silent s ->
now (occurred (InputLock c)) s ->
eventually (fun s => held (nwState (evt_a (hd s)) (Client c)) = true) s.
Proof using.
intros.
find_eapply_lem_hyp locking_clients_eventually_receive_lock_lb; eauto.
apply eventually_next.
eapply eventually_monotonic with (J := lb_step_execution lb_step_async).
4:eauto.
all:eauto using lb_step_execution_invar.
eauto using MsgLocked_held.
Qed.
End LockServ.
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_t_e
//
// Generated
// by: wig
// on: Mon Jun 26 16:51:35 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../open.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_t_e.v,v 1.4 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: inst_t_e.v,v $
// Revision 1.4 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_t_e
//
// No user `defines in this module
module inst_t_e
//
// Generated Module inst_t
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [2:0] non_open;
wire non_open_bit;
wire [3:0] wire_open;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
inst_a_e inst_a (
.open_bit(),
.open_bus(),
.open_bus_9(),
.open_in_bit_11(),
.open_in_bus_10(),
.open_part12({ non_open_bit, 3'bz, non_open }), // __W_PORT // from 5 to 3 // __W_PORT // __I_BIT_TO_BUSPORT // __I_COMBINE_SPLICES
.open_part13({ 1'bz, non_open_bit, 1'bz, 1'bz, non_open }), // __W_PORT // __I_BIT_TO_BUSPORT (x4) // __I_COMBINE_SPLICES
.openport14(), // check width and type
.wire_open({ 2'bz, wire_open }), // __W_PORT (x2) // __I_COMBINE_SPLICES
.wire_open_in(wire_open)
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
inst_b_e inst_b (
.mix_key_open(), // replace name
.non_open(non_open),
.non_open_bit(non_open_bit),
.open_bit_2(),
.open_bit_3(),
.open_bit_4()
);
// End of Generated Instance Port Map for inst_b
endmodule
//
// End of Generated Module rtl of inst_t_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__SDFXBP_BEHAVIORAL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXBP_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O31AI_BEHAVIORAL_PP_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o31ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31AI_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 14:31:45 05/12/2016
// Design Name:
// Module Name: identificador_teclas
// Project Name:
// Target Devices:
// Tool versions:
// Description: FSM que evalúa la detección el "break code" F0, y extraer codigo de la tecla correspondiente (código siguiente)
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module identificador_teclas
(
input wire clk, reset,
input wire rx_done_tick,
input wire [7:0] dout,//Utilizar solo los bits que realmente contienen el código de la tecla
output reg gotten_code_flag //Bandera para actualizar el FIFO
);
//Declaración de constantes
localparam break_code = 8'hF0;
//Declaración simbólica de estados
localparam wait_break_code = 1'b0;
localparam get_code = 1'b1;
//Declaración de señales
reg state_next, state_reg;
//=================================================
// FSM
//=================================================
// Estado FSM y registros de datos
always @(posedge clk, posedge reset)
if (reset)
state_reg <= wait_break_code;
else
state_reg <= state_next;
// Lógica de siguiente estado siguiente de la FSM
always @*
begin
gotten_code_flag = 1'b0;
state_next = state_reg;
case (state_reg)
wait_break_code: // Espera "break code"
if (rx_done_tick == 1'b1 && dout == break_code)
state_next = get_code;
get_code: // Obtener el próximo código
if (rx_done_tick)
begin
gotten_code_flag =1'b1;
state_next = wait_break_code;
end
endcase
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_dtl_vref.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_dtl_vref (/*AUTOARG*/
// Inputs
vref_impctl, vddo
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output vref_impctl;
input vddo; // From cluster_header0 of cluster_header.v
assign vref_impctl = 1'b1;
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAM16_s36_s36_altera.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altsyncram ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" DEVICE_FAMILY="Stratix II" INDATA_REG_B="CLOCK1" NUMWORDS_A=1024 NUMWORDS_B=1024 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" WIDTH_A=32 WIDTH_B=32 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=10 WIDTHAD_B=10 WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 data_a data_b q_a q_b wren_a wren_b
//VERSION_BEGIN 11.1 cbx_altsyncram 2011:10:31:21:11:05:SJ cbx_cycloneii 2011:10:31:21:11:05:SJ cbx_lpm_add_sub 2011:10:31:21:11:05:SJ cbx_lpm_compare 2011:10:31:21:11:05:SJ cbx_lpm_decode 2011:10:31:21:11:05:SJ cbx_lpm_mux 2011:10:31:21:11:05:SJ cbx_mgl 2011:10:31:21:12:31:SJ cbx_stratix 2011:10:31:21:11:05:SJ cbx_stratixii 2011:10:31:21:11:05:SJ cbx_stratixiii 2011:10:31:21:11:05:SJ cbx_stratixv 2011:10:31:21:11:05:SJ cbx_util_mgl 2011:10:31:21:11:05:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = ram_bits (AUTO) 32768
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"} *)
module RAM16_s36_s36_altera_altsyncram
(
address_a,
address_b,
clock0,
clock1,
data_a,
data_b,
q_a,
q_b,
wren_a,
wren_b) /* synthesis synthesis_clearbox=1 */;
input [9:0] address_a;
input [9:0] address_b;
input clock0;
input clock1;
input [31:0] data_a;
input [31:0] data_b;
output [31:0] q_a;
output [31:0] q_b;
input wren_a;
input wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [9:0] address_b;
tri1 clock0;
tri1 clock1;
tri1 [31:0] data_a;
tri1 [31:0] data_b;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] wire_ram_block1a_0portadataout;
wire [0:0] wire_ram_block1a_1portadataout;
wire [0:0] wire_ram_block1a_2portadataout;
wire [0:0] wire_ram_block1a_3portadataout;
wire [0:0] wire_ram_block1a_4portadataout;
wire [0:0] wire_ram_block1a_5portadataout;
wire [0:0] wire_ram_block1a_6portadataout;
wire [0:0] wire_ram_block1a_7portadataout;
wire [0:0] wire_ram_block1a_8portadataout;
wire [0:0] wire_ram_block1a_9portadataout;
wire [0:0] wire_ram_block1a_10portadataout;
wire [0:0] wire_ram_block1a_11portadataout;
wire [0:0] wire_ram_block1a_12portadataout;
wire [0:0] wire_ram_block1a_13portadataout;
wire [0:0] wire_ram_block1a_14portadataout;
wire [0:0] wire_ram_block1a_15portadataout;
wire [0:0] wire_ram_block1a_16portadataout;
wire [0:0] wire_ram_block1a_17portadataout;
wire [0:0] wire_ram_block1a_18portadataout;
wire [0:0] wire_ram_block1a_19portadataout;
wire [0:0] wire_ram_block1a_20portadataout;
wire [0:0] wire_ram_block1a_21portadataout;
wire [0:0] wire_ram_block1a_22portadataout;
wire [0:0] wire_ram_block1a_23portadataout;
wire [0:0] wire_ram_block1a_24portadataout;
wire [0:0] wire_ram_block1a_25portadataout;
wire [0:0] wire_ram_block1a_26portadataout;
wire [0:0] wire_ram_block1a_27portadataout;
wire [0:0] wire_ram_block1a_28portadataout;
wire [0:0] wire_ram_block1a_29portadataout;
wire [0:0] wire_ram_block1a_30portadataout;
wire [0:0] wire_ram_block1a_31portadataout;
wire [0:0] wire_ram_block1a_0portbdataout;
wire [0:0] wire_ram_block1a_1portbdataout;
wire [0:0] wire_ram_block1a_2portbdataout;
wire [0:0] wire_ram_block1a_3portbdataout;
wire [0:0] wire_ram_block1a_4portbdataout;
wire [0:0] wire_ram_block1a_5portbdataout;
wire [0:0] wire_ram_block1a_6portbdataout;
wire [0:0] wire_ram_block1a_7portbdataout;
wire [0:0] wire_ram_block1a_8portbdataout;
wire [0:0] wire_ram_block1a_9portbdataout;
wire [0:0] wire_ram_block1a_10portbdataout;
wire [0:0] wire_ram_block1a_11portbdataout;
wire [0:0] wire_ram_block1a_12portbdataout;
wire [0:0] wire_ram_block1a_13portbdataout;
wire [0:0] wire_ram_block1a_14portbdataout;
wire [0:0] wire_ram_block1a_15portbdataout;
wire [0:0] wire_ram_block1a_16portbdataout;
wire [0:0] wire_ram_block1a_17portbdataout;
wire [0:0] wire_ram_block1a_18portbdataout;
wire [0:0] wire_ram_block1a_19portbdataout;
wire [0:0] wire_ram_block1a_20portbdataout;
wire [0:0] wire_ram_block1a_21portbdataout;
wire [0:0] wire_ram_block1a_22portbdataout;
wire [0:0] wire_ram_block1a_23portbdataout;
wire [0:0] wire_ram_block1a_24portbdataout;
wire [0:0] wire_ram_block1a_25portbdataout;
wire [0:0] wire_ram_block1a_26portbdataout;
wire [0:0] wire_ram_block1a_27portbdataout;
wire [0:0] wire_ram_block1a_28portbdataout;
wire [0:0] wire_ram_block1a_29portbdataout;
wire [0:0] wire_ram_block1a_30portbdataout;
wire [0:0] wire_ram_block1a_31portbdataout;
wire [9:0] address_a_wire;
wire [9:0] address_b_wire;
stratixii_ram_block ram_block1a_0
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[0]}),
.portadataout(wire_ram_block1a_0portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[0]}),
.portbdataout(wire_ram_block1a_0portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_0.connectivity_checking = "OFF",
ram_block1a_0.logical_ram_name = "ALTSYNCRAM",
ram_block1a_0.mixed_port_feed_through_mode = "dont_care",
ram_block1a_0.operation_mode = "bidir_dual_port",
ram_block1a_0.port_a_address_width = 10,
ram_block1a_0.port_a_data_width = 1,
ram_block1a_0.port_a_disable_ce_on_input_registers = "on",
ram_block1a_0.port_a_disable_ce_on_output_registers = "on",
ram_block1a_0.port_a_first_address = 0,
ram_block1a_0.port_a_first_bit_number = 0,
ram_block1a_0.port_a_last_address = 1023,
ram_block1a_0.port_a_logical_ram_depth = 1024,
ram_block1a_0.port_a_logical_ram_width = 32,
ram_block1a_0.port_b_address_clock = "clock1",
ram_block1a_0.port_b_address_width = 10,
ram_block1a_0.port_b_data_in_clock = "clock1",
ram_block1a_0.port_b_data_width = 1,
ram_block1a_0.port_b_disable_ce_on_input_registers = "on",
ram_block1a_0.port_b_disable_ce_on_output_registers = "on",
ram_block1a_0.port_b_first_address = 0,
ram_block1a_0.port_b_first_bit_number = 0,
ram_block1a_0.port_b_last_address = 1023,
ram_block1a_0.port_b_logical_ram_depth = 1024,
ram_block1a_0.port_b_logical_ram_width = 32,
ram_block1a_0.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_0.power_up_uninitialized = "false",
ram_block1a_0.ram_block_type = "AUTO",
ram_block1a_0.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_1
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[1]}),
.portadataout(wire_ram_block1a_1portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[1]}),
.portbdataout(wire_ram_block1a_1portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_1.connectivity_checking = "OFF",
ram_block1a_1.logical_ram_name = "ALTSYNCRAM",
ram_block1a_1.mixed_port_feed_through_mode = "dont_care",
ram_block1a_1.operation_mode = "bidir_dual_port",
ram_block1a_1.port_a_address_width = 10,
ram_block1a_1.port_a_data_width = 1,
ram_block1a_1.port_a_disable_ce_on_input_registers = "on",
ram_block1a_1.port_a_disable_ce_on_output_registers = "on",
ram_block1a_1.port_a_first_address = 0,
ram_block1a_1.port_a_first_bit_number = 1,
ram_block1a_1.port_a_last_address = 1023,
ram_block1a_1.port_a_logical_ram_depth = 1024,
ram_block1a_1.port_a_logical_ram_width = 32,
ram_block1a_1.port_b_address_clock = "clock1",
ram_block1a_1.port_b_address_width = 10,
ram_block1a_1.port_b_data_in_clock = "clock1",
ram_block1a_1.port_b_data_width = 1,
ram_block1a_1.port_b_disable_ce_on_input_registers = "on",
ram_block1a_1.port_b_disable_ce_on_output_registers = "on",
ram_block1a_1.port_b_first_address = 0,
ram_block1a_1.port_b_first_bit_number = 1,
ram_block1a_1.port_b_last_address = 1023,
ram_block1a_1.port_b_logical_ram_depth = 1024,
ram_block1a_1.port_b_logical_ram_width = 32,
ram_block1a_1.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_1.power_up_uninitialized = "false",
ram_block1a_1.ram_block_type = "AUTO",
ram_block1a_1.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_2
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[2]}),
.portadataout(wire_ram_block1a_2portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[2]}),
.portbdataout(wire_ram_block1a_2portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_2.connectivity_checking = "OFF",
ram_block1a_2.logical_ram_name = "ALTSYNCRAM",
ram_block1a_2.mixed_port_feed_through_mode = "dont_care",
ram_block1a_2.operation_mode = "bidir_dual_port",
ram_block1a_2.port_a_address_width = 10,
ram_block1a_2.port_a_data_width = 1,
ram_block1a_2.port_a_disable_ce_on_input_registers = "on",
ram_block1a_2.port_a_disable_ce_on_output_registers = "on",
ram_block1a_2.port_a_first_address = 0,
ram_block1a_2.port_a_first_bit_number = 2,
ram_block1a_2.port_a_last_address = 1023,
ram_block1a_2.port_a_logical_ram_depth = 1024,
ram_block1a_2.port_a_logical_ram_width = 32,
ram_block1a_2.port_b_address_clock = "clock1",
ram_block1a_2.port_b_address_width = 10,
ram_block1a_2.port_b_data_in_clock = "clock1",
ram_block1a_2.port_b_data_width = 1,
ram_block1a_2.port_b_disable_ce_on_input_registers = "on",
ram_block1a_2.port_b_disable_ce_on_output_registers = "on",
ram_block1a_2.port_b_first_address = 0,
ram_block1a_2.port_b_first_bit_number = 2,
ram_block1a_2.port_b_last_address = 1023,
ram_block1a_2.port_b_logical_ram_depth = 1024,
ram_block1a_2.port_b_logical_ram_width = 32,
ram_block1a_2.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_2.power_up_uninitialized = "false",
ram_block1a_2.ram_block_type = "AUTO",
ram_block1a_2.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_3
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[3]}),
.portadataout(wire_ram_block1a_3portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[3]}),
.portbdataout(wire_ram_block1a_3portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_3.connectivity_checking = "OFF",
ram_block1a_3.logical_ram_name = "ALTSYNCRAM",
ram_block1a_3.mixed_port_feed_through_mode = "dont_care",
ram_block1a_3.operation_mode = "bidir_dual_port",
ram_block1a_3.port_a_address_width = 10,
ram_block1a_3.port_a_data_width = 1,
ram_block1a_3.port_a_disable_ce_on_input_registers = "on",
ram_block1a_3.port_a_disable_ce_on_output_registers = "on",
ram_block1a_3.port_a_first_address = 0,
ram_block1a_3.port_a_first_bit_number = 3,
ram_block1a_3.port_a_last_address = 1023,
ram_block1a_3.port_a_logical_ram_depth = 1024,
ram_block1a_3.port_a_logical_ram_width = 32,
ram_block1a_3.port_b_address_clock = "clock1",
ram_block1a_3.port_b_address_width = 10,
ram_block1a_3.port_b_data_in_clock = "clock1",
ram_block1a_3.port_b_data_width = 1,
ram_block1a_3.port_b_disable_ce_on_input_registers = "on",
ram_block1a_3.port_b_disable_ce_on_output_registers = "on",
ram_block1a_3.port_b_first_address = 0,
ram_block1a_3.port_b_first_bit_number = 3,
ram_block1a_3.port_b_last_address = 1023,
ram_block1a_3.port_b_logical_ram_depth = 1024,
ram_block1a_3.port_b_logical_ram_width = 32,
ram_block1a_3.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_3.power_up_uninitialized = "false",
ram_block1a_3.ram_block_type = "AUTO",
ram_block1a_3.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_4
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[4]}),
.portadataout(wire_ram_block1a_4portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[4]}),
.portbdataout(wire_ram_block1a_4portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_4.connectivity_checking = "OFF",
ram_block1a_4.logical_ram_name = "ALTSYNCRAM",
ram_block1a_4.mixed_port_feed_through_mode = "dont_care",
ram_block1a_4.operation_mode = "bidir_dual_port",
ram_block1a_4.port_a_address_width = 10,
ram_block1a_4.port_a_data_width = 1,
ram_block1a_4.port_a_disable_ce_on_input_registers = "on",
ram_block1a_4.port_a_disable_ce_on_output_registers = "on",
ram_block1a_4.port_a_first_address = 0,
ram_block1a_4.port_a_first_bit_number = 4,
ram_block1a_4.port_a_last_address = 1023,
ram_block1a_4.port_a_logical_ram_depth = 1024,
ram_block1a_4.port_a_logical_ram_width = 32,
ram_block1a_4.port_b_address_clock = "clock1",
ram_block1a_4.port_b_address_width = 10,
ram_block1a_4.port_b_data_in_clock = "clock1",
ram_block1a_4.port_b_data_width = 1,
ram_block1a_4.port_b_disable_ce_on_input_registers = "on",
ram_block1a_4.port_b_disable_ce_on_output_registers = "on",
ram_block1a_4.port_b_first_address = 0,
ram_block1a_4.port_b_first_bit_number = 4,
ram_block1a_4.port_b_last_address = 1023,
ram_block1a_4.port_b_logical_ram_depth = 1024,
ram_block1a_4.port_b_logical_ram_width = 32,
ram_block1a_4.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_4.power_up_uninitialized = "false",
ram_block1a_4.ram_block_type = "AUTO",
ram_block1a_4.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_5
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[5]}),
.portadataout(wire_ram_block1a_5portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[5]}),
.portbdataout(wire_ram_block1a_5portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_5.connectivity_checking = "OFF",
ram_block1a_5.logical_ram_name = "ALTSYNCRAM",
ram_block1a_5.mixed_port_feed_through_mode = "dont_care",
ram_block1a_5.operation_mode = "bidir_dual_port",
ram_block1a_5.port_a_address_width = 10,
ram_block1a_5.port_a_data_width = 1,
ram_block1a_5.port_a_disable_ce_on_input_registers = "on",
ram_block1a_5.port_a_disable_ce_on_output_registers = "on",
ram_block1a_5.port_a_first_address = 0,
ram_block1a_5.port_a_first_bit_number = 5,
ram_block1a_5.port_a_last_address = 1023,
ram_block1a_5.port_a_logical_ram_depth = 1024,
ram_block1a_5.port_a_logical_ram_width = 32,
ram_block1a_5.port_b_address_clock = "clock1",
ram_block1a_5.port_b_address_width = 10,
ram_block1a_5.port_b_data_in_clock = "clock1",
ram_block1a_5.port_b_data_width = 1,
ram_block1a_5.port_b_disable_ce_on_input_registers = "on",
ram_block1a_5.port_b_disable_ce_on_output_registers = "on",
ram_block1a_5.port_b_first_address = 0,
ram_block1a_5.port_b_first_bit_number = 5,
ram_block1a_5.port_b_last_address = 1023,
ram_block1a_5.port_b_logical_ram_depth = 1024,
ram_block1a_5.port_b_logical_ram_width = 32,
ram_block1a_5.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_5.power_up_uninitialized = "false",
ram_block1a_5.ram_block_type = "AUTO",
ram_block1a_5.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_6
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[6]}),
.portadataout(wire_ram_block1a_6portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[6]}),
.portbdataout(wire_ram_block1a_6portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_6.connectivity_checking = "OFF",
ram_block1a_6.logical_ram_name = "ALTSYNCRAM",
ram_block1a_6.mixed_port_feed_through_mode = "dont_care",
ram_block1a_6.operation_mode = "bidir_dual_port",
ram_block1a_6.port_a_address_width = 10,
ram_block1a_6.port_a_data_width = 1,
ram_block1a_6.port_a_disable_ce_on_input_registers = "on",
ram_block1a_6.port_a_disable_ce_on_output_registers = "on",
ram_block1a_6.port_a_first_address = 0,
ram_block1a_6.port_a_first_bit_number = 6,
ram_block1a_6.port_a_last_address = 1023,
ram_block1a_6.port_a_logical_ram_depth = 1024,
ram_block1a_6.port_a_logical_ram_width = 32,
ram_block1a_6.port_b_address_clock = "clock1",
ram_block1a_6.port_b_address_width = 10,
ram_block1a_6.port_b_data_in_clock = "clock1",
ram_block1a_6.port_b_data_width = 1,
ram_block1a_6.port_b_disable_ce_on_input_registers = "on",
ram_block1a_6.port_b_disable_ce_on_output_registers = "on",
ram_block1a_6.port_b_first_address = 0,
ram_block1a_6.port_b_first_bit_number = 6,
ram_block1a_6.port_b_last_address = 1023,
ram_block1a_6.port_b_logical_ram_depth = 1024,
ram_block1a_6.port_b_logical_ram_width = 32,
ram_block1a_6.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_6.power_up_uninitialized = "false",
ram_block1a_6.ram_block_type = "AUTO",
ram_block1a_6.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_7
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[7]}),
.portadataout(wire_ram_block1a_7portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[7]}),
.portbdataout(wire_ram_block1a_7portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_7.connectivity_checking = "OFF",
ram_block1a_7.logical_ram_name = "ALTSYNCRAM",
ram_block1a_7.mixed_port_feed_through_mode = "dont_care",
ram_block1a_7.operation_mode = "bidir_dual_port",
ram_block1a_7.port_a_address_width = 10,
ram_block1a_7.port_a_data_width = 1,
ram_block1a_7.port_a_disable_ce_on_input_registers = "on",
ram_block1a_7.port_a_disable_ce_on_output_registers = "on",
ram_block1a_7.port_a_first_address = 0,
ram_block1a_7.port_a_first_bit_number = 7,
ram_block1a_7.port_a_last_address = 1023,
ram_block1a_7.port_a_logical_ram_depth = 1024,
ram_block1a_7.port_a_logical_ram_width = 32,
ram_block1a_7.port_b_address_clock = "clock1",
ram_block1a_7.port_b_address_width = 10,
ram_block1a_7.port_b_data_in_clock = "clock1",
ram_block1a_7.port_b_data_width = 1,
ram_block1a_7.port_b_disable_ce_on_input_registers = "on",
ram_block1a_7.port_b_disable_ce_on_output_registers = "on",
ram_block1a_7.port_b_first_address = 0,
ram_block1a_7.port_b_first_bit_number = 7,
ram_block1a_7.port_b_last_address = 1023,
ram_block1a_7.port_b_logical_ram_depth = 1024,
ram_block1a_7.port_b_logical_ram_width = 32,
ram_block1a_7.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_7.power_up_uninitialized = "false",
ram_block1a_7.ram_block_type = "AUTO",
ram_block1a_7.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_8
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[8]}),
.portadataout(wire_ram_block1a_8portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[8]}),
.portbdataout(wire_ram_block1a_8portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_8.connectivity_checking = "OFF",
ram_block1a_8.logical_ram_name = "ALTSYNCRAM",
ram_block1a_8.mixed_port_feed_through_mode = "dont_care",
ram_block1a_8.operation_mode = "bidir_dual_port",
ram_block1a_8.port_a_address_width = 10,
ram_block1a_8.port_a_data_width = 1,
ram_block1a_8.port_a_disable_ce_on_input_registers = "on",
ram_block1a_8.port_a_disable_ce_on_output_registers = "on",
ram_block1a_8.port_a_first_address = 0,
ram_block1a_8.port_a_first_bit_number = 8,
ram_block1a_8.port_a_last_address = 1023,
ram_block1a_8.port_a_logical_ram_depth = 1024,
ram_block1a_8.port_a_logical_ram_width = 32,
ram_block1a_8.port_b_address_clock = "clock1",
ram_block1a_8.port_b_address_width = 10,
ram_block1a_8.port_b_data_in_clock = "clock1",
ram_block1a_8.port_b_data_width = 1,
ram_block1a_8.port_b_disable_ce_on_input_registers = "on",
ram_block1a_8.port_b_disable_ce_on_output_registers = "on",
ram_block1a_8.port_b_first_address = 0,
ram_block1a_8.port_b_first_bit_number = 8,
ram_block1a_8.port_b_last_address = 1023,
ram_block1a_8.port_b_logical_ram_depth = 1024,
ram_block1a_8.port_b_logical_ram_width = 32,
ram_block1a_8.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_8.power_up_uninitialized = "false",
ram_block1a_8.ram_block_type = "AUTO",
ram_block1a_8.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_9
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[9]}),
.portadataout(wire_ram_block1a_9portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[9]}),
.portbdataout(wire_ram_block1a_9portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_9.connectivity_checking = "OFF",
ram_block1a_9.logical_ram_name = "ALTSYNCRAM",
ram_block1a_9.mixed_port_feed_through_mode = "dont_care",
ram_block1a_9.operation_mode = "bidir_dual_port",
ram_block1a_9.port_a_address_width = 10,
ram_block1a_9.port_a_data_width = 1,
ram_block1a_9.port_a_disable_ce_on_input_registers = "on",
ram_block1a_9.port_a_disable_ce_on_output_registers = "on",
ram_block1a_9.port_a_first_address = 0,
ram_block1a_9.port_a_first_bit_number = 9,
ram_block1a_9.port_a_last_address = 1023,
ram_block1a_9.port_a_logical_ram_depth = 1024,
ram_block1a_9.port_a_logical_ram_width = 32,
ram_block1a_9.port_b_address_clock = "clock1",
ram_block1a_9.port_b_address_width = 10,
ram_block1a_9.port_b_data_in_clock = "clock1",
ram_block1a_9.port_b_data_width = 1,
ram_block1a_9.port_b_disable_ce_on_input_registers = "on",
ram_block1a_9.port_b_disable_ce_on_output_registers = "on",
ram_block1a_9.port_b_first_address = 0,
ram_block1a_9.port_b_first_bit_number = 9,
ram_block1a_9.port_b_last_address = 1023,
ram_block1a_9.port_b_logical_ram_depth = 1024,
ram_block1a_9.port_b_logical_ram_width = 32,
ram_block1a_9.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_9.power_up_uninitialized = "false",
ram_block1a_9.ram_block_type = "AUTO",
ram_block1a_9.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_10
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[10]}),
.portadataout(wire_ram_block1a_10portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[10]}),
.portbdataout(wire_ram_block1a_10portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_10.connectivity_checking = "OFF",
ram_block1a_10.logical_ram_name = "ALTSYNCRAM",
ram_block1a_10.mixed_port_feed_through_mode = "dont_care",
ram_block1a_10.operation_mode = "bidir_dual_port",
ram_block1a_10.port_a_address_width = 10,
ram_block1a_10.port_a_data_width = 1,
ram_block1a_10.port_a_disable_ce_on_input_registers = "on",
ram_block1a_10.port_a_disable_ce_on_output_registers = "on",
ram_block1a_10.port_a_first_address = 0,
ram_block1a_10.port_a_first_bit_number = 10,
ram_block1a_10.port_a_last_address = 1023,
ram_block1a_10.port_a_logical_ram_depth = 1024,
ram_block1a_10.port_a_logical_ram_width = 32,
ram_block1a_10.port_b_address_clock = "clock1",
ram_block1a_10.port_b_address_width = 10,
ram_block1a_10.port_b_data_in_clock = "clock1",
ram_block1a_10.port_b_data_width = 1,
ram_block1a_10.port_b_disable_ce_on_input_registers = "on",
ram_block1a_10.port_b_disable_ce_on_output_registers = "on",
ram_block1a_10.port_b_first_address = 0,
ram_block1a_10.port_b_first_bit_number = 10,
ram_block1a_10.port_b_last_address = 1023,
ram_block1a_10.port_b_logical_ram_depth = 1024,
ram_block1a_10.port_b_logical_ram_width = 32,
ram_block1a_10.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_10.power_up_uninitialized = "false",
ram_block1a_10.ram_block_type = "AUTO",
ram_block1a_10.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_11
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[11]}),
.portadataout(wire_ram_block1a_11portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[11]}),
.portbdataout(wire_ram_block1a_11portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_11.connectivity_checking = "OFF",
ram_block1a_11.logical_ram_name = "ALTSYNCRAM",
ram_block1a_11.mixed_port_feed_through_mode = "dont_care",
ram_block1a_11.operation_mode = "bidir_dual_port",
ram_block1a_11.port_a_address_width = 10,
ram_block1a_11.port_a_data_width = 1,
ram_block1a_11.port_a_disable_ce_on_input_registers = "on",
ram_block1a_11.port_a_disable_ce_on_output_registers = "on",
ram_block1a_11.port_a_first_address = 0,
ram_block1a_11.port_a_first_bit_number = 11,
ram_block1a_11.port_a_last_address = 1023,
ram_block1a_11.port_a_logical_ram_depth = 1024,
ram_block1a_11.port_a_logical_ram_width = 32,
ram_block1a_11.port_b_address_clock = "clock1",
ram_block1a_11.port_b_address_width = 10,
ram_block1a_11.port_b_data_in_clock = "clock1",
ram_block1a_11.port_b_data_width = 1,
ram_block1a_11.port_b_disable_ce_on_input_registers = "on",
ram_block1a_11.port_b_disable_ce_on_output_registers = "on",
ram_block1a_11.port_b_first_address = 0,
ram_block1a_11.port_b_first_bit_number = 11,
ram_block1a_11.port_b_last_address = 1023,
ram_block1a_11.port_b_logical_ram_depth = 1024,
ram_block1a_11.port_b_logical_ram_width = 32,
ram_block1a_11.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_11.power_up_uninitialized = "false",
ram_block1a_11.ram_block_type = "AUTO",
ram_block1a_11.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_12
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[12]}),
.portadataout(wire_ram_block1a_12portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[12]}),
.portbdataout(wire_ram_block1a_12portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_12.connectivity_checking = "OFF",
ram_block1a_12.logical_ram_name = "ALTSYNCRAM",
ram_block1a_12.mixed_port_feed_through_mode = "dont_care",
ram_block1a_12.operation_mode = "bidir_dual_port",
ram_block1a_12.port_a_address_width = 10,
ram_block1a_12.port_a_data_width = 1,
ram_block1a_12.port_a_disable_ce_on_input_registers = "on",
ram_block1a_12.port_a_disable_ce_on_output_registers = "on",
ram_block1a_12.port_a_first_address = 0,
ram_block1a_12.port_a_first_bit_number = 12,
ram_block1a_12.port_a_last_address = 1023,
ram_block1a_12.port_a_logical_ram_depth = 1024,
ram_block1a_12.port_a_logical_ram_width = 32,
ram_block1a_12.port_b_address_clock = "clock1",
ram_block1a_12.port_b_address_width = 10,
ram_block1a_12.port_b_data_in_clock = "clock1",
ram_block1a_12.port_b_data_width = 1,
ram_block1a_12.port_b_disable_ce_on_input_registers = "on",
ram_block1a_12.port_b_disable_ce_on_output_registers = "on",
ram_block1a_12.port_b_first_address = 0,
ram_block1a_12.port_b_first_bit_number = 12,
ram_block1a_12.port_b_last_address = 1023,
ram_block1a_12.port_b_logical_ram_depth = 1024,
ram_block1a_12.port_b_logical_ram_width = 32,
ram_block1a_12.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_12.power_up_uninitialized = "false",
ram_block1a_12.ram_block_type = "AUTO",
ram_block1a_12.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_13
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[13]}),
.portadataout(wire_ram_block1a_13portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[13]}),
.portbdataout(wire_ram_block1a_13portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_13.connectivity_checking = "OFF",
ram_block1a_13.logical_ram_name = "ALTSYNCRAM",
ram_block1a_13.mixed_port_feed_through_mode = "dont_care",
ram_block1a_13.operation_mode = "bidir_dual_port",
ram_block1a_13.port_a_address_width = 10,
ram_block1a_13.port_a_data_width = 1,
ram_block1a_13.port_a_disable_ce_on_input_registers = "on",
ram_block1a_13.port_a_disable_ce_on_output_registers = "on",
ram_block1a_13.port_a_first_address = 0,
ram_block1a_13.port_a_first_bit_number = 13,
ram_block1a_13.port_a_last_address = 1023,
ram_block1a_13.port_a_logical_ram_depth = 1024,
ram_block1a_13.port_a_logical_ram_width = 32,
ram_block1a_13.port_b_address_clock = "clock1",
ram_block1a_13.port_b_address_width = 10,
ram_block1a_13.port_b_data_in_clock = "clock1",
ram_block1a_13.port_b_data_width = 1,
ram_block1a_13.port_b_disable_ce_on_input_registers = "on",
ram_block1a_13.port_b_disable_ce_on_output_registers = "on",
ram_block1a_13.port_b_first_address = 0,
ram_block1a_13.port_b_first_bit_number = 13,
ram_block1a_13.port_b_last_address = 1023,
ram_block1a_13.port_b_logical_ram_depth = 1024,
ram_block1a_13.port_b_logical_ram_width = 32,
ram_block1a_13.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_13.power_up_uninitialized = "false",
ram_block1a_13.ram_block_type = "AUTO",
ram_block1a_13.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_14
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[14]}),
.portadataout(wire_ram_block1a_14portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[14]}),
.portbdataout(wire_ram_block1a_14portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_14.connectivity_checking = "OFF",
ram_block1a_14.logical_ram_name = "ALTSYNCRAM",
ram_block1a_14.mixed_port_feed_through_mode = "dont_care",
ram_block1a_14.operation_mode = "bidir_dual_port",
ram_block1a_14.port_a_address_width = 10,
ram_block1a_14.port_a_data_width = 1,
ram_block1a_14.port_a_disable_ce_on_input_registers = "on",
ram_block1a_14.port_a_disable_ce_on_output_registers = "on",
ram_block1a_14.port_a_first_address = 0,
ram_block1a_14.port_a_first_bit_number = 14,
ram_block1a_14.port_a_last_address = 1023,
ram_block1a_14.port_a_logical_ram_depth = 1024,
ram_block1a_14.port_a_logical_ram_width = 32,
ram_block1a_14.port_b_address_clock = "clock1",
ram_block1a_14.port_b_address_width = 10,
ram_block1a_14.port_b_data_in_clock = "clock1",
ram_block1a_14.port_b_data_width = 1,
ram_block1a_14.port_b_disable_ce_on_input_registers = "on",
ram_block1a_14.port_b_disable_ce_on_output_registers = "on",
ram_block1a_14.port_b_first_address = 0,
ram_block1a_14.port_b_first_bit_number = 14,
ram_block1a_14.port_b_last_address = 1023,
ram_block1a_14.port_b_logical_ram_depth = 1024,
ram_block1a_14.port_b_logical_ram_width = 32,
ram_block1a_14.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_14.power_up_uninitialized = "false",
ram_block1a_14.ram_block_type = "AUTO",
ram_block1a_14.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_15
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[15]}),
.portadataout(wire_ram_block1a_15portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[15]}),
.portbdataout(wire_ram_block1a_15portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_15.connectivity_checking = "OFF",
ram_block1a_15.logical_ram_name = "ALTSYNCRAM",
ram_block1a_15.mixed_port_feed_through_mode = "dont_care",
ram_block1a_15.operation_mode = "bidir_dual_port",
ram_block1a_15.port_a_address_width = 10,
ram_block1a_15.port_a_data_width = 1,
ram_block1a_15.port_a_disable_ce_on_input_registers = "on",
ram_block1a_15.port_a_disable_ce_on_output_registers = "on",
ram_block1a_15.port_a_first_address = 0,
ram_block1a_15.port_a_first_bit_number = 15,
ram_block1a_15.port_a_last_address = 1023,
ram_block1a_15.port_a_logical_ram_depth = 1024,
ram_block1a_15.port_a_logical_ram_width = 32,
ram_block1a_15.port_b_address_clock = "clock1",
ram_block1a_15.port_b_address_width = 10,
ram_block1a_15.port_b_data_in_clock = "clock1",
ram_block1a_15.port_b_data_width = 1,
ram_block1a_15.port_b_disable_ce_on_input_registers = "on",
ram_block1a_15.port_b_disable_ce_on_output_registers = "on",
ram_block1a_15.port_b_first_address = 0,
ram_block1a_15.port_b_first_bit_number = 15,
ram_block1a_15.port_b_last_address = 1023,
ram_block1a_15.port_b_logical_ram_depth = 1024,
ram_block1a_15.port_b_logical_ram_width = 32,
ram_block1a_15.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_15.power_up_uninitialized = "false",
ram_block1a_15.ram_block_type = "AUTO",
ram_block1a_15.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_16
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[16]}),
.portadataout(wire_ram_block1a_16portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[16]}),
.portbdataout(wire_ram_block1a_16portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_16.connectivity_checking = "OFF",
ram_block1a_16.logical_ram_name = "ALTSYNCRAM",
ram_block1a_16.mixed_port_feed_through_mode = "dont_care",
ram_block1a_16.operation_mode = "bidir_dual_port",
ram_block1a_16.port_a_address_width = 10,
ram_block1a_16.port_a_data_width = 1,
ram_block1a_16.port_a_disable_ce_on_input_registers = "on",
ram_block1a_16.port_a_disable_ce_on_output_registers = "on",
ram_block1a_16.port_a_first_address = 0,
ram_block1a_16.port_a_first_bit_number = 16,
ram_block1a_16.port_a_last_address = 1023,
ram_block1a_16.port_a_logical_ram_depth = 1024,
ram_block1a_16.port_a_logical_ram_width = 32,
ram_block1a_16.port_b_address_clock = "clock1",
ram_block1a_16.port_b_address_width = 10,
ram_block1a_16.port_b_data_in_clock = "clock1",
ram_block1a_16.port_b_data_width = 1,
ram_block1a_16.port_b_disable_ce_on_input_registers = "on",
ram_block1a_16.port_b_disable_ce_on_output_registers = "on",
ram_block1a_16.port_b_first_address = 0,
ram_block1a_16.port_b_first_bit_number = 16,
ram_block1a_16.port_b_last_address = 1023,
ram_block1a_16.port_b_logical_ram_depth = 1024,
ram_block1a_16.port_b_logical_ram_width = 32,
ram_block1a_16.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_16.power_up_uninitialized = "false",
ram_block1a_16.ram_block_type = "AUTO",
ram_block1a_16.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_17
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[17]}),
.portadataout(wire_ram_block1a_17portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[17]}),
.portbdataout(wire_ram_block1a_17portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_17.connectivity_checking = "OFF",
ram_block1a_17.logical_ram_name = "ALTSYNCRAM",
ram_block1a_17.mixed_port_feed_through_mode = "dont_care",
ram_block1a_17.operation_mode = "bidir_dual_port",
ram_block1a_17.port_a_address_width = 10,
ram_block1a_17.port_a_data_width = 1,
ram_block1a_17.port_a_disable_ce_on_input_registers = "on",
ram_block1a_17.port_a_disable_ce_on_output_registers = "on",
ram_block1a_17.port_a_first_address = 0,
ram_block1a_17.port_a_first_bit_number = 17,
ram_block1a_17.port_a_last_address = 1023,
ram_block1a_17.port_a_logical_ram_depth = 1024,
ram_block1a_17.port_a_logical_ram_width = 32,
ram_block1a_17.port_b_address_clock = "clock1",
ram_block1a_17.port_b_address_width = 10,
ram_block1a_17.port_b_data_in_clock = "clock1",
ram_block1a_17.port_b_data_width = 1,
ram_block1a_17.port_b_disable_ce_on_input_registers = "on",
ram_block1a_17.port_b_disable_ce_on_output_registers = "on",
ram_block1a_17.port_b_first_address = 0,
ram_block1a_17.port_b_first_bit_number = 17,
ram_block1a_17.port_b_last_address = 1023,
ram_block1a_17.port_b_logical_ram_depth = 1024,
ram_block1a_17.port_b_logical_ram_width = 32,
ram_block1a_17.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_17.power_up_uninitialized = "false",
ram_block1a_17.ram_block_type = "AUTO",
ram_block1a_17.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_18
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[18]}),
.portadataout(wire_ram_block1a_18portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[18]}),
.portbdataout(wire_ram_block1a_18portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_18.connectivity_checking = "OFF",
ram_block1a_18.logical_ram_name = "ALTSYNCRAM",
ram_block1a_18.mixed_port_feed_through_mode = "dont_care",
ram_block1a_18.operation_mode = "bidir_dual_port",
ram_block1a_18.port_a_address_width = 10,
ram_block1a_18.port_a_data_width = 1,
ram_block1a_18.port_a_disable_ce_on_input_registers = "on",
ram_block1a_18.port_a_disable_ce_on_output_registers = "on",
ram_block1a_18.port_a_first_address = 0,
ram_block1a_18.port_a_first_bit_number = 18,
ram_block1a_18.port_a_last_address = 1023,
ram_block1a_18.port_a_logical_ram_depth = 1024,
ram_block1a_18.port_a_logical_ram_width = 32,
ram_block1a_18.port_b_address_clock = "clock1",
ram_block1a_18.port_b_address_width = 10,
ram_block1a_18.port_b_data_in_clock = "clock1",
ram_block1a_18.port_b_data_width = 1,
ram_block1a_18.port_b_disable_ce_on_input_registers = "on",
ram_block1a_18.port_b_disable_ce_on_output_registers = "on",
ram_block1a_18.port_b_first_address = 0,
ram_block1a_18.port_b_first_bit_number = 18,
ram_block1a_18.port_b_last_address = 1023,
ram_block1a_18.port_b_logical_ram_depth = 1024,
ram_block1a_18.port_b_logical_ram_width = 32,
ram_block1a_18.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_18.power_up_uninitialized = "false",
ram_block1a_18.ram_block_type = "AUTO",
ram_block1a_18.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_19
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[19]}),
.portadataout(wire_ram_block1a_19portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[19]}),
.portbdataout(wire_ram_block1a_19portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_19.connectivity_checking = "OFF",
ram_block1a_19.logical_ram_name = "ALTSYNCRAM",
ram_block1a_19.mixed_port_feed_through_mode = "dont_care",
ram_block1a_19.operation_mode = "bidir_dual_port",
ram_block1a_19.port_a_address_width = 10,
ram_block1a_19.port_a_data_width = 1,
ram_block1a_19.port_a_disable_ce_on_input_registers = "on",
ram_block1a_19.port_a_disable_ce_on_output_registers = "on",
ram_block1a_19.port_a_first_address = 0,
ram_block1a_19.port_a_first_bit_number = 19,
ram_block1a_19.port_a_last_address = 1023,
ram_block1a_19.port_a_logical_ram_depth = 1024,
ram_block1a_19.port_a_logical_ram_width = 32,
ram_block1a_19.port_b_address_clock = "clock1",
ram_block1a_19.port_b_address_width = 10,
ram_block1a_19.port_b_data_in_clock = "clock1",
ram_block1a_19.port_b_data_width = 1,
ram_block1a_19.port_b_disable_ce_on_input_registers = "on",
ram_block1a_19.port_b_disable_ce_on_output_registers = "on",
ram_block1a_19.port_b_first_address = 0,
ram_block1a_19.port_b_first_bit_number = 19,
ram_block1a_19.port_b_last_address = 1023,
ram_block1a_19.port_b_logical_ram_depth = 1024,
ram_block1a_19.port_b_logical_ram_width = 32,
ram_block1a_19.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_19.power_up_uninitialized = "false",
ram_block1a_19.ram_block_type = "AUTO",
ram_block1a_19.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_20
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[20]}),
.portadataout(wire_ram_block1a_20portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[20]}),
.portbdataout(wire_ram_block1a_20portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_20.connectivity_checking = "OFF",
ram_block1a_20.logical_ram_name = "ALTSYNCRAM",
ram_block1a_20.mixed_port_feed_through_mode = "dont_care",
ram_block1a_20.operation_mode = "bidir_dual_port",
ram_block1a_20.port_a_address_width = 10,
ram_block1a_20.port_a_data_width = 1,
ram_block1a_20.port_a_disable_ce_on_input_registers = "on",
ram_block1a_20.port_a_disable_ce_on_output_registers = "on",
ram_block1a_20.port_a_first_address = 0,
ram_block1a_20.port_a_first_bit_number = 20,
ram_block1a_20.port_a_last_address = 1023,
ram_block1a_20.port_a_logical_ram_depth = 1024,
ram_block1a_20.port_a_logical_ram_width = 32,
ram_block1a_20.port_b_address_clock = "clock1",
ram_block1a_20.port_b_address_width = 10,
ram_block1a_20.port_b_data_in_clock = "clock1",
ram_block1a_20.port_b_data_width = 1,
ram_block1a_20.port_b_disable_ce_on_input_registers = "on",
ram_block1a_20.port_b_disable_ce_on_output_registers = "on",
ram_block1a_20.port_b_first_address = 0,
ram_block1a_20.port_b_first_bit_number = 20,
ram_block1a_20.port_b_last_address = 1023,
ram_block1a_20.port_b_logical_ram_depth = 1024,
ram_block1a_20.port_b_logical_ram_width = 32,
ram_block1a_20.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_20.power_up_uninitialized = "false",
ram_block1a_20.ram_block_type = "AUTO",
ram_block1a_20.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_21
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[21]}),
.portadataout(wire_ram_block1a_21portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[21]}),
.portbdataout(wire_ram_block1a_21portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_21.connectivity_checking = "OFF",
ram_block1a_21.logical_ram_name = "ALTSYNCRAM",
ram_block1a_21.mixed_port_feed_through_mode = "dont_care",
ram_block1a_21.operation_mode = "bidir_dual_port",
ram_block1a_21.port_a_address_width = 10,
ram_block1a_21.port_a_data_width = 1,
ram_block1a_21.port_a_disable_ce_on_input_registers = "on",
ram_block1a_21.port_a_disable_ce_on_output_registers = "on",
ram_block1a_21.port_a_first_address = 0,
ram_block1a_21.port_a_first_bit_number = 21,
ram_block1a_21.port_a_last_address = 1023,
ram_block1a_21.port_a_logical_ram_depth = 1024,
ram_block1a_21.port_a_logical_ram_width = 32,
ram_block1a_21.port_b_address_clock = "clock1",
ram_block1a_21.port_b_address_width = 10,
ram_block1a_21.port_b_data_in_clock = "clock1",
ram_block1a_21.port_b_data_width = 1,
ram_block1a_21.port_b_disable_ce_on_input_registers = "on",
ram_block1a_21.port_b_disable_ce_on_output_registers = "on",
ram_block1a_21.port_b_first_address = 0,
ram_block1a_21.port_b_first_bit_number = 21,
ram_block1a_21.port_b_last_address = 1023,
ram_block1a_21.port_b_logical_ram_depth = 1024,
ram_block1a_21.port_b_logical_ram_width = 32,
ram_block1a_21.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_21.power_up_uninitialized = "false",
ram_block1a_21.ram_block_type = "AUTO",
ram_block1a_21.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_22
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[22]}),
.portadataout(wire_ram_block1a_22portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[22]}),
.portbdataout(wire_ram_block1a_22portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_22.connectivity_checking = "OFF",
ram_block1a_22.logical_ram_name = "ALTSYNCRAM",
ram_block1a_22.mixed_port_feed_through_mode = "dont_care",
ram_block1a_22.operation_mode = "bidir_dual_port",
ram_block1a_22.port_a_address_width = 10,
ram_block1a_22.port_a_data_width = 1,
ram_block1a_22.port_a_disable_ce_on_input_registers = "on",
ram_block1a_22.port_a_disable_ce_on_output_registers = "on",
ram_block1a_22.port_a_first_address = 0,
ram_block1a_22.port_a_first_bit_number = 22,
ram_block1a_22.port_a_last_address = 1023,
ram_block1a_22.port_a_logical_ram_depth = 1024,
ram_block1a_22.port_a_logical_ram_width = 32,
ram_block1a_22.port_b_address_clock = "clock1",
ram_block1a_22.port_b_address_width = 10,
ram_block1a_22.port_b_data_in_clock = "clock1",
ram_block1a_22.port_b_data_width = 1,
ram_block1a_22.port_b_disable_ce_on_input_registers = "on",
ram_block1a_22.port_b_disable_ce_on_output_registers = "on",
ram_block1a_22.port_b_first_address = 0,
ram_block1a_22.port_b_first_bit_number = 22,
ram_block1a_22.port_b_last_address = 1023,
ram_block1a_22.port_b_logical_ram_depth = 1024,
ram_block1a_22.port_b_logical_ram_width = 32,
ram_block1a_22.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_22.power_up_uninitialized = "false",
ram_block1a_22.ram_block_type = "AUTO",
ram_block1a_22.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_23
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[23]}),
.portadataout(wire_ram_block1a_23portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[23]}),
.portbdataout(wire_ram_block1a_23portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_23.connectivity_checking = "OFF",
ram_block1a_23.logical_ram_name = "ALTSYNCRAM",
ram_block1a_23.mixed_port_feed_through_mode = "dont_care",
ram_block1a_23.operation_mode = "bidir_dual_port",
ram_block1a_23.port_a_address_width = 10,
ram_block1a_23.port_a_data_width = 1,
ram_block1a_23.port_a_disable_ce_on_input_registers = "on",
ram_block1a_23.port_a_disable_ce_on_output_registers = "on",
ram_block1a_23.port_a_first_address = 0,
ram_block1a_23.port_a_first_bit_number = 23,
ram_block1a_23.port_a_last_address = 1023,
ram_block1a_23.port_a_logical_ram_depth = 1024,
ram_block1a_23.port_a_logical_ram_width = 32,
ram_block1a_23.port_b_address_clock = "clock1",
ram_block1a_23.port_b_address_width = 10,
ram_block1a_23.port_b_data_in_clock = "clock1",
ram_block1a_23.port_b_data_width = 1,
ram_block1a_23.port_b_disable_ce_on_input_registers = "on",
ram_block1a_23.port_b_disable_ce_on_output_registers = "on",
ram_block1a_23.port_b_first_address = 0,
ram_block1a_23.port_b_first_bit_number = 23,
ram_block1a_23.port_b_last_address = 1023,
ram_block1a_23.port_b_logical_ram_depth = 1024,
ram_block1a_23.port_b_logical_ram_width = 32,
ram_block1a_23.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_23.power_up_uninitialized = "false",
ram_block1a_23.ram_block_type = "AUTO",
ram_block1a_23.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_24
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[24]}),
.portadataout(wire_ram_block1a_24portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[24]}),
.portbdataout(wire_ram_block1a_24portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_24.connectivity_checking = "OFF",
ram_block1a_24.logical_ram_name = "ALTSYNCRAM",
ram_block1a_24.mixed_port_feed_through_mode = "dont_care",
ram_block1a_24.operation_mode = "bidir_dual_port",
ram_block1a_24.port_a_address_width = 10,
ram_block1a_24.port_a_data_width = 1,
ram_block1a_24.port_a_disable_ce_on_input_registers = "on",
ram_block1a_24.port_a_disable_ce_on_output_registers = "on",
ram_block1a_24.port_a_first_address = 0,
ram_block1a_24.port_a_first_bit_number = 24,
ram_block1a_24.port_a_last_address = 1023,
ram_block1a_24.port_a_logical_ram_depth = 1024,
ram_block1a_24.port_a_logical_ram_width = 32,
ram_block1a_24.port_b_address_clock = "clock1",
ram_block1a_24.port_b_address_width = 10,
ram_block1a_24.port_b_data_in_clock = "clock1",
ram_block1a_24.port_b_data_width = 1,
ram_block1a_24.port_b_disable_ce_on_input_registers = "on",
ram_block1a_24.port_b_disable_ce_on_output_registers = "on",
ram_block1a_24.port_b_first_address = 0,
ram_block1a_24.port_b_first_bit_number = 24,
ram_block1a_24.port_b_last_address = 1023,
ram_block1a_24.port_b_logical_ram_depth = 1024,
ram_block1a_24.port_b_logical_ram_width = 32,
ram_block1a_24.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_24.power_up_uninitialized = "false",
ram_block1a_24.ram_block_type = "AUTO",
ram_block1a_24.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_25
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[25]}),
.portadataout(wire_ram_block1a_25portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[25]}),
.portbdataout(wire_ram_block1a_25portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_25.connectivity_checking = "OFF",
ram_block1a_25.logical_ram_name = "ALTSYNCRAM",
ram_block1a_25.mixed_port_feed_through_mode = "dont_care",
ram_block1a_25.operation_mode = "bidir_dual_port",
ram_block1a_25.port_a_address_width = 10,
ram_block1a_25.port_a_data_width = 1,
ram_block1a_25.port_a_disable_ce_on_input_registers = "on",
ram_block1a_25.port_a_disable_ce_on_output_registers = "on",
ram_block1a_25.port_a_first_address = 0,
ram_block1a_25.port_a_first_bit_number = 25,
ram_block1a_25.port_a_last_address = 1023,
ram_block1a_25.port_a_logical_ram_depth = 1024,
ram_block1a_25.port_a_logical_ram_width = 32,
ram_block1a_25.port_b_address_clock = "clock1",
ram_block1a_25.port_b_address_width = 10,
ram_block1a_25.port_b_data_in_clock = "clock1",
ram_block1a_25.port_b_data_width = 1,
ram_block1a_25.port_b_disable_ce_on_input_registers = "on",
ram_block1a_25.port_b_disable_ce_on_output_registers = "on",
ram_block1a_25.port_b_first_address = 0,
ram_block1a_25.port_b_first_bit_number = 25,
ram_block1a_25.port_b_last_address = 1023,
ram_block1a_25.port_b_logical_ram_depth = 1024,
ram_block1a_25.port_b_logical_ram_width = 32,
ram_block1a_25.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_25.power_up_uninitialized = "false",
ram_block1a_25.ram_block_type = "AUTO",
ram_block1a_25.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_26
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[26]}),
.portadataout(wire_ram_block1a_26portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[26]}),
.portbdataout(wire_ram_block1a_26portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_26.connectivity_checking = "OFF",
ram_block1a_26.logical_ram_name = "ALTSYNCRAM",
ram_block1a_26.mixed_port_feed_through_mode = "dont_care",
ram_block1a_26.operation_mode = "bidir_dual_port",
ram_block1a_26.port_a_address_width = 10,
ram_block1a_26.port_a_data_width = 1,
ram_block1a_26.port_a_disable_ce_on_input_registers = "on",
ram_block1a_26.port_a_disable_ce_on_output_registers = "on",
ram_block1a_26.port_a_first_address = 0,
ram_block1a_26.port_a_first_bit_number = 26,
ram_block1a_26.port_a_last_address = 1023,
ram_block1a_26.port_a_logical_ram_depth = 1024,
ram_block1a_26.port_a_logical_ram_width = 32,
ram_block1a_26.port_b_address_clock = "clock1",
ram_block1a_26.port_b_address_width = 10,
ram_block1a_26.port_b_data_in_clock = "clock1",
ram_block1a_26.port_b_data_width = 1,
ram_block1a_26.port_b_disable_ce_on_input_registers = "on",
ram_block1a_26.port_b_disable_ce_on_output_registers = "on",
ram_block1a_26.port_b_first_address = 0,
ram_block1a_26.port_b_first_bit_number = 26,
ram_block1a_26.port_b_last_address = 1023,
ram_block1a_26.port_b_logical_ram_depth = 1024,
ram_block1a_26.port_b_logical_ram_width = 32,
ram_block1a_26.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_26.power_up_uninitialized = "false",
ram_block1a_26.ram_block_type = "AUTO",
ram_block1a_26.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_27
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[27]}),
.portadataout(wire_ram_block1a_27portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[27]}),
.portbdataout(wire_ram_block1a_27portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_27.connectivity_checking = "OFF",
ram_block1a_27.logical_ram_name = "ALTSYNCRAM",
ram_block1a_27.mixed_port_feed_through_mode = "dont_care",
ram_block1a_27.operation_mode = "bidir_dual_port",
ram_block1a_27.port_a_address_width = 10,
ram_block1a_27.port_a_data_width = 1,
ram_block1a_27.port_a_disable_ce_on_input_registers = "on",
ram_block1a_27.port_a_disable_ce_on_output_registers = "on",
ram_block1a_27.port_a_first_address = 0,
ram_block1a_27.port_a_first_bit_number = 27,
ram_block1a_27.port_a_last_address = 1023,
ram_block1a_27.port_a_logical_ram_depth = 1024,
ram_block1a_27.port_a_logical_ram_width = 32,
ram_block1a_27.port_b_address_clock = "clock1",
ram_block1a_27.port_b_address_width = 10,
ram_block1a_27.port_b_data_in_clock = "clock1",
ram_block1a_27.port_b_data_width = 1,
ram_block1a_27.port_b_disable_ce_on_input_registers = "on",
ram_block1a_27.port_b_disable_ce_on_output_registers = "on",
ram_block1a_27.port_b_first_address = 0,
ram_block1a_27.port_b_first_bit_number = 27,
ram_block1a_27.port_b_last_address = 1023,
ram_block1a_27.port_b_logical_ram_depth = 1024,
ram_block1a_27.port_b_logical_ram_width = 32,
ram_block1a_27.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_27.power_up_uninitialized = "false",
ram_block1a_27.ram_block_type = "AUTO",
ram_block1a_27.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_28
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[28]}),
.portadataout(wire_ram_block1a_28portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[28]}),
.portbdataout(wire_ram_block1a_28portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_28.connectivity_checking = "OFF",
ram_block1a_28.logical_ram_name = "ALTSYNCRAM",
ram_block1a_28.mixed_port_feed_through_mode = "dont_care",
ram_block1a_28.operation_mode = "bidir_dual_port",
ram_block1a_28.port_a_address_width = 10,
ram_block1a_28.port_a_data_width = 1,
ram_block1a_28.port_a_disable_ce_on_input_registers = "on",
ram_block1a_28.port_a_disable_ce_on_output_registers = "on",
ram_block1a_28.port_a_first_address = 0,
ram_block1a_28.port_a_first_bit_number = 28,
ram_block1a_28.port_a_last_address = 1023,
ram_block1a_28.port_a_logical_ram_depth = 1024,
ram_block1a_28.port_a_logical_ram_width = 32,
ram_block1a_28.port_b_address_clock = "clock1",
ram_block1a_28.port_b_address_width = 10,
ram_block1a_28.port_b_data_in_clock = "clock1",
ram_block1a_28.port_b_data_width = 1,
ram_block1a_28.port_b_disable_ce_on_input_registers = "on",
ram_block1a_28.port_b_disable_ce_on_output_registers = "on",
ram_block1a_28.port_b_first_address = 0,
ram_block1a_28.port_b_first_bit_number = 28,
ram_block1a_28.port_b_last_address = 1023,
ram_block1a_28.port_b_logical_ram_depth = 1024,
ram_block1a_28.port_b_logical_ram_width = 32,
ram_block1a_28.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_28.power_up_uninitialized = "false",
ram_block1a_28.ram_block_type = "AUTO",
ram_block1a_28.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_29
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[29]}),
.portadataout(wire_ram_block1a_29portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[29]}),
.portbdataout(wire_ram_block1a_29portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_29.connectivity_checking = "OFF",
ram_block1a_29.logical_ram_name = "ALTSYNCRAM",
ram_block1a_29.mixed_port_feed_through_mode = "dont_care",
ram_block1a_29.operation_mode = "bidir_dual_port",
ram_block1a_29.port_a_address_width = 10,
ram_block1a_29.port_a_data_width = 1,
ram_block1a_29.port_a_disable_ce_on_input_registers = "on",
ram_block1a_29.port_a_disable_ce_on_output_registers = "on",
ram_block1a_29.port_a_first_address = 0,
ram_block1a_29.port_a_first_bit_number = 29,
ram_block1a_29.port_a_last_address = 1023,
ram_block1a_29.port_a_logical_ram_depth = 1024,
ram_block1a_29.port_a_logical_ram_width = 32,
ram_block1a_29.port_b_address_clock = "clock1",
ram_block1a_29.port_b_address_width = 10,
ram_block1a_29.port_b_data_in_clock = "clock1",
ram_block1a_29.port_b_data_width = 1,
ram_block1a_29.port_b_disable_ce_on_input_registers = "on",
ram_block1a_29.port_b_disable_ce_on_output_registers = "on",
ram_block1a_29.port_b_first_address = 0,
ram_block1a_29.port_b_first_bit_number = 29,
ram_block1a_29.port_b_last_address = 1023,
ram_block1a_29.port_b_logical_ram_depth = 1024,
ram_block1a_29.port_b_logical_ram_width = 32,
ram_block1a_29.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_29.power_up_uninitialized = "false",
ram_block1a_29.ram_block_type = "AUTO",
ram_block1a_29.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_30
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[30]}),
.portadataout(wire_ram_block1a_30portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[30]}),
.portbdataout(wire_ram_block1a_30portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_30.connectivity_checking = "OFF",
ram_block1a_30.logical_ram_name = "ALTSYNCRAM",
ram_block1a_30.mixed_port_feed_through_mode = "dont_care",
ram_block1a_30.operation_mode = "bidir_dual_port",
ram_block1a_30.port_a_address_width = 10,
ram_block1a_30.port_a_data_width = 1,
ram_block1a_30.port_a_disable_ce_on_input_registers = "on",
ram_block1a_30.port_a_disable_ce_on_output_registers = "on",
ram_block1a_30.port_a_first_address = 0,
ram_block1a_30.port_a_first_bit_number = 30,
ram_block1a_30.port_a_last_address = 1023,
ram_block1a_30.port_a_logical_ram_depth = 1024,
ram_block1a_30.port_a_logical_ram_width = 32,
ram_block1a_30.port_b_address_clock = "clock1",
ram_block1a_30.port_b_address_width = 10,
ram_block1a_30.port_b_data_in_clock = "clock1",
ram_block1a_30.port_b_data_width = 1,
ram_block1a_30.port_b_disable_ce_on_input_registers = "on",
ram_block1a_30.port_b_disable_ce_on_output_registers = "on",
ram_block1a_30.port_b_first_address = 0,
ram_block1a_30.port_b_first_bit_number = 30,
ram_block1a_30.port_b_last_address = 1023,
ram_block1a_30.port_b_logical_ram_depth = 1024,
ram_block1a_30.port_b_logical_ram_width = 32,
ram_block1a_30.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_30.power_up_uninitialized = "false",
ram_block1a_30.ram_block_type = "AUTO",
ram_block1a_30.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block1a_31
(
.clk0(clock0),
.clk1(clock1),
.portaaddr({address_a_wire[9:0]}),
.portadatain({data_a[31]}),
.portadataout(wire_ram_block1a_31portadataout[0:0]),
.portawe(wren_a),
.portbaddr({address_b_wire[9:0]}),
.portbdatain({data_b[31]}),
.portbdataout(wire_ram_block1a_31portbdataout[0:0]),
.portbrewe(wren_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.ena0(1'b1),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_31.connectivity_checking = "OFF",
ram_block1a_31.logical_ram_name = "ALTSYNCRAM",
ram_block1a_31.mixed_port_feed_through_mode = "dont_care",
ram_block1a_31.operation_mode = "bidir_dual_port",
ram_block1a_31.port_a_address_width = 10,
ram_block1a_31.port_a_data_width = 1,
ram_block1a_31.port_a_disable_ce_on_input_registers = "on",
ram_block1a_31.port_a_disable_ce_on_output_registers = "on",
ram_block1a_31.port_a_first_address = 0,
ram_block1a_31.port_a_first_bit_number = 31,
ram_block1a_31.port_a_last_address = 1023,
ram_block1a_31.port_a_logical_ram_depth = 1024,
ram_block1a_31.port_a_logical_ram_width = 32,
ram_block1a_31.port_b_address_clock = "clock1",
ram_block1a_31.port_b_address_width = 10,
ram_block1a_31.port_b_data_in_clock = "clock1",
ram_block1a_31.port_b_data_width = 1,
ram_block1a_31.port_b_disable_ce_on_input_registers = "on",
ram_block1a_31.port_b_disable_ce_on_output_registers = "on",
ram_block1a_31.port_b_first_address = 0,
ram_block1a_31.port_b_first_bit_number = 31,
ram_block1a_31.port_b_last_address = 1023,
ram_block1a_31.port_b_logical_ram_depth = 1024,
ram_block1a_31.port_b_logical_ram_width = 32,
ram_block1a_31.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_31.power_up_uninitialized = "false",
ram_block1a_31.ram_block_type = "AUTO",
ram_block1a_31.lpm_type = "stratixii_ram_block";
assign
address_a_wire = address_a,
address_b_wire = address_b,
q_a = {wire_ram_block1a_31portadataout[0], wire_ram_block1a_30portadataout[0], wire_ram_block1a_29portadataout[0], wire_ram_block1a_28portadataout[0], wire_ram_block1a_27portadataout[0], wire_ram_block1a_26portadataout[0], wire_ram_block1a_25portadataout[0], wire_ram_block1a_24portadataout[0], wire_ram_block1a_23portadataout[0], wire_ram_block1a_22portadataout[0], wire_ram_block1a_21portadataout[0], wire_ram_block1a_20portadataout[0], wire_ram_block1a_19portadataout[0], wire_ram_block1a_18portadataout[0], wire_ram_block1a_17portadataout[0], wire_ram_block1a_16portadataout[0], wire_ram_block1a_15portadataout[0], wire_ram_block1a_14portadataout[0], wire_ram_block1a_13portadataout[0], wire_ram_block1a_12portadataout[0], wire_ram_block1a_11portadataout[0], wire_ram_block1a_10portadataout[0], wire_ram_block1a_9portadataout[0], wire_ram_block1a_8portadataout[0], wire_ram_block1a_7portadataout[0], wire_ram_block1a_6portadataout[0], wire_ram_block1a_5portadataout[0], wire_ram_block1a_4portadataout[0], wire_ram_block1a_3portadataout[0], wire_ram_block1a_2portadataout[0], wire_ram_block1a_1portadataout[0], wire_ram_block1a_0portadataout[0]},
q_b = {wire_ram_block1a_31portbdataout[0], wire_ram_block1a_30portbdataout[0], wire_ram_block1a_29portbdataout[0], wire_ram_block1a_28portbdataout[0], wire_ram_block1a_27portbdataout[0], wire_ram_block1a_26portbdataout[0], wire_ram_block1a_25portbdataout[0], wire_ram_block1a_24portbdataout[0], wire_ram_block1a_23portbdataout[0], wire_ram_block1a_22portbdataout[0], wire_ram_block1a_21portbdataout[0], wire_ram_block1a_20portbdataout[0], wire_ram_block1a_19portbdataout[0], wire_ram_block1a_18portbdataout[0], wire_ram_block1a_17portbdataout[0], wire_ram_block1a_16portbdataout[0], wire_ram_block1a_15portbdataout[0], wire_ram_block1a_14portbdataout[0], wire_ram_block1a_13portbdataout[0], wire_ram_block1a_12portbdataout[0], wire_ram_block1a_11portbdataout[0], wire_ram_block1a_10portbdataout[0], wire_ram_block1a_9portbdataout[0], wire_ram_block1a_8portbdataout[0], wire_ram_block1a_7portbdataout[0], wire_ram_block1a_6portbdataout[0], wire_ram_block1a_5portbdataout[0], wire_ram_block1a_4portbdataout[0], wire_ram_block1a_3portbdataout[0], wire_ram_block1a_2portbdataout[0], wire_ram_block1a_1portbdataout[0], wire_ram_block1a_0portbdataout[0]};
endmodule //RAM16_s36_s36_altera_altsyncram
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module RAM16_s36_s36_altera (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b)/* synthesis synthesis_clearbox = 1 */;
input [9:0] address_a;
input [9:0] address_b;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire [31:0] q_a = sub_wire0[31:0];
wire [31:0] q_b = sub_wire1[31:0];
RAM16_s36_s36_altera_altsyncram RAM16_s36_s36_altera_altsyncram_component (
.clock0 (clock_a),
.wren_a (wren_a),
.address_b (address_b),
.clock1 (clock_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_wave*.jpg TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM16_s36_s36_altera_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:21:16 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45,
n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59,
n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73,
n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87,
n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144,
n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155,
n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166,
n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177,
n178, n179, n180, n181, n182, n183, n184, n185, n186, n187, n188,
n189, n190, n191, n192, n193, n194, n195, n196, n197, n198, n199,
n200, n201, n202, n203, n204, n205, n206, n207, n208, n209, n210,
n211, n212, n213, n214, n215, n216, n217, n218, n219, n220, n221,
n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, n232,
n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243,
n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254,
n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, n265,
n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276,
n277, n278, n279, n280, n281, n282, n283, n284, n285, n286, n287,
n288, n289, n290, n291, n292, n293, n294, n295, n296, n297, n298,
n299, n300, n301, n302, n303, n304, n305, n306, n307, n308, n309,
n310, n311, n312, n313, n314, n315, n316, n317, n318, n319, n320,
n321, n322, n323, n324, n325, n326, n327, n328, n329, n330, n331,
n332, n333, n334, n335, n336, n337, n338, n339, n340, n341, n342,
n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, n353,
n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, n364,
n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375,
n376, n377, n378;
XNOR2X1TS U35 ( .A(n242), .B(n241), .Y(res[23]) );
XNOR2X1TS U36 ( .A(n248), .B(n247), .Y(res[22]) );
NAND2X1TS U37 ( .A(n146), .B(n201), .Y(n202) );
NAND2X1TS U38 ( .A(n150), .B(n207), .Y(n208) );
NAND2X1TS U39 ( .A(n240), .B(n239), .Y(n241) );
NAND2X1TS U40 ( .A(n266), .B(n265), .Y(n267) );
NAND2X1TS U41 ( .A(n251), .B(n250), .Y(n252) );
NAND2X1TS U42 ( .A(n246), .B(n245), .Y(n247) );
NAND2X1TS U43 ( .A(n193), .B(n192), .Y(n194) );
NAND2X1TS U44 ( .A(n185), .B(n188), .Y(n187) );
NAND2XLTS U45 ( .A(n234), .B(n233), .Y(n235) );
NAND2XLTS U46 ( .A(n224), .B(n223), .Y(n225) );
BUFX6TS U47 ( .A(n215), .Y(n216) );
NAND2X2TS U48 ( .A(n177), .B(in1[31]), .Y(n182) );
OAI21X1TS U49 ( .A0(n239), .A1(n232), .B0(n233), .Y(n218) );
NAND2X4TS U50 ( .A(n215), .B(n122), .Y(n137) );
OR2X6TS U51 ( .A(n161), .B(in1[27]), .Y(n7) );
INVX6TS U52 ( .A(n160), .Y(n163) );
INVX2TS U53 ( .A(n212), .Y(n162) );
NAND2X4TS U54 ( .A(n141), .B(in1[26]), .Y(n160) );
NAND2X1TS U55 ( .A(n342), .B(in1[5]), .Y(n370) );
NOR2X6TS U56 ( .A(n8), .B(n126), .Y(n127) );
OAI21X2TS U57 ( .A0(n222), .A1(n233), .B0(n223), .Y(n132) );
NAND2X2TS U58 ( .A(n165), .B(in1[29]), .Y(n201) );
NAND2X2TS U59 ( .A(n164), .B(in1[28]), .Y(n207) );
NOR2X4TS U60 ( .A(n222), .B(n232), .Y(n133) );
MX2X2TS U61 ( .A(in2[28]), .B(n149), .S0(n175), .Y(n164) );
NAND2BX2TS U62 ( .AN(in2[29]), .B(n158), .Y(n173) );
NAND2X2TS U63 ( .A(n130), .B(in1[24]), .Y(n233) );
NAND2X1TS U64 ( .A(in1[0]), .B(in2[0]), .Y(n377) );
NOR2X6TS U65 ( .A(n125), .B(in1[21]), .Y(n249) );
NAND2X1TS U66 ( .A(n327), .B(in1[4]), .Y(n330) );
NAND2X1TS U67 ( .A(n154), .B(in2[27]), .Y(n155) );
NOR2X4TS U68 ( .A(n130), .B(in1[24]), .Y(n232) );
MX2X1TS U69 ( .A(in2[15]), .B(n81), .S0(n175), .Y(n83) );
MX2X2TS U70 ( .A(in2[18]), .B(n5), .S0(n339), .Y(n96) );
NAND2X2TS U71 ( .A(n138), .B(n144), .Y(n139) );
NOR3X4TS U72 ( .A(n152), .B(in2[28]), .C(n147), .Y(n158) );
NOR2X4TS U73 ( .A(n152), .B(n151), .Y(n153) );
MXI2X4TS U74 ( .A(n116), .B(n115), .S0(n339), .Y(n124) );
INVX2TS U75 ( .A(in2[21]), .Y(n3) );
NAND2X1TS U76 ( .A(n72), .B(in1[14]), .Y(n292) );
NAND2X2TS U77 ( .A(n54), .B(in1[10]), .Y(n311) );
CLKXOR2X2TS U78 ( .A(n321), .B(in2[3]), .Y(n322) );
XNOR2X2TS U79 ( .A(n105), .B(in2[23]), .Y(n106) );
XNOR2X2TS U80 ( .A(n86), .B(in2[19]), .Y(n87) );
NAND2X1TS U81 ( .A(n144), .B(n143), .Y(n151) );
NOR2X2TS U82 ( .A(n45), .B(n361), .Y(n48) );
NOR2X2TS U83 ( .A(n118), .B(n117), .Y(n119) );
NOR2X4TS U84 ( .A(n152), .B(in2[24]), .Y(n110) );
MXI2X2TS U85 ( .A(n67), .B(n62), .S0(n317), .Y(n64) );
INVX2TS U86 ( .A(n109), .Y(n89) );
NOR2X1TS U87 ( .A(n350), .B(in1[7]), .Y(n43) );
NOR2X2TS U88 ( .A(in2[25]), .B(in2[24]), .Y(n144) );
BUFX4TS U89 ( .A(add_sub), .Y(n175) );
NOR4BX2TS U90 ( .AN(n56), .B(n51), .C(n50), .D(n49), .Y(n52) );
OR2X2TS U91 ( .A(in2[21]), .B(in2[20]), .Y(n117) );
NOR2X2TS U92 ( .A(in2[13]), .B(in2[12]), .Y(n78) );
INVX4TS U93 ( .A(in2[8]), .Y(n21) );
NOR2X1TS U94 ( .A(in2[19]), .B(in2[18]), .Y(n102) );
NAND2X1TS U95 ( .A(n103), .B(n102), .Y(n107) );
INVX2TS U96 ( .A(n175), .Y(n154) );
CLKMX2X2TS U97 ( .A(in2[11]), .B(n59), .S0(n175), .Y(n63) );
BUFX8TS U98 ( .A(add_sub), .Y(n317) );
OR2X1TS U99 ( .A(n350), .B(in1[7]), .Y(n354) );
NAND2X2TS U100 ( .A(n63), .B(in1[11]), .Y(n306) );
NAND2X2TS U101 ( .A(n94), .B(in1[16]), .Y(n283) );
NAND2X1TS U102 ( .A(n196), .B(n150), .Y(n200) );
OR2X1TS U103 ( .A(in1[0]), .B(in2[0]), .Y(n374) );
OAI21XLTS U104 ( .A0(n309), .A1(n305), .B0(n306), .Y(n304) );
INVX2TS U105 ( .A(n183), .Y(n178) );
INVX4TS U106 ( .A(n245), .Y(n128) );
INVX2TS U107 ( .A(n264), .Y(n266) );
INVX2TS U108 ( .A(n232), .Y(n234) );
CLKAND2X2TS U109 ( .A(n374), .B(n377), .Y(res[0]) );
NAND2X2TS U110 ( .A(n178), .B(n182), .Y(n179) );
XNOR2X2TS U111 ( .A(n110), .B(in2[25]), .Y(n111) );
OAI21X2TS U112 ( .A0(n25), .A1(n24), .B0(n23), .Y(n44) );
INVX12TS U113 ( .A(in2[4]), .Y(n336) );
BUFX12TS U114 ( .A(add_sub), .Y(n339) );
NOR2X4TS U115 ( .A(n183), .B(n181), .Y(n185) );
INVX4TS U116 ( .A(n238), .Y(n227) );
INVX2TS U117 ( .A(n243), .Y(n244) );
NAND2X4TS U118 ( .A(n146), .B(n150), .Y(n168) );
INVX4TS U119 ( .A(n207), .Y(n197) );
INVX2TS U120 ( .A(n222), .Y(n224) );
OR2X6TS U121 ( .A(n164), .B(in1[28]), .Y(n150) );
NAND2X4TS U122 ( .A(n129), .B(in1[23]), .Y(n239) );
OR2X6TS U123 ( .A(n165), .B(in1[29]), .Y(n146) );
NOR2X4TS U124 ( .A(n131), .B(in1[25]), .Y(n222) );
MX2X2TS U125 ( .A(in2[25]), .B(n111), .S0(n175), .Y(n131) );
XOR2X1TS U126 ( .A(n349), .B(n346), .Y(res[6]) );
NOR2X2TS U127 ( .A(n173), .B(in2[30]), .Y(n174) );
NAND2X2TS U128 ( .A(n296), .B(n6), .Y(n76) );
XOR2X2TS U129 ( .A(n119), .B(in2[22]), .Y(n120) );
NOR2X4TS U130 ( .A(n89), .B(in2[16]), .Y(n90) );
OR2X2TS U131 ( .A(n83), .B(in1[15]), .Y(n82) );
MX2X2TS U132 ( .A(in2[13]), .B(n69), .S0(add_sub), .Y(n71) );
NOR2X4TS U133 ( .A(n44), .B(in1[8]), .Y(n361) );
NAND2X2TS U134 ( .A(n188), .B(n193), .Y(n172) );
INVX12TS U135 ( .A(n216), .Y(n258) );
NOR2X4TS U136 ( .A(n168), .B(n204), .Y(n188) );
NAND2X6TS U137 ( .A(n243), .B(n246), .Y(n238) );
NAND2X4TS U138 ( .A(n99), .B(n260), .Y(n101) );
INVX2TS U139 ( .A(n192), .Y(n170) );
INVX4TS U140 ( .A(n126), .Y(n246) );
XOR2X1TS U141 ( .A(n365), .B(n364), .Y(res[8]) );
MX2X2TS U142 ( .A(in2[30]), .B(n159), .S0(n175), .Y(n169) );
XOR2X1TS U143 ( .A(n298), .B(n297), .Y(res[13]) );
MX2X2TS U144 ( .A(in2[17]), .B(n91), .S0(add_sub), .Y(n95) );
XOR2X1TS U145 ( .A(n309), .B(n308), .Y(res[11]) );
XNOR2X2TS U146 ( .A(n90), .B(in2[17]), .Y(n91) );
XOR2X1TS U147 ( .A(n329), .B(n328), .Y(res[4]) );
XOR2X1TS U148 ( .A(n369), .B(n368), .Y(res[3]) );
NAND2X2TS U149 ( .A(n64), .B(in1[12]), .Y(n301) );
OR2X2TS U150 ( .A(n342), .B(in1[5]), .Y(n371) );
OR2X2TS U151 ( .A(n151), .B(in2[27]), .Y(n147) );
AND2X2TS U152 ( .A(n49), .B(n317), .Y(n34) );
NOR2X2TS U153 ( .A(in2[17]), .B(in2[16]), .Y(n103) );
INVX4TS U154 ( .A(in2[6]), .Y(n20) );
NOR2X4TS U155 ( .A(n54), .B(in1[10]), .Y(n310) );
NOR4X2TS U156 ( .A(n19), .B(n36), .C(in2[2]), .D(in2[0]), .Y(n25) );
NAND4X1TS U157 ( .A(n39), .B(n38), .C(in2[6]), .D(n336), .Y(n40) );
NAND2X2TS U158 ( .A(n83), .B(in1[15]), .Y(n288) );
MXI2X8TS U159 ( .A(n4), .B(n3), .S0(n154), .Y(n125) );
XOR2X4TS U160 ( .A(n114), .B(in2[21]), .Y(n4) );
XNOR2X1TS U161 ( .A(n236), .B(n235), .Y(res[24]) );
AOI21X4TS U162 ( .A0(n229), .A1(n240), .B0(n228), .Y(n230) );
OAI21X2TS U163 ( .A0(n365), .A1(n361), .B0(n362), .Y(n360) );
OAI21X2TS U164 ( .A0(n45), .A1(n362), .B0(n357), .Y(n46) );
NAND2X4TS U165 ( .A(n44), .B(in1[8]), .Y(n362) );
NOR2X4TS U166 ( .A(n277), .B(n282), .Y(n260) );
OAI21X4TS U167 ( .A0(n277), .A1(n283), .B0(n278), .Y(n261) );
INVX4TS U168 ( .A(n217), .Y(n240) );
NOR2X4TS U169 ( .A(in2[6]), .B(in2[4]), .Y(n27) );
XNOR2X1TS U170 ( .A(n281), .B(n280), .Y(res[17]) );
NAND2X4TS U171 ( .A(n336), .B(n21), .Y(n12) );
OAI21X1TS U172 ( .A0(n291), .A1(n298), .B0(n295), .Y(n294) );
XNOR2X1TS U173 ( .A(n275), .B(n274), .Y(res[18]) );
NOR2X4TS U174 ( .A(n64), .B(in1[12]), .Y(n300) );
BUFX3TS U175 ( .A(n259), .Y(n276) );
OAI21X2TS U176 ( .A0(n43), .A1(n347), .B0(n352), .Y(n47) );
NAND2X8TS U177 ( .A(n109), .B(n108), .Y(n152) );
OAI21X4TS U178 ( .A0(n258), .A1(n231), .B0(n230), .Y(n236) );
OAI21X4TS U179 ( .A0(n211), .A1(n172), .B0(n171), .Y(n180) );
XOR2X2TS U180 ( .A(n109), .B(in2[16]), .Y(n92) );
XOR2X2TS U181 ( .A(n88), .B(in2[18]), .Y(n5) );
XOR2X2TS U182 ( .A(n173), .B(in2[30]), .Y(n159) );
AOI21X4TS U183 ( .A0(n189), .A1(n193), .B0(n170), .Y(n171) );
INVX2TS U184 ( .A(n188), .Y(n191) );
MXI2X4TS U185 ( .A(n113), .B(n112), .S0(n339), .Y(n130) );
OAI21X2TS U186 ( .A0(n183), .A1(n192), .B0(n182), .Y(n184) );
NOR2X6TS U187 ( .A(n177), .B(in1[31]), .Y(n183) );
MX2X4TS U188 ( .A(in2[31]), .B(n176), .S0(n175), .Y(n177) );
NAND2X4TS U189 ( .A(n124), .B(in1[20]), .Y(n255) );
NOR2X4TS U190 ( .A(n118), .B(in2[20]), .Y(n114) );
XNOR2X4TS U191 ( .A(n118), .B(in2[20]), .Y(n115) );
OAI31X4TS U192 ( .A0(n37), .A1(n36), .A2(in2[0]), .B0(n35), .Y(n41) );
OAI21X4TS U193 ( .A0(n258), .A1(n238), .B0(n237), .Y(n242) );
NOR2X2TS U194 ( .A(n88), .B(in2[18]), .Y(n86) );
OAI21X4TS U195 ( .A0(n264), .A1(n272), .B0(n265), .Y(n98) );
NAND2X4TS U196 ( .A(n97), .B(in1[19]), .Y(n265) );
NOR2X8TS U197 ( .A(n97), .B(in1[19]), .Y(n264) );
MX2X4TS U198 ( .A(in2[19]), .B(n87), .S0(add_sub), .Y(n97) );
XNOR2X4TS U199 ( .A(n139), .B(in2[26]), .Y(n140) );
MXI2X8TS U200 ( .A(n143), .B(n140), .S0(n339), .Y(n141) );
MXI2X4TS U201 ( .A(n121), .B(n120), .S0(n339), .Y(n123) );
NAND2X8TS U202 ( .A(n79), .B(n78), .Y(n85) );
XOR2X1TS U203 ( .A(n258), .B(n257), .Y(res[20]) );
INVX2TS U204 ( .A(n288), .Y(n84) );
NAND3XLTS U205 ( .A(n320), .B(n317), .C(n29), .Y(n30) );
MXI2X2TS U206 ( .A(n93), .B(n92), .S0(n339), .Y(n94) );
NOR2X4TS U207 ( .A(n129), .B(in1[23]), .Y(n217) );
INVX2TS U208 ( .A(n152), .Y(n138) );
NAND2X4TS U209 ( .A(n344), .B(in1[6]), .Y(n347) );
NOR2X1TS U210 ( .A(n344), .B(in1[6]), .Y(n348) );
NOR2BX1TS U211 ( .AN(n15), .B(n14), .Y(n16) );
NAND2X2TS U212 ( .A(in1[9]), .B(n356), .Y(n357) );
NOR2X4TS U213 ( .A(n95), .B(in1[17]), .Y(n277) );
NOR2X2TS U214 ( .A(n94), .B(in1[16]), .Y(n282) );
NAND2X2TS U215 ( .A(n95), .B(in1[17]), .Y(n278) );
NOR2X4TS U216 ( .A(n96), .B(in1[18]), .Y(n271) );
INVX2TS U217 ( .A(n261), .Y(n269) );
INVX2TS U218 ( .A(n260), .Y(n270) );
NAND2X2TS U219 ( .A(n96), .B(in1[18]), .Y(n272) );
INVX4TS U220 ( .A(n276), .Y(n286) );
INVX2TS U221 ( .A(n210), .Y(n157) );
NOR2X4TS U222 ( .A(n141), .B(in1[26]), .Y(n210) );
NOR2X4TS U223 ( .A(n135), .B(n238), .Y(n122) );
NOR2X4TS U224 ( .A(in2[6]), .B(in2[5]), .Y(n11) );
NAND2X1TS U225 ( .A(n319), .B(n20), .Y(n36) );
NAND3XLTS U226 ( .A(n323), .B(n29), .C(n21), .Y(n19) );
NOR2X4TS U227 ( .A(in2[8]), .B(in2[9]), .Y(n56) );
INVX2TS U228 ( .A(in2[10]), .Y(n55) );
NAND3X1TS U229 ( .A(n12), .B(add_sub), .C(n10), .Y(n15) );
NOR2X4TS U230 ( .A(n356), .B(in1[9]), .Y(n45) );
INVX2TS U231 ( .A(n295), .Y(n74) );
NAND3XLTS U232 ( .A(n79), .B(n78), .C(n77), .Y(n80) );
NOR2X4TS U233 ( .A(n123), .B(in1[22]), .Y(n126) );
INVX2TS U234 ( .A(n239), .Y(n228) );
INVX2TS U235 ( .A(n237), .Y(n229) );
NAND2X4TS U236 ( .A(n240), .B(n133), .Y(n135) );
NOR2X4TS U237 ( .A(n63), .B(in1[11]), .Y(n305) );
INVX2TS U238 ( .A(n299), .Y(n309) );
INVX2TS U239 ( .A(n291), .Y(n296) );
NOR2X2TS U240 ( .A(n71), .B(in1[13]), .Y(n291) );
NAND2X2TS U241 ( .A(n71), .B(in1[13]), .Y(n295) );
CLKBUFX2TS U242 ( .A(n290), .Y(n298) );
OAI21X1TS U243 ( .A0(n269), .A1(n271), .B0(n272), .Y(n262) );
NOR2X1TS U244 ( .A(n270), .B(n271), .Y(n263) );
NOR2X2TS U245 ( .A(n124), .B(in1[20]), .Y(n254) );
NAND2X2TS U246 ( .A(n123), .B(in1[22]), .Y(n245) );
NAND2X1TS U247 ( .A(n227), .B(n240), .Y(n231) );
NAND2X1TS U248 ( .A(n219), .B(n227), .Y(n221) );
NAND2X2TS U249 ( .A(n131), .B(in1[25]), .Y(n223) );
NAND2X2TS U250 ( .A(n169), .B(in1[30]), .Y(n192) );
INVX2TS U251 ( .A(n181), .Y(n193) );
NOR2X4TS U252 ( .A(n169), .B(in1[30]), .Y(n181) );
INVX2TS U253 ( .A(n201), .Y(n166) );
NAND2X1TS U254 ( .A(n354), .B(n352), .Y(n351) );
NAND2X1TS U255 ( .A(n358), .B(n357), .Y(n359) );
OR2X1TS U256 ( .A(n356), .B(in1[9]), .Y(n358) );
XOR2XLTS U257 ( .A(n314), .B(n313), .Y(res[10]) );
INVX2TS U258 ( .A(n310), .Y(n312) );
NAND2X1TS U259 ( .A(n307), .B(n306), .Y(n308) );
INVX2TS U260 ( .A(n305), .Y(n307) );
XNOR2X1TS U261 ( .A(n304), .B(n303), .Y(res[12]) );
NAND2X1TS U262 ( .A(n302), .B(n301), .Y(n303) );
INVX2TS U263 ( .A(n300), .Y(n302) );
NAND2X1TS U264 ( .A(n296), .B(n295), .Y(n297) );
XNOR2X1TS U265 ( .A(n294), .B(n293), .Y(res[14]) );
NAND2X1TS U266 ( .A(n292), .B(n6), .Y(n293) );
XNOR2X1TS U267 ( .A(n287), .B(n289), .Y(res[15]) );
NAND2X1TS U268 ( .A(n82), .B(n288), .Y(n289) );
NAND2X1TS U269 ( .A(n284), .B(n283), .Y(n285) );
INVX2TS U270 ( .A(n282), .Y(n284) );
NAND2X1TS U271 ( .A(n279), .B(n278), .Y(n280) );
OAI21X1TS U272 ( .A0(n282), .A1(n276), .B0(n283), .Y(n281) );
OAI21X1TS U273 ( .A0(n270), .A1(n276), .B0(n269), .Y(n275) );
INVX2TS U274 ( .A(n271), .Y(n273) );
NAND2X1TS U275 ( .A(n256), .B(n255), .Y(n257) );
INVX2TS U276 ( .A(n254), .Y(n256) );
NAND2X1TS U277 ( .A(n157), .B(n160), .Y(n142) );
NAND2X1TS U278 ( .A(n7), .B(n212), .Y(n213) );
XNOR2X2TS U279 ( .A(n209), .B(n208), .Y(res[28]) );
AOI21X4TS U280 ( .A0(n48), .A1(n47), .B0(n46), .Y(n313) );
OR2X2TS U281 ( .A(n72), .B(in1[14]), .Y(n6) );
NOR2X2TS U282 ( .A(n305), .B(n300), .Y(n66) );
XOR2X2TS U283 ( .A(n268), .B(n267), .Y(res[19]) );
NOR2X4TS U284 ( .A(n249), .B(n254), .Y(n243) );
NAND2X4TS U285 ( .A(n161), .B(in1[27]), .Y(n212) );
AOI21X2TS U286 ( .A0(n189), .A1(n185), .B0(n184), .Y(n186) );
INVX2TS U287 ( .A(n189), .Y(n190) );
NAND2X4TS U288 ( .A(n125), .B(in1[21]), .Y(n250) );
NOR4X1TS U289 ( .A(n13), .B(n37), .C(n28), .D(n12), .Y(n14) );
INVX4TS U290 ( .A(n205), .Y(n198) );
XNOR2X1TS U291 ( .A(n337), .B(n336), .Y(n326) );
NAND2X4TS U292 ( .A(n109), .B(n104), .Y(n118) );
NAND2X2TS U293 ( .A(n109), .B(n103), .Y(n88) );
MXI2X4TS U294 ( .A(n323), .B(n322), .S0(n339), .Y(n324) );
NAND2X2TS U295 ( .A(n7), .B(n157), .Y(n204) );
INVX2TS U296 ( .A(n204), .Y(n196) );
OA21X4TS U297 ( .A0(n249), .A1(n255), .B0(n250), .Y(n8) );
NAND3X1TS U298 ( .A(n11), .B(in2[9]), .C(n29), .Y(n13) );
NOR3X4TS U299 ( .A(n118), .B(in2[22]), .C(n117), .Y(n105) );
CLKINVX6TS U300 ( .A(in2[5]), .Y(n341) );
INVX2TS U301 ( .A(n292), .Y(n73) );
NOR2X2TS U302 ( .A(n232), .B(n217), .Y(n219) );
NAND2X2TS U303 ( .A(n350), .B(in1[7]), .Y(n352) );
INVX2TS U304 ( .A(n277), .Y(n279) );
INVX2TS U305 ( .A(n249), .Y(n251) );
AOI21X1TS U306 ( .A0(n198), .A1(n150), .B0(n197), .Y(n199) );
NAND2X1TS U307 ( .A(n312), .B(n311), .Y(n314) );
NAND2X1TS U308 ( .A(n273), .B(n272), .Y(n274) );
OR2X8TS U309 ( .A(in2[3]), .B(in2[2]), .Y(n37) );
OR2X8TS U310 ( .A(in2[1]), .B(in2[0]), .Y(n28) );
NOR2X8TS U311 ( .A(n37), .B(n28), .Y(n337) );
INVX2TS U312 ( .A(n337), .Y(n51) );
INVX2TS U313 ( .A(n11), .Y(n9) );
NOR4X2TS U314 ( .A(n51), .B(in2[9]), .C(in2[7]), .D(n9), .Y(n18) );
XNOR2X1TS U315 ( .A(n317), .B(in2[9]), .Y(n17) );
INVX2TS U316 ( .A(in2[9]), .Y(n10) );
CLKINVX6TS U317 ( .A(in2[7]), .Y(n29) );
OAI21X4TS U318 ( .A0(n18), .A1(n17), .B0(n16), .Y(n356) );
INVX2TS U319 ( .A(in2[3]), .Y(n323) );
INVX2TS U320 ( .A(in2[1]), .Y(n319) );
XOR2X1TS U321 ( .A(n21), .B(n317), .Y(n24) );
NAND2X4TS U322 ( .A(n341), .B(n336), .Y(n49) );
NAND2X4TS U323 ( .A(n29), .B(n20), .Y(n50) );
NOR2X8TS U324 ( .A(n49), .B(n50), .Y(n57) );
NOR3X1TS U325 ( .A(n37), .B(n28), .C(n21), .Y(n22) );
AOI22X1TS U326 ( .A0(n57), .A1(n22), .B0(n34), .B1(n21), .Y(n23) );
INVX2TS U327 ( .A(n27), .Y(n26) );
NOR4X1TS U328 ( .A(in2[7]), .B(n26), .C(in2[5]), .D(n37), .Y(n33) );
XOR2X1TS U329 ( .A(n29), .B(n317), .Y(n32) );
NAND4X1TS U330 ( .A(n341), .B(in2[7]), .C(n27), .D(n337), .Y(n31) );
BUFX3TS U331 ( .A(n28), .Y(n320) );
OAI211X4TS U332 ( .A0(n33), .A1(n32), .B0(n31), .C0(n30), .Y(n350) );
INVX2TS U333 ( .A(n34), .Y(n42) );
XOR2X1TS U334 ( .A(n317), .B(in2[6]), .Y(n35) );
INVX2TS U335 ( .A(n320), .Y(n39) );
NOR2X1TS U336 ( .A(n37), .B(in2[5]), .Y(n38) );
OAI211X4TS U337 ( .A0(in2[6]), .A1(n42), .B0(n41), .C0(n40), .Y(n344) );
XOR2X1TS U338 ( .A(n52), .B(in2[10]), .Y(n53) );
MXI2X4TS U339 ( .A(n55), .B(n53), .S0(n317), .Y(n54) );
OAI21X4TS U340 ( .A0(n313), .A1(n310), .B0(n311), .Y(n299) );
NAND2X2TS U341 ( .A(n56), .B(n55), .Y(n60) );
NAND2X8TS U342 ( .A(n337), .B(n57), .Y(n61) );
NOR2X1TS U343 ( .A(n60), .B(n61), .Y(n58) );
XNOR2X1TS U344 ( .A(n58), .B(in2[11]), .Y(n59) );
INVX2TS U345 ( .A(in2[12]), .Y(n67) );
NOR3X8TS U346 ( .A(n61), .B(in2[11]), .C(n60), .Y(n79) );
XOR2X1TS U347 ( .A(n79), .B(in2[12]), .Y(n62) );
OAI21X4TS U348 ( .A0(n300), .A1(n306), .B0(n301), .Y(n65) );
AOI21X4TS U349 ( .A0(n299), .A1(n66), .B0(n65), .Y(n290) );
NAND2X1TS U350 ( .A(n79), .B(n67), .Y(n68) );
XOR2X1TS U351 ( .A(n68), .B(in2[13]), .Y(n69) );
INVX2TS U352 ( .A(in2[14]), .Y(n77) );
XNOR2X1TS U353 ( .A(in2[14]), .B(n85), .Y(n70) );
MXI2X4TS U354 ( .A(n77), .B(n70), .S0(n317), .Y(n72) );
AOI21X4TS U355 ( .A0(n6), .A1(n74), .B0(n73), .Y(n75) );
OAI21X4TS U356 ( .A0(n290), .A1(n76), .B0(n75), .Y(n287) );
XOR2X1TS U357 ( .A(n80), .B(in2[15]), .Y(n81) );
AOI21X4TS U358 ( .A0(n287), .A1(n82), .B0(n84), .Y(n259) );
NOR3X8TS U359 ( .A(n85), .B(in2[15]), .C(in2[14]), .Y(n109) );
NOR2X8TS U360 ( .A(n264), .B(n271), .Y(n99) );
INVX2TS U361 ( .A(in2[16]), .Y(n93) );
AOI21X4TS U362 ( .A0(n261), .A1(n99), .B0(n98), .Y(n100) );
OAI21X4TS U363 ( .A0(n259), .A1(n101), .B0(n100), .Y(n215) );
INVX2TS U364 ( .A(n107), .Y(n104) );
MX2X4TS U365 ( .A(in2[23]), .B(n106), .S0(n175), .Y(n129) );
NOR4X2TS U366 ( .A(n107), .B(n117), .C(in2[23]), .D(in2[22]), .Y(n108) );
INVX2TS U367 ( .A(in2[24]), .Y(n113) );
XNOR2X1TS U368 ( .A(n152), .B(in2[24]), .Y(n112) );
INVX2TS U369 ( .A(in2[20]), .Y(n116) );
INVX2TS U370 ( .A(in2[22]), .Y(n121) );
NOR2X8TS U371 ( .A(n128), .B(n127), .Y(n237) );
AOI21X4TS U372 ( .A0(n133), .A1(n228), .B0(n132), .Y(n134) );
OA21X4TS U373 ( .A0(n237), .A1(n135), .B0(n134), .Y(n136) );
NAND2X8TS U374 ( .A(n137), .B(n136), .Y(n206) );
INVX16TS U375 ( .A(n206), .Y(n211) );
INVX2TS U376 ( .A(in2[26]), .Y(n143) );
XOR2X1TS U377 ( .A(n211), .B(n142), .Y(res[26]) );
XNOR2X1TS U378 ( .A(n158), .B(in2[29]), .Y(n145) );
MX2X4TS U379 ( .A(in2[29]), .B(n145), .S0(n175), .Y(n165) );
NOR2X2TS U380 ( .A(n152), .B(n147), .Y(n148) );
XNOR2X1TS U381 ( .A(n148), .B(in2[28]), .Y(n149) );
XNOR2X1TS U382 ( .A(n153), .B(in2[27]), .Y(n156) );
OAI2BB1X4TS U383 ( .A0N(n175), .A1N(n156), .B0(n155), .Y(n161) );
AOI21X4TS U384 ( .A0(n163), .A1(n7), .B0(n162), .Y(n205) );
AOI21X4TS U385 ( .A0(n146), .A1(n197), .B0(n166), .Y(n167) );
OAI21X4TS U386 ( .A0(n205), .A1(n168), .B0(n167), .Y(n189) );
XNOR2X1TS U387 ( .A(n174), .B(in2[31]), .Y(n176) );
XNOR2X2TS U388 ( .A(n180), .B(n179), .Y(res[31]) );
OAI21X1TS U389 ( .A0(n187), .A1(n211), .B0(n186), .Y(res[32]) );
OAI21X4TS U390 ( .A0(n211), .A1(n191), .B0(n190), .Y(n195) );
XNOR2X2TS U391 ( .A(n195), .B(n194), .Y(res[30]) );
OAI21X4TS U392 ( .A0(n211), .A1(n200), .B0(n199), .Y(n203) );
XNOR2X4TS U393 ( .A(n203), .B(n202), .Y(res[29]) );
OAI2BB1X4TS U394 ( .A0N(n206), .A1N(n196), .B0(n205), .Y(n209) );
OAI21X4TS U395 ( .A0(n211), .A1(n210), .B0(n160), .Y(n214) );
XNOR2X2TS U396 ( .A(n214), .B(n213), .Y(res[27]) );
AOI21X4TS U397 ( .A0(n229), .A1(n219), .B0(n218), .Y(n220) );
OAI21X4TS U398 ( .A0(n258), .A1(n221), .B0(n220), .Y(n226) );
XNOR2X1TS U399 ( .A(n226), .B(n225), .Y(res[25]) );
OAI21X4TS U400 ( .A0(n258), .A1(n244), .B0(n8), .Y(n248) );
OAI21X4TS U401 ( .A0(n258), .A1(n254), .B0(n255), .Y(n253) );
XNOR2X2TS U402 ( .A(n253), .B(n252), .Y(res[21]) );
AOI21X4TS U403 ( .A0(n286), .A1(n263), .B0(n262), .Y(n268) );
XNOR2X1TS U404 ( .A(n286), .B(n285), .Y(res[16]) );
INVX2TS U405 ( .A(in2[2]), .Y(n316) );
XNOR2X1TS U406 ( .A(n320), .B(in2[2]), .Y(n315) );
MXI2X1TS U407 ( .A(n316), .B(n315), .S0(n339), .Y(n376) );
XOR2X1TS U408 ( .A(n319), .B(in2[0]), .Y(n318) );
MXI2X1TS U409 ( .A(n319), .B(n318), .S0(n317), .Y(n378) );
INVX2TS U410 ( .A(n369), .Y(n325) );
NOR2X1TS U411 ( .A(n320), .B(in2[2]), .Y(n321) );
OR2X2TS U412 ( .A(n324), .B(in1[3]), .Y(n367) );
NAND2X2TS U413 ( .A(n324), .B(in1[3]), .Y(n366) );
INVX2TS U414 ( .A(n366), .Y(n332) );
AOI21X1TS U415 ( .A0(n325), .A1(n367), .B0(n332), .Y(n329) );
MXI2X2TS U416 ( .A(n336), .B(n326), .S0(n339), .Y(n327) );
OR2X2TS U417 ( .A(n327), .B(in1[4]), .Y(n333) );
NAND2X1TS U418 ( .A(n333), .B(n330), .Y(n328) );
NAND2X1TS U419 ( .A(n333), .B(n367), .Y(n335) );
INVX2TS U420 ( .A(n330), .Y(n331) );
AOI21X1TS U421 ( .A0(n333), .A1(n332), .B0(n331), .Y(n334) );
OAI21X4TS U422 ( .A0(n369), .A1(n335), .B0(n334), .Y(n373) );
NAND2X1TS U423 ( .A(n337), .B(n336), .Y(n338) );
XNOR2X1TS U424 ( .A(n338), .B(in2[5]), .Y(n340) );
MXI2X2TS U425 ( .A(n341), .B(n340), .S0(n339), .Y(n342) );
INVX2TS U426 ( .A(n370), .Y(n343) );
AOI21X4TS U427 ( .A0(n373), .A1(n371), .B0(n343), .Y(n349) );
INVX2TS U428 ( .A(n348), .Y(n345) );
NAND2X1TS U429 ( .A(n345), .B(n347), .Y(n346) );
OAI21X2TS U430 ( .A0(n349), .A1(n348), .B0(n347), .Y(n355) );
XNOR2X1TS U431 ( .A(n355), .B(n351), .Y(res[7]) );
INVX2TS U432 ( .A(n352), .Y(n353) );
AOI21X2TS U433 ( .A0(n355), .A1(n354), .B0(n353), .Y(n365) );
XNOR2X1TS U434 ( .A(n360), .B(n359), .Y(res[9]) );
INVX2TS U435 ( .A(n361), .Y(n363) );
NAND2X1TS U436 ( .A(n363), .B(n362), .Y(n364) );
NAND2X1TS U437 ( .A(n367), .B(n366), .Y(n368) );
NAND2X1TS U438 ( .A(n371), .B(n370), .Y(n372) );
XNOR2X1TS U439 ( .A(n373), .B(n372), .Y(res[5]) );
AFHCONX2TS U440 ( .A(in1[2]), .B(n376), .CI(n375), .CON(n369), .S(res[2]) );
AFHCINX2TS U441 ( .CIN(n377), .B(n378), .A(in1[1]), .S(res[1]), .CO(n375) );
initial $sdf_annotate("Approx_adder_GeArN16R6P4_syn.sdf");
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file BRAM_larg.v when simulating
// the core, BRAM_larg. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module BRAM_larg(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb);
input clka;
input [0 : 0] wea;
input [11 : 0] addra;
input [31 : 0] dina;
input clkb;
input [11 : 0] addrb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V3_3 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex5"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(4096),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(4096),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("virtex5"))
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
endmodule
|
(** * Logic: Logic in Coq *)
Require Export MoreProp.
(** Coq's built-in logic is very small: the only primitives are
[Inductive] definitions, universal quantification ([forall]), and
implication ([->]), while all the other familiar logical
connectives -- conjunction, disjunction, negation, existential
quantification, even equality -- can be encoded using just these.
This chapter explains the encodings and shows how the tactics
we've seen can be used to carry out standard forms of logical
reasoning involving these connectives. *)
(* ########################################################### *)
(** * Conjunction *)
(** The logical conjunction of propositions [P] and [Q] can be
represented using an [Inductive] definition with one
constructor. *)
Inductive and (P Q : Prop) : Prop := conj : P -> Q -> (and P Q).
(** Note that, like the definition of [ev] in a previous
chapter, this definition is parameterized; however, in this case,
the parameters are themselves propositions, rather than numbers. *)
(** The intuition behind this definition is simple: to
construct evidence for [and P Q], we must provide evidence
for [P] and evidence for [Q]. More precisely:
- [conj p q] can be taken as evidence for [and P Q] if [p]
is evidence for [P] and [q] is evidence for [Q]; and
- this is the _only_ way to give evidence for [and P Q] --
that is, if someone gives us evidence for [and P Q], we
know it must have the form [conj p q], where [p] is
evidence for [P] and [q] is evidence for [Q].
Since we'll be using conjunction a lot, let's introduce a more
familiar-looking infix notation for it. *)
Notation "P /\ Q" := (and P Q) : type_scope.
(** (The [type_scope] annotation tells Coq that this notation
will be appearing in propositions, not values.) *)
(** Consider the "type" of the constructor [conj]: *)
Check conj.
(* ===> forall P Q : Prop, P -> Q -> P /\ Q *)
(** Notice that it takes 4 inputs -- namely the propositions [P]
and [Q] and evidence for [P] and [Q] -- and returns as output the
evidence of [P /\ Q]. *)
(** Besides the elegance of building everything up from a tiny
foundation, what's nice about defining conjunction this way is
that we can prove statements involving conjunction using the
tactics that we already know. For example, if the goal statement
is a conjuction, we can prove it by applying the single
constructor [conj], which (as can be seen from the type of [conj])
solves the current goal and leaves the two parts of the
conjunction as subgoals to be proved separately. *)
Theorem and_example :
(beautiful 0) /\ (beautiful 3).
Proof.
apply conj.
Case "left". apply b_0.
Case "right". apply b_3. Qed.
(** Just for convenience, we can use the tactic [split] as a shorthand for
[apply conj]. *)
Theorem and_example' :
(ev 0) /\ (ev 4).
Proof.
split.
Case "left". apply ev_0.
Case "right". apply ev_SS. apply ev_SS. apply ev_0. Qed.
(** Conversely, the [inversion] tactic can be used to take a
conjunction hypothesis in the context, calculate what evidence
must have been used to build it, and add variables representing
this evidence to the proof context. *)
Theorem proj1 : forall P Q : Prop,
P /\ Q -> P.
Proof.
intros P Q H.
inversion H as [HP HQ].
apply HP. Qed.
(** **** Exercise: 1 star, optional (proj2) *)
Theorem proj2 : forall P Q : Prop,
P /\ Q -> Q.
Proof.
intros P Q H.
inversion H as [HP HQ].
apply HQ. Qed.
(** [] *)
Theorem and_commut : forall P Q : Prop,
P /\ Q -> Q /\ P.
Proof.
intros P Q H.
inversion H as [HP HQ].
split.
Case "left". apply HQ.
Case "right". apply HP. Qed.
(** **** Exercise: 2 stars (and_assoc) *)
(** In the following proof, notice how the _nested pattern_ in the
[inversion] breaks the hypothesis [H : P /\ (Q /\ R)] down into
[HP: P], [HQ : Q], and [HR : R]. Finish the proof from there: *)
Definition assoc {A: Type} (binop: A -> A -> A): Prop :=
forall a b c: A, binop a (binop b c) = binop (binop a b) c.
Theorem and_assoc : forall P Q R : Prop,
P /\ (Q /\ R) -> (P /\ Q) /\ R.
Proof.
intros P Q R H.
inversion H as [HP [HQ HR]].
split. split. apply HP. apply HQ. apply HR.
Qed.
(** [] *)
(** **** Exercise: 2 stars (even__ev) *)
(** Now we can prove the other direction of the equivalence of [even]
and [ev], which we left hanging in chapter [Prop]. Notice that the
left-hand conjunct here is the statement we are actually interested
in; the right-hand conjunct is needed in order to make the
induction hypothesis strong enough that we can carry out the
reasoning in the inductive step. (To see why this is needed, try
proving the left conjunct by itself and observe where things get
stuck.) *)
Theorem even__ev : forall n : nat,
(even n -> ev n) /\ (even (S n) -> ev (S n)).
Proof.
(* Hint: Use induction on [n]. *)
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** ** Iff *)
(** The handy "if and only if" connective is just the conjunction of
two implications. *)
Definition iff (P Q : Prop) := (P -> Q) /\ (Q -> P).
Notation "P <-> Q" := (iff P Q)
(at level 95, no associativity)
: type_scope.
Theorem iff_implies : forall P Q : Prop,
(P <-> Q) -> P -> Q.
Proof.
intros P Q H.
inversion H as [HAB HBA]. apply HAB. Qed.
Theorem iff_sym : forall P Q : Prop, (P <-> Q) -> (Q <-> P).
Proof.
(* WORKED IN CLASS *)
intros P Q H.
inversion H as [HAB HBA].
split.
Case "->". apply HBA.
Case "<-". apply HAB. Qed.
(** **** Exercise: 1 star, optional (iff_properties) *)
(** Using the above proof that [<->] is symmetric ([iff_sym]) as
a guide, prove that it is also reflexive and transitive. *)
Theorem iff_refl : forall P : Prop,
P <-> P.
Proof. intros. unfold iff. split. tauto. tauto. Qed.
Theorem iff_trans : transitive iff.
Proof.
unfold transitive.
intros. inversion H. inversion H0.
split. intros. apply H3. apply H1. apply H5.
intros. apply H2. apply H4. apply H5.
Qed.
(** Hint: If you have an iff hypothesis in the context, you can use
[inversion] to break it into two separate implications. (Think
about why this works.) *)
(** [] *)
(** Some of Coq's tactics treat [iff] statements specially, thus
avoiding the need for some low-level manipulation when reasoning
with them. In particular, [rewrite] can be used with [iff]
statements, not just equalities. *)
(* ############################################################ *)
(** * Disjunction *)
(** Disjunction ("logical or") can also be defined as an
inductive proposition. *)
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
Notation "P \/ Q" := (or P Q) : type_scope.
(** Consider the "type" of the constructor [or_introl]: *)
Check or_introl.
(* ===> forall P Q : Prop, P -> P \/ Q *)
(** It takes 3 inputs, namely the propositions [P], [Q] and
evidence of [P], and returns, as output, the evidence of [P \/ Q].
Next, look at the type of [or_intror]: *)
Check or_intror.
(* ===> forall P Q : Prop, Q -> P \/ Q *)
(** It is like [or_introl] but it requires evidence of [Q]
instead of evidence of [P]. *)
(** Intuitively, there are two ways of giving evidence for [P \/ Q]:
- give evidence for [P] (and say that it is [P] you are giving
evidence for -- this is the function of the [or_introl]
constructor), or
- give evidence for [Q], tagged with the [or_intror]
constructor. *)
(** Since [P \/ Q] has two constructors, doing [inversion] on a
hypothesis of type [P \/ Q] yields two subgoals. *)
Theorem or_commut : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
inversion H as [HP | HQ].
Case "left". apply or_intror. apply HP.
Case "right". apply or_introl. apply HQ. Qed.
(** From here on, we'll use the shorthand tactics [left] and [right]
in place of [apply or_introl] and [apply or_intror]. *)
Theorem or_commut' : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
inversion H as [HP | HQ].
Case "left". right. apply HP.
Case "right". left. apply HQ. Qed.
Theorem or_distributes_over_and_1 : forall P Q R : Prop,
P \/ (Q /\ R) -> (P \/ Q) /\ (P \/ R).
Proof.
intros P Q R. intros H. inversion H as [HP | [HQ HR]].
Case "left". split.
SCase "left". left. apply HP.
SCase "right". left. apply HP.
Case "right". split.
SCase "left". right. apply HQ.
SCase "right". right. apply HR. Qed.
(** **** Exercise: 2 stars (or_distributes_over_and_2) *)
Theorem or_distributes_over_and_2 : forall P Q R : Prop,
(P \/ Q) /\ (P \/ R) -> P \/ (Q /\ R).
Proof.
intros. inversion H. inversion H0. left. apply H2.
inversion H1. left. apply H3. right. split. apply H2. apply H3.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (or_distributes_over_and) *)
Theorem or_distributes_over_and : forall P Q R : Prop,
P \/ (Q /\ R) <-> (P \/ Q) /\ (P \/ R).
Proof.
intros. split.
apply or_distributes_over_and_1. apply or_distributes_over_and_2.
Qed.
(** [] *)
(* ################################################### *)
(** ** Relating [/\] and [\/] with [andb] and [orb] (advanced) *)
(** We've already seen several places where analogous structures
can be found in Coq's computational ([Type]) and logical ([Prop])
worlds. Here is one more: the boolean operators [andb] and [orb]
are clearly analogs of the logical connectives [/\] and [\/].
This analogy can be made more precise by the following theorems,
which show how to translate knowledge about [andb] and [orb]'s
behaviors on certain inputs into propositional facts about those
inputs. *)
Theorem andb_prop : forall b c,
andb b c = true -> b = true /\ c = true.
Proof.
(* WORKED IN CLASS *)
intros b c H.
destruct b.
Case "b = true". destruct c.
SCase "c = true". apply conj. reflexivity. reflexivity.
SCase "c = false". inversion H.
Case "b = false". inversion H. Qed.
Theorem andb_true_intro : forall b c,
b = true /\ c = true -> andb b c = true.
Proof.
(* WORKED IN CLASS *)
intros b c H.
inversion H.
rewrite H0. rewrite H1. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (bool_prop) *)
Theorem andb_false : forall b c,
andb b c = false -> b = false \/ c = false.
Proof.
intros. destruct b. simpl in H. right. apply H.
left. reflexivity. Qed.
Theorem orb_prop : forall b c,
orb b c = true -> b = true \/ c = true.
Proof.
intros. destruct b. left. reflexivity. simpl in H. right. apply H.
Qed.
Theorem orb_false_elim : forall b c,
orb b c = false -> b = false /\ c = false.
Proof.
intros. split. destruct b. inversion H. reflexivity.
destruct b. simpl in H. inversion H. simpl in H. apply H.
Qed.
(** [] *)
(* ################################################### *)
(** * Falsehood *)
(** Logical falsehood can be represented in Coq as an inductively
defined proposition with no constructors. *)
Inductive False : Prop := .
(** Intuition: [False] is a proposition for which there is no way
to give evidence. *)
(** Since [False] has no constructors, inverting an assumption
of type [False] always yields zero subgoals, allowing us to
immediately prove any goal. *)
Theorem False_implies_nonsense :
False -> 2 + 2 = 5.
Proof.
intros contra.
inversion contra. Qed.
(** How does this work? The [inversion] tactic breaks [contra] into
each of its possible cases, and yields a subgoal for each case.
As [contra] is evidence for [False], it has _no_ possible cases,
hence, there are no possible subgoals and the proof is done. *)
(** Conversely, the only way to prove [False] is if there is already
something nonsensical or contradictory in the context: *)
Theorem nonsense_implies_False :
2 + 2 = 5 -> False.
Proof.
intros contra.
inversion contra. Qed.
(** Actually, since the proof of [False_implies_nonsense]
doesn't actually have anything to do with the specific nonsensical
thing being proved; it can easily be generalized to work for an
arbitrary [P]: *)
Theorem ex_falso_quodlibet : forall (P:Prop),
False -> P.
Proof.
(* WORKED IN CLASS *)
intros P contra.
inversion contra. Qed.
(** The Latin _ex falso quodlibet_ means, literally, "from
falsehood follows whatever you please." This theorem is also
known as the _principle of explosion_. *)
(* #################################################### *)
(** ** Truth *)
(** Since we have defined falsehood in Coq, one might wonder whether
it is possible to define truth in the same way. We can. *)
(** **** Exercise: 2 stars, advanced (True) *)
(** Define [True] as another inductively defined proposition. (The
intution is that [True] should be a proposition for which it is
trivial to give evidence.) *)
Inductive True : Prop := i_am_true.
(** [] *)
(** However, unlike [False], which we'll use extensively, [True] is
used fairly rarely. By itself, it is trivial (and therefore
uninteresting) to prove as a goal, and it carries no useful
information as a hypothesis. But it can be useful when defining
complex [Prop]s using conditionals, or as a parameter to
higher-order [Prop]s. *)
(* #################################################### *)
(** * Negation *)
(** The logical complement of a proposition [P] is written [not
P] or, for shorthand, [~P]: *)
Definition not (P:Prop) := P -> False.
(** The intuition is that, if [P] is not true, then anything at
all (even [False]) follows from assuming [P]. *)
Notation "~ x" := (not x) : type_scope.
Check not.
(* ===> Prop -> Prop *)
(** It takes a little practice to get used to working with
negation in Coq. Even though you can see perfectly well why
something is true, it can be a little hard at first to get things
into the right configuration so that Coq can see it! Here are
proofs of a few familiar facts about negation to get you warmed
up. *)
Theorem not_False :
~ False.
Proof.
unfold not. intros H. inversion H. Qed.
Theorem contradiction_implies_anything : forall P Q : Prop,
(P /\ ~P) -> Q.
Proof.
(* WORKED IN CLASS *)
intros P Q H. inversion H as [HP HNA]. unfold not in HNA.
apply HNA in HP. inversion HP. Qed.
Theorem double_neg : forall P : Prop,
P -> ~~P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not. intros G. apply G. apply H. Qed.
(** **** Exercise: 2 stars, advanced (double_neg_inf) *)
(** Write an informal proof of [double_neg]:
_Theorem_: [P] implies [~~P], for any proposition [P].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars (contrapositive) *)
Theorem contrapositive : forall P Q : Prop,
(P -> Q) -> (~Q -> ~P).
Proof.
intros. unfold not. unfold not in H0. intros. apply H in H1.
apply H0 in H1. apply H1.
Qed.
(** [] *)
(** **** Exercise: 1 star (not_both_true_and_false) *)
Theorem not_both_true_and_false : forall P : Prop,
~ (P /\ ~P).
Proof.
intros. unfold not. intros. inversion H. apply H1 in H0. apply H0.
Qed.
(** [] *)
(** **** Exercise: 1 star, advanced (informal_not_PNP) *)
(** Write an informal proof (in English) of the proposition [forall P
: Prop, ~(P /\ ~P)]. *)
(* FILL IN HERE *)
(** [] *)
Theorem five_not_even :
~ ev 5.
Proof.
(* WORKED IN CLASS *)
unfold not. intros Hev5. inversion Hev5 as [|n Hev3 Heqn].
inversion Hev3 as [|n' Hev1 Heqn']. inversion Hev1. Qed.
(** **** Exercise: 1 star (ev_not_ev_S) *)
(** Theorem [five_not_even] confirms the unsurprising fact that five
is not an even number. Prove this more interesting fact: *)
Theorem ev_not_ev_S : forall n,
ev n -> ~ ev (S n).
Proof.
unfold not. intros n H. induction H.
intros. inversion H. intros. inversion H0.
apply IHev in H2. apply H2.
Qed.
(** [] *)
(** Note that some theorems that are true in classical logic are _not_
provable in Coq's (constructive) logic. E.g., let's look at how
this proof gets stuck... *)
Theorem classic_double_neg : forall P : Prop,
~~P -> P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not in H.
(* But now what? There is no way to "invent" evidence for [~P]
from evidence for [P]. *)
Abort.
(** **** Exercise: 5 stars, advanced, optional (classical_axioms) *)
(** For those who like a challenge, here is an exercise
taken from the Coq'Art book (p. 123). The following five
statements are often considered as characterizations of
classical logic (as opposed to constructive logic, which is
what is "built in" to Coq). We can't prove them in Coq, but
we can consistently add any one of them as an unproven axiom
if we wish to work in classical logic. Prove that these five
propositions are equivalent. *)
Definition peirce := forall P Q: Prop, ((P->Q)->P)->P.
Definition classic := forall P:Prop, ~~P -> P.
Definition excluded_middle := forall P:Prop, P \/ ~P.
Definition de_morgan_not_and_not := forall P Q:Prop, ~(~P /\ ~Q) -> P\/Q.
Definition implies_to_or := forall P Q:Prop, (P->Q) -> (~P\/Q).
(* FILL IN HERE *)
(** [] *)
(* ########################################################## *)
(** ** Inequality *)
(** Saying [x <> y] is just the same as saying [~(x = y)]. *)
Notation "x <> y" := (~ (x = y)) : type_scope.
(** Since inequality involves a negation, it again requires
a little practice to be able to work with it fluently. Here
is one very useful trick. If you are trying to prove a goal
that is nonsensical (e.g., the goal state is [false = true]),
apply the lemma [ex_falso_quodlibet] to change the goal to
[False]. This makes it easier to use assumptions of the form
[~P] that are available in the context -- in particular,
assumptions of the form [x<>y]. *)
Theorem not_false_then_true : forall b : bool,
b <> false -> b = true.
Proof.
intros b H. destruct b.
Case "b = true". reflexivity.
Case "b = false".
unfold not in H.
apply ex_falso_quodlibet.
apply H. reflexivity. Qed.
Lemma succ_neq : forall n m, n <> m -> S n <> S m.
Proof.
intros n.
induction n. intros. destruct m.
unfold not in H. apply ex_falso_quodlibet. apply H. reflexivity.
unfold not. intros. inversion H0.
intros. destruct m. unfold not. intros. inversion H0.
unfold not. intros. inversion H0. unfold not in H.
apply H. rewrite H2. reflexivity.
Qed.
(** **** Exercise: 2 stars (false_beq_nat) *)
Theorem false_beq_nat : forall n m : nat,
n <> m ->
beq_nat n m = false.
Proof.
intros n m neq. generalize dependent m. induction n.
Case "n = 0". induction m.
SCase "m = 0".
unfold not. intros. apply ex_falso_quodlibet. apply neq. reflexivity.
SCase "m = S m".
intros. simpl. reflexivity.
Case "n = S n". destruct m.
SCase "m = 0".
simpl. intros. reflexivity.
SCase "m = S m".
simpl. intros. apply IHn. unfold not. intros. rewrite -> H in neq.
unfold not in neq. apply neq. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (beq_nat_false) *)
Theorem beq_nat_false : forall n m,
beq_nat n m = false -> n <> m.
Proof.
intros n m neq. generalize dependent m.
induction n.
Case "n = 0". destruct m.
SCase "m = 0". simpl. intros. inversion neq.
SCase "m = S m". simpl. unfold not. intros. inversion H.
Case "n = S n". destruct m.
SCase "m = 0". simpl. unfold not. intros. inversion H.
SCase "m = S m".
simpl. unfold not. intros. apply IHn in neq. inversion H. contradiction.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (ble_nat_false) *)
Theorem ble_nat_false : forall n m,
ble_nat n m = false -> ~(n <= m).
Proof.
intros n m ble. generalize dependent m.
induction n. destruct m. simpl. intros. inversion ble.
simpl. intros. inversion ble.
destruct m. simpl. intros. unfold not. intros. inversion H.
simpl. intros. apply IHn in ble.
unfold not. intros contra. inversion contra. unfold not in ble.
rewrite H0 in ble. apply ble. apply le_n. unfold not in ble.
apply ble. apply Sn_le_Sm__n_le_m. apply contra.
Qed.
(** [] *)
Lemma beq_nat_true_eq: forall n m, n = m -> beq_nat n m = true.
Proof.
intros n. induction n.
intros. rewrite <- H. reflexivity.
intros. rewrite -> H. rewrite <- beq_nat_refl. reflexivity.
Qed.
Definition boolfunc_prop_equiv {A B: Type}
(boolfunc: A -> B -> bool) (prop: A -> B -> Prop) :=
forall (x: A) (y: B), (boolfunc x y = true -> prop x y) /\
(boolfunc x y = false -> ~(prop x y)) /\
(prop x y -> boolfunc x y = true) /\
(~(prop x y) -> boolfunc x y = false).
Check eq.
Lemma beq_nat_works : boolfunc_prop_equiv beq_nat eq.
Proof.
unfold boolfunc_prop_equiv. intros.
split. apply beq_nat_true. split. apply beq_nat_false.
split. apply beq_nat_true_eq. apply false_beq_nat.
Qed.
(* ############################################################ *)
(** * Existential Quantification *)
(** Another critical logical connective is _existential
quantification_. We can express it with the following
definition: *)
Inductive ex (X:Type) (P : X->Prop) : Prop :=
ex_intro : forall (witness:X), P witness -> ex X P.
(** That is, [ex] is a family of propositions indexed by a type [X]
and a property [P] over [X]. In order to give evidence for the
assertion "there exists an [x] for which the property [P] holds"
we must actually name a _witness_ -- a specific value [x] -- and
then give evidence for [P x], i.e., evidence that [x] has the
property [P].
*)
(** Coq's [Notation] facility can be used to introduce more
familiar notation for writing existentially quantified
propositions, exactly parallel to the built-in syntax for
universally quantified propositions. Instead of writing [ex nat
ev] to express the proposition that there exists some number that
is even, for example, we can write [exists x:nat, ev x]. (It is
not necessary to understand exactly how the [Notation] definition
works.) *)
Notation "'exists' x , p" := (ex _ (fun x => p))
(at level 200, x ident, right associativity) : type_scope.
Notation "'exists' x : X , p" := (ex _ (fun x:X => p))
(at level 200, x ident, right associativity) : type_scope.
(** We can use the usual set of tactics for
manipulating existentials. For example, to prove an
existential, we can [apply] the constructor [ex_intro]. Since the
premise of [ex_intro] involves a variable ([witness]) that does
not appear in its conclusion, we need to explicitly give its value
when we use [apply]. *)
Example exists_example_1 : exists n, n + (n * n) = 6.
Proof.
apply ex_intro with (witness:=2).
reflexivity. Qed.
(** Note that we have to explicitly give the witness. *)
(** Or, instead of writing [apply ex_intro with (witness:=e)] all the
time, we can use the convenient shorthand [exists e], which means
the same thing. *)
Example exists_example_1' : exists n, n + (n * n) = 6.
Proof.
exists 2.
reflexivity. Qed.
(** Conversely, if we have an existential hypothesis in the
context, we can eliminate it with [inversion]. Note the use
of the [as...] pattern to name the variable that Coq
introduces to name the witness value and get evidence that
the hypothesis holds for the witness. (If we don't
explicitly choose one, Coq will just call it [witness], which
makes proofs confusing.) *)
Theorem exists_example_2 : forall n,
(exists m, n = 4 + m) ->
(exists o, n = 2 + o).
Proof.
intros n H.
inversion H as [m Hm].
exists (2 + m).
apply Hm. Qed.
(** **** Exercise: 1 star, optional (english_exists) *)
(** In English, what does the proposition
ex nat (fun n => beautiful (S n))
]]
mean? *)
(* We have a proposition on numbers that states "the successor of this number is
beautiful". So the proposition states, "there exists a natural number whose
successor is beautiful." In fact, let's prove this silly thing. *)
Theorem exists_beautiful_succ: exists n, beautiful (S n).
Proof. exists 2. apply b_3. Qed.
(** **** Exercise: 1 star (dist_not_exists) *)
(** Prove that "[P] holds for all [x]" implies "there is no [x] for
which [P] does not hold." *)
Theorem dist_not_exists : forall (X:Type) (P : X -> Prop),
(forall x, P x) -> ~ (exists x, ~ P x).
Proof.
intros. unfold not. intros. inversion H0. apply H1. apply H.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (not_exists_dist) *)
(** (The other direction of this theorem requires the classical "law
of the excluded middle".) *)
Theorem not_exists_dist :
excluded_middle ->
forall (X:Type) (P : X -> Prop),
~ (exists x, ~ P x) -> (forall x, P x).
Proof.
intros.
unfold excluded_middle in H.
unfold not in H. unfold not in H0.
destruct H with (P:=P x). apply H1. apply ex_falso_quodlibet.
apply H0. exists x. apply H1.
Qed.
(** [] *)
(** **** Exercise: 2 stars (dist_exists_or) *)
(** Prove that existential quantification distributes over
disjunction. *)
Theorem dist_exists_or : forall (X:Type) (P Q : X -> Prop),
(exists x, P x \/ Q x) <-> (exists x, P x) \/ (exists x, Q x).
Proof.
intros. split.
Case "->".
intros. inversion H. inversion H0.
left. exists witness. apply H1.
right. exists witness. apply H1.
Case "->".
intros. inversion H. inversion H0.
exists witness. left. apply H1.
inversion H0. exists witness. right. apply H1.
Qed.
(** [] *)
(* ###################################################### *)
(** * Equality *)
(** Even Coq's equality relation is not built in. It has (roughly)
the following inductive definition. *)
(* (We enclose the definition in a module to avoid confusion with the
standard library equality, which we have used extensively
already.) *)
Module MyEquality.
Inductive eq {X:Type} : X -> X -> Prop :=
refl_equal : forall x, eq x x.
(** Standard infix notation: *)
Notation "x = y" := (eq x y)
(at level 70, no associativity)
: type_scope.
(** The definition of [=] is a bit subtle. The way to think about it
is that, given a set [X], it defines a _family_ of propositions
"[x] is equal to [y]," indexed by pairs of values ([x] and [y])
from [X]. There is just one way of constructing evidence for
members of this family: applying the constructor [refl_equal] to a
type [X] and a value [x : X] yields evidence that [x] is equal to
[x]. *)
(** **** Exercise: 2 stars (leibniz_equality) *)
(** The inductive definitions of equality corresponds to _Leibniz equality_:
what we mean when we say "[x] and [y] are equal" is that every
property on [P] that is true of [x] is also true of [y]. *)
Lemma leibniz_equality : forall (X : Type) (x y: X),
x = y -> forall P : X -> Prop, P x -> P y.
Proof.
intros. inversion H. rewrite <- H2. apply H0.
Qed.
(** [] *)
(** We can use
[refl_equal] to construct evidence that, for example, [2 = 2].
Can we also use it to construct evidence that [1 + 1 = 2]? Yes:
indeed, it is the very same piece of evidence! The reason is that
Coq treats as "the same" any two terms that are _convertible_
according to a simple set of computation rules. These rules,
which are similar to those used by [Eval compute], include
evaluation of function application, inlining of definitions, and
simplification of [match]es.
*)
Lemma four: 2 + 2 = 1 + 3.
Proof.
apply refl_equal.
Qed.
(** The [reflexivity] tactic that we have used to prove equalities up
to now is essentially just short-hand for [apply refl_equal]. *)
End MyEquality.
(* ###################################################### *)
(** * Evidence-carrying booleans. *)
(** So far we've seen two different forms of equality predicates:
[eq], which produces a [Prop], and
the type-specific forms, like [beq_nat], that produce [boolean]
values. The former are more convenient to reason about, but
we've relied on the latter to let us use equality tests
in _computations_. While it is straightforward to write lemmas
(e.g. [beq_nat_true] and [beq_nat_false]) that connect the two forms,
using these lemmas quickly gets tedious.
It turns out that we can get the benefits of both forms at once
by using a construct called [sumbool]. *)
Inductive sumbool (A B : Prop) : Set :=
| left : A -> sumbool A B
| right : B -> sumbool A B.
Notation "{ A } + { B }" := (sumbool A B) : type_scope.
(** Think of [sumbool] as being like the [boolean] type, but instead
of its values being just [true] and [false], they carry _evidence_
of truth or falsity. This means that when we [destruct] them, we
are left with the relevant evidence as a hypothesis -- just as with [or].
(In fact, the definition of [sumbool] is almost the same as for [or].
The only difference is that values of [sumbool] are declared to be in
[Set] rather than in [Prop]; this is a technical distinction
that allows us to compute with them.) *)
(** Here's how we can define a [sumbool] for equality on [nat]s *)
Theorem eq_nat_dec : forall n m : nat, {n = m} + {n <> m}.
Proof.
intros n.
induction n as [|n'].
Case "n = 0".
intros m.
destruct m as [|m'].
SCase "m = 0".
left. reflexivity.
SCase "m = S m'".
right. intros contra. inversion contra.
Case "n = S n'".
intros m.
destruct m as [|m'].
SCase "m = 0".
right. intros contra. inversion contra.
SCase "m = S m'".
destruct IHn' with (m := m') as [eq | neq].
left. apply f_equal. apply eq.
right. intros Heq. inversion Heq as [Heq']. apply neq. apply Heq'.
Defined.
(** Read as a theorem, this says that equality on [nat]s is decidable:
that is, given two [nat] values, we can always produce either
evidence that they are equal or evidence that they are not.
Read computationally, [eq_nat_dec] takes two [nat] values and returns
a [sumbool] constructed with [left] if they are equal and [right]
if they are not; this result can be tested with a [match] or, better,
with an [if-then-else], just like a regular [boolean].
(Notice that we ended this proof with [Defined] rather than [Qed].
The only difference this makes is that the proof becomes _transparent_,
meaning that its definition is available when Coq tries to do reductions,
which is important for the computational interpretation.)
Here's a simple example illustrating the advantages of the [sumbool] form. *)
Definition override' {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if eq_nat_dec k k' then x else f k'.
Theorem override_same' : forall (X:Type) x1 k1 (f : nat->X),
f k1 = x1 ->
forall k2, (override' f k1 x1) k2 = f k2.
Proof.
intros X x1 k1 f. intros Hx1 k2.
unfold override'.
destruct (eq_nat_dec k1 k2). (* observe what appears as a hypothesis *)
Case "k1 = k2".
rewrite <- e.
symmetry. apply Hx1.
Case "k1 <> k2".
reflexivity. Qed.
(** Compare this to the more laborious proof (in MoreCoq.v) for the
version of [override] defined using [beq_nat], where we had to
use the auxiliary lemma [beq_nat_true] to convert a fact about booleans
to a Prop. *)
(** **** Exercise: 1 star (override_shadow') *)
Theorem override_shadow' : forall (T:Type) out1 out2 in1 in2 (func : nat->T),
(override' (override' func in1 out2) in1 out1) in2 =
(override' func in1 out1) in2.
Proof.
intros. unfold override'.
destruct (eq_nat_dec in1 in2). reflexivity. reflexivity.
Qed.
(** [] *)
(* ####################################################### *)
(** ** Inversion, Again (Advanced) *)
(** We've seen [inversion] used with both equality hypotheses and
hypotheses about inductively defined propositions. Now that we've
seen that these are actually the same thing, we're in a position
to take a closer look at how [inversion] behaves...
In general, the [inversion] tactic
- takes a hypothesis [H] whose type [P] is inductively defined,
and
- for each constructor [C] in [P]'s definition,
- generates a new subgoal in which we assume [H] was
built with [C],
- adds the arguments (premises) of [C] to the context of
the subgoal as extra hypotheses,
- matches the conclusion (result type) of [C] against the
current goal and calculates a set of equalities that must
hold in order for [C] to be applicable,
- adds these equalities to the context (and, for convenience,
rewrites them in the goal), and
- if the equalities are not satisfiable (e.g., they involve
things like [S n = O]), immediately solves the subgoal. *)
(** _Example_: If we invert a hypothesis built with [or], there are two
constructors, so two subgoals get generated. The
conclusion (result type) of the constructor ([P \/ Q]) doesn't
place any restrictions on the form of [P] or [Q], so we don't get
any extra equalities in the context of the subgoal.
_Example_: If we invert a hypothesis built with [and], there is
only one constructor, so only one subgoal gets generated. Again,
the conclusion (result type) of the constructor ([P /\ Q]) doesn't
place any restrictions on the form of [P] or [Q], so we don't get
any extra equalities in the context of the subgoal. The
constructor does have two arguments, though, and these can be seen
in the context in the subgoal.
_Example_: If we invert a hypothesis built with [eq], there is
again only one constructor, so only one subgoal gets generated.
Now, though, the form of the [refl_equal] constructor does give us
some extra information: it tells us that the two arguments to [eq]
must be the same! The [inversion] tactic adds this fact to the
context. *)
(** **** Exercise: 1 star, optional (dist_and_or_eq_implies_and) *)
Lemma dist_and_or_eq_implies_and : forall P Q R,
P /\ (Q \/ R) /\ Q = R -> P/\Q.
Proof.
intros. inversion H. inversion H1.
destruct H2. split. apply H0. apply H2. rewrite -> H3.
split. apply H0. apply H2.
Qed.
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (all_forallb) *)
(** Inductively define a property [all] of lists, parameterized by a
type [X] and a property [P : X -> Prop], such that [all X P l]
asserts that [P] is true for every element of the list [l]. *)
Inductive all {X : Type} (P : X -> Prop) : list X -> Prop :=
| all_nil : all P []
| all_cons : forall l x, P x -> all P l -> all P (x::l).
Remark all_even_stupid: all ev [2; 4; 10].
Proof.
apply all_cons. apply ev_SS. apply ev_0.
apply all_cons. apply ev_SS. apply ev_SS. apply ev_0.
apply all_cons. apply ev_SS. apply ev_SS. apply ev_SS. apply ev_SS. apply ev_SS. apply ev_0.
apply all_nil.
Qed.
(** Recall the function [forallb], from the exercise
[forall_exists_challenge] in chapter [Poly]: *)
Fixpoint forallb {X : Type} (test : X -> bool) (l : list X) : bool :=
match l with
| [] => true
| x :: l' => andb (test x) (forallb test l')
end.
(** Using the property [all], write down a specification for [forallb],
and prove that it satisfies the specification. Try to make your
specification as precise as possible.
Are there any important properties of the function [forallb] which
are not captured by your specification? *)
Theorem forallb_works: forall T l test,
forallb (X:=T) test l = true -> all (fun x => test x = true) l.
Proof.
intros. induction l.
apply all_nil.
simpl in H. apply all_cons.
apply andb_true_elim1 in H. apply H.
apply andb_true_elim2 in H. apply IHl. apply H.
Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced (filter_challenge) *)
(** One of the main purposes of Coq is to prove that programs match
their specifications. To this end, let's prove that our
definition of [filter] matches a specification. Here is the
specification, written out informally in English.
Suppose we have a set [X], a function [test: X->bool], and a list
[l] of type [list X]. Suppose further that [l] is an "in-order
merge" of two lists, [l1] and [l2], such that every item in [l1]
satisfies [test] and no item in [l2] satisfies test. Then [filter
test l = l1].
A list [l] is an "in-order merge" of [l1] and [l2] if it contains
all the same elements as [l1] and [l2], in the same order as [l1]
and [l2], but possibly interleaved. For example,
[1,4,6,2,3]
is an in-order merge of
[1,6,2]
and
[4,3].
Your job is to translate this specification into a Coq theorem and
prove it. (Hint: You'll need to begin by defining what it means
for one list to be a merge of two others. Do this with an
inductive relation, not a [Fixpoint].) *)
Inductive inorder_merge {T: Type}: list T -> list T -> list T -> Prop :=
| iom_nil_l: forall l, inorder_merge l [] l
| iom_nil_r: forall l, inorder_merge [] l l
| iom_cons: forall x y l1 l2 l, inorder_merge l1 l2 l ->
inorder_merge (x::l1) (y::l2) (x::y::l).
Example iom_1: inorder_merge [1;6;3] [4;2] [1;4;6;2;3].
Proof. apply iom_cons. apply iom_cons. apply iom_nil_l. Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 5 stars, advanced, optional (filter_challenge_2) *)
(** A different way to formally characterize the behavior of [filter]
goes like this: Among all subsequences of [l] with the property
that [test] evaluates to [true] on all their members, [filter test
l] is the longest. Express this claim formally and prove it. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, advanced (no_repeats) *)
(** The following inductively defined proposition... *)
Inductive appears_in {X:Type} (a:X) : list X -> Prop :=
| ai_here : forall l, appears_in a (a::l)
| ai_later : forall b l, appears_in a l -> appears_in a (b::l).
(** ...gives us a precise way of saying that a value [a] appears at
least once as a member of a list [l].
Here's a pair of warm-ups about [appears_in].
*)
Lemma appears_in_app : forall (X:Type) (xs ys : list X) (x:X),
appears_in x (xs ++ ys) -> appears_in x xs \/ appears_in x ys.
Proof.
intros.
induction xs.
Case "xs empty". right. apply H.
Case "xs nonempty".
inversion H.
SCase "ai_here: x is at the head of xs++ys".
left. apply ai_here.
SCase "ai_later: x is in the tail of xs++ys".
apply IHxs in H1. inversion H1.
SSCase "x appears in xs". left. apply ai_later. apply H3.
SSCase "x appears in ys". right. apply H3.
Qed.
Lemma nil_app: forall (X: Type) (l: list X), l ++ [] = l.
Proof. intros. induction l. reflexivity. simpl. rewrite IHl. reflexivity. Qed.
Lemma nothing_in_empty: forall (X: Type) (x: X), ~(appears_in x []).
Proof. unfold not. intros. inversion H. Qed.
Lemma app_appears_in : forall (X:Type) (xs ys : list X) (x:X),
appears_in x xs \/ appears_in x ys -> appears_in x (xs ++ ys).
Proof.
intros. induction xs.
Case "x is empty". destruct ys.
SCase "ys is empty". inversion H. simpl. apply H0. rewrite -> nil_app. apply H0.
SCase "ys is nonempty". simpl. inversion H.
apply ex_falso_quodlibet. apply nothing_in_empty in H0. apply H0.
apply H0.
Case "x is nonempty". inversion H.
SCase "x is in x0::xs". simpl. inversion H0.
SSCase "x is head of xs". apply ai_here.
SSCase "x is in tail of xs". apply ai_later. apply IHxs. left. apply H2.
SCase "x is in ys".
simpl. apply ai_later. apply IHxs. right. apply H0.
Qed.
(** Now use [appears_in] to define a proposition [disjoint X l1 l2],
which should be provable exactly when [l1] and [l2] are
lists (with elements of type X) that have no elements in common. *)
Definition disjoint {T: Type} (l1 l2: list T): Prop :=
forall x:T, appears_in x l1 -> ~(appears_in x l2).
Theorem disjoint_sym: forall T, symmetric (disjoint (T:=T)).
Proof.
unfold symmetric. unfold disjoint. unfold not.
intros T l1 l2 H. intros x contains contra.
apply H in contra. apply contra. apply contains.
Qed.
(** Next, use [appears_in] to define an inductive proposition
[no_repeats X l], which should be provable exactly when [l] is a
list (with elements of type [X]) where every member is different
from every other. For example, [no_repeats nat [1,2,3,4]] and
[no_repeats bool []] should be provable, while [no_repeats nat
[1,2,1]] and [no_repeats bool [true,true]] should not be. *)
Inductive no_repeats {T:Type}: list T -> Prop :=
| no_repeats_nil: no_repeats []
| no_repeats_cons: forall x l, ~(appears_in x l) -> no_repeats (x::l).
Example not_norepeats_11: ~(no_repeats [1;1]).
Proof. unfold not. intros. inversion H. apply H1. apply ai_here. Qed.
Inductive monotonic_increase: list nat -> Prop :=
| incr_nil: monotonic_increase []
| incr_cons: forall l n,
monotonic_increase l -> all (fun m => n <= m) l -> monotonic_increase (n::l).
Definition has_upper_bound (n: nat) (l: list nat): Prop := all (fun m => m <= n) l.
Definition has_lower_bound (n: nat) (l: list nat): Prop := all (fun m => n <= m) l.
Theorem all_applies: forall (T:Type) (elem:T) (l:list T) (P: T -> Prop),
appears_in elem l -> all P l -> P elem.
Proof. intros. induction H.
inversion H0. apply H2.
inversion H0. apply IHappears_in. apply H4.
Qed.
Theorem all_implication: forall (T: Type) (l: list T) (P1 P2: T -> Prop),
(forall x, P1 x -> P2 x) -> all P1 l -> all P2 l.
Proof.
(* Note to self: There's some connection here to category theory... *)
intros. induction l.
apply all_nil.
apply all_cons. inversion H0.
apply H in H3. apply H3.
inversion H0. apply IHl. apply H4.
Qed.
Theorem monotonic_is_bounded:
forall lowest l,
monotonic_increase (lowest::l) -> has_lower_bound lowest l.
Proof.
intros.
inversion H.
unfold has_lower_bound. apply H3.
Qed.
Inductive strict_increase: list nat -> Prop :=
| si_nil: strict_increase []
| si_cons: forall n l,
strict_increase l -> all (fun m => n < m) l -> strict_increase (n::l).
Lemma lt_impl_le: forall n m, n < m -> n <= m.
Proof.
intros. unfold lt in H. apply Sn_le_m_n_le_m in H. apply H.
Qed.
Theorem strict_increase_implies_monotonic_increase: forall l,
strict_increase l -> monotonic_increase l.
Proof.
intros.
induction H. apply incr_nil.
(* Here we need to show that any n is <= any element of l. *)
assert (n_le: all (fun x => n <= x) l).
destruct l. apply all_nil.
apply all_cons. inversion H0.
apply lt_impl_le. apply H3.
Admitted.
(** Finally, state and prove one or more interesting theorems relating
[disjoint], [no_repeats] and [++] (list append). *)
Lemma lt_trans: forall a b c, a < b -> b < c -> a < c.
Proof.
unfold lt. intros. apply Sn_le_m_n_le_m in H0.
apply le_trans with (a:=S a) (b:=b). apply H. apply H0.
Qed.
Lemma Sn_neq_n: forall n, ~(S n = n).
Proof. unfold not. intros. induction n. inversion H.
inversion H. apply IHn. apply H1. Qed.
Lemma Sn_not_le_n: forall n, ~(S n <= n).
Proof. unfold not. intros. induction n.
inversion H.
apply Sn_le_Sm__n_le_m in H. apply IHn. apply H.
Qed.
Lemma ordered_naturals: forall n m, n < m -> ~(m <= n).
Proof.
intros n. unfold not. induction n.
intros. destruct m. inversion H.
inversion H. rewrite <- H2 in H0. apply Sn_not_le_n in H0. apply H0.
inversion H0.
intros. inversion H. rewrite <- H1 in H0. apply Sn_le_Sm__n_le_m in H0.
rewrite <- H1 in H. apply Sn_not_le_n in H0. apply H0.
rewrite <- H2 in H0. apply Sn_le_Sm__n_le_m in H0.
assert (S n <= n).
apply Sn_le_m_n_le_m.
apply le_trans with (a:= S(S n)) (b:=m0) (c:=n). apply H1. apply H0.
apply Sn_not_le_n in H3. apply H3.
Qed.
Theorem disjoint_bounds: forall n m l1 l2,
has_upper_bound n l1 -> has_lower_bound m l2 -> n < m -> disjoint l1 l2.
Proof.
intros n m l1 l2 bounded_up bounded_down n_lt_m.
unfold disjoint. intros elem isinl1.
(* because elem is in l1, we know that it must be <= n. *)
assert (elem <= n).
apply all_applies with (P := fun e => le e n) (l:=l1).
apply isinl1. apply bounded_up.
assert (elem_lt_m: elem < m).
inversion H. apply n_lt_m. apply lt_trans with (b:=n).
rewrite <- H1. unfold lt. apply n_le_m__Sn_le_Sm. apply H0. apply n_lt_m.
unfold not. intros contra.
(* If elem appears in l2, then m <= elem. *)
assert (m_le_elem: m <= elem).
apply all_applies with (P := le m) (l:=l2). apply contra. apply bounded_down.
(* But we earlier proved elem < m, so we have a contradiction. *)
apply ordered_naturals in elem_lt_m. apply elem_lt_m. apply m_le_elem.
Qed.
(** [] *)
(** **** Exercise: 3 stars (nostutter) *)
(** Formulating inductive definitions of predicates is an important
skill you'll need in this course. Try to solve this exercise
without any help at all (except from your study group partner, if
you have one).
We say that a list of numbers "stutters" if it repeats the same
number consecutively. The predicate "[nostutter mylist]" means
that [mylist] does not stutter. Formulate an inductive definition
for [nostutter]. (This is different from the [no_repeats]
predicate in the exercise above; the sequence [1,4,1] repeats but
does not stutter.) *)
Inductive nostutter: list nat -> Prop :=
| nostutter_nil: nostutter []
| nostutter_single: forall n, nostutter [n]
| nostutter_multi: forall n m l,
n <> m -> nostutter l ->
hd_opt l <> Some m ->
nostutter (n::m::l).
Example nostutter_141: nostutter [1;4;1].
Proof.
apply nostutter_multi. unfold not. intros. inversion H.
apply nostutter_single. simpl. unfold not. intros contra.
inversion contra.
Qed.
Example not_nostutter_114: ~(nostutter [1;1;4]).
Proof.
unfold not. intros contra. inversion contra.
unfold not in H2. apply H2. reflexivity.
Qed.
(** Make sure each of these tests succeeds, but you are free
to change the proof if the given one doesn't work for you.
Your definition might be different from mine and still correct,
in which case the examples might need a different proof.
The suggested proofs for the examples (in comments) use a number
of tactics we haven't talked about, to try to make them robust
with respect to different possible ways of defining [nostutter].
You should be able to just uncomment and use them as-is, but if
you prefer you can also prove each example with more basic
tactics. *)
Example test_nostutter_1: nostutter [3;1;4;1;5;6].
apply nostutter_multi. unfold not; intros noteq; inversion noteq.
apply nostutter_multi. unfold not; intros noteq; inversion noteq.
apply nostutter_multi. unfold not; intros noteq; inversion noteq.
apply nostutter_nil. unfold not; intros noteq; inversion noteq.
unfold not; intros noteq; inversion noteq.
unfold not; intros noteq; inversion noteq.
Qed.
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_2: nostutter [].
Proof. apply nostutter_nil. Qed.
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_3: nostutter [5].
Proof. apply nostutter_single. Qed.
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_4: not (nostutter [3;1;1;4]).
Proof. unfold not. intros contra. inversion contra.
simpl in H4. unfold not in H4. apply H4. reflexivity.
Qed.
(*
Proof. intro.
repeat match goal with
h: nostutter _ |- _ => inversion h; clear h; subst
end.
contradiction H1; auto. Qed.
*)
(** [] *)
(** **** Exercise: 4 stars, advanced (pigeonhole principle) *)
(** The "pigeonhole principle" states a basic fact about counting:
if you distribute more than [n] items into [n] pigeonholes, some
pigeonhole must contain at least two items. As is often the case,
this apparently trivial fact about numbers requires non-trivial
machinery to prove, but we now have enough... *)
(** First a pair of useful lemmas (we already proved these for lists
of naturals, but not for arbitrary lists). *)
Lemma app_length : forall (X:Type) (l1 l2 : list X),
length (l1 ++ l2) = length l1 + length l2.
Proof.
intros. induction l1. reflexivity.
simpl. rewrite IHl1. reflexivity.
Qed.
Lemma appears_in_app_split : forall (X:Type) (x:X) (l:list X),
appears_in x l ->
exists l1, exists l2, l = l1 ++ (x::l2).
Proof.
intros. induction l.
inversion H.
inversion H.
exists []. simpl. exists l. reflexivity.
apply IHl in H1.
Admitted.
(** Now define a predicate [repeats] (analogous to [no_repeats] in the
exercise above), such that [repeats X l] asserts that [l] contains
at least one repeated element (of type [X]). *)
Inductive repeats {X:Type} : list X -> Prop :=
| repeats_head: forall x l, repeats (x::x::l)
| repeats_inside: forall x l, repeats l -> repeats (x::l).
(** Now here's a way to formalize the pigeonhole principle. List [l2]
represents a list of pigeonhole labels, and list [l1] represents an
assignment of items to labels: if there are more items than labels,
at least two items must have the same label. You will almost
certainly need to use the [excluded_middle] hypothesis. *)
Theorem pigeonhole_principle: forall (X:Type) (l1 l2:list X),
excluded_middle ->
(forall x, appears_in x l1 -> appears_in x l2) ->
length l2 < length l1 ->
repeats l1.
Proof. intros X l1. induction l1.
intros l2 excl_mid appears contra.
simpl in contra. inversion contra.
intros l2 excl_mid appears smaller.
(* FILL IN HERE *) Admitted.
(** [] *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Display List Processor REgister Block
// File : dlp_reg.v
// Author : Frank Bruno
// Created : 12-May-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
// DLP_REG contains the ping pong registers used in the DLP.
// writing the start address changes the active write registers.
// Consecutively written end addresses are written into the same bank
// as the start addresses are. Readbacks are always of the active regs
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module dlp_reg
(
input hb_clk, /* clock input */
input hb_rstn, /* reset input */
input dlp_rstn_hb, // Sync reset of DLP when stopped
input [8:2] hb_adr, /* host bus address */
input hb_wstrb, /* host bus write strobr. */
input [3:0] hb_ben, /* host bus byte enables */
input hb_csn, /* host bus chip select. -Drawing engine*/
input [31:0] hb_din, /* host bus data */
input [8:2] de_adr, /* host bus address */
input de_wstrb, /* host bus write strobr. */
input [3:0] de_ben, /* host bus byte enables */
input de_csn, /* host bus chip select. -Drawing engine*/
input [31:0] de_din, /* host bus data */
input actv_stp, /* reset dlp_actv */
input next_dle, /* Increment Display List counter */
input cmd_ack, /* Acknowledge start of list */
input reset_wait, // Reset the WCF bit
input [3:0] dlp_offset, // Offset for the DLP
output reg [27:0] hb_addr, /* Current start address */
output reg [27:0] hb_end, /* End address of current list */
output hb_fmt, /* Format of executing list */
output hb_wc, /* WC status of executing list */
output hb_sen, /* Current Source Enable bit */
output hb_stp, /* Status of the current command */
output reg dlp_actv_2, /* Display list active signal */
output dl_idle, /* Display list is idle */
output reg hold_start, /* Start address must be held from being
written */
output reg cmd_rdy_ld, /* Load the command ready when active */
output wcf, /* When set, wait for cache flush */
output reg [4:0] dlp_wcnt /* When set, wait for cache flush */
);
`define DLP_BURST_SIZE 28'h8
`define DLP_BURST_SIZE_M1 5'h7
reg signed [28:0] remainder;
reg dl_cmd_strb; /* Signal to load level 1 CMD to level 2*/
reg start_strobe; /* Signal to load level 1 CMD to level 2*/
reg [27:0] hb_addr1; /* Current address for level 1,1 */
reg [27:0] hb_end1; /* End address for level 1,1 */
reg wc1; /* Wait for cache to clear 1,1 */
reg [3:0] hb_cntrl_w1; /* Control signals for level 1,1 */
reg wc2; /* Wait for cache to clear 2,1 */
reg [3:0] hb_cntrl_w2; /* Control signals for level 2,1 */
reg [1:0] adr_cntrl2; /* start control signals for level 2,1 */
reg [1:0] adr_cntrl1; /* start control signals for level 1,1 */
wire next_stp; /* Execute next command bit */
wire toggle_out; /* Toggle the output pointer */
wire dlp_hb_w; /* Host bus write to the DLP */
wire dlp_de_w; /* Write to the DLP from w/in a list */
wire start_strobe_comb;
//`include "de_host_adr.h"
parameter DLCNT_DLADR = 6'b0_1111_1; /* address 0x0f8 and 0x0fc */
always @(posedge hb_clk or negedge hb_rstn) begin
if (!hb_rstn) cmd_rdy_ld <= 1'b0;
else if (dlp_rstn_hb) cmd_rdy_ld <= 1'b0;
else if (dl_cmd_strb || start_strobe && dl_idle) cmd_rdy_ld <= 1'b1;
else if (cmd_ack) cmd_rdy_ld <= 1'b0;
end
/************************************************************************/
/* REGISTER DECODER */
/* Current Instruction Registers level 1 */
/************************************************************************/
assign dlp_hb_w = (hb_adr[8:3]==DLCNT_DLADR) && hb_wstrb && !hb_csn;
assign dlp_de_w = (de_adr[8:3]==DLCNT_DLADR) && de_wstrb && !de_csn;
assign start_strobe_comb = ((dlp_hb_w & ~hb_ben[3] & ~hb_adr[2]) |
(dlp_de_w & ~de_adr[2]));
wire stop_list;
assign stop_list = ~hb_cntrl_w2[3] && hb_cntrl_w1[3];
// Added frank's synchronous hb_rstn here to match the gates. Vic
always @(posedge hb_clk) begin
if (!hb_rstn) begin
dl_cmd_strb <= 1'b0;
hb_addr1 <= 28'b0;
hb_end1 <= 28'b0;
adr_cntrl1 <= 2'b0;
wc1 <= 1'b0;
hb_cntrl_w1 <= 4'b0;
hb_addr <= 28'b0;
hb_end <= 28'b0;
hb_cntrl_w2 <= 4'b1000;
start_strobe <= 1'b0;
adr_cntrl2 <= 2'b0;
wc2 <= 1'b0;
hold_start <= 1'b0;
remainder <= 0;
end else if (dlp_rstn_hb) begin
dl_cmd_strb <= 1'b0;
start_strobe <= 1'b0;
hb_cntrl_w2 <= 4'b1000;
hold_start <= 1'b0;
remainder <= 0;
end else begin
remainder <= (hb_end - hb_addr);
if (start_strobe_comb) start_strobe <= 1'b1;
/**********************************************************************/
/* Load the address register, host bus has priority over DE. */
/**********************************************************************/
if (dlp_hb_w && ~hb_adr[2]) begin
hold_start <= 1'b1;
// Load level 1_1 from Host Bus
if(!hb_ben[0]) hb_addr1[3:0] <= hb_din[7:4];
if(!hb_ben[1]) hb_addr1[11:4] <= hb_din[15:8];
if(!hb_ben[2]) hb_addr1[19:12] <= hb_din[23:16];
if(!hb_ben[3]) begin
hb_addr1[27:20] <= {dlp_offset, hb_din[27:24]};
end
if(!hb_ben[3]) adr_cntrl1 <= hb_din[30:29];
if(!hb_ben[3]) wc1 <= hb_din[31];
end else if (dlp_de_w && ~de_adr[2]) begin
hold_start <= 1'b1;
// Load level 1_1 from Within the DLP
if(!de_ben[0]) hb_addr1[3:0] <= de_din[7:4];
if(!de_ben[1]) hb_addr1[11:4] <= de_din[15:8];
if(!de_ben[2]) hb_addr1[19:12] <= de_din[23:16];
if(!de_ben[3]) begin
hb_addr1[27:20] <= {dlp_offset, de_din[27:24]};
end
if(!de_ben[3]) adr_cntrl1 <= de_din[30:29]; // was hb_din??
if(!de_ben[3]) wc1 <= de_din[31];
end
/**********************************************************************/
/* Load the control register, host bus has priority over DE. Use the */
/* inverted pointer register. The control register always points to */
/* the oposite register than the start address. */
/**********************************************************************/
// Load level 1_1 from Host Bus
if (dlp_hb_w && hb_adr[2]) begin
dl_cmd_strb <= ~hb_ben[3];
if(!hb_ben[0]) hb_end1[3:0] <= hb_din[7:4];
if(!hb_ben[1]) hb_end1[11:4] <= hb_din[15:8];
if(!hb_ben[2]) hb_end1[19:12] <= hb_din[23:16];
if(!hb_ben[3]) begin
hb_end1[27:20] <= {dlp_offset, hb_din[27:24]};
end
if(!hb_ben[3]) hb_cntrl_w1[3:0] <= hb_din[31:28];
end else if (dlp_de_w && de_adr[2]) begin
dl_cmd_strb <= ~de_ben[3];
// Load level 1_1 from Within the DLP
if(!de_ben[0]) hb_end1[3:0] <= de_din[7:4];
if(!de_ben[1]) hb_end1[11:4] <= de_din[15:8];
if(!de_ben[2]) hb_end1[19:12] <= de_din[23:16];
if(!de_ben[3]) begin
hb_end1[27:20] <= {dlp_offset, de_din[27:24]};
end
if(!de_ben[3]) hb_cntrl_w1[3:0] <= de_din[31:28];
end
/***********************************************************************/
/* Current Instruction Register level 2 */
/***********************************************************************/
// Reset the WCF bit after first wait
if (reset_wait) adr_cntrl2[0] <= 1'b0;
if (dl_cmd_strb && ~hold_start && stop_list && ~dl_idle) begin
hb_addr <= hb_end1-28'h1;
start_strobe <= 1'b0;
dl_cmd_strb <= 1'b0;
//dl_idle <= 1'b1;
end else if (start_strobe && dl_idle) begin
hold_start <= 1'b0;
start_strobe <= 1'b0;
hb_addr <= hb_addr1;
adr_cntrl2 <= adr_cntrl1;
wc2 <= wc1;
end else if (next_dle && ~dl_idle)
hb_addr <= hb_addr + 28'h1;
if (dl_cmd_strb && ~hold_start)
begin
hb_end <= hb_end1;
hb_cntrl_w2 <= hb_cntrl_w1;
dl_cmd_strb <= 1'b0;
end
else if (dl_idle && ~start_strobe)
hb_cntrl_w2[3] <= 1'b1;
end // else: !if(!hb_rstn)
end // always @ (posedge hb_clk)
/*
always @* begin
if (({1'b0, hb_end} - {1'b0, hb_addr}) >= `DLP_BURST_SIZE)
dlp_wcnt = `DLP_BURST_SIZE_M1;
else
dlp_wcnt = (hb_end - hb_addr) - 1'b1;
end
*/
//always @* remainder = (hb_end - hb_addr) - `DLP_BURST_SIZE;
always @*
if(remainder > `DLP_BURST_SIZE) dlp_wcnt = `DLP_BURST_SIZE_M1;
else dlp_wcnt = remainder -1'b1;
/************************************************************************/
/* Current DLP instruction Mux */
/************************************************************************/
assign hb_fmt = hb_cntrl_w2[1];
assign hb_sen = hb_cntrl_w2[2];
assign hb_stp = hb_cntrl_w2[3];
assign hb_wc = wc2;
assign wcf = adr_cntrl2[0];
/************************************************************************/
/* DLP next instruction command */
/************************************************************************/
reg dl_idle_hold;
assign dl_idle = (hb_addr == hb_end) | dl_idle_hold; // DLP is done w/ current command
always @(posedge hb_clk, negedge hb_rstn) begin
if (!hb_rstn) dl_idle_hold <= 1'b0;
//else if (hb_stp) dl_idle_hold <= 1'b0;
else if (dl_cmd_strb && ~hold_start) dl_idle_hold <= 1'b0;
else if (hb_stp || dl_idle) dl_idle_hold <= 1'b1;
end
assign next_stp = hb_cntrl_w2[3];
assign toggle_out = dl_idle & ~next_stp;
/************************************************************************/
/* Generate active signal */
/************************************************************************/
always @(posedge hb_clk or negedge hb_rstn) begin
if(!hb_rstn) dlp_actv_2 <= 1'b0;
else if(dlp_rstn_hb) dlp_actv_2 <= 1'b0;
else if ((dl_cmd_strb && ~hb_cntrl_w1[3]) || toggle_out) dlp_actv_2 <= 1'b1;
else if ((~actv_stp && dl_idle && next_stp) ||
(dl_cmd_strb && hb_cntrl_w1[3])) dlp_actv_2 <= 1'b0;
end
endmodule
|
/*
* Titor - System - ASCII Character Display
* Copyright (C) 2012,2013 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_block_Character_Screen
`else
`define INC_block_Character_Screen
`timescale 1 ns / 100 ps
// Memory module
// takes values written to it in ASCII and prints it out to a 640 X 480 VGA screen
// 106 characters (and then some) wide, 60 characters tall
module block_Character_Screen (
dout,
din,
address,
size,
read_write,
enable,
VGA_hsync,
VGA_vsync,
VGA_pixel,
clk,
reset
);
`include "definition/Definition.v"
output wire [WORD-1:0] dout;
input wire [WORD-1:0] din;
input wire [WORD-1:0] address;
input wire [LOGWORDBYTE-1:0] size;
input wire read_write;
input wire enable;
output reg VGA_hsync;
output reg VGA_vsync;
output reg VGA_pixel;
input wire clk;
input wire reset;
reg [WORD-1:0] x [0:0];
reg [WORD-1:0] y [0:0];
reg [0:0] hsync [1:0];
reg [0:0] vsync [1:0];
reg [0:0] blank [1:0];
wire out_VGA_hsync;
wire out_VGA_vsync;
wire out_pixel_blank;
wire [WORD-1:0] out_bit_row;
wire [WORD-1:0] out_bit_column;
wire [WORD-1:0] out_char_row;
wire [WORD-1:0] out_char_column;
wire [WORD-1:0] out_screen_row;
wire [WORD-1:0] out_screen_column;
wire [WORD-1:0] out_char_offset;
wire out_char_blank;
wire [WORD-1:0] out_ascii;
wire out_pixel;
reg out_invert;
wire [WORD-1:0] buffer_address_read;
assign buffer_address_read = out_char_offset + out_char_column;
always @(posedge clk) begin
if(reset) begin
x[0] <= 0;
y[0] <= 0;
hsync[0] <= 0;
vsync[0] <= 0;
blank[0] <= 0;
hsync[1] <= 0;
vsync[1] <= 0;
blank[1] <= 0;
VGA_hsync <= 0;
VGA_vsync <= 0;
VGA_pixel <= 0;
out_invert <= 0;
end else begin
x[0] <= out_bit_column;
y[0] <= out_bit_row;
hsync[0] <= out_VGA_hsync;
vsync[0] <= out_VGA_vsync;
blank[0] <= out_pixel_blank || out_char_blank;
hsync[1] <= hsync[0];
vsync[1] <= vsync[0];
blank[1] <= blank[0];
VGA_hsync <= hsync[1];
VGA_vsync <= vsync[1];
VGA_pixel <= blank[1] ? 0 : (out_invert^^out_pixel);
out_invert <= out_ascii[ASCII_WIDTH];
end
end
FSM_VGA fsm_vga(
.VGA_hsync (out_VGA_hsync ),
.VGA_vsync (out_VGA_vsync ),
.pixel_blank (out_pixel_blank ),
.screen_row (out_screen_row ),
.screen_column (out_screen_column ),
.reset (reset ),
.clk (clk )
);
FSM_Character fsm_character(
.bit_row (out_bit_row ), .bit_column (out_bit_column ),
.char_row (out_char_row ), .char_column (out_char_column ),
.screen_row (out_screen_row ), .screen_column (out_screen_column ),
.char_offset (out_char_offset ),
.char_blank (out_char_blank ),
.reset (reset ),
.clk (clk )
);
DualMemory #(
.memfile (BLANKFILE ),
.LOGMEM (CHARMEM_BITSIZE )
)
character_buffer (
// the one that talks on the bus
.A_dout (dout ),
.A_din (din ),
.A_address (address ),
.A_size (size ),
.A_read_write (read_write ),
.A_enable (enable ),
// the one that sits in the character device pipeline
.B_dout (out_ascii ),
.B_din (0 ),
.B_address (buffer_address_read ),
.B_size (0 ), // read (1<<0) bytes
.B_read_write (READ ),
.B_enable (ENABLE[0:0] ), // down-convert the value to 1 bit
.reset(reset),
.clk(clk)
);
Character_Map
mapping (
.ascii ({1'b0,out_ascii[ASCII_WIDTH-1:0]} ),
.bit_y (y[0] ),
.bit_x (x[0] ),
.pixel (out_pixel ),
.reset (reset ),
.clk (clk )
);
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4B_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__AND4B_PP_BLACKBOX_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and4b (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4B_PP_BLACKBOX_V
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bg2_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module bg2_new (
address,
clock,
q);
input [14:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/bg2-new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/bg2-new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bg2_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg2_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg2_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg2_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg2_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg2_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Sincronizador ////
//// ////
//// ////
//// Este archivo describe el comportamiento ////
//// de un soncronizador antirrebote en Verilog ////
//// ////
//// Description ////
//// Modulo encargado de sincronizar las entradas con el reloj ////
//// del sistema. Tiene como entradas 3 bits del identificador ////
//// del piso en código Gray, la señal binaria del sensor de ////
//// sobrepeso, la señal binaria del sensor de obtaculización ////
//// de la puerta y los 2 bits por cada uno de los 5 pisos donde ////
//// el MSB es señal desubida y el LSB de bajada. ////
//// Su funcionamiento se basa en pasar cada una de las entradas////
//// por 2 flipflops para sincronizar los pulsos con el reloj ////
//// del sistema, luego se encarga de tomar 4 muestras de las ////
//// entradas cada 10ms y asi se identifica el estado en que ////
//// se encuentran. ////
//// ////
//// ////
//// ////
//// ////
//// Autor : ////
//// - Manuel Zumbado Corrales [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
/// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module Sincronizador( _clk_, piso_actual_i, sensor_sobrePeso_i, sensor_puerta_i, solicitud_ps_i, solicitud_p1_i,
solicitud_p2_i, solicitud_p3_i, solicitud_p4_i, piso_actual_o, sensor_sobrePeso_o,
sensor_puerta_o, solicitud_ps_o, solicitud_p1_o, solicitud_p2_o, solicitud_p3_o,
solicitud_p4_o);
//Se definen las entradas y salidas del módulo
input sensor_sobrePeso_i, sensor_puerta_i, _clk_;
input [2:0] piso_actual_i;
input [1:0] solicitud_ps_i, solicitud_p1_i, solicitud_p2_i, solicitud_p3_i, solicitud_p4_i;
output reg sensor_sobrePeso_o, sensor_puerta_o;
output reg [2:0] piso_actual_o;
output reg [1:0] solicitud_ps_o, solicitud_p1_o, solicitud_p2_o, solicitud_p3_o, solicitud_p4_o;
//El contador cuenta hasta 10ms, por lo que se almacena 1000000.
localparam contador_max= 20'd1000000;
//Se crea el primer registro (flip-flop) por cada entrada para sincronizarlos con el clk
reg sensor_sobrePeso_sync_0;
reg sensor_puerta_sync_0;
reg [2:0] piso_actual_sync_0;
reg [1:0] solicitud_ps_sync_0;
reg [1:0] solicitud_p1_sync_0;
reg [1:0] solicitud_p2_sync_0;
reg [1:0] solicitud_p3_sync_0;
reg [1:0] solicitud_p4_sync_0;
//En cada estado positivo del clk, los registros guardan los valores de los botones/switches
always @(posedge _clk_)
begin
sensor_sobrePeso_sync_0 <= sensor_sobrePeso_i;
sensor_puerta_sync_0 <= sensor_puerta_i;
piso_actual_sync_0 <= piso_actual_i;
solicitud_ps_sync_0 <= solicitud_ps_i;
solicitud_p1_sync_0 <= solicitud_p1_i;
solicitud_p2_sync_0 <= solicitud_p2_i;
solicitud_p3_sync_0 <= solicitud_p3_i;
solicitud_p4_sync_0 <= solicitud_p4_i;
end
//Se crea el segundo registro (flip-flop) por cada salida de los registros anteriores para sincronizarlos con el clk
reg sensor_sobrePeso_sync_1;
reg sensor_puerta_sync_1;
reg [2:0] piso_actual_sync_1;
reg [1:0] solicitud_ps_sync_1;
reg [1:0] solicitud_p1_sync_1;
reg [1:0] solicitud_p2_sync_1;
reg [1:0] solicitud_p3_sync_1;
reg [1:0] solicitud_p4_sync_1;
//En cada estado positivo del clk, los registros guardan los valores el registro anterior para sincronizar con el clk
always @(posedge _clk_)
begin
sensor_sobrePeso_sync_1 <= sensor_sobrePeso_sync_0;
sensor_puerta_sync_1 <= sensor_puerta_sync_0;
piso_actual_sync_1 <= piso_actual_sync_0;
solicitud_ps_sync_1 <= solicitud_ps_sync_0;
solicitud_p1_sync_1 <= solicitud_p1_sync_0;
solicitud_p2_sync_1 <= solicitud_p2_sync_0;
solicitud_p3_sync_1 <= solicitud_p3_sync_0;
solicitud_p4_sync_1 <= solicitud_p4_sync_0;
end
//Se crea el registro que almacena el contador
reg [19:0] contador=0;
//Se crean los shift registers que almacenan las 4 muestras de los estados de los botones y switches correspondientes
reg [3:0] sr_sobrePeso= 4'b0, sr_puerta= 4'b0, sr_piso_actual_0= 4'b0, sr_piso_actual_1= 4'b0, sr_piso_actual_2= 4'b0;
reg [3:0] sr_solicitud_ps_0=4'b0, sr_solicitud_ps_1=4'b0, sr_solicitud_p1_0= 4'b0, sr_solicitud_p1_1=4'b0, sr_solicitud_p2_0=4'b0;
reg [3:0] sr_solicitud_p2_1=4'b0, sr_solicitud_p3_0=4'b0, sr_solicitud_p3_1=4'b0, sr_solicitud_p4_0= 4'b0, sr_solicitud_p4_1=4'b0;
//Contador
always @(posedge _clk_)
begin
if (contador == contador_max)
contador <= 1'b0;
else
contador <= contador + 1'b1;
end
always @(posedge _clk_)
begin
if (contador==contador_max) begin
//Se hace un corrimiento a la izquierda y se almacena el estado de la entrada segun muestreo cada 10ms.
sr_sobrePeso <= (sr_sobrePeso << 1) | sensor_sobrePeso_sync_1;
sr_puerta <= (sr_puerta << 1) | sensor_puerta_sync_1;
sr_piso_actual_0 <= (sr_piso_actual_0 << 1) | piso_actual_sync_1[0];
sr_piso_actual_1 <= (sr_piso_actual_1 << 1) | piso_actual_sync_1[1];
sr_piso_actual_2 <= (sr_piso_actual_2 << 1) | piso_actual_sync_1[2];
sr_solicitud_ps_0 <= (sr_solicitud_ps_0 << 1) | solicitud_ps_sync_1[0];
sr_solicitud_ps_1 <= (sr_solicitud_ps_1 << 1) | solicitud_ps_sync_1[1];
sr_solicitud_p1_0 <= (sr_solicitud_p1_0 << 1) | solicitud_p1_sync_1[0];
sr_solicitud_p1_1 <= (sr_solicitud_p1_1 << 1) | solicitud_p1_sync_1[1];
sr_solicitud_p2_0 <= (sr_solicitud_p2_0 << 1) | solicitud_p2_sync_1[0];
sr_solicitud_p2_1 <= (sr_solicitud_p2_1 << 1) | solicitud_p2_sync_1[1];
sr_solicitud_p3_0 <= (sr_solicitud_p3_0 << 1) | solicitud_p3_sync_1[0];
sr_solicitud_p3_1 <= (sr_solicitud_p3_1 << 1) | solicitud_p3_sync_1[1];
sr_solicitud_p4_0 <= (sr_solicitud_p4_0 << 1) | solicitud_p4_sync_1[0];
sr_solicitud_p4_1 <= (sr_solicitud_p4_1 << 1) | solicitud_p4_sync_1[1];
end
//Se escribe en cada salida correspondiente un 1 si los 4 bits muestreados cada 10ns son 1111 y 0 si los 4 bits muestreados fueron 0000
case (sr_sobrePeso)
4'b0000: sensor_sobrePeso_o <= 0;
4'b1111: sensor_sobrePeso_o <= 1;
endcase
case (sr_puerta)
4'b0000: sensor_puerta_o <= 0;
4'b1111: sensor_puerta_o <= 1;
endcase
case (sr_piso_actual_0)
4'b0000: piso_actual_o[0] <= 0;
4'b1111: piso_actual_o[0] <= 1;
endcase
case (sr_piso_actual_1)
4'b0000: piso_actual_o[1] <= 0;
4'b1111: piso_actual_o[1] <= 1;
endcase
case (sr_piso_actual_2)
4'b0000: piso_actual_o[2] <= 0;
4'b1111: piso_actual_o[2] <= 1;
endcase
case (sr_solicitud_ps_0)
4'b0000: solicitud_ps_o[0] <= 0;
4'b1111: solicitud_ps_o[0] <= 1;
endcase
case (sr_solicitud_ps_1)
4'b0000: solicitud_ps_o[1] <= 0;
4'b1111: solicitud_ps_o[1] <= 1;
endcase
case (sr_solicitud_p1_0)
4'b0000: solicitud_p1_o[0] <= 0;
4'b1111: solicitud_p1_o[0] <= 1;
endcase
case (sr_solicitud_p1_1)
4'b0000: solicitud_p1_o[1] <= 0;
4'b1111: solicitud_p1_o[1] <= 1;
endcase
case (sr_solicitud_p2_0)
4'b0000: solicitud_p2_o[0] <= 0;
4'b1111: solicitud_p2_o[0] <= 1;
endcase
case (sr_solicitud_p2_1)
4'b0000: solicitud_p2_o[1] <= 0;
4'b1111: solicitud_p2_o[1] <= 1;
endcase
case (sr_solicitud_p3_0)
4'b0000: solicitud_p3_o[0] <= 0;
4'b1111: solicitud_p3_o[0] <= 1;
endcase
case (sr_solicitud_p3_1)
4'b0000: solicitud_p3_o[1] <= 0;
4'b1111: solicitud_p3_o[1] <= 1;
endcase
case (sr_solicitud_p4_0)
4'b0000: solicitud_p4_o[0] <= 0;
4'b1111: solicitud_p4_o[0] <= 1;
endcase
case (sr_solicitud_p4_1)
4'b0000: solicitud_p4_o[1] <= 0;
4'b1111: solicitud_p4_o[1] <= 1;
endcase
end
endmodule
|
Set Implicit Arguments.
Generalizable All Variables.
Require Import Arith.
Require Import Lia.
Require Import Dblib.DblibTactics.
(* ---------------------------------------------------------------------------- *)
(* Terminology. *)
(* A variable, represented as a de Bruijn index, is [k]-free if it is greater
than or equal to [k]. It is [k]-bound otherwise. This terminology is useful
when one traverses a term and [k] represents the number of binders that have
been entered. *)
(* ---------------------------------------------------------------------------- *)
(* Operations provided by the client. *)
(* We expect the client to define a type [V] of values and a type [T] of terms.
These types may coincide, but need not coincide. The client provides a number
of operations on values and terms, described below, and the library provides
lifting and substitution operations. Lifting maps values to values and terms
to terms, while substitution allows substituting values for variables within
terms. *)
(* Our use of the terminology ``value'' and ``term'' is arbitrary. It is
inspired by the operational semantics of the call-by-value lambda-calculus.
The point is that [V] -- the type of the things that are substituted for
variables -- and [T] -- the type of the things within which substitution is
performed -- need not coincide. *)
(* Since values are substituted for variables, and since we need an identity
substitution, there follows that a variable must be a value, or, more
precisely, there must exist a function that maps variables to values. *)
Class Var (V : Type) := {
var:
nat -> V
}.
(* Let us immediately define [var] at variables. This may help clarify
things, and it is used in the statement of some laws below. *)
Instance Var_idx : Var nat := {
var x := x
}.
(* [traverse] can be thought of as a semantic substitution function. The idea
is, [traverse f l t] traverses the term [t], incrementing the index [l]
whenever a binder is entered, and, at every variable [x], it invokes [f l x].
This produces a value, which is grafted instead of [x]. *)
(* The definition of [traverse] is the main task that we require of the client.
Via the manner in which [l] is incremented, this function determines the
binding structure of terms. *)
Class Traverse (V T : Type) := {
traverse:
(nat -> nat -> V) -> (nat -> T -> T)
}.
(* [traverse_var] is a specialization of [traverse] to the case where [f]
maps variables to variables. *)
Notation traverse_var f := (traverse (fun l x => var (f l x))).
(* We expect the client to establish the following properties of [traverse]. *)
(* If [f] is injective, then [traverse_var f] is injective. *)
(* This reflects the fact that [traverse] preserves the structure of the term.
It acts only on variables. *)
Class TraverseVarInjective `{Var V, Traverse V T} := {
traverse_var_injective:
forall f,
(forall x1 x2 l, f l x1 = f l x2 -> x1 = x2) ->
forall t1 t2 l,
traverse_var f l t1 = traverse_var f l t2 ->
t1 = t2
}.
(* Two successive traversals can be fused. *)
(* This law is analogous to the law that describes the composition of two
syntactic substitutions -- see [SubstSubst] below. *)
Class TraverseFunctorial `{Traverse V V, Traverse V T} := {
traverse_functorial:
forall f g t l,
traverse g l (traverse f l t) = traverse (fun l x => traverse g l (f l x)) l t
}.
(* [traverse] is position-independent. That is, adding [p] to the argument
of [traverse] leads to adding [p] to the argument of every call to [f].
Furthermore, [traverse] is compatible with extensional equality. *)
Class TraverseRelative `{Traverse V T} := {
traverse_relative:
forall f g p t m l,
(forall l x, f (l + p) x = g l x) ->
m = l + p ->
traverse f m t =
traverse g l t
}.
(* [traverse] identifies [var] and simplifies to a call to [f]. *)
Class TraverseIdentifiesVar `{Var V, Traverse V V} := {
traverse_identifies_var:
forall f l x,
traverse f l (var x) = f l x
}.
(* The application of [traverse_var] to the identity is the identity. *)
Class TraverseVarIsIdentity `{Var V, Traverse V T} := {
traverse_var_is_identity:
forall f,
(forall l x, f l x = var x) ->
forall t l,
traverse f l t = t
}.
(* ---------------------------------------------------------------------------- *)
(* Operations provided by the library. *)
(* [lift w k t] is the term obtained by adding [w] to the [k]-free variables
of the term [t]. *)
Class Lift (T : Type) := {
lift:
nat -> nat -> T -> T
}.
(* Let us immediately define [lift] at variables. This may help clarify
things, and it is used in the statement of some laws below. *)
Instance Lift_idx : Lift nat := {
lift w k x :=
if le_gt_dec k x then w + x else x
}.
(* [shift k t] is an abbreviation for [lift 1 k t]. *)
(* From a programming language point of view, [shift] can be understood
as an end-of-scope construct. That is, if we are working in a context
where the variable [k] exists, then writing [shift k .] allows us to
go back to a context where this variable does not exist any more. In
this context, we can place a term [t] that makes sense in the absence
of this variable. Thus, [shift k t] can be read intuitively as [end k
in t], that is, end the scope of the variable [k] before interpreting
the term [t]. *)
Notation shift :=
(lift 1).
(* [subst v k t] is the term obtained by substituting the value [v] for
the variable [k] in the term [t]. *)
(* From a programming language point of view, [subst] can be understood as
a [let] construct. That is, [subst v k t] is in a certain sense equivalent
to [let k = v in t]. It is a binding construct for the variable [k], in the
sense that if [subst v k t] is used in a context where [k] does not exist,
then inside the sub-term [t], the variable [k] exists. *)
Class Subst (V T : Type) := {
subst:
V -> nat -> T -> T
}.
(* Let us immediately define [subst] at variables. This may help clarify
things, and it is used in the statement of some laws below. This definition
does not constitute an instance of the class [Subst] because we need a
heterogeneous version of substitution, one that maps variables to values,
as a basic building block. A homogeneous instance definition follows. *)
(* Note that [subst_idx] depends on [var]. *)
Definition subst_idx `{Var V} (v : V) (k x : nat) : V :=
match lt_eq_lt_dec x k with
| inleft (left _) => var x
| inleft (right _) => v
| inright _ => var (x - 1)
end.
Instance Subst_idx : Subst nat nat := {
subst := subst_idx
}.
(* The predicate [closed k t] means that the term [t] is [k]-closed, that is,
it has no [k]-free variables. In particular, if [k] is 0, then [t] is closed. *)
(* We defined [closed] in terms of [lift]: a term is closed if and only if it
is invariant under shifting (lifting by one). We show that this implies
that it is also invariant under arbitrary lifting and under substitution.
It is important to use a quantifier-free definition of closedness, as this
makes it much easier to write tactics that construct and destruct closedness
assertions. *)
Definition closed `{Lift T} k t :=
shift k t = t.
(* [rotate n] maps the variable [0] to the variable [n], maps [n] to [n-1], ...,
[1] to [0]. It preserves every variable above [n]. In particular, [rotate 1]
exchanges the variables [0] and [1]. *)
Definition rotate `{Var V, Lift T, Subst V T} (n : nat) (t : T) : T :=
subst (var n) 0 (shift (S n) t).
(* ---------------------------------------------------------------------------- *)
(* Properties of these operations. *)
(* [lift] commutes with [var]. *)
(* This law alone is probably not of great interest to the client, who needs a
more general way of simplifying the application of [lift] to a constructor.
We name this property because it is used by some of our lemmas. *)
Class LiftVar `{Var A, Lift A} := {
lift_var:
forall w k x,
lift w k (var x) = var (lift w k x)
}.
(* [lift 0] is the identity. *)
Class LiftZero `{Lift T} := {
lift_zero:
forall k t,
lift 0 k t = t
}.
(* [lift] is injective. *)
Class LiftInjective `{Lift T} := {
lift_injective:
forall w k t1 t2,
lift w k t1 = lift w k t2 ->
t1 = t2
}.
Ltac lift_injective :=
match goal with h: lift ?w ?k ?t1 = lift ?w ?k ?t2 |- _ =>
generalize (lift_injective _ _ _ _ h); clear h; intro h; try (subst t1)
end.
(* [lift] commutes with itself. *)
(* In the special case where [wk] and [ws] are 1, the law becomes:
[k <= s -> shift k (shift s t) = shift (1 + s) (shift k t)].
Since [k] is the smaller index, it is always called [k], regardless
of whether [s] is or is not in scope. Conversely, since [s] is the
larger index, it is called [s] when [k] is not in scope, but it is
called [1 + s] when [k] is in scope. The law expresses the fact
that ending the scope of [k] first, then the scope of [s], is the
same as ending the scope of [1 + s], then the scope of [k]. It is
a commutation law with a slight technical adjustment. *)
(* Roughly speaking, [end k in end s in t] is equivalent to [end s in
end k in t]. *)
Class LiftLift `{Lift T} := {
lift_lift:
forall t k s wk ws,
k <= s ->
lift wk k (lift ws s t) = lift ws (wk + s) (lift wk k t)
}.
(* One might wonder whether it is sufficient for this law to consider
the case where [k <= s] holds. What happens in the other cases?
Well, one can check that if [k >= s + ws] holds, then the law
applies in the other direction. The following lemma proves this. *)
Lemma lift_lift_reversed:
forall `{Lift T},
LiftLift ->
forall wk k ws s t,
k >= s + ws ->
lift wk k (lift ws s t) = lift ws s (lift wk (k - ws) t).
Proof.
intros.
replace k with (ws + (k - ws)) by lia.
erewrite <- lift_lift by lia.
replace (ws + (k - ws) - ws) with (k - ws) by lia.
reflexivity.
Qed.
(* If [ws] is 1, then the two cases considered above, namely [k <= s]
and [k >= s + ws], are exhaustive. Now, what happens when [k] is
comprised between [s] and [s + ws]? The following law answers this
question. This law also covers the extreme cases where [k = s] and
[k = s + ws], which may seem surprising, since they are already
covered by [lift_lift]. The law below states that, in this case,
the two [lift] operations can be combined into a single one. Note
that the exact value of [k] is irrelevant as long as it lies within
this interval. *)
Class LiftLiftFuse `{Lift T} := {
lift_lift_fuse:
forall t k s wk ws,
s <= k <= s + ws ->
lift wk k (lift ws s t) = lift (wk + ws) s t
}.
(* [subst] identifies [var] and simplifies to [subst_idx]. *)
(* This law alone is probably not of great interest to the client, who needs a
more general way of simplifying the application of [subst] to a constructor.
We name this property because it is used by some of our lemmas. *)
Class SubstVar `{Var A, Subst A A} := {
subst_var:
forall a k x,
subst a k (var x) = subst_idx a k x
}.
(* A substitution for the variable [k] vanishes when it reaches an
end-of-scope marker for the variable [k]. This is expressed by
the following law. *)
Class SubstLift `{Lift T, Subst V T} := {
subst_lift:
forall v k t,
subst v k (shift k t) =
t
}.
(* [lift] and [subst] commute. *)
(* Roughly speaking, [end k in let s = v in t] is equivalent to [let s = (end
k in v) in (end k in t)]. At least, that is the idea. The ``technical
adjustments'' make it quite difficult to understand what is going on in
detail. *)
(* Below, we propose two laws, which cover the cases [k <= s] and [s <= k]. It
may seem somewhat troubling that these cases are not disjoint! When [k = s],
the two right-hand sides differ in a certain manner that is described by the
law [PunPun] shown further on. *)
(* We also offer a general law, which unifies these two laws, and arbitrarily
gives preference to the second law in the case where [k = s]. It is not
clear whether this complex general law is of any use in practice. *)
Class LiftSubst1 `{Lift V, Lift T, Subst V T} := {
lift_subst_1:
forall t k v s w,
k <= s ->
lift w k (subst v s t) =
subst (lift w k v) (w + s) (lift w k t)
}.
Class LiftSubst2 `{Lift V, Lift T, Subst V T} := {
lift_subst_2:
forall t k v s w,
s <= k ->
lift w k (subst v s t) =
subst (lift w k v) s (lift w (1 + k) t)
}.
Class LiftSubst `{Lift V, Lift T, Subst V T} := {
lift_subst:
forall t k v s w,
lift w k (subst v s t) =
subst (lift w k v) (lift w (1 + k) s) (lift w (shift s k) t)
}.
(* [subst] commutes with itself. *)
(* Roughly speaking, [let s = v in let k = w in t] is equivalent to
[let k = (let s = v in w) in let s = v in t], again with ``technical
adjustments''. *)
(* This law covers only the case where [k <= s]. I am not sure what can
be said about the other case. Of course the law can be read from right
to left, and this says something about the case where [k >= 1 + s], but
only if the values [v] and [w] are of a specific form. Maybe there is
nothing more to be said. *)
Class SubstSubst `{Lift V, Subst V V, Subst V T} := {
subst_subst:
forall t k v s w,
k <= s ->
subst v s (subst w k t) =
subst (subst v s w) k (subst (shift k v) (1 + s) t)
}.
(* Substituting [x] for [x] is the identity. This is known as a pun. *)
(* In a de Bruijn setting, it does not even make sense to speak of replacing
a variable with itself, because in the term [subst v k t], the value [v]
and the variable [k] inhabit different spaces. *)
(* Instead, we can write [let S k = k in end k in t]. This introduces [S k] as
an alias for [k], then forgets about [k], so [S k] is renumbered and becomes
[k] again. Or we can write [let k = k in end S k in t]. This introduces [k]
as an alias for the old [k], which gets renumbered and becomes [S k], then
forgets about [S k]. In each of these two cases, we introduce a new variable
and forget about the old one; the apparent difference lies in how we number
the new variable, but this makes no deep difference. We give the variants
of the law for puns, plus a law that helps recognize these two variants as
equal. *)
Class Pun1 `{Var V, Lift T, Subst V T} := {
pun_1:
forall t k,
subst (var k) (S k) (shift k t) = t
}.
Class Pun2 `{Var V, Lift T, Subst V T} := {
pun_2:
forall t k,
subst (var k) k (shift (S k) t) = t
}.
Class PunPun `{Var V, Lift T, Subst V T} := {
pun_pun:
forall v w k t,
subst v (w + k) (lift w k t) =
subst v k (lift w (1 + k) t)
}.
(* [rotate 1] exchanges the variables [0] and [1], so it is own inverse. *)
Class Rotate1SelfInverse `{Var V, Lift T, Subst V T} := {
rotate1_self_inverse:
forall t,
rotate 1 (rotate 1 t) = t
}.
(* ---------------------------------------------------------------------------- *)
(* ---------------------------------------------------------------------------- *)
(* A few consequences of the properties that the user proves about [traverse]. *)
(* We could present these properties in the form of classes, as opposed to lemmas.
This would be perhaps slightly more convenient but also more confusing. It is
seems preferable to work directly with the basic classes that the user knows
about. *)
(* [traverse] is compatible with extensional equality. *)
Lemma traverse_extensional:
forall `{Traverse V T},
TraverseRelative ->
forall f g,
(forall l x, f l x = g l x) ->
forall t l,
traverse f l t = traverse g l t.
Proof.
intros.
eapply traverse_relative with (p := 0).
intros m ?. replace (m + 0) with m by lia. eauto.
lia.
Qed.
(* A composition of [traverse] with [traverse_var] simplifies to a single call
to [traverse]. In other words, composing a substitution and a (not
necessarily bijective) renaming yields another substitution. *)
Lemma traverse_traverse_var:
forall `{Var V, Traverse V V, Traverse V T},
@TraverseFunctorial V _ T _ ->
@TraverseRelative V T _ -> (* TraverseExtensional *)
@TraverseIdentifiesVar V _ _ ->
forall f g t l,
traverse g l (traverse_var f l t) =
traverse (fun l x => g l (f l x)) l t.
Proof.
intros.
rewrite traverse_functorial.
eapply (traverse_extensional _).
eauto using traverse_identifies_var.
Qed.
(* ---------------------------------------------------------------------------- *)
(* This internal tactic helps prove goals by examination of all cases. *)
Ltac just_do_it :=
unfold subst, Subst_idx, subst_idx, lift, Lift_idx, var, Var_idx;
intros;
dblib_by_cases; eauto with lia.
(* The following two lemmas re-state the definition of [lift] at type [nat]. *)
Lemma lift_idx_recent:
forall w k x,
k > x ->
lift w k x = x.
Proof.
just_do_it.
Qed.
Lemma lift_idx_old:
forall w k x,
k <= x ->
lift w k x = w + x.
Proof.
just_do_it.
Qed.
(* This tactic applies whichever of the above two lemmas is applicable. *)
Create HintDb lift_idx_hints.
(* more hints to be added later on into this database *)
Ltac lift_idx :=
first [ rewrite @lift_idx_recent by solve [ lia | eauto with lift_idx_hints ]
| rewrite @lift_idx_old by lia ].
Hint Extern 1 => lift_idx : lift_idx.
Ltac lift_idx_in h :=
first [ rewrite @lift_idx_recent in h by solve [ lia | eauto with lift_idx_hints ]
| rewrite @lift_idx_old in h by lia ].
Ltac lift_idx_all :=
first [ rewrite @lift_idx_recent in * by solve [ lia | eauto with lift_idx_hints ]
| rewrite @lift_idx_old in * by lia ].
(* This tactic finds an occurrence of [lift _ _ _] at type [nat] and
examines both cases. *)
Ltac destruct_lift_idx :=
match goal with |- context[@lift nat _ _ ?y ?x] =>
destruct (le_gt_dec y x); lift_idx
end.
(* Our definition of [lift] at type [nat] satisfies the properties listed above. *)
Instance LiftVar_idx: @LiftVar nat _ _.
Proof. constructor. just_do_it. Qed.
Instance LiftZero_idx: @LiftZero nat _.
Proof. constructor. just_do_it. Qed.
Instance LiftInjective_idx: @LiftInjective nat _.
Proof. constructor. just_do_it. Qed.
Instance LiftLift_idx: @LiftLift nat _.
Proof. constructor. just_do_it. Qed.
Instance LiftLiftFuse_idx: @LiftLiftFuse nat _.
Proof. constructor. just_do_it. Qed.
(* We could also state and prove that our definition of [subst] at type [nat]
satisfies the properties listed above. However, this would not be very
interesting, because we need more general statements about [subst_idx],
which is heterogeneous: the type [V] is not [nat]. We are able to get away
without making these more general statements explicit: they appear inside
some proofs and we prove them on the fly. *)
(* The following three lemmas re-state the definition of [subst_idx]. *)
Lemma subst_idx_miss_1:
forall `{Var V} v k x,
k > x ->
subst_idx v k x = var x.
Proof.
just_do_it.
Qed.
Lemma subst_idx_identity:
forall `{Var V} v k x,
k = x ->
subst_idx v k x = v.
Proof.
just_do_it.
Qed.
Lemma subst_idx_miss_2:
forall `{Var V} v k x,
k < x ->
subst_idx v k x = var (x - 1).
Proof.
just_do_it.
Qed.
(* This tactic applies whichever of the above three lemmas is applicable. *)
Ltac subst_idx :=
first [
rewrite @subst_idx_identity by lia
| rewrite @subst_idx_miss_1 by lia
| rewrite @subst_idx_miss_2 by lia
].
Ltac subst_idx_in h :=
first [
rewrite @subst_idx_identity in h by lia
| rewrite @subst_idx_miss_1 in h by lia
| rewrite @subst_idx_miss_2 in h by lia
].
Ltac subst_idx_all :=
first [
rewrite @subst_idx_identity in * by lia
| rewrite @subst_idx_miss_1 in * by lia
| rewrite @subst_idx_miss_2 in * by lia
].
(* A little lemma: replacing a variable with a variable always yields a
variable. *)
Lemma subst_idx_var:
forall `{Var V},
forall v k x,
subst_idx (var v) k x =
var (subst_idx v k x).
Proof.
just_do_it.
Qed.
(* ---------------------------------------------------------------------------- *)
(* This is our generic definition of [lift] in terms of [traverse]. *)
Instance Lift_Traverse `{Var V, Traverse V T} : Lift T := {
lift w k t :=
traverse (fun l x => var (lift w (l + k) x)) 0 t
}.
(* This lemma repeats the definition (!) and is useful when rewriting. *)
Lemma expand_lift:
forall `{Var V, Traverse V T},
forall w k t,
lift w k t =
traverse (fun l x => var (lift w (l + k) x)) 0 t.
Proof.
reflexivity.
Qed.
(* This auxiliary tactic simplifies expressions of the form [x + 0] in
the goal. It does *not* affect [x + ?y] where [y] is a
meta-variable. *)
Ltac plus_0_r :=
repeat match goal with |- context[?x + 0] => rewrite (plus_0_r x) end.
Ltac plus_0_r_in h :=
repeat match type of h with context[?x + 0] => rewrite (plus_0_r x) in h end.
(* It is worth noting that instead of writing:
traverse (fun l x => var (lift w (l + k) x)) 0 t
one might have instead written:
traverse (fun l x => var (lift w l x)) k t
Indeed, because [traverse] is relative, these two expressions are
equivalent. The following lemma states this fact. When used as a
rewriting rule, it recognizes a general form of the above expressions
and replaces it with an application of [lift]. *)
Lemma recognize_lift:
forall `{Var V, Traverse V T},
TraverseRelative ->
forall w k1 k2 t,
forall traverse_,
traverse_ = traverse -> (* helps rewrite *)
traverse_ (fun l x => var (lift w (l + k2) x)) k1 t =
lift w (k1 + k2) t.
Proof.
intros. subst. simpl.
eapply traverse_relative; [ | instantiate (1 := k1); lia ].
just_do_it.
Qed.
(* This tactic recognizes an application of the user's [traverse_term]
function that is really a [lift] operation, and folds it. *)
Ltac recognize_lift :=
rewrite recognize_lift by eauto with typeclass_instances;
repeat rewrite plus_0_l. (* useful when [k1] is zero *)
Ltac recognize_lift_in h :=
rewrite recognize_lift in h by eauto with typeclass_instances;
repeat rewrite plus_0_l in h. (* useful when [k1] is zero *)
(* The tactic [simpl_lift] is used to simplify an application of [lift] to a
concrete term, such as [TApp t ...], where [TApp] is a user-defined
constructor of the user-defined type of [term]s. We assume that the user
has manually rewritten one or several occurrences of [lift] using the lemma
[expand_lift], so as to indicate where simplification is desired. Thus, one
or several instances of [traverse] must be visible in a hypothesis or in the
goal. We further assume that [simpl (@traverse _ _ _)] has been used so as to
replace the generic [traverse] with user-defined [_traverse] functions. We
start there and do the rest of the work. *)
(* A difficulty arises when the goal or hypothesis contains instances of
[lift] at multiple types. In that case, after expanding [traverse], we find
multiple user-defined [_traverse] functions, each of which we must deal
with in turn. After dealing with one specific [_traverse] function, we use
[recognize_lift] at a specific type in order to eliminate all occurrences
of this particular [_traverse] function. We are then able to iterate this
process without looping. *)
Ltac simpl_lift :=
match goal with
(* Case: [_traverse] appears in the goal. *)
(* this binds the meta-variable [_traverse] to the user's [traverse_term] *)
|- context[?_traverse (fun l x : nat => var (lift ?w (l + ?k) x)) _ _] =>
(* this causes the reduction of the fixpoint: *)
unfold _traverse; fold _traverse;
(* we now have a term of the form [TApp (traverse_term ...) ...].
There remains to recognize the definition of [lift]. *)
plus_0_r; (* useful when we have traversed a binder: 1 + 0 is 1 *)
(* use [recognize_lift] at the specific type of the [_traverse] function
that we have just simplified *)
match type of _traverse with (nat -> nat -> ?V) -> nat -> ?T -> ?T =>
repeat rewrite (@recognize_lift V _ T _ _) by eauto with typeclass_instances
end;
repeat rewrite plus_0_l (* useful when [k1] is zero and we are at a leaf *)
(* Case: [_traverse] appears in a hypothesis. *)
(* this binds the meta-variable [_traverse] to the user's [traverse_term] *)
| h: context[?_traverse (fun l x : nat => var (lift ?w (l + ?k) x)) _ _] |- _ =>
(* this causes the reduction of the fixpoint: *)
unfold _traverse in h; fold _traverse in h;
(* we now have a term of the form [TApp (traverse_term ...) ...].
There remains to recognize the definition of [lift]. *)
plus_0_r_in h; (* useful when we have traversed a binder: 1 + 0 is 1 *)
(* use [recognize_lift] at the specific type of the [_traverse] function
that we have just simplified *)
match type of _traverse with (nat -> nat -> ?V) -> nat -> ?T -> ?T =>
repeat rewrite (@recognize_lift V _ T _ _) in h by eauto with typeclass_instances
end;
repeat rewrite plus_0_l in h (* useful when [k1] is zero and we are at a leaf *)
end.
(* This tactic attempts to all occurrences of [lift] in the goal. *)
Ltac simpl_lift_goal :=
(* this replaces [lift] with applications of [traverse] *)
repeat rewrite @expand_lift;
(* this replaces the generic [traverse] with the user's [_traverse] functions *)
simpl (@traverse _ _ _);
(* this simplifies applications of each [_traverse] function and folds them back *)
repeat simpl_lift;
(* if we have exposed applications of [lift_idx], try simplifying them away *)
repeat lift_idx;
(* if this exposes uses of [var], replace them with the user's [TVar] constructor *)
simpl var.
Hint Extern 1 (lift _ _ _ = _) => simpl_lift_goal : simpl_lift_goal.
Hint Extern 1 (_ = lift _ _ _) => simpl_lift_goal : simpl_lift_goal.
(* This tactic attempts to simplify all occurrences of [lift] in the goal
and the hypotheses. *)
Ltac simpl_lift_all :=
repeat rewrite @expand_lift in *;
simpl (@traverse _ _ _) in *;
repeat simpl_lift;
repeat lift_idx_all;
simpl var in *.
(* This tactic attempts to simplify all occurrences of [lift] in a specific
hypothesis. *)
Ltac simpl_lift_in h :=
repeat rewrite @expand_lift in h;
simpl (@traverse _ _ _) in h;
repeat simpl_lift;
repeat lift_idx_in h;
simpl var in h.
(* ---------------------------------------------------------------------------- *)
(* Our definition of [lift] in terms of [traverse] satisfies all of the desired
properties. *)
Instance LiftVar_Traverse:
forall `{Var V, Traverse V V},
TraverseIdentifiesVar ->
@LiftVar V _ _.
Proof.
constructor. unfold lift, Lift_Traverse. intros.
rewrite traverse_identifies_var. reflexivity.
Qed.
Instance LiftZero_Traverse:
forall `{Var V, Traverse V V},
TraverseVarIsIdentity ->
@LiftZero V _.
Proof.
constructor. intros.
unfold lift, Lift_Traverse.
rewrite traverse_var_is_identity. reflexivity. intros.
rewrite lift_zero. reflexivity.
Qed.
Instance LiftInjective_Traverse:
forall `{Var V, Traverse V T},
TraverseVarInjective ->
@LiftInjective T _.
Proof.
constructor. unfold lift, Lift_Traverse. intros w k. intros.
eapply traverse_var_injective with (f := fun l x => lift w (l + k) x).
eauto using lift_injective.
eassumption.
Qed.
Instance LiftLift_Traverse:
forall `{Var V, Traverse V V, Traverse V T},
@TraverseFunctorial V _ T _ ->
@TraverseRelative V T _ -> (* TraverseExtensional *)
@TraverseIdentifiesVar V _ _ ->
@LiftLift T _.
Proof.
constructor. unfold lift, Lift_Traverse. intros.
rewrite (traverse_traverse_var _ _ _).
rewrite (traverse_traverse_var _ _ _).
eapply (traverse_extensional _).
intros. f_equal.
rewrite lift_lift by lia.
f_equal. lia.
Qed.
Instance LiftLiftFuse_Traverse:
forall `{Var V, Traverse V V, Traverse V T},
@TraverseFunctorial V _ T _ ->
@TraverseRelative V T _ -> (* TraverseExtensional *)
@TraverseIdentifiesVar V _ _ ->
@LiftLiftFuse T _.
Proof.
constructor. unfold lift, Lift_Traverse. intros.
rewrite (traverse_traverse_var _ _ _).
eapply (traverse_extensional _).
intros. f_equal.
rewrite lift_lift_fuse by lia. reflexivity.
Qed.
(* ---------------------------------------------------------------------------- *)
(* This is our generic definition of [subst] in terms of [traverse]. *)
Instance Subst_Traverse `{Var V, Traverse V V, Traverse V T} : Subst V T := {
subst v k t :=
traverse (fun l x => subst_idx (lift l 0 v) (l + k) x) 0 t
}.
(* This lemma repeats the definition (!) and is useful when rewriting. *)
Lemma expand_subst:
forall `{Var V, Traverse V V, Traverse V T},
forall v k t,
subst v k t =
traverse (fun l x => subst_idx (lift l 0 v) (l + k) x) 0 t.
Proof.
reflexivity.
Qed.
(* Again, because [traverse] is relative, there can be several ways of
writing a substitution. The following lemma states this. When used
as a rewriting rule, it helps recognize applications of [subst]. *)
Lemma recognize_subst:
forall `{Var V, Traverse V V, Traverse V T},
@TraverseFunctorial V _ V _ ->
@TraverseIdentifiesVar V _ _ ->
@TraverseRelative V V _ ->
@TraverseRelative V T _ ->
forall traverse_,
traverse_ = traverse -> (* helps rewrite *)
forall v k2 k1 t,
traverse_ (fun l x => subst_idx (lift l 0 v) (l + k2) x) k1 t =
subst (lift k1 0 v) (k1 + k2) t.
Proof.
intros. subst.
unfold subst, Subst_Traverse.
eapply traverse_relative; [ | instantiate (1 := k1); lia ].
intros.
f_equal.
rewrite lift_lift_fuse by lia. reflexivity.
lia.
Qed.
(* This tactic recognizes an application of the user's [traverse_term]
function that is really a [subst] operation, and folds it. *)
Ltac recognize_subst :=
rewrite recognize_subst by eauto with typeclass_instances;
try rewrite lift_zero; (* useful when [k1] is zero *)
repeat rewrite plus_0_l. (* useful when [k1] is zero *)
Ltac recognize_subst_in h :=
rewrite recognize_subst in h by eauto with typeclass_instances;
try rewrite lift_zero in h; (* useful when [k1] is zero *)
repeat rewrite plus_0_l in h. (* useful when [k1] is zero *)
(* This tactic is used to simplify an application of [subst] to a concrete
term, such as [TApp t1 t2], where [TApp] is a user-defined constructor of
the user-defined type of [term]s. We assume that the user has manually
rewritten one occurrence of [subst] using the lemma [expand_subst], so as to
indicate where simplification is desired. Thus, one instance of [traverse]
must be visible in a hypothesis or in the goal. We start there and do the
rest of the work. *)
Ltac simpl_subst :=
match goal with
(* Case: [_traverse] appears in the goal. *)
(* this binds the meta-variable [_traverse] to the user's [traverse_term] *)
|- context[?_traverse (fun l x : nat => subst_idx (lift l 0 ?v) (l + ?k) x) _ _] =>
(* this causes the reduction of the fixpoint: *)
unfold _traverse; fold _traverse;
(* we now have a term of the form [TApp (traverse_term ...) (traverse_term ...)].
There remains to recognize the definition of [subst]. *)
plus_0_r; (* useful when we have traversed a binder: 1 + 0 is 1 *)
(* use [recognize_subst] at the specific type of the [_traverse] function
that we have just simplified *)
match type of _traverse with (nat -> nat -> ?V) -> nat -> ?T -> ?T =>
repeat rewrite (@recognize_subst V _ _ T _ _ _ _ _) by eauto with typeclass_instances
end;
repeat rewrite plus_0_l; (* useful when [k1] is zero and we are at a leaf *)
repeat rewrite lift_zero (* useful when [k1] is zero and we are at a leaf *)
(* Case: [_traverse] appears in a hypothesis. *)
(* this binds the meta-variable [_traverse] to the user's [traverse_term] *)
| h: context[?_traverse (fun l x : nat => subst_idx (lift l 0 ?v) (l + ?k) x) _ _] |- _ =>
(* this causes the reduction of the fixpoint: *)
unfold _traverse in h; fold _traverse in h;
(* we now have a term of the form [TApp (traverse_term ...) (traverse_term ...)].
There remains to recognize the definition of [subst]. *)
plus_0_r_in h; (* useful when we have traversed a binder: 1 + 0 is 1 *)
(* use [recognize_subst] at the specific type of the [_traverse] function
that we have just simplified *)
match type of _traverse with (nat -> nat -> ?V) -> nat -> ?T -> ?T =>
repeat rewrite (@recognize_subst V _ _ T _ _ _ _ _) in h by eauto with typeclass_instances
end;
repeat rewrite plus_0_l in h; (* useful when [k1] is zero and we are at a leaf *)
repeat rewrite lift_zero in h (* useful when [k1] is zero and we are at a leaf *)
end.
(* This tactic attempts to simplify all occurrences of [subst] in the goal. *)
Ltac simpl_subst_goal :=
(* this replaces [subst] with applications of [traverse] *)
repeat rewrite @expand_subst;
(* this replaces the generic [traverse] with the user's [_traverse] functions *)
simpl (@traverse _ _ _);
(* this simplifies applications of each [_traverse] function and folds them back *)
repeat simpl_subst;
(* if we have exposed applications of [subst_idx], try simplifying them away *)
repeat subst_idx;
(* if this exposes uses of [var], replace them with the user's [TVar] constructor *)
simpl var.
Hint Extern 1 (subst _ _ _ = _) => simpl_subst_goal : simpl_subst_goal.
Hint Extern 1 (_ = subst _ _ _) => simpl_subst_goal : simpl_subst_goal.
(* This tactic attempts to simplify all occurrences of [subst] in the goal
and the hypotheses. *)
Ltac simpl_subst_all :=
repeat rewrite @expand_subst in *;
simpl (@traverse _ _ _) in *;
repeat simpl_subst;
repeat subst_idx_all;
simpl var in *.
(* This tactic attempts to simplify all occurrences of [subst] in a specific
hypothesis. *)
Ltac simpl_subst_in h :=
repeat rewrite @expand_subst in h;
simpl (@traverse _ _ _) in h;
repeat simpl_subst;
repeat subst_idx_in h;
simpl var in h.
(* ---------------------------------------------------------------------------- *)
(* Our definition of [subst] in terms of [traverse] satisfies all of the desired
properties. *)
Instance SubstVar_Traverse:
forall `{Var V, Traverse V V},
TraverseIdentifiesVar ->
TraverseVarIsIdentity ->
SubstVar.
Proof.
constructor. unfold subst, Subst_Traverse. intros.
rewrite traverse_identifies_var.
rewrite lift_zero.
reflexivity.
Qed.
Instance SubstLift_Traverse:
forall `{Var V, Traverse V V, Traverse V T},
@TraverseFunctorial V _ T _ ->
@TraverseIdentifiesVar V _ _ ->
@TraverseVarIsIdentity V _ T _ ->
@SubstLift T _ V _.
Proof.
constructor. intros.
(* First, argue that everything boils down to examining what happens
at variables. *)
unfold lift, Lift_Traverse.
unfold subst, Subst_Traverse.
rewrite traverse_functorial.
eapply traverse_var_is_identity. intros.
rewrite traverse_identifies_var.
(* At the leaves, there remains a basic lemma, which we prove on the fly. *)
just_do_it.
Qed.
Instance LiftSubst1_Traverse:
forall `{Var V, Traverse V V, Traverse V T},
@TraverseRelative V V _ ->
@TraverseRelative V T _ -> (* TraverseExtensional *)
@TraverseFunctorial V _ V _ ->
@TraverseFunctorial V _ T _ ->
@TraverseIdentifiesVar V _ _ ->
@LiftSubst1 V _ T _ _.
Proof.
constructor. intros.
(* First, argue that everything boils down to examining what happens
at variables. *)
unfold lift at 1 3. unfold Lift_Traverse.
unfold subst, Subst_Traverse.
do 2 rewrite traverse_functorial.
eapply (traverse_extensional _). intros.
rewrite traverse_identifies_var.
recognize_lift.
(* This is what must be proven at variables. Tidy it up slightly. *)
rewrite lift_lift by lia.
replace (l + (w + s)) with (w + (l + s)) by lia. (* optional *)
(* We now recognize a heterogeneous version of [LiftSubst1] at types
[nat] and [V]. We could make it a separate lemma, but brute force
is more concise. *)
replace (lift w (l + k) x)
with ((let (lift0) := Lift_idx in lift0) w (l + k) x)
by (unfold lift; reflexivity).
unfold Lift_idx.
unfold subst_idx. dblib_by_cases; try rewrite lift_var; just_do_it.
Qed.
Instance LiftSubst2_Traverse:
forall `{Var V, Traverse V V, Traverse V T},
@TraverseRelative V V _ ->
@TraverseRelative V T _ -> (* TraverseExtensional *)
@TraverseFunctorial V _ V _ ->
@TraverseFunctorial V _ T _ ->
@TraverseIdentifiesVar V _ _ ->
@LiftSubst2 V _ T _ _.
Proof.
constructor. intros.
(* First, argue that everything boils down to examining what happens
at variables. *)
unfold lift at 1 3. unfold Lift_Traverse.
unfold subst, Subst_Traverse.
do 2 rewrite traverse_functorial.
eapply (traverse_extensional _). intros.
rewrite traverse_identifies_var.
recognize_lift.
(* This is what must be proven at variables. Tidy it up slightly. *)
rewrite lift_lift by lia.
replace (l + (1 + k)) with (1 + (l + k)) by lia. (* optional *)
(* We now recognize a heterogeneous version of [LiftSubst2] at types
[nat] and [V]. We could make it a separate lemma, but brute force
is more concise. *)
replace (lift w (1 + (l + k)) x)
with ((let (lift0) := Lift_idx in lift0) w (1 + (l + k)) x)
by (unfold lift; reflexivity).
unfold Lift_idx.
unfold subst_idx. dblib_by_cases; try rewrite lift_var; just_do_it.
Qed.
(* [LiftSubst1] and [LiftSubst2] imply [LiftSubst]. No surprise, since the
latter law is just a combination of the former two. *)
Instance LiftSubst_LiftSubst12 `{Lift V, Lift T, Subst V T} :
LiftSubst1 ->
LiftSubst2 ->
LiftSubst.
Proof.
constructor. intros.
destruct (le_gt_dec s k); do 2 lift_idx.
(* Case [s <= k]. *)
eapply lift_subst_2. lia.
(* Case [s > k]. *)
eapply lift_subst_1. lia.
Qed.
Instance SubstSubst_Traverse:
forall `{Var V, Traverse V V, Traverse V T},
@TraverseRelative V V _ ->
@TraverseRelative V T _ -> (* TraverseExtensional *)
@TraverseIdentifiesVar V _ _ ->
@TraverseVarIsIdentity V _ V _ ->
@TraverseFunctorial V _ V _ ->
@TraverseFunctorial V _ T _ ->
@SubstSubst V _ _ T _.
Proof.
constructor. intros.
(* First, argue that everything boils down to examining what happens
at variables. *)
unfold subst at 1 2 3 5. unfold Subst_Traverse.
do 2 rewrite traverse_functorial.
eapply (traverse_extensional _). intros.
do 2 recognize_subst.
(* This is what must be proven at variables. Tidy it up slightly. *)
rewrite lift_subst_1 by lia.
(* We now recognize a heterogeneous version of [SubstSubst] at types
[nat] and [V]. We could make it a separate lemma, but brute force
is more concise. *)
unfold subst_idx; dblib_by_cases; repeat rewrite subst_var; try solve [ just_do_it ].
(* The special case [x = l + s + 1] remains. *)
subst_idx. rewrite lift_lift by lia. rewrite subst_lift. reflexivity. (* Phew! *)
Qed.
Instance Pun1_Traverse:
forall `{Var V, Traverse V V, Traverse V T},
@TraverseFunctorial V _ T _ ->
@TraverseVarIsIdentity V _ T _ ->
@TraverseIdentifiesVar V _ _ ->
@Pun1 V _ T _ _.
Proof.
constructor. intros.
unfold lift, Lift_Traverse.
unfold subst, Subst_Traverse.
rewrite traverse_functorial.
rewrite traverse_var_is_identity. reflexivity. intros.
rewrite traverse_identifies_var.
rewrite lift_var.
just_do_it.
Qed.
Instance Pun2_Traverse:
forall `{Var V, Traverse V V, Traverse V T},
@TraverseFunctorial V _ T _ ->
@TraverseVarIsIdentity V _ T _ ->
@TraverseIdentifiesVar V _ _ ->
@Pun2 V _ T _ _.
Proof.
constructor. intros.
unfold lift, Lift_Traverse.
unfold subst, Subst_Traverse.
rewrite traverse_functorial.
rewrite traverse_var_is_identity. reflexivity. intros.
rewrite traverse_identifies_var.
rewrite lift_var.
just_do_it.
Qed.
Instance PunPun_Traverse:
forall `{Var V, Traverse V V, Traverse V T},
@TraverseRelative V T _ -> (* TraverseExtensional *)
@TraverseFunctorial V _ T _ ->
@TraverseIdentifiesVar V _ _ ->
@PunPun V _ T _ _.
Proof.
constructor. intros.
unfold lift, Lift_Traverse.
unfold subst, Subst_Traverse.
do 2 rewrite traverse_functorial.
eapply (traverse_extensional _). intros.
do 2 rewrite traverse_identifies_var.
just_do_it.
Qed.
(* ------------------------------------------------------------------------------ *)
(* Properties of the predicate [closed]. *)
(* This technical lemma helps prove [closed_monotonic] below. *)
Lemma closed_increment:
forall `{Lift T},
LiftLift ->
forall k t,
closed k t ->
closed (1 + k) t.
Proof.
unfold closed. intros.
match goal with h: shift _ _ = _ |- _ => rewrite <- h at 1 end.
rewrite <- lift_lift by lia.
congruence. (* amazing, isn't it? *)
Qed.
(* If a term is [k]-closed, then it is also [j]-closed for any [j] that
is greater than or equal to [k]. *)
Lemma closed_monotonic:
forall `{Lift T},
LiftLift ->
forall k t,
closed k t ->
forall j,
j >= k ->
closed j t.
Proof.
do 6 intro.
(* Inductive reformulation. *)
assert (forall i, closed (i + k) t).
induction i.
(* Base case. *)
assumption.
(* Inductive case. *)
replace (S i + k) with (1 + (i + k)) by lia. eauto using closed_increment with typeclass_instances.
(* Conclusion. *)
intros j ?.
replace j with ((j - k) + k) by lia.
eauto.
Qed.
(* A closed term is invariant under lifting. *)
Lemma closed_lift_invariant:
forall `{Lift T},
forall { _ : LiftZero },
forall { _ : LiftLift },
forall { _ : LiftLiftFuse },
forall k t,
closed k t ->
forall j,
j >= k ->
forall w,
lift w j t = t.
Proof.
induction w.
(* Base case. *)
eauto using lift_zero.
(* Inductive case. *)
change (S w) with (1 + w).
erewrite <- lift_lift_fuse by (instantiate (1 := j); lia).
rewrite IHw.
eapply closed_monotonic; eauto.
Qed.
(* A closed term is invariant under substitution. *)
Lemma closed_subst_invariant:
forall `{Lift T, Subst V T},
forall { _ : LiftLift},
forall { _ : SubstLift},
forall k t,
closed k t ->
forall j,
j >= k ->
forall v,
subst v j t = t.
Proof.
intros.
assert (h: shift j t = t).
eapply closed_monotonic; eauto.
rewrite <- h at 1.
eapply subst_lift.
Qed.
(* A variable is not closed. *)
Lemma closed_var:
forall k x : nat,
x >= k ->
closed k x ->
False.
Proof.
unfold closed. just_do_it.
Qed.
(* If [t] is [k-closed], then [shift 0 t] is [k+1]-closed. *)
Lemma lift_preserves_closed:
forall `{Lift T},
@LiftLift T _ ->
forall k (t : T),
closed k t ->
closed (S k) (shift 0 t).
Proof.
unfold closed. intros.
change (S k) with (1 + k).
rewrite <- lift_lift by lia.
congruence. (* wow! *)
Qed.
(* If [v] is [k]-closed and [t] is [k+1]-closed, then [subst v 0 t]
is [k]-closed. *)
Lemma subst_preserves_closed:
forall `{Lift V, Lift T, Subst V T},
@LiftSubst2 V _ T _ _ ->
forall k (v : V) (t : T),
closed k v ->
closed (S k) t ->
closed k (subst v 0 t).
Proof.
unfold closed. intros.
rewrite lift_subst_2 by lia.
simpl. change (1 + k) with (S k). congruence. (* wow! *)
Qed.
(* The tactic [fold_closed_hyps] looks for unfolded closedness hypotheses and
folds them. *)
Lemma fold_closed:
forall `{Lift T},
forall k t,
shift k t = t ->
closed k t.
Proof.
auto.
Qed.
Ltac fold_closed_hyps :=
repeat match goal with h: shift _ ?t = ?t |- _ =>
generalize (fold_closed _ h); clear h; intro h
end.
(* The following tactics help invert (destruct) a closedness hypothesis.
[inversion_closed_in h] destructs a specific closedness hypothesis [h],
whereas [inversion_closed] destructs all closedness hypotheses. *)
Ltac inversion_closed_in_internal h :=
(* Unfold the definition of [closed]. This exposes [lift]. *)
unfold closed in h;
(* If [lift] is applied to a constructor, simplify it. *)
rewrite expand_lift in h; simpl (@traverse _ _ _) in h; simpl_lift;
(* This may result in an equality that involves two constructors. Decompose it. *)
try (injection h; clear h; intros).
(* The above line assumes that [lift] is opaque. Otherwise, the following would
be required:
try (protects @lift do (injection h; clear h; intros))
We make [lift] opaque at the end of this file.
*)
(* At this point, [closed] is still unfolded. This is intentional. *)
Ltac inversion_closed_in h :=
inversion_closed_in_internal h;
fold_closed_hyps.
Ltac inversion_closed :=
repeat match goal with h: closed _ _ |- _ =>
inversion_closed_in_internal h
end;
fold_closed_hyps.
(* The tactic solves a closedness goal by using whatever closedness
hypotheses are available. *)
Hint Extern 1 => f_equal : construction_closed.
(* more hints to be added later on into this database *)
Ltac construction_closed :=
solve [
(* Expose the definition of [closed] in terms of [lift]. *)
unfold closed in *;
(* Presumably [lift] is applied to a constructor in the goal. Simplify it. *)
simpl_lift_goal;
(* If we are looking at a variable, the equation should look like this:
[var (shift k x) = var x]. Simplify [var] away, and apply the tactic
[lift_idx] to simplify [shift] away. *)
try (simpl; lift_idx);
(* Conclude. *)
eauto with lia construction_closed
].
(* The following hint proves a goal of the form [shift x v = v] when
the value [v] is [k]-closed for some [k] that is less than or equal
to [x]. *)
Hint Extern 1 (shift ?x ?v = ?v) =>
solve [
eapply closed_monotonic; [
eauto with typeclass_instances (* LiftLift *)
| construction_closed (* [v] is [k]-closed *)
| lia (* [k <= x] *)
]
]
: shift_closed.
(* The following tactic replaces [shift x v] with [v] in the goal
when an explicit hypothesis states that [v] is closed. *)
Ltac shift_closed :=
match goal with h: closed ?x ?v |- context[shift ?x ?v] =>
replace (shift x v) with v (* no subgoals are generated;
apparently the hypothesis [h] allows Coq to recognize
that these terms are equal *)
end.
(* The following hint proves a goal of the form [subst w x v = v] when
the value [v] is [k]-closed for some [k] that is less than or equal
to [x]. *)
Hint Extern 1 (subst ?w ?x ?v = ?v) =>
solve [
eapply closed_subst_invariant; [
eauto with typeclass_instances
| eauto with typeclass_instances
| construction_closed
| lia
]
]
: subst_closed.
(* ------------------------------------------------------------------------------ *)
(* A few properties of the function [rotate]. *)
(* This lemma ensures that we got the definition right. It is otherwise unused. *)
Lemma rotate_characterization:
forall n k,
(k = 0 -> rotate n k = n) /\
(k > 0 -> k <= n -> rotate n k = k - 1) /\
(k > n -> rotate n k = k).
Proof.
intros; repeat split; intros; unfold rotate; just_do_it.
Qed.
Instance Rotate1SelfInverse_Algebraic:
forall `{Var V, Lift V, Lift T, Subst V V, Subst V T},
@LiftVar V _ _ ->
@SubstVar V _ _ ->
@LiftLift T _ ->
@LiftSubst2 V _ T _ _ ->
@SubstSubst V _ _ T _ ->
@Pun2 V _ T _ _ ->
@Rotate1SelfInverse V _ T _ _.
Proof.
constructor. intro. unfold rotate.
(* We are looking at a subst-lift-subst-lift composition. *)
(* Permute the central lift/subst pair, to obtain subst-subst-lift-lift. *)
rewrite lift_subst_2 by lia.
(* Permute the two lifts. *)
rewrite <- lift_lift by lia.
(* Simplify. *)
rewrite lift_var. simpl.
(* Permute the two substs. *)
rewrite subst_subst by lia.
rewrite subst_var.
rewrite lift_var. subst_idx. simpl.
(* De-simplify to prepare the next rewriting step. *)
replace (@var V _ 2) with (shift 1 (@var V _ 1)) by (rewrite lift_var; auto).
(* Permute the central subst-lift. *)
rewrite <- lift_subst_2 by lia.
(* Identify two puns, and we are done. *)
rewrite pun_2.
rewrite pun_2.
reflexivity.
(* In summary, we have done this:
substA-liftA-substB-liftB
substA-substB-liftA-liftB
substB-substA-liftB-liftA
substB-liftB-substA-liftA
*)
Qed.
(* The above algebraic proof was admittedly quite tricky and obscure. Perhaps
one could come up with a simpler approach. If we are willing to give up a
tiny bit of generality and assume that [lift] and [subst] arise out of
[traverse], then we can give a simple proof, as usual, by going down to the
leaves and using [just_do_it] there. I have done this proof, so here it is,
for the record. *)
Instance Rotate1SelfInverse_Traverse:
forall `{Var V, Traverse V V, Traverse V T},
@TraverseVarIsIdentity V _ T _ ->
@TraverseIdentifiesVar V _ _ ->
@TraverseFunctorial V _ T _ ->
@Rotate1SelfInverse V _ T _ _.
Proof.
constructor. intros.
unfold rotate, subst, lift, Subst_Traverse, Lift_Traverse.
(* Go down to the leaves. *)
do 3 rewrite traverse_functorial.
apply traverse_var_is_identity. intros l x.
rewrite traverse_identifies_var.
rewrite lift_var.
rewrite subst_idx_var.
do 2 rewrite traverse_identifies_var.
rewrite lift_var.
rewrite subst_idx_var.
f_equal.
(* The goal boils down to proving that a generalized version of
[rotate 1], which exchanges [l] and [l+1], is its own inverse. *)
just_do_it.
Qed.
(* ------------------------------------------------------------------------------ *)
(* These tactics are supposed to help the user prove properties of her
custom [traverse] functions. They should work out of the box. *)
Ltac prove_traverse_identifies_var :=
reflexivity.
Ltac prove_traverse_var_injective :=
let t1 := fresh "t1" in
intros ? ? t1; induction t1;
let t2 := fresh "t2" in
intro t2; destruct t2; simpl;
let h := fresh "h" in
intros ? h; inversion h;
f_equal;
eauto using @traverse_var_injective with typeclass_instances.
(* The lemma [traverse_var_injective] can be useful if the [traverse]
function at hand calls another [traverse] function which has already
been proved injective. *)
Ltac prove_traverse_functorial :=
let t := fresh "t" in
intros ? ? t; induction t; intros; simpl;
f_equal; eauto using @traverse_functorial with typeclass_instances.
Ltac prove_traverse_relative :=
let t := fresh "t" in
intros ? ? ? t; induction t; intros; subst; simpl;
eauto using @traverse_relative with f_equal lia typeclass_instances.
Ltac prove_traverse_var_is_identity :=
intros ? ? t; induction t; intros; simpl;
f_equal; eauto using @traverse_var_is_identity with typeclass_instances.
(* ------------------------------------------------------------------------------ *)
(* The following hint databases help [eauto] solve equality goals that involve
the above laws. They can be very useful provided one takes care to organize
one's proof in such a way that these equality goals appear. This is usually
done by letting explicit equality hypotheses appear in the statement that
one is trying to establish by induction. *)
(* Using [reflexivity] just after a [rewrite] is often successful, and should
prevent [eauto] from erring too far away. However, sometimes, this is too
restrictive: for instance, multiple successive rewrites may be required.
Thus, we also use hints that involve just a [rewrite]; this allows [eauto]
to continue searching. *)
Ltac lift_lift_hint :=
first [
rewrite lift_lift by lia; reflexivity
| rewrite <- lift_lift by lia; reflexivity
| rewrite lift_lift by lia
| rewrite <- lift_lift by lia
].
Hint Extern 1 (_ = lift _ _ (lift _ _ _)) => lift_lift_hint : lift_lift.
Hint Extern 1 (lift _ _ (lift _ _ _) = _) => lift_lift_hint : lift_lift.
Ltac subst_lift_hint :=
first [
rewrite subst_lift; reflexivity
| rewrite subst_lift
].
Hint Extern 1 (subst _ _ (lift _ _ _) = _) => subst_lift_hint : subst_lift.
Hint Extern 1 (_ = subst _ _ (lift _ _ _)) => subst_lift_hint : subst_lift.
Hint Extern 1 (subst _ _ _ = _) => subst_lift_hint : subst_lift.
Hint Extern 1 (_ = subst _ _ _) => subst_lift_hint : subst_lift.
Ltac lift_subst_hint :=
first [
rewrite lift_subst_1 by lia; reflexivity
| rewrite lift_subst_2 by lia; reflexivity
| rewrite <- lift_subst_1 by lia; reflexivity
| rewrite <- lift_subst_2 by lia; reflexivity
| rewrite lift_subst_1 by lia
| rewrite lift_subst_2 by lia
| rewrite <- lift_subst_1 by lia
| rewrite <- lift_subst_2 by lia
].
Hint Extern 1 (_ = lift _ _ (subst _ _ _)) => lift_subst_hint : lift_subst.
Hint Extern 1 (lift _ _ (subst _ _ _) = _) => lift_subst_hint : lift_subst.
Hint Extern 1 (_ = lift _ _ (lift _ _ (subst _ _ _))) => do 2 lift_subst_hint : lift_subst.
Hint Extern 1 (lift _ _ (lift _ _ (subst _ _ _)) = _) => do 2 lift_subst_hint : lift_subst.
Hint Extern 1
(lift _ _ _ = subst (lift _ _ _) _ (lift _ _ _)) => lift_subst_hint : lift_subst.
Ltac subst_subst_hint :=
first [
rewrite subst_subst by lia; reflexivity
| rewrite <- subst_subst by lia; reflexivity
| rewrite subst_subst by lia
| rewrite <- subst_subst by lia
].
Hint Extern 1 (_ = subst _ _ (subst _ _ _)) => subst_subst_hint : subst_subst.
Hint Extern 1 (subst _ _ (subst _ _ _) = _) => subst_subst_hint : subst_subst.
Ltac lift_lift_fuse_hint :=
rewrite lift_lift_fuse by lia.
Hint Extern 1 (lift _ _ (lift _ _ _) = _) => lift_lift_fuse_hint : lift_lift_fuse.
Hint Extern 1 (_ = lift _ _ (lift _ _ _)) => lift_lift_fuse_hint : lift_lift_fuse.
(* ------------------------------------------------------------------------------ *)
(* Miscellaneous lemmas, often combinations and/or special cases of the above
lemmas. *)
(* Lifts are invariant under translation. *)
Lemma translate_lift:
forall w x y z,
lift w x y = z ->
forall k,
lift w (k + x) (k + y) = k + z.
Proof.
just_do_it.
Qed.
(* The following is a simple consequence of [lift_fuse_fuse]. *)
Lemma lift_one_lift_zero:
forall `{LiftLiftFuse T} t,
shift 1 (shift 0 t) = shift 0 (shift 0 t).
Proof.
eauto with lift_lift_fuse.
Qed.
(* The following is a special case of [lift_lift_fuse] that is often
useful. [ws] is [1] and [k] is [s]. *)
Lemma lift_lift_fuse_successor:
forall `{LiftLiftFuse T} t s wk,
lift wk s (shift s t) = lift (S wk) s t.
Proof.
intros.
replace (S wk) with (wk + 1) by lia.
eapply lift_lift_fuse. lia.
Qed.
Hint Extern 1 (lift ?wk _ _ = lift (S ?wk) _ _) =>
eapply lift_lift_fuse_successor
: lift_lift_fuse_successor.
(* [lift_zero] and [lift_lift_fuse_successor] are often useful when
arguing that [lift n] is equivalent to [n] successive applications
of [lift 1]. The following tactic helps with this argument. *)
Ltac iterated_lift :=
first [
rewrite lift_zero
| rewrite <- lift_lift_fuse_successor
].
(* The following lemma can be viewed as a general form of [subst_lift].
Indeed, [subst_lift] corresponds to a special case of
[subst_lift_generalized] where [n] is zero. *)
Lemma subst_lift_generalized:
forall `{Lift T, Subst V T},
forall { _ : LiftLift },
forall { _ : LiftLiftFuse },
forall { _ : SubstLift },
forall n v t,
subst v n (lift (S n) 0 t) = lift n 0 t.
Proof.
intros.
rewrite <- lift_lift_fuse_successor.
rewrite lift_lift by lia.
rewrite plus_0_r.
apply subst_lift.
Qed.
(* ------------------------------------------------------------------------------ *)
(* Hopefully, outside of this module, it is never necessary to know how [lift]
and [subst] are defined. We make them opaque. This is useful, as it
prevents [simpl] from unfolding the definitions and making a mess. *)
Global Opaque lift.
Global Opaque subst.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2B_SYMBOL_V
`define SKY130_FD_SC_HDLL__AND2B_SYMBOL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2B_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22O_2_V
`define SKY130_FD_SC_LP__A22O_2_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22o_2 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22O_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2_FUNCTIONAL_V
`define SKY130_FD_SC_LS__NOR2_FUNCTIONAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2_FUNCTIONAL_V |
module edge_detect(
input clk, //输入系统时钟
input rst_n, //复位信号，低电平有效
input rx_int, //需要检测的输入信号
output pos_rx_int, //检测到上升沿信号
output neg_rx_int, //检测到下降沿信号
output doub_rx_int //双边检测信号
);
reg rx_int0,rx_int1,rx_int2; //在内部新建寄存器，用来暂存数据信号
//若这里只用到两个寄存器变量，那么边沿检测信号是实时输出的
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
rx_int0 <= 1'b0;
rx_int1 <= 1'b0;
rx_int2 <= 1'b0;
end
else
begin
rx_int0 <= rx_int; //初始值信号赋值给0
rx_int1 <= rx_int0; //0的前一个周期的信号赋给1
rx_int2 <= rx_int1; //1的前一个周期的信号赋给2
end
end
assign pos_rx_int = rx_int1 & ~rx_int2; //前一个周期的信号为0，当前周期信号为1，则上升沿检测信号为1（有效），即检测到一个上升沿信号
assign neg_rx_int = ~rx_int1 & rx_int2; //前一个周期的信号为1，当前周期信号为0，则下降沿检测信号为1（有效），即检测到一个下降沿信号
assign doub_rx_int = rx_int1 ^ rx_int2; //两次变量发生变化时，双边检测信号为1（有效），即检测到上升沿、和下降沿信号
endmodule
|
/*
** -----------------------------------------------------------------------------**
** interrupts_vector333.v
**
** Interrupts controller
**
** Copyright (C) 2005-2008 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X333
** X333 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
// will support 16 priority (0 - highest) masked vector interrupts (pos. edge triggered), use 4 locations of address space,
// generate 32-bit data output (16MSBs - before mask, lower 16 bits - masked)
module interrupts_vector(sclk, // @negedge
pre_wen, // 1 cycle ahead of write data
pre_wa, // [1:0] - write address:
// 0 - reset selected interrupt bits
// 1 - disable selected interrupt bits (mask)
// 2 - enable selected interrupt bits
// 3 - write vector number (bits [0:7], [11:8] - interrupt number (0..15)
di, // [15:0] data in
do, // [31:0] data out (bits {15:0} - masked interrupts, [31:0] - same before mask
irq, // interrupt request (active high)
inta, // interrupt acknowledge input (active low) 170ns long
irq_in, // [15:0] input interrupt requests (posedge)
irqv); // [7:0] interrupt vector (valid befor end on inta
input sclk;
input pre_wen;
input [1:0] pre_wa;
input [15:0] di;
output [31:0] do;
output irq;
input inta;
input [15:0] irq_in;
output [7:0] irqv;
wire [15:0] irq_insa;
reg [15:0] irq_insb;
reg [15:0] irq_insc; //single cycle sync interrupt request.
///AF: wire [15:0] irq_rst;
reg rst_rqs, en_rqs, dis_rqs, pre_set_irqv, set_irqv;
reg [ 3:0] irqv_a; // irq vectors table write address
reg [ 7:0] irqv_d; // irq vectors table write data
reg [15:0] rst_rq;
reg [15:0] dis_rq;
// reg [15:0] en_rq;
wire [15:0] en_rq;
wire [15:0] irqm;
reg [ 5:0] inta_s; // inta sync to clock
// reg [15:0] irq_um; // interrupts (before mask)
wire [15:0] irq_um; // interrupts (before mask)
reg [15:0] irq_frz; // frozen masked irq-s (for the duration of the synchronized inta)
wire [15:0] irqp; // one-hot irq (prioritized)
wire [ 3:0] irqn; // encoded vector number;
reg [ 3:0] irqn_r; // registered encoded vector number (not neded to be registered?
wire [15:0] rst_rq_inta; // reset interrupts from inta
reg pre_irq;
reg [15:0] did; // did[15:0] delayed by 1 cycle
wire en_all_rq; // for simulation
assign irq=pre_irq && inta;
assign do[31:0]={irq_um[15:0], irq_frz[15:0]};
assign irqp[ 0] = irq_frz[ 0];
assign irqp[ 1] = irq_frz[ 1] && !irq_frz[ 0];
assign irqp[ 2] = irq_frz[ 2] && !(|irq_frz[ 1:0]);
assign irqp[ 3] = irq_frz[ 3] && !(|irq_frz[ 2:0]);
assign irqp[ 4] = irq_frz[ 4] && !(|irq_frz[ 3:0]);
assign irqp[ 5] = irq_frz[ 5] && !(|irq_frz[ 4:0]);
assign irqp[ 6] = irq_frz[ 6] && !(|irq_frz[ 5:0]);
assign irqp[ 7] = irq_frz[ 7] && !(|irq_frz[ 6:0]);
assign irqp[ 8] = irq_frz[ 8] && !(|irq_frz[ 7:0]);
assign irqp[ 9] = irq_frz[ 9] && !(|irq_frz[ 8:0]);
assign irqp[10] = irq_frz[10] && !(|irq_frz[ 9:0]);
assign irqp[11] = irq_frz[11] && !(|irq_frz[10:0]);
assign irqp[12] = irq_frz[12] && !(|irq_frz[11:0]);
assign irqp[13] = irq_frz[13] && !(|irq_frz[12:0]);
assign irqp[14] = irq_frz[14] && !(|irq_frz[13:0]);
assign irqp[15] = irq_frz[15] && !(|irq_frz[14:0]);
assign irqn[0]= irqp[1] | irqp[3] | irqp[ 5] | irqp[ 7] | irqp[ 9] | irqp[11] | irqp[13] | irqp[15];
assign irqn[1]= irqp[2] | irqp[3] | irqp[ 6] | irqp[ 7] | irqp[10] | irqp[11] | irqp[14] | irqp[15];
assign irqn[2]= irqp[4] | irqp[5] | irqp[ 6] | irqp[ 7] | irqp[12] | irqp[13] | irqp[14] | irqp[15];
assign irqn[3]= irqp[8] | irqp[9] | irqp[10] | irqp[11] | irqp[12] | irqp[13] | irqp[14] | irqp[15];
assign rst_rq_inta[ 0]= inta_s[1] && !inta_s[2] && (irqn_r[3:0] == 4'h0);
assign rst_rq_inta[ 1]= inta_s[1] && !inta_s[2] && (irqn_r[3:0] == 4'h1);
assign rst_rq_inta[ 2]= inta_s[1] && !inta_s[2] && (irqn_r[3:0] == 4'h2);
assign rst_rq_inta[ 3]= inta_s[1] && !inta_s[2] && (irqn_r[3:0] == 4'h3);
assign rst_rq_inta[ 4]= inta_s[1] && !inta_s[2] && (irqn_r[3:0] == 4'h4);
assign rst_rq_inta[ 5]= inta_s[1] && !inta_s[2] && (irqn_r[3:0] == 4'h5);
assign rst_rq_inta[ 6]= inta_s[1] && !inta_s[2] && (irqn_r[3:0] == 4'h6);
assign rst_rq_inta[ 7]= inta_s[1] && !inta_s[2] && (irqn_r[3:0] == 4'h7);
assign rst_rq_inta[ 8]= inta_s[1] && !inta_s[2] && (irqn_r[3:0] == 4'h8);
assign rst_rq_inta[ 9]= inta_s[1] && !inta_s[2] && (irqn_r[3:0] == 4'h9);
assign rst_rq_inta[10]= inta_s[1] && !inta_s[2] && (irqn_r[3:0] == 4'ha);
assign rst_rq_inta[11]= inta_s[1] && !inta_s[2] && (irqn_r[3:0] == 4'hb);
assign rst_rq_inta[12]= inta_s[1] && !inta_s[2] && (irqn_r[3:0] == 4'hc);
assign rst_rq_inta[13]= inta_s[1] && !inta_s[2] && (irqn_r[3:0] == 4'hd);
assign rst_rq_inta[14]= inta_s[1] && !inta_s[2] && (irqn_r[3:0] == 4'he);
assign rst_rq_inta[15]= inta_s[1] && !inta_s[2] && (irqn_r[3:0] == 4'hf);
FDE_1 i_en_all_rq(.C(sclk), .CE(pre_wen), .D(1'b1), .Q(en_all_rq)); // initially disabled - till first write
FDC i_insa_0 (.C(irq_in[ 0]), .CLR(irq_insc[ 0]), .D(1'b1), .Q(irq_insa[ 0]));
FDC i_insa_1 (.C(irq_in[ 1]), .CLR(irq_insc[ 1]), .D(1'b1), .Q(irq_insa[ 1]));
FDC i_insa_2 (.C(irq_in[ 2]), .CLR(irq_insc[ 2]), .D(1'b1), .Q(irq_insa[ 2]));
FDC i_insa_3 (.C(irq_in[ 3]), .CLR(irq_insc[ 3]), .D(1'b1), .Q(irq_insa[ 3]));
FDC i_insa_4 (.C(irq_in[ 4]), .CLR(irq_insc[ 4]), .D(1'b1), .Q(irq_insa[ 4]));
FDC i_insa_5 (.C(irq_in[ 5]), .CLR(irq_insc[ 5]), .D(1'b1), .Q(irq_insa[ 5]));
FDC i_insa_6 (.C(irq_in[ 6]), .CLR(irq_insc[ 6]), .D(1'b1), .Q(irq_insa[ 6]));
FDC i_insa_7 (.C(irq_in[ 7]), .CLR(irq_insc[ 7]), .D(1'b1), .Q(irq_insa[ 7]));
FDC i_insa_8 (.C(irq_in[ 8]), .CLR(irq_insc[ 8]), .D(1'b1), .Q(irq_insa[ 8]));
FDC i_insa_9 (.C(irq_in[ 9]), .CLR(irq_insc[ 9]), .D(1'b1), .Q(irq_insa[ 9]));
FDC i_insa_10 (.C(irq_in[10]), .CLR(irq_insc[10]), .D(1'b1), .Q(irq_insa[10]));
FDC i_insa_11 (.C(irq_in[11]), .CLR(irq_insc[11]), .D(1'b1), .Q(irq_insa[11]));
FDC i_insa_12 (.C(irq_in[12]), .CLR(irq_insc[12]), .D(1'b1), .Q(irq_insa[12]));
FDC i_insa_13 (.C(irq_in[13]), .CLR(irq_insc[13]), .D(1'b1), .Q(irq_insa[13]));
FDC i_insa_14 (.C(irq_in[14]), .CLR(irq_insc[14]), .D(1'b1), .Q(irq_insa[14]));
FDC i_insa_15 (.C(irq_in[15]), .CLR(irq_insc[15]), .D(1'b1), .Q(irq_insa[15]));
FD_1 i_irqm_0 (.C(sclk), .D(en_rq[ 0] || (!dis_rq[ 0] && irqm[ 0])), .Q(irqm[ 0]));
FD_1 i_irqm_1 (.C(sclk), .D(en_rq[ 1] || (!dis_rq[ 1] && irqm[ 1])), .Q(irqm[ 1]));
FD_1 i_irqm_2 (.C(sclk), .D(en_rq[ 2] || (!dis_rq[ 2] && irqm[ 2])), .Q(irqm[ 2]));
FD_1 i_irqm_3 (.C(sclk), .D(en_rq[ 3] || (!dis_rq[ 3] && irqm[ 3])), .Q(irqm[ 3]));
FD_1 i_irqm_4 (.C(sclk), .D(en_rq[ 4] || (!dis_rq[ 4] && irqm[ 4])), .Q(irqm[ 4]));
FD_1 i_irqm_5 (.C(sclk), .D(en_rq[ 5] || (!dis_rq[ 5] && irqm[ 5])), .Q(irqm[ 5]));
FD_1 i_irqm_6 (.C(sclk), .D(en_rq[ 6] || (!dis_rq[ 6] && irqm[ 6])), .Q(irqm[ 6]));
FD_1 i_irqm_7 (.C(sclk), .D(en_rq[ 7] || (!dis_rq[ 7] && irqm[ 7])), .Q(irqm[ 7]));
FD_1 i_irqm_8 (.C(sclk), .D(en_rq[ 8] || (!dis_rq[ 8] && irqm[ 8])), .Q(irqm[ 8]));
FD_1 i_irqm_9 (.C(sclk), .D(en_rq[ 9] || (!dis_rq[ 9] && irqm[ 9])), .Q(irqm[ 9]));
FD_1 i_irqm_10 (.C(sclk), .D(en_rq[10] || (!dis_rq[10] && irqm[10])), .Q(irqm[10]));
FD_1 i_irqm_11 (.C(sclk), .D(en_rq[11] || (!dis_rq[11] && irqm[11])), .Q(irqm[11]));
FD_1 i_irqm_12 (.C(sclk), .D(en_rq[12] || (!dis_rq[12] && irqm[12])), .Q(irqm[12]));
FD_1 i_irqm_13 (.C(sclk), .D(en_rq[13] || (!dis_rq[13] && irqm[13])), .Q(irqm[13]));
FD_1 i_irqm_14 (.C(sclk), .D(en_rq[14] || (!dis_rq[14] && irqm[14])), .Q(irqm[14]));
FD_1 i_irqm_15 (.C(sclk), .D(en_rq[15] || (!dis_rq[15] && irqm[15])), .Q(irqm[15]));
FD_1 i_en_rq_0 (.C(sclk), .D(en_rqs & did[ 0]), .Q(en_rq[ 0]));
FD_1 i_en_rq_1 (.C(sclk), .D(en_rqs & did[ 1]), .Q(en_rq[ 1]));
FD_1 i_en_rq_2 (.C(sclk), .D(en_rqs & did[ 2]), .Q(en_rq[ 2]));
FD_1 i_en_rq_3 (.C(sclk), .D(en_rqs & did[ 3]), .Q(en_rq[ 3]));
FD_1 i_en_rq_4 (.C(sclk), .D(en_rqs & did[ 4]), .Q(en_rq[ 4]));
FD_1 i_en_rq_5 (.C(sclk), .D(en_rqs & did[ 5]), .Q(en_rq[ 5]));
FD_1 i_en_rq_6 (.C(sclk), .D(en_rqs & did[ 6]), .Q(en_rq[ 6]));
FD_1 i_en_rq_7 (.C(sclk), .D(en_rqs & did[ 7]), .Q(en_rq[ 7]));
FD_1 i_en_rq_8 (.C(sclk), .D(en_rqs & did[ 8]), .Q(en_rq[ 8]));
FD_1 i_en_rq_9 (.C(sclk), .D(en_rqs & did[ 9]), .Q(en_rq[ 9]));
FD_1 i_en_rq_10 (.C(sclk), .D(en_rqs & did[10]), .Q(en_rq[10]));
FD_1 i_en_rq_11 (.C(sclk), .D(en_rqs & did[11]), .Q(en_rq[11]));
FD_1 i_en_rq_12 (.C(sclk), .D(en_rqs & did[12]), .Q(en_rq[12]));
FD_1 i_en_rq_13 (.C(sclk), .D(en_rqs & did[13]), .Q(en_rq[13]));
FD_1 i_en_rq_14 (.C(sclk), .D(en_rqs & did[14]), .Q(en_rq[14]));
FD_1 i_en_rq_15 (.C(sclk), .D(en_rqs & did[15]), .Q(en_rq[15]));
FD_1 i_irq_um_0 (.C(sclk), .D(~(rst_rq[ 0]) & (irq_insc[ 0] | irq_um[ 0])), .Q(irq_um[ 0]));
FD_1 i_irq_um_1 (.C(sclk), .D(~(rst_rq[ 1]) & (irq_insc[ 1] | irq_um[ 1])), .Q(irq_um[ 1]));
FD_1 i_irq_um_2 (.C(sclk), .D(~(rst_rq[ 2]) & (irq_insc[ 2] | irq_um[ 2])), .Q(irq_um[ 2]));
FD_1 i_irq_um_3 (.C(sclk), .D(~(rst_rq[ 3]) & (irq_insc[ 3] | irq_um[ 3])), .Q(irq_um[ 3]));
FD_1 i_irq_um_4 (.C(sclk), .D(~(rst_rq[ 4]) & (irq_insc[ 4] | irq_um[ 4])), .Q(irq_um[ 4]));
FD_1 i_irq_um_5 (.C(sclk), .D(~(rst_rq[ 5]) & (irq_insc[ 5] | irq_um[ 5])), .Q(irq_um[ 5]));
FD_1 i_irq_um_6 (.C(sclk), .D(~(rst_rq[ 6]) & (irq_insc[ 6] | irq_um[ 6])), .Q(irq_um[ 6]));
FD_1 i_irq_um_7 (.C(sclk), .D(~(rst_rq[ 7]) & (irq_insc[ 7] | irq_um[ 7])), .Q(irq_um[ 7]));
FD_1 i_irq_um_8 (.C(sclk), .D(~(rst_rq[ 8]) & (irq_insc[ 8] | irq_um[ 8])), .Q(irq_um[ 8]));
FD_1 i_irq_um_9 (.C(sclk), .D(~(rst_rq[ 9]) & (irq_insc[ 9] | irq_um[ 9])), .Q(irq_um[ 9]));
FD_1 i_irq_um_10 (.C(sclk), .D(~(rst_rq[10]) & (irq_insc[10] | irq_um[10])), .Q(irq_um[10]));
FD_1 i_irq_um_11 (.C(sclk), .D(~(rst_rq[11]) & (irq_insc[11] | irq_um[11])), .Q(irq_um[11]));
FD_1 i_irq_um_12 (.C(sclk), .D(~(rst_rq[12]) & (irq_insc[12] | irq_um[12])), .Q(irq_um[12]));
FD_1 i_irq_um_13 (.C(sclk), .D(~(rst_rq[13]) & (irq_insc[13] | irq_um[13])), .Q(irq_um[13]));
FD_1 i_irq_um_14 (.C(sclk), .D(~(rst_rq[14]) & (irq_insc[14] | irq_um[14])), .Q(irq_um[14]));
FD_1 i_irq_um_15 (.C(sclk), .D(~(rst_rq[15]) & (irq_insc[15] | irq_um[15])), .Q(irq_um[15]));
myRAM16X8D_1 i_vecttab (.D(irqv_d[7:0]), .WE(set_irqv), .clk(sclk), .AW(irqv_a[3:0]), .AR(irqn_r[3:0]), .QR(irqv[7:0]), .QW());
always @ (negedge sclk) begin
if (pre_wen) did[15:0] <= di[15:0];
if (en_all_rq) begin
irq_insb[15:0] <= irq_insa[15:0];
irq_insc[15:0] <= irq_insb[15:0] & (~irq_insc[15:0]);
end else begin
irq_insb[15:0] <= 16'h0;
irq_insc[15:0] <= 16'h0;
end
rst_rqs <= pre_wen && (pre_wa[1:0] == 2'h0);
dis_rqs <= pre_wen && (pre_wa[1:0] == 2'h1);
en_rqs <= pre_wen && (pre_wa[1:0] == 2'h2);
pre_set_irqv <= pre_wen && (pre_wa[1:0] == 2'h3);
set_irqv <= pre_set_irqv;
if (pre_set_irqv) irqv_a[3:0] <= did[11:8];
if (pre_set_irqv) irqv_d[7:0] <= did[ 7:0];
rst_rq[15:0] <= ({16{rst_rqs}} & did[15:0]) | rst_rq_inta[15:0];
dis_rq[15:0] <= ({16{dis_rqs}} & did[15:0]);
// en_rq [15:0] <= ({15{ en_rqs}} & did[15:0]);
inta_s[5:0] <= {inta_s[4:0], inta};
if (inta_s[1]) irq_frz[15:0] <= irq_um[15:0] & irqm[15:0];
irqn_r[3:0] <= irqn[3:0]; // will be invalid for a cycle - long combinatorial logic delays
pre_irq <= |irq_frz[15:0] & inta_s[5];
end
endmodule
module myRAM16X8D_1(D,WE,clk,AW,AR,QW,QR);
input [7:0] D;
input WE,clk;
input [3:0] AW;
input [3:0] AR;
output [7:0] QW;
output [7:0] QR;
reg [7:0] ram [0:15];
always @ (negedge clk) if (WE) ram[AW] <= D;
assign QW= ram[AW];
assign QR= ram[AR];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_BEHAVIORAL_V
`define SKY130_FD_SC_HS__FILL_BEHAVIORAL_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_BEHAVIORAL_V |
//
`timescale 1ns/1ps
module test_afifo_sram ();
parameter DEPTH =256, ADDRESS_WIDTH = 8, WIDTH=8;
parameter clk_period = 2;
parameter half_period = 1;
reg CLK;
reg REN;
reg WEN;
reg RESET;
reg valid;
reg [WIDTH-1:0] Data_in [DEPTH-1:0];
wire [WIDTH-1:0] Data_out [DEPTH-1:0];
wire [DEPTH-1:0] Full_out;
wire [DEPTH-1:0] Empty_out;
MatrixInput_sram #(.DEPTH(DEPTH),.ADDRESS_WIDTH(ADDRESS_WIDTH),.WIDTH(WIDTH)) DUT (
.CLK(CLK),.valid(valid),.REN(REN),.WEN(WEN),.RESET(RESET),
.Data_in(Data_in),.Data_out(Data_out),.Full_out(Full_out),.Empty_out(Empty_out));
always begin
#half_period
CLK = ~CLK;
end
initial begin
RESET = 1'b1;
valid = 1'b0;
REN = 1'b0;
WEN = 1'b0;
CLK = 1'b0;
$dumpfile("test.vcd") ;
$dumpvars;
#20 RESET=1'b0;
#clk_period
for (integer i=0;i<DEPTH;i++)
Data_in[i] = 8'haa;
writeMem();
#clk_period
for (integer i=0;i<DEPTH;i++)
Data_in[i] = 8'hbb;
writeMem();
#clk_period
#clk_period
#clk_period readMem();
#clk_period readMem();
#clk_period
#clk_period
#clk_period $finish;
end
task writeMem;
//input [WIDTH-1:0] wdata [DEPTH-1:0];
begin
WEN = 1;
//D = wdata;
#clk_period
WEN = 0;
end
endtask
task readMem;
begin
REN = 1;
valid = 1;
#clk_period
REN = 0;
valid = 0;
end
endtask
endmodule
|
// Copyright (C) 2005 Peio Azkarate, [email protected]
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
(* signal_encoding = "user" *)
(* safe_implementation = "yes" *)
module pciwbsequ_new ( clk_i, nrst_i, cmd_i, cbe_i, frame_i, irdy_i, devsel_o,
trdy_o, adrcfg_i, adrmem_i, pciadrLD_o, pcidOE_o, parOE_o, wbdatLD_o,
wbrgdMX_o, wbd16MX_o, wrcfg_o, rdcfg_o, wb_sel_o, wb_we_o, wb_stb_o,
wb_cyc_o, wb_ack_i, wb_err_i, debug_init, debug_access );
// General
input clk_i;
input nrst_i;
// pci
// adr_i
input [3:0] cmd_i;
input [3:0] cbe_i;
input frame_i;
input irdy_i;
output devsel_o;
output trdy_o;
// control
input adrcfg_i;
input adrmem_i;
output pciadrLD_o;
output pcidOE_o;
output reg parOE_o;
output wbdatLD_o;
output wbrgdMX_o;
output wbd16MX_o;
output wrcfg_o;
output rdcfg_o;
// whisbone
output [1:0] wb_sel_o;
output wb_we_o;
inout wb_stb_o;
output wb_cyc_o;
input wb_ack_i;
input wb_err_i;
// debug signals
output reg debug_init;
output reg debug_access;
//type PciFSM is ( PCIIDLE, B_BUSY, S_DATA1, S_DATA2, TURN_AR );
//wire pst_pci : PciFSM;
//wire nxt_pci : PciFSM;
// typedef enum reg [2:0] {
// RED, GREEN, BLUE, CYAN, MAGENTA, YELLOW
// } color_t;
//
// color_t my_color = GREEN;
// parameter PCIIDLE = 2'b00;
// parameter B_BUSY = 2'b01;
// parameter S_DATA1 = 2'b10;
// parameter S_DATA2 = 2'b11;
// parameter TURN_AR = 3'b100;
reg [2:0] pst_pci;
reg [2:0] nxt_pci;
parameter [2:0]
PCIIDLE = 3'b000,
B_BUSY = 3'b001,
S_DATA1 = 3'b010,
S_DATA2 = 3'b011,
TURN_AR = 3'b100;
initial begin
pst_pci = 3'b000;
end
initial begin
nxt_pci = 3'b000;
end
wire sdata1;
wire sdata2;
wire idleNX;
wire sdata1NX;
wire sdata2NX;
wire turnarNX;
wire idle;
reg devselNX_n;
reg trdyNX_n;
reg devsel;
reg trdy;
wire adrpci;
wire acking;
wire rdcfg;
reg targOE;
reg pcidOE;
// always @(nrst_i or clk_i or nxt_pci)
always @(negedge nrst_i or posedge clk_i)
begin
if( nrst_i == 0 )
pst_pci <= PCIIDLE;
else
pst_pci <= nxt_pci;
end
// always @(negedge nrst_i or posedge clk_i)
always @( pst_pci or frame_i or irdy_i or adrcfg_i or adrpci or acking )
begin
devselNX_n <= 1'b1;
trdyNX_n <= 1'b1;
case (pst_pci)
PCIIDLE :
begin
if ( frame_i == 0 )
nxt_pci <= B_BUSY;
else
nxt_pci <= PCIIDLE;
end
B_BUSY:
if ( adrpci == 0 )
nxt_pci <= TURN_AR;
else
begin
nxt_pci <= S_DATA1;
devselNX_n <= 0;
end
S_DATA1:
if ( acking == 1 )
begin
nxt_pci <= S_DATA2;
devselNX_n <= 0;
trdyNX_n <= 0;
end
else
begin
nxt_pci <= S_DATA1;
devselNX_n <= 0;
end
S_DATA2:
if ( frame_i == 1 && irdy_i == 0 )
nxt_pci <= TURN_AR;
else
begin
nxt_pci <= S_DATA2;
devselNX_n <= 0;
trdyNX_n <= 0;
end
TURN_AR:
if ( frame_i == 1 )
nxt_pci <= PCIIDLE;
else
nxt_pci <= TURN_AR;
endcase
end
// FSM control signals
assign adrpci = adrmem_i;
assign acking = (
( wb_ack_i == 1 || wb_err_i == 1 ) ||
( adrcfg_i == 1 && irdy_i == 0)
) ? 1'b1 : 1'b0;
// FSM derived Control signals
assign idle = ( pst_pci <= PCIIDLE ) ? 1'b1 : 1'b0;
assign sdata1 = ( pst_pci <= S_DATA1 ) ? 1'b1 : 1'b0;
assign sdata2 = ( pst_pci <= S_DATA2 ) ? 1'b1 : 1'b0;
assign idleNX = ( nxt_pci <= PCIIDLE ) ? 1'b1 : 1'b0;
assign sdata1NX = ( nxt_pci <= S_DATA1 ) ? 1'b1 : 1'b0;
assign sdata2NX = ( nxt_pci <= S_DATA2 ) ? 1'b1 : 1'b0;
assign turnarNX = ( nxt_pci <= TURN_AR ) ? 1'b1 : 1'b0;
// PCI Data Output Enable
// always @( nrst_i or clk_i or cmd_i [0] or sdata1NX or turnarNX )
always @(negedge nrst_i or posedge clk_i)
begin
if ( nrst_i == 0 )
pcidOE <= 0;
else
if ( sdata1NX == 1 && cmd_i [0] == 0 )
pcidOE <= 1;
else
if ( turnarNX == 1 )
pcidOE <= 0;
end
assign pcidOE_o = pcidOE;
// PAR Output Enable
// PCI Read data phase
// PAR is valid 1 cicle after data is valid
// always @( nrst_i or clk_i or cmd_i [0] or sdata2NX or turnarNX )
always @(negedge nrst_i or posedge clk_i)
begin
if ( nrst_i == 0 )
parOE_o <= 0;
else
if ( ( sdata2NX == 1 || turnarNX == 1 ) && cmd_i [0] == 0 )
parOE_o <= 1;
else
parOE_o <= 0;
end
// Target s/t/s signals OE control
// targOE <= '1' when ( idle = '0' and adrpci = '1' ) else '0';
// always @( nrst_i or clk_i or sdata1NX or idleNX )
always @(negedge nrst_i or posedge clk_i)
begin
if ( nrst_i == 0 )
targOE <= 0;
else
if ( sdata1NX == 1 )
targOE <= 1;
else
if ( idleNX == 1 )
targOE <= 0;
end
// WHISBONE outs
assign wb_cyc_o = (adrmem_i == 1 && sdata1 == 1) ? 1'b1 : 1'b0;
assign wb_stb_o = (adrmem_i == 1 && sdata1 == 1 && irdy_i == 0 ) ? 1'b1 : 1'b0;
// PCI(Little endian) to WB(Big endian)
assign wb_sel_o [1] = (! cbe_i [0]) || (! cbe_i [2]);
assign wb_sel_o [0] = (! cbe_i [1]) || (! cbe_i [3]);
assign wb_we_o = cmd_i [0];
// Syncronized PCI outs
always @(negedge nrst_i or posedge clk_i)
begin
if( nrst_i == 0 )
begin
devsel <= 1;
trdy <= 1;
end
else
begin
devsel <= devselNX_n;
trdy <= trdyNX_n;
end
end
assign devsel_o = ( targOE == 1 ) ? devsel : 1'bZ;
assign trdy_o = ( targOE == 1 ) ? trdy : 1'bZ;
// rd/wr Configuration Space Registers
assign wrcfg_o = (
adrcfg_i == 1 &&
cmd_i [0] == 1 &&
sdata2 == 1
) ? 1'b1 : 1'b0;
assign rdcfg = (
adrcfg_i == 1 &&
cmd_i [0] == 0 &&
(sdata1 == 1 || sdata2 == 1)
) ? 1'b1 : 1'b0;
assign rdcfg_o = rdcfg;
// LoaD enable signals
assign pciadrLD_o = ! frame_i;
assign wbdatLD_o = wb_ack_i;
// Mux control signals
assign wbrgdMX_o = ! rdcfg;
assign wbd16MX_o = (cbe_i [3] == 0 || cbe_i [2] == 0) ? 1'b1 : 1'b0;
// debug outs
always @(negedge nrst_i or posedge clk_i)
begin
if ( nrst_i == 0 )
debug_init <= 0;
else
if (devsel == 0)
debug_init <= 1;
end
always @(negedge nrst_i or posedge clk_i)
begin
if ( nrst_i == 0 )
debug_access <= 0;
else
if (wb_stb_o == 1)
debug_access <= 1;
end
endmodule
|
// -*- Mode: Verilog -*-
// Filename : adxl362_spi.v
// Description : SPI Slave Interface for ADXL362
// Author : Philip Tracton
// Created On : Wed Jun 22 21:33:25 2016
// Last Modified By: Philip Tracton
// Last Modified On: Wed Jun 22 21:33:25 2016
// Update Count : 0
// Status : Unknown, Use with caution!
`include "adxl362_registers.vh"
module adxl362_spi (/*AUTOARG*/
// Outputs
MISO, address, data_write, data_fifo_write, write, read_data_fifo,
// Inputs
SCLK, MOSI, nCS, clk_sys, data_read, data_fifo_read, rst
) ;
input wire SCLK;
input wire MOSI;
input wire nCS;
output reg MISO;
// output wire MISO;
input wire clk_sys;
output reg [5:0] address;
output reg [7:0] data_write;
input wire [7:0] data_read;
input wire [15:0] data_fifo_read;
output reg data_fifo_write;
output reg write;
input wire rst;
output reg read_data_fifo;
/*AUTOWIRE*/
/*AUTOREG*/
reg [7:0] spi_data_in = 0;
reg [7:0] spi_data_out =0 ;
reg [2:0] bit_count =0;
reg [2:0] bit_count_previous =0;
reg [7:0] command =0;
reg read_fifo = 0;
wire [7:0] data_rd;
reg flush_fifo = 0;
wire flush = flush_fifo ;//| (nCS == 1);
reg write_fifo =0;
wire empty_fifo; // From fifo of adxl362_fifo.v
wire full_fifo; // From fifo of adxl362_fifo.v
//
// Capture SPI data coming in. The spec says this IC is always CPHA = 0 and CPOL = 0
// so we can get away with this very simple solution.
//
reg [7:0] running_bit_count =0;
// assign MISO = (nCS) ? 1'bz : spi_data_out[7-bit_count];
always @(posedge SCLK or posedge nCS)
if (nCS) begin
bit_count <= 0;
bit_count_previous <= 0;
spi_data_in <= 0;
MISO <= 1'bz;
end else begin
bit_count_previous <= bit_count;
bit_count <= bit_count + 1;
running_bit_count <= running_bit_count + 1;
spi_data_in <= {spi_data_in[6:0], MOSI};
MISO <= spi_data_out[7-bit_count];
end
//
wire spi_byte_done = (bit_count == 0) && (bit_count_previous == 7);
wire spi_byte_begin = (bit_count == 1) && (bit_count_previous == 0);
// wire spi_byte_done = (bit_count == 7);
// wire spi_byte_begin = (bit_count == 0);
//
// Detect the edge and pulse write for a single clock while we
// are not flushing the FIFO
//
reg [2:0] wr_state;
reg [2:0] wr_next_state;
parameter WR_IDLE = 3'h0;
parameter WR_WRITE = 3'h1;
parameter WR_DONE = 3'h2;
always @(posedge clk_sys) begin
wr_state <= wr_next_state;
end
always @(*)
case (wr_state)
WR_IDLE: begin
write_fifo = 0;
if ((bit_count == 0) && (bit_count_previous == 7)) begin
wr_next_state = WR_WRITE;
end else begin
wr_next_state = WR_IDLE;
end
end
WR_WRITE: begin
write_fifo = 1;
wr_next_state = WR_DONE;
end
WR_DONE:begin
write_fifo = 0;
wr_next_state = WR_IDLE;
end
default:
wr_next_state = WR_IDLE;
endcase // case (state)
adxl362_fifo #(.WIDTH(8),.DEPTH(8))
fifo (
// Outputs
.data_read (data_rd),
.full (full_fifo),
.empty (empty_fifo),
// Inputs
.data_write (spi_data_in),
.clk (clk_sys),
.rst (rst),
.flush (flush_fifo),
.read (read_fifo),
.write (write_fifo));
parameter STATE_IDLE = 5'h00;
parameter STATE_WAIT_START_ADDRESS = 5'h02;
parameter STATE_READ_ADDRESS = 5'h03;
parameter STATE_WAIT_START_DATA= 5'h04;
parameter STATE_WAIT_START_READ_RESPONSE = 5'h05;
parameter STATE_READ_DATA = 5'h06;
parameter STATE_WRITE_REGISTER = 5'h07;
parameter STATE_WRITE_REGISTER_DONE = 5'h08;
parameter STATE_WRITE_INCREMENT_ADDRESS = 5'h09;
parameter STATE_WAIT_DONE_READ_RESPONSE = 5'h0A;
parameter STATE_READ_INCREMENT_ADDRESS = 5'h0B;
parameter STATE_WAIT_START_FIFO_RESPONSE_LOW = 5'h0C;
parameter STATE_WAIT_DONE_FIFO_RESPONSE_LOW = 5'h0D;
parameter STATE_WAIT_START_FIFO_RESPONSE_HIGH = 5'h0E;
parameter STATE_WAIT_DONE_FIFO_RESPONSE_HIGH= 5'h0F;
parameter STATE_WAIT_START_FIFO_READ_LOW = 5'h10;
parameter STATE_WAIT_START_FIFO_READ_HIGH = 5'h11;
parameter STATE_POP_FIFO = 5'h12;
reg [4:0] state = STATE_IDLE;
reg [4:0] next_state = STATE_IDLE;
reg first = 0;
reg finish = 0;
reg terminate_transaction =0;
always @(posedge clk_sys)
state <= next_state;
always @(*) begin
case (state)
STATE_IDLE: begin
if (nCS) begin
command = 0;
address = 0;
spi_data_out = 0;
data_write = 0;
write = 0;
first = 0;
read_data_fifo = 0;
end
if (! nCS) begin
if (spi_byte_done) begin
command = spi_data_in;
if (`ADXL362_COMMAND_FIFO == command) begin
spi_data_out = data_rd;
next_state = STATE_WAIT_START_FIFO_READ_LOW;
end else if ((`ADXL362_COMMAND_WRITE == command) || (`ADXL362_COMMAND_READ==command)) begin
next_state = STATE_WAIT_START_ADDRESS;
end
end
end
end // case: STATE_IDLE
STATE_WAIT_START_ADDRESS: begin
if (nCS) begin
next_state = STATE_IDLE;
end else if (spi_byte_begin) begin
next_state = STATE_READ_ADDRESS;
end else begin
next_state = STATE_WAIT_START_ADDRESS;
end
end
STATE_READ_ADDRESS: begin
if (nCS) begin
next_state = STATE_IDLE;
end else if (spi_byte_done) begin
address = spi_data_in;
spi_data_out = data_read;
if (`ADXL362_COMMAND_WRITE == command) next_state = STATE_WAIT_START_DATA;
if (`ADXL362_COMMAND_READ == command) next_state = STATE_WAIT_START_READ_RESPONSE;
end else begin
next_state = STATE_READ_ADDRESS;
end
end
STATE_WAIT_START_DATA: begin
if (!nCS) begin
if (spi_byte_begin) begin
next_state = STATE_READ_DATA;
end else begin
next_state = STATE_WAIT_START_DATA;
end
end else begin
next_state = STATE_IDLE;
end
end
STATE_READ_DATA:begin
if (nCS) begin
next_state = STATE_IDLE;
end else if (spi_byte_done) begin
data_write = spi_data_in;
next_state = STATE_WRITE_REGISTER;
end else begin
next_state = STATE_READ_DATA;
end
end
STATE_WRITE_REGISTER:begin
write = 1;
next_state = STATE_WRITE_REGISTER_DONE;
end
STATE_WRITE_REGISTER_DONE:begin
if (nCS) begin
next_state = STATE_IDLE;
end else begin
write = 0;
first = 1;
next_state = STATE_WRITE_INCREMENT_ADDRESS;
end
end
STATE_WRITE_INCREMENT_ADDRESS: begin
if (nCS) begin
next_state = STATE_IDLE;
end else begin
if (first) begin
address = address + 1;
first = 0;
end
next_state = STATE_WAIT_START_DATA;
end
end
STATE_WAIT_START_READ_RESPONSE:begin
if (! nCS) begin
spi_data_out = data_read; //Needed for burst mode
if (spi_byte_begin) begin
next_state = STATE_WAIT_DONE_READ_RESPONSE;
end else begin
next_state = STATE_WAIT_START_READ_RESPONSE;
end
end else begin
next_state = STATE_IDLE;
end
end // case: STATE_WAIT_START_READ_RESPONSE
STATE_WAIT_DONE_READ_RESPONSE: begin
if (!nCS) begin
if (spi_byte_done) begin
first = 1;
next_state = STATE_READ_INCREMENT_ADDRESS;
end else begin
next_state = STATE_WAIT_DONE_READ_RESPONSE;
end
end else begin
next_state = STATE_IDLE;
end
end // case: STATE_WAIT_DONE_READ_RESPONSE
STATE_READ_INCREMENT_ADDRESS: begin
if (nCS) begin
next_state = STATE_IDLE;
end else begin
if (first) begin
address = address + 1;
first = 0;
end
next_state = STATE_WAIT_START_READ_RESPONSE;
end
end
STATE_WAIT_START_FIFO_READ_LOW: begin
if (nCS) begin
next_state = STATE_IDLE;
end else begin
read_data_fifo = 0;
spi_data_out = data_fifo_read[7:0];
next_state = STATE_WAIT_START_FIFO_RESPONSE_LOW;
end
end
STATE_WAIT_START_FIFO_RESPONSE_LOW: begin
if (nCS) begin
next_state = STATE_IDLE;
end else begin
if (spi_byte_begin) begin
next_state = STATE_WAIT_DONE_FIFO_RESPONSE_LOW;
end else begin
next_state = STATE_WAIT_START_FIFO_RESPONSE_LOW;
end
end
end
STATE_WAIT_DONE_FIFO_RESPONSE_LOW:begin
if (nCS) begin
next_state = STATE_IDLE;
end else if (spi_byte_done) begin
next_state = STATE_WAIT_START_FIFO_READ_HIGH;
end else begin
next_state = STATE_WAIT_DONE_FIFO_RESPONSE_LOW;
end
end
STATE_WAIT_START_FIFO_READ_HIGH:begin
if (nCS) begin
next_state = STATE_IDLE;
end else begin
read_data_fifo = 0;
spi_data_out = data_fifo_read[15:08];
next_state = STATE_WAIT_START_FIFO_RESPONSE_HIGH;
end
end
STATE_WAIT_START_FIFO_RESPONSE_HIGH: begin
if (nCS) begin
next_state = STATE_IDLE;
end else if (spi_byte_begin) begin
next_state = STATE_WAIT_DONE_FIFO_RESPONSE_HIGH;
end else begin
next_state = STATE_WAIT_START_FIFO_RESPONSE_HIGH;
end
end
STATE_WAIT_DONE_FIFO_RESPONSE_HIGH:begin
if (nCS) begin
next_state = STATE_IDLE;
end else if (spi_byte_done) begin
next_state = STATE_POP_FIFO;
end else begin
next_state = STATE_WAIT_DONE_FIFO_RESPONSE_HIGH;
end
end
STATE_POP_FIFO:begin
if (nCS) begin
next_state = STATE_IDLE;
end else begin
read_data_fifo = 1;
next_state = STATE_WAIT_START_FIFO_READ_LOW;
end
end
default: begin
next_state = STATE_IDLE;
end
endcase // case (state)
end
reg [(40*8)-1:0] state_name =0;
always @(*)
case (state)
STATE_IDLE: state_name = "IDLE";
STATE_WAIT_START_FIFO_READ_LOW: state_name = "START FIFO READ LOW";
STATE_WAIT_START_ADDRESS : state_name = "WAIT START ADDRESS";
STATE_READ_ADDRESS : state_name = "READ ADDRESS";
STATE_WAIT_START_DATA: state_name = "WAIT START DATA";
STATE_WAIT_START_READ_RESPONSE : state_name = "WAIT START READ";
STATE_READ_DATA : state_name = "READ DATA";
STATE_WRITE_REGISTER : state_name = "WRITE REGISTER";
STATE_WRITE_REGISTER_DONE : state_name = "WRITE REGISTER DONE";
STATE_WRITE_INCREMENT_ADDRESS : state_name = "WRITE INCREMENT ADDRESS";
STATE_WAIT_DONE_READ_RESPONSE: state_name = "DONE READ RESPONSE";
STATE_READ_INCREMENT_ADDRESS: state_name = "READ INCREMENT ADDRESS";
STATE_WAIT_START_FIFO_RESPONSE_LOW: state_name = "START FIFO RESPONSE LOW";
STATE_WAIT_DONE_FIFO_RESPONSE_LOW : state_name = "WAIT DONE FIFO RESPONSE LOW";
STATE_WAIT_START_FIFO_RESPONSE_HIGH: state_name = "START FIFO RESPONSE HIGH";
STATE_WAIT_DONE_FIFO_RESPONSE_HIGH : state_name = "WAIT DONE FIFO RESPONSE HIGH";
STATE_POP_FIFO: state_name = "POP FIFO";
default: state_name = "DEFAULT!";
endcase // case (state)
endmodule // adxl362_spi
|
module servo
#(
parameter WIDTH = 16, ///< Width of position word. Should be 2-16 bits
parameter NUM = 1 ///< Number of servos to drive
) (
input clk50Mhz, ///< Built around a 50 MHz clock
input rst, ///< Reset, active high
input [(WIDTH*NUM)-1:0] posArray, ///< Flattened position array
output reg [NUM-1:0] pwm ///< PWM for hobby servos
);
wire [WIDTH-1:0] posArrayInternal[NUM-1:0];
reg [19:0] counter;
integer i;
genvar j;
// Create internal array of positions
generate
begin
for (j=0; j<NUM; j=j+1) begin
assign posArrayInternal[j] = posArray[(WIDTH*(j+1)-1):(WIDTH*j)];
end
end
endgenerate
// PWM based on single timer
always @(posedge clk50Mhz) begin
if (rst) begin
counter <= 'd0;
pwm <= 'b0;
end else begin
counter <= counter + 1;
for (i=0; i<NUM; i=i+1) begin
// 42232 centers PWM on 1.5ms when pos is half of full possible value
// Shift if necessary so that the pos word always creates PWM between 1-2 ms
if (((posArrayInternal[i] << (16-WIDTH)) + 42232) > counter)
pwm[i] <= 1'b1;
else
pwm[i] <= 1'b0;
end
end
end
endmodule
|
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: March, 9th 2017
*/
`timescale 1ns / 1ps
/*
input sampling rate must be the same as clk frequency
interpolate input signal accordingly to get the
right sampling rate.
Refer to sigmadelta.ods to see how the internal width (int_w)
was determined.
*/
module jt12_dac2 #(parameter width=12)
(
input clk,
input rst,
input signed [width-1:0] din,
output reg dout
);
localparam int_w = width+5;
reg [int_w-1:0] y, error, error_1, error_2;
wire [width-1:0] undin = { ~din[width-1], din[width-2:0] };
always @(*) begin
y = undin + { error_1, 1'b0} - error_2;
dout = ~y[int_w-1];
error = y - {dout, {width{1'b0}}};
end
always @(posedge clk)
if( rst ) begin
error_1 <= {int_w{1'b0}};
error_2 <= {int_w{1'b0}};
end else begin
error_1 <= error;
error_2 <= error_1;
end
endmodule
|
/*
-- ============================================================================
-- FILE NAME : uart_ctrl.v
-- DESCRIPTION : UARTÖÆÓù¥â¥¸¥å©`¥ë
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹²Í¨¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** e¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "uart.h"
/********** ¥â¥¸¥å©`¥ë **********/
module uart_ctrl (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire cs_, // ¥Á¥Ã¥×¥»¥ì¥¯¥È
input wire as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
input wire rw, // Read / Write
input wire [`UartAddrBus] addr, // ¥¢¥É¥ì¥¹
input wire [`WordDataBus] wr_data, // ø¤Þz¤ß¥Ç©`¥¿
output reg [`WordDataBus] rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
output reg rdy_, // ¥ì¥Ç¥£
/********** ¸î¤êÞz¤ß **********/
output reg irq_rx, // ÊÜÐÅÍêÁ˸î¤êÞz¤ß£¨ÖÆÓù¥ì¥¸¥¹¥¿ 0£©
output reg irq_tx, // ËÍÐÅÍêÁ˸î¤êÞz¤ß£¨ÖÆÓù¥ì¥¸¥¹¥¿ 0£©
/********** ÖÆÓùÐźŠ**********/
// ÊÜÐÅÖÆÓù
input wire rx_busy, // ÊÜÐÅÖХե饰£¨ÖÆÓù¥ì¥¸¥¹¥¿ 0£©
input wire rx_end, // ÊÜÐÅÍêÁËÐźÅ
input wire [`ByteDataBus] rx_data, // ÊÜÐťǩ`¥¿
// ËÍÐÅÖÆÓù
input wire tx_busy, // ËÍÐÅÖХե饰£¨ÖÆÓù¥ì¥¸¥¹¥¿ 0£©
input wire tx_end, // ËÍÐÅÍêÁËÐźÅ
output reg tx_start, // ËÍÐÅé_ʼÐźÅ
output reg [`ByteDataBus] tx_data // ËÍÐťǩ`¥¿
);
/********** ÖÆÓù¥ì¥¸¥Ä¥¿ **********/
// ÖÆÓù¥ì¥¸¥¹¥¿ 1 : ËÍÊÜÐťǩ`¥¿
reg [`ByteDataBus] rx_buf; // ÊÜÐťХåե¡
/********** UARTÖÆÓùÕÀí **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* ·ÇͬÆڥꥻ¥Ã¥È */
rd_data <= #1 `WORD_DATA_W'h0;
rdy_ <= #1 `DISABLE_;
irq_rx <= #1 `DISABLE;
irq_tx <= #1 `DISABLE;
rx_buf <= #1 `BYTE_DATA_W'h0;
tx_start <= #1 `DISABLE;
tx_data <= #1 `BYTE_DATA_W'h0;
end else begin
/* ¥ì¥Ç¥£¤ÎÉú³É */
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_)) begin
rdy_ <= #1 `ENABLE_;
end else begin
rdy_ <= #1 `DISABLE_;
end
/* Õi¤ß³ö¤·¥¢¥¯¥»¥¹ */
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && (rw == `READ)) begin
case (addr)
`UART_ADDR_STATUS : begin // ÖÆÓù¥ì¥¸¥¹¥¿ 0
rd_data <= #1 {{`WORD_DATA_W-4{1'b0}},
tx_busy, rx_busy, irq_tx, irq_rx};
end
`UART_ADDR_DATA : begin // ÖÆÓù¥ì¥¸¥¹¥¿ 1
rd_data <= #1 {{`BYTE_DATA_W*2{1'b0}}, rx_buf};
end
endcase
end else begin
rd_data <= #1 `WORD_DATA_W'h0;
end
/* ø¤Þz¤ß¥¢¥¯¥»¥¹ */
// ÖÆÓù¥ì¥¸¥¹¥¿ 0 : ËÍÐÅÍêÁ˸î¤êÞz¤ß
if (tx_end == `ENABLE) begin
irq_tx<= #1 `ENABLE;
end else if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) &&
(rw == `WRITE) && (addr == `UART_ADDR_STATUS)) begin
irq_tx<= #1 wr_data[`UartCtrlIrqTx];
end
// ÖÆÓù¥ì¥¸¥¹¥¿ 0 : ÊÜÐÅÍêÁ˸î¤êÞz¤ß
if (rx_end == `ENABLE) begin
irq_rx<= #1 `ENABLE;
end else if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) &&
(rw == `WRITE) && (addr == `UART_ADDR_STATUS)) begin
irq_rx<= #1 wr_data[`UartCtrlIrqRx];
end
// ÖÆÓù¥ì¥¸¥¹¥¿ 1
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) &&
(rw == `WRITE) && (addr == `UART_ADDR_DATA)) begin // ËÍÐÅé_ʼ
tx_start <= #1 `ENABLE;
tx_data <= #1 wr_data[`BYTE_MSB:`LSB];
end else begin
tx_start <= #1 `DISABLE;
tx_data <= #1 `BYTE_DATA_W'h0;
end
/* ÊÜÐťǩ`¥¿¤ÎÈ¡¤êÞz¤ß */
if (rx_end == `ENABLE) begin
rx_buf <= #1 rx_data;
end
end
end
endmodule
|
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// Test bench for renderer.
`include "registers.vh"
`include "tile_registers.vh"
`include "sprite_registers.vh"
`define DISPLAY_HCOUNT_WIDTH 10
`define DISPLAY_VCOUNT_WIDTH 10
module Renderer_Test;
reg clk; // System clock
reg reset; // System reset
wire [`DISPLAY_HCOUNT_WIDTH-1:0] h_pos;
wire [`DISPLAY_VCOUNT_WIDTH-1:0] v_pos;
DisplayController #(.HCOUNT_WIDTH(`DISPLAY_HCOUNT_WIDTH),
.VCOUNT_WIDTH(`DISPLAY_VCOUNT_WIDTH))
display(.clk(clk),
.reset(reset),
.v_pos(v_pos),
.h_pos(h_pos));
wire h_sync, v_sync;
reg [127:0] spr_values [255:0];
reg [127:0] spr_data;
reg [127:0] spr_data_reg;
wire [7:0] spr_addr;
wire spr_clk;
// Simulate the reading of sprite RAM.
always @ (posedge spr_clk)
spr_data <= spr_values[spr_addr];
// Renderer
Renderer renderer(.clk(clk),
.reset(reset),
.reg_values(0),
.tile_reg_values(0),
.spr_clk(spr_clk),
.spr_addr(spr_addr),
.spr_data(spr_data),
.h_pos(h_pos),
.v_pos(v_pos),
.h_sync(h_sync),
.v_sync(v_sync));
// Generate clock.
always
#1 clk = ~clk;
integer i;
integer stage = 0;
initial begin
clk = 0;
reset = 0;
// Reset
#5 reset = 1;
#1 reset = 0;
// Set up sprite register values.
for (i = 0; i < `NUM_SPRITES; i = i + 1) begin
if (i < 4) begin
// Enable the first four registers.
spr_values[i * 2] = 1 | ((15-i)) << 16;
// Also give them x/y offsets.
spr_values[i * 2 + 1] = (i * 8) | ((i * 8) << 16);
end else begin
spr_values[i * 2] = 0;
spr_values[i * 2 + 1] = 0;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41O_BLACKBOX_V
`define SKY130_FD_SC_MS__A41O_BLACKBOX_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a41o (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41O_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:07:39 12/10/2012
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(
output txd,
input rxd,
input rst,
input clk
);
// 27MHz clock with 115200 baud
wire got_data;
wire[7:0] data;
wire SCLK,MOSI,SSbar;
spim spim(
.clk(clk),
.rst(rst),
.din(data),
.wen(got_data),
.rdy(),
.wdiv(1'b0),
.SCLK(SCLK),
.MOSI(MOSI),
.SSbar(SSbar)
);
wire[7:0] data_out;
wire strobe;
wire rdy;
spis spis(
.clk(clk),
.rst(rst),
.SCLK(SCLK),
.MOSI(MOSI),
.SSbar(SSbar),
.dout(data_out),
.data_present(strobe),
.rd(strobe)
);
uart UART0(
.clk(clk),
.rst(rst),
.txd(txd),
.rxd(rxd),
.wr(strobe),
.din(data_out), //data_out
.rdy(rdy),
.dout(data),
.valid(got_data),
.rd(got_data)
);
endmodule
|
// BF2HW
// Copyright (C) 2017 Christian Fibich
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// Toplevel module instantiating BAMBU generated hardware
//
module bf2hw_top(input clk12, input SERIAL_RX, output SERIAL_TX);
`define D_BAUD_FREQ 12'd4
`define D_BAUD_LIMIT 16'd621
wire TX_BUSY;
wire TX_WRITE;
wire RX_VALID;
wire [7:0] RX_DATA;
wire [7:0] TX_DATA;
wire TX_READY;
wire clock; // 24 MHz clock generated by the PLL
wire locked;
wire reset;
reg [2:0] reset_sync;
assign TX_READY = ~TX_BUSY;
pll the_pll (.clock_in(clk12), .clock_out(clock), .locked(locked));
assign reset = reset_sync[2];
initial begin
reset_sync <= 3'b11;
end
always @(posedge clock or negedge locked) begin
if (locked == 1'b0) begin
reset_sync <= 3'b11;
end else begin
reset_sync <= {reset_sync[1:0],1'b0};
end
end
uart_top uart (.clock(clock), .reset(reset),.ser_in(SERIAL_RX), .ser_out(SERIAL_TX),
.rx_data(RX_DATA), .new_rx_data(RX_VALID),
.tx_data(TX_DATA), .new_tx_data(TX_WRITE), .tx_busy(TX_BUSY),
.baud_freq(`D_BAUD_FREQ), .baud_limit(`D_BAUD_LIMIT),
.baud_clk()
);
main_minimal_interface main(.clock(clock), .reset(reset),
.start_port(1'b1), .RX_VALID(RX_VALID), .RX_DATA(RX_DATA),
.TX_READY(TX_READY), .done_port(), .return_port(),
.TX_ENABLE(TX_WRITE), .TX_DATA(TX_DATA));
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
// Date : Mon Nov 03 20:56:59 2014
// Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// C:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/half_band_FIR/half_band_FIR_stub.v
// Design : half_band_FIR
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fir_compiler_v7_1,Vivado 2014.2" *)
module half_band_FIR(aclk, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[23:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */;
input aclk;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [23:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [23:0]m_axis_data_tdata;
endmodule
|
`default_nettype none
// ============================================================================
module comparator #
(
parameter WIDTH = 8,
parameter ERROR_COUNT = 8,
parameter ERROR_HOLD = 2500000
)
(
// Clock and reset
input wire CLK,
input wire RST,
// Transmitted data input port
input wire TX_STB,
input wire [WIDTH-1:0] TX_DAT,
// Received data input port + bitslip
input wire RX_STB,
input wire [WIDTH-1:0] RX_DAT,
output wire RX_BITSLIP,
// Error indicator
output wire O_ERROR
);
// ============================================================================
// Data latch and comparator
reg [WIDTH-1:0] tx_dat;
reg tx_valid;
reg [WIDTH-1:0] rx_dat;
reg rx_valid;
wire i_rdy = rx_valid && rx_valid;
always @(posedge CLK)
if (!tx_valid && TX_STB)
tx_dat <= TX_DAT;
always @(posedge CLK)
if (RST)
tx_valid <= 1'b0;
else if (i_rdy)
tx_valid <= 1'b0;
else if (TX_STB)
tx_valid <= 1'b1;
always @(posedge CLK)
if (!rx_valid && RX_STB)
rx_dat <= RX_DAT;
always @(posedge CLK)
if (RST)
rx_valid <= 1'b0;
else if (i_rdy)
rx_valid <= 1'b0;
else if (RX_STB)
rx_valid <= 1'b1;
reg x_stb;
reg x_error;
always @(posedge CLK)
if (RST)
x_stb <= 1'b0;
else if(!x_stb && i_rdy)
x_stb <= 1'b1;
else if( x_stb)
x_stb <= 1'b0;
always @(posedge CLK)
if (i_rdy)
x_error <= (rx_dat != tx_dat);
// ============================================================================
// Error counter and bitslip generator
reg [31:0] count_err;
reg o_bitslip;
always @(posedge CLK)
if (RST)
count_err <= 0;
else if (x_stb && x_error)
count_err <= count_err + 1;
else if (o_bitslip)
count_err <= 0;
always @(posedge CLK)
if (RST)
o_bitslip <= 1'b0;
else if (!o_bitslip && (count_err >= ERROR_COUNT))
o_bitslip <= 1'b1;
else if ( o_bitslip)
o_bitslip <= 1'b0;
assign RX_BITSLIP = o_bitslip;
// ============================================================================
// Error output
reg [32:0] o_cnt;
always @(posedge CLK)
if (RST)
o_cnt <= 0;
else if (x_stb && x_error)
o_cnt <= ERROR_HOLD;
else
o_cnt <= (o_cnt[32]) ? o_cnt : (o_cnt - 1);
assign O_ERROR = !o_cnt[32];
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Euclidean Division for integers, Euclid convention
We use here the "usual" formulation of the Euclid Theorem
[forall a b, b<>0 -> exists b q, a = b*q+r /\ 0 < r < |b| ]
The outcome of the modulo function is hence always positive.
This corresponds to convention "E" in the following paper:
R. Boute, "The Euclidean definition of the functions div and mod",
ACM Transactions on Programming Languages and Systems,
Vol. 14, No.2, pp. 127-144, April 1992.
See files [ZDivTrunc] and [ZDivFloor] for others conventions.
*)
Require Import ZAxioms ZProperties NZDiv.
Module Type ZDivSpecific (Import Z : ZAxiomsExtSig')(Import DM : DivMod' Z).
Axiom mod_always_pos : forall a b, 0 <= a mod b < abs b.
End ZDivSpecific.
Module Type ZDiv (Z:ZAxiomsExtSig)
:= DivMod Z <+ NZDivCommon Z <+ ZDivSpecific Z.
Module Type ZDivSig := ZAxiomsExtSig <+ ZDiv.
Module Type ZDivSig' := ZAxiomsExtSig' <+ ZDiv <+ DivModNotation.
Module ZDivPropFunct (Import Z : ZDivSig')(Import ZP : ZPropSig Z).
(** We benefit from what already exists for NZ *)
Module ZD <: NZDiv Z.
Definition div := div.
Definition modulo := modulo.
Definition div_wd := div_wd.
Definition mod_wd := mod_wd.
Definition div_mod := div_mod.
Lemma mod_bound : forall a b, 0<=a -> 0<b -> 0 <= a mod b < b.
Proof.
intros. rewrite <- (abs_eq b) at 3 by now apply lt_le_incl.
apply mod_always_pos.
Qed.
End ZD.
Module Import NZDivP := NZDivPropFunct Z ZP ZD.
(** Another formulation of the main equation *)
Lemma mod_eq :
forall a b, b~=0 -> a mod b == a - b*(a/b).
Proof.
intros.
rewrite <- add_move_l.
symmetry. now apply div_mod.
Qed.
Ltac pos_or_neg a :=
let LT := fresh "LT" in
let LE := fresh "LE" in
destruct (le_gt_cases 0 a) as [LE|LT]; [|rewrite <- opp_pos_neg in LT].
(** Uniqueness theorems *)
Theorem div_mod_unique : forall b q1 q2 r1 r2 : t,
0<=r1<abs b -> 0<=r2<abs b ->
b*q1+r1 == b*q2+r2 -> q1 == q2 /\ r1 == r2.
Proof.
intros b q1 q2 r1 r2 Hr1 Hr2 EQ.
pos_or_neg b.
rewrite abs_eq in * by trivial.
apply div_mod_unique with b; trivial.
rewrite abs_neq' in * by auto using lt_le_incl.
rewrite eq_sym_iff. apply div_mod_unique with (-b); trivial.
rewrite 2 mul_opp_l.
rewrite add_move_l, sub_opp_r.
rewrite <-add_assoc.
symmetry. rewrite add_move_l, sub_opp_r.
now rewrite (add_comm r2), (add_comm r1).
Qed.
Theorem div_unique:
forall a b q r, 0<=r<abs b -> a == b*q + r -> q == a/b.
Proof.
intros a b q r Hr EQ.
assert (Hb : b~=0).
pos_or_neg b.
rewrite abs_eq in Hr; intuition; order.
rewrite <- opp_0, eq_opp_r. rewrite abs_neq' in Hr; intuition; order.
destruct (div_mod_unique b q (a/b) r (a mod b)); trivial.
now apply mod_always_pos.
now rewrite <- div_mod.
Qed.
Theorem mod_unique:
forall a b q r, 0<=r<abs b -> a == b*q + r -> r == a mod b.
Proof.
intros a b q r Hr EQ.
assert (Hb : b~=0).
pos_or_neg b.
rewrite abs_eq in Hr; intuition; order.
rewrite <- opp_0, eq_opp_r. rewrite abs_neq' in Hr; intuition; order.
destruct (div_mod_unique b q (a/b) r (a mod b)); trivial.
now apply mod_always_pos.
now rewrite <- div_mod.
Qed.
(** Sign rules *)
Lemma div_opp_r : forall a b, b~=0 -> a/(-b) == -(a/b).
Proof.
intros. symmetry.
apply div_unique with (a mod b).
rewrite abs_opp; apply mod_always_pos.
rewrite mul_opp_opp; now apply div_mod.
Qed.
Lemma mod_opp_r : forall a b, b~=0 -> a mod (-b) == a mod b.
Proof.
intros. symmetry.
apply mod_unique with (-(a/b)).
rewrite abs_opp; apply mod_always_pos.
rewrite mul_opp_opp; now apply div_mod.
Qed.
Lemma div_opp_l_z : forall a b, b~=0 -> a mod b == 0 ->
(-a)/b == -(a/b).
Proof.
intros a b Hb Hab. symmetry.
apply div_unique with (-(a mod b)).
rewrite Hab, opp_0. split; [order|].
pos_or_neg b; [rewrite abs_eq | rewrite abs_neq']; order.
now rewrite mul_opp_r, <-opp_add_distr, <-div_mod.
Qed.
Lemma div_opp_l_nz : forall a b, b~=0 -> a mod b ~= 0 ->
(-a)/b == -(a/b)-sgn b.
Proof.
intros a b Hb Hab. symmetry.
apply div_unique with (abs b -(a mod b)).
rewrite lt_sub_lt_add_l.
rewrite <- le_add_le_sub_l. nzsimpl.
rewrite <- (add_0_l (abs b)) at 2.
rewrite <- add_lt_mono_r.
destruct (mod_always_pos a b); intuition order.
rewrite <- 2 add_opp_r, mul_add_distr_l, 2 mul_opp_r.
rewrite sgn_abs.
rewrite add_shuffle2, add_opp_diag_l; nzsimpl.
rewrite <-opp_add_distr, <-div_mod; order.
Qed.
Lemma mod_opp_l_z : forall a b, b~=0 -> a mod b == 0 ->
(-a) mod b == 0.
Proof.
intros a b Hb Hab. symmetry.
apply mod_unique with (-(a/b)).
split; [order|now rewrite abs_pos].
now rewrite <-opp_0, <-Hab, mul_opp_r, <-opp_add_distr, <-div_mod.
Qed.
Lemma mod_opp_l_nz : forall a b, b~=0 -> a mod b ~= 0 ->
(-a) mod b == abs b - (a mod b).
Proof.
intros a b Hb Hab. symmetry.
apply mod_unique with (-(a/b)-sgn b).
rewrite lt_sub_lt_add_l.
rewrite <- le_add_le_sub_l. nzsimpl.
rewrite <- (add_0_l (abs b)) at 2.
rewrite <- add_lt_mono_r.
destruct (mod_always_pos a b); intuition order.
rewrite <- 2 add_opp_r, mul_add_distr_l, 2 mul_opp_r.
rewrite sgn_abs.
rewrite add_shuffle2, add_opp_diag_l; nzsimpl.
rewrite <-opp_add_distr, <-div_mod; order.
Qed.
Lemma div_opp_opp_z : forall a b, b~=0 -> a mod b == 0 ->
(-a)/(-b) == a/b.
Proof.
intros. now rewrite div_opp_r, div_opp_l_z, opp_involutive.
Qed.
Lemma div_opp_opp_nz : forall a b, b~=0 -> a mod b ~= 0 ->
(-a)/(-b) == a/b + sgn(b).
Proof.
intros. rewrite div_opp_r, div_opp_l_nz by trivial.
now rewrite opp_sub_distr, opp_involutive.
Qed.
Lemma mod_opp_opp_z : forall a b, b~=0 -> a mod b == 0 ->
(-a) mod (-b) == 0.
Proof.
intros. now rewrite mod_opp_r, mod_opp_l_z.
Qed.
Lemma mod_opp_opp_nz : forall a b, b~=0 -> a mod b ~= 0 ->
(-a) mod (-b) == abs b - a mod b.
Proof.
intros. now rewrite mod_opp_r, mod_opp_l_nz.
Qed.
(** A division by itself returns 1 *)
Lemma div_same : forall a, a~=0 -> a/a == 1.
Proof.
intros. symmetry. apply div_unique with 0.
split; [order|now rewrite abs_pos].
now nzsimpl.
Qed.
Lemma mod_same : forall a, a~=0 -> a mod a == 0.
Proof.
intros.
rewrite mod_eq, div_same by trivial. nzsimpl. apply sub_diag.
Qed.
(** A division of a small number by a bigger one yields zero. *)
Theorem div_small: forall a b, 0<=a<b -> a/b == 0.
Proof. exact div_small. Qed.
(** Same situation, in term of modulo: *)
Theorem mod_small: forall a b, 0<=a<b -> a mod b == a.
Proof. exact mod_small. Qed.
(** * Basic values of divisions and modulo. *)
Lemma div_0_l: forall a, a~=0 -> 0/a == 0.
Proof.
intros. pos_or_neg a. apply div_0_l; order.
apply opp_inj. rewrite <- div_opp_r, opp_0 by trivial. now apply div_0_l.
Qed.
Lemma mod_0_l: forall a, a~=0 -> 0 mod a == 0.
Proof.
intros; rewrite mod_eq, div_0_l; now nzsimpl.
Qed.
Lemma div_1_r: forall a, a/1 == a.
Proof.
intros. symmetry. apply div_unique with 0.
assert (H:=lt_0_1); rewrite abs_pos; intuition; order.
now nzsimpl.
Qed.
Lemma mod_1_r: forall a, a mod 1 == 0.
Proof.
intros. rewrite mod_eq, div_1_r; nzsimpl; auto using sub_diag.
apply neq_sym, lt_neq; apply lt_0_1.
Qed.
Lemma div_1_l: forall a, 1<a -> 1/a == 0.
Proof. exact div_1_l. Qed.
Lemma mod_1_l: forall a, 1<a -> 1 mod a == 1.
Proof. exact mod_1_l. Qed.
Lemma div_mul : forall a b, b~=0 -> (a*b)/b == a.
Proof.
intros. symmetry. apply div_unique with 0.
split; [order|now rewrite abs_pos].
nzsimpl; apply mul_comm.
Qed.
Lemma mod_mul : forall a b, b~=0 -> (a*b) mod b == 0.
Proof.
intros. rewrite mod_eq, div_mul by trivial. rewrite mul_comm; apply sub_diag.
Qed.
(** * Order results about mod and div *)
(** A modulo cannot grow beyond its starting point. *)
Theorem mod_le: forall a b, 0<=a -> b~=0 -> a mod b <= a.
Proof.
intros. pos_or_neg b. apply mod_le; order.
rewrite <- mod_opp_r by trivial. apply mod_le; order.
Qed.
Theorem div_pos : forall a b, 0<=a -> 0<b -> 0<= a/b.
Proof. exact div_pos. Qed.
Lemma div_str_pos : forall a b, 0<b<=a -> 0 < a/b.
Proof. exact div_str_pos. Qed.
Lemma div_small_iff : forall a b, b~=0 -> (a/b==0 <-> 0<=a<abs b).
Proof.
intros a b Hb.
split.
intros EQ.
rewrite (div_mod a b Hb), EQ; nzsimpl.
apply mod_always_pos.
intros. pos_or_neg b.
apply div_small.
now rewrite <- (abs_eq b).
apply opp_inj; rewrite opp_0, <- div_opp_r by trivial.
apply div_small.
rewrite <- (abs_neq' b) by order. trivial.
Qed.
Lemma mod_small_iff : forall a b, b~=0 -> (a mod b == a <-> 0<=a<abs b).
Proof.
intros.
rewrite <- div_small_iff, mod_eq by trivial.
rewrite sub_move_r, <- (add_0_r a) at 1. rewrite add_cancel_l.
rewrite eq_sym_iff, eq_mul_0. tauto.
Qed.
(** As soon as the divisor is strictly greater than 1,
the division is strictly decreasing. *)
Lemma div_lt : forall a b, 0<a -> 1<b -> a/b < a.
Proof. exact div_lt. Qed.
(** [le] is compatible with a positive division. *)
Lemma div_le_mono : forall a b c, 0<c -> a<=b -> a/c <= b/c.
Proof.
intros a b c Hc Hab.
rewrite lt_eq_cases in Hab. destruct Hab as [LT|EQ];
[|rewrite EQ; order].
rewrite <- lt_succ_r.
rewrite (mul_lt_mono_pos_l c) by order.
nzsimpl.
rewrite (add_lt_mono_r _ _ (a mod c)).
rewrite <- div_mod by order.
apply lt_le_trans with b; trivial.
rewrite (div_mod b c) at 1 by order.
rewrite <- add_assoc, <- add_le_mono_l.
apply le_trans with (c+0).
nzsimpl; destruct (mod_always_pos b c); try order.
rewrite abs_eq in *; order.
rewrite <- add_le_mono_l. destruct (mod_always_pos a c); order.
Qed.
(** In this convention, [div] performs Rounding-Toward-Bottom
when divisor is positive, and Rounding-Toward-Top otherwise.
Since we cannot speak of rational values here, we express this
fact by multiplying back by [b], and this leads to a nice
unique statement.
*)
Lemma mul_div_le : forall a b, b~=0 -> b*(a/b) <= a.
Proof.
intros.
rewrite (div_mod a b) at 2; trivial.
rewrite <- (add_0_r (b*(a/b))) at 1.
rewrite <- add_le_mono_l.
now destruct (mod_always_pos a b).
Qed.
(** Giving a reversed bound is slightly more complex *)
Lemma mul_succ_div_gt: forall a b, 0<b -> a < b*(S (a/b)).
Proof.
intros.
nzsimpl.
rewrite (div_mod a b) at 1; try order.
rewrite <- add_lt_mono_l.
destruct (mod_always_pos a b).
rewrite abs_eq in *; order.
Qed.
Lemma mul_pred_div_gt: forall a b, b<0 -> a < b*(P (a/b)).
Proof.
intros a b Hb.
rewrite mul_pred_r, <- add_opp_r.
rewrite (div_mod a b) at 1; try order.
rewrite <- add_lt_mono_l.
destruct (mod_always_pos a b).
rewrite <- opp_pos_neg in Hb. rewrite abs_neq' in *; order.
Qed.
(** NB: The three previous properties could be used as
specifications for [div]. *)
(** Inequality [mul_div_le] is exact iff the modulo is zero. *)
Lemma div_exact : forall a b, b~=0 -> (a == b*(a/b) <-> a mod b == 0).
Proof.
intros.
rewrite (div_mod a b) at 1; try order.
rewrite <- (add_0_r (b*(a/b))) at 2.
apply add_cancel_l.
Qed.
(** Some additionnal inequalities about div. *)
Theorem div_lt_upper_bound:
forall a b q, 0<b -> a < b*q -> a/b < q.
Proof.
intros.
rewrite (mul_lt_mono_pos_l b) by trivial.
apply le_lt_trans with a; trivial.
apply mul_div_le; order.
Qed.
Theorem div_le_upper_bound:
forall a b q, 0<b -> a <= b*q -> a/b <= q.
Proof.
intros.
rewrite <- (div_mul q b) by order.
apply div_le_mono; trivial. now rewrite mul_comm.
Qed.
Theorem div_le_lower_bound:
forall a b q, 0<b -> b*q <= a -> q <= a/b.
Proof.
intros.
rewrite <- (div_mul q b) by order.
apply div_le_mono; trivial. now rewrite mul_comm.
Qed.
(** A division respects opposite monotonicity for the divisor *)
Lemma div_le_compat_l: forall p q r, 0<=p -> 0<q<=r -> p/r <= p/q.
Proof. exact div_le_compat_l. Qed.
(** * Relations between usual operations and mod and div *)
Lemma mod_add : forall a b c, c~=0 ->
(a + b * c) mod c == a mod c.
Proof.
intros.
symmetry.
apply mod_unique with (a/c+b); trivial.
now apply mod_always_pos.
rewrite mul_add_distr_l, add_shuffle0, <- div_mod by order.
now rewrite mul_comm.
Qed.
Lemma div_add : forall a b c, c~=0 ->
(a + b * c) / c == a / c + b.
Proof.
intros.
apply (mul_cancel_l _ _ c); try order.
apply (add_cancel_r _ _ ((a+b*c) mod c)).
rewrite <- div_mod, mod_add by order.
rewrite mul_add_distr_l, add_shuffle0, <- div_mod by order.
now rewrite mul_comm.
Qed.
Lemma div_add_l: forall a b c, b~=0 ->
(a * b + c) / b == a + c / b.
Proof.
intros a b c. rewrite (add_comm _ c), (add_comm a).
now apply div_add.
Qed.
(** Cancellations. *)
(** With the current convention, the following isn't always true
when [c<0]: [-3*-1 / -2*-1 = 3/2 = 1] while [-3/-2 = 2] *)
Lemma div_mul_cancel_r : forall a b c, b~=0 -> 0<c ->
(a*c)/(b*c) == a/b.
Proof.
intros.
symmetry.
apply div_unique with ((a mod b)*c).
(* ineqs *)
rewrite abs_mul, (abs_eq c) by order.
rewrite <-(mul_0_l c), <-mul_lt_mono_pos_r, <-mul_le_mono_pos_r by trivial.
apply mod_always_pos.
(* equation *)
rewrite (div_mod a b) at 1 by order.
rewrite mul_add_distr_r.
rewrite add_cancel_r.
rewrite <- 2 mul_assoc. now rewrite (mul_comm c).
Qed.
Lemma div_mul_cancel_l : forall a b c, b~=0 -> 0<c ->
(c*a)/(c*b) == a/b.
Proof.
intros. rewrite !(mul_comm c); now apply div_mul_cancel_r.
Qed.
Lemma mul_mod_distr_l: forall a b c, b~=0 -> 0<c ->
(c*a) mod (c*b) == c * (a mod b).
Proof.
intros.
rewrite <- (add_cancel_l _ _ ((c*b)* ((c*a)/(c*b)))).
rewrite <- div_mod.
rewrite div_mul_cancel_l by trivial.
rewrite <- mul_assoc, <- mul_add_distr_l, mul_cancel_l by order.
apply div_mod; order.
rewrite <- neq_mul_0; intuition; order.
Qed.
Lemma mul_mod_distr_r: forall a b c, b~=0 -> 0<c ->
(a*c) mod (b*c) == (a mod b) * c.
Proof.
intros. rewrite !(mul_comm _ c); now rewrite mul_mod_distr_l.
Qed.
(** Operations modulo. *)
Theorem mod_mod: forall a n, n~=0 ->
(a mod n) mod n == a mod n.
Proof.
intros. rewrite mod_small_iff by trivial.
now apply mod_always_pos.
Qed.
Lemma mul_mod_idemp_l : forall a b n, n~=0 ->
((a mod n)*b) mod n == (a*b) mod n.
Proof.
intros a b n Hn. symmetry.
rewrite (div_mod a n) at 1 by order.
rewrite add_comm, (mul_comm n), (mul_comm _ b).
rewrite mul_add_distr_l, mul_assoc.
rewrite mod_add by trivial.
now rewrite mul_comm.
Qed.
Lemma mul_mod_idemp_r : forall a b n, n~=0 ->
(a*(b mod n)) mod n == (a*b) mod n.
Proof.
intros. rewrite !(mul_comm a). now apply mul_mod_idemp_l.
Qed.
Theorem mul_mod: forall a b n, n~=0 ->
(a * b) mod n == ((a mod n) * (b mod n)) mod n.
Proof.
intros. now rewrite mul_mod_idemp_l, mul_mod_idemp_r.
Qed.
Lemma add_mod_idemp_l : forall a b n, n~=0 ->
((a mod n)+b) mod n == (a+b) mod n.
Proof.
intros a b n Hn. symmetry.
rewrite (div_mod a n) at 1 by order.
rewrite <- add_assoc, add_comm, mul_comm.
now rewrite mod_add.
Qed.
Lemma add_mod_idemp_r : forall a b n, n~=0 ->
(a+(b mod n)) mod n == (a+b) mod n.
Proof.
intros. rewrite !(add_comm a). now apply add_mod_idemp_l.
Qed.
Theorem add_mod: forall a b n, n~=0 ->
(a+b) mod n == (a mod n + b mod n) mod n.
Proof.
intros. now rewrite add_mod_idemp_l, add_mod_idemp_r.
Qed.
(** With the current convention, the following result isn't always
true for negative divisors. For instance
[ 3/(-2)/(-2) = 1 <> 0 = 3 / (-2*-2) ]. *)
Lemma div_div : forall a b c, 0<b -> 0<c ->
(a/b)/c == a/(b*c).
Proof.
intros a b c Hb Hc.
apply div_unique with (b*((a/b) mod c) + a mod b).
(* begin 0<= ... <abs(b*c) *)
rewrite abs_mul.
destruct (mod_always_pos (a/b) c), (mod_always_pos a b).
split.
apply add_nonneg_nonneg; trivial.
apply mul_nonneg_nonneg; order.
apply lt_le_trans with (b*((a/b) mod c) + abs b).
now rewrite <- add_lt_mono_l.
rewrite (abs_eq b) by order.
now rewrite <- mul_succ_r, <- mul_le_mono_pos_l, le_succ_l.
(* end 0<= ... < abs(b*c) *)
rewrite (div_mod a b) at 1 by order.
rewrite add_assoc, add_cancel_r.
rewrite <- mul_assoc, <- mul_add_distr_l, mul_cancel_l by order.
apply div_mod; order.
Qed.
(** A last inequality: *)
Theorem div_mul_le:
forall a b c, 0<=a -> 0<b -> 0<=c -> c*(a/b) <= (c*a)/b.
Proof. exact div_mul_le. Qed.
(** mod is related to divisibility *)
Lemma mod_divides : forall a b, b~=0 ->
(a mod b == 0 <-> exists c, a == b*c).
Proof.
intros a b Hb. split.
intros Hab. exists (a/b). rewrite (div_mod a b Hb) at 1.
rewrite Hab; now nzsimpl.
intros (c,Hc).
rewrite Hc, mul_comm.
now apply mod_mul.
Qed.
End ZDivPropFunct.
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*
*
* @reminder December 1, 2007
* Remember to remove wrbyteen and ctrl_ppp from the inputs to
* the ALU and its testbench
*/
// GOLD VERSION
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/alu.v
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*
* ALU is a combinational logic block without clock signals
*/
`include "control.h"
// Behavioral model for the ALU
module alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result,wrbyteen);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
/**
* Overflow fromn arithmetic operations are ignored; use
* saturating mode for arithmetic operations - cap the value
* at the maximum value.
*
* Also, an output signal to indicate that an overflow has
* occurred will not be provided
*/
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Clock signal
//input clock;
// Control signal bits - ppp
input [0:2] ctrl_ppp;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* Byte-write enable signals: one for each byte of the data
*
* Asserted high when each byte of the address word needs to be
* updated during the write operation
*/
input [15:0] wrbyteen;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// Defining constants: parameter [name_of_constant] = value;
parameter max_128_bits = 128'hffffffffffffffffffffffffffffffff;
//parameter max_128_bits = 128'hfffffffffffffffffffffffffffffffff;
//parameter max_128_bits = 128'h00112233445566778899aabbccddeeff1;
//parameter max_128_bits = 128'h123415678901234567890123456789012;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
// ===============================================================
always @(reg_A or reg_B or ctrl_ppp or ctrl_ww or alu_op or wrbyteen)
begin
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
/**
* In computer science, a logical shift is a shift operator
* that shifts all the bits of its operand. Unlike an
* arithmetic shift, a logical shift does not preserve
* a number's sign bit or distinguish a number's exponent
* from its mantissa; every bit in the operand is simply
* moved a given number of bit positions, and the vacant
* bit-positions are filled in, generally with zeros
* (compare with a circular shift).
*
* SRL,SLL,Srli,sra,srai...
*/
// ================================================
// ======================================================
// SLL instruction << mv to LSB << bit 127
`aluwsll:
begin
case(ctrl_ww)
`w8: // aluwsll AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]<<reg_B[5:7];
result[8:15]<=reg_A[8:15]<<reg_B[13:15];
result[16:23]<=reg_A[16:23]<<reg_B[21:23];
result[24:31]<=reg_A[24:31]<<reg_B[29:31];
result[32:39]<=reg_A[32:39]<<reg_B[37:39];
result[40:47]<=reg_A[40:47]<<reg_B[45:47];
result[48:55]<=reg_A[48:55]<<reg_B[53:55];
result[56:63]<=reg_A[56:63]<<reg_B[61:63];
result[64:71]<=reg_A[64:71]<<reg_B[69:71];
result[72:79]<=reg_A[72:79]<<reg_B[77:79];
result[80:87]<=reg_A[80:87]<<reg_B[85:87];
result[88:95]<=reg_A[88:95]<<reg_B[93:95];
result[96:103]<=reg_A[96:103]<<reg_B[101:103];
result[104:111]<=reg_A[104:111]<<reg_B[109:111];
result[112:119]<=reg_A[112:119]<<reg_B[117:119];
result[120:127]<=reg_A[120:127]<<reg_B[125:127];
end
`w16: // aluwsll AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]<<reg_B[12:15];
result[16:31]<=reg_A[16:31]<<reg_B[28:31];
result[32:47]<=reg_A[32:47]<<reg_B[44:47];
result[48:63]<=reg_A[48:63]<<reg_B[60:63];
result[64:79]<=reg_A[64:79]<<reg_B[76:79];
result[80:95]<=reg_A[80:95]<<reg_B[92:95];
result[96:111]<=reg_A[96:111]<<reg_B[108:111];
result[112:127]<=reg_A[112:127]<<reg_B[124:127];
end
`w32: // aluwsll AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]<<reg_B[27:31];
result[32:63]<=reg_A[32:63]<<reg_B[59:63];
result[64:95]<=reg_A[64:95]<<reg_B[91:95];
result[96:127]<=reg_A[96:127]<<reg_B[123:127];
end
default: // aluwsll AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
/*
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
*/
// ======================================================
// SRL instruction >> mv to MSB >> bit 0
`aluwsrl:
begin
case(ctrl_ppp)
`aa: // aluwsrl AND `aa
begin
case(ctrl_ww)
`w8: // aluwsrl AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default: // aluwsrl AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwsrl AND `uu
begin
case(ctrl_ww)
`w8: // aluwsrl AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
end
`w16: // aluwsrl AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
end
`w32: // aluwsrl AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
end
default:
begin
// aluwsrl AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwsrl AND `dd
begin
case(ctrl_ww)
`w8: // aluwsrl AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwsrl AND `ee
begin
case(ctrl_ww)
`w8: // aluwsrl AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
end
`w16: // aluwsrl AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
end
`w32: // aluwsrl AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
end
default:
begin
// aluwsrl AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwsrl AND `oo
begin
case(ctrl_ww)
`w8: // aluwsrl AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwsrl AND `mm
begin
case(ctrl_ww)
`w8: // aluwsrl AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
end
`w16: // aluwsrl AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
end
`w32: // aluwsrl AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
end
default:
begin
// aluwsrl AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwsrl AND `ll
begin
case(ctrl_ww)
`w8: // aluwsrl AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwsrl AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
// ================================================
// ADD instruction
`aluwadd:
begin
case(ctrl_ppp)
`aa: // aluwadd AND `aa
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwadd AND `uu
begin
case(ctrl_ww)
`w8: // aluwadd AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
end
`w16: // aluwadd AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
end
`w32: // aluwadd AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwadd AND `dd
begin
case(ctrl_ww)
`w8: // aluwadd AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwadd AND `ee
begin
case(ctrl_ww)
`w8: // aluwadd AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
end
`w16: // aluwadd AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
end
`w32: // aluwadd AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
end
default:
begin
// aluwadd AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwadd AND `oo
begin
case(ctrl_ww)
`w8: // aluwadd AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwadd AND `mm
begin
case(ctrl_ww)
`w8: // aluwadd AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
end
`w16: // aluwadd AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
end
`w32: // aluwadd AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
end
default:
begin
// aluwadd AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwadd AND `ll
begin
case(ctrl_ww)
`w8: // aluwadd AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwadd AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// AND instruction
`aluwand:
begin
case(ctrl_ppp)
`aa: // aluwand AND `aa
begin
case(ctrl_ww)
`w8: // aluwand AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default: // aluwand AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwand AND `uu
begin
case(ctrl_ww)
`w8: // aluwand AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
end
`w16: // aluwand AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
end
`w32: // aluwand AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
end
default:
begin
// aluwand AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwand AND `dd
begin
case(ctrl_ww)
`w8: // aluwand AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwand AND `ee
begin
case(ctrl_ww)
`w8: // aluwand AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[112:119]<=reg_A[112:119]®_B[112:119];
end
`w16: // aluwand AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[96:111]<=reg_A[96:111]®_B[96:111];
end
`w32: // aluwand AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[64:95]<=reg_A[64:95]®_B[64:95];
end
default:
begin
// aluwand AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwand AND `oo
begin
case(ctrl_ww)
`w8: // aluwand AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]®_B[8:15];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]®_B[16:31];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]®_B[32:63];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwand AND `mm
begin
case(ctrl_ww)
`w8: // aluwand AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
end
`w16: // aluwand AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
end
`w32: // aluwand AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
end
default:
begin
// aluwand AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwand AND `ll
begin
case(ctrl_ww)
`w8: // aluwand AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwand AND Default
begin
result<=128'd0;
end
endcase
end
// ==============================================
// ================================================
// NOT instruction
`aluwnot:
begin
case(ctrl_ppp)
`aa: // aluwnot AND `aa
begin
case(ctrl_ww)
`w8: // aluwnot AND `aa AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `aa AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `aa AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default: // aluwnot AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwnot AND `uu
begin
case(ctrl_ww)
`w8: // aluwnot AND `uu AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
end
`w16: // aluwnot AND `uu AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
end
`w32: // aluwnot AND `uu AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
end
default:
begin
// aluwnot AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwnot AND `dd
begin
case(ctrl_ww)
`w8: // aluwnot AND `dd AND `w8
begin
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `dd AND `w16
begin
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `dd AND `w32
begin
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwnot AND `ee
begin
case(ctrl_ww)
`w8: // aluwnot AND `ee AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[16:23]<=~reg_A[16:23];
result[32:39]<=~reg_A[32:39];
result[48:55]<=~reg_A[48:55];
result[64:71]<=~reg_A[64:71];
result[80:87]<=~reg_A[80:87];
result[96:103]<=~reg_A[96:103];
result[112:119]<=~reg_A[112:119];
end
`w16: // aluwnot AND `ee AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[32:47]<=~reg_A[32:47];
result[64:79]<=~reg_A[64:79];
result[96:111]<=~reg_A[96:111];
end
`w32: // aluwnot AND `ee AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[64:95]<=~reg_A[64:95];
end
default:
begin
// aluwnot AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwnot AND `oo
begin
case(ctrl_ww)
`w8: // aluwnot AND `oo AND `w8
begin
result[8:15]<=~reg_A[8:15];
result[24:31]<=~reg_A[24:31];
result[40:47]<=~reg_A[40:47];
result[56:63]<=~reg_A[56:63];
result[72:79]<=~reg_A[72:79];
result[88:95]<=~reg_A[88:95];
result[104:111]<=~reg_A[104:111];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `oo AND `w16
begin
result[16:31]<=~reg_A[16:31];
result[48:63]<=~reg_A[48:63];
result[80:95]<=~reg_A[80:95];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `oo AND `w32
begin
result[32:63]<=~reg_A[32:63];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwnot AND `mm
begin
case(ctrl_ww)
`w8: // aluwnot AND `mm AND `w8
begin
result[0:7]<=~reg_A[0:7];
end
`w16: // aluwnot AND `mm AND `w16
begin
result[0:15]<=~reg_A[0:15];
end
`w32: // aluwnot AND `mm AND `w32
begin
result[0:31]<=~reg_A[0:31];
end
default:
begin
// aluwnot AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwnot AND `ll
begin
case(ctrl_ww)
`w8: // aluwnot AND `ll AND `w8
begin
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `ll AND `w16
begin
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `ll AND `w32
begin
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwnot AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// OR instruction
`aluwor:
begin
case(ctrl_ppp)
`aa: // aluwor AND `aa
begin
case(ctrl_ww)
`w8: // aluwor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default: // aluwor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwor AND `uu
begin
case(ctrl_ww)
`w8: // aluwor AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
end
`w16: // aluwor AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
end
`w32: // aluwor AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
end
default:
begin
// aluwor AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwor AND `dd
begin
case(ctrl_ww)
`w8: // aluwor AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwor AND `ee
begin
case(ctrl_ww)
`w8: // aluwor AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
end
`w16: // aluwor AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
end
`w32: // aluwor AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
end
default:
begin
// aluwor AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwor AND `oo
begin
case(ctrl_ww)
`w8: // aluwor AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwor AND `mm
begin
case(ctrl_ww)
`w8: // aluwor AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
end
`w16: // aluwor AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
end
`w32: // aluwor AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
end
default:
begin
// aluwor AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwor AND `ll
begin
case(ctrl_ww)
`w8: // aluwor AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwor AND Default
begin
result<=128'd0;
end
endcase
end
// ========================================================
// XOR instruction
`aluwxor:
begin
case(ctrl_ppp)
`aa: // aluwxor AND `aa
begin
case(ctrl_ww)
`w8: // aluwxor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default: // aluwxor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwxor AND `uu
begin
case(ctrl_ww)
`w8: // aluwxor AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
end
`w16: // aluwxor AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
end
`w32: // aluwxor AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
end
default:
begin
// aluwxor AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwxor AND `dd
begin
case(ctrl_ww)
`w8: // aluwxor AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwxor AND `ee
begin
case(ctrl_ww)
`w8: // aluwxor AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
end
`w16: // aluwxor AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
end
`w32: // aluwxor AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
end
default:
begin
// aluwxor AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwxor AND `oo
begin
case(ctrl_ww)
`w8: // aluwxor AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwxor AND `mm
begin
case(ctrl_ww)
`w8: // aluwxor AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
end
`w16: // aluwxor AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
end
`w32: // aluwxor AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
end
default:
begin
// aluwxor AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwxor AND `ll
begin
case(ctrl_ww)
`w8: // aluwxor AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwxor AND Default
begin
result<=128'd0;
end
endcase
end
// ======================================================
// SUB instruction
`aluwsub:
begin
case(ctrl_ppp)
`aa: // aluwsub AND `aa
begin
case(ctrl_ww)
`w8: // aluwsub AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default: // aluwsub AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwsub AND `uu
begin
case(ctrl_ww)
`w8: // aluwsub AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
end
`w16: // aluwsub AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
end
`w32: // aluwsub AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
end
default:
begin
// aluwsub AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwsub AND `dd
begin
case(ctrl_ww)
`w8: // aluwsub AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwsub AND `ee
begin
case(ctrl_ww)
`w8: // aluwsub AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
end
`w16: // aluwsub AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
end
`w32: // aluwsub AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
end
default:
begin
// aluwsub AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwsub AND `oo
begin
case(ctrl_ww)
`w8: // aluwsub AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwsub AND `mm
begin
case(ctrl_ww)
`w8: // aluwsub AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
end
`w16: // aluwsub AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
end
`w32: // aluwsub AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
end
default:
begin
// aluwsub AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwsub AND `ll
begin
case(ctrl_ww)
`w8: // aluwsub AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwsub AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
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//================================================================================
// ==============================================================
// PRM instruction
`aluwprm:
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
/*
* ========================================================
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*/
// ==============================================================
// SLLI instruction
`aluwslli:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
// ==============================================================
// SRLI instruction
`aluwsrli:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={{1'b0},reg_A[0:6]};
result[8:15]<={{1'b0},reg_A[8:14]};
result[16:23]<={{1'b0},reg_A[16:22]};
result[24:31]<={{1'b0},reg_A[24:30]};
result[32:39]<={{1'b0},reg_A[32:38]};
result[40:47]<={{1'b0},reg_A[40:46]};
result[48:55]<={{1'b0},reg_A[48:54]};
result[56:63]<={{1'b0},reg_A[56:62]};
result[64:71]<={{1'b0},reg_A[64:70]};
result[72:79]<={{1'b0},reg_A[72:78]};
result[80:87]<={{1'b0},reg_A[80:86]};
result[88:95]<={{1'b0},reg_A[88:94]};
result[96:103]<={{1'b0},reg_A[96:102]};
result[104:111]<={{1'b0},reg_A[104:110]};
result[112:119]<={{1'b0},reg_A[112:118]};
result[120:127]<={{1'b0},reg_A[120:126]};
end
3'd2:
begin
result[0:7]<={{2{1'b0}},reg_A[0:5]};
result[8:15]<={{2{1'b0}},reg_A[8:13]};
result[16:23]<={{2{1'b0}},reg_A[16:21]};
result[24:31]<={{2{1'b0}},reg_A[24:29]};
result[32:39]<={{2{1'b0}},reg_A[32:37]};
result[40:47]<={{2{1'b0}},reg_A[40:45]};
result[48:55]<={{2{1'b0}},reg_A[48:53]};
result[56:63]<={{2{1'b0}},reg_A[56:61]};
result[64:71]<={{2{1'b0}},reg_A[64:69]};
result[72:79]<={{2{1'b0}},reg_A[72:77]};
result[80:87]<={{2{1'b0}},reg_A[80:85]};
result[88:95]<={{2{1'b0}},reg_A[88:93]};
result[96:103]<={{2{1'b0}},reg_A[96:101]};
result[104:111]<={{2{1'b0}},reg_A[104:109]};
result[112:119]<={{2{1'b0}},reg_A[112:117]};
result[120:127]<={{2{1'b0}},reg_A[120:125]};
end
3'd3:
begin
result[0:7]<={{3{1'b0}},reg_A[0:4]};
result[8:15]<={{3{1'b0}},reg_A[8:12]};
result[16:23]<={{3{1'b0}},reg_A[16:20]};
result[24:31]<={{3{1'b0}},reg_A[24:28]};
result[32:39]<={{3{1'b0}},reg_A[32:36]};
result[40:47]<={{3{1'b0}},reg_A[40:44]};
result[48:55]<={{3{1'b0}},reg_A[48:52]};
result[56:63]<={{3{1'b0}},reg_A[56:60]};
result[64:71]<={{3{1'b0}},reg_A[64:68]};
result[72:79]<={{3{1'b0}},reg_A[72:76]};
result[80:87]<={{3{1'b0}},reg_A[80:84]};
result[88:95]<={{3{1'b0}},reg_A[88:92]};
result[96:103]<={{3{1'b0}},reg_A[96:100]};
result[104:111]<={{3{1'b0}},reg_A[104:108]};
result[112:119]<={{3{1'b0}},reg_A[112:116]};
result[120:127]<={{3{1'b0}},reg_A[120:124]};
end
3'd4:
begin
result[0:7]<={{4{1'b0}},reg_A[0:3]};
result[8:15]<={{4{1'b0}},reg_A[8:11]};
result[16:23]<={{4{1'b0}},reg_A[16:19]};
result[24:31]<={{4{1'b0}},reg_A[24:27]};
result[32:39]<={{4{1'b0}},reg_A[32:35]};
result[40:47]<={{4{1'b0}},reg_A[40:43]};
result[48:55]<={{4{1'b0}},reg_A[48:51]};
result[56:63]<={{4{1'b0}},reg_A[56:69]};
result[64:71]<={{4{1'b0}},reg_A[64:67]};
result[72:79]<={{4{1'b0}},reg_A[72:75]};
result[80:87]<={{4{1'b0}},reg_A[80:83]};
result[88:95]<={{4{1'b0}},reg_A[88:91]};
result[96:103]<={{4{1'b0}},reg_A[96:99]};
result[104:111]<={{4{1'b0}},reg_A[104:107]};
result[112:119]<={{4{1'b0}},reg_A[112:115]};
result[120:127]<={{4{1'b0}},reg_A[120:123]};
end
3'd5:
begin
result[0:7]<={{5{1'b0}},reg_A[0:2]};
result[8:15]<={{5{1'b0}},reg_A[8:10]};
result[16:23]<={{5{1'b0}},reg_A[16:18]};
result[24:31]<={{5{1'b0}},reg_A[24:26]};
result[32:39]<={{5{1'b0}},reg_A[32:34]};
result[40:47]<={{5{1'b0}},reg_A[40:42]};
result[48:55]<={{5{1'b0}},reg_A[48:50]};
result[56:63]<={{5{1'b0}},reg_A[56:68]};
result[64:71]<={{5{1'b0}},reg_A[64:66]};
result[72:79]<={{5{1'b0}},reg_A[72:74]};
result[80:87]<={{5{1'b0}},reg_A[80:82]};
result[88:95]<={{5{1'b0}},reg_A[88:90]};
result[96:103]<={{5{1'b0}},reg_A[96:98]};
result[104:111]<={{5{1'b0}},reg_A[104:106]};
result[112:119]<={{5{1'b0}},reg_A[112:114]};
result[120:127]<={{5{1'b0}},reg_A[120:122]};
end
3'd6:
begin
result[0:7]<={{6{1'b0}},reg_A[0:1]};
result[8:15]<={{6{1'b0}},reg_A[8:9]};
result[16:23]<={{6{1'b0}},reg_A[16:17]};
result[24:31]<={{6{1'b0}},reg_A[24:25]};
result[32:39]<={{6{1'b0}},reg_A[32:33]};
result[40:47]<={{6{1'b0}},reg_A[40:41]};
result[48:55]<={{6{1'b0}},reg_A[48:49]};
result[56:63]<={{6{1'b0}},reg_A[56:67]};
result[64:71]<={{6{1'b0}},reg_A[64:65]};
result[72:79]<={{6{1'b0}},reg_A[72:73]};
result[80:87]<={{6{1'b0}},reg_A[80:81]};
result[88:95]<={{6{1'b0}},reg_A[88:89]};
result[96:103]<={{6{1'b0}},reg_A[96:97]};
result[104:111]<={{6{1'b0}},reg_A[104:105]};
result[112:119]<={{6{1'b0}},reg_A[112:113]};
result[120:127]<={{6{1'b0}},reg_A[120:121]};
end
3'd7:
begin
result[0:7]<={{7{1'b0}},reg_A[0]};
result[8:15]<={{7{1'b0}},reg_A[8]};
result[16:23]<={{7{1'b0}},reg_A[16]};
result[24:31]<={{7{1'b0}},reg_A[24]};
result[32:39]<={{7{1'b0}},reg_A[32]};
result[40:47]<={{7{1'b0}},reg_A[40]};
result[48:55]<={{7{1'b0}},reg_A[48]};
result[56:63]<={{7{1'b0}},reg_A[56]};
result[64:71]<={{7{1'b0}},reg_A[64]};
result[72:79]<={{7{1'b0}},reg_A[72]};
result[80:87]<={{7{1'b0}},reg_A[80]};
result[88:95]<={{7{1'b0}},reg_A[88]};
result[96:103]<={{7{1'b0}},reg_A[96]};
result[104:111]<={{7{1'b0}},reg_A[104]};
result[112:119]<={{7{1'b0}},reg_A[112]};
result[120:127]<={{7{1'b0}},reg_A[120]};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={{1'b0},reg_A[0:14]};
result[16:31]<={{1'b0},reg_A[16:30]};
result[32:47]<={{1'b0},reg_A[32:46]};
result[48:63]<={{1'b0},reg_A[48:62]};
result[64:79]<={{1'b0},reg_A[64:78]};
result[80:95]<={{1'b0},reg_A[80:94]};
result[96:111]<={{1'b0},reg_A[96:110]};
result[112:127]<={{1'b0},reg_A[112:126]};
end
4'd2:
begin
result[0:15]<={{2{1'b0}},reg_A[0:13]};
result[16:31]<={{2{1'b0}},reg_A[16:29]};
result[32:47]<={{2{1'b0}},reg_A[32:45]};
result[48:63]<={{2{1'b0}},reg_A[48:61]};
result[64:79]<={{2{1'b0}},reg_A[64:77]};
result[80:95]<={{2{1'b0}},reg_A[80:93]};
result[96:111]<={{2{1'b0}},reg_A[96:109]};
result[112:127]<={{2{1'b0}},reg_A[112:125]};
end
4'd3:
begin
result[0:15]<={{3{1'b0}},reg_A[0:12]};
result[16:31]<={{3{1'b0}},reg_A[16:28]};
result[32:47]<={{3{1'b0}},reg_A[32:44]};
result[48:63]<={{3{1'b0}},reg_A[48:60]};
result[64:79]<={{3{1'b0}},reg_A[64:76]};
result[80:95]<={{3{1'b0}},reg_A[80:92]};
result[96:111]<={{3{1'b0}},reg_A[96:108]};
result[112:127]<={{3{1'b0}},reg_A[112:124]};
end
4'd4:
begin
result[0:15]<={{4{1'b0}},reg_A[0:11]};
result[16:31]<={{4{1'b0}},reg_A[16:27]};
result[32:47]<={{4{1'b0}},reg_A[32:43]};
result[48:63]<={{4{1'b0}},reg_A[48:59]};
result[64:79]<={{4{1'b0}},reg_A[64:75]};
result[80:95]<={{4{1'b0}},reg_A[80:91]};
result[96:111]<={{4{1'b0}},reg_A[96:107]};
result[112:127]<={{4{1'b0}},reg_A[112:123]};
end
4'd5:
begin
result[0:15]<={{5{1'b0}},reg_A[0:10]};
result[16:31]<={{5{1'b0}},reg_A[16:26]};
result[32:47]<={{5{1'b0}},reg_A[32:42]};
result[48:63]<={{5{1'b0}},reg_A[48:58]};
result[64:79]<={{5{1'b0}},reg_A[64:74]};
result[80:95]<={{5{1'b0}},reg_A[80:90]};
result[96:111]<={{5{1'b0}},reg_A[96:106]};
result[112:127]<={{5{1'b0}},reg_A[112:122]};
end
4'd6:
begin
result[0:15]<={{6{1'b0}},reg_A[0:9]};
result[16:31]<={{6{1'b0}},reg_A[16:25]};
result[32:47]<={{6{1'b0}},reg_A[32:41]};
result[48:63]<={{6{1'b0}},reg_A[48:57]};
result[64:79]<={{6{1'b0}},reg_A[64:73]};
result[80:95]<={{6{1'b0}},reg_A[80:89]};
result[96:111]<={{6{1'b0}},reg_A[96:105]};
result[112:127]<={{6{1'b0}},reg_A[112:121]};
end
4'd7:
begin
result[0:15]<={{7{1'b0}},reg_A[0:8]};
result[16:31]<={{7{1'b0}},reg_A[16:24]};
result[32:47]<={{7{1'b0}},reg_A[32:40]};
result[48:63]<={{7{1'b0}},reg_A[48:56]};
result[64:79]<={{7{1'b0}},reg_A[64:72]};
result[80:95]<={{7{1'b0}},reg_A[80:88]};
result[96:111]<={{7{1'b0}},reg_A[96:104]};
result[112:127]<={{7{1'b0}},reg_A[112:120]};
end
4'd8:
begin
result[0:15]<={{8{1'b0}},reg_A[0:7]};
result[16:31]<={{8{1'b0}},reg_A[16:23]};
result[32:47]<={{8{1'b0}},reg_A[32:39]};
result[48:63]<={{8{1'b0}},reg_A[48:55]};
result[64:79]<={{8{1'b0}},reg_A[64:71]};
result[80:95]<={{8{1'b0}},reg_A[80:87]};
result[96:111]<={{8{1'b0}},reg_A[96:103]};
result[112:127]<={{8{1'b0}},reg_A[112:119]};
end
4'd9:
begin
result[0:15]<={{9{1'b0}},reg_A[0:6]};
result[16:31]<={{9{1'b0}},reg_A[16:22]};
result[32:47]<={{9{1'b0}},reg_A[32:38]};
result[48:63]<={{9{1'b0}},reg_A[48:54]};
result[64:79]<={{9{1'b0}},reg_A[64:70]};
result[80:95]<={{9{1'b0}},reg_A[80:86]};
result[96:111]<={{9{1'b0}},reg_A[96:102]};
result[112:127]<={{9{1'b0}},reg_A[112:118]};
end
4'd10:
begin
result[0:15]<={{10{1'b0}},reg_A[0:5]};
result[16:31]<={{10{1'b0}},reg_A[16:21]};
result[32:47]<={{10{1'b0}},reg_A[32:37]};
result[48:63]<={{10{1'b0}},reg_A[48:53]};
result[64:79]<={{10{1'b0}},reg_A[64:69]};
result[80:95]<={{10{1'b0}},reg_A[80:85]};
result[96:111]<={{10{1'b0}},reg_A[96:101]};
result[112:127]<={{10{1'b0}},reg_A[112:117]};
end
4'd11:
begin
result[0:15]<={{11{1'b0}},reg_A[0:4]};
result[16:31]<={{11{1'b0}},reg_A[16:20]};
result[32:47]<={{11{1'b0}},reg_A[32:36]};
result[48:63]<={{11{1'b0}},reg_A[48:52]};
result[64:79]<={{11{1'b0}},reg_A[64:68]};
result[80:95]<={{11{1'b0}},reg_A[80:84]};
result[96:111]<={{11{1'b0}},reg_A[96:100]};
result[112:127]<={{11{1'b0}},reg_A[112:116]};
end
4'd12:
begin
result[0:15]<={{12{1'b0}},reg_A[0:3]};
result[16:31]<={{12{1'b0}},reg_A[16:19]};
result[32:47]<={{12{1'b0}},reg_A[32:35]};
result[48:63]<={{12{1'b0}},reg_A[48:51]};
result[64:79]<={{12{1'b0}},reg_A[64:67]};
result[80:95]<={{12{1'b0}},reg_A[80:83]};
result[96:111]<={{12{1'b0}},reg_A[96:99]};
result[112:127]<={{12{1'b0}},reg_A[112:115]};
end
4'd13:
begin
result[0:15]<={{13{1'b0}},reg_A[0:2]};
result[16:31]<={{13{1'b0}},reg_A[16:18]};
result[32:47]<={{13{1'b0}},reg_A[32:34]};
result[48:63]<={{13{1'b0}},reg_A[48:50]};
result[64:79]<={{13{1'b0}},reg_A[64:66]};
result[80:95]<={{13{1'b0}},reg_A[80:82]};
result[96:111]<={{13{1'b0}},reg_A[96:98]};
result[112:127]<={{13{1'b0}},reg_A[112:114]};
end
4'd14:
begin
result[0:15]<={{14{1'b0}},reg_A[0:1]};
result[16:31]<={{14{1'b0}},reg_A[16:17]};
result[32:47]<={{14{1'b0}},reg_A[32:33]};
result[48:63]<={{14{1'b0}},reg_A[48:49]};
result[64:79]<={{14{1'b0}},reg_A[64:65]};
result[80:95]<={{14{1'b0}},reg_A[80:81]};
result[96:111]<={{14{1'b0}},reg_A[96:97]};
result[112:127]<={{14{1'b0}},reg_A[112:113]};
end
4'd15:
begin
result[0:15]<={{15{1'b0}},reg_A[0]};
result[16:31]<={{15{1'b0}},reg_A[16]};
result[32:47]<={{15{1'b0}},reg_A[32]};
result[48:63]<={{15{1'b0}},reg_A[48]};
result[64:79]<={{15{1'b0}},reg_A[64]};
result[80:95]<={{15{1'b0}},reg_A[80]};
result[96:111]<={{15{1'b0}},reg_A[96]};
result[112:127]<={{15{1'b0}},reg_A[112]};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={{1'b0},reg_A[0:30]};
result[32:63]<={{1'b0},reg_A[32:62]};
result[64:95]<={{1'b0},reg_A[64:94]};
result[96:127]<={{1'b0},reg_A[96:126]};
end
5'd2:
begin
result[0:31]<={{2{1'b0}},reg_A[0:29]};
result[32:63]<={{2{1'b0}},reg_A[32:61]};
result[64:95]<={{2{1'b0}},reg_A[64:93]};
result[96:127]<={{2{1'b0}},reg_A[96:125]};
end
5'd3:
begin
result[0:31]<={{3{1'b0}},reg_A[0:28]};
result[32:63]<={{3{1'b0}},reg_A[32:60]};
result[64:95]<={{3{1'b0}},reg_A[64:92]};
result[96:127]<={{3{1'b0}},reg_A[96:124]};
end
5'd4:
begin
result[0:31]<={{4{1'b0}},reg_A[0:27]};
result[32:63]<={{4{1'b0}},reg_A[32:59]};
result[64:95]<={{4{1'b0}},reg_A[64:91]};
result[96:127]<={{4{1'b0}},reg_A[96:123]};
end
5'd5:
begin
result[0:31]<={{5{1'b0}},reg_A[0:26]};
result[32:63]<={{5{1'b0}},reg_A[32:58]};
result[64:95]<={{5{1'b0}},reg_A[64:90]};
result[96:127]<={{5{1'b0}},reg_A[96:122]};
end
5'd6:
begin
result[0:31]<={{6{1'b0}},reg_A[0:25]};
result[32:63]<={{6{1'b0}},reg_A[32:57]};
result[64:95]<={{6{1'b0}},reg_A[64:89]};
result[96:127]<={{6{1'b0}},reg_A[96:121]};
end
5'd7:
begin
result[0:31]<={{7{1'b0}},reg_A[0:24]};
result[32:63]<={{7{1'b0}},reg_A[32:56]};
result[64:95]<={{7{1'b0}},reg_A[64:88]};
result[96:127]<={{7{1'b0}},reg_A[96:120]};
end
5'd8:
begin
result[0:31]<={{8{1'b0}},reg_A[0:23]};
result[32:63]<={{8{1'b0}},reg_A[32:55]};
result[64:95]<={{8{1'b0}},reg_A[64:87]};
result[96:127]<={{8{1'b0}},reg_A[96:119]};
end
5'd9:
begin
result[0:31]<={{9{1'b0}},reg_A[0:22]};
result[32:63]<={{9{1'b0}},reg_A[32:54]};
result[64:95]<={{9{1'b0}},reg_A[64:86]};
result[96:127]<={{9{1'b0}},reg_A[96:118]};
end
5'd10:
begin
result[0:31]<={{10{1'b0}},reg_A[0:21]};
result[32:63]<={{10{1'b0}},reg_A[32:53]};
result[64:95]<={{10{1'b0}},reg_A[64:85]};
result[96:127]<={{10{1'b0}},reg_A[96:117]};
end
5'd11:
begin
result[0:31]<={{11{1'b0}},reg_A[0:20]};
result[32:63]<={{11{1'b0}},reg_A[32:52]};
result[64:95]<={{11{1'b0}},reg_A[64:84]};
result[96:127]<={{11{1'b0}},reg_A[96:116]};
end
5'd12:
begin
result[0:31]<={{12{1'b0}},reg_A[0:19]};
result[32:63]<={{12{1'b0}},reg_A[32:51]};
result[64:95]<={{12{1'b0}},reg_A[64:83]};
result[96:127]<={{12{1'b0}},reg_A[96:115]};
end
5'd13:
begin
result[0:31]<={{13{1'b0}},reg_A[0:18]};
result[32:63]<={{13{1'b0}},reg_A[32:50]};
result[64:95]<={{13{1'b0}},reg_A[64:82]};
result[96:127]<={{13{1'b0}},reg_A[96:114]};
end
5'd14:
begin
result[0:31]<={{14{1'b0}},reg_A[0:17]};
result[32:63]<={{14{1'b0}},reg_A[32:49]};
result[64:95]<={{14{1'b0}},reg_A[64:81]};
result[96:127]<={{14{1'b0}},reg_A[96:113]};
end
5'd15:
begin
result[0:31]<={{15{1'b0}},reg_A[0:16]};
result[32:63]<={{15{1'b0}},reg_A[32:48]};
result[64:95]<={{15{1'b0}},reg_A[64:80]};
result[96:127]<={{15{1'b0}},reg_A[96:112]};
end
5'd16:
begin
result[0:31]<={{16{1'b0}},reg_A[0:15]};
result[32:63]<={{16{1'b0}},reg_A[32:47]};
result[64:95]<={{16{1'b0}},reg_A[64:79]};
result[96:127]<={{16{1'b0}},reg_A[96:111]};
end
5'd17:
begin
result[0:31]<={{17{1'b0}},reg_A[0:14]};
result[32:63]<={{17{1'b0}},reg_A[32:46]};
result[64:95]<={{17{1'b0}},reg_A[64:78]};
result[96:127]<={{17{1'b0}},reg_A[96:110]};
end
5'd18:
begin
result[0:31]<={{18{1'b0}},reg_A[0:13]};
result[32:63]<={{18{1'b0}},reg_A[32:45]};
result[64:95]<={{18{1'b0}},reg_A[64:77]};
result[96:127]<={{18{1'b0}},reg_A[96:109]};
end
5'd19:
begin
result[0:31]<={{19{1'b0}},reg_A[0:12]};
result[32:63]<={{19{1'b0}},reg_A[32:44]};
result[64:95]<={{19{1'b0}},reg_A[64:76]};
result[96:127]<={{19{1'b0}},reg_A[96:108]};
end
5'd20:
begin
result[0:31]<={{20{1'b0}},reg_A[0:11]};
result[32:63]<={{20{1'b0}},reg_A[32:43]};
result[64:95]<={{20{1'b0}},reg_A[64:75]};
result[96:127]<={{20{1'b0}},reg_A[96:107]};
end
5'd21:
begin
result[0:31]<={{21{1'b0}},reg_A[0:10]};
result[32:63]<={{21{1'b0}},reg_A[32:42]};
result[64:95]<={{21{1'b0}},reg_A[64:74]};
result[96:127]<={{21{1'b0}},reg_A[96:106]};
end
5'd22:
begin
result[0:31]<={{22{1'b0}},reg_A[0:9]};
result[32:63]<={{22{1'b0}},reg_A[32:41]};
result[64:95]<={{22{1'b0}},reg_A[64:73]};
result[96:127]<={{22{1'b0}},reg_A[96:105]};
end
5'd23:
begin
result[0:31]<={{23{1'b0}},reg_A[0:8]};
result[32:63]<={{23{1'b0}},reg_A[32:40]};
result[64:95]<={{23{1'b0}},reg_A[64:72]};
result[96:127]<={{23{1'b0}},reg_A[96:104]};
end
5'd24:
begin
result[0:31]<={{24{1'b0}},reg_A[0:7]};
result[32:63]<={{24{1'b0}},reg_A[32:39]};
result[64:95]<={{24{1'b0}},reg_A[64:71]};
result[96:127]<={{24{1'b0}},reg_A[96:103]};
end
5'd25:
begin
result[0:31]<={{25{1'b0}},reg_A[0:6]};
result[32:63]<={{25{1'b0}},reg_A[32:38]};
result[64:95]<={{25{1'b0}},reg_A[64:70]};
result[96:127]<={{25{1'b0}},reg_A[96:102]};
end
5'd26:
begin
result[0:31]<={{26{1'b0}},reg_A[0:5]};
result[32:63]<={{26{1'b0}},reg_A[32:37]};
result[64:95]<={{26{1'b0}},reg_A[64:69]};
result[96:127]<={{26{1'b0}},reg_A[96:101]};
end
5'd27:
begin
result[0:31]<={{27{1'b0}},reg_A[0:4]};
result[32:63]<={{27{1'b0}},reg_A[32:36]};
result[64:95]<={{27{1'b0}},reg_A[64:68]};
result[96:127]<={{27{1'b0}},reg_A[96:100]};
end
5'd28:
begin
result[0:31]<={{28{1'b0}},reg_A[0:3]};
result[32:63]<={{28{1'b0}},reg_A[32:35]};
result[64:95]<={{28{1'b0}},reg_A[64:67]};
result[96:127]<={{28{1'b0}},reg_A[96:99]};
end
5'd29:
begin
result[0:31]<={{29{1'b0}},reg_A[0:2]};
result[32:63]<={{29{1'b0}},reg_A[32:34]};
result[64:95]<={{29{1'b0}},reg_A[64:66]};
result[96:127]<={{29{1'b0}},reg_A[96:98]};
end
5'd30:
begin
result[0:31]<={{30{1'b0}},reg_A[0:1]};
result[32:63]<={{30{1'b0}},reg_A[32:33]};
result[64:95]<={{30{1'b0}},reg_A[64:65]};
result[96:127]<={{30{1'b0}},reg_A[96:97]};
end
5'd31:
begin
result[0:31]<={{31{1'b0}},reg_A[0]};
result[32:63]<={{31{1'b0}},reg_A[32]};
result[64:95]<={{31{1'b0}},reg_A[64]};
result[96:127]<={{31{1'b0}},reg_A[96]};
end
endcase
end
endcase
end
// ==============================================================
// SRAI instruction
`aluwsrai:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={{reg_A[0]},reg_A[0:6]};
result[8:15]<={{reg_A[8]},reg_A[8:14]};
result[16:23]<={{reg_A[16]},reg_A[16:22]};
result[24:31]<={{reg_A[24]},reg_A[24:30]};
result[32:39]<={{reg_A[32]},reg_A[32:38]};
result[40:47]<={{reg_A[40]},reg_A[40:46]};
result[48:55]<={{reg_A[48]},reg_A[48:54]};
result[56:63]<={{reg_A[56]},reg_A[56:62]};
result[64:71]<={{reg_A[64]},reg_A[64:70]};
result[72:79]<={{reg_A[72]},reg_A[72:78]};
result[80:87]<={{reg_A[80]},reg_A[80:86]};
result[88:95]<={{reg_A[88]},reg_A[88:94]};
result[96:103]<={{reg_A[96]},reg_A[96:102]};
result[104:111]<={{reg_A[104]},reg_A[104:110]};
result[112:119]<={{reg_A[112]},reg_A[112:118]};
result[120:127]<={{reg_A[120]},reg_A[120:126]};
end
3'd2:
begin
result[0:7]<={{2{reg_A[0]}},reg_A[0:5]};
result[8:15]<={{2{reg_A[8]}},reg_A[8:13]};
result[16:23]<={{2{reg_A[16]}},reg_A[16:21]};
result[24:31]<={{2{reg_A[24]}},reg_A[24:29]};
result[32:39]<={{2{reg_A[32]}},reg_A[32:37]};
result[40:47]<={{2{reg_A[40]}},reg_A[40:45]};
result[48:55]<={{2{reg_A[48]}},reg_A[48:53]};
result[56:63]<={{2{reg_A[56]}},reg_A[56:61]};
result[64:71]<={{2{reg_A[64]}},reg_A[64:69]};
result[72:79]<={{2{reg_A[72]}},reg_A[72:77]};
result[80:87]<={{2{reg_A[80]}},reg_A[80:85]};
result[88:95]<={{2{reg_A[88]}},reg_A[88:93]};
result[96:103]<={{2{reg_A[96]}},reg_A[96:101]};
result[104:111]<={{2{reg_A[104]}},reg_A[104:109]};
result[112:119]<={{2{reg_A[112]}},reg_A[112:117]};
result[120:127]<={{2{reg_A[120]}},reg_A[120:125]};
end
3'd3:
begin
result[0:7]<={{3{reg_A[0]}},reg_A[0:4]};
result[8:15]<={{3{reg_A[8]}},reg_A[8:12]};
result[16:23]<={{3{reg_A[16]}},reg_A[16:20]};
result[24:31]<={{3{reg_A[24]}},reg_A[24:28]};
result[32:39]<={{3{reg_A[32]}},reg_A[32:36]};
result[40:47]<={{3{reg_A[40]}},reg_A[40:44]};
result[48:55]<={{3{reg_A[48]}},reg_A[48:52]};
result[56:63]<={{3{reg_A[56]}},reg_A[56:60]};
result[64:71]<={{3{reg_A[64]}},reg_A[64:68]};
result[72:79]<={{3{reg_A[72]}},reg_A[72:76]};
result[80:87]<={{3{reg_A[80]}},reg_A[80:84]};
result[88:95]<={{3{reg_A[88]}},reg_A[88:92]};
result[96:103]<={{3{reg_A[96]}},reg_A[96:100]};
result[104:111]<={{3{reg_A[104]}},reg_A[104:108]};
result[112:119]<={{3{reg_A[112]}},reg_A[112:116]};
result[120:127]<={{3{reg_A[120]}},reg_A[120:124]};
end
3'd4:
begin
result[0:7]<={{4{reg_A[0]}},reg_A[0:3]};
result[8:15]<={{4{reg_A[8]}},reg_A[8:11]};
result[16:23]<={{4{reg_A[16]}},reg_A[16:19]};
result[24:31]<={{4{reg_A[24]}},reg_A[24:27]};
result[32:39]<={{4{reg_A[32]}},reg_A[32:35]};
result[40:47]<={{4{reg_A[40]}},reg_A[40:43]};
result[48:55]<={{4{reg_A[48]}},reg_A[48:51]};
result[56:63]<={{4{reg_A[56]}},reg_A[56:69]};
result[64:71]<={{4{reg_A[64]}},reg_A[64:67]};
result[72:79]<={{4{reg_A[72]}},reg_A[72:75]};
result[80:87]<={{4{reg_A[80]}},reg_A[80:83]};
result[88:95]<={{4{reg_A[88]}},reg_A[88:91]};
result[96:103]<={{4{reg_A[96]}},reg_A[96:99]};
result[104:111]<={{4{reg_A[104]}},reg_A[104:107]};
result[112:119]<={{4{reg_A[112]}},reg_A[112:115]};
result[120:127]<={{4{reg_A[120]}},reg_A[120:123]};
end
3'd5:
begin
result[0:7]<={{5{reg_A[0]}},reg_A[0:2]};
result[8:15]<={{5{reg_A[8]}},reg_A[8:10]};
result[16:23]<={{5{reg_A[16]}},reg_A[16:18]};
result[24:31]<={{5{reg_A[24]}},reg_A[24:26]};
result[32:39]<={{5{reg_A[32]}},reg_A[32:34]};
result[40:47]<={{5{reg_A[40]}},reg_A[40:42]};
result[48:55]<={{5{reg_A[48]}},reg_A[48:50]};
result[56:63]<={{5{reg_A[56]}},reg_A[56:68]};
result[64:71]<={{5{reg_A[64]}},reg_A[64:66]};
result[72:79]<={{5{reg_A[72]}},reg_A[72:74]};
result[80:87]<={{5{reg_A[80]}},reg_A[80:82]};
result[88:95]<={{5{reg_A[88]}},reg_A[88:90]};
result[96:103]<={{5{reg_A[96]}},reg_A[96:98]};
result[104:111]<={{5{reg_A[104]}},reg_A[104:106]};
result[112:119]<={{5{reg_A[112]}},reg_A[112:114]};
result[120:127]<={{5{reg_A[120]}},reg_A[120:122]};
end
3'd6:
begin
result[0:7]<={{6{reg_A[0]}},reg_A[0:1]};
result[8:15]<={{6{reg_A[8]}},reg_A[8:9]};
result[16:23]<={{6{reg_A[16]}},reg_A[16:17]};
result[24:31]<={{6{reg_A[24]}},reg_A[24:25]};
result[32:39]<={{6{reg_A[32]}},reg_A[32:33]};
result[40:47]<={{6{reg_A[40]}},reg_A[40:41]};
result[48:55]<={{6{reg_A[48]}},reg_A[48:49]};
result[56:63]<={{6{reg_A[56]}},reg_A[56:67]};
result[64:71]<={{6{reg_A[64]}},reg_A[64:65]};
result[72:79]<={{6{reg_A[72]}},reg_A[72:73]};
result[80:87]<={{6{reg_A[80]}},reg_A[80:81]};
result[88:95]<={{6{reg_A[88]}},reg_A[88:89]};
result[96:103]<={{6{reg_A[96]}},reg_A[96:97]};
result[104:111]<={{6{reg_A[104]}},reg_A[104:105]};
result[112:119]<={{6{reg_A[112]}},reg_A[112:113]};
result[120:127]<={{6{reg_A[120]}},reg_A[120:121]};
end
3'd7:
begin
result[0:7]<={{7{reg_A[0]}},reg_A[0]};
result[8:15]<={{7{reg_A[8]}},reg_A[8]};
result[16:23]<={{7{reg_A[16]}},reg_A[16]};
result[24:31]<={{7{reg_A[24]}},reg_A[24]};
result[32:39]<={{7{reg_A[32]}},reg_A[32]};
result[40:47]<={{7{reg_A[40]}},reg_A[40]};
result[48:55]<={{7{reg_A[48]}},reg_A[48]};
result[56:63]<={{7{reg_A[56]}},reg_A[56]};
result[64:71]<={{7{reg_A[64]}},reg_A[64]};
result[72:79]<={{7{reg_A[72]}},reg_A[72]};
result[80:87]<={{7{reg_A[80]}},reg_A[80]};
result[88:95]<={{7{reg_A[88]}},reg_A[88]};
result[96:103]<={{7{reg_A[96]}},reg_A[96]};
result[104:111]<={{7{reg_A[104]}},reg_A[104]};
result[112:119]<={{7{reg_A[112]}},reg_A[112]};
result[120:127]<={{7{reg_A[120]}},reg_A[120]};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={{reg_A[0]},reg_A[0:14]};
result[16:31]<={{reg_A[16]},reg_A[16:30]};
result[32:47]<={{reg_A[32]},reg_A[32:46]};
result[48:63]<={{reg_A[48]},reg_A[48:62]};
result[64:79]<={{reg_A[64]},reg_A[64:78]};
result[80:95]<={{reg_A[80]},reg_A[80:94]};
result[96:111]<={{reg_A[96]},reg_A[96:110]};
result[112:127]<={{reg_A[112]},reg_A[112:126]};
end
4'd2:
begin
result[0:15]<={{2{reg_A[0]}},reg_A[0:13]};
result[16:31]<={{2{reg_A[16]}},reg_A[16:29]};
result[32:47]<={{2{reg_A[32]}},reg_A[32:45]};
result[48:63]<={{2{reg_A[48]}},reg_A[48:61]};
result[64:79]<={{2{reg_A[64]}},reg_A[64:77]};
result[80:95]<={{2{reg_A[80]}},reg_A[80:93]};
result[96:111]<={{2{reg_A[96]}},reg_A[96:109]};
result[112:127]<={{2{reg_A[112]}},reg_A[112:125]};
end
4'd3:
begin
result[0:15]<={{3{reg_A[0]}},reg_A[0:12]};
result[16:31]<={{3{reg_A[16]}},reg_A[16:28]};
result[32:47]<={{3{reg_A[32]}},reg_A[32:44]};
result[48:63]<={{3{reg_A[48]}},reg_A[48:60]};
result[64:79]<={{3{reg_A[64]}},reg_A[64:76]};
result[80:95]<={{3{reg_A[80]}},reg_A[80:92]};
result[96:111]<={{3{reg_A[96]}},reg_A[96:108]};
result[112:127]<={{3{reg_A[112]}},reg_A[112:124]};
end
4'd4:
begin
result[0:15]<={{4{reg_A[0]}},reg_A[0:11]};
result[16:31]<={{4{reg_A[8]}},reg_A[16:27]};
result[32:47]<={{4{reg_A[16]}},reg_A[32:43]};
result[48:63]<={{4{reg_A[32]}},reg_A[48:59]};
result[64:79]<={{4{reg_A[48]}},reg_A[64:75]};
result[80:95]<={{4{reg_A[64]}},reg_A[80:91]};
result[96:111]<={{4{reg_A[80]}},reg_A[96:107]};
result[112:127]<={{4{reg_A[112]}},reg_A[112:123]};
end
4'd5:
begin
result[0:15]<={{5{reg_A[0]}},reg_A[0:10]};
result[16:31]<={{5{reg_A[16]}},reg_A[16:26]};
result[32:47]<={{5{reg_A[32]}},reg_A[32:42]};
result[48:63]<={{5{reg_A[48]}},reg_A[48:58]};
result[64:79]<={{5{reg_A[64]}},reg_A[64:74]};
result[80:95]<={{5{reg_A[80]}},reg_A[80:90]};
result[96:111]<={{5{reg_A[96]}},reg_A[96:106]};
result[112:127]<={{5{reg_A[112]}},reg_A[112:122]};
end
4'd6:
begin
result[0:15]<={{6{reg_A[0]}},reg_A[0:9]};
result[16:31]<={{6{reg_A[16]}},reg_A[16:25]};
result[32:47]<={{6{reg_A[32]}},reg_A[32:41]};
result[48:63]<={{6{reg_A[48]}},reg_A[48:57]};
result[64:79]<={{6{reg_A[64]}},reg_A[64:73]};
result[80:95]<={{6{reg_A[80]}},reg_A[80:89]};
result[96:111]<={{6{reg_A[96]}},reg_A[96:105]};
result[112:127]<={{6{reg_A[112]}},reg_A[112:121]};
end
4'd7:
begin
result[0:15]<={{7{reg_A[0]}},reg_A[0:8]};
result[16:31]<={{7{reg_A[16]}},reg_A[16:24]};
result[32:47]<={{7{reg_A[32]}},reg_A[32:40]};
result[48:63]<={{7{reg_A[48]}},reg_A[48:56]};
result[64:79]<={{7{reg_A[64]}},reg_A[64:72]};
result[80:95]<={{7{reg_A[80]}},reg_A[80:88]};
result[96:111]<={{7{reg_A[96]}},reg_A[96:104]};
result[112:127]<={{7{reg_A[112]}},reg_A[112:120]};
end
4'd8:
begin
result[0:15]<={{8{reg_A[0]}},reg_A[0:7]};
result[16:31]<={{8{reg_A[16]}},reg_A[16:23]};
result[32:47]<={{8{reg_A[32]}},reg_A[32:39]};
result[48:63]<={{8{reg_A[48]}},reg_A[48:55]};
result[64:79]<={{8{reg_A[64]}},reg_A[64:71]};
result[80:95]<={{8{reg_A[80]}},reg_A[80:87]};
result[96:111]<={{8{reg_A[96]}},reg_A[96:103]};
result[112:127]<={{8{reg_A[112]}},reg_A[112:119]};
end
4'd9:
begin
result[0:15]<={{9{reg_A[0]}},reg_A[0:6]};
result[16:31]<={{9{reg_A[16]}},reg_A[16:22]};
result[32:47]<={{9{reg_A[32]}},reg_A[32:38]};
result[48:63]<={{9{reg_A[48]}},reg_A[48:54]};
result[64:79]<={{9{reg_A[64]}},reg_A[64:70]};
result[80:95]<={{9{reg_A[80]}},reg_A[80:86]};
result[96:111]<={{9{reg_A[96]}},reg_A[96:102]};
result[112:127]<={{9{reg_A[112]}},reg_A[112:118]};
end
4'd10:
begin
result[0:15]<={{10{reg_A[0]}},reg_A[0:5]};
result[16:31]<={{10{reg_A[16]}},reg_A[16:21]};
result[32:47]<={{10{reg_A[32]}},reg_A[32:37]};
result[48:63]<={{10{reg_A[48]}},reg_A[48:53]};
result[64:79]<={{10{reg_A[64]}},reg_A[64:69]};
result[80:95]<={{10{reg_A[80]}},reg_A[80:85]};
result[96:111]<={{10{reg_A[96]}},reg_A[96:101]};
result[112:127]<={{10{reg_A[112]}},reg_A[112:117]};
end
4'd11:
begin
result[0:15]<={{11{reg_A[0]}},reg_A[0:4]};
result[16:31]<={{11{reg_A[16]}},reg_A[16:20]};
result[32:47]<={{11{reg_A[32]}},reg_A[32:36]};
result[48:63]<={{11{reg_A[48]}},reg_A[48:52]};
result[64:79]<={{11{reg_A[64]}},reg_A[64:68]};
result[80:95]<={{11{reg_A[80]}},reg_A[80:84]};
result[96:111]<={{11{reg_A[96]}},reg_A[96:100]};
result[112:127]<={{11{reg_A[112]}},reg_A[112:116]};
end
4'd12:
begin
result[0:15]<={{12{reg_A[0]}},reg_A[0:3]};
result[16:31]<={{12{reg_A[16]}},reg_A[16:19]};
result[32:47]<={{12{reg_A[32]}},reg_A[32:35]};
result[48:63]<={{12{reg_A[48]}},reg_A[48:51]};
result[64:79]<={{12{reg_A[64]}},reg_A[64:67]};
result[80:95]<={{12{reg_A[80]}},reg_A[80:83]};
result[96:111]<={{12{reg_A[96]}},reg_A[96:99]};
result[112:127]<={{12{reg_A[112]}},reg_A[112:115]};
end
4'd13:
begin
result[0:15]<={{13{reg_A[0]}},reg_A[0:2]};
result[16:31]<={{13{reg_A[16]}},reg_A[16:18]};
result[32:47]<={{13{reg_A[32]}},reg_A[32:34]};
result[48:63]<={{13{reg_A[48]}},reg_A[48:50]};
result[64:79]<={{13{reg_A[64]}},reg_A[64:66]};
result[80:95]<={{13{reg_A[80]}},reg_A[80:82]};
result[96:111]<={{13{reg_A[96]}},reg_A[96:98]};
result[112:127]<={{13{reg_A[112]}},reg_A[112:114]};
end
4'd14:
begin
result[0:15]<={{14{reg_A[0]}},reg_A[0:1]};
result[16:31]<={{14{reg_A[16]}},reg_A[16:17]};
result[32:47]<={{14{reg_A[32]}},reg_A[32:33]};
result[48:63]<={{14{reg_A[48]}},reg_A[48:49]};
result[64:79]<={{14{reg_A[64]}},reg_A[64:65]};
result[80:95]<={{14{reg_A[80]}},reg_A[80:81]};
result[96:111]<={{14{reg_A[96]}},reg_A[96:97]};
result[112:127]<={{14{reg_A[112]}},reg_A[112:113]};
end
4'd15:
begin
result[0:15]<={{15{reg_A[0]}},reg_A[0]};
result[16:31]<={{15{reg_A[16]}},reg_A[16]};
result[32:47]<={{15{reg_A[32]}},reg_A[32]};
result[48:63]<={{15{reg_A[48]}},reg_A[48]};
result[64:79]<={{15{reg_A[64]}},reg_A[64]};
result[80:95]<={{15{reg_A[80]}},reg_A[80]};
result[96:111]<={{15{reg_A[96]}},reg_A[96]};
result[112:127]<={{15{reg_A[112]}},reg_A[112]};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={{reg_A[0]},reg_A[0:30]};
result[32:63]<={{reg_A[32]},reg_A[32:62]};
result[64:95]<={{reg_A[64]},reg_A[64:94]};
result[96:127]<={{reg_A[96]},reg_A[96:126]};
end
5'd2:
begin
result[0:31]<={{2{reg_A[0]}},reg_A[0:29]};
result[32:63]<={{2{reg_A[32]}},reg_A[32:61]};
result[64:95]<={{2{reg_A[64]}},reg_A[64:93]};
result[96:127]<={{2{reg_A[96]}},reg_A[96:125]};
end
5'd3:
begin
result[0:31]<={{3{reg_A[0]}},reg_A[0:28]};
result[32:63]<={{3{reg_A[32]}},reg_A[32:60]};
result[64:95]<={{3{reg_A[64]}},reg_A[64:92]};
result[96:127]<={{3{reg_A[96]}},reg_A[96:124]};
end
5'd4:
begin
result[0:31]<={{4{reg_A[0]}},reg_A[0:27]};
result[32:63]<={{4{reg_A[32]}},reg_A[32:59]};
result[64:95]<={{4{reg_A[64]}},reg_A[64:91]};
result[96:127]<={{4{reg_A[96]}},reg_A[96:123]};
end
5'd5:
begin
result[0:31]<={{5{reg_A[0]}},reg_A[0:26]};
result[32:63]<={{5{reg_A[32]}},reg_A[32:58]};
result[64:95]<={{5{reg_A[64]}},reg_A[64:90]};
result[96:127]<={{5{reg_A[96]}},reg_A[96:122]};
end
5'd6:
begin
result[0:31]<={{6{reg_A[0]}},reg_A[0:25]};
result[32:63]<={{6{reg_A[32]}},reg_A[32:57]};
result[64:95]<={{6{reg_A[64]}},reg_A[64:89]};
result[96:127]<={{6{reg_A[96]}},reg_A[96:121]};
end
5'd7:
begin
result[0:31]<={{7{reg_A[0]}},reg_A[0:24]};
result[32:63]<={{7{reg_A[32]}},reg_A[32:56]};
result[64:95]<={{7{reg_A[64]}},reg_A[64:88]};
result[96:127]<={{7{reg_A[96]}},reg_A[96:120]};
end
5'd8:
begin
result[0:31]<={{8{reg_A[0]}},reg_A[0:23]};
result[32:63]<={{8{reg_A[32]}},reg_A[32:55]};
result[64:95]<={{8{reg_A[64]}},reg_A[64:87]};
result[96:127]<={{8{reg_A[96]}},reg_A[96:119]};
end
5'd9:
begin
result[0:31]<={{9{reg_A[0]}},reg_A[0:22]};
result[32:63]<={{9{reg_A[32]}},reg_A[32:54]};
result[64:95]<={{9{reg_A[64]}},reg_A[64:86]};
result[96:127]<={{9{reg_A[96]}},reg_A[96:118]};
end
5'd10:
begin
result[0:31]<={{10{reg_A[0]}},reg_A[0:21]};
result[32:63]<={{10{reg_A[32]}},reg_A[32:53]};
result[64:95]<={{10{reg_A[64]}},reg_A[64:85]};
result[96:127]<={{10{reg_A[96]}},reg_A[96:117]};
end
5'd11:
begin
result[0:31]<={{11{reg_A[0]}},reg_A[0:20]};
result[32:63]<={{11{reg_A[32]}},reg_A[32:52]};
result[64:95]<={{11{reg_A[64]}},reg_A[64:84]};
result[96:127]<={{11{reg_A[96]}},reg_A[96:116]};
end
5'd12:
begin
result[0:31]<={{12{reg_A[0]}},reg_A[0:19]};
result[32:63]<={{12{reg_A[32]}},reg_A[32:51]};
result[64:95]<={{12{reg_A[64]}},reg_A[64:83]};
result[96:127]<={{12{reg_A[96]}},reg_A[96:115]};
end
5'd13:
begin
result[0:31]<={{13{reg_A[0]}},reg_A[0:18]};
result[32:63]<={{13{reg_A[32]}},reg_A[32:50]};
result[64:95]<={{13{reg_A[64]}},reg_A[64:82]};
result[96:127]<={{13{reg_A[96]}},reg_A[96:114]};
end
5'd14:
begin
result[0:31]<={{14{reg_A[0]}},reg_A[0:17]};
result[32:63]<={{14{reg_A[32]}},reg_A[32:49]};
result[64:95]<={{14{reg_A[64]}},reg_A[64:81]};
result[96:127]<={{14{reg_A[96]}},reg_A[96:113]};
end
5'd15:
begin
result[0:31]<={{15{reg_A[0]}},reg_A[0:16]};
result[32:63]<={{15{reg_A[32]}},reg_A[32:48]};
result[64:95]<={{15{reg_A[64]}},reg_A[64:80]};
result[96:127]<={{15{reg_A[96]}},reg_A[96:112]};
end
5'd16:
begin
result[0:31]<={{16{reg_A[0]}},reg_A[0:15]};
result[32:63]<={{16{reg_A[32]}},reg_A[32:47]};
result[64:95]<={{16{reg_A[64]}},reg_A[64:79]};
result[96:127]<={{16{reg_A[96]}},reg_A[96:111]};
end
5'd17:
begin
result[0:31]<={{17{reg_A[0]}},reg_A[0:14]};
result[32:63]<={{17{reg_A[32]}},reg_A[32:46]};
result[64:95]<={{17{reg_A[64]}},reg_A[64:78]};
result[96:127]<={{17{reg_A[96]}},reg_A[96:110]};
end
5'd18:
begin
result[0:31]<={{18{reg_A[0]}},reg_A[0:13]};
result[32:63]<={{18{reg_A[32]}},reg_A[32:45]};
result[64:95]<={{18{reg_A[64]}},reg_A[64:77]};
result[96:127]<={{18{reg_A[96]}},reg_A[96:109]};
end
5'd19:
begin
result[0:31]<={{19{reg_A[0]}},reg_A[0:12]};
result[32:63]<={{19{reg_A[32]}},reg_A[32:44]};
result[64:95]<={{19{reg_A[64]}},reg_A[64:76]};
result[96:127]<={{19{reg_A[96]}},reg_A[96:108]};
end
5'd20:
begin
result[0:31]<={{20{reg_A[0]}},reg_A[0:11]};
result[32:63]<={{20{reg_A[32]}},reg_A[32:43]};
result[64:95]<={{20{reg_A[64]}},reg_A[64:75]};
result[96:127]<={{20{reg_A[96]}},reg_A[96:107]};
end
5'd21:
begin
result[0:31]<={{21{reg_A[0]}},reg_A[0:10]};
result[32:63]<={{21{reg_A[32]}},reg_A[32:42]};
result[64:95]<={{21{reg_A[64]}},reg_A[64:74]};
result[96:127]<={{21{reg_A[96]}},reg_A[96:106]};
end
5'd22:
begin
result[0:31]<={{22{reg_A[0]}},reg_A[0:9]};
result[32:63]<={{22{reg_A[32]}},reg_A[32:41]};
result[64:95]<={{22{reg_A[64]}},reg_A[64:73]};
result[96:127]<={{22{reg_A[96]}},reg_A[96:105]};
end
5'd23:
begin
result[0:31]<={{23{reg_A[0]}},reg_A[0:8]};
result[32:63]<={{23{reg_A[32]}},reg_A[32:40]};
result[64:95]<={{23{reg_A[64]}},reg_A[64:72]};
result[96:127]<={{23{reg_A[96]}},reg_A[96:104]};
end
5'd24:
begin
result[0:31]<={{24{reg_A[0]}},reg_A[0:7]};
result[32:63]<={{24{reg_A[32]}},reg_A[32:39]};
result[64:95]<={{24{reg_A[64]}},reg_A[64:71]};
result[96:127]<={{24{reg_A[96]}},reg_A[96:103]};
end
5'd25:
begin
result[0:31]<={{25{reg_A[0]}},reg_A[0:6]};
result[32:63]<={{25{reg_A[32]}},reg_A[32:38]};
result[64:95]<={{25{reg_A[64]}},reg_A[64:70]};
result[96:127]<={{25{reg_A[96]}},reg_A[96:102]};
end
5'd26:
begin
result[0:31]<={{26{reg_A[0]}},reg_A[0:5]};
result[32:63]<={{26{reg_A[32]}},reg_A[32:37]};
result[64:95]<={{26{reg_A[64]}},reg_A[64:69]};
result[96:127]<={{26{reg_A[96]}},reg_A[96:101]};
end
5'd27:
begin
result[0:31]<={{27{reg_A[0]}},reg_A[0:4]};
result[32:63]<={{27{reg_A[32]}},reg_A[32:36]};
result[64:95]<={{27{reg_A[64]}},reg_A[64:68]};
result[96:127]<={{27{reg_A[96]}},reg_A[96:100]};
end
5'd28:
begin
result[0:31]<={{28{reg_A[0]}},reg_A[0:3]};
result[32:63]<={{28{reg_A[32]}},reg_A[32:35]};
result[64:95]<={{28{reg_A[64]}},reg_A[64:67]};
result[96:127]<={{28{reg_A[96]}},reg_A[96:99]};
end
5'd29:
begin
result[0:31]<={{29{reg_A[0]}},reg_A[0:2]};
result[32:63]<={{29{reg_A[32]}},reg_A[32:34]};
result[64:95]<={{29{reg_A[64]}},reg_A[64:66]};
result[96:127]<={{29{reg_A[96]}},reg_A[96:98]};
end
5'd30:
begin
result[0:31]<={{30{reg_A[0]}},reg_A[0:1]};
result[32:63]<={{30{reg_A[32]}},reg_A[32:33]};
result[64:95]<={{30{reg_A[64]}},reg_A[64:65]};
result[96:127]<={{30{reg_A[96]}},reg_A[96:97]};
end
5'd31:
begin
result[0:31]<={{31{reg_A[0]}},reg_A[0]};
result[32:63]<={{31{reg_A[32]}},reg_A[32]};
result[64:95]<={{31{reg_A[64]}},reg_A[64]};
result[96:127]<={{31{reg_A[96]}},reg_A[96]};
end
endcase
end
endcase
end
// ==============================================================
// SRA instruction
`aluwsra:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[5:7]) // byte 0
3'd0:
result[0:7]<=reg_A[0:7];
3'd1:
result[0:7]<={{1{reg_A[0]}},reg_A[0:6]};
3'd2:
result[0:7]<={{2{reg_A[0]}},reg_A[0:5]};
3'd3:
result[0:7]<={{3{reg_A[0]}},reg_A[0:4]};
3'd4:
result[0:7]<={{4{reg_A[0]}},reg_A[0:3]};
3'd5:
result[0:7]<={{5{reg_A[0]}},reg_A[0:2]};
3'd6:
result[0:7]<={{6{reg_A[0]}},reg_A[0:1]};
3'd7:
result[0:7]<={{7{reg_A[0]}},reg_A[0]};
endcase
case(reg_B[13:15]) // byte 1
3'd0:
result[8:15]<=reg_A[8:15];
3'd1:
result[8:15]<={{1{reg_A[8]}},reg_A[8:14]};
3'd2:
result[8:15]<={{2{reg_A[8]}},reg_A[8:13]};
3'd3:
result[8:15]<={{3{reg_A[8]}},reg_A[8:12]};
3'd4:
result[8:15]<={{4{reg_A[8]}},reg_A[8:11]};
3'd5:
result[8:15]<={{5{reg_A[8]}},reg_A[8:10]};
3'd6:
result[8:15]<={{6{reg_A[8]}},reg_A[8:9]};
3'd7:
result[8:15]<={{7{reg_A[8]}},reg_A[8]};
endcase
case(reg_B[21:23]) // byte 2
3'd0:
result[16:23]<=reg_A[16:23];
3'd1:
result[16:23]<={{1{reg_A[16]}},reg_A[16:22]};
3'd2:
result[16:23]<={{2{reg_A[16]}},reg_A[16:21]};
3'd3:
result[16:23]<={{3{reg_A[16]}},reg_A[16:20]};
3'd4:
result[16:23]<={{4{reg_A[16]}},reg_A[16:19]};
3'd5:
result[16:23]<={{5{reg_A[16]}},reg_A[16:18]};
3'd6:
result[16:23]<={{6{reg_A[16]}},reg_A[16:17]};
3'd7:
result[16:23]<={{7{reg_A[16]}},reg_A[16]};
endcase
case(reg_B[29:31]) // byte 3
3'd0:
result[24:31]<=reg_A[24:31];
3'd1:
result[24:31]<={{1{reg_A[24]}},reg_A[24:30]};
3'd2:
result[24:31]<={{2{reg_A[24]}},reg_A[24:29]};
3'd3:
result[24:31]<={{3{reg_A[24]}},reg_A[24:28]};
3'd4:
result[24:31]<={{4{reg_A[24]}},reg_A[24:27]};
3'd5:
result[24:31]<={{5{reg_A[24]}},reg_A[24:26]};
3'd6:
result[24:31]<={{6{reg_A[24]}},reg_A[24:25]};
3'd7:
result[24:31]<={{7{reg_A[24]}},reg_A[24]};
endcase
case(reg_B[37:39]) // byte 4
3'd0:
result[32:39]<=reg_A[32:39];
3'd1:
result[32:39]<={{1{reg_A[32]}},reg_A[32:38]};
3'd2:
result[32:39]<={{2{reg_A[32]}},reg_A[32:37]};
3'd3:
result[32:39]<={{3{reg_A[32]}},reg_A[32:36]};
3'd4:
result[32:39]<={{4{reg_A[32]}},reg_A[32:35]};
3'd5:
result[32:39]<={{5{reg_A[32]}},reg_A[32:34]};
3'd6:
result[32:39]<={{6{reg_A[32]}},reg_A[32:33]};
3'd7:
result[32:39]<={{7{reg_A[32]}},reg_A[32]};
endcase
case(reg_B[45:47]) // byte 5
3'd0:
result[40:47]<=reg_A[40:47];
3'd1:
result[40:47]<={{1{reg_A[40]}},reg_A[40:46]};
3'd2:
result[40:47]<={{2{reg_A[40]}},reg_A[40:45]};
3'd3:
result[40:47]<={{3{reg_A[40]}},reg_A[40:44]};
3'd4:
result[40:47]<={{4{reg_A[40]}},reg_A[40:43]};
3'd5:
result[40:47]<={{5{reg_A[40]}},reg_A[40:42]};
3'd6:
result[40:47]<={{6{reg_A[40]}},reg_A[40:41]};
3'd7:
result[40:47]<={{7{reg_A[40]}},reg_A[40]};
endcase
case(reg_B[53:55]) // byte 6
3'd0:
result[48:55]<=reg_A[48:55];
3'd1:
result[48:55]<={{1{reg_A[48]}},reg_A[48:54]};
3'd2:
result[48:55]<={{2{reg_A[48]}},reg_A[48:53]};
3'd3:
result[48:55]<={{3{reg_A[48]}},reg_A[48:52]};
3'd4:
result[48:55]<={{4{reg_A[48]}},reg_A[48:51]};
3'd5:
result[48:55]<={{5{reg_A[48]}},reg_A[48:50]};
3'd6:
result[48:55]<={{6{reg_A[48]}},reg_A[48:49]};
3'd7:
result[48:55]<={{7{reg_A[48]}},reg_A[48]};
endcase
case(reg_B[61:63]) // byte 7
3'd0:
result[56:63]<=reg_A[56:63];
3'd1:
result[56:63]<={{1{reg_A[56]}},reg_A[56:62]};
3'd2:
result[56:63]<={{2{reg_A[56]}},reg_A[56:61]};
3'd3:
result[56:63]<={{3{reg_A[56]}},reg_A[56:60]};
3'd4:
result[56:63]<={{4{reg_A[56]}},reg_A[56:59]};
3'd5:
result[56:63]<={{5{reg_A[56]}},reg_A[56:58]};
3'd6:
result[56:63]<={{6{reg_A[56]}},reg_A[56:57]};
3'd7:
result[56:63]<={{7{reg_A[56]}},reg_A[56]};
endcase
case(reg_B[69:71]) // byte 8
3'd0:
result[64:71]<=reg_A[64:71];
3'd1:
result[64:71]<={{1{reg_A[64]}},reg_A[64:70]};
3'd2:
result[64:71]<={{2{reg_A[64]}},reg_A[64:69]};
3'd3:
result[64:71]<={{3{reg_A[64]}},reg_A[64:68]};
3'd4:
result[64:71]<={{4{reg_A[64]}},reg_A[64:67]};
3'd5:
result[64:71]<={{5{reg_A[64]}},reg_A[64:66]};
3'd6:
result[64:71]<={{6{reg_A[64]}},reg_A[64:65]};
3'd7:
result[64:71]<={{7{reg_A[64]}},reg_A[64]};
endcase
case(reg_B[77:79]) // byte 9
3'd0:
result[72:79]<=reg_A[72:79];
3'd1:
result[72:79]<={{1{reg_A[72]}},reg_A[72:78]};
3'd2:
result[72:79]<={{2{reg_A[72]}},reg_A[72:77]};
3'd3:
result[72:79]<={{3{reg_A[72]}},reg_A[72:76]};
3'd4:
result[72:79]<={{4{reg_A[72]}},reg_A[72:75]};
3'd5:
result[72:79]<={{5{reg_A[72]}},reg_A[72:74]};
3'd6:
result[72:79]<={{6{reg_A[72]}},reg_A[72:73]};
3'd7:
result[72:79]<={{7{reg_A[72]}},reg_A[72]};
endcase
case(reg_B[85:87]) // byte 10
3'd0:
result[80:87]<=reg_A[80:87];
3'd1:
result[80:87]<={{1{reg_A[80]}},reg_A[80:86]};
3'd2:
result[80:87]<={{2{reg_A[80]}},reg_A[80:85]};
3'd3:
result[80:87]<={{3{reg_A[80]}},reg_A[80:84]};
3'd4:
result[80:87]<={{4{reg_A[80]}},reg_A[80:83]};
3'd5:
result[80:87]<={{5{reg_A[80]}},reg_A[80:82]};
3'd6:
result[80:87]<={{6{reg_A[80]}},reg_A[80:81]};
3'd7:
result[80:87]<={{7{reg_A[80]}},reg_A[80]};
endcase
case(reg_B[93:95]) // byte 11
3'd0:
result[88:95]<=reg_A[88:95];
3'd1:
result[88:95]<={{1{reg_A[88]}},reg_A[88:94]};
3'd2:
result[88:95]<={{2{reg_A[88]}},reg_A[88:93]};
3'd3:
result[88:95]<={{3{reg_A[88]}},reg_A[88:92]};
3'd4:
result[88:95]<={{4{reg_A[88]}},reg_A[88:91]};
3'd5:
result[88:95]<={{5{reg_A[88]}},reg_A[88:90]};
3'd6:
result[88:95]<={{6{reg_A[88]}},reg_A[88:89]};
3'd7:
result[88:95]<={{7{reg_A[88]}},reg_A[88]};
endcase
case(reg_B[101:103]) // byte 12
3'd0:
result[96:103]<=reg_A[96:103];
3'd1:
result[96:103]<={{1{reg_A[96]}},reg_A[96:102]};
3'd2:
result[96:103]<={{2{reg_A[96]}},reg_A[96:101]};
3'd3:
result[96:103]<={{3{reg_A[96]}},reg_A[96:100]};
3'd4:
result[96:103]<={{4{reg_A[96]}},reg_A[96:99]};
3'd5:
result[96:103]<={{5{reg_A[96]}},reg_A[96:98]};
3'd6:
result[96:103]<={{6{reg_A[96]}},reg_A[96:97]};
3'd7:
result[96:103]<={{7{reg_A[96]}},reg_A[96]};
endcase
case(reg_B[109:111]) // byte 13
3'd0:
result[104:111]<=reg_A[104:111];
3'd1:
result[104:111]<={{1{reg_A[104]}},reg_A[104:110]};
3'd2:
result[104:111]<={{2{reg_A[104]}},reg_A[104:109]};
3'd3:
result[104:111]<={{3{reg_A[104]}},reg_A[104:108]};
3'd4:
result[104:111]<={{4{reg_A[104]}},reg_A[104:107]};
3'd5:
result[104:111]<={{5{reg_A[104]}},reg_A[104:106]};
3'd6:
result[104:111]<={{6{reg_A[104]}},reg_A[104:105]};
3'd7:
result[104:111]<={{7{reg_A[104]}},reg_A[104]};
endcase
case(reg_B[117:119]) // byte 14
3'd0:
result[112:119]<=reg_A[112:119];
3'd1:
result[112:119]<={{1{reg_A[112]}},reg_A[112:118]};
3'd2:
result[112:119]<={{2{reg_A[112]}},reg_A[112:117]};
3'd3:
result[112:119]<={{3{reg_A[112]}},reg_A[112:116]};
3'd4:
result[112:119]<={{4{reg_A[112]}},reg_A[112:115]};
3'd5:
result[112:119]<={{5{reg_A[112]}},reg_A[112:114]};
3'd6:
result[112:119]<={{6{reg_A[112]}},reg_A[112:113]};
3'd7:
result[112:119]<={{7{reg_A[112]}},reg_A[112]};
endcase
case(reg_B[125:127]) // byte 15
3'd0:
result[120:127]<=reg_A[120:127];
3'd1:
result[120:127]<={{1{reg_A[120]}},reg_A[120:126]};
3'd2:
result[120:127]<={{2{reg_A[120]}},reg_A[120:125]};
3'd3:
result[120:127]<={{3{reg_A[120]}},reg_A[120:124]};
3'd4:
result[120:127]<={{4{reg_A[120]}},reg_A[120:123]};
3'd5:
result[120:127]<={{5{reg_A[120]}},reg_A[120:122]};
3'd6:
result[120:127]<={{6{reg_A[120]}},reg_A[120:121]};
3'd7:
result[120:127]<={{7{reg_A[120]}},reg_A[120]};
endcase
end
`w16:
begin
case(reg_B[12:15]) // word0
4'd0:
result[0:15]<=reg_A[0:15];
4'd1:
result[0:15]<={{1{reg_A[0]}},reg_A[0:14]};
4'd2:
result[0:15]<={{2{reg_A[0]}},reg_A[0:13]};
4'd3:
result[0:15]<={{3{reg_A[0]}},reg_A[0:12]};
4'd4:
result[0:15]<={{4{reg_A[0]}},reg_A[0:11]};
4'd5:
result[0:15]<={{5{reg_A[0]}},reg_A[0:10]};
4'd6:
result[0:15]<={{6{reg_A[0]}},reg_A[0:9]};
4'd7:
result[0:15]<={{7{reg_A[0]}},reg_A[0:8]};
4'd8:
result[0:15]<={{8{reg_A[0]}},reg_A[0:7]};
4'd9:
result[0:15]<={{9{reg_A[0]}},reg_A[0:6]};
4'd10:
result[0:15]<={{10{reg_A[0]}},reg_A[0:5]};
4'd11:
result[0:15]<={{11{reg_A[0]}},reg_A[0:4]};
4'd12:
result[0:15]<={{12{reg_A[0]}},reg_A[0:3]};
4'd13:
result[0:15]<={{13{reg_A[0]}},reg_A[0:2]};
4'd14:
result[0:15]<={{14{reg_A[0]}},reg_A[0:1]};
4'd15:
result[0:15]<={{15{reg_A[0]}},reg_A[0]};
endcase
case(reg_B[28:31]) //word1
4'd0:
result[16:31]<=reg_A[16:31];
4'd1:
result[16:31]<={{1{reg_A[16]}},reg_A[16:30]};
4'd2:
result[16:31]<={{2{reg_A[16]}},reg_A[16:29]};
4'd3:
result[16:31]<={{3{reg_A[16]}},reg_A[16:28]};
4'd4:
result[16:31]<={{4{reg_A[16]}},reg_A[16:27]};
4'd5:
result[16:31]<={{5{reg_A[16]}},reg_A[16:26]};
4'd6:
result[16:31]<={{6{reg_A[16]}},reg_A[16:25]};
4'd7:
result[16:31]<={{7{reg_A[16]}},reg_A[16:24]};
4'd8:
result[16:31]<={{8{reg_A[16]}},reg_A[16:23]};
4'd9:
result[16:31]<={{9{reg_A[16]}},reg_A[16:22]};
4'd10:
result[16:31]<={{10{reg_A[16]}},reg_A[16:21]};
4'd11:
result[16:31]<={{11{reg_A[16]}},reg_A[16:20]};
4'd12:
result[16:31]<={{12{reg_A[16]}},reg_A[16:19]};
4'd13:
result[16:31]<={{13{reg_A[16]}},reg_A[16:18]};
4'd14:
result[16:31]<={{14{reg_A[16]}},reg_A[16:17]};
4'd15:
result[16:31]<={{15{reg_A[16]}},reg_A[16]};
endcase
case(reg_B[44:47]) // word2
4'd0:
result[32:47]<=reg_A[32:47];
4'd1:
result[32:47]<={{1{reg_A[32]}},reg_A[32:46]};
4'd2:
result[32:47]<={{2{reg_A[32]}},reg_A[32:45]};
4'd3:
result[32:47]<={{3{reg_A[32]}},reg_A[32:44]};
4'd4:
result[32:47]<={{4{reg_A[32]}},reg_A[32:43]};
4'd5:
result[32:47]<={{5{reg_A[32]}},reg_A[32:42]};
4'd6:
result[32:47]<={{6{reg_A[32]}},reg_A[32:41]};
4'd7:
result[32:47]<={{7{reg_A[32]}},reg_A[32:40]};
4'd8:
result[32:47]<={{8{reg_A[32]}},reg_A[32:39]};
4'd9:
result[32:47]<={{9{reg_A[32]}},reg_A[32:38]};
4'd10:
result[32:47]<={{10{reg_A[32]}},reg_A[32:37]};
4'd11:
result[32:47]<={{11{reg_A[32]}},reg_A[32:36]};
4'd12:
result[32:47]<={{12{reg_A[32]}},reg_A[32:35]};
4'd13:
result[32:47]<={{13{reg_A[32]}},reg_A[32:34]};
4'd14:
result[32:47]<={{14{reg_A[32]}},reg_A[32:33]};
4'd15:
result[32:47]<={{15{reg_A[32]}},reg_A[32]};
endcase
case(reg_B[60:63]) // word3
4'd0:
result[48:63]<=reg_A[48:63];
4'd1:
result[48:63]<={{1{reg_A[48]}},reg_A[48:62]};
4'd2:
result[48:63]<={{2{reg_A[48]}},reg_A[48:61]};
4'd3:
result[48:63]<={{3{reg_A[48]}},reg_A[48:60]};
4'd4:
result[48:63]<={{4{reg_A[48]}},reg_A[48:59]};
4'd5:
result[48:63]<={{5{reg_A[48]}},reg_A[48:58]};
4'd6:
result[48:63]<={{6{reg_A[48]}},reg_A[48:57]};
4'd7:
result[48:63]<={{7{reg_A[48]}},reg_A[48:56]};
4'd8:
result[48:63]<={{8{reg_A[48]}},reg_A[48:55]};
4'd9:
result[48:63]<={{9{reg_A[48]}},reg_A[48:54]};
4'd10:
result[48:63]<={{10{reg_A[48]}},reg_A[48:53]};
4'd11:
result[48:63]<={{11{reg_A[48]}},reg_A[48:52]};
4'd12:
result[48:63]<={{12{reg_A[48]}},reg_A[48:51]};
4'd13:
result[48:63]<={{13{reg_A[48]}},reg_A[48:50]};
4'd14:
result[48:63]<={{14{reg_A[48]}},reg_A[48:49]};
4'd15:
result[48:63]<={{15{reg_A[48]}},reg_A[48]};
endcase
case(reg_B[76:79]) // word4
4'd0:
result[64:79]<=reg_A[64:79];
4'd1:
result[64:79]<={{1{reg_A[64]}},reg_A[64:78]};
4'd2:
result[64:79]<={{2{reg_A[64]}},reg_A[64:77]};
4'd3:
result[64:79]<={{3{reg_A[64]}},reg_A[64:76]};
4'd4:
result[64:79]<={{4{reg_A[64]}},reg_A[64:75]};
4'd5:
result[64:79]<={{5{reg_A[64]}},reg_A[64:74]};
4'd6:
result[64:79]<={{6{reg_A[64]}},reg_A[64:73]};
4'd7:
result[64:79]<={{7{reg_A[64]}},reg_A[64:72]};
4'd8:
result[64:79]<={{8{reg_A[64]}},reg_A[64:71]};
4'd9:
result[64:79]<={{9{reg_A[64]}},reg_A[64:70]};
4'd10:
result[64:79]<={{10{reg_A[64]}},reg_A[64:69]};
4'd11:
result[64:79]<={{11{reg_A[64]}},reg_A[64:68]};
4'd12:
result[64:79]<={{12{reg_A[64]}},reg_A[64:67]};
4'd13:
result[64:79]<={{13{reg_A[64]}},reg_A[64:66]};
4'd14:
result[64:79]<={{14{reg_A[64]}},reg_A[64:65]};
4'd15:
result[64:79]<={{15{reg_A[64]}},reg_A[64]};
endcase
case(reg_B[92:95]) // word5
4'd0:
result[80:95]<=reg_A[80:95];
4'd1:
result[80:95]<={{1{reg_A[80]}},reg_A[80:94]};
4'd2:
result[80:95]<={{2{reg_A[80]}},reg_A[80:93]};
4'd3:
result[80:95]<={{3{reg_A[80]}},reg_A[80:92]};
4'd4:
result[80:95]<={{4{reg_A[80]}},reg_A[80:91]};
4'd5:
result[80:95]<={{5{reg_A[80]}},reg_A[80:90]};
4'd6:
result[80:95]<={{6{reg_A[80]}},reg_A[80:89]};
4'd7:
result[80:95]<={{7{reg_A[80]}},reg_A[80:88]};
4'd8:
result[80:95]<={{8{reg_A[80]}},reg_A[80:87]};
4'd9:
result[80:95]<={{9{reg_A[80]}},reg_A[80:86]};
4'd10:
result[80:95]<={{10{reg_A[80]}},reg_A[80:85]};
4'd11:
result[80:95]<={{11{reg_A[80]}},reg_A[80:84]};
4'd12:
result[80:95]<={{12{reg_A[80]}},reg_A[80:83]};
4'd13:
result[80:95]<={{13{reg_A[80]}},reg_A[80:82]};
4'd14:
result[80:95]<={{14{reg_A[80]}},reg_A[80:81]};
4'd15:
result[80:95]<={{15{reg_A[80]}},reg_A[80]};
endcase
case(reg_B[92:111]) // word6
4'd0:
result[96:111]<=reg_A[96:111];
4'd1:
result[96:111]<={{1{reg_A[96]}},reg_A[96:110]};
4'd2:
result[96:111]<={{2{reg_A[96]}},reg_A[96:109]};
4'd3:
result[96:111]<={{3{reg_A[96]}},reg_A[96:108]};
4'd4:
result[96:111]<={{4{reg_A[96]}},reg_A[96:107]};
4'd5:
result[96:111]<={{5{reg_A[96]}},reg_A[96:106]};
4'd6:
result[96:111]<={{6{reg_A[96]}},reg_A[96:105]};
4'd7:
result[96:111]<={{7{reg_A[96]}},reg_A[96:104]};
4'd8:
result[96:111]<={{8{reg_A[96]}},reg_A[96:103]};
4'd9:
result[96:111]<={{9{reg_A[96]}},reg_A[96:102]};
4'd10:
result[96:111]<={{10{reg_A[96]}},reg_A[96:101]};
4'd11:
result[96:111]<={{11{reg_A[96]}},reg_A[96:100]};
4'd12:
result[96:111]<={{12{reg_A[96]}},reg_A[96:99]};
4'd13:
result[96:111]<={{13{reg_A[96]}},reg_A[96:98]};
4'd14:
result[96:111]<={{14{reg_A[96]}},reg_A[96:97]};
4'd15:
result[96:111]<={{15{reg_A[96]}},reg_A[96]};
endcase
case(reg_B[92:127]) // word7
4'd0:
result[112:127]<=reg_A[112:127];
4'd1:
result[112:127]<={{1{reg_A[112]}},reg_A[112:126]};
4'd2:
result[112:127]<={{2{reg_A[112]}},reg_A[112:125]};
4'd3:
result[112:127]<={{3{reg_A[112]}},reg_A[112:124]};
4'd4:
result[112:127]<={{4{reg_A[112]}},reg_A[112:123]};
4'd5:
result[112:127]<={{5{reg_A[112]}},reg_A[112:122]};
4'd6:
result[112:127]<={{6{reg_A[112]}},reg_A[112:121]};
4'd7:
result[112:127]<={{7{reg_A[112]}},reg_A[112:120]};
4'd8:
result[112:127]<={{8{reg_A[112]}},reg_A[112:119]};
4'd9:
result[112:127]<={{9{reg_A[112]}},reg_A[112:118]};
4'd10:
result[112:127]<={{10{reg_A[112]}},reg_A[112:117]};
4'd11:
result[112:127]<={{11{reg_A[112]}},reg_A[112:116]};
4'd12:
result[112:127]<={{12{reg_A[112]}},reg_A[112:115]};
4'd13:
result[112:127]<={{13{reg_A[112]}},reg_A[112:114]};
4'd14:
result[112:127]<={{14{reg_A[112]}},reg_A[112:113]};
4'd15:
result[112:127]<={{15{reg_A[112]}},reg_A[112]};
endcase
end
`w32:
begin
case(reg_B[27:31])
5'd0:
result[0:31]<=reg_A[0:31];
5'd1:
result[0:31]<={{1{reg_A[0]}},reg_A[0:30]};
5'd2:
result[0:31]<={{2{reg_A[0]}},reg_A[0:29]};
5'd3:
result[0:31]<={{3{reg_A[0]}},reg_A[0:28]};
5'd4:
result[0:31]<={{4{reg_A[0]}},reg_A[0:27]};
5'd5:
result[0:31]<={{5{reg_A[0]}},reg_A[0:26]};
5'd6:
result[0:31]<={{6{reg_A[0]}},reg_A[0:25]};
5'd7:
result[0:31]<={{7{reg_A[0]}},reg_A[0:24]};
5'd8:
result[0:31]<={{8{reg_A[0]}},reg_A[0:23]};
5'd9:
result[0:31]<={{9{reg_A[0]}},reg_A[0:22]};
5'd10:
result[0:31]<={{10{reg_A[0]}},reg_A[0:21]};
5'd11:
result[0:31]<={{11{reg_A[0]}},reg_A[0:20]};
5'd12:
result[0:31]<={{12{reg_A[0]}},reg_A[0:19]};
5'd13:
result[0:31]<={{13{reg_A[0]}},reg_A[0:18]};
5'd14:
result[0:31]<={{14{reg_A[0]}},reg_A[0:17]};
5'd15:
result[0:31]<={{15{reg_A[0]}},reg_A[0:16]};
5'd16:
result[0:31]<={{16{reg_A[0]}},reg_A[0:15]};
5'd17:
result[0:31]<={{17{reg_A[0]}},reg_A[0:14]};
5'd18:
result[0:31]<={{18{reg_A[0]}},reg_A[0:13]};
5'd19:
result[0:31]<={{19{reg_A[0]}},reg_A[0:12]};
5'd20:
result[0:31]<={{20{reg_A[0]}},reg_A[0:11]};
5'd21:
result[0:31]<={{21{reg_A[0]}},reg_A[0:10]};
5'd22:
result[0:31]<={{22{reg_A[0]}},reg_A[0:9]};
5'd23:
result[0:31]<={{23{reg_A[0]}},reg_A[0:8]};
5'd24:
result[0:31]<={{24{reg_A[0]}},reg_A[0:7]};
5'd25:
result[0:31]<={{25{reg_A[0]}},reg_A[0:6]};
5'd26:
result[0:31]<={{26{reg_A[0]}},reg_A[0:5]};
5'd27:
result[0:31]<={{27{reg_A[0]}},reg_A[0:4]};
5'd28:
result[0:31]<={{28{reg_A[0]}},reg_A[0:3]};
5'd29:
result[0:31]<={{29{reg_A[0]}},reg_A[0:2]};
5'd30:
result[0:31]<={{30{reg_A[0]}},reg_A[0:1]};
5'd31:
result[0:31]<={{31{reg_A[0]}},reg_A[0]};
endcase
case(reg_B[59:63])
5'd0:
result[32:63]<=reg_A[32:63];
5'd1:
result[32:63]<={{1{reg_A[32]}},reg_A[32:62]};
5'd2:
result[32:63]<={{2{reg_A[32]}},reg_A[32:61]};
5'd3:
result[32:63]<={{3{reg_A[32]}},reg_A[32:60]};
5'd4:
result[32:63]<={{4{reg_A[32]}},reg_A[32:59]};
5'd5:
result[32:63]<={{5{reg_A[32]}},reg_A[32:58]};
5'd6:
result[32:63]<={{6{reg_A[32]}},reg_A[32:57]};
5'd7:
result[32:63]<={{7{reg_A[32]}},reg_A[32:56]};
5'd8:
result[32:63]<={{8{reg_A[32]}},reg_A[32:55]};
5'd9:
result[32:63]<={{9{reg_A[32]}},reg_A[32:54]};
5'd10:
result[32:63]<={{10{reg_A[32]}},reg_A[32:53]};
5'd11:
result[32:63]<={{11{reg_A[32]}},reg_A[32:52]};
5'd12:
result[32:63]<={{12{reg_A[32]}},reg_A[32:51]};
5'd13:
result[32:63]<={{13{reg_A[32]}},reg_A[32:50]};
5'd14:
result[32:63]<={{14{reg_A[32]}},reg_A[32:49]};
5'd15:
result[32:63]<={{15{reg_A[32]}},reg_A[32:48]};
5'd16:
result[32:63]<={{16{reg_A[32]}},reg_A[32:47]};
5'd17:
result[32:63]<={{17{reg_A[32]}},reg_A[32:46]};
5'd18:
result[32:63]<={{18{reg_A[32]}},reg_A[32:45]};
5'd19:
result[32:63]<={{19{reg_A[32]}},reg_A[32:44]};
5'd20:
result[32:63]<={{20{reg_A[32]}},reg_A[32:43]};
5'd21:
result[32:63]<={{21{reg_A[32]}},reg_A[32:42]};
5'd22:
result[32:63]<={{22{reg_A[32]}},reg_A[32:41]};
5'd23:
result[32:63]<={{23{reg_A[32]}},reg_A[32:40]};
5'd24:
result[32:63]<={{24{reg_A[32]}},reg_A[32:39]};
5'd25:
result[32:63]<={{25{reg_A[32]}},reg_A[32:38]};
5'd26:
result[32:63]<={{26{reg_A[32]}},reg_A[32:37]};
5'd27:
result[32:63]<={{27{reg_A[32]}},reg_A[32:36]};
5'd28:
result[32:63]<={{28{reg_A[32]}},reg_A[32:35]};
5'd29:
result[32:63]<={{29{reg_A[32]}},reg_A[32:34]};
5'd30:
result[32:63]<={{30{reg_A[32]}},reg_A[32:33]};
5'd31:
result[32:63]<={{31{reg_A[32]}},reg_A[32]};
endcase
case(reg_B[91:95])
5'd0:
result[64:95]<=reg_A[64:95];
5'd1:
result[64:95]<={{1{reg_A[64]}},reg_A[64:94]};
5'd2:
result[64:95]<={{2{reg_A[64]}},reg_A[64:93]};
5'd3:
result[64:95]<={{3{reg_A[64]}},reg_A[64:92]};
5'd4:
result[64:95]<={{4{reg_A[64]}},reg_A[64:91]};
5'd5:
result[64:95]<={{5{reg_A[64]}},reg_A[64:90]};
5'd6:
result[64:95]<={{6{reg_A[64]}},reg_A[64:89]};
5'd7:
result[64:95]<={{7{reg_A[64]}},reg_A[64:88]};
5'd8:
result[64:95]<={{8{reg_A[64]}},reg_A[64:87]};
5'd9:
result[64:95]<={{9{reg_A[64]}},reg_A[64:86]};
5'd10:
result[64:95]<={{10{reg_A[64]}},reg_A[64:85]};
5'd11:
result[64:95]<={{11{reg_A[64]}},reg_A[64:84]};
5'd12:
result[64:95]<={{12{reg_A[64]}},reg_A[64:83]};
5'd13:
result[64:95]<={{13{reg_A[64]}},reg_A[64:82]};
5'd14:
result[64:95]<={{14{reg_A[64]}},reg_A[64:81]};
5'd15:
result[64:95]<={{15{reg_A[64]}},reg_A[64:80]};
5'd16:
result[64:95]<={{16{reg_A[64]}},reg_A[64:79]};
5'd17:
result[64:95]<={{17{reg_A[64]}},reg_A[64:78]};
5'd18:
result[64:95]<={{18{reg_A[64]}},reg_A[64:77]};
5'd19:
result[64:95]<={{19{reg_A[64]}},reg_A[64:76]};
5'd20:
result[64:95]<={{20{reg_A[64]}},reg_A[64:75]};
5'd21:
result[64:95]<={{21{reg_A[64]}},reg_A[64:74]};
5'd22:
result[64:95]<={{22{reg_A[64]}},reg_A[64:73]};
5'd23:
result[64:95]<={{23{reg_A[64]}},reg_A[64:72]};
5'd24:
result[64:95]<={{24{reg_A[64]}},reg_A[64:71]};
5'd25:
result[64:95]<={{25{reg_A[64]}},reg_A[64:70]};
5'd26:
result[64:95]<={{26{reg_A[64]}},reg_A[64:69]};
5'd27:
result[64:95]<={{27{reg_A[64]}},reg_A[64:68]};
5'd28:
result[64:95]<={{28{reg_A[64]}},reg_A[64:67]};
5'd29:
result[64:95]<={{29{reg_A[64]}},reg_A[64:66]};
5'd30:
result[64:95]<={{30{reg_A[64]}},reg_A[64:65]};
5'd31:
result[64:95]<={{31{reg_A[64]}},reg_A[64]};
endcase
case(reg_B[123:127])
5'd0:
result[96:127]<=reg_A[96:127];
5'd1:
result[96:127]<={{1{reg_A[96]}},reg_A[96:126]};
5'd2:
result[96:127]<={{2{reg_A[96]}},reg_A[96:125]};
5'd3:
result[96:127]<={{3{reg_A[96]}},reg_A[96:124]};
5'd4:
result[96:127]<={{4{reg_A[96]}},reg_A[96:123]};
5'd5:
result[96:127]<={{5{reg_A[96]}},reg_A[96:122]};
5'd6:
result[96:127]<={{6{reg_A[96]}},reg_A[96:121]};
5'd7:
result[96:127]<={{7{reg_A[96]}},reg_A[96:120]};
5'd8:
result[96:127]<={{8{reg_A[96]}},reg_A[96:119]};
5'd9:
result[96:127]<={{9{reg_A[96]}},reg_A[96:118]};
5'd10:
result[96:127]<={{10{reg_A[96]}},reg_A[96:117]};
5'd11:
result[96:127]<={{11{reg_A[96]}},reg_A[96:116]};
5'd12:
result[96:127]<={{12{reg_A[96]}},reg_A[96:115]};
5'd13:
result[96:127]<={{13{reg_A[96]}},reg_A[96:114]};
5'd14:
result[96:127]<={{14{reg_A[96]}},reg_A[96:113]};
5'd15:
result[96:127]<={{15{reg_A[96]}},reg_A[96:112]};
5'd16:
result[96:127]<={{16{reg_A[96]}},reg_A[96:111]};
5'd17:
result[96:127]<={{17{reg_A[96]}},reg_A[96:110]};
5'd18:
result[96:127]<={{18{reg_A[96]}},reg_A[96:109]};
5'd19:
result[96:127]<={{19{reg_A[96]}},reg_A[96:108]};
5'd20:
result[96:127]<={{20{reg_A[96]}},reg_A[96:107]};
5'd21:
result[96:127]<={{21{reg_A[96]}},reg_A[96:106]};
5'd22:
result[96:127]<={{22{reg_A[96]}},reg_A[96:105]};
5'd23:
result[96:127]<={{23{reg_A[96]}},reg_A[96:104]};
5'd24:
result[96:127]<={{24{reg_A[96]}},reg_A[96:103]};
5'd25:
result[96:127]<={{25{reg_A[96]}},reg_A[96:102]};
5'd26:
result[96:127]<={{26{reg_A[96]}},reg_A[96:101]};
5'd27:
result[96:127]<={{27{reg_A[96]}},reg_A[96:100]};
5'd28:
result[96:127]<={{28{reg_A[96]}},reg_A[96:99]};
5'd29:
result[96:127]<={{29{reg_A[96]}},reg_A[96:98]};
5'd30:
result[96:127]<={{30{reg_A[96]}},reg_A[96:97]};
5'd31:
result[96:127]<={{31{reg_A[96]}},reg_A[96]};
endcase
end
endcase
end
// ==================================================================
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule
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