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`include "define.v"
module phase1_top(
input clk,
input rst
);
//here, you should instantiate and connect your PC, ALU, control, imemory, dmemory
//depending on your group organization, you may use more or fewer sub-modules, but
//you may not make *any* modifications to the given modules. During the demo, you
//may be asked to download fresh copies of the given files to verify that you did
//not make changes to those files in order to get your design working.
//IF
wire [15:0] pc_in_imem;
wire [15:0] pc_curr;
wire [15:0] pc_added;
wire [15:0] inst_curr;
//ID
wire [15:0] pc_added_IDIF;
wire [15:0] inst_curr_IDIF;
wire [3:0] inst_raddr1;
wire lhb_llb_regcon;
wire [15:0] mem_data_in;
wire [15:0] mem_data_out;
wire [15:0] alu_out_mem;
//ID control signals
wire[3:0] opcode;
wire dmem_wen;
wire rf_wen;
wire [2:0] alu_op;
wire alusrc;
wire regdest;
wire branch;
wire mem2reg;
//wire lhb_llb_1;
//wire lhb_llb_2;
wire dmem_wen_idex;
wire rf_wen_idex;
wire [2:0] alu_op_idex;
wire alusrc_idex;
wire regdest_idex;
//wire branch_idex;
wire mem2reg_idex;
//wire jr_adder_idex;
wire [15:0] rdata1_idex;
wire [15:0] rdata2_idex;
wire [15:0] extended_idex;
wire [15:0] pc_added_IDEX;
wire [15:0] pc_adder_out;
wire [15:0] inst_curr_IDEX;
wire control_lhb_llb_idex;
wire [15:0] rf_wdata;
wire [3:0] rf_waddr;
wire [15:0] rdata1, rdata2;
wire [15:0] extended;
wire [15:0] extended_1;
//wire [15:0] extended_JR;
wire [15:0] alu_second_input;
wire [15:0] signextended;
wire dmem_wen_exmem;
wire rf_wen_exmem;
//wire mem_branch_exmem;
wire mem2reg_exmem;
wire jr_adder_exmem;
wire [15:0] pc_adder_out_exmem;
wire [15:0] aluout_exmem;
wire [2:0] flag_exmem;
wire [15:0] rdata1_exmem;
wire [15:0] rdata2_exmem;
wire [3:0] rf_waddr_exmem;
wire [15:0] wdata_LHB_LLB;
//wire jr_rf;
//wire jr_adder;
wire [15:0] lhb_llb_out_exmem;
wire control_lhb_llb_exmem;
wire rf_wen_memwb;
wire mem2reg_memwb;
wire [3:0] rf_waddr_memwb;
wire [15:0] aluout_memwb;
wire [15:0] lhb_llb_out_data;
wire lhb_llb_control_memwb;
wire [15:0] rf_data_final;
wire [15:0] imm_final;
///EXE
wire [2:0] flag; //Z,V,N
//reg [2:0] flag_previous;
wire [15:0] aluout;
wire[15:0] extended_JAL;
wire[15:0] JAL_target_add_IDIF;
wire[15:0] JAL_target_add_IDEX;
wire[15:0] JAL_target_add_exmem;
wire JAL_control_jump_idex;
wire JAL_control_jump_exmem;
wire JAL_control_mux_final;
wire JAL_write_reg;
wire [15:0] pc_normal_added_out;
wire [15:0] lhb_llb_regval;
/// assigning opcode
assign opcode = inst_curr_IDIF[15:12];
wire [3:0] inst_raddr2;
wire [15:0] pc_in_mux_out, pc_in_mux_in, pc_in_mux_in_latest;
wire pcsrc;
wire s5;
//s7 is used for the final mux between mem/alu vs LLB
wire s6,s7;
wire [15:0] rf_wdata_bef_mux;
wire [15:0] aluout_or_lhbllb_memwb;
MUX16 mem2regMUX(.in0(aluout_memwb), .in1(mem_data_out),
.select(mem2reg_memwb), .out(rf_wdata_bef_mux));
//this is the last mux which compares the value of((ALU/Mem)vs LLB imm) and sends it to the regiter
wire s7_memwb;
wire [15:0] imm_16_0_memwb;
wire s7_exmem;
wire [15:0] pc_mux_out;
//wire [15:0] pc_added_idif;
//wire [15:0] pc_added_idex;
wire [15:0] pc_added_exmem;
wire [15:0] pc_added_memwb;
wire [15:0] branch_target_idex, branch_target_exmem;
/// Passing flag from ALU to Control
wire [2:0] flag_aluout;
wire [2:0] flag_controlexein;
wire [3:0] cond_IDIF;
assign flag_controlexein = flag_aluout;
assign cond_IDIF = inst_curr_IDIF[11:8];
wire nop_lw_idex, nop_sw_idex;
wire nop_lw_exmem, nop_sw_exmem;
wire nop_lw_memwb;
wire jal, jal_idex, jal_exmem, jal_memwb;
wire jr, jr_idex;
wire exec, exec_idex;
wire [15:0] branch_target_final;
//to decide what we are going to write to reg, ALU/MEM or LLB
MUX16 S7( .in0(rf_wdata_bef_mux), .in1(imm_16_0_memwb),
.select(s7_memwb), .out(rf_wdata));
//To decide what our destination address is going to be - mostly it will be [11:18]
MUX4 regdestMUX(.in0(inst_curr_IDEX[3:0]), .in1(inst_curr_IDEX[11:8]),
.select(regdest_idex), .out(rf_waddr));
/// Memory instantiation
//mem_data_in is empty
/*memory IMem (.clk(clk), .rst(rst), .wen(1'b1), .addr(pc_curr),
.data_in(mem_data_in), .fileid(4'd2), .data_out(inst_curr));*/
wire branch2_exmem;
assign pc_in_imem = (branch2_exmem === 1'b1) ? branch_target_exmem : pc_added;
memory IMem (.clk(clk), .rst(rst), .wen(1'b1), .addr(pc_in_imem),
.data_in(mem_data_in), .fileid(4'd1), .data_out(inst_curr));
// NOP store statement
wire dmem_wen_exmem_muxout;
// DONT USE MUX COZ 1 BIT - MUX4 dmemNOPMux(.in0(dmem_wen_exmem), .in1(), .select(nop_sw_exmem), .out(dmem_wen_exmem_muxout));
assign dmem_wen_exmem_muxout = (nop_sw_exmem===1'b1)?1'b1:dmem_wen_exmem;
memory DMem (.clk(clk), .rst(rst), .wen(dmem_wen_exmem_muxout), .addr(aluout_exmem),
.data_in(rdata2_exmem), .fileid(4'd9), .data_out(mem_data_out));
/// IF Stage instantiation
wire pc_stall_wire, ifid_stall_wire, pc_stall_out, ifid_stall_out, idex_stall_wire, idex_stall_out, inst_stall_wire, inst_stall_out;
assign pc_stall_wire = pc_stall_out;
assign ifid_stall_wire = ifid_stall_out;
assign idex_stall_wire = idex_stall_out;
assign inst_stall_wire = inst_stall_out;
pc PC(.in(pc_mux_out), .out(pc_curr), .clk(clk), .rst(rst), .stall(pc_stall_wire));
addPC incPC(.in(pc_curr), .out(pc_added), .stall(inst_stall_wire));
//S9 is used to decide whether (PC = PC+1) or (PC = branch target+pC+1)
//THIS IS THE FIRST PCMUX
//branch target is PC+1+branch_offset and
//branch_2_exmem is control generated from control_exe
MUX16 S9 (.in0(pc_added), .in1(branch_target_exmem),
.select(branch2_exmem), .out(pc_mux_out));
wire [15:0] imm_16_0_idex;
wire [7:0] imm_7_0_idex;
wire [15:0] imm_12_to_16_idif;
wire [15:0] imm_12_to_16_idex;
//needed for the usual 4 bit extension to 16 bits for immediate
sign_ext_4_16 signext4_16( .imm_4(inst_curr_IDIF[3:0]), .imm_16(extended));
//needed for the LLB immeduate and the Branch immediate extension
sign_ext_8_16 signext8_16_1( .imm_8(imm_7_0_idex),.imm_16(imm_16_0_idex));
//needed to extend the JAL instruction immediate
sign_ext_12_16 signext12_16_1(.imm_12(inst_curr_IDIF[11:0]),.imm_16(imm_12_to_16_idif));
///IF_ID instantiation
if_id IF_ID (.clk(clk), .inst_curr(inst_curr), .pc_added(pc_added),
.inst_curr_IFID(inst_curr_IDIF),.pc_added_IDIF(pc_added_IDIF), .ifid_stall(ifid_stall_wire));
//mux for deciding which input to go to raddr2
MUX4 S4 (.in0(inst_curr_IDIF[3:0]), .in1(inst_curr_IDIF[11:8])
, .select(lhb_llb_regcon), .out(inst_raddr2));
wire [3:0] rf_waddr_memwb_muxout;
wire [3:0] rf_15_or_waddr;
wire [15:0] pcORwdata;
//This mux is used to decide what register we are writing to - normal address or R15
MUX4 r15ORwaddr(.in0(rf_waddr_memwb), .in1(4'b1111), .select(jal_memwb), .out(rf_15_or_waddr));
//This mux is used to introduce a nop in the Load instruction writeback, as we want to prevent any wb
MUX4 nopLWMUX(.in0(rf_15_or_waddr), .in1(4'b0000), .select(nop_lw_memwb), .out(rf_waddr_memwb_muxout));
//MUX4 nopLWMUX(.in0(rf_waddr_memwb), .in1(4'b0000), .select(nop_lw_memwb), .out(rf_waddr_memwb_muxout));
MUX16 pcORwdataMUX(.in0(rf_wdata), .in1(pc_added_memwb), .select(jal_memwb), .out(pcORwdata));
// we send pc_added_exmem because wdata bypasses the MemWb pipeline
// we send jal_exmem to bypass the MemWb Reg
wire write_done_out, write_done_wire;
reg write_done_temp;
reg [1:0] stallCount_reg;
wire [1:0] stallCount;
assign write_done_wire = write_done_out;
assign stallCount = (pc_stall_out===1'b1)? 2'b10: 2'b00;
always @ (posedge clk) begin
if(!(stallCount_reg>2'b00) || stallCount_reg===2'bxx) begin
stallCount_reg = stallCount;
write_done_temp=0;
end
else begin
stallCount_reg = stallCount_reg-1;
if(stallCount_reg===1'b0) begin write_done_temp=1; end
end
end
assign write_done_out = write_done_temp;
regfile RF(
.clk(clk),
.rst(rst),
.wen(rf_wen_memwb),
.raddr1(inst_curr_IDIF[7:4]),
.raddr2(inst_raddr2),
.waddr(rf_waddr_memwb_muxout),
//.wdata(rf_wdata),
.wdata(pcORwdata),
.rdata1(rdata1),
.rdata2(rdata2)
);
wire [15:0] lhb_llb_imm_16;
///ID Instantiation
wire lw_out, lw_wire, lw_idex;
assign lw_wire = lw_out;
///Control instantiation
control Ctrl(
.opcode(opcode),
//.cond(inst_curr_IDIF[11:8]),
//.flag(flag_controlin),
.dmem_wen(dmem_wen),
.rf_wen(rf_wen),
.alu_op(alu_op),
.alusrc(alusrc),
.regdest(regdest),
.branch(branch),
.mem2reg(mem2reg),
.lhb_llb_con1(lhb_llb_regcon),
.s5(s5),
.s6(s6),
.s7(s7),
.jal(jal),
.jr(jr),
.exec(exec),
.lw(lw_out)
);
wire s5_idex, s6_idex, s7_idex;
wire lhb_llb_con_idex;
hdUnit hdu(
.d_raddr1(inst_curr_IDIF[7:4]),
.d_raddr2(inst_raddr2),
.d_addrselector(lhb_llb_regcon),
.d_jr_or_exec((jr||exec)?1'b1:1'b0),
.d_immonly(opcode===4'b1010 || opcode===4'b1100 || opcode===4'b1101),
.d_opcode(opcode),
.e_isLoad(lw_idex),
.e_wreg(rf_waddr),
.pc_stall(pc_stall_out),
.ifid_stall(ifid_stall_out),
.idex_stall(idex_stall_out),
.inst_stall(inst_stall_out),
.write_done(write_done_wire)
);
//ID_EX instantiation
wire branch_idex;
wire [3:0] cond_IDEX;
id_ex ID_EX(.clk(clk), .pc_added_IDIF(pc_added_IDIF), .cond_IDIF(cond_IDIF),
.inst_curr_IDIF(inst_curr_IDIF),.dmem_wen(dmem_wen), .rf_wen(rf_wen),
.alu_op(alu_op), .alusrc(alusrc), .rdest1(regdest), .branch(branch),
.mem2reg(mem2reg),.rdata1(rdata1), .rdata2(rdata2),
.extended(extended), .imm_7_0(inst_curr_IDIF[7:0]),
.s5_idif(s5), .s6_idif(s6), .s7_idif(s7),
.inst_curr_IDEX(inst_curr_IDEX),
.dmem_wen_idex(dmem_wen_idex), .rf_wen_idex(rf_wen_idex),
.alu_op_idex(alu_op_idex),
.alusrc_idex(alusrc_idex), .rdest_idex(regdest_idex),
.branch_idex(branch_idex),
.mem2reg_idex(mem2reg_idex), .rdata1_idex(rdata1_idex),
.rdata2_idex(rdata2_idex), .extended_idex(extended_idex),
.imm_7_0_idex(imm_7_0_idex),
.s5_idex(s5_idex),.s6_idex(s6_idex), .s7_idex(s7_idex),
.pc_added_IDEX(pc_added_IDEX), .cond_IDEX(cond_IDEX),
.jal(jal), .jal_idex(jal_idex),
.imm_12_to_16_idif(imm_12_to_16_idif), .imm_12_to_16_idex(imm_12_to_16_idex),
.jr(jr), .jr_idex(jr_idex),
.exec(exec), .exec_idex(exec_idex),
.lw(lw_wire), .lw_idex(lw_idex),
.stall(idex_stall_wire)
);
///EXE instantiation
wire [15:0] alu_second_input_final;
wire [15:0] rdata1_idex_final;
wire [15:0] rdata2_idex_final,rdata2_idex_sw_val;
wire [1:0] forwardA,forwardB, rdata2_sw_fcontrol;
//MUX for selecting rdata1 / memwb_data / exmem_data (assuming this is the value inside EX)
MUX16_3_input forward_a_alu( .in0(rdata1_idex), .in1(pcORwdata), .in2(aluout_exmem),
.select(forwardA), .out(rdata1_idex_final));
//MUX for selecting rdata2 / memwb_data / exmem_data (assuming this is the value inside EX)
MUX16_3_input forward_b_alu(.in0(rdata2_idex), .in1(pcORwdata), .in2(aluout_exmem),
.select(forwardB), .out(rdata2_idex_final));
//MUX for selecting rdata2/forwarded value for store instruction (special case)
MUX16_3_input forward_sw_rdata2(.in0(rdata2_idex),.in1(pcORwdata),.in2(aluout_exmem),
.select(rdata2_sw_fcontrol), .out(rdata2_idex_sw_val));
//FORWARDING UNIT
forwarding_unit f_unit1 (
.rf_waddr_exmem(rf_waddr_exmem),
.rf_waddr_memwb(rf_waddr_memwb),
.inst_curr_IDEX_7_4_rs(inst_curr_IDEX[7:4]),
.inst_curr_IDEX_3_0_rt(inst_curr_IDEX[3:0]),
.inst_curr_IDEX_11_8_rd(inst_curr_IDEX[11:8]),
.rf_wen_exmem(rf_wen_exmem),
.rf_wen_memwb(rf_wen_memwb),
.mem2reg_memwb(mem2reg_memwb),
.mem2reg_exmem(mem2reg_exmem),
.dmem_wen_idex(dmem_wen_idex),
.forwardA(forwardA),
.forwardB(forwardB),
.rdata2_sw_fcontrol(rdata2_sw_fcontrol)
);
//mux for deciding between rdata2 and immediate value as ALU's second input
MUX16 S1( .in0(alu_second_input), .in1(extended_idex), .select(alusrc_idex), .out(alu_second_input_final));
///ALU instantiation
wire [15:0] alu_first_input;
//wire [2:0] flag_prev_to_send;
wire branch2_idex;
wire nop_alu;
wire [15:0] execPCadded;
wire putPCback;
wire [15:0] branch_target_final_muxout;
//choosing which immediate to add to the PC_added value
wire [15:0]adderToAdd = (jal_idex===1'b1)? imm_12_to_16_idex : imm_16_0_idex;
//adder for adding the PC added value and the adderToAdd
adder branch_adder(.pc_add(pc_added_IDEX),.imm(adderToAdd),.shiftout(branch_target_idex));
//this mux is used to select JR/JAL relative branch target or JR jump target absolute
//MUX16 adderout_or_jr(.in0(branch_target_idex), .in1(rdata2_idex), .select(jr_idex),.out(branch_target_final));
//what should be the value of the PC during branch
assign branch_target_final = (jr_idex===1'b1 || exec_idex === 1'b1)? rdata2_idex : branch_target_idex;
//we need branch_target to determine if branch is to be done/not?
//this mux is needed for EXEC vs JR/BR/JAL and the output becomes the FINAL branch target
MUX16 branch_target_final_or_exec (.in0(branch_target_final), .in1(execPCadded),.select(putPCback),.out(branch_target_final_muxout));
control_exe control_EXE(
.clk(clk),
.rst(rst),
.branch_target(branch_target_final),
.pc_added(pc_added_IDEX),
.flag(flag_controlexein),
.cond(cond_IDEX),
.branch_idex(branch_idex),
.jal_idex(jal_idex),
.jr_idex(jr_idex),
.exec_idex(exec_idex),
.branch2_idex(branch2_idex),
.nop_alu(nop_alu),
.nop_lw(nop_lw_idex),
.nop_sw(nop_sw_idex),
.execPCadded(execPCadded),
.putPCback(putPCback)
);
alu ALU(
.a(alu_first_input), //1st operand
.b(alu_second_input_final), //2nd operand
.op(alu_op_idex), //3-bit operation
.imm(inst_curr_IDEX[3:0]), //4-bit immediate operand for shift/rotate
.nop(nop_alu),
.flag_prev_to_send(flag_aluout), // output flag register for indicating Z,V,N
.out(aluout) //output
);
wire [15:0] mux_ex_out;
wire [15:0] aluout_or_lhbllb_exmem;
wire [15:0] shifted81;
//wire branch2_exmem;
wire [15:0] changed8_1;
//functions needed for LHB
ShiftLeftThenAdd1s shiftleftthenadd1s(.In(imm_7_0_idex), .Out_L8_1(shifted81));
changefirst8bits_1 changefirst8bits_1(.In(rdata2_idex),.Out_F8_1(changed8_1));
//for ALU first input
MUX16 S6(.in0(shifted81), .in1(rdata1_idex_final), .select(s6_idex), .out(alu_first_input));
//for ALU second input
MUX16 S5(.in0(rdata2_idex_final),.in1(changed8_1),.select(s5_idex),.out(alu_second_input));
//mux to select whether to jump to target address or continue with next program counter
//MUX16 select_jump(.in0(pc_curr), .in1(imm_16_0_idex), .select(jump_control), .out(pc_added));
/// EX_MEM instantiation
wire [15:0] imm_16_0_exmem;
//rdata2_idex_sw_val is the muxed val needed for forwarding store(sw) instruction
ex_mem EX_MEM (.clk(clk),.s7_idex(s7_idex), .dmem_wen_idex(dmem_wen_idex),
.rf_wen_idex(rf_wen_idex),
.branch2_idex(branch2_idex), .mem2reg_idex(mem2reg_idex), .aluout(aluout),
.flag(flag), .extended_16_idex(imm_16_0_idex),
.rdata2_idex(rdata2_idex_sw_val), .rf_waddr(rf_waddr), .dmem_wen_exmem(dmem_wen_exmem),
.rf_wen_exmem(rf_wen_exmem), .branch2_exmem(branch2_exmem), .mem2reg_exmem(mem2reg_exmem),
.aluout_exmem(aluout_exmem), .flag_exmem(flag_exmem),
.rdata2_exmem(rdata2_exmem), .rf_waddr_exmem(rf_waddr_exmem),
.extended_exmem(imm_16_0_exmem)
,.s7_exmem(s7_exmem),
.branch_target_final_muxout(branch_target_final_muxout), .branch_target_exmem(branch_target_exmem),
.nop_lw_idex(nop_lw_idex),.nop_lw_exmem(nop_lw_exmem),
.nop_sw_idex(nop_sw_idex),.nop_sw_exmem(nop_sw_exmem),
.pc_added_idex(pc_added_IDEX), .pc_added_exmem(pc_added_exmem),
.jal_idex(jal_idex), .jal_exmem(jal_exmem)
);
///MEM_WB instantiation
mem_wb MEM_WB (.clk(clk),.s7_exmem(s7_exmem)
,.rf_wen_exmem(rf_wen_exmem),
.mem2reg_exmem(mem2reg_exmem), .rf_waddr_exmem(rf_waddr_exmem),
.aluout_exmem(aluout_exmem),
.extended_exmem(imm_16_0_exmem),
.rf_wen_memwb(rf_wen_memwb),
.mem2reg_memwb(mem2reg_memwb),.rf_waddr_memwb(rf_waddr_memwb),
.aluout_memwb(aluout_memwb), .extended_memwb(imm_16_0_memwb)
,.s7_memwb(s7_memwb),
.nop_lw_exmem(nop_lw_exmem),.nop_lw_memwb(nop_lw_memwb),
.jal_exmem(jal_exmem), .jal_memwb(jal_memwb),
.pc_added_exmem(pc_added_exmem), .pc_added_memwb(pc_added_memwb)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DFXBP_FUNCTIONAL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p/sky130_fd_sc_ms__udp_dff_p.v"
`celldefine
module sky130_fd_sc_ms__dfxbp (
Q ,
Q_N,
CLK,
D
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_ms__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXBP_FUNCTIONAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ccx_arbdp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////
/*
//
// Module Name: ccx_arbdp.v
// Description: Datapath portion of arbiter
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
// Code start here
//
module ccx_arbdp(/*AUTOARG*/
// Outputs
arb_dp_grant_a, arb_src7_grant_a, arb_src6_grant_a,
arb_src5_grant_a, arb_src4_grant_a, arb_src3_grant_a,
arb_src2_grant_a, arb_src1_grant_a, arb_src0_grant_a,
ccx_dest_data_rdy_a, ccx_dest_atom_a, req_pkt_empty, grant_a,
inreg_req_vld_d1,
// Inputs
src7_arb_atom_q, src6_arb_atom_q, src5_arb_atom_q,
src4_arb_atom_q, src3_arb_atom_q, src2_arb_atom_q,
src1_arb_atom_q, src0_arb_atom_q, src7_arb_req_q, src6_arb_req_q,
src5_arb_req_q, src4_arb_req_q, src3_arb_req_q, src2_arb_req_q,
src1_arb_req_q, src0_arb_req_q, reset_d1, qfull, direction,
stall_a, fifo_req_sel, current_req_sel, input_req_sel,
input_req_sel_d1, fifo_bypass, fifo_bypass_l, wrptr_l, rdptr,
fifo_sel15_12, fifo_sel11_8, fifo_sel7_4, fifo_sel3_0, fifo_valid,
arbctl_atom, rclk, se
);
//Primary outputs to ccx datapaths
output [7:0] arb_dp_grant_a; //to ccx datapath
//Output to source: sparc or sctag grant flops
output arb_src7_grant_a;
output arb_src6_grant_a;
output arb_src5_grant_a;
output arb_src4_grant_a;
output arb_src3_grant_a;
output arb_src2_grant_a;
output arb_src1_grant_a;
output arb_src0_grant_a;
//Output to arb control logic
output ccx_dest_data_rdy_a;
output ccx_dest_atom_a;
output req_pkt_empty;
output [7:0] grant_a;
output inreg_req_vld_d1;
//Primary inputs from sources
input src7_arb_atom_q;//indicates 2 packet transaction
input src6_arb_atom_q;
input src5_arb_atom_q;
input src4_arb_atom_q;
input src3_arb_atom_q;
input src2_arb_atom_q;
input src1_arb_atom_q;
input src0_arb_atom_q;
input src7_arb_req_q;//indicates request from source
input src6_arb_req_q;
input src5_arb_req_q;
input src4_arb_req_q;
input src3_arb_req_q;
input src2_arb_req_q;
input src1_arb_req_q;
input src0_arb_req_q;
//Primary inputs from destinations
//Primary inputs from arbiter control logic
input reset_d1; //reset latched in ctl
input [7:0] qfull;
input direction;
input stall_a; //stall input driven from control
input fifo_req_sel, current_req_sel;
input input_req_sel, input_req_sel_d1;
input fifo_bypass, fifo_bypass_l;//selects for fifo byp mux
input [15:0] wrptr_l; //write pointer for fifo.
input [15:0] rdptr;
input fifo_sel15_12, fifo_sel11_8, fifo_sel7_4, fifo_sel3_0;
input fifo_valid;
input [7:0] arbctl_atom;
//Global signals
input rclk;
//input tmb_l;
input se ;
//Wires between FIFO and PE sections
wire [7:0] req_q, atom_q;
wire [7:0] fq_req, fq_atomic;//fq-> fifo or qual from
wire fq_dir; // current packet
wire [7:0] qual_req, qual_atomic,qual_atomic_d1;//fq-> qual from
wire qual_dir; // current packet
wire [7:0] fifo_req, fifo_atomic;//fq-> from fifo
wire fifo_dir; //
wire [7:0] req_fifo_a, atom_fifo_a;
//Wires within PE section
wire [7:0] fq_atomic_a, fq_req_a;
wire [7:0] grant_asc, grant_des, grant_a;
wire [7:0] qfull_a;
wire [7:0] req_a, atom_a;
wire [7:0] req, atom;
wire dir_a;
wire dira, dird;//asc & desc PE selects
//Wires within FIFO section
//write data
wire [8:0] fifo_wdata;
//read data
wire [8:0] fifo_rdata15;
wire [8:0] fifo_rdata14;
wire [8:0] fifo_rdata13;
wire [8:0] fifo_rdata12;
wire [8:0] fifo_rdata11;
wire [8:0] fifo_rdata10;
wire [8:0] fifo_rdata9;
wire [8:0] fifo_rdata8;
wire [8:0] fifo_rdata7;
wire [8:0] fifo_rdata6;
wire [8:0] fifo_rdata5;
wire [8:0] fifo_rdata4;
wire [8:0] fifo_rdata3;
wire [8:0] fifo_rdata2;
wire [8:0] fifo_rdata1;
wire [8:0] fifo_rdata0;
wire [8:0] fifo_rdata15_12;
wire [8:0] fifo_rdata11_8;
wire [8:0] fifo_rdata7_4;
wire [8:0] fifo_rdata3_0;
wire [8:0] fifo_rdata15_0;
wire [8:0] fifo_rdata;
//gated clocks
wire [15:0] clk_fifo_write;
assign atom_q[7:0] = { src7_arb_atom_q,
src6_arb_atom_q,
src5_arb_atom_q,
src4_arb_atom_q,
src3_arb_atom_q,
src2_arb_atom_q,
src1_arb_atom_q,
src0_arb_atom_q };
assign req_q[7:0] = { src7_arb_req_q,
src6_arb_req_q,
src5_arb_req_q,
src4_arb_req_q,
src3_arb_req_q,
src2_arb_req_q,
src1_arb_req_q,
src0_arb_req_q };
//BEGIN FIFO SECTION
assign req_fifo_a[7:0] = ~qfull_a[7:0] & req_a[7:0] ;
assign atom_fifo_a[7:0] = ~qfull_a[7:0] & req_a[7:0] & atom_a[7:0] ;
// assign fifo_wdata[16:0] = {dir_a,atom_fifo_a[7:0], req_fifo_a[7:0]};
assign fifo_wdata[8:0] = {dir_a, req_fifo_a[7:0]};
//create gated clocks
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~se ;
clken_buf ck0(
.clk (clk_fifo_write[0]),
.rclk (rclk),
.enb_l (wrptr_l[0]),
.tmb_l (se_l));
clken_buf ck1(
.clk (clk_fifo_write[1]),
.rclk (rclk),
.enb_l (wrptr_l[1]),
.tmb_l (se_l));
clken_buf ck2(
.clk (clk_fifo_write[2]),
.rclk (rclk),
.enb_l (wrptr_l[2]),
.tmb_l (se_l));
clken_buf ck3(
.clk (clk_fifo_write[3]),
.rclk (rclk),
.enb_l (wrptr_l[3]),
.tmb_l (se_l));
clken_buf ck4(
.clk (clk_fifo_write[4]),
.rclk (rclk),
.enb_l (wrptr_l[4]),
.tmb_l (se_l));
clken_buf ck5(
.clk (clk_fifo_write[5]),
.rclk (rclk),
.enb_l (wrptr_l[5]),
.tmb_l (se_l));
clken_buf ck6(
.clk (clk_fifo_write[6]),
.rclk (rclk),
.enb_l (wrptr_l[6]),
.tmb_l (se_l));
clken_buf ck7(
.clk (clk_fifo_write[7]),
.rclk (rclk),
.enb_l (wrptr_l[7]),
.tmb_l (se_l));
clken_buf ck8(
.clk (clk_fifo_write[8]),
.rclk (rclk),
.enb_l (wrptr_l[8]),
.tmb_l (se_l));
clken_buf ck9(
.clk (clk_fifo_write[9]),
.rclk (rclk),
.enb_l (wrptr_l[9]),
.tmb_l (se_l));
clken_buf ck10(
.clk (clk_fifo_write[10]),
.rclk (rclk),
.enb_l (wrptr_l[10]),
.tmb_l (se_l));
clken_buf ck11(
.clk (clk_fifo_write[11]),
.rclk (rclk),
.enb_l (wrptr_l[11]),
.tmb_l (se_l));
clken_buf ck12(
.clk (clk_fifo_write[12]),
.rclk (rclk),
.enb_l (wrptr_l[12]),
.tmb_l (se_l));
clken_buf ck13(
.clk (clk_fifo_write[13]),
.rclk (rclk),
.enb_l (wrptr_l[13]),
.tmb_l (se_l));
clken_buf ck14(
.clk (clk_fifo_write[14]),
.rclk (rclk),
.enb_l (wrptr_l[14]),
.tmb_l (se_l));
clken_buf ck15(
.clk (clk_fifo_write[15]),
.rclk (rclk),
.enb_l (wrptr_l[15]),
.tmb_l (se_l));
//create flop memory
dff_s #(9) dff_ccx_arb_fmem15(
.din (fifo_wdata[8:0]),
.q (fifo_rdata15[8:0]),
.clk (clk_fifo_write[15]),
.se (1'd0),
.si (9'd0),
.so ());
dff_s #(9) dff_ccx_arb_fmem14(
.din (fifo_wdata[8:0]),
.q (fifo_rdata14[8:0]),
.clk (clk_fifo_write[14]),
.se (1'd0),
.si (9'd0),
.so ());
dff_s #(9) dff_ccx_arb_fmem13(
.din (fifo_wdata[8:0]),
.q (fifo_rdata13[8:0]),
.clk (clk_fifo_write[13]),
.se (1'd0),
.si (9'd0),
.so ());
dff_s #(9) dff_ccx_arb_fmem12(
.din (fifo_wdata[8:0]),
.q (fifo_rdata12[8:0]),
.clk (clk_fifo_write[12]),
.se (1'd0),
.si (9'd0),
.so ());
//Read mux 15-12
mux4ds #(9) mux4ds_ccx_arb_fmem15_12(
.dout (fifo_rdata15_12[8:0]),
.in0 (fifo_rdata15[8:0]),
.in1 (fifo_rdata14[8:0]),
.in2 (fifo_rdata13[8:0]),
.in3 (fifo_rdata12[8:0]),
.sel0 (rdptr[15]),
.sel1 (rdptr[14]),
.sel2 (rdptr[13]),
.sel3 (rdptr[12]));
dff_s #(9) dff_ccx_arb_fmem11(
.din (fifo_wdata[8:0]),
.q (fifo_rdata11[8:0]),
.clk (clk_fifo_write[11]),
.se (1'd0),
.si (9'd0),
.so ());
dff_s #(9) dff_ccx_arb_fmem10(
.din (fifo_wdata[8:0]),
.q (fifo_rdata10[8:0]),
.clk (clk_fifo_write[10]),
.se (1'd0),
.si (9'd0),
.so ());
dff_s #(9) dff_ccx_arb_fmem9(
.din (fifo_wdata[8:0]),
.q (fifo_rdata9[8:0]),
.clk (clk_fifo_write[9]),
.se (1'd0),
.si (9'd0),
.so ());
dff_s #(9) dff_ccx_arb_fmem8(
.din (fifo_wdata[8:0]),
.q (fifo_rdata8[8:0]),
.clk (clk_fifo_write[8]),
.se (1'd0),
.si (9'd0),
.so ());
//Read mux 11 to 8
mux4ds #(9) mux4ds_ccx_arb_fmem11_8(
.dout (fifo_rdata11_8[8:0]),
.in0 (fifo_rdata11[8:0]),
.in1 (fifo_rdata10[8:0]),
.in2 (fifo_rdata9[8:0]),
.in3 (fifo_rdata8[8:0]),
.sel0 (rdptr[11]),
.sel1 (rdptr[10]),
.sel2 (rdptr[9]),
.sel3 (rdptr[8]));
dff_s #(9) dff_ccx_arb_fmem7(
.din (fifo_wdata[8:0]),
.q (fifo_rdata7[8:0]),
.clk (clk_fifo_write[7]),
.se (1'd0),
.si (9'd0),
.so ());
dff_s #(9) dff_ccx_arb_fmem6(
.din (fifo_wdata[8:0]),
.q (fifo_rdata6[8:0]),
.clk (clk_fifo_write[6]),
.se (1'd0),
.si (9'd0),
.so ());
dff_s #(9) dff_ccx_arb_fmem5(
.din (fifo_wdata[8:0]),
.q (fifo_rdata5[8:0]),
.clk (clk_fifo_write[5]),
.se (1'd0),
.si (9'd0),
.so ());
dff_s #(9) dff_ccx_arb_fmem4(
.din (fifo_wdata[8:0]),
.q (fifo_rdata4[8:0]),
.clk (clk_fifo_write[4]),
.se (1'd0),
.si (9'd0),
.so ());
//Read mux 7 to 4
mux4ds #(9) mux4ds_ccx_arb_fmem7_4(
.dout (fifo_rdata7_4[8:0]),
.in0 (fifo_rdata7[8:0]),
.in1 (fifo_rdata6[8:0]),
.in2 (fifo_rdata5[8:0]),
.in3 (fifo_rdata4[8:0]),
.sel0 (rdptr[7]),
.sel1 (rdptr[6]),
.sel2 (rdptr[5]),
.sel3 (rdptr[4]));
dff_s #(9) dff_ccx_arb_fmem3(
.din (fifo_wdata[8:0]),
.q (fifo_rdata3[8:0]),
.clk (clk_fifo_write[3]),
.se (1'd0),
.si (9'd0),
.so ());
dff_s #(9) dff_ccx_arb_fmem2(
.din (fifo_wdata[8:0]),
.q (fifo_rdata2[8:0]),
.clk (clk_fifo_write[2]),
.se (1'd0),
.si (9'd0),
.so ());
dff_s #(9) dff_ccx_arb_fmem1(
.din (fifo_wdata[8:0]),
.q (fifo_rdata1[8:0]),
.clk (clk_fifo_write[1]),
.se (1'd0),
.si (9'd0),
.so ());
dff_s #(9) dff_ccx_arb_fmem0(
.din (fifo_wdata[8:0]),
.q (fifo_rdata0[8:0]),
.clk (clk_fifo_write[0]),
.se (1'd0),
.si (9'd0),
.so ());
//Read mux 3 to 0
mux4ds #(9) mux4ds_ccx_arb_fmem3_0(
.dout (fifo_rdata3_0[8:0]),
.in0 (fifo_rdata3[8:0]),
.in1 (fifo_rdata2[8:0]),
.in2 (fifo_rdata1[8:0]),
.in3 (fifo_rdata0[8:0]),
.sel0 (rdptr[3]),
.sel1 (rdptr[2]),
.sel2 (rdptr[1]),
.sel3 (rdptr[0]));
//Read mux 15 to 0
mux4ds #(9) mux4ds_ccx_arb_fmem15_0(
.dout (fifo_rdata15_0[8:0]),
.in0 (fifo_rdata15_12[8:0]),
.in1 (fifo_rdata11_8[8:0]),
.in2 (fifo_rdata7_4[8:0]),
.in3 (fifo_rdata3_0[8:0]),
.sel0 (fifo_sel15_12),
.sel1 (fifo_sel11_8),
.sel2 (fifo_sel7_4),
.sel3 (fifo_sel3_0));
assign fifo_rdata = (fifo_sel15_12 | fifo_sel11_8 | fifo_sel7_4 | fifo_sel3_0) ? fifo_rdata15_0[8:0] : 9'd0;
// mux2ds #(17) mx2ds_ccx_arb_bypmx(
// .dout ({fifo_dir,fifo_atomic[7:0],fifo_req[7:0]}),
// .in0 ({fifo_rdata[8],arbctl_atom[7:0],fifo_rdata[7:0]}),
// .in1 ({fifo_wdata[8],atom_fifo_a[7:0],fifo_wdata[7:0]}),
// .sel0 (fifo_bypass_l),
// .sel1 (fifo_bypass));
mux2ds #(9) mx2ds_ccx_arb_bypmx(
.dout ({fifo_dir,fifo_req[7:0]}),
.in0 ({fifo_rdata[8:0]}),
.in1 ({fifo_wdata[8:0]}),
.sel0 (fifo_bypass_l),
.sel1 (fifo_bypass));
//End flop memory section
//BEGIN PE SECTION
dff_s #(8) dff_ccx_arb_newreq(
.din (req_q[7:0]),
.q (req_a[7:0]),
.clk (rclk),
.se (1'd0),
.si (8'd0),
.so ());
dff_s #(8) dff_ccx_arb_newatom(
.din (atom_q[7:0]),
.q (atom_a[7:0]),
.clk (rclk),
.se (1'd0),
.si (8'd0),
.so ());
dff_s dff_ccx_arb_newdir(
.din (direction),
.q (dir_a),
.clk (rclk),
.se (1'd0),
.si (1'd0),
.so ());
dff_s #(8) dff_ccx_arb_qfull_l(
.din (qfull[7:0]),
.q (qfull_a[7:0]),
.clk (rclk),
.se (1'b0),
.si (8'd0),
.so ());
// mux3ds #(17) mx3ds_ccx_arb_l(
// .dout ({fq_dir,fq_atomic[7:0], fq_req[7:0]}),
// .in0 ({qual_dir,qual_atomic[7:0],qual_req[7:0]}),
// .in1 ({fifo_dir,fifo_atomic[7:0],fifo_req[7:0]}),
// .in2 (17'd0),
// .sel0 (current_req_sel),
// .sel1 (fifo_req_sel),
// .sel2 (input_req_sel));
mux3ds #(9) mx3ds_ccx_arb_l(
.dout ({fq_dir,fq_req[7:0]}),
.in0 ({qual_dir,qual_req[7:0]}),
.in1 ({fifo_dir,fifo_req[7:0]}),
.in2 (9'd0),
.sel0 (current_req_sel),
.sel1 (fifo_req_sel),
.sel2 (input_req_sel));
dff_s #(9) dff_ccx_arb_fqreg(
.din ({fq_dir,fq_req[7:0]}),
.q ({fq_dir_a,fq_req_a[7:0]}),
.clk (rclk),
.se (1'd0),
.si (9'd0),
.so ());
//see if any valid requests in flopped request packet.
assign inreg_req_vld_d1 = |((req_a[7:0] & ~qfull_a[7:0])) ;
assign req[7:0] = (input_req_sel_d1 ? (~qfull_a[7:0] & req_a[7:0]) : 8'd0) | fq_req_a[7:0];
//assign atom[7:0] = (input_req_sel_d1 ? ~qfull_a[7:0] & req_a[7:0] & atom_a[7:0] : 8'd0) | fq_atomic_a[7:0];
//assign atom[7:0] = (input_req_sel_d1 ? ~qfull_a[7:0] & req_a[7:0] & atom_a[7:0] : 8'd0) | arbctl_atom[7:0];
assign atom[7:0] = input_req_sel_d1 ? ~qfull_a[7:0] & req_a[7:0] & atom_a[7:0] : arbctl_atom[7:0];
assign dira = ((input_req_sel_d1 & dir_a) | fq_dir_a) & ~stall_a & ~reset_d1;
assign dird = ~((input_req_sel_d1 & dir_a) | fq_dir_a) & ~stall_a & ~reset_d1;
// dir signal selects between asc and des PEs, and also reduces both PE
// outputs to '0' when stalled.
//Ascending priority encoder
assign grant_asc[0] = req[0]&dira;
assign grant_asc[1] = ~req[0]& req[1]&dira;
assign grant_asc[2] = ~req[0]&~req[1]& req[2]&dira;
assign grant_asc[3] = ~req[0]&~req[1]&~req[2]& req[3]&dira;
assign grant_asc[4] = ~req[0]&~req[1]&~req[2]&~req[3]& req[4]&dira;
assign grant_asc[5] = ~req[0]&~req[1]&~req[2]&~req[3]&~req[4]& req[5]&dira;
assign grant_asc[6] = ~req[0]&~req[1]&~req[2]&~req[3]&~req[4]&~req[5]& req[6]&dira;
assign grant_asc[7] = ~req[0]&~req[1]&~req[2]&~req[3]&~req[4]&~req[5]&~req[6]& req[7]&dira;
//Descending priority encoder.
assign grant_des[7] = req[7]&dird;
assign grant_des[6] = ~req[7]& req[6]&dird;
assign grant_des[5] = ~req[7]&~req[6]& req[5]&dird;
assign grant_des[4] = ~req[7]&~req[6]&~req[5]& req[4]&dird;
assign grant_des[3] = ~req[7]&~req[6]&~req[5]&~req[4]& req[3]&dird;
assign grant_des[2] = ~req[7]&~req[6]&~req[5]&~req[4]&~req[3]& req[2]&dird;
assign grant_des[1] = ~req[7]&~req[6]&~req[5]&~req[4]&~req[3]&~req[2]& req[1]&dird;
assign grant_des[0] = ~req[7]&~req[6]&~req[5]&~req[4]&~req[3]&~req[2]&~req[1]&req[0]&dird;
//Final select & generation of data_ready signal.
assign grant_a[7:0] = grant_asc[7:0] | grant_des[7:0];
assign ccx_dest_data_rdy_a = |(grant_a[7:0]);
// assign ccx_dest_atom_a = |(grant_a[7:0] & atom[7:0]);
assign ccx_dest_atom_a = |(grant_a[7:0] & atom[7:0] & ~qual_atomic_d1[7:0]);
/*
*/
assign arb_src7_grant_a = grant_a[7];//Outputs to sources eg. sparc/sctag
assign arb_src6_grant_a = grant_a[6];
assign arb_src5_grant_a = grant_a[5];
assign arb_src4_grant_a = grant_a[4];
assign arb_src3_grant_a = grant_a[3];
assign arb_src2_grant_a = grant_a[2];
assign arb_src1_grant_a = grant_a[1];
assign arb_src0_grant_a = grant_a[0];
assign arb_dp_grant_a[7:0] = grant_a[7:0];//outputs to ccx datapath.
// Logic to determine if req packet was drained in current cycle
// assign qual_req[7:0] = (req[7:0] & ~grant_a[7:0]) | (req[7:0] & atom[7:0]) ;
assign qual_req[7:0] = (req[7:0] & ~grant_a[7:0]) |
(atom[7:0] & grant_a[7:0] & ~qual_atomic_d1[7:0]) ;
// (req[7:0] & atom[7:0] & grant_a[7:0] & ~qual_atomic_d1[7:0]) ;
assign req_pkt_empty = ~(|(qual_req[7:0]));
// assign qual_atomic[7:0] = atom[7:0] & ~grant_a[7:0];
// assign qual_atomic[7:0] = (req[7:0] & atom[7:0] & grant_a[7:0] & ~qual_atomic_d1[7:0]) | // set
assign qual_atomic[7:0] = (atom[7:0] & grant_a[7:0] & ~qual_atomic_d1[7:0]) | // set
(~{8{reset_d1}} & ~grant_a[7:0] & qual_atomic_d1[7:0]); // hold if l2stall=1 after 1st atomic packet
assign qual_dir = ((input_req_sel_d1 & dir_a) | fq_dir_a) & ~reset_d1;
dff_s #(8) dff_qual_atomic_d1(
.din (qual_atomic[7:0]),
.q (qual_atomic_d1[7:0]),
.clk (rclk),
.se (1'd0),
.si (8'd0),
.so ());
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../../common/rtl" "../../common/rtl")
// End:
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
* This module generates a CRC16 value from an incomming bitstream
* the value is generated from bit that is currently shifting out
* The final crc is valid after the last bit is sent, it might be
* necessary to send this value one clock cycle before
*
* Last two bytes of the data
* CCCCCCCCCCCCCCCC
* C = CRC bit
*
* Hold in reset when not using
*
* Online documentation is way to fucking complicated
* x^16 + x^12 + x^5 + 1
* To find the polynomial remove the top x^16 then add 2^12 + 2^5 + 1 = 0x1021
*
*
* Changes:
* 2015.08.08: Initial Add
*
*/
module crc16 #(
parameter POLYNOMIAL = 16'h1021,
parameter SEED = 16'h0000
)(
input clk,
input rst,
input en,
input bit,
output reg [15:0] crc
);
//local parameters
//registes/wires
wire inv;
//submodules
//asynchronous logic
assign inv = bit ^ crc[15]; // XOR required?
//synchronous logic
//XXX: Does this need to be asynchronous?
always @ (posedge clk) begin
if (rst) begin
//crc <= SEED;
crc <= 0;
end
else begin
//Shift the output value
if (en) begin
//crc <= bit ? ({crc[14:0], 1'b0} ^ POLYNOMIAL) : {crc[14:0], 1'b0};
crc[15] <= crc[14];
crc[14] <= crc[13];
crc[13] <= crc[12];
crc[12] <= crc[11] ^ inv;
crc[11] <= crc[10];
crc[10] <= crc[9];
crc[9] <= crc[8];
crc[8] <= crc[7];
crc[7] <= crc[6];
crc[6] <= crc[5];
crc[5] <= crc[4] ^ inv;
crc[4] <= crc[3];
crc[3] <= crc[2];
crc[2] <= crc[1];
crc[1] <= crc[0];
crc[0] <= inv;
end
end
end
endmodule
|
module spi_slave_tb
#(parameter transactions = 1000,
parameter init_value = 8'h42);
reg clk = 1'b1;
reg rst = 1'b1;
always #5 clk = ~clk;
initial #100 rst = 1'b0;
wire [7:0] gpio;
vlog_tb_utils vtu();
spi_bfm #(.sclk_period (50))
bfm
(.sclk_o (sclk),
.mosi_o (mosi),
.miso_i (1'b0),
.cs_n_o (cs_n));
spi_slave
#(.INIT_VALUE (init_value))
dut
(.clk (clk),
.rst (rst),
.sclk_i (sclk),
.mosi_i (mosi),
.miso_o (),
.cs_n_i (cs_n),
.gpio_o (gpio));
integer idx;
integer seed = 1;
reg [7:0] value = init_value;
initial begin
$display("Running %0d transactions", transactions);
@(negedge rst);
$display("Reset released");
@(clk);
for (idx=0 ; idx<transactions ; idx=idx+1 ) begin
bfm.send(value, 1'b0);
if (gpio != value) begin
$display("Error in transaction %0d. Expected %02x. Got %02x", idx, value, gpio);
$finish;
end
value = $dist_uniform(seed, 0, 255);
end
$display("Test passed!");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221AI_1_V
`define SKY130_FD_SC_LP__O221AI_1_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221ai_1 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221AI_1_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Fri Oct 28 13:01:03 2016
/////////////////////////////////////////////////////////////
module FPU_Add_Subtract_Function_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_FSM,
ack_FSM, Data_X, Data_Y, add_subt, r_mode, overflow_flag,
underflow_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
input [1:0] r_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
wire FSM_selector_C, add_overflow_flag, FSM_exp_operation_A_S,
FSM_selector_D, intAS, sign_final_result, n12, n13, n14, n15, n16,
n17, n19, n20, n21, n23, n24, n25, n27, n28, n29, n31, n32, n33, n35,
n36, n37, n39, n40, n41, n43, n44, n45, n47, n48, n49, n50, n51, n52,
n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66,
n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80,
n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94,
n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106,
n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117,
n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128,
n129, n130, n131, n132, n133, n134, n135, n136, n137, n138, n139,
n140, n141, n142, n143, n144, n145, n146, n147, n148, n149, n150,
n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, n161,
n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172,
n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183,
n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194,
n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, n205,
n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216,
n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, n227,
n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, n238,
n239, n240, n242, n243, n244, n245, n246, n247, n248,
DP_OP_42J1_122_8048_n20, DP_OP_42J1_122_8048_n19,
DP_OP_42J1_122_8048_n18, DP_OP_42J1_122_8048_n17,
DP_OP_42J1_122_8048_n16, DP_OP_42J1_122_8048_n15,
DP_OP_42J1_122_8048_n14, DP_OP_42J1_122_8048_n13,
DP_OP_42J1_122_8048_n8, DP_OP_42J1_122_8048_n7,
DP_OP_42J1_122_8048_n6, DP_OP_42J1_122_8048_n5,
DP_OP_42J1_122_8048_n4, DP_OP_42J1_122_8048_n3,
DP_OP_42J1_122_8048_n2, DP_OP_42J1_122_8048_n1, n652, n653, n654,
n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676,
n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698,
n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720,
n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731,
n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742,
n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753,
n754, n755, n756, n757, n758, n759, n760, n761, n762, n763, n764,
n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, n775,
n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786,
n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, n797,
n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808,
n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819,
n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, n830,
n831, n832, n833, n834, n835, n836, n837, n838, n839, n840, n841,
n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, n852,
n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863,
n864, n865, n866, n867, n868, n869, n870, n871, n872, n873, n874,
n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, n885,
n886, n887, n888, n889, n890, n891, n892, n893, n894, n895, n896,
n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918,
n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951,
n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962,
n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973,
n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984,
n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995,
n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005,
n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015,
n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025,
n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035,
n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045,
n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055,
n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065,
n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075,
n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085,
n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095,
n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105,
n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115,
n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125,
n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135,
n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145,
n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295,
n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305,
n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315,
n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325,
n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335,
n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345,
n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355,
n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365,
n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375,
n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385,
n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395,
n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405,
n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415,
n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425,
n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435,
n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445,
n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455,
n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465,
n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475,
n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558;
wire [1:0] FSM_selector_B;
wire [31:0] intDX;
wire [31:0] intDY;
wire [30:0] DMP;
wire [30:0] DmP;
wire [7:0] exp_oper_result;
wire [7:0] S_Oper_A_exp;
wire [4:1] LZA_output;
wire [25:0] Add_Subt_result;
wire [25:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [7:0] Exp_Operation_Module_Data_S;
wire [51:0] Barrel_Shifter_module_Mux_Array_Data_array;
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[25]), .CK(clk), .RN(n1557),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[51]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n248), .CK(clk),
.RN(n1552), .Q(Sgf_normalized_result[0]) );
DFFRXLTS Sel_C_Q_reg_0_ ( .D(n243), .CK(clk), .RN(n244), .Q(FSM_selector_C),
.QN(n1519) );
DFFRXLTS Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ ( .D(n667), .CK(
clk), .RN(n1552), .Q(add_overflow_flag), .QN(n1520) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(n240), .CK(clk),
.RN(n1549), .Q(Add_Subt_result[24]) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(n239), .CK(clk),
.RN(n1548), .Q(Add_Subt_result[23]) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(n238), .CK(clk),
.RN(n1548), .Q(Add_Subt_result[22]) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(n237), .CK(clk),
.RN(n1548), .Q(Add_Subt_result[21]), .QN(n1525) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(n236), .CK(clk),
.RN(n1548), .Q(Add_Subt_result[20]) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(n235), .CK(clk),
.RN(n1548), .Q(Add_Subt_result[19]) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(n234), .CK(clk),
.RN(n1547), .Q(Add_Subt_result[18]) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(n233), .CK(clk),
.RN(n1547), .Q(Add_Subt_result[17]), .QN(n1530) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(n232), .CK(clk),
.RN(n1547), .Q(Add_Subt_result[16]) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(n231), .CK(clk),
.RN(n1547), .Q(Add_Subt_result[15]) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(n230), .CK(clk),
.RN(n1547), .Q(Add_Subt_result[14]), .QN(n1521) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(n229), .CK(clk),
.RN(n1546), .Q(Add_Subt_result[13]) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(n228), .CK(clk),
.RN(n1546), .Q(Add_Subt_result[12]), .QN(n1451) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(n227), .CK(clk),
.RN(n1546), .Q(Add_Subt_result[11]), .QN(n1526) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(n226), .CK(clk),
.RN(n1547), .Q(Add_Subt_result[10]) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(n225), .CK(clk),
.RN(n1547), .Q(Add_Subt_result[9]), .QN(n1528) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(n224), .CK(clk),
.RN(n1547), .Q(Add_Subt_result[8]) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(n223), .CK(clk),
.RN(n1547), .Q(Add_Subt_result[7]), .QN(n1522) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(n222), .CK(clk),
.RN(n1547), .Q(Add_Subt_result[6]) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(n221), .CK(clk),
.RN(n1548), .Q(Add_Subt_result[5]) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(n220), .CK(clk),
.RN(n1548), .Q(Add_Subt_result[4]) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(n219), .CK(clk),
.RN(n1548), .Q(Add_Subt_result[3]) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(n218), .CK(clk),
.RN(n1548), .Q(Add_Subt_result[2]) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(n217), .CK(clk),
.RN(n1548), .Q(Add_Subt_result[1]), .QN(n1527) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(n216), .CK(clk),
.RN(n1557), .Q(Add_Subt_result[0]), .QN(n1452) );
DFFRXLTS XRegister_Q_reg_30_ ( .D(n213), .CK(clk), .RN(n1533), .Q(intDX[30]),
.QN(n1440) );
DFFRXLTS XRegister_Q_reg_29_ ( .D(n212), .CK(clk), .RN(n1533), .Q(intDX[29]),
.QN(n1441) );
DFFRXLTS XRegister_Q_reg_28_ ( .D(n211), .CK(clk), .RN(n1533), .QN(n1501) );
DFFRXLTS XRegister_Q_reg_27_ ( .D(n210), .CK(clk), .RN(n1533), .Q(intDX[27]),
.QN(n1489) );
DFFRXLTS XRegister_Q_reg_26_ ( .D(n209), .CK(clk), .RN(n1533), .Q(intDX[26]),
.QN(n1485) );
DFFRXLTS XRegister_Q_reg_25_ ( .D(n208), .CK(clk), .RN(n1533), .Q(intDX[25]),
.QN(n1443) );
DFFRXLTS XRegister_Q_reg_24_ ( .D(n207), .CK(clk), .RN(n1533), .Q(intDX[24])
);
DFFRXLTS XRegister_Q_reg_23_ ( .D(n206), .CK(clk), .RN(n1533), .Q(intDX[23]),
.QN(n1483) );
DFFRXLTS XRegister_Q_reg_22_ ( .D(n205), .CK(clk), .RN(n1533), .Q(intDX[22]),
.QN(n1446) );
DFFRXLTS XRegister_Q_reg_21_ ( .D(n204), .CK(clk), .RN(n1533), .Q(intDX[21]),
.QN(n1480) );
DFFRXLTS XRegister_Q_reg_20_ ( .D(n203), .CK(clk), .RN(n1534), .Q(intDX[20]),
.QN(n1445) );
DFFRXLTS XRegister_Q_reg_19_ ( .D(n202), .CK(clk), .RN(n1534), .Q(intDX[19]),
.QN(n1436) );
DFFRXLTS XRegister_Q_reg_18_ ( .D(n201), .CK(clk), .RN(n1534), .Q(intDX[18]),
.QN(n1484) );
DFFRXLTS XRegister_Q_reg_17_ ( .D(n200), .CK(clk), .RN(n1534), .Q(intDX[17]),
.QN(n1494) );
DFFRXLTS XRegister_Q_reg_16_ ( .D(n199), .CK(clk), .RN(n1534), .Q(intDX[16]),
.QN(n1509) );
DFFRXLTS XRegister_Q_reg_15_ ( .D(n198), .CK(clk), .RN(n1534), .Q(intDX[15]),
.QN(n1479) );
DFFRXLTS XRegister_Q_reg_14_ ( .D(n197), .CK(clk), .RN(n1534), .Q(intDX[14]),
.QN(n1487) );
DFFRXLTS XRegister_Q_reg_13_ ( .D(n196), .CK(clk), .RN(n1534), .Q(intDX[13]),
.QN(n1442) );
DFFRXLTS XRegister_Q_reg_12_ ( .D(n195), .CK(clk), .RN(n1534), .Q(intDX[12]),
.QN(n1444) );
DFFRXLTS XRegister_Q_reg_11_ ( .D(n194), .CK(clk), .RN(n1534), .Q(intDX[11]),
.QN(n1481) );
DFFRXLTS XRegister_Q_reg_10_ ( .D(n193), .CK(clk), .RN(n1535), .Q(intDX[10]),
.QN(n1506) );
DFFRXLTS XRegister_Q_reg_9_ ( .D(n192), .CK(clk), .RN(n1535), .Q(intDX[9]),
.QN(n1488) );
DFFRXLTS XRegister_Q_reg_8_ ( .D(n191), .CK(clk), .RN(n1535), .Q(intDX[8]),
.QN(n1482) );
DFFRXLTS XRegister_Q_reg_7_ ( .D(n190), .CK(clk), .RN(n1535), .QN(n1447) );
DFFRXLTS XRegister_Q_reg_6_ ( .D(n189), .CK(clk), .RN(n1551), .Q(intDX[6]),
.QN(n1507) );
DFFRXLTS XRegister_Q_reg_5_ ( .D(n188), .CK(clk), .RN(n1554), .Q(intDX[5]),
.QN(n1448) );
DFFRXLTS XRegister_Q_reg_4_ ( .D(n187), .CK(clk), .RN(n1553), .Q(intDX[4]),
.QN(n1508) );
DFFRXLTS XRegister_Q_reg_3_ ( .D(n186), .CK(clk), .RN(n1553), .Q(intDX[3]),
.QN(n1490) );
DFFRXLTS XRegister_Q_reg_2_ ( .D(n185), .CK(clk), .RN(n1553), .Q(intDX[2]),
.QN(n1492) );
DFFRXLTS XRegister_Q_reg_1_ ( .D(n184), .CK(clk), .RN(n1553), .Q(intDX[1]),
.QN(n1491) );
DFFRXLTS XRegister_Q_reg_0_ ( .D(n183), .CK(clk), .RN(n1552), .Q(intDX[0]),
.QN(n1493) );
DFFRXLTS YRegister_Q_reg_30_ ( .D(n180), .CK(clk), .RN(n1535), .Q(intDY[30]),
.QN(n1449) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n179), .CK(clk), .RN(
n1550), .Q(DmP[30]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n178), .CK(clk), .RN(
n1551), .Q(DMP[30]) );
DFFRXLTS YRegister_Q_reg_29_ ( .D(n177), .CK(clk), .RN(n1535), .Q(intDY[29]),
.QN(n1498) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n176), .CK(clk), .RN(
n1550), .Q(DmP[29]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n175), .CK(clk), .RN(
n1551), .Q(DMP[29]) );
DFFRXLTS YRegister_Q_reg_28_ ( .D(n174), .CK(clk), .RN(n1535), .Q(intDY[28])
);
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n173), .CK(clk), .RN(
n1550), .Q(DmP[28]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n172), .CK(clk), .RN(
n1551), .Q(DMP[28]) );
DFFRXLTS YRegister_Q_reg_27_ ( .D(n171), .CK(clk), .RN(n1535), .Q(intDY[27])
);
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n170), .CK(clk), .RN(
n1549), .Q(DmP[27]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n169), .CK(clk), .RN(
n1551), .Q(DMP[27]) );
DFFRXLTS YRegister_Q_reg_26_ ( .D(n168), .CK(clk), .RN(n1535), .Q(intDY[26]),
.QN(n1496) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n167), .CK(clk), .RN(
n1549), .Q(DmP[26]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n166), .CK(clk), .RN(
n1551), .Q(DMP[26]) );
DFFRXLTS YRegister_Q_reg_25_ ( .D(n165), .CK(clk), .RN(n1535), .Q(intDY[25]),
.QN(n1499) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n164), .CK(clk), .RN(
n1549), .Q(DmP[25]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n163), .CK(clk), .RN(
n1550), .Q(DMP[25]) );
DFFRXLTS YRegister_Q_reg_24_ ( .D(n162), .CK(clk), .RN(n1536), .Q(intDY[24]),
.QN(n1486) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n161), .CK(clk), .RN(
n1549), .Q(DmP[24]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n160), .CK(clk), .RN(
n1550), .Q(DMP[24]) );
DFFRXLTS YRegister_Q_reg_23_ ( .D(n159), .CK(clk), .RN(n1536), .Q(intDY[23]),
.QN(n1438) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n158), .CK(clk), .RN(
n1549), .Q(DmP[23]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n157), .CK(clk), .RN(
n1550), .Q(DMP[23]) );
DFFRXLTS YRegister_Q_reg_22_ ( .D(n156), .CK(clk), .RN(n1536), .Q(intDY[22]),
.QN(n1473) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n155), .CK(clk), .RN(
n1536), .Q(DmP[22]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n154), .CK(clk), .RN(
n1557), .Q(DMP[22]) );
DFFRXLTS YRegister_Q_reg_21_ ( .D(n153), .CK(clk), .RN(n1536), .Q(intDY[21]),
.QN(n1495) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n152), .CK(clk), .RN(
n1536), .Q(DmP[21]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n151), .CK(clk), .RN(
n1557), .Q(DMP[21]) );
DFFRXLTS YRegister_Q_reg_20_ ( .D(n150), .CK(clk), .RN(n1536), .Q(intDY[20]),
.QN(n1497) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n149), .CK(clk), .RN(
n1536), .Q(DmP[20]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n148), .CK(clk), .RN(
n1557), .Q(DMP[20]) );
DFFRXLTS YRegister_Q_reg_19_ ( .D(n147), .CK(clk), .RN(n1536), .Q(intDY[19]),
.QN(n1500) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n146), .CK(clk), .RN(
n1536), .Q(DmP[19]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n145), .CK(clk), .RN(
n1557), .Q(DMP[19]) );
DFFRXLTS YRegister_Q_reg_18_ ( .D(n144), .CK(clk), .RN(n1537), .Q(intDY[18]),
.QN(n1450) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n143), .CK(clk), .RN(
n1537), .Q(DmP[18]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n142), .CK(clk), .RN(
n1556), .Q(DMP[18]) );
DFFRXLTS YRegister_Q_reg_17_ ( .D(n141), .CK(clk), .RN(n1537), .Q(intDY[17]),
.QN(n1518) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n140), .CK(clk), .RN(
n1537), .Q(DmP[17]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n139), .CK(clk), .RN(
n1556), .Q(DMP[17]) );
DFFRXLTS YRegister_Q_reg_16_ ( .D(n138), .CK(clk), .RN(n1537), .Q(intDY[16])
);
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n137), .CK(clk), .RN(
n1537), .Q(DmP[16]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n136), .CK(clk), .RN(
n1556), .Q(DMP[16]) );
DFFRXLTS YRegister_Q_reg_15_ ( .D(n135), .CK(clk), .RN(n1537), .Q(intDY[15]),
.QN(n1439) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n134), .CK(clk), .RN(
n1537), .Q(DmP[15]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n133), .CK(clk), .RN(
n1556), .Q(DMP[15]) );
DFFRXLTS YRegister_Q_reg_14_ ( .D(n132), .CK(clk), .RN(n1537), .Q(intDY[14]),
.QN(n1472) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n131), .CK(clk), .RN(
n1537), .Q(DmP[14]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n130), .CK(clk), .RN(
n1556), .Q(DMP[14]) );
DFFRXLTS YRegister_Q_reg_13_ ( .D(n129), .CK(clk), .RN(n1538), .Q(intDY[13]),
.QN(n1469) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n128), .CK(clk), .RN(
n1538), .Q(DmP[13]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n127), .CK(clk), .RN(
n1555), .Q(DMP[13]) );
DFFRXLTS YRegister_Q_reg_12_ ( .D(n126), .CK(clk), .RN(n1538), .Q(intDY[12]),
.QN(n1471) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n125), .CK(clk), .RN(
n1538), .Q(DmP[12]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n124), .CK(clk), .RN(
n1555), .Q(DMP[12]) );
DFFRXLTS YRegister_Q_reg_11_ ( .D(n123), .CK(clk), .RN(n1538), .Q(intDY[11]),
.QN(n1475) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n122), .CK(clk), .RN(
n1538), .Q(DmP[11]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n121), .CK(clk), .RN(
n1555), .Q(DMP[11]) );
DFFRXLTS YRegister_Q_reg_10_ ( .D(n120), .CK(clk), .RN(n1538), .Q(intDY[10])
);
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n119), .CK(clk), .RN(
n1538), .Q(DmP[10]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n118), .CK(clk), .RN(
n1555), .Q(DMP[10]) );
DFFRXLTS YRegister_Q_reg_9_ ( .D(n117), .CK(clk), .RN(n1538), .Q(intDY[9])
);
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n116), .CK(clk), .RN(
n1538), .Q(DmP[9]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n115), .CK(clk), .RN(
n1555), .Q(DMP[9]) );
DFFRXLTS YRegister_Q_reg_8_ ( .D(n114), .CK(clk), .RN(n1539), .Q(intDY[8]),
.QN(n1474) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n113), .CK(clk), .RN(
n1539), .Q(DmP[8]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n112), .CK(clk), .RN(
n1554), .Q(DMP[8]) );
DFFRXLTS YRegister_Q_reg_7_ ( .D(n111), .CK(clk), .RN(n1539), .Q(intDY[7])
);
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n110), .CK(clk), .RN(
n1539), .Q(DmP[7]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n109), .CK(clk), .RN(
n1554), .Q(DMP[7]) );
DFFRXLTS YRegister_Q_reg_6_ ( .D(n108), .CK(clk), .RN(n1539), .Q(intDY[6])
);
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n107), .CK(clk), .RN(
n1539), .Q(DmP[6]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n106), .CK(clk), .RN(
n1554), .Q(DMP[6]) );
DFFRXLTS YRegister_Q_reg_5_ ( .D(n105), .CK(clk), .RN(n1539), .Q(intDY[5])
);
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n104), .CK(clk), .RN(
n1539), .Q(DmP[5]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n103), .CK(clk), .RN(
n1554), .Q(DMP[5]) );
DFFRXLTS YRegister_Q_reg_4_ ( .D(n102), .CK(clk), .RN(n1539), .Q(intDY[4])
);
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n101), .CK(clk), .RN(
n1539), .Q(DmP[4]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n100), .CK(clk), .RN(
n1553), .Q(DMP[4]) );
DFFRXLTS YRegister_Q_reg_3_ ( .D(n99), .CK(clk), .RN(n1540), .Q(intDY[3]),
.QN(n1468) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(n98), .CK(clk), .RN(
n1540), .Q(DmP[3]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n97), .CK(clk), .RN(
n1553), .Q(DMP[3]) );
DFFRXLTS YRegister_Q_reg_2_ ( .D(n96), .CK(clk), .RN(n1540), .Q(intDY[2]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n95), .CK(clk), .RN(
n1540), .Q(DmP[2]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n94), .CK(clk), .RN(
n1553), .Q(DMP[2]) );
DFFRXLTS YRegister_Q_reg_1_ ( .D(n93), .CK(clk), .RN(n1540), .Q(intDY[1]),
.QN(n1470) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n92), .CK(clk), .RN(
n1540), .Q(DmP[1]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n91), .CK(clk), .RN(
n1552), .Q(DMP[1]) );
DFFRXLTS YRegister_Q_reg_0_ ( .D(n90), .CK(clk), .RN(n1540), .Q(intDY[0]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n89), .CK(clk), .RN(
n1540), .Q(DmP[0]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n88), .CK(clk), .RN(
n1552), .Q(DMP[0]) );
DFFRXLTS Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(n86), .CK(clk),
.RN(n1558), .Q(sign_final_result), .QN(n1453) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(n85), .CK(clk), .RN(
n1551), .Q(exp_oper_result[6]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(n84), .CK(clk), .RN(
n1551), .Q(exp_oper_result[5]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(n83), .CK(clk), .RN(
n1551), .Q(exp_oper_result[4]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n82), .CK(clk), .RN(
n1550), .Q(exp_oper_result[3]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n81), .CK(clk), .RN(
n1550), .Q(exp_oper_result[2]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n80), .CK(clk), .RN(
n1550), .Q(exp_oper_result[1]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n79), .CK(clk), .RN(
n1549), .Q(exp_oper_result[0]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(n78), .CK(clk), .RN(
n1551), .Q(exp_oper_result[7]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ ( .D(n76), .CK(clk), .RN(n1549), .Q(LZA_output[3]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ ( .D(n75), .CK(clk), .RN(n1549), .Q(LZA_output[2]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ ( .D(n74), .CK(clk), .RN(n1549), .Q(LZA_output[1]), .QN(n1467) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ ( .D(n73), .CK(clk), .RN(n1540), .QN(n1531) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ ( .D(n72), .CK(clk), .RN(n1550), .Q(LZA_output[4]) );
DFFRXLTS Sel_B_Q_reg_0_ ( .D(n71), .CK(clk), .RN(n244), .Q(FSM_selector_B[0]), .QN(n1459) );
DFFRXLTS Sel_B_Q_reg_1_ ( .D(n70), .CK(clk), .RN(n244), .Q(FSM_selector_B[1]), .QN(n1437) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[18]), .CK(clk), .RN(n1540),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[44]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[17]), .CK(clk), .RN(n1541),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[43]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[16]), .CK(clk), .RN(n1541),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[42]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[15]), .CK(clk), .RN(n1541),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[41]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[14]), .CK(clk), .RN(n1541),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[40]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[13]), .CK(clk), .RN(n1541),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[39]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[12]), .CK(clk), .RN(n1541),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[38]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[11]), .CK(clk), .RN(n1541),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[37]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[10]), .CK(clk), .RN(n1541),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[36]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[9]), .CK(clk), .RN(n1541),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[35]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[8]), .CK(clk), .RN(n1541),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[34]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[7]), .CK(clk), .RN(n1542),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[33]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[3]), .CK(clk), .RN(n1542),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[29]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[6]), .CK(clk), .RN(n1542),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[32]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[2]), .CK(clk), .RN(n1542),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[28]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[5]), .CK(clk), .RN(n1542),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[31]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[1]), .CK(clk), .RN(n1542),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[27]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[4]), .CK(clk), .RN(n1542),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[30]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[0]), .CK(clk), .RN(n1542),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[26]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[20]), .CK(clk), .RN(n1543),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[46]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[19]), .CK(clk), .RN(n1543),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[45]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[24]), .CK(clk), .RN(n1558),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[50]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[23]), .CK(clk), .RN(n1543),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[49]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[22]), .CK(clk), .RN(n1544),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[48]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[21]), .CK(clk), .RN(n1544),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[47]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n59), .CK(clk),
.RN(n1555), .Q(Sgf_normalized_result[12]), .QN(n1462) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n57), .CK(clk),
.RN(n1555), .Q(Sgf_normalized_result[13]), .QN(n1466) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n55), .CK(clk),
.RN(n1554), .Q(Sgf_normalized_result[11]), .QN(n1461) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n53), .CK(clk),
.RN(n1555), .Q(Sgf_normalized_result[14]), .QN(n1465) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n51), .CK(clk),
.RN(n1554), .Q(Sgf_normalized_result[10]), .QN(n1460) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n49), .CK(clk),
.RN(n1555), .Q(Sgf_normalized_result[15]), .QN(n1464) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n47), .CK(clk), .RN(
n1554), .Q(Sgf_normalized_result[9]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n45), .CK(clk),
.RN(n1555), .Q(Sgf_normalized_result[16]), .QN(n1463) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n43), .CK(clk), .RN(
n1554), .Q(Sgf_normalized_result[8]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n41), .CK(clk),
.RN(n1556), .Q(Sgf_normalized_result[17]), .QN(n1478) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n39), .CK(clk), .RN(
n1554), .Q(Sgf_normalized_result[7]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n37), .CK(clk),
.RN(n1556), .Q(Sgf_normalized_result[18]), .QN(n1477) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n35), .CK(clk), .RN(
n1553), .Q(Sgf_normalized_result[6]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n33), .CK(clk),
.RN(n1556), .Q(Sgf_normalized_result[19]), .QN(n1476) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n31), .CK(clk), .RN(
n1553), .Q(Sgf_normalized_result[5]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n29), .CK(clk),
.RN(n1556), .Q(Sgf_normalized_result[20]), .QN(n1505) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n27), .CK(clk), .RN(
n1553), .Q(Sgf_normalized_result[4]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n25), .CK(clk),
.RN(n1556), .Q(Sgf_normalized_result[21]), .QN(n1504) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n23), .CK(clk), .RN(
n1552), .Q(Sgf_normalized_result[3]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n21), .CK(clk),
.RN(n1557), .Q(Sgf_normalized_result[22]), .QN(n1503) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n19), .CK(clk), .RN(
n1552), .Q(Sgf_normalized_result[2]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n17), .CK(clk),
.RN(n1557), .Q(Sgf_normalized_result[23]), .QN(n1502) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n15), .CK(clk), .RN(
n1552), .Q(Sgf_normalized_result[1]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n14), .CK(clk),
.RN(n1557), .Q(Sgf_normalized_result[24]), .QN(n1524) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n12), .CK(clk),
.RN(n1558), .Q(Sgf_normalized_result[25]) );
CMPR32X2TS DP_OP_42J1_122_8048_U8 ( .A(DP_OP_42J1_122_8048_n19), .B(
S_Oper_A_exp[1]), .C(DP_OP_42J1_122_8048_n8), .CO(
DP_OP_42J1_122_8048_n7), .S(Exp_Operation_Module_Data_S[1]) );
CMPR32X2TS DP_OP_42J1_122_8048_U7 ( .A(DP_OP_42J1_122_8048_n18), .B(
S_Oper_A_exp[2]), .C(DP_OP_42J1_122_8048_n7), .CO(
DP_OP_42J1_122_8048_n6), .S(Exp_Operation_Module_Data_S[2]) );
CMPR32X2TS DP_OP_42J1_122_8048_U6 ( .A(DP_OP_42J1_122_8048_n17), .B(
S_Oper_A_exp[3]), .C(DP_OP_42J1_122_8048_n6), .CO(
DP_OP_42J1_122_8048_n5), .S(Exp_Operation_Module_Data_S[3]) );
CMPR32X2TS DP_OP_42J1_122_8048_U5 ( .A(DP_OP_42J1_122_8048_n16), .B(
S_Oper_A_exp[4]), .C(DP_OP_42J1_122_8048_n5), .CO(
DP_OP_42J1_122_8048_n4), .S(Exp_Operation_Module_Data_S[4]) );
CMPR32X2TS DP_OP_42J1_122_8048_U4 ( .A(DP_OP_42J1_122_8048_n15), .B(
S_Oper_A_exp[5]), .C(DP_OP_42J1_122_8048_n4), .CO(
DP_OP_42J1_122_8048_n3), .S(Exp_Operation_Module_Data_S[5]) );
CMPR32X2TS DP_OP_42J1_122_8048_U3 ( .A(DP_OP_42J1_122_8048_n14), .B(
S_Oper_A_exp[6]), .C(DP_OP_42J1_122_8048_n3), .CO(
DP_OP_42J1_122_8048_n2), .S(Exp_Operation_Module_Data_S[6]) );
CMPR32X2TS DP_OP_42J1_122_8048_U2 ( .A(DP_OP_42J1_122_8048_n13), .B(
S_Oper_A_exp[7]), .C(DP_OP_42J1_122_8048_n2), .CO(
DP_OP_42J1_122_8048_n1), .S(Exp_Operation_Module_Data_S[7]) );
CMPR32X2TS DP_OP_42J1_122_8048_U9 ( .A(S_Oper_A_exp[0]), .B(
FSM_exp_operation_A_S), .C(DP_OP_42J1_122_8048_n20), .CO(
DP_OP_42J1_122_8048_n8), .S(Exp_Operation_Module_Data_S[0]) );
DFFRXLTS FS_Module_state_reg_reg_0_ ( .D(n214), .CK(clk), .RN(n1552), .Q(
FS_Module_state_reg[0]), .QN(n1455) );
DFFRXLTS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(n215), .CK(clk),
.RN(n1557), .Q(Add_Subt_result[25]), .QN(n1523) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n28),
.CK(clk), .RN(n1545), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n60),
.CK(clk), .RN(n1543), .Q(final_result_ieee[30]) );
DFFRXLTS YRegister_Q_reg_31_ ( .D(n87), .CK(clk), .RN(n1558), .Q(intDY[31])
);
DFFRXLTS FS_Module_state_reg_reg_1_ ( .D(n247), .CK(clk), .RN(n1558), .Q(
FS_Module_state_reg[1]), .QN(n1456) );
DFFRXLTS FS_Module_state_reg_reg_2_ ( .D(n246), .CK(clk), .RN(n1558), .Q(
FS_Module_state_reg[2]), .QN(n1457) );
DFFRXLTS Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n77), .CK(clk), .RN(
n1546), .Q(overflow_flag), .QN(n1532) );
DFFRXLTS Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n69), .CK(clk), .RN(
n1546), .Q(underflow_flag), .QN(n1529) );
DFFRXLTS Sel_D_Q_reg_0_ ( .D(n245), .CK(clk), .RN(n244), .Q(FSM_selector_D)
);
DFFRXLTS FS_Module_state_reg_reg_3_ ( .D(n242), .CK(clk), .RN(n1552), .Q(
FS_Module_state_reg[3]), .QN(n1458) );
DFFRXLTS XRegister_Q_reg_31_ ( .D(n182), .CK(clk), .RN(n1558), .Q(intDX[31]),
.QN(n1454) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n68),
.CK(clk), .RN(n1542), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n58),
.CK(clk), .RN(n1544), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n56),
.CK(clk), .RN(n1544), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n54), .CK(
clk), .RN(n1544), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n52),
.CK(clk), .RN(n1544), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n50), .CK(
clk), .RN(n1544), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n48),
.CK(clk), .RN(n1544), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n44),
.CK(clk), .RN(n1544), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n40),
.CK(clk), .RN(n1544), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n36),
.CK(clk), .RN(n1545), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n32),
.CK(clk), .RN(n1545), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n24),
.CK(clk), .RN(n1545), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n20),
.CK(clk), .RN(n1545), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n16),
.CK(clk), .RN(n1545), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n13),
.CK(clk), .RN(n1545), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n1517),
.CK(clk), .RN(n1545), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n1516),
.CK(clk), .RN(n1545), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n1515),
.CK(clk), .RN(n1545), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n1514),
.CK(clk), .RN(n1546), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n1513),
.CK(clk), .RN(n1546), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n1512),
.CK(clk), .RN(n1546), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n1511),
.CK(clk), .RN(n1546), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n1510),
.CK(clk), .RN(n1546), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n62),
.CK(clk), .RN(n1543), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n61),
.CK(clk), .RN(n1543), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n67),
.CK(clk), .RN(n1542), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n66),
.CK(clk), .RN(n1543), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n65),
.CK(clk), .RN(n1543), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n64),
.CK(clk), .RN(n1543), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n63),
.CK(clk), .RN(n1543), .Q(final_result_ieee[27]) );
DFFRXLTS ASRegister_Q_reg_0_ ( .D(n181), .CK(clk), .RN(n1558), .Q(intAS) );
OAI21XLTS U892 ( .A0(intDX[18]), .A1(n1450), .B0(n760), .Y(n764) );
INVX2TS U893 ( .A(n919), .Y(n1305) );
INVX2TS U894 ( .A(n919), .Y(n1267) );
INVX2TS U895 ( .A(n1093), .Y(n1076) );
OAI211XLTS U896 ( .A0(n717), .A1(n773), .B0(n716), .C0(n715), .Y(n722) );
INVX2TS U897 ( .A(n1026), .Y(n783) );
NOR2XLTS U898 ( .A(n1074), .B(Add_Subt_result[18]), .Y(n1089) );
AOI211XLTS U899 ( .A0(n769), .A1(n768), .B0(n767), .C0(n766), .Y(n775) );
NOR2XLTS U900 ( .A(n1465), .B(n702), .Y(n675) );
NOR2XLTS U901 ( .A(n1478), .B(n702), .Y(n673) );
NOR2XLTS U902 ( .A(FS_Module_state_reg[1]), .B(n1457), .Y(n824) );
NOR3XLTS U903 ( .A(n939), .B(n659), .C(n921), .Y(n954) );
NOR2XLTS U904 ( .A(n655), .B(n926), .Y(n1398) );
NOR2XLTS U905 ( .A(n1459), .B(FSM_selector_B[1]), .Y(n1012) );
INVX2TS U906 ( .A(n795), .Y(n800) );
NOR2XLTS U907 ( .A(n1456), .B(FS_Module_state_reg[2]), .Y(n1024) );
NAND2X1TS U908 ( .A(FS_Module_state_reg[0]), .B(n1024), .Y(n1025) );
INVX2TS U909 ( .A(n1422), .Y(n1431) );
NOR2XLTS U910 ( .A(FS_Module_state_reg[0]), .B(n1458), .Y(n1029) );
INVX2TS U911 ( .A(n1359), .Y(n1006) );
NAND2X1TS U912 ( .A(FS_Module_state_reg[2]), .B(n1023), .Y(n1032) );
INVX2TS U913 ( .A(n935), .Y(n939) );
NOR2XLTS U914 ( .A(n976), .B(FS_Module_state_reg[1]), .Y(n1420) );
INVX2TS U915 ( .A(n890), .Y(n975) );
OAI21XLTS U916 ( .A0(n988), .A1(n1529), .B0(n987), .Y(n69) );
OAI31X1TS U917 ( .A0(n1245), .A1(n1311), .A2(n937), .B0(n936), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[25]) );
INVX2TS U918 ( .A(n864), .Y(ready) );
OAI211X1TS U919 ( .A0(Add_Subt_result[3]), .A1(n1097), .B0(n1096), .C0(n1095), .Y(n1416) );
NOR3BX1TS U920 ( .AN(n1099), .B(Add_Subt_result[3]), .C(Add_Subt_result[2]),
.Y(n1094) );
XOR2X1TS U921 ( .A(DP_OP_42J1_122_8048_n1), .B(FSM_exp_operation_A_S), .Y(
n1230) );
NAND2BX1TS U922 ( .AN(Add_Subt_result[5]), .B(n1100), .Y(n1081) );
INVX1TS U923 ( .A(n1078), .Y(n1415) );
OAI31XLTS U924 ( .A0(Add_Subt_result[5]), .A1(Add_Subt_result[9]), .A2(
Add_Subt_result[8]), .B0(n1082), .Y(n1083) );
OAI31XLTS U925 ( .A0(Add_Subt_result[12]), .A1(Add_Subt_result[11]), .A2(
Add_Subt_result[13]), .B0(n1098), .Y(n1102) );
INVX1TS U926 ( .A(n1238), .Y(n957) );
NAND3BX1TS U927 ( .AN(n758), .B(n756), .C(n755), .Y(n776) );
NOR3X1TS U928 ( .A(n981), .B(n1374), .C(n980), .Y(n983) );
INVX1TS U929 ( .A(n931), .Y(n656) );
INVX1TS U930 ( .A(n984), .Y(n988) );
XOR2X1TS U931 ( .A(n696), .B(n678), .Y(n1217) );
XOR2X1TS U932 ( .A(n696), .B(n671), .Y(n1151) );
XOR2X1TS U933 ( .A(n1038), .B(n670), .Y(n1133) );
INVX1TS U934 ( .A(n926), .Y(n921) );
XOR2X1TS U935 ( .A(n696), .B(n674), .Y(n1204) );
XOR2X1TS U936 ( .A(n1038), .B(n672), .Y(n1169) );
XOR2X1TS U937 ( .A(n696), .B(n680), .Y(n1200) );
INVX1TS U938 ( .A(n950), .Y(n784) );
XOR2X1TS U939 ( .A(n1038), .B(n673), .Y(n1187) );
XOR2X1TS U940 ( .A(n696), .B(n695), .Y(n1195) );
XOR2X1TS U941 ( .A(n1038), .B(n699), .Y(n1178) );
XOR2X1TS U942 ( .A(n1038), .B(n708), .Y(n1141) );
AOI2BB2X1TS U943 ( .B0(n722), .B1(n771), .A0N(n721), .A1N(n720), .Y(n777) );
INVX1TS U944 ( .A(n915), .Y(n940) );
INVX1TS U945 ( .A(n1028), .Y(n978) );
NAND2XLTS U946 ( .A(n782), .B(FS_Module_state_reg[0]), .Y(n1019) );
INVX1TS U947 ( .A(n1177), .Y(n700) );
NAND2XLTS U948 ( .A(n1455), .B(n782), .Y(n1026) );
INVX1TS U949 ( .A(n1194), .Y(n697) );
INVX1TS U950 ( .A(n1159), .Y(n705) );
NOR2X1TS U951 ( .A(n1505), .B(n702), .Y(n703) );
NOR2X1TS U952 ( .A(n1477), .B(n707), .Y(n699) );
NOR2X1TS U953 ( .A(n1463), .B(n707), .Y(n695) );
INVX1TS U954 ( .A(n1140), .Y(n709) );
NOR2X1TS U955 ( .A(n1503), .B(n707), .Y(n708) );
NAND2BX1TS U956 ( .AN(Sgf_normalized_result[25]), .B(n707), .Y(n1034) );
NOR2X1TS U957 ( .A(n1476), .B(n707), .Y(n672) );
OAI21X1TS U958 ( .A0(intDX[26]), .A1(n1496), .B0(n714), .Y(n773) );
AOI211X1TS U959 ( .A0(intDY[28]), .A1(n1501), .B0(n720), .C0(n718), .Y(n771)
);
OAI211X1TS U960 ( .A0(intDX[20]), .A1(n1497), .B0(n769), .C0(n754), .Y(n763)
);
OAI211X1TS U961 ( .A0(intDX[12]), .A1(n1471), .B0(n749), .C0(n723), .Y(n753)
);
NAND2XLTS U962 ( .A(Sgf_normalized_result[1]), .B(n1127), .Y(n666) );
NAND2XLTS U963 ( .A(FSM_selector_C), .B(n824), .Y(n785) );
NOR2X1TS U964 ( .A(n1499), .B(intDX[25]), .Y(n772) );
NOR2X1TS U965 ( .A(Add_Subt_result[21]), .B(Add_Subt_result[20]), .Y(n1110)
);
NAND2BX1TS U966 ( .AN(intDX[19]), .B(intDY[19]), .Y(n760) );
NAND2BX1TS U967 ( .AN(intDX[24]), .B(intDY[24]), .Y(n770) );
NOR3X1TS U968 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[1]), .C(
FS_Module_state_reg[3]), .Y(n982) );
NOR2X1TS U969 ( .A(Add_Subt_result[25]), .B(Add_Subt_result[24]), .Y(n1111)
);
OR2X2TS U970 ( .A(FSM_selector_B[0]), .B(FSM_selector_B[1]), .Y(n1014) );
NOR2X1TS U971 ( .A(Add_Subt_result[17]), .B(Add_Subt_result[16]), .Y(n1107)
);
NOR2X1TS U972 ( .A(n1498), .B(intDX[29]), .Y(n718) );
NOR2X1TS U973 ( .A(n1518), .B(intDX[17]), .Y(n758) );
NAND2BX1TS U974 ( .AN(intDX[27]), .B(intDY[27]), .Y(n714) );
ADDFHX1TS U975 ( .A(n1035), .B(n1034), .CI(n1033), .CO(n711), .S(n1036) );
ADDFHX2TS U976 ( .A(n1125), .B(n1124), .CI(n1123), .CO(n1033), .S(n1126) );
XOR2XLTS U977 ( .A(n1143), .B(n1142), .Y(n1144) );
XOR2XLTS U978 ( .A(n1162), .B(n1161), .Y(n1163) );
XOR2XLTS U979 ( .A(n1180), .B(n1179), .Y(n1181) );
XOR2XLTS U980 ( .A(n1197), .B(n1196), .Y(n1198) );
MXI2X1TS U981 ( .A(n1532), .B(n1233), .S0(n1232), .Y(n77) );
NOR2X1TS U982 ( .A(Add_Subt_result[4]), .B(n1081), .Y(n1099) );
NOR3X1TS U983 ( .A(Add_Subt_result[7]), .B(Add_Subt_result[6]), .C(n1078),
.Y(n1100) );
NOR2X1TS U984 ( .A(Add_Subt_result[10]), .B(n1076), .Y(n1082) );
XOR2XLTS U985 ( .A(n1175), .B(n1174), .Y(n1176) );
INVX1TS U986 ( .A(n970), .Y(n898) );
NOR2X1TS U987 ( .A(Add_Subt_result[11]), .B(n1116), .Y(n1417) );
NAND2BX1TS U988 ( .AN(Add_Subt_result[13]), .B(n1098), .Y(n1116) );
NAND2BX1TS U989 ( .AN(n1052), .B(n654), .Y(n1067) );
NOR2X1TS U990 ( .A(Add_Subt_result[14]), .B(n1112), .Y(n1098) );
OR2X2TS U991 ( .A(n778), .B(n993), .Y(n1000) );
NOR2X1TS U992 ( .A(n939), .B(n938), .Y(n1375) );
AFHCONX2TS U993 ( .A(n1138), .B(n1137), .CI(n1136), .CON(n1145), .S(n1139)
);
NOR2X1TS U994 ( .A(n653), .B(n926), .Y(n1394) );
XOR2XLTS U995 ( .A(n1141), .B(n1140), .Y(n1142) );
OAI31XLTS U996 ( .A0(FS_Module_state_reg[0]), .A1(FS_Module_state_reg[1]),
.A2(FS_Module_state_reg[3]), .B0(n863), .Y(n865) );
XOR2XLTS U997 ( .A(n1178), .B(n1177), .Y(n1179) );
XOR2XLTS U998 ( .A(n1195), .B(n1194), .Y(n1196) );
XOR2XLTS U999 ( .A(n1160), .B(n1159), .Y(n1161) );
XOR2XLTS U1000 ( .A(n1173), .B(n1172), .Y(n1174) );
NOR2X1TS U1001 ( .A(n799), .B(n795), .Y(n961) );
NOR2X1TS U1002 ( .A(n1073), .B(n1103), .Y(n1410) );
NOR2X1TS U1003 ( .A(n1075), .B(Add_Subt_result[15]), .Y(n1086) );
AO22X1TS U1004 ( .A0(LZA_output[2]), .A1(n1012), .B0(n665), .B1(
exp_oper_result[2]), .Y(n1236) );
NOR2X1TS U1005 ( .A(n1072), .B(Add_Subt_result[19]), .Y(n1104) );
AND2X2TS U1006 ( .A(n1455), .B(n979), .Y(n974) );
OR2X2TS U1007 ( .A(n977), .B(FS_Module_state_reg[3]), .Y(n1153) );
NAND2BX1TS U1008 ( .AN(n825), .B(n824), .Y(n826) );
MX2X1TS U1009 ( .A(DMP[11]), .B(Sgf_normalized_result[13]), .S0(n704), .Y(
n1222) );
NOR2XLTS U1010 ( .A(n1466), .B(n702), .Y(n676) );
INVX1TS U1011 ( .A(n825), .Y(n862) );
INVX1TS U1012 ( .A(n1012), .Y(n1015) );
NAND2XLTS U1013 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[3]),
.Y(n825) );
NAND2XLTS U1014 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[1]),
.Y(n977) );
NOR2X1TS U1015 ( .A(n1449), .B(intDX[30]), .Y(n720) );
NOR2X2TS U1016 ( .A(n1130), .B(n690), .Y(n1136) );
AFHCINX2TS U1017 ( .CIN(n1220), .B(n1221), .A(n1222), .S(n1223), .CO(n1212)
);
NAND3X1TS U1018 ( .A(n983), .B(n1063), .C(n244), .Y(FSM_exp_operation_A_S)
);
NAND4BXLTS U1019 ( .AN(n979), .B(n978), .C(add_overflow_flag), .D(n1405),
.Y(n980) );
MX2X1TS U1020 ( .A(DMP[24]), .B(exp_oper_result[1]), .S0(n1070), .Y(
S_Oper_A_exp[1]) );
XOR2XLTS U1021 ( .A(FSM_exp_operation_A_S), .B(n1016), .Y(
DP_OP_42J1_122_8048_n19) );
MX2X1TS U1022 ( .A(DMP[27]), .B(exp_oper_result[4]), .S0(n1070), .Y(
S_Oper_A_exp[4]) );
XOR2XLTS U1023 ( .A(FSM_exp_operation_A_S), .B(n1010), .Y(
DP_OP_42J1_122_8048_n16) );
AO22XLTS U1024 ( .A0(LZA_output[4]), .A1(n1012), .B0(n665), .B1(DmP[27]),
.Y(n1010) );
NAND2BXLTS U1025 ( .AN(intDX[13]), .B(intDY[13]), .Y(n723) );
NOR2BX1TS U1026 ( .AN(n1141), .B(n709), .Y(n710) );
NAND2BXLTS U1027 ( .AN(n1081), .B(Add_Subt_result[4]), .Y(n1095) );
AO22XLTS U1028 ( .A0(n1410), .A1(Add_Subt_result[18]), .B0(
Add_Subt_result[10]), .B1(n1093), .Y(n1119) );
MX2X1TS U1029 ( .A(DMP[30]), .B(exp_oper_result[7]), .S0(n1070), .Y(
S_Oper_A_exp[7]) );
XOR2XLTS U1030 ( .A(FSM_exp_operation_A_S), .B(n1007), .Y(
DP_OP_42J1_122_8048_n13) );
CLKAND2X2TS U1031 ( .A(n664), .B(DmP[30]), .Y(n1007) );
MX2X1TS U1032 ( .A(DMP[25]), .B(exp_oper_result[2]), .S0(n1070), .Y(
S_Oper_A_exp[2]) );
XOR2XLTS U1033 ( .A(FSM_exp_operation_A_S), .B(n1013), .Y(
DP_OP_42J1_122_8048_n18) );
AO22XLTS U1034 ( .A0(LZA_output[2]), .A1(n1012), .B0(n665), .B1(DmP[25]),
.Y(n1013) );
MX2X1TS U1035 ( .A(DMP[28]), .B(exp_oper_result[5]), .S0(n1070), .Y(
S_Oper_A_exp[5]) );
XOR2XLTS U1036 ( .A(FSM_exp_operation_A_S), .B(n1009), .Y(
DP_OP_42J1_122_8048_n15) );
CLKAND2X2TS U1037 ( .A(n664), .B(DmP[28]), .Y(n1009) );
MX2X1TS U1038 ( .A(DMP[0]), .B(Sgf_normalized_result[2]), .S0(n692), .Y(
n1138) );
MX2X1TS U1039 ( .A(DMP[6]), .B(Sgf_normalized_result[8]), .S0(n692), .Y(
n1192) );
OAI21XLTS U1040 ( .A0(intDX[3]), .A1(n1468), .B0(intDX[2]), .Y(n729) );
NAND2BXLTS U1041 ( .AN(intDY[9]), .B(intDX[9]), .Y(n741) );
NAND3XLTS U1042 ( .A(n1474), .B(n739), .C(intDX[8]), .Y(n740) );
NOR2XLTS U1043 ( .A(intDY[10]), .B(n737), .Y(n738) );
OAI211XLTS U1044 ( .A0(intDX[8]), .A1(n1474), .B0(n739), .C0(n742), .Y(n751)
);
NOR2BX1TS U1045 ( .AN(n1173), .B(n693), .Y(n694) );
NOR2BX1TS U1046 ( .AN(n1160), .B(n705), .Y(n706) );
OAI21XLTS U1047 ( .A0(n1019), .A1(n1318), .B0(n918), .Y(n950) );
NOR2XLTS U1048 ( .A(r_mode[1]), .B(sign_final_result), .Y(n947) );
AOI2BB2XLTS U1049 ( .B0(n1322), .B1(n1255), .A0N(n1242), .A1N(n1322), .Y(
n1252) );
NAND2BXLTS U1050 ( .AN(Add_Subt_result[6]), .B(n1522), .Y(n1079) );
AOI31XLTS U1051 ( .A0(n1094), .A1(Add_Subt_result[0]), .A2(n1527), .B0(n1119), .Y(n1096) );
MX2X1TS U1052 ( .A(DMP[23]), .B(exp_oper_result[0]), .S0(n1070), .Y(
S_Oper_A_exp[0]) );
XOR2XLTS U1053 ( .A(FSM_exp_operation_A_S), .B(n1018), .Y(
DP_OP_42J1_122_8048_n20) );
AO21XLTS U1054 ( .A0(DmP[23]), .A1(n1459), .B0(n1017), .Y(n1018) );
MX2X1TS U1055 ( .A(DMP[26]), .B(exp_oper_result[3]), .S0(n1070), .Y(
S_Oper_A_exp[3]) );
XOR2XLTS U1056 ( .A(FSM_exp_operation_A_S), .B(n1011), .Y(
DP_OP_42J1_122_8048_n17) );
AO22XLTS U1057 ( .A0(LZA_output[3]), .A1(n1012), .B0(n664), .B1(DmP[26]),
.Y(n1011) );
MX2X1TS U1058 ( .A(DMP[29]), .B(exp_oper_result[6]), .S0(n1070), .Y(
S_Oper_A_exp[6]) );
XOR2XLTS U1059 ( .A(FSM_exp_operation_A_S), .B(n1008), .Y(
DP_OP_42J1_122_8048_n14) );
CLKAND2X2TS U1060 ( .A(n665), .B(DmP[29]), .Y(n1008) );
CLKAND2X2TS U1061 ( .A(Sgf_normalized_result[0]), .B(n1127), .Y(n1039) );
XOR2XLTS U1062 ( .A(n682), .B(n689), .Y(n1128) );
MX2X1TS U1063 ( .A(DMP[2]), .B(Sgf_normalized_result[4]), .S0(n692), .Y(
n1157) );
MX2X1TS U1064 ( .A(DMP[7]), .B(Sgf_normalized_result[9]), .S0(n692), .Y(
n1201) );
MX2X1TS U1065 ( .A(DMP[10]), .B(Sgf_normalized_result[12]), .S0(n704), .Y(
n1226) );
NOR2XLTS U1066 ( .A(n1462), .B(n702), .Y(n677) );
AFHCINX2TS U1067 ( .CIN(n1150), .B(n1151), .A(n1152), .S(n1154), .CO(n1143)
);
MX2X1TS U1068 ( .A(DMP[19]), .B(Sgf_normalized_result[21]), .S0(n704), .Y(
n1152) );
OAI22X2TS U1069 ( .A0(n1162), .A1(n706), .B0(n1160), .B1(n1159), .Y(n1150)
);
MX2X1TS U1070 ( .A(DMP[22]), .B(Sgf_normalized_result[24]), .S0(n1070), .Y(
n1124) );
NOR3BXLTS U1071 ( .AN(n862), .B(FS_Module_state_reg[2]), .C(
FS_Module_state_reg[1]), .Y(n1028) );
CLKAND2X2TS U1072 ( .A(n953), .B(n1028), .Y(n1020) );
NOR2XLTS U1073 ( .A(n1475), .B(intDX[11]), .Y(n737) );
OAI211XLTS U1074 ( .A0(n1468), .A1(intDX[3]), .B0(n728), .C0(n727), .Y(n731)
);
AOI2BB2XLTS U1075 ( .B0(intDX[3]), .B1(n1468), .A0N(intDY[2]), .A1N(n729),
.Y(n730) );
NAND2BXLTS U1076 ( .AN(intDX[2]), .B(intDY[2]), .Y(n727) );
OAI21XLTS U1077 ( .A0(intDX[13]), .A1(n1469), .B0(intDX[12]), .Y(n736) );
NAND2BXLTS U1078 ( .AN(intDX[9]), .B(intDY[9]), .Y(n739) );
AOI211XLTS U1079 ( .A0(n749), .A1(n748), .B0(n747), .C0(n746), .Y(n750) );
NAND2BXLTS U1080 ( .AN(intDX[21]), .B(intDY[21]), .Y(n754) );
NAND2BXLTS U1081 ( .AN(intDY[27]), .B(intDX[27]), .Y(n716) );
NAND3XLTS U1082 ( .A(n1496), .B(n714), .C(intDX[26]), .Y(n715) );
AO22XLTS U1083 ( .A0(n1305), .A1(Add_Subt_result[19]), .B0(DmP[4]), .B1(
n1294), .Y(n1295) );
AO22XLTS U1084 ( .A0(n1305), .A1(Add_Subt_result[20]), .B0(DmP[3]), .B1(
n1318), .Y(n1300) );
AO22XLTS U1085 ( .A0(n1305), .A1(Add_Subt_result[18]), .B0(DmP[5]), .B1(
n1294), .Y(n1288) );
AO22XLTS U1086 ( .A0(n1305), .A1(Add_Subt_result[17]), .B0(DmP[6]), .B1(
n1519), .Y(n1282) );
AO22XLTS U1087 ( .A0(n1305), .A1(Add_Subt_result[16]), .B0(n1294), .B1(
DmP[7]), .Y(n1277) );
AO22XLTS U1088 ( .A0(n1305), .A1(Add_Subt_result[15]), .B0(DmP[8]), .B1(
n1294), .Y(n1272) );
AO22XLTS U1089 ( .A0(n1305), .A1(Add_Subt_result[10]), .B0(DmP[13]), .B1(
n1294), .Y(n1250) );
AO22XLTS U1090 ( .A0(n1305), .A1(Add_Subt_result[9]), .B0(n1519), .B1(
DmP[14]), .Y(n875) );
AO22XLTS U1091 ( .A0(n1267), .A1(Add_Subt_result[8]), .B0(DmP[15]), .B1(
n1519), .Y(n870) );
AO22XLTS U1092 ( .A0(n1267), .A1(Add_Subt_result[7]), .B0(n1294), .B1(
DmP[16]), .Y(n869) );
AO22XLTS U1093 ( .A0(n1267), .A1(Add_Subt_result[6]), .B0(DmP[17]), .B1(
n1519), .Y(n868) );
INVX2TS U1094 ( .A(n1128), .Y(n690) );
OR2X1TS U1095 ( .A(Sgf_normalized_result[2]), .B(n1070), .Y(n687) );
NOR2BX1TS U1096 ( .AN(n1195), .B(n697), .Y(n698) );
NOR2BX1TS U1097 ( .AN(n1178), .B(n700), .Y(n701) );
NOR2XLTS U1098 ( .A(n1504), .B(n702), .Y(n671) );
NOR2XLTS U1099 ( .A(n1502), .B(n702), .Y(n670) );
INVX2TS U1100 ( .A(FSM_selector_C), .Y(n1294) );
NOR2XLTS U1101 ( .A(n938), .B(n915), .Y(n922) );
NAND3XLTS U1102 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[2]),
.C(n1029), .Y(n864) );
CLKAND2X2TS U1103 ( .A(n917), .B(n916), .Y(n928) );
AO22XLTS U1104 ( .A0(n1305), .A1(Add_Subt_result[4]), .B0(n1519), .B1(
DmP[19]), .Y(n801) );
AO22XLTS U1105 ( .A0(n1267), .A1(Add_Subt_result[5]), .B0(n1519), .B1(
DmP[18]), .Y(n871) );
AO22XLTS U1106 ( .A0(n1305), .A1(Add_Subt_result[21]), .B0(DmP[2]), .B1(
n1318), .Y(n1306) );
NAND3XLTS U1107 ( .A(n1410), .B(Add_Subt_result[16]), .C(n1530), .Y(n1411)
);
AFHCINX2TS U1108 ( .CIN(n1145), .B(n1146), .A(n1147), .S(n1149), .CO(n1155)
);
MX2X1TS U1109 ( .A(DMP[1]), .B(Sgf_normalized_result[3]), .S0(n692), .Y(
n1147) );
XOR2XLTS U1110 ( .A(n682), .B(n686), .Y(n1146) );
XOR2XLTS U1111 ( .A(n682), .B(n691), .Y(n1173) );
MX2X1TS U1112 ( .A(DMP[4]), .B(Sgf_normalized_result[6]), .S0(n692), .Y(
n1172) );
MX2X1TS U1113 ( .A(DMP[3]), .B(Sgf_normalized_result[5]), .S0(n692), .Y(
n1166) );
XOR2XLTS U1114 ( .A(n682), .B(n684), .Y(n1165) );
AFHCINX2TS U1115 ( .CIN(n1182), .B(n1183), .A(n1184), .S(n1185), .CO(n1190)
);
MX2X1TS U1116 ( .A(DMP[5]), .B(Sgf_normalized_result[7]), .S0(n692), .Y(
n1184) );
XOR2XLTS U1117 ( .A(n682), .B(n683), .Y(n1183) );
OAI22X1TS U1118 ( .A0(n1175), .A1(n694), .B0(n1173), .B1(n1172), .Y(n1182)
);
MX2X1TS U1119 ( .A(DMP[8]), .B(Sgf_normalized_result[10]), .S0(n692), .Y(
n1210) );
NOR2XLTS U1120 ( .A(n1460), .B(n702), .Y(n679) );
AFHCINX2TS U1121 ( .CIN(n1216), .B(n1217), .A(n1218), .S(n1219), .CO(n1224)
);
MX2X1TS U1122 ( .A(DMP[9]), .B(Sgf_normalized_result[11]), .S0(n692), .Y(
n1218) );
NOR2XLTS U1123 ( .A(n1461), .B(n702), .Y(n678) );
MX2X1TS U1124 ( .A(DMP[12]), .B(Sgf_normalized_result[14]), .S0(n704), .Y(
n1214) );
MX2X1TS U1125 ( .A(DMP[14]), .B(Sgf_normalized_result[16]), .S0(n704), .Y(
n1194) );
AFHCINX2TS U1126 ( .CIN(n1203), .B(n1204), .A(n1205), .S(n1207), .CO(n1197)
);
MX2X1TS U1127 ( .A(DMP[13]), .B(Sgf_normalized_result[15]), .S0(n704), .Y(
n1205) );
NOR2XLTS U1128 ( .A(n1464), .B(n707), .Y(n674) );
MX2X1TS U1129 ( .A(DMP[16]), .B(Sgf_normalized_result[18]), .S0(n704), .Y(
n1177) );
AFHCINX2TS U1130 ( .CIN(n1186), .B(n1187), .A(n1188), .S(n1189), .CO(n1180)
);
MX2X1TS U1131 ( .A(DMP[15]), .B(Sgf_normalized_result[17]), .S0(n704), .Y(
n1188) );
OAI22X1TS U1132 ( .A0(n1197), .A1(n698), .B0(n1195), .B1(n1194), .Y(n1186)
);
MX2X1TS U1133 ( .A(DMP[18]), .B(Sgf_normalized_result[20]), .S0(n704), .Y(
n1159) );
AFHCINX2TS U1134 ( .CIN(n1168), .B(n1169), .A(n1170), .S(n1171), .CO(n1162)
);
MX2X1TS U1135 ( .A(DMP[17]), .B(Sgf_normalized_result[19]), .S0(n704), .Y(
n1170) );
OAI22X1TS U1136 ( .A0(n1180), .A1(n701), .B0(n1178), .B1(n1177), .Y(n1168)
);
MX2X1TS U1137 ( .A(DMP[20]), .B(Sgf_normalized_result[22]), .S0(
FSM_selector_D), .Y(n1140) );
MX2X1TS U1138 ( .A(DMP[21]), .B(Sgf_normalized_result[23]), .S0(
FSM_selector_D), .Y(n1134) );
OAI22X1TS U1139 ( .A0(n1143), .A1(n710), .B0(n1141), .B1(n1140), .Y(n1132)
);
XOR2XLTS U1140 ( .A(n1038), .B(n668), .Y(n1035) );
NAND3XLTS U1141 ( .A(n971), .B(n949), .C(n974), .Y(n1030) );
CLKAND2X2TS U1142 ( .A(n924), .B(n923), .Y(n930) );
MX2X1TS U1143 ( .A(Data_Y[31]), .B(intDY[31]), .S0(n1063), .Y(n87) );
AOI2BB1XLTS U1144 ( .A0N(n866), .A1N(n865), .B0(n1023), .Y(n214) );
MX2X1TS U1145 ( .A(add_subt), .B(intAS), .S0(n1063), .Y(n181) );
AO22XLTS U1146 ( .A0(n1405), .A1(final_result_ieee[0]), .B0(
Sgf_normalized_result[2]), .B1(n1006), .Y(n1510) );
AO22XLTS U1147 ( .A0(n826), .A1(final_result_ieee[1]), .B0(
Sgf_normalized_result[3]), .B1(n1006), .Y(n1511) );
AO22XLTS U1148 ( .A0(n826), .A1(final_result_ieee[2]), .B0(
Sgf_normalized_result[4]), .B1(n1006), .Y(n1512) );
AO22XLTS U1149 ( .A0(n826), .A1(final_result_ieee[3]), .B0(
Sgf_normalized_result[5]), .B1(n1006), .Y(n1513) );
AO22XLTS U1150 ( .A0(n826), .A1(final_result_ieee[4]), .B0(
Sgf_normalized_result[6]), .B1(n1006), .Y(n1514) );
AO22XLTS U1151 ( .A0(n826), .A1(final_result_ieee[5]), .B0(
Sgf_normalized_result[7]), .B1(n1006), .Y(n1515) );
AO22XLTS U1152 ( .A0(n826), .A1(final_result_ieee[6]), .B0(
Sgf_normalized_result[8]), .B1(n1006), .Y(n1516) );
AO22XLTS U1153 ( .A0(n826), .A1(final_result_ieee[7]), .B0(
Sgf_normalized_result[9]), .B1(n1006), .Y(n1517) );
MX2X1TS U1154 ( .A(Data_X[31]), .B(intDX[31]), .S0(n1063), .Y(n182) );
OAI211XLTS U1155 ( .A0(n953), .A1(n978), .B0(n952), .C0(n951), .Y(n242) );
OR2X1TS U1156 ( .A(n1020), .B(n1127), .Y(n245) );
OAI211XLTS U1157 ( .A0(n930), .A1(n1371), .B0(n925), .C0(n1368), .Y(n12) );
OAI211XLTS U1158 ( .A0(n928), .A1(n1371), .B0(n920), .C0(n1368), .Y(n14) );
OAI21XLTS U1159 ( .A0(n928), .A1(n1373), .B0(n927), .Y(n15) );
NAND3XLTS U1160 ( .A(n1354), .B(n1353), .C(n1368), .Y(n17) );
NAND3XLTS U1161 ( .A(n1069), .B(n1068), .C(n1067), .Y(n19) );
AOI2BB2XLTS U1162 ( .B0(n659), .B1(Sgf_normalized_result[2]), .A0N(n1373),
.A1N(n1352), .Y(n1069) );
NAND3XLTS U1163 ( .A(n1358), .B(n1357), .C(n1368), .Y(n21) );
NAND3XLTS U1164 ( .A(n1062), .B(n1061), .C(n1067), .Y(n23) );
AOI2BB2XLTS U1165 ( .B0(n661), .B1(Sgf_normalized_result[3]), .A0N(n655),
.A1N(n1355), .Y(n1062) );
NAND3XLTS U1166 ( .A(n1362), .B(n1361), .C(n1368), .Y(n25) );
NAND3XLTS U1167 ( .A(n1060), .B(n1059), .C(n1067), .Y(n27) );
AOI2BB2XLTS U1168 ( .B0(n660), .B1(Sgf_normalized_result[4]), .A0N(n655),
.A1N(n1360), .Y(n1060) );
NAND3XLTS U1169 ( .A(n1365), .B(n1364), .C(n1368), .Y(n29) );
NAND3XLTS U1170 ( .A(n1058), .B(n1057), .C(n1067), .Y(n31) );
AOI2BB2XLTS U1171 ( .B0(n659), .B1(Sgf_normalized_result[5]), .A0N(n1373),
.A1N(n1363), .Y(n1058) );
NAND3XLTS U1172 ( .A(n1370), .B(n1369), .C(n1368), .Y(n33) );
NAND3XLTS U1173 ( .A(n1056), .B(n1055), .C(n1067), .Y(n35) );
AOI2BB2XLTS U1174 ( .B0(n661), .B1(Sgf_normalized_result[6]), .A0N(n1373),
.A1N(n1367), .Y(n1056) );
OAI211XLTS U1175 ( .A0(n1371), .A1(n1051), .B0(n956), .C0(n955), .Y(n37) );
NAND3XLTS U1176 ( .A(n1054), .B(n1053), .C(n1067), .Y(n39) );
AOI2BB2XLTS U1177 ( .B0(n660), .B1(Sgf_normalized_result[7]), .A0N(n655),
.A1N(n1051), .Y(n1054) );
OAI211XLTS U1178 ( .A0(n1048), .A1(n1373), .B0(n946), .C0(n945), .Y(n41) );
AO21XLTS U1179 ( .A0(n1050), .A1(n654), .B0(n1049), .Y(n43) );
OAI211XLTS U1180 ( .A0(n1048), .A1(n1371), .B0(n1047), .C0(n1046), .Y(n1049)
);
OAI211XLTS U1181 ( .A0(n1043), .A1(n1373), .B0(n943), .C0(n942), .Y(n45) );
AO21XLTS U1182 ( .A0(n1045), .A1(n654), .B0(n1044), .Y(n47) );
NAND4XLTS U1183 ( .A(n1378), .B(n1377), .C(n1400), .D(n1376), .Y(n49) );
NAND4XLTS U1184 ( .A(n1383), .B(n1382), .C(n1400), .D(n1381), .Y(n51) );
NAND4XLTS U1185 ( .A(n1386), .B(n1385), .C(n1400), .D(n1384), .Y(n53) );
NAND4XLTS U1186 ( .A(n1389), .B(n1388), .C(n1400), .D(n1387), .Y(n55) );
NAND4XLTS U1187 ( .A(n1392), .B(n1391), .C(n1400), .D(n1390), .Y(n57) );
NAND4XLTS U1188 ( .A(n1402), .B(n1401), .C(n1400), .D(n1399), .Y(n59) );
OAI21XLTS U1189 ( .A0(n803), .A1(n1236), .B0(n802), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[21]) );
OAI211XLTS U1190 ( .A0(n939), .A1(n1240), .B0(n1238), .C0(n934), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[23]) );
OAI21XLTS U1191 ( .A0(n1247), .A1(n1236), .B0(n1238), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[24]) );
OAI211XLTS U1192 ( .A0(n965), .A1(n1245), .B0(n959), .C0(n958), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[19]) );
OAI211XLTS U1193 ( .A0(n965), .A1(n931), .B0(n874), .C0(n873), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[17]) );
OAI211XLTS U1194 ( .A0(n965), .A1(n1243), .B0(n964), .C0(n963), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[18]) );
MXI2XLTS U1195 ( .A(n1459), .B(add_overflow_flag), .S0(n1071), .Y(n71) );
MX2X1TS U1196 ( .A(n1085), .B(LZA_output[4]), .S0(n1418), .Y(n72) );
NAND4XLTS U1197 ( .A(n1115), .B(n1095), .C(n1084), .D(n1083), .Y(n1085) );
OAI211XLTS U1198 ( .A0(Add_Subt_result[25]), .A1(n1413), .B0(n1412), .C0(
n1411), .Y(n1414) );
MXI2XLTS U1199 ( .A(n1121), .B(n1467), .S0(n1418), .Y(n74) );
OAI21XLTS U1200 ( .A0(n1416), .A1(n1105), .B0(n1420), .Y(n1106) );
OAI211XLTS U1201 ( .A0(n1104), .A1(n1103), .B0(n1102), .C0(n1101), .Y(n1105)
);
AO21XLTS U1202 ( .A0(LZA_output[3]), .A1(n1418), .B0(n1092), .Y(n76) );
AOI211XLTS U1203 ( .A0(n1089), .A1(n1088), .B0(n1087), .C0(n1409), .Y(n1090)
);
MX2X1TS U1204 ( .A(exp_oper_result[7]), .B(Exp_Operation_Module_Data_S[7]),
.S0(n1232), .Y(n78) );
MX2X1TS U1205 ( .A(Exp_Operation_Module_Data_S[0]), .B(exp_oper_result[0]),
.S0(n1122), .Y(n79) );
MX2X1TS U1206 ( .A(Exp_Operation_Module_Data_S[1]), .B(exp_oper_result[1]),
.S0(n1122), .Y(n80) );
MX2X1TS U1207 ( .A(Exp_Operation_Module_Data_S[2]), .B(exp_oper_result[2]),
.S0(n1122), .Y(n81) );
MX2X1TS U1208 ( .A(exp_oper_result[3]), .B(Exp_Operation_Module_Data_S[3]),
.S0(n1232), .Y(n82) );
MX2X1TS U1209 ( .A(exp_oper_result[4]), .B(Exp_Operation_Module_Data_S[4]),
.S0(n1232), .Y(n83) );
MX2X1TS U1210 ( .A(exp_oper_result[5]), .B(Exp_Operation_Module_Data_S[5]),
.S0(n1232), .Y(n84) );
MX2X1TS U1211 ( .A(exp_oper_result[6]), .B(Exp_Operation_Module_Data_S[6]),
.S0(n1232), .Y(n85) );
AOI2BB2XLTS U1212 ( .B0(intDX[31]), .B1(n974), .A0N(n971), .A1N(n970), .Y(
n972) );
AO22XLTS U1213 ( .A0(n1432), .A1(Data_Y[0]), .B0(n1427), .B1(intDY[0]), .Y(
n90) );
AO22XLTS U1214 ( .A0(n1428), .A1(Data_Y[1]), .B0(n1423), .B1(intDY[1]), .Y(
n93) );
AO22XLTS U1215 ( .A0(n1428), .A1(Data_Y[2]), .B0(n1423), .B1(intDY[2]), .Y(
n96) );
AO22XLTS U1216 ( .A0(n1428), .A1(Data_Y[3]), .B0(n1424), .B1(intDY[3]), .Y(
n99) );
AO22XLTS U1217 ( .A0(n1428), .A1(Data_Y[4]), .B0(n1424), .B1(intDY[4]), .Y(
n102) );
AO22XLTS U1218 ( .A0(n1428), .A1(Data_Y[5]), .B0(n1424), .B1(intDY[5]), .Y(
n105) );
AO22XLTS U1219 ( .A0(n1425), .A1(Data_Y[6]), .B0(n1424), .B1(intDY[6]), .Y(
n108) );
AO22XLTS U1220 ( .A0(n1425), .A1(Data_Y[7]), .B0(n1424), .B1(intDY[7]), .Y(
n111) );
AO22XLTS U1221 ( .A0(n1425), .A1(Data_Y[8]), .B0(n1424), .B1(intDY[8]), .Y(
n114) );
AO22XLTS U1222 ( .A0(n1425), .A1(Data_Y[9]), .B0(n1424), .B1(intDY[9]), .Y(
n117) );
AO22XLTS U1223 ( .A0(n1425), .A1(Data_Y[10]), .B0(n1424), .B1(intDY[10]),
.Y(n120) );
AO22XLTS U1224 ( .A0(n1425), .A1(Data_Y[11]), .B0(n1424), .B1(intDY[11]),
.Y(n123) );
AO22XLTS U1225 ( .A0(n1425), .A1(Data_Y[12]), .B0(n1424), .B1(intDY[12]),
.Y(n126) );
AO22XLTS U1226 ( .A0(n1425), .A1(Data_Y[13]), .B0(n1423), .B1(intDY[13]),
.Y(n129) );
AO22XLTS U1227 ( .A0(n1425), .A1(Data_Y[14]), .B0(n1423), .B1(intDY[14]),
.Y(n132) );
AO22XLTS U1228 ( .A0(n1425), .A1(Data_Y[15]), .B0(n1423), .B1(intDY[15]),
.Y(n135) );
AO22XLTS U1229 ( .A0(n1426), .A1(Data_Y[16]), .B0(n1423), .B1(intDY[16]),
.Y(n138) );
OAI21XLTS U1230 ( .A0(n1494), .A1(n969), .B0(n968), .Y(n139) );
AO22XLTS U1231 ( .A0(n1426), .A1(Data_Y[18]), .B0(n1423), .B1(intDY[18]),
.Y(n144) );
AO22XLTS U1232 ( .A0(n1426), .A1(Data_Y[19]), .B0(n1423), .B1(intDY[19]),
.Y(n147) );
AO22XLTS U1233 ( .A0(n1426), .A1(Data_Y[20]), .B0(n1423), .B1(intDY[20]),
.Y(n150) );
AO22XLTS U1234 ( .A0(n1426), .A1(Data_Y[21]), .B0(n1423), .B1(intDY[21]),
.Y(n153) );
AO22XLTS U1235 ( .A0(n1426), .A1(Data_Y[22]), .B0(n1422), .B1(intDY[22]),
.Y(n156) );
AO22XLTS U1236 ( .A0(n1426), .A1(Data_Y[23]), .B0(n1427), .B1(intDY[23]),
.Y(n159) );
AO22XLTS U1237 ( .A0(n1426), .A1(Data_Y[25]), .B0(n1427), .B1(intDY[25]),
.Y(n165) );
AO22XLTS U1238 ( .A0(n1426), .A1(Data_Y[26]), .B0(n1427), .B1(intDY[26]),
.Y(n168) );
AO22XLTS U1239 ( .A0(n1426), .A1(Data_Y[27]), .B0(n1427), .B1(intDY[27]),
.Y(n171) );
AO22XLTS U1240 ( .A0(n1432), .A1(Data_Y[28]), .B0(n1427), .B1(intDY[28]),
.Y(n174) );
AO22XLTS U1241 ( .A0(n1432), .A1(Data_Y[29]), .B0(n1427), .B1(intDY[29]),
.Y(n177) );
AO22XLTS U1242 ( .A0(n1432), .A1(Data_Y[30]), .B0(n1427), .B1(intDY[30]),
.Y(n180) );
MX2X1TS U1243 ( .A(Data_X[0]), .B(intDX[0]), .S0(n1063), .Y(n183) );
MX2X1TS U1244 ( .A(Data_X[1]), .B(intDX[1]), .S0(n1063), .Y(n184) );
MX2X1TS U1245 ( .A(Data_X[2]), .B(intDX[2]), .S0(n1063), .Y(n185) );
MX2X1TS U1246 ( .A(Data_X[3]), .B(intDX[3]), .S0(n1427), .Y(n186) );
MX2X1TS U1247 ( .A(Data_X[4]), .B(intDX[4]), .S0(n1063), .Y(n187) );
MX2X1TS U1248 ( .A(Data_X[5]), .B(intDX[5]), .S0(n1063), .Y(n188) );
MX2X1TS U1249 ( .A(Data_X[6]), .B(intDX[6]), .S0(n1427), .Y(n189) );
AO22XLTS U1250 ( .A0(n1432), .A1(Data_X[24]), .B0(n1422), .B1(intDX[24]),
.Y(n207) );
MX2X1TS U1251 ( .A(Add_Subt_result[0]), .B(n1040), .S0(n1148), .Y(n216) );
MX2X1TS U1252 ( .A(Add_Subt_result[1]), .B(n1131), .S0(n1148), .Y(n217) );
XOR2XLTS U1253 ( .A(n1130), .B(n1129), .Y(n1131) );
XOR2XLTS U1254 ( .A(n1128), .B(n666), .Y(n1129) );
MX2X1TS U1255 ( .A(Add_Subt_result[2]), .B(n1139), .S0(n1148), .Y(n218) );
MX2X1TS U1256 ( .A(Add_Subt_result[3]), .B(n1149), .S0(n1148), .Y(n219) );
MX2X1TS U1257 ( .A(Add_Subt_result[4]), .B(n1158), .S0(n1206), .Y(n220) );
MX2X1TS U1258 ( .A(Add_Subt_result[5]), .B(n1167), .S0(n1206), .Y(n221) );
MX2X1TS U1259 ( .A(Add_Subt_result[6]), .B(n1176), .S0(n1206), .Y(n222) );
MX2X1TS U1260 ( .A(Add_Subt_result[7]), .B(n1185), .S0(n1206), .Y(n223) );
MX2X1TS U1261 ( .A(Add_Subt_result[8]), .B(n1193), .S0(n1227), .Y(n224) );
MX2X1TS U1262 ( .A(Add_Subt_result[9]), .B(n1202), .S0(n1227), .Y(n225) );
MX2X1TS U1263 ( .A(Add_Subt_result[10]), .B(n1211), .S0(n1227), .Y(n226) );
MX2X1TS U1264 ( .A(Add_Subt_result[11]), .B(n1219), .S0(n1227), .Y(n227) );
MX2X1TS U1265 ( .A(Add_Subt_result[12]), .B(n1228), .S0(n1227), .Y(n228) );
MX2X1TS U1266 ( .A(Add_Subt_result[13]), .B(n1223), .S0(n1227), .Y(n229) );
MX2X1TS U1267 ( .A(Add_Subt_result[14]), .B(n1215), .S0(n1227), .Y(n230) );
MX2X1TS U1268 ( .A(Add_Subt_result[15]), .B(n1207), .S0(n1206), .Y(n231) );
MX2X1TS U1269 ( .A(Add_Subt_result[16]), .B(n1198), .S0(n1227), .Y(n232) );
MX2X1TS U1270 ( .A(Add_Subt_result[17]), .B(n1189), .S0(n1206), .Y(n233) );
MX2X1TS U1271 ( .A(Add_Subt_result[18]), .B(n1181), .S0(n1206), .Y(n234) );
MX2X1TS U1272 ( .A(Add_Subt_result[19]), .B(n1171), .S0(n1206), .Y(n235) );
MX2X1TS U1273 ( .A(Add_Subt_result[20]), .B(n1163), .S0(n1206), .Y(n236) );
MX2X1TS U1274 ( .A(Add_Subt_result[21]), .B(n1154), .S0(n1206), .Y(n237) );
MX2X1TS U1275 ( .A(Add_Subt_result[22]), .B(n1144), .S0(n1148), .Y(n238) );
MX2X1TS U1276 ( .A(Add_Subt_result[23]), .B(n1135), .S0(n1148), .Y(n239) );
MX2X1TS U1277 ( .A(Add_Subt_result[24]), .B(n1126), .S0(n1148), .Y(n240) );
MX2X1TS U1278 ( .A(add_overflow_flag), .B(n712), .S0(n1148), .Y(n667) );
XOR2XLTS U1279 ( .A(n711), .B(n682), .Y(n712) );
NAND4XLTS U1280 ( .A(n1032), .B(n1122), .C(n1031), .D(n1030), .Y(n246) );
NAND3XLTS U1281 ( .A(n1063), .B(n1022), .C(n1021), .Y(n247) );
OAI21XLTS U1282 ( .A0(n930), .A1(n1373), .B0(n929), .Y(n248) );
OAI21XLTS U1283 ( .A0(n1245), .A1(n1236), .B0(n935), .Y(n936) );
INVX2TS U1284 ( .A(n1371), .Y(n652) );
INVX2TS U1285 ( .A(n652), .Y(n653) );
INVX2TS U1286 ( .A(n1373), .Y(n654) );
INVX2TS U1287 ( .A(n654), .Y(n655) );
INVX2TS U1288 ( .A(n931), .Y(n657) );
INVX2TS U1289 ( .A(n1372), .Y(n658) );
CLKBUFX2TS U1290 ( .A(n1374), .Y(n1395) );
INVX2TS U1291 ( .A(n1395), .Y(n659) );
INVX2TS U1292 ( .A(n1395), .Y(n660) );
INVX2TS U1293 ( .A(n1395), .Y(n661) );
INVX2TS U1294 ( .A(n1245), .Y(n662) );
INVX2TS U1295 ( .A(n1245), .Y(n663) );
INVX2TS U1296 ( .A(n1014), .Y(n664) );
INVX2TS U1297 ( .A(n1014), .Y(n665) );
NOR2BX2TS U1298 ( .AN(n949), .B(n1127), .Y(n682) );
OAI21XLTS U1299 ( .A0(intDX[1]), .A1(n1470), .B0(intDX[0]), .Y(n726) );
OAI21XLTS U1300 ( .A0(intDX[15]), .A1(n1439), .B0(intDX[14]), .Y(n745) );
INVX2TS U1301 ( .A(n1172), .Y(n693) );
NOR2XLTS U1302 ( .A(n1524), .B(n702), .Y(n669) );
OAI31X1TS U1303 ( .A0(Add_Subt_result[12]), .A1(n1526), .A2(n1116), .B0(
n1115), .Y(n1117) );
AOI211XLTS U1304 ( .A0(n1029), .A1(n1024), .B0(n1028), .C0(n950), .Y(n863)
);
NOR4BXLTS U1305 ( .AN(n1030), .B(n1366), .C(n1227), .D(n950), .Y(n952) );
AOI211XLTS U1306 ( .A0(r_mode[0]), .A1(r_mode[1]), .B0(n948), .C0(n947), .Y(
n953) );
OAI211XLTS U1307 ( .A0(n1043), .A1(n1371), .B0(n1042), .C0(n1041), .Y(n1044)
);
AFHCINX2TS U1308 ( .CIN(n1164), .B(n1165), .A(n1166), .S(n1167), .CO(n1175)
);
INVX2TS U1309 ( .A(rst), .Y(n822) );
OAI211XLTS U1310 ( .A0(n1240), .A1(n965), .B0(n877), .C0(n876), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[16]) );
XNOR2X1TS U1311 ( .A(intDY[31]), .B(intAS), .Y(n973) );
XOR2X1TS U1312 ( .A(n973), .B(n1454), .Y(n949) );
CLKBUFX2TS U1313 ( .A(FSM_selector_D), .Y(n1127) );
BUFX3TS U1314 ( .A(n682), .Y(n1038) );
NOR2BX1TS U1315 ( .AN(Sgf_normalized_result[25]), .B(n1127), .Y(n668) );
CLKBUFX2TS U1316 ( .A(FSM_selector_D), .Y(n707) );
CLKBUFX2TS U1317 ( .A(FSM_selector_D), .Y(n702) );
XOR2X1TS U1318 ( .A(n1038), .B(n669), .Y(n1125) );
CLKBUFX2TS U1319 ( .A(FSM_selector_D), .Y(n1070) );
CLKBUFX2TS U1320 ( .A(FSM_selector_D), .Y(n704) );
CLKBUFX2TS U1321 ( .A(n682), .Y(n696) );
XOR2X1TS U1322 ( .A(n696), .B(n675), .Y(n1213) );
XOR2X1TS U1323 ( .A(n696), .B(n676), .Y(n1221) );
XOR2X1TS U1324 ( .A(n696), .B(n677), .Y(n1225) );
CLKBUFX2TS U1325 ( .A(FSM_selector_D), .Y(n692) );
XOR2X1TS U1326 ( .A(n696), .B(n679), .Y(n1209) );
NOR2BX1TS U1327 ( .AN(Sgf_normalized_result[9]), .B(n1127), .Y(n680) );
NOR2BX1TS U1328 ( .AN(Sgf_normalized_result[8]), .B(n1127), .Y(n681) );
XOR2X1TS U1329 ( .A(n696), .B(n681), .Y(n1191) );
NOR2BX1TS U1330 ( .AN(Sgf_normalized_result[7]), .B(n1127), .Y(n683) );
NOR2BX1TS U1331 ( .AN(Sgf_normalized_result[5]), .B(n707), .Y(n684) );
NOR2BX1TS U1332 ( .AN(Sgf_normalized_result[4]), .B(n707), .Y(n685) );
XOR2X1TS U1333 ( .A(n682), .B(n685), .Y(n1156) );
NOR2BX1TS U1334 ( .AN(Sgf_normalized_result[3]), .B(n1127), .Y(n686) );
XOR2X1TS U1335 ( .A(n682), .B(n687), .Y(n1137) );
NOR2BX1TS U1336 ( .AN(Sgf_normalized_result[0]), .B(n707), .Y(n688) );
XOR2X4TS U1337 ( .A(n1038), .B(n688), .Y(n1037) );
NOR2BX1TS U1338 ( .AN(Sgf_normalized_result[1]), .B(n707), .Y(n689) );
NOR2BX1TS U1339 ( .AN(Sgf_normalized_result[6]), .B(n1127), .Y(n691) );
XOR2X1TS U1340 ( .A(n1038), .B(n703), .Y(n1160) );
INVX2TS U1341 ( .A(n1153), .Y(n1148) );
NOR2XLTS U1342 ( .A(intDY[24]), .B(n772), .Y(n713) );
AOI22X1TS U1343 ( .A0(intDX[24]), .A1(n713), .B0(intDX[25]), .B1(n1499), .Y(
n717) );
NOR3XLTS U1344 ( .A(n1501), .B(intDY[28]), .C(n718), .Y(n719) );
AOI221XLTS U1345 ( .A0(intDX[30]), .A1(n1449), .B0(intDX[29]), .B1(n1498),
.C0(n719), .Y(n721) );
OA22X1TS U1346 ( .A0(n1472), .A1(intDX[14]), .B0(n1439), .B1(intDX[15]), .Y(
n749) );
OAI2BB1X1TS U1347 ( .A0N(n1448), .A1N(intDY[5]), .B0(intDX[4]), .Y(n724) );
OAI22X1TS U1348 ( .A0(intDY[4]), .A1(n724), .B0(n1448), .B1(intDY[5]), .Y(
n735) );
OAI2BB1X1TS U1349 ( .A0N(n1447), .A1N(intDY[7]), .B0(intDX[6]), .Y(n725) );
OAI22X1TS U1350 ( .A0(intDY[6]), .A1(n725), .B0(n1447), .B1(intDY[7]), .Y(
n734) );
OAI2BB2XLTS U1351 ( .B0(intDY[0]), .B1(n726), .A0N(intDX[1]), .A1N(n1470),
.Y(n728) );
AOI222XLTS U1352 ( .A0(intDY[4]), .A1(n1508), .B0(n731), .B1(n730), .C0(
intDY[5]), .C1(n1448), .Y(n733) );
AOI22X1TS U1353 ( .A0(intDY[7]), .A1(n1447), .B0(intDY[6]), .B1(n1507), .Y(
n732) );
OAI32X1TS U1354 ( .A0(n735), .A1(n734), .A2(n733), .B0(n732), .B1(n734), .Y(
n752) );
AOI21X1TS U1355 ( .A0(intDY[10]), .A1(n1506), .B0(n737), .Y(n742) );
OAI2BB2XLTS U1356 ( .B0(intDY[12]), .B1(n736), .A0N(intDX[13]), .A1N(n1469),
.Y(n748) );
AOI22X1TS U1357 ( .A0(intDX[10]), .A1(n738), .B0(intDX[11]), .B1(n1475), .Y(
n744) );
AOI21X1TS U1358 ( .A0(n741), .A1(n740), .B0(n753), .Y(n743) );
OAI2BB2XLTS U1359 ( .B0(n744), .B1(n753), .A0N(n743), .A1N(n742), .Y(n747)
);
OAI2BB2XLTS U1360 ( .B0(intDY[14]), .B1(n745), .A0N(intDX[15]), .A1N(n1439),
.Y(n746) );
OAI31X1TS U1361 ( .A0(n753), .A1(n752), .A2(n751), .B0(n750), .Y(n756) );
OA22X1TS U1362 ( .A0(n1473), .A1(intDX[22]), .B0(n1438), .B1(intDX[23]), .Y(
n769) );
AOI211XLTS U1363 ( .A0(intDY[16]), .A1(n1509), .B0(n763), .C0(n764), .Y(n755) );
OAI21XLTS U1364 ( .A0(intDX[21]), .A1(n1495), .B0(intDX[20]), .Y(n757) );
OAI2BB2XLTS U1365 ( .B0(intDY[20]), .B1(n757), .A0N(intDX[21]), .A1N(n1495),
.Y(n768) );
NOR2XLTS U1366 ( .A(intDY[16]), .B(n758), .Y(n759) );
AOI22X1TS U1367 ( .A0(intDX[16]), .A1(n759), .B0(intDX[17]), .B1(n1518), .Y(
n762) );
AOI32X1TS U1368 ( .A0(n760), .A1(n1450), .A2(intDX[18]), .B0(intDX[19]),
.B1(n1500), .Y(n761) );
OAI32X1TS U1369 ( .A0(n764), .A1(n763), .A2(n762), .B0(n761), .B1(n763), .Y(
n767) );
OAI21XLTS U1370 ( .A0(intDX[23]), .A1(n1438), .B0(intDX[22]), .Y(n765) );
OAI2BB2XLTS U1371 ( .B0(intDY[22]), .B1(n765), .A0N(intDX[23]), .A1N(n1438),
.Y(n766) );
NAND4BBX1TS U1372 ( .AN(n773), .BN(n772), .C(n771), .D(n770), .Y(n774) );
AOI32X1TS U1373 ( .A0(n777), .A1(n776), .A2(n775), .B0(n774), .B1(n777), .Y(
n778) );
NOR2BX1TS U1374 ( .AN(n1024), .B(FS_Module_state_reg[3]), .Y(n979) );
INVX2TS U1375 ( .A(n974), .Y(n993) );
CLKBUFX2TS U1376 ( .A(n1000), .Y(n970) );
CLKBUFX2TS U1377 ( .A(n970), .Y(n992) );
INVX2TS U1378 ( .A(n974), .Y(n906) );
INVX2TS U1379 ( .A(n974), .Y(n1003) );
NOR2BX1TS U1380 ( .AN(n778), .B(n1003), .Y(n989) );
AOI22X1TS U1381 ( .A0(DmP[3]), .A1(n906), .B0(intDY[3]), .B1(n989), .Y(n779)
);
OAI21XLTS U1382 ( .A0(n1490), .A1(n992), .B0(n779), .Y(n98) );
AOI22X1TS U1383 ( .A0(DmP[2]), .A1(n906), .B0(intDY[2]), .B1(n989), .Y(n780)
);
OAI21XLTS U1384 ( .A0(n1492), .A1(n992), .B0(n780), .Y(n95) );
CLKBUFX2TS U1385 ( .A(n1000), .Y(n996) );
INVX2TS U1386 ( .A(n974), .Y(n990) );
CLKBUFX2TS U1387 ( .A(n989), .Y(n890) );
AOI22X1TS U1388 ( .A0(DmP[0]), .A1(n990), .B0(intDY[0]), .B1(n890), .Y(n781)
);
OAI21XLTS U1389 ( .A0(n1493), .A1(n996), .B0(n781), .Y(n89) );
AOI22X1TS U1390 ( .A0(LZA_output[1]), .A1(n1012), .B0(n665), .B1(
exp_oper_result[1]), .Y(n795) );
NOR2BX1TS U1391 ( .AN(n824), .B(FS_Module_state_reg[3]), .Y(n782) );
CLKBUFX2TS U1392 ( .A(n1294), .Y(n1318) );
NAND2X1TS U1393 ( .A(n1029), .B(n824), .Y(n918) );
AOI22X1TS U1394 ( .A0(n783), .A1(FSM_selector_C), .B0(n1024), .B1(n862), .Y(
n984) );
AOI21X1TS U1395 ( .A0(n784), .A1(n984), .B0(n1520), .Y(n935) );
OAI22X1TS U1396 ( .A0(n1015), .A1(n1531), .B0(FSM_selector_B[0]), .B1(n1437),
.Y(n1017) );
AOI21X1TS U1397 ( .A0(exp_oper_result[0]), .A1(n1459), .B0(n1017), .Y(n799)
);
NOR2X1TS U1398 ( .A(n799), .B(n800), .Y(n1327) );
INVX2TS U1399 ( .A(n1327), .Y(n1243) );
INVX2TS U1400 ( .A(n1243), .Y(n1290) );
OR3X1TS U1401 ( .A(FS_Module_state_reg[3]), .B(n785), .C(add_overflow_flag),
.Y(n919) );
INVX2TS U1402 ( .A(n919), .Y(n1340) );
NOR2X1TS U1403 ( .A(n1340), .B(n1318), .Y(n1283) );
CLKBUFX2TS U1404 ( .A(n1283), .Y(n1341) );
AOI22X1TS U1405 ( .A0(n1341), .A1(n1523), .B0(n1340), .B1(n1452), .Y(n1235)
);
NAND2X1TS U1406 ( .A(n1340), .B(Add_Subt_result[1]), .Y(n787) );
NAND2X1TS U1407 ( .A(n1318), .B(DmP[22]), .Y(n786) );
NAND2X1TS U1408 ( .A(n787), .B(n786), .Y(n788) );
AOI21X1TS U1409 ( .A0(n1341), .A1(Add_Subt_result[24]), .B0(n788), .Y(n872)
);
INVX2TS U1410 ( .A(n872), .Y(n1234) );
NAND2X1TS U1411 ( .A(n799), .B(n795), .Y(n1245) );
INVX2TS U1412 ( .A(n1245), .Y(n1347) );
AOI222XLTS U1413 ( .A0(n800), .A1(n935), .B0(n1290), .B1(n1235), .C0(n1234),
.C1(n1347), .Y(n1247) );
CLKBUFX2TS U1414 ( .A(n1236), .Y(n1311) );
NAND2X1TS U1415 ( .A(n1311), .B(n935), .Y(n1238) );
AOI22X1TS U1416 ( .A0(DmP[4]), .A1(n990), .B0(intDY[4]), .B1(n890), .Y(n789)
);
OAI21XLTS U1417 ( .A0(n1508), .A1(n992), .B0(n789), .Y(n101) );
CLKBUFX2TS U1418 ( .A(n989), .Y(n994) );
INVX2TS U1419 ( .A(n994), .Y(n1005) );
INVX2TS U1420 ( .A(n996), .Y(n1002) );
AOI22X1TS U1421 ( .A0(n1003), .A1(DMP[2]), .B0(intDY[2]), .B1(n1002), .Y(
n790) );
OAI21XLTS U1422 ( .A0(n1005), .A1(n1492), .B0(n790), .Y(n94) );
AOI22X1TS U1423 ( .A0(n1003), .A1(DMP[0]), .B0(intDY[0]), .B1(n1002), .Y(
n791) );
OAI21XLTS U1424 ( .A0(n1005), .A1(n1493), .B0(n791), .Y(n88) );
AOI22X1TS U1425 ( .A0(n1003), .A1(DMP[3]), .B0(intDY[3]), .B1(n1002), .Y(
n792) );
OAI21XLTS U1426 ( .A0(n1005), .A1(n1490), .B0(n792), .Y(n97) );
AOI22X1TS U1427 ( .A0(DmP[6]), .A1(n990), .B0(intDY[6]), .B1(n989), .Y(n793)
);
OAI21XLTS U1428 ( .A0(n1507), .A1(n992), .B0(n793), .Y(n107) );
AOI22X1TS U1429 ( .A0(n1340), .A1(Add_Subt_result[3]), .B0(DmP[20]), .B1(
n1318), .Y(n794) );
OAI2BB1X1TS U1430 ( .A0N(Add_Subt_result[22]), .A1N(n1283), .B0(n794), .Y(
n1242) );
CLKBUFX2TS U1431 ( .A(n1283), .Y(n1319) );
NAND2X1TS U1432 ( .A(n1340), .B(Add_Subt_result[2]), .Y(n797) );
NAND2X1TS U1433 ( .A(n1318), .B(DmP[21]), .Y(n796) );
NAND2X1TS U1434 ( .A(n797), .B(n796), .Y(n798) );
AOI21X1TS U1435 ( .A0(n1319), .A1(Add_Subt_result[23]), .B0(n798), .Y(n932)
);
INVX2TS U1436 ( .A(n932), .Y(n1241) );
NAND2X1TS U1437 ( .A(n800), .B(n799), .Y(n931) );
INVX2TS U1438 ( .A(n931), .Y(n1339) );
AOI222XLTS U1439 ( .A0(n1242), .A1(n1290), .B0(n1234), .B1(n961), .C0(n1241),
.C1(n656), .Y(n803) );
INVX2TS U1440 ( .A(n1311), .Y(n1345) );
AOI21X1TS U1441 ( .A0(n1283), .A1(Add_Subt_result[21]), .B0(n801), .Y(n1244)
);
INVX2TS U1442 ( .A(n1235), .Y(n937) );
CLKBUFX2TS U1443 ( .A(n1311), .Y(n1342) );
AOI22X1TS U1444 ( .A0(n1345), .A1(n1244), .B0(n937), .B1(n1342), .Y(n962) );
AOI22X1TS U1445 ( .A0(n663), .A1(n962), .B0(n957), .B1(n1245), .Y(n802) );
AOI22X1TS U1446 ( .A0(DmP[8]), .A1(n990), .B0(intDY[8]), .B1(n989), .Y(n804)
);
OAI21XLTS U1447 ( .A0(n1482), .A1(n992), .B0(n804), .Y(n113) );
INVX2TS U1448 ( .A(n974), .Y(n966) );
AOI22X1TS U1449 ( .A0(intDY[30]), .A1(n890), .B0(DmP[30]), .B1(n966), .Y(
n805) );
OAI21XLTS U1450 ( .A0(n1440), .A1(n996), .B0(n805), .Y(n179) );
AOI22X1TS U1451 ( .A0(intDY[29]), .A1(n890), .B0(DmP[29]), .B1(n993), .Y(
n806) );
OAI21XLTS U1452 ( .A0(n1441), .A1(n996), .B0(n806), .Y(n176) );
AOI22X1TS U1453 ( .A0(DmP[1]), .A1(n990), .B0(intDY[1]), .B1(n890), .Y(n807)
);
OAI21XLTS U1454 ( .A0(n1491), .A1(n1000), .B0(n807), .Y(n92) );
INVX2TS U1455 ( .A(n970), .Y(n913) );
AOI22X1TS U1456 ( .A0(intDY[22]), .A1(n913), .B0(DMP[22]), .B1(n966), .Y(
n808) );
OAI21XLTS U1457 ( .A0(n1446), .A1(n975), .B0(n808), .Y(n154) );
INVX2TS U1458 ( .A(n974), .Y(n912) );
AOI22X1TS U1459 ( .A0(intDY[25]), .A1(n994), .B0(DmP[25]), .B1(n912), .Y(
n809) );
OAI21XLTS U1460 ( .A0(n1443), .A1(n996), .B0(n809), .Y(n164) );
AOI22X1TS U1461 ( .A0(intDY[26]), .A1(n994), .B0(DmP[26]), .B1(n912), .Y(
n810) );
OAI21XLTS U1462 ( .A0(n1485), .A1(n996), .B0(n810), .Y(n167) );
AOI22X1TS U1463 ( .A0(intDY[27]), .A1(n994), .B0(DmP[27]), .B1(n912), .Y(
n811) );
OAI21XLTS U1464 ( .A0(n1489), .A1(n996), .B0(n811), .Y(n170) );
AOI22X1TS U1465 ( .A0(intDX[24]), .A1(n994), .B0(DMP[24]), .B1(n912), .Y(
n812) );
OAI21XLTS U1466 ( .A0(n1486), .A1(n996), .B0(n812), .Y(n160) );
CLKBUFX2TS U1467 ( .A(n989), .Y(n997) );
AOI22X1TS U1468 ( .A0(DmP[11]), .A1(n990), .B0(intDY[11]), .B1(n997), .Y(
n813) );
OAI21XLTS U1469 ( .A0(n1481), .A1(n992), .B0(n813), .Y(n122) );
INVX2TS U1470 ( .A(n974), .Y(n998) );
AOI22X1TS U1471 ( .A0(DmP[19]), .A1(n998), .B0(intDY[19]), .B1(n997), .Y(
n814) );
OAI21XLTS U1472 ( .A0(n1436), .A1(n970), .B0(n814), .Y(n146) );
AOI22X1TS U1473 ( .A0(DmP[9]), .A1(n990), .B0(intDY[9]), .B1(n997), .Y(n815)
);
OAI21XLTS U1474 ( .A0(n1488), .A1(n992), .B0(n815), .Y(n116) );
AOI22X1TS U1475 ( .A0(DmP[20]), .A1(n998), .B0(intDY[20]), .B1(n994), .Y(
n816) );
OAI21XLTS U1476 ( .A0(n1445), .A1(n970), .B0(n816), .Y(n149) );
AOI22X1TS U1477 ( .A0(DmP[21]), .A1(n998), .B0(intDY[21]), .B1(n994), .Y(
n817) );
OAI21XLTS U1478 ( .A0(n1480), .A1(n970), .B0(n817), .Y(n152) );
AOI22X1TS U1479 ( .A0(n1003), .A1(DMP[4]), .B0(intDY[4]), .B1(n1002), .Y(
n818) );
OAI21XLTS U1480 ( .A0(n1005), .A1(n1508), .B0(n818), .Y(n100) );
AOI22X1TS U1481 ( .A0(n1003), .A1(DMP[1]), .B0(intDY[1]), .B1(n1002), .Y(
n819) );
OAI21XLTS U1482 ( .A0(n1005), .A1(n1491), .B0(n819), .Y(n91) );
CLKBUFX2TS U1483 ( .A(n822), .Y(n1541) );
CLKBUFX2TS U1484 ( .A(n822), .Y(n821) );
CLKBUFX2TS U1485 ( .A(n821), .Y(n1551) );
CLKBUFX2TS U1486 ( .A(n822), .Y(n820) );
CLKBUFX2TS U1487 ( .A(n820), .Y(n1535) );
CLKBUFX2TS U1488 ( .A(n822), .Y(n1550) );
CLKBUFX2TS U1489 ( .A(n820), .Y(n1540) );
CLKBUFX2TS U1490 ( .A(n820), .Y(n1536) );
CLKBUFX2TS U1491 ( .A(n821), .Y(n1539) );
CLKBUFX2TS U1492 ( .A(n820), .Y(n1537) );
CLKBUFX2TS U1493 ( .A(n821), .Y(n1549) );
CLKBUFX2TS U1494 ( .A(n821), .Y(n1545) );
CLKBUFX2TS U1495 ( .A(n822), .Y(n1538) );
CLKBUFX2TS U1496 ( .A(n820), .Y(n1546) );
CLKBUFX2TS U1497 ( .A(n822), .Y(n1547) );
CLKBUFX2TS U1498 ( .A(n820), .Y(n1553) );
CLKBUFX2TS U1499 ( .A(n821), .Y(n1556) );
CLKBUFX2TS U1500 ( .A(n820), .Y(n1552) );
CLKBUFX2TS U1501 ( .A(n820), .Y(n1548) );
CLKBUFX2TS U1502 ( .A(n820), .Y(n1558) );
CLKBUFX2TS U1503 ( .A(n821), .Y(n1557) );
CLKBUFX2TS U1504 ( .A(n821), .Y(n1543) );
CLKBUFX2TS U1505 ( .A(n821), .Y(n1534) );
CLKBUFX2TS U1506 ( .A(n822), .Y(n1554) );
CLKBUFX2TS U1507 ( .A(n822), .Y(n1555) );
CLKBUFX2TS U1508 ( .A(n821), .Y(n1533) );
CLKBUFX2TS U1509 ( .A(n822), .Y(n1544) );
CLKBUFX2TS U1510 ( .A(n822), .Y(n1542) );
NOR2BX1TS U1511 ( .AN(n1029), .B(FS_Module_state_reg[2]), .Y(n1071) );
INVX2TS U1512 ( .A(n1071), .Y(n976) );
INVX2TS U1513 ( .A(n1420), .Y(n1418) );
AOI22X1TS U1514 ( .A0(n1029), .A1(n1024), .B0(FSM_selector_B[1]), .B1(n976),
.Y(n823) );
OAI21XLTS U1515 ( .A0(n1418), .A1(n1520), .B0(n823), .Y(n70) );
INVX2TS U1516 ( .A(n826), .Y(n1407) );
CLKBUFX2TS U1517 ( .A(n1407), .Y(n1366) );
INVX2TS U1518 ( .A(n1366), .Y(n1405) );
OR3X1TS U1519 ( .A(overflow_flag), .B(underflow_flag), .C(n1405), .Y(n1359)
);
CLKBUFX2TS U1520 ( .A(n1359), .Y(n1403) );
OA22X1TS U1521 ( .A0(exp_oper_result[6]), .A1(n1403), .B0(n1366), .B1(
final_result_ieee[29]), .Y(n61) );
NAND2X1TS U1522 ( .A(n982), .B(n1455), .Y(n244) );
OAI22X1TS U1523 ( .A0(n1486), .A1(intDX[24]), .B0(n1501), .B1(intDY[28]),
.Y(n827) );
AOI221XLTS U1524 ( .A0(n1486), .A1(intDX[24]), .B0(intDY[28]), .B1(n1501),
.C0(n827), .Y(n833) );
OAI22X1TS U1525 ( .A0(n1493), .A1(intDY[0]), .B0(n1508), .B1(intDY[4]), .Y(
n828) );
AOI221XLTS U1526 ( .A0(n1493), .A1(intDY[0]), .B0(intDY[4]), .B1(n1508),
.C0(n828), .Y(n832) );
OAI22X1TS U1527 ( .A0(n1448), .A1(intDY[5]), .B0(n1492), .B1(intDY[2]), .Y(
n829) );
AOI221XLTS U1528 ( .A0(n1448), .A1(intDY[5]), .B0(intDY[2]), .B1(n1492),
.C0(n829), .Y(n831) );
AOI22X1TS U1529 ( .A0(intDX[17]), .A1(n1518), .B0(intDY[17]), .B1(n1494),
.Y(n830) );
NAND4XLTS U1530 ( .A(n833), .B(n832), .C(n831), .D(n830), .Y(n861) );
OAI22X1TS U1531 ( .A0(n1490), .A1(intDY[3]), .B0(n1447), .B1(intDY[7]), .Y(
n834) );
AOI221XLTS U1532 ( .A0(n1490), .A1(intDY[3]), .B0(intDY[7]), .B1(n1447),
.C0(n834), .Y(n841) );
OAI22X1TS U1533 ( .A0(n1482), .A1(intDY[8]), .B0(n1442), .B1(intDY[13]), .Y(
n835) );
AOI221XLTS U1534 ( .A0(n1482), .A1(intDY[8]), .B0(intDY[13]), .B1(n1442),
.C0(n835), .Y(n840) );
OAI22X1TS U1535 ( .A0(n1507), .A1(intDY[6]), .B0(n1481), .B1(intDY[11]), .Y(
n836) );
AOI221XLTS U1536 ( .A0(n1507), .A1(intDY[6]), .B0(intDY[11]), .B1(n1481),
.C0(n836), .Y(n839) );
OAI22X1TS U1537 ( .A0(n1444), .A1(intDY[12]), .B0(n1491), .B1(intDY[1]), .Y(
n837) );
AOI221XLTS U1538 ( .A0(n1444), .A1(intDY[12]), .B0(intDY[1]), .B1(n1491),
.C0(n837), .Y(n838) );
NAND4XLTS U1539 ( .A(n841), .B(n840), .C(n839), .D(n838), .Y(n860) );
OAI22X1TS U1540 ( .A0(n1506), .A1(intDY[10]), .B0(n1479), .B1(intDY[15]),
.Y(n842) );
AOI221XLTS U1541 ( .A0(n1506), .A1(intDY[10]), .B0(intDY[15]), .B1(n1479),
.C0(n842), .Y(n849) );
OAI22X1TS U1542 ( .A0(n1509), .A1(intDY[16]), .B0(n1480), .B1(intDY[21]),
.Y(n843) );
AOI221XLTS U1543 ( .A0(n1509), .A1(intDY[16]), .B0(intDY[21]), .B1(n1480),
.C0(n843), .Y(n848) );
OAI22X1TS U1544 ( .A0(n1487), .A1(intDY[14]), .B0(n1436), .B1(intDY[19]),
.Y(n844) );
AOI221XLTS U1545 ( .A0(n1487), .A1(intDY[14]), .B0(intDY[19]), .B1(n1436),
.C0(n844), .Y(n847) );
OAI22X1TS U1546 ( .A0(n1445), .A1(intDY[20]), .B0(n1488), .B1(intDY[9]), .Y(
n845) );
AOI221XLTS U1547 ( .A0(n1445), .A1(intDY[20]), .B0(intDY[9]), .B1(n1488),
.C0(n845), .Y(n846) );
NAND4XLTS U1548 ( .A(n849), .B(n848), .C(n847), .D(n846), .Y(n859) );
OAI22X1TS U1549 ( .A0(n1484), .A1(intDY[18]), .B0(n1443), .B1(intDY[25]),
.Y(n850) );
AOI221XLTS U1550 ( .A0(n1484), .A1(intDY[18]), .B0(intDY[25]), .B1(n1443),
.C0(n850), .Y(n857) );
OAI22X1TS U1551 ( .A0(n1483), .A1(intDY[23]), .B0(n1440), .B1(intDY[30]),
.Y(n851) );
AOI221XLTS U1552 ( .A0(n1483), .A1(intDY[23]), .B0(intDY[30]), .B1(n1440),
.C0(n851), .Y(n856) );
OAI22X1TS U1553 ( .A0(n1446), .A1(intDY[22]), .B0(n1489), .B1(intDY[27]),
.Y(n852) );
AOI221XLTS U1554 ( .A0(n1446), .A1(intDY[22]), .B0(intDY[27]), .B1(n1489),
.C0(n852), .Y(n855) );
OAI22X1TS U1555 ( .A0(n1485), .A1(intDY[26]), .B0(n1441), .B1(intDY[29]),
.Y(n853) );
AOI221XLTS U1556 ( .A0(n1485), .A1(intDY[26]), .B0(intDY[29]), .B1(n1441),
.C0(n853), .Y(n854) );
NAND4XLTS U1557 ( .A(n857), .B(n856), .C(n855), .D(n854), .Y(n858) );
NOR4XLTS U1558 ( .A(n861), .B(n860), .C(n859), .D(n858), .Y(n971) );
AOI21X1TS U1559 ( .A0(n971), .A1(n949), .B0(n1003), .Y(n866) );
OAI22X1TS U1560 ( .A0(beg_FSM), .A1(n244), .B0(ack_FSM), .B1(n864), .Y(n1023) );
AOI22X1TS U1561 ( .A0(DmP[5]), .A1(n906), .B0(intDY[5]), .B1(n989), .Y(n867)
);
OAI21XLTS U1562 ( .A0(n1448), .A1(n992), .B0(n867), .Y(n104) );
INVX2TS U1563 ( .A(n1311), .Y(n1322) );
AOI21X1TS U1564 ( .A0(n1283), .A1(Add_Subt_result[19]), .B0(n868), .Y(n1251)
);
OAI2BB2XLTS U1565 ( .B0(n1322), .B1(n1241), .A0N(n1322), .A1N(n1251), .Y(
n965) );
INVX2TS U1566 ( .A(n1243), .Y(n1349) );
AOI21X1TS U1567 ( .A0(n1283), .A1(Add_Subt_result[18]), .B0(n869), .Y(n1255)
);
AOI21X1TS U1568 ( .A0(n1283), .A1(Add_Subt_result[17]), .B0(n870), .Y(n1259)
);
AOI22X1TS U1569 ( .A0(n1345), .A1(n1259), .B0(n1244), .B1(n1342), .Y(n1256)
);
AOI22X1TS U1570 ( .A0(n1349), .A1(n1252), .B0(n1347), .B1(n1256), .Y(n874)
);
AOI21X1TS U1571 ( .A0(Add_Subt_result[20]), .A1(n1341), .B0(n871), .Y(n1246)
);
AOI22X1TS U1572 ( .A0(n1345), .A1(n1246), .B0(n872), .B1(n1342), .Y(n960) );
NAND2X1TS U1573 ( .A(n960), .B(n961), .Y(n873) );
INVX2TS U1574 ( .A(n961), .Y(n1240) );
AOI21X1TS U1575 ( .A0(Add_Subt_result[16]), .A1(n1341), .B0(n875), .Y(n1263)
);
AOI22X1TS U1576 ( .A0(n1345), .A1(n1263), .B0(n1246), .B1(n1342), .Y(n1260)
);
AOI22X1TS U1577 ( .A0(n1349), .A1(n1256), .B0(n663), .B1(n1260), .Y(n877) );
NAND2X1TS U1578 ( .A(n657), .B(n1252), .Y(n876) );
AOI22X1TS U1579 ( .A0(DmP[17]), .A1(n998), .B0(intDX[17]), .B1(n898), .Y(
n878) );
OAI21XLTS U1580 ( .A0(n1518), .A1(n975), .B0(n878), .Y(n140) );
AOI22X1TS U1581 ( .A0(intDY[23]), .A1(n994), .B0(DmP[23]), .B1(n912), .Y(
n879) );
OAI21XLTS U1582 ( .A0(n1483), .A1(n1000), .B0(n879), .Y(n158) );
AOI22X1TS U1583 ( .A0(DmP[15]), .A1(n998), .B0(intDY[15]), .B1(n997), .Y(
n880) );
OAI21XLTS U1584 ( .A0(n1479), .A1(n1000), .B0(n880), .Y(n134) );
AOI22X1TS U1585 ( .A0(DmP[18]), .A1(n998), .B0(intDY[18]), .B1(n997), .Y(
n881) );
OAI21XLTS U1586 ( .A0(n1484), .A1(n1000), .B0(n881), .Y(n143) );
AOI22X1TS U1587 ( .A0(DmP[12]), .A1(n998), .B0(intDY[12]), .B1(n997), .Y(
n882) );
OAI21XLTS U1588 ( .A0(n1444), .A1(n1000), .B0(n882), .Y(n125) );
AOI22X1TS U1589 ( .A0(DmP[14]), .A1(n990), .B0(intDY[14]), .B1(n997), .Y(
n883) );
OAI21XLTS U1590 ( .A0(n1487), .A1(n1000), .B0(n883), .Y(n131) );
AOI22X1TS U1591 ( .A0(DmP[13]), .A1(n998), .B0(intDY[13]), .B1(n997), .Y(
n884) );
OAI21XLTS U1592 ( .A0(n1442), .A1(n1000), .B0(n884), .Y(n128) );
AOI22X1TS U1593 ( .A0(DmP[22]), .A1(n998), .B0(intDY[22]), .B1(n994), .Y(
n885) );
OAI21XLTS U1594 ( .A0(n1446), .A1(n996), .B0(n885), .Y(n155) );
AOI22X1TS U1595 ( .A0(DmP[10]), .A1(n990), .B0(intDY[10]), .B1(n997), .Y(
n886) );
OAI21XLTS U1596 ( .A0(n1506), .A1(n992), .B0(n886), .Y(n119) );
INVX2TS U1597 ( .A(n890), .Y(n969) );
INVX2TS U1598 ( .A(n970), .Y(n967) );
AOI22X1TS U1599 ( .A0(intDY[15]), .A1(n967), .B0(DMP[15]), .B1(n906), .Y(
n887) );
OAI21XLTS U1600 ( .A0(n1479), .A1(n969), .B0(n887), .Y(n133) );
AOI22X1TS U1601 ( .A0(intDY[18]), .A1(n967), .B0(DMP[18]), .B1(n966), .Y(
n888) );
OAI21XLTS U1602 ( .A0(n1484), .A1(n969), .B0(n888), .Y(n142) );
AOI22X1TS U1603 ( .A0(intDY[19]), .A1(n913), .B0(DMP[19]), .B1(n966), .Y(
n889) );
OAI21XLTS U1604 ( .A0(n1436), .A1(n969), .B0(n889), .Y(n145) );
INVX2TS U1605 ( .A(n890), .Y(n909) );
AOI22X1TS U1606 ( .A0(intDY[27]), .A1(n913), .B0(DMP[27]), .B1(n912), .Y(
n891) );
OAI21XLTS U1607 ( .A0(n1489), .A1(n909), .B0(n891), .Y(n169) );
AOI22X1TS U1608 ( .A0(intDY[20]), .A1(n913), .B0(DMP[20]), .B1(n966), .Y(
n892) );
OAI21XLTS U1609 ( .A0(n1445), .A1(n969), .B0(n892), .Y(n148) );
AOI22X1TS U1610 ( .A0(intDY[11]), .A1(n967), .B0(DMP[11]), .B1(n966), .Y(
n893) );
OAI21XLTS U1611 ( .A0(n1481), .A1(n909), .B0(n893), .Y(n121) );
AOI22X1TS U1612 ( .A0(intDY[30]), .A1(n967), .B0(DMP[30]), .B1(n993), .Y(
n894) );
OAI21XLTS U1613 ( .A0(n1440), .A1(n909), .B0(n894), .Y(n178) );
AOI22X1TS U1614 ( .A0(intDY[12]), .A1(n967), .B0(DMP[12]), .B1(n906), .Y(
n895) );
OAI21XLTS U1615 ( .A0(n1444), .A1(n969), .B0(n895), .Y(n124) );
AOI22X1TS U1616 ( .A0(intDX[24]), .A1(n913), .B0(DmP[24]), .B1(n912), .Y(
n896) );
OAI21XLTS U1617 ( .A0(n1486), .A1(n909), .B0(n896), .Y(n161) );
AOI22X1TS U1618 ( .A0(intDY[8]), .A1(n1002), .B0(DMP[8]), .B1(n906), .Y(n897) );
OAI21XLTS U1619 ( .A0(n1482), .A1(n909), .B0(n897), .Y(n112) );
AOI22X1TS U1620 ( .A0(intDY[9]), .A1(n898), .B0(DMP[9]), .B1(n906), .Y(n899)
);
OAI21XLTS U1621 ( .A0(n1488), .A1(n909), .B0(n899), .Y(n115) );
AOI22X1TS U1622 ( .A0(intDY[25]), .A1(n913), .B0(DMP[25]), .B1(n912), .Y(
n900) );
OAI21XLTS U1623 ( .A0(n1443), .A1(n909), .B0(n900), .Y(n163) );
AOI22X1TS U1624 ( .A0(intDY[13]), .A1(n967), .B0(DMP[13]), .B1(n906), .Y(
n901) );
OAI21XLTS U1625 ( .A0(n1442), .A1(n969), .B0(n901), .Y(n127) );
AOI22X1TS U1626 ( .A0(intDY[29]), .A1(n1002), .B0(DMP[29]), .B1(n993), .Y(
n902) );
OAI21XLTS U1627 ( .A0(n1441), .A1(n909), .B0(n902), .Y(n175) );
AOI22X1TS U1628 ( .A0(intDY[21]), .A1(n913), .B0(DMP[21]), .B1(n966), .Y(
n903) );
OAI21XLTS U1629 ( .A0(n1480), .A1(n969), .B0(n903), .Y(n151) );
AOI22X1TS U1630 ( .A0(intDY[14]), .A1(n967), .B0(DMP[14]), .B1(n966), .Y(
n904) );
OAI21XLTS U1631 ( .A0(n1487), .A1(n969), .B0(n904), .Y(n130) );
AOI22X1TS U1632 ( .A0(intDY[10]), .A1(n967), .B0(DMP[10]), .B1(n906), .Y(
n905) );
OAI21XLTS U1633 ( .A0(n1506), .A1(n909), .B0(n905), .Y(n118) );
AOI22X1TS U1634 ( .A0(intDY[16]), .A1(n967), .B0(DMP[16]), .B1(n906), .Y(
n907) );
OAI21XLTS U1635 ( .A0(n1509), .A1(n969), .B0(n907), .Y(n136) );
AOI22X1TS U1636 ( .A0(intDY[28]), .A1(n913), .B0(DMP[28]), .B1(n912), .Y(
n908) );
OAI21XLTS U1637 ( .A0(n1501), .A1(n909), .B0(n908), .Y(n172) );
AOI22X1TS U1638 ( .A0(n1003), .A1(DMP[6]), .B0(intDY[6]), .B1(n1002), .Y(
n910) );
OAI21XLTS U1639 ( .A0(n1005), .A1(n1507), .B0(n910), .Y(n106) );
AOI22X1TS U1640 ( .A0(intDY[23]), .A1(n913), .B0(DMP[23]), .B1(n966), .Y(
n911) );
OAI21XLTS U1641 ( .A0(n1483), .A1(n1005), .B0(n911), .Y(n157) );
AOI22X1TS U1642 ( .A0(intDY[26]), .A1(n913), .B0(DMP[26]), .B1(n912), .Y(
n914) );
OAI21XLTS U1643 ( .A0(n1485), .A1(n1005), .B0(n914), .Y(n166) );
AOI22X1TS U1644 ( .A0(LZA_output[3]), .A1(n1012), .B0(n664), .B1(
exp_oper_result[3]), .Y(n915) );
AOI22X1TS U1645 ( .A0(LZA_output[4]), .A1(n1012), .B0(n664), .B1(
exp_oper_result[4]), .Y(n938) );
NAND2X1TS U1646 ( .A(n915), .B(n938), .Y(n926) );
NOR2X1TS U1647 ( .A(n938), .B(n940), .Y(n1064) );
AOI22X1TS U1648 ( .A0(n921), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[27]), .B0(n1064), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n917) );
NAND2X1TS U1649 ( .A(n940), .B(n938), .Y(n1372) );
INVX2TS U1650 ( .A(n1372), .Y(n1065) );
AOI22X1TS U1651 ( .A0(n922), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .B1(n658), .Y(n916)
);
NAND2X1TS U1652 ( .A(n1019), .B(n918), .Y(n1374) );
NAND2X1TS U1653 ( .A(n1374), .B(n1340), .Y(n1371) );
NAND2X1TS U1654 ( .A(n1374), .B(n919), .Y(n1373) );
CLKBUFX2TS U1655 ( .A(n1398), .Y(n1380) );
AOI22X1TS U1656 ( .A0(n659), .A1(Sgf_normalized_result[24]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .B1(n1380), .Y(n920)
);
INVX2TS U1657 ( .A(n954), .Y(n1368) );
AOI22X1TS U1658 ( .A0(n921), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[26]), .B0(n1064), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n924) );
AOI22X1TS U1659 ( .A0(n922), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .B1(n658), .Y(n923)
);
AOI22X1TS U1660 ( .A0(n661), .A1(Sgf_normalized_result[25]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .B1(n1380), .Y(n925)
);
CLKBUFX2TS U1661 ( .A(n1394), .Y(n1066) );
AOI22X1TS U1662 ( .A0(n1066), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .B0(n659), .B1(
Sgf_normalized_result[1]), .Y(n927) );
AOI22X1TS U1663 ( .A0(n1066), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .B0(n660), .B1(
Sgf_normalized_result[0]), .Y(n929) );
OAI22X1TS U1664 ( .A0(n932), .A1(n1245), .B0(n931), .B1(n937), .Y(n933) );
INVX2TS U1665 ( .A(n1311), .Y(n1331) );
AOI32X1TS U1666 ( .A0(n1290), .A1(n1322), .A2(n1234), .B0(n933), .B1(n1331),
.Y(n934) );
AOI21X1TS U1667 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[50]), .A1(
n1065), .B0(n1375), .Y(n1043) );
AOI22X1TS U1668 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[51]), .A1(
n1064), .B0(n1065), .B1(Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n941) );
NAND2X1TS U1669 ( .A(n1375), .B(n940), .Y(n1052) );
NAND2X1TS U1670 ( .A(n941), .B(n1052), .Y(n1045) );
CLKBUFX2TS U1671 ( .A(n1394), .Y(n1379) );
AOI22X1TS U1672 ( .A0(n652), .A1(n1045), .B0(n1379), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .Y(n943) );
AOI22X1TS U1673 ( .A0(n659), .A1(Sgf_normalized_result[16]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .B1(n1380), .Y(n942)
);
AOI21X1TS U1674 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[51]), .A1(
n1065), .B0(n1375), .Y(n1048) );
AOI22X1TS U1675 ( .A0(n1065), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .B1(n1064), .Y(n944)
);
NAND2X1TS U1676 ( .A(n944), .B(n1052), .Y(n1050) );
AOI22X1TS U1677 ( .A0(n652), .A1(n1050), .B0(n1379), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .Y(n946) );
AOI22X1TS U1678 ( .A0(n660), .A1(Sgf_normalized_result[17]), .B0(n1380),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n945) );
OAI22X1TS U1679 ( .A0(r_mode[0]), .A1(n1453), .B0(Sgf_normalized_result[0]),
.B1(Sgf_normalized_result[1]), .Y(n948) );
INVX2TS U1680 ( .A(n1153), .Y(n1227) );
OAI21XLTS U1681 ( .A0(n1023), .A1(n1024), .B0(FS_Module_state_reg[3]), .Y(
n951) );
AOI22X1TS U1682 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[41]), .A1(
n1065), .B0(Barrel_Shifter_module_Mux_Array_Data_array[49]), .B1(n1064), .Y(n1051) );
AOI21X1TS U1683 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(
n1380), .B0(n954), .Y(n956) );
AOI22X1TS U1684 ( .A0(n661), .A1(Sgf_normalized_result[18]), .B0(n1379),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[33]), .Y(n955) );
AOI22X1TS U1685 ( .A0(n1349), .A1(n960), .B0(n656), .B1(n962), .Y(n959) );
INVX2TS U1686 ( .A(n1240), .Y(n1333) );
AOI32X1TS U1687 ( .A0(n1345), .A1(n1333), .A2(n1242), .B0(n957), .B1(n1333),
.Y(n958) );
AOI22X1TS U1688 ( .A0(n960), .A1(n1339), .B0(n662), .B1(n1252), .Y(n964) );
NAND2X1TS U1689 ( .A(n962), .B(n961), .Y(n963) );
AOI22X1TS U1690 ( .A0(intDY[17]), .A1(n967), .B0(DMP[17]), .B1(n966), .Y(
n968) );
OAI222X1TS U1691 ( .A0(n975), .A1(n1454), .B0(n1453), .B1(n974), .C0(n973),
.C1(n972), .Y(n86) );
OAI211XLTS U1692 ( .A0(n1026), .A1(FSM_selector_C), .B0(n977), .C0(n976),
.Y(n981) );
NAND2X1TS U1693 ( .A(n982), .B(FS_Module_state_reg[0]), .Y(n1422) );
INVX2TS U1694 ( .A(n1422), .Y(n1430) );
CLKBUFX2TS U1695 ( .A(n1430), .Y(n1433) );
INVX2TS U1696 ( .A(n1433), .Y(n1063) );
OR4X2TS U1697 ( .A(Exp_Operation_Module_Data_S[2]), .B(
Exp_Operation_Module_Data_S[0]), .C(Exp_Operation_Module_Data_S[1]),
.D(n984), .Y(n985) );
OR4X2TS U1698 ( .A(Exp_Operation_Module_Data_S[5]), .B(
Exp_Operation_Module_Data_S[4]), .C(Exp_Operation_Module_Data_S[3]),
.D(n985), .Y(n986) );
OR4X2TS U1699 ( .A(n1230), .B(Exp_Operation_Module_Data_S[7]), .C(
Exp_Operation_Module_Data_S[6]), .D(n986), .Y(n987) );
OAI21XLTS U1700 ( .A0(n1153), .A1(FS_Module_state_reg[0]), .B0(n1318), .Y(
n243) );
AOI22X1TS U1701 ( .A0(DmP[7]), .A1(n990), .B0(intDY[7]), .B1(n989), .Y(n991)
);
OAI21XLTS U1702 ( .A0(n1447), .A1(n992), .B0(n991), .Y(n110) );
AOI22X1TS U1703 ( .A0(intDY[28]), .A1(n994), .B0(DmP[28]), .B1(n993), .Y(
n995) );
OAI21XLTS U1704 ( .A0(n1501), .A1(n996), .B0(n995), .Y(n173) );
AOI22X1TS U1705 ( .A0(DmP[16]), .A1(n998), .B0(intDY[16]), .B1(n997), .Y(
n999) );
OAI21XLTS U1706 ( .A0(n1509), .A1(n1000), .B0(n999), .Y(n137) );
AOI22X1TS U1707 ( .A0(n1003), .A1(DMP[7]), .B0(intDY[7]), .B1(n1002), .Y(
n1001) );
OAI21XLTS U1708 ( .A0(n1005), .A1(n1447), .B0(n1001), .Y(n109) );
AOI22X1TS U1709 ( .A0(n1003), .A1(DMP[5]), .B0(intDY[5]), .B1(n1002), .Y(
n1004) );
OAI21XLTS U1710 ( .A0(n1005), .A1(n1448), .B0(n1004), .Y(n103) );
OAI2BB2XLTS U1711 ( .B0(n1467), .B1(n1015), .A0N(DmP[24]), .A1N(n664), .Y(
n1016) );
OAI21XLTS U1712 ( .A0(FSM_selector_C), .A1(n1019), .B0(n1405), .Y(n1027) );
AOI211XLTS U1713 ( .A0(FS_Module_state_reg[1]), .A1(n1023), .B0(n1020), .C0(
n1027), .Y(n1022) );
AOI22X1TS U1714 ( .A0(FS_Module_state_reg[0]), .A1(n1148), .B0(n1024), .B1(
n1455), .Y(n1021) );
NAND2X1TS U1715 ( .A(n1026), .B(n1025), .Y(n1232) );
INVX2TS U1716 ( .A(n1232), .Y(n1122) );
AOI211XLTS U1717 ( .A0(n1029), .A1(n1456), .B0(n1028), .C0(n1027), .Y(n1031)
);
CLKMX2X2TS U1718 ( .A(Add_Subt_result[25]), .B(n1036), .S0(n1227), .Y(n215)
);
AFHCONX2TS U1719 ( .A(n1039), .B(n1038), .CI(n1037), .CON(n1130), .S(n1040)
);
CLKBUFX2TS U1720 ( .A(n1398), .Y(n1356) );
AOI22X1TS U1721 ( .A0(n1356), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .B0(n661), .B1(
Sgf_normalized_result[9]), .Y(n1042) );
NAND2X1TS U1722 ( .A(n1066), .B(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n1041) );
AOI22X1TS U1723 ( .A0(n1356), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .B0(n660), .B1(
Sgf_normalized_result[8]), .Y(n1047) );
NAND2X1TS U1724 ( .A(n1066), .B(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n1046) );
AOI22X1TS U1725 ( .A0(n1066), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(n1356), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .Y(n1053) );
AOI22X1TS U1726 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[40]), .A1(
n1065), .B0(Barrel_Shifter_module_Mux_Array_Data_array[48]), .B1(n1064), .Y(n1367) );
AOI22X1TS U1727 ( .A0(n1066), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(n1356), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .Y(n1055) );
INVX2TS U1728 ( .A(n1433), .Y(n1427) );
AOI22X1TS U1729 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[39]), .A1(
n1065), .B0(Barrel_Shifter_module_Mux_Array_Data_array[47]), .B1(n1064), .Y(n1363) );
AOI22X1TS U1730 ( .A0(n1066), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .B0(n1356), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .Y(n1057) );
AOI22X1TS U1731 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[38]), .A1(
n1065), .B0(Barrel_Shifter_module_Mux_Array_Data_array[46]), .B1(n1064), .Y(n1360) );
AOI22X1TS U1732 ( .A0(n1066), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .B0(n1356), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .Y(n1059) );
AOI22X1TS U1733 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[37]), .A1(
n1065), .B0(Barrel_Shifter_module_Mux_Array_Data_array[45]), .B1(n1064), .Y(n1355) );
AOI22X1TS U1734 ( .A0(n1066), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .B0(n1356), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .Y(n1061) );
AOI22X1TS U1735 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[36]), .A1(
n1065), .B0(Barrel_Shifter_module_Mux_Array_Data_array[44]), .B1(n1064), .Y(n1352) );
AOI22X1TS U1736 ( .A0(n1066), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .B0(n1356), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[28]), .Y(n1068) );
INVX2TS U1737 ( .A(n1110), .Y(n1072) );
INVX2TS U1738 ( .A(n1104), .Y(n1073) );
NOR2XLTS U1739 ( .A(Add_Subt_result[23]), .B(Add_Subt_result[22]), .Y(n1108)
);
NAND2X1TS U1740 ( .A(n1111), .B(n1108), .Y(n1103) );
INVX2TS U1741 ( .A(n1410), .Y(n1074) );
INVX2TS U1742 ( .A(n1107), .Y(n1075) );
NAND2X1TS U1743 ( .A(n1089), .B(n1086), .Y(n1112) );
NOR2BX1TS U1744 ( .AN(n1417), .B(Add_Subt_result[12]), .Y(n1093) );
NOR2XLTS U1745 ( .A(Add_Subt_result[9]), .B(Add_Subt_result[8]), .Y(n1077)
);
NAND2X1TS U1746 ( .A(n1082), .B(n1077), .Y(n1078) );
OR2X1TS U1747 ( .A(Add_Subt_result[3]), .B(Add_Subt_result[2]), .Y(n1080) );
AOI22X1TS U1748 ( .A0(n1099), .A1(n1080), .B0(n1415), .B1(n1079), .Y(n1115)
);
OAI21XLTS U1749 ( .A0(Add_Subt_result[1]), .A1(Add_Subt_result[0]), .B0(
n1094), .Y(n1084) );
AOI22X1TS U1750 ( .A0(Add_Subt_result[10]), .A1(n1417), .B0(n1094), .B1(
Add_Subt_result[1]), .Y(n1091) );
INVX2TS U1751 ( .A(n1086), .Y(n1088) );
OA21XLTS U1752 ( .A0(Add_Subt_result[11]), .A1(Add_Subt_result[13]), .B0(
n1098), .Y(n1087) );
OAI22X1TS U1753 ( .A0(n1116), .A1(n1451), .B0(n1112), .B1(n1521), .Y(n1409)
);
AOI21X1TS U1754 ( .A0(n1091), .A1(n1090), .B0(n1418), .Y(n1092) );
NAND2X1TS U1755 ( .A(Add_Subt_result[2]), .B(n1099), .Y(n1097) );
AOI22X1TS U1756 ( .A0(Add_Subt_result[5]), .A1(n1100), .B0(
Add_Subt_result[3]), .B1(n1099), .Y(n1101) );
OAI2BB1X1TS U1757 ( .A0N(LZA_output[2]), .A1N(n1418), .B0(n1106), .Y(n75) );
AND3X1TS U1758 ( .A(n1410), .B(Add_Subt_result[15]), .C(n1107), .Y(n1120) );
INVX2TS U1759 ( .A(n1108), .Y(n1109) );
AOI21X1TS U1760 ( .A0(n1110), .A1(Add_Subt_result[19]), .B0(n1109), .Y(n1114) );
INVX2TS U1761 ( .A(n1111), .Y(n1113) );
OAI22X1TS U1762 ( .A0(n1114), .A1(n1113), .B0(n1521), .B1(n1112), .Y(n1118)
);
NOR4XLTS U1763 ( .A(n1120), .B(n1119), .C(n1118), .D(n1117), .Y(n1121) );
AFHCINX2TS U1764 ( .CIN(n1132), .B(n1133), .A(n1134), .S(n1135), .CO(n1123)
);
INVX2TS U1765 ( .A(n1153), .Y(n1206) );
AFHCONX2TS U1766 ( .A(n1157), .B(n1156), .CI(n1155), .CON(n1164), .S(n1158)
);
AFHCONX2TS U1767 ( .A(n1192), .B(n1191), .CI(n1190), .CON(n1199), .S(n1193)
);
AFHCINX2TS U1768 ( .CIN(n1199), .B(n1200), .A(n1201), .S(n1202), .CO(n1208)
);
AFHCONX2TS U1769 ( .A(n1210), .B(n1209), .CI(n1208), .CON(n1216), .S(n1211)
);
AFHCONX2TS U1770 ( .A(n1214), .B(n1213), .CI(n1212), .CON(n1203), .S(n1215)
);
AFHCONX2TS U1771 ( .A(n1226), .B(n1225), .CI(n1224), .CON(n1220), .S(n1228)
);
AND4X1TS U1772 ( .A(Exp_Operation_Module_Data_S[3]), .B(
Exp_Operation_Module_Data_S[2]), .C(Exp_Operation_Module_Data_S[0]),
.D(Exp_Operation_Module_Data_S[1]), .Y(n1229) );
AND4X1TS U1773 ( .A(Exp_Operation_Module_Data_S[6]), .B(
Exp_Operation_Module_Data_S[5]), .C(Exp_Operation_Module_Data_S[4]),
.D(n1229), .Y(n1231) );
AOI21X1TS U1774 ( .A0(Exp_Operation_Module_Data_S[7]), .A1(n1231), .B0(n1230), .Y(n1233) );
AOI22X1TS U1775 ( .A0(n1349), .A1(n1241), .B0(n656), .B1(n1234), .Y(n1239)
);
AOI22X1TS U1776 ( .A0(n1235), .A1(n1333), .B0(n662), .B1(n1242), .Y(n1237)
);
CLKBUFX2TS U1777 ( .A(n1236), .Y(n1328) );
AOI32X1TS U1778 ( .A0(n1239), .A1(n1238), .A2(n1237), .B0(n1328), .B1(n1238),
.Y(Barrel_Shifter_module_Mux_Array_Data_array[22]) );
INVX2TS U1779 ( .A(n1240), .Y(n1337) );
AOI22X1TS U1780 ( .A0(n657), .A1(n1242), .B0(n1337), .B1(n1241), .Y(n1249)
);
OA22X1TS U1781 ( .A0(n1246), .A1(n1245), .B0(n1244), .B1(n1243), .Y(n1248)
);
AOI32X1TS U1782 ( .A0(n1249), .A1(n1322), .A2(n1248), .B0(n1247), .B1(n1311),
.Y(Barrel_Shifter_module_Mux_Array_Data_array[20]) );
AOI21X1TS U1783 ( .A0(n1319), .A1(Add_Subt_result[15]), .B0(n1250), .Y(n1268) );
AOI22X1TS U1784 ( .A0(n1345), .A1(n1268), .B0(n1251), .B1(n1342), .Y(n1264)
);
AOI22X1TS U1785 ( .A0(n1349), .A1(n1260), .B0(n662), .B1(n1264), .Y(n1254)
);
AOI22X1TS U1786 ( .A0(n657), .A1(n1256), .B0(n1337), .B1(n1252), .Y(n1253)
);
NAND2X1TS U1787 ( .A(n1254), .B(n1253), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[15]) );
AOI222XLTS U1788 ( .A0(n1519), .A1(DmP[12]), .B0(Add_Subt_result[14]), .B1(
n1319), .C0(Add_Subt_result[11]), .C1(n1267), .Y(n1273) );
AOI22X1TS U1789 ( .A0(n1345), .A1(n1273), .B0(n1255), .B1(n1342), .Y(n1269)
);
AOI22X1TS U1790 ( .A0(n1349), .A1(n1264), .B0(n663), .B1(n1269), .Y(n1258)
);
AOI22X1TS U1791 ( .A0(n1339), .A1(n1260), .B0(n1337), .B1(n1256), .Y(n1257)
);
NAND2X1TS U1792 ( .A(n1258), .B(n1257), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[14]) );
AOI222XLTS U1793 ( .A0(n1519), .A1(DmP[11]), .B0(Add_Subt_result[13]), .B1(
n1319), .C0(Add_Subt_result[12]), .C1(n1267), .Y(n1278) );
AOI22X1TS U1794 ( .A0(n1345), .A1(n1278), .B0(n1259), .B1(n1342), .Y(n1274)
);
AOI22X1TS U1795 ( .A0(n1349), .A1(n1269), .B0(n1347), .B1(n1274), .Y(n1262)
);
AOI22X1TS U1796 ( .A0(n657), .A1(n1264), .B0(n1337), .B1(n1260), .Y(n1261)
);
NAND2X1TS U1797 ( .A(n1262), .B(n1261), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[13]) );
AOI222XLTS U1798 ( .A0(n1519), .A1(DmP[10]), .B0(Add_Subt_result[13]), .B1(
n1267), .C0(Add_Subt_result[12]), .C1(n1319), .Y(n1284) );
AOI22X1TS U1799 ( .A0(n1345), .A1(n1284), .B0(n1263), .B1(n1342), .Y(n1279)
);
AOI22X1TS U1800 ( .A0(n1349), .A1(n1274), .B0(n662), .B1(n1279), .Y(n1266)
);
AOI22X1TS U1801 ( .A0(n1339), .A1(n1269), .B0(n1337), .B1(n1264), .Y(n1265)
);
NAND2X1TS U1802 ( .A(n1266), .B(n1265), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[12]) );
AOI222XLTS U1803 ( .A0(n1519), .A1(DmP[9]), .B0(Add_Subt_result[14]), .B1(
n1267), .C0(Add_Subt_result[11]), .C1(n1319), .Y(n1289) );
AOI22X1TS U1804 ( .A0(n1331), .A1(n1289), .B0(n1268), .B1(n1342), .Y(n1285)
);
AOI22X1TS U1805 ( .A0(n1349), .A1(n1279), .B0(n663), .B1(n1285), .Y(n1271)
);
AOI22X1TS U1806 ( .A0(n657), .A1(n1274), .B0(n1337), .B1(n1269), .Y(n1270)
);
NAND2X1TS U1807 ( .A(n1271), .B(n1270), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[11]) );
AOI21X1TS U1808 ( .A0(n1283), .A1(Add_Subt_result[10]), .B0(n1272), .Y(n1296) );
AOI22X1TS U1809 ( .A0(n1331), .A1(n1296), .B0(n1273), .B1(n1328), .Y(n1291)
);
AOI22X1TS U1810 ( .A0(n1327), .A1(n1285), .B0(n663), .B1(n1291), .Y(n1276)
);
AOI22X1TS U1811 ( .A0(n657), .A1(n1279), .B0(n1337), .B1(n1274), .Y(n1275)
);
NAND2X1TS U1812 ( .A(n1276), .B(n1275), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[10]) );
AOI21X1TS U1813 ( .A0(n1283), .A1(Add_Subt_result[9]), .B0(n1277), .Y(n1301)
);
AOI22X1TS U1814 ( .A0(n1331), .A1(n1301), .B0(n1278), .B1(n1328), .Y(n1297)
);
AOI22X1TS U1815 ( .A0(n1327), .A1(n1291), .B0(n1347), .B1(n1297), .Y(n1281)
);
AOI22X1TS U1816 ( .A0(n657), .A1(n1285), .B0(n1337), .B1(n1279), .Y(n1280)
);
NAND2X1TS U1817 ( .A(n1281), .B(n1280), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[9]) );
AOI21X1TS U1818 ( .A0(n1283), .A1(Add_Subt_result[8]), .B0(n1282), .Y(n1307)
);
AOI22X1TS U1819 ( .A0(n1331), .A1(n1307), .B0(n1284), .B1(n1328), .Y(n1302)
);
AOI22X1TS U1820 ( .A0(n1290), .A1(n1297), .B0(n1347), .B1(n1302), .Y(n1287)
);
AOI22X1TS U1821 ( .A0(n1339), .A1(n1291), .B0(n1337), .B1(n1285), .Y(n1286)
);
NAND2X1TS U1822 ( .A(n1287), .B(n1286), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[8]) );
AOI21X1TS U1823 ( .A0(n1341), .A1(Add_Subt_result[7]), .B0(n1288), .Y(n1312)
);
AOI22X1TS U1824 ( .A0(n1331), .A1(n1312), .B0(n1289), .B1(n1328), .Y(n1308)
);
AOI22X1TS U1825 ( .A0(n1290), .A1(n1302), .B0(n662), .B1(n1308), .Y(n1293)
);
AOI22X1TS U1826 ( .A0(n657), .A1(n1297), .B0(n1333), .B1(n1291), .Y(n1292)
);
NAND2X1TS U1827 ( .A(n1293), .B(n1292), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[7]) );
AOI21X1TS U1828 ( .A0(n1341), .A1(Add_Subt_result[6]), .B0(n1295), .Y(n1320)
);
AOI22X1TS U1829 ( .A0(n1331), .A1(n1320), .B0(n1296), .B1(n1328), .Y(n1315)
);
AOI22X1TS U1830 ( .A0(n1327), .A1(n1308), .B0(n662), .B1(n1315), .Y(n1299)
);
AOI22X1TS U1831 ( .A0(n1339), .A1(n1302), .B0(n1333), .B1(n1297), .Y(n1298)
);
NAND2X1TS U1832 ( .A(n1299), .B(n1298), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[6]) );
AOI21X1TS U1833 ( .A0(n1341), .A1(Add_Subt_result[5]), .B0(n1300), .Y(n1329)
);
AOI22X1TS U1834 ( .A0(n1331), .A1(n1329), .B0(n1301), .B1(n1328), .Y(n1324)
);
AOI22X1TS U1835 ( .A0(n1327), .A1(n1315), .B0(n663), .B1(n1324), .Y(n1304)
);
AOI22X1TS U1836 ( .A0(n1339), .A1(n1308), .B0(n1333), .B1(n1302), .Y(n1303)
);
NAND2X1TS U1837 ( .A(n1304), .B(n1303), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[5]) );
AOI21X1TS U1838 ( .A0(n1341), .A1(Add_Subt_result[4]), .B0(n1306), .Y(n1343)
);
AOI22X1TS U1839 ( .A0(n1331), .A1(n1343), .B0(n1307), .B1(n1328), .Y(n1332)
);
AOI22X1TS U1840 ( .A0(n1327), .A1(n1324), .B0(n1347), .B1(n1332), .Y(n1310)
);
AOI22X1TS U1841 ( .A0(n657), .A1(n1315), .B0(n1333), .B1(n1308), .Y(n1309)
);
NAND2X1TS U1842 ( .A(n1310), .B(n1309), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[4]) );
AOI22X1TS U1843 ( .A0(n1340), .A1(Add_Subt_result[22]), .B0(DmP[1]), .B1(
n1318), .Y(n1314) );
NAND2X1TS U1844 ( .A(Add_Subt_result[3]), .B(n1319), .Y(n1313) );
AOI32X1TS U1845 ( .A0(n1314), .A1(n1322), .A2(n1313), .B0(n1312), .B1(n1311),
.Y(n1336) );
AOI22X1TS U1846 ( .A0(n1327), .A1(n1332), .B0(n662), .B1(n1336), .Y(n1317)
);
AOI22X1TS U1847 ( .A0(n1339), .A1(n1324), .B0(n1333), .B1(n1315), .Y(n1316)
);
NAND2X1TS U1848 ( .A(n1317), .B(n1316), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[3]) );
AOI22X1TS U1849 ( .A0(n1340), .A1(Add_Subt_result[23]), .B0(DmP[0]), .B1(
n1318), .Y(n1323) );
NAND2X1TS U1850 ( .A(Add_Subt_result[2]), .B(n1319), .Y(n1321) );
AOI32X1TS U1851 ( .A0(n1323), .A1(n1322), .A2(n1321), .B0(n1320), .B1(n1328),
.Y(n1338) );
AOI22X1TS U1852 ( .A0(n1327), .A1(n1336), .B0(n663), .B1(n1338), .Y(n1326)
);
AOI22X1TS U1853 ( .A0(n1339), .A1(n1332), .B0(n1333), .B1(n1324), .Y(n1325)
);
NAND2X1TS U1854 ( .A(n1326), .B(n1325), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[2]) );
AOI22X1TS U1855 ( .A0(n1327), .A1(n1338), .B0(n657), .B1(n1336), .Y(n1335)
);
AOI22X1TS U1856 ( .A0(n1341), .A1(Add_Subt_result[1]), .B0(n1340), .B1(
Add_Subt_result[24]), .Y(n1330) );
AOI22X1TS U1857 ( .A0(n1331), .A1(n1330), .B0(n1329), .B1(n1328), .Y(n1348)
);
AOI22X1TS U1858 ( .A0(n1347), .A1(n1348), .B0(n1333), .B1(n1332), .Y(n1334)
);
NAND2X1TS U1859 ( .A(n1335), .B(n1334), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[1]) );
AOI22X1TS U1860 ( .A0(n1339), .A1(n1338), .B0(n1337), .B1(n1336), .Y(n1351)
);
AOI22X1TS U1861 ( .A0(n1341), .A1(Add_Subt_result[0]), .B0(
Add_Subt_result[25]), .B1(n1340), .Y(n1344) );
AOI22X1TS U1862 ( .A0(n1345), .A1(n1344), .B0(n1343), .B1(n1342), .Y(n1346)
);
AOI22X1TS U1863 ( .A0(n1349), .A1(n1348), .B0(n1347), .B1(n1346), .Y(n1350)
);
NAND2X1TS U1864 ( .A(n1351), .B(n1350), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[0]) );
OAI2BB2XLTS U1865 ( .B0(n1524), .B1(n1359), .A0N(final_result_ieee[22]),
.A1N(n1405), .Y(n13) );
OAI2BB2XLTS U1866 ( .B0(n1502), .B1(n1359), .A0N(final_result_ieee[21]),
.A1N(n1405), .Y(n16) );
OA22X1TS U1867 ( .A0(n1374), .A1(n1502), .B0(n1352), .B1(n653), .Y(n1354) );
AOI22X1TS U1868 ( .A0(n1379), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[28]), .B0(n1356), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .Y(n1353) );
OAI2BB2XLTS U1869 ( .B0(n1503), .B1(n1359), .A0N(final_result_ieee[20]),
.A1N(n1405), .Y(n20) );
OA22X1TS U1870 ( .A0(n1374), .A1(n1503), .B0(n1355), .B1(n1371), .Y(n1358)
);
AOI22X1TS U1871 ( .A0(n1379), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .B0(n1356), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .Y(n1357) );
CLKBUFX2TS U1872 ( .A(n1359), .Y(n1404) );
OAI2BB2XLTS U1873 ( .B0(n1504), .B1(n1404), .A0N(final_result_ieee[19]),
.A1N(n1405), .Y(n24) );
OA22X1TS U1874 ( .A0(n1374), .A1(n1504), .B0(n1360), .B1(n653), .Y(n1362) );
AOI22X1TS U1875 ( .A0(n1379), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .B0(n1380), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .Y(n1361) );
OAI2BB2XLTS U1876 ( .B0(n1505), .B1(n1404), .A0N(final_result_ieee[18]),
.A1N(n1405), .Y(n28) );
OA22X1TS U1877 ( .A0(n1374), .A1(n1505), .B0(n1363), .B1(n653), .Y(n1365) );
AOI22X1TS U1878 ( .A0(n1379), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .B0(n1380), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .Y(n1364) );
INVX2TS U1879 ( .A(n1366), .Y(n1393) );
OAI2BB2XLTS U1880 ( .B0(n1476), .B1(n1404), .A0N(final_result_ieee[17]),
.A1N(n1393), .Y(n32) );
OA22X1TS U1881 ( .A0(n1374), .A1(n1476), .B0(n1367), .B1(n653), .Y(n1370) );
AOI22X1TS U1882 ( .A0(n1379), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .B0(n1380), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .Y(n1369) );
OAI2BB2XLTS U1883 ( .B0(n1477), .B1(n1404), .A0N(final_result_ieee[16]),
.A1N(n1393), .Y(n36) );
OAI2BB2XLTS U1884 ( .B0(n1478), .B1(n1404), .A0N(final_result_ieee[15]),
.A1N(n1393), .Y(n40) );
OAI2BB2XLTS U1885 ( .B0(n1463), .B1(n1404), .A0N(final_result_ieee[14]),
.A1N(n1393), .Y(n44) );
OAI2BB2XLTS U1886 ( .B0(n1464), .B1(n1403), .A0N(final_result_ieee[13]),
.A1N(n1393), .Y(n48) );
AOI22X1TS U1887 ( .A0(n660), .A1(Sgf_normalized_result[15]), .B0(n1379),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(n1378) );
NOR2X1TS U1888 ( .A(n653), .B(n1372), .Y(n1396) );
NOR2X1TS U1889 ( .A(n655), .B(n1372), .Y(n1397) );
AOI22X1TS U1890 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(
n1396), .B0(Barrel_Shifter_module_Mux_Array_Data_array[49]), .B1(n1397), .Y(n1377) );
NAND2X1TS U1891 ( .A(n1375), .B(n1374), .Y(n1400) );
NAND2X1TS U1892 ( .A(n1380), .B(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(n1376) );
OAI2BB2XLTS U1893 ( .B0(n1460), .B1(n1403), .A0N(final_result_ieee[8]),
.A1N(n1393), .Y(n50) );
AOI22X1TS U1894 ( .A0(n661), .A1(Sgf_normalized_result[10]), .B0(n1379),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(n1383) );
AOI22X1TS U1895 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(
n1397), .B0(Barrel_Shifter_module_Mux_Array_Data_array[49]), .B1(n1396), .Y(n1382) );
NAND2X1TS U1896 ( .A(n1380), .B(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .Y(n1381) );
OAI2BB2XLTS U1897 ( .B0(n1465), .B1(n1403), .A0N(final_result_ieee[12]),
.A1N(n1393), .Y(n52) );
AOI22X1TS U1898 ( .A0(n659), .A1(Sgf_normalized_result[14]), .B0(n1394),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(n1386) );
AOI22X1TS U1899 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[45]), .A1(
n1396), .B0(Barrel_Shifter_module_Mux_Array_Data_array[48]), .B1(n1397), .Y(n1385) );
NAND2X1TS U1900 ( .A(n1398), .B(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(n1384) );
OAI2BB2XLTS U1901 ( .B0(n1461), .B1(n1403), .A0N(final_result_ieee[9]),
.A1N(n1393), .Y(n54) );
AOI22X1TS U1902 ( .A0(n660), .A1(Sgf_normalized_result[11]), .B0(n1394),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(n1389) );
AOI22X1TS U1903 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[45]), .A1(
n1397), .B0(Barrel_Shifter_module_Mux_Array_Data_array[48]), .B1(n1396), .Y(n1388) );
NAND2X1TS U1904 ( .A(n1398), .B(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(n1387) );
OAI2BB2XLTS U1905 ( .B0(n1466), .B1(n1403), .A0N(final_result_ieee[11]),
.A1N(n1393), .Y(n56) );
AOI22X1TS U1906 ( .A0(n661), .A1(Sgf_normalized_result[13]), .B0(n1394),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n1392) );
AOI22X1TS U1907 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1(
n1396), .B0(Barrel_Shifter_module_Mux_Array_Data_array[47]), .B1(n1397), .Y(n1391) );
NAND2X1TS U1908 ( .A(n1398), .B(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .Y(n1390) );
OAI2BB2XLTS U1909 ( .B0(n1462), .B1(n1403), .A0N(final_result_ieee[10]),
.A1N(n1393), .Y(n58) );
AOI22X1TS U1910 ( .A0(n659), .A1(Sgf_normalized_result[12]), .B0(n1394),
.B1(Barrel_Shifter_module_Mux_Array_Data_array[39]), .Y(n1402) );
AOI22X1TS U1911 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1(
n1397), .B0(Barrel_Shifter_module_Mux_Array_Data_array[47]), .B1(n1396), .Y(n1401) );
NAND2X1TS U1912 ( .A(n1398), .B(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .Y(n1399) );
OA22X1TS U1913 ( .A0(exp_oper_result[7]), .A1(n1403), .B0(n1407), .B1(
final_result_ieee[30]), .Y(n60) );
OA22X1TS U1914 ( .A0(exp_oper_result[5]), .A1(n1403), .B0(n1407), .B1(
final_result_ieee[28]), .Y(n62) );
OA22X1TS U1915 ( .A0(n1407), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n1403), .Y(n63) );
OA22X1TS U1916 ( .A0(n1407), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n1404), .Y(n64) );
OA22X1TS U1917 ( .A0(n1407), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n1404), .Y(n65) );
OA22X1TS U1918 ( .A0(n1407), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n1404), .Y(n66) );
OA22X1TS U1919 ( .A0(n1407), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n1404), .Y(n67) );
AOI21X1TS U1920 ( .A0(n1453), .A1(n1529), .B0(overflow_flag), .Y(n1406) );
AO22XLTS U1921 ( .A0(n1407), .A1(n1406), .B0(n1405), .B1(
final_result_ieee[31]), .Y(n68) );
AOI21X1TS U1922 ( .A0(n1525), .A1(Add_Subt_result[20]), .B0(
Add_Subt_result[22]), .Y(n1408) );
AOI2BB1XLTS U1923 ( .A0N(n1408), .A1N(Add_Subt_result[23]), .B0(
Add_Subt_result[24]), .Y(n1413) );
INVX2TS U1924 ( .A(n1409), .Y(n1412) );
AOI31XLTS U1925 ( .A0(Add_Subt_result[6]), .A1(n1415), .A2(n1522), .B0(n1414), .Y(n1421) );
AOI31XLTS U1926 ( .A0(n1417), .A1(Add_Subt_result[8]), .A2(n1528), .B0(n1416), .Y(n1419) );
AOI32X1TS U1927 ( .A0(n1421), .A1(n1420), .A2(n1419), .B0(n1531), .B1(n1418),
.Y(n73) );
CLKBUFX2TS U1928 ( .A(n1431), .Y(n1432) );
CLKBUFX2TS U1929 ( .A(n1431), .Y(n1428) );
CLKBUFX2TS U1930 ( .A(n1430), .Y(n1435) );
INVX2TS U1931 ( .A(n1435), .Y(n1423) );
INVX2TS U1932 ( .A(n1435), .Y(n1424) );
CLKBUFX2TS U1933 ( .A(n1431), .Y(n1425) );
CLKBUFX2TS U1934 ( .A(n1431), .Y(n1426) );
CLKBUFX2TS U1935 ( .A(n1431), .Y(n1429) );
OAI2BB2XLTS U1936 ( .B0(n1430), .B1(n1518), .A0N(n1429), .A1N(Data_Y[17]),
.Y(n141) );
OAI2BB2XLTS U1937 ( .B0(n1433), .B1(n1486), .A0N(n1432), .A1N(Data_Y[24]),
.Y(n162) );
OAI2BB2XLTS U1938 ( .B0(n1428), .B1(n1447), .A0N(n1432), .A1N(Data_X[7]),
.Y(n190) );
OAI2BB2XLTS U1939 ( .B0(n1428), .B1(n1482), .A0N(n1432), .A1N(Data_X[8]),
.Y(n191) );
OAI2BB2XLTS U1940 ( .B0(n1428), .B1(n1488), .A0N(n1432), .A1N(Data_X[9]),
.Y(n192) );
OAI2BB2XLTS U1941 ( .B0(n1428), .B1(n1506), .A0N(n1432), .A1N(Data_X[10]),
.Y(n193) );
OAI2BB2XLTS U1942 ( .B0(n1428), .B1(n1481), .A0N(n1429), .A1N(Data_X[11]),
.Y(n194) );
OAI2BB2XLTS U1943 ( .B0(n1435), .B1(n1444), .A0N(n1429), .A1N(Data_X[12]),
.Y(n195) );
OAI2BB2XLTS U1944 ( .B0(n1435), .B1(n1442), .A0N(n1429), .A1N(Data_X[13]),
.Y(n196) );
OAI2BB2XLTS U1945 ( .B0(n1430), .B1(n1487), .A0N(n1429), .A1N(Data_X[14]),
.Y(n197) );
OAI2BB2XLTS U1946 ( .B0(n1435), .B1(n1479), .A0N(n1429), .A1N(Data_X[15]),
.Y(n198) );
OAI2BB2XLTS U1947 ( .B0(n1435), .B1(n1509), .A0N(n1429), .A1N(Data_X[16]),
.Y(n199) );
OAI2BB2XLTS U1948 ( .B0(n1430), .B1(n1494), .A0N(n1429), .A1N(Data_X[17]),
.Y(n200) );
OAI2BB2XLTS U1949 ( .B0(n1430), .B1(n1484), .A0N(n1429), .A1N(Data_X[18]),
.Y(n201) );
OAI2BB2XLTS U1950 ( .B0(n1430), .B1(n1436), .A0N(n1429), .A1N(Data_X[19]),
.Y(n202) );
CLKBUFX2TS U1951 ( .A(n1431), .Y(n1434) );
OAI2BB2XLTS U1952 ( .B0(n1435), .B1(n1445), .A0N(n1434), .A1N(Data_X[20]),
.Y(n203) );
OAI2BB2XLTS U1953 ( .B0(n1433), .B1(n1480), .A0N(n1434), .A1N(Data_X[21]),
.Y(n204) );
OAI2BB2XLTS U1954 ( .B0(n1433), .B1(n1446), .A0N(n1434), .A1N(Data_X[22]),
.Y(n205) );
OAI2BB2XLTS U1955 ( .B0(n1433), .B1(n1483), .A0N(n1434), .A1N(Data_X[23]),
.Y(n206) );
OAI2BB2XLTS U1956 ( .B0(n1433), .B1(n1443), .A0N(n1434), .A1N(Data_X[25]),
.Y(n208) );
OAI2BB2XLTS U1957 ( .B0(n1433), .B1(n1485), .A0N(n1434), .A1N(Data_X[26]),
.Y(n209) );
OAI2BB2XLTS U1958 ( .B0(n1433), .B1(n1489), .A0N(n1434), .A1N(Data_X[27]),
.Y(n210) );
OAI2BB2XLTS U1959 ( .B0(n1433), .B1(n1501), .A0N(n1434), .A1N(Data_X[28]),
.Y(n211) );
OAI2BB2XLTS U1960 ( .B0(n1435), .B1(n1441), .A0N(n1434), .A1N(Data_X[29]),
.Y(n212) );
OAI2BB2XLTS U1961 ( .B0(n1435), .B1(n1440), .A0N(n1434), .A1N(Data_X[30]),
.Y(n213) );
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
|
////////////////////////////////////////////////////////////////
// File: vga_sync.v
// Author: BBB (based on Terasic module VGA_Ctrl.v)
// About: Controls VGA signals
////////////////////////////////////////////////////////////////
module vga_sync(
input wire clock,
input wire aresetn,
input wire [2:0] color,
output wire vga_clk,
output reg [7:0] R,
output reg [7:0] G,
output reg [7:0] B,
output reg h_sync,
output reg v_sync,
output wire blank_n,
output wire sync_n
);
/*
VGA Frequency: 72Hz
VGA Resolution: 800x600
VGA Pixel Clock: 50MHz
*/
//Horizontal Parameters
localparam H_FRONT = 56;
localparam H_SYNC = 120;
localparam H_BACK = 64;
localparam H_ACT = 800;
localparam H_BLANK = H_FRONT+H_SYNC+H_BACK;
localparam H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT;
localparam H_TOTAL_WIDTH = 10;
//Vertical Parameters
localparam V_FRONT = 37;
localparam V_SYNC = 6;
localparam V_BACK = 23;
localparam V_ACT = 600;
localparam V_BLANK = V_FRONT+V_SYNC+V_BACK;
localparam V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT;
localparam V_TOTAL_WIDTH = 10;
//Clock
assign vga_clk = ~clock;
//Position Info
reg [(H_TOTAL_WIDTH-1):0] hor_pos;
reg [(V_TOTAL_WIDTH-1):0] ver_pos;
//Horizontal Data
always @(posedge clock) begin
if (~aresetn)
begin
hor_pos <= 'd0;
h_sync <= 1'b0;
end
else
begin
if (hor_pos < H_TOTAL) hor_pos <= hor_pos + 1;
else hor_pos <= 0;
if (hor_pos == H_FRONT-1) h_sync <= 1'b1;
if (hor_pos == H_FRONT+H_SYNC-1) h_sync <= 1'b0;
end
end
//Vertical Data
always @(posedge h_sync) begin
if (~aresetn)
begin
ver_pos <= 'd0;
v_sync <= 1'b0;
end
else
begin
if (ver_pos < V_TOTAL) ver_pos <= ver_pos + 1;
else ver_pos <= 0;
if (ver_pos == V_FRONT-1) v_sync <= 1'b1;
if (ver_pos == V_FRONT+V_SYNC-1) v_sync <= 1'b0;
end
end
//RGB Data
always @(posedge clock) begin
if (~aresetn)
begin
R <= 8'd0;
B <= 8'd0;
G <= 8'd0;
end
else if ((hor_pos < H_BLANK) | (ver_pos < V_BLANK))
begin
R <= 8'd0;
B <= 8'd0;
G <= 8'd0;
end
else
begin
if (color == 3'b100)
begin
R <= hor_pos[7:0];
G <= ver_pos[7:0];
B <= hor_pos[7:0];
end
else if (color == 3'b110)
begin
R <= 8'd255;
G <= 8'd0;
B <= 8'd0;
end
else if (color == 3'b101)
begin
R <= 8'd0;
G <= 8'd255;
B <= 8'd0;
end
else if (color == 3'b011)
begin
R <= 8'd0;
G <= 8'd0;
B <= 8'd255;
end
else
begin
R <= R;
G <= G;
B <= B;
end
end
end
//Blank (ADV7123)
assign blank_n = ~((hor_pos < H_BLANK)||(ver_pos < V_BLANK));
//Sync (ADV7123)
assign sync_n = 1'b1;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_3_0_7vx.v
// Version : 4.1
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : <CoreName>_pcie_3_0_7vx.v //
// Description : Instantiates PCIe Top Level and GT top level and connects //
// them via PIPE interface. //
// //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_3_0_7vx.v //
// gt_top.v //
// pcie_tx_elec_idle_filter_7vx.v //
// pipe_clock.v //
// pipe_reset.v //
// qpll_reset.v //
// * Generate GTHE2_CHANNEL for every lane. //
// pipe_user.v //
// pipe_rate.v //
// pipe_sync.v //
// pipe_drp.v //
// pipe_eq.v //
// rxeq_scan.v //
// gt_wrapper.v //
// GTHE2_CHANNEL //
// GTHE2_COMMON //
// * Generate GTHE2_COMMON for every quad. //
// qpll_drp.v //
// qpll_wrapper.v //
// pcie_top.v //
// pcie_init_ctrl.v //
// pcie_tlp_tph_tbl_7vx.v //
// pcie_7vx.v //
// PCIE_3_0 //
// pcie_bram_7vx.v //
// pcie_bram_7vx_rep.v //
// pcie_bram_7vx_rep_8k.v //
// pcie_bram_7vx_req.v //
// pcie_bram_7vx_8k.v //
// pcie_bram_7vx_cpl.v //
// pcie_bram_7vx_8k.v //
// pcie_bram_7vx_16k.v //
// pcie_pipe_pipeline.v //
// pcie_pipe_lane.v //
// pcie_pipe_misc.v //
// tandem_cpler.v //
// tandem_cpler_ctl_arb.v //
// PIO_RX_ENGINE.v //
// PIO_TX_ENGINE.v //
// PIO_INTR_CTRL.v //
// Fast_PCIe_config_top.v //
// pr_loader.v //
// PIO_FPC.v //
// PIO_TO_CTRL_FPC.v //
// PIO_EP_FPC.v //
// PIO_EP_MA_FPC.v //
// PIO_TX_ENG_FPC.v //
// PIO_RX_ENG_FPC.v //
// icap_access.v //
// data_transfer.v //
// fastConfigFIFO.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_3_0_7vx # (
parameter integer TCQ = 100,
parameter component_name = "pcie3_7x_v4_1_1",
// The following parameters can be changed to configure the link to a different width/speed.
// See Product Guide for details: Table "Data Width and Clock Frequency Settings for the Client Interfaces"
parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4, // Maximum Link Speed
parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8, // Maximum Link Width
parameter integer USER_CLK2_FREQ = 4, // AXI Client Interface Frequency
parameter C_DATA_WIDTH = 256, // AXI Client Interface Width
parameter integer PIPE_PIPELINE_STAGES = 0, // PIPE Interface pipeline: 0-None, 1- single pipeline, 2-double pipeline
parameter PIPE_SIM = "FALSE", // No effect in RTL using this parameter.
parameter PIPE_SIM_MODE = "FALSE", // Use this paramter to control PIPE mode simulation logic; in-side this module
parameter EXT_PIPE_SIM = "FALSE",
//GT Parameters
parameter REF_CLK_FREQ = 0, // Reference Clock Frequency
parameter PCIE_EXT_CLK = "TRUE",
parameter PCIE_EXT_GT_COMMON = "FALSE",
parameter EXT_CH_GT_DRP = "FALSE", // PCIe external CH DRP
parameter PCIE_DRP = "FALSE", // PCIe DRP
parameter TRANSCEIVER_CTRL_STATUS_PORTS = "FALSE",
parameter PCIE_TXBUF_EN = "FALSE",
parameter PCIE_GT_DEVICE = "GTH",
parameter integer PCIE_CHAN_BOND = 0,
parameter PCIE_CHAN_BOND_EN = "FALSE",
parameter PCIE_USE_MODE = "2.0",
parameter PCIE_LPM_DFE = "LPM",
parameter integer PCIE_LINK_SPEED = 3,
parameter integer KEEP_WIDTH = (C_DATA_WIDTH/32),
parameter TX_MARGIN_FULL_0 = 7'b1001111,
parameter TX_MARGIN_FULL_1 = 7'b1001110,
parameter TX_MARGIN_FULL_2 = 7'b1001101,
parameter TX_MARGIN_FULL_3 = 7'b1001100,
parameter TX_MARGIN_FULL_4 = 7'b1000011,
parameter TX_MARGIN_LOW_0 = 7'b1000101,
parameter TX_MARGIN_LOW_1 = 7'b1000110,
parameter TX_MARGIN_LOW_2 = 7'b1000011,
parameter TX_MARGIN_LOW_3 =7'b1000010,
parameter TX_MARGIN_LOW_4 =7'b1000000,
// PCIe 3_0 Core parameters
parameter ARI_CAP_ENABLE = "FALSE",
parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_CC_PARITY_CHK = "FALSE",
parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE",
parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h2FFFF,
parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE",
parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_RC_STRADDLE = "FALSE",
parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_RQ_PARITY_CHK = "FALSE",
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [1:0] GEN3_PCS_AUTO_REALIGN = 2'h1,
parameter GEN3_PCS_RX_ELECIDLE_INTERNAL = "TRUE",
parameter [8:0] LL_ACK_TIMEOUT = 9'h000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000,
parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000,
parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000,
parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000,
parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0,
parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA,
parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE",
parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE",
parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000,
parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000,
parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00,
parameter [3:0] PF0_ARI_CAP_VER = 4'h1,
parameter [4:0] PF0_BAR0_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR0_CONTROL = 3'h4,
parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00,
parameter [2:0] PF0_BAR1_CONTROL = 3'h0,
parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR2_CONTROL = 3'h4,
parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR3_CONTROL = 3'h0,
parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR4_CONTROL = 3'h4,
parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR5_CONTROL = 3'h0,
parameter [7:0] PF0_BIST_REGISTER = 8'h00,
parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50,
parameter [23:0] PF0_CLASS_CODE = 24'h000000,
parameter [15:0] PF0_VENDOR_ID = 16'h10EE,
parameter [15:0] PF0_DEVICE_ID = 16'h0007,
parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE",
parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE",
parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE",
parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE",
parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE",
parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0,
parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE",
parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0,
parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE",
parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000,
parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE",
parameter VF0_TPHR_CAP_ENABLE = "FALSE",
parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'b010,
parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 3'b10,
parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF0_TPHR_CAP_VER = 4'h1,
parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE",
parameter VF1_TPHR_CAP_ENABLE = "FALSE",
parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'b010,
parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 3'b10,
parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF1_TPHR_CAP_VER = 4'h1,
parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE",
parameter VF2_TPHR_CAP_ENABLE = "FALSE",
parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'b010,
parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 3'b10,
parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF2_TPHR_CAP_VER = 4'h1,
parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE",
parameter VF3_TPHR_CAP_ENABLE = "FALSE",
parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'b010,
parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 3'b10,
parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF3_TPHR_CAP_VER = 4'h1,
parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE",
parameter VF4_TPHR_CAP_ENABLE = "FALSE",
parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'b010,
parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 3'b10,
parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF4_TPHR_CAP_VER = 4'h1,
parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE",
parameter VF5_TPHR_CAP_ENABLE = "FALSE",
parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'b010,
parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 3'b10,
parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF5_TPHR_CAP_VER = 4'h1,
parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
parameter [3:0] PF0_DPA_CAP_VER = 4'h1,
parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C,
parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
parameter PF0_EXPANSION_ROM_ENABLE = "FALSE",
parameter [7:0] PF0_INTERRUPT_LINE = 8'h00,
parameter [2:0] PF0_INTERRUPT_PIN = 3'h1,
parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7,
parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000,
parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000,
parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000,
parameter [3:0] PF0_LTR_CAP_VER = 4'h1,
parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00,
parameter integer PF0_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer PF0_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00,
parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000,
parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
parameter [3:0] PF0_PB_CAP_VER = 4'h1,
parameter [7:0] PF0_PM_CAP_ID = 8'h01,
parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00,
parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE",
parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE",
parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE",
parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE",
parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3,
parameter PF0_PM_CSR_NOSOFTRESET = "TRUE",
parameter PF0_RBAR_CAP_ENABLE = "FALSE",
parameter [2:0] PF0_RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] PF0_RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] PF0_RBAR_CAP_INDEX2 = 3'h0,
parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000,
parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000,
parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000,
parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000,
parameter [3:0] PF0_RBAR_CAP_VER = 4'h1,
parameter [2:0] PF0_RBAR_NUM = 3'h1,
parameter [7:0] PF0_REVISION_ID = 8'h00,
parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4,
parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0,
parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4,
parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0,
parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4,
parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0,
parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000,
parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000,
parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000,
parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1,
parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000,
parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000,
parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000,
parameter [15:0] PF0_SUBSYSTEM_VENDOR_ID = 16'h0000,
parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000,
parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE",
parameter PF0_TPHR_CAP_ENABLE = "TRUE",
parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h300,
parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'b010,
parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'b10,
parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] PF0_TPHR_CAP_VER = 4'h1,
parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000,
parameter [3:0] PF0_VC_CAP_VER = 4'h1,
parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000,
parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000,
parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00,
parameter [4:0] PF1_BAR0_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR0_CONTROL = 3'h4,
parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00,
parameter [2:0] PF1_BAR1_CONTROL = 3'h0,
parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR2_CONTROL = 3'h4,
parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR3_CONTROL = 3'h0,
parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR4_CONTROL = 3'h4,
parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR5_CONTROL = 3'h0,
parameter [7:0] PF1_BIST_REGISTER = 8'h00,
parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50,
parameter [23:0] PF1_CLASS_CODE = 24'h000000,
parameter [15:0] PF1_DEVICE_ID = 16'h0000,
parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000,
parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
parameter [3:0] PF1_DPA_CAP_VER = 4'h1,
parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C,
parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
parameter PF1_EXPANSION_ROM_ENABLE = "FALSE",
parameter [7:0] PF1_INTERRUPT_LINE = 8'h00,
parameter [2:0] PF1_INTERRUPT_PIN = 3'h1,
parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00,
parameter integer PF1_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer PF1_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00,
parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000,
parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
parameter [3:0] PF1_PB_CAP_VER = 4'h1,
parameter [7:0] PF1_PM_CAP_ID = 8'h01,
parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3,
parameter PF1_RBAR_CAP_ENABLE = "FALSE",
parameter [2:0] PF1_RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] PF1_RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] PF1_RBAR_CAP_INDEX2 = 3'h0,
parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000,
parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000,
parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000,
parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000,
parameter [3:0] PF1_RBAR_CAP_VER = 4'h1,
parameter [2:0] PF1_RBAR_NUM = 3'h1,
parameter [7:0] PF1_REVISION_ID = 8'h00,
parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4,
parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0,
parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4,
parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0,
parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4,
parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0,
parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000,
parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000,
parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000,
parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1,
parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000,
parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000,
parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000,
parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000,
parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "FALSE",
parameter PF1_TPHR_CAP_ENABLE = "TRUE",
parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h300,
parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'b010,
parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'b10,
parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] PF1_TPHR_CAP_VER = 4'h1,
parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE",
parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE",
parameter PL_DISABLE_SCRAMBLING = "FALSE",
parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE",
parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE",
parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE",
parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02,
parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1,
parameter PL_EQ_BYPASS_PHASE23 = "FALSE",
parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE",
parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3400,
parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3400,
parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3400,
parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3400,
parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3400,
parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3400,
parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3400,
parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3400,
parameter integer PL_N_FTS_COMCLK_GEN1 = 255,
parameter integer PL_N_FTS_COMCLK_GEN2 = 255,
parameter integer PL_N_FTS_COMCLK_GEN3 = 255,
parameter integer PL_N_FTS_GEN1 = 255,
parameter integer PL_N_FTS_GEN2 = 255,
parameter integer PL_N_FTS_GEN3 = 255,
parameter PL_UPSTREAM_FACING = "TRUE",
parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC,
parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00ABE,
parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE",
parameter [31:0] PM_L1_REENTRY_DELAY = 32'h000061A8,
parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0,
parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064,
parameter SIM_VERSION = "1.0",
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter SRIOV_CAP_ENABLE = "FALSE",
parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20,
parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h3211620,
parameter [11:0] TL_CREDITS_CD = 12'h3E0,
parameter [7:0] TL_CREDITS_CH = 8'h20,
parameter [11:0] TL_CREDITS_NPD = 12'h028,
parameter [7:0] TL_CREDITS_NPH = 8'h20,
parameter [11:0] TL_CREDITS_PD = 12'h198,
parameter [7:0] TL_CREDITS_PH = 8'h20,
parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE",
parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE",
parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE",
parameter TL_LEGACY_MODE_ENABLE = "FALSE",
parameter TL_PF_ENABLE_REG = "FALSE",
parameter TL_TAG_MGMT_ENABLE = "TRUE",
parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50,
parameter integer VF0_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF0_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF0_PM_CAP_ID = 8'h01,
parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3,
parameter integer VF1_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF1_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF1_PM_CAP_ID = 8'h01,
parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3,
parameter integer VF2_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF2_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF2_PM_CAP_ID = 8'h01,
parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3,
parameter integer VF3_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF3_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF3_PM_CAP_ID = 8'h01,
parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3,
parameter integer VF4_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF4_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF4_PM_CAP_ID = 8'h01,
parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3,
parameter integer VF5_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF5_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF5_PM_CAP_ID = 8'h01,
parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3,
parameter IMPL_TARGET = "HARD",
parameter NO_DECODE_LOGIC = "FALSE",
parameter COMPLETION_SPACE = "16KB",
// Tandem PROM/PCIe Parameters
parameter PCIE_FAST_CONFIG = "NONE", // NONE, TANDEM_PROM, TANDEM_PCIE
//Parameters below are used during GU Customization. Do not change.
parameter gen_x0y0_ucf = "FALSE",
parameter gen_x0y1_ucf = "FALSE",
parameter gen_x0y2_ucf = "FALSE",
parameter gen_x0y3_ucf = "FALSE",
parameter pcie_blk_locn = 0,
parameter silicon_revision = "GES",
parameter xlnx_ref_board = 0,
parameter MSI_EN = "TRUE",
parameter MSIX_EN = "FALSE",
parameter SHARED_LOGIC_IN_CORE = "FALSE",
parameter TX_FC_IF = "FALSE",
parameter CFG_FC_IF = "FALSE",
parameter CFG_EXT_IF = "FALSE",
parameter CFG_STATUS_IF = "FALSE",
parameter PER_FUNC_STATUS_IF = "FALSE",
parameter CFG_MGMT_IF = "FALSE",
parameter RCV_MSG_IF = "FALSE",
parameter CFG_TX_MSG_IF = "FALSE",
parameter CFG_CTL_IF = "FALSE",
parameter EXT_STARTUP_PRIMITIVE = "FALSE",
parameter EXT_PIPE_INTERFACE = "FALSE",
parameter POWER_DOWN = "FALSE",
parameter PCIE_ASYNC_EN = "FALSE",
parameter DEV_PORT_TYPE = 0
) (
//----------------------------------------------------------------------------------------------------------------//
// 1. PCI Express (pci_exp) Interface //
//----------------------------------------------------------------------------------------------------------------//
// Tx
output [(PL_LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txn,
output [(PL_LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_txp,
// Rx
input [(PL_LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxn,
input [(PL_LINK_CAP_MAX_LINK_WIDTH-1):0] pci_exp_rxp,
//----------------------------------------------------------------------------------------------------------------//
// 2. Clock & GT COMMON Sharing Interface //
//----------------------------------------------------------------------------------------------------------------//
// Shared Logic Internal
output int_pclk_out_slave,
output int_pipe_rxusrclk_out,
output [(PL_LINK_CAP_MAX_LINK_WIDTH-1):0] int_rxoutclk_out,
output int_dclk_out,
output int_userclk1_out,
output int_userclk2_out,
output int_oobclk_out,
output [1:0] int_qplllock_out,
output [1:0] int_qplloutclk_out,
output [1:0] int_qplloutrefclk_out,
input [(PL_LINK_CAP_MAX_LINK_WIDTH-1):0] int_pclk_sel_slave,
// Shared Logic External Clock
input pipe_pclk_in,
input pipe_rxusrclk_in,
input [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_rxoutclk_in,
input pipe_dclk_in,
input pipe_userclk1_in,
input pipe_userclk2_in,
input pipe_oobclk_in,
input pipe_mmcm_lock_in,
output pipe_txoutclk_out,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_rxoutclk_out,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_pclk_sel_out,
output pipe_gen3_out,
// Shared Logic External GT COMMON
input [11:0] qpll_drp_crscode,
input [17:0] qpll_drp_fsm,
input [1:0] qpll_drp_done,
input [1:0] qpll_drp_reset,
input [1:0] qpll_qplllock,
input [1:0] qpll_qplloutclk,
input [1:0] qpll_qplloutrefclk,
output qpll_qplld,
output [1:0] qpll_qpllreset,
output qpll_drp_clk,
output qpll_drp_rst_n,
output qpll_drp_ovrd,
output qpll_drp_gen3,
output qpll_drp_start,
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
output user_clk,
output reg user_reset,
output user_lnk_up,
output user_app_rdy,
input s_axis_rq_tlast,
input [C_DATA_WIDTH-1:0] s_axis_rq_tdata,
input [59:0] s_axis_rq_tuser,
input [KEEP_WIDTH-1:0] s_axis_rq_tkeep,
output [3:0] s_axis_rq_tready,
input s_axis_rq_tvalid,
output [C_DATA_WIDTH-1:0] m_axis_rc_tdata,
output [74:0] m_axis_rc_tuser,
output m_axis_rc_tlast,
output [KEEP_WIDTH-1:0] m_axis_rc_tkeep,
output m_axis_rc_tvalid,
input m_axis_rc_tready,
output [C_DATA_WIDTH-1:0] m_axis_cq_tdata,
output [84:0] m_axis_cq_tuser,
output m_axis_cq_tlast,
output [KEEP_WIDTH-1:0] m_axis_cq_tkeep,
output m_axis_cq_tvalid,
input m_axis_cq_tready,
input [C_DATA_WIDTH-1:0] s_axis_cc_tdata,
input [32:0] s_axis_cc_tuser,
input s_axis_cc_tlast,
input [KEEP_WIDTH-1:0] s_axis_cc_tkeep,
input s_axis_cc_tvalid,
output [3:0] s_axis_cc_tready,
output [3:0] pcie_rq_seq_num,
output pcie_rq_seq_num_vld,
output [5:0] pcie_rq_tag,
output pcie_rq_tag_vld,
output [1:0] pcie_tfc_nph_av,
output [1:0] pcie_tfc_npd_av,
input pcie_cq_np_req,
output [5:0] pcie_cq_np_req_count,
//----------------------------------------------------------------------------------------------------------------//
// 4. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
//----------------------------------------------------------------------------------------------------------------//
// EP and RP //
//----------------------------------------------------------------------------------------------------------------//
output cfg_phy_link_down,
output [1:0] cfg_phy_link_status,
output [3:0] cfg_negotiated_width,
output [2:0] cfg_current_speed,
output [2:0] cfg_max_payload,
output [2:0] cfg_max_read_req,
output [7:0] cfg_function_status,
output [5:0] cfg_function_power_state,
output [11:0] cfg_vf_status,
output [17:0] cfg_vf_power_state,
output [1:0] cfg_link_power_state,
// Management Interface
input [18:0] cfg_mgmt_addr,
input cfg_mgmt_write,
input [31:0] cfg_mgmt_write_data,
input [3:0] cfg_mgmt_byte_enable,
input cfg_mgmt_read,
output [31:0] cfg_mgmt_read_data,
output cfg_mgmt_read_write_done,
input cfg_mgmt_type1_cfg_reg_access,
// Error Reporting Interface
output cfg_err_cor_out,
output cfg_err_nonfatal_out,
output cfg_err_fatal_out,
// output cfg_local_error,
output cfg_ltr_enable,
output [5:0] cfg_ltssm_state,
output [1:0] cfg_rcb_status,
output [1:0] cfg_dpa_substate_change,
output [1:0] cfg_obff_enable,
output cfg_pl_status_change,
output [1:0] cfg_tph_requester_enable,
output [5:0] cfg_tph_st_mode,
output [5:0] cfg_vf_tph_requester_enable,
output [17:0] cfg_vf_tph_st_mode,
output cfg_msg_received,
output [7:0] cfg_msg_received_data,
output [4:0] cfg_msg_received_type,
input cfg_msg_transmit,
input [2:0] cfg_msg_transmit_type,
input [31:0] cfg_msg_transmit_data,
output cfg_msg_transmit_done,
output [7:0] cfg_fc_ph,
output [11:0] cfg_fc_pd,
output [7:0] cfg_fc_nph,
output [11:0] cfg_fc_npd,
output [7:0] cfg_fc_cplh,
output [11:0] cfg_fc_cpld,
input [2:0] cfg_fc_sel,
input [2:0] cfg_per_func_status_control,
output [15:0] cfg_per_func_status_data,
input [2:0] cfg_per_function_number,
input cfg_per_function_output_request,
output cfg_per_function_update_done,
input [15:0] cfg_subsys_vend_id,
input [63:0] cfg_dsn,
input cfg_power_state_change_ack,
output cfg_power_state_change_interrupt,
input cfg_err_cor_in,
input cfg_err_uncor_in,
output [1:0] cfg_flr_in_process,
input [1:0] cfg_flr_done,
output [5:0] cfg_vf_flr_in_process,
input [5:0] cfg_vf_flr_done,
input cfg_link_training_enable,
output cfg_ext_read_received,
output cfg_ext_write_received,
output [9:0] cfg_ext_register_number,
output [7:0] cfg_ext_function_number,
output [31:0] cfg_ext_write_data,
output [3:0] cfg_ext_write_byte_enable,
input [31:0] cfg_ext_read_data,
input cfg_ext_read_data_valid,
// Interrupt Interface Signals
input [3:0] cfg_interrupt_int,
input [1:0] cfg_interrupt_pending,
output cfg_interrupt_sent,
output [1:0] cfg_interrupt_msi_enable,
output [5:0] cfg_interrupt_msi_vf_enable,
output [5:0] cfg_interrupt_msi_mmenable,
output cfg_interrupt_msi_mask_update,
output [31:0] cfg_interrupt_msi_data,
input [3:0] cfg_interrupt_msi_select,
input [31:0] cfg_interrupt_msi_int,
input [63:0] cfg_interrupt_msi_pending_status,
output cfg_interrupt_msi_sent,
output cfg_interrupt_msi_fail,
output [1:0] cfg_interrupt_msix_enable,
output [1:0] cfg_interrupt_msix_mask,
output [5:0] cfg_interrupt_msix_vf_enable,
output [5:0] cfg_interrupt_msix_vf_mask,
input [31:0] cfg_interrupt_msix_data,
input [63:0] cfg_interrupt_msix_address,
input cfg_interrupt_msix_int,
output cfg_interrupt_msix_sent,
output cfg_interrupt_msix_fail,
input [2:0] cfg_interrupt_msi_attr,
input cfg_interrupt_msi_tph_present,
input [1:0] cfg_interrupt_msi_tph_type,
input [8:0] cfg_interrupt_msi_tph_st_tag,
input [2:0] cfg_interrupt_msi_function_number,
output cfg_hot_reset_out,
input cfg_config_space_enable,
input cfg_req_pm_transition_l23_ready,
//----------------------------------------------------------------------------------------------------------------//
// RP Only //
//----------------------------------------------------------------------------------------------------------------//
input cfg_hot_reset_in,
input [7:0] cfg_ds_port_number,
input [7:0] cfg_ds_bus_number,
input [4:0] cfg_ds_device_number,
input [2:0] cfg_ds_function_number,
//----------------------------------------------------------------------------------------------------------------//
// 6. TPH Interface //
//----------------------------------------------------------------------------------------------------------------//
input [4:0] user_tph_stt_address,
input [2:0] user_tph_function_num,
output [31:0] user_tph_stt_read_data,
output user_tph_stt_read_data_valid,
input user_tph_stt_read_enable,
//----------------------------------------------------------------------------------------------------------------//
// 7. System(SYS) Interface //
//----------------------------------------------------------------------------------------------------------------//
input wire sys_clk,
input wire sys_reset,
input pipe_mmcm_rst_n,
//--------------TRANSCEIVER_DEBUG---------------------------------
input [ 2:0] pipe_txprbssel,
input [ 2:0] pipe_rxprbssel,
input pipe_txprbsforceerr,
input pipe_rxprbscntreset,
input [ 2:0] pipe_loopback,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_rxprbserr,
input [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_txinhibit,
output [4:0] pipe_rst_fsm,
output [11:0] pipe_qrst_fsm,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*5)-1:0] pipe_rate_fsm,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*6)-1:0] pipe_sync_fsm_tx,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*7)-1:0] pipe_sync_fsm_rx,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*7)-1:0] pipe_drp_fsm,
output pipe_rst_idle,
output pipe_qrst_idle,
output pipe_rate_idle,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_eyescandataerror,
output [PL_LINK_CAP_MAX_LINK_WIDTH*3-1:0] pipe_rxstatus,
output [PL_LINK_CAP_MAX_LINK_WIDTH*15-1:0] pipe_dmonitorout,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_cpll_lock,
output [(PL_LINK_CAP_MAX_LINK_WIDTH-1)>>2:0] pipe_qpll_lock,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxpmaresetdone,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*3)-1:0] pipe_rxbufstatus,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txphaligndone,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txphinitdone,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txdlysresetdone,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxphaligndone,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxdlysresetdone,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxsyncdone,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*8)-1:0] pipe_rxdisperr,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*8)-1:0] pipe_rxnotintable,
output [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxcommadet,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] gt_ch_drp_rdy,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_0,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_1,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_2,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_3,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_4,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_5,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_6,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_7,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_8,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_9,
output [31:0] pipe_debug,
//---- PIPE Ports to Core Top Level for PIPE Mode Simulation with 3rd Party IP/BFM/Xilinx BFM ------------------------
input [25:0] common_commands_in,
input [83:0] pipe_rx_0_sigs,
input [83:0] pipe_rx_1_sigs,
input [83:0] pipe_rx_2_sigs,
input [83:0] pipe_rx_3_sigs,
input [83:0] pipe_rx_4_sigs,
input [83:0] pipe_rx_5_sigs,
input [83:0] pipe_rx_6_sigs,
input [83:0] pipe_rx_7_sigs,
output [16:0] common_commands_out,
output [69:0] pipe_tx_0_sigs,
output [69:0] pipe_tx_1_sigs,
output [69:0] pipe_tx_2_sigs,
output [69:0] pipe_tx_3_sigs,
output [69:0] pipe_tx_4_sigs,
output [69:0] pipe_tx_5_sigs,
output [69:0] pipe_tx_6_sigs,
output [69:0] pipe_tx_7_sigs,
//--------------Channel DRP---------------------------------
output ext_ch_gt_drpclk,
input [(PL_LINK_CAP_MAX_LINK_WIDTH*9)-1:0] ext_ch_gt_drpaddr,
input [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpen,
input [(PL_LINK_CAP_MAX_LINK_WIDTH*16)-1:0]ext_ch_gt_drpdi,
input [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpwe,
output [(PL_LINK_CAP_MAX_LINK_WIDTH*16)-1:0]ext_ch_gt_drpdo,
output [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drprdy,
//----------------------------------------------------------------------------------------------------------------//
// 9. Tandem PROM/PCIE ICAP Primitive Ports //
//----------------------------------------------------------------------------------------------------------------//
input icap_clk,
input icap_csib,
input icap_rdwrb,
input [31:0] icap_i,
output [31:0] icap_o,
output pcie_drp_rdy,
output [15:0] pcie_drp_do,
input pcie_drp_clk,
input pcie_drp_en,
input pcie_drp_we,
input [10:0] pcie_drp_addr,
input [15:0] pcie_drp_di,
//----------------------------------------------------------------------------------------------------------------//
// 10. Tandem PROM/PCIE STARTUP primitive Ports //
//----------------------------------------------------------------------------------------------------------------//
// This input should be used when the startup block is generated exteranl to the PCI Express Core
input startup_eos_in, // 1-bit input: This signal should be driven by the EOS output of the STARTUP primitive.
// These inputs and outputs may be use when the startup block is generated internal to the PCI Express Core.
output startup_cfgclk, // 1-bit output: Configuration main clock output
output startup_cfgmclk, // 1-bit output: Configuration internal oscillator clock output
output startup_eos, // 1-bit output: Active high output signal indicating the End Of Startup
output startup_preq, // 1-bit output: PROGRAM request to fabric output
input startup_clk, // 1-bit input: User start-up clock input
input startup_gsr, // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
input startup_gts, // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
input startup_keyclearb, // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
input startup_pack, // 1-bit input: PROGRAM acknowledge input
input startup_usrcclko, // 1-bit input: User CCLK input
input startup_usrcclkts, // 1-bit input: User CCLK 3-state enable input
input startup_usrdoneo, // 1-bit input: User DONE pin output control
input startup_usrdonets, // 1-bit input: User DONE 3-state enable output
input [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] cpllpd,
input [(PL_LINK_CAP_MAX_LINK_WIDTH*2)-1:0] txpd,
input [(PL_LINK_CAP_MAX_LINK_WIDTH*2)-1:0] rxpd,
input [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] txpdelecidlemode,
input [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] txdetectrx,
input [(PL_LINK_CAP_MAX_LINK_WIDTH)-1:0] txelecidle,
input [(PL_LINK_CAP_MAX_LINK_WIDTH-1)>>2:0] qpllpd,
input powerdown
);
localparam integer USER_CLK_FREQ = ((PL_LINK_CAP_MAX_LINK_SPEED == 3'h4) ? 5 : 4);
localparam [1:0] CRM_USER_CLK_FREQ = ((USER_CLK2_FREQ == 4) ? 2'b10: ((USER_CLK2_FREQ == 3) ? 2'b01 : 2'b00));
localparam [1:0] AXISTEN_IF_WIDTH = (C_DATA_WIDTH == 256) ? 2'b10 : ((C_DATA_WIDTH == 128) ? 2'b01 : 2'b00);
localparam CRM_CORE_CLK_FREQ_500 = ((PL_LINK_CAP_MAX_LINK_SPEED == 3'h4) ? "TRUE" : "FALSE");
localparam INTERFACE_SPEED = ((PL_LINK_CAP_MAX_LINK_SPEED == 3'h4) ? "500 MHZ" : "250 MHZ");
localparam ENABLE_FAST_SIM_TRAINING = "TRUE";
wire drp_clk_wire;
wire drp_en_wire;
wire drp_we_wire;
wire [10:0] drp_addr_wire;
wire [15:0] drp_di_wire;
wire drp_rdy_wire;
wire [15:0] drp_do_wire;
wire dt_654524_drp_clk;
wire dt_654524_drp_en;
wire dt_654524_drp_we;
wire [10:0] dt_654524_drp_addr;
wire [15:0] dt_654524_drp_di;
wire cfg_local_error;
wire rec_clk;
wire pipe_clk;
wire core_clk;
wire [15:0] cfg_vend_id = PF0_VENDOR_ID;
wire [15:0] cfg_dev_id = PF0_DEVICE_ID;
wire [7:0] cfg_rev_id = PF0_REVISION_ID;
// wire [15:0] cfg_subsys_vend_id = PF0_SUBSYSTEM_VENDOR_ID;
wire [15:0] cfg_subsys_id = PF0_SUBSYSTEM_ID;
// PIPE Interface Wires
wire pipe_tx_reset;
wire pipe_rx0_polarity;
wire pipe_rx1_polarity;
wire pipe_rx2_polarity;
wire pipe_rx3_polarity;
wire pipe_rx4_polarity;
wire pipe_rx5_polarity;
wire pipe_rx6_polarity;
wire pipe_rx7_polarity;
wire pipe_tx0_compliance;
wire pipe_tx1_compliance;
wire pipe_tx2_compliance;
wire pipe_tx3_compliance;
wire pipe_tx4_compliance;
wire pipe_tx5_compliance;
wire pipe_tx6_compliance;
wire pipe_tx7_compliance;
wire pipe_rx0_data_valid;
wire pipe_rx1_data_valid;
wire pipe_rx2_data_valid;
wire pipe_rx3_data_valid;
wire pipe_rx4_data_valid;
wire pipe_rx5_data_valid;
wire pipe_rx6_data_valid;
wire pipe_rx7_data_valid;
wire pipe_tx0_elec_idle;
wire pipe_tx1_elec_idle;
wire pipe_tx2_elec_idle;
wire pipe_tx3_elec_idle;
wire pipe_tx4_elec_idle;
wire pipe_tx5_elec_idle;
wire pipe_tx6_elec_idle;
wire pipe_tx7_elec_idle;
wire pipe_rx0_start_block;
wire pipe_rx1_start_block;
wire pipe_rx2_start_block;
wire pipe_rx3_start_block;
wire pipe_rx4_start_block;
wire pipe_rx5_start_block;
wire pipe_rx6_start_block;
wire pipe_rx7_start_block;
wire pipe_tx_deemph;
wire pipe_tx_rcvr_det;
wire [1:0] pipe_tx_rate;
wire [2:0] pipe_tx_margin;
wire pipe_tx_swing;
wire [5:0] pipe_tx_eqfs;
wire [5:0] pipe_tx_eqlf;
wire [1:0] pipe_rx0_eqcontrol;
wire [1:0] pipe_rx1_eqcontrol;
wire [1:0] pipe_rx2_eqcontrol;
wire [1:0] pipe_rx3_eqcontrol;
wire [1:0] pipe_rx4_eqcontrol;
wire [1:0] pipe_rx5_eqcontrol;
wire [1:0] pipe_rx6_eqcontrol;
wire [1:0] pipe_rx7_eqcontrol;
wire [1:0] pipe_tx0_char_is_k;
wire [1:0] pipe_tx1_char_is_k;
wire [1:0] pipe_tx2_char_is_k;
wire [1:0] pipe_tx3_char_is_k;
wire [1:0] pipe_tx4_char_is_k;
wire [1:0] pipe_tx5_char_is_k;
wire [1:0] pipe_tx6_char_is_k;
wire [1:0] pipe_tx7_char_is_k;
wire [1:0] pipe_tx0_eqcontrol;
wire [1:0] pipe_tx1_eqcontrol;
wire [1:0] pipe_tx2_eqcontrol;
wire [1:0] pipe_tx3_eqcontrol;
wire [1:0] pipe_tx4_eqcontrol;
wire [1:0] pipe_tx5_eqcontrol;
wire [1:0] pipe_tx6_eqcontrol;
wire [1:0] pipe_tx7_eqcontrol;
wire [1:0] pipe_tx0_powerdown;
wire [1:0] pipe_tx1_powerdown;
wire [1:0] pipe_tx2_powerdown;
wire [1:0] pipe_tx3_powerdown;
wire [1:0] pipe_tx4_powerdown;
wire [1:0] pipe_tx5_powerdown;
wire [1:0] pipe_tx6_powerdown;
wire [1:0] pipe_tx7_powerdown;
wire [1:0] pipe_rx0_syncheader;
wire [1:0] pipe_rx1_syncheader;
wire [1:0] pipe_rx2_syncheader;
wire [1:0] pipe_rx3_syncheader;
wire [1:0] pipe_rx4_syncheader;
wire [1:0] pipe_rx5_syncheader;
wire [1:0] pipe_rx6_syncheader;
wire [1:0] pipe_rx7_syncheader;
wire [2:0] pipe_rx0_eqpreset;
wire [2:0] pipe_rx1_eqpreset;
wire [2:0] pipe_rx2_eqpreset;
wire [2:0] pipe_rx3_eqpreset;
wire [2:0] pipe_rx4_eqpreset;
wire [2:0] pipe_rx5_eqpreset;
wire [2:0] pipe_rx6_eqpreset;
wire [2:0] pipe_rx7_eqpreset;
wire [31:0] pipe_tx0_data;
wire [31:0] pipe_tx1_data;
wire [31:0] pipe_tx2_data;
wire [31:0] pipe_tx3_data;
wire [31:0] pipe_tx4_data;
wire [31:0] pipe_tx5_data;
wire [31:0] pipe_tx6_data;
wire [31:0] pipe_tx7_data;
wire [3:0] pipe_rx0_eq_txpreset;
wire [3:0] pipe_rx1_eq_txpreset;
wire [3:0] pipe_rx2_eq_txpreset;
wire [3:0] pipe_rx3_eq_txpreset;
wire [3:0] pipe_rx4_eq_txpreset;
wire [3:0] pipe_rx5_eq_txpreset;
wire [3:0] pipe_rx6_eq_txpreset;
wire [3:0] pipe_rx7_eq_txpreset;
wire [3:0] pipe_tx0_eqpreset;
wire [3:0] pipe_tx1_eqpreset;
wire [3:0] pipe_tx2_eqpreset;
wire [3:0] pipe_tx3_eqpreset;
wire [3:0] pipe_tx4_eqpreset;
wire [3:0] pipe_tx5_eqpreset;
wire [3:0] pipe_tx6_eqpreset;
wire [3:0] pipe_tx7_eqpreset;
wire [5:0] pipe_rx0_eq_lffs;
wire [5:0] pipe_rx1_eq_lffs;
wire [5:0] pipe_rx2_eq_lffs;
wire [5:0] pipe_rx3_eq_lffs;
wire [5:0] pipe_rx4_eq_lffs;
wire [5:0] pipe_rx5_eq_lffs;
wire [5:0] pipe_rx6_eq_lffs;
wire [5:0] pipe_rx7_eq_lffs;
wire [5:0] pipe_tx0_eqdeemph;
wire [5:0] pipe_tx1_eqdeemph;
wire [5:0] pipe_tx2_eqdeemph;
wire [5:0] pipe_tx3_eqdeemph;
wire [5:0] pipe_tx4_eqdeemph;
wire [5:0] pipe_tx5_eqdeemph;
wire [5:0] pipe_tx6_eqdeemph;
wire [5:0] pipe_tx7_eqdeemph;
wire [7:0] pipe_rx_slide;
wire pipe_rx0_elec_idle;
wire pipe_rx1_elec_idle;
wire pipe_rx2_elec_idle;
wire pipe_rx3_elec_idle;
wire pipe_rx4_elec_idle;
wire pipe_rx5_elec_idle;
wire pipe_rx6_elec_idle;
wire pipe_rx7_elec_idle;
wire pipe_rx0_eqdone;
wire pipe_rx1_eqdone;
wire pipe_rx2_eqdone;
wire pipe_rx3_eqdone;
wire pipe_rx4_eqdone;
wire pipe_rx5_eqdone;
wire pipe_rx6_eqdone;
wire pipe_rx7_eqdone;
wire pipe_rx0_eq_adapt_done;
wire pipe_rx1_eq_adapt_done;
wire pipe_rx2_eq_adapt_done;
wire pipe_rx3_eq_adapt_done;
wire pipe_rx4_eq_adapt_done;
wire pipe_rx5_eq_adapt_done;
wire pipe_rx6_eq_adapt_done;
wire pipe_rx7_eq_adapt_done;
wire pipe_rx0_eq_lffs_sel;
wire pipe_rx1_eq_lffs_sel;
wire pipe_rx2_eq_lffs_sel;
wire pipe_rx3_eq_lffs_sel;
wire pipe_rx4_eq_lffs_sel;
wire pipe_rx5_eq_lffs_sel;
wire pipe_rx6_eq_lffs_sel;
wire pipe_rx7_eq_lffs_sel;
wire pipe_rx0_phy_status;
wire pipe_rx1_phy_status;
wire pipe_rx2_phy_status;
wire pipe_rx3_phy_status;
wire pipe_rx4_phy_status;
wire pipe_rx5_phy_status;
wire pipe_rx6_phy_status;
wire pipe_rx7_phy_status;
wire pipe_rx0_valid;
wire pipe_rx1_valid;
wire pipe_rx2_valid;
wire pipe_rx3_valid;
wire pipe_rx4_valid;
wire pipe_rx5_valid;
wire pipe_rx6_valid;
wire pipe_rx7_valid;
wire pipe_tx0_eqdone;
wire pipe_tx1_eqdone;
wire pipe_tx2_eqdone;
wire pipe_tx3_eqdone;
wire pipe_tx4_eqdone;
wire pipe_tx5_eqdone;
wire pipe_tx6_eqdone;
wire pipe_tx7_eqdone;
wire [17:0] pipe_rx0_eq_new_txcoeff;
wire [17:0] pipe_rx1_eq_new_txcoeff;
wire [17:0] pipe_rx2_eq_new_txcoeff;
wire [17:0] pipe_rx3_eq_new_txcoeff;
wire [17:0] pipe_rx4_eq_new_txcoeff;
wire [17:0] pipe_rx5_eq_new_txcoeff;
wire [17:0] pipe_rx6_eq_new_txcoeff;
wire [17:0] pipe_rx7_eq_new_txcoeff;
wire [17:0] pipe_tx0_eqcoeff;
wire [17:0] pipe_tx1_eqcoeff;
wire [17:0] pipe_tx2_eqcoeff;
wire [17:0] pipe_tx3_eqcoeff;
wire [17:0] pipe_tx4_eqcoeff;
wire [17:0] pipe_tx5_eqcoeff;
wire [17:0] pipe_tx6_eqcoeff;
wire [17:0] pipe_tx7_eqcoeff;
wire [1:0] pipe_rx0_char_is_k;
wire [1:0] pipe_rx1_char_is_k;
wire [1:0] pipe_rx2_char_is_k;
wire [1:0] pipe_rx3_char_is_k;
wire [1:0] pipe_rx4_char_is_k;
wire [1:0] pipe_rx5_char_is_k;
wire [1:0] pipe_rx6_char_is_k;
wire [1:0] pipe_rx7_char_is_k;
wire [2:0] pipe_rx0_status;
wire [2:0] pipe_rx1_status;
wire [2:0] pipe_rx2_status;
wire [2:0] pipe_rx3_status;
wire [2:0] pipe_rx4_status;
wire [2:0] pipe_rx5_status;
wire [2:0] pipe_rx6_status;
wire [2:0] pipe_rx7_status;
wire [31:0] pipe_rx0_data;
wire [31:0] pipe_rx1_data;
wire [31:0] pipe_rx2_data;
wire [31:0] pipe_rx3_data;
wire [31:0] pipe_rx4_data;
wire [31:0] pipe_rx5_data;
wire [31:0] pipe_rx6_data;
wire [31:0] pipe_rx7_data;
wire [7:0] pipe_rx_syncdone;
wire sys_or_hot_rst;
wire user_lnk_up_int;
reg user_reset_int;
// Wire Declaration for Inputs that are issolated in Tandem configuration
wire cfg_mgmt_write_wire;
wire cfg_mgmt_read_wire;
wire [2:0] cfg_per_func_status_control_wire;
wire cfg_per_function_output_request_wire;
wire [63:0] cfg_dsn_wire;
wire cfg_power_state_change_ack_wire;
wire cfg_err_cor_in_wire;
wire cfg_err_uncor_in_wire;
wire [1:0] cfg_flr_done_wire;
wire [5:0] cfg_vf_flr_done_wire;
wire cfg_link_training_enable_wire;
wire cfg_ext_read_data_valid_wire;
wire [1:0] cfg_interrupt_pending_wire;
wire [3:0] cfg_interrupt_msi_select_wire;
wire [63:0] cfg_interrupt_msi_pending_status_wire;
wire cfg_config_space_enable_wire;
wire cfg_req_pm_transition_l23_ready_wire;
wire cfg_hot_reset_in_wire;
wire [7:0] cfg_ds_port_number_wire;
wire [7:0] cfg_ds_bus_number_wire;
wire [4:0] cfg_ds_device_number_wire;
wire [2:0] cfg_ds_function_number_wire;
wire [4:0] user_tph_stt_address_wire;
wire [2:0] user_tph_function_num_wire;
wire user_tph_stt_read_enable_wire;
// Wire Declaration for Outputs that are issolated in Tandem configuration
wire cfg_phy_link_down_wire;
wire [1:0] cfg_phy_link_status_wire;
wire [5:0] cfg_ltssm_state_wire;
wire cfg_hot_reset_out_wire;
// Wire Declarations for tandem_cplr to pcie_top connections
wire [C_DATA_WIDTH-1:0] s_axis_cc_tdata_wire;
wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_wire;
wire s_axis_cc_tlast_wire;
wire s_axis_cc_tvalid_wire;
wire [32:0] s_axis_cc_tuser_wire;
wire [3:0] s_axis_cc_tready_wire;
wire s_axis_rq_tlast_wire;
wire [C_DATA_WIDTH-1:0] s_axis_rq_tdata_wire;
wire [59:0] s_axis_rq_tuser_wire;
wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_wire;
wire [3:0] s_axis_rq_tready_wire;
wire s_axis_rq_tvalid_wire;
wire cfg_msg_transmit_done_wire;
wire cfg_msg_transmit_wire;
wire [2:0] cfg_msg_transmit_type_wire;
wire [31:0] cfg_msg_transmit_data_wire;
wire [5:0] pcie_rq_tag_wire;
wire pcie_rq_tag_vld_wire;
wire [1:0] pcie_tfc_nph_av_wire;
wire [1:0] pcie_tfc_npd_av_wire;
wire [3:0] pcie_rq_seq_num_wire;
wire pcie_rq_seq_num_vld_wire;
wire [7:0] cfg_fc_ph_wire;
wire [7:0] cfg_fc_nph_wire;
wire [7:0] cfg_fc_cplh_wire;
wire [11:0] cfg_fc_pd_wire;
wire [11:0] cfg_fc_npd_wire;
wire [11:0] cfg_fc_cpld_wire;
wire [2:0] cfg_fc_sel_wire;
wire [C_DATA_WIDTH-1:0] m_axis_cq_tdata_wire;
wire m_axis_cq_tlast_wire;
wire m_axis_cq_tvalid_wire;
wire [84:0] m_axis_cq_tuser_wire;
wire [KEEP_WIDTH-1:0] m_axis_cq_tkeep_wire;
wire [21:0] m_axis_cq_tready_wire;
wire pcie_cq_np_req_wire;
wire [5:0] pcie_cq_np_req_count_wire;
wire [C_DATA_WIDTH-1:0] m_axis_rc_tdata_wire;
wire m_axis_rc_tlast_wire;
wire m_axis_rc_tvalid_wire;
wire [74:0] m_axis_rc_tuser_wire;
wire [KEEP_WIDTH-1:0] m_axis_rc_tkeep_wire;
wire [21:0] m_axis_rc_tready_wire;
wire cfg_msg_received_wire;
wire [4:0] cfg_msg_received_type_wire;
wire [7:0] cfg_msg_received_data_wire;
wire [3:0] cfg_interrupt_int_wire;
wire [31:0] cfg_interrupt_msi_int_wire;
wire cfg_interrupt_msix_int_wire;
wire [C_DATA_WIDTH-1:0] s_axis_cc_tdata_cplr;
wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_cplr;
wire s_axis_cc_tlast_cplr;
wire s_axis_cc_tvalid_cplr;
wire [32:0] s_axis_cc_tuser_cplr;
wire m_axis_cq_tready_cplr;
wire s_axis_rq_tlast_cplr;
wire [C_DATA_WIDTH-1:0] s_axis_rq_tdata_cplr;
wire [59:0] s_axis_rq_tuser_cplr;
wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_cplr;
wire s_axis_rq_tvalid_cplr;
wire cfg_msg_transmit_cplr;
wire [2:0] cfg_msg_transmit_type_cplr;
wire [31:0] cfg_msg_transmit_data_cplr;
wire [2:0] cfg_fc_sel_cplr;
wire pcie_cq_np_req_cplr;
wire m_axis_rc_tready_cplr;
wire mmcm_lock;
// user_app_rdy signals which control the issolation muxes
wire user_app_rdy_req;
// Variables and Parameters for Pipe mode Simulation
wire [7:0] pipe_rxeq_user_en ;
wire [143:0] pipe_rxeq_user_txcoeff ;
generate
if(PIPE_SIM_MODE=="FALSE") begin
assign pipe_rxeq_user_en = 8'h00 ;
assign pipe_rxeq_user_txcoeff = 144'h0 ;
assign pipe_rx0_data_valid = 1'b0;
assign pipe_rx1_data_valid = 1'b0;
assign pipe_rx2_data_valid = 1'b0;
assign pipe_rx3_data_valid = 1'b0;
assign pipe_rx4_data_valid = 1'b0;
assign pipe_rx5_data_valid = 1'b0;
assign pipe_rx6_data_valid = 1'b0;
assign pipe_rx7_data_valid = 1'b0;
assign pipe_rx0_start_block = 1'b0;
assign pipe_rx1_start_block = 1'b0;
assign pipe_rx2_start_block = 1'b0;
assign pipe_rx3_start_block = 1'b0;
assign pipe_rx4_start_block = 1'b0;
assign pipe_rx5_start_block = 1'b0;
assign pipe_rx6_start_block = 1'b0;
assign pipe_rx7_start_block = 1'b0;
assign pipe_rx0_syncheader = 2'b0;
assign pipe_rx1_syncheader = 2'b0;
assign pipe_rx2_syncheader = 2'b0;
assign pipe_rx3_syncheader = 2'b0;
assign pipe_rx4_syncheader = 2'b0;
assign pipe_rx5_syncheader = 2'b0;
assign pipe_rx6_syncheader = 2'b0;
assign pipe_rx7_syncheader = 2'b0;
end
else begin
assign pipe_rxeq_user_en = 8'hff;
assign pipe_rxeq_user_txcoeff = {8{6'd00,6'd30,6'd10}} ;
end
endgenerate
//------------------------------------------------------------------------------------------------------------------//
// Convert incoming reset from AXI required active High //
// to active low as that is what is required by GT and PCIe Block //
//------------------------------------------------------------------------------------------------------------------//
wire sys_rst_n;
wire PIPE_MMCM_LOCK_IN_wire;
assign sys_rst_n = !sys_reset;
assign PIPE_MMCM_LOCK_IN_wire = pipe_mmcm_lock_in;
assign user_lnk_up_int = (cfg_phy_link_status_wire == 2'b11) ? 1'b1 : 1'b0;
assign sys_or_hot_rst = !sys_rst_n || cfg_hot_reset_out_wire;
//------------------------------------------------------------------------------------------------------------------//
// Generate user_reset //
// Once user reset output of PCIE and Phy Layer is active, de-assert reset //
// Only assert reset if system reset or hot reset is seen. Keep AXI backend/user application alive otherwise //
//------------------------------------------------------------------------------------------------------------------//
always @(posedge user_clk or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset_int <= #TCQ 1'b1;
end else if (cfg_phy_link_status_wire[1] && !cfg_phy_link_down_wire) begin
user_reset_int <= #TCQ 1'b0;
end
end
// Invert active low reset to active high AXI reset
always @(posedge user_clk or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset <= #TCQ 1'b1;
end else begin
user_reset <= #TCQ user_reset_int;
end
end
pcie3_7x_0_pcie_top #(
.TCQ ( TCQ ),
.PIPE_SIM_MODE (PIPE_SIM_MODE ),
.PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ),
.ARI_CAP_ENABLE ( ARI_CAP_ENABLE ),
.AXISTEN_IF_CC_ALIGNMENT_MODE ( AXISTEN_IF_CC_ALIGNMENT_MODE ),
.AXISTEN_IF_CC_PARITY_CHK ( AXISTEN_IF_CC_PARITY_CHK ),
.AXISTEN_IF_CQ_ALIGNMENT_MODE ( AXISTEN_IF_CQ_ALIGNMENT_MODE ),
.AXISTEN_IF_ENABLE_CLIENT_TAG ( AXISTEN_IF_ENABLE_CLIENT_TAG ),
.AXISTEN_IF_ENABLE_MSG_ROUTE ( AXISTEN_IF_ENABLE_MSG_ROUTE ),
.AXISTEN_IF_ENABLE_RX_MSG_INTFC ( AXISTEN_IF_ENABLE_RX_MSG_INTFC ),
.AXISTEN_IF_RC_ALIGNMENT_MODE ( AXISTEN_IF_RC_ALIGNMENT_MODE ),
.AXISTEN_IF_RC_STRADDLE ( AXISTEN_IF_RC_STRADDLE ),
.AXISTEN_IF_RQ_ALIGNMENT_MODE ( AXISTEN_IF_RQ_ALIGNMENT_MODE ),
.AXISTEN_IF_RQ_PARITY_CHK ( AXISTEN_IF_RQ_PARITY_CHK ),
.AXISTEN_IF_WIDTH ( AXISTEN_IF_WIDTH ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.CRM_CORE_CLK_FREQ_500 ( CRM_CORE_CLK_FREQ_500 ),
.CRM_USER_CLK_FREQ ( CRM_USER_CLK_FREQ ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.GEN3_PCS_AUTO_REALIGN ( GEN3_PCS_AUTO_REALIGN ),
.GEN3_PCS_RX_ELECIDLE_INTERNAL ( GEN3_PCS_RX_ELECIDLE_INTERNAL ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_CPL_FC_UPDATE_TIMER ( LL_CPL_FC_UPDATE_TIMER ),
.LL_CPL_FC_UPDATE_TIMER_OVERRIDE ( LL_CPL_FC_UPDATE_TIMER_OVERRIDE ),
.LL_FC_UPDATE_TIMER ( LL_FC_UPDATE_TIMER ),
.LL_FC_UPDATE_TIMER_OVERRIDE ( LL_FC_UPDATE_TIMER_OVERRIDE ),
.LL_NP_FC_UPDATE_TIMER ( LL_NP_FC_UPDATE_TIMER ),
.LL_NP_FC_UPDATE_TIMER_OVERRIDE ( LL_NP_FC_UPDATE_TIMER_OVERRIDE ),
.LL_P_FC_UPDATE_TIMER ( LL_P_FC_UPDATE_TIMER ),
.LL_P_FC_UPDATE_TIMER_OVERRIDE ( LL_P_FC_UPDATE_TIMER_OVERRIDE ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTR_TX_MESSAGE_MINIMUM_INTERVAL ( LTR_TX_MESSAGE_MINIMUM_INTERVAL ),
.LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE ( LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE ),
.LTR_TX_MESSAGE_ON_LTR_ENABLE ( LTR_TX_MESSAGE_ON_LTR_ENABLE ),
.PF0_AER_CAP_ECRC_CHECK_CAPABLE ( PF0_AER_CAP_ECRC_CHECK_CAPABLE ),
.PF0_AER_CAP_ECRC_GEN_CAPABLE ( PF0_AER_CAP_ECRC_GEN_CAPABLE ),
.PF0_AER_CAP_NEXTPTR ( PF0_AER_CAP_NEXTPTR ),
.PF0_ARI_CAP_NEXTPTR ( PF0_ARI_CAP_NEXTPTR ),
.PF0_ARI_CAP_NEXT_FUNC ( PF0_ARI_CAP_NEXT_FUNC ),
.PF0_ARI_CAP_VER ( PF0_ARI_CAP_VER ),
.PF0_BAR0_APERTURE_SIZE ( PF0_BAR0_APERTURE_SIZE ),
.PF0_BAR0_CONTROL ( PF0_BAR0_CONTROL ),
.PF0_BAR1_APERTURE_SIZE ( PF0_BAR1_APERTURE_SIZE ),
.PF0_BAR1_CONTROL ( PF0_BAR1_CONTROL ),
.PF0_BAR2_APERTURE_SIZE ( PF0_BAR2_APERTURE_SIZE ),
.PF0_BAR2_CONTROL ( PF0_BAR2_CONTROL ),
.PF0_BAR3_APERTURE_SIZE ( PF0_BAR3_APERTURE_SIZE ),
.PF0_BAR3_CONTROL ( PF0_BAR3_CONTROL ),
.PF0_BAR4_APERTURE_SIZE ( PF0_BAR4_APERTURE_SIZE ),
.PF0_BAR4_CONTROL ( PF0_BAR4_CONTROL ),
.PF0_BAR5_APERTURE_SIZE ( PF0_BAR5_APERTURE_SIZE ),
.PF0_BAR5_CONTROL ( PF0_BAR5_CONTROL ),
.PF0_BIST_REGISTER ( PF0_BIST_REGISTER ),
.PF0_CAPABILITY_POINTER ( PF0_CAPABILITY_POINTER ),
.PF0_CLASS_CODE ( PF0_CLASS_CODE ),
.PF0_DEVICE_ID ( PF0_DEVICE_ID ),
.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT ( PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT ),
.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT ( PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT ),
.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT ( PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT ),
.PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE ( PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE ),
.PF0_DEV_CAP2_LTR_SUPPORT ( PF0_DEV_CAP2_LTR_SUPPORT ),
.PF0_DEV_CAP2_OBFF_SUPPORT ( PF0_DEV_CAP2_OBFF_SUPPORT ),
.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT ( PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT ),
.PF0_DEV_CAP_ENDPOINT_L0S_LATENCY ( PF0_DEV_CAP_ENDPOINT_L0S_LATENCY ),
.PF0_DEV_CAP_ENDPOINT_L1_LATENCY ( PF0_DEV_CAP_ENDPOINT_L1_LATENCY ),
.PF0_DEV_CAP_EXT_TAG_SUPPORTED ( PF0_DEV_CAP_EXT_TAG_SUPPORTED ),
.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.PF0_DEV_CAP_MAX_PAYLOAD_SIZE ( PF0_DEV_CAP_MAX_PAYLOAD_SIZE ),
.PF0_DPA_CAP_NEXTPTR ( PF0_DPA_CAP_NEXTPTR ),
.VF0_ARI_CAP_NEXTPTR ( VF0_ARI_CAP_NEXTPTR ),
.VF1_ARI_CAP_NEXTPTR ( VF1_ARI_CAP_NEXTPTR ),
.VF2_ARI_CAP_NEXTPTR ( VF2_ARI_CAP_NEXTPTR ),
.VF3_ARI_CAP_NEXTPTR ( VF3_ARI_CAP_NEXTPTR ),
.VF4_ARI_CAP_NEXTPTR ( VF4_ARI_CAP_NEXTPTR ),
.VF5_ARI_CAP_NEXTPTR ( VF5_ARI_CAP_NEXTPTR ),
.VF0_TPHR_CAP_DEV_SPECIFIC_MODE ( VF0_TPHR_CAP_DEV_SPECIFIC_MODE ),
.VF0_TPHR_CAP_ENABLE ( VF0_TPHR_CAP_ENABLE ),
.VF0_TPHR_CAP_INT_VEC_MODE ( VF0_TPHR_CAP_INT_VEC_MODE ),
.VF0_TPHR_CAP_NEXTPTR ( VF0_TPHR_CAP_NEXTPTR ),
.VF0_TPHR_CAP_ST_MODE_SEL ( VF0_TPHR_CAP_ST_MODE_SEL ),
.VF0_TPHR_CAP_ST_TABLE_LOC ( VF0_TPHR_CAP_ST_TABLE_LOC ),
.VF0_TPHR_CAP_ST_TABLE_SIZE ( VF0_TPHR_CAP_ST_TABLE_SIZE ),
.VF0_TPHR_CAP_VER ( VF0_TPHR_CAP_VER ),
.VF1_TPHR_CAP_DEV_SPECIFIC_MODE ( VF1_TPHR_CAP_DEV_SPECIFIC_MODE ),
.VF1_TPHR_CAP_ENABLE ( VF1_TPHR_CAP_ENABLE ),
.VF1_TPHR_CAP_INT_VEC_MODE ( VF1_TPHR_CAP_INT_VEC_MODE ),
.VF1_TPHR_CAP_NEXTPTR ( VF1_TPHR_CAP_NEXTPTR ),
.VF1_TPHR_CAP_ST_MODE_SEL ( VF1_TPHR_CAP_ST_MODE_SEL ),
.VF1_TPHR_CAP_ST_TABLE_LOC ( VF1_TPHR_CAP_ST_TABLE_LOC ),
.VF1_TPHR_CAP_ST_TABLE_SIZE ( VF1_TPHR_CAP_ST_TABLE_SIZE ),
.VF1_TPHR_CAP_VER ( VF1_TPHR_CAP_VER ),
.VF2_TPHR_CAP_DEV_SPECIFIC_MODE ( VF2_TPHR_CAP_DEV_SPECIFIC_MODE ),
.VF2_TPHR_CAP_ENABLE ( VF2_TPHR_CAP_ENABLE ),
.VF2_TPHR_CAP_INT_VEC_MODE ( VF2_TPHR_CAP_INT_VEC_MODE ),
.VF2_TPHR_CAP_NEXTPTR ( VF2_TPHR_CAP_NEXTPTR ),
.VF2_TPHR_CAP_ST_MODE_SEL ( VF2_TPHR_CAP_ST_MODE_SEL ),
.VF2_TPHR_CAP_ST_TABLE_LOC ( VF2_TPHR_CAP_ST_TABLE_LOC ),
.VF2_TPHR_CAP_ST_TABLE_SIZE ( VF2_TPHR_CAP_ST_TABLE_SIZE ),
.VF2_TPHR_CAP_VER ( VF2_TPHR_CAP_VER ),
.VF3_TPHR_CAP_DEV_SPECIFIC_MODE ( VF3_TPHR_CAP_DEV_SPECIFIC_MODE ),
.VF3_TPHR_CAP_ENABLE ( VF3_TPHR_CAP_ENABLE ),
.VF3_TPHR_CAP_INT_VEC_MODE ( VF3_TPHR_CAP_INT_VEC_MODE ),
.VF3_TPHR_CAP_NEXTPTR ( VF3_TPHR_CAP_NEXTPTR ),
.VF3_TPHR_CAP_ST_MODE_SEL ( VF3_TPHR_CAP_ST_MODE_SEL ),
.VF3_TPHR_CAP_ST_TABLE_LOC ( VF3_TPHR_CAP_ST_TABLE_LOC ),
.VF3_TPHR_CAP_ST_TABLE_SIZE ( VF3_TPHR_CAP_ST_TABLE_SIZE ),
.VF3_TPHR_CAP_VER ( VF3_TPHR_CAP_VER ),
.VF4_TPHR_CAP_DEV_SPECIFIC_MODE ( VF4_TPHR_CAP_DEV_SPECIFIC_MODE ),
.VF4_TPHR_CAP_ENABLE ( VF4_TPHR_CAP_ENABLE ),
.VF4_TPHR_CAP_INT_VEC_MODE ( VF4_TPHR_CAP_INT_VEC_MODE ),
.VF4_TPHR_CAP_NEXTPTR ( VF4_TPHR_CAP_NEXTPTR ),
.VF4_TPHR_CAP_ST_MODE_SEL ( VF4_TPHR_CAP_ST_MODE_SEL ),
.VF4_TPHR_CAP_ST_TABLE_LOC ( VF4_TPHR_CAP_ST_TABLE_LOC ),
.VF4_TPHR_CAP_ST_TABLE_SIZE ( VF4_TPHR_CAP_ST_TABLE_SIZE ),
.VF4_TPHR_CAP_VER ( VF4_TPHR_CAP_VER ),
.VF5_TPHR_CAP_DEV_SPECIFIC_MODE ( VF5_TPHR_CAP_DEV_SPECIFIC_MODE ),
.VF5_TPHR_CAP_ENABLE ( VF5_TPHR_CAP_ENABLE ),
.VF5_TPHR_CAP_INT_VEC_MODE ( VF5_TPHR_CAP_INT_VEC_MODE ),
.VF5_TPHR_CAP_NEXTPTR ( VF5_TPHR_CAP_NEXTPTR ),
.VF5_TPHR_CAP_ST_MODE_SEL ( VF5_TPHR_CAP_ST_MODE_SEL ),
.VF5_TPHR_CAP_ST_TABLE_LOC ( VF5_TPHR_CAP_ST_TABLE_LOC ),
.VF5_TPHR_CAP_ST_TABLE_SIZE ( VF5_TPHR_CAP_ST_TABLE_SIZE ),
.VF5_TPHR_CAP_VER ( VF5_TPHR_CAP_VER ),
.PF0_DPA_CAP_SUB_STATE_CONTROL ( PF0_DPA_CAP_SUB_STATE_CONTROL ),
.PF0_DPA_CAP_SUB_STATE_CONTROL_EN ( PF0_DPA_CAP_SUB_STATE_CONTROL_EN ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 ),
.PF0_DPA_CAP_VER ( PF0_DPA_CAP_VER ),
.PF0_DSN_CAP_NEXTPTR ( PF0_DSN_CAP_NEXTPTR ),
.PF0_EXPANSION_ROM_APERTURE_SIZE ( PF0_EXPANSION_ROM_APERTURE_SIZE ),
.PF0_EXPANSION_ROM_ENABLE ( PF0_EXPANSION_ROM_ENABLE ),
.PF0_INTERRUPT_LINE ( PF0_INTERRUPT_LINE ),
.PF0_INTERRUPT_PIN ( PF0_INTERRUPT_PIN ),
.PF0_LINK_CAP_ASPM_SUPPORT ( PF0_LINK_CAP_ASPM_SUPPORT ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 ( PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 ( PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 ( PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 ( PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 ),
.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG ( PF0_LINK_STATUS_SLOT_CLOCK_CONFIG ),
.PF0_LTR_CAP_MAX_NOSNOOP_LAT ( PF0_LTR_CAP_MAX_NOSNOOP_LAT ),
.PF0_LTR_CAP_MAX_SNOOP_LAT ( PF0_LTR_CAP_MAX_SNOOP_LAT ),
.PF0_LTR_CAP_NEXTPTR ( PF0_LTR_CAP_NEXTPTR ),
.PF0_LTR_CAP_VER ( PF0_LTR_CAP_VER ),
.PF0_MSIX_CAP_NEXTPTR ( PF0_MSIX_CAP_NEXTPTR ),
.PF0_MSIX_CAP_PBA_BIR ( PF0_MSIX_CAP_PBA_BIR ),
.PF0_MSIX_CAP_PBA_OFFSET ( PF0_MSIX_CAP_PBA_OFFSET ),
.PF0_MSIX_CAP_TABLE_BIR ( PF0_MSIX_CAP_TABLE_BIR ),
.PF0_MSIX_CAP_TABLE_OFFSET ( PF0_MSIX_CAP_TABLE_OFFSET ),
.PF0_MSIX_CAP_TABLE_SIZE ( PF0_MSIX_CAP_TABLE_SIZE ),
.PF0_MSI_CAP_MULTIMSGCAP ( PF0_MSI_CAP_MULTIMSGCAP ),
.PF0_MSI_CAP_NEXTPTR ( PF0_MSI_CAP_NEXTPTR ),
.PF0_PB_CAP_NEXTPTR ( PF0_PB_CAP_NEXTPTR ),
.PF0_PB_CAP_SYSTEM_ALLOCATED ( PF0_PB_CAP_SYSTEM_ALLOCATED ),
.PF0_PB_CAP_VER ( PF0_PB_CAP_VER ),
.PF0_PM_CAP_ID ( PF0_PM_CAP_ID ),
.PF0_PM_CAP_NEXTPTR ( PF0_PM_CAP_NEXTPTR ),
.PF0_PM_CAP_PMESUPPORT_D0 ( PF0_PM_CAP_PMESUPPORT_D0 ),
.PF0_PM_CAP_PMESUPPORT_D1 ( PF0_PM_CAP_PMESUPPORT_D1 ),
.PF0_PM_CAP_PMESUPPORT_D3HOT ( PF0_PM_CAP_PMESUPPORT_D3HOT ),
.PF0_PM_CAP_SUPP_D1_STATE ( PF0_PM_CAP_SUPP_D1_STATE ),
.PF0_PM_CAP_VER_ID ( PF0_PM_CAP_VER_ID ),
.PF0_PM_CSR_NOSOFTRESET ( PF0_PM_CSR_NOSOFTRESET ),
.PF0_RBAR_CAP_ENABLE ( PF0_RBAR_CAP_ENABLE ),
.PF0_RBAR_CAP_INDEX0 ( PF0_RBAR_CAP_INDEX0 ),
.PF0_RBAR_CAP_INDEX1 ( PF0_RBAR_CAP_INDEX1 ),
.PF0_RBAR_CAP_INDEX2 ( PF0_RBAR_CAP_INDEX2 ),
.PF0_RBAR_CAP_NEXTPTR ( PF0_RBAR_CAP_NEXTPTR ),
.PF0_RBAR_CAP_SIZE0 ( PF0_RBAR_CAP_SIZE0 ),
.PF0_RBAR_CAP_SIZE1 ( PF0_RBAR_CAP_SIZE1 ),
.PF0_RBAR_CAP_SIZE2 ( PF0_RBAR_CAP_SIZE2 ),
.PF0_RBAR_CAP_VER ( PF0_RBAR_CAP_VER ),
.PF0_RBAR_NUM ( PF0_RBAR_NUM ),
.PF0_REVISION_ID ( PF0_REVISION_ID ),
.PF0_SRIOV_BAR0_APERTURE_SIZE ( PF0_SRIOV_BAR0_APERTURE_SIZE ),
.PF0_SRIOV_BAR0_CONTROL ( PF0_SRIOV_BAR0_CONTROL ),
.PF0_SRIOV_BAR1_APERTURE_SIZE ( PF0_SRIOV_BAR1_APERTURE_SIZE ),
.PF0_SRIOV_BAR1_CONTROL ( PF0_SRIOV_BAR1_CONTROL ),
.PF0_SRIOV_BAR2_APERTURE_SIZE ( PF0_SRIOV_BAR2_APERTURE_SIZE ),
.PF0_SRIOV_BAR2_CONTROL ( PF0_SRIOV_BAR2_CONTROL ),
.PF0_SRIOV_BAR3_APERTURE_SIZE ( PF0_SRIOV_BAR3_APERTURE_SIZE ),
.PF0_SRIOV_BAR3_CONTROL ( PF0_SRIOV_BAR3_CONTROL ),
.PF0_SRIOV_BAR4_APERTURE_SIZE ( PF0_SRIOV_BAR4_APERTURE_SIZE ),
.PF0_SRIOV_BAR4_CONTROL ( PF0_SRIOV_BAR4_CONTROL ),
.PF0_SRIOV_BAR5_APERTURE_SIZE ( PF0_SRIOV_BAR5_APERTURE_SIZE ),
.PF0_SRIOV_BAR5_CONTROL ( PF0_SRIOV_BAR5_CONTROL ),
.PF0_SRIOV_CAP_INITIAL_VF ( PF0_SRIOV_CAP_INITIAL_VF ),
.PF0_SRIOV_CAP_NEXTPTR ( PF0_SRIOV_CAP_NEXTPTR ),
.PF0_SRIOV_CAP_TOTAL_VF ( PF0_SRIOV_CAP_TOTAL_VF ),
.PF0_SRIOV_CAP_VER ( PF0_SRIOV_CAP_VER ),
.PF0_SRIOV_FIRST_VF_OFFSET ( PF0_SRIOV_FIRST_VF_OFFSET ),
.PF0_SRIOV_FUNC_DEP_LINK ( PF0_SRIOV_FUNC_DEP_LINK ),
.PF0_SRIOV_SUPPORTED_PAGE_SIZE ( PF0_SRIOV_SUPPORTED_PAGE_SIZE ),
.PF0_SRIOV_VF_DEVICE_ID ( PF0_SRIOV_VF_DEVICE_ID ),
.PF0_SUBSYSTEM_ID ( PF0_SUBSYSTEM_ID ),
.PF0_TPHR_CAP_DEV_SPECIFIC_MODE ( PF0_TPHR_CAP_DEV_SPECIFIC_MODE ),
.PF0_TPHR_CAP_ENABLE ( PF0_TPHR_CAP_ENABLE ),
.PF0_TPHR_CAP_INT_VEC_MODE ( PF0_TPHR_CAP_INT_VEC_MODE ),
.PF0_TPHR_CAP_NEXTPTR ( PF0_TPHR_CAP_NEXTPTR ),
.PF0_TPHR_CAP_ST_MODE_SEL ( PF0_TPHR_CAP_ST_MODE_SEL ),
.PF0_TPHR_CAP_ST_TABLE_LOC ( PF0_TPHR_CAP_ST_TABLE_LOC ),
.PF0_TPHR_CAP_ST_TABLE_SIZE ( PF0_TPHR_CAP_ST_TABLE_SIZE ),
.PF0_TPHR_CAP_VER ( PF0_TPHR_CAP_VER ),
.PF0_VC_CAP_NEXTPTR ( PF0_VC_CAP_NEXTPTR ),
.PF0_VC_CAP_VER ( PF0_VC_CAP_VER ),
.PF1_AER_CAP_ECRC_CHECK_CAPABLE ( PF1_AER_CAP_ECRC_CHECK_CAPABLE ),
.PF1_AER_CAP_ECRC_GEN_CAPABLE ( PF1_AER_CAP_ECRC_GEN_CAPABLE ),
.PF1_AER_CAP_NEXTPTR ( PF1_AER_CAP_NEXTPTR ),
.PF1_ARI_CAP_NEXTPTR ( PF1_ARI_CAP_NEXTPTR ),
.PF1_ARI_CAP_NEXT_FUNC ( PF1_ARI_CAP_NEXT_FUNC ),
.PF1_BAR0_APERTURE_SIZE ( PF1_BAR0_APERTURE_SIZE ),
.PF1_BAR0_CONTROL ( PF1_BAR0_CONTROL ),
.PF1_BAR1_APERTURE_SIZE ( PF1_BAR1_APERTURE_SIZE ),
.PF1_BAR1_CONTROL ( PF1_BAR1_CONTROL ),
.PF1_BAR2_APERTURE_SIZE ( PF1_BAR2_APERTURE_SIZE ),
.PF1_BAR2_CONTROL ( PF1_BAR2_CONTROL ),
.PF1_BAR3_APERTURE_SIZE ( PF1_BAR3_APERTURE_SIZE ),
.PF1_BAR3_CONTROL ( PF1_BAR3_CONTROL ),
.PF1_BAR4_APERTURE_SIZE ( PF1_BAR4_APERTURE_SIZE ),
.PF1_BAR4_CONTROL ( PF1_BAR4_CONTROL ),
.PF1_BAR5_APERTURE_SIZE ( PF1_BAR5_APERTURE_SIZE ),
.PF1_BAR5_CONTROL ( PF1_BAR5_CONTROL ),
.PF1_BIST_REGISTER ( PF1_BIST_REGISTER ),
.PF1_CAPABILITY_POINTER ( PF1_CAPABILITY_POINTER ),
.PF1_CLASS_CODE ( PF1_CLASS_CODE ),
.PF1_DEVICE_ID ( PF1_DEVICE_ID ),
.PF1_DEV_CAP_MAX_PAYLOAD_SIZE ( PF1_DEV_CAP_MAX_PAYLOAD_SIZE ),
.PF1_DPA_CAP_NEXTPTR ( PF1_DPA_CAP_NEXTPTR ),
.PF1_DPA_CAP_SUB_STATE_CONTROL ( PF1_DPA_CAP_SUB_STATE_CONTROL ),
.PF1_DPA_CAP_SUB_STATE_CONTROL_EN ( PF1_DPA_CAP_SUB_STATE_CONTROL_EN ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 ),
.PF1_DPA_CAP_VER ( PF1_DPA_CAP_VER ),
.PF1_DSN_CAP_NEXTPTR ( PF1_DSN_CAP_NEXTPTR ),
.PF1_EXPANSION_ROM_APERTURE_SIZE ( PF1_EXPANSION_ROM_APERTURE_SIZE ),
.PF1_EXPANSION_ROM_ENABLE ( PF1_EXPANSION_ROM_ENABLE ),
.PF1_INTERRUPT_LINE ( PF1_INTERRUPT_LINE ),
.PF1_INTERRUPT_PIN ( PF1_INTERRUPT_PIN ),
.PF1_MSIX_CAP_NEXTPTR ( PF1_MSIX_CAP_NEXTPTR ),
.PF1_MSIX_CAP_PBA_BIR ( PF1_MSIX_CAP_PBA_BIR ),
.PF1_MSIX_CAP_PBA_OFFSET ( PF1_MSIX_CAP_PBA_OFFSET ),
.PF1_MSIX_CAP_TABLE_BIR ( PF1_MSIX_CAP_TABLE_BIR ),
.PF1_MSIX_CAP_TABLE_OFFSET ( PF1_MSIX_CAP_TABLE_OFFSET ),
.PF1_MSIX_CAP_TABLE_SIZE ( PF1_MSIX_CAP_TABLE_SIZE ),
.PF1_MSI_CAP_MULTIMSGCAP ( PF1_MSI_CAP_MULTIMSGCAP ),
.PF1_MSI_CAP_NEXTPTR ( PF1_MSI_CAP_NEXTPTR ),
.PF1_PB_CAP_NEXTPTR ( PF1_PB_CAP_NEXTPTR ),
.PF1_PB_CAP_SYSTEM_ALLOCATED ( PF1_PB_CAP_SYSTEM_ALLOCATED ),
.PF1_PB_CAP_VER ( PF1_PB_CAP_VER ),
.PF1_PM_CAP_ID ( PF1_PM_CAP_ID ),
.PF1_PM_CAP_NEXTPTR ( PF1_PM_CAP_NEXTPTR ),
.PF1_PM_CAP_VER_ID ( PF1_PM_CAP_VER_ID ),
.PF1_RBAR_CAP_ENABLE ( PF1_RBAR_CAP_ENABLE ),
.PF1_RBAR_CAP_INDEX0 ( PF1_RBAR_CAP_INDEX0 ),
.PF1_RBAR_CAP_INDEX1 ( PF1_RBAR_CAP_INDEX1 ),
.PF1_RBAR_CAP_INDEX2 ( PF1_RBAR_CAP_INDEX2 ),
.PF1_RBAR_CAP_NEXTPTR ( PF1_RBAR_CAP_NEXTPTR ),
.PF1_RBAR_CAP_SIZE0 ( PF1_RBAR_CAP_SIZE0 ),
.PF1_RBAR_CAP_SIZE1 ( PF1_RBAR_CAP_SIZE1 ),
.PF1_RBAR_CAP_SIZE2 ( PF1_RBAR_CAP_SIZE2 ),
.PF1_RBAR_CAP_VER ( PF1_RBAR_CAP_VER ),
.PF1_RBAR_NUM ( PF1_RBAR_NUM ),
.PF1_REVISION_ID ( PF1_REVISION_ID ),
.PF1_SRIOV_BAR0_APERTURE_SIZE ( PF1_SRIOV_BAR0_APERTURE_SIZE ),
.PF1_SRIOV_BAR0_CONTROL ( PF1_SRIOV_BAR0_CONTROL ),
.PF1_SRIOV_BAR1_APERTURE_SIZE ( PF1_SRIOV_BAR1_APERTURE_SIZE ),
.PF1_SRIOV_BAR1_CONTROL ( PF1_SRIOV_BAR1_CONTROL ),
.PF1_SRIOV_BAR2_APERTURE_SIZE ( PF1_SRIOV_BAR2_APERTURE_SIZE ),
.PF1_SRIOV_BAR2_CONTROL ( PF1_SRIOV_BAR2_CONTROL ),
.PF1_SRIOV_BAR3_APERTURE_SIZE ( PF1_SRIOV_BAR3_APERTURE_SIZE ),
.PF1_SRIOV_BAR3_CONTROL ( PF1_SRIOV_BAR3_CONTROL ),
.PF1_SRIOV_BAR4_APERTURE_SIZE ( PF1_SRIOV_BAR4_APERTURE_SIZE ),
.PF1_SRIOV_BAR4_CONTROL ( PF1_SRIOV_BAR4_CONTROL ),
.PF1_SRIOV_BAR5_APERTURE_SIZE ( PF1_SRIOV_BAR5_APERTURE_SIZE ),
.PF1_SRIOV_BAR5_CONTROL ( PF1_SRIOV_BAR5_CONTROL ),
.PF1_SRIOV_CAP_INITIAL_VF ( PF1_SRIOV_CAP_INITIAL_VF ),
.PF1_SRIOV_CAP_NEXTPTR ( PF1_SRIOV_CAP_NEXTPTR ),
.PF1_SRIOV_CAP_TOTAL_VF ( PF1_SRIOV_CAP_TOTAL_VF ),
.PF1_SRIOV_CAP_VER ( PF1_SRIOV_CAP_VER ),
.PF1_SRIOV_FIRST_VF_OFFSET ( PF1_SRIOV_FIRST_VF_OFFSET ),
.PF1_SRIOV_FUNC_DEP_LINK ( PF1_SRIOV_FUNC_DEP_LINK ),
.PF1_SRIOV_SUPPORTED_PAGE_SIZE ( PF1_SRIOV_SUPPORTED_PAGE_SIZE ),
.PF1_SRIOV_VF_DEVICE_ID ( PF1_SRIOV_VF_DEVICE_ID ),
.PF1_SUBSYSTEM_ID ( PF1_SUBSYSTEM_ID ),
.PF1_TPHR_CAP_DEV_SPECIFIC_MODE ( PF1_TPHR_CAP_DEV_SPECIFIC_MODE ),
.PF1_TPHR_CAP_ENABLE ( PF1_TPHR_CAP_ENABLE ),
.PF1_TPHR_CAP_INT_VEC_MODE ( PF1_TPHR_CAP_INT_VEC_MODE ),
.PF1_TPHR_CAP_NEXTPTR ( PF1_TPHR_CAP_NEXTPTR ),
.PF1_TPHR_CAP_ST_MODE_SEL ( PF1_TPHR_CAP_ST_MODE_SEL ),
.PF1_TPHR_CAP_ST_TABLE_LOC ( PF1_TPHR_CAP_ST_TABLE_LOC ),
.PF1_TPHR_CAP_ST_TABLE_SIZE ( PF1_TPHR_CAP_ST_TABLE_SIZE ),
.PF1_TPHR_CAP_VER ( PF1_TPHR_CAP_VER ),
.PL_DISABLE_EI_INFER_IN_L0 ( PL_DISABLE_EI_INFER_IN_L0 ),
.PL_DISABLE_GEN3_DC_BALANCE ( PL_DISABLE_GEN3_DC_BALANCE ),
.PL_DISABLE_SCRAMBLING ( PL_DISABLE_SCRAMBLING ),
.PL_DISABLE_UPCONFIG_CAPABLE ( PL_DISABLE_UPCONFIG_CAPABLE ),
.PL_EQ_ADAPT_DISABLE_COEFF_CHECK ( PL_EQ_ADAPT_DISABLE_COEFF_CHECK ),
.PL_EQ_ADAPT_DISABLE_PRESET_CHECK ( PL_EQ_ADAPT_DISABLE_PRESET_CHECK ),
.PL_EQ_ADAPT_ITER_COUNT ( PL_EQ_ADAPT_ITER_COUNT ),
.PL_EQ_ADAPT_REJECT_RETRY_COUNT ( PL_EQ_ADAPT_REJECT_RETRY_COUNT ),
.PL_EQ_BYPASS_PHASE23 ( PL_EQ_BYPASS_PHASE23 ),
.PL_EQ_SHORT_ADAPT_PHASE ( PL_EQ_SHORT_ADAPT_PHASE ),
.PL_LANE0_EQ_CONTROL ( PL_LANE0_EQ_CONTROL ),
.PL_LANE1_EQ_CONTROL ( PL_LANE1_EQ_CONTROL ),
.PL_LANE2_EQ_CONTROL ( PL_LANE2_EQ_CONTROL ),
.PL_LANE3_EQ_CONTROL ( PL_LANE3_EQ_CONTROL ),
.PL_LANE4_EQ_CONTROL ( PL_LANE4_EQ_CONTROL ),
.PL_LANE5_EQ_CONTROL ( PL_LANE5_EQ_CONTROL ),
.PL_LANE6_EQ_CONTROL ( PL_LANE6_EQ_CONTROL ),
.PL_LANE7_EQ_CONTROL ( PL_LANE7_EQ_CONTROL ),
.PL_LINK_CAP_MAX_LINK_SPEED ( PL_LINK_CAP_MAX_LINK_SPEED ),
.PL_LINK_CAP_MAX_LINK_WIDTH ( PL_LINK_CAP_MAX_LINK_WIDTH ),
.PL_N_FTS_COMCLK_GEN1 ( PL_N_FTS_COMCLK_GEN1 ),
.PL_N_FTS_COMCLK_GEN2 ( PL_N_FTS_COMCLK_GEN2 ),
.PL_N_FTS_COMCLK_GEN3 ( PL_N_FTS_COMCLK_GEN3 ),
.PL_N_FTS_GEN1 ( PL_N_FTS_GEN1 ),
.PL_N_FTS_GEN2 ( PL_N_FTS_GEN2 ),
.PL_N_FTS_GEN3 ( PL_N_FTS_GEN3 ),
// synthesis translate_off
.PL_SIM_FAST_LINK_TRAINING ( ENABLE_FAST_SIM_TRAINING ),
// synthesis translate_on
.PL_UPSTREAM_FACING ( PL_UPSTREAM_FACING ),
.PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ),
.PM_ASPML1_ENTRY_DELAY ( PM_ASPML1_ENTRY_DELAY ),
.PM_ENABLE_SLOT_POWER_CAPTURE ( PM_ENABLE_SLOT_POWER_CAPTURE ),
.PM_L1_REENTRY_DELAY ( PM_L1_REENTRY_DELAY ),
.PM_PME_SERVICE_TIMEOUT_DELAY ( PM_PME_SERVICE_TIMEOUT_DELAY ),
.PM_PME_TURNOFF_ACK_DELAY ( PM_PME_TURNOFF_ACK_DELAY ),
.SIM_VERSION ( SIM_VERSION ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SRIOV_CAP_ENABLE ( SRIOV_CAP_ENABLE ),
.TL_COMPL_TIMEOUT_REG0 ( TL_COMPL_TIMEOUT_REG0 ),
.TL_COMPL_TIMEOUT_REG1 ( TL_COMPL_TIMEOUT_REG1 ),
.TL_CREDITS_CD ( TL_CREDITS_CD ),
.TL_CREDITS_CH ( TL_CREDITS_CH ),
.TL_CREDITS_NPD ( TL_CREDITS_NPD ),
.TL_CREDITS_NPH ( TL_CREDITS_NPH ),
.TL_CREDITS_PD ( TL_CREDITS_PD ),
.TL_CREDITS_PH ( TL_CREDITS_PH ),
.TL_ENABLE_MESSAGE_RID_CHECK_ENABLE ( TL_ENABLE_MESSAGE_RID_CHECK_ENABLE ),
.TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE ( TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE ),
.TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE ( TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE ),
.TL_LEGACY_MODE_ENABLE ( TL_LEGACY_MODE_ENABLE ),
.TL_PF_ENABLE_REG ( TL_PF_ENABLE_REG ),
.TL_TAG_MGMT_ENABLE ( TL_TAG_MGMT_ENABLE ),
.VF0_CAPABILITY_POINTER ( VF0_CAPABILITY_POINTER ),
.VF0_MSIX_CAP_PBA_BIR ( VF0_MSIX_CAP_PBA_BIR ),
.VF0_MSIX_CAP_PBA_OFFSET ( VF0_MSIX_CAP_PBA_OFFSET ),
.VF0_MSIX_CAP_TABLE_BIR ( VF0_MSIX_CAP_TABLE_BIR ),
.VF0_MSIX_CAP_TABLE_OFFSET ( VF0_MSIX_CAP_TABLE_OFFSET ),
.VF0_MSIX_CAP_TABLE_SIZE ( VF0_MSIX_CAP_TABLE_SIZE ),
.VF0_MSI_CAP_MULTIMSGCAP ( VF0_MSI_CAP_MULTIMSGCAP ),
.VF0_PM_CAP_ID ( VF0_PM_CAP_ID ),
.VF0_PM_CAP_NEXTPTR ( VF0_PM_CAP_NEXTPTR ),
.VF0_PM_CAP_VER_ID ( VF0_PM_CAP_VER_ID ),
.VF1_MSIX_CAP_PBA_BIR ( VF1_MSIX_CAP_PBA_BIR ),
.VF1_MSIX_CAP_PBA_OFFSET ( VF1_MSIX_CAP_PBA_OFFSET ),
.VF1_MSIX_CAP_TABLE_BIR ( VF1_MSIX_CAP_TABLE_BIR ),
.VF1_MSIX_CAP_TABLE_OFFSET ( VF1_MSIX_CAP_TABLE_OFFSET ),
.VF1_MSIX_CAP_TABLE_SIZE ( VF1_MSIX_CAP_TABLE_SIZE ),
.VF1_MSI_CAP_MULTIMSGCAP ( VF1_MSI_CAP_MULTIMSGCAP ),
.VF1_PM_CAP_ID ( VF1_PM_CAP_ID ),
.VF1_PM_CAP_NEXTPTR ( VF1_PM_CAP_NEXTPTR ),
.VF1_PM_CAP_VER_ID ( VF1_PM_CAP_VER_ID ),
.VF2_MSIX_CAP_PBA_BIR ( VF2_MSIX_CAP_PBA_BIR ),
.VF2_MSIX_CAP_PBA_OFFSET ( VF2_MSIX_CAP_PBA_OFFSET ),
.VF2_MSIX_CAP_TABLE_BIR ( VF2_MSIX_CAP_TABLE_BIR ),
.VF2_MSIX_CAP_TABLE_OFFSET ( VF2_MSIX_CAP_TABLE_OFFSET ),
.VF2_MSIX_CAP_TABLE_SIZE ( VF2_MSIX_CAP_TABLE_SIZE ),
.VF2_MSI_CAP_MULTIMSGCAP ( VF2_MSI_CAP_MULTIMSGCAP ),
.VF2_PM_CAP_ID ( VF2_PM_CAP_ID ),
.VF2_PM_CAP_NEXTPTR ( VF2_PM_CAP_NEXTPTR ),
.VF2_PM_CAP_VER_ID ( VF2_PM_CAP_VER_ID ),
.VF3_MSIX_CAP_PBA_BIR ( VF3_MSIX_CAP_PBA_BIR ),
.VF3_MSIX_CAP_PBA_OFFSET ( VF3_MSIX_CAP_PBA_OFFSET ),
.VF3_MSIX_CAP_TABLE_BIR ( VF3_MSIX_CAP_TABLE_BIR ),
.VF3_MSIX_CAP_TABLE_OFFSET ( VF3_MSIX_CAP_TABLE_OFFSET ),
.VF3_MSIX_CAP_TABLE_SIZE ( VF3_MSIX_CAP_TABLE_SIZE ),
.VF3_MSI_CAP_MULTIMSGCAP ( VF3_MSI_CAP_MULTIMSGCAP ),
.VF3_PM_CAP_ID ( VF3_PM_CAP_ID ),
.VF3_PM_CAP_NEXTPTR ( VF3_PM_CAP_NEXTPTR ),
.VF3_PM_CAP_VER_ID ( VF3_PM_CAP_VER_ID ),
.VF4_MSIX_CAP_PBA_BIR ( VF4_MSIX_CAP_PBA_BIR ),
.VF4_MSIX_CAP_PBA_OFFSET ( VF4_MSIX_CAP_PBA_OFFSET ),
.VF4_MSIX_CAP_TABLE_BIR ( VF4_MSIX_CAP_TABLE_BIR ),
.VF4_MSIX_CAP_TABLE_OFFSET ( VF4_MSIX_CAP_TABLE_OFFSET ),
.VF4_MSIX_CAP_TABLE_SIZE ( VF4_MSIX_CAP_TABLE_SIZE ),
.VF4_MSI_CAP_MULTIMSGCAP ( VF4_MSI_CAP_MULTIMSGCAP ),
.VF4_PM_CAP_ID ( VF4_PM_CAP_ID ),
.VF4_PM_CAP_NEXTPTR ( VF4_PM_CAP_NEXTPTR ),
.VF4_PM_CAP_VER_ID ( VF4_PM_CAP_VER_ID ),
.VF5_MSIX_CAP_PBA_BIR ( VF5_MSIX_CAP_PBA_BIR ),
.VF5_MSIX_CAP_PBA_OFFSET ( VF5_MSIX_CAP_PBA_OFFSET ),
.VF5_MSIX_CAP_TABLE_BIR ( VF5_MSIX_CAP_TABLE_BIR ),
.VF5_MSIX_CAP_TABLE_OFFSET ( VF5_MSIX_CAP_TABLE_OFFSET ),
.VF5_MSIX_CAP_TABLE_SIZE ( VF5_MSIX_CAP_TABLE_SIZE ),
.VF5_MSI_CAP_MULTIMSGCAP ( VF5_MSI_CAP_MULTIMSGCAP ),
.VF5_PM_CAP_ID ( VF5_PM_CAP_ID ),
.VF5_PM_CAP_NEXTPTR ( VF5_PM_CAP_NEXTPTR ),
.VF5_PM_CAP_VER_ID ( VF5_PM_CAP_VER_ID ),
.IMPL_TARGET ( IMPL_TARGET ),
.NO_DECODE_LOGIC ( NO_DECODE_LOGIC ),
.INTERFACE_SPEED ( INTERFACE_SPEED ),
.COMPLETION_SPACE ( COMPLETION_SPACE )
) pcie_top_i (
.core_clk ( core_clk ), // I
.rec_clk ( rec_clk ), // I
.user_clk ( user_clk ), // I
.pipe_clk ( pipe_clk ), // I
.phy_rdy ( phy_rdy ), // I
.mmcm_lock ( mmcm_lock ), // I
.s_axis_rq_tlast ( s_axis_rq_tlast_wire ), // I
.s_axis_rq_tdata ( s_axis_rq_tdata_wire ), // I
.s_axis_rq_tuser ( s_axis_rq_tuser_wire ), // I
.s_axis_rq_tkeep ( s_axis_rq_tkeep_wire ), // I
.s_axis_rq_tready ( s_axis_rq_tready_wire ), // O
.s_axis_rq_tvalid ( s_axis_rq_tvalid_wire ), // I
.m_axis_rc_tdata ( m_axis_rc_tdata_wire ), // O
.m_axis_rc_tuser ( m_axis_rc_tuser_wire ), // O
.m_axis_rc_tlast ( m_axis_rc_tlast_wire ), // O
.m_axis_rc_tkeep ( m_axis_rc_tkeep_wire ), // O
.m_axis_rc_tvalid ( m_axis_rc_tvalid_wire ), // O
.m_axis_rc_tready ( m_axis_rc_tready_wire ), // I
.m_axis_cq_tdata ( m_axis_cq_tdata_wire ), // O
.m_axis_cq_tuser ( m_axis_cq_tuser_wire ), // O
.m_axis_cq_tlast ( m_axis_cq_tlast_wire ), // O
.m_axis_cq_tkeep ( m_axis_cq_tkeep_wire ), // O
.m_axis_cq_tvalid ( m_axis_cq_tvalid_wire ), // O
.m_axis_cq_tready ( m_axis_cq_tready_wire ), // I
.s_axis_cc_tdata ( s_axis_cc_tdata_wire ), // I
.s_axis_cc_tuser ( s_axis_cc_tuser_wire ), // I
.s_axis_cc_tlast ( s_axis_cc_tlast_wire ), // I
.s_axis_cc_tkeep ( s_axis_cc_tkeep_wire ), // I
.s_axis_cc_tvalid ( s_axis_cc_tvalid_wire ), // I
.s_axis_cc_tready ( s_axis_cc_tready_wire ), // O
.pcie_rq_seq_num ( pcie_rq_seq_num_wire ), // O
.pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld_wire ), // O
.pcie_rq_tag ( pcie_rq_tag_wire ), // O
.pcie_rq_tag_vld ( pcie_rq_tag_vld_wire ), // O
.pcie_tfc_nph_av ( pcie_tfc_nph_av_wire ), // O
.pcie_tfc_npd_av ( pcie_tfc_npd_av_wire ), // O
.pcie_cq_np_req ( pcie_cq_np_req_wire ), // I
.pcie_cq_np_req_count ( pcie_cq_np_req_count_wire ), // O
.cfg_mgmt_addr ( cfg_mgmt_addr ), // I
.cfg_mgmt_write ( cfg_mgmt_write_wire ), // I
.cfg_mgmt_write_data ( cfg_mgmt_write_data ), // I
.cfg_mgmt_byte_enable ( cfg_mgmt_byte_enable ), // I
.cfg_mgmt_read ( cfg_mgmt_read_wire ), // I
.cfg_mgmt_read_data ( cfg_mgmt_read_data ), // O
.cfg_mgmt_read_write_done ( cfg_mgmt_read_write_done ), // O
.cfg_mgmt_type1_cfg_reg_access ( cfg_mgmt_type1_cfg_reg_access ),// I
.cfg_phy_link_down ( cfg_phy_link_down_wire ), // O
.cfg_phy_link_status ( cfg_phy_link_status_wire ), // O
.cfg_negotiated_width ( cfg_negotiated_width ), // O
.cfg_current_speed ( cfg_current_speed ), // O
.cfg_max_payload ( cfg_max_payload ), // O
.cfg_max_read_req ( cfg_max_read_req ), // O
.cfg_function_status ( cfg_function_status ), // O
.cfg_function_power_state ( cfg_function_power_state ), // O
.cfg_vf_status ( cfg_vf_status ), // O
.cfg_vf_power_state ( cfg_vf_power_state ), // O
.cfg_link_power_state ( cfg_link_power_state ), // O
.cfg_err_cor_out ( cfg_err_cor_out ), // O
.cfg_err_nonfatal_out ( cfg_err_nonfatal_out ), // O
.cfg_err_fatal_out ( cfg_err_fatal_out ), // O
.cfg_local_error ( cfg_local_error ), // O
.cfg_ltr_enable ( cfg_ltr_enable ), // O
.cfg_ltssm_state ( cfg_ltssm_state_wire ), // O
.cfg_rcb_status ( cfg_rcb_status ), // O
.cfg_dpa_substate_change ( cfg_dpa_substate_change ), // O
.cfg_obff_enable ( cfg_obff_enable ), // O
.cfg_pl_status_change ( cfg_pl_status_change ), // O
.cfg_tph_requester_enable ( cfg_tph_requester_enable ), // O
.cfg_tph_st_mode ( cfg_tph_st_mode ), // O
.cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ), // O
.cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ), // O
.cfg_msg_received ( cfg_msg_received_wire ), // O
.cfg_msg_received_data ( cfg_msg_received_data_wire ), // O
.cfg_msg_received_type ( cfg_msg_received_type_wire ), // O
.cfg_msg_transmit ( cfg_msg_transmit_wire ), // I
.cfg_msg_transmit_type ( cfg_msg_transmit_type_wire ), // I
.cfg_msg_transmit_data ( cfg_msg_transmit_data_wire ), // I
.cfg_msg_transmit_done ( cfg_msg_transmit_done_wire ), // O
.cfg_fc_ph ( cfg_fc_ph_wire ), // O
.cfg_fc_pd ( cfg_fc_pd_wire ), // O
.cfg_fc_nph ( cfg_fc_nph_wire ), // O
.cfg_fc_npd ( cfg_fc_npd_wire ), // O
.cfg_fc_cplh ( cfg_fc_cplh_wire ), // O
.cfg_fc_cpld ( cfg_fc_cpld_wire ), // O
.cfg_fc_sel ( cfg_fc_sel_wire ), // I
.cfg_per_func_status_control ( cfg_per_func_status_control_wire ), // I
.cfg_per_func_status_data ( cfg_per_func_status_data ), // O
.cfg_per_function_number ( cfg_per_function_number ), // I
.cfg_per_function_output_request ( cfg_per_function_output_request_wire ), // I
.cfg_per_function_update_done ( cfg_per_function_update_done ), // O
.cfg_dsn ( cfg_dsn_wire ), // I
.cfg_power_state_change_ack ( cfg_power_state_change_ack_wire ), // I
.cfg_power_state_change_interrupt ( cfg_power_state_change_interrupt ), // O
.cfg_err_cor_in ( cfg_err_cor_in_wire ), // I
.cfg_err_uncor_in ( cfg_err_uncor_in_wire ), // I
.cfg_flr_in_process ( cfg_flr_in_process ), // O
.cfg_flr_done ( cfg_flr_done_wire ), // I
.cfg_vf_flr_in_process ( cfg_vf_flr_in_process ), // O
.cfg_vf_flr_done ( cfg_vf_flr_done_wire ), // I
.cfg_link_training_enable ( cfg_link_training_enable_wire ), // I
.cfg_interrupt_int ( cfg_interrupt_int_wire ), // I
.cfg_interrupt_pending ( cfg_interrupt_pending_wire ), // I
.cfg_interrupt_sent ( cfg_interrupt_sent ), // O
.cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ), // O
.cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ), // O
.cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ), // O
.cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ), // O
.cfg_interrupt_msi_data ( cfg_interrupt_msi_data ), // O
.cfg_interrupt_msi_select ( cfg_interrupt_msi_select_wire ), // I
.cfg_interrupt_msi_int ( cfg_interrupt_msi_int_wire ), // I
.cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status_wire ),// I
.cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ), // O
.cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ), // O
.cfg_interrupt_msix_enable ( cfg_interrupt_msix_enable ), // O
.cfg_interrupt_msix_mask ( cfg_interrupt_msix_mask ), // O
.cfg_interrupt_msix_vf_enable ( cfg_interrupt_msix_vf_enable ), // O
.cfg_interrupt_msix_vf_mask ( cfg_interrupt_msix_vf_mask ), // O
.cfg_interrupt_msix_data ( cfg_interrupt_msix_data ), // I
.cfg_interrupt_msix_address ( cfg_interrupt_msix_address ), // I
.cfg_interrupt_msix_int ( cfg_interrupt_msix_int_wire ), // I
.cfg_interrupt_msix_sent ( cfg_interrupt_msix_sent ), // O
.cfg_interrupt_msix_fail ( cfg_interrupt_msix_fail ), // O
.cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ), // I
.cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ), // I
.cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ), // I
.cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ), // I
.cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ), // I
.cfg_ext_read_received ( cfg_ext_read_received ), // O
.cfg_ext_write_received ( cfg_ext_write_received ), // O
.cfg_ext_register_number ( cfg_ext_register_number ), // O
.cfg_ext_function_number ( cfg_ext_function_number ), // O
.cfg_ext_write_data ( cfg_ext_write_data ), // O
.cfg_ext_write_byte_enable ( cfg_ext_write_byte_enable ), // O
.cfg_ext_read_data ( cfg_ext_read_data ), // I
.cfg_ext_read_data_valid ( cfg_ext_read_data_valid_wire ), // I
.cfg_dev_id ( cfg_dev_id ), // I
.cfg_vend_id ( cfg_vend_id ), // I
.cfg_rev_id ( cfg_rev_id ), // I
.cfg_subsys_id ( cfg_subsys_id ), // I
.cfg_subsys_vend_id ( cfg_subsys_vend_id ), // I
.cfg_hot_reset_out ( cfg_hot_reset_out_wire ), // O
.cfg_config_space_enable ( cfg_config_space_enable_wire ), // I
.cfg_req_pm_transition_l23_ready ( cfg_req_pm_transition_l23_ready_wire ), // I
.cfg_hot_reset_in ( cfg_hot_reset_in_wire ), // I
.cfg_ds_port_number ( cfg_ds_port_number_wire ), // I
.cfg_ds_bus_number ( cfg_ds_bus_number_wire ), // I
.cfg_ds_device_number ( cfg_ds_device_number_wire ), // I
.cfg_ds_function_number ( cfg_ds_function_number_wire ), // I
.user_tph_stt_address ( user_tph_stt_address_wire ), // I
.user_tph_function_num ( user_tph_function_num_wire ), // I
.user_tph_stt_read_data ( user_tph_stt_read_data ), // O
.user_tph_stt_read_data_valid ( user_tph_stt_read_data_valid ), // O
.user_tph_stt_read_enable ( user_tph_stt_read_enable_wire ), // I
.drp_rdy ( drp_rdy_wire ), // O
.drp_do ( drp_do_wire ), // O
.drp_clk ( drp_clk_wire ), // I
.drp_en ( drp_en_wire ), // I
.drp_we ( drp_we_wire ), // I
.drp_addr ( drp_addr_wire ), // I
.drp_di ( drp_di_wire ), // I
.pipe_tx_reset_gt ( pipe_tx_reset ),
.pipe_rx0_polarity_gt ( pipe_rx0_polarity ),
.pipe_rx1_polarity_gt ( pipe_rx1_polarity ),
.pipe_rx2_polarity_gt ( pipe_rx2_polarity ),
.pipe_rx3_polarity_gt ( pipe_rx3_polarity ),
.pipe_rx4_polarity_gt ( pipe_rx4_polarity ),
.pipe_rx5_polarity_gt ( pipe_rx5_polarity ),
.pipe_rx6_polarity_gt ( pipe_rx6_polarity ),
.pipe_rx7_polarity_gt ( pipe_rx7_polarity ),
.pipe_tx0_compliance_gt ( pipe_tx0_compliance ),
.pipe_tx1_compliance_gt ( pipe_tx1_compliance ),
.pipe_tx2_compliance_gt ( pipe_tx2_compliance ),
.pipe_tx3_compliance_gt ( pipe_tx3_compliance ),
.pipe_tx4_compliance_gt ( pipe_tx4_compliance ),
.pipe_tx5_compliance_gt ( pipe_tx5_compliance ),
.pipe_tx6_compliance_gt ( pipe_tx6_compliance ),
.pipe_tx7_compliance_gt ( pipe_tx7_compliance ),
.pipe_tx0_data_valid_gt ( ),
.pipe_tx1_data_valid_gt ( ),
.pipe_tx2_data_valid_gt ( ),
.pipe_tx3_data_valid_gt ( ),
.pipe_tx4_data_valid_gt ( ),
.pipe_tx5_data_valid_gt ( ),
.pipe_tx6_data_valid_gt ( ),
.pipe_tx7_data_valid_gt ( ),
.pipe_tx0_elec_idle_gt ( pipe_tx0_elec_idle ),
.pipe_tx1_elec_idle_gt ( pipe_tx1_elec_idle ),
.pipe_tx2_elec_idle_gt ( pipe_tx2_elec_idle ),
.pipe_tx3_elec_idle_gt ( pipe_tx3_elec_idle ),
.pipe_tx4_elec_idle_gt ( pipe_tx4_elec_idle ),
.pipe_tx5_elec_idle_gt ( pipe_tx5_elec_idle ),
.pipe_tx6_elec_idle_gt ( pipe_tx6_elec_idle ),
.pipe_tx7_elec_idle_gt ( pipe_tx7_elec_idle ),
.pipe_tx0_start_block_gt ( ),
.pipe_tx1_start_block_gt ( ),
.pipe_tx2_start_block_gt ( ),
.pipe_tx3_start_block_gt ( ),
.pipe_tx4_start_block_gt ( ),
.pipe_tx5_start_block_gt ( ),
.pipe_tx6_start_block_gt ( ),
.pipe_tx7_start_block_gt ( ),
.pipe_tx_deemph_gt ( pipe_tx_deemph ),
.pipe_tx_rcvr_det_gt ( pipe_tx_rcvr_det ),
.pipe_tx_rate_gt ( pipe_tx_rate ),
.pipe_tx_margin_gt ( pipe_tx_margin ),
.pipe_tx_swing_gt ( pipe_tx_swing ),
.pipe_tx_eqfs_gt ( pipe_tx_eqfs ),
.pipe_tx_eqlf_gt ( pipe_tx_eqlf ),
.pipe_rx0_eqcontrol_gt ( pipe_rx0_eqcontrol ),
.pipe_rx1_eqcontrol_gt ( pipe_rx1_eqcontrol ),
.pipe_rx2_eqcontrol_gt ( pipe_rx2_eqcontrol ),
.pipe_rx3_eqcontrol_gt ( pipe_rx3_eqcontrol ),
.pipe_rx4_eqcontrol_gt ( pipe_rx4_eqcontrol ),
.pipe_rx5_eqcontrol_gt ( pipe_rx5_eqcontrol ),
.pipe_rx6_eqcontrol_gt ( pipe_rx6_eqcontrol ),
.pipe_rx7_eqcontrol_gt ( pipe_rx7_eqcontrol ),
.pipe_tx0_char_is_k_gt ( pipe_tx0_char_is_k ),
.pipe_tx1_char_is_k_gt ( pipe_tx1_char_is_k ),
.pipe_tx2_char_is_k_gt ( pipe_tx2_char_is_k ),
.pipe_tx3_char_is_k_gt ( pipe_tx3_char_is_k ),
.pipe_tx4_char_is_k_gt ( pipe_tx4_char_is_k ),
.pipe_tx5_char_is_k_gt ( pipe_tx5_char_is_k ),
.pipe_tx6_char_is_k_gt ( pipe_tx6_char_is_k ),
.pipe_tx7_char_is_k_gt ( pipe_tx7_char_is_k ),
.pipe_tx0_eqcontrol_gt ( pipe_tx0_eqcontrol ),
.pipe_tx1_eqcontrol_gt ( pipe_tx1_eqcontrol ),
.pipe_tx2_eqcontrol_gt ( pipe_tx2_eqcontrol ),
.pipe_tx3_eqcontrol_gt ( pipe_tx3_eqcontrol ),
.pipe_tx4_eqcontrol_gt ( pipe_tx4_eqcontrol ),
.pipe_tx5_eqcontrol_gt ( pipe_tx5_eqcontrol ),
.pipe_tx6_eqcontrol_gt ( pipe_tx6_eqcontrol ),
.pipe_tx7_eqcontrol_gt ( pipe_tx7_eqcontrol ),
.pipe_tx0_powerdown_gt ( pipe_tx0_powerdown ),
.pipe_tx1_powerdown_gt ( pipe_tx1_powerdown ),
.pipe_tx2_powerdown_gt ( pipe_tx2_powerdown ),
.pipe_tx3_powerdown_gt ( pipe_tx3_powerdown ),
.pipe_tx4_powerdown_gt ( pipe_tx4_powerdown ),
.pipe_tx5_powerdown_gt ( pipe_tx5_powerdown ),
.pipe_tx6_powerdown_gt ( pipe_tx6_powerdown ),
.pipe_tx7_powerdown_gt ( pipe_tx7_powerdown ),
.pipe_tx0_syncheader_gt ( ),
.pipe_tx1_syncheader_gt ( ),
.pipe_tx2_syncheader_gt ( ),
.pipe_tx3_syncheader_gt ( ),
.pipe_tx4_syncheader_gt ( ),
.pipe_tx5_syncheader_gt ( ),
.pipe_tx6_syncheader_gt ( ),
.pipe_tx7_syncheader_gt ( ),
.pipe_rx0_eqpreset_gt ( pipe_rx0_eqpreset ),
.pipe_rx1_eqpreset_gt ( pipe_rx1_eqpreset ),
.pipe_rx2_eqpreset_gt ( pipe_rx2_eqpreset ),
.pipe_rx3_eqpreset_gt ( pipe_rx3_eqpreset ),
.pipe_rx4_eqpreset_gt ( pipe_rx4_eqpreset ),
.pipe_rx5_eqpreset_gt ( pipe_rx5_eqpreset ),
.pipe_rx6_eqpreset_gt ( pipe_rx6_eqpreset ),
.pipe_rx7_eqpreset_gt ( pipe_rx7_eqpreset ),
.pipe_tx0_data_gt ( pipe_tx0_data ),
.pipe_tx1_data_gt ( pipe_tx1_data ),
.pipe_tx2_data_gt ( pipe_tx2_data ),
.pipe_tx3_data_gt ( pipe_tx3_data ),
.pipe_tx4_data_gt ( pipe_tx4_data ),
.pipe_tx5_data_gt ( pipe_tx5_data ),
.pipe_tx6_data_gt ( pipe_tx6_data ),
.pipe_tx7_data_gt ( pipe_tx7_data ),
.pipe_rx0_eqlp_txpreset_gt ( pipe_rx0_eq_txpreset ),
.pipe_rx1_eqlp_txpreset_gt ( pipe_rx1_eq_txpreset ),
.pipe_rx2_eqlp_txpreset_gt ( pipe_rx2_eq_txpreset ),
.pipe_rx3_eqlp_txpreset_gt ( pipe_rx3_eq_txpreset ),
.pipe_rx4_eqlp_txpreset_gt ( pipe_rx4_eq_txpreset ),
.pipe_rx5_eqlp_txpreset_gt ( pipe_rx5_eq_txpreset ),
.pipe_rx6_eqlp_txpreset_gt ( pipe_rx6_eq_txpreset ),
.pipe_rx7_eqlp_txpreset_gt ( pipe_rx7_eq_txpreset ),
.pipe_tx0_eqpreset_gt ( pipe_tx0_eqpreset ),
.pipe_tx1_eqpreset_gt ( pipe_tx1_eqpreset ),
.pipe_tx2_eqpreset_gt ( pipe_tx2_eqpreset ),
.pipe_tx3_eqpreset_gt ( pipe_tx3_eqpreset ),
.pipe_tx4_eqpreset_gt ( pipe_tx4_eqpreset ),
.pipe_tx5_eqpreset_gt ( pipe_tx5_eqpreset ),
.pipe_tx6_eqpreset_gt ( pipe_tx6_eqpreset ),
.pipe_tx7_eqpreset_gt ( pipe_tx7_eqpreset ),
.pipe_rx0_eqlp_lffs_gt ( pipe_rx0_eq_lffs ),
.pipe_rx1_eqlp_lffs_gt ( pipe_rx1_eq_lffs ),
.pipe_rx2_eqlp_lffs_gt ( pipe_rx2_eq_lffs ),
.pipe_rx3_eqlp_lffs_gt ( pipe_rx3_eq_lffs ),
.pipe_rx4_eqlp_lffs_gt ( pipe_rx4_eq_lffs ),
.pipe_rx5_eqlp_lffs_gt ( pipe_rx5_eq_lffs ),
.pipe_rx6_eqlp_lffs_gt ( pipe_rx6_eq_lffs ),
.pipe_rx7_eqlp_lffs_gt ( pipe_rx7_eq_lffs ),
.pipe_tx0_eqdeemph_gt ( pipe_tx0_eqdeemph ),
.pipe_tx1_eqdeemph_gt ( pipe_tx1_eqdeemph ),
.pipe_tx2_eqdeemph_gt ( pipe_tx2_eqdeemph ),
.pipe_tx3_eqdeemph_gt ( pipe_tx3_eqdeemph ),
.pipe_tx4_eqdeemph_gt ( pipe_tx4_eqdeemph ),
.pipe_tx5_eqdeemph_gt ( pipe_tx5_eqdeemph ),
.pipe_tx6_eqdeemph_gt ( pipe_tx6_eqdeemph ),
.pipe_tx7_eqdeemph_gt ( pipe_tx7_eqdeemph ),
.pipe_rx_slide_gt ( pipe_rx_slide ),
.pipe_rx0_data_valid_gt ( pipe_rx0_data_valid ),
.pipe_rx1_data_valid_gt ( pipe_rx1_data_valid ),
.pipe_rx2_data_valid_gt ( pipe_rx2_data_valid ),
.pipe_rx3_data_valid_gt ( pipe_rx3_data_valid ),
.pipe_rx4_data_valid_gt ( pipe_rx4_data_valid ),
.pipe_rx5_data_valid_gt ( pipe_rx5_data_valid ),
.pipe_rx6_data_valid_gt ( pipe_rx6_data_valid ),
.pipe_rx7_data_valid_gt ( pipe_rx7_data_valid ),
.pipe_rx0_elec_idle_gt ( pipe_rx0_elec_idle ),
.pipe_rx1_elec_idle_gt ( pipe_rx1_elec_idle ),
.pipe_rx2_elec_idle_gt ( pipe_rx2_elec_idle ),
.pipe_rx3_elec_idle_gt ( pipe_rx3_elec_idle ),
.pipe_rx4_elec_idle_gt ( pipe_rx4_elec_idle ),
.pipe_rx5_elec_idle_gt ( pipe_rx5_elec_idle ),
.pipe_rx6_elec_idle_gt ( pipe_rx6_elec_idle ),
.pipe_rx7_elec_idle_gt ( pipe_rx7_elec_idle ),
.pipe_rx0_eqdone_gt ( pipe_rx0_eqdone ),
.pipe_rx1_eqdone_gt ( pipe_rx1_eqdone ),
.pipe_rx2_eqdone_gt ( pipe_rx2_eqdone ),
.pipe_rx3_eqdone_gt ( pipe_rx3_eqdone ),
.pipe_rx4_eqdone_gt ( pipe_rx4_eqdone ),
.pipe_rx5_eqdone_gt ( pipe_rx5_eqdone ),
.pipe_rx6_eqdone_gt ( pipe_rx6_eqdone ),
.pipe_rx7_eqdone_gt ( pipe_rx7_eqdone ),
.pipe_rx0_eqlp_adaptdone_gt ( pipe_rx0_eq_adapt_done ),
.pipe_rx1_eqlp_adaptdone_gt ( pipe_rx1_eq_adapt_done ),
.pipe_rx2_eqlp_adaptdone_gt ( pipe_rx2_eq_adapt_done ),
.pipe_rx3_eqlp_adaptdone_gt ( pipe_rx3_eq_adapt_done ),
.pipe_rx4_eqlp_adaptdone_gt ( pipe_rx4_eq_adapt_done ),
.pipe_rx5_eqlp_adaptdone_gt ( pipe_rx5_eq_adapt_done ),
.pipe_rx6_eqlp_adaptdone_gt ( pipe_rx6_eq_adapt_done ),
.pipe_rx7_eqlp_adaptdone_gt ( pipe_rx7_eq_adapt_done ),
.pipe_rx0_eqlp_lffs_sel_gt ( pipe_rx0_eq_lffs_sel ),
.pipe_rx1_eqlp_lffs_sel_gt ( pipe_rx1_eq_lffs_sel ),
.pipe_rx2_eqlp_lffs_sel_gt ( pipe_rx2_eq_lffs_sel ),
.pipe_rx3_eqlp_lffs_sel_gt ( pipe_rx3_eq_lffs_sel ),
.pipe_rx4_eqlp_lffs_sel_gt ( pipe_rx4_eq_lffs_sel ),
.pipe_rx5_eqlp_lffs_sel_gt ( pipe_rx5_eq_lffs_sel ),
.pipe_rx6_eqlp_lffs_sel_gt ( pipe_rx6_eq_lffs_sel ),
.pipe_rx7_eqlp_lffs_sel_gt ( pipe_rx7_eq_lffs_sel ),
.pipe_rx0_phy_status_gt ( pipe_rx0_phy_status ),
.pipe_rx1_phy_status_gt ( pipe_rx1_phy_status ),
.pipe_rx2_phy_status_gt ( pipe_rx2_phy_status ),
.pipe_rx3_phy_status_gt ( pipe_rx3_phy_status ),
.pipe_rx4_phy_status_gt ( pipe_rx4_phy_status ),
.pipe_rx5_phy_status_gt ( pipe_rx5_phy_status ),
.pipe_rx6_phy_status_gt ( pipe_rx6_phy_status ),
.pipe_rx7_phy_status_gt ( pipe_rx7_phy_status ),
.pipe_rx0_start_block_gt ( pipe_rx0_start_block ),
.pipe_rx1_start_block_gt ( pipe_rx1_start_block ),
.pipe_rx2_start_block_gt ( pipe_rx2_start_block ),
.pipe_rx3_start_block_gt ( pipe_rx3_start_block ),
.pipe_rx4_start_block_gt ( pipe_rx4_start_block ),
.pipe_rx5_start_block_gt ( pipe_rx5_start_block ),
.pipe_rx6_start_block_gt ( pipe_rx6_start_block ),
.pipe_rx7_start_block_gt ( pipe_rx7_start_block ),
.pipe_rx0_valid_gt ( pipe_rx0_valid ),
.pipe_rx1_valid_gt ( pipe_rx1_valid ),
.pipe_rx2_valid_gt ( pipe_rx2_valid ),
.pipe_rx3_valid_gt ( pipe_rx3_valid ),
.pipe_rx4_valid_gt ( pipe_rx4_valid ),
.pipe_rx5_valid_gt ( pipe_rx5_valid ),
.pipe_rx6_valid_gt ( pipe_rx6_valid ),
.pipe_rx7_valid_gt ( pipe_rx7_valid ),
.pipe_tx0_eqdone_gt ( pipe_tx0_eqdone ),
.pipe_tx1_eqdone_gt ( pipe_tx1_eqdone ),
.pipe_tx2_eqdone_gt ( pipe_tx2_eqdone ),
.pipe_tx3_eqdone_gt ( pipe_tx3_eqdone ),
.pipe_tx4_eqdone_gt ( pipe_tx4_eqdone ),
.pipe_tx5_eqdone_gt ( pipe_tx5_eqdone ),
.pipe_tx6_eqdone_gt ( pipe_tx6_eqdone ),
.pipe_tx7_eqdone_gt ( pipe_tx7_eqdone ),
.pipe_rx0_eqlp_new_txcoef_forpreset_gt ( pipe_rx0_eq_new_txcoeff ),
.pipe_rx1_eqlp_new_txcoef_forpreset_gt ( pipe_rx1_eq_new_txcoeff ),
.pipe_rx2_eqlp_new_txcoef_forpreset_gt ( pipe_rx2_eq_new_txcoeff ),
.pipe_rx3_eqlp_new_txcoef_forpreset_gt ( pipe_rx3_eq_new_txcoeff ),
.pipe_rx4_eqlp_new_txcoef_forpreset_gt ( pipe_rx4_eq_new_txcoeff ),
.pipe_rx5_eqlp_new_txcoef_forpreset_gt ( pipe_rx5_eq_new_txcoeff ),
.pipe_rx6_eqlp_new_txcoef_forpreset_gt ( pipe_rx6_eq_new_txcoeff ),
.pipe_rx7_eqlp_new_txcoef_forpreset_gt ( pipe_rx7_eq_new_txcoeff ),
.pipe_tx0_eqcoeff_gt ( pipe_tx0_eqcoeff ),
.pipe_tx1_eqcoeff_gt ( pipe_tx1_eqcoeff ),
.pipe_tx2_eqcoeff_gt ( pipe_tx2_eqcoeff ),
.pipe_tx3_eqcoeff_gt ( pipe_tx3_eqcoeff ),
.pipe_tx4_eqcoeff_gt ( pipe_tx4_eqcoeff ),
.pipe_tx5_eqcoeff_gt ( pipe_tx5_eqcoeff ),
.pipe_tx6_eqcoeff_gt ( pipe_tx6_eqcoeff ),
.pipe_tx7_eqcoeff_gt ( pipe_tx7_eqcoeff ),
.pipe_rx0_char_is_k_gt ( pipe_rx0_char_is_k ),
.pipe_rx1_char_is_k_gt ( pipe_rx1_char_is_k ),
.pipe_rx2_char_is_k_gt ( pipe_rx2_char_is_k ),
.pipe_rx3_char_is_k_gt ( pipe_rx3_char_is_k ),
.pipe_rx4_char_is_k_gt ( pipe_rx4_char_is_k ),
.pipe_rx5_char_is_k_gt ( pipe_rx5_char_is_k ),
.pipe_rx6_char_is_k_gt ( pipe_rx6_char_is_k ),
.pipe_rx7_char_is_k_gt ( pipe_rx7_char_is_k ),
.pipe_rx0_syncheader_gt ( pipe_rx0_syncheader ),
.pipe_rx1_syncheader_gt ( pipe_rx1_syncheader ),
.pipe_rx2_syncheader_gt ( pipe_rx2_syncheader ),
.pipe_rx3_syncheader_gt ( pipe_rx3_syncheader ),
.pipe_rx4_syncheader_gt ( pipe_rx4_syncheader ),
.pipe_rx5_syncheader_gt ( pipe_rx5_syncheader ),
.pipe_rx6_syncheader_gt ( pipe_rx6_syncheader ),
.pipe_rx7_syncheader_gt ( pipe_rx7_syncheader ),
.pipe_rx0_status_gt ( pipe_rx0_status ),
.pipe_rx1_status_gt ( pipe_rx1_status ),
.pipe_rx2_status_gt ( pipe_rx2_status ),
.pipe_rx3_status_gt ( pipe_rx3_status ),
.pipe_rx4_status_gt ( pipe_rx4_status ),
.pipe_rx5_status_gt ( pipe_rx5_status ),
.pipe_rx6_status_gt ( pipe_rx6_status ),
.pipe_rx7_status_gt ( pipe_rx7_status ),
.pipe_rx0_data_gt ( pipe_rx0_data ),
.pipe_rx1_data_gt ( pipe_rx1_data ),
.pipe_rx2_data_gt ( pipe_rx2_data ),
.pipe_rx3_data_gt ( pipe_rx3_data ),
.pipe_rx4_data_gt ( pipe_rx4_data ),
.pipe_rx5_data_gt ( pipe_rx5_data ),
.pipe_rx6_data_gt ( pipe_rx6_data ),
.pipe_rx7_data_gt ( pipe_rx7_data ),
.pipe_rx_syncdone_gt ( pipe_rx_syncdone )
);
pcie3_7x_0_gt_top #(
.TCQ ( TCQ ),
.PL_LINK_CAP_MAX_LINK_WIDTH ( PL_LINK_CAP_MAX_LINK_WIDTH ),
.PL_LINK_CAP_MAX_LINK_SPEED ( PL_LINK_CAP_MAX_LINK_SPEED ),
.REF_CLK_FREQ ( REF_CLK_FREQ ),
.USER_CLK2_FREQ ( USER_CLK2_FREQ ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.PCIE_ASYNC_EN ( PCIE_ASYNC_EN ),
// synthesis translate_off
.PL_SIM_FAST_LINK_TRAINING ( ENABLE_FAST_SIM_TRAINING ),
// synthesis translate_on
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PCIE_EXT_GT_COMMON ( PCIE_EXT_GT_COMMON ),
.EXT_CH_GT_DRP ( EXT_CH_GT_DRP ),
.TX_MARGIN_FULL_0 ( TX_MARGIN_FULL_0 ),
.TX_MARGIN_FULL_1 ( TX_MARGIN_FULL_1 ),
.TX_MARGIN_FULL_2 ( TX_MARGIN_FULL_2 ),
.TX_MARGIN_FULL_3 ( TX_MARGIN_FULL_3 ),
.TX_MARGIN_FULL_4 ( TX_MARGIN_FULL_4 ),
.TX_MARGIN_LOW_0 ( TX_MARGIN_LOW_0 ),
.TX_MARGIN_LOW_1 ( TX_MARGIN_LOW_1 ),
.TX_MARGIN_LOW_2 ( TX_MARGIN_LOW_2 ),
.TX_MARGIN_LOW_3 ( TX_MARGIN_LOW_3 ),
.TX_MARGIN_LOW_4 ( TX_MARGIN_LOW_4 ),
.PCIE_TXBUF_EN ( PCIE_TXBUF_EN ),
.PCIE_GT_DEVICE ( PCIE_GT_DEVICE ),
.PCIE_CHAN_BOND ( PCIE_CHAN_BOND ),
.PCIE_CHAN_BOND_EN ( PCIE_CHAN_BOND_EN ),
.PCIE_USE_MODE ( PCIE_USE_MODE ),
.PCIE_LPM_DFE ( PCIE_LPM_DFE ),
.PCIE_LINK_SPEED ( PCIE_LINK_SPEED )
) gt_top_i(
//------------------------------------------------------------------------------------//
// Pipe Per-Link Signals //
//------------------------------------------------------------------------------------//
.pipe_tx_rcvr_det ( pipe_tx_rcvr_det ),
.pipe_tx_reset ( pipe_tx_reset ),
.pipe_tx_rate ( pipe_tx_rate ),
.pipe_tx_deemph ( pipe_tx_deemph ),
.pipe_tx_margin ( pipe_tx_margin ),
.pipe_tx_swing ( pipe_tx_swing ),
.pipe_txeq_fs ( pipe_tx_eqfs ),
.pipe_txeq_lf ( pipe_tx_eqlf ),
.pipe_rxslide ( pipe_rx_slide ),
.pipe_rxsync_done ( pipe_rx_syncdone ),
.cfg_ltssm_state ( cfg_ltssm_state_wire ),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k ( pipe_rx0_char_is_k ),
.pipe_rx0_data ( pipe_rx0_data ),
.pipe_rx0_valid ( pipe_rx0_valid ),
.pipe_rx0_chanisaligned ( ),
.pipe_rx0_status ( pipe_rx0_status ),
.pipe_rx0_phy_status ( pipe_rx0_phy_status ),
.pipe_rx0_elec_idle ( pipe_rx0_elec_idle ),
.pipe_rx0_polarity ( pipe_rx0_polarity ),
.pipe_tx0_compliance ( pipe_tx0_compliance ),
.pipe_tx0_char_is_k ( pipe_tx0_char_is_k ),
.pipe_tx0_data ( pipe_tx0_data ),
.pipe_tx0_elec_idle ( pipe_tx0_elec_idle ),
.pipe_tx0_powerdown ( pipe_tx0_powerdown ),
.pipe_tx0_eqcontrol ( pipe_tx0_eqcontrol ),
.pipe_tx0_eqpreset ( pipe_tx0_eqpreset ),
.pipe_tx0_eqdeemph ( pipe_tx0_eqdeemph ),
.pipe_tx0_eqdone ( pipe_tx0_eqdone ),
.pipe_tx0_eqcoeff ( pipe_tx0_eqcoeff ),
.pipe_rx0_eqcontrol ( pipe_rx0_eqcontrol ),
.pipe_rx0_eqpreset ( pipe_rx0_eqpreset ),
.pipe_rx0_eq_lffs ( pipe_rx0_eq_lffs ),
.pipe_rx0_eq_txpreset ( pipe_rx0_eq_txpreset ),
.pipe_rx0_eq_new_txcoeff ( pipe_rx0_eq_new_txcoeff ),
.pipe_rx0_eq_lffs_sel ( pipe_rx0_eq_lffs_sel ),
.pipe_rx0_eq_adapt_done ( pipe_rx0_eq_adapt_done ),
.pipe_rx0_eqdone ( pipe_rx0_eqdone ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k ( pipe_rx1_char_is_k ),
.pipe_rx1_data ( pipe_rx1_data ),
.pipe_rx1_valid ( pipe_rx1_valid ),
.pipe_rx1_chanisaligned ( ),
.pipe_rx1_status ( pipe_rx1_status ),
.pipe_rx1_phy_status ( pipe_rx1_phy_status ),
.pipe_rx1_elec_idle ( pipe_rx1_elec_idle ),
.pipe_rx1_polarity ( pipe_rx1_polarity ),
.pipe_tx1_compliance ( pipe_tx1_compliance ),
.pipe_tx1_char_is_k ( pipe_tx1_char_is_k ),
.pipe_tx1_data ( pipe_tx1_data ),
.pipe_tx1_elec_idle ( pipe_tx1_elec_idle ),
.pipe_tx1_powerdown ( pipe_tx1_powerdown ),
.pipe_tx1_eqcontrol ( pipe_tx1_eqcontrol ),
.pipe_tx1_eqpreset ( pipe_tx1_eqpreset ),
.pipe_tx1_eqdeemph ( pipe_tx1_eqdeemph ),
.pipe_tx1_eqdone ( pipe_tx1_eqdone ),
.pipe_tx1_eqcoeff ( pipe_tx1_eqcoeff ),
.pipe_rx1_eqcontrol ( pipe_rx1_eqcontrol ),
.pipe_rx1_eqpreset ( pipe_rx1_eqpreset ),
.pipe_rx1_eq_lffs ( pipe_rx1_eq_lffs ),
.pipe_rx1_eq_txpreset ( pipe_rx1_eq_txpreset ),
.pipe_rx1_eq_new_txcoeff ( pipe_rx1_eq_new_txcoeff ),
.pipe_rx1_eq_lffs_sel ( pipe_rx1_eq_lffs_sel ),
.pipe_rx1_eq_adapt_done ( pipe_rx1_eq_adapt_done ),
.pipe_rx1_eqdone ( pipe_rx1_eqdone ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k ( pipe_rx2_char_is_k ),
.pipe_rx2_data ( pipe_rx2_data ),
.pipe_rx2_valid ( pipe_rx2_valid ),
.pipe_rx2_chanisaligned ( ),
.pipe_rx2_status ( pipe_rx2_status ),
.pipe_rx2_phy_status ( pipe_rx2_phy_status ),
.pipe_rx2_elec_idle ( pipe_rx2_elec_idle ),
.pipe_rx2_polarity ( pipe_rx2_polarity ),
.pipe_tx2_compliance ( pipe_tx2_compliance ),
.pipe_tx2_char_is_k ( pipe_tx2_char_is_k ),
.pipe_tx2_data ( pipe_tx2_data ),
.pipe_tx2_elec_idle ( pipe_tx2_elec_idle ),
.pipe_tx2_powerdown ( pipe_tx2_powerdown ),
.pipe_tx2_eqcontrol ( pipe_tx2_eqcontrol ),
.pipe_tx2_eqpreset ( pipe_tx2_eqpreset ),
.pipe_tx2_eqdeemph ( pipe_tx2_eqdeemph ),
.pipe_tx2_eqdone ( pipe_tx2_eqdone ),
.pipe_tx2_eqcoeff ( pipe_tx2_eqcoeff ),
.pipe_rx2_eqcontrol ( pipe_rx2_eqcontrol ),
.pipe_rx2_eqpreset ( pipe_rx2_eqpreset ),
.pipe_rx2_eq_lffs ( pipe_rx2_eq_lffs ),
.pipe_rx2_eq_txpreset ( pipe_rx2_eq_txpreset ),
.pipe_rx2_eq_new_txcoeff ( pipe_rx2_eq_new_txcoeff ),
.pipe_rx2_eq_lffs_sel ( pipe_rx2_eq_lffs_sel ),
.pipe_rx2_eq_adapt_done ( pipe_rx2_eq_adapt_done ),
.pipe_rx2_eqdone ( pipe_rx2_eqdone ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k ( pipe_rx3_char_is_k ),
.pipe_rx3_data ( pipe_rx3_data ),
.pipe_rx3_valid ( pipe_rx3_valid ),
.pipe_rx3_chanisaligned ( ),
.pipe_rx3_status ( pipe_rx3_status ),
.pipe_rx3_phy_status ( pipe_rx3_phy_status ),
.pipe_rx3_elec_idle ( pipe_rx3_elec_idle ),
.pipe_rx3_polarity ( pipe_rx3_polarity ),
.pipe_tx3_compliance ( pipe_tx3_compliance ),
.pipe_tx3_char_is_k ( pipe_tx3_char_is_k ),
.pipe_tx3_data ( pipe_tx3_data ),
.pipe_tx3_elec_idle ( pipe_tx3_elec_idle ),
.pipe_tx3_powerdown ( pipe_tx3_powerdown ),
.pipe_tx3_eqcontrol ( pipe_tx3_eqcontrol ),
.pipe_tx3_eqpreset ( pipe_tx3_eqpreset ),
.pipe_tx3_eqdeemph ( pipe_tx3_eqdeemph ),
.pipe_tx3_eqdone ( pipe_tx3_eqdone ),
.pipe_tx3_eqcoeff ( pipe_tx3_eqcoeff ),
.pipe_rx3_eqcontrol ( pipe_rx3_eqcontrol ),
.pipe_rx3_eqpreset ( pipe_rx3_eqpreset ),
.pipe_rx3_eq_lffs ( pipe_rx3_eq_lffs ),
.pipe_rx3_eq_txpreset ( pipe_rx3_eq_txpreset ),
.pipe_rx3_eq_new_txcoeff ( pipe_rx3_eq_new_txcoeff ),
.pipe_rx3_eq_lffs_sel ( pipe_rx3_eq_lffs_sel ),
.pipe_rx3_eq_adapt_done ( pipe_rx3_eq_adapt_done ),
.pipe_rx3_eqdone ( pipe_rx3_eqdone ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k ( pipe_rx4_char_is_k ),
.pipe_rx4_data ( pipe_rx4_data ),
.pipe_rx4_valid ( pipe_rx4_valid ),
.pipe_rx4_chanisaligned ( ),
.pipe_rx4_status ( pipe_rx4_status ),
.pipe_rx4_phy_status ( pipe_rx4_phy_status ),
.pipe_rx4_elec_idle ( pipe_rx4_elec_idle ),
.pipe_rx4_polarity ( pipe_rx4_polarity ),
.pipe_tx4_compliance ( pipe_tx4_compliance ),
.pipe_tx4_char_is_k ( pipe_tx4_char_is_k ),
.pipe_tx4_data ( pipe_tx4_data ),
.pipe_tx4_elec_idle ( pipe_tx4_elec_idle ),
.pipe_tx4_powerdown ( pipe_tx4_powerdown ),
.pipe_tx4_eqcontrol ( pipe_tx4_eqcontrol ),
.pipe_tx4_eqpreset ( pipe_tx4_eqpreset ),
.pipe_tx4_eqdeemph ( pipe_tx4_eqdeemph ),
.pipe_tx4_eqdone ( pipe_tx4_eqdone ),
.pipe_tx4_eqcoeff ( pipe_tx4_eqcoeff ),
.pipe_rx4_eqcontrol ( pipe_rx4_eqcontrol ),
.pipe_rx4_eqpreset ( pipe_rx4_eqpreset ),
.pipe_rx4_eq_lffs ( pipe_rx4_eq_lffs ),
.pipe_rx4_eq_txpreset ( pipe_rx4_eq_txpreset ),
.pipe_rx4_eq_new_txcoeff ( pipe_rx4_eq_new_txcoeff ),
.pipe_rx4_eq_lffs_sel ( pipe_rx4_eq_lffs_sel ),
.pipe_rx4_eq_adapt_done ( pipe_rx4_eq_adapt_done ),
.pipe_rx4_eqdone ( pipe_rx4_eqdone ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k ( pipe_rx5_char_is_k ),
.pipe_rx5_data ( pipe_rx5_data ),
.pipe_rx5_valid ( pipe_rx5_valid ),
.pipe_rx5_chanisaligned ( ),
.pipe_rx5_status ( pipe_rx5_status ),
.pipe_rx5_phy_status ( pipe_rx5_phy_status ),
.pipe_rx5_elec_idle ( pipe_rx5_elec_idle ),
.pipe_rx5_polarity ( pipe_rx5_polarity ),
.pipe_tx5_compliance ( pipe_tx5_compliance ),
.pipe_tx5_char_is_k ( pipe_tx5_char_is_k ),
.pipe_tx5_data ( pipe_tx5_data ),
.pipe_tx5_elec_idle ( pipe_tx5_elec_idle ),
.pipe_tx5_powerdown ( pipe_tx5_powerdown ),
.pipe_tx5_eqcontrol ( pipe_tx5_eqcontrol ),
.pipe_tx5_eqpreset ( pipe_tx5_eqpreset ),
.pipe_tx5_eqdeemph ( pipe_tx5_eqdeemph ),
.pipe_tx5_eqdone ( pipe_tx5_eqdone ),
.pipe_tx5_eqcoeff ( pipe_tx5_eqcoeff ),
.pipe_rx5_eqcontrol ( pipe_rx5_eqcontrol ),
.pipe_rx5_eqpreset ( pipe_rx5_eqpreset ),
.pipe_rx5_eq_lffs ( pipe_rx5_eq_lffs ),
.pipe_rx5_eq_txpreset ( pipe_rx5_eq_txpreset ),
.pipe_rx5_eq_new_txcoeff ( pipe_rx5_eq_new_txcoeff ),
.pipe_rx5_eq_lffs_sel ( pipe_rx5_eq_lffs_sel ),
.pipe_rx5_eq_adapt_done ( pipe_rx5_eq_adapt_done ),
.pipe_rx5_eqdone ( pipe_rx5_eqdone ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k ( pipe_rx6_char_is_k ),
.pipe_rx6_data ( pipe_rx6_data ),
.pipe_rx6_valid ( pipe_rx6_valid ),
.pipe_rx6_chanisaligned ( ),
.pipe_rx6_status ( pipe_rx6_status ),
.pipe_rx6_phy_status ( pipe_rx6_phy_status ),
.pipe_rx6_elec_idle ( pipe_rx6_elec_idle ),
.pipe_rx6_polarity ( pipe_rx6_polarity ),
.pipe_tx6_compliance ( pipe_tx6_compliance ),
.pipe_tx6_char_is_k ( pipe_tx6_char_is_k ),
.pipe_tx6_data ( pipe_tx6_data ),
.pipe_tx6_elec_idle ( pipe_tx6_elec_idle ),
.pipe_tx6_powerdown ( pipe_tx6_powerdown ),
.pipe_tx6_eqcontrol ( pipe_tx6_eqcontrol ),
.pipe_tx6_eqpreset ( pipe_tx6_eqpreset ),
.pipe_tx6_eqdeemph ( pipe_tx6_eqdeemph ),
.pipe_tx6_eqdone ( pipe_tx6_eqdone ),
.pipe_tx6_eqcoeff ( pipe_tx6_eqcoeff ),
.pipe_rx6_eqcontrol ( pipe_rx6_eqcontrol ),
.pipe_rx6_eqpreset ( pipe_rx6_eqpreset ),
.pipe_rx6_eq_lffs ( pipe_rx6_eq_lffs ),
.pipe_rx6_eq_txpreset ( pipe_rx6_eq_txpreset ),
.pipe_rx6_eq_new_txcoeff ( pipe_rx6_eq_new_txcoeff ),
.pipe_rx6_eq_lffs_sel ( pipe_rx6_eq_lffs_sel ),
.pipe_rx6_eq_adapt_done ( pipe_rx6_eq_adapt_done ),
.pipe_rx6_eqdone ( pipe_rx6_eqdone ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k ( pipe_rx7_char_is_k ),
.pipe_rx7_data ( pipe_rx7_data ),
.pipe_rx7_valid ( pipe_rx7_valid ),
.pipe_rx7_chanisaligned ( ),
.pipe_rx7_status ( pipe_rx7_status ),
.pipe_rx7_phy_status ( pipe_rx7_phy_status ),
.pipe_rx7_elec_idle ( pipe_rx7_elec_idle ),
.pipe_rx7_polarity ( pipe_rx7_polarity ),
.pipe_tx7_compliance ( pipe_tx7_compliance ),
.pipe_tx7_char_is_k ( pipe_tx7_char_is_k ),
.pipe_tx7_data ( pipe_tx7_data ),
.pipe_tx7_elec_idle ( pipe_tx7_elec_idle ),
.pipe_tx7_powerdown ( pipe_tx7_powerdown ),
.pipe_tx7_eqcontrol ( pipe_tx7_eqcontrol ),
.pipe_tx7_eqpreset ( pipe_tx7_eqpreset ),
.pipe_tx7_eqdeemph ( pipe_tx7_eqdeemph ),
.pipe_tx7_eqdone ( pipe_tx7_eqdone ),
.pipe_tx7_eqcoeff ( pipe_tx7_eqcoeff ),
.pipe_rx7_eqcontrol ( pipe_rx7_eqcontrol ),
.pipe_rx7_eqpreset ( pipe_rx7_eqpreset ),
.pipe_rx7_eq_lffs ( pipe_rx7_eq_lffs ),
.pipe_rx7_eq_txpreset ( pipe_rx7_eq_txpreset ),
.pipe_rx7_eq_new_txcoeff ( pipe_rx7_eq_new_txcoeff ),
.pipe_rx7_eq_lffs_sel ( pipe_rx7_eq_lffs_sel ),
.pipe_rx7_eq_adapt_done ( pipe_rx7_eq_adapt_done ),
.pipe_rx7_eqdone ( pipe_rx7_eqdone ),
// Manual PCIe Equalization Control
.pipe_rxeq_user_en ( pipe_rxeq_user_en[PL_LINK_CAP_MAX_LINK_WIDTH-1:0] ),
.pipe_rxeq_user_txcoeff ( pipe_rxeq_user_txcoeff[18*PL_LINK_CAP_MAX_LINK_WIDTH-1:0] ),
.pipe_rxeq_user_mode ( {PL_LINK_CAP_MAX_LINK_WIDTH{1'b0}} ),
.drp_rdy ( drp_rdy_wire ),
.drp_do ( drp_do_wire ),
.drp_clk ( dt_654524_drp_clk ),
.drp_en ( dt_654524_drp_en ),
.drp_we ( dt_654524_drp_we ),
.drp_addr ( dt_654524_drp_addr ),
.drp_di ( dt_654524_drp_di ),
// PCI Express signals
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
//---------- PIPE Clock & Reset Ports ------------------
.pipe_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n ),
.rec_clk ( rec_clk ),
.pipe_pclk ( pipe_clk ),
.core_clk ( core_clk ),
.user_clk ( user_clk ),
.phy_rdy ( phy_rdy ),
.mmcm_lock ( mmcm_lock ),
.pipe_mmcm_rst_n ( pipe_mmcm_rst_n),
// ---------- Shared Logic Internal------------------
.INT_PCLK_OUT_SLAVE ( int_pclk_out_slave ),
.INT_RXUSRCLK_OUT ( int_pipe_rxusrclk_out ),
.INT_RXOUTCLK_OUT ( int_rxoutclk_out ),
.INT_DCLK_OUT ( int_dclk_out ),
.INT_USERCLK1_OUT ( int_userclk1_out ),
.INT_USERCLK2_OUT ( int_userclk2_out),
.INT_OOBCLK_OUT ( int_oobclk_out),
.INT_QPLLLOCK_OUT ( int_qplllock_out ),
.INT_QPLLOUTCLK_OUT ( int_qplloutclk_out ),
.INT_QPLLOUTREFCLK_OUT ( int_qplloutrefclk_out ),
.INT_PCLK_SEL_SLAVE ( int_pclk_sel_slave ),
// ---------- Shared Logic External------------------
//External GT COMMON Ports
.qpll_drp_crscode ( qpll_drp_crscode ),
.qpll_drp_fsm ( qpll_drp_fsm ),
.qpll_drp_done ( qpll_drp_done ),
.qpll_drp_reset ( qpll_drp_reset ),
.qpll_qplllock ( qpll_qplllock ),
.qpll_qplloutclk ( qpll_qplloutclk ),
.qpll_qplloutrefclk ( qpll_qplloutrefclk ),
.qpll_qplld ( qpll_qplld ),
.qpll_qpllreset ( qpll_qpllreset ),
.qpll_drp_clk ( qpll_drp_clk ),
.qpll_drp_rst_n ( qpll_drp_rst_n ),
.qpll_drp_ovrd ( qpll_drp_ovrd ),
.qpll_drp_gen3 ( qpll_drp_gen3),
.qpll_drp_start ( qpll_drp_start ),
//External Clock Ports
.PIPE_PCLK_IN ( pipe_pclk_in ),
.PIPE_RXUSRCLK_IN ( pipe_rxusrclk_in ),
.PIPE_RXOUTCLK_IN ( pipe_rxoutclk_in ),
.PIPE_DCLK_IN ( pipe_dclk_in ),
.PIPE_USERCLK1_IN ( pipe_userclk1_in ),
.PIPE_USERCLK2_IN ( pipe_userclk2_in ),
.PIPE_OOBCLK_IN ( pipe_oobclk_in ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN_wire ),
.PIPE_TXOUTCLK_OUT ( pipe_txoutclk_out ),
.PIPE_RXOUTCLK_OUT ( pipe_rxoutclk_out ),
.PIPE_PCLK_SEL_OUT ( pipe_pclk_sel_out ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT_wire ),
//----------TRANSCEIVER DEBUG EOU------------------
.ext_ch_gt_drpclk (ext_ch_gt_drpclk),
.ext_ch_gt_drpaddr (ext_ch_gt_drpaddr),
.ext_ch_gt_drpen (ext_ch_gt_drpen),
.ext_ch_gt_drpdi (ext_ch_gt_drpdi),
.ext_ch_gt_drpwe (ext_ch_gt_drpwe),
.ext_ch_gt_drpdo (ext_ch_gt_drpdo),
.ext_ch_gt_drprdy (ext_ch_gt_drprdy),
//---------- PRBS/Loopback Ports -----------------------
.PIPE_TXPRBSSEL ( pipe_txprbssel ),
.PIPE_RXPRBSSEL ( pipe_rxprbssel ),
.PIPE_TXPRBSFORCEERR ( pipe_txprbsforceerr ),
.PIPE_RXPRBSCNTRESET ( pipe_rxprbscntreset ),
.PIPE_LOOPBACK ( pipe_loopback),
.PIPE_RXPRBSERR ( pipe_rxprbserr),
.PIPE_TXINHIBIT ( pipe_txinhibit),
.PIPE_PCSRSVDIN ( {PL_LINK_CAP_MAX_LINK_WIDTH{16'b0}} ),
//---------- Transceiver Debug FSM Ports ---------------------------------
.PIPE_RST_FSM (pipe_rst_fsm),
.PIPE_QRST_FSM (pipe_qrst_fsm),
.PIPE_RATE_FSM (pipe_rate_fsm ),
.PIPE_SYNC_FSM_TX (pipe_sync_fsm_tx ),
.PIPE_SYNC_FSM_RX (pipe_sync_fsm_rx ),
.PIPE_DRP_FSM (pipe_drp_fsm ),
.PIPE_RST_IDLE (pipe_rst_idle ),
.PIPE_QRST_IDLE (pipe_qrst_idle ),
.PIPE_RATE_IDLE (pipe_rate_idle ),
.PIPE_EYESCANDATAERROR ( pipe_eyescandataerror ),
.PIPE_RXSTATUS ( pipe_rxstatus ),
.PIPE_DMONITOROUT ( pipe_dmonitorout ),
.PIPE_CPLL_LOCK ( pipe_cpll_lock ),
.PIPE_QPLL_LOCK ( pipe_qpll_lock ),
.PIPE_RXPMARESETDONE ( pipe_rxpmaresetdone ),
.PIPE_RXBUFSTATUS ( pipe_rxbufstatus ),
.PIPE_TXPHALIGNDONE ( pipe_txphaligndone ),
.PIPE_TXPHINITDONE ( pipe_txphinitdone ),
.PIPE_TXDLYSRESETDONE ( pipe_txdlysresetdone ),
.PIPE_RXPHALIGNDONE ( pipe_rxphaligndone ),
.PIPE_RXDLYSRESETDONE ( pipe_rxdlysresetdone ),
.PIPE_RXSYNCDONE ( pipe_rxsyncdone ),
.PIPE_RXDISPERR ( pipe_rxdisperr ),
.PIPE_RXNOTINTABLE ( pipe_rxnotintable ),
.PIPE_RXCOMMADET ( pipe_rxcommadet ),
//---------- JTAG Ports --------------------------------
.PIPE_JTAG_RDY (gt_ch_drp_rdy),
//---------- Debug Ports -------------------------------
.PIPE_DEBUG_0 (pipe_debug_0 ),
.PIPE_DEBUG_1 (pipe_debug_1 ),
.PIPE_DEBUG_2 (pipe_debug_2 ),
.PIPE_DEBUG_3 (pipe_debug_3 ),
.PIPE_DEBUG_4 (pipe_debug_4 ),
.PIPE_DEBUG_5 (pipe_debug_5 ),
.PIPE_DEBUG_6 (pipe_debug_6 ),
.PIPE_DEBUG_7 (pipe_debug_7 ),
.PIPE_DEBUG_8 (pipe_debug_8 ),
.PIPE_DEBUG_9 (pipe_debug_9 ),
.PIPE_DEBUG (pipe_debug),
.CPLLPD (cpllpd),
.TXPD (txpd),
.RXPD (rxpd),
.TXPDELECIDLEMODE (txpdelecidlemode),
.TXDETECTRX (txdetectrx),
.TXELECIDLE (txelecidle),
.QPLLPD (qpllpd),
.POWERDOWN (powerdown)
);
assign pipe_gen3_out = 1'b0;
assign common_commands_out = 17'b0;
assign pipe_tx_0_sigs = 70'b0;
assign pipe_tx_1_sigs = 70'b0;
assign pipe_tx_2_sigs = 70'b0;
assign pipe_tx_3_sigs = 70'b0;
assign pipe_tx_4_sigs = 70'b0;
assign pipe_tx_5_sigs = 70'b0;
assign pipe_tx_6_sigs = 70'b0;
assign pipe_tx_7_sigs = 70'b0;
// Assign as passthrough if not tandem configuration
// Input assigned passthroughs
assign icap_o = 32'h0000_0000;
assign cfg_mgmt_write_wire = cfg_mgmt_write;
assign cfg_mgmt_read_wire = cfg_mgmt_read;
assign cfg_per_func_status_control_wire = cfg_per_func_status_control;
assign cfg_per_function_output_request_wire = cfg_per_function_output_request;
assign cfg_dsn_wire = cfg_dsn;
assign cfg_power_state_change_ack_wire = cfg_power_state_change_ack;
assign cfg_err_cor_in_wire = cfg_err_cor_in;
assign cfg_err_uncor_in_wire = cfg_err_uncor_in;
assign cfg_flr_done_wire = cfg_flr_done;
assign cfg_vf_flr_done_wire = cfg_vf_flr_done;
assign cfg_link_training_enable_wire = cfg_link_training_enable;
assign cfg_ext_read_data_valid_wire = cfg_ext_read_data_valid;
assign cfg_interrupt_pending_wire = cfg_interrupt_pending;
assign cfg_interrupt_msi_select_wire = cfg_interrupt_msi_select;
assign cfg_interrupt_msi_pending_status_wire = cfg_interrupt_msi_pending_status;
assign cfg_config_space_enable_wire = cfg_config_space_enable;
assign cfg_req_pm_transition_l23_ready_wire = cfg_req_pm_transition_l23_ready;
assign cfg_hot_reset_in_wire = cfg_hot_reset_in;
assign cfg_ds_port_number_wire = cfg_ds_port_number;
assign cfg_ds_bus_number_wire = cfg_ds_bus_number;
assign cfg_ds_device_number_wire = cfg_ds_device_number;
assign cfg_ds_function_number_wire = cfg_ds_function_number;
assign user_tph_stt_address_wire = user_tph_stt_address;
assign user_tph_function_num_wire = user_tph_function_num;
assign user_tph_stt_read_enable_wire = user_tph_stt_read_enable;
// Output assigned passthroughs
assign cfg_phy_link_down = cfg_phy_link_down_wire;
assign cfg_phy_link_status = cfg_phy_link_status_wire;
assign cfg_ltssm_state = cfg_ltssm_state_wire;
assign cfg_hot_reset_out = cfg_hot_reset_out_wire;
assign pcie_drp_rdy = drp_rdy_wire;
assign pcie_drp_do = drp_do_wire;
// Input assigned passthroughs
assign drp_clk_wire = pcie_drp_clk;
assign drp_en_wire = pcie_drp_en;
assign drp_we_wire = pcie_drp_we;
assign drp_addr_wire = pcie_drp_addr;
assign drp_di_wire = pcie_drp_di;
// Passthrough for tandem_cplr outputs
assign s_axis_cc_tdata_wire = s_axis_cc_tdata;
assign s_axis_cc_tkeep_wire = s_axis_cc_tkeep;
assign s_axis_cc_tlast_wire = s_axis_cc_tlast;
assign s_axis_cc_tvalid_wire = s_axis_cc_tvalid;
assign s_axis_cc_tuser_wire = s_axis_cc_tuser;
assign s_axis_cc_tready = s_axis_cc_tready_wire;
assign m_axis_cq_tdata = m_axis_cq_tdata_wire;
assign m_axis_cq_tlast = m_axis_cq_tlast_wire;
assign m_axis_cq_tvalid = m_axis_cq_tvalid_wire;
assign m_axis_cq_tuser = m_axis_cq_tuser_wire;
assign m_axis_cq_tkeep = m_axis_cq_tkeep_wire;
assign m_axis_cq_tready_wire = {22{m_axis_cq_tready}};
assign s_axis_rq_tdata_wire = s_axis_rq_tdata;
assign s_axis_rq_tkeep_wire = s_axis_rq_tkeep;
assign s_axis_rq_tlast_wire = s_axis_rq_tlast;
assign s_axis_rq_tvalid_wire = s_axis_rq_tvalid;
assign s_axis_rq_tuser_wire = s_axis_rq_tuser;
assign s_axis_rq_tready = s_axis_rq_tready_wire;
assign m_axis_rc_tdata = m_axis_rc_tdata_wire;
assign m_axis_rc_tlast = m_axis_rc_tlast_wire;
assign m_axis_rc_tvalid = m_axis_rc_tvalid_wire;
assign m_axis_rc_tuser = m_axis_rc_tuser_wire;
assign m_axis_rc_tkeep = m_axis_rc_tkeep_wire;
assign m_axis_rc_tready_wire = {22{m_axis_rc_tready}};
assign cfg_msg_transmit_done = cfg_msg_transmit_done_wire;
assign cfg_msg_transmit_wire = cfg_msg_transmit;
assign cfg_msg_transmit_type_wire = cfg_msg_transmit_type;
assign cfg_msg_transmit_data_wire = cfg_msg_transmit_data;
assign pcie_rq_tag = pcie_rq_tag_wire;
assign pcie_rq_tag_vld = pcie_rq_tag_vld_wire;
assign pcie_tfc_nph_av = pcie_tfc_nph_av_wire;
assign pcie_tfc_npd_av = pcie_tfc_npd_av_wire;
assign pcie_rq_seq_num = pcie_rq_seq_num_wire;
assign pcie_rq_seq_num_vld = pcie_rq_seq_num_vld_wire;
assign cfg_fc_ph = cfg_fc_ph_wire;
assign cfg_fc_nph = cfg_fc_nph_wire;
assign cfg_fc_cplh = cfg_fc_cplh_wire;
assign cfg_fc_pd = cfg_fc_pd_wire;
assign cfg_fc_npd = cfg_fc_npd_wire;
assign cfg_fc_cpld = cfg_fc_cpld_wire;
assign cfg_fc_sel_wire = cfg_fc_sel;
assign pcie_cq_np_req_count = pcie_cq_np_req_count_wire;
assign pcie_cq_np_req_wire = pcie_cq_np_req;
assign cfg_msg_received = cfg_msg_received_wire;
assign cfg_msg_received_type = cfg_msg_received_type_wire;
assign cfg_msg_received_data = cfg_msg_received_data_wire;
assign cfg_interrupt_int_wire = cfg_interrupt_int;
assign cfg_interrupt_msi_int_wire = cfg_interrupt_msi_int;
assign cfg_interrupt_msix_int_wire = cfg_interrupt_msix_int;
assign user_app_rdy = 1'b1;
assign startup_cfgclk = 1'b0;
assign startup_cfgmclk = 1'b0;
assign startup_eos = 1'b0;
assign startup_preq = 1'b0;
// Generate user_lnk_up
assign user_lnk_up = user_lnk_up_int;
//----------------------------------------------------------------------------------------------------------------//
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:46:10 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch2v1_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, ack_add_subt, add_subt_dataA,
add_subt_dataB, result_add_subt, op_add_subt, ready_add_subt );
input [63:0] data_in;
input [1:0] shift_region_flag;
output [63:0] data_output;
output [63:0] add_subt_dataA;
output [63:0] add_subt_dataB;
input [63:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, ack_add_subt, op_add_subt;
wire d_ff1_operation_out, sel_mux_1_reg, d_ff3_sign_out, sel_mux_3_reg,
data_output2_63_, cordic_FSM_state_next_1_, n564, n569, n570, n571,
n572, n573, n574, n575, n576, n577, n578, n579, n580, n581, n582,
n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, n593,
n594, n595, n596, n597, n598, n599, n600, n601, n602, n603, n604,
n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615,
n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626,
n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637,
n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648,
n649, n650, n651, n652, n653, n654, n655, n656, n657, n658, n659,
n660, n661, n662, n663, n664, n665, n666, n667, n668, n669, n670,
n671, n672, n673, n674, n675, n676, n677, n678, n679, n680, n681,
n682, n683, n684, n685, n686, n687, n688, n689, n690, n691, n692,
n693, n694, n695, n696, n697, n698, n699, n700, n701, n702, n703,
n704, n705, n706, n707, n708, n709, n710, n711, n712, n713, n714,
n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, n725,
n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736,
n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747,
n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758,
n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769,
n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780,
n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791,
n792, n793, n794, n795, n796, n797, n798, n799, n800, n801, n802,
n803, n804, n805, n806, n807, n808, n809, n810, n811, n812, n813,
n814, n815, n816, n817, n818, n819, n820, n821, n822, n823, n824,
n825, n826, n827, n828, n829, n830, n831, n832, n833, n834, n835,
n836, n837, n838, n839, n840, n841, n842, n843, n844, n845, n846,
n847, n848, n849, n850, n851, n852, n853, n854, n855, n856, n857,
n858, n859, n860, n861, n862, n863, n864, n865, n866, n867, n868,
n869, n870, n871, n872, n873, n874, n875, n876, n877, n878, n879,
n880, n881, n882, n883, n884, n885, n886, n887, n888, n889, n890,
n891, n892, n893, n894, n895, n896, n897, n898, n899, n900, n901,
n902, n903, n904, n905, n906, n907, n908, n909, n910, n911, n912,
n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, n923,
n924, n925, n926, n927, n928, n929, n930, n931, n932, n933, n934,
n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, n945,
n946, n947, n948, n949, n950, n951, n952, n953, n954, n955, n956,
n957, n958, n959, n960, n961, n962, n963, n964, n965, n966, n967,
n968, n969, n970, n971, n972, n973, n974, n975, n976, n977, n978,
n979, n980, n981, n982, n983, n984, n985, n986, n987, n988, n989,
n990, n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000,
n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010,
n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020,
n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030,
n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040,
n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050,
n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060,
n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070,
n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080,
n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090,
n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100,
n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110,
n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120,
n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130,
n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140,
n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150,
n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160,
n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170,
n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180,
n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190,
n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230,
n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240,
n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250,
n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260,
n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270,
n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280,
n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290,
n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300,
n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310,
n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1475, n1476, n1477, n1478, n1479,
n1480, n1481, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490,
n1491, n1492, n1493, n1494, n1495, n1496, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611,
n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621,
n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631,
n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641,
n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651,
n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661,
n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671,
n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681,
n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691,
n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701,
n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711,
n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721,
n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731,
n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741,
n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751,
n1752, n1753, n1754, n1755, n1756, n1757, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822,
n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832,
n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852,
n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1880, n1881, n1882, n1883,
n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893,
n1894, n1895, n1896, n1898, n1899, n1900, n1901, n1902, n1903, n1904,
n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915,
n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925,
n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935,
n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946,
n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956,
n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966,
n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976,
n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1987,
n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997,
n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007,
n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017,
n2018, n2019, n2020, n2021, n2022, n2023, n2025, n2026, n2027, n2028,
n2029, n2030, n2031, n2032, n2034, n2035, n2036, n2037, n2038, n2039,
n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049,
n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059,
n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069,
n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079,
n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089,
n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099,
n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109,
n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119,
n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129,
n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139,
n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149,
n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159,
n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169,
n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179,
n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189,
n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199,
n2200, n2201, n2202, n2203, n2204;
wire [1:0] d_ff1_shift_region_flag_out;
wire [1:0] cont_var_out;
wire [3:1] cont_iter_out;
wire [63:0] d_ff1_Z;
wire [63:0] d_ff_Xn;
wire [63:0] d_ff_Yn;
wire [63:0] d_ff_Zn;
wire [63:0] d_ff2_X;
wire [63:0] d_ff2_Y;
wire [63:0] d_ff2_Z;
wire [63:0] d_ff3_sh_x_out;
wire [63:0] d_ff3_sh_y_out;
wire [56:0] d_ff3_LUT_out;
wire [1:0] sel_mux_2_reg;
wire [62:0] sign_inv_out;
wire [3:0] cordic_FSM_state_reg;
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n1333), .CK(clk), .RN(n2134), .Q(d_ff1_Z[0])
);
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n1332), .CK(clk), .RN(n2162), .Q(d_ff1_Z[1])
);
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n1331), .CK(clk), .RN(n2133), .Q(d_ff1_Z[2])
);
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n1330), .CK(clk), .RN(n2168), .Q(d_ff1_Z[3])
);
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n1329), .CK(clk), .RN(n2145), .Q(d_ff1_Z[4])
);
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n1328), .CK(clk), .RN(n2147), .Q(d_ff1_Z[5])
);
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n1327), .CK(clk), .RN(n2131), .Q(d_ff1_Z[6])
);
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n1326), .CK(clk), .RN(n2169), .Q(d_ff1_Z[7])
);
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n1325), .CK(clk), .RN(n2166), .Q(d_ff1_Z[8])
);
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n1324), .CK(clk), .RN(n2166), .Q(d_ff1_Z[9])
);
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n1323), .CK(clk), .RN(n2166), .Q(d_ff1_Z[10])
);
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n1322), .CK(clk), .RN(n2166), .Q(d_ff1_Z[11])
);
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n1321), .CK(clk), .RN(n2166), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n1320), .CK(clk), .RN(n2166), .Q(d_ff1_Z[13])
);
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n1319), .CK(clk), .RN(n2166), .Q(d_ff1_Z[14])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n1318), .CK(clk), .RN(n2166), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n1317), .CK(clk), .RN(n2166), .Q(d_ff1_Z[16])
);
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n1316), .CK(clk), .RN(n2166), .Q(d_ff1_Z[17])
);
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n1315), .CK(clk), .RN(n2166), .Q(d_ff1_Z[18])
);
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n1314), .CK(clk), .RN(n2166), .Q(d_ff1_Z[19])
);
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n1313), .CK(clk), .RN(n2165), .Q(d_ff1_Z[20])
);
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n1312), .CK(clk), .RN(n2165), .Q(d_ff1_Z[21])
);
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n1311), .CK(clk), .RN(n2165), .Q(d_ff1_Z[22])
);
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n1310), .CK(clk), .RN(n2165), .Q(d_ff1_Z[23])
);
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n1309), .CK(clk), .RN(n2165), .Q(d_ff1_Z[24])
);
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n1308), .CK(clk), .RN(n2165), .Q(d_ff1_Z[25])
);
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n1307), .CK(clk), .RN(n2165), .Q(d_ff1_Z[26])
);
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n1306), .CK(clk), .RN(n2165), .Q(d_ff1_Z[27])
);
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n1305), .CK(clk), .RN(n2165), .Q(d_ff1_Z[28])
);
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n1304), .CK(clk), .RN(n2165), .Q(d_ff1_Z[29])
);
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n1303), .CK(clk), .RN(n2165), .Q(d_ff1_Z[30])
);
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n1302), .CK(clk), .RN(n2165), .Q(d_ff1_Z[31])
);
DFFRXLTS reg_Z0_Q_reg_32_ ( .D(n1301), .CK(clk), .RN(n2164), .Q(d_ff1_Z[32])
);
DFFRXLTS reg_Z0_Q_reg_33_ ( .D(n1300), .CK(clk), .RN(n2164), .Q(d_ff1_Z[33])
);
DFFRXLTS reg_Z0_Q_reg_34_ ( .D(n1299), .CK(clk), .RN(n2164), .Q(d_ff1_Z[34])
);
DFFRXLTS reg_Z0_Q_reg_35_ ( .D(n1298), .CK(clk), .RN(n2164), .Q(d_ff1_Z[35])
);
DFFRXLTS reg_Z0_Q_reg_36_ ( .D(n1297), .CK(clk), .RN(n2164), .Q(d_ff1_Z[36])
);
DFFRXLTS reg_Z0_Q_reg_37_ ( .D(n1296), .CK(clk), .RN(n2164), .Q(d_ff1_Z[37])
);
DFFRXLTS reg_Z0_Q_reg_38_ ( .D(n1295), .CK(clk), .RN(n2164), .Q(d_ff1_Z[38])
);
DFFRXLTS reg_Z0_Q_reg_39_ ( .D(n1294), .CK(clk), .RN(n2164), .Q(d_ff1_Z[39])
);
DFFRXLTS reg_Z0_Q_reg_40_ ( .D(n1293), .CK(clk), .RN(n2164), .Q(d_ff1_Z[40])
);
DFFRXLTS reg_Z0_Q_reg_41_ ( .D(n1292), .CK(clk), .RN(n2164), .Q(d_ff1_Z[41])
);
DFFRXLTS reg_Z0_Q_reg_42_ ( .D(n1291), .CK(clk), .RN(n2164), .Q(d_ff1_Z[42])
);
DFFRXLTS reg_Z0_Q_reg_43_ ( .D(n1290), .CK(clk), .RN(n2164), .Q(d_ff1_Z[43])
);
DFFRXLTS reg_Z0_Q_reg_44_ ( .D(n1289), .CK(clk), .RN(n2163), .Q(d_ff1_Z[44])
);
DFFRXLTS reg_Z0_Q_reg_45_ ( .D(n1288), .CK(clk), .RN(n2163), .Q(d_ff1_Z[45])
);
DFFRXLTS reg_Z0_Q_reg_46_ ( .D(n1287), .CK(clk), .RN(n2163), .Q(d_ff1_Z[46])
);
DFFRXLTS reg_Z0_Q_reg_47_ ( .D(n1286), .CK(clk), .RN(n2163), .Q(d_ff1_Z[47])
);
DFFRXLTS reg_Z0_Q_reg_48_ ( .D(n1285), .CK(clk), .RN(n2163), .Q(d_ff1_Z[48])
);
DFFRXLTS reg_Z0_Q_reg_49_ ( .D(n1284), .CK(clk), .RN(n2163), .Q(d_ff1_Z[49])
);
DFFRXLTS reg_Z0_Q_reg_50_ ( .D(n1283), .CK(clk), .RN(n2163), .Q(d_ff1_Z[50])
);
DFFRXLTS reg_Z0_Q_reg_51_ ( .D(n1282), .CK(clk), .RN(n2163), .Q(d_ff1_Z[51])
);
DFFRXLTS reg_Z0_Q_reg_52_ ( .D(n1281), .CK(clk), .RN(n2163), .Q(d_ff1_Z[52])
);
DFFRXLTS reg_Z0_Q_reg_53_ ( .D(n1280), .CK(clk), .RN(n2163), .Q(d_ff1_Z[53])
);
DFFRXLTS reg_Z0_Q_reg_54_ ( .D(n1279), .CK(clk), .RN(n2163), .Q(d_ff1_Z[54])
);
DFFRXLTS reg_Z0_Q_reg_55_ ( .D(n1278), .CK(clk), .RN(n2163), .Q(d_ff1_Z[55])
);
DFFRXLTS reg_Z0_Q_reg_56_ ( .D(n1277), .CK(clk), .RN(n2162), .Q(d_ff1_Z[56])
);
DFFRXLTS reg_Z0_Q_reg_57_ ( .D(n1276), .CK(clk), .RN(n2162), .Q(d_ff1_Z[57])
);
DFFRXLTS reg_Z0_Q_reg_58_ ( .D(n1275), .CK(clk), .RN(n2162), .Q(d_ff1_Z[58])
);
DFFRXLTS reg_Z0_Q_reg_59_ ( .D(n1274), .CK(clk), .RN(n2162), .Q(d_ff1_Z[59])
);
DFFRXLTS reg_Z0_Q_reg_60_ ( .D(n1273), .CK(clk), .RN(n2162), .Q(d_ff1_Z[60])
);
DFFRXLTS reg_Z0_Q_reg_61_ ( .D(n1272), .CK(clk), .RN(n2162), .Q(d_ff1_Z[61])
);
DFFRXLTS reg_Z0_Q_reg_62_ ( .D(n1271), .CK(clk), .RN(n2162), .Q(d_ff1_Z[62])
);
DFFRXLTS reg_Z0_Q_reg_63_ ( .D(n1270), .CK(clk), .RN(n2162), .Q(d_ff1_Z[63])
);
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n1265), .CK(clk), .RN(n2161), .Q(d_ff_Zn[0])
);
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n1264), .CK(clk), .RN(n2161), .Q(d_ff_Zn[1])
);
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n1263), .CK(clk), .RN(n2161), .Q(d_ff_Zn[2])
);
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n1262), .CK(clk), .RN(n2161), .Q(d_ff_Zn[3])
);
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n1261), .CK(clk), .RN(n2161), .Q(d_ff_Zn[4])
);
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n1260), .CK(clk), .RN(n2161), .Q(d_ff_Zn[5])
);
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n1259), .CK(clk), .RN(n2161), .Q(d_ff_Zn[6])
);
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n1258), .CK(clk), .RN(n2161), .Q(d_ff_Zn[7])
);
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n1257), .CK(clk), .RN(n2161), .Q(d_ff_Zn[8])
);
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n1256), .CK(clk), .RN(n2161), .Q(d_ff_Zn[9])
);
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n1255), .CK(clk), .RN(n2161), .Q(
d_ff_Zn[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n1254), .CK(clk), .RN(n2161), .Q(
d_ff_Zn[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n1253), .CK(clk), .RN(n2160), .Q(
d_ff_Zn[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n1252), .CK(clk), .RN(n2160), .Q(
d_ff_Zn[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n1251), .CK(clk), .RN(n2160), .Q(
d_ff_Zn[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n1250), .CK(clk), .RN(n2160), .Q(
d_ff_Zn[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n2149), .Q(
d_ff_Zn[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n1248), .CK(clk), .RN(n2160), .Q(
d_ff_Zn[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n1247), .CK(clk), .RN(n2160), .Q(
d_ff_Zn[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n1246), .CK(clk), .RN(n2160), .Q(
d_ff_Zn[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n1245), .CK(clk), .RN(n2160), .Q(
d_ff_Zn[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n1244), .CK(clk), .RN(n2160), .Q(
d_ff_Zn[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n1243), .CK(clk), .RN(n2160), .Q(
d_ff_Zn[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n1242), .CK(clk), .RN(n2160), .Q(
d_ff_Zn[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n1241), .CK(clk), .RN(n2159), .Q(
d_ff_Zn[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n1240), .CK(clk), .RN(n2159), .Q(
d_ff_Zn[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n1239), .CK(clk), .RN(n2159), .Q(
d_ff_Zn[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n1238), .CK(clk), .RN(n2159), .Q(
d_ff_Zn[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n1237), .CK(clk), .RN(n2159), .Q(
d_ff_Zn[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n1236), .CK(clk), .RN(n2159), .Q(
d_ff_Zn[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n1235), .CK(clk), .RN(n2159), .Q(
d_ff_Zn[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n1234), .CK(clk), .RN(n2159), .Q(
d_ff_Zn[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_32_ ( .D(n1233), .CK(clk), .RN(n2159), .Q(
d_ff_Zn[32]) );
DFFRXLTS d_ff4_Zn_Q_reg_33_ ( .D(n1232), .CK(clk), .RN(n2159), .Q(
d_ff_Zn[33]) );
DFFRXLTS d_ff4_Zn_Q_reg_34_ ( .D(n1231), .CK(clk), .RN(n2159), .Q(
d_ff_Zn[34]) );
DFFRXLTS d_ff4_Zn_Q_reg_35_ ( .D(n1230), .CK(clk), .RN(n2159), .Q(
d_ff_Zn[35]) );
DFFRXLTS d_ff4_Zn_Q_reg_36_ ( .D(n1229), .CK(clk), .RN(n2158), .Q(
d_ff_Zn[36]) );
DFFRXLTS d_ff4_Zn_Q_reg_37_ ( .D(n1228), .CK(clk), .RN(n2158), .Q(
d_ff_Zn[37]) );
DFFRXLTS d_ff4_Zn_Q_reg_38_ ( .D(n1227), .CK(clk), .RN(n2158), .Q(
d_ff_Zn[38]) );
DFFRXLTS d_ff4_Zn_Q_reg_39_ ( .D(n1226), .CK(clk), .RN(n2158), .Q(
d_ff_Zn[39]) );
DFFRXLTS d_ff4_Zn_Q_reg_40_ ( .D(n1225), .CK(clk), .RN(n2158), .Q(
d_ff_Zn[40]) );
DFFRXLTS d_ff4_Zn_Q_reg_41_ ( .D(n1224), .CK(clk), .RN(n2158), .Q(
d_ff_Zn[41]) );
DFFRXLTS d_ff4_Zn_Q_reg_42_ ( .D(n1223), .CK(clk), .RN(n2158), .Q(
d_ff_Zn[42]) );
DFFRXLTS d_ff4_Zn_Q_reg_43_ ( .D(n1222), .CK(clk), .RN(n2158), .Q(
d_ff_Zn[43]) );
DFFRXLTS d_ff4_Zn_Q_reg_44_ ( .D(n1221), .CK(clk), .RN(n2158), .Q(
d_ff_Zn[44]) );
DFFRXLTS d_ff4_Zn_Q_reg_45_ ( .D(n1220), .CK(clk), .RN(n2158), .Q(
d_ff_Zn[45]) );
DFFRXLTS d_ff4_Zn_Q_reg_46_ ( .D(n1219), .CK(clk), .RN(n2158), .Q(
d_ff_Zn[46]) );
DFFRXLTS d_ff4_Zn_Q_reg_47_ ( .D(n1218), .CK(clk), .RN(n2158), .Q(
d_ff_Zn[47]) );
DFFRXLTS d_ff4_Zn_Q_reg_48_ ( .D(n1217), .CK(clk), .RN(n2157), .Q(
d_ff_Zn[48]) );
DFFRXLTS d_ff4_Zn_Q_reg_49_ ( .D(n1216), .CK(clk), .RN(n2157), .Q(
d_ff_Zn[49]) );
DFFRXLTS d_ff4_Zn_Q_reg_50_ ( .D(n1215), .CK(clk), .RN(n2157), .Q(
d_ff_Zn[50]) );
DFFRXLTS d_ff4_Zn_Q_reg_51_ ( .D(n1214), .CK(clk), .RN(n2157), .Q(
d_ff_Zn[51]) );
DFFRXLTS d_ff4_Zn_Q_reg_52_ ( .D(n1213), .CK(clk), .RN(n2157), .Q(
d_ff_Zn[52]) );
DFFRXLTS d_ff4_Zn_Q_reg_53_ ( .D(n1212), .CK(clk), .RN(n2157), .Q(
d_ff_Zn[53]) );
DFFRXLTS d_ff4_Zn_Q_reg_54_ ( .D(n1211), .CK(clk), .RN(n2157), .Q(
d_ff_Zn[54]) );
DFFRXLTS d_ff4_Zn_Q_reg_55_ ( .D(n1210), .CK(clk), .RN(n2157), .Q(
d_ff_Zn[55]) );
DFFRXLTS d_ff4_Zn_Q_reg_56_ ( .D(n1209), .CK(clk), .RN(n2157), .Q(
d_ff_Zn[56]) );
DFFRXLTS d_ff4_Zn_Q_reg_57_ ( .D(n1208), .CK(clk), .RN(n2157), .Q(
d_ff_Zn[57]) );
DFFRXLTS d_ff4_Zn_Q_reg_58_ ( .D(n1207), .CK(clk), .RN(n2157), .Q(
d_ff_Zn[58]) );
DFFRXLTS d_ff4_Zn_Q_reg_59_ ( .D(n1206), .CK(clk), .RN(n2157), .Q(
d_ff_Zn[59]) );
DFFRXLTS d_ff4_Zn_Q_reg_60_ ( .D(n1205), .CK(clk), .RN(n2157), .Q(
d_ff_Zn[60]) );
DFFRXLTS d_ff4_Zn_Q_reg_61_ ( .D(n1204), .CK(clk), .RN(n2156), .Q(
d_ff_Zn[61]) );
DFFRXLTS d_ff4_Zn_Q_reg_62_ ( .D(n1203), .CK(clk), .RN(n2157), .Q(
d_ff_Zn[62]) );
DFFRXLTS d_ff4_Zn_Q_reg_63_ ( .D(n1202), .CK(clk), .RN(n2156), .Q(
d_ff_Zn[63]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(n1201), .CK(clk), .RN(n2157), .Q(d_ff_Yn[0]),
.QN(n2074) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(n1200), .CK(clk), .RN(n2156), .Q(d_ff_Yn[1]),
.QN(n2075) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(n1199), .CK(clk), .RN(n2157), .Q(d_ff_Yn[2]),
.QN(n2076) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(n1198), .CK(clk), .RN(n2156), .Q(d_ff_Yn[3]),
.QN(n2077) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(n1197), .CK(clk), .RN(n2157), .Q(d_ff_Yn[4]),
.QN(n2078) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(n1196), .CK(clk), .RN(n2156), .Q(d_ff_Yn[5]),
.QN(n2079) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(n1195), .CK(clk), .RN(n2157), .Q(d_ff_Yn[6]),
.QN(n2080) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(n1194), .CK(clk), .RN(n2156), .Q(d_ff_Yn[7]),
.QN(n2081) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(n1193), .CK(clk), .RN(n2156), .Q(d_ff_Yn[8]),
.QN(n2082) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(n1192), .CK(clk), .RN(n2156), .Q(d_ff_Yn[9]),
.QN(n2083) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(n1191), .CK(clk), .RN(n2156), .Q(
d_ff_Yn[10]), .QN(n2084) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(n1190), .CK(clk), .RN(n2156), .Q(
d_ff_Yn[11]), .QN(n2085) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(n1189), .CK(clk), .RN(n2156), .Q(
d_ff_Yn[12]), .QN(n2086) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(n1188), .CK(clk), .RN(n2156), .Q(
d_ff_Yn[13]), .QN(n2087) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(n1187), .CK(clk), .RN(n2156), .Q(
d_ff_Yn[14]), .QN(n2088) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(n1186), .CK(clk), .RN(n2156), .Q(
d_ff_Yn[15]), .QN(n2089) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(n1185), .CK(clk), .RN(n2156), .Q(
d_ff_Yn[16]), .QN(n2090) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(n1184), .CK(clk), .RN(n2156), .Q(
d_ff_Yn[17]), .QN(n2091) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(n1183), .CK(clk), .RN(n2156), .Q(
d_ff_Yn[18]), .QN(n2092) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(n1182), .CK(clk), .RN(n2156), .Q(
d_ff_Yn[19]), .QN(n2093) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(n1181), .CK(clk), .RN(n2155), .Q(
d_ff_Yn[20]), .QN(n2094) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(n1180), .CK(clk), .RN(n2155), .Q(
d_ff_Yn[21]), .QN(n2095) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(n1179), .CK(clk), .RN(n2155), .Q(
d_ff_Yn[22]), .QN(n2096) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(n1178), .CK(clk), .RN(n2155), .Q(
d_ff_Yn[23]), .QN(n2097) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(n1177), .CK(clk), .RN(n2155), .Q(
d_ff_Yn[24]), .QN(n2098) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(n1176), .CK(clk), .RN(n2155), .Q(
d_ff_Yn[25]), .QN(n2099) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(n1175), .CK(clk), .RN(n2155), .Q(
d_ff_Yn[26]), .QN(n2100) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(n1174), .CK(clk), .RN(n2155), .Q(
d_ff_Yn[27]), .QN(n2101) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(n1173), .CK(clk), .RN(n2155), .Q(
d_ff_Yn[28]), .QN(n2102) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(n1172), .CK(clk), .RN(n2155), .Q(
d_ff_Yn[29]), .QN(n2103) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(n1171), .CK(clk), .RN(n2155), .Q(
d_ff_Yn[30]), .QN(n2104) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(n1170), .CK(clk), .RN(n2155), .Q(
d_ff_Yn[31]), .QN(n2105) );
DFFRXLTS d_ff4_Yn_Q_reg_32_ ( .D(n1169), .CK(clk), .RN(n2154), .Q(
d_ff_Yn[32]), .QN(n2106) );
DFFRXLTS d_ff4_Yn_Q_reg_33_ ( .D(n1168), .CK(clk), .RN(n2154), .Q(
d_ff_Yn[33]), .QN(n2107) );
DFFRXLTS d_ff4_Yn_Q_reg_34_ ( .D(n1167), .CK(clk), .RN(n2154), .Q(
d_ff_Yn[34]), .QN(n2108) );
DFFRXLTS d_ff4_Yn_Q_reg_35_ ( .D(n1166), .CK(clk), .RN(n2154), .Q(
d_ff_Yn[35]), .QN(n2109) );
DFFRXLTS d_ff4_Yn_Q_reg_36_ ( .D(n1165), .CK(clk), .RN(n2154), .Q(
d_ff_Yn[36]), .QN(n2110) );
DFFRXLTS d_ff4_Yn_Q_reg_37_ ( .D(n1164), .CK(clk), .RN(n2154), .Q(
d_ff_Yn[37]), .QN(n2111) );
DFFRXLTS d_ff4_Yn_Q_reg_38_ ( .D(n1163), .CK(clk), .RN(n2154), .Q(
d_ff_Yn[38]), .QN(n2112) );
DFFRXLTS d_ff4_Yn_Q_reg_39_ ( .D(n1162), .CK(clk), .RN(n2154), .Q(
d_ff_Yn[39]), .QN(n2113) );
DFFRXLTS d_ff4_Yn_Q_reg_40_ ( .D(n1161), .CK(clk), .RN(n2154), .Q(
d_ff_Yn[40]), .QN(n2114) );
DFFRXLTS d_ff4_Yn_Q_reg_41_ ( .D(n1160), .CK(clk), .RN(n2154), .Q(
d_ff_Yn[41]), .QN(n2115) );
DFFRXLTS d_ff4_Yn_Q_reg_42_ ( .D(n1159), .CK(clk), .RN(n2154), .Q(
d_ff_Yn[42]), .QN(n2116) );
DFFRXLTS d_ff4_Yn_Q_reg_43_ ( .D(n1158), .CK(clk), .RN(n2154), .Q(
d_ff_Yn[43]), .QN(n2117) );
DFFRXLTS d_ff4_Yn_Q_reg_44_ ( .D(n1157), .CK(clk), .RN(n2153), .Q(
d_ff_Yn[44]), .QN(n2118) );
DFFRXLTS d_ff4_Yn_Q_reg_45_ ( .D(n1156), .CK(clk), .RN(n2153), .Q(
d_ff_Yn[45]), .QN(n2119) );
DFFRXLTS d_ff4_Yn_Q_reg_46_ ( .D(n1155), .CK(clk), .RN(n2153), .Q(
d_ff_Yn[46]), .QN(n2120) );
DFFRXLTS d_ff4_Yn_Q_reg_47_ ( .D(n1154), .CK(clk), .RN(n2153), .Q(
d_ff_Yn[47]), .QN(n2121) );
DFFRXLTS d_ff4_Yn_Q_reg_48_ ( .D(n1153), .CK(clk), .RN(n2153), .Q(
d_ff_Yn[48]), .QN(n2122) );
DFFRXLTS d_ff4_Yn_Q_reg_49_ ( .D(n1152), .CK(clk), .RN(n2153), .Q(
d_ff_Yn[49]), .QN(n2123) );
DFFRXLTS d_ff4_Yn_Q_reg_50_ ( .D(n1151), .CK(clk), .RN(n2153), .Q(
d_ff_Yn[50]), .QN(n2124) );
DFFRXLTS d_ff4_Yn_Q_reg_51_ ( .D(n1150), .CK(clk), .RN(n2160), .Q(
d_ff_Yn[51]), .QN(n2125) );
DFFRXLTS d_ff4_Yn_Q_reg_54_ ( .D(n1147), .CK(clk), .RN(n2173), .Q(
d_ff_Yn[54]), .QN(n2126) );
DFFRXLTS d_ff4_Yn_Q_reg_63_ ( .D(n1138), .CK(clk), .RN(n2174), .Q(
d_ff_Yn[63]), .QN(n2127) );
DFFRXLTS d_ff5_Q_reg_0_ ( .D(n1073), .CK(clk), .RN(n2174), .Q(
sign_inv_out[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n1072), .CK(clk), .RN(n2174), .Q(
data_output[0]) );
DFFRXLTS d_ff5_Q_reg_1_ ( .D(n1071), .CK(clk), .RN(n2174), .Q(
sign_inv_out[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n1070), .CK(clk), .RN(n2174), .Q(
data_output[1]) );
DFFRXLTS d_ff5_Q_reg_2_ ( .D(n1069), .CK(clk), .RN(n2175), .Q(
sign_inv_out[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n1068), .CK(clk), .RN(n2175), .Q(
data_output[2]) );
DFFRXLTS d_ff5_Q_reg_3_ ( .D(n1067), .CK(clk), .RN(n2175), .Q(
sign_inv_out[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n1066), .CK(clk), .RN(n2175), .Q(
data_output[3]) );
DFFRXLTS d_ff5_Q_reg_4_ ( .D(n1065), .CK(clk), .RN(n2175), .Q(
sign_inv_out[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n1064), .CK(clk), .RN(n2175), .Q(
data_output[4]) );
DFFRXLTS d_ff5_Q_reg_5_ ( .D(n1063), .CK(clk), .RN(n2175), .Q(
sign_inv_out[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n1062), .CK(clk), .RN(n2175), .Q(
data_output[5]) );
DFFRXLTS d_ff5_Q_reg_6_ ( .D(n1061), .CK(clk), .RN(n2176), .Q(
sign_inv_out[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n1060), .CK(clk), .RN(n2176), .Q(
data_output[6]) );
DFFRXLTS d_ff5_Q_reg_7_ ( .D(n1059), .CK(clk), .RN(n2176), .Q(
sign_inv_out[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n1058), .CK(clk), .RN(n2176), .Q(
data_output[7]) );
DFFRXLTS d_ff5_Q_reg_8_ ( .D(n1057), .CK(clk), .RN(n2176), .Q(
sign_inv_out[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n1056), .CK(clk), .RN(n2176), .Q(
data_output[8]) );
DFFRXLTS d_ff5_Q_reg_9_ ( .D(n1055), .CK(clk), .RN(n2176), .Q(
sign_inv_out[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n1054), .CK(clk), .RN(n2176), .Q(
data_output[9]) );
DFFRXLTS d_ff5_Q_reg_10_ ( .D(n1053), .CK(clk), .RN(n2177), .Q(
sign_inv_out[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n1052), .CK(clk), .RN(n2177), .Q(
data_output[10]) );
DFFRXLTS d_ff5_Q_reg_11_ ( .D(n1051), .CK(clk), .RN(n2177), .Q(
sign_inv_out[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n1050), .CK(clk), .RN(n2177), .Q(
data_output[11]) );
DFFRXLTS d_ff5_Q_reg_12_ ( .D(n1049), .CK(clk), .RN(n2177), .Q(
sign_inv_out[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n1048), .CK(clk), .RN(n2177), .Q(
data_output[12]) );
DFFRXLTS d_ff5_Q_reg_13_ ( .D(n1047), .CK(clk), .RN(n2177), .Q(
sign_inv_out[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n1046), .CK(clk), .RN(n2177), .Q(
data_output[13]) );
DFFRXLTS d_ff5_Q_reg_14_ ( .D(n1045), .CK(clk), .RN(n2178), .Q(
sign_inv_out[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n1044), .CK(clk), .RN(n2178), .Q(
data_output[14]) );
DFFRXLTS d_ff5_Q_reg_15_ ( .D(n1043), .CK(clk), .RN(n2178), .Q(
sign_inv_out[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n1042), .CK(clk), .RN(n2178), .Q(
data_output[15]) );
DFFRXLTS d_ff5_Q_reg_16_ ( .D(n1041), .CK(clk), .RN(n2178), .Q(
sign_inv_out[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n1040), .CK(clk), .RN(n2178), .Q(
data_output[16]) );
DFFRXLTS d_ff5_Q_reg_17_ ( .D(n1039), .CK(clk), .RN(n2178), .Q(
sign_inv_out[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n1038), .CK(clk), .RN(n2178), .Q(
data_output[17]) );
DFFRXLTS d_ff5_Q_reg_18_ ( .D(n1037), .CK(clk), .RN(n2179), .Q(
sign_inv_out[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n1036), .CK(clk), .RN(n2179), .Q(
data_output[18]) );
DFFRXLTS d_ff5_Q_reg_19_ ( .D(n1035), .CK(clk), .RN(n2179), .Q(
sign_inv_out[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n1034), .CK(clk), .RN(n2179), .Q(
data_output[19]) );
DFFRXLTS d_ff5_Q_reg_20_ ( .D(n1033), .CK(clk), .RN(n2179), .Q(
sign_inv_out[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n1032), .CK(clk), .RN(n2179), .Q(
data_output[20]) );
DFFRXLTS d_ff5_Q_reg_21_ ( .D(n1031), .CK(clk), .RN(n2179), .Q(
sign_inv_out[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n1030), .CK(clk), .RN(n2179), .Q(
data_output[21]) );
DFFRXLTS d_ff5_Q_reg_22_ ( .D(n1029), .CK(clk), .RN(n2180), .Q(
sign_inv_out[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n1028), .CK(clk), .RN(n2180), .Q(
data_output[22]) );
DFFRXLTS d_ff5_Q_reg_23_ ( .D(n1027), .CK(clk), .RN(n2180), .Q(
sign_inv_out[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n1026), .CK(clk), .RN(n2180), .Q(
data_output[23]) );
DFFRXLTS d_ff5_Q_reg_24_ ( .D(n1025), .CK(clk), .RN(n2180), .Q(
sign_inv_out[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n1024), .CK(clk), .RN(n2180), .Q(
data_output[24]) );
DFFRXLTS d_ff5_Q_reg_25_ ( .D(n1023), .CK(clk), .RN(n2180), .Q(
sign_inv_out[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n1022), .CK(clk), .RN(n2180), .Q(
data_output[25]) );
DFFRXLTS d_ff5_Q_reg_26_ ( .D(n1021), .CK(clk), .RN(n2181), .Q(
sign_inv_out[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n1020), .CK(clk), .RN(n2181), .Q(
data_output[26]) );
DFFRXLTS d_ff5_Q_reg_27_ ( .D(n1019), .CK(clk), .RN(n2181), .Q(
sign_inv_out[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n1018), .CK(clk), .RN(n2181), .Q(
data_output[27]) );
DFFRXLTS d_ff5_Q_reg_28_ ( .D(n1017), .CK(clk), .RN(n2173), .Q(
sign_inv_out[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n1016), .CK(clk), .RN(n2173), .Q(
data_output[28]) );
DFFRXLTS d_ff5_Q_reg_29_ ( .D(n1015), .CK(clk), .RN(n2173), .Q(
sign_inv_out[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n1014), .CK(clk), .RN(n2172), .Q(
data_output[29]) );
DFFRXLTS d_ff5_Q_reg_30_ ( .D(n1013), .CK(clk), .RN(n2172), .Q(
sign_inv_out[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n1012), .CK(clk), .RN(n2172), .Q(
data_output[30]) );
DFFRXLTS d_ff5_Q_reg_31_ ( .D(n1011), .CK(clk), .RN(n2172), .Q(
sign_inv_out[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n1010), .CK(clk), .RN(n2172), .Q(
data_output[31]) );
DFFRXLTS d_ff5_Q_reg_32_ ( .D(n1009), .CK(clk), .RN(n2172), .Q(
sign_inv_out[32]) );
DFFRXLTS d_ff5_data_out_Q_reg_32_ ( .D(n1008), .CK(clk), .RN(n2172), .Q(
data_output[32]) );
DFFRXLTS d_ff5_Q_reg_33_ ( .D(n1007), .CK(clk), .RN(n2172), .Q(
sign_inv_out[33]) );
DFFRXLTS d_ff5_data_out_Q_reg_33_ ( .D(n1006), .CK(clk), .RN(n2171), .Q(
data_output[33]) );
DFFRXLTS d_ff5_Q_reg_34_ ( .D(n1005), .CK(clk), .RN(n2171), .Q(
sign_inv_out[34]) );
DFFRXLTS d_ff5_data_out_Q_reg_34_ ( .D(n1004), .CK(clk), .RN(n2171), .Q(
data_output[34]) );
DFFRXLTS d_ff5_Q_reg_35_ ( .D(n1003), .CK(clk), .RN(n2171), .Q(
sign_inv_out[35]) );
DFFRXLTS d_ff5_data_out_Q_reg_35_ ( .D(n1002), .CK(clk), .RN(n2171), .Q(
data_output[35]) );
DFFRXLTS d_ff5_Q_reg_36_ ( .D(n1001), .CK(clk), .RN(n2171), .Q(
sign_inv_out[36]) );
DFFRXLTS d_ff5_data_out_Q_reg_36_ ( .D(n1000), .CK(clk), .RN(n2171), .Q(
data_output[36]) );
DFFRXLTS d_ff5_Q_reg_37_ ( .D(n999), .CK(clk), .RN(n2171), .Q(
sign_inv_out[37]) );
DFFRXLTS d_ff5_data_out_Q_reg_37_ ( .D(n998), .CK(clk), .RN(n2175), .Q(
data_output[37]) );
DFFRXLTS d_ff5_Q_reg_38_ ( .D(n997), .CK(clk), .RN(n2173), .Q(
sign_inv_out[38]) );
DFFRXLTS d_ff5_data_out_Q_reg_38_ ( .D(n996), .CK(clk), .RN(n2171), .Q(
data_output[38]) );
DFFRXLTS d_ff5_Q_reg_39_ ( .D(n995), .CK(clk), .RN(n2177), .Q(
sign_inv_out[39]) );
DFFRXLTS d_ff5_data_out_Q_reg_39_ ( .D(n994), .CK(clk), .RN(n2178), .Q(
data_output[39]) );
DFFRXLTS d_ff5_Q_reg_40_ ( .D(n993), .CK(clk), .RN(n2180), .Q(
sign_inv_out[40]) );
DFFRXLTS d_ff5_data_out_Q_reg_40_ ( .D(n992), .CK(clk), .RN(n2175), .Q(
data_output[40]) );
DFFRXLTS d_ff5_Q_reg_41_ ( .D(n991), .CK(clk), .RN(n2173), .Q(
sign_inv_out[41]) );
DFFRXLTS d_ff5_data_out_Q_reg_41_ ( .D(n990), .CK(clk), .RN(n2170), .Q(
data_output[41]) );
DFFRXLTS d_ff5_Q_reg_42_ ( .D(n989), .CK(clk), .RN(n2170), .Q(
sign_inv_out[42]) );
DFFRXLTS d_ff5_data_out_Q_reg_42_ ( .D(n988), .CK(clk), .RN(n2170), .Q(
data_output[42]) );
DFFRXLTS d_ff5_Q_reg_43_ ( .D(n987), .CK(clk), .RN(n2170), .Q(
sign_inv_out[43]) );
DFFRXLTS d_ff5_data_out_Q_reg_43_ ( .D(n986), .CK(clk), .RN(n2170), .Q(
data_output[43]) );
DFFRXLTS d_ff5_Q_reg_44_ ( .D(n985), .CK(clk), .RN(n2170), .Q(
sign_inv_out[44]) );
DFFRXLTS d_ff5_data_out_Q_reg_44_ ( .D(n984), .CK(clk), .RN(n2170), .Q(
data_output[44]) );
DFFRXLTS d_ff5_Q_reg_45_ ( .D(n983), .CK(clk), .RN(n2170), .Q(
sign_inv_out[45]) );
DFFRXLTS d_ff5_data_out_Q_reg_45_ ( .D(n982), .CK(clk), .RN(n2169), .Q(
data_output[45]) );
DFFRXLTS d_ff5_Q_reg_46_ ( .D(n981), .CK(clk), .RN(n2169), .Q(
sign_inv_out[46]) );
DFFRXLTS d_ff5_data_out_Q_reg_46_ ( .D(n980), .CK(clk), .RN(n2169), .Q(
data_output[46]) );
DFFRXLTS d_ff5_Q_reg_47_ ( .D(n979), .CK(clk), .RN(n2169), .Q(
sign_inv_out[47]) );
DFFRXLTS d_ff5_data_out_Q_reg_47_ ( .D(n978), .CK(clk), .RN(n2169), .Q(
data_output[47]) );
DFFRXLTS d_ff5_Q_reg_48_ ( .D(n977), .CK(clk), .RN(n2169), .Q(
sign_inv_out[48]) );
DFFRXLTS d_ff5_data_out_Q_reg_48_ ( .D(n976), .CK(clk), .RN(n2169), .Q(
data_output[48]) );
DFFRXLTS d_ff5_Q_reg_49_ ( .D(n975), .CK(clk), .RN(n2169), .Q(
sign_inv_out[49]) );
DFFRXLTS d_ff5_data_out_Q_reg_49_ ( .D(n974), .CK(clk), .RN(n2168), .Q(
data_output[49]) );
DFFRXLTS d_ff5_Q_reg_50_ ( .D(n973), .CK(clk), .RN(n2168), .Q(
sign_inv_out[50]) );
DFFRXLTS d_ff5_data_out_Q_reg_50_ ( .D(n972), .CK(clk), .RN(n2168), .Q(
data_output[50]) );
DFFRXLTS d_ff5_Q_reg_51_ ( .D(n971), .CK(clk), .RN(n2168), .Q(
sign_inv_out[51]) );
DFFRXLTS d_ff5_data_out_Q_reg_51_ ( .D(n970), .CK(clk), .RN(n2168), .Q(
data_output[51]) );
DFFRXLTS d_ff5_Q_reg_52_ ( .D(n969), .CK(clk), .RN(n2168), .Q(
sign_inv_out[52]) );
DFFRXLTS d_ff5_data_out_Q_reg_52_ ( .D(n968), .CK(clk), .RN(n2168), .Q(
data_output[52]) );
DFFRXLTS d_ff5_Q_reg_53_ ( .D(n967), .CK(clk), .RN(n2168), .Q(
sign_inv_out[53]) );
DFFRXLTS d_ff5_data_out_Q_reg_53_ ( .D(n966), .CK(clk), .RN(n2167), .Q(
data_output[53]) );
DFFRXLTS d_ff5_Q_reg_54_ ( .D(n965), .CK(clk), .RN(n2167), .Q(
sign_inv_out[54]) );
DFFRXLTS d_ff5_data_out_Q_reg_54_ ( .D(n964), .CK(clk), .RN(n2167), .Q(
data_output[54]) );
DFFRXLTS d_ff5_Q_reg_55_ ( .D(n963), .CK(clk), .RN(n2167), .Q(
sign_inv_out[55]) );
DFFRXLTS d_ff5_data_out_Q_reg_55_ ( .D(n962), .CK(clk), .RN(n2167), .Q(
data_output[55]) );
DFFRXLTS d_ff5_Q_reg_56_ ( .D(n961), .CK(clk), .RN(n2167), .Q(
sign_inv_out[56]) );
DFFRXLTS d_ff5_data_out_Q_reg_56_ ( .D(n960), .CK(clk), .RN(n2167), .Q(
data_output[56]) );
DFFRXLTS d_ff5_Q_reg_57_ ( .D(n959), .CK(clk), .RN(n2167), .Q(
sign_inv_out[57]) );
DFFRXLTS d_ff5_data_out_Q_reg_57_ ( .D(n958), .CK(clk), .RN(n2173), .Q(
data_output[57]) );
DFFRXLTS d_ff5_Q_reg_58_ ( .D(n957), .CK(clk), .RN(n2178), .Q(
sign_inv_out[58]) );
DFFRXLTS d_ff5_data_out_Q_reg_58_ ( .D(n956), .CK(clk), .RN(n2158), .Q(
data_output[58]) );
DFFRXLTS d_ff5_Q_reg_59_ ( .D(n955), .CK(clk), .RN(n2163), .Q(
sign_inv_out[59]) );
DFFRXLTS d_ff5_data_out_Q_reg_59_ ( .D(n954), .CK(clk), .RN(n2173), .Q(
data_output[59]) );
DFFRXLTS d_ff5_Q_reg_60_ ( .D(n953), .CK(clk), .RN(n2138), .Q(
sign_inv_out[60]) );
DFFRXLTS d_ff5_data_out_Q_reg_60_ ( .D(n952), .CK(clk), .RN(n2138), .Q(
data_output[60]) );
DFFRXLTS d_ff5_Q_reg_61_ ( .D(n951), .CK(clk), .RN(n2137), .Q(
sign_inv_out[61]) );
DFFRXLTS d_ff5_data_out_Q_reg_61_ ( .D(n950), .CK(clk), .RN(n2137), .Q(
data_output[61]) );
DFFRXLTS d_ff5_Q_reg_62_ ( .D(n949), .CK(clk), .RN(n2137), .Q(
sign_inv_out[62]) );
DFFRXLTS d_ff5_data_out_Q_reg_62_ ( .D(n948), .CK(clk), .RN(n2137), .Q(
data_output[62]) );
DFFRXLTS d_ff5_Q_reg_63_ ( .D(n947), .CK(clk), .RN(n2137), .Q(
data_output2_63_) );
DFFRXLTS d_ff5_data_out_Q_reg_63_ ( .D(n946), .CK(clk), .RN(n2137), .Q(
data_output[63]) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n945), .CK(clk), .RN(n2137), .Q(
d_ff3_LUT_out[0]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n944), .CK(clk), .RN(n2137), .Q(
d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n943), .CK(clk), .RN(n2137), .Q(
d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(n941), .CK(clk), .RN(n2136), .Q(
d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n940), .CK(clk), .RN(n2136), .Q(
d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n939), .CK(clk), .RN(n2136), .Q(
d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n938), .CK(clk), .RN(n2136), .Q(
d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n937), .CK(clk), .RN(n2136), .QN(n2185) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n935), .CK(clk), .RN(n2136), .Q(
d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_11_ ( .D(n934), .CK(clk), .RN(n2136), .Q(
d_ff3_LUT_out[11]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n933), .CK(clk), .RN(n2136), .Q(
d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n932), .CK(clk), .RN(n2136), .Q(
d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_14_ ( .D(n931), .CK(clk), .RN(n2136), .Q(
d_ff3_LUT_out[14]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n930), .CK(clk), .RN(n2135), .Q(
d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(n929), .CK(clk), .RN(n2135), .Q(
d_ff3_LUT_out[16]) );
DFFRXLTS reg_LUT_Q_reg_17_ ( .D(n928), .CK(clk), .RN(n2135), .Q(
d_ff3_LUT_out[17]) );
DFFRXLTS reg_LUT_Q_reg_18_ ( .D(n927), .CK(clk), .RN(n2135), .Q(
d_ff3_LUT_out[18]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n926), .CK(clk), .RN(n2135), .QN(n2072) );
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(n925), .CK(clk), .RN(n2135), .Q(
d_ff3_LUT_out[20]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n924), .CK(clk), .RN(n2135), .Q(
d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(n923), .CK(clk), .RN(n2135), .Q(
d_ff3_LUT_out[22]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n922), .CK(clk), .RN(n2135), .Q(
d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n921), .CK(clk), .RN(n2135), .Q(
d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(n920), .CK(clk), .RN(n2135), .Q(
d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n919), .CK(clk), .RN(n2135), .Q(
d_ff3_LUT_out[26]) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(n918), .CK(clk), .RN(n2134), .Q(
d_ff3_LUT_out[27]) );
DFFRXLTS reg_LUT_Q_reg_28_ ( .D(n917), .CK(clk), .RN(n2134), .Q(
d_ff3_LUT_out[28]) );
DFFRXLTS reg_LUT_Q_reg_29_ ( .D(n916), .CK(clk), .RN(n2134), .Q(
d_ff3_LUT_out[29]) );
DFFRXLTS reg_LUT_Q_reg_30_ ( .D(n915), .CK(clk), .RN(n2134), .Q(
d_ff3_LUT_out[30]) );
DFFRXLTS reg_LUT_Q_reg_31_ ( .D(n914), .CK(clk), .RN(n2134), .Q(
d_ff3_LUT_out[31]) );
DFFRXLTS reg_LUT_Q_reg_32_ ( .D(n913), .CK(clk), .RN(n2134), .Q(
d_ff3_LUT_out[32]) );
DFFRXLTS reg_LUT_Q_reg_33_ ( .D(n912), .CK(clk), .RN(n2134), .Q(
d_ff3_LUT_out[33]) );
DFFRXLTS reg_LUT_Q_reg_34_ ( .D(n911), .CK(clk), .RN(n2134), .Q(
d_ff3_LUT_out[34]) );
DFFRXLTS reg_LUT_Q_reg_35_ ( .D(n910), .CK(clk), .RN(n2134), .Q(
d_ff3_LUT_out[35]) );
DFFRXLTS reg_LUT_Q_reg_36_ ( .D(n909), .CK(clk), .RN(n2134), .Q(
d_ff3_LUT_out[36]) );
DFFRXLTS reg_LUT_Q_reg_37_ ( .D(n908), .CK(clk), .RN(n2134), .Q(
d_ff3_LUT_out[37]) );
DFFRXLTS reg_LUT_Q_reg_38_ ( .D(n907), .CK(clk), .RN(n2134), .Q(
d_ff3_LUT_out[38]) );
DFFRXLTS reg_LUT_Q_reg_39_ ( .D(n906), .CK(clk), .RN(n2161), .Q(
d_ff3_LUT_out[39]) );
DFFRXLTS reg_LUT_Q_reg_40_ ( .D(n905), .CK(clk), .RN(n2162), .Q(
d_ff3_LUT_out[40]) );
DFFRXLTS reg_LUT_Q_reg_41_ ( .D(n904), .CK(clk), .RN(n2163), .QN(n2186) );
DFFRXLTS reg_LUT_Q_reg_42_ ( .D(n903), .CK(clk), .RN(n2149), .Q(
d_ff3_LUT_out[42]) );
DFFRXLTS reg_LUT_Q_reg_43_ ( .D(n902), .CK(clk), .RN(n2160), .Q(
d_ff3_LUT_out[43]) );
DFFRXLTS reg_LUT_Q_reg_44_ ( .D(n901), .CK(clk), .RN(n2155), .Q(
d_ff3_LUT_out[44]) );
DFFRXLTS reg_LUT_Q_reg_45_ ( .D(n900), .CK(clk), .RN(n2154), .Q(
d_ff3_LUT_out[45]) );
DFFRXLTS reg_LUT_Q_reg_46_ ( .D(n899), .CK(clk), .RN(n2137), .Q(
d_ff3_LUT_out[46]) );
DFFRXLTS reg_LUT_Q_reg_47_ ( .D(n898), .CK(clk), .RN(n2150), .Q(
d_ff3_LUT_out[47]) );
DFFRXLTS reg_LUT_Q_reg_49_ ( .D(n896), .CK(clk), .RN(n2159), .Q(
d_ff3_LUT_out[49]) );
DFFRXLTS reg_LUT_Q_reg_50_ ( .D(n895), .CK(clk), .RN(n2135), .Q(
d_ff3_LUT_out[50]) );
DFFRXLTS reg_LUT_Q_reg_52_ ( .D(n894), .CK(clk), .RN(n2135), .Q(
d_ff3_LUT_out[52]) );
DFFRXLTS reg_LUT_Q_reg_53_ ( .D(n893), .CK(clk), .RN(n2158), .Q(
d_ff3_LUT_out[53]), .QN(n2128) );
DFFRXLTS reg_LUT_Q_reg_54_ ( .D(n892), .CK(clk), .RN(n2159), .Q(
d_ff3_LUT_out[54]) );
DFFRXLTS reg_LUT_Q_reg_55_ ( .D(n891), .CK(clk), .RN(n2160), .Q(
d_ff3_LUT_out[55]) );
DFFRXLTS reg_LUT_Q_reg_56_ ( .D(n890), .CK(clk), .RN(n2153), .Q(
d_ff3_LUT_out[56]) );
DFFRXLTS reg_shift_y_Q_reg_52_ ( .D(n709), .CK(clk), .RN(n2154), .Q(
d_ff3_sh_y_out[52]) );
DFFRXLTS reg_shift_y_Q_reg_53_ ( .D(n708), .CK(clk), .RN(n2155), .Q(
d_ff3_sh_y_out[53]) );
DFFRXLTS reg_shift_y_Q_reg_54_ ( .D(n707), .CK(clk), .RN(n2133), .Q(
d_ff3_sh_y_out[54]) );
DFFRXLTS reg_shift_y_Q_reg_55_ ( .D(n706), .CK(clk), .RN(n2151), .Q(
d_ff3_sh_y_out[55]) );
DFFRXLTS reg_shift_y_Q_reg_56_ ( .D(n705), .CK(clk), .RN(n2152), .Q(
d_ff3_sh_y_out[56]) );
DFFRXLTS reg_shift_y_Q_reg_57_ ( .D(n704), .CK(clk), .RN(n2133), .Q(
d_ff3_sh_y_out[57]) );
DFFRXLTS reg_shift_y_Q_reg_58_ ( .D(n703), .CK(clk), .RN(n2134), .Q(
d_ff3_sh_y_out[58]) );
DFFRXLTS reg_shift_y_Q_reg_59_ ( .D(n702), .CK(clk), .RN(n2161), .Q(
d_ff3_sh_y_out[59]) );
DFFRXLTS reg_shift_y_Q_reg_60_ ( .D(n701), .CK(clk), .RN(n2162), .Q(
d_ff3_sh_y_out[60]) );
DFFRXLTS reg_shift_y_Q_reg_61_ ( .D(n700), .CK(clk), .RN(n2163), .Q(
d_ff3_sh_y_out[61]) );
DFFRXLTS reg_shift_y_Q_reg_62_ ( .D(n699), .CK(clk), .RN(n2149), .Q(
d_ff3_sh_y_out[62]) );
DFFRXLTS reg_shift_x_Q_reg_52_ ( .D(n581), .CK(clk), .RN(n2137), .Q(
d_ff3_sh_x_out[52]) );
DFFRXLTS reg_shift_x_Q_reg_53_ ( .D(n580), .CK(clk), .RN(n2150), .Q(
d_ff3_sh_x_out[53]) );
DFFRXLTS reg_shift_x_Q_reg_54_ ( .D(n579), .CK(clk), .RN(n2148), .Q(
d_ff3_sh_x_out[54]) );
DFFRXLTS reg_shift_x_Q_reg_55_ ( .D(n578), .CK(clk), .RN(n2136), .Q(
d_ff3_sh_x_out[55]) );
DFFRXLTS reg_shift_x_Q_reg_56_ ( .D(n577), .CK(clk), .RN(n2134), .Q(
d_ff3_sh_x_out[56]) );
DFFRXLTS reg_shift_x_Q_reg_57_ ( .D(n576), .CK(clk), .RN(n2138), .Q(
d_ff3_sh_x_out[57]) );
DFFRXLTS reg_shift_x_Q_reg_58_ ( .D(n575), .CK(clk), .RN(n2158), .Q(
d_ff3_sh_x_out[58]) );
DFFRXLTS reg_shift_x_Q_reg_59_ ( .D(n574), .CK(clk), .RN(n2153), .Q(
d_ff3_sh_x_out[59]) );
DFFRXLTS reg_shift_x_Q_reg_60_ ( .D(n573), .CK(clk), .RN(n2133), .Q(
d_ff3_sh_x_out[60]) );
DFFRXLTS reg_shift_x_Q_reg_61_ ( .D(n572), .CK(clk), .RN(n2133), .Q(
d_ff3_sh_x_out[61]) );
DFFRXLTS reg_shift_x_Q_reg_62_ ( .D(n571), .CK(clk), .RN(n2133), .Q(
d_ff3_sh_x_out[62]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n889), .CK(clk), .RN(n2133), .Q(
d_ff2_Z[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n887), .CK(clk), .RN(n2133), .Q(
d_ff2_Z[2]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n886), .CK(clk), .RN(n2133), .Q(
d_ff2_Z[3]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n885), .CK(clk), .RN(n2133), .Q(
d_ff2_Z[4]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n884), .CK(clk), .RN(n2133), .Q(
d_ff2_Z[5]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n883), .CK(clk), .RN(n2133), .Q(
d_ff2_Z[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n882), .CK(clk), .RN(n2133), .Q(
d_ff2_Z[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n881), .CK(clk), .RN(n2168), .Q(
d_ff2_Z[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n880), .CK(clk), .RN(n2169), .Q(
d_ff2_Z[9]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n879), .CK(clk), .RN(n2170), .Q(
d_ff2_Z[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n878), .CK(clk), .RN(n2138), .Q(
d_ff2_Z[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n877), .CK(clk), .RN(n2167), .Q(
d_ff2_Z[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n876), .CK(clk), .RN(n2164), .Q(
d_ff2_Z[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n875), .CK(clk), .RN(n2165), .Q(
d_ff2_Z[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n874), .CK(clk), .RN(n2166), .Q(
d_ff2_Z[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n873), .CK(clk), .RN(n2169), .Q(
d_ff2_Z[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n872), .CK(clk), .RN(n2132), .Q(
d_ff2_Z[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n871), .CK(clk), .RN(n2174), .Q(
d_ff2_Z[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n870), .CK(clk), .RN(n2168), .Q(
d_ff2_Z[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n869), .CK(clk), .RN(n2132), .Q(
d_ff2_Z[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n867), .CK(clk), .RN(n2132), .Q(
d_ff2_Z[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n866), .CK(clk), .RN(n2132), .Q(
d_ff2_Z[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n864), .CK(clk), .RN(n2132), .Q(
d_ff2_Z[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n863), .CK(clk), .RN(n2132), .Q(
d_ff2_Z[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n862), .CK(clk), .RN(n2132), .Q(
d_ff2_Z[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n861), .CK(clk), .RN(n2132), .Q(
d_ff2_Z[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n860), .CK(clk), .RN(n2132), .Q(
d_ff2_Z[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n859), .CK(clk), .RN(n2132), .Q(
d_ff2_Z[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n858), .CK(clk), .RN(n2132), .Q(
d_ff2_Z[31]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_32_ ( .D(n857), .CK(clk), .RN(n2170), .Q(
d_ff2_Z[32]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_33_ ( .D(n856), .CK(clk), .RN(n2151), .Q(
d_ff2_Z[33]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_34_ ( .D(n855), .CK(clk), .RN(n2167), .Q(
d_ff2_Z[34]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_35_ ( .D(n854), .CK(clk), .RN(n2164), .Q(
d_ff2_Z[35]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_36_ ( .D(n853), .CK(clk), .RN(n2165), .Q(
d_ff2_Z[36]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_37_ ( .D(n852), .CK(clk), .RN(n2166), .Q(
d_ff2_Z[37]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_38_ ( .D(n851), .CK(clk), .RN(n2132), .Q(
d_ff2_Z[38]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_39_ ( .D(n850), .CK(clk), .RN(n2175), .Q(
d_ff2_Z[39]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_40_ ( .D(n849), .CK(clk), .RN(n2153), .Q(
d_ff2_Z[40]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_41_ ( .D(n848), .CK(clk), .RN(n2167), .Q(
d_ff2_Z[41]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_43_ ( .D(n846), .CK(clk), .RN(n2165), .Q(
d_ff2_Z[43]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_44_ ( .D(n845), .CK(clk), .RN(n2145), .Q(
d_ff2_Z[44]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_45_ ( .D(n844), .CK(clk), .RN(n2146), .Q(
d_ff2_Z[45]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_46_ ( .D(n843), .CK(clk), .RN(n2147), .Q(
d_ff2_Z[46]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_47_ ( .D(n842), .CK(clk), .RN(n2142), .Q(
d_ff2_Z[47]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_50_ ( .D(n839), .CK(clk), .RN(n2139), .Q(
d_ff2_Z[50]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_51_ ( .D(n838), .CK(clk), .RN(n2140), .Q(
d_ff2_Z[51]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_52_ ( .D(n837), .CK(clk), .RN(n2141), .Q(
d_ff2_Z[52]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_54_ ( .D(n835), .CK(clk), .RN(n2131), .Q(
d_ff2_Z[54]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_55_ ( .D(n834), .CK(clk), .RN(n2145), .Q(
d_ff2_Z[55]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_56_ ( .D(n833), .CK(clk), .RN(n2131), .Q(
d_ff2_Z[56]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_57_ ( .D(n832), .CK(clk), .RN(n2131), .Q(
d_ff2_Z[57]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_58_ ( .D(n831), .CK(clk), .RN(n2131), .Q(
d_ff2_Z[58]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_59_ ( .D(n830), .CK(clk), .RN(n2131), .Q(
d_ff2_Z[59]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_60_ ( .D(n829), .CK(clk), .RN(n2131), .Q(
d_ff2_Z[60]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_61_ ( .D(n828), .CK(clk), .RN(n2131), .Q(
d_ff2_Z[61]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_62_ ( .D(n827), .CK(clk), .RN(n2131), .Q(
d_ff2_Z[62]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n823), .CK(clk), .RN(n2131), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n821), .CK(clk), .RN(n2147), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n819), .CK(clk), .RN(n2143), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n817), .CK(clk), .RN(n2139), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n815), .CK(clk), .RN(n2141), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n813), .CK(clk), .RN(n2142), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n811), .CK(clk), .RN(n2144), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n809), .CK(clk), .RN(n2172), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n807), .CK(clk), .RN(n2176), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n805), .CK(clk), .RN(n2176), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n803), .CK(clk), .RN(n2166), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n801), .CK(clk), .RN(n2180), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n799), .CK(clk), .RN(n2177), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n797), .CK(clk), .RN(n2130), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n795), .CK(clk), .RN(n2130), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n793), .CK(clk), .RN(n2130), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n791), .CK(clk), .RN(n2130), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n789), .CK(clk), .RN(n2130), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n787), .CK(clk), .RN(n2130), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n785), .CK(clk), .RN(n2153), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n783), .CK(clk), .RN(n2153), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n781), .CK(clk), .RN(n2151), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n779), .CK(clk), .RN(n2136), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(n777), .CK(clk), .RN(n2160), .Q(
d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n775), .CK(clk), .RN(n2137), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n773), .CK(clk), .RN(n2148), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n771), .CK(clk), .RN(n2135), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n769), .CK(clk), .RN(n2152), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n767), .CK(clk), .RN(n2152), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n765), .CK(clk), .RN(n2152), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n763), .CK(clk), .RN(n2152), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n761), .CK(clk), .RN(n2152), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS reg_shift_y_Q_reg_32_ ( .D(n759), .CK(clk), .RN(n2152), .Q(
d_ff3_sh_y_out[32]) );
DFFRXLTS reg_shift_y_Q_reg_33_ ( .D(n757), .CK(clk), .RN(n2151), .Q(
d_ff3_sh_y_out[33]) );
DFFRXLTS reg_shift_y_Q_reg_34_ ( .D(n755), .CK(clk), .RN(n2151), .Q(
d_ff3_sh_y_out[34]) );
DFFRXLTS reg_shift_y_Q_reg_35_ ( .D(n753), .CK(clk), .RN(n2151), .Q(
d_ff3_sh_y_out[35]) );
DFFRXLTS reg_shift_y_Q_reg_36_ ( .D(n751), .CK(clk), .RN(n2151), .Q(
d_ff3_sh_y_out[36]) );
DFFRXLTS reg_shift_y_Q_reg_37_ ( .D(n749), .CK(clk), .RN(n2151), .Q(
d_ff3_sh_y_out[37]) );
DFFRXLTS reg_shift_y_Q_reg_38_ ( .D(n747), .CK(clk), .RN(n2151), .Q(
d_ff3_sh_y_out[38]) );
DFFRXLTS reg_shift_y_Q_reg_39_ ( .D(n745), .CK(clk), .RN(n2150), .Q(
d_ff3_sh_y_out[39]) );
DFFRXLTS reg_shift_y_Q_reg_40_ ( .D(n743), .CK(clk), .RN(n2150), .Q(
d_ff3_sh_y_out[40]) );
DFFRXLTS reg_shift_y_Q_reg_41_ ( .D(n741), .CK(clk), .RN(n2150), .Q(
d_ff3_sh_y_out[41]) );
DFFRXLTS reg_shift_y_Q_reg_42_ ( .D(n739), .CK(clk), .RN(n2150), .Q(
d_ff3_sh_y_out[42]) );
DFFRXLTS reg_shift_y_Q_reg_43_ ( .D(n737), .CK(clk), .RN(n2150), .Q(
d_ff3_sh_y_out[43]) );
DFFRXLTS reg_shift_y_Q_reg_44_ ( .D(n735), .CK(clk), .RN(n2150), .Q(
d_ff3_sh_y_out[44]) );
DFFRXLTS reg_shift_y_Q_reg_45_ ( .D(n733), .CK(clk), .RN(n2149), .Q(
d_ff3_sh_y_out[45]) );
DFFRXLTS reg_shift_y_Q_reg_46_ ( .D(n731), .CK(clk), .RN(n2149), .Q(
d_ff3_sh_y_out[46]) );
DFFRXLTS reg_shift_y_Q_reg_47_ ( .D(n729), .CK(clk), .RN(n2149), .Q(
d_ff3_sh_y_out[47]) );
DFFRXLTS reg_shift_y_Q_reg_48_ ( .D(n727), .CK(clk), .RN(n2149), .Q(
d_ff3_sh_y_out[48]) );
DFFRXLTS reg_shift_y_Q_reg_49_ ( .D(n725), .CK(clk), .RN(n2149), .Q(
d_ff3_sh_y_out[49]) );
DFFRXLTS reg_shift_y_Q_reg_50_ ( .D(n723), .CK(clk), .RN(n2149), .Q(
d_ff3_sh_y_out[50]) );
DFFRXLTS reg_shift_y_Q_reg_51_ ( .D(n721), .CK(clk), .RN(n2148), .Q(
d_ff3_sh_y_out[51]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_59_ ( .D(n713), .CK(clk), .RN(n2148), .Q(
d_ff2_Y[59]), .QN(n2063) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_62_ ( .D(n710), .CK(clk), .RN(n2148), .Q(
d_ff2_Y[62]), .QN(n2065) );
DFFRXLTS reg_shift_y_Q_reg_63_ ( .D(n697), .CK(clk), .RN(n2147), .Q(
d_ff3_sh_y_out[63]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n695), .CK(clk), .RN(n2147), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n693), .CK(clk), .RN(n2147), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n691), .CK(clk), .RN(n2147), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n689), .CK(clk), .RN(n2147), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n687), .CK(clk), .RN(n2147), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n685), .CK(clk), .RN(n2146), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n683), .CK(clk), .RN(n2146), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n681), .CK(clk), .RN(n2146), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n679), .CK(clk), .RN(n2146), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n677), .CK(clk), .RN(n2146), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n675), .CK(clk), .RN(n2145), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n673), .CK(clk), .RN(n2145), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n671), .CK(clk), .RN(n2145), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n669), .CK(clk), .RN(n2145), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n667), .CK(clk), .RN(n2145), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n665), .CK(clk), .RN(n2145), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n663), .CK(clk), .RN(n2144), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n661), .CK(clk), .RN(n2144), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n659), .CK(clk), .RN(n2144), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n657), .CK(clk), .RN(n2144), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n655), .CK(clk), .RN(n2144), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n653), .CK(clk), .RN(n2144), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n2143), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n2143), .Q(
d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n647), .CK(clk), .RN(n2143), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n645), .CK(clk), .RN(n2143), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n643), .CK(clk), .RN(n2143), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n641), .CK(clk), .RN(n2143), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n639), .CK(clk), .RN(n2142), .Q(
d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n637), .CK(clk), .RN(n2142), .Q(
d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n635), .CK(clk), .RN(n2142), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n633), .CK(clk), .RN(n2142), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_32_ ( .D(n631), .CK(clk), .RN(n2142), .Q(
d_ff3_sh_x_out[32]) );
DFFRXLTS reg_shift_x_Q_reg_33_ ( .D(n629), .CK(clk), .RN(n2142), .Q(
d_ff3_sh_x_out[33]) );
DFFRXLTS reg_shift_x_Q_reg_34_ ( .D(n627), .CK(clk), .RN(n2141), .Q(
d_ff3_sh_x_out[34]) );
DFFRXLTS reg_shift_x_Q_reg_35_ ( .D(n625), .CK(clk), .RN(n2141), .Q(
d_ff3_sh_x_out[35]) );
DFFRXLTS reg_shift_x_Q_reg_36_ ( .D(n623), .CK(clk), .RN(n2141), .Q(
d_ff3_sh_x_out[36]) );
DFFRXLTS reg_shift_x_Q_reg_37_ ( .D(n621), .CK(clk), .RN(n2141), .Q(
d_ff3_sh_x_out[37]) );
DFFRXLTS reg_shift_x_Q_reg_38_ ( .D(n619), .CK(clk), .RN(n2141), .Q(
d_ff3_sh_x_out[38]) );
DFFRXLTS reg_shift_x_Q_reg_39_ ( .D(n617), .CK(clk), .RN(n2141), .Q(
d_ff3_sh_x_out[39]) );
DFFRXLTS reg_shift_x_Q_reg_40_ ( .D(n615), .CK(clk), .RN(n2140), .Q(
d_ff3_sh_x_out[40]) );
DFFRXLTS reg_shift_x_Q_reg_41_ ( .D(n613), .CK(clk), .RN(n2140), .Q(
d_ff3_sh_x_out[41]) );
DFFRXLTS reg_shift_x_Q_reg_42_ ( .D(n611), .CK(clk), .RN(n2140), .Q(
d_ff3_sh_x_out[42]) );
DFFRXLTS reg_shift_x_Q_reg_43_ ( .D(n609), .CK(clk), .RN(n2140), .Q(
d_ff3_sh_x_out[43]) );
DFFRXLTS reg_shift_x_Q_reg_44_ ( .D(n607), .CK(clk), .RN(n2140), .Q(
d_ff3_sh_x_out[44]) );
DFFRXLTS reg_shift_x_Q_reg_45_ ( .D(n605), .CK(clk), .RN(n2140), .Q(
d_ff3_sh_x_out[45]) );
DFFRXLTS reg_shift_x_Q_reg_46_ ( .D(n603), .CK(clk), .RN(n2139), .Q(
d_ff3_sh_x_out[46]) );
DFFRXLTS reg_shift_x_Q_reg_47_ ( .D(n601), .CK(clk), .RN(n2139), .Q(
d_ff3_sh_x_out[47]) );
DFFRXLTS reg_shift_x_Q_reg_48_ ( .D(n599), .CK(clk), .RN(n2139), .Q(
d_ff3_sh_x_out[48]) );
DFFRXLTS reg_shift_x_Q_reg_49_ ( .D(n597), .CK(clk), .RN(n2139), .Q(
d_ff3_sh_x_out[49]) );
DFFRXLTS reg_shift_x_Q_reg_50_ ( .D(n595), .CK(clk), .RN(n2139), .Q(
d_ff3_sh_x_out[50]) );
DFFRXLTS reg_shift_x_Q_reg_51_ ( .D(n593), .CK(clk), .RN(n2139), .Q(
d_ff3_sh_x_out[51]) );
DFFRXLTS reg_shift_x_Q_reg_63_ ( .D(n569), .CK(clk), .RN(n2153), .Q(
d_ff3_sh_x_out[63]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_53_ ( .D(n591), .CK(clk), .RN(n2138), .Q(
d_ff2_X[53]), .QN(n2071) );
DFFRX2TS cordic_FSM_state_reg_reg_1_ ( .D(cordic_FSM_state_next_1_), .CK(clk), .RN(n564), .Q(cordic_FSM_state_reg[1]), .QN(n2069) );
DFFRX4TS cont_iter_count_reg_0_ ( .D(n1341), .CK(clk), .RN(n2180), .Q(n2129),
.QN(n1485) );
DFFRX4TS cont_iter_count_reg_2_ ( .D(n1339), .CK(clk), .RN(n2171), .Q(
cont_iter_out[2]), .QN(n2070) );
DFFRX4TS cordic_FSM_state_reg_reg_3_ ( .D(n1345), .CK(clk), .RN(n564), .Q(
cordic_FSM_state_reg[3]), .QN(n2187) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_61_ ( .D(n583), .CK(clk), .RN(n2138), .Q(
d_ff2_X[61]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_59_ ( .D(n585), .CK(clk), .RN(n2138), .Q(
d_ff2_X[59]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_57_ ( .D(n587), .CK(clk), .RN(n2138), .Q(
d_ff2_X[57]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_60_ ( .D(n712), .CK(clk), .RN(n2148),
.QN(n2201) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_58_ ( .D(n714), .CK(clk), .RN(n2148),
.QN(n2200) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_56_ ( .D(n716), .CK(clk), .RN(n2148),
.QN(n2199) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_54_ ( .D(n590), .CK(clk), .RN(n2138), .Q(
d_ff2_X[54]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_54_ ( .D(n718), .CK(clk), .RN(n2148), .Q(
d_ff2_Y[54]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_63_ ( .D(n826), .CK(clk), .RN(n2131), .Q(
d_ff2_Z[63]) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n1335), .CK(clk), .RN(n2170), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n2073) );
DFFRX1TS cont_var_count_reg_1_ ( .D(n1342), .CK(clk), .RN(n2179), .Q(
cont_var_out[1]), .QN(n1483) );
DFFRX1TS d_ff4_Yn_Q_reg_62_ ( .D(n1139), .CK(clk), .RN(n2174), .QN(n2197) );
DFFRX1TS d_ff4_Yn_Q_reg_61_ ( .D(n1140), .CK(clk), .RN(n2174), .QN(n2196) );
DFFRX1TS d_ff4_Yn_Q_reg_59_ ( .D(n1142), .CK(clk), .RN(n2174), .QN(n2194) );
DFFRX1TS d_ff4_Yn_Q_reg_55_ ( .D(n1146), .CK(clk), .RN(n2173), .QN(n2190) );
DFFRX1TS d_ff4_Yn_Q_reg_53_ ( .D(n1148), .CK(clk), .RN(n2173), .QN(n2189) );
DFFRX1TS d_ff4_Yn_Q_reg_52_ ( .D(n1149), .CK(clk), .RN(n2177), .QN(n2188) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(n1336), .CK(clk), .RN(n2130), .Q(
d_ff1_operation_out), .QN(n2066) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_49_ ( .D(n598), .CK(clk), .RN(n2139), .Q(
d_ff2_X[49]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_46_ ( .D(n604), .CK(clk), .RN(n2140), .Q(
d_ff2_X[46]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_45_ ( .D(n606), .CK(clk), .RN(n2140), .Q(
d_ff2_X[45]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_42_ ( .D(n612), .CK(clk), .RN(n2140), .Q(
d_ff2_X[42]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_41_ ( .D(n614), .CK(clk), .RN(n2140), .Q(
d_ff2_X[41]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_39_ ( .D(n618), .CK(clk), .RN(n2141), .Q(
d_ff2_X[39]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_34_ ( .D(n628), .CK(clk), .RN(n2142), .Q(
d_ff2_X[34]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n634), .CK(clk), .RN(n2142), .Q(
d_ff2_X[31]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n640), .CK(clk), .RN(n2143), .Q(
d_ff2_X[28]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n644), .CK(clk), .RN(n2143), .Q(
d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n648), .CK(clk), .RN(n2143), .Q(
d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n658), .CK(clk), .RN(n2144), .Q(
d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n668), .CK(clk), .RN(n2145), .Q(
d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n670), .CK(clk), .RN(n2145), .Q(
d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n674), .CK(clk), .RN(n2145), .Q(
d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n678), .CK(clk), .RN(n2146), .Q(
d_ff2_X[9]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n680), .CK(clk), .RN(n2146), .Q(
d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n682), .CK(clk), .RN(n2146), .Q(
d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n684), .CK(clk), .RN(n2146), .Q(
d_ff2_X[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n690), .CK(clk), .RN(n2147), .Q(
d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n696), .CK(clk), .RN(n2147), .Q(
d_ff2_X[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_63_ ( .D(n698), .CK(clk), .RN(n2147), .Q(
d_ff2_Y[63]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_51_ ( .D(n722), .CK(clk), .RN(n2149), .Q(
d_ff2_Y[51]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_50_ ( .D(n724), .CK(clk), .RN(n2149), .Q(
d_ff2_Y[50]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_49_ ( .D(n726), .CK(clk), .RN(n2149), .Q(
d_ff2_Y[49]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_47_ ( .D(n730), .CK(clk), .RN(n2149), .Q(
d_ff2_Y[47]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_46_ ( .D(n732), .CK(clk), .RN(n2149), .Q(
d_ff2_Y[46]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_45_ ( .D(n734), .CK(clk), .RN(n2150), .Q(
d_ff2_Y[45]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_42_ ( .D(n740), .CK(clk), .RN(n2150), .Q(
d_ff2_Y[42]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_41_ ( .D(n742), .CK(clk), .RN(n2150), .Q(
d_ff2_Y[41]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_39_ ( .D(n746), .CK(clk), .RN(n2151), .Q(
d_ff2_Y[39]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_34_ ( .D(n756), .CK(clk), .RN(n2151), .Q(
d_ff2_Y[34]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_33_ ( .D(n758), .CK(clk), .RN(n2152), .Q(
d_ff2_Y[33]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n762), .CK(clk), .RN(n2152), .Q(
d_ff2_Y[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n768), .CK(clk), .RN(n2152), .Q(
d_ff2_Y[28]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n770), .CK(clk), .RN(n2154), .Q(
d_ff2_Y[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n772), .CK(clk), .RN(n2159), .Q(
d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n776), .CK(clk), .RN(n2155), .Q(
d_ff2_Y[24]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n778), .CK(clk), .RN(n2138), .Q(
d_ff2_Y[23]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n780), .CK(clk), .RN(n2152), .Q(
d_ff2_Y[22]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n782), .CK(clk), .RN(n2153), .Q(
d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n784), .CK(clk), .RN(n2153), .Q(
d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n786), .CK(clk), .RN(n2133), .Q(
d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n788), .CK(clk), .RN(n2130), .Q(
d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n790), .CK(clk), .RN(n2130), .Q(
d_ff2_Y[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n792), .CK(clk), .RN(n2130), .Q(
d_ff2_Y[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n794), .CK(clk), .RN(n2130), .Q(
d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n796), .CK(clk), .RN(n2130), .Q(
d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n798), .CK(clk), .RN(n2178), .Q(
d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n800), .CK(clk), .RN(n2179), .Q(
d_ff2_Y[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n802), .CK(clk), .RN(n2171), .Q(
d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n804), .CK(clk), .RN(n2132), .Q(
d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n806), .CK(clk), .RN(n2172), .Q(
d_ff2_Y[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n808), .CK(clk), .RN(n2172), .Q(
d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n810), .CK(clk), .RN(n2139), .Q(
d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n812), .CK(clk), .RN(n2143), .Q(
d_ff2_Y[6]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n814), .CK(clk), .RN(n2131), .Q(
d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n816), .CK(clk), .RN(n2140), .Q(
d_ff2_Y[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n818), .CK(clk), .RN(n2144), .Q(
d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n820), .CK(clk), .RN(n2142), .Q(
d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n822), .CK(clk), .RN(n2131), .Q(
d_ff2_Y[1]) );
DFFRX1TS d_ff4_Xn_Q_reg_43_ ( .D(n1094), .CK(clk), .RN(n2170), .Q(
d_ff_Xn[43]) );
DFFRX1TS d_ff4_Xn_Q_reg_36_ ( .D(n1101), .CK(clk), .RN(n2171), .Q(
d_ff_Xn[36]) );
DFFRX1TS d_ff4_Xn_Q_reg_35_ ( .D(n1102), .CK(clk), .RN(n2171), .Q(
d_ff_Xn[35]) );
DFFRX1TS d_ff4_Xn_Q_reg_32_ ( .D(n1105), .CK(clk), .RN(n2172), .Q(
d_ff_Xn[32]) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n1108), .CK(clk), .RN(n2173), .Q(
d_ff_Xn[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n642), .CK(clk), .RN(n2143), .Q(
d_ff2_X[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n2143), .Q(
d_ff2_X[23]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n2144), .Q(
d_ff2_X[22]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n2144), .Q(
d_ff2_X[21]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n656), .CK(clk), .RN(n2144), .Q(
d_ff2_X[20]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n660), .CK(clk), .RN(n2144), .Q(
d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n662), .CK(clk), .RN(n2144), .Q(
d_ff2_X[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n664), .CK(clk), .RN(n2145), .Q(
d_ff2_X[16]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n666), .CK(clk), .RN(n2145), .Q(
d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n672), .CK(clk), .RN(n2145), .Q(
d_ff2_X[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n676), .CK(clk), .RN(n2146), .Q(
d_ff2_X[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n686), .CK(clk), .RN(n2146), .Q(
d_ff2_X[5]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n688), .CK(clk), .RN(n2147), .Q(
d_ff2_X[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n692), .CK(clk), .RN(n2147), .Q(
d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n694), .CK(clk), .RN(n2147), .Q(
d_ff2_X[1]) );
DFFRX1TS d_ff4_Xn_Q_reg_44_ ( .D(n1093), .CK(clk), .RN(n2170), .Q(
d_ff_Xn[44]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n1107), .CK(clk), .RN(n2172), .Q(
d_ff_Xn[30]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_52_ ( .D(n592), .CK(clk), .RN(n2139), .Q(
d_ff2_X[52]) );
DFFRX1TS reg_LUT_Q_reg_3_ ( .D(n942), .CK(clk), .RN(n2136), .Q(
d_ff3_LUT_out[3]) );
DFFRX1TS reg_LUT_Q_reg_48_ ( .D(n897), .CK(clk), .RN(n2148), .Q(
d_ff3_LUT_out[48]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_57_ ( .D(n715), .CK(clk), .RN(n2148), .Q(
d_ff2_Y[57]), .QN(n2062) );
DFFRX2TS cont_var_count_reg_0_ ( .D(n1337), .CK(clk), .RN(n2130), .Q(
cont_var_out[0]), .QN(n2184) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_55_ ( .D(n589), .CK(clk), .RN(n2138), .Q(
d_ff2_X[55]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_53_ ( .D(n719), .CK(clk), .RN(n2148), .Q(
d_ff2_Y[53]), .QN(n2198) );
DFFRX1TS reg_ch_mux_2_Q_reg_1_ ( .D(n1266), .CK(clk), .RN(n2162), .Q(
sel_mux_2_reg[1]) );
DFFRX4TS cordic_FSM_state_reg_reg_2_ ( .D(n1344), .CK(clk), .RN(n564), .Q(
cordic_FSM_state_reg[2]), .QN(n2067) );
DFFRX4TS cont_iter_count_reg_1_ ( .D(n1340), .CK(clk), .RN(n2152), .Q(
cont_iter_out[1]), .QN(n1480) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n1334), .CK(clk), .RN(n2130), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n2068) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_62_ ( .D(n582), .CK(clk), .RN(n2146), .Q(
d_ff2_X[62]) );
DFFRX1TS reg_ch_mux_2_Q_reg_0_ ( .D(n1267), .CK(clk), .RN(n2162), .Q(
sel_mux_2_reg[0]), .QN(n2183) );
DFFRX1TS d_ff4_Yn_Q_reg_56_ ( .D(n1145), .CK(clk), .RN(n2173), .QN(n2191) );
DFFRX1TS d_ff4_Yn_Q_reg_57_ ( .D(n1144), .CK(clk), .RN(n2173), .QN(n2192) );
DFFRX1TS d_ff4_Yn_Q_reg_58_ ( .D(n1143), .CK(clk), .RN(n2173), .QN(n2193) );
DFFRX1TS d_ff4_Yn_Q_reg_60_ ( .D(n1141), .CK(clk), .RN(n2174), .QN(n2195) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n638), .CK(clk), .RN(n2142), .Q(
d_ff2_X[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_32_ ( .D(n632), .CK(clk), .RN(n2142), .Q(
d_ff2_X[32]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_35_ ( .D(n626), .CK(clk), .RN(n2141), .Q(
d_ff2_X[35]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_36_ ( .D(n624), .CK(clk), .RN(n2141), .Q(
d_ff2_X[36]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_43_ ( .D(n610), .CK(clk), .RN(n2140), .Q(
d_ff2_X[43]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_48_ ( .D(n600), .CK(clk), .RN(n2139), .Q(
d_ff2_X[48]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n764), .CK(clk), .RN(n2152), .Q(
d_ff2_Y[30]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_37_ ( .D(n750), .CK(clk), .RN(n2151), .Q(
d_ff2_Y[37]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_38_ ( .D(n748), .CK(clk), .RN(n2151), .Q(
d_ff2_Y[38]) );
DFFRX1TS d_ff4_Xn_Q_reg_55_ ( .D(n1082), .CK(clk), .RN(n2167), .Q(
d_ff_Xn[55]) );
DFFRX1TS d_ff4_Xn_Q_reg_57_ ( .D(n1080), .CK(clk), .RN(n2167), .Q(
d_ff_Xn[57]) );
DFFRX1TS d_ff4_Xn_Q_reg_59_ ( .D(n1078), .CK(clk), .RN(n2161), .Q(
d_ff_Xn[59]) );
DFFRX1TS d_ff4_Xn_Q_reg_61_ ( .D(n1076), .CK(clk), .RN(n2137), .Q(
d_ff_Xn[61]) );
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n1137), .CK(clk), .RN(n2174), .Q(d_ff_Xn[0])
);
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n1134), .CK(clk), .RN(n2175), .Q(d_ff_Xn[3])
);
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n1131), .CK(clk), .RN(n2175), .Q(d_ff_Xn[6])
);
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n1130), .CK(clk), .RN(n2176), .Q(d_ff_Xn[7])
);
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n1129), .CK(clk), .RN(n2176), .Q(d_ff_Xn[8])
);
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n1128), .CK(clk), .RN(n2176), .Q(d_ff_Xn[9])
);
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n1126), .CK(clk), .RN(n2177), .Q(
d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n1124), .CK(clk), .RN(n2177), .Q(
d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n1123), .CK(clk), .RN(n2178), .Q(
d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n1118), .CK(clk), .RN(n2179), .Q(
d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n1113), .CK(clk), .RN(n2180), .Q(
d_ff_Xn[24]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n1111), .CK(clk), .RN(n2181), .Q(
d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n1109), .CK(clk), .RN(n2173), .Q(
d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n1106), .CK(clk), .RN(n2172), .Q(
d_ff_Xn[31]) );
DFFRX1TS d_ff4_Xn_Q_reg_34_ ( .D(n1103), .CK(clk), .RN(n2171), .Q(
d_ff_Xn[34]) );
DFFRX1TS d_ff4_Xn_Q_reg_39_ ( .D(n1098), .CK(clk), .RN(n2176), .Q(
d_ff_Xn[39]) );
DFFRX1TS d_ff4_Xn_Q_reg_41_ ( .D(n1096), .CK(clk), .RN(n2174), .Q(
d_ff_Xn[41]) );
DFFRX1TS d_ff4_Xn_Q_reg_42_ ( .D(n1095), .CK(clk), .RN(n2170), .Q(
d_ff_Xn[42]) );
DFFRX1TS d_ff4_Xn_Q_reg_45_ ( .D(n1092), .CK(clk), .RN(n2170), .Q(
d_ff_Xn[45]) );
DFFRX1TS d_ff4_Xn_Q_reg_46_ ( .D(n1091), .CK(clk), .RN(n2169), .Q(
d_ff_Xn[46]) );
DFFRX1TS d_ff4_Xn_Q_reg_48_ ( .D(n1089), .CK(clk), .RN(n2169), .Q(
d_ff_Xn[48]) );
DFFRX1TS d_ff4_Xn_Q_reg_49_ ( .D(n1088), .CK(clk), .RN(n2169), .Q(
d_ff_Xn[49]) );
DFFRX1TS d_ff4_Xn_Q_reg_53_ ( .D(n1084), .CK(clk), .RN(n2168), .Q(
d_ff_Xn[53]) );
DFFRX1TS d_ff4_Xn_Q_reg_54_ ( .D(n1083), .CK(clk), .RN(n2167), .Q(
d_ff_Xn[54]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_58_ ( .D(n586), .CK(clk), .RN(n2138), .Q(
d_ff2_X[58]), .QN(n2203) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_60_ ( .D(n584), .CK(clk), .RN(n2138), .Q(
d_ff2_X[60]), .QN(n2204) );
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n1136), .CK(clk), .RN(n2174), .Q(d_ff_Xn[1])
);
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n1135), .CK(clk), .RN(n2174), .Q(d_ff_Xn[2])
);
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n1133), .CK(clk), .RN(n2175), .Q(d_ff_Xn[4])
);
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n1132), .CK(clk), .RN(n2175), .Q(d_ff_Xn[5])
);
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n1127), .CK(clk), .RN(n2176), .Q(
d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n1125), .CK(clk), .RN(n2177), .Q(
d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n1122), .CK(clk), .RN(n2178), .Q(
d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n1121), .CK(clk), .RN(n2178), .Q(
d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n1120), .CK(clk), .RN(n2178), .Q(
d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n1119), .CK(clk), .RN(n2179), .Q(
d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n1117), .CK(clk), .RN(n2179), .Q(
d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n1116), .CK(clk), .RN(n2179), .Q(
d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n1115), .CK(clk), .RN(n2180), .Q(
d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n1114), .CK(clk), .RN(n2180), .Q(
d_ff_Xn[23]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n1112), .CK(clk), .RN(n2180), .Q(
d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n1110), .CK(clk), .RN(n2181), .Q(
d_ff_Xn[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_33_ ( .D(n1104), .CK(clk), .RN(n2172), .Q(
d_ff_Xn[33]) );
DFFRX1TS d_ff4_Xn_Q_reg_37_ ( .D(n1100), .CK(clk), .RN(n2171), .Q(
d_ff_Xn[37]) );
DFFRX1TS d_ff4_Xn_Q_reg_38_ ( .D(n1099), .CK(clk), .RN(n2174), .Q(
d_ff_Xn[38]) );
DFFRX1TS d_ff4_Xn_Q_reg_40_ ( .D(n1097), .CK(clk), .RN(n2179), .Q(
d_ff_Xn[40]) );
DFFRX1TS d_ff4_Xn_Q_reg_47_ ( .D(n1090), .CK(clk), .RN(n2169), .Q(
d_ff_Xn[47]) );
DFFRX1TS d_ff4_Xn_Q_reg_50_ ( .D(n1087), .CK(clk), .RN(n2168), .Q(
d_ff_Xn[50]) );
DFFRX1TS d_ff4_Xn_Q_reg_51_ ( .D(n1086), .CK(clk), .RN(n2168), .Q(
d_ff_Xn[51]) );
DFFRX1TS d_ff4_Xn_Q_reg_52_ ( .D(n1085), .CK(clk), .RN(n2168), .Q(
d_ff_Xn[52]) );
DFFRX1TS d_ff4_Xn_Q_reg_63_ ( .D(n1074), .CK(clk), .RN(n2137), .Q(
d_ff_Xn[63]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_56_ ( .D(n588), .CK(clk), .RN(n2138), .Q(
d_ff2_X[56]), .QN(n2202) );
DFFRX1TS d_ff4_Xn_Q_reg_56_ ( .D(n1081), .CK(clk), .RN(n2167), .Q(
d_ff_Xn[56]) );
DFFRX1TS d_ff4_Xn_Q_reg_58_ ( .D(n1079), .CK(clk), .RN(n2177), .Q(
d_ff_Xn[58]) );
DFFRX1TS d_ff4_Xn_Q_reg_60_ ( .D(n1077), .CK(clk), .RN(n2138), .Q(
d_ff_Xn[60]) );
DFFRX1TS d_ff4_Xn_Q_reg_62_ ( .D(n1075), .CK(clk), .RN(n2137), .Q(
d_ff_Xn[62]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_55_ ( .D(n717), .CK(clk), .RN(n2148), .Q(
d_ff2_Y[55]), .QN(n2060) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n646), .CK(clk), .RN(n2143), .Q(
d_ff2_X[25]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n636), .CK(clk), .RN(n2142), .Q(
d_ff2_X[30]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_33_ ( .D(n630), .CK(clk), .RN(n2142), .Q(
d_ff2_X[33]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_37_ ( .D(n622), .CK(clk), .RN(n2141), .Q(
d_ff2_X[37]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_38_ ( .D(n620), .CK(clk), .RN(n2141), .Q(
d_ff2_X[38]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_40_ ( .D(n616), .CK(clk), .RN(n2141), .Q(
d_ff2_X[40]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_44_ ( .D(n608), .CK(clk), .RN(n2140), .Q(
d_ff2_X[44]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_47_ ( .D(n602), .CK(clk), .RN(n2139), .Q(
d_ff2_X[47]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_50_ ( .D(n596), .CK(clk), .RN(n2139), .Q(
d_ff2_X[50]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_51_ ( .D(n594), .CK(clk), .RN(n2139), .Q(
d_ff2_X[51]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_63_ ( .D(n570), .CK(clk), .RN(n2130), .Q(
d_ff2_X[63]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n824), .CK(clk), .RN(n2131), .Q(
d_ff2_Y[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n774), .CK(clk), .RN(n2150), .Q(
d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n766), .CK(clk), .RN(n2152), .Q(
d_ff2_Y[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_32_ ( .D(n760), .CK(clk), .RN(n2152), .Q(
d_ff2_Y[32]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_35_ ( .D(n754), .CK(clk), .RN(n2151), .Q(
d_ff2_Y[35]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_36_ ( .D(n752), .CK(clk), .RN(n2151), .Q(
d_ff2_Y[36]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_40_ ( .D(n744), .CK(clk), .RN(n2150), .Q(
d_ff2_Y[40]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_43_ ( .D(n738), .CK(clk), .RN(n2150), .Q(
d_ff2_Y[43]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_44_ ( .D(n736), .CK(clk), .RN(n2150), .Q(
d_ff2_Y[44]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_48_ ( .D(n728), .CK(clk), .RN(n2149), .Q(
d_ff2_Y[48]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n825), .CK(clk), .RN(n2131), .Q(
d_ff3_sign_out) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_52_ ( .D(n720), .CK(clk), .RN(n2148), .Q(
d_ff2_Y[52]), .QN(n2061) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n888), .CK(clk), .RN(n2133), .Q(
d_ff2_Z[1]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n868), .CK(clk), .RN(n2132), .Q(
d_ff2_Z[21]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n865), .CK(clk), .RN(n2132), .Q(
d_ff2_Z[24]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_42_ ( .D(n847), .CK(clk), .RN(n2164), .Q(
d_ff2_Z[42]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_48_ ( .D(n841), .CK(clk), .RN(n2143), .Q(
d_ff2_Z[48]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_49_ ( .D(n840), .CK(clk), .RN(n2144), .Q(
d_ff2_Z[49]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_61_ ( .D(n711), .CK(clk), .RN(n2148), .Q(
d_ff2_Y[61]), .QN(n2064) );
DFFRX1TS reg_LUT_Q_reg_9_ ( .D(n936), .CK(clk), .RN(n2136), .Q(
d_ff3_LUT_out[9]) );
DFFRX4TS cordic_FSM_state_reg_reg_0_ ( .D(n1343), .CK(clk), .RN(n564), .Q(
cordic_FSM_state_reg[0]), .QN(n2182) );
DFFRX1TS reg_ch_mux_1_Q_reg_0_ ( .D(n1268), .CK(clk), .RN(n2162), .Q(
sel_mux_1_reg) );
DFFRX1TS reg_ch_mux_3_Q_reg_0_ ( .D(n1269), .CK(clk), .RN(n2162), .Q(
sel_mux_3_reg) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_53_ ( .D(n836), .CK(clk), .RN(n2146), .Q(
d_ff2_Z[53]) );
DFFRX4TS cont_iter_count_reg_3_ ( .D(n1338), .CK(clk), .RN(n2136), .Q(
cont_iter_out[3]), .QN(n1475) );
OR3X6TS U1472 ( .A(n2067), .B(n2187), .C(n1857), .Y(n1486) );
BUFX6TS U1473 ( .A(n1477), .Y(n1496) );
AOI222X1TS U1474 ( .A0(n1808), .A1(d_ff3_LUT_out[0]), .B0(n1848), .B1(
d_ff3_sh_x_out[0]), .C0(n1847), .C1(d_ff3_sh_y_out[0]), .Y(n1778) );
AOI222X1TS U1475 ( .A0(d_ff3_LUT_out[27]), .A1(n1808), .B0(n1848), .B1(
d_ff3_sh_x_out[27]), .C0(n1847), .C1(d_ff3_sh_y_out[27]), .Y(n1817) );
AOI222X1TS U1476 ( .A0(d_ff3_LUT_out[7]), .A1(n1808), .B0(n1845), .B1(
d_ff3_sh_x_out[7]), .C0(n1812), .C1(d_ff3_sh_y_out[7]), .Y(n1769) );
AOI222X1TS U1477 ( .A0(d_ff3_LUT_out[5]), .A1(n1799), .B0(n1845), .B1(
d_ff3_sh_x_out[5]), .C0(n1812), .C1(d_ff3_sh_y_out[5]), .Y(n1772) );
AOI222X1TS U1478 ( .A0(d_ff3_LUT_out[29]), .A1(n1799), .B0(n1845), .B1(
d_ff3_sh_x_out[29]), .C0(n1847), .C1(d_ff3_sh_y_out[29]), .Y(n1815) );
AOI222X1TS U1479 ( .A0(d_ff3_LUT_out[11]), .A1(n1825), .B0(n1848), .B1(
d_ff3_sh_x_out[11]), .C0(n1812), .C1(d_ff3_sh_y_out[11]), .Y(n1764) );
AOI222X1TS U1480 ( .A0(d_ff3_LUT_out[15]), .A1(n1825), .B0(n1848), .B1(
d_ff3_sh_x_out[15]), .C0(n1812), .C1(d_ff3_sh_y_out[15]), .Y(n1760) );
AOI222X1TS U1481 ( .A0(d_ff3_LUT_out[14]), .A1(n1828), .B0(n1848), .B1(
d_ff3_sh_x_out[14]), .C0(n1812), .C1(d_ff3_sh_y_out[14]), .Y(n1761) );
AOI222X1TS U1482 ( .A0(d_ff2_Z[9]), .A1(n1712), .B0(d_ff2_Y[9]), .B1(n1807),
.C0(d_ff2_X[9]), .C1(n1847), .Y(n1702) );
AOI222X1TS U1483 ( .A0(d_ff3_LUT_out[1]), .A1(n1808), .B0(n1845), .B1(
d_ff3_sh_x_out[1]), .C0(n1843), .C1(d_ff3_sh_y_out[1]), .Y(n1777) );
AOI222X1TS U1484 ( .A0(d_ff3_LUT_out[26]), .A1(n1825), .B0(n1845), .B1(
d_ff3_sh_x_out[26]), .C0(n1847), .C1(d_ff3_sh_y_out[26]), .Y(n1818) );
AOI222X1TS U1485 ( .A0(d_ff3_LUT_out[6]), .A1(n1838), .B0(n1845), .B1(
d_ff3_sh_x_out[6]), .C0(n1812), .C1(d_ff3_sh_y_out[6]), .Y(n1771) );
AOI222X1TS U1486 ( .A0(d_ff3_LUT_out[25]), .A1(n1838), .B0(n1845), .B1(
d_ff3_sh_x_out[25]), .C0(n1847), .C1(d_ff3_sh_y_out[25]), .Y(n1819) );
AOI222X1TS U1487 ( .A0(d_ff2_Z[2]), .A1(n1808), .B0(d_ff2_Y[2]), .B1(n1807),
.C0(d_ff2_X[2]), .C1(n1812), .Y(n1746) );
AOI222X1TS U1488 ( .A0(d_ff2_Z[4]), .A1(n1799), .B0(d_ff2_Y[4]), .B1(n1807),
.C0(d_ff2_X[4]), .C1(n1812), .Y(n1744) );
AOI222X1TS U1489 ( .A0(d_ff2_Z[6]), .A1(n1799), .B0(d_ff2_Y[6]), .B1(n1807),
.C0(d_ff2_X[6]), .C1(n1812), .Y(n1740) );
AOI222X1TS U1490 ( .A0(d_ff2_Z[5]), .A1(n1825), .B0(d_ff2_Y[5]), .B1(n1807),
.C0(d_ff2_X[5]), .C1(n1812), .Y(n1742) );
AOI222X1TS U1491 ( .A0(d_ff2_Z[22]), .A1(n1712), .B0(d_ff2_Y[22]), .B1(n1807), .C0(d_ff2_X[22]), .C1(n1812), .Y(n1699) );
AOI222X1TS U1492 ( .A0(d_ff2_Z[3]), .A1(n1712), .B0(d_ff2_Y[3]), .B1(n1807),
.C0(d_ff2_X[3]), .C1(n1812), .Y(n1700) );
AOI222X1TS U1493 ( .A0(d_ff2_Z[12]), .A1(n1799), .B0(d_ff2_Y[12]), .B1(n1807), .C0(d_ff2_X[12]), .C1(n1823), .Y(n1748) );
AOI222X1TS U1494 ( .A0(d_ff2_Z[15]), .A1(n1712), .B0(d_ff2_Y[15]), .B1(n1807), .C0(d_ff2_X[15]), .C1(n1823), .Y(n1714) );
AOI222X1TS U1495 ( .A0(d_ff2_Z[18]), .A1(n1712), .B0(d_ff2_Y[18]), .B1(n1807), .C0(d_ff2_X[18]), .C1(n1823), .Y(n1709) );
AOI222X1TS U1496 ( .A0(d_ff3_LUT_out[39]), .A1(n1808), .B0(n1848), .B1(
d_ff3_sh_x_out[39]), .C0(n1823), .C1(d_ff3_sh_y_out[39]), .Y(n1736) );
AOI222X1TS U1497 ( .A0(d_ff3_LUT_out[33]), .A1(n1808), .B0(n1845), .B1(
d_ff3_sh_x_out[33]), .C0(n1823), .C1(d_ff3_sh_y_out[33]), .Y(n1810) );
AOI222X1TS U1498 ( .A0(d_ff2_Z[16]), .A1(n1712), .B0(d_ff2_Y[16]), .B1(n1807), .C0(d_ff2_X[16]), .C1(n1798), .Y(n1708) );
AOI222X1TS U1499 ( .A0(d_ff2_Z[19]), .A1(n1712), .B0(d_ff2_Y[19]), .B1(n1807), .C0(d_ff2_X[19]), .C1(n1798), .Y(n1706) );
AOI222X1TS U1500 ( .A0(d_ff2_Z[38]), .A1(n1825), .B0(d_ff2_Y[38]), .B1(n1837), .C0(d_ff2_X[38]), .C1(n1798), .Y(n1789) );
AOI222X1TS U1501 ( .A0(d_ff2_Z[37]), .A1(n1808), .B0(d_ff2_Y[37]), .B1(n1837), .C0(d_ff2_X[37]), .C1(n1798), .Y(n1788) );
AOI222X1TS U1502 ( .A0(d_ff2_Z[43]), .A1(n1828), .B0(d_ff2_Y[43]), .B1(n1829), .C0(d_ff2_X[43]), .C1(n1798), .Y(n1793) );
AOI222X1TS U1503 ( .A0(d_ff2_Z[36]), .A1(n1808), .B0(d_ff2_Y[36]), .B1(n1837), .C0(d_ff2_X[36]), .C1(n1798), .Y(n1787) );
AOI222X1TS U1504 ( .A0(d_ff2_Z[40]), .A1(n1799), .B0(d_ff2_Y[40]), .B1(n1824), .C0(d_ff2_X[40]), .C1(n1798), .Y(n1791) );
AOI222X1TS U1505 ( .A0(d_ff2_Z[44]), .A1(n1838), .B0(d_ff2_Y[44]), .B1(n1824), .C0(d_ff2_X[44]), .C1(n1798), .Y(n1794) );
AOI222X1TS U1506 ( .A0(d_ff2_Z[10]), .A1(n1808), .B0(d_ff2_Y[10]), .B1(n1807), .C0(d_ff2_X[10]), .C1(n1798), .Y(n1743) );
AOI222X1TS U1507 ( .A0(d_ff2_Z[47]), .A1(n1799), .B0(d_ff2_Y[47]), .B1(n1829), .C0(d_ff2_X[47]), .C1(n1798), .Y(n1797) );
AOI222X1TS U1508 ( .A0(d_ff2_Z[8]), .A1(n1808), .B0(d_ff2_Y[8]), .B1(n1807),
.C0(d_ff2_X[8]), .C1(n1798), .Y(n1745) );
AOI222X1TS U1509 ( .A0(d_ff2_Z[13]), .A1(n1828), .B0(d_ff2_Y[13]), .B1(n1807), .C0(d_ff2_X[13]), .C1(n1798), .Y(n1749) );
AOI222X1TS U1510 ( .A0(d_ff2_Z[39]), .A1(n1799), .B0(d_ff2_Y[39]), .B1(n1824), .C0(d_ff2_X[39]), .C1(n1798), .Y(n1790) );
AOI222X1TS U1511 ( .A0(d_ff2_Z[41]), .A1(n1808), .B0(d_ff2_Y[41]), .B1(n1824), .C0(d_ff2_X[41]), .C1(n1798), .Y(n1792) );
AOI222X1TS U1512 ( .A0(d_ff2_Z[45]), .A1(n1828), .B0(d_ff2_Y[45]), .B1(n1824), .C0(d_ff2_X[45]), .C1(n1798), .Y(n1795) );
AOI222X1TS U1513 ( .A0(d_ff2_Z[46]), .A1(n1838), .B0(d_ff2_Y[46]), .B1(n1824), .C0(d_ff2_X[46]), .C1(n1798), .Y(n1796) );
AOI222X1TS U1514 ( .A0(d_ff2_Z[17]), .A1(n1712), .B0(d_ff2_Y[17]), .B1(n1807), .C0(d_ff2_X[17]), .C1(n1806), .Y(n1710) );
AOI222X1TS U1515 ( .A0(d_ff2_Z[51]), .A1(n1828), .B0(d_ff2_Y[51]), .B1(n1829), .C0(d_ff2_X[51]), .C1(n1806), .Y(n1803) );
AOI222X1TS U1516 ( .A0(d_ff2_Z[0]), .A1(n1838), .B0(d_ff2_Y[0]), .B1(n1829),
.C0(d_ff2_X[0]), .C1(n1806), .Y(n1759) );
AOI222X1TS U1517 ( .A0(d_ff2_Z[14]), .A1(n1712), .B0(d_ff2_Y[14]), .B1(n1807), .C0(d_ff2_X[14]), .C1(n1806), .Y(n1707) );
AOI222X1TS U1518 ( .A0(d_ff2_Z[20]), .A1(n1808), .B0(d_ff2_Y[20]), .B1(n1807), .C0(d_ff2_X[20]), .C1(n1806), .Y(n1809) );
AOI222X1TS U1519 ( .A0(d_ff2_Z[50]), .A1(n1825), .B0(d_ff2_Y[50]), .B1(n1824), .C0(d_ff2_X[50]), .C1(n1806), .Y(n1802) );
AOI222X1TS U1520 ( .A0(d_ff2_Z[7]), .A1(n1799), .B0(d_ff2_Y[7]), .B1(n1807),
.C0(d_ff2_X[7]), .C1(n1806), .Y(n1747) );
AOI222X1TS U1521 ( .A0(d_ff2_Z[11]), .A1(n1808), .B0(d_ff2_Y[11]), .B1(n1807), .C0(d_ff2_X[11]), .C1(n1806), .Y(n1741) );
AOI222X1TS U1522 ( .A0(d_ff2_Z[54]), .A1(n1808), .B0(d_ff2_Y[54]), .B1(n1824), .C0(d_ff2_X[54]), .C1(n1806), .Y(n1804) );
AOI222X1TS U1523 ( .A0(d_ff3_LUT_out[54]), .A1(n1838), .B0(n1829), .B1(
d_ff3_sh_x_out[54]), .C0(n1806), .C1(d_ff3_sh_y_out[54]), .Y(n1729) );
AOI222X1TS U1524 ( .A0(d_ff3_LUT_out[55]), .A1(n1838), .B0(
d_ff3_sh_y_out[55]), .B1(n1806), .C0(d_ff3_sh_x_out[55]), .C1(n1807),
.Y(n1733) );
AOI222X1TS U1525 ( .A0(d_ff2_Z[30]), .A1(n1808), .B0(d_ff2_Y[30]), .B1(n1837), .C0(d_ff2_X[30]), .C1(n1785), .Y(n1780) );
AOI222X1TS U1526 ( .A0(d_ff2_Z[35]), .A1(n1825), .B0(d_ff2_Y[35]), .B1(n1829), .C0(d_ff2_X[35]), .C1(n1785), .Y(n1786) );
AOI222X1TS U1527 ( .A0(d_ff2_Z[32]), .A1(n1838), .B0(d_ff2_Y[32]), .B1(n1837), .C0(d_ff2_X[32]), .C1(n1785), .Y(n1782) );
AOI222X1TS U1528 ( .A0(d_ff2_Z[29]), .A1(n1825), .B0(d_ff2_Y[29]), .B1(n1837), .C0(d_ff2_X[29]), .C1(n1785), .Y(n1779) );
AOI222X1TS U1529 ( .A0(d_ff2_Z[25]), .A1(n1828), .B0(d_ff2_Y[25]), .B1(n1807), .C0(d_ff2_X[25]), .C1(n1785), .Y(n1768) );
AOI222X1TS U1530 ( .A0(d_ff2_Z[23]), .A1(n1712), .B0(d_ff2_Y[23]), .B1(n1807), .C0(d_ff2_X[23]), .C1(n1785), .Y(n1704) );
AOI222X1TS U1531 ( .A0(d_ff2_Z[27]), .A1(n1712), .B0(d_ff2_Y[27]), .B1(n1837), .C0(d_ff2_X[27]), .C1(n1785), .Y(n1703) );
AOI222X1TS U1532 ( .A0(d_ff2_Z[33]), .A1(n1799), .B0(d_ff2_Y[33]), .B1(n1837), .C0(d_ff2_X[33]), .C1(n1785), .Y(n1783) );
AOI222X1TS U1533 ( .A0(d_ff2_Z[26]), .A1(n1799), .B0(d_ff2_Y[26]), .B1(n1807), .C0(d_ff2_X[26]), .C1(n1785), .Y(n1770) );
AOI222X1TS U1534 ( .A0(d_ff2_Z[28]), .A1(n1825), .B0(d_ff2_Y[28]), .B1(n1837), .C0(d_ff2_X[28]), .C1(n1785), .Y(n1773) );
AOI222X1TS U1535 ( .A0(d_ff2_Z[31]), .A1(n1825), .B0(d_ff2_Y[31]), .B1(n1837), .C0(d_ff2_X[31]), .C1(n1785), .Y(n1781) );
AOI222X1TS U1536 ( .A0(d_ff2_Z[34]), .A1(n1808), .B0(d_ff2_Y[34]), .B1(n1837), .C0(d_ff2_X[34]), .C1(n1785), .Y(n1784) );
OAI32X4TS U1537 ( .A0(cont_iter_out[1]), .A1(n2129), .A2(n1600), .B0(n1967),
.B1(n1480), .Y(n1927) );
OR2X6TS U1538 ( .A(n1508), .B(n1885), .Y(n1487) );
INVX6TS U1539 ( .A(n1507), .Y(n1876) );
OR4X4TS U1540 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[1]),
.C(n2182), .D(n2067), .Y(n1479) );
BUFX4TS U1541 ( .A(n2011), .Y(n2010) );
CLKINVX6TS U1542 ( .A(n1698), .Y(n1712) );
CMPR32X2TS U1543 ( .A(n2070), .B(d_ff2_X[54]), .C(n1594), .CO(n2035), .S(
n1504) );
CMPR32X2TS U1544 ( .A(d_ff2_Y[54]), .B(n2070), .C(n1992), .CO(n1995), .S(
n1993) );
BUFX6TS U1545 ( .A(n1887), .Y(n1476) );
NAND2X2TS U1546 ( .A(n2027), .B(sel_mux_1_reg), .Y(n2011) );
NOR2X4TS U1547 ( .A(sel_mux_3_reg), .B(n1509), .Y(n1519) );
NAND2BX4TS U1548 ( .AN(n1509), .B(sel_mux_3_reg), .Y(n1523) );
AND3X2TS U1549 ( .A(cordic_FSM_state_reg[2]), .B(n1506), .C(n2187), .Y(n1500) );
BUFX8TS U1550 ( .A(n1488), .Y(n1477) );
NAND3X2TS U1551 ( .A(n1860), .B(n2182), .C(n2187), .Y(n1622) );
BUFX6TS U1552 ( .A(n1479), .Y(n1478) );
OR2X2TS U1553 ( .A(sel_mux_2_reg[1]), .B(n2183), .Y(n1711) );
NOR2XLTS U1554 ( .A(sel_mux_2_reg[0]), .B(sel_mux_2_reg[1]), .Y(n1491) );
AOI211X1TS U1555 ( .A0(n1611), .A1(n1475), .B0(n1973), .C0(n1926), .Y(n1939)
);
AOI222X1TS U1556 ( .A0(d_ff2_Z[49]), .A1(n1799), .B0(d_ff2_Y[49]), .B1(n1829), .C0(d_ff2_X[49]), .C1(n1806), .Y(n1801) );
AOI222X1TS U1557 ( .A0(d_ff2_Z[63]), .A1(n1825), .B0(d_ff2_Y[63]), .B1(n1829), .C0(d_ff2_X[63]), .C1(n1806), .Y(n1805) );
AO22XLTS U1558 ( .A0(n1901), .A1(result_add_subt[62]), .B0(n1900), .B1(
d_ff_Xn[62]), .Y(n1075) );
AO22XLTS U1559 ( .A0(n1901), .A1(result_add_subt[60]), .B0(n1899), .B1(
d_ff_Xn[60]), .Y(n1077) );
AO22XLTS U1560 ( .A0(n1901), .A1(result_add_subt[58]), .B0(n1487), .B1(
d_ff_Xn[58]), .Y(n1079) );
AO22XLTS U1561 ( .A0(n1901), .A1(result_add_subt[56]), .B0(n1899), .B1(
d_ff_Xn[56]), .Y(n1081) );
AO22XLTS U1562 ( .A0(n1902), .A1(result_add_subt[63]), .B0(n1487), .B1(
d_ff_Xn[63]), .Y(n1074) );
AO22XLTS U1563 ( .A0(n1901), .A1(result_add_subt[52]), .B0(n1899), .B1(
d_ff_Xn[52]), .Y(n1085) );
AO22XLTS U1564 ( .A0(n1901), .A1(result_add_subt[51]), .B0(n1899), .B1(
d_ff_Xn[51]), .Y(n1086) );
AO22XLTS U1565 ( .A0(n1901), .A1(result_add_subt[50]), .B0(n1899), .B1(
d_ff_Xn[50]), .Y(n1087) );
AO22XLTS U1566 ( .A0(n1902), .A1(result_add_subt[47]), .B0(n1899), .B1(
d_ff_Xn[47]), .Y(n1090) );
AO22XLTS U1567 ( .A0(n1902), .A1(result_add_subt[40]), .B0(n1487), .B1(
d_ff_Xn[40]), .Y(n1097) );
AO22XLTS U1568 ( .A0(n1902), .A1(result_add_subt[38]), .B0(n1487), .B1(
d_ff_Xn[38]), .Y(n1099) );
AO22XLTS U1569 ( .A0(n1902), .A1(result_add_subt[37]), .B0(n1487), .B1(
d_ff_Xn[37]), .Y(n1100) );
AO22XLTS U1570 ( .A0(n1896), .A1(result_add_subt[33]), .B0(n1900), .B1(
d_ff_Xn[33]), .Y(n1104) );
AO22XLTS U1571 ( .A0(n1896), .A1(result_add_subt[27]), .B0(n1900), .B1(
d_ff_Xn[27]), .Y(n1110) );
AO22XLTS U1572 ( .A0(n1896), .A1(result_add_subt[25]), .B0(n1900), .B1(
d_ff_Xn[25]), .Y(n1112) );
AO22XLTS U1573 ( .A0(n1896), .A1(result_add_subt[23]), .B0(n1898), .B1(
d_ff_Xn[23]), .Y(n1114) );
AO22XLTS U1574 ( .A0(n1896), .A1(result_add_subt[22]), .B0(n1898), .B1(
d_ff_Xn[22]), .Y(n1115) );
AO22XLTS U1575 ( .A0(n1896), .A1(result_add_subt[21]), .B0(n1898), .B1(
d_ff_Xn[21]), .Y(n1116) );
AO22XLTS U1576 ( .A0(n1896), .A1(result_add_subt[20]), .B0(n1898), .B1(
d_ff_Xn[20]), .Y(n1117) );
AO22XLTS U1577 ( .A0(n1896), .A1(result_add_subt[18]), .B0(n1898), .B1(
d_ff_Xn[18]), .Y(n1119) );
AO22XLTS U1578 ( .A0(n1896), .A1(result_add_subt[17]), .B0(n1899), .B1(
d_ff_Xn[17]), .Y(n1120) );
AO22XLTS U1579 ( .A0(n1896), .A1(result_add_subt[16]), .B0(n1898), .B1(
d_ff_Xn[16]), .Y(n1121) );
AO22XLTS U1580 ( .A0(n1896), .A1(result_add_subt[15]), .B0(n1900), .B1(
d_ff_Xn[15]), .Y(n1122) );
AO22XLTS U1581 ( .A0(n1896), .A1(result_add_subt[12]), .B0(n1898), .B1(
d_ff_Xn[12]), .Y(n1125) );
AO22XLTS U1582 ( .A0(n1895), .A1(result_add_subt[10]), .B0(n1898), .B1(
d_ff_Xn[10]), .Y(n1127) );
AO22XLTS U1583 ( .A0(n1895), .A1(result_add_subt[5]), .B0(n1898), .B1(
d_ff_Xn[5]), .Y(n1132) );
AO22XLTS U1584 ( .A0(n1895), .A1(result_add_subt[4]), .B0(n1898), .B1(
d_ff_Xn[4]), .Y(n1133) );
AO22XLTS U1585 ( .A0(n1895), .A1(result_add_subt[2]), .B0(n1898), .B1(
d_ff_Xn[2]), .Y(n1135) );
AO22XLTS U1586 ( .A0(n1895), .A1(result_add_subt[1]), .B0(n1487), .B1(
d_ff_Xn[1]), .Y(n1136) );
AO22XLTS U1587 ( .A0(n1901), .A1(result_add_subt[54]), .B0(n1899), .B1(
d_ff_Xn[54]), .Y(n1083) );
AO22XLTS U1588 ( .A0(n1901), .A1(result_add_subt[53]), .B0(n1899), .B1(
d_ff_Xn[53]), .Y(n1084) );
AO22XLTS U1589 ( .A0(n1901), .A1(result_add_subt[49]), .B0(n1899), .B1(
d_ff_Xn[49]), .Y(n1088) );
AO22XLTS U1590 ( .A0(n1901), .A1(result_add_subt[48]), .B0(n1899), .B1(
d_ff_Xn[48]), .Y(n1089) );
AO22XLTS U1591 ( .A0(n1902), .A1(result_add_subt[46]), .B0(n1899), .B1(
d_ff_Xn[46]), .Y(n1091) );
AO22XLTS U1592 ( .A0(n1902), .A1(result_add_subt[45]), .B0(n1487), .B1(
d_ff_Xn[45]), .Y(n1092) );
AO22XLTS U1593 ( .A0(n1902), .A1(result_add_subt[42]), .B0(n1487), .B1(
d_ff_Xn[42]), .Y(n1095) );
AO22XLTS U1594 ( .A0(n1902), .A1(result_add_subt[41]), .B0(n1487), .B1(
d_ff_Xn[41]), .Y(n1096) );
AO22XLTS U1595 ( .A0(n1902), .A1(result_add_subt[39]), .B0(n1487), .B1(
d_ff_Xn[39]), .Y(n1098) );
AO22XLTS U1596 ( .A0(n1895), .A1(result_add_subt[34]), .B0(n1900), .B1(
d_ff_Xn[34]), .Y(n1103) );
AO22XLTS U1597 ( .A0(n1896), .A1(result_add_subt[31]), .B0(n1900), .B1(
d_ff_Xn[31]), .Y(n1106) );
AO22XLTS U1598 ( .A0(n1895), .A1(result_add_subt[28]), .B0(n1900), .B1(
d_ff_Xn[28]), .Y(n1109) );
AO22XLTS U1599 ( .A0(n1895), .A1(result_add_subt[26]), .B0(n1900), .B1(
d_ff_Xn[26]), .Y(n1111) );
AO22XLTS U1600 ( .A0(n1895), .A1(result_add_subt[24]), .B0(n1900), .B1(
d_ff_Xn[24]), .Y(n1113) );
AO22XLTS U1601 ( .A0(n1896), .A1(result_add_subt[19]), .B0(n1898), .B1(
d_ff_Xn[19]), .Y(n1118) );
AO22XLTS U1602 ( .A0(n1896), .A1(result_add_subt[14]), .B0(n1899), .B1(
d_ff_Xn[14]), .Y(n1123) );
AO22XLTS U1603 ( .A0(n1896), .A1(result_add_subt[13]), .B0(n1898), .B1(
d_ff_Xn[13]), .Y(n1124) );
AO22XLTS U1604 ( .A0(n1895), .A1(result_add_subt[11]), .B0(n1898), .B1(
d_ff_Xn[11]), .Y(n1126) );
AO22XLTS U1605 ( .A0(n1895), .A1(result_add_subt[9]), .B0(n1898), .B1(
d_ff_Xn[9]), .Y(n1128) );
AO22XLTS U1606 ( .A0(n1895), .A1(result_add_subt[8]), .B0(n1898), .B1(
d_ff_Xn[8]), .Y(n1129) );
AO22XLTS U1607 ( .A0(n1895), .A1(result_add_subt[7]), .B0(n1898), .B1(
d_ff_Xn[7]), .Y(n1130) );
AO22XLTS U1608 ( .A0(n1895), .A1(result_add_subt[6]), .B0(n1898), .B1(
d_ff_Xn[6]), .Y(n1131) );
AO22XLTS U1609 ( .A0(n1895), .A1(result_add_subt[3]), .B0(n1898), .B1(
d_ff_Xn[3]), .Y(n1134) );
AO22XLTS U1610 ( .A0(n1895), .A1(result_add_subt[0]), .B0(n1487), .B1(
d_ff_Xn[0]), .Y(n1137) );
AO22XLTS U1611 ( .A0(n1902), .A1(result_add_subt[61]), .B0(n1900), .B1(
d_ff_Xn[61]), .Y(n1076) );
AO22XLTS U1612 ( .A0(n1901), .A1(result_add_subt[59]), .B0(n1898), .B1(
d_ff_Xn[59]), .Y(n1078) );
AO22XLTS U1613 ( .A0(n1901), .A1(result_add_subt[57]), .B0(n1487), .B1(
d_ff_Xn[57]), .Y(n1080) );
AO22XLTS U1614 ( .A0(n1901), .A1(result_add_subt[55]), .B0(n1899), .B1(
d_ff_Xn[55]), .Y(n1082) );
OAI32X1TS U1615 ( .A0(n1517), .A1(n1477), .A2(n2183), .B0(n1886), .B1(n1518),
.Y(n1267) );
OAI32X1TS U1616 ( .A0(n1518), .A1(n1954), .A2(n1483), .B0(n1517), .B1(n1516),
.Y(n1266) );
AO22XLTS U1617 ( .A0(n1895), .A1(result_add_subt[30]), .B0(n1900), .B1(
d_ff_Xn[30]), .Y(n1107) );
AO22XLTS U1618 ( .A0(n1902), .A1(result_add_subt[44]), .B0(n1487), .B1(
d_ff_Xn[44]), .Y(n1093) );
AO22XLTS U1619 ( .A0(n1896), .A1(result_add_subt[29]), .B0(n1900), .B1(
d_ff_Xn[29]), .Y(n1108) );
AO22XLTS U1620 ( .A0(n1895), .A1(result_add_subt[32]), .B0(n1900), .B1(
d_ff_Xn[32]), .Y(n1105) );
AO22XLTS U1621 ( .A0(n1896), .A1(result_add_subt[35]), .B0(n1487), .B1(
d_ff_Xn[35]), .Y(n1102) );
AO22XLTS U1622 ( .A0(n1902), .A1(result_add_subt[36]), .B0(n1487), .B1(
d_ff_Xn[36]), .Y(n1101) );
AO22XLTS U1623 ( .A0(n1902), .A1(result_add_subt[43]), .B0(n1487), .B1(
d_ff_Xn[43]), .Y(n1094) );
AOI32X1TS U1624 ( .A0(beg_fsm_cordic), .A1(cordic_FSM_state_reg[0]), .A2(
n1834), .B0(n2182), .B1(n1833), .Y(n1836) );
NAND2BXLTS U1625 ( .AN(n1972), .B(n1971), .Y(n906) );
OR2X1TS U1626 ( .A(d_ff2_Y[59]), .B(n2002), .Y(n1481) );
NOR4X1TS U1627 ( .A(cordic_FSM_state_reg[1]), .B(n2182), .C(n2067), .D(n2187), .Y(ready_cordic) );
CLKINVX6TS U1628 ( .A(n1725), .Y(n1848) );
INVX4TS U1629 ( .A(n1725), .Y(n1845) );
BUFX6TS U1630 ( .A(n1712), .Y(n1808) );
NOR4X2TS U1631 ( .A(cordic_FSM_state_reg[3]), .B(n2182), .C(n2067), .D(n2069), .Y(beg_add_subt) );
CLKINVX6TS U1632 ( .A(n1496), .Y(n2157) );
INVX6TS U1633 ( .A(n1983), .Y(n2047) );
CLKINVX3TS U1634 ( .A(n1488), .Y(n2181) );
AND3X4TS U1635 ( .A(n1506), .B(n2067), .C(n2187), .Y(n1488) );
OAI32X1TS U1636 ( .A0(n2021), .A1(n1931), .A2(n1941), .B0(n1952), .B1(
d_ff3_LUT_out[9]), .Y(n1921) );
AOI222X1TS U1637 ( .A0(d_ff3_LUT_out[9]), .A1(n1799), .B0(n1848), .B1(
d_ff3_sh_x_out[9]), .C0(n1812), .C1(d_ff3_sh_y_out[9]), .Y(n1767) );
AOI222X1TS U1638 ( .A0(n1687), .A1(d_ff2_Z[48]), .B0(n1692), .B1(d_ff1_Z[48]), .C0(d_ff_Zn[48]), .C1(n2057), .Y(n1667) );
AOI222X1TS U1639 ( .A0(d_ff2_Z[48]), .A1(n1828), .B0(d_ff2_Y[48]), .B1(n1829), .C0(d_ff2_X[48]), .C1(n1798), .Y(n1800) );
AOI222X4TS U1640 ( .A0(n1693), .A1(d_ff2_Z[46]), .B0(n1692), .B1(d_ff1_Z[46]), .C0(d_ff_Zn[46]), .C1(n2057), .Y(n1665) );
AOI222X4TS U1641 ( .A0(n1687), .A1(d_ff2_Z[45]), .B0(n1692), .B1(d_ff1_Z[45]), .C0(d_ff_Zn[45]), .C1(n2057), .Y(n1673) );
AOI222X4TS U1642 ( .A0(n1687), .A1(d_ff2_Z[44]), .B0(n1692), .B1(d_ff1_Z[44]), .C0(d_ff_Zn[44]), .C1(n2013), .Y(n1685) );
AOI222X4TS U1643 ( .A0(n1693), .A1(d_ff2_Z[43]), .B0(n1692), .B1(d_ff1_Z[43]), .C0(d_ff_Zn[43]), .C1(n2057), .Y(n1668) );
AOI222X1TS U1644 ( .A0(n1670), .A1(d_ff2_Z[42]), .B0(n1692), .B1(d_ff1_Z[42]), .C0(d_ff_Zn[42]), .C1(n2013), .Y(n1683) );
AOI222X1TS U1645 ( .A0(d_ff2_Z[42]), .A1(n1712), .B0(d_ff2_Y[42]), .B1(n1829), .C0(d_ff2_X[42]), .C1(n1798), .Y(n1713) );
AOI222X4TS U1646 ( .A0(n1670), .A1(d_ff2_Z[41]), .B0(n1692), .B1(d_ff1_Z[41]), .C0(d_ff_Zn[41]), .C1(n2057), .Y(n1666) );
AOI222X4TS U1647 ( .A0(n1687), .A1(d_ff2_Z[40]), .B0(n1692), .B1(d_ff1_Z[40]), .C0(d_ff_Zn[40]), .C1(n2013), .Y(n1694) );
AOI222X1TS U1648 ( .A0(n1696), .A1(d_ff2_Z[24]), .B0(n1686), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n2013), .Y(n1679) );
AOI222X1TS U1649 ( .A0(d_ff2_Z[24]), .A1(n1828), .B0(d_ff2_Y[24]), .B1(n1837), .C0(d_ff2_X[24]), .C1(n1785), .Y(n1766) );
AOI222X1TS U1650 ( .A0(n1670), .A1(d_ff2_Z[21]), .B0(n1686), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n2013), .Y(n1688) );
AOI222X1TS U1651 ( .A0(d_ff2_Z[21]), .A1(n1712), .B0(d_ff2_Y[21]), .B1(n1837), .C0(d_ff2_X[21]), .C1(n1823), .Y(n1715) );
AOI222X1TS U1652 ( .A0(n1687), .A1(d_ff2_Z[1]), .B0(n1669), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n2057), .Y(n1671) );
AOI222X1TS U1653 ( .A0(d_ff2_Z[1]), .A1(n1712), .B0(d_ff2_Y[1]), .B1(n1807),
.C0(d_ff2_X[1]), .C1(n1812), .Y(n1701) );
AOI222X4TS U1654 ( .A0(n2056), .A1(d_ff2_Z[61]), .B0(n1695), .B1(d_ff1_Z[61]), .C0(d_ff_Zn[61]), .C1(n2057), .Y(n1678) );
AOI222X4TS U1655 ( .A0(n2056), .A1(d_ff2_Z[59]), .B0(n1695), .B1(d_ff1_Z[59]), .C0(d_ff_Zn[59]), .C1(n2013), .Y(n1690) );
AOI222X4TS U1656 ( .A0(n2056), .A1(d_ff2_Z[57]), .B0(n1695), .B1(d_ff1_Z[57]), .C0(d_ff_Zn[57]), .C1(n2013), .Y(n1684) );
AOI222X4TS U1657 ( .A0(n2056), .A1(d_ff2_Z[55]), .B0(n1695), .B1(d_ff1_Z[55]), .C0(d_ff_Zn[55]), .C1(n2013), .Y(n1682) );
AOI222X1TS U1658 ( .A0(n1693), .A1(d_ff2_Z[53]), .B0(n1695), .B1(d_ff1_Z[53]), .C0(d_ff_Zn[53]), .C1(n2013), .Y(n1697) );
AOI222X4TS U1659 ( .A0(n1693), .A1(d_ff2_Z[52]), .B0(n1695), .B1(d_ff1_Z[52]), .C0(d_ff_Zn[52]), .C1(n2057), .Y(n1675) );
INVX1TS U1660 ( .A(n1969), .Y(n1941) );
OAI21X2TS U1661 ( .A0(n1928), .A1(n1937), .B0(n2041), .Y(n1617) );
INVX2TS U1662 ( .A(n1481), .Y(n1484) );
OAI21X2TS U1663 ( .A0(n1938), .A1(n1927), .B0(n2041), .Y(n1911) );
BUFX3TS U1664 ( .A(n1711), .Y(n1725) );
OAI21X2TS U1665 ( .A0(n1609), .A1(n1967), .B0(n2041), .Y(n1947) );
NOR2X2TS U1666 ( .A(d_ff2_Y[52]), .B(n1485), .Y(n1990) );
OAI21X2TS U1667 ( .A0(n1615), .A1(n1600), .B0(n2041), .Y(n1935) );
OAI211X2TS U1668 ( .A0(cont_iter_out[3]), .A1(n1480), .B0(n1952), .C0(n1967),
.Y(n1940) );
CLKINVX6TS U1669 ( .A(n1478), .Y(n1952) );
AOI222X1TS U1670 ( .A0(d_ff3_sh_y_out[53]), .A1(n1847), .B0(
d_ff3_sh_x_out[53]), .B1(n1829), .C0(n1825), .C1(d_ff3_LUT_out[53]),
.Y(n1827) );
AOI222X1TS U1671 ( .A0(d_ff3_sh_y_out[56]), .A1(n1847), .B0(
d_ff3_sh_x_out[56]), .B1(n1829), .C0(n1838), .C1(d_ff3_LUT_out[56]),
.Y(n1830) );
AOI222X1TS U1672 ( .A0(d_ff3_LUT_out[45]), .A1(n1838), .B0(n1829), .B1(
d_ff3_sh_x_out[45]), .C0(n1806), .C1(d_ff3_sh_y_out[45]), .Y(n1730) );
AOI222X1TS U1673 ( .A0(d_ff3_LUT_out[50]), .A1(n1838), .B0(n1829), .B1(
d_ff3_sh_x_out[50]), .C0(n1806), .C1(d_ff3_sh_y_out[50]), .Y(n1731) );
AOI222X1TS U1674 ( .A0(d_ff3_LUT_out[47]), .A1(n1799), .B0(n1829), .B1(
d_ff3_sh_x_out[47]), .C0(n1806), .C1(d_ff3_sh_y_out[47]), .Y(n1734) );
AOI222X1TS U1675 ( .A0(n1808), .A1(d_ff3_LUT_out[46]), .B0(n1829), .B1(
d_ff3_sh_x_out[46]), .C0(n1823), .C1(d_ff3_sh_y_out[46]), .Y(n1750) );
CLKINVX6TS U1676 ( .A(n1711), .Y(n1829) );
BUFX4TS U1677 ( .A(n1712), .Y(n1828) );
BUFX4TS U1678 ( .A(n1712), .Y(n1838) );
AOI222X4TS U1679 ( .A0(n1670), .A1(d_ff2_Z[30]), .B0(n1692), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n2014), .Y(n1664) );
AOI222X4TS U1680 ( .A0(n1693), .A1(d_ff2_Z[38]), .B0(n1692), .B1(d_ff1_Z[38]), .C0(d_ff_Zn[38]), .C1(n2014), .Y(n1663) );
AOI222X4TS U1681 ( .A0(n1687), .A1(d_ff2_Z[25]), .B0(n1695), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n2014), .Y(n1662) );
AOI222X4TS U1682 ( .A0(n2026), .A1(d_ff2_Z[27]), .B0(n1692), .B1(d_ff1_Z[27]), .C0(d_ff_Zn[27]), .C1(n2014), .Y(n1661) );
AOI222X4TS U1683 ( .A0(n1670), .A1(d_ff2_Z[31]), .B0(n1695), .B1(d_ff1_Z[31]), .C0(d_ff_Zn[31]), .C1(n2014), .Y(n1660) );
AOI222X4TS U1684 ( .A0(n2030), .A1(d_ff2_Z[28]), .B0(n1695), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n2014), .Y(n1657) );
AOI222X4TS U1685 ( .A0(n1693), .A1(d_ff2_Z[39]), .B0(n1692), .B1(d_ff1_Z[39]), .C0(d_ff_Zn[39]), .C1(n2014), .Y(n1656) );
AOI222X4TS U1686 ( .A0(n1687), .A1(d_ff2_Z[36]), .B0(n1669), .B1(d_ff1_Z[36]), .C0(d_ff_Zn[36]), .C1(n2014), .Y(n1654) );
AOI222X4TS U1687 ( .A0(n1670), .A1(d_ff2_Z[34]), .B0(n1669), .B1(d_ff1_Z[34]), .C0(d_ff_Zn[34]), .C1(n2014), .Y(n1653) );
AOI222X4TS U1688 ( .A0(n1693), .A1(d_ff2_Z[35]), .B0(n1669), .B1(d_ff1_Z[35]), .C0(d_ff_Zn[35]), .C1(n2014), .Y(n1652) );
AOI222X4TS U1689 ( .A0(n1687), .A1(d_ff2_Z[32]), .B0(n1686), .B1(d_ff1_Z[32]), .C0(d_ff_Zn[32]), .C1(n2014), .Y(n1651) );
AOI222X4TS U1690 ( .A0(n2026), .A1(d_ff2_Z[26]), .B0(n1686), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n2014), .Y(n1650) );
AOI222X4TS U1691 ( .A0(n2030), .A1(d_ff2_Z[20]), .B0(n1686), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n2014), .Y(n1649) );
AOI222X4TS U1692 ( .A0(n1696), .A1(d_ff2_Z[18]), .B0(n1686), .B1(d_ff1_Z[18]), .C0(d_ff_Zn[18]), .C1(n2014), .Y(n1648) );
AOI222X4TS U1693 ( .A0(n1670), .A1(d_ff2_Z[14]), .B0(n1686), .B1(d_ff1_Z[14]), .C0(d_ff_Zn[14]), .C1(n2014), .Y(n1647) );
AOI222X4TS U1694 ( .A0(n1693), .A1(d_ff2_Z[19]), .B0(n1686), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n2014), .Y(n1646) );
AOI222X4TS U1695 ( .A0(n1670), .A1(d_ff2_Z[29]), .B0(n1686), .B1(d_ff1_Z[29]), .C0(d_ff_Zn[29]), .C1(n2014), .Y(n1645) );
AOI222X4TS U1696 ( .A0(n1687), .A1(d_ff2_Z[16]), .B0(n1686), .B1(d_ff1_Z[16]), .C0(d_ff_Zn[16]), .C1(n2014), .Y(n1644) );
AOI222X4TS U1697 ( .A0(n2056), .A1(d_ff2_Z[0]), .B0(n2017), .B1(d_ff_Zn[0]),
.C0(n1669), .C1(d_ff1_Z[0]), .Y(n1625) );
AOI222X4TS U1698 ( .A0(n2056), .A1(d_ff2_Z[54]), .B0(n1695), .B1(d_ff1_Z[54]), .C0(d_ff_Zn[54]), .C1(n2017), .Y(n1655) );
AOI222X4TS U1699 ( .A0(n2056), .A1(d_ff2_Z[2]), .B0(n1669), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n2017), .Y(n1643) );
AOI222X4TS U1700 ( .A0(n1670), .A1(d_ff2_Z[23]), .B0(n1686), .B1(d_ff1_Z[23]), .C0(d_ff_Zn[23]), .C1(n2017), .Y(n1642) );
AOI222X4TS U1701 ( .A0(n1693), .A1(d_ff2_Z[6]), .B0(n1669), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n2017), .Y(n1641) );
AOI222X4TS U1702 ( .A0(n1687), .A1(d_ff2_Z[5]), .B0(n1669), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n2017), .Y(n1640) );
AOI222X4TS U1703 ( .A0(n1696), .A1(d_ff2_Z[17]), .B0(n1686), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n2017), .Y(n1639) );
AOI222X4TS U1704 ( .A0(n1670), .A1(d_ff2_Z[8]), .B0(n1669), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n2017), .Y(n1638) );
AOI222X4TS U1705 ( .A0(n1693), .A1(d_ff2_Z[4]), .B0(n1669), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n2017), .Y(n1637) );
AOI222X4TS U1706 ( .A0(n1687), .A1(d_ff2_Z[3]), .B0(n1669), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n2017), .Y(n1636) );
AOI222X4TS U1707 ( .A0(n1670), .A1(d_ff2_Z[9]), .B0(n1669), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n2017), .Y(n1635) );
AOI222X4TS U1708 ( .A0(n2026), .A1(d_ff2_Z[22]), .B0(n1686), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n2017), .Y(n1634) );
AOI222X4TS U1709 ( .A0(n1696), .A1(d_ff2_Z[10]), .B0(n1669), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n2017), .Y(n1633) );
AOI222X4TS U1710 ( .A0(n2030), .A1(d_ff2_Z[15]), .B0(n1686), .B1(d_ff1_Z[15]), .C0(d_ff_Zn[15]), .C1(n2017), .Y(n1632) );
AOI222X4TS U1711 ( .A0(n1693), .A1(d_ff2_Z[37]), .B0(n1669), .B1(d_ff1_Z[37]), .C0(d_ff_Zn[37]), .C1(n2017), .Y(n1631) );
AOI222X4TS U1712 ( .A0(n2026), .A1(d_ff2_Z[7]), .B0(n1669), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n2017), .Y(n1630) );
AOI222X4TS U1713 ( .A0(n2030), .A1(d_ff2_Z[11]), .B0(n1669), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n2017), .Y(n1629) );
AOI222X4TS U1714 ( .A0(n1693), .A1(d_ff2_Z[12]), .B0(n1686), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n2017), .Y(n1628) );
AOI222X4TS U1715 ( .A0(n1687), .A1(d_ff2_Z[13]), .B0(n1686), .B1(d_ff1_Z[13]), .C0(d_ff_Zn[13]), .C1(n2017), .Y(n1627) );
OAI33X1TS U1716 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_operation_out), .A2(n2073), .B0(n2068), .B1(n2066), .B2(
d_ff1_shift_region_flag_out[0]), .Y(n1498) );
OAI21X2TS U1717 ( .A0(cont_iter_out[1]), .A1(n1967), .B0(n1969), .Y(n1926)
);
NOR2X2TS U1718 ( .A(n2129), .B(cont_iter_out[1]), .Y(n1615) );
NAND2X2TS U1719 ( .A(cont_iter_out[1]), .B(n2070), .Y(n1913) );
NOR4X2TS U1720 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[0]),
.C(n2067), .D(n2069), .Y(n1517) );
NOR2X4TS U1721 ( .A(cordic_FSM_state_reg[2]), .B(n2069), .Y(n1860) );
INVX6TS U1722 ( .A(n1711), .Y(n1807) );
NOR2X2TS U1723 ( .A(cont_iter_out[3]), .B(n1913), .Y(n1981) );
NOR2X2TS U1724 ( .A(cont_iter_out[3]), .B(n2070), .Y(n1942) );
NOR3X2TS U1725 ( .A(cont_iter_out[3]), .B(cont_iter_out[2]), .C(
cont_iter_out[1]), .Y(n1928) );
BUFX4TS U1726 ( .A(n1476), .Y(n1891) );
BUFX4TS U1727 ( .A(n1580), .Y(n1590) );
BUFX6TS U1728 ( .A(n1580), .Y(n1575) );
BUFX4TS U1729 ( .A(n1580), .Y(n1586) );
NOR2X2TS U1730 ( .A(n1616), .B(n2021), .Y(n1972) );
CLKINVX6TS U1731 ( .A(n2021), .Y(n2039) );
BUFX4TS U1732 ( .A(n1478), .Y(n2021) );
CLKINVX3TS U1733 ( .A(n2023), .Y(n1985) );
CLKINVX6TS U1734 ( .A(n2023), .Y(n2018) );
INVX4TS U1735 ( .A(n1622), .Y(n1870) );
INVX4TS U1736 ( .A(n1622), .Y(n1868) );
INVX4TS U1737 ( .A(n1622), .Y(n1871) );
INVX6TS U1738 ( .A(n1725), .Y(n1824) );
AOI222X1TS U1739 ( .A0(d_ff3_LUT_out[32]), .A1(n1808), .B0(n1848), .B1(
d_ff3_sh_x_out[32]), .C0(n1823), .C1(d_ff3_sh_y_out[32]), .Y(n1811) );
AOI222X1TS U1740 ( .A0(d_ff3_LUT_out[31]), .A1(n1828), .B0(n1845), .B1(
d_ff3_sh_x_out[31]), .C0(n1812), .C1(d_ff3_sh_y_out[31]), .Y(n1813) );
AOI222X1TS U1741 ( .A0(d_ff3_LUT_out[30]), .A1(n1799), .B0(n1848), .B1(
d_ff3_sh_x_out[30]), .C0(n1847), .C1(d_ff3_sh_y_out[30]), .Y(n1814) );
INVX3TS U1742 ( .A(n1487), .Y(n1902) );
INVX6TS U1743 ( .A(n1984), .Y(n2059) );
CLKINVX6TS U1744 ( .A(n1479), .Y(n2052) );
INVX6TS U1745 ( .A(n1479), .Y(n2019) );
AOI222X1TS U1746 ( .A0(d_ff3_LUT_out[4]), .A1(n1808), .B0(n1845), .B1(
d_ff3_sh_x_out[4]), .C0(n1812), .C1(d_ff3_sh_y_out[4]), .Y(n1774) );
AOI222X1TS U1747 ( .A0(d_ff3_LUT_out[2]), .A1(n1825), .B0(n1848), .B1(
d_ff3_sh_x_out[2]), .C0(n1843), .C1(d_ff3_sh_y_out[2]), .Y(n1776) );
INVX6TS U1748 ( .A(n2021), .Y(n2055) );
NOR3X2TS U1749 ( .A(n1954), .B(n2184), .C(n1835), .Y(n1832) );
OAI211X4TS U1750 ( .A0(n1920), .A1(n1619), .B0(n1618), .C0(n1617), .Y(n934)
);
NOR2X2TS U1751 ( .A(d_ff2_Y[57]), .B(n1998), .Y(n2000) );
AOI222X4TS U1752 ( .A0(n1693), .A1(d_ff2_Z[56]), .B0(n1695), .B1(d_ff1_Z[56]), .C0(d_ff_Zn[56]), .C1(n2014), .Y(n1658) );
AOI222X4TS U1753 ( .A0(n1696), .A1(d_ff2_Z[58]), .B0(n1695), .B1(d_ff1_Z[58]), .C0(d_ff_Zn[58]), .C1(n2013), .Y(n1689) );
AOI222X4TS U1754 ( .A0(n1670), .A1(d_ff2_Z[60]), .B0(n1695), .B1(d_ff1_Z[60]), .C0(d_ff_Zn[60]), .C1(n2013), .Y(n1680) );
AOI222X4TS U1755 ( .A0(n1687), .A1(d_ff2_Z[62]), .B0(n1695), .B1(d_ff1_Z[62]), .C0(d_ff_Zn[62]), .C1(n2057), .Y(n1677) );
AOI32X1TS U1756 ( .A0(n1475), .A1(n1952), .A2(n1605), .B0(d_ff3_sh_y_out[55]), .B1(n1478), .Y(n1604) );
AOI32X4TS U1757 ( .A0(n2129), .A1(n1952), .A2(n1597), .B0(d_ff3_LUT_out[54]),
.B1(n1478), .Y(n1598) );
AOI222X1TS U1758 ( .A0(d_ff3_LUT_out[3]), .A1(n1808), .B0(n1845), .B1(
d_ff3_sh_x_out[3]), .C0(n1843), .C1(d_ff3_sh_y_out[3]), .Y(n1775) );
OAI32X4TS U1759 ( .A0(n2021), .A1(n1931), .A2(n1930), .B0(d_ff3_LUT_out[15]),
.B1(n1952), .Y(n1932) );
AOI222X4TS U1760 ( .A0(n2030), .A1(d_ff2_Z[33]), .B0(n1692), .B1(d_ff1_Z[33]), .C0(d_ff_Zn[33]), .C1(n2014), .Y(n1659) );
AOI222X4TS U1761 ( .A0(n2026), .A1(d_ff2_Z[47]), .B0(n1692), .B1(d_ff1_Z[47]), .C0(d_ff_Zn[47]), .C1(n2057), .Y(n1674) );
AOI222X4TS U1762 ( .A0(n1696), .A1(d_ff2_Z[50]), .B0(n1692), .B1(d_ff1_Z[50]), .C0(d_ff_Zn[50]), .C1(n2057), .Y(n1676) );
AOI222X4TS U1763 ( .A0(n2030), .A1(d_ff2_Z[51]), .B0(n1695), .B1(d_ff1_Z[51]), .C0(d_ff_Zn[51]), .C1(n2013), .Y(n1681) );
NOR4X4TS U1764 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[1]),
.C(n2182), .D(n2187), .Y(ack_add_subt) );
NOR2X2TS U1765 ( .A(d_ff2_X[52]), .B(n1485), .Y(n2031) );
OAI32X4TS U1766 ( .A0(n1478), .A1(n1865), .A2(n1930), .B0(d_ff3_LUT_out[26]),
.B1(n1952), .Y(n1505) );
NOR2X2TS U1767 ( .A(n1623), .B(n1967), .Y(n1865) );
NOR3X6TS U1768 ( .A(n1475), .B(n2070), .C(n1623), .Y(n1954) );
NAND2X2TS U1769 ( .A(n2129), .B(cont_iter_out[1]), .Y(n1623) );
AOI222X1TS U1770 ( .A0(n2026), .A1(d_ff2_Z[63]), .B0(n1695), .B1(d_ff1_Z[63]), .C0(d_ff_Zn[63]), .C1(n2013), .Y(n1691) );
OAI21X2TS U1771 ( .A0(cont_iter_out[3]), .A1(n1920), .B0(n2041), .Y(n1973)
);
BUFX3TS U1772 ( .A(n1891), .Y(n1892) );
BUFX4TS U1773 ( .A(n1476), .Y(n1889) );
CLKINVX6TS U1774 ( .A(n1496), .Y(n2156) );
NOR2X2TS U1775 ( .A(d_ff2_X[57]), .B(n2038), .Y(n2042) );
NOR2X2TS U1776 ( .A(d_ff2_X[59]), .B(n2045), .Y(n2048) );
NOR2X2TS U1777 ( .A(n2129), .B(n1480), .Y(n1611) );
INVX4TS U1778 ( .A(n1876), .Y(n1882) );
INVX4TS U1779 ( .A(n1486), .Y(n1908) );
INVX3TS U1780 ( .A(n1487), .Y(n1901) );
INVX4TS U1781 ( .A(n1869), .Y(n1874) );
INVX4TS U1782 ( .A(n2025), .Y(n2030) );
BUFX6TS U1783 ( .A(n1847), .Y(n1812) );
BUFX4TS U1784 ( .A(n1847), .Y(n1843) );
BUFX6TS U1785 ( .A(n1491), .Y(n1847) );
BUFX6TS U1786 ( .A(n1519), .Y(n1548) );
AOI222X1TS U1787 ( .A0(d_ff3_LUT_out[21]), .A1(n1799), .B0(n1824), .B1(
d_ff3_sh_x_out[21]), .C0(n1812), .C1(d_ff3_sh_y_out[21]), .Y(n1753) );
AOI222X1TS U1788 ( .A0(d_ff3_LUT_out[22]), .A1(n1799), .B0(n1848), .B1(
d_ff3_sh_x_out[22]), .C0(n1847), .C1(d_ff3_sh_y_out[22]), .Y(n1754) );
AOI222X1TS U1789 ( .A0(d_ff3_LUT_out[18]), .A1(n1828), .B0(n1848), .B1(
d_ff3_sh_x_out[18]), .C0(n1812), .C1(d_ff3_sh_y_out[18]), .Y(n1755) );
AOI222X1TS U1790 ( .A0(d_ff3_LUT_out[17]), .A1(n1838), .B0(n1848), .B1(
d_ff3_sh_x_out[17]), .C0(n1812), .C1(d_ff3_sh_y_out[17]), .Y(n1756) );
AOI222X1TS U1791 ( .A0(d_ff3_LUT_out[16]), .A1(n1808), .B0(n1845), .B1(
d_ff3_sh_x_out[16]), .C0(n1812), .C1(d_ff3_sh_y_out[16]), .Y(n1757) );
BUFX6TS U1792 ( .A(n1712), .Y(n1799) );
OAI21XLTS U1793 ( .A0(n2048), .A1(n2204), .B0(n2050), .Y(n2049) );
OAI21XLTS U1794 ( .A0(n1484), .A1(n2201), .B0(n2005), .Y(n2004) );
OAI32X1TS U1795 ( .A0(cordic_FSM_state_reg[2]), .A1(beg_fsm_cordic), .A2(
n1858), .B0(n1857), .B1(n2067), .Y(n1863) );
OAI21XLTS U1796 ( .A0(n2190), .A1(n1593), .B0(n1549), .Y(n963) );
OAI21XLTS U1797 ( .A0(n2101), .A1(n1588), .B0(n1574), .Y(n1019) );
OAI21XLTS U1798 ( .A0(n2072), .A1(n1698), .B0(n1492), .Y(add_subt_dataB[19])
);
OAI21XLTS U1799 ( .A0(n2186), .A1(n1698), .B0(n1495), .Y(add_subt_dataB[41])
);
OAI21XLTS U1800 ( .A0(n2061), .A1(n1711), .B0(n1716), .Y(add_subt_dataA[52])
);
NOR2X2TS U1801 ( .A(cordic_FSM_state_reg[0]), .B(cordic_FSM_state_reg[1]),
.Y(n1506) );
AOI211XLTS U1802 ( .A0(n1954), .A1(n2067), .B0(n1506), .C0(n1860), .Y(n1490)
);
INVX2TS U1803 ( .A(beg_add_subt), .Y(n1489) );
NAND4BXLTS U1804 ( .AN(ack_cordic), .B(cordic_FSM_state_reg[3]), .C(
cordic_FSM_state_reg[2]), .D(n2069), .Y(n1862) );
OAI211XLTS U1805 ( .A0(n1490), .A1(n2187), .B0(n1489), .C0(n1862), .Y(n1345)
);
NAND2X1TS U1806 ( .A(n2183), .B(sel_mux_2_reg[1]), .Y(n1698) );
AOI22X1TS U1807 ( .A0(n1845), .A1(d_ff3_sh_x_out[19]), .B0(n1847), .B1(
d_ff3_sh_y_out[19]), .Y(n1492) );
INVX2TS U1808 ( .A(n1954), .Y(n1982) );
XNOR2X1TS U1809 ( .A(d_ff1_shift_region_flag_out[1]), .B(d_ff1_operation_out), .Y(n1493) );
CLKXOR2X2TS U1810 ( .A(d_ff1_shift_region_flag_out[0]), .B(n1493), .Y(n1513)
);
AO22XLTS U1811 ( .A0(n1982), .A1(n2184), .B0(n1954), .B1(n1513), .Y(n1886)
);
INVX2TS U1812 ( .A(n1517), .Y(n1518) );
AOI22X1TS U1813 ( .A0(n1845), .A1(d_ff3_sh_x_out[8]), .B0(n1847), .B1(
d_ff3_sh_y_out[8]), .Y(n1494) );
OAI21XLTS U1814 ( .A0(n2185), .A1(n1698), .B0(n1494), .Y(add_subt_dataB[8])
);
AOI22X1TS U1815 ( .A0(n1848), .A1(d_ff3_sh_x_out[41]), .B0(n1847), .B1(
d_ff3_sh_y_out[41]), .Y(n1495) );
INVX4TS U1816 ( .A(n1488), .Y(n2171) );
INVX4TS U1817 ( .A(n1477), .Y(n2180) );
INVX4TS U1818 ( .A(n1477), .Y(n2179) );
INVX4TS U1819 ( .A(n1477), .Y(n2132) );
INVX4TS U1820 ( .A(n1477), .Y(n2170) );
INVX4TS U1821 ( .A(n1496), .Y(n2169) );
INVX4TS U1822 ( .A(n1496), .Y(n2168) );
INVX4TS U1823 ( .A(n1496), .Y(n2134) );
INVX4TS U1824 ( .A(n1477), .Y(n2167) );
INVX4TS U1825 ( .A(n1477), .Y(n2158) );
INVX4TS U1826 ( .A(n1477), .Y(n2161) );
INVX4TS U1827 ( .A(n1496), .Y(n2162) );
INVX4TS U1828 ( .A(n1477), .Y(n2163) );
INVX4TS U1829 ( .A(n1496), .Y(n2166) );
INVX4TS U1830 ( .A(n1477), .Y(n2175) );
INVX4TS U1831 ( .A(n1488), .Y(n2174) );
INVX4TS U1832 ( .A(n1477), .Y(n2173) );
INVX4TS U1833 ( .A(n1488), .Y(n2177) );
INVX4TS U1834 ( .A(n1477), .Y(n2178) );
INVX4TS U1835 ( .A(n1477), .Y(n2149) );
INVX4TS U1836 ( .A(n1496), .Y(n2154) );
INVX4TS U1837 ( .A(n1496), .Y(n2135) );
INVX4TS U1838 ( .A(n1496), .Y(n2159) );
INVX4TS U1839 ( .A(n1496), .Y(n2148) );
INVX4TS U1840 ( .A(n1496), .Y(n2150) );
INVX4TS U1841 ( .A(n1496), .Y(n2137) );
INVX4TS U1842 ( .A(n1477), .Y(n2155) );
INVX4TS U1843 ( .A(n1477), .Y(n2160) );
INVX4TS U1844 ( .A(n1477), .Y(n2136) );
INVX4TS U1845 ( .A(n1477), .Y(n2152) );
INVX4TS U1846 ( .A(n1488), .Y(n2151) );
INVX4TS U1847 ( .A(n1496), .Y(n2133) );
INVX4TS U1848 ( .A(n1477), .Y(n2153) );
INVX4TS U1849 ( .A(n1488), .Y(n2138) );
INVX4TS U1850 ( .A(n1496), .Y(n2146) );
INVX4TS U1851 ( .A(n1477), .Y(n2165) );
INVX4TS U1852 ( .A(n1496), .Y(n2141) );
INVX4TS U1853 ( .A(n1496), .Y(n2140) );
INVX4TS U1854 ( .A(n1477), .Y(n2145) );
INVX4TS U1855 ( .A(n1477), .Y(n2164) );
INVX4TS U1856 ( .A(n1496), .Y(n2139) );
INVX4TS U1857 ( .A(n1496), .Y(n2143) );
INVX4TS U1858 ( .A(n1496), .Y(n2144) );
INVX4TS U1859 ( .A(n1488), .Y(n2147) );
INVX4TS U1860 ( .A(n1477), .Y(n2130) );
INVX4TS U1861 ( .A(n1488), .Y(n2142) );
INVX4TS U1862 ( .A(n1488), .Y(n2131) );
INVX2TS U1863 ( .A(n1506), .Y(n1857) );
XOR2XLTS U1864 ( .A(data_output2_63_), .B(n1498), .Y(n1499) );
AO22XLTS U1865 ( .A0(n1908), .A1(n1499), .B0(n1486), .B1(data_output[63]),
.Y(n946) );
INVX4TS U1866 ( .A(n1486), .Y(n1904) );
BUFX3TS U1867 ( .A(n1486), .Y(n1909) );
AO22XLTS U1868 ( .A0(n1903), .A1(sign_inv_out[30]), .B0(n1909), .B1(
data_output[30]), .Y(n1012) );
INVX4TS U1869 ( .A(n1486), .Y(n1903) );
AO22XLTS U1870 ( .A0(n1903), .A1(sign_inv_out[31]), .B0(n1909), .B1(
data_output[31]), .Y(n1010) );
AO22XLTS U1871 ( .A0(n1904), .A1(sign_inv_out[32]), .B0(n1909), .B1(
data_output[32]), .Y(n1008) );
AO22XLTS U1872 ( .A0(n1903), .A1(sign_inv_out[35]), .B0(n1486), .B1(
data_output[35]), .Y(n1002) );
AO22XLTS U1873 ( .A0(n1904), .A1(sign_inv_out[27]), .B0(n1909), .B1(
data_output[27]), .Y(n1018) );
AO22XLTS U1874 ( .A0(n1908), .A1(sign_inv_out[33]), .B0(n1909), .B1(
data_output[33]), .Y(n1006) );
AO22XLTS U1875 ( .A0(n1903), .A1(sign_inv_out[25]), .B0(n1909), .B1(
data_output[25]), .Y(n1022) );
AO22XLTS U1876 ( .A0(n1908), .A1(sign_inv_out[34]), .B0(n1909), .B1(
data_output[34]), .Y(n1004) );
AO22XLTS U1877 ( .A0(n1903), .A1(sign_inv_out[26]), .B0(n1909), .B1(
data_output[26]), .Y(n1020) );
AO22XLTS U1878 ( .A0(n1904), .A1(sign_inv_out[28]), .B0(n1909), .B1(
data_output[28]), .Y(n1016) );
AO22XLTS U1879 ( .A0(n1908), .A1(sign_inv_out[24]), .B0(n1909), .B1(
data_output[24]), .Y(n1024) );
AO22XLTS U1880 ( .A0(n1904), .A1(sign_inv_out[29]), .B0(n1909), .B1(
data_output[29]), .Y(n1014) );
BUFX3TS U1881 ( .A(n1486), .Y(n1907) );
AO22XLTS U1882 ( .A0(n1903), .A1(sign_inv_out[13]), .B0(n1907), .B1(
data_output[13]), .Y(n1046) );
AO22XLTS U1883 ( .A0(n1904), .A1(sign_inv_out[14]), .B0(n1909), .B1(
data_output[14]), .Y(n1044) );
AO22XLTS U1884 ( .A0(n1908), .A1(sign_inv_out[16]), .B0(n1907), .B1(
data_output[16]), .Y(n1040) );
BUFX4TS U1885 ( .A(n1500), .Y(n2027) );
BUFX4TS U1886 ( .A(n2011), .Y(n2022) );
OA22X1TS U1887 ( .A0(n2027), .A1(d_ff2_X[45]), .B0(d_ff_Xn[45]), .B1(n2022),
.Y(n606) );
OA22X1TS U1888 ( .A0(n2027), .A1(d_ff2_X[39]), .B0(d_ff_Xn[39]), .B1(n2022),
.Y(n618) );
OA22X1TS U1889 ( .A0(n2027), .A1(d_ff2_X[54]), .B0(d_ff_Xn[54]), .B1(n2022),
.Y(n590) );
OA22X1TS U1890 ( .A0(n2027), .A1(d_ff2_X[48]), .B0(d_ff_Xn[48]), .B1(n2022),
.Y(n600) );
OA22X1TS U1891 ( .A0(n2027), .A1(d_ff2_X[43]), .B0(d_ff_Xn[43]), .B1(n2022),
.Y(n610) );
OA22X1TS U1892 ( .A0(n2027), .A1(d_ff2_X[41]), .B0(d_ff_Xn[41]), .B1(n2022),
.Y(n614) );
AOI22X1TS U1893 ( .A0(cont_iter_out[1]), .A1(n2071), .B0(d_ff2_X[53]), .B1(
n1480), .Y(n1501) );
XNOR2X1TS U1894 ( .A(n2031), .B(n1501), .Y(n1502) );
AO22XLTS U1895 ( .A0(n2019), .A1(n1502), .B0(n2021), .B1(d_ff3_sh_x_out[53]),
.Y(n580) );
OA22X1TS U1896 ( .A0(n2027), .A1(d_ff2_X[46]), .B0(d_ff_Xn[46]), .B1(n2022),
.Y(n604) );
NAND2X1TS U1897 ( .A(d_ff2_X[53]), .B(n1480), .Y(n1503) );
AOI22X1TS U1898 ( .A0(cont_iter_out[1]), .A1(n2071), .B0(n2031), .B1(n1503),
.Y(n1594) );
BUFX3TS U1899 ( .A(n1478), .Y(n2043) );
AO22XLTS U1900 ( .A0(n2047), .A1(n1504), .B0(n2043), .B1(d_ff3_sh_x_out[54]),
.Y(n579) );
INVX2TS U1901 ( .A(n1942), .Y(n1967) );
NAND3X1TS U1902 ( .A(n1942), .B(n1485), .C(n1480), .Y(n1602) );
INVX2TS U1903 ( .A(n1602), .Y(n1930) );
NAND2X1TS U1904 ( .A(n1505), .B(n1940), .Y(n919) );
NAND2X1TS U1905 ( .A(n2129), .B(n1981), .Y(n1969) );
NAND2X1TS U1906 ( .A(n2055), .B(n1926), .Y(n1949) );
NAND2X2TS U1907 ( .A(n1981), .B(n1485), .Y(n1974) );
INVX2TS U1908 ( .A(n1974), .Y(n1938) );
NAND2X1TS U1909 ( .A(cont_iter_out[3]), .B(n2070), .Y(n1600) );
INVX4TS U1910 ( .A(n1478), .Y(n2041) );
OAI211XLTS U1911 ( .A0(n1952), .A1(n2072), .B0(n1949), .C0(n1911), .Y(n926)
);
BUFX3TS U1912 ( .A(n2010), .Y(n2028) );
OA22X1TS U1913 ( .A0(n2027), .A1(d_ff2_X[34]), .B0(d_ff_Xn[34]), .B1(n2028),
.Y(n628) );
OA22X1TS U1914 ( .A0(n2027), .A1(d_ff2_X[35]), .B0(d_ff_Xn[35]), .B1(n2028),
.Y(n626) );
OA22X1TS U1915 ( .A0(n2027), .A1(d_ff2_X[42]), .B0(d_ff_Xn[42]), .B1(n2028),
.Y(n612) );
NAND2X1TS U1916 ( .A(cont_var_out[1]), .B(n2184), .Y(n1853) );
NOR2X1TS U1917 ( .A(n1954), .B(n1853), .Y(n1620) );
NAND4X1TS U1918 ( .A(cordic_FSM_state_reg[3]), .B(n1506), .C(ready_add_subt),
.D(n2067), .Y(n1885) );
NOR2BX1TS U1919 ( .AN(n1620), .B(n1885), .Y(n1507) );
INVX4TS U1920 ( .A(n1876), .Y(n1877) );
BUFX3TS U1921 ( .A(n1876), .Y(n1883) );
AO22XLTS U1922 ( .A0(n1877), .A1(result_add_subt[35]), .B0(n1883), .B1(
d_ff_Zn[35]), .Y(n1230) );
INVX4TS U1923 ( .A(n1876), .Y(n1878) );
BUFX3TS U1924 ( .A(n1876), .Y(n1881) );
AO22XLTS U1925 ( .A0(n1878), .A1(result_add_subt[32]), .B0(n1881), .B1(
d_ff_Zn[32]), .Y(n1233) );
AO22XLTS U1926 ( .A0(n1878), .A1(result_add_subt[34]), .B0(n1881), .B1(
d_ff_Zn[34]), .Y(n1231) );
AO22XLTS U1927 ( .A0(n1878), .A1(result_add_subt[30]), .B0(n1881), .B1(
d_ff_Zn[30]), .Y(n1235) );
AO22XLTS U1928 ( .A0(n1878), .A1(result_add_subt[15]), .B0(n1881), .B1(
d_ff_Zn[15]), .Y(n1250) );
AO22XLTS U1929 ( .A0(n1878), .A1(result_add_subt[14]), .B0(n1876), .B1(
d_ff_Zn[14]), .Y(n1251) );
AO22XLTS U1930 ( .A0(n1877), .A1(result_add_subt[31]), .B0(n1881), .B1(
d_ff_Zn[31]), .Y(n1234) );
AO22XLTS U1931 ( .A0(n1877), .A1(result_add_subt[27]), .B0(n1881), .B1(
d_ff_Zn[27]), .Y(n1238) );
AO22XLTS U1932 ( .A0(n1877), .A1(result_add_subt[29]), .B0(n1881), .B1(
d_ff_Zn[29]), .Y(n1236) );
AO22XLTS U1933 ( .A0(n1878), .A1(result_add_subt[28]), .B0(n1881), .B1(
d_ff_Zn[28]), .Y(n1237) );
AO22XLTS U1934 ( .A0(n1878), .A1(result_add_subt[26]), .B0(n1881), .B1(
d_ff_Zn[26]), .Y(n1239) );
AO22XLTS U1935 ( .A0(n1877), .A1(result_add_subt[25]), .B0(n1881), .B1(
d_ff_Zn[25]), .Y(n1240) );
AO22XLTS U1936 ( .A0(n1878), .A1(result_add_subt[24]), .B0(n1881), .B1(
d_ff_Zn[24]), .Y(n1241) );
AO22XLTS U1937 ( .A0(n1878), .A1(result_add_subt[17]), .B0(n1876), .B1(
d_ff_Zn[17]), .Y(n1248) );
AO22XLTS U1938 ( .A0(n1877), .A1(result_add_subt[33]), .B0(n1881), .B1(
d_ff_Zn[33]), .Y(n1232) );
AOI32X1TS U1939 ( .A0(n2184), .A1(n1982), .A2(n1483), .B0(n1513), .B1(n1954),
.Y(n1508) );
INVX4TS U1940 ( .A(n1487), .Y(n1895) );
BUFX4TS U1941 ( .A(n1487), .Y(n1898) );
INVX4TS U1942 ( .A(n1487), .Y(n1896) );
INVX4TS U1943 ( .A(n1488), .Y(n2172) );
INVX4TS U1944 ( .A(n1488), .Y(n2176) );
INVX2TS U1945 ( .A(rst), .Y(n564) );
NAND3X1TS U1946 ( .A(cordic_FSM_state_reg[0]), .B(cordic_FSM_state_reg[3]),
.C(n1860), .Y(n1509) );
BUFX4TS U1947 ( .A(n1523), .Y(n1593) );
BUFX4TS U1948 ( .A(n1509), .Y(n1580) );
AOI22X1TS U1949 ( .A0(d_ff_Xn[56]), .A1(n1519), .B0(sign_inv_out[56]), .B1(
n1586), .Y(n1510) );
OAI21XLTS U1950 ( .A0(n2191), .A1(n1593), .B0(n1510), .Y(n961) );
NAND3XLTS U1951 ( .A(cordic_FSM_state_reg[3]), .B(n1860), .C(n2182), .Y(
n1512) );
NAND3XLTS U1952 ( .A(n1512), .B(sel_mux_3_reg), .C(n2181), .Y(n1511) );
OAI21XLTS U1953 ( .A0(n1513), .A1(n1512), .B0(n1511), .Y(n1269) );
NAND2X1TS U1954 ( .A(n1928), .B(n1485), .Y(n1925) );
INVX2TS U1955 ( .A(n1925), .Y(n1977) );
NAND3XLTS U1956 ( .A(cordic_FSM_state_reg[0]), .B(n1860), .C(n2187), .Y(
n1515) );
NAND3XLTS U1957 ( .A(n1515), .B(sel_mux_1_reg), .C(n2181), .Y(n1514) );
OAI21XLTS U1958 ( .A0(n1977), .A1(n1515), .B0(n1514), .Y(n1268) );
NAND2X1TS U1959 ( .A(sel_mux_2_reg[1]), .B(n2181), .Y(n1516) );
BUFX4TS U1960 ( .A(n1523), .Y(n1582) );
AOI22X1TS U1961 ( .A0(d_ff_Xn[1]), .A1(n1519), .B0(sign_inv_out[1]), .B1(
n1590), .Y(n1520) );
OAI21XLTS U1962 ( .A0(n2075), .A1(n1582), .B0(n1520), .Y(n1071) );
AOI22X1TS U1963 ( .A0(d_ff_Xn[60]), .A1(n1519), .B0(sign_inv_out[60]), .B1(
n1575), .Y(n1521) );
OAI21XLTS U1964 ( .A0(n2195), .A1(n1582), .B0(n1521), .Y(n953) );
AOI22X1TS U1965 ( .A0(d_ff_Xn[58]), .A1(n1519), .B0(sign_inv_out[58]), .B1(
n1586), .Y(n1522) );
OAI21XLTS U1966 ( .A0(n2193), .A1(n1593), .B0(n1522), .Y(n957) );
AOI22X1TS U1967 ( .A0(d_ff_Xn[19]), .A1(n1548), .B0(sign_inv_out[19]), .B1(
n1590), .Y(n1524) );
OAI21XLTS U1968 ( .A0(n2093), .A1(n1523), .B0(n1524), .Y(n1035) );
BUFX3TS U1969 ( .A(n1582), .Y(n1588) );
AOI22X1TS U1970 ( .A0(d_ff_Xn[25]), .A1(n1548), .B0(sign_inv_out[25]), .B1(
n1586), .Y(n1525) );
OAI21XLTS U1971 ( .A0(n2099), .A1(n1588), .B0(n1525), .Y(n1023) );
AOI22X1TS U1972 ( .A0(d_ff_Xn[18]), .A1(n1548), .B0(sign_inv_out[18]), .B1(
n1580), .Y(n1526) );
OAI21XLTS U1973 ( .A0(n2092), .A1(n1593), .B0(n1526), .Y(n1037) );
AOI22X1TS U1974 ( .A0(d_ff_Xn[21]), .A1(n1548), .B0(sign_inv_out[21]), .B1(
n1575), .Y(n1527) );
OAI21XLTS U1975 ( .A0(n2095), .A1(n1523), .B0(n1527), .Y(n1031) );
AOI22X1TS U1976 ( .A0(d_ff_Xn[17]), .A1(n1548), .B0(sign_inv_out[17]), .B1(
n1580), .Y(n1528) );
OAI21XLTS U1977 ( .A0(n2091), .A1(n1523), .B0(n1528), .Y(n1039) );
AOI22X1TS U1978 ( .A0(d_ff_Xn[14]), .A1(n1548), .B0(sign_inv_out[14]), .B1(
n1580), .Y(n1529) );
OAI21XLTS U1979 ( .A0(n2088), .A1(n1593), .B0(n1529), .Y(n1045) );
AOI22X1TS U1980 ( .A0(d_ff_Xn[22]), .A1(n1548), .B0(sign_inv_out[22]), .B1(
n1586), .Y(n1530) );
OAI21XLTS U1981 ( .A0(n2096), .A1(n1593), .B0(n1530), .Y(n1029) );
AOI22X1TS U1982 ( .A0(d_ff_Xn[16]), .A1(n1548), .B0(sign_inv_out[16]), .B1(
n1580), .Y(n1531) );
OAI21XLTS U1983 ( .A0(n2090), .A1(n1593), .B0(n1531), .Y(n1041) );
AOI22X1TS U1984 ( .A0(d_ff_Xn[15]), .A1(n1548), .B0(sign_inv_out[15]), .B1(
n1580), .Y(n1532) );
OAI21XLTS U1985 ( .A0(n2089), .A1(n1523), .B0(n1532), .Y(n1043) );
AOI22X1TS U1986 ( .A0(d_ff_Xn[23]), .A1(n1548), .B0(sign_inv_out[23]), .B1(
n1575), .Y(n1533) );
OAI21XLTS U1987 ( .A0(n2097), .A1(n1523), .B0(n1533), .Y(n1027) );
AOI22X1TS U1988 ( .A0(d_ff_Xn[20]), .A1(n1548), .B0(sign_inv_out[20]), .B1(
n1575), .Y(n1534) );
OAI21XLTS U1989 ( .A0(n2094), .A1(n1593), .B0(n1534), .Y(n1033) );
AOI22X1TS U1990 ( .A0(d_ff_Xn[7]), .A1(n1548), .B0(sign_inv_out[7]), .B1(
n1580), .Y(n1535) );
OAI21XLTS U1991 ( .A0(n2081), .A1(n1582), .B0(n1535), .Y(n1059) );
AOI22X1TS U1992 ( .A0(d_ff_Xn[12]), .A1(n1548), .B0(sign_inv_out[12]), .B1(
n1580), .Y(n1536) );
OAI21XLTS U1993 ( .A0(n2086), .A1(n1582), .B0(n1536), .Y(n1049) );
AOI22X1TS U1994 ( .A0(d_ff_Xn[13]), .A1(n1548), .B0(sign_inv_out[13]), .B1(
n1580), .Y(n1537) );
OAI21XLTS U1995 ( .A0(n2087), .A1(n1588), .B0(n1537), .Y(n1047) );
AOI22X1TS U1996 ( .A0(d_ff_Xn[8]), .A1(n1548), .B0(sign_inv_out[8]), .B1(
n1580), .Y(n1538) );
OAI21XLTS U1997 ( .A0(n2082), .A1(n1582), .B0(n1538), .Y(n1057) );
AOI22X1TS U1998 ( .A0(d_ff_Xn[6]), .A1(n1548), .B0(sign_inv_out[6]), .B1(
n1580), .Y(n1539) );
OAI21XLTS U1999 ( .A0(n2080), .A1(n1582), .B0(n1539), .Y(n1061) );
AOI22X1TS U2000 ( .A0(d_ff_Xn[24]), .A1(n1548), .B0(sign_inv_out[24]), .B1(
n1586), .Y(n1540) );
OAI21XLTS U2001 ( .A0(n2098), .A1(n1588), .B0(n1540), .Y(n1025) );
AOI22X1TS U2002 ( .A0(d_ff_Xn[0]), .A1(n1548), .B0(sign_inv_out[0]), .B1(
n1575), .Y(n1541) );
OAI21XLTS U2003 ( .A0(n2074), .A1(n1582), .B0(n1541), .Y(n1073) );
AOI22X1TS U2004 ( .A0(d_ff_Xn[3]), .A1(n1548), .B0(sign_inv_out[3]), .B1(
n1590), .Y(n1542) );
OAI21XLTS U2005 ( .A0(n2077), .A1(n1582), .B0(n1542), .Y(n1067) );
AOI22X1TS U2006 ( .A0(d_ff_Xn[9]), .A1(n1548), .B0(sign_inv_out[9]), .B1(
n1580), .Y(n1543) );
OAI21XLTS U2007 ( .A0(n2083), .A1(n1582), .B0(n1543), .Y(n1055) );
AOI22X1TS U2008 ( .A0(d_ff_Xn[11]), .A1(n1548), .B0(sign_inv_out[11]), .B1(
n1580), .Y(n1544) );
OAI21XLTS U2009 ( .A0(n2085), .A1(n1582), .B0(n1544), .Y(n1051) );
AOI22X1TS U2010 ( .A0(d_ff_Xn[63]), .A1(n1548), .B0(data_output2_63_), .B1(
n1586), .Y(n1545) );
OAI21XLTS U2011 ( .A0(n2127), .A1(n1582), .B0(n1545), .Y(n947) );
AOI22X1TS U2012 ( .A0(d_ff_Xn[62]), .A1(n1548), .B0(sign_inv_out[62]), .B1(
n1575), .Y(n1546) );
OAI21XLTS U2013 ( .A0(n2197), .A1(n1582), .B0(n1546), .Y(n949) );
AOI22X1TS U2014 ( .A0(d_ff_Xn[57]), .A1(n1548), .B0(sign_inv_out[57]), .B1(
n1590), .Y(n1547) );
OAI21XLTS U2015 ( .A0(n2192), .A1(n1593), .B0(n1547), .Y(n959) );
AOI22X1TS U2016 ( .A0(d_ff_Xn[55]), .A1(n1548), .B0(sign_inv_out[55]), .B1(
n1590), .Y(n1549) );
BUFX4TS U2017 ( .A(n1519), .Y(n1566) );
AOI22X1TS U2018 ( .A0(d_ff_Xn[39]), .A1(n1566), .B0(sign_inv_out[39]), .B1(
n1590), .Y(n1550) );
OAI21XLTS U2019 ( .A0(n2113), .A1(n1523), .B0(n1550), .Y(n995) );
AOI22X1TS U2020 ( .A0(d_ff_Xn[40]), .A1(n1566), .B0(sign_inv_out[40]), .B1(
n1586), .Y(n1551) );
OAI21XLTS U2021 ( .A0(n2114), .A1(n1523), .B0(n1551), .Y(n993) );
AOI22X1TS U2022 ( .A0(d_ff_Xn[51]), .A1(n1566), .B0(sign_inv_out[51]), .B1(
n1575), .Y(n1552) );
OAI21XLTS U2023 ( .A0(n2125), .A1(n1593), .B0(n1552), .Y(n971) );
AOI22X1TS U2024 ( .A0(d_ff_Xn[44]), .A1(n1566), .B0(sign_inv_out[44]), .B1(
n1586), .Y(n1553) );
OAI21XLTS U2025 ( .A0(n2118), .A1(n1523), .B0(n1553), .Y(n985) );
AOI22X1TS U2026 ( .A0(d_ff_Xn[42]), .A1(n1566), .B0(sign_inv_out[42]), .B1(
n1575), .Y(n1554) );
OAI21XLTS U2027 ( .A0(n2116), .A1(n1523), .B0(n1554), .Y(n989) );
AOI22X1TS U2028 ( .A0(d_ff_Xn[46]), .A1(n1566), .B0(sign_inv_out[46]), .B1(
n1586), .Y(n1555) );
OAI21XLTS U2029 ( .A0(n2120), .A1(n1523), .B0(n1555), .Y(n981) );
AOI22X1TS U2030 ( .A0(d_ff_Xn[50]), .A1(n1566), .B0(sign_inv_out[50]), .B1(
n1575), .Y(n1556) );
OAI21XLTS U2031 ( .A0(n2124), .A1(n1593), .B0(n1556), .Y(n973) );
AOI22X1TS U2032 ( .A0(d_ff_Xn[47]), .A1(n1566), .B0(sign_inv_out[47]), .B1(
n1586), .Y(n1557) );
OAI21XLTS U2033 ( .A0(n2121), .A1(n1523), .B0(n1557), .Y(n979) );
AOI22X1TS U2034 ( .A0(d_ff_Xn[4]), .A1(n1566), .B0(sign_inv_out[4]), .B1(
n1580), .Y(n1558) );
OAI21XLTS U2035 ( .A0(n2078), .A1(n1582), .B0(n1558), .Y(n1065) );
AOI22X1TS U2036 ( .A0(d_ff_Xn[43]), .A1(n1566), .B0(sign_inv_out[43]), .B1(
n1575), .Y(n1559) );
OAI21XLTS U2037 ( .A0(n2117), .A1(n1523), .B0(n1559), .Y(n987) );
AOI22X1TS U2038 ( .A0(d_ff_Xn[41]), .A1(n1566), .B0(sign_inv_out[41]), .B1(
n1575), .Y(n1560) );
OAI21XLTS U2039 ( .A0(n2115), .A1(n1523), .B0(n1560), .Y(n991) );
AOI22X1TS U2040 ( .A0(d_ff_Xn[49]), .A1(n1566), .B0(sign_inv_out[49]), .B1(
n1586), .Y(n1561) );
OAI21XLTS U2041 ( .A0(n2123), .A1(n1593), .B0(n1561), .Y(n975) );
AOI22X1TS U2042 ( .A0(d_ff_Xn[48]), .A1(n1566), .B0(sign_inv_out[48]), .B1(
n1575), .Y(n1562) );
OAI21XLTS U2043 ( .A0(n2122), .A1(n1593), .B0(n1562), .Y(n977) );
AOI22X1TS U2044 ( .A0(d_ff_Xn[54]), .A1(n1566), .B0(sign_inv_out[54]), .B1(
n1590), .Y(n1563) );
OAI21XLTS U2045 ( .A0(n2126), .A1(n1593), .B0(n1563), .Y(n965) );
AOI22X1TS U2046 ( .A0(d_ff_Xn[45]), .A1(n1566), .B0(sign_inv_out[45]), .B1(
n1575), .Y(n1564) );
OAI21XLTS U2047 ( .A0(n2119), .A1(n1523), .B0(n1564), .Y(n983) );
AOI22X1TS U2048 ( .A0(d_ff_Xn[53]), .A1(n1566), .B0(sign_inv_out[53]), .B1(
n1590), .Y(n1565) );
OAI21XLTS U2049 ( .A0(n2189), .A1(n1593), .B0(n1565), .Y(n967) );
AOI22X1TS U2050 ( .A0(d_ff_Xn[61]), .A1(n1566), .B0(sign_inv_out[61]), .B1(
n1590), .Y(n1567) );
OAI21XLTS U2051 ( .A0(n2196), .A1(n1582), .B0(n1567), .Y(n951) );
BUFX4TS U2052 ( .A(n1519), .Y(n1591) );
AOI22X1TS U2053 ( .A0(d_ff_Xn[26]), .A1(n1591), .B0(sign_inv_out[26]), .B1(
n1590), .Y(n1568) );
OAI21XLTS U2054 ( .A0(n2100), .A1(n1588), .B0(n1568), .Y(n1021) );
AOI22X1TS U2055 ( .A0(d_ff_Xn[29]), .A1(n1591), .B0(sign_inv_out[29]), .B1(
n1575), .Y(n1569) );
OAI21XLTS U2056 ( .A0(n2103), .A1(n1588), .B0(n1569), .Y(n1015) );
AOI22X1TS U2057 ( .A0(d_ff_Xn[32]), .A1(n1591), .B0(sign_inv_out[32]), .B1(
n1586), .Y(n1570) );
OAI21XLTS U2058 ( .A0(n2106), .A1(n1588), .B0(n1570), .Y(n1009) );
AOI22X1TS U2059 ( .A0(d_ff_Xn[36]), .A1(n1591), .B0(sign_inv_out[36]), .B1(
n1575), .Y(n1571) );
OAI21XLTS U2060 ( .A0(n2110), .A1(n1523), .B0(n1571), .Y(n1001) );
AOI22X1TS U2061 ( .A0(d_ff_Xn[30]), .A1(n1591), .B0(sign_inv_out[30]), .B1(
n1586), .Y(n1572) );
OAI21XLTS U2062 ( .A0(n2104), .A1(n1588), .B0(n1572), .Y(n1013) );
AOI22X1TS U2063 ( .A0(d_ff_Xn[10]), .A1(n1591), .B0(sign_inv_out[10]), .B1(
n1580), .Y(n1573) );
OAI21XLTS U2064 ( .A0(n2084), .A1(n1582), .B0(n1573), .Y(n1053) );
AOI22X1TS U2065 ( .A0(d_ff_Xn[27]), .A1(n1591), .B0(sign_inv_out[27]), .B1(
n1575), .Y(n1574) );
AOI22X1TS U2066 ( .A0(d_ff_Xn[2]), .A1(n1591), .B0(sign_inv_out[2]), .B1(
n1575), .Y(n1576) );
OAI21XLTS U2067 ( .A0(n2076), .A1(n1582), .B0(n1576), .Y(n1069) );
AOI22X1TS U2068 ( .A0(d_ff_Xn[38]), .A1(n1591), .B0(sign_inv_out[38]), .B1(
n1586), .Y(n1577) );
OAI21XLTS U2069 ( .A0(n2112), .A1(n1523), .B0(n1577), .Y(n997) );
AOI22X1TS U2070 ( .A0(d_ff_Xn[37]), .A1(n1591), .B0(sign_inv_out[37]), .B1(
n1575), .Y(n1578) );
OAI21XLTS U2071 ( .A0(n2111), .A1(n1523), .B0(n1578), .Y(n999) );
AOI22X1TS U2072 ( .A0(d_ff_Xn[28]), .A1(n1591), .B0(sign_inv_out[28]), .B1(
n1590), .Y(n1579) );
OAI21XLTS U2073 ( .A0(n2102), .A1(n1588), .B0(n1579), .Y(n1017) );
AOI22X1TS U2074 ( .A0(d_ff_Xn[5]), .A1(n1591), .B0(sign_inv_out[5]), .B1(
n1580), .Y(n1581) );
OAI21XLTS U2075 ( .A0(n2079), .A1(n1582), .B0(n1581), .Y(n1063) );
AOI22X1TS U2076 ( .A0(d_ff_Xn[33]), .A1(n1591), .B0(sign_inv_out[33]), .B1(
n1575), .Y(n1583) );
OAI21XLTS U2077 ( .A0(n2107), .A1(n1588), .B0(n1583), .Y(n1007) );
AOI22X1TS U2078 ( .A0(d_ff_Xn[35]), .A1(n1591), .B0(sign_inv_out[35]), .B1(
n1575), .Y(n1584) );
OAI21XLTS U2079 ( .A0(n2109), .A1(n1588), .B0(n1584), .Y(n1003) );
AOI22X1TS U2080 ( .A0(d_ff_Xn[34]), .A1(n1591), .B0(sign_inv_out[34]), .B1(
n1590), .Y(n1585) );
OAI21XLTS U2081 ( .A0(n2108), .A1(n1588), .B0(n1585), .Y(n1005) );
AOI22X1TS U2082 ( .A0(d_ff_Xn[31]), .A1(n1591), .B0(sign_inv_out[31]), .B1(
n1590), .Y(n1587) );
OAI21XLTS U2083 ( .A0(n2105), .A1(n1588), .B0(n1587), .Y(n1011) );
AOI22X1TS U2084 ( .A0(d_ff_Xn[59]), .A1(n1591), .B0(sign_inv_out[59]), .B1(
n1590), .Y(n1589) );
OAI21XLTS U2085 ( .A0(n2194), .A1(n1593), .B0(n1589), .Y(n955) );
AOI22X1TS U2086 ( .A0(d_ff_Xn[52]), .A1(n1591), .B0(sign_inv_out[52]), .B1(
n1575), .Y(n1592) );
OAI21XLTS U2087 ( .A0(n2188), .A1(n1593), .B0(n1592), .Y(n969) );
NAND2X2TS U2088 ( .A(n2129), .B(n1480), .Y(n1965) );
INVX2TS U2089 ( .A(n1965), .Y(n1951) );
OAI32X1TS U2090 ( .A0(n2021), .A1(n1951), .A2(n1611), .B0(n1952), .B1(n2128),
.Y(n893) );
CLKAND2X2TS U2091 ( .A(n2035), .B(d_ff2_X[55]), .Y(n2034) );
AOI2BB1X1TS U2092 ( .A0N(n2035), .A1N(d_ff2_X[55]), .B0(n2034), .Y(n1596) );
NOR2X2TS U2093 ( .A(n1478), .B(n1475), .Y(n1915) );
AOI22X1TS U2094 ( .A0(n1596), .A1(n1915), .B0(d_ff3_sh_x_out[55]), .B1(n1478), .Y(n1595) );
OAI31X1TS U2095 ( .A0(cont_iter_out[3]), .A1(n1596), .A2(n1478), .B0(n1595),
.Y(n578) );
NAND2X1TS U2096 ( .A(n2070), .B(n1623), .Y(n1924) );
NOR2XLTS U2097 ( .A(n2070), .B(n1480), .Y(n1597) );
OAI21XLTS U2098 ( .A0(n1478), .A1(n1924), .B0(n1598), .Y(n892) );
NAND2X2TS U2099 ( .A(cont_iter_out[2]), .B(n1915), .Y(n1961) );
NAND2X1TS U2100 ( .A(n2041), .B(n1927), .Y(n1934) );
NAND2X1TS U2101 ( .A(n1969), .B(n1602), .Y(n1937) );
NOR2X1TS U2102 ( .A(n1478), .B(n1937), .Y(n1919) );
OAI31X1TS U2103 ( .A0(cont_iter_out[3]), .A1(cont_iter_out[2]), .A2(n1965),
.B0(n1919), .Y(n1917) );
OAI21XLTS U2104 ( .A0(n1952), .A1(d_ff3_LUT_out[1]), .B0(n1917), .Y(n1599)
);
OAI211XLTS U2105 ( .A0(n1961), .A1(n1965), .B0(n1934), .C0(n1599), .Y(n944)
);
OAI21XLTS U2106 ( .A0(n1952), .A1(d_ff3_LUT_out[7]), .B0(n1935), .Y(n1601)
);
OAI211XLTS U2107 ( .A0(n1602), .A1(n1478), .B0(n1911), .C0(n1601), .Y(n938)
);
INVX2TS U2108 ( .A(n1915), .Y(n1619) );
NAND2X1TS U2109 ( .A(d_ff2_Y[53]), .B(n1480), .Y(n1603) );
AOI22X1TS U2110 ( .A0(cont_iter_out[1]), .A1(n2198), .B0(n1990), .B1(n1603),
.Y(n1992) );
OR2X1TS U2111 ( .A(n1995), .B(d_ff2_Y[55]), .Y(n1994) );
OAI2BB1X1TS U2112 ( .A0N(d_ff2_Y[55]), .A1N(n1995), .B0(n1994), .Y(n1605) );
OAI21XLTS U2113 ( .A0(n1619), .A1(n1605), .B0(n1604), .Y(n706) );
INVX2TS U2114 ( .A(n1615), .Y(n1608) );
INVX2TS U2115 ( .A(n1611), .Y(n1609) );
NOR2XLTS U2116 ( .A(cont_iter_out[3]), .B(n1609), .Y(n1606) );
OAI22X1TS U2117 ( .A0(n1952), .A1(d_ff3_LUT_out[3]), .B0(n1606), .B1(n1935),
.Y(n1607) );
OAI211XLTS U2118 ( .A0(n1608), .A1(n1961), .B0(n1617), .C0(n1607), .Y(n942)
);
NAND3XLTS U2119 ( .A(cont_iter_out[2]), .B(n2041), .C(n1480), .Y(n1959) );
OAI21XLTS U2120 ( .A0(n1952), .A1(d_ff3_LUT_out[14]), .B0(n1947), .Y(n1610)
);
OAI211XLTS U2121 ( .A0(n1619), .A1(n1480), .B0(n1959), .C0(n1610), .Y(n931)
);
NAND2X1TS U2122 ( .A(n1951), .B(n2070), .Y(n1920) );
NOR2XLTS U2123 ( .A(n2052), .B(d_ff3_LUT_out[55]), .Y(n1612) );
AOI31XLTS U2124 ( .A0(n1939), .A1(n1982), .A2(n1925), .B0(n1612), .Y(n891)
);
INVX2TS U2125 ( .A(n1961), .Y(n1950) );
AOI21X1TS U2126 ( .A0(d_ff3_LUT_out[33]), .A1(n2021), .B0(n1950), .Y(n1613)
);
OAI211XLTS U2127 ( .A0(n1619), .A1(n1913), .B0(n1613), .C0(n1617), .Y(n912)
);
INVX2TS U2128 ( .A(ack_add_subt), .Y(n1835) );
AOI31XLTS U2129 ( .A0(ack_add_subt), .A1(n1982), .A2(n1483), .B0(
cont_var_out[0]), .Y(n1614) );
NOR3XLTS U2130 ( .A(n1952), .B(n1832), .C(n1614), .Y(n1337) );
AOI31XLTS U2131 ( .A0(cont_iter_out[3]), .A1(n1615), .A2(n2070), .B0(n1865),
.Y(n1616) );
NOR3X1TS U2132 ( .A(n2129), .B(n1913), .C(n1619), .Y(n1923) );
AOI211XLTS U2133 ( .A0(d_ff3_LUT_out[11]), .A1(n1478), .B0(n1972), .C0(n1923), .Y(n1618) );
NAND2X2TS U2134 ( .A(ack_add_subt), .B(n1620), .Y(n1866) );
BUFX4TS U2135 ( .A(n1622), .Y(n1869) );
BUFX3TS U2136 ( .A(n1869), .Y(n1867) );
OAI211XLTS U2137 ( .A0(n1485), .A1(n1866), .B0(cont_iter_out[1]), .C0(n1872),
.Y(n1621) );
OAI21XLTS U2138 ( .A0(n1866), .A1(n1965), .B0(n1621), .Y(n1340) );
OAI211XLTS U2139 ( .A0(n1623), .A1(n1866), .B0(cont_iter_out[2]), .C0(n1622),
.Y(n1624) );
OAI31X1TS U2140 ( .A0(n1866), .A1(n1485), .A2(n1913), .B0(n1624), .Y(n1339)
);
BUFX4TS U2141 ( .A(n2027), .Y(n2023) );
BUFX3TS U2142 ( .A(n2023), .Y(n2025) );
CLKINVX6TS U2143 ( .A(n2010), .Y(n2017) );
NOR2X1TS U2144 ( .A(sel_mux_1_reg), .B(n2056), .Y(n1626) );
BUFX4TS U2145 ( .A(n1626), .Y(n1669) );
INVX2TS U2146 ( .A(n1625), .Y(n889) );
INVX4TS U2147 ( .A(n2025), .Y(n1670) );
BUFX4TS U2148 ( .A(n1626), .Y(n1686) );
INVX2TS U2149 ( .A(n1627), .Y(n876) );
INVX2TS U2150 ( .A(n1628), .Y(n877) );
INVX2TS U2151 ( .A(n1629), .Y(n878) );
INVX2TS U2152 ( .A(n1630), .Y(n882) );
INVX4TS U2153 ( .A(n2025), .Y(n1693) );
INVX2TS U2154 ( .A(n1631), .Y(n852) );
INVX4TS U2155 ( .A(n2025), .Y(n1687) );
INVX2TS U2156 ( .A(n1632), .Y(n874) );
INVX2TS U2157 ( .A(n1633), .Y(n879) );
INVX2TS U2158 ( .A(n1634), .Y(n867) );
INVX2TS U2159 ( .A(n1635), .Y(n880) );
INVX2TS U2160 ( .A(n1636), .Y(n886) );
INVX2TS U2161 ( .A(n1637), .Y(n885) );
INVX2TS U2162 ( .A(n1638), .Y(n881) );
INVX2TS U2163 ( .A(n1639), .Y(n872) );
INVX2TS U2164 ( .A(n1640), .Y(n884) );
INVX2TS U2165 ( .A(n1641), .Y(n883) );
INVX2TS U2166 ( .A(n1642), .Y(n866) );
INVX2TS U2167 ( .A(n1643), .Y(n887) );
CLKINVX6TS U2168 ( .A(n2010), .Y(n2014) );
INVX2TS U2169 ( .A(n1644), .Y(n873) );
INVX2TS U2170 ( .A(n1645), .Y(n860) );
INVX2TS U2171 ( .A(n1646), .Y(n870) );
INVX2TS U2172 ( .A(n1647), .Y(n875) );
INVX2TS U2173 ( .A(n1648), .Y(n871) );
INVX2TS U2174 ( .A(n1649), .Y(n869) );
INVX2TS U2175 ( .A(n1650), .Y(n863) );
INVX2TS U2176 ( .A(n1651), .Y(n857) );
INVX2TS U2177 ( .A(n1652), .Y(n854) );
INVX2TS U2178 ( .A(n1653), .Y(n855) );
INVX2TS U2179 ( .A(n1654), .Y(n853) );
INVX4TS U2180 ( .A(n2025), .Y(n2026) );
BUFX4TS U2181 ( .A(n1669), .Y(n1695) );
INVX2TS U2182 ( .A(n1655), .Y(n835) );
BUFX4TS U2183 ( .A(n1669), .Y(n1692) );
INVX2TS U2184 ( .A(n1656), .Y(n850) );
INVX2TS U2185 ( .A(n1657), .Y(n861) );
INVX2TS U2186 ( .A(n1658), .Y(n833) );
INVX2TS U2187 ( .A(n1659), .Y(n856) );
INVX2TS U2188 ( .A(n1660), .Y(n858) );
INVX2TS U2189 ( .A(n1661), .Y(n862) );
INVX2TS U2190 ( .A(n1662), .Y(n864) );
INVX2TS U2191 ( .A(n1663), .Y(n851) );
INVX2TS U2192 ( .A(n1664), .Y(n859) );
INVX4TS U2193 ( .A(n2025), .Y(n1696) );
CLKINVX6TS U2194 ( .A(n2010), .Y(n2057) );
INVX2TS U2195 ( .A(n1665), .Y(n843) );
INVX2TS U2196 ( .A(n1666), .Y(n848) );
INVX2TS U2197 ( .A(n1667), .Y(n841) );
INVX2TS U2198 ( .A(n1668), .Y(n846) );
INVX2TS U2199 ( .A(n1671), .Y(n888) );
AOI222X1TS U2200 ( .A0(n1670), .A1(d_ff2_Z[49]), .B0(n1692), .B1(d_ff1_Z[49]), .C0(d_ff_Zn[49]), .C1(n2057), .Y(n1672) );
INVX2TS U2201 ( .A(n1672), .Y(n840) );
INVX2TS U2202 ( .A(n1673), .Y(n844) );
INVX2TS U2203 ( .A(n1674), .Y(n842) );
INVX2TS U2204 ( .A(n1675), .Y(n837) );
INVX2TS U2205 ( .A(n1676), .Y(n839) );
INVX2TS U2206 ( .A(n1677), .Y(n827) );
INVX2TS U2207 ( .A(n1678), .Y(n828) );
CLKINVX6TS U2208 ( .A(n2010), .Y(n2013) );
INVX2TS U2209 ( .A(n1679), .Y(n865) );
INVX2TS U2210 ( .A(n1680), .Y(n829) );
INVX2TS U2211 ( .A(n1681), .Y(n838) );
INVX2TS U2212 ( .A(n1682), .Y(n834) );
INVX2TS U2213 ( .A(n1683), .Y(n847) );
INVX2TS U2214 ( .A(n1684), .Y(n832) );
INVX2TS U2215 ( .A(n1685), .Y(n845) );
INVX2TS U2216 ( .A(n1688), .Y(n868) );
INVX2TS U2217 ( .A(n1689), .Y(n831) );
INVX2TS U2218 ( .A(n1690), .Y(n830) );
INVX2TS U2219 ( .A(n1691), .Y(n826) );
INVX2TS U2220 ( .A(n1694), .Y(n849) );
INVX2TS U2221 ( .A(n1697), .Y(n836) );
INVX2TS U2222 ( .A(n1699), .Y(add_subt_dataA[22]) );
INVX2TS U2223 ( .A(n1700), .Y(add_subt_dataA[3]) );
INVX2TS U2224 ( .A(n1701), .Y(add_subt_dataA[1]) );
INVX2TS U2225 ( .A(n1702), .Y(add_subt_dataA[9]) );
INVX4TS U2226 ( .A(n1711), .Y(n1837) );
BUFX3TS U2227 ( .A(n1812), .Y(n1785) );
INVX2TS U2228 ( .A(n1703), .Y(add_subt_dataA[27]) );
INVX2TS U2229 ( .A(n1704), .Y(add_subt_dataA[23]) );
AOI22X1TS U2230 ( .A0(d_ff2_Z[53]), .A1(n1825), .B0(d_ff2_X[53]), .B1(n1847),
.Y(n1705) );
OAI21XLTS U2231 ( .A0(n2198), .A1(n1711), .B0(n1705), .Y(add_subt_dataA[53])
);
BUFX4TS U2232 ( .A(n1843), .Y(n1798) );
INVX2TS U2233 ( .A(n1706), .Y(add_subt_dataA[19]) );
BUFX4TS U2234 ( .A(n1843), .Y(n1806) );
INVX2TS U2235 ( .A(n1707), .Y(add_subt_dataA[14]) );
INVX2TS U2236 ( .A(n1708), .Y(add_subt_dataA[16]) );
BUFX4TS U2237 ( .A(n1843), .Y(n1823) );
INVX2TS U2238 ( .A(n1709), .Y(add_subt_dataA[18]) );
INVX2TS U2239 ( .A(n1710), .Y(add_subt_dataA[17]) );
INVX2TS U2240 ( .A(n1713), .Y(add_subt_dataA[42]) );
INVX2TS U2241 ( .A(n1714), .Y(add_subt_dataA[15]) );
INVX2TS U2242 ( .A(n1715), .Y(add_subt_dataA[21]) );
BUFX4TS U2243 ( .A(n1712), .Y(n1825) );
AOI22X1TS U2244 ( .A0(n1808), .A1(d_ff2_Z[52]), .B0(d_ff2_X[52]), .B1(n1847),
.Y(n1716) );
AOI22X1TS U2245 ( .A0(d_ff2_X[60]), .A1(n1843), .B0(d_ff2_Z[60]), .B1(n1799),
.Y(n1717) );
OAI21XLTS U2246 ( .A0(n2201), .A1(n1725), .B0(n1717), .Y(add_subt_dataA[60])
);
AOI22X1TS U2247 ( .A0(d_ff2_X[58]), .A1(n1843), .B0(d_ff2_Z[58]), .B1(n1825),
.Y(n1718) );
OAI21XLTS U2248 ( .A0(n2200), .A1(n1725), .B0(n1718), .Y(add_subt_dataA[58])
);
AOI22X1TS U2249 ( .A0(d_ff2_X[56]), .A1(n1843), .B0(d_ff2_Z[56]), .B1(n1825),
.Y(n1719) );
OAI21XLTS U2250 ( .A0(n2199), .A1(n1725), .B0(n1719), .Y(add_subt_dataA[56])
);
AOI22X1TS U2251 ( .A0(d_ff2_X[62]), .A1(n1843), .B0(d_ff2_Z[62]), .B1(n1799),
.Y(n1720) );
OAI21XLTS U2252 ( .A0(n2065), .A1(n1725), .B0(n1720), .Y(add_subt_dataA[62])
);
AOI22X1TS U2253 ( .A0(d_ff2_X[61]), .A1(n1843), .B0(d_ff2_Z[61]), .B1(n1799),
.Y(n1721) );
OAI21XLTS U2254 ( .A0(n2064), .A1(n1725), .B0(n1721), .Y(add_subt_dataA[61])
);
AOI22X1TS U2255 ( .A0(d_ff2_X[59]), .A1(n1843), .B0(d_ff2_Z[59]), .B1(n1838),
.Y(n1722) );
OAI21XLTS U2256 ( .A0(n2063), .A1(n1725), .B0(n1722), .Y(add_subt_dataA[59])
);
AOI22X1TS U2257 ( .A0(d_ff2_X[57]), .A1(n1843), .B0(d_ff2_Z[57]), .B1(n1799),
.Y(n1723) );
OAI21XLTS U2258 ( .A0(n2062), .A1(n1725), .B0(n1723), .Y(add_subt_dataA[57])
);
AOI22X1TS U2259 ( .A0(d_ff2_X[55]), .A1(n1847), .B0(d_ff2_Z[55]), .B1(n1799),
.Y(n1724) );
OAI21XLTS U2260 ( .A0(n2060), .A1(n1711), .B0(n1724), .Y(add_subt_dataA[55])
);
AOI222X1TS U2261 ( .A0(n1828), .A1(d_ff3_LUT_out[44]), .B0(n1824), .B1(
d_ff3_sh_x_out[44]), .C0(n1806), .C1(d_ff3_sh_y_out[44]), .Y(n1726) );
INVX2TS U2262 ( .A(n1726), .Y(add_subt_dataB[44]) );
AOI222X1TS U2263 ( .A0(n1828), .A1(d_ff3_LUT_out[20]), .B0(n1824), .B1(
d_ff3_sh_x_out[20]), .C0(n1812), .C1(d_ff3_sh_y_out[20]), .Y(n1727) );
INVX2TS U2264 ( .A(n1727), .Y(add_subt_dataB[20]) );
AOI222X1TS U2265 ( .A0(n1828), .A1(d_ff3_LUT_out[37]), .B0(n1824), .B1(
d_ff3_sh_x_out[37]), .C0(n1823), .C1(d_ff3_sh_y_out[37]), .Y(n1728) );
INVX2TS U2266 ( .A(n1728), .Y(add_subt_dataB[37]) );
INVX2TS U2267 ( .A(n1729), .Y(add_subt_dataB[54]) );
INVX2TS U2268 ( .A(n1730), .Y(add_subt_dataB[45]) );
INVX2TS U2269 ( .A(n1731), .Y(add_subt_dataB[50]) );
AOI222X1TS U2270 ( .A0(d_ff3_LUT_out[43]), .A1(n1828), .B0(n1824), .B1(
d_ff3_sh_x_out[43]), .C0(n1823), .C1(d_ff3_sh_y_out[43]), .Y(n1732) );
INVX2TS U2271 ( .A(n1732), .Y(add_subt_dataB[43]) );
INVX2TS U2272 ( .A(n1733), .Y(add_subt_dataB[55]) );
INVX2TS U2273 ( .A(n1734), .Y(add_subt_dataB[47]) );
AOI222X1TS U2274 ( .A0(d_ff3_LUT_out[40]), .A1(n1825), .B0(n1824), .B1(
d_ff3_sh_x_out[40]), .C0(n1823), .C1(d_ff3_sh_y_out[40]), .Y(n1735) );
INVX2TS U2275 ( .A(n1735), .Y(add_subt_dataB[40]) );
INVX2TS U2276 ( .A(n1736), .Y(add_subt_dataB[39]) );
AOI222X1TS U2277 ( .A0(d_ff3_LUT_out[38]), .A1(n1828), .B0(n1824), .B1(
d_ff3_sh_x_out[38]), .C0(n1823), .C1(d_ff3_sh_y_out[38]), .Y(n1737) );
INVX2TS U2278 ( .A(n1737), .Y(add_subt_dataB[38]) );
AOI222X1TS U2279 ( .A0(d_ff3_LUT_out[36]), .A1(n1838), .B0(n1824), .B1(
d_ff3_sh_x_out[36]), .C0(n1823), .C1(d_ff3_sh_y_out[36]), .Y(n1738) );
INVX2TS U2280 ( .A(n1738), .Y(add_subt_dataB[36]) );
AOI222X1TS U2281 ( .A0(d_ff3_LUT_out[42]), .A1(n1828), .B0(n1824), .B1(
d_ff3_sh_x_out[42]), .C0(n1823), .C1(d_ff3_sh_y_out[42]), .Y(n1739) );
INVX2TS U2282 ( .A(n1739), .Y(add_subt_dataB[42]) );
INVX2TS U2283 ( .A(n1740), .Y(add_subt_dataA[6]) );
INVX2TS U2284 ( .A(n1741), .Y(add_subt_dataA[11]) );
INVX2TS U2285 ( .A(n1742), .Y(add_subt_dataA[5]) );
INVX2TS U2286 ( .A(n1743), .Y(add_subt_dataA[10]) );
INVX2TS U2287 ( .A(n1744), .Y(add_subt_dataA[4]) );
INVX2TS U2288 ( .A(n1745), .Y(add_subt_dataA[8]) );
INVX2TS U2289 ( .A(n1746), .Y(add_subt_dataA[2]) );
INVX2TS U2290 ( .A(n1747), .Y(add_subt_dataA[7]) );
INVX2TS U2291 ( .A(n1748), .Y(add_subt_dataA[12]) );
INVX2TS U2292 ( .A(n1749), .Y(add_subt_dataA[13]) );
INVX2TS U2293 ( .A(n1750), .Y(add_subt_dataB[46]) );
AOI222X1TS U2294 ( .A0(n1838), .A1(d_ff3_LUT_out[52]), .B0(n1829), .B1(
d_ff3_sh_x_out[52]), .C0(n1823), .C1(d_ff3_sh_y_out[52]), .Y(n1751) );
INVX2TS U2295 ( .A(n1751), .Y(add_subt_dataB[52]) );
AOI222X1TS U2296 ( .A0(n1799), .A1(d_ff3_LUT_out[49]), .B0(n1829), .B1(
d_ff3_sh_x_out[49]), .C0(n1806), .C1(d_ff3_sh_y_out[49]), .Y(n1752) );
INVX2TS U2297 ( .A(n1752), .Y(add_subt_dataB[49]) );
INVX2TS U2298 ( .A(n1753), .Y(add_subt_dataB[21]) );
INVX2TS U2299 ( .A(n1754), .Y(add_subt_dataB[22]) );
INVX2TS U2300 ( .A(n1755), .Y(add_subt_dataB[18]) );
INVX2TS U2301 ( .A(n1756), .Y(add_subt_dataB[17]) );
INVX2TS U2302 ( .A(n1757), .Y(add_subt_dataB[16]) );
INVX2TS U2303 ( .A(n1759), .Y(add_subt_dataA[0]) );
INVX2TS U2304 ( .A(n1760), .Y(add_subt_dataB[15]) );
INVX2TS U2305 ( .A(n1761), .Y(add_subt_dataB[14]) );
AOI222X1TS U2306 ( .A0(d_ff3_LUT_out[13]), .A1(n1825), .B0(n1824), .B1(
d_ff3_sh_x_out[13]), .C0(n1812), .C1(d_ff3_sh_y_out[13]), .Y(n1762) );
INVX2TS U2307 ( .A(n1762), .Y(add_subt_dataB[13]) );
AOI222X1TS U2308 ( .A0(d_ff3_LUT_out[12]), .A1(n1838), .B0(n1824), .B1(
d_ff3_sh_x_out[12]), .C0(n1812), .C1(d_ff3_sh_y_out[12]), .Y(n1763) );
INVX2TS U2309 ( .A(n1763), .Y(add_subt_dataB[12]) );
INVX2TS U2310 ( .A(n1764), .Y(add_subt_dataB[11]) );
AOI222X1TS U2311 ( .A0(d_ff3_LUT_out[10]), .A1(n1838), .B0(n1824), .B1(
d_ff3_sh_x_out[10]), .C0(n1812), .C1(d_ff3_sh_y_out[10]), .Y(n1765) );
INVX2TS U2312 ( .A(n1765), .Y(add_subt_dataB[10]) );
INVX2TS U2313 ( .A(n1766), .Y(add_subt_dataA[24]) );
INVX2TS U2314 ( .A(n1767), .Y(add_subt_dataB[9]) );
INVX2TS U2315 ( .A(n1768), .Y(add_subt_dataA[25]) );
INVX2TS U2316 ( .A(n1769), .Y(add_subt_dataB[7]) );
INVX2TS U2317 ( .A(n1770), .Y(add_subt_dataA[26]) );
INVX2TS U2318 ( .A(n1771), .Y(add_subt_dataB[6]) );
INVX2TS U2319 ( .A(n1772), .Y(add_subt_dataB[5]) );
INVX2TS U2320 ( .A(n1773), .Y(add_subt_dataA[28]) );
INVX2TS U2321 ( .A(n1774), .Y(add_subt_dataB[4]) );
INVX2TS U2322 ( .A(n1775), .Y(add_subt_dataB[3]) );
INVX2TS U2323 ( .A(n1776), .Y(add_subt_dataB[2]) );
INVX2TS U2324 ( .A(n1777), .Y(add_subt_dataB[1]) );
INVX2TS U2325 ( .A(n1778), .Y(add_subt_dataB[0]) );
INVX2TS U2326 ( .A(n1779), .Y(add_subt_dataA[29]) );
INVX2TS U2327 ( .A(n1780), .Y(add_subt_dataA[30]) );
INVX2TS U2328 ( .A(n1781), .Y(add_subt_dataA[31]) );
INVX2TS U2329 ( .A(n1782), .Y(add_subt_dataA[32]) );
INVX2TS U2330 ( .A(n1783), .Y(add_subt_dataA[33]) );
INVX2TS U2331 ( .A(n1784), .Y(add_subt_dataA[34]) );
INVX2TS U2332 ( .A(n1786), .Y(add_subt_dataA[35]) );
INVX2TS U2333 ( .A(n1787), .Y(add_subt_dataA[36]) );
INVX2TS U2334 ( .A(n1788), .Y(add_subt_dataA[37]) );
INVX2TS U2335 ( .A(n1789), .Y(add_subt_dataA[38]) );
INVX2TS U2336 ( .A(n1790), .Y(add_subt_dataA[39]) );
INVX2TS U2337 ( .A(n1791), .Y(add_subt_dataA[40]) );
INVX2TS U2338 ( .A(n1792), .Y(add_subt_dataA[41]) );
INVX2TS U2339 ( .A(n1793), .Y(add_subt_dataA[43]) );
INVX2TS U2340 ( .A(n1794), .Y(add_subt_dataA[44]) );
INVX2TS U2341 ( .A(n1795), .Y(add_subt_dataA[45]) );
INVX2TS U2342 ( .A(n1796), .Y(add_subt_dataA[46]) );
INVX2TS U2343 ( .A(n1797), .Y(add_subt_dataA[47]) );
INVX2TS U2344 ( .A(n1800), .Y(add_subt_dataA[48]) );
INVX2TS U2345 ( .A(n1801), .Y(add_subt_dataA[49]) );
INVX2TS U2346 ( .A(n1802), .Y(add_subt_dataA[50]) );
INVX2TS U2347 ( .A(n1803), .Y(add_subt_dataA[51]) );
INVX2TS U2348 ( .A(n1804), .Y(add_subt_dataA[54]) );
INVX2TS U2349 ( .A(n1805), .Y(add_subt_dataA[63]) );
INVX2TS U2350 ( .A(n1809), .Y(add_subt_dataA[20]) );
INVX2TS U2351 ( .A(n1810), .Y(add_subt_dataB[33]) );
INVX2TS U2352 ( .A(n1811), .Y(add_subt_dataB[32]) );
INVX2TS U2353 ( .A(n1813), .Y(add_subt_dataB[31]) );
INVX2TS U2354 ( .A(n1814), .Y(add_subt_dataB[30]) );
INVX2TS U2355 ( .A(n1815), .Y(add_subt_dataB[29]) );
AOI222X1TS U2356 ( .A0(d_ff3_LUT_out[28]), .A1(n1838), .B0(n1824), .B1(
d_ff3_sh_x_out[28]), .C0(n1847), .C1(d_ff3_sh_y_out[28]), .Y(n1816) );
INVX2TS U2357 ( .A(n1816), .Y(add_subt_dataB[28]) );
INVX2TS U2358 ( .A(n1817), .Y(add_subt_dataB[27]) );
INVX2TS U2359 ( .A(n1818), .Y(add_subt_dataB[26]) );
INVX2TS U2360 ( .A(n1819), .Y(add_subt_dataB[25]) );
AOI222X1TS U2361 ( .A0(d_ff3_LUT_out[24]), .A1(n1799), .B0(n1824), .B1(
d_ff3_sh_x_out[24]), .C0(n1847), .C1(d_ff3_sh_y_out[24]), .Y(n1820) );
INVX2TS U2362 ( .A(n1820), .Y(add_subt_dataB[24]) );
AOI222X1TS U2363 ( .A0(d_ff3_LUT_out[23]), .A1(n1799), .B0(n1824), .B1(
d_ff3_sh_x_out[23]), .C0(n1847), .C1(d_ff3_sh_y_out[23]), .Y(n1821) );
INVX2TS U2364 ( .A(n1821), .Y(add_subt_dataB[23]) );
AOI222X1TS U2365 ( .A0(d_ff3_LUT_out[35]), .A1(n1828), .B0(n1824), .B1(
d_ff3_sh_x_out[35]), .C0(n1823), .C1(d_ff3_sh_y_out[35]), .Y(n1822) );
INVX2TS U2366 ( .A(n1822), .Y(add_subt_dataB[35]) );
AOI222X1TS U2367 ( .A0(d_ff3_LUT_out[34]), .A1(n1828), .B0(n1824), .B1(
d_ff3_sh_x_out[34]), .C0(n1823), .C1(d_ff3_sh_y_out[34]), .Y(n1826) );
INVX2TS U2368 ( .A(n1826), .Y(add_subt_dataB[34]) );
INVX2TS U2369 ( .A(n1827), .Y(add_subt_dataB[53]) );
INVX2TS U2370 ( .A(n1830), .Y(add_subt_dataB[56]) );
INVX2TS U2371 ( .A(n1832), .Y(n1831) );
AOI221XLTS U2372 ( .A0(cont_var_out[1]), .A1(n1832), .B0(n1483), .B1(n1831),
.C0(n1952), .Y(n1342) );
NAND2X1TS U2373 ( .A(n2187), .B(n2069), .Y(n1858) );
INVX2TS U2374 ( .A(n1858), .Y(n1834) );
AOI21X1TS U2375 ( .A0(cordic_FSM_state_reg[3]), .A1(cordic_FSM_state_reg[2]),
.B0(n2069), .Y(n1833) );
NAND3XLTS U2376 ( .A(n1836), .B(n2021), .C(n1835), .Y(
cordic_FSM_state_next_1_) );
AO22XLTS U2377 ( .A0(n1837), .A1(d_ff3_sh_x_out[63]), .B0(n1843), .B1(
d_ff3_sh_y_out[63]), .Y(add_subt_dataB[63]) );
AO22XLTS U2378 ( .A0(d_ff3_sh_y_out[62]), .A1(n1843), .B0(d_ff3_sh_x_out[62]), .B1(n1837), .Y(add_subt_dataB[62]) );
AOI22X1TS U2379 ( .A0(d_ff3_sh_y_out[61]), .A1(n1847), .B0(
d_ff3_sh_x_out[61]), .B1(n1845), .Y(n1839) );
NAND2X2TS U2380 ( .A(d_ff3_LUT_out[48]), .B(n1808), .Y(n1849) );
NAND2X1TS U2381 ( .A(n1839), .B(n1849), .Y(add_subt_dataB[61]) );
AOI22X1TS U2382 ( .A0(d_ff3_sh_y_out[60]), .A1(n1847), .B0(
d_ff3_sh_x_out[60]), .B1(n1845), .Y(n1840) );
NAND2X1TS U2383 ( .A(n1840), .B(n1849), .Y(add_subt_dataB[60]) );
AOI22X1TS U2384 ( .A0(d_ff3_sh_y_out[59]), .A1(n1843), .B0(
d_ff3_sh_x_out[59]), .B1(n1848), .Y(n1841) );
NAND2X1TS U2385 ( .A(n1841), .B(n1849), .Y(add_subt_dataB[59]) );
AOI22X1TS U2386 ( .A0(d_ff3_sh_y_out[58]), .A1(n1843), .B0(
d_ff3_sh_x_out[58]), .B1(n1848), .Y(n1842) );
NAND2X1TS U2387 ( .A(n1842), .B(n1849), .Y(add_subt_dataB[58]) );
AOI22X1TS U2388 ( .A0(d_ff3_sh_y_out[57]), .A1(n1843), .B0(
d_ff3_sh_x_out[57]), .B1(n1848), .Y(n1844) );
NAND2X1TS U2389 ( .A(n1844), .B(n1849), .Y(add_subt_dataB[57]) );
AOI22X1TS U2390 ( .A0(n1848), .A1(d_ff3_sh_x_out[51]), .B0(n1847), .B1(
d_ff3_sh_y_out[51]), .Y(n1846) );
NAND2X1TS U2391 ( .A(n1846), .B(n1849), .Y(add_subt_dataB[51]) );
AOI22X1TS U2392 ( .A0(n1845), .A1(d_ff3_sh_x_out[48]), .B0(n1847), .B1(
d_ff3_sh_y_out[48]), .Y(n1850) );
NAND2X1TS U2393 ( .A(n1850), .B(n1849), .Y(add_subt_dataB[48]) );
AOI2BB2XLTS U2394 ( .B0(d_ff3_sign_out), .B1(n2184), .A0N(n2184), .A1N(
d_ff3_sign_out), .Y(op_add_subt) );
INVX2TS U2395 ( .A(n1860), .Y(n1856) );
NOR2XLTS U2396 ( .A(cordic_FSM_state_reg[0]), .B(cordic_FSM_state_reg[3]),
.Y(n1852) );
AOI31XLTS U2397 ( .A0(cordic_FSM_state_reg[0]), .A1(cordic_FSM_state_reg[3]),
.A2(ack_cordic), .B0(cordic_FSM_state_reg[1]), .Y(n1851) );
OAI21X1TS U2398 ( .A0(n1852), .A1(n1851), .B0(cordic_FSM_state_reg[2]), .Y(
n1855) );
NAND4XLTS U2399 ( .A(cordic_FSM_state_reg[3]), .B(n2067), .C(n1982), .D(
n1853), .Y(n1854) );
AOI32X1TS U2400 ( .A0(n1856), .A1(n1855), .A2(n1854), .B0(n2182), .B1(n1855),
.Y(n1344) );
CLKAND2X2TS U2401 ( .A(ready_add_subt), .B(n2067), .Y(n1859) );
OAI31X1TS U2402 ( .A0(n1860), .A1(n1859), .A2(n2187), .B0(n2182), .Y(n1861)
);
NAND4BXLTS U2403 ( .AN(n1863), .B(n1866), .C(n1862), .D(n1861), .Y(n1343) );
NAND2X1TS U2404 ( .A(n1869), .B(n1866), .Y(n1864) );
AOI22X1TS U2405 ( .A0(n2129), .A1(n1864), .B0(n1866), .B1(n1485), .Y(n1341)
);
INVX2TS U2406 ( .A(n1865), .Y(n1944) );
OAI22X1TS U2407 ( .A0(n1874), .A1(n1475), .B0(n1866), .B1(n1944), .Y(n1338)
);
AO22XLTS U2408 ( .A0(n1622), .A1(d_ff1_operation_out), .B0(n1870), .B1(
operation), .Y(n1336) );
BUFX3TS U2409 ( .A(n1869), .Y(n1873) );
AO22XLTS U2410 ( .A0(n1875), .A1(d_ff1_shift_region_flag_out[0]), .B0(n1870),
.B1(shift_region_flag[0]), .Y(n1335) );
AO22XLTS U2411 ( .A0(n1873), .A1(d_ff1_shift_region_flag_out[1]), .B0(n1870),
.B1(shift_region_flag[1]), .Y(n1334) );
AO22XLTS U2412 ( .A0(n1871), .A1(data_in[0]), .B0(n1873), .B1(d_ff1_Z[0]),
.Y(n1333) );
AO22XLTS U2413 ( .A0(n1871), .A1(data_in[1]), .B0(n1873), .B1(d_ff1_Z[1]),
.Y(n1332) );
AO22XLTS U2414 ( .A0(n1868), .A1(data_in[2]), .B0(n1872), .B1(d_ff1_Z[2]),
.Y(n1331) );
AO22XLTS U2415 ( .A0(n1871), .A1(data_in[3]), .B0(n1867), .B1(d_ff1_Z[3]),
.Y(n1330) );
AO22XLTS U2416 ( .A0(n1868), .A1(data_in[4]), .B0(n1875), .B1(d_ff1_Z[4]),
.Y(n1329) );
AO22XLTS U2417 ( .A0(n1871), .A1(data_in[5]), .B0(n1873), .B1(d_ff1_Z[5]),
.Y(n1328) );
AO22XLTS U2418 ( .A0(n1868), .A1(data_in[6]), .B0(n1872), .B1(d_ff1_Z[6]),
.Y(n1327) );
AO22XLTS U2419 ( .A0(n1871), .A1(data_in[7]), .B0(n1867), .B1(d_ff1_Z[7]),
.Y(n1326) );
AO22XLTS U2420 ( .A0(n1868), .A1(data_in[8]), .B0(n1875), .B1(d_ff1_Z[8]),
.Y(n1325) );
AO22XLTS U2421 ( .A0(n1874), .A1(data_in[9]), .B0(n1873), .B1(d_ff1_Z[9]),
.Y(n1324) );
AO22XLTS U2422 ( .A0(n1871), .A1(data_in[10]), .B0(n1872), .B1(d_ff1_Z[10]),
.Y(n1323) );
AO22XLTS U2423 ( .A0(n1871), .A1(data_in[11]), .B0(n1867), .B1(d_ff1_Z[11]),
.Y(n1322) );
AO22XLTS U2424 ( .A0(n1868), .A1(data_in[12]), .B0(n1869), .B1(d_ff1_Z[12]),
.Y(n1321) );
AO22XLTS U2425 ( .A0(n1868), .A1(data_in[13]), .B0(n1869), .B1(d_ff1_Z[13]),
.Y(n1320) );
AO22XLTS U2426 ( .A0(n1871), .A1(data_in[14]), .B0(n1869), .B1(d_ff1_Z[14]),
.Y(n1319) );
AO22XLTS U2427 ( .A0(n1868), .A1(data_in[15]), .B0(n1869), .B1(d_ff1_Z[15]),
.Y(n1318) );
AO22XLTS U2428 ( .A0(n1871), .A1(data_in[16]), .B0(n1869), .B1(d_ff1_Z[16]),
.Y(n1317) );
AO22XLTS U2429 ( .A0(n1868), .A1(data_in[17]), .B0(n1869), .B1(d_ff1_Z[17]),
.Y(n1316) );
AO22XLTS U2430 ( .A0(n1871), .A1(data_in[18]), .B0(n1869), .B1(d_ff1_Z[18]),
.Y(n1315) );
AO22XLTS U2431 ( .A0(n1868), .A1(data_in[19]), .B0(n1869), .B1(d_ff1_Z[19]),
.Y(n1314) );
AO22XLTS U2432 ( .A0(n1868), .A1(data_in[20]), .B0(n1869), .B1(d_ff1_Z[20]),
.Y(n1313) );
AO22XLTS U2433 ( .A0(n1871), .A1(data_in[21]), .B0(n1869), .B1(d_ff1_Z[21]),
.Y(n1312) );
AO22XLTS U2434 ( .A0(n1868), .A1(data_in[22]), .B0(n1869), .B1(d_ff1_Z[22]),
.Y(n1311) );
BUFX3TS U2435 ( .A(n1869), .Y(n1875) );
AO22XLTS U2436 ( .A0(n1870), .A1(data_in[23]), .B0(n1872), .B1(d_ff1_Z[23]),
.Y(n1310) );
AO22XLTS U2437 ( .A0(n1868), .A1(data_in[24]), .B0(n1867), .B1(d_ff1_Z[24]),
.Y(n1309) );
AO22XLTS U2438 ( .A0(n1870), .A1(data_in[25]), .B0(n1875), .B1(d_ff1_Z[25]),
.Y(n1308) );
AO22XLTS U2439 ( .A0(n1871), .A1(data_in[26]), .B0(n1873), .B1(d_ff1_Z[26]),
.Y(n1307) );
AO22XLTS U2440 ( .A0(n1868), .A1(data_in[27]), .B0(n1872), .B1(d_ff1_Z[27]),
.Y(n1306) );
AO22XLTS U2441 ( .A0(n1870), .A1(data_in[28]), .B0(n1867), .B1(d_ff1_Z[28]),
.Y(n1305) );
AO22XLTS U2442 ( .A0(n1871), .A1(data_in[29]), .B0(n1875), .B1(d_ff1_Z[29]),
.Y(n1304) );
AO22XLTS U2443 ( .A0(n1868), .A1(data_in[30]), .B0(n1873), .B1(d_ff1_Z[30]),
.Y(n1303) );
AO22XLTS U2444 ( .A0(n1870), .A1(data_in[31]), .B0(n1872), .B1(d_ff1_Z[31]),
.Y(n1302) );
AO22XLTS U2445 ( .A0(n1871), .A1(data_in[32]), .B0(n1867), .B1(d_ff1_Z[32]),
.Y(n1301) );
BUFX3TS U2446 ( .A(n1869), .Y(n1872) );
AO22XLTS U2447 ( .A0(n1870), .A1(data_in[33]), .B0(n1867), .B1(d_ff1_Z[33]),
.Y(n1300) );
AO22XLTS U2448 ( .A0(n1874), .A1(data_in[34]), .B0(n1875), .B1(d_ff1_Z[34]),
.Y(n1299) );
AO22XLTS U2449 ( .A0(n1874), .A1(data_in[35]), .B0(n1873), .B1(d_ff1_Z[35]),
.Y(n1298) );
AO22XLTS U2450 ( .A0(n1870), .A1(data_in[36]), .B0(n1872), .B1(d_ff1_Z[36]),
.Y(n1297) );
AO22XLTS U2451 ( .A0(n1870), .A1(data_in[37]), .B0(n1867), .B1(d_ff1_Z[37]),
.Y(n1296) );
AO22XLTS U2452 ( .A0(n1870), .A1(data_in[38]), .B0(n1875), .B1(d_ff1_Z[38]),
.Y(n1295) );
AO22XLTS U2453 ( .A0(n1870), .A1(data_in[39]), .B0(n1873), .B1(d_ff1_Z[39]),
.Y(n1294) );
AO22XLTS U2454 ( .A0(n1870), .A1(data_in[40]), .B0(n1872), .B1(d_ff1_Z[40]),
.Y(n1293) );
AO22XLTS U2455 ( .A0(n1870), .A1(data_in[41]), .B0(n1867), .B1(d_ff1_Z[41]),
.Y(n1292) );
AO22XLTS U2456 ( .A0(n1870), .A1(data_in[42]), .B0(n1875), .B1(d_ff1_Z[42]),
.Y(n1291) );
AO22XLTS U2457 ( .A0(n1870), .A1(data_in[43]), .B0(n1873), .B1(d_ff1_Z[43]),
.Y(n1290) );
AO22XLTS U2458 ( .A0(n1870), .A1(data_in[44]), .B0(n1872), .B1(d_ff1_Z[44]),
.Y(n1289) );
AO22XLTS U2459 ( .A0(n1871), .A1(data_in[45]), .B0(n1875), .B1(d_ff1_Z[45]),
.Y(n1288) );
AO22XLTS U2460 ( .A0(n1868), .A1(data_in[46]), .B0(n1872), .B1(d_ff1_Z[46]),
.Y(n1287) );
AO22XLTS U2461 ( .A0(n1871), .A1(data_in[47]), .B0(n1867), .B1(d_ff1_Z[47]),
.Y(n1286) );
AO22XLTS U2462 ( .A0(n1868), .A1(data_in[48]), .B0(n1873), .B1(d_ff1_Z[48]),
.Y(n1285) );
AO22XLTS U2463 ( .A0(n1871), .A1(data_in[49]), .B0(n1867), .B1(d_ff1_Z[49]),
.Y(n1284) );
AO22XLTS U2464 ( .A0(n1874), .A1(data_in[50]), .B0(n1875), .B1(d_ff1_Z[50]),
.Y(n1283) );
AO22XLTS U2465 ( .A0(n1874), .A1(data_in[51]), .B0(n1872), .B1(d_ff1_Z[51]),
.Y(n1282) );
AO22XLTS U2466 ( .A0(n1874), .A1(data_in[52]), .B0(n1875), .B1(d_ff1_Z[52]),
.Y(n1281) );
AO22XLTS U2467 ( .A0(n1874), .A1(data_in[53]), .B0(n1873), .B1(d_ff1_Z[53]),
.Y(n1280) );
AO22XLTS U2468 ( .A0(n1874), .A1(data_in[54]), .B0(n1867), .B1(d_ff1_Z[54]),
.Y(n1279) );
AO22XLTS U2469 ( .A0(n1874), .A1(data_in[55]), .B0(n1873), .B1(d_ff1_Z[55]),
.Y(n1278) );
AO22XLTS U2470 ( .A0(n1874), .A1(data_in[56]), .B0(n1872), .B1(d_ff1_Z[56]),
.Y(n1277) );
AO22XLTS U2471 ( .A0(n1874), .A1(data_in[57]), .B0(n1867), .B1(d_ff1_Z[57]),
.Y(n1276) );
AO22XLTS U2472 ( .A0(n1874), .A1(data_in[58]), .B0(n1875), .B1(d_ff1_Z[58]),
.Y(n1275) );
AO22XLTS U2473 ( .A0(n1874), .A1(data_in[59]), .B0(n1873), .B1(d_ff1_Z[59]),
.Y(n1274) );
AO22XLTS U2474 ( .A0(n1874), .A1(data_in[60]), .B0(n1872), .B1(d_ff1_Z[60]),
.Y(n1273) );
AO22XLTS U2475 ( .A0(n1874), .A1(data_in[61]), .B0(n1867), .B1(d_ff1_Z[61]),
.Y(n1272) );
AO22XLTS U2476 ( .A0(n1874), .A1(data_in[62]), .B0(n1875), .B1(d_ff1_Z[62]),
.Y(n1271) );
AO22XLTS U2477 ( .A0(n1874), .A1(data_in[63]), .B0(n1875), .B1(d_ff1_Z[63]),
.Y(n1270) );
AO22XLTS U2478 ( .A0(n1877), .A1(result_add_subt[0]), .B0(n1876), .B1(
d_ff_Zn[0]), .Y(n1265) );
AO22XLTS U2479 ( .A0(n1877), .A1(result_add_subt[1]), .B0(n1876), .B1(
d_ff_Zn[1]), .Y(n1264) );
BUFX4TS U2480 ( .A(n1876), .Y(n1880) );
AO22XLTS U2481 ( .A0(n1877), .A1(result_add_subt[2]), .B0(n1880), .B1(
d_ff_Zn[2]), .Y(n1263) );
AO22XLTS U2482 ( .A0(n1877), .A1(result_add_subt[3]), .B0(n1880), .B1(
d_ff_Zn[3]), .Y(n1262) );
AO22XLTS U2483 ( .A0(n1877), .A1(result_add_subt[4]), .B0(n1880), .B1(
d_ff_Zn[4]), .Y(n1261) );
AO22XLTS U2484 ( .A0(n1877), .A1(result_add_subt[5]), .B0(n1880), .B1(
d_ff_Zn[5]), .Y(n1260) );
AO22XLTS U2485 ( .A0(n1877), .A1(result_add_subt[6]), .B0(n1880), .B1(
d_ff_Zn[6]), .Y(n1259) );
AO22XLTS U2486 ( .A0(n1877), .A1(result_add_subt[7]), .B0(n1880), .B1(
d_ff_Zn[7]), .Y(n1258) );
AO22XLTS U2487 ( .A0(n1877), .A1(result_add_subt[8]), .B0(n1880), .B1(
d_ff_Zn[8]), .Y(n1257) );
AO22XLTS U2488 ( .A0(n1877), .A1(result_add_subt[9]), .B0(n1880), .B1(
d_ff_Zn[9]), .Y(n1256) );
AO22XLTS U2489 ( .A0(n1877), .A1(result_add_subt[10]), .B0(n1880), .B1(
d_ff_Zn[10]), .Y(n1255) );
AO22XLTS U2490 ( .A0(n1877), .A1(result_add_subt[11]), .B0(n1880), .B1(
d_ff_Zn[11]), .Y(n1254) );
AO22XLTS U2491 ( .A0(n1878), .A1(result_add_subt[12]), .B0(n1880), .B1(
d_ff_Zn[12]), .Y(n1253) );
AO22XLTS U2492 ( .A0(n1878), .A1(result_add_subt[13]), .B0(n1880), .B1(
d_ff_Zn[13]), .Y(n1252) );
AO22XLTS U2493 ( .A0(n1878), .A1(result_add_subt[16]), .B0(n1880), .B1(
d_ff_Zn[16]), .Y(n1249) );
AO22XLTS U2494 ( .A0(n1878), .A1(result_add_subt[18]), .B0(n1880), .B1(
d_ff_Zn[18]), .Y(n1247) );
AO22XLTS U2495 ( .A0(n1878), .A1(result_add_subt[19]), .B0(n1880), .B1(
d_ff_Zn[19]), .Y(n1246) );
AO22XLTS U2496 ( .A0(n1878), .A1(result_add_subt[20]), .B0(n1880), .B1(
d_ff_Zn[20]), .Y(n1245) );
AO22XLTS U2497 ( .A0(n1878), .A1(result_add_subt[21]), .B0(n1880), .B1(
d_ff_Zn[21]), .Y(n1244) );
AO22XLTS U2498 ( .A0(n1878), .A1(result_add_subt[22]), .B0(n1880), .B1(
d_ff_Zn[22]), .Y(n1243) );
AO22XLTS U2499 ( .A0(n1878), .A1(result_add_subt[23]), .B0(n1880), .B1(
d_ff_Zn[23]), .Y(n1242) );
INVX2TS U2500 ( .A(n1876), .Y(n1884) );
AO22XLTS U2501 ( .A0(n1884), .A1(result_add_subt[36]), .B0(n1883), .B1(
d_ff_Zn[36]), .Y(n1229) );
AO22XLTS U2502 ( .A0(n1884), .A1(result_add_subt[37]), .B0(n1883), .B1(
d_ff_Zn[37]), .Y(n1228) );
AO22XLTS U2503 ( .A0(n1884), .A1(result_add_subt[38]), .B0(n1883), .B1(
d_ff_Zn[38]), .Y(n1227) );
AO22XLTS U2504 ( .A0(n1884), .A1(result_add_subt[39]), .B0(n1883), .B1(
d_ff_Zn[39]), .Y(n1226) );
AO22XLTS U2505 ( .A0(n1884), .A1(result_add_subt[40]), .B0(n1883), .B1(
d_ff_Zn[40]), .Y(n1225) );
AO22XLTS U2506 ( .A0(n1884), .A1(result_add_subt[41]), .B0(n1883), .B1(
d_ff_Zn[41]), .Y(n1224) );
AO22XLTS U2507 ( .A0(n1884), .A1(result_add_subt[42]), .B0(n1883), .B1(
d_ff_Zn[42]), .Y(n1223) );
AO22XLTS U2508 ( .A0(n1884), .A1(result_add_subt[43]), .B0(n1883), .B1(
d_ff_Zn[43]), .Y(n1222) );
AO22XLTS U2509 ( .A0(n1884), .A1(result_add_subt[44]), .B0(n1883), .B1(
d_ff_Zn[44]), .Y(n1221) );
AO22XLTS U2510 ( .A0(n1882), .A1(result_add_subt[45]), .B0(n1883), .B1(
d_ff_Zn[45]), .Y(n1220) );
AO22XLTS U2511 ( .A0(n1882), .A1(result_add_subt[46]), .B0(n1883), .B1(
d_ff_Zn[46]), .Y(n1219) );
AO22XLTS U2512 ( .A0(n1884), .A1(result_add_subt[47]), .B0(n1876), .B1(
d_ff_Zn[47]), .Y(n1218) );
AO22XLTS U2513 ( .A0(n1882), .A1(result_add_subt[48]), .B0(n1876), .B1(
d_ff_Zn[48]), .Y(n1217) );
AO22XLTS U2514 ( .A0(n1882), .A1(result_add_subt[49]), .B0(n1876), .B1(
d_ff_Zn[49]), .Y(n1216) );
AO22XLTS U2515 ( .A0(n1882), .A1(result_add_subt[50]), .B0(n1876), .B1(
d_ff_Zn[50]), .Y(n1215) );
AO22XLTS U2516 ( .A0(n1882), .A1(result_add_subt[51]), .B0(n1876), .B1(
d_ff_Zn[51]), .Y(n1214) );
AO22XLTS U2517 ( .A0(n1882), .A1(result_add_subt[52]), .B0(n1876), .B1(
d_ff_Zn[52]), .Y(n1213) );
AO22XLTS U2518 ( .A0(n1882), .A1(result_add_subt[53]), .B0(n1876), .B1(
d_ff_Zn[53]), .Y(n1212) );
AO22XLTS U2519 ( .A0(n1882), .A1(result_add_subt[54]), .B0(n1876), .B1(
d_ff_Zn[54]), .Y(n1211) );
AO22XLTS U2520 ( .A0(n1882), .A1(result_add_subt[55]), .B0(n1876), .B1(
d_ff_Zn[55]), .Y(n1210) );
AO22XLTS U2521 ( .A0(n1882), .A1(result_add_subt[56]), .B0(n1876), .B1(
d_ff_Zn[56]), .Y(n1209) );
AO22XLTS U2522 ( .A0(n1882), .A1(result_add_subt[57]), .B0(n1881), .B1(
d_ff_Zn[57]), .Y(n1208) );
AO22XLTS U2523 ( .A0(n1882), .A1(result_add_subt[58]), .B0(n1883), .B1(
d_ff_Zn[58]), .Y(n1207) );
AO22XLTS U2524 ( .A0(n1882), .A1(result_add_subt[59]), .B0(n1876), .B1(
d_ff_Zn[59]), .Y(n1206) );
AO22XLTS U2525 ( .A0(n1882), .A1(result_add_subt[60]), .B0(n1880), .B1(
d_ff_Zn[60]), .Y(n1205) );
AO22XLTS U2526 ( .A0(n1882), .A1(result_add_subt[61]), .B0(n1876), .B1(
d_ff_Zn[61]), .Y(n1204) );
AO22XLTS U2527 ( .A0(n1882), .A1(result_add_subt[62]), .B0(n1881), .B1(
d_ff_Zn[62]), .Y(n1203) );
AO22XLTS U2528 ( .A0(n1882), .A1(result_add_subt[63]), .B0(n1883), .B1(
d_ff_Zn[63]), .Y(n1202) );
NOR2X1TS U2529 ( .A(n1886), .B(n1885), .Y(n1887) );
BUFX3TS U2530 ( .A(n1476), .Y(n1888) );
OAI2BB2XLTS U2531 ( .B0(n1891), .B1(n2074), .A0N(n1892), .A1N(
result_add_subt[0]), .Y(n1201) );
BUFX4TS U2532 ( .A(n1890), .Y(n1893) );
OAI2BB2XLTS U2533 ( .B0(n1893), .B1(n2075), .A0N(n1891), .A1N(
result_add_subt[1]), .Y(n1200) );
OAI2BB2XLTS U2534 ( .B0(n1890), .B1(n2076), .A0N(n1889), .A1N(
result_add_subt[2]), .Y(n1199) );
BUFX3TS U2535 ( .A(n1476), .Y(n1890) );
OAI2BB2XLTS U2536 ( .B0(n1893), .B1(n2077), .A0N(n1888), .A1N(
result_add_subt[3]), .Y(n1198) );
OAI2BB2XLTS U2537 ( .B0(n1893), .B1(n2078), .A0N(n1890), .A1N(
result_add_subt[4]), .Y(n1197) );
OAI2BB2XLTS U2538 ( .B0(n1891), .B1(n2079), .A0N(n1891), .A1N(
result_add_subt[5]), .Y(n1196) );
OAI2BB2XLTS U2539 ( .B0(n1890), .B1(n2080), .A0N(n1889), .A1N(
result_add_subt[6]), .Y(n1195) );
OAI2BB2XLTS U2540 ( .B0(n1893), .B1(n2081), .A0N(n1888), .A1N(
result_add_subt[7]), .Y(n1194) );
OAI2BB2XLTS U2541 ( .B0(n1893), .B1(n2082), .A0N(n1889), .A1N(
result_add_subt[8]), .Y(n1193) );
OAI2BB2XLTS U2542 ( .B0(n1893), .B1(n2083), .A0N(n1891), .A1N(
result_add_subt[9]), .Y(n1192) );
OAI2BB2XLTS U2543 ( .B0(n1892), .B1(n2084), .A0N(n1890), .A1N(
result_add_subt[10]), .Y(n1191) );
OAI2BB2XLTS U2544 ( .B0(n1893), .B1(n2085), .A0N(n1890), .A1N(
result_add_subt[11]), .Y(n1190) );
OAI2BB2XLTS U2545 ( .B0(n1893), .B1(n2086), .A0N(n1890), .A1N(
result_add_subt[12]), .Y(n1189) );
OAI2BB2XLTS U2546 ( .B0(n1893), .B1(n2087), .A0N(n1891), .A1N(
result_add_subt[13]), .Y(n1188) );
OAI2BB2XLTS U2547 ( .B0(n1893), .B1(n2088), .A0N(n1890), .A1N(
result_add_subt[14]), .Y(n1187) );
OAI2BB2XLTS U2548 ( .B0(n1893), .B1(n2089), .A0N(n1889), .A1N(
result_add_subt[15]), .Y(n1186) );
OAI2BB2XLTS U2549 ( .B0(n1892), .B1(n2090), .A0N(n1888), .A1N(
result_add_subt[16]), .Y(n1185) );
OAI2BB2XLTS U2550 ( .B0(n1892), .B1(n2091), .A0N(n1890), .A1N(
result_add_subt[17]), .Y(n1184) );
OAI2BB2XLTS U2551 ( .B0(n1893), .B1(n2092), .A0N(n1890), .A1N(
result_add_subt[18]), .Y(n1183) );
OAI2BB2XLTS U2552 ( .B0(n1892), .B1(n2093), .A0N(n1891), .A1N(
result_add_subt[19]), .Y(n1182) );
OAI2BB2XLTS U2553 ( .B0(n1892), .B1(n2094), .A0N(n1888), .A1N(
result_add_subt[20]), .Y(n1181) );
OAI2BB2XLTS U2554 ( .B0(n1892), .B1(n2095), .A0N(n1891), .A1N(
result_add_subt[21]), .Y(n1180) );
OAI2BB2XLTS U2555 ( .B0(n1892), .B1(n2096), .A0N(n1888), .A1N(
result_add_subt[22]), .Y(n1179) );
OAI2BB2XLTS U2556 ( .B0(n1892), .B1(n2097), .A0N(n1888), .A1N(
result_add_subt[23]), .Y(n1178) );
OAI2BB2XLTS U2557 ( .B0(n1892), .B1(n2098), .A0N(n1888), .A1N(
result_add_subt[24]), .Y(n1177) );
OAI2BB2XLTS U2558 ( .B0(n1892), .B1(n2099), .A0N(n1889), .A1N(
result_add_subt[25]), .Y(n1176) );
OAI2BB2XLTS U2559 ( .B0(n1892), .B1(n2100), .A0N(n1891), .A1N(
result_add_subt[26]), .Y(n1175) );
BUFX3TS U2560 ( .A(n1889), .Y(n1894) );
OAI2BB2XLTS U2561 ( .B0(n1894), .B1(n2101), .A0N(n1888), .A1N(
result_add_subt[27]), .Y(n1174) );
OAI2BB2XLTS U2562 ( .B0(n1894), .B1(n2102), .A0N(n1888), .A1N(
result_add_subt[28]), .Y(n1173) );
OAI2BB2XLTS U2563 ( .B0(n1894), .B1(n2103), .A0N(n1890), .A1N(
result_add_subt[29]), .Y(n1172) );
OAI2BB2XLTS U2564 ( .B0(n1894), .B1(n2104), .A0N(n1888), .A1N(
result_add_subt[30]), .Y(n1171) );
OAI2BB2XLTS U2565 ( .B0(n1892), .B1(n2105), .A0N(n1888), .A1N(
result_add_subt[31]), .Y(n1170) );
OAI2BB2XLTS U2566 ( .B0(n1894), .B1(n2106), .A0N(n1889), .A1N(
result_add_subt[32]), .Y(n1169) );
OAI2BB2XLTS U2567 ( .B0(n1894), .B1(n2107), .A0N(n1891), .A1N(
result_add_subt[33]), .Y(n1168) );
OAI2BB2XLTS U2568 ( .B0(n1894), .B1(n2108), .A0N(n1889), .A1N(
result_add_subt[34]), .Y(n1167) );
OAI2BB2XLTS U2569 ( .B0(n1894), .B1(n2109), .A0N(n1891), .A1N(
result_add_subt[35]), .Y(n1166) );
OAI2BB2XLTS U2570 ( .B0(n1894), .B1(n2110), .A0N(n1891), .A1N(
result_add_subt[36]), .Y(n1165) );
OAI2BB2XLTS U2571 ( .B0(n1894), .B1(n2111), .A0N(n1889), .A1N(
result_add_subt[37]), .Y(n1164) );
OAI2BB2XLTS U2572 ( .B0(n1894), .B1(n2112), .A0N(n1890), .A1N(
result_add_subt[38]), .Y(n1163) );
OAI2BB2XLTS U2573 ( .B0(n1476), .B1(n2113), .A0N(n1891), .A1N(
result_add_subt[39]), .Y(n1162) );
OAI2BB2XLTS U2574 ( .B0(n1476), .B1(n2114), .A0N(n1891), .A1N(
result_add_subt[40]), .Y(n1161) );
OAI2BB2XLTS U2575 ( .B0(n1476), .B1(n2115), .A0N(n1890), .A1N(
result_add_subt[41]), .Y(n1160) );
OAI2BB2XLTS U2576 ( .B0(n1476), .B1(n2116), .A0N(n1891), .A1N(
result_add_subt[42]), .Y(n1159) );
OAI2BB2XLTS U2577 ( .B0(n1476), .B1(n2117), .A0N(n1890), .A1N(
result_add_subt[43]), .Y(n1158) );
OAI2BB2XLTS U2578 ( .B0(n1476), .B1(n2118), .A0N(n1889), .A1N(
result_add_subt[44]), .Y(n1157) );
OAI2BB2XLTS U2579 ( .B0(n1476), .B1(n2119), .A0N(n1891), .A1N(
result_add_subt[45]), .Y(n1156) );
OAI2BB2XLTS U2580 ( .B0(n1476), .B1(n2120), .A0N(n1891), .A1N(
result_add_subt[46]), .Y(n1155) );
OAI2BB2XLTS U2581 ( .B0(n1476), .B1(n2121), .A0N(n1889), .A1N(
result_add_subt[47]), .Y(n1154) );
OAI2BB2XLTS U2582 ( .B0(n1476), .B1(n2122), .A0N(n1889), .A1N(
result_add_subt[48]), .Y(n1153) );
OAI2BB2XLTS U2583 ( .B0(n1476), .B1(n2123), .A0N(n1889), .A1N(
result_add_subt[49]), .Y(n1152) );
OAI2BB2XLTS U2584 ( .B0(n1476), .B1(n2124), .A0N(n1889), .A1N(
result_add_subt[50]), .Y(n1151) );
OAI2BB2XLTS U2585 ( .B0(n1476), .B1(n2125), .A0N(n1889), .A1N(
result_add_subt[51]), .Y(n1150) );
OAI2BB2XLTS U2586 ( .B0(n1476), .B1(n2188), .A0N(n1891), .A1N(
result_add_subt[52]), .Y(n1149) );
OAI2BB2XLTS U2587 ( .B0(n1893), .B1(n2189), .A0N(n1889), .A1N(
result_add_subt[53]), .Y(n1148) );
OAI2BB2XLTS U2588 ( .B0(n1893), .B1(n2126), .A0N(n1889), .A1N(
result_add_subt[54]), .Y(n1147) );
OAI2BB2XLTS U2589 ( .B0(n1476), .B1(n2190), .A0N(n1888), .A1N(
result_add_subt[55]), .Y(n1146) );
OAI2BB2XLTS U2590 ( .B0(n1893), .B1(n2191), .A0N(n1888), .A1N(
result_add_subt[56]), .Y(n1145) );
OAI2BB2XLTS U2591 ( .B0(n1476), .B1(n2192), .A0N(n1889), .A1N(
result_add_subt[57]), .Y(n1144) );
OAI2BB2XLTS U2592 ( .B0(n1893), .B1(n2193), .A0N(n1476), .A1N(
result_add_subt[58]), .Y(n1143) );
OAI2BB2XLTS U2593 ( .B0(n1476), .B1(n2194), .A0N(n1888), .A1N(
result_add_subt[59]), .Y(n1142) );
OAI2BB2XLTS U2594 ( .B0(n1893), .B1(n2195), .A0N(n1476), .A1N(
result_add_subt[60]), .Y(n1141) );
OAI2BB2XLTS U2595 ( .B0(n1476), .B1(n2196), .A0N(n1891), .A1N(
result_add_subt[61]), .Y(n1140) );
OAI2BB2XLTS U2596 ( .B0(n1893), .B1(n2197), .A0N(n1892), .A1N(
result_add_subt[62]), .Y(n1139) );
OAI2BB2XLTS U2597 ( .B0(n1894), .B1(n2127), .A0N(n1894), .A1N(
result_add_subt[63]), .Y(n1138) );
BUFX3TS U2598 ( .A(n1487), .Y(n1899) );
BUFX3TS U2599 ( .A(n1487), .Y(n1900) );
AO22XLTS U2600 ( .A0(n1908), .A1(sign_inv_out[0]), .B0(n1486), .B1(
data_output[0]), .Y(n1072) );
AO22XLTS U2601 ( .A0(n1904), .A1(sign_inv_out[1]), .B0(n1486), .B1(
data_output[1]), .Y(n1070) );
BUFX4TS U2602 ( .A(n1486), .Y(n1906) );
AO22XLTS U2603 ( .A0(n1908), .A1(sign_inv_out[2]), .B0(n1906), .B1(
data_output[2]), .Y(n1068) );
AO22XLTS U2604 ( .A0(n1903), .A1(sign_inv_out[3]), .B0(n1906), .B1(
data_output[3]), .Y(n1066) );
AO22XLTS U2605 ( .A0(n1904), .A1(sign_inv_out[4]), .B0(n1906), .B1(
data_output[4]), .Y(n1064) );
AO22XLTS U2606 ( .A0(n1908), .A1(sign_inv_out[5]), .B0(n1906), .B1(
data_output[5]), .Y(n1062) );
AO22XLTS U2607 ( .A0(n1903), .A1(sign_inv_out[6]), .B0(n1906), .B1(
data_output[6]), .Y(n1060) );
AO22XLTS U2608 ( .A0(n1904), .A1(sign_inv_out[7]), .B0(n1906), .B1(
data_output[7]), .Y(n1058) );
AO22XLTS U2609 ( .A0(n1908), .A1(sign_inv_out[8]), .B0(n1906), .B1(
data_output[8]), .Y(n1056) );
AO22XLTS U2610 ( .A0(n1903), .A1(sign_inv_out[9]), .B0(n1906), .B1(
data_output[9]), .Y(n1054) );
AO22XLTS U2611 ( .A0(n1904), .A1(sign_inv_out[10]), .B0(n1906), .B1(
data_output[10]), .Y(n1052) );
AO22XLTS U2612 ( .A0(n1908), .A1(sign_inv_out[11]), .B0(n1906), .B1(
data_output[11]), .Y(n1050) );
AO22XLTS U2613 ( .A0(n1903), .A1(sign_inv_out[12]), .B0(n1906), .B1(
data_output[12]), .Y(n1048) );
AO22XLTS U2614 ( .A0(n1904), .A1(sign_inv_out[15]), .B0(n1906), .B1(
data_output[15]), .Y(n1042) );
AO22XLTS U2615 ( .A0(n1908), .A1(sign_inv_out[17]), .B0(n1906), .B1(
data_output[17]), .Y(n1038) );
AO22XLTS U2616 ( .A0(n1903), .A1(sign_inv_out[18]), .B0(n1906), .B1(
data_output[18]), .Y(n1036) );
AO22XLTS U2617 ( .A0(n1904), .A1(sign_inv_out[19]), .B0(n1906), .B1(
data_output[19]), .Y(n1034) );
AO22XLTS U2618 ( .A0(n1908), .A1(sign_inv_out[20]), .B0(n1906), .B1(
data_output[20]), .Y(n1032) );
AO22XLTS U2619 ( .A0(n1903), .A1(sign_inv_out[21]), .B0(n1906), .B1(
data_output[21]), .Y(n1030) );
AO22XLTS U2620 ( .A0(n1904), .A1(sign_inv_out[22]), .B0(n1906), .B1(
data_output[22]), .Y(n1028) );
AO22XLTS U2621 ( .A0(n1908), .A1(sign_inv_out[23]), .B0(n1906), .B1(
data_output[23]), .Y(n1026) );
INVX2TS U2622 ( .A(n1486), .Y(n1910) );
AO22XLTS U2623 ( .A0(n1910), .A1(sign_inv_out[36]), .B0(n1486), .B1(
data_output[36]), .Y(n1000) );
AO22XLTS U2624 ( .A0(n1910), .A1(sign_inv_out[37]), .B0(n1486), .B1(
data_output[37]), .Y(n998) );
AO22XLTS U2625 ( .A0(n1910), .A1(sign_inv_out[38]), .B0(n1486), .B1(
data_output[38]), .Y(n996) );
AO22XLTS U2626 ( .A0(n1910), .A1(sign_inv_out[39]), .B0(n1486), .B1(
data_output[39]), .Y(n994) );
AO22XLTS U2627 ( .A0(n1910), .A1(sign_inv_out[40]), .B0(n1486), .B1(
data_output[40]), .Y(n992) );
AO22XLTS U2628 ( .A0(n1910), .A1(sign_inv_out[41]), .B0(n1486), .B1(
data_output[41]), .Y(n990) );
AO22XLTS U2629 ( .A0(n1908), .A1(sign_inv_out[42]), .B0(n1486), .B1(
data_output[42]), .Y(n988) );
AO22XLTS U2630 ( .A0(n1903), .A1(sign_inv_out[43]), .B0(n1486), .B1(
data_output[43]), .Y(n986) );
AO22XLTS U2631 ( .A0(n1904), .A1(sign_inv_out[44]), .B0(n1486), .B1(
data_output[44]), .Y(n984) );
AO22XLTS U2632 ( .A0(n1908), .A1(sign_inv_out[45]), .B0(n1486), .B1(
data_output[45]), .Y(n982) );
AO22XLTS U2633 ( .A0(n1910), .A1(sign_inv_out[46]), .B0(n1907), .B1(
data_output[46]), .Y(n980) );
AO22XLTS U2634 ( .A0(n1910), .A1(sign_inv_out[47]), .B0(n1907), .B1(
data_output[47]), .Y(n978) );
AO22XLTS U2635 ( .A0(n1903), .A1(sign_inv_out[48]), .B0(n1907), .B1(
data_output[48]), .Y(n976) );
AO22XLTS U2636 ( .A0(n1904), .A1(sign_inv_out[49]), .B0(n1907), .B1(
data_output[49]), .Y(n974) );
AO22XLTS U2637 ( .A0(n1908), .A1(sign_inv_out[50]), .B0(n1907), .B1(
data_output[50]), .Y(n972) );
AO22XLTS U2638 ( .A0(n1903), .A1(sign_inv_out[51]), .B0(n1907), .B1(
data_output[51]), .Y(n970) );
AO22XLTS U2639 ( .A0(n1904), .A1(sign_inv_out[52]), .B0(n1907), .B1(
data_output[52]), .Y(n968) );
AO22XLTS U2640 ( .A0(n1908), .A1(sign_inv_out[53]), .B0(n1907), .B1(
data_output[53]), .Y(n966) );
AO22XLTS U2641 ( .A0(n1903), .A1(sign_inv_out[54]), .B0(n1907), .B1(
data_output[54]), .Y(n964) );
AO22XLTS U2642 ( .A0(n1904), .A1(sign_inv_out[55]), .B0(n1907), .B1(
data_output[55]), .Y(n962) );
AO22XLTS U2643 ( .A0(n1908), .A1(sign_inv_out[56]), .B0(n1907), .B1(
data_output[56]), .Y(n960) );
AO22XLTS U2644 ( .A0(n1903), .A1(sign_inv_out[57]), .B0(n1909), .B1(
data_output[57]), .Y(n958) );
AO22XLTS U2645 ( .A0(n1903), .A1(sign_inv_out[58]), .B0(n1486), .B1(
data_output[58]), .Y(n956) );
AO22XLTS U2646 ( .A0(n1904), .A1(sign_inv_out[59]), .B0(n1486), .B1(
data_output[59]), .Y(n954) );
AO22XLTS U2647 ( .A0(n1910), .A1(sign_inv_out[60]), .B0(n1906), .B1(
data_output[60]), .Y(n952) );
AO22XLTS U2648 ( .A0(n1904), .A1(sign_inv_out[61]), .B0(n1907), .B1(
data_output[61]), .Y(n950) );
AO22XLTS U2649 ( .A0(n1910), .A1(sign_inv_out[62]), .B0(n1909), .B1(
data_output[62]), .Y(n948) );
AOI32X1TS U2650 ( .A0(n1951), .A1(n1952), .A2(n1475), .B0(d_ff3_LUT_out[0]),
.B1(n1478), .Y(n1912) );
NAND3X1TS U2651 ( .A(cont_iter_out[2]), .B(cont_iter_out[1]), .C(n1915), .Y(
n1956) );
NAND3XLTS U2652 ( .A(n1912), .B(n1956), .C(n1911), .Y(n945) );
BUFX3TS U2653 ( .A(n1479), .Y(n1983) );
AOI31XLTS U2654 ( .A0(n1475), .A1(n1485), .A2(n1913), .B0(n1478), .Y(n1914)
);
AO21XLTS U2655 ( .A0(d_ff3_LUT_out[2]), .A1(n1983), .B0(n1914), .Y(n943) );
AOI21X2TS U2656 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[1]), .B0(
cont_iter_out[3]), .Y(n1975) );
AOI31X1TS U2657 ( .A0(n1975), .A1(n1974), .A2(n1925), .B0(n1478), .Y(n1962)
);
AO21XLTS U2658 ( .A0(d_ff3_LUT_out[4]), .A1(n1479), .B0(n1962), .Y(n941) );
AOI22X1TS U2659 ( .A0(n1915), .A1(n2070), .B0(n1478), .B1(d_ff3_LUT_out[5]),
.Y(n1916) );
NAND2X1TS U2660 ( .A(n1916), .B(n1949), .Y(n940) );
NAND2X1TS U2661 ( .A(n2041), .B(n1938), .Y(n1960) );
OAI21XLTS U2662 ( .A0(n1952), .A1(d_ff3_LUT_out[6]), .B0(n1917), .Y(n1918)
);
NAND3XLTS U2663 ( .A(n1961), .B(n1960), .C(n1918), .Y(n939) );
AOI22X1TS U2664 ( .A0(n2185), .A1(n1478), .B0(n1940), .B1(n1919), .Y(n937)
);
NAND3XLTS U2665 ( .A(n1952), .B(n1951), .C(n1475), .Y(n1922) );
INVX2TS U2666 ( .A(n1920), .Y(n1931) );
NAND4BXLTS U2667 ( .AN(n1923), .B(n1934), .C(n1922), .D(n1921), .Y(n936) );
AOI211X1TS U2668 ( .A0(cont_iter_out[3]), .A1(n1924), .B0(n1478), .C0(n1926),
.Y(n1963) );
AOI2BB2XLTS U2669 ( .B0(n1963), .B1(n1925), .A0N(n2055), .A1N(
d_ff3_LUT_out[10]), .Y(n935) );
AOI211X1TS U2670 ( .A0(n2129), .A1(n1480), .B0(cont_iter_out[3]), .C0(
cont_iter_out[2]), .Y(n1946) );
NAND2X1TS U2671 ( .A(n2055), .B(n1946), .Y(n1980) );
OA21XLTS U2672 ( .A0(n2052), .A1(d_ff3_LUT_out[12]), .B0(n1980), .Y(n933) );
NOR3XLTS U2673 ( .A(n1931), .B(n1927), .C(n1926), .Y(n1929) );
NOR2X2TS U2674 ( .A(n1928), .B(n2021), .Y(n1979) );
AOI2BB2XLTS U2675 ( .B0(n1929), .B1(n1979), .A0N(n2055), .A1N(
d_ff3_LUT_out[13]), .Y(n932) );
NAND3BXLTS U2676 ( .AN(n1972), .B(n1932), .C(n1960), .Y(n930) );
BUFX3TS U2677 ( .A(n1479), .Y(n1984) );
AOI21X1TS U2678 ( .A0(n1975), .A1(n1965), .B0(n1478), .Y(n1933) );
AO21XLTS U2679 ( .A0(d_ff3_LUT_out[16]), .A1(n1984), .B0(n1933), .Y(n929) );
OAI2BB1X1TS U2680 ( .A0N(d_ff3_LUT_out[17]), .A1N(n1479), .B0(n1934), .Y(
n928) );
AOI211X1TS U2681 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[3]), .B0(n1977),
.C0(n1935), .Y(n1970) );
NAND2BXLTS U2682 ( .AN(n1937), .B(n1970), .Y(n1966) );
OA22X1TS U2683 ( .A0(n1938), .A1(n1966), .B0(n2055), .B1(d_ff3_LUT_out[18]),
.Y(n927) );
AOI2BB2XLTS U2684 ( .B0(n2047), .B1(n1975), .A0N(d_ff3_LUT_out[20]), .A1N(
n2052), .Y(n925) );
AOI2BB2XLTS U2685 ( .B0(n1939), .B1(n1944), .A0N(n2055), .A1N(
d_ff3_LUT_out[21]), .Y(n924) );
OAI2BB1X1TS U2686 ( .A0N(d_ff3_LUT_out[22]), .A1N(n1479), .B0(n1940), .Y(
n923) );
AOI211X1TS U2687 ( .A0(n1942), .A1(n1951), .B0(n1947), .C0(n1941), .Y(n1943)
);
INVX2TS U2688 ( .A(n1943), .Y(n1953) );
NOR2XLTS U2689 ( .A(n1954), .B(n1953), .Y(n1945) );
AOI2BB2XLTS U2690 ( .B0(n1945), .B1(n1944), .A0N(n2055), .A1N(
d_ff3_LUT_out[23]), .Y(n922) );
NAND2X1TS U2691 ( .A(n1946), .B(n1974), .Y(n1964) );
AO22XLTS U2692 ( .A0(n2039), .A1(n1964), .B0(n1983), .B1(d_ff3_LUT_out[24]),
.Y(n921) );
OAI21XLTS U2693 ( .A0(n2052), .A1(d_ff3_LUT_out[25]), .B0(n1947), .Y(n1948)
);
NAND3XLTS U2694 ( .A(n1956), .B(n1949), .C(n1948), .Y(n920) );
NAND2X1TS U2695 ( .A(n1951), .B(n1950), .Y(n1957) );
OAI22X1TS U2696 ( .A0(n1954), .A1(n1953), .B0(n1952), .B1(d_ff3_LUT_out[27]),
.Y(n1955) );
NAND4XLTS U2697 ( .A(n1957), .B(n1960), .C(n1956), .D(n1955), .Y(n918) );
OAI2BB1X1TS U2698 ( .A0N(d_ff3_LUT_out[28]), .A1N(n1479), .B0(n1973), .Y(
n917) );
NAND2X1TS U2699 ( .A(d_ff3_LUT_out[29]), .B(n2021), .Y(n1958) );
NAND4XLTS U2700 ( .A(n1961), .B(n1960), .C(n1959), .D(n1958), .Y(n916) );
AO21XLTS U2701 ( .A0(d_ff3_LUT_out[30]), .A1(n1479), .B0(n1962), .Y(n915) );
AOI2BB2XLTS U2702 ( .B0(n1963), .B1(n1974), .A0N(n2055), .A1N(
d_ff3_LUT_out[31]), .Y(n914) );
OAI21X1TS U2703 ( .A0(n1977), .A1(n1964), .B0(n2041), .Y(n1968) );
OAI2BB1X1TS U2704 ( .A0N(d_ff3_LUT_out[32]), .A1N(n1479), .B0(n1968), .Y(
n913) );
AOI31X1TS U2705 ( .A0(n1975), .A1(n1965), .A2(n1974), .B0(n1478), .Y(n1976)
);
AO21XLTS U2706 ( .A0(d_ff3_LUT_out[34]), .A1(n1479), .B0(n1976), .Y(n911) );
OA21XLTS U2707 ( .A0(n2039), .A1(d_ff3_LUT_out[35]), .B0(n1966), .Y(n910) );
OAI2BB1X1TS U2708 ( .A0N(d_ff3_LUT_out[36]), .A1N(n1479), .B0(n1973), .Y(
n909) );
AO22XLTS U2709 ( .A0(n2039), .A1(n1967), .B0(n1983), .B1(d_ff3_LUT_out[37]),
.Y(n908) );
OAI2BB1X1TS U2710 ( .A0N(d_ff3_LUT_out[38]), .A1N(n1479), .B0(n1968), .Y(
n907) );
OAI2BB2XLTS U2711 ( .B0(n2055), .B1(d_ff3_LUT_out[39]), .A0N(n1970), .A1N(
n1969), .Y(n1971) );
OAI2BB1X1TS U2712 ( .A0N(d_ff3_LUT_out[40]), .A1N(n1479), .B0(n1973), .Y(
n905) );
AOI32X1TS U2713 ( .A0(n1975), .A1(n1952), .A2(n1974), .B0(n2186), .B1(n1478),
.Y(n904) );
AOI31X1TS U2714 ( .A0(n1475), .A1(n1485), .A2(n2070), .B0(n1478), .Y(n1978)
);
AO21XLTS U2715 ( .A0(d_ff3_LUT_out[42]), .A1(n1983), .B0(n1978), .Y(n903) );
AO21XLTS U2716 ( .A0(d_ff3_LUT_out[43]), .A1(n1983), .B0(n1976), .Y(n902) );
AO21XLTS U2717 ( .A0(d_ff3_LUT_out[44]), .A1(n1983), .B0(n1979), .Y(n901) );
OA22X1TS U2718 ( .A0(n1977), .A1(n1980), .B0(n2055), .B1(d_ff3_LUT_out[45]),
.Y(n900) );
AO21XLTS U2719 ( .A0(d_ff3_LUT_out[46]), .A1(n1983), .B0(n1979), .Y(n899) );
AO21XLTS U2720 ( .A0(d_ff3_LUT_out[47]), .A1(n1983), .B0(n1978), .Y(n898) );
NAND2BXLTS U2721 ( .AN(d_ff3_LUT_out[48]), .B(n2021), .Y(n897) );
AO21XLTS U2722 ( .A0(d_ff3_LUT_out[49]), .A1(n1983), .B0(n1979), .Y(n896) );
OA22X1TS U2723 ( .A0(n1981), .A1(n1980), .B0(n2055), .B1(d_ff3_LUT_out[50]),
.Y(n895) );
AO22XLTS U2724 ( .A0(n2039), .A1(n2129), .B0(n1983), .B1(d_ff3_LUT_out[52]),
.Y(n894) );
AO22XLTS U2725 ( .A0(n2019), .A1(n1982), .B0(n1983), .B1(d_ff3_LUT_out[56]),
.Y(n890) );
AO22XLTS U2726 ( .A0(n1479), .A1(d_ff3_sign_out), .B0(n2039), .B1(
d_ff2_Z[63]), .Y(n825) );
INVX4TS U2727 ( .A(n2010), .Y(n2029) );
AO22XLTS U2728 ( .A0(d_ff_Yn[0]), .A1(n2029), .B0(d_ff2_Y[0]), .B1(n1687),
.Y(n824) );
AO22XLTS U2729 ( .A0(n2039), .A1(d_ff2_Y[0]), .B0(n1983), .B1(
d_ff3_sh_y_out[0]), .Y(n823) );
INVX4TS U2730 ( .A(n2010), .Y(n2016) );
AO22XLTS U2731 ( .A0(d_ff_Yn[1]), .A1(n2016), .B0(d_ff2_Y[1]), .B1(n1670),
.Y(n822) );
AO22XLTS U2732 ( .A0(n2052), .A1(d_ff2_Y[1]), .B0(n1984), .B1(
d_ff3_sh_y_out[1]), .Y(n821) );
AO22XLTS U2733 ( .A0(d_ff_Yn[2]), .A1(n2016), .B0(d_ff2_Y[2]), .B1(n1985),
.Y(n820) );
AO22XLTS U2734 ( .A0(n2039), .A1(d_ff2_Y[2]), .B0(n1984), .B1(
d_ff3_sh_y_out[2]), .Y(n819) );
AO22XLTS U2735 ( .A0(d_ff_Yn[3]), .A1(n2029), .B0(d_ff2_Y[3]), .B1(n1985),
.Y(n818) );
AO22XLTS U2736 ( .A0(n2039), .A1(d_ff2_Y[3]), .B0(n1984), .B1(
d_ff3_sh_y_out[3]), .Y(n817) );
AO22XLTS U2737 ( .A0(d_ff_Yn[4]), .A1(n2029), .B0(d_ff2_Y[4]), .B1(n1985),
.Y(n816) );
AO22XLTS U2738 ( .A0(n2052), .A1(d_ff2_Y[4]), .B0(n1984), .B1(
d_ff3_sh_y_out[4]), .Y(n815) );
AO22XLTS U2739 ( .A0(d_ff_Yn[5]), .A1(n2016), .B0(d_ff2_Y[5]), .B1(n1985),
.Y(n814) );
AO22XLTS U2740 ( .A0(n2039), .A1(d_ff2_Y[5]), .B0(n1984), .B1(
d_ff3_sh_y_out[5]), .Y(n813) );
AO22XLTS U2741 ( .A0(d_ff_Yn[6]), .A1(n2016), .B0(d_ff2_Y[6]), .B1(n1985),
.Y(n812) );
AO22XLTS U2742 ( .A0(n2052), .A1(d_ff2_Y[6]), .B0(n1984), .B1(
d_ff3_sh_y_out[6]), .Y(n811) );
AO22XLTS U2743 ( .A0(d_ff_Yn[7]), .A1(n2016), .B0(d_ff2_Y[7]), .B1(n1985),
.Y(n810) );
AO22XLTS U2744 ( .A0(n2019), .A1(d_ff2_Y[7]), .B0(n1984), .B1(
d_ff3_sh_y_out[7]), .Y(n809) );
AO22XLTS U2745 ( .A0(d_ff_Yn[8]), .A1(n2016), .B0(d_ff2_Y[8]), .B1(n1985),
.Y(n808) );
AO22XLTS U2746 ( .A0(n2019), .A1(d_ff2_Y[8]), .B0(n1984), .B1(
d_ff3_sh_y_out[8]), .Y(n807) );
AO22XLTS U2747 ( .A0(d_ff_Yn[9]), .A1(n2016), .B0(d_ff2_Y[9]), .B1(n1985),
.Y(n806) );
AO22XLTS U2748 ( .A0(n2019), .A1(d_ff2_Y[9]), .B0(n1984), .B1(
d_ff3_sh_y_out[9]), .Y(n805) );
AO22XLTS U2749 ( .A0(d_ff_Yn[10]), .A1(n2016), .B0(d_ff2_Y[10]), .B1(n1985),
.Y(n804) );
AO22XLTS U2750 ( .A0(n2019), .A1(d_ff2_Y[10]), .B0(n1984), .B1(
d_ff3_sh_y_out[10]), .Y(n803) );
AO22XLTS U2751 ( .A0(d_ff_Yn[11]), .A1(n2016), .B0(d_ff2_Y[11]), .B1(n1985),
.Y(n802) );
AO22XLTS U2752 ( .A0(n2019), .A1(d_ff2_Y[11]), .B0(n1984), .B1(
d_ff3_sh_y_out[11]), .Y(n801) );
AO22XLTS U2753 ( .A0(d_ff_Yn[12]), .A1(n2016), .B0(d_ff2_Y[12]), .B1(n1985),
.Y(n800) );
BUFX3TS U2754 ( .A(n1479), .Y(n2012) );
AO22XLTS U2755 ( .A0(n2052), .A1(d_ff2_Y[12]), .B0(n2012), .B1(
d_ff3_sh_y_out[12]), .Y(n799) );
AO22XLTS U2756 ( .A0(d_ff_Yn[13]), .A1(n2016), .B0(d_ff2_Y[13]), .B1(n1985),
.Y(n798) );
AO22XLTS U2757 ( .A0(n2052), .A1(d_ff2_Y[13]), .B0(n2012), .B1(
d_ff3_sh_y_out[13]), .Y(n797) );
AO22XLTS U2758 ( .A0(d_ff_Yn[14]), .A1(n2016), .B0(d_ff2_Y[14]), .B1(n2018),
.Y(n796) );
BUFX4TS U2759 ( .A(n2012), .Y(n2058) );
AO22XLTS U2760 ( .A0(n2019), .A1(d_ff2_Y[14]), .B0(n2058), .B1(
d_ff3_sh_y_out[14]), .Y(n795) );
AO22XLTS U2761 ( .A0(d_ff_Yn[15]), .A1(n2016), .B0(d_ff2_Y[15]), .B1(n2018),
.Y(n794) );
AO22XLTS U2762 ( .A0(n2052), .A1(d_ff2_Y[15]), .B0(n2058), .B1(
d_ff3_sh_y_out[15]), .Y(n793) );
AO22XLTS U2763 ( .A0(d_ff_Yn[16]), .A1(n2013), .B0(d_ff2_Y[16]), .B1(n1696),
.Y(n792) );
AO22XLTS U2764 ( .A0(n2019), .A1(d_ff2_Y[16]), .B0(n2058), .B1(
d_ff3_sh_y_out[16]), .Y(n791) );
AO22XLTS U2765 ( .A0(d_ff_Yn[17]), .A1(n2057), .B0(d_ff2_Y[17]), .B1(n2030),
.Y(n790) );
AO22XLTS U2766 ( .A0(n2052), .A1(d_ff2_Y[17]), .B0(n2058), .B1(
d_ff3_sh_y_out[17]), .Y(n789) );
AO22XLTS U2767 ( .A0(d_ff_Yn[18]), .A1(n2013), .B0(d_ff2_Y[18]), .B1(n1696),
.Y(n788) );
AO22XLTS U2768 ( .A0(n2019), .A1(d_ff2_Y[18]), .B0(n2058), .B1(
d_ff3_sh_y_out[18]), .Y(n787) );
AO22XLTS U2769 ( .A0(d_ff_Yn[19]), .A1(n2057), .B0(d_ff2_Y[19]), .B1(n1696),
.Y(n786) );
AO22XLTS U2770 ( .A0(n2052), .A1(d_ff2_Y[19]), .B0(n2058), .B1(
d_ff3_sh_y_out[19]), .Y(n785) );
AO22XLTS U2771 ( .A0(d_ff_Yn[20]), .A1(n2057), .B0(d_ff2_Y[20]), .B1(n1687),
.Y(n784) );
AO22XLTS U2772 ( .A0(n2059), .A1(d_ff2_Y[20]), .B0(n2058), .B1(
d_ff3_sh_y_out[20]), .Y(n783) );
AO22XLTS U2773 ( .A0(d_ff_Yn[21]), .A1(n2013), .B0(d_ff2_Y[21]), .B1(n2030),
.Y(n782) );
AO22XLTS U2774 ( .A0(n2019), .A1(d_ff2_Y[21]), .B0(n2058), .B1(
d_ff3_sh_y_out[21]), .Y(n781) );
AO22XLTS U2775 ( .A0(d_ff_Yn[22]), .A1(n2013), .B0(d_ff2_Y[22]), .B1(n2026),
.Y(n780) );
AO22XLTS U2776 ( .A0(n2019), .A1(d_ff2_Y[22]), .B0(n2058), .B1(
d_ff3_sh_y_out[22]), .Y(n779) );
AO22XLTS U2777 ( .A0(d_ff_Yn[23]), .A1(n2013), .B0(d_ff2_Y[23]), .B1(n2030),
.Y(n778) );
BUFX3TS U2778 ( .A(n1479), .Y(n2009) );
BUFX4TS U2779 ( .A(n2009), .Y(n1987) );
AO22XLTS U2780 ( .A0(n2019), .A1(d_ff2_Y[23]), .B0(n1987), .B1(
d_ff3_sh_y_out[23]), .Y(n777) );
AO22XLTS U2781 ( .A0(d_ff_Yn[24]), .A1(n2057), .B0(d_ff2_Y[24]), .B1(n2030),
.Y(n776) );
AO22XLTS U2782 ( .A0(n2019), .A1(d_ff2_Y[24]), .B0(n2009), .B1(
d_ff3_sh_y_out[24]), .Y(n775) );
AO22XLTS U2783 ( .A0(d_ff_Yn[25]), .A1(n2057), .B0(d_ff2_Y[25]), .B1(n1693),
.Y(n774) );
AO22XLTS U2784 ( .A0(n2019), .A1(d_ff2_Y[25]), .B0(n2009), .B1(
d_ff3_sh_y_out[25]), .Y(n773) );
AO22XLTS U2785 ( .A0(d_ff_Yn[26]), .A1(n2013), .B0(d_ff2_Y[26]), .B1(n2026),
.Y(n772) );
AO22XLTS U2786 ( .A0(n2019), .A1(d_ff2_Y[26]), .B0(n1987), .B1(
d_ff3_sh_y_out[26]), .Y(n771) );
AO22XLTS U2787 ( .A0(d_ff_Yn[27]), .A1(n2057), .B0(d_ff2_Y[27]), .B1(n1696),
.Y(n770) );
AO22XLTS U2788 ( .A0(n2019), .A1(d_ff2_Y[27]), .B0(n1987), .B1(
d_ff3_sh_y_out[27]), .Y(n769) );
AO22XLTS U2789 ( .A0(d_ff_Yn[28]), .A1(n2017), .B0(d_ff2_Y[28]), .B1(n2026),
.Y(n768) );
AO22XLTS U2790 ( .A0(n2019), .A1(d_ff2_Y[28]), .B0(n1987), .B1(
d_ff3_sh_y_out[28]), .Y(n767) );
INVX4TS U2791 ( .A(n2011), .Y(n2015) );
AO22XLTS U2792 ( .A0(d_ff_Yn[29]), .A1(n2015), .B0(d_ff2_Y[29]), .B1(n2026),
.Y(n766) );
AO22XLTS U2793 ( .A0(n2019), .A1(d_ff2_Y[29]), .B0(n1987), .B1(
d_ff3_sh_y_out[29]), .Y(n765) );
INVX4TS U2794 ( .A(n2025), .Y(n2056) );
AO22XLTS U2795 ( .A0(d_ff_Yn[30]), .A1(n2015), .B0(d_ff2_Y[30]), .B1(n2026),
.Y(n764) );
AO22XLTS U2796 ( .A0(n2047), .A1(d_ff2_Y[30]), .B0(n1987), .B1(
d_ff3_sh_y_out[30]), .Y(n763) );
AO22XLTS U2797 ( .A0(d_ff_Yn[31]), .A1(n2015), .B0(d_ff2_Y[31]), .B1(n1696),
.Y(n762) );
AO22XLTS U2798 ( .A0(n2019), .A1(d_ff2_Y[31]), .B0(n1987), .B1(
d_ff3_sh_y_out[31]), .Y(n761) );
AO22XLTS U2799 ( .A0(d_ff_Yn[32]), .A1(n2015), .B0(d_ff2_Y[32]), .B1(n2030),
.Y(n760) );
AO22XLTS U2800 ( .A0(n2047), .A1(d_ff2_Y[32]), .B0(n1987), .B1(
d_ff3_sh_y_out[32]), .Y(n759) );
AO22XLTS U2801 ( .A0(d_ff_Yn[33]), .A1(n2015), .B0(d_ff2_Y[33]), .B1(n2030),
.Y(n758) );
AO22XLTS U2802 ( .A0(n2019), .A1(d_ff2_Y[33]), .B0(n1987), .B1(
d_ff3_sh_y_out[33]), .Y(n757) );
AO22XLTS U2803 ( .A0(d_ff_Yn[34]), .A1(n2015), .B0(d_ff2_Y[34]), .B1(n2026),
.Y(n756) );
AO22XLTS U2804 ( .A0(n2047), .A1(d_ff2_Y[34]), .B0(n1987), .B1(
d_ff3_sh_y_out[34]), .Y(n755) );
AO22XLTS U2805 ( .A0(d_ff_Yn[35]), .A1(n2015), .B0(d_ff2_Y[35]), .B1(n2026),
.Y(n754) );
AO22XLTS U2806 ( .A0(n2047), .A1(d_ff2_Y[35]), .B0(n1987), .B1(
d_ff3_sh_y_out[35]), .Y(n753) );
AO22XLTS U2807 ( .A0(d_ff_Yn[36]), .A1(n2015), .B0(d_ff2_Y[36]), .B1(n1696),
.Y(n752) );
AO22XLTS U2808 ( .A0(n2047), .A1(d_ff2_Y[36]), .B0(n1987), .B1(
d_ff3_sh_y_out[36]), .Y(n751) );
AO22XLTS U2809 ( .A0(d_ff_Yn[37]), .A1(n2015), .B0(d_ff2_Y[37]), .B1(n1696),
.Y(n750) );
AO22XLTS U2810 ( .A0(n2047), .A1(d_ff2_Y[37]), .B0(n1987), .B1(
d_ff3_sh_y_out[37]), .Y(n749) );
AO22XLTS U2811 ( .A0(d_ff_Yn[38]), .A1(n2015), .B0(d_ff2_Y[38]), .B1(n2030),
.Y(n748) );
AO22XLTS U2812 ( .A0(n2047), .A1(d_ff2_Y[38]), .B0(n1987), .B1(
d_ff3_sh_y_out[38]), .Y(n747) );
AO22XLTS U2813 ( .A0(d_ff_Yn[39]), .A1(n2015), .B0(d_ff2_Y[39]), .B1(n1696),
.Y(n746) );
AO22XLTS U2814 ( .A0(n2047), .A1(d_ff2_Y[39]), .B0(n1987), .B1(
d_ff3_sh_y_out[39]), .Y(n745) );
AO22XLTS U2815 ( .A0(d_ff_Yn[40]), .A1(n2014), .B0(d_ff2_Y[40]), .B1(n2026),
.Y(n744) );
AO22XLTS U2816 ( .A0(n2047), .A1(d_ff2_Y[40]), .B0(n1987), .B1(
d_ff3_sh_y_out[40]), .Y(n743) );
AO22XLTS U2817 ( .A0(d_ff_Yn[41]), .A1(n2057), .B0(d_ff2_Y[41]), .B1(n2030),
.Y(n742) );
AO22XLTS U2818 ( .A0(n2047), .A1(d_ff2_Y[41]), .B0(n1987), .B1(
d_ff3_sh_y_out[41]), .Y(n741) );
AO22XLTS U2819 ( .A0(d_ff_Yn[42]), .A1(n2017), .B0(d_ff2_Y[42]), .B1(n2026),
.Y(n740) );
AO22XLTS U2820 ( .A0(n2047), .A1(d_ff2_Y[42]), .B0(n1987), .B1(
d_ff3_sh_y_out[42]), .Y(n739) );
AO22XLTS U2821 ( .A0(d_ff_Yn[43]), .A1(n2015), .B0(d_ff2_Y[43]), .B1(n1693),
.Y(n738) );
AO22XLTS U2822 ( .A0(n2047), .A1(d_ff2_Y[43]), .B0(n1987), .B1(
d_ff3_sh_y_out[43]), .Y(n737) );
AO22XLTS U2823 ( .A0(d_ff_Yn[44]), .A1(n2016), .B0(d_ff2_Y[44]), .B1(n2018),
.Y(n736) );
AO22XLTS U2824 ( .A0(n2059), .A1(d_ff2_Y[44]), .B0(n1987), .B1(
d_ff3_sh_y_out[44]), .Y(n735) );
AO22XLTS U2825 ( .A0(d_ff_Yn[45]), .A1(n2029), .B0(d_ff2_Y[45]), .B1(n2018),
.Y(n734) );
AO22XLTS U2826 ( .A0(n2047), .A1(d_ff2_Y[45]), .B0(n2058), .B1(
d_ff3_sh_y_out[45]), .Y(n733) );
AO22XLTS U2827 ( .A0(d_ff_Yn[46]), .A1(n2015), .B0(d_ff2_Y[46]), .B1(n2018),
.Y(n732) );
AO22XLTS U2828 ( .A0(n2059), .A1(d_ff2_Y[46]), .B0(n2058), .B1(
d_ff3_sh_y_out[46]), .Y(n731) );
AO22XLTS U2829 ( .A0(d_ff_Yn[47]), .A1(n2016), .B0(d_ff2_Y[47]), .B1(n2018),
.Y(n730) );
AO22XLTS U2830 ( .A0(n2047), .A1(d_ff2_Y[47]), .B0(n2058), .B1(
d_ff3_sh_y_out[47]), .Y(n729) );
AO22XLTS U2831 ( .A0(d_ff_Yn[48]), .A1(n2029), .B0(d_ff2_Y[48]), .B1(n2018),
.Y(n728) );
AO22XLTS U2832 ( .A0(n2059), .A1(d_ff2_Y[48]), .B0(n2058), .B1(
d_ff3_sh_y_out[48]), .Y(n727) );
AO22XLTS U2833 ( .A0(d_ff_Yn[49]), .A1(n2015), .B0(d_ff2_Y[49]), .B1(n2018),
.Y(n726) );
AO22XLTS U2834 ( .A0(n2059), .A1(d_ff2_Y[49]), .B0(n2043), .B1(
d_ff3_sh_y_out[49]), .Y(n725) );
AO22XLTS U2835 ( .A0(d_ff_Yn[50]), .A1(n2029), .B0(d_ff2_Y[50]), .B1(n2018),
.Y(n724) );
AO22XLTS U2836 ( .A0(n2059), .A1(d_ff2_Y[50]), .B0(n2058), .B1(
d_ff3_sh_y_out[50]), .Y(n723) );
AO22XLTS U2837 ( .A0(d_ff_Yn[51]), .A1(n2029), .B0(d_ff2_Y[51]), .B1(n2018),
.Y(n722) );
AO22XLTS U2838 ( .A0(n2059), .A1(d_ff2_Y[51]), .B0(n2058), .B1(
d_ff3_sh_y_out[51]), .Y(n721) );
OAI22X1TS U2839 ( .A0(n1500), .A1(n2061), .B0(n2188), .B1(n2022), .Y(n720)
);
OAI22X1TS U2840 ( .A0(n1500), .A1(n2198), .B0(n2189), .B1(n2022), .Y(n719)
);
AO22XLTS U2841 ( .A0(d_ff_Yn[54]), .A1(n2015), .B0(d_ff2_Y[54]), .B1(n2018),
.Y(n718) );
OAI22X1TS U2842 ( .A0(n2027), .A1(n2060), .B0(n2190), .B1(n2022), .Y(n717)
);
OAI22X1TS U2843 ( .A0(n1500), .A1(n2199), .B0(n2191), .B1(n2022), .Y(n716)
);
OAI22X1TS U2844 ( .A0(n1500), .A1(n2062), .B0(n2192), .B1(n2010), .Y(n715)
);
OAI22X1TS U2845 ( .A0(n1500), .A1(n2200), .B0(n2193), .B1(n2011), .Y(n714)
);
OAI22X1TS U2846 ( .A0(n2027), .A1(n2063), .B0(n2194), .B1(n2011), .Y(n713)
);
OAI22X1TS U2847 ( .A0(n2027), .A1(n2201), .B0(n2195), .B1(n2011), .Y(n712)
);
OAI22X1TS U2848 ( .A0(n1500), .A1(n2064), .B0(n2196), .B1(n2011), .Y(n711)
);
OAI22X1TS U2849 ( .A0(n2027), .A1(n2065), .B0(n2197), .B1(n2022), .Y(n710)
);
AOI21X1TS U2850 ( .A0(d_ff2_Y[52]), .A1(n1485), .B0(n1990), .Y(n1988) );
AOI2BB2XLTS U2851 ( .B0(n2052), .B1(n1988), .A0N(d_ff3_sh_y_out[52]), .A1N(
n2039), .Y(n709) );
AOI22X1TS U2852 ( .A0(cont_iter_out[1]), .A1(n2198), .B0(d_ff2_Y[53]), .B1(
n1480), .Y(n1989) );
XNOR2X1TS U2853 ( .A(n1990), .B(n1989), .Y(n1991) );
AO22XLTS U2854 ( .A0(n2059), .A1(n1991), .B0(n2058), .B1(d_ff3_sh_y_out[53]),
.Y(n708) );
AO22XLTS U2855 ( .A0(n2059), .A1(n1993), .B0(n2058), .B1(d_ff3_sh_y_out[54]),
.Y(n707) );
AOI22X1TS U2856 ( .A0(n1995), .A1(d_ff2_Y[55]), .B0(n1475), .B1(n1994), .Y(
n1996) );
NAND2X1TS U2857 ( .A(n1996), .B(n2199), .Y(n1998) );
OAI21XLTS U2858 ( .A0(n1996), .A1(n2199), .B0(n1998), .Y(n1997) );
AO22XLTS U2859 ( .A0(n2059), .A1(n1997), .B0(n2009), .B1(d_ff3_sh_y_out[56]),
.Y(n705) );
AOI21X1TS U2860 ( .A0(d_ff2_Y[57]), .A1(n1998), .B0(n2000), .Y(n1999) );
AOI2BB2XLTS U2861 ( .B0(n2041), .B1(n1999), .A0N(d_ff3_sh_y_out[57]), .A1N(
n2039), .Y(n704) );
NAND2X1TS U2862 ( .A(n2000), .B(n2200), .Y(n2002) );
OAI21XLTS U2863 ( .A0(n2000), .A1(n2200), .B0(n2002), .Y(n2001) );
AO22XLTS U2864 ( .A0(n2059), .A1(n2001), .B0(n2009), .B1(d_ff3_sh_y_out[58]),
.Y(n703) );
AOI21X1TS U2865 ( .A0(d_ff2_Y[59]), .A1(n2002), .B0(n1484), .Y(n2003) );
AOI2BB2XLTS U2866 ( .B0(n2047), .B1(n2003), .A0N(d_ff3_sh_y_out[59]), .A1N(
n2039), .Y(n702) );
NAND2X1TS U2867 ( .A(n1484), .B(n2201), .Y(n2005) );
AO22XLTS U2868 ( .A0(n2039), .A1(n2004), .B0(n2009), .B1(d_ff3_sh_y_out[60]),
.Y(n701) );
NOR2X1TS U2869 ( .A(d_ff2_Y[61]), .B(n2005), .Y(n2007) );
AOI21X1TS U2870 ( .A0(d_ff2_Y[61]), .A1(n2005), .B0(n2007), .Y(n2006) );
AOI2BB2XLTS U2871 ( .B0(n2041), .B1(n2006), .A0N(d_ff3_sh_y_out[61]), .A1N(
n2039), .Y(n700) );
XOR2XLTS U2872 ( .A(d_ff2_Y[62]), .B(n2007), .Y(n2008) );
AO22XLTS U2873 ( .A0(n2055), .A1(n2008), .B0(n2009), .B1(d_ff3_sh_y_out[62]),
.Y(n699) );
AO22XLTS U2874 ( .A0(d_ff_Yn[63]), .A1(n2015), .B0(d_ff2_Y[63]), .B1(n2018),
.Y(n698) );
AO22XLTS U2875 ( .A0(n2041), .A1(d_ff2_Y[63]), .B0(n2009), .B1(
d_ff3_sh_y_out[63]), .Y(n697) );
OA22X1TS U2876 ( .A0(n1500), .A1(d_ff2_X[0]), .B0(d_ff_Xn[0]), .B1(n2022),
.Y(n696) );
AO22XLTS U2877 ( .A0(n2055), .A1(d_ff2_X[0]), .B0(n2009), .B1(
d_ff3_sh_x_out[0]), .Y(n695) );
AO22XLTS U2878 ( .A0(d_ff_Xn[1]), .A1(n2016), .B0(d_ff2_X[1]), .B1(n2018),
.Y(n694) );
AO22XLTS U2879 ( .A0(n2041), .A1(d_ff2_X[1]), .B0(n2009), .B1(
d_ff3_sh_x_out[1]), .Y(n693) );
AO22XLTS U2880 ( .A0(d_ff_Xn[2]), .A1(n2015), .B0(d_ff2_X[2]), .B1(n2018),
.Y(n692) );
AO22XLTS U2881 ( .A0(n2055), .A1(d_ff2_X[2]), .B0(n2009), .B1(
d_ff3_sh_x_out[2]), .Y(n691) );
OA22X1TS U2882 ( .A0(n1500), .A1(d_ff2_X[3]), .B0(d_ff_Xn[3]), .B1(n2022),
.Y(n690) );
AO22XLTS U2883 ( .A0(n2055), .A1(d_ff2_X[3]), .B0(n2009), .B1(
d_ff3_sh_x_out[3]), .Y(n689) );
AO22XLTS U2884 ( .A0(d_ff_Xn[4]), .A1(n2016), .B0(d_ff2_X[4]), .B1(n2018),
.Y(n688) );
AO22XLTS U2885 ( .A0(n2055), .A1(d_ff2_X[4]), .B0(n2009), .B1(
d_ff3_sh_x_out[4]), .Y(n687) );
AO22XLTS U2886 ( .A0(d_ff_Xn[5]), .A1(n2057), .B0(d_ff2_X[5]), .B1(n2018),
.Y(n686) );
AO22XLTS U2887 ( .A0(n2055), .A1(d_ff2_X[5]), .B0(n2009), .B1(
d_ff3_sh_x_out[5]), .Y(n685) );
OA22X1TS U2888 ( .A0(n2023), .A1(d_ff2_X[6]), .B0(d_ff_Xn[6]), .B1(n2028),
.Y(n684) );
AO22XLTS U2889 ( .A0(n2055), .A1(d_ff2_X[6]), .B0(n2012), .B1(
d_ff3_sh_x_out[6]), .Y(n683) );
OA22X1TS U2890 ( .A0(n2023), .A1(d_ff2_X[7]), .B0(d_ff_Xn[7]), .B1(n2022),
.Y(n682) );
AO22XLTS U2891 ( .A0(n2055), .A1(d_ff2_X[7]), .B0(n2012), .B1(
d_ff3_sh_x_out[7]), .Y(n681) );
OA22X1TS U2892 ( .A0(n2023), .A1(d_ff2_X[8]), .B0(d_ff_Xn[8]), .B1(n2022),
.Y(n680) );
AO22XLTS U2893 ( .A0(n2039), .A1(d_ff2_X[8]), .B0(n2012), .B1(
d_ff3_sh_x_out[8]), .Y(n679) );
OA22X1TS U2894 ( .A0(n2023), .A1(d_ff2_X[9]), .B0(d_ff_Xn[9]), .B1(n2010),
.Y(n678) );
AO22XLTS U2895 ( .A0(n2055), .A1(d_ff2_X[9]), .B0(n2012), .B1(
d_ff3_sh_x_out[9]), .Y(n677) );
AO22XLTS U2896 ( .A0(d_ff_Xn[10]), .A1(n2013), .B0(d_ff2_X[10]), .B1(n1696),
.Y(n676) );
AO22XLTS U2897 ( .A0(n2055), .A1(d_ff2_X[10]), .B0(n2012), .B1(
d_ff3_sh_x_out[10]), .Y(n675) );
OA22X1TS U2898 ( .A0(n2023), .A1(d_ff2_X[11]), .B0(d_ff_Xn[11]), .B1(n2010),
.Y(n674) );
AO22XLTS U2899 ( .A0(n2055), .A1(d_ff2_X[11]), .B0(n2012), .B1(
d_ff3_sh_x_out[11]), .Y(n673) );
AO22XLTS U2900 ( .A0(d_ff_Xn[12]), .A1(n2057), .B0(d_ff2_X[12]), .B1(n2018),
.Y(n672) );
AO22XLTS U2901 ( .A0(n1952), .A1(d_ff2_X[12]), .B0(n2012), .B1(
d_ff3_sh_x_out[12]), .Y(n671) );
OA22X1TS U2902 ( .A0(n2023), .A1(d_ff2_X[13]), .B0(d_ff_Xn[13]), .B1(n2011),
.Y(n670) );
AO22XLTS U2903 ( .A0(n2039), .A1(d_ff2_X[13]), .B0(n2012), .B1(
d_ff3_sh_x_out[13]), .Y(n669) );
OA22X1TS U2904 ( .A0(n2023), .A1(d_ff2_X[14]), .B0(d_ff_Xn[14]), .B1(n2028),
.Y(n668) );
AO22XLTS U2905 ( .A0(n1952), .A1(d_ff2_X[14]), .B0(n2012), .B1(
d_ff3_sh_x_out[14]), .Y(n667) );
AO22XLTS U2906 ( .A0(d_ff_Xn[15]), .A1(n2013), .B0(d_ff2_X[15]), .B1(n2030),
.Y(n666) );
AO22XLTS U2907 ( .A0(n2039), .A1(d_ff2_X[15]), .B0(n2012), .B1(
d_ff3_sh_x_out[15]), .Y(n665) );
AO22XLTS U2908 ( .A0(d_ff_Xn[16]), .A1(n2057), .B0(d_ff2_X[16]), .B1(n2018),
.Y(n664) );
AO22XLTS U2909 ( .A0(n2039), .A1(d_ff2_X[16]), .B0(n2012), .B1(
d_ff3_sh_x_out[16]), .Y(n663) );
AO22XLTS U2910 ( .A0(d_ff_Xn[17]), .A1(n2013), .B0(d_ff2_X[17]), .B1(n2026),
.Y(n662) );
AO22XLTS U2911 ( .A0(n2039), .A1(d_ff2_X[17]), .B0(n2043), .B1(
d_ff3_sh_x_out[17]), .Y(n661) );
AO22XLTS U2912 ( .A0(d_ff_Xn[18]), .A1(n2013), .B0(d_ff2_X[18]), .B1(n2018),
.Y(n660) );
AO22XLTS U2913 ( .A0(n2059), .A1(d_ff2_X[18]), .B0(n1478), .B1(
d_ff3_sh_x_out[18]), .Y(n659) );
OA22X1TS U2914 ( .A0(n2023), .A1(d_ff2_X[19]), .B0(d_ff_Xn[19]), .B1(n2028),
.Y(n658) );
BUFX4TS U2915 ( .A(n2043), .Y(n2020) );
AO22XLTS U2916 ( .A0(n2047), .A1(d_ff2_X[19]), .B0(n2020), .B1(
d_ff3_sh_x_out[19]), .Y(n657) );
AO22XLTS U2917 ( .A0(d_ff_Xn[20]), .A1(n2014), .B0(d_ff2_X[20]), .B1(n1696),
.Y(n656) );
AO22XLTS U2918 ( .A0(n2059), .A1(d_ff2_X[20]), .B0(n2043), .B1(
d_ff3_sh_x_out[20]), .Y(n655) );
AO22XLTS U2919 ( .A0(d_ff_Xn[21]), .A1(n2017), .B0(d_ff2_X[21]), .B1(n2018),
.Y(n654) );
AO22XLTS U2920 ( .A0(n2047), .A1(d_ff2_X[21]), .B0(n2020), .B1(
d_ff3_sh_x_out[21]), .Y(n653) );
AO22XLTS U2921 ( .A0(d_ff_Xn[22]), .A1(n2014), .B0(d_ff2_X[22]), .B1(n2030),
.Y(n652) );
AO22XLTS U2922 ( .A0(n2041), .A1(d_ff2_X[22]), .B0(n2020), .B1(
d_ff3_sh_x_out[22]), .Y(n651) );
AO22XLTS U2923 ( .A0(d_ff_Xn[23]), .A1(n2015), .B0(d_ff2_X[23]), .B1(n2018),
.Y(n650) );
AO22XLTS U2924 ( .A0(n2052), .A1(d_ff2_X[23]), .B0(n2020), .B1(
d_ff3_sh_x_out[23]), .Y(n649) );
OA22X1TS U2925 ( .A0(n2023), .A1(d_ff2_X[24]), .B0(d_ff_Xn[24]), .B1(n2028),
.Y(n648) );
AO22XLTS U2926 ( .A0(n2052), .A1(d_ff2_X[24]), .B0(n2020), .B1(
d_ff3_sh_x_out[24]), .Y(n647) );
AO22XLTS U2927 ( .A0(d_ff_Xn[25]), .A1(n2016), .B0(d_ff2_X[25]), .B1(n2026),
.Y(n646) );
AO22XLTS U2928 ( .A0(n2052), .A1(d_ff2_X[25]), .B0(n2020), .B1(
d_ff3_sh_x_out[25]), .Y(n645) );
OA22X1TS U2929 ( .A0(n2023), .A1(d_ff2_X[26]), .B0(d_ff_Xn[26]), .B1(n2028),
.Y(n644) );
AO22XLTS U2930 ( .A0(n2052), .A1(d_ff2_X[26]), .B0(n2020), .B1(
d_ff3_sh_x_out[26]), .Y(n643) );
AO22XLTS U2931 ( .A0(d_ff_Xn[27]), .A1(n2029), .B0(d_ff2_X[27]), .B1(n2018),
.Y(n642) );
AO22XLTS U2932 ( .A0(n2052), .A1(d_ff2_X[27]), .B0(n2020), .B1(
d_ff3_sh_x_out[27]), .Y(n641) );
OA22X1TS U2933 ( .A0(n2023), .A1(d_ff2_X[28]), .B0(d_ff_Xn[28]), .B1(n2028),
.Y(n640) );
AO22XLTS U2934 ( .A0(n2052), .A1(d_ff2_X[28]), .B0(n2020), .B1(
d_ff3_sh_x_out[28]), .Y(n639) );
OA22X1TS U2935 ( .A0(n2023), .A1(d_ff2_X[29]), .B0(d_ff_Xn[29]), .B1(n2028),
.Y(n638) );
AO22XLTS U2936 ( .A0(n2059), .A1(d_ff2_X[29]), .B0(n2020), .B1(
d_ff3_sh_x_out[29]), .Y(n637) );
AO22XLTS U2937 ( .A0(d_ff_Xn[30]), .A1(n2029), .B0(d_ff2_X[30]), .B1(n2030),
.Y(n636) );
AO22XLTS U2938 ( .A0(n2055), .A1(d_ff2_X[30]), .B0(n2020), .B1(
d_ff3_sh_x_out[30]), .Y(n635) );
OA22X1TS U2939 ( .A0(n2023), .A1(d_ff2_X[31]), .B0(d_ff_Xn[31]), .B1(n2028),
.Y(n634) );
AO22XLTS U2940 ( .A0(n2052), .A1(d_ff2_X[31]), .B0(n2020), .B1(
d_ff3_sh_x_out[31]), .Y(n633) );
OA22X1TS U2941 ( .A0(n2023), .A1(d_ff2_X[32]), .B0(d_ff_Xn[32]), .B1(n2028),
.Y(n632) );
AO22XLTS U2942 ( .A0(n2055), .A1(d_ff2_X[32]), .B0(n2020), .B1(
d_ff3_sh_x_out[32]), .Y(n631) );
AO22XLTS U2943 ( .A0(d_ff_Xn[33]), .A1(n2029), .B0(d_ff2_X[33]), .B1(n2056),
.Y(n630) );
AO22XLTS U2944 ( .A0(n2019), .A1(d_ff2_X[33]), .B0(n2020), .B1(
d_ff3_sh_x_out[33]), .Y(n629) );
AO22XLTS U2945 ( .A0(n2047), .A1(d_ff2_X[34]), .B0(n2020), .B1(
d_ff3_sh_x_out[34]), .Y(n627) );
AO22XLTS U2946 ( .A0(n2059), .A1(d_ff2_X[35]), .B0(n2020), .B1(
d_ff3_sh_x_out[35]), .Y(n625) );
OA22X1TS U2947 ( .A0(n2023), .A1(d_ff2_X[36]), .B0(d_ff_Xn[36]), .B1(n2022),
.Y(n624) );
AO22XLTS U2948 ( .A0(n2019), .A1(d_ff2_X[36]), .B0(n2020), .B1(
d_ff3_sh_x_out[36]), .Y(n623) );
AO22XLTS U2949 ( .A0(d_ff_Xn[37]), .A1(n2017), .B0(d_ff2_X[37]), .B1(n2056),
.Y(n622) );
AO22XLTS U2950 ( .A0(n2019), .A1(d_ff2_X[37]), .B0(n2020), .B1(
d_ff3_sh_x_out[37]), .Y(n621) );
AO22XLTS U2951 ( .A0(d_ff_Xn[38]), .A1(n2029), .B0(d_ff2_X[38]), .B1(n2056),
.Y(n620) );
AO22XLTS U2952 ( .A0(n2047), .A1(d_ff2_X[38]), .B0(n2020), .B1(
d_ff3_sh_x_out[38]), .Y(n619) );
AO22XLTS U2953 ( .A0(n2059), .A1(d_ff2_X[39]), .B0(n2043), .B1(
d_ff3_sh_x_out[39]), .Y(n617) );
AO22XLTS U2954 ( .A0(d_ff_Xn[40]), .A1(n2029), .B0(d_ff2_X[40]), .B1(n2056),
.Y(n616) );
AO22XLTS U2955 ( .A0(n2039), .A1(d_ff2_X[40]), .B0(n2043), .B1(
d_ff3_sh_x_out[40]), .Y(n615) );
AO22XLTS U2956 ( .A0(n2059), .A1(d_ff2_X[41]), .B0(n2043), .B1(
d_ff3_sh_x_out[41]), .Y(n613) );
AO22XLTS U2957 ( .A0(n2047), .A1(d_ff2_X[42]), .B0(n2043), .B1(
d_ff3_sh_x_out[42]), .Y(n611) );
AO22XLTS U2958 ( .A0(n2059), .A1(d_ff2_X[43]), .B0(n2043), .B1(
d_ff3_sh_x_out[43]), .Y(n609) );
AO22XLTS U2959 ( .A0(d_ff_Xn[44]), .A1(n2029), .B0(d_ff2_X[44]), .B1(n2018),
.Y(n608) );
AO22XLTS U2960 ( .A0(n1952), .A1(d_ff2_X[44]), .B0(n2043), .B1(
d_ff3_sh_x_out[44]), .Y(n607) );
AO22XLTS U2961 ( .A0(n2019), .A1(d_ff2_X[45]), .B0(n2043), .B1(
d_ff3_sh_x_out[45]), .Y(n605) );
AO22XLTS U2962 ( .A0(n2047), .A1(d_ff2_X[46]), .B0(n2021), .B1(
d_ff3_sh_x_out[46]), .Y(n603) );
AO22XLTS U2963 ( .A0(d_ff_Xn[47]), .A1(n2029), .B0(d_ff2_X[47]), .B1(n2056),
.Y(n602) );
AO22XLTS U2964 ( .A0(n2059), .A1(d_ff2_X[47]), .B0(n2021), .B1(
d_ff3_sh_x_out[47]), .Y(n601) );
AO22XLTS U2965 ( .A0(n2047), .A1(d_ff2_X[48]), .B0(n2020), .B1(
d_ff3_sh_x_out[48]), .Y(n599) );
OA22X1TS U2966 ( .A0(n2027), .A1(d_ff2_X[49]), .B0(d_ff_Xn[49]), .B1(n2022),
.Y(n598) );
AO22XLTS U2967 ( .A0(n2039), .A1(d_ff2_X[49]), .B0(n2021), .B1(
d_ff3_sh_x_out[49]), .Y(n597) );
AO22XLTS U2968 ( .A0(d_ff_Xn[50]), .A1(n2029), .B0(d_ff2_X[50]), .B1(n2056),
.Y(n596) );
AO22XLTS U2969 ( .A0(n2059), .A1(d_ff2_X[50]), .B0(n1479), .B1(
d_ff3_sh_x_out[50]), .Y(n595) );
AO22XLTS U2970 ( .A0(d_ff_Xn[51]), .A1(n2029), .B0(d_ff2_X[51]), .B1(n2056),
.Y(n594) );
AO22XLTS U2971 ( .A0(n2059), .A1(d_ff2_X[51]), .B0(n2021), .B1(
d_ff3_sh_x_out[51]), .Y(n593) );
AO22XLTS U2972 ( .A0(d_ff_Xn[52]), .A1(n2029), .B0(d_ff2_X[52]), .B1(n1670),
.Y(n592) );
OA22X1TS U2973 ( .A0(n2025), .A1(d_ff2_X[53]), .B0(d_ff_Xn[53]), .B1(n2022),
.Y(n591) );
OA22X1TS U2974 ( .A0(d_ff_Xn[55]), .A1(n2028), .B0(d_ff2_X[55]), .B1(n2023),
.Y(n589) );
AOI2BB2XLTS U2975 ( .B0(n2202), .B1(n1670), .A0N(d_ff_Xn[56]), .A1N(n2010),
.Y(n588) );
OA22X1TS U2976 ( .A0(d_ff_Xn[57]), .A1(n2010), .B0(d_ff2_X[57]), .B1(n2027),
.Y(n587) );
AOI2BB2XLTS U2977 ( .B0(n2203), .B1(n1687), .A0N(d_ff_Xn[58]), .A1N(n2010),
.Y(n586) );
OA22X1TS U2978 ( .A0(d_ff_Xn[59]), .A1(n2011), .B0(d_ff2_X[59]), .B1(n2025),
.Y(n585) );
AOI2BB2XLTS U2979 ( .B0(n2204), .B1(n1693), .A0N(d_ff_Xn[60]), .A1N(n2010),
.Y(n584) );
OA22X1TS U2980 ( .A0(d_ff_Xn[61]), .A1(n2028), .B0(d_ff2_X[61]), .B1(n2027),
.Y(n583) );
AO22XLTS U2981 ( .A0(d_ff2_X[62]), .A1(n2056), .B0(d_ff_Xn[62]), .B1(n2029),
.Y(n582) );
AOI21X1TS U2982 ( .A0(d_ff2_X[52]), .A1(n1485), .B0(n2031), .Y(n2032) );
AOI2BB2XLTS U2983 ( .B0(n2041), .B1(n2032), .A0N(d_ff3_sh_x_out[52]), .A1N(
n2039), .Y(n581) );
OAI22X1TS U2984 ( .A0(n2035), .A1(d_ff2_X[55]), .B0(n2034), .B1(n1475), .Y(
n2036) );
NAND2X1TS U2985 ( .A(n2202), .B(n2036), .Y(n2038) );
OAI21XLTS U2986 ( .A0(n2036), .A1(n2202), .B0(n2038), .Y(n2037) );
AO22XLTS U2987 ( .A0(n2059), .A1(n2037), .B0(n2043), .B1(d_ff3_sh_x_out[56]),
.Y(n577) );
AOI21X1TS U2988 ( .A0(d_ff2_X[57]), .A1(n2038), .B0(n2042), .Y(n2040) );
AOI2BB2XLTS U2989 ( .B0(n2041), .B1(n2040), .A0N(d_ff3_sh_x_out[57]), .A1N(
n2039), .Y(n576) );
NAND2X1TS U2990 ( .A(n2042), .B(n2203), .Y(n2045) );
OAI21XLTS U2991 ( .A0(n2042), .A1(n2203), .B0(n2045), .Y(n2044) );
AO22XLTS U2992 ( .A0(n2059), .A1(n2044), .B0(n2043), .B1(d_ff3_sh_x_out[58]),
.Y(n575) );
AOI21X1TS U2993 ( .A0(d_ff2_X[59]), .A1(n2045), .B0(n2048), .Y(n2046) );
AOI2BB2XLTS U2994 ( .B0(n2047), .B1(n2046), .A0N(d_ff3_sh_x_out[59]), .A1N(
n2052), .Y(n574) );
NAND2X1TS U2995 ( .A(n2048), .B(n2204), .Y(n2050) );
AO22XLTS U2996 ( .A0(n2059), .A1(n2049), .B0(n2058), .B1(d_ff3_sh_x_out[60]),
.Y(n573) );
NOR2X1TS U2997 ( .A(d_ff2_X[61]), .B(n2050), .Y(n2053) );
AOI21X1TS U2998 ( .A0(d_ff2_X[61]), .A1(n2050), .B0(n2053), .Y(n2051) );
AOI2BB2XLTS U2999 ( .B0(n2052), .B1(n2051), .A0N(d_ff3_sh_x_out[61]), .A1N(
n2052), .Y(n572) );
XOR2XLTS U3000 ( .A(d_ff2_X[62]), .B(n2053), .Y(n2054) );
AO22XLTS U3001 ( .A0(n2055), .A1(n2054), .B0(n2058), .B1(d_ff3_sh_x_out[62]),
.Y(n571) );
AO22XLTS U3002 ( .A0(d_ff_Xn[63]), .A1(n2057), .B0(d_ff2_X[63]), .B1(n1696),
.Y(n570) );
AO22XLTS U3003 ( .A0(n2059), .A1(d_ff2_X[63]), .B0(n2058), .B1(
d_ff3_sh_x_out[63]), .Y(n569) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk40.tcl_syn.sdf");
endmodule
|
//======================================================================
//
// chacha_poly1305.v
// -----------------
// Top level wrapper for ChaCha20-Poly1305 AEAD cipher core.
//
//
// Copyright (c) 2016, Secworks Sweden AB
// Joachim Strömbergson
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module chacha20_poly1305(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam CTRL_DONE_BIT = 2;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam STATUS_VALID_BIT = 1;
localparam STATUS_TAG_OK_BIT = 2;
localparam ADDR_CONFIG = 8'h0a;
localparam CONFIG_ENCDEC_BIT = 0;
localparam ADDR_KEY0 = 8'h10;
localparam ADDR_KEY7 = 8'h17;
localparam ADDR_NONCE0 = 8'h20;
localparam ADDR_NONCE2 = 8'h22;
localparam ADDR_DATA0 = 8'h30;
localparam ADDR_DATA15 = 8'h3f;
localparam ADDR_TAG0 = 8'h40;
localparam ADDR_TAG3 = 8'h43;
localparam CORE_NAME0 = 32'h63323070; // "c20p"
localparam CORE_NAME1 = 32'h31333035; // "1305"
localparam CORE_VERSION = 32'h302e3031; // "1.01"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg done_reg;
reg done_new;
reg encdec_reg;
reg encdec_we;
reg [31 : 0] init_ctr_reg[0 : 1];
reg init_ctr_we;
reg [31 : 0] key_reg [0 : 7];
reg key_we;
reg [31 : 0] nonce_reg [0 : 2];
reg nonce_we;
reg [31 : 0] data_reg [0 : 15];
reg data_we;
reg [4 : 0] rounds_reg;
reg rounds_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
wire core_ready;
wire core_valid;
wire core_tag_ok;
wire [255 : 0] core_key;
wire [095 : 0] core_nonce;
wire [511 : 0] core_data_in;
wire [511 : 0] core_data_out;
wire [127 : 0] core_tag;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
assign core_nonce = {nonce_reg[0], nonce_reg[1]};
assign core_data_in = {data_reg[00], data_reg[01], data_reg[02], data_reg[03],
data_reg[04], data_reg[05], data_reg[06], data_reg[07],
data_reg[08], data_reg[09], data_reg[10], data_reg[11],
data_reg[12], data_reg[13], data_reg[14], data_reg[15]};
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
chacha20_poly1305_core core(
.clk(clk),
.reset_n(reset_n),
.init(init_reg),
.next(next_reg),
.done(done_reg),
.encdec(encdec_reg),
.key(core_key),
.nonce(core_nonce),
.data_in(core_data_in),
.ready(core_ready),
.valid(core_valid),
.tag_ok(core_tag_ok),
.data_out(core_data_out),
.tag(core_tag)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
integer i;
if (!reset_n)
begin
init_reg <= 0;
next_reg <= 0;
done_reg <= 0;
encdec_reg <= 0;
init_ctr_reg[0] <= 32'h0;
init_ctr_reg[1] <= 32'h0;
nonce_reg[0] <= 32'h0;
nonce_reg[1] <= 32'h0;
nonce_reg[2] <= 32'h0;
for (i = 0 ; i < 8 ; i = i + 1)
begin
key_reg[i] <= 32'h0;
data_reg[i] <= 32'h0;
data_reg[(i + 8)] <= 32'h0;
end
end
else
begin
init_reg <= init_new;
next_reg <= next_new;
done_reg <= done_new;
if (encdec_we)
encdec_reg <= write_data[0];
if (init_ctr_we)
init_ctr_reg[address[0]] <= write_data;
if (key_we)
key_reg[address[2 : 0]] <= write_data;
if (nonce_we)
nonce_reg[address[1 : 0]] <= write_data;
if (data_we)
data_reg[address[3 : 0]] <= write_data;
end
end // reg_update
//----------------------------------------------------------------
// Address decoder logic.
//----------------------------------------------------------------
always @*
begin : addr_decoder
init_new = 0;
next_new = 0;
done_new = 0;
encdec_we = 0;
key_we = 0;
nonce_we = 0;
data_we = 0;
tmp_read_data = 32'h0;
if (cs)
begin
if (we)
begin
if (address == ADDR_CTRL)
begin
init_new = write_data[CTRL_INIT_BIT];
next_new = write_data[CTRL_NEXT_BIT];
done_new = write_data[CTRL_DONE_BIT];
end
if (address == ADDR_CONFIG)
begin
encdec_we = 1;
end
if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
key_we = 1;
if ((address >= ADDR_NONCE0) && (address <= ADDR_NONCE2))
nonce_we = 1;
if ((address >= ADDR_DATA0) && (address <= ADDR_DATA15))
data_we = 1;
end
else
begin
if (address == ADDR_NAME0)
tmp_read_data = CORE_NAME0;
if (address == ADDR_NAME1)
tmp_read_data = CORE_NAME1;
if (address == ADDR_VERSION)
tmp_read_data = CORE_VERSION;
if (address == ADDR_STATUS)
tmp_read_data = {29'h0, core_tag_ok, core_valid, core_ready};
if (address == ADDR_CONFIG)
tmp_read_data = {31'h0, encdec_reg};
if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
tmp_read_data = key_reg[address[2 : 0]];
if ((address >= ADDR_NONCE0) && (address <= ADDR_NONCE2))
tmp_read_data = nonce_reg[address[2 : 0]];
if ((address >= ADDR_DATA0) && (address <= ADDR_DATA15))
tmp_read_data = core_data_out[(15 - (address - ADDR_DATA0)) * 32 +: 32];
if ((address >= ADDR_TAG0) && (address <= ADDR_TAG3))
tmp_read_data = core_tag[(3 - (address - ADDR_TAG0)) * 32 +: 32];
end
end
end // addr_decoder
endmodule // chacha_poly1305
//======================================================================
// EOF chacha_poly1305.v
//======================================================================
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
module m26_rx_ch
(
input wire RST,
input wire CLK_RX,
input wire MKD_RX,
input wire DATA_RX,
output wire WRITE, FRAME_START,
output wire [15:0] DATA
);
reg [15:0] mkd_sr;
always@(posedge CLK_RX)
mkd_sr[15:0] <= {mkd_sr[14:0], MKD_RX};
reg [15:0] data_sr;
always@(posedge CLK_RX)
data_sr[15:0] <= {DATA_RX, data_sr[15:1]};
assign FRAME_START = (mkd_sr[15:12] == 4'b1111);
reg [15:0] data_cnt;
always@(posedge CLK_RX)
if(RST)
data_cnt <= 16'hffff;
else if(FRAME_START)
data_cnt <= 0;
else if(data_cnt != 16'hffff)
data_cnt <= data_cnt + 1;
reg [15:0] data_len;
always@(posedge CLK_RX)
if(RST)
data_len <= 0;
else if(data_cnt==31)
data_len <= data_sr;
assign WRITE = FRAME_START | data_cnt == 15 | data_cnt == 31 | ((data_cnt + 1) % 16 == 0 && data_cnt / 16 < data_len + 3);
assign DATA = data_sr;
endmodule
|
// File : ../RTL/slaveController/slaveGetpacket.v
// Generated : 11/10/06 05:37:25
// From : ../RTL/slaveController/slaveGetpacket.asf
// By : FSM2VHDL ver. 5.0.0.9
//////////////////////////////////////////////////////////////////////
//// ////
//// slaveGetPacket
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
module slaveGetPacket (ACKRxed, CRCError, RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXOverflow, RXPacketRdy, RXStreamStatusIn, RXTimeOut, RxPID, SIERxTimeOut, SIERxTimeOutEn, bitStuffError, clk, dataSequence, endPointReady, getPacketEn, rst);
input [7:0] RXDataIn;
input RXDataValid;
input RXFifoFull;
input [7:0] RXStreamStatusIn;
input SIERxTimeOut; // Single cycle pulse
input clk;
input endPointReady;
input getPacketEn;
input rst;
output ACKRxed;
output CRCError;
output [7:0] RXFifoData;
output RXFifoWEn;
output RXOverflow;
output RXPacketRdy;
output RXTimeOut;
output [3:0] RxPID;
output SIERxTimeOutEn;
output bitStuffError;
output dataSequence;
reg ACKRxed, next_ACKRxed;
reg CRCError, next_CRCError;
wire [7:0] RXDataIn;
wire RXDataValid;
reg [7:0] RXFifoData, next_RXFifoData;
wire RXFifoFull;
reg RXFifoWEn, next_RXFifoWEn;
reg RXOverflow, next_RXOverflow;
reg RXPacketRdy, next_RXPacketRdy;
wire [7:0] RXStreamStatusIn;
reg RXTimeOut, next_RXTimeOut;
reg [3:0] RxPID, next_RxPID;
wire SIERxTimeOut;
reg SIERxTimeOutEn, next_SIERxTimeOutEn;
reg bitStuffError, next_bitStuffError;
wire clk;
reg dataSequence, next_dataSequence;
wire endPointReady;
wire getPacketEn;
wire rst;
// diagram signals declarations
reg [7:0]RXByteOld, next_RXByteOld;
reg [7:0]RXByteOldest, next_RXByteOldest;
reg [7:0]RXByte, next_RXByte;
reg [7:0]RXStreamStatus, next_RXStreamStatus;
// BINARY ENCODED state machine: slvGetPkt
// State codes definitions:
`define PROC_PKT_CHK_PID 5'b00000
`define PROC_PKT_HS 5'b00001
`define PROC_PKT_DATA_W_D1 5'b00010
`define PROC_PKT_DATA_CHK_D1 5'b00011
`define PROC_PKT_DATA_W_D2 5'b00100
`define PROC_PKT_DATA_FIN 5'b00101
`define PROC_PKT_DATA_CHK_D2 5'b00110
`define PROC_PKT_DATA_W_D3 5'b00111
`define PROC_PKT_DATA_CHK_D3 5'b01000
`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
`define PROC_PKT_DATA_LOOP_W_D 5'b01011
`define START_GP 5'b01100
`define WAIT_PKT 5'b01101
`define CHK_PKT_START 5'b01110
`define WAIT_EN 5'b01111
`define PKT_RDY 5'b10000
`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
`define PROC_PKT_DATA_LOOP_EP_N_RDY 5'b10010
reg [4:0] CurrState_slvGetPkt;
reg [4:0] NextState_slvGetPkt;
//--------------------------------------------------------------------
// Machine: slvGetPkt
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or RXDataValid or SIERxTimeOut or RXStreamStatus or getPacketEn or endPointReady or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or ACKRxed or dataSequence or SIERxTimeOutEn or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_slvGetPkt)
begin : slvGetPkt_NextState
NextState_slvGetPkt <= CurrState_slvGetPkt;
// Set default values for outputs and signals
next_CRCError <= CRCError;
next_bitStuffError <= bitStuffError;
next_RXOverflow <= RXOverflow;
next_RXTimeOut <= RXTimeOut;
next_ACKRxed <= ACKRxed;
next_dataSequence <= dataSequence;
next_SIERxTimeOutEn <= SIERxTimeOutEn;
next_RXByte <= RXByte;
next_RXStreamStatus <= RXStreamStatus;
next_RxPID <= RxPID;
next_RXPacketRdy <= RXPacketRdy;
next_RXByteOldest <= RXByteOldest;
next_RXByteOld <= RXByteOld;
next_RXFifoWEn <= RXFifoWEn;
next_RXFifoData <= RXFifoData;
case (CurrState_slvGetPkt)
`START_GP:
NextState_slvGetPkt <= `WAIT_EN;
`WAIT_PKT:
begin
next_CRCError <= 1'b0;
next_bitStuffError <= 1'b0;
next_RXOverflow <= 1'b0;
next_RXTimeOut <= 1'b0;
next_ACKRxed <= 1'b0;
next_dataSequence <= 1'b0;
next_SIERxTimeOutEn <= 1'b1;
if (RXDataValid == 1'b1)
begin
NextState_slvGetPkt <= `CHK_PKT_START;
next_RXByte <= RXDataIn;
next_RXStreamStatus <= RXStreamStatusIn;
end
else if (SIERxTimeOut == 1'b1)
begin
NextState_slvGetPkt <= `PKT_RDY;
next_RXTimeOut <= 1'b1;
end
end
`CHK_PKT_START:
if (RXStreamStatus == `RX_PACKET_START)
begin
NextState_slvGetPkt <= `PROC_PKT_CHK_PID;
next_RxPID <= RXByte[3:0];
end
else
begin
NextState_slvGetPkt <= `PKT_RDY;
next_RXTimeOut <= 1'b1;
end
`WAIT_EN:
begin
next_RXPacketRdy <= 1'b0;
next_SIERxTimeOutEn <= 1'b0;
if (getPacketEn == 1'b1)
NextState_slvGetPkt <= `WAIT_PKT;
end
`PKT_RDY:
begin
next_RXPacketRdy <= 1'b1;
NextState_slvGetPkt <= `WAIT_EN;
end
`PROC_PKT_CHK_PID:
if (RXByte[1:0] == `HANDSHAKE)
NextState_slvGetPkt <= `PROC_PKT_HS;
else if (RXByte[1:0] == `DATA)
NextState_slvGetPkt <= `PROC_PKT_DATA_W_D1;
else
NextState_slvGetPkt <= `PKT_RDY;
`PROC_PKT_HS:
if (RXDataValid == 1'b1)
begin
NextState_slvGetPkt <= `PKT_RDY;
next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
end
`PROC_PKT_DATA_W_D1:
if (RXDataValid == 1'b1)
begin
NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D1;
next_RXByte <= RXDataIn;
next_RXStreamStatus <= RXStreamStatusIn;
end
`PROC_PKT_DATA_CHK_D1:
if (RXStreamStatus == `RX_PACKET_STREAM)
begin
NextState_slvGetPkt <= `PROC_PKT_DATA_W_D2;
next_RXByteOldest <= RXByte;
end
else
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
`PROC_PKT_DATA_W_D2:
if (RXDataValid == 1'b1)
begin
NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D2;
next_RXByte <= RXDataIn;
next_RXStreamStatus <= RXStreamStatusIn;
end
`PROC_PKT_DATA_FIN:
begin
next_CRCError <= RXByte[`CRC_ERROR_BIT];
next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
NextState_slvGetPkt <= `PKT_RDY;
end
`PROC_PKT_DATA_CHK_D2:
if (RXStreamStatus == `RX_PACKET_STREAM)
begin
NextState_slvGetPkt <= `PROC_PKT_DATA_W_D3;
next_RXByteOld <= RXByte;
end
else
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
`PROC_PKT_DATA_W_D3:
if (RXDataValid == 1'b1)
begin
NextState_slvGetPkt <= `PROC_PKT_DATA_CHK_D3;
next_RXByte <= RXDataIn;
next_RXStreamStatus <= RXStreamStatusIn;
end
`PROC_PKT_DATA_CHK_D3:
if (RXStreamStatus == `RX_PACKET_STREAM)
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
else
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
`PROC_PKT_DATA_LOOP_CHK_FIFO:
if (endPointReady == 1'b0)
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_EP_N_RDY;
else if (RXFifoFull == 1'b1)
begin
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
next_RXOverflow <= 1'b1;
end
else
begin
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
next_RXFifoWEn <= 1'b1;
next_RXFifoData <= RXByteOldest;
next_RXByteOldest <= RXByteOld;
next_RXByteOld <= RXByte;
end
`PROC_PKT_DATA_LOOP_FIFO_FULL:
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
`PROC_PKT_DATA_LOOP_W_D:
begin
next_RXFifoWEn <= 1'b0;
if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
begin
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_DELAY;
next_RXByte <= RXDataIn;
end
else if (RXDataValid == 1'b1)
begin
NextState_slvGetPkt <= `PROC_PKT_DATA_FIN;
next_RXByte <= RXDataIn;
end
end
`PROC_PKT_DATA_LOOP_DELAY:
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
`PROC_PKT_DATA_LOOP_EP_N_RDY: // Discard data
NextState_slvGetPkt <= `PROC_PKT_DATA_LOOP_W_D;
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : slvGetPkt_CurrentState
if (rst)
CurrState_slvGetPkt <= `START_GP;
else
CurrState_slvGetPkt <= NextState_slvGetPkt;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : slvGetPkt_RegOutput
if (rst)
begin
RXByteOld <= 8'h00;
RXByteOldest <= 8'h00;
RXByte <= 8'h00;
RXStreamStatus <= 8'h00;
RXPacketRdy <= 1'b0;
RXFifoWEn <= 1'b0;
RXFifoData <= 8'h00;
CRCError <= 1'b0;
bitStuffError <= 1'b0;
RXOverflow <= 1'b0;
RXTimeOut <= 1'b0;
ACKRxed <= 1'b0;
dataSequence <= 1'b0;
SIERxTimeOutEn <= 1'b0;
RxPID <= 4'h0;
end
else
begin
RXByteOld <= next_RXByteOld;
RXByteOldest <= next_RXByteOldest;
RXByte <= next_RXByte;
RXStreamStatus <= next_RXStreamStatus;
RXPacketRdy <= next_RXPacketRdy;
RXFifoWEn <= next_RXFifoWEn;
RXFifoData <= next_RXFifoData;
CRCError <= next_CRCError;
bitStuffError <= next_bitStuffError;
RXOverflow <= next_RXOverflow;
RXTimeOut <= next_RXTimeOut;
ACKRxed <= next_ACKRxed;
dataSequence <= next_dataSequence;
SIERxTimeOutEn <= next_SIERxTimeOutEn;
RxPID <= next_RxPID;
end
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_8_V
`define SKY130_FD_SC_LP__INV_8_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_8_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRBP_1_V
`define SKY130_FD_SC_HS__DFRBP_1_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog wrapper for dfrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfrbp_1 (
RESET_B,
CLK ,
D ,
Q ,
Q_N ,
VPWR ,
VGND
);
input RESET_B;
input CLK ;
input D ;
output Q ;
output Q_N ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dfrbp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfrbp_1 (
RESET_B,
CLK ,
D ,
Q ,
Q_N
);
input RESET_B;
input CLK ;
input D ;
output Q ;
output Q_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfrbp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRBP_1_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: DE5Gen2x8If128
// Version:
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Altera Stratix V Hard IP for PCI Express
// module and the Terasic DE5 net Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "functions.vh"
`include "riffa.vh"
`include "altera.vh"
`timescale 1ps / 1ps
module DE5Gen2x8If128
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes
parameter C_NUM_LANES = 8,
// Settings from Quartus IP Library
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5
)
(
// ----------LEDs----------
output [7:0] LED,
// ----------PCIE----------
input PCIE_RESET_N,
input PCIE_REFCLK,
// ----------PCIE Serial RX----------
input [C_NUM_LANES-1:0] PCIE_RX_IN,
// ----------PCIE Serial TX----------
output [C_NUM_LANES-1:0] PCIE_TX_OUT,
// ----------Oscillators----------
input OSC_BANK3D_50MHZ
);
wire npor;
wire pin_perst;
// ----------LMI Interface----------
wire [11:0] lmi_addr;
wire [31:0] lmi_din;
wire lmi_rden;
wire lmi_wren;
wire lmi_ack;
wire [31:0] lmi_dout;
// ----------TL Config interface----------
wire [3:0] tl_cfg_add;
wire [31:0] tl_cfg_ctl;
wire [52:0] tl_cfg_sts;
// ----------Rx/TX Interfaces----------
wire [0:0] rx_st_sop;
wire [0:0] rx_st_eop;
wire [0:0] rx_st_err;
wire [0:0] rx_st_valid;
wire [0:0] rx_st_empty;
wire rx_st_ready;
wire [C_PCI_DATA_WIDTH-1:0] rx_st_data;
wire [7:0] rx_st_bar;
wire rx_st_mask;
wire [0:0] tx_st_sop;
wire [0:0] tx_st_eop;
wire [0:0] tx_st_err;
wire [0:0] tx_st_valid;
wire [0:0] tx_st_empty;
wire tx_st_ready;
wire [C_PCI_DATA_WIDTH-1:0] tx_st_data;
// ----------Clocks----------
wire pld_clk;
wire coreclkout_hip;
wire refclk;
wire pld_core_ready;
wire reset_status;
wire serdes_pll_locked;
wire pld_clk_inuse;
// ----------Reconfiguration busses----------
wire [699:0] reconfig_to_xcvr;
wire [505:0] reconfig_from_xcvr;
// ----------Interrupt Interfaces----------
wire app_int_sts;
wire [4:0] app_msi_num;
wire app_msi_req;
wire [2:0] app_msi_tc;
wire app_int_ack;
wire app_msi_ack;
// ----------Link status signals----------
wire derr_cor_ext_rcv;
wire derr_cor_ext_rpl;
wire derr_rpl;
wire dlup;
wire dlup_exit;
wire ev128ns;
wire ev1us;
wire hotrst_exit;
wire [3:0] int_status;
wire l2_exit;
wire [3:0] lane_act;
wire [4:0] ltssmstate;
wire rx_par_err;
wire [1:0] tx_par_err;
wire cfg_par_err;
wire [1:0] currentspeed;
wire [7:0] ko_cpl_spc_header;
wire [11:0] ko_cpl_spc_data;
// ----------Link Status Signals (Driver)----------
wire derr_cor_ext_rcv_drv;
wire derr_cor_ext_rpl_drv;
wire derr_rpl_drv;
wire dlup_drv;
wire dlup_exit_drv;
wire ev128ns_drv;
wire ev1us_drv;
wire hotrst_exit_drv;
wire [3:0] int_status_drv;
wire l2_exit_drv;
wire [3:0] lane_act_drv;
wire [4:0] ltssmstate_drv;
wire rx_par_err_drv;
wire [1:0] tx_par_err_drv;
wire cfg_par_err_drv;
wire [7:0] ko_cpl_spc_header_drv;
wire [11:0] ko_cpl_spc_data_drv;
// ----------Reconfiguration Controller signals----------
wire reconfig_busy;
wire mgmt_clk_clk;
wire mgmt_rst_reset;
wire [6:0] reconfig_mgmt_address;
wire reconfig_mgmt_read;
wire [31:0] reconfig_mgmt_readdata;
wire reconfig_mgmt_waitrequest;
wire reconfig_mgmt_write;
wire [31:0] reconfig_mgmt_writedata;
// ----------Reconfiguration Driver signals----------
wire reconfig_xcvr_clk;
wire reconfig_xcvr_rst;
wire [7:0] rx_in;
wire [7:0] tx_out;
// ----------Serial interfaces----------
assign rx_in = PCIE_RX_IN;
assign PCIE_TX_OUT = tx_out;
// ----------Clocks----------
assign pld_clk = coreclkout_hip;
assign mgmt_clk_clk = PCIE_REFCLK;
assign reconfig_xcvr_clk = PCIE_REFCLK;
assign refclk = PCIE_REFCLK;
assign pld_core_ready = serdes_pll_locked;
// ----------Resets----------
assign reconfig_xcvr_rst = 1'b0;
assign mgmt_rst_reset = 1'b0;
assign pin_perst = PCIE_RESET_N;
assign npor = PCIE_RESET_N;
// ----------LED's----------
assign LED[7:0] = 8'hff;
// -------------------- BEGIN ALTERA IP INSTANTIATION --------------------
// Transciever driver (Required for Gen1)
altpcie_reconfig_driver
#(.number_of_reconfig_interfaces(10),
.gen123_lane_rate_mode_hwtcl("Gen2 (5.0 Gbps)"),
.INTENDED_DEVICE_FAMILY("Stratix V"))
XCVRDriverGen2x8_inst
(
// Outputs
.reconfig_mgmt_address (reconfig_mgmt_address[6:0]),
.reconfig_mgmt_read (reconfig_mgmt_read),
.reconfig_mgmt_write (reconfig_mgmt_write),
.reconfig_mgmt_writedata (reconfig_mgmt_writedata[31:0]),
.cal_busy_in (),
// Inputs
.pld_clk (pld_clk),
.reconfig_xcvr_rst (reconfig_xcvr_rst),
.reconfig_mgmt_readdata (reconfig_mgmt_readdata[31:0]),
.reconfig_mgmt_waitrequest (reconfig_mgmt_waitrequest),
.reconfig_xcvr_clk (reconfig_xcvr_clk),
.reconfig_busy (reconfig_busy),
// Link Status signals
.derr_cor_ext_rcv_drv (derr_cor_ext_rcv_drv),
.derr_cor_ext_rpl_drv (derr_cor_ext_rpl_drv),
.derr_rpl_drv (derr_rpl_drv),
.dlup_drv (dlup_drv),
.dlup_exit_drv (dlup_exit_drv),
.ev128ns_drv (ev128ns_drv),
.ev1us_drv (ev1us_drv),
.hotrst_exit_drv (hotrst_exit_drv),
.int_status_drv (int_status_drv[3:0]),
.l2_exit_drv (l2_exit_drv),
.lane_act_drv (lane_act_drv[3:0]),
.ltssmstate_drv (ltssmstate_drv[4:0]),
.rx_par_err_drv (rx_par_err_drv),
.tx_par_err_drv (tx_par_err_drv[1:0]),
.cfg_par_err_drv (cfg_par_err_drv),
.ko_cpl_spc_header_drv (ko_cpl_spc_header_drv[7:0]),
.ko_cpl_spc_data_drv (ko_cpl_spc_data_drv[11:0]),
.currentspeed (currentspeed[1:0]));
assign derr_cor_ext_rcv_drv = derr_cor_ext_rcv;
assign derr_cor_ext_rpl_drv = derr_cor_ext_rpl;
assign derr_rpl_drv = derr_rpl;
assign dlup_drv = dlup;
assign dlup_exit_drv = dlup_exit;
assign ev128ns_drv = ev128ns;
assign ev1us_drv = ev1us;
assign hotrst_exit_drv = hotrst_exit;
assign int_status_drv = int_status;
assign l2_exit_drv = l2_exit;
assign lane_act_drv = lane_act;
assign ltssmstate_drv = ltssmstate;
assign rx_par_err_drv = rx_par_err;
assign tx_par_err_drv = tx_par_err;
assign cfg_par_err_drv = cfg_par_err;
assign ko_cpl_spc_header_drv = ko_cpl_spc_header;
assign ko_cpl_spc_data_drv = ko_cpl_spc_data;
XCVRCtrlGen2x8 XCVRCtrlGen2x8_inst
(
// Outputs
.reconfig_busy (reconfig_busy),
.reconfig_mgmt_readdata (reconfig_mgmt_readdata[31:0]),
.reconfig_mgmt_waitrequest (reconfig_mgmt_waitrequest),
.reconfig_to_xcvr (reconfig_to_xcvr[699:0]),
// Inputs
.mgmt_clk_clk (mgmt_clk_clk),
.mgmt_rst_reset (mgmt_rst_reset),
.reconfig_mgmt_address (reconfig_mgmt_address[6:0]),
.reconfig_mgmt_read (reconfig_mgmt_read),
.reconfig_mgmt_write (reconfig_mgmt_write),
.reconfig_mgmt_writedata (reconfig_mgmt_writedata[31:0]),
.reconfig_from_xcvr (reconfig_from_xcvr[459:0]));
// PCIE Core
PCIeGen2x8If128 PCIeGen2x8If128_inst
(
// Outputs
// Local Management Interface
.lmi_ack (lmi_ack),
.lmi_dout (lmi_dout[31:0]),
.tl_cfg_add (tl_cfg_add[3:0]),
.tl_cfg_ctl (tl_cfg_ctl[31:0]),
.tl_cfg_sts (tl_cfg_sts[52:0]),
// RX Interface
.rx_st_sop (rx_st_sop[0:0]),
.rx_st_eop (rx_st_eop[0:0]),
.rx_st_err (rx_st_err[0:0]),
.rx_st_valid (rx_st_valid[0:0]),
.rx_st_empty (rx_st_empty[0:0]),
.rx_st_data (rx_st_data[127:0]),
.rx_st_bar (rx_st_bar[7:0]),
// TX Interface
.tx_st_ready (tx_st_ready),
.coreclkout_hip (coreclkout_hip),
.reset_status (reset_status),
.serdes_pll_locked (serdes_pll_locked),
.pld_clk_inuse (pld_clk_inuse),
// Reconfiguration Interface
.reconfig_from_xcvr (reconfig_from_xcvr[459:0]),
.tx_out0 (tx_out[0]),
.tx_out1 (tx_out[1]),
.tx_out2 (tx_out[2]),
.tx_out3 (tx_out[3]),
.tx_out4 (tx_out[4]),
.tx_out5 (tx_out[5]),
.tx_out6 (tx_out[6]),
.tx_out7 (tx_out[7]),
.app_int_ack (app_int_ack),
.app_msi_ack (app_msi_ack),
// Link status signals
.derr_cor_ext_rcv (derr_cor_ext_rcv),
.derr_cor_ext_rpl (derr_cor_ext_rpl),
.derr_rpl (derr_rpl),
.dlup (dlup),
.dlup_exit (dlup_exit),
.ev128ns (ev128ns),
.ev1us (ev1us),
.hotrst_exit (hotrst_exit),
.int_status (int_status[3:0]),
.l2_exit (l2_exit),
.lane_act (lane_act[3:0]),
.ltssmstate (ltssmstate[4:0]),
.rx_par_err (rx_par_err),
.tx_par_err (tx_par_err[1:0]),
.cfg_par_err (cfg_par_err),
.ko_cpl_spc_header (ko_cpl_spc_header[7:0]),
.ko_cpl_spc_data (ko_cpl_spc_data[11:0]),
.currentspeed (currentspeed[1:0]),
// Inputs
// Resets
.npor (npor),
.pin_perst (pin_perst),
// Clocks
.pld_clk (pld_clk),
.refclk (refclk),
.pld_core_ready (pld_core_ready),
// Local management Interface
.lmi_addr (lmi_addr[11:0]),
.lmi_din (lmi_din[31:0]),
.lmi_rden (lmi_rden),
.lmi_wren (lmi_wren),
// RX Interface
.rx_st_ready (rx_st_ready),
.rx_st_mask (rx_st_mask),
// TX Interface
.tx_st_sop (tx_st_sop[0:0]),
.tx_st_eop (tx_st_eop[0:0]),
.tx_st_err (tx_st_err[0:0]),
.tx_st_valid (tx_st_valid[0:0]),
.tx_st_empty (tx_st_empty[0:0]),
.tx_st_data (tx_st_data[127:0]),
// Reconfiguration Interface
.reconfig_to_xcvr (reconfig_to_xcvr[699:0]),
// RX Serial interface
.rx_in0 (rx_in[0]),
.rx_in1 (rx_in[1]),
.rx_in2 (rx_in[2]),
.rx_in3 (rx_in[3]),
.rx_in4 (rx_in[4]),
.rx_in5 (rx_in[5]),
.rx_in6 (rx_in[6]),
.rx_in7 (rx_in[7]),
// Interrupt Interface
.app_int_sts (app_int_sts),
.app_msi_num (app_msi_num[4:0]),
.app_msi_req (app_msi_req),
.app_msi_tc (app_msi_tc[2:0]),
.simu_mode_pipe (1'b0));
// -------------------- END ALTERA IP INSTANTIATION --------------------
// -------------------- BEGIN RIFFA INSTANTAION --------------------
// RIFFA channel interface
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
wire chnl_reset;
wire chnl_clk;
wire riffa_reset;
wire riffa_clk;
assign chnl_clk = pld_clk;
assign chnl_reset = rst_out;
riffa_wrapper_de5
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(
// Outputs
.RX_ST_READY (rx_st_ready),
.TX_ST_DATA (tx_st_data[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (tx_st_valid[0:0]),
.TX_ST_EOP (tx_st_eop[0:0]),
.TX_ST_SOP (tx_st_sop[0:0]),
.TX_ST_EMPTY (tx_st_empty[0:0]),
.APP_MSI_REQ (app_msi_req),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.RX_ST_DATA (rx_st_data[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (rx_st_eop[0:0]),
.RX_ST_SOP (rx_st_sop[0:0]),
.RX_ST_VALID (rx_st_valid[0:0]),
.RX_ST_EMPTY (rx_st_empty[0:0]),
.TX_ST_READY (tx_st_ready),
.TL_CFG_CTL (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
.TL_CFG_ADD (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
.TL_CFG_STS (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
.KO_CPL_SPC_HEADER (ko_cpl_spc_header[`SIG_KO_CPLH_W-1:0]),
.KO_CPL_SPC_DATA (ko_cpl_spc_data[`SIG_KO_CPLD_W-1:0]),
.APP_MSI_ACK (app_msi_ack),
.PLD_CLK (pld_clk),
.RESET_STATUS (reset_status),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
// -------------------- END RIFFA INSTANTAION --------------------
// -------------------- BEGIN USER CODE --------------------
genvar i;
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
// Instantiate and assign modules to RIFFA channels. Users should
// replace the chnl_tester instantiation with their own core.
chnl_tester
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
)
chnl_tester_i
(
.CLK(chnl_clk),
.RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[i]),
.CHNL_RX(chnl_rx[i]),
.CHNL_RX_ACK(chnl_rx_ack[i]),
.CHNL_RX_LAST(chnl_rx_last[i]),
.CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]),
.CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[i]),
.CHNL_TX(chnl_tx[i]),
.CHNL_TX_ACK(chnl_tx_ack[i]),
.CHNL_TX_LAST(chnl_tx_last[i]),
.CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]),
.CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
);
end
endgenerate
// -------------------- END USER CODE --------------------
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22O_2_V
`define SKY130_FD_SC_HDLL__A22O_2_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a22o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a22o_2 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22O_2_V
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE revB.2 compliant I2C Master controller Top-level ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_top.v,v 1.12 2009-01-19 20:29:26 rherveille Exp $
//
// $Date: 2009-01-19 20:29:26 $
// $Revision: 1.12 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// Revision 1.11 2005/02/27 09:26:24 rherveille
// Fixed register overwrite issue.
// Removed full_case pragma, replaced it by a default statement.
//
// Revision 1.10 2003/09/01 10:34:38 rherveille
// Fix a blocking vs. non-blocking error in the wb_dat output mux.
//
// Revision 1.9 2003/01/09 16:44:45 rherveille
// Fixed a bug in the Command Register declaration.
//
// Revision 1.8 2002/12/26 16:05:12 rherveille
// Small code simplifications
//
// Revision 1.7 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.6 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.5 2001/11/10 10:52:55 rherveille
// Changed PRER reset value from 0x0000 to 0xffff, conform specs.
//
//// synopsys translate_off
//`include "timescale.v"
//// synopsys translate_on
`timescale 1ps / 1ps
`include "i2c_master_defines.v"
module i2c_master_top(
wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
// parameters
parameter ARST_LVL = 1'b0; // asynchronous reset level
//
// inputs & outputs
//
// wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
input arst_i; // asynchronous reset
input [2:0] wb_adr_i; // lower address bits
input [7:0] wb_dat_i; // databus input
output [7:0] wb_dat_o; // databus output
input wb_we_i; // write enable input
input wb_stb_i; // stobe/core select signal
input wb_cyc_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_inta_o; // interrupt request signal output
reg [7:0] wb_dat_o;
reg wb_ack_o;
reg wb_inta_o;
// I2C signals
// i2c clock line
input scl_pad_i; // SCL-line input
output scl_pad_o; // SCL-line output (always 1'b0)
output scl_padoen_o; // SCL-line output enable (active low)
// i2c data line
input sda_pad_i; // SDA-line input
output sda_pad_o; // SDA-line output (always 1'b0)
output sda_padoen_o; // SDA-line output enable (active low)
//
// variable declarations
//
// registers
reg [15:0] prer; // clock prescale register
reg [ 7:0] ctr; // control register
reg [ 7:0] txr; // transmit register
wire [ 7:0] rxr; // receive register
reg [ 7:0] cr; // command register
wire [ 7:0] sr; // status register
// done signal: command completed, clear command register
wire done;
// core enable signal
wire core_en;
wire ien;
// status register signals
wire irxack;
reg rxack; // received aknowledge from slave
reg tip; // transfer in progress
reg irq_flag; // interrupt pending flag
wire i2c_busy; // bus busy (start signal detected)
wire i2c_al; // i2c bus arbitration lost
reg al; // status register arbitration lost bit
//
// module body
//
// generate internal reset
wire rst_i = arst_i ^ ARST_LVL;
// generate wishbone signals
wire wb_wacc = wb_we_i & wb_ack_o;
// generate acknowledge output signal
always @(posedge wb_clk_i)
wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
// assign DAT_O
always @(posedge wb_clk_i)
begin
case (wb_adr_i) // synopsys parallel_case
3'b000: wb_dat_o <= #1 prer[ 7:0];
3'b001: wb_dat_o <= #1 prer[15:8];
3'b010: wb_dat_o <= #1 ctr;
3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
3'b101: wb_dat_o <= #1 txr;
3'b110: wb_dat_o <= #1 cr;
3'b111: wb_dat_o <= #1 0; // reserved
endcase
end
// generate registers
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else if (wb_rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else
if (wb_wacc)
case (wb_adr_i) // synopsys parallel_case
3'b000 : prer [ 7:0] <= #1 wb_dat_i;
3'b001 : prer [15:8] <= #1 wb_dat_i;
3'b010 : ctr <= #1 wb_dat_i;
3'b011 : txr <= #1 wb_dat_i;
default: ;
endcase
// generate command register (special case)
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
cr <= #1 8'h0;
else if (wb_rst_i)
cr <= #1 8'h0;
else if (wb_wacc)
begin
if (core_en & (wb_adr_i == 3'b100) )
cr <= #1 wb_dat_i;
end
else
begin
if (done | i2c_al)
cr[7:4] <= #1 4'h0; // clear command bits when done
// or when aribitration lost
cr[2:1] <= #1 2'b0; // reserved bits
cr[0] <= #1 1'b0; // clear IRQ_ACK bit
end
// decode command register
wire sta = cr[7];
wire sto = cr[6];
wire rd = cr[5];
wire wr = cr[4];
wire ack = cr[3];
wire iack = cr[0];
// decode control register
assign core_en = ctr[7];
assign ien = ctr[6];
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
.clk ( wb_clk_i ),
.rst ( wb_rst_i ),
.nReset ( rst_i ),
.ena ( core_en ),
.clk_cnt ( prer ),
.start ( sta ),
.stop ( sto ),
.read ( rd ),
.write ( wr ),
.ack_in ( ack ),
.din ( txr ),
.cmd_ack ( done ),
.ack_out ( irxack ),
.dout ( rxr ),
.i2c_busy ( i2c_busy ),
.i2c_al ( i2c_al ),
.scl_i ( scl_pad_i ),
.scl_o ( scl_pad_o ),
.scl_oen ( scl_padoen_o ),
.sda_i ( sda_pad_i ),
.sda_o ( sda_pad_o ),
.sda_oen ( sda_padoen_o )
);
// status register block + interrupt request signal
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else if (wb_rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else
begin
al <= #1 i2c_al | (al & ~sta);
rxack <= #1 irxack;
tip <= #1 (rd | wr);
irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
end
// generate interrupt request signals
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
wb_inta_o <= #1 1'b0;
else if (wb_rst_i)
wb_inta_o <= #1 1'b0;
else
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
// assign status register bits
assign sr[7] = rxack;
assign sr[6] = i2c_busy;
assign sr[5] = al;
assign sr[4:2] = 3'h0; // reserved
assign sr[1] = tip;
assign sr[0] = irq_flag;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_jid_to_yid_pool.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// jbi_jid_to_yid_pool -- JID tracking unit.
// _____________________________________________________________________________
//
// Description:
// Provides a table 'used_jids[]' to manage unused JIDs. Provides 16 entries
// each 1 bit wide to hold up to 16 JIDs. Access is one read port and one write
// port.
// _____________________________________________________________________________
`include "sys.h"
module jbi_jid_to_yid_pool (/*AUTOARG*/
// Outputs
jid_is_avail, jid, trans_valid0, trans_valid1,
// Inputs
remove, add0, add_jid0, add1, add_jid1, trans_jid0, trans_jid1, clk,
rst_l
);
// Removing from pool.
output jid_is_avail; // Asserted if an unused JID is available.
output [3:0] jid; // An unused JID. Valid only if 'jid_is_avail' is asserted.
input remove; // When asserted, the JID specified in 'jid' will be removed from the JID pool on the next cycle.
//
// Adding to pool, port0.
input add0; // If asserted, the JID in 'add_jid0' will be added to the JID pool.
input [3:0] add_jid0; // The JID to add to the JID pool.
//
// Adding to pool, port 1.
input add1; // If asserted, the JID in 'add_jid1' will be added to the JID pool.
input [3:0] add_jid1; // The JID to add to the JID pool.
//
// Translation validation, port 0.
input [3:0] trans_jid0; // Verify that transaction exists for this JID.
output trans_valid0; // Translation for 'trans_jid0[]' exists and is valid.
//
// Translation validation, port 1.
input [3:0] trans_jid1; // Verify that transaction exists for this JID.
output trans_valid1; // Translation for 'trans_jid1[]' exists and is valid.
//
// System interface.
input clk; // JBus clock.
input rst_l; // Reset.
// Wires and Regs.
wire last_avail_jid_en;
wire [3:0] next_last_avail_jid, last_avail_jid;
wire [15:0] used_jids, next_used_jids;
wire [15:0] used_jids_en;
wire [15:0] next_used_jids_clr;
wire [15:0] next_used_jids_set;
wire [15:0] unused_jids;
wire [15:0] unused_jids_reordered;
wire [15:0] avail_jids_reordered;
wire [15:0] decoded_jid;
reg trans_valid0, trans_valid1;
reg [3:0] jid;
// JID Pool.
dffrle_ns used_jids_reg00 (.din(next_used_jids[ 0]), .en(used_jids_en[ 0]), .q(used_jids[ 0]), .rst_l(rst_l), .clk(clk));
dffrle_ns used_jids_reg01 (.din(next_used_jids[ 1]), .en(used_jids_en[ 1]), .q(used_jids[ 1]), .rst_l(rst_l), .clk(clk));
dffrle_ns used_jids_reg02 (.din(next_used_jids[ 2]), .en(used_jids_en[ 2]), .q(used_jids[ 2]), .rst_l(rst_l), .clk(clk));
dffrle_ns used_jids_reg03 (.din(next_used_jids[ 3]), .en(used_jids_en[ 3]), .q(used_jids[ 3]), .rst_l(rst_l), .clk(clk));
dffrle_ns used_jids_reg04 (.din(next_used_jids[ 4]), .en(used_jids_en[ 4]), .q(used_jids[ 4]), .rst_l(rst_l), .clk(clk));
dffrle_ns used_jids_reg05 (.din(next_used_jids[ 5]), .en(used_jids_en[ 5]), .q(used_jids[ 5]), .rst_l(rst_l), .clk(clk));
dffrle_ns used_jids_reg06 (.din(next_used_jids[ 6]), .en(used_jids_en[ 6]), .q(used_jids[ 6]), .rst_l(rst_l), .clk(clk));
dffrle_ns used_jids_reg07 (.din(next_used_jids[ 7]), .en(used_jids_en[ 7]), .q(used_jids[ 7]), .rst_l(rst_l), .clk(clk));
dffrle_ns used_jids_reg08 (.din(next_used_jids[ 8]), .en(used_jids_en[ 8]), .q(used_jids[ 8]), .rst_l(rst_l), .clk(clk));
dffrle_ns used_jids_reg09 (.din(next_used_jids[ 9]), .en(used_jids_en[ 9]), .q(used_jids[ 9]), .rst_l(rst_l), .clk(clk));
dffrle_ns used_jids_reg10 (.din(next_used_jids[10]), .en(used_jids_en[10]), .q(used_jids[10]), .rst_l(rst_l), .clk(clk));
dffrle_ns used_jids_reg11 (.din(next_used_jids[11]), .en(used_jids_en[11]), .q(used_jids[11]), .rst_l(rst_l), .clk(clk));
dffrle_ns used_jids_reg12 (.din(next_used_jids[12]), .en(used_jids_en[12]), .q(used_jids[12]), .rst_l(rst_l), .clk(clk));
dffrle_ns used_jids_reg13 (.din(next_used_jids[13]), .en(used_jids_en[13]), .q(used_jids[13]), .rst_l(rst_l), .clk(clk));
dffrle_ns used_jids_reg14 (.din(next_used_jids[14]), .en(used_jids_en[14]), .q(used_jids[14]), .rst_l(rst_l), .clk(clk));
dffrle_ns used_jids_reg15 (.din(next_used_jids[15]), .en(used_jids_en[15]), .q(used_jids[15]), .rst_l(rst_l), .clk(clk));
// Altering the JID Pool.
assign used_jids_en[15:0] = (next_used_jids_set[15:0] | next_used_jids_clr[15:0]);
assign next_used_jids[15:0] = next_used_jids_set[15:0];
//
assign next_used_jids_clr[ 0] = (add0 && (add_jid0 == 4'b0000)) || (add1 && (add_jid1 == 4'b0000));
assign next_used_jids_set[ 0] = (remove && (jid == 4'b0000));
assign next_used_jids_clr[ 1] = (add0 && (add_jid0 == 4'b0001)) || (add1 && (add_jid1 == 4'b0001));
assign next_used_jids_set[ 1] = (remove && (jid == 4'b0001));
assign next_used_jids_clr[ 2] = (add0 && (add_jid0 == 4'b0010)) || (add1 && (add_jid1 == 4'b0010));
assign next_used_jids_set[ 2] = (remove && (jid == 4'b0010));
assign next_used_jids_clr[ 3] = (add0 && (add_jid0 == 4'b0011)) || (add1 && (add_jid1 == 4'b0011));
assign next_used_jids_set[ 3] = (remove && (jid == 4'b0011));
assign next_used_jids_clr[ 4] = (add0 && (add_jid0 == 4'b0100)) || (add1 && (add_jid1 == 4'b0100));
assign next_used_jids_set[ 4] = (remove && (jid == 4'b0100));
assign next_used_jids_clr[ 5] = (add0 && (add_jid0 == 4'b0101)) || (add1 && (add_jid1 == 4'b0101));
assign next_used_jids_set[ 5] = (remove && (jid == 4'b0101));
assign next_used_jids_clr[ 6] = (add0 && (add_jid0 == 4'b0110)) || (add1 && (add_jid1 == 4'b0110));
assign next_used_jids_set[ 6] = (remove && (jid == 4'b0110));
assign next_used_jids_clr[ 7] = (add0 && (add_jid0 == 4'b0111)) || (add1 && (add_jid1 == 4'b0111));
assign next_used_jids_set[ 7] = (remove && (jid == 4'b0111));
assign next_used_jids_clr[ 8] = (add0 && (add_jid0 == 4'b1000)) || (add1 && (add_jid1 == 4'b1000));
assign next_used_jids_set[ 8] = (remove && (jid == 4'b1000));
assign next_used_jids_clr[ 9] = (add0 && (add_jid0 == 4'b1001)) || (add1 && (add_jid1 == 4'b1001));
assign next_used_jids_set[ 9] = (remove && (jid == 4'b1001));
assign next_used_jids_clr[10] = (add0 && (add_jid0 == 4'b1010)) || (add1 && (add_jid1 == 4'b1010));
assign next_used_jids_set[10] = (remove && (jid == 4'b1010));
assign next_used_jids_clr[11] = (add0 && (add_jid0 == 4'b1011)) || (add1 && (add_jid1 == 4'b1011));
assign next_used_jids_set[11] = (remove && (jid == 4'b1011));
assign next_used_jids_clr[12] = (add0 && (add_jid0 == 4'b1100)) || (add1 && (add_jid1 == 4'b1100));
assign next_used_jids_set[12] = (remove && (jid == 4'b1100));
assign next_used_jids_clr[13] = (add0 && (add_jid0 == 4'b1101)) || (add1 && (add_jid1 == 4'b1101));
assign next_used_jids_set[13] = (remove && (jid == 4'b1101));
assign next_used_jids_clr[14] = (add0 && (add_jid0 == 4'b1110)) || (add1 && (add_jid1 == 4'b1110));
assign next_used_jids_set[14] = (remove && (jid == 4'b1110));
assign next_used_jids_clr[15] = (add0 && (add_jid0 == 4'b1111)) || (add1 && (add_jid1 == 4'b1111));
assign next_used_jids_set[15] = (remove && (jid == 4'b1111));
// Verify that a translation exists, port 0
always @(/*AS*/trans_jid0 or used_jids) begin
case (trans_jid0) // synopsys infer_mux
4'd00: trans_valid0 = used_jids[ 0];
4'd01: trans_valid0 = used_jids[ 1];
4'd02: trans_valid0 = used_jids[ 2];
4'd03: trans_valid0 = used_jids[ 3];
4'd04: trans_valid0 = used_jids[ 4];
4'd05: trans_valid0 = used_jids[ 5];
4'd06: trans_valid0 = used_jids[ 6];
4'd07: trans_valid0 = used_jids[ 7];
4'd08: trans_valid0 = used_jids[ 8];
4'd09: trans_valid0 = used_jids[ 9];
4'd10: trans_valid0 = used_jids[10];
4'd11: trans_valid0 = used_jids[11];
4'd12: trans_valid0 = used_jids[12];
4'd13: trans_valid0 = used_jids[13];
4'd14: trans_valid0 = used_jids[14];
4'd15: trans_valid0 = used_jids[15];
endcase
end
// Verify that a translation exists, port 1
always @(/*AS*/trans_jid1 or used_jids) begin
case (trans_jid1) // synopsys infer_mux
4'd00: trans_valid1 = used_jids[ 0];
4'd01: trans_valid1 = used_jids[ 1];
4'd02: trans_valid1 = used_jids[ 2];
4'd03: trans_valid1 = used_jids[ 3];
4'd04: trans_valid1 = used_jids[ 4];
4'd05: trans_valid1 = used_jids[ 5];
4'd06: trans_valid1 = used_jids[ 6];
4'd07: trans_valid1 = used_jids[ 7];
4'd08: trans_valid1 = used_jids[ 8];
4'd09: trans_valid1 = used_jids[ 9];
4'd10: trans_valid1 = used_jids[10];
4'd11: trans_valid1 = used_jids[11];
4'd12: trans_valid1 = used_jids[12];
4'd13: trans_valid1 = used_jids[13];
4'd14: trans_valid1 = used_jids[14];
4'd15: trans_valid1 = used_jids[15];
endcase
end
// Any JID available?
assign jid_is_avail = (used_jids != 16'b1111_1111_1111_1111);
// Save the last consumed jid as a reference for the round-robin arbiter.
assign next_last_avail_jid = jid;
assign last_avail_jid_en = remove;
dffrle_ns #(4) last_avail_jid_reg (.din(next_last_avail_jid), .en(last_avail_jid_en), .q(last_avail_jid), .rst_l(rst_l), .clk(clk));
// Finding next available JID in pool.
//
// Always issuing just released JIDs would make transaction tracking in verification and
// bringup difficult. So we try and cycle through the JIDs here.
//
// We want to know the unused jids.
assign unused_jids[15:0] = ~used_jids[15:0];
//
// Reorder the 'unused_jids[]' based on the 'last_avail_jid' such that highest priority is in the MSB
// and lowest priority is in the LSB.
assign unused_jids_reordered[15:0] =
((last_avail_jid == 4'd00)? {unused_jids[15:0] }: 16'b0) | /* last_avail_jid == 0 -> priority = 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0 */
((last_avail_jid == 4'd15)? {unused_jids[14:0], unused_jids[15] }: 16'b0) | /* last_avail_jid == 15 -> priority = 14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,15 */
((last_avail_jid == 4'd14)? {unused_jids[13:0], unused_jids[15:14]}: 16'b0) | /* last_avail_jid == 14 -> priority = 13,12,11,10,9,8,7,6,5,4,3,2,1,0,15,14 */
((last_avail_jid == 4'd13)? {unused_jids[12:0], unused_jids[15:13]}: 16'b0) | /* last_avail_jid == 13 -> priority = 12,11,10,9,8,7,6,5,4,3,2,1,0,15,14,13 */
((last_avail_jid == 4'd12)? {unused_jids[11:0], unused_jids[15:12]}: 16'b0) | /* last_avail_jid == 12 -> priority = 11,10,9,8,7,6,5,4,3,2,1,0,15,14,13,12 */
((last_avail_jid == 4'd11)? {unused_jids[10:0], unused_jids[15:11]}: 16'b0) | /* last_avail_jid == 11 -> priority = 10,9,8,7,6,5,4,3,2,1,0,15,14,13,12,11 */
((last_avail_jid == 4'd10)? {unused_jids[ 9:0], unused_jids[15:10]}: 16'b0) | /* last_avail_jid == 10 -> priority = 9,8,7,6,5,4,3,2,1,0,15,14,13,12,11,10 */
((last_avail_jid == 4'd09)? {unused_jids[ 8:0], unused_jids[15: 9]}: 16'b0) | /* last_avail_jid == 9 -> priority = 8,7,6,5,4,3,2,1,0,15,14,13,12,11,10,9 */
((last_avail_jid == 4'd08)? {unused_jids[ 7:0], unused_jids[15: 8]}: 16'b0) | /* last_avail_jid == 8 -> priority = 7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8 */
((last_avail_jid == 4'd07)? {unused_jids[ 6:0], unused_jids[15: 7]}: 16'b0) | /* last_avail_jid == 7 -> priority = 6,5,4,3,2,1,0,15,14,13,12,11,10,9,8,7 */
((last_avail_jid == 4'd06)? {unused_jids[ 5:0], unused_jids[15: 6]}: 16'b0) | /* last_avail_jid == 6 -> priority = 5,4,3,2,1,0,15,14,13,12,11,10,9,8,7,6 */
((last_avail_jid == 4'd05)? {unused_jids[ 4:0], unused_jids[15: 5]}: 16'b0) | /* last_avail_jid == 5 -> priority = 4,3,2,1,0,15,14,13,12,11,10,9,8,7,6,5 */
((last_avail_jid == 4'd04)? {unused_jids[ 3:0], unused_jids[15: 4]}: 16'b0) | /* last_avail_jid == 4 -> priority = 3,2,1,0,15,14,13,12,11,10,9,8,7,6,5,4 */
((last_avail_jid == 4'd03)? {unused_jids[ 2:0], unused_jids[15: 3]}: 16'b0) | /* last_avail_jid == 3 -> priority = 2,1,0,15,14,13,12,11,10,9,8,7,6,5,4,3 */
((last_avail_jid == 4'd02)? {unused_jids[ 1:0], unused_jids[15: 2]}: 16'b0) | /* last_avail_jid == 2 -> priority = 1,0,15,14,13,12,11,10,9,8,7,6,5,4,3,2 */
((last_avail_jid == 4'd01)? {unused_jids[ 0], unused_jids[15: 1]}: 16'b0) ; /* last_avail_jid == 1 -> priority = 0,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1 */
//
// Do a priority encode.
assign avail_jids_reordered[15:0] = {
(unused_jids_reordered[15] ),
(unused_jids_reordered[14] && !(| unused_jids_reordered[15] )),
(unused_jids_reordered[13] && !(| unused_jids_reordered[15:14])),
(unused_jids_reordered[12] && !(| unused_jids_reordered[15:13])),
(unused_jids_reordered[11] && !(| unused_jids_reordered[15:12])),
(unused_jids_reordered[10] && !(| unused_jids_reordered[15:11])),
(unused_jids_reordered[ 9] && !(| unused_jids_reordered[15:10])),
(unused_jids_reordered[ 8] && !(| unused_jids_reordered[15: 9])),
(unused_jids_reordered[ 7] && !(| unused_jids_reordered[15: 8])),
(unused_jids_reordered[ 6] && !(| unused_jids_reordered[15: 7])),
(unused_jids_reordered[ 5] && !(| unused_jids_reordered[15: 6])),
(unused_jids_reordered[ 4] && !(| unused_jids_reordered[15: 5])),
(unused_jids_reordered[ 3] && !(| unused_jids_reordered[15: 4])),
(unused_jids_reordered[ 2] && !(| unused_jids_reordered[15: 3])),
(unused_jids_reordered[ 1] && !(| unused_jids_reordered[15: 2])),
(unused_jids_reordered[ 0] && !(| unused_jids_reordered[15: 1]))
};
//
// Reverse the reordering mapping done in 'unused_jids_reordered[]'.
assign decoded_jid[15:0] =
((last_avail_jid == 4'd00)? { avail_jids_reordered[15: 0]}: 16'b0) |
((last_avail_jid == 4'd15)? {avail_jids_reordered[ 0] , avail_jids_reordered[15: 1]}: 16'b0) |
((last_avail_jid == 4'd14)? {avail_jids_reordered[ 1:0], avail_jids_reordered[15: 2]}: 16'b0) |
((last_avail_jid == 4'd13)? {avail_jids_reordered[ 2:0], avail_jids_reordered[15: 3]}: 16'b0) |
((last_avail_jid == 4'd12)? {avail_jids_reordered[ 3:0], avail_jids_reordered[15: 4]}: 16'b0) |
((last_avail_jid == 4'd11)? {avail_jids_reordered[ 4:0], avail_jids_reordered[15: 5]}: 16'b0) |
((last_avail_jid == 4'd10)? {avail_jids_reordered[ 5:0], avail_jids_reordered[15: 6]}: 16'b0) |
((last_avail_jid == 4'd09)? {avail_jids_reordered[ 6:0], avail_jids_reordered[15: 7]}: 16'b0) |
((last_avail_jid == 4'd08)? {avail_jids_reordered[ 7:0], avail_jids_reordered[15: 8]}: 16'b0) |
((last_avail_jid == 4'd07)? {avail_jids_reordered[ 8:0], avail_jids_reordered[15: 9]}: 16'b0) |
((last_avail_jid == 4'd06)? {avail_jids_reordered[ 9:0], avail_jids_reordered[15:10]}: 16'b0) |
((last_avail_jid == 4'd05)? {avail_jids_reordered[10:0], avail_jids_reordered[15:11]}: 16'b0) |
((last_avail_jid == 4'd04)? {avail_jids_reordered[11:0], avail_jids_reordered[15:12]}: 16'b0) |
((last_avail_jid == 4'd03)? {avail_jids_reordered[12:0], avail_jids_reordered[15:13]}: 16'b0) |
((last_avail_jid == 4'd02)? {avail_jids_reordered[13:0], avail_jids_reordered[15:14]}: 16'b0) |
((last_avail_jid == 4'd01)? {avail_jids_reordered[14:0], avail_jids_reordered[15 ]}: 16'b0);
//
// Encode the JID.
always @(/*AS*/decoded_jid) begin
case (1'b1)
decoded_jid[15]: jid = 4'd15;
decoded_jid[14]: jid = 4'd14;
decoded_jid[13]: jid = 4'd13;
decoded_jid[12]: jid = 4'd12;
decoded_jid[11]: jid = 4'd11;
decoded_jid[10]: jid = 4'd10;
decoded_jid[ 9]: jid = 4'd09;
decoded_jid[ 8]: jid = 4'd08;
decoded_jid[ 7]: jid = 4'd07;
decoded_jid[ 6]: jid = 4'd06;
decoded_jid[ 5]: jid = 4'd05;
decoded_jid[ 4]: jid = 4'd04;
decoded_jid[ 3]: jid = 4'd03;
decoded_jid[ 2]: jid = 4'd02;
decoded_jid[ 1]: jid = 4'd01;
decoded_jid[ 0]: jid = 4'd00;
// CoverMeter line_off
default: jid = 4'bX;
// CoverMeter line_on
endcase
end
// Monitors.
// simtech modcovoff -bpen
// synopsys translate_off
always @(posedge clk) begin
// Check: 'remove' should never be asserted when '!jid_is_avail'.
if (remove && !jid_is_avail) begin
$dispmon ("jbi_mout_jbi_jid_to_yid_pool", 49, "%d %m: ERROR - JID Pool has underflowed!", $time);
end
// (This check is commented out because an 'Unexpected Data Return' after a 'Read Return Timeout' is legal)
//
//// Check: Adding a JID should not already be there.
//if (add0 && unused_jids[add_jid0]) begin
// $dispmon ("jbi_mout_jbi_jid_to_yid_pool", 49, "%d %m: ERROR - Attempted to add an existing JID to the JID Pool! (add_jid0=%h, unused_jids[add_jid0]=%h)", $time, add_jid0, unused_jids[add_jid0]);
// end
//if (add1 && unused_jids[add_jid1]) begin
// $dispmon ("jbi_mout_jbi_jid_to_yid_pool", 49, "%d %m: ERROR - Attempted to add an existing JID to the JID Pool! (add_jid1=%h, unused_jids[add_jid1]=%h)", $time, add_jid1, unused_jids[add_jid1]);
// end
end
// synopsys translate_on
// simtech modcovon -bpen
endmodule
// Local Variables:
// verilog-library-directories:("../../../include")
// verilog-library-files:("../../../common/rtl/swrvr_clib.v")
// verilog-module-parents:("jbi_jid_to_yid")
// End:
|
/*
Filename: TopModule.v
Author: Duane Niles, Jason Thweatt, Danny Dutton
Date: 1 April 2015
Version: 2
Description: Top-Level module for synthesis.
Updated for use on the DE1-SoC platform.
*/
module TopModule(CLOCK_50, SW, KEY, HEX3, HEX2, HEX1, HEX0);
input CLOCK_50;
input [5:0] SW;
input [1:0] KEY;
output [0:6] HEX3, HEX2, HEX1, HEX0; // 7-segment display driver interface
// READ PAGE 26 OF THE MANUAL TO UNDERSTAND WHY THE VECTOR LOOKS LIKE THIS.
// NO, REALLY. GO READ IT. YOU'LL NEED IT ANYWAY.
wire enable;
wire [15:0] hexDigits;
// The dot notation represents a "named assignment" - the dotted names of the signals in the module declarations
// correspond to the signals in the top-level module that are enclosed in parentheses.
// This notation helps a reader to make clear associations between signals in a module and the ports of an
// instance of some other module.
keypressed K1 (.clock(CLOCK_50), // 50 MHz FPGA Clock
.reset(KEY[0]), // Master Reset - Pushbutton Key 0
.enable_in(KEY[1]), // Enable - Pushbutton Key 1
.enable_out(enable)); // Connect to the enable input port of the counter.
counter16bit C1 (.clock(CLOCK_50), // 50 MHz FPGA Clock
.enable(enable), // Driven by the enable_out port from the keypressed FSM
.clear(KEY[0]), // Master Reset - Pushbutton key 0
.disp(SW[5]), // Disp - DIP switch 5
.dir(SW[4]), // Dir - DIP switch 2
.countValue(SW[3:0]), // countValue - DIP switches (3:0)
.outputValue(hexDigits)); // hexDigits - Connect to the seven-segment displays
// INSTANTIATE FOUR INSTANCES OF YOUR 7-SEGMENT DISPLAY DRIVER.
// EACH ONE SHOULD ACCEPT A FOUR-BIT VALUE THAT CORRESPONDS TO ONE HEX DIGIT OF THE COUNTER VALUE.
// THE OUTPUTS OF THE DISPLAY DRIVERS SHOULD CORRESPOND TO A SET OF DRIVERS FOR THE 7-SEGMENT DISPLAYS.
// FOLLOW THE "NAMED ASSIGNMENT" APPROACH USED IN KEYPRESSED AND COUNTER16BIT.
sevensegdecoder_always S0 (.digit(hexDigits[3:0]),
.drivers(HEX0));
sevensegdecoder_always S1 (.digit(hexDigits[7:4]),
.drivers(HEX1));
sevensegdecoder_always S2 (.digit(hexDigits[11:8]),
.drivers(HEX2));
sevensegdecoder_always S3 (.digit(hexDigits[15:12]),
.drivers(HEX3));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:14:01 03/09/2017
// Design Name:
// Module Name: SimpleAI_TB
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LookupAI_TB;
reg [8:0] X_state;
reg [8:0] O_state;
wire [8:0] AI_move;
integer i, j;
initial begin
#10;
// do stuff
X_state = 9'b000000000;
O_state = 9'b000000000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
// do stuff
X_state = 9'b100000000;
O_state = 9'b000100000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
// do stuff
X_state = 9'b101000000;
O_state = 9'0001000001;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
// do stuff
X_state = 9'b111000000;
O_state = 9'0000000000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#200;
$finish;
end
LookupTableAI lai (
X_state,
O_state,
AI_move
);
endmodule
|
`timescale 1ns / 1ps
module Tic_tac_toe(
input iCLK_50,
input [3:0] iSW,
input BTN_WEST,
input BTN_EAST,
input BTN_NORTH,
input BTN_SOUTH,
output wire oVGA_R,
output wire oVGA_G,
output wire oVGA_B,
output oHS,
output oVS,
output [7:0] oLED
);
reg CLK_25;
wire reset;
wire start;
wire btn_player1;
wire btn_player2;
wire [10:0] vcounter;
wire [11:0] hcounter;
wire [8:0] symbol;
wire [8:0] occupied;
assign reset = BTN_SOUTH;
syn_edge_detect sed1(CLK_25, reset, BTN_EAST, btn_player1);
syn_edge_detect sed2(CLK_25, reset, BTN_WEST, btn_player2);
syn_edge_detect sed3(CLK_25, reset, BTN_NORTH, start);
// generate a 25Mhz clock
always @(posedge iCLK_50)
CLK_25 = ~CLK_25;
VGA_control vga_c(.CLK(CLK_25),.reset(reset),.vcounter(vcounter),
.hcounter(hcounter),.visible(visible),.oHS(oHS),.oVS(oVS));
state_control s_control(.CLK(CLK_25),.START(start),.RESET(reset),.BTN_PLAYER1(btn_player1), .BTN_PLAYER2(btn_player2),.iSW(iSW),.OLED(oLED), .occupied(occupied), .symbol(symbol));
draw_symbols d_symbol(.reset(reset), .vcounter(vcounter), .hcounter(hcounter), .visible(visible), .VGA_R(oVGA_R), .VGA_G(oVGA_G), .VGA_B(oVGA_B), .occupied(occupied), .symbol(symbol));
endmodule
|
`default_nettype none
module gci_std_display_data_read #(
parameter P_AREA_H = 640,
parameter P_AREA_Y = 480,
parameter P_READ_FIFO_DEPTH = 64,
parameter P_READ_FIFO_DEPTH_N = 6,
parameter P_MEM_ADDR_N = 19
)(
//System
input wire iGCI_CLOCK,
input wire iDISP_CLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Read Request
input wire iRD_ENA,
input wire iRD_SYNC,
output wire oRD_VALID,
output wire [7:0] oRD_DATA_R,
output wire [7:0] oRD_DATA_G,
output wire [7:0] oRD_DATA_B,
//Memory IF
output wire oIF_REQ,
input wire iIF_ACK,
output wire oIF_FINISH,
output wire oIF_ENA,
input wire iIF_BUSY,
output wire [P_MEM_ADDR_N-1:0] oIF_ADDR,
input wire iIF_VALID,
input wire [31:0] iIF_DATA
);
//Main State
localparam P_L_MAIN_STT_IDLE = 2'h0;
localparam P_L_MAIN_STT_IF_REQ = 2'h1;
localparam P_L_MAIN_STT_WORK = 2'h2;
localparam P_L_MAIN_STT_IF_FINISH = 2'h3;
//Read State
localparam P_L_READ_STT_IDLE = 1'h0;
localparam P_L_READ_STT_READ = 1'h1;
localparam P_L_READ_STT_END = 1'h2;
//Main State
reg [1:0] b_main_state;
//Read State
reg b_read_state;
reg [P_MEM_ADDR_N-1:0] b_read_addr;
reg [P_READ_FIFO_DEPTH_N-1:0] b_read_count;
//FIFO
wire vramfifo0_full;
wire vramfifo0_empty;
wire [23:0] vramfifo0_data;
wire vramfifo1_full;
wire vramfifo1_empty;
wire [7:0] vramfifo1_data_r, vramfifo1_data_g, vramfifo1_data_b;
//Output Buffer
reg b_out_buff_valid;
reg [7:0] b_out_buff_r, b_out_buff_g, b_out_buff_b;
//Condition
wire if_request_condition = vramfifo0_empty;
wire read_state_start_condition = (b_main_state == P_L_MAIN_STT_WORK);
/***************************************************
Main State
***************************************************/
always@(posedge iGCI_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_main_state <= P_L_MAIN_STT_IDLE;
end
else if(iRESET_SYNC)begin
b_main_state <= P_L_MAIN_STT_IDLE;
end
else begin
case(b_main_state)
P_L_MAIN_STT_IDLE:
begin
if(if_request_condition)begin
b_main_state <= P_L_MAIN_STT_IF_REQ;
end
end
P_L_MAIN_STT_IF_REQ:
begin
if(iIF_ACK)begin
b_main_state <= P_L_MAIN_STT_WORK;
end
end
P_L_MAIN_STT_WORK:
begin
if(b_read_state == P_L_READ_STT_END)begin
b_main_state <= P_L_MAIN_STT_IF_FINISH;
end
end
P_L_MAIN_STT_IF_FINISH:
begin
b_main_state <= P_L_MAIN_STT_IDLE;
end
endcase
end
end
/***************************************************
Read State
***************************************************/
always@(posedge iGCI_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_read_state <= P_L_READ_STT_IDLE;
b_read_addr <= {P_MEM_ADDR_N{1'b0}};
b_read_count <= {P_READ_FIFO_DEPTH_N{1'b0}};
end
else if(iRESET_SYNC)begin
b_read_state <= P_L_READ_STT_IDLE;
b_read_addr <= {P_MEM_ADDR_N{1'b0}};
b_read_count <= {P_READ_FIFO_DEPTH_N{1'b0}};
end
else begin
case(b_read_state)
P_L_READ_STT_IDLE:
begin
b_read_count <= {P_READ_FIFO_DEPTH_N{1'b0}};
if(read_state_start_condition)begin
b_read_state <= P_L_READ_STT_READ;
end
end
P_L_READ_STT_READ:
begin
if(b_read_count < {P_READ_FIFO_DEPTH_N{1'b0}})begin
if(!iIF_BUSY)begin //Busy Check
b_read_addr <= func_read_next_addr(b_read_addr);
b_read_count <= b_read_count + {{P_READ_FIFO_DEPTH_N-1{1'b0}}, 1'b1};
end
end
else begin
b_read_state <= P_L_READ_STT_END;
end
end
P_L_READ_STT_END:
begin
b_read_state <= P_L_READ_STT_IDLE;
end
default:
begin
b_read_state <= P_L_READ_STT_IDLE;
end
endcase
end
end //Read State
function [P_MEM_ADDR_N-1:0] func_read_next_addr;
input [P_MEM_ADDR_N-1:0] func_now_addr;
begin
if(func_now_addr < (P_AREA_H*P_AREA_V)-1)begin
func_read_next_addr = func_now_addr + 1;
end
else begin
func_read_next_addr = {P_MEM_ADDR_N{1'b0}};
end
end
endfunction
/***************************************************
Output FIFO
***************************************************/
gci_std_sync_fifo #(24, P_READ_FIFO_DEPTH, P_READ_FIFO_DEPTH_N) VRAMREAD_FIFO0(
.inRESET(inRESET),
.iREMOVE(iRESET_SYNC),
.iCLOCK(iGCI_CLOCK),
.iWR_EN(iIF_VALID && !vramfifo0_full),
.iWR_DATA(iIF_DATA[23:0]),
.oWR_FULL(vramfifo0_full),
.oWR_ALMOST_FULL(),
.iRD_EN(!vramfifo0_empty && !vramfifo1_full),
.oRD_DATA(vramfifo0_data),
.oRD_EMPTY(vramfifo0_empty)
);
gci_std_async_fifo #(24, P_READ_FIFO_DEPTH, P_READ_FIFO_DEPTH_N) VRAMREAD_FIFO1(
.inRESET(inRESET),
.iREMOVE(iRESET_SYNC),
.iWR_CLOCK(iGCI_CLOCK),
.iWR_EN(!vramfifo0_empty && !vramfifo1_full),
.iWR_DATA(vramfifo0_data),
.oWR_FULL(vramfifo1_full),
.iRD_CLOCK(iDISP_CLOCK),
.iRD_EN(!vramfifo1_empty && iRD_ENA),
.oRD_DATA({vramfifo1_data_r, vramfifo1_data_g, vramfifo1_data_b}),
.oRD_EMPTY(vramfifo1_empty)
);
/***************************************************
Output Buffer
***************************************************/
always@(posedge iDISP_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_out_buff_valid <= 1'b0;
b_out_buff_r <= 8'h0;
b_out_buff_g <= 8'h0;
b_out_buff_b <= 8'h0;
end
else begin
b_out_buff_valid <= iRD_ENA;
b_out_buff_r <= vramfifo1_data_r;
b_out_buff_g <= vramfifo1_data_g;
b_out_buff_b <= vramfifo1_data_b;
end
end
/***************************************************
Assign
***************************************************/
assign oRD_VALID = b_out_buff_valid;
assign oRD_DATA_R = b_out_buff_r;
assign oRD_DATA_G = b_out_buff_g;
assign oRD_DATA_B = b_out_buff_b;
assign oIF_REQ = (b_main_state == P_L_MAIN_STT_IF_REQ);
assign oIF_FINISH = (b_main_state == P_L_MAIN_STT_IF_FINISH);
assign oIF_ENA = !iIF_BUSY && (b_read_state == P_L_READ_STT_READ);
assign oIF_ADDR = b_read_addr;
/***************************************************
Assertion
***************************************************/
`ifdef GCI_STD_DISP_SVA_ASSERTION
proterty PRO_FIFO_NEVER_NOT_EMPTY;
@(posedge iDISP_CLOCK) disable iff (!inRESET) (!vramfifo1_empty |=> !vramfifo1_empty);
endproperty
assert property(PRO_FIFO_NEVER_NOT_EMPTY);
`endif
endmodule
`default_nettype wire
|
/***************************************************************************************************
** fpga_nes/hw/src/cmn/block_ram/block_ram.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Various generic, inferred block ram descriptors.
***************************************************************************************************/
// Dual port RAM with synchronous read. Modified version of listing 12.4 in "FPGA Prototyping by
// Verilog Examples," itself a modified version of XST 8.11 v_rams_11.
module dual_port_ram_sync
#(
parameter ADDR_WIDTH = 6,
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire we,
input wire [ADDR_WIDTH-1:0] addr_a,
input wire [ADDR_WIDTH-1:0] addr_b,
input wire [DATA_WIDTH-1:0] din_a,
output wire [DATA_WIDTH-1:0] dout_a,
output wire [DATA_WIDTH-1:0] dout_b
);
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] q_addr_a;
reg [ADDR_WIDTH-1:0] q_addr_b;
always @(posedge clk)
begin
if (we)
ram[addr_a] <= din_a;
q_addr_a <= addr_a;
q_addr_b <= addr_b;
end
assign dout_a = ram[q_addr_a];
assign dout_b = ram[q_addr_b];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__BUF_BEHAVIORAL_PP_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUF_BEHAVIORAL_PP_V |
//----------------------------------------------------------------------
// Title : Demo testbench
// Project : Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper
// File : demo_tb.v
// Version : 1.8
//-----------------------------------------------------------------------------
//
// (c) Copyright 2004-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------
// Description: This testbench will exercise the PHY ports of the EMAC
// to demonstrate the functionality.
//----------------------------------------------------------------------
`timescale 1ps / 1ps
module testbench;
//--------------------------------------------------------------------
// testbench signals
//--------------------------------------------------------------------
wire reset;
// EMAC0
wire tx_client_clk_0;
wire [7:0] tx_ifg_delay_0;
wire rx_client_clk_0;
wire [15:0] pause_val_0;
wire pause_req_0;
// GMII wires
wire gmii_tx_clk_0;
wire gmii_tx_en_0;
wire gmii_tx_er_0;
wire [7:0] gmii_txd_0;
wire gmii_rx_clk_0;
wire gmii_rx_dv_0;
wire gmii_rx_er_0;
wire [7:0] gmii_rxd_0;
// Not asserted: full duplex only testbench
wire mii_tx_clk_0;
wire gmii_crs_0;
wire gmii_col_0;
// Clock wires
wire host_clk;
reg gtx_clk;
reg refclk;
//----------------------------------------------------------------
// Test Bench Semaphores
//----------------------------------------------------------------
wire emac0_configuration_busy;
wire emac0_monitor_finished_1g;
wire emac0_monitor_finished_100m;
wire emac0_monitor_finished_10m;
wire emac1_configuration_busy;
wire emac1_monitor_finished_1g;
wire emac1_monitor_finished_100m;
wire emac1_monitor_finished_10m;
//----------------------------------------------------------------
// Wire up Device Under Test
//----------------------------------------------------------------
emac_single_example_design dut
(
// Client Receiver Interface - EMAC0
.EMAC0CLIENTRXDVLD (),
.EMAC0CLIENTRXFRAMEDROP (),
.EMAC0CLIENTRXSTATS (),
.EMAC0CLIENTRXSTATSVLD (),
.EMAC0CLIENTRXSTATSBYTEVLD (),
// Client Transmitter Interface - EMAC0
.CLIENTEMAC0TXIFGDELAY (tx_ifg_delay_0),
.EMAC0CLIENTTXSTATS (),
.EMAC0CLIENTTXSTATSVLD (),
.EMAC0CLIENTTXSTATSBYTEVLD (),
// MAC Control Interface - EMAC0
.CLIENTEMAC0PAUSEREQ (pause_req_0),
.CLIENTEMAC0PAUSEVAL (pause_val_0),
// Clock wire - EMAC0
.GTX_CLK_0 (gtx_clk),
// GMII Interface - EMAC0
.GMII_TXD_0 (gmii_txd_0),
.GMII_TX_EN_0 (gmii_tx_en_0),
.GMII_TX_ER_0 (gmii_tx_er_0),
.GMII_TX_CLK_0 (gmii_tx_clk_0),
.GMII_RXD_0 (gmii_rxd_0),
.GMII_RX_DV_0 (gmii_rx_dv_0),
.GMII_RX_ER_0 (gmii_rx_er_0),
.GMII_RX_CLK_0 (gmii_rx_clk_0),
.REFCLK (refclk),
// Asynchronous Reset
.RESET (reset)
);
//--------------------------------------------------------------------------
// Flow Control is unused in this demonstration
//--------------------------------------------------------------------------
assign pause_req_0 = 1'b0;
assign pause_val_0 = 16'b0;
// IFG stretching not used in demo.
assign tx_ifg_delay_0 = 8'b0;
//--------------------------------------------------------------------------
// Clock drivers
//--------------------------------------------------------------------------
// Drive GTX_CLK at 125 MHz
initial // drives gtx_clk at 125 MHz
begin
gtx_clk <= 1'b0;
#10000;
forever
begin
gtx_clk <= 1'b0;
#4000;
gtx_clk <= 1'b1;
#4000;
end
end
// Drive refclk at 200MHz
initial
begin
refclk <= 1'b0;
#10000;
forever
begin
refclk <= 1'b1;
#2500;
refclk <= 1'b0;
#2500;
end
end
//--------------------------------------------------------------------
// Instantiate the EMAC0 PHY stimulus and monitor
//--------------------------------------------------------------------
emac0_phy_tb phy0_test
(
//----------------------------------------------------------------
// GMII Interface
//----------------------------------------------------------------
.gmii_txd (gmii_txd_0),
.gmii_tx_en (gmii_tx_en_0),
.gmii_tx_er (gmii_tx_er_0),
.gmii_tx_clk (gmii_tx_clk_0),
.gmii_rxd (gmii_rxd_0),
.gmii_rx_dv (gmii_rx_dv_0),
.gmii_rx_er (gmii_rx_er_0),
.gmii_rx_clk (gmii_rx_clk_0),
.gmii_col (gmii_col_0),
.gmii_crs (gmii_crs_0),
.mii_tx_clk (mii_tx_clk_0),
//----------------------------------------------------------------
// Test Bench Semaphores
//----------------------------------------------------------------
.configuration_busy (emac0_configuration_busy),
.monitor_finished_1g (emac0_monitor_finished_1g),
.monitor_finished_100m (emac0_monitor_finished_100m),
.monitor_finished_10m (emac0_monitor_finished_10m),
.monitor_error (monitor_error_emac0)
);
//--------------------------------------------------------------------
// Instantiate the No-Host Configuration Stimulus
//--------------------------------------------------------------------
configuration_tb config_test
(
.reset (reset),
//----------------------------------------------------------------
// Host Interface: host_clk is always required
//----------------------------------------------------------------
.host_clk (host_clk),
//----------------------------------------------------------------
// Test Bench Semaphores
//----------------------------------------------------------------
.emac0_configuration_busy (emac0_configuration_busy),
.emac0_monitor_finished_1g (emac0_monitor_finished_1g),
.emac0_monitor_finished_100m (emac0_monitor_finished_100m),
.emac0_monitor_finished_10m (emac0_monitor_finished_10m),
.emac1_configuration_busy (emac1_configuration_busy),
.emac1_monitor_finished_1g (emac1_monitor_finished_1g),
.emac1_monitor_finished_100m (emac1_monitor_finished_100m),
.emac1_monitor_finished_10m (emac1_monitor_finished_10m),
.monitor_error_emac0 (monitor_error_emac0)
);
endmodule // testbench
|
module stage1(
clk,rst,
i_valid,inverse,
i_transize,
i_0 ,i_1 ,i_2 ,i_3 ,
i_4 ,i_5 ,i_6 ,i_7 ,
i_8 ,i_9 ,i_10,i_11,
i_12,i_13,i_14,i_15,
i_16,i_17,i_18,i_19,
i_20,i_21,i_22,i_23,
i_24,i_25,i_26,i_27,
i_28,i_29,i_30,i_31,
o_valid,
o_0 ,o_1 ,o_2 ,o_3 ,
o_4 ,o_5 ,o_6 ,o_7 ,
o_8 ,o_9 ,o_10,o_11,
o_12,o_13,o_14,o_15,
o_16,o_17,o_18,o_19,
o_20,o_21,o_22,o_23,
o_24,o_25,o_26,o_27,
o_28,o_29,o_30,o_31
);
// *******************************************
//
// INPUT / OUTPUT DECLARATION
//
// *******************************************
input clk;
input rst;
input i_valid;
input [1:0] i_transize;
input inverse;
input signed [15:0] i_0;
input signed [15:0] i_1;
input signed [15:0] i_2;
input signed [15:0] i_3;
input signed [15:0] i_4;
input signed [15:0] i_5;
input signed [15:0] i_6;
input signed [15:0] i_7;
input signed [15:0] i_8;
input signed [15:0] i_9;
input signed [15:0] i_10;
input signed [15:0] i_11;
input signed [15:0] i_12;
input signed [15:0] i_13;
input signed [15:0] i_14;
input signed [15:0] i_15;
input signed [15:0] i_16;
input signed [15:0] i_17;
input signed [15:0] i_18;
input signed [15:0] i_19;
input signed [15:0] i_20;
input signed [15:0] i_21;
input signed [15:0] i_22;
input signed [15:0] i_23;
input signed [15:0] i_24;
input signed [15:0] i_25;
input signed [15:0] i_26;
input signed [15:0] i_27;
input signed [15:0] i_28;
input signed [15:0] i_29;
input signed [15:0] i_30;
input signed [15:0] i_31;
output reg o_valid;
output reg signed [18:0] o_0 ;
output reg signed [18:0] o_1 ;
output reg signed [18:0] o_2 ;
output reg signed [18:0] o_3 ;
output reg signed [18:0] o_4 ;
output reg signed [18:0] o_5 ;
output reg signed [18:0] o_6 ;
output reg signed [18:0] o_7 ;
output reg signed [18:0] o_8 ;
output reg signed [18:0] o_9 ;
output reg signed [18:0] o_10;
output reg signed [18:0] o_11;
output reg signed [18:0] o_12;
output reg signed [18:0] o_13;
output reg signed [18:0] o_14;
output reg signed [18:0] o_15;
output reg signed [18:0] o_16;
output reg signed [18:0] o_17;
output reg signed [18:0] o_18;
output reg signed [18:0] o_19;
output reg signed [18:0] o_20;
output reg signed [18:0] o_21;
output reg signed [18:0] o_22;
output reg signed [18:0] o_23;
output reg signed [18:0] o_24;
output reg signed [18:0] o_25;
output reg signed [18:0] o_26;
output reg signed [18:0] o_27;
output reg signed [18:0] o_28;
output reg signed [18:0] o_29;
output reg signed [18:0] o_30;
output reg signed [18:0] o_31;
// ********************************************
//
// WIRE DECLARATION
//
// ********************************************
wire signed [15:0] in_0;
wire signed [15:0] in_1;
wire signed [15:0] in_2;
wire signed [15:0] in_3;
wire signed [15:0] in_4;
wire signed [15:0] in_5;
wire signed [15:0] in_6;
wire signed [15:0] in_7;
wire signed [15:0] in_8;
wire signed [15:0] in_9;
wire signed [15:0] in_10;
wire signed [15:0] in_11;
wire signed [15:0] in_12;
wire signed [15:0] in_13;
wire signed [15:0] in_14;
wire signed [15:0] in_15;
wire signed [15:0] in_16;
wire signed [15:0] in_17;
wire signed [15:0] in_18;
wire signed [15:0] in_19;
wire signed [15:0] in_20;
wire signed [15:0] in_21;
wire signed [15:0] in_22;
wire signed [15:0] in_23;
wire signed [15:0] in_24;
wire signed [15:0] in_25;
wire signed [15:0] in_26;
wire signed [15:0] in_27;
wire signed [15:0] in_28;
wire signed [15:0] in_29;
wire signed [15:0] in_30;
wire signed [15:0] in_31;
wire signed [18:0] ob_0;
wire signed [18:0] ob_1;
wire signed [18:0] ob_2;
wire signed [18:0] ob_3;
wire signed [18:0] ob_4;
wire signed [18:0] ob_5;
wire signed [18:0] ob_6;
wire signed [18:0] ob_7;
wire signed [18:0] ob_8;
wire signed [18:0] ob_9;
wire signed [18:0] ob_10;
wire signed [18:0] ob_11;
wire signed [18:0] ob_12;
wire signed [18:0] ob_13;
wire signed [18:0] ob_14;
wire signed [18:0] ob_15;
wire signed [18:0] ob_16;
wire signed [18:0] ob_17;
wire signed [18:0] ob_18;
wire signed [18:0] ob_19;
wire signed [18:0] ob_20;
wire signed [18:0] ob_21;
wire signed [18:0] ob_22;
wire signed [18:0] ob_23;
wire signed [18:0] ob_24;
wire signed [18:0] ob_25;
wire signed [18:0] ob_26;
wire signed [18:0] ob_27;
wire signed [18:0] ob_28;
wire signed [18:0] ob_29;
wire signed [18:0] ob_30;
wire signed [18:0] ob_31;
wire signed [15:0] op_0;
wire signed [15:0] op_1;
wire signed [15:0] op_2;
wire signed [15:0] op_3;
wire signed [15:0] op_4;
wire signed [15:0] op_5;
wire signed [15:0] op_6;
wire signed [15:0] op_7;
wire signed [15:0] op_8;
wire signed [15:0] op_9;
wire signed [15:0] op_10;
wire signed [15:0] op_11;
wire signed [15:0] op_12;
wire signed [15:0] op_13;
wire signed [15:0] op_14;
wire signed [15:0] op_15;
wire signed [15:0] op_16;
wire signed [15:0] op_17;
wire signed [15:0] op_18;
wire signed [15:0] op_19;
wire signed [15:0] op_20;
wire signed [15:0] op_21;
wire signed [15:0] op_22;
wire signed [15:0] op_23;
wire signed [15:0] op_24;
wire signed [15:0] op_25;
wire signed [15:0] op_26;
wire signed [15:0] op_27;
wire signed [15:0] op_28;
wire signed [15:0] op_29;
wire signed [15:0] op_30;
wire signed [15:0] op_31;
wire signed [18:0] o0;
wire signed [18:0] o1;
wire signed [18:0] o2;
wire signed [18:0] o3;
wire signed [18:0] o4;
wire signed [18:0] o5;
wire signed [18:0] o6;
wire signed [18:0] o7;
wire signed [18:0] o8;
wire signed [18:0] o9;
wire signed [18:0] o10;
wire signed [18:0] o11;
wire signed [18:0] o12;
wire signed [18:0] o13;
wire signed [18:0] o14;
wire signed [18:0] o15;
wire signed [18:0] o16;
wire signed [18:0] o17;
wire signed [18:0] o18;
wire signed [18:0] o19;
wire signed [18:0] o20;
wire signed [18:0] o21;
wire signed [18:0] o22;
wire signed [18:0] o23;
wire signed [18:0] o24;
wire signed [18:0] o25;
wire signed [18:0] o26;
wire signed [18:0] o27;
wire signed [18:0] o28;
wire signed [18:0] o29;
wire signed [18:0] o30;
wire signed [18:0] o31;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign in_0=i_valid?i_0:'b0;
assign in_1=i_valid?i_1:'b0;
assign in_2=i_valid?i_2:'b0;
assign in_3=i_valid?i_3:'b0;
assign in_4=i_valid?i_4:'b0;
assign in_5=i_valid?i_5:'b0;
assign in_6=i_valid?i_6:'b0;
assign in_7=i_valid?i_7:'b0;
assign in_8=i_valid?i_8:'b0;
assign in_9=i_valid?i_9:'b0;
assign in_10=i_valid?i_10:'b0;
assign in_11=i_valid?i_11:'b0;
assign in_12=i_valid?i_12:'b0;
assign in_13=i_valid?i_13:'b0;
assign in_14=i_valid?i_14:'b0;
assign in_15=i_valid?i_15:'b0;
assign in_16=i_valid?i_16:'b0;
assign in_17=i_valid?i_17:'b0;
assign in_18=i_valid?i_18:'b0;
assign in_19=i_valid?i_19:'b0;
assign in_20=i_valid?i_20:'b0;
assign in_21=i_valid?i_21:'b0;
assign in_22=i_valid?i_22:'b0;
assign in_23=i_valid?i_23:'b0;
assign in_24=i_valid?i_24:'b0;
assign in_25=i_valid?i_25:'b0;
assign in_26=i_valid?i_26:'b0;
assign in_27=i_valid?i_27:'b0;
assign in_28=i_valid?i_28:'b0;
assign in_29=i_valid?i_29:'b0;
assign in_30=i_valid?i_30:'b0;
assign in_31=i_valid?i_31:'b0;
assign o0 = inverse?op_0 :ob_0 ;
assign o1 = inverse?op_1 :ob_1 ;
assign o2 = inverse?op_2 :ob_2 ;
assign o3 = inverse?op_3 :ob_3 ;
assign o4 = inverse?op_4 :ob_4 ;
assign o5 = inverse?op_5 :ob_5 ;
assign o6 = inverse?op_6 :ob_6 ;
assign o7 = inverse?op_7 :ob_7 ;
assign o8 = inverse?op_8 :ob_8 ;
assign o9 = inverse?op_9 :ob_9 ;
assign o10 = inverse?op_10:ob_10;
assign o11 = inverse?op_11:ob_11;
assign o12 = inverse?op_12:ob_12;
assign o13 = inverse?op_13:ob_13;
assign o14 = inverse?op_14:ob_14;
assign o15 = inverse?op_15:ob_15;
assign o16 = inverse?op_16:ob_16;
assign o17 = inverse?op_17:ob_17;
assign o18 = inverse?op_18:ob_18;
assign o19 = inverse?op_19:ob_19;
assign o20 = inverse?op_20:ob_20;
assign o21 = inverse?op_21:ob_21;
assign o22 = inverse?op_22:ob_22;
assign o23 = inverse?op_23:ob_23;
assign o24 = inverse?op_24:ob_24;
assign o25 = inverse?op_25:ob_25;
assign o26 = inverse?op_26:ob_26;
assign o27 = inverse?op_27:ob_27;
assign o28 = inverse?op_28:ob_28;
assign o29 = inverse?op_29:ob_29;
assign o30 = inverse?op_30:ob_30;
assign o31 = inverse?op_31:ob_31;
// ********************************************
//
// sequence Logic
//
// ********************************************
always@(posedge clk or negedge rst)
if(!rst)
o_valid<=1'b0;
else
o_valid<=i_valid;
always@(posedge clk or negedge rst)
if(!rst) begin
o_0 <='b0;o_1 <='b0;o_2 <='b0;o_3 <='b0;
o_4 <='b0;o_5 <='b0;o_6 <='b0;o_7 <='b0;
o_8 <='b0;o_9 <='b0;o_10<='b0;o_11<='b0;
o_12<='b0;o_13<='b0;o_14<='b0;o_15<='b0;
o_16<='b0;o_17<='b0;o_18<='b0;o_19<='b0;
o_20<='b0;o_21<='b0;o_22<='b0;o_23<='b0;
o_24<='b0;o_25<='b0;o_26<='b0;o_27<='b0;
o_28<='b0;o_29<='b0;o_30<='b0;o_31<='b0;
end
else begin
o_0 <=o0 ;o_1 <=o1 ;o_2 <=o2 ;o_3 <=o3 ;
o_4 <=o4 ;o_5 <=o5 ;o_6 <=o6 ;o_7 <=o7 ;
o_8 <=o8 ;o_9 <=o9 ;o_10<=o10;o_11<=o11;
o_12<=o12;o_13<=o13;o_14<=o14;o_15<=o15;
o_16<=o16;o_17<=o17;o_18<=o18;o_19<=o19;
o_20<=o20;o_21<=o21;o_22<=o22;o_23<=o23;
o_24<=o24;o_25<=o25;o_26<=o26;o_27<=o27;
o_28<=o28;o_29<=o29;o_30<=o30;o_31<=o31;
end
// *********************************************
//
// Sub Modules
//
// *********************************************
butterfly1 butterfly1_0(
inverse,i_transize,
in_0 ,in_1 ,in_2 ,in_3 ,
in_4 ,in_5 ,in_6 ,in_7 ,
in_8 ,in_9 ,in_10,in_11,
in_12,in_13,in_14,in_15,
in_16,in_17,in_18,in_19,
in_20,in_21,in_22,in_23,
in_24,in_25,in_26,in_27,
in_28,in_29,in_30,in_31,
ob_0 ,ob_1 ,ob_2 ,ob_3 ,
ob_4 ,ob_5 ,ob_6 ,ob_7 ,
ob_8 ,ob_9 ,ob_10,ob_11,
ob_12,ob_13,ob_14,ob_15,
ob_16,ob_17,ob_18,ob_19,
ob_20,ob_21,ob_22,ob_23,
ob_24,ob_25,ob_26,ob_27,
ob_28,ob_29,ob_30,ob_31
);
premuat1 premuat1_0(
inverse,i_transize,
in_0 ,in_1 ,in_2 ,in_3 ,
in_4 ,in_5 ,in_6 ,in_7 ,
in_8 ,in_9 ,in_10,in_11,
in_12,in_13,in_14,in_15,
in_16,in_17,in_18,in_19,
in_20,in_21,in_22,in_23,
in_24,in_25,in_26,in_27,
in_28,in_29,in_30,in_31,
op_0 ,op_1 ,op_2 ,op_3 ,
op_4 ,op_5 ,op_6 ,op_7 ,
op_8 ,op_9 ,op_10,op_11,
op_12,op_13,op_14,op_15,
op_16,op_17,op_18,op_19,
op_20,op_21,op_22,op_23,
op_24,op_25,op_26,op_27,
op_28,op_29,op_30,op_31
);
endmodule |
module spmc_sd_card(
//*** Connections to SpartanMC Core (do not change) ***
input wire clk_peri, //System-Clock
input wire [17:0] do_peri, //Data Bus from MC
output [17:0] di_peri, //Data Bus to MC
input wire [9:0] addr_peri, //Address Bus from MC
input wire access_peri, //Peripheral Access Signal
input wire wr_peri, //Write Enable Signal
//*** Connections to SpartanMC Core which can be changed ***
input wire reset, //Reset-Signal (could be external)
// BlockRAM interface
input mem_clk, //BRAM clk
input mem_access,
input store_access,
input store_access_low,
input store_access_high,
input [7:0] addr_high,
//*** io interface ***
input wire sd_miso,
output wire sd_mosi,
output wire sd_clk,
output wire sd_cs,
output wire ts_dummy
);
parameter BASE_ADR = 10'h0;
parameter DMA_BASE_ADR = 18'h19c00; //1024 addresses below IO ports
parameter CLOCK_FREQUENCY = 16000000;
assign ts_dummy = 1'b1;
wire [17:0] di_peri_dma;
wire select;
// Address decoder generates the select sinal out of the upper part of the peripheral address.
pselect iCSL (
.addr ( addr_peri[9:3] ),
.activ_peri ( access_peri ),
.select ( select )
);
defparam iCSL.ADDR_WIDTH = 7;
defparam iCSL.BASE_WIDTH = 7;
defparam iCSL.BASE_ADDR = BASE_ADR >> 3; //BASE_ADR has to be divisible by 8
//delay read signal by one cycle (for new pipeline), data is already generated in this cycle by sdcard module
reg reg_read;
always @(posedge clk_peri) begin
reg_read <= select & !wr_peri;
end
wire [17:0] sd_dat_out;
reg [17:0] sd_dat_out_last;
wire [17:0] sd_dat_out_spmc;
assign sd_dat_out_spmc = sd_dat_out_last;
assign di_peri = (reg_read ? sd_dat_out_spmc : 18'b0) | di_peri_dma;
always @(posedge clk_peri) begin
sd_dat_out_last <= sd_dat_out;
end
spiMaster sdcard(
.clk_i(clk_peri),
.rst_i(reset),
.address_i(addr_peri[2:0]),
.data_i(do_peri[17:0]),
.data_o(sd_dat_out),
.select(select),
.we_i(wr_peri),
// SPI logic clock
.spiSysClk(clk_peri),
//SPI bus
.spiClkOut(sd_clk),
.spiDataIn(sd_miso),
.spiDataOut(sd_mosi),
.spiCS_n(sd_cs),
.do_peri(do_peri),
.di_peri(di_peri_dma),
.addr_peri(addr_peri),
.mem_clk(mem_clk),
.mem_access(mem_access),
.store_access(store_access | store_access_low),
.addr_high(addr_high)
);
defparam sdcard.SDCARD_CLOCK = CLOCK_FREQUENCY;
defparam sdcard.u_readWriteSDBlock.SDCARD_CLOCK = CLOCK_FREQUENCY;
defparam sdcard.u_spiMasterSpmcBI.SDCARD_CLOCK = CLOCK_FREQUENCY;
defparam sdcard.DMA_ADR = DMA_BASE_ADR;
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
nios_system_nios2_qsys_0_cpu_debug_slave_tck the_nios_system_nios2_qsys_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
nios_system_nios2_qsys_0_cpu_debug_slave_sysclk the_nios_system_nios2_qsys_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic nios_system_nios2_qsys_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_instance_index = 0,
// nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_ir_width = 2,
// nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_sim_action = "",
// nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_type_id = 34,
// nios_system_nios2_qsys_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
//module for forwarding the arithmetic instructions and preventing data hazards
module forwarding_unit
(
rf_waddr_exmem,
rf_waddr_memwb,
inst_curr_IDEX_7_4_rs,
inst_curr_IDEX_3_0_rt,
inst_curr_IDEX_11_8_rd,
rf_wen_exmem,
rf_wen_memwb,
mem2reg_memwb,
mem2reg_exmem,
dmem_wen_idex,
forwardA,
forwardB,
rdata2_sw_fcontrol,
);
input [3:0] rf_waddr_exmem;
input [3:0] rf_waddr_memwb;
input [3:0] inst_curr_IDEX_7_4_rs;
input [3:0] inst_curr_IDEX_3_0_rt;
input [3:0] inst_curr_IDEX_11_8_rd;
input rf_wen_exmem;
input rf_wen_memwb;
input mem2reg_memwb;
input mem2reg_exmem;
input dmem_wen_idex;
output [1:0] forwardA;
output [1:0] forwardB;
output [1:0] rdata2_sw_fcontrol;
//just doing it for basic arithmetic data hazards at the moment
/*assign forwardA = ((rf_wen_exmem === 1'b1) && (!(rf_waddr_exmem === 4'b0000))
&& (rf_waddr_exmem === inst_curr_IDEX_7_4_rs) && mem2reg_exmem===1'b1)? 2'b10 :
(((rf_wen_memwb === 1'b1) && (!(rf_waddr_memwb === 4'b0000))
&& (!(rf_waddr_exmem === inst_curr_IDEX_7_4_rs))
&& (rf_waddr_memwb === inst_curr_IDEX_7_4_rs)
&& (mem2reg_memwb === 1'b1)) ? 2'b01 : 2'b00);
assign forwardB = ((rf_wen_exmem === 1'b1) && (!(rf_waddr_exmem === 4'b0000))
&& (rf_waddr_exmem === inst_curr_IDEX_3_0_rt) && mem2reg_exmem===1'b1)? 2'b10 :
(((rf_wen_memwb === 1'b1) && (!(rf_waddr_memwb === 4'b0000))
&& (!(rf_waddr_exmem === inst_curr_IDEX_3_0_rt))
&& (rf_waddr_memwb === inst_curr_IDEX_3_0_rt)
&& (mem2reg_memwb === 1'b1)) ? 2'b01 : 2'b00);*/
assign forwardA = ((rf_wen_exmem === 1'b1) && (!(rf_waddr_exmem === 4'b0000))
&& (rf_waddr_exmem === inst_curr_IDEX_7_4_rs))? ((mem2reg_exmem!==1'b1)? 2'b10 : 2'b00) :
(((rf_wen_memwb === 1'b1) && (!(rf_waddr_memwb === 4'b0000))
&& (!(rf_waddr_exmem === inst_curr_IDEX_7_4_rs))
&& (rf_waddr_memwb === inst_curr_IDEX_7_4_rs)
) ? ((mem2reg_memwb!==1'b1)? 2'b01: 2'b00) : 2'b00);
assign forwardB = ((rf_wen_exmem === 1'b1) && (!(rf_waddr_exmem === 4'b0000))
&& (rf_waddr_exmem === inst_curr_IDEX_3_0_rt))? ((mem2reg_exmem!==1'b1)? 2'b10 : 2'b00) :
(((rf_wen_memwb === 1'b1) && (!(rf_waddr_memwb === 4'b0000))
&& (!(rf_waddr_exmem === inst_curr_IDEX_3_0_rt))
&& (rf_waddr_memwb === inst_curr_IDEX_3_0_rt)
) ? ((mem2reg_memwb!==1'b1)? 2'b01: 2'b00) : 2'b00);
//data forwarding for store instruction
assign rdata2_sw_fcontrol = ((dmem_wen_idex === 1'b0) && (!(rf_waddr_exmem === 4'b0000))
&& (rf_waddr_exmem === inst_curr_IDEX_11_8_rd)) ? ((mem2reg_exmem!==1'b1)? 2'b10: 2'b00) :
(((dmem_wen_idex === 1'b0) && (!(rf_waddr_memwb === 4'b0000))
&& (rf_waddr_memwb === inst_curr_IDEX_11_8_rd)) ? ((mem2reg_memwb!==1'b1)? 2'b01 : 2'b00) : 2'b00);
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// Company: RMIT University
// Engineer: Matthew Myungha Kim
// [email protected], [email protected]
//
// Create Date: 17:37:00 18/03/2014
// Design Name: stimulus_gen
// Module Name: stimulus_gen
// Project Name: Streaming Media on Null Convention Logic
// Description: Testbench for UNCLE NCL libraries
// https://sites.google.com/site/asynctools/
//
// Stimulus Signal Generation - Testbench
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//#############################################################
// Testbench NCL basic gates
//#############################################################
//-----------------------------------------------------------
//-- tb_th34w32
//-----------------------------------------------------------
module tb_stimulus_gen;
parameter PERIOD = 10; // 100MHz clock
parameter INPUT_PORTS = 3;
parameter RESET_PORT = 1; // 0: no reset, 1: has reset
parameter RESET_SENS = 0; // 0: Active Low, 1: Active High
// Inputs
// Internal Signals
reg clk;
wire [INPUT_PORTS-1:0] stm_value;
wire rsb;
wire gnt;
reg rst;
reg req;
// Stimulus generation
stimulus_gen
#(.INPUT_PORTS(INPUT_PORTS),
.RESET_PORT(RESET_PORT),
.RESET_SENS(RESET_SENS)
)
stimulus_gen (
.clk(clk),
.rst(rst),
.req(req),
.stm_value(stm_value),
.rsb(rsb),
.gnt(gnt)
);
// Clock for signal generation
always begin
clk = 1'b0;
#(PERIOD/2) clk = 1'b1;
#(PERIOD/2);
end
initial begin
// Initialize Inputs
rst = 1;
req = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
req = 0;
// Add stimulus here
#100;
req = 1;
$display("<< Starting the Simulation >>");
#100;
req = 0;
//$monitor(" %0d %b", $time, gnt);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVN_2_V
`define SKY130_FD_SC_HDLL__EINVN_2_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvn_2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvn_2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVN_2_V
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
// Date : Thu Jul 24 13:39:23 2014
// Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_1_stub.v
// Design : fifo_generator_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2014.1" *)
module fifo_generator_1(clk, rst, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,din[93:0],wr_en,rd_en,dout[93:0],full,empty" */;
input clk;
input rst;
input [93:0]din;
input wr_en;
input rd_en;
output [93:0]dout;
output full;
output empty;
endmodule
|
//wb_dma_writer.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Self Defining Bus (SDB)
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x0000000D
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: (19 UNICODE characters)
SDB_NAME:wb_dma_writer
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x21
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0x00
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/01/07
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:6
*/
`include "dma_writer_defines.v"
module wb_dma_writer #(
parameter BUFFER_SIZE = 12
)(
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
output reg o_wbs_int,
//master control signal for memory arbitration
output mem_o_we,
output mem_o_stb,
output mem_o_cyc,
output [3:0] mem_o_sel,
output [31:0] mem_o_adr,
output [31:0] mem_o_dat,
input [31:0] mem_i_dat,
input mem_i_ack,
input mem_i_int
);
//Local Parameters
localparam REG_CONTROL = 32'h00000000;
localparam REG_STATUS = 32'h00000001;
localparam REG_MEM_0_BASE = 32'h00000002;
localparam REG_MEM_0_SIZE = 32'h00000003;
localparam REG_MEM_1_BASE = 32'h00000004;
localparam REG_MEM_1_SIZE = 32'h00000005;
localparam REG_TOTAL_WRITE_SIZE = 32'h00000006;
//Local Registers/Wires
reg [31:0] r_control;
wire [31:0] w_status;
//Control Signals
wire w_enable;
wire w_enable_interrupt;
wire w_control_reset;
//PPFIFO Signals
wire [23:0] w_wfifo_size;
wire [1:0] w_wfifo_ready;
wire [1:0] w_wfifo_activate;
wire w_wfifo_strobe;
wire [31:0] w_wfifo_data;
wire [23:0] w_rfifo_size;
wire w_rfifo_ready;
wire w_rfifo_activate;
wire w_rfifo_strobe;
wire [31:0] w_rfifo_data;
reg [31:0] r_ppfifo_size_request;
//Mem 2 PPFIFO
reg [31:0] r_memory_0_base;
reg [31:0] r_memory_0_size;
wire [31:0] w_memory_0_count;
reg r_memory_0_new_data;
wire w_memory_0_empty;
wire [31:0] w_default_mem_0_base;
reg [31:0] r_memory_1_base;
reg [31:0] r_memory_1_size;
wire [31:0] w_memory_1_count;
reg r_memory_1_new_data;
wire w_memory_1_empty;
wire [31:0] w_default_mem_1_base;
wire w_read_finished;
//Submodules
wb_mem_2_ppfifo m2p(
.clk (clk ),
.rst (rst || w_control_reset ),
//.debug (debug ),
//Control
.i_enable (w_enable ),
.i_memory_0_base (r_memory_0_base ),
.i_memory_0_size (r_memory_0_size ),
.o_memory_0_count (w_memory_0_count ),
.i_memory_0_new_data (r_memory_0_new_data ),
.o_memory_0_empty (w_memory_0_empty ),
.o_default_mem_0_base (w_default_mem_0_base ),
.i_memory_1_base (r_memory_1_base ),
.i_memory_1_size (r_memory_1_size ),
.o_memory_1_count (w_memory_1_count ),
.i_memory_1_new_data (r_memory_1_new_data ),
.o_memory_1_empty (w_memory_1_empty ),
.o_default_mem_1_base (w_default_mem_1_base ),
.o_read_finished (w_read_finished ),
//master control signal for memory arbitration
.o_mem_we (mem_o_we ),
.o_mem_stb (mem_o_stb ),
.o_mem_cyc (mem_o_cyc ),
.o_mem_sel (mem_o_sel ),
.o_mem_adr (mem_o_adr ),
.o_mem_dat (mem_o_dat ),
.i_mem_dat (mem_i_dat ),
.i_mem_ack (mem_i_ack ),
.i_mem_int (mem_i_int ),
//Ping Pong FIFO Interface
.i_ppfifo_rdy (w_wfifo_ready ),
.o_ppfifo_act (w_wfifo_activate ),
.i_ppfifo_size (w_wfifo_size ),
.o_ppfifo_stb (w_wfifo_strobe ),
.o_ppfifo_data (w_wfifo_data )
);
/*
* It may be better if the Ping Pong FIFO is in another core, especially you
* are clocking the data in with a seperate clock
*/
ppfifo #(
.DATA_WIDTH (32 ),
//Size will always be 32 bits for mem
.ADDRESS_WIDTH (BUFFER_SIZE )
//Parameterize the depth of the PPFIFO
) ping_pong (
.reset (rst | w_control_reset ),
//write
.write_clock (clk ),
.write_ready (w_wfifo_ready ),
.write_activate (w_wfifo_activate ),
.write_fifo_size (w_wfifo_size ),
.write_strobe (w_wfifo_strobe ),
.write_data (w_wfifo_data ),
//read
.read_clock (clk ),
.read_strobe (w_rfifo_strobe ),
.read_ready (w_rfifo_ready ),
.read_activate (w_rfifo_activate ),
.read_count (w_rfifo_size ),
.read_data (w_rfifo_data )
);
ppfifo_data_sink sink(
.clk (clk ),
.rst (rst | w_control_reset ),
.i_rd_rdy (w_rfifo_ready ),
.o_rd_act (w_rfifo_activate ),
.i_rd_size (w_rfifo_size ),
.o_rd_stb (w_rfifo_strobe ),
.i_rd_data (w_rfifo_data )
);
//Asynchronous Logic
assign w_enable = r_control[`CONTROL_ENABLE];
assign w_enable_interrupt = r_control[`CONTROL_ENABLE_INTERRUPT];
assign w_control_reset = r_control[`CONTROL_RESET];
assign w_default_mem_0_base= `DEFAULT_MEM_0_BASE;
assign w_default_mem_1_base= `DEFAULT_MEM_1_BASE;
assign w_status = {30'h0,
w_memory_1_empty,
w_memory_0_empty};
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
r_control <= 0;
//Default base, user can change this from the API
r_memory_0_base <= w_default_mem_0_base;
r_memory_1_base <= w_default_mem_1_base;
//Nothing in the memory initially
r_memory_0_size <= 0;
r_memory_1_size <= 0;
r_memory_0_new_data <= 0;
r_memory_1_new_data <= 0;
r_ppfifo_size_request <= 0;
end
else begin
//Strobes
r_memory_0_new_data <= 0;
r_memory_1_new_data <= 0;
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
REG_CONTROL: begin
r_control <= i_wbs_dat;
end
REG_MEM_0_BASE: begin
r_memory_0_base <= i_wbs_dat;
end
REG_MEM_0_SIZE: begin
r_memory_0_size <= i_wbs_dat;
r_ppfifo_size_request <= i_wbs_dat;
if (i_wbs_dat > 0) begin
r_memory_0_new_data <= 1;
end
end
REG_MEM_1_BASE: begin
r_memory_1_base <= i_wbs_dat;
end
REG_MEM_1_SIZE: begin
r_memory_1_size <= i_wbs_dat;
r_ppfifo_size_request <= i_wbs_dat;
if (i_wbs_dat > 0) begin
r_memory_1_new_data <= 1;
end
end
REG_TOTAL_WRITE_SIZE: begin
end
default: begin
end
endcase
end
else begin
if (!o_wbs_ack) begin //Fix double reads
//read request
case (i_wbs_adr)
REG_CONTROL: begin
o_wbs_dat <= r_control;
end
REG_STATUS: begin
o_wbs_dat <= w_status;
end
REG_MEM_0_BASE: begin
o_wbs_dat <= r_memory_0_base;
end
REG_MEM_0_SIZE: begin
o_wbs_dat <= w_memory_0_count;
end
REG_MEM_1_BASE: begin
o_wbs_dat <= r_memory_1_base;
end
REG_MEM_1_SIZE: begin
o_wbs_dat <= w_memory_1_count;
end
REG_TOTAL_WRITE_SIZE: begin
o_wbs_dat <= r_ppfifo_size_request;
end
default: begin
o_wbs_dat <= 32'h00;
end
endcase
end
end
o_wbs_ack <= 1;
end
end
end
//initerrupt controller
always @ (posedge clk) begin
if (rst) begin
o_wbs_int <= 0;
end
else if (w_enable) begin
if (!w_memory_0_empty && !w_memory_1_empty) begin
o_wbs_int <= 0;
end
if (i_wbs_stb) begin
//de-assert the interrupt on wbs transactions so I can launch another
//interrupt when the wbs is de-asserted
o_wbs_int <= 0;
end
else if (w_memory_0_empty || w_memory_1_empty) begin
o_wbs_int <= 1;
end
end
else begin
//if we're not enable de-assert interrupt
o_wbs_int <= 0;
end
end
endmodule
|
`include "defs.v"
// Bundling CPU and ICache together
module toycpu(
input clk, // clock
input rst, // reset
// Memory bus
input [31:0] bus_data_in, // bus data in
input bus_data_in_ready, // bus data ready
input bus_data_ack, // acknowledge write op
output bus_data_wr, // request data write
output bus_data_rd, // request data read
output [31:0] bus_data_address, // output data address
output [31:0] bus_data_out, // data to be written
// CPU signals
input irq, // IRQ requested
input [3:0] irqn, // IRQ number
output irq_ack, // Interrupt acknowledged and processed
output irq_busy, // Busy doing current interrupt (maintain your fifo outside!)
output [31:0] debug_reg_out,
input [3:0] debug_reg_num,
input debug,
input step,
output step_ack,
input stall
);
wire [31:0] ic_addr;
wire [31:0] ic_data_out;
wire [31:0] ic_bus_data_address;
wire [31:0] ic_data_in;
wire [31:0] data_in;
wire [31:0] data_out;
wire [31:0] data_address;
wire ic_rq;
wire ic_data_out_valid;
wire data_ack;
wire data_wr;
wire data_rd;
wire data_in_ready;
wire ic_data_in_ready;
wire ic_data_rd;
toycpu_core core1(.clk(clk),
.rst(rst),
.ic_addr(ic_addr),
.ic_rq(ic_rq),
.ic_data_out(ic_data_out),
.ic_data_out_valid(ic_data_out_valid),
.data_in(data_in),
.data_in_ready(data_in_ready),
.data_ack(data_ack),
.data_wr(data_wr),
.data_rd(data_rd),
.data_address(data_address),
.data_out(data_out),
.irq(irq),
.irqn(irqn),
.irq_ack(irq_ack),
.irq_busy(irq_busy),
.debug_reg_out(debug_reg_out),
.debug_reg_num(debug_reg_num),
.debug(debug),
.step(step),
.step_ack(step_ack),
.stall(stall)
);
toy_icache cache1 (.clk(clk),
.reset(rst),
.ic_addr(ic_addr),
.ic_rq(ic_rq),
.ic_data_out_valid(ic_data_out_valid),
.ic_data_out(ic_data_out),
.data_in(ic_data_in),
.data_in_ready(ic_data_in_ready),
.data_rd(ic_data_rd),
.data_address(ic_bus_data_address));
wire grant_ic;
wire grant_lsu;
reg ic_rq_cnt;
reg lsu_rq_cnt;
wire gnt2;
wire gnt3;
arbiter arb1 (.clk(clk),
.rst(!rst),
.req0(ic_rq_cnt),
.req1(lsu_rq_cnt),
.req2(0),
.req3(0),
.gnt0(grant_ic),
.gnt1(grant_lsu),
.gnt2(gnt2),
.gnt3(gnt3)
);
always @(posedge clk)
if(!rst) begin
ic_rq_cnt <= 0;
lsu_rq_cnt <= 0;
end else begin
if (ic_data_rd) ic_rq_cnt <= 1;
else if (grant_ic && !bus_data_in_ready) ic_rq_cnt <= 0;
if (data_rd|data_wr) lsu_rq_cnt <= 1;
else if (grant_lsu && !bus_data_in_ready && !bus_data_ack)
lsu_rq_cnt <= 0;
end
assign ic_data_in_ready = grant_ic?bus_data_in_ready:0;
assign data_in_ready = grant_lsu?bus_data_in_ready:0;
assign ic_data_in = grant_ic?bus_data_in:0;
assign data_in = grant_lsu?bus_data_in:0;
// Memory bus combinational logic
assign bus_data_address = grant_ic?ic_bus_data_address:data_address;
assign bus_data_wr = grant_lsu?data_wr:0;
assign bus_data_rd = grant_ic?ic_data_rd:grant_lsu?data_rd:0;
assign bus_data_out = grant_lsu?data_out:0;
assign data_ack = grant_lsu?bus_data_ack:0;
endmodule // toycpu
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBE_P_BLACKBOX_V
`define SKY130_FD_SC_HDLL__PROBE_P_BLACKBOX_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__probe_p (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBE_P_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDLCLKP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__SDLCLKP_PP_BLACKBOX_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdlclkp (
GCLK,
GATE,
CLK ,
SCE ,
VPWR,
VGND
);
output GCLK;
input GATE;
input CLK ;
input SCE ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDLCLKP_PP_BLACKBOX_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_arbiter #
( parameter
CFG_DWIDTH_RATIO = 4,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_REG_GRANT = 0,
CFG_REG_REQ = 0,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_DISABLE_PRIORITY = 1
)
(
ctl_clk,
ctl_reset_n,
// Common
stall_row_arbiter,
stall_col_arbiter,
// Sideband Interface
sb_do_precharge_all,
sb_do_refresh,
sb_do_self_refresh,
sb_do_power_down,
sb_do_deep_pdown,
sb_do_zq_cal,
// TBP Interface
row_req,
col_req,
act_req,
pch_req,
rd_req,
wr_req,
row_grant,
col_grant,
act_grant,
pch_grant,
rd_grant,
wr_grant,
log2_row_grant,
log2_col_grant,
log2_act_grant,
log2_pch_grant,
log2_rd_grant,
log2_wr_grant,
or_row_grant,
or_col_grant,
tbp_activate,
tbp_precharge,
tbp_read,
tbp_write,
tbp_chipsel,
tbp_bank,
tbp_row,
tbp_col,
tbp_size,
tbp_localid,
tbp_dataid,
tbp_ap,
tbp_burst_chop,
tbp_rmw_correct,
tbp_rmw_partial,
tbp_age,
tbp_priority,
// Rank Timer Interface
can_activate,
can_precharge,
can_write,
can_read,
// Arbiter Output Interface
arb_do_write,
arb_do_read,
arb_do_burst_chop,
arb_do_burst_terminate,
arb_do_auto_precharge,
arb_do_rmw_correct,
arb_do_rmw_partial,
arb_do_activate,
arb_do_precharge,
arb_do_precharge_all,
arb_do_refresh,
arb_do_self_refresh,
arb_do_power_down,
arb_do_deep_pdown,
arb_do_zq_cal,
arb_do_lmr,
arb_to_chipsel,
arb_to_chip,
arb_to_bank,
arb_to_row,
arb_to_col,
arb_localid,
arb_dataid,
arb_size
);
localparam AFI_INTF_LOW_PHASE = 0;
localparam AFI_INTF_HIGH_PHASE = 1;
input ctl_clk;
input ctl_reset_n;
// Common
input stall_row_arbiter;
input stall_col_arbiter;
// Sideband Interface
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_precharge_all;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_refresh;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_self_refresh;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_power_down;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_deep_pdown;
input [CFG_MEM_IF_CHIP - 1 : 0] sb_do_zq_cal;
// TBP Interface
input [CFG_CTL_TBP_NUM - 1 : 0] row_req;
input [CFG_CTL_TBP_NUM - 1 : 0] col_req;
input [CFG_CTL_TBP_NUM - 1 : 0] act_req;
input [CFG_CTL_TBP_NUM - 1 : 0] pch_req;
input [CFG_CTL_TBP_NUM - 1 : 0] rd_req;
input [CFG_CTL_TBP_NUM - 1 : 0] wr_req;
output [CFG_CTL_TBP_NUM - 1 : 0] row_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] col_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] act_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] pch_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] rd_grant;
output [CFG_CTL_TBP_NUM - 1 : 0] wr_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_row_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_col_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_act_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_pch_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_rd_grant;
output [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_wr_grant;
output or_row_grant;
output or_col_grant;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_activate;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_precharge;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_read;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_write;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_chipsel;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] tbp_bank;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] tbp_row;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] tbp_col;
input [(CFG_CTL_TBP_NUM * CFG_INT_SIZE_WIDTH) - 1 : 0] tbp_size;
input [(CFG_CTL_TBP_NUM * CFG_LOCAL_ID_WIDTH) - 1 : 0] tbp_localid;
input [(CFG_CTL_TBP_NUM * CFG_DATA_ID_WIDTH) - 1 : 0] tbp_dataid;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_ap;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_burst_chop;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_correct;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_rmw_partial;
input [(CFG_CTL_TBP_NUM * CFG_CTL_TBP_NUM) - 1 : 0] tbp_age;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_priority;
// Rank Timer Interface
input [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
input [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
input [CFG_CTL_TBP_NUM - 1 : 0] can_write;
input [CFG_CTL_TBP_NUM - 1 : 0] can_read;
// Arbiter Output Interface
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
output [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
output [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
//--------------------------------------------------------------------------------------------------------
//
// [START] Registers & Wires
//
//--------------------------------------------------------------------------------------------------------
// General
wire one = 1'b1;
wire zero = 1'b0;
// TBP Interface
reg [CFG_CTL_TBP_NUM - 1 : 0] row_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] act_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] pch_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] rd_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] wr_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_row_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_col_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_act_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_pch_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_rd_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_wr_grant;
reg or_row_grant;
reg or_col_grant;
reg or_act_grant;
reg or_pch_grant;
reg or_rd_grant;
reg or_wr_grant;
// Arbiter Output Interface
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
// Common
reg granted_read [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_write [CFG_CTL_TBP_NUM - 1 : 0];
// WSHUM: See Case:70614
// Flatten these into 1-D arrays to avoid using a 2-D array element as an index
// into another array, which causes data mismatches in Modelsim SE 10.1b
// granted_chipsel_r[tbp] becomes
// granted_chipsel_r[CFG_MEM_IF_CS_WIDTH*(tbp+1) - 1 : CFG_MEM_IF_CS_WIDTH * tbp]
//reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] granted_chipsel_r [CFG_CTL_TBP_NUM - 1 : 0];
//reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] granted_chipsel_c [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_CS_WIDTH*CFG_CTL_TBP_NUM - 1 : 0] granted_chipsel_r;
reg [CFG_MEM_IF_CS_WIDTH*CFG_CTL_TBP_NUM - 1 : 0] granted_chipsel_c;
reg [CFG_MEM_IF_CHIP - 1 : 0] granted_to_chip_r ;
reg [CFG_MEM_IF_CHIP - 1 : 0] granted_to_chip_c ;
reg [CFG_MEM_IF_BA_WIDTH - 1 : 0] granted_bank_r [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_BA_WIDTH - 1 : 0] granted_bank_c [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_ROW_WIDTH - 1 : 0] granted_row_r [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_ROW_WIDTH - 1 : 0] granted_row_c [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_MEM_IF_COL_WIDTH - 1 : 0] granted_col [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_INT_SIZE_WIDTH - 1 : 0] granted_size [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_DATA_ID_WIDTH - 1 : 0] granted_dataid [CFG_CTL_TBP_NUM - 1 : 0];
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] granted_localid [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_ap [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_burst_chop [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_rmw_correct [CFG_CTL_TBP_NUM - 1 : 0];
reg granted_rmw_partial [CFG_CTL_TBP_NUM - 1 : 0];
// Arbiter
reg [CFG_CTL_TBP_NUM - 1 : 0] int_act_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_pch_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_col_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_act_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_pch_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_rd_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_wr_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_row_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] oldest_col_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] act_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] pch_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] rd_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] wr_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] row_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] col_req_with_priority;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_row_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_act_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_pch_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_rd_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_wr_grant;
reg internal_or_row_grant;
reg internal_or_col_grant;
reg int_or_row_grant;
reg int_or_col_grant;
reg int_or_act_grant;
reg int_or_pch_grant;
reg int_or_rd_grant;
reg int_or_wr_grant;
reg granted_or_row_grant;
reg granted_or_col_grant;
reg granted_or_act_grant;
reg granted_or_pch_grant;
reg granted_or_rd_grant;
reg granted_or_wr_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_row_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_col_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_act_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_pch_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_rd_grant;
reg [CFG_CTL_TBP_NUM - 1 : 0] granted_wr_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_row_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_col_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_act_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_pch_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_rd_grant;
reg [log2(CFG_CTL_TBP_NUM) - 1 : 0] log2_granted_wr_grant;
wire [CFG_CTL_TBP_NUM - 1 : 0] all_grant;
//--------------------------------------------------------------------------------------------------------
//
// [END] Registers & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Outputs
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Granted logic specific grant signals
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
granted_or_row_grant = or_row_grant;
granted_or_col_grant = or_col_grant;
granted_or_act_grant = or_act_grant;
granted_or_pch_grant = or_pch_grant;
granted_or_rd_grant = or_rd_grant;
granted_or_wr_grant = or_wr_grant;
granted_row_grant = row_grant;
granted_col_grant = col_grant;
granted_act_grant = act_grant;
granted_pch_grant = pch_grant;
granted_rd_grant = rd_grant;
granted_wr_grant = wr_grant;
log2_granted_row_grant = log2_row_grant;
log2_granted_col_grant = log2_col_grant;
log2_granted_act_grant = log2_act_grant;
log2_granted_pch_grant = log2_pch_grant;
log2_granted_rd_grant = log2_rd_grant;
log2_granted_wr_grant = log2_wr_grant;
end
//----------------------------------------------------------------------------------------------------
// Sideband outputs
//----------------------------------------------------------------------------------------------------
// Precharge all
always @ (*)
begin
arb_do_precharge_all = {CFG_AFI_INTF_PHASE_NUM{sb_do_precharge_all}};
end
// Refresh
always @ (*)
begin
arb_do_refresh = {CFG_AFI_INTF_PHASE_NUM{sb_do_refresh}};
end
// Self refresh
always @ (*)
begin
arb_do_self_refresh = {CFG_AFI_INTF_PHASE_NUM{sb_do_self_refresh}};
end
// Power down
always @ (*)
begin
arb_do_power_down = {CFG_AFI_INTF_PHASE_NUM{sb_do_power_down}};
end
// Power down
always @ (*)
begin
arb_do_deep_pdown = {CFG_AFI_INTF_PHASE_NUM{sb_do_deep_pdown}};
end
// ZQ calibration
always @ (*)
begin
arb_do_zq_cal = {CFG_AFI_INTF_PHASE_NUM{sb_do_zq_cal}};
end
// LMR
always @ (*)
begin
arb_do_lmr = {CFG_AFI_INTF_PHASE_NUM{zero}};
end
//----------------------------------------------------------------------------------------------------
// Non arbiter type aware outputs
//----------------------------------------------------------------------------------------------------
// Burst chop
always @ (*)
begin
arb_do_burst_chop = {CFG_AFI_INTF_PHASE_NUM{granted_burst_chop [CFG_CTL_TBP_NUM - 1]}};
end
// Burst terminate
always @ (*)
begin
arb_do_burst_terminate = 0;
end
// RMW Correct
always @ (*)
begin
arb_do_rmw_correct = {CFG_AFI_INTF_PHASE_NUM{granted_rmw_correct [CFG_CTL_TBP_NUM - 1]}};
end
// RMW Partial
always @ (*)
begin
arb_do_rmw_partial = {CFG_AFI_INTF_PHASE_NUM{granted_rmw_partial [CFG_CTL_TBP_NUM - 1]}};
end
// LMR
// SPYGLASS FIX: altera_mem_if_ddr3_emif_test.altera_mem_if_ddr3_emif_inst.c0.ng0.alt_mem_ddrx_controller_top_inst.controller_inst.arb_do_lmr[1:0]' has multiple simultaneous drivers
// always @ (*)
// begin
// arb_do_lmr = 0;
// end
// Local ID
always @ (*)
begin
arb_localid = granted_localid [CFG_CTL_TBP_NUM - 1];
end
// Data ID
always @ (*)
begin
arb_dataid = granted_dataid [CFG_CTL_TBP_NUM - 1];
end
// Size
always @ (*)
begin
arb_size = granted_size [CFG_CTL_TBP_NUM - 1];
end
// Column address
// column command will only require column address, therefore there will be no conflcting column addresses
always @ (*)
begin
arb_to_col = {CFG_AFI_INTF_PHASE_NUM{granted_col [CFG_CTL_TBP_NUM - 1]}};
end
//----------------------------------------------------------------------------------------------------
// Arbiter type aware outputs
//----------------------------------------------------------------------------------------------------
generate
begin
if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
// Write
always @ (*)
begin
arb_do_write = 0;
arb_do_write [AFI_INTF_LOW_PHASE] = granted_wr_grant;
end
// Read
always @ (*)
begin
arb_do_read = 0;
arb_do_read [AFI_INTF_LOW_PHASE] = granted_rd_grant;
end
// Auto precharge
always @ (*)
begin
arb_do_auto_precharge = 0;
arb_do_auto_precharge [AFI_INTF_LOW_PHASE] = granted_ap [CFG_CTL_TBP_NUM - 1];
end
// Activate
always @ (*)
begin
arb_do_activate = 0;
arb_do_activate [AFI_INTF_HIGH_PHASE] = granted_act_grant;
end
// Precharge
always @ (*)
begin
arb_do_precharge = 0;
arb_do_precharge [AFI_INTF_HIGH_PHASE] = granted_pch_grant;
end
// Chip address
// chipsel to to_chip address conversion
always @ (*)
begin
granted_to_chip_r = 0;
if (|granted_row_grant)
granted_to_chip_r [granted_chipsel_r [CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM) - 1 : CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM-1)]] = 1'b1;
end
always @ (*)
begin
granted_to_chip_c = 0;
if (|granted_col_grant)
granted_to_chip_c [granted_chipsel_c [CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM) - 1 : CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM-1)]] = 1'b1;
end
always @ (*)
begin
arb_to_chipsel = {granted_chipsel_r [CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM) - 1 : CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM-1)], granted_chipsel_c [CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM) - 1 : CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM-1)]};
end
always @ (*)
begin
arb_to_chip = {granted_to_chip_r, granted_to_chip_c};
end
// Bank address
always @ (*)
begin
arb_to_bank = {granted_bank_r [CFG_CTL_TBP_NUM - 1], granted_bank_c [CFG_CTL_TBP_NUM - 1]};
end
// Row address
always @ (*)
begin
arb_to_row = {granted_row_r [CFG_CTL_TBP_NUM - 1], granted_row_c [CFG_CTL_TBP_NUM - 1]};
end
end
else
begin
// Write
always @ (*)
begin
arb_do_write = 0;
arb_do_write [AFI_INTF_HIGH_PHASE] = |(tbp_write & granted_col_grant);
end
// Read
always @ (*)
begin
arb_do_read = 0;
arb_do_read [AFI_INTF_HIGH_PHASE] = |(tbp_read & granted_col_grant);
end
// Auto precharge
always @ (*)
begin
arb_do_auto_precharge = 0;
arb_do_auto_precharge [AFI_INTF_HIGH_PHASE] = granted_ap [CFG_CTL_TBP_NUM - 1];
end
// Activate
always @ (*)
begin
arb_do_activate = 0;
arb_do_activate [AFI_INTF_LOW_PHASE] = |(tbp_activate & granted_row_grant);
end
// Precharge
always @ (*)
begin
arb_do_precharge = 0;
arb_do_precharge [AFI_INTF_LOW_PHASE] = |(tbp_precharge & granted_row_grant);
end
// Chip address
// chipsel to to_chip address conversion
always @ (*)
begin
granted_to_chip_r = 0;
if (|granted_row_grant)
granted_to_chip_r [granted_chipsel_r [CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM) - 1 : CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM-1)]] = 1'b1;
end
always @ (*)
begin
granted_to_chip_c = 0;
if (|granted_col_grant)
granted_to_chip_c [granted_chipsel_c [CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM) - 1 : CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM-1)]] = 1'b1;
end
always @ (*)
begin
arb_to_chipsel = {granted_chipsel_c [CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM) - 1 : CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM-1)], granted_chipsel_r [CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM) - 1 : CFG_MEM_IF_CS_WIDTH*(CFG_CTL_TBP_NUM-1)]};
end
always @ (*)
begin
arb_to_chip = {granted_to_chip_c, granted_to_chip_r};
end
// Bank address
always @ (*)
begin
arb_to_bank = {granted_bank_c [CFG_CTL_TBP_NUM - 1], granted_bank_r [CFG_CTL_TBP_NUM - 1]};
end
// Row address
always @ (*)
begin
arb_to_row = {granted_row_c [CFG_CTL_TBP_NUM - 1], granted_row_r [CFG_CTL_TBP_NUM - 1]};
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Granted outputs
//----------------------------------------------------------------------------------------------------
// Chip address
always @ (*)
begin
granted_chipsel_r [CFG_MEM_IF_CS_WIDTH-1 : 0] = {CFG_MEM_IF_CS_WIDTH {granted_row_grant [0]}} & tbp_chipsel [CFG_MEM_IF_CS_WIDTH - 1 : 0];
granted_chipsel_c [CFG_MEM_IF_CS_WIDTH-1 : 0] = {CFG_MEM_IF_CS_WIDTH {granted_col_grant [0]}} & tbp_chipsel [CFG_MEM_IF_CS_WIDTH - 1 : 0];
end
// Bank address
always @ (*)
begin
granted_bank_r [0] = {CFG_MEM_IF_BA_WIDTH {granted_row_grant [0]}} & tbp_bank [CFG_MEM_IF_BA_WIDTH - 1 : 0];
granted_bank_c [0] = {CFG_MEM_IF_BA_WIDTH {granted_col_grant [0]}} & tbp_bank [CFG_MEM_IF_BA_WIDTH - 1 : 0];
end
// Row address
always @ (*)
begin
granted_row_r [0] = {CFG_MEM_IF_ROW_WIDTH{granted_row_grant [0]}} & tbp_row [CFG_MEM_IF_ROW_WIDTH - 1 : 0];
granted_row_c [0] = {CFG_MEM_IF_ROW_WIDTH{granted_col_grant [0]}} & tbp_row [CFG_MEM_IF_ROW_WIDTH - 1 : 0];
end
// Column address
always @ (*)
begin
granted_col [0] = {CFG_MEM_IF_COL_WIDTH{granted_col_grant [0]}} & tbp_col [CFG_MEM_IF_COL_WIDTH - 1 : 0];
end
// Size
always @ (*)
begin
granted_size [0] = {CFG_INT_SIZE_WIDTH {granted_col_grant [0]}} & tbp_size [CFG_INT_SIZE_WIDTH - 1 : 0];
end
// Local ID
always @ (*)
begin
granted_localid [0] = {CFG_LOCAL_ID_WIDTH {granted_col_grant [0]}} & tbp_localid [CFG_LOCAL_ID_WIDTH - 1 : 0];
end
// Data ID
always @ (*)
begin
granted_dataid [0] = {CFG_DATA_ID_WIDTH {granted_col_grant [0]}} & tbp_dataid [CFG_DATA_ID_WIDTH - 1 : 0];
end
// Auto precharge
always @ (*)
begin
granted_ap [0] = granted_col_grant [0] & tbp_ap [ 0];
end
// Burst Chop
always @ (*)
begin
granted_burst_chop [0] = granted_col_grant [0] & tbp_burst_chop [ 0];
end
// RMW Correct
always @ (*)
begin
granted_rmw_correct [0] = granted_col_grant [0] & tbp_rmw_correct [ 0];
end
// RMW Partial
always @ (*)
begin
granted_rmw_partial [0] = granted_col_grant [0] & tbp_rmw_partial [ 0];
end
generate
begin
genvar j_tbp;
for (j_tbp = 1;j_tbp < CFG_CTL_TBP_NUM;j_tbp = j_tbp + 1)
begin : granted_information_per_tbp
wire [CFG_MEM_IF_CS_WIDTH - 1 : 0] chipsel_addr = tbp_chipsel [(j_tbp + 1) * CFG_MEM_IF_CS_WIDTH - 1 : j_tbp * CFG_MEM_IF_CS_WIDTH ];
wire [CFG_MEM_IF_BA_WIDTH - 1 : 0] bank_addr = tbp_bank [(j_tbp + 1) * CFG_MEM_IF_BA_WIDTH - 1 : j_tbp * CFG_MEM_IF_BA_WIDTH ];
wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0] row_addr = tbp_row [(j_tbp + 1) * CFG_MEM_IF_ROW_WIDTH - 1 : j_tbp * CFG_MEM_IF_ROW_WIDTH];
wire [CFG_MEM_IF_COL_WIDTH - 1 : 0] col_addr = tbp_col [(j_tbp + 1) * CFG_MEM_IF_COL_WIDTH - 1 : j_tbp * CFG_MEM_IF_COL_WIDTH];
wire [CFG_INT_SIZE_WIDTH - 1 : 0] size = tbp_size [(j_tbp + 1) * CFG_INT_SIZE_WIDTH - 1 : j_tbp * CFG_INT_SIZE_WIDTH ];
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] localid = tbp_localid [(j_tbp + 1) * CFG_LOCAL_ID_WIDTH - 1 : j_tbp * CFG_LOCAL_ID_WIDTH ];
wire [CFG_DATA_ID_WIDTH - 1 : 0] dataid = tbp_dataid [(j_tbp + 1) * CFG_DATA_ID_WIDTH - 1 : j_tbp * CFG_DATA_ID_WIDTH ];
wire ap = tbp_ap [(j_tbp + 1) - 1 : j_tbp ];
wire burst_chop = tbp_burst_chop [(j_tbp + 1) - 1 : j_tbp ];
wire rmw_correct = tbp_rmw_correct [(j_tbp + 1) - 1 : j_tbp ];
wire rmw_partial = tbp_rmw_partial [(j_tbp + 1) - 1 : j_tbp ];
// Chip address
always @ (*)
begin
granted_chipsel_r [CFG_MEM_IF_CS_WIDTH*(j_tbp+1) - 1 : CFG_MEM_IF_CS_WIDTH*j_tbp] = ({CFG_MEM_IF_CS_WIDTH {granted_row_grant [j_tbp]}} & chipsel_addr) | granted_chipsel_r [CFG_MEM_IF_CS_WIDTH*(j_tbp) - 1 : CFG_MEM_IF_CS_WIDTH*(j_tbp-1)];
granted_chipsel_c [CFG_MEM_IF_CS_WIDTH*(j_tbp+1) - 1 : CFG_MEM_IF_CS_WIDTH*j_tbp] = ({CFG_MEM_IF_CS_WIDTH {granted_col_grant [j_tbp]}} & chipsel_addr) | granted_chipsel_c [CFG_MEM_IF_CS_WIDTH*(j_tbp) - 1 : CFG_MEM_IF_CS_WIDTH*(j_tbp-1)];
end
// Bank address
always @ (*)
begin
granted_bank_r [j_tbp] = ({CFG_MEM_IF_BA_WIDTH {granted_row_grant [j_tbp]}} & bank_addr ) | granted_bank_r [j_tbp - 1];
granted_bank_c [j_tbp] = ({CFG_MEM_IF_BA_WIDTH {granted_col_grant [j_tbp]}} & bank_addr ) | granted_bank_c [j_tbp - 1];
end
// Row address
always @ (*)
begin
granted_row_r [j_tbp] = ({CFG_MEM_IF_ROW_WIDTH{granted_row_grant [j_tbp]}} & row_addr ) | granted_row_r [j_tbp - 1];
granted_row_c [j_tbp] = ({CFG_MEM_IF_ROW_WIDTH{granted_col_grant [j_tbp]}} & row_addr ) | granted_row_c [j_tbp - 1];
end
// Column address
always @ (*)
begin
granted_col [j_tbp] = ({CFG_MEM_IF_COL_WIDTH{granted_col_grant [j_tbp]}} & col_addr ) | granted_col [j_tbp - 1];
end
// Size
always @ (*)
begin
granted_size [j_tbp] = ({CFG_INT_SIZE_WIDTH {granted_col_grant [j_tbp]}} & size ) | granted_size [j_tbp - 1];
end
// Local ID
always @ (*)
begin
granted_localid [j_tbp] = ({CFG_LOCAL_ID_WIDTH {granted_col_grant [j_tbp]}} & localid ) | granted_localid [j_tbp - 1];
end
// Data ID
always @ (*)
begin
granted_dataid [j_tbp] = ({CFG_DATA_ID_WIDTH {granted_col_grant [j_tbp]}} & dataid ) | granted_dataid [j_tbp - 1];
end
// Auto precharge
always @ (*)
begin
granted_ap [j_tbp] = ( granted_col_grant [j_tbp] & ap ) | granted_ap [j_tbp - 1];
end
// Auto precharge
always @ (*)
begin
granted_burst_chop [j_tbp] = ( granted_col_grant [j_tbp] & burst_chop ) | granted_burst_chop [j_tbp - 1];
end
// RMW Correct
always @ (*)
begin
granted_rmw_correct [j_tbp] = ( granted_col_grant [j_tbp] & rmw_correct ) | granted_rmw_correct [j_tbp - 1];
end
// RMW Partial
always @ (*)
begin
granted_rmw_partial [j_tbp] = ( granted_col_grant [j_tbp] & rmw_partial ) | granted_rmw_partial [j_tbp - 1];
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Outputs
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Arbiter
//
// Arbitration Rules (Priority Command-Aging Arbiter):
//
// - If only one master is requesting, grant that master immediately ELSE
// - If two of more masters are requesting:
// - Grant the request with priority ELSE
// - Grant read request over write request ELSE
// - Grant oldest request
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Common logic
//----------------------------------------------------------------------------------------------------
// Indicate OR of both grant signal
assign all_grant = row_grant | col_grant;
//----------------------------------------------------------------------------------------------------
// Priority Command-aging logic
//----------------------------------------------------------------------------------------------------
// ==========Command-Aging==========
//
// The following logic will check for the oldest requesting commands by cross checking between age dependencies & request
// eg: Let say we have 4 TBPs and TBP is loaded in the following fashion: TBP0, TBP1, TBP2, TBP3
// Age dependecies will have the following value:
// TBP0 age - 0000
// TBP1 age - 0001
// TBP2 age - 0011
// TBP3 age - 0111
// Let say TBP1 and TBP2 are requesting at the same time, we would want the command-aging logic to pick TBP1 instead of TBP2
// TBP2 have age dependencies on TBP1, this will cause oldest_req[2] signal to be set to '0'
// TBP1 have no age dependencies on TBP2, this will cause oldest_req[1] signal to be set to '1'
// So the oldest_req signal will have "0010"
//
// ==========Priority==========
//
// The following logic will have similar logic as command-aging logic, this logic will pick commands with priority bit set
// if there are more than 1 priority command, it will pick the oldest priority command
// eg: Let say we have 4 TBPs and TBP is loaded in the following fashion: TBP0, TBP1, TBP2, TBP3
// Age dependecies and priority bit will have the following value:
// TBP0 age - 0000 priority - 0
// TBP1 age - 0001 priority - 1
// TBP2 age - 0011 priority - 1
// TBP3 age - 0111 priority - 0
// Let say all TBPs are requesting at the same time, priority_req [1] will be set to '1' because it is the oldest priority command
// and the rest will be set to '0'
// If there is/are priority command/s, we need to select between those priority command
// if there is no priority command, we set int_priority to all '1'
// this will cause arbiter to select between all commands which will provide with similar result as non-priority command-aging arbiter
always @ (*)
begin
int_act_priority = {CFG_CTL_TBP_NUM{one}};
int_pch_priority = {CFG_CTL_TBP_NUM{one}};
if (CFG_DISABLE_PRIORITY == 1)
begin
int_col_priority = {CFG_CTL_TBP_NUM{one}};
end
else
begin
if ((tbp_priority & col_req) == 0)
begin
int_col_priority = {CFG_CTL_TBP_NUM{one}};
end
else
begin
int_col_priority = tbp_priority;
end
end
end
generate
begin
genvar k_tbp;
for (k_tbp = 0;k_tbp < CFG_CTL_TBP_NUM;k_tbp = k_tbp + 1)
begin : priority_request_per_tbp
wire [CFG_CTL_TBP_NUM - 1 : 0] current_age = tbp_age [(k_tbp + 1) * CFG_CTL_TBP_NUM - 1 : k_tbp * CFG_CTL_TBP_NUM];
reg pre_calculated_act_info;
reg pre_calculated_pch_info;
reg pre_calculated_rd_info;
reg pre_calculated_wr_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_act_age_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_pch_age_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_rd_age_info;
reg [CFG_CTL_TBP_NUM - 1 : 0] pre_calculated_wr_age_info;
if (CFG_REG_REQ)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_act_info <= 1'b0;
pre_calculated_pch_info <= 1'b0;
pre_calculated_rd_info <= 1'b0;
pre_calculated_wr_info <= 1'b0;
end
else
begin
pre_calculated_act_info <= int_act_priority [k_tbp];
pre_calculated_pch_info <= int_pch_priority [k_tbp];
pre_calculated_rd_info <= int_col_priority [k_tbp];
pre_calculated_wr_info <= int_col_priority [k_tbp];
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_act_age_info <= 0;
pre_calculated_pch_age_info <= 0;
pre_calculated_rd_age_info <= 0;
pre_calculated_wr_age_info <= 0;
end
else
begin
pre_calculated_act_age_info <= current_age & int_act_priority;
pre_calculated_pch_age_info <= current_age & int_pch_priority;
pre_calculated_rd_age_info <= current_age & int_col_priority;
pre_calculated_wr_age_info <= current_age & int_col_priority;
end
end
end
else
begin
always @ (*)
begin
pre_calculated_act_info = int_act_priority [k_tbp];
pre_calculated_pch_info = int_pch_priority [k_tbp];
pre_calculated_rd_info = int_col_priority [k_tbp];
pre_calculated_wr_info = int_col_priority [k_tbp];
end
always @ (*)
begin
pre_calculated_act_age_info = current_age & int_act_priority;
pre_calculated_pch_age_info = current_age & int_pch_priority;
pre_calculated_rd_age_info = current_age & int_col_priority;
pre_calculated_wr_age_info = current_age & int_col_priority;
end
end
always @ (*)
begin
oldest_act_req_with_priority [k_tbp] = pre_calculated_act_info & act_req [k_tbp] & can_activate [k_tbp] & ~|(pre_calculated_act_age_info & act_req & can_activate );
oldest_pch_req_with_priority [k_tbp] = pre_calculated_pch_info & pch_req [k_tbp] & can_precharge [k_tbp] & ~|(pre_calculated_pch_age_info & pch_req & can_precharge);
oldest_rd_req_with_priority [k_tbp] = pre_calculated_rd_info & rd_req [k_tbp] & can_read [k_tbp] & ~|(pre_calculated_rd_age_info & rd_req & can_read );
oldest_wr_req_with_priority [k_tbp] = pre_calculated_wr_info & wr_req [k_tbp] & can_write [k_tbp] & ~|(pre_calculated_wr_age_info & wr_req & can_write );
end
always @ (*)
begin
act_req_with_priority [k_tbp] = pre_calculated_act_info & act_req [k_tbp] & can_activate [k_tbp];
pch_req_with_priority [k_tbp] = pre_calculated_pch_info & pch_req [k_tbp] & can_precharge [k_tbp];
rd_req_with_priority [k_tbp] = pre_calculated_rd_info & rd_req [k_tbp] & can_read [k_tbp];
wr_req_with_priority [k_tbp] = pre_calculated_wr_info & wr_req [k_tbp] & can_write [k_tbp];
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Arbiter logic
//----------------------------------------------------------------------------------------------------
generate
begin
if (CFG_DWIDTH_RATIO == 2)
begin
// Full rate arbiter
always @ (*)
begin
int_row_grant = 0;
int_col_grant = 0;
int_act_grant = 0;
int_pch_grant = 0;
int_rd_grant = 0;
int_wr_grant = 0;
int_or_row_grant = 1'b0;
int_or_col_grant = 1'b0;
int_or_act_grant = 1'b0;
int_or_pch_grant = 1'b0;
int_or_rd_grant = 1'b0;
int_or_wr_grant = 1'b0;
if (!stall_col_arbiter && !internal_or_col_grant && |rd_req_with_priority)
begin
int_col_grant = oldest_rd_req_with_priority;
int_rd_grant = oldest_rd_req_with_priority;
int_or_col_grant = 1'b1;
int_or_rd_grant = 1'b1;
end
else if (!stall_col_arbiter && !internal_or_col_grant && |wr_req_with_priority)
begin
int_col_grant = oldest_wr_req_with_priority;
int_wr_grant = oldest_wr_req_with_priority;
int_or_col_grant = 1'b1;
int_or_wr_grant = 1'b1;
end
else if (!stall_row_arbiter && !internal_or_row_grant && |pch_req_with_priority)
begin
int_row_grant = oldest_pch_req_with_priority;
int_pch_grant = oldest_pch_req_with_priority;
int_or_row_grant = 1'b1;
int_or_pch_grant = 1'b1;
end
else if (!stall_row_arbiter && !internal_or_row_grant && |act_req_with_priority)
begin
int_row_grant = oldest_act_req_with_priority;
int_act_grant = oldest_act_req_with_priority;
int_or_row_grant = 1'b1;
int_or_act_grant = 1'b1;
end
end
end
else
begin
// Half and quarter rate arbiter
// Row arbiter
always @ (*)
begin
int_row_grant = 0;
int_act_grant = 0;
int_pch_grant = 0;
int_or_row_grant = 1'b0;
int_or_act_grant = 1'b0;
int_or_pch_grant = 1'b0;
if (!stall_row_arbiter && !internal_or_row_grant && |pch_req_with_priority)
begin
int_row_grant = oldest_pch_req_with_priority;
int_pch_grant = oldest_pch_req_with_priority;
int_or_row_grant = 1'b1;
int_or_pch_grant = 1'b1;
end
else if (!stall_row_arbiter && !internal_or_row_grant && |act_req_with_priority)
begin
int_row_grant = oldest_act_req_with_priority;
int_act_grant = oldest_act_req_with_priority;
int_or_row_grant = 1'b1;
int_or_act_grant = 1'b1;
end
end
// Column arbiter
always @ (*)
begin
int_col_grant = 0;
int_rd_grant = 0;
int_wr_grant = 0;
int_or_col_grant = 1'b0;
int_or_rd_grant = 1'b0;
int_or_wr_grant = 1'b0;
if (!stall_col_arbiter && !internal_or_col_grant && |rd_req_with_priority)
begin
int_col_grant = oldest_rd_req_with_priority;
int_rd_grant = oldest_rd_req_with_priority;
int_or_col_grant = 1'b1;
int_or_rd_grant = 1'b1;
end
else if (!stall_col_arbiter && !internal_or_col_grant && |wr_req_with_priority)
begin
int_col_grant = oldest_wr_req_with_priority;
int_wr_grant = oldest_wr_req_with_priority;
int_or_col_grant = 1'b1;
int_or_wr_grant = 1'b1;
end
end
end
end
endgenerate
generate
begin
if (CFG_REG_GRANT == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
row_grant <= 0;
col_grant <= 0;
act_grant <= 0;
pch_grant <= 0;
rd_grant <= 0;
wr_grant <= 0;
or_row_grant <= 0;
or_col_grant <= 0;
or_act_grant <= 0;
or_pch_grant <= 0;
or_rd_grant <= 0;
or_wr_grant <= 0;
end
else
begin
row_grant <= int_row_grant;
col_grant <= int_col_grant;
act_grant <= int_act_grant;
pch_grant <= int_pch_grant;
rd_grant <= int_rd_grant;
wr_grant <= int_wr_grant;
or_row_grant <= int_or_row_grant;
or_col_grant <= int_or_col_grant;
or_act_grant <= int_or_act_grant;
or_pch_grant <= int_or_pch_grant;
or_rd_grant <= int_or_rd_grant;
or_wr_grant <= int_or_wr_grant;
end
end
always @ (*)
begin
log2_row_grant = log2(row_grant);
log2_col_grant = log2(col_grant);
log2_act_grant = log2(act_grant);
log2_pch_grant = log2(pch_grant);
log2_rd_grant = log2(rd_grant );
log2_wr_grant = log2(wr_grant );
end
always @ (*)
begin
internal_or_row_grant = or_row_grant;
internal_or_col_grant = or_col_grant;
end
end
else
begin
always @ (*)
begin
row_grant = int_row_grant;
col_grant = int_col_grant;
act_grant = int_act_grant;
pch_grant = int_pch_grant;
rd_grant = int_rd_grant;
wr_grant = int_wr_grant;
log2_row_grant = log2(int_row_grant);
log2_col_grant = log2(int_col_grant);
log2_act_grant = log2(int_act_grant);
log2_pch_grant = log2(int_pch_grant);
log2_rd_grant = log2(int_rd_grant );
log2_wr_grant = log2(int_wr_grant );
or_row_grant = int_or_row_grant;
or_col_grant = int_or_col_grant;
or_act_grant = int_or_act_grant;
or_pch_grant = int_or_pch_grant;
or_rd_grant = int_or_rd_grant;
or_wr_grant = int_or_wr_grant;
end
always @ (*)
begin
internal_or_row_grant = zero; // Hardwire to '0' because it's not require when col grant reg mode is disabled
internal_or_col_grant = zero; // Hardwire to '0' because it's not require when col grant reg mode is disabled
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Arbiter
//
//--------------------------------------------------------------------------------------------------------
function integer log2;
input [31 : 0] value;
integer i;
begin
log2 = 0;
for(i = 0;2 ** i < value;i = i + 1)
begin
log2 = i + 1;
end
end
endfunction
endmodule
|
/*****************************************************************
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: byte_group_io.v,v 1.3.44.3 2011/05/30 10:45:53 pboya Exp $
// $Author: pboya $
// $DateTime: $
// $Change: $
// Description:
// This verilog file is a paramertizable I/O termination for
// the single byte lane.
// to create a N byte-lane wide phy.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
//////////////////////////////////////////////////////////////////
*****************************************************************/
`timescale 1ps/1ps
module byte_group_io #(
parameter PO_DATA_CTL = "FALSE",
// bit lane existance
parameter BITLANES = 12'b1111_1111_1111,
parameter BITLANES_OUTONLY = 12'b0000_0000_0000,
parameter OSERDES_DATA_RATE = "DDR",
parameter OSERDES_DATA_WIDTH = 4,
parameter DIFFERENTIAL_DQS = "TRUE",
parameter IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter IDELAYE2_IDELAY_VALUE = 00,
parameter IODELAY_GRP = "IODELAY_MIG",
// local usage only, don't pass down
parameter BUS_WIDTH = 12
)
(
input [9:0] mem_dq_in,
output [BUS_WIDTH-1:0] mem_dq_out,
output [BUS_WIDTH-1:0] mem_dq_ts,
input mem_dqs_in,
output mem_dqs_out,
output mem_dqs_ts,
output [(4*10)-1:0] iserdes_dout, // 2 extra 12-bit lanes not used
output dqs_to_phaser,
input iserdes_clk,
input iserdes_clkb,
input iserdes_clkdiv,
input phy_clk,
input rst,
input oserdes_rst,
input iserdes_rst,
input [1:0] oserdes_dqs,
input [1:0] oserdes_dqsts,
input [(4*BUS_WIDTH)-1:0] oserdes_dq,
input [1:0] oserdes_dqts,
input oserdes_clk,
input oserdes_clk_delayed,
input oserdes_clkdiv,
input idelay_inc,
input idelay_ce,
input idelay_ld,
input idelayctrl_refclk
);
/// INSTANCES
localparam ISERDES_DQ_DATA_RATE = "DDR";
localparam ISERDES_DQ_DATA_WIDTH = 4;
localparam ISERDES_DQ_DYN_CLKDIV_INV_EN = "FALSE";
localparam ISERDES_DQ_DYN_CLK_INV_EN = "FALSE";
localparam ISERDES_DQ_INIT_Q1 = 1'b0;
localparam ISERDES_DQ_INIT_Q2 = 1'b0;
localparam ISERDES_DQ_INIT_Q3 = 1'b0;
localparam ISERDES_DQ_INIT_Q4 = 1'b0;
localparam ISERDES_DQ_INTERFACE_TYPE = "MEMORY_DDR3";
localparam ISERDES_NUM_CE = 2;
localparam ISERDES_DQ_IOBDELAY = "IFD";
localparam ISERDES_DQ_OFB_USED = "FALSE";
localparam ISERDES_DQ_SERDES_MODE = "MASTER";
localparam ISERDES_DQ_SRVAL_Q1 = 1'b0;
localparam ISERDES_DQ_SRVAL_Q2 = 1'b0;
localparam ISERDES_DQ_SRVAL_Q3 = 1'b0;
localparam ISERDES_DQ_SRVAL_Q4 = 1'b0;
wire [BUS_WIDTH-1:0] data_in_dly;
wire [BUS_WIDTH-1:0] oserdes_dq_buf;
wire [BUS_WIDTH-1:0] oserdes_dqts_buf;
wire oserdes_dqs_buf;
wire oserdes_dqsts_buf;
wire [9:0] data_in;
wire tbyte_out;
assign mem_dq_out = oserdes_dq_buf;
assign mem_dq_ts = oserdes_dqts_buf;
assign data_in = mem_dq_in;
assign mem_dqs_out = oserdes_dqs_buf;
assign mem_dqs_ts = oserdes_dqsts_buf;
assign dqs_to_phaser = mem_dqs_in;
reg iserdes_clk_d;
always @(*)
iserdes_clk_d <= #(025) iserdes_clk;
genvar i;
generate
for ( i = 0; i != 10; i=i+1) begin : input_
if ( BITLANES[i] && !BITLANES_OUTONLY[i]) begin : iserdes_dq_
ISERDESE2 #(
.DATA_RATE ( ISERDES_DQ_DATA_RATE),
.DATA_WIDTH ( ISERDES_DQ_DATA_WIDTH),
.DYN_CLKDIV_INV_EN ( ISERDES_DQ_DYN_CLKDIV_INV_EN),
.DYN_CLK_INV_EN ( ISERDES_DQ_DYN_CLK_INV_EN),
.INIT_Q1 ( ISERDES_DQ_INIT_Q1),
.INIT_Q2 ( ISERDES_DQ_INIT_Q2),
.INIT_Q3 ( ISERDES_DQ_INIT_Q3),
.INIT_Q4 ( ISERDES_DQ_INIT_Q4),
.INTERFACE_TYPE ( ISERDES_DQ_INTERFACE_TYPE),
.NUM_CE ( ISERDES_NUM_CE),
.IOBDELAY ( ISERDES_DQ_IOBDELAY),
.OFB_USED ( ISERDES_DQ_OFB_USED),
.SERDES_MODE ( ISERDES_DQ_SERDES_MODE),
.SRVAL_Q1 ( ISERDES_DQ_SRVAL_Q1),
.SRVAL_Q2 ( ISERDES_DQ_SRVAL_Q2),
.SRVAL_Q3 ( ISERDES_DQ_SRVAL_Q3),
.SRVAL_Q4 ( ISERDES_DQ_SRVAL_Q4)
)
iserdesdq
(
.O (),
.Q1 (iserdes_dout[4*i + 3]),
.Q2 (iserdes_dout[4*i + 2]),
.Q3 (iserdes_dout[4*i + 1]),
.Q4 (iserdes_dout[4*i + 0]),
.Q5 (),
.Q6 (),
.Q7 (),
.Q8 (),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (iserdes_clk_d),
.CLKB (!iserdes_clk_d),
.CLKDIVP (iserdes_clkdiv),
.CLKDIV (),
.DDLY (data_in_dly[i]),
.D (),
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
// NOTE: OCLK is not used in this design, but is required to meet
// a design rule check in map and bitgen. Do not disconnect it.
.OCLK (oserdes_clk),
.OCLKB (),
.OFB (),
.RST (iserdes_rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0)
);
localparam IDELAYE2_CINVCTRL_SEL = "FALSE";
localparam IDELAYE2_DELAY_SRC = "IDATAIN";
localparam IDELAYE2_HIGH_PERFORMANCE_MODE = "TRUE";
localparam IDELAYE2_PIPE_SEL = "FALSE";
localparam IDELAYE2_ODELAY_TYPE = "FIXED";
localparam IDELAYE2_REFCLK_FREQUENCY = 200.0;
localparam IDELAYE2_SIGNAL_PATTERN = "DATA";
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYE2 #(
.CINVCTRL_SEL ( IDELAYE2_CINVCTRL_SEL),
.DELAY_SRC ( IDELAYE2_DELAY_SRC),
.HIGH_PERFORMANCE_MODE ( IDELAYE2_HIGH_PERFORMANCE_MODE),
.IDELAY_TYPE ( IDELAYE2_IDELAY_TYPE),
.IDELAY_VALUE ( IDELAYE2_IDELAY_VALUE),
.PIPE_SEL ( IDELAYE2_PIPE_SEL),
.REFCLK_FREQUENCY ( IDELAYE2_REFCLK_FREQUENCY ),
.SIGNAL_PATTERN ( IDELAYE2_SIGNAL_PATTERN)
)
idelaye2
(
.CNTVALUEOUT (),
.DATAOUT (data_in_dly[i]),
.C (phy_clk), // automatically wired by ISE
.CE (idelay_ce),
.CINVCTRL (),
.CNTVALUEIN (),
.DATAIN (1'b0),
.IDATAIN (data_in[i]),
.INC (idelay_inc),
.LD (idelay_ld),
.LDPIPEEN (1'b0),
.REGRST (rst)
);
end // iserdes_dq
else begin
assign iserdes_dout[4*i + 3] = 0;
assign iserdes_dout[4*i + 2] = 0;
assign iserdes_dout[4*i + 1] = 0;
assign iserdes_dout[4*i + 0] = 0;
end
end // input_
endgenerate // iserdes_dq_
localparam OSERDES_DQ_DATA_RATE_OQ = OSERDES_DATA_RATE;
localparam OSERDES_DQ_DATA_RATE_TQ = OSERDES_DQ_DATA_RATE_OQ;
localparam OSERDES_DQ_DATA_WIDTH = OSERDES_DATA_WIDTH;
localparam OSERDES_DQ_INIT_OQ = 1'b1;
localparam OSERDES_DQ_INIT_TQ = 1'b1;
localparam OSERDES_DQ_INTERFACE_TYPE = "DEFAULT";
localparam OSERDES_DQ_ODELAY_USED = 0;
localparam OSERDES_DQ_SERDES_MODE = "MASTER";
localparam OSERDES_DQ_SRVAL_OQ = 1'b1;
localparam OSERDES_DQ_SRVAL_TQ = 1'b1;
// note: obuf used in control path case, no ts input so width irrelevant
localparam OSERDES_DQ_TRISTATE_WIDTH = (OSERDES_DQ_DATA_RATE_OQ == "DDR") ? 4 : 1;
localparam OSERDES_DQS_DATA_RATE_OQ = "DDR";
localparam OSERDES_DQS_DATA_RATE_TQ = "DDR";
localparam OSERDES_DQS_TRISTATE_WIDTH = 4; // this is always ddr
localparam OSERDES_DQS_DATA_WIDTH = 4;
localparam ODDR_CLK_EDGE = "SAME_EDGE";
localparam OSERDES_TBYTE_CTL = "TRUE";
generate
localparam NUM_BITLANES = PO_DATA_CTL == "TRUE" ? 10 : BUS_WIDTH;
if ( PO_DATA_CTL == "TRUE" ) begin : slave_ts
OSERDESE2 #(
.DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),
.DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),
.DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),
.INIT_OQ (OSERDES_DQ_INIT_OQ),
.INIT_TQ (OSERDES_DQ_INIT_TQ),
.SERDES_MODE (OSERDES_DQ_SERDES_MODE),
.SRVAL_OQ (OSERDES_DQ_SRVAL_OQ),
.SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),
.TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH),
.TBYTE_CTL ("TRUE"),
.TBYTE_SRC ("TRUE")
)
oserdes_slave_ts
(
.OFB (),
.OQ (),
.SHIFTOUT1 (), // not extended
.SHIFTOUT2 (), // not extended
.TFB (),
.TQ (),
.CLK (oserdes_clk),
.CLKDIV (oserdes_clkdiv),
.D1 (),
.D2 (),
.D3 (),
.D4 (),
.D5 (),
.D6 (),
.D7 (),
.D8 (),
.OCE (1'b1),
.RST (oserdes_rst),
.SHIFTIN1 (), // not extended
.SHIFTIN2 (), // not extended
.T1 (oserdes_dqts[0]),
.T2 (oserdes_dqts[0]),
.T3 (oserdes_dqts[1]),
.T4 (oserdes_dqts[1]),
.TCE (1'b1),
.TBYTEOUT (tbyte_out),
.TBYTEIN (tbyte_out)
);
end // slave_ts
for (i = 0; i != NUM_BITLANES; i=i+1) begin : output_
if ( BITLANES[i]) begin : oserdes_dq_
if ( PO_DATA_CTL == "TRUE" ) begin : ddr
OSERDESE2 #(
.DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),
.DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),
.DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),
.INIT_OQ (OSERDES_DQ_INIT_OQ),
.INIT_TQ (OSERDES_DQ_INIT_TQ),
.SERDES_MODE (OSERDES_DQ_SERDES_MODE),
.SRVAL_OQ (OSERDES_DQ_SRVAL_OQ),
.SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),
.TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH),
.TBYTE_CTL (OSERDES_TBYTE_CTL),
.TBYTE_SRC ("FALSE")
)
oserdes_dq_i
(
.OFB (),
.OQ (oserdes_dq_buf[i]),
.SHIFTOUT1 (), // not extended
.SHIFTOUT2 (), // not extended
.TFB (),
.TQ (oserdes_dqts_buf[i]),
.CLK (oserdes_clk),
.CLKDIV (oserdes_clkdiv),
.D1 (oserdes_dq[4 * i + 0]),
.D2 (oserdes_dq[4 * i + 1]),
.D3 (oserdes_dq[4 * i + 2]),
.D4 (oserdes_dq[4 * i + 3]),
.D5 (),
.D6 (),
.D7 (),
.D8 (),
.OCE (1'b1),
.RST (oserdes_rst),
.SHIFTIN1 (), // not extended
.SHIFTIN2 (), // not extended
.T1 (/*oserdes_dqts[0]*/),
.T2 (/*oserdes_dqts[0]*/),
.T3 (/*oserdes_dqts[1]*/),
.T4 (/*oserdes_dqts[1]*/),
.TCE (1'b1),
.TBYTEOUT (),
.TBYTEIN (tbyte_out)
);
end
else begin : sdr
OSERDESE2 #(
.DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),
.DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),
.DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),
.INIT_OQ (OSERDES_DQ_INIT_OQ),
.INIT_TQ (OSERDES_DQ_INIT_TQ),
.SERDES_MODE (OSERDES_DQ_SERDES_MODE),
.SRVAL_OQ (OSERDES_DQ_SRVAL_OQ),
.SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),
.TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH)
)
oserdes_dq_i
(
.OFB (),
.OQ (oserdes_dq_buf[i]),
.SHIFTOUT1 (), // not extended
.SHIFTOUT2 (), // not extended
.TFB (),
.TQ (),
.CLK (oserdes_clk),
.CLKDIV (oserdes_clkdiv),
.D1 (oserdes_dq[4 * i + 0]),
.D2 (oserdes_dq[4 * i + 1]),
.D3 (oserdes_dq[4 * i + 2]),
.D4 (oserdes_dq[4 * i + 3]),
.D5 (),
.D6 (),
.D7 (),
.D8 (),
.OCE (1'b1),
.RST (oserdes_rst),
.SHIFTIN1 (), // not extended
.SHIFTIN2 (), // not extended
.T1 (),
.T2 (),
.T3 (),
.T4 (),
.TCE (1'b1),
.TBYTEOUT (),
.TBYTEIN ()
);
end // ddr
end // oserdes_dq_
end // output_
endgenerate
generate
if ( PO_DATA_CTL == "TRUE" ) begin : dqs_gen
ODDR
#(.DDR_CLK_EDGE (ODDR_CLK_EDGE))
oddr_dqs
(
.Q (oserdes_dqs_buf),
.D1 (oserdes_dqs[0]),
.D2 (oserdes_dqs[1]),
.C (oserdes_clk_delayed),
.R (oserdes_rst),
.S (),
.CE (1'b1)
);
ODDR
#(.DDR_CLK_EDGE (ODDR_CLK_EDGE))
oddr_dqsts
( .Q (oserdes_dqsts_buf),
.D1 (oserdes_dqsts[0]),
.D2 (oserdes_dqsts[0]),
.C (oserdes_clk_delayed),
.R (),
.S (oserdes_rst),
.CE (1'b1)
);
end // sdr rate
else begin:null_dqs
end
endgenerate
endmodule // byte_group_io
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTN_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DLXTN_PP_SYMBOL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlxtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTN_PP_SYMBOL_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:hls:get:1.0
// IP Revision: 1602022135
(* X_CORE_INFO = "get,Vivado 2015.4" *)
(* CHECK_LICENSE_TYPE = "zc702_get_0_0,get,{}" *)
(* CORE_GENERATION_INFO = "zc702_get_0_0,get,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=hls,x_ipName=get,x_ipVersion=1.0,x_ipCoreRevision=1602022135,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_M_AXI_GMEM_ID_WIDTH=1,C_M_AXI_GMEM_ADDR_WIDTH=32,C_M_AXI_GMEM_DATA_WIDTH=32,C_M_AXI_GMEM_AWUSER_WIDTH=1,C_M_AXI_GMEM_ARUSER_WIDTH=1,C_M_AXI_GMEM_WUSER_WIDTH=1,C_M_AXI_GMEM_RUSER_WIDTH=1,C_M_AXI_GMEM_BUSER_WIDTH=1,C_M_AXI_GMEM_USER_VALUE=0x00000000,C_M_AXI_GMEM_PROT_VALUE=000,C_M_AXI_GMEM_CACHE_VALUE=0011}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_get_0_0 (
val_r_ap_vld,
ap_clk,
ap_rst_n,
ap_start,
ap_done,
ap_idle,
ap_ready,
ap_return,
m_axi_gmem_AWADDR,
m_axi_gmem_AWLEN,
m_axi_gmem_AWSIZE,
m_axi_gmem_AWBURST,
m_axi_gmem_AWLOCK,
m_axi_gmem_AWREGION,
m_axi_gmem_AWCACHE,
m_axi_gmem_AWPROT,
m_axi_gmem_AWQOS,
m_axi_gmem_AWVALID,
m_axi_gmem_AWREADY,
m_axi_gmem_WDATA,
m_axi_gmem_WSTRB,
m_axi_gmem_WLAST,
m_axi_gmem_WVALID,
m_axi_gmem_WREADY,
m_axi_gmem_BRESP,
m_axi_gmem_BVALID,
m_axi_gmem_BREADY,
m_axi_gmem_ARADDR,
m_axi_gmem_ARLEN,
m_axi_gmem_ARSIZE,
m_axi_gmem_ARBURST,
m_axi_gmem_ARLOCK,
m_axi_gmem_ARREGION,
m_axi_gmem_ARCACHE,
m_axi_gmem_ARPROT,
m_axi_gmem_ARQOS,
m_axi_gmem_ARVALID,
m_axi_gmem_ARREADY,
m_axi_gmem_RDATA,
m_axi_gmem_RRESP,
m_axi_gmem_RLAST,
m_axi_gmem_RVALID,
m_axi_gmem_RREADY,
data,
key,
val_r
);
output wire val_r_ap_vld;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
input wire ap_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ap_rst_n RST" *)
input wire ap_rst_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:acc_handshake:1.0 ap_ctrl start" *)
input wire ap_start;
(* X_INTERFACE_INFO = "xilinx.com:interface:acc_handshake:1.0 ap_ctrl done" *)
output wire ap_done;
(* X_INTERFACE_INFO = "xilinx.com:interface:acc_handshake:1.0 ap_ctrl idle" *)
output wire ap_idle;
(* X_INTERFACE_INFO = "xilinx.com:interface:acc_handshake:1.0 ap_ctrl ready" *)
output wire ap_ready;
(* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 ap_return DATA" *)
output wire [31 : 0] ap_return;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWADDR" *)
output wire [31 : 0] m_axi_gmem_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWLEN" *)
output wire [7 : 0] m_axi_gmem_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWSIZE" *)
output wire [2 : 0] m_axi_gmem_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWBURST" *)
output wire [1 : 0] m_axi_gmem_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWLOCK" *)
output wire [1 : 0] m_axi_gmem_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWREGION" *)
output wire [3 : 0] m_axi_gmem_AWREGION;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWCACHE" *)
output wire [3 : 0] m_axi_gmem_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWPROT" *)
output wire [2 : 0] m_axi_gmem_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWQOS" *)
output wire [3 : 0] m_axi_gmem_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWVALID" *)
output wire m_axi_gmem_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem AWREADY" *)
input wire m_axi_gmem_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem WDATA" *)
output wire [31 : 0] m_axi_gmem_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem WSTRB" *)
output wire [3 : 0] m_axi_gmem_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem WLAST" *)
output wire m_axi_gmem_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem WVALID" *)
output wire m_axi_gmem_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem WREADY" *)
input wire m_axi_gmem_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem BRESP" *)
input wire [1 : 0] m_axi_gmem_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem BVALID" *)
input wire m_axi_gmem_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem BREADY" *)
output wire m_axi_gmem_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARADDR" *)
output wire [31 : 0] m_axi_gmem_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARLEN" *)
output wire [7 : 0] m_axi_gmem_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARSIZE" *)
output wire [2 : 0] m_axi_gmem_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARBURST" *)
output wire [1 : 0] m_axi_gmem_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARLOCK" *)
output wire [1 : 0] m_axi_gmem_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARREGION" *)
output wire [3 : 0] m_axi_gmem_ARREGION;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARCACHE" *)
output wire [3 : 0] m_axi_gmem_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARPROT" *)
output wire [2 : 0] m_axi_gmem_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARQOS" *)
output wire [3 : 0] m_axi_gmem_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARVALID" *)
output wire m_axi_gmem_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem ARREADY" *)
input wire m_axi_gmem_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem RDATA" *)
input wire [31 : 0] m_axi_gmem_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem RRESP" *)
input wire [1 : 0] m_axi_gmem_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem RLAST" *)
input wire m_axi_gmem_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem RVALID" *)
input wire m_axi_gmem_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi_gmem RREADY" *)
output wire m_axi_gmem_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 data DATA" *)
input wire [31 : 0] data;
(* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 key DATA" *)
input wire [31 : 0] key;
(* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 val_r DATA" *)
output wire [31 : 0] val_r;
get #(
.C_M_AXI_GMEM_ID_WIDTH(1),
.C_M_AXI_GMEM_ADDR_WIDTH(32),
.C_M_AXI_GMEM_DATA_WIDTH(32),
.C_M_AXI_GMEM_AWUSER_WIDTH(1),
.C_M_AXI_GMEM_ARUSER_WIDTH(1),
.C_M_AXI_GMEM_WUSER_WIDTH(1),
.C_M_AXI_GMEM_RUSER_WIDTH(1),
.C_M_AXI_GMEM_BUSER_WIDTH(1),
.C_M_AXI_GMEM_USER_VALUE('H00000000),
.C_M_AXI_GMEM_PROT_VALUE('B000),
.C_M_AXI_GMEM_CACHE_VALUE('B0011)
) inst (
.val_r_ap_vld(val_r_ap_vld),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.ap_start(ap_start),
.ap_done(ap_done),
.ap_idle(ap_idle),
.ap_ready(ap_ready),
.ap_return(ap_return),
.m_axi_gmem_AWID(),
.m_axi_gmem_AWADDR(m_axi_gmem_AWADDR),
.m_axi_gmem_AWLEN(m_axi_gmem_AWLEN),
.m_axi_gmem_AWSIZE(m_axi_gmem_AWSIZE),
.m_axi_gmem_AWBURST(m_axi_gmem_AWBURST),
.m_axi_gmem_AWLOCK(m_axi_gmem_AWLOCK),
.m_axi_gmem_AWREGION(m_axi_gmem_AWREGION),
.m_axi_gmem_AWCACHE(m_axi_gmem_AWCACHE),
.m_axi_gmem_AWPROT(m_axi_gmem_AWPROT),
.m_axi_gmem_AWQOS(m_axi_gmem_AWQOS),
.m_axi_gmem_AWUSER(),
.m_axi_gmem_AWVALID(m_axi_gmem_AWVALID),
.m_axi_gmem_AWREADY(m_axi_gmem_AWREADY),
.m_axi_gmem_WID(),
.m_axi_gmem_WDATA(m_axi_gmem_WDATA),
.m_axi_gmem_WSTRB(m_axi_gmem_WSTRB),
.m_axi_gmem_WLAST(m_axi_gmem_WLAST),
.m_axi_gmem_WUSER(),
.m_axi_gmem_WVALID(m_axi_gmem_WVALID),
.m_axi_gmem_WREADY(m_axi_gmem_WREADY),
.m_axi_gmem_BID(1'B0),
.m_axi_gmem_BRESP(m_axi_gmem_BRESP),
.m_axi_gmem_BUSER(1'B0),
.m_axi_gmem_BVALID(m_axi_gmem_BVALID),
.m_axi_gmem_BREADY(m_axi_gmem_BREADY),
.m_axi_gmem_ARID(),
.m_axi_gmem_ARADDR(m_axi_gmem_ARADDR),
.m_axi_gmem_ARLEN(m_axi_gmem_ARLEN),
.m_axi_gmem_ARSIZE(m_axi_gmem_ARSIZE),
.m_axi_gmem_ARBURST(m_axi_gmem_ARBURST),
.m_axi_gmem_ARLOCK(m_axi_gmem_ARLOCK),
.m_axi_gmem_ARREGION(m_axi_gmem_ARREGION),
.m_axi_gmem_ARCACHE(m_axi_gmem_ARCACHE),
.m_axi_gmem_ARPROT(m_axi_gmem_ARPROT),
.m_axi_gmem_ARQOS(m_axi_gmem_ARQOS),
.m_axi_gmem_ARUSER(),
.m_axi_gmem_ARVALID(m_axi_gmem_ARVALID),
.m_axi_gmem_ARREADY(m_axi_gmem_ARREADY),
.m_axi_gmem_RID(1'B0),
.m_axi_gmem_RDATA(m_axi_gmem_RDATA),
.m_axi_gmem_RRESP(m_axi_gmem_RRESP),
.m_axi_gmem_RLAST(m_axi_gmem_RLAST),
.m_axi_gmem_RUSER(1'B0),
.m_axi_gmem_RVALID(m_axi_gmem_RVALID),
.m_axi_gmem_RREADY(m_axi_gmem_RREADY),
.data(data),
.key(key),
.val_r(val_r)
);
endmodule
|
module memory(
gm_or_lds,
rd_en,
wr_en,
addresses,
wr_data,
input_tag,
// wr_mask,
rd_data,
output_tag,
ack,
clk,
rst
);
input clk;
input rst;
input gm_or_lds;
input rd_en, wr_en;
input [31:0] addresses;
input [31:0] wr_data;
input [6:0] input_tag;
output [6:0] output_tag;
output ack;
output [31:0] rd_data;
reg[7:0] data_memory[50000:0];
reg[7:0] lds_memory[65535:0];
reg ack_reg;
reg [6:0] tag_reg;
//integer locrd = 4; // num of loc to read
assign ack = ack_reg;
assign output_tag = tag_reg;
integer i;
always@(posedge clk, posedge rst) begin
// if(rst) begin
// for(i = 0; i < 50001; i = i+1) begin
// data_memory[i] <= 0;
// end
// for(i = 0; i < 65536; i = i+1) begin
// lds_memory[i] <= 0;
// end
// end
// else
if(wr_en) begin
if(gm_or_lds) begin
lds_memory [addresses] <= wr_data[7:0];
lds_memory [addresses+1] <= wr_data[15:7];
lds_memory [addresses+2] <= wr_data[23:16];
lds_memory [addresses+3] <= wr_data[31:24];
end
else begin
data_memory [addresses] <= wr_data[7:0];
data_memory [addresses+1] <= wr_data[15:7];
data_memory [addresses+2] <= wr_data[23:16];
data_memory [addresses+3] <= wr_data[31:24];
end
end
end
always@(posedge clk) begin
if(rst) begin
ack_reg <= 1'b0;
tag_reg <= 7'd0;
end
else begin
ack_reg <= 1'b0;
tag_reg <= 7'd0;
if(rd_en | wr_en) begin
ack_reg <= 1'b1;
tag_reg <= input_tag;
end
end
end
wire [31:0] rd_lds;
wire [31:0] rd_dm;
assign rd_lds = {lds_memory[addresses+3],lds_memory[addresses+2],lds_memory[addresses+1],lds_memory[addresses]};
assign rd_dm = {data_memory[addresses+3],data_memory[addresses+2],data_memory[addresses+1],data_memory[addresses]};
assign rd_data = (gm_or_lds) ? rd_lds:rd_dm;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:07:35 10/15/2016
// Design Name: main
// Module Name: /home/luno/git/BEL/M-1_HW/ise/trc_v002/src/sim_main.v
// Project Name: trc_v002
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: main
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sim_main;
`include "parameters_global.v"
// Inputs
reg SPARE;
reg RESET_2;
reg TRC_RESET;
reg TCK_1;
reg TCK_2;
reg TMS_1;
reg TMS_2;
reg TDO_1;
reg TDO_2;
reg TRST_1;
reg TRST_2;
reg SCL;
reg OSC_RC;
reg TDI1_COMP;
reg TDI2_COMP;
// Outputs
wire TDI_1;
wire TDI_2;
wire OSC_OUT;
wire I2C_EN;
wire I2C_SEL_0;
wire I2C_SEL_1;
wire I2C_SEL_2;
wire DBG;
wire GND1_REL;
wire GND2_REL;
wire TAP1_REL;
wire TAP2_REL;
wire DIO1_REL;
wire DIO2_REL;
wire AIO1_REL;
wire AIO2_REL;
wire TRM_DIO1_REL;
wire TRM_DIO2_REL;
wire TRM_TDI_REL;
wire TRST1_DRV;
wire TRST2_DRV;
wire TCK1_DRV;
wire TCK2_DRV;
wire TMS1_DRV;
wire TMS2_DRV;
wire TDO1_DRV;
wire TDO2_DRV;
wire ADJ_VCCIO_1_1V5;
wire ADJ_VCCIO_1_1V8;
wire ADJ_VCCIO_1_2V5;
wire ADJ_VCCIO_2_1V5;
wire ADJ_VCCIO_2_1V8;
wire ADJ_VCCIO_2_2V5;
// Bidirs
wire [3:0] GPIO;
wire SDA;
wire DIO11_DRV;
wire DIO12_DRV;
wire DIO21_DRV;
wire DIO22_DRV;
// Instantiate the Unit Under Test (UUT)
main uut (
.SPARE(SPARE),
.RESET_2(RESET_2),
.TRC_RESET(TRC_RESET),
.TCK_1(TCK_1),
.TCK_2(TCK_2),
.TMS_1(TMS_1),
.TMS_2(TMS_2),
.TDO_1(TDO_1),
.TDO_2(TDO_2),
.TRST_1(TRST_1),
.TRST_2(TRST_2),
.TDI_1(TDI_1),
.TDI_2(TDI_2),
.GPIO(GPIO),
.SDA(SDA),
.SCL(SCL),
.OSC_RC(OSC_RC),
.OSC_OUT(OSC_OUT),
.I2C_EN(I2C_EN),
.I2C_SEL_0(I2C_SEL_0),
.I2C_SEL_1(I2C_SEL_1),
.I2C_SEL_2(I2C_SEL_2),
.DBG(DBG),
.GND1_REL(GND1_REL),
.GND2_REL(GND2_REL),
.TAP1_REL(TAP1_REL),
.TAP2_REL(TAP2_REL),
.DIO1_REL(DIO1_REL),
.DIO2_REL(DIO2_REL),
.AIO1_REL(AIO1_REL),
.AIO2_REL(AIO2_REL),
.TRM_DIO1_REL(TRM_DIO1_REL),
.TRM_DIO2_REL(TRM_DIO2_REL),
.TRM_TDI_REL(TRM_TDI_REL),
.TDI1_COMP(TDI1_COMP),
.TDI2_COMP(TDI2_COMP),
.TRST1_DRV(TRST1_DRV),
.TRST2_DRV(TRST2_DRV),
.TCK1_DRV(TCK1_DRV),
.TCK2_DRV(TCK2_DRV),
.TMS1_DRV(TMS1_DRV),
.TMS2_DRV(TMS2_DRV),
.TDO1_DRV(TDO1_DRV),
.TDO2_DRV(TDO2_DRV),
.DIO11_DRV(DIO11_DRV),
.DIO12_DRV(DIO12_DRV),
.DIO21_DRV(DIO21_DRV),
.DIO22_DRV(DIO22_DRV),
.ADJ_VCCIO_1_1V5(ADJ_VCCIO_1_1V5),
.ADJ_VCCIO_1_1V8(ADJ_VCCIO_1_1V8),
.ADJ_VCCIO_1_2V5(ADJ_VCCIO_1_2V5),
.ADJ_VCCIO_2_1V5(ADJ_VCCIO_2_1V5),
.ADJ_VCCIO_2_1V8(ADJ_VCCIO_2_1V8),
.ADJ_VCCIO_2_2V5(ADJ_VCCIO_2_2V5)
);
initial begin
// Initialize Inputs
SPARE = 0;
RESET_2 = 0;
TRC_RESET = 1;
TCK_1 = 0;
TCK_2 = 0;
TMS_1 = 0;
TMS_2 = 0;
TDO_1 = 0;
TDO_2 = 0;
TRST_1 = 0;
TRST_2 = 0;
SCL = 0;
OSC_RC = 1;
TDI1_COMP = 0;
TDI2_COMP = 0;
// Wait 100 ns for global reset to finish
#100;
TRC_RESET = 0;
#100;
TRC_RESET = 1;
// Add stimulus here
end
always #10 OSC_RC = ~OSC_RC; // main clock // period
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MAJ3_4_V
`define SKY130_FD_SC_HS__MAJ3_4_V
/**
* maj3: 3-input majority vote.
*
* Verilog wrapper for maj3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__maj3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__maj3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__maj3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__MAJ3_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCIN_BLACKBOX_V
`define SKY130_FD_SC_HS__FAHCIN_BLACKBOX_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fahcin (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCIN_BLACKBOX_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module pixelq_op_OUTPUT_STREAM_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [23:0] TDATA,
output wire [2:0] TKEEP,
output wire [2:0] TSTRB,
output wire [0:0] TUSER,
output wire [0:0] TLAST,
output wire [0:0] TID,
output wire [0:0] TDEST,
// User signals
input wire [23:0] dst_axi_V_data_V_din,
output wire dst_axi_V_data_V_full_n,
input wire dst_axi_V_data_V_write,
input wire [2:0] dst_axi_V_keep_V_din,
output wire dst_axi_V_keep_V_full_n,
input wire dst_axi_V_keep_V_write,
input wire [2:0] dst_axi_V_strb_V_din,
output wire dst_axi_V_strb_V_full_n,
input wire dst_axi_V_strb_V_write,
input wire [0:0] dst_axi_V_user_V_din,
output wire dst_axi_V_user_V_full_n,
input wire dst_axi_V_user_V_write,
input wire [0:0] dst_axi_V_last_V_din,
output wire dst_axi_V_last_V_full_n,
input wire dst_axi_V_last_V_write,
input wire [0:0] dst_axi_V_id_V_din,
output wire dst_axi_V_id_V_full_n,
input wire dst_axi_V_id_V_write,
input wire [0:0] dst_axi_V_dest_V_din,
output wire dst_axi_V_dest_V_full_n,
input wire dst_axi_V_dest_V_write
);
//------------------------Local signal-------------------
// FIFO
wire [0:0] fifo_read;
wire [0:0] fifo_empty_n;
wire [23:0] dst_axi_V_data_V_dout;
wire [0:0] dst_axi_V_data_V_empty_n;
wire [2:0] dst_axi_V_keep_V_dout;
wire [0:0] dst_axi_V_keep_V_empty_n;
wire [2:0] dst_axi_V_strb_V_dout;
wire [0:0] dst_axi_V_strb_V_empty_n;
wire [0:0] dst_axi_V_user_V_dout;
wire [0:0] dst_axi_V_user_V_empty_n;
wire [0:0] dst_axi_V_last_V_dout;
wire [0:0] dst_axi_V_last_V_empty_n;
wire [0:0] dst_axi_V_id_V_dout;
wire [0:0] dst_axi_V_id_V_empty_n;
wire [0:0] dst_axi_V_dest_V_dout;
wire [0:0] dst_axi_V_dest_V_empty_n;
// register slice
wire [0:0] s_valid;
wire [0:0] s_ready;
wire [33:0] s_data;
wire [0:0] m_valid;
wire [0:0] m_ready;
wire [33:0] m_data;
//------------------------Instantiation------------------
// rs
pixelq_op_OUTPUT_STREAM_reg_slice #(
.N ( 34 )
) rs (
.clk ( ACLK ),
.reset ( ARESETN ),
.s_data ( s_data ),
.s_valid ( s_valid ),
.s_ready ( s_ready ),
.m_data ( m_data ),
.m_valid ( m_valid ),
.m_ready ( m_ready )
);
// dst_axi_V_data_V_fifo
pixelq_op_OUTPUT_STREAM_fifo #(
.DATA_BITS ( 24 ),
.DEPTH_BITS ( 4 )
) dst_axi_V_data_V_fifo (
.clk ( ACLK ),
.aclr ( ~ARESETN ),
.empty_n ( dst_axi_V_data_V_empty_n ),
.full_n ( dst_axi_V_data_V_full_n ),
.read ( fifo_read ),
.write ( dst_axi_V_data_V_write ),
.dout ( dst_axi_V_data_V_dout ),
.din ( dst_axi_V_data_V_din )
);
// dst_axi_V_keep_V_fifo
pixelq_op_OUTPUT_STREAM_fifo #(
.DATA_BITS ( 3 ),
.DEPTH_BITS ( 4 )
) dst_axi_V_keep_V_fifo (
.clk ( ACLK ),
.aclr ( ~ARESETN ),
.empty_n ( dst_axi_V_keep_V_empty_n ),
.full_n ( dst_axi_V_keep_V_full_n ),
.read ( fifo_read ),
.write ( dst_axi_V_keep_V_write ),
.dout ( dst_axi_V_keep_V_dout ),
.din ( dst_axi_V_keep_V_din )
);
// dst_axi_V_strb_V_fifo
pixelq_op_OUTPUT_STREAM_fifo #(
.DATA_BITS ( 3 ),
.DEPTH_BITS ( 4 )
) dst_axi_V_strb_V_fifo (
.clk ( ACLK ),
.aclr ( ~ARESETN ),
.empty_n ( dst_axi_V_strb_V_empty_n ),
.full_n ( dst_axi_V_strb_V_full_n ),
.read ( fifo_read ),
.write ( dst_axi_V_strb_V_write ),
.dout ( dst_axi_V_strb_V_dout ),
.din ( dst_axi_V_strb_V_din )
);
// dst_axi_V_user_V_fifo
pixelq_op_OUTPUT_STREAM_fifo #(
.DATA_BITS ( 1 ),
.DEPTH_BITS ( 4 )
) dst_axi_V_user_V_fifo (
.clk ( ACLK ),
.aclr ( ~ARESETN ),
.empty_n ( dst_axi_V_user_V_empty_n ),
.full_n ( dst_axi_V_user_V_full_n ),
.read ( fifo_read ),
.write ( dst_axi_V_user_V_write ),
.dout ( dst_axi_V_user_V_dout ),
.din ( dst_axi_V_user_V_din )
);
// dst_axi_V_last_V_fifo
pixelq_op_OUTPUT_STREAM_fifo #(
.DATA_BITS ( 1 ),
.DEPTH_BITS ( 4 )
) dst_axi_V_last_V_fifo (
.clk ( ACLK ),
.aclr ( ~ARESETN ),
.empty_n ( dst_axi_V_last_V_empty_n ),
.full_n ( dst_axi_V_last_V_full_n ),
.read ( fifo_read ),
.write ( dst_axi_V_last_V_write ),
.dout ( dst_axi_V_last_V_dout ),
.din ( dst_axi_V_last_V_din )
);
// dst_axi_V_id_V_fifo
pixelq_op_OUTPUT_STREAM_fifo #(
.DATA_BITS ( 1 ),
.DEPTH_BITS ( 4 )
) dst_axi_V_id_V_fifo (
.clk ( ACLK ),
.aclr ( ~ARESETN ),
.empty_n ( dst_axi_V_id_V_empty_n ),
.full_n ( dst_axi_V_id_V_full_n ),
.read ( fifo_read ),
.write ( dst_axi_V_id_V_write ),
.dout ( dst_axi_V_id_V_dout ),
.din ( dst_axi_V_id_V_din )
);
// dst_axi_V_dest_V_fifo
pixelq_op_OUTPUT_STREAM_fifo #(
.DATA_BITS ( 1 ),
.DEPTH_BITS ( 4 )
) dst_axi_V_dest_V_fifo (
.clk ( ACLK ),
.aclr ( ~ARESETN ),
.empty_n ( dst_axi_V_dest_V_empty_n ),
.full_n ( dst_axi_V_dest_V_full_n ),
.read ( fifo_read ),
.write ( dst_axi_V_dest_V_write ),
.dout ( dst_axi_V_dest_V_dout ),
.din ( dst_axi_V_dest_V_din )
);
//------------------------Body---------------------------
//++++++++++++++++++++++++AXI4-Stream++++++++++++++++++++
assign TVALID = m_valid;
assign TDATA = m_data[23:0];
assign TKEEP = m_data[26:24];
assign TSTRB = m_data[29:27];
assign TUSER = m_data[30:30];
assign TLAST = m_data[31:31];
assign TID = m_data[32:32];
assign TDEST = m_data[33:33];
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++Reigister Slice++++++++++++++++
assign s_valid = fifo_empty_n;
assign m_ready = TREADY;
assign s_data = {dst_axi_V_dest_V_dout, dst_axi_V_id_V_dout, dst_axi_V_last_V_dout, dst_axi_V_user_V_dout, dst_axi_V_strb_V_dout, dst_axi_V_keep_V_dout, dst_axi_V_data_V_dout};
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++FIFO+++++++++++++++++++++++++++
assign fifo_read = fifo_empty_n & s_ready;
assign fifo_empty_n = dst_axi_V_data_V_empty_n & dst_axi_V_keep_V_empty_n & dst_axi_V_strb_V_empty_n & dst_axi_V_user_V_empty_n & dst_axi_V_last_V_empty_n & dst_axi_V_id_V_empty_n & dst_axi_V_dest_V_empty_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
`timescale 1ns/1ps
module pixelq_op_OUTPUT_STREAM_fifo
#(parameter
DATA_BITS = 8,
DEPTH_BITS = 4
)(
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam
DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [DATA_BITS-1:0] mem[0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr)
empty <= 1'b1;
else if (empty & write & ~read)
empty <= 1'b0;
else if (~empty & ~write & read & (index==1'b0))
empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr)
full <= 1'b0;
else if (full & read & ~write)
full <= 1'b0;
else if (~full & ~read & write & (index==DEPTH-2'd2))
full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr)
index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read)
index <= index - 1'b1;
else if (~full & ~read & write)
index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
`timescale 1ns/1ps
module pixelq_op_OUTPUT_STREAM_reg_slice
#(parameter
N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [1:0] state;
reg [1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2)
data_p1 <= data_p2;
else
data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset)
s_ready_t <= 1'b0;
else if (state == ZERO)
s_ready_t <= 1'b1;
else if (state == ONE && next == TWO)
s_ready_t <= 1'b0;
else if (state == TWO && next == ONE)
s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset)
state <= ZERO;
else
state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready)
next = ONE;
else
next = ZERO;
ONE:
if (~s_valid & m_ready)
next = ZERO;
else if (s_valid & ~m_ready)
next = TWO;
else
next = ONE;
TWO:
if (m_ready)
next = ONE;
else
next = TWO;
default:
next = ZERO;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__FILL_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__FILL_BEHAVIORAL_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__FILL_BEHAVIORAL_V |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the program counter
// Import the modules that will be tested for in this testbench
//`include "prog_counter2.v"
`include "program_counter2.syn.v"
`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"
// IMPORTANT: To run this, try: ncverilog -f prog_counter.f +gui
module tb_prog_counter2();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the prog_counter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// next_pc output signal
wire [0:31] n_pc;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// clk, rst
reg clock,reset;
// cur_pc
//reg [0:31] c_pc;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 5ns <==> 200 MHz clock
*/
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of regfile() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
program_counter2 pc2 (
// instance_name(signal name),
// Signal name can be the same as the instance name
// next_pc,cur_pc,rst,clk
n_pc,reset,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
$sdf_annotate("../sdf/program_counter2.sdf",pc2,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
//c_pc=$random;
reset=1'b1;
#20
//c_pc=200;
reset=1'b0;
// Write to 8 data locations
for(count=200; count<216; count=count+1)
begin
#10
//c_pc=count;
//c_pc=n_pc;
reset=1'b0;
end
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__MUX2_BEHAVIORAL_PP_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to10_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_2to10_out_X , A0, A1, S );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2_BEHAVIORAL_PP_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_2048x32.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.10 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.9 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.8 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.4.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.4 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.3 2002/10/28 15:03:50 mohor
// Signal scanb_sen renamed to scanb_en.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_2048x32(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 11;
parameter dw = 32;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hdsp_2048x32 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_2048x32_bist artisan_ssp(
`else
art_hssp_2048x32 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_2048x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x32_bist vs_ssp(
`else
vs_hdsp_2048x32 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[1:0]),
.EN(ce),
.WE(we),
.DO(doq[1:0])
);
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[3:2]),
.EN(ce),
.WE(we),
.DO(doq[3:2])
);
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[5:4]),
.EN(ce),
.WE(we),
.DO(doq[5:4])
);
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:6]),
.EN(ce),
.WE(we),
.DO(doq[7:6])
);
//
// Block 4
//
RAMB4_S2 ramb4_s2_4(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[9:8]),
.EN(ce),
.WE(we),
.DO(doq[9:8])
);
//
// Block 5
//
RAMB4_S2 ramb4_s2_5(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[11:10]),
.EN(ce),
.WE(we),
.DO(doq[11:10])
);
//
// Block 6
//
RAMB4_S2 ramb4_s2_6(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[13:12]),
.EN(ce),
.WE(we),
.DO(doq[13:12])
);
//
// Block 7
//
RAMB4_S2 ramb4_s2_7(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[15:14]),
.EN(ce),
.WE(we),
.DO(doq[15:14])
);
//
// Block 8
//
RAMB4_S2 ramb4_s2_8(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[17:16]),
.EN(ce),
.WE(we),
.DO(doq[17:16])
);
//
// Block 9
//
RAMB4_S2 ramb4_s2_9(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[19:18]),
.EN(ce),
.WE(we),
.DO(doq[19:18])
);
//
// Block 10
//
RAMB4_S2 ramb4_s2_10(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[21:20]),
.EN(ce),
.WE(we),
.DO(doq[21:20])
);
//
// Block 11
//
RAMB4_S2 ramb4_s2_11(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[23:22]),
.EN(ce),
.WE(we),
.DO(doq[23:22])
);
//
// Block 12
//
RAMB4_S2 ramb4_s2_12(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[25:24]),
.EN(ce),
.WE(we),
.DO(doq[25:24])
);
//
// Block 13
//
RAMB4_S2 ramb4_s2_13(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[27:26]),
.EN(ce),
.WE(we),
.DO(doq[27:26])
);
//
// Block 14
//
RAMB4_S2 ramb4_s2_14(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[29:28]),
.EN(ce),
.WE(we),
.DO(doq[29:28])
);
//
// Block 15
//
RAMB4_S2 ramb4_s2_15(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[31:30]),
.EN(ce),
.WE(we),
.DO(doq[31:30])
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
//
// Block 0
//
RAMB16_S9 ramb16_s9_0(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[7:0]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[7:0]),
.DOP()
);
//
// Block 1
//
RAMB16_S9 ramb16_s9_1(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[15:8]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[15:8]),
.DOP()
);
//
// Block 2
//
RAMB16_S9 ramb16_s9_2(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[23:16]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[23:16]),
.DOP()
);
//
// Block 3
//
RAMB16_S9 ramb16_s9_3(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[31:24]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[31:24]),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
//
// Conformal-LEC Version 16.10-d005 ( 21-Apr-2016 ) ( 64 bit executable )
//
module top ( n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 , n80 , n81 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 , n96 , n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 , n106 , n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 , n116 , n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 , n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 , n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 , n146 , n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 , n156 , n157 , n158 , n159 , n160 , n161 , n162 , n163 , n164 , n165 , n166 , n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 , n175 , n176 , n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 , n185 , n186 , n187 , n188 , n189 , n190 , n191 , n192 , n193 , n194 , n195 , n196 , n197 , n198 , n199 , n200 , n201 , n202 , n203 , n204 , n205 , n206 , n207 , n208 , n209 , n210 , n211 , n212 , n213 , n214 , n215 , n216 , n217 , n218 , n219 , n220 , n221 , n222 , n223 , n224 , n225 , n226 , n227 , n228 , n229 , n230 , n231 , n232 , n233 , n234 , n235 , n236 , n237 , n238 , n239 , n240 , n241 , n242 , n243 , n244 , n245 , n246 , n247 , n248 , n249 , n250 , n251 , n252 , n253 , n254 , n255 , n256 , n257 , n258 , n259 , n260 , n261 , n262 , n263 , n264 , n265 , n266 , n267 , n268 , n269 , n270 , n271 , n272 , n273 , n274 , n275 , n276 , n277 , n278 , n279 , n280 , n281 , n282 , n283 , n284 , n285 , n286 , n287 , n288 , n289 , n290 , n291 , n292 , n293 , n294 , n295 , n296 , n297 , n298 , n299 , n300 , n301 , n302 , n303 , n304 , n305 , n306 , n307 , n308 , n309 , n310 , n311 , n312 , n313 , n314 , n315 , n316 , n317 , n318 , n319 , n320 , n321 , n322 , n323 , n324 , n325 , n326 , n327 , n328 , n329 , n330 , n331 , n332 , n333 , n334 , n335 , n336 , n337 , n338 , n339 , n340 , n341 , n342 , n343 , n344 , n345 , n346 , n347 , n348 , n349 , n350 , n351 , n352 , n353 , n354 , n355 , n356 , n357 , n358 , n359 , n360 , n361 , n362 , n363 , n364 , n365 , n366 , n367 , n368 , n369 , n370 , n371 , n372 , n373 , n374 , n375 , n376 , n377 , n378 , n379 , n380 , n381 , n382 , n383 , n384 , n385 , n386 , n387 , n388 , n389 , n390 , n391 , n392 , n393 , n394 , n395 , n396 , n397 , n398 , n399 , n400 , n401 , n402 , n403 , n404 , n405 , n406 , n407 , n408 , n409 , n410 , n411 , n412 , n413 , n414 , n415 , n416 , n417 , n418 , n419 , n420 , n421 , n422 , n423 , n424 , n425 , n426 , n427 , n428 , n429 , n430 , n431 , n432 , n433 , n434 , n435 , n436 , n437 , n438 , n439 , n440 , n441 , n442 , n443 , n444 , n445 , n446 , n447 , n448 , n449 , n450 , n451 , n452 , n453 , n454 , n455 , n456 , n457 , n458 , n459 , n460 , n461 , n462 , n463 , n464 , n465 , n466 , n467 , n468 , n469 , n470 , n471 , n472 , n473 , n474 , n475 , n476 , n477 , n478 , n479 , n480 , n481 , n482 , n483 , n484 , n485 , n486 , n487 , n488 , n489 , n490 , n491 , n492 , n493 , n494 , n495 , n496 , n497 , n498 , n499 , n500 , n501 , n502 , n503 , n504 , n505 , n506 , n507 , n508 , n509 , n510 , n511 , n512 , n513 , n514 , n515 , n516 , n517 , n518 , n519 , n520 , n521 , n522 , n523 , n524 , n525 , n526 , n527 , n528 , n529 , n530 , n531 , n532 , n533 , n534 , n535 , n536 , n537 , n538 , n539 , n540 , n541 , n542 , n543 , n544 , n545 , n546 , n547 , n548 , n549 , n550 , n551 , n552 , n553 , n554 , n555 , n556 , n557 , n558 , n559 , n560 , n561 , n562 , n563 , n564 , n565 , n566 , n567 , n568 , n569 , n570 , n571 , n572 , n573 , n574 , n575 , n576 , n577 , n578 , n579 , n580 , n581 , n582 , n583 , n584 , n585 , n586 , n587 , n588 , n589 , n590 , n591 , n592 , n593 , n594 , n595 , n596 , n597 , n598 , n599 , n600 , n601 , n602 , n603 , n604 , n605 , n606 , n607 , n608 , n609 , n610 , n611 , n612 , n613 , n614 , n615 , n616 , n617 , n618 , n619 , n620 , n621 , n622 , n623 , n624 , n625 , n626 , n627 , n628 , n629 , n630 , n631 , n632 , n633 , n634 , n635 , n636 , n637 , n638 , n639 , n640 , n641 , n642 , n643 , n644 , n645 , n646 , n647 , n648 , n649 , n650 , n651 , n652 , n653 , n654 , n655 , n656 , n657 , n658 , n659 , n660 , n661 , n662 , n663 , n664 , n665 , n666 , n667 , n668 , n669 , n670 , n671 , n672 , n673 , n674 , n675 , n676 , n677 , n678 , n679 , n680 , n681 , n682 , n683 , n684 , n685 , n686 , n687 , n688 , n689 , n690 , n691 , n692 , n693 , n694 , n695 , n696 , n697 , n698 , n699 , n700 , n701 , n702 , n703 , n704 , n705 , n706 , n707 , n708 , n709 , n710 , n711 , n712 , n713 , n714 , n715 , n716 , n717 , n718 , n719 , n720 , n721 , n722 , n723 , n724 , n725 , n726 , n727 , n728 , n729 , n730 , n731 , n732 , n733 , n734 , n735 , n736 , n737 , n738 , n739 , n740 , n741 , n742 , n743 , n744 , n745 , n746 , n747 , n748 , n749 , n750 , n751 , n752 , n753 , n754 , n755 , n756 , n757 , n758 , n759 , n760 , n761 , n762 , n763 , n764 , n765 , n766 , n767 , n768 , n769 , n770 , n771 , n772 , n773 , n774 , n775 , n776 , n777 , n778 , n779 , n780 , n781 , n782 , n783 , n784 , n785 , n786 , n787 , n788 , n789 , n790 , n791 , n792 , n793 , n794 , n795 , n796 , n797 , n798 , n799 , n800 , n801 , n802 , n803 , n804 , n805 , n806 , n807 , n808 , n809 , n810 , n811 , n812 , n813 , n814 , n815 , n816 , n817 , n818 , n819 , n820 , n821 , n822 , n823 , n824 , n825 , n826 , n827 , n828 , n829 , n830 , n831 , n832 , n833 , n834 , n835 , n836 , n837 , n838 , n839 , n840 , n841 , n842 , n843 , n844 , n845 , n846 , n847 , n848 , n849 , n850 , n851 , n852 , n853 , n854 , n855 , n856 , n857 , n858 , n859 , n860 , n861 , n862 , n863 , n864 , n865 , n866 , n867 , n868 , n869 , n870 , n871 , n872 , n873 , n874 , n875 , n876 , n877 , n878 , n879 , n880 , n881 , n882 , n883 , n884 , n885 , n886 , n887 , n888 , n889 , n890 , n891 , n892 , n893 , n894 , n895 , n896 , n897 , n898 , n899 , n900 , n901 , n902 , n903 , n904 , n905 , n906 , n907 , n908 , n909 , n910 , n911 , n912 , n913 , n914 , n915 , n916 , n917 , n918 , n919 , n920 , n921 , n922 , n923 , n924 , n925 , n926 , n927 , n928 , n929 , n930 , n931 , n932 , n933 , n934 , n935 , n936 , n937 , n938 , n939 , n940 , n941 , n942 , n943 , n944 , n945 , n946 , n947 , n948 , n949 , n950 , n951 , n952 , n953 , n954 , n955 , n956 , n957 , n958 , n959 , n960 , n961 , n962 , n963 , n964 , n965 , n966 , n967 , n968 , n969 , n970 , n971 , n972 , n973 , n974 , n975 , n976 , n977 , n978 , n979 , n980 , n981 , n982 , n983 , n984 , n985 , n986 , n987 , n988 , n989 , n990 , n991 , n992 , n993 , n994 , n995 , n996 , n997 , n998 , n999 , n1000 , n1001 , n1002 , n1003 , n1004 , n1005 , n1006 , n1007 , n1008 , n1009 , n1010 , n1011 , n1012 , n1013 , n1014 , n1015 , n1016 , n1017 , n1018 , n1019 , n1020 , n1021 , n1022 , n1023 , n1024 , n1025 , n1026 , n1027 , n1028 , n1029 , n1030 , n1031 , n1032 , n1033 , n1034 , n1035 , n1036 , n1037 , n1038 , n1039 , n1040 , n1041 , n1042 , n1043 , n1044 , n1045 , n1046 , n1047 , n1048 , n1049 , n1050 , n1051 , n1052 , n1053 , n1054 , n1055 , n1056 , n1057 , n1058 , n1059 , n1060 , n1061 , n1062 , n1063 , n1064 , n1065 , n1066 , n1067 , n1068 , n1069 , n1070 , n1071 , n1072 , n1073 , n1074 , n1075 , n1076 , n1077 , n1078 , n1079 , n1080 , n1081 , n1082 , n1083 , n1084 , n1085 , n1086 , n1087 , n1088 , n1089 , n1090 , n1091 , n1092 , n1093 , n1094 , n1095 , n1096 , n1097 , n1098 , n1099 , n1100 , n1101 , n1102 , n1103 , n1104 , n1105 , n1106 , n1107 , n1108 , n1109 , n1110 , n1111 , n1112 , n1113 , n1114 , n1115 , n1116 , n1117 , n1118 , n1119 , n1120 , n1121 , n1122 , n1123 , n1124 , n1125 , n1126 , n1127 , n1128 , n1129 , n1130 , n1131 , n1132 , n1133 , n1134 , n1135 , n1136 , n1137 , n1138 , n1139 , n1140 , n1141 , n1142 , n1143 , n1144 , n1145 , n1146 , n1147 , n1148 , n1149 , n1150 , n1151 , n1152 , n1153 , n1154 , n1155 , n1156 , n1157 , n1158 , n1159 , n1160 , n1161 , n1162 , n1163 , n1164 , n1165 , n1166 , n1167 , n1168 , n1169 , n1170 , n1171 , n1172 , n1173 , n1174 , n1175 , n1176 , n1177 , n1178 , n1179 , n1180 , n1181 , n1182 , n1183 , n1184 , n1185 , n1186 , n1187 , n1188 , n1189 , n1190 , n1191 , n1192 , n1193 , n1194 , n1195 , n1196 , n1197 , n1198 , n1199 , n1200 , n1201 , n1202 , n1203 , n1204 , n1205 , n1206 , n1207 , n1208 , n1209 , n1210 , n1211 , n1212 , n1213 , n1214 , n1215 , n1216 , n1217 , n1218 , n1219 , n1220 , n1221 , n1222 , n1223 , n1224 , n1225 , n1226 , n1227 , n1228 , n1229 , n1230 , n1231 , n1232 , n1233 , n1234 , n1235 , n1236 , n1237 , n1238 , n1239 , n1240 , n1241 , n1242 , n1243 , n1244 , n1245 , n1246 , n1247 , n1248 , n1249 , n1250 , n1251 , n1252 , n1253 , n1254 , n1255 , n1256 , n1257 , n1258 , n1259 , n1260 , n1261 , n1262 , n1263 , n1264 , n1265 , n1266 , n1267 , n1268 , n1269 , n1270 , n1271 , n1272 , n1273 , n1274 , n1275 , n1276 , n1277 , n1278 , n1279 , n1280 , n1281 , n1282 , n1283 , n1284 , n1285 , n1286 , n1287 , n1288 , n1289 , n1290 , n1291 , n1292 , n1293 , n1294 , n1295 , n1296 , n1297 , n1298 , n1299 , n1300 , n1301 , n1302 , n1303 , n1304 , n1305 , n1306 , n1307 , n1308 , n1309 , n1310 , n1311 , n1312 , n1313 , n1314 , n1315 , n1316 , n1317 , n1318 , n1319 , n1320 , n1321 , n1322 , n1323 , n1324 , n1325 , n1326 , n1327 , n1328 , n1329 , n1330 , n1331 , n1332 , n1333 , n1334 , n1335 , n1336 , n1337 , n1338 , n1339 , n1340 , n1341 , n1342 , n1343 , n1344 , n1345 , n1346 , n1347 , n1348 , n1349 , n1350 , n1351 , n1352 , n1353 , n1354 , n1355 , n1356 , n1357 , n1358 , n1359 , n1360 , n1361 , n1362 , n1363 , n1364 , n1365 , n1366 , n1367 , n1368 , n1369 , n1370 , n1371 , n1372 , n1373 , n1374 , n1375 , n1376 , n1377 , n1378 , n1379 , n1380 , n1381 , n1382 , n1383 , n1384 , n1385 , n1386 , n1387 , n1388 , n1389 , n1390 , n1391 , n1392 , n1393 , n1394 , n1395 , n1396 , n1397 , n1398 , n1399 , n1400 , n1401 , n1402 , n1403 , n1404 , n1405 , n1406 , n1407 , n1408 , n1409 , n1410 , n1411 , n1412 , n1413 , n1414 , n1415 , n1416 , n1417 , n1418 , n1419 , n1420 , n1421 , n1422 , n1423 , n1424 , n1425 , n1426 , n1427 , n1428 , n1429 , n1430 , n1431 , n1432 , n1433 , n1434 , n1435 , n1436 , n1437 , n1438 , n1439 , n1440 , n1441 , n1442 , n1443 , n1444 , n1445 , n1446 , n1447 , n1448 , n1449 , n1450 , n1451 , n1452 , n1453 , n1454 , n1455 , n1456 , n1457 , n1458 , n1459 , n1460 , n1461 , n1462 , n1463 , n1464 , n1465 , n1466 , n1467 , n1468 , n1469 , n1470 , n1471 , n1472 , n1473 , n1474 , n1475 , n1476 , n1477 , n1478 , n1479 , n1480 , n1481 , n1482 , n1483 , n1484 , n1485 , n1486 , n1487 , n1488 , n1489 , n1490 , n1491 , n1492 , n1493 , n1494 , n1495 , n1496 , n1497 , n1498 , n1499 , n1500 , n1501 , n1502 , n1503 , n1504 , n1505 , n1506 , n1507 , n1508 , n1509 , n1510 , n1511 , n1512 , n1513 , n1514 , n1515 , n1516 , n1517 , n1518 , n1519 , n1520 , n1521 , n1522 , n1523 , n1524 , n1525 , n1526 , n1527 , n1528 , n1529 , n1530 , n1531 , n1532 , n1533 , n1534 , n1535 , n1536 , n1537 , n1538 , n1539 , n1540 , n1541 , n1542 , n1543 , n1544 , n1545 , n1546 , n1547 , n1548 , n1549 , n1550 , n1551 , n1552 , n1553 , n1554 , n1555 , n1556 , n1557 , n1558 , n1559 , n1560 , n1561 , n1562 , n1563 , n1564 , n1565 , n1566 , n1567 , n1568 , n1569 , n1570 , n1571 , n1572 , n1573 , n1574 , n1575 , n1576 , n1577 , n1578 , n1579 , n1580 , n1581 , n1582 , n1583 , n1584 , n1585 , n1586 , n1587 , n1588 , n1589 , n1590 , n1591 , n1592 , n1593 , n1594 , n1595 , n1596 , n1597 , n1598 , n1599 , n1600 , n1601 , n1602 , n1603 , n1604 , n1605 , n1606 , n1607 , n1608 , n1609 , n1610 , n1611 , n1612 , n1613 , n1614 , n1615 , n1616 , n1617 , n1618 , n1619 , n1620 , n1621 , n1622 , n1623 , n1624 , n1625 , n1626 , n1627 , n1628 , n1629 , n1630 , n1631 , n1632 , n1633 , n1634 , n1635 , n1636 , n1637 , n1638 , n1639 , n1640 , n1641 , n1642 , n1643 , n1644 , n1645 , n1646 , n1647 , n1648 , n1649 , n1650 , n1651 , n1652 , n1653 , n1654 , n1655 , n1656 , n1657 , n1658 , n1659 , n1660 , n1661 , n1662 , n1663 , n1664 , n1665 , n1666 , n1667 , n1668 , n1669 , n1670 , n1671 , n1672 , n1673 , n1674 , n1675 , n1676 , n1677 , n1678 , n1679 , n1680 , n1681 , n1682 , n1683 , n1684 , n1685 , n1686 , n1687 , n1688 , n1689 , n1690 , n1691 , n1692 , n1693 , n1694 , n1695 , n1696 , n1697 , n1698 , n1699 , n1700 , n1701 , n1702 , n1703 , n1704 , n1705 , n1706 , n1707 , n1708 , n1709 , n1710 , n1711 , n1712 , n1713 , n1714 , n1715 , n1716 , n1717 , n1718 , n1719 , n1720 , n1721 , n1722 , n1723 , n1724 , n1725 , n1726 , n1727 , n1728 , n1729 , n1730 , n1731 , n1732 , n1733 , n1734 , n1735 , n1736 , n1737 , n1738 , n1739 , n1740 , n1741 , n1742 , n1743 , n1744 , n1745 , n1746 , n1747 , n1748 , n1749 , n1750 , n1751 , n1752 , n1753 , n1754 , n1755 , n1756 , n1757 , n1758 , n1759 , n1760 , n1761 , n1762 , n1763 , n1764 , n1765 , n1766 , n1767 , n1768 , n1769 , n1770 , n1771 , n1772 , n1773 , n1774 , n1775 , n1776 , n1777 , n1778 , n1779 , n1780 , n1781 , n1782 , n1783 , n1784 , n1785 , n1786 , n1787 , n1788 , n1789 , n1790 , n1791 , n1792 , n1793 , n1794 , n1795 , n1796 , n1797 , n1798 , n1799 , n1800 , n1801 , n1802 , n1803 , n1804 , n1805 , n1806 , n1807 , n1808 , n1809 , n1810 , n1811 , n1812 , n1813 , n1814 , n1815 , n1816 , n1817 , n1818 , n1819 , n1820 , n1821 , n1822 , n1823 , n1824 , n1825 , n1826 , n1827 , n1828 , n1829 , n1830 , n1831 , n1832 , n1833 , n1834 , n1835 , n1836 , n1837 , n1838 , n1839 , n1840 , n1841 , n1842 , n1843 , n1844 , n1845 , n1846 , n1847 , n1848 , n1849 , n1850 , n1851 , n1852 , n1853 , n1854 , n1855 , n1856 , n1857 , n1858 , n1859 , n1860 , n1861 , n1862 , n1863 , n1864 , n1865 , n1866 , n1867 , n1868 , n1869 , n1870 , n1871 , n1872 , n1873 , n1874 , n1875 , n1876 , n1877 , n1878 , n1879 , n1880 , n1881 , n1882 , n1883 , n1884 , n1885 , n1886 , n1887 , n1888 , n1889 , n1890 , n1891 , n1892 , n1893 , n1894 , n1895 , n1896 , n1897 , n1898 , n1899 , n1900 , n1901 , n1902 , n1903 , n1904 , n1905 , n1906 , n1907 , n1908 , n1909 , n1910 , n1911 , n1912 , n1913 , n1914 , n1915 , n1916 , n1917 , n1918 , n1919 , n1920 , n1921 , n1922 , n1923 , n1924 , n1925 , n1926 , n1927 , n1928 , n1929 , n1930 , n1931 , n1932 , n1933 , n1934 , n1935 , n1936 , n1937 , n1938 , n1939 , n1940 , n1941 , n1942 , n1943 , n1944 , n1945 , n1946 , n1947 , n1948 , n1949 , n1950 , n1951 , n1952 , n1953 , n1954 , n1955 , n1956 , n1957 , n1958 , n1959 , n1960 , n1961 , n1962 , n1963 , n1964 , n1965 , n1966 , n1967 , n1968 , n1969 , n1970 , n1971 , n1972 , n1973 , n1974 , n1975 , n1976 , n1977 , n1978 , n1979 , n1980 , n1981 , n1982 , n1983 , n1984 , n1985 , n1986 , n1987 , n1988 , n1989 , n1990 , n1991 , n1992 , n1993 , n1994 , n1995 , n1996 , n1997 , n1998 , n1999 , n2000 , n2001 , n2002 , n2003 , n2004 , n2005 , n2006 , n2007 , n2008 , n2009 , n2010 , n2011 , n2012 , n2013 , n2014 , n2015 , n2016 , n2017 , n2018 , n2019 , n2020 , n2021 , n2022 , n2023 , n2024 , n2025 , n2026 , n2027 , n2028 , n2029 , n2030 , n2031 , n2032 , n2033 , n2034 , n2035 , n2036 , n2037 , n2038 , n2039 , n2040 , n2041 , n2042 , n2043 , n2044 , n2045 , n2046 , n2047 , n2048 , n2049 , n2050 , n2051 , n2052 , n2053 , n2054 , n2055 , n2056 , n2057 , n2058 , n2059 , n2060 , n2061 , n2062 , n2063 , n2064 , n2065 , n2066 , n2067 , n2068 , n2069 , n2070 , n2071 , n2072 , n2073 , n2074 , n2075 , n2076 , n2077 , n2078 , n2079 , n2080 , n2081 , n2082 , n2083 , n2084 , n2085 , n2086 , n2087 , n2088 , n2089 , n2090 , n2091 , n2092 , n2093 , n2094 , n2095 , n2096 , n2097 , n2098 , n2099 , n2100 , n2101 , n2102 , n2103 , n2104 , n2105 , n2106 , n2107 , n2108 , n2109 , n2110 , n2111 , n2112 , n2113 , n2114 , n2115 , n2116 , n2117 , n2118 , n2119 , n2120 , n2121 , n2122 , n2123 , n2124 , n2125 , n2126 , n2127 , n2128 , n2129 , n2130 , n2131 , n2132 , n2133 , n2134 , n2135 , n2136 , n2137 , n2138 , n2139 , n2140 , n2141 , n2142 , n2143 , n2144 , n2145 , n2146 , n2147 , n2148 , n2149 , n2150 , n2151 , n2152 , n2153 , n2154 , n2155 , n2156 , n2157 , n2158 , n2159 , n2160 );
input n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 , n80 , n81 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 , n96 , n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 , n106 , n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 , n116 , n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 , n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 , n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 , n146 , n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 , n156 , n157 , n158 , n159 , n160 , n161 , n162 , n163 , n164 , n165 , n166 , n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 , n175 , n176 , n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 , n185 , n186 , n187 , n188 , n189 , n190 , n191 , n192 , n193 , n194 , n195 , n196 , n197 , n198 , n199 , n200 , n201 , n202 , n203 , n204 , n205 , n206 , n207 , n208 , n209 , n210 , n211 , n212 , n213 , n214 , n215 , n216 , n217 , n218 , n219 , n220 , n221 , n222 , n223 , n224 , n225 , n226 , n227 , n228 , n229 , n230 , n231 , n232 , n233 , n234 , n235 , n236 , n237 , n238 , n239 , n240 , n241 , n242 , n243 , n244 , n245 , n246 , n247 , n248 , n249 , n250 , n251 , n252 , n253 , n254 , n255 , n256 , n257 , n258 , n259 , n260 , n261 , n262 , n263 , n264 , n265 , n266 , n267 , n268 , n269 , n270 , n271 , n272 , n273 , n274 , n275 , n276 , n277 , n278 , n279 , n280 , n281 , n282 , n283 , n284 , n285 , n286 , n287 , n288 , n289 , n290 , n291 , n292 , n293 , n294 , n295 , n296 , n297 , n298 , n299 , n300 , n301 , n302 , n303 , n304 , n305 , n306 , n307 , n308 , n309 , n310 , n311 , n312 , n313 , n314 , n315 , n316 , n317 , n318 , n319 , n320 , n321 , n322 , n323 , n324 , n325 , n326 , n327 , n328 , n329 , n330 , n331 , n332 , n333 , n334 , n335 , n336 , n337 , n338 , n339 , n340 , n341 , n342 , n343 , n344 , n345 , n346 , n347 , n348 , n349 , n350 , n351 , n352 , n353 , n354 , n355 , n356 , n357 , n358 , n359 , n360 , n361 , n362 , n363 , n364 , n365 , n366 , n367 , n368 , n369 , n370 , n371 , n372 , n373 , n374 , n375 , n376 , n377 , n378 , n379 , n380 , n381 , n382 , n383 , n384 , n385 , n386 , n387 , n388 , n389 , n390 , n391 , n392 , n393 , n394 , n395 , n396 , n397 , n398 , n399 , n400 , n401 , n402 , n403 , n404 , n405 , n406 , n407 , n408 , n409 , n410 , n411 , n412 , n413 , n414 , n415 , n416 , n417 , n418 , n419 , n420 , n421 , n422 , n423 , n424 , n425 , n426 , n427 , n428 , n429 , n430 , n431 , n432 , n433 , n434 , n435 , n436 , n437 , n438 , n439 , n440 , n441 , n442 , n443 , n444 , n445 , n446 , n447 , n448 , n449 , n450 , n451 , n452 , n453 , n454 , n455 , n456 , n457 , n458 , n459 , n460 , n461 , n462 , n463 , n464 , n465 , n466 , n467 , n468 , n469 , n470 , n471 , n472 , n473 , n474 , n475 , n476 , n477 , n478 , n479 , n480 , n481 , n482 , n483 , n484 , n485 , n486 , n487 , n488 , n489 , n490 , n491 , n492 , n493 , n494 , n495 , n496 , n497 , n498 , n499 , n500 , n501 , n502 , n503 , n504 , n505 , n506 , n507 , n508 , n509 , n510 , n511 , n512 , n513 , n514 , n515 , n516 , n517 , n518 , n519 , n520 , n521 , n522 , n523 , n524 , n525 , n526 , n527 , n528 , n529 , n530 , n531 , n532 , n533 , n534 , n535 , n536 , n537 , n538 , n539 , n540 , n541 , n542 , n543 , n544 , n545 , n546 , n547 , n548 , n549 , n550 , n551 , n552 , n553 , n554 , n555 , n556 , n557 , n558 , n559 , n560 , n561 , n562 , n563 , n564 , n565 , n566 , n567 , n568 , n569 , n570 , n571 , n572 , n573 , n574 , n575 , n576 , n577 , n578 , n579 , n580 , n581 , n582 , n583 , n584 , n585 , n586 , n587 , n588 , n589 , n590 , n591 , n592 , n593 , n594 , n595 , n596 , n597 , n598 , n599 , n600 , n601 , n602 , n603 , n604 , n605 , n606 , n607 , n608 , n609 , n610 , n611 , n612 , n613 , n614 , n615 , n616 , n617 , n618 , n619 , n620 , n621 , n622 , n623 , n624 , n625 , n626 , n627 , n628 , n629 , n630 , n631 , n632 , n633 , n634 , n635 , n636 , n637 , n638 , n639 , n640 , n641 , n642 , n643 , n644 , n645 , n646 , n647 , n648 , n649 , n650 , n651 , n652 , n653 , n654 , n655 , n656 , n657 , n658 , n659 , n660 , n661 , n662 , n663 , n664 , n665 , n666 , n667 , n668 , n669 , n670 , n671 , n672 , n673 , n674 , n675 , n676 , n677 , n678 , n679 , n680 , n681 , n682 , n683 , n684 , n685 , n686 , n687 , n688 , n689 , n690 , n691 , n692 , n693 , n694 , n695 , n696 , n697 , n698 , n699 , n700 , n701 , n702 , n703 , n704 , n705 , n706 , n707 , n708 , n709 , n710 , n711 , n712 , n713 , n714 , n715 , n716 , n717 , n718 , n719 , n720 , n721 , n722 , n723 , n724 , n725 , n726 , n727 , n728 , n729 , n730 , n731 , n732 , n733 , n734 , n735 , n736 , n737 , n738 , n739 , n740 , n741 , n742 , n743 , n744 , n745 , n746 , n747 , n748 , n749 , n750 , n751 , n752 , n753 , n754 , n755 , n756 , n757 , n758 , n759 , n760 , n761 , n762 , n763 , n764 , n765 , n766 , n767 , n768 , n769 , n770 , n771 , n772 , n773 , n774 , n775 , n776 , n777 , n778 , n779 , n780 , n781 , n782 , n783 , n784 , n785 , n786 , n787 , n788 , n789 , n790 , n791 , n792 , n793 , n794 , n795 , n796 , n797 , n798 , n799 , n800 , n801 , n802 , n803 , n804 , n805 , n806 , n807 , n808 , n809 , n810 , n811 , n812 , n813 , n814 , n815 , n816 , n817 , n818 , n819 , n820 , n821 , n822 , n823 , n824 , n825 , n826 , n827 , n828 , n829 , n830 , n831 , n832 , n833 , n834 , n835 , n836 , n837 , n838 , n839 , n840 , n841 , n842 , n843 , n844 , n845 , n846 , n847 , n848 , n849 , n850 , n851 , n852 , n853 , n854 , n855 , n856 , n857 , n858 , n859 , n860 , n861 , n862 , n863 , n864 , n865 , n866 , n867 , n868 , n869 , n870 , n871 , n872 , n873 , n874 , n875 , n876 , n877 , n878 , n879 , n880 , n881 , n882 , n883 , n884 , n885 , n886 , n887 , n888 , n889 , n890 , n891 , n892 , n893 , n894 , n895 , n896 , n897 , n898 , n899 , n900 , n901 , n902 , n903 , n904 , n905 , n906 , n907 , n908 , n909 , n910 , n911 , n912 , n913 , n914 , n915 , n916 , n917 , n918 , n919 , n920 , n921 , n922 , n923 , n924 , n925 , n926 , n927 , n928 , n929 , n930 , n931 , n932 , n933 , n934 , n935 , n936 , n937 , n938 , n939 , n940 , n941 , n942 , n943 , n944 , n945 , n946 , n947 , n948 , n949 , n950 , n951 , n952 , n953 , n954 , n955 , n956 , n957 , n958 , n959 , n960 , n961 , n962 , n963 , n964 , n965 , n966 , n967 , n968 , n969 , n970 , n971 , n972 , n973 , n974 , n975 , n976 , n977 , n978 , n979 , n980 , n981 , n982 , n983 , n984 , n985 , n986 , n987 , n988 , n989 , n990 , n991 , n992 , n993 , n994 , n995 , n996 , n997 , n998 , n999 , n1000 , n1001 , n1002 , n1003 , n1004 , n1005 , n1006 , n1007 , n1008 , n1009 , n1010 , n1011 , n1012 , n1013 , n1014 , n1015 , n1016 , n1017 , n1018 , n1019 , n1020 , n1021 , n1022 , n1023 , n1024 , n1025 , n1026 , n1027 , n1028 , n1029 , n1030 , n1031 , n1032 , n1033 , n1034 , n1035 , n1036 , n1037 , n1038 , n1039 , n1040 , n1041 , n1042 , n1043 , n1044 , n1045 , n1046 , n1047 , n1048 , n1049 , n1050 , n1051 , n1052 , n1053 , n1054 , n1055 , n1056 , n1057 , n1058 , n1059 , n1060 , n1061 , n1062 , n1063 , n1064 , n1065 , n1066 , n1067 , n1068 , n1069 , n1070 , n1071 , n1072 , n1073 , n1074 , n1075 , n1076 , n1077 , n1078 , n1079 , n1080 , n1081 , n1082 , n1083 , n1084 , n1085 , n1086 , n1087 , n1088 , n1089 , n1090 , n1091 , n1092 , n1093 , n1094 , n1095 , n1096 , n1097 , n1098 , n1099 , n1100 , n1101 , n1102 , n1103 , n1104 , n1105 , n1106 , n1107 , n1108 , n1109 , n1110 , n1111 , n1112 , n1113 , n1114 , n1115 , n1116 , n1117 , n1118 , n1119 , n1120 , n1121 , n1122 , n1123 , n1124 , n1125 , n1126 , n1127 , n1128 , n1129 , n1130 , n1131 , n1132 , n1133 , n1134 , n1135 , n1136 , n1137 , n1138 , n1139 , n1140 , n1141 , n1142 , n1143 , n1144 , n1145 , n1146 , n1147 , n1148 , n1149 , n1150 , n1151 , n1152 , n1153 , n1154 , n1155 , n1156 , n1157 , n1158 , n1159 , n1160 , n1161 , n1162 , n1163 , n1164 , n1165 , n1166 , n1167 , n1168 , n1169 , n1170 , n1171 , n1172 , n1173 , n1174 , n1175 , n1176 , n1177 , n1178 , n1179 , n1180 , n1181 , n1182 , n1183 , n1184 , n1185 , n1186 , n1187 , n1188 , n1189 , n1190 , n1191 , n1192 , n1193 , n1194 , n1195 , n1196 , n1197 , n1198 , n1199 , n1200 , n1201 , n1202 , n1203 , n1204 , n1205 , n1206 , n1207 , n1208 , n1209 , n1210 , n1211 , n1212 , n1213 , n1214 , n1215 , n1216 , n1217 , n1218 , n1219 , n1220 , n1221 , n1222 , n1223 , n1224 , n1225 , n1226 , n1227 , n1228 , n1229 , n1230 , n1231 , n1232 , n1233 , n1234 , n1235 , n1236 , n1237 , n1238 , n1239 , n1240 , n1241 , n1242 , n1243 , n1244 , n1245 , n1246 , n1247 , n1248 , n1249 , n1250 , n1251 , n1252 , n1253 , n1254 , n1255 , n1256 , n1257 , n1258 , n1259 , n1260 , n1261 , n1262 , n1263 , n1264 , n1265 , n1266 , n1267 , n1268 , n1269 , n1270 , n1271 , n1272 , n1273 , n1274 , n1275 , n1276 , n1277 , n1278 , n1279 , n1280 , n1281 , n1282 , n1283 , n1284 , n1285 , n1286 , n1287 , n1288 , n1289 , n1290 , n1291 , n1292 , n1293 , n1294 , n1295 , n1296 , n1297 , n1298 , n1299 , n1300 , n1301 , n1302 , n1303 , n1304 , n1305 , n1306 , n1307 , n1308 , n1309 , n1310 , n1311 , n1312 , n1313 , n1314 , n1315 , n1316 , n1317 , n1318 , n1319 , n1320 , n1321 , n1322 , n1323 , n1324 , n1325 , n1326 , n1327 , n1328 , n1329 , n1330 , n1331 , n1332 , n1333 , n1334 , n1335 , n1336 , n1337 , n1338 , n1339 , n1340 , n1341 , n1342 , n1343 , n1344 , n1345 , n1346 , n1347 , n1348 , n1349 , n1350 , n1351 , n1352 , n1353 , n1354 , n1355 , n1356 , n1357 , n1358 , n1359 , n1360 , n1361 , n1362 , n1363 , n1364 , n1365 , n1366 , n1367 , n1368 , n1369 , n1370 , n1371 , n1372 , n1373 , n1374 , n1375 , n1376 , n1377 , n1378 , n1379 , n1380 , n1381 , n1382 , n1383 , n1384 , n1385 , n1386 , n1387 , n1388 , n1389 , n1390 , n1391 , n1392 , n1393 , n1394 , n1395 , n1396 , n1397 , n1398 , n1399 , n1400 , n1401 , n1402 , n1403 , n1404 , n1405 , n1406 , n1407 , n1408 , n1409 , n1410 , n1411 , n1412 , n1413 , n1414 , n1415 , n1416 , n1417 , n1418 , n1419 , n1420 , n1421 , n1422 , n1423 , n1424 , n1425 , n1426 , n1427 , n1428 , n1429 , n1430 , n1431 , n1432 , n1433 , n1434 , n1435 , n1436 , n1437 , n1438 , n1439 , n1440 , n1441 , n1442 , n1443 , n1444 , n1445 , n1446 , n1447 , n1448 , n1449 , n1450 , n1451 , n1452 , n1453 , n1454 , n1455 , n1456 , n1457 , n1458 , n1459 , n1460 , n1461 , n1462 , n1463 , n1464 , n1465 , n1466 , n1467 , n1468 , n1469 , n1470 , n1471 , n1472 , n1473 , n1474 , n1475 , n1476 , n1477 , n1478 , n1479 , n1480 , n1481 , n1482 , n1483 , n1484 , n1485 , n1486 , n1487 , n1488 , n1489 , n1490 , n1491 , n1492 , n1493 , n1494 , n1495 , n1496 , n1497 , n1498 , n1499 , n1500 , n1501 , n1502 , n1503 , n1504 , n1505 , n1506 , n1507 , n1508 , n1509 , n1510 , n1511 , n1512 , n1513 , n1514 , n1515 , n1516 , n1517 , n1518 , n1519 , n1520 , n1521 , n1522 , n1523 , n1524 , n1525 , n1526 , n1527 , n1528 , n1529 , n1530 , n1531 , n1532 , n1533 , n1534 , n1535 , n1536 , n1537 , n1538 , n1539 , n1540 , n1541 , n1542 , n1543 , n1544 , n1545 , n1546 , n1547 , n1548 , n1549 , n1550 , n1551 , n1552 , n1553 , n1554 , n1555 , n1556 , n1557 , n1558 , n1559 , n1560 , n1561 , n1562 , n1563 , n1564 , n1565 , n1566 , n1567 , n1568 , n1569 , n1570 , n1571 , n1572 , n1573 , n1574 , n1575 , n1576 , n1577 , n1578 , n1579 , n1580 , n1581 , n1582 , n1583 , n1584 , n1585 , n1586 , n1587 , n1588 , n1589 , n1590 , n1591 , n1592 , n1593 , n1594 , n1595 , n1596 , n1597 , n1598 , n1599 , n1600 , n1601 , n1602 , n1603 , n1604 , n1605 , n1606 , n1607 , n1608 , n1609 , n1610 , n1611 , n1612 , n1613 , n1614 , n1615 , n1616 , n1617 , n1618 , n1619 , n1620 , n1621 , n1622 , n1623 , n1624 , n1625 , n1626 , n1627 , n1628 , n1629 , n1630 , n1631 , n1632 , n1633 , n1634 , n1635 , n1636 , n1637 , n1638 , n1639 , n1640 , n1641 , n1642 , n1643 , n1644 , n1645 , n1646 , n1647 , n1648 , n1649 , n1650 , n1651 , n1652 , n1653 , n1654 , n1655 , n1656 , n1657 , n1658 , n1659 , n1660 , n1661 , n1662 , n1663 , n1664 , n1665 , n1666 , n1667 , n1668 , n1669 , n1670 , n1671 , n1672 , n1673 , n1674 , n1675 , n1676 , n1677 , n1678 , n1679 , n1680 , n1681 , n1682 , n1683 , n1684 , n1685 , n1686 , n1687 , n1688 , n1689 , n1690 , n1691 , n1692 , n1693 , n1694 , n1695 , n1696 , n1697 , n1698 , n1699 , n1700 , n1701 , n1702 , n1703 , n1704 , n1705 , n1706 , n1707 , n1708 , n1709 , n1710 , n1711 , n1712 , n1713 , n1714 , n1715 , n1716 , n1717 , n1718 , n1719 , n1720 , n1721 , n1722 , n1723 , n1724 , n1725 , n1726 , n1727 , n1728 , n1729 , n1730 , n1731 , n1732 , n1733 , n1734 , n1735 , n1736 , n1737 , n1738 , n1739 , n1740 , n1741 , n1742 , n1743 , n1744 , n1745 , n1746 , n1747 , n1748 , n1749 , n1750 , n1751 , n1752 , n1753 , n1754 , n1755 , n1756 , n1757 , n1758 , n1759 , n1760 , n1761 , n1762 , n1763 , n1764 , n1765 , n1766 , n1767 , n1768 , n1769 , n1770 , n1771 , n1772 , n1773 , n1774 , n1775 , n1776 , n1777 , n1778 , n1779 , n1780 , n1781 , n1782 , n1783 , n1784 , n1785 , n1786 , n1787 , n1788 , n1789 , n1790 , n1791 , n1792 , n1793 , n1794 , n1795 , n1796 , n1797 , n1798 , n1799 , n1800 , n1801 , n1802 , n1803 , n1804 , n1805 , n1806 , n1807 , n1808 , n1809 , n1810 , n1811 , n1812 , n1813 , n1814 , n1815 , n1816 , n1817 , n1818 , n1819 , n1820 , n1821 , n1822 , n1823 , n1824 , n1825 , n1826 , n1827 , n1828 , n1829 , n1830 , n1831 , n1832 , n1833 , n1834 , n1835 , n1836 , n1837 , n1838 , n1839 , n1840 , n1841 , n1842 , n1843 , n1844 , n1845 , n1846 , n1847 , n1848 , n1849 , n1850 , n1851 , n1852 , n1853 , n1854 , n1855 , n1856 , n1857 , n1858 , n1859 , n1860 , n1861 , n1862 , n1863 , n1864 , n1865 , n1866 , n1867 , n1868 , n1869 , n1870 , n1871 , n1872 , n1873 , n1874 , n1875 , n1876 , n1877 , n1878 , n1879 , n1880 , n1881 , n1882 , n1883 , n1884 , n1885 , n1886 , n1887 , n1888 , n1889 , n1890 , n1891 , n1892 , n1893 , n1894 , n1895 , n1896 , n1897 , n1898 , n1899 , n1900 , n1901 , n1902 , n1903 , n1904 , n1905 , n1906 , n1907 , n1908 , n1909 , n1910 , n1911 , n1912 , n1913 , n1914 , n1915 , n1916 , n1917 , n1918 , n1919 , n1920 , n1921 , n1922 , n1923 , n1924 , n1925 , n1926 , n1927 , n1928 , n1929 , n1930 , n1931 , n1932 , n1933 , n1934 , n1935 , n1936 , n1937 , n1938 , n1939 , n1940 , n1941 , n1942 , n1943 , n1944 , n1945 , n1946 , n1947 , n1948 , n1949 , n1950 , n1951 , n1952 , n1953 , n1954 , n1955 , n1956 , n1957 , n1958 , n1959 , n1960 , n1961 , n1962 , n1963 , n1964 , n1965 , n1966 , n1967 , n1968 , n1969 , n1970 , n1971 , n1972 , n1973 , n1974 , n1975 , n1976 , n1977 , n1978 , n1979 , n1980 , n1981 , n1982 , n1983 , n1984 , n1985 , n1986 , n1987 , n1988 , n1989 , n1990 , n1991 , n1992 , n1993 , n1994 , n1995 , n1996 , n1997 , n1998 , n1999 , n2000 , n2001 , n2002 , n2003 , n2004 , n2005 , n2006 , n2007 , n2008 , n2009 , n2010 , n2011 , n2012 , n2013 , n2014 , n2015 , n2016 , n2017 , n2018 , n2019 , n2020 , n2021 , n2022 , n2023 , n2024 , n2025 , n2026 , n2027 , n2028 , n2029 , n2030 , n2031 , n2032 , n2033 , n2034 , n2035 , n2036 , n2037 , n2038 , n2039 , n2040 , n2041 , n2042 , n2043 , n2044 , n2045 , n2046 , n2047 , n2048 , n2049 , n2050 , n2051 , n2052 , n2053 , n2054 , n2055 , n2056 , n2057 , n2058 , n2059 , n2060 , n2061 , n2062 , n2063 , n2064 , n2065 , n2066 , n2067 , n2068 , n2069 , n2070 , n2071 , n2072 , n2073 , n2074 , n2075 , n2076 , n2077 , n2078 , n2079 , n2080 , n2081 , n2082 , n2083 , n2084 , n2085 , n2086 , n2087 , n2088 , n2089 , n2090 , n2091 , n2092 , n2093 , n2094 , n2095 , n2096 , n2097 , n2098 , n2099 , n2100 , n2101 , n2102 , n2103 , n2104 , n2105 , n2106 , n2107 , n2108 , n2109 , n2110 , n2111 , n2112 , n2113 , n2114 , n2115 , n2116 , n2117 , n2118 , n2119 , n2120 , n2121 , n2122 , n2123 , n2124 , n2125 , n2126 , n2127 , n2128 , n2129 , n2130 , n2131 , n2132 , n2133 , n2134 , n2135 , n2136 , n2137 , n2138 , n2139 , n2140 , n2141 , n2142 , n2143 , n2144 , n2145 , n2146 , n2147 , n2148 , n2149 , n2150 ;
output n2151 , n2152 , n2153 , n2154 , n2155 , n2156 , n2157 , n2158 , n2159 , n2160 ;
wire n4322 , n4323 , n4324 , n4325 , n4326 , n4327 , n4328 , n4329 , n4330 ,
n4331 , n4332 , n4333 , n4334 , n4335 , n4336 , n4337 , n4338 , n4339 , n4340 ,
n4341 , n4342 , n4343 , n4344 , n4345 , n4346 , n4347 , n4348 , n4349 , n4350 ,
n4351 , n4352 , n4353 , n4354 , n4355 , n4356 , n4357 , n4358 , n4359 , n4360 ,
n4361 , n4362 , n4363 , n4364 , n4365 , n4366 , n4367 , n4368 , n4369 , n4370 ,
n4371 , n4372 , n4373 , n4374 , n4375 , n4376 , n4377 , n4378 , n4379 , n4380 ,
n4381 , n4382 , n4383 , n4384 , n4385 , n4386 , n4387 , n4388 , n4389 , n4390 ,
n4391 , n4392 , n4393 , n4394 , n4395 , n4396 , n4397 , n4398 , n4399 , n4400 ,
n4401 , n4402 , n4403 , n4404 , n4405 , n4406 , n4407 , n4408 , n4409 , n4410 ,
n4411 , n4412 , n4413 , n4414 , n4415 , n4416 , n4417 , n4418 , n4419 , n4420 ,
n4421 , n4422 , n4423 , n4424 , n4425 , n4426 , n4427 , n4428 , n4429 , n4430 ,
n4431 , n4432 , n4433 , n4434 , n4435 , n4436 , n4437 , n4438 , n4439 , n4440 ,
n4441 , n4442 , n4443 , n4444 , n4445 , n4446 , n4447 , n4448 , n4449 , n4450 ,
n4451 , n4452 , n4453 , n4454 , n4455 , n4456 , n4457 , n4458 , n4459 , n4460 ,
n4461 , n4462 , n4463 , n4464 , n4465 , n4466 , n4467 , n4468 , n4469 , n4470 ,
n4471 , n4472 , n4473 , n4474 , n4475 , n4476 , n4477 , n4478 , n4479 , n4480 ,
n4481 , n4482 , n4483 , n4484 , n4485 , n4486 , n4487 , n4488 , n4489 , n4490 ,
n4491 , n4492 , n4493 , n4494 , n4495 , n4496 , n4497 , n4498 , n4499 , n4500 ,
n4501 , n4502 , n4503 , n4504 , n4505 , n4506 , n4507 , n4508 , n4509 , n4510 ,
n4511 , n4512 , n4513 , n4514 , n4515 , n4516 , n4517 , n4518 , n4519 , n4520 ,
n4521 , n4522 , n4523 , n4524 , n4525 , n4526 , n4527 , n4528 , n4529 , n4530 ,
n4531 , n4532 , n4533 , n4534 , n4535 , n4536 , n4537 , n4538 , n4539 , n4540 ,
n4541 , n4542 , n4543 , n4544 , n4545 , n4546 , n4547 , n4548 , n4549 , n4550 ,
n4551 , n4552 , n4553 , n4554 , n4555 , n4556 , n4557 , n4558 , n4559 , n4560 ,
n4561 , n4562 , n4563 , n4564 , n4565 , n4566 , n4567 , n4568 , n4569 , n4570 ,
n4571 , n4572 , n4573 , n4574 , n4575 , n4576 , n4577 , n4578 , n4579 , n4580 ,
n4581 , n4582 , n4583 , n4584 , n4585 , n4586 , n4587 , n4588 , n4589 , n4590 ,
n4591 , n4592 , n4593 , n4594 , n4595 , n4596 , n4597 , n4598 , n4599 , n4600 ,
n4601 , n4602 , n4603 , n4604 , n4605 , n4606 , n4607 , n4608 , n4609 , n4610 ,
n4611 , n4612 , n4613 , n4614 , n4615 , n4616 , n4617 , n4618 , n4619 , n4620 ,
n4621 , n4622 , n4623 , n4624 , n4625 , n4626 , n4627 , n4628 , n4629 , n4630 ,
n4631 , n4632 , n4633 , n4634 , n4635 , n4636 , n4637 , n4638 , n4639 , n4640 ,
n4641 , n4642 , n4643 , n4644 , n4645 , n4646 , n4647 , n4648 , n4649 , n4650 ,
n4651 , n4652 , n4653 , n4654 , n4655 , n4656 , n4657 , n4658 , n4659 , n4660 ,
n4661 , n4662 , n4663 , n4664 , n4665 , n4666 , n4667 , n4668 , n4669 , n4670 ,
n4671 , n4672 , n4673 , n4674 , n4675 , n4676 , n4677 , n4678 , n4679 , n4680 ,
n4681 , n4682 , n4683 , n4684 , n4685 , n4686 , n4687 , n4688 , n4689 , n4690 ,
n4691 , n4692 , n4693 , n4694 , n4695 , n4696 , n4697 , n4698 , n4699 , n4700 ,
n4701 , n4702 , n4703 , n4704 , n4705 , n4706 , n4707 , n4708 , n4709 , n4710 ,
n4711 , n4712 , n4713 , n4714 , n4715 , n4716 , n4717 , n4718 , n4719 , n4720 ,
n4721 , n4722 , n4723 , n4724 , n4725 , n4726 , n4727 , n4728 , n4729 , n4730 ,
n4731 , n4732 , n4733 , n4734 , n4735 , n4736 , n4737 , n4738 , n4739 , n4740 ,
n4741 , n4742 , n4743 , n4744 , n4745 , n4746 , n4747 , n4748 , n4749 , n4750 ,
n4751 , n4752 , n4753 , n4754 , n4755 , n4756 , n4757 , n4758 , n4759 , n4760 ,
n4761 , n4762 , n4763 , n4764 , n4765 , n4766 , n4767 , n4768 , n4769 , n4770 ,
n4771 , n4772 , n4773 , n4774 , n4775 , n4776 , n4777 , n4778 , n4779 , n4780 ,
n4781 , n4782 , n4783 , n4784 , n4785 , n4786 , n4787 , n4788 , n4789 , n4790 ,
n4791 , n4792 , n4793 , n4794 , n4795 , n4796 , n4797 , n4798 , n4799 , n4800 ,
n4801 , n4802 , n4803 , n4804 , n4805 , n4806 , n4807 , n4808 , n4809 , n4810 ,
n4811 , n4812 , n4813 , n4814 , n4815 , n4816 , n4817 , n4818 , n4819 , n4820 ,
n4821 , n4822 , n4823 , n4824 , n4825 , n4826 , n4827 , n4828 , n4829 , n4830 ,
n4831 , n4832 , n4833 , n4834 , n4835 , n4836 , n4837 , n4838 , n4839 , n4840 ,
n4841 , n4842 , n4843 , n4844 , n4845 , n4846 , n4847 , n4848 , n4849 , n4850 ,
n4851 , n4852 , n4853 , n4854 , n4855 , n4856 , n4857 , n4858 , n4859 , n4860 ,
n4861 , n4862 , n4863 , n4864 , n4865 , n4866 , n4867 , n4868 , n4869 , n4870 ,
n4871 , n4872 , n4873 , n4874 , n4875 , n4876 , n4877 , n4878 , n4879 , n4880 ,
n4881 , n4882 , n4883 , n4884 , n4885 , n4886 , n4887 , n4888 , n4889 , n4890 ,
n4891 , n4892 , n4893 , n4894 , n4895 , n4896 , n4897 , n4898 , n4899 , n4900 ,
n4901 , n4902 , n4903 , n4904 , n4905 , n4906 , n4907 , n4908 , n4909 , n4910 ,
n4911 , n4912 , n4913 , n4914 , n4915 , n4916 , n4917 , n4918 , n4919 , n4920 ,
n4921 , n4922 , n4923 , n4924 , n4925 , n4926 , n4927 , n4928 , n4929 , n4930 ,
n4931 , n4932 , n4933 , n4934 , n4935 , n4936 , n4937 , n4938 , n4939 , n4940 ,
n4941 , n4942 , n4943 , n4944 , n4945 , n4946 , n4947 , n4948 , n4949 , n4950 ,
n4951 , n4952 , n4953 , n4954 , n4955 , n4956 , n4957 , n4958 , n4959 , n4960 ,
n4961 , n4962 , n4963 , n4964 , n4965 , n4966 , n4967 , n4968 , n4969 , n4970 ,
n4971 , n4972 , n4973 , n4974 , n4975 , n4976 , n4977 , n4978 , n4979 , n4980 ,
n4981 , n4982 , n4983 , n4984 , n4985 , n4986 , n4987 , n4988 , n4989 , n4990 ,
n4991 , n4992 , n4993 , n4994 , n4995 , n4996 , n4997 , n4998 , n4999 , n5000 ,
n5001 , n5002 , n5003 , n5004 , n5005 , n5006 , n5007 , n5008 , n5009 , n5010 ,
n5011 , n5012 , n5013 , n5014 , n5015 , n5016 , n5017 , n5018 , n5019 , n5020 ,
n5021 , n5022 , n5023 , n5024 , n5025 , n5026 , n5027 , n5028 , n5029 , n5030 ,
n5031 , n5032 , n5033 , n5034 , n5035 , n5036 , n5037 , n5038 , n5039 , n5040 ,
n5041 , n5042 , n5043 , n5044 , n5045 , n5046 , n5047 , n5048 , n5049 , n5050 ,
n5051 , n5052 , n5053 , n5054 , n5055 , n5056 , n5057 , n5058 , n5059 , n5060 ,
n5061 , n5062 , n5063 , n5064 , n5065 , n5066 , n5067 , n5068 , n5069 , n5070 ,
n5071 , n5072 , n5073 , n5074 , n5075 , n5076 , n5077 , n5078 , n5079 , n5080 ,
n5081 , n5082 , n5083 , n5084 , n5085 , n5086 , n5087 , n5088 , n5089 , n5090 ,
n5091 , n5092 , n5093 , n5094 , n5095 , n5096 , n5097 , n5098 , n5099 , n5100 ,
n5101 , n5102 , n5103 , n5104 , n5105 , n5106 , n5107 , n5108 , n5109 , n5110 ,
n5111 , n5112 , n5113 , n5114 , n5115 , n5116 , n5117 , n5118 , n5119 , n5120 ,
n5121 , n5122 , n5123 , n5124 , n5125 , n5126 , n5127 , n5128 , n5129 , n5130 ,
n5131 , n5132 , n5133 , n5134 , n5135 , n5136 , n5137 , n5138 , n5139 , n5140 ,
n5141 , n5142 , n5143 , n5144 , n5145 , n5146 , n5147 , n5148 , n5149 , n5150 ,
n5151 , n5152 , n5153 , n5154 , n5155 , n5156 , n5157 , n5158 , n5159 , n5160 ,
n5161 , n5162 , n5163 , n5164 , n5165 , n5166 , n5167 , n5168 , n5169 , n5170 ,
n5171 , n5172 , n5173 , n5174 , n5175 , n5176 , n5177 , n5178 , n5179 , n5180 ,
n5181 , n5182 , n5183 , n5184 , n5185 , n5186 , n5187 , n5188 , n5189 , n5190 ,
n5191 , n5192 , n5193 , n5194 , n5195 , n5196 , n5197 , n5198 , n5199 , n5200 ,
n5201 , n5202 , n5203 , n5204 , n5205 , n5206 , n5207 , n5208 , n5209 , n5210 ,
n5211 , n5212 , n5213 , n5214 , n5215 , n5216 , n5217 , n5218 , n5219 , n5220 ,
n5221 , n5222 , n5223 , n5224 , n5225 , n5226 , n5227 , n5228 , n5229 , n5230 ,
n5231 , n5232 , n5233 , n5234 , n5235 , n5236 , n5237 , n5238 , n5239 , n5240 ,
n5241 , n5242 , n5243 , n5244 , n5245 , n5246 , n5247 , n5248 , n5249 , n5250 ,
n5251 , n5252 , n5253 , n5254 , n5255 , n5256 , n5257 , n5258 , n5259 , n5260 ,
n5261 , n5262 , n5263 , n5264 , n5265 , n5266 , n5267 , n5268 , n5269 , n5270 ,
n5271 , n5272 , n5273 , n5274 , n5275 , n5276 , n5277 , n5278 , n5279 , n5280 ,
n5281 , n5282 , n5283 , n5284 , n5285 , n5286 , n5287 , n5288 , n5289 , n5290 ,
n5291 , n5292 , n5293 , n5294 , n5295 , n5296 , n5297 , n5298 , n5299 , n5300 ,
n5301 , n5302 , n5303 , n5304 , n5305 , n5306 , n5307 , n5308 , n5309 , n5310 ,
n5311 , n5312 , n5313 , n5314 , n5315 , n5316 , n5317 , n5318 , n5319 , n5320 ,
n5321 , n5322 , n5323 , n5324 , n5325 , n5326 , n5327 , n5328 , n5329 , n5330 ,
n5331 , n5332 , n5333 , n5334 , n5335 , n5336 , n5337 , n5338 , n5339 , n5340 ,
n5341 , n5342 , n5343 , n5344 , n5345 , n5346 , n5347 , n5348 , n5349 , n5350 ,
n5351 , n5352 , n5353 , n5354 , n5355 , n5356 , n5357 , n5358 , n5359 , n5360 ,
n5361 , n5362 , n5363 , n5364 , n5365 , n5366 , n5367 , n5368 , n5369 , n5370 ,
n5371 , n5372 , n5373 , n5374 , n5375 , n5376 , n5377 , n5378 , n5379 , n5380 ,
n5381 , n5382 , n5383 , n5384 , n5385 , n5386 , n5387 , n5388 , n5389 , n5390 ,
n5391 , n5392 , n5393 , n5394 , n5395 , n5396 , n5397 , n5398 , n5399 , n5400 ,
n5401 , n5402 , n5403 , n5404 , n5405 , n5406 , n5407 , n5408 , n5409 , n5410 ,
n5411 , n5412 , n5413 , n5414 , n5415 , n5416 , n5417 , n5418 , n5419 , n5420 ,
n5421 , n5422 , n5423 , n5424 , n5425 , n5426 , n5427 , n5428 , n5429 , n5430 ,
n5431 , n5432 , n5433 , n5434 , n5435 , n5436 , n5437 , n5438 , n5439 , n5440 ,
n5441 , n5442 , n5443 , n5444 , n5445 , n5446 , n5447 , n5448 , n5449 , n5450 ,
n5451 , n5452 , n5453 , n5454 , n5455 , n5456 , n5457 , n5458 , n5459 , n5460 ,
n5461 , n5462 , n5463 , n5464 , n5465 , n5466 , n5467 , n5468 , n5469 , n5470 ,
n5471 , n5472 , n5473 , n5474 , n5475 , n5476 , n5477 , n5478 , n5479 , n5480 ,
n5481 , n5482 , n5483 , n5484 , n5485 , n5486 , n5487 , n5488 , n5489 , n5490 ,
n5491 , n5492 , n5493 , n5494 , n5495 , n5496 , n5497 , n5498 , n5499 , n5500 ,
n5501 , n5502 , n5503 , n5504 , n5505 , n5506 , n5507 , n5508 , n5509 , n5510 ,
n5511 , n5512 , n5513 , n5514 , n5515 , n5516 , n5517 , n5518 , n5519 , n5520 ,
n5521 , n5522 , n5523 , n5524 , n5525 , n5526 , n5527 , n5528 , n5529 , n5530 ,
n5531 , n5532 , n5533 , n5534 , n5535 , n5536 , n5537 , n5538 , n5539 , n5540 ,
n5541 , n5542 , n5543 , n5544 , n5545 , n5546 , n5547 , n5548 , n5549 , n5550 ,
n5551 , n5552 , n5553 , n5554 , n5555 , n5556 , n5557 , n5558 , n5559 , n5560 ,
n5561 , n5562 , n5563 , n5564 , n5565 , n5566 , n5567 , n5568 , n5569 , n5570 ,
n5571 , n5572 , n5573 , n5574 , n5575 , n5576 , n5577 , n5578 , n5579 , n5580 ,
n5581 , n5582 , n5583 , n5584 , n5585 , n5586 , n5587 , n5588 , n5589 , n5590 ,
n5591 , n5592 , n5593 , n5594 , n5595 , n5596 , n5597 , n5598 , n5599 , n5600 ,
n5601 , n5602 , n5603 , n5604 , n5605 , n5606 , n5607 , n5608 , n5609 , n5610 ,
n5611 , n5612 , n5613 , n5614 , n5615 , n5616 , n5617 , n5618 , n5619 , n5620 ,
n5621 , n5622 , n5623 , n5624 , n5625 , n5626 , n5627 , n5628 , n5629 , n5630 ,
n5631 , n5632 , n5633 , n5634 , n5635 , n5636 , n5637 , n5638 , n5639 , n5640 ,
n5641 , n5642 , n5643 , n5644 , n5645 , n5646 , n5647 , n5648 , n5649 , n5650 ,
n5651 , n5652 , n5653 , n5654 , n5655 , n5656 , n5657 , n5658 , n5659 , n5660 ,
n5661 , n5662 , n5663 , n5664 , n5665 , n5666 , n5667 , n5668 , n5669 , n5670 ,
n5671 , n5672 , n5673 , n5674 , n5675 , n5676 , n5677 , n5678 , n5679 , n5680 ,
n5681 , n5682 , n5683 , n5684 , n5685 , n5686 , n5687 , n5688 , n5689 , n5690 ,
n5691 , n5692 , n5693 , n5694 , n5695 , n5696 , n5697 , n5698 , n5699 , n5700 ,
n5701 , n5702 , n5703 , n5704 , n5705 , n5706 , n5707 , n5708 , n5709 , n5710 ,
n5711 , n5712 , n5713 , n5714 , n5715 , n5716 , n5717 , n5718 , n5719 , n5720 ,
n5721 , n5722 , n5723 , n5724 , n5725 , n5726 , n5727 , n5728 , n5729 , n5730 ,
n5731 , n5732 , n5733 , n5734 , n5735 , n5736 , n5737 , n5738 , n5739 , n5740 ,
n5741 , n5742 , n5743 , n5744 , n5745 , n5746 , n5747 , n5748 , n5749 , n5750 ,
n5751 , n5752 , n5753 , n5754 , n5755 , n5756 , n5757 , n5758 , n5759 , n5760 ,
n5761 , n5762 , n5763 , n5764 , n5765 , n5766 , n5767 , n5768 , n5769 , n5770 ,
n5771 , n5772 , n5773 , n5774 , n5775 , n5776 , n5777 , n5778 , n5779 , n5780 ,
n5781 , n5782 , n5783 , n5784 , n5785 , n5786 , n5787 , n5788 , n5789 , n5790 ,
n5791 , n5792 , n5793 , n5794 , n5795 , n5796 , n5797 , n5798 , n5799 , n5800 ,
n5801 , n5802 , n5803 , n5804 , n5805 , n5806 , n5807 , n5808 , n5809 , n5810 ,
n5811 , n5812 , n5813 , n5814 , n5815 , n5816 , n5817 , n5818 , n5819 , n5820 ,
n5821 , n5822 , n5823 , n5824 , n5825 , n5826 , n5827 , n5828 , n5829 , n5830 ,
n5831 , n5832 , n5833 , n5834 , n5835 , n5836 , n5837 , n5838 , n5839 , n5840 ,
n5841 , n5842 , n5843 , n5844 , n5845 , n5846 , n5847 , n5848 , n5849 , n5850 ,
n5851 , n5852 , n5853 , n5854 , n5855 , n5856 , n5857 , n5858 , n5859 , n5860 ,
n5861 , n5862 , n5863 , n5864 , n5865 , n5866 , n5867 , n5868 , n5869 , n5870 ,
n5871 , n5872 , n5873 , n5874 , n5875 , n5876 , n5877 , n5878 , n5879 , n5880 ,
n5881 , n5882 , n5883 , n5884 , n5885 , n5886 , n5887 , n5888 , n5889 , n5890 ,
n5891 , n5892 , n5893 , n5894 , n5895 , n5896 , n5897 , n5898 , n5899 , n5900 ,
n5901 , n5902 , n5903 , n5904 , n5905 , n5906 , n5907 , n5908 , n5909 , n5910 ,
n5911 , n5912 , n5913 , n5914 , n5915 , n5916 , n5917 , n5918 , n5919 , n5920 ,
n5921 , n5922 , n5923 , n5924 , n5925 , n5926 , n5927 , n5928 , n5929 , n5930 ,
n5931 , n5932 , n5933 , n5934 , n5935 , n5936 , n5937 , n5938 , n5939 , n5940 ,
n5941 , n5942 , n5943 , n5944 , n5945 , n5946 , n5947 , n5948 , n5949 , n5950 ,
n5951 , n5952 , n5953 , n5954 , n5955 , n5956 , n5957 , n5958 , n5959 , n5960 ,
n5961 , n5962 , n5963 , n5964 , n5965 , n5966 , n5967 , n5968 , n5969 , n5970 ,
n5971 , n5972 , n5973 , n5974 , n5975 , n5976 , n5977 , n5978 , n5979 , n5980 ,
n5981 , n5982 , n5983 , n5984 , n5985 , n5986 , n5987 , n5988 , n5989 , n5990 ,
n5991 , n5992 , n5993 , n5994 , n5995 , n5996 , n5997 , n5998 , n5999 , n6000 ,
n6001 , n6002 , n6003 , n6004 , n6005 , n6006 , n6007 , n6008 , n6009 , n6010 ,
n6011 , n6012 , n6013 , n6014 , n6015 , n6016 , n6017 , n6018 , n6019 , n6020 ,
n6021 , n6022 , n6023 , n6024 , n6025 , n6026 , n6027 , n6028 , n6029 , n6030 ,
n6031 , n6032 , n6033 , n6034 , n6035 , n6036 , n6037 , n6038 , n6039 , n6040 ,
n6041 , n6042 , n6043 , n6044 , n6045 , n6046 , n6047 , n6048 , n6049 , n6050 ,
n6051 , n6052 , n6053 , n6054 , n6055 , n6056 , n6057 , n6058 , n6059 , n6060 ,
n6061 , n6062 , n6063 , n6064 , n6065 , n6066 , n6067 , n6068 , n6069 , n6070 ,
n6071 , n6072 , n6073 , n6074 , n6075 , n6076 , n6077 , n6078 , n6079 , n6080 ,
n6081 , n6082 , n6083 , n6084 , n6085 , n6086 , n6087 , n6088 , n6089 , n6090 ,
n6091 , n6092 , n6093 , n6094 , n6095 , n6096 , n6097 , n6098 , n6099 , n6100 ,
n6101 , n6102 , n6103 , n6104 , n6105 , n6106 , n6107 , n6108 , n6109 , n6110 ,
n6111 , n6112 , n6113 , n6114 , n6115 , n6116 , n6117 , n6118 , n6119 , n6120 ,
n6121 , n6122 , n6123 , n6124 , n6125 , n6126 , n6127 , n6128 , n6129 , n6130 ,
n6131 , n6132 , n6133 , n6134 , n6135 , n6136 , n6137 , n6138 , n6139 , n6140 ,
n6141 , n6142 , n6143 , n6144 , n6145 , n6146 , n6147 , n6148 , n6149 , n6150 ,
n6151 , n6152 , n6153 , n6154 , n6155 , n6156 , n6157 , n6158 , n6159 , n6160 ,
n6161 , n6162 , n6163 , n6164 , n6165 , n6166 , n6167 , n6168 , n6169 , n6170 ,
n6171 , n6172 , n6173 , n6174 , n6175 , n6176 , n6177 , n6178 , n6179 , n6180 ,
n6181 , n6182 , n6183 , n6184 , n6185 , n6186 , n6187 , n6188 , n6189 , n6190 ,
n6191 , n6192 , n6193 , n6194 , n6195 , n6196 , n6197 , n6198 , n6199 , n6200 ,
n6201 , n6202 , n6203 , n6204 , n6205 , n6206 , n6207 , n6208 , n6209 , n6210 ,
n6211 , n6212 , n6213 , n6214 , n6215 , n6216 , n6217 , n6218 , n6219 , n6220 ,
n6221 , n6222 , n6223 , n6224 , n6225 , n6226 , n6227 , n6228 , n6229 , n6230 ,
n6231 , n6232 , n6233 , n6234 , n6235 , n6236 , n6237 , n6238 , n6239 , n6240 ,
n6241 , n6242 , n6243 , n6244 , n6245 , n6246 , n6247 , n6248 , n6249 , n6250 ,
n6251 , n6252 , n6253 , n6254 , n6255 , n6256 , n6257 , n6258 , n6259 , n6260 ,
n6261 , n6262 , n6263 , n6264 , n6265 , n6266 , n6267 , n6268 , n6269 , n6270 ,
n6271 , n6272 , n6273 , n6274 , n6275 , n6276 , n6277 , n6278 , n6279 , n6280 ,
n6281 , n6282 , n6283 , n6284 , n6285 , n6286 , n6287 , n6288 , n6289 , n6290 ,
n6291 , n6292 , n6293 , n6294 , n6295 , n6296 , n6297 , n6298 , n6299 , n6300 ,
n6301 , n6302 , n6303 , n6304 , n6305 , n6306 , n6307 , n6308 , n6309 , n6310 ,
n6311 , n6312 , n6313 , n6314 , n6315 , n6316 , n6317 , n6318 , n6319 , n6320 ,
n6321 , n6322 , n6323 , n6324 , n6325 , n6326 , n6327 , n6328 , n6329 , n6330 ,
n6331 , n6332 , n6333 , n6334 , n6335 , n6336 , n6337 , n6338 , n6339 , n6340 ,
n6341 , n6342 , n6343 , n6344 , n6345 , n6346 , n6347 , n6348 , n6349 , n6350 ,
n6351 , n6352 , n6353 , n6354 , n6355 , n6356 , n6357 , n6358 , n6359 , n6360 ,
n6361 , n6362 , n6363 , n6364 , n6365 , n6366 , n6367 , n6368 , n6369 , n6370 ,
n6371 , n6372 , n6373 , n6374 , n6375 , n6376 , n6377 , n6378 , n6379 , n6380 ,
n6381 , n6382 , n6383 , n6384 , n6385 , n6386 , n6387 , n6388 , n6389 , n6390 ,
n6391 , n6392 , n6393 , n6394 , n6395 , n6396 , n6397 , n6398 , n6399 , n6400 ,
n6401 , n6402 , n6403 , n6404 , n6405 , n6406 , n6407 , n6408 , n6409 , n6410 ,
n6411 , n6412 , n6413 , n6414 , n6415 , n6416 , n6417 , n6418 , n6419 , n6420 ,
n6421 , n6422 , n6423 , n6424 , n6425 , n6426 , n6427 , n6428 , n6429 , n6430 ,
n6431 , n6432 , n6433 , n6434 , n6435 , n6436 , n6437 , n6438 , n6439 , n6440 ,
n6441 , n6442 , n6443 , n6444 , n6445 , n6446 , n6447 , n6448 , n6449 , n6450 ,
n6451 , n6452 , n6453 , n6454 , n6455 , n6456 , n6457 , n6458 , n6459 , n6460 ,
n6461 , n6462 , n6463 , n6464 , n6465 , n6466 , n6467 , n6468 , n6469 , n6470 ,
n6471 , n6472 , n6473 , n6474 , n6475 , n6476 , n6477 , n6478 , n6479 , n6480 ,
n6481 , n6482 , n6483 , n6484 , n6485 , n6486 , n6487 , n6488 , n6489 , n6490 ,
n6491 , n6492 , n6493 , n6494 , n6495 , n6496 , n6497 , n6498 , n6499 , n6500 ,
n6501 , n6502 , n6503 , n6504 , n6505 , n6506 , n6507 , n6508 , n6509 , n6510 ,
n6511 , n6512 , n6513 , n6514 , n6515 , n6516 , n6517 , n6518 , n6519 , n6520 ,
n6521 , n6522 , n6523 , n6524 , n6525 , n6526 , n6527 , n6528 , n6529 , n6530 ,
n6531 , n6532 , n6533 , n6534 , n6535 , n6536 , n6537 , n6538 , n6539 , n6540 ,
n6541 , n6542 , n6543 , n6544 , n6545 , n6546 , n6547 , n6548 , n6549 , n6550 ,
n6551 , n6552 , n6553 , n6554 , n6555 , n6556 , n6557 , n6558 , n6559 , n6560 ,
n6561 , n6562 , n6563 , n6564 , n6565 , n6566 , n6567 , n6568 , n6569 , n6570 ,
n6571 , n6572 , n6573 , n6574 , n6575 , n6576 , n6577 , n6578 , n6579 , n6580 ,
n6581 , n6582 , n6583 , n6584 , n6585 , n6586 , n6587 , n6588 , n6589 , n6590 ,
n6591 , n6592 , n6593 , n6594 , n6595 , n6596 , n6597 , n6598 , n6599 , n6600 ,
n6601 , n6602 , n6603 , n6604 , n6605 , n6606 , n6607 , n6608 , n6609 , n6610 ,
n6611 , n6612 , n6613 , n6614 , n6615 , n6616 , n6617 , n6618 , n6619 , n6620 ,
n6621 , n6622 , n6623 , n6624 , n6625 , n6626 , n6627 , n6628 , n6629 , n6630 ,
n6631 , n6632 , n6633 , n6634 , n6635 , n6636 , n6637 , n6638 , n6639 , n6640 ,
n6641 , n6642 , n6643 , n6644 , n6645 , n6646 , n6647 , n6648 , n6649 , n6650 ,
n6651 , n6652 , n6653 , n6654 , n6655 , n6656 , n6657 , n6658 , n6659 , n6660 ,
n6661 , n6662 , n6663 , n6664 , n6665 , n6666 , n6667 , n6668 , n6669 , n6670 ,
n6671 , n6672 , n6673 , n6674 , n6675 , n6676 , n6677 , n6678 , n6679 , n6680 ,
n6681 , n6682 , n6683 , n6684 , n6685 , n6686 , n6687 , n6688 , n6689 , n6690 ,
n6691 , n6692 , n6693 , n6694 , n6695 , n6696 , n6697 , n6698 , n6699 , n6700 ,
n6701 , n6702 , n6703 , n6704 , n6705 , n6706 , n6707 , n6708 , n6709 , n6710 ,
n6711 , n6712 , n6713 , n6714 , n6715 , n6716 , n6717 , n6718 , n6719 , n6720 ,
n6721 , n6722 , n6723 , n6724 , n6725 , n6726 , n6727 , n6728 , n6729 , n6730 ,
n6731 , n6732 , n6733 , n6734 , n6735 , n6736 , n6737 , n6738 , n6739 , n6740 ,
n6741 , n6742 , n6743 , n6744 , n6745 , n6746 , n6747 , n6748 , n6749 , n6750 ,
n6751 , n6752 , n6753 , n6754 , n6755 , n6756 , n6757 , n6758 , n6759 , n6760 ,
n6761 , n6762 , n6763 , n6764 , n6765 , n6766 , n6767 , n6768 , n6769 , n6770 ,
n6771 , n6772 , n6773 , n6774 , n6775 , n6776 , n6777 , n6778 , n6779 , n6780 ,
n6781 , n6782 , n6783 , n6784 , n6785 , n6786 , n6787 , n6788 , n6789 , n6790 ,
n6791 , n6792 , n6793 , n6794 , n6795 , n6796 , n6797 , n6798 , n6799 , n6800 ,
n6801 , n6802 , n6803 , n6804 , n6805 , n6806 , n6807 , n6808 , n6809 , n6810 ,
n6811 , n6812 , n6813 , n6814 , n6815 , n6816 , n6817 , n6818 , n6819 , n6820 ,
n6821 , n6822 , n6823 , n6824 , n6825 , n6826 , n6827 , n6828 , n6829 , n6830 ,
n6831 , n6832 , n6833 , n6834 , n6835 , n6836 , n6837 , n6838 , n6839 , n6840 ,
n6841 , n6842 , n6843 , n6844 , n6845 , n6846 , n6847 , n6848 , n6849 , n6850 ,
n6851 , n6852 , n6853 , n6854 , n6855 , n6856 , n6857 , n6858 , n6859 , n6860 ,
n6861 , n6862 , n6863 , n6864 , n6865 , n6866 , n6867 , n6868 , n6869 , n6870 ,
n6871 , n6872 , n6873 , n6874 , n6875 , n6876 , n6877 , n6878 , n6879 , n6880 ,
n6881 , n6882 , n6883 , n6884 , n6885 , n6886 , n6887 , n6888 , n6889 , n6890 ,
n6891 , n6892 , n6893 , n6894 , n6895 , n6896 , n6897 , n6898 , n6899 , n6900 ,
n6901 , n6902 , n6903 , n6904 , n6905 , n6906 , n6907 , n6908 , n6909 , n6910 ,
n6911 , n6912 , n6913 , n6914 , n6915 , n6916 , n6917 , n6918 , n6919 , n6920 ,
n6921 , n6922 , n6923 , n6924 , n6925 , n6926 , n6927 , n6928 , n6929 , n6930 ,
n6931 , n6932 , n6933 , n6934 , n6935 , n6936 , n6937 , n6938 , n6939 , n6940 ,
n6941 , n6942 , n6943 , n6944 , n6945 , n6946 , n6947 , n6948 , n6949 , n6950 ,
n6951 , n6952 , n6953 , n6954 , n6955 , n6956 , n6957 , n6958 , n6959 , n6960 ,
n6961 , n6962 , n6963 , n6964 , n6965 , n6966 , n6967 , n6968 , n6969 , n6970 ,
n6971 , n6972 , n6973 , n6974 , n6975 , n6976 , n6977 , n6978 , n6979 , n6980 ,
n6981 , n6982 , n6983 , n6984 , n6985 , n6986 , n6987 , n6988 , n6989 , n6990 ,
n6991 , n6992 , n6993 , n6994 , n6995 , n6996 , n6997 , n6998 , n6999 , n7000 ,
n7001 , n7002 , n7003 , n7004 , n7005 , n7006 , n7007 , n7008 , n7009 , n7010 ,
n7011 , n7012 , n7013 , n7014 , n7015 , n7016 , n7017 , n7018 , n7019 , n7020 ,
n7021 , n7022 , n7023 , n7024 , n7025 , n7026 , n7027 , n7028 , n7029 , n7030 ,
n7031 , n7032 , n7033 , n7034 , n7035 , n7036 , n7037 , n7038 , n7039 , n7040 ,
n7041 , n7042 , n7043 , n7044 , n7045 , n7046 , n7047 , n7048 , n7049 , n7050 ,
n7051 , n7052 , n7053 , n7054 , n7055 , n7056 , n7057 , n7058 , n7059 , n7060 ,
n7061 , n7062 , n7063 , n7064 , n7065 , n7066 , n7067 , n7068 , n7069 , n7070 ,
n7071 , n7072 , n7073 , n7074 , n7075 , n7076 , n7077 , n7078 , n7079 , n7080 ,
n7081 , n7082 , n7083 , n7084 , n7085 , n7086 , n7087 , n7088 , n7089 , n7090 ,
n7091 , n7092 , n7093 , n7094 , n7095 , n7096 , n7097 , n7098 , n7099 , n7100 ,
n7101 , n7102 , n7103 , n7104 , n7105 , n7106 , n7107 , n7108 , n7109 , n7110 ,
n7111 , n7112 , n7113 , n7114 , n7115 , n7116 , n7117 , n7118 , n7119 , n7120 ,
n7121 , n7122 , n7123 , n7124 , n7125 , n7126 , n7127 , n7128 , n7129 , n7130 ,
n7131 , n7132 , n7133 , n7134 , n7135 , n7136 , n7137 , n7138 , n7139 , n7140 ,
n7141 , n7142 , n7143 , n7144 , n7145 , n7146 , n7147 , n7148 , n7149 , n7150 ,
n7151 , n7152 , n7153 , n7154 , n7155 , n7156 , n7157 , n7158 , n7159 , n7160 ,
n7161 , n7162 , n7163 , n7164 , n7165 , n7166 , n7167 , n7168 , n7169 , n7170 ,
n7171 , n7172 , n7173 , n7174 , n7175 , n7176 , n7177 , n7178 , n7179 , n7180 ,
n7181 , n7182 , n7183 , n7184 , n7185 , n7186 , n7187 , n7188 , n7189 , n7190 ,
n7191 , n7192 , n7193 , n7194 , n7195 , n7196 , n7197 , n7198 , n7199 , n7200 ,
n7201 , n7202 , n7203 , n7204 , n7205 , n7206 , n7207 , n7208 , n7209 , n7210 ,
n7211 , n7212 , n7213 , n7214 , n7215 , n7216 , n7217 , n7218 , n7219 , n7220 ,
n7221 , n7222 , n7223 , n7224 , n7225 , n7226 , n7227 , n7228 , n7229 , n7230 ,
n7231 , n7232 , n7233 , n7234 , n7235 , n7236 , n7237 , n7238 , n7239 , n7240 ,
n7241 , n7242 , n7243 , n7244 , n7245 , n7246 , n7247 , n7248 , n7249 , n7250 ,
n7251 , n7252 , n7253 , n7254 , n7255 , n7256 , n7257 , n7258 , n7259 , n7260 ,
n7261 , n7262 , n7263 , n7264 , n7265 , n7266 , n7267 , n7268 , n7269 , n7270 ,
n7271 , n7272 , n7273 , n7274 , n7275 , n7276 , n7277 , n7278 , n7279 , n7280 ,
n7281 , n7282 , n7283 , n7284 , n7285 , n7286 , n7287 , n7288 , n7289 , n7290 ,
n7291 , n7292 , n7293 , n7294 , n7295 , n7296 , n7297 , n7298 , n7299 , n7300 ,
n7301 , n7302 , n7303 , n7304 , n7305 , n7306 , n7307 , n7308 , n7309 , n7310 ,
n7311 , n7312 , n7313 , n7314 , n7315 , n7316 , n7317 , n7318 , n7319 , n7320 ,
n7321 , n7322 , n7323 , n7324 , n7325 , n7326 , n7327 , n7328 , n7329 , n7330 ,
n7331 , n7332 , n7333 , n7334 , n7335 , n7336 , n7337 , n7338 , n7339 , n7340 ,
n7341 , n7342 , n7343 , n7344 , n7345 , n7346 , n7347 , n7348 , n7349 , n7350 ,
n7351 , n7352 , n7353 , n7354 , n7355 , n7356 , n7357 , n7358 , n7359 , n7360 ,
n7361 , n7362 , n7363 , n7364 , n7365 , n7366 , n7367 , n7368 , n7369 , n7370 ,
n7371 , n7372 , n7373 , n7374 , n7375 , n7376 , n7377 , n7378 , n7379 , n7380 ,
n7381 , n7382 , n7383 , n7384 , n7385 , n7386 , n7387 , n7388 , n7389 , n7390 ,
n7391 , n7392 , n7393 , n7394 , n7395 , n7396 , n7397 , n7398 , n7399 , n7400 ,
n7401 , n7402 , n7403 , n7404 , n7405 , n7406 , n7407 , n7408 , n7409 , n7410 ,
n7411 , n7412 , n7413 , n7414 , n7415 , n7416 , n7417 , n7418 , n7419 , n7420 ,
n7421 , n7422 , n7423 , n7424 , n7425 , n7426 , n7427 , n7428 , n7429 , n7430 ,
n7431 , n7432 , n7433 , n7434 , n7435 , n7436 , n7437 , n7438 , n7439 , n7440 ,
n7441 , n7442 , n7443 , n7444 , n7445 , n7446 , n7447 , n7448 , n7449 , n7450 ,
n7451 , n7452 , n7453 , n7454 , n7455 , n7456 , n7457 , n7458 , n7459 , n7460 ,
n7461 , n7462 , n7463 , n7464 , n7465 , n7466 , n7467 , n7468 , n7469 , n7470 ,
n7471 , n7472 , n7473 , n7474 , n7475 , n7476 , n7477 , n7478 , n7479 , n7480 ,
n7481 , n7482 , n7483 , n7484 , n7485 , n7486 , n7487 , n7488 , n7489 , n7490 ,
n7491 , n7492 , n7493 , n7494 , n7495 , n7496 , n7497 , n7498 , n7499 , n7500 ,
n7501 , n7502 , n7503 , n7504 , n7505 , n7506 , n7507 , n7508 , n7509 , n7510 ,
n7511 , n7512 , n7513 , n7514 , n7515 , n7516 , n7517 , n7518 , n7519 , n7520 ,
n7521 , n7522 , n7523 , n7524 , n7525 , n7526 , n7527 , n7528 , n7529 , n7530 ,
n7531 , n7532 , n7533 , n7534 , n7535 , n7536 , n7537 , n7538 , n7539 , n7540 ,
n7541 , n7542 , n7543 , n7544 , n7545 , n7546 , n7547 , n7548 , n7549 , n7550 ,
n7551 , n7552 , n7553 , n7554 , n7555 , n7556 , n7557 , n7558 , n7559 , n7560 ,
n7561 , n7562 , n7563 , n7564 , n7565 , n7566 , n7567 , n7568 , n7569 , n7570 ,
n7571 , n7572 , n7573 , n7574 , n7575 , n7576 , n7577 , n7578 , n7579 , n7580 ,
n7581 , n7582 , n7583 , n7584 , n7585 , n7586 , n7587 , n7588 , n7589 , n7590 ,
n7591 , n7592 , n7593 , n7594 , n7595 , n7596 , n7597 , n7598 , n7599 , n7600 ,
n7601 , n7602 , n7603 , n7604 , n7605 , n7606 , n7607 , n7608 , n7609 , n7610 ,
n7611 , n7612 , n7613 , n7614 , n7615 , n7616 , n7617 , n7618 , n7619 , n7620 ,
n7621 , n7622 , n7623 , n7624 , n7625 , n7626 , n7627 , n7628 , n7629 , n7630 ,
n7631 , n7632 , n7633 , n7634 , n7635 , n7636 , n7637 , n7638 , n7639 , n7640 ,
n7641 , n7642 , n7643 , n7644 , n7645 , n7646 , n7647 , n7648 , n7649 , n7650 ,
n7651 , n7652 , n7653 , n7654 , n7655 , n7656 , n7657 , n7658 , n7659 , n7660 ,
n7661 , n7662 , n7663 , n7664 , n7665 , n7666 , n7667 , n7668 , n7669 , n7670 ,
n7671 , n7672 , n7673 , n7674 , n7675 , n7676 , n7677 , n7678 , n7679 , n7680 ,
n7681 , n7682 , n7683 , n7684 , n7685 , n7686 , n7687 , n7688 , n7689 , n7690 ,
n7691 , n7692 , n7693 , n7694 , n7695 , n7696 , n7697 , n7698 , n7699 , n7700 ,
n7701 , n7702 , n7703 , n7704 , n7705 , n7706 , n7707 , n7708 , n7709 , n7710 ,
n7711 , n7712 , n7713 , n7714 , n7715 , n7716 , n7717 , n7718 , n7719 , n7720 ,
n7721 , n7722 , n7723 , n7724 , n7725 , n7726 , n7727 , n7728 , n7729 , n7730 ,
n7731 , n7732 , n7733 , n7734 , n7735 , n7736 , n7737 , n7738 , n7739 , n7740 ,
n7741 , n7742 , n7743 , n7744 , n7745 , n7746 , n7747 , n7748 , n7749 , n7750 ,
n7751 , n7752 , n7753 , n7754 , n7755 , n7756 , n7757 , n7758 , n7759 , n7760 ,
n7761 , n7762 , n7763 , n7764 , n7765 , n7766 , n7767 , n7768 , n7769 , n7770 ,
n7771 , n7772 , n7773 , n7774 , n7775 , n7776 , n7777 , n7778 , n7779 , n7780 ,
n7781 , n7782 , n7783 , n7784 , n7785 , n7786 , n7787 , n7788 , n7789 , n7790 ,
n7791 , n7792 , n7793 , n7794 , n7795 , n7796 , n7797 , n7798 , n7799 , n7800 ,
n7801 , n7802 , n7803 , n7804 , n7805 , n7806 , n7807 , n7808 , n7809 , n7810 ,
n7811 , n7812 , n7813 , n7814 , n7815 , n7816 , n7817 , n7818 , n7819 , n7820 ,
n7821 , n7822 , n7823 , n7824 , n7825 , n7826 , n7827 , n7828 , n7829 , n7830 ,
n7831 , n7832 , n7833 , n7834 , n7835 , n7836 , n7837 , n7838 , n7839 , n7840 ,
n7841 , n7842 , n7843 , n7844 , n7845 , n7846 , n7847 , n7848 , n7849 , n7850 ,
n7851 , n7852 , n7853 , n7854 , n7855 , n7856 , n7857 , n7858 , n7859 , n7860 ,
n7861 , n7862 , n7863 , n7864 , n7865 , n7866 , n7867 , n7868 , n7869 , n7870 ,
n7871 , n7872 , n7873 , n7874 , n7875 , n7876 , n7877 , n7878 , n7879 , n7880 ,
n7881 , n7882 , n7883 , n7884 , n7885 , n7886 , n7887 , n7888 , n7889 , n7890 ,
n7891 , n7892 , n7893 , n7894 , n7895 , n7896 , n7897 , n7898 , n7899 , n7900 ,
n7901 , n7902 , n7903 , n7904 , n7905 , n7906 , n7907 , n7908 , n7909 , n7910 ,
n7911 , n7912 , n7913 , n7914 , n7915 , n7916 , n7917 , n7918 , n7919 , n7920 ,
n7921 , n7922 , n7923 , n7924 , n7925 , n7926 , n7927 , n7928 , n7929 , n7930 ,
n7931 , n7932 , n7933 , n7934 , n7935 , n7936 , n7937 , n7938 , n7939 , n7940 ,
n7941 , n7942 , n7943 , n7944 , n7945 , n7946 , n7947 , n7948 , n7949 , n7950 ,
n7951 , n7952 , n7953 , n7954 , n7955 , n7956 , n7957 , n7958 , n7959 , n7960 ,
n7961 , n7962 , n7963 , n7964 , n7965 , n7966 , n7967 , n7968 , n7969 , n7970 ,
n7971 , n7972 , n7973 , n7974 , n7975 , n7976 , n7977 , n7978 , n7979 , n7980 ,
n7981 , n7982 , n7983 , n7984 , n7985 , n7986 , n7987 , n7988 , n7989 , n7990 ,
n7991 , n7992 , n7993 , n7994 , n7995 , n7996 , n7997 , n7998 , n7999 , n8000 ,
n8001 , n8002 , n8003 , n8004 , n8005 , n8006 , n8007 , n8008 , n8009 , n8010 ,
n8011 , n8012 , n8013 , n8014 , n8015 , n8016 , n8017 , n8018 , n8019 , n8020 ,
n8021 , n8022 , n8023 , n8024 , n8025 , n8026 , n8027 , n8028 , n8029 , n8030 ,
n8031 , n8032 , n8033 , n8034 , n8035 , n8036 , n8037 , n8038 , n8039 , n8040 ,
n8041 , n8042 , n8043 , n8044 , n8045 , n8046 , n8047 , n8048 , n8049 , n8050 ,
n8051 , n8052 , n8053 , n8054 , n8055 , n8056 , n8057 , n8058 , n8059 , n8060 ,
n8061 , n8062 , n8063 , n8064 , n8065 , n8066 , n8067 , n8068 , n8069 , n8070 ,
n8071 , n8072 , n8073 , n8074 , n8075 , n8076 , n8077 , n8078 , n8079 , n8080 ,
n8081 , n8082 , n8083 , n8084 , n8085 , n8086 , n8087 , n8088 , n8089 , n8090 ,
n8091 , n8092 , n8093 , n8094 , n8095 , n8096 , n8097 , n8098 , n8099 , n8100 ,
n8101 , n8102 , n8103 , n8104 , n8105 , n8106 , n8107 , n8108 , n8109 , n8110 ,
n8111 , n8112 , n8113 , n8114 , n8115 , n8116 , n8117 , n8118 , n8119 , n8120 ,
n8121 , n8122 , n8123 , n8124 , n8125 , n8126 , n8127 , n8128 , n8129 , n8130 ,
n8131 , n8132 , n8133 , n8134 , n8135 , n8136 , n8137 , n8138 , n8139 , n8140 ,
n8141 , n8142 , n8143 , n8144 , n8145 , n8146 , n8147 , n8148 , n8149 , n8150 ,
n8151 , n8152 , n8153 , n8154 , n8155 , n8156 , n8157 , n8158 , n8159 , n8160 ,
n8161 , n8162 , n8163 , n8164 , n8165 , n8166 , n8167 , n8168 , n8169 , n8170 ,
n8171 , n8172 , n8173 , n8174 , n8175 , n8176 , n8177 , n8178 , n8179 , n8180 ,
n8181 , n8182 , n8183 , n8184 , n8185 , n8186 , n8187 , n8188 , n8189 , n8190 ,
n8191 , n8192 , n8193 , n8194 , n8195 , n8196 , n8197 , n8198 , n8199 , n8200 ,
n8201 , n8202 , n8203 , n8204 , n8205 , n8206 , n8207 , n8208 , n8209 , n8210 ,
n8211 , n8212 , n8213 , n8214 , n8215 , n8216 , n8217 , n8218 , n8219 , n8220 ,
n8221 , n8222 , n8223 , n8224 , n8225 , n8226 , n8227 , n8228 , n8229 , n8230 ,
n8231 , n8232 , n8233 , n8234 , n8235 , n8236 , n8237 , n8238 , n8239 , n8240 ,
n8241 , n8242 , n8243 , n8244 , n8245 , n8246 , n8247 , n8248 , n8249 , n8250 ,
n8251 , n8252 , n8253 , n8254 , n8255 , n8256 , n8257 , n8258 , n8259 , n8260 ,
n8261 , n8262 , n8263 , n8264 , n8265 , n8266 , n8267 , n8268 , n8269 , n8270 ,
n8271 , n8272 , n8273 , n8274 , n8275 , n8276 , n8277 , n8278 , n8279 , n8280 ,
n8281 , n8282 , n8283 , n8284 , n8285 , n8286 , n8287 , n8288 , n8289 , n8290 ,
n8291 , n8292 , n8293 , n8294 , n8295 , n8296 , n8297 , n8298 , n8299 , n8300 ,
n8301 , n8302 , n8303 , n8304 , n8305 , n8306 , n8307 , n8308 , n8309 , n8310 ,
n8311 , n8312 , n8313 , n8314 , n8315 , n8316 , n8317 , n8318 , n8319 , n8320 ,
n8321 , n8322 , n8323 , n8324 , n8325 , n8326 , n8327 , n8328 , n8329 , n8330 ,
n8331 , n8332 , n8333 , n8334 , n8335 , n8336 , n8337 , n8338 , n8339 , n8340 ,
n8341 , n8342 , n8343 , n8344 , n8345 , n8346 , n8347 , n8348 , n8349 , n8350 ,
n8351 , n8352 , n8353 , n8354 , n8355 , n8356 , n8357 , n8358 , n8359 , n8360 ,
n8361 , n8362 , n8363 , n8364 , n8365 , n8366 , n8367 , n8368 , n8369 , n8370 ,
n8371 , n8372 , n8373 , n8374 , n8375 , n8376 , n8377 , n8378 , n8379 , n8380 ,
n8381 , n8382 , n8383 , n8384 , n8385 , n8386 , n8387 , n8388 , n8389 , n8390 ,
n8391 , n8392 , n8393 , n8394 , n8395 , n8396 , n8397 , n8398 , n8399 , n8400 ,
n8401 , n8402 , n8403 , n8404 , n8405 , n8406 , n8407 , n8408 , n8409 , n8410 ,
n8411 , n8412 , n8413 , n8414 , n8415 , n8416 , n8417 , n8418 , n8419 , n8420 ,
n8421 , n8422 , n8423 , n8424 , n8425 , n8426 , n8427 , n8428 , n8429 , n8430 ,
n8431 , n8432 , n8433 , n8434 , n8435 , n8436 , n8437 , n8438 , n8439 , n8440 ,
n8441 , n8442 , n8443 , n8444 , n8445 , n8446 , n8447 , n8448 , n8449 , n8450 ,
n8451 , n8452 , n8453 , n8454 , n8455 , n8456 , n8457 , n8458 , n8459 , n8460 ,
n8461 , n8462 , n8463 , n8464 , n8465 , n8466 , n8467 , n8468 , n8469 , n8470 ,
n8471 , n8472 , n8473 , n8474 , n8475 , n8476 , n8477 , n8478 , n8479 , n8480 ,
n8481 , n8482 , n8483 , n8484 , n8485 , n8486 , n8487 , n8488 , n8489 , n8490 ,
n8491 , n8492 , n8493 , n8494 , n8495 , n8496 , n8497 , n8498 , n8499 , n8500 ,
n8501 , n8502 , n8503 , n8504 , n8505 , n8506 , n8507 , n8508 , n8509 , n8510 ,
n8511 , n8512 , n8513 , n8514 , n8515 , n8516 , n8517 , n8518 , n8519 , n8520 ,
n8521 , n8522 , n8523 , n8524 , n8525 , n8526 , n8527 , n8528 , n8529 , n8530 ,
n8531 , n8532 , n8533 , n8534 , n8535 , n8536 , n8537 , n8538 , n8539 , n8540 ,
n8541 , n8542 , n8543 , n8544 , n8545 , n8546 , n8547 , n8548 , n8549 , n8550 ,
n8551 , n8552 , n8553 , n8554 , n8555 , n8556 , n8557 , n8558 , n8559 , n8560 ,
n8561 , n8562 , n8563 , n8564 , n8565 , n8566 , n8567 , n8568 , n8569 , n8570 ,
n8571 , n8572 , n8573 , n8574 , n8575 , n8576 , n8577 , n8578 , n8579 , n8580 ,
n8581 , n8582 , n8583 , n8584 , n8585 , n8586 , n8587 , n8588 , n8589 , n8590 ,
n8591 , n8592 , n8593 , n8594 , n8595 , n8596 , n8597 , n8598 , n8599 , n8600 ,
n8601 , n8602 , n8603 , n8604 , n8605 , n8606 , n8607 , n8608 , n8609 , n8610 ,
n8611 , n8612 , n8613 , n8614 , n8615 , n8616 , n8617 , n8618 , n8619 , n8620 ,
n8621 , n8622 , n8623 , n8624 , n8625 , n8626 , n8627 , n8628 , n8629 , n8630 ,
n8631 , n8632 , n8633 , n8634 , n8635 , n8636 , n8637 , n8638 , n8639 , n8640 ,
n8641 , n8642 , n8643 , n8644 , n8645 , n8646 , n8647 , n8648 , n8649 , n8650 ,
n8651 , n8652 , n8653 , n8654 , n8655 , n8656 , n8657 , n8658 , n8659 , n8660 ,
n8661 , n8662 , n8663 , n8664 , n8665 , n8666 , n8667 , n8668 , n8669 , n8670 ,
n8671 , n8672 , n8673 , n8674 , n8675 , n8676 , n8677 , n8678 , n8679 , n8680 ,
n8681 , n8682 , n8683 , n8684 , n8685 , n8686 , n8687 , n8688 , n8689 , n8690 ,
n8691 , n8692 , n8693 , n8694 , n8695 , n8696 , n8697 , n8698 , n8699 , n8700 ,
n8701 , n8702 , n8703 , n8704 , n8705 , n8706 , n8707 , n8708 , n8709 , n8710 ,
n8711 , n8712 , n8713 , n8714 , n8715 , n8716 , n8717 , n8718 , n8719 , n8720 ,
n8721 , n8722 , n8723 , n8724 , n8725 , n8726 , n8727 , n8728 , n8729 , n8730 ,
n8731 , n8732 , n8733 , n8734 , n8735 , n8736 , n8737 , n8738 , n8739 , n8740 ,
n8741 , n8742 , n8743 , n8744 , n8745 , n8746 , n8747 , n8748 , n8749 , n8750 ,
n8751 , n8752 , n8753 , n8754 , n8755 , n8756 , n8757 , n8758 , n8759 , n8760 ,
n8761 , n8762 , n8763 , n8764 , n8765 , n8766 , n8767 , n8768 , n8769 , n8770 ,
n8771 , n8772 , n8773 , n8774 , n8775 , n8776 , n8777 , n8778 , n8779 , n8780 ,
n8781 , n8782 , n8783 , n8784 , n8785 , n8786 , n8787 , n8788 , n8789 , n8790 ,
n8791 , n8792 , n8793 , n8794 , n8795 , n8796 , n8797 , n8798 , n8799 , n8800 ,
n8801 , n8802 , n8803 , n8804 , n8805 , n8806 , n8807 , n8808 , n8809 , n8810 ,
n8811 , n8812 , n8813 , n8814 , n8815 , n8816 , n8817 , n8818 , n8819 , n8820 ,
n8821 , n8822 , n8823 , n8824 , n8825 , n8826 , n8827 , n8828 , n8829 , n8830 ,
n8831 , n8832 , n8833 , n8834 , n8835 , n8836 , n8837 , n8838 , n8839 , n8840 ,
n8841 , n8842 , n8843 , n8844 , n8845 , n8846 , n8847 , n8848 , n8849 , n8850 ,
n8851 , n8852 , n8853 , n8854 , n8855 , n8856 , n8857 , n8858 , n8859 , n8860 ,
n8861 , n8862 , n8863 , n8864 , n8865 , n8866 , n8867 , n8868 , n8869 , n8870 ,
n8871 , n8872 , n8873 , n8874 , n8875 , n8876 , n8877 , n8878 , n8879 , n8880 ,
n8881 , n8882 , n8883 , n8884 , n8885 , n8886 , n8887 , n8888 , n8889 , n8890 ,
n8891 , n8892 , n8893 , n8894 , n8895 , n8896 , n8897 , n8898 , n8899 , n8900 ,
n8901 , n8902 , n8903 , n8904 , n8905 , n8906 , n8907 , n8908 , n8909 , n8910 ,
n8911 , n8912 , n8913 , n8914 , n8915 , n8916 , n8917 , n8918 , n8919 , n8920 ,
n8921 , n8922 , n8923 , n8924 , n8925 , n8926 , n8927 , n8928 , n8929 , n8930 ,
n8931 , n8932 , n8933 , n8934 , n8935 , n8936 , n8937 , n8938 , n8939 , n8940 ,
n8941 , n8942 , n8943 , n8944 , n8945 , n8946 , n8947 , n8948 , n8949 , n8950 ,
n8951 , n8952 , n8953 , n8954 , n8955 , n8956 , n8957 , n8958 , n8959 , n8960 ,
n8961 , n8962 , n8963 , n8964 , n8965 , n8966 , n8967 , n8968 , n8969 , n8970 ,
n8971 , n8972 , n8973 , n8974 , n8975 , n8976 , n8977 , n8978 , n8979 , n8980 ,
n8981 , n8982 , n8983 , n8984 , n8985 , n8986 , n8987 , n8988 , n8989 , n8990 ,
n8991 , n8992 , n8993 , n8994 , n8995 , n8996 , n8997 , n8998 , n8999 , n9000 ,
n9001 , n9002 , n9003 , n9004 , n9005 , n9006 , n9007 , n9008 , n9009 , n9010 ,
n9011 , n9012 , n9013 , n9014 , n9015 , n9016 , n9017 , n9018 , n9019 , n9020 ,
n9021 , n9022 , n9023 , n9024 , n9025 , n9026 , n9027 , n9028 , n9029 , n9030 ,
n9031 , n9032 , n9033 , n9034 , n9035 , n9036 , n9037 , n9038 , n9039 , n9040 ,
n9041 , n9042 , n9043 , n9044 , n9045 , n9046 , n9047 , n9048 , n9049 , n9050 ,
n9051 , n9052 , n9053 , n9054 , n9055 , n9056 , n9057 , n9058 , n9059 , n9060 ,
n9061 , n9062 , n9063 , n9064 , n9065 , n9066 , n9067 , n9068 , n9069 , n9070 ,
n9071 , n9072 , n9073 , n9074 , n9075 , n9076 , n9077 , n9078 , n9079 , n9080 ,
n9081 , n9082 , n9083 , n9084 , n9085 , n9086 , n9087 , n9088 , n9089 , n9090 ,
n9091 , n9092 , n9093 , n9094 , n9095 , n9096 , n9097 , n9098 , n9099 , n9100 ,
n9101 , n9102 , n9103 , n9104 , n9105 , n9106 , n9107 , n9108 , n9109 , n9110 ,
n9111 , n9112 , n9113 , n9114 , n9115 , n9116 , n9117 , n9118 , n9119 , n9120 ,
n9121 , n9122 , n9123 , n9124 , n9125 , n9126 , n9127 , n9128 , n9129 , n9130 ,
n9131 , n9132 , n9133 , n9134 , n9135 , n9136 , n9137 , n9138 , n9139 , n9140 ,
n9141 , n9142 , n9143 , n9144 , n9145 , n9146 , n9147 , n9148 , n9149 , n9150 ,
n9151 , n9152 , n9153 , n9154 , n9155 , n9156 , n9157 , n9158 , n9159 , n9160 ,
n9161 , n9162 , n9163 , n9164 , n9165 , n9166 , n9167 , n9168 , n9169 , n9170 ,
n9171 , n9172 , n9173 , n9174 , n9175 , n9176 , n9177 , n9178 , n9179 , n9180 ,
n9181 , n9182 , n9183 , n9184 , n9185 , n9186 , n9187 , n9188 , n9189 , n9190 ,
n9191 , n9192 , n9193 , n9194 , n9195 , n9196 , n9197 , n9198 , n9199 , n9200 ,
n9201 , n9202 , n9203 , n9204 , n9205 , n9206 , n9207 , n9208 , n9209 , n9210 ,
n9211 , n9212 , n9213 , n9214 , n9215 , n9216 , n9217 , n9218 , n9219 , n9220 ,
n9221 , n9222 , n9223 , n9224 , n9225 , n9226 , n9227 , n9228 , n9229 , n9230 ,
n9231 , n9232 , n9233 , n9234 , n9235 , n9236 , n9237 , n9238 , n9239 , n9240 ,
n9241 , n9242 , n9243 , n9244 , n9245 , n9246 , n9247 , n9248 , n9249 , n9250 ,
n9251 , n9252 , n9253 , n9254 , n9255 , n9256 , n9257 , n9258 , n9259 , n9260 ,
n9261 , n9262 , n9263 , n9264 , n9265 , n9266 , n9267 , n9268 , n9269 , n9270 ,
n9271 , n9272 , n9273 , n9274 , n9275 , n9276 , n9277 , n9278 , n9279 , n9280 ,
n9281 , n9282 , n9283 , n9284 , n9285 , n9286 , n9287 , n9288 , n9289 , n9290 ,
n9291 , n9292 , n9293 , n9294 , n9295 , n9296 , n9297 , n9298 , n9299 , n9300 ,
n9301 , n9302 , n9303 , n9304 , n9305 , n9306 , n9307 , n9308 , n9309 , n9310 ,
n9311 , n9312 , n9313 , n9314 , n9315 , n9316 , n9317 , n9318 , n9319 , n9320 ,
n9321 , n9322 , n9323 , n9324 , n9325 , n9326 , n9327 , n9328 , n9329 , n9330 ,
n9331 , n9332 , n9333 , n9334 , n9335 , n9336 , n9337 , n9338 , n9339 , n9340 ,
n9341 , n9342 , n9343 , n9344 , n9345 , n9346 , n9347 , n9348 , n9349 , n9350 ,
n9351 , n9352 , n9353 , n9354 , n9355 , n9356 , n9357 , n9358 , n9359 , n9360 ,
n9361 , n9362 , n9363 , n9364 , n9365 , n9366 , n9367 , n9368 , n9369 , n9370 ,
n9371 , n9372 , n9373 , n9374 , n9375 , n9376 , n9377 , n9378 , n9379 , n9380 ,
n9381 , n9382 , n9383 , n9384 , n9385 , n9386 , n9387 , n9388 , n9389 , n9390 ,
n9391 , n9392 , n9393 , n9394 , n9395 , n9396 , n9397 , n9398 , n9399 , n9400 ,
n9401 , n9402 , n9403 , n9404 , n9405 , n9406 , n9407 , n9408 , n9409 , n9410 ,
n9411 , n9412 , n9413 , n9414 , n9415 , n9416 , n9417 , n9418 , n9419 , n9420 ,
n9421 , n9422 , n9423 , n9424 , n9425 , n9426 , n9427 , n9428 , n9429 , n9430 ,
n9431 , n9432 , n9433 , n9434 , n9435 , n9436 , n9437 , n9438 , n9439 , n9440 ,
n9441 , n9442 , n9443 , n9444 , n9445 , n9446 , n9447 , n9448 , n9449 , n9450 ,
n9451 , n9452 , n9453 , n9454 , n9455 , n9456 , n9457 , n9458 , n9459 , n9460 ,
n9461 , n9462 , n9463 , n9464 , n9465 , n9466 , n9467 , n9468 , n9469 , n9470 ,
n9471 , n9472 , n9473 , n9474 , n9475 , n9476 , n9477 , n9478 , n9479 , n9480 ,
n9481 , n9482 , n9483 , n9484 , n9485 , n9486 , n9487 , n9488 , n9489 , n9490 ,
n9491 , n9492 , n9493 , n9494 , n9495 , n9496 , n9497 , n9498 , n9499 , n9500 ,
n9501 , n9502 , n9503 , n9504 , n9505 , n9506 , n9507 , n9508 , n9509 , n9510 ,
n9511 , n9512 , n9513 , n9514 , n9515 , n9516 , n9517 , n9518 , n9519 , n9520 ,
n9521 , n9522 , n9523 , n9524 , n9525 , n9526 , n9527 , n9528 , n9529 , n9530 ,
n9531 , n9532 , n9533 , n9534 , n9535 , n9536 , n9537 , n9538 , n9539 , n9540 ,
n9541 , n9542 , n9543 , n9544 , n9545 , n9546 , n9547 , n9548 , n9549 , n9550 ,
n9551 , n9552 , n9553 , n9554 , n9555 , n9556 , n9557 , n9558 , n9559 , n9560 ,
n9561 , n9562 , n9563 , n9564 , n9565 , n9566 , n9567 , n9568 , n9569 , n9570 ,
n9571 , n9572 , n9573 , n9574 , n9575 , n9576 , n9577 , n9578 , n9579 , n9580 ,
n9581 , n9582 , n9583 , n9584 , n9585 , n9586 , n9587 , n9588 , n9589 , n9590 ,
n9591 , n9592 , n9593 , n9594 , n9595 , n9596 , n9597 , n9598 , n9599 , n9600 ,
n9601 , n9602 , n9603 , n9604 , n9605 , n9606 , n9607 , n9608 , n9609 , n9610 ,
n9611 , n9612 , n9613 , n9614 , n9615 , n9616 , n9617 , n9618 , n9619 , n9620 ,
n9621 , n9622 , n9623 , n9624 , n9625 , n9626 , n9627 , n9628 , n9629 , n9630 ,
n9631 , n9632 , n9633 , n9634 , n9635 , n9636 , n9637 , n9638 , n9639 , n9640 ,
n9641 , n9642 , n9643 , n9644 , n9645 , n9646 , n9647 , n9648 , n9649 , n9650 ,
n9651 , n9652 , n9653 , n9654 , n9655 , n9656 , n9657 , n9658 , n9659 , n9660 ,
n9661 , n9662 , n9663 , n9664 , n9665 , n9666 , n9667 , n9668 , n9669 , n9670 ,
n9671 , n9672 , n9673 , n9674 , n9675 , n9676 , n9677 , n9678 , n9679 , n9680 ,
n9681 , n9682 , n9683 , n9684 , n9685 , n9686 , n9687 , n9688 , n9689 , n9690 ,
n9691 , n9692 , n9693 , n9694 , n9695 , n9696 , n9697 , n9698 , n9699 , n9700 ,
n9701 , n9702 , n9703 , n9704 , n9705 , n9706 , n9707 , n9708 , n9709 , n9710 ,
n9711 , n9712 , n9713 , n9714 , n9715 , n9716 , n9717 , n9718 , n9719 , n9720 ,
n9721 , n9722 , n9723 , n9724 , n9725 , n9726 , n9727 , n9728 , n9729 , n9730 ,
n9731 , n9732 , n9733 , n9734 , n9735 , n9736 , n9737 , n9738 , n9739 , n9740 ,
n9741 , n9742 , n9743 , n9744 , n9745 , n9746 , n9747 , n9748 , n9749 , n9750 ,
n9751 , n9752 , n9753 , n9754 , n9755 , n9756 , n9757 , n9758 , n9759 , n9760 ,
n9761 , n9762 , n9763 , n9764 , n9765 , n9766 , n9767 , n9768 , n9769 , n9770 ,
n9771 , n9772 , n9773 , n9774 , n9775 , n9776 , n9777 , n9778 , n9779 , n9780 ,
n9781 , n9782 , n9783 , n9784 , n9785 , n9786 , n9787 , n9788 , n9789 , n9790 ,
n9791 , n9792 , n9793 , n9794 , n9795 , n9796 , n9797 , n9798 , n9799 , n9800 ,
n9801 , n9802 , n9803 , n9804 , n9805 , n9806 , n9807 , n9808 , n9809 , n9810 ,
n9811 , n9812 , n9813 , n9814 , n9815 , n9816 , n9817 , n9818 , n9819 , n9820 ,
n9821 , n9822 , n9823 , n9824 , n9825 , n9826 , n9827 , n9828 , n9829 , n9830 ,
n9831 , n9832 , n9833 , n9834 , n9835 , n9836 , n9837 , n9838 , n9839 , n9840 ,
n9841 , n9842 , n9843 , n9844 , n9845 , n9846 , n9847 , n9848 , n9849 , n9850 ,
n9851 , n9852 , n9853 , n9854 , n9855 , n9856 , n9857 , n9858 , n9859 , n9860 ,
n9861 , n9862 , n9863 , n9864 , n9865 , n9866 , n9867 , n9868 , n9869 , n9870 ,
n9871 , n9872 , n9873 , n9874 , n9875 , n9876 , n9877 , n9878 , n9879 , n9880 ,
n9881 , n9882 , n9883 , n9884 , n9885 , n9886 , n9887 , n9888 , n9889 , n9890 ,
n9891 , n9892 , n9893 , n9894 , n9895 , n9896 , n9897 , n9898 , n9899 , n9900 ,
n9901 , n9902 , n9903 , n9904 , n9905 , n9906 , n9907 , n9908 , n9909 , n9910 ,
n9911 , n9912 , n9913 , n9914 , n9915 , n9916 , n9917 , n9918 , n9919 , n9920 ,
n9921 , n9922 , n9923 , n9924 , n9925 , n9926 , n9927 , n9928 , n9929 , n9930 ,
n9931 , n9932 , n9933 , n9934 , n9935 , n9936 , n9937 , n9938 , n9939 , n9940 ,
n9941 , n9942 , n9943 , n9944 , n9945 , n9946 , n9947 , n9948 , n9949 , n9950 ,
n9951 , n9952 , n9953 , n9954 , n9955 , n9956 , n9957 , n9958 , n9959 , n9960 ,
n9961 , n9962 , n9963 , n9964 , n9965 , n9966 , n9967 , n9968 , n9969 , n9970 ,
n9971 , n9972 , n9973 , n9974 , n9975 , n9976 , n9977 , n9978 , n9979 , n9980 ,
n9981 , n9982 , n9983 , n9984 , n9985 , n9986 , n9987 , n9988 , n9989 , n9990 ,
n9991 , n9992 , n9993 , n9994 , n9995 , n9996 , n9997 , n9998 , n9999 , n10000 ,
n10001 , n10002 , n10003 , n10004 , n10005 , n10006 , n10007 , n10008 , n10009 , n10010 ,
n10011 , n10012 , n10013 , n10014 , n10015 , n10016 , n10017 , n10018 , n10019 , n10020 ,
n10021 , n10022 , n10023 , n10024 , n10025 , n10026 , n10027 , n10028 , n10029 , n10030 ,
n10031 , n10032 , n10033 , n10034 , n10035 , n10036 , n10037 , n10038 , n10039 , n10040 ,
n10041 , n10042 , n10043 , n10044 , n10045 , n10046 , n10047 , n10048 , n10049 , n10050 ,
n10051 , n10052 , n10053 , n10054 , n10055 , n10056 , n10057 , n10058 , n10059 , n10060 ,
n10061 , n10062 , n10063 , n10064 , n10065 , n10066 , n10067 , n10068 , n10069 , n10070 ,
n10071 , n10072 , n10073 , n10074 , n10075 , n10076 , n10077 , n10078 , n10079 , n10080 ,
n10081 , n10082 , n10083 , n10084 , n10085 , n10086 , n10087 , n10088 , n10089 , n10090 ,
n10091 , n10092 , n10093 , n10094 , n10095 , n10096 , n10097 , n10098 , n10099 , n10100 ,
n10101 , n10102 , n10103 , n10104 , n10105 , n10106 , n10107 , n10108 , n10109 , n10110 ,
n10111 , n10112 , n10113 , n10114 , n10115 , n10116 , n10117 , n10118 , n10119 , n10120 ,
n10121 , n10122 , n10123 , n10124 , n10125 , n10126 , n10127 , n10128 , n10129 , n10130 ,
n10131 , n10132 , n10133 , n10134 , n10135 , n10136 , n10137 , n10138 , n10139 , n10140 ,
n10141 , n10142 , n10143 , n10144 , n10145 , n10146 , n10147 , n10148 , n10149 , n10150 ,
n10151 , n10152 , n10153 , n10154 , n10155 , n10156 , n10157 , n10158 , n10159 , n10160 ,
n10161 , n10162 , n10163 , n10164 , n10165 , n10166 , n10167 , n10168 , n10169 , n10170 ,
n10171 , n10172 , n10173 , n10174 , n10175 , n10176 , n10177 , n10178 , n10179 , n10180 ,
n10181 , n10182 , n10183 , n10184 , n10185 , n10186 , n10187 , n10188 , n10189 , n10190 ,
n10191 , n10192 , n10193 , n10194 , n10195 , n10196 , n10197 , n10198 , n10199 , n10200 ,
n10201 , n10202 , n10203 , n10204 , n10205 , n10206 , n10207 , n10208 , n10209 , n10210 ,
n10211 , n10212 , n10213 , n10214 , n10215 , n10216 , n10217 , n10218 , n10219 , n10220 ,
n10221 , n10222 , n10223 , n10224 , n10225 , n10226 , n10227 , n10228 , n10229 , n10230 ,
n10231 , n10232 , n10233 , n10234 , n10235 , n10236 , n10237 , n10238 , n10239 , n10240 ,
n10241 , n10242 , n10243 , n10244 , n10245 , n10246 , n10247 , n10248 , n10249 , n10250 ,
n10251 , n10252 , n10253 , n10254 , n10255 , n10256 , n10257 , n10258 , n10259 , n10260 ,
n10261 , n10262 , n10263 , n10264 , n10265 , n10266 , n10267 , n10268 , n10269 , n10270 ,
n10271 , n10272 , n10273 , n10274 , n10275 , n10276 , n10277 , n10278 , n10279 , n10280 ,
n10281 , n10282 , n10283 , n10284 , n10285 , n10286 , n10287 , n10288 , n10289 , n10290 ,
n10291 , n10292 , n10293 , n10294 , n10295 , n10296 , n10297 , n10298 , n10299 , n10300 ,
n10301 , n10302 , n10303 , n10304 , n10305 , n10306 , n10307 , n10308 , n10309 , n10310 ,
n10311 , n10312 , n10313 , n10314 , n10315 , n10316 , n10317 , n10318 , n10319 , n10320 ,
n10321 , n10322 , n10323 , n10324 , n10325 , n10326 , n10327 , n10328 , n10329 , n10330 ,
n10331 , n10332 , n10333 , n10334 , n10335 , n10336 , n10337 , n10338 , n10339 , n10340 ,
n10341 , n10342 , n10343 , n10344 , n10345 , n10346 , n10347 , n10348 , n10349 , n10350 ,
n10351 , n10352 , n10353 , n10354 , n10355 , n10356 , n10357 , n10358 , n10359 , n10360 ,
n10361 , n10362 , n10363 , n10364 , n10365 , n10366 , n10367 , n10368 , n10369 , n10370 ,
n10371 , n10372 , n10373 , n10374 , n10375 , n10376 , n10377 , n10378 , n10379 , n10380 ,
n10381 , n10382 , n10383 , n10384 , n10385 , n10386 , n10387 , n10388 , n10389 , n10390 ,
n10391 , n10392 , n10393 , n10394 , n10395 , n10396 , n10397 , n10398 , n10399 , n10400 ,
n10401 , n10402 , n10403 , n10404 , n10405 , n10406 , n10407 , n10408 , n10409 , n10410 ,
n10411 , n10412 , n10413 , n10414 , n10415 , n10416 , n10417 , n10418 , n10419 , n10420 ,
n10421 , n10422 , n10423 , n10424 , n10425 , n10426 , n10427 , n10428 , n10429 , n10430 ,
n10431 , n10432 , n10433 , n10434 , n10435 , n10436 , n10437 , n10438 , n10439 , n10440 ,
n10441 , n10442 , n10443 , n10444 , n10445 , n10446 , n10447 , n10448 , n10449 , n10450 ,
n10451 , n10452 , n10453 , n10454 , n10455 , n10456 , n10457 , n10458 , n10459 , n10460 ,
n10461 , n10462 , n10463 , n10464 , n10465 , n10466 , n10467 , n10468 , n10469 , n10470 ,
n10471 , n10472 , n10473 , n10474 , n10475 , n10476 , n10477 , n10478 , n10479 , n10480 ,
n10481 , n10482 , n10483 , n10484 , n10485 , n10486 , n10487 , n10488 , n10489 , n10490 ,
n10491 , n10492 , n10493 , n10494 , n10495 , n10496 , n10497 , n10498 , n10499 , n10500 ,
n10501 , n10502 , n10503 , n10504 , n10505 , n10506 , n10507 , n10508 , n10509 , n10510 ,
n10511 , n10512 , n10513 , n10514 , n10515 , n10516 , n10517 , n10518 , n10519 , n10520 ,
n10521 , n10522 , n10523 , n10524 , n10525 , n10526 , n10527 , n10528 , n10529 , n10530 ,
n10531 , n10532 , n10533 , n10534 , n10535 , n10536 , n10537 , n10538 , n10539 , n10540 ,
n10541 , n10542 , n10543 , n10544 , n10545 , n10546 , n10547 , n10548 , n10549 , n10550 ,
n10551 , n10552 , n10553 , n10554 , n10555 , n10556 , n10557 , n10558 , n10559 , n10560 ,
n10561 , n10562 , n10563 , n10564 , n10565 , n10566 , n10567 , n10568 , n10569 , n10570 ,
n10571 , n10572 , n10573 , n10574 , n10575 , n10576 , n10577 , n10578 , n10579 , n10580 ,
n10581 , n10582 , n10583 , n10584 , n10585 , n10586 , n10587 , n10588 , n10589 , n10590 ,
n10591 , n10592 , n10593 , n10594 , n10595 , n10596 , n10597 , n10598 , n10599 , n10600 ,
n10601 , n10602 , n10603 , n10604 , n10605 , n10606 , n10607 , n10608 , n10609 , n10610 ,
n10611 , n10612 , n10613 , n10614 , n10615 , n10616 , n10617 , n10618 , n10619 , n10620 ,
n10621 , n10622 , n10623 , n10624 , n10625 , n10626 , n10627 , n10628 , n10629 , n10630 ,
n10631 , n10632 , n10633 , n10634 , n10635 , n10636 , n10637 , n10638 , n10639 , n10640 ,
n10641 , n10642 , n10643 , n10644 , n10645 , n10646 , n10647 , n10648 , n10649 , n10650 ,
n10651 , n10652 , n10653 , n10654 , n10655 , n10656 , n10657 , n10658 , n10659 , n10660 ,
n10661 , n10662 , n10663 , n10664 , n10665 , n10666 , n10667 , n10668 , n10669 , n10670 ,
n10671 , n10672 , n10673 , n10674 , n10675 , n10676 , n10677 , n10678 , n10679 , n10680 ,
n10681 , n10682 , n10683 , n10684 , n10685 , n10686 , n10687 , n10688 , n10689 , n10690 ,
n10691 , n10692 , n10693 , n10694 , n10695 , n10696 , n10697 , n10698 , n10699 , n10700 ,
n10701 , n10702 , n10703 , n10704 , n10705 , n10706 , n10707 , n10708 , n10709 , n10710 ,
n10711 , n10712 , n10713 , n10714 , n10715 , n10716 , n10717 , n10718 , n10719 , n10720 ,
n10721 , n10722 , n10723 , n10724 , n10725 , n10726 , n10727 , n10728 , n10729 , n10730 ,
n10731 , n10732 , n10733 , n10734 , n10735 , n10736 , n10737 , n10738 , n10739 , n10740 ,
n10741 , n10742 , n10743 , n10744 , n10745 , n10746 , n10747 , n10748 , n10749 , n10750 ,
n10751 , n10752 , n10753 , n10754 , n10755 , n10756 , n10757 , n10758 , n10759 , n10760 ,
n10761 , n10762 , n10763 , n10764 , n10765 , n10766 , n10767 , n10768 , n10769 , n10770 ,
n10771 , n10772 , n10773 , n10774 , n10775 , n10776 , n10777 , n10778 , n10779 , n10780 ,
n10781 , n10782 , n10783 , n10784 , n10785 , n10786 , n10787 , n10788 , n10789 , n10790 ,
n10791 , n10792 , n10793 , n10794 , n10795 , n10796 , n10797 , n10798 , n10799 , n10800 ,
n10801 , n10802 , n10803 , n10804 , n10805 , n10806 , n10807 , n10808 , n10809 , n10810 ,
n10811 , n10812 , n10813 , n10814 , n10815 , n10816 , n10817 , n10818 , n10819 , n10820 ,
n10821 , n10822 , n10823 , n10824 , n10825 , n10826 , n10827 , n10828 , n10829 , n10830 ,
n10831 , n10832 , n10833 , n10834 , n10835 , n10836 , n10837 , n10838 , n10839 , n10840 ,
n10841 , n10842 , n10843 , n10844 , n10845 , n10846 , n10847 , n10848 , n10849 , n10850 ,
n10851 , n10852 , n10853 , n10854 , n10855 , n10856 , n10857 , n10858 , n10859 , n10860 ,
n10861 , n10862 , n10863 , n10864 , n10865 , n10866 , n10867 , n10868 , n10869 , n10870 ,
n10871 , n10872 , n10873 , n10874 , n10875 , n10876 , n10877 , n10878 , n10879 , n10880 ,
n10881 , n10882 , n10883 , n10884 , n10885 , n10886 , n10887 , n10888 , n10889 , n10890 ,
n10891 , n10892 , n10893 , n10894 , n10895 , n10896 , n10897 , n10898 , n10899 , n10900 ,
n10901 , n10902 , n10903 , n10904 , n10905 , n10906 , n10907 , n10908 , n10909 , n10910 ,
n10911 , n10912 , n10913 , n10914 , n10915 , n10916 , n10917 , n10918 , n10919 , n10920 ,
n10921 , n10922 , n10923 , n10924 , n10925 , n10926 , n10927 , n10928 , n10929 , n10930 ,
n10931 , n10932 , n10933 , n10934 , n10935 , n10936 , n10937 , n10938 , n10939 , n10940 ,
n10941 , n10942 , n10943 , n10944 , n10945 , n10946 , n10947 , n10948 , n10949 , n10950 ,
n10951 , n10952 , n10953 , n10954 , n10955 , n10956 , n10957 , n10958 , n10959 , n10960 ,
n10961 , n10962 , n10963 , n10964 , n10965 , n10966 , n10967 , n10968 , n10969 , n10970 ,
n10971 , n10972 , n10973 , n10974 , n10975 , n10976 , n10977 , n10978 , n10979 , n10980 ,
n10981 , n10982 , n10983 , n10984 , n10985 , n10986 , n10987 , n10988 , n10989 , n10990 ,
n10991 , n10992 , n10993 , n10994 , n10995 , n10996 , n10997 , n10998 , n10999 , n11000 ,
n11001 , n11002 , n11003 , n11004 , n11005 , n11006 , n11007 , n11008 , n11009 , n11010 ,
n11011 , n11012 , n11013 , n11014 , n11015 , n11016 , n11017 , n11018 , n11019 , n11020 ,
n11021 , n11022 , n11023 , n11024 , n11025 , n11026 , n11027 , n11028 , n11029 , n11030 ,
n11031 , n11032 , n11033 , n11034 , n11035 , n11036 , n11037 , n11038 , n11039 , n11040 ,
n11041 , n11042 , n11043 , n11044 , n11045 , n11046 , n11047 , n11048 , n11049 , n11050 ,
n11051 , n11052 , n11053 , n11054 , n11055 , n11056 , n11057 , n11058 , n11059 , n11060 ,
n11061 , n11062 , n11063 , n11064 , n11065 , n11066 , n11067 , n11068 , n11069 , n11070 ,
n11071 , n11072 , n11073 , n11074 , n11075 , n11076 , n11077 , n11078 , n11079 , n11080 ,
n11081 , n11082 , n11083 , n11084 , n11085 , n11086 , n11087 , n11088 , n11089 , n11090 ,
n11091 , n11092 , n11093 , n11094 , n11095 , n11096 , n11097 , n11098 , n11099 , n11100 ,
n11101 , n11102 , n11103 , n11104 , n11105 , n11106 , n11107 , n11108 , n11109 , n11110 ,
n11111 , n11112 , n11113 , n11114 , n11115 , n11116 , n11117 , n11118 , n11119 , n11120 ,
n11121 , n11122 , n11123 , n11124 , n11125 , n11126 , n11127 , n11128 , n11129 , n11130 ,
n11131 , n11132 , n11133 , n11134 , n11135 , n11136 , n11137 , n11138 , n11139 , n11140 ,
n11141 , n11142 , n11143 , n11144 , n11145 , n11146 , n11147 , n11148 , n11149 , n11150 ,
n11151 , n11152 , n11153 , n11154 , n11155 , n11156 , n11157 , n11158 , n11159 , n11160 ,
n11161 , n11162 , n11163 , n11164 , n11165 , n11166 , n11167 , n11168 , n11169 , n11170 ,
n11171 , n11172 , n11173 , n11174 , n11175 , n11176 , n11177 , n11178 , n11179 , n11180 ,
n11181 , n11182 , n11183 , n11184 , n11185 , n11186 , n11187 , n11188 , n11189 , n11190 ,
n11191 , n11192 , n11193 , n11194 , n11195 , n11196 , n11197 , n11198 , n11199 , n11200 ,
n11201 , n11202 , n11203 , n11204 , n11205 , n11206 , n11207 , n11208 , n11209 , n11210 ,
n11211 , n11212 , n11213 , n11214 , n11215 , n11216 , n11217 , n11218 , n11219 , n11220 ,
n11221 , n11222 , n11223 , n11224 , n11225 , n11226 , n11227 , n11228 , n11229 , n11230 ,
n11231 , n11232 , n11233 , n11234 , n11235 , n11236 , n11237 , n11238 , n11239 , n11240 ,
n11241 , n11242 , n11243 , n11244 , n11245 , n11246 , n11247 , n11248 , n11249 , n11250 ,
n11251 , n11252 , n11253 , n11254 , n11255 , n11256 , n11257 , n11258 , n11259 , n11260 ,
n11261 , n11262 , n11263 , n11264 , n11265 , n11266 , n11267 , n11268 , n11269 , n11270 ,
n11271 , n11272 , n11273 , n11274 , n11275 , n11276 , n11277 , n11278 , n11279 , n11280 ,
n11281 , n11282 , n11283 , n11284 , n11285 , n11286 , n11287 , n11288 , n11289 , n11290 ,
n11291 , n11292 , n11293 , n11294 , n11295 , n11296 , n11297 , n11298 , n11299 , n11300 ,
n11301 , n11302 , n11303 , n11304 , n11305 , n11306 , n11307 , n11308 , n11309 , n11310 ,
n11311 , n11312 , n11313 , n11314 , n11315 , n11316 , n11317 , n11318 , n11319 , n11320 ,
n11321 , n11322 , n11323 , n11324 , n11325 , n11326 , n11327 , n11328 , n11329 , n11330 ,
n11331 , n11332 , n11333 , n11334 , n11335 , n11336 , n11337 , n11338 , n11339 , n11340 ,
n11341 , n11342 , n11343 , n11344 , n11345 , n11346 , n11347 , n11348 , n11349 , n11350 ,
n11351 , n11352 , n11353 , n11354 , n11355 , n11356 , n11357 , n11358 , n11359 , n11360 ,
n11361 , n11362 , n11363 , n11364 , n11365 , n11366 , n11367 , n11368 , n11369 , n11370 ,
n11371 , n11372 , n11373 , n11374 , n11375 , n11376 , n11377 , n11378 , n11379 , n11380 ,
n11381 , n11382 , n11383 , n11384 , n11385 , n11386 , n11387 , n11388 , n11389 , n11390 ,
n11391 , n11392 , n11393 , n11394 , n11395 , n11396 , n11397 , n11398 , n11399 , n11400 ,
n11401 , n11402 , n11403 , n11404 , n11405 , n11406 , n11407 , n11408 , n11409 , n11410 ,
n11411 , n11412 , n11413 , n11414 , n11415 , n11416 , n11417 , n11418 , n11419 , n11420 ,
n11421 , n11422 , n11423 , n11424 , n11425 , n11426 , n11427 , n11428 , n11429 , n11430 ,
n11431 , n11432 , n11433 , n11434 , n11435 , n11436 , n11437 , n11438 , n11439 , n11440 ,
n11441 , n11442 , n11443 , n11444 , n11445 , n11446 , n11447 , n11448 , n11449 , n11450 ,
n11451 , n11452 , n11453 , n11454 , n11455 , n11456 , n11457 , n11458 , n11459 , n11460 ,
n11461 , n11462 , n11463 , n11464 , n11465 , n11466 , n11467 , n11468 , n11469 , n11470 ,
n11471 , n11472 , n11473 , n11474 , n11475 , n11476 , n11477 , n11478 , n11479 , n11480 ,
n11481 , n11482 , n11483 , n11484 , n11485 , n11486 , n11487 , n11488 , n11489 , n11490 ,
n11491 , n11492 , n11493 , n11494 , n11495 , n11496 , n11497 , n11498 , n11499 , n11500 ,
n11501 , n11502 , n11503 , n11504 , n11505 , n11506 , n11507 , n11508 , n11509 , n11510 ,
n11511 , n11512 , n11513 , n11514 , n11515 , n11516 , n11517 , n11518 , n11519 , n11520 ,
n11521 , n11522 , n11523 , n11524 , n11525 , n11526 , n11527 , n11528 , n11529 , n11530 ,
n11531 , n11532 , n11533 , n11534 , n11535 , n11536 , n11537 , n11538 , n11539 , n11540 ,
n11541 , n11542 , n11543 , n11544 , n11545 , n11546 , n11547 , n11548 , n11549 , n11550 ,
n11551 , n11552 , n11553 , n11554 , n11555 , n11556 , n11557 , n11558 , n11559 , n11560 ,
n11561 , n11562 , n11563 , n11564 , n11565 , n11566 , n11567 , n11568 , n11569 , n11570 ,
n11571 , n11572 , n11573 , n11574 , n11575 , n11576 , n11577 , n11578 , n11579 , n11580 ,
n11581 , n11582 , n11583 , n11584 , n11585 , n11586 , n11587 , n11588 , n11589 , n11590 ,
n11591 , n11592 , n11593 , n11594 , n11595 , n11596 , n11597 , n11598 , n11599 , n11600 ,
n11601 , n11602 , n11603 , n11604 , n11605 , n11606 , n11607 , n11608 , n11609 , n11610 ,
n11611 , n11612 , n11613 , n11614 , n11615 , n11616 , n11617 , n11618 , n11619 , n11620 ,
n11621 , n11622 , n11623 , n11624 , n11625 , n11626 , n11627 , n11628 , n11629 , n11630 ,
n11631 , n11632 , n11633 , n11634 , n11635 , n11636 , n11637 , n11638 , n11639 , n11640 ,
n11641 , n11642 , n11643 , n11644 , n11645 , n11646 , n11647 , n11648 , n11649 , n11650 ,
n11651 , n11652 , n11653 , n11654 , n11655 , n11656 , n11657 , n11658 , n11659 , n11660 ,
n11661 , n11662 , n11663 , n11664 , n11665 , n11666 , n11667 , n11668 , n11669 , n11670 ,
n11671 , n11672 , n11673 , n11674 , n11675 , n11676 , n11677 , n11678 , n11679 , n11680 ,
n11681 , n11682 , n11683 , n11684 , n11685 , n11686 , n11687 , n11688 , n11689 , n11690 ,
n11691 , n11692 , n11693 , n11694 , n11695 , n11696 , n11697 , n11698 , n11699 , n11700 ,
n11701 , n11702 , n11703 , n11704 , n11705 , n11706 , n11707 , n11708 , n11709 , n11710 ,
n11711 , n11712 , n11713 , n11714 , n11715 , n11716 , n11717 , n11718 , n11719 , n11720 ,
n11721 , n11722 , n11723 , n11724 , n11725 , n11726 , n11727 , n11728 , n11729 , n11730 ,
n11731 , n11732 , n11733 , n11734 , n11735 , n11736 , n11737 , n11738 , n11739 , n11740 ,
n11741 , n11742 , n11743 , n11744 , n11745 , n11746 , n11747 , n11748 , n11749 , n11750 ,
n11751 , n11752 , n11753 , n11754 , n11755 , n11756 , n11757 , n11758 , n11759 , n11760 ,
n11761 , n11762 , n11763 , n11764 , n11765 , n11766 , n11767 , n11768 , n11769 , n11770 ,
n11771 , n11772 , n11773 , n11774 , n11775 , n11776 , n11777 , n11778 , n11779 , n11780 ,
n11781 , n11782 , n11783 , n11784 , n11785 , n11786 , n11787 , n11788 , n11789 , n11790 ,
n11791 , n11792 , n11793 , n11794 , n11795 , n11796 , n11797 , n11798 , n11799 , n11800 ,
n11801 , n11802 , n11803 , n11804 , n11805 , n11806 , n11807 , n11808 , n11809 , n11810 ,
n11811 , n11812 , n11813 , n11814 , n11815 , n11816 , n11817 , n11818 , n11819 , n11820 ,
n11821 , n11822 , n11823 , n11824 , n11825 , n11826 , n11827 , n11828 , n11829 , n11830 ,
n11831 , n11832 , n11833 , n11834 , n11835 , n11836 , n11837 , n11838 , n11839 , n11840 ,
n11841 , n11842 , n11843 , n11844 , n11845 , n11846 , n11847 , n11848 , n11849 , n11850 ,
n11851 , n11852 , n11853 , n11854 , n11855 , n11856 , n11857 , n11858 , n11859 , n11860 ,
n11861 , n11862 , n11863 , n11864 , n11865 , n11866 , n11867 , n11868 , n11869 , n11870 ,
n11871 , n11872 , n11873 , n11874 , n11875 , n11876 , n11877 , n11878 , n11879 , n11880 ,
n11881 , n11882 , n11883 , n11884 , n11885 , n11886 , n11887 , n11888 , n11889 , n11890 ,
n11891 , n11892 , n11893 , n11894 , n11895 , n11896 , n11897 , n11898 , n11899 , n11900 ,
n11901 , n11902 , n11903 , n11904 , n11905 , n11906 , n11907 , n11908 , n11909 , n11910 ,
n11911 , n11912 , n11913 , n11914 , n11915 , n11916 , n11917 , n11918 , n11919 , n11920 ,
n11921 , n11922 , n11923 , n11924 , n11925 , n11926 , n11927 , n11928 , n11929 , n11930 ,
n11931 , n11932 , n11933 , n11934 , n11935 , n11936 , n11937 , n11938 , n11939 , n11940 ,
n11941 , n11942 , n11943 , n11944 , n11945 , n11946 , n11947 , n11948 , n11949 , n11950 ,
n11951 , n11952 , n11953 , n11954 , n11955 , n11956 , n11957 , n11958 , n11959 , n11960 ,
n11961 , n11962 , n11963 , n11964 , n11965 , n11966 , n11967 , n11968 , n11969 , n11970 ,
n11971 , n11972 , n11973 , n11974 , n11975 , n11976 , n11977 , n11978 , n11979 , n11980 ,
n11981 , n11982 , n11983 , n11984 , n11985 , n11986 , n11987 , n11988 , n11989 , n11990 ,
n11991 , n11992 , n11993 , n11994 , n11995 , n11996 , n11997 , n11998 , n11999 , n12000 ,
n12001 , n12002 , n12003 , n12004 , n12005 , n12006 , n12007 , n12008 , n12009 , n12010 ,
n12011 , n12012 , n12013 , n12014 , n12015 , n12016 , n12017 , n12018 , n12019 , n12020 ,
n12021 , n12022 , n12023 , n12024 , n12025 , n12026 , n12027 , n12028 , n12029 , n12030 ,
n12031 , n12032 , n12033 , n12034 , n12035 , n12036 , n12037 , n12038 , n12039 , n12040 ,
n12041 , n12042 , n12043 , n12044 , n12045 , n12046 , n12047 , n12048 , n12049 , n12050 ,
n12051 , n12052 , n12053 , n12054 , n12055 , n12056 , n12057 , n12058 , n12059 , n12060 ,
n12061 , n12062 , n12063 , n12064 , n12065 , n12066 , n12067 , n12068 , n12069 , n12070 ,
n12071 , n12072 , n12073 , n12074 , n12075 , n12076 , n12077 , n12078 , n12079 , n12080 ,
n12081 , n12082 , n12083 , n12084 , n12085 , n12086 , n12087 , n12088 , n12089 , n12090 ,
n12091 , n12092 , n12093 , n12094 , n12095 , n12096 , n12097 , n12098 , n12099 , n12100 ,
n12101 , n12102 , n12103 , n12104 , n12105 , n12106 , n12107 , n12108 , n12109 , n12110 ,
n12111 , n12112 , n12113 , n12114 , n12115 , n12116 , n12117 , n12118 , n12119 , n12120 ,
n12121 , n12122 , n12123 , n12124 , n12125 , n12126 , n12127 , n12128 , n12129 , n12130 ,
n12131 , n12132 , n12133 , n12134 , n12135 , n12136 , n12137 , n12138 , n12139 , n12140 ,
n12141 , n12142 , n12143 , n12144 , n12145 , n12146 , n12147 , n12148 , n12149 , n12150 ,
n12151 , n12152 , n12153 , n12154 , n12155 , n12156 , n12157 , n12158 , n12159 , n12160 ,
n12161 , n12162 , n12163 , n12164 , n12165 , n12166 , n12167 , n12168 , n12169 , n12170 ,
n12171 , n12172 , n12173 , n12174 , n12175 , n12176 , n12177 , n12178 , n12179 , n12180 ,
n12181 , n12182 , n12183 , n12184 , n12185 , n12186 , n12187 , n12188 , n12189 , n12190 ,
n12191 , n12192 , n12193 , n12194 , n12195 , n12196 , n12197 , n12198 , n12199 , n12200 ,
n12201 , n12202 , n12203 , n12204 , n12205 , n12206 , n12207 , n12208 , n12209 , n12210 ,
n12211 , n12212 , n12213 , n12214 , n12215 , n12216 , n12217 , n12218 , n12219 , n12220 ,
n12221 , n12222 , n12223 , n12224 , n12225 , n12226 , n12227 , n12228 , n12229 , n12230 ,
n12231 , n12232 , n12233 , n12234 , n12235 , n12236 , n12237 , n12238 , n12239 , n12240 ,
n12241 , n12242 , n12243 , n12244 , n12245 , n12246 , n12247 , n12248 , n12249 , n12250 ,
n12251 , n12252 , n12253 , n12254 , n12255 , n12256 , n12257 , n12258 , n12259 , n12260 ,
n12261 , n12262 , n12263 , n12264 , n12265 , n12266 , n12267 , n12268 , n12269 , n12270 ,
n12271 , n12272 , n12273 , n12274 , n12275 , n12276 , n12277 , n12278 , n12279 , n12280 ,
n12281 , n12282 , n12283 , n12284 , n12285 , n12286 , n12287 , n12288 , n12289 , n12290 ,
n12291 , n12292 , n12293 , n12294 , n12295 , n12296 , n12297 , n12298 , n12299 , n12300 ,
n12301 , n12302 , n12303 , n12304 , n12305 , n12306 , n12307 , n12308 , n12309 , n12310 ,
n12311 , n12312 , n12313 , n12314 , n12315 , n12316 , n12317 , n12318 , n12319 , n12320 ,
n12321 , n12322 , n12323 , n12324 , n12325 , n12326 , n12327 , n12328 , n12329 , n12330 ,
n12331 , n12332 , n12333 , n12334 , n12335 , n12336 , n12337 , n12338 , n12339 , n12340 ,
n12341 , n12342 , n12343 , n12344 , n12345 , n12346 , n12347 , n12348 , n12349 , n12350 ,
n12351 , n12352 , n12353 , n12354 , n12355 , n12356 , n12357 , n12358 , n12359 , n12360 ,
n12361 , n12362 , n12363 , n12364 , n12365 , n12366 , n12367 , n12368 , n12369 , n12370 ,
n12371 , n12372 , n12373 , n12374 , n12375 , n12376 , n12377 , n12378 , n12379 , n12380 ,
n12381 , n12382 , n12383 , n12384 , n12385 , n12386 , n12387 , n12388 , n12389 , n12390 ,
n12391 , n12392 , n12393 , n12394 , n12395 , n12396 , n12397 , n12398 , n12399 , n12400 ,
n12401 , n12402 , n12403 , n12404 , n12405 , n12406 , n12407 , n12408 , n12409 , n12410 ,
n12411 , n12412 , n12413 , n12414 , n12415 , n12416 , n12417 , n12418 , n12419 , n12420 ,
n12421 , n12422 , n12423 , n12424 , n12425 , n12426 , n12427 , n12428 , n12429 , n12430 ,
n12431 , n12432 , n12433 , n12434 , n12435 , n12436 , n12437 , n12438 , n12439 , n12440 ,
n12441 , n12442 , n12443 , n12444 , n12445 , n12446 , n12447 , n12448 , n12449 , n12450 ,
n12451 , n12452 , n12453 , n12454 , n12455 , n12456 , n12457 , n12458 , n12459 , n12460 ,
n12461 , n12462 , n12463 , n12464 , n12465 , n12466 , n12467 , n12468 , n12469 , n12470 ,
n12471 , n12472 , n12473 , n12474 , n12475 , n12476 , n12477 , n12478 , n12479 , n12480 ,
n12481 , n12482 , n12483 , n12484 , n12485 , n12486 , n12487 , n12488 , n12489 , n12490 ,
n12491 , n12492 , n12493 , n12494 , n12495 , n12496 , n12497 , n12498 , n12499 , n12500 ,
n12501 , n12502 , n12503 , n12504 , n12505 , n12506 , n12507 , n12508 , n12509 , n12510 ,
n12511 , n12512 , n12513 , n12514 , n12515 , n12516 , n12517 , n12518 , n12519 , n12520 ,
n12521 , n12522 , n12523 , n12524 , n12525 , n12526 , n12527 , n12528 , n12529 , n12530 ,
n12531 , n12532 , n12533 , n12534 , n12535 , n12536 , n12537 , n12538 , n12539 , n12540 ,
n12541 , n12542 , n12543 , n12544 , n12545 , n12546 , n12547 , n12548 , n12549 , n12550 ,
n12551 , n12552 , n12553 , n12554 , n12555 , n12556 , n12557 , n12558 , n12559 , n12560 ,
n12561 , n12562 , n12563 , n12564 , n12565 , n12566 , n12567 , n12568 , n12569 , n12570 ,
n12571 , n12572 , n12573 , n12574 , n12575 , n12576 , n12577 , n12578 , n12579 , n12580 ,
n12581 , n12582 , n12583 , n12584 , n12585 , n12586 , n12587 , n12588 , n12589 , n12590 ,
n12591 , n12592 , n12593 , n12594 , n12595 , n12596 , n12597 , n12598 , n12599 , n12600 ,
n12601 , n12602 , n12603 , n12604 , n12605 , n12606 , n12607 , n12608 , n12609 , n12610 ,
n12611 , n12612 , n12613 , n12614 , n12615 , n12616 , n12617 , n12618 , n12619 , n12620 ,
n12621 , n12622 , n12623 , n12624 , n12625 , n12626 , n12627 , n12628 , n12629 , n12630 ,
n12631 , n12632 , n12633 , n12634 , n12635 , n12636 , n12637 , n12638 , n12639 , n12640 ,
n12641 , n12642 , n12643 , n12644 , n12645 , n12646 , n12647 , n12648 , n12649 , n12650 ,
n12651 , n12652 , n12653 , n12654 , n12655 , n12656 , n12657 , n12658 , n12659 , n12660 ,
n12661 , n12662 , n12663 , n12664 , n12665 , n12666 , n12667 , n12668 , n12669 , n12670 ,
n12671 , n12672 , n12673 , n12674 , n12675 , n12676 , n12677 , n12678 , n12679 , n12680 ,
n12681 , n12682 , n12683 , n12684 , n12685 , n12686 , n12687 , n12688 , n12689 , n12690 ,
n12691 , n12692 , n12693 , n12694 , n12695 , n12696 , n12697 , n12698 , n12699 , n12700 ,
n12701 , n12702 , n12703 , n12704 , n12705 , n12706 , n12707 , n12708 , n12709 , n12710 ,
n12711 , n12712 , n12713 , n12714 , n12715 , n12716 , n12717 , n12718 , n12719 , n12720 ,
n12721 , n12722 , n12723 , n12724 , n12725 , n12726 , n12727 , n12728 , n12729 , n12730 ,
n12731 , n12732 , n12733 , n12734 , n12735 , n12736 , n12737 , n12738 , n12739 , n12740 ,
n12741 , n12742 , n12743 , n12744 , n12745 , n12746 , n12747 , n12748 , n12749 , n12750 ,
n12751 , n12752 , n12753 , n12754 , n12755 , n12756 , n12757 , n12758 , n12759 , n12760 ,
n12761 , n12762 , n12763 , n12764 , n12765 , n12766 , n12767 , n12768 , n12769 , n12770 ,
n12771 , n12772 , n12773 , n12774 , n12775 , n12776 , n12777 , n12778 , n12779 , n12780 ,
n12781 , n12782 , n12783 , n12784 , n12785 , n12786 , n12787 , n12788 , n12789 , n12790 ,
n12791 , n12792 , n12793 , n12794 , n12795 , n12796 , n12797 , n12798 , n12799 , n12800 ,
n12801 , n12802 , n12803 , n12804 , n12805 , n12806 , n12807 , n12808 , n12809 , n12810 ,
n12811 , n12812 , n12813 , n12814 , n12815 , n12816 , n12817 , n12818 , n12819 , n12820 ,
n12821 , n12822 , n12823 , n12824 , n12825 , n12826 , n12827 , n12828 , n12829 , n12830 ,
n12831 , n12832 , n12833 , n12834 , n12835 , n12836 , n12837 , n12838 , n12839 , n12840 ,
n12841 , n12842 , n12843 , n12844 , n12845 , n12846 , n12847 , n12848 , n12849 , n12850 ,
n12851 , n12852 , n12853 , n12854 , n12855 , n12856 , n12857 , n12858 , n12859 , n12860 ,
n12861 , n12862 , n12863 , n12864 , n12865 , n12866 , n12867 , n12868 , n12869 , n12870 ,
n12871 , n12872 , n12873 , n12874 , n12875 , n12876 , n12877 , n12878 , n12879 , n12880 ,
n12881 , n12882 , n12883 , n12884 , n12885 , n12886 , n12887 , n12888 , n12889 , n12890 ,
n12891 , n12892 , n12893 , n12894 , n12895 , n12896 , n12897 , n12898 , n12899 , n12900 ,
n12901 , n12902 , n12903 , n12904 , n12905 , n12906 , n12907 , n12908 , n12909 , n12910 ,
n12911 , n12912 , n12913 , n12914 , n12915 , n12916 , n12917 , n12918 , n12919 , n12920 ,
n12921 , n12922 , n12923 , n12924 , n12925 , n12926 , n12927 , n12928 , n12929 , n12930 ,
n12931 , n12932 , n12933 , n12934 , n12935 , n12936 , n12937 , n12938 , n12939 , n12940 ,
n12941 , n12942 , n12943 , n12944 , n12945 , n12946 , n12947 , n12948 , n12949 , n12950 ,
n12951 , n12952 , n12953 , n12954 , n12955 , n12956 , n12957 , n12958 , n12959 , n12960 ,
n12961 , n12962 , n12963 , n12964 , n12965 , n12966 , n12967 , n12968 , n12969 , n12970 ,
n12971 , n12972 , n12973 , n12974 , n12975 , n12976 , n12977 , n12978 , n12979 , n12980 ,
n12981 , n12982 , n12983 , n12984 , n12985 , n12986 , n12987 , n12988 , n12989 , n12990 ,
n12991 , n12992 , n12993 , n12994 , n12995 , n12996 , n12997 , n12998 , n12999 , n13000 ,
n13001 , n13002 , n13003 , n13004 , n13005 , n13006 , n13007 , n13008 , n13009 , n13010 ,
n13011 , n13012 , n13013 , n13014 , n13015 , n13016 , n13017 , n13018 , n13019 , n13020 ,
n13021 , n13022 , n13023 , n13024 , n13025 , n13026 , n13027 , n13028 , n13029 , n13030 ,
n13031 , n13032 , n13033 , n13034 , n13035 , n13036 , n13037 , n13038 , n13039 , n13040 ,
n13041 , n13042 , n13043 , n13044 , n13045 , n13046 , n13047 , n13048 , n13049 , n13050 ,
n13051 , n13052 , n13053 , n13054 , n13055 , n13056 , n13057 , n13058 , n13059 , n13060 ,
n13061 , n13062 , n13063 , n13064 , n13065 , n13066 , n13067 , n13068 , n13069 , n13070 ,
n13071 , n13072 , n13073 , n13074 , n13075 , n13076 , n13077 , n13078 , n13079 , n13080 ,
n13081 , n13082 , n13083 , n13084 , n13085 , n13086 , n13087 , n13088 , n13089 , n13090 ,
n13091 , n13092 , n13093 , n13094 , n13095 , n13096 , n13097 , n13098 , n13099 , n13100 ,
n13101 , n13102 , n13103 , n13104 , n13105 , n13106 , n13107 , n13108 , n13109 , n13110 ,
n13111 , n13112 , n13113 , n13114 , n13115 , n13116 , n13117 , n13118 , n13119 , n13120 ,
n13121 , n13122 , n13123 , n13124 , n13125 , n13126 , n13127 , n13128 , n13129 , n13130 ,
n13131 , n13132 , n13133 , n13134 , n13135 , n13136 , n13137 , n13138 , n13139 , n13140 ,
n13141 , n13142 , n13143 , n13144 , n13145 , n13146 , n13147 , n13148 , n13149 , n13150 ,
n13151 , n13152 , n13153 , n13154 , n13155 , n13156 , n13157 , n13158 , n13159 , n13160 ,
n13161 , n13162 , n13163 , n13164 , n13165 , n13166 , n13167 , n13168 , n13169 , n13170 ,
n13171 , n13172 , n13173 , n13174 , n13175 , n13176 , n13177 , n13178 , n13179 , n13180 ,
n13181 , n13182 , n13183 , n13184 , n13185 , n13186 , n13187 , n13188 , n13189 , n13190 ,
n13191 , n13192 , n13193 , n13194 , n13195 , n13196 , n13197 , n13198 , n13199 , n13200 ,
n13201 , n13202 , n13203 , n13204 , n13205 , n13206 , n13207 , n13208 , n13209 , n13210 ,
n13211 , n13212 , n13213 , n13214 , n13215 , n13216 , n13217 , n13218 , n13219 , n13220 ,
n13221 , n13222 , n13223 , n13224 , n13225 , n13226 , n13227 , n13228 , n13229 , n13230 ,
n13231 , n13232 , n13233 , n13234 , n13235 , n13236 , n13237 , n13238 , n13239 , n13240 ,
n13241 , n13242 , n13243 , n13244 , n13245 , n13246 , n13247 , n13248 , n13249 , n13250 ,
n13251 , n13252 , n13253 , n13254 , n13255 , n13256 , n13257 , n13258 , n13259 , n13260 ,
n13261 , n13262 , n13263 , n13264 , n13265 , n13266 , n13267 , n13268 , n13269 , n13270 ,
n13271 , n13272 , n13273 , n13274 , n13275 , n13276 , n13277 , n13278 , n13279 , n13280 ,
n13281 , n13282 , n13283 , n13284 , n13285 , n13286 , n13287 , n13288 , n13289 , n13290 ,
n13291 , n13292 , n13293 , n13294 , n13295 , n13296 , n13297 , n13298 , n13299 , n13300 ,
n13301 , n13302 , n13303 , n13304 , n13305 , n13306 , n13307 , n13308 , n13309 , n13310 ,
n13311 , n13312 , n13313 , n13314 , n13315 , n13316 , n13317 , n13318 , n13319 , n13320 ,
n13321 , n13322 , n13323 , n13324 , n13325 , n13326 , n13327 , n13328 , n13329 , n13330 ,
n13331 , n13332 , n13333 , n13334 , n13335 , n13336 , n13337 , n13338 , n13339 , n13340 ,
n13341 , n13342 , n13343 , n13344 , n13345 , n13346 , n13347 , n13348 , n13349 , n13350 ,
n13351 , n13352 , n13353 , n13354 , n13355 , n13356 , n13357 , n13358 , n13359 , n13360 ,
n13361 , n13362 , n13363 , n13364 , n13365 , n13366 , n13367 , n13368 , n13369 , n13370 ,
n13371 , n13372 , n13373 , n13374 , n13375 , n13376 , n13377 , n13378 , n13379 , n13380 ,
n13381 , n13382 , n13383 , n13384 , n13385 , n13386 , n13387 , n13388 , n13389 , n13390 ,
n13391 , n13392 , n13393 , n13394 , n13395 , n13396 , n13397 , n13398 , n13399 , n13400 ,
n13401 , n13402 , n13403 , n13404 , n13405 , n13406 , n13407 , n13408 , n13409 , n13410 ,
n13411 , n13412 , n13413 , n13414 , n13415 , n13416 , n13417 , n13418 , n13419 , n13420 ,
n13421 , n13422 , n13423 , n13424 , n13425 , n13426 , n13427 , n13428 , n13429 , n13430 ,
n13431 , n13432 , n13433 , n13434 , n13435 , n13436 , n13437 , n13438 , n13439 , n13440 ,
n13441 , n13442 , n13443 , n13444 , n13445 , n13446 , n13447 , n13448 , n13449 , n13450 ,
n13451 , n13452 , n13453 , n13454 , n13455 , n13456 , n13457 , n13458 , n13459 , n13460 ,
n13461 , n13462 , n13463 , n13464 , n13465 , n13466 , n13467 , n13468 , n13469 , n13470 ,
n13471 , n13472 , n13473 , n13474 , n13475 , n13476 , n13477 , n13478 , n13479 , n13480 ,
n13481 , n13482 , n13483 , n13484 , n13485 , n13486 , n13487 , n13488 , n13489 , n13490 ,
n13491 , n13492 , n13493 , n13494 , n13495 , n13496 , n13497 , n13498 , n13499 , n13500 ,
n13501 , n13502 , n13503 , n13504 , n13505 , n13506 , n13507 , n13508 , n13509 , n13510 ,
n13511 , n13512 , n13513 , n13514 , n13515 , n13516 , n13517 , n13518 , n13519 , n13520 ,
n13521 , n13522 , n13523 , n13524 , n13525 , n13526 , n13527 , n13528 , n13529 , n13530 ,
n13531 , n13532 , n13533 , n13534 , n13535 , n13536 , n13537 , n13538 , n13539 , n13540 ,
n13541 , n13542 , n13543 , n13544 , n13545 , n13546 , n13547 , n13548 , n13549 , n13550 ,
n13551 , n13552 , n13553 , n13554 , n13555 , n13556 , n13557 , n13558 , n13559 , n13560 ,
n13561 , n13562 , n13563 , n13564 , n13565 , n13566 , n13567 , n13568 , n13569 , n13570 ,
n13571 , n13572 , n13573 , n13574 , n13575 , n13576 , n13577 , n13578 , n13579 , n13580 ,
n13581 , n13582 , n13583 , n13584 , n13585 , n13586 , n13587 , n13588 , n13589 , n13590 ,
n13591 , n13592 , n13593 , n13594 , n13595 , n13596 , n13597 , n13598 , n13599 , n13600 ,
n13601 , n13602 , n13603 , n13604 , n13605 , n13606 , n13607 , n13608 , n13609 , n13610 ,
n13611 , n13612 , n13613 , n13614 , n13615 , n13616 , n13617 , n13618 , n13619 , n13620 ,
n13621 , n13622 , n13623 , n13624 , n13625 , n13626 , n13627 , n13628 , n13629 , n13630 ,
n13631 , n13632 , n13633 , n13634 , n13635 , n13636 , n13637 , n13638 , n13639 , n13640 ,
n13641 , n13642 , n13643 , n13644 , n13645 , n13646 , n13647 , n13648 , n13649 , n13650 ,
n13651 , n13652 , n13653 , n13654 , n13655 , n13656 , n13657 , n13658 , n13659 , n13660 ,
n13661 , n13662 , n13663 , n13664 , n13665 , n13666 , n13667 , n13668 , n13669 , n13670 ,
n13671 , n13672 , n13673 , n13674 , n13675 , n13676 , n13677 , n13678 , n13679 , n13680 ,
n13681 , n13682 , n13683 , n13684 , n13685 , n13686 , n13687 , n13688 , n13689 , n13690 ,
n13691 , n13692 , n13693 , n13694 , n13695 , n13696 , n13697 , n13698 , n13699 , n13700 ,
n13701 , n13702 , n13703 , n13704 , n13705 , n13706 , n13707 , n13708 , n13709 , n13710 ,
n13711 , n13712 , n13713 , n13714 , n13715 , n13716 , n13717 , n13718 , n13719 , n13720 ,
n13721 , n13722 , n13723 , n13724 , n13725 , n13726 , n13727 , n13728 , n13729 , n13730 ,
n13731 , n13732 , n13733 , n13734 , n13735 , n13736 , n13737 , n13738 , n13739 , n13740 ,
n13741 , n13742 , n13743 , n13744 , n13745 , n13746 , n13747 , n13748 , n13749 , n13750 ,
n13751 , n13752 , n13753 , n13754 , n13755 , n13756 , n13757 , n13758 , n13759 , n13760 ,
n13761 , n13762 , n13763 , n13764 , n13765 , n13766 , n13767 , n13768 , n13769 , n13770 ,
n13771 , n13772 , n13773 , n13774 , n13775 , n13776 , n13777 , n13778 , n13779 , n13780 ,
n13781 , n13782 , n13783 , n13784 , n13785 , n13786 , n13787 , n13788 , n13789 , n13790 ,
n13791 , n13792 , n13793 , n13794 , n13795 , n13796 , n13797 , n13798 , n13799 , n13800 ,
n13801 , n13802 , n13803 , n13804 , n13805 , n13806 , n13807 , n13808 , n13809 , n13810 ,
n13811 , n13812 , n13813 , n13814 , n13815 , n13816 , n13817 , n13818 , n13819 , n13820 ,
n13821 , n13822 , n13823 , n13824 , n13825 , n13826 , n13827 , n13828 , n13829 , n13830 ,
n13831 , n13832 , n13833 , n13834 , n13835 , n13836 , n13837 , n13838 , n13839 , n13840 ,
n13841 , n13842 , n13843 , n13844 , n13845 , n13846 , n13847 , n13848 , n13849 , n13850 ,
n13851 , n13852 , n13853 , n13854 , n13855 , n13856 , n13857 , n13858 , n13859 , n13860 ,
n13861 , n13862 , n13863 , n13864 , n13865 , n13866 , n13867 , n13868 , n13869 , n13870 ,
n13871 , n13872 , n13873 , n13874 , n13875 , n13876 , n13877 , n13878 , n13879 , n13880 ,
n13881 , n13882 , n13883 , n13884 , n13885 , n13886 , n13887 , n13888 , n13889 , n13890 ,
n13891 , n13892 , n13893 , n13894 , n13895 , n13896 , n13897 , n13898 , n13899 , n13900 ,
n13901 , n13902 , n13903 , n13904 , n13905 , n13906 , n13907 , n13908 , n13909 , n13910 ,
n13911 , n13912 , n13913 , n13914 , n13915 , n13916 , n13917 , n13918 , n13919 , n13920 ,
n13921 , n13922 , n13923 , n13924 , n13925 , n13926 , n13927 , n13928 , n13929 , n13930 ,
n13931 , n13932 , n13933 , n13934 , n13935 , n13936 , n13937 , n13938 , n13939 , n13940 ,
n13941 , n13942 , n13943 , n13944 , n13945 , n13946 , n13947 , n13948 , n13949 , n13950 ,
n13951 , n13952 , n13953 , n13954 , n13955 , n13956 , n13957 , n13958 , n13959 , n13960 ,
n13961 , n13962 , n13963 , n13964 , n13965 , n13966 , n13967 , n13968 , n13969 , n13970 ,
n13971 , n13972 , n13973 , n13974 , n13975 , n13976 , n13977 , n13978 , n13979 , n13980 ,
n13981 , n13982 , n13983 , n13984 , n13985 , n13986 , n13987 , n13988 , n13989 , n13990 ,
n13991 , n13992 , n13993 , n13994 , n13995 , n13996 , n13997 , n13998 , n13999 , n14000 ,
n14001 , n14002 , n14003 , n14004 , n14005 , n14006 , n14007 , n14008 , n14009 , n14010 ,
n14011 , n14012 , n14013 , n14014 , n14015 , n14016 , n14017 , n14018 , n14019 , n14020 ,
n14021 , n14022 , n14023 , n14024 , n14025 , n14026 , n14027 , n14028 , n14029 , n14030 ,
n14031 , n14032 , n14033 , n14034 , n14035 , n14036 , n14037 , n14038 , n14039 , n14040 ,
n14041 , n14042 , n14043 , n14044 , n14045 , n14046 , n14047 , n14048 , n14049 , n14050 ,
n14051 , n14052 , n14053 , n14054 , n14055 , n14056 , n14057 , n14058 , n14059 , n14060 ,
n14061 , n14062 , n14063 , n14064 , n14065 , n14066 , n14067 , n14068 , n14069 , n14070 ,
n14071 , n14072 , n14073 , n14074 , n14075 , n14076 , n14077 , n14078 , n14079 , n14080 ,
n14081 , n14082 , n14083 , n14084 , n14085 , n14086 , n14087 , n14088 , n14089 , n14090 ,
n14091 , n14092 , n14093 , n14094 , n14095 , n14096 , n14097 , n14098 , n14099 , n14100 ,
n14101 , n14102 , n14103 , n14104 , n14105 , n14106 , n14107 , n14108 , n14109 , n14110 ,
n14111 , n14112 , n14113 , n14114 , n14115 , n14116 , n14117 , n14118 , n14119 , n14120 ,
n14121 , n14122 , n14123 , n14124 , n14125 , n14126 , n14127 , n14128 , n14129 , n14130 ,
n14131 , n14132 , n14133 , n14134 , n14135 , n14136 , n14137 , n14138 , n14139 , n14140 ,
n14141 , n14142 , n14143 , n14144 , n14145 , n14146 , n14147 , n14148 , n14149 , n14150 ,
n14151 , n14152 , n14153 , n14154 , n14155 , n14156 , n14157 , n14158 , n14159 , n14160 ,
n14161 , n14162 , n14163 , n14164 , n14165 , n14166 , n14167 , n14168 , n14169 , n14170 ,
n14171 , n14172 , n14173 , n14174 , n14175 , n14176 , n14177 , n14178 , n14179 , n14180 ,
n14181 , n14182 , n14183 , n14184 , n14185 , n14186 , n14187 , n14188 , n14189 , n14190 ,
n14191 , n14192 , n14193 , n14194 , n14195 , n14196 , n14197 , n14198 , n14199 , n14200 ,
n14201 , n14202 , n14203 , n14204 , n14205 , n14206 , n14207 , n14208 , n14209 , n14210 ,
n14211 , n14212 , n14213 , n14214 , n14215 , n14216 , n14217 , n14218 , n14219 , n14220 ,
n14221 , n14222 , n14223 , n14224 , n14225 , n14226 , n14227 , n14228 , n14229 , n14230 ,
n14231 , n14232 , n14233 , n14234 , n14235 , n14236 , n14237 , n14238 , n14239 , n14240 ,
n14241 , n14242 , n14243 , n14244 , n14245 , n14246 , n14247 , n14248 , n14249 , n14250 ,
n14251 , n14252 , n14253 , n14254 , n14255 , n14256 , n14257 , n14258 , n14259 , n14260 ,
n14261 , n14262 , n14263 , n14264 , n14265 , n14266 , n14267 , n14268 , n14269 , n14270 ,
n14271 , n14272 , n14273 , n14274 , n14275 , n14276 , n14277 , n14278 , n14279 , n14280 ,
n14281 , n14282 , n14283 , n14284 , n14285 , n14286 , n14287 , n14288 , n14289 , n14290 ,
n14291 , n14292 , n14293 , n14294 , n14295 , n14296 , n14297 , n14298 , n14299 , n14300 ,
n14301 , n14302 , n14303 , n14304 , n14305 , n14306 , n14307 , n14308 , n14309 , n14310 ,
n14311 , n14312 , n14313 , n14314 , n14315 , n14316 , n14317 , n14318 , n14319 , n14320 ,
n14321 , n14322 , n14323 , n14324 , n14325 , n14326 , n14327 , n14328 , n14329 , n14330 ,
n14331 , n14332 , n14333 , n14334 , n14335 , n14336 , n14337 , n14338 , n14339 , n14340 ,
n14341 , n14342 , n14343 , n14344 , n14345 , n14346 , n14347 , n14348 , n14349 , n14350 ,
n14351 , n14352 , n14353 , n14354 , n14355 , n14356 , n14357 , n14358 , n14359 , n14360 ,
n14361 , n14362 , n14363 , n14364 , n14365 , n14366 , n14367 , n14368 , n14369 , n14370 ,
n14371 , n14372 , n14373 , n14374 , n14375 , n14376 , n14377 , n14378 , n14379 , n14380 ,
n14381 , n14382 , n14383 , n14384 , n14385 , n14386 , n14387 , n14388 , n14389 , n14390 ,
n14391 , n14392 , n14393 , n14394 , n14395 , n14396 , n14397 , n14398 , n14399 , n14400 ,
n14401 , n14402 , n14403 , n14404 , n14405 , n14406 , n14407 , n14408 , n14409 , n14410 ,
n14411 , n14412 , n14413 , n14414 , n14415 , n14416 , n14417 , n14418 , n14419 , n14420 ,
n14421 , n14422 , n14423 , n14424 , n14425 , n14426 , n14427 , n14428 , n14429 , n14430 ,
n14431 , n14432 , n14433 , n14434 , n14435 , n14436 , n14437 , n14438 , n14439 , n14440 ,
n14441 , n14442 , n14443 , n14444 , n14445 , n14446 , n14447 , n14448 , n14449 , n14450 ,
n14451 , n14452 , n14453 , n14454 , n14455 , n14456 , n14457 , n14458 , n14459 , n14460 ,
n14461 , n14462 , n14463 , n14464 , n14465 , n14466 , n14467 , n14468 , n14469 , n14470 ,
n14471 , n14472 , n14473 , n14474 , n14475 , n14476 , n14477 , n14478 , n14479 , n14480 ,
n14481 , n14482 , n14483 , n14484 , n14485 , n14486 , n14487 , n14488 , n14489 , n14490 ,
n14491 , n14492 , n14493 , n14494 , n14495 , n14496 , n14497 , n14498 , n14499 , n14500 ,
n14501 , n14502 , n14503 , n14504 , n14505 , n14506 , n14507 , n14508 , n14509 , n14510 ,
n14511 , n14512 , n14513 , n14514 , n14515 , n14516 , n14517 , n14518 , n14519 , n14520 ,
n14521 , n14522 , n14523 , n14524 , n14525 , n14526 , n14527 , n14528 , n14529 , n14530 ,
n14531 , n14532 , n14533 , n14534 , n14535 , n14536 , n14537 , n14538 , n14539 , n14540 ,
n14541 , n14542 , n14543 , n14544 , n14545 , n14546 , n14547 , n14548 , n14549 , n14550 ,
n14551 , n14552 , n14553 , n14554 , n14555 , n14556 , n14557 , n14558 , n14559 , n14560 ,
n14561 , n14562 , n14563 , n14564 , n14565 , n14566 , n14567 , n14568 , n14569 , n14570 ,
n14571 , n14572 , n14573 , n14574 , n14575 , n14576 , n14577 , n14578 , n14579 , n14580 ,
n14581 , n14582 , n14583 , n14584 , n14585 , n14586 , n14587 , n14588 , n14589 , n14590 ,
n14591 , n14592 , n14593 , n14594 , n14595 , n14596 , n14597 , n14598 , n14599 , n14600 ,
n14601 , n14602 , n14603 , n14604 , n14605 , n14606 , n14607 , n14608 , n14609 , n14610 ,
n14611 , n14612 , n14613 , n14614 , n14615 , n14616 , n14617 , n14618 , n14619 , n14620 ,
n14621 , n14622 , n14623 , n14624 , n14625 , n14626 , n14627 , n14628 , n14629 , n14630 ,
n14631 , n14632 , n14633 , n14634 , n14635 , n14636 , n14637 , n14638 , n14639 , n14640 ,
n14641 , n14642 , n14643 , n14644 , n14645 , n14646 , n14647 , n14648 , n14649 , n14650 ,
n14651 , n14652 , n14653 , n14654 , n14655 , n14656 , n14657 , n14658 , n14659 , n14660 ,
n14661 , n14662 , n14663 , n14664 , n14665 , n14666 , n14667 , n14668 , n14669 , n14670 ,
n14671 , n14672 , n14673 , n14674 , n14675 , n14676 , n14677 , n14678 , n14679 , n14680 ,
n14681 , n14682 , n14683 , n14684 , n14685 , n14686 , n14687 , n14688 , n14689 , n14690 ,
n14691 , n14692 , n14693 , n14694 , n14695 , n14696 , n14697 , n14698 , n14699 , n14700 ,
n14701 , n14702 , n14703 , n14704 , n14705 , n14706 , n14707 , n14708 , n14709 , n14710 ,
n14711 , n14712 , n14713 , n14714 , n14715 , n14716 , n14717 , n14718 , n14719 , n14720 ,
n14721 , n14722 , n14723 , n14724 , n14725 , n14726 , n14727 , n14728 , n14729 , n14730 ,
n14731 , n14732 , n14733 , n14734 , n14735 , n14736 , n14737 , n14738 , n14739 , n14740 ,
n14741 , n14742 , n14743 , n14744 , n14745 , n14746 , n14747 , n14748 , n14749 , n14750 ,
n14751 , n14752 , n14753 , n14754 , n14755 , n14756 , n14757 , n14758 , n14759 , n14760 ,
n14761 , n14762 , n14763 , n14764 , n14765 , n14766 , n14767 , n14768 , n14769 , n14770 ,
n14771 , n14772 , n14773 , n14774 , n14775 , n14776 , n14777 , n14778 , n14779 , n14780 ,
n14781 , n14782 , n14783 , n14784 , n14785 , n14786 , n14787 , n14788 , n14789 , n14790 ,
n14791 , n14792 , n14793 , n14794 , n14795 , n14796 , n14797 , n14798 , n14799 , n14800 ,
n14801 , n14802 , n14803 , n14804 , n14805 , n14806 , n14807 , n14808 , n14809 , n14810 ,
n14811 , n14812 , n14813 , n14814 , n14815 , n14816 , n14817 , n14818 , n14819 , n14820 ,
n14821 , n14822 , n14823 , n14824 , n14825 , n14826 , n14827 , n14828 , n14829 , n14830 ,
n14831 , n14832 , n14833 , n14834 , n14835 , n14836 , n14837 , n14838 , n14839 , n14840 ,
n14841 , n14842 , n14843 , n14844 , n14845 , n14846 , n14847 , n14848 , n14849 , n14850 ,
n14851 , n14852 , n14853 , n14854 , n14855 , n14856 , n14857 , n14858 , n14859 , n14860 ,
n14861 , n14862 , n14863 , n14864 , n14865 , n14866 , n14867 , n14868 , n14869 , n14870 ,
n14871 , n14872 , n14873 , n14874 , n14875 , n14876 , n14877 , n14878 , n14879 , n14880 ,
n14881 , n14882 , n14883 , n14884 , n14885 , n14886 , n14887 , n14888 , n14889 , n14890 ,
n14891 , n14892 , n14893 , n14894 , n14895 , n14896 , n14897 , n14898 , n14899 , n14900 ,
n14901 , n14902 , n14903 , n14904 , n14905 , n14906 , n14907 , n14908 , n14909 , n14910 ,
n14911 , n14912 , n14913 , n14914 , n14915 , n14916 , n14917 , n14918 , n14919 , n14920 ,
n14921 , n14922 , n14923 , n14924 , n14925 , n14926 , n14927 , n14928 , n14929 , n14930 ,
n14931 , n14932 , n14933 , n14934 , n14935 , n14936 , n14937 , n14938 , n14939 , n14940 ,
n14941 , n14942 , n14943 , n14944 , n14945 , n14946 , n14947 , n14948 , n14949 , n14950 ,
n14951 , n14952 , n14953 , n14954 , n14955 , n14956 , n14957 , n14958 , n14959 , n14960 ,
n14961 , n14962 , n14963 , n14964 , n14965 , n14966 , n14967 , n14968 , n14969 , n14970 ,
n14971 , n14972 , n14973 , n14974 , n14975 , n14976 , n14977 , n14978 , n14979 , n14980 ,
n14981 , n14982 , n14983 , n14984 , n14985 , n14986 , n14987 , n14988 , n14989 , n14990 ,
n14991 , n14992 , n14993 , n14994 , n14995 , n14996 , n14997 , n14998 , n14999 , n15000 ,
n15001 , n15002 , n15003 , n15004 , n15005 , n15006 , n15007 , n15008 , n15009 , n15010 ,
n15011 , n15012 , n15013 , n15014 , n15015 , n15016 , n15017 , n15018 , n15019 , n15020 ,
n15021 , n15022 , n15023 , n15024 , n15025 , n15026 , n15027 , n15028 , n15029 , n15030 ,
n15031 , n15032 , n15033 , n15034 , n15035 , n15036 , n15037 , n15038 , n15039 , n15040 ,
n15041 , n15042 , n15043 , n15044 , n15045 , n15046 , n15047 , n15048 , n15049 , n15050 ,
n15051 , n15052 , n15053 , n15054 , n15055 , n15056 , n15057 , n15058 , n15059 , n15060 ,
n15061 , n15062 , n15063 , n15064 , n15065 , n15066 , n15067 , n15068 , n15069 , n15070 ,
n15071 , n15072 , n15073 , n15074 , n15075 , n15076 , n15077 , n15078 , n15079 , n15080 ,
n15081 , n15082 , n15083 ;
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buf ( n6219 , n455 );
buf ( n6220 , n36 );
buf ( n6221 , n1843 );
buf ( n6222 , n439 );
buf ( n6223 , n1035 );
buf ( n6224 , n474 );
buf ( n6225 , n677 );
buf ( n6226 , n178 );
buf ( n6227 , n2003 );
buf ( n6228 , n1137 );
buf ( n6229 , n548 );
buf ( n6230 , n221 );
buf ( n6231 , n1272 );
buf ( n6232 , n142 );
buf ( n6233 , n924 );
buf ( n6234 , n264 );
buf ( n6235 , n1352 );
buf ( n6236 , n1201 );
buf ( n6237 , n1499 );
buf ( n6238 , n496 );
buf ( n6239 , n567 );
buf ( n6240 , n1427 );
buf ( n6241 , n941 );
buf ( n6242 , n750 );
buf ( n6243 , n1097 );
buf ( n6244 , n693 );
buf ( n6245 , n1076 );
buf ( n6246 , n230 );
buf ( n6247 , n1278 );
buf ( n6248 , n845 );
buf ( n6249 , n63 );
buf ( n6250 , n213 );
buf ( n6251 , n2128 );
buf ( n6252 , n2040 );
buf ( n6253 , n705 );
buf ( n6254 , n958 );
buf ( n6255 , n1400 );
buf ( n6256 , n854 );
buf ( n6257 , n313 );
buf ( n6258 , n856 );
buf ( n6259 , n689 );
buf ( n6260 , n923 );
buf ( n6261 , n1679 );
buf ( n6262 , n1842 );
buf ( n6263 , n2142 );
buf ( n6264 , n1112 );
buf ( n6265 , n412 );
buf ( n6266 , n1289 );
buf ( n6267 , n162 );
buf ( n6268 , n282 );
buf ( n6269 , n1409 );
buf ( n6270 , n229 );
buf ( n6271 , n1029 );
buf ( n6272 , n195 );
buf ( n6273 , n155 );
buf ( n6274 , n1514 );
buf ( n6275 , n1402 );
buf ( n6276 , n1724 );
buf ( n6277 , n659 );
buf ( n6278 , n406 );
buf ( n6279 , n633 );
buf ( n6280 , n2035 );
buf ( n6281 , n1206 );
buf ( n6282 , n909 );
buf ( n6283 , n561 );
buf ( n6284 , n1880 );
buf ( n6285 , n337 );
buf ( n6286 , n389 );
buf ( n6287 , n1504 );
buf ( n6288 , n1945 );
buf ( n6289 , n1786 );
buf ( n6290 , n122 );
buf ( n6291 , n479 );
buf ( n6292 , n1259 );
buf ( n6293 , n547 );
buf ( n6294 , n537 );
buf ( n6295 , n160 );
buf ( n6296 , n806 );
buf ( n6297 , n1051 );
buf ( n6298 , n1921 );
buf ( n6299 , n851 );
buf ( n6300 , n1552 );
buf ( n6301 , n986 );
buf ( n6302 , n232 );
buf ( n6303 , n203 );
buf ( n6304 , n1384 );
buf ( n6305 , n586 );
buf ( n6306 , n1512 );
buf ( n6307 , n939 );
buf ( n6308 , n672 );
buf ( n6309 , n1002 );
buf ( n6310 , n2077 );
buf ( n6311 , n1816 );
buf ( n6312 , n451 );
buf ( n6313 , n971 );
buf ( n6314 , n706 );
buf ( n6315 , n1300 );
buf ( n6316 , n207 );
buf ( n6317 , n1167 );
buf ( n6318 , n424 );
buf ( n6319 , n1932 );
buf ( n6320 , n251 );
buf ( n6321 , n673 );
buf ( n6322 , n860 );
buf ( n6323 , n1953 );
buf ( n6324 , n2121 );
buf ( n6325 , n1211 );
buf ( n6326 , n1421 );
buf ( n6327 , n701 );
buf ( n6328 , n1148 );
buf ( n6329 , n258 );
buf ( n6330 , n1857 );
buf ( n6331 , n1637 );
buf ( n6332 , n1055 );
buf ( n6333 , n1847 );
buf ( n6334 , n128 );
buf ( n6335 , n1463 );
buf ( n6336 , n928 );
buf ( n6337 , n25 );
buf ( n6338 , n1288 );
buf ( n6339 , n1793 );
buf ( n6340 , n468 );
buf ( n6341 , n132 );
buf ( n6342 , n817 );
buf ( n6343 , n726 );
buf ( n6344 , n921 );
buf ( n6345 , n49 );
buf ( n6346 , n1120 );
buf ( n6347 , n611 );
buf ( n6348 , n308 );
buf ( n6349 , n1313 );
buf ( n6350 , n210 );
buf ( n6351 , n1373 );
buf ( n6352 , n1714 );
buf ( n6353 , n1763 );
buf ( n6354 , n1795 );
buf ( n6355 , n919 );
buf ( n6356 , n830 );
buf ( n6357 , n70 );
buf ( n6358 , n831 );
buf ( n6359 , n915 );
buf ( n6360 , n1270 );
buf ( n6361 , n127 );
buf ( n6362 , n319 );
buf ( n6363 , n1082 );
buf ( n6364 , n1343 );
buf ( n6365 , n482 );
buf ( n6366 , n820 );
buf ( n6367 , n1551 );
buf ( n6368 , n197 );
buf ( n6369 , n769 );
buf ( n6370 , n1371 );
buf ( n6371 , n1668 );
buf ( n6372 , n1422 );
buf ( n6373 , n321 );
buf ( n6374 , n1592 );
buf ( n6375 , n1689 );
buf ( n6376 , n2081 );
buf ( n6377 , n1534 );
buf ( n6378 , n1756 );
buf ( n6379 , n51 );
buf ( n6380 , n948 );
buf ( n6381 , n1348 );
buf ( n6382 , n713 );
buf ( n6383 , n265 );
buf ( n6384 , n116 );
buf ( n6385 , n348 );
buf ( n6386 , n1363 );
buf ( n6387 , n1968 );
buf ( n6388 , n1286 );
buf ( n6389 , n427 );
buf ( n6390 , n442 );
buf ( n6391 , n815 );
buf ( n6392 , n1386 );
buf ( n6393 , n152 );
buf ( n6394 , n307 );
buf ( n6395 , n2111 );
buf ( n6396 , n374 );
buf ( n6397 , n390 );
buf ( n6398 , n2110 );
buf ( n6399 , n885 );
buf ( n6400 , n653 );
buf ( n6401 , n575 );
buf ( n6402 , n641 );
buf ( n6403 , n903 );
buf ( n6404 , n718 );
buf ( n6405 , n1768 );
buf ( n6406 , n1524 );
buf ( n6407 , n435 );
buf ( n6408 , n2032 );
buf ( n6409 , n935 );
buf ( n6410 , n1899 );
buf ( n6411 , n1379 );
buf ( n6412 , n1292 );
buf ( n6413 , n124 );
buf ( n6414 , n1350 );
buf ( n6415 , n149 );
buf ( n6416 , n1164 );
buf ( n6417 , n46 );
buf ( n6418 , n2056 );
buf ( n6419 , n1477 );
buf ( n6420 , n469 );
buf ( n6421 , n1834 );
buf ( n6422 , n109 );
buf ( n6423 , n1317 );
buf ( n6424 , n1810 );
buf ( n6425 , n1582 );
buf ( n6426 , n590 );
buf ( n6427 , n238 );
buf ( n6428 , n14 );
buf ( n6429 , n553 );
buf ( n6430 , n799 );
buf ( n6431 , n217 );
buf ( n6432 , n1767 );
buf ( n6433 , n1489 );
buf ( n6434 , n97 );
buf ( n6435 , n616 );
buf ( n6436 , n1715 );
buf ( n6437 , n271 );
buf ( n6438 , n1090 );
buf ( n6439 , n341 );
buf ( n6440 , n950 );
buf ( n6441 , n734 );
buf ( n6442 , n1929 );
buf ( n6443 , n457 );
buf ( n6444 , n168 );
buf ( n6445 , n967 );
buf ( n6446 , n1712 );
buf ( n6447 , n2113 );
buf ( n6448 , n283 );
buf ( n6449 , n1817 );
buf ( n6450 , n1098 );
buf ( n6451 , n1820 );
buf ( n6452 , n1150 );
buf ( n6453 , n896 );
buf ( n6454 , n576 );
buf ( n6455 , n102 );
buf ( n6456 , n1990 );
buf ( n6457 , n2010 );
buf ( n6458 , n772 );
buf ( n6459 , n311 );
buf ( n6460 , n1704 );
buf ( n6461 , n2102 );
buf ( n6462 , n314 );
buf ( n6463 , n2132 );
buf ( n6464 , n434 );
buf ( n6465 , n630 );
buf ( n6466 , n759 );
buf ( n6467 , n44 );
buf ( n6468 , n196 );
buf ( n6469 , n4324 );
not ( n6470 , n6469 );
buf ( n6471 , n4325 );
buf ( n6472 , n4326 );
not ( n6473 , n6471 );
and ( n6474 , n6472 , n6473 );
or ( n6475 , n6471 , n6474 );
not ( n6476 , n6475 );
buf ( n6477 , n4327 );
and ( n6478 , n6476 , n6477 );
buf ( n6479 , n4328 );
not ( n6480 , n6474 );
buf ( n6481 , n4329 );
and ( n6482 , n6480 , n6481 );
buf ( n6483 , n4330 );
xor ( n6484 , n6483 , n6481 );
and ( n6485 , n6484 , n6474 );
or ( n6486 , n6482 , n6485 );
not ( n6487 , n6474 );
buf ( n6488 , n4331 );
and ( n6489 , n6487 , n6488 );
buf ( n6490 , n4332 );
xor ( n6491 , n6490 , n6488 );
and ( n6492 , n6491 , n6474 );
or ( n6493 , n6489 , n6492 );
xor ( n6494 , n6486 , n6493 );
buf ( n6495 , n4333 );
xor ( n6496 , n6494 , n6495 );
buf ( n6497 , n4334 );
xor ( n6498 , n6496 , n6497 );
buf ( n6499 , n4335 );
xor ( n6500 , n6498 , n6499 );
xor ( n6501 , n6479 , n6500 );
not ( n6502 , n6474 );
buf ( n6503 , n4336 );
and ( n6504 , n6502 , n6503 );
buf ( n6505 , n4337 );
xor ( n6506 , n6505 , n6503 );
and ( n6507 , n6506 , n6474 );
or ( n6508 , n6504 , n6507 );
buf ( n6509 , n4338 );
xor ( n6510 , n6508 , n6509 );
buf ( n6511 , n4339 );
xor ( n6512 , n6510 , n6511 );
buf ( n6513 , n4340 );
xor ( n6514 , n6512 , n6513 );
buf ( n6515 , n4341 );
xor ( n6516 , n6514 , n6515 );
xor ( n6517 , n6501 , n6516 );
buf ( n6518 , n4342 );
not ( n6519 , n6474 );
not ( n6520 , n4343 );
buf ( n6521 , n6520 );
and ( n6522 , n6519 , n6521 );
buf ( n6523 , n6474 );
or ( n6524 , n6522 , n6523 );
not ( n6525 , n6474 );
buf ( n6526 , n4344 );
and ( n6527 , n6525 , n6526 );
buf ( n6528 , n4345 );
xor ( n6529 , n6528 , n6526 );
and ( n6530 , n6529 , n6474 );
or ( n6531 , n6527 , n6530 );
xor ( n6532 , n6524 , n6531 );
buf ( n6533 , n4346 );
xor ( n6534 , n6532 , n6533 );
buf ( n6535 , n4347 );
xor ( n6536 , n6534 , n6535 );
buf ( n6537 , n4348 );
xor ( n6538 , n6536 , n6537 );
xor ( n6539 , n6518 , n6538 );
not ( n6540 , n6474 );
buf ( n6541 , n4349 );
and ( n6542 , n6540 , n6541 );
buf ( n6543 , n4350 );
xor ( n6544 , n6543 , n6541 );
and ( n6545 , n6544 , n6474 );
or ( n6546 , n6542 , n6545 );
not ( n6547 , n6474 );
buf ( n6548 , n4351 );
and ( n6549 , n6547 , n6548 );
buf ( n6550 , n4352 );
xor ( n6551 , n6550 , n6548 );
and ( n6552 , n6551 , n6474 );
or ( n6553 , n6549 , n6552 );
xor ( n6554 , n6546 , n6553 );
buf ( n6555 , n4353 );
xor ( n6556 , n6554 , n6555 );
buf ( n6557 , n4354 );
xor ( n6558 , n6556 , n6557 );
buf ( n6559 , n4355 );
xor ( n6560 , n6558 , n6559 );
xor ( n6561 , n6539 , n6560 );
not ( n6562 , n6561 );
not ( n6563 , n6474 );
buf ( n6564 , n4356 );
and ( n6565 , n6563 , n6564 );
buf ( n6566 , n4357 );
xor ( n6567 , n6566 , n6564 );
and ( n6568 , n6567 , n6474 );
or ( n6569 , n6565 , n6568 );
not ( n6570 , n6474 );
buf ( n6571 , n4358 );
and ( n6572 , n6570 , n6571 );
buf ( n6573 , n4359 );
xor ( n6574 , n6573 , n6571 );
and ( n6575 , n6574 , n6474 );
or ( n6576 , n6572 , n6575 );
buf ( n6577 , n4360 );
xor ( n6578 , n6576 , n6577 );
buf ( n6579 , n4361 );
xor ( n6580 , n6578 , n6579 );
buf ( n6581 , n4362 );
xor ( n6582 , n6580 , n6581 );
buf ( n6583 , n4363 );
xor ( n6584 , n6582 , n6583 );
xor ( n6585 , n6569 , n6584 );
not ( n6586 , n6474 );
buf ( n6587 , n4364 );
and ( n6588 , n6586 , n6587 );
buf ( n6589 , n4365 );
xor ( n6590 , n6589 , n6587 );
and ( n6591 , n6590 , n6474 );
or ( n6592 , n6588 , n6591 );
not ( n6593 , n6474 );
buf ( n6594 , n4366 );
and ( n6595 , n6593 , n6594 );
buf ( n6596 , n4367 );
xor ( n6597 , n6596 , n6594 );
and ( n6598 , n6597 , n6474 );
or ( n6599 , n6595 , n6598 );
xor ( n6600 , n6592 , n6599 );
buf ( n6601 , n4368 );
xor ( n6602 , n6600 , n6601 );
buf ( n6603 , n4369 );
xor ( n6604 , n6602 , n6603 );
buf ( n6605 , n4370 );
xor ( n6606 , n6604 , n6605 );
xor ( n6607 , n6585 , n6606 );
and ( n6608 , n6562 , n6607 );
xor ( n6609 , n6517 , n6608 );
buf ( n6610 , n4371 );
not ( n6611 , n6474 );
buf ( n6612 , n4372 );
and ( n6613 , n6611 , n6612 );
buf ( n6614 , n4373 );
xor ( n6615 , n6614 , n6612 );
and ( n6616 , n6615 , n6474 );
or ( n6617 , n6613 , n6616 );
not ( n6618 , n6474 );
buf ( n6619 , n4374 );
and ( n6620 , n6618 , n6619 );
buf ( n6621 , n4375 );
xor ( n6622 , n6621 , n6619 );
and ( n6623 , n6622 , n6474 );
or ( n6624 , n6620 , n6623 );
xor ( n6625 , n6617 , n6624 );
buf ( n6626 , n4376 );
xor ( n6627 , n6625 , n6626 );
buf ( n6628 , n4377 );
xor ( n6629 , n6627 , n6628 );
buf ( n6630 , n4378 );
xor ( n6631 , n6629 , n6630 );
xor ( n6632 , n6610 , n6631 );
not ( n6633 , n6474 );
buf ( n6634 , n4379 );
and ( n6635 , n6633 , n6634 );
buf ( n6636 , n4380 );
xor ( n6637 , n6636 , n6634 );
and ( n6638 , n6637 , n6474 );
or ( n6639 , n6635 , n6638 );
not ( n6640 , n6474 );
buf ( n6641 , n4381 );
and ( n6642 , n6640 , n6641 );
buf ( n6643 , n4382 );
xor ( n6644 , n6643 , n6641 );
and ( n6645 , n6644 , n6474 );
or ( n6646 , n6642 , n6645 );
xor ( n6647 , n6639 , n6646 );
buf ( n6648 , n4383 );
xor ( n6649 , n6647 , n6648 );
buf ( n6650 , n4384 );
xor ( n6651 , n6649 , n6650 );
buf ( n6652 , n4385 );
xor ( n6653 , n6651 , n6652 );
xor ( n6654 , n6632 , n6653 );
not ( n6655 , n6517 );
and ( n6656 , n6655 , n6561 );
xor ( n6657 , n6654 , n6656 );
buf ( n6658 , n4386 );
not ( n6659 , n6474 );
buf ( n6660 , n4387 );
and ( n6661 , n6659 , n6660 );
buf ( n6662 , n4388 );
xor ( n6663 , n6662 , n6660 );
and ( n6664 , n6663 , n6474 );
or ( n6665 , n6661 , n6664 );
buf ( n6666 , n4389 );
xor ( n6667 , n6665 , n6666 );
buf ( n6668 , n4390 );
xor ( n6669 , n6667 , n6668 );
buf ( n6670 , n4391 );
xor ( n6671 , n6669 , n6670 );
buf ( n6672 , n4392 );
xor ( n6673 , n6671 , n6672 );
xor ( n6674 , n6658 , n6673 );
not ( n6675 , n6474 );
buf ( n6676 , n4393 );
and ( n6677 , n6675 , n6676 );
buf ( n6678 , n4394 );
xor ( n6679 , n6678 , n6676 );
and ( n6680 , n6679 , n6474 );
or ( n6681 , n6677 , n6680 );
not ( n6682 , n6474 );
buf ( n6683 , n4395 );
and ( n6684 , n6682 , n6683 );
buf ( n6685 , n4396 );
xor ( n6686 , n6685 , n6683 );
and ( n6687 , n6686 , n6474 );
or ( n6688 , n6684 , n6687 );
xor ( n6689 , n6681 , n6688 );
buf ( n6690 , n4397 );
xor ( n6691 , n6689 , n6690 );
buf ( n6692 , n4398 );
xor ( n6693 , n6691 , n6692 );
buf ( n6694 , n4399 );
xor ( n6695 , n6693 , n6694 );
xor ( n6696 , n6674 , n6695 );
buf ( n6697 , n4400 );
not ( n6698 , n6474 );
buf ( n6699 , n4401 );
and ( n6700 , n6698 , n6699 );
buf ( n6701 , n6699 );
and ( n6702 , n6701 , n6474 );
or ( n6703 , n6700 , n6702 );
not ( n6704 , n6474 );
buf ( n6705 , n4402 );
and ( n6706 , n6704 , n6705 );
buf ( n6707 , n4403 );
xor ( n6708 , n6707 , n6705 );
and ( n6709 , n6708 , n6474 );
or ( n6710 , n6706 , n6709 );
xor ( n6711 , n6703 , n6710 );
buf ( n6712 , n4404 );
xor ( n6713 , n6711 , n6712 );
buf ( n6714 , n4405 );
xor ( n6715 , n6713 , n6714 );
buf ( n6716 , n4406 );
xor ( n6717 , n6715 , n6716 );
xor ( n6718 , n6697 , n6717 );
not ( n6719 , n6474 );
buf ( n6720 , n4407 );
and ( n6721 , n6719 , n6720 );
buf ( n6722 , n4408 );
xor ( n6723 , n6722 , n6720 );
and ( n6724 , n6723 , n6474 );
or ( n6725 , n6721 , n6724 );
not ( n6726 , n6474 );
buf ( n6727 , n4409 );
and ( n6728 , n6726 , n6727 );
buf ( n6729 , n4410 );
xor ( n6730 , n6729 , n6727 );
and ( n6731 , n6730 , n6474 );
or ( n6732 , n6728 , n6731 );
xor ( n6733 , n6725 , n6732 );
buf ( n6734 , n4411 );
xor ( n6735 , n6733 , n6734 );
buf ( n6736 , n4412 );
xor ( n6737 , n6735 , n6736 );
buf ( n6738 , n4413 );
xor ( n6739 , n6737 , n6738 );
xor ( n6740 , n6718 , n6739 );
not ( n6741 , n6740 );
buf ( n6742 , n4414 );
not ( n6743 , n6474 );
buf ( n6744 , n4415 );
and ( n6745 , n6743 , n6744 );
buf ( n6746 , n4416 );
xor ( n6747 , n6746 , n6744 );
and ( n6748 , n6747 , n6474 );
or ( n6749 , n6745 , n6748 );
not ( n6750 , n6474 );
buf ( n6751 , n4417 );
and ( n6752 , n6750 , n6751 );
buf ( n6753 , n4418 );
xor ( n6754 , n6753 , n6751 );
and ( n6755 , n6754 , n6474 );
or ( n6756 , n6752 , n6755 );
xor ( n6757 , n6749 , n6756 );
buf ( n6758 , n4419 );
xor ( n6759 , n6757 , n6758 );
buf ( n6760 , n4420 );
xor ( n6761 , n6759 , n6760 );
buf ( n6762 , n4421 );
xor ( n6763 , n6761 , n6762 );
xor ( n6764 , n6742 , n6763 );
not ( n6765 , n6474 );
buf ( n6766 , n4422 );
and ( n6767 , n6765 , n6766 );
buf ( n6768 , n4423 );
xor ( n6769 , n6768 , n6766 );
and ( n6770 , n6769 , n6474 );
or ( n6771 , n6767 , n6770 );
not ( n6772 , n6474 );
buf ( n6773 , n4424 );
and ( n6774 , n6772 , n6773 );
buf ( n6775 , n4425 );
xor ( n6776 , n6775 , n6773 );
and ( n6777 , n6776 , n6474 );
or ( n6778 , n6774 , n6777 );
xor ( n6779 , n6771 , n6778 );
buf ( n6780 , n4426 );
xor ( n6781 , n6779 , n6780 );
buf ( n6782 , n4427 );
xor ( n6783 , n6781 , n6782 );
buf ( n6784 , n4428 );
xor ( n6785 , n6783 , n6784 );
xor ( n6786 , n6764 , n6785 );
and ( n6787 , n6741 , n6786 );
xor ( n6788 , n6696 , n6787 );
xor ( n6789 , n6657 , n6788 );
buf ( n6790 , n4429 );
not ( n6791 , n6474 );
buf ( n6792 , n4430 );
and ( n6793 , n6791 , n6792 );
buf ( n6794 , n4431 );
xor ( n6795 , n6794 , n6792 );
and ( n6796 , n6795 , n6474 );
or ( n6797 , n6793 , n6796 );
not ( n6798 , n6474 );
buf ( n6799 , n4432 );
and ( n6800 , n6798 , n6799 );
buf ( n6801 , n4433 );
xor ( n6802 , n6801 , n6799 );
and ( n6803 , n6802 , n6474 );
or ( n6804 , n6800 , n6803 );
xor ( n6805 , n6797 , n6804 );
buf ( n6806 , n4434 );
xor ( n6807 , n6805 , n6806 );
buf ( n6808 , n4435 );
xor ( n6809 , n6807 , n6808 );
buf ( n6810 , n4436 );
xor ( n6811 , n6809 , n6810 );
xor ( n6812 , n6790 , n6811 );
not ( n6813 , n6474 );
buf ( n6814 , n4437 );
and ( n6815 , n6813 , n6814 );
buf ( n6816 , n4438 );
xor ( n6817 , n6816 , n6814 );
and ( n6818 , n6817 , n6474 );
or ( n6819 , n6815 , n6818 );
buf ( n6820 , n4439 );
xor ( n6821 , n6819 , n6820 );
buf ( n6822 , n4440 );
xor ( n6823 , n6821 , n6822 );
buf ( n6824 , n4441 );
xor ( n6825 , n6823 , n6824 );
buf ( n6826 , n4442 );
xor ( n6827 , n6825 , n6826 );
xor ( n6828 , n6812 , n6827 );
buf ( n6829 , n4443 );
not ( n6830 , n6474 );
buf ( n6831 , n4444 );
and ( n6832 , n6830 , n6831 );
buf ( n6833 , n4445 );
xor ( n6834 , n6833 , n6831 );
and ( n6835 , n6834 , n6474 );
or ( n6836 , n6832 , n6835 );
not ( n6837 , n6474 );
buf ( n6838 , n4446 );
and ( n6839 , n6837 , n6838 );
buf ( n6840 , n4447 );
xor ( n6841 , n6840 , n6838 );
and ( n6842 , n6841 , n6474 );
or ( n6843 , n6839 , n6842 );
xor ( n6844 , n6836 , n6843 );
buf ( n6845 , n4448 );
xor ( n6846 , n6844 , n6845 );
buf ( n6847 , n4449 );
xor ( n6848 , n6846 , n6847 );
buf ( n6849 , n4450 );
xor ( n6850 , n6848 , n6849 );
xor ( n6851 , n6829 , n6850 );
not ( n6852 , n6474 );
buf ( n6853 , n4451 );
and ( n6854 , n6852 , n6853 );
buf ( n6855 , n4452 );
xor ( n6856 , n6855 , n6853 );
and ( n6857 , n6856 , n6474 );
or ( n6858 , n6854 , n6857 );
not ( n6859 , n6474 );
buf ( n6860 , n4453 );
and ( n6861 , n6859 , n6860 );
buf ( n6862 , n4454 );
xor ( n6863 , n6862 , n6860 );
and ( n6864 , n6863 , n6474 );
or ( n6865 , n6861 , n6864 );
xor ( n6866 , n6858 , n6865 );
buf ( n6867 , n4455 );
xor ( n6868 , n6866 , n6867 );
buf ( n6869 , n4456 );
xor ( n6870 , n6868 , n6869 );
buf ( n6871 , n4457 );
xor ( n6872 , n6870 , n6871 );
xor ( n6873 , n6851 , n6872 );
not ( n6874 , n6873 );
buf ( n6875 , n4458 );
not ( n6876 , n6474 );
buf ( n6877 , n4459 );
and ( n6878 , n6876 , n6877 );
buf ( n6879 , n4460 );
xor ( n6880 , n6879 , n6877 );
and ( n6881 , n6880 , n6474 );
or ( n6882 , n6878 , n6881 );
buf ( n6883 , n4461 );
xor ( n6884 , n6882 , n6883 );
buf ( n6885 , n4462 );
xor ( n6886 , n6884 , n6885 );
buf ( n6887 , n4463 );
buf ( n6888 , n6887 );
xor ( n6889 , n6886 , n6888 );
buf ( n6890 , n4464 );
xor ( n6891 , n6889 , n6890 );
xor ( n6892 , n6875 , n6891 );
not ( n6893 , n6474 );
buf ( n6894 , n4465 );
and ( n6895 , n6893 , n6894 );
buf ( n6896 , n4466 );
xor ( n6897 , n6896 , n6894 );
and ( n6898 , n6897 , n6474 );
or ( n6899 , n6895 , n6898 );
not ( n6900 , n6474 );
buf ( n6901 , n4467 );
and ( n6902 , n6900 , n6901 );
buf ( n6903 , n4468 );
xor ( n6904 , n6903 , n6901 );
and ( n6905 , n6904 , n6474 );
or ( n6906 , n6902 , n6905 );
xor ( n6907 , n6899 , n6906 );
buf ( n6908 , n4469 );
xor ( n6909 , n6907 , n6908 );
buf ( n6910 , n4470 );
xor ( n6911 , n6909 , n6910 );
buf ( n6912 , n4471 );
xor ( n6913 , n6911 , n6912 );
xor ( n6914 , n6892 , n6913 );
and ( n6915 , n6874 , n6914 );
xor ( n6916 , n6828 , n6915 );
xor ( n6917 , n6789 , n6916 );
buf ( n6918 , n4472 );
not ( n6919 , n6474 );
buf ( n6920 , n4473 );
and ( n6921 , n6919 , n6920 );
buf ( n6922 , n4474 );
xor ( n6923 , n6922 , n6920 );
and ( n6924 , n6923 , n6474 );
or ( n6925 , n6921 , n6924 );
not ( n6926 , n6474 );
buf ( n6927 , n4475 );
and ( n6928 , n6926 , n6927 );
buf ( n6929 , n4476 );
xor ( n6930 , n6929 , n6927 );
and ( n6931 , n6930 , n6474 );
or ( n6932 , n6928 , n6931 );
xor ( n6933 , n6925 , n6932 );
buf ( n6934 , n4477 );
xor ( n6935 , n6933 , n6934 );
buf ( n6936 , n4478 );
xor ( n6937 , n6935 , n6936 );
buf ( n6938 , n4479 );
xor ( n6939 , n6937 , n6938 );
xor ( n6940 , n6918 , n6939 );
not ( n6941 , n6474 );
buf ( n6942 , n4480 );
and ( n6943 , n6941 , n6942 );
buf ( n6944 , n4481 );
xor ( n6945 , n6944 , n6942 );
and ( n6946 , n6945 , n6474 );
or ( n6947 , n6943 , n6946 );
not ( n6948 , n6474 );
buf ( n6949 , n4482 );
and ( n6950 , n6948 , n6949 );
buf ( n6951 , n4483 );
xor ( n6952 , n6951 , n6949 );
and ( n6953 , n6952 , n6474 );
or ( n6954 , n6950 , n6953 );
xor ( n6955 , n6947 , n6954 );
buf ( n6956 , n4484 );
xor ( n6957 , n6955 , n6956 );
buf ( n6958 , n4485 );
xor ( n6959 , n6957 , n6958 );
buf ( n6960 , n4486 );
xor ( n6961 , n6959 , n6960 );
xor ( n6962 , n6940 , n6961 );
buf ( n6963 , n4487 );
not ( n6964 , n6474 );
buf ( n6965 , n4488 );
and ( n6966 , n6964 , n6965 );
buf ( n6967 , n4489 );
xor ( n6968 , n6967 , n6965 );
and ( n6969 , n6968 , n6474 );
or ( n6970 , n6966 , n6969 );
not ( n6971 , n6474 );
buf ( n6972 , n4490 );
and ( n6973 , n6971 , n6972 );
buf ( n6974 , n4491 );
xor ( n6975 , n6974 , n6972 );
and ( n6976 , n6975 , n6474 );
or ( n6977 , n6973 , n6976 );
xor ( n6978 , n6970 , n6977 );
buf ( n6979 , n4492 );
xor ( n6980 , n6978 , n6979 );
buf ( n6981 , n4493 );
xor ( n6982 , n6980 , n6981 );
buf ( n6983 , n4494 );
xor ( n6984 , n6982 , n6983 );
xor ( n6985 , n6963 , n6984 );
not ( n6986 , n6474 );
buf ( n6987 , n4495 );
and ( n6988 , n6986 , n6987 );
buf ( n6989 , n4496 );
xor ( n6990 , n6989 , n6987 );
and ( n6991 , n6990 , n6474 );
or ( n6992 , n6988 , n6991 );
not ( n6993 , n6474 );
buf ( n6994 , n4497 );
and ( n6995 , n6993 , n6994 );
buf ( n6996 , n4498 );
xor ( n6997 , n6996 , n6994 );
and ( n6998 , n6997 , n6474 );
or ( n6999 , n6995 , n6998 );
xor ( n7000 , n6992 , n6999 );
buf ( n7001 , n4499 );
xor ( n7002 , n7000 , n7001 );
buf ( n7003 , n4500 );
xor ( n7004 , n7002 , n7003 );
buf ( n7005 , n4501 );
xor ( n7006 , n7004 , n7005 );
xor ( n7007 , n6985 , n7006 );
not ( n7008 , n7007 );
buf ( n7009 , n4502 );
not ( n7010 , n6474 );
buf ( n7011 , n4503 );
and ( n7012 , n7010 , n7011 );
buf ( n7013 , n4504 );
xor ( n7014 , n7013 , n7011 );
and ( n7015 , n7014 , n6474 );
or ( n7016 , n7012 , n7015 );
not ( n7017 , n6474 );
buf ( n7018 , n4505 );
and ( n7019 , n7017 , n7018 );
buf ( n7020 , n4506 );
xor ( n7021 , n7020 , n7018 );
and ( n7022 , n7021 , n6474 );
or ( n7023 , n7019 , n7022 );
xor ( n7024 , n7016 , n7023 );
buf ( n7025 , n4507 );
xor ( n7026 , n7024 , n7025 );
buf ( n7027 , n4508 );
xor ( n7028 , n7026 , n7027 );
buf ( n7029 , n4509 );
xor ( n7030 , n7028 , n7029 );
xor ( n7031 , n7009 , n7030 );
not ( n7032 , n6474 );
buf ( n7033 , n4510 );
and ( n7034 , n7032 , n7033 );
buf ( n7035 , n4511 );
xor ( n7036 , n7035 , n7033 );
and ( n7037 , n7036 , n6474 );
or ( n7038 , n7034 , n7037 );
buf ( n7039 , n4512 );
xor ( n7040 , n7038 , n7039 );
buf ( n7041 , n4513 );
xor ( n7042 , n7040 , n7041 );
buf ( n7043 , n4514 );
xor ( n7044 , n7042 , n7043 );
buf ( n7045 , n4515 );
xor ( n7046 , n7044 , n7045 );
xor ( n7047 , n7031 , n7046 );
and ( n7048 , n7008 , n7047 );
xor ( n7049 , n6962 , n7048 );
xor ( n7050 , n6917 , n7049 );
buf ( n7051 , n4516 );
not ( n7052 , n6474 );
buf ( n7053 , n4517 );
and ( n7054 , n7052 , n7053 );
buf ( n7055 , n4518 );
xor ( n7056 , n7055 , n7053 );
and ( n7057 , n7056 , n6474 );
or ( n7058 , n7054 , n7057 );
not ( n7059 , n6474 );
buf ( n7060 , n4519 );
and ( n7061 , n7059 , n7060 );
buf ( n7062 , n4520 );
xor ( n7063 , n7062 , n7060 );
and ( n7064 , n7063 , n6474 );
or ( n7065 , n7061 , n7064 );
xor ( n7066 , n7058 , n7065 );
buf ( n7067 , n4521 );
xor ( n7068 , n7066 , n7067 );
buf ( n7069 , n4522 );
xor ( n7070 , n7068 , n7069 );
buf ( n7071 , n4523 );
xor ( n7072 , n7070 , n7071 );
xor ( n7073 , n7051 , n7072 );
not ( n7074 , n6474 );
buf ( n7075 , n4524 );
and ( n7076 , n7074 , n7075 );
buf ( n7077 , n4525 );
xor ( n7078 , n7077 , n7075 );
and ( n7079 , n7078 , n6474 );
or ( n7080 , n7076 , n7079 );
not ( n7081 , n6474 );
buf ( n7082 , n4526 );
and ( n7083 , n7081 , n7082 );
buf ( n7084 , n4527 );
xor ( n7085 , n7084 , n7082 );
and ( n7086 , n7085 , n6474 );
or ( n7087 , n7083 , n7086 );
xor ( n7088 , n7080 , n7087 );
buf ( n7089 , n4528 );
xor ( n7090 , n7088 , n7089 );
buf ( n7091 , n4529 );
buf ( n7092 , n7091 );
xor ( n7093 , n7090 , n7092 );
buf ( n7094 , n4530 );
xor ( n7095 , n7093 , n7094 );
xor ( n7096 , n7073 , n7095 );
buf ( n7097 , n4531 );
not ( n7098 , n6474 );
buf ( n7099 , n4532 );
and ( n7100 , n7098 , n7099 );
buf ( n7101 , n4533 );
xor ( n7102 , n7101 , n7099 );
and ( n7103 , n7102 , n6474 );
or ( n7104 , n7100 , n7103 );
buf ( n7105 , n4534 );
xor ( n7106 , n7104 , n7105 );
buf ( n7107 , n4535 );
xor ( n7108 , n7106 , n7107 );
buf ( n7109 , n4536 );
xor ( n7110 , n7108 , n7109 );
buf ( n7111 , n4537 );
xor ( n7112 , n7110 , n7111 );
xor ( n7113 , n7097 , n7112 );
not ( n7114 , n6474 );
buf ( n7115 , n4538 );
and ( n7116 , n7114 , n7115 );
buf ( n7117 , n4539 );
xor ( n7118 , n7117 , n7115 );
and ( n7119 , n7118 , n6474 );
or ( n7120 , n7116 , n7119 );
not ( n7121 , n6474 );
buf ( n7122 , n4540 );
and ( n7123 , n7121 , n7122 );
buf ( n7124 , n4541 );
xor ( n7125 , n7124 , n7122 );
and ( n7126 , n7125 , n6474 );
or ( n7127 , n7123 , n7126 );
xor ( n7128 , n7120 , n7127 );
buf ( n7129 , n4542 );
xor ( n7130 , n7128 , n7129 );
buf ( n7131 , n4543 );
xor ( n7132 , n7130 , n7131 );
buf ( n7133 , n4544 );
xor ( n7134 , n7132 , n7133 );
xor ( n7135 , n7113 , n7134 );
not ( n7136 , n7135 );
buf ( n7137 , n4545 );
not ( n7138 , n6474 );
buf ( n7139 , n4546 );
and ( n7140 , n7138 , n7139 );
buf ( n7141 , n4547 );
xor ( n7142 , n7141 , n7139 );
and ( n7143 , n7142 , n6474 );
or ( n7144 , n7140 , n7143 );
not ( n7145 , n6474 );
buf ( n7146 , n4548 );
and ( n7147 , n7145 , n7146 );
buf ( n7148 , n4549 );
xor ( n7149 , n7148 , n7146 );
and ( n7150 , n7149 , n6474 );
or ( n7151 , n7147 , n7150 );
xor ( n7152 , n7144 , n7151 );
buf ( n7153 , n4550 );
xor ( n7154 , n7152 , n7153 );
buf ( n7155 , n4551 );
xor ( n7156 , n7154 , n7155 );
buf ( n7157 , n4552 );
buf ( n7158 , n7157 );
xor ( n7159 , n7156 , n7158 );
xor ( n7160 , n7137 , n7159 );
not ( n7161 , n6474 );
buf ( n7162 , n4553 );
and ( n7163 , n7161 , n7162 );
buf ( n7164 , n4554 );
xor ( n7165 , n7164 , n7162 );
and ( n7166 , n7165 , n6474 );
or ( n7167 , n7163 , n7166 );
not ( n7168 , n6474 );
buf ( n7169 , n4555 );
and ( n7170 , n7168 , n7169 );
buf ( n7171 , n4556 );
xor ( n7172 , n7171 , n7169 );
and ( n7173 , n7172 , n6474 );
or ( n7174 , n7170 , n7173 );
xor ( n7175 , n7167 , n7174 );
buf ( n7176 , n4557 );
xor ( n7177 , n7175 , n7176 );
buf ( n7178 , n4558 );
xor ( n7179 , n7177 , n7178 );
buf ( n7180 , n4559 );
xor ( n7181 , n7179 , n7180 );
xor ( n7182 , n7160 , n7181 );
and ( n7183 , n7136 , n7182 );
xor ( n7184 , n7096 , n7183 );
xor ( n7185 , n7050 , n7184 );
xor ( n7186 , n6609 , n7185 );
buf ( n7187 , n4560 );
not ( n7188 , n6474 );
buf ( n7189 , n4561 );
and ( n7190 , n7188 , n7189 );
buf ( n7191 , n4562 );
xor ( n7192 , n7191 , n7189 );
and ( n7193 , n7192 , n6474 );
or ( n7194 , n7190 , n7193 );
not ( n7195 , n6474 );
buf ( n7196 , n4563 );
and ( n7197 , n7195 , n7196 );
buf ( n7198 , n4564 );
xor ( n7199 , n7198 , n7196 );
and ( n7200 , n7199 , n6474 );
or ( n7201 , n7197 , n7200 );
xor ( n7202 , n7194 , n7201 );
buf ( n7203 , n4565 );
xor ( n7204 , n7202 , n7203 );
buf ( n7205 , n4566 );
xor ( n7206 , n7204 , n7205 );
buf ( n7207 , n4567 );
xor ( n7208 , n7206 , n7207 );
xor ( n7209 , n7187 , n7208 );
not ( n7210 , n6474 );
buf ( n7211 , n4568 );
and ( n7212 , n7210 , n7211 );
buf ( n7213 , n4569 );
xor ( n7214 , n7213 , n7211 );
and ( n7215 , n7214 , n6474 );
or ( n7216 , n7212 , n7215 );
not ( n7217 , n6474 );
buf ( n7218 , n4570 );
and ( n7219 , n7217 , n7218 );
buf ( n7220 , n4571 );
xor ( n7221 , n7220 , n7218 );
and ( n7222 , n7221 , n6474 );
or ( n7223 , n7219 , n7222 );
xor ( n7224 , n7216 , n7223 );
buf ( n7225 , n4572 );
xor ( n7226 , n7224 , n7225 );
buf ( n7227 , n4573 );
xor ( n7228 , n7226 , n7227 );
buf ( n7229 , n4574 );
xor ( n7230 , n7228 , n7229 );
xor ( n7231 , n7209 , n7230 );
not ( n7232 , n6474 );
buf ( n7233 , n4575 );
and ( n7234 , n7232 , n7233 );
buf ( n7235 , n4576 );
xor ( n7236 , n7235 , n7233 );
and ( n7237 , n7236 , n6474 );
or ( n7238 , n7234 , n7237 );
not ( n7239 , n6474 );
buf ( n7240 , n4577 );
and ( n7241 , n7239 , n7240 );
buf ( n7242 , n4578 );
xor ( n7243 , n7242 , n7240 );
and ( n7244 , n7243 , n6474 );
or ( n7245 , n7241 , n7244 );
buf ( n7246 , n4579 );
xor ( n7247 , n7245 , n7246 );
buf ( n7248 , n4580 );
xor ( n7249 , n7247 , n7248 );
buf ( n7250 , n4581 );
xor ( n7251 , n7249 , n7250 );
buf ( n7252 , n4582 );
xor ( n7253 , n7251 , n7252 );
xor ( n7254 , n7238 , n7253 );
not ( n7255 , n6474 );
buf ( n7256 , n4583 );
and ( n7257 , n7255 , n7256 );
buf ( n7258 , n4584 );
xor ( n7259 , n7258 , n7256 );
and ( n7260 , n7259 , n6474 );
or ( n7261 , n7257 , n7260 );
not ( n7262 , n6474 );
buf ( n7263 , n4585 );
and ( n7264 , n7262 , n7263 );
buf ( n7265 , n4586 );
xor ( n7266 , n7265 , n7263 );
and ( n7267 , n7266 , n6474 );
or ( n7268 , n7264 , n7267 );
xor ( n7269 , n7261 , n7268 );
buf ( n7270 , n4587 );
xor ( n7271 , n7269 , n7270 );
buf ( n7272 , n4588 );
xor ( n7273 , n7271 , n7272 );
xor ( n7274 , n7273 , n7137 );
xor ( n7275 , n7254 , n7274 );
not ( n7276 , n7275 );
not ( n7277 , n6474 );
buf ( n7278 , n4589 );
and ( n7279 , n7277 , n7278 );
buf ( n7280 , n4590 );
xor ( n7281 , n7280 , n7278 );
and ( n7282 , n7281 , n6474 );
or ( n7283 , n7279 , n7282 );
xor ( n7284 , n7283 , n6717 );
xor ( n7285 , n7284 , n6739 );
and ( n7286 , n7276 , n7285 );
xor ( n7287 , n7231 , n7286 );
buf ( n7288 , n4591 );
not ( n7289 , n6474 );
buf ( n7290 , n4592 );
and ( n7291 , n7289 , n7290 );
buf ( n7292 , n4593 );
xor ( n7293 , n7292 , n7290 );
and ( n7294 , n7293 , n6474 );
or ( n7295 , n7291 , n7294 );
not ( n7296 , n6474 );
buf ( n7297 , n4594 );
and ( n7298 , n7296 , n7297 );
buf ( n7299 , n4595 );
xor ( n7300 , n7299 , n7297 );
and ( n7301 , n7300 , n6474 );
or ( n7302 , n7298 , n7301 );
xor ( n7303 , n7295 , n7302 );
buf ( n7304 , n4596 );
xor ( n7305 , n7303 , n7304 );
buf ( n7306 , n4597 );
xor ( n7307 , n7305 , n7306 );
buf ( n7308 , n4598 );
xor ( n7309 , n7307 , n7308 );
xor ( n7310 , n7288 , n7309 );
not ( n7311 , n6474 );
buf ( n7312 , n4599 );
and ( n7313 , n7311 , n7312 );
buf ( n7314 , n4600 );
xor ( n7315 , n7314 , n7312 );
and ( n7316 , n7315 , n6474 );
or ( n7317 , n7313 , n7316 );
not ( n7318 , n6474 );
buf ( n7319 , n4601 );
and ( n7320 , n7318 , n7319 );
buf ( n7321 , n4602 );
xor ( n7322 , n7321 , n7319 );
and ( n7323 , n7322 , n6474 );
or ( n7324 , n7320 , n7323 );
xor ( n7325 , n7317 , n7324 );
buf ( n7326 , n4603 );
xor ( n7327 , n7325 , n7326 );
buf ( n7328 , n4604 );
xor ( n7329 , n7327 , n7328 );
buf ( n7330 , n4605 );
xor ( n7331 , n7329 , n7330 );
xor ( n7332 , n7310 , n7331 );
not ( n7333 , n6474 );
buf ( n7334 , n4606 );
and ( n7335 , n7333 , n7334 );
buf ( n7336 , n4607 );
xor ( n7337 , n7336 , n7334 );
and ( n7338 , n7337 , n6474 );
or ( n7339 , n7335 , n7338 );
not ( n7340 , n6474 );
buf ( n7341 , n4608 );
and ( n7342 , n7340 , n7341 );
buf ( n7343 , n4609 );
xor ( n7344 , n7343 , n7341 );
and ( n7345 , n7344 , n6474 );
or ( n7346 , n7342 , n7345 );
not ( n7347 , n6474 );
buf ( n7348 , n4610 );
and ( n7349 , n7347 , n7348 );
buf ( n7350 , n4611 );
xor ( n7351 , n7350 , n7348 );
and ( n7352 , n7351 , n6474 );
or ( n7353 , n7349 , n7352 );
xor ( n7354 , n7346 , n7353 );
buf ( n7355 , n4612 );
xor ( n7356 , n7354 , n7355 );
buf ( n7357 , n4613 );
xor ( n7358 , n7356 , n7357 );
buf ( n7359 , n4614 );
xor ( n7360 , n7358 , n7359 );
xor ( n7361 , n7339 , n7360 );
not ( n7362 , n6474 );
buf ( n7363 , n4615 );
and ( n7364 , n7362 , n7363 );
buf ( n7365 , n4616 );
xor ( n7366 , n7365 , n7363 );
and ( n7367 , n7366 , n6474 );
or ( n7368 , n7364 , n7367 );
buf ( n7369 , n4617 );
xor ( n7370 , n7368 , n7369 );
buf ( n7371 , n4618 );
xor ( n7372 , n7370 , n7371 );
buf ( n7373 , n4619 );
xor ( n7374 , n7372 , n7373 );
buf ( n7375 , n4620 );
xor ( n7376 , n7374 , n7375 );
xor ( n7377 , n7361 , n7376 );
not ( n7378 , n7377 );
buf ( n7379 , n4621 );
not ( n7380 , n6474 );
buf ( n7381 , n4622 );
and ( n7382 , n7380 , n7381 );
buf ( n7383 , n4623 );
xor ( n7384 , n7383 , n7381 );
and ( n7385 , n7384 , n6474 );
or ( n7386 , n7382 , n7385 );
not ( n7387 , n6474 );
buf ( n7388 , n4624 );
and ( n7389 , n7387 , n7388 );
buf ( n7390 , n4625 );
xor ( n7391 , n7390 , n7388 );
and ( n7392 , n7391 , n6474 );
or ( n7393 , n7389 , n7392 );
xor ( n7394 , n7386 , n7393 );
buf ( n7395 , n4626 );
xor ( n7396 , n7394 , n7395 );
xor ( n7397 , n7396 , n6479 );
buf ( n7398 , n4627 );
xor ( n7399 , n7397 , n7398 );
xor ( n7400 , n7379 , n7399 );
not ( n7401 , n6474 );
buf ( n7402 , n4628 );
and ( n7403 , n7401 , n7402 );
buf ( n7404 , n4629 );
xor ( n7405 , n7404 , n7402 );
and ( n7406 , n7405 , n6474 );
or ( n7407 , n7403 , n7406 );
not ( n7408 , n6474 );
buf ( n7409 , n4630 );
and ( n7410 , n7408 , n7409 );
buf ( n7411 , n4631 );
xor ( n7412 , n7411 , n7409 );
and ( n7413 , n7412 , n6474 );
or ( n7414 , n7410 , n7413 );
xor ( n7415 , n7407 , n7414 );
buf ( n7416 , n4632 );
xor ( n7417 , n7415 , n7416 );
buf ( n7418 , n4633 );
xor ( n7419 , n7417 , n7418 );
buf ( n7420 , n4634 );
xor ( n7421 , n7419 , n7420 );
xor ( n7422 , n7400 , n7421 );
and ( n7423 , n7378 , n7422 );
xor ( n7424 , n7332 , n7423 );
xor ( n7425 , n7287 , n7424 );
buf ( n7426 , n4635 );
not ( n7427 , n6474 );
buf ( n7428 , n4636 );
and ( n7429 , n7427 , n7428 );
buf ( n7430 , n4637 );
xor ( n7431 , n7430 , n7428 );
and ( n7432 , n7431 , n6474 );
or ( n7433 , n7429 , n7432 );
buf ( n7434 , n4638 );
xor ( n7435 , n7433 , n7434 );
buf ( n7436 , n4639 );
xor ( n7437 , n7435 , n7436 );
buf ( n7438 , n4640 );
xor ( n7439 , n7437 , n7438 );
buf ( n7440 , n4641 );
xor ( n7441 , n7439 , n7440 );
xor ( n7442 , n7426 , n7441 );
not ( n7443 , n6474 );
buf ( n7444 , n4642 );
and ( n7445 , n7443 , n7444 );
buf ( n7446 , n4643 );
xor ( n7447 , n7446 , n7444 );
and ( n7448 , n7447 , n6474 );
or ( n7449 , n7445 , n7448 );
not ( n7450 , n6474 );
buf ( n7451 , n4644 );
and ( n7452 , n7450 , n7451 );
buf ( n7453 , n4645 );
xor ( n7454 , n7453 , n7451 );
and ( n7455 , n7454 , n6474 );
or ( n7456 , n7452 , n7455 );
xor ( n7457 , n7449 , n7456 );
buf ( n7458 , n4646 );
xor ( n7459 , n7457 , n7458 );
buf ( n7460 , n4647 );
xor ( n7461 , n7459 , n7460 );
buf ( n7462 , n4648 );
xor ( n7463 , n7461 , n7462 );
xor ( n7464 , n7442 , n7463 );
xor ( n7465 , n7261 , n7159 );
xor ( n7466 , n7465 , n7181 );
not ( n7467 , n7466 );
not ( n7468 , n6474 );
buf ( n7469 , n4649 );
and ( n7470 , n7468 , n7469 );
buf ( n7471 , n4650 );
xor ( n7472 , n7471 , n7469 );
and ( n7473 , n7472 , n6474 );
or ( n7474 , n7470 , n7473 );
not ( n7475 , n6474 );
buf ( n7476 , n7475 );
buf ( n7477 , n4651 );
not ( n7478 , n7477 );
and ( n7479 , n7478 , n6474 );
or ( n7480 , n7476 , n7479 );
not ( n7481 , n6474 );
buf ( n7482 , n4652 );
and ( n7483 , n7481 , n7482 );
buf ( n7484 , n4653 );
xor ( n7485 , n7484 , n7482 );
and ( n7486 , n7485 , n6474 );
or ( n7487 , n7483 , n7486 );
xor ( n7488 , n7480 , n7487 );
buf ( n7489 , n4654 );
xor ( n7490 , n7488 , n7489 );
buf ( n7491 , n4655 );
xor ( n7492 , n7490 , n7491 );
buf ( n7493 , n4656 );
xor ( n7494 , n7492 , n7493 );
xor ( n7495 , n7474 , n7494 );
xor ( n7496 , n7495 , n6850 );
and ( n7497 , n7467 , n7496 );
xor ( n7498 , n7464 , n7497 );
xor ( n7499 , n7425 , n7498 );
buf ( n7500 , n4657 );
not ( n7501 , n6474 );
buf ( n7502 , n4658 );
and ( n7503 , n7501 , n7502 );
buf ( n7504 , n4659 );
xor ( n7505 , n7504 , n7502 );
and ( n7506 , n7505 , n6474 );
or ( n7507 , n7503 , n7506 );
not ( n7508 , n6474 );
buf ( n7509 , n4660 );
and ( n7510 , n7508 , n7509 );
buf ( n7511 , n4661 );
xor ( n7512 , n7511 , n7509 );
and ( n7513 , n7512 , n6474 );
or ( n7514 , n7510 , n7513 );
xor ( n7515 , n7507 , n7514 );
buf ( n7516 , n4662 );
xor ( n7517 , n7515 , n7516 );
buf ( n7518 , n4663 );
xor ( n7519 , n7517 , n7518 );
buf ( n7520 , n4664 );
xor ( n7521 , n7519 , n7520 );
xor ( n7522 , n7500 , n7521 );
not ( n7523 , n6474 );
buf ( n7524 , n4665 );
and ( n7525 , n7523 , n7524 );
buf ( n7526 , n4666 );
xor ( n7527 , n7526 , n7524 );
and ( n7528 , n7527 , n6474 );
or ( n7529 , n7525 , n7528 );
buf ( n7530 , n4667 );
xor ( n7531 , n7529 , n7530 );
buf ( n7532 , n4668 );
xor ( n7533 , n7531 , n7532 );
buf ( n7534 , n4669 );
xor ( n7535 , n7533 , n7534 );
buf ( n7536 , n4670 );
xor ( n7537 , n7535 , n7536 );
xor ( n7538 , n7522 , n7537 );
not ( n7539 , n6474 );
buf ( n7540 , n4671 );
and ( n7541 , n7539 , n7540 );
buf ( n7542 , n4672 );
xor ( n7543 , n7542 , n7540 );
and ( n7544 , n7543 , n6474 );
or ( n7545 , n7541 , n7544 );
not ( n7546 , n6474 );
buf ( n7547 , n4673 );
and ( n7548 , n7546 , n7547 );
buf ( n7549 , n4674 );
xor ( n7550 , n7549 , n7547 );
and ( n7551 , n7550 , n6474 );
or ( n7552 , n7548 , n7551 );
not ( n7553 , n6474 );
buf ( n7554 , n4675 );
and ( n7555 , n7553 , n7554 );
buf ( n7556 , n4676 );
xor ( n7557 , n7556 , n7554 );
and ( n7558 , n7557 , n6474 );
or ( n7559 , n7555 , n7558 );
xor ( n7560 , n7552 , n7559 );
buf ( n7561 , n4677 );
xor ( n7562 , n7560 , n7561 );
buf ( n7563 , n4678 );
xor ( n7564 , n7562 , n7563 );
buf ( n7565 , n4679 );
xor ( n7566 , n7564 , n7565 );
xor ( n7567 , n7545 , n7566 );
not ( n7568 , n6474 );
buf ( n7569 , n4680 );
and ( n7570 , n7568 , n7569 );
buf ( n7571 , n4681 );
xor ( n7572 , n7571 , n7569 );
and ( n7573 , n7572 , n6474 );
or ( n7574 , n7570 , n7573 );
not ( n7575 , n6474 );
buf ( n7576 , n4682 );
and ( n7577 , n7575 , n7576 );
buf ( n7578 , n4683 );
xor ( n7579 , n7578 , n7576 );
and ( n7580 , n7579 , n6474 );
or ( n7581 , n7577 , n7580 );
xor ( n7582 , n7574 , n7581 );
buf ( n7583 , n4684 );
xor ( n7584 , n7582 , n7583 );
buf ( n7585 , n4685 );
xor ( n7586 , n7584 , n7585 );
buf ( n7587 , n4686 );
xor ( n7588 , n7586 , n7587 );
xor ( n7589 , n7567 , n7588 );
not ( n7590 , n7589 );
not ( n7591 , n6474 );
buf ( n7592 , n4687 );
and ( n7593 , n7591 , n7592 );
buf ( n7594 , n4688 );
xor ( n7595 , n7594 , n7592 );
and ( n7596 , n7595 , n6474 );
or ( n7597 , n7593 , n7596 );
not ( n7598 , n6474 );
buf ( n7599 , n4689 );
and ( n7600 , n7598 , n7599 );
buf ( n7601 , n4690 );
xor ( n7602 , n7601 , n7599 );
and ( n7603 , n7602 , n6474 );
or ( n7604 , n7600 , n7603 );
buf ( n7605 , n4691 );
xor ( n7606 , n7604 , n7605 );
buf ( n7607 , n4692 );
xor ( n7608 , n7606 , n7607 );
buf ( n7609 , n4693 );
xor ( n7610 , n7608 , n7609 );
buf ( n7611 , n4694 );
xor ( n7612 , n7610 , n7611 );
xor ( n7613 , n7597 , n7612 );
not ( n7614 , n6474 );
buf ( n7615 , n4695 );
and ( n7616 , n7614 , n7615 );
buf ( n7617 , n4696 );
xor ( n7618 , n7617 , n7615 );
and ( n7619 , n7618 , n6474 );
or ( n7620 , n7616 , n7619 );
not ( n7621 , n6474 );
buf ( n7622 , n4697 );
and ( n7623 , n7621 , n7622 );
buf ( n7624 , n4698 );
xor ( n7625 , n7624 , n7622 );
and ( n7626 , n7625 , n6474 );
or ( n7627 , n7623 , n7626 );
xor ( n7628 , n7620 , n7627 );
buf ( n7629 , n4699 );
xor ( n7630 , n7628 , n7629 );
buf ( n7631 , n4700 );
xor ( n7632 , n7630 , n7631 );
buf ( n7633 , n4701 );
xor ( n7634 , n7632 , n7633 );
xor ( n7635 , n7613 , n7634 );
and ( n7636 , n7590 , n7635 );
xor ( n7637 , n7538 , n7636 );
xor ( n7638 , n7499 , n7637 );
buf ( n7639 , n4702 );
not ( n7640 , n6474 );
buf ( n7641 , n4703 );
and ( n7642 , n7640 , n7641 );
buf ( n7643 , n4704 );
xor ( n7644 , n7643 , n7641 );
and ( n7645 , n7644 , n6474 );
or ( n7646 , n7642 , n7645 );
not ( n7647 , n6474 );
buf ( n7648 , n4705 );
and ( n7649 , n7647 , n7648 );
buf ( n7650 , n4706 );
xor ( n7651 , n7650 , n7648 );
and ( n7652 , n7651 , n6474 );
or ( n7653 , n7649 , n7652 );
xor ( n7654 , n7646 , n7653 );
xor ( n7655 , n7654 , n6658 );
buf ( n7656 , n4707 );
xor ( n7657 , n7655 , n7656 );
buf ( n7658 , n4708 );
xor ( n7659 , n7657 , n7658 );
xor ( n7660 , n7639 , n7659 );
not ( n7661 , n6474 );
buf ( n7662 , n4709 );
and ( n7663 , n7661 , n7662 );
buf ( n7664 , n4710 );
xor ( n7665 , n7664 , n7662 );
and ( n7666 , n7665 , n6474 );
or ( n7667 , n7663 , n7666 );
not ( n7668 , n6474 );
buf ( n7669 , n4711 );
and ( n7670 , n7668 , n7669 );
buf ( n7671 , n4712 );
xor ( n7672 , n7671 , n7669 );
and ( n7673 , n7672 , n6474 );
or ( n7674 , n7670 , n7673 );
xor ( n7675 , n7667 , n7674 );
buf ( n7676 , n4713 );
xor ( n7677 , n7675 , n7676 );
buf ( n7678 , n4714 );
xor ( n7679 , n7677 , n7678 );
buf ( n7680 , n4715 );
xor ( n7681 , n7679 , n7680 );
xor ( n7682 , n7660 , n7681 );
not ( n7683 , n6474 );
buf ( n7684 , n4716 );
and ( n7685 , n7683 , n7684 );
buf ( n7686 , n4717 );
xor ( n7687 , n7686 , n7684 );
and ( n7688 , n7687 , n6474 );
or ( n7689 , n7685 , n7688 );
not ( n7690 , n6474 );
buf ( n7691 , n4718 );
and ( n7692 , n7690 , n7691 );
buf ( n7693 , n4719 );
xor ( n7694 , n7693 , n7691 );
and ( n7695 , n7694 , n6474 );
or ( n7696 , n7692 , n7695 );
not ( n7697 , n6474 );
buf ( n7698 , n4720 );
and ( n7699 , n7697 , n7698 );
buf ( n7700 , n4721 );
xor ( n7701 , n7700 , n7698 );
and ( n7702 , n7701 , n6474 );
or ( n7703 , n7699 , n7702 );
xor ( n7704 , n7696 , n7703 );
buf ( n7705 , n4722 );
xor ( n7706 , n7704 , n7705 );
buf ( n7707 , n4723 );
xor ( n7708 , n7706 , n7707 );
buf ( n7709 , n4724 );
xor ( n7710 , n7708 , n7709 );
xor ( n7711 , n7689 , n7710 );
not ( n7712 , n6474 );
buf ( n7713 , n4725 );
and ( n7714 , n7712 , n7713 );
buf ( n7715 , n4726 );
xor ( n7716 , n7715 , n7713 );
and ( n7717 , n7716 , n6474 );
or ( n7718 , n7714 , n7717 );
not ( n7719 , n6474 );
buf ( n7720 , n4727 );
and ( n7721 , n7719 , n7720 );
buf ( n7722 , n4728 );
xor ( n7723 , n7722 , n7720 );
and ( n7724 , n7723 , n6474 );
or ( n7725 , n7721 , n7724 );
xor ( n7726 , n7718 , n7725 );
buf ( n7727 , n4729 );
xor ( n7728 , n7726 , n7727 );
buf ( n7729 , n4730 );
xor ( n7730 , n7728 , n7729 );
buf ( n7731 , n4731 );
xor ( n7732 , n7730 , n7731 );
xor ( n7733 , n7711 , n7732 );
not ( n7734 , n7733 );
not ( n7735 , n6474 );
buf ( n7736 , n4732 );
and ( n7737 , n7735 , n7736 );
buf ( n7738 , n4733 );
xor ( n7739 , n7738 , n7736 );
and ( n7740 , n7739 , n6474 );
or ( n7741 , n7737 , n7740 );
xor ( n7742 , n7741 , n7030 );
xor ( n7743 , n7742 , n7046 );
and ( n7744 , n7734 , n7743 );
xor ( n7745 , n7682 , n7744 );
xor ( n7746 , n7638 , n7745 );
xor ( n7747 , n7186 , n7746 );
buf ( n7748 , n4734 );
not ( n7749 , n6474 );
buf ( n7750 , n4735 );
and ( n7751 , n7749 , n7750 );
buf ( n7752 , n4736 );
xor ( n7753 , n7752 , n7750 );
and ( n7754 , n7753 , n6474 );
or ( n7755 , n7751 , n7754 );
not ( n7756 , n6474 );
buf ( n7757 , n4737 );
and ( n7758 , n7756 , n7757 );
buf ( n7759 , n4738 );
xor ( n7760 , n7759 , n7757 );
and ( n7761 , n7760 , n6474 );
or ( n7762 , n7758 , n7761 );
xor ( n7763 , n7755 , n7762 );
buf ( n7764 , n4739 );
xor ( n7765 , n7763 , n7764 );
not ( n7766 , n4740 );
buf ( n7767 , n7766 );
buf ( n7768 , n7767 );
xor ( n7769 , n7765 , n7768 );
buf ( n7770 , n4741 );
xor ( n7771 , n7769 , n7770 );
xor ( n7772 , n7748 , n7771 );
not ( n7773 , n6474 );
buf ( n7774 , n4742 );
and ( n7775 , n7773 , n7774 );
buf ( n7776 , n4743 );
xor ( n7777 , n7776 , n7774 );
and ( n7778 , n7777 , n6474 );
or ( n7779 , n7775 , n7778 );
not ( n7780 , n6474 );
buf ( n7781 , n4744 );
and ( n7782 , n7780 , n7781 );
buf ( n7783 , n4745 );
xor ( n7784 , n7783 , n7781 );
and ( n7785 , n7784 , n6474 );
or ( n7786 , n7782 , n7785 );
xor ( n7787 , n7779 , n7786 );
buf ( n7788 , n4746 );
xor ( n7789 , n7787 , n7788 );
buf ( n7790 , n4747 );
xor ( n7791 , n7789 , n7790 );
buf ( n7792 , n4748 );
xor ( n7793 , n7791 , n7792 );
xor ( n7794 , n7772 , n7793 );
not ( n7795 , n6474 );
buf ( n7796 , n4749 );
and ( n7797 , n7795 , n7796 );
buf ( n7798 , n4750 );
xor ( n7799 , n7798 , n7796 );
and ( n7800 , n7799 , n6474 );
or ( n7801 , n7797 , n7800 );
not ( n7802 , n6474 );
buf ( n7803 , n4751 );
and ( n7804 , n7802 , n7803 );
buf ( n7805 , n4752 );
xor ( n7806 , n7805 , n7803 );
and ( n7807 , n7806 , n6474 );
or ( n7808 , n7804 , n7807 );
not ( n7809 , n6474 );
buf ( n7810 , n4753 );
and ( n7811 , n7809 , n7810 );
buf ( n7812 , n4754 );
xor ( n7813 , n7812 , n7810 );
and ( n7814 , n7813 , n6474 );
or ( n7815 , n7811 , n7814 );
xor ( n7816 , n7808 , n7815 );
buf ( n7817 , n4755 );
xor ( n7818 , n7816 , n7817 );
buf ( n7819 , n4756 );
xor ( n7820 , n7818 , n7819 );
buf ( n7821 , n4757 );
xor ( n7822 , n7820 , n7821 );
xor ( n7823 , n7801 , n7822 );
not ( n7824 , n6474 );
buf ( n7825 , n4758 );
and ( n7826 , n7824 , n7825 );
buf ( n7827 , n4759 );
xor ( n7828 , n7827 , n7825 );
and ( n7829 , n7828 , n6474 );
or ( n7830 , n7826 , n7829 );
xor ( n7831 , n7830 , n7379 );
buf ( n7832 , n4760 );
xor ( n7833 , n7831 , n7832 );
buf ( n7834 , n4761 );
xor ( n7835 , n7833 , n7834 );
buf ( n7836 , n4762 );
xor ( n7837 , n7835 , n7836 );
xor ( n7838 , n7823 , n7837 );
not ( n7839 , n7838 );
buf ( n7840 , n4763 );
not ( n7841 , n6474 );
buf ( n7842 , n4764 );
and ( n7843 , n7841 , n7842 );
buf ( n7844 , n4765 );
xor ( n7845 , n7844 , n7842 );
and ( n7846 , n7845 , n6474 );
or ( n7847 , n7843 , n7846 );
not ( n7848 , n6474 );
buf ( n7849 , n4766 );
and ( n7850 , n7848 , n7849 );
buf ( n7851 , n4767 );
xor ( n7852 , n7851 , n7849 );
and ( n7853 , n7852 , n6474 );
or ( n7854 , n7850 , n7853 );
xor ( n7855 , n7847 , n7854 );
buf ( n7856 , n4768 );
xor ( n7857 , n7855 , n7856 );
buf ( n7858 , n4769 );
xor ( n7859 , n7857 , n7858 );
buf ( n7860 , n4770 );
xor ( n7861 , n7859 , n7860 );
xor ( n7862 , n7840 , n7861 );
not ( n7863 , n6474 );
buf ( n7864 , n4771 );
and ( n7865 , n7863 , n7864 );
buf ( n7866 , n4772 );
xor ( n7867 , n7866 , n7864 );
and ( n7868 , n7867 , n6474 );
or ( n7869 , n7865 , n7868 );
not ( n7870 , n6474 );
buf ( n7871 , n4773 );
and ( n7872 , n7870 , n7871 );
buf ( n7873 , n4774 );
xor ( n7874 , n7873 , n7871 );
and ( n7875 , n7874 , n6474 );
or ( n7876 , n7872 , n7875 );
xor ( n7877 , n7869 , n7876 );
buf ( n7878 , n4775 );
xor ( n7879 , n7877 , n7878 );
buf ( n7880 , n4776 );
xor ( n7881 , n7879 , n7880 );
buf ( n7882 , n4777 );
xor ( n7883 , n7881 , n7882 );
xor ( n7884 , n7862 , n7883 );
and ( n7885 , n7839 , n7884 );
xor ( n7886 , n7794 , n7885 );
not ( n7887 , n4780 );
buf ( n7888 , n7887 );
buf ( n7889 , n7888 );
not ( n7890 , n6474 );
buf ( n7891 , n4778 );
and ( n7892 , n7890 , n7891 );
buf ( n7893 , n4779 );
xor ( n7894 , n7893 , n7891 );
and ( n7895 , n7894 , n6474 );
or ( n7896 , n7892 , n7895 );
not ( n7897 , n6474 );
buf ( n7898 , n4780 );
and ( n7899 , n7897 , n7898 );
buf ( n7900 , n4781 );
xor ( n7901 , n7900 , n7898 );
and ( n7902 , n7901 , n6474 );
or ( n7903 , n7899 , n7902 );
xor ( n7904 , n7896 , n7903 );
buf ( n7905 , n4782 );
xor ( n7906 , n7904 , n7905 );
buf ( n7907 , n4783 );
xor ( n7908 , n7906 , n7907 );
buf ( n7909 , n4784 );
xor ( n7910 , n7908 , n7909 );
xor ( n7911 , n7889 , n7910 );
not ( n7912 , n6474 );
buf ( n7913 , n4785 );
and ( n7914 , n7912 , n7913 );
buf ( n7915 , n4786 );
xor ( n7916 , n7915 , n7913 );
and ( n7917 , n7916 , n6474 );
or ( n7918 , n7914 , n7917 );
buf ( n7919 , n4787 );
xor ( n7920 , n7918 , n7919 );
buf ( n7921 , n4788 );
xor ( n7922 , n7920 , n7921 );
buf ( n7923 , n4789 );
xor ( n7924 , n7922 , n7923 );
xor ( n7925 , n7924 , n6518 );
xor ( n7926 , n7911 , n7925 );
buf ( n7927 , n4790 );
not ( n7928 , n6474 );
buf ( n7929 , n4791 );
and ( n7930 , n7928 , n7929 );
buf ( n7931 , n4792 );
xor ( n7932 , n7931 , n7929 );
and ( n7933 , n7932 , n6474 );
or ( n7934 , n7930 , n7933 );
not ( n7935 , n6474 );
buf ( n7936 , n4793 );
and ( n7937 , n7935 , n7936 );
buf ( n7938 , n4794 );
xor ( n7939 , n7938 , n7936 );
and ( n7940 , n7939 , n6474 );
or ( n7941 , n7937 , n7940 );
xor ( n7942 , n7934 , n7941 );
buf ( n7943 , n4795 );
xor ( n7944 , n7942 , n7943 );
buf ( n7945 , n4796 );
xor ( n7946 , n7944 , n7945 );
buf ( n7947 , n4797 );
xor ( n7948 , n7946 , n7947 );
xor ( n7949 , n7927 , n7948 );
not ( n7950 , n6474 );
buf ( n7951 , n4798 );
and ( n7952 , n7950 , n7951 );
buf ( n7953 , n4799 );
xor ( n7954 , n7953 , n7951 );
and ( n7955 , n7954 , n6474 );
or ( n7956 , n7952 , n7955 );
not ( n7957 , n6474 );
buf ( n7958 , n4800 );
and ( n7959 , n7957 , n7958 );
buf ( n7960 , n4801 );
xor ( n7961 , n7960 , n7958 );
and ( n7962 , n7961 , n6474 );
or ( n7963 , n7959 , n7962 );
xor ( n7964 , n7956 , n7963 );
buf ( n7965 , n4802 );
xor ( n7966 , n7964 , n7965 );
buf ( n7967 , n4803 );
xor ( n7968 , n7966 , n7967 );
buf ( n7969 , n4804 );
xor ( n7970 , n7968 , n7969 );
xor ( n7971 , n7949 , n7970 );
not ( n7972 , n7971 );
not ( n7973 , n6474 );
buf ( n7974 , n4805 );
and ( n7975 , n7973 , n7974 );
buf ( n7976 , n4806 );
xor ( n7977 , n7976 , n7974 );
and ( n7978 , n7977 , n6474 );
or ( n7979 , n7975 , n7978 );
not ( n7980 , n6474 );
buf ( n7981 , n4807 );
and ( n7982 , n7980 , n7981 );
buf ( n7983 , n4808 );
xor ( n7984 , n7983 , n7981 );
and ( n7985 , n7984 , n6474 );
or ( n7986 , n7982 , n7985 );
buf ( n7987 , n4809 );
xor ( n7988 , n7986 , n7987 );
buf ( n7989 , n4810 );
xor ( n7990 , n7988 , n7989 );
buf ( n7991 , n4811 );
xor ( n7992 , n7990 , n7991 );
buf ( n7993 , n4812 );
xor ( n7994 , n7992 , n7993 );
xor ( n7995 , n7979 , n7994 );
not ( n7996 , n6474 );
buf ( n7997 , n4813 );
and ( n7998 , n7996 , n7997 );
buf ( n7999 , n4814 );
xor ( n8000 , n7999 , n7997 );
and ( n8001 , n8000 , n6474 );
or ( n8002 , n7998 , n8001 );
not ( n8003 , n6474 );
buf ( n8004 , n4815 );
and ( n8005 , n8003 , n8004 );
buf ( n8006 , n4816 );
xor ( n8007 , n8006 , n8004 );
and ( n8008 , n8007 , n6474 );
or ( n8009 , n8005 , n8008 );
xor ( n8010 , n8002 , n8009 );
buf ( n8011 , n4817 );
xor ( n8012 , n8010 , n8011 );
buf ( n8013 , n4818 );
xor ( n8014 , n8012 , n8013 );
buf ( n8015 , n4819 );
xor ( n8016 , n8014 , n8015 );
xor ( n8017 , n7995 , n8016 );
and ( n8018 , n7972 , n8017 );
xor ( n8019 , n7926 , n8018 );
buf ( n8020 , n4820 );
not ( n8021 , n6474 );
buf ( n8022 , n4821 );
and ( n8023 , n8021 , n8022 );
buf ( n8024 , n4822 );
xor ( n8025 , n8024 , n8022 );
and ( n8026 , n8025 , n6474 );
or ( n8027 , n8023 , n8026 );
xor ( n8028 , n8027 , n7597 );
buf ( n8029 , n4823 );
xor ( n8030 , n8028 , n8029 );
buf ( n8031 , n4824 );
xor ( n8032 , n8030 , n8031 );
buf ( n8033 , n4825 );
xor ( n8034 , n8032 , n8033 );
xor ( n8035 , n8020 , n8034 );
not ( n8036 , n6474 );
buf ( n8037 , n4826 );
and ( n8038 , n8036 , n8037 );
buf ( n8039 , n4827 );
xor ( n8040 , n8039 , n8037 );
and ( n8041 , n8040 , n6474 );
or ( n8042 , n8038 , n8041 );
not ( n8043 , n6474 );
buf ( n8044 , n4828 );
and ( n8045 , n8043 , n8044 );
buf ( n8046 , n4829 );
xor ( n8047 , n8046 , n8044 );
and ( n8048 , n8047 , n6474 );
or ( n8049 , n8045 , n8048 );
xor ( n8050 , n8042 , n8049 );
buf ( n8051 , n4830 );
xor ( n8052 , n8050 , n8051 );
buf ( n8053 , n4831 );
xor ( n8054 , n8052 , n8053 );
buf ( n8055 , n4832 );
xor ( n8056 , n8054 , n8055 );
xor ( n8057 , n8035 , n8056 );
not ( n8058 , n7794 );
and ( n8059 , n8058 , n7838 );
xor ( n8060 , n8057 , n8059 );
xor ( n8061 , n8019 , n8060 );
xor ( n8062 , n6581 , n7732 );
not ( n8063 , n6474 );
buf ( n8064 , n4833 );
and ( n8065 , n8063 , n8064 );
buf ( n8066 , n4834 );
xor ( n8067 , n8066 , n8064 );
and ( n8068 , n8067 , n6474 );
or ( n8069 , n8065 , n8068 );
xor ( n8070 , n7238 , n8069 );
buf ( n8071 , n4835 );
xor ( n8072 , n8070 , n8071 );
buf ( n8073 , n4836 );
xor ( n8074 , n8072 , n8073 );
buf ( n8075 , n4837 );
xor ( n8076 , n8074 , n8075 );
xor ( n8077 , n8062 , n8076 );
not ( n8078 , n6474 );
buf ( n8079 , n4838 );
and ( n8080 , n8078 , n8079 );
buf ( n8081 , n4839 );
xor ( n8082 , n8081 , n8079 );
and ( n8083 , n8082 , n6474 );
or ( n8084 , n8080 , n8083 );
buf ( n8085 , n4840 );
xor ( n8086 , n8084 , n8085 );
buf ( n8087 , n4841 );
xor ( n8088 , n8086 , n8087 );
buf ( n8089 , n4842 );
xor ( n8090 , n8088 , n8089 );
buf ( n8091 , n4843 );
xor ( n8092 , n8090 , n8091 );
xor ( n8093 , n6938 , n8092 );
not ( n8094 , n6474 );
buf ( n8095 , n4844 );
and ( n8096 , n8094 , n8095 );
buf ( n8097 , n4845 );
xor ( n8098 , n8097 , n8095 );
and ( n8099 , n8098 , n6474 );
or ( n8100 , n8096 , n8099 );
not ( n8101 , n6474 );
buf ( n8102 , n4846 );
and ( n8103 , n8101 , n8102 );
buf ( n8104 , n4847 );
xor ( n8105 , n8104 , n8102 );
and ( n8106 , n8105 , n6474 );
or ( n8107 , n8103 , n8106 );
xor ( n8108 , n8100 , n8107 );
buf ( n8109 , n4848 );
xor ( n8110 , n8108 , n8109 );
buf ( n8111 , n4849 );
xor ( n8112 , n8110 , n8111 );
buf ( n8113 , n4850 );
xor ( n8114 , n8112 , n8113 );
xor ( n8115 , n8093 , n8114 );
not ( n8116 , n8115 );
not ( n8117 , n6474 );
buf ( n8118 , n4851 );
and ( n8119 , n8117 , n8118 );
buf ( n8120 , n4852 );
xor ( n8121 , n8120 , n8118 );
and ( n8122 , n8121 , n6474 );
or ( n8123 , n8119 , n8122 );
not ( n8124 , n6474 );
buf ( n8125 , n4853 );
and ( n8126 , n8124 , n8125 );
buf ( n8127 , n4854 );
xor ( n8128 , n8127 , n8125 );
and ( n8129 , n8128 , n6474 );
or ( n8130 , n8126 , n8129 );
xor ( n8131 , n8123 , n8130 );
buf ( n8132 , n4855 );
xor ( n8133 , n8131 , n8132 );
buf ( n8134 , n4856 );
xor ( n8135 , n8133 , n8134 );
buf ( n8136 , n4857 );
xor ( n8137 , n8135 , n8136 );
xor ( n8138 , n8002 , n8137 );
not ( n8139 , n6474 );
buf ( n8140 , n4858 );
and ( n8141 , n8139 , n8140 );
buf ( n8142 , n4859 );
xor ( n8143 , n8142 , n8140 );
and ( n8144 , n8143 , n6474 );
or ( n8145 , n8141 , n8144 );
not ( n8146 , n6474 );
buf ( n8147 , n4860 );
and ( n8148 , n8146 , n8147 );
buf ( n8149 , n4861 );
xor ( n8150 , n8149 , n8147 );
and ( n8151 , n8150 , n6474 );
or ( n8152 , n8148 , n8151 );
xor ( n8153 , n8145 , n8152 );
buf ( n8154 , n4862 );
xor ( n8155 , n8153 , n8154 );
buf ( n8156 , n4863 );
xor ( n8157 , n8155 , n8156 );
buf ( n8158 , n4864 );
xor ( n8159 , n8157 , n8158 );
xor ( n8160 , n8138 , n8159 );
and ( n8161 , n8116 , n8160 );
xor ( n8162 , n8077 , n8161 );
xor ( n8163 , n8061 , n8162 );
buf ( n8164 , n4865 );
xor ( n8165 , n8164 , n7494 );
xor ( n8166 , n8165 , n6850 );
buf ( n8167 , n4866 );
not ( n8168 , n6474 );
buf ( n8169 , n4867 );
and ( n8170 , n8168 , n8169 );
buf ( n8171 , n4868 );
xor ( n8172 , n8171 , n8169 );
and ( n8173 , n8172 , n6474 );
or ( n8174 , n8170 , n8173 );
not ( n8175 , n6474 );
buf ( n8176 , n4869 );
and ( n8177 , n8175 , n8176 );
buf ( n8178 , n4870 );
xor ( n8179 , n8178 , n8176 );
and ( n8180 , n8179 , n6474 );
or ( n8181 , n8177 , n8180 );
xor ( n8182 , n8174 , n8181 );
buf ( n8183 , n4871 );
xor ( n8184 , n8182 , n8183 );
buf ( n8185 , n4872 );
xor ( n8186 , n8184 , n8185 );
buf ( n8187 , n4873 );
xor ( n8188 , n8186 , n8187 );
xor ( n8189 , n8167 , n8188 );
not ( n8190 , n6474 );
buf ( n8191 , n4874 );
and ( n8192 , n8190 , n8191 );
buf ( n8193 , n4875 );
xor ( n8194 , n8193 , n8191 );
and ( n8195 , n8194 , n6474 );
or ( n8196 , n8192 , n8195 );
buf ( n8197 , n4876 );
xor ( n8198 , n8196 , n8197 );
buf ( n8199 , n4877 );
xor ( n8200 , n8198 , n8199 );
buf ( n8201 , n4878 );
xor ( n8202 , n8200 , n8201 );
buf ( n8203 , n4879 );
xor ( n8204 , n8202 , n8203 );
xor ( n8205 , n8189 , n8204 );
not ( n8206 , n8205 );
not ( n8207 , n6474 );
buf ( n8208 , n4880 );
and ( n8209 , n8207 , n8208 );
buf ( n8210 , n4881 );
xor ( n8211 , n8210 , n8208 );
and ( n8212 , n8211 , n6474 );
or ( n8213 , n8209 , n8212 );
not ( n8214 , n6474 );
buf ( n8215 , n4882 );
and ( n8216 , n8214 , n8215 );
buf ( n8217 , n4883 );
xor ( n8218 , n8217 , n8215 );
and ( n8219 , n8218 , n6474 );
or ( n8220 , n8216 , n8219 );
xor ( n8221 , n8213 , n8220 );
buf ( n8222 , n4884 );
xor ( n8223 , n8221 , n8222 );
buf ( n8224 , n4885 );
xor ( n8225 , n8223 , n8224 );
buf ( n8226 , n4886 );
xor ( n8227 , n8225 , n8226 );
xor ( n8228 , n7433 , n8227 );
not ( n8229 , n6474 );
buf ( n8230 , n4887 );
and ( n8231 , n8229 , n8230 );
buf ( n8232 , n4888 );
xor ( n8233 , n8232 , n8230 );
and ( n8234 , n8233 , n6474 );
or ( n8235 , n8231 , n8234 );
not ( n8236 , n6474 );
buf ( n8237 , n4889 );
and ( n8238 , n8236 , n8237 );
buf ( n8239 , n4890 );
xor ( n8240 , n8239 , n8237 );
and ( n8241 , n8240 , n6474 );
or ( n8242 , n8238 , n8241 );
xor ( n8243 , n8235 , n8242 );
buf ( n8244 , n4891 );
xor ( n8245 , n8243 , n8244 );
buf ( n8246 , n4892 );
xor ( n8247 , n8245 , n8246 );
buf ( n8248 , n4893 );
xor ( n8249 , n8247 , n8248 );
xor ( n8250 , n8228 , n8249 );
and ( n8251 , n8206 , n8250 );
xor ( n8252 , n8166 , n8251 );
xor ( n8253 , n8163 , n8252 );
buf ( n8254 , n4894 );
not ( n8255 , n6474 );
buf ( n8256 , n4895 );
and ( n8257 , n8255 , n8256 );
buf ( n8258 , n4896 );
xor ( n8259 , n8258 , n8256 );
and ( n8260 , n8259 , n6474 );
or ( n8261 , n8257 , n8260 );
buf ( n8262 , n4897 );
xor ( n8263 , n8261 , n8262 );
buf ( n8264 , n4898 );
xor ( n8265 , n8263 , n8264 );
buf ( n8266 , n4899 );
xor ( n8267 , n8265 , n8266 );
buf ( n8268 , n4900 );
xor ( n8269 , n8267 , n8268 );
xor ( n8270 , n8254 , n8269 );
not ( n8271 , n6474 );
buf ( n8272 , n4901 );
and ( n8273 , n8271 , n8272 );
buf ( n8274 , n4902 );
xor ( n8275 , n8274 , n8272 );
and ( n8276 , n8275 , n6474 );
or ( n8277 , n8273 , n8276 );
not ( n8278 , n6474 );
buf ( n8279 , n4903 );
and ( n8280 , n8278 , n8279 );
buf ( n8281 , n4904 );
xor ( n8282 , n8281 , n8279 );
and ( n8283 , n8282 , n6474 );
or ( n8284 , n8280 , n8283 );
xor ( n8285 , n8277 , n8284 );
buf ( n8286 , n4905 );
xor ( n8287 , n8285 , n8286 );
buf ( n8288 , n4906 );
xor ( n8289 , n8287 , n8288 );
buf ( n8290 , n4907 );
xor ( n8291 , n8289 , n8290 );
xor ( n8292 , n8270 , n8291 );
buf ( n8293 , n4908 );
not ( n8294 , n6474 );
buf ( n8295 , n4909 );
and ( n8296 , n8294 , n8295 );
buf ( n8297 , n4910 );
xor ( n8298 , n8297 , n8295 );
and ( n8299 , n8298 , n6474 );
or ( n8300 , n8296 , n8299 );
not ( n8301 , n6474 );
buf ( n8302 , n4911 );
and ( n8303 , n8301 , n8302 );
buf ( n8304 , n4912 );
xor ( n8305 , n8304 , n8302 );
and ( n8306 , n8305 , n6474 );
or ( n8307 , n8303 , n8306 );
xor ( n8308 , n8300 , n8307 );
buf ( n8309 , n4913 );
xor ( n8310 , n8308 , n8309 );
buf ( n8311 , n4914 );
xor ( n8312 , n8310 , n8311 );
buf ( n8313 , n4915 );
xor ( n8314 , n8312 , n8313 );
xor ( n8315 , n8293 , n8314 );
not ( n8316 , n6474 );
buf ( n8317 , n4916 );
and ( n8318 , n8316 , n8317 );
buf ( n8319 , n4917 );
xor ( n8320 , n8319 , n8317 );
and ( n8321 , n8320 , n6474 );
or ( n8322 , n8318 , n8321 );
not ( n8323 , n6474 );
buf ( n8324 , n4918 );
and ( n8325 , n8323 , n8324 );
buf ( n8326 , n4919 );
xor ( n8327 , n8326 , n8324 );
and ( n8328 , n8327 , n6474 );
or ( n8329 , n8325 , n8328 );
xor ( n8330 , n8322 , n8329 );
buf ( n8331 , n4920 );
xor ( n8332 , n8330 , n8331 );
buf ( n8333 , n4921 );
xor ( n8334 , n8332 , n8333 );
buf ( n8335 , n4922 );
xor ( n8336 , n8334 , n8335 );
xor ( n8337 , n8315 , n8336 );
not ( n8338 , n8337 );
not ( n8339 , n6474 );
buf ( n8340 , n4923 );
and ( n8341 , n8339 , n8340 );
buf ( n8342 , n4924 );
xor ( n8343 , n8342 , n8340 );
and ( n8344 , n8343 , n6474 );
or ( n8345 , n8341 , n8344 );
not ( n8346 , n6474 );
buf ( n8347 , n4925 );
and ( n8348 , n8346 , n8347 );
buf ( n8349 , n4926 );
xor ( n8350 , n8349 , n8347 );
and ( n8351 , n8350 , n6474 );
or ( n8352 , n8348 , n8351 );
not ( n8353 , n6474 );
buf ( n8354 , n4927 );
and ( n8355 , n8353 , n8354 );
buf ( n8356 , n4928 );
xor ( n8357 , n8356 , n8354 );
and ( n8358 , n8357 , n6474 );
or ( n8359 , n8355 , n8358 );
xor ( n8360 , n8352 , n8359 );
buf ( n8361 , n4929 );
xor ( n8362 , n8360 , n8361 );
buf ( n8363 , n4930 );
xor ( n8364 , n8362 , n8363 );
buf ( n8365 , n4931 );
xor ( n8366 , n8364 , n8365 );
xor ( n8367 , n8345 , n8366 );
not ( n8368 , n6474 );
buf ( n8369 , n4932 );
and ( n8370 , n8368 , n8369 );
buf ( n8371 , n4933 );
xor ( n8372 , n8371 , n8369 );
and ( n8373 , n8372 , n6474 );
or ( n8374 , n8370 , n8373 );
not ( n8375 , n6474 );
buf ( n8376 , n4934 );
and ( n8377 , n8375 , n8376 );
buf ( n8378 , n4935 );
xor ( n8379 , n8378 , n8376 );
and ( n8380 , n8379 , n6474 );
or ( n8381 , n8377 , n8380 );
xor ( n8382 , n8374 , n8381 );
buf ( n8383 , n4936 );
xor ( n8384 , n8382 , n8383 );
buf ( n8385 , n4937 );
xor ( n8386 , n8384 , n8385 );
buf ( n8387 , n4938 );
xor ( n8388 , n8386 , n8387 );
xor ( n8389 , n8367 , n8388 );
and ( n8390 , n8338 , n8389 );
xor ( n8391 , n8292 , n8390 );
xor ( n8392 , n8253 , n8391 );
xor ( n8393 , n7886 , n8392 );
xor ( n8394 , n8123 , n7046 );
not ( n8395 , n6474 );
buf ( n8396 , n4939 );
and ( n8397 , n8395 , n8396 );
buf ( n8398 , n4940 );
xor ( n8399 , n8398 , n8396 );
and ( n8400 , n8399 , n6474 );
or ( n8401 , n8397 , n8400 );
not ( n8402 , n6474 );
buf ( n8403 , n4941 );
and ( n8404 , n8402 , n8403 );
buf ( n8405 , n4942 );
xor ( n8406 , n8405 , n8403 );
and ( n8407 , n8406 , n6474 );
or ( n8408 , n8404 , n8407 );
xor ( n8409 , n8401 , n8408 );
buf ( n8410 , n4943 );
xor ( n8411 , n8409 , n8410 );
buf ( n8412 , n4944 );
xor ( n8413 , n8411 , n8412 );
xor ( n8414 , n8413 , n8293 );
xor ( n8415 , n8394 , n8414 );
not ( n8416 , n6474 );
buf ( n8417 , n4945 );
and ( n8418 , n8416 , n8417 );
buf ( n8419 , n4946 );
xor ( n8420 , n8419 , n8417 );
and ( n8421 , n8420 , n6474 );
or ( n8422 , n8418 , n8421 );
xor ( n8423 , n8422 , n8034 );
xor ( n8424 , n8423 , n8056 );
not ( n8425 , n8424 );
buf ( n8426 , n4947 );
not ( n8427 , n6474 );
buf ( n8428 , n4948 );
and ( n8429 , n8427 , n8428 );
buf ( n8430 , n4949 );
xor ( n8431 , n8430 , n8428 );
and ( n8432 , n8431 , n6474 );
or ( n8433 , n8429 , n8432 );
not ( n8434 , n6474 );
buf ( n8435 , n4950 );
and ( n8436 , n8434 , n8435 );
buf ( n8437 , n4951 );
xor ( n8438 , n8437 , n8435 );
and ( n8439 , n8438 , n6474 );
or ( n8440 , n8436 , n8439 );
xor ( n8441 , n8433 , n8440 );
buf ( n8442 , n4952 );
xor ( n8443 , n8441 , n8442 );
buf ( n8444 , n4953 );
xor ( n8445 , n8443 , n8444 );
buf ( n8446 , n4954 );
xor ( n8447 , n8445 , n8446 );
xor ( n8448 , n8426 , n8447 );
not ( n8449 , n6474 );
buf ( n8450 , n4955 );
and ( n8451 , n8449 , n8450 );
buf ( n8452 , n4956 );
xor ( n8453 , n8452 , n8450 );
and ( n8454 , n8453 , n6474 );
or ( n8455 , n8451 , n8454 );
not ( n8456 , n6474 );
buf ( n8457 , n4957 );
and ( n8458 , n8456 , n8457 );
buf ( n8459 , n4958 );
xor ( n8460 , n8459 , n8457 );
and ( n8461 , n8460 , n6474 );
or ( n8462 , n8458 , n8461 );
xor ( n8463 , n8455 , n8462 );
buf ( n8464 , n4959 );
xor ( n8465 , n8463 , n8464 );
buf ( n8466 , n4960 );
xor ( n8467 , n8465 , n8466 );
buf ( n8468 , n4961 );
xor ( n8469 , n8467 , n8468 );
xor ( n8470 , n8448 , n8469 );
and ( n8471 , n8425 , n8470 );
xor ( n8472 , n8415 , n8471 );
xor ( n8473 , n7386 , n6500 );
xor ( n8474 , n8473 , n6516 );
buf ( n8475 , n4962 );
not ( n8476 , n6474 );
buf ( n8477 , n4963 );
and ( n8478 , n8476 , n8477 );
buf ( n8479 , n4964 );
xor ( n8480 , n8479 , n8477 );
and ( n8481 , n8480 , n6474 );
or ( n8482 , n8478 , n8481 );
not ( n8483 , n6474 );
buf ( n8484 , n4965 );
and ( n8485 , n8483 , n8484 );
buf ( n8486 , n4966 );
xor ( n8487 , n8486 , n8484 );
and ( n8488 , n8487 , n6474 );
or ( n8489 , n8485 , n8488 );
xor ( n8490 , n8482 , n8489 );
buf ( n8491 , n4967 );
xor ( n8492 , n8490 , n8491 );
xor ( n8493 , n8492 , n7889 );
buf ( n8494 , n4968 );
xor ( n8495 , n8493 , n8494 );
xor ( n8496 , n8475 , n8495 );
not ( n8497 , n6474 );
buf ( n8498 , n4969 );
and ( n8499 , n8497 , n8498 );
buf ( n8500 , n4970 );
xor ( n8501 , n8500 , n8498 );
and ( n8502 , n8501 , n6474 );
or ( n8503 , n8499 , n8502 );
not ( n8504 , n6474 );
buf ( n8505 , n4971 );
and ( n8506 , n8504 , n8505 );
buf ( n8507 , n4972 );
xor ( n8508 , n8507 , n8505 );
and ( n8509 , n8508 , n6474 );
or ( n8510 , n8506 , n8509 );
xor ( n8511 , n8503 , n8510 );
buf ( n8512 , n4973 );
xor ( n8513 , n8511 , n8512 );
buf ( n8514 , n4974 );
xor ( n8515 , n8513 , n8514 );
buf ( n8516 , n4975 );
xor ( n8517 , n8515 , n8516 );
xor ( n8518 , n8496 , n8517 );
not ( n8519 , n8518 );
buf ( n8520 , n4976 );
not ( n8521 , n6474 );
buf ( n8522 , n4977 );
and ( n8523 , n8521 , n8522 );
buf ( n8524 , n4978 );
xor ( n8525 , n8524 , n8522 );
and ( n8526 , n8525 , n6474 );
or ( n8527 , n8523 , n8526 );
buf ( n8528 , n4979 );
xor ( n8529 , n8527 , n8528 );
buf ( n8530 , n4980 );
xor ( n8531 , n8529 , n8530 );
buf ( n8532 , n4981 );
xor ( n8533 , n8531 , n8532 );
buf ( n8534 , n4982 );
xor ( n8535 , n8533 , n8534 );
xor ( n8536 , n8520 , n8535 );
xor ( n8537 , n8536 , n6763 );
and ( n8538 , n8519 , n8537 );
xor ( n8539 , n8474 , n8538 );
xor ( n8540 , n8472 , n8539 );
xor ( n8541 , n8401 , n8314 );
xor ( n8542 , n8541 , n8336 );
not ( n8543 , n6474 );
buf ( n8544 , n4983 );
and ( n8545 , n8543 , n8544 );
buf ( n8546 , n4984 );
xor ( n8547 , n8546 , n8544 );
and ( n8548 , n8547 , n6474 );
or ( n8549 , n8545 , n8548 );
xor ( n8550 , n8549 , n7710 );
xor ( n8551 , n8550 , n7732 );
not ( n8552 , n8551 );
buf ( n8553 , n4985 );
not ( n8554 , n6474 );
buf ( n8555 , n4986 );
and ( n8556 , n8554 , n8555 );
buf ( n8557 , n4987 );
xor ( n8558 , n8557 , n8555 );
and ( n8559 , n8558 , n6474 );
or ( n8560 , n8556 , n8559 );
not ( n8561 , n6474 );
buf ( n8562 , n4988 );
and ( n8563 , n8561 , n8562 );
buf ( n8564 , n4989 );
xor ( n8565 , n8564 , n8562 );
and ( n8566 , n8565 , n6474 );
or ( n8567 , n8563 , n8566 );
xor ( n8568 , n8560 , n8567 );
buf ( n8569 , n4990 );
xor ( n8570 , n8568 , n8569 );
buf ( n8571 , n4991 );
xor ( n8572 , n8570 , n8571 );
buf ( n8573 , n4992 );
xor ( n8574 , n8572 , n8573 );
xor ( n8575 , n8553 , n8574 );
xor ( n8576 , n8575 , n7441 );
and ( n8577 , n8552 , n8576 );
xor ( n8578 , n8542 , n8577 );
xor ( n8579 , n8540 , n8578 );
not ( n8580 , n6474 );
buf ( n8581 , n4993 );
and ( n8582 , n8580 , n8581 );
buf ( n8583 , n4994 );
xor ( n8584 , n8583 , n8581 );
and ( n8585 , n8584 , n6474 );
or ( n8586 , n8582 , n8585 );
not ( n8587 , n6474 );
buf ( n8588 , n4995 );
and ( n8589 , n8587 , n8588 );
buf ( n8590 , n4996 );
xor ( n8591 , n8590 , n8588 );
and ( n8592 , n8591 , n6474 );
or ( n8593 , n8589 , n8592 );
xor ( n8594 , n7801 , n8593 );
buf ( n8595 , n4997 );
xor ( n8596 , n8594 , n8595 );
buf ( n8597 , n4998 );
xor ( n8598 , n8596 , n8597 );
buf ( n8599 , n4999 );
xor ( n8600 , n8598 , n8599 );
xor ( n8601 , n8586 , n8600 );
not ( n8602 , n6474 );
buf ( n8603 , n5000 );
and ( n8604 , n8602 , n8603 );
buf ( n8605 , n5001 );
xor ( n8606 , n8605 , n8603 );
and ( n8607 , n8606 , n6474 );
or ( n8608 , n8604 , n8607 );
not ( n8609 , n6474 );
buf ( n8610 , n5002 );
and ( n8611 , n8609 , n8610 );
buf ( n8612 , n5003 );
xor ( n8613 , n8612 , n8610 );
and ( n8614 , n8613 , n6474 );
or ( n8615 , n8611 , n8614 );
xor ( n8616 , n8608 , n8615 );
buf ( n8617 , n5004 );
xor ( n8618 , n8616 , n8617 );
buf ( n8619 , n5005 );
xor ( n8620 , n8618 , n8619 );
buf ( n8621 , n5006 );
xor ( n8622 , n8620 , n8621 );
xor ( n8623 , n8601 , n8622 );
not ( n8624 , n6474 );
buf ( n8625 , n5007 );
and ( n8626 , n8624 , n8625 );
buf ( n8627 , n5008 );
xor ( n8628 , n8627 , n8625 );
and ( n8629 , n8628 , n6474 );
or ( n8630 , n8626 , n8629 );
buf ( n8631 , n5009 );
xor ( n8632 , n8630 , n8631 );
buf ( n8633 , n5010 );
xor ( n8634 , n8632 , n8633 );
buf ( n8635 , n5011 );
xor ( n8636 , n8634 , n8635 );
buf ( n8637 , n5012 );
xor ( n8638 , n8636 , n8637 );
xor ( n8639 , n7581 , n8638 );
not ( n8640 , n6474 );
buf ( n8641 , n5013 );
and ( n8642 , n8640 , n8641 );
buf ( n8643 , n5014 );
xor ( n8644 , n8643 , n8641 );
and ( n8645 , n8644 , n6474 );
or ( n8646 , n8642 , n8645 );
not ( n8647 , n6474 );
buf ( n8648 , n5015 );
and ( n8649 , n8647 , n8648 );
buf ( n8650 , n5016 );
xor ( n8651 , n8650 , n8648 );
and ( n8652 , n8651 , n6474 );
or ( n8653 , n8649 , n8652 );
xor ( n8654 , n8646 , n8653 );
buf ( n8655 , n5017 );
xor ( n8656 , n8654 , n8655 );
buf ( n8657 , n5018 );
xor ( n8658 , n8656 , n8657 );
buf ( n8659 , n5019 );
xor ( n8660 , n8658 , n8659 );
xor ( n8661 , n8639 , n8660 );
not ( n8662 , n8661 );
buf ( n8663 , n5020 );
xor ( n8664 , n8663 , n7659 );
xor ( n8665 , n8664 , n7681 );
and ( n8666 , n8662 , n8665 );
xor ( n8667 , n8623 , n8666 );
xor ( n8668 , n8579 , n8667 );
not ( n8669 , n6474 );
buf ( n8670 , n5021 );
and ( n8671 , n8669 , n8670 );
buf ( n8672 , n5022 );
xor ( n8673 , n8672 , n8670 );
and ( n8674 , n8673 , n6474 );
or ( n8675 , n8671 , n8674 );
not ( n8676 , n6474 );
buf ( n8677 , n5023 );
and ( n8678 , n8676 , n8677 );
buf ( n8679 , n5024 );
xor ( n8680 , n8679 , n8677 );
and ( n8681 , n8680 , n6474 );
or ( n8682 , n8678 , n8681 );
not ( n8683 , n6474 );
buf ( n8684 , n5025 );
and ( n8685 , n8683 , n8684 );
buf ( n8686 , n5026 );
xor ( n8687 , n8686 , n8684 );
and ( n8688 , n8687 , n6474 );
or ( n8689 , n8685 , n8688 );
xor ( n8690 , n8682 , n8689 );
buf ( n8691 , n5027 );
xor ( n8692 , n8690 , n8691 );
buf ( n8693 , n5028 );
xor ( n8694 , n8692 , n8693 );
buf ( n8695 , n5029 );
xor ( n8696 , n8694 , n8695 );
xor ( n8697 , n8675 , n8696 );
not ( n8698 , n6474 );
buf ( n8699 , n5030 );
and ( n8700 , n8698 , n8699 );
buf ( n8701 , n5031 );
xor ( n8702 , n8701 , n8699 );
and ( n8703 , n8702 , n6474 );
or ( n8704 , n8700 , n8703 );
xor ( n8705 , n8704 , n7741 );
buf ( n8706 , n5032 );
xor ( n8707 , n8705 , n8706 );
buf ( n8708 , n5033 );
xor ( n8709 , n8707 , n8708 );
xor ( n8710 , n8709 , n7009 );
xor ( n8711 , n8697 , n8710 );
not ( n8712 , n6474 );
buf ( n8713 , n5034 );
and ( n8714 , n8712 , n8713 );
buf ( n8715 , n5035 );
xor ( n8716 , n8715 , n8713 );
and ( n8717 , n8716 , n6474 );
or ( n8718 , n8714 , n8717 );
xor ( n8719 , n8718 , n8188 );
xor ( n8720 , n8719 , n8204 );
not ( n8721 , n8720 );
buf ( n8722 , n5036 );
not ( n8723 , n6474 );
buf ( n8724 , n5037 );
and ( n8725 , n8723 , n8724 );
buf ( n8726 , n5038 );
xor ( n8727 , n8726 , n8724 );
and ( n8728 , n8727 , n6474 );
or ( n8729 , n8725 , n8728 );
not ( n8730 , n6474 );
buf ( n8731 , n5039 );
and ( n8732 , n8730 , n8731 );
buf ( n8733 , n5040 );
xor ( n8734 , n8733 , n8731 );
and ( n8735 , n8734 , n6474 );
or ( n8736 , n8732 , n8735 );
xor ( n8737 , n8729 , n8736 );
buf ( n8738 , n5041 );
xor ( n8739 , n8737 , n8738 );
buf ( n8740 , n5042 );
xor ( n8741 , n8739 , n8740 );
buf ( n8742 , n5043 );
xor ( n8743 , n8741 , n8742 );
xor ( n8744 , n8722 , n8743 );
not ( n8745 , n6474 );
buf ( n8746 , n5044 );
and ( n8747 , n8745 , n8746 );
buf ( n8748 , n5045 );
xor ( n8749 , n8748 , n8746 );
and ( n8750 , n8749 , n6474 );
or ( n8751 , n8747 , n8750 );
not ( n8752 , n6474 );
buf ( n8753 , n5046 );
and ( n8754 , n8752 , n8753 );
buf ( n8755 , n5047 );
xor ( n8756 , n8755 , n8753 );
and ( n8757 , n8756 , n6474 );
or ( n8758 , n8754 , n8757 );
xor ( n8759 , n8751 , n8758 );
buf ( n8760 , n5048 );
xor ( n8761 , n8759 , n8760 );
xor ( n8762 , n8761 , n8254 );
buf ( n8763 , n5049 );
xor ( n8764 , n8762 , n8763 );
xor ( n8765 , n8744 , n8764 );
and ( n8766 , n8721 , n8765 );
xor ( n8767 , n8711 , n8766 );
xor ( n8768 , n8668 , n8767 );
xor ( n8769 , n8393 , n8768 );
not ( n8770 , n8769 );
not ( n8771 , n6474 );
buf ( n8772 , n5050 );
and ( n8773 , n8771 , n8772 );
buf ( n8774 , n5051 );
xor ( n8775 , n8774 , n8772 );
and ( n8776 , n8775 , n6474 );
or ( n8777 , n8773 , n8776 );
xor ( n8778 , n8777 , n7095 );
not ( n8779 , n6474 );
buf ( n8780 , n5052 );
and ( n8781 , n8779 , n8780 );
buf ( n8782 , n5053 );
xor ( n8783 , n8782 , n8780 );
and ( n8784 , n8783 , n6474 );
or ( n8785 , n8781 , n8784 );
not ( n8786 , n6474 );
buf ( n8787 , n5054 );
and ( n8788 , n8786 , n8787 );
buf ( n8789 , n5055 );
xor ( n8790 , n8789 , n8787 );
and ( n8791 , n8790 , n6474 );
or ( n8792 , n8788 , n8791 );
xor ( n8793 , n8785 , n8792 );
buf ( n8794 , n5056 );
xor ( n8795 , n8793 , n8794 );
buf ( n8796 , n5057 );
xor ( n8797 , n8795 , n8796 );
buf ( n8798 , n5058 );
xor ( n8799 , n8797 , n8798 );
xor ( n8800 , n8778 , n8799 );
not ( n8801 , n6474 );
buf ( n8802 , n5059 );
and ( n8803 , n8801 , n8802 );
buf ( n8804 , n5060 );
xor ( n8805 , n8804 , n8802 );
and ( n8806 , n8805 , n6474 );
or ( n8807 , n8803 , n8806 );
not ( n8808 , n6474 );
buf ( n8809 , n5061 );
and ( n8810 , n8808 , n8809 );
buf ( n8811 , n5062 );
xor ( n8812 , n8811 , n8809 );
and ( n8813 , n8812 , n6474 );
or ( n8814 , n8810 , n8813 );
xor ( n8815 , n8814 , n7283 );
buf ( n8816 , n5063 );
xor ( n8817 , n8815 , n8816 );
xor ( n8818 , n8817 , n6697 );
buf ( n8819 , n5064 );
xor ( n8820 , n8818 , n8819 );
xor ( n8821 , n8807 , n8820 );
not ( n8822 , n6474 );
buf ( n8823 , n5065 );
and ( n8824 , n8822 , n8823 );
buf ( n8825 , n5066 );
xor ( n8826 , n8825 , n8823 );
and ( n8827 , n8826 , n6474 );
or ( n8828 , n8824 , n8827 );
not ( n8829 , n6474 );
buf ( n8830 , n5067 );
and ( n8831 , n8829 , n8830 );
buf ( n8832 , n5068 );
xor ( n8833 , n8832 , n8830 );
and ( n8834 , n8833 , n6474 );
or ( n8835 , n8831 , n8834 );
xor ( n8836 , n8828 , n8835 );
buf ( n8837 , n5069 );
xor ( n8838 , n8836 , n8837 );
buf ( n8839 , n5070 );
xor ( n8840 , n8838 , n8839 );
buf ( n8841 , n5071 );
xor ( n8842 , n8840 , n8841 );
xor ( n8843 , n8821 , n8842 );
not ( n8844 , n8843 );
not ( n8845 , n6474 );
buf ( n8846 , n5072 );
and ( n8847 , n8845 , n8846 );
buf ( n8848 , n5073 );
xor ( n8849 , n8848 , n8846 );
and ( n8850 , n8849 , n6474 );
or ( n8851 , n8847 , n8850 );
not ( n8852 , n6474 );
buf ( n8853 , n5074 );
and ( n8854 , n8852 , n8853 );
buf ( n8855 , n5075 );
xor ( n8856 , n8855 , n8853 );
and ( n8857 , n8856 , n6474 );
or ( n8858 , n8854 , n8857 );
xor ( n8859 , n8851 , n8858 );
buf ( n8860 , n5076 );
xor ( n8861 , n8859 , n8860 );
buf ( n8862 , n5077 );
xor ( n8863 , n8861 , n8862 );
buf ( n8864 , n5078 );
xor ( n8865 , n8863 , n8864 );
xor ( n8866 , n7727 , n8865 );
xor ( n8867 , n8866 , n7253 );
and ( n8868 , n8844 , n8867 );
xor ( n8869 , n8800 , n8868 );
buf ( n8870 , n5079 );
not ( n8871 , n6474 );
buf ( n8872 , n5080 );
and ( n8873 , n8871 , n8872 );
buf ( n8874 , n5081 );
xor ( n8875 , n8874 , n8872 );
and ( n8876 , n8875 , n6474 );
or ( n8877 , n8873 , n8876 );
not ( n8878 , n6474 );
buf ( n8879 , n5082 );
and ( n8880 , n8878 , n8879 );
buf ( n8881 , n5083 );
xor ( n8882 , n8881 , n8879 );
and ( n8883 , n8882 , n6474 );
or ( n8884 , n8880 , n8883 );
xor ( n8885 , n8877 , n8884 );
buf ( n8886 , n5084 );
xor ( n8887 , n8885 , n8886 );
buf ( n8888 , n5085 );
xor ( n8889 , n8887 , n8888 );
buf ( n8890 , n5086 );
xor ( n8891 , n8889 , n8890 );
xor ( n8892 , n8870 , n8891 );
not ( n8893 , n6474 );
buf ( n8894 , n5087 );
and ( n8895 , n8893 , n8894 );
buf ( n8896 , n5088 );
xor ( n8897 , n8896 , n8894 );
and ( n8898 , n8897 , n6474 );
or ( n8899 , n8895 , n8898 );
not ( n8900 , n6474 );
buf ( n8901 , n5089 );
and ( n8902 , n8900 , n8901 );
buf ( n8903 , n5090 );
xor ( n8904 , n8903 , n8901 );
and ( n8905 , n8904 , n6474 );
or ( n8906 , n8902 , n8905 );
xor ( n8907 , n8899 , n8906 );
buf ( n8908 , n5091 );
xor ( n8909 , n8907 , n8908 );
buf ( n8910 , n5092 );
xor ( n8911 , n8909 , n8910 );
buf ( n8912 , n5093 );
xor ( n8913 , n8911 , n8912 );
xor ( n8914 , n8892 , n8913 );
not ( n8915 , n6474 );
buf ( n8916 , n5094 );
and ( n8917 , n8915 , n8916 );
buf ( n8918 , n5095 );
xor ( n8919 , n8918 , n8916 );
and ( n8920 , n8919 , n6474 );
or ( n8921 , n8917 , n8920 );
not ( n8922 , n6474 );
buf ( n8923 , n5096 );
and ( n8924 , n8922 , n8923 );
buf ( n8925 , n5097 );
xor ( n8926 , n8925 , n8923 );
and ( n8927 , n8926 , n6474 );
or ( n8928 , n8924 , n8927 );
buf ( n8929 , n5098 );
xor ( n8930 , n8928 , n8929 );
xor ( n8931 , n8930 , n7051 );
buf ( n8932 , n5099 );
xor ( n8933 , n8931 , n8932 );
buf ( n8934 , n5100 );
xor ( n8935 , n8933 , n8934 );
xor ( n8936 , n8921 , n8935 );
not ( n8937 , n6474 );
buf ( n8938 , n5101 );
and ( n8939 , n8937 , n8938 );
buf ( n8940 , n5102 );
xor ( n8941 , n8940 , n8938 );
and ( n8942 , n8941 , n6474 );
or ( n8943 , n8939 , n8942 );
xor ( n8944 , n8777 , n8943 );
buf ( n8945 , n5103 );
xor ( n8946 , n8944 , n8945 );
buf ( n8947 , n5104 );
xor ( n8948 , n8946 , n8947 );
buf ( n8949 , n5105 );
xor ( n8950 , n8948 , n8949 );
xor ( n8951 , n8936 , n8950 );
not ( n8952 , n8951 );
not ( n8953 , n6474 );
buf ( n8954 , n5106 );
and ( n8955 , n8953 , n8954 );
buf ( n8956 , n5107 );
xor ( n8957 , n8956 , n8954 );
and ( n8958 , n8957 , n6474 );
or ( n8959 , n8955 , n8958 );
not ( n8960 , n6474 );
buf ( n8961 , n5108 );
and ( n8962 , n8960 , n8961 );
buf ( n8963 , n5109 );
xor ( n8964 , n8963 , n8961 );
and ( n8965 , n8964 , n6474 );
or ( n8966 , n8962 , n8965 );
xor ( n8967 , n8959 , n8966 );
buf ( n8968 , n5110 );
xor ( n8969 , n8967 , n8968 );
buf ( n8970 , n5111 );
xor ( n8971 , n8969 , n8970 );
xor ( n8972 , n8971 , n7426 );
xor ( n8973 , n6906 , n8972 );
xor ( n8974 , n8973 , n7822 );
and ( n8975 , n8952 , n8974 );
xor ( n8976 , n8914 , n8975 );
buf ( n8977 , n5112 );
xor ( n8978 , n8977 , n8447 );
xor ( n8979 , n8978 , n8469 );
not ( n8980 , n6474 );
buf ( n8981 , n5113 );
and ( n8982 , n8980 , n8981 );
buf ( n8983 , n5114 );
xor ( n8984 , n8983 , n8981 );
and ( n8985 , n8984 , n6474 );
or ( n8986 , n8982 , n8985 );
xor ( n8987 , n8986 , n7181 );
not ( n8988 , n6474 );
buf ( n8989 , n5115 );
and ( n8990 , n8988 , n8989 );
buf ( n8991 , n5116 );
xor ( n8992 , n8991 , n8989 );
and ( n8993 , n8992 , n6474 );
or ( n8994 , n8990 , n8993 );
buf ( n8995 , n5117 );
xor ( n8996 , n8994 , n8995 );
buf ( n8997 , n5118 );
xor ( n8998 , n8996 , n8997 );
buf ( n8999 , n5119 );
xor ( n9000 , n8998 , n8999 );
buf ( n9001 , n5120 );
xor ( n9002 , n9000 , n9001 );
xor ( n9003 , n8987 , n9002 );
not ( n9004 , n9003 );
buf ( n9005 , n5121 );
not ( n9006 , n6474 );
buf ( n9007 , n5122 );
and ( n9008 , n9006 , n9007 );
buf ( n9009 , n5123 );
xor ( n9010 , n9009 , n9007 );
and ( n9011 , n9010 , n6474 );
or ( n9012 , n9008 , n9011 );
not ( n9013 , n6474 );
buf ( n9014 , n5124 );
and ( n9015 , n9013 , n9014 );
buf ( n9016 , n5125 );
xor ( n9017 , n9016 , n9014 );
and ( n9018 , n9017 , n6474 );
or ( n9019 , n9015 , n9018 );
xor ( n9020 , n9012 , n9019 );
buf ( n9021 , n5126 );
xor ( n9022 , n9020 , n9021 );
buf ( n9023 , n5127 );
xor ( n9024 , n9022 , n9023 );
buf ( n9025 , n5128 );
xor ( n9026 , n9024 , n9025 );
xor ( n9027 , n9005 , n9026 );
not ( n9028 , n6474 );
buf ( n9029 , n5129 );
and ( n9030 , n9028 , n9029 );
buf ( n9031 , n5130 );
xor ( n9032 , n9031 , n9029 );
and ( n9033 , n9032 , n6474 );
or ( n9034 , n9030 , n9033 );
not ( n9035 , n6474 );
buf ( n9036 , n5131 );
and ( n9037 , n9035 , n9036 );
buf ( n9038 , n5132 );
xor ( n9039 , n9038 , n9036 );
and ( n9040 , n9039 , n6474 );
or ( n9041 , n9037 , n9040 );
xor ( n9042 , n9034 , n9041 );
xor ( n9043 , n9042 , n8520 );
buf ( n9044 , n5133 );
xor ( n9045 , n9043 , n9044 );
buf ( n9046 , n5134 );
xor ( n9047 , n9045 , n9046 );
xor ( n9048 , n9027 , n9047 );
and ( n9049 , n9004 , n9048 );
xor ( n9050 , n8979 , n9049 );
xor ( n9051 , n8976 , n9050 );
xor ( n9052 , n8136 , n7046 );
xor ( n9053 , n9052 , n8414 );
not ( n9054 , n8800 );
and ( n9055 , n9054 , n8843 );
xor ( n9056 , n9053 , n9055 );
xor ( n9057 , n9051 , n9056 );
buf ( n9058 , n5135 );
not ( n9059 , n6474 );
buf ( n9060 , n5136 );
and ( n9061 , n9059 , n9060 );
buf ( n9062 , n5137 );
xor ( n9063 , n9062 , n9060 );
and ( n9064 , n9063 , n6474 );
or ( n9065 , n9061 , n9064 );
not ( n9066 , n6474 );
buf ( n9067 , n5138 );
and ( n9068 , n9066 , n9067 );
buf ( n9069 , n5139 );
xor ( n9070 , n9069 , n9067 );
and ( n9071 , n9070 , n6474 );
or ( n9072 , n9068 , n9071 );
xor ( n9073 , n9065 , n9072 );
buf ( n9074 , n5140 );
xor ( n9075 , n9073 , n9074 );
buf ( n9076 , n5141 );
xor ( n9077 , n9075 , n9076 );
buf ( n9078 , n5142 );
xor ( n9079 , n9077 , n9078 );
xor ( n9080 , n9058 , n9079 );
not ( n9081 , n6474 );
buf ( n9082 , n5143 );
and ( n9083 , n9081 , n9082 );
buf ( n9084 , n5144 );
xor ( n9085 , n9084 , n9082 );
and ( n9086 , n9085 , n6474 );
or ( n9087 , n9083 , n9086 );
buf ( n9088 , n5145 );
xor ( n9089 , n9087 , n9088 );
xor ( n9090 , n9089 , n8722 );
buf ( n9091 , n5146 );
xor ( n9092 , n9090 , n9091 );
buf ( n9093 , n5147 );
xor ( n9094 , n9092 , n9093 );
xor ( n9095 , n9080 , n9094 );
not ( n9096 , n6474 );
buf ( n9097 , n5148 );
and ( n9098 , n9096 , n9097 );
buf ( n9099 , n5149 );
xor ( n9100 , n9099 , n9097 );
and ( n9101 , n9100 , n6474 );
or ( n9102 , n9098 , n9101 );
not ( n9103 , n6474 );
buf ( n9104 , n5150 );
and ( n9105 , n9103 , n9104 );
buf ( n9106 , n5151 );
xor ( n9107 , n9106 , n9104 );
and ( n9108 , n9107 , n6474 );
or ( n9109 , n9105 , n9108 );
not ( n9110 , n6474 );
buf ( n9111 , n5152 );
and ( n9112 , n9110 , n9111 );
buf ( n9113 , n5153 );
xor ( n9114 , n9113 , n9111 );
and ( n9115 , n9114 , n6474 );
or ( n9116 , n9112 , n9115 );
xor ( n9117 , n9109 , n9116 );
buf ( n9118 , n5154 );
xor ( n9119 , n9117 , n9118 );
buf ( n9120 , n5155 );
xor ( n9121 , n9119 , n9120 );
buf ( n9122 , n5156 );
xor ( n9123 , n9121 , n9122 );
xor ( n9124 , n9102 , n9123 );
xor ( n9125 , n9124 , n7659 );
not ( n9126 , n9125 );
not ( n9127 , n6474 );
buf ( n9128 , n5157 );
and ( n9129 , n9127 , n9128 );
buf ( n9130 , n5158 );
xor ( n9131 , n9130 , n9128 );
and ( n9132 , n9131 , n6474 );
or ( n9133 , n9129 , n9132 );
not ( n9134 , n6474 );
buf ( n9135 , n5159 );
and ( n9136 , n9134 , n9135 );
buf ( n9137 , n5160 );
xor ( n9138 , n9137 , n9135 );
and ( n9139 , n9138 , n6474 );
or ( n9140 , n9136 , n9139 );
buf ( n9141 , n5161 );
xor ( n9142 , n9140 , n9141 );
buf ( n9143 , n5162 );
xor ( n9144 , n9142 , n9143 );
buf ( n9145 , n5163 );
xor ( n9146 , n9144 , n9145 );
buf ( n9147 , n5164 );
xor ( n9148 , n9146 , n9147 );
xor ( n9149 , n9133 , n9148 );
not ( n9150 , n6474 );
buf ( n9151 , n5165 );
and ( n9152 , n9150 , n9151 );
buf ( n9153 , n5166 );
xor ( n9154 , n9153 , n9151 );
and ( n9155 , n9154 , n6474 );
or ( n9156 , n9152 , n9155 );
not ( n9157 , n6474 );
buf ( n9158 , n5167 );
and ( n9159 , n9157 , n9158 );
buf ( n9160 , n5168 );
xor ( n9161 , n9160 , n9158 );
and ( n9162 , n9161 , n6474 );
or ( n9163 , n9159 , n9162 );
xor ( n9164 , n9156 , n9163 );
buf ( n9165 , n5169 );
xor ( n9166 , n9164 , n9165 );
buf ( n9167 , n5170 );
xor ( n9168 , n9166 , n9167 );
buf ( n9169 , n5171 );
xor ( n9170 , n9168 , n9169 );
xor ( n9171 , n9149 , n9170 );
and ( n9172 , n9126 , n9171 );
xor ( n9173 , n9095 , n9172 );
xor ( n9174 , n9057 , n9173 );
buf ( n9175 , n5172 );
not ( n9176 , n6474 );
buf ( n9177 , n5173 );
and ( n9178 , n9176 , n9177 );
buf ( n9179 , n5174 );
xor ( n9180 , n9179 , n9177 );
and ( n9181 , n9180 , n6474 );
or ( n9182 , n9178 , n9181 );
not ( n9183 , n6474 );
buf ( n9184 , n5175 );
and ( n9185 , n9183 , n9184 );
buf ( n9186 , n5176 );
xor ( n9187 , n9186 , n9184 );
and ( n9188 , n9187 , n6474 );
or ( n9189 , n9185 , n9188 );
xor ( n9190 , n9182 , n9189 );
buf ( n9191 , n5177 );
xor ( n9192 , n9190 , n9191 );
xor ( n9193 , n9192 , n7097 );
buf ( n9194 , n5178 );
xor ( n9195 , n9193 , n9194 );
xor ( n9196 , n9175 , n9195 );
not ( n9197 , n6474 );
buf ( n9198 , n5179 );
and ( n9199 , n9197 , n9198 );
buf ( n9200 , n5180 );
xor ( n9201 , n9200 , n9198 );
and ( n9202 , n9201 , n6474 );
or ( n9203 , n9199 , n9202 );
not ( n9204 , n6474 );
buf ( n9205 , n5181 );
and ( n9206 , n9204 , n9205 );
buf ( n9207 , n5182 );
xor ( n9208 , n9207 , n9205 );
and ( n9209 , n9208 , n6474 );
or ( n9210 , n9206 , n9209 );
xor ( n9211 , n9203 , n9210 );
buf ( n9212 , n5183 );
xor ( n9213 , n9211 , n9212 );
buf ( n9214 , n5184 );
xor ( n9215 , n9213 , n9214 );
buf ( n9216 , n5185 );
xor ( n9217 , n9215 , n9216 );
xor ( n9218 , n9196 , n9217 );
not ( n9219 , n6474 );
buf ( n9220 , n5186 );
and ( n9221 , n9219 , n9220 );
buf ( n9222 , n5187 );
xor ( n9223 , n9222 , n9220 );
and ( n9224 , n9223 , n6474 );
or ( n9225 , n9221 , n9224 );
not ( n9226 , n6474 );
buf ( n9227 , n5188 );
and ( n9228 , n9226 , n9227 );
buf ( n9229 , n5189 );
xor ( n9230 , n9229 , n9227 );
and ( n9231 , n9230 , n6474 );
or ( n9232 , n9228 , n9231 );
xor ( n9233 , n9232 , n8422 );
buf ( n9234 , n5190 );
xor ( n9235 , n9233 , n9234 );
xor ( n9236 , n9235 , n8020 );
buf ( n9237 , n5191 );
xor ( n9238 , n9236 , n9237 );
xor ( n9239 , n9225 , n9238 );
not ( n9240 , n6474 );
buf ( n9241 , n5192 );
and ( n9242 , n9240 , n9241 );
buf ( n9243 , n5193 );
xor ( n9244 , n9243 , n9241 );
and ( n9245 , n9244 , n6474 );
or ( n9246 , n9242 , n9245 );
not ( n9247 , n6474 );
buf ( n9248 , n5194 );
and ( n9249 , n9247 , n9248 );
buf ( n9250 , n5195 );
xor ( n9251 , n9250 , n9248 );
and ( n9252 , n9251 , n6474 );
or ( n9253 , n9249 , n9252 );
xor ( n9254 , n9246 , n9253 );
buf ( n9255 , n5196 );
xor ( n9256 , n9254 , n9255 );
buf ( n9257 , n5197 );
xor ( n9258 , n9256 , n9257 );
buf ( n9259 , n5198 );
xor ( n9260 , n9258 , n9259 );
xor ( n9261 , n9239 , n9260 );
not ( n9262 , n9261 );
not ( n9263 , n6474 );
buf ( n9264 , n5199 );
and ( n9265 , n9263 , n9264 );
buf ( n9266 , n5200 );
xor ( n9267 , n9266 , n9264 );
and ( n9268 , n9267 , n6474 );
or ( n9269 , n9265 , n9268 );
not ( n9270 , n6474 );
buf ( n9271 , n5201 );
and ( n9272 , n9270 , n9271 );
buf ( n9273 , n5202 );
xor ( n9274 , n9273 , n9271 );
and ( n9275 , n9274 , n6474 );
or ( n9276 , n9272 , n9275 );
not ( n9277 , n6474 );
buf ( n9278 , n5203 );
and ( n9279 , n9277 , n9278 );
buf ( n9280 , n5204 );
xor ( n9281 , n9280 , n9278 );
and ( n9282 , n9281 , n6474 );
or ( n9283 , n9279 , n9282 );
xor ( n9284 , n9276 , n9283 );
buf ( n9285 , n5205 );
xor ( n9286 , n9284 , n9285 );
buf ( n9287 , n5206 );
xor ( n9288 , n9286 , n9287 );
buf ( n9289 , n5207 );
xor ( n9290 , n9288 , n9289 );
xor ( n9291 , n9269 , n9290 );
not ( n9292 , n6474 );
buf ( n9293 , n5208 );
and ( n9294 , n9292 , n9293 );
buf ( n9295 , n5209 );
xor ( n9296 , n9295 , n9293 );
and ( n9297 , n9296 , n6474 );
or ( n9298 , n9294 , n9297 );
buf ( n9299 , n5210 );
xor ( n9300 , n9298 , n9299 );
buf ( n9301 , n5211 );
xor ( n9302 , n9300 , n9301 );
buf ( n9303 , n5212 );
xor ( n9304 , n9302 , n9303 );
buf ( n9305 , n5213 );
xor ( n9306 , n9304 , n9305 );
xor ( n9307 , n9291 , n9306 );
and ( n9308 , n9262 , n9307 );
xor ( n9309 , n9218 , n9308 );
xor ( n9310 , n9174 , n9309 );
xor ( n9311 , n8869 , n9310 );
xor ( n9312 , n7456 , n8249 );
xor ( n9313 , n9312 , n6500 );
buf ( n9314 , n5214 );
xor ( n9315 , n9314 , n6913 );
xor ( n9316 , n9315 , n8600 );
not ( n9317 , n9316 );
buf ( n9318 , n5215 );
not ( n9319 , n6474 );
buf ( n9320 , n5215 );
and ( n9321 , n9319 , n9320 );
buf ( n9322 , n5216 );
xor ( n9323 , n9322 , n9320 );
and ( n9324 , n9323 , n6474 );
or ( n9325 , n9321 , n9324 );
not ( n9326 , n6474 );
buf ( n9327 , n5215 );
and ( n9328 , n9326 , n9327 );
buf ( n9329 , n5217 );
xor ( n9330 , n9329 , n9327 );
and ( n9331 , n9330 , n6474 );
or ( n9332 , n9328 , n9331 );
xor ( n9333 , n9325 , n9332 );
buf ( n9334 , n5218 );
xor ( n9335 , n9333 , n9334 );
buf ( n9336 , n5219 );
xor ( n9337 , n9335 , n9336 );
xor ( n9338 , n9337 , n6742 );
xor ( n9339 , n9318 , n9338 );
not ( n9340 , n6474 );
buf ( n9341 , n5220 );
and ( n9342 , n9340 , n9341 );
buf ( n9343 , n5221 );
xor ( n9344 , n9343 , n9341 );
and ( n9345 , n9344 , n6474 );
or ( n9346 , n9342 , n9345 );
buf ( n9347 , n5222 );
xor ( n9348 , n9346 , n9347 );
buf ( n9349 , n5223 );
xor ( n9350 , n9348 , n9349 );
buf ( n9351 , n5224 );
xor ( n9352 , n9350 , n9351 );
buf ( n9353 , n5225 );
xor ( n9354 , n9352 , n9353 );
xor ( n9355 , n9339 , n9354 );
and ( n9356 , n9317 , n9355 );
xor ( n9357 , n9313 , n9356 );
not ( n9358 , n6474 );
buf ( n9359 , n5226 );
and ( n9360 , n9358 , n9359 );
buf ( n9361 , n5227 );
xor ( n9362 , n9361 , n9359 );
and ( n9363 , n9362 , n6474 );
or ( n9364 , n9360 , n9363 );
not ( n9365 , n6474 );
buf ( n9366 , n5228 );
and ( n9367 , n9365 , n9366 );
buf ( n9368 , n5229 );
xor ( n9369 , n9368 , n9366 );
and ( n9370 , n9369 , n6474 );
or ( n9371 , n9367 , n9370 );
xor ( n9372 , n9364 , n9371 );
buf ( n9373 , n5230 );
xor ( n9374 , n9372 , n9373 );
buf ( n9375 , n5231 );
xor ( n9376 , n9374 , n9375 );
buf ( n9377 , n5232 );
xor ( n9378 , n9376 , n9377 );
xor ( n9379 , n8528 , n9378 );
not ( n9380 , n6474 );
buf ( n9381 , n5233 );
and ( n9382 , n9380 , n9381 );
buf ( n9383 , n5234 );
xor ( n9384 , n9383 , n9381 );
and ( n9385 , n9384 , n6474 );
or ( n9386 , n9382 , n9385 );
not ( n9387 , n6474 );
buf ( n9388 , n5235 );
and ( n9389 , n9387 , n9388 );
buf ( n9390 , n5236 );
xor ( n9391 , n9390 , n9388 );
and ( n9392 , n9391 , n6474 );
or ( n9393 , n9389 , n9392 );
xor ( n9394 , n9386 , n9393 );
buf ( n9395 , n5237 );
xor ( n9396 , n9394 , n9395 );
buf ( n9397 , n5238 );
xor ( n9398 , n9396 , n9397 );
buf ( n9399 , n5239 );
xor ( n9400 , n9398 , n9399 );
xor ( n9401 , n9379 , n9400 );
buf ( n9402 , n5240 );
not ( n9403 , n6474 );
buf ( n9404 , n5241 );
and ( n9405 , n9403 , n9404 );
buf ( n9406 , n5242 );
xor ( n9407 , n9406 , n9404 );
and ( n9408 , n9407 , n6474 );
or ( n9409 , n9405 , n9408 );
buf ( n9410 , n5243 );
xor ( n9411 , n9409 , n9410 );
buf ( n9412 , n5244 );
xor ( n9413 , n9411 , n9412 );
buf ( n9414 , n5245 );
xor ( n9415 , n9413 , n9414 );
buf ( n9416 , n5246 );
xor ( n9417 , n9415 , n9416 );
xor ( n9418 , n9402 , n9417 );
not ( n9419 , n6474 );
buf ( n9420 , n5247 );
and ( n9421 , n9419 , n9420 );
buf ( n9422 , n5248 );
xor ( n9423 , n9422 , n9420 );
and ( n9424 , n9423 , n6474 );
or ( n9425 , n9421 , n9424 );
not ( n9426 , n6474 );
buf ( n9427 , n5249 );
and ( n9428 , n9426 , n9427 );
buf ( n9429 , n5250 );
xor ( n9430 , n9429 , n9427 );
and ( n9431 , n9430 , n6474 );
or ( n9432 , n9428 , n9431 );
xor ( n9433 , n9425 , n9432 );
buf ( n9434 , n5251 );
xor ( n9435 , n9433 , n9434 );
buf ( n9436 , n5252 );
xor ( n9437 , n9435 , n9436 );
buf ( n9438 , n5253 );
xor ( n9439 , n9437 , n9438 );
xor ( n9440 , n9418 , n9439 );
not ( n9441 , n9440 );
buf ( n9442 , n5254 );
xor ( n9443 , n9442 , n8622 );
not ( n9444 , n6474 );
buf ( n9445 , n5255 );
and ( n9446 , n9444 , n9445 );
buf ( n9447 , n5256 );
xor ( n9448 , n9447 , n9445 );
and ( n9449 , n9448 , n6474 );
or ( n9450 , n9446 , n9449 );
not ( n9451 , n6474 );
buf ( n9452 , n5257 );
and ( n9453 , n9451 , n9452 );
buf ( n9454 , n5258 );
xor ( n9455 , n9454 , n9452 );
and ( n9456 , n9455 , n6474 );
or ( n9457 , n9453 , n9456 );
xor ( n9458 , n9450 , n9457 );
buf ( n9459 , n5259 );
xor ( n9460 , n9458 , n9459 );
buf ( n9461 , n5260 );
xor ( n9462 , n9460 , n9461 );
buf ( n9463 , n5261 );
xor ( n9464 , n9462 , n9463 );
xor ( n9465 , n9443 , n9464 );
and ( n9466 , n9441 , n9465 );
xor ( n9467 , n9401 , n9466 );
xor ( n9468 , n9357 , n9467 );
not ( n9469 , n6474 );
buf ( n9470 , n5262 );
and ( n9471 , n9469 , n9470 );
buf ( n9472 , n5263 );
xor ( n9473 , n9472 , n9470 );
and ( n9474 , n9473 , n6474 );
or ( n9475 , n9471 , n9474 );
not ( n9476 , n6474 );
buf ( n9477 , n5264 );
and ( n9478 , n9476 , n9477 );
buf ( n9479 , n5265 );
xor ( n9480 , n9479 , n9477 );
and ( n9481 , n9480 , n6474 );
or ( n9482 , n9478 , n9481 );
xor ( n9483 , n9475 , n9482 );
buf ( n9484 , n5266 );
xor ( n9485 , n9483 , n9484 );
buf ( n9486 , n5267 );
xor ( n9487 , n9485 , n9486 );
buf ( n9488 , n5268 );
xor ( n9489 , n9487 , n9488 );
xor ( n9490 , n6732 , n9489 );
not ( n9491 , n6474 );
buf ( n9492 , n5269 );
and ( n9493 , n9491 , n9492 );
buf ( n9494 , n5270 );
xor ( n9495 , n9494 , n9492 );
and ( n9496 , n9495 , n6474 );
or ( n9497 , n9493 , n9496 );
not ( n9498 , n6474 );
buf ( n9499 , n5271 );
and ( n9500 , n9498 , n9499 );
buf ( n9501 , n5272 );
xor ( n9502 , n9501 , n9499 );
and ( n9503 , n9502 , n6474 );
or ( n9504 , n9500 , n9503 );
xor ( n9505 , n9497 , n9504 );
buf ( n9506 , n5273 );
xor ( n9507 , n9505 , n9506 );
buf ( n9508 , n5274 );
xor ( n9509 , n9507 , n9508 );
buf ( n9510 , n5275 );
xor ( n9511 , n9509 , n9510 );
xor ( n9512 , n9490 , n9511 );
buf ( n9513 , n5276 );
not ( n9514 , n6474 );
buf ( n9515 , n5277 );
and ( n9516 , n9514 , n9515 );
buf ( n9517 , n5278 );
xor ( n9518 , n9517 , n9515 );
and ( n9519 , n9518 , n6474 );
or ( n9520 , n9516 , n9519 );
not ( n9521 , n6474 );
buf ( n9522 , n5279 );
and ( n9523 , n9521 , n9522 );
buf ( n9524 , n5280 );
xor ( n9525 , n9524 , n9522 );
and ( n9526 , n9525 , n6474 );
or ( n9527 , n9523 , n9526 );
xor ( n9528 , n9520 , n9527 );
buf ( n9529 , n5281 );
xor ( n9530 , n9528 , n9529 );
buf ( n9531 , n5282 );
xor ( n9532 , n9530 , n9531 );
buf ( n9533 , n5283 );
xor ( n9534 , n9532 , n9533 );
xor ( n9535 , n9513 , n9534 );
buf ( n9536 , n5284 );
xor ( n9537 , n9102 , n9536 );
buf ( n9538 , n5285 );
xor ( n9539 , n9537 , n9538 );
buf ( n9540 , n5286 );
xor ( n9541 , n9539 , n9540 );
buf ( n9542 , n5287 );
xor ( n9543 , n9541 , n9542 );
xor ( n9544 , n9535 , n9543 );
not ( n9545 , n9544 );
buf ( n9546 , n5288 );
not ( n9547 , n6474 );
buf ( n9548 , n5289 );
and ( n9549 , n9547 , n9548 );
buf ( n9550 , n5290 );
xor ( n9551 , n9550 , n9548 );
and ( n9552 , n9551 , n6474 );
or ( n9553 , n9549 , n9552 );
xor ( n9554 , n9553 , n8718 );
buf ( n9555 , n5291 );
xor ( n9556 , n9554 , n9555 );
buf ( n9557 , n5292 );
xor ( n9558 , n9556 , n9557 );
xor ( n9559 , n9558 , n8167 );
xor ( n9560 , n9546 , n9559 );
not ( n9561 , n6474 );
buf ( n9562 , n5293 );
and ( n9563 , n9561 , n9562 );
buf ( n9564 , n5294 );
xor ( n9565 , n9564 , n9562 );
and ( n9566 , n9565 , n6474 );
or ( n9567 , n9563 , n9566 );
not ( n9568 , n6474 );
buf ( n9569 , n5295 );
and ( n9570 , n9568 , n9569 );
buf ( n9571 , n5296 );
xor ( n9572 , n9571 , n9569 );
and ( n9573 , n9572 , n6474 );
or ( n9574 , n9570 , n9573 );
xor ( n9575 , n9567 , n9574 );
buf ( n9576 , n5297 );
xor ( n9577 , n9575 , n9576 );
buf ( n9578 , n5298 );
xor ( n9579 , n9577 , n9578 );
buf ( n9580 , n5299 );
xor ( n9581 , n9579 , n9580 );
xor ( n9582 , n9560 , n9581 );
and ( n9583 , n9545 , n9582 );
xor ( n9584 , n9512 , n9583 );
xor ( n9585 , n9468 , n9584 );
not ( n9586 , n6474 );
buf ( n9587 , n5300 );
and ( n9588 , n9586 , n9587 );
buf ( n9589 , n5301 );
xor ( n9590 , n9589 , n9587 );
and ( n9591 , n9590 , n6474 );
or ( n9592 , n9588 , n9591 );
not ( n9593 , n6474 );
buf ( n9594 , n5302 );
and ( n9595 , n9593 , n9594 );
buf ( n9596 , n5303 );
xor ( n9597 , n9596 , n9594 );
and ( n9598 , n9597 , n6474 );
or ( n9599 , n9595 , n9598 );
xor ( n9600 , n9599 , n7840 );
buf ( n9601 , n5304 );
xor ( n9602 , n9600 , n9601 );
buf ( n9603 , n5305 );
xor ( n9604 , n9602 , n9603 );
buf ( n9605 , n5306 );
xor ( n9606 , n9604 , n9605 );
xor ( n9607 , n9592 , n9606 );
not ( n9608 , n6474 );
buf ( n9609 , n5307 );
and ( n9610 , n9608 , n9609 );
buf ( n9611 , n5308 );
xor ( n9612 , n9611 , n9609 );
and ( n9613 , n9612 , n6474 );
or ( n9614 , n9610 , n9613 );
not ( n9615 , n6474 );
buf ( n9616 , n5309 );
and ( n9617 , n9615 , n9616 );
buf ( n9618 , n5310 );
xor ( n9619 , n9618 , n9616 );
and ( n9620 , n9619 , n6474 );
or ( n9621 , n9617 , n9620 );
xor ( n9622 , n9614 , n9621 );
buf ( n9623 , n5311 );
xor ( n9624 , n9622 , n9623 );
buf ( n9625 , n5312 );
xor ( n9626 , n9624 , n9625 );
buf ( n9627 , n5313 );
xor ( n9628 , n9626 , n9627 );
xor ( n9629 , n9607 , n9628 );
buf ( n9630 , n5314 );
not ( n9631 , n6474 );
buf ( n9632 , n5315 );
and ( n9633 , n9631 , n9632 );
buf ( n9634 , n5316 );
xor ( n9635 , n9634 , n9632 );
and ( n9636 , n9635 , n6474 );
or ( n9637 , n9633 , n9636 );
not ( n9638 , n6474 );
buf ( n9639 , n5317 );
and ( n9640 , n9638 , n9639 );
buf ( n9641 , n5318 );
xor ( n9642 , n9641 , n9639 );
and ( n9643 , n9642 , n6474 );
or ( n9644 , n9640 , n9643 );
xor ( n9645 , n9637 , n9644 );
buf ( n9646 , n5319 );
xor ( n9647 , n9645 , n9646 );
buf ( n9648 , n5320 );
xor ( n9649 , n9647 , n9648 );
buf ( n9650 , n5321 );
xor ( n9651 , n9649 , n9650 );
xor ( n9652 , n9630 , n9651 );
not ( n9653 , n6474 );
buf ( n9654 , n5322 );
and ( n9655 , n9653 , n9654 );
buf ( n9656 , n5323 );
xor ( n9657 , n9656 , n9654 );
and ( n9658 , n9657 , n6474 );
or ( n9659 , n9655 , n9658 );
not ( n9660 , n6474 );
buf ( n9661 , n5324 );
and ( n9662 , n9660 , n9661 );
buf ( n9663 , n5325 );
xor ( n9664 , n9663 , n9661 );
and ( n9665 , n9664 , n6474 );
or ( n9666 , n9662 , n9665 );
xor ( n9667 , n9659 , n9666 );
buf ( n9668 , n5326 );
xor ( n9669 , n9667 , n9668 );
buf ( n9670 , n5327 );
xor ( n9671 , n9669 , n9670 );
buf ( n9672 , n5328 );
xor ( n9673 , n9671 , n9672 );
xor ( n9674 , n9652 , n9673 );
not ( n9675 , n9674 );
buf ( n9676 , n5329 );
xor ( n9677 , n9676 , n8696 );
xor ( n9678 , n9677 , n8710 );
and ( n9679 , n9675 , n9678 );
xor ( n9680 , n9629 , n9679 );
xor ( n9681 , n9585 , n9680 );
not ( n9682 , n6474 );
buf ( n9683 , n5330 );
and ( n9684 , n9682 , n9683 );
buf ( n9685 , n5331 );
xor ( n9686 , n9685 , n9683 );
and ( n9687 , n9686 , n6474 );
or ( n9688 , n9684 , n9687 );
xor ( n9689 , n9688 , n9079 );
xor ( n9690 , n9689 , n9094 );
buf ( n9691 , n5332 );
xor ( n9692 , n9691 , n7208 );
xor ( n9693 , n9692 , n7230 );
not ( n9694 , n9693 );
buf ( n9695 , n5333 );
not ( n9696 , n6474 );
buf ( n9697 , n5334 );
and ( n9698 , n9696 , n9697 );
buf ( n9699 , n5335 );
xor ( n9700 , n9699 , n9697 );
and ( n9701 , n9700 , n6474 );
or ( n9702 , n9698 , n9701 );
buf ( n9703 , n5336 );
xor ( n9704 , n9702 , n9703 );
buf ( n9705 , n5337 );
xor ( n9706 , n9704 , n9705 );
buf ( n9707 , n5338 );
xor ( n9708 , n9706 , n9707 );
buf ( n9709 , n5339 );
xor ( n9710 , n9708 , n9709 );
xor ( n9711 , n9695 , n9710 );
not ( n9712 , n6474 );
buf ( n9713 , n5340 );
and ( n9714 , n9712 , n9713 );
buf ( n9715 , n5341 );
xor ( n9716 , n9715 , n9713 );
and ( n9717 , n9716 , n6474 );
or ( n9718 , n9714 , n9717 );
not ( n9719 , n6474 );
buf ( n9720 , n5342 );
and ( n9721 , n9719 , n9720 );
buf ( n9722 , n5343 );
xor ( n9723 , n9722 , n9720 );
and ( n9724 , n9723 , n6474 );
or ( n9725 , n9721 , n9724 );
xor ( n9726 , n9718 , n9725 );
buf ( n9727 , n5344 );
xor ( n9728 , n9726 , n9727 );
buf ( n9729 , n5345 );
xor ( n9730 , n9728 , n9729 );
buf ( n9731 , n5346 );
xor ( n9732 , n9730 , n9731 );
xor ( n9733 , n9711 , n9732 );
and ( n9734 , n9694 , n9733 );
xor ( n9735 , n9690 , n9734 );
xor ( n9736 , n9681 , n9735 );
xor ( n9737 , n9311 , n9736 );
and ( n9738 , n8770 , n9737 );
xor ( n9739 , n7747 , n9738 );
and ( n9740 , n9739 , n6475 );
or ( n9741 , n6478 , n9740 );
and ( n9742 , n6470 , n9741 );
buf ( n9743 , n9742 );
buf ( n9744 , n9743 );
not ( n9745 , n6469 );
not ( n9746 , n6475 );
buf ( n9747 , n5347 );
and ( n9748 , n9746 , n9747 );
buf ( n9749 , n5348 );
not ( n9750 , n6474 );
buf ( n9751 , n5349 );
and ( n9752 , n9750 , n9751 );
buf ( n9753 , n5350 );
xor ( n9754 , n9753 , n9751 );
and ( n9755 , n9754 , n6474 );
or ( n9756 , n9752 , n9755 );
not ( n9757 , n6474 );
buf ( n9758 , n5351 );
and ( n9759 , n9757 , n9758 );
buf ( n9760 , n5352 );
xor ( n9761 , n9760 , n9758 );
and ( n9762 , n9761 , n6474 );
or ( n9763 , n9759 , n9762 );
xor ( n9764 , n9756 , n9763 );
buf ( n9765 , n5353 );
xor ( n9766 , n9764 , n9765 );
buf ( n9767 , n5354 );
xor ( n9768 , n9766 , n9767 );
buf ( n9769 , n5355 );
xor ( n9770 , n9768 , n9769 );
xor ( n9771 , n9749 , n9770 );
xor ( n9772 , n9771 , n7112 );
buf ( n9773 , n5356 );
not ( n9774 , n6474 );
buf ( n9775 , n5357 );
and ( n9776 , n9774 , n9775 );
buf ( n9777 , n5358 );
xor ( n9778 , n9777 , n9775 );
and ( n9779 , n9778 , n6474 );
or ( n9780 , n9776 , n9779 );
not ( n9781 , n6474 );
buf ( n9782 , n5359 );
and ( n9783 , n9781 , n9782 );
buf ( n9784 , n5360 );
xor ( n9785 , n9784 , n9782 );
and ( n9786 , n9785 , n6474 );
or ( n9787 , n9783 , n9786 );
xor ( n9788 , n9780 , n9787 );
buf ( n9789 , n5361 );
xor ( n9790 , n9788 , n9789 );
buf ( n9791 , n5362 );
xor ( n9792 , n9790 , n9791 );
buf ( n9793 , n5363 );
xor ( n9794 , n9792 , n9793 );
xor ( n9795 , n9773 , n9794 );
not ( n9796 , n6474 );
buf ( n9797 , n5364 );
and ( n9798 , n9796 , n9797 );
buf ( n9799 , n5365 );
xor ( n9800 , n9799 , n9797 );
and ( n9801 , n9800 , n6474 );
or ( n9802 , n9798 , n9801 );
not ( n9803 , n6474 );
buf ( n9804 , n5366 );
and ( n9805 , n9803 , n9804 );
buf ( n9806 , n5367 );
xor ( n9807 , n9806 , n9804 );
and ( n9808 , n9807 , n6474 );
or ( n9809 , n9805 , n9808 );
xor ( n9810 , n9802 , n9809 );
buf ( n9811 , n5368 );
xor ( n9812 , n9810 , n9811 );
buf ( n9813 , n5369 );
xor ( n9814 , n9812 , n9813 );
buf ( n9815 , n5370 );
xor ( n9816 , n9814 , n9815 );
xor ( n9817 , n9795 , n9816 );
not ( n9818 , n9817 );
xor ( n9819 , n8763 , n8269 );
xor ( n9820 , n9819 , n8291 );
and ( n9821 , n9818 , n9820 );
xor ( n9822 , n9772 , n9821 );
not ( n9823 , n6474 );
buf ( n9824 , n5371 );
and ( n9825 , n9823 , n9824 );
buf ( n9826 , n5372 );
xor ( n9827 , n9826 , n9824 );
and ( n9828 , n9827 , n6474 );
or ( n9829 , n9825 , n9828 );
not ( n9830 , n6474 );
buf ( n9831 , n5373 );
and ( n9832 , n9830 , n9831 );
buf ( n9833 , n5374 );
xor ( n9834 , n9833 , n9831 );
and ( n9835 , n9834 , n6474 );
or ( n9836 , n9832 , n9835 );
not ( n9837 , n6474 );
buf ( n9838 , n5375 );
and ( n9839 , n9837 , n9838 );
buf ( n9840 , n5376 );
xor ( n9841 , n9840 , n9838 );
and ( n9842 , n9841 , n6474 );
or ( n9843 , n9839 , n9842 );
xor ( n9844 , n9836 , n9843 );
buf ( n9845 , n5377 );
xor ( n9846 , n9844 , n9845 );
buf ( n9847 , n5378 );
xor ( n9848 , n9846 , n9847 );
buf ( n9849 , n5379 );
xor ( n9850 , n9848 , n9849 );
xor ( n9851 , n9829 , n9850 );
not ( n9852 , n6474 );
buf ( n9853 , n5380 );
and ( n9854 , n9852 , n9853 );
buf ( n9855 , n5381 );
xor ( n9856 , n9855 , n9853 );
and ( n9857 , n9856 , n6474 );
or ( n9858 , n9854 , n9857 );
not ( n9859 , n6474 );
buf ( n9860 , n5382 );
and ( n9861 , n9859 , n9860 );
buf ( n9862 , n5383 );
xor ( n9863 , n9862 , n9860 );
and ( n9864 , n9863 , n6474 );
or ( n9865 , n9861 , n9864 );
xor ( n9866 , n9858 , n9865 );
buf ( n9867 , n5384 );
xor ( n9868 , n9866 , n9867 );
buf ( n9869 , n5385 );
xor ( n9870 , n9868 , n9869 );
buf ( n9871 , n5386 );
xor ( n9872 , n9870 , n9871 );
xor ( n9873 , n9851 , n9872 );
xor ( n9874 , n8154 , n8414 );
xor ( n9875 , n9874 , n9026 );
not ( n9876 , n9875 );
buf ( n9877 , n5387 );
not ( n9878 , n6474 );
and ( n9879 , n9878 , n9747 );
buf ( n9880 , n5388 );
xor ( n9881 , n9880 , n9747 );
and ( n9882 , n9881 , n6474 );
or ( n9883 , n9879 , n9882 );
not ( n9884 , n6474 );
buf ( n9885 , n5389 );
and ( n9886 , n9884 , n9885 );
buf ( n9887 , n5390 );
xor ( n9888 , n9887 , n9885 );
and ( n9889 , n9888 , n6474 );
or ( n9890 , n9886 , n9889 );
xor ( n9891 , n9883 , n9890 );
xor ( n9892 , n9891 , n8426 );
buf ( n9893 , n5391 );
xor ( n9894 , n9892 , n9893 );
xor ( n9895 , n9894 , n8977 );
xor ( n9896 , n9877 , n9895 );
xor ( n9897 , n9896 , n7612 );
and ( n9898 , n9876 , n9897 );
xor ( n9899 , n9873 , n9898 );
buf ( n9900 , n5392 );
not ( n9901 , n6474 );
buf ( n9902 , n5393 );
and ( n9903 , n9901 , n9902 );
buf ( n9904 , n5394 );
xor ( n9905 , n9904 , n9902 );
and ( n9906 , n9905 , n6474 );
or ( n9907 , n9903 , n9906 );
not ( n9908 , n6474 );
buf ( n9909 , n5395 );
and ( n9910 , n9908 , n9909 );
buf ( n9911 , n5396 );
xor ( n9912 , n9911 , n9909 );
and ( n9913 , n9912 , n6474 );
or ( n9914 , n9910 , n9913 );
xor ( n9915 , n9907 , n9914 );
buf ( n9916 , n5397 );
xor ( n9917 , n9915 , n9916 );
buf ( n9918 , n5398 );
xor ( n9919 , n9917 , n9918 );
buf ( n9920 , n5399 );
xor ( n9921 , n9919 , n9920 );
xor ( n9922 , n9900 , n9921 );
not ( n9923 , n6474 );
buf ( n9924 , n5400 );
and ( n9925 , n9923 , n9924 );
buf ( n9926 , n5401 );
xor ( n9927 , n9926 , n9924 );
and ( n9928 , n9927 , n6474 );
or ( n9929 , n9925 , n9928 );
not ( n9930 , n6474 );
and ( n9931 , n9930 , n6477 );
buf ( n9932 , n5402 );
xor ( n9933 , n9932 , n6477 );
and ( n9934 , n9933 , n6474 );
or ( n9935 , n9931 , n9934 );
xor ( n9936 , n9929 , n9935 );
buf ( n9937 , n5403 );
xor ( n9938 , n9936 , n9937 );
buf ( n9939 , n5404 );
xor ( n9940 , n9938 , n9939 );
buf ( n9941 , n5405 );
xor ( n9942 , n9940 , n9941 );
xor ( n9943 , n9922 , n9942 );
buf ( n9944 , n5406 );
xor ( n9945 , n9944 , n6891 );
xor ( n9946 , n9945 , n6913 );
not ( n9947 , n9946 );
buf ( n9948 , n5407 );
xor ( n9949 , n9948 , n9047 );
xor ( n9950 , n9949 , n9338 );
and ( n9951 , n9947 , n9950 );
xor ( n9952 , n9943 , n9951 );
xor ( n9953 , n9899 , n9952 );
not ( n9954 , n6474 );
buf ( n9955 , n5408 );
and ( n9956 , n9954 , n9955 );
buf ( n9957 , n5409 );
xor ( n9958 , n9957 , n9955 );
and ( n9959 , n9958 , n6474 );
or ( n9960 , n9956 , n9959 );
not ( n9961 , n6474 );
buf ( n9962 , n5410 );
and ( n9963 , n9961 , n9962 );
buf ( n9964 , n5411 );
xor ( n9965 , n9964 , n9962 );
and ( n9966 , n9965 , n6474 );
or ( n9967 , n9963 , n9966 );
xor ( n9968 , n9960 , n9967 );
buf ( n9969 , n5412 );
xor ( n9970 , n9968 , n9969 );
xor ( n9971 , n9970 , n9442 );
buf ( n9972 , n5413 );
xor ( n9973 , n9971 , n9972 );
xor ( n9974 , n6493 , n9973 );
not ( n9975 , n6474 );
buf ( n9976 , n5414 );
and ( n9977 , n9975 , n9976 );
buf ( n9978 , n5415 );
xor ( n9979 , n9978 , n9976 );
and ( n9980 , n9979 , n6474 );
or ( n9981 , n9977 , n9980 );
not ( n9982 , n6474 );
buf ( n9983 , n5416 );
and ( n9984 , n9982 , n9983 );
buf ( n9985 , n5417 );
xor ( n9986 , n9985 , n9983 );
and ( n9987 , n9986 , n6474 );
or ( n9988 , n9984 , n9987 );
xor ( n9989 , n9981 , n9988 );
buf ( n9990 , n5418 );
xor ( n9991 , n9989 , n9990 );
buf ( n9992 , n5419 );
xor ( n9993 , n9991 , n9992 );
buf ( n9994 , n5420 );
xor ( n9995 , n9993 , n9994 );
xor ( n9996 , n9974 , n9995 );
not ( n9997 , n9772 );
and ( n9998 , n9997 , n9817 );
xor ( n9999 , n9996 , n9998 );
xor ( n10000 , n9953 , n9999 );
not ( n10001 , n6474 );
buf ( n10002 , n5421 );
and ( n10003 , n10001 , n10002 );
buf ( n10004 , n5422 );
xor ( n10005 , n10004 , n10002 );
and ( n10006 , n10005 , n6474 );
or ( n10007 , n10003 , n10006 );
not ( n10008 , n6474 );
buf ( n10009 , n5423 );
and ( n10010 , n10008 , n10009 );
buf ( n10011 , n5424 );
xor ( n10012 , n10011 , n10009 );
and ( n10013 , n10012 , n6474 );
or ( n10014 , n10010 , n10013 );
buf ( n10015 , n5425 );
xor ( n10016 , n10014 , n10015 );
buf ( n10017 , n5426 );
xor ( n10018 , n10016 , n10017 );
buf ( n10019 , n5427 );
xor ( n10020 , n10018 , n10019 );
buf ( n10021 , n5428 );
xor ( n10022 , n10020 , n10021 );
xor ( n10023 , n10007 , n10022 );
not ( n10024 , n6474 );
buf ( n10025 , n5429 );
and ( n10026 , n10024 , n10025 );
buf ( n10027 , n5430 );
xor ( n10028 , n10027 , n10025 );
and ( n10029 , n10028 , n6474 );
or ( n10030 , n10026 , n10029 );
not ( n10031 , n6474 );
buf ( n10032 , n5431 );
and ( n10033 , n10031 , n10032 );
buf ( n10034 , n5432 );
xor ( n10035 , n10034 , n10032 );
and ( n10036 , n10035 , n6474 );
or ( n10037 , n10033 , n10036 );
xor ( n10038 , n10030 , n10037 );
buf ( n10039 , n5433 );
xor ( n10040 , n10038 , n10039 );
buf ( n10041 , n5434 );
xor ( n10042 , n10040 , n10041 );
buf ( n10043 , n5435 );
xor ( n10044 , n10042 , n10043 );
xor ( n10045 , n10023 , n10044 );
buf ( n10046 , n5436 );
not ( n10047 , n6474 );
buf ( n10048 , n5437 );
and ( n10049 , n10047 , n10048 );
buf ( n10050 , n5438 );
xor ( n10051 , n10050 , n10048 );
and ( n10052 , n10051 , n6474 );
or ( n10053 , n10049 , n10052 );
not ( n10054 , n6474 );
buf ( n10055 , n5439 );
and ( n10056 , n10054 , n10055 );
buf ( n10057 , n5440 );
xor ( n10058 , n10057 , n10055 );
and ( n10059 , n10058 , n6474 );
or ( n10060 , n10056 , n10059 );
xor ( n10061 , n10053 , n10060 );
buf ( n10062 , n5441 );
xor ( n10063 , n10061 , n10062 );
buf ( n10064 , n5442 );
xor ( n10065 , n10063 , n10064 );
buf ( n10066 , n5443 );
xor ( n10067 , n10065 , n10066 );
xor ( n10068 , n10046 , n10067 );
not ( n10069 , n6474 );
buf ( n10070 , n5444 );
and ( n10071 , n10069 , n10070 );
buf ( n10072 , n5445 );
xor ( n10073 , n10072 , n10070 );
and ( n10074 , n10073 , n6474 );
or ( n10075 , n10071 , n10074 );
not ( n10076 , n6474 );
buf ( n10077 , n5446 );
and ( n10078 , n10076 , n10077 );
buf ( n10079 , n5447 );
xor ( n10080 , n10079 , n10077 );
and ( n10081 , n10080 , n6474 );
or ( n10082 , n10078 , n10081 );
xor ( n10083 , n10075 , n10082 );
buf ( n10084 , n5448 );
xor ( n10085 , n10083 , n10084 );
buf ( n10086 , n5449 );
xor ( n10087 , n10085 , n10086 );
buf ( n10088 , n5450 );
xor ( n10089 , n10087 , n10088 );
xor ( n10090 , n10068 , n10089 );
not ( n10091 , n10090 );
xor ( n10092 , n9287 , n8660 );
not ( n10093 , n6474 );
buf ( n10094 , n5451 );
and ( n10095 , n10093 , n10094 );
buf ( n10096 , n5452 );
xor ( n10097 , n10096 , n10094 );
and ( n10098 , n10097 , n6474 );
or ( n10099 , n10095 , n10098 );
xor ( n10100 , n10099 , n9688 );
buf ( n10101 , n5453 );
xor ( n10102 , n10100 , n10101 );
buf ( n10103 , n5454 );
xor ( n10104 , n10102 , n10103 );
xor ( n10105 , n10104 , n9058 );
xor ( n10106 , n10092 , n10105 );
and ( n10107 , n10091 , n10106 );
xor ( n10108 , n10045 , n10107 );
xor ( n10109 , n10000 , n10108 );
not ( n10110 , n6474 );
buf ( n10111 , n5455 );
and ( n10112 , n10110 , n10111 );
buf ( n10113 , n5456 );
xor ( n10114 , n10113 , n10111 );
and ( n10115 , n10114 , n6474 );
or ( n10116 , n10112 , n10115 );
not ( n10117 , n6474 );
buf ( n10118 , n5457 );
and ( n10119 , n10117 , n10118 );
buf ( n10120 , n5458 );
xor ( n10121 , n10120 , n10118 );
and ( n10122 , n10121 , n6474 );
or ( n10123 , n10119 , n10122 );
xor ( n10124 , n10116 , n10123 );
buf ( n10125 , n5459 );
xor ( n10126 , n10124 , n10125 );
buf ( n10127 , n5460 );
xor ( n10128 , n10126 , n10127 );
buf ( n10129 , n5461 );
xor ( n10130 , n10128 , n10129 );
xor ( n10131 , n7941 , n10130 );
not ( n10132 , n6474 );
buf ( n10133 , n5462 );
and ( n10134 , n10132 , n10133 );
buf ( n10135 , n5463 );
xor ( n10136 , n10135 , n10133 );
and ( n10137 , n10136 , n6474 );
or ( n10138 , n10134 , n10137 );
buf ( n10139 , n5464 );
xor ( n10140 , n10138 , n10139 );
buf ( n10141 , n5465 );
xor ( n10142 , n10140 , n10141 );
buf ( n10143 , n5466 );
xor ( n10144 , n10142 , n10143 );
buf ( n10145 , n5467 );
xor ( n10146 , n10144 , n10145 );
xor ( n10147 , n10131 , n10146 );
buf ( n10148 , n5468 );
xor ( n10149 , n10148 , n7793 );
not ( n10150 , n6474 );
buf ( n10151 , n5469 );
and ( n10152 , n10150 , n10151 );
buf ( n10153 , n5470 );
xor ( n10154 , n10153 , n10151 );
and ( n10155 , n10154 , n6474 );
or ( n10156 , n10152 , n10155 );
not ( n10157 , n6474 );
buf ( n10158 , n5471 );
and ( n10159 , n10157 , n10158 );
buf ( n10160 , n5472 );
xor ( n10161 , n10160 , n10158 );
and ( n10162 , n10161 , n6474 );
or ( n10163 , n10159 , n10162 );
xor ( n10164 , n10156 , n10163 );
buf ( n10165 , n5473 );
xor ( n10166 , n10164 , n10165 );
buf ( n10167 , n5474 );
xor ( n10168 , n10166 , n10167 );
buf ( n10169 , n5475 );
xor ( n10170 , n10168 , n10169 );
xor ( n10171 , n10149 , n10170 );
not ( n10172 , n10171 );
buf ( n10173 , n5476 );
xor ( n10174 , n10173 , n7994 );
xor ( n10175 , n10174 , n8016 );
and ( n10176 , n10172 , n10175 );
xor ( n10177 , n10147 , n10176 );
xor ( n10178 , n10109 , n10177 );
xor ( n10179 , n9822 , n10178 );
not ( n10180 , n6474 );
buf ( n10181 , n5477 );
and ( n10182 , n10180 , n10181 );
buf ( n10183 , n5478 );
xor ( n10184 , n10183 , n10181 );
and ( n10185 , n10184 , n6474 );
or ( n10186 , n10182 , n10185 );
xor ( n10187 , n9225 , n10186 );
buf ( n10188 , n5479 );
xor ( n10189 , n10187 , n10188 );
buf ( n10190 , n5480 );
xor ( n10191 , n10189 , n10190 );
buf ( n10192 , n5481 );
xor ( n10193 , n10191 , n10192 );
xor ( n10194 , n8466 , n10193 );
not ( n10195 , n6474 );
buf ( n10196 , n5482 );
and ( n10197 , n10195 , n10196 );
buf ( n10198 , n5483 );
xor ( n10199 , n10198 , n10196 );
and ( n10200 , n10199 , n6474 );
or ( n10201 , n10197 , n10200 );
buf ( n10202 , n5484 );
xor ( n10203 , n10201 , n10202 );
buf ( n10204 , n5485 );
xor ( n10205 , n10203 , n10204 );
buf ( n10206 , n5486 );
xor ( n10207 , n10205 , n10206 );
buf ( n10208 , n5487 );
xor ( n10209 , n10207 , n10208 );
xor ( n10210 , n10194 , n10209 );
not ( n10211 , n6474 );
buf ( n10212 , n5488 );
and ( n10213 , n10211 , n10212 );
buf ( n10214 , n5489 );
xor ( n10215 , n10214 , n10212 );
and ( n10216 , n10215 , n6474 );
or ( n10217 , n10213 , n10216 );
xor ( n10218 , n10217 , n9269 );
buf ( n10219 , n5490 );
xor ( n10220 , n10218 , n10219 );
buf ( n10221 , n5491 );
xor ( n10222 , n10220 , n10221 );
buf ( n10223 , n5492 );
xor ( n10224 , n10222 , n10223 );
xor ( n10225 , n7375 , n10224 );
not ( n10226 , n6474 );
buf ( n10227 , n5493 );
and ( n10228 , n10226 , n10227 );
buf ( n10229 , n5494 );
xor ( n10230 , n10229 , n10227 );
and ( n10231 , n10230 , n6474 );
or ( n10232 , n10228 , n10231 );
not ( n10233 , n6474 );
buf ( n10234 , n5495 );
and ( n10235 , n10233 , n10234 );
buf ( n10236 , n5496 );
xor ( n10237 , n10236 , n10234 );
and ( n10238 , n10237 , n6474 );
or ( n10239 , n10235 , n10238 );
xor ( n10240 , n10232 , n10239 );
buf ( n10241 , n5497 );
xor ( n10242 , n10240 , n10241 );
buf ( n10243 , n5498 );
xor ( n10244 , n10242 , n10243 );
buf ( n10245 , n5499 );
xor ( n10246 , n10244 , n10245 );
xor ( n10247 , n10225 , n10246 );
not ( n10248 , n10247 );
not ( n10249 , n6474 );
buf ( n10250 , n5500 );
and ( n10251 , n10249 , n10250 );
buf ( n10252 , n5501 );
xor ( n10253 , n10252 , n10250 );
and ( n10254 , n10253 , n6474 );
or ( n10255 , n10251 , n10254 );
buf ( n10256 , n5502 );
xor ( n10257 , n10255 , n10256 );
buf ( n10258 , n5503 );
xor ( n10259 , n10257 , n10258 );
buf ( n10260 , n5504 );
xor ( n10261 , n10259 , n10260 );
buf ( n10262 , n5505 );
xor ( n10263 , n10261 , n10262 );
xor ( n10264 , n7216 , n10263 );
not ( n10265 , n6474 );
buf ( n10266 , n5506 );
and ( n10267 , n10265 , n10266 );
buf ( n10268 , n5507 );
xor ( n10269 , n10268 , n10266 );
and ( n10270 , n10269 , n6474 );
or ( n10271 , n10267 , n10270 );
not ( n10272 , n6474 );
buf ( n10273 , n5508 );
and ( n10274 , n10272 , n10273 );
buf ( n10275 , n5509 );
xor ( n10276 , n10275 , n10273 );
and ( n10277 , n10276 , n6474 );
or ( n10278 , n10274 , n10277 );
xor ( n10279 , n10271 , n10278 );
buf ( n10280 , n5510 );
xor ( n10281 , n10279 , n10280 );
buf ( n10282 , n5511 );
xor ( n10283 , n10281 , n10282 );
buf ( n10284 , n5512 );
xor ( n10285 , n10283 , n10284 );
xor ( n10286 , n10264 , n10285 );
and ( n10287 , n10248 , n10286 );
xor ( n10288 , n10210 , n10287 );
xor ( n10289 , n6760 , n9400 );
not ( n10290 , n6474 );
buf ( n10291 , n5513 );
and ( n10292 , n10290 , n10291 );
buf ( n10293 , n5514 );
xor ( n10294 , n10293 , n10291 );
and ( n10295 , n10294 , n6474 );
or ( n10296 , n10292 , n10295 );
not ( n10297 , n6474 );
buf ( n10298 , n5515 );
and ( n10299 , n10297 , n10298 );
buf ( n10300 , n5516 );
xor ( n10301 , n10300 , n10298 );
and ( n10302 , n10301 , n6474 );
or ( n10303 , n10299 , n10302 );
xor ( n10304 , n10296 , n10303 );
buf ( n10305 , n5517 );
xor ( n10306 , n10304 , n10305 );
buf ( n10307 , n5518 );
xor ( n10308 , n10306 , n10307 );
xor ( n10309 , n10308 , n7288 );
xor ( n10310 , n10289 , n10309 );
xor ( n10311 , n7909 , n9628 );
xor ( n10312 , n10311 , n6538 );
not ( n10313 , n10312 );
not ( n10314 , n6474 );
buf ( n10315 , n5519 );
and ( n10316 , n10314 , n10315 );
buf ( n10317 , n5520 );
xor ( n10318 , n10317 , n10315 );
and ( n10319 , n10318 , n6474 );
or ( n10320 , n10316 , n10319 );
not ( n10321 , n6474 );
buf ( n10322 , n5521 );
and ( n10323 , n10321 , n10322 );
buf ( n10324 , n5522 );
xor ( n10325 , n10324 , n10322 );
and ( n10326 , n10325 , n6474 );
or ( n10327 , n10323 , n10326 );
xor ( n10328 , n10320 , n10327 );
buf ( n10329 , n5523 );
xor ( n10330 , n10328 , n10329 );
buf ( n10331 , n5524 );
xor ( n10332 , n10330 , n10331 );
buf ( n10333 , n5525 );
xor ( n10334 , n10332 , n10333 );
xor ( n10335 , n6639 , n10334 );
not ( n10336 , n6474 );
buf ( n10337 , n5526 );
and ( n10338 , n10336 , n10337 );
buf ( n10339 , n5527 );
xor ( n10340 , n10339 , n10337 );
and ( n10341 , n10340 , n6474 );
or ( n10342 , n10338 , n10341 );
buf ( n10343 , n5528 );
xor ( n10344 , n10342 , n10343 );
buf ( n10345 , n5529 );
xor ( n10346 , n10344 , n10345 );
buf ( n10347 , n5530 );
xor ( n10348 , n10346 , n10347 );
buf ( n10349 , n5531 );
xor ( n10350 , n10348 , n10349 );
xor ( n10351 , n10335 , n10350 );
and ( n10352 , n10313 , n10351 );
xor ( n10353 , n10310 , n10352 );
xor ( n10354 , n10288 , n10353 );
buf ( n10355 , n5532 );
not ( n10356 , n6474 );
buf ( n10357 , n5533 );
and ( n10358 , n10356 , n10357 );
buf ( n10359 , n5534 );
xor ( n10360 , n10359 , n10357 );
and ( n10361 , n10360 , n6474 );
or ( n10362 , n10358 , n10361 );
not ( n10363 , n6474 );
buf ( n10364 , n5535 );
and ( n10365 , n10363 , n10364 );
buf ( n10366 , n5536 );
xor ( n10367 , n10366 , n10364 );
and ( n10368 , n10367 , n6474 );
or ( n10369 , n10365 , n10368 );
xor ( n10370 , n10362 , n10369 );
buf ( n10371 , n5537 );
xor ( n10372 , n10370 , n10371 );
buf ( n10373 , n5538 );
xor ( n10374 , n10372 , n10373 );
buf ( n10375 , n5539 );
xor ( n10376 , n10374 , n10375 );
xor ( n10377 , n10355 , n10376 );
xor ( n10378 , n10377 , n10067 );
buf ( n10379 , n5540 );
not ( n10380 , n6474 );
buf ( n10381 , n5541 );
and ( n10382 , n10380 , n10381 );
buf ( n10383 , n5542 );
xor ( n10384 , n10383 , n10381 );
and ( n10385 , n10384 , n6474 );
or ( n10386 , n10382 , n10385 );
buf ( n10387 , n5543 );
xor ( n10388 , n10386 , n10387 );
buf ( n10389 , n5544 );
xor ( n10390 , n10388 , n10389 );
buf ( n10391 , n5545 );
xor ( n10392 , n10390 , n10391 );
buf ( n10393 , n5546 );
xor ( n10394 , n10392 , n10393 );
xor ( n10395 , n10379 , n10394 );
not ( n10396 , n6474 );
buf ( n10397 , n5547 );
and ( n10398 , n10396 , n10397 );
buf ( n10399 , n5548 );
xor ( n10400 , n10399 , n10397 );
and ( n10401 , n10400 , n6474 );
or ( n10402 , n10398 , n10401 );
not ( n10403 , n6474 );
buf ( n10404 , n5549 );
and ( n10405 , n10403 , n10404 );
buf ( n10406 , n5550 );
xor ( n10407 , n10406 , n10404 );
and ( n10408 , n10407 , n6474 );
or ( n10409 , n10405 , n10408 );
xor ( n10410 , n10402 , n10409 );
buf ( n10411 , n5551 );
xor ( n10412 , n10410 , n10411 );
buf ( n10413 , n5552 );
xor ( n10414 , n10412 , n10413 );
buf ( n10415 , n5553 );
xor ( n10416 , n10414 , n10415 );
xor ( n10417 , n10395 , n10416 );
not ( n10418 , n10417 );
not ( n10419 , n6474 );
buf ( n10420 , n5554 );
and ( n10421 , n10419 , n10420 );
buf ( n10422 , n5555 );
xor ( n10423 , n10422 , n10420 );
and ( n10424 , n10423 , n6474 );
or ( n10425 , n10421 , n10424 );
not ( n10426 , n6474 );
buf ( n10427 , n5556 );
and ( n10428 , n10426 , n10427 );
buf ( n10429 , n5557 );
xor ( n10430 , n10429 , n10427 );
and ( n10431 , n10430 , n6474 );
or ( n10432 , n10428 , n10431 );
xor ( n10433 , n10425 , n10432 );
buf ( n10434 , n5558 );
xor ( n10435 , n10433 , n10434 );
xor ( n10436 , n10435 , n9695 );
buf ( n10437 , n5559 );
buf ( n10438 , n10437 );
xor ( n10439 , n10436 , n10438 );
xor ( n10440 , n10271 , n10439 );
xor ( n10441 , n10440 , n8574 );
and ( n10442 , n10418 , n10441 );
xor ( n10443 , n10378 , n10442 );
xor ( n10444 , n10354 , n10443 );
not ( n10445 , n6474 );
buf ( n10446 , n5560 );
and ( n10447 , n10445 , n10446 );
buf ( n10448 , n5561 );
xor ( n10449 , n10448 , n10446 );
and ( n10450 , n10449 , n6474 );
or ( n10451 , n10447 , n10450 );
not ( n10452 , n6474 );
buf ( n10453 , n5562 );
and ( n10454 , n10452 , n10453 );
buf ( n10455 , n5563 );
xor ( n10456 , n10455 , n10453 );
and ( n10457 , n10456 , n6474 );
or ( n10458 , n10454 , n10457 );
xor ( n10459 , n10451 , n10458 );
buf ( n10460 , n5564 );
xor ( n10461 , n10459 , n10460 );
buf ( n10462 , n5565 );
xor ( n10463 , n10461 , n10462 );
buf ( n10464 , n5566 );
xor ( n10465 , n10463 , n10464 );
xor ( n10466 , n9076 , n10465 );
xor ( n10467 , n10466 , n8743 );
not ( n10468 , n6474 );
buf ( n10469 , n5567 );
and ( n10470 , n10468 , n10469 );
buf ( n10471 , n5568 );
xor ( n10472 , n10471 , n10469 );
and ( n10473 , n10472 , n6474 );
or ( n10474 , n10470 , n10473 );
not ( n10475 , n6474 );
buf ( n10476 , n5569 );
and ( n10477 , n10475 , n10476 );
buf ( n10478 , n5570 );
xor ( n10479 , n10478 , n10476 );
and ( n10480 , n10479 , n6474 );
or ( n10481 , n10477 , n10480 );
xor ( n10482 , n10474 , n10481 );
buf ( n10483 , n5571 );
xor ( n10484 , n10482 , n10483 );
buf ( n10485 , n5572 );
xor ( n10486 , n10484 , n10485 );
buf ( n10487 , n5573 );
xor ( n10488 , n10486 , n10487 );
xor ( n10489 , n6849 , n10488 );
not ( n10490 , n6474 );
buf ( n10491 , n5574 );
and ( n10492 , n10490 , n10491 );
buf ( n10493 , n5575 );
xor ( n10494 , n10493 , n10491 );
and ( n10495 , n10494 , n6474 );
or ( n10496 , n10492 , n10495 );
buf ( n10497 , n5576 );
xor ( n10498 , n10496 , n10497 );
buf ( n10499 , n5577 );
xor ( n10500 , n10498 , n10499 );
buf ( n10501 , n5578 );
xor ( n10502 , n10500 , n10501 );
buf ( n10503 , n5579 );
xor ( n10504 , n10502 , n10503 );
xor ( n10505 , n10489 , n10504 );
not ( n10506 , n10505 );
not ( n10507 , n6474 );
buf ( n10508 , n5580 );
and ( n10509 , n10507 , n10508 );
buf ( n10510 , n5581 );
xor ( n10511 , n10510 , n10508 );
and ( n10512 , n10511 , n6474 );
or ( n10513 , n10509 , n10512 );
not ( n10514 , n6474 );
buf ( n10515 , n5582 );
and ( n10516 , n10514 , n10515 );
buf ( n10517 , n5583 );
xor ( n10518 , n10517 , n10515 );
and ( n10519 , n10518 , n6474 );
or ( n10520 , n10516 , n10519 );
xor ( n10521 , n10513 , n10520 );
buf ( n10522 , n5584 );
xor ( n10523 , n10521 , n10522 );
buf ( n10524 , n5585 );
xor ( n10525 , n10523 , n10524 );
buf ( n10526 , n5586 );
xor ( n10527 , n10525 , n10526 );
xor ( n10528 , n9409 , n10527 );
not ( n10529 , n6474 );
buf ( n10530 , n5587 );
and ( n10531 , n10529 , n10530 );
buf ( n10532 , n5588 );
xor ( n10533 , n10532 , n10530 );
and ( n10534 , n10533 , n6474 );
or ( n10535 , n10531 , n10534 );
not ( n10536 , n6474 );
buf ( n10537 , n5589 );
and ( n10538 , n10536 , n10537 );
buf ( n10539 , n5590 );
xor ( n10540 , n10539 , n10537 );
and ( n10541 , n10540 , n6474 );
or ( n10542 , n10538 , n10541 );
xor ( n10543 , n10535 , n10542 );
buf ( n10544 , n5591 );
xor ( n10545 , n10543 , n10544 );
buf ( n10546 , n5592 );
xor ( n10547 , n10545 , n10546 );
buf ( n10548 , n5593 );
xor ( n10549 , n10547 , n10548 );
xor ( n10550 , n10528 , n10549 );
and ( n10551 , n10506 , n10550 );
xor ( n10552 , n10467 , n10551 );
xor ( n10553 , n10444 , n10552 );
xor ( n10554 , n8134 , n7046 );
xor ( n10555 , n10554 , n8414 );
not ( n10556 , n6474 );
buf ( n10557 , n5594 );
and ( n10558 , n10556 , n10557 );
buf ( n10559 , n5595 );
xor ( n10560 , n10559 , n10557 );
and ( n10561 , n10560 , n6474 );
or ( n10562 , n10558 , n10561 );
not ( n10563 , n6474 );
buf ( n10564 , n5596 );
and ( n10565 , n10563 , n10564 );
buf ( n10566 , n5597 );
xor ( n10567 , n10566 , n10564 );
and ( n10568 , n10567 , n6474 );
or ( n10569 , n10565 , n10568 );
xor ( n10570 , n10562 , n10569 );
xor ( n10571 , n10570 , n9944 );
buf ( n10572 , n5598 );
xor ( n10573 , n10571 , n10572 );
xor ( n10574 , n10573 , n6875 );
xor ( n10575 , n9731 , n10574 );
not ( n10576 , n6474 );
buf ( n10577 , n5599 );
and ( n10578 , n10576 , n10577 );
buf ( n10579 , n5600 );
xor ( n10580 , n10579 , n10577 );
and ( n10581 , n10580 , n6474 );
or ( n10582 , n10578 , n10581 );
not ( n10583 , n6474 );
buf ( n10584 , n5601 );
and ( n10585 , n10583 , n10584 );
buf ( n10586 , n5602 );
xor ( n10587 , n10586 , n10584 );
and ( n10588 , n10587 , n6474 );
or ( n10589 , n10585 , n10588 );
xor ( n10590 , n10582 , n10589 );
xor ( n10591 , n10590 , n9314 );
buf ( n10592 , n5603 );
xor ( n10593 , n10591 , n10592 );
buf ( n10594 , n5604 );
xor ( n10595 , n10593 , n10594 );
xor ( n10596 , n10575 , n10595 );
not ( n10597 , n10596 );
not ( n10598 , n6474 );
buf ( n10599 , n5605 );
and ( n10600 , n10598 , n10599 );
buf ( n10601 , n5606 );
xor ( n10602 , n10601 , n10599 );
and ( n10603 , n10602 , n6474 );
or ( n10604 , n10600 , n10603 );
not ( n10605 , n6474 );
buf ( n10606 , n5607 );
and ( n10607 , n10605 , n10606 );
buf ( n10608 , n5608 );
xor ( n10609 , n10608 , n10606 );
and ( n10610 , n10609 , n6474 );
or ( n10611 , n10607 , n10610 );
not ( n10612 , n6474 );
buf ( n10613 , n5609 );
and ( n10614 , n10612 , n10613 );
buf ( n10615 , n5610 );
xor ( n10616 , n10615 , n10613 );
and ( n10617 , n10616 , n6474 );
or ( n10618 , n10614 , n10617 );
xor ( n10619 , n10611 , n10618 );
buf ( n10620 , n5611 );
xor ( n10621 , n10619 , n10620 );
buf ( n10622 , n5612 );
xor ( n10623 , n10621 , n10622 );
buf ( n10624 , n5613 );
xor ( n10625 , n10623 , n10624 );
xor ( n10626 , n10604 , n10625 );
xor ( n10627 , n10626 , n7208 );
and ( n10628 , n10597 , n10627 );
xor ( n10629 , n10555 , n10628 );
xor ( n10630 , n10553 , n10629 );
xor ( n10631 , n10179 , n10630 );
not ( n10632 , n6474 );
buf ( n10633 , n5614 );
and ( n10634 , n10632 , n10633 );
buf ( n10635 , n5615 );
xor ( n10636 , n10635 , n10633 );
and ( n10637 , n10636 , n6474 );
or ( n10638 , n10634 , n10637 );
not ( n10639 , n6474 );
buf ( n10640 , n5616 );
and ( n10641 , n10639 , n10640 );
buf ( n10642 , n5617 );
xor ( n10643 , n10642 , n10640 );
and ( n10644 , n10643 , n6474 );
or ( n10645 , n10641 , n10644 );
xor ( n10646 , n10638 , n10645 );
buf ( n10647 , n5618 );
xor ( n10648 , n10646 , n10647 );
buf ( n10649 , n5619 );
xor ( n10650 , n10648 , n10649 );
buf ( n10651 , n5620 );
xor ( n10652 , n10650 , n10651 );
xor ( n10653 , n10485 , n10652 );
not ( n10654 , n6474 );
buf ( n10655 , n5621 );
and ( n10656 , n10654 , n10655 );
buf ( n10657 , n5622 );
xor ( n10658 , n10657 , n10655 );
and ( n10659 , n10658 , n6474 );
or ( n10660 , n10656 , n10659 );
not ( n10661 , n6474 );
buf ( n10662 , n5623 );
and ( n10663 , n10661 , n10662 );
buf ( n10664 , n5624 );
xor ( n10665 , n10664 , n10662 );
and ( n10666 , n10665 , n6474 );
or ( n10667 , n10663 , n10666 );
xor ( n10668 , n10660 , n10667 );
buf ( n10669 , n5625 );
xor ( n10670 , n10668 , n10669 );
buf ( n10671 , n5626 );
xor ( n10672 , n10670 , n10671 );
buf ( n10673 , n5627 );
xor ( n10674 , n10672 , n10673 );
xor ( n10675 , n10653 , n10674 );
buf ( n10676 , n5628 );
not ( n10677 , n6474 );
buf ( n10678 , n5629 );
and ( n10679 , n10677 , n10678 );
buf ( n10680 , n5630 );
xor ( n10681 , n10680 , n10678 );
and ( n10682 , n10681 , n6474 );
or ( n10683 , n10679 , n10682 );
not ( n10684 , n6474 );
buf ( n10685 , n5631 );
and ( n10686 , n10684 , n10685 );
buf ( n10687 , n5632 );
xor ( n10688 , n10687 , n10685 );
and ( n10689 , n10688 , n6474 );
or ( n10690 , n10686 , n10689 );
xor ( n10691 , n10683 , n10690 );
buf ( n10692 , n5633 );
xor ( n10693 , n10691 , n10692 );
buf ( n10694 , n5634 );
xor ( n10695 , n10693 , n10694 );
buf ( n10696 , n5635 );
xor ( n10697 , n10695 , n10696 );
xor ( n10698 , n10676 , n10697 );
not ( n10699 , n6474 );
buf ( n10700 , n5636 );
and ( n10701 , n10699 , n10700 );
buf ( n10702 , n5637 );
xor ( n10703 , n10702 , n10700 );
and ( n10704 , n10703 , n6474 );
or ( n10705 , n10701 , n10704 );
buf ( n10706 , n5638 );
xor ( n10707 , n10705 , n10706 );
buf ( n10708 , n5639 );
xor ( n10709 , n10707 , n10708 );
buf ( n10710 , n5640 );
xor ( n10711 , n10709 , n10710 );
buf ( n10712 , n5641 );
xor ( n10713 , n10711 , n10712 );
xor ( n10714 , n10698 , n10713 );
not ( n10715 , n10714 );
and ( n10716 , n10715 , n8623 );
xor ( n10717 , n10675 , n10716 );
not ( n10718 , n6474 );
buf ( n10719 , n5642 );
and ( n10720 , n10718 , n10719 );
buf ( n10721 , n5643 );
xor ( n10722 , n10721 , n10719 );
and ( n10723 , n10722 , n6474 );
or ( n10724 , n10720 , n10723 );
xor ( n10725 , n10604 , n10724 );
buf ( n10726 , n5644 );
xor ( n10727 , n10725 , n10726 );
buf ( n10728 , n5645 );
xor ( n10729 , n10727 , n10728 );
buf ( n10730 , n5646 );
xor ( n10731 , n10729 , n10730 );
xor ( n10732 , n6535 , n10731 );
not ( n10733 , n6474 );
buf ( n10734 , n5647 );
and ( n10735 , n10733 , n10734 );
buf ( n10736 , n5648 );
xor ( n10737 , n10736 , n10734 );
and ( n10738 , n10737 , n6474 );
or ( n10739 , n10735 , n10738 );
buf ( n10740 , n5649 );
xor ( n10741 , n10739 , n10740 );
xor ( n10742 , n10741 , n9691 );
buf ( n10743 , n5650 );
xor ( n10744 , n10742 , n10743 );
xor ( n10745 , n10744 , n7187 );
xor ( n10746 , n10732 , n10745 );
not ( n10747 , n10746 );
not ( n10748 , n6474 );
buf ( n10749 , n5651 );
and ( n10750 , n10748 , n10749 );
buf ( n10751 , n5652 );
xor ( n10752 , n10751 , n10749 );
and ( n10753 , n10752 , n6474 );
or ( n10754 , n10750 , n10753 );
not ( n10755 , n6474 );
buf ( n10756 , n5653 );
and ( n10757 , n10755 , n10756 );
buf ( n10758 , n5654 );
xor ( n10759 , n10758 , n10756 );
and ( n10760 , n10759 , n6474 );
or ( n10761 , n10757 , n10760 );
xor ( n10762 , n10754 , n10761 );
buf ( n10763 , n5655 );
xor ( n10764 , n10762 , n10763 );
buf ( n10765 , n5656 );
xor ( n10766 , n10764 , n10765 );
buf ( n10767 , n5657 );
xor ( n10768 , n10766 , n10767 );
xor ( n10769 , n10145 , n10768 );
not ( n10770 , n6474 );
buf ( n10771 , n5658 );
and ( n10772 , n10770 , n10771 );
buf ( n10773 , n5659 );
xor ( n10774 , n10773 , n10771 );
and ( n10775 , n10774 , n6474 );
or ( n10776 , n10772 , n10775 );
not ( n10777 , n6474 );
buf ( n10778 , n5660 );
and ( n10779 , n10777 , n10778 );
buf ( n10780 , n5661 );
xor ( n10781 , n10780 , n10778 );
and ( n10782 , n10781 , n6474 );
or ( n10783 , n10779 , n10782 );
xor ( n10784 , n10776 , n10783 );
buf ( n10785 , n5662 );
xor ( n10786 , n10784 , n10785 );
buf ( n10787 , n5663 );
xor ( n10788 , n10786 , n10787 );
buf ( n10789 , n5664 );
xor ( n10790 , n10788 , n10789 );
xor ( n10791 , n10769 , n10790 );
and ( n10792 , n10747 , n10791 );
xor ( n10793 , n8470 , n10792 );
not ( n10794 , n6474 );
buf ( n10795 , n5665 );
and ( n10796 , n10794 , n10795 );
buf ( n10797 , n5666 );
xor ( n10798 , n10797 , n10795 );
and ( n10799 , n10798 , n6474 );
or ( n10800 , n10796 , n10799 );
not ( n10801 , n6474 );
buf ( n10802 , n5667 );
and ( n10803 , n10801 , n10802 );
buf ( n10804 , n5668 );
xor ( n10805 , n10804 , n10802 );
and ( n10806 , n10805 , n6474 );
or ( n10807 , n10803 , n10806 );
xor ( n10808 , n10800 , n10807 );
buf ( n10809 , n5669 );
xor ( n10810 , n10808 , n10809 );
buf ( n10811 , n5670 );
xor ( n10812 , n10810 , n10811 );
buf ( n10813 , n5671 );
xor ( n10814 , n10812 , n10813 );
xor ( n10815 , n7631 , n10814 );
not ( n10816 , n6474 );
buf ( n10817 , n5672 );
and ( n10818 , n10816 , n10817 );
buf ( n10819 , n5673 );
xor ( n10820 , n10819 , n10817 );
and ( n10821 , n10820 , n6474 );
or ( n10822 , n10818 , n10821 );
not ( n10823 , n6474 );
buf ( n10824 , n5674 );
and ( n10825 , n10823 , n10824 );
buf ( n10826 , n5675 );
xor ( n10827 , n10826 , n10824 );
and ( n10828 , n10827 , n6474 );
or ( n10829 , n10825 , n10828 );
xor ( n10830 , n10822 , n10829 );
buf ( n10831 , n5676 );
xor ( n10832 , n10830 , n10831 );
buf ( n10833 , n5677 );
xor ( n10834 , n10832 , n10833 );
buf ( n10835 , n5678 );
xor ( n10836 , n10834 , n10835 );
xor ( n10837 , n10815 , n10836 );
not ( n10838 , n10837 );
buf ( n10839 , n5679 );
xor ( n10840 , n10839 , n8366 );
xor ( n10841 , n10840 , n8388 );
and ( n10842 , n10838 , n10841 );
xor ( n10843 , n8537 , n10842 );
xor ( n10844 , n10793 , n10843 );
not ( n10845 , n6474 );
buf ( n10846 , n5680 );
and ( n10847 , n10845 , n10846 );
buf ( n10848 , n5681 );
xor ( n10849 , n10848 , n10846 );
and ( n10850 , n10849 , n6474 );
or ( n10851 , n10847 , n10850 );
not ( n10852 , n6474 );
buf ( n10853 , n5682 );
and ( n10854 , n10852 , n10853 );
buf ( n10855 , n5683 );
xor ( n10856 , n10855 , n10853 );
and ( n10857 , n10856 , n6474 );
or ( n10858 , n10854 , n10857 );
xor ( n10859 , n10851 , n10858 );
xor ( n10860 , n10859 , n9513 );
buf ( n10861 , n5684 );
xor ( n10862 , n10860 , n10861 );
buf ( n10863 , n5685 );
xor ( n10864 , n10862 , n10863 );
xor ( n10865 , n7250 , n10864 );
xor ( n10866 , n10865 , n7159 );
not ( n10867 , n10866 );
buf ( n10868 , n5686 );
xor ( n10869 , n10868 , n9148 );
xor ( n10870 , n10869 , n9170 );
and ( n10871 , n10867 , n10870 );
xor ( n10872 , n8576 , n10871 );
xor ( n10873 , n10844 , n10872 );
not ( n10874 , n10675 );
and ( n10875 , n10874 , n10714 );
xor ( n10876 , n8665 , n10875 );
xor ( n10877 , n10873 , n10876 );
buf ( n10878 , n5687 );
xor ( n10879 , n10878 , n10394 );
xor ( n10880 , n10879 , n10416 );
not ( n10881 , n10880 );
buf ( n10882 , n5688 );
xor ( n10883 , n10882 , n9850 );
xor ( n10884 , n10883 , n9872 );
and ( n10885 , n10881 , n10884 );
xor ( n10886 , n8765 , n10885 );
xor ( n10887 , n10877 , n10886 );
xor ( n10888 , n10717 , n10887 );
buf ( n10889 , n5689 );
xor ( n10890 , n10889 , n6850 );
xor ( n10891 , n10890 , n6872 );
xor ( n10892 , n8300 , n7537 );
not ( n10893 , n6474 );
buf ( n10894 , n5690 );
and ( n10895 , n10893 , n10894 );
buf ( n10896 , n5691 );
xor ( n10897 , n10896 , n10894 );
and ( n10898 , n10897 , n6474 );
or ( n10899 , n10895 , n10898 );
xor ( n10900 , n10899 , n9829 );
buf ( n10901 , n5692 );
xor ( n10902 , n10900 , n10901 );
buf ( n10903 , n5693 );
xor ( n10904 , n10902 , n10903 );
xor ( n10905 , n10904 , n10882 );
xor ( n10906 , n10892 , n10905 );
not ( n10907 , n10906 );
xor ( n10908 , n7627 , n10814 );
xor ( n10909 , n10908 , n10836 );
and ( n10910 , n10907 , n10909 );
xor ( n10911 , n10891 , n10910 );
buf ( n10912 , n5694 );
xor ( n10913 , n10912 , n8696 );
xor ( n10914 , n10913 , n8710 );
xor ( n10915 , n9981 , n9464 );
not ( n10916 , n6474 );
buf ( n10917 , n5695 );
and ( n10918 , n10916 , n10917 );
buf ( n10919 , n5696 );
xor ( n10920 , n10919 , n10917 );
and ( n10921 , n10920 , n6474 );
or ( n10922 , n10918 , n10921 );
buf ( n10923 , n5697 );
xor ( n10924 , n10922 , n10923 );
buf ( n10925 , n5698 );
xor ( n10926 , n10924 , n10925 );
xor ( n10927 , n10926 , n9773 );
buf ( n10928 , n5699 );
xor ( n10929 , n10927 , n10928 );
xor ( n10930 , n10915 , n10929 );
not ( n10931 , n10930 );
xor ( n10932 , n7919 , n6538 );
xor ( n10933 , n10932 , n6560 );
and ( n10934 , n10931 , n10933 );
xor ( n10935 , n10914 , n10934 );
xor ( n10936 , n10911 , n10935 );
buf ( n10937 , n5700 );
xor ( n10938 , n10937 , n9606 );
xor ( n10939 , n10938 , n9628 );
xor ( n10940 , n10899 , n9850 );
xor ( n10941 , n10940 , n9872 );
not ( n10942 , n10941 );
not ( n10943 , n6474 );
buf ( n10944 , n5701 );
and ( n10945 , n10943 , n10944 );
buf ( n10946 , n5702 );
xor ( n10947 , n10946 , n10944 );
and ( n10948 , n10947 , n6474 );
or ( n10949 , n10945 , n10948 );
not ( n10950 , n6474 );
buf ( n10951 , n5703 );
and ( n10952 , n10950 , n10951 );
buf ( n10953 , n5704 );
xor ( n10954 , n10953 , n10951 );
and ( n10955 , n10954 , n6474 );
or ( n10956 , n10952 , n10955 );
xor ( n10957 , n10949 , n10956 );
buf ( n10958 , n5705 );
xor ( n10959 , n10957 , n10958 );
buf ( n10960 , n5706 );
xor ( n10961 , n10959 , n10960 );
buf ( n10962 , n5707 );
xor ( n10963 , n10961 , n10962 );
xor ( n10964 , n8858 , n10963 );
xor ( n10965 , n10964 , n10864 );
and ( n10966 , n10942 , n10965 );
xor ( n10967 , n10939 , n10966 );
xor ( n10968 , n10936 , n10967 );
buf ( n10969 , n5708 );
not ( n10970 , n6474 );
buf ( n10971 , n5709 );
and ( n10972 , n10970 , n10971 );
buf ( n10973 , n5710 );
xor ( n10974 , n10973 , n10971 );
and ( n10975 , n10974 , n6474 );
or ( n10976 , n10972 , n10975 );
not ( n10977 , n6474 );
buf ( n10978 , n5711 );
and ( n10979 , n10977 , n10978 );
buf ( n10980 , n5712 );
xor ( n10981 , n10980 , n10978 );
and ( n10982 , n10981 , n6474 );
or ( n10983 , n10979 , n10982 );
xor ( n10984 , n10976 , n10983 );
buf ( n10985 , n5713 );
xor ( n10986 , n10984 , n10985 );
buf ( n10987 , n5714 );
xor ( n10988 , n10986 , n10987 );
buf ( n10989 , n5715 );
xor ( n10990 , n10988 , n10989 );
xor ( n10991 , n10969 , n10990 );
xor ( n10992 , n10991 , n10022 );
xor ( n10993 , n7830 , n7399 );
xor ( n10994 , n10993 , n7421 );
not ( n10995 , n10994 );
not ( n10996 , n6474 );
buf ( n10997 , n5716 );
and ( n10998 , n10996 , n10997 );
buf ( n10999 , n5717 );
xor ( n11000 , n10999 , n10997 );
and ( n11001 , n11000 , n6474 );
or ( n11002 , n10998 , n11001 );
xor ( n11003 , n11002 , n7376 );
xor ( n11004 , n11003 , n10465 );
and ( n11005 , n10995 , n11004 );
xor ( n11006 , n10992 , n11005 );
xor ( n11007 , n10968 , n11006 );
buf ( n11008 , n5718 );
xor ( n11009 , n11008 , n9047 );
xor ( n11010 , n11009 , n9338 );
not ( n11011 , n6474 );
buf ( n11012 , n5719 );
and ( n11013 , n11011 , n11012 );
buf ( n11014 , n5720 );
xor ( n11015 , n11014 , n11012 );
and ( n11016 , n11015 , n6474 );
or ( n11017 , n11013 , n11016 );
not ( n11018 , n6474 );
buf ( n11019 , n5721 );
and ( n11020 , n11018 , n11019 );
buf ( n11021 , n5722 );
xor ( n11022 , n11021 , n11019 );
and ( n11023 , n11022 , n6474 );
or ( n11024 , n11020 , n11023 );
xor ( n11025 , n11017 , n11024 );
buf ( n11026 , n5723 );
xor ( n11027 , n11025 , n11026 );
buf ( n11028 , n5724 );
xor ( n11029 , n11027 , n11028 );
buf ( n11030 , n5725 );
xor ( n11031 , n11029 , n11030 );
xor ( n11032 , n7016 , n11031 );
not ( n11033 , n6474 );
buf ( n11034 , n5726 );
and ( n11035 , n11033 , n11034 );
buf ( n11036 , n5727 );
xor ( n11037 , n11036 , n11034 );
and ( n11038 , n11037 , n6474 );
or ( n11039 , n11035 , n11038 );
not ( n11040 , n6474 );
buf ( n11041 , n5728 );
and ( n11042 , n11040 , n11041 );
buf ( n11043 , n5729 );
xor ( n11044 , n11043 , n11041 );
and ( n11045 , n11044 , n6474 );
or ( n11046 , n11042 , n11045 );
xor ( n11047 , n11039 , n11046 );
buf ( n11048 , n5730 );
xor ( n11049 , n11047 , n11048 );
buf ( n11050 , n5731 );
xor ( n11051 , n11049 , n11050 );
xor ( n11052 , n11051 , n7500 );
xor ( n11053 , n11032 , n11052 );
not ( n11054 , n11053 );
not ( n11055 , n6474 );
buf ( n11056 , n5732 );
and ( n11057 , n11055 , n11056 );
buf ( n11058 , n5733 );
xor ( n11059 , n11058 , n11056 );
and ( n11060 , n11059 , n6474 );
or ( n11061 , n11057 , n11060 );
xor ( n11062 , n11061 , n10697 );
xor ( n11063 , n11062 , n10713 );
and ( n11064 , n11054 , n11063 );
xor ( n11065 , n11010 , n11064 );
xor ( n11066 , n11007 , n11065 );
xor ( n11067 , n10888 , n11066 );
not ( n11068 , n11067 );
not ( n11069 , n6474 );
buf ( n11070 , n5734 );
and ( n11071 , n11069 , n11070 );
buf ( n11072 , n5735 );
xor ( n11073 , n11072 , n11070 );
and ( n11074 , n11073 , n6474 );
or ( n11075 , n11071 , n11074 );
not ( n11076 , n6474 );
buf ( n11077 , n5736 );
and ( n11078 , n11076 , n11077 );
buf ( n11079 , n5737 );
xor ( n11080 , n11079 , n11077 );
and ( n11081 , n11080 , n6474 );
or ( n11082 , n11078 , n11081 );
xor ( n11083 , n11075 , n11082 );
buf ( n11084 , n5738 );
xor ( n11085 , n11083 , n11084 );
buf ( n11086 , n5739 );
xor ( n11087 , n11085 , n11086 );
buf ( n11088 , n5740 );
xor ( n11089 , n11087 , n11088 );
xor ( n11090 , n10043 , n11089 );
not ( n11091 , n6474 );
buf ( n11092 , n5741 );
and ( n11093 , n11091 , n11092 );
buf ( n11094 , n5742 );
xor ( n11095 , n11094 , n11092 );
and ( n11096 , n11095 , n6474 );
or ( n11097 , n11093 , n11096 );
not ( n11098 , n6474 );
buf ( n11099 , n5743 );
and ( n11100 , n11098 , n11099 );
buf ( n11101 , n5744 );
xor ( n11102 , n11101 , n11099 );
and ( n11103 , n11102 , n6474 );
or ( n11104 , n11100 , n11103 );
xor ( n11105 , n11097 , n11104 );
buf ( n11106 , n5745 );
xor ( n11107 , n11105 , n11106 );
buf ( n11108 , n5746 );
xor ( n11109 , n11107 , n11108 );
xor ( n11110 , n11109 , n7748 );
xor ( n11111 , n11090 , n11110 );
not ( n11112 , n6474 );
buf ( n11113 , n5747 );
and ( n11114 , n11112 , n11113 );
buf ( n11115 , n5748 );
xor ( n11116 , n11115 , n11113 );
and ( n11117 , n11116 , n6474 );
or ( n11118 , n11114 , n11117 );
not ( n11119 , n6474 );
buf ( n11120 , n5749 );
and ( n11121 , n11119 , n11120 );
buf ( n11122 , n5750 );
xor ( n11123 , n11122 , n11120 );
and ( n11124 , n11123 , n6474 );
or ( n11125 , n11121 , n11124 );
xor ( n11126 , n11118 , n11125 );
buf ( n11127 , n5751 );
xor ( n11128 , n11126 , n11127 );
buf ( n11129 , n5752 );
xor ( n11130 , n11128 , n11129 );
buf ( n11131 , n5753 );
xor ( n11132 , n11130 , n11131 );
xor ( n11133 , n8174 , n11132 );
not ( n11134 , n6474 );
buf ( n11135 , n5754 );
and ( n11136 , n11134 , n11135 );
buf ( n11137 , n5755 );
xor ( n11138 , n11137 , n11135 );
and ( n11139 , n11138 , n6474 );
or ( n11140 , n11136 , n11139 );
xor ( n11141 , n11140 , n11061 );
buf ( n11142 , n5756 );
xor ( n11143 , n11141 , n11142 );
buf ( n11144 , n5757 );
xor ( n11145 , n11143 , n11144 );
xor ( n11146 , n11145 , n10676 );
xor ( n11147 , n11133 , n11146 );
not ( n11148 , n11147 );
not ( n11149 , n6474 );
buf ( n11150 , n5758 );
and ( n11151 , n11149 , n11150 );
buf ( n11152 , n5759 );
xor ( n11153 , n11152 , n11150 );
and ( n11154 , n11153 , n6474 );
or ( n11155 , n11151 , n11154 );
xor ( n11156 , n11155 , n8799 );
not ( n11157 , n6474 );
buf ( n11158 , n5760 );
and ( n11159 , n11157 , n11158 );
buf ( n11160 , n5761 );
xor ( n11161 , n11160 , n11158 );
and ( n11162 , n11161 , n6474 );
or ( n11163 , n11159 , n11162 );
buf ( n11164 , n5762 );
xor ( n11165 , n11163 , n11164 );
buf ( n11166 , n5763 );
xor ( n11167 , n11165 , n11166 );
buf ( n11168 , n5764 );
xor ( n11169 , n11167 , n11168 );
buf ( n11170 , n5765 );
xor ( n11171 , n11169 , n11170 );
xor ( n11172 , n11156 , n11171 );
and ( n11173 , n11148 , n11172 );
xor ( n11174 , n11111 , n11173 );
not ( n11175 , n6474 );
buf ( n11176 , n5766 );
and ( n11177 , n11175 , n11176 );
buf ( n11178 , n5767 );
xor ( n11179 , n11178 , n11176 );
and ( n11180 , n11179 , n6474 );
or ( n11181 , n11177 , n11180 );
xor ( n11182 , n11181 , n7474 );
buf ( n11183 , n5768 );
xor ( n11184 , n11182 , n11183 );
xor ( n11185 , n11184 , n8164 );
buf ( n11186 , n5769 );
xor ( n11187 , n11185 , n11186 );
xor ( n11188 , n10765 , n11187 );
not ( n11189 , n6474 );
buf ( n11190 , n5770 );
and ( n11191 , n11189 , n11190 );
buf ( n11192 , n5771 );
xor ( n11193 , n11192 , n11190 );
and ( n11194 , n11193 , n6474 );
or ( n11195 , n11191 , n11194 );
buf ( n11196 , n5772 );
xor ( n11197 , n11195 , n11196 );
buf ( n11198 , n5773 );
xor ( n11199 , n11197 , n11198 );
xor ( n11200 , n11199 , n6829 );
xor ( n11201 , n11200 , n10889 );
xor ( n11202 , n11188 , n11201 );
xor ( n11203 , n6583 , n7732 );
xor ( n11204 , n11203 , n8076 );
not ( n11205 , n11204 );
xor ( n11206 , n9637 , n10713 );
not ( n11207 , n6474 );
buf ( n11208 , n5774 );
and ( n11209 , n11207 , n11208 );
buf ( n11210 , n5775 );
xor ( n11211 , n11210 , n11208 );
and ( n11212 , n11211 , n6474 );
or ( n11213 , n11209 , n11212 );
not ( n11214 , n6474 );
buf ( n11215 , n5776 );
and ( n11216 , n11214 , n11215 );
buf ( n11217 , n5777 );
xor ( n11218 , n11217 , n11215 );
and ( n11219 , n11218 , n6474 );
or ( n11220 , n11216 , n11219 );
xor ( n11221 , n11213 , n11220 );
buf ( n11222 , n5778 );
xor ( n11223 , n11221 , n11222 );
buf ( n11224 , n5779 );
xor ( n11225 , n11223 , n11224 );
buf ( n11226 , n5780 );
xor ( n11227 , n11225 , n11226 );
xor ( n11228 , n11206 , n11227 );
and ( n11229 , n11205 , n11228 );
xor ( n11230 , n11202 , n11229 );
xor ( n11231 , n10462 , n10246 );
not ( n11232 , n6474 );
buf ( n11233 , n5781 );
and ( n11234 , n11232 , n11233 );
buf ( n11235 , n5782 );
xor ( n11236 , n11235 , n11233 );
and ( n11237 , n11236 , n6474 );
or ( n11238 , n11234 , n11237 );
not ( n11239 , n6474 );
buf ( n11240 , n5783 );
and ( n11241 , n11239 , n11240 );
buf ( n11242 , n5784 );
xor ( n11243 , n11242 , n11240 );
and ( n11244 , n11243 , n6474 );
or ( n11245 , n11241 , n11244 );
xor ( n11246 , n11238 , n11245 );
buf ( n11247 , n5785 );
xor ( n11248 , n11246 , n11247 );
buf ( n11249 , n5786 );
xor ( n11250 , n11248 , n11249 );
buf ( n11251 , n5787 );
xor ( n11252 , n11250 , n11251 );
xor ( n11253 , n11231 , n11252 );
buf ( n11254 , n5788 );
not ( n11255 , n6474 );
buf ( n11256 , n5789 );
and ( n11257 , n11255 , n11256 );
buf ( n11258 , n5790 );
xor ( n11259 , n11258 , n11256 );
and ( n11260 , n11259 , n6474 );
or ( n11261 , n11257 , n11260 );
not ( n11262 , n6474 );
buf ( n11263 , n5791 );
and ( n11264 , n11262 , n11263 );
buf ( n11265 , n5792 );
xor ( n11266 , n11265 , n11263 );
and ( n11267 , n11266 , n6474 );
or ( n11268 , n11264 , n11267 );
xor ( n11269 , n11261 , n11268 );
buf ( n11270 , n5793 );
xor ( n11271 , n11269 , n11270 );
buf ( n11272 , n5794 );
xor ( n11273 , n11271 , n11272 );
buf ( n11274 , n5795 );
xor ( n11275 , n11273 , n11274 );
xor ( n11276 , n11254 , n11275 );
xor ( n11277 , n11276 , n9559 );
not ( n11278 , n11277 );
xor ( n11279 , n6524 , n10731 );
xor ( n11280 , n11279 , n10745 );
and ( n11281 , n11278 , n11280 );
xor ( n11282 , n11253 , n11281 );
xor ( n11283 , n11230 , n11282 );
not ( n11284 , n6474 );
buf ( n11285 , n5796 );
and ( n11286 , n11284 , n11285 );
buf ( n11287 , n5797 );
xor ( n11288 , n11287 , n11285 );
and ( n11289 , n11288 , n6474 );
or ( n11290 , n11286 , n11289 );
not ( n11291 , n6474 );
buf ( n11292 , n5798 );
and ( n11293 , n11291 , n11292 );
buf ( n11294 , n5799 );
xor ( n11295 , n11294 , n11292 );
and ( n11296 , n11295 , n6474 );
or ( n11297 , n11293 , n11296 );
xor ( n11298 , n11290 , n11297 );
buf ( n11299 , n5800 );
xor ( n11300 , n11298 , n11299 );
buf ( n11301 , n5801 );
xor ( n11302 , n11300 , n11301 );
buf ( n11303 , n5802 );
xor ( n11304 , n11302 , n11303 );
xor ( n11305 , n7534 , n11304 );
xor ( n11306 , n11305 , n9850 );
buf ( n11307 , n5803 );
xor ( n11308 , n11307 , n9002 );
not ( n11309 , n6474 );
buf ( n11310 , n5804 );
and ( n11311 , n11309 , n11310 );
buf ( n11312 , n5805 );
xor ( n11313 , n11312 , n11310 );
and ( n11314 , n11313 , n6474 );
or ( n11315 , n11311 , n11314 );
not ( n11316 , n6474 );
buf ( n11317 , n5806 );
and ( n11318 , n11316 , n11317 );
buf ( n11319 , n5807 );
xor ( n11320 , n11319 , n11317 );
and ( n11321 , n11320 , n6474 );
or ( n11322 , n11318 , n11321 );
xor ( n11323 , n11315 , n11322 );
buf ( n11324 , n5808 );
xor ( n11325 , n11323 , n11324 );
buf ( n11326 , n5809 );
xor ( n11327 , n11325 , n11326 );
buf ( n11328 , n5810 );
xor ( n11329 , n11327 , n11328 );
xor ( n11330 , n11308 , n11329 );
not ( n11331 , n11330 );
not ( n11332 , n6474 );
buf ( n11333 , n5811 );
and ( n11334 , n11332 , n11333 );
buf ( n11335 , n5812 );
xor ( n11336 , n11335 , n11333 );
and ( n11337 , n11336 , n6474 );
or ( n11338 , n11334 , n11337 );
xor ( n11339 , n11338 , n10007 );
buf ( n11340 , n5813 );
xor ( n11341 , n11339 , n11340 );
buf ( n11342 , n5814 );
xor ( n11343 , n11341 , n11342 );
buf ( n11344 , n5815 );
xor ( n11345 , n11343 , n11344 );
xor ( n11346 , n11213 , n11345 );
not ( n11347 , n6474 );
buf ( n11348 , n5816 );
and ( n11349 , n11347 , n11348 );
buf ( n11350 , n5817 );
xor ( n11351 , n11350 , n11348 );
and ( n11352 , n11351 , n6474 );
or ( n11353 , n11349 , n11352 );
not ( n11354 , n6474 );
buf ( n11355 , n5818 );
and ( n11356 , n11354 , n11355 );
buf ( n11357 , n5819 );
xor ( n11358 , n11357 , n11355 );
and ( n11359 , n11358 , n6474 );
or ( n11360 , n11356 , n11359 );
xor ( n11361 , n11353 , n11360 );
buf ( n11362 , n5820 );
xor ( n11363 , n11361 , n11362 );
buf ( n11364 , n5821 );
xor ( n11365 , n11363 , n11364 );
buf ( n11366 , n5822 );
xor ( n11367 , n11365 , n11366 );
xor ( n11368 , n11346 , n11367 );
and ( n11369 , n11331 , n11368 );
xor ( n11370 , n11306 , n11369 );
xor ( n11371 , n11283 , n11370 );
xor ( n11372 , n9531 , n6606 );
xor ( n11373 , n11372 , n9123 );
buf ( n11374 , n5823 );
xor ( n11375 , n11374 , n9217 );
xor ( n11376 , n11375 , n9417 );
not ( n11377 , n11376 );
not ( n11378 , n6474 );
buf ( n11379 , n5824 );
and ( n11380 , n11378 , n11379 );
buf ( n11381 , n5825 );
xor ( n11382 , n11381 , n11379 );
and ( n11383 , n11382 , n6474 );
or ( n11384 , n11380 , n11383 );
xor ( n11385 , n11384 , n8495 );
xor ( n11386 , n11385 , n8517 );
and ( n11387 , n11377 , n11386 );
xor ( n11388 , n11373 , n11387 );
xor ( n11389 , n11371 , n11388 );
buf ( n11390 , n5826 );
not ( n11391 , n6474 );
buf ( n11392 , n5827 );
and ( n11393 , n11391 , n11392 );
buf ( n11394 , n5828 );
xor ( n11395 , n11394 , n11392 );
and ( n11396 , n11395 , n6474 );
or ( n11397 , n11393 , n11396 );
buf ( n11398 , n5829 );
xor ( n11399 , n11397 , n11398 );
buf ( n11400 , n5830 );
xor ( n11401 , n11399 , n11400 );
buf ( n11402 , n5831 );
xor ( n11403 , n11401 , n11402 );
buf ( n11404 , n5832 );
xor ( n11405 , n11403 , n11404 );
xor ( n11406 , n11390 , n11405 );
not ( n11407 , n6474 );
buf ( n11408 , n5833 );
and ( n11409 , n11407 , n11408 );
buf ( n11410 , n5834 );
xor ( n11411 , n11410 , n11408 );
and ( n11412 , n11411 , n6474 );
or ( n11413 , n11409 , n11412 );
not ( n11414 , n6474 );
buf ( n11415 , n5835 );
and ( n11416 , n11414 , n11415 );
buf ( n11417 , n5836 );
xor ( n11418 , n11417 , n11415 );
and ( n11419 , n11418 , n6474 );
or ( n11420 , n11416 , n11419 );
xor ( n11421 , n11413 , n11420 );
buf ( n11422 , n5837 );
xor ( n11423 , n11421 , n11422 );
buf ( n11424 , n5838 );
xor ( n11425 , n11423 , n11424 );
buf ( n11426 , n5839 );
xor ( n11427 , n11425 , n11426 );
xor ( n11428 , n11406 , n11427 );
not ( n11429 , n11111 );
and ( n11430 , n11429 , n11147 );
xor ( n11431 , n11428 , n11430 );
xor ( n11432 , n11389 , n11431 );
xor ( n11433 , n11174 , n11432 );
xor ( n11434 , n11338 , n10022 );
xor ( n11435 , n11434 , n10044 );
xor ( n11436 , n10458 , n10246 );
xor ( n11437 , n11436 , n11252 );
not ( n11438 , n11437 );
xor ( n11439 , n9285 , n8660 );
xor ( n11440 , n11439 , n10105 );
and ( n11441 , n11438 , n11440 );
xor ( n11442 , n11435 , n11441 );
not ( n11443 , n6474 );
buf ( n11444 , n5840 );
and ( n11445 , n11443 , n11444 );
buf ( n11446 , n5841 );
xor ( n11447 , n11446 , n11444 );
and ( n11448 , n11447 , n6474 );
or ( n11449 , n11445 , n11448 );
not ( n11450 , n6474 );
buf ( n11451 , n5842 );
and ( n11452 , n11450 , n11451 );
buf ( n11453 , n5843 );
xor ( n11454 , n11453 , n11451 );
and ( n11455 , n11454 , n6474 );
or ( n11456 , n11452 , n11455 );
xor ( n11457 , n11449 , n11456 );
buf ( n11458 , n5844 );
xor ( n11459 , n11457 , n11458 );
xor ( n11460 , n11459 , n6963 );
buf ( n11461 , n5845 );
xor ( n11462 , n11460 , n11461 );
xor ( n11463 , n7194 , n11462 );
xor ( n11464 , n11463 , n10263 );
xor ( n11465 , n10139 , n10768 );
xor ( n11466 , n11465 , n10790 );
not ( n11467 , n11466 );
not ( n11468 , n6474 );
buf ( n11469 , n5846 );
and ( n11470 , n11468 , n11469 );
buf ( n11471 , n5847 );
xor ( n11472 , n11471 , n11469 );
and ( n11473 , n11472 , n6474 );
or ( n11474 , n11470 , n11473 );
buf ( n11475 , n5848 );
xor ( n11476 , n11474 , n11475 );
xor ( n11477 , n11476 , n10148 );
buf ( n11478 , n5849 );
xor ( n11479 , n11477 , n11478 );
buf ( n11480 , n5850 );
xor ( n11481 , n11479 , n11480 );
xor ( n11482 , n8908 , n11481 );
xor ( n11483 , n11482 , n8696 );
and ( n11484 , n11467 , n11483 );
xor ( n11485 , n11464 , n11484 );
xor ( n11486 , n11442 , n11485 );
xor ( n11487 , n10030 , n11089 );
xor ( n11488 , n11487 , n11110 );
xor ( n11489 , n7514 , n8016 );
xor ( n11490 , n11489 , n11304 );
not ( n11491 , n11490 );
not ( n11492 , n6474 );
buf ( n11493 , n5851 );
and ( n11494 , n11492 , n11493 );
buf ( n11495 , n5852 );
xor ( n11496 , n11495 , n11493 );
and ( n11497 , n11496 , n6474 );
or ( n11498 , n11494 , n11497 );
not ( n11499 , n6474 );
buf ( n11500 , n5853 );
and ( n11501 , n11499 , n11500 );
buf ( n11502 , n5854 );
xor ( n11503 , n11502 , n11500 );
and ( n11504 , n11503 , n6474 );
or ( n11505 , n11501 , n11504 );
xor ( n11506 , n11498 , n11505 );
buf ( n11507 , n5855 );
xor ( n11508 , n11506 , n11507 );
buf ( n11509 , n5856 );
xor ( n11510 , n11508 , n11509 );
buf ( n11511 , n5857 );
xor ( n11512 , n11510 , n11511 );
xor ( n11513 , n7856 , n11512 );
xor ( n11514 , n11384 , n8475 );
buf ( n11515 , n5858 );
xor ( n11516 , n11514 , n11515 );
buf ( n11517 , n5859 );
xor ( n11518 , n11516 , n11517 );
buf ( n11519 , n5860 );
xor ( n11520 , n11518 , n11519 );
xor ( n11521 , n11513 , n11520 );
and ( n11522 , n11491 , n11521 );
xor ( n11523 , n11488 , n11522 );
xor ( n11524 , n11486 , n11523 );
xor ( n11525 , n7918 , n6538 );
xor ( n11526 , n11525 , n6560 );
not ( n11527 , n6474 );
buf ( n11528 , n5861 );
and ( n11529 , n11527 , n11528 );
buf ( n11530 , n5862 );
xor ( n11531 , n11530 , n11528 );
and ( n11532 , n11531 , n6474 );
or ( n11533 , n11529 , n11532 );
xor ( n11534 , n11533 , n10929 );
not ( n11535 , n6474 );
buf ( n11536 , n5863 );
and ( n11537 , n11535 , n11536 );
buf ( n11538 , n5864 );
xor ( n11539 , n11538 , n11536 );
and ( n11540 , n11539 , n6474 );
or ( n11541 , n11537 , n11540 );
not ( n11542 , n6474 );
buf ( n11543 , n5865 );
and ( n11544 , n11542 , n11543 );
buf ( n11545 , n5866 );
xor ( n11546 , n11545 , n11543 );
and ( n11547 , n11546 , n6474 );
or ( n11548 , n11544 , n11547 );
xor ( n11549 , n11541 , n11548 );
buf ( n11550 , n5867 );
xor ( n11551 , n11549 , n11550 );
buf ( n11552 , n5868 );
xor ( n11553 , n11551 , n11552 );
buf ( n11554 , n5869 );
xor ( n11555 , n11553 , n11554 );
xor ( n11556 , n11534 , n11555 );
not ( n11557 , n11556 );
xor ( n11558 , n6758 , n9400 );
xor ( n11559 , n11558 , n10309 );
and ( n11560 , n11557 , n11559 );
xor ( n11561 , n11526 , n11560 );
xor ( n11562 , n11524 , n11561 );
not ( n11563 , n6474 );
buf ( n11564 , n5870 );
and ( n11565 , n11563 , n11564 );
buf ( n11566 , n5871 );
xor ( n11567 , n11566 , n11564 );
and ( n11568 , n11567 , n6474 );
or ( n11569 , n11565 , n11568 );
not ( n11570 , n6474 );
buf ( n11571 , n5872 );
and ( n11572 , n11570 , n11571 );
buf ( n11573 , n5873 );
xor ( n11574 , n11573 , n11571 );
and ( n11575 , n11574 , n6474 );
or ( n11576 , n11572 , n11575 );
xor ( n11577 , n11569 , n11576 );
buf ( n11578 , n5874 );
xor ( n11579 , n11577 , n11578 );
buf ( n11580 , n5875 );
xor ( n11581 , n11579 , n11580 );
buf ( n11582 , n5876 );
xor ( n11583 , n11581 , n11582 );
xor ( n11584 , n10683 , n11583 );
not ( n11585 , n6474 );
buf ( n11586 , n5877 );
and ( n11587 , n11585 , n11586 );
buf ( n11588 , n5878 );
xor ( n11589 , n11588 , n11586 );
and ( n11590 , n11589 , n6474 );
or ( n11591 , n11587 , n11590 );
not ( n11592 , n6474 );
buf ( n11593 , n5879 );
and ( n11594 , n11592 , n11593 );
buf ( n11595 , n5880 );
xor ( n11596 , n11595 , n11593 );
and ( n11597 , n11596 , n6474 );
or ( n11598 , n11594 , n11597 );
xor ( n11599 , n11591 , n11598 );
buf ( n11600 , n5881 );
xor ( n11601 , n11599 , n11600 );
buf ( n11602 , n5882 );
xor ( n11603 , n11601 , n11602 );
xor ( n11604 , n11603 , n10969 );
xor ( n11605 , n11584 , n11604 );
not ( n11606 , n6474 );
buf ( n11607 , n5883 );
and ( n11608 , n11606 , n11607 );
buf ( n11609 , n5884 );
xor ( n11610 , n11609 , n11607 );
and ( n11611 , n11610 , n6474 );
or ( n11612 , n11608 , n11611 );
xor ( n11613 , n11612 , n9217 );
xor ( n11614 , n11613 , n9417 );
not ( n11615 , n11614 );
not ( n11616 , n6474 );
buf ( n11617 , n5885 );
and ( n11618 , n11616 , n11617 );
buf ( n11619 , n5886 );
xor ( n11620 , n11619 , n11617 );
and ( n11621 , n11620 , n6474 );
or ( n11622 , n11618 , n11621 );
not ( n11623 , n6474 );
buf ( n11624 , n5887 );
and ( n11625 , n11623 , n11624 );
buf ( n11626 , n5888 );
xor ( n11627 , n11626 , n11624 );
and ( n11628 , n11627 , n6474 );
or ( n11629 , n11625 , n11628 );
xor ( n11630 , n11622 , n11629 );
buf ( n11631 , n5889 );
xor ( n11632 , n11630 , n11631 );
buf ( n11633 , n5890 );
xor ( n11634 , n11632 , n11633 );
buf ( n11635 , n5891 );
xor ( n11636 , n11634 , n11635 );
xor ( n11637 , n6822 , n11636 );
not ( n11638 , n6474 );
buf ( n11639 , n5892 );
and ( n11640 , n11638 , n11639 );
buf ( n11641 , n5893 );
xor ( n11642 , n11641 , n11639 );
and ( n11643 , n11642 , n6474 );
or ( n11644 , n11640 , n11643 );
not ( n11645 , n6474 );
buf ( n11646 , n5894 );
and ( n11647 , n11645 , n11646 );
buf ( n11648 , n5895 );
xor ( n11649 , n11648 , n11646 );
and ( n11650 , n11649 , n6474 );
or ( n11651 , n11647 , n11650 );
xor ( n11652 , n11644 , n11651 );
buf ( n11653 , n5896 );
xor ( n11654 , n11652 , n11653 );
xor ( n11655 , n11654 , n11390 );
buf ( n11656 , n5897 );
xor ( n11657 , n11655 , n11656 );
xor ( n11658 , n11637 , n11657 );
and ( n11659 , n11615 , n11658 );
xor ( n11660 , n11605 , n11659 );
xor ( n11661 , n11562 , n11660 );
xor ( n11662 , n11433 , n11661 );
and ( n11663 , n11068 , n11662 );
xor ( n11664 , n10631 , n11663 );
and ( n11665 , n11664 , n6475 );
or ( n11666 , n9748 , n11665 );
and ( n11667 , n9745 , n11666 );
buf ( n11668 , n11667 );
buf ( n11669 , n11668 );
not ( n11670 , n6469 );
not ( n11671 , n6475 );
and ( n11672 , n11671 , n9661 );
xor ( n11673 , n8682 , n10170 );
xor ( n11674 , n11673 , n7030 );
not ( n11675 , n6474 );
buf ( n11676 , n5898 );
and ( n11677 , n11675 , n11676 );
buf ( n11678 , n5899 );
xor ( n11679 , n11678 , n11676 );
and ( n11680 , n11679 , n6474 );
or ( n11681 , n11677 , n11680 );
not ( n11682 , n6474 );
buf ( n11683 , n5900 );
and ( n11684 , n11682 , n11683 );
buf ( n11685 , n5901 );
xor ( n11686 , n11685 , n11683 );
and ( n11687 , n11686 , n6474 );
or ( n11688 , n11684 , n11687 );
xor ( n11689 , n11681 , n11688 );
buf ( n11690 , n5902 );
xor ( n11691 , n11689 , n11690 );
xor ( n11692 , n11691 , n9948 );
xor ( n11693 , n11692 , n11008 );
xor ( n11694 , n9865 , n11693 );
not ( n11695 , n6474 );
buf ( n11696 , n5903 );
and ( n11697 , n11695 , n11696 );
buf ( n11698 , n5904 );
xor ( n11699 , n11698 , n11696 );
and ( n11700 , n11699 , n6474 );
or ( n11701 , n11697 , n11700 );
not ( n11702 , n6474 );
buf ( n11703 , n5905 );
and ( n11704 , n11702 , n11703 );
buf ( n11705 , n5906 );
xor ( n11706 , n11705 , n11703 );
and ( n11707 , n11706 , n6474 );
or ( n11708 , n11704 , n11707 );
xor ( n11709 , n11701 , n11708 );
buf ( n11710 , n5907 );
xor ( n11711 , n11709 , n11710 );
xor ( n11712 , n11711 , n9318 );
buf ( n11713 , n5908 );
xor ( n11714 , n11712 , n11713 );
xor ( n11715 , n11694 , n11714 );
not ( n11716 , n11715 );
xor ( n11717 , n7203 , n11462 );
xor ( n11718 , n11717 , n10263 );
and ( n11719 , n11716 , n11718 );
xor ( n11720 , n11674 , n11719 );
not ( n11721 , n6474 );
buf ( n11722 , n5909 );
and ( n11723 , n11721 , n11722 );
buf ( n11724 , n5910 );
xor ( n11725 , n11724 , n11722 );
and ( n11726 , n11725 , n6474 );
or ( n11727 , n11723 , n11726 );
not ( n11728 , n6474 );
buf ( n11729 , n5911 );
and ( n11730 , n11728 , n11729 );
buf ( n11731 , n5912 );
xor ( n11732 , n11731 , n11729 );
and ( n11733 , n11732 , n6474 );
or ( n11734 , n11730 , n11733 );
xor ( n11735 , n11727 , n11734 );
buf ( n11736 , n5913 );
xor ( n11737 , n11735 , n11736 );
buf ( n11738 , n5914 );
xor ( n11739 , n11737 , n11738 );
buf ( n11740 , n5915 );
xor ( n11741 , n11739 , n11740 );
xor ( n11742 , n9001 , n11741 );
not ( n11743 , n6474 );
buf ( n11744 , n5916 );
and ( n11745 , n11743 , n11744 );
buf ( n11746 , n5917 );
xor ( n11747 , n11746 , n11744 );
and ( n11748 , n11747 , n6474 );
or ( n11749 , n11745 , n11748 );
not ( n11750 , n6474 );
buf ( n11751 , n5918 );
and ( n11752 , n11750 , n11751 );
buf ( n11753 , n5919 );
xor ( n11754 , n11753 , n11751 );
and ( n11755 , n11754 , n6474 );
or ( n11756 , n11752 , n11755 );
xor ( n11757 , n11749 , n11756 );
buf ( n11758 , n5920 );
xor ( n11759 , n11757 , n11758 );
buf ( n11760 , n5921 );
xor ( n11761 , n11759 , n11760 );
buf ( n11762 , n5922 );
xor ( n11763 , n11761 , n11762 );
xor ( n11764 , n11742 , n11763 );
xor ( n11765 , n8899 , n11481 );
xor ( n11766 , n11765 , n8696 );
not ( n11767 , n11766 );
not ( n11768 , n6474 );
buf ( n11769 , n5923 );
and ( n11770 , n11768 , n11769 );
buf ( n11771 , n5924 );
xor ( n11772 , n11771 , n11769 );
and ( n11773 , n11772 , n6474 );
or ( n11774 , n11770 , n11773 );
not ( n11775 , n6474 );
buf ( n11776 , n5925 );
and ( n11777 , n11775 , n11776 );
buf ( n11778 , n5926 );
xor ( n11779 , n11778 , n11776 );
and ( n11780 , n11779 , n6474 );
or ( n11781 , n11777 , n11780 );
xor ( n11782 , n11774 , n11781 );
buf ( n11783 , n5927 );
xor ( n11784 , n11782 , n11783 );
xor ( n11785 , n11784 , n10878 );
xor ( n11786 , n11785 , n10379 );
xor ( n11787 , n8284 , n11786 );
not ( n11788 , n6474 );
buf ( n11789 , n5928 );
and ( n11790 , n11788 , n11789 );
buf ( n11791 , n5929 );
xor ( n11792 , n11791 , n11789 );
and ( n11793 , n11792 , n6474 );
or ( n11794 , n11790 , n11793 );
not ( n11795 , n6474 );
buf ( n11796 , n5930 );
and ( n11797 , n11795 , n11796 );
buf ( n11798 , n5931 );
xor ( n11799 , n11798 , n11796 );
and ( n11800 , n11799 , n6474 );
or ( n11801 , n11797 , n11800 );
xor ( n11802 , n11794 , n11801 );
buf ( n11803 , n5932 );
xor ( n11804 , n11802 , n11803 );
buf ( n11805 , n5933 );
xor ( n11806 , n11804 , n11805 );
buf ( n11807 , n5934 );
xor ( n11808 , n11806 , n11807 );
xor ( n11809 , n11787 , n11808 );
and ( n11810 , n11767 , n11809 );
xor ( n11811 , n11764 , n11810 );
xor ( n11812 , n9672 , n11227 );
not ( n11813 , n6474 );
buf ( n11814 , n5935 );
and ( n11815 , n11813 , n11814 );
buf ( n11816 , n5936 );
xor ( n11817 , n11816 , n11814 );
and ( n11818 , n11817 , n6474 );
or ( n11819 , n11815 , n11818 );
not ( n11820 , n6474 );
buf ( n11821 , n5937 );
and ( n11822 , n11820 , n11821 );
buf ( n11823 , n5938 );
xor ( n11824 , n11823 , n11821 );
and ( n11825 , n11824 , n6474 );
or ( n11826 , n11822 , n11825 );
xor ( n11827 , n11819 , n11826 );
buf ( n11828 , n5939 );
xor ( n11829 , n11827 , n11828 );
buf ( n11830 , n5940 );
xor ( n11831 , n11829 , n11830 );
buf ( n11832 , n5941 );
xor ( n11833 , n11831 , n11832 );
xor ( n11834 , n11812 , n11833 );
not ( n11835 , n6474 );
buf ( n11836 , n5942 );
and ( n11837 , n11835 , n11836 );
buf ( n11838 , n5943 );
xor ( n11839 , n11838 , n11836 );
and ( n11840 , n11839 , n6474 );
or ( n11841 , n11837 , n11840 );
xor ( n11842 , n11841 , n8574 );
xor ( n11843 , n11842 , n7441 );
not ( n11844 , n11843 );
not ( n11845 , n6474 );
buf ( n11846 , n5944 );
and ( n11847 , n11845 , n11846 );
buf ( n11848 , n5945 );
xor ( n11849 , n11848 , n11846 );
and ( n11850 , n11849 , n6474 );
or ( n11851 , n11847 , n11850 );
not ( n11852 , n6474 );
buf ( n11853 , n5946 );
and ( n11854 , n11852 , n11853 );
buf ( n11855 , n5947 );
xor ( n11856 , n11855 , n11853 );
and ( n11857 , n11856 , n6474 );
or ( n11858 , n11854 , n11857 );
xor ( n11859 , n11851 , n11858 );
buf ( n11860 , n5948 );
xor ( n11861 , n11859 , n11860 );
buf ( n11862 , n5949 );
xor ( n11863 , n11861 , n11862 );
buf ( n11864 , n5950 );
xor ( n11865 , n11863 , n11864 );
xor ( n11866 , n8085 , n11865 );
not ( n11867 , n6474 );
buf ( n11868 , n5951 );
and ( n11869 , n11867 , n11868 );
buf ( n11870 , n5952 );
xor ( n11871 , n11870 , n11868 );
and ( n11872 , n11871 , n6474 );
or ( n11873 , n11869 , n11872 );
xor ( n11874 , n11873 , n9133 );
buf ( n11875 , n5953 );
xor ( n11876 , n11874 , n11875 );
buf ( n11877 , n5954 );
xor ( n11878 , n11876 , n11877 );
xor ( n11879 , n11878 , n10868 );
xor ( n11880 , n11866 , n11879 );
and ( n11881 , n11844 , n11880 );
xor ( n11882 , n11834 , n11881 );
xor ( n11883 , n11811 , n11882 );
xor ( n11884 , n10789 , n11201 );
not ( n11885 , n6474 );
buf ( n11886 , n5955 );
and ( n11887 , n11885 , n11886 );
buf ( n11888 , n5956 );
xor ( n11889 , n11888 , n11886 );
and ( n11890 , n11889 , n6474 );
or ( n11891 , n11887 , n11890 );
not ( n11892 , n6474 );
buf ( n11893 , n5957 );
and ( n11894 , n11892 , n11893 );
buf ( n11895 , n5958 );
xor ( n11896 , n11895 , n11893 );
and ( n11897 , n11896 , n6474 );
or ( n11898 , n11894 , n11897 );
xor ( n11899 , n11891 , n11898 );
buf ( n11900 , n5959 );
xor ( n11901 , n11899 , n11900 );
buf ( n11902 , n5960 );
xor ( n11903 , n11901 , n11902 );
buf ( n11904 , n5961 );
xor ( n11905 , n11903 , n11904 );
xor ( n11906 , n11884 , n11905 );
not ( n11907 , n11674 );
and ( n11908 , n11907 , n11715 );
xor ( n11909 , n11906 , n11908 );
xor ( n11910 , n11883 , n11909 );
xor ( n11911 , n8841 , n6739 );
not ( n11912 , n6474 );
buf ( n11913 , n5962 );
and ( n11914 , n11912 , n11913 );
buf ( n11915 , n5963 );
xor ( n11916 , n11915 , n11913 );
and ( n11917 , n11916 , n6474 );
or ( n11918 , n11914 , n11917 );
buf ( n11919 , n5964 );
buf ( n11920 , n11919 );
xor ( n11921 , n11918 , n11920 );
buf ( n11922 , n5965 );
xor ( n11923 , n11921 , n11922 );
buf ( n11924 , n5966 );
xor ( n11925 , n11923 , n11924 );
buf ( n11926 , n5967 );
xor ( n11927 , n11925 , n11926 );
xor ( n11928 , n11911 , n11927 );
not ( n11929 , n6474 );
buf ( n11930 , n5968 );
and ( n11931 , n11929 , n11930 );
buf ( n11932 , n5969 );
xor ( n11933 , n11932 , n11930 );
and ( n11934 , n11933 , n6474 );
or ( n11935 , n11931 , n11934 );
not ( n11936 , n6474 );
buf ( n11937 , n5970 );
and ( n11938 , n11936 , n11937 );
buf ( n11939 , n5971 );
xor ( n11940 , n11939 , n11937 );
and ( n11941 , n11940 , n6474 );
or ( n11942 , n11938 , n11941 );
xor ( n11943 , n11935 , n11942 );
buf ( n11944 , n5972 );
xor ( n11945 , n11943 , n11944 );
buf ( n11946 , n5973 );
xor ( n11947 , n11945 , n11946 );
buf ( n11948 , n5974 );
xor ( n11949 , n11947 , n11948 );
xor ( n11950 , n9702 , n11949 );
xor ( n11951 , n11950 , n10574 );
not ( n11952 , n11951 );
not ( n11953 , n6474 );
buf ( n11954 , n5975 );
and ( n11955 , n11953 , n11954 );
buf ( n11956 , n5976 );
xor ( n11957 , n11956 , n11954 );
and ( n11958 , n11957 , n6474 );
or ( n11959 , n11955 , n11958 );
xor ( n11960 , n11959 , n6827 );
not ( n11961 , n6474 );
buf ( n11962 , n5977 );
and ( n11963 , n11961 , n11962 );
buf ( n11964 , n5978 );
xor ( n11965 , n11964 , n11962 );
and ( n11966 , n11965 , n6474 );
or ( n11967 , n11963 , n11966 );
not ( n11968 , n6474 );
buf ( n11969 , n5979 );
and ( n11970 , n11968 , n11969 );
buf ( n11971 , n5980 );
xor ( n11972 , n11971 , n11969 );
and ( n11973 , n11972 , n6474 );
or ( n11974 , n11970 , n11973 );
xor ( n11975 , n11967 , n11974 );
buf ( n11976 , n5981 );
xor ( n11977 , n11975 , n11976 );
buf ( n11978 , n5982 );
xor ( n11979 , n11977 , n11978 );
buf ( n11980 , n5983 );
xor ( n11981 , n11979 , n11980 );
xor ( n11982 , n11960 , n11981 );
and ( n11983 , n11952 , n11982 );
xor ( n11984 , n11928 , n11983 );
xor ( n11985 , n11910 , n11984 );
not ( n11986 , n6474 );
buf ( n11987 , n5984 );
and ( n11988 , n11986 , n11987 );
buf ( n11989 , n5985 );
xor ( n11990 , n11989 , n11987 );
and ( n11991 , n11990 , n6474 );
or ( n11992 , n11988 , n11991 );
xor ( n11993 , n7979 , n11992 );
buf ( n11994 , n5986 );
xor ( n11995 , n11993 , n11994 );
xor ( n11996 , n11995 , n10173 );
buf ( n11997 , n5987 );
xor ( n11998 , n11996 , n11997 );
xor ( n11999 , n11030 , n11998 );
xor ( n12000 , n11999 , n7521 );
xor ( n12001 , n11353 , n10044 );
xor ( n12002 , n12001 , n8891 );
not ( n12003 , n12002 );
not ( n12004 , n6474 );
buf ( n12005 , n5988 );
and ( n12006 , n12004 , n12005 );
buf ( n12007 , n5989 );
xor ( n12008 , n12007 , n12005 );
and ( n12009 , n12008 , n6474 );
or ( n12010 , n12006 , n12009 );
not ( n12011 , n6474 );
buf ( n12012 , n5990 );
and ( n12013 , n12011 , n12012 );
buf ( n12014 , n5991 );
xor ( n12015 , n12014 , n12012 );
and ( n12016 , n12015 , n6474 );
or ( n12017 , n12013 , n12016 );
xor ( n12018 , n12017 , n8807 );
buf ( n12019 , n5992 );
xor ( n12020 , n12018 , n12019 );
buf ( n12021 , n5993 );
xor ( n12022 , n12020 , n12021 );
buf ( n12023 , n5994 );
xor ( n12024 , n12022 , n12023 );
xor ( n12025 , n12010 , n12024 );
not ( n12026 , n6474 );
buf ( n12027 , n5995 );
and ( n12028 , n12026 , n12027 );
buf ( n12029 , n5996 );
xor ( n12030 , n12029 , n12027 );
and ( n12031 , n12030 , n6474 );
or ( n12032 , n12028 , n12031 );
buf ( n12033 , n5997 );
xor ( n12034 , n12032 , n12033 );
buf ( n12035 , n5998 );
xor ( n12036 , n12034 , n12035 );
buf ( n12037 , n5999 );
xor ( n12038 , n12036 , n12037 );
buf ( n12039 , n6000 );
xor ( n12040 , n12038 , n12039 );
xor ( n12041 , n12025 , n12040 );
and ( n12042 , n12003 , n12041 );
xor ( n12043 , n12000 , n12042 );
xor ( n12044 , n11985 , n12043 );
xor ( n12045 , n11720 , n12044 );
not ( n12046 , n6474 );
buf ( n12047 , n6001 );
and ( n12048 , n12046 , n12047 );
buf ( n12049 , n6002 );
xor ( n12050 , n12049 , n12047 );
and ( n12051 , n12050 , n6474 );
or ( n12052 , n12048 , n12051 );
not ( n12053 , n6474 );
buf ( n12054 , n6003 );
and ( n12055 , n12053 , n12054 );
buf ( n12056 , n6004 );
xor ( n12057 , n12056 , n12054 );
and ( n12058 , n12057 , n6474 );
or ( n12059 , n12055 , n12058 );
xor ( n12060 , n12052 , n12059 );
buf ( n12061 , n6005 );
xor ( n12062 , n12060 , n12061 );
buf ( n12063 , n6006 );
xor ( n12064 , n12062 , n12063 );
buf ( n12065 , n6007 );
xor ( n12066 , n12064 , n12065 );
xor ( n12067 , n10409 , n12066 );
xor ( n12068 , n12067 , n9895 );
buf ( n12069 , n6008 );
xor ( n12070 , n12069 , n8291 );
xor ( n12071 , n12070 , n9921 );
not ( n12072 , n12071 );
xor ( n12073 , n7858 , n11512 );
xor ( n12074 , n12073 , n11520 );
and ( n12075 , n12072 , n12074 );
xor ( n12076 , n12068 , n12075 );
not ( n12077 , n6474 );
buf ( n12078 , n6009 );
and ( n12079 , n12077 , n12078 );
buf ( n12080 , n6010 );
xor ( n12081 , n12080 , n12078 );
and ( n12082 , n12081 , n6474 );
or ( n12083 , n12079 , n12082 );
not ( n12084 , n6474 );
buf ( n12085 , n6011 );
and ( n12086 , n12084 , n12085 );
buf ( n12087 , n6012 );
xor ( n12088 , n12087 , n12085 );
and ( n12089 , n12088 , n6474 );
or ( n12090 , n12086 , n12089 );
xor ( n12091 , n12083 , n12090 );
buf ( n12092 , n6013 );
xor ( n12093 , n12091 , n12092 );
buf ( n12094 , n6014 );
xor ( n12095 , n12093 , n12094 );
buf ( n12096 , n6015 );
xor ( n12097 , n12095 , n12096 );
xor ( n12098 , n9141 , n12097 );
not ( n12099 , n6474 );
buf ( n12100 , n6016 );
and ( n12101 , n12099 , n12100 );
buf ( n12102 , n6017 );
xor ( n12103 , n12102 , n12100 );
and ( n12104 , n12103 , n6474 );
or ( n12105 , n12101 , n12104 );
xor ( n12106 , n12105 , n9592 );
buf ( n12107 , n6018 );
xor ( n12108 , n12106 , n12107 );
buf ( n12109 , n6019 );
xor ( n12110 , n12108 , n12109 );
xor ( n12111 , n12110 , n10937 );
xor ( n12112 , n12098 , n12111 );
xor ( n12113 , n8309 , n7537 );
xor ( n12114 , n12113 , n10905 );
not ( n12115 , n12114 );
xor ( n12116 , n8444 , n9942 );
xor ( n12117 , n12116 , n10193 );
and ( n12118 , n12115 , n12117 );
xor ( n12119 , n12112 , n12118 );
xor ( n12120 , n12076 , n12119 );
xor ( n12121 , n9332 , n6763 );
xor ( n12122 , n12121 , n6785 );
not ( n12123 , n6474 );
buf ( n12124 , n6020 );
and ( n12125 , n12123 , n12124 );
buf ( n12126 , n6021 );
xor ( n12127 , n12126 , n12124 );
and ( n12128 , n12127 , n6474 );
or ( n12129 , n12125 , n12128 );
not ( n12130 , n6474 );
buf ( n12131 , n6022 );
and ( n12132 , n12130 , n12131 );
buf ( n12133 , n6023 );
xor ( n12134 , n12133 , n12131 );
and ( n12135 , n12134 , n6474 );
or ( n12136 , n12132 , n12135 );
xor ( n12137 , n12129 , n12136 );
buf ( n12138 , n6024 );
xor ( n12139 , n12137 , n12138 );
buf ( n12140 , n6025 );
xor ( n12141 , n12139 , n12140 );
buf ( n12142 , n6026 );
xor ( n12143 , n12141 , n12142 );
xor ( n12144 , n7001 , n12143 );
xor ( n12145 , n12144 , n9710 );
not ( n12146 , n12145 );
buf ( n12147 , n6027 );
xor ( n12148 , n12147 , n7331 );
not ( n12149 , n6474 );
buf ( n12150 , n6028 );
and ( n12151 , n12149 , n12150 );
buf ( n12152 , n6029 );
xor ( n12153 , n12152 , n12150 );
and ( n12154 , n12153 , n6474 );
or ( n12155 , n12151 , n12154 );
xor ( n12156 , n6569 , n12155 );
buf ( n12157 , n6030 );
xor ( n12158 , n12156 , n12157 );
buf ( n12159 , n6031 );
xor ( n12160 , n12158 , n12159 );
buf ( n12161 , n6032 );
xor ( n12162 , n12160 , n12161 );
xor ( n12163 , n12148 , n12162 );
and ( n12164 , n12146 , n12163 );
xor ( n12165 , n12122 , n12164 );
xor ( n12166 , n12120 , n12165 );
xor ( n12167 , n11651 , n11405 );
xor ( n12168 , n12167 , n11427 );
xor ( n12169 , n6601 , n8076 );
not ( n12170 , n6474 );
buf ( n12171 , n6033 );
and ( n12172 , n12170 , n12171 );
buf ( n12173 , n6034 );
xor ( n12174 , n12173 , n12171 );
and ( n12175 , n12174 , n6474 );
or ( n12176 , n12172 , n12175 );
not ( n12177 , n6474 );
buf ( n12178 , n6035 );
and ( n12179 , n12177 , n12178 );
buf ( n12180 , n6036 );
xor ( n12181 , n12180 , n12178 );
and ( n12182 , n12181 , n6474 );
or ( n12183 , n12179 , n12182 );
xor ( n12184 , n12176 , n12183 );
buf ( n12185 , n6037 );
xor ( n12186 , n12184 , n12185 );
buf ( n12187 , n6038 );
xor ( n12188 , n12186 , n12187 );
buf ( n12189 , n6039 );
xor ( n12190 , n12188 , n12189 );
xor ( n12191 , n12169 , n12190 );
not ( n12192 , n12191 );
not ( n12193 , n6474 );
buf ( n12194 , n6040 );
and ( n12195 , n12193 , n12194 );
buf ( n12196 , n6041 );
xor ( n12197 , n12196 , n12194 );
and ( n12198 , n12197 , n6474 );
or ( n12199 , n12195 , n12198 );
not ( n12200 , n6474 );
buf ( n12201 , n6042 );
and ( n12202 , n12200 , n12201 );
buf ( n12203 , n6043 );
xor ( n12204 , n12203 , n12201 );
and ( n12205 , n12204 , n6474 );
or ( n12206 , n12202 , n12205 );
xor ( n12207 , n12199 , n12206 );
buf ( n12208 , n6044 );
xor ( n12209 , n12207 , n12208 );
buf ( n12210 , n6045 );
xor ( n12211 , n12209 , n12210 );
buf ( n12212 , n6046 );
xor ( n12213 , n12211 , n12212 );
xor ( n12214 , n10127 , n12213 );
xor ( n12215 , n12214 , n10768 );
and ( n12216 , n12192 , n12215 );
xor ( n12217 , n12168 , n12216 );
xor ( n12218 , n12166 , n12217 );
xor ( n12219 , n8835 , n6739 );
xor ( n12220 , n12219 , n11927 );
xor ( n12221 , n7371 , n10224 );
xor ( n12222 , n12221 , n10246 );
not ( n12223 , n12222 );
buf ( n12224 , n6047 );
xor ( n12225 , n12224 , n9094 );
not ( n12226 , n6474 );
buf ( n12227 , n6048 );
and ( n12228 , n12226 , n12227 );
buf ( n12229 , n6049 );
xor ( n12230 , n12229 , n12227 );
and ( n12231 , n12230 , n6474 );
or ( n12232 , n12228 , n12231 );
not ( n12233 , n6474 );
buf ( n12234 , n6050 );
and ( n12235 , n12233 , n12234 );
buf ( n12236 , n6051 );
xor ( n12237 , n12236 , n12234 );
and ( n12238 , n12237 , n6474 );
or ( n12239 , n12235 , n12238 );
xor ( n12240 , n12232 , n12239 );
buf ( n12241 , n6052 );
xor ( n12242 , n12240 , n12241 );
buf ( n12243 , n6053 );
xor ( n12244 , n12242 , n12243 );
buf ( n12245 , n6054 );
xor ( n12246 , n12244 , n12245 );
xor ( n12247 , n12225 , n12246 );
and ( n12248 , n12223 , n12247 );
xor ( n12249 , n12220 , n12248 );
xor ( n12250 , n12218 , n12249 );
xor ( n12251 , n12045 , n12250 );
not ( n12252 , n6474 );
buf ( n12253 , n6055 );
and ( n12254 , n12252 , n12253 );
buf ( n12255 , n6056 );
xor ( n12256 , n12255 , n12253 );
and ( n12257 , n12256 , n6474 );
or ( n12258 , n12254 , n12257 );
xor ( n12259 , n12258 , n9002 );
xor ( n12260 , n12259 , n11329 );
not ( n12261 , n6474 );
buf ( n12262 , n6057 );
and ( n12263 , n12261 , n12262 );
buf ( n12264 , n6058 );
xor ( n12265 , n12264 , n12262 );
and ( n12266 , n12265 , n6474 );
or ( n12267 , n12263 , n12266 );
not ( n12268 , n6474 );
buf ( n12269 , n6059 );
and ( n12270 , n12268 , n12269 );
buf ( n12271 , n6060 );
xor ( n12272 , n12271 , n12269 );
and ( n12273 , n12272 , n6474 );
or ( n12274 , n12270 , n12273 );
xor ( n12275 , n12267 , n12274 );
buf ( n12276 , n6061 );
xor ( n12277 , n12275 , n12276 );
buf ( n12278 , n6062 );
xor ( n12279 , n12277 , n12278 );
buf ( n12280 , n6063 );
xor ( n12281 , n12279 , n12280 );
xor ( n12282 , n7129 , n12281 );
not ( n12283 , n6474 );
buf ( n12284 , n6064 );
and ( n12285 , n12283 , n12284 );
buf ( n12286 , n6065 );
xor ( n12287 , n12286 , n12284 );
and ( n12288 , n12287 , n6474 );
or ( n12289 , n12285 , n12288 );
not ( n12290 , n6474 );
buf ( n12291 , n6066 );
and ( n12292 , n12290 , n12291 );
buf ( n12293 , n6067 );
xor ( n12294 , n12293 , n12291 );
and ( n12295 , n12294 , n6474 );
or ( n12296 , n12292 , n12295 );
xor ( n12297 , n12289 , n12296 );
xor ( n12298 , n12297 , n6610 );
buf ( n12299 , n6068 );
xor ( n12300 , n12298 , n12299 );
buf ( n12301 , n6069 );
xor ( n12302 , n12300 , n12301 );
xor ( n12303 , n12282 , n12302 );
not ( n12304 , n12303 );
buf ( n12305 , n6070 );
xor ( n12306 , n12305 , n11275 );
xor ( n12307 , n12306 , n9559 );
and ( n12308 , n12304 , n12307 );
xor ( n12309 , n12260 , n12308 );
not ( n12310 , n6474 );
buf ( n12311 , n6071 );
and ( n12312 , n12310 , n12311 );
buf ( n12313 , n6072 );
xor ( n12314 , n12313 , n12311 );
and ( n12315 , n12314 , n6474 );
or ( n12316 , n12312 , n12315 );
xor ( n12317 , n12316 , n9094 );
xor ( n12318 , n12317 , n12246 );
xor ( n12319 , n9163 , n12111 );
xor ( n12320 , n12319 , n7910 );
not ( n12321 , n12320 );
xor ( n12322 , n6956 , n8114 );
xor ( n12323 , n12322 , n7861 );
and ( n12324 , n12321 , n12323 );
xor ( n12325 , n12318 , n12324 );
xor ( n12326 , n9364 , n9872 );
not ( n12327 , n6474 );
buf ( n12328 , n6073 );
and ( n12329 , n12327 , n12328 );
buf ( n12330 , n6074 );
xor ( n12331 , n12330 , n12328 );
and ( n12332 , n12331 , n6474 );
or ( n12333 , n12329 , n12332 );
buf ( n12334 , n6075 );
xor ( n12335 , n12333 , n12334 );
buf ( n12336 , n6076 );
xor ( n12337 , n12335 , n12336 );
buf ( n12338 , n6077 );
xor ( n12339 , n12337 , n12338 );
buf ( n12340 , n6078 );
xor ( n12341 , n12339 , n12340 );
xor ( n12342 , n12326 , n12341 );
buf ( n12343 , n6079 );
xor ( n12344 , n12343 , n11833 );
not ( n12345 , n6474 );
buf ( n12346 , n6080 );
and ( n12347 , n12345 , n12346 );
buf ( n12348 , n6081 );
xor ( n12349 , n12348 , n12346 );
and ( n12350 , n12349 , n6474 );
or ( n12351 , n12347 , n12350 );
not ( n12352 , n6474 );
buf ( n12353 , n6082 );
and ( n12354 , n12352 , n12353 );
buf ( n12355 , n6083 );
xor ( n12356 , n12355 , n12353 );
and ( n12357 , n12356 , n6474 );
or ( n12358 , n12354 , n12357 );
xor ( n12359 , n12351 , n12358 );
buf ( n12360 , n6084 );
xor ( n12361 , n12359 , n12360 );
buf ( n12362 , n6085 );
xor ( n12363 , n12361 , n12362 );
buf ( n12364 , n6086 );
xor ( n12365 , n12363 , n12364 );
xor ( n12366 , n12344 , n12365 );
not ( n12367 , n12366 );
not ( n12368 , n6474 );
buf ( n12369 , n6087 );
and ( n12370 , n12368 , n12369 );
buf ( n12371 , n6088 );
xor ( n12372 , n12371 , n12369 );
and ( n12373 , n12372 , n6474 );
or ( n12374 , n12370 , n12373 );
xor ( n12375 , n12374 , n9900 );
buf ( n12376 , n6089 );
xor ( n12377 , n12375 , n12376 );
buf ( n12378 , n6090 );
xor ( n12379 , n12377 , n12378 );
buf ( n12380 , n6091 );
xor ( n12381 , n12379 , n12380 );
xor ( n12382 , n12061 , n12381 );
xor ( n12383 , n12382 , n8447 );
and ( n12384 , n12367 , n12383 );
xor ( n12385 , n12342 , n12384 );
xor ( n12386 , n12325 , n12385 );
xor ( n12387 , n12232 , n8764 );
not ( n12388 , n6474 );
buf ( n12389 , n6092 );
and ( n12390 , n12388 , n12389 );
buf ( n12391 , n6093 );
xor ( n12392 , n12391 , n12389 );
and ( n12393 , n12392 , n6474 );
or ( n12394 , n12390 , n12393 );
not ( n12395 , n6474 );
buf ( n12396 , n6094 );
and ( n12397 , n12395 , n12396 );
buf ( n12398 , n6095 );
xor ( n12399 , n12398 , n12396 );
and ( n12400 , n12399 , n6474 );
or ( n12401 , n12397 , n12400 );
xor ( n12402 , n12394 , n12401 );
xor ( n12403 , n12402 , n12069 );
buf ( n12404 , n6096 );
xor ( n12405 , n12403 , n12404 );
buf ( n12406 , n6097 );
xor ( n12407 , n12405 , n12406 );
xor ( n12408 , n12387 , n12407 );
xor ( n12409 , n8049 , n7634 );
xor ( n12410 , n12409 , n7072 );
not ( n12411 , n12410 );
xor ( n12412 , n11048 , n7521 );
xor ( n12413 , n12412 , n7537 );
and ( n12414 , n12411 , n12413 );
xor ( n12415 , n12408 , n12414 );
xor ( n12416 , n12386 , n12415 );
not ( n12417 , n6474 );
buf ( n12418 , n6098 );
and ( n12419 , n12417 , n12418 );
buf ( n12420 , n6099 );
xor ( n12421 , n12420 , n12418 );
and ( n12422 , n12421 , n6474 );
or ( n12423 , n12419 , n12422 );
xor ( n12424 , n12423 , n9026 );
xor ( n12425 , n12424 , n9047 );
not ( n12426 , n12260 );
and ( n12427 , n12426 , n12303 );
xor ( n12428 , n12425 , n12427 );
xor ( n12429 , n12416 , n12428 );
xor ( n12430 , n9276 , n8660 );
xor ( n12431 , n12430 , n10105 );
not ( n12432 , n6474 );
buf ( n12433 , n6100 );
and ( n12434 , n12432 , n12433 );
buf ( n12435 , n6101 );
xor ( n12436 , n12435 , n12433 );
and ( n12437 , n12436 , n6474 );
or ( n12438 , n12434 , n12437 );
not ( n12439 , n6474 );
buf ( n12440 , n6102 );
and ( n12441 , n12439 , n12440 );
buf ( n12442 , n6103 );
xor ( n12443 , n12442 , n12440 );
and ( n12444 , n12443 , n6474 );
or ( n12445 , n12441 , n12444 );
xor ( n12446 , n12438 , n12445 );
buf ( n12447 , n6104 );
xor ( n12448 , n12446 , n12447 );
buf ( n12449 , n6105 );
xor ( n12450 , n12448 , n12449 );
buf ( n12451 , n6106 );
xor ( n12452 , n12450 , n12451 );
xor ( n12453 , n9787 , n12452 );
not ( n12454 , n6474 );
buf ( n12455 , n6107 );
and ( n12456 , n12454 , n12455 );
buf ( n12457 , n6108 );
xor ( n12458 , n12457 , n12455 );
and ( n12459 , n12458 , n6474 );
or ( n12460 , n12456 , n12459 );
buf ( n12461 , n6109 );
xor ( n12462 , n12460 , n12461 );
buf ( n12463 , n6110 );
xor ( n12464 , n12462 , n12463 );
xor ( n12465 , n12464 , n10355 );
buf ( n12466 , n6111 );
xor ( n12467 , n12465 , n12466 );
xor ( n12468 , n12453 , n12467 );
not ( n12469 , n12468 );
xor ( n12470 , n10141 , n10768 );
xor ( n12471 , n12470 , n10790 );
and ( n12472 , n12469 , n12471 );
xor ( n12473 , n12431 , n12472 );
xor ( n12474 , n12429 , n12473 );
xor ( n12475 , n12309 , n12474 );
xor ( n12476 , n11507 , n9170 );
xor ( n12477 , n12476 , n8495 );
not ( n12478 , n6474 );
buf ( n12479 , n6112 );
and ( n12480 , n12478 , n12479 );
buf ( n12481 , n6113 );
xor ( n12482 , n12481 , n12479 );
and ( n12483 , n12482 , n6474 );
or ( n12484 , n12480 , n12483 );
xor ( n12485 , n8345 , n12484 );
buf ( n12486 , n6114 );
xor ( n12487 , n12485 , n12486 );
buf ( n12488 , n6115 );
xor ( n12489 , n12487 , n12488 );
xor ( n12490 , n12489 , n10839 );
xor ( n12491 , n7790 , n12490 );
not ( n12492 , n6474 );
buf ( n12493 , n6116 );
and ( n12494 , n12492 , n12493 );
buf ( n12495 , n6117 );
xor ( n12496 , n12495 , n12493 );
and ( n12497 , n12496 , n6474 );
or ( n12498 , n12494 , n12497 );
buf ( n12499 , n6118 );
xor ( n12500 , n12498 , n12499 );
buf ( n12501 , n6119 );
xor ( n12502 , n12500 , n12501 );
buf ( n12503 , n6120 );
xor ( n12504 , n12502 , n12503 );
buf ( n12505 , n6121 );
xor ( n12506 , n12504 , n12505 );
xor ( n12507 , n12491 , n12506 );
not ( n12508 , n12507 );
xor ( n12509 , n11926 , n9511 );
not ( n12510 , n6474 );
buf ( n12511 , n6122 );
and ( n12512 , n12510 , n12511 );
buf ( n12513 , n6123 );
xor ( n12514 , n12513 , n12511 );
and ( n12515 , n12514 , n6474 );
or ( n12516 , n12512 , n12515 );
not ( n12517 , n6474 );
buf ( n12518 , n6124 );
and ( n12519 , n12517 , n12518 );
buf ( n12520 , n6125 );
xor ( n12521 , n12520 , n12518 );
and ( n12522 , n12521 , n6474 );
or ( n12523 , n12519 , n12522 );
xor ( n12524 , n12516 , n12523 );
buf ( n12525 , n6126 );
xor ( n12526 , n12524 , n12525 );
buf ( n12527 , n6127 );
xor ( n12528 , n12526 , n12527 );
buf ( n12529 , n6128 );
xor ( n12530 , n12528 , n12529 );
xor ( n12531 , n12509 , n12530 );
and ( n12532 , n12508 , n12531 );
xor ( n12533 , n12477 , n12532 );
not ( n12534 , n6474 );
buf ( n12535 , n6129 );
and ( n12536 , n12534 , n12535 );
buf ( n12537 , n6130 );
xor ( n12538 , n12537 , n12535 );
and ( n12539 , n12538 , n6474 );
or ( n12540 , n12536 , n12539 );
buf ( n12541 , n6131 );
xor ( n12542 , n12540 , n12541 );
buf ( n12543 , n6132 );
xor ( n12544 , n12542 , n12543 );
buf ( n12545 , n6133 );
xor ( n12546 , n12544 , n12545 );
buf ( n12547 , n6134 );
xor ( n12548 , n12546 , n12547 );
xor ( n12549 , n9937 , n12548 );
xor ( n12550 , n12549 , n9238 );
xor ( n12551 , n10622 , n8517 );
xor ( n12552 , n12551 , n11462 );
not ( n12553 , n12552 );
xor ( n12554 , n9289 , n8660 );
xor ( n12555 , n12554 , n10105 );
and ( n12556 , n12553 , n12555 );
xor ( n12557 , n12550 , n12556 );
xor ( n12558 , n12533 , n12557 );
xor ( n12559 , n11299 , n8159 );
xor ( n12560 , n12423 , n9005 );
buf ( n12561 , n6135 );
xor ( n12562 , n12560 , n12561 );
buf ( n12563 , n6136 );
xor ( n12564 , n12562 , n12563 );
buf ( n12565 , n6137 );
xor ( n12566 , n12564 , n12565 );
xor ( n12567 , n12559 , n12566 );
not ( n12568 , n6474 );
buf ( n12569 , n6138 );
and ( n12570 , n12568 , n12569 );
buf ( n12571 , n6139 );
xor ( n12572 , n12571 , n12569 );
and ( n12573 , n12572 , n6474 );
or ( n12574 , n12570 , n12573 );
xor ( n12575 , n12574 , n11155 );
buf ( n12576 , n6140 );
xor ( n12577 , n12575 , n12576 );
buf ( n12578 , n6141 );
xor ( n12579 , n12577 , n12578 );
buf ( n12580 , n6142 );
xor ( n12581 , n12579 , n12580 );
xor ( n12582 , n7109 , n12581 );
xor ( n12583 , n12582 , n12281 );
not ( n12584 , n12583 );
xor ( n12585 , n11344 , n10022 );
xor ( n12586 , n12585 , n10044 );
and ( n12587 , n12584 , n12586 );
xor ( n12588 , n12567 , n12587 );
xor ( n12589 , n12558 , n12588 );
not ( n12590 , n6474 );
buf ( n12591 , n6143 );
and ( n12592 , n12590 , n12591 );
buf ( n12593 , n6144 );
xor ( n12594 , n12593 , n12591 );
and ( n12595 , n12594 , n6474 );
or ( n12596 , n12592 , n12595 );
not ( n12597 , n6474 );
buf ( n12598 , n6145 );
and ( n12599 , n12597 , n12598 );
buf ( n12600 , n6146 );
xor ( n12601 , n12600 , n12598 );
and ( n12602 , n12601 , n6474 );
or ( n12603 , n12599 , n12602 );
xor ( n12604 , n12596 , n12603 );
xor ( n12605 , n12604 , n9402 );
buf ( n12606 , n6147 );
xor ( n12607 , n12605 , n12606 );
buf ( n12608 , n6148 );
xor ( n12609 , n12607 , n12608 );
xor ( n12610 , n6626 , n12609 );
xor ( n12611 , n12610 , n10334 );
xor ( n12612 , n8185 , n11132 );
xor ( n12613 , n12612 , n11146 );
not ( n12614 , n12613 );
buf ( n12615 , n6149 );
xor ( n12616 , n12615 , n6811 );
xor ( n12617 , n12616 , n6827 );
and ( n12618 , n12614 , n12617 );
xor ( n12619 , n12611 , n12618 );
xor ( n12620 , n12589 , n12619 );
xor ( n12621 , n11198 , n6850 );
xor ( n12622 , n12621 , n6872 );
xor ( n12623 , n6936 , n8092 );
xor ( n12624 , n12623 , n8114 );
not ( n12625 , n12624 );
xor ( n12626 , n10415 , n12066 );
xor ( n12627 , n12626 , n9895 );
and ( n12628 , n12625 , n12627 );
xor ( n12629 , n12622 , n12628 );
xor ( n12630 , n12620 , n12629 );
xor ( n12631 , n12475 , n12630 );
not ( n12632 , n12631 );
xor ( n12633 , n10925 , n9794 );
xor ( n12634 , n12633 , n9816 );
not ( n12635 , n6474 );
buf ( n12636 , n6150 );
and ( n12637 , n12635 , n12636 );
buf ( n12638 , n6151 );
xor ( n12639 , n12638 , n12636 );
and ( n12640 , n12639 , n6474 );
or ( n12641 , n12637 , n12640 );
buf ( n12642 , n6152 );
xor ( n12643 , n12641 , n12642 );
buf ( n12644 , n6153 );
xor ( n12645 , n12643 , n12644 );
buf ( n12646 , n6154 );
xor ( n12647 , n12645 , n12646 );
buf ( n12648 , n6155 );
xor ( n12649 , n12647 , n12648 );
xor ( n12650 , n10064 , n12649 );
not ( n12651 , n6474 );
buf ( n12652 , n6156 );
and ( n12653 , n12651 , n12652 );
buf ( n12654 , n6157 );
xor ( n12655 , n12654 , n12652 );
and ( n12656 , n12655 , n6474 );
or ( n12657 , n12653 , n12656 );
not ( n12658 , n6474 );
buf ( n12659 , n6158 );
and ( n12660 , n12658 , n12659 );
buf ( n12661 , n6159 );
xor ( n12662 , n12661 , n12659 );
and ( n12663 , n12662 , n6474 );
or ( n12664 , n12660 , n12663 );
xor ( n12665 , n12657 , n12664 );
buf ( n12666 , n6160 );
xor ( n12667 , n12665 , n12666 );
buf ( n12668 , n6161 );
xor ( n12669 , n12667 , n12668 );
buf ( n12670 , n6162 );
xor ( n12671 , n12669 , n12670 );
xor ( n12672 , n12650 , n12671 );
not ( n12673 , n12672 );
buf ( n12674 , n6163 );
xor ( n12675 , n12674 , n9651 );
xor ( n12676 , n12675 , n9673 );
and ( n12677 , n12673 , n12676 );
xor ( n12678 , n12634 , n12677 );
not ( n12679 , n6474 );
buf ( n12680 , n6164 );
and ( n12681 , n12679 , n12680 );
buf ( n12682 , n6165 );
xor ( n12683 , n12682 , n12680 );
and ( n12684 , n12683 , n6474 );
or ( n12685 , n12681 , n12684 );
not ( n12686 , n6474 );
buf ( n12687 , n6166 );
and ( n12688 , n12686 , n12687 );
buf ( n12689 , n6167 );
xor ( n12690 , n12689 , n12687 );
and ( n12691 , n12690 , n6474 );
or ( n12692 , n12688 , n12691 );
xor ( n12693 , n12685 , n12692 );
buf ( n12694 , n6168 );
xor ( n12695 , n12693 , n12694 );
buf ( n12696 , n6169 );
xor ( n12697 , n12695 , n12696 );
buf ( n12698 , n6170 );
xor ( n12699 , n12697 , n12698 );
xor ( n12700 , n11420 , n12699 );
xor ( n12701 , n12700 , n7360 );
buf ( n12702 , n6171 );
xor ( n12703 , n12702 , n11981 );
xor ( n12704 , n12703 , n7566 );
not ( n12705 , n12704 );
buf ( n12706 , n6172 );
not ( n12707 , n6474 );
buf ( n12708 , n6173 );
and ( n12709 , n12707 , n12708 );
buf ( n12710 , n6174 );
xor ( n12711 , n12710 , n12708 );
and ( n12712 , n12711 , n6474 );
or ( n12713 , n12709 , n12712 );
not ( n12714 , n6474 );
buf ( n12715 , n6175 );
and ( n12716 , n12714 , n12715 );
buf ( n12717 , n6176 );
xor ( n12718 , n12717 , n12715 );
and ( n12719 , n12718 , n6474 );
or ( n12720 , n12716 , n12719 );
xor ( n12721 , n12713 , n12720 );
buf ( n12722 , n6177 );
xor ( n12723 , n12721 , n12722 );
buf ( n12724 , n6178 );
xor ( n12725 , n12723 , n12724 );
buf ( n12726 , n6179 );
xor ( n12727 , n12725 , n12726 );
xor ( n12728 , n12706 , n12727 );
not ( n12729 , n6474 );
buf ( n12730 , n6180 );
and ( n12731 , n12729 , n12730 );
buf ( n12732 , n6181 );
xor ( n12733 , n12732 , n12730 );
and ( n12734 , n12733 , n6474 );
or ( n12735 , n12731 , n12734 );
buf ( n12736 , n6182 );
xor ( n12737 , n12735 , n12736 );
buf ( n12738 , n6183 );
xor ( n12739 , n12737 , n12738 );
buf ( n12740 , n6184 );
xor ( n12741 , n12739 , n12740 );
xor ( n12742 , n12741 , n7927 );
xor ( n12743 , n12728 , n12742 );
and ( n12744 , n12705 , n12743 );
xor ( n12745 , n12701 , n12744 );
xor ( n12746 , n8995 , n11741 );
xor ( n12747 , n12746 , n11763 );
xor ( n12748 , n11340 , n10022 );
xor ( n12749 , n12748 , n10044 );
not ( n12750 , n12749 );
buf ( n12751 , n6185 );
xor ( n12752 , n12751 , n7588 );
xor ( n12753 , n12752 , n9290 );
and ( n12754 , n12750 , n12753 );
xor ( n12755 , n12747 , n12754 );
xor ( n12756 , n12745 , n12755 );
xor ( n12757 , n12484 , n8366 );
xor ( n12758 , n12757 , n8388 );
not ( n12759 , n6474 );
buf ( n12760 , n6186 );
and ( n12761 , n12759 , n12760 );
buf ( n12762 , n6187 );
xor ( n12763 , n12762 , n12760 );
and ( n12764 , n12763 , n6474 );
or ( n12765 , n12761 , n12764 );
not ( n12766 , n6474 );
buf ( n12767 , n6188 );
and ( n12768 , n12766 , n12767 );
buf ( n12769 , n6189 );
xor ( n12770 , n12769 , n12767 );
and ( n12771 , n12770 , n6474 );
or ( n12772 , n12768 , n12771 );
xor ( n12773 , n12765 , n12772 );
buf ( n12774 , n6190 );
xor ( n12775 , n12773 , n12774 );
buf ( n12776 , n6191 );
xor ( n12777 , n12775 , n12776 );
buf ( n12778 , n6192 );
xor ( n12779 , n12777 , n12778 );
xor ( n12780 , n10669 , n12779 );
xor ( n12781 , n12780 , n8092 );
not ( n12782 , n12781 );
xor ( n12783 , n7991 , n8710 );
xor ( n12784 , n12783 , n8137 );
and ( n12785 , n12782 , n12784 );
xor ( n12786 , n12758 , n12785 );
xor ( n12787 , n12756 , n12786 );
buf ( n12788 , n6193 );
xor ( n12789 , n8586 , n12788 );
buf ( n12790 , n6194 );
xor ( n12791 , n12789 , n12790 );
buf ( n12792 , n6195 );
xor ( n12793 , n12791 , n12792 );
buf ( n12794 , n6196 );
xor ( n12795 , n12793 , n12794 );
xor ( n12796 , n8242 , n12795 );
xor ( n12797 , n12796 , n9973 );
xor ( n12798 , n8410 , n8314 );
xor ( n12799 , n12798 , n8336 );
not ( n12800 , n12799 );
buf ( n12801 , n6197 );
xor ( n12802 , n12801 , n7710 );
xor ( n12803 , n12802 , n7732 );
and ( n12804 , n12800 , n12803 );
xor ( n12805 , n12797 , n12804 );
xor ( n12806 , n12787 , n12805 );
xor ( n12807 , n7065 , n10836 );
not ( n12808 , n6474 );
buf ( n12809 , n6198 );
and ( n12810 , n12808 , n12809 );
buf ( n12811 , n6199 );
xor ( n12812 , n12811 , n12809 );
and ( n12813 , n12812 , n6474 );
or ( n12814 , n12810 , n12813 );
buf ( n12815 , n6200 );
xor ( n12816 , n12814 , n12815 );
buf ( n12817 , n6201 );
xor ( n12818 , n12816 , n12817 );
buf ( n12819 , n6202 );
xor ( n12820 , n12818 , n12819 );
buf ( n12821 , n6203 );
xor ( n12822 , n12820 , n12821 );
xor ( n12823 , n12807 , n12822 );
not ( n12824 , n12634 );
and ( n12825 , n12824 , n12672 );
xor ( n12826 , n12823 , n12825 );
xor ( n12827 , n12806 , n12826 );
xor ( n12828 , n12678 , n12827 );
xor ( n12829 , n7945 , n10130 );
xor ( n12830 , n12829 , n10146 );
buf ( n12831 , n6204 );
xor ( n12832 , n12831 , n7331 );
xor ( n12833 , n12832 , n12162 );
not ( n12834 , n12833 );
xor ( n12835 , n9567 , n8204 );
not ( n12836 , n6474 );
buf ( n12837 , n6205 );
and ( n12838 , n12836 , n12837 );
buf ( n12839 , n6206 );
xor ( n12840 , n12839 , n12837 );
and ( n12841 , n12840 , n6474 );
or ( n12842 , n12838 , n12841 );
not ( n12843 , n6474 );
buf ( n12844 , n6207 );
and ( n12845 , n12843 , n12844 );
buf ( n12846 , n6208 );
xor ( n12847 , n12846 , n12844 );
and ( n12848 , n12847 , n6474 );
or ( n12849 , n12845 , n12848 );
xor ( n12850 , n12842 , n12849 );
xor ( n12851 , n12850 , n9630 );
buf ( n12852 , n6209 );
xor ( n12853 , n12851 , n12852 );
xor ( n12854 , n12853 , n12674 );
xor ( n12855 , n12835 , n12854 );
and ( n12856 , n12834 , n12855 );
xor ( n12857 , n12830 , n12856 );
not ( n12858 , n6474 );
buf ( n12859 , n6210 );
and ( n12860 , n12858 , n12859 );
buf ( n12861 , n6211 );
xor ( n12862 , n12861 , n12859 );
and ( n12863 , n12862 , n6474 );
or ( n12864 , n12860 , n12863 );
xor ( n12865 , n12864 , n11002 );
buf ( n12866 , n6212 );
xor ( n12867 , n12865 , n12866 );
buf ( n12868 , n6213 );
xor ( n12869 , n12867 , n12868 );
buf ( n12870 , n6214 );
xor ( n12871 , n12869 , n12870 );
xor ( n12872 , n8657 , n12871 );
xor ( n12873 , n12872 , n9079 );
xor ( n12874 , n6738 , n9489 );
xor ( n12875 , n12874 , n9511 );
not ( n12876 , n12875 );
xor ( n12877 , n8482 , n7910 );
xor ( n12878 , n12877 , n7925 );
and ( n12879 , n12876 , n12878 );
xor ( n12880 , n12873 , n12879 );
xor ( n12881 , n12857 , n12880 );
xor ( n12882 , n7043 , n11052 );
xor ( n12883 , n12882 , n8314 );
xor ( n12884 , n7658 , n6673 );
xor ( n12885 , n12884 , n6695 );
not ( n12886 , n12885 );
xor ( n12887 , n12842 , n9651 );
xor ( n12888 , n12887 , n9673 );
and ( n12889 , n12886 , n12888 );
xor ( n12890 , n12883 , n12889 );
xor ( n12891 , n12881 , n12890 );
xor ( n12892 , n8862 , n10963 );
xor ( n12893 , n12892 , n10864 );
xor ( n12894 , n12580 , n8799 );
xor ( n12895 , n12894 , n11171 );
not ( n12896 , n12895 );
xor ( n12897 , n9599 , n7861 );
xor ( n12898 , n12897 , n7883 );
and ( n12899 , n12896 , n12898 );
xor ( n12900 , n12893 , n12899 );
xor ( n12901 , n12891 , n12900 );
buf ( n12902 , n6215 );
xor ( n12903 , n12902 , n6827 );
xor ( n12904 , n12903 , n11981 );
xor ( n12905 , n11226 , n11345 );
xor ( n12906 , n12905 , n11367 );
not ( n12907 , n12906 );
not ( n12908 , n6474 );
buf ( n12909 , n6216 );
and ( n12910 , n12908 , n12909 );
buf ( n12911 , n6217 );
xor ( n12912 , n12911 , n12909 );
and ( n12913 , n12912 , n6474 );
or ( n12914 , n12910 , n12913 );
xor ( n12915 , n12914 , n11275 );
xor ( n12916 , n12915 , n9559 );
and ( n12917 , n12907 , n12916 );
xor ( n12918 , n12904 , n12917 );
xor ( n12919 , n12901 , n12918 );
xor ( n12920 , n12828 , n12919 );
and ( n12921 , n12632 , n12920 );
xor ( n12922 , n12251 , n12921 );
and ( n12923 , n12922 , n6475 );
or ( n12924 , n11672 , n12923 );
and ( n12925 , n11670 , n12924 );
buf ( n12926 , n12925 );
buf ( n12927 , n12926 );
not ( n12928 , n6469 );
not ( n12929 , n6475 );
and ( n12930 , n12929 , n10437 );
not ( n12931 , n9897 );
not ( n12932 , n6474 );
buf ( n12933 , n6218 );
and ( n12934 , n12932 , n12933 );
buf ( n12935 , n6219 );
xor ( n12936 , n12935 , n12933 );
and ( n12937 , n12936 , n6474 );
or ( n12938 , n12934 , n12937 );
xor ( n12939 , n7339 , n12938 );
buf ( n12940 , n6220 );
xor ( n12941 , n12939 , n12940 );
buf ( n12942 , n6221 );
xor ( n12943 , n12941 , n12942 );
buf ( n12944 , n6222 );
xor ( n12945 , n12943 , n12944 );
xor ( n12946 , n8637 , n12945 );
xor ( n12947 , n12946 , n12871 );
and ( n12948 , n12931 , n12947 );
xor ( n12949 , n9875 , n12948 );
xor ( n12950 , n12949 , n10178 );
xor ( n12951 , n12950 , n10630 );
xor ( n12952 , n7768 , n12365 );
xor ( n12953 , n12952 , n12490 );
xor ( n12954 , n12726 , n11329 );
xor ( n12955 , n12954 , n7948 );
not ( n12956 , n12955 );
not ( n12957 , n6474 );
buf ( n12958 , n6223 );
and ( n12959 , n12957 , n12958 );
buf ( n12960 , n6224 );
xor ( n12961 , n12960 , n12958 );
and ( n12962 , n12961 , n6474 );
or ( n12963 , n12959 , n12962 );
xor ( n12964 , n12963 , n9895 );
xor ( n12965 , n12964 , n7612 );
and ( n12966 , n12956 , n12965 );
xor ( n12967 , n12953 , n12966 );
xor ( n12968 , n9668 , n11227 );
xor ( n12969 , n12968 , n11833 );
xor ( n12970 , n12942 , n7360 );
xor ( n12971 , n12970 , n7376 );
not ( n12972 , n12971 );
xor ( n12973 , n6515 , n9995 );
not ( n12974 , n6474 );
buf ( n12975 , n6225 );
and ( n12976 , n12974 , n12975 );
buf ( n12977 , n6226 );
xor ( n12978 , n12977 , n12975 );
and ( n12979 , n12978 , n6474 );
or ( n12980 , n12976 , n12979 );
xor ( n12981 , n12980 , n11533 );
buf ( n12982 , n6227 );
xor ( n12983 , n12981 , n12982 );
buf ( n12984 , n6228 );
xor ( n12985 , n12983 , n12984 );
buf ( n12986 , n6229 );
xor ( n12987 , n12985 , n12986 );
xor ( n12988 , n12973 , n12987 );
and ( n12989 , n12972 , n12988 );
xor ( n12990 , n12969 , n12989 );
xor ( n12991 , n11875 , n9148 );
xor ( n12992 , n12991 , n9170 );
not ( n12993 , n12953 );
and ( n12994 , n12993 , n12955 );
xor ( n12995 , n12992 , n12994 );
xor ( n12996 , n12990 , n12995 );
buf ( n12997 , n6230 );
not ( n12998 , n6474 );
buf ( n12999 , n6231 );
and ( n13000 , n12998 , n12999 );
buf ( n13001 , n6232 );
xor ( n13002 , n13001 , n12999 );
and ( n13003 , n13002 , n6474 );
or ( n13004 , n13000 , n13003 );
not ( n13005 , n6474 );
buf ( n13006 , n6233 );
and ( n13007 , n13005 , n13006 );
buf ( n13008 , n6234 );
xor ( n13009 , n13008 , n13006 );
and ( n13010 , n13009 , n6474 );
or ( n13011 , n13007 , n13010 );
xor ( n13012 , n13004 , n13011 );
buf ( n13013 , n6235 );
xor ( n13014 , n13012 , n13013 );
buf ( n13015 , n6236 );
xor ( n13016 , n13014 , n13015 );
buf ( n13017 , n6237 );
xor ( n13018 , n13016 , n13017 );
xor ( n13019 , n12997 , n13018 );
xor ( n13020 , n13019 , n10394 );
xor ( n13021 , n10260 , n7006 );
xor ( n13022 , n13021 , n10439 );
not ( n13023 , n13022 );
buf ( n13024 , n6238 );
xor ( n13025 , n13024 , n6827 );
xor ( n13026 , n13025 , n11981 );
and ( n13027 , n13023 , n13026 );
xor ( n13028 , n13020 , n13027 );
xor ( n13029 , n12996 , n13028 );
xor ( n13030 , n9727 , n10574 );
xor ( n13031 , n13030 , n10595 );
not ( n13032 , n6474 );
buf ( n13033 , n6239 );
and ( n13034 , n13032 , n13033 );
buf ( n13035 , n6240 );
xor ( n13036 , n13035 , n13033 );
and ( n13037 , n13036 , n6474 );
or ( n13038 , n13034 , n13037 );
not ( n13039 , n6474 );
buf ( n13040 , n6241 );
and ( n13041 , n13039 , n13040 );
buf ( n13042 , n6242 );
xor ( n13043 , n13042 , n13040 );
and ( n13044 , n13043 , n6474 );
or ( n13045 , n13041 , n13044 );
xor ( n13046 , n13038 , n13045 );
buf ( n13047 , n6243 );
xor ( n13048 , n13046 , n13047 );
buf ( n13049 , n6244 );
xor ( n13050 , n13048 , n13049 );
buf ( n13051 , n6245 );
xor ( n13052 , n13050 , n13051 );
xor ( n13053 , n12449 , n13052 );
xor ( n13054 , n13053 , n10376 );
not ( n13055 , n13054 );
xor ( n13056 , n7731 , n8865 );
xor ( n13057 , n13056 , n7253 );
and ( n13058 , n13055 , n13057 );
xor ( n13059 , n13031 , n13058 );
xor ( n13060 , n13029 , n13059 );
xor ( n13061 , n11922 , n9511 );
xor ( n13062 , n13061 , n12530 );
xor ( n13063 , n9578 , n8204 );
xor ( n13064 , n13063 , n12854 );
not ( n13065 , n13064 );
buf ( n13066 , n6246 );
xor ( n13067 , n13066 , n6939 );
xor ( n13068 , n13067 , n6961 );
and ( n13069 , n13065 , n13068 );
xor ( n13070 , n13062 , n13069 );
xor ( n13071 , n13060 , n13070 );
xor ( n13072 , n12967 , n13071 );
xor ( n13073 , n10928 , n9794 );
xor ( n13074 , n13073 , n9816 );
xor ( n13075 , n6858 , n10504 );
not ( n13076 , n6474 );
buf ( n13077 , n6247 );
and ( n13078 , n13076 , n13077 );
buf ( n13079 , n6248 );
xor ( n13080 , n13079 , n13077 );
and ( n13081 , n13080 , n6474 );
or ( n13082 , n13078 , n13081 );
not ( n13083 , n6474 );
buf ( n13084 , n6249 );
and ( n13085 , n13083 , n13084 );
buf ( n13086 , n6250 );
xor ( n13087 , n13086 , n13084 );
and ( n13088 , n13087 , n6474 );
or ( n13089 , n13085 , n13088 );
xor ( n13090 , n13082 , n13089 );
xor ( n13091 , n13090 , n6918 );
buf ( n13092 , n6251 );
xor ( n13093 , n13091 , n13092 );
xor ( n13094 , n13093 , n13066 );
xor ( n13095 , n13075 , n13094 );
not ( n13096 , n13095 );
xor ( n13097 , n7762 , n12365 );
xor ( n13098 , n13097 , n12490 );
and ( n13099 , n13096 , n13098 );
xor ( n13100 , n13074 , n13099 );
xor ( n13101 , n10129 , n12213 );
xor ( n13102 , n13101 , n10768 );
xor ( n13103 , n8455 , n10193 );
xor ( n13104 , n13103 , n10209 );
not ( n13105 , n13104 );
xor ( n13106 , n8631 , n12945 );
xor ( n13107 , n13106 , n12871 );
and ( n13108 , n13105 , n13107 );
xor ( n13109 , n13102 , n13108 );
xor ( n13110 , n13100 , n13109 );
xor ( n13111 , n11656 , n11405 );
xor ( n13112 , n13111 , n11427 );
xor ( n13113 , n13082 , n6939 );
xor ( n13114 , n13113 , n6961 );
not ( n13115 , n13114 );
xor ( n13116 , n11456 , n6984 );
xor ( n13117 , n13116 , n7006 );
and ( n13118 , n13115 , n13117 );
xor ( n13119 , n13112 , n13118 );
xor ( n13120 , n13110 , n13119 );
xor ( n13121 , n10863 , n9534 );
xor ( n13122 , n13121 , n9543 );
not ( n13123 , n6474 );
buf ( n13124 , n6252 );
and ( n13125 , n13123 , n13124 );
buf ( n13126 , n6253 );
xor ( n13127 , n13126 , n13124 );
and ( n13128 , n13127 , n6474 );
or ( n13129 , n13125 , n13128 );
xor ( n13130 , n12963 , n13129 );
buf ( n13131 , n6254 );
xor ( n13132 , n13130 , n13131 );
xor ( n13133 , n13132 , n9877 );
buf ( n13134 , n6255 );
xor ( n13135 , n13133 , n13134 );
xor ( n13136 , n12540 , n13135 );
xor ( n13137 , n13136 , n8034 );
not ( n13138 , n13137 );
xor ( n13139 , n6710 , n10350 );
xor ( n13140 , n13139 , n9489 );
and ( n13141 , n13138 , n13140 );
xor ( n13142 , n13122 , n13141 );
xor ( n13143 , n13120 , n13142 );
xor ( n13144 , n8113 , n11879 );
xor ( n13145 , n13144 , n11512 );
xor ( n13146 , n11181 , n7494 );
xor ( n13147 , n13146 , n6850 );
not ( n13148 , n13147 );
xor ( n13149 , n7725 , n8865 );
xor ( n13150 , n13149 , n7253 );
and ( n13151 , n13148 , n13150 );
xor ( n13152 , n13145 , n13151 );
xor ( n13153 , n13143 , n13152 );
xor ( n13154 , n13072 , n13153 );
not ( n13155 , n13154 );
not ( n13156 , n8160 );
xor ( n13157 , n10303 , n7309 );
xor ( n13158 , n13157 , n7331 );
and ( n13159 , n13156 , n13158 );
xor ( n13160 , n8115 , n13159 );
xor ( n13161 , n13160 , n8392 );
xor ( n13162 , n13161 , n8768 );
and ( n13163 , n13155 , n13162 );
xor ( n13164 , n12951 , n13163 );
and ( n13165 , n13164 , n6475 );
or ( n13166 , n12930 , n13165 );
and ( n13167 , n12928 , n13166 );
buf ( n13168 , n13167 );
buf ( n13169 , n13168 );
not ( n13170 , n6469 );
not ( n13171 , n6475 );
and ( n13172 , n13171 , n9198 );
xor ( n13173 , n8837 , n6739 );
xor ( n13174 , n13173 , n11927 );
xor ( n13175 , n8635 , n12945 );
xor ( n13176 , n13175 , n12871 );
not ( n13177 , n13176 );
buf ( n13178 , n6256 );
xor ( n13179 , n13178 , n8935 );
xor ( n13180 , n13179 , n8950 );
and ( n13181 , n13177 , n13180 );
xor ( n13182 , n13174 , n13181 );
xor ( n13183 , n6599 , n8076 );
xor ( n13184 , n13183 , n12190 );
xor ( n13185 , n8860 , n10963 );
xor ( n13186 , n13185 , n10864 );
not ( n13187 , n13186 );
buf ( n13188 , n6257 );
xor ( n13189 , n13188 , n9217 );
xor ( n13190 , n13189 , n9417 );
and ( n13191 , n13187 , n13190 );
xor ( n13192 , n13184 , n13191 );
xor ( n13193 , n7105 , n12581 );
xor ( n13194 , n13193 , n12281 );
xor ( n13195 , n9811 , n12467 );
not ( n13196 , n6474 );
buf ( n13197 , n6258 );
and ( n13198 , n13196 , n13197 );
buf ( n13199 , n6259 );
xor ( n13200 , n13199 , n13197 );
and ( n13201 , n13200 , n6474 );
or ( n13202 , n13198 , n13201 );
not ( n13203 , n6474 );
buf ( n13204 , n6260 );
and ( n13205 , n13203 , n13204 );
buf ( n13206 , n6261 );
xor ( n13207 , n13206 , n13204 );
and ( n13208 , n13207 , n6474 );
or ( n13209 , n13205 , n13208 );
xor ( n13210 , n13202 , n13209 );
xor ( n13211 , n13210 , n10046 );
buf ( n13212 , n6262 );
xor ( n13213 , n13211 , n13212 );
buf ( n13214 , n6263 );
xor ( n13215 , n13213 , n13214 );
xor ( n13216 , n13195 , n13215 );
not ( n13217 , n13216 );
xor ( n13218 , n7272 , n7159 );
xor ( n13219 , n13218 , n7181 );
and ( n13220 , n13217 , n13219 );
xor ( n13221 , n13194 , n13220 );
xor ( n13222 , n13192 , n13221 );
not ( n13223 , n6474 );
buf ( n13224 , n6264 );
and ( n13225 , n13223 , n13224 );
buf ( n13226 , n6265 );
xor ( n13227 , n13226 , n13224 );
and ( n13228 , n13227 , n6474 );
or ( n13229 , n13225 , n13228 );
xor ( n13230 , n13229 , n11981 );
xor ( n13231 , n13230 , n7566 );
not ( n13232 , n13174 );
and ( n13233 , n13232 , n13176 );
xor ( n13234 , n13231 , n13233 );
xor ( n13235 , n13222 , n13234 );
xor ( n13236 , n8130 , n7046 );
xor ( n13237 , n13236 , n8414 );
xor ( n13238 , n10460 , n10246 );
xor ( n13239 , n13238 , n11252 );
not ( n13240 , n13239 );
xor ( n13241 , n9893 , n8447 );
xor ( n13242 , n13241 , n8469 );
and ( n13243 , n13240 , n13242 );
xor ( n13244 , n13237 , n13243 );
xor ( n13245 , n13235 , n13244 );
xor ( n13246 , n7854 , n11512 );
xor ( n13247 , n13246 , n11520 );
xor ( n13248 , n8530 , n9378 );
xor ( n13249 , n13248 , n9400 );
not ( n13250 , n13249 );
buf ( n13251 , n6266 );
xor ( n13252 , n13251 , n9354 );
xor ( n13253 , n13252 , n7710 );
and ( n13254 , n13250 , n13253 );
xor ( n13255 , n13247 , n13254 );
xor ( n13256 , n13245 , n13255 );
xor ( n13257 , n13182 , n13256 );
xor ( n13258 , n10524 , n12302 );
not ( n13259 , n6474 );
buf ( n13260 , n6267 );
and ( n13261 , n13259 , n13260 );
buf ( n13262 , n6268 );
xor ( n13263 , n13262 , n13260 );
and ( n13264 , n13263 , n6474 );
or ( n13265 , n13261 , n13264 );
buf ( n13266 , n6269 );
xor ( n13267 , n13265 , n13266 );
buf ( n13268 , n6270 );
xor ( n13269 , n13267 , n13268 );
buf ( n13270 , n6271 );
xor ( n13271 , n13269 , n13270 );
buf ( n13272 , n6272 );
xor ( n13273 , n13271 , n13272 );
xor ( n13274 , n13258 , n13273 );
xor ( n13275 , n12547 , n13135 );
xor ( n13276 , n13275 , n8034 );
not ( n13277 , n13276 );
xor ( n13278 , n7407 , n6516 );
xor ( n13279 , n13278 , n13052 );
and ( n13280 , n13277 , n13279 );
xor ( n13281 , n13274 , n13280 );
buf ( n13282 , n6273 );
xor ( n13283 , n13282 , n7659 );
xor ( n13284 , n13283 , n7681 );
xor ( n13285 , n10594 , n6913 );
xor ( n13286 , n13285 , n8600 );
not ( n13287 , n13286 );
xor ( n13288 , n11591 , n10990 );
xor ( n13289 , n13288 , n10022 );
and ( n13290 , n13287 , n13289 );
xor ( n13291 , n13284 , n13290 );
xor ( n13292 , n13281 , n13291 );
xor ( n13293 , n7373 , n10224 );
xor ( n13294 , n13293 , n10246 );
xor ( n13295 , n7094 , n12822 );
not ( n13296 , n6474 );
buf ( n13297 , n6274 );
and ( n13298 , n13296 , n13297 );
buf ( n13299 , n6275 );
xor ( n13300 , n13299 , n13297 );
and ( n13301 , n13300 , n6474 );
or ( n13302 , n13298 , n13301 );
not ( n13303 , n6474 );
buf ( n13304 , n6276 );
and ( n13305 , n13303 , n13304 );
buf ( n13306 , n6277 );
xor ( n13307 , n13306 , n13304 );
and ( n13308 , n13307 , n6474 );
or ( n13309 , n13305 , n13308 );
xor ( n13310 , n13302 , n13309 );
buf ( n13311 , n6278 );
xor ( n13312 , n13310 , n13311 );
buf ( n13313 , n6279 );
xor ( n13314 , n13312 , n13313 );
xor ( n13315 , n13314 , n9175 );
xor ( n13316 , n13295 , n13315 );
not ( n13317 , n13316 );
xor ( n13318 , n13038 , n12987 );
not ( n13319 , n6474 );
buf ( n13320 , n6280 );
and ( n13321 , n13319 , n13320 );
buf ( n13322 , n6281 );
xor ( n13323 , n13322 , n13320 );
and ( n13324 , n13323 , n6474 );
or ( n13325 , n13321 , n13324 );
not ( n13326 , n6474 );
buf ( n13327 , n6282 );
and ( n13328 , n13326 , n13327 );
buf ( n13329 , n6283 );
xor ( n13330 , n13329 , n13327 );
and ( n13331 , n13330 , n6474 );
or ( n13332 , n13328 , n13331 );
xor ( n13333 , n13325 , n13332 );
buf ( n13334 , n6284 );
xor ( n13335 , n13333 , n13334 );
buf ( n13336 , n6285 );
xor ( n13337 , n13335 , n13336 );
buf ( n13338 , n6286 );
xor ( n13339 , n13337 , n13338 );
xor ( n13340 , n13318 , n13339 );
and ( n13341 , n13317 , n13340 );
xor ( n13342 , n13294 , n13341 );
xor ( n13343 , n13292 , n13342 );
xor ( n13344 , n10190 , n9238 );
xor ( n13345 , n13344 , n9260 );
xor ( n13346 , n6537 , n10731 );
xor ( n13347 , n13346 , n10745 );
not ( n13348 , n13347 );
xor ( n13349 , n8196 , n11146 );
xor ( n13350 , n13349 , n9651 );
and ( n13351 , n13348 , n13350 );
xor ( n13352 , n13345 , n13351 );
xor ( n13353 , n13343 , n13352 );
buf ( n13354 , n6287 );
not ( n13355 , n6474 );
buf ( n13356 , n6288 );
and ( n13357 , n13355 , n13356 );
buf ( n13358 , n6289 );
xor ( n13359 , n13358 , n13356 );
and ( n13360 , n13359 , n6474 );
or ( n13361 , n13357 , n13360 );
buf ( n13362 , n6290 );
xor ( n13363 , n13361 , n13362 );
buf ( n13364 , n6291 );
xor ( n13365 , n13363 , n13364 );
xor ( n13366 , n13365 , n12147 );
xor ( n13367 , n13366 , n12831 );
xor ( n13368 , n13354 , n13367 );
xor ( n13369 , n13368 , n10963 );
xor ( n13370 , n11554 , n9816 );
xor ( n13371 , n13370 , n6811 );
not ( n13372 , n13371 );
xor ( n13373 , n7808 , n7463 );
xor ( n13374 , n13373 , n7399 );
and ( n13375 , n13372 , n13374 );
xor ( n13376 , n13369 , n13375 );
xor ( n13377 , n13353 , n13376 );
xor ( n13378 , n13257 , n13377 );
xor ( n13379 , n10728 , n10625 );
xor ( n13380 , n13379 , n7208 );
not ( n13381 , n6474 );
buf ( n13382 , n6292 );
and ( n13383 , n13381 , n13382 );
buf ( n13384 , n6293 );
xor ( n13385 , n13384 , n13382 );
and ( n13386 , n13385 , n6474 );
or ( n13387 , n13383 , n13386 );
xor ( n13388 , n8675 , n13387 );
buf ( n13389 , n6294 );
xor ( n13390 , n13388 , n13389 );
xor ( n13391 , n13390 , n9676 );
xor ( n13392 , n13391 , n10912 );
xor ( n13393 , n8387 , n13392 );
xor ( n13394 , n13393 , n7994 );
not ( n13395 , n13394 );
xor ( n13396 , n6819 , n11636 );
xor ( n13397 , n13396 , n11657 );
and ( n13398 , n13395 , n13397 );
xor ( n13399 , n13380 , n13398 );
xor ( n13400 , n9212 , n7134 );
xor ( n13401 , n13400 , n10527 );
xor ( n13402 , n8597 , n7822 );
xor ( n13403 , n13402 , n7837 );
not ( n13404 , n13403 );
xor ( n13405 , n11519 , n8495 );
xor ( n13406 , n13405 , n8517 );
and ( n13407 , n13404 , n13406 );
xor ( n13408 , n13401 , n13407 );
xor ( n13409 , n7153 , n9543 );
not ( n13410 , n6474 );
buf ( n13411 , n6295 );
and ( n13412 , n13410 , n13411 );
buf ( n13413 , n6296 );
xor ( n13414 , n13413 , n13411 );
and ( n13415 , n13414 , n6474 );
or ( n13416 , n13412 , n13415 );
not ( n13417 , n6474 );
buf ( n13418 , n6297 );
and ( n13419 , n13417 , n13418 );
buf ( n13420 , n6298 );
xor ( n13421 , n13420 , n13418 );
and ( n13422 , n13421 , n6474 );
or ( n13423 , n13419 , n13422 );
xor ( n13424 , n13416 , n13423 );
xor ( n13425 , n13424 , n8663 );
xor ( n13426 , n13425 , n13282 );
xor ( n13427 , n13426 , n7639 );
xor ( n13428 , n13409 , n13427 );
xor ( n13429 , n9436 , n10549 );
xor ( n13430 , n13429 , n12024 );
not ( n13431 , n13430 );
xor ( n13432 , n9871 , n11693 );
xor ( n13433 , n13432 , n11714 );
and ( n13434 , n13431 , n13433 );
xor ( n13435 , n13428 , n13434 );
xor ( n13436 , n13408 , n13435 );
xor ( n13437 , n10371 , n13339 );
xor ( n13438 , n13437 , n12649 );
xor ( n13439 , n10143 , n10768 );
xor ( n13440 , n13439 , n10790 );
not ( n13441 , n13440 );
xor ( n13442 , n10438 , n9710 );
xor ( n13443 , n13442 , n9732 );
and ( n13444 , n13441 , n13443 );
xor ( n13445 , n13438 , n13444 );
xor ( n13446 , n13436 , n13445 );
xor ( n13447 , n11900 , n6872 );
not ( n13448 , n6474 );
buf ( n13449 , n6299 );
and ( n13450 , n13448 , n13449 );
buf ( n13451 , n6300 );
xor ( n13452 , n13451 , n13449 );
and ( n13453 , n13452 , n6474 );
or ( n13454 , n13450 , n13453 );
not ( n13455 , n6474 );
buf ( n13456 , n6301 );
and ( n13457 , n13455 , n13456 );
buf ( n13458 , n6302 );
xor ( n13459 , n13458 , n13456 );
and ( n13460 , n13459 , n6474 );
or ( n13461 , n13457 , n13460 );
xor ( n13462 , n13454 , n13461 );
buf ( n13463 , n6303 );
xor ( n13464 , n13462 , n13463 );
buf ( n13465 , n6304 );
xor ( n13466 , n13464 , n13465 );
buf ( n13467 , n6305 );
xor ( n13468 , n13466 , n13467 );
xor ( n13469 , n13447 , n13468 );
not ( n13470 , n13380 );
and ( n13471 , n13470 , n13394 );
xor ( n13472 , n13469 , n13471 );
xor ( n13473 , n13446 , n13472 );
xor ( n13474 , n10204 , n9260 );
not ( n13475 , n6474 );
buf ( n13476 , n6306 );
and ( n13477 , n13475 , n13476 );
buf ( n13478 , n6307 );
xor ( n13479 , n13478 , n13476 );
and ( n13480 , n13479 , n6474 );
or ( n13481 , n13477 , n13480 );
xor ( n13482 , n8921 , n13481 );
buf ( n13483 , n6308 );
xor ( n13484 , n13482 , n13483 );
buf ( n13485 , n6309 );
xor ( n13486 , n13484 , n13485 );
xor ( n13487 , n13486 , n13178 );
xor ( n13488 , n13474 , n13487 );
xor ( n13489 , n7092 , n12822 );
xor ( n13490 , n13489 , n13315 );
not ( n13491 , n13490 );
xor ( n13492 , n6605 , n8076 );
xor ( n13493 , n13492 , n12190 );
and ( n13494 , n13491 , n13493 );
xor ( n13495 , n13488 , n13494 );
xor ( n13496 , n13473 , n13495 );
xor ( n13497 , n13399 , n13496 );
not ( n13498 , n6607 );
xor ( n13499 , n9432 , n10549 );
xor ( n13500 , n13499 , n12024 );
and ( n13501 , n13498 , n13500 );
xor ( n13502 , n6561 , n13501 );
not ( n13503 , n6474 );
buf ( n13504 , n6310 );
and ( n13505 , n13503 , n13504 );
buf ( n13506 , n6311 );
xor ( n13507 , n13506 , n13504 );
and ( n13508 , n13507 , n6474 );
or ( n13509 , n13505 , n13508 );
not ( n13510 , n6474 );
buf ( n13511 , n6312 );
and ( n13512 , n13510 , n13511 );
buf ( n13513 , n6313 );
xor ( n13514 , n13513 , n13511 );
and ( n13515 , n13514 , n6474 );
or ( n13516 , n13512 , n13515 );
xor ( n13517 , n13509 , n13516 );
buf ( n13518 , n6314 );
xor ( n13519 , n13517 , n13518 );
buf ( n13520 , n6315 );
xor ( n13521 , n13519 , n13520 );
buf ( n13522 , n6316 );
xor ( n13523 , n13521 , n13522 );
xor ( n13524 , n7552 , n13523 );
xor ( n13525 , n13524 , n8638 );
not ( n13526 , n13525 );
xor ( n13527 , n12788 , n8600 );
xor ( n13528 , n13527 , n8622 );
and ( n13529 , n13526 , n13528 );
xor ( n13530 , n6786 , n13529 );
xor ( n13531 , n13502 , n13530 );
xor ( n13532 , n6592 , n8076 );
xor ( n13533 , n13532 , n12190 );
not ( n13534 , n13533 );
xor ( n13535 , n10123 , n12213 );
xor ( n13536 , n13535 , n10768 );
and ( n13537 , n13534 , n13536 );
xor ( n13538 , n6914 , n13537 );
xor ( n13539 , n13531 , n13538 );
not ( n13540 , n6474 );
buf ( n13541 , n6317 );
and ( n13542 , n13540 , n13541 );
buf ( n13543 , n6318 );
xor ( n13544 , n13543 , n13541 );
and ( n13545 , n13544 , n6474 );
or ( n13546 , n13542 , n13545 );
not ( n13547 , n6474 );
buf ( n13548 , n6319 );
and ( n13549 , n13547 , n13548 );
buf ( n13550 , n6320 );
xor ( n13551 , n13550 , n13548 );
and ( n13552 , n13551 , n6474 );
or ( n13553 , n13549 , n13552 );
xor ( n13554 , n13546 , n13553 );
buf ( n13555 , n6321 );
xor ( n13556 , n13554 , n13555 );
buf ( n13557 , n6322 );
xor ( n13558 , n13556 , n13557 );
buf ( n13559 , n6323 );
xor ( n13560 , n13558 , n13559 );
xor ( n13561 , n11397 , n13560 );
xor ( n13562 , n13561 , n12699 );
not ( n13563 , n13562 );
xor ( n13564 , n9935 , n12548 );
xor ( n13565 , n13564 , n9238 );
and ( n13566 , n13563 , n13565 );
xor ( n13567 , n7047 , n13566 );
xor ( n13568 , n13539 , n13567 );
xor ( n13569 , n10296 , n7309 );
xor ( n13570 , n13569 , n7331 );
not ( n13571 , n13570 );
xor ( n13572 , n8381 , n13392 );
xor ( n13573 , n13572 , n7994 );
and ( n13574 , n13571 , n13573 );
xor ( n13575 , n7182 , n13574 );
xor ( n13576 , n13568 , n13575 );
xor ( n13577 , n13497 , n13576 );
not ( n13578 , n13577 );
not ( n13579 , n8389 );
not ( n13580 , n6474 );
buf ( n13581 , n6324 );
and ( n13582 , n13580 , n13581 );
buf ( n13583 , n6325 );
xor ( n13584 , n13583 , n13581 );
and ( n13585 , n13584 , n6474 );
or ( n13586 , n13582 , n13585 );
xor ( n13587 , n12914 , n13586 );
buf ( n13588 , n6326 );
xor ( n13589 , n13587 , n13588 );
xor ( n13590 , n13589 , n12305 );
xor ( n13591 , n13590 , n11254 );
xor ( n13592 , n9504 , n13591 );
not ( n13593 , n6474 );
buf ( n13594 , n6327 );
and ( n13595 , n13593 , n13594 );
buf ( n13596 , n6328 );
xor ( n13597 , n13596 , n13594 );
and ( n13598 , n13597 , n6474 );
or ( n13599 , n13595 , n13598 );
buf ( n13600 , n6329 );
xor ( n13601 , n13599 , n13600 );
buf ( n13602 , n6330 );
xor ( n13603 , n13601 , n13602 );
xor ( n13604 , n13603 , n9546 );
buf ( n13605 , n6331 );
xor ( n13606 , n13604 , n13605 );
xor ( n13607 , n13592 , n13606 );
and ( n13608 , n13579 , n13607 );
xor ( n13609 , n8337 , n13608 );
xor ( n13610 , n13609 , n8392 );
xor ( n13611 , n13610 , n8768 );
and ( n13612 , n13578 , n13611 );
xor ( n13613 , n13378 , n13612 );
and ( n13614 , n13613 , n6475 );
or ( n13615 , n13172 , n13614 );
and ( n13616 , n13170 , n13615 );
buf ( n13617 , n13616 );
buf ( n13618 , n13617 );
not ( n13619 , n6469 );
not ( n13620 , n6475 );
and ( n13621 , n13620 , n7091 );
xor ( n13622 , n9709 , n11949 );
xor ( n13623 , n13622 , n10574 );
xor ( n13624 , n7646 , n6673 );
xor ( n13625 , n13624 , n6695 );
not ( n13626 , n13625 );
not ( n13627 , n6474 );
buf ( n13628 , n6332 );
and ( n13629 , n13627 , n13628 );
buf ( n13630 , n6333 );
xor ( n13631 , n13630 , n13628 );
and ( n13632 , n13631 , n6474 );
or ( n13633 , n13629 , n13632 );
not ( n13634 , n6474 );
buf ( n13635 , n6334 );
and ( n13636 , n13634 , n13635 );
buf ( n13637 , n6335 );
xor ( n13638 , n13637 , n13635 );
and ( n13639 , n13638 , n6474 );
or ( n13640 , n13636 , n13639 );
xor ( n13641 , n13633 , n13640 );
buf ( n13642 , n6336 );
xor ( n13643 , n13641 , n13642 );
buf ( n13644 , n6337 );
xor ( n13645 , n13643 , n13644 );
buf ( n13646 , n6338 );
xor ( n13647 , n13645 , n13646 );
xor ( n13648 , n11268 , n13647 );
xor ( n13649 , n13648 , n8188 );
and ( n13650 , n13626 , n13649 );
xor ( n13651 , n13623 , n13650 );
xor ( n13652 , n10373 , n13339 );
xor ( n13653 , n13652 , n12649 );
not ( n13654 , n13623 );
and ( n13655 , n13654 , n13625 );
xor ( n13656 , n13653 , n13655 );
xor ( n13657 , n11129 , n12530 );
xor ( n13658 , n13657 , n10697 );
xor ( n13659 , n8864 , n10963 );
xor ( n13660 , n13659 , n10864 );
not ( n13661 , n13660 );
xor ( n13662 , n10099 , n9079 );
xor ( n13663 , n13662 , n9094 );
and ( n13664 , n13661 , n13663 );
xor ( n13665 , n13658 , n13664 );
xor ( n13666 , n13656 , n13665 );
xor ( n13667 , n9145 , n12097 );
xor ( n13668 , n13667 , n12111 );
xor ( n13669 , n8621 , n7837 );
not ( n13670 , n6474 );
buf ( n13671 , n6339 );
and ( n13672 , n13670 , n13671 );
buf ( n13673 , n6340 );
xor ( n13674 , n13673 , n13671 );
and ( n13675 , n13674 , n6474 );
or ( n13676 , n13672 , n13675 );
not ( n13677 , n6474 );
buf ( n13678 , n6341 );
and ( n13679 , n13677 , n13678 );
buf ( n13680 , n6342 );
xor ( n13681 , n13680 , n13678 );
and ( n13682 , n13681 , n6474 );
or ( n13683 , n13679 , n13682 );
xor ( n13684 , n13676 , n13683 );
buf ( n13685 , n6343 );
xor ( n13686 , n13684 , n13685 );
buf ( n13687 , n6344 );
xor ( n13688 , n13686 , n13687 );
buf ( n13689 , n6345 );
xor ( n13690 , n13688 , n13689 );
xor ( n13691 , n13669 , n13690 );
not ( n13692 , n13691 );
not ( n13693 , n6474 );
buf ( n13694 , n6346 );
and ( n13695 , n13693 , n13694 );
buf ( n13696 , n6347 );
xor ( n13697 , n13696 , n13694 );
and ( n13698 , n13697 , n6474 );
or ( n13699 , n13695 , n13698 );
xor ( n13700 , n13699 , n12258 );
buf ( n13701 , n6348 );
xor ( n13702 , n13700 , n13701 );
buf ( n13703 , n6349 );
xor ( n13704 , n13702 , n13703 );
xor ( n13705 , n13704 , n11307 );
xor ( n13706 , n6681 , n13705 );
xor ( n13707 , n13706 , n12727 );
and ( n13708 , n13692 , n13707 );
xor ( n13709 , n13668 , n13708 );
xor ( n13710 , n13666 , n13709 );
xor ( n13711 , n8571 , n9732 );
xor ( n13712 , n13711 , n8227 );
xor ( n13713 , n9025 , n8336 );
xor ( n13714 , n13713 , n8535 );
not ( n13715 , n13714 );
xor ( n13716 , n7368 , n10224 );
xor ( n13717 , n13716 , n10246 );
and ( n13718 , n13715 , n13717 );
xor ( n13719 , n13712 , n13718 );
xor ( n13720 , n13710 , n13719 );
xor ( n13721 , n10546 , n13273 );
xor ( n13722 , n13721 , n8820 );
xor ( n13723 , n11328 , n11763 );
xor ( n13724 , n13723 , n10130 );
not ( n13725 , n13724 );
xor ( n13726 , n9520 , n6606 );
xor ( n13727 , n13726 , n9123 );
and ( n13728 , n13725 , n13727 );
xor ( n13729 , n13722 , n13728 );
xor ( n13730 , n13720 , n13729 );
xor ( n13731 , n13651 , n13730 );
xor ( n13732 , n13699 , n9002 );
xor ( n13733 , n13732 , n11329 );
xor ( n13734 , n11125 , n12530 );
xor ( n13735 , n13734 , n10697 );
not ( n13736 , n13735 );
xor ( n13737 , n13588 , n11275 );
xor ( n13738 , n13737 , n9559 );
and ( n13739 , n13736 , n13738 );
xor ( n13740 , n13733 , n13739 );
xor ( n13741 , n8729 , n11252 );
xor ( n13742 , n13741 , n8269 );
xor ( n13743 , n12461 , n10376 );
xor ( n13744 , n13743 , n10067 );
not ( n13745 , n13744 );
xor ( n13746 , n7965 , n10146 );
xor ( n13747 , n13746 , n10652 );
and ( n13748 , n13745 , n13747 );
xor ( n13749 , n13742 , n13748 );
xor ( n13750 , n13740 , n13749 );
xor ( n13751 , n11315 , n11763 );
xor ( n13752 , n13751 , n10130 );
xor ( n13753 , n13461 , n13094 );
xor ( n13754 , n13753 , n12097 );
not ( n13755 , n13754 );
xor ( n13756 , n12940 , n7360 );
xor ( n13757 , n13756 , n7376 );
and ( n13758 , n13755 , n13757 );
xor ( n13759 , n13752 , n13758 );
xor ( n13760 , n13750 , n13759 );
xor ( n13761 , n9298 , n10105 );
not ( n13762 , n6474 );
buf ( n13763 , n6350 );
and ( n13764 , n13762 , n13763 );
buf ( n13765 , n6351 );
xor ( n13766 , n13765 , n13763 );
and ( n13767 , n13766 , n6474 );
or ( n13768 , n13764 , n13767 );
xor ( n13769 , n12316 , n13768 );
buf ( n13770 , n6352 );
xor ( n13771 , n13769 , n13770 );
xor ( n13772 , n13771 , n12224 );
buf ( n13773 , n6353 );
xor ( n13774 , n13772 , n13773 );
xor ( n13775 , n13761 , n13774 );
xor ( n13776 , n7087 , n12822 );
xor ( n13777 , n13776 , n13315 );
not ( n13778 , n13777 );
xor ( n13779 , n10620 , n8517 );
xor ( n13780 , n13779 , n11462 );
and ( n13781 , n13778 , n13780 );
xor ( n13782 , n13775 , n13781 );
xor ( n13783 , n13760 , n13782 );
xor ( n13784 , n12176 , n7274 );
not ( n13785 , n6474 );
buf ( n13786 , n6354 );
and ( n13787 , n13785 , n13786 );
buf ( n13788 , n6355 );
xor ( n13789 , n13788 , n13786 );
and ( n13790 , n13789 , n6474 );
or ( n13791 , n13787 , n13790 );
xor ( n13792 , n8986 , n13791 );
buf ( n13793 , n6356 );
xor ( n13794 , n13792 , n13793 );
buf ( n13795 , n6357 );
xor ( n13796 , n13794 , n13795 );
buf ( n13797 , n6358 );
xor ( n13798 , n13796 , n13797 );
xor ( n13799 , n13784 , n13798 );
xor ( n13800 , n9019 , n8336 );
xor ( n13801 , n13800 , n8535 );
not ( n13802 , n13801 );
xor ( n13803 , n9412 , n10527 );
xor ( n13804 , n13803 , n10549 );
and ( n13805 , n13802 , n13804 );
xor ( n13806 , n13799 , n13805 );
xor ( n13807 , n13783 , n13806 );
xor ( n13808 , n13731 , n13807 );
not ( n13809 , n6474 );
buf ( n13810 , n6359 );
and ( n13811 , n13809 , n13810 );
buf ( n13812 , n6360 );
xor ( n13813 , n13812 , n13810 );
and ( n13814 , n13813 , n6474 );
or ( n13815 , n13811 , n13814 );
xor ( n13816 , n13815 , n9770 );
xor ( n13817 , n13816 , n7112 );
xor ( n13818 , n9088 , n8743 );
xor ( n13819 , n13818 , n8764 );
not ( n13820 , n13819 );
xor ( n13821 , n6555 , n10745 );
not ( n13822 , n6474 );
buf ( n13823 , n6361 );
and ( n13824 , n13822 , n13823 );
buf ( n13825 , n6362 );
xor ( n13826 , n13825 , n13823 );
and ( n13827 , n13826 , n6474 );
or ( n13828 , n13824 , n13827 );
not ( n13829 , n6474 );
buf ( n13830 , n6363 );
and ( n13831 , n13829 , n13830 );
buf ( n13832 , n6364 );
xor ( n13833 , n13832 , n13830 );
and ( n13834 , n13833 , n6474 );
or ( n13835 , n13831 , n13834 );
xor ( n13836 , n13828 , n13835 );
buf ( n13837 , n6365 );
xor ( n13838 , n13836 , n13837 );
buf ( n13839 , n6366 );
xor ( n13840 , n13838 , n13839 );
buf ( n13841 , n6367 );
xor ( n13842 , n13840 , n13841 );
xor ( n13843 , n13821 , n13842 );
and ( n13844 , n13820 , n13843 );
xor ( n13845 , n13817 , n13844 );
xor ( n13846 , n6826 , n11636 );
xor ( n13847 , n13846 , n11657 );
xor ( n13848 , n12105 , n9606 );
xor ( n13849 , n13848 , n9628 );
not ( n13850 , n13849 );
xor ( n13851 , n11024 , n11998 );
xor ( n13852 , n13851 , n7521 );
and ( n13853 , n13850 , n13852 );
xor ( n13854 , n13847 , n13853 );
xor ( n13855 , n12778 , n11905 );
xor ( n13856 , n13855 , n11865 );
not ( n13857 , n13817 );
and ( n13858 , n13857 , n13819 );
xor ( n13859 , n13856 , n13858 );
xor ( n13860 , n13854 , n13859 );
xor ( n13861 , n12870 , n7376 );
xor ( n13862 , n13861 , n10465 );
xor ( n13863 , n9614 , n7883 );
xor ( n13864 , n13863 , n10731 );
not ( n13865 , n13864 );
xor ( n13866 , n8567 , n9732 );
xor ( n13867 , n13866 , n8227 );
and ( n13868 , n13865 , n13867 );
xor ( n13869 , n13862 , n13868 );
xor ( n13870 , n13860 , n13869 );
xor ( n13871 , n11740 , n7681 );
not ( n13872 , n6474 );
buf ( n13873 , n6368 );
and ( n13874 , n13872 , n13873 );
buf ( n13875 , n6369 );
xor ( n13876 , n13875 , n13873 );
and ( n13877 , n13876 , n6474 );
or ( n13878 , n13874 , n13877 );
buf ( n13879 , n6370 );
xor ( n13880 , n13878 , n13879 );
buf ( n13881 , n6371 );
xor ( n13882 , n13880 , n13881 );
buf ( n13883 , n6372 );
xor ( n13884 , n13882 , n13883 );
buf ( n13885 , n6373 );
xor ( n13886 , n13884 , n13885 );
xor ( n13887 , n13871 , n13886 );
xor ( n13888 , n8928 , n7072 );
xor ( n13889 , n13888 , n7095 );
not ( n13890 , n13889 );
xor ( n13891 , n12523 , n13606 );
xor ( n13892 , n13891 , n11583 );
and ( n13893 , n13890 , n13892 );
xor ( n13894 , n13887 , n13893 );
xor ( n13895 , n13870 , n13894 );
xor ( n13896 , n10624 , n8517 );
xor ( n13897 , n13896 , n11462 );
xor ( n13898 , n13454 , n13094 );
xor ( n13899 , n13898 , n12097 );
not ( n13900 , n13899 );
xor ( n13901 , n13791 , n7181 );
xor ( n13902 , n13901 , n9002 );
and ( n13903 , n13900 , n13902 );
xor ( n13904 , n13897 , n13903 );
xor ( n13905 , n13895 , n13904 );
xor ( n13906 , n13845 , n13905 );
xor ( n13907 , n8009 , n8137 );
xor ( n13908 , n13907 , n8159 );
xor ( n13909 , n7025 , n11031 );
xor ( n13910 , n13909 , n11052 );
not ( n13911 , n13910 );
buf ( n13912 , n6374 );
xor ( n13913 , n13912 , n12407 );
xor ( n13914 , n13913 , n12381 );
and ( n13915 , n13911 , n13914 );
xor ( n13916 , n13908 , n13915 );
not ( n13917 , n6474 );
buf ( n13918 , n6375 );
and ( n13919 , n13917 , n13918 );
buf ( n13920 , n6376 );
xor ( n13921 , n13920 , n13918 );
and ( n13922 , n13921 , n6474 );
or ( n13923 , n13919 , n13922 );
not ( n13924 , n6474 );
buf ( n13925 , n6377 );
and ( n13926 , n13924 , n13925 );
buf ( n13927 , n6378 );
xor ( n13928 , n13927 , n13925 );
and ( n13929 , n13928 , n6474 );
or ( n13930 , n13926 , n13929 );
xor ( n13931 , n13923 , n13930 );
xor ( n13932 , n13931 , n12997 );
buf ( n13933 , n6379 );
xor ( n13934 , n13932 , n13933 );
buf ( n13935 , n6380 );
xor ( n13936 , n13934 , n13935 );
xor ( n13937 , n8262 , n13936 );
xor ( n13938 , n13937 , n11786 );
xor ( n13939 , n7225 , n10263 );
xor ( n13940 , n13939 , n10285 );
not ( n13941 , n13940 );
xor ( n13942 , n8412 , n8314 );
xor ( n13943 , n13942 , n8336 );
and ( n13944 , n13941 , n13943 );
xor ( n13945 , n13938 , n13944 );
xor ( n13946 , n13916 , n13945 );
xor ( n13947 , n10589 , n6913 );
xor ( n13948 , n13947 , n8600 );
xor ( n13949 , n9255 , n8056 );
xor ( n13950 , n13949 , n8935 );
not ( n13951 , n13950 );
xor ( n13952 , n7834 , n7399 );
xor ( n13953 , n13952 , n7421 );
and ( n13954 , n13951 , n13953 );
xor ( n13955 , n13948 , n13954 );
xor ( n13956 , n13946 , n13955 );
xor ( n13957 , n9574 , n8204 );
xor ( n13958 , n13957 , n12854 );
xor ( n13959 , n13047 , n12987 );
xor ( n13960 , n13959 , n13339 );
not ( n13961 , n13960 );
xor ( n13962 , n13520 , n11427 );
xor ( n13963 , n13962 , n12945 );
and ( n13964 , n13961 , n13963 );
xor ( n13965 , n13958 , n13964 );
xor ( n13966 , n13956 , n13965 );
xor ( n13967 , n11734 , n7681 );
xor ( n13968 , n13967 , n13886 );
buf ( n13969 , n6381 );
xor ( n13970 , n13969 , n11833 );
xor ( n13971 , n13970 , n12365 );
not ( n13972 , n13971 );
xor ( n13973 , n8910 , n11481 );
xor ( n13974 , n13973 , n8696 );
and ( n13975 , n13972 , n13974 );
xor ( n13976 , n13968 , n13975 );
xor ( n13977 , n13966 , n13976 );
xor ( n13978 , n13906 , n13977 );
not ( n13979 , n13978 );
xor ( n13980 , n7023 , n11031 );
xor ( n13981 , n13980 , n11052 );
xor ( n13982 , n12092 , n6961 );
xor ( n13983 , n13982 , n9606 );
not ( n13984 , n13983 );
and ( n13985 , n13984 , n11306 );
xor ( n13986 , n13981 , n13985 );
xor ( n13987 , n8653 , n12871 );
xor ( n13988 , n13987 , n9079 );
not ( n13989 , n13988 );
not ( n13990 , n6474 );
buf ( n13991 , n6382 );
and ( n13992 , n13990 , n13991 );
buf ( n13993 , n6383 );
xor ( n13994 , n13993 , n13991 );
and ( n13995 , n13994 , n6474 );
or ( n13996 , n13992 , n13995 );
not ( n13997 , n6474 );
buf ( n13998 , n6384 );
and ( n13999 , n13997 , n13998 );
buf ( n14000 , n6385 );
xor ( n14001 , n14000 , n13998 );
and ( n14002 , n14001 , n6474 );
or ( n14003 , n13999 , n14002 );
xor ( n14004 , n13996 , n14003 );
buf ( n14005 , n6386 );
xor ( n14006 , n14004 , n14005 );
xor ( n14007 , n14006 , n12751 );
buf ( n14008 , n6387 );
xor ( n14009 , n14007 , n14008 );
xor ( n14010 , n7355 , n14009 );
xor ( n14011 , n14010 , n10224 );
and ( n14012 , n13989 , n14011 );
xor ( n14013 , n11228 , n14012 );
xor ( n14014 , n12736 , n7948 );
xor ( n14015 , n14014 , n7970 );
not ( n14016 , n14015 );
not ( n14017 , n6474 );
buf ( n14018 , n6388 );
and ( n14019 , n14017 , n14018 );
buf ( n14020 , n6389 );
xor ( n14021 , n14020 , n14018 );
and ( n14022 , n14021 , n6474 );
or ( n14023 , n14019 , n14022 );
buf ( n14024 , n6390 );
xor ( n14025 , n14023 , n14024 );
buf ( n14026 , n6391 );
xor ( n14027 , n14025 , n14026 );
buf ( n14028 , n6392 );
xor ( n14029 , n14027 , n14028 );
xor ( n14030 , n14029 , n8870 );
xor ( n14031 , n12360 , n14030 );
xor ( n14032 , n14031 , n8366 );
and ( n14033 , n14016 , n14032 );
xor ( n14034 , n11280 , n14033 );
xor ( n14035 , n14013 , n14034 );
not ( n14036 , n13981 );
and ( n14037 , n14036 , n13983 );
xor ( n14038 , n11368 , n14037 );
xor ( n14039 , n14035 , n14038 );
xor ( n14040 , n7414 , n6516 );
xor ( n14041 , n14040 , n13052 );
not ( n14042 , n14041 );
xor ( n14043 , n11690 , n9047 );
xor ( n14044 , n14043 , n9338 );
and ( n14045 , n14042 , n14044 );
xor ( n14046 , n11386 , n14045 );
xor ( n14047 , n14039 , n14046 );
not ( n14048 , n11172 );
not ( n14049 , n6474 );
buf ( n14050 , n6393 );
and ( n14051 , n14049 , n14050 );
buf ( n14052 , n6394 );
xor ( n14053 , n14052 , n14050 );
and ( n14054 , n14053 , n6474 );
or ( n14055 , n14051 , n14054 );
not ( n14056 , n6474 );
buf ( n14057 , n6395 );
and ( n14058 , n14056 , n14057 );
buf ( n14059 , n6396 );
xor ( n14060 , n14059 , n14057 );
and ( n14061 , n14060 , n6474 );
or ( n14062 , n14058 , n14061 );
xor ( n14063 , n14055 , n14062 );
xor ( n14064 , n14063 , n6790 );
buf ( n14065 , n6397 );
xor ( n14066 , n14064 , n14065 );
xor ( n14067 , n14066 , n12615 );
xor ( n14068 , n12644 , n14067 );
not ( n14069 , n6474 );
buf ( n14070 , n6398 );
and ( n14071 , n14069 , n14070 );
buf ( n14072 , n6399 );
xor ( n14073 , n14072 , n14070 );
and ( n14074 , n14073 , n6474 );
or ( n14075 , n14071 , n14074 );
xor ( n14076 , n14075 , n11959 );
buf ( n14077 , n6400 );
xor ( n14078 , n14076 , n14077 );
xor ( n14079 , n14078 , n12902 );
xor ( n14080 , n14079 , n13024 );
xor ( n14081 , n14068 , n14080 );
and ( n14082 , n14048 , n14081 );
xor ( n14083 , n11147 , n14082 );
xor ( n14084 , n14047 , n14083 );
xor ( n14085 , n13986 , n14084 );
xor ( n14086 , n6847 , n10488 );
xor ( n14087 , n14086 , n10504 );
not ( n14088 , n14087 );
xor ( n14089 , n7252 , n10864 );
xor ( n14090 , n14089 , n7159 );
and ( n14091 , n14088 , n14090 );
xor ( n14092 , n11440 , n14091 );
buf ( n14093 , n6401 );
xor ( n14094 , n14093 , n13774 );
xor ( n14095 , n14094 , n13018 );
not ( n14096 , n14095 );
xor ( n14097 , n8187 , n11132 );
xor ( n14098 , n14097 , n11146 );
and ( n14099 , n14096 , n14098 );
xor ( n14100 , n11483 , n14099 );
xor ( n14101 , n14092 , n14100 );
xor ( n14102 , n12563 , n9026 );
xor ( n14103 , n14102 , n9047 );
not ( n14104 , n14103 );
xor ( n14105 , n11762 , n13886 );
xor ( n14106 , n14105 , n12213 );
and ( n14107 , n14104 , n14106 );
xor ( n14108 , n11521 , n14107 );
xor ( n14109 , n14101 , n14108 );
xor ( n14110 , n12187 , n7274 );
xor ( n14111 , n14110 , n13798 );
not ( n14112 , n14111 );
xor ( n14113 , n10526 , n12302 );
xor ( n14114 , n14113 , n13273 );
and ( n14115 , n14112 , n14114 );
xor ( n14116 , n11559 , n14115 );
xor ( n14117 , n14109 , n14116 );
buf ( n14118 , n6402 );
xor ( n14119 , n7545 , n14118 );
buf ( n14120 , n6403 );
xor ( n14121 , n14119 , n14120 );
buf ( n14122 , n6404 );
xor ( n14123 , n14121 , n14122 );
buf ( n14124 , n6405 );
xor ( n14125 , n14123 , n14124 );
xor ( n14126 , n12696 , n14125 );
xor ( n14127 , n14126 , n14009 );
not ( n14128 , n14127 );
xor ( n14129 , n7770 , n12365 );
xor ( n14130 , n14129 , n12490 );
and ( n14131 , n14128 , n14130 );
xor ( n14132 , n11658 , n14131 );
xor ( n14133 , n14117 , n14132 );
xor ( n14134 , n14085 , n14133 );
and ( n14135 , n13979 , n14134 );
xor ( n14136 , n13808 , n14135 );
and ( n14137 , n14136 , n6475 );
or ( n14138 , n13621 , n14137 );
and ( n14139 , n13619 , n14138 );
buf ( n14140 , n14139 );
buf ( n14141 , n14140 );
not ( n14142 , n6469 );
not ( n14143 , n6475 );
and ( n14144 , n14143 , n7157 );
not ( n14145 , n6654 );
and ( n14146 , n14145 , n6517 );
xor ( n14147 , n13500 , n14146 );
not ( n14148 , n6696 );
and ( n14149 , n14148 , n6740 );
xor ( n14150 , n13528 , n14149 );
xor ( n14151 , n14147 , n14150 );
not ( n14152 , n6828 );
and ( n14153 , n14152 , n6873 );
xor ( n14154 , n13536 , n14153 );
xor ( n14155 , n14151 , n14154 );
not ( n14156 , n6962 );
and ( n14157 , n14156 , n7007 );
xor ( n14158 , n13565 , n14157 );
xor ( n14159 , n14155 , n14158 );
not ( n14160 , n7096 );
and ( n14161 , n14160 , n7135 );
xor ( n14162 , n13573 , n14161 );
xor ( n14163 , n14159 , n14162 );
xor ( n14164 , n6657 , n14163 );
xor ( n14165 , n9992 , n9464 );
xor ( n14166 , n14165 , n10929 );
not ( n14167 , n7231 );
and ( n14168 , n14167 , n7275 );
xor ( n14169 , n14166 , n14168 );
not ( n14170 , n6474 );
buf ( n14171 , n6406 );
and ( n14172 , n14170 , n14171 );
buf ( n14173 , n6407 );
xor ( n14174 , n14173 , n14171 );
and ( n14175 , n14174 , n6474 );
or ( n14176 , n14172 , n14175 );
not ( n14177 , n6474 );
buf ( n14178 , n6408 );
and ( n14179 , n14177 , n14178 );
buf ( n14180 , n6409 );
xor ( n14181 , n14180 , n14178 );
and ( n14182 , n14181 , n6474 );
or ( n14183 , n14179 , n14182 );
xor ( n14184 , n14176 , n14183 );
buf ( n14185 , n6410 );
xor ( n14186 , n14184 , n14185 );
buf ( n14187 , n6411 );
xor ( n14188 , n14186 , n14187 );
buf ( n14189 , n6412 );
xor ( n14190 , n14188 , n14189 );
xor ( n14191 , n9486 , n14190 );
xor ( n14192 , n14191 , n13591 );
not ( n14193 , n7332 );
and ( n14194 , n14193 , n7377 );
xor ( n14195 , n14192 , n14194 );
xor ( n14196 , n14169 , n14195 );
xor ( n14197 , n10501 , n10674 );
xor ( n14198 , n14197 , n6939 );
not ( n14199 , n7464 );
and ( n14200 , n14199 , n7466 );
xor ( n14201 , n14198 , n14200 );
xor ( n14202 , n14196 , n14201 );
xor ( n14203 , n12140 , n13842 );
xor ( n14204 , n14203 , n11949 );
not ( n14205 , n7538 );
and ( n14206 , n14205 , n7589 );
xor ( n14207 , n14204 , n14206 );
xor ( n14208 , n14202 , n14207 );
xor ( n14209 , n12278 , n11171 );
xor ( n14210 , n14209 , n6631 );
not ( n14211 , n7682 );
and ( n14212 , n14211 , n7733 );
xor ( n14213 , n14210 , n14212 );
xor ( n14214 , n14208 , n14213 );
xor ( n14215 , n14164 , n14214 );
not ( n14216 , n10841 );
and ( n14217 , n14216 , n8474 );
xor ( n14218 , n10837 , n14217 );
xor ( n14219 , n14218 , n10887 );
xor ( n14220 , n14219 , n11066 );
not ( n14221 , n14220 );
xor ( n14222 , n9849 , n12566 );
xor ( n14223 , n14222 , n11693 );
xor ( n14224 , n7120 , n12281 );
xor ( n14225 , n14224 , n12302 );
not ( n14226 , n14225 );
xor ( n14227 , n13586 , n11275 );
xor ( n14228 , n14227 , n9559 );
and ( n14229 , n14226 , n14228 );
xor ( n14230 , n14223 , n14229 );
xor ( n14231 , n6782 , n10309 );
xor ( n14232 , n14231 , n13367 );
xor ( n14233 , n12505 , n8388 );
xor ( n14234 , n14233 , n11998 );
not ( n14235 , n14234 );
xor ( n14236 , n9182 , n7112 );
xor ( n14237 , n14236 , n7134 );
and ( n14238 , n14235 , n14237 );
xor ( n14239 , n14232 , n14238 );
xor ( n14240 , n13687 , n7421 );
xor ( n14241 , n14240 , n12452 );
xor ( n14242 , n8055 , n7634 );
xor ( n14243 , n14242 , n7072 );
not ( n14244 , n14243 );
not ( n14245 , n6474 );
buf ( n14246 , n6413 );
and ( n14247 , n14245 , n14246 );
buf ( n14248 , n6414 );
xor ( n14249 , n14248 , n14246 );
and ( n14250 , n14249 , n6474 );
or ( n14251 , n14247 , n14250 );
xor ( n14252 , n14251 , n12727 );
xor ( n14253 , n14252 , n12742 );
and ( n14254 , n14244 , n14253 );
xor ( n14255 , n14241 , n14254 );
xor ( n14256 , n14239 , n14255 );
xor ( n14257 , n8201 , n11146 );
xor ( n14258 , n14257 , n9651 );
not ( n14259 , n14223 );
and ( n14260 , n14259 , n14225 );
xor ( n14261 , n14258 , n14260 );
xor ( n14262 , n14256 , n14261 );
xor ( n14263 , n7027 , n11031 );
xor ( n14264 , n14263 , n11052 );
xor ( n14265 , n13935 , n13018 );
xor ( n14266 , n14265 , n10394 );
not ( n14267 , n14266 );
xor ( n14268 , n8994 , n11741 );
xor ( n14269 , n14268 , n11763 );
and ( n14270 , n14267 , n14269 );
xor ( n14271 , n14264 , n14270 );
xor ( n14272 , n14262 , n14271 );
xor ( n14273 , n10572 , n6891 );
xor ( n14274 , n14273 , n6913 );
xor ( n14275 , n6630 , n12609 );
xor ( n14276 , n14275 , n10334 );
not ( n14277 , n14276 );
not ( n14278 , n6474 );
buf ( n14279 , n6415 );
and ( n14280 , n14278 , n14279 );
buf ( n14281 , n6416 );
xor ( n14282 , n14281 , n14279 );
and ( n14283 , n14282 , n6474 );
or ( n14284 , n14280 , n14283 );
not ( n14285 , n6474 );
buf ( n14286 , n6417 );
and ( n14287 , n14285 , n14286 );
buf ( n14288 , n6418 );
xor ( n14289 , n14288 , n14286 );
and ( n14290 , n14289 , n6474 );
or ( n14291 , n14287 , n14290 );
xor ( n14292 , n14284 , n14291 );
buf ( n14293 , n6419 );
xor ( n14294 , n14292 , n14293 );
buf ( n14295 , n6420 );
xor ( n14296 , n14294 , n14295 );
buf ( n14297 , n6421 );
xor ( n14298 , n14296 , n14297 );
xor ( n14299 , n10822 , n14298 );
not ( n14300 , n6474 );
buf ( n14301 , n6422 );
and ( n14302 , n14300 , n14301 );
buf ( n14303 , n6423 );
xor ( n14304 , n14303 , n14301 );
and ( n14305 , n14304 , n6474 );
or ( n14306 , n14302 , n14305 );
xor ( n14307 , n13815 , n14306 );
xor ( n14308 , n14307 , n9749 );
buf ( n14309 , n6424 );
xor ( n14310 , n14308 , n14309 );
buf ( n14311 , n6425 );
xor ( n14312 , n14310 , n14311 );
xor ( n14313 , n14299 , n14312 );
and ( n14314 , n14277 , n14313 );
xor ( n14315 , n14274 , n14314 );
xor ( n14316 , n14272 , n14315 );
xor ( n14317 , n14230 , n14316 );
xor ( n14318 , n12267 , n11171 );
xor ( n14319 , n14318 , n6631 );
xor ( n14320 , n13683 , n7421 );
xor ( n14321 , n14320 , n12452 );
not ( n14322 , n14321 );
xor ( n14323 , n6495 , n9973 );
xor ( n14324 , n14323 , n9995 );
and ( n14325 , n14322 , n14324 );
xor ( n14326 , n14319 , n14325 );
xor ( n14327 , n7934 , n10130 );
xor ( n14328 , n14327 , n10146 );
xor ( n14329 , n9347 , n6785 );
not ( n14330 , n6474 );
buf ( n14331 , n6426 );
and ( n14332 , n14330 , n14331 );
buf ( n14333 , n6427 );
xor ( n14334 , n14333 , n14331 );
and ( n14335 , n14334 , n6474 );
or ( n14336 , n14332 , n14335 );
not ( n14337 , n6474 );
buf ( n14338 , n6428 );
and ( n14339 , n14337 , n14338 );
buf ( n14340 , n6429 );
xor ( n14341 , n14340 , n14338 );
and ( n14342 , n14341 , n6474 );
or ( n14343 , n14339 , n14342 );
xor ( n14344 , n14336 , n14343 );
buf ( n14345 , n6430 );
xor ( n14346 , n14344 , n14345 );
xor ( n14347 , n14346 , n13354 );
buf ( n14348 , n6431 );
xor ( n14349 , n14347 , n14348 );
xor ( n14350 , n14329 , n14349 );
not ( n14351 , n14350 );
xor ( n14352 , n6712 , n10350 );
xor ( n14353 , n14352 , n9489 );
and ( n14354 , n14351 , n14353 );
xor ( n14355 , n14328 , n14354 );
xor ( n14356 , n14326 , n14355 );
xor ( n14357 , n6617 , n12609 );
xor ( n14358 , n14357 , n10334 );
xor ( n14359 , n8181 , n11132 );
xor ( n14360 , n14359 , n11146 );
not ( n14361 , n14360 );
xor ( n14362 , n13793 , n7181 );
xor ( n14363 , n14362 , n9002 );
and ( n14364 , n14361 , n14363 );
xor ( n14365 , n14358 , n14364 );
xor ( n14366 , n14356 , n14365 );
not ( n14367 , n6474 );
buf ( n14368 , n6432 );
and ( n14369 , n14367 , n14368 );
buf ( n14370 , n6433 );
xor ( n14371 , n14370 , n14368 );
and ( n14372 , n14371 , n6474 );
or ( n14373 , n14369 , n14372 );
xor ( n14374 , n14251 , n14373 );
buf ( n14375 , n6434 );
xor ( n14376 , n14374 , n14375 );
xor ( n14377 , n14376 , n12706 );
buf ( n14378 , n6435 );
xor ( n14379 , n14377 , n14378 );
xor ( n14380 , n13878 , n14379 );
not ( n14381 , n6474 );
buf ( n14382 , n6436 );
and ( n14383 , n14381 , n14382 );
buf ( n14384 , n6437 );
xor ( n14385 , n14384 , n14382 );
and ( n14386 , n14385 , n6474 );
or ( n14387 , n14383 , n14386 );
not ( n14388 , n6474 );
buf ( n14389 , n6438 );
and ( n14390 , n14388 , n14389 );
buf ( n14391 , n6439 );
xor ( n14392 , n14391 , n14389 );
and ( n14393 , n14392 , n6474 );
or ( n14394 , n14390 , n14393 );
xor ( n14395 , n14387 , n14394 );
buf ( n14396 , n6440 );
xor ( n14397 , n14395 , n14396 );
buf ( n14398 , n6441 );
xor ( n14399 , n14397 , n14398 );
buf ( n14400 , n6442 );
xor ( n14401 , n14399 , n14400 );
xor ( n14402 , n14380 , n14401 );
xor ( n14403 , n8510 , n7925 );
xor ( n14404 , n14403 , n6984 );
not ( n14405 , n14404 );
xor ( n14406 , n10039 , n11089 );
xor ( n14407 , n14406 , n11110 );
and ( n14408 , n14405 , n14407 );
xor ( n14409 , n14402 , n14408 );
xor ( n14410 , n14366 , n14409 );
xor ( n14411 , n9756 , n8950 );
xor ( n14412 , n14411 , n12581 );
xor ( n14413 , n13930 , n13018 );
xor ( n14414 , n14413 , n10394 );
not ( n14415 , n14414 );
xor ( n14416 , n9705 , n11949 );
xor ( n14417 , n14416 , n10574 );
and ( n14418 , n14415 , n14417 );
xor ( n14419 , n14412 , n14418 );
xor ( n14420 , n14410 , n14419 );
xor ( n14421 , n14317 , n14420 );
and ( n14422 , n14221 , n14421 );
xor ( n14423 , n14215 , n14422 );
and ( n14424 , n14423 , n6475 );
or ( n14425 , n14144 , n14424 );
and ( n14426 , n14142 , n14425 );
buf ( n14427 , n14426 );
buf ( n14428 , n14427 );
not ( n14429 , n6469 );
not ( n14430 , n6475 );
and ( n14431 , n14430 , n6887 );
xor ( n14432 , n11342 , n10022 );
xor ( n14433 , n14432 , n10044 );
xor ( n14434 , n9169 , n12111 );
xor ( n14435 , n14434 , n7910 );
not ( n14436 , n14435 );
xor ( n14437 , n10474 , n10652 );
xor ( n14438 , n14437 , n10674 );
and ( n14439 , n14436 , n14438 );
xor ( n14440 , n14433 , n14439 );
xor ( n14441 , n11106 , n7771 );
xor ( n14442 , n14441 , n7793 );
xor ( n14443 , n10103 , n9079 );
xor ( n14444 , n14443 , n9094 );
not ( n14445 , n14444 );
xor ( n14446 , n12466 , n10376 );
xor ( n14447 , n14446 , n10067 );
and ( n14448 , n14445 , n14447 );
xor ( n14449 , n14442 , n14448 );
xor ( n14450 , n7878 , n11520 );
xor ( n14451 , n14450 , n10625 );
xor ( n14452 , n8693 , n10170 );
xor ( n14453 , n14452 , n7030 );
not ( n14454 , n14453 );
xor ( n14455 , n11186 , n7494 );
xor ( n14456 , n14455 , n6850 );
and ( n14457 , n14454 , n14456 );
xor ( n14458 , n14451 , n14457 );
xor ( n14459 , n14449 , n14458 );
xor ( n14460 , n9916 , n11808 );
xor ( n14461 , n14460 , n12548 );
not ( n14462 , n6474 );
buf ( n14463 , n6443 );
and ( n14464 , n14462 , n14463 );
buf ( n14465 , n6444 );
xor ( n14466 , n14465 , n14463 );
and ( n14467 , n14466 , n6474 );
or ( n14468 , n14464 , n14467 );
xor ( n14469 , n11841 , n14468 );
xor ( n14470 , n14469 , n8553 );
buf ( n14471 , n6445 );
xor ( n14472 , n14470 , n14471 );
buf ( n14473 , n6446 );
xor ( n14474 , n14472 , n14473 );
xor ( n14475 , n6888 , n14474 );
xor ( n14476 , n14475 , n8972 );
not ( n14477 , n14476 );
xor ( n14478 , n12698 , n14125 );
xor ( n14479 , n14478 , n14009 );
and ( n14480 , n14477 , n14479 );
xor ( n14481 , n14461 , n14480 );
xor ( n14482 , n14459 , n14481 );
xor ( n14483 , n7458 , n8249 );
xor ( n14484 , n14483 , n6500 );
xor ( n14485 , n6808 , n13215 );
xor ( n14486 , n14485 , n11636 );
not ( n14487 , n14486 );
xor ( n14488 , n9122 , n12190 );
xor ( n14489 , n14488 , n6673 );
and ( n14490 , n14487 , n14489 );
xor ( n14491 , n14484 , n14490 );
xor ( n14492 , n14482 , n14491 );
xor ( n14493 , n8199 , n11146 );
xor ( n14494 , n14493 , n9651 );
not ( n14495 , n14433 );
and ( n14496 , n14495 , n14435 );
xor ( n14497 , n14494 , n14496 );
xor ( n14498 , n14492 , n14497 );
xor ( n14499 , n14440 , n14498 );
xor ( n14500 , n12648 , n14067 );
xor ( n14501 , n14500 , n14080 );
xor ( n14502 , n11873 , n9148 );
xor ( n14503 , n14502 , n9170 );
not ( n14504 , n14503 );
xor ( n14505 , n8689 , n10170 );
xor ( n14506 , n14505 , n7030 );
and ( n14507 , n14504 , n14506 );
xor ( n14508 , n14501 , n14507 );
xor ( n14509 , n10487 , n10652 );
xor ( n14510 , n14509 , n10674 );
xor ( n14511 , n7058 , n10836 );
xor ( n14512 , n14511 , n12822 );
not ( n14513 , n14512 );
xor ( n14514 , n9299 , n10105 );
xor ( n14515 , n14514 , n13774 );
and ( n14516 , n14513 , n14515 );
xor ( n14517 , n14510 , n14516 );
xor ( n14518 , n14508 , n14517 );
xor ( n14519 , n7587 , n8638 );
xor ( n14520 , n14519 , n8660 );
xor ( n14521 , n9156 , n12111 );
xor ( n14522 , n14521 , n7910 );
not ( n14523 , n14522 );
not ( n14524 , n6474 );
buf ( n14525 , n6447 );
and ( n14526 , n14524 , n14525 );
buf ( n14527 , n6448 );
xor ( n14528 , n14527 , n14525 );
and ( n14529 , n14528 , n6474 );
or ( n14530 , n14526 , n14529 );
xor ( n14531 , n14530 , n10285 );
xor ( n14532 , n14531 , n14474 );
and ( n14533 , n14523 , n14532 );
xor ( n14534 , n14520 , n14533 );
xor ( n14535 , n14518 , n14534 );
xor ( n14536 , n13797 , n7181 );
xor ( n14537 , n14536 , n9002 );
xor ( n14538 , n10201 , n9260 );
xor ( n14539 , n14538 , n13487 );
not ( n14540 , n14539 );
xor ( n14541 , n13640 , n11927 );
xor ( n14542 , n14541 , n11132 );
and ( n14543 , n14540 , n14542 );
xor ( n14544 , n14537 , n14543 );
xor ( n14545 , n14535 , n14544 );
xor ( n14546 , n9627 , n7883 );
xor ( n14547 , n14546 , n10731 );
xor ( n14548 , n12765 , n11905 );
xor ( n14549 , n14548 , n11865 );
not ( n14550 , n14549 );
xor ( n14551 , n9116 , n12190 );
xor ( n14552 , n14551 , n6673 );
and ( n14553 , n14550 , n14552 );
xor ( n14554 , n14547 , n14553 );
xor ( n14555 , n14545 , n14554 );
xor ( n14556 , n14499 , n14555 );
xor ( n14557 , n12565 , n9026 );
xor ( n14558 , n14557 , n9047 );
xor ( n14559 , n6703 , n10350 );
xor ( n14560 , n14559 , n9489 );
not ( n14561 , n14560 );
xor ( n14562 , n13209 , n10067 );
xor ( n14563 , n14562 , n10089 );
and ( n14564 , n14561 , n14563 );
xor ( n14565 , n14558 , n14564 );
xor ( n14566 , n9120 , n12190 );
xor ( n14567 , n14566 , n6673 );
not ( n14568 , n14558 );
and ( n14569 , n14568 , n14560 );
xor ( n14570 , n14567 , n14569 );
xor ( n14571 , n12668 , n14080 );
not ( n14572 , n6474 );
buf ( n14573 , n6449 );
and ( n14574 , n14572 , n14573 );
buf ( n14575 , n6450 );
xor ( n14576 , n14575 , n14573 );
and ( n14577 , n14576 , n6474 );
or ( n14578 , n14574 , n14577 );
xor ( n14579 , n14578 , n13229 );
xor ( n14580 , n14579 , n12702 );
buf ( n14581 , n6451 );
xor ( n14582 , n14580 , n14581 );
buf ( n14583 , n6452 );
xor ( n14584 , n14582 , n14583 );
xor ( n14585 , n14571 , n14584 );
xor ( n14586 , n9216 , n7134 );
xor ( n14587 , n14586 , n10527 );
not ( n14588 , n14587 );
xor ( n14589 , n10660 , n12779 );
xor ( n14590 , n14589 , n8092 );
and ( n14591 , n14588 , n14590 );
xor ( n14592 , n14585 , n14591 );
xor ( n14593 , n14570 , n14592 );
xor ( n14594 , n14028 , n8891 );
xor ( n14595 , n14594 , n8913 );
xor ( n14596 , n14348 , n13367 );
xor ( n14597 , n14596 , n10963 );
not ( n14598 , n14597 );
xor ( n14599 , n9475 , n14190 );
xor ( n14600 , n14599 , n13591 );
and ( n14601 , n14598 , n14600 );
xor ( n14602 , n14595 , n14601 );
xor ( n14603 , n14593 , n14602 );
xor ( n14604 , n9869 , n11693 );
xor ( n14605 , n14604 , n11714 );
xor ( n14606 , n8468 , n10193 );
xor ( n14607 , n14606 , n10209 );
not ( n14608 , n14607 );
xor ( n14609 , n11195 , n6850 );
xor ( n14610 , n14609 , n6872 );
and ( n14611 , n14608 , n14610 );
xor ( n14612 , n14605 , n14611 );
xor ( n14613 , n14603 , n14612 );
xor ( n14614 , n7418 , n6516 );
xor ( n14615 , n14614 , n13052 );
xor ( n14616 , n11274 , n13647 );
xor ( n14617 , n14616 , n8188 );
not ( n14618 , n14617 );
xor ( n14619 , n12289 , n6631 );
xor ( n14620 , n14619 , n6653 );
and ( n14621 , n14618 , n14620 );
xor ( n14622 , n14615 , n14621 );
xor ( n14623 , n14613 , n14622 );
xor ( n14624 , n14565 , n14623 );
xor ( n14625 , n14176 , n12040 );
xor ( n14626 , n14625 , n11275 );
xor ( n14627 , n12664 , n14080 );
xor ( n14628 , n14627 , n14584 );
not ( n14629 , n14628 );
xor ( n14630 , n6806 , n13215 );
xor ( n14631 , n14630 , n11636 );
and ( n14632 , n14629 , n14631 );
xor ( n14633 , n14626 , n14632 );
xor ( n14634 , n11851 , n13468 );
xor ( n14635 , n14634 , n9148 );
xor ( n14636 , n9536 , n9123 );
xor ( n14637 , n14636 , n7659 );
not ( n14638 , n14637 );
xor ( n14639 , n9576 , n8204 );
xor ( n14640 , n14639 , n12854 );
and ( n14641 , n14638 , n14640 );
xor ( n14642 , n14635 , n14641 );
xor ( n14643 , n14633 , n14642 );
xor ( n14644 , n11261 , n13647 );
xor ( n14645 , n14644 , n8188 );
xor ( n14646 , n11360 , n10044 );
xor ( n14647 , n14646 , n8891 );
not ( n14648 , n14647 );
xor ( n14649 , n10763 , n11187 );
xor ( n14650 , n14649 , n11201 );
and ( n14651 , n14648 , n14650 );
xor ( n14652 , n14645 , n14651 );
xor ( n14653 , n14643 , n14652 );
xor ( n14654 , n10496 , n10674 );
xor ( n14655 , n14654 , n6939 );
xor ( n14656 , n10569 , n6891 );
xor ( n14657 , n14656 , n6913 );
not ( n14658 , n14657 );
xor ( n14659 , n11026 , n11998 );
xor ( n14660 , n14659 , n7521 );
and ( n14661 , n14658 , n14660 );
xor ( n14662 , n14655 , n14661 );
xor ( n14663 , n14653 , n14662 );
xor ( n14664 , n10320 , n9439 );
not ( n14665 , n6474 );
buf ( n14666 , n6453 );
and ( n14667 , n14665 , n14666 );
buf ( n14668 , n6454 );
xor ( n14669 , n14668 , n14666 );
and ( n14670 , n14669 , n6474 );
or ( n14671 , n14667 , n14670 );
xor ( n14672 , n14671 , n12010 );
buf ( n14673 , n6455 );
xor ( n14674 , n14672 , n14673 );
buf ( n14675 , n6456 );
xor ( n14676 , n14674 , n14675 );
buf ( n14677 , n6457 );
xor ( n14678 , n14676 , n14677 );
xor ( n14679 , n14664 , n14678 );
xor ( n14680 , n8462 , n10193 );
xor ( n14681 , n14680 , n10209 );
not ( n14682 , n14681 );
xor ( n14683 , n7832 , n7399 );
xor ( n14684 , n14683 , n7421 );
and ( n14685 , n14682 , n14684 );
xor ( n14686 , n14679 , n14685 );
xor ( n14687 , n14663 , n14686 );
xor ( n14688 , n14624 , n14687 );
not ( n14689 , n14688 );
not ( n14690 , n11880 );
xor ( n14691 , n8132 , n7046 );
xor ( n14692 , n14691 , n8414 );
and ( n14693 , n14690 , n14692 );
xor ( n14694 , n11843 , n14693 );
xor ( n14695 , n14694 , n12044 );
xor ( n14696 , n14695 , n12250 );
and ( n14697 , n14689 , n14696 );
xor ( n14698 , n14556 , n14697 );
and ( n14699 , n14698 , n6475 );
or ( n14700 , n14431 , n14699 );
and ( n14701 , n14429 , n14700 );
buf ( n14702 , n14701 );
buf ( n14703 , n14702 );
not ( n14704 , n6469 );
not ( n14705 , n6475 );
and ( n14706 , n14705 , n11919 );
xor ( n14707 , n7436 , n8227 );
xor ( n14708 , n14707 , n8249 );
xor ( n14709 , n8619 , n7837 );
xor ( n14710 , n14709 , n13690 );
not ( n14711 , n14710 );
xor ( n14712 , n9488 , n14190 );
xor ( n14713 , n14712 , n13591 );
and ( n14714 , n14711 , n14713 );
xor ( n14715 , n14708 , n14714 );
xor ( n14716 , n11548 , n9816 );
xor ( n14717 , n14716 , n6811 );
xor ( n14718 , n12447 , n13052 );
xor ( n14719 , n14718 , n10376 );
not ( n14720 , n14719 );
xor ( n14721 , n10861 , n9534 );
xor ( n14722 , n14721 , n9543 );
and ( n14723 , n14720 , n14722 );
xor ( n14724 , n14717 , n14723 );
xor ( n14725 , n6577 , n7732 );
xor ( n14726 , n14725 , n8076 );
xor ( n14727 , n13642 , n11927 );
xor ( n14728 , n14727 , n11132 );
not ( n14729 , n14728 );
xor ( n14730 , n13212 , n10067 );
xor ( n14731 , n14730 , n10089 );
and ( n14732 , n14729 , n14731 );
xor ( n14733 , n14726 , n14732 );
xor ( n14734 , n14724 , n14733 );
xor ( n14735 , n10983 , n12854 );
not ( n14736 , n6474 );
buf ( n14737 , n6458 );
and ( n14738 , n14736 , n14737 );
buf ( n14739 , n6459 );
xor ( n14740 , n14739 , n14737 );
and ( n14741 , n14740 , n6474 );
or ( n14742 , n14738 , n14741 );
not ( n14743 , n6474 );
buf ( n14744 , n6460 );
and ( n14745 , n14743 , n14744 );
buf ( n14746 , n6461 );
xor ( n14747 , n14746 , n14744 );
and ( n14748 , n14747 , n6474 );
or ( n14749 , n14745 , n14748 );
xor ( n14750 , n14742 , n14749 );
buf ( n14751 , n6462 );
xor ( n14752 , n14750 , n14751 );
buf ( n14753 , n6463 );
xor ( n14754 , n14752 , n14753 );
buf ( n14755 , n6464 );
xor ( n14756 , n14754 , n14755 );
xor ( n14757 , n14735 , n14756 );
xor ( n14758 , n14375 , n12727 );
xor ( n14759 , n14758 , n12742 );
not ( n14760 , n14759 );
buf ( n14761 , n6465 );
xor ( n14762 , n14761 , n11833 );
xor ( n14763 , n14762 , n12365 );
and ( n14764 , n14760 , n14763 );
xor ( n14765 , n14757 , n14764 );
xor ( n14766 , n14734 , n14765 );
xor ( n14767 , n7223 , n10263 );
xor ( n14768 , n14767 , n10285 );
xor ( n14769 , n8361 , n8913 );
xor ( n14770 , n14769 , n13392 );
not ( n14771 , n14770 );
xor ( n14772 , n8333 , n10905 );
xor ( n14773 , n14772 , n9378 );
and ( n14774 , n14771 , n14773 );
xor ( n14775 , n14768 , n14774 );
xor ( n14776 , n14766 , n14775 );
xor ( n14777 , n9914 , n11808 );
xor ( n14778 , n14777 , n12548 );
not ( n14779 , n14708 );
and ( n14780 , n14779 , n14710 );
xor ( n14781 , n14778 , n14780 );
xor ( n14782 , n14776 , n14781 );
xor ( n14783 , n14715 , n14782 );
xor ( n14784 , n14783 , n14623 );
xor ( n14785 , n8740 , n11252 );
xor ( n14786 , n14785 , n8269 );
not ( n14787 , n14501 );
and ( n14788 , n14787 , n14503 );
xor ( n14789 , n14786 , n14788 );
xor ( n14790 , n12486 , n8366 );
xor ( n14791 , n14790 , n8388 );
not ( n14792 , n14786 );
and ( n14793 , n14792 , n14501 );
xor ( n14794 , n14791 , n14793 );
xor ( n14795 , n8512 , n7925 );
xor ( n14796 , n14795 , n6984 );
xor ( n14797 , n11028 , n11998 );
xor ( n14798 , n14797 , n7521 );
not ( n14799 , n14798 );
and ( n14800 , n14799 , n14510 );
xor ( n14801 , n14796 , n14800 );
xor ( n14802 , n14794 , n14801 );
xor ( n14803 , n13131 , n9895 );
xor ( n14804 , n14803 , n7612 );
xor ( n14805 , n7438 , n8227 );
xor ( n14806 , n14805 , n8249 );
not ( n14807 , n14806 );
and ( n14808 , n14807 , n14520 );
xor ( n14809 , n14804 , n14808 );
xor ( n14810 , n14802 , n14809 );
xor ( n14811 , n9969 , n8622 );
xor ( n14812 , n14811 , n9464 );
xor ( n14813 , n10086 , n12671 );
xor ( n14814 , n14813 , n13560 );
not ( n14815 , n14814 );
and ( n14816 , n14815 , n14537 );
xor ( n14817 , n14812 , n14816 );
xor ( n14818 , n14810 , n14817 );
xor ( n14819 , n10708 , n11604 );
xor ( n14820 , n14819 , n11345 );
not ( n14821 , n6474 );
buf ( n14822 , n6466 );
and ( n14823 , n14821 , n14822 );
buf ( n14824 , n6467 );
xor ( n14825 , n14824 , n14822 );
and ( n14826 , n14825 , n6474 );
or ( n14827 , n14823 , n14826 );
xor ( n14828 , n14827 , n12343 );
xor ( n14829 , n14828 , n13969 );
xor ( n14830 , n14829 , n14761 );
buf ( n14831 , n6468 );
xor ( n14832 , n14830 , n14831 );
xor ( n14833 , n11086 , n14832 );
xor ( n14834 , n14833 , n7771 );
not ( n14835 , n14834 );
and ( n14836 , n14835 , n14547 );
xor ( n14837 , n14820 , n14836 );
xor ( n14838 , n14818 , n14837 );
xor ( n14839 , n14789 , n14838 );
xor ( n14840 , n14839 , n13905 );
not ( n14841 , n14840 );
not ( n14842 , n13663 );
xor ( n14843 , n10923 , n9794 );
xor ( n14844 , n14843 , n9816 );
and ( n14845 , n14842 , n14844 );
xor ( n14846 , n13660 , n14845 );
xor ( n14847 , n14846 , n13730 );
xor ( n14848 , n14847 , n13807 );
and ( n14849 , n14841 , n14848 );
xor ( n14850 , n14784 , n14849 );
and ( n14851 , n14850 , n6475 );
or ( n14852 , n14706 , n14851 );
and ( n14853 , n14704 , n14852 );
buf ( n14854 , n14853 );
buf ( n14855 , n14854 );
not ( n14856 , n6469 );
not ( n14857 , n6475 );
and ( n14858 , n14857 , n6860 );
xor ( n14859 , n11301 , n8159 );
xor ( n14860 , n14859 , n12566 );
xor ( n14861 , n10021 , n14756 );
xor ( n14862 , n14861 , n11089 );
not ( n14863 , n14862 );
xor ( n14864 , n8027 , n7612 );
xor ( n14865 , n14864 , n7634 );
and ( n14866 , n14863 , n14865 );
xor ( n14867 , n14860 , n14866 );
xor ( n14868 , n12138 , n13842 );
xor ( n14869 , n14868 , n11949 );
not ( n14870 , n14860 );
and ( n14871 , n14870 , n14862 );
xor ( n14872 , n14869 , n14871 );
xor ( n14873 , n7089 , n12822 );
xor ( n14874 , n14873 , n13315 );
xor ( n14875 , n9729 , n10574 );
xor ( n14876 , n14875 , n10595 );
not ( n14877 , n14876 );
xor ( n14878 , n12406 , n8291 );
xor ( n14879 , n14878 , n9921 );
and ( n14880 , n14877 , n14879 );
xor ( n14881 , n14874 , n14880 );
xor ( n14882 , n14872 , n14881 );
xor ( n14883 , n6780 , n10309 );
xor ( n14884 , n14883 , n13367 );
xor ( n14885 , n10347 , n14678 );
xor ( n14886 , n14885 , n14190 );
not ( n14887 , n14886 );
xor ( n14888 , n10169 , n12506 );
xor ( n14889 , n14888 , n11031 );
and ( n14890 , n14887 , n14889 );
xor ( n14891 , n14884 , n14890 );
xor ( n14892 , n14882 , n14891 );
xor ( n14893 , n11270 , n13647 );
xor ( n14894 , n14893 , n8188 );
xor ( n14895 , n11364 , n10044 );
xor ( n14896 , n14895 , n8891 );
not ( n14897 , n14896 );
xor ( n14898 , n12944 , n7360 );
xor ( n14899 , n14898 , n7376 );
and ( n14900 , n14897 , n14899 );
xor ( n14901 , n14894 , n14900 );
xor ( n14902 , n14892 , n14901 );
xor ( n14903 , n9601 , n7861 );
xor ( n14904 , n14903 , n7883 );
xor ( n14905 , n8514 , n7925 );
xor ( n14906 , n14905 , n6984 );
not ( n14907 , n14906 );
xor ( n14908 , n14297 , n13487 );
xor ( n14909 , n14908 , n9770 );
and ( n14910 , n14907 , n14909 );
xor ( n14911 , n14904 , n14910 );
xor ( n14912 , n14902 , n14911 );
xor ( n14913 , n14867 , n14912 );
xor ( n14914 , n14831 , n11833 );
xor ( n14915 , n14914 , n12365 );
xor ( n14916 , n10800 , n10209 );
xor ( n14917 , n14916 , n14298 );
not ( n14918 , n14917 );
xor ( n14919 , n9725 , n10574 );
xor ( n14920 , n14919 , n10595 );
and ( n14921 , n14918 , n14920 );
xor ( n14922 , n14915 , n14921 );
xor ( n14923 , n11807 , n10416 );
xor ( n14924 , n14923 , n13135 );
xor ( n14925 , n9109 , n12190 );
xor ( n14926 , n14925 , n6673 );
not ( n14927 , n14926 );
xor ( n14928 , n7530 , n11304 );
xor ( n14929 , n14928 , n9850 );
and ( n14930 , n14927 , n14929 );
xor ( n14931 , n14924 , n14930 );
xor ( n14932 , n14922 , n14931 );
xor ( n14933 , n11997 , n7994 );
xor ( n14934 , n14933 , n8016 );
xor ( n14935 , n14284 , n13487 );
xor ( n14936 , n14935 , n9770 );
not ( n14937 , n14936 );
xor ( n14938 , n10327 , n9439 );
xor ( n14939 , n14938 , n14678 );
and ( n14940 , n14937 , n14939 );
xor ( n14941 , n14934 , n14940 );
xor ( n14942 , n14932 , n14941 );
xor ( n14943 , n10223 , n9290 );
xor ( n14944 , n14943 , n9306 );
xor ( n14945 , n7245 , n10864 );
xor ( n14946 , n14945 , n7159 );
not ( n14947 , n14946 );
xor ( n14948 , n6932 , n8092 );
xor ( n14949 , n14948 , n8114 );
and ( n14950 , n14947 , n14949 );
xor ( n14951 , n14944 , n14950 );
xor ( n14952 , n14942 , n14951 );
xor ( n14953 , n8949 , n7095 );
xor ( n14954 , n14953 , n8799 );
xor ( n14955 , n9883 , n8447 );
xor ( n14956 , n14955 , n8469 );
not ( n14957 , n14956 );
xor ( n14958 , n12938 , n7360 );
xor ( n14959 , n14958 , n7376 );
and ( n14960 , n14957 , n14959 );
xor ( n14961 , n14954 , n14960 );
xor ( n14962 , n14952 , n14961 );
xor ( n14963 , n14913 , n14962 );
xor ( n14964 , n10088 , n12671 );
xor ( n14965 , n14964 , n13560 );
xor ( n14966 , n11039 , n7521 );
xor ( n14967 , n14966 , n7537 );
not ( n14968 , n14967 );
xor ( n14969 , n8197 , n11146 );
xor ( n14970 , n14969 , n9651 );
and ( n14971 , n14968 , n14970 );
xor ( n14972 , n14965 , n14971 );
xor ( n14973 , n11602 , n10990 );
xor ( n14974 , n14973 , n10022 );
xor ( n14975 , n9416 , n10527 );
xor ( n14976 , n14975 , n10549 );
not ( n14977 , n14976 );
xor ( n14978 , n7574 , n8638 );
xor ( n14979 , n14978 , n8660 );
and ( n14980 , n14977 , n14979 );
xor ( n14981 , n14974 , n14980 );
xor ( n14982 , n13092 , n6939 );
xor ( n14983 , n14982 , n6961 );
not ( n14984 , n14965 );
and ( n14985 , n14984 , n14967 );
xor ( n14986 , n14983 , n14985 );
xor ( n14987 , n14981 , n14986 );
xor ( n14988 , n7609 , n8469 );
xor ( n14989 , n14988 , n10814 );
xor ( n14990 , n13646 , n11927 );
xor ( n14991 , n14990 , n11132 );
not ( n14992 , n14991 );
xor ( n14993 , n8646 , n12871 );
xor ( n14994 , n14993 , n9079 );
and ( n14995 , n14992 , n14994 );
xor ( n14996 , n14989 , n14995 );
xor ( n14997 , n14987 , n14996 );
xor ( n14998 , n10331 , n9439 );
xor ( n14999 , n14998 , n14678 );
xor ( n15000 , n7398 , n6500 );
xor ( n15001 , n15000 , n6516 );
not ( n15002 , n15001 );
xor ( n15003 , n7986 , n8710 );
xor ( n15004 , n15003 , n8137 );
and ( n15005 , n15002 , n15004 );
xor ( n15006 , n14999 , n15005 );
xor ( n15007 , n14997 , n15006 );
xor ( n15008 , n14398 , n12742 );
xor ( n15009 , n15008 , n7494 );
xor ( n15010 , n10464 , n10246 );
xor ( n15011 , n15010 , n11252 );
not ( n15012 , n15011 );
xor ( n15013 , n14578 , n11981 );
xor ( n15014 , n15013 , n7566 );
and ( n15015 , n15012 , n15014 );
xor ( n15016 , n15009 , n15015 );
xor ( n15017 , n15007 , n15016 );
xor ( n15018 , n14972 , n15017 );
xor ( n15019 , n12864 , n7376 );
xor ( n15020 , n15019 , n10465 );
xor ( n15021 , n13089 , n6939 );
xor ( n15022 , n15021 , n6961 );
not ( n15023 , n15022 );
xor ( n15024 , n12774 , n11905 );
xor ( n15025 , n15024 , n11865 );
and ( n15026 , n15023 , n15025 );
xor ( n15027 , n15020 , n15026 );
xor ( n15028 , n11290 , n8159 );
xor ( n15029 , n15028 , n12566 );
xor ( n15030 , n10706 , n11604 );
xor ( n15031 , n15030 , n11345 );
not ( n15032 , n15031 );
xor ( n15033 , n8760 , n8269 );
xor ( n15034 , n15033 , n8291 );
and ( n15035 , n15032 , n15034 );
xor ( n15036 , n15029 , n15035 );
xor ( n15037 , n15027 , n15036 );
xor ( n15038 , n10451 , n10246 );
xor ( n15039 , n15038 , n11252 );
xor ( n15040 , n9890 , n8447 );
xor ( n15041 , n15040 , n8469 );
not ( n15042 , n15041 );
xor ( n15043 , n8383 , n13392 );
xor ( n15044 , n15043 , n7994 );
and ( n15045 , n15042 , n15044 );
xor ( n15046 , n15039 , n15045 );
xor ( n15047 , n15037 , n15046 );
xor ( n15048 , n7038 , n11052 );
xor ( n15049 , n15048 , n8314 );
xor ( n15050 , n7151 , n9543 );
xor ( n15051 , n15050 , n13427 );
not ( n15052 , n15051 );
xor ( n15053 , n8945 , n7095 );
xor ( n15054 , n15053 , n8799 );
and ( n15055 , n15052 , n15054 );
xor ( n15056 , n15049 , n15055 );
xor ( n15057 , n15047 , n15056 );
xor ( n15058 , n13509 , n11427 );
xor ( n15059 , n15058 , n12945 );
xor ( n15060 , n7393 , n6500 );
xor ( n15061 , n15060 , n6516 );
not ( n15062 , n15061 );
xor ( n15063 , n13881 , n14379 );
xor ( n15064 , n15063 , n14401 );
and ( n15065 , n15062 , n15064 );
xor ( n15066 , n15059 , n15065 );
xor ( n15067 , n15057 , n15066 );
xor ( n15068 , n15018 , n15067 );
not ( n15069 , n15068 );
not ( n15070 , n13867 );
xor ( n15071 , n8464 , n10193 );
xor ( n15072 , n15071 , n10209 );
and ( n15073 , n15070 , n15072 );
xor ( n15074 , n13864 , n15073 );
xor ( n15075 , n15074 , n13905 );
xor ( n15076 , n15075 , n13977 );
and ( n15077 , n15069 , n15076 );
xor ( n15078 , n14963 , n15077 );
and ( n15079 , n15078 , n6475 );
or ( n15080 , n14858 , n15079 );
and ( n15081 , n14856 , n15080 );
buf ( n15082 , n15081 );
buf ( n15083 , n15082 );
endmodule
|
module xilinx_decoder #(
parameter T = 3,
parameter DATA_BITS = 5,
parameter BITS = 1,
parameter SYN_REG_RATIO = 1,
parameter ERR_REG_RATIO = 1,
parameter SYN_PIPELINE_STAGES = 0,
parameter ERR_PIPELINE_STAGES = 0,
parameter ACCUM = 1
) (
input [BITS-1:0] data_in,
input clk_in,
input start_in,
output [BITS-1:0] err_out,
output first_out
);
`include "bch_params.vh"
localparam BCH_PARAMS = bch_params(DATA_BITS, T);
wire [`BCH_SYNDROMES_SZ(BCH_PARAMS)-1:0] syndromes;
wire syn_done;
wire key_ready;
wire key_done;
(* KEEP = "TRUE" *)
(* S = "TRUE" *)
wire [`BCH_SIGMA_SZ(BCH_PARAMS)-1:0] sigma;
wire [`BCH_ERR_SZ(BCH_PARAMS)-1:0] err_count;
wire err_first;
wire [BITS-1:0] data;
wire start;
wire [BITS-1:0] err;
pipeline #(1) u_pipeline [BITS*2+2-1:0] (
.clk(clk),
.i({data_in, start_in, err_first, err}),
.o({data, start, first_out, err_out})
);
BUFG u_bufg (
.I(clk_in),
.O(clk)
);
bch_syndrome #(BCH_PARAMS, BITS, SYN_REG_RATIO, SYN_PIPELINE_STAGES) u_bch_syndrome(
.clk(clk),
.start(start),
.ce(1'b1),
.data_in(data),
.syndromes(syndromes),
.done(syn_done)
);
bch_sigma_bma_serial #(BCH_PARAMS) u_bma (
.clk(clk),
.start(syn_done && key_ready),
.ready(key_ready),
.syndromes(syndromes),
.sigma(sigma),
.done(key_done),
.ack_done(1'b1),
.err_count(err_count)
);
bch_error_tmec #(BCH_PARAMS, BITS, ERR_REG_RATIO, ERR_PIPELINE_STAGES, ACCUM) u_error_tmec(
.clk(clk),
.start(key_done),
.sigma(sigma),
.first(err_first),
.err(err)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A211O_BEHAVIORAL_PP_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a211o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211O_BEHAVIORAL_PP_V |
//
// Designed by Qiang Wu
//
`timescale 1ns/1ps
`include "yf32_define.v"
`include "NF_2.1_defines.v"
`include "reg_defines_reference_router.v"
`include "registers.v"
module np_core
#(parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter INPUT_ARBITER_STAGE_NUM = 2,
parameter IO_QUEUE_STAGE_NUM = 8'hff,
parameter NUM_OUTPUT_QUEUES = 8,
parameter NUM_IQ_BITS = 3,
parameter STAGE_NUM = 4,
parameter CPU_NUM = 4,
parameter CPU_QUEUE_NUM = 0)
(
input protocol,
// --- data path interface
output [DATA_WIDTH-1:0] out_data,
output [CTRL_WIDTH-1:0] out_ctrl,
output out_wr,
input out_rdy,
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
output in_rdy,
// --- Register interface
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg_req_out,
output reg_ack_out,
output reg_rd_wr_L_out,
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
// --- Misc
input clk,
input core_sp_clk,
input statemac_clk,
input reset,
//for monitor
// for security monitoring
output [31:0] instruction_sec_mon,
output [31:0] prog_counter_sec_mon,
output [31:0] ppu_mem_addr,
input packet_drop
);
assign reg_req_out = reg_req_in;
assign reg_ack_out = reg_ack_in;
assign reg_rd_wr_L_out = reg_rd_wr_L_in;
assign reg_addr_out = reg_addr_in;
assign reg_data_out = reg_data_in;
assign reg_src_out = reg_src_in;
wire [63:0] fc_out_data0;
wire [23:0] fc_out_pkt_route0;
wire fc_out_wr0;
wire fc_out_req0;
wire fc_out_ack0;
wire fc_out_bypass0;
wire [63:0] fc_out_data1;
wire [23:0] fc_out_pkt_route1;
wire fc_out_wr1;
wire fc_out_req1;
wire fc_out_ack1;
wire fc_out_bypass1;
wire [63:0] fc_out_data2;
wire [23:0] fc_out_pkt_route2;
wire fc_out_wr2;
wire fc_out_req2;
wire fc_out_ack2;
wire fc_out_bypass2;
wire [63:0] fc_out_data3;
wire [23:0] fc_out_pkt_route3;
wire fc_out_wr3;
wire fc_out_req3;
wire fc_out_ack3;
wire fc_out_bypass3;
wire [63:0] pg_out_data0;
wire [23:0] pg_out_pkt_route0;
wire pg_out_wr0;
wire pg_out_req0;
wire pg_out_ack0;
wire pg_out_bop0;
wire pg_out_eop0;
wire pg_out_rdy0;
wire pg_out_bypass0;
wire [63:0] pg_out_data1;
wire [23:0] pg_out_pkt_route1;
wire pg_out_wr1;
wire pg_out_req1;
wire pg_out_ack1;
wire pg_out_bop1;
wire pg_out_eop1;
wire pg_out_rdy1;
wire pg_out_bypass1;
wire [63:0] pg_out_data2;
wire [23:0] pg_out_pkt_route2;
wire pg_out_wr2;
wire pg_out_req2;
wire pg_out_ack2;
wire pg_out_bop2;
wire pg_out_eop2;
wire pg_out_rdy2;
wire pg_out_bypass2;
wire [63:0] pg_out_data3;
wire [23:0] pg_out_pkt_route3;
wire pg_out_wr3;
wire pg_out_req3;
wire pg_out_ack3;
wire pg_out_bop3;
wire pg_out_eop3;
wire pg_out_rdy3;
wire [63:0] data01;
wire [23:0] pkt_route01;
wire wr01;
wire req01;
wire ack01;
wire bypass01;
wire [63:0] data10;
wire [23:0] pkt_route10;
wire wr10;
wire req10;
wire ack10;
wire bypass10;
wire [63:0] data02;
wire [23:0] pkt_route02;
wire wr02;
wire req02;
wire ack02;
wire bypass02;
wire [63:0] data20;
wire [23:0] pkt_route20;
wire wr20;
wire req20;
wire ack20;
wire bypass20;
wire [63:0] data13;
wire [23:0] pkt_route13;
wire wr13;
wire req13;
wire ack13;
wire bypass13;
wire [63:0] data31;
wire [23:0] pkt_route31;
wire wr31;
wire req31;
wire ack31;
wire bypass31;
wire [63:0] data23;
wire [23:0] pkt_route23;
wire wr23;
wire req23;
wire ack23;
wire bypass23;
wire [63:0] data32;
wire [23:0] pkt_route32;
wire wr32;
wire req32;
wire ack32;
wire bypass32;
wire [239:0] TRIG_IS0;
wire [239:0] TRIG_IS2;
wire [239:0] TRIG_OS0;
wire reset0;
wire reset1;
wire reset2;
wire reset3;
wire packet_drop_core_zero;
wire packet_drop_core_one;
wire packet_drop_core_two;
wire packet_drop_core_three;
wire cam_we;
wire [3:0] cam_wr_addr;
wire [31:0] cam_din;
wire cam_wr_ack;
wire ppu3_sel;
flow_classification fc(
.protocol1(protocol),
.out_data0 (fc_out_data0),
.out_pkt_route0 (fc_out_pkt_route0),
.out_wr0 (fc_out_wr0),
.out_req0 (fc_out_req0),
.out_ack0 (fc_out_ack0),
.out_bypass0 (fc_out_bypass0),
.out_protocol0 (fc_out_protocol0),
.out_data1 (fc_out_data1),
.out_pkt_route1 (fc_out_pkt_route1),
.out_wr1 (fc_out_wr1),
.out_req1 (fc_out_req1),
.out_ack1 (fc_out_ack1),
.out_bypass1 (fc_out_bypass1),
.out_protocol1(fc_out_protocol1),
.out_data2 (fc_out_data2),
.out_pkt_route2 (fc_out_pkt_route2),
.out_wr2 (fc_out_wr2),
.out_req2 (fc_out_req2),
.out_ack2 (fc_out_ack2),
.out_bypass2 (fc_out_bypass2),
.out_protocol2(fc_out_protocol2),
.out_data3 (fc_out_data3),
.out_pkt_route3 (fc_out_pkt_route3),
.out_wr3 (fc_out_wr3),
.out_req3 (fc_out_req3),
.out_ack3 (fc_out_ack3),
.out_bypass3 (fc_out_bypass3),
.out_protocol3(fc_out_protocol3),
.in_data (in_data),
.in_ctrl (in_ctrl),
.in_wr (in_wr),
.in_rdy (in_rdy),
.ppu3_sel (ppu3_sel),
.clk (clk),
.reset (reset)
);
wire packet_drop_signal[CPU_NUM -1 :0];
wire processor_reset_seq[CPU_NUM -1 :0];
wire sp_pkt_done[CPU_NUM -1 :0];
wire out_ack_reset[CPU_NUM -1 :0];
wire sp_interrupt_wire[CPU_NUM -1 :0];
wire [3:0]four_bit_hash_output_0, four_bit_hash_output_1, four_bit_hash_output_2, four_bit_hash_output_3;
wire new_inst_signal[CPU_NUM -1 :0];
ppu ppu0(
.clk (clk),
.core_sp_clk (core_sp_clk),
.reset (reset),
.TRIG_IS (TRIG_IS0),
.in_data0 (data10),
.in_pkt_route0 (pkt_route10),
.in_wr0 (wr10),
.in_req0 (req10),
.in_ack0 (ack10),
.in_bypass0 (bypass10),
.in_data1 (fc_out_data0),
.in_pkt_route1 (fc_out_pkt_route0),
.in_wr1 (fc_out_wr0),
.in_req1 (fc_out_req0),
.in_ack1 (fc_out_ack0),
.in_bypass1 (fc_out_bypass0),
.in_protocol1(fc_out_protocol0),
.in_data2 (),
.in_pkt_route2 (),
.in_wr2 (),
.in_req2 (),
.in_ack2 (),
.in_bypass2 (),
.in_data3 (data20),
.in_pkt_route3 (pkt_route20),
.in_wr3 (wr20),
.in_req3 (req20),
.in_ack3 (ack20),
.in_bypass3 (bypass20),
.out_data0 (data01),
.out_pkt_route0 (pkt_route01),
.out_wr0 (wr01),
.out_req0 (req01),
.out_ack0 (ack01),
.out_bop0 (),
.out_eop0 (),
.out_rdy0 (1'b1),
.out_bypass0 (bypass01),
.out_data1 (),
.out_pkt_route1 (),
.out_wr1 (),
.out_req1 (),
.out_ack1 (),
.out_bop1 (),
.out_eop1 (),
.out_rdy1 (),
.out_bypass1 (),
.out_data2 (),
.out_pkt_route2 (),
.out_wr2 (),
.out_req2 (),
.out_ack2 (),
.out_bop2 (),
.out_eop2 (),
.out_rdy2 (),
.out_bypass2 (),
.out_data3 (pg_out_data0),
.out_pkt_route3 (pg_out_pkt_route0),
.out_wr3 (pg_out_wr0),
.out_req3 (pg_out_req0),
.out_ack3 (pg_out_ack0),
.out_bop3 (pg_out_bop0),
.out_eop3 (pg_out_eop0),
.out_rdy3 (pg_out_rdy0),
.out_bypass3 (),
//Separate the monitor
//.four_bit_hash_output(four_bit_hash_output0),
//.pc_input_hash_wire(pc_input_hash_wire0),
//.new_inst_signal(new_inst_signal0),
.cam_we(cam_we),
.cam_wr_addr(cam_wr_addr),
.cam_din(cam_din),
//.cam_wr_ack(cam_wr_ack),
.out_four_bit_hash(four_bit_hash_output_0),
.out_new_inst_signal(new_inst_signal[0]),
.in_packet_drop_signal(packet_drop_signal[0]),
.out_processor_reset_seq(processor_reset_seq[0]),
.out_sp_pkt_done(sp_pkt_done[0]),
.out_sp_interrupt_wire(sp_interrupt_wire[0]),
.out_ack_reset(out_ack_reset[0])
);
CAM_monitor security_mon_0
(
.clk(clk),
.reset(reset),
.four_bit_hash(four_bit_hash_output_0),
.new_inst_signal(new_inst_signal[0]),
.packet_drop_signal(packet_drop_signal[0]),
.cam_we(cam_we),
.cam_wr_addr(cam_wr_addr),
.cam_din(cam_din),
.proc_ack(sp_interrupt_wire[0]),
.out_ack_reset(out_ack_reset[0]),
.cam_wr_ack(),
.processor_reset_seq (processor_reset_seq[0]),
.packet_done(sp_pkt_done[0])
);
CAM_monitor security_mon_1
(
.clk(clk),
.reset(reset),
.four_bit_hash(four_bit_hash_output_1),
.new_inst_signal(new_inst_signal[1]),
.packet_drop_signal(packet_drop_signal[1]),
.cam_we(cam_we),
.cam_wr_addr(cam_wr_addr),
.cam_din(cam_din),
.proc_ack(sp_interrupt_wire[1]),
.out_ack_reset(out_ack_reset[1]),
.cam_wr_ack(),
.processor_reset_seq (processor_reset_seq[1]),
.packet_done(sp_pkt_done[1])
);
wire packet_drop_signal_2_cm;
wire packet_drop_signal_2_ipv4;
wire out_ack_reset_2_cm;
wire out_ack_reset_2_ipv4;
CAM_monitor security_mon_2
(
.clk(clk),
.reset(reset),
.four_bit_hash(four_bit_hash_output_2),
.new_inst_signal(new_inst_signal[2]),
.packet_drop_signal(packet_drop_signal_2_cm),
.cam_we(cam_we),
.cam_wr_addr(cam_wr_addr),
.cam_din(cam_din),
.proc_ack(sp_interrupt_wire[2]),
.out_ack_reset(out_ack_reset_2_cm),
.cam_wr_ack(),
.processor_reset_seq (processor_reset_seq[2]),
.packet_done(sp_pkt_done[2])
);
CAM_monitor security_mon_3
(
.clk(clk),
.reset(reset),
.four_bit_hash(),
.new_inst_signal(),
.packet_drop_signal(),
.cam_we(),
.cam_wr_addr(),
.cam_din(),
.proc_ack(),
.out_ack_reset(),
.cam_wr_ack(),
.processor_reset_seq (),
.packet_done()
);
CAM_monitor_ipv4 security_mon_4
(
.clk(clk),
.reset(reset),
.four_bit_hash(four_bit_hash_output_2),
.new_inst_signal(new_inst_signal[2]),
.packet_drop_signal(packet_drop_signal_2_ipv4),
.cam_we(cam_we),
.cam_wr_addr(cam_wr_addr),
.cam_din(cam_din),
.proc_ack(sp_interrupt_wire[2]),
.out_ack_reset(out_ack_reset_2_ipv4),
.cam_wr_ack(),
.processor_reset_seq (processor_reset_seq[2]),
.packet_done(sp_pkt_done[2])
);
assign out_ack_reset[2] = (ppu3_sel) ? out_ack_reset_2_cm : out_ack_reset_2_ipv4;
assign packet_drop_signal[2] = (ppu3_sel) ? packet_drop_signal_2_cm : packet_drop_signal_2_ipv4;
CAM_monitor_ipv4 security_mon_5
(
.clk(clk),
.reset(reset),
.four_bit_hash(four_bit_hash_output_3),
.new_inst_signal(new_inst_signal[3]),
.packet_drop_signal(packet_drop_signal[3]),
.cam_we(cam_we),
.cam_wr_addr(cam_wr_addr),
.cam_din(cam_din),
.proc_ack(sp_interrupt_wire[3]),
.out_ack_reset(out_ack_reset[3]),
.cam_wr_ack(),
.processor_reset_seq (processor_reset_seq[3]),
.packet_done(sp_pkt_done[3])
);
router_op_lut_regs_non_cntr //#(
// .NUM_QUEUES (NUM_QUEUES),
// .ARP_LUT_DEPTH_BITS (ARP_LUT_DEPTH_BITS),
// .LPM_LUT_DEPTH_BITS (LPM_LUT_DEPTH_BITS),
//.FILTER_DEPTH_BITS (FILTER_DEPTH_BITS),
//.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH)
// )
router_op_lut_regs_non_cntr (
.reg_req_in (reg_req_in),
.reg_ack_in (reg_ack_in),
.reg_rd_wr_L_in (reg_rd_wr_L_in),
.reg_addr_in (reg_addr_in),
.reg_data_in (reg_data_in),
.reg_src_in (reg_src_in),
// .reg_req_out (reg_req_out),
// .reg_ack_out (reg_ack_out),
// .reg_rd_wr_L_out (reg_rd_wr_L_out),
// .reg_addr_out (reg_addr_out),
// .reg_data_out (reg_data_out),
// .reg_src_out (reg_src_out),
// --- interface to dest_ip_filter
.dest_ip_filter_rd_addr (), // address in table to read
.dest_ip_filter_rd_req (), // request a read
.dest_ip_filter_rd_ip (), // ip to match in the CAM
.dest_ip_filter_rd_ack (), // pulses high
.dest_ip_filter_wr_addr (cam_wr_addr),
.dest_ip_filter_wr_req (cam_we),
.dest_ip_filter_wr_ip (cam_din), // data to match in the CAM
.dest_ip_filter_wr_ack (cam_wr_ack),
// --- eth_parser
.clk (clk),
.reset (reset)
);
ppu ppu1(
.clk (clk),
.core_sp_clk (core_sp_clk),
.reset (reset),
.in_data0 (),
.in_pkt_route0 (),
.in_wr0 (),
.in_req0 (),
.in_ack0 (),
.in_bypass0 (),
.in_data1 (fc_out_data1),
.in_pkt_route1 (fc_out_pkt_route1),
.in_wr1 (fc_out_wr1),
.in_req1 (fc_out_req1),
.in_ack1 (fc_out_ack1),
.in_bypass1 (fc_out_bypass1),
.in_protocol1(fc_out_protocol1),
.in_data2 (),
.in_pkt_route2 (),
.in_wr2 (),
.in_req2 (),
.in_ack2 (),
.in_bypass2 (),
.in_data3 (),
.in_pkt_route3 (),
.in_wr3 (),
.in_req3 (),
.in_ack3 (),
.in_bypass3 (),
.out_data0 (),
.out_pkt_route0 (),
.out_wr0 (),
.out_req0 (),
.out_ack0 (),
.out_bop0 (),
.out_eop0 (),
.out_rdy0 (),
.out_bypass0 (),
.out_data1 (),
.out_pkt_route1 (),
.out_wr1 (),
.out_req1 (),
.out_ack1 (),
.out_bop1 (),
.out_eop1 (),
.out_rdy1 (),
.out_bypass1 (),
.out_data2 (),
.out_pkt_route2 (),
.out_wr2 (),
.out_req2 (),
.out_ack2 (),
.out_bop2 (),
.out_eop2 (),
.out_rdy2 (),
.out_bypass2 (),
.out_data3 (pg_out_data1),
.out_pkt_route3 (pg_out_pkt_route1),
.out_wr3 (pg_out_wr1),
.out_req3 (pg_out_req1),
.out_ack3 (pg_out_ack1),
.out_bop3 (pg_out_bop1),
.out_eop3 (pg_out_eop1),
.out_rdy3 (pg_out_rdy1),
.out_bypass3 (),
//Separate the monitor
//.four_bit_hash_output(four_bit_hash_output0),
//.pc_input_hash_wire(pc_input_hash_wire0),
//.new_inst_signal(new_inst_signal0),
.cam_we(cam_we),
.cam_wr_addr(cam_wr_addr),
.cam_din(cam_din),
//.cam_wr_ack(cam_wr_ack),
.out_four_bit_hash(four_bit_hash_output_1),
.out_new_inst_signal(new_inst_signal[1]),
.in_packet_drop_signal(packet_drop_signal[1]),
.out_processor_reset_seq(processor_reset_seq[1]),
.out_sp_pkt_done(sp_pkt_done[1]),
.out_sp_interrupt_wire(sp_interrupt_wire[1]),
.out_ack_reset(out_ack_reset[1])
);
ppu ppu2(
.clk (clk),
.core_sp_clk (core_sp_clk),
.reset (reset),
.TRIG_IS (TRIG_IS2),
.in_data0 (),
.in_pkt_route0 (),
.in_wr0 (),
.in_req0 (),
.in_ack0 (),
.in_bypass0 (),
.in_data1 (fc_out_data2),
.in_pkt_route1 (fc_out_pkt_route2),
.in_wr1 (fc_out_wr2),
.in_req1 (fc_out_req2),
.in_ack1 (fc_out_ack2),
.in_bypass1 (fc_out_bypass2),
.in_protocol1(fc_out_protocol2),
.in_data2 (),
.in_pkt_route2 (),
.in_wr2 (),
.in_req2 (),
.in_ack2 (),
.in_bypass2 (),
.in_data3 (),
.in_pkt_route3 (),
.in_wr3 (),
.in_req3 (),
.in_ack3 (),
.in_bypass3 (),
.out_data0 (),
.out_pkt_route0 (),
.out_wr0 (),
.out_req0 (),
.out_ack0 (),
.out_bop0 (),
.out_eop0 (),
.out_rdy0 (),
.out_bypass0 (),
.out_data1 (),
.out_pkt_route1 (),
.out_wr1 (),
.out_req1 (),
.out_ack1 (),
.out_bop1 (),
.out_eop1 (),
.out_rdy1 (),
.out_bypass1 (),
.out_data2 (),
.out_pkt_route2 (),
.out_wr2 (),
.out_req2 (),
.out_ack2 (),
.out_bop2 (),
.out_eop2 (),
.out_rdy2 (),
.out_bypass2 (),
.out_data3 (pg_out_data2),
.out_pkt_route3 (pg_out_pkt_route2),
.out_wr3 (pg_out_wr2),
.out_req3 (pg_out_req2),
.out_ack3 (pg_out_ack2),
.out_bop3 (pg_out_bop2),
.out_eop3 (pg_out_eop2),
.out_rdy3 (pg_out_rdy2),
.out_bypass3 (),
//Separate the monitor
//.four_bit_hash_output(four_bit_hash_output0),
//.pc_input_hash_wire(pc_input_hash_wire0),
//.new_inst_signal(new_inst_signal0),
.cam_we(cam_we),
.cam_wr_addr(cam_wr_addr),
.cam_din(cam_din),
//.cam_wr_ack(cam_wr_ack),
.out_four_bit_hash(four_bit_hash_output_2),
.out_new_inst_signal(new_inst_signal[2]),
.in_packet_drop_signal(packet_drop_signal[2]),
.out_processor_reset_seq(processor_reset_seq[2]),
.out_sp_pkt_done(sp_pkt_done[2]),
.out_sp_interrupt_wire(sp_interrupt_wire[2]),
.out_ack_reset(out_ack_reset[2])
);
ppu ppu3(
.clk (clk),
.core_sp_clk (core_sp_clk),
.reset (reset),
.in_data0 (),
.in_pkt_route0 (),
.in_wr0 (),
.in_req0 (),
.in_ack0 (),
.in_bypass0 (),
.in_data1 (fc_out_data3),
.in_pkt_route1 (fc_out_pkt_route3),
.in_wr1 (fc_out_wr3),
.in_req1 (fc_out_req3),
.in_ack1 (fc_out_ack3),
.in_bypass1 (fc_out_bypass3),
.in_protocol1(fc_out_protocol3),
.in_data2 (),
.in_pkt_route2 (),
.in_wr2 (),
.in_req2 (),
.in_ack2 (),
.in_bypass2 (),
.in_data3 (),
.in_pkt_route3 (),
.in_wr3 (),
.in_req3 (),
.in_ack3 (),
.in_bypass3 (),
.out_data0 (),
.out_pkt_route0 (),
.out_wr0 (),
.out_req0 (),
.out_ack0 (),
.out_bop0 (),
.out_eop0 (),
.out_rdy0 (),
.out_bypass0 (),
.out_data1 (),
.out_pkt_route1 (),
.out_wr1 (),
.out_req1 (),
.out_ack1 (),
.out_bop1 (),
.out_eop1 (),
.out_rdy1 (),
.out_bypass1 (),
.out_data2 (),
.out_pkt_route2 (),
.out_wr2 (),
.out_req2 (),
.out_ack2 (),
.out_bop2 (),
.out_eop2 (),
.out_rdy2 (),
.out_bypass2 (),
.out_data3 (pg_out_data3),
.out_pkt_route3 (pg_out_pkt_route3),
.out_wr3 (pg_out_wr3),
.out_req3 (pg_out_req3),
.out_ack3 (pg_out_ack3),
.out_bop3 (pg_out_bop3),
.out_eop3 (pg_out_eop3),
.out_rdy3 (pg_out_rdy3),
.out_bypass3 (),
//Separate the monitor
//.four_bit_hash_output(four_bit_hash_output0),
//.pc_input_hash_wire(pc_input_hash_wire0),
//.new_inst_signal(new_inst_signal0),
.cam_we(cam_we),
.cam_wr_addr(cam_wr_addr),
.cam_din(cam_din),
//.cam_wr_ack(cam_wr_ack),
.out_four_bit_hash(four_bit_hash_output_3),
.out_new_inst_signal(new_inst_signal[3]),
.in_packet_drop_signal(packet_drop_signal[3]),
.out_processor_reset_seq(processor_reset_seq[3]),
.out_sp_pkt_done(sp_pkt_done[3]),
.out_sp_interrupt_wire(sp_interrupt_wire[3]),
.out_ack_reset(out_ack_reset[3])
);
out_arbiter oa(
.out_data (out_data),
.out_ctrl (out_ctrl),
.out_wr (out_wr),
.out_rdy (out_rdy),
.in_data0 (pg_out_data0),
.in_wr0 (pg_out_wr0),
.in_req0 (pg_out_req0),
.in_ack0 (pg_out_ack0),
.in_bop0 (pg_out_bop0),
.in_eop0 (pg_out_eop0),
.in_outrdy0 (pg_out_rdy0),
.in_data1 (pg_out_data1),
.in_wr1 (pg_out_wr1),
.in_req1 (pg_out_req1),
.in_ack1 (pg_out_ack1),
.in_bop1 (pg_out_bop1),
.in_eop1 (pg_out_eop1),
.in_outrdy1 (pg_out_rdy1),
.in_data2 (pg_out_data2),
.in_wr2 (pg_out_wr2),
.in_req2 (pg_out_req2),
.in_ack2 (pg_out_ack2),
.in_bop2 (pg_out_bop2),
.in_eop2 (pg_out_eop2),
.in_outrdy2 (pg_out_rdy2),
.in_data3 (pg_out_data3),
.in_wr3 (pg_out_wr3),
.in_req3 (pg_out_req3),
.in_ack3 (pg_out_ack3),
.in_bop3 (pg_out_bop3),
.in_eop3 (pg_out_eop3),
.in_outrdy3 (pg_out_rdy3),
.clk (clk),
.reset (reset)
);
wire [35:0] CONTROL0;
wire [239:0] TRIG0;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:00:03 05/22/2014
// Design Name:
// Module Name: cpu_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CPU_top(
input wire stp,rst,clk,
input wire [1:0] dptype,
input wire [4:0] regselect,
output wire exec,
output wire [5:0] initype,
output wire [3:0] node,
output wire [7:0] segment
);
wire clock;
wire memclock;
wire resetn;
wire [31:0] dpdata;
reg [15:0] digit,count=0;
wire [7:0] pc;
wire [31:0] inst;
wire [31:0] ealu;
wire [31:0] malu;
wire [31:0] walu;
wire [7:0] bpc,jpc,npc,dpc4,epc4,pc4;
wire [31:0] ins,da,db,ea,eb,dimm,eimm; //instÖظ´£¿
wire [31:0] mb,mmo,wmo,wdi;
wire [4:0] drn,ern0,ern,mrn,wrn,dsa,esa;
wire [3:0] daluc,ealuc;
wire [1:0] pcsource;
wire wpcir;
wire dwreg,dm2reg,dwmem,daluimm,dshift,djal;//id stage
wire ewreg,em2reg,ewmem,ealuimm,eshift,ejal;//exe stage
wire mwreg,mm2reg,mwmem;//mem stage
wire wwreg,wm2reg;//wb stage
pbdebounce p0(clk,stp,clock);
assign memclock=clk;
pbdebounce p1(clk,rst,resetn);
always @(posedge clock) count=count+1;
pipepc prog_cnt(npc,wpcir,clock,resetn,pc);
pipeif if_stage(pcsource,pc,bpc,da,jpc,npc,pc4,ins);
pipeir inst_reg(pc4,ins,wpcir,clock,resetn,dpc4,inst);
pipeid id_stage(mwreg,mrn,ern,ewreg,em2reg,mm2reg,dpc4,inst,wrn,wdi,ealu,malu,mmo,wwreg,clock,resetn,bpc,jpc,pcsource,wpcir,dwreg,dm2reg,dwmem,daluc,daluimm,da,db,dimm,drn,dshift,djal,dsa,regselect,dpdata);
pipedereg de_reg(dwreg,dm2reg,dwmem,daluc,daluimm,da,db,dimm,drn,dshift,djal,dpc4,dsa,clock,resetn,ewreg,em2reg,ewmem,ealuc,ealuimm,ea,eb,eimm,ern0,eshift,ejal,epc4,esa);
pipeexe exe_stage(ealuc,ealuimm,ea,eb,eimm,esa,eshift,ern0,epc4,ejal,ern,ealu);
pipeemreg em_reg(ewreg,em2reg,ewmem,ealu,eb,ern,clock,resetn,mwreg,mm2reg,mwmem,malu,mb,mrn);
pipemem mem_stage(mwmem,malu,mb,clock,memclock,mmo);
pipemwreg mw_reg(mwreg,mm2reg,mmo,malu,mrn,clock,resetn,wwreg,wm2reg,wmo,walu,wrn);
mux2x32 wb_stage(walu,wmo,wm2reg,wdi);
display dp(clk,digit,node,segment);
always @* begin
case (dptype)
2'b00:digit<=dpdata[15:0];
2'b01:digit<=dpdata[31:16];
2'b10:digit<={8'b0,pc[7:0]};
2'b11:digit<=count;
endcase
end
assign exec=clock;
assign initype=inst[31:26];
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clock.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clock (
inclk0,
c0);
input inclk0;
output c0;
wire [4:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 5,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clock",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clock.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clock_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: wbuart.v
// {{{
// Project: wbuart32, a full featured UART with simulator
//
// Purpose: Unlilke wbuart-insert.v, this is a full blown wishbone core
// with integrated FIFO support to support the UART transmitter
// and receiver found within here. As a result, it's usage may be
// heavier on the bus than the insert, but it may also be more useful.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2015-2021, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
// }}}
// License: GPL, v3, as defined and found on www.gnu.org,
// {{{
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
// }}}
// `define USE_LITE_UART
module wbuart #(
// {{{
// 4MB 8N1, when using 100MHz clock
parameter [30:0] INITIAL_SETUP = 31'd25,
parameter [3:0] LGFLEN = 4,
parameter [0:0] HARDWARE_FLOW_CONTROL_PRESENT = 1'b1,
// Perform a simple/quick bounds check on the log FIFO length,
// to make sure its within the bounds we can support with our
// current interface.
localparam [3:0] LCLLGFLEN = (LGFLEN > 4'ha)? 4'ha
: ((LGFLEN < 4'h2) ? 4'h2 : LGFLEN)
// }}}
) (
// {{{
input wire i_clk, i_reset,
// Wishbone inputs
input wire i_wb_cyc,
input wire i_wb_stb, i_wb_we,
input wire [1:0] i_wb_addr,
input wire [31:0] i_wb_data,
input wire [3:0] i_wb_sel,
output wire o_wb_stall,
output reg o_wb_ack,
output reg [31:0] o_wb_data,
//
input wire i_uart_rx,
output wire o_uart_tx,
input wire i_cts_n,
output reg o_rts_n,
output wire o_uart_rx_int, o_uart_tx_int,
o_uart_rxfifo_int, o_uart_txfifo_int
// }}}
);
localparam [1:0] UART_SETUP = 2'b00,
UART_FIFO = 2'b01,
UART_RXREG = 2'b10,
UART_TXREG = 2'b11;
// Register and signal declarations
// {{{
wire tx_busy;
reg [30:0] uart_setup;
// Receiver
wire rx_stb, rx_break, rx_perr, rx_ferr, ck_uart;
wire [7:0] rx_uart_data;
reg rx_uart_reset;
// Receive FIFO
wire rx_empty_n, rx_fifo_err;
wire [7:0] rxf_wb_data;
wire [15:0] rxf_status;
reg rxf_wb_read;
//
wire [(LCLLGFLEN-1):0] check_cutoff;
reg r_rx_perr, r_rx_ferr;
wire [31:0] wb_rx_data;
// The transmitter
wire tx_empty_n, txf_err, tx_break;
wire [7:0] tx_data;
wire [15:0] txf_status;
reg txf_wb_write, tx_uart_reset;
reg [7:0] txf_wb_data;
//
wire [31:0] wb_tx_data;
wire [31:0] wb_fifo_data;
reg [1:0] r_wb_addr;
reg r_wb_ack;
// }}}
// uart_setup
// {{{
// The UART setup parameters: bits per byte, stop bits, parity, and
// baud rate are all captured within this uart_setup register.
//
initial uart_setup = INITIAL_SETUP
| ((HARDWARE_FLOW_CONTROL_PRESENT==1'b0)? 31'h40000000 : 0);
always @(posedge i_clk)
// Under wishbone rules, a write takes place any time i_wb_stb
// is high. If that's the case, and if the write was to the
// setup address, then set us up for the new parameters.
if ((i_wb_stb)&&(i_wb_addr == UART_SETUP)&&(i_wb_we))
begin
if (i_wb_sel[0])
uart_setup[7:0] <= i_wb_data[7:0];
if (i_wb_sel[1])
uart_setup[15:8] <= i_wb_data[15:8];
if (i_wb_sel[2])
uart_setup[23:16] <= i_wb_data[23:16];
if (i_wb_sel[3])
uart_setup[30:24] <= { (i_wb_data[30])
||(!HARDWARE_FLOW_CONTROL_PRESENT),
i_wb_data[29:24] };
end
// }}}
////////////////////////////////////////////////////////////////////////
//
// The UART receiver
// {{{
////////////////////////////////////////////////////////////////////////
//
//
// The receiver itself
// {{{
// Here's our UART receiver. Basically, it accepts our setup wires,
// the UART input, a clock, and a reset line, and produces outputs:
// a stb (true when new data is ready), and an 8-bit data out value
// valid when stb is high.
`ifdef USE_LITE_UART
// {{{
rxuartlite #(.CLOCKS_PER_BAUD(INITIAL_SETUP[23:0]))
rx(i_clk, i_uart_rx, rx_stb, rx_uart_data);
assign rx_break = 1'b0;
assign rx_perr = 1'b0;
assign rx_ferr = 1'b0;
assign ck_uart = 1'b0;
// }}}
`else
// {{{
// The full receiver also produces a break value (true during a break
// cond.), and parity/framing error flags--also valid when stb is true.
rxuart #(.INITIAL_SETUP(INITIAL_SETUP)) rx(i_clk, (i_reset)||(rx_uart_reset),
uart_setup, i_uart_rx,
rx_stb, rx_uart_data, rx_break,
rx_perr, rx_ferr, ck_uart);
// The real trick is ... now that we have this extra data, what do we do
// with it?
// }}}
`endif
// }}}
// The receive FIFO
// {{{
// We place new arriving data into a receiver FIFO.
//
// And here's the FIFO proper.
//
// Note that the FIFO will be cleared upon any reset: either if there's
// a UART break condition on the line, the receiver is in reset, or an
// external reset is issued.
//
// The FIFO accepts strobe and data from the receiver.
// We issue another wire to it (rxf_wb_read), true when we wish to read
// from the FIFO, and we get our data in rxf_wb_data. The FIFO outputs
// four status-type values: 1) is it non-empty, 2) is the FIFO over half
// full, 3) a 16-bit status register, containing info regarding how full
// the FIFO truly is, and 4) an error indicator.
ufifo #(.LGFLEN(LCLLGFLEN), .RXFIFO(1))
rxfifo(i_clk, (i_reset)||(rx_break)||(rx_uart_reset),
rx_stb, rx_uart_data,
rx_empty_n,
rxf_wb_read, rxf_wb_data,
rxf_status, rx_fifo_err);
// }}}
assign o_uart_rxfifo_int = rxf_status[1];
// We produce four interrupts. One of the receive interrupts indicates
// whether or not the receive FIFO is non-empty. This should wake up
// the CPU.
assign o_uart_rx_int = rxf_status[0];
// o_rts_n
// {{{
// The clear to send line, which may be ignored, but which we set here
// to be true any time the FIFO has fewer than N-2 items in it.
// Why not N-1? Because at N-1 we are totally full, but already so full
// that if the transmit end starts sending we won't have a location to
// receive it. (Transmit might've started on the next character by the
// time we set this--thus we need to set it to one, one character before
// necessary).
assign check_cutoff = -3;
always @(posedge i_clk)
o_rts_n <= ((HARDWARE_FLOW_CONTROL_PRESENT)
&&(!uart_setup[30])
&&(rxf_status[(LCLLGFLEN+1):2] > check_cutoff));
// }}}
// rxf_wb_read
// {{{
// If the bus requests that we read from the receive FIFO, we need to
// tell this to the receive FIFO. Note that because we are using a
// clock here, the output from the receive FIFO will necessarily be
// delayed by an extra clock.
initial rxf_wb_read = 1'b0;
always @(posedge i_clk)
rxf_wb_read <= (i_wb_stb)&&(i_wb_addr[1:0]== UART_RXREG)
&&(!i_wb_we);
// }}}
// r_rx_perr, r_rx_ferr -- parity and framing errors
// {{{
// Now, let's deal with those RX UART errors: both the parity and frame
// errors. As you may recall, these are valid only when rx_stb is
// valid, so we need to hold on to them until the user reads them via
// a UART read request..
initial r_rx_perr = 1'b0;
initial r_rx_ferr = 1'b0;
always @(posedge i_clk)
if ((rx_uart_reset)||(rx_break))
begin
// Clear the error
r_rx_perr <= 1'b0;
r_rx_ferr <= 1'b0;
end else if ((i_wb_stb)
&&(i_wb_addr[1:0]== UART_RXREG)&&(i_wb_we))
begin
// Reset the error lines if a '1' is ever written to
// them, otherwise leave them alone.
//
if (i_wb_sel[1])
begin
r_rx_perr <= (r_rx_perr)&&(~i_wb_data[9]);
r_rx_ferr <= (r_rx_ferr)&&(~i_wb_data[10]);
end
end else if (rx_stb)
begin
// On an rx_stb, capture any parity or framing error
// indications. These aren't kept with the data rcvd,
// but rather kept external to the FIFO. As a result,
// if you get a parity or framing error, you will never
// know which data byte it was associated with.
// For now ... that'll work.
r_rx_perr <= (r_rx_perr)||(rx_perr);
r_rx_ferr <= (r_rx_ferr)||(rx_ferr);
end
// }}}
// rx_uart_reset
// {{{
initial rx_uart_reset = 1'b1;
always @(posedge i_clk)
if ((i_reset)||((i_wb_stb)&&(i_wb_addr[1:0]== UART_SETUP)&&(i_wb_we)))
// The receiver reset, always set on a master reset
// request.
rx_uart_reset <= 1'b1;
else if ((i_wb_stb)&&(i_wb_addr[1:0]== UART_RXREG)&&(i_wb_we)&&i_wb_sel[1])
// Writes to the receive register will command a receive
// reset anytime bit[12] is set.
rx_uart_reset <= i_wb_data[12];
else
rx_uart_reset <= 1'b0;
// }}}
// wb_rx_data
// {{{
// Finally, we'll construct a 32-bit value from these various wires,
// to be returned over the bus on any read. These include the data
// that would be read from the FIFO, an error indicator set upon
// reading from an empty FIFO, a break indicator, and the frame and
// parity error signals.
assign wb_rx_data = { 16'h00,
3'h0, rx_fifo_err,
rx_break, rx_ferr, r_rx_perr, !rx_empty_n,
rxf_wb_data};
// }}}
// }}}
////////////////////////////////////////////////////////////////////////
//
// The UART transmitter
// {{{
////////////////////////////////////////////////////////////////////////
//
//
// txf_wb_write, txf_wb_data
// {{{
// Unlike the receiver which goes from RXUART -> UFIFO -> WB, the
// transmitter basically goes WB -> UFIFO -> TXUART. Hence, to build
// support for the transmitter, we start with the command to write data
// into the FIFO. In this case, we use the act of writing to the
// UART_TXREG address as our indication that we wish to write to the
// FIFO. Here, we create a write command line, and latch the data for
// the extra clock that it'll take so that the command and data can be
// both true on the same clock.
initial txf_wb_write = 1'b0;
always @(posedge i_clk)
begin
txf_wb_write <= (i_wb_stb)&&(i_wb_addr == UART_TXREG)
&&(i_wb_we)&&(i_wb_sel[0]);
txf_wb_data <= i_wb_data[7:0];
end
// }}}
// Transmit FIFO
// {{{
// Most of this is just wire management. The TX FIFO is identical in
// implementation to the RX FIFO (theyre both UFIFOs), but the TX
// FIFO is fed from the WB and read by the transmitter. Some key
// differences to note: we reset the transmitter on any request for a
// break. We read from the FIFO any time the UART transmitter is idle.
// and ... we just set the values (above) for controlling writing into
// this.
ufifo #(.LGFLEN(LGFLEN), .RXFIFO(0))
txfifo(i_clk, (tx_break)||(tx_uart_reset),
txf_wb_write, txf_wb_data,
tx_empty_n,
(!tx_busy)&&(tx_empty_n), tx_data,
txf_status, txf_err);
// }}}
// Transmit interrupts
// {{{
// Let's create two transmit based interrupts from the FIFO for the CPU.
// The first will be true any time the FIFO has at least one open
// position within it.
assign o_uart_tx_int = txf_status[0];
// The second will be true any time the FIFO is less than half
// full, allowing us a change to always keep it (near) fully
// charged.
assign o_uart_txfifo_int = txf_status[1];
// }}}
// Break logic
`ifndef USE_LITE_UART
// {{{
// A break in a UART controller is any time the UART holds the line
// low for an extended period of time. Here, we capture the wb_data[9]
// wire, on writes, as an indication we wish to break. As long as you
// write unsigned characters to the interface, this will never be true
// unless you wish it to be true. Be aware, though, writing a valid
// value to the interface will bring it out of the break condition.
reg r_tx_break;
initial r_tx_break = 1'b0;
always @(posedge i_clk)
if (i_reset)
r_tx_break <= 1'b0;
else if ((i_wb_stb)&&(i_wb_addr[1:0]== UART_TXREG)&&(i_wb_we)
&&(i_wb_sel[1]))
r_tx_break <= i_wb_data[9];
assign tx_break = r_tx_break;
// }}}
`else
// {{{
assign tx_break = 1'b0;
// }}}
`endif
// TX-Reset logic
// {{{{
// This is nearly identical to the RX reset logic above. Basically,
// any time someone writes to bit [12] the transmitter will go through
// a reset cycle. Keep bit [12] low, and everything will proceed as
// normal.
initial tx_uart_reset = 1'b1;
always @(posedge i_clk)
if((i_reset)||((i_wb_stb)&&(i_wb_addr == UART_SETUP)&&(i_wb_we)))
tx_uart_reset <= 1'b1;
else if ((i_wb_stb)&&(i_wb_addr[1:0]== UART_TXREG)&&(i_wb_we) && i_wb_sel[1])
tx_uart_reset <= i_wb_data[12];
else
tx_uart_reset <= 1'b0;
// }}}
// The actuall transmitter itself
`ifdef USE_LITE_UART
// {{{
txuartlite #(.CLOCKS_PER_BAUD(INITIAL_SETUP[23:0])) tx(i_clk, (tx_empty_n), tx_data,
o_uart_tx, tx_busy);
// }}}
`else
// cts_n
// {{{
wire cts_n;
assign cts_n = (HARDWARE_FLOW_CONTROL_PRESENT)&&(i_cts_n);
// }}}
// The *full* transmitter impleemntation
// {{{
// Finally, the UART transmitter module itself. Note that we haven't
// connected the reset wire. Transmitting is as simple as setting
// the stb value (here set to tx_empty_n) and the data. When these
// are both set on the same clock that tx_busy is low, the transmitter
// will move on to the next data byte. Really, the only thing magical
// here is that tx_empty_n wire--thus, if there's anything in the FIFO,
// we read it here. (You might notice above, we register a read any
// time (tx_empty_n) and (!tx_busy) are both true---the condition for
// starting to transmit a new byte.)
txuart #(.INITIAL_SETUP(INITIAL_SETUP)) tx(i_clk, 1'b0, uart_setup,
r_tx_break, (tx_empty_n), tx_data,
cts_n, o_uart_tx, tx_busy);
// }}}
`endif
// wb_tx_data
// {{{
// Now that we are done with the chain, pick some wires for the user
// to read on any read of the transmit port.
//
// This port is different from reading from the receive port, since
// there are no side effects. (Reading from the receive port advances
// the receive FIFO, here only writing to the transmit port advances the
// transmit FIFO--hence the read values are free for ... whatever.)
// We choose here to provide information about the transmit FIFO
// (txf_err, txf_half_full, txf_full_n), information about the current
// voltage on the line (o_uart_tx)--and even the voltage on the receive
// line (ck_uart), as well as our current setting of the break and
// whether or not we are actively transmitting.
assign wb_tx_data = { 16'h00,
i_cts_n, txf_status[1:0], txf_err,
ck_uart, o_uart_tx, tx_break, (tx_busy|txf_status[0]),
(tx_busy|txf_status[0])?txf_wb_data:8'b00};
// }}}
// }}}
////////////////////////////////////////////////////////////////////////
//
// Bus / register handling
// {{{
////////////////////////////////////////////////////////////////////////
//
//
// wb_fifo_data
// {{{
// Each of the FIFO's returns a 16 bit status value. This value tells
// us both how big the FIFO is, as well as how much of the FIFO is in
// use. Let's merge those two status words together into a word we
// can use when reading about the FIFO.
assign wb_fifo_data = { txf_status, rxf_status };
// }}}
// r_wb_addr
// {{{
// You may recall from above that reads take two clocks. Hence, we
// need to delay the address decoding for a clock until the data is
// ready. We do that here.
always @(posedge i_clk)
r_wb_addr <= i_wb_addr;
// }}}
// r_wb_ack
// {{{
initial r_wb_ack = 1'b0;
always @(posedge i_clk) // We'll ACK in two clocks
r_wb_ack <= i_wb_stb;
// }}}
// o_wb_ack
// {{{
initial o_wb_ack = 1'b0;
always @(posedge i_clk) // Okay, time to set the ACK
o_wb_ack <= i_wb_cyc && r_wb_ack;
// }}}
// o_wb_data
// {{{
// Finally, set the return data. This data must be valid on the same
// clock o_wb_ack is high. On all other clocks, it is irrelelant--since
// no one cares, no one is reading it, it gets lost in the mux in the
// interconnect, etc. For this reason, we can just simplify our logic.
always @(posedge i_clk)
casez(r_wb_addr)
UART_SETUP: o_wb_data <= { 1'b0, uart_setup };
UART_FIFO: o_wb_data <= wb_fifo_data;
UART_RXREG: o_wb_data <= wb_rx_data;
UART_TXREG: o_wb_data <= wb_tx_data;
endcase
// }}}
// o_wb_stall
// {{{
// This device never stalls. Sure, it takes two clocks, but they are
// pipelined, and nothing stalls that pipeline. (Creates FIFO errors,
// perhaps, but doesn't stall the pipeline.) Hence, we can just
// set this value to zero.
assign o_wb_stall = 1'b0;
// }}}
// }}}
// Make verilator happy
// {{{
// verilator lint_off UNUSED
wire unused;
assign unused = &{ 1'b0, i_wb_data[31] };
// verilator lint_on UNUSED
// }}}
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD2_FUNCTIONAL_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD2_FUNCTIONAL_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd2 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD2_FUNCTIONAL_V |
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: sram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ethernet_rx_buffer (
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [9:0] rdaddress;
input rden;
input [9:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.rden_b (rden),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
// Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sram_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sram_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// Lab 4
// Created by David Tran
// Last Modified 02-05-2014
// extras
`timescale 1 ms /1 us
`include "full_adder.v"
// Testbench Module
module full_adder_tb (A, B, D);
output A, B, D;
reg A, B, D;
wire S, C;
reg t_A [5000:0];
reg t_B [5000:0];
reg t_D [5000:0];
reg t_clock;
reg [31:0] vectornum; //Values from 0 -> 2^31
integer fp;
full_adder I1 (A, B, D, S, C);
//initial #1000 $finish;
initial
begin
t_clock=0;
forever #5 t_clock=~t_clock;
end
initial
begin
$readmemb("./bit_str_a_0.txt",t_A);
$readmemb("./bit_str_a_1.txt",t_B);
$readmemb("./bit_str_a_2.txt",t_D);
vectornum=0; // Set test vector 0
end
always @(negedge t_clock)
begin
A<=t_A[vectornum];
B<=t_B[vectornum];
D<=t_D[vectornum];
vectornum<=vectornum+1;
end
initial
begin
fp=$fopen("full_adder_tb.out");
//$fmonitor(fp, "time=%0d", $time,, "A=%b B=%b D=%b S=%b C=%b", A, B, D, S, C);
$monitor("time=%0d", $time,, "A=%b B=%b D=%b S=%b C=%b", A, B, D, S, C);
#1000
$fclose(fp);
$finish;
end
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* SRL-based FIFO (Tds ~ 100 ps)
*/
module srl_fifo #
(
parameter WIDTH = 8,
parameter DEPTH = 16
)
(
input wire clk,
input wire rst,
input wire write_en,
input wire [WIDTH-1:0] write_data,
input wire read_en,
output wire [WIDTH-1:0] read_data,
output wire full,
output wire empty,
output wire [$clog2(DEPTH+1)-1:0] count
);
reg [WIDTH-1:0] data_reg[DEPTH-1:0];
reg [$clog2(DEPTH+1)-1:0] ptr_reg = 0, ptr_next;
reg full_reg = 0, full_next;
reg empty_reg = 1, empty_next;
assign read_data = data_reg[ptr_reg-1];
assign full = full_reg;
assign empty = empty_reg;
assign count = ptr_reg;
wire [WIDTH-1:0] data_reg_0 = data_reg[0];
wire [WIDTH-1:0] data_reg_1 = data_reg[1];
//wire [WIDTH-1:0] data_reg_2 = data_reg[2];
//wire [WIDTH-1:0] data_reg_3 = data_reg[3];
wire ptr_empty = ptr_reg == 0;
wire ptr_empty1 = ptr_reg == 1;
wire ptr_full = ptr_reg == DEPTH;
wire ptr_full1 = ptr_reg == DEPTH-1;
reg shift;
reg inc;
reg dec;
integer i;
initial begin
for (i = 0; i < DEPTH; i = i + 1) begin
data_reg[i] <= 0;
end
end
always @* begin
shift = 0;
inc = 0;
dec = 0;
ptr_next = ptr_reg;
full_next = full_reg;
empty_next = empty_reg;
if (read_en & write_en) begin
shift = 1;
end else if (read_en & ~empty) begin
dec = 1;
full_next = 0;
empty_next = ptr_empty1;
end else if (write_en & ~full) begin
shift = 1;
inc = 1;
full_next = ptr_full1;
empty_next = 0;
end
end
always @(posedge clk) begin
if (rst) begin
ptr_reg <= 0;
end else begin
if (shift) begin
data_reg[0] <= write_data;
for (i = 0; i < DEPTH-1; i = i + 1) begin
data_reg[i+1] <= data_reg[i];
end
end
if (inc) begin
ptr_reg <= ptr_reg + 1;
end else if (dec) begin
ptr_reg <= ptr_reg - 1;
end else begin
ptr_reg <= ptr_reg;
end
//full_reg <= ptr_next == DEPTH;
//empty_reg <= ptr_next == 0;
//full_reg <= (ptr_reg == DEPTH && ~(~write_en & read_en)) || (ptr_reg == (DEPTH-1) && (write_en & ~read_en));
//empty_reg <= (ptr_reg == 0 && ~(~read_en & write_en)) || (ptr_reg == 1 && (read_en & ~write_en));
//full_reg <= (ptr_full && ~(~write_en & read_en)) || (ptr_full1 && (write_en & ~read_en));
//empty_reg <= (ptr_empty && ~(~read_en & write_en)) || (ptr_empty1 && (read_en & ~write_en));
full_reg <= full_next;
empty_reg <= empty_next;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: test_stub_bist.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// ____________________________________________________________________________
//
// test_stub_bist - Test Stub with BIST Support
// ____________________________________________________________________________
//
// Description: DBB interface for test signal generation and BIST execution
// ____________________________________________________________________________
module test_stub_bist (/*AUTOARG*/
// Outputs
mux_drive_disable, mem_write_disable, sehold, se, testmode_l,
mem_bypass, so_0, so_1, so_2, so, tst_ctu_mbist_done,
tst_ctu_mbist_fail, bist_ctl_reg_out, mbist_bisi_mode,
mbist_stop_on_next_fail, mbist_stop_on_fail, mbist_loop_mode,
mbist_loop_on_addr, mbist_data_mode, mbist_start,
// Inputs
ctu_tst_pre_grst_l, arst_l, cluster_grst_l, global_shift_enable,
ctu_tst_scan_disable, ctu_tst_scanmode, ctu_tst_macrotest,
ctu_tst_short_chain, long_chain_so_0, short_chain_so_0,
long_chain_so_1, short_chain_so_1, long_chain_so_2, short_chain_so_2,
si, ctu_tst_mbist_enable, rclk, bist_ctl_reg_in, bist_ctl_reg_wr_en,
mbist_done, mbist_err
);
// Scan interface
input ctu_tst_pre_grst_l;
input arst_l;
input cluster_grst_l;
input global_shift_enable;
input ctu_tst_scan_disable;
input ctu_tst_scanmode;
input ctu_tst_macrotest;
input ctu_tst_short_chain;
input long_chain_so_0;
input short_chain_so_0;
input long_chain_so_1;
input short_chain_so_1;
input long_chain_so_2;
input short_chain_so_2;
input si;
output mux_drive_disable;
output mem_write_disable;
output sehold;
output se;
output testmode_l;
output mem_bypass;
output so_0;
output so_1;
output so_2;
output so;
// Global BIST control interface
input ctu_tst_mbist_enable;
output tst_ctu_mbist_done;
output tst_ctu_mbist_fail;
// CSR interface
input rclk;
input [6:0] bist_ctl_reg_in;
input bist_ctl_reg_wr_en;
output [10:0] bist_ctl_reg_out;
// BIST diagnostic interface
input mbist_done;
input [2:0] mbist_err;
output mbist_bisi_mode;
output mbist_stop_on_next_fail;
output mbist_stop_on_fail;
output mbist_loop_mode;
output mbist_loop_on_addr;
output mbist_data_mode;
output mbist_start;
// Internal wires
wire csr_write; // write enable for bist_ctl_reg
wire mbist_enable_d1; // delayed version of ctu_tst_mbist_enable
wire mbist_enable_d2; // delayed version of mbist_enable_d1
wire mbist_stop_serial_in; // delayed version of mbist_start
wire [6:0] bist_diag_mode; // data written to bist_ctl_reg
wire mbist_done_delayed; // flopped version of mbist_done
wire clr_mbist_ctl_l; // flag to clear mbist control bits
wire mbist_fail_flag; // summation of array error signals
wire serial_setup_mode; // serial setup mode flag
wire serial_setup_mode_ctl; // serial setup mode control
wire serial_setup_start; // edge to enable serial setup mode
wire serial_setup_enable; // kick off serial setup mode
wire serial_setup_stop; // reset for serial setup mode
wire serial_setup_valid; // bist start qualifier
wire si; // scanin place holder
wire so; // scanout place holder
// Scan control
test_stub_scan scan_ctls (
.ctu_tst_pre_grst_l(ctu_tst_pre_grst_l),
.arst_l(arst_l),
.global_shift_enable(global_shift_enable),
.ctu_tst_scan_disable(ctu_tst_scan_disable),
.ctu_tst_scanmode(ctu_tst_scanmode),
.ctu_tst_macrotest(ctu_tst_macrotest),
.ctu_tst_short_chain(ctu_tst_short_chain),
.long_chain_so_0(long_chain_so_0),
.short_chain_so_0(short_chain_so_0),
.long_chain_so_1(long_chain_so_1),
.short_chain_so_1(short_chain_so_1),
.long_chain_so_2(long_chain_so_2),
.short_chain_so_2(short_chain_so_2),
.mux_drive_disable(mux_drive_disable),
.mem_write_disable(mem_write_disable),
.sehold(sehold),
.se(se),
.testmode_l(testmode_l),
.mem_bypass(mem_bypass),
.so_0(so_0),
.so_1(so_1),
.so_2(so_2)
);
// BIST control
assign csr_write = bist_ctl_reg_wr_en | serial_setup_mode;
assign mbist_done_delayed = bist_ctl_reg_out[10];
assign clr_mbist_ctl_l = cluster_grst_l & ~serial_setup_start;
assign {mbist_bisi_mode,
mbist_stop_on_next_fail,
mbist_stop_on_fail,
mbist_loop_mode,
mbist_loop_on_addr,
mbist_data_mode,
mbist_start
} = bist_ctl_reg_out[6:0];
// Software accessible CSR (parallel interface)
//
// Bit Type Function
// --- ____ -----------------
// 10 S Done flag
// 9 S Array 2 fail flag
// 8 S Array 1 fail flag
// 7 S Array 0 fail flag
// 6 C Bisi mode
// 5 C Stop on next fail
// 4 C Stop on fail
// 3 C Loop
// 2 C Loop on address
// 1 C User data mode
// 0 C Start
dffrl_ns #(4) bist_ctl_reg_10_7 (
.din({mbist_done,mbist_err[2:0]}),
.clk(rclk),
.rst_l(cluster_grst_l),
.q(bist_ctl_reg_out[10:7])
);
dffrle_ns #(1) bist_ctl_reg_6 (
.din(bist_diag_mode[6]),
.clk(rclk),
.rst_l(clr_mbist_ctl_l),
.en(csr_write),
.q(bist_ctl_reg_out[6])
);
dffrle_ns #(5) bist_ctl_reg_5_1 (
.din(bist_diag_mode[5:1]),
.clk(rclk),
.rst_l(clr_mbist_ctl_l),
.en(csr_write),
.q(bist_ctl_reg_out[5:1])
);
dffrle_ns #(1) bist_ctl_reg_0 (
.din(bist_diag_mode[0]),
.clk(rclk),
.rst_l(clr_mbist_ctl_l),
.en(csr_write),
.q(bist_ctl_reg_out[0])
);
// CTU serial BIST interface. Bit ordering is 5,4,3,2,1,6,0.
assign tst_ctu_mbist_done = mbist_done_delayed;
assign mbist_fail_flag = |mbist_err[2:0];
assign serial_setup_start = mbist_enable_d1 & ~mbist_enable_d2 & ~serial_setup_mode;
assign serial_setup_stop = cluster_grst_l & ~serial_setup_valid;
assign serial_setup_enable = serial_setup_start | serial_setup_mode;
assign bist_diag_mode[5:1] = serial_setup_mode ? {mbist_enable_d2, bist_ctl_reg_out[5:2]} : bist_ctl_reg_in[5:1];
assign bist_diag_mode[6] = serial_setup_mode ? bist_ctl_reg_out[1] : bist_ctl_reg_in[6];
assign bist_diag_mode[0] = serial_setup_mode ? bist_ctl_reg_out[6] & serial_setup_valid : bist_ctl_reg_in[0];
dff_ns #(1) tst_ctu_mbist_fail_reg (
.din(mbist_fail_flag),
.clk(rclk),
.q(tst_ctu_mbist_fail)
);
dff_ns #(1) mbist_enable_d1_reg (
.din(ctu_tst_mbist_enable),
.clk(rclk),
.q(mbist_enable_d1)
);
dff_ns #(1) mbist_enable_d2_reg (
.din(mbist_enable_d1),
.clk(rclk),
.q(mbist_enable_d2)
);
dff_ns #(1) serial_setup_valid_reg (
.din(bist_ctl_reg_out[6]),
.clk(rclk),
.q(serial_setup_valid)
);
dffrl_ns #(1) serial_setup_mode_reg (
.din (serial_setup_enable),
.clk(rclk),
.rst_l(serial_setup_stop),
.q(serial_setup_mode)
);
endmodule // test_stub_bist
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_4_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_4_V
/**
* lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer, vpb/vnb
* taps, double-row-height cell.
*
* Verilog wrapper for lpflow_lsbuf_lh_isowell_tap with
* size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A),
.LOWLVPWR(LOWLVPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
wire LOWLVPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211OI_FUNCTIONAL_V
`define SKY130_FD_SC_HD__A211OI_FUNCTIONAL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a211oi (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, B1, C1);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211OI_FUNCTIONAL_V |
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2011 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Euclidean Division for integers (Trunc convention)
We use here the convention known as Trunc, or Round-Toward-Zero,
where [a/b] is the integer with the largest absolute value to
be between zero and the exact fraction. It can be summarized by:
[a = bq+r /\ 0 <= |r| < |b| /\ Sign(r) = Sign(a)]
This is the convention of Ocaml and many other systems (C, ASM, ...).
This convention is named "T" in the following paper:
R. Boute, "The Euclidean definition of the functions div and mod",
ACM Transactions on Programming Languages and Systems,
Vol. 14, No.2, pp. 127-144, April 1992.
See files [ZDivFloor] and [ZDivEucl] for others conventions.
*)
Require Import ZAxioms ZProperties NZDiv.
Module Type ZDivSpecific (Import Z:ZAxiomsSig')(Import DM : DivMod' Z).
Axiom mod_bound : forall a b, 0<=a -> 0<b -> 0 <= a mod b < b.
Axiom mod_opp_l : forall a b, b ~= 0 -> (-a) mod b == - (a mod b).
Axiom mod_opp_r : forall a b, b ~= 0 -> a mod (-b) == a mod b.
End ZDivSpecific.
Module Type ZDiv (Z:ZAxiomsSig)
:= DivMod Z <+ NZDivCommon Z <+ ZDivSpecific Z.
Module Type ZDivSig := ZAxiomsExtSig <+ ZDiv.
Module Type ZDivSig' := ZAxiomsExtSig' <+ ZDiv <+ DivModNotation.
Module ZDivPropFunct (Import Z : ZDivSig')(Import ZP : ZPropSig Z).
(** We benefit from what already exists for NZ *)
Module Import NZDivP := NZDivPropFunct Z ZP Z.
Ltac pos_or_neg a :=
let LT := fresh "LT" in
let LE := fresh "LE" in
destruct (le_gt_cases 0 a) as [LE|LT]; [|rewrite <- opp_pos_neg in LT].
(** Another formulation of the main equation *)
Lemma mod_eq :
forall a b, b~=0 -> a mod b == a - b*(a/b).
Proof.
intros.
rewrite <- add_move_l.
symmetry. now apply div_mod.
Qed.
(** A few sign rules (simple ones) *)
Lemma mod_opp_opp : forall a b, b ~= 0 -> (-a) mod (-b) == - (a mod b).
Proof. intros. now rewrite mod_opp_r, mod_opp_l. Qed.
Lemma div_opp_l : forall a b, b ~= 0 -> (-a)/b == -(a/b).
Proof.
intros.
rewrite <- (mul_cancel_l _ _ b) by trivial.
rewrite <- (add_cancel_r _ _ ((-a) mod b)).
now rewrite <- div_mod, mod_opp_l, mul_opp_r, <- opp_add_distr, <- div_mod.
Qed.
Lemma div_opp_r : forall a b, b ~= 0 -> a/(-b) == -(a/b).
Proof.
intros.
assert (-b ~= 0) by (now rewrite eq_opp_l, opp_0).
rewrite <- (mul_cancel_l _ _ (-b)) by trivial.
rewrite <- (add_cancel_r _ _ (a mod (-b))).
now rewrite <- div_mod, mod_opp_r, mul_opp_opp, <- div_mod.
Qed.
Lemma div_opp_opp : forall a b, b ~= 0 -> (-a)/(-b) == a/b.
Proof. intros. now rewrite div_opp_r, div_opp_l, opp_involutive. Qed.
(** The sign of [a mod b] is the one of [a] *)
(* TODO: a proper sgn function and theory *)
Lemma mod_sign : forall a b, b~=0 -> 0 <= (a mod b) * a.
Proof.
assert (Aux : forall a b, 0<b -> 0 <= (a mod b) * a).
intros. pos_or_neg a.
apply mul_nonneg_nonneg; trivial. now destruct (mod_bound a b).
rewrite <- mul_opp_opp, <- mod_opp_l by order.
apply mul_nonneg_nonneg; try order. destruct (mod_bound (-a) b); order.
intros. pos_or_neg b. apply Aux; order.
rewrite <- mod_opp_r by order. apply Aux; order.
Qed.
(** Uniqueness theorems *)
Theorem div_mod_unique : forall b q1 q2 r1 r2 : t,
(0<=r1<b \/ b<r1<=0) -> (0<=r2<b \/ b<r2<=0) ->
b*q1+r1 == b*q2+r2 -> q1 == q2 /\ r1 == r2.
Proof.
intros b q1 q2 r1 r2 Hr1 Hr2 EQ.
destruct Hr1; destruct Hr2; try (intuition; order).
apply div_mod_unique with b; trivial.
rewrite <- (opp_inj_wd r1 r2).
apply div_mod_unique with (-b); trivial.
rewrite <- opp_lt_mono, opp_nonneg_nonpos; tauto.
rewrite <- opp_lt_mono, opp_nonneg_nonpos; tauto.
now rewrite 2 mul_opp_l, <- 2 opp_add_distr, opp_inj_wd.
Qed.
Theorem div_unique:
forall a b q r, 0<=a -> 0<=r<b -> a == b*q + r -> q == a/b.
Proof. intros; now apply div_unique with r. Qed.
Theorem mod_unique:
forall a b q r, 0<=a -> 0<=r<b -> a == b*q + r -> r == a mod b.
Proof. intros; now apply mod_unique with q. Qed.
(** A division by itself returns 1 *)
Lemma div_same : forall a, a~=0 -> a/a == 1.
Proof.
intros. pos_or_neg a. apply div_same; order.
rewrite <- div_opp_opp by trivial. now apply div_same.
Qed.
Lemma mod_same : forall a, a~=0 -> a mod a == 0.
Proof.
intros. rewrite mod_eq, div_same by trivial. nzsimpl. apply sub_diag.
Qed.
(** A division of a small number by a bigger one yields zero. *)
Theorem div_small: forall a b, 0<=a<b -> a/b == 0.
Proof. exact div_small. Qed.
(** Same situation, in term of modulo: *)
Theorem mod_small: forall a b, 0<=a<b -> a mod b == a.
Proof. exact mod_small. Qed.
(** * Basic values of divisions and modulo. *)
Lemma div_0_l: forall a, a~=0 -> 0/a == 0.
Proof.
intros. pos_or_neg a. apply div_0_l; order.
rewrite <- div_opp_opp, opp_0 by trivial. now apply div_0_l.
Qed.
Lemma mod_0_l: forall a, a~=0 -> 0 mod a == 0.
Proof.
intros; rewrite mod_eq, div_0_l; now nzsimpl.
Qed.
Lemma div_1_r: forall a, a/1 == a.
Proof.
intros. pos_or_neg a. now apply div_1_r.
apply opp_inj. rewrite <- div_opp_l. apply div_1_r; order.
intro EQ; symmetry in EQ; revert EQ; apply lt_neq, lt_0_1.
Qed.
Lemma mod_1_r: forall a, a mod 1 == 0.
Proof.
intros. rewrite mod_eq, div_1_r; nzsimpl; auto using sub_diag.
intro EQ; symmetry in EQ; revert EQ; apply lt_neq; apply lt_0_1.
Qed.
Lemma div_1_l: forall a, 1<a -> 1/a == 0.
Proof. exact div_1_l. Qed.
Lemma mod_1_l: forall a, 1<a -> 1 mod a == 1.
Proof. exact mod_1_l. Qed.
Lemma div_mul : forall a b, b~=0 -> (a*b)/b == a.
Proof.
intros. pos_or_neg a; pos_or_neg b. apply div_mul; order.
rewrite <- div_opp_opp, <- mul_opp_r by order. apply div_mul; order.
rewrite <- opp_inj_wd, <- div_opp_l, <- mul_opp_l by order. apply div_mul; order.
rewrite <- opp_inj_wd, <- div_opp_r, <- mul_opp_opp by order. apply div_mul; order.
Qed.
Lemma mod_mul : forall a b, b~=0 -> (a*b) mod b == 0.
Proof.
intros. rewrite mod_eq, div_mul by trivial. rewrite mul_comm; apply sub_diag.
Qed.
(** * Order results about mod and div *)
(** A modulo cannot grow beyond its starting point. *)
Theorem mod_le: forall a b, 0<=a -> 0<b -> a mod b <= a.
Proof. exact mod_le. Qed.
Theorem div_pos : forall a b, 0<=a -> 0<b -> 0<= a/b.
Proof. exact div_pos. Qed.
Lemma div_str_pos : forall a b, 0<b<=a -> 0 < a/b.
Proof. exact div_str_pos. Qed.
Lemma div_small_iff : forall a b, b~=0 -> (a/b==0 <-> abs a < abs b).
Proof.
intros. pos_or_neg a; pos_or_neg b.
rewrite div_small_iff; try order. rewrite 2 abs_eq; intuition; order.
rewrite <- opp_inj_wd, opp_0, <- div_opp_r, div_small_iff by order.
rewrite (abs_eq a), (abs_neq' b); intuition; order.
rewrite <- opp_inj_wd, opp_0, <- div_opp_l, div_small_iff by order.
rewrite (abs_neq' a), (abs_eq b); intuition; order.
rewrite <- div_opp_opp, div_small_iff by order.
rewrite (abs_neq' a), (abs_neq' b); intuition; order.
Qed.
Lemma mod_small_iff : forall a b, b~=0 -> (a mod b == a <-> abs a < abs b).
Proof.
intros. rewrite mod_eq, <- div_small_iff by order.
rewrite sub_move_r, <- (add_0_r a) at 1. rewrite add_cancel_l.
rewrite eq_sym_iff, eq_mul_0. tauto.
Qed.
(** As soon as the divisor is strictly greater than 1,
the division is strictly decreasing. *)
Lemma div_lt : forall a b, 0<a -> 1<b -> a/b < a.
Proof. exact div_lt. Qed.
(** [le] is compatible with a positive division. *)
Lemma div_le_mono : forall a b c, 0<c -> a<=b -> a/c <= b/c.
Proof.
intros. pos_or_neg a. apply div_le_mono; auto.
pos_or_neg b. apply le_trans with 0.
rewrite <- opp_nonneg_nonpos, <- div_opp_l by order.
apply div_pos; order.
apply div_pos; order.
rewrite opp_le_mono in *. rewrite <- 2 div_opp_l by order.
apply div_le_mono; intuition; order.
Qed.
(** With this choice of division,
rounding of div is always done toward zero: *)
Lemma mul_div_le : forall a b, 0<=a -> b~=0 -> 0 <= b*(a/b) <= a.
Proof.
intros. pos_or_neg b.
split.
apply mul_nonneg_nonneg; [|apply div_pos]; order.
apply mul_div_le; order.
rewrite <- mul_opp_opp, <- div_opp_r by order.
split.
apply mul_nonneg_nonneg; [|apply div_pos]; order.
apply mul_div_le; order.
Qed.
Lemma mul_div_ge : forall a b, a<=0 -> b~=0 -> a <= b*(a/b) <= 0.
Proof.
intros.
rewrite <- opp_nonneg_nonpos, opp_le_mono, <-mul_opp_r, <-div_opp_l by order.
rewrite <- opp_nonneg_nonpos in *.
destruct (mul_div_le (-a) b); tauto.
Qed.
(** For positive numbers, considering [S (a/b)] leads to an upper bound for [a] *)
Lemma mul_succ_div_gt: forall a b, 0<=a -> 0<b -> a < b*(S (a/b)).
Proof. exact mul_succ_div_gt. Qed.
(** Similar results with negative numbers *)
Lemma mul_pred_div_lt: forall a b, a<=0 -> 0<b -> b*(P (a/b)) < a.
Proof.
intros.
rewrite opp_lt_mono, <- mul_opp_r, opp_pred, <- div_opp_l by order.
rewrite <- opp_nonneg_nonpos in *.
now apply mul_succ_div_gt.
Qed.
Lemma mul_pred_div_gt: forall a b, 0<=a -> b<0 -> a < b*(P (a/b)).
Proof.
intros.
rewrite <- mul_opp_opp, opp_pred, <- div_opp_r by order.
rewrite <- opp_pos_neg in *.
now apply mul_succ_div_gt.
Qed.
Lemma mul_succ_div_lt: forall a b, a<=0 -> b<0 -> b*(S (a/b)) < a.
Proof.
intros.
rewrite opp_lt_mono, <- mul_opp_l, <- div_opp_opp by order.
rewrite <- opp_nonneg_nonpos, <- opp_pos_neg in *.
now apply mul_succ_div_gt.
Qed.
(** Inequality [mul_div_le] is exact iff the modulo is zero. *)
Lemma div_exact : forall a b, b~=0 -> (a == b*(a/b) <-> a mod b == 0).
Proof.
intros. rewrite mod_eq by order. rewrite sub_move_r; nzsimpl; tauto.
Qed.
(** Some additionnal inequalities about div. *)
Theorem div_lt_upper_bound:
forall a b q, 0<=a -> 0<b -> a < b*q -> a/b < q.
Proof. exact div_lt_upper_bound. Qed.
Theorem div_le_upper_bound:
forall a b q, 0<b -> a <= b*q -> a/b <= q.
Proof.
intros.
rewrite <- (div_mul q b) by order.
apply div_le_mono; trivial. now rewrite mul_comm.
Qed.
Theorem div_le_lower_bound:
forall a b q, 0<b -> b*q <= a -> q <= a/b.
Proof.
intros.
rewrite <- (div_mul q b) by order.
apply div_le_mono; trivial. now rewrite mul_comm.
Qed.
(** A division respects opposite monotonicity for the divisor *)
Lemma div_le_compat_l: forall p q r, 0<=p -> 0<q<=r -> p/r <= p/q.
Proof. exact div_le_compat_l. Qed.
(** * Relations between usual operations and mod and div *)
(** Unlike with other division conventions, some results here aren't
always valid, and need to be restricted. For instance
[(a+b*c) mod c <> a mod c] for [a=9,b=-5,c=2] *)
Lemma mod_add : forall a b c, c~=0 -> 0 <= (a+b*c)*a ->
(a + b * c) mod c == a mod c.
Proof.
assert (forall a b c, c~=0 -> 0<=a -> 0<=a+b*c -> (a+b*c) mod c == a mod c).
intros. pos_or_neg c. apply mod_add; order.
rewrite <- (mod_opp_r a), <- (mod_opp_r (a+b*c)) by order.
rewrite <- mul_opp_opp in *.
apply mod_add; order.
intros a b c Hc Habc.
destruct (le_0_mul _ _ Habc) as [(Habc',Ha)|(Habc',Ha)]. auto.
apply opp_inj. revert Ha Habc'.
rewrite <- 2 opp_nonneg_nonpos.
rewrite <- 2 mod_opp_l, opp_add_distr, <- mul_opp_l by order. auto.
Qed.
Lemma div_add : forall a b c, c~=0 -> 0 <= (a+b*c)*a ->
(a + b * c) / c == a / c + b.
Proof.
intros.
rewrite <- (mul_cancel_l _ _ c) by trivial.
rewrite <- (add_cancel_r _ _ ((a+b*c) mod c)).
rewrite <- div_mod, mod_add by trivial.
now rewrite mul_add_distr_l, add_shuffle0, <-div_mod, mul_comm.
Qed.
Lemma div_add_l: forall a b c, b~=0 -> 0 <= (a*b+c)*c ->
(a * b + c) / b == a + c / b.
Proof.
intros a b c. rewrite add_comm, (add_comm a). now apply div_add.
Qed.
(** Cancellations. *)
Lemma div_mul_cancel_r : forall a b c, b~=0 -> c~=0 ->
(a*c)/(b*c) == a/b.
Proof.
assert (Aux1 : forall a b c, 0<=a -> 0<b -> c~=0 -> (a*c)/(b*c) == a/b).
intros. pos_or_neg c. apply div_mul_cancel_r; order.
rewrite <- div_opp_opp, <- 2 mul_opp_r. apply div_mul_cancel_r; order.
rewrite <- neq_mul_0; intuition order.
assert (Aux2 : forall a b c, 0<=a -> b~=0 -> c~=0 -> (a*c)/(b*c) == a/b).
intros. pos_or_neg b. apply Aux1; order.
apply opp_inj. rewrite <- 2 div_opp_r, <- mul_opp_l; try order. apply Aux1; order.
rewrite <- neq_mul_0; intuition order.
intros. pos_or_neg a. apply Aux2; order.
apply opp_inj. rewrite <- 2 div_opp_l, <- mul_opp_l; try order. apply Aux2; order.
rewrite <- neq_mul_0; intuition order.
Qed.
Lemma div_mul_cancel_l : forall a b c, b~=0 -> c~=0 ->
(c*a)/(c*b) == a/b.
Proof.
intros. rewrite !(mul_comm c); now apply div_mul_cancel_r.
Qed.
Lemma mul_mod_distr_r: forall a b c, b~=0 -> c~=0 ->
(a*c) mod (b*c) == (a mod b) * c.
Proof.
intros.
assert (b*c ~= 0) by (rewrite <- neq_mul_0; tauto).
rewrite ! mod_eq by trivial.
rewrite div_mul_cancel_r by order.
now rewrite mul_sub_distr_r, <- !mul_assoc, (mul_comm (a/b) c).
Qed.
Lemma mul_mod_distr_l: forall a b c, b~=0 -> c~=0 ->
(c*a) mod (c*b) == c * (a mod b).
Proof.
intros; rewrite !(mul_comm c); now apply mul_mod_distr_r.
Qed.
(** Operations modulo. *)
Theorem mod_mod: forall a n, n~=0 ->
(a mod n) mod n == a mod n.
Proof.
intros. pos_or_neg a; pos_or_neg n. apply mod_mod; order.
rewrite <- ! (mod_opp_r _ n) by trivial. apply mod_mod; order.
apply opp_inj. rewrite <- !mod_opp_l by order. apply mod_mod; order.
apply opp_inj. rewrite <- !mod_opp_opp by order. apply mod_mod; order.
Qed.
Lemma mul_mod_idemp_l : forall a b n, n~=0 ->
((a mod n)*b) mod n == (a*b) mod n.
Proof.
assert (Aux1 : forall a b n, 0<=a -> 0<=b -> n~=0 ->
((a mod n)*b) mod n == (a*b) mod n).
intros. pos_or_neg n. apply mul_mod_idemp_l; order.
rewrite <- ! (mod_opp_r _ n) by order. apply mul_mod_idemp_l; order.
assert (Aux2 : forall a b n, 0<=a -> n~=0 ->
((a mod n)*b) mod n == (a*b) mod n).
intros. pos_or_neg b. now apply Aux1.
apply opp_inj. rewrite <-2 mod_opp_l, <-2 mul_opp_r by order.
apply Aux1; order.
intros a b n Hn. pos_or_neg a. now apply Aux2.
apply opp_inj. rewrite <-2 mod_opp_l, <-2 mul_opp_l, <-mod_opp_l by order.
apply Aux2; order.
Qed.
Lemma mul_mod_idemp_r : forall a b n, n~=0 ->
(a*(b mod n)) mod n == (a*b) mod n.
Proof.
intros. rewrite !(mul_comm a). now apply mul_mod_idemp_l.
Qed.
Theorem mul_mod: forall a b n, n~=0 ->
(a * b) mod n == ((a mod n) * (b mod n)) mod n.
Proof.
intros. now rewrite mul_mod_idemp_l, mul_mod_idemp_r.
Qed.
(** addition and modulo
Generally speaking, unlike with other conventions, we don't have
[(a+b) mod n = (a mod n + b mod n) mod n]
for any a and b.
For instance, take (8 + (-10)) mod 3 = -2 whereas
(8 mod 3 + (-10 mod 3)) mod 3 = 1.
*)
Lemma add_mod_idemp_l : forall a b n, n~=0 -> 0 <= a*b ->
((a mod n)+b) mod n == (a+b) mod n.
Proof.
assert (Aux : forall a b n, 0<=a -> 0<=b -> n~=0 ->
((a mod n)+b) mod n == (a+b) mod n).
intros. pos_or_neg n. apply add_mod_idemp_l; order.
rewrite <- ! (mod_opp_r _ n) by order. apply add_mod_idemp_l; order.
intros a b n Hn Hab. destruct (le_0_mul _ _ Hab) as [(Ha,Hb)|(Ha,Hb)].
now apply Aux.
apply opp_inj. rewrite <-2 mod_opp_l, 2 opp_add_distr, <-mod_opp_l by order.
rewrite <- opp_nonneg_nonpos in *.
now apply Aux.
Qed.
Lemma add_mod_idemp_r : forall a b n, n~=0 -> 0 <= a*b ->
(a+(b mod n)) mod n == (a+b) mod n.
Proof.
intros. rewrite !(add_comm a). apply add_mod_idemp_l; trivial.
now rewrite mul_comm.
Qed.
Theorem add_mod: forall a b n, n~=0 -> 0 <= a*b ->
(a+b) mod n == (a mod n + b mod n) mod n.
Proof.
intros a b n Hn Hab. rewrite add_mod_idemp_l, add_mod_idemp_r; trivial.
reflexivity.
destruct (le_0_mul _ _ Hab) as [(Ha,Hb)|(Ha,Hb)];
destruct (le_0_mul _ _ (mod_sign b n Hn)) as [(Hb',Hm)|(Hb',Hm)];
auto using mul_nonneg_nonneg, mul_nonpos_nonpos.
setoid_replace b with 0 by order. rewrite mod_0_l by order. nzsimpl; order.
setoid_replace b with 0 by order. rewrite mod_0_l by order. nzsimpl; order.
Qed.
(** Conversely, the following result needs less restrictions here. *)
Lemma div_div : forall a b c, b~=0 -> c~=0 ->
(a/b)/c == a/(b*c).
Proof.
assert (Aux1 : forall a b c, 0<=a -> 0<b -> c~=0 -> (a/b)/c == a/(b*c)).
intros. pos_or_neg c. apply div_div; order.
apply opp_inj. rewrite <- 2 div_opp_r, <- mul_opp_r; trivial.
apply div_div; order.
rewrite <- neq_mul_0; intuition order.
assert (Aux2 : forall a b c, 0<=a -> b~=0 -> c~=0 -> (a/b)/c == a/(b*c)).
intros. pos_or_neg b. apply Aux1; order.
apply opp_inj. rewrite <- div_opp_l, <- 2 div_opp_r, <- mul_opp_l; trivial.
apply Aux1; trivial.
rewrite <- neq_mul_0; intuition order.
intros. pos_or_neg a. apply Aux2; order.
apply opp_inj. rewrite <- 3 div_opp_l; try order. apply Aux2; order.
rewrite <- neq_mul_0. tauto.
Qed.
(** A last inequality: *)
Theorem div_mul_le:
forall a b c, 0<=a -> 0<b -> 0<=c -> c*(a/b) <= (c*a)/b.
Proof. exact div_mul_le. Qed.
(** mod is related to divisibility *)
Lemma mod_divides : forall a b, b~=0 ->
(a mod b == 0 <-> exists c, a == b*c).
Proof.
intros a b Hb. split.
intros Hab. exists (a/b). rewrite (div_mod a b Hb) at 1.
rewrite Hab; now nzsimpl.
intros (c,Hc). rewrite Hc, mul_comm. now apply mod_mul.
Qed.
End ZDivPropFunct.
|
//-----------------------------------------------------------------------------
// File : test_setup.v
// Creation date : 28.11.2017
// Creation time : 16:31:16
// Description : Test arrangement for the example CPU with data memory, instuction memory, clock source, and SPI slave.
// Created by : TermosPullo
// Tool : Kactus2 3.4.1184 32-bit
// Plugin : Verilog generator 2.1
// This file was generated based on IP-XACT component tut.fi:cpu.structure.test:cpu_example.setup:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/cpu.structure.test/cpu_example.setup/1.0/cpu_example.setup.1.0.xml
//-----------------------------------------------------------------------------
module test_setup();
// cpu_example_0_wb_system_to_clock_generator_0_wb_system wires:
wire cpu_example_0_wb_system_to_clock_generator_0_wb_systemclk;
wire cpu_example_0_wb_system_to_clock_generator_0_wb_systemrst;
// instruction_memory_0_slave_to_cpu_example_0_iaddr_o wires:
wire [7:0] instruction_memory_0_slave_to_cpu_example_0_iaddr_oaddress;
wire [27:0] instruction_memory_0_slave_to_cpu_example_0_iaddr_oread_data;
// cpu_example_0_local_data_to_data_memory_0_slave wires:
wire [9:0] cpu_example_0_local_data_to_data_memory_0_slaveaddress;
wire [31:0] cpu_example_0_local_data_to_data_memory_0_slaveread_data;
wire cpu_example_0_local_data_to_data_memory_0_slavewrite;
wire [31:0] cpu_example_0_local_data_to_data_memory_0_slavewrite_data;
// spi_slave_0_slave_if_to_cpu_example_0_spi_master wires:
wire spi_slave_0_slave_if_to_cpu_example_0_spi_masterMISO;
wire spi_slave_0_slave_if_to_cpu_example_0_spi_masterMOSI;
wire spi_slave_0_slave_if_to_cpu_example_0_spi_masterSCLK;
wire spi_slave_0_slave_if_to_cpu_example_0_spi_masterSS;
// Ad-hoc wires:
wire spi_slave_0_rst_in_to_clock_generator_0_rst_o;
wire clock_generator_0_rst_o_to_instruction_memory_0_rst_i;
wire clock_generator_0_rst_o_to_cpu_example_0_rst_i;
wire clock_generator_0_clk_o_to_cpu_example_0_clk_i;
wire clock_generator_0_clk_o_to_instruction_memory_0_clk_i;
wire clock_generator_0_rst_o_to_data_memory_0_rst_i;
wire data_memory_0_clk_i_to_clock_generator_0_clk_o;
// clock_generator_0 port wires:
wire clock_generator_0_clk_o;
wire clock_generator_0_rst_o;
// cpu_example_0 port wires:
wire cpu_example_0_clk_i;
wire cpu_example_0_clk_out;
wire cpu_example_0_data_in;
wire cpu_example_0_data_out;
wire [7:0] cpu_example_0_iaddr_o;
wire [27:0] cpu_example_0_instruction_feed;
wire [9:0] cpu_example_0_local_address_o;
wire [15:0] cpu_example_0_local_read_data;
wire [15:0] cpu_example_0_local_write_data;
wire cpu_example_0_local_write_o;
wire cpu_example_0_rst_i;
wire cpu_example_0_slave_select_out;
// data_memory_0 port wires:
wire [8:0] data_memory_0_adr_i;
wire data_memory_0_clk_i;
wire [31:0] data_memory_0_read_data;
wire data_memory_0_rst_i;
wire data_memory_0_write;
wire [31:0] data_memory_0_write_data;
// instruction_memory_0 port wires:
wire instruction_memory_0_clk_i;
wire [7:0] instruction_memory_0_iaddr_i;
wire [27:0] instruction_memory_0_instruction_feed;
wire instruction_memory_0_rst_i;
// spi_slave_0 port wires:
wire spi_slave_0_clk_in;
wire spi_slave_0_data_in;
wire spi_slave_0_data_out;
wire spi_slave_0_rst_in;
wire spi_slave_0_slave_select_in;
// clock_generator_0 assignments:
assign cpu_example_0_wb_system_to_clock_generator_0_wb_systemclk = clock_generator_0_clk_o;
assign clock_generator_0_clk_o_to_cpu_example_0_clk_i = clock_generator_0_clk_o;
assign clock_generator_0_clk_o_to_instruction_memory_0_clk_i = clock_generator_0_clk_o;
assign data_memory_0_clk_i_to_clock_generator_0_clk_o = clock_generator_0_clk_o;
assign clock_generator_0_rst_o_to_cpu_example_0_rst_i = clock_generator_0_rst_o;
assign clock_generator_0_rst_o_to_data_memory_0_rst_i = clock_generator_0_rst_o;
assign clock_generator_0_rst_o_to_instruction_memory_0_rst_i = clock_generator_0_rst_o;
assign cpu_example_0_wb_system_to_clock_generator_0_wb_systemrst = clock_generator_0_rst_o;
assign spi_slave_0_rst_in_to_clock_generator_0_rst_o = clock_generator_0_rst_o;
// cpu_example_0 assignments:
assign cpu_example_0_clk_i = cpu_example_0_wb_system_to_clock_generator_0_wb_systemclk;
assign cpu_example_0_clk_i = clock_generator_0_clk_o_to_cpu_example_0_clk_i;
assign spi_slave_0_slave_if_to_cpu_example_0_spi_masterSCLK = cpu_example_0_clk_out;
assign cpu_example_0_data_in = spi_slave_0_slave_if_to_cpu_example_0_spi_masterMISO;
assign spi_slave_0_slave_if_to_cpu_example_0_spi_masterMOSI = cpu_example_0_data_out;
assign instruction_memory_0_slave_to_cpu_example_0_iaddr_oaddress[7:0] = cpu_example_0_iaddr_o[7:0];
assign cpu_example_0_instruction_feed[27:0] = instruction_memory_0_slave_to_cpu_example_0_iaddr_oread_data[27:0];
assign cpu_example_0_local_data_to_data_memory_0_slaveaddress[9:0] = cpu_example_0_local_address_o[9:0];
assign cpu_example_0_local_read_data[15:0] = cpu_example_0_local_data_to_data_memory_0_slaveread_data[15:0];
assign cpu_example_0_local_data_to_data_memory_0_slavewrite_data[15:0] = cpu_example_0_local_write_data[15:0];
assign cpu_example_0_local_data_to_data_memory_0_slavewrite = cpu_example_0_local_write_o;
assign cpu_example_0_rst_i = clock_generator_0_rst_o_to_cpu_example_0_rst_i;
assign cpu_example_0_rst_i = cpu_example_0_wb_system_to_clock_generator_0_wb_systemrst;
assign spi_slave_0_slave_if_to_cpu_example_0_spi_masterSS = cpu_example_0_slave_select_out;
// data_memory_0 assignments:
assign data_memory_0_adr_i[8:0] = cpu_example_0_local_data_to_data_memory_0_slaveaddress[8:0];
assign data_memory_0_clk_i = data_memory_0_clk_i_to_clock_generator_0_clk_o;
assign cpu_example_0_local_data_to_data_memory_0_slaveread_data[31:0] = data_memory_0_read_data[31:0];
assign data_memory_0_rst_i = clock_generator_0_rst_o_to_data_memory_0_rst_i;
assign data_memory_0_write = cpu_example_0_local_data_to_data_memory_0_slavewrite;
assign data_memory_0_write_data[31:0] = cpu_example_0_local_data_to_data_memory_0_slavewrite_data[31:0];
// instruction_memory_0 assignments:
assign instruction_memory_0_clk_i = clock_generator_0_clk_o_to_instruction_memory_0_clk_i;
assign instruction_memory_0_iaddr_i[7:0] = instruction_memory_0_slave_to_cpu_example_0_iaddr_oaddress[7:0];
assign instruction_memory_0_slave_to_cpu_example_0_iaddr_oread_data[27:0] = instruction_memory_0_instruction_feed[27:0];
assign instruction_memory_0_rst_i = clock_generator_0_rst_o_to_instruction_memory_0_rst_i;
// spi_slave_0 assignments:
assign spi_slave_0_clk_in = spi_slave_0_slave_if_to_cpu_example_0_spi_masterSCLK;
assign spi_slave_0_data_in = spi_slave_0_slave_if_to_cpu_example_0_spi_masterMOSI;
assign spi_slave_0_slave_if_to_cpu_example_0_spi_masterMISO = spi_slave_0_data_out;
assign spi_slave_0_rst_in = spi_slave_0_rst_in_to_clock_generator_0_rst_o;
assign spi_slave_0_slave_select_in = spi_slave_0_slave_if_to_cpu_example_0_spi_masterSS;
// IP-XACT VLNV: tut.fi:other.test:clock_generator:1.1
clock_generator clock_generator_0(
// Interface: wb_system
.clk_o (clock_generator_0_clk_o),
.rst_o (clock_generator_0_rst_o));
// IP-XACT VLNV: tut.fi:cpu.structure:cpu_example:1.0
cpu_example_0 #(
.ADDR_WIDTH (10),
.DATA_WIDTH (16),
.SUPPORTED_MEMORY (1024),
.INSTRUCTION_WIDTH (28),
.INSTRUCTION_ADDRESS_WIDTH(8))
cpu_example_0(
// Interface: instructions
.instruction_feed (cpu_example_0_instruction_feed),
.iaddr_o (cpu_example_0_iaddr_o),
// Interface: local_data
.local_read_data (cpu_example_0_local_read_data),
.local_address_o (cpu_example_0_local_address_o),
.local_write_data (cpu_example_0_local_write_data),
.local_write_o (cpu_example_0_local_write_o),
// Interface: spi_master
.data_in (cpu_example_0_data_in),
.clk_out (cpu_example_0_clk_out),
.data_out (cpu_example_0_data_out),
.slave_select_out (cpu_example_0_slave_select_out),
// Interface: wb_system
.clk_i (cpu_example_0_clk_i),
.rst_i (cpu_example_0_rst_i));
// IP-XACT VLNV: tut.fi:cpu.logic.test:data_memory:1.0
data_memory #(
.DATA_WIDTH (32),
.ADDR_WIDTH (9),
.MEMORY_SIZE (128),
.AUB (8))
data_memory_0(
// Interface: slave
.adr_i (data_memory_0_adr_i),
.write (data_memory_0_write),
.write_data (data_memory_0_write_data),
.read_data (data_memory_0_read_data),
// These ports are not in any interface
.clk_i (data_memory_0_clk_i),
.rst_i (data_memory_0_rst_i));
// IP-XACT VLNV: tut.fi:cpu.logic.test:instruction_memory:1.0
instruction_memory #(
.INSTRUCTION_WIDTH (28),
.INSTRUCTION_ADDRESS_WIDTH(8))
instruction_memory_0(
// Interface: slave
.iaddr_i (instruction_memory_0_iaddr_i),
.instruction_feed (instruction_memory_0_instruction_feed),
// These ports are not in any interface
.clk_i (instruction_memory_0_clk_i),
.rst_i (instruction_memory_0_rst_i));
// IP-XACT VLNV: tut.fi:communication.template:spi_slave:1.0
spi_slave #(
.SLAVE_ID (0))
spi_slave_0(
// Interface: slave_if
.clk_in (spi_slave_0_clk_in),
.data_in (spi_slave_0_data_in),
.slave_select_in (spi_slave_0_slave_select_in),
.data_out (spi_slave_0_data_out),
// These ports are not in any interface
.rst_in (spi_slave_0_rst_in));
endmodule
|
module score_counter
(
input wire clk, reset,
input wire d_inc, d_dec, d_clr,
// inc -- increase (hit signal)
// dec -- decrease by 2 (kill signal)
// cle -- simple clear signal
output wire [3:0] dig0, dig1
);
// signal declaration
reg [3:0] dig0_reg, dig1_reg, dig0_next, dig1_next;
// well, common sense, hah?
// simple state machine like textbook
// registers
always @(posedge clk, posedge reset)
if (reset)
begin
dig1_reg <= 0;
dig0_reg <= 0;
end
else
begin
dig1_reg <= dig1_next;
dig0_reg <= dig0_next;
end
// next-state logic
always @*
begin
dig0_next = dig0_reg;
dig1_next = dig1_reg;
if (d_clr)
begin
dig0_next = 0;
dig1_next = 0;
end
else if (d_inc)
if (dig0_reg==9)
begin
dig0_next = 0;
if (dig1_reg==9)
dig1_next = 0;
else
dig1_next = dig1_reg + 1;
end
else // dig0 not 9
dig0_next = dig0_reg + 1;
else if (d_dec)
if((dig1_reg == 0) && (dig0_reg < 2))
begin
dig0_next = 0;
dig1_next = 1;
end
else if((dig1_reg > 0) && (dig0_reg == 1))
begin
dig1_next = dig1_reg - 1;
dig0_next = 9;
end
else if((dig1_reg > 0) && (dig0_reg == 0))
begin
dig1_next = dig1_reg - 1;
dig0_next = 8;
end
else
dig0_next = dig0_reg - 2;
end
// output
assign dig0 = dig0_reg;
assign dig1 = dig1_reg;
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: mem_1k.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mem_1k (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [63:0] data;
input [9:0] rdaddress;
input rdclock;
input [9:0] wraddress;
input wrclock;
input wren;
output [63:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({64{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 64,
altsyncram_component.width_b = 64,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "65536"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL data[63..0]
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
// Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL rdaddress[9..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL wraddress[9..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
// Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mem_1k_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
* This module generates a CRC7 value from an incomming bitstream
* the value is generated from bit that is currently shifting out
* The final crc is valid after the last bit is sent, it might be
* necessary to send this value one clock cycle before
*
* this value should be placed in the top bits of the last byte
* CCCCCCC1
* C = CRC bit
*
* Hold in reset when not using
*
* Changes:
* 2015.08.08: Initial Add
*/
module crc7 #(
parameter POLYNOMIAL = 8'h09,
parameter SEED = 8'h00
)(
input clk,
input rst,
input bit,
output reg [6:0] crc,
input en
);
//local parameters
//registes/wires
wire inv;
//submodules
//asynchronous logic
assign inv = bit ^ crc[6]; // XOR required?
//synchronous logic
//XXX: Does this need to be asynchronous?
always @ (posedge clk) begin
if (rst) begin
crc <= SEED;
end
else begin
//Shift the output value
if (en) begin
crc[6] <= crc[5];
crc[5] <= crc[4];
crc[4] <= crc[3];
crc[3] <= crc[2] ^ inv;
crc[2] <= crc[1];
crc[1] <= crc[0];
crc[0] <= inv;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: MossbauerLab
// Engineer: EvilLord666 (Ushakov MV)
//
// Create Date: 23:57:05 08/28/2017
// Design Name:
// Module Name: messbauer_generator
// Project Name: messbauer_test_environment
// Target Devices:
// Tool versions: ISE 14.7
// Description: ALINX AX309 Board Messbauer Generator
//
// Dependencies:
//
// Revision:
// Revision 1.0
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`define START_AND_CHANNEL_SYNC 1
`define CHANNEL_AFTER_MEASURE 2
`define MAX_CHANNEL_NUMBER 4096
`timescale 1 ns / 1 ps
module messbauer_generator #
(
//parameter GCLK_FREQUENCY = 50000000, // maybe will be used in future
parameter GCLK_PERIOD = 20, // nanoseconds
parameter START_DURATION = 50, // number of GCLK periods (aclk port), 1 clock is 20ns
parameter CHANNEL_NUMBER = 512, // is a degree of 2 i.e. 128, 256, 512, 1024 and others smaller than 4096 !
parameter CHANNEL_DURATION = (16 * (`MAX_CHANNEL_NUMBER / CHANNEL_NUMBER)) * 1000 / (2 *GCLK_PERIOD), // channel duration in clock periods
parameter CHANNEL_TYPE = `CHANNEL_AFTER_MEASURE // options are 1) START_AND_CHANNEL_SYNC or 2) CHANNEL_AFTER_MEASURE
)
(
input wire aclk,
input wire areset_n,
output reg start,
output reg channel
);
localparam CHANNEL_GUARD_DURATION = CHANNEL_DURATION - 4 * (1000 / GCLK_PERIOD); // for switch before 4 us
localparam CHANNEL_MEANDR_GUARD_DURATION = CHANNEL_DURATION / 2;
localparam START_HIGH_PHASE_DURATION = 15464 * (1000 / GCLK_PERIOD);
localparam reg[2:0] INITIAL_STATE = 0;
localparam reg[2:0] START_LOW_PHASE_STATE = 1;
localparam reg[2:0] CHANNEL_GENERATION_STATE = 2;
localparam reg[2:0] START_HIGH_PHASE_STATE = 3;
reg[31:0] clk_counter;
reg[2:0] state;
reg[31:0] channel_counter;
always @(posedge aclk)
begin
if(~areset_n)
begin
start <= 1'b1;
channel <= 1'b1;
clk_counter <= 8'b0;
state <= INITIAL_STATE;
end
else
begin
case (state)
INITIAL_STATE:
begin
state <= START_LOW_PHASE_STATE;
clk_counter <= 0;
end
START_LOW_PHASE_STATE:
begin
start <= 0;
channel_counter <= 0;
if(CHANNEL_TYPE == `START_AND_CHANNEL_SYNC && clk_counter == 0)
channel <= 0;
clk_counter <= clk_counter + 1;
if(clk_counter == START_DURATION)
state <= CHANNEL_GENERATION_STATE;
end
CHANNEL_GENERATION_STATE:
begin
start <= 1;
clk_counter <= clk_counter + 1;
if(clk_counter == CHANNEL_GUARD_DURATION)
begin
channel <= ~channel;
end
if(clk_counter == CHANNEL_DURATION)
begin
channel <= ~channel;
channel_counter <= channel_counter + 1;
clk_counter <= 0;
if((channel_counter == CHANNEL_NUMBER - 1 && CHANNEL_TYPE != `START_AND_CHANNEL_SYNC) ||
(channel_counter == CHANNEL_NUMBER && CHANNEL_TYPE == `START_AND_CHANNEL_SYNC))
begin
state <= START_HIGH_PHASE_STATE;
end
end
end
START_HIGH_PHASE_STATE:
begin
start <= 1;
channel <= 1;
clk_counter <= clk_counter + 1;
if(clk_counter == START_HIGH_PHASE_DURATION)
state <= INITIAL_STATE;
end
default:
begin
end
endcase
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jan 22 23:57:55 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_auto_pc_0 -prefix
// design_1_auto_pc_0_ design_1_auto_pc_0_stub.v
// Design : design_1_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4" *)
module design_1_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_r_irf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: bw_r_irf
// Description: Register file with 3 read ports and 2 write ports. Has
// 32 registers per thread with 4 threads. Reading and writing
// the same register concurrently produces x.
*/
//FPGA_SYN enables all FPGA related modifications
`ifdef FPGA_SYN
`define FPGA_SYN_IRF
`endif
`ifdef FPGA_SYN_IRF
`ifdef FPGA_SYN_1THREAD
module bw_r_irf (/*AUTOARG*/
// Outputs
so, irf_byp_rs1_data_d_l, irf_byp_rs2_data_d_l,
irf_byp_rs3_data_d_l, irf_byp_rs3h_data_d_l,
// Inputs
rclk, reset_l, si, se, sehold, rst_tri_en, ifu_exu_tid_s2,
ifu_exu_rs1_s, ifu_exu_rs2_s, ifu_exu_rs3_s, ifu_exu_ren1_s,
ifu_exu_ren2_s, ifu_exu_ren3_s, ecl_irf_wen_w, ecl_irf_wen_w2,
ecl_irf_rd_m, ecl_irf_rd_g, byp_irf_rd_data_w, byp_irf_rd_data_w2,
ecl_irf_tid_m, ecl_irf_tid_g, rml_irf_old_lo_cwp_e,
rml_irf_new_lo_cwp_e, rml_irf_old_e_cwp_e, rml_irf_new_e_cwp_e,
rml_irf_swap_even_e, rml_irf_swap_odd_e, rml_irf_swap_local_e,
rml_irf_kill_restore_w, rml_irf_cwpswap_tid_e, rml_irf_old_agp,
rml_irf_new_agp, rml_irf_swap_global, rml_irf_global_tid
) ;
input rclk;
input reset_l;
input si;
input se;
input sehold;
input rst_tri_en;
input [1:0] ifu_exu_tid_s2; // s stage thread
input [4:0] ifu_exu_rs1_s; // source addresses
input [4:0] ifu_exu_rs2_s;
input [4:0] ifu_exu_rs3_s;
input ifu_exu_ren1_s; // read enables for all 3 ports
input ifu_exu_ren2_s;
input ifu_exu_ren3_s;
input ecl_irf_wen_w; // write enables for both write ports
input ecl_irf_wen_w2;
input [4:0] ecl_irf_rd_m; // w destination
input [4:0] ecl_irf_rd_g; // w2 destination
input [71:0] byp_irf_rd_data_w;// write data from w1
input [71:0] byp_irf_rd_data_w2; // write data from w2
input [1:0] ecl_irf_tid_m; // w stage thread
input [1:0] ecl_irf_tid_g; // w2 thread
input [2:0] rml_irf_old_lo_cwp_e; // current window pointer for locals and odds
input [2:0] rml_irf_new_lo_cwp_e; // target window pointer for locals and odds
input [2:1] rml_irf_old_e_cwp_e; // current window pointer for evens
input [2:1] rml_irf_new_e_cwp_e; // target window pointer for evens
input rml_irf_swap_even_e;
input rml_irf_swap_odd_e;
input rml_irf_swap_local_e;
input rml_irf_kill_restore_w;
input [1:0] rml_irf_cwpswap_tid_e;
input [1:0] rml_irf_old_agp; // alternate global pointer
input [1:0] rml_irf_new_agp; // alternate global pointer
input rml_irf_swap_global;
input [1:0] rml_irf_global_tid;
output so;
output [71:0] irf_byp_rs1_data_d_l;
output [71:0] irf_byp_rs2_data_d_l;
output [71:0] irf_byp_rs3_data_d_l;
output [31:0] irf_byp_rs3h_data_d_l;
wire [71:0] irf_byp_rs1_data_d;
wire [71:0] irf_byp_rs2_data_d;
wire [71:0] irf_byp_rs3_data_d;
wire [71:0] irf_byp_rs3h_data_d;
wire [1:0] ecl_irf_tid_w; // w stage thread
wire [1:0] ecl_irf_tid_w2; // w2 thread
wire [4:0] ecl_irf_rd_w; // w destination
wire [4:0] ecl_irf_rd_w2; // w2 destination
wire [1:0] ifu_exu_thr_d; // d stage thread
wire ifu_exu_ren1_d; // read enables for all 3 ports
wire ifu_exu_ren2_d;
wire ifu_exu_ren3_d;
wire [4:0] ifu_exu_rs1_d; // source addresses
wire [4:0] ifu_exu_rs2_d;
wire [4:0] ifu_exu_rs3_d;
wire [6:0] thr_rs1; // these 5 are a combination of the thr and reg
wire [6:0] thr_rs2; // so that comparison can be done more easily
wire [6:0] thr_rs3;
wire [6:0] thr_rs3h;
wire [6:0] thr_rd_w;
wire [6:0] thr_rd_w2;
reg [1:0] cwpswap_tid_m;
reg [1:0] cwpswap_tid_w;
reg [2:0] old_lo_cwp_m;
reg [2:0] new_lo_cwp_m;
reg [2:0] new_lo_cwp_w;
reg [1:0] old_e_cwp_m;
reg [1:0] new_e_cwp_m;
reg [1:0] new_e_cwp_w;
reg swap_local_m;
reg swap_local_w;
reg swap_even_m;
reg swap_even_w;
reg swap_odd_m;
reg swap_odd_w;
reg kill_restore_d1;
reg swap_global_d1;
reg swap_global_d2;
reg [1:0] global_tid_d1;
reg [1:0] global_tid_d2;
reg [1:0] old_agp_d1,
new_agp_d1,
new_agp_d2;
`ifdef FPGA_SYN_SAVE_BRAM
wire [71:0] active_win_thr_rd_w_neg;
wire [71:0] active_win_thr_rd_w2_neg;
wire [6:0] thr_rd_w_neg;
wire [6:0] thr_rd_w2_neg;
wire active_win_thr_rd_w_neg_wr_en;
wire active_win_thr_rd_w2_neg_wr_en;
wire rst_tri_en_neg;
`else
reg [71:0] active_win_thr_rd_w_neg;
reg [71:0] active_win_thr_rd_w2_neg;
reg [6:0] thr_rd_w_neg;
reg [6:0] thr_rd_w2_neg;
reg active_win_thr_rd_w_neg_wr_en;
reg active_win_thr_rd_w2_neg_wr_en;
reg rst_tri_en_neg;
`endif
wire se;
wire clk;
// assign clk = rclk & reset_l;
assign clk = rclk;
wire ren1_s;
wire ren2_s;
wire ren3_s;
wire [4:0] rs1_s;
wire [4:0] rs2_s;
wire [4:0] rs3_s;
wire [1:0] tid_s;
wire [1:0] tid_g;
wire [1:0] tid_m;
wire [4:0] rd_m;
wire [4:0] rd_g;
wire kill_restore_w;
wire swap_global_d1_vld;
wire swap_local_m_vld;
wire swap_even_m_vld;
wire swap_odd_m_vld;
assign {ren1_s,ren2_s,ren3_s,rs1_s[4:0],rs2_s[4:0],rs3_s[4:0],tid_s[1:0],tid_g[1:0],tid_m[1:0],
rd_m[4:0], rd_g[4:0]} = (sehold)?
{ifu_exu_ren1_d,ifu_exu_ren2_d,ifu_exu_ren3_d,ifu_exu_rs1_d[4:0],ifu_exu_rs2_d[4:0],
ifu_exu_rs3_d[4:0],ifu_exu_thr_d[1:0],ecl_irf_tid_w2[1:0],ecl_irf_tid_w[1:0],
ecl_irf_rd_w[4:0],ecl_irf_rd_w2[4:0]}:
{ifu_exu_ren1_s,ifu_exu_ren2_s,ifu_exu_ren3_s,ifu_exu_rs1_s[4:0],ifu_exu_rs2_s[4:0],
ifu_exu_rs3_s[4:0],ifu_exu_tid_s2[1:0],ecl_irf_tid_g[1:0],ecl_irf_tid_m[1:0],
ecl_irf_rd_m[4:0],ecl_irf_rd_g[4:0]};
// Pipeline flops for irf control signals
dff_s dff_ren1_s2d(.din(ren1_s), .clk(clk), .q(ifu_exu_ren1_d), .se(se),
.si(), .so());
dff_s dff_ren2_s2d(.din(ren2_s), .clk(clk), .q(ifu_exu_ren2_d), .se(se),
.si(), .so());
dff_s dff_ren3_s2d(.din(ren3_s), .clk(clk), .q(ifu_exu_ren3_d), .se(se),
.si(), .so());
dff_s #5 dff_rs1_s2d(.din(rs1_s[4:0]), .clk(clk), .q(ifu_exu_rs1_d[4:0]), .se(se),
.si(),.so());
dff_s #5 dff_rs2_s2d(.din(rs2_s[4:0]), .clk(clk), .q(ifu_exu_rs2_d[4:0]), .se(se),
.si(),.so());
dff_s #5 dff_rs3_s2d(.din(rs3_s[4:0]), .clk(clk), .q(ifu_exu_rs3_d[4:0]), .se(se),
.si(),.so());
dff_s #2 dff_thr_s2d(.din(tid_s[1:0]), .clk(clk), .q(ifu_exu_thr_d[1:0]), .se(se),
.si(),.so());
dff_s #2 dff_thr_g2w2(.din(tid_g[1:0]), .clk(clk), .q(ecl_irf_tid_w2[1:0]), .se(se),
.si(),.so());
dff_s #2 dff_thr_m2w(.din(tid_m[1:0]), .clk(clk), .q(ecl_irf_tid_w[1:0]), .se(se),
.si(),.so());
dff_s #5 dff_rd_m2w(.din(rd_m[4:0]), .clk(clk), .q(ecl_irf_rd_w[4:0]), .se(se),
.si(),.so());
dff_s #5 dff_rd_g2w2(.din(rd_g[4:0]), .clk(clk), .q(ecl_irf_rd_w2[4:0]), .se(se),
.si(),.so());
// Concatenate the thread and rs1/rd bits together
assign thr_rs1[6:0] = {ifu_exu_thr_d, ifu_exu_rs1_d};
assign thr_rs2[6:0] = {ifu_exu_thr_d, ifu_exu_rs2_d};
assign thr_rs3[6:0] = {ifu_exu_thr_d, ifu_exu_rs3_d[4:0]};
assign thr_rs3h[6:0] = {ifu_exu_thr_d[1:0], ifu_exu_rs3_d[4:1], 1'b1};
assign thr_rd_w[6:0] = {ecl_irf_tid_w, ecl_irf_rd_w};
assign thr_rd_w2[6:0] = {ecl_irf_tid_w2, ecl_irf_rd_w2};
// Active low outputs
assign irf_byp_rs1_data_d_l[71:0] = ~irf_byp_rs1_data_d[71:0];
assign irf_byp_rs2_data_d_l[71:0] = ~irf_byp_rs2_data_d[71:0];
assign irf_byp_rs3_data_d_l[71:0] = ~irf_byp_rs3_data_d[71:0];
assign irf_byp_rs3h_data_d_l[31:0] = ~irf_byp_rs3h_data_d[31:0];
/////////////////////////////////////////////////////////////////
/// Write ports
////////////////////////////////////////////////////////////////
// This is a latch that works if both wen is high and clk is low
`ifdef FPGA_SYN_SAVE_BRAM
assign rst_tri_en_neg = rst_tri_en;
assign active_win_thr_rd_w_neg = byp_irf_rd_data_w;
assign active_win_thr_rd_w2_neg = byp_irf_rd_data_w2;
assign thr_rd_w_neg = thr_rd_w;
assign thr_rd_w2_neg = thr_rd_w2;
assign active_win_thr_rd_w_neg_wr_en = ecl_irf_wen_w & (thr_rd_w[4:0] != 5'b0);
assign active_win_thr_rd_w2_neg_wr_en = ecl_irf_wen_w2 & (thr_rd_w2[4:0] != 5'b0);
`else
always @(negedge clk) begin
rst_tri_en_neg <= rst_tri_en;
// write conflict results in X written to destination
if (ecl_irf_wen_w & ecl_irf_wen_w2 & (thr_rd_w[6:0] == thr_rd_w2[6:0])) begin
active_win_thr_rd_w_neg <= {72{1'bx}};
thr_rd_w_neg <= thr_rd_w;
active_win_thr_rd_w_neg_wr_en <= 1'b1;
active_win_thr_rd_w2_neg_wr_en <= 1'b0;
end
else begin
// W1 write port
if (ecl_irf_wen_w & (thr_rd_w[4:0] != 5'b0)) begin
active_win_thr_rd_w_neg <= byp_irf_rd_data_w;
thr_rd_w_neg <= thr_rd_w;
active_win_thr_rd_w_neg_wr_en <= 1'b1;
end
else
active_win_thr_rd_w_neg_wr_en <= 1'b0;
// W2 write port
if (ecl_irf_wen_w2 & (thr_rd_w2[4:0] != 5'b0)) begin
active_win_thr_rd_w2_neg <= byp_irf_rd_data_w2;
thr_rd_w2_neg <= thr_rd_w2;
active_win_thr_rd_w2_neg_wr_en <= 1'b1;
end
else
active_win_thr_rd_w2_neg_wr_en <= 1'b0;
end
end
`endif
/* MOVED TO CMP ENVIRONMENT
initial begin
// Hardcode R0 to zero
active_window[{2'b00, 5'b00000}] = 72'b0;
active_window[{2'b01, 5'b00000}] = 72'b0;
active_window[{2'b10, 5'b00000}] = 72'b0;
active_window[{2'b11, 5'b00000}] = 72'b0;
end
*/
//////////////////////////////////////////////////
// Window management logic
//////////////////////////////////////////////////
// Pipeline flops for control signals
// cwp swap signals
assign kill_restore_w = (sehold)? kill_restore_d1: rml_irf_kill_restore_w;
assign swap_local_m_vld = swap_local_m & ~rst_tri_en;
assign swap_odd_m_vld = swap_odd_m & ~rst_tri_en;
assign swap_even_m_vld = swap_even_m & ~rst_tri_en;
assign swap_global_d1_vld = swap_global_d1 & ~rst_tri_en;
always @ (posedge clk) begin
cwpswap_tid_m[1:0] <= (sehold)? cwpswap_tid_m[1:0]: rml_irf_cwpswap_tid_e[1:0];
cwpswap_tid_w[1:0] <= cwpswap_tid_m[1:0];
old_lo_cwp_m[2:0] <= (sehold)? old_lo_cwp_m[2:0]: rml_irf_old_lo_cwp_e[2:0];
new_lo_cwp_m[2:0] <= (sehold)? new_lo_cwp_m[2:0]: rml_irf_new_lo_cwp_e[2:0];
new_lo_cwp_w[2:0] <= new_lo_cwp_m[2:0];
old_e_cwp_m[1:0] <= (sehold)? old_e_cwp_m[1:0]: rml_irf_old_e_cwp_e[2:1];
new_e_cwp_m[1:0] <= (sehold)? new_e_cwp_m[1:0]: rml_irf_new_e_cwp_e[2:1];
new_e_cwp_w[1:0] <= new_e_cwp_m[1:0];
swap_local_m <= (sehold)? swap_local_m & rst_tri_en: rml_irf_swap_local_e;
swap_local_w <= swap_local_m_vld;
swap_odd_m <= (sehold)? swap_odd_m & rst_tri_en: rml_irf_swap_odd_e;
swap_odd_w <= swap_odd_m_vld;
swap_even_m <= (sehold)? swap_even_m & rst_tri_en: rml_irf_swap_even_e;
swap_even_w <= swap_even_m_vld;
kill_restore_d1 <= kill_restore_w;
end
// global swap signals
always @ (posedge clk) begin
swap_global_d1 <= (sehold)? swap_global_d1 & rst_tri_en: rml_irf_swap_global;
swap_global_d2 <= swap_global_d1_vld;
global_tid_d1[1:0] <= (sehold)? global_tid_d1[1:0]: rml_irf_global_tid[1:0];
global_tid_d2[1:0] <= global_tid_d1[1:0];
old_agp_d1[1:0] <= (sehold)? old_agp_d1[1:0]: rml_irf_old_agp[1:0];
new_agp_d1[1:0] <= (sehold)? new_agp_d1[1:0]: rml_irf_new_agp[1:0];
new_agp_d2[1:0] <= new_agp_d1[1:0];
end
wire wr_en = active_win_thr_rd_w_neg_wr_en & (~rst_tri_en | ~rst_tri_en_neg);
wire wr_en2 = active_win_thr_rd_w2_neg_wr_en & (~rst_tri_en | ~rst_tri_en_neg);
// synthesis translate_off
always @(posedge clk) begin
if(wr_en)
$display("Write Port 1: %h %h", active_win_thr_rd_w_neg, thr_rd_w_neg );
if(wr_en2)
$display("Write Port 2: %h %h", active_win_thr_rd_w2_neg, thr_rd_w2_neg );
if(ifu_exu_ren1_d) begin
@(posedge clk);
$display("Read Port 1: %h %h", irf_byp_rs1_data_d, thr_rs1);
end
if(ifu_exu_ren2_d) begin
@(posedge clk);
$display("Read Port 2: %h %h", irf_byp_rs2_data_d, thr_rs2);
end
if(ifu_exu_ren3_d) begin
@(posedge clk);
$display("Read Port 3: %h %h", irf_byp_rs3_data_d, thr_rs3);
end
end
//synthesis translate_on
bw_r_irf_core bw_r_irf_core (
.clk (clk),
.ifu_exu_ren1_d (ifu_exu_ren1_d),
.ifu_exu_ren2_d (ifu_exu_ren2_d),
.ifu_exu_ren3_d (ifu_exu_ren3_d),
.thr_rs1 (thr_rs1),
.thr_rs2 (thr_rs2),
.thr_rs3 (thr_rs3),
.thr_rs3h (thr_rs3h),
.irf_byp_rs1_data_d (irf_byp_rs1_data_d),
.irf_byp_rs2_data_d (irf_byp_rs2_data_d),
.irf_byp_rs3_data_d (irf_byp_rs3_data_d),
.irf_byp_rs3h_data_d (irf_byp_rs3h_data_d),
.wr_en (wr_en),
.wr_en2 (wr_en2),
.active_win_thr_rd_w_neg(active_win_thr_rd_w_neg),
.active_win_thr_rd_w2_neg(active_win_thr_rd_w2_neg),
.thr_rd_w_neg (thr_rd_w_neg),
.thr_rd_w2_neg (thr_rd_w2_neg),
.swap_global_d1_vld (swap_global_d1_vld),
.swap_global_d2 (swap_global_d2),
.global_tid_d1 (global_tid_d1),
.global_tid_d2 (global_tid_d2),
.old_agp_d1 (old_agp_d1),
.new_agp_d2 (new_agp_d2),
.swap_local_m_vld (swap_local_m_vld),
.swap_local_w (swap_local_w),
.old_lo_cwp_m (old_lo_cwp_m),
.new_lo_cwp_w (new_lo_cwp_w),
.swap_even_m_vld (swap_even_m_vld),
.swap_even_w (swap_even_w),
.old_e_cwp_m (old_e_cwp_m),
.new_e_cwp_w (new_e_cwp_w),
.swap_odd_m_vld (swap_odd_m_vld),
.swap_odd_w (swap_odd_w),
.cwpswap_tid_m (cwpswap_tid_m),
.cwpswap_tid_w (cwpswap_tid_w),
.kill_restore_w (kill_restore_w)
);
endmodule // bw_r_irf
module bw_r_irf_core(
clk,
ifu_exu_ren1_d,
ifu_exu_ren2_d,
ifu_exu_ren3_d,
thr_rs1,
thr_rs2,
thr_rs3,
thr_rs3h,
irf_byp_rs1_data_d,
irf_byp_rs2_data_d,
irf_byp_rs3_data_d,
irf_byp_rs3h_data_d,
wr_en,
wr_en2,
active_win_thr_rd_w_neg,
active_win_thr_rd_w2_neg,
thr_rd_w_neg,
thr_rd_w2_neg,
swap_global_d1_vld,
swap_global_d2,
global_tid_d1,
global_tid_d2,
old_agp_d1,
new_agp_d2,
swap_local_m_vld,
swap_local_w,
old_lo_cwp_m,
new_lo_cwp_w,
swap_even_m_vld,
swap_even_w,
old_e_cwp_m,
new_e_cwp_w,
swap_odd_m_vld,
swap_odd_w,
cwpswap_tid_m,
cwpswap_tid_w,
kill_restore_w);
input clk;
input ifu_exu_ren1_d;
input ifu_exu_ren2_d;
input ifu_exu_ren3_d;
input [6:0] thr_rs1;
input [6:0] thr_rs2;
input [6:0] thr_rs3;
input [6:0] thr_rs3h;
output [71:0] irf_byp_rs1_data_d;
output [71:0] irf_byp_rs2_data_d;
output [71:0] irf_byp_rs3_data_d;
output [71:0] irf_byp_rs3h_data_d;
reg [71:0] irf_byp_rs1_data_d;
reg [71:0] irf_byp_rs2_data_d;
reg [71:0] irf_byp_rs3_data_d;
reg [71:0] irf_byp_rs3h_data_d;
input wr_en;
input wr_en2;
input [71:0] active_win_thr_rd_w_neg;
input [71:0] active_win_thr_rd_w2_neg;
input [6:0] thr_rd_w_neg;
input [6:0] thr_rd_w2_neg;
input swap_global_d1_vld;
input swap_global_d2;
input [1:0] global_tid_d1;
input [1:0] global_tid_d2;
input [1:0] old_agp_d1;
input [1:0] new_agp_d2;
input swap_local_m_vld;
input swap_local_w;
input [2:0] old_lo_cwp_m;
input [2:0] new_lo_cwp_w;
input swap_even_m_vld;
input swap_even_w;
input [1:0] old_e_cwp_m;
input [1:0] new_e_cwp_w;
input swap_odd_m_vld;
input swap_odd_w;
input [1:0] cwpswap_tid_m;
input [1:0] cwpswap_tid_w;
input kill_restore_w;
wire [71:0] rd_data00;
wire [71:0] rd_data01;
wire [71:0] rd_data02;
wire [71:0] rd_data03;
wire [71:0] rd_data04;
wire [71:0] rd_data05;
wire [71:0] rd_data06;
wire [71:0] rd_data07;
wire [71:0] rd_data08;
wire [71:0] rd_data09;
wire [71:0] rd_data10;
wire [71:0] rd_data11;
wire [71:0] rd_data12;
wire [71:0] rd_data13;
wire [71:0] rd_data14;
wire [71:0] rd_data15;
wire [71:0] rd_data16;
wire [71:0] rd_data17;
wire [71:0] rd_data18;
wire [71:0] rd_data19;
wire [71:0] rd_data20;
wire [71:0] rd_data21;
wire [71:0] rd_data22;
wire [71:0] rd_data23;
wire [71:0] rd_data24;
wire [71:0] rd_data25;
wire [71:0] rd_data26;
wire [71:0] rd_data27;
wire [71:0] rd_data28;
wire [71:0] rd_data29;
wire [71:0] rd_data30;
wire [71:0] rd_data31;
// synthesis translate_off
always @(posedge clk) begin
if(ifu_exu_ren1_d | ifu_exu_ren2_d | ifu_exu_ren3_d) begin
if(thr_rs1[6:5] != 2'b00) begin
$display("Accessing thread # other than 0");
$finish;
end
end
end
// synthesis translate_on
//reg [71:0] active_window [127:0];// 32x4 72 bit registers
always @(negedge clk)
if(ifu_exu_ren1_d) //comes from a posedge clk
case(thr_rs1[4:0])
5'b00000: irf_byp_rs1_data_d <= rd_data00;
5'b00001: irf_byp_rs1_data_d <= rd_data01;
5'b00010: irf_byp_rs1_data_d <= rd_data02;
5'b00011: irf_byp_rs1_data_d <= rd_data03;
5'b00100: irf_byp_rs1_data_d <= rd_data04;
5'b00101: irf_byp_rs1_data_d <= rd_data05;
5'b00110: irf_byp_rs1_data_d <= rd_data06;
5'b00111: irf_byp_rs1_data_d <= rd_data07;
5'b01000: irf_byp_rs1_data_d <= rd_data08;
5'b01001: irf_byp_rs1_data_d <= rd_data09;
5'b01010: irf_byp_rs1_data_d <= rd_data10;
5'b01011: irf_byp_rs1_data_d <= rd_data11;
5'b01100: irf_byp_rs1_data_d <= rd_data12;
5'b01101: irf_byp_rs1_data_d <= rd_data13;
5'b01110: irf_byp_rs1_data_d <= rd_data14;
5'b01111: irf_byp_rs1_data_d <= rd_data15;
5'b10000: irf_byp_rs1_data_d <= rd_data16;
5'b10001: irf_byp_rs1_data_d <= rd_data17;
5'b10010: irf_byp_rs1_data_d <= rd_data18;
5'b10011: irf_byp_rs1_data_d <= rd_data19;
5'b10100: irf_byp_rs1_data_d <= rd_data20;
5'b10101: irf_byp_rs1_data_d <= rd_data21;
5'b10110: irf_byp_rs1_data_d <= rd_data22;
5'b10111: irf_byp_rs1_data_d <= rd_data23;
5'b11000: irf_byp_rs1_data_d <= rd_data24;
5'b11001: irf_byp_rs1_data_d <= rd_data25;
5'b11010: irf_byp_rs1_data_d <= rd_data26;
5'b11011: irf_byp_rs1_data_d <= rd_data27;
5'b11100: irf_byp_rs1_data_d <= rd_data28;
5'b11101: irf_byp_rs1_data_d <= rd_data29;
5'b11110: irf_byp_rs1_data_d <= rd_data30;
5'b11111: irf_byp_rs1_data_d <= rd_data31;
endcase
always @(negedge clk)
if(ifu_exu_ren2_d)
case(thr_rs2[4:0])
5'b00000: irf_byp_rs2_data_d <= rd_data00;
5'b00001: irf_byp_rs2_data_d <= rd_data01;
5'b00010: irf_byp_rs2_data_d <= rd_data02;
5'b00011: irf_byp_rs2_data_d <= rd_data03;
5'b00100: irf_byp_rs2_data_d <= rd_data04;
5'b00101: irf_byp_rs2_data_d <= rd_data05;
5'b00110: irf_byp_rs2_data_d <= rd_data06;
5'b00111: irf_byp_rs2_data_d <= rd_data07;
5'b01000: irf_byp_rs2_data_d <= rd_data08;
5'b01001: irf_byp_rs2_data_d <= rd_data09;
5'b01010: irf_byp_rs2_data_d <= rd_data10;
5'b01011: irf_byp_rs2_data_d <= rd_data11;
5'b01100: irf_byp_rs2_data_d <= rd_data12;
5'b01101: irf_byp_rs2_data_d <= rd_data13;
5'b01110: irf_byp_rs2_data_d <= rd_data14;
5'b01111: irf_byp_rs2_data_d <= rd_data15;
5'b10000: irf_byp_rs2_data_d <= rd_data16;
5'b10001: irf_byp_rs2_data_d <= rd_data17;
5'b10010: irf_byp_rs2_data_d <= rd_data18;
5'b10011: irf_byp_rs2_data_d <= rd_data19;
5'b10100: irf_byp_rs2_data_d <= rd_data20;
5'b10101: irf_byp_rs2_data_d <= rd_data21;
5'b10110: irf_byp_rs2_data_d <= rd_data22;
5'b10111: irf_byp_rs2_data_d <= rd_data23;
5'b11000: irf_byp_rs2_data_d <= rd_data24;
5'b11001: irf_byp_rs2_data_d <= rd_data25;
5'b11010: irf_byp_rs2_data_d <= rd_data26;
5'b11011: irf_byp_rs2_data_d <= rd_data27;
5'b11100: irf_byp_rs2_data_d <= rd_data28;
5'b11101: irf_byp_rs2_data_d <= rd_data29;
5'b11110: irf_byp_rs2_data_d <= rd_data30;
5'b11111: irf_byp_rs2_data_d <= rd_data31;
endcase
always @(negedge clk)
if(ifu_exu_ren3_d)
case(thr_rs3[4:0])
5'b00000: irf_byp_rs3_data_d <= rd_data00;
5'b00001: irf_byp_rs3_data_d <= rd_data01;
5'b00010: irf_byp_rs3_data_d <= rd_data02;
5'b00011: irf_byp_rs3_data_d <= rd_data03;
5'b00100: irf_byp_rs3_data_d <= rd_data04;
5'b00101: irf_byp_rs3_data_d <= rd_data05;
5'b00110: irf_byp_rs3_data_d <= rd_data06;
5'b00111: irf_byp_rs3_data_d <= rd_data07;
5'b01000: irf_byp_rs3_data_d <= rd_data08;
5'b01001: irf_byp_rs3_data_d <= rd_data09;
5'b01010: irf_byp_rs3_data_d <= rd_data10;
5'b01011: irf_byp_rs3_data_d <= rd_data11;
5'b01100: irf_byp_rs3_data_d <= rd_data12;
5'b01101: irf_byp_rs3_data_d <= rd_data13;
5'b01110: irf_byp_rs3_data_d <= rd_data14;
5'b01111: irf_byp_rs3_data_d <= rd_data15;
5'b10000: irf_byp_rs3_data_d <= rd_data16;
5'b10001: irf_byp_rs3_data_d <= rd_data17;
5'b10010: irf_byp_rs3_data_d <= rd_data18;
5'b10011: irf_byp_rs3_data_d <= rd_data19;
5'b10100: irf_byp_rs3_data_d <= rd_data20;
5'b10101: irf_byp_rs3_data_d <= rd_data21;
5'b10110: irf_byp_rs3_data_d <= rd_data22;
5'b10111: irf_byp_rs3_data_d <= rd_data23;
5'b11000: irf_byp_rs3_data_d <= rd_data24;
5'b11001: irf_byp_rs3_data_d <= rd_data25;
5'b11010: irf_byp_rs3_data_d <= rd_data26;
5'b11011: irf_byp_rs3_data_d <= rd_data27;
5'b11100: irf_byp_rs3_data_d <= rd_data28;
5'b11101: irf_byp_rs3_data_d <= rd_data29;
5'b11110: irf_byp_rs3_data_d <= rd_data30;
5'b11111: irf_byp_rs3_data_d <= rd_data31;
endcase
always @(negedge clk)
if(ifu_exu_ren3_d)
case(thr_rs3h[4:1])
4'b0000: irf_byp_rs3h_data_d <= rd_data01;
4'b0001: irf_byp_rs3h_data_d <= rd_data03;
4'b0010: irf_byp_rs3h_data_d <= rd_data05;
4'b0011: irf_byp_rs3h_data_d <= rd_data07;
4'b0100: irf_byp_rs3h_data_d <= rd_data09;
4'b0101: irf_byp_rs3h_data_d <= rd_data11;
4'b0110: irf_byp_rs3h_data_d <= rd_data13;
4'b0111: irf_byp_rs3h_data_d <= rd_data15;
4'b1000: irf_byp_rs3h_data_d <= rd_data17;
4'b1001: irf_byp_rs3h_data_d <= rd_data19;
4'b1010: irf_byp_rs3h_data_d <= rd_data21;
4'b1011: irf_byp_rs3h_data_d <= rd_data23;
4'b1100: irf_byp_rs3h_data_d <= rd_data25;
4'b1101: irf_byp_rs3h_data_d <= rd_data27;
4'b1110: irf_byp_rs3h_data_d <= rd_data29;
4'b1111: irf_byp_rs3h_data_d <= rd_data31;
endcase
wire wren = wr_en | wr_en2;
wire [4:0] wr_addr = wr_en ? thr_rd_w_neg[4:0] : thr_rd_w2_neg[4:0];
wire [71:0] wr_data = wr_en ? active_win_thr_rd_w_neg : active_win_thr_rd_w2_neg;
//GLOBALs
bw_r_irf_register register00(
.clk(clk),
.wren(wren & (wr_addr == 5'b00000)),
.save(swap_global_d1_vld),
.save_addr({1'b0,old_agp_d1[1:0]}),
.restore(swap_global_d2),
.restore_addr({1'b0,new_agp_d2[1:0]}),
.wr_data(72'b0),
.rd_data(rd_data00)
);
bw_r_irf_register register01(
.clk(clk),
.wren(wren & (wr_addr == 5'b00001)),
.save(swap_global_d1_vld),
.save_addr({1'b0,old_agp_d1[1:0]}),
.restore(swap_global_d2),
.restore_addr({1'b0,new_agp_d2[1:0]}),
.wr_data(wr_data),
.rd_data(rd_data01)
);
bw_r_irf_register register02(
.clk(clk),
.wren(wren & (wr_addr == 5'b00010)),
.save(swap_global_d1_vld),
.save_addr({1'b0,old_agp_d1[1:0]}),
.restore(swap_global_d2),
.restore_addr({1'b0,new_agp_d2[1:0]}),
.wr_data(wr_data),
.rd_data(rd_data02)
);
bw_r_irf_register register03(
.clk(clk),
.wren(wren & (wr_addr == 5'b00011)),
.save(swap_global_d1_vld),
.save_addr({1'b0,old_agp_d1[1:0]}),
.restore(swap_global_d2),
.restore_addr({1'b0,new_agp_d2[1:0]}),
.wr_data(wr_data),
.rd_data(rd_data03)
);
bw_r_irf_register register04(
.clk(clk),
.wren(wren & (wr_addr == 5'b00100)),
.save(swap_global_d1_vld),
.save_addr({1'b0,old_agp_d1[1:0]}),
.restore(swap_global_d2),
.restore_addr({1'b0,new_agp_d2[1:0]}),
.wr_data(wr_data),
.rd_data(rd_data04)
);
bw_r_irf_register register05(
.clk(clk),
.wren(wren & (wr_addr == 5'b00101)),
.save(swap_global_d1_vld),
.save_addr({1'b0,old_agp_d1[1:0]}),
.restore(swap_global_d2),
.restore_addr({1'b0,new_agp_d2[1:0]}),
.wr_data(wr_data),
.rd_data(rd_data05)
);
bw_r_irf_register register06(
.clk(clk),
.wren(wren & (wr_addr == 5'b00110)),
.save(swap_global_d1_vld),
.save_addr({1'b0,old_agp_d1[1:0]}),
.restore(swap_global_d2),
.restore_addr({1'b0,new_agp_d2[1:0]}),
.wr_data(wr_data),
.rd_data(rd_data06)
);
bw_r_irf_register register07(
.clk(clk),
.wren(wren & (wr_addr == 5'b00111)),
.save(swap_global_d1_vld),
.save_addr({1'b0,old_agp_d1[1:0]}),
.restore(swap_global_d2),
.restore_addr({1'b0,new_agp_d2[1:0]}),
.wr_data(wr_data),
.rd_data(rd_data07)
);
//ODDs
bw_r_irf_register register08(
.clk(clk),
.wren(wren & (wr_addr == 5'b01000)),
.save(swap_odd_m_vld),
.save_addr({1'b0,old_lo_cwp_m[2:1]}),
.restore(swap_odd_w & ~kill_restore_w),
.restore_addr({1'b0,new_lo_cwp_w[2:1]}),
.wr_data(wr_data),
.rd_data(rd_data08)
);
bw_r_irf_register register09(
.clk(clk),
.wren(wren & (wr_addr == 5'b01001)),
.save(swap_odd_m_vld),
.save_addr({1'b0,old_lo_cwp_m[2:1]}),
.restore(swap_odd_w & ~kill_restore_w),
.restore_addr({1'b0,new_lo_cwp_w[2:1]}),
.wr_data(wr_data),
.rd_data(rd_data09)
);
bw_r_irf_register register10(
.clk(clk),
.wren(wren & (wr_addr == 5'b01010)),
.save(swap_odd_m_vld),
.save_addr({1'b0,old_lo_cwp_m[2:1]}),
.restore(swap_odd_w & ~kill_restore_w),
.restore_addr({1'b0,new_lo_cwp_w[2:1]}),
.wr_data(wr_data),
.rd_data(rd_data10)
);
bw_r_irf_register register11(
.clk(clk),
.wren(wren & (wr_addr == 5'b01011)),
.save(swap_odd_m_vld),
.save_addr({1'b0,old_lo_cwp_m[2:1]}),
.restore(swap_odd_w & ~kill_restore_w),
.restore_addr({1'b0,new_lo_cwp_w[2:1]}),
.wr_data(wr_data),
.rd_data(rd_data11)
);
bw_r_irf_register register12(
.clk(clk),
.wren(wren & (wr_addr == 5'b01100)),
.save(swap_odd_m_vld),
.save_addr({1'b0,old_lo_cwp_m[2:1]}),
.restore(swap_odd_w & ~kill_restore_w),
.restore_addr({1'b0,new_lo_cwp_w[2:1]}),
.wr_data(wr_data),
.rd_data(rd_data12)
);
bw_r_irf_register register13(
.clk(clk),
.wren(wren & (wr_addr == 5'b01101)),
.save(swap_odd_m_vld),
.save_addr({1'b0,old_lo_cwp_m[2:1]}),
.restore(swap_odd_w & ~kill_restore_w),
.restore_addr({1'b0,new_lo_cwp_w[2:1]}),
.wr_data(wr_data),
.rd_data(rd_data13)
);
bw_r_irf_register register14(
.clk(clk),
.wren(wren & (wr_addr == 5'b01110)),
.save(swap_odd_m_vld),
.save_addr({1'b0,old_lo_cwp_m[2:1]}),
.restore(swap_odd_w & ~kill_restore_w),
.restore_addr({1'b0,new_lo_cwp_w[2:1]}),
.wr_data(wr_data),
.rd_data(rd_data14)
);
bw_r_irf_register register15(
.clk(clk),
.wren(wren & (wr_addr == 5'b01111)),
.save(swap_odd_m_vld),
.save_addr({1'b0,old_lo_cwp_m[2:1]}),
.restore(swap_odd_w & ~kill_restore_w),
.restore_addr({1'b0,new_lo_cwp_w[2:1]}),
.wr_data(wr_data),
.rd_data(rd_data15)
);
//LOCALs
bw_r_irf_register register16(
.clk(clk),
.wren(wren & (wr_addr == 5'b10000)),
.save(swap_local_m_vld),
.save_addr({old_lo_cwp_m[2:0]}),
.restore(swap_local_w & ~kill_restore_w),
.restore_addr({new_lo_cwp_w[2:0]}),
.wr_data(wr_data),
.rd_data(rd_data16)
);
bw_r_irf_register register17(
.clk(clk),
.wren(wren & (wr_addr == 5'b10001)),
.save(swap_local_m_vld),
.save_addr({old_lo_cwp_m[2:0]}),
.restore(swap_local_w & ~kill_restore_w),
.restore_addr({new_lo_cwp_w[2:0]}),
.wr_data(wr_data),
.rd_data(rd_data17)
);
bw_r_irf_register register18(
.clk(clk),
.wren(wren & (wr_addr == 5'b10010)),
.save(swap_local_m_vld),
.save_addr({old_lo_cwp_m[2:0]}),
.restore(swap_local_w & ~kill_restore_w),
.restore_addr({new_lo_cwp_w[2:0]}),
.wr_data(wr_data),
.rd_data(rd_data18)
);
bw_r_irf_register register19(
.clk(clk),
.wren(wren & (wr_addr == 5'b10011)),
.save(swap_local_m_vld),
.save_addr({old_lo_cwp_m[2:0]}),
.restore(swap_local_w & ~kill_restore_w),
.restore_addr({new_lo_cwp_w[2:0]}),
.wr_data(wr_data),
.rd_data(rd_data19)
);
bw_r_irf_register register20(
.clk(clk),
.wren(wren & (wr_addr == 5'b10100)),
.save(swap_local_m_vld),
.save_addr({old_lo_cwp_m[2:0]}),
.restore(swap_local_w & ~kill_restore_w),
.restore_addr({new_lo_cwp_w[2:0]}),
.wr_data(wr_data),
.rd_data(rd_data20)
);
bw_r_irf_register register21(
.clk(clk),
.wren(wren & (wr_addr == 5'b10101)),
.save(swap_local_m_vld),
.save_addr({old_lo_cwp_m[2:0]}),
.restore(swap_local_w & ~kill_restore_w),
.restore_addr({new_lo_cwp_w[2:0]}),
.wr_data(wr_data),
.rd_data(rd_data21)
);
bw_r_irf_register register22(
.clk(clk),
.wren(wren & (wr_addr == 5'b10110)),
.save(swap_local_m_vld),
.save_addr({old_lo_cwp_m[2:0]}),
.restore(swap_local_w & ~kill_restore_w),
.restore_addr({new_lo_cwp_w[2:0]}),
.wr_data(wr_data),
.rd_data(rd_data22)
);
bw_r_irf_register register23(
.clk(clk),
.wren(wren & (wr_addr == 5'b10111)),
.save(swap_local_m_vld),
.save_addr({old_lo_cwp_m[2:0]}),
.restore(swap_local_w & ~kill_restore_w),
.restore_addr({new_lo_cwp_w[2:0]}),
.wr_data(wr_data),
.rd_data(rd_data23)
);
//EVENs
bw_r_irf_register register24(
.clk(clk),
.wren(wren & (wr_addr == 5'b11000)),
.save(swap_even_m_vld),
.save_addr({1'b0,old_e_cwp_m[1:0]}),
.restore(swap_even_w & ~kill_restore_w),
.restore_addr({1'b0,new_e_cwp_w[1:0]}),
.wr_data(wr_data),
.rd_data(rd_data24)
);
bw_r_irf_register register25(
.clk(clk),
.wren(wren & (wr_addr == 5'b11001)),
.save(swap_even_m_vld),
.save_addr({1'b0,old_e_cwp_m[1:0]}),
.restore(swap_even_w & ~kill_restore_w),
.restore_addr({1'b0,new_e_cwp_w[1:0]}),
.wr_data(wr_data),
.rd_data(rd_data25)
);
bw_r_irf_register register26(
.clk(clk),
.wren(wren & (wr_addr == 5'b11010)),
.save(swap_even_m_vld),
.save_addr({1'b0,old_e_cwp_m[1:0]}),
.restore(swap_even_w & ~kill_restore_w),
.restore_addr({1'b0,new_e_cwp_w[1:0]}),
.wr_data(wr_data),
.rd_data(rd_data26)
);
bw_r_irf_register register27(
.clk(clk),
.wren(wren & (wr_addr == 5'b11011)),
.save(swap_even_m_vld),
.save_addr({1'b0,old_e_cwp_m[1:0]}),
.restore(swap_even_w & ~kill_restore_w),
.restore_addr({1'b0,new_e_cwp_w[1:0]}),
.wr_data(wr_data),
.rd_data(rd_data27)
);
bw_r_irf_register register28(
.clk(clk),
.wren(wren & (wr_addr == 5'b11100)),
.save(swap_even_m_vld),
.save_addr({1'b0,old_e_cwp_m[1:0]}),
.restore(swap_even_w & ~kill_restore_w),
.restore_addr({1'b0,new_e_cwp_w[1:0]}),
.wr_data(wr_data),
.rd_data(rd_data28)
);
bw_r_irf_register register29(
.clk(clk),
.wren(wren & (wr_addr == 5'b11101)),
.save(swap_even_m_vld),
.save_addr({1'b0,old_e_cwp_m[1:0]}),
.restore(swap_even_w & ~kill_restore_w),
.restore_addr({1'b0,new_e_cwp_w[1:0]}),
.wr_data(wr_data),
.rd_data(rd_data29)
);
bw_r_irf_register register30(
.clk(clk),
.wren(wren & (wr_addr == 5'b11110)),
.save(swap_even_m_vld),
.save_addr({1'b0,old_e_cwp_m[1:0]}),
.restore(swap_even_w & ~kill_restore_w),
.restore_addr({1'b0,new_e_cwp_w[1:0]}),
.wr_data(wr_data),
.rd_data(rd_data30)
);
bw_r_irf_register register31(
.clk(clk),
.wren(wren & (wr_addr == 5'b11111)),
.save(swap_even_m_vld),
.save_addr({1'b0,old_e_cwp_m[1:0]}),
.restore(swap_even_w & ~kill_restore_w),
.restore_addr({1'b0,new_e_cwp_w[1:0]}),
.wr_data(wr_data),
.rd_data(rd_data31)
);
endmodule
`else
module bw_r_irf(so, irf_byp_rs1_data_d_l, irf_byp_rs2_data_d_l,
irf_byp_rs3_data_d_l, irf_byp_rs3h_data_d_l, rclk, reset_l, si, se,
sehold, rst_tri_en, ifu_exu_tid_s2, ifu_exu_rs1_s, ifu_exu_rs2_s,
ifu_exu_rs3_s, ifu_exu_ren1_s, ifu_exu_ren2_s, ifu_exu_ren3_s,
ecl_irf_wen_w, ecl_irf_wen_w2, ecl_irf_rd_m, ecl_irf_rd_g,
byp_irf_rd_data_w, byp_irf_rd_data_w2, ecl_irf_tid_m, ecl_irf_tid_g,
rml_irf_old_lo_cwp_e, rml_irf_new_lo_cwp_e, rml_irf_old_e_cwp_e,
rml_irf_new_e_cwp_e, rml_irf_swap_even_e, rml_irf_swap_odd_e,
rml_irf_swap_local_e, rml_irf_kill_restore_w, rml_irf_cwpswap_tid_e,
rml_irf_old_agp, rml_irf_new_agp, rml_irf_swap_global,
rml_irf_global_tid);
input rclk;
input reset_l;
input si;
input se;
input sehold;
input rst_tri_en;
input [1:0] ifu_exu_tid_s2;
input [4:0] ifu_exu_rs1_s;
input [4:0] ifu_exu_rs2_s;
input [4:0] ifu_exu_rs3_s;
input ifu_exu_ren1_s;
input ifu_exu_ren2_s;
input ifu_exu_ren3_s;
input ecl_irf_wen_w;
input ecl_irf_wen_w2;
input [4:0] ecl_irf_rd_m;
input [4:0] ecl_irf_rd_g;
input [71:0] byp_irf_rd_data_w;
input [71:0] byp_irf_rd_data_w2;
input [1:0] ecl_irf_tid_m;
input [1:0] ecl_irf_tid_g;
input [2:0] rml_irf_old_lo_cwp_e;
input [2:0] rml_irf_new_lo_cwp_e;
input [2:1] rml_irf_old_e_cwp_e;
input [2:1] rml_irf_new_e_cwp_e;
input rml_irf_swap_even_e;
input rml_irf_swap_odd_e;
input rml_irf_swap_local_e;
input rml_irf_kill_restore_w;
input [1:0] rml_irf_cwpswap_tid_e;
input [1:0] rml_irf_old_agp;
input [1:0] rml_irf_new_agp;
input rml_irf_swap_global;
input [1:0] rml_irf_global_tid;
output so;
output [71:0] irf_byp_rs1_data_d_l;
output [71:0] irf_byp_rs2_data_d_l;
output [71:0] irf_byp_rs3_data_d_l;
output [31:0] irf_byp_rs3h_data_d_l;
wire [71:0] irf_byp_rs1_data_d;
wire [71:0] irf_byp_rs2_data_d;
wire [71:0] irf_byp_rs3_data_d;
wire [71:0] irf_byp_rs3h_data_d;
wire [1:0] ecl_irf_tid_w;
wire [1:0] ecl_irf_tid_w2;
wire [4:0] ecl_irf_rd_w;
wire [4:0] ecl_irf_rd_w2;
wire [1:0] ifu_exu_thr_d;
wire ifu_exu_ren1_d;
wire ifu_exu_ren2_d;
wire ifu_exu_ren3_d;
wire [4:0] ifu_exu_rs1_d;
wire [4:0] ifu_exu_rs2_d;
wire [4:0] ifu_exu_rs3_d;
wire [6:0] thr_rs1;
wire [6:0] thr_rs2;
wire [6:0] thr_rs3;
wire [6:0] thr_rs3h;
wire [6:0] thr_rd_w;
wire [6:0] thr_rd_w2;
reg [1:0] cwpswap_tid_m;
reg [1:0] cwpswap_tid_w;
reg [2:0] old_lo_cwp_m;
reg [2:0] new_lo_cwp_m;
reg [2:0] new_lo_cwp_w;
reg [1:0] old_e_cwp_m;
reg [1:0] new_e_cwp_m;
reg [1:0] new_e_cwp_w;
reg swap_local_m;
reg swap_local_w;
reg swap_even_m;
reg swap_even_w;
reg swap_odd_m;
reg swap_odd_w;
reg kill_restore_d1;
reg swap_global_d1;
reg swap_global_d2;
reg [1:0] global_tid_d1;
reg [1:0] global_tid_d2;
reg [1:0] old_agp_d1;
reg [1:0] new_agp_d1;
reg [1:0] new_agp_d2;
reg [71:0] active_win_thr_rd_w_neg;
reg [71:0] active_win_thr_rd_w2_neg;
reg [6:0] thr_rd_w_neg;
reg [6:0] thr_rd_w2_neg;
reg active_win_thr_rd_w_neg_wr_en;
reg active_win_thr_rd_w2_neg_wr_en;
reg rst_tri_en_neg;
wire clk;
wire ren1_s;
wire ren2_s;
wire ren3_s;
wire [4:0] rs1_s;
wire [4:0] rs2_s;
wire [4:0] rs3_s;
wire [1:0] tid_s;
wire [1:0] tid_g;
wire [1:0] tid_m;
wire [4:0] rd_m;
wire [4:0] rd_g;
wire kill_restore_w;
wire swap_global_d1_vld;
wire swap_local_m_vld;
wire swap_even_m_vld;
wire swap_odd_m_vld;
wire wr_en;
wire wr_en2;
assign clk = rclk;
assign {ren1_s, ren2_s, ren3_s, rs1_s[4:0], rs2_s[4:0], rs3_s[4:0],
tid_s[1:0], tid_g[1:0], tid_m[1:0], rd_m[4:0], rd_g[4:0]} = (
sehold ? {ifu_exu_ren1_d, ifu_exu_ren2_d, ifu_exu_ren3_d,
ifu_exu_rs1_d[4:0], ifu_exu_rs2_d[4:0], ifu_exu_rs3_d[4:0],
ifu_exu_thr_d[1:0], ecl_irf_tid_w2[1:0], ecl_irf_tid_w[1:0],
ecl_irf_rd_w[4:0], ecl_irf_rd_w2[4:0]} : {ifu_exu_ren1_s,
ifu_exu_ren2_s, ifu_exu_ren3_s, ifu_exu_rs1_s[4:0],
ifu_exu_rs2_s[4:0], ifu_exu_rs3_s[4:0], ifu_exu_tid_s2[1:0],
ecl_irf_tid_g[1:0], ecl_irf_tid_m[1:0], ecl_irf_rd_m[4:0],
ecl_irf_rd_g[4:0]});
assign thr_rs1[6:0] = {ifu_exu_thr_d, ifu_exu_rs1_d};
assign thr_rs2[6:0] = {ifu_exu_thr_d, ifu_exu_rs2_d};
assign thr_rs3[6:0] = {ifu_exu_thr_d, ifu_exu_rs3_d[4:0]};
assign thr_rs3h[6:0] = {ifu_exu_thr_d[1:0], ifu_exu_rs3_d[4:1], 1'b1};
assign thr_rd_w[6:0] = {ecl_irf_tid_w, ecl_irf_rd_w};
assign thr_rd_w2[6:0] = {ecl_irf_tid_w2, ecl_irf_rd_w2};
assign irf_byp_rs1_data_d_l[71:0] = (~irf_byp_rs1_data_d[71:0]);
assign irf_byp_rs2_data_d_l[71:0] = (~irf_byp_rs2_data_d[71:0]);
assign irf_byp_rs3_data_d_l[71:0] = (~irf_byp_rs3_data_d[71:0]);
assign irf_byp_rs3h_data_d_l[31:0] = (~irf_byp_rs3h_data_d[31:0]);
assign kill_restore_w = (sehold ? kill_restore_d1 :
rml_irf_kill_restore_w);
assign swap_local_m_vld = (swap_local_m & (~rst_tri_en));
assign swap_odd_m_vld = (swap_odd_m & (~rst_tri_en));
assign swap_even_m_vld = (swap_even_m & (~rst_tri_en));
assign swap_global_d1_vld = (swap_global_d1 & (~rst_tri_en));
assign wr_en = (active_win_thr_rd_w_neg_wr_en & ((~rst_tri_en) | (~
rst_tri_en_neg)));
assign wr_en2 = (active_win_thr_rd_w2_neg_wr_en & ((~rst_tri_en) | (~
rst_tri_en_neg)));
dff_s dff_ren1_s2d(
.din (ren1_s),
.clk (clk),
.q (ifu_exu_ren1_d),
.se (se));
dff_s dff_ren2_s2d(
.din (ren2_s),
.clk (clk),
.q (ifu_exu_ren2_d),
.se (se));
dff_s dff_ren3_s2d(
.din (ren3_s),
.clk (clk),
.q (ifu_exu_ren3_d),
.se (se));
dff_s #(5) dff_rs1_s2d(
.din (rs1_s[4:0]),
.clk (clk),
.q (ifu_exu_rs1_d[4:0]),
.se (se));
dff_s #(5) dff_rs2_s2d(
.din (rs2_s[4:0]),
.clk (clk),
.q (ifu_exu_rs2_d[4:0]),
.se (se));
dff_s #(5) dff_rs3_s2d(
.din (rs3_s[4:0]),
.clk (clk),
.q (ifu_exu_rs3_d[4:0]),
.se (se));
dff_s #(2) dff_thr_s2d(
.din (tid_s[1:0]),
.clk (clk),
.q (ifu_exu_thr_d[1:0]),
.se (se));
dff_s #(2) dff_thr_g2w2(
.din (tid_g[1:0]),
.clk (clk),
.q (ecl_irf_tid_w2[1:0]),
.se (se));
dff_s #(2) dff_thr_m2w(
.din (tid_m[1:0]),
.clk (clk),
.q (ecl_irf_tid_w[1:0]),
.se (se));
dff_s #(5) dff_rd_m2w(
.din (rd_m[4:0]),
.clk (clk),
.q (ecl_irf_rd_w[4:0]),
.se (se));
dff_s #(5) dff_rd_g2w2(
.din (rd_g[4:0]),
.clk (clk),
.q (ecl_irf_rd_w2[4:0]),
.se (se));
bw_r_irf_core bw_r_irf_core(
.clk (clk),
.ifu_exu_ren1_d (ifu_exu_ren1_d),
.ifu_exu_ren2_d (ifu_exu_ren2_d),
.ifu_exu_ren3_d (ifu_exu_ren3_d),
.thr_rs1 (thr_rs1),
.thr_rs2 (thr_rs2),
.thr_rs3 (thr_rs3),
.thr_rs3h (thr_rs3h),
.irf_byp_rs1_data_d (irf_byp_rs1_data_d),
.irf_byp_rs2_data_d (irf_byp_rs2_data_d),
.irf_byp_rs3_data_d (irf_byp_rs3_data_d),
.irf_byp_rs3h_data_d (irf_byp_rs3h_data_d),
.wr_en (wr_en),
.wr_en2 (wr_en2),
.active_win_thr_rd_w_neg (active_win_thr_rd_w_neg),
.active_win_thr_rd_w2_neg (active_win_thr_rd_w2_neg),
.thr_rd_w_neg (thr_rd_w_neg),
.thr_rd_w2_neg (thr_rd_w2_neg),
.swap_global_d1_vld (swap_global_d1_vld),
.swap_global_d2 (swap_global_d2),
.global_tid_d1 (global_tid_d1),
.global_tid_d2 (global_tid_d2),
.old_agp_d1 (old_agp_d1),
.new_agp_d2 (new_agp_d2),
.swap_local_m_vld (swap_local_m_vld),
.swap_local_w (swap_local_w),
.old_lo_cwp_m (old_lo_cwp_m),
.new_lo_cwp_w (new_lo_cwp_w),
.swap_even_m_vld (swap_even_m_vld),
.swap_even_w (swap_even_w),
.old_e_cwp_m (old_e_cwp_m),
.new_e_cwp_w (new_e_cwp_w),
.swap_odd_m_vld (swap_odd_m_vld),
.swap_odd_w (swap_odd_w),
.cwpswap_tid_m (cwpswap_tid_m),
.cwpswap_tid_w (cwpswap_tid_w),
.kill_restore_w (kill_restore_w));
always @(negedge clk) begin
rst_tri_en_neg <= rst_tri_en;
if ((ecl_irf_wen_w & ecl_irf_wen_w2) & (thr_rd_w[6:0] ==
thr_rd_w2[6:0])) begin
active_win_thr_rd_w_neg <= {72 {1'bx}};
thr_rd_w_neg <= thr_rd_w;
active_win_thr_rd_w_neg_wr_en <= 1'b1;
active_win_thr_rd_w2_neg_wr_en <= 1'b0;
end
else
begin
if (ecl_irf_wen_w & (thr_rd_w[4:0] != 5'b0)) begin
active_win_thr_rd_w_neg <= byp_irf_rd_data_w;
thr_rd_w_neg <= thr_rd_w;
active_win_thr_rd_w_neg_wr_en <= 1'b1;
end
else begin
active_win_thr_rd_w_neg_wr_en <= 1'b0;
end
if (ecl_irf_wen_w2 & (thr_rd_w2[4:0] != 5'b0)) begin
active_win_thr_rd_w2_neg <= byp_irf_rd_data_w2;
thr_rd_w2_neg <= thr_rd_w2;
active_win_thr_rd_w2_neg_wr_en <= 1'b1;
end
else begin
active_win_thr_rd_w2_neg_wr_en <= 1'b0;
end
end
end
always @(posedge clk) begin
cwpswap_tid_m[1:0] <= (sehold ? cwpswap_tid_m[1:0] :
rml_irf_cwpswap_tid_e[1:0]);
cwpswap_tid_w[1:0] <= cwpswap_tid_m[1:0];
old_lo_cwp_m[2:0] <= (sehold ? old_lo_cwp_m[2:0] :
rml_irf_old_lo_cwp_e[2:0]);
new_lo_cwp_m[2:0] <= (sehold ? new_lo_cwp_m[2:0] :
rml_irf_new_lo_cwp_e[2:0]);
new_lo_cwp_w[2:0] <= new_lo_cwp_m[2:0];
old_e_cwp_m[1:0] <= (sehold ? old_e_cwp_m[1:0] :
rml_irf_old_e_cwp_e[2:1]);
new_e_cwp_m[1:0] <= (sehold ? new_e_cwp_m[1:0] :
rml_irf_new_e_cwp_e[2:1]);
new_e_cwp_w[1:0] <= new_e_cwp_m[1:0];
swap_local_m <= (sehold ? (swap_local_m & rst_tri_en) :
rml_irf_swap_local_e);
swap_local_w <= swap_local_m_vld;
swap_odd_m <= (sehold ? (swap_odd_m & rst_tri_en) : rml_irf_swap_odd_e
);
swap_odd_w <= swap_odd_m_vld;
swap_even_m <= (sehold ? (swap_even_m & rst_tri_en) :
rml_irf_swap_even_e);
swap_even_w <= swap_even_m_vld;
kill_restore_d1 <= kill_restore_w;
end
always @(posedge clk) begin
swap_global_d1 <= (sehold ? (swap_global_d1 & rst_tri_en) :
rml_irf_swap_global);
swap_global_d2 <= swap_global_d1_vld;
global_tid_d1[1:0] <= (sehold ? global_tid_d1[1:0] :
rml_irf_global_tid[1:0]);
global_tid_d2[1:0] <= global_tid_d1[1:0];
old_agp_d1[1:0] <= (sehold ? old_agp_d1[1:0] : rml_irf_old_agp[1:0]);
new_agp_d1[1:0] <= (sehold ? new_agp_d1[1:0] : rml_irf_new_agp[1:0]);
new_agp_d2[1:0] <= new_agp_d1[1:0];
end
/*
always @(posedge clk) begin
if (wr_en) begin
$display("Write Port 1: %h %h", active_win_thr_rd_w_neg,
thr_rd_w_neg);
end
if (wr_en2) begin
$display("Write Port 2: %h %h", active_win_thr_rd_w2_neg,
thr_rd_w2_neg);
end
if (ifu_exu_ren1_d) begin
@(posedge clk) ;
$display("Read Port 1: %h %h", irf_byp_rs1_data_d, thr_rs1);
end
if (ifu_exu_ren2_d) begin
@(posedge clk) ;
$display("Read Port 2: %h %h", irf_byp_rs2_data_d, thr_rs2);
end
if (ifu_exu_ren3_d) begin
@(posedge clk) ;
$display("Read Port 3: %h %h", irf_byp_rs3_data_d, thr_rs3);
end
end
*/
endmodule
module bw_r_irf_core(clk, ifu_exu_ren1_d, ifu_exu_ren2_d, ifu_exu_ren3_d,
thr_rs1, thr_rs2, thr_rs3, thr_rs3h, irf_byp_rs1_data_d,
irf_byp_rs2_data_d, irf_byp_rs3_data_d, irf_byp_rs3h_data_d, wr_en,
wr_en2, active_win_thr_rd_w_neg, active_win_thr_rd_w2_neg, thr_rd_w_neg,
thr_rd_w2_neg, swap_global_d1_vld, swap_global_d2, global_tid_d1,
global_tid_d2, old_agp_d1, new_agp_d2, swap_local_m_vld, swap_local_w,
old_lo_cwp_m, new_lo_cwp_w, swap_even_m_vld, swap_even_w, old_e_cwp_m,
new_e_cwp_w, swap_odd_m_vld, swap_odd_w, cwpswap_tid_m, cwpswap_tid_w,
kill_restore_w);
input clk;
input ifu_exu_ren1_d;
input ifu_exu_ren2_d;
input ifu_exu_ren3_d;
input [6:0] thr_rs1;
input [6:0] thr_rs2;
input [6:0] thr_rs3;
input [6:0] thr_rs3h;
output [71:0] irf_byp_rs1_data_d;
output [71:0] irf_byp_rs2_data_d;
output [71:0] irf_byp_rs3_data_d;
output [71:0] irf_byp_rs3h_data_d;
input wr_en;
input wr_en2;
input [71:0] active_win_thr_rd_w_neg;
input [71:0] active_win_thr_rd_w2_neg;
input [6:0] thr_rd_w_neg;
input [6:0] thr_rd_w2_neg;
input swap_global_d1_vld;
input swap_global_d2;
input [1:0] global_tid_d1;
input [1:0] global_tid_d2;
input [1:0] old_agp_d1;
input [1:0] new_agp_d2;
input swap_local_m_vld;
input swap_local_w;
input [2:0] old_lo_cwp_m;
input [2:0] new_lo_cwp_w;
input swap_even_m_vld;
input swap_even_w;
input [1:0] old_e_cwp_m;
input [1:0] new_e_cwp_w;
input swap_odd_m_vld;
input swap_odd_w;
input [1:0] cwpswap_tid_m;
input [1:0] cwpswap_tid_w;
input kill_restore_w;
reg [71:0] irf_byp_rs1_data_d;
reg [71:0] irf_byp_rs2_data_d;
reg [71:0] irf_byp_rs3_data_d;
reg [71:0] irf_byp_rs3h_data_d;
wire [71:0] rd_data00;
wire [71:0] rd_data01;
wire [71:0] rd_data02;
wire [71:0] rd_data03;
wire [71:0] rd_data04;
wire [71:0] rd_data05;
wire [71:0] rd_data06;
wire [71:0] rd_data07;
wire [71:0] rd_data08;
wire [71:0] rd_data09;
wire [71:0] rd_data10;
wire [71:0] rd_data11;
wire [71:0] rd_data12;
wire [71:0] rd_data13;
wire [71:0] rd_data14;
wire [71:0] rd_data15;
wire [71:0] rd_data16;
wire [71:0] rd_data17;
wire [71:0] rd_data18;
wire [71:0] rd_data19;
wire [71:0] rd_data20;
wire [71:0] rd_data21;
wire [71:0] rd_data22;
wire [71:0] rd_data23;
wire [71:0] rd_data24;
wire [71:0] rd_data25;
wire [71:0] rd_data26;
wire [71:0] rd_data27;
wire [71:0] rd_data28;
wire [71:0] rd_data29;
wire [71:0] rd_data30;
wire [71:0] rd_data31;
wire wren;
wire [4:0] wr_addr;
wire [71:0] wr_data;
wire [127:0] wr_en1s = (wr_en << {thr_rd_w_neg[4:0],thr_rd_w_neg[6:5]});
wire [127:0] wr_en2s = (wr_en2 << {thr_rd_w2_neg[4:0],thr_rd_w2_neg[6:5]});
wire [127:0] wrens = wr_en1s | wr_en2s;
wire [3:0] wr_th1 = wr_en << thr_rd_w_neg[6:5];
wire [71:0] wr_data0 = wr_th1[0] ? active_win_thr_rd_w_neg : active_win_thr_rd_w2_neg;
wire [71:0] wr_data1 = wr_th1[1] ? active_win_thr_rd_w_neg : active_win_thr_rd_w2_neg;
wire [71:0] wr_data2 = wr_th1[2] ? active_win_thr_rd_w_neg : active_win_thr_rd_w2_neg;
wire [71:0] wr_data3 = wr_th1[3] ? active_win_thr_rd_w_neg : active_win_thr_rd_w2_neg;
bw_r_irf_register register00(
.clk (clk),
.wrens (wrens[3:0]),
.save (swap_global_d1_vld),
.save_addr ({global_tid_d1, 1'b0, old_agp_d1[1:0]}),
.restore (swap_global_d2),
.restore_addr ({global_tid_d2, 1'b0, new_agp_d2[1:0]}),
.wr_data0 (72'b0),
.wr_data1 (72'b0),
.wr_data2 (72'b0),
.wr_data3 (72'b0),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data00));
bw_r_irf_register register01(
.clk (clk),
.wrens (wrens[7:4]),
.save (swap_global_d1_vld),
.save_addr ({global_tid_d1, 1'b0, old_agp_d1[1:0]}),
.restore (swap_global_d2),
.restore_addr ({global_tid_d2, 1'b0, new_agp_d2[1:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data01));
bw_r_irf_register register02(
.clk (clk),
.wrens (wrens[11:8]),
.save (swap_global_d1_vld),
.save_addr ({global_tid_d1, 1'b0, old_agp_d1[1:0]}),
.restore (swap_global_d2),
.restore_addr ({global_tid_d2, 1'b0, new_agp_d2[1:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data02));
bw_r_irf_register register03(
.clk (clk),
.wrens (wrens[15:12]),
.save (swap_global_d1_vld),
.save_addr ({global_tid_d1, 1'b0, old_agp_d1[1:0]}),
.restore (swap_global_d2),
.restore_addr ({global_tid_d2, 1'b0, new_agp_d2[1:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data03));
bw_r_irf_register register04(
.clk (clk),
.wrens (wrens[19:16]),
.save (swap_global_d1_vld),
.save_addr ({global_tid_d1, 1'b0, old_agp_d1[1:0]}),
.restore (swap_global_d2),
.restore_addr ({global_tid_d2, 1'b0, new_agp_d2[1:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data04));
bw_r_irf_register register05(
.clk (clk),
.wrens (wrens[23:20]),
.save (swap_global_d1_vld),
.save_addr ({global_tid_d1, 1'b0, old_agp_d1[1:0]}),
.restore (swap_global_d2),
.restore_addr ({global_tid_d2, 1'b0, new_agp_d2[1:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data05));
bw_r_irf_register register06(
.clk (clk),
.wrens (wrens[27:24]),
.save (swap_global_d1_vld),
.save_addr ({global_tid_d1, 1'b0, old_agp_d1[1:0]}),
.restore (swap_global_d2),
.restore_addr ({global_tid_d2, 1'b0, new_agp_d2[1:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data06));
bw_r_irf_register register07(
.clk (clk),
.wrens (wrens[31:28]),
.save (swap_global_d1_vld),
.save_addr ({global_tid_d1, 1'b0, old_agp_d1[1:0]}),
.restore (swap_global_d2),
.restore_addr ({global_tid_d2, 1'b0, new_agp_d2[1:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data07));
bw_r_irf_register register08(
.clk (clk),
.wrens (wrens[35:32]),
.save (swap_odd_m_vld),
.save_addr ({cwpswap_tid_m, 1'b0, old_lo_cwp_m[2:1]}),
.restore ((swap_odd_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w,1'b0, new_lo_cwp_w[2:1]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data08));
bw_r_irf_register register09(
.clk (clk),
.wrens (wrens[39:36]),
.save (swap_odd_m_vld),
.save_addr ({cwpswap_tid_m, 1'b0, old_lo_cwp_m[2:1]}),
.restore ((swap_odd_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w,1'b0, new_lo_cwp_w[2:1]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data09));
bw_r_irf_register register10(
.clk (clk),
.wrens (wrens[43:40]),
.save (swap_odd_m_vld),
.save_addr ({cwpswap_tid_m, 1'b0, old_lo_cwp_m[2:1]}),
.restore ((swap_odd_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w,1'b0, new_lo_cwp_w[2:1]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data10));
bw_r_irf_register register11(
.clk (clk),
.wrens (wrens[47:44]),
.save (swap_odd_m_vld),
.save_addr ({cwpswap_tid_m, 1'b0, old_lo_cwp_m[2:1]}),
.restore ((swap_odd_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w,1'b0, new_lo_cwp_w[2:1]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data11));
bw_r_irf_register register12(
.clk (clk),
.wrens (wrens[51:48]),
.save (swap_odd_m_vld),
.save_addr ({cwpswap_tid_m, 1'b0, old_lo_cwp_m[2:1]}),
.restore ((swap_odd_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w,1'b0, new_lo_cwp_w[2:1]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data12));
bw_r_irf_register register13(
.clk (clk),
.wrens (wrens[55:52]),
.save (swap_odd_m_vld),
.save_addr ({cwpswap_tid_m, 1'b0, old_lo_cwp_m[2:1]}),
.restore ((swap_odd_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w,1'b0, new_lo_cwp_w[2:1]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data13));
bw_r_irf_register register14(
.clk (clk),
.wrens (wrens[59:56]),
.save (swap_odd_m_vld),
.save_addr ({cwpswap_tid_m, 1'b0, old_lo_cwp_m[2:1]}),
.restore ((swap_odd_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w,1'b0, new_lo_cwp_w[2:1]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data14));
bw_r_irf_register register15(
.clk (clk),
.wrens (wrens[63:60]),
.save (swap_odd_m_vld),
.save_addr ({cwpswap_tid_m, 1'b0, old_lo_cwp_m[2:1]}),
.restore ((swap_odd_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w,1'b0, new_lo_cwp_w[2:1]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data15));
bw_r_irf_register register16(
.clk (clk),
.wrens (wrens[67:64]),
.save (swap_local_m_vld),
.save_addr ({cwpswap_tid_m, old_lo_cwp_m[2:0]}),
.restore ((swap_local_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w, new_lo_cwp_w[2:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data16));
bw_r_irf_register register17(
.clk (clk),
.wrens (wrens[71:68]),
.save (swap_local_m_vld),
.save_addr ({cwpswap_tid_m, old_lo_cwp_m[2:0]}),
.restore ((swap_local_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w, new_lo_cwp_w[2:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data17));
bw_r_irf_register register18(
.clk (clk),
.wrens (wrens[75:72]),
.save (swap_local_m_vld),
.save_addr ({cwpswap_tid_m, old_lo_cwp_m[2:0]}),
.restore ((swap_local_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w, new_lo_cwp_w[2:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data18));
bw_r_irf_register register19(
.clk (clk),
.wrens (wrens[79:76]),
.save (swap_local_m_vld),
.save_addr ({cwpswap_tid_m, old_lo_cwp_m[2:0]}),
.restore ((swap_local_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w, new_lo_cwp_w[2:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data19));
bw_r_irf_register register20(
.clk (clk),
.wrens (wrens[83:80]),
.save (swap_local_m_vld),
.save_addr ({cwpswap_tid_m, old_lo_cwp_m[2:0]}),
.restore ((swap_local_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w, new_lo_cwp_w[2:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data20));
bw_r_irf_register register21(
.clk (clk),
.wrens (wrens[87:84]),
.save (swap_local_m_vld),
.save_addr ({cwpswap_tid_m, old_lo_cwp_m[2:0]}),
.restore ((swap_local_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w, new_lo_cwp_w[2:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data21));
bw_r_irf_register register22(
.clk (clk),
.wrens (wrens[91:88]),
.save (swap_local_m_vld),
.save_addr ({cwpswap_tid_m, old_lo_cwp_m[2:0]}),
.restore ((swap_local_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w, new_lo_cwp_w[2:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data22));
bw_r_irf_register register23(
.clk (clk),
.wrens (wrens[95:92]),
.save (swap_local_m_vld),
.save_addr ({cwpswap_tid_m, old_lo_cwp_m[2:0]}),
.restore ((swap_local_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w, new_lo_cwp_w[2:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data23));
bw_r_irf_register register24(
.clk (clk),
.wrens (wrens[99:96]),
.save (swap_even_m_vld),
.save_addr ({cwpswap_tid_m[1:0], 1'b0, old_e_cwp_m[1:0]}),
.restore ((swap_even_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w[1:0], 1'b0, new_e_cwp_w[1:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data24));
bw_r_irf_register register25(
.clk (clk),
.wrens (wrens[103:100]),
.save (swap_even_m_vld),
.save_addr ({cwpswap_tid_m[1:0], 1'b0, old_e_cwp_m[1:0]}),
.restore ((swap_even_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w[1:0], 1'b0, new_e_cwp_w[1:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data25));
bw_r_irf_register register26(
.clk (clk),
.wrens (wrens[107:104]),
.save (swap_even_m_vld),
.save_addr ({cwpswap_tid_m[1:0], 1'b0, old_e_cwp_m[1:0]}),
.restore ((swap_even_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w[1:0], 1'b0, new_e_cwp_w[1:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data26));
bw_r_irf_register register27(
.clk (clk),
.wrens (wrens[111:108]),
.save (swap_even_m_vld),
.save_addr ({cwpswap_tid_m[1:0], 1'b0, old_e_cwp_m[1:0]}),
.restore ((swap_even_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w[1:0], 1'b0, new_e_cwp_w[1:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data27));
bw_r_irf_register register28(
.clk (clk),
.wrens (wrens[115:112]),
.save (swap_even_m_vld),
.save_addr ({cwpswap_tid_m[1:0], 1'b0, old_e_cwp_m[1:0]}),
.restore ((swap_even_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w[1:0], 1'b0, new_e_cwp_w[1:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data28));
bw_r_irf_register register29(
.clk (clk),
.wrens (wrens[119:116]),
.save (swap_even_m_vld),
.save_addr ({cwpswap_tid_m[1:0], 1'b0, old_e_cwp_m[1:0]}),
.restore ((swap_even_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w[1:0], 1'b0, new_e_cwp_w[1:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data29));
bw_r_irf_register register30(
.clk (clk),
.wrens (wrens[123:120]),
.save (swap_even_m_vld),
.save_addr ({cwpswap_tid_m[1:0], 1'b0, old_e_cwp_m[1:0]}),
.restore ((swap_even_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w[1:0], 1'b0, new_e_cwp_w[1:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data30));
bw_r_irf_register register31(
.clk (clk),
.wrens (wrens[127:124]),
.save (swap_even_m_vld),
.save_addr ({cwpswap_tid_m[1:0], 1'b0, old_e_cwp_m[1:0]}),
.restore ((swap_even_w & (~kill_restore_w))),
.restore_addr ({cwpswap_tid_w[1:0], 1'b0, new_e_cwp_w[1:0]}),
.wr_data0 (wr_data0),
.wr_data1 (wr_data1),
.wr_data2 (wr_data2),
.wr_data3 (wr_data3),
.rd_thread (thr_rs1[6:5]),
.rd_data (rd_data31));
always @(negedge clk) if (ifu_exu_ren1_d) begin
case (thr_rs1[4:0])
5'b0:
irf_byp_rs1_data_d <= rd_data00;
5'b1:
irf_byp_rs1_data_d <= rd_data01;
5'b00010:
irf_byp_rs1_data_d <= rd_data02;
5'b00011:
irf_byp_rs1_data_d <= rd_data03;
5'b00100:
irf_byp_rs1_data_d <= rd_data04;
5'b00101:
irf_byp_rs1_data_d <= rd_data05;
5'b00110:
irf_byp_rs1_data_d <= rd_data06;
5'b00111:
irf_byp_rs1_data_d <= rd_data07;
5'b01000:
irf_byp_rs1_data_d <= rd_data08;
5'b01001:
irf_byp_rs1_data_d <= rd_data09;
5'b01010:
irf_byp_rs1_data_d <= rd_data10;
5'b01011:
irf_byp_rs1_data_d <= rd_data11;
5'b01100:
irf_byp_rs1_data_d <= rd_data12;
5'b01101:
irf_byp_rs1_data_d <= rd_data13;
5'b01110:
irf_byp_rs1_data_d <= rd_data14;
5'b01111:
irf_byp_rs1_data_d <= rd_data15;
5'b10000:
irf_byp_rs1_data_d <= rd_data16;
5'b10001:
irf_byp_rs1_data_d <= rd_data17;
5'b10010:
irf_byp_rs1_data_d <= rd_data18;
5'b10011:
irf_byp_rs1_data_d <= rd_data19;
5'b10100:
irf_byp_rs1_data_d <= rd_data20;
5'b10101:
irf_byp_rs1_data_d <= rd_data21;
5'b10110:
irf_byp_rs1_data_d <= rd_data22;
5'b10111:
irf_byp_rs1_data_d <= rd_data23;
5'b11000:
irf_byp_rs1_data_d <= rd_data24;
5'b11001:
irf_byp_rs1_data_d <= rd_data25;
5'b11010:
irf_byp_rs1_data_d <= rd_data26;
5'b11011:
irf_byp_rs1_data_d <= rd_data27;
5'b11100:
irf_byp_rs1_data_d <= rd_data28;
5'b11101:
irf_byp_rs1_data_d <= rd_data29;
5'b11110:
irf_byp_rs1_data_d <= rd_data30;
5'b11111:
irf_byp_rs1_data_d <= rd_data31;
endcase
end
always @(negedge clk) if (ifu_exu_ren2_d) begin
case (thr_rs2[4:0])
5'b0:
irf_byp_rs2_data_d <= rd_data00;
5'b1:
irf_byp_rs2_data_d <= rd_data01;
5'b00010:
irf_byp_rs2_data_d <= rd_data02;
5'b00011:
irf_byp_rs2_data_d <= rd_data03;
5'b00100:
irf_byp_rs2_data_d <= rd_data04;
5'b00101:
irf_byp_rs2_data_d <= rd_data05;
5'b00110:
irf_byp_rs2_data_d <= rd_data06;
5'b00111:
irf_byp_rs2_data_d <= rd_data07;
5'b01000:
irf_byp_rs2_data_d <= rd_data08;
5'b01001:
irf_byp_rs2_data_d <= rd_data09;
5'b01010:
irf_byp_rs2_data_d <= rd_data10;
5'b01011:
irf_byp_rs2_data_d <= rd_data11;
5'b01100:
irf_byp_rs2_data_d <= rd_data12;
5'b01101:
irf_byp_rs2_data_d <= rd_data13;
5'b01110:
irf_byp_rs2_data_d <= rd_data14;
5'b01111:
irf_byp_rs2_data_d <= rd_data15;
5'b10000:
irf_byp_rs2_data_d <= rd_data16;
5'b10001:
irf_byp_rs2_data_d <= rd_data17;
5'b10010:
irf_byp_rs2_data_d <= rd_data18;
5'b10011:
irf_byp_rs2_data_d <= rd_data19;
5'b10100:
irf_byp_rs2_data_d <= rd_data20;
5'b10101:
irf_byp_rs2_data_d <= rd_data21;
5'b10110:
irf_byp_rs2_data_d <= rd_data22;
5'b10111:
irf_byp_rs2_data_d <= rd_data23;
5'b11000:
irf_byp_rs2_data_d <= rd_data24;
5'b11001:
irf_byp_rs2_data_d <= rd_data25;
5'b11010:
irf_byp_rs2_data_d <= rd_data26;
5'b11011:
irf_byp_rs2_data_d <= rd_data27;
5'b11100:
irf_byp_rs2_data_d <= rd_data28;
5'b11101:
irf_byp_rs2_data_d <= rd_data29;
5'b11110:
irf_byp_rs2_data_d <= rd_data30;
5'b11111:
irf_byp_rs2_data_d <= rd_data31;
endcase
end
always @(negedge clk) if (ifu_exu_ren3_d) begin
case (thr_rs3[4:0])
5'b0:
irf_byp_rs3_data_d <= rd_data00;
5'b1:
irf_byp_rs3_data_d <= rd_data01;
5'b00010:
irf_byp_rs3_data_d <= rd_data02;
5'b00011:
irf_byp_rs3_data_d <= rd_data03;
5'b00100:
irf_byp_rs3_data_d <= rd_data04;
5'b00101:
irf_byp_rs3_data_d <= rd_data05;
5'b00110:
irf_byp_rs3_data_d <= rd_data06;
5'b00111:
irf_byp_rs3_data_d <= rd_data07;
5'b01000:
irf_byp_rs3_data_d <= rd_data08;
5'b01001:
irf_byp_rs3_data_d <= rd_data09;
5'b01010:
irf_byp_rs3_data_d <= rd_data10;
5'b01011:
irf_byp_rs3_data_d <= rd_data11;
5'b01100:
irf_byp_rs3_data_d <= rd_data12;
5'b01101:
irf_byp_rs3_data_d <= rd_data13;
5'b01110:
irf_byp_rs3_data_d <= rd_data14;
5'b01111:
irf_byp_rs3_data_d <= rd_data15;
5'b10000:
irf_byp_rs3_data_d <= rd_data16;
5'b10001:
irf_byp_rs3_data_d <= rd_data17;
5'b10010:
irf_byp_rs3_data_d <= rd_data18;
5'b10011:
irf_byp_rs3_data_d <= rd_data19;
5'b10100:
irf_byp_rs3_data_d <= rd_data20;
5'b10101:
irf_byp_rs3_data_d <= rd_data21;
5'b10110:
irf_byp_rs3_data_d <= rd_data22;
5'b10111:
irf_byp_rs3_data_d <= rd_data23;
5'b11000:
irf_byp_rs3_data_d <= rd_data24;
5'b11001:
irf_byp_rs3_data_d <= rd_data25;
5'b11010:
irf_byp_rs3_data_d <= rd_data26;
5'b11011:
irf_byp_rs3_data_d <= rd_data27;
5'b11100:
irf_byp_rs3_data_d <= rd_data28;
5'b11101:
irf_byp_rs3_data_d <= rd_data29;
5'b11110:
irf_byp_rs3_data_d <= rd_data30;
5'b11111:
irf_byp_rs3_data_d <= rd_data31;
endcase
end
always @(negedge clk) if (ifu_exu_ren3_d) begin
case (thr_rs3h[4:1])
4'b0:
irf_byp_rs3h_data_d <= rd_data01;
4'b1:
irf_byp_rs3h_data_d <= rd_data03;
4'b0010:
irf_byp_rs3h_data_d <= rd_data05;
4'b0011:
irf_byp_rs3h_data_d <= rd_data07;
4'b0100:
irf_byp_rs3h_data_d <= rd_data09;
4'b0101:
irf_byp_rs3h_data_d <= rd_data11;
4'b0110:
irf_byp_rs3h_data_d <= rd_data13;
4'b0111:
irf_byp_rs3h_data_d <= rd_data15;
4'b1000:
irf_byp_rs3h_data_d <= rd_data17;
4'b1001:
irf_byp_rs3h_data_d <= rd_data19;
4'b1010:
irf_byp_rs3h_data_d <= rd_data21;
4'b1011:
irf_byp_rs3h_data_d <= rd_data23;
4'b1100:
irf_byp_rs3h_data_d <= rd_data25;
4'b1101:
irf_byp_rs3h_data_d <= rd_data27;
4'b1110:
irf_byp_rs3h_data_d <= rd_data29;
4'b1111:
irf_byp_rs3h_data_d <= rd_data31;
endcase
end
endmodule
`endif
`else
module bw_r_irf (/*AUTOARG*/
// Outputs
so, irf_byp_rs1_data_d_l, irf_byp_rs2_data_d_l,
irf_byp_rs3_data_d_l, irf_byp_rs3h_data_d_l,
// Inputs
rclk, reset_l, si, se, sehold, rst_tri_en, ifu_exu_tid_s2,
ifu_exu_rs1_s, ifu_exu_rs2_s, ifu_exu_rs3_s, ifu_exu_ren1_s,
ifu_exu_ren2_s, ifu_exu_ren3_s, ecl_irf_wen_w, ecl_irf_wen_w2,
ecl_irf_rd_m, ecl_irf_rd_g, byp_irf_rd_data_w, byp_irf_rd_data_w2,
ecl_irf_tid_m, ecl_irf_tid_g, rml_irf_old_lo_cwp_e,
rml_irf_new_lo_cwp_e, rml_irf_old_e_cwp_e, rml_irf_new_e_cwp_e,
rml_irf_swap_even_e, rml_irf_swap_odd_e, rml_irf_swap_local_e,
rml_irf_kill_restore_w, rml_irf_cwpswap_tid_e, rml_irf_old_agp,
rml_irf_new_agp, rml_irf_swap_global, rml_irf_global_tid
) ;
input rclk;
input reset_l;
input si;
input se;
input sehold;
input rst_tri_en;
input [1:0] ifu_exu_tid_s2; // s stage thread
input [4:0] ifu_exu_rs1_s; // source addresses
input [4:0] ifu_exu_rs2_s;
input [4:0] ifu_exu_rs3_s;
input ifu_exu_ren1_s; // read enables for all 3 ports
input ifu_exu_ren2_s;
input ifu_exu_ren3_s;
input ecl_irf_wen_w; // write enables for both write ports
input ecl_irf_wen_w2;
input [4:0] ecl_irf_rd_m; // w destination
input [4:0] ecl_irf_rd_g; // w2 destination
input [71:0] byp_irf_rd_data_w;// write data from w1
input [71:0] byp_irf_rd_data_w2; // write data from w2
input [1:0] ecl_irf_tid_m; // w stage thread
input [1:0] ecl_irf_tid_g; // w2 thread
input [2:0] rml_irf_old_lo_cwp_e; // current window pointer for locals and odds
input [2:0] rml_irf_new_lo_cwp_e; // target window pointer for locals and odds
input [2:1] rml_irf_old_e_cwp_e; // current window pointer for evens
input [2:1] rml_irf_new_e_cwp_e; // target window pointer for evens
input rml_irf_swap_even_e;
input rml_irf_swap_odd_e;
input rml_irf_swap_local_e;
input rml_irf_kill_restore_w;
input [1:0] rml_irf_cwpswap_tid_e;
input [1:0] rml_irf_old_agp; // alternate global pointer
input [1:0] rml_irf_new_agp; // alternate global pointer
input rml_irf_swap_global;
input [1:0] rml_irf_global_tid;
output so;
output [71:0] irf_byp_rs1_data_d_l;
output [71:0] irf_byp_rs2_data_d_l;
output [71:0] irf_byp_rs3_data_d_l;
output [31:0] irf_byp_rs3h_data_d_l;
reg [71:0] irf_byp_rs1_data_d;
reg [71:0] irf_byp_rs2_data_d;
reg [71:0] irf_byp_rs3_data_d;
reg [71:0] irf_byp_rs3h_data_d;
reg [71:0] active_window [127:0];// 32x4 72 bit registers
reg [71:0] locals[255:0]; // 4x8x8 registers
reg [71:0] evens[127:0]; // 4x4x8 registers
reg [71:0] odds[127:0]; // 4x4x8 registers
reg [71:0] globals[127:0]; // 4x4x8 registers
// registers for manipulating windows
reg [6:0] active_pointer;
reg [7:0] regfile_pointer;
reg [5:0] i;
wire [1:0] ecl_irf_tid_w; // w stage thread
wire [1:0] ecl_irf_tid_w2; // w2 thread
wire [4:0] ecl_irf_rd_w; // w destination
wire [4:0] ecl_irf_rd_w2; // w2 destination
wire [1:0] ifu_exu_thr_d; // d stage thread
wire ifu_exu_ren1_d; // read enables for all 3 ports
wire ifu_exu_ren2_d;
wire ifu_exu_ren3_d;
wire [4:0] ifu_exu_rs1_d; // source addresses
wire [4:0] ifu_exu_rs2_d;
wire [4:0] ifu_exu_rs3_d;
wire [6:0] thr_rs1; // these 5 are a combination of the thr and reg
wire [6:0] thr_rs2; // so that comparison can be done more easily
wire [6:0] thr_rs3;
wire [6:0] thr_rs3h;
wire [6:0] thr_rd_w;
wire [6:0] thr_rd_w2;
reg [1:0] cwpswap_tid_m;
reg [1:0] cwpswap_tid_w;
reg [2:0] old_lo_cwp_m;
reg [2:0] new_lo_cwp_m;
reg [2:0] new_lo_cwp_w;
reg [1:0] old_e_cwp_m;
reg [1:0] new_e_cwp_m;
reg [1:0] new_e_cwp_w;
reg swap_local_m;
reg swap_local_w;
reg swap_even_m;
reg swap_even_w;
reg swap_odd_m;
reg swap_odd_w;
reg kill_restore_d1;
reg swap_global_d1;
reg swap_global_d2;
reg [1:0] global_tid_d1;
reg [1:0] global_tid_d2;
reg [1:0] old_agp_d1,
new_agp_d1,
new_agp_d2;
reg [71:0] active_win_thr_rd_w_neg;
reg active_win_thr_rd_w_neg_wr_en;
reg [6:0] thr_rd_w_neg;
reg [71:0] active_win_thr_rd_w2_neg;
reg active_win_thr_rd_w2_neg_wr_en;
reg [6:0] thr_rd_w2_neg;
reg rst_tri_en_neg;
wire se;
wire clk;
assign clk = rclk & reset_l;
wire ren1_s;
wire ren2_s;
wire ren3_s;
wire [4:0] rs1_s;
wire [4:0] rs2_s;
wire [4:0] rs3_s;
wire [1:0] tid_s;
wire [1:0] tid_g;
wire [1:0] tid_m;
wire [4:0] rd_m;
wire [4:0] rd_g;
wire kill_restore_w;
wire swap_global_d1_vld;
wire swap_local_m_vld;
wire swap_even_m_vld;
wire swap_odd_m_vld;
assign {ren1_s,ren2_s,ren3_s,rs1_s[4:0],rs2_s[4:0],rs3_s[4:0],tid_s[1:0],tid_g[1:0],tid_m[1:0],
rd_m[4:0], rd_g[4:0]} = (sehold)?
{ifu_exu_ren1_d,ifu_exu_ren2_d,ifu_exu_ren3_d,ifu_exu_rs1_d[4:0],ifu_exu_rs2_d[4:0],
ifu_exu_rs3_d[4:0],ifu_exu_thr_d[1:0],ecl_irf_tid_w2[1:0],ecl_irf_tid_w[1:0],
ecl_irf_rd_w[4:0],ecl_irf_rd_w2[4:0]}:
{ifu_exu_ren1_s,ifu_exu_ren2_s,ifu_exu_ren3_s,ifu_exu_rs1_s[4:0],ifu_exu_rs2_s[4:0],
ifu_exu_rs3_s[4:0],ifu_exu_tid_s2[1:0],ecl_irf_tid_g[1:0],ecl_irf_tid_m[1:0],
ecl_irf_rd_m[4:0],ecl_irf_rd_g[4:0]};
// Pipeline flops for irf control signals
dff_s dff_ren1_s2d(.din(ren1_s), .clk(clk), .q(ifu_exu_ren1_d), .se(se),
.si(), .so());
dff_s dff_ren2_s2d(.din(ren2_s), .clk(clk), .q(ifu_exu_ren2_d), .se(se),
.si(), .so());
dff_s dff_ren3_s2d(.din(ren3_s), .clk(clk), .q(ifu_exu_ren3_d), .se(se),
.si(), .so());
dff_s #5 dff_rs1_s2d(.din(rs1_s[4:0]), .clk(clk), .q(ifu_exu_rs1_d[4:0]), .se(se),
.si(),.so());
dff_s #5 dff_rs2_s2d(.din(rs2_s[4:0]), .clk(clk), .q(ifu_exu_rs2_d[4:0]), .se(se),
.si(),.so());
dff_s #5 dff_rs3_s2d(.din(rs3_s[4:0]), .clk(clk), .q(ifu_exu_rs3_d[4:0]), .se(se),
.si(),.so());
dff_s #2 dff_thr_s2d(.din(tid_s[1:0]), .clk(clk), .q(ifu_exu_thr_d[1:0]), .se(se),
.si(),.so());
dff_s #2 dff_thr_g2w2(.din(tid_g[1:0]), .clk(clk), .q(ecl_irf_tid_w2[1:0]), .se(se),
.si(),.so());
dff_s #2 dff_thr_m2w(.din(tid_m[1:0]), .clk(clk), .q(ecl_irf_tid_w[1:0]), .se(se),
.si(),.so());
dff_s #5 dff_rd_m2w(.din(rd_m[4:0]), .clk(clk), .q(ecl_irf_rd_w[4:0]), .se(se),
.si(),.so());
dff_s #5 dff_rd_g2w2(.din(rd_g[4:0]), .clk(clk), .q(ecl_irf_rd_w2[4:0]), .se(se),
.si(),.so());
// Concatenate the thread and rs1/rd bits together
assign thr_rs1[6:0] = {ifu_exu_thr_d, ifu_exu_rs1_d};
assign thr_rs2[6:0] = {ifu_exu_thr_d, ifu_exu_rs2_d};
assign thr_rs3[6:0] = {ifu_exu_thr_d, ifu_exu_rs3_d[4:0]};
assign thr_rs3h[6:0] = {ifu_exu_thr_d[1:0], ifu_exu_rs3_d[4:1], 1'b1};
assign thr_rd_w[6:0] = {ecl_irf_tid_w, ecl_irf_rd_w};
assign thr_rd_w2[6:0] = {ecl_irf_tid_w2, ecl_irf_rd_w2};
// Active low outputs
assign irf_byp_rs1_data_d_l[71:0] = ~irf_byp_rs1_data_d[71:0];
assign irf_byp_rs2_data_d_l[71:0] = ~irf_byp_rs2_data_d[71:0];
assign irf_byp_rs3_data_d_l[71:0] = ~irf_byp_rs3_data_d[71:0];
assign irf_byp_rs3h_data_d_l[31:0] = ~irf_byp_rs3h_data_d[31:0];
// Read port 1
always @ ( clk ) begin
if (clk) irf_byp_rs1_data_d <= {72{1'bx}};
else begin
if (ifu_exu_ren1_d) begin // read enable must be high
if (thr_rs1[4:0] == 5'b0) irf_byp_rs1_data_d <= {72{1'b0}};
else begin
if ((ecl_irf_wen_w && (thr_rs1 == thr_rd_w)) || // check r/w conflict
(ecl_irf_wen_w2 && (thr_rs1 == thr_rd_w2))) begin
irf_byp_rs1_data_d <= {72{1'bx}}; // rw conflict gives x
end
else begin
irf_byp_rs1_data_d <= active_window[thr_rs1[6:0]];
end
end
end
// output disabled
else begin
irf_byp_rs1_data_d <= {72{1'bx}};
end
end
end
// Read port 2
always @ ( clk ) begin
if (clk) irf_byp_rs2_data_d <= {72{1'bx}};
else begin
if (ifu_exu_ren2_d) begin
if (thr_rs2[4:0] == 5'b0) irf_byp_rs2_data_d <= {72{1'b0}};
else if ((ecl_irf_wen_w && (thr_rs2 == thr_rd_w)) ||
(ecl_irf_wen_w2 && (thr_rs2 == thr_rd_w2)))
irf_byp_rs2_data_d <= {72{1'bx}};
else begin
irf_byp_rs2_data_d <= active_window[thr_rs2];
end
end
// output disabled
else irf_byp_rs2_data_d <= {72{1'bx}};
end
end
// Read port 3
always @ ( clk ) begin
if (clk) irf_byp_rs3_data_d <= {72{1'bx}};
else begin
if (ifu_exu_ren3_d) begin
if (thr_rs3[4:0] == 5'b0) irf_byp_rs3_data_d[71:0] <= {72{1'b0}};
else if ((ecl_irf_wen_w && (thr_rs3 == thr_rd_w)) ||
(ecl_irf_wen_w2 && (thr_rs3 == thr_rd_w2)))
begin
irf_byp_rs3_data_d[71:0] <= {72{1'bx}};
end
else begin
irf_byp_rs3_data_d[71:0] <= active_window[thr_rs3];
end
end
// output disabled
else begin
irf_byp_rs3_data_d[71:0] <= {72{1'bx}};
end
end
end
// Read port 3h
always @ ( clk ) begin
if (clk) irf_byp_rs3h_data_d[71:0] <= {72{1'bx}};
else begin
if (ifu_exu_ren3_d) begin
if (thr_rs3h[4:0] == 5'b0) irf_byp_rs3h_data_d[71:0] <= 72'b0;
else if ((ecl_irf_wen_w && (thr_rs3h == thr_rd_w)) ||
(ecl_irf_wen_w2 && (thr_rs3h == thr_rd_w2)))
begin
irf_byp_rs3h_data_d[71:0] <= {72{1'bx}};
end
else begin
irf_byp_rs3h_data_d[71:0] <= active_window[thr_rs3h];
end
end
// output disabled
else begin
irf_byp_rs3h_data_d[71:0] <= {72{1'bx}};
end
end
end
/////////////////////////////////////////////////////////////////
/// Write ports
////////////////////////////////////////////////////////////////
// This is a latch that works if both wen is high and clk is low
always @(negedge clk) begin
rst_tri_en_neg <= rst_tri_en;
// write conflict results in X written to destination
if (ecl_irf_wen_w & ecl_irf_wen_w2 & (thr_rd_w[6:0] == thr_rd_w2[6:0])) begin
active_win_thr_rd_w_neg <= {72{1'bx}};
thr_rd_w_neg <= thr_rd_w;
active_win_thr_rd_w_neg_wr_en <= 1'b1;
active_win_thr_rd_w2_neg_wr_en <= 1'b0;
end
else begin
// W1 write port
if (ecl_irf_wen_w & (thr_rd_w[4:0] != 5'b0)) begin
active_win_thr_rd_w_neg <= byp_irf_rd_data_w;
thr_rd_w_neg <= thr_rd_w;
active_win_thr_rd_w_neg_wr_en <= 1'b1;
end
else
active_win_thr_rd_w_neg_wr_en <= 1'b0;
// W2 write port
if (ecl_irf_wen_w2 & (thr_rd_w2[4:0] != 5'b0)) begin
active_win_thr_rd_w2_neg <= byp_irf_rd_data_w2;
thr_rd_w2_neg <= thr_rd_w2;
active_win_thr_rd_w2_neg_wr_en <= 1'b1;
end
else
active_win_thr_rd_w2_neg_wr_en <= 1'b0;
end
end
/* MOVED TO CMP ENVIRONMENT
initial begin
// Hardcode R0 to zero
active_window[{2'b00, 5'b00000}] = 72'b0;
active_window[{2'b01, 5'b00000}] = 72'b0;
active_window[{2'b10, 5'b00000}] = 72'b0;
active_window[{2'b11, 5'b00000}] = 72'b0;
end
*/
//////////////////////////////////////////////////
// Window management logic
//////////////////////////////////////////////////
// Pipeline flops for control signals
// cwp swap signals
assign kill_restore_w = (sehold)? kill_restore_d1: rml_irf_kill_restore_w;
assign swap_local_m_vld = swap_local_m & ~rst_tri_en;
assign swap_odd_m_vld = swap_odd_m & ~rst_tri_en;
assign swap_even_m_vld = swap_even_m & ~rst_tri_en;
assign swap_global_d1_vld = swap_global_d1 & ~rst_tri_en;
always @ (posedge clk) begin
cwpswap_tid_m[1:0] <= (sehold)? cwpswap_tid_m[1:0]: rml_irf_cwpswap_tid_e[1:0];
cwpswap_tid_w[1:0] <= cwpswap_tid_m[1:0];
old_lo_cwp_m[2:0] <= (sehold)? old_lo_cwp_m[2:0]: rml_irf_old_lo_cwp_e[2:0];
new_lo_cwp_m[2:0] <= (sehold)? new_lo_cwp_m[2:0]: rml_irf_new_lo_cwp_e[2:0];
new_lo_cwp_w[2:0] <= new_lo_cwp_m[2:0];
old_e_cwp_m[1:0] <= (sehold)? old_e_cwp_m[1:0]: rml_irf_old_e_cwp_e[2:1];
new_e_cwp_m[1:0] <= (sehold)? new_e_cwp_m[1:0]: rml_irf_new_e_cwp_e[2:1];
new_e_cwp_w[1:0] <= new_e_cwp_m[1:0];
swap_local_m <= (sehold)? swap_local_m & rst_tri_en: rml_irf_swap_local_e;
swap_local_w <= swap_local_m_vld;
swap_odd_m <= (sehold)? swap_odd_m & rst_tri_en: rml_irf_swap_odd_e;
swap_odd_w <= swap_odd_m_vld;
swap_even_m <= (sehold)? swap_even_m & rst_tri_en: rml_irf_swap_even_e;
swap_even_w <= swap_even_m_vld;
kill_restore_d1 <= kill_restore_w;
end
// global swap signals
always @ (posedge clk) begin
swap_global_d1 <= (sehold)? swap_global_d1 & rst_tri_en: rml_irf_swap_global;
swap_global_d2 <= swap_global_d1_vld;
global_tid_d1[1:0] <= (sehold)? global_tid_d1[1:0]: rml_irf_global_tid[1:0];
global_tid_d2[1:0] <= global_tid_d1[1:0];
old_agp_d1[1:0] <= (sehold)? old_agp_d1[1:0]: rml_irf_old_agp[1:0];
new_agp_d1[1:0] <= (sehold)? new_agp_d1[1:0]: rml_irf_new_agp[1:0];
new_agp_d2[1:0] <= new_agp_d1[1:0];
end
/////////////////////////////////////////////
// Globals
//-----------------------------------
// rml inputs are latched on rising edge
// 1st cycle used for decode
// 2nd cycle stores active window in phase 1
// 3rd cycle loads new globals in phase 1
/////////////////////////////////////////////
always @ (posedge clk) begin
if (active_win_thr_rd_w_neg_wr_en & (~rst_tri_en | ~rst_tri_en_neg)) begin
active_window[thr_rd_w_neg] = active_win_thr_rd_w_neg;
end
if (active_win_thr_rd_w2_neg_wr_en & (~rst_tri_en | ~rst_tri_en_neg)) begin
active_window[thr_rd_w2_neg] = active_win_thr_rd_w2_neg;
end
// save active globals in phase 1
if (swap_global_d1_vld) begin
for (i = 6'd0; i < 6'd8; i = i + 1) begin
active_pointer[6:0] = {global_tid_d1[1:0], i[4:0]};
regfile_pointer[7:0] = {1'b0, global_tid_d1[1:0], old_agp_d1[1:0], i[2:0]};
// prevent back to back swaps on same thread
if (swap_global_d2 & (global_tid_d1[1:0] == global_tid_d2[1:0])) begin
globals[regfile_pointer[6:0]] = {72{1'bx}};
end
else globals[regfile_pointer[6:0]] = active_window[active_pointer[6:0]];
end
end
// load in new active globals in phase 2
if (swap_global_d2) begin
for (i = 6'd0; i < 6'd8; i = i + 1) begin
active_pointer[6:0] = {global_tid_d2[1:0], i[4:0]};
regfile_pointer[7:0] = {1'b0, global_tid_d2[1:0], new_agp_d2[1:0], i[2:0]};
if (swap_global_d1_vld & (global_tid_d1[1:0] == global_tid_d2[1:0])) begin
active_window[active_pointer] = {72{1'bx}};
globals[regfile_pointer[6:0]] = {72{1'bx}};
end
else active_window[active_pointer] = globals[regfile_pointer[6:0]];
end
end
////////////////////////////
// locals, ins and outs
//-------------------------
// E - set up inputs to flop
// M - Decode
// W (phase 1) - Save
// W (phase 2) - write is allowed for save because restore will get killed
// W2 (phase 1) - Restore
// W2 (phase 2) - write is allowed
//
// actions that occur in phase one are modelled as occurring on the
// rising edge
//
// swaps to the same thread in consecutive cycles not allowed
/////////////////////////////
if (swap_local_m_vld) begin
// save the locals (16-23 in active window)
for (i = 6'd16; i < 6'd24; i = i + 1) begin
active_pointer[6:0] = {cwpswap_tid_m[1:0], i[4:0]};
regfile_pointer[7:0] = {cwpswap_tid_m[1:0], old_lo_cwp_m[2:0], i[2:0]};
if (swap_local_w & ~kill_restore_w & (cwpswap_tid_m[1:0] == cwpswap_tid_w[1:0]))
locals[regfile_pointer[7:0]] = {72{1'bx}};
else
locals[regfile_pointer[7:0]] = active_window[active_pointer];
end
end
if (swap_even_m_vld) begin
// save the ins in even window (24-31 in active window)
for (i = 6'd24; i < 6'd32; i = i + 1) begin
active_pointer[6:0] = {cwpswap_tid_m[1:0], i[4:0]};
regfile_pointer[7:0] = {1'b0, cwpswap_tid_m[1:0], old_e_cwp_m[1:0], i[2:0]};
if (swap_even_w & ~kill_restore_w & (cwpswap_tid_m[1:0] == cwpswap_tid_w[1:0]))
evens[regfile_pointer[6:0]] = {72{1'bx}};
else
evens[regfile_pointer[6:0]] = active_window[active_pointer];
end
end
if (swap_odd_m_vld) begin
// save the ins in odd window (8-15 in active window)
for (i = 6'd8; i < 6'd16; i = i + 1) begin
active_pointer[6:0] = {cwpswap_tid_m[1:0], i[4:0]};
regfile_pointer[7:0] = {1'b0, cwpswap_tid_m[1:0], old_lo_cwp_m[2:1], i[2:0]};
if (swap_odd_w & ~kill_restore_w & (cwpswap_tid_m[1:0] == cwpswap_tid_w[1:0]))
odds[regfile_pointer[6:0]] = {72{1'bx}};
else
odds[regfile_pointer[6:0]] = active_window[active_pointer];
end
end
if(~kill_restore_w) begin
if (swap_local_w) begin
// restore the locals (16-23 in active window)
for (i = 6'd16; i < 6'd24; i = i + 1) begin
active_pointer[6:0] = {cwpswap_tid_w[1:0], i[4:0]};
regfile_pointer[7:0] = {cwpswap_tid_w[1:0], new_lo_cwp_w[2:0], i[2:0]};
if (swap_local_m_vld & (cwpswap_tid_m[1:0] == cwpswap_tid_w[1:0])) begin
active_window[active_pointer] = {72{1'bx}};
locals[regfile_pointer[7:0]] = {72{1'bx}};
end
else
active_window[active_pointer] = locals[regfile_pointer[7:0]];
end
end
if (swap_even_w) begin
// restore the ins in even window (24-32 in active window)
for (i = 6'd24; i < 6'd32; i = i + 1) begin
active_pointer[6:0] = {cwpswap_tid_w[1:0], i[4:0]};
regfile_pointer[7:0] = {1'b0, cwpswap_tid_w[1:0], new_e_cwp_w[1:0], i[2:0]};
if (swap_even_m_vld & (cwpswap_tid_m[1:0] == cwpswap_tid_w[1:0])) begin
active_window[active_pointer] = {72{1'bx}};
evens[regfile_pointer[6:0]] = {72{1'bx}};
end
else
active_window[active_pointer] = evens[regfile_pointer[6:0]];
end
end
if (swap_odd_w) begin
// restore the ins in odd window (8-16 in active window)
for (i = 6'd8; i < 6'd16; i = i + 1) begin
active_pointer[6:0] = {cwpswap_tid_w[1:0], i[4:0]};
regfile_pointer[7:0] = {1'b0, cwpswap_tid_w[1:0], new_lo_cwp_w[2:1], i[2:0]};
if (swap_odd_m_vld & (cwpswap_tid_m[1:0] == cwpswap_tid_w[1:0])) begin
active_window[active_pointer] = {72{1'bx}};
odds[regfile_pointer[6:0]] = {72{1'bx}};
end
else
active_window[active_pointer] = odds[regfile_pointer[6:0]];
end
end
end
end // always @ (posedge clk)
endmodule // bw_r_irf
`endif
|
`timescale 1ns / 1ps
module logic_top(
input CLKIN48,
input IFCLK,
output LED,
output MISO,
input MOSI,
input SS,
input SCLK,
output [7:0] PORT_B,
output [7:0] PORT_D,
output RDY0,
input CTL0,
input [15:0] PROBE
);
wire clksel, clkgen_rst, clklock; // async
wire fastclk, normalclk, ifclk_int;
wire fifo_valid_out; // ifclk
wire [15:0] fifo_data_out; // - " -
IBUFG clk48_ibuf(.I(CLKIN48), .O(normalclk));
OBUF fifo_valid_buf(.I(fifo_valid_out), .O(RDY0));
multi_obuf #(16) fifo_data_buf(.I(fifo_data_out), .O({PORT_D, PORT_B}));
clock_generators clkgen (.clk48(normalclk), .IFCLK(IFCLK),
.clkgen_rst(clkgen_rst),
.clksel(clksel), .fastclk(fastclk),
.ifclk_out(ifclk_int), .clocks_locked(clklock));
wire fifo_reset; // async
wire [15:0] sample_data; // fast clock domain
wire sample_data_avail; // - " -
wire fifo_overflow; // - " -
wire fcd_rst; // - " -
wire ncd_rst; // normal clock domain
fifo_generator_v9_3 fifo(.rst(fifo_reset), .wr_clk(fastclk), .rd_clk(ifclk_int),
.din(sample_data), .wr_en(sample_data_avail),
.rd_en(~CTL0), .dout(fifo_data_out),
.full(), .overflow(fifo_overflow),
.empty(), .valid(fifo_valid_out));
// normal clock domain -> fast clock domain
wire acq_enable_ncd, acq_enable_fcd;
wire acq_reset_ncd, acq_reset_fcd;
wire [7:0] clkdiv_ncd, clkdiv_fcd;
wire [15:0] channel_enable_ncd, channel_enable_fcd;
// fast clock domain -> normal clock domain
wire acq_stalled_fcd, acq_stalled_ncd;
synchronizer clklock_sync (.clk(normalclk), .in(clklock), .out(clklock_ncd));
normal_clock_domain ncd(.clk(normalclk), .rst(ncd_rst), .miso(MISO),
.mosi(MOSI), .ss(SS), .sclk(SCLK), .led_out(LED),
.acq_enable(acq_enable_ncd), .acq_reset(acq_reset_ncd),
.clock_select(clksel), .clock_divisor(clkdiv_ncd),
.channel_enable(channel_enable_ncd),
.fifo_overflow(acq_stalled_ncd), .clklock(clklock_ncd));
synchronizer acq_enable_sync (.clk(fastclk),
.in(acq_enable_ncd), .out(acq_enable_fcd));
synchronizer acq_reset_sync (.clk(fastclk),
.in(acq_reset_ncd), .out(acq_reset_fcd));
synchronizer #(8) clkdiv_sync (.clk(fastclk),
.in(clkdiv_ncd), .out(clkdiv_fcd));
synchronizer #(16) channel_enable_sync (.clk(fastclk),
.in(channel_enable_ncd),
.out(channel_enable_fcd));
synchronizer acq_stalled_sync (.clk(normalclk),
.in(acq_stalled_fcd), .out(acq_stalled_ncd));
fast_clock_domain fcd(.clk(fastclk), .rst(fcd_rst), .probe(PROBE),
.sample_data(sample_data),
.sample_data_avail(sample_data_avail),
.overflow(fifo_overflow),
.acq_enable(acq_enable_fcd),
.clock_divisor(clkdiv_fcd),
.channel_enable(channel_enable_fcd),
.stalled(acq_stalled_fcd));
assign fcd_rst = acq_reset_fcd;
assign fifo_reset = acq_reset_fcd;
// Global reset
reset_generator rst_gen (.clk(normalclk), .rst(ncd_rst));
assign clkgen_rst = ncd_rst;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__XNOR3_BEHAVIORAL_PP_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X , A, B, C );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR3_BEHAVIORAL_PP_V |
/*
* Copyright (c) Atomic Rules LLC, Auburn NH., 2009-2010
*
* Atomic Rules LLC
* 287 Chester Road
* Auburn, NH 03032
* United States of America
* Telephone 603-483-0994
*
* This file is part of OpenCPI (www.opencpi.org).
* ____ __________ ____
* / __ \____ ___ ____ / ____/ __ \ / _/ ____ _________ _
* / / / / __ \/ _ \/ __ \/ / / /_/ / / / / __ \/ ___/ __ `/
* / /_/ / /_/ / __/ / / / /___/ ____/_/ / _/ /_/ / / / /_/ /
* \____/ .___/\___/_/ /_/\____/_/ /___/(_)____/_/ \__, /
* /_/ /____/
*
* OpenCPI is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published
* by the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* OpenCPI is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with OpenCPI. If not, see <http://www.gnu.org/licenses/>.
*/
// ddrInput2.v
//
// Transforms typ ddr250 (500Mb/lvds_pair/cycle) to 1/4 rate SDR (125 MHz)
//
// 2009-11-11 ssiegel Creation
// 2010-01-06 ssiegel Adapation to use V5 ISERDES_NODELAY, add IDELAY to clock
// 2010-01-07 ssiegel Fix delays on the data input; only adjust IODELAY on clock
// 2010-01-09 ssiegel Added ClkDlyVal and DataDlyVal paramaters
// 2010-01-11 ssiegel Tweak default delay; bitslip SDR by 1 click
// 2010-01-18 ssiegel Improved OSERDES Reset Synchronizer
// 2010-01-26 ssiegel Tie unused ISERDES CE2 to 1'b1 to quiet DRC check warning
// 2010-05-15 ssiegel Added the IODELAY_GRP paramater to set the IODELAY_GROUP attribute on IODELAYs
module ddrInput2#(
parameter ClockDlyVal = 0, // Number of 78.125 pS clicks of clock delay
parameter DataDlyVal = 18, // Number of 78.125 pS clicks of data delay
parameter ndb = 7,
parameter nsb = 2*ndb,
parameter IODELAY_GRP = "IODELAY_ADC") // Used to set the IODELAY_GROUP attribute on IODELAYs
( input ddrClk, // SE DDR clock ddr250 input_clock ddr
input[ndb-1:0] ddrDataP,ddrDataN, // DIFF DDR data ddr250 Bit#(7) Action
input psClk, // phase shift Control Clock c125 default_clock in
input psRstN, // reset to default delay c125 default_reset in
input psEna, // CE for Clock IDELAY up/down c125 Bool Action
input psInc, // Inc/Dec c125 Bool Action
output sdrClk, // SDR clock from BUFR sdr125 Clock sdrClk out
output[nsb-1:0] sdrData0, // SDR Data sdr125 First Bit#(14) Value
output[nsb-1:0] sdrData1 // SDR Data sdr125 Next Bit#(14) Value
);
wire ddrClkDly, rstSerdes;
(* IODELAY_GROUP = IODELAY_GRP *) IODELAY # (
.DELAY_SRC("I"), // Port to be used, "I"=IDATAIN,"O"=ODATAIN,"DATAIN"=DATAIN,"IO"=Bi-directional
.HIGH_PERFORMANCE_MODE("TRUE"), // "TRUE" specifies lower jitter
.IDELAY_TYPE("VARIABLE"), // "FIXED" or "VARIABLE"
.IDELAY_VALUE(ClockDlyVal), // 0 to 63 tap values
.ODELAY_VALUE(0), // 0 to 63 tap values
.REFCLK_FREQUENCY(200.0), // Frequency used for IDELAYCTRL
.SIGNAL_PATTERN("CLOCK") // Input signal type, "CLOCK" or "DATA"
) IODELAY_INST (
.DATAOUT(ddrClkDly), // 1-bit delayed data output
.C(psClk), // 1-bit clock input
.CE(psEna), // 1-bit clock enable input
.DATAIN(), // 1-bit internal data input
.IDATAIN(ddrClk), // 1-bit input data input (connect to port)
.INC(psInc), // 1-bit increment/decrement input
.ODATAIN(), // 1-bit output data input
.RST(!psRstN), // 1-bit active high, synch reset input
.T() // 1-bit 3-state control input
);
BUFIO bufio_i(.O(ddrIoClk),.I(ddrClkDly));
BUFR#(.BUFR_DIVIDE("2"),.SIM_DEVICE("VIRTEX5")) bufr_i(.O(sdrClk),.CE(1'b1),.CLR(1'b0),.I(ddrClkDly));
FDRSE#(.INIT(1'b0))
FRDSE_inst (.Q(rstSerdes), .C(sdrClk), .CE(1'b1), .D(!psRstN), .R(1'b0), .S(1'b0));
// The DDR/SDR Input datapath...
wire[ndb-1:0] ddrData;
wire[(ndb-1):0] ddrDataDly;
genvar i; generate
for (i=0;i<ndb;i=i+1) begin : DDR_g
IBUFDS#(.IOSTANDARD("LVDS_25")) ibufds_i(.O(ddrData[i]),.I(ddrDataP[i]),.IB(ddrDataN[i]));
(* IODELAY_GROUP = IODELAY_GRP *) IODELAY # (
.DELAY_SRC("I"), // Port to be used, "I"=IDATAIN,"O"=ODATAIN,"DATAIN"=DATAIN,"IO"=Bi-directional
.HIGH_PERFORMANCE_MODE("TRUE"), // "TRUE" specifies lower jitter
.IDELAY_TYPE("FIXED"), // "FIXED" or "VARIABLE"
.IDELAY_VALUE(DataDlyVal), // 0 to 63 tap values
.ODELAY_VALUE(0), // 0 to 63 tap values
.REFCLK_FREQUENCY(200.0), // Frequency used for IDELAYCTRL
.SIGNAL_PATTERN("DATA") // Input signal type, "CLOCK" or "DATA"
) IODELAY_INST (
.DATAOUT(ddrDataDly[i]), // 1-bit delayed data output
.C(1'b0), // 1-bit clock input
.CE(1'b0), // 1-bit clock enable input
.DATAIN(), // 1-bit internal data input
.IDATAIN(ddrData[i]), // 1-bit input data input (connect to port)
.INC(1'b0), // 1-bit increment/decrement input
.ODATAIN(), // 1-bit output data input
.RST(rstSerdes), // 1-bit active high, synch reset input
.T() // 1-bit 3-state control input
);
ISERDES_NODELAY #(
.BITSLIP_ENABLE("TRUE"), // "TRUE"/"FALSE" to enable bitslip controller
.DATA_RATE("DDR"), // Specify data rate of "DDR" or "SDR"
.DATA_WIDTH(4), // Specify data width -
.INTERFACE_TYPE("NETWORKING"), // Use model - "MEMORY" or "NETWORKING"
.NUM_CE(1), // Number of clock enables used, 1 or 2
.SERDES_MODE("MASTER") // Set SERDES mode to "MASTER" or "SLAVE"
) ISERDES_NODELAY_inst (
.Q1(), // 1-bit registered SERDES output
.Q2(sdrData1[(i*2)+1]), // 1-bit registered SERDES output (late sample, odd bit)
.Q3(sdrData1[(i*2)+0]), // 1-bit registered SERDES output (late sample, even bit)
.Q4(sdrData0[(i*2)+1]), // 1-bit registered SERDES output (early sample, odd bit)
.Q5(sdrData0[(i*2)+0]), // 1-bit registered SERDES output (early sample, even bit)
.Q6(), // 1-bit registered SERDES output
.SHIFTOUT1(), // 1-bit cascade Master/Slave output
.SHIFTOUT2(), // 1-bit cascade Master/Slave output
.BITSLIP(1'b0), // 1-bit Bitslip enable input
.CE1(1'b1), // 1-bit clock enable input
.CE2(1'b1), // 1-bit clock enable input
.CLK(ddrIoClk), // 1-bit master clock input
.CLKB(!ddrIoClk), // 1-bit secondary clock input for DATA_RATE=DDR
.CLKDIV(sdrClk), // 1-bit divided clock input
.D(ddrDataDly[i]), // 1-bit data input, connects to IODELAY or input buffer
.OCLK(), // 1-bit fast output clock input
.RST(rstSerdes), // 1-bit asynchronous reset input
.SHIFTIN1(1'b0), // 1-bit cascade Master/Slave input
.SHIFTIN2(1'b0) // 1-bit cascade Master/Slave input
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41O_BLACKBOX_V
`define SKY130_FD_SC_HD__A41O_BLACKBOX_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a41o (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41O_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4_4_V
`define SKY130_FD_SC_MS__NOR4_4_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor4_4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor4_4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4_4_V
|
//-----------------------------------------------------------------------------
// Copyright 2017 Damien Pretet ThotIP
// Copyright 2018 Julius Baxter
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`default_nettype none
module async_bidir_fifo
#(
parameter DSIZE = 8,
parameter ASIZE = 4,
parameter FALLTHROUGH = "TRUE" // First word fall-through
) (
input wire a_clk,
input wire a_rst_n,
input wire a_winc,
input wire [DSIZE-1:0] a_wdata,
input wire a_rinc,
output wire [DSIZE-1:0] a_rdata,
output wire a_full,
output wire a_afull,
output wire a_empty,
output wire a_aempty,
input wire a_dir, // dir = 1: this side is writing, dir = 0: this side is reading
input wire b_clk,
input wire b_rst_n,
input wire b_winc,
input wire [DSIZE-1:0] b_wdata,
input wire b_rinc,
output wire [DSIZE-1:0] b_rdata,
output wire b_full,
output wire b_afull,
output wire b_empty,
output wire b_aempty,
input wire b_dir // dir = 1: this side is writing, dir = 0: this side is reading
);
wire [ASIZE-1:0] a_addr, b_addr;
wire [ASIZE-1:0] a_waddr, a_raddr, b_waddr, b_raddr;
wire [ ASIZE:0] a_wptr, b_rptr, a2b_wptr, b2a_rptr;
wire [ ASIZE:0] a_rptr, b_wptr, a2b_rptr, b2a_wptr;
assign a_addr = a_dir ? a_waddr : a_raddr;
assign b_addr = b_dir ? b_waddr : b_raddr;
//////////////////////////////////////////////////////////////////////////////
// A-side logic
//////////////////////////////////////////////////////////////////////////////
// Sync b write pointer to a domain
sync_ptr #(ASIZE)
sync_b2a_wptr
(
.dest_clk (a_clk),
.dest_rst_n (a_rst_n),
.src_ptr (b_wptr),
.dest_ptr (b2a_wptr)
);
// Sync b read pointer to a domain
sync_ptr #(ASIZE)
sync_b2a_rptr
(
.dest_clk (a_clk),
.dest_rst_n (a_rst_n),
.src_ptr (b_rptr),
.dest_ptr (b2a_rptr)
);
// The module handling the write requests
// outputs valid when dir == 0 (a is writing)
wptr_full #(ASIZE)
a_wptr_inst
(
.wclk (a_clk),
.wrst_n (a_rst_n),
.winc (a_winc),
.wq2_rptr (b2a_rptr),
.awfull (a_afull),
.wfull (a_full),
.waddr (a_waddr),
.wptr (a_wptr)
);
// dir == 1 read pointer on a side calculation
rptr_empty #(ASIZE)
a_rptr_inst
(
.rclk (a_clk),
.rrst_n (a_rst_n),
.rinc (a_rinc),
.rq2_wptr (b2a_wptr),
.arempty (a_aempty),
.rempty (a_empty),
.raddr (a_raddr),
.rptr (a_rptr)
);
//////////////////////////////////////////////////////////////////////////////
// B-side logic
//////////////////////////////////////////////////////////////////////////////
// Sync a write pointer to b domain
sync_ptr #(ASIZE)
sync_a2b_wptr
(
.dest_clk (b_clk),
.dest_rst_n (b_rst_n),
.src_ptr (a_wptr),
.dest_ptr (a2b_wptr)
);
// Sync a read pointer to b domain
sync_ptr #(ASIZE)
sync_a2b_rptr
(
.dest_clk (b_clk),
.dest_rst_n (b_rst_n),
.src_ptr (a_rptr),
.dest_ptr (a2b_rptr)
);
// The module handling the write requests
// outputs valid when dir == 0 (b is writing)
wptr_full #(ASIZE)
b_wptr_inst
(
.wclk (b_clk),
.wrst_n (b_rst_n),
.winc (b_winc),
.wq2_rptr (a2b_rptr),
.awfull (b_afull),
.wfull (b_full),
.waddr (b_waddr),
.wptr (b_wptr)
);
// dir == 1 read pointer on b side calculation
rptr_empty #(ASIZE)
b_rptr_inst
(
.rclk (b_clk),
.rrst_n (b_rst_n),
.rinc (b_rinc),
.rq2_wptr (a2b_wptr),
.arempty (b_aempty),
.rempty (b_empty),
.raddr (b_raddr),
.rptr (b_rptr)
);
//////////////////////////////////////////////////////////////////////////////
// FIFO RAM
//////////////////////////////////////////////////////////////////////////////
fifomem_dp #(DSIZE, ASIZE, FALLTHROUGH)
fifomem_dp
(
.a_clk (a_clk),
.a_wdata (a_wdata),
.a_rdata (a_rdata),
.a_addr (a_addr),
.a_rinc (a_rinc & !a_dir),
.a_winc (a_winc & a_dir),
.b_clk (b_clk),
.b_wdata (b_wdata),
.b_rdata (b_rdata),
.b_addr (b_addr),
.b_rinc (b_rinc & !b_dir),
.b_winc (b_winc & b_dir)
);
endmodule
`resetall
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/01/2015 05:56:12 PM
// Design Name:
// Module Name: des_cipher_text
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module des_datapath
(
input wire clk,
input wire reset,
// -- inputs --------------------------------------------------------- >>>>>
input wire enable,
input wire source_sel,
input wire [0:63] plaintext_din,
input wire [0:47] round_key_din,
// -- outputs -------------------------------------------------------- >>>>>
output wire [0:63] ciphertext_dout
);
// -- Declaracion temprana de señales ------------------------------------ >>>>>
wire [0:31] left_round_out;
wire [0:31] right_round_out;
// -- Initial Permutation ------------------------------------------------ >>>>>
wire [0:63] initial_permutation;
assign initial_permutation[0 +: 8] = {
plaintext_din[57],
plaintext_din[49],
plaintext_din[41],
plaintext_din[33],
plaintext_din[25],
plaintext_din[17],
plaintext_din[9],
plaintext_din[1]
};
assign initial_permutation[8 +: 8] = {
plaintext_din[59],
plaintext_din[51],
plaintext_din[43],
plaintext_din[35],
plaintext_din[27],
plaintext_din[19],
plaintext_din[11],
plaintext_din[3]
};
assign initial_permutation[16 +: 8] = {
plaintext_din[61],
plaintext_din[53],
plaintext_din[45],
plaintext_din[37],
plaintext_din[29],
plaintext_din[21],
plaintext_din[13],
plaintext_din[5]
};
assign initial_permutation[24 +: 8] = {
plaintext_din[63],
plaintext_din[55],
plaintext_din[47],
plaintext_din[39],
plaintext_din[31],
plaintext_din[23],
plaintext_din[15],
plaintext_din[7]
};
assign initial_permutation[32 +: 8] = {
plaintext_din[56],
plaintext_din[48],
plaintext_din[40],
plaintext_din[32],
plaintext_din[24],
plaintext_din[16],
plaintext_din[8],
plaintext_din[0]
};
assign initial_permutation[40 +: 8] = {
plaintext_din[58],
plaintext_din[50],
plaintext_din[42],
plaintext_din[34],
plaintext_din[26],
plaintext_din[18],
plaintext_din[10],
plaintext_din[2]
};
assign initial_permutation[48 +: 8] = {
plaintext_din[60],
plaintext_din[52],
plaintext_din[44],
plaintext_din[36],
plaintext_din[28],
plaintext_din[20],
plaintext_din[12],
plaintext_din[4]
};
assign initial_permutation[56 +: 8] = {
plaintext_din[62],
plaintext_din[54],
plaintext_din[46],
plaintext_din[38],
plaintext_din[30],
plaintext_din[22],
plaintext_din[14],
plaintext_din[6]
};
// -- Selector de origen de datos ---------------------------------------- >>>>>
wire [0:31] round_left;
wire [0:31] round_right;
assign round_left = (source_sel) ? left_round_out : initial_permutation[0 :31];
assign round_right = (source_sel) ? right_round_out : initial_permutation[32:63];
// -- Registros de Entrada ----------------------------------------------- >>>>>
reg [0:31] left_reg;
reg [0:31] right_reg;
always @(posedge clk)
begin
if (reset)
begin
left_reg <= {32{1'b0}};
right_reg <= {32{1'b0}};
end
else
if (enable)
begin
left_reg <= round_left;
right_reg <= round_right;
end
end
// -- DES function ------------------------------------------------------- >>>>>
wire [0:47] right_expansion;
wire [0:47] right_xor_key;
wire [0:31] sboxs_out;
wire [0:31] pbox_permutation;
// -- Expansion permutation ------------------------------------------ >>>>>
assign right_expansion[0 +: 6] = {right_reg[31], right_reg[0 +: 5]};
assign right_expansion[6 +: 6] = {right_reg[3 +: 6]};
assign right_expansion[12 +: 6] = {right_reg[7 +: 6]};
assign right_expansion[18 +: 6] = {right_reg[11 +: 6]};
assign right_expansion[24 +: 6] = {right_reg[15 +: 6]};
assign right_expansion[30 +: 6] = {right_reg[19 +: 6]};
assign right_expansion[36 +: 6] = {right_reg[23 +: 6]};
assign right_expansion[42 +: 6] = {
right_reg[27],
right_reg[28],
right_reg[29],
right_reg[30],
right_reg[31],
right_reg[0]
};
// -- Expanded Right XOR Round Key ----------------------------------- >>>>>
assign right_xor_key = right_expansion ^ round_key_din;
// -- S Boxes -------------------------------------------------------- >>>>>
des_sbox1 sbox1 (
.right_xor_key_segment_din(right_xor_key[0 +: 6]),
.sbox_dout(sboxs_out[0 +: 4])
);
des_sbox2 sbox2 (
.right_xor_key_segment_din(right_xor_key[6 +: 6]),
.sbox_dout(sboxs_out[4 +: 4])
);
des_sbox3 sbox3 (
.right_xor_key_segment_din(right_xor_key[12 +: 6]),
.sbox_dout(sboxs_out[8 +: 4])
);
des_sbox4 sbox4 (
.right_xor_key_segment_din(right_xor_key[18 +: 6]),
.sbox_dout(sboxs_out[12 +: 4])
);
des_sbox5 sbox5 (
.right_xor_key_segment_din(right_xor_key[24 +: 6]),
.sbox_dout(sboxs_out[16 +: 4])
);
des_sbox6 sbox6 (
.right_xor_key_segment_din(right_xor_key[30 +: 6]),
.sbox_dout(sboxs_out[20 +: 4])
);
des_sbox7 sbox7 (
.right_xor_key_segment_din(right_xor_key[36 +: 6]),
.sbox_dout(sboxs_out[24 +: 4])
);
des_sbox8 sbox8 (
.right_xor_key_segment_din(right_xor_key[42 +: 6]),
.sbox_dout(sboxs_out[28 +: 4])
);
// -- Straight Permutation ---------------------------------------------- >>>>>
assign pbox_permutation[0 +: 8] = {
sboxs_out[15],
sboxs_out[6],
sboxs_out[19],
sboxs_out[20],
sboxs_out[28],
sboxs_out[11],
sboxs_out[27],
sboxs_out[16]
};
assign pbox_permutation[8 +: 8] = {
sboxs_out[0],
sboxs_out[14],
sboxs_out[22],
sboxs_out[25],
sboxs_out[4],
sboxs_out[17],
sboxs_out[30],
sboxs_out[9]
};
assign pbox_permutation[16 +: 8] = {
sboxs_out[1],
sboxs_out[7],
sboxs_out[23],
sboxs_out[13],
sboxs_out[31],
sboxs_out[26],
sboxs_out[2],
sboxs_out[8]
};
assign pbox_permutation[24 +: 8] = {
sboxs_out[18],
sboxs_out[12],
sboxs_out[29],
sboxs_out[5],
sboxs_out[21],
sboxs_out[10],
sboxs_out[3],
sboxs_out[24]
};
// -- Salidas Parciales --------------------------------------------- >>>>>
assign left_round_out = right_reg;
assign right_round_out = pbox_permutation ^ left_reg;
// -- Final Permutation ------------------------------------------------ >>>>>
wire [0:63] partial_result;
wire [0:63] final_permutation;
assign partial_result = {right_round_out, left_round_out};
assign final_permutation[0 +: 8] = {
partial_result[39],
partial_result[7],
partial_result[47],
partial_result[15],
partial_result[55],
partial_result[23],
partial_result[63],
partial_result[31]
};
assign final_permutation[8 +: 8] = {
partial_result[38],
partial_result[6],
partial_result[46],
partial_result[14],
partial_result[54],
partial_result[22],
partial_result[62],
partial_result[30]
};
assign final_permutation[16 +: 8] = {
partial_result[37],
partial_result[5],
partial_result[45],
partial_result[13],
partial_result[53],
partial_result[21],
partial_result[61],
partial_result[29]
};
assign final_permutation[24 +: 8] = {
partial_result[36],
partial_result[4],
partial_result[44],
partial_result[12],
partial_result[52],
partial_result[20],
partial_result[60],
partial_result[28]
};
assign final_permutation[32 +: 8] = {
partial_result[35],
partial_result[3],
partial_result[43],
partial_result[11],
partial_result[51],
partial_result[19],
partial_result[59],
partial_result[27]
};
assign final_permutation[40 +: 8] = {
partial_result[34],
partial_result[2],
partial_result[42],
partial_result[10],
partial_result[50],
partial_result[18],
partial_result[58],
partial_result[26]
};
assign final_permutation[48 +: 8] = {
partial_result[33],
partial_result[1],
partial_result[41],
partial_result[9],
partial_result[49],
partial_result[17],
partial_result[57],
partial_result[25]
};
assign final_permutation[56 +: 8] = {
partial_result[32],
partial_result[0],
partial_result[40],
partial_result[8],
partial_result[48],
partial_result[16],
partial_result[56],
partial_result[24]
};
assign ciphertext_dout = final_permutation;
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : fme_ctrl.v
// Author : Yufeng Bai
// Email : [email protected]
//
// $Id$
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module fme_ctrl (
clk ,
rstn ,
sysif_start_i ,
sysif_done_o ,
current_state ,
fimeif_partition_i ,
fimeif_mv_rden_o ,
fimeif_mv_rdaddr_o ,
fimeif_mv_data_i ,
mcif_mv_rden_o ,
mcif_mv_rdaddr_o ,
mcif_mv_data_i ,
ref_rden_o ,
ref_idx_x_o ,
ref_idx_y_o ,
ip_start_o ,
ip_done_i ,
ip_mv_x_o ,
ip_mv_y_o ,
ip_frac_x_o ,
ip_frac_y_o ,
ip_half_flag_o ,
ip_idx_o ,
cost_done_i ,
predicted_en_o
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input [1-1:0] sysif_start_i ; // fme start signal
output [1-1:0] sysif_done_o ; // fme done signal
output [4-1:0] current_state ; // fme current state
input [42-1:0] fimeif_partition_i ; // ime partition info
output fimeif_mv_rden_o ;
output [6-1:0] fimeif_mv_rdaddr_o ;
input [2*`FMV_WIDTH-1:0]fimeif_mv_data_i ;
output mcif_mv_rden_o ;
output [6-1:0] mcif_mv_rdaddr_o ;
input [2*`FMV_WIDTH-1:0]mcif_mv_data_i ;
output [1-1:0] ref_rden_o ; // referenced pixel read enable
output [7-1:0] ref_idx_x_o ; // referenced pixel x index
output [7-1:0] ref_idx_y_o ; // referenced pixel y index
output [1-1:0] ip_start_o ; // interpolation start
input [1-1:0] ip_done_i ; // interpolation done
output [`FMV_WIDTH-1:0] ip_mv_x_o ; // interpolation mv x index
output [`FMV_WIDTH-1:0] ip_mv_y_o ; // interpolation mv y index
output [2-1:0] ip_frac_x_o ; // interpolation mv x index
output [2-1:0] ip_frac_y_o ; // interpolation mv y index
output [1-1:0] ip_half_flag_o ; // interpolation half/quarter flag
output [6-1:0] ip_idx_o ; // interpolation 8x8 block index
input [1-1:0] cost_done_i ; // cost cal & cmp done
output [1-1:0] predicted_en_o ;
// ********************************************
//
// WIRE / REG DECLARATION
//
// ********************************************
parameter IDLE = 4'd0;
parameter PRE_HALF = 4'd1;
parameter HALF = 4'd2;
parameter DONE_HALF = 4'd3;
parameter PRE_QUAR = 4'd4;
parameter QUAR = 4'd5;
parameter DONE_QUAR = 4'd6;
parameter PRE_MC = 4'd7;
parameter MC = 4'd8;
parameter DONE_MC = 4'd9;
// ********************************************
//
// WIRE / REG DECLARATION
//
// ********************************************
reg [3: 0] current_state, next_state;
reg [1: 0] cnt32, cnt16, cnt08;
reg [1: 0] mode32, mode16;
wire [1: 0] mode64;
wire [2: 0] fimeif_rdaddr_x;
wire [2: 0] fimeif_rdaddr_y;
wire signed [`FMV_WIDTH-1:0] imv_x ;
wire signed [`FMV_WIDTH-1:0] imv_y ;
wire signed [`FMV_WIDTH-1:0] fmv_x ;
wire signed [`FMV_WIDTH-1:0] fmv_y ;
reg [1-1 :0] ip_start_o ;
reg [3: 0] refcnt ;
reg [1-1:0] sysif_done_o ;
wire [2-1: 0] partition64 ;
wire [2-1: 0] partition32_00 ;
wire [2-1: 0] partition32_01 ;
wire [2-1: 0] partition32_02 ;
wire [2-1: 0] partition32_03 ;
wire [2-1: 0] partition16_00 ;
wire [2-1: 0] partition16_01 ;
wire [2-1: 0] partition16_02 ;
wire [2-1: 0] partition16_03 ;
wire [2-1: 0] partition16_04 ;
wire [2-1: 0] partition16_05 ;
wire [2-1: 0] partition16_06 ;
wire [2-1: 0] partition16_07 ;
wire [2-1: 0] partition16_08 ;
wire [2-1: 0] partition16_09 ;
wire [2-1: 0] partition16_10 ;
wire [2-1: 0] partition16_11 ;
wire [2-1: 0] partition16_12 ;
wire [2-1: 0] partition16_13 ;
wire [2-1: 0] partition16_14 ;
wire [2-1: 0] partition16_15 ;
wire signed [3-1: 0] dmv_x, dmv_y ;
wire [2-1: 0] frac_x, frac_y ;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign partition64 = fimeif_partition_i[1 : 0];
assign partition32_00 = fimeif_partition_i[3 : 2];
assign partition32_01 = fimeif_partition_i[5 : 4];
assign partition32_02 = fimeif_partition_i[7 : 6];
assign partition32_03 = fimeif_partition_i[9 : 8];
assign partition16_00 = fimeif_partition_i[11 : 10];
assign partition16_01 = fimeif_partition_i[13 : 12];
assign partition16_02 = fimeif_partition_i[15 : 14];
assign partition16_03 = fimeif_partition_i[17 : 16];
assign partition16_04 = fimeif_partition_i[19 : 18];
assign partition16_05 = fimeif_partition_i[21 : 20];
assign partition16_06 = fimeif_partition_i[23 : 22];
assign partition16_07 = fimeif_partition_i[25 : 24];
assign partition16_08 = fimeif_partition_i[27 : 26];
assign partition16_09 = fimeif_partition_i[29 : 28];
assign partition16_10 = fimeif_partition_i[31 : 30];
assign partition16_11 = fimeif_partition_i[33 : 32];
assign partition16_12 = fimeif_partition_i[35 : 34];
assign partition16_13 = fimeif_partition_i[37 : 36];
assign partition16_14 = fimeif_partition_i[39 : 38];
assign partition16_15 = fimeif_partition_i[41 : 40];
assign mode64 = partition64;
always @ (*) begin
case(cnt32)
2'd0: mode32 = partition32_00;
2'd1: mode32 = partition32_01;
2'd2: mode32 = partition32_02;
2'd3: mode32 = partition32_03;
endcase
end
always @ (*) begin
case({cnt32,cnt16})
4'd00:mode16 = partition16_00;
4'd01:mode16 = partition16_01;
4'd02:mode16 = partition16_02;
4'd03:mode16 = partition16_03;
4'd04:mode16 = partition16_04;
4'd05:mode16 = partition16_05;
4'd06:mode16 = partition16_06;
4'd07:mode16 = partition16_07;
4'd08:mode16 = partition16_08;
4'd09:mode16 = partition16_09;
4'd10:mode16 = partition16_10;
4'd11:mode16 = partition16_11;
4'd12:mode16 = partition16_12;
4'd13:mode16 = partition16_13;
4'd14:mode16 = partition16_14;
4'd15:mode16 = partition16_15;
endcase
end
always @ (*) begin
case ( current_state)
IDLE : begin
if (sysif_start_i) begin
next_state = PRE_HALF;
end
else begin
next_state = IDLE;
end
end
PRE_HALF: next_state = HALF;
HALF : begin
if (cnt08 == 'd3 && cnt16 == 'd3 && cnt32 == 'd3 && refcnt == 'd15) begin
next_state = DONE_HALF;
end
else begin
next_state = HALF;
end
end
DONE_HALF: begin
if (cost_done_i)
next_state = PRE_QUAR;
else
next_state = DONE_HALF;
end
PRE_QUAR: next_state = QUAR;
QUAR : begin
if (cnt08 == 'd3 && cnt16 == 'd3 && cnt32 == 'd3 && refcnt == 'd15) begin
next_state = DONE_QUAR;
end
else begin
next_state = QUAR;
end
end
DONE_QUAR: begin
if (cost_done_i)
next_state = PRE_MC;
else
next_state = DONE_QUAR;
end
PRE_MC: next_state = MC;
MC : begin
if (cnt08 == 'd3 && cnt16 == 'd3 && cnt32 == 'd3 && refcnt == 'd15) begin
next_state = DONE_MC;
end
else begin
next_state = MC;
end
end
DONE_MC: begin
if (ip_done_i) begin
next_state = IDLE;
end
else begin
next_state = DONE_MC;
end
end
default:next_state = IDLE;
endcase
end
// ********************************************
//
// Sequential Logic
//
// ********************************************
//fsm
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
current_state <= IDLE;
end
else begin
current_state <= next_state;
end
end
// fme done
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
sysif_done_o <= 'd0;
end
else if(current_state == DONE_MC && ip_done_i) begin
sysif_done_o <= 1'b1;
end
else begin
sysif_done_o <= 1'b0;
end
end
// block index generation
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
cnt32 <= 'd0;
end
else if (current_state == IDLE || current_state == DONE_HALF || current_state == DONE_QUAR) begin
cnt32 <= 'd0;
end
else if (cnt16 == 'd3 && cnt08 == 'd3 && refcnt == 'd15) begin
case (cnt32)
'd0 : cnt32 <= (mode64 == `PART_NX2N) ? 'd2 : 'd1;
'd1 : cnt32 <= (mode64 == `PART_NX2N) ? 'd3 : 'd2;
'd2 : cnt32 <= (mode64 == `PART_NX2N) ? 'd1 : 'd3;
'd3 : cnt32 <= 'd0;
endcase
end
end
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
cnt16 <= 'd0;
end
else if (current_state == IDLE || current_state == DONE_HALF || current_state == DONE_QUAR) begin
cnt16 <= 'd0;
end
else if (cnt08 == 'd3 && refcnt == 'd15) begin
case (cnt16)
'd0 : cnt16 <= (mode32 == `PART_NX2N) ? 'd2 : 'd1;
'd1 : cnt16 <= (mode32 == `PART_NX2N) ? 'd3 : 'd2;
'd2 : cnt16 <= (mode32 == `PART_NX2N) ? 'd1 : 'd3;
'd3 : cnt16 <= 'd0;
endcase
end
end
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
cnt08 <= 'd0;
end
else if (current_state == IDLE || current_state == DONE_HALF || current_state == DONE_QUAR) begin
cnt08 <= 'd0;
end
else if (refcnt == 'd15) begin
case (cnt08)
'd0 : cnt08 <= (mode16 == `PART_NX2N) ? 'd2 : 'd1;
'd1 : cnt08 <= (mode16 == `PART_NX2N) ? 'd3 : 'd2;
'd2 : cnt08 <= (mode16 == `PART_NX2N) ? 'd1 : 'd3;
'd3 : cnt08 <= 'd0;
endcase
end
end
// mv fetching
//
assign fimeif_mv_rden_o = (current_state == PRE_HALF || current_state == PRE_QUAR || current_state == PRE_MC || (refcnt =='d0 && ~ip_start_o && (current_state != IDLE && current_state != DONE_HALF && current_state != DONE_QUAR && current_state != DONE_MC)));
assign fimeif_rdaddr_x = {cnt32[0],cnt16[0],cnt08[0]};
assign fimeif_rdaddr_y = {cnt32[1],cnt16[1],cnt08[1]};
assign fimeif_mv_rdaddr_o = {fimeif_rdaddr_y,fimeif_rdaddr_x};
assign mcif_mv_rden_o = fimeif_mv_rden_o && (current_state == PRE_QUAR || current_state == QUAR);
assign mcif_mv_rdaddr_o = {fimeif_rdaddr_y,fimeif_rdaddr_x};
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
ip_start_o <= 1'b0;
end
else begin
ip_start_o <= fimeif_mv_rden_o;
end
end
// ref pixel fetch
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
refcnt <= 'd0;
end
else if ( fimeif_mv_rden_o || current_state == DONE_HALF || current_state == DONE_QUAR || current_state == IDLE) begin
refcnt <= 'd0;
end
else begin
refcnt <= refcnt + 'd1;
end
end
assign imv_x = fimeif_mv_data_i[2*`FMV_WIDTH-1 : `FMV_WIDTH];
assign imv_y = fimeif_mv_data_i[`FMV_WIDTH-1 : 0];
assign fmv_x = mcif_mv_data_i [2*`FMV_WIDTH-1 : `FMV_WIDTH];
assign fmv_y = mcif_mv_data_i [`FMV_WIDTH-1 : 0];
assign ip_mv_x_o = (ip_half_flag_o) ? imv_x : fmv_x;
assign ip_mv_y_o = (ip_half_flag_o) ? imv_y : fmv_y;
assign ip_half_flag_o = (current_state == HALF || current_state == DONE_HALF) ? 1'b1 : 1'b0;
assign ip_idx_o = {cnt32, cnt16, cnt08};
assign ref_idx_x_o = imv_x[8:2] + {1'b0, cnt32[0], cnt16[0], cnt08[0],3'b0} + 7'd12; // imv for refpel fetching
assign ref_idx_y_o = imv_y[8:2] + {1'b0, cnt32[1], cnt16[1], cnt08[1],3'b0} + {3'b0,refcnt} + 7'd12; // imv for refpel fetching
assign ref_rden_o = (current_state == HALF || current_state == QUAR || current_state == MC) && ~fimeif_mv_rden_o;
assign dmv_x = fmv_x - imv_x;
assign dmv_y = fmv_y - imv_y;
assign frac_x = (dmv_x == 0) ? 2'b0 : ((dmv_x > 0) ? 2'b01 : 2'b11);
assign frac_y = (dmv_y == 0) ? 2'b0 : ((dmv_y > 0) ? 2'b01 : 2'b11);
assign ip_frac_x_o = (ip_half_flag_o) ? 2'b00 : frac_x;
assign ip_frac_y_o = (ip_half_flag_o) ? 2'b00 : frac_y;
assign predicted_en_o = (current_state == MC || current_state == DONE_MC);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
//
// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
////////////////////////////////////////////////////////////////////////////////
// Design Name: aurora_64b66b_25p4G_WRAPPER
//
// Module aurora_64b66b_25p4G_WRAPPER
// This is V8/K8 wrapper
`timescale 1 ps / 1 ps
(* core_generation_info = "aurora_64b66b_25p4G,aurora_64b66b_v11_2_2,{c_aurora_lanes=1,c_column_used=left,c_gt_clock_1=GTYQ0,c_gt_clock_2=None,c_gt_loc_1=1,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=25.4,c_gt_type=GTYE4,c_qpll=true,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=100.0,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=false,c_user_k=false,flow_mode=None,interface_mode=Framing,dataflow_config=Duplex}" *)
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_WRAPPER #
(
parameter INTER_CB_GAP = 5'd9,
parameter SEQ_COUNT = 4,
parameter wait_for_fifo_wr_rst_busy_value = 6'd32,
parameter TRAVELLING_STAGES = 3'd2,
parameter BACKWARD_COMP_MODE1 = 1'b0, //disable check for interCB gap
parameter BACKWARD_COMP_MODE2 = 1'b0, //reduce RXCDR lock time, Block Sync SH max count, disable CDR FSM in wrapper
parameter BACKWARD_COMP_MODE3 = 1'b0, //clear hot-plug counter with any valid btf detected
parameter SCRAMBLER_SEED = 58'h2AA_AAAA_AAAA_AAAA,
// Channel bond MASTER/SLAVE connection
parameter CHAN_BOND_MODE_0 = 2'b00,
parameter CHAN_BOND_MODE_1 = 2'b00,
// Simulation attributes
parameter EXAMPLE_SIMULATION = 0 // Set to 1 to speed up sim reset
)
`define DLY #1
(
//----------------- Receive Ports - Channel Bonding Ports -----------------
ENCHANSYNC_IN,
CHBONDDONE_OUT,
//RXLOSSOFSYNC indication
RXLOSSOFSYNC_OUT,
//----------------- Receive Ports - Clock Correction Ports -----------------
RXBUFERR_OUT,
//----------------- Receive Ports - RX Data Path interface -----------------
RXDATA_OUT,
RXHEADER_OUT,
RXHEADER_OUT_ERR,
RXRESET_IN,
RXUSRCLK2_IN,
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RX1N_IN,
RX1P_IN,
//--------------- Receive Ports - RX Polarity Control Ports ----------------
CHECK_POLARITY_IN,
RXPOLARITY_IN,
RX_NEG_OUT,
//------------------- Shared Ports - Tile and PLL Ports --------------------
REFCLK1_IN,
GTXRESET_IN,
RESET,
GT_RXCDROVRDEN_IN,
CHAN_BOND_RESET,
PLLLKDET_OUT,
POWERDOWN_IN,
TXOUTCLK1_OUT,
//-------------- Transmit Ports - 64b66b TX Header Ports --------------
TXHEADER_IN,
//---------------- Transmit Ports - TX Data Path interface -----------------
TXDATA_IN,
TXRESET_IN,
TXUSRCLK_IN,//
TXUSRCLK2_IN,//
//txusrclk_out,
//txusrclk2_out,
TXBUFERR_OUT,
//--------------Data Valid Signals for Local Link
TXDATAVALID_OUT,
TXDATAVALID_SYMGEN_OUT,
RXDATAVALID_OUT,
//------------- Transmit Ports - TX Driver and OOB signalling --------------
TX1N_OUT,
TX1P_OUT,
//---------------------- Loopback Port ----------------------
LOOPBACK_IN,
//---------------------- GTXE2 CHANNEL DRP Ports ----------------------
DRP_CLK_IN,
//---{
gt_qpllclk_quad1_in,
gt_qpllrefclk_quad1_in,
gt_qplllock_quad1_in,
gt_qpllrefclklost_quad1,
//gt_qplllock_in,
//gt_qpllrefclklost_in,
gt_to_common_qpllreset_out,
//---}
gt0_drpaddr,
gt0_drpdi,
gt0_drpdo,
gt0_drprdy,
gt0_drpen,
gt0_drpwe,
//---------------------- GTXE2 COMMON DRP Ports ----------------------
gt_powergood,
//TXCLK_LOCK,
INIT_CLK,
USER_CLK,
FSM_RESETDONE,
LINK_RESET_OUT,
bufg_gt_clr_out, // connect to clk_locked port of clocking module
gtwiz_userclk_tx_active_out// connect to mmcm not locked of clocking module
);
//***************************** Port Declarations *****************************
//---------------------- Loopback and Powerdown Ports ----------------------
input [2:0] LOOPBACK_IN;
//----------------- Receive Ports - Channel Bonding Ports -----------------
//----------------- Receive Ports - Channel Bonding Ports -----------------
input ENCHANSYNC_IN;
output CHBONDDONE_OUT;
output RXLOSSOFSYNC_OUT;
//----------------- Receive Ports - Clock Correction Ports -----------------
output RXBUFERR_OUT;
//----------------- Receive Ports - RX Data Path interface -----------------
output [63:0] RXDATA_OUT;
output [1:0] RXHEADER_OUT;
output RXHEADER_OUT_ERR;
input RXRESET_IN;
input RXUSRCLK2_IN;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
input RX1N_IN;
input RX1P_IN;
//--------------- Receive Ports - RX Polarity Control Ports ----------------
input CHECK_POLARITY_IN;
input RXPOLARITY_IN;
output reg RX_NEG_OUT;
//------------------- Shared Ports - Tile and PLL Ports --------------------
input REFCLK1_IN;
input GTXRESET_IN;
input CHAN_BOND_RESET;
output PLLLKDET_OUT;
output TXOUTCLK1_OUT;
input POWERDOWN_IN;
input RESET;
input GT_RXCDROVRDEN_IN;
//-------------- Transmit Ports - TX Header Control Port ----------------
input [1:0] TXHEADER_IN;
//---------------- Transmit Ports - TX Data Path interface -----------------
input [63:0] TXDATA_IN;
input TXRESET_IN;
output TXBUFERR_OUT;
input TXUSRCLK_IN;//
input TXUSRCLK2_IN;//
//output txusrclk_out;//
//output txusrclk2_out;//
//------------- Transmit Ports - TX Driver and OOB signalling --------------
output TX1N_OUT;
output TX1P_OUT;
output TXDATAVALID_OUT;
output TXDATAVALID_SYMGEN_OUT;
output RXDATAVALID_OUT;
//---------------------- GTXE2 CHANNEL DRP Ports ----------------------
input DRP_CLK_IN;
//---{
input gt_qpllclk_quad1_in;// connected to GT common
input gt_qpllrefclk_quad1_in;// connected to GT common
input gt_qplllock_quad1_in ;
input gt_qpllrefclklost_quad1;
//input gt_qplllock_in;
//input gt_qpllrefclklost_in;
output gt_to_common_qpllreset_out;
//---}
input [9:0] gt0_drpaddr;
input [15:0] gt0_drpdi;
output [15:0] gt0_drpdo;
output gt0_drprdy;
input gt0_drpen;
input gt0_drpwe;
output [0:0] gt_powergood;
//input TXCLK_LOCK;
input INIT_CLK;
input USER_CLK;
output reg LINK_RESET_OUT;
output wire FSM_RESETDONE;
output bufg_gt_clr_out; // connect to clocking module
input gtwiz_userclk_tx_active_out;// connect to clocking module
//***************************** FIFO Watermark settings ************************
localparam LOW_WATER_MARK_SLAVE = 13'd450;
localparam LOW_WATER_MARK_MASTER = 13'd450;
localparam HIGH_WATER_MARK_SLAVE = 13'd8;
localparam HIGH_WATER_MARK_MASTER = 13'd14;
localparam SH_CNT_MAX = EXAMPLE_SIMULATION ? 16'd64 : (BACKWARD_COMP_MODE2) ? 16'd64 : 16'd60000;
localparam SH_INVALID_CNT_MAX = 16'd16;
//***************************** Wire Declarations *****************************
// Ground and VCC signals
wire tied_to_ground_i;
wire [280:0] tied_to_ground_vec_i;
// floating input port connection signals
wire [1:0] open_rxbufstatus_i;
wire open_txbufstatus_i;
// wire to output lock signal
wire tx_plllkdet_i;
wire rx_plllkdet_i;
// Electrical idle reset logic signals
wire resetdone_i;
wire rx_resetdone_i;
wire tx_resetdone_i;
// Channel Bonding
wire [4:0] chbondi;
wire [4:0] chbondi_unused_i;
wire [4:0] chbondo_to_slaves_i;
wire state;
wire [6:0] txsequence_i;
reg txsequence_ctr_en_int = 1'b0;
reg [6:0] txseq_counter_i;
wire data_valid_i;
reg [6:0] datavalid_counter_i;
reg [10:0] count_for_reset_r;
reg [2:0] extend_reset_r;
reg resetdone_r1;
reg resetdone_r2;
reg resetdone_r3;
reg reset_r1;
reg reset_r2;
reg rx_reset_r1;
reg rx_reset_r2;
reg [3:0] reset_debounce_r;
reg data_valid_r;
reg FSM_RESETDONE_j;
//reg [63:0] pmaInitStage = 64'd0;
wire [1:0] txheader_i;
wire [63:0] scrambled_data_i;
(* shift_extract = "{no}"*) wire [63:0] pre_rxdata_from_gtx_i;
(* shift_extract = "{no}"*) wire [1:0] pre_rxheader_from_gtx_i;
(* shift_extract = "{no}"*) wire pre_rxdatavalid_i;
(* shift_extract = "{no}"*) wire pre_rxheadervalid_i;
(* shift_extract = "{no}"*) reg [63:0] pre_r1_rxdata_from_gtx_i;
(* shift_extract = "{no}"*) reg [1:0] pre_r1_rxheader_from_gtx_i;
(* shift_extract = "{no}"*) reg pre_r1_rxdatavalid_i;
(* shift_extract = "{no}"*) reg pre_r1_rxheadervalid_i;
(* shift_extract = "{no}"*) reg [63:0] pre_r2_rxdata_from_gtx_i;
(* shift_extract = "{no}"*) reg [1:0] pre_r2_rxheader_from_gtx_i;
(* shift_extract = "{no}"*) reg pre_r2_rxdatavalid_i;
(* shift_extract = "{no}"*) reg pre_r2_rxheadervalid_i;
(* shift_extract = "{no}"*) reg [63:0] pre_r3_rxdata_from_gtx_i;
(* shift_extract = "{no}"*) reg [1:0] pre_r3_rxheader_from_gtx_i;
(* shift_extract = "{no}"*) reg pre_r3_rxdatavalid_i;
(* shift_extract = "{no}"*) reg pre_r3_rxheadervalid_i;
(* shift_extract = "{no}"*) reg [63:0] pre_r4_rxdata_from_gtx_i;
(* shift_extract = "{no}"*) reg [1:0] pre_r4_rxheader_from_gtx_i;
(* shift_extract = "{no}"*) reg pre_r4_rxdatavalid_i;
(* shift_extract = "{no}"*) reg pre_r4_rxheadervalid_i;
(* shift_extract = "{no}"*) reg [63:0] pos_rxdata_from_gtx_i;
(* shift_extract = "{no}"*) reg [1:0] pos_rxheader_from_gtx_i;
(* shift_extract = "{no}"*) reg pos_rxdatavalid_i;
(* shift_extract = "{no}"*) reg pos_rxheadervalid_i;
(* shift_extract = "{no}"*) reg [63:0] rxdata_from_gtx_i;
(* shift_extract = "{no}"*) reg [1:0] rxheader_from_gtx_i;
(* shift_extract = "{no}"*) reg rxdatavalid_i;
(* shift_extract = "{no}"*) reg rxheadervalid_i;
wire rxgearboxslip_i;
wire open_rxheader_i;
wire rxlossofsync_out_i;
reg rxlossofsync_out_q;
wire [63:0] rxdata_to_fifo_i;
wire rxrecclk_from_gtx_i;
wire [0:6] not_connected_i;
wire sync_rx_polarity_r;
wire [0:0] sync_rx_polarity_r_j;
wire check_polarity_r2;
wire gtpll_locked_out_r2;
reg reset_blocksync_r;
reg new_gtx_rx_pcsreset_comb = 1'b1;
// (* KEEP = "TRUE" *) wire rxrecclk_to_fabric_i;
// (* KEEP = "TRUE" *) wire rxfsm_reset_i;//
wire clkfbout_i;
wire locked_i;
wire gtx_rx_pcsreset_comb;
wire enable_32_i = 1'b1;
wire gtpll_locked_out_i;
wire gt_qplllock_quad1_i;
wire gt_qplllock_quad2_i;
wire gt_qplllock_quad3_i;
wire gt_qplllock_quad4_i;
wire gt_qplllock_quad5_i;
wire txusrclk_gtx_reset_comb;
wire stableclk_gtx_reset_comb;
wire gtx_reset_comb;
reg [1:0] txheader_r;
reg [1:0] tx_hdr_r;
reg [1:0] cdr_reset_fsm_r = 2'd0;
reg [7:0] cdr_reset_fsm_cntr_r = 8'd0;
reg allow_block_sync_propagation = 1'b0;
reg cdr_reset_fsm_lnkreset = 1'b0;
localparam IDLE = 2'b00;
localparam ASSERT_RXRESET = 2'b01;
localparam DONE = 2'b10;
wire allow_block_sync_propagation_inrxclk;
wire blocksync_all_lanes_instableclk;
wire blocksync_out_i;
wire blocksync_all_lanes_inrxclk;
reg blocksync_all_lanes_inrxclk_q = 1'b0;
wire hpreset_or_pma_init_in;
wire hpreset_in;
wire hp_reset_i;
wire [1:0] rxbuferr_out_i;
wire [1:0] link_reset_0_c;
wire link_reset_c;
//-------------------------------------------------
//-------------------------------------------------
wire qpllreset_i;
assign gt_to_common_qpllreset_out = qpllreset_i;
wire gtxreset_i;
reg rxdatavalid_to_fifo_i;
reg [1:0] rxheader_to_fifo_i;
wire tied_to_vcc_i;
reg [7:0] reset_counter = 8'd0;
(* KEEP = "TRUE" *) wire rx_fsm_resetdone_i;
(* KEEP = "TRUE" *) wire tx_fsm_resetdone_i;
(* KEEP = "TRUE" *) wire rx_fsm_resetdone_ii;
(* KEEP = "TRUE" *) wire tx_fsm_resetdone_ii;
wire rx_fsm_resetdone_i_i;
wire tx_fsm_resetdone_i_i;
wire rx_fsm_resetdone_i_j;
wire tx_fsm_resetdone_i_j;
wire gtrxreset_t;
wire gtrxreset_i;
wire gttxreset_t;
// wire txuserrdy_t;
// wire rxuserrdy_t;
wire cpllreset_t;
wire qpllreset_t;
wire qpllrefclklost_i;
wire cpllrefclklost_i;
wire [0:0] tx_resetdone_j;
wire [0:0] rx_resetdone_j;
wire tx_resetdone_t;
wire rx_resetdone_t;
wire mmcm_reset_i;
wire enchansync_all_i;
wire txreset_for_lanes;
wire rxreset_for_lanes;
reg rxreset_for_lanes_q;
// wire HPCNT_RESET_IN;//
// wire sys_and_fsm_reset_for_hpcnt;//
// Common CBCC Reset module wires
wire cbcc_fifo_reset_wr_clk;
wire cbcc_fifo_reset_to_fifo_wr_clk;
wire cbcc_data_srst;
wire cbcc_fifo_reset_rd_clk;
wire cbcc_fifo_reset_to_fifo_rd_clk;
wire cbcc_only_reset_rd_clk;
wire cbcc_reset_cbstg2_rd_clk;
// Common Logic for CBCC module reg/wires
wire any_vld_btf_i;
wire start_cb_writes_i;
(* KEEP = "TRUE" *) wire do_rd_en_i;
(* KEEP = "TRUE" *) wire bit_err_chan_bond_i;
(* KEEP = "TRUE" *) wire final_gater_for_fifo_din_i;
(* KEEP = "TRUE" *) wire all_start_cb_writes_i ;
(* KEEP = "TRUE" *) wire master_do_rd_en_i ;
(* KEEP = "TRUE" *) wire all_vld_btf_flag_i ;
wire cb_bit_err_i;
wire fsm_resetdone_to_new_gtx_rx_comb;
wire rxusrclk_out;
//********************************* Main Body of Code**************************
// For GT Assignment
assign sync_rx_polarity_r_j = {
sync_rx_polarity_r
};
//------------------------- Static signal Assigments ---------------------
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 281'h0;
assign tied_to_vcc_i = 1'b1;
//------------------------------------------------------------------------------
// Assign lock signals
//-----------------------
//-----------------------
/// quad 1 channels
assign PLLLKDET_OUT = gt_qplllock_quad1_i &
//!mmcm_reset_i;// channel 1 will be default
//!mmcm_reset_i;
mmcm_reset_i;
aurora_64b66b_25p4G_cdc_sync
# (
.c_cdc_type (1), // 0 Pulse synchronizer, 1 level synchronizer 2 level synchronizer with ACK
.c_flop_input (0), // 1 Adds one flop stage to the input prmry_in signal
.c_reset_state (0), // 1 Reset needed for sync flops
.c_single_bit (1), // 1 single bit input.
.c_mtbf_stages (5) // Number of sync stages needed
) u_cdc_gt_qplllock_quad1_i
(
.prmry_aclk (1'b0),
.prmry_rst_n (1'b1 ),
.prmry_in (gt_qplllock_quad1_in),
.prmry_vect_in ('d0 ),
.scndry_aclk (INIT_CLK ),
.scndry_rst_n (1'b1 ),
.prmry_ack ( ),
.scndry_out (gt_qplllock_quad1_i),
.scndry_vect_out ( )
);
/// quad 2 channels
/// quad 3 channels
/// quad 4 channels
/// quad 5 channels
//-----------------------
//------------------------------------------------------------------------------
assign RXBUFERR_OUT =
rxbuferr_out_i[1]
||
rxbuferr_out_i[0];
//------------------------------------------------------------------------------
// TXBUFERR_OUT ports are not used & are tied to ground
assign TXBUFERR_OUT = 1'b0;
//------------------------------------------------------------------------------
// Channel Bonding
assign chbondi_unused_i = 5'b0;
//------------------------------------------------------------------------------
assign chbondi = chbondi_unused_i;
//------------------------------------------------------------------------------
assign tx_resetdone_t = tx_resetdone_i;
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// below synchronizers are needed for synchronizing the xx_fsm_resetdone in user clock domain
//----------------------------------------
// rx_fsm_resetdone_i sychronized on user_clock
aurora_64b66b_25p4G_rst_sync #
(
.c_mtbf_stages (3)
)u_rst_done_sync_rx
(
.prmry_in (rx_fsm_resetdone_i),
.scndry_aclk (USER_CLK),
.scndry_out (rx_fsm_resetdone_i_i)
);
//----------------------------------------
// rx_fsm_resetdone_i sychronized on rxusrclk_out
aurora_64b66b_25p4G_rst_sync #
(
.c_mtbf_stages (3)
)u_rst_done_sync_rx1
(
.prmry_in (rx_fsm_resetdone_i),
.scndry_aclk (rxusrclk_out),
.scndry_out (rx_fsm_resetdone_i_j)
);
//----------------------------------------
// tx_fsm_resetdone_i sychronized on user_clock
aurora_64b66b_25p4G_rst_sync #
(
.c_mtbf_stages (3)
)u_rst_done_sync_tx
(
.prmry_in (tx_fsm_resetdone_i),
.scndry_aclk (USER_CLK),
.scndry_out (tx_fsm_resetdone_i_i)
);
//----------------------------------------
// tx_fsm_resetdone_i sychronized on rxusrclk_out
aurora_64b66b_25p4G_rst_sync #
(
.c_mtbf_stages (3)
)u_rst_done_sync_tx1
(
.prmry_in (tx_fsm_resetdone_i),
.scndry_aclk (rxusrclk_out),
.scndry_out (tx_fsm_resetdone_i_j)
);
//----------------------------------------
//------------------------------------------------------------------------------
// Assumption: TR/RX Reset Done are static and will remain active once activated
assign FSM_RESETDONE = tx_fsm_resetdone_i_i & rx_fsm_resetdone_i_i;
assign FSM_RESETDONE_i = tx_fsm_resetdone_i_j & rx_fsm_resetdone_i_j;
always @(posedge USER_CLK) begin
FSM_RESETDONE_j <= `DLY FSM_RESETDONE;
end
//------------------------------------------------------------------------------
aurora_64b66b_25p4G_rst_sync u_rst_sync_txusrclk_gtx_reset_comb
(
.prmry_in (txusrclk_gtx_reset_comb),
.scndry_aclk (INIT_CLK),
.scndry_out (stableclk_gtx_reset_comb)
);
aurora_64b66b_25p4G_rst_sync u_rst_sync_gtx_reset_comb
(
.prmry_in (stableclk_gtx_reset_comb),
.scndry_aclk (TXUSRCLK2_IN),
.scndry_out (gtx_reset_comb)
);
//------------------------------------------------------------------------------
//------------------------- External Sequence Counter--------------------------
//always @(TXUSRCLK2_IN)//
always @(posedge TXUSRCLK2_IN)
begin
if(gtx_reset_comb) begin
txseq_counter_i <= `DLY 7'd0;
txsequence_ctr_en_int <= `DLY 1'b0;
end
else if (txsequence_ctr_en_int) begin
if(txseq_counter_i == 32)
txseq_counter_i <= `DLY 7'd0;
else
txseq_counter_i <= `DLY txseq_counter_i + 7'd1;
end
txsequence_ctr_en_int <= `DLY ~txsequence_ctr_en_int;
end
//Assign the Data Valid signal
assign TXDATAVALID_OUT = ((txseq_counter_i != 30));
//assign TXDATAVALID_OUT = ((txseq_counter_i != 30) && !((txseq_counter_i == 29) && txsequence_ctr_en_int));
assign TXDATAVALID_SYMGEN_OUT = (txseq_counter_i != 31);
assign data_valid_i = (txseq_counter_i != 32);
//------------------------
//------------------------
//------------------------
assign gtpll_locked_out_i = gt_qplllock_quad1_i;
//------------------------
//------------------------
//------------------------
//------------------------
//------------------------
//------------------------------------------------------------------------------
assign gtpll_locked_out_r2 = gtpll_locked_out_i;
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// qualifying the reset from gtx_rx_pcsreset_comb with !FSM_RESETDONE to
// avoid X propagation
aurora_64b66b_25p4G_rst_sync u_rst_sync_fsm_resetdone
(
.prmry_in(FSM_RESETDONE_j),
.scndry_aclk (rxusrclk_out), // (rxrecclk_to_fabric_i),
.scndry_out (fsm_resetdone_to_new_gtx_rx_comb)
);
//-- logical oring of incoming rx reset in signal for no. of lanes
assign rxreset_for_lanes = RXRESET_IN;
//--ored rx_reset_in signal is taken in the recovered rx clock
always @(posedge RXUSRCLK2_IN)
begin
rxreset_for_lanes_q <= `DLY rxreset_for_lanes;
end
//-- added synchronizer
wire fsm_resetdone_to_rxreset_in;
aurora_64b66b_25p4G_rst_sync u_rst_sync_rxreset_in
(
.prmry_in (rxreset_for_lanes_q),
.scndry_aclk (rxusrclk_out),
.scndry_out (fsm_resetdone_to_rxreset_in)
);
//--
always @(posedge rxusrclk_out)//always @(posedge rxrecclk_to_fabric_i)
begin
new_gtx_rx_pcsreset_comb = gtx_rx_pcsreset_comb
| (!fsm_resetdone_to_new_gtx_rx_comb)
| fsm_resetdone_to_rxreset_in ;
end
assign hpreset_or_pma_init_in = GTXRESET_IN | hpreset_in;
assign hpreset_in = link_reset_0_c[0];
assign gtrxreset_i = gtrxreset_t;
//------------------------------------------------------------------------------
always @ (posedge TXUSRCLK2_IN)//always @ (posedge TXUSRCLK2_IN)
begin
tx_hdr_r <= `DLY TXHEADER_IN;
end
assign txreset_for_lanes = TXRESET_IN;
//------------------------------------------------------------------------------
always @ (posedge INIT_CLK)
LINK_RESET_OUT <= `DLY
cdr_reset_fsm_lnkreset |
link_reset_0_c[0] ;
//Clocking onto the INIT-clock.
aurora_64b66b_25p4G_cdc_sync
# (
.c_cdc_type (1), // 0 Pulse synchronizer, 1 level synchronizer 2 level synchronizer with ACK
.c_flop_input (0), // 1 Adds one flop stage to the input prmry_in signal
.c_reset_state (0), // 1 Reset needed for sync flops
.c_single_bit (1), // 1 single bit input.
.c_mtbf_stages (5) // Number of sync stages needed
) u_cdc_tx_fsm_resetdone_i
(
.prmry_aclk (1'b0),
.prmry_rst_n (1'b1 ),
.prmry_in (tx_fsm_resetdone_i),
.prmry_vect_in ('d0 ),
.scndry_aclk (INIT_CLK ),
.scndry_rst_n (1'b1 ),
.prmry_ack ( ),
.scndry_out (tx_fsm_resetdone_ii),
.scndry_vect_out ( )
);
//Clocking onto the INIT-clock.
aurora_64b66b_25p4G_cdc_sync
# (
.c_cdc_type (1), // 0 Pulse synchronizer, 1 level synchronizer 2 level synchronizer with ACK
.c_flop_input (0), // 1 Adds one flop stage to the input prmry_in signal
.c_reset_state (0), // 1 Reset needed for sync flops
.c_single_bit (1), // 1 single bit input.
.c_mtbf_stages (5) // Number of sync stages needed
) u_cdc_rx_fsm_resetdone_i
(
.prmry_aclk (1'b0),
.prmry_rst_n (1'b1 ),
.prmry_in (rx_fsm_resetdone_i),
.prmry_vect_in ('d0 ),
.scndry_aclk (INIT_CLK ),
.scndry_rst_n (1'b1 ),
.prmry_ack ( ),
.scndry_out (rx_fsm_resetdone_ii),
.scndry_vect_out ( )
);
assign mmcm_reset_i = tx_fsm_resetdone_ii & rx_fsm_resetdone_ii;
wire fabric_pcs_reset;
assign txusrclk_gtx_reset_comb = fabric_pcs_reset;
//------------------------------------------------------------------------------
//*************************************************************************************************
//-----------------------------------GTX INSTANCE-----------------------------------------------
//*************************************************************************************************
aurora_64b66b_25p4G_MULTI_GT aurora_64b66b_25p4G_multi_gt_i
(
//---------------------------------------------------------------------
//gtwix reset module interface ports starts
//---------------------------------------------------------------------
.gtwiz_reset_all_in (GTXRESET_IN),
.gtwiz_reset_clk_freerun_in (INIT_CLK ),
.gtwiz_reset_tx_pll_and_datapath_in (1'b0),
.gtwiz_reset_tx_datapath_in (1'b0),
.gtwiz_reset_rx_pll_and_datapath_in (GTXRESET_IN),
.gtwiz_reset_rx_datapath_in (rxfsm_reset_i),
.gtwiz_reset_rx_data_good_in (1'b1),
.gtwiz_reset_rx_cdr_stable_out (),
.gtwiz_reset_tx_done_out (tx_fsm_resetdone_i),
.gtwiz_reset_rx_done_out (rx_fsm_resetdone_i),
.gtwiz_reset_qpll0reset_output (qpllreset_i),//(?? gt common is in GT at the moment ),
//---------------------------------------------------------------------
//gtwix reset module interface ports ends
//---------------------------------------------------------------------
.fabric_pcs_reset (fabric_pcs_reset ),
.bufg_gt_clr_out (bufg_gt_clr_out ),// connect to clk_locked of clock module
.gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out ),// connect to mmcm not locked of clock module
.userclk_rx_active_out (gtx_rx_pcsreset_comb ),
//---------------------------------------------------------------------
// connection of GT comman and GT channel clk and refclk starts
//---------------------------------------------------------------------
// when no . of channels are less than or equal to 4
// connect the qpllclk and ref clk from GT common to GT channel
//.gtrefclk00_in (gt_qpllclk_quad1_in),//(gtrefclk00_in[0]),
.gt0_qpll0clk_in (gt_qpllclk_quad1_in ),
.gt0_qpll0refclk_in (gt_qpllrefclk_quad1_in),
.gt0_gtwiz_reset_qpll0lock_in (gt_qplllock_quad1_i ),
//---------------------------------------------------------------------
// connection of GT comman and GT channel clk and refclk ends
//---------------------------------------------------------------------
.gt0_gtrefclk0_in (REFCLK1_IN),// connect to same as GT common ref clock
// GT reference clock per channel, connect to REF clk - same as for GT Common
//, only one gt ref clk is needed
//.gt0_gtrefclk1_in (REFCLK1_IN),// connect to same as GT common ref clock
//-------------------------- Channel - DRP Ports --------------------------
.gt0_drpaddr (gt0_drpaddr),
.gt0_drp_clk_in (INIT_CLK),
.gt0_drpdi (gt0_drpdi),
.gt0_drpdo (gt0_drpdo),
.gt0_drpen (gt0_drpen),
.gt0_drprdy (gt0_drprdy),
.gt0_drpwe (gt0_drpwe),
//----------------------------- Loopback Ports -----------------------------
//------------------- RX Initialization and Reset Ports --------------------
.gt0_rxusrclk_out (rxusrclk_out), //(rxrecclk_to_fabric_i),
.gt0_rxusrclk2_out (),//(keep it open --> rxusrclk2_out),//(rxrecclk_to_fabric_i),
//---------------- Transmit Ports - FPGA TX Interface Ports ----------------
.gt0_txusrclk_in (TXUSRCLK_IN),
.gt0_txusrclk2_in (TXUSRCLK2_IN),
//----------------------------- Loopback Ports -----------------------------
.gt_loopback ({1{LOOPBACK_IN}}),
//.gt0_rxuserrdy_in (rxuserrdy_t),
.gt_rxpolarity (sync_rx_polarity_r_j),
.gt0_rxdata_out (pre_rxdata_from_gtx_i),
//---------------------- Receive Ports - RX AFE Ports ----------------------
.gt0_gthrxn_in (RX1N_IN),
.gt0_gthrxp_in (RX1P_IN),
//------------- Receive Ports - RX Fabric Output Control Ports -------------
.gt0_rxoutclk_out (rxrecclk_from_gtx_i),
//-------------------- Receive Ports - RX Gearbox Ports --------------------
.gt0_rxdatavalid_out (pre_rxdatavalid_i),
.gt0_rxheader_out (pre_rxheader_from_gtx_i),
.gt0_rxheadervalid_out (pre_rxheadervalid_i),
//------------------- Receive Ports - RX Gearbox Ports --------------------
.gt0_rxgearboxslip_in (rxgearboxslip_i),
//----------- Receive Ports - RX Initialization and Reset Ports ------------
.gt_gtrxreset ({1{GTXRESET_IN}}),
//------------ Receive Ports -RX Initialization and Reset Ports ------------
.gt_rxresetdone (rx_resetdone_j),
//------------------- TX Initialization and Reset Ports --------------------
.gt_gttxreset ({1{GTXRESET_IN}}),
//.gt0_txuserrdy_in (txuserrdy_t),//
//------------ Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
.gt0_txheader_in (txheader_r),
//---------------- Transmit Ports - TX Data Path interface -----------------
.gt0_txdata_in (scrambled_data_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.gt0_gthtxn_out (TX1N_OUT),
.gt0_gthtxp_out (TX1P_OUT),
//--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
.gt0_txoutclk_out (TXOUTCLK1_OUT),
.gt0_txoutclkfabric_out (),
.gt0_txoutclkpcs_out (),
//------------------- Transmit Ports - TX Gearbox Ports --------------------
.gt0_txsequence_in (txseq_counter_i),
//----------------------- Receive Ports - CDR Ports ------------------------
.gt0_rxcdrovrden_in (GT_RXCDROVRDEN_IN),
// transceiver port list is not enabled. below ports are at their default.
.gt_rxbufstatus (),
.gt_rxpmareset (tied_to_ground_vec_i[0:0]),
.gt_rxrate (tied_to_ground_vec_i[2 :0]),
.gt_txpmareset (tied_to_ground_vec_i[0:0]),
.gt_txpcsreset (tied_to_ground_vec_i[0:0]),
.gt_rxpcsreset (tied_to_ground_vec_i[0:0]), //MAS
.gt_rxbufreset (tied_to_ground_vec_i[0:0]),
.gt_rxpmaresetdone (),
.gt_txprbssel (tied_to_ground_vec_i[3 :0]),
.gt_rxprbssel (tied_to_ground_vec_i[3 :0]),
.gt_txprbsforceerr (tied_to_ground_vec_i[0:0]),
.gt_rxprbserr (),
.gt_rxprbscntreset (tied_to_ground_vec_i[0:0]),
.gt_dmonitorout (),
.gt_txbufstatus (),
//------------------------ RX Margin Analysis Ports ------------------------
.gt_eyescandataerror (),
.gt_eyescanreset (tied_to_ground_vec_i[0:0]),
.gt_eyescantrigger (tied_to_ground_vec_i[0:0]),
//------------------- Receive Ports - RX Equalizer Ports -------------------
.gt_rxcdrhold (tied_to_ground_vec_i[0:0]),
.gt_rxdfelpmreset (tied_to_ground_vec_i[0:0]),
.gt_rxlpmen (tied_to_ground_vec_i[0:0]),
//---------------------- TX Configurable Driver Ports ----------------------
.gt_txpostcursor (tied_to_ground_vec_i[4 :0]),
.gt_txdiffctrl ({1{4'b1000}}),
.gt_txprecursor (tied_to_ground_vec_i[4 :0]),
//--------------- Transmit Ports - TX Polarity Control Ports ---------------
.gt_txpolarity (tied_to_ground_vec_i[0:0]),
.gt_txinhibit (tied_to_ground_vec_i[0:0]),
.gt_pcsrsvdin (tied_to_ground_vec_i[15:0]),
//----------- GT POWERGOOD STATUS Port -----------
.gt_powergood (gt_powergood),
//----------- Transmit Ports - TX Initialization and Reset Ports -----------
.gt_txresetdone (tx_resetdone_j)
);
always @(posedge rxusrclk_out)//always @(posedge rxrecclk_to_fabric_i)//
begin
pre_r1_rxdata_from_gtx_i <= `DLY pre_rxdata_from_gtx_i ;
pre_r1_rxdatavalid_i <= `DLY pre_rxdatavalid_i ;
end
always @(posedge rxusrclk_out)//always @(posedge rxrecclk_to_fabric_i)//
begin
if(pre_r1_rxdatavalid_i)
begin
pos_rxdata_from_gtx_i <= `DLY pre_r1_rxdata_from_gtx_i;
pos_rxdatavalid_i <= `DLY 1'b1;
end
else
begin
pos_rxdatavalid_i <= `DLY 1'b0;
end
end
always @(posedge rxusrclk_out)//always @(posedge rxrecclk_to_fabric_i)//
begin
pre_r1_rxheader_from_gtx_i <= `DLY pre_rxheader_from_gtx_i ;
pre_r1_rxheadervalid_i <= `DLY pre_rxheadervalid_i ;
end
always @(posedge rxusrclk_out)//always @(posedge rxrecclk_to_fabric_i)//
begin
if(pre_r1_rxheadervalid_i)
begin
pos_rxheader_from_gtx_i <= `DLY pre_r1_rxheader_from_gtx_i;
pos_rxheadervalid_i <= `DLY 1'b1;
end
else
begin
pos_rxheadervalid_i <= `DLY 1'b0;
end
end
//---- Final stage of posedge flop -----
always @(posedge rxusrclk_out)//always @(posedge rxrecclk_to_fabric_i)//
begin
rxdata_from_gtx_i <= `DLY pos_rxdata_from_gtx_i;
rxdatavalid_i <= `DLY pos_rxdatavalid_i;
rxheader_from_gtx_i <= `DLY pos_rxheader_from_gtx_i;
rxheadervalid_i <= `DLY pos_rxheadervalid_i;
end
// Common_reset_cbcc module to generate & control reset for CBCC module
// This will drive reset to all CBCC instances used in the core
assign enchansync_all_i = ENCHANSYNC_IN;
aurora_64b66b_25p4G_common_reset_cbcc common_reset_cbcc_i
(
.enchansync ( enchansync_all_i ),
.chan_bond_reset ( CHAN_BOND_RESET ),
.cb_bit_err ( cb_bit_err_i ),
.reset ( new_gtx_rx_pcsreset_comb ),
.rd_clk ( RXUSRCLK2_IN ),
.init_clk ( INIT_CLK ),
.user_clk ( rxusrclk_out ),//( rxrecclk_to_fabric_i ),
.cbcc_fifo_reset_wr_clk ( cbcc_fifo_reset_wr_clk ),
.cbcc_fifo_reset_to_fifo_wr_clk ( cbcc_fifo_reset_to_fifo_wr_clk ),
.cbcc_data_srst ( cbcc_data_srst ),
.cbcc_fifo_reset_rd_clk ( cbcc_fifo_reset_rd_clk ),
.cbcc_fifo_reset_to_fifo_rd_clk ( cbcc_fifo_reset_to_fifo_rd_clk ),
.cbcc_only_reset_rd_clk ( cbcc_only_reset_rd_clk ),
.cbcc_reset_cbstg2_rd_clk ( cbcc_reset_cbstg2_rd_clk )
);
aurora_64b66b_25p4G_common_logic_cbcc #
(
.BACKWARD_COMP_MODE1(BACKWARD_COMP_MODE1)
)common_logic_cbcc_i
(
.start_cb_writes_in ( start_cb_writes_i ),
.do_rd_en_in ( do_rd_en_i ),
.bit_err_chan_bond_in ( bit_err_chan_bond_i ),
.final_gater_for_fifo_din_in ( final_gater_for_fifo_din_i ),
.any_vld_btf_in ( any_vld_btf_i ),
.all_start_cb_writes_out ( all_start_cb_writes_i ),
.cbcc_fifo_reset_wr_clk ( cbcc_fifo_reset_wr_clk ),
.cbcc_fifo_reset_rd_clk ( cbcc_fifo_reset_rd_clk ),
.master_do_rd_en_out ( master_do_rd_en_i ),
.cb_bit_err_out ( cb_bit_err_i ),
.all_vld_btf_out ( all_vld_btf_flag_i ),
.rxusrclk2_in ( RXUSRCLK2_IN ),
.rxrecclk_to_fabric ( rxusrclk_out )////( rxrecclk_to_fabric_i )
);
//#########################scrambler instantiation########################
reg [63:0] TXDATA_IN_REG;
always @ (posedge TXUSRCLK2_IN)
begin
TXDATA_IN_REG <= `DLY TXDATA_IN;
txheader_r <= `DLY tx_hdr_r;
end
aurora_64b66b_25p4G_SCRAMBLER_64B66B #
(
.SCRAMBLER_SEED(SCRAMBLER_SEED),
.TX_DATA_WIDTH(64)
)
scrambler_64b66b_gtx0_i
(
// User Interface
.UNSCRAMBLED_DATA_IN (TXDATA_IN_REG),
.SCRAMBLED_DATA_OUT (scrambled_data_i),
.DATA_VALID_IN (data_valid_i),
// System Interface
.USER_CLK (TXUSRCLK2_IN), // (TXUSRCLK2_IN),
.SYSTEM_RESET (gtx_reset_comb)
);
//---------------------------Polarity Control Logic---------------------
//Double synchronize CHECK_POLARITY_IN signal to account for domain crossing
aurora_64b66b_25p4G_cdc_sync
# (
.c_cdc_type (1), // 0 Pulse synchronizer, 1 level synchronizer 2 level synchronizer with ACK
.c_flop_input (0), // 1 Adds one flop stage to the input prmry_in signal
.c_reset_state (0), // 1 Reset needed for sync flops
.c_single_bit (1), // 1 single bit input.
.c_mtbf_stages (2) // Number of sync stages needed
) u_cdc__check_polarity
(
.prmry_aclk (1'b0 ),
.prmry_rst_n (1'b1 ),
.prmry_in (CHECK_POLARITY_IN),
.prmry_vect_in ('d0 ),
.scndry_aclk (rxusrclk_out ),//(rxrecclk_to_fabric_i ),
.scndry_rst_n (1'b1 ),
.prmry_ack (),
.scndry_out (check_polarity_r2),
.scndry_vect_out ()
);
//Logic to account for polarity reversal
always @(posedge rxusrclk_out)//always @(posedge rxrecclk_to_fabric_i)//
begin
if(check_polarity_r2 && (rxheader_from_gtx_i == 2'b01) && rxheadervalid_i)
RX_NEG_OUT <= `DLY 1'b1;
else if(check_polarity_r2 && RX_NEG_OUT )
RX_NEG_OUT <= `DLY 1'b1;
else
RX_NEG_OUT <= `DLY 1'b0;
end
//Finally double synchronize RX_POLARITY_IN signal and port map to RXPOLARITY0/1
aurora_64b66b_25p4G_cdc_sync
# (
.c_cdc_type (1), // 0 Pulse synchronizer, 1 level synchronizer 2 level synchronizer with ACK
.c_flop_input (0), // 1 Adds one flop stage to the input prmry_in signal
.c_reset_state (0), // 1 Reset needed for sync flops
.c_single_bit (1), // 1 single bit input.
.c_mtbf_stages (3) // Number of sync stages needed
) u_cdc_rxpolarity_
(
.prmry_aclk (RXUSRCLK2_IN ),//?? what about this clock and logic for cdc_sync
.prmry_rst_n (1'b1 ),
.prmry_in (RXPOLARITY_IN),
.prmry_vect_in ('d0 ),
.scndry_aclk (rxusrclk_out ),//(rxrecclk_to_fabric_i ),//
.scndry_rst_n (1'b1 ),
.prmry_ack (),
.scndry_out (sync_rx_polarity_r ),
.scndry_vect_out ()
);
always @(posedge rxusrclk_out)//always @(posedge rxrecclk_to_fabric_i)//
begin
rxdatavalid_to_fifo_i <= `DLY rxdatavalid_i;
rxheader_to_fifo_i <= `DLY rxheader_from_gtx_i;
end
//##########################descrambler instantiation########################
aurora_64b66b_25p4G_DESCRAMBLER_64B66B #
(
.SCRAMBLER_SEED(SCRAMBLER_SEED),
.RX_DATA_WIDTH(64)
)
descrambler_64b66b_gtx0_i
(
// User Interface
.SCRAMBLED_DATA_IN (rxdata_from_gtx_i ),
.UNSCRAMBLED_DATA_OUT (rxdata_to_fifo_i ),
.DATA_VALID_IN (rxdatavalid_i ),
// System Interface
.USER_CLK (rxusrclk_out ),//(rxrecclk_to_fabric_i),//
//.ENABLE (enable_32_i ),
.SYSTEM_RESET (!rxlossofsync_out_q )
);
//#########################block sync instantiation##############################
aurora_64b66b_25p4G_BLOCK_SYNC_SM #
(
.SH_CNT_MAX (SH_CNT_MAX ),
.SH_INVALID_CNT_MAX (SH_INVALID_CNT_MAX )
)
block_sync_sm_gtx0_i
(
// User Interface
.BLOCKSYNC_OUT (blocksync_out_i ),
.RXGEARBOXSLIP_OUT (rxgearboxslip_i ),
.RXHEADER_IN (rxheader_from_gtx_i),
.RXHEADERVALID_IN (rxheadervalid_i ),
// System Interface
.USER_CLK (rxusrclk_out ),//(rxrecclk_to_fabric_i),//
.SYSTEM_RESET (new_gtx_rx_pcsreset_comb )
);
//#########################CBCC module instantiation########################
aurora_64b66b_25p4G_CLOCK_CORRECTION_CHANNEL_BONDING #
(
.INTER_CB_GAP (INTER_CB_GAP ),
.EXAMPLE_SIMULATION (EXAMPLE_SIMULATION ),
.wait_for_fifo_wr_rst_busy_value (wait_for_fifo_wr_rst_busy_value),
.LOW_WATER_MARK (LOW_WATER_MARK_MASTER ),
.HIGH_WATER_MARK (HIGH_WATER_MARK_MASTER ),
.BACKWARD_COMP_MODE3 (BACKWARD_COMP_MODE3),
.CH_BOND_MAX_SKEW (2'b10),
.CH_BOND_MODE (CHAN_BOND_MODE_0 )
)
cbcc_gtx0_i
(
//Write Interface
.GTX_RX_DATA_IN (rxdata_to_fifo_i ),
.GTX_RX_DATAVALID_IN (rxdatavalid_to_fifo_i),
.GTX_RX_HEADER_IN (rxheader_to_fifo_i ),
.WR_ENABLE (enable_32_i ),
.USER_CLK (rxusrclk_out),//(rxrecclk_to_fabric_i),//
.RXLOSSOFSYNC_IN (rxlossofsync_out_q ),
.ENCHANSYNC (ENCHANSYNC_IN ),
.CHAN_BOND_RESET (CHAN_BOND_RESET ),
//Read Interface
.CC_RX_DATA_OUT(RXDATA_OUT),
.CC_RX_BUF_STATUS_OUT (rxbuferr_out_i ),
.CC_RX_DATAVALID_OUT (RXDATAVALID_OUT ),
.CC_RX_HEADER_OUT (RXHEADER_OUT ),
.CC_RX_HEADER_OUT_ERR (RXHEADER_OUT_ERR ),
.CC_RXLOSSOFSYNC_OUT (RXLOSSOFSYNC_OUT ),
.CHBONDI (chbondi),
.CHBONDO (chbondo_to_slaves_i),
.RXCHANISALIGNED (CHBONDDONE_OUT ),
.CBCC_FIFO_RESET_WR_CLK (cbcc_fifo_reset_wr_clk ),
.CBCC_FIFO_RESET_TO_FIFO_WR_CLK( cbcc_fifo_reset_to_fifo_wr_clk ),
.cbcc_data_srst ( cbcc_data_srst ),
.CBCC_FIFO_RESET_RD_CLK (cbcc_fifo_reset_rd_clk ),
.CBCC_FIFO_RESET_TO_FIFO_RD_CLK(cbcc_fifo_reset_to_fifo_rd_clk ),
.CBCC_ONLY_RESET_RD_CLK (cbcc_only_reset_rd_clk ),
.CBCC_RESET_CBSTG2_RD_CLK (cbcc_reset_cbstg2_rd_clk ),
.ANY_VLD_BTF_FLAG (any_vld_btf_i ),
.START_CB_WRITES_OUT (start_cb_writes_i ),
.ALL_START_CB_WRITES_IN (all_start_cb_writes_i ),
.ALL_VLD_BTF_FLAG_IN (all_vld_btf_flag_i ),
.PERLN_DO_RD_EN (do_rd_en_i ),
.MASTER_DO_RD_EN (master_do_rd_en_i ),
.FIRST_CB_BITERR_CB_RESET_OUT (bit_err_chan_bond_i ),
.FINAL_GATER_FOR_FIFO_DIN (final_gater_for_fifo_din_i ),
.RESET (new_gtx_rx_pcsreset_comb ),
.RD_CLK (RXUSRCLK2_IN ),
.HPCNT_RESET_IN (stableclk_gtx_reset_comb),//
.GTXRESET_IN (GTXRESET_IN ),
.INIT_CLK (INIT_CLK ),
.LINK_RESET (link_reset_0_c )
);
wire reset_initclk;
aurora_64b66b_25p4G_rst_sync u_rst_sync_reset_initclk
(
.prmry_in (RESET),
.scndry_aclk (INIT_CLK),
.scndry_out (reset_initclk)
);
assign rxfsm_reset_i = hpreset_or_pma_init_in | cdr_reset_fsm_lnkreset;
assign sys_and_fsm_reset_for_hpcnt = rxfsm_reset_i ? 1'b0 : (reset_initclk | ~FSM_RESETDONE);
assign hp_reset_i = hpreset_in | cdr_reset_fsm_lnkreset;
assign HPCNT_RESET_IN = GTXRESET_IN | sys_and_fsm_reset_for_hpcnt | cdr_reset_fsm_lnkreset ;
assign blocksync_all_lanes_inrxclk = blocksync_out_i ;
assign rxlossofsync_out_i = allow_block_sync_propagation_inrxclk ? blocksync_out_i : 1'b0;
always @(posedge rxusrclk_out)//always @(posedge rxrecclk_to_fabric_i)//
begin
rxlossofsync_out_q <= `DLY rxlossofsync_out_i;
end
always @(posedge rxusrclk_out)//always @(posedge rxrecclk_to_fabric_i)//
begin
blocksync_all_lanes_inrxclk_q <= `DLY blocksync_all_lanes_inrxclk;
end
aurora_64b66b_25p4G_rst_sync u_rst_sync_blocksyncall_initclk_sync
(
.prmry_in (blocksync_all_lanes_inrxclk_q),
.scndry_aclk (INIT_CLK),
.scndry_out (blocksync_all_lanes_instableclk)
);
aurora_64b66b_25p4G_rst_sync u_rst_sync_blocksyncprop_inrxclk_sync
(
.prmry_in (allow_block_sync_propagation),
.scndry_aclk (rxusrclk_out),//(rxrecclk_to_fabric_i),//
.scndry_out (allow_block_sync_propagation_inrxclk)
);
always @(posedge INIT_CLK) begin
if(hpreset_or_pma_init_in | BACKWARD_COMP_MODE2) begin
cdr_reset_fsm_r <= IDLE;
cdr_reset_fsm_cntr_r <= 8'h0;
cdr_reset_fsm_lnkreset <= 1'b0;
allow_block_sync_propagation <= BACKWARD_COMP_MODE2;
end else begin
case(cdr_reset_fsm_r)
IDLE: begin
cdr_reset_fsm_cntr_r <= 8'h0;
allow_block_sync_propagation <= 1'b0;
cdr_reset_fsm_lnkreset <= 1'b0;
if(blocksync_all_lanes_instableclk) begin
cdr_reset_fsm_r <= ASSERT_RXRESET;
end
end
ASSERT_RXRESET: begin
allow_block_sync_propagation <= 1'b0;
cdr_reset_fsm_lnkreset <= 1'b1;
if(cdr_reset_fsm_cntr_r == 8'hFF) begin
cdr_reset_fsm_r <= DONE;
end else begin
cdr_reset_fsm_cntr_r <= cdr_reset_fsm_cntr_r + 8'h1;
end
end
DONE: begin
cdr_reset_fsm_cntr_r <= 8'h0;
cdr_reset_fsm_r <= DONE;
cdr_reset_fsm_lnkreset <= 1'b0;
allow_block_sync_propagation <= 1'b1;
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:36:03 09/06/2013
// Design Name:
// Module Name: counter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module counter(div_clk,rst,time_value,contando, terminado);
input div_clk;
input rst;
input contando;
input [3:0] time_value;
output reg terminado;
reg [3:0] contador;
always @(posedge div_clk or posedge rst)
begin
if(rst)
begin
contador <= 0;
terminado <= 0;
end
else
if(contando)
begin
if(contador == time_value)
begin
contador <= 0;
terminado <= 1;
end
else
begin
terminado <= 0;
contador <= contador + 1;
end
end
else
terminado <= 0;
end
endmodule
|
module Keyboard_dev(clk, reset, kbd_clk, kbd_data, Keyboard_Data, ready_pulse);
input clk;
input reset;
input kbd_clk;
input kbd_data;
output reg ready_pulse;
output reg [7: 0] Keyboard_Data;
//
// reg [3: 0] cnt, last;
// reg useless;
//
// initial begin
// cnt = 0;
// ready_pulse = 0;
// Keyboard_Data = 0;
// end
//
// always @(negedge kbd_clk) begin
// if (cnt == 10) cnt <= 0;
// else cnt <= cnt + 1;
// case(cnt)
// 0: useless <= 1;
// 9: useless <= 1;
// 10: useless <= 1;
// default: begin
// Keyboard_Data[cnt - 1] <= kbd_data;
// end
// endcase
// end
//
// always @(posedge clk) begin
// last <= cnt;
// ready_pulse <= (last != 10) && (cnt == 10);
// end
reg [3:0] counter;
reg [3:0] last;
initial begin
Keyboard_Data <= 8'b0;
ready_pulse <= 1'b0;
counter <= 4'b0;
last <= 4'b0;
end
always @ (negedge kbd_clk) begin
case (counter)
0: begin
counter <= counter + 1;
end
1: begin
counter <= counter + 1;
Keyboard_Data[0] <= kbd_data;
end
2: begin
counter <= counter + 1;
Keyboard_Data[1] <= kbd_data;
end
3: begin
counter <= counter + 1;
Keyboard_Data[2] <= kbd_data;
end
4: begin
counter <= counter + 1;
Keyboard_Data[3] <= kbd_data;
end
5: begin
counter <= counter + 1;
Keyboard_Data[4] <= kbd_data;
end
6: begin
counter <= counter + 1;
Keyboard_Data[5] <= kbd_data;
end
7: begin
counter <= counter + 1;
Keyboard_Data[6] <= kbd_data;
end
8: begin
counter <= counter + 1;
Keyboard_Data[7] <= kbd_data;
end
9: begin
counter <= counter + 1;
end
10: begin
counter <= 4'b0;
end
endcase
end
always @(posedge clk) begin
ready_pulse <= (last != 4'd10 && counter == 4'd10);
last <= counter;
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// All of the general DFF and Latch modules
//
// ====================================================================
//
//
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 1
//
// ===========================================================================
module sirv_gnrl_dfflrs # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFLRS_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b1}};
else if (lden == 1'b1)
qout_r <= #1 dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable and Reset
// Default reset value is 0
//
// ===========================================================================
module sirv_gnrl_dfflr # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFLR_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b0}};
else if (lden == 1'b1)
qout_r <= #1 dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Load-enable, no reset
//
// ===========================================================================
module sirv_gnrl_dffl # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk
);
reg [DW-1:0] qout_r;
always @(posedge clk)
begin : DFFL_PROC
if (lden == 1'b1)
qout_r <= #1 dnxt;
end
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
sirv_gnrl_xchecker # (
.DW(1)
) sirv_gnrl_xchecker(
.i_dat(lden),
.clk (clk)
);
//synopsys translate_on
`endif//}
`endif//}
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 1
//
// ===========================================================================
module sirv_gnrl_dffrs # (
parameter DW = 32
) (
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFRS_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b1}};
else
qout_r <= #1 dnxt;
end
assign qout = qout_r;
endmodule
// ===========================================================================
//
// Description:
// Verilog module sirv_gnrl DFF with Reset, no load-enable
// Default reset value is 0
//
// ===========================================================================
module sirv_gnrl_dffr # (
parameter DW = 32
) (
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFR_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b0}};
else
qout_r <= #1 dnxt;
end
assign qout = qout_r;
endmodule
// ===========================================================================
//
// Description:
// Verilog module for general latch
//
// ===========================================================================
module sirv_gnrl_ltch # (
parameter DW = 32
) (
//input test_mode,
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout
);
reg [DW-1:0] qout_r;
always @ *
begin : LTCH_PROC
if (lden == 1'b1)
qout_r <= dnxt;
end
//assign qout = test_mode ? dnxt : qout_r;
assign qout = qout_r;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
always_comb
begin
CHECK_THE_X_VALUE:
assert (lden !== 1'bx)
else $fatal ("\n Error: Oops, detected a X value!!! This should never happen. \n");
end
//synopsys translate_on
`endif//}
`endif//}
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_M_V
`define SKY130_FD_SC_LP__NOR4_M_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4_m (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor4_m (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_M_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSTP_4_V
`define SKY130_FD_SC_HD__DFSTP_4_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfstp_4 (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfstp_4 (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSTP_4_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: iobdg_jbus_mondo_buf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: iobdg_jbus_int_in
// Description: This block assembles interrupts that
// come from the JBUS.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module iobdg_jbus_mondo_buf (/*AUTOARG*/
// Outputs
mondo_vld, mondo_data0, mondo_data1, mondo_target, mondo_source,
// Inputs
rst_l, clk, jbi_iob_vld, jbi_iob_data, rd_mondo_buf
);
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
// Global interface
input rst_l;
input clk;
// JBI interface
input jbi_iob_vld;
input [`JBI_IOB_MONDO_BUS_WIDTH-1:0] jbi_iob_data;
// Local interface
output mondo_vld;
output [63:0] mondo_data0;
output [63:0] mondo_data1;
output [`JBI_IOB_MONDO_TRG_WIDTH-1:0] mondo_target;
output [`JBI_IOB_MONDO_SRC_WIDTH-1:0] mondo_source;
input rd_mondo_buf;
// Internal signals
wire [`JBI_IOB_MONDO_BUS_CYCLE-1:0] vldreg_next;
wire [`JBI_IOB_MONDO_BUS_CYCLE-1:0] vldreg;
wire [`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE-1:0] datareg_next;
wire [`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE-1:0] datareg;
wire shift_en;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
/************************************************************
* Shift register
************************************************************/
assign vldreg_next = {vldreg[`JBI_IOB_MONDO_BUS_CYCLE-2:0],jbi_iob_vld};
dffrle_ns #(`JBI_IOB_MONDO_BUS_CYCLE) vldreg_ff (.din(vldreg_next),
.rst_l(rst_l),
.en(shift_en),
.clk(clk),
.q(vldreg));
assign datareg_next = {datareg[`JBI_IOB_MONDO_BUS_WIDTH*(`JBI_IOB_MONDO_BUS_CYCLE-1)-1:0],
jbi_iob_data};
dffrle_ns #(`JBI_IOB_MONDO_BUS_WIDTH*`JBI_IOB_MONDO_BUS_CYCLE) datareg_ff (.din(datareg_next),
.en(shift_en),
.clk(clk),
.rst_l(rst_l),
.q(datareg));
assign shift_en = ~&vldreg | rd_mondo_buf;
/************************************************************
* Local interface
************************************************************/
assign mondo_vld = &vldreg;
assign mondo_target = datareg[`JBI_IOB_MONDO_TRG_HI+128:`JBI_IOB_MONDO_TRG_LO+128];
assign mondo_source = datareg[`JBI_IOB_MONDO_SRC_HI+128:`JBI_IOB_MONDO_SRC_LO+128];
assign mondo_data0 = datareg[127:64];
assign mondo_data1 = datareg[63:0];
endmodule // iobdg_jbus_mondo_buf
|
module rgb2hsv (
input clk,
input res,
input read,
input [15:0] data,
output [4:0] saturation,
output [4:0] value,
output [8:0] hue,
output reg hue_invalid,
output reg done
);
parameter DIVLATENCY = 4'h8;
parameter FETCH = 3'h0,
COMPARE = 3'h1,
DIVSET = 3'h2,
DIVIDE = 3'h3,
HUE = 3'h4;
wire [4:0] r;
wire [4:0] g;
wire [4:0] b;
reg [4:0] rbuf;
reg [4:0] gbuf;
reg [4:0] bbuf;
reg [10:0] huediff;
reg [2:0] multiwait;
reg [4:0] min;
reg [4:0] max;
reg [2:0] state;
reg signed [10:0] numer;
assign {r, g, b} = data [14:0];
reg [2:0] colorcomp;
reg [8:0] colordomain;
assign hue = colordomain;
parameter RED = 3'h1;
parameter BLUE = 3'h2;
parameter GREEN = 3'h4;
parameter WHITE = 3'h0;
function [3:0] maxsel;
input [3:0] colorcomp;
begin
casex (colorcomp)
4'b1x0: maxsel = RED;
4'bx01: maxsel = BLUE;
4'b01x: maxsel = GREEN;
default: maxsel = WHITE;
endcase
end
endfunction
function [3:0] minsel;
input [3:0] colorcomp;
begin
casex (colorcomp)
4'b0x1: minsel = RED;
4'bx10: minsel = BLUE;
4'b10x: minsel = GREEN;
default: minsel = WHITE;
endcase
end
endfunction
reg [3:0] clkcount;
wire [16:0] huediff60;
wire [10:0] quot;
divider div0 (
.clock ( clkcount[3] ),
.denom ( saturation ),
.numer ( numer ),
.quotient ( quot ),
.remain ( rem )
);
multi ml0(
clk,
huediff,
huediff60);
assign value = max;
assign saturation = max - min;
reg [3:0] divwait;
always @(posedge clk)
begin
clkcount <= clkcount + 4'b1;
if(res) begin
rbuf <= 5'h00;
gbuf <= 5'h00;
bbuf <= 5'h00;
state <= FETCH;
end else begin
if (read && (state == FETCH)) begin
rbuf <= r;
gbuf <= g;
bbuf <= b;
done <= 0;
state <= COMPARE;
clkcount <= 0;
end else if (state == COMPARE) begin
colorcomp[2] <= (rbuf >= gbuf);
colorcomp[1] <= (gbuf >= bbuf);
colorcomp[0] <= (bbuf >= rbuf);
divwait <= 4'h0;
multiwait <= 3'b001;
state <= DIVSET;
end else if (state == DIVSET) begin
divwait <= 4'h0;
case (maxsel(colorcomp))
RED: max <= rbuf;
BLUE: max <= bbuf;
GREEN: max <= gbuf;
WHITE: max <= 5'h00;
endcase
case (minsel(colorcomp))
RED: begin
min <= rbuf;
numer <= (bbuf - gbuf) << 5;
state <= DIVIDE;
colordomain <= 9'd180;
hue_invalid <= 0;
end
BLUE: begin
min <= bbuf;
numer <= (gbuf - rbuf) << 5;
state <= DIVIDE;
colordomain <= 9'd60;
hue_invalid <= 0;
end
GREEN: begin
min <= gbuf;
numer <= (rbuf - bbuf) << 5;
state <= DIVIDE;
colordomain <= 9'd300;
hue_invalid <= 0;
end
WHITE: begin
min <= 5'h00;
hue_invalid <= 1;
done <= 1;
state <= FETCH;
end
endcase
end else if (state == DIVIDE) begin
if (divwait == DIVLATENCY) begin
huediff <= quot[10:0];
state <= HUE;
end else begin
divwait <= divwait + 4'h1;
end
end else if (state == HUE) begin
if (multiwait[2] == 1'd1) begin
colordomain <= (huediff60[13:5] + colordomain);
done <= 1'b1;
state <= FETCH;
end else begin
multiwait <= multiwait << 1;
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31A_SYMBOL_V
`define SKY130_FD_SC_LP__O31A_SYMBOL_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o31a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31A_SYMBOL_V
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1_____7.143______0.000______50.0______244.806____114.212
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module clk_wiz_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_clk_wiz_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkout1_unused;
wire clkout2_unused;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
PLLE2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (8),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (112),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (10.0))
plle2_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_wiz_0),
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT1 (clkout1_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_0),
.CLKIN1 (clk_in1_clk_wiz_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Other control and status signals
.LOCKED (locked_int),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = reset;
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_wiz_0),
.I (clkfbout_clk_wiz_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_wiz_0));
endmodule
|
// -----------------------------------------------------------------------------
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Filename: pselect_f.v
//
// Description:
// (Note: At least as early as I.31, XST implements a carry-
// chain structure for most decoders when these are coded in
// inferrable VHLD. An example of such code can be seen
// below in the "INFERRED_GEN" Generate Statement.
//
// -> New code should not need to instantiate pselect-type
// components.
//
// -> Existing code can be ported to Virtex5 and later by
// replacing pselect instances by pselect_f instances.
// As long as the C_FAMILY parameter is not included
// in the Generic Map, an inferred implementation
// will result.
//
// -> If the designer wishes to force an explicit carry-
// chain implementation, pselect_f can be used with
// the C_FAMILY parameter set to the target
// Xilinx FPGA family.
// )
//
// Parameterizeable peripheral select (address decode).
// AValid qualifier comes in on Carry In at bottom
// of carry chain.
//
//
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of axi_lite_ipif.
//
// --axi_lite_ipif.v
// --slave_attachment.v
// --address_decoder.v
// --pselect_f.v
// --counter_f.v
//-----------------------------------------------------------------------------
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// reset signals: "rst", "rst_n"
// generics: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port "*_i"
// device pins: "*_pin"
// ports: - Names begin with Uppercase
// processes: "*_PROCESS"
// component instantiations: "<ENTITY_>I_<#|FUNC>
//-----------------------------------------------------------------------------
//---------------------------------------------------------------------------
// Entity section
//---------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Definition of Generics:
// C_AB -- number of address bits to decode
// C_AW -- width of address bus
// C_BAR -- base address of peripheral (peripheral select
// is asserted when the C_AB most significant
// address bits match the C_AB most significant
// C_BAR bits
// Definition of Ports:
// A -- address input
// AValid -- address qualifier
// CS -- peripheral select
//-----------------------------------------------------------------------------
module pselect_f (A, AValid, CS);
parameter C_AB = 9;
parameter C_AW = 32;
parameter [0:C_AW - 1] C_BAR = 'bz;
parameter C_FAMILY = "nofamily";
input[0:C_AW-1] A;
input AValid;
output CS;
wire CS;
parameter [0:C_AB-1]BAR = C_BAR[0:C_AB-1];
//----------------------------------------------------------------------------
// Build a behavioral decoder
//----------------------------------------------------------------------------
generate
if (C_AB > 0) begin : XST_WA
assign CS = (A[0:C_AB - 1] == BAR[0:C_AB - 1]) ? AValid : 1'b0 ;
end
endgenerate
generate
if (C_AB == 0) begin : PASS_ON_GEN
assign CS = AValid ;
end
endgenerate
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* MBus master layer wrapper for NON-power gating
*
* Update history:
*
* date: 11/08 '13
* modified content: Newly added
* modified by: Ye-sheng Kuo <[email protected]>
* --------------------------------------------------------------------------
* IMPORTANT:
* --------------------------------------------------------------------------
* */
`include "include/mbus_def.v"
module mbus_ctrl_layer_wrapper
(
input CLK_EXT,
input CLKIN,
input RESETn,
input DIN,
output CLKOUT,
output DOUT,
input [`ADDR_WIDTH-1:0] TX_ADDR,
input [`DATA_WIDTH-1:0] TX_DATA,
input TX_PEND,
input TX_REQ,
input TX_PRIORITY,
output TX_ACK,
output [`ADDR_WIDTH-1:0] RX_ADDR,
output [`DATA_WIDTH-1:0] RX_DATA,
output RX_REQ,
input RX_ACK,
output RX_BROADCAST,
output RX_FAIL,
output RX_PEND,
output TX_FAIL,
output TX_SUCC,
input TX_RESP_ACK
);
parameter ADDRESS = 20'haaaaa;
wire w_n0lc0_clk_out;
wire w_n0lc0;
mbus_ctrl_wrapper#(.ADDRESS(ADDRESS)) n0
(
.CLK_EXT (CLK_EXT),
.CLKIN (CLKIN),
.CLKOUT (w_n0lc0_clk_out),
.RESETn (RESETn),
.DIN (DIN),
.DOUT (w_n0lc0),
.TX_ADDR (TX_ADDR),
.TX_DATA (TX_DATA),
.TX_REQ (TX_REQ),
.TX_ACK (TX_ACK),
.TX_PEND (TX_PEND),
.TX_PRIORITY (TX_PRIORITY),
.RX_ADDR (RX_ADDR),
.RX_DATA (RX_DATA),
.RX_REQ (RX_REQ),
.RX_ACK (RX_ACK),
.RX_BROADCAST (RX_BROADCAST),
.RX_FAIL (RX_FAIL),
.RX_PEND (RX_PEND),
.TX_SUCC (TX_SUCC),
.TX_FAIL (TX_FAIL),
.TX_RESP_ACK (TX_RESP_ACK),
.THRESHOLD (20'h05fff)
);
mbus_wire_ctrl lc0
(
.RESETn(RESETn),
.DOUT_FROM_BUS(w_n0lc0),
.CLKOUT_FROM_BUS(w_n0lc0_clk_out),
.DOUT(DOUT),
.CLKOUT(CLKOUT)
);
endmodule // mbus_layer_wrapper
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Connection Matrix Slave Interface ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_conmax_slave_if.v,v 1.1 2008/05/07 22:43:23 daughtry Exp $
//
// $Date: 2008/05/07 22:43:23 $
// $Revision: 1.1 $
// $Author: daughtry $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: wb_conmax_slave_if.v,v $
// Revision 1.1 2008/05/07 22:43:23 daughtry
// Initial Demo RTL check-in
//
// Revision 1.2 2002/10/03 05:40:07 rudi
// Fixed a minor bug in parameter passing, updated headers and specification.
//
// Revision 1.1.1.1 2001/10/19 11:01:39 rudi
// WISHBONE CONMAX IP Core
//
//
//
//
//
`include "wb_conmax_defines.v"
module wb_conmax_slave_if(
clk_i, rst_i, conf,
// Slave interface
wb_data_i, wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o,
wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i,
// Master 0 Interface
m0_data_i, m0_data_o, m0_addr_i, m0_sel_i, m0_we_i, m0_cyc_i,
m0_stb_i, m0_ack_o, m0_err_o, m0_rty_o,
// Master 1 Interface
m1_data_i, m1_data_o, m1_addr_i, m1_sel_i, m1_we_i, m1_cyc_i,
m1_stb_i, m1_ack_o, m1_err_o, m1_rty_o,
// Master 2 Interface
m2_data_i, m2_data_o, m2_addr_i, m2_sel_i, m2_we_i, m2_cyc_i,
m2_stb_i, m2_ack_o, m2_err_o, m2_rty_o,
// Master 3 Interface
m3_data_i, m3_data_o, m3_addr_i, m3_sel_i, m3_we_i, m3_cyc_i,
m3_stb_i, m3_ack_o, m3_err_o, m3_rty_o,
// Master 4 Interface
m4_data_i, m4_data_o, m4_addr_i, m4_sel_i, m4_we_i, m4_cyc_i,
m4_stb_i, m4_ack_o, m4_err_o, m4_rty_o,
// Master 5 Interface
m5_data_i, m5_data_o, m5_addr_i, m5_sel_i, m5_we_i, m5_cyc_i,
m5_stb_i, m5_ack_o, m5_err_o, m5_rty_o,
// Master 6 Interface
m6_data_i, m6_data_o, m6_addr_i, m6_sel_i, m6_we_i, m6_cyc_i,
m6_stb_i, m6_ack_o, m6_err_o, m6_rty_o,
// Master 7 Interface
m7_data_i, m7_data_o, m7_addr_i, m7_sel_i, m7_we_i, m7_cyc_i,
m7_stb_i, m7_ack_o, m7_err_o, m7_rty_o
);
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
parameter [1:0] pri_sel = 2'd2;
parameter aw = 32; // Address bus Width
parameter dw = 32; // Data bus Width
parameter sw = dw / 8; // Number of Select Lines
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
input clk_i, rst_i;
input [15:0] conf;
// Slave Interface
input [dw-1:0] wb_data_i;
output [dw-1:0] wb_data_o;
output [aw-1:0] wb_addr_o;
output [sw-1:0] wb_sel_o;
output wb_we_o;
output wb_cyc_o;
output wb_stb_o;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
// Master 0 Interface
input [dw-1:0] m0_data_i;
output [dw-1:0] m0_data_o;
input [aw-1:0] m0_addr_i;
input [sw-1:0] m0_sel_i;
input m0_we_i;
input m0_cyc_i;
input m0_stb_i;
output m0_ack_o;
output m0_err_o;
output m0_rty_o;
// Master 1 Interface
input [dw-1:0] m1_data_i;
output [dw-1:0] m1_data_o;
input [aw-1:0] m1_addr_i;
input [sw-1:0] m1_sel_i;
input m1_we_i;
input m1_cyc_i;
input m1_stb_i;
output m1_ack_o;
output m1_err_o;
output m1_rty_o;
// Master 2 Interface
input [dw-1:0] m2_data_i;
output [dw-1:0] m2_data_o;
input [aw-1:0] m2_addr_i;
input [sw-1:0] m2_sel_i;
input m2_we_i;
input m2_cyc_i;
input m2_stb_i;
output m2_ack_o;
output m2_err_o;
output m2_rty_o;
// Master 3 Interface
input [dw-1:0] m3_data_i;
output [dw-1:0] m3_data_o;
input [aw-1:0] m3_addr_i;
input [sw-1:0] m3_sel_i;
input m3_we_i;
input m3_cyc_i;
input m3_stb_i;
output m3_ack_o;
output m3_err_o;
output m3_rty_o;
// Master 4 Interface
input [dw-1:0] m4_data_i;
output [dw-1:0] m4_data_o;
input [aw-1:0] m4_addr_i;
input [sw-1:0] m4_sel_i;
input m4_we_i;
input m4_cyc_i;
input m4_stb_i;
output m4_ack_o;
output m4_err_o;
output m4_rty_o;
// Master 5 Interface
input [dw-1:0] m5_data_i;
output [dw-1:0] m5_data_o;
input [aw-1:0] m5_addr_i;
input [sw-1:0] m5_sel_i;
input m5_we_i;
input m5_cyc_i;
input m5_stb_i;
output m5_ack_o;
output m5_err_o;
output m5_rty_o;
// Master 6 Interface
input [dw-1:0] m6_data_i;
output [dw-1:0] m6_data_o;
input [aw-1:0] m6_addr_i;
input [sw-1:0] m6_sel_i;
input m6_we_i;
input m6_cyc_i;
input m6_stb_i;
output m6_ack_o;
output m6_err_o;
output m6_rty_o;
// Master 7 Interface
input [dw-1:0] m7_data_i;
output [dw-1:0] m7_data_o;
input [aw-1:0] m7_addr_i;
input [sw-1:0] m7_sel_i;
input m7_we_i;
input m7_cyc_i;
input m7_stb_i;
output m7_ack_o;
output m7_err_o;
output m7_rty_o;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [aw-1:0] wb_addr_o;
reg [dw-1:0] wb_data_o;
reg [sw-1:0] wb_sel_o;
reg wb_we_o;
reg wb_cyc_o;
reg wb_stb_o;
wire [2:0] mast_sel_simple;
wire [2:0] mast_sel_pe;
wire [2:0] mast_sel;
reg next;
reg m0_cyc_r, m1_cyc_r, m2_cyc_r, m3_cyc_r;
reg m4_cyc_r, m5_cyc_r, m6_cyc_r, m7_cyc_r;
////////////////////////////////////////////////////////////////////
//
// Select logic
//
always @(posedge clk_i)
next <= #1 ~wb_cyc_o;
wb_conmax_arb arb(
.clk( clk_i ),
.rst( rst_i ),
.req( { m7_cyc_i,
m6_cyc_i,
m5_cyc_i,
m4_cyc_i,
m3_cyc_i,
m2_cyc_i,
m1_cyc_i,
m0_cyc_i } ),
.gnt( mast_sel_simple ),
.next( 1'b0 )
);
wb_conmax_msel #(pri_sel) msel(
.clk_i( clk_i ),
.rst_i( rst_i ),
.conf( conf ),
.req( { m7_cyc_i,
m6_cyc_i,
m5_cyc_i,
m4_cyc_i,
m3_cyc_i,
m2_cyc_i,
m1_cyc_i,
m0_cyc_i} ),
.sel( mast_sel_pe ),
.next( next )
);
assign mast_sel = (pri_sel == 2'd0) ? mast_sel_simple : mast_sel_pe;
////////////////////////////////////////////////////////////////////
//
// Address & Data Pass
//
always @(mast_sel or m0_addr_i or m1_addr_i or m2_addr_i or m3_addr_i
or m4_addr_i or m5_addr_i or m6_addr_i or m7_addr_i)
case(mast_sel) // synopsys parallel_case
3'd0: wb_addr_o = m0_addr_i;
3'd1: wb_addr_o = m1_addr_i;
3'd2: wb_addr_o = m2_addr_i;
3'd3: wb_addr_o = m3_addr_i;
3'd4: wb_addr_o = m4_addr_i;
3'd5: wb_addr_o = m5_addr_i;
3'd6: wb_addr_o = m6_addr_i;
3'd7: wb_addr_o = m7_addr_i;
default: wb_addr_o = {aw{1'bx}};
endcase
always @(mast_sel or m0_sel_i or m1_sel_i or m2_sel_i or m3_sel_i
or m4_sel_i or m5_sel_i or m6_sel_i or m7_sel_i)
case(mast_sel) // synopsys parallel_case
3'd0: wb_sel_o = m0_sel_i;
3'd1: wb_sel_o = m1_sel_i;
3'd2: wb_sel_o = m2_sel_i;
3'd3: wb_sel_o = m3_sel_i;
3'd4: wb_sel_o = m4_sel_i;
3'd5: wb_sel_o = m5_sel_i;
3'd6: wb_sel_o = m6_sel_i;
3'd7: wb_sel_o = m7_sel_i;
default: wb_sel_o = {sw{1'bx}};
endcase
always @(mast_sel or m0_data_i or m1_data_i or m2_data_i or m3_data_i
or m4_data_i or m5_data_i or m6_data_i or m7_data_i)
case(mast_sel) // synopsys parallel_case
3'd0: wb_data_o = m0_data_i;
3'd1: wb_data_o = m1_data_i;
3'd2: wb_data_o = m2_data_i;
3'd3: wb_data_o = m3_data_i;
3'd4: wb_data_o = m4_data_i;
3'd5: wb_data_o = m5_data_i;
3'd6: wb_data_o = m6_data_i;
3'd7: wb_data_o = m7_data_i;
default: wb_data_o = {dw{1'bx}};
endcase
assign m0_data_o = wb_data_i;
assign m1_data_o = wb_data_i;
assign m2_data_o = wb_data_i;
assign m3_data_o = wb_data_i;
assign m4_data_o = wb_data_i;
assign m5_data_o = wb_data_i;
assign m6_data_o = wb_data_i;
assign m7_data_o = wb_data_i;
////////////////////////////////////////////////////////////////////
//
// Control Signal Pass
//
always @(mast_sel or m0_we_i or m1_we_i or m2_we_i or m3_we_i
or m4_we_i or m5_we_i or m6_we_i or m7_we_i)
case(mast_sel) // synopsys parallel_case
3'd0: wb_we_o = m0_we_i;
3'd1: wb_we_o = m1_we_i;
3'd2: wb_we_o = m2_we_i;
3'd3: wb_we_o = m3_we_i;
3'd4: wb_we_o = m4_we_i;
3'd5: wb_we_o = m5_we_i;
3'd6: wb_we_o = m6_we_i;
3'd7: wb_we_o = m7_we_i;
default: wb_we_o = 1'bx;
endcase
always @(posedge clk_i)
m0_cyc_r <= #1 m0_cyc_i;
always @(posedge clk_i)
m1_cyc_r <= #1 m1_cyc_i;
always @(posedge clk_i)
m2_cyc_r <= #1 m2_cyc_i;
always @(posedge clk_i)
m3_cyc_r <= #1 m3_cyc_i;
always @(posedge clk_i)
m4_cyc_r <= #1 m4_cyc_i;
always @(posedge clk_i)
m5_cyc_r <= #1 m5_cyc_i;
always @(posedge clk_i)
m6_cyc_r <= #1 m6_cyc_i;
always @(posedge clk_i)
m7_cyc_r <= #1 m7_cyc_i;
always @(mast_sel or m0_cyc_i or m1_cyc_i or m2_cyc_i or m3_cyc_i
or m4_cyc_i or m5_cyc_i or m6_cyc_i or m7_cyc_i
or m0_cyc_r or m1_cyc_r or m2_cyc_r or m3_cyc_r
or m4_cyc_r or m5_cyc_r or m6_cyc_r or m7_cyc_r)
case(mast_sel) // synopsys parallel_case
3'd0: wb_cyc_o = m0_cyc_i & m0_cyc_r;
3'd1: wb_cyc_o = m1_cyc_i & m1_cyc_r;
3'd2: wb_cyc_o = m2_cyc_i & m2_cyc_r;
3'd3: wb_cyc_o = m3_cyc_i & m3_cyc_r;
3'd4: wb_cyc_o = m4_cyc_i & m4_cyc_r;
3'd5: wb_cyc_o = m5_cyc_i & m5_cyc_r;
3'd6: wb_cyc_o = m6_cyc_i & m6_cyc_r;
3'd7: wb_cyc_o = m7_cyc_i & m7_cyc_r;
default: wb_cyc_o = 1'b0;
endcase
always @(mast_sel or m0_stb_i or m1_stb_i or m2_stb_i or m3_stb_i
or m4_stb_i or m5_stb_i or m6_stb_i or m7_stb_i)
case(mast_sel) // synopsys parallel_case
3'd0: wb_stb_o = m0_stb_i;
3'd1: wb_stb_o = m1_stb_i;
3'd2: wb_stb_o = m2_stb_i;
3'd3: wb_stb_o = m3_stb_i;
3'd4: wb_stb_o = m4_stb_i;
3'd5: wb_stb_o = m5_stb_i;
3'd6: wb_stb_o = m6_stb_i;
3'd7: wb_stb_o = m7_stb_i;
default: wb_stb_o = 1'b0;
endcase
assign m0_ack_o = (mast_sel==3'd0) & wb_ack_i;
assign m1_ack_o = (mast_sel==3'd1) & wb_ack_i;
assign m2_ack_o = (mast_sel==3'd2) & wb_ack_i;
assign m3_ack_o = (mast_sel==3'd3) & wb_ack_i;
assign m4_ack_o = (mast_sel==3'd4) & wb_ack_i;
assign m5_ack_o = (mast_sel==3'd5) & wb_ack_i;
assign m6_ack_o = (mast_sel==3'd6) & wb_ack_i;
assign m7_ack_o = (mast_sel==3'd7) & wb_ack_i;
assign m0_err_o = (mast_sel==3'd0) & wb_err_i;
assign m1_err_o = (mast_sel==3'd1) & wb_err_i;
assign m2_err_o = (mast_sel==3'd2) & wb_err_i;
assign m3_err_o = (mast_sel==3'd3) & wb_err_i;
assign m4_err_o = (mast_sel==3'd4) & wb_err_i;
assign m5_err_o = (mast_sel==3'd5) & wb_err_i;
assign m6_err_o = (mast_sel==3'd6) & wb_err_i;
assign m7_err_o = (mast_sel==3'd7) & wb_err_i;
assign m0_rty_o = (mast_sel==3'd0) & wb_rty_i;
assign m1_rty_o = (mast_sel==3'd1) & wb_rty_i;
assign m2_rty_o = (mast_sel==3'd2) & wb_rty_i;
assign m3_rty_o = (mast_sel==3'd3) & wb_rty_i;
assign m4_rty_o = (mast_sel==3'd4) & wb_rty_i;
assign m5_rty_o = (mast_sel==3'd5) & wb_rty_i;
assign m6_rty_o = (mast_sel==3'd6) & wb_rty_i;
assign m7_rty_o = (mast_sel==3'd7) & wb_rty_i;
endmodule
|
// bsg_fifo_1r1w_small
//
// bsg_fifo with 1 read and 1 write
//
// When harden=0 (default), it uses async-read memory implementation
// Otherwise, it uses sync-read hardened memory implementation
// *** Two implementations above are functionally equivalent ***
//
// used for smaller fifos.
//
// input handshake protocol (based on ready_THEN_valid_p parameter):
// valid-and-ready or
// ready-then-valid
//
// output protocol is valid-yumi (like typical fifo)
// aka valid-then-ready
//
//
`include "bsg_defines.v"
module bsg_fifo_1r1w_small #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter harden_p = 0
, parameter ready_THEN_valid_p = 0
)
( input clk_i
, input reset_i
, input v_i
, output ready_o
, input [width_p-1:0] data_i
, output v_o
, output [width_p-1:0] data_o
, input yumi_i
);
if (harden_p == 0)
begin: unhardened
if (els_p == 2) begin:tf
bsg_two_fifo #(.width_p(width_p)
,.ready_THEN_valid_p(ready_THEN_valid_p)
) twof
(.*);
end
else begin:un
bsg_fifo_1r1w_small_unhardened #(.width_p(width_p)
,.els_p(els_p)
,.ready_THEN_valid_p(ready_THEN_valid_p)
) fifo
(.*);
end
end
else
begin: hardened
bsg_fifo_1r1w_small_hardened #(.width_p(width_p)
,.els_p(els_p)
,.ready_THEN_valid_p(ready_THEN_valid_p)
) fifo
(.*);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_fifo_1r1w_small)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32OI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A32OI_PP_SYMBOL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a32oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32OI_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHETAP_TB_V
`define SKY130_FD_SC_LS__DECAPHETAP_TB_V
/**
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__decaphetap.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VPB = 1'b0;
#60 VPWR = 1'b0;
#80 VGND = 1'b1;
#100 VPB = 1'b1;
#120 VPWR = 1'b1;
#140 VGND = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VPB = 1'b1;
#240 VGND = 1'b1;
#260 VPWR = 1'bx;
#280 VPB = 1'bx;
#300 VGND = 1'bx;
end
sky130_fd_sc_ls__decaphetap dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHETAP_TB_V
|
`timescale 1 ps / 1 ps
module ov7670_marker_tracker_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
output intr,
input [7:0]OV7670_D,
input OV7670_HREF,
input OV7670_PCLK,
output OV7670_PWDN,
output OV7670_RESET,
output OV7670_SIOC,
inout OV7670_SIOD,
input OV7670_VSYNC,
output OV7670_XCLK,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
reg intr_reg;
wire [16:0] marker_x, marker_y;
wire update_tracker_pos;
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 1;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 4
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
// I/O Connections assignments
assign intr = intr_reg;
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h1:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h2:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h3:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
reg_data_out <= 0;
end
else
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0 : reg_data_out <= slv_reg0;
2'h1 : reg_data_out <= slv_reg1;
2'h2 : reg_data_out <= {15'b0, marker_x};//slv_reg2;
2'h3 : reg_data_out <= {15'b0, marker_y}; //slv_reg3;
default : reg_data_out <= 0;
endcase
end
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
always@(posedge S_AXI_ACLK)
if(update_tracker_pos == 1 && slv_reg1[2])
intr_reg <= 1;
else
intr_reg <= 0;
// Add user logic here
//reg_intr
design_2_wrapper d(
.Config_Done(),
.OV7670_D,
.OV7670_HREF,
.OV7670_PCLK,
.OV7670_PWDN,
.OV7670_RESET,
.OV7670_SIOC,
.OV7670_SIOD,
.OV7670_VSYNC,
.OV7670_XCLK,
.clock_rtl(S_AXI_ACLK),
.go(slv_reg1[0]),
.marker_x(marker_x),
.marker_y(marker_y),
.resend_cam_config(slv_reg1[1]),
.reset_rtl(!S_AXI_ARESETN),
.track_clr(slv_reg0[20:0]),
.update_tracker_pos(update_tracker_pos)
);
// User logic ends
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBN_1_V
`define SKY130_FD_SC_MS__SDFBBN_1_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog wrapper for sdfbbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfbbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfbbn_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfbbn_1 (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.SCD(SCD),
.SCE(SCE),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBN_1_V
|
//-----------------------------------------------------------------------------
// File : spi_slave.v
// Creation date : 10.04.2017
// Creation time : 16:16:13
// Description : A minimalistic example for SPI slave IP-XACT document.
// Created by : TermosPullo
// Tool : Kactus2 3.4.20 32-bit
// Plugin : Verilog generator 2.0d
// This file was generated based on IP-XACT component tut.fi:template:spi_slave:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/template/spi_slave/1.0/spi_slave.1.0.xml
//-----------------------------------------------------------------------------
module spi_slave #(
parameter SLAVE_ID = 0
) (
// Interface: slave_if
input clk_in,
input data_in,
input slave_select_in,
output reg data_out,
// These ports are not in any interface
input rst_in // General reset, independent from master.
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
localparam BYTE_SIZE = 8; // How many bits are transferred per transaction
localparam BYTE_INDEX_SIZE = $clog2(BYTE_SIZE); // How many bits are needed to index a byte.
// Input and output bytes.
reg [BYTE_SIZE-1:0] data_recv;
reg [BYTE_SIZE-1:0] data_send;
// Used to iterate through the bytes.
reg [BYTE_INDEX_SIZE-1:0] send_iterator;
reg [BYTE_INDEX_SIZE-1:0] recv_iterator;
reg transferring;
reg transferred;
always @(posedge clk_in or posedge rst_in) begin
if(rst_in == 1'b1) begin
data_recv <= 0;
data_send <= 8'hAA;
send_iterator <= 1;
recv_iterator <= 0;
data_out <= 1'bz;
transferring <= 1;
transferred <= 0;
end
else begin
if (transferring == 1'b0) begin
data_out <= data_send[send_iterator];
if (!transferred) begin
data_recv[recv_iterator] <= data_in;
recv_iterator <= recv_iterator + 1;
end
else
data_send <= data_recv;
if (send_iterator < BYTE_SIZE - 1) begin
send_iterator <= send_iterator + 1;
end
if (recv_iterator >= BYTE_SIZE - 1) begin
transferred <= 1;
end
end
else begin
if (slave_select_in == 1'b0) begin
data_out <= data_send[0];
transferred <= 0;
send_iterator <= 1;
recv_iterator <= 0;
end
else begin
data_out <= 1'bz;
end
end
transferring <= slave_select_in;
end
end
endmodule
|
// system_acl_iface_hps_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module system_acl_iface_hps_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO53 // .hps_io_gpio_inst_GPIO53
);
system_acl_iface_hps_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53) // .hps_io_gpio_inst_GPIO53
);
endmodule
|
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