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// megafunction wizard: %Virtual JTAG%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: sld_virtual_jtag
// ============================================================
// File Name: vjtag.v
// Megafunction Name(s):
// sld_virtual_jtag
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module vjtag (
ir_out,
tdo,
ir_in,
tck,
tdi,
virtual_state_cdr,
virtual_state_cir,
virtual_state_e1dr,
virtual_state_e2dr,
virtual_state_pdr,
virtual_state_sdr,
virtual_state_udr,
virtual_state_uir);
input [1:0] ir_out;
input tdo;
output [1:0] ir_in;
output tck;
output tdi;
output virtual_state_cdr;
output virtual_state_cir;
output virtual_state_e1dr;
output virtual_state_e2dr;
output virtual_state_pdr;
output virtual_state_sdr;
output virtual_state_udr;
output virtual_state_uir;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: show_jtag_state STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "NO"
// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0"
// Retrieval info: CONSTANT: SLD_IR_WIDTH NUMERIC "2"
// Retrieval info: CONSTANT: SLD_SIM_ACTION STRING "((0,2,0,4),(0,1,1,2),(0,2,12,8),(0,2,34,8),(0,2,56,8),(0,1,0,2),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8))"
// Retrieval info: CONSTANT: SLD_SIM_N_SCAN NUMERIC "41"
// Retrieval info: CONSTANT: SLD_SIM_TOTAL_LENGTH NUMERIC "312"
// Retrieval info: USED_PORT: ir_in 0 0 2 0 OUTPUT NODEFVAL "ir_in[1..0]"
// Retrieval info: USED_PORT: ir_out 0 0 2 0 INPUT NODEFVAL "ir_out[1..0]"
// Retrieval info: USED_PORT: tck 0 0 0 0 OUTPUT NODEFVAL "tck"
// Retrieval info: USED_PORT: tdi 0 0 0 0 OUTPUT NODEFVAL "tdi"
// Retrieval info: USED_PORT: tdo 0 0 0 0 INPUT NODEFVAL "tdo"
// Retrieval info: USED_PORT: virtual_state_cdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cdr"
// Retrieval info: USED_PORT: virtual_state_cir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cir"
// Retrieval info: USED_PORT: virtual_state_e1dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e1dr"
// Retrieval info: USED_PORT: virtual_state_e2dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e2dr"
// Retrieval info: USED_PORT: virtual_state_pdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_pdr"
// Retrieval info: USED_PORT: virtual_state_sdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_sdr"
// Retrieval info: USED_PORT: virtual_state_udr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_udr"
// Retrieval info: USED_PORT: virtual_state_uir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_uir"
// Retrieval info: CONNECT: @ir_out 0 0 2 0 ir_out 0 0 2 0
// Retrieval info: CONNECT: @tdo 0 0 0 0 tdo 0 0 0 0
// Retrieval info: CONNECT: ir_in 0 0 2 0 @ir_in 0 0 2 0
// Retrieval info: CONNECT: tck 0 0 0 0 @tck 0 0 0 0
// Retrieval info: CONNECT: tdi 0 0 0 0 @tdi 0 0 0 0
// Retrieval info: CONNECT: virtual_state_cdr 0 0 0 0 @virtual_state_cdr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_cir 0 0 0 0 @virtual_state_cir 0 0 0 0
// Retrieval info: CONNECT: virtual_state_e1dr 0 0 0 0 @virtual_state_e1dr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_e2dr 0 0 0 0 @virtual_state_e2dr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_pdr 0 0 0 0 @virtual_state_pdr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_sdr 0 0 0 0 @virtual_state_sdr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_udr 0 0 0 0 @virtual_state_udr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_uir 0 0 0 0 @virtual_state_uir 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag_bb.v TRUE
|
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file Ins_Mem.v when simulating
// the core, Ins_Mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module Ins_Mem(
a,
spo);
input [9 : 0] a;
output [31 : 0] spo;
// synthesis translate_off
DIST_MEM_GEN_V5_1 #(
.C_ADDR_WIDTH(10),
.C_DEFAULT_DATA("0"),
.C_DEPTH(1024),
.C_FAMILY("spartan3"),
.C_HAS_CLK(0),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_SPRA(0),
.C_HAS_WE(0),
.C_MEM_INIT_FILE("Ins_Mem.mif"),
.C_MEM_TYPE(0),
.C_PARSER_TYPE(1),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(32))
inst (
.A(a),
.SPO(spo),
.D(),
.DPRA(),
.SPRA(),
.CLK(),
.WE(),
.I_CE(),
.QSPO_CE(),
.QDPO_CE(),
.QDPO_CLK(),
.QSPO_RST(),
.QDPO_RST(),
.QSPO_SRST(),
.QDPO_SRST(),
.DPO(),
.QSPO(),
.QDPO());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of Ins_Mem is "black_box"
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EBUFN_1_V
`define SKY130_FD_SC_LP__EBUFN_1_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ebufn_1 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ebufn_1 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EBUFN_1_V
|
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Module: gpio.v
// Description: Wishbone based general purpose IO
// --------------------------------------------------------------------
// --------------------------------------------------------------------
module gpio (
input wb_clk_i, // Wishbone slave interface
input wb_rst_i,
input wb_adr_i,
output [15:0] wb_dat_o,
input [15:0] wb_dat_i,
input [ 1:0] wb_sel_i,
input wb_we_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
output reg [7:0] leds_, // GPIO inputs/outputs
input [7:0] sw_
);
wire op;
assign op = wb_cyc_i & wb_stb_i;
assign wb_ack_o = op;
assign wb_dat_o = wb_adr_i ? { 8'h00, leds_ } : { 8'h00, sw_ };
always @(posedge wb_clk_i)
leds_ <= wb_rst_i ? 8'h0 : ((op & wb_we_i & wb_adr_i) ? wb_dat_i[7:0] : leds_);
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__SDFSTP_BEHAVIORAL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSTP_BEHAVIORAL_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 20 13:53:00 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top affine_block_ieee754_fp_multiplier_1_2 -prefix
// affine_block_ieee754_fp_multiplier_1_2_ affine_block_ieee754_fp_multiplier_0_0_stub.v
// Design : affine_block_ieee754_fp_multiplier_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ieee754_fp_multiplier,Vivado 2016.4" *)
module affine_block_ieee754_fp_multiplier_1_2(x, y, z)
/* synthesis syn_black_box black_box_pad_pin="x[31:0],y[31:0],z[31:0]" */;
input [31:0]x;
input [31:0]y;
output [31:0]z;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOLATCH_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__ISOLATCH_BEHAVIORAL_PP_V
/**
* isolatch: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_isolatch_pp_pkg_sn/sky130_fd_sc_lp__udp_isolatch_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__isolatch (
Q ,
D ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SLEEP_B_delayed;
wire D_delayed ;
reg notifier ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_isolatch_pp$PKG$sN isolatch_pp0 (buf_Q , D_delayed, SLEEP_B_delayed, notifier, KAPWR, VGND, VPWR);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOLATCH_BEHAVIORAL_PP_V |
module j1#(
//parameter bootram_file = "../image.ram" // For synthesis
parameter bootram_file = "./image.ram" // For simulation
)
(
// Inputs
sys_clk_i, sys_rst_i, io_din,
// Outputs
io_rd, io_wr, io_addr, io_dout);
input sys_clk_i; // main clock
input sys_rst_i; // reset
input [15:0] io_din; // io data in
output io_rd; // io read
output io_wr; // io write
output [15:0] io_addr; // io address
output [15:0] io_dout; // io data out
wire [15:0] insn;
wire [15:0] immediate = { 1'b0, insn[14:0] };
wire [15:0] ramrd;
reg [4:0] dsp;
reg [4:0] _dsp;
reg [15:0] st0;
reg [15:0] _st0;
wire [15:0] st1;
wire _dstkW; // D stack write
reg [12:0] pc;
reg [12:0] _pc;
reg [4:0] rsp;
reg [4:0] _rsp;
wire [15:0] rst0;
reg _rstkW; // R stack write
reg [15:0] _rstkD;
wire _ramWE; // RAM write enable
wire [15:0] pc_plus_1;
assign pc_plus_1 = pc + 1;
dp_ram #(13, 16, bootram_file)
ram0 ( .clk_b(sys_clk_i), .en_b(1), .dat_b(insn), .adr_b({_pc}),
.clk_a(sys_clk_i), .en_a(|_st0[15:14] == 0), .dat_a_out(ramrd), .dat_a(st1), .we_a(_ramWE & (_st0[15:14] == 0)), .adr_a(st0[15:1])
);
reg [15:0] dstack[0:31];
reg [15:0] rstack[0:31];
always @(posedge sys_clk_i) begin
if (_dstkW)
dstack[_dsp] = st0;
if (_rstkW)
rstack[_rsp] = _rstkD;
end
assign st1 = dstack[dsp];
assign rst0 = rstack[rsp];
reg [3:0] st0sel;
always @* begin
case (insn[14:13])
2'b00: st0sel = 0; // ubranch
2'b01: st0sel = 1; // 0branch
2'b10: st0sel = 0; // call
2'b11: st0sel = insn[11:8]; // ALU
default: st0sel = 4'bxxxx;
endcase
end
always @* begin
if (insn[15])
_st0 = immediate;
else
case (st0sel)
4'b0000: _st0 = st0;
4'b0001: _st0 = st1;
4'b0010: _st0 = st0 + st1;
4'b0011: _st0 = st0 & st1;
4'b0100: _st0 = st0 | st1;
4'b0101: _st0 = st0 ^ st1;
4'b0110: _st0 = ~st0;
4'b0111: _st0 = {16{(st1 == st0)}};
4'b1000: _st0 = {16{($signed(st1) < $signed(st0))}};
4'b1001: _st0 = st1 >> st0[3:0];
4'b1010: _st0 = st0 - 1;
4'b1011: _st0 = rst0;
4'b1100: _st0 = |st0[15:14] ? io_din : ramrd;
4'b1101: _st0 = st1 << st0[3:0];
4'b1110: _st0 = {rsp, 3'b000, dsp};
4'b1111: _st0 = {16{(st1 < st0)}};
default: _st0 = 16'hxxxx;
endcase
end
wire is_alu = (insn[15:13] == 3'b011);
wire is_lit = (insn[15]);
assign io_rd = (is_alu & (insn[11:8] == 4'hc) & (|st0[15:14]));
assign io_wr = _ramWE;
assign io_addr = st0;
assign io_dout = st1;
assign _ramWE = is_alu & insn[5];
assign _dstkW = is_lit | (is_alu & insn[7]);
wire [1:0] dd = insn[1:0]; // D stack delta
wire [1:0] rd = insn[3:2]; // R stack delta
always @* begin
if (is_lit) begin // literal
_dsp = dsp + 1;
_rsp = rsp;
_rstkW = 0;
_rstkD = _pc;
end else if (is_alu) begin
_dsp = dsp + {dd[1], dd[1], dd[1], dd};
_rsp = rsp + {rd[1], rd[1], rd[1], rd};
_rstkW = insn[6];
_rstkD = st0;
end else begin // jump/call
// predicated jump is like DROP
if (insn[15:13] == 3'b001) begin
_dsp = dsp - 1;
end else begin
_dsp = dsp;
end
if (insn[15:13] == 3'b010) begin // call
_rsp = rsp + 1;
_rstkW = 1;
_rstkD = {pc_plus_1[14:0], 1'b0};
end else begin
_rsp = rsp;
_rstkW = 0;
_rstkD = _pc;
end
end
always @* begin
if (sys_rst_i)
_pc = pc;
else
if ((insn[15:13] == 3'b000) |
((insn[15:13] == 3'b001) & (|st0 == 0)) |
(insn[15:13] == 3'b010))
_pc = insn[12:0];
else if (is_alu & insn[12])
_pc = rst0[15:1];
else
_pc = pc_plus_1;
end
always @(posedge sys_clk_i) begin
if (sys_rst_i) begin
pc <= 0;
dsp <= 0;
st0 <= 0;
rsp <= 0;
end else begin
dsp <= _dsp;
pc <= _pc;
st0 <= _st0;
rsp <= _rsp;
end
end
endmodule // j1 |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:55:59 06/28/2016
// Design Name:
// Module Name: genframe
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module genframe (
input wire clk, // 10 MHz
input wire mode, // 0: interlaced. 1: progressive
output reg [2:0] r,
output reg [2:0] g,
output reg [2:0] b,
output reg csync
);
reg [9:0] hc = 10'd0;
reg [9:0] vc = 10'd0;
reg intprog = 1'b0; // internal copy of mode
// Counters (horizontal and vertical).
// Horizontal counts tenths of microseconds. Vertical counts lines.
always @(posedge clk) begin
if (hc != 10'd639) begin
hc <= hc + 10'd1;
end
else begin
hc <= 10'd0;
if (intprog == 1'b0) begin
if (vc != 624) begin
vc <= vc + 10'd1;
end
else begin
vc <= 10'd0;
intprog <= mode;
end
end
else begin
if (vc != 311) begin
vc <= vc + 10'd1;
end
else begin
vc <= 10'd0;
intprog <= mode;
end
end
end
end
// Sync generation (info taken from http://martin.hinner.info/vga/pal.html )
reg videoen;
always @* begin
csync = 1'b1;
videoen = 1'b0;
if (vc == 10'd0 ||
vc == 10'd1 ||
vc == 10'd313 ||
vc == 10'd314) begin
if ((hc >= 10'd0 && hc < 10'd300) || (hc >= 10'd320 && hc < 10'd620)) begin
csync = 1'b0;
end
end
else if (vc == 10'd2) begin
if ((hc >= 10'd0 && hc < 10'd300) || (hc >= 10'd320 && hc < 10'd340)) begin
csync = 1'b0;
end
end
else if (vc == 10'd312) begin
if ((hc >= 10'd0 && hc < 10'd20) || (hc >= 10'd320 && hc < 10'd620)) begin
csync = 1'b0;
end
end
else if (vc == 10'd3 ||
vc == 10'd4 ||
vc == 10'd310 ||
vc == 10'd311 ||
vc == 10'd315 ||
vc == 10'd316 ||
vc == 10'd622 ||
vc == 10'd623 ||
vc == 10'd624 ||
(vc == 10'd309 && intprog == 1'b1)) begin
if ((hc >= 10'd0 && hc < 10'd20) || (hc >= 10'd320 && hc < 10'd340)) begin
csync = 1'b0;
end
end
else begin // we are in one visible scanline
if (hc >= 10'd0 && hc < 10'd40) begin
csync = 1'b0;
end
else if (hc >= 10'd120) begin
videoen = 1'b1;
end
end
end
// Color bars generation
always @* begin
r = 3'b000;
g = 3'b000;
b = 3'b000;
if (videoen == 1'b1) begin
if (hc >= 120+65*0 && hc < 120+65*1) begin
r = 3'b111;
g = 3'b111;
b = 3'b111;
end
else if (hc >= 120+65*1 && hc < 120+65*2) begin
r = 3'b111;
g = 3'b111;
b = 3'b000;
end
else if (hc >= 120+65*2 && hc < 120+65*3) begin
r = 3'b000;
g = 3'b111;
b = 3'b111;
end
else if (hc >= 120+65*3 && hc < 120+65*4) begin
r = 3'b000;
g = 3'b111;
b = 3'b000;
end
else if (hc >= 120+65*4 && hc < 120+65*5) begin
r = 3'b111;
g = 3'b000;
b = 3'b111;
end
else if (hc >= 120+65*5 && hc < 120+65*6) begin
r = 3'b111;
g = 3'b000;
b = 3'b000;
end
else if (hc >= 120+65*6 && hc < 120+65*7) begin
r = 3'b000;
g = 3'b000;
b = 3'b111;
end
else if (hc >= 120+65*7 && hc < 120+65*8) begin
r = 3'b000;
g = 3'b000;
b = 3'b000;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:06:02 05/29/2015
// Design Name:
// Module Name: UART_TX
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Serializer
//1 start bit, 1 stop bit
module UART_TX(
input [7:0] RxD_par, // 8 bit data
input RxD_start,
input RTS, // USB clear to send (active high)
input sys_clk,
input BaudTick,
output reg TxD_ser
);
//State machine
reg [3:0] state=0;
reg [7:0] RxD_buff=0;
always @(posedge sys_clk)
begin
if (RxD_start & state<2) begin
RxD_buff <= RxD_par; // Buffer data received
end else if (state[3] & BaudTick) begin
RxD_buff <= (RxD_buff >> 1); // Shift a bit at every baud tick during transmission
end
case(state)
4'b0000: if(RxD_start & RTS) state <= 4'b0010;//Initiate process when data is valied and USB is ready to receive
4'b0010: if(BaudTick) state <= 4'b0011; // Synchronize to baudtick,
4'b0011: if(BaudTick) state <= 4'b1000; //start (state !< 2 , state[3]=0 ie TxD = 0)
4'b1000: if(BaudTick) state <= 4'b1001; //bit 0
4'b1001: if(BaudTick) state <= 4'b1010; //bit 1
4'b1010: if(BaudTick) state <= 4'b1011; //bit 2
4'b1011: if(BaudTick) state <= 4'b1100; //bit 3
4'b1100: if(BaudTick) state <= 4'b1101; //bit 4
4'b1101: if(BaudTick) state <= 4'b1110; //bit 5
4'b1110: if(BaudTick) state <= 4'b1111; //bit 6
4'b1111: if(BaudTick) state <= 4'b0001; //bit 7
4'b0001: if(BaudTick) begin //stop
if(RxD_start & RTS) begin
state <= 4'b0011; // Data already synchronized to baudtick
end else begin
state <= 4'b0000; // (state < 2 ie TxD = 1)
end
end
default: if(BaudTick) state <= 4'b0000;
endcase
end
//reg TxD_ser;
always @(posedge sys_clk)
begin
// Filter according to state
TxD_ser <= (state < 3) | (state[3] & RxD_buff[0]); // Send it through a register
end
endmodule
|
// (c) NedoPC 2010
//
// doubles video line by replicating it in 3x512b RAM buffer
module vga_double(
input wire clk,
input wire hsync_start,
input wire scanin_start,
input wire [ 5:0] pix_in,
input wire scanout_start,
output reg [ 5:0] pix_out
);
/*
addressing of non-overlapping pages:
pg0 pg1
0xx 1xx
2xx 3xx
4xx 5xx
*/
reg [9:0] ptr_in; // count up to 720
reg [9:0] ptr_out; //
reg pages; // swapping of pages
reg wr_stb;
wire [ 7:0] data_out;
always @(posedge clk) if( hsync_start )
pages <= ~pages;
// write ptr and strobe
always @(posedge clk)
begin
if( scanin_start )
begin
ptr_in[9:8] <= 2'b00;
ptr_in[5:4] <= 2'b11;
end
else
begin
if( ptr_in[9:8]!=2'b11 ) // 768-720=48
begin
wr_stb <= ~wr_stb;
if( wr_stb )
begin
ptr_in <= ptr_in + 10'd1;
end
end
end
end
// read ptr
always @(posedge clk)
begin
if( scanout_start )
begin
ptr_out[9:8] <= 2'b00;
ptr_out[5:4] <= 2'b11;
end
else
begin
if( ptr_out[9:8]!=2'b11 )
begin
ptr_out <= ptr_out + 10'd1;
end
end
end
//read data
always @(posedge clk)
begin
if( ptr_out[9:8]!=2'b11 )
pix_out <= data_out[5:0];
else
pix_out <= 6'd0;
end
mem1536 line_buf( .clk(clk),
.wraddr({ptr_in[9:8], pages, ptr_in[7:0]}),
.wrdata({2'b00,pix_in}),
.wr_stb(wr_stb),
.rdaddr({ptr_out[9:8], (~pages), ptr_out[7:0]}),
.rddata(data_out)
);
endmodule
// 3x512b memory
module mem1536(
input wire clk,
input wire [10:0] wraddr,
input wire [ 7:0] wrdata,
input wire wr_stb,
input wire [10:0] rdaddr,
output reg [ 7:0] rddata
);
reg [7:0] mem [0:1535];
always @(posedge clk)
begin
if( wr_stb )
begin
mem[wraddr] <= wrdata;
end
rddata <= mem[rdaddr];
end
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
parameter CHANGE_START = 1'b0;
parameter CHANGE_CHECK = 1'b1;
reg r_change;
reg [width-1:0] r_test_expr;
reg r_state;
integer i;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_start_event;
wire valid_test_expr;
assign valid_start_event = ~(start_event^start_event);
assign valid_test_expr = ~((^test_expr)^(^test_expr));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_SYNTHESIS
`else
initial begin
r_state=CHANGE_START;
r_change=1'b0;
end
`endif
`ifdef OVL_SHARED_CODE
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin // active low reset
case (r_state)
CHANGE_START: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
if (start_event == 1'b1) begin
r_change <= 1'b0;
r_state <= CHANGE_CHECK;
r_test_expr <= test_expr;
i <= num_cks;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_open covered");
end
end
`endif // OVL_COVER_ON
end
end
CHANGE_CHECK: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (action_on_new_start != `OVL_IGNORE_NEW_START)
begin
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
end
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
// Count clock ticks
if (start_event == 1'b1) begin
if (action_on_new_start == `OVL_IGNORE_NEW_START && i > 0)
i <= i-1;
else if (action_on_new_start == `OVL_RESET_ON_NEW_START) begin
r_change <= 1'b0;
i <= num_cks;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_CORNER_ON) begin //corner coverage
if (action_on_new_start == `OVL_RESET_ON_NEW_START) begin
ovl_cover_t("window_resets covered");
end
end
end
`endif // OVL_COVER_ON
end
else if (action_on_new_start == `OVL_ERROR_ON_NEW_START) begin
i <= i-1;
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Start event evaluated TRUE before test expression changed");
`endif // OVL_ASSERT_ON
end
end
else if (i > 0)
i <= i-1;
if (r_test_expr != test_expr && !(start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)) begin
r_change <= 1'b1;
end
// go to start state on last check
if (i == 1 && !(start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)) begin
r_state <= CHANGE_START;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_close covered");
end
end
`endif // OVL_COVER_ON
// Check that the property is true
`ifdef OVL_ASSERT_ON
if ((r_change != 1'b1) && (r_test_expr == test_expr)) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression did not change value within num_cks cycles after start event");
end
`endif // OVL_ASSERT_ON
end
r_test_expr <= test_expr;
end
endcase
end
else begin
r_state <= CHANGE_START;
r_change <= 1'b0;
i <= 0;
`ifdef OVL_INIT_REG
r_test_expr <= {width{1'b0}};
`endif
end
end // always
`endif // OVL_SHARED_CODE
|
// megafunction wizard: %Altera PLL v17.0%
// GENERATION: XML
// pll_200.v
// Generated using ACDS version 17.0 595
`timescale 1 ps / 1 ps
module pll_200 (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire locked // locked.export
);
pll_200_0002 pll_200_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.locked (locked) // locked.export
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2017 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
// Retrieval info: <generic name="gui_device_speed_grade" value="1" />
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="true" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="1" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="200.0" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: </instance>
// IPFS_FILES : pll_200.vo
// RELATED_FILES: pll_200.v, pll_200_0002.v
|
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
//Date : Fri Oct 06 11:21:26 2017
//Host : WK115 running 64-bit major release (build 9200)
//Command : generate_target PmodCOLOR.bd
//Design : PmodCOLOR
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "PmodCOLOR,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=PmodCOLOR,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=8,numReposBlks=8,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,synth_mode=Global}" *) (* HW_HANDOFF = "PmodCOLOR.hwdef" *)
module PmodCOLOR
(AXI_LITE_GPIO_araddr,
AXI_LITE_GPIO_arready,
AXI_LITE_GPIO_arvalid,
AXI_LITE_GPIO_awaddr,
AXI_LITE_GPIO_awready,
AXI_LITE_GPIO_awvalid,
AXI_LITE_GPIO_bready,
AXI_LITE_GPIO_bresp,
AXI_LITE_GPIO_bvalid,
AXI_LITE_GPIO_rdata,
AXI_LITE_GPIO_rready,
AXI_LITE_GPIO_rresp,
AXI_LITE_GPIO_rvalid,
AXI_LITE_GPIO_wdata,
AXI_LITE_GPIO_wready,
AXI_LITE_GPIO_wstrb,
AXI_LITE_GPIO_wvalid,
AXI_LITE_IIC_araddr,
AXI_LITE_IIC_arready,
AXI_LITE_IIC_arvalid,
AXI_LITE_IIC_awaddr,
AXI_LITE_IIC_awready,
AXI_LITE_IIC_awvalid,
AXI_LITE_IIC_bready,
AXI_LITE_IIC_bresp,
AXI_LITE_IIC_bvalid,
AXI_LITE_IIC_rdata,
AXI_LITE_IIC_rready,
AXI_LITE_IIC_rresp,
AXI_LITE_IIC_rvalid,
AXI_LITE_IIC_wdata,
AXI_LITE_IIC_wready,
AXI_LITE_IIC_wstrb,
AXI_LITE_IIC_wvalid,
Pmod_out_pin10_i,
Pmod_out_pin10_o,
Pmod_out_pin10_t,
Pmod_out_pin1_i,
Pmod_out_pin1_o,
Pmod_out_pin1_t,
Pmod_out_pin2_i,
Pmod_out_pin2_o,
Pmod_out_pin2_t,
Pmod_out_pin3_i,
Pmod_out_pin3_o,
Pmod_out_pin3_t,
Pmod_out_pin4_i,
Pmod_out_pin4_o,
Pmod_out_pin4_t,
Pmod_out_pin7_i,
Pmod_out_pin7_o,
Pmod_out_pin7_t,
Pmod_out_pin8_i,
Pmod_out_pin8_o,
Pmod_out_pin8_t,
Pmod_out_pin9_i,
Pmod_out_pin9_o,
Pmod_out_pin9_t,
gpio_interrupt,
iic_interrupt,
s_axi_aclk,
s_axi_aresetn);
input [8:0]AXI_LITE_GPIO_araddr;
output AXI_LITE_GPIO_arready;
input AXI_LITE_GPIO_arvalid;
input [8:0]AXI_LITE_GPIO_awaddr;
output AXI_LITE_GPIO_awready;
input AXI_LITE_GPIO_awvalid;
input AXI_LITE_GPIO_bready;
output [1:0]AXI_LITE_GPIO_bresp;
output AXI_LITE_GPIO_bvalid;
output [31:0]AXI_LITE_GPIO_rdata;
input AXI_LITE_GPIO_rready;
output [1:0]AXI_LITE_GPIO_rresp;
output AXI_LITE_GPIO_rvalid;
input [31:0]AXI_LITE_GPIO_wdata;
output AXI_LITE_GPIO_wready;
input [3:0]AXI_LITE_GPIO_wstrb;
input AXI_LITE_GPIO_wvalid;
input [8:0]AXI_LITE_IIC_araddr;
output AXI_LITE_IIC_arready;
input AXI_LITE_IIC_arvalid;
input [8:0]AXI_LITE_IIC_awaddr;
output AXI_LITE_IIC_awready;
input AXI_LITE_IIC_awvalid;
input AXI_LITE_IIC_bready;
output [1:0]AXI_LITE_IIC_bresp;
output AXI_LITE_IIC_bvalid;
output [31:0]AXI_LITE_IIC_rdata;
input AXI_LITE_IIC_rready;
output [1:0]AXI_LITE_IIC_rresp;
output AXI_LITE_IIC_rvalid;
input [31:0]AXI_LITE_IIC_wdata;
output AXI_LITE_IIC_wready;
input [3:0]AXI_LITE_IIC_wstrb;
input AXI_LITE_IIC_wvalid;
input Pmod_out_pin10_i;
output Pmod_out_pin10_o;
output Pmod_out_pin10_t;
input Pmod_out_pin1_i;
output Pmod_out_pin1_o;
output Pmod_out_pin1_t;
input Pmod_out_pin2_i;
output Pmod_out_pin2_o;
output Pmod_out_pin2_t;
input Pmod_out_pin3_i;
output Pmod_out_pin3_o;
output Pmod_out_pin3_t;
input Pmod_out_pin4_i;
output Pmod_out_pin4_o;
output Pmod_out_pin4_t;
input Pmod_out_pin7_i;
output Pmod_out_pin7_o;
output Pmod_out_pin7_t;
input Pmod_out_pin8_i;
output Pmod_out_pin8_o;
output Pmod_out_pin8_t;
input Pmod_out_pin9_i;
output Pmod_out_pin9_o;
output Pmod_out_pin9_t;
output gpio_interrupt;
output iic_interrupt;
input s_axi_aclk;
input s_axi_aresetn;
wire [8:0]S_AXI_1_1_ARADDR;
wire S_AXI_1_1_ARREADY;
wire S_AXI_1_1_ARVALID;
wire [8:0]S_AXI_1_1_AWADDR;
wire S_AXI_1_1_AWREADY;
wire S_AXI_1_1_AWVALID;
wire S_AXI_1_1_BREADY;
wire [1:0]S_AXI_1_1_BRESP;
wire S_AXI_1_1_BVALID;
wire [31:0]S_AXI_1_1_RDATA;
wire S_AXI_1_1_RREADY;
wire [1:0]S_AXI_1_1_RRESP;
wire S_AXI_1_1_RVALID;
wire [31:0]S_AXI_1_1_WDATA;
wire S_AXI_1_1_WREADY;
wire [3:0]S_AXI_1_1_WSTRB;
wire S_AXI_1_1_WVALID;
wire [8:0]S_AXI_1_ARADDR;
wire S_AXI_1_ARREADY;
wire S_AXI_1_ARVALID;
wire [8:0]S_AXI_1_AWADDR;
wire S_AXI_1_AWREADY;
wire S_AXI_1_AWVALID;
wire S_AXI_1_BREADY;
wire [1:0]S_AXI_1_BRESP;
wire S_AXI_1_BVALID;
wire [31:0]S_AXI_1_RDATA;
wire S_AXI_1_RREADY;
wire [1:0]S_AXI_1_RRESP;
wire S_AXI_1_RVALID;
wire [31:0]S_AXI_1_WDATA;
wire S_AXI_1_WREADY;
wire [3:0]S_AXI_1_WSTRB;
wire S_AXI_1_WVALID;
wire [1:0]axi_gpio_0_gpio_io_o;
wire [1:0]axi_gpio_0_gpio_io_t;
wire axi_gpio_0_ip2intc_irpt;
wire axi_iic_0_iic2intc_irpt;
wire axi_iic_0_scl_o;
wire axi_iic_0_scl_t;
wire axi_iic_0_sda_o;
wire axi_iic_0_sda_t;
wire pmod_bridge_0_Pmod_out_PIN10_I;
wire pmod_bridge_0_Pmod_out_PIN10_O;
wire pmod_bridge_0_Pmod_out_PIN10_T;
wire pmod_bridge_0_Pmod_out_PIN1_I;
wire pmod_bridge_0_Pmod_out_PIN1_O;
wire pmod_bridge_0_Pmod_out_PIN1_T;
wire pmod_bridge_0_Pmod_out_PIN2_I;
wire pmod_bridge_0_Pmod_out_PIN2_O;
wire pmod_bridge_0_Pmod_out_PIN2_T;
wire pmod_bridge_0_Pmod_out_PIN3_I;
wire pmod_bridge_0_Pmod_out_PIN3_O;
wire pmod_bridge_0_Pmod_out_PIN3_T;
wire pmod_bridge_0_Pmod_out_PIN4_I;
wire pmod_bridge_0_Pmod_out_PIN4_O;
wire pmod_bridge_0_Pmod_out_PIN4_T;
wire pmod_bridge_0_Pmod_out_PIN7_I;
wire pmod_bridge_0_Pmod_out_PIN7_O;
wire pmod_bridge_0_Pmod_out_PIN7_T;
wire pmod_bridge_0_Pmod_out_PIN8_I;
wire pmod_bridge_0_Pmod_out_PIN8_O;
wire pmod_bridge_0_Pmod_out_PIN8_T;
wire pmod_bridge_0_Pmod_out_PIN9_I;
wire pmod_bridge_0_Pmod_out_PIN9_O;
wire pmod_bridge_0_Pmod_out_PIN9_T;
wire [3:0]pmod_bridge_0_in_top_bus_I;
wire [1:0]pmod_i_to_gpio_o_Dout;
wire [3:0]pmod_o_concat_dout;
wire [3:0]pmod_t_concat_dout;
wire s_axi_aclk_1;
wire s_axi_aresetn_1;
wire [0:0]xlslice_1_Dout;
wire [0:0]xlslice_2_Dout;
assign AXI_LITE_GPIO_arready = S_AXI_1_ARREADY;
assign AXI_LITE_GPIO_awready = S_AXI_1_AWREADY;
assign AXI_LITE_GPIO_bresp[1:0] = S_AXI_1_BRESP;
assign AXI_LITE_GPIO_bvalid = S_AXI_1_BVALID;
assign AXI_LITE_GPIO_rdata[31:0] = S_AXI_1_RDATA;
assign AXI_LITE_GPIO_rresp[1:0] = S_AXI_1_RRESP;
assign AXI_LITE_GPIO_rvalid = S_AXI_1_RVALID;
assign AXI_LITE_GPIO_wready = S_AXI_1_WREADY;
assign AXI_LITE_IIC_arready = S_AXI_1_1_ARREADY;
assign AXI_LITE_IIC_awready = S_AXI_1_1_AWREADY;
assign AXI_LITE_IIC_bresp[1:0] = S_AXI_1_1_BRESP;
assign AXI_LITE_IIC_bvalid = S_AXI_1_1_BVALID;
assign AXI_LITE_IIC_rdata[31:0] = S_AXI_1_1_RDATA;
assign AXI_LITE_IIC_rresp[1:0] = S_AXI_1_1_RRESP;
assign AXI_LITE_IIC_rvalid = S_AXI_1_1_RVALID;
assign AXI_LITE_IIC_wready = S_AXI_1_1_WREADY;
assign Pmod_out_pin10_o = pmod_bridge_0_Pmod_out_PIN10_O;
assign Pmod_out_pin10_t = pmod_bridge_0_Pmod_out_PIN10_T;
assign Pmod_out_pin1_o = pmod_bridge_0_Pmod_out_PIN1_O;
assign Pmod_out_pin1_t = pmod_bridge_0_Pmod_out_PIN1_T;
assign Pmod_out_pin2_o = pmod_bridge_0_Pmod_out_PIN2_O;
assign Pmod_out_pin2_t = pmod_bridge_0_Pmod_out_PIN2_T;
assign Pmod_out_pin3_o = pmod_bridge_0_Pmod_out_PIN3_O;
assign Pmod_out_pin3_t = pmod_bridge_0_Pmod_out_PIN3_T;
assign Pmod_out_pin4_o = pmod_bridge_0_Pmod_out_PIN4_O;
assign Pmod_out_pin4_t = pmod_bridge_0_Pmod_out_PIN4_T;
assign Pmod_out_pin7_o = pmod_bridge_0_Pmod_out_PIN7_O;
assign Pmod_out_pin7_t = pmod_bridge_0_Pmod_out_PIN7_T;
assign Pmod_out_pin8_o = pmod_bridge_0_Pmod_out_PIN8_O;
assign Pmod_out_pin8_t = pmod_bridge_0_Pmod_out_PIN8_T;
assign Pmod_out_pin9_o = pmod_bridge_0_Pmod_out_PIN9_O;
assign Pmod_out_pin9_t = pmod_bridge_0_Pmod_out_PIN9_T;
assign S_AXI_1_1_ARADDR = AXI_LITE_IIC_araddr[8:0];
assign S_AXI_1_1_ARVALID = AXI_LITE_IIC_arvalid;
assign S_AXI_1_1_AWADDR = AXI_LITE_IIC_awaddr[8:0];
assign S_AXI_1_1_AWVALID = AXI_LITE_IIC_awvalid;
assign S_AXI_1_1_BREADY = AXI_LITE_IIC_bready;
assign S_AXI_1_1_RREADY = AXI_LITE_IIC_rready;
assign S_AXI_1_1_WDATA = AXI_LITE_IIC_wdata[31:0];
assign S_AXI_1_1_WSTRB = AXI_LITE_IIC_wstrb[3:0];
assign S_AXI_1_1_WVALID = AXI_LITE_IIC_wvalid;
assign S_AXI_1_ARADDR = AXI_LITE_GPIO_araddr[8:0];
assign S_AXI_1_ARVALID = AXI_LITE_GPIO_arvalid;
assign S_AXI_1_AWADDR = AXI_LITE_GPIO_awaddr[8:0];
assign S_AXI_1_AWVALID = AXI_LITE_GPIO_awvalid;
assign S_AXI_1_BREADY = AXI_LITE_GPIO_bready;
assign S_AXI_1_RREADY = AXI_LITE_GPIO_rready;
assign S_AXI_1_WDATA = AXI_LITE_GPIO_wdata[31:0];
assign S_AXI_1_WSTRB = AXI_LITE_GPIO_wstrb[3:0];
assign S_AXI_1_WVALID = AXI_LITE_GPIO_wvalid;
assign gpio_interrupt = axi_gpio_0_ip2intc_irpt;
assign iic_interrupt = axi_iic_0_iic2intc_irpt;
assign pmod_bridge_0_Pmod_out_PIN10_I = Pmod_out_pin10_i;
assign pmod_bridge_0_Pmod_out_PIN1_I = Pmod_out_pin1_i;
assign pmod_bridge_0_Pmod_out_PIN2_I = Pmod_out_pin2_i;
assign pmod_bridge_0_Pmod_out_PIN3_I = Pmod_out_pin3_i;
assign pmod_bridge_0_Pmod_out_PIN4_I = Pmod_out_pin4_i;
assign pmod_bridge_0_Pmod_out_PIN7_I = Pmod_out_pin7_i;
assign pmod_bridge_0_Pmod_out_PIN8_I = Pmod_out_pin8_i;
assign pmod_bridge_0_Pmod_out_PIN9_I = Pmod_out_pin9_i;
assign s_axi_aclk_1 = s_axi_aclk;
assign s_axi_aresetn_1 = s_axi_aresetn;
PmodCOLOR_axi_gpio_0_0 axi_gpio_0
(.gpio_io_i(pmod_i_to_gpio_o_Dout),
.gpio_io_o(axi_gpio_0_gpio_io_o),
.gpio_io_t(axi_gpio_0_gpio_io_t),
.ip2intc_irpt(axi_gpio_0_ip2intc_irpt),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_araddr(S_AXI_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(S_AXI_1_ARREADY),
.s_axi_arvalid(S_AXI_1_ARVALID),
.s_axi_awaddr(S_AXI_1_AWADDR),
.s_axi_awready(S_AXI_1_AWREADY),
.s_axi_awvalid(S_AXI_1_AWVALID),
.s_axi_bready(S_AXI_1_BREADY),
.s_axi_bresp(S_AXI_1_BRESP),
.s_axi_bvalid(S_AXI_1_BVALID),
.s_axi_rdata(S_AXI_1_RDATA),
.s_axi_rready(S_AXI_1_RREADY),
.s_axi_rresp(S_AXI_1_RRESP),
.s_axi_rvalid(S_AXI_1_RVALID),
.s_axi_wdata(S_AXI_1_WDATA),
.s_axi_wready(S_AXI_1_WREADY),
.s_axi_wstrb(S_AXI_1_WSTRB),
.s_axi_wvalid(S_AXI_1_WVALID));
PmodCOLOR_axi_iic_0_0 axi_iic_0
(.iic2intc_irpt(axi_iic_0_iic2intc_irpt),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_araddr(S_AXI_1_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(S_AXI_1_1_ARREADY),
.s_axi_arvalid(S_AXI_1_1_ARVALID),
.s_axi_awaddr(S_AXI_1_1_AWADDR),
.s_axi_awready(S_AXI_1_1_AWREADY),
.s_axi_awvalid(S_AXI_1_1_AWVALID),
.s_axi_bready(S_AXI_1_1_BREADY),
.s_axi_bresp(S_AXI_1_1_BRESP),
.s_axi_bvalid(S_AXI_1_1_BVALID),
.s_axi_rdata(S_AXI_1_1_RDATA),
.s_axi_rready(S_AXI_1_1_RREADY),
.s_axi_rresp(S_AXI_1_1_RRESP),
.s_axi_rvalid(S_AXI_1_1_RVALID),
.s_axi_wdata(S_AXI_1_1_WDATA),
.s_axi_wready(S_AXI_1_1_WREADY),
.s_axi_wstrb(S_AXI_1_1_WSTRB),
.s_axi_wvalid(S_AXI_1_1_WVALID),
.scl_i(xlslice_1_Dout),
.scl_o(axi_iic_0_scl_o),
.scl_t(axi_iic_0_scl_t),
.sda_i(xlslice_2_Dout),
.sda_o(axi_iic_0_sda_o),
.sda_t(axi_iic_0_sda_t));
PmodCOLOR_pmod_bridge_0_0 pmod_bridge_0
(.in_top_bus_I(pmod_bridge_0_in_top_bus_I),
.in_top_bus_O(pmod_o_concat_dout),
.in_top_bus_T(pmod_t_concat_dout),
.out0_I(pmod_bridge_0_Pmod_out_PIN1_I),
.out0_O(pmod_bridge_0_Pmod_out_PIN1_O),
.out0_T(pmod_bridge_0_Pmod_out_PIN1_T),
.out1_I(pmod_bridge_0_Pmod_out_PIN2_I),
.out1_O(pmod_bridge_0_Pmod_out_PIN2_O),
.out1_T(pmod_bridge_0_Pmod_out_PIN2_T),
.out2_I(pmod_bridge_0_Pmod_out_PIN3_I),
.out2_O(pmod_bridge_0_Pmod_out_PIN3_O),
.out2_T(pmod_bridge_0_Pmod_out_PIN3_T),
.out3_I(pmod_bridge_0_Pmod_out_PIN4_I),
.out3_O(pmod_bridge_0_Pmod_out_PIN4_O),
.out3_T(pmod_bridge_0_Pmod_out_PIN4_T),
.out4_I(pmod_bridge_0_Pmod_out_PIN7_I),
.out4_O(pmod_bridge_0_Pmod_out_PIN7_O),
.out4_T(pmod_bridge_0_Pmod_out_PIN7_T),
.out5_I(pmod_bridge_0_Pmod_out_PIN8_I),
.out5_O(pmod_bridge_0_Pmod_out_PIN8_O),
.out5_T(pmod_bridge_0_Pmod_out_PIN8_T),
.out6_I(pmod_bridge_0_Pmod_out_PIN9_I),
.out6_O(pmod_bridge_0_Pmod_out_PIN9_O),
.out6_T(pmod_bridge_0_Pmod_out_PIN9_T),
.out7_I(pmod_bridge_0_Pmod_out_PIN10_I),
.out7_O(pmod_bridge_0_Pmod_out_PIN10_O),
.out7_T(pmod_bridge_0_Pmod_out_PIN10_T));
PmodCOLOR_xlslice_0_0 pmod_i_to_gpio_i
(.Din(pmod_bridge_0_in_top_bus_I),
.Dout(pmod_i_to_gpio_o_Dout));
PmodCOLOR_xlconcat_0_1 pmod_o_concat
(.In0(axi_gpio_0_gpio_io_o),
.In1(axi_iic_0_scl_o),
.In2(axi_iic_0_sda_o),
.dout(pmod_o_concat_dout));
PmodCOLOR_xlconcat_0_0 pmod_t_concat
(.In0(axi_gpio_0_gpio_io_t),
.In1(axi_iic_0_scl_t),
.In2(axi_iic_0_sda_t),
.dout(pmod_t_concat_dout));
PmodCOLOR_xlslice_0_1 xlslice_1
(.Din(pmod_bridge_0_in_top_bus_I),
.Dout(xlslice_1_Dout));
PmodCOLOR_xlslice_0_2 xlslice_2
(.Din(pmod_bridge_0_in_top_bus_I),
.Dout(xlslice_2_Dout));
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_registers.v
// Version : v1.0
// Description: Registers defined/implemented for the core to set/report
// various features/status of the core.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
`include "axi_traffic_gen_v2_0_defines.v"
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_registers
# (
parameter C_IS_COHERENT = 0 ,
parameter C_IS_AFI = 0 ,
parameter C_M_AXI_DATA_WIDTH = 32,
parameter C_IS_AXI4 = 1 ,
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_M_AXI_THREAD_ID_WIDTH = 1 ,
parameter C_S_AXI_ID_WIDTH = 1 ,
parameter C_ATG_BASIC_AXI4 = 0 ,
parameter C_ATG_REPEAT_TYPE = 0 , //0-One-shit,1-Repititive
parameter C_ATG_HLTP_MODE = 0 , //0-Custom,1-High Level Traffic.
parameter C_ATG_STATIC = 0 ,
parameter C_ATG_SLAVE_ONLY = 0 ,
parameter C_ATG_SYSTEM_INIT = 0 ,
parameter C_ATG_STREAMING = 0
) (
input Clk ,
input rst_l ,
input core_global_start ,
input core_global_stop ,
//write
input [15:0] wr_reg_decode ,
input [31:0] wr_reg_data ,
input [9:0] reg0_mr_ptr_update ,
input [9:0] reg0_mw_ptr_update ,
input mr_done_ff ,
input mw_done_ff ,
input rddec6_valid_ff ,
input [15:0] err_new_slv ,
//read
input [15:0] rd_reg_decode ,
output [31:0] rd_reg_data_raw ,
input [71:0] slv_ex_info0_ff ,
input [71:0] slv_ex_info1_ff ,
input [71:0] slv_ex_info1 ,
input slv_ex_valid0_ff ,
input slv_ex_valid1_ff ,
input slv_ex_toggle_ff ,
//masterwrite
input b_resp_unexp_ff ,
input b_resp_bad_ff ,
//masterslave
input mr_unexp ,
input mr_fifo_out_resp_bad ,
input mr_bad_last_ff ,
//controls to external modules
output reg1_disallow_excl ,
output reg1_sgl_slv_wr ,
output reg1_wrs_block_rds ,
output reg1_sgl_slv_rd ,
output reg [9:0] reg0_mw_ptr_ff ,
output reg0_m_enable_cmdram_mrw ,
output reg0_m_enable_cmdram_mrw_ff,
output reg reg0_m_enable_ff ,
output reg reg0_m_enable_3ff ,
output reg reg0_loop_en_ff ,
//masterread
output reg [9:0] reg0_mr_ptr_ff ,
output err_out ,
output irq_out ,
//debug capture
output [9:0] reg0_mr_ptr ,
output [9:0] reg0_mw_ptr ,
output [7:0] reg0_rev
);
//write path
reg [31:0] reg1_slvctl_ff ;
reg [31:0] reg2_err_ff ;
reg [31:0] reg3_err_en_ff ;
reg [31:0] reg4_mstctl_ff ;
reg [31:0] reg9_dbgpause1_ff ;
reg [31:0] reg10_dbgpause2_ff;
reg [31:0] reg11_dbgpause3_ff;
reg reg0_m_enable_2ff ;
reg reg0_m_enable_2pff ;
//generate global_start/global_stop pulse
wire global_start_pulse;
wire global_stop_pulse;
reg global_start_1ff;
reg global_stop_1ff;
always @(posedge Clk) begin
global_start_1ff <= (rst_l) ? core_global_start : 1'b0;
global_stop_1ff <= (rst_l) ? core_global_stop : 1'b0;
end
assign global_start_pulse = ~global_start_1ff & core_global_start;
assign global_stop_pulse = ~global_stop_1ff & core_global_stop ;
wire reg0_m_disable;
//
//loop from sw registers-enable.
//
wire set_reg0_loop_en; //enable looping from sw register.
wire set_reg0_loop_dis; //disable looping from sw register.
//reg reg0_loop_en_ff;
//
//Generate control signal for repeat pattern type
//
wire repetitive_on;
assign repetitive_on = (C_ATG_REPEAT_TYPE == 1 & C_ATG_HLTP_MODE == 1 ) ? 1'b1 :
(C_ATG_HLTP_MODE == 0 & reg0_loop_en_ff == 1'b1) ? 1'b1 :1'b0;
wire restart_core_pre1;
reg restart_core_pre;
reg restart_core; //Delayed to allow better settling time for the core before
//re-start.
reg cycle_complete;
reg cycle_complete_1ff;
//wait for disable, and generate a restart pulse
//always @(posedge Clk) begin
// if(rst_l == 1'b0 ) begin
// cycle_complete <= 1'b0;
// cycle_complete_1ff <= 1'b0;
// restart_core_pre <= 1'b0;
// restart_core <= 1'b0;
// end else begin
// if(repetitive_on == 1'b1) begin
// cycle_complete <= reg0_m_disable;
// cycle_complete_1ff <= cycle_complete;
// restart_core_pre <= restart_core_pre1;
// restart_core <= restart_core_pre;
// end
// end
//end
//assign restart_core_pre1 = ~cycle_complete_1ff & cycle_complete;
//pulse generation for HLTP-REPEAT-ON
reg hltp_repeat_pre;
reg hltp_repeat_pre_d1;
always @(posedge Clk) begin
if(rst_l == 1'b0 ) begin
hltp_repeat_pre <= 1'b0;
hltp_repeat_pre_d1 <= 1'b0;
end else if(C_ATG_REPEAT_TYPE == 1 & C_ATG_HLTP_MODE == 1)begin
hltp_repeat_pre <= 1'b1;
hltp_repeat_pre_d1 <= hltp_repeat_pre;
end
end
wire hltp_repeat_pulse;
assign hltp_repeat_pulse = ~hltp_repeat_pre_d1 & hltp_repeat_pre;
wire set_reg0_m_enable;
assign set_reg0_m_enable = (wr_reg_decode[0] & wr_reg_data[20] ) | (global_start_pulse);// | (restart_core);
assign set_reg0_loop_en = (wr_reg_decode[0] & wr_reg_data[19] ) | (global_start_pulse &(C_ATG_REPEAT_TYPE == 1 & C_ATG_HLTP_MODE == 1) );
assign set_reg0_loop_dis = (wr_reg_decode[0] & ~wr_reg_data[19]) | (global_stop_pulse );
//register is sperated- only read/write functionality. This value will not
//effect the current running ptr value/initial value of the pointer.
reg [9:0] reg0_mr_ptr_reg_ff;
reg [9:0] reg0_mw_ptr_reg_ff;
wire [9:0] reg0_mr_ptr_reg = (wr_reg_decode[0]) ? wr_reg_data[9:0] : reg0_mr_ptr_reg_ff;
wire [9:0] reg0_mw_ptr_reg = (wr_reg_decode[0]) ? wr_reg_data[19:10] : reg0_mw_ptr_reg_ff;
assign reg0_mr_ptr = reg0_mr_ptr_update[9:0];
assign reg0_mw_ptr = reg0_mw_ptr_update[9:0];
assign reg0_m_disable = mr_done_ff && mw_done_ff;
wire reg0_m_enable = (set_reg0_m_enable) ? 1'b1 :
(reg0_m_disable) ? 1'b0 : reg0_m_enable_ff;
wire reg0_loop_en = (set_reg0_loop_en) ? 1'b1 :
(set_reg0_loop_dis) ? 1'b0 :
reg0_loop_en_ff;
wire [31:0] reg1_slvctl = (wr_reg_decode[1]) ? wr_reg_data[31:0] :
reg1_slvctl_ff[31:0];
wire [31:0] reg2_err_pre2 = (wr_reg_decode[2]) ?
~wr_reg_data[31:0] & reg2_err_ff[31:0] :
reg2_err_ff[31:0];
wire [31:0] reg3_err_en = (wr_reg_decode[3]) ? wr_reg_data[31:0] :
reg3_err_en_ff[31:0];
wire [31:0] reg4_mstctl = (wr_reg_decode[4]) ? wr_reg_data[31:0] :
reg4_mstctl_ff[31:0];
wire [31:0] reg9_dbgpause1 = (wr_reg_decode[9]) ? wr_reg_data[31:0] :
reg9_dbgpause1_ff[31:0];
wire [31:0] reg10_dbgpause2 = (wr_reg_decode[10]) ? wr_reg_data[31:0] :
reg10_dbgpause2_ff[31:0];
wire [31:0] reg11_dbgpause3 = (wr_reg_decode[11]) ? wr_reg_data[31:0] :
reg11_dbgpause3_ff[31:0];
wire [31:0] reg2_err_pre = { ~rddec6_valid_ff && reg2_err_pre2[31],
reg2_err_pre2[30:0] };
wire [31:16] err_new_mst;
//Clear Status register when the core is enabled afresh.
wire [31:0] reg2_err = (set_reg0_m_enable == 1'b1) ? (32'h0):
(reg2_err_pre[31:0] | (reg3_err_en_ff[31:0] & { err_new_mst[31:16], err_new_slv[15:0] }));
wire reg0_m_enable_3 = reg0_m_enable_ff && reg0_m_enable_2ff;
wire reg0_m_enable_4 = reg0_m_enable_ff && reg0_m_enable_2pff;
always @(posedge Clk) begin
reg0_m_enable_ff <= (rst_l) ? reg0_m_enable : 1'b0;
reg0_m_enable_2ff <= (rst_l) ? reg0_m_enable_ff : 1'b0;
reg0_m_enable_2pff <= (rst_l) ? reg0_m_enable_3 : 1'b0;
reg0_m_enable_3ff <= (rst_l) ? reg0_m_enable_4 : 1'b0;
reg1_slvctl_ff[31:0] <= (rst_l) ? reg1_slvctl[31:0] : 32'h0;
reg2_err_ff[31:0] <= (rst_l) ? reg2_err[31:0] : 32'h0;
reg3_err_en_ff[31:0] <= (rst_l) ? reg3_err_en[31:0] : 32'h80000000;
reg4_mstctl_ff[31:0] <= (rst_l) ? reg4_mstctl[31:0] : 32'h0;
reg9_dbgpause1_ff[31:0] <= (rst_l) ? reg9_dbgpause1[31:0] : 32'h0;
reg10_dbgpause2_ff[31:0] <= (rst_l) ? reg10_dbgpause2[31:0] : 32'h0;
reg11_dbgpause3_ff[31:0] <= (rst_l) ? reg11_dbgpause3[31:0] : 32'h0;
reg0_mr_ptr_reg_ff[9:0] <= (rst_l) ? reg0_mr_ptr_reg[9:0] : 10'h0;
reg0_mw_ptr_reg_ff[9:0] <= (rst_l) ? reg0_mw_ptr_reg[9:0] : 10'h0;
reg0_loop_en_ff <= (rst_l) ? reg0_loop_en : 1'b0;
end
always @(posedge Clk) begin
if(rst_l == 1'b0 ) begin
reg0_mw_ptr_ff[9:0] <= 10'h0 ;
reg0_mr_ptr_ff[9:0] <= 10'h0 ;
end else if(reg0_m_disable == 1'b1) begin
reg0_mw_ptr_ff[9:0] <= 10'h0 ;
reg0_mr_ptr_ff[9:0] <= 10'h0 ;
end else begin
reg0_mw_ptr_ff[9:0] <= reg0_mw_ptr[9:0] ;
reg0_mr_ptr_ff[9:0] <= reg0_mr_ptr[9:0] ;
end
end
//read path
assign reg0_rev = `AXIEX_REV; // version, revision
wire datam64 = (C_M_AXI_DATA_WIDTH == 64);
wire datas64 = (C_S_AXI_DATA_WIDTH == 64);
wire [3:0] reg5_s_id_width = C_S_AXI_ID_WIDTH;
wire is_axi4 = (C_IS_AXI4 != 0);
wire is_coh = (C_IS_COHERENT != 0);
wire is_afi = (C_IS_AFI != 0);
wire is_pele_gs = 1'b0;
wire [1:0] afi_num = 2'b00;
wire [2:0] reg0_m_id_width = C_M_AXI_THREAD_ID_WIDTH-1'b1;
wire [31:0] reg0_rd = { reg0_rev[7:0], //31:24
reg0_m_id_width[2:0], reg0_m_enable_ff, //23:20 //KPOLISE
reg0_loop_en_ff,19'h0 }; //19:0
wire [31:0] reg1_rd = { 12'h0, reg1_slvctl_ff[19:0] };
wire [31:0] reg2_rd = reg2_err_ff[31:0];
wire [31:0] reg3_rd = reg3_err_en_ff[31:0];
wire [31:0] reg4_rd = { 16'h0, reg4_mstctl_ff[15:0] };
//wire [31:0] reg5_rd = { 1'b0, is_axi4, 1'b0, datam64,
// 1'b0, datas64, is_coh, is_afi,
// reg5_s_id_width[3:0], is_pele_gs, 1'b0, afi_num[1:0],
// 5'h0, slv_ex_toggle_ff, slv_ex_valid1_ff, slv_ex_valid0_ff,
// slv_ex_info0_ff[71:64] };
wire reserved_0 = 1'b0;
wire [2:0] m_data_width;
wire [2:0] s_data_width;
generate if(C_S_AXI_DATA_WIDTH == 32) begin : ATG_S_D_WIDTH_32
assign s_data_width = 3'b000;
end
endgenerate
generate if(C_S_AXI_DATA_WIDTH == 64) begin : ATG_S_D_WIDTH_64
assign s_data_width = 3'b001;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 32) begin : ATG_M_D_WIDTH_32
assign m_data_width = 3'b000;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 64) begin : ATG_M_D_WIDTH_64
assign m_data_width = 3'b001;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 128) begin : ATG_M_D_WIDTH_128
assign m_data_width = 3'b010;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 256) begin : ATG_M_D_WIDTH_256
assign m_data_width = 3'b011;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 512) begin : ATG_M_D_WIDTH_512
assign m_data_width = 3'b100;
end
endgenerate
wire mode_basic = (C_ATG_BASIC_AXI4 == 1 );
wire mode_static = (C_ATG_STATIC == 1 );
wire mode_slvonly = (C_ATG_SLAVE_ONLY == 1 );
wire mode_sysinit = (C_ATG_SYSTEM_INIT == 1 );
wire mode_streaming = (C_ATG_STREAMING == 1 );
wire mode_full = ~mode_basic && ~mode_static && ~mode_slvonly && ~mode_sysinit && ~mode_streaming;
wire [31:0] reg5_rd = { reserved_0 , //31
m_data_width , //30-28
s_data_width , //27-25
mode_full , //24
mode_basic , //23
mode_static , //22
mode_slvonly , //21
mode_sysinit , //20
mode_streaming, //19
{19 {reserved_0}}
};
//wire [31:0] reg7_rd = { slv_ex_info0_ff[63:40], slv_ex_info1[71:64] };
//wire [31:0] reg8_rd = slv_ex_info1_ff[63:32];
wire [31:0] reg7_rd = { 32'h0 };
wire [31:0] reg8_rd = 32'h0;
wire [31:0] reg9_rd = 32'h0;
wire [31:0] reg10_rd = 32'h0;
wire [31:0] reg11_rd = 32'h0;
assign rd_reg_data_raw =
((rd_reg_decode[0]) ? reg0_rd[31:0] : 32'h0) |
((rd_reg_decode[1]) ? reg1_rd[31:0] : 32'h0) |
((rd_reg_decode[2]) ? reg2_rd[31:0] : 32'h0) |
((rd_reg_decode[3]) ? reg3_rd[31:0] : 32'h0) |
((rd_reg_decode[4]) ? reg4_rd[31:0] : 32'h0) |
((rd_reg_decode[5]) ? reg5_rd[31:0] : 32'h0) |
((rd_reg_decode[6]) ? reg2_rd[31:0] : 32'h0) |
((rd_reg_decode[7]) ? reg7_rd[31:0] : 32'h0) |
((rd_reg_decode[8]) ? reg8_rd[31:0] : 32'h0) |
((rd_reg_decode[9]) ? reg9_rd[31:0] : 32'h0) |
((rd_reg_decode[10]) ? reg10_rd[31:0] : 32'h0) |
((rd_reg_decode[11]) ? reg11_rd[31:0] : 32'h0);
//controls to external modules
wire [1:0] reg1_awready_pause_sel = reg1_slvctl_ff[1:0];
wire [1:0] reg1_arready_pause_sel = reg1_slvctl_ff[3:2];
wire [1:0] reg1_wready_pause_sel = reg1_slvctl_ff[5:4];
wire [1:0] reg1_bvalid_pause_sel = reg1_slvctl_ff[7:6];
wire [1:0] reg1_rvalid_pause_sel = reg1_slvctl_ff[9:8];
wire [1:0] reg1_bfifo_pause_sel = reg1_slvctl_ff[11:10];
wire [1:0] reg1_rdata_pause_sel = reg1_slvctl_ff[13:12];
wire reg1_errsig_enable = reg1_slvctl_ff[15];
assign reg1_sgl_slv_rd = reg1_slvctl_ff[16];
assign reg1_sgl_slv_wr = reg1_slvctl_ff[17];
assign reg1_disallow_excl = reg1_slvctl_ff[18];
assign reg1_wrs_block_rds = reg1_slvctl_ff[19];
wire [1:0] reg4_awvalid_pause_sel = reg4_mstctl_ff[1:0];
wire [1:0] reg4_arvalid_pause_sel = reg4_mstctl_ff[3:2];
wire [1:0] reg4_wvalid_pause_sel = reg4_mstctl_ff[5:4];
wire [1:0] reg4_bready_pause_sel = reg4_mstctl_ff[7:6];
wire [1:0] reg4_rready_pause_sel = reg4_mstctl_ff[9:8];
wire reg4_errsig_enable = reg4_mstctl_ff[15];
wire [3:0] dbg_pause;
// grahams : removing for timing closure
assign dbg_pause = 0;
//for Master logic
axi_traffic_gen_v2_0_regslice
#(
.DWIDTH (1 ),
.IDWIDTH (1 ),
.DATADEPTH(`REGSLICE_CMDRAM_MR_REGENABLE),
.IDDEPTH (1 )
)
regenable_regslice
(
.din (reg0_m_enable ),
.dout (reg0_m_enable_cmdram_mrw_ff),
.dout_early (reg0_m_enable_cmdram_mrw ),
.idin (1'b0 ),
.idout ( ),
.id_stable ( ),
.id_stable_ff ( ),
.data_stable ( ),
.clk (Clk ),
.reset (~rst_l )
);
//error updates from master-write path
wire err_detect_slv = reg1_errsig_enable && (reg2_err_ff[15:0] != 16'h0);
wire err_detect_mst = reg4_errsig_enable && (reg2_err_ff[30:16] != 15'h0);
wire err_detect = err_detect_slv || err_detect_mst;
reg err_detect_ff;
always @(posedge Clk) begin
err_detect_ff <= (rst_l) ? err_detect : 1'b0;
end
assign err_out = err_detect_ff;
assign irq_out = reg2_err_ff[31];
assign err_new_mst[31:16] = { reg0_m_disable, 7'h0,
3'b000, mr_unexp,
b_resp_unexp_ff, b_resp_bad_ff,
mr_fifo_out_resp_bad, mr_bad_last_ff };
endmodule
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Stratix IV" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 11.0SP1 cbx_altiobuf_out 2011:07:03:21:10:33:SJ cbx_mgl 2011:07:03:21:11:41:SJ cbx_stratixiii 2011:07:03:21:10:33:SJ cbx_stratixv 2011:07:03:21:10:33:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = stratixiv_io_obuf 2 stratixiv_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module ddr3_s4_uniphy_example_if0_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obufa_o;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] oe_b;
wire [0:0] oe_w;
stratixiv_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(oe_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({14{1'b0}}),
.seriesterminationcontrol({14{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "stratixiv_io_obuf";
stratixiv_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(oe_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({14{1'b0}}),
.seriesterminationcontrol({14{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.shift_series_termination_control = "false",
obufa_0.lpm_type = "stratixiv_io_obuf";
stratixiv_pseudo_diff_out pseudo_diffa_0
(
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]));
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_b = 1'b1,
oe_w = 1'b1;
endmodule //ddr3_s4_uniphy_example_if0_p0_clock_pair_generator
//VALID FILE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__OR4_FUNCTIONAL_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__or4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4_FUNCTIONAL_V |
(** * MoreCoq: More About Coq's Tactics *)
Require Export Poly.
(** This chapter introduces several more proof strategies and
tactics that, together, allow us to prove theorems about the
functional programs we have been writing. In particular, we'll
reason about functions that work with natural numbers and lists.
In particular, we will see:
- how to use auxiliary lemmas, in both forwards and backwards reasoning;
- how to reason about data constructors, which are injective and disjoint;
- how to create a strong induction hypotheses (and when
strengthening is required); and
- how to reason by case analysis.
*)
(* ###################################################### *)
(** * The [apply] Tactic *)
(** We often encounter situations where the goal to be proved is
exactly the same as some hypothesis in the context or some
previously proved lemma. *)
Theorem silly1 : forall (n m o p : nat),
n = m ->
[n;o] = [n;p] ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
rewrite <- eq1.
(* At this point, we could finish with
"[rewrite -> eq2. reflexivity.]" as we have
done several times above. But we can achieve the
same effect in a single step by using the
[apply] tactic instead: *)
apply eq2. Qed.
(** The [apply] tactic also works with _conditional_ hypotheses
and lemmas: if the statement being applied is an implication, then
the premises of this implication will be added to the list of
subgoals needing to be proved. *)
Theorem silly2 : forall (n m o p : nat),
n = m ->
(forall (q r : nat), q = r -> [q;o] = [r;p]) ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
(*rewrite <- eq1.
rewrite (eq2 n n).
reflexivity.
reflexivity.*)
apply eq2. apply eq1. Qed.
(** You may find it instructive to experiment with this proof
and see if there is a way to complete it using just [rewrite]
instead of [apply]. *)
(** Typically, when we use [apply H], the statement [H] will
begin with a [forall] binding some _universal variables_. When
Coq matches the current goal against the conclusion of [H], it
will try to find appropriate values for these variables. For
example, when we do [apply eq2] in the following proof, the
universal variable [q] in [eq2] gets instantiated with [n] and [r]
gets instantiated with [m]. *)
Theorem silly2a : forall (n m : nat),
(n,n) = (m,m) ->
(forall (q r : nat), (q,q) = (r,r) -> [q] = [r]) ->
[n] = [m].
Proof.
intros n m eq1 eq2.
apply eq2. apply eq1. Qed.
(** **** Exercise: 2 stars, optional (silly_ex) *)
(** Complete the following proof without using [simpl]. *)
Theorem silly_ex :
(forall n, evenb n = true -> oddb (S n) = true) ->
evenb 3 = true ->
oddb 4 = true.
Proof.
intros H H0.
apply H0.
Qed.
(** [] *)
(** To use the [apply] tactic, the (conclusion of the) fact
being applied must match the goal _exactly_ -- for example, [apply]
will not work if the left and right sides of the equality are
swapped. *)
Theorem silly3_firsttry : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
simpl.
(* Here we cannot use [apply] directly *)
Abort.
(** In this case we can use the [symmetry] tactic, which switches the
left and right sides of an equality in the goal. *)
Theorem silly3 : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
symmetry.
simpl. (* Actually, this [simpl] is unnecessary, since
[apply] will perform simplification first. *)
apply H. Qed.
(** **** Exercise: 3 stars (apply_exercise1) *)
(** Hint: you can use [apply] with previously defined lemmas, not
just hypotheses in the context. Remember that [SearchAbout] is
your friend. *)
Theorem rev_exercise1 : forall (l l' : list nat),
l = rev l' ->
l' = rev l.
Proof.
intros l l' H.
symmetry.
rewrite H.
apply rev_involutive.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (apply_rewrite) *)
(** Briefly explain the difference between the tactics [apply] and
[rewrite]. Are there situations where both can usefully be
applied?
Rewrite takes an equality to rewrite the current goal.
Apply basically uses rewrite with a few extra smarts (calls simpl)
*)
(** [] *)
(* ###################################################### *)
(** * The [apply ... with ...] Tactic *)
(** The following silly example uses two rewrites in a row to
get from [[a,b]] to [[e,f]]. *)
Example trans_eq_example : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
rewrite -> eq1. rewrite -> eq2. reflexivity. Qed.
(** Since this is a common pattern, we might
abstract it out as a lemma recording once and for all
the fact that equality is transitive. *)
Theorem trans_eq : forall (X:Type) (n m o : X),
n = m -> m = o -> n = o.
Proof.
intros X n m o eq1 eq2. rewrite -> eq1. rewrite -> eq2.
reflexivity. Qed.
(** Now, we should be able to use [trans_eq] to
prove the above example. However, to do this we need
a slight refinement of the [apply] tactic. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
(* If we simply tell Coq [apply trans_eq] at this point,
it can tell (by matching the goal against the
conclusion of the lemma) that it should instantiate [X]
with [[nat]], [n] with [[a,b]], and [o] with [[e,f]].
However, the matching process doesn't determine an
instantiation for [m]: we have to supply one explicitly
by adding [with (m:=[c,d])] to the invocation of
[apply]. *)
apply trans_eq with (m:=[c;d]). apply eq1. apply eq2. Qed.
(** Actually, we usually don't have to include the name [m]
in the [with] clause; Coq is often smart enough to
figure out which instantiation we're giving. We could
instead write: [apply trans_eq with [c,d]]. *)
(** **** Exercise: 3 stars, optional (apply_with_exercise) *)
Example trans_eq_exercise : forall (n m o p : nat),
m = (minustwo o) ->
(n + p) = m ->
(n + p) = (minustwo o).
Proof.
intros n m o mm2 npm npm2.
apply trans_eq with m.
apply npm2.
apply npm.
Qed.
(** [] *)
(* ###################################################### *)
(** * The [inversion] tactic *)
(** Recall the definition of natural numbers:
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
It is clear from this definition that every number has one of two
forms: either it is the constructor [O] or it is built by applying
the constructor [S] to another number. But there is more here than
meets the eye: implicit in the definition (and in our informal
understanding of how datatype declarations work in other
programming languages) are two other facts:
- The constructor [S] is _injective_. That is, the only way we can
have [S n = S m] is if [n = m].
- The constructors [O] and [S] are _disjoint_. That is, [O] is not
equal to [S n] for any [n]. *)
(** Similar principles apply to all inductively defined types: all
constructors are injective, and the values built from distinct
constructors are never equal. For lists, the [cons] constructor is
injective and [nil] is different from every non-empty list. For
booleans, [true] and [false] are unequal. (Since neither [true]
nor [false] take any arguments, their injectivity is not an issue.) *)
(** Coq provides a tactic called [inversion] that allows us to exploit
these principles in proofs.
The [inversion] tactic is used like this. Suppose [H] is a
hypothesis in the context (or a previously proven lemma) of the
form
c a1 a2 ... an = d b1 b2 ... bm
for some constructors [c] and [d] and arguments [a1 ... an] and
[b1 ... bm]. Then [inversion H] instructs Coq to "invert" this
equality to extract the information it contains about these terms:
- If [c] and [d] are the same constructor, then we know, by the
injectivity of this constructor, that [a1 = b1], [a2 = b2],
etc.; [inversion H] adds these facts to the context, and tries
to use them to rewrite the goal.
- If [c] and [d] are different constructors, then the hypothesis
[H] is contradictory. That is, a false assumption has crept
into the context, and this means that any goal whatsoever is
provable! In this case, [inversion H] marks the current goal as
completed and pops it off the goal stack. *)
(** The [inversion] tactic is probably easier to understand by
seeing it in action than from general descriptions like the above.
Below you will find example theorems that demonstrate the use of
[inversion] and exercises to test your understanding. *)
Theorem eq_add_S : forall (n m : nat),
S n = S m ->
n = m.
Proof.
intros n m eq. inversion eq. reflexivity. Qed.
Theorem silly4 : forall (n m : nat),
[n] = [m] ->
n = m.
Proof.
intros n o eq. inversion eq. reflexivity. Qed.
(** As a convenience, the [inversion] tactic can also
destruct equalities between complex values, binding
multiple variables as it goes. *)
Theorem silly5 : forall (n m o : nat),
[n;m] = [o;o] ->
[n] = [m].
Proof.
intros n m o eq. inversion eq. reflexivity. Qed.
(** **** Exercise: 1 star (sillyex1) *)
Example sillyex1 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = z :: j ->
y :: l = x :: j ->
x = y.
Proof.
intros.
inversion H0.
reflexivity.
Qed.
(** [] *)
Theorem silly6 : forall (n : nat),
S n = O ->
2 + 2 = 5.
Proof.
intros n contra. inversion contra. Qed.
Theorem silly7 : forall (n m : nat),
false = true ->
[n] = [m].
Proof.
intros n m contra. inversion contra. Qed.
(** **** Exercise: 1 star (sillyex2) *)
Example sillyex2 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = [] ->
y :: l = z :: j ->
x = z.
Proof.
intros X x y z l j contra H.
inversion contra.
Qed.
(** [] *)
(** While the injectivity of constructors allows us to reason
[forall (n m : nat), S n = S m -> n = m], the reverse direction of
the implication is an instance of a more general fact about
constructors and functions, which we will often find useful: *)
Theorem f_equal : forall (A B : Type) (f: A -> B) (x y: A),
x = y -> f x = f y.
Proof. intros A B f x y eq. rewrite eq. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (practice) *)
(** A couple more nontrivial but not-too-complicated proofs to work
together in class, or for you to work as exercises. *)
Theorem beq_nat_0_l : forall n,
beq_nat 0 n = true -> n = 0.
Proof.
intros.
inversion H.
destruct n.
reflexivity.
inversion H1.
Qed.
Theorem beq_nat_0_r : forall n,
beq_nat n 0 = true -> n = 0.
Proof.
intros.
destruct n.
reflexivity.
inversion H.
Qed.
(** [] *)
(* ###################################################### *)
(** * Using Tactics on Hypotheses *)
(** By default, most tactics work on the goal formula and leave
the context unchanged. However, most tactics also have a variant
that performs a similar operation on a statement in the context.
For example, the tactic [simpl in H] performs simplification in
the hypothesis named [H] in the context. *)
Theorem S_inj : forall (n m : nat) (b : bool),
beq_nat (S n) (S m) = b ->
beq_nat n m = b.
Proof.
intros n m b H. simpl in H. apply H. Qed.
(** Similarly, the tactic [apply L in H] matches some
conditional statement [L] (of the form [L1 -> L2], say) against a
hypothesis [H] in the context. However, unlike ordinary
[apply] (which rewrites a goal matching [L2] into a subgoal [L1]),
[apply L in H] matches [H] against [L1] and, if successful,
replaces it with [L2].
In other words, [apply L in H] gives us a form of "forward
reasoning" -- from [L1 -> L2] and a hypothesis matching [L1], it
gives us a hypothesis matching [L2]. By contrast, [apply L] is
"backward reasoning" -- it says that if we know [L1->L2] and we
are trying to prove [L2], it suffices to prove [L1].
Here is a variant of a proof from above, using forward reasoning
throughout instead of backward reasoning. *)
Theorem silly3' : forall (n : nat),
(beq_nat n 5 = true -> beq_nat (S (S n)) 7 = true) ->
true = beq_nat n 5 ->
true = beq_nat (S (S n)) 7.
Proof.
intros n eq H.
symmetry in H. apply eq in H. symmetry in H.
apply H. Qed.
(** Forward reasoning starts from what is _given_ (premises,
previously proven theorems) and iteratively draws conclusions from
them until the goal is reached. Backward reasoning starts from
the _goal_, and iteratively reasons about what would imply the
goal, until premises or previously proven theorems are reached.
If you've seen informal proofs before (for example, in a math or
computer science class), they probably used forward reasoning. In
general, Coq tends to favor backward reasoning, but in some
situations the forward style can be easier to use or to think
about. *)
(** **** Exercise: 3 stars (plus_n_n_injective) *)
(** Practice using "in" variants in this exercise. *)
Theorem plus_n_n_injective : forall n m,
n + n = m + m ->
n = m.
Proof.
intros n. induction n as [| n'].
(* Case n = 0 *)
intros.
destruct m.
simpl in H.
reflexivity.
simpl in H.
inversion H.
(* Case n = S n' *)
intros.
simpl in H.
simpl in H.
(* Hint: use the plus_n_Sm lemma *)
(* plus_n_Sm: forall n m : nat, S (n + m) = n + S m *)
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Varying the Induction Hypothesis *)
(** Sometimes it is important to control the exact form of the
induction hypothesis when carrying out inductive proofs in Coq.
In particular, we need to be careful about which of the
assumptions we move (using [intros]) from the goal to the context
before invoking the [induction] tactic. For example, suppose
we want to show that the [double] function is injective -- i.e.,
that it always maps different arguments to different results:
Theorem double_injective: forall n m, double n = double m -> n = m.
The way we _start_ this proof is a little bit delicate: if we
begin it with
intros n. induction n.
]]
all is well. But if we begin it with
intros n m. induction n.
we get stuck in the middle of the inductive case... *)
Theorem double_injective_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction n as [| n'].
Case "n = O". simpl. intros eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'". intros eq. destruct m as [| m'].
SCase "m = O". inversion eq.
SCase "m = S m'". apply f_equal.
(* Here we are stuck. The induction hypothesis, [IHn'], does
not give us [n' = m'] -- there is an extra [S] in the
way -- so the goal is not provable. *)
Abort.
(** What went wrong? *)
(** The problem is that, at the point we invoke the induction
hypothesis, we have already introduced [m] into the context --
intuitively, we have told Coq, "Let's consider some particular
[n] and [m]..." and we now have to prove that, if [double n =
double m] for _this particular_ [n] and [m], then [n = m].
The next tactic, [induction n] says to Coq: We are going to show
the goal by induction on [n]. That is, we are going to prove that
the proposition
- [P n] = "if [double n = double m], then [n = m]"
holds for all [n] by showing
- [P O]
(i.e., "if [double O = double m] then [O = m]")
- [P n -> P (S n)]
(i.e., "if [double n = double m] then [n = m]" implies "if
[double (S n) = double m] then [S n = m]").
If we look closely at the second statement, it is saying something
rather strange: it says that, for a _particular_ [m], if we know
- "if [double n = double m] then [n = m]"
then we can prove
- "if [double (S n) = double m] then [S n = m]".
To see why this is strange, let's think of a particular [m] --
say, [5]. The statement is then saying that, if we know
- [Q] = "if [double n = 10] then [n = 5]"
then we can prove
- [R] = "if [double (S n) = 10] then [S n = 5]".
But knowing [Q] doesn't give us any help with proving [R]! (If we
tried to prove [R] from [Q], we would say something like "Suppose
[double (S n) = 10]..." but then we'd be stuck: knowing that
[double (S n)] is [10] tells us nothing about whether [double n]
is [10], so [Q] is useless at this point.) *)
(** To summarize: Trying to carry out this proof by induction on [n]
when [m] is already in the context doesn't work because we are
trying to prove a relation involving _every_ [n] but just a
_single_ [m]. *)
(** The good proof of [double_injective] leaves [m] in the goal
statement at the point where the [induction] tactic is invoked on
[n]: *)
Theorem double_injective : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
Case "n = O". simpl. intros m eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'".
(* Notice that both the goal and the induction
hypothesis have changed: the goal asks us to prove
something more general (i.e., to prove the
statement for _every_ [m]), but the IH is
correspondingly more flexible, allowing us to
choose any [m] we like when we apply the IH. *)
intros m eq.
(* Now we choose a particular [m] and introduce the
assumption that [double n = double m]. Since we
are doing a case analysis on [n], we need a case
analysis on [m] to keep the two "in sync." *)
destruct m as [| m'].
SCase "m = O".
(* The 0 case is trivial *)
inversion eq.
SCase "m = S m'".
apply f_equal.
(* At this point, since we are in the second
branch of the [destruct m], the [m'] mentioned
in the context at this point is actually the
predecessor of the one we started out talking
about. Since we are also in the [S] branch of
the induction, this is perfect: if we
instantiate the generic [m] in the IH with the
[m'] that we are talking about right now (this
instantiation is performed automatically by
[apply]), then [IHn'] gives us exactly what we
need to finish the proof. *)
apply IHn'. inversion eq. reflexivity. Qed.
(** What this teaches us is that we need to be careful about using
induction to try to prove something too specific: If we're proving
a property of [n] and [m] by induction on [n], we may need to
leave [m] generic. *)
(** The proof of this theorem (left as an exercise) has to be treated similarly: *)
(** **** Exercise: 2 stars (beq_nat_true) *)
Theorem beq_nat_true : forall n m,
beq_nat n m = true -> n = m.
Proof.
intro n.
induction n.
intros.
destruct m.
reflexivity.
inversion H.
intros.
destruct m.
inversion H.
Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (beq_nat_true_informal) *)
(** Give a careful informal proof of [beq_nat_true], being as explicit
as possible about quantifiers. *)
(* FILL IN HERE *)
(** [] *)
(** The strategy of doing fewer [intros] before an [induction] doesn't
always work directly; sometimes a little _rearrangement_ of
quantified variables is needed. Suppose, for example, that we
wanted to prove [double_injective] by induction on [m] instead of
[n]. *)
Theorem double_injective_take2_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction m as [| m'].
Case "m = O". simpl. intros eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
(* Stuck again here, just like before. *)
Abort.
(** The problem is that, to do induction on [m], we must first
introduce [n]. (If we simply say [induction m] without
introducing anything first, Coq will automatically introduce
[n] for us!) *)
(** What can we do about this? One possibility is to rewrite the
statement of the lemma so that [m] is quantified before [n]. This
will work, but it's not nice: We don't want to have to mangle the
statements of lemmas to fit the needs of a particular strategy for
proving them -- we want to state them in the most clear and
natural way. *)
(** What we can do instead is to first introduce all the
quantified variables and then _re-generalize_ one or more of
them, taking them out of the context and putting them back at
the beginning of the goal. The [generalize dependent] tactic
does this. *)
Theorem double_injective_take2 : forall n m,
double n = double m ->
n = m.
Proof.
intros n m.
(* [n] and [m] are both in the context *)
generalize dependent n.
(* Now [n] is back in the goal and we can do induction on
[m] and get a sufficiently general IH. *)
induction m as [| m'].
Case "m = O". simpl. intros n eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros n eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
apply IHm'. inversion eq. reflexivity. Qed.
(** Let's look at an informal proof of this theorem. Note that
the proposition we prove by induction leaves [n] quantified,
corresponding to the use of generalize dependent in our formal
proof.
_Theorem_: For any nats [n] and [m], if [double n = double m], then
[n = m].
_Proof_: Let [m] be a [nat]. We prove by induction on [m] that, for
any [n], if [double n = double m] then [n = m].
- First, suppose [m = 0], and suppose [n] is a number such
that [double n = double m]. We must show that [n = 0].
Since [m = 0], by the definition of [double] we have [double n =
0]. There are two cases to consider for [n]. If [n = 0] we are
done, since this is what we wanted to show. Otherwise, if [n = S
n'] for some [n'], we derive a contradiction: by the definition of
[double] we would have [double n = S (S (double n'))], but this
contradicts the assumption that [double n = 0].
- Otherwise, suppose [m = S m'] and that [n] is again a number such
that [double n = double m]. We must show that [n = S m'], with
the induction hypothesis that for every number [s], if [double s =
double m'] then [s = m'].
By the fact that [m = S m'] and the definition of [double], we
have [double n = S (S (double m'))]. There are two cases to
consider for [n].
If [n = 0], then by definition [double n = 0], a contradiction.
Thus, we may assume that [n = S n'] for some [n'], and again by
the definition of [double] we have [S (S (double n')) = S (S
(double m'))], which implies by inversion that [double n' = double
m'].
Instantiating the induction hypothesis with [n'] thus allows us to
conclude that [n' = m'], and it follows immediately that [S n' = S
m']. Since [S n' = n] and [S m' = m], this is just what we wanted
to show. [] *)
(** Here's another illustration of [inversion] and using an
appropriately general induction hypothesis. This is a slightly
roundabout way of stating a fact that we have already proved
above. The extra equalities force us to do a little more
equational reasoning and exercise some of the tactics we've seen
recently. *)
Theorem length_snoc' : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l. induction l as [| v' l'].
Case "l = []".
intros n eq. rewrite <- eq. reflexivity.
Case "l = v' :: l'".
intros n eq. simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. apply IHl'. inversion eq. reflexivity. Qed.
(** It might be tempting to start proving the above theorem
by introducing [n] and [eq] at the outset. However, this leads
to an induction hypothesis that is not strong enough. Compare
the above to the following (aborted) attempt: *)
Theorem length_snoc_bad : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l n eq. induction l as [| v' l'].
Case "l = []".
rewrite <- eq. reflexivity.
Case "l = v' :: l'".
simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. Abort. (* apply IHl'. *) (* The IH doesn't apply! *)
(** As in the double examples, the problem is that by
introducing [n] before doing induction on [l], the induction
hypothesis is specialized to one particular natural number, namely
[n]. In the induction case, however, we need to be able to use
the induction hypothesis on some other natural number [n'].
Retaining the more general form of the induction hypothesis thus
gives us more flexibility.
In general, a good rule of thumb is to make the induction hypothesis
as general as possible. *)
(** **** Exercise: 3 stars (gen_dep_practice) *)
(** Prove this by induction on [l]. *)
Theorem index_after_last: forall (n : nat) (X : Type) (l : list X),
length l = n ->
index n l = None.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (index_after_last_informal) *)
(** Write an informal proof corresponding to your Coq proof
of [index_after_last]:
_Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index n l = None].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (gen_dep_practice_more) *)
(** Prove this by induction on [l]. *)
Theorem length_snoc''' : forall (n : nat) (X : Type)
(v : X) (l : list X),
length l = n ->
length (snoc l v) = S n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (app_length_cons) *)
(** Prove this by induction on [l1], without using [app_length]
from [Lists]. *)
Theorem app_length_cons : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
length (l1 ++ (x :: l2)) = n ->
S (length (l1 ++ l2)) = n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, optional (app_length_twice) *)
(** Prove this by induction on [l], without using app_length. *)
Theorem app_length_twice : forall (X:Type) (n:nat) (l:list X),
length l = n ->
length (l ++ l) = n + n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (double_induction) *)
(** Prove the following principle of induction over two naturals. *)
Theorem double_induction: forall (P : nat -> nat -> Prop),
P 0 0 ->
(forall m, P m 0 -> P (S m) 0) ->
(forall n, P 0 n -> P 0 (S n)) ->
(forall m n, P m n -> P (S m) (S n)) ->
forall m n, P m n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Using [destruct] on Compound Expressions *)
(** We have seen many examples where the [destruct] tactic is
used to perform case analysis of the value of some variable. But
sometimes we need to reason by cases on the result of some
_expression_. We can also do this with [destruct].
Here are some examples: *)
Definition sillyfun (n : nat) : bool :=
if beq_nat n 3 then false
else if beq_nat n 5 then false
else false.
Theorem sillyfun_false : forall (n : nat),
sillyfun n = false.
Proof.
intros n. unfold sillyfun.
destruct (beq_nat n 3).
Case "beq_nat n 3 = true". reflexivity.
Case "beq_nat n 3 = false". destruct (beq_nat n 5).
SCase "beq_nat n 5 = true". reflexivity.
SCase "beq_nat n 5 = false". reflexivity. Qed.
Definition dumbfun (n : nat) : bool :=
if beq_nat n 10 then true
else if beq_nat n 20 then false
else false.
Theorem dumb_fun_true :
dumbfun 10 = true.
Proof.
unfold dumbfun. destruct (beq_nat 10 10) eqn: Foo.
unfold beq_nat in Foo.
reflexivity.
unfold beq_nat in Foo.
inversion Foo.
Qed.
(** After unfolding [sillyfun] in the above proof, we find that
we are stuck on [if (beq_nat n 3) then ... else ...]. Well,
either [n] is equal to [3] or it isn't, so we use [destruct
(beq_nat n 3)] to let us reason about the two cases.
In general, the [destruct] tactic can be used to perform case
analysis of the results of arbitrary computations. If [e] is an
expression whose type is some inductively defined type [T], then,
for each constructor [c] of [T], [destruct e] generates a subgoal
in which all occurrences of [e] (in the goal and in the context)
are replaced by [c].
*)
(** **** Exercise: 1 star (override_shadow) *)
Theorem override_shadow : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override (override f k1 x2) k1 x1) k2 = (override f k1 x1) k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (combine_split) *)
(** Complete the proof below *)
Theorem combine_split : forall X Y (l : list (X * Y)) l1 l2,
split l = (l1, l2) ->
combine l1 l2 = l.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Sometimes, doing a [destruct] on a compound expression (a
non-variable) will erase information we need to complete a proof. *)
(** For example, suppose
we define a function [sillyfun1] like this: *)
Definition sillyfun1 (n : nat) : bool :=
if beq_nat n 3 then true
else if beq_nat n 5 then true
else false.
(** And suppose that we want to convince Coq of the rather
obvious observation that [sillyfun1 n] yields [true] only when [n]
is odd. By analogy with the proofs we did with [sillyfun] above,
it is natural to start the proof like this: *)
Theorem sillyfun1_odd_FAILED : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3).
(* stuck... *)
Abort.
(** We get stuck at this point because the context does not
contain enough information to prove the goal! The problem is that
the substitution peformed by [destruct] is too brutal -- it threw
away every occurrence of [beq_nat n 3], but we need to keep some
memory of this expression and how it was destructed, because we
need to be able to reason that since, in this branch of the case
analysis, [beq_nat n 3 = true], it must be that [n = 3], from
which it follows that [n] is odd.
What we would really like is to substitute away all existing
occurences of [beq_nat n 3], but at the same time add an equation
to the context that records which case we are in. The [eqn:]
qualifier allows us to introduce such an equation (with whatever
name we choose). *)
Theorem sillyfun1_odd : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3) eqn:Heqe3.
(* Now we have the same state as at the point where we got stuck
above, except that the context contains an extra equality
assumption, which is exactly what we need to make progress. *)
Case "e3 = true". apply beq_nat_true in Heqe3.
rewrite -> Heqe3. reflexivity.
Case "e3 = false".
(* When we come to the second equality test in the body of the
function we are reasoning about, we can use [eqn:] again in the
same way, allow us to finish the proof. *)
destruct (beq_nat n 5) eqn:Heqe5.
SCase "e5 = true".
apply beq_nat_true in Heqe5.
rewrite -> Heqe5. reflexivity.
SCase "e5 = false". inversion eq. Qed.
(** **** Exercise: 2 stars (destruct_eqn_practice) *)
Theorem bool_fn_applied_thrice :
forall (f : bool -> bool) (b : bool),
f (f (f b)) = f b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (override_same) *)
Theorem override_same : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override f k1 x1) k2 = f k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################## *)
(** * Review *)
(** We've now seen a bunch of Coq's fundamental tactics. We'll
introduce a few more as we go along through the coming lectures,
and later in the course we'll introduce some more powerful
_automation_ tactics that make Coq do more of the low-level work
in many cases. But basically we've got what we need to get work
done.
Here are the ones we've seen:
- [intros]:
move hypotheses/variables from goal to context
- [reflexivity]:
finish the proof (when the goal looks like [e = e])
- [apply]:
prove goal using a hypothesis, lemma, or constructor
- [apply... in H]:
apply a hypothesis, lemma, or constructor to a hypothesis in
the context (forward reasoning)
- [apply... with...]:
explicitly specify values for variables that cannot be
determined by pattern matching
- [simpl]:
simplify computations in the goal
- [simpl in H]:
... or a hypothesis
- [rewrite]:
use an equality hypothesis (or lemma) to rewrite the goal
- [rewrite ... in H]:
... or a hypothesis
- [symmetry]:
changes a goal of the form [t=u] into [u=t]
- [symmetry in H]:
changes a hypothesis of the form [t=u] into [u=t]
- [unfold]:
replace a defined constant by its right-hand side in the goal
- [unfold... in H]:
... or a hypothesis
- [destruct... as...]:
case analysis on values of inductively defined types
- [destruct... eqn:...]:
specify the name of an equation to be added to the context,
recording the result of the case analysis
- [induction... as...]:
induction on values of inductively defined types
- [inversion]:
reason by injectivity and distinctness of constructors
- [assert (e) as H]:
introduce a "local lemma" [e] and call it [H]
- [generalize dependent x]:
move the variable [x] (and anything else that depends on it)
from the context back to an explicit hypothesis in the goal
formula
*)
(* ###################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (beq_nat_sym) *)
Theorem beq_nat_sym : forall (n m : nat),
beq_nat n m = beq_nat m n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (beq_nat_sym_informal) *)
(** Give an informal proof of this lemma that corresponds to your
formal proof above:
Theorem: For any [nat]s [n] [m], [beq_nat n m = beq_nat m n].
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (beq_nat_trans) *)
Theorem beq_nat_trans : forall n m p,
beq_nat n m = true ->
beq_nat m p = true ->
beq_nat n p = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (split_combine) *)
(** We have just proven that for all lists of pairs, [combine] is the
inverse of [split]. How would you formalize the statement that
[split] is the inverse of [combine]? When is this property true?
Complete the definition of [split_combine_statement] below with a
property that states that [split] is the inverse of
[combine]. Then, prove that the property holds. (Be sure to leave
your induction hypothesis general by not doing [intros] on more
things than necessary. Hint: what property do you need of [l1]
and [l2] for [split] [combine l1 l2 = (l1,l2)] to be true?) *)
Definition split_combine_statement : Prop :=
(* FILL IN HERE *) admit.
Theorem split_combine : split_combine_statement.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (override_permute) *)
Theorem override_permute : forall (X:Type) x1 x2 k1 k2 k3 (f : nat->X),
beq_nat k2 k1 = false ->
(override (override f k2 x2) k1 x1) k3 = (override (override f k1 x1) k2 x2) k3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (filter_exercise) *)
(** This one is a bit challenging. Pay attention to the form of your IH. *)
Theorem filter_exercise : forall (X : Type) (test : X -> bool)
(x : X) (l lf : list X),
filter test l = x :: lf ->
test x = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced (forall_exists_challenge) *)
(** Define two recursive [Fixpoints], [forallb] and [existsb]. The
first checks whether every element in a list satisfies a given
predicate:
forallb oddb [1;3;5;7;9] = true
forallb negb [false;false] = true
forallb evenb [0;2;4;5] = false
forallb (beq_nat 5) [] = true
The second checks whether there exists an element in the list that
satisfies a given predicate:
existsb (beq_nat 5) [0;2;3;6] = false
existsb (andb true) [true;true;false] = true
existsb oddb [1;0;0;0;0;3] = true
existsb evenb [] = false
Next, define a _nonrecursive_ version of [existsb] -- call it
[existsb'] -- using [forallb] and [negb].
Prove theorem [existsb_existsb'] that [existsb'] and [existsb] have
the same behavior.
*)
(* FILL IN HERE *)
(** [] *)
(** $Date: 2014-12-31 16:01:37 -0500 (Wed, 31 Dec 2014) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1P_LP_V
`define SKY130_FD_SC_LP__INPUTISO1P_LP_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog wrapper for inputiso1p with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inputiso1p.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inputiso1p_lp (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__inputiso1p base (
.X(X),
.A(A),
.SLEEP(SLEEP),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inputiso1p_lp (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__inputiso1p base (
.X(X),
.A(A),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1P_LP_V
|
/*
-- ============================================================================
-- FILE NAME : chip_top.v
-- DESCRIPTION : ¶¥²ãÄ£¿é
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ´´½¨
-- 1.0.1 2014/06/27 zhangly
-- ============================================================================
*/
/********** ͨÓÃÍ·Îļþ **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** ÏîÄ¿Í·Îļþ **********/
`include "gpio.h"
/********** Ä£¿é **********/
module chip_top (
/********** ʱÖÓÓ븴λ **********/
input wire clk_ref, // »ù±¾Ê±ÖÓ
input wire reset_sw // È«¾Ö¸´Î»£¬È±Ê¡¶¨ÒåΪ¸ºÂß¼,¼ûglobal_config.h
/********** UART **********/
`ifdef IMPLEMENT_UART // UARTʵÏÖ
, input wire uart_rx // UART½ÓÊÕÐźÅ
, output wire uart_tx // UART·¢ËÍÐźÅ
`endif
/********** ͨÓÃI/ O¶Ë¿Ú **********/
`ifdef IMPLEMENT_GPIO // GPIOʵÏÖ
`ifdef GPIO_IN_CH //ÊäÈë½Ó¿ÚʵÏÖ
, input wire [`GPIO_IN_CH-1:0] gpio_in // ÊäÈë½Ó¿Ú
`endif
`ifdef GPIO_OUT_CH // Êä³ö½Ó¿ÚʵÏÖ
, output wire [`GPIO_OUT_CH-1:0] gpio_out // Êä³ö½Ó¿Ú
`endif
`ifdef GPIO_IO_CH // ÊäÈëÊä³ö½Ó¿ÚʵÏÖ
, inout wire [`GPIO_IO_CH-1:0] gpio_io // ÊäÈëÊä³ö½Ó¿Ú
`endif
`endif
);
/********** ʱÖÓÓ븴λ **********/
wire clk; // ʱÖÓ
wire clk_; // ·´ÏàʱÖÓ
wire chip_reset; // ¸´Î»
/********** ʱÖÓÄ£¿é **********/
clk_gen clk_gen (
/********** ʱÖÓÓ븴λ **********/
.clk_ref (clk_ref), // »ù±¾Ê±ÖÓ
.reset_sw (reset_sw), // È«¾Ö¸´Î»
/********** Éú³ÉʱÖÓ **********/
.clk (clk), // ʱÖÓ
.clk_ (clk_), // ·´ÏòʱÖÓ
/********** ¸´Î» **********/
.chip_reset (chip_reset) // ¸´Î»
);
/********** оƬ **********/
chip chip (
/********** ʱÖÓÓ븴λ **********/
.clk (clk), // ʱÖÓ
.clk_ (clk_), // ·´ÏòʱÖÓ
.reset (chip_reset) // ¸´Î»
/********** UART **********/
`ifdef IMPLEMENT_UART
, .uart_rx (uart_rx) // UART½ÓÊÕÐźÅ
, .uart_tx (uart_tx) // UART·¢ËÍÐźÅ
`endif
/********** GPIO **********/
`ifdef IMPLEMENT_GPIO
`ifdef GPIO_IN_CH // ÊäÈë½Ó¿ÚʵÏÖ
, .gpio_in (gpio_in) // ÊäÈë½Ó¿Ú
`endif
`ifdef GPIO_OUT_CH // Êä³ö½Ó¿ÚʵÏÖ
, .gpio_out (gpio_out) // Êä³ö½Ó¿Ú
`endif
`ifdef GPIO_IO_CH // ÊäÈëÊä³ö½Ó¿ÚʵÏÖ
, .gpio_io (gpio_io) // ÊäÈëÊä³ö½Ó¿Ú
`endif
`endif
);
endmodule
|
`default_nettype none
//---------------------------------------------------------------------
//-- --
//-- Company: University of Bonn --
//-- Engineer: John Bieling --
//-- --
//---------------------------------------------------------------------
//-- --
//-- Copyright (C) 2015 John Bieling --
//-- --
//-- This program is free software; you can redistribute it and/or --
//-- modify it under the terms of the GNU General Public License as --
//-- published by the Free Software Foundation; either version 3 of --
//-- the License, or (at your option) any later version. --
//-- --
//-- This program is distributed in the hope that it will be useful, --
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
//-- GNU General Public License for more details. --
//-- --
//-- You should have received a copy of the GNU General Public --
//-- License along with this program; if not, see --
//-- <http://www.gnu.org/licenses>. --
//-- --
//---------------------------------------------------------------------
//-- The module can be configured with these parameters (defaults given in braces):
//--
//-- outputwidth(32) : width of output register
//-- size(31) : Size of counter, set from 5 to outputwidth-1. (overflow bit is extra, so max (outputwidth-1) Bit)
//-- clip_count(1) : sets if the count signal is to be clipped
//-- clip_reset(1 : sets if the reset signal is to be clipped
//--
//-- !!! IMPORTANT !!! Include slimfast_multioption_counter.ucf
module slimfast_multioption_counter (countClock,
count,
reset,
countout);
parameter clip_count = 1;
parameter clip_reset = 1;
parameter size = 31;
parameter outputwidth = 32;
input wire countClock;
input wire count;
input wire reset;
output wire [outputwidth-1:0] countout;
wire [size-3:0] highbits_this;
wire [size-3:0] highbits_next;
//-- Counter
slimfast_multioption_counter_core #(.clip_count(clip_count),.clip_reset(clip_reset),.size(size),.outputwidth(outputwidth)) counter(
.countClock(countClock),
.count(count),
.reset(reset),
.highbits_this(highbits_this),
.highbits_next(highbits_next),
.countout(countout)
);
//-- pure combinatorial +1 operation (multi cycle path, this may take up to 40ns without breaking the counter)
assign highbits_next = highbits_this + 1;
endmodule
module slimfast_multioption_counter_core (countClock,
count,
reset,
highbits_this,
highbits_next,
countout);
parameter clip_count = 1;
parameter clip_reset = 1;
parameter size = 31;
parameter outputwidth = 32;
input wire countClock;
input wire count;
input wire reset;
input wire [size-3:0] highbits_next;
output wire [size-3:0] highbits_this;
output wire [outputwidth-1:0] countout;
wire final_count;
wire final_reset;
reg [2:0] fast_counts = 3'b0;
(* KEEP = "true" *) reg [size-3:0] SFC_slow_counts = 'b0; //SFC_ prefix to make this name unique
wire [size-3:0] slow_counts_next;
//-- if an if-statement compares a value to 1 (not 1'b1), it is a generate-if
generate
//-- this is pure combinatorial
//-- after change of SFC_slow_counts, the update of slow_counts_next is allowed to take
//-- 16clk cycles of countClock
assign highbits_this = SFC_slow_counts;
assign slow_counts_next[size-4:0] = highbits_next[size-4:0];
//the overflow bit is counted like all the other bits, but it cannot fall back to zero
assign slow_counts_next[size-3] = highbits_next[size-3] || highbits_this[size-3];
if (clip_count == 0) assign final_count = count; else
if (clip_count == 1)
begin
wire clipped_count;
signal_clipper countclip ( .sig(count), .CLK(countClock), .clipped_sig(clipped_count));
assign final_count = clipped_count;
end else begin // I added this, so that one could switch from "clipped" to "not clipped" without changing the number of flip flop stages
reg piped_count;
always@(posedge countClock)
begin
piped_count <= count;
end
assign final_count = piped_count;
end
if (clip_reset == 0) assign final_reset = reset; else
begin
wire clipped_reset;
signal_clipper resetclip ( .sig(reset), .CLK(countClock), .clipped_sig(clipped_reset));
assign final_reset = clipped_reset;
end
always@(posedge countClock)
begin
if (final_reset == 1'b1)
begin
fast_counts <= 0;
SFC_slow_counts <= 0;
end else begin
//-- uses overflow as CE, valid only one clock cycle
if (final_count == 1'b1 && fast_counts == 3'b111) begin
SFC_slow_counts <= slow_counts_next;
end
//-- uses final_count as CE
if (final_count == 1'b1) fast_counts <= fast_counts + 1'b1;
end
end
endgenerate
assign countout[outputwidth-1] = SFC_slow_counts[size-3];
assign countout[outputwidth-2:0] = {'b0,SFC_slow_counts[size-4:0],fast_counts};
endmodule
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_128_32x32_dp.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 176 10/26/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module ram_128_32x32_dp (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [127:0] data;
input [3:0] rdaddress;
input rdclock;
input [1:0] wraddress;
input wrclock;
input wren;
output [31:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "2"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL rdaddress[3..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: wraddress 0 0 2 0 INPUT NODEFVAL wraddress[1..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 128 0 data 0 0 128 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 2 0 wraddress 0 0 2 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_32x32_dp.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_32x32_dp.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_32x32_dp.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_32x32_dp.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_32x32_dp_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_32x32_dp_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_32x32_dp_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_128_32x32_dp_wave*.jpg FALSE
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Graphics core top level
// File : graph_core.v
// Author : Jim MacLeod
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
//////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module takes in up to 6 PLL derived clocks plus a master clock (PCI).
// This module allows the glitchless switching amongst the clock frequencies.
// The purpose of this is to allow an FPGA w/o a programmable PLL
// (ex Cyclone2) to provide us with a variety of frequencies for generating
// Pixel clock and CRT clocks.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module clk_gen
(
input hb_clk,
input hb_resetn,
input pll_locked,
input [1:0] bpp,
input [13:0] hactive_regist,
input [2:0] pixclksel,
input vga_mode,
input [1:0] int_fs,
input sync_ext,
input pix_clk,
output pix_clk_vga,
output reg crt_clk,
output reg locked,
output reg [2:0] int_clk_sel // internal snapshot of clksel
);
reg [2:0] horiz_actv_decode;
reg [2:0] current, next; // State variables
reg set_clock; // set the current clock register
reg [1:0] int_crt_divider; // internal snapshot of crt_divider
reg [5:0] counter;
reg [7:0] neg_enable;
reg [7:0] neg_enable_0;
reg [7:0] neg_enable_1;
reg [1:0] crt_count0;
reg [1:0] crt_count1;
reg [1:0] crt_count2;
reg [1:0] crt_count3;
reg [1:0] crt_count4;
reg [1:0] crt_count5;
reg [1:0] crt_count6;
reg [1:0] crt_count7;
reg [2:0] crt_counter;
reg [1:0] crt_divider;
reg [2:0] clk_sel;
wire [7:0] gated_clocks;
parameter IDLE = 3'b000,
ENABLE_CLOCK = 3'b001,
WAIT4CHANGE = 3'b010,
WAIT4QUIET = 3'b011,
WAIT4QUIET2 = 3'b100;
wire int_fs_1 = int_fs[1];
`include "hres_table_4clk.h"
always @*
begin
casex({vga_mode, bpp})
3'b1_xx: crt_divider = 2'b00;
3'b0_01: crt_divider = 2'b10;
3'b0_10: crt_divider = 2'b01;
default: crt_divider = 2'b00;
endcase
end
always @*
begin
casex({vga_mode, pixclksel, sync_ext, int_fs_1})
// VGA Core resolutions.
6'b1_001_0_x: clk_sel = 3'b001; // External 25.17MHz (640x480 60Hz).
6'b1_100_0_x: clk_sel = 3'b001;
6'b1_001_1_x: clk_sel = 3'b010; // External 28MHz(720x480 60Hz).
6'b1_100_1_x: clk_sel = 3'b010;
6'b1_011_x_0: clk_sel = 3'b001; // Internal 25MHz (640x480 60Hz).
6'b1_101_x_0: clk_sel = 3'b001;
6'b1_011_x_1: clk_sel = 3'b010; // Internal 28MHz (720x480 60Hz).
6'b1_101_x_1: clk_sel = 3'b010;
default: clk_sel = horiz_actv_decode;
endcase
end
always @(posedge hb_clk or negedge hb_resetn)
if (!hb_resetn) begin
current <= IDLE;
int_clk_sel <= 3'b0;
locked <= 1'b0;
end else begin
locked <= current == IDLE;
current <= next;
if (set_clock) begin
int_clk_sel <= clk_sel;
int_crt_divider <= crt_divider;
end
// counter for waiting for clocks to be quiet
if (current == WAIT4CHANGE || current == IDLE)
counter <= 6'h0;
else if (current == WAIT4QUIET ||
current == WAIT4QUIET2)
counter <= counter + 6'h1;
end
always @* begin
set_clock = 1'b0;
next = current;
case (current)
IDLE: begin
// Wait for the PLLS to lock, then enable the current PLL
if (pll_locked) begin
next = WAIT4QUIET;
end else
next = IDLE;
end
ENABLE_CLOCK: begin
next = WAIT4CHANGE;
end
WAIT4CHANGE: begin
if ((clk_sel != int_clk_sel) || (crt_divider != int_crt_divider)) begin
// we've detected a change, disable all clocks
// set_clock = 1'b1;
next = WAIT4QUIET;
end else
next = WAIT4CHANGE;
end
WAIT4QUIET: begin
if (&counter[4:0]) begin
next = WAIT4QUIET2;
set_clock = 1'b1;
end else
next = WAIT4QUIET;
end
WAIT4QUIET2: begin
if (&counter) begin
next = ENABLE_CLOCK;
end else
next = WAIT4QUIET2;
end
endcase // case(current)
end
always @(posedge pix_clk or negedge hb_resetn)
begin
if(!hb_resetn)
begin
crt_clk <= 1'b1;
crt_counter <= 3'b000;
end
else begin
crt_counter <= crt_counter + 3'h1;
case (int_crt_divider)
0: crt_clk <= 1'b1;
1: crt_clk <= ~crt_counter[0];
2: crt_clk <= ~|crt_counter[1:0];
3: crt_clk <= ~|crt_counter[2:0];
endcase // case(int_crt_divider)
end
end
endmodule // clk_switch
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlxtn (
Q ,
D ,
GATE_N
);
// Module ports
output Q ;
input D ;
input GATE_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
not not0 (GATE , GATE_N_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_jid_to_yid.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// jbi_jid_to_yid -- JBus JID to YID translator.
// _____________________________________________________________________________
//
// Description:
// Responsible for performing the YID to JID translations for outbound local PIO
// transactions, and inbound local data returns.
// For outbound local transactions, an interface is provided for allocating an unused JID
// and remembering the JID to YID translation.
// For inbound local data returns, an interface is provided to perform a JID to YID lookup,
// and to free a JID translation from the table.
// The PIO JID pool has 16 JIDs which can be associated with any 9-bit YID value.
//
// Interface:
// Translation request:
// A JID 'trans_jid0' is given to the 'jid_to_yid_table' which returns the YID 'trans_yid0'
// on the same cycle. There are no qualifier signals.
//
// Allocating an assignment request:
// When 'alloc' is asserted, the YID 'alloc_yid' will be associated with the next available
// JID and that associated JID returned in 'alloc_jid'. Note that 'alloc_jid' is only valid
// during the current cycle that 'alloc' is valid. 'alloc_stall' denotes that there are
// no more available JIDs and 'alloc' must not be asserted until one is freed. When a JID
// is allocated, it is removed from the free jid pool 'free_jid_pool'.
//
// Freeing an assignment request:
// When '*' is asserted, the JID in 'free*_jid' is added to the JID free space
// pool maintained by 'free_jid_pool'.
// _____________________________________________________________________________
`include "sys.h"
module jbi_jid_to_yid (/*AUTOARG*/
// Outputs
trans_yid0, trans_valid0, trans_yid1, trans_valid1, alloc_stall, alloc_jid,
// Inputs
trans_jid0, trans_jid1, alloc, alloc_yid, free0, free_jid0, free1, free_jid1,
clk, rst_l
);
// Translation, port 0.
input [3:0] trans_jid0;
output [9:0] trans_yid0;
output trans_valid0;
// Translation, port 1.
input [3:0] trans_jid1;
output [9:0] trans_yid1;
output trans_valid1;
// Allocating an assignment.
output alloc_stall;
input alloc;
input [9:0] alloc_yid;
output [3:0] alloc_jid;
// Free an assignment, port 0.
input free0;
input [3:0] free_jid0;
// Free an assignment, port 1.
input free1;
input [3:0] free_jid1;
// Clock and reset.
input clk;
input rst_l;
// Wires and Regs.
// JID to YID translation table.
jbi_jid_to_yid_table jid_to_yid_table (
//
// Translation, port 0.
.trans_jid0 (trans_jid0),
.trans_yid0 (trans_yid0),
//
// Translation, port 1.
.trans_jid1 (trans_jid1),
.trans_yid1 (trans_yid1),
//
// Allocating an assignment.
.alloc (alloc),
.alloc_jid (alloc_jid),
.alloc_yid (alloc_yid),
//
// Clock and reset.
.clk (clk),
.rst_l (rst_l)
);
// Free JID pool.
jbi_jid_to_yid_pool jid_to_yid_pool (
//
// Removing from pool (allocating jid).
.jid_is_avail (jid_is_avail),
.jid (alloc_jid),
.remove (alloc),
//
// Adding to pool, port 0.
.add0 (free0),
.add_jid0 (free_jid0),
//
// Adding to pool, port 1.
.add1 (free1),
.add_jid1 (free_jid1),
//
// Translation validation, port0.
.trans_jid0 (trans_jid0),
.trans_valid0 (trans_valid0),
//
// Translation validation, port1.
.trans_jid1 (trans_jid1),
.trans_valid1 (trans_valid1),
//
// System interface.
.clk (clk),
.rst_l (rst_l)
);
assign alloc_stall = ~jid_is_avail;
// Monitors.
// simtech modcovoff -bpen
// synopsys translate_off
// Checks: 'alloc' not asserted while 'alloc_stall'.
always @(posedge clk) begin
if (alloc_stall && alloc) begin
$dispmon ("jbi_mout_jbi_jid_to_yid", 49, "%d %m: ERROR - Attempt made to allocate a JID when none are available.", $time);
end
end
// synopsys translate_on
// simtech modcovon -bpen
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../include")
// verilog-module-parents:("jbi_mout")
// End:
|
/**
\file "shoelace.v"
Chain a bunch of inverters between VPI/VCS and prsim, shoelacing.
$Id: shoelace.v,v 1.3 2010/04/06 00:08:37 fang Exp $
Thanks to Ilya Ganusov for contributing this test.
*/
`timescale 1ns/1ps
`define inv_delay 0.010
`include "clkgen.v"
/* the humble inverter */
module inverter (in, out);
parameter DELAY=`inv_delay;
input in;
output out;
reg __o;
wire out = __o;
always @(in)
begin
#DELAY __o <= ~in;
end
endmodule
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
/* our top-level */
module TOP;
wire in, in1, in2, in3, in4;
reg out0, out1, out2, out3, out;
clk_gen #(.HALF_PERIOD(1)) clk(in);
/**
assign in1 = ~out0;
assign in2 = ~out1;
assign in3 = ~out2;
assign in4 = ~out3;
**/
inverter q0(out0, in1);
inverter q1(out1, in2);
inverter q2(out2, in3);
inverter q3(out3, in4);
// prsim stuff
initial
begin
// @haco@ inverters.haco-c
$prsim("inverters.haco-c");
$prsim_cmd("echo $start of simulation");
$to_prsim("TOP.in", "in0");
$to_prsim("TOP.in1", "in1");
$to_prsim("TOP.in2", "in2");
$to_prsim("TOP.in3", "in3");
$to_prsim("TOP.in4", "in4");
$from_prsim("out0","TOP.out0");
$from_prsim("out1","TOP.out1");
$from_prsim("out2","TOP.out2");
$from_prsim("out3","TOP.out3");
$from_prsim("out4","TOP.out");
end
initial #45 $finish;
/**
// optional: produce vector file for dump
initial begin
$dumpfile ("test.dump");
$dumpvars(0,TOP);
end
**/
always @(in)
begin
$display("at time %7.3f, observed in %b", $realtime,in);
end
always @(out)
begin
$display("at time %7.3f, observed out = %b", $realtime,out);
end
endmodule
|
(*
* Copyright 2019 Jade Philipoom
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*)
Require Import Coq.Lists.List.
Require Import Coq.Arith.PeanoNat.
Require Import Hafnium.AbstractModel.
Require Import Hafnium.Concrete.Parameters.
Require Import Hafnium.Concrete.State.
Require Import Hafnium.Concrete.Datatypes.
Require Import Hafnium.Util.Tactics.
Require Import Hafnium.Concrete.Api.Implementation.
Require Import Hafnium.Concrete.Api.Proofs.
Require Import Hafnium.Concrete.Assumptions.Addr.
Require Import Hafnium.Concrete.Assumptions.Mpool.
(*** This file gives the definition of execution in the concrete model and
includes the highest-level correctness proof, stating that the execution
rules of the concrete model obey the system invariants. ***)
Inductive api_call : Type :=
| clear_memory : paddr_t -> paddr_t -> mpool -> api_call
| share_memory : nat -> ipaddr_t -> size_t -> hf_share -> vm -> api_call
.
(* Given concrete parameters and a start state, execute api calls and
return the final concrete state. *)
Definition execute_trace
{cp : concrete_params}
(start_state : concrete_state)
(trace : list api_call) : concrete_state :=
fold_right (fun next_call state =>
match next_call with
| clear_memory begin end_ ppool =>
let ret := api_clear_memory state begin end_ ppool in
snd (fst ret)
| share_memory vid addr size share current =>
let ret := api_share_memory state vid addr size share current in
snd ret
end)
start_state trace.
(* A concrete state obeys the invariants if it's represented by an abstract
state that obeys them. *)
Definition obeys_invariants
{ap : abstract_state_parameters} {cp : concrete_params}
(conc : concrete_state) : Prop :=
exists abst : abstract_state,
represents_valid abst conc /\ AbstractModel.obeys_invariants abst.
(* because [represents_valid] includes [AbstractModel.is_valid], and we've proved
all valid abstract states obey the invariants, it's sufficient to just prove
[represents_valid] *)
Lemma represents_obeys_invariants
{ap : abstract_state_parameters} {cp : concrete_params}
(conc : concrete_state) :
(exists abst, represents_valid abst conc) ->
obeys_invariants conc.
Proof.
cbv [represents_valid obeys_invariants]; basics.
eexists; basics; try solver; [ ].
eauto using valid_obeys_invariants.
Qed.
(* Given a start concrete state that represents a vaild abstract state,
execution of api calls always returns a concrete state that also represents
a valid abstract state. *)
Lemma execution_represents
{ap : @abstract_state_parameters paddr_t nat} {cp : concrete_params}
{cp_ok : params_valid}
(start_state : concrete_state) (trace : list api_call) :
(exists abst, represents_valid abst start_state) ->
exists abst, represents_valid abst (execute_trace start_state trace).
Proof.
cbv [execute_trace]; intros; induction trace; [ basics; solver | ].
destruct IHtrace as [abst IHtrace]. basics.
cbn [fold_right]. break_match; intros.
{ (* case : api_clear_memory *)
apply api_clear_memory_represents with (abst0:=abst).
eapply IHtrace. }
{ (* case : api_share_memory *)
apply api_share_memory_represents with (abst0:=abst).
eapply IHtrace. }
Qed.
(*** Highest-level correctness theorem: any execution of api calls will preserve
the invariants; that is, if you obey the invariants at the start, no
sequence of api calls can make you stop obeying them. ***)
Theorem execution_preserves_invariants
{ap : abstract_state_parameters} {cp : concrete_params}
{cp_ok : params_valid} :
forall (trace : list api_call) (start_state : concrete_state),
obeys_invariants start_state ->
obeys_invariants (execute_trace start_state trace).
Proof.
intros; apply represents_obeys_invariants, execution_represents.
cbv [obeys_invariants] in *. basics; solver.
Qed.
(* Uncomment the below to see all assumptions that the top-level correctness
theorem depends on. *)
(* Print Assumptions execution_preserves_invariants. *)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 28.06.2017 17:24:09
// Design Name:
// Module Name: ctrlunit
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Based off the code provided by the professor for the assignment
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ctrlunit(
input [5:0] OPCode, Funct,
output MemToReg, MemWrite, Branch, ALUSrc, RegDst, RegWrite, Jump,
output [2:0] ALUControl
);
wire [1:0] ALUOp;
//wire zerosignal;
maindecoder md_inst(
.op( OPCode ),
.memtoreg( MemToReg ),
.memwrite( MemWrite ),
.branch( Branch ),
.alusrc( ALUSrc ),
.regdst( RegDst ),
.regwrite( RegWrite ),
.jump( Jump ),
.aluop( ALUOp )
);
aludecoder ad_inst(
.funct( Funct ),
.aluop( ALUOp ),
.alucontrol( ALUControl )
);
//PCSrc will be created at combining all the sections of the processor.
//assign PCSrc = Branch & zerosignal;
endmodule
module maindecoder(
input [5:0] op,
output memtoreg, memwrite,
output branch, alusrc,
output regdst, regwrite,
output jump,
output [1:0] aluop);
reg [8:0] controls;
assign {memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump, aluop} = controls;
always @ (op) begin
case(op)
6'b000000: controls <= 9'b000011011; //Rtype
6'b100011: controls <= 9'b100101000; //LW
6'b101011: controls <= 9'b010100000; //SW
6'b000100: controls <= 9'b001000001; //BEQ
6'b001000: controls <= 9'b000101000; //ADDI
6'b000010: controls <= 9'b000000100; //J
default: controls <= 9'bxxxxxxxxx; //???
endcase
end
endmodule
module aludecoder(
output reg [2:0] alucontrol,
input [5:0] funct,
input [1:0] aluop
);
always @ (aluop or funct) begin
case(aluop)
2'b00: alucontrol <= 3'b010; //addi
2'b01: alucontrol <= 3'b110; //sub, although not needed
default: case(funct) // Rtype
6'b100000: alucontrol <= 3'b010; // ADD
6'b100010: alucontrol <= 3'b110; // SUB
6'b100100: alucontrol <= 3'b000; // AND
6'b100101: alucontrol <= 3'b001; // OR
6'b101010: alucontrol <= 3'b111; // SLT
default: alucontrol <= 3'bxxx; // unused
endcase
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SHA-160 ////
//// Secure Hash Algorithm (SHA-160) ////
//// ////
//// Author: marsgod ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/sha_core/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002-2004 marsgod ////
//// [email protected] ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
`define SHA1_H0 32'h67452301
`define SHA1_H1 32'hefcdab89
`define SHA1_H2 32'h98badcfe
`define SHA1_H3 32'h10325476
`define SHA1_H4 32'hc3d2e1f0
`define SHA1_K0 32'h5a827999
`define SHA1_K1 32'h6ed9eba1
`define SHA1_K2 32'h8f1bbcdc
`define SHA1_K3 32'hca62c1d6
module sha1 (clk_i, reset, text_i, text_o, cmd_i, cmd_w_i, cmd_o);
input clk_i; // global clock input
input reset; // global reset input , active high
input [31:0] text_i; // text input 32bit
output [31:0] text_o; // text output 32bit
input [2:0] cmd_i; // command input
input cmd_w_i;// command input write enable
output [3:0] cmd_o; // command output(status)
/*
cmd
Busy Round W R
bit3 bit2 bit1 bit0
Busy Round W R
Busy:
0 idle
1 busy
Round:
0 first round
1 internal round
W:
0 No-op
1 write data
R:
0 No-op
1 read data
*/
reg [3:0] cmd;
wire [3:0] cmd_o;
reg [31:0] text_o;
reg [6:0] round;
wire [6:0] round_plus_1;
reg [2:0] read_counter;
reg [31:0] H0,H1,H2,H3,H4;
reg [31:0] W0,W1,W2,W3,W4,W5,W6,W7,W8,W9,W10,W11,W12,W13,W14;
reg [31:0] Wt,Kt;
reg [31:0] A,B,C,D,E;
reg busy;
assign cmd_o = cmd;
always @ (posedge clk_i)
begin
if (reset)
cmd <= 4'b0000;
else
if (cmd_w_i)
cmd[2:0] <= cmd_i[2:0]; // busy bit can't write
else
begin
cmd[3] <= busy; // update busy bit
if (~busy)
cmd[1:0] <= 2'b00; // hardware auto clean R/W bits
end
end
// Hash functions
wire [31:0] SHA1_f1_BCD,SHA1_f2_BCD,SHA1_f3_BCD,SHA1_Wt_1;
wire [31:0] SHA1_ft_BCD;
wire [31:0] next_Wt,next_A,next_C;
wire [159:0] SHA1_result;
assign SHA1_f1_BCD = (B & C) ^ (~B & D);
assign SHA1_f2_BCD = B ^ C ^ D;
assign SHA1_f3_BCD = (B & C) ^ (C & D) ^ (B & D);
assign SHA1_ft_BCD = (round < 7'b0100101) ? SHA1_f1_BCD : (round < 7'b101001) ? SHA1_f2_BCD : (round < 7'b1111101) ? SHA1_f3_BCD : SHA1_f2_BCD;
// Odin II doesn't support binary operations inside concatenations presently.
//assign SHA1_Wt_1 = {W13 ^ W8 ^ W2 ^ W0};
assign SHA1_Wt_1 = W13 ^ W8 ^ W2 ^ W0;
assign next_Wt = {SHA1_Wt_1[30:0],SHA1_Wt_1[31]}; // NSA fix added
assign next_A = {A[26:0],A[31:27]} + SHA1_ft_BCD + E + Kt + Wt;
assign next_C = {B[1:0],B[31:2]};
assign SHA1_result = {A,B,C,D,E};
assign round_plus_1 = round + 1;
//------------------------------------------------------------------
// SHA round
//------------------------------------------------------------------
always @(posedge clk_i)
begin
if (reset)
begin
round <= 7'b0000000;
busy <= 1'b0;
W0 <= 32'b00000000000000000000000000000000;
W1 <= 32'b00000000000000000000000000000000;
W2 <= 32'b00000000000000000000000000000000;
W3 <= 32'b00000000000000000000000000000000;
W4 <= 32'b00000000000000000000000000000000;
W5 <= 32'b00000000000000000000000000000000;
W6 <= 32'b00000000000000000000000000000000;
W7 <= 32'b00000000000000000000000000000000;
W8 <= 32'b00000000000000000000000000000000;
W9 <= 32'b00000000000000000000000000000000;
W10 <= 32'b00000000000000000000000000000000;
W11 <= 32'b00000000000000000000000000000000;
W12 <= 32'b00000000000000000000000000000000;
W13 <= 32'b00000000000000000000000000000000;
W14 <= 32'b00000000000000000000000000000000;
Wt <= 32'b00000000000000000000000000000000;
A <= 32'b00000000000000000000000000000000;
B <= 32'b00000000000000000000000000000000;
C <= 32'b00000000000000000000000000000000;
D <= 32'b00000000000000000000000000000000;
E <= 32'b00000000000000000000000000000000;
H0 <= 32'b00000000000000000000000000000000;
H1 <= 32'b00000000000000000000000000000000;
H2 <= 32'b00000000000000000000000000000000;
H3 <= 32'b00000000000000000000000000000000;
H4 <= 32'b00000000000000000000000000000000;
end
else
begin
case (round)
7'b0000000:
begin
if (cmd[1])
begin
W0 <= text_i;
Wt <= text_i;
busy <= 1'b1;
round <= round_plus_1;
case (cmd[2])
1'b0: // sha-1 first message
begin
A <= `SHA1_H0;
B <= `SHA1_H1;
C <= `SHA1_H2;
D <= `SHA1_H3;
E <= `SHA1_H4;
H0 <= `SHA1_H0;
H1 <= `SHA1_H1;
H2 <= `SHA1_H2;
H3 <= `SHA1_H3;
H4 <= `SHA1_H4;
end
1'b1: // sha-1 internal message
begin
H0 <= A;
H1 <= B;
H2 <= C;
H3 <= D;
H4 <= E;
end
endcase
end
else
begin // IDLE
round <= 7'b0000000;
end
end
7'b0000001:
begin
W1 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0000010:
begin
W2 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0000011:
begin
W3 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0000100:
begin
W4 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0000101:
begin
W5 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0000110:
begin
W6 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0000111:
begin
W7 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0001000:
begin
W8 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0001001:
begin
W9 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0001010:
begin
W10 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0001011:
begin
W11 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0001100:
begin
W12 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0001101:
begin
W13 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0001110:
begin
W14 <= text_i;
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0001111:
begin
Wt <= text_i;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0010000:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0010001:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0010010:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0010011:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0010100:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0010101:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0010110:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0010111:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0011000:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0011001:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0011010:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0011011:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0011100:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0011101:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0011110:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0011111:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0100000:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0100001:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0100010:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0100011:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0100100:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0100101:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0100110:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0100111:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0101000:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0101001:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0101010:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0101011:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0101100:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0101101:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0101110:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0101111:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0110000:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0110001:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0110010:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0110011:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0110100:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0110101:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0110110:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0110111:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0111000:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0111001:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0111010:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0111011:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0111100:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0111101:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0111110:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b0111111:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1000000:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1000001:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1000010:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1000011:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1000100:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1000101:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1000110:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1000111:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1001000:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1001001:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1001010:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1001011:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1001100:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1001101:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1001110:begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1001111:
begin
W0 <= W1;
W1 <= W2;
W2 <= W3;
W3 <= W4;
W4 <= W5;
W5 <= W6;
W6 <= W7;
W7 <= W8;
W8 <= W9;
W9 <= W10;
W10 <= W11;
W11 <= W12;
W12 <= W13;
W13 <= W14;
W14 <= Wt;
Wt <= next_Wt;
E <= D;
D <= C;
C <= next_C;
B <= A;
A <= next_A;
round <= round_plus_1;
end
7'b1010000:
begin
A <= next_A + H0;
B <= A + H1;
C <= next_C + H2;
D <= C + H3;
E <= D + H4;
round <= 7'b0000000;
busy <= 1'b0;
end
default:
begin
round <= 7'b0000000;
busy <= 1'b0;
end
endcase
end
end
//------------------------------------------------------------------
// Kt generator
//------------------------------------------------------------------
always @ (posedge clk_i)
begin
if (reset)
begin
Kt <= 32'b00000000000000000000000000000000;
end
else
begin
if (round < 7'b0100000)
Kt <= `SHA1_K0;
else
if (round < 7'b1010000)
Kt <= `SHA1_K1;
else
if (round < 7'b1111100)
Kt <= `SHA1_K2;
else
Kt <= `SHA1_K3;
end
end
//------------------------------------------------------------------
// read result
//------------------------------------------------------------------
always @ (posedge clk_i)
begin
if (reset)
begin
text_o <= 32'b00000000000000000000000000000000;
read_counter <= 3'b000;
end
else
begin
if (cmd[0])
begin
read_counter <= 3'b100; // sha-1 160/32=5
end
else
begin
if (~busy)
begin
case (read_counter)
3'b100: text_o <= SHA1_result[5*32-1:4*32];
3'b011: text_o <= SHA1_result[4*32-1:3*32];
3'b010: text_o <= SHA1_result[3*32-1:2*32];
3'b001: text_o <= SHA1_result[2*32-1:1*32];
3'b000: text_o <= SHA1_result[1*32-1:0*32];
default:text_o <= 3'b000;
endcase
if (|read_counter)
read_counter <= read_counter - 7'b0000001;
end
else
begin
text_o <= 32'b00000000000000000000000000000000;
end
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O311A_FUNCTIONAL_PP_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_FUNCTIONAL_PP_V |
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 8
(* X_CORE_INFO = "axi_protocol_converter_v2_1_8_axi_protocol_converter,Vivado 2016.1" *)
(* CHECK_LICENSE_TYPE = "design_1_auto_pc_1,axi_protocol_converter_v2_1_8_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "design_1_auto_pc_1,axi_protocol_converter_v2_1_8_axi_protocol_converter,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDT\
H=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_pc_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_8_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// lattice ice5lp4k rxadc v2
// 07-17-16 E. Brombaugh
module rxadc_2 #(
parameter isz = 10,
fsz = 26,
dsz = 16
)
(
// SPI slave port
input SPI_CSL,
input SPI_MOSI,
output SPI_MISO,
input SPI_SCLK,
// rxadc board interface
input rxadc_clk,
output rxadc_dfs,
input rxadc_otr,
input [9:0] rxadc_dat,
// I2S DAC output
output dac_mclk,
output dac_sdout,
output dac_sclk,
output dac_lrck,
// I2S MCU interface
input mcu_sdin,
output mcu_sdout,
output mcu_sclk,
output mcu_lrck,
// RGB output
output wire o_red,
output wire o_green,
output wire o_blue
);
// This should be unique so firmware knows who it's talking to
parameter DESIGN_ID = 32'h2ADC0003;
//------------------------------
// Instantiate ADC clock buffer
//------------------------------
wire adc_clk;
SB_GB clk_gbuf(
.USER_SIGNAL_TO_GLOBAL_BUFFER(!rxadc_clk),
.GLOBAL_BUFFER_OUTPUT(adc_clk)
);
//------------------------------
// Instantiate HF Osc with div 1
//------------------------------
wire clk;
SB_HFOSC #(.CLKHF_DIV("0b00")) OSCInst0 (
.CLKHFEN(1'b1),
.CLKHFPU(1'b1),
.CLKHF(clk)
) /* synthesis ROUTE_THROUGH_FABRIC= 0 */;
//------------------------------
// reset generators
//------------------------------
reg [3:0] reset_pipe = 4'hf;
reg reset = 1'b1;
always @(posedge clk)
begin
reset <= |reset_pipe;
reset_pipe <= {reset_pipe[2:0],1'b0};
end
reg [3:0] adc_reset_pipe = 4'hf;
reg adc_reset = 1'b1;
always @(posedge adc_clk)
begin
adc_reset <= |adc_reset_pipe;
adc_reset_pipe <= {adc_reset_pipe[2:0],1'b0};
end
//------------------------------
// Internal SPI slave port
//------------------------------
wire [31:0] wdat;
reg [31:0] rdat;
wire [6:0] addr;
wire re, we, spi_slave_miso;
spi_slave
uspi(.clk(clk), .reset(reset),
.spiclk(SPI_SCLK), .spimosi(SPI_MOSI),
.spimiso(SPI_MISO), .spicsl(SPI_CSL),
.we(we), .re(re), .wdat(wdat), .addr(addr), .rdat(rdat));
//------------------------------
// Writeable registers
//------------------------------
reg [13:0] cnt_limit_reg;
reg [9:0] dpram_raddr;
reg dpram_trig;
reg [25:0] ddc_frq;
reg dac_mux_sel;
reg ddc_ns_ena;
always @(posedge clk)
if(reset)
begin
cnt_limit_reg <= 14'd2499; // 1/4 sec blink rate
dpram_raddr <= 10'h000; // read address
dpram_trig <= 1'b0;
ddc_frq <= 26'h0;
dac_mux_sel <= 1'b0;
ddc_ns_ena <= 1'b0;
end
else if(we)
case(addr)
7'h01: cnt_limit_reg <= wdat;
7'h02: dpram_raddr <= wdat;
7'h03: dpram_trig <= wdat;
7'h10: ddc_frq <= wdat;
7'h11: dac_mux_sel <= wdat;
7'h12: ddc_ns_ena <= wdat;
endcase
//------------------------------
// readable registers
//------------------------------
reg dpram_wen;
reg [10:0] dpram_rdat;
always @(*)
case(addr)
7'h00: rdat = DESIGN_ID;
7'h01: rdat = cnt_limit_reg;
7'h02: rdat = dpram_raddr;
7'h03: rdat = {dpram_raddr,dpram_rdat};
7'h04: rdat = dpram_wen;
7'h10: rdat = ddc_frq;
7'h11: rdat = dac_mux_sel;
7'h12: rdat = ddc_ns_ena;
default: rdat = 32'd0;
endcase
//------------------------------
// register ADC input data
//------------------------------
reg [9:0] dpram_waddr;
reg [10:0] dpram_wdat;
always @(posedge adc_clk)
dpram_wdat <= {rxadc_otr,rxadc_dat};
//------------------------------
// 1k x 11 dual-port RAM
//------------------------------
reg [10:0] mem [1023:0];
always @(posedge adc_clk) // Write memory.
begin
if(dpram_wen)
mem[dpram_waddr] <= dpram_wdat;
end
always @(posedge clk) // Read memory.
dpram_rdat <= mem[dpram_raddr];
//------------------------------
// write state machine - runs from 40MHz clock
//------------------------------
reg [2:0] dpram_trig_sync;
always @(posedge adc_clk)
if(adc_reset)
begin
dpram_waddr <= 10'h000;
dpram_trig_sync <= 3'b000;
dpram_wen <= 1'b0;
end
else
begin
dpram_trig_sync <= {dpram_trig_sync[1:0],dpram_trig};
if(~dpram_wen)
begin
if(dpram_trig_sync[2])
dpram_wen <= 1'b1;
dpram_waddr <= 10'h000;
end
else
begin
if(dpram_waddr == 10'h3ff)
dpram_wen <= 1'b0;
dpram_waddr <= dpram_waddr + 1;
end
end
//------------------------------
// DDC instance
//------------------------------
wire signed [dsz-1:0] ddc_i, ddc_q;
wire ddc_v;
ddc_2 #(
.isz(isz),
.fsz(fsz),
.osz(dsz)
)
u_ddc(
.clk(adc_clk), .reset(adc_reset),
.in(dpram_wdat[isz-1:0]),
.frq(ddc_frq),
.ns_ena(ddc_ns_ena),
.valid(ddc_v),
.i_out(ddc_i), .q_out(ddc_q)
);
//------------------------------
// Strap ADC Data Format for 2's comp
//------------------------------
assign rxadc_dfs = 1'b0;
//------------------------------
// handoff between ddc and i2s
//------------------------------
reg signed [dsz-1:0] ddc_i_l, ddc_q_l;
wire audio_ena;
always @(posedge adc_clk)
if(adc_reset)
begin
ddc_i_l <= 16'h0000;
ddc_q_l <= 16'h0000;
end
else
begin
if(audio_ena)
begin
ddc_i_l <= ddc_i;
ddc_q_l <= ddc_q;
end
end
//------------------------------
// I2S serializer
//------------------------------
wire sdout;
i2s_out
ui2s(.clk(adc_clk), .reset(adc_reset),
.l_data(ddc_i_l), .r_data(ddc_q_l),
.mclk(dac_mclk), .sdout(sdout), .sclk(dac_sclk), .lrclk(dac_lrck),
.load(audio_ena));
// Hook up I2S to DAC and MCU I2S pins
assign mcu_lrck = dac_lrck;
assign mcu_sclk = dac_sclk;
assign dac_sdout = (dac_mux_sel == 1'b1) ? mcu_sdin : sdout;
assign mcu_sdout = sdout;
//------------------------------
// Instantiate LF Osc
//------------------------------
wire CLKLF;
SB_LFOSC OSCInst1 (
.CLKLFEN(1'b1),
.CLKLFPU(1'b1),
.CLKLF(CLKLF)
) /* synthesis ROUTE_THROUGH_FABRIC= 0 */;
//------------------------------
// Divide the clock
//------------------------------
reg [13:0] clkdiv;
reg onepps;
always @(posedge CLKLF)
begin
if(clkdiv == 14'd0)
begin
onepps <= 1'b1;
clkdiv <= cnt_limit_reg;
end
else
begin
onepps <= 1'b0;
clkdiv <= clkdiv - 14'd1;
end
end
//------------------------------
// LED signals
//------------------------------
reg [2:0] state;
always @(posedge CLKLF)
begin
if(onepps)
state <= state + 3'd1;
end
//------------------------------
// Instantiate RGB DRV
//------------------------------
wire red_pwm_i = state[0];
wire grn_pwm_i = state[1];
wire blu_pwm_i = state[2];
SB_RGB_DRV RGB_DRIVER (
.RGBLEDEN (1'b1), // Enable current for all 3 RGB LED pins
.RGB0PWM (red_pwm_i), // Input to drive RGB0 - from LEDD HardIP
.RGB1PWM (grn_pwm_i), // Input to drive RGB1 - from LEDD HardIP
.RGB2PWM (blu_pwm_i), // Input to drive RGB2 - from LEDD HardIP
.RGBPU (led_power_up_i), //Connects to LED_DRV_CUR primitive
.RGB0 (o_red),
.RGB1 (o_green),
.RGB2 (o_blue)
);
defparam RGB_DRIVER.RGB0_CURRENT = "0b000111";
defparam RGB_DRIVER.RGB1_CURRENT = "0b000111";
defparam RGB_DRIVER.RGB2_CURRENT = "0b000111";
//------------------------------
// Instantiate LED CUR DRV
//------------------------------
SB_LED_DRV_CUR LED_CUR_inst (
.EN (1'b1), //Enable to supply reference current to the LED drivers
.LEDPU (led_power_up_i) //Connects to SB_RGB_DRV primitive
);
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module peripheral_clock_crossing_downstream_fifo (
// inputs:
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
// outputs:
q,
rdempty,
wrfull
)
;
output [ 93: 0] q;
output rdempty;
output wrfull;
input aclr;
input [ 93: 0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
wire [ 93: 0] q;
wire rdempty;
wire wrfull;
dcfifo downstream_fifo
(
.aclr (aclr),
.data (data),
.q (q),
.rdclk (rdclk),
.rdempty (rdempty),
.rdreq (rdreq),
.wrclk (wrclk),
.wrfull (wrfull),
.wrreq (wrreq)
);
defparam downstream_fifo.intended_device_family = "STRATIXIV",
downstream_fifo.lpm_numwords = 16,
downstream_fifo.lpm_showahead = "OFF",
downstream_fifo.lpm_type = "dcfifo",
downstream_fifo.lpm_width = 94,
downstream_fifo.lpm_widthu = 4,
downstream_fifo.overflow_checking = "ON",
downstream_fifo.rdsync_delaypipe = 5,
downstream_fifo.underflow_checking = "ON",
downstream_fifo.use_eab = "ON",
downstream_fifo.wrsync_delaypipe = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module peripheral_clock_crossing_upstream_fifo (
// inputs:
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
// outputs:
q,
rdempty,
wrusedw
)
;
output [ 32: 0] q;
output rdempty;
output [ 5: 0] wrusedw;
input aclr;
input [ 32: 0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
wire [ 32: 0] q;
wire rdempty;
wire [ 5: 0] wrusedw;
dcfifo upstream_fifo
(
.aclr (aclr),
.data (data),
.q (q),
.rdclk (rdclk),
.rdempty (rdempty),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.wrusedw (wrusedw)
);
defparam upstream_fifo.intended_device_family = "STRATIXIV",
upstream_fifo.lpm_numwords = 64,
upstream_fifo.lpm_showahead = "OFF",
upstream_fifo.lpm_type = "dcfifo",
upstream_fifo.lpm_width = 33,
upstream_fifo.lpm_widthu = 6,
upstream_fifo.overflow_checking = "ON",
upstream_fifo.rdsync_delaypipe = 5,
upstream_fifo.underflow_checking = "ON",
upstream_fifo.use_eab = "ON",
upstream_fifo.wrsync_delaypipe = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module peripheral_clock_crossing (
// inputs:
master_clk,
master_endofpacket,
master_readdata,
master_readdatavalid,
master_reset_n,
master_waitrequest,
slave_address,
slave_byteenable,
slave_clk,
slave_nativeaddress,
slave_read,
slave_reset_n,
slave_write,
slave_writedata,
// outputs:
master_address,
master_byteenable,
master_nativeaddress,
master_read,
master_write,
master_writedata,
slave_endofpacket,
slave_readdata,
slave_readdatavalid,
slave_waitrequest
)
;
output [ 29: 0] master_address;
output [ 3: 0] master_byteenable;
output [ 27: 0] master_nativeaddress;
output master_read;
output master_write;
output [ 31: 0] master_writedata;
output slave_endofpacket;
output [ 31: 0] slave_readdata;
output slave_readdatavalid;
output slave_waitrequest;
input master_clk;
input master_endofpacket;
input [ 31: 0] master_readdata;
input master_readdatavalid;
input master_reset_n;
input master_waitrequest;
input [ 27: 0] slave_address;
input [ 3: 0] slave_byteenable;
input slave_clk;
input [ 27: 0] slave_nativeaddress;
input slave_read;
input slave_reset_n;
input slave_write;
input [ 31: 0] slave_writedata;
wire [ 93: 0] downstream_data_in;
wire [ 93: 0] downstream_data_out;
wire downstream_rdempty;
reg downstream_rdempty_delayed_n;
wire downstream_rdreq;
wire downstream_wrfull;
wire downstream_wrreq;
reg downstream_wrreq_delayed;
wire [ 27: 0] internal_master_address;
wire internal_master_read;
wire internal_master_write;
wire [ 29: 0] master_address;
wire [ 29: 0] master_byte_address;
wire [ 3: 0] master_byteenable;
wire master_hold_read;
wire master_hold_write;
wire [ 27: 0] master_nativeaddress;
wire master_new_read;
wire master_new_read_term_one;
wire master_new_read_term_two;
wire master_new_write;
wire master_new_write_term_one;
wire master_new_write_term_two;
wire master_read;
wire master_read_write_unchanged_on_wait;
reg master_waitrequest_delayed;
wire master_write;
wire [ 31: 0] master_writedata;
wire slave_endofpacket;
wire [ 31: 0] slave_readdata;
reg slave_readdatavalid;
wire slave_waitrequest;
wire [ 32: 0] upstream_data_in;
wire [ 32: 0] upstream_data_out;
wire upstream_rdempty;
wire upstream_rdreq;
wire upstream_write_almost_full;
reg upstream_write_almost_full_delayed;
wire upstream_wrreq;
wire [ 5: 0] upstream_wrusedw;
//s1, which is an e_avalon_slave
//m1, which is an e_avalon_master
assign upstream_data_in = {master_readdata, master_endofpacket};
assign {slave_readdata, slave_endofpacket} = upstream_data_out;
assign downstream_data_in = {slave_writedata, slave_address, slave_read, slave_write, slave_nativeaddress, slave_byteenable};
assign {master_writedata, internal_master_address, internal_master_read, internal_master_write, master_nativeaddress, master_byteenable} = downstream_data_out;
//the_downstream_fifo, which is an e_instance
peripheral_clock_crossing_downstream_fifo the_downstream_fifo
(
.aclr (~slave_reset_n),
.data (downstream_data_in),
.q (downstream_data_out),
.rdclk (master_clk),
.rdempty (downstream_rdempty),
.rdreq (downstream_rdreq),
.wrclk (slave_clk),
.wrfull (downstream_wrfull),
.wrreq (downstream_wrreq)
);
assign downstream_wrreq = slave_read | slave_write | downstream_wrreq_delayed;
assign slave_waitrequest = downstream_wrfull;
assign downstream_rdreq = !downstream_rdempty & !master_waitrequest & !upstream_write_almost_full;
assign upstream_write_almost_full = upstream_wrusedw >= 15;
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
downstream_wrreq_delayed <= 0;
else
downstream_wrreq_delayed <= slave_read | slave_write;
end
assign master_new_read_term_one = internal_master_read & downstream_rdempty_delayed_n;
assign master_new_read_term_two = !master_read_write_unchanged_on_wait & !upstream_write_almost_full_delayed;
assign master_new_read = master_new_read_term_one & master_new_read_term_two;
assign master_hold_read = master_read_write_unchanged_on_wait & internal_master_read;
assign master_new_write_term_one = internal_master_write & downstream_rdempty_delayed_n;
assign master_new_write_term_two = !master_read_write_unchanged_on_wait & !upstream_write_almost_full_delayed;
assign master_new_write = master_new_write_term_one & master_new_write_term_two;
assign master_hold_write = master_read_write_unchanged_on_wait & internal_master_write;
assign master_read_write_unchanged_on_wait = master_waitrequest_delayed;
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_waitrequest_delayed <= 0;
else
master_waitrequest_delayed <= master_waitrequest;
end
assign master_read = master_new_read | master_hold_read;
assign master_write = master_new_write | master_hold_write;
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
downstream_rdempty_delayed_n <= 0;
else
downstream_rdempty_delayed_n <= !downstream_rdempty;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
upstream_write_almost_full_delayed <= 0;
else
upstream_write_almost_full_delayed <= upstream_write_almost_full;
end
assign master_byte_address = {internal_master_address, 2'b0};
assign master_address = master_byte_address;
//the_upstream_fifo, which is an e_instance
peripheral_clock_crossing_upstream_fifo the_upstream_fifo
(
.aclr (~master_reset_n),
.data (upstream_data_in),
.q (upstream_data_out),
.rdclk (slave_clk),
.rdempty (upstream_rdempty),
.rdreq (upstream_rdreq),
.wrclk (master_clk),
.wrreq (upstream_wrreq),
.wrusedw (upstream_wrusedw)
);
assign upstream_wrreq = master_readdatavalid;
assign upstream_rdreq = !upstream_rdempty;
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_readdatavalid <= 0;
else
slave_readdatavalid <= !upstream_rdempty;
end
endmodule
|
/**
* @module mips
* @author sabertazimi
* @email [email protected]
* @param DATA_WIDTH data width
* @param CODE_FILE rom code static path
* @param IM_BUS_WIDTH instrution rom address width
* @param DM_BUS_WIDTH data ram address width
* @param CLK_HZ cpu hz
* @input raw_X input of control signal
* @input switch_X switch to change led data display
* @output anodes anodes binding
* @output cnodes cnodes binding
*/
module mips
#(parameter DATA_WIDTH = 32, CODE_FILE = "~/Work/Source/architecture/design/verilog/mips/benchmarkpp.hex", IM_BUS_WIDTH = 10, DM_BUS_WIDTH = 10, CLK_HZ = 18)
(
input raw_clk,
input raw_rst,
input raw_en,
input switch_rst,
input switch_stat,
input switch_ram,
input switch_correctprediction,
input switch_misprediction,
input switch_loaduse,
input switch_branchstall,
input [4:0] switch_addr,
output [7:0] anodes,
output [7:0] cnodes
);
`include "defines.vh"
///< wire declaration
/// clock divider
wire [DATA_WIDTH-1:0] clk_group;
// clock halt unit
wire [DATA_WIDTH-1:0] latch_out;
wire clk_count;
wire clk;
// pc update unit
wire [DATA_WIDTH-1:0] IF_pc;
wire [DATA_WIDTH-1:0] IF_pc_next;
wire [DATA_WIDTH-1:0] IF_predict_addr;
wire [DATA_WIDTH-1:0] IF_mispredict_fix_addr;
wire [`BTB_PREDICT_SIZE-1:0] IF_taken;
// instruction memory
wire [DATA_WIDTH-1:0] IF_ir;
/// IF/ID
wire [DATA_WIDTH-1:0] ID_pc, ID_ir;
wire ID_taken;
// instruction decoder
wire [5:0] ID_op;
wire [4:0] ID_raw_rs;
wire [4:0] ID_rt;
wire [4:0] ID_rd;
wire [4:0] ID_sham;
wire [5:0] ID_funct;
wire [15:0] ID_imm16;
wire [25:0] ID_imm26;
// control unit
wire [3:0] ID_aluop;
wire ID_alusrc;
wire ID_alusham;
wire ID_regdst;
wire ID_regwe;
wire ID_extop;
wire ID_ramtoreg;
wire ID_ramwe;
wire ID_beq;
wire ID_bne;
wire ID_bgtz;
wire ID_j;
wire ID_jal;
wire ID_jr;
wire ID_syscall;
wire ID_writetolo;
wire ID_lotoreg;
wire ID_rambyte;
// regfile
wire [DATA_WIDTH-1:0] ID_raw_r1;
wire [DATA_WIDTH-1:0] ID_raw_r2;
wire [DATA_WIDTH-1:0] v0_data;
wire [DATA_WIDTH-1:0] a0_data;
wire [4:0] ID_rs;
// prediction handle
wire ID_equal_address;
wire ID_success_prediction;
wire ID_misprediction;
// forward in ID stage
wire [DATA_WIDTH-1:0] ID_r1;
wire [DATA_WIDTH-1:0] ID_r2;
// branch judgement unit
wire ID_jmp_imm, ID_jmp_reg, ID_jmp_branch, ID_jmp_need_reg;
wire eq, less;
wire signed [DATA_WIDTH-1:0] ID_signed_r1;
wire signed [DATA_WIDTH-1:0] ID_signed_r2;
// branch address calculation unit
wire [DATA_WIDTH-1:0] ID_addr_imm;
wire [DATA_WIDTH-1:0] ID_addr_reg;
wire [DATA_WIDTH-1:0] ID_addr_branch;
wire [DATA_WIDTH-1:0] ID_extshft_imm16;
wire [DATA_WIDTH-1:0] ID_extshft_imm26;
/// ID/EX
wire [DATA_WIDTH-1:0] EX_pc;
wire [DATA_WIDTH-1:0] EX_ir;
wire EX_writetolo;
wire EX_regwe;
wire EX_ramtoreg;
wire EX_lotoreg;
wire EX_syscall;
wire EX_ramwe;
wire EX_rambyte;
wire EX_regdst;
wire [3:0] EX_aluop;
wire EX_alusrc;
wire EX_extop;
wire EX_alusham;
wire EX_jal;
wire [4:0] EX_rs;
wire [4:0] EX_rt;
wire [4:0] EX_rd;
wire [4:0] EX_sham;
wire [15:0] EX_imm16;
wire [DATA_WIDTH-1:0] EX_r1;
wire [DATA_WIDTH-1:0] EX_r2;
// EX stage
wire [4:0] EX_RW;
wire [DATA_WIDTH-1:0] EX_raw_aluX;
wire [DATA_WIDTH-1:0] EX_raw_aluY;
wire [DATA_WIDTH-1:0] EX_unsigned_imm32;
wire [DATA_WIDTH-1:0] EX_signed_imm32;
wire [DATA_WIDTH-1:0] EX_imm32;
wire [DATA_WIDTH-1:0] EX_sham32;
wire [DATA_WIDTH-1:0] EX_aluX;
wire [DATA_WIDTH-1:0] EX_aluY;
wire [DATA_WIDTH-1:0] EX_result;
/// EX_MEM
wire [DATA_WIDTH-1:0] MEM_pc;
wire [DATA_WIDTH-1:0] MEM_ir;
wire MEM_writetolo;
wire MEM_regwe;
wire MEM_ramtoreg;
wire MEM_lotoreg;
wire MEM_syscall;
wire MEM_ramwe;
wire MEM_rambyte;
wire [4:0] MEM_rt;
wire [DATA_WIDTH-1:0] MEM_result;
wire [4:0] MEM_RW;
wire [DATA_WIDTH-1:0] MEM_r2;
// MEM stage
wire [DATA_WIDTH-1:0] MEM_wdata;
wire [DATA_WIDTH-1:0] MEM_raw_ramdata;
wire [1:0] MEM_byteaddr;
wire [7:0] MEM_bytedata8;
wire [DATA_WIDTH-1:0] MEM_bytedata32;
wire [DATA_WIDTH-1:0] MEM_ramdata;
/// MEM/WB
wire [DATA_WIDTH-1:0] WB_pc;
wire [DATA_WIDTH-1:0] WB_ir;
wire WB_writetolo;
wire WB_regwe;
wire WB_ramtoreg;
wire WB_lotoreg;
wire WB_syscall;
wire [DATA_WIDTH-1:0] WB_ramdata;
wire [DATA_WIDTH-1:0] WB_result;
wire [4:0] WB_RW;
// WB stage
wire [DATA_WIDTH-1:0] WB_lodata;
wire [DATA_WIDTH-1:0] WB_regdata;
// forward unit
wire [1:0] ID_forwardA;
wire [1:0] ID_forwardB;
wire [1:0] EX_forwardA;
wire [1:0] EX_forwardB;
wire MEM_forward;
// bubble detection
wire load_use_hazard;
wire branch_flushD;
wire branch_flushE;
wire stall;
wire flushD;
wire flushE;
// syscall unit
wire equal_ten;
wire halt;
wire syscall_count;
// led unit
wire [DATA_WIDTH-1:0] led_data;
// statistic unit
wire [DATA_WIDTH-1:0] stat_count;
wire [DATA_WIDTH-1:0] stat_misprediction;
wire [DATA_WIDTH-1:0] stat_correctprediction;
wire [DATA_WIDTH-1:0] stat_flushD;
wire [DATA_WIDTH-1:0] stat_loaduse;
wire [DATA_WIDTH-1:0] stat_branchstall;
// memory direct output for led display
wire [DATA_WIDTH-1:0] ram_data;
///> wire declaration
/// clock divider
tick_divider #(
.DATA_WIDTH(DATA_WIDTH)
) clk_divider (
.clk_src(raw_clk),
.clk_group(clk_group)
);
///< IF stage
// clock halt unit
latch_counter #(
.DATA_WIDTH(DATA_WIDTH),
.MAX(1)
) latch_counter (
.clk(halt || switch_rst),
.rst(raw_rst),
.en(raw_en),
.count(latch_out)
);
counter clk_counter (
.clk(clk || switch_rst),
.rst(raw_rst),
.en(latch_out && raw_en),
.count(clk_count)
);
assign clk = clk_group[CLK_HZ] && ~clk_count;
// pc update unit
assign IF_mispredict_fix_addr = ID_jmp_branch ? ID_addr_branch : (ID_pc + 4);
assign IF_pc_next = ID_jmp_reg ? ID_addr_reg
: ID_misprediction ? IF_mispredict_fix_addr
: IF_predict_addr;
register #(
.DATA_WIDTH(DATA_WIDTH)
) PC (
.clk(clk || switch_rst),
.rst(raw_rst),
.en(stall && raw_en),
.din(IF_pc_next),
.dout(IF_pc)
);
// btb
wire IF_hit;
wire IF_branch;
wire [DATA_WIDTH-1:0] IF_predict_branch;
wire [DATA_WIDTH-1:0] ID_true_branch;
wire [DATA_WIDTH-1:0] btb_branch_addr;
branch_target_buffer btb (
.clk(clk || switch_rst),
.rst(raw_rst),
.en(stall && raw_en),
.IF_branch(IF_branch),
.ID_branch(ID_beq || ID_bne || ID_bgtz),
.misprediction(ID_misprediction),
.IF_branch_pc(IF_pc),
.IF_predict_addr(IF_predict_branch),
.ID_branch_pc(ID_pc),
.ID_branch_addr(ID_true_branch),
.taken(IF_taken),
.IF_hit(IF_hit),
.btb_branch_addr(btb_branch_addr)
);
branch_predictor #(
.DATA_WIDTH(DATA_WIDTH)
) branch_predictor (
.pc(IF_pc),
.ir(IF_ir),
.hit(IF_hit),
.btb_branch_addr(btb_branch_addr),
.IF_branch(IF_branch),
.IF_predict_branch(IF_predict_branch),
.predict_addr(IF_predict_addr)
);
// instruction memory
imem #(
.DATA_WIDTH(DATA_WIDTH),
.BUS_WIDTH(IM_BUS_WIDTH),
.CODE_FILE(CODE_FILE)
) imem (
.addr(IF_pc[11:2]),
.rdata(IF_ir)
);
///> IF stage
/// IF/ID
IF_ID #(
.DATA_WIDTH(DATA_WIDTH)
) IF_ID (
.clk(clk || switch_rst),
.rst(flushD || raw_rst),
.en(stall && raw_en),
.IF_PC(IF_pc),
.IF_IR(IF_ir),
.IF_taken(IF_taken[1]),
.ID_PC(ID_pc),
.ID_IR(ID_ir),
.ID_taken(ID_taken)
);
///< ID stage
// instruction decoder
decoder decoder (
.instruction(ID_ir),
.op(ID_op),
.rs(ID_raw_rs),
.rt(ID_rt),
.rd(ID_rd),
.sham(ID_sham),
.funct(ID_funct),
.imm16(ID_imm16),
.imm26(ID_imm26)
);
// control unit
controller controller (
.op(ID_op),
.funct(ID_funct),
.aluop(ID_aluop),
.alusrc(ID_alusrc),
.alusham(ID_alusham),
.regdst(ID_regdst),
.regwe(ID_regwe),
.extop(ID_extop),
.ramtoreg(ID_ramtoreg),
.ramwe(ID_ramwe),
.beq(ID_beq),
.bne(ID_bne),
.bgtz(ID_bgtz),
.j(ID_j),
.jal(ID_jal),
.jr(ID_jr),
.syscall(ID_syscall),
.writetolo(ID_writetolo),
.lotoreg(ID_lotoreg),
.rambyte(ID_rambyte)
);
// regfile
assign ID_rs = ID_alusham ? ID_rt : ID_raw_rs;
regfile #(
.DATA_WIDTH(DATA_WIDTH)
) regfile (
.clk(clk || switch_rst),
.rst(raw_rst),
.we(WB_regwe && raw_en),
.raddrA(ID_rs),
.raddrB(ID_rt),
.waddr(WB_RW),
.wdata(WB_regdata),
.regA(ID_raw_r1),
.regB(ID_raw_r2),
.v0_data(v0_data),
.a0_data(a0_data)
);
// prediction handle
assign ID_equal_address = (ID_jmp_branch == ID_taken);
assign ID_success_prediction = ID_equal_address && (ID_beq || ID_bne || ID_bgtz);
assign ID_misprediction = ~ID_equal_address && (ID_beq || ID_bne || ID_bgtz);
// forward in ID stage
assign ID_r1 = (ID_forwardA == 2'b10) ? MEM_result
: (ID_forwardA == 2'b01) ? WB_regdata
: ID_raw_r1;
assign ID_r2 = (ID_forwardB == 2'b10) ? MEM_result
: (ID_forwardB == 2'b01) ? WB_regdata
: ID_raw_r2;
// branch judgement unit
assign ID_signed_r1 = $signed(ID_r1);
assign ID_signed_r2 = $signed(ID_r2);
assign eq = (ID_r1 == ID_r2);
assign less = (ID_signed_r1 < ID_signed_r2);
assign ID_jmp_imm = ID_j || ID_jal;
assign ID_jmp_reg = ID_jr;
assign ID_jmp_branch = (ID_beq && eq) || (ID_bne && ~eq) || (ID_bgtz && ~eq && ~less);
assign ID_jmp_need_reg = ID_beq || ID_bne || ID_bgtz || ID_jr;
// branch address calculation unit
assign ID_addr_reg = ID_r1;
address_calculator #(
.DATA_WIDTH(DATA_WIDTH)
) ID_address_calculator (
.pc(ID_pc),
.imm16(ID_imm16),
.imm26(ID_imm26),
.addr_imm(ID_addr_imm),
.addr_branch(ID_addr_branch)
);
assign ID_true_branch = ID_jmp_branch ? ID_addr_branch : (ID_pc + 4);
///> ID stage
/// ID/EX
ID_EX #(
.DATA_WIDTH(DATA_WIDTH)
) ID_EX (
.clk(clk || switch_rst),
.rst(flushE || raw_rst),
.en(raw_en),
.ID_PC(ID_pc),
.ID_IR(ID_ir),
.ID_writetolo(ID_writetolo),
.ID_regwe(ID_regwe),
.ID_ramtoreg(ID_ramtoreg),
.ID_lotoreg(ID_lotoreg),
.ID_syscall(ID_syscall),
.ID_ramwe(ID_ramwe),
.ID_rambyte(ID_rambyte),
.ID_regdst(ID_regdst),
.ID_aluop(ID_aluop),
.ID_alusrc(ID_alusrc),
.ID_extop(ID_extop),
.ID_alusham(ID_alusham),
.ID_jal(ID_jal),
.ID_rs(ID_rs),
.ID_rt(ID_rt),
.ID_rd(ID_rd),
.ID_sham(ID_sham),
.ID_imm16(ID_imm16),
.ID_r1(ID_r1),
.ID_r2(ID_r2),
.EX_PC(EX_pc),
.EX_IR(EX_ir),
.EX_writetolo(EX_writetolo),
.EX_regwe(EX_regwe),
.EX_ramtoreg(EX_ramtoreg),
.EX_lotoreg(EX_lotoreg),
.EX_syscall(EX_syscall),
.EX_ramwe(EX_ramwe),
.EX_rambyte(EX_rambyte),
.EX_regdst(EX_regdst),
.EX_aluop(EX_aluop),
.EX_alusrc(EX_alusrc),
.EX_extop(EX_extop),
.EX_alusham(EX_alusham),
.EX_jal(EX_jal),
.EX_rs(EX_rs),
.EX_rt(EX_rt),
.EX_rd(EX_rd),
.EX_sham(EX_sham),
.EX_imm16(EX_imm16),
.EX_r1(EX_r1),
.EX_r2(EX_r2)
);
///< EX stage
assign EX_RW = EX_jal ? 5'h1f
: EX_regdst ? EX_rd
: EX_rt;
assign EX_raw_aluX = (EX_forwardA == 2'b10) ? MEM_result
: (EX_forwardA == 2'b01) ? WB_regdata
: EX_r1;
assign EX_raw_aluY = (EX_forwardB == 2'b10) ? MEM_result
: (EX_forwardB == 2'b01) ? WB_regdata
: EX_r2;
assign EX_unsigned_imm32 = {{(DATA_WIDTH-16){1'b0}}, EX_imm16};
assign EX_signed_imm32 = {{(DATA_WIDTH-16){EX_imm16[15]}}, EX_imm16};
assign EX_imm32 = EX_extop ? EX_signed_imm32 : EX_unsigned_imm32;
assign EX_sham32 = {{(DATA_WIDTH-5){1'b0}}, EX_sham};
assign EX_aluX = EX_jal ? EX_pc : EX_raw_aluX;
assign EX_aluY = EX_jal ? 32'h4
: EX_alusham ? EX_sham32
: EX_alusrc ? EX_imm32
: EX_raw_aluY;
// alu
alu #(
.DATA_WIDTH(DATA_WIDTH)
) alu (
.srcA(EX_aluX),
.srcB(EX_aluY),
.aluop(EX_aluop),
.aluout(EX_result),
.zero(),
.of(),
.uof()
);
///> EX stage
/// EX_MEM
EX_MEM #(
.DATA_WIDTH(DATA_WIDTH)
) EX_MEM (
.clk(clk || switch_rst),
.rst(raw_rst),
.en(raw_en),
.EX_PC(EX_pc),
.EX_IR(EX_ir),
.EX_writetolo(EX_writetolo),
.EX_regwe(EX_regwe),
.EX_ramtoreg(EX_ramtoreg),
.EX_lotoreg(EX_lotoreg),
.EX_syscall(EX_syscall),
.EX_ramwe(EX_ramwe),
.EX_rambyte(EX_rambyte),
.EX_rt(EX_rt),
.EX_result(EX_result),
.EX_RW(EX_RW),
.EX_r2(EX_r2),
.MEM_PC(MEM_pc),
.MEM_IR(MEM_ir),
.MEM_writetolo(MEM_writetolo),
.MEM_regwe(MEM_regwe),
.MEM_ramtoreg(MEM_ramtoreg),
.MEM_lotoreg(MEM_lotoreg),
.MEM_syscall(MEM_syscall),
.MEM_ramwe(MEM_ramwe),
.MEM_rambyte(MEM_rambyte),
.MEM_rt(MEM_rt),
.MEM_result(MEM_result),
.MEM_RW(MEM_RW),
.MEM_r2(MEM_r2)
);
///< MEM stage
assign MEM_wdata = MEM_forward ? WB_regdata : MEM_r2;
dmem #(
.DATA_WIDTH(DATA_WIDTH),
.BUS_WIDTH(DM_BUS_WIDTH)
) dmem (
.clk(clk || switch_rst),
.re(MEM_ramtoreg),
.we(MEM_ramwe && ~halt && raw_en),
.addr(MEM_result[25:2]),
.wdata(MEM_wdata),
.switch_addr(switch_addr),
.rdata(MEM_raw_ramdata),
.led_data(ram_data)
);
assign MEM_byteaddr = MEM_result[1:0];
assign MEM_bytedata8 = (MEM_byteaddr == 2'b00) ? MEM_raw_ramdata[7:0]
: (MEM_byteaddr == 2'b01) ? MEM_raw_ramdata[15:8]
: (MEM_byteaddr == 2'b10) ? MEM_raw_ramdata[23:16]
: MEM_raw_ramdata[31:24];
assign MEM_bytedata32 = {{(DATA_WIDTH-8){MEM_bytedata8[7]}}, MEM_bytedata8};
assign MEM_ramdata = MEM_rambyte ? MEM_bytedata32 : MEM_raw_ramdata;
///> MEM stage
/// MEM/WB
MEM_WB #(
.DATA_WIDTH(DATA_WIDTH)
) MEM_WB (
.clk(clk || switch_rst),
.rst(raw_rst),
.en(raw_en),
.MEM_PC(MEM_pc),
.MEM_IR(MEM_ir),
.MEM_writetolo(MEM_writetolo),
.MEM_regwe(MEM_regwe),
.MEM_ramtoreg(MEM_ramtoreg),
.MEM_lotoreg(MEM_lotoreg),
.MEM_syscall(MEM_syscall),
.MEM_ramdata(MEM_ramdata),
.MEM_result(MEM_result),
.MEM_RW(MEM_RW),
.WB_PC(WB_pc),
.WB_IR(WB_ir),
.WB_writetolo(WB_writetolo),
.WB_regwe(WB_regwe),
.WB_ramtoreg(WB_ramtoreg),
.WB_lotoreg(WB_lotoreg),
.WB_syscall(WB_syscall),
.WB_ramdata(WB_ramdata),
.WB_result(WB_result),
.WB_RW(WB_RW)
);
///< WB stage
register #(
.DATA_WIDTH(DATA_WIDTH)
) LO (
.clk(clk || switch_rst),
.rst(raw_rst),
.en(WB_writetolo && raw_en),
.din(MEM_result),
.dout(WB_lodata)
);
assign WB_regdata = WB_lotoreg ? WB_lodata
: WB_ramtoreg ? WB_ramdata
: WB_result;
///> WB stage
// forward unit
forward_unit forward_unit (
.ID_rs(ID_rs),
.ID_rt(ID_rt),
.EX_rs(EX_rs),
.EX_rt(EX_rt),
.MEM_rt(MEM_rt),
.MEM_ramwe(MEM_ramwe),
.MEM_regwe(MEM_regwe),
.WB_regwe(WB_regwe),
.MEM_RW(MEM_RW),
.WB_RW(WB_RW),
.ID_forwardA(ID_forwardA),
.ID_forwardB(ID_forwardB),
.EX_forwardA(EX_forwardA),
.EX_forwardB(EX_forwardB),
.MEM_forward(MEM_forward)
);
// bubble detection
load_use_detector load_use_detector (
.ID_rs(ID_rs),
.ID_rt(ID_rt),
.EX_rt(EX_rt),
.EX_ramtoreg(EX_ramtoreg),
.load_use_hazard(load_use_hazard)
);
branch_hazard_detector branch_hazard_detector (
.ID_rs(ID_rs),
.ID_rt(ID_rt),
.EX_regwe(EX_regwe),
.EX_RW(EX_RW),
.MEM_ramtoreg(MEM_ramtoreg),
.MEM_RW(MEM_RW),
.ID_jmp_need_reg(ID_jmp_need_reg),
.ID_jmp_reg(ID_jmp_reg),
.ID_misprediction(ID_misprediction),
.branch_flushD(branch_flushD),
.branch_flushE(branch_flushE)
);
assign stall = ~(load_use_hazard || branch_flushE);
assign flushD = branch_flushD;
assign flushE = load_use_hazard || branch_flushE;
// syscall unit
assign equal_ten = (v0_data == 32'ha);
assign halt = WB_syscall && equal_ten;
register #(
.DATA_WIDTH(1)
) syscall_register (
.clk(clk || switch_rst),
.rst(raw_rst),
.en(~equal_ten && WB_syscall && raw_en),
.din(1),
.dout(syscall_count)
);
// statistic unit
counter #(
.DATA_WIDTH(DATA_WIDTH),
.STEP(1)
) stat_counter (
.clk(clk || switch_rst),
.rst(raw_rst),
.en(raw_en),
.count(stat_count)
);
counter #(
.DATA_WIDTH(DATA_WIDTH),
.STEP(1)
) stat_mispredictor (
.clk(clk || switch_rst),
.rst(raw_rst),
.en(stall && ID_misprediction && raw_en),
.count(stat_misprediction)
);
counter #(
.DATA_WIDTH(DATA_WIDTH),
.STEP(1)
) stat_correctpredictor (
.clk(clk || switch_rst),
.rst(raw_rst),
.en(stall && (ID_success_prediction || ID_j || ID_jal) && raw_en),
.count(stat_correctprediction)
);
counter #(
.DATA_WIDTH(DATA_WIDTH),
.STEP(1)
) stat_flushDer (
.clk(clk || switch_rst),
.rst(raw_rst),
.en(stall && flushD && raw_en),
.count(stat_flushD)
);
counter #(
.DATA_WIDTH(DATA_WIDTH),
.STEP(1)
) stat_loaduser (
.clk(clk || switch_rst),
.rst(raw_rst),
.en(load_use_hazard && raw_en),
.count(stat_loaduse)
);
counter #(
.DATA_WIDTH(DATA_WIDTH),
.STEP(1)
) stat_branchstaller (
.clk(clk || switch_rst),
.rst(raw_rst),
.en(branch_flushE && raw_en),
.count(stat_branchstall)
);
// led unit
assign led_data = switch_stat ? stat_count
: switch_ram ? ram_data
: switch_correctprediction ? stat_correctprediction
: switch_misprediction ? stat_misprediction
: switch_loaduse ? stat_loaduse
: switch_branchstall ? stat_branchstall
: syscall_count ? a0_data
: 0;
led_unit #(
.DATA_WIDTH(DATA_WIDTH)
) led_unit (
.clk_src(clk_group[15]),
.led_data(led_data),
.anodes(anodes),
.cnodes(cnodes)
);
endmodule // mips
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FA_BEHAVIORAL_V
`define SKY130_FD_SC_LS__FA_BEHAVIORAL_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fa (
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT;
wire or2_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT, and1_out, and0_out);
buf buf0 (COUT , or1_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out);
buf buf1 (SUM , or2_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FA_BEHAVIORAL_V |
module CPU(reset, clk);
input reset, clk;
// PC.
reg [31:0] PC;
wire [31:0] PC_next;
always @(posedge reset or posedge clk)
if (reset)
PC <= 32'h00000000;
else
PC <= PC_next;
wire [31:0] PC_plus_4;
assign PC_plus_4 = PC + 32'd4;
// Read instruction.
wire [31:0] Instruction;
InstructionMemory instruction_memory1(.Address(PC), .Instruction(Instruction));
// Generate control signals.
wire [1:0] RegDst;
wire [1:0] PCSrc;
wire Branch;
wire MemRead;
wire [1:0] MemtoReg;
wire [3:0] ALUOp;
wire ExtOp;
wire LuOp;
wire MemWrite;
wire ALUSrc1;
wire ALUSrc2;
wire RegWrite;
Control control1(
.OpCode(Instruction[31:26]), .Funct(Instruction[5:0]),
.PCSrc(PCSrc), .Branch(Branch), .RegWrite(RegWrite), .RegDst(RegDst),
.MemRead(MemRead), .MemWrite(MemWrite), .MemtoReg(MemtoReg),
.ALUSrc1(ALUSrc1), .ALUSrc2(ALUSrc2), .ExtOp(ExtOp), .LuOp(LuOp), .ALUOp(ALUOp));
// Register file.
wire [31:0] Databus1, Databus2, Databus3;
wire [4:0] Write_register;
assign Write_register = (RegDst == 2'b00)? Instruction[20:16]: (RegDst == 2'b01)? Instruction[15:11]: 5'b11111;
RegisterFile register_file1(.reset(reset), .clk(clk), .RegWrite(RegWrite),
.Read_register1(Instruction[25:21]), .Read_register2(Instruction[20:16]), .Write_register(Write_register),
.Write_data(Databus3), .Read_data1(Databus1), .Read_data2(Databus2));
// Immediate.
wire [31:0] Ext_out;
assign Ext_out = {ExtOp? {16{Instruction[15]}}: 16'h0000, Instruction[15:0]};
wire [31:0] LU_out;
assign LU_out = LuOp? {Instruction[15:0], 16'h0000}: Ext_out;
// ALU Control.
wire [4:0] ALUCtl;
wire Sign;
ALUControl alu_control1(.ALUOp(ALUOp), .Funct(Instruction[5:0]), .ALUCtl(ALUCtl), .Sign(Sign));
// ALU.
wire [31:0] ALU_in1;
wire [31:0] ALU_in2;
wire [31:0] ALU_out;
wire Zero;
assign ALU_in1 = ALUSrc1? {17'h00000, Instruction[10:6]}: Databus1;
assign ALU_in2 = ALUSrc2? LU_out: Databus2;
ALU alu1(.in1(ALU_in1), .in2(ALU_in2), .ALUCtl(ALUCtl), .Sign(Sign), .out(ALU_out), .zero(Zero));
// Memory.
wire [31:0] Read_data;
DataMemory data_memory1(.reset(reset), .clk(clk), .Address(ALU_out), .Write_data(Databus2), .Read_data(Read_data), .MemRead(MemRead), .MemWrite(MemWrite));
assign Databus3 = (MemtoReg == 2'b00)? ALU_out: (MemtoReg == 2'b01)? Read_data: PC_plus_4;
// Jump.
wire [31:0] Jump_target;
assign Jump_target = {PC_plus_4[31:28], Instruction[25:0], 2'b00};
// Branch.
wire [31:0] Branch_target;
assign Branch_target = (Branch & Zero)? PC_plus_4 + {LU_out[29:0], 2'b00}: PC_plus_4;
// Branch or PC + 4 / j / jr.
assign PC_next = (PCSrc == 2'b00)? Branch_target: (PCSrc == 2'b01)? Jump_target: Databus1;
endmodule
|
// Actel Corporation Proprietary and Confidential
// Copyright 2008 Actel Corporation. All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Revision Information:
// SVN Revision Information:
// SVN $Revision: 11864 $
// SVN $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $
`timescale 1ns/100ps
module
BFM_APBSLAVEEXT
(
PCLK
,
PRESETN
,
PENABLE
,
PWRITE
,
PSEL
,
PADDR
,
PWDATA
,
PRDATA
,
PREADY
,
PSLVERR
,
EXT_EN
,
EXT_WR
,
EXT_RD
,
EXT_ADDR
,
EXT_DATA
)
;
parameter
AWIDTH
=
10
;
parameter
DEPTH
=
256
;
parameter
DWIDTH
=
32
;
parameter
EXT_SIZE
=
2
;
parameter
INITFILE
=
" "
;
parameter
ID
=
0
;
parameter
TPD
=
1
;
parameter
ENFUNC
=
0
;
parameter
DEBUG
=
0
;
// Actel Corporation Proprietary and Confidential
// Copyright 2008 Actel Corporation. All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Revision Information:
// SVN Revision Information:
// SVN $Revision: 11864 $
// SVN $Date: 2010-01-22 06:51:45 +0000 (Fri, 22 Jan 2010) $
localparam
BFMA1I11
=
22
;
localparam
BFMA1l11
=
0
;
localparam
BFMA1OOOI
=
4
;
localparam
BFMA1IOOI
=
8
;
localparam
BFMA1lOOI
=
12
;
localparam
BFMA1OIOI
=
16
;
localparam
BFMA1IIOI
=
20
;
localparam
BFMA1lIOI
=
24
;
localparam
BFMA1OlOI
=
28
;
localparam
BFMA1IlOI
=
32
;
localparam
BFMA1llOI
=
36
;
localparam
BFMA1O0OI
=
40
;
localparam
BFMA1I0OI
=
44
;
localparam
BFMA1l0OI
=
48
;
localparam
BFMA1O1OI
=
52
;
localparam
BFMA1I1OI
=
56
;
localparam
BFMA1l1OI
=
60
;
localparam
BFMA1OOII
=
64
;
localparam
BFMA1IOII
=
68
;
localparam
BFMA1lOII
=
72
;
localparam
BFMA1OIII
=
76
;
localparam
BFMA1IIII
=
80
;
localparam
BFMA1lIII
=
100
;
localparam
BFMA1OlII
=
101
;
localparam
BFMA1IlII
=
102
;
localparam
BFMA1llII
=
103
;
localparam
BFMA1O0II
=
104
;
localparam
BFMA1I0II
=
105
;
localparam
BFMA1l0II
=
106
;
localparam
BFMA1O1II
=
107
;
localparam
BFMA1I1II
=
108
;
localparam
BFMA1l1II
=
109
;
localparam
BFMA1OOlI
=
110
;
localparam
BFMA1IOlI
=
111
;
localparam
BFMA1lOlI
=
112
;
localparam
BFMA1OIlI
=
113
;
localparam
BFMA1IIlI
=
114
;
localparam
BFMA1lIlI
=
115
;
localparam
BFMA1OllI
=
128
;
localparam
BFMA1IllI
=
129
;
localparam
BFMA1lllI
=
130
;
localparam
BFMA1O0lI
=
131
;
localparam
BFMA1I0lI
=
132
;
localparam
BFMA1l0lI
=
133
;
localparam
BFMA1O1lI
=
134
;
localparam
BFMA1I1lI
=
135
;
localparam
BFMA1l1lI
=
136
;
localparam
BFMA1OO0I
=
137
;
localparam
BFMA1IO0I
=
138
;
localparam
BFMA1lO0I
=
139
;
localparam
BFMA1OI0I
=
140
;
localparam
BFMA1II0I
=
141
;
localparam
BFMA1lI0I
=
142
;
localparam
BFMA1Ol0I
=
150
;
localparam
BFMA1Il0I
=
151
;
localparam
BFMA1ll0I
=
152
;
localparam
BFMA1O00I
=
153
;
localparam
BFMA1I00I
=
154
;
localparam
BFMA1l00I
=
160
;
localparam
BFMA1O10I
=
161
;
localparam
BFMA1I10I
=
162
;
localparam
BFMA1l10I
=
163
;
localparam
BFMA1OO1I
=
164
;
localparam
BFMA1IO1I
=
165
;
localparam
BFMA1lO1I
=
166
;
localparam
BFMA1OI1I
=
167
;
localparam
BFMA1II1I
=
168
;
localparam
BFMA1lI1I
=
169
;
localparam
BFMA1Ol1I
=
170
;
localparam
BFMA1Il1I
=
171
;
localparam
BFMA1ll1I
=
172
;
localparam
BFMA1O01I
=
200
;
localparam
BFMA1I01I
=
201
;
localparam
BFMA1l01I
=
202
;
localparam
BFMA1O11I
=
203
;
localparam
BFMA1I11I
=
204
;
localparam
BFMA1l11I
=
205
;
localparam
BFMA1OOOl
=
206
;
localparam
BFMA1IOOl
=
207
;
localparam
BFMA1lOOl
=
208
;
localparam
BFMA1OIOl
=
209
;
localparam
BFMA1IIOl
=
210
;
localparam
BFMA1lIOl
=
211
;
localparam
BFMA1OlOl
=
212
;
localparam
BFMA1IlOl
=
213
;
localparam
BFMA1llOl
=
214
;
localparam
BFMA1O0Ol
=
215
;
localparam
BFMA1I0Ol
=
216
;
localparam
BFMA1l0Ol
=
217
;
localparam
BFMA1O1Ol
=
218
;
localparam
BFMA1I1Ol
=
219
;
localparam
BFMA1l1Ol
=
220
;
localparam
BFMA1OOIl
=
221
;
localparam
BFMA1IOIl
=
222
;
localparam
BFMA1lOIl
=
250
;
localparam
BFMA1OIIl
=
251
;
localparam
BFMA1IIIl
=
252
;
localparam
BFMA1lIIl
=
253
;
localparam
BFMA1OlIl
=
254
;
localparam
BFMA1IlIl
=
255
;
localparam
BFMA1llIl
=
1001
;
localparam
BFMA1O0Il
=
1002
;
localparam
BFMA1I0Il
=
1003
;
localparam
BFMA1l0Il
=
1004
;
localparam
BFMA1O1Il
=
1005
;
localparam
BFMA1I1Il
=
1006
;
localparam
BFMA1l1Il
=
1007
;
localparam
BFMA1OOll
=
1008
;
localparam
BFMA1IOll
=
1009
;
localparam
BFMA1lOll
=
1010
;
localparam
BFMA1OIll
=
1011
;
localparam
BFMA1IIll
=
1012
;
localparam
BFMA1lIll
=
1013
;
localparam
BFMA1Olll
=
1014
;
localparam
BFMA1Illl
=
1015
;
localparam
BFMA1llll
=
1016
;
localparam
BFMA1O0ll
=
1017
;
localparam
BFMA1I0ll
=
1018
;
localparam
BFMA1l0ll
=
1019
;
localparam
BFMA1O1ll
=
1020
;
localparam
BFMA1I1ll
=
1021
;
localparam
BFMA1l1ll
=
1022
;
localparam
BFMA1OO0l
=
1023
;
localparam
BFMA1IO0l
=
0
;
localparam
BFMA1lO0l
=
1
;
localparam
BFMA1OI0l
=
2
;
localparam
BFMA1II0l
=
3
;
localparam
BFMA1lI0l
=
4
;
localparam
BFMA1Ol0l
=
5
;
localparam
BFMA1Il0l
=
6
;
localparam
BFMA1ll0l
=
7
;
localparam
BFMA1O00l
=
8
;
localparam
BFMA1I00l
=
0
;
localparam
BFMA1l00l
=
1
;
localparam
BFMA1O10l
=
2
;
localparam
BFMA1I10l
=
3
;
localparam
BFMA1l10l
=
4
;
localparam
BFMA1OO1l
=
32
'h
00000000
;
localparam
BFMA1IO1l
=
32
'h
00002000
;
localparam
BFMA1lO1l
=
32
'h
00004000
;
localparam
BFMA1OI1l
=
32
'h
00006000
;
localparam
BFMA1II1l
=
32
'h
00008000
;
localparam
[
1
:
0
]
BFMA1lI1l
=
0
;
localparam
[
1
:
0
]
BFMA1Ol1l
=
1
;
localparam
[
1
:
0
]
BFMA1Il1l
=
2
;
localparam
[
1
:
0
]
BFMA1ll1l
=
3
;
function
integer
BFMA1O01l
;
input
[
31
:
0
]
BFMA1I01l
;
integer
BFMA1ll1l
;
begin
BFMA1ll1l
=
BFMA1I01l
;
BFMA1O01l
=
BFMA1ll1l
;
end
endfunction
function
integer
to_int_unsigned
;
input
[
31
:
0
]
BFMA1I01l
;
integer
BFMA1I01l
;
integer
BFMA1ll1l
;
begin
BFMA1ll1l
=
BFMA1I01l
;
to_int_unsigned
=
BFMA1ll1l
;
end
endfunction
function
integer
to_int_signed
;
input
[
31
:
0
]
BFMA1I01l
;
integer
BFMA1ll1l
;
begin
BFMA1ll1l
=
BFMA1I01l
;
to_int_signed
=
BFMA1ll1l
;
end
endfunction
function
[
31
:
0
]
to_slv32
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
reg
[
31
:
0
]
BFMA1I01l
;
begin
BFMA1I01l
=
BFMA1ll1l
;
to_slv32
=
BFMA1I01l
;
end
endfunction
function
[
31
:
0
]
BFMA1l01l
;
input
[
2
:
0
]
BFMA1O11l
;
input
[
1
:
0
]
BFMA1I11l
;
input
[
31
:
0
]
BFMA1l11l
;
input
BFMA1OOO0
;
integer
BFMA1OOO0
;
reg
[
31
:
0
]
BFMA1IOO0
;
reg
BFMA1lOO0
;
begin
BFMA1IOO0
=
{
32
{
1
'b
0
}
}
;
case
(
BFMA1OOO0
)
0
:
begin
case
(
BFMA1O11l
)
3
'b
000
:
begin
case
(
BFMA1I11l
)
2
'b
00
:
begin
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
01
:
begin
BFMA1IOO0
[
15
:
8
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
10
:
begin
BFMA1IOO0
[
23
:
16
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
11
:
begin
BFMA1IOO0
[
31
:
24
]
=
BFMA1l11l
[
7
:
0
]
;
end
default
:
begin
end
endcase
end
3
'b
001
:
begin
case
(
BFMA1I11l
)
2
'b
00
:
begin
BFMA1IOO0
[
15
:
0
]
=
BFMA1l11l
[
15
:
0
]
;
end
2
'b
01
:
begin
BFMA1IOO0
[
15
:
0
]
=
BFMA1l11l
[
15
:
0
]
;
$display
(
"BFM: Missaligned AHB Cycle(Half A10=01) ? (WARNING)"
)
;
end
2
'b
10
:
begin
BFMA1IOO0
[
31
:
16
]
=
BFMA1l11l
[
15
:
0
]
;
end
2
'b
11
:
begin
BFMA1IOO0
[
31
:
16
]
=
BFMA1l11l
[
15
:
0
]
;
$display
(
"BFM: Missaligned AHB Cycle(Half A10=11) ? (WARNING)"
)
;
end
default
:
begin
end
endcase
end
3
'b
010
:
begin
BFMA1IOO0
=
BFMA1l11l
;
case
(
BFMA1I11l
)
2
'b
00
:
begin
end
2
'b
01
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Word A10=01) ? (WARNING)"
)
;
end
2
'b
10
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Word A10=10) ? (WARNING)"
)
;
end
2
'b
11
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Word A10=11) ? (WARNING)"
)
;
end
default
:
begin
end
endcase
end
default
:
begin
$display
(
"Unexpected AHB Size setting (ERROR)"
)
;
end
endcase
end
1
:
begin
case
(
BFMA1O11l
)
3
'b
000
:
begin
case
(
BFMA1I11l
)
2
'b
00
:
begin
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
01
:
begin
BFMA1IOO0
[
15
:
8
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
10
:
begin
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
7
:
0
]
;
end
2
'b
11
:
begin
BFMA1IOO0
[
15
:
8
]
=
BFMA1l11l
[
7
:
0
]
;
end
default
:
begin
end
endcase
end
3
'b
001
:
begin
BFMA1IOO0
[
15
:
0
]
=
BFMA1l11l
[
15
:
0
]
;
case
(
BFMA1I11l
)
2
'b
00
:
begin
end
2
'b
01
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Half A10=01) ? (WARNING)"
)
;
end
2
'b
10
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Half A10=10) ? (WARNING)"
)
;
end
2
'b
11
:
begin
$display
(
"BFM: Missaligned AHB Cycle(Half A10=11) ? (WARNING)"
)
;
end
default
:
begin
end
endcase
end
default
:
begin
$display
(
"Unexpected AHB Size setting (ERROR)"
)
;
end
endcase
end
2
:
begin
case
(
BFMA1O11l
)
3
'b
000
:
begin
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
7
:
0
]
;
end
default
:
begin
$display
(
"Unexpected AHB Size setting (ERROR)"
)
;
end
endcase
end
8
:
begin
BFMA1IOO0
=
BFMA1l11l
;
end
default
:
begin
$display
(
"Illegal Alignment mode (ERROR)"
)
;
end
endcase
BFMA1l01l
=
BFMA1IOO0
;
end
endfunction
function
[
31
:
0
]
BFMA1OIO0
;
input
[
2
:
0
]
BFMA1O11l
;
input
[
1
:
0
]
BFMA1I11l
;
input
[
31
:
0
]
BFMA1l11l
;
input
BFMA1OOO0
;
integer
BFMA1OOO0
;
reg
[
31
:
0
]
BFMA1IOO0
;
begin
BFMA1IOO0
=
BFMA1l01l
(
BFMA1O11l
,
BFMA1I11l
,
BFMA1l11l
,
BFMA1OOO0
)
;
BFMA1OIO0
=
BFMA1IOO0
;
end
endfunction
function
[
31
:
0
]
BFMA1IIO0
;
input
[
2
:
0
]
BFMA1O11l
;
input
[
1
:
0
]
BFMA1I11l
;
input
[
31
:
0
]
BFMA1l11l
;
input
BFMA1OOO0
;
integer
BFMA1OOO0
;
reg
[
31
:
0
]
BFMA1IOO0
;
reg
BFMA1lOO0
;
begin
if
(
BFMA1OOO0
==
8
)
begin
BFMA1IOO0
=
BFMA1l11l
;
end
else
begin
BFMA1IOO0
=
0
;
BFMA1lOO0
=
BFMA1I11l
[
1
]
;
case
(
BFMA1O11l
)
3
'b
000
:
begin
case
(
BFMA1I11l
)
2
'b
00
:
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
7
:
0
]
;
2
'b
01
:
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
15
:
8
]
;
2
'b
10
:
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
23
:
16
]
;
2
'b
11
:
BFMA1IOO0
[
7
:
0
]
=
BFMA1l11l
[
31
:
24
]
;
default
:
begin
end
endcase
end
3
'b
001
:
begin
case
(
BFMA1lOO0
)
1
'b
0
:
BFMA1IOO0
[
15
:
0
]
=
BFMA1l11l
[
15
:
0
]
;
1
'b
1
:
BFMA1IOO0
[
15
:
0
]
=
BFMA1l11l
[
31
:
16
]
;
default
:
begin
end
endcase
end
3
'b
010
:
begin
BFMA1IOO0
=
BFMA1l11l
;
end
default
:
$display
(
"Unexpected AHB Size setting (ERROR)"
)
;
endcase
end
BFMA1IIO0
=
BFMA1IOO0
;
end
endfunction
function
integer
BFMA1lIO0
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
integer
BFMA1OlO0
;
begin
BFMA1OlO0
=
BFMA1ll1l
;
BFMA1lIO0
=
BFMA1OlO0
;
end
endfunction
function
integer
BFMA1IlO0
;
input
BFMA1O11l
;
integer
BFMA1O11l
;
integer
BFMA1OlO0
;
begin
case
(
BFMA1O11l
)
0
:
begin
BFMA1OlO0
=
'h
62
;
end
1
:
begin
BFMA1OlO0
=
'h
68
;
end
2
:
begin
BFMA1OlO0
=
'h
77
;
end
3
:
begin
BFMA1OlO0
=
'h
78
;
end
default
:
begin
BFMA1OlO0
=
'h
3f
;
end
endcase
BFMA1IlO0
=
BFMA1OlO0
;
end
endfunction
function
integer
BFMA1llO0
;
input
BFMA1O11l
;
integer
BFMA1O11l
;
input
BFMA1O0O0
;
integer
BFMA1O0O0
;
integer
BFMA1OlO0
;
begin
case
(
BFMA1O11l
)
0
:
begin
BFMA1OlO0
=
1
;
end
1
:
begin
BFMA1OlO0
=
2
;
end
2
:
begin
BFMA1OlO0
=
4
;
end
3
:
begin
BFMA1OlO0
=
BFMA1O0O0
;
end
default
:
begin
BFMA1OlO0
=
0
;
end
endcase
BFMA1llO0
=
BFMA1OlO0
;
end
endfunction
function
integer
BFMA1I0O0
;
input
BFMA1O11l
;
integer
BFMA1O11l
;
input
BFMA1l0O0
;
integer
BFMA1l0O0
;
reg
[
2
:
0
]
BFMA1OlO0
;
begin
case
(
BFMA1O11l
)
0
:
begin
BFMA1OlO0
=
3
'b
000
;
end
1
:
begin
BFMA1OlO0
=
3
'b
001
;
end
2
:
begin
BFMA1OlO0
=
3
'b
010
;
end
3
:
begin
BFMA1OlO0
=
BFMA1l0O0
;
end
default
:
begin
BFMA1OlO0
=
3
'b
XXX
;
end
endcase
BFMA1I0O0
=
BFMA1OlO0
;
end
endfunction
function
integer
BFMA1O1O0
;
input
BFMA1I1O0
;
integer
BFMA1I1O0
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
input
BFMA1l1O0
;
integer
BFMA1l1O0
;
input
BFMA1OOI0
;
integer
BFMA1OOI0
;
integer
BFMA1IOI0
;
reg
[
31
:
0
]
BFMA1lOI0
;
reg
[
31
:
0
]
BFMA1OII0
;
reg
[
31
:
0
]
BFMA1III0
;
integer
BFMA1lII0
;
reg
[
63
:
0
]
BFMA1OlI0
;
localparam
[
31
:
0
]
BFMA1IlI0
=
0
;
localparam
[
31
:
0
]
BFMA1llI0
=
1
;
begin
BFMA1lOI0
=
BFMA1ll1l
;
BFMA1OII0
=
BFMA1l1O0
;
BFMA1lII0
=
BFMA1l1O0
;
BFMA1III0
=
{
32
{
1
'b
0
}
}
;
case
(
BFMA1I1O0
)
BFMA1llIl
:
begin
BFMA1III0
=
0
;
end
BFMA1O0Il
:
begin
BFMA1III0
=
BFMA1lOI0
+
BFMA1OII0
;
end
BFMA1I0Il
:
begin
BFMA1III0
=
BFMA1lOI0
-
BFMA1OII0
;
end
BFMA1l0Il
:
begin
BFMA1OlI0
=
BFMA1lOI0
*
BFMA1OII0
;
BFMA1III0
=
BFMA1OlI0
[
31
:
0
]
;
end
BFMA1O1Il
:
begin
BFMA1III0
=
BFMA1lOI0
/
BFMA1OII0
;
end
BFMA1OOll
:
begin
BFMA1III0
=
BFMA1lOI0
&
BFMA1OII0
;
end
BFMA1IOll
:
begin
BFMA1III0
=
BFMA1lOI0
|
BFMA1OII0
;
end
BFMA1lOll
:
begin
BFMA1III0
=
BFMA1lOI0
^
BFMA1OII0
;
end
BFMA1OIll
:
begin
BFMA1III0
=
BFMA1lOI0
^
BFMA1OII0
;
end
BFMA1lIll
:
begin
if
(
BFMA1lII0
==
0
)
begin
BFMA1III0
=
BFMA1lOI0
;
end
else
begin
BFMA1III0
=
BFMA1lOI0
>>
BFMA1lII0
;
end
end
BFMA1IIll
:
begin
if
(
BFMA1lII0
==
0
)
begin
BFMA1III0
=
BFMA1lOI0
;
end
else
begin
BFMA1III0
=
BFMA1lOI0
<<
BFMA1lII0
;
end
end
BFMA1l1Il
:
begin
BFMA1OlI0
=
{
BFMA1IlI0
,
BFMA1llI0
}
;
if
(
BFMA1lII0
>
0
)
begin
begin
:
BFMA1O0I0
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
1
;
BFMA1I0I0
<=
BFMA1lII0
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1OlI0
=
BFMA1OlI0
[
31
:
0
]
*
BFMA1lOI0
;
end
end
end
BFMA1III0
=
BFMA1OlI0
[
31
:
0
]
;
end
BFMA1Olll
:
begin
if
(
BFMA1lOI0
==
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1Illl
:
begin
if
(
BFMA1lOI0
!=
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1llll
:
begin
if
(
BFMA1lOI0
>
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1O0ll
:
begin
if
(
BFMA1lOI0
<
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1I0ll
:
begin
if
(
BFMA1lOI0
>=
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1l0ll
:
begin
if
(
BFMA1lOI0
<=
BFMA1OII0
)
begin
BFMA1III0
=
BFMA1llI0
;
end
end
BFMA1I1Il
:
begin
BFMA1III0
=
BFMA1lOI0
%
BFMA1OII0
;
end
BFMA1O1ll
:
begin
if
(
BFMA1l1O0
<=
31
)
begin
BFMA1III0
=
BFMA1lOI0
;
BFMA1III0
[
BFMA1l1O0
]
=
1
'b
1
;
end
else
begin
$display
(
"Bit operation on bit >31 (FAILURE)"
)
;
$stop
;
end
end
BFMA1I1ll
:
begin
if
(
BFMA1l1O0
<=
31
)
begin
BFMA1III0
=
BFMA1lOI0
;
BFMA1III0
[
BFMA1l1O0
]
=
1
'b
0
;
end
else
begin
$display
(
"Bit operation on bit >31 (FAILURE)"
)
;
$stop
;
end
end
BFMA1l1ll
:
begin
if
(
BFMA1l1O0
<=
31
)
begin
BFMA1III0
=
BFMA1lOI0
;
BFMA1III0
[
BFMA1l1O0
]
=
~
BFMA1III0
[
BFMA1l1O0
]
;
end
else
begin
$display
(
"Bit operation on bit >31 (FAILURE)"
)
;
$stop
;
end
end
BFMA1OO0l
:
begin
if
(
BFMA1l1O0
<=
31
)
begin
BFMA1III0
=
0
;
BFMA1III0
[
0
]
=
BFMA1lOI0
[
BFMA1l1O0
]
;
end
else
begin
$display
(
"Bit operation on bit >31 (FAILURE)"
)
;
$stop
;
end
end
default
:
begin
$display
(
"Illegal Maths Operator (FAILURE)"
)
;
$stop
;
end
endcase
BFMA1IOI0
=
BFMA1III0
;
if
(
BFMA1OOI0
>=
4
)
begin
$display
(
"Calculated %d = %d (%d) %d"
,
BFMA1IOI0
,
BFMA1ll1l
,
BFMA1I1O0
,
BFMA1l1O0
)
;
end
BFMA1O1O0
=
BFMA1IOI0
;
end
endfunction
function
[
31
:
0
]
BFMA1l0I0
;
input
[
31
:
0
]
BFMA1ll1l
;
reg
[
31
:
0
]
BFMA1O1I0
;
begin
BFMA1O1I0
=
BFMA1ll1l
;
BFMA1O1I0
=
0
;
begin
:
BFMA1I1I0
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
31
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
if
(
(
BFMA1ll1l
[
BFMA1I0I0
]
)
==
1
'b
1
)
begin
BFMA1O1I0
[
BFMA1I0I0
]
=
1
'b
1
;
end
end
end
BFMA1l0I0
=
BFMA1O1I0
;
end
endfunction
function
integer
BFMA1l1I0
;
input
BFMA1OOl0
;
integer
BFMA1OOl0
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
integer
BFMA1IOl0
;
integer
BFMA1lOl0
;
begin
BFMA1lOl0
=
BFMA1OOl0
/
BFMA1ll1l
;
BFMA1IOl0
=
BFMA1OOl0
-
BFMA1lOl0
*
BFMA1ll1l
;
BFMA1l1I0
=
BFMA1IOl0
;
end
endfunction
function
integer
BFMA1OIl0
;
input
BFMA1OOl0
;
integer
BFMA1OOl0
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
integer
BFMA1IOl0
;
integer
BFMA1lOl0
;
begin
BFMA1lOl0
=
BFMA1OOl0
/
BFMA1ll1l
;
BFMA1IOl0
=
BFMA1OOl0
-
BFMA1lOl0
*
BFMA1ll1l
;
BFMA1OIl0
=
BFMA1lOl0
;
end
endfunction
function
integer
to_boolean
;
input
BFMA1ll1l
;
integer
BFMA1ll1l
;
integer
BFMA1IIl0
;
begin
BFMA1IIl0
=
0
;
if
(
BFMA1ll1l
!=
0
)
BFMA1IIl0
=
1
;
to_boolean
=
BFMA1IIl0
;
end
endfunction
function
integer
BFMA1lIl0
;
input
BFMA1Oll0
;
integer
BFMA1Oll0
;
reg
[
31
:
0
]
BFMA1Ill0
;
reg
[
31
:
0
]
BFMA1lll0
;
reg
BFMA1O0l0
;
begin
BFMA1Ill0
=
BFMA1Oll0
;
BFMA1O0l0
=
1
'b
1
;
BFMA1lll0
[
0
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
;
BFMA1lll0
[
1
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
0
]
;
BFMA1lll0
[
2
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
1
]
;
BFMA1lll0
[
3
]
=
BFMA1Ill0
[
2
]
;
BFMA1lll0
[
4
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
3
]
;
BFMA1lll0
[
5
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
4
]
;
BFMA1lll0
[
6
]
=
BFMA1Ill0
[
5
]
;
BFMA1lll0
[
7
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
6
]
;
BFMA1lll0
[
8
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
7
]
;
BFMA1lll0
[
9
]
=
BFMA1Ill0
[
8
]
;
BFMA1lll0
[
10
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
9
]
;
BFMA1lll0
[
11
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
10
]
;
BFMA1lll0
[
12
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
11
]
;
BFMA1lll0
[
13
]
=
BFMA1Ill0
[
12
]
;
BFMA1lll0
[
14
]
=
BFMA1Ill0
[
13
]
;
BFMA1lll0
[
15
]
=
BFMA1Ill0
[
14
]
;
BFMA1lll0
[
16
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
15
]
;
BFMA1lll0
[
17
]
=
BFMA1Ill0
[
16
]
;
BFMA1lll0
[
18
]
=
BFMA1Ill0
[
17
]
;
BFMA1lll0
[
19
]
=
BFMA1Ill0
[
18
]
;
BFMA1lll0
[
20
]
=
BFMA1Ill0
[
19
]
;
BFMA1lll0
[
21
]
=
BFMA1Ill0
[
20
]
;
BFMA1lll0
[
22
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
21
]
;
BFMA1lll0
[
23
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
22
]
;
BFMA1lll0
[
24
]
=
BFMA1Ill0
[
23
]
;
BFMA1lll0
[
25
]
=
BFMA1Ill0
[
24
]
;
BFMA1lll0
[
26
]
=
BFMA1O0l0
^
BFMA1Ill0
[
31
]
^
BFMA1Ill0
[
25
]
;
BFMA1lll0
[
27
]
=
BFMA1Ill0
[
26
]
;
BFMA1lll0
[
28
]
=
BFMA1Ill0
[
27
]
;
BFMA1lll0
[
29
]
=
BFMA1Ill0
[
28
]
;
BFMA1lll0
[
30
]
=
BFMA1Ill0
[
29
]
;
BFMA1lll0
[
31
]
=
BFMA1Ill0
[
30
]
;
BFMA1lIl0
=
BFMA1lll0
;
end
endfunction
function
integer
BFMA1I0l0
;
input
BFMA1Oll0
;
integer
BFMA1Oll0
;
input
BFMA1O11l
;
integer
BFMA1O11l
;
integer
BFMA1l0l0
;
integer
BFMA1I0I0
;
reg
[
31
:
0
]
BFMA1Ill0
;
begin
BFMA1Ill0
=
BFMA1Oll0
;
for
(
BFMA1I0I0
=
31
;
BFMA1I0I0
>=
BFMA1O11l
;
BFMA1I0I0
=
BFMA1I0I0
-
1
)
BFMA1Ill0
[
BFMA1I0I0
]
=
0
;
BFMA1l0l0
=
BFMA1Ill0
;
BFMA1I0l0
=
BFMA1l0l0
;
end
endfunction
function
integer
BFMA1O1l0
;
input
BFMA1Oll0
;
integer
BFMA1Oll0
;
input
BFMA1O11l
;
integer
BFMA1O11l
;
integer
BFMA1l0l0
;
reg
[
31
:
0
]
BFMA1Ill0
;
integer
BFMA1I1l0
;
integer
BFMA1I0I0
;
begin
case
(
BFMA1O11l
)
1
:
begin
BFMA1I1l0
=
0
;
end
2
:
begin
BFMA1I1l0
=
1
;
end
4
:
begin
BFMA1I1l0
=
2
;
end
8
:
begin
BFMA1I1l0
=
3
;
end
16
:
begin
BFMA1I1l0
=
4
;
end
32
:
begin
BFMA1I1l0
=
5
;
end
64
:
begin
BFMA1I1l0
=
6
;
end
128
:
begin
BFMA1I1l0
=
7
;
end
256
:
begin
BFMA1I1l0
=
8
;
end
512
:
begin
BFMA1I1l0
=
9
;
end
1024
:
begin
BFMA1I1l0
=
10
;
end
2048
:
begin
BFMA1I1l0
=
11
;
end
4096
:
begin
BFMA1I1l0
=
12
;
end
8192
:
begin
BFMA1I1l0
=
13
;
end
16384
:
begin
BFMA1I1l0
=
14
;
end
32768
:
begin
BFMA1I1l0
=
15
;
end
65536
:
begin
BFMA1I1l0
=
16
;
end
131072
:
BFMA1I1l0
=
17
;
262144
:
BFMA1I1l0
=
18
;
524288
:
BFMA1I1l0
=
19
;
1048576
:
BFMA1I1l0
=
20
;
2097152
:
BFMA1I1l0
=
21
;
4194304
:
BFMA1I1l0
=
22
;
8388608
:
BFMA1I1l0
=
23
;
16777216
:
BFMA1I1l0
=
24
;
33554432
:
BFMA1I1l0
=
25
;
67108864
:
BFMA1I1l0
=
26
;
134217728
:
BFMA1I1l0
=
27
;
268435456
:
BFMA1I1l0
=
28
;
536870912
:
BFMA1I1l0
=
29
;
1073741824
:
BFMA1I1l0
=
30
;
default
:
begin
$display
(
"Random function error (FAILURE)"
)
;
$finish
;
end
endcase
BFMA1Ill0
=
to_slv32
(
BFMA1Oll0
)
;
if
(
BFMA1I1l0
<
31
)
begin
for
(
BFMA1I0I0
=
31
;
BFMA1I0I0
>=
BFMA1I1l0
;
BFMA1I0I0
=
BFMA1I0I0
-
1
)
BFMA1Ill0
[
BFMA1I0I0
]
=
0
;
end
BFMA1l0l0
=
to_int_signed
(
BFMA1Ill0
)
;
BFMA1O1l0
=
BFMA1l0l0
;
end
endfunction
function
bound1k
;
input
BFMA1l1l0
;
integer
BFMA1l1l0
;
input
BFMA1OO00
;
integer
BFMA1OO00
;
reg
[
31
:
0
]
BFMA1IO00
;
reg
BFMA1lO00
;
begin
BFMA1IO00
=
BFMA1OO00
;
BFMA1lO00
=
0
;
case
(
BFMA1l1l0
)
0
:
begin
if
(
BFMA1IO00
[
9
:
0
]
==
10
'b
0000000000
)
begin
BFMA1lO00
=
1
;
end
end
1
:
begin
BFMA1lO00
=
1
;
end
2
:
begin
end
default
:
begin
$display
(
"Illegal Burst Boundary Set (FAILURE)"
)
;
$finish
;
end
endcase
bound1k
=
BFMA1lO00
;
end
endfunction
input
PCLK
;
input
PRESETN
;
input
PENABLE
;
input
PWRITE
;
input
PSEL
;
input
[
AWIDTH
-
1
:
0
]
PADDR
;
input
[
DWIDTH
-
1
:
0
]
PWDATA
;
output
[
DWIDTH
-
1
:
0
]
PRDATA
;
wire
[
DWIDTH
-
1
:
0
]
PRDATA
;
output
PREADY
;
wire
PREADY
;
output
PSLVERR
;
wire
PSLVERR
;
input
EXT_EN
;
input
EXT_WR
;
input
EXT_RD
;
input
[
AWIDTH
-
1
:
0
]
EXT_ADDR
;
inout
[
DWIDTH
-
1
:
0
]
EXT_DATA
;
reg
[
DWIDTH
-
1
:
0
]
BFMA1lI1II
;
integer
BFMA1Ol1II
=
DEBUG
;
wire
BFMA1O11lI
;
reg
BFMA1I11lI
;
reg
BFMA1l11lI
;
wire
BFMA1OOO0I
;
reg
BFMA1IOO0I
;
reg
BFMA1lOO0I
;
wire
BFMA1OIO0I
;
reg
BFMA1IIO0I
;
reg
BFMA1lIO0I
;
wire
[
AWIDTH
-
1
:
0
]
BFMA1OlO0I
;
reg
[
AWIDTH
-
1
:
0
]
BFMA1IlO0I
;
reg
[
AWIDTH
-
1
:
0
]
BFMA1llO0I
;
wire
[
DWIDTH
-
1
:
0
]
BFMA1O0O0I
;
reg
[
DWIDTH
-
1
:
0
]
BFMA1I0O0I
;
reg
[
DWIDTH
-
1
:
0
]
BFMA1l0O0I
;
reg
[
31
:
0
]
BFMA1l0III
;
reg
[
31
:
0
]
BFMA1O1O0I
;
reg
BFMA1I1O0I
;
reg
BFMA1l1O0I
;
parameter
BFMA1Il1
=
TPD
*
1
;
reg
[
31
:
0
]
BFMA1OOI0I
;
wire
[
31
:
0
]
BFMA1IlI0
;
assign
BFMA1IlI0
=
{
32
{
1
'b
0
}
}
;
reg
BFMA1OlOlI
;
initial
begin
BFMA1OlOlI
<=
1
'b
0
;
#
1
;
BFMA1OlOlI
<=
1
'b
1
;
end
always
@
(
posedge
PCLK
or
negedge
PRESETN
or
negedge
BFMA1OlOlI
)
begin
:
BFMA1I0OlI
integer
BFMA1l0OlI
;
reg
[
7
:
0
]
BFMA1l1OlI
[
0
:
DEPTH
-
1
]
;
integer
BFMA1OOIlI
;
reg
[
31
:
0
]
BFMA1IOIlI
;
reg
BFMA1lIIlI
;
integer
BFMA1l1IlI
;
integer
BFMA1OOllI
;
reg
[
31
:
0
]
BFMA1IOllI
;
reg
BFMA1OIllI
;
integer
BFMA1IIllI
;
integer
BFMA1IIIlI
;
integer
BFMA1IOI0I
;
reg
[
7
:
0
]
BFMA1O1I0
;
reg
BFMA1OIOOI
;
reg
BFMA1lIllI
;
reg
BFMA1OlllI
;
reg
BFMA1Oll1
;
reg
BFMA1IIOOI
;
integer
BFMA1ll11
;
integer
BFMA1IlllI
;
integer
BFMA1llllI
;
reg
[
1
:
(
80
)
*
8
]
BFMA1I011
;
reg
[
1
:
(
80
)
*
8
]
BFMA1O011
;
integer
BFMA1OO0lI
;
integer
BFMA1lOI0I
;
integer
BFMA1IO0lI
;
if
(
INITFILE
!=
8
'h
20
&&
BFMA1Oll1
==
0
&&
BFMA1OlOlI
==
1
'b
1
)
begin
$display
(
"Opening BFM APB Slave %0d Initialisation file %s"
,
ID
,
INITFILE
)
;
$readmemb
(
INITFILE
,
BFMA1l1OlI
)
;
BFMA1Oll1
=
1
;
end
if
(
BFMA1OlOlI
==
1
'b
0
)
begin
BFMA1IIIlI
=
0
;
BFMA1Oll1
=
0
;
BFMA1OIllI
=
0
;
end
else
if
(
PRESETN
==
1
'b
0
)
begin
BFMA1l1IlI
=
0
;
BFMA1OOllI
=
256
;
BFMA1OIllI
=
0
;
BFMA1IIllI
=
0
;
BFMA1IIIlI
=
0
;
BFMA1lIIlI
=
1
'b
0
;
BFMA1I1O0I
<=
1
'b
0
;
BFMA1l1O0I
<=
1
'b
0
;
BFMA1lI1II
<=
{
DWIDTH
{
1
'b
z
}
}
;
BFMA1OO0lI
=
69
;
BFMA1IO0lI
=
0
;
BFMA1OOI0I
=
0
;
end
else
begin
BFMA1lIIlI
=
1
'b
0
;
BFMA1l1O0I
<=
1
'b
0
;
if
(
PSEL
==
1
'b
1
)
begin
BFMA1OOIlI
=
{
PADDR
[
AWIDTH
-
1
:
2
]
,
2
'b
00
}
;
if
(
PSEL
==
1
'b
1
&
PENABLE
==
1
'b
0
)
begin
if
(
BFMA1IIIlI
>=
256
)
begin
BFMA1OO0lI
=
BFMA1lIl0
(
BFMA1OO0lI
)
;
BFMA1lOI0I
=
BFMA1O1l0
(
BFMA1OO0lI
,
BFMA1IIIlI
%
256
)
;
end
else
begin
BFMA1lOI0I
=
BFMA1IIIlI
;
end
BFMA1IOI0I
=
BFMA1lOI0I
-
1
;
if
(
BFMA1lOI0I
==
0
)
begin
BFMA1lIIlI
=
1
'b
1
;
BFMA1IOI0I
=
0
;
end
end
if
(
PSEL
==
1
'b
1
&
PENABLE
==
1
'b
1
&
BFMA1IIIlI
>
0
)
begin
if
(
BFMA1IOI0I
>
0
)
begin
BFMA1IOI0I
=
BFMA1IOI0I
-
1
;
end
else
if
(
BFMA1I1O0I
==
1
'b
0
)
begin
BFMA1lIIlI
=
1
'b
1
;
if
(
BFMA1IIIlI
>=
256
)
begin
BFMA1OO0lI
=
BFMA1lIl0
(
BFMA1OO0lI
)
;
BFMA1IOI0I
=
BFMA1O1l0
(
BFMA1OO0lI
,
BFMA1IIIlI
%
256
)
;
end
else
begin
BFMA1IOI0I
=
BFMA1IIIlI
;
end
end
else
begin
BFMA1lIIlI
=
1
'b
0
;
end
end
if
(
PSEL
==
1
'b
1
&
BFMA1lIIlI
==
1
'b
1
)
begin
if
(
BFMA1OIllI
)
begin
if
(
BFMA1IIllI
>
1
)
begin
BFMA1IIllI
=
BFMA1IIllI
-
1
;
end
else
begin
BFMA1OIllI
=
0
;
BFMA1l1O0I
<=
1
'b
1
;
end
end
end
if
(
PENABLE
==
1
'b
1
&
PWRITE
==
1
'b
1
&
BFMA1I1O0I
==
1
'b
1
)
begin
if
(
~
(
ENFUNC
>
0
&
BFMA1OOIlI
>=
ENFUNC
&
BFMA1OOIlI
<
ENFUNC
+
256
)
)
begin
BFMA1l1OlI
[
BFMA1OOIlI
+
0
]
=
BFMA1l0III
[
7
:
0
]
;
BFMA1l1OlI
[
BFMA1OOIlI
+
1
]
=
BFMA1l0III
[
15
:
8
]
;
BFMA1l1OlI
[
BFMA1OOIlI
+
2
]
=
BFMA1l0III
[
23
:
16
]
;
BFMA1l1OlI
[
BFMA1OOIlI
+
3
]
=
BFMA1l0III
[
31
:
24
]
;
if
(
BFMA1Ol1II
>=
1
)
$display
(
"APBS: Slot %0d Write %04x=%04x "
,
ID
,
BFMA1OOIlI
,
PWDATA
)
;
BFMA1IlllI
=
BFMA1OOIlI
;
BFMA1llllI
=
BFMA1O01l
(
PWDATA
)
;
end
else
begin
if
(
ENFUNC
>
0
&
BFMA1OOIlI
>=
ENFUNC
&
BFMA1OOIlI
<
ENFUNC
+
256
)
begin
$display
(
"APBS:%0d Setting ENFUNC %0d %0d"
,
ID
,
BFMA1OOIlI
-
ENFUNC
,
PWDATA
)
;
case
(
BFMA1OOIlI
-
ENFUNC
)
0
:
begin
BFMA1OIllI
=
1
;
BFMA1IIllI
=
BFMA1O01l
(
PWDATA
[
7
:
0
]
)
;
$display
(
"APBS: PSLVERR will be set on the %0d access"
,
BFMA1IIllI
)
;
end
4
:
begin
BFMA1IIIlI
=
BFMA1O01l
(
PWDATA
[
9
:
0
]
)
;
if
(
BFMA1IIIlI
>=
256
)
begin
$display
(
"APBS:PREADY timing random 0 to %0d cycles"
,
(
BFMA1IIIlI
%
256
)
)
;
end
else
begin
$display
(
"APBS:PREADY timing %0d cycles "
,
BFMA1IIIlI
)
;
end
end
8
:
begin
BFMA1Ol1II
<=
BFMA1O01l
(
PWDATA
[
7
:
0
]
)
;
end
12
:
begin
begin
:
BFMA1OII0I
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
DEPTH
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1l1OlI
[
BFMA1I0I0
]
=
0
;
end
end
end
16
:
begin
begin
:
BFMA1III0I
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
DEPTH
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1l1OlI
[
BFMA1I0I0
]
=
~
BFMA1I0I0
;
end
end
end
28
:
begin
BFMA1IOllI
=
BFMA1l0III
;
BFMA1l1IlI
=
BFMA1OOllI
;
end
32
:
begin
BFMA1OOllI
=
BFMA1O01l
(
PWDATA
)
;
end
36
:
begin
BFMA1Oll1
=
0
;
end
40
:
begin
$swrite
(
BFMA1I011
,
"image%0d.txt"
,
ID
)
;
$display
(
"APBS:%0d: Dumping to %0s"
,
ID
,
BFMA1I011
)
;
BFMA1l0OlI
=
$fopen
(
BFMA1I011
,
"w"
)
;
begin
:
BFMA1l01OI
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
DEPTH
-
1
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
$fdisplay
(
BFMA1l0OlI
,
"%08b"
,
BFMA1l1OlI
[
BFMA1I0I0
]
)
;
end
$fflush
(
BFMA1l0OlI
)
;
$fclose
(
BFMA1l0OlI
)
;
end
52
:
begin
BFMA1IO0lI
=
(
PWDATA
[
0
]
==
1
'b
1
)
;
$display
(
"APBS: Special Mode Enables set to %d"
,
PWDATA
[
2
:
0
]
)
;
if
(
BFMA1IO0lI
==
1
'b
1
)
BFMA1OOI0I
=
{
32
{
1
'b
X
}
}
;
else
BFMA1OOI0I
=
{
32
{
1
'b
0
}
}
;
end
default
:
begin
end
endcase
end
end
end
if
(
PSEL
==
1
'b
1
&
PWRITE
==
1
'b
0
&
BFMA1lIIlI
==
1
'b
1
)
begin
BFMA1IOIlI
=
{
BFMA1l1OlI
[
BFMA1OOIlI
+
3
]
,
BFMA1l1OlI
[
BFMA1OOIlI
+
2
]
,
BFMA1l1OlI
[
BFMA1OOIlI
+
1
]
,
BFMA1l1OlI
[
BFMA1OOIlI
+
0
]
}
;
if
(
~
(
ENFUNC
>
0
&
BFMA1OOIlI
>=
ENFUNC
&
BFMA1OOIlI
<
ENFUNC
+
256
)
)
begin
BFMA1IlllI
=
BFMA1OOIlI
;
BFMA1llllI
=
BFMA1O01l
(
BFMA1IOIlI
)
;
end
else
begin
case
(
BFMA1OOIlI
-
ENFUNC
)
44
:
begin
BFMA1IOIlI
=
to_slv32
(
BFMA1IlllI
)
;
end
48
:
begin
BFMA1IOIlI
=
to_slv32
(
BFMA1llllI
)
;
end
default
:
begin
end
endcase
end
BFMA1O1O0I
<=
BFMA1IOIlI
;
end
if
(
PSEL
==
1
'b
1
&
PWRITE
==
1
'b
0
&
PENABLE
==
1
'b
1
&
BFMA1I1O0I
==
1
'b
1
)
begin
if
(
BFMA1Ol1II
>=
1
)
$display
(
"APBS: Slot %0d Read %04x=%04x "
,
ID
,
BFMA1OOIlI
,
BFMA1IOIlI
)
;
end
end
BFMA1I1O0I
<=
BFMA1lIIlI
;
if
(
BFMA1l1IlI
>
1
)
begin
BFMA1l1IlI
=
BFMA1l1IlI
-
1
;
end
else
if
(
BFMA1l1IlI
==
1
)
begin
BFMA1l1OlI
[
ENFUNC
+
28
+
0
]
=
BFMA1IOllI
[
7
:
0
]
;
BFMA1l1OlI
[
ENFUNC
+
28
+
1
]
=
BFMA1IOllI
[
15
:
8
]
;
BFMA1l1OlI
[
ENFUNC
+
28
+
2
]
=
BFMA1IOllI
[
23
:
16
]
;
BFMA1l1OlI
[
ENFUNC
+
28
+
3
]
=
BFMA1IOllI
[
31
:
24
]
;
BFMA1l1IlI
=
0
;
end
BFMA1lI1II
<=
{
DWIDTH
{
1
'b
z
}
}
;
if
(
EXT_EN
==
1
'b
1
&
EXT_RD
==
1
'b
1
)
begin
case
(
EXT_SIZE
)
0
:
begin
BFMA1OOIlI
=
EXT_ADDR
[
AWIDTH
-
1
:
0
]
;
BFMA1IOIlI
=
{
BFMA1IlI0
[
31
:
8
]
,
BFMA1l1OlI
[
BFMA1OOIlI
+
0
]
}
;
end
1
:
begin
BFMA1OOIlI
=
{
EXT_ADDR
[
AWIDTH
-
1
:
1
]
,
1
'b
0
}
;
BFMA1IOIlI
=
{
BFMA1IlI0
[
31
:
16
]
,
BFMA1l1OlI
[
BFMA1OOIlI
+
1
]
,
BFMA1l1OlI
[
BFMA1OOIlI
+
0
]
}
;
end
2
:
begin
BFMA1OOIlI
=
{
EXT_ADDR
[
AWIDTH
-
1
:
2
]
,
2
'b
00
}
;
BFMA1IOIlI
=
{
BFMA1l1OlI
[
BFMA1OOIlI
+
3
]
,
BFMA1l1OlI
[
BFMA1OOIlI
+
2
]
,
BFMA1l1OlI
[
BFMA1OOIlI
+
1
]
,
BFMA1l1OlI
[
BFMA1OOIlI
+
0
]
}
;
end
endcase
if
(
BFMA1Ol1II
>=
1
)
$display
(
"APBS:%0d Extension Read %04x=%04x "
,
ID
,
BFMA1OOIlI
,
BFMA1IOIlI
)
;
BFMA1lI1II
<=
BFMA1IOIlI
;
end
if
(
EXT_EN
==
1
'b
1
&
EXT_WR
==
1
'b
1
)
begin
case
(
EXT_SIZE
)
0
:
begin
BFMA1OOIlI
=
EXT_ADDR
[
AWIDTH
-
1
:
0
]
;
BFMA1l1OlI
[
BFMA1OOIlI
+
0
]
=
EXT_DATA
[
7
:
0
]
;
end
1
:
begin
BFMA1OOIlI
=
{
EXT_ADDR
[
AWIDTH
-
1
:
1
]
,
1
'b
0
}
;
BFMA1l1OlI
[
BFMA1OOIlI
+
0
]
=
EXT_DATA
[
7
:
0
]
;
BFMA1l1OlI
[
BFMA1OOIlI
+
1
]
=
EXT_DATA
[
15
:
8
]
;
end
2
:
begin
BFMA1OOIlI
=
{
EXT_ADDR
[
AWIDTH
-
1
:
2
]
,
2
'b
00
}
;
BFMA1l1OlI
[
BFMA1OOIlI
+
0
]
=
EXT_DATA
[
7
:
0
]
;
BFMA1l1OlI
[
BFMA1OOIlI
+
1
]
=
EXT_DATA
[
15
:
8
]
;
BFMA1l1OlI
[
BFMA1OOIlI
+
2
]
=
EXT_DATA
[
23
:
16
]
;
BFMA1l1OlI
[
BFMA1OOIlI
+
3
]
=
EXT_DATA
[
31
:
24
]
;
end
endcase
if
(
BFMA1Ol1II
>=
1
)
$display
(
"APBS:%0d Extension Write %04x=%04x "
,
ID
,
BFMA1OOIlI
,
EXT_DATA
)
;
end
end
end
assign
#
TPD
PRDATA
=
(
PENABLE
==
1
'b
1
)
?
BFMA1O1O0I
[
DWIDTH
-
1
:
0
]
:
BFMA1OOI0I
[
DWIDTH
-
1
:
0
]
;
assign
#
TPD
PREADY
=
BFMA1I1O0I
;
assign
#
TPD
PSLVERR
=
BFMA1l1O0I
;
wire
[
DWIDTH
-
1
:
0
]
EXT_DATA
=
BFMA1lI1II
;
always
@
(
PWDATA
)
begin
BFMA1l0III
<=
{
32
{
1
'b
0
}
}
;
BFMA1l0III
[
DWIDTH
-
1
:
0
]
<=
PWDATA
;
end
assign
BFMA1O11lI
=
PENABLE
;
assign
BFMA1OOO0I
=
PWRITE
;
assign
BFMA1OIO0I
=
PSEL
;
assign
BFMA1OlO0I
=
BFMA1l0I0
(
PADDR
)
;
assign
BFMA1O0O0I
=
BFMA1l0I0
(
PWDATA
)
;
always
@
(
posedge
PCLK
)
begin
:
BFMA1lII0I
reg
BFMA1l01lI
;
BFMA1I11lI
<=
BFMA1O11lI
;
BFMA1l11lI
<=
BFMA1I11lI
;
BFMA1IOO0I
<=
BFMA1OOO0I
;
BFMA1lOO0I
<=
BFMA1IOO0I
;
BFMA1IIO0I
<=
BFMA1OIO0I
;
BFMA1lIO0I
<=
BFMA1IIO0I
;
BFMA1IlO0I
<=
BFMA1OlO0I
;
BFMA1llO0I
<=
BFMA1IlO0I
;
BFMA1I0O0I
<=
BFMA1O0O0I
;
BFMA1l0O0I
<=
BFMA1I0O0I
;
BFMA1l01lI
=
0
;
if
(
BFMA1O11lI
==
1
'b
1
&
BFMA1OIO0I
==
1
'b
1
)
begin
if
(
BFMA1OlO0I
!=
BFMA1IlO0I
)
begin
$display
(
"APBS:%0d Address not stable in both cycles"
,
ID
)
;
BFMA1l01lI
=
1
;
end
if
(
BFMA1OOO0I
!=
BFMA1IOO0I
)
begin
$display
(
"APBS:%0d PWRITE not stable in both cycles"
,
ID
)
;
BFMA1l01lI
=
1
;
end
if
(
BFMA1OIO0I
!=
BFMA1IIO0I
)
begin
$display
(
"APBS:%0d PSEL not stable in both cycles"
,
ID
)
;
BFMA1l01lI
=
1
;
end
if
(
BFMA1O0O0I
!=
BFMA1I0O0I
&
BFMA1OOO0I
==
1
'b
1
)
begin
$display
(
"APBS:%0d PWDATA not stable in both cycles"
,
ID
)
;
BFMA1l01lI
=
1
;
end
if
(
BFMA1IIO0I
!=
1
'b
1
)
begin
$display
(
"APBS:%0d PSEL was not active in cycle before PENABLE"
,
ID
)
;
BFMA1l01lI
=
1
;
end
end
if
(
BFMA1l01lI
)
begin
$display
(
"APB Protocol violation (ERROR)"
)
;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ifu_ctr5.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ifu_ctr5
// Description:
// 5 bit counter for starvation detect
*/
module sparc_ifu_ctr5(/*AUTOARG*/
// Outputs
limit, so,
// Inputs
clk, se, si, rst_ctr_l
);
input clk;
input se, si;
input rst_ctr_l;
output limit;
output so;
wire [4:0] count,
count_nxt,
sum;
assign sum[0] = ~count[0];
assign sum[1] = count[1] ^ count[0];
assign sum[2] = count[2] ^ (count[1] & count[0]);
assign sum[3] = count[3] ^ (count[2] & count[1] & count[0]);
assign sum[4] = count[4] ^ (count[3] & count[2] & count[1] & count[0]);
assign count_nxt = sum & {5{rst_ctr_l}};
dff_s #(5) cnt_reg(.din (count_nxt),
.q (count),
.clk (clk),
.se (se), .si(), .so());
// limit set to 24 for now
assign limit = count[4] & count[3];
endmodule
|
module synth_arb (
clk,
reset_n,
memadrs,
memdata,
wreq,
synth_ctrl,
synth_data,
fifo_full);
input wire clk, reset_n, wreq, fifo_full;
input wire [7:0] memadrs, memdata;
output reg [7:0] synth_ctrl, synth_data;
reg [7:0] state_reg;
reg [3:0] wait_cnt;
reg wreq_inter, w_done;
always @(posedge wreq, posedge w_done, negedge reset_n)
begin
if(reset_n == 0) wreq_inter <= 0;
else if(w_done == 1) wreq_inter <= 0;
else if(wreq == 1 && w_done != 1) wreq_inter <= 1;
end
always @(posedge clk, negedge reset_n)
begin
if(!reset_n)
begin
state_reg <= 0;
synth_ctrl <= 0;
synth_data <= 0;
wait_cnt <= 0;
w_done <= 0;
end
else
begin
case(state_reg)
8'D0 : state_reg <= state_reg + 1;
//recovery reset while 16count
8'D1 : begin
if(wait_cnt != 4'b1111) wait_cnt <= wait_cnt + 1;
else state_reg <= state_reg + 1;
end
//step phase, operator 1
8'D2 : begin
state_reg <= state_reg + 1;
synth_ctrl <= 8'b00000001;
end
//fifo full check, operator stall
8'D3 : begin
synth_ctrl <= 8'b00000000;
if(fifo_full != 1) state_reg <= state_reg + 1;
else state_reg <= state_reg;
end
//write req to fifo, operator 1
8'D4 : begin
state_reg <= state_reg + 1;
synth_ctrl <= 8'b10000001;
end
//write wait
8'D5 : begin
state_reg <= state_reg + 1;
synth_ctrl <= 8'b00000000;
end
//jump to state 2 if write strobe is not active
8'D6 : begin
if(wreq_inter == 1) state_reg <= state_reg + 1;
else state_reg <= 2;
end
//get recieve data and command, write data
8'D7 : begin
synth_data <= memdata;
synth_ctrl <= d2ctrl_synth(memadrs);
state_reg <= state_reg + 1;
w_done <= 1;
end
//finishing write data
8'D8 : begin
state_reg <= 2;
synth_ctrl <= 8'b00000000;
w_done <= 0;
end
default : state_reg <= 0;
endcase
end
end
function [7:0] d2ctrl_synth;
input [7:0] adrs;
begin
casex(adrs)
8'b00000001 : d2ctrl_synth = 8'b01000001;
8'b00010001 : d2ctrl_synth = 8'b00010001;
8'b00100001 : d2ctrl_synth = 8'b01010001;
8'b1000xxxx : d2ctrl_synth = 8'b00100000;
default : d2ctrl_synth = 0;
endcase
end
endfunction
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_cpx_rptr_3.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_cpx_rptr_3 (/*AUTOARG*/
// Outputs
sig_buf,
// Inputs
sig
);
// this repeater has 164 bits
output [163:0] sig_buf;
input [163:0] sig;
assign sig_buf = sig;
//output [7:0] sctag_cpx_req_cq_buf; // sctag to processor request
//output sctag_cpx_atom_cq_buf;
//output [`CPX_WIDTH-1:0] sctag_cpx_data_ca_buf; // sctag to cpx data pkt
//output [7:0] cpx_sctag_grant_cx_buf;
//input [7:0] sctag_cpx_req_cq; // sctag to processor request
//input sctag_cpx_atom_cq;
//input [`CPX_WIDTH-1:0] sctag_cpx_data_ca; // sctag to cpx data pkt
//input [7:0] cpx_sctag_grant_cx;
//assign sctag_cpx_atom_cq_buf = sctag_cpx_atom_cq;
//assign sctag_cpx_data_ca_buf = sctag_cpx_data_ca;
//assign cpx_sctag_grant_cx_buf = cpx_sctag_grant_cx;
//assign sctag_cpx_req_cq_buf = sctag_cpx_req_cq;
endmodule
|
`default_nettype none
module displayIK_7seg_16
(
input wire CLK,
input wire RSTN,
input wire [15:0] data0,
input wire [15:0] data1,
input wire [15:0] data2,
input wire [15:0] data3,
input wire [15:0] data4,
input wire [15:0] data5,
input wire [15:0] data6,
input wire [15:0] data7,
input wire [15:0] data8,
input wire [15:0] data9,
input wire [15:0] data10,
input wire [15:0] data11,
input wire [15:0] data12,
input wire [15:0] data13,
input wire [15:0] data14,
input wire [15:0] data15,
output wire [7:0] SEG_A,
output wire [7:0] SEG_B,
output wire [7:0] SEG_C,
output wire [7:0] SEG_D,
output wire [7:0] SEG_E,
output wire [7:0] SEG_F,
output wire [7:0] SEG_G,
output wire [7:0] SEG_H,
output wire [8:0] SEG_SEL
);
wire [31:0] SEG_0,SEG_1,SEG_2,SEG_3,SEG_4,SEG_5,SEG_6,SEG_7;
wire [31:0] SEG_8,SEG_9,SEG_10,SEG_11,SEG_12,SEG_13,SEG_14,SEG_15;
display_module_async_16b
i0
(
.data (data0),
.SEG_32 (SEG_0)
);
display_module_async_16b
i1
(
.data (data1),
.SEG_32 (SEG_1)
);
display_module_async_16b
i2
(
.data (data2),
.SEG_32 (SEG_2)
);
display_module_async_16b
i3
(
.data (data3),
.SEG_32 (SEG_3)
);
display_module_async_16b
i4
(
.data (data4),
.SEG_32 (SEG_4)
);
display_module_async_16b
i5
(
.data (data5),
.SEG_32 (SEG_5)
);
display_module_async_16b
i6
(
.data (data6),
.SEG_32 (SEG_6)
);
display_module_async_16b
i7
(
.data (data7),
.SEG_32 (SEG_7)
);
display_module_async_16b
i8
(
.data (data8),
.SEG_32 (SEG_8)
);
display_module_async_16b
i9
(
.data (data9),
.SEG_32 (SEG_9)
);
display_module_async_16b
i10
(
.data (data10),
.SEG_32 (SEG_10)
);
display_module_async_16b
i11
(
.data (data11),
.SEG_32 (SEG_11)
);
display_module_async_16b
i12
(
.data (data12),
.SEG_32 (SEG_12)
);
display_module_async_16b
i13
(
.data (data13),
.SEG_32 (SEG_13)
);
display_module_async_16b
i14
(
.data (data14),
.SEG_32 (SEG_14)
);
display_module_async_16b
i15
(
.data (data15),
.SEG_32 (SEG_15)
);
dynamic_displayIK_16
i16
(
.CLK (CLK),
.RST (RSTN),
.SEG_0 (SEG_0),
.SEG_1 (SEG_1),
.SEG_2 (SEG_2),
.SEG_3 (SEG_3),
.SEG_4 (SEG_4),
.SEG_5 (SEG_5),
.SEG_6 (SEG_6),
.SEG_7 (SEG_7),
.SEG_8 (SEG_8),
.SEG_9 (SEG_9),
.SEG_10 (SEG_10),
.SEG_11 (SEG_11),
.SEG_12 (SEG_12),
.SEG_13 (SEG_13),
.SEG_14 (SEG_14),
.SEG_15 (SEG_15),
.SEG_A (SEG_A),
.SEG_B (SEG_B),
.SEG_C (SEG_C),
.SEG_D (SEG_D),
.SEG_E (SEG_E),
.SEG_F (SEG_F),
.SEG_G (SEG_G),
.SEG_H (SEG_H),
.SEG_SEL (SEG_SEL)
);
endmodule
module dynamic_displayIK_16
(
input wire CLK,
input wire RST,
input wire [31:0] SEG_0,
input wire [31:0] SEG_1,
input wire [31:0] SEG_2,
input wire [31:0] SEG_3,
input wire [31:0] SEG_4,
input wire [31:0] SEG_5,
input wire [31:0] SEG_6,
input wire [31:0] SEG_7,
input wire [31:0] SEG_8,
input wire [31:0] SEG_9,
input wire [31:0] SEG_10,
input wire [31:0] SEG_11,
input wire [31:0] SEG_12,
input wire [31:0] SEG_13,
input wire [31:0] SEG_14,
input wire [31:0] SEG_15,
output reg [7:0] SEG_A,
output reg [7:0] SEG_B,
output reg [7:0] SEG_C,
output reg [7:0] SEG_D,
output reg [7:0] SEG_E,
output reg [7:0] SEG_F,
output reg [7:0] SEG_G,
output reg [7:0] SEG_H,
output reg [8:0] SEG_SEL
);
localparam DEF_MAX = 16'h7FFF;
localparam COUNT_MAX = 3'b111;
reg [2:0] COUNTER;
reg [15:0] DEF_COUNTER;
always @(posedge CLK or negedge RST) begin
if(!RST) begin
SEG_A <= 8'hFC;
SEG_B <= 8'hFC;
SEG_C <= 8'hFC;
SEG_D <= 8'hFC;
SEG_E <= 8'hFC;
SEG_F <= 8'hFC;
SEG_G <= 8'hFC;
SEG_H <= 8'hFC;
SEG_SEL <=9'h1FF;
COUNTER <= 3'h0;
DEF_COUNTER <= 16'h0000;
end else begin
if(DEF_COUNTER != DEF_MAX) begin
DEF_COUNTER <= DEF_COUNTER + 16'd1;
SEG_SEL <=9'h000;
end
else begin
DEF_COUNTER <= 16'h0000;
case(COUNTER)
3'd0: begin
SEG_A <= SEG_0[31:24];
SEG_B <= SEG_0[23:16];
SEG_C <= SEG_0[15:8];
SEG_D <= SEG_0[7:0];
SEG_E <= SEG_1[31:24];
SEG_F <= SEG_1[23:16];
SEG_G <= SEG_1[15:8];
SEG_H <= SEG_1[7:0];
SEG_SEL <= 9'b0_0000_0001;
end
3'd1: begin
SEG_A <= SEG_2[31:24];
SEG_B <= SEG_2[23:16];
SEG_C <= SEG_2[15:8];
SEG_D <= SEG_2[7:0];
SEG_E <= SEG_3[31:24];
SEG_F <= SEG_3[23:16];
SEG_G <= SEG_3[15:8];
SEG_H <= SEG_3[7:0];
SEG_SEL <= 9'b0_0000_0010;
end
3'd2: begin
SEG_A <= SEG_4[31:24];
SEG_B <= SEG_4[23:16];
SEG_C <= SEG_4[15:8];
SEG_D <= SEG_4[7:0];
SEG_E <= SEG_5[31:24];
SEG_F <= SEG_5[23:16];
SEG_G <= SEG_5[15:8];
SEG_H <= SEG_5[7:0];
SEG_SEL <= 9'b0_0000_0100;
end
3'd3: begin
SEG_A <= SEG_6[31:24];
SEG_B <= SEG_6[23:16];
SEG_C <= SEG_6[15:8];
SEG_D <= SEG_6[7:0];
SEG_E <= SEG_7[31:24];
SEG_F <= SEG_7[23:16];
SEG_G <= SEG_7[15:8];
SEG_H <= SEG_7[7:0];
SEG_SEL <= 9'b0_0000_1000;
end
3'd4: begin
SEG_A <= SEG_8[31:24];
SEG_B <= SEG_8[23:16];
SEG_C <= SEG_8[15:8];
SEG_D <= SEG_8[7:0];
SEG_E <= SEG_9[31:24];
SEG_F <= SEG_9[23:16];
SEG_G <= SEG_9[15:8];
SEG_H <= SEG_9[7:0];
SEG_SEL <= 9'b0_0001_0000;
end
3'd5: begin
SEG_A <= SEG_10[31:24];
SEG_B <= SEG_10[23:16];
SEG_C <= SEG_10[15:8];
SEG_D <= SEG_10[7:0];
SEG_E <= SEG_11[31:24];
SEG_F <= SEG_11[23:16];
SEG_G <= SEG_11[15:8];
SEG_H <= SEG_11[7:0];
SEG_SEL <= 9'b0_0010_0000;
end
3'd6: begin
SEG_A <= SEG_12[31:24];
SEG_B <= SEG_12[23:16];
SEG_C <= SEG_12[15:8];
SEG_D <= SEG_12[7:0];
SEG_E <= SEG_13[31:24];
SEG_F <= SEG_13[23:16];
SEG_G <= SEG_13[15:8];
SEG_H <= SEG_13[7:0];
SEG_SEL <= 9'b0_0100_0000;
end
3'd7: begin
SEG_A <= SEG_14[31:24];
SEG_B <= SEG_14[23:16];
SEG_C <= SEG_14[15:8];
SEG_D <= SEG_14[7:0];
SEG_E <= SEG_15[31:24];
SEG_F <= SEG_15[23:16];
SEG_G <= SEG_15[15:8];
SEG_H <= SEG_15[7:0];
SEG_SEL <= 9'b0_1000_0000;
end
endcase
if(COUNTER == COUNT_MAX) begin
COUNTER <= 3'd0;
end else begin
COUNTER <= COUNTER + 3'd1;
end
end
end
end
endmodule
module display_module_async_16b
(
input wire [15:0] data,
output wire [31:0] SEG_32
);
display_module_async
i0
(
.SEG_VAL (data[3:0]),
.SEG (SEG_32[7:0])
);
display_module_async
i1
(
.SEG_VAL (data[7:4]),
.SEG (SEG_32[15:8])
);
display_module_async
i2
(
.SEG_VAL (data[11:8]),
.SEG (SEG_32[23:16])
);
display_module_async
i3
(
.SEG_VAL (data[15:12]),
.SEG (SEG_32[31:24])
);
endmodule
module display_module_async
(
input wire [3:0] SEG_VAL,
output reg [7:0] SEG
);
always @ (*) begin
case (SEG_VAL)
4'h0: SEG <= 8'b11111100;
4'h1: SEG <= 8'b01100000;
4'h2: SEG <= 8'b11011010;
4'h3: SEG <= 8'b11110010;
4'h4: SEG <= 8'b01100110;
4'h5: SEG <= 8'b10110110;
4'h6: SEG <= 8'b10111110;
4'h7: SEG <= 8'b11100000;
4'h8: SEG <= 8'b11111110;
4'h9: SEG <= 8'b11110110;
4'ha: SEG <= 8'b11101110;
4'hb: SEG <= 8'b00111110;
4'hc: SEG <= 8'b00011010;
4'hd: SEG <= 8'b01111010;
4'he: SEG <= 8'b10011110;
4'hf: SEG <= 8'b10001110;
endcase
end
endmodule
`default_nettype wire
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:40:01 08/24/2014
// Design Name:
// Module Name: ps2_kbd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ps2_kbd (
clk,
clrn,
ps2_clk,
ps2_data,
rdn,
data,
ready,
overflow
);
input clk, clrn; // clock and reset (active low)
input ps2_clk, ps2_data; // ps2 signals from keyboard
input rdn; // read (active low) signal from cpu
output [ 7: 0] data; // keyboard code
output ready; // queue (fifo) state
output reg overflow; // queue (fifo) overflow
reg [ 3: 0] count; // count ps2_data bits
reg [ 9: 0] buffer; // ps2_data bits
reg [ 7: 0] fifoo[7:0]; // data queue (fifo)
reg [ 2: 0] w_ptr, r_ptr; // fifo write and read pointers
reg [ 2: 0] ps2_clk_sync; // for detecting the falling-edge of a frame
integer i;
initial begin
count <= 0; // clear count
w_ptr <= 0; // clear w_ptr
r_ptr <= 0; // clear r_ptr
overflow <= 0; // clear overflow
for(i = 0; i < 8; i = i + 1) fifoo[i]=0;
end
always @ (posedge clk) begin // this is a common method to
ps2_clk_sync <= {ps2_clk_sync[1:0],ps2_clk}; // detect
end // falling-edge
wire sampling = ps2_clk_sync[2] & ~ps2_clk_sync[1]; // (start bit)
reg [1:0] rdn_falling;
always @ (posedge clk) begin
rdn_falling <= {rdn_falling[0],rdn};
if (clrn == 0) begin
count <= 0;
w_ptr <= 0;
r_ptr <= 0;
overflow <= 0;
end else if (sampling) begin
if (count == 4'd10) begin // for one frame
if ((buffer[0] == 0) && (ps2_data) && (^buffer[9:1])) begin // odd prity
fifoo[w_ptr] <= buffer[8:1]; // write fifo
w_ptr <= w_ptr + 3'b1; // w_ptr++
overflow <= overflow | (r_ptr == (w_ptr + 3'b1));
end
count <= 0; // for next
end else begin // within one frame
buffer[count] <= ps2_data; // store ps2_data
count <= count + 3'b1; // count ps2_data bits
end
end
if ((rdn_falling == 2'b01) && ready) begin // when cpu reads fifo
r_ptr <= r_ptr + 3'b1; // r_ptr++
overflow <= 0; // clear overflow
end
end
assign ready = (w_ptr != r_ptr); // fifo has data
assign data = fifoo[r_ptr]; // fifo data
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211A_LP_V
`define SKY130_FD_SC_LP__O211A_LP_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211a_lp (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o211a_lp (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211A_LP_V
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "regs.v"
`include "alu.v"
`include "mem.v"
module cpu(
input clk,
output uart_tx_wire);
localparam WIDTH = 32;
localparam INSTR_WIDTH = WIDTH;
localparam REG_COUNT = 32;
localparam ADDRESS_WIDTH = 14;
localparam IO_SPACE_WIDTH = 2; //MSB bits for memory mapped IO
localparam STACK_REG_IDX = 2;
localparam PC_INC = $clog2(INSTR_WIDTH) - 1;
localparam WORD_ALIGNMENT = $clog2(WIDTH / 8);
localparam STACK_START = ((1 << (ADDRESS_WIDTH - IO_SPACE_WIDTH - 1)) << WORD_ALIGNMENT) - PC_INC;
localparam REG_WIDTH = $clog2(REG_COUNT);
localparam OPCODE_START = 0;
localparam OPCODE_END = 6;
localparam RD_START = OPCODE_END + 1;
localparam RD_END = RD_START + REG_WIDTH - 1;
localparam FUNCT3_START = RD_START + REG_WIDTH;
localparam FUNCT3_WIDTH = 2;
localparam FUNCT3_END = FUNCT3_START + FUNCT3_WIDTH;
localparam RS1_START = FUNCT3_END + 1;
localparam RS1_END = RS1_START + REG_WIDTH - 1;
localparam RS2_START = RS1_START + REG_WIDTH;
localparam RS2_END = RS2_START + REG_WIDTH - 1;
localparam ITYPE_IMM_START = RS1_END + 1;
localparam ITYPE_IMM_END = INSTR_WIDTH - 1;
localparam STYPE_IMM1_START = RD_START;
localparam STYPE_IMM1_END = RD_END;
localparam STYPE_IMM2_START = RS2_START + REG_WIDTH;
localparam STYPE_IMM2_END = ITYPE_IMM_END;
localparam UTYPE_IMM_START = RD_END + 1;
localparam UTYPE_IMM_END = INSTR_WIDTH - 1;
localparam JTYPE_IMM12 = RD_END + 1;
localparam JTYPE_IMM19 = JTYPE_IMM12 + 7;
localparam JTYPE_IMM11 = JTYPE_IMM19 + 1;
localparam JTYPE_IMM1 = JTYPE_IMM11 + 1;
localparam JTYPE_IMM10 = JTYPE_IMM1 + 9;
localparam JTYPE_IMM20 = JTYPE_IMM10 + 1;
localparam BTYPE_IMM11 = RD_START;
localparam BTYPE_IMM1 = RD_START + 1;
localparam BTYPE_IMM4 = BTYPE_IMM1 + 3;
localparam BTYPE_IMM5 = RS2_END + 1;
localparam BTYPE_IMM10 = BTYPE_IMM5 + 5;
localparam BTYPE_IMM12 = BTYPE_IMM10 + 1;
//Load instructions
localparam LOAD_OPCODE = 7'b0000011;
localparam LB_FUNCT3 = 3'b000;
localparam LH_FUNCT3 = 3'b001;
localparam LW_FUNCT3 = 3'b010;
localparam LBU_FUNCT3 = 3'b100;
localparam LHU_FUNCT3 = 3'b101;
//Store instructions
localparam STORE_OPCODE = 7'b0100011;
localparam SB_FUNCT3 = 3'b000;
localparam SH_FUNCT3 = 3'b001;
localparam SW_FUNCT3 = 3'b010;
//Load immediate instructions
localparam LUI_OPCODE = 7'b0110111;
localparam AUIPC_OPCODE = 7'b0010111;
//Control tranfer instructions
localparam JAL_OPCODE = 7'b1101111;
localparam JALR_OPCODE = 7'b1100111;
//Branch instructions
localparam BRANCH_OPCODE = 7'b1100011;
localparam BEQ_FUNCT3 = 3'b000;
localparam BNE_FUNCT3 = 3'b001;
localparam BLT_FUNCT3 = 3'b100;
localparam BGE_FUNCT3 = 3'b101;
localparam BLTU_FUNCT3 = 3'b110;
localparam BGEU_FUNCT3 = 3'b111;
//Arithmetic instructions
localparam IARITH_OPCODE = 7'b0010011;
localparam ARITH_OPCODE = 7'b0110011;
localparam ADD_FUNCT3 = 3'b000;
localparam SLT_FUNCT3 = 3'b010;
localparam SLTU_FUNCT3 = 3'b011;
localparam XOR_FUNCT3 = 3'b100;
localparam OR_FUNCT3 = 3'b110;
localparam AND_FUNCT3 = 3'b111;
localparam SL_FUNCT3 = 3'b001;
localparam SR_FUNCT3 = 3'b101;
localparam SUB_BIT = 30;
localparam ARITH_SHIFT_BIT = 30;
//Fence instruction
localparam FENCE_OPCODE = 7'b0001111;
localparam STAGE_T0 = 0;
localparam STAGE_T1 = 1;
localparam STAGE_T2 = 2;
localparam STAGE_T3 = 3;
localparam STAGE_T4 = 4;
localparam STAGE_COUNT = STAGE_T4 + 1;
localparam STAGE_WIDTH = $clog2(STAGE_COUNT);
`ifdef IVERILOG
localparam rst_size = 3;
`else
localparam rst_size = 6;
`endif
localparam rst_max = (1 << rst_size) - 1;
reg [rst_size : 0] rst_cnt = 0;
reg rstn = 0;
reg [WIDTH-1 : 0] ir; //Instruction register.
reg [STAGE_WIDTH-1 : 0] stage_reg; //Keeps track of the current execution stage.
reg [WIDTH-1 : 0] pc_reg; //Program counter
wire [OPCODE_END : 0] opcode;
wire [FUNCT3_WIDTH : 0] funct3;
wire [REG_WIDTH-1 : 0] rd;
wire [REG_WIDTH-1 : 0] rs1;
wire [REG_WIDTH-1 : 0] rs2;
wire [WIDTH-1 : 0] itype_imm;
wire [WIDTH-1 : 0] stype_imm;
wire [WIDTH-1 : 0] utype_imm;
wire [WIDTH-1 : 0] jtype_imm;
wire [WIDTH-1 : 0] btype_imm;
reg regs_wr_enable;
reg [REG_WIDTH-1 : 0] regs_rs1_offset, regs_rs2_offset, regs_rd_offset;
reg [WIDTH-1 : 0] regs_rd_in;
wire [WIDTH-1 : 0] regs_rs1_out, regs_rs2_out;
registers #(
.WIDTH(WIDTH),
.REG_WIDTH(REG_WIDTH),
.STACK_REG(STACK_REG_IDX),
.STACK_START(STACK_START)) cpu_regs (
.rst(!rstn),
.clk(clk),
.write_enable(regs_wr_enable),
.rs1_offset(regs_rs1_offset),
.rs2_offset(regs_rs2_offset),
.rd_offset(regs_rd_offset),
.rd_data_in(regs_rd_in),
.rs1_data_out(regs_rs1_out),
.rs2_data_out(regs_rs2_out));
reg sub_enable, alu_arith_shift;
reg [2 : 0] alu_op;
reg [REG_WIDTH-1 : 0] alu_shamt;
reg [WIDTH-1 : 0] alu_a, alu_b;
wire [WIDTH-1 : 0] alu_res;
wire alu_eq, alu_bgeu, alu_bge;
alu #(
.WIDTH(WIDTH),
.ADD_OP(ADD_FUNCT3),
.SLT_OP(SLT_FUNCT3),
.SLTU_OP(SLTU_FUNCT3),
.XOR_OP(XOR_FUNCT3),
.OR_OP(OR_FUNCT3),
.AND_OP(ADD_FUNCT3),
.SL_OP(SL_FUNCT3),
.SR_OP(SR_FUNCT3)) cpu_alu(
.a(alu_a),
.b(alu_b),
.sub_enable(sub_enable),
.arith_shift(alu_arith_shift),
.op(alu_op),
.shamt(alu_shamt),
.res(alu_res),
.eq(alu_eq),
.bgeu(alu_bgeu),
.bge(alu_bge));
reg ram_wr_enable = 0;
reg [ADDRESS_WIDTH-1 : 0] ram_rd_addr, ram_wr_addr;
reg [WIDTH-1 : 0] ram_data_in;
wire [WIDTH-1 : 0] ram_data_out;
ram #(
.WIDTH(WIDTH),
.ADDRESS_WIDTH(ADDRESS_WIDTH),
.IO_SPACE_WIDTH(IO_SPACE_WIDTH),
.SB_FUNCT3(SB_FUNCT3),
.SW_FUNCT3(SW_FUNCT3),
.SH_FUNCT3(SH_FUNCT3)) cpu_ram(
.rst(!rstn),
.clk(clk),
.write_enable(ram_wr_enable),
.read_addr(ram_rd_addr),
.write_addr(ram_wr_addr),
.data_in(ram_data_in),
.store_funct3(funct3),
.data_out(ram_data_out),
.uart_tx_wire(uart_tx_wire));
always @(posedge clk) begin
if (rst_cnt != rst_max) begin
rst_cnt <= rst_cnt + 1;
end else begin
rstn <= 1;
end
end
assign opcode = ir[OPCODE_END : OPCODE_START];
assign funct3 = ir[FUNCT3_END : FUNCT3_START];
assign rd = ir[RD_END : RD_START];
assign rs1 = ir[RS1_END : RS1_START];
assign rs2 = ir[RS2_END : RS2_START];
assign itype_imm = {{20{ir[ITYPE_IMM_END]}}, ir[ITYPE_IMM_END : ITYPE_IMM_START]};
assign stype_imm = {{20{ir[STYPE_IMM2_END]}},
{ir[STYPE_IMM2_END : STYPE_IMM2_START], ir[STYPE_IMM1_END : STYPE_IMM1_START]}};
assign utype_imm = {ir[UTYPE_IMM_END : UTYPE_IMM_START], 12'b0};
assign jtype_imm = {{12{ir[JTYPE_IMM20]}}, {ir[JTYPE_IMM20],
ir[JTYPE_IMM19 : JTYPE_IMM12], ir[JTYPE_IMM11], ir[JTYPE_IMM10 : JTYPE_IMM1], 1'b0}};
assign btype_imm = {{20{ir[BTYPE_IMM12]}}, {ir[BTYPE_IMM12],
ir[BTYPE_IMM11], ir[BTYPE_IMM10 : BTYPE_IMM5], ir[BTYPE_IMM4 : BTYPE_IMM1], 1'b0}};
always @(posedge clk) begin
if (rstn) begin
case (stage_reg)
STAGE_T0: begin
ir <= ram_data_out;
alu_a <= pc_reg;
alu_b <= PC_INC;
sub_enable <= 0;
alu_op <= ADD_FUNCT3;
regs_wr_enable <= 0;
ram_wr_enable <= 0;
stage_reg <= STAGE_T1;
end
STAGE_T1: begin
case (opcode)
FENCE_OPCODE: begin
pc_reg <= alu_res;
ram_rd_addr <= alu_res;
stage_reg <= STAGE_T0;
end
ARITH_OPCODE: begin
regs_rs1_offset <= rs1;
regs_rs2_offset <= rs2;
pc_reg <= alu_res;
stage_reg <= STAGE_T2;
end
IARITH_OPCODE: begin
regs_rs1_offset <= rs1;
pc_reg <= alu_res;
stage_reg <= STAGE_T2;
end
BRANCH_OPCODE: begin
regs_rd_in <= alu_res;
alu_b <= btype_imm;
regs_rs1_offset <= rs1;
regs_rs2_offset <= rs2;
stage_reg <= STAGE_T2;
end
LOAD_OPCODE: begin
regs_rs1_offset <= rs1;
pc_reg <= alu_res;
stage_reg <= STAGE_T2;
end
STORE_OPCODE: begin
regs_rs1_offset <= rs1;
pc_reg <= alu_res;
stage_reg <= STAGE_T2;
end
LUI_OPCODE: begin
regs_wr_enable <= 1;
regs_rd_offset <= rd;
regs_rd_in <= utype_imm;
pc_reg <= alu_res;
ram_rd_addr <= alu_res;
stage_reg <= STAGE_T0;
end
AUIPC_OPCODE: begin
ram_rd_addr <= alu_res;
alu_b <= utype_imm;
stage_reg <= STAGE_T2;
end
JAL_OPCODE: begin
regs_wr_enable <= 1;
regs_rd_offset <= rd;
regs_rd_in <= alu_res;
alu_b <= jtype_imm;
stage_reg <= STAGE_T2;
end
JALR_OPCODE: begin
regs_wr_enable <= 1;
regs_rd_offset <= rd;
regs_rd_in <= alu_res;
regs_rs1_offset <= rs1;
stage_reg <= STAGE_T2;
end
default: begin
`ifdef IVERILOG
$display("Unsupported opcode: %d!\n", opcode);
`endif
end
endcase
end
STAGE_T2: begin
case (opcode)
ARITH_OPCODE: begin
alu_a <= regs_rs1_out;
alu_b <= regs_rs2_out;
alu_op <= funct3;
sub_enable <= ir[SUB_BIT];
alu_arith_shift <= ir[ARITH_SHIFT_BIT];
alu_shamt <= regs_rs2_out[REG_WIDTH-1 : 0];
stage_reg <= STAGE_T3;
end
IARITH_OPCODE: begin
alu_a <= regs_rs1_out;
alu_b <= itype_imm;
alu_op <= funct3;
alu_arith_shift <= ir[ARITH_SHIFT_BIT];
alu_shamt <= rs2;
stage_reg <= STAGE_T3;
end
BRANCH_OPCODE: begin
ram_data_in <= alu_res;
alu_a <= regs_rs1_out;
alu_b <= regs_rs2_out;
stage_reg <= STAGE_T3;
end
LOAD_OPCODE: begin
alu_a <= regs_rs1_out;
alu_b <= itype_imm;
sub_enable <= 0;
stage_reg <= STAGE_T3;
end
STORE_OPCODE: begin
alu_a <= regs_rs1_out;
alu_b <= stype_imm;
sub_enable <= 0;
stage_reg <= STAGE_T3;
end
AUIPC_OPCODE: begin
pc_reg <= ram_rd_addr;
regs_wr_enable <= 1;
regs_rd_offset = rd;
regs_rd_in <= alu_res;
stage_reg <= STAGE_T0;
end
JAL_OPCODE: begin
pc_reg <= alu_res;
ram_rd_addr <= alu_res;
regs_wr_enable <= 0;
stage_reg <= STAGE_T0;
end
JALR_OPCODE: begin
regs_wr_enable <= 0;
alu_a <= regs_rs1_out;
alu_b <= itype_imm;
stage_reg <= STAGE_T3;
end
default: begin
end
endcase
end
STAGE_T3: begin
case (opcode)
ARITH_OPCODE: begin
regs_wr_enable <= 1;
regs_rd_in <= alu_res;
regs_rd_offset <= rd;
ram_rd_addr <= pc_reg;
stage_reg <= STAGE_T0;
end
IARITH_OPCODE: begin
regs_wr_enable <= 1;
regs_rd_in <= alu_res;
regs_rd_offset <= rd;
ram_rd_addr <= pc_reg;
stage_reg <= STAGE_T0;
end
BRANCH_OPCODE: begin
stage_reg <= STAGE_T0;
case (funct3)
BEQ_FUNCT3: begin
pc_reg <= alu_eq ? ram_data_in : regs_rd_in;
ram_rd_addr <= alu_eq ? ram_data_in : regs_rd_in;
end
BNE_FUNCT3: begin
pc_reg <= !alu_eq ? ram_data_in : regs_rd_in;
ram_rd_addr <= !alu_eq ? ram_data_in : regs_rd_in;
end
BGE_FUNCT3: begin
pc_reg <= alu_bge ? ram_data_in : regs_rd_in;
ram_rd_addr <= alu_bge ? ram_data_in : regs_rd_in;
end
BGEU_FUNCT3: begin
pc_reg <= alu_bgeu ? ram_data_in : regs_rd_in;
ram_rd_addr <= alu_bgeu ? ram_data_in : regs_rd_in;
end
BLT_FUNCT3: begin
pc_reg <= !alu_bge ? ram_data_in : regs_rd_in;
ram_rd_addr <= !alu_bge ? ram_data_in : regs_rd_in;
end
BLTU_FUNCT3: begin
pc_reg <= !alu_bgeu ? ram_data_in : regs_rd_in;
ram_rd_addr <= !alu_bgeu ? ram_data_in : regs_rd_in;
end
default: begin
`ifdef IVERILOG
$display("Unsupported branch function: %d !\n", funct3);
`endif
end
endcase
end
LOAD_OPCODE: begin
ram_rd_addr <= alu_res;
stage_reg <= STAGE_T4;
end
STORE_OPCODE: begin
ram_wr_addr <= alu_res;
regs_rs2_offset <= rs2;
stage_reg <= STAGE_T4;
end
JALR_OPCODE: begin
pc_reg <= {alu_res[31:1], 1'b0};
ram_rd_addr <= {alu_res[31:1], 1'b0};
stage_reg <= STAGE_T0;
end
default: begin
end
endcase
end
STAGE_T4: begin
case (opcode)
LOAD_OPCODE: begin
regs_rd_offset <= rd;
regs_wr_enable <= 1;
ram_rd_addr <= pc_reg;
stage_reg <= STAGE_T0;
case (funct3)
LW_FUNCT3: begin
regs_rd_in <= ram_data_out;
end
LB_FUNCT3: begin
case (alu_res[1:0])
2'b00: begin
regs_rd_in <= {{24{ram_data_out[7]}}, ram_data_out[7:0]};
end
2'b01: begin
regs_rd_in <= {{24{ram_data_out[15]}}, ram_data_out[15:8]};
end
2'b10: begin
regs_rd_in <= {{24{ram_data_out[23]}}, ram_data_out[23:16]};
end
2'b11: begin
regs_rd_in <= {{24{ram_data_out[31]}}, ram_data_out[31:24]};
end
endcase
end
LH_FUNCT3: begin
regs_rd_in <= alu_res[1] ? {{16{ram_data_out[31]}}, ram_data_out[31:16]} :
{{16{ram_data_out[15]}}, ram_data_out[15:0]};
if (alu_res[0]) begin
`ifdef IVERILOG
$display("Unaligned word load !\n");
`endif
end
end
LBU_FUNCT3: begin
case (alu_res[1:0])
2'b00: begin
regs_rd_in <= {24'b0, (ram_data_out[7:0])};
end
2'b01: begin
regs_rd_in <= {24'b0, (ram_data_out[15:8])};
end
2'b10: begin
regs_rd_in <= {24'b0, (ram_data_out[23:16])};
end
2'b11: begin
regs_rd_in <= {24'b0, (ram_data_out[31:24])};
end
endcase
end
LHU_FUNCT3: begin
regs_rd_in <= alu_res[1] ? {16'b0, (ram_data_out[31:16])} :
{16'b0, (ram_data_out[15:0])};
if (alu_res[0]) begin
`ifdef IVERILOG
$display("Unaligned uword load !\n");
`endif
end
end
default: begin
`ifdef IVERILOG
$display("Unsupported load function: %d !\n", funct3);
`endif
end
endcase
end
STORE_OPCODE: begin
ram_wr_enable <= 1;
ram_rd_addr <= pc_reg;
stage_reg <= STAGE_T0;
case (funct3)
SB_FUNCT3: begin
ram_data_in[7:0] <= regs_rs2_out[7:0];
end
SH_FUNCT3: begin
ram_data_in[15:0] <= regs_rs2_out[15:0];
end
SW_FUNCT3: begin
ram_data_in <= regs_rs2_out;
end
default: begin
`ifdef IVERILOG
$display("Unsupported store function: %d !\n", funct3);
`endif
end
endcase
end
endcase
end
default: begin
end
endcase
end else begin
ir <= 0;
pc_reg <= 0;
ram_rd_addr <= 0;
stage_reg <= STAGE_T0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBN_1_V
`define SKY130_FD_SC_LP__DLXBN_1_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog wrapper for dlxbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlxbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxbn_1 (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxbn_1 (
Q ,
Q_N ,
D ,
GATE_N
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBN_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O22AI_BEHAVIORAL_PP_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22AI_BEHAVIORAL_PP_V |
/*
* HIFIFO: Harmon Instruments PCI Express to FIFO
* Copyright (C) 2014 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*/
module sync
(
input clock,
input in,
output out
);
(* ASYNC_REG="TRUE", TIG="TRUE" *) reg [2:0] sreg = 0;
always @(posedge clock)
sreg <= {sreg[1:0], in};
assign out = sreg[2];
endmodule
module one_shot
(
input clock,
input in,
output reg out = 0
);
reg in_prev = 0;
always @(posedge clock)
begin
in_prev <= in;
out <= in & ~in_prev;
end
endmodule
module pulse_stretch
(
input clock,
input in,
output reg out = 0
);
parameter NB=3;
reg [NB-1:0] count = 0;
always @(posedge clock)
begin
if(in)
count <= 1'b1;
else
count <= count + (count != 0);
out <= in | (count != 0);
end
endmodule
module sync_oneshot(input c, input i, output o);
wire synced;
sync sync(.clock(c), .in(i), .o(synced));
one_shot one_shot(.clock(c), .in(synced), .out(o));
endmodule
module sync_pulse (input ci, input co, input i, output reg o = 0);
reg tog = 0;
always @ (posedge ci)
tog <= tog ^ i;
reg [1:0] prev = 0;
always @ (posedge co) begin
prev <= {prev[0], tog};
o <= prev[0] ^ prev[1];
end
endmodule
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Mon Oct 26 08:39:07 EDT 2015
//
// Method conflict info:
// Method: output_arbs_0_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_0_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_1_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_1_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_2_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_2_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_3_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_3_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_4_select
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
// Method: output_arbs_4_next
// Conflict-free: output_arbs_0_select,
// output_arbs_0_next,
// output_arbs_1_select,
// output_arbs_1_next,
// output_arbs_2_select,
// output_arbs_2_next,
// output_arbs_3_select,
// output_arbs_3_next,
// output_arbs_4_select,
// output_arbs_4_next
//
//
// Ports:
// Name I/O size props
// output_arbs_0_select O 5
// output_arbs_1_select O 5
// output_arbs_2_select O 5
// output_arbs_3_select O 5
// output_arbs_4_select O 5
// CLK I 1 unused
// RST_N I 1 unused
// output_arbs_0_select_requests I 5
// output_arbs_1_select_requests I 5
// output_arbs_2_select_requests I 5
// output_arbs_3_select_requests I 5
// output_arbs_4_select_requests I 5
// EN_output_arbs_0_next I 1 unused
// EN_output_arbs_1_next I 1 unused
// EN_output_arbs_2_next I 1 unused
// EN_output_arbs_3_next I 1 unused
// EN_output_arbs_4_next I 1 unused
//
// Combinational paths from inputs to outputs:
// output_arbs_0_select_requests -> output_arbs_0_select
// output_arbs_1_select_requests -> output_arbs_1_select
// output_arbs_2_select_requests -> output_arbs_2_select
// output_arbs_3_select_requests -> output_arbs_3_select
// output_arbs_4_select_requests -> output_arbs_4_select
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkRouterOutputArbitersStatic(CLK,
RST_N,
output_arbs_0_select_requests,
output_arbs_0_select,
EN_output_arbs_0_next,
output_arbs_1_select_requests,
output_arbs_1_select,
EN_output_arbs_1_next,
output_arbs_2_select_requests,
output_arbs_2_select,
EN_output_arbs_2_next,
output_arbs_3_select_requests,
output_arbs_3_select,
EN_output_arbs_3_next,
output_arbs_4_select_requests,
output_arbs_4_select,
EN_output_arbs_4_next);
input CLK;
input RST_N;
// value method output_arbs_0_select
input [4 : 0] output_arbs_0_select_requests;
output [4 : 0] output_arbs_0_select;
// action method output_arbs_0_next
input EN_output_arbs_0_next;
// value method output_arbs_1_select
input [4 : 0] output_arbs_1_select_requests;
output [4 : 0] output_arbs_1_select;
// action method output_arbs_1_next
input EN_output_arbs_1_next;
// value method output_arbs_2_select
input [4 : 0] output_arbs_2_select_requests;
output [4 : 0] output_arbs_2_select;
// action method output_arbs_2_next
input EN_output_arbs_2_next;
// value method output_arbs_3_select
input [4 : 0] output_arbs_3_select_requests;
output [4 : 0] output_arbs_3_select;
// action method output_arbs_3_next
input EN_output_arbs_3_next;
// value method output_arbs_4_select
input [4 : 0] output_arbs_4_select_requests;
output [4 : 0] output_arbs_4_select;
// action method output_arbs_4_next
input EN_output_arbs_4_next;
// signals for module outputs
wire [4 : 0] output_arbs_0_select,
output_arbs_1_select,
output_arbs_2_select,
output_arbs_3_select,
output_arbs_4_select;
// value method output_arbs_0_select
assign output_arbs_0_select =
{ output_arbs_0_select_requests[4],
!output_arbs_0_select_requests[4] &&
output_arbs_0_select_requests[3],
!output_arbs_0_select_requests[4] &&
!output_arbs_0_select_requests[3] &&
output_arbs_0_select_requests[2],
!output_arbs_0_select_requests[4] &&
!output_arbs_0_select_requests[3] &&
!output_arbs_0_select_requests[2] &&
output_arbs_0_select_requests[1],
!output_arbs_0_select_requests[4] &&
!output_arbs_0_select_requests[3] &&
!output_arbs_0_select_requests[2] &&
!output_arbs_0_select_requests[1] &&
output_arbs_0_select_requests[0] } ;
// value method output_arbs_1_select
assign output_arbs_1_select =
{ !output_arbs_1_select_requests[0] &&
output_arbs_1_select_requests[4],
!output_arbs_1_select_requests[0] &&
!output_arbs_1_select_requests[4] &&
output_arbs_1_select_requests[3],
!output_arbs_1_select_requests[0] &&
!output_arbs_1_select_requests[4] &&
!output_arbs_1_select_requests[3] &&
output_arbs_1_select_requests[2],
!output_arbs_1_select_requests[0] &&
!output_arbs_1_select_requests[4] &&
!output_arbs_1_select_requests[3] &&
!output_arbs_1_select_requests[2] &&
output_arbs_1_select_requests[1],
output_arbs_1_select_requests[0] } ;
// value method output_arbs_2_select
assign output_arbs_2_select =
{ !output_arbs_2_select_requests[1] &&
!output_arbs_2_select_requests[0] &&
output_arbs_2_select_requests[4],
!output_arbs_2_select_requests[1] &&
!output_arbs_2_select_requests[0] &&
!output_arbs_2_select_requests[4] &&
output_arbs_2_select_requests[3],
!output_arbs_2_select_requests[1] &&
!output_arbs_2_select_requests[0] &&
!output_arbs_2_select_requests[4] &&
!output_arbs_2_select_requests[3] &&
output_arbs_2_select_requests[2],
output_arbs_2_select_requests[1],
!output_arbs_2_select_requests[1] &&
output_arbs_2_select_requests[0] } ;
// value method output_arbs_3_select
assign output_arbs_3_select =
{ !output_arbs_3_select_requests[2] &&
!output_arbs_3_select_requests[1] &&
!output_arbs_3_select_requests[0] &&
output_arbs_3_select_requests[4],
!output_arbs_3_select_requests[2] &&
!output_arbs_3_select_requests[1] &&
!output_arbs_3_select_requests[0] &&
!output_arbs_3_select_requests[4] &&
output_arbs_3_select_requests[3],
output_arbs_3_select_requests[2],
!output_arbs_3_select_requests[2] &&
output_arbs_3_select_requests[1],
!output_arbs_3_select_requests[2] &&
!output_arbs_3_select_requests[1] &&
output_arbs_3_select_requests[0] } ;
// value method output_arbs_4_select
assign output_arbs_4_select =
{ !output_arbs_4_select_requests[3] &&
!output_arbs_4_select_requests[2] &&
!output_arbs_4_select_requests[1] &&
!output_arbs_4_select_requests[0] &&
output_arbs_4_select_requests[4],
output_arbs_4_select_requests[3],
!output_arbs_4_select_requests[3] &&
output_arbs_4_select_requests[2],
!output_arbs_4_select_requests[3] &&
!output_arbs_4_select_requests[2] &&
output_arbs_4_select_requests[1],
!output_arbs_4_select_requests[3] &&
!output_arbs_4_select_requests[2] &&
!output_arbs_4_select_requests[1] &&
output_arbs_4_select_requests[0] } ;
endmodule // mkRouterOutputArbitersStatic
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR2_1_V
`define SKY130_FD_SC_HDLL__XOR2_1_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xor2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xor2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR2_1_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue Jun 06 02:50:17 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/system_vga_hessian_0_0_stub.v
// Design : system_vga_hessian_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_hessian,Vivado 2016.4" *)
module system_vga_hessian_0_0(clk_x16, active, rst, x_addr, y_addr, g_in,
hessian_out)
/* synthesis syn_black_box black_box_pad_pin="clk_x16,active,rst,x_addr[9:0],y_addr[9:0],g_in[7:0],hessian_out[31:0]" */;
input clk_x16;
input active;
input rst;
input [9:0]x_addr;
input [9:0]y_addr;
input [7:0]g_in;
output [31:0]hessian_out;
endmodule
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: sram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module sram (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [15:0] data;
input [11:0] rdaddress;
input [11:0] wraddress;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "65536"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 12 0 INPUT NODEFVAL "rdaddress[11..0]"
// Retrieval info: USED_PORT: wraddress 0 0 12 0 INPUT NODEFVAL "wraddress[11..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 12 0 wraddress 0 0 12 0
// Retrieval info: CONNECT: @address_b 0 0 12 0 rdaddress 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sram_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sram_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : BUFGCE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 05/15/12 - Initial version.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFGCE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
)(
output O,
input CE,
input I
);
// define constants
localparam MODULE_NAME = "BUFGCE";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam CE_TYPE_ASYNC = 1;
localparam CE_TYPE_SYNC = 0;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
`ifdef XIL_DR
`include "BUFGCE_dr.v"
`else
localparam [40:1] CE_TYPE_REG = CE_TYPE;
localparam [0:0] IS_CE_INVERTED_REG = IS_CE_INVERTED;
localparam [0:0] IS_I_INVERTED_REG = IS_I_INVERTED;
`endif
wire CE_TYPE_BIN;
wire IS_CE_INVERTED_BIN;
wire IS_I_INVERTED_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire O_out;
wire CE_in;
wire I_in;
`ifdef XIL_TIMING
wire CE_dly;
wire I_dly;
assign CE_in = (CE === 1'bz) || (CE_dly ^ IS_CE_INVERTED_BIN); // rv 1
assign I_in = I_dly ^ IS_I_INVERTED_BIN;
`else
assign CE_in = (CE === 1'bz) || (CE ^ IS_CE_INVERTED_BIN); // rv 1
assign I_in = I ^ IS_I_INVERTED_BIN;
`endif
assign O = O_out;
assign CE_TYPE_BIN =
(CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC :
(CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC :
CE_TYPE_SYNC;
assign IS_CE_INVERTED_BIN = IS_CE_INVERTED_REG;
assign IS_I_INVERTED_BIN = IS_I_INVERTED_REG;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((CE_TYPE_REG != "SYNC") &&
(CE_TYPE_REG != "ASYNC"))) begin
$display("Error: [Unisim %s-101] CE_TYPE attribute is set to %s. Legal values for this attribute are SYNC or ASYNC. Instance: %m", MODULE_NAME, CE_TYPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_CE_INVERTED_REG !== 1'b0) && (IS_CE_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-102] IS_CE_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CE_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_I_INVERTED_REG !== 1'b0) && (IS_I_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-103] IS_I_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_I_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
wire ce_inv, ice, CE_TYPE_INV;
reg enable_clk;
assign CE_TYPE_INV = ~CE_TYPE_BIN;
assign ce_inv = ~CE_in;
assign ice = ~(CE_TYPE_INV & I_in);
always @(ice or ce_inv or glblGSR) begin
if (glblGSR)
enable_clk <= 1'b1;
else if (ice)
enable_clk <= ~ce_inv;
end
assign O_out = enable_clk & I_in ;
`ifdef XIL_TIMING
reg notifier;
wire sh_i_en_p;
wire sh_i_en_n;
assign sh_i_en_p = ~IS_I_INVERTED_BIN;
assign sh_i_en_n = IS_I_INVERTED_BIN;
specify
(CE => O) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier,sh_i_en_n,sh_i_en_n, I_dly, CE_dly);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier,sh_i_en_n,sh_i_en_n, I_dly, CE_dly);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier,sh_i_en_p,sh_i_en_p, I_dly, CE_dly);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier,sh_i_en_p,sh_i_en_p, I_dly, CE_dly);
$width (negedge CE, 0:0:0, 0, notifier);
$width (posedge CE, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module ram(
input clk,
input enable,
input write_enable,
input [WIDTH-1 : 0] addr,
input [WIDTH-1 : 0] data_in,
output [WIDTH-1 : 0] data_out);
parameter ADDRESS_WIDTH = 4;
parameter WIDTH = 8;
parameter MEMORY_SIZE = 1 << ADDRESS_WIDTH;
reg [WIDTH-1 : 0] mem [0 : MEMORY_SIZE-1];
initial begin
`ifdef IVERILOG_SIM
$readmemb(`TEST_PROG, mem);
`else
$readmemb("prog_fib.list", mem);
`endif
end
assign data_out = (enable) ? mem[addr] : {WIDTH{1'b0}};
always @(posedge clk) begin
if (write_enable) begin
mem[addr] <= data_in;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_PP_G_TB_V
`define SKY130_FD_SC_HD__UDP_PWRGOOD_PP_G_TB_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_pwrgood_pp_g.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VGND;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VGND = 1'bX;
#20 UDP_IN = 1'b0;
#40 VGND = 1'b0;
#60 UDP_IN = 1'b1;
#80 VGND = 1'b1;
#100 UDP_IN = 1'b0;
#120 VGND = 1'b0;
#140 VGND = 1'b1;
#160 UDP_IN = 1'b1;
#180 VGND = 1'bx;
#200 UDP_IN = 1'bx;
end
sky130_fd_sc_hd__udp_pwrgood_pp$G dut (.UDP_IN(UDP_IN), .VGND(VGND), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_PP_G_TB_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: flop_rptrs_xc1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module flop_rptrs_xc1(/*AUTOARG*/
// Outputs
sparc_out, so, jbussync2_out, jbussync1_out, grst_out,
gdbginit_out, ddrsync2_out, ddrsync1_out, cken_out,
// Inputs
spare_in, se, sd, jbussync2_in, jbussync1_in, grst_in,
gdbginit_in, gclk, ddrsync2_in, ddrsync1_in, cken_in, agrst_l,
adbginit_l
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [25:0] cken_out; // From cken_ff_25_ of bw_u1_soffasr_2x.v, ...
output ddrsync1_out; // From ddrsync1_ff of bw_u1_soffasr_2x.v
output ddrsync2_out; // From ddrsync2_ff of bw_u1_soffasr_2x.v
output gdbginit_out; // From gdbginit_ff of bw_u1_soffasr_2x.v
output grst_out; // From gclk_ff of bw_u1_soffasr_2x.v
output jbussync1_out; // From jbussync1_ff of bw_u1_soffasr_2x.v
output jbussync2_out; // From jbussync2_ff of bw_u1_soffasr_2x.v
output so; // From scanout_latch of bw_u1_scanlg_2x.v
output [5:0] sparc_out; // From spare_ff_5_ of bw_u1_soffasr_2x.v, ...
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To gdbginit_ff of bw_u1_soffasr_2x.v
input agrst_l; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
input [25:0] cken_in; // To cken_ff_25_ of bw_u1_soffasr_2x.v, ...
input ddrsync1_in; // To ddrsync1_ff of bw_u1_soffasr_2x.v
input ddrsync2_in; // To ddrsync2_ff of bw_u1_soffasr_2x.v
input gclk; // To I73 of bw_u1_ckbuf_33x.v
input gdbginit_in; // To gdbginit_ff of bw_u1_soffasr_2x.v
input grst_in; // To gclk_ff of bw_u1_soffasr_2x.v
input jbussync1_in; // To jbussync1_ff of bw_u1_soffasr_2x.v
input jbussync2_in; // To jbussync2_ff of bw_u1_soffasr_2x.v
input sd; // To spare_ff_5_ of bw_u1_soffasr_2x.v
input se; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
input [5:0] spare_in; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire clk; // From I73 of bw_u1_ckbuf_33x.v
wire scan_data_0; // From spare_ff_5_ of bw_u1_soffasr_2x.v
wire scan_data_1; // From spare_ff_4_ of bw_u1_soffasr_2x.v
wire scan_data_10; // From gdbginit_ff of bw_u1_soffasr_2x.v
wire scan_data_11; // From gclk_ff of bw_u1_soffasr_2x.v
wire scan_data_2; // From spare_ff_3_ of bw_u1_soffasr_2x.v
wire scan_data_3; // From spare_ff_2_ of bw_u1_soffasr_2x.v
wire scan_data_4; // From spare_ff_1_ of bw_u1_soffasr_2x.v
wire scan_data_5; // From spare_ff_0_ of bw_u1_soffasr_2x.v
wire scan_data_6; // From jbussync2_ff of bw_u1_soffasr_2x.v
wire scan_data_7; // From jbussync1_ff of bw_u1_soffasr_2x.v
wire scan_data_8; // From ddrsync2_ff of bw_u1_soffasr_2x.v
wire scan_data_9; // From ddrsync1_ff of bw_u1_soffasr_2x.v
// End of automatics
/* bw_u1_ckbuf_33x AUTO_TEMPLATE (
.clk (clk ),
.rclk (gclk ) ); */
bw_u1_ckbuf_33x I73
(/*AUTOINST*/
// Outputs
.clk (clk ), // Templated
// Inputs
.rclk (gclk )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (sparc_out[@]),
.d (spare_in[@]),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.sd (scan_data_@"(- 4 @)" ),
.so (scan_data_@"(- 5 @)" ),
); */
bw_u1_soffasr_2x spare_ff_5_
(
// Inputs
.sd (sd ),
/*AUTOINST*/
// Outputs
.q (sparc_out[5]), // Templated
.so (scan_data_0 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[5]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se));
bw_u1_soffasr_2x spare_ff_4_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[4]), // Templated
.so (scan_data_1 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[4]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_0 )); // Templated
bw_u1_soffasr_2x spare_ff_3_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[3]), // Templated
.so (scan_data_2 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[3]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_1 )); // Templated
bw_u1_soffasr_2x spare_ff_2_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[2]), // Templated
.so (scan_data_3 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[2]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_2 )); // Templated
bw_u1_soffasr_2x spare_ff_1_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[1]), // Templated
.so (scan_data_4 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[1]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_3 )); // Templated
bw_u1_soffasr_2x spare_ff_0_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[0]), // Templated
.so (scan_data_5 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[0]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_4 )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (cken_out[@] ),
.d (cken_in[@] ),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (1'b0),
.sd (1'b0),
.so (),
); */
bw_u1_soffasr_2x cken_ff_25_
( /*AUTOINST*/
// Outputs
.q (cken_out[25] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[25] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_24_
( /*AUTOINST*/
// Outputs
.q (cken_out[24] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[24] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_23_
( /*AUTOINST*/
// Outputs
.q (cken_out[23] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[23] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_22_
( /*AUTOINST*/
// Outputs
.q (cken_out[22] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[22] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_21_
( /*AUTOINST*/
// Outputs
.q (cken_out[21] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[21] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_20_
( /*AUTOINST*/
// Outputs
.q (cken_out[20] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[20] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_19_
( /*AUTOINST*/
// Outputs
.q (cken_out[19] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[19] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_18_
( /*AUTOINST*/
// Outputs
.q (cken_out[18] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[18] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_17_
( /*AUTOINST*/
// Outputs
.q (cken_out[17] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[17] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_16_
( /*AUTOINST*/
// Outputs
.q (cken_out[16] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[16] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_15_
( /*AUTOINST*/
// Outputs
.q (cken_out[15] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[15] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_14_
( /*AUTOINST*/
// Outputs
.q (cken_out[14] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[14] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_13_
( /*AUTOINST*/
// Outputs
.q (cken_out[13] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[13] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_12_
( /*AUTOINST*/
// Outputs
.q (cken_out[12] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[12] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_11_
( /*AUTOINST*/
// Outputs
.q (cken_out[11] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[11] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_10_
( /*AUTOINST*/
// Outputs
.q (cken_out[10] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[10] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_9_
( /*AUTOINST*/
// Outputs
.q (cken_out[9] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[9] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_8_
( /*AUTOINST*/
// Outputs
.q (cken_out[8] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[8] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_7_
( /*AUTOINST*/
// Outputs
.q (cken_out[7] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[7] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_6_
( /*AUTOINST*/
// Outputs
.q (cken_out[6] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[6] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_5_
( /*AUTOINST*/
// Outputs
.q (cken_out[5] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[5] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_4_
( /*AUTOINST*/
// Outputs
.q (cken_out[4] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[4] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_3_
( /*AUTOINST*/
// Outputs
.q (cken_out[3] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[3] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_2_
( /*AUTOINST*/
// Outputs
.q (cken_out[2] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[2] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_1_
( /*AUTOINST*/
// Outputs
.q (cken_out[1] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[1] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_0_
( /*AUTOINST*/
// Outputs
.q (cken_out[0] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[0] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (se ),
); */
bw_u1_soffasr_2x ddrsync1_ff
(
// Outputs
.q (ddrsync1_out ),
.so (scan_data_9 ),
// Inputs
.d (ddrsync1_in ),
.sd (scan_data_8 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x ddrsync2_ff
(
// Outputs
.q (ddrsync2_out ),
.so (scan_data_8 ),
// Inputs
.d (ddrsync2_in ),
.sd (scan_data_7 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync1_ff
(
// Outputs
.q (jbussync1_out ),
.so (scan_data_7 ),
// Inputs
.d (jbussync1_in ),
.sd (scan_data_6 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync2_ff
(
// Outputs
.q (jbussync2_out ),
.so (scan_data_6 ),
// Inputs
.d (jbussync2_in ),
.sd (scan_data_5 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gdbginit_ff
(
// Outputs
.q (gdbginit_out ),
.so (scan_data_10 ),
// Inputs
.d (gdbginit_in ),
.sd (scan_data_9 ),
.r_l (adbginit_l),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gclk_ff
(
// Outputs
.q (grst_out ),
.so (scan_data_11 ),
// Inputs
.d (grst_in ),
.sd (scan_data_10 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
/* bw_u1_scanlg_2x AUTO_TEMPLATE (
.sd (scan_data_11 ),
.ck (clk ),
); */
bw_u1_scanlg_2x scanout_latch
( /*AUTOINST*/
// Outputs
.so (so),
// Inputs
.sd (scan_data_11 ), // Templated
.ck (clk ), // Templated
.se (1'b1));
endmodule
// Local Variables:
// verilog-library-files:("../../../common/rtl/u1.behV" )
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41AI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O41AI_BEHAVIORAL_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o41ai (
Y ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41AI_BEHAVIORAL_V |
/*
This file is a simple top level that will generate one of four types of
Avalon-MM master. As a result all the ports must be declared and it will be
up to the component .tcl file to stub unused signals.
*/
// altera message_off 10034
module custom_master (
clk,
reset,
// control inputs and outputs
control_fixed_location,
control_read_base,
control_read_length,
control_write_base,
control_write_length,
control_go,
control_done,
control_early_done,
// user logic inputs and outputs
user_read_buffer,
user_write_buffer,
user_buffer_input_data,
user_buffer_output_data,
user_data_available,
user_buffer_full,
// master inputs and outputs
master_address,
master_read,
master_write,
master_byteenable,
master_readdata,
master_readdatavalid,
master_writedata,
master_burstcount,
master_waitrequest
);
parameter MASTER_DIRECTION = 0; // 0 for read master, 1 for write master
parameter DATA_WIDTH = 32;
parameter MEMORY_BASED_FIFO = 1; // 0 for LE/ALUT FIFOs, 1 for memory FIFOs (highly recommend 1)
parameter FIFO_DEPTH = 32;
parameter FIFO_DEPTH_LOG2 = 5;
parameter ADDRESS_WIDTH = 32;
parameter BURST_CAPABLE = 0; // 1 to enable burst, 0 to disable it
parameter MAXIMUM_BURST_COUNT = 2;
parameter BURST_COUNT_WIDTH = 2;
input clk;
input reset;
// control inputs and outputs
input control_fixed_location;
input [ADDRESS_WIDTH-1:0] control_read_base; // for read master
input [ADDRESS_WIDTH-1:0] control_read_length; // for read master
input [ADDRESS_WIDTH-1:0] control_write_base; // for write master
input [ADDRESS_WIDTH-1:0] control_write_length; // for write master
input control_go;
output wire control_done;
output wire control_early_done; // for read master
// user logic inputs and outputs
input user_read_buffer; // for read master
input user_write_buffer; // for write master
input [DATA_WIDTH-1:0] user_buffer_input_data; // for write master
output wire [DATA_WIDTH-1:0] user_buffer_output_data; // for read master
output wire user_data_available; // for read master
output wire user_buffer_full; // for write master
// master inputs and outputs
output wire [ADDRESS_WIDTH-1:0] master_address;
output wire master_read; // for read master
output wire master_write; // for write master
output wire [(DATA_WIDTH/8)-1:0] master_byteenable;
input [DATA_WIDTH-1:0] master_readdata; // for read master
input master_readdatavalid; // for read master
output wire [DATA_WIDTH-1:0] master_writedata; // for write master
output wire [BURST_COUNT_WIDTH-1:0] master_burstcount; // for bursting read and write masters
input master_waitrequest;
generate // big generate if statement to select the approprate master depending on the direction and burst parameters
if(MASTER_DIRECTION == 0)
begin
if(BURST_CAPABLE == 1)
begin
burst_read_master a_burst_read_master(
.clk (clk),
.reset (reset),
.control_fixed_location (control_fixed_location),
.control_read_base (control_read_base),
.control_read_length (control_read_length),
.control_go (control_go),
.control_done (control_done),
.control_early_done (control_early_done),
.user_read_buffer (user_read_buffer),
.user_buffer_data (user_buffer_output_data),
.user_data_available (user_data_available),
.master_address (master_address),
.master_read (master_read),
.master_byteenable (master_byteenable),
.master_readdata (master_readdata),
.master_readdatavalid (master_readdatavalid),
.master_burstcount (master_burstcount),
.master_waitrequest (master_waitrequest)
);
defparam a_burst_read_master.DATAWIDTH = DATA_WIDTH;
defparam a_burst_read_master.MAXBURSTCOUNT = MAXIMUM_BURST_COUNT;
defparam a_burst_read_master.BURSTCOUNTWIDTH = BURST_COUNT_WIDTH;
defparam a_burst_read_master.BYTEENABLEWIDTH = DATA_WIDTH/8;
defparam a_burst_read_master.ADDRESSWIDTH = ADDRESS_WIDTH;
defparam a_burst_read_master.FIFODEPTH = FIFO_DEPTH;
defparam a_burst_read_master.FIFODEPTH_LOG2 = FIFO_DEPTH_LOG2;
defparam a_burst_read_master.FIFOUSEMEMORY = MEMORY_BASED_FIFO;
end
else
begin
latency_aware_read_master a_latency_aware_read_master(
.clk (clk),
.reset (reset),
.control_fixed_location (control_fixed_location),
.control_read_base (control_read_base),
.control_read_length (control_read_length),
.control_go (control_go),
.control_done (control_done),
.control_early_done (control_early_done),
.user_read_buffer (user_read_buffer),
.user_buffer_data (user_buffer_output_data),
.user_data_available (user_data_available),
.master_address (master_address),
.master_read (master_read),
.master_byteenable (master_byteenable),
.master_readdata (master_readdata),
.master_readdatavalid (master_readdatavalid),
.master_waitrequest (master_waitrequest)
);
defparam a_latency_aware_read_master.DATAWIDTH = DATA_WIDTH;
defparam a_latency_aware_read_master.BYTEENABLEWIDTH = DATA_WIDTH/8;
defparam a_latency_aware_read_master.ADDRESSWIDTH = ADDRESS_WIDTH;
defparam a_latency_aware_read_master.FIFODEPTH = FIFO_DEPTH;
defparam a_latency_aware_read_master.FIFODEPTH_LOG2 = FIFO_DEPTH_LOG2;
defparam a_latency_aware_read_master.FIFOUSEMEMORY = MEMORY_BASED_FIFO;
end
end
else
begin
if(BURST_CAPABLE == 1)
begin
burst_write_master a_burst_write_master(
.clk (clk),
.reset (reset),
.control_fixed_location (control_fixed_location),
.control_write_base (control_write_base),
.control_write_length (control_write_length),
.control_go (control_go),
.control_done (control_done),
.user_write_buffer (user_write_buffer),
.user_buffer_data (user_buffer_input_data),
.user_buffer_full (user_buffer_full),
.master_address (master_address),
.master_write (master_write),
.master_byteenable (master_byteenable),
.master_writedata (master_writedata),
.master_burstcount (master_burstcount),
.master_waitrequest (master_waitrequest)
);
defparam a_burst_write_master.DATAWIDTH = DATA_WIDTH;
defparam a_burst_write_master.MAXBURSTCOUNT = MAXIMUM_BURST_COUNT;
defparam a_burst_write_master.BURSTCOUNTWIDTH = BURST_COUNT_WIDTH;
defparam a_burst_write_master.BYTEENABLEWIDTH = DATA_WIDTH/8;
defparam a_burst_write_master.ADDRESSWIDTH = ADDRESS_WIDTH;
defparam a_burst_write_master.FIFODEPTH = FIFO_DEPTH;
defparam a_burst_write_master.FIFODEPTH_LOG2 = FIFO_DEPTH_LOG2;
defparam a_burst_write_master.FIFOUSEMEMORY = MEMORY_BASED_FIFO;
end
else
begin
write_master a_write_master(
.clk (clk),
.reset (reset),
.control_fixed_location (control_fixed_location),
.control_write_base (control_write_base),
.control_write_length (control_write_length),
.control_go (control_go),
.control_done (control_done),
.user_write_buffer (user_write_buffer),
.user_buffer_data (user_buffer_input_data),
.user_buffer_full (user_buffer_full),
.master_address (master_address),
.master_write (master_write),
.master_byteenable (master_byteenable),
.master_writedata (master_writedata),
.master_waitrequest (master_waitrequest)
);
defparam a_write_master.DATAWIDTH = DATA_WIDTH;
defparam a_write_master.BYTEENABLEWIDTH = DATA_WIDTH/8;
defparam a_write_master.ADDRESSWIDTH = ADDRESS_WIDTH;
defparam a_write_master.FIFODEPTH = FIFO_DEPTH;
defparam a_write_master.FIFODEPTH_LOG2 = FIFO_DEPTH_LOG2;
defparam a_write_master.FIFOUSEMEMORY = MEMORY_BASED_FIFO;
end
end
endgenerate
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the program counter
// Import the modules that will be tested for in this testbench
`include "prog_counter.v"
// IMPORTANT: To run this, try: ncverilog -f prog_counter.f +gui
module tb_prog_counter();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the prog_counter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// next_pc output signal
wire [0:31] n_pc;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// clk, rst
reg clock,reset;
// cur_pc
reg [0:31] c_pc;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 5ns <==> 200 MHz clock
*/
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of regfile() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
program_counter pc (
// instance_name(signal name),
// Signal name can be the same as the instance name
// next_pc,cur_pc,rst,clk
n_pc,c_pc,reset,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
c_pc=$random;
reset=1'b1;
#10
c_pc=200;
reset=1'b0;
// Write to 8 data locations
for(count=200; count<216; count=count+1)
begin
#20
//c_pc=count;
c_pc=n_pc;
reset=1'b0;
end
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41A_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O41A_BEHAVIORAL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
// Local signals
wire A4 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41A_BEHAVIORAL_V |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module hls_gamma_correction_AXILiteS_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 6,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
// user signals
output wire [7:0] gamma,
output wire [15:0] height,
output wire [15:0] width
);
//------------------------Address Info-------------------
// 0x00 : reserved
// 0x04 : reserved
// 0x08 : reserved
// 0x0c : reserved
// 0x10 : Data signal of gamma
// bit 7~0 - gamma[7:0] (Read/Write)
// others - reserved
// 0x14 : reserved
// 0x18 : Data signal of height
// bit 15~0 - height[15:0] (Read/Write)
// others - reserved
// 0x1c : reserved
// 0x20 : Data signal of width
// bit 15~0 - width[15:0] (Read/Write)
// others - reserved
// 0x24 : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_GAMMA_DATA_0 = 6'h10,
ADDR_GAMMA_CTRL = 6'h14,
ADDR_HEIGHT_DATA_0 = 6'h18,
ADDR_HEIGHT_CTRL = 6'h1c,
ADDR_WIDTH_DATA_0 = 6'h20,
ADDR_WIDTH_CTRL = 6'h24,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
WRRESET = 2'd3,
RDIDLE = 2'd0,
RDDATA = 2'd1,
RDRESET = 2'd2,
ADDR_BITS = 6;
//------------------------Local signal-------------------
reg [1:0] wstate = WRRESET;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate = RDRESET;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
reg [7:0] int_gamma = 'b0;
reg [15:0] int_height = 'b0;
reg [15:0] int_width = 'b0;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRRESET;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDRESET;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_GAMMA_DATA_0: begin
rdata <= int_gamma[7:0];
end
ADDR_HEIGHT_DATA_0: begin
rdata <= int_height[15:0];
end
ADDR_WIDTH_DATA_0: begin
rdata <= int_width[15:0];
end
endcase
end
end
end
//------------------------Register logic-----------------
assign gamma = int_gamma;
assign height = int_height;
assign width = int_width;
// int_gamma[7:0]
always @(posedge ACLK) begin
if (ARESET)
int_gamma[7:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GAMMA_DATA_0)
int_gamma[7:0] <= (WDATA[31:0] & wmask) | (int_gamma[7:0] & ~wmask);
end
end
// int_height[15:0]
always @(posedge ACLK) begin
if (ARESET)
int_height[15:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_HEIGHT_DATA_0)
int_height[15:0] <= (WDATA[31:0] & wmask) | (int_height[15:0] & ~wmask);
end
end
// int_width[15:0]
always @(posedge ACLK) begin
if (ARESET)
int_width[15:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_WIDTH_DATA_0)
int_width[15:0] <= (WDATA[31:0] & wmask) | (int_width[15:0] & ~wmask);
end
end
//------------------------Memory logic-------------------
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD1_FUNCTIONAL_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD1_FUNCTIONAL_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__clkdlyinv5sd1 (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD1_FUNCTIONAL_V |
//
// cpu.v -- the ECO32 CPU
//
module cpu(clk, reset,
bus_en, bus_wr, bus_size, bus_addr,
bus_data_in, bus_data_out, bus_wt,
irq);
input clk; // system clock
input reset; // system reset
output bus_en; // bus enable
output bus_wr; // bus write
output [1:0] bus_size; // 00: byte, 01: halfword, 10: word
output [31:0] bus_addr; // bus address
input [31:0] bus_data_in; // bus data input, for reads
output [31:0] bus_data_out; // bus data output, for writes
input bus_wt; // bus wait
input [15:0] irq; // interrupt requests
// program counter
wire [31:0] pc; // program counter
wire pc_we; // pc write enable
wire [2:0] pc_src; // pc source selector
wire [31:0] pc_next; // value written into pc
// bus & mmu
wire [31:0] mar; // memory address register
wire mar_we; // mar write enable
wire ma_src; // memory address source selector
wire [2:0] mmu_fnc; // mmu function
wire [31:0] virt_addr; // virtual address
wire [31:0] phys_addr; // physical address
wire [31:0] mdor; // memory data out register
wire mdor_we; // mdor write enable
wire [31:0] mdir; // memory data in register
wire mdir_we; // mdir write enable
wire mdir_sx; // mdir sign-extend
// instruction register & decoder
wire ir_we; // ir write enable
wire [5:0] opcode; // opcode part of ir
wire [4:0] reg1; // register 1 part of ir
wire [4:0] reg2; // register 2 part of ir
wire [4:0] reg3; // register 3 part of ir
wire [31:0] sx16; // sign-extended 16-bit immediate
wire [31:0] zx16; // zero-extended 16-bit immediate
wire [31:0] hi16; // high 16-bit immediate
wire [31:0] sx16s2; // sign-extended 16-bit immediate << 2
wire [31:0] sx26s2; // sign-extended 26-bit immediate << 2
// register file
wire [4:0] reg_a1; // register address 1
wire [31:0] reg_do1; // register data out 1
wire [1:0] reg_src2; // register source 2 selector
wire [4:0] reg_a2; // register address 2
wire [31:0] reg_do2; // register data out 2
wire reg_we2; // register write enable 2
wire reg_we2_prot; // register write enable 2,
// protected against writes with a2 = 0
wire [2:0] reg_di2_src; // register data in 2 source selector
wire [31:0] reg_di2; // register data in 2
// alu, shift, and muldiv units
wire alu_src1; // alu source 1 selector
wire [31:0] alu_op1; // alu operand 1
wire [2:0] alu_src2; // alu source 2 selector
wire [31:0] alu_op2; // alu operand 2
wire [2:0] alu_fnc; // alu function
wire [31:0] alu_res; // alu result
wire alu_equ; // alu operand 1 = operand 2
wire alu_ult; // alu operand 1 < operand 2 (unsigned)
wire alu_slt; // alu operand 1 < operand 2 (signed)
wire [1:0] shift_fnc; // shift function
wire [31:0] shift_res; // shift result
wire [2:0] muldiv_fnc; // muldiv function
wire muldiv_start; // muldiv should start
wire muldiv_done; // muldiv has finished
wire muldiv_error; // muldiv detected division by zero
wire [31:0] muldiv_res; // muldiv result
// special registers
wire [2:0] sreg_num; // special register number
wire sreg_we; // special register write enable
wire [31:0] sreg_di; // special register data in
wire [31:0] sreg_do; // special register data out
wire [31:0] psw; // special register 0 (psw) contents
wire psw_we; // psw write enable
wire [31:0] psw_new; // new psw contents
wire [31:0] tlb_index; // special register 1 (tlb index) contents
wire tlb_index_we; // tlb index write enable
wire [31:0] tlb_index_new; // new tlb index contents
wire [31:0] tlb_entry_hi; // special register 2 (tlb entry hi) contents
wire tlb_entry_hi_we; // tlb entry hi write enable
wire [31:0] tlb_entry_hi_new; // new tlb entry hi contents
wire [31:0] tlb_entry_lo; // special register 3 (tlb entry lo) contents
wire tlb_entry_lo_we; // tlb entry lo write enable
wire [31:0] tlb_entry_lo_new; // new tlb entry lo contents
wire [31:0] mmu_bad_addr; // special register 4 (mmu bad addr) contents
wire mmu_bad_addr_we; // mmu bad addr write enable
wire [31:0] mmu_bad_addr_new; // new mmu bad addr contents
// mmu & tlb
wire tlb_kmissed; // page not found in tlb, MSB of addr is 1
wire tlb_umissed; // page not found in tlb, MSB of addr is 0
wire tlb_invalid; // tlb entry is invalid
wire tlb_wrtprot; // frame is write-protected
//------------------------------------------------------------
// program counter
assign pc_next = (pc_src == 3'b000) ? alu_res :
(pc_src == 3'b001) ? 32'hE0000000 :
(pc_src == 3'b010) ? 32'hE0000004 :
(pc_src == 3'b011) ? 32'hC0000004 :
(pc_src == 3'b100) ? 32'hE0000008 :
(pc_src == 3'b101) ? 32'hC0000008 :
32'hxxxxxxxx;
pc pc1(clk, pc_we, pc_next, pc);
// bus & mmu
mar mar1(clk, mar_we, alu_res, mar);
assign virt_addr = (ma_src == 0) ? pc : mar;
mmu mmu1(clk, reset, mmu_fnc, virt_addr, phys_addr,
tlb_index, tlb_index_new,
tlb_entry_hi, tlb_entry_hi_new,
tlb_entry_lo, tlb_entry_lo_new,
tlb_kmissed, tlb_umissed,
tlb_invalid, tlb_wrtprot);
assign bus_addr = phys_addr;
mdor mdor1(clk, mdor_we, reg_do2, mdor);
assign bus_data_out = mdor;
mdir mdir1(clk, mdir_we, bus_data_in, bus_size, mdir_sx, mdir);
// instruction register & decoder
ir ir1(clk,
ir_we, bus_data_in,
opcode, reg1, reg2, reg3,
sx16, zx16, hi16, sx16s2, sx26s2);
// register file
assign reg_a1 = reg1;
assign reg_a2 = (reg_src2 == 2'b00) ? reg2 :
(reg_src2 == 2'b01) ? reg3 :
(reg_src2 == 2'b10) ? 5'b11111 :
(reg_src2 == 2'b11) ? 5'b11110 :
5'bxxxxx;
assign reg_we2_prot = reg_we2 & (| reg_a2[4:0]);
assign reg_di2 = (reg_di2_src == 3'b000) ? alu_res :
(reg_di2_src == 3'b001) ? shift_res :
(reg_di2_src == 3'b010) ? muldiv_res :
(reg_di2_src == 3'b011) ? mdir :
(reg_di2_src == 3'b100) ? sreg_do :
32'hxxxxxxxx;
regs regs1(clk,
reg_a1, reg_do1,
reg_a2, reg_do2, reg_we2_prot, reg_di2);
// alu, shift, and muldiv units
assign alu_op1 = (alu_src1 == 0) ? pc : reg_do1;
assign alu_op2 = (alu_src2 == 3'b000) ? 32'h00000004 :
(alu_src2 == 3'b001) ? reg_do2 :
(alu_src2 == 3'b010) ? sx16 :
(alu_src2 == 3'b011) ? zx16 :
(alu_src2 == 3'b100) ? hi16 :
(alu_src2 == 3'b101) ? sx16s2 :
(alu_src2 == 3'b110) ? sx26s2 :
32'hxxxxxxxx;
alu alu1(alu_op1, alu_op2, alu_fnc,
alu_res, alu_equ, alu_ult, alu_slt);
shift shift1(clk, alu_op1, alu_op2[4:0], shift_fnc, shift_res);
muldiv muldiv1(clk, alu_op1, alu_op2, muldiv_fnc, muldiv_start,
muldiv_done, muldiv_error, muldiv_res);
// special registers
assign sreg_num = zx16[2:0];
assign sreg_di = reg_do2;
sregs sregs1(clk, reset,
sreg_num, sreg_we, sreg_di, sreg_do,
psw, psw_we, psw_new,
tlb_index, tlb_index_we, tlb_index_new,
tlb_entry_hi, tlb_entry_hi_we, tlb_entry_hi_new,
tlb_entry_lo, tlb_entry_lo_we, tlb_entry_lo_new,
mmu_bad_addr, mmu_bad_addr_we, mmu_bad_addr_new);
assign mmu_bad_addr_new = virt_addr;
// ctrl
ctrl ctrl1(clk, reset,
opcode, alu_equ, alu_ult, alu_slt,
bus_wt, bus_en, bus_wr, bus_size,
pc_src, pc_we,
mar_we, ma_src, mmu_fnc,
mdor_we, mdir_we, mdir_sx, ir_we,
reg_src2, reg_di2_src, reg_we2,
alu_src1, alu_src2, alu_fnc, shift_fnc,
muldiv_fnc, muldiv_start,
muldiv_done, muldiv_error,
sreg_we, irq, psw, psw_we, psw_new,
virt_addr[31], virt_addr[1], virt_addr[0],
tlb_kmissed, tlb_umissed,
tlb_invalid, tlb_wrtprot,
tlb_index_we, tlb_entry_hi_we,
tlb_entry_lo_we, mmu_bad_addr_we);
endmodule
//--------------------------------------------------------------
// ctrl -- the finite state machine within the CPU
//--------------------------------------------------------------
module ctrl(clk, reset,
opcode, alu_equ, alu_ult, alu_slt,
bus_wt, bus_en, bus_wr, bus_size,
pc_src, pc_we,
mar_we, ma_src, mmu_fnc,
mdor_we, mdir_we, mdir_sx, ir_we,
reg_src2, reg_di2_src, reg_we2,
alu_src1, alu_src2, alu_fnc, shift_fnc,
muldiv_fnc, muldiv_start,
muldiv_done, muldiv_error,
sreg_we, irq, psw, psw_we, psw_new,
va_31, va_1, va_0,
tlb_kmissed, tlb_umissed,
tlb_invalid, tlb_wrtprot,
tlb_index_we, tlb_entry_hi_we,
tlb_entry_lo_we, mmu_bad_addr_we);
input clk;
input reset;
input [5:0] opcode;
input alu_equ;
input alu_ult;
input alu_slt;
input bus_wt;
output reg bus_en;
output reg bus_wr;
output reg [1:0] bus_size;
output reg [2:0] pc_src;
output reg pc_we;
output reg mar_we;
output reg ma_src;
output reg [2:0] mmu_fnc;
output reg mdor_we;
output reg mdir_we;
output reg mdir_sx;
output reg ir_we;
output reg [1:0] reg_src2;
output reg [2:0] reg_di2_src;
output reg reg_we2;
output reg alu_src1;
output reg [2:0] alu_src2;
output reg [2:0] alu_fnc;
output reg [1:0] shift_fnc;
output reg [2:0] muldiv_fnc;
output reg muldiv_start;
input muldiv_done;
input muldiv_error;
output reg sreg_we;
input [15:0] irq;
input [31:0] psw;
output reg psw_we;
output reg [31:0] psw_new;
input va_31, va_1, va_0;
input tlb_kmissed;
input tlb_umissed;
input tlb_invalid;
input tlb_wrtprot;
output reg tlb_index_we;
output reg tlb_entry_hi_we;
output reg tlb_entry_lo_we;
output reg mmu_bad_addr_we;
wire type_rrr; // instr type is RRR
wire type_rrs; // instr type is RRS
wire type_rrh; // instr type is RRH
wire type_rhh; // instr type is RHH
wire type_rrb; // instr type is RRB
wire type_j; // instr type is J
wire type_jr; // instr type is JR
wire type_link; // instr saves PC+4 in $31
wire type_ld; // instr loads data
wire type_st; // instr stores data
wire type_ldst; // instr loads or stores data
wire [1:0] ldst_size; // load/store transfer size
wire type_shift; // instr uses the shift unit
wire type_muldiv; // instr uses the muldiv unit
wire type_fast; // instr is not shift or muldiv
wire type_mvfs; // instr is mvfs
wire type_mvts; // instr is mvts
wire type_rfx; // instr is rfx
wire type_trap; // instr is trap
wire type_tb; // instr is a TLB instr
reg [4:0] state; // cpu internal state
// 0: reset
// 1: fetch instr (addr xlat)
// 2: decode instr
// increment pc by 4
// possibly store pc+4 in $31
// 3: execute RRR-type instr
// 4: execute RRS-type instr
// 5: execute RRH-type instr
// 6: execute RHH-type instr
// 7: execute RRB-type instr (1)
// 8: execute RRB-type instr (2)
// 9: execute J-type instr
// 10: execute JR-type instr
// 11: execute LDST-type instr (1)
// 12: execute LD-type instr (addr xlat)
// 13: execute LD-type instr (3)
// 14: execute ST-type instr (addr xlat)
// 15: interrupt
// 16: extra state for RRR shift instr
// 17: extra state for RRH shift instr
// 18: extra state for RRR muldiv instr
// 19: extra state for RRS muldiv instr
// 20: extra state for RRH muldiv instr
// 21: execute mvfs instr
// 22: execute mvts instr
// 23: execute rfx instr
// 24: irq_trigger check for mvts and rfx
// 25: exception (locus is PC-4)
// 26: exception (locus is PC)
// 27: execute TLB instr
// 28: fetch instr (bus cycle)
// 29: execute LD-type instr (bus cycle)
// 30: execute ST-type instr (bus cycle)
// all other: unused
reg branch; // take the branch iff true
wire [15:0] irq_pending; // the vector of pending unmasked irqs
wire irq_trigger; // true iff any pending irq is present
// and interrupts are globally enabled
reg [3:0] irq_priority; // highest priority of pending interrupts
reg [3:0] exc_priority; // exception, when entering state 25 or 26
reg [7:0] bus_count; // counter to detect bus timeout
wire bus_timeout; // bus timeout detected
wire exc_prv_addr; // privileged address exception detected
wire exc_ill_addr; // illegal address exception detected
wire exc_tlb_but_wrtprot; // any tlb exception but write protection
wire exc_tlb_any; // any tlb exception
//------------------------------------------------------------
// decode instr type
assign type_rrr = ((opcode == 6'h00) ||
(opcode == 6'h02) ||
(opcode == 6'h04) ||
(opcode == 6'h06) ||
(opcode == 6'h08) ||
(opcode == 6'h0A) ||
(opcode == 6'h0C) ||
(opcode == 6'h0E) ||
(opcode == 6'h10) ||
(opcode == 6'h12) ||
(opcode == 6'h14) ||
(opcode == 6'h16) ||
(opcode == 6'h18) ||
(opcode == 6'h1A) ||
(opcode == 6'h1C)) ? 1 : 0;
assign type_rrs = ((opcode == 6'h01) ||
(opcode == 6'h03) ||
(opcode == 6'h05) ||
(opcode == 6'h09) ||
(opcode == 6'h0D)) ? 1 : 0;
assign type_rrh = ((opcode == 6'h07) ||
(opcode == 6'h0B) ||
(opcode == 6'h0F) ||
(opcode == 6'h11) ||
(opcode == 6'h13) ||
(opcode == 6'h15) ||
(opcode == 6'h17) ||
(opcode == 6'h19) ||
(opcode == 6'h1B) ||
(opcode == 6'h1D)) ? 1 : 0;
assign type_rhh = (opcode == 6'h1F) ? 1 : 0;
assign type_rrb = ((opcode == 6'h20) ||
(opcode == 6'h21) ||
(opcode == 6'h22) ||
(opcode == 6'h23) ||
(opcode == 6'h24) ||
(opcode == 6'h25) ||
(opcode == 6'h26) ||
(opcode == 6'h27) ||
(opcode == 6'h28) ||
(opcode == 6'h29)) ? 1 : 0;
assign type_j = ((opcode == 6'h2A) ||
(opcode == 6'h2C)) ? 1 : 0;
assign type_jr = ((opcode == 6'h2B) ||
(opcode == 6'h2D)) ? 1 : 0;
assign type_link = ((opcode == 6'h2C) ||
(opcode == 6'h2D)) ? 1 : 0;
assign type_ld = ((opcode == 6'h30) ||
(opcode == 6'h31) ||
(opcode == 6'h32) ||
(opcode == 6'h33) ||
(opcode == 6'h34)) ? 1 : 0;
assign type_st = ((opcode == 6'h35) ||
(opcode == 6'h36) ||
(opcode == 6'h37)) ? 1 : 0;
assign type_ldst = type_ld | type_st;
assign ldst_size = ((opcode == 6'h30) ||
(opcode == 6'h35)) ? 2'b10 :
((opcode == 6'h31) ||
(opcode == 6'h32) ||
(opcode == 6'h36)) ? 2'b01 :
((opcode == 6'h33) ||
(opcode == 6'h34) ||
(opcode == 6'h37)) ? 2'b00 :
2'bxx;
assign type_shift = ((opcode == 6'h18) ||
(opcode == 6'h19) ||
(opcode == 6'h1A) ||
(opcode == 6'h1B) ||
(opcode == 6'h1C) ||
(opcode == 6'h1D)) ? 1 : 0;
assign type_muldiv = ((opcode == 6'h04) ||
(opcode == 6'h05) ||
(opcode == 6'h06) ||
(opcode == 6'h07) ||
(opcode == 6'h08) ||
(opcode == 6'h09) ||
(opcode == 6'h0A) ||
(opcode == 6'h0B) ||
(opcode == 6'h0C) ||
(opcode == 6'h0D) ||
(opcode == 6'h0E) ||
(opcode == 6'h0F)) ? 1 : 0;
assign type_fast = ~(type_shift | type_muldiv);
assign type_mvfs = (opcode == 6'h38) ? 1 : 0;
assign type_mvts = (opcode == 6'h39) ? 1 : 0;
assign type_rfx = (opcode == 6'h2F) ? 1 : 0;
assign type_trap = (opcode == 6'h2E) ? 1 : 0;
assign type_tb = ((opcode == 6'h3A) ||
(opcode == 6'h3B) ||
(opcode == 6'h3C) ||
(opcode == 6'h3D)) ? 1 : 0;
// state machine
always @(posedge clk) begin
if (reset == 1) begin
state <= 0;
end else begin
case (state)
5'd0: // reset
begin
state <= 5'd1;
end
5'd1: // fetch instr (addr xlat)
begin
if (exc_prv_addr) begin
state <= 26;
exc_priority <= 4'd9;
end else
if (exc_ill_addr) begin
state <= 26;
exc_priority <= 4'd8;
end else begin
state <= 5'd28;
end
end
5'd2: // decode instr
// increment pc by 4
// possibly store pc+4 in $31
begin
if (type_rrr) begin
// RRR-type instruction
state <= 5'd3;
end else
if (type_rrs) begin
// RRS-type instruction
state <= 5'd4;
end else
if (type_rrh) begin
// RRH-type instruction
state <= 5'd5;
end else
if (type_rhh) begin
// RHH-type instruction
state <= 5'd6;
end else
if (type_rrb) begin
// RRB-type instr
state <= 5'd7;
end else
if (type_j) begin
// J-type instr
state <= 5'd9;
end else
if (type_jr) begin
// JR-type instr
state <= 5'd10;
end else
if (type_ldst) begin
// LDST-type instr
state <= 5'd11;
end else
if (type_mvfs) begin
// mvfs instr
state <= 5'd21;
end else
if (type_mvts) begin
// mvts instr
if (psw[26] == 1) begin
state <= 5'd25;
exc_priority <= 4'd2;
end else begin
state <= 5'd22;
end
end else
if (type_rfx) begin
// rfx instr
if (psw[26] == 1) begin
state <= 5'd25;
exc_priority <= 4'd2;
end else begin
state <= 5'd23;
end
end else
if (type_trap) begin
// trap instr
state <= 5'd25;
exc_priority <= 4'd4;
end else
if (type_tb) begin
// TLB instr
if (psw[26] == 1) begin
state <= 5'd25;
exc_priority <= 4'd2;
end else begin
state <= 5'd27;
end
end else begin
// illegal instruction
state <= 5'd25;
exc_priority <= 4'd1;
end
end
5'd3: // execute RRR-type instr
begin
if (type_muldiv) begin
state <= 5'd18;
end else
if (type_shift) begin
state <= 5'd16;
end else begin
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end
end
5'd4: // execute RRS-type instr
begin
if (type_muldiv) begin
state <= 5'd19;
end else begin
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end
end
5'd5: // execute RRH-type instr
begin
if (type_muldiv) begin
state <= 5'd20;
end else
if (type_shift) begin
state <= 5'd17;
end else begin
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end
end
5'd6: // execute RHH-type instr
begin
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end
5'd7: // execute RRB-type instr (1)
begin
if (branch) begin
state <= 5'd8;
end else begin
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end
end
5'd8: // execute RRB-type instr (2)
begin
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end
5'd9: // execute J-type instr
begin
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end
5'd10: // execute JR-type instr
begin
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end
5'd11: // execute LDST-type instr (1)
begin
if (type_ld) begin
state <= 5'd12;
end else begin
state <= 5'd14;
end
end
5'd12: // execute LD-type instr (addr xlat)
begin
if (exc_prv_addr) begin
state <= 25;
exc_priority <= 4'd9;
end else
if (exc_ill_addr) begin
state <= 25;
exc_priority <= 4'd8;
end else begin
state <= 5'd29;
end
end
5'd13: // execute LD-type instr (3)
begin
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end
5'd14: // execute ST-type instr (addr xlat)
begin
if (exc_prv_addr) begin
state <= 25;
exc_priority <= 4'd9;
end else
if (exc_ill_addr) begin
state <= 25;
exc_priority <= 4'd8;
end else begin
state <= 5'd30;
end
end
5'd15: // interrupt
begin
state <= 5'd1;
end
5'd16: // extra state for RRR shift instr
begin
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end
5'd17: // extra state for RRH shift instr
begin
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end
5'd18: // extra state for RRR muldiv instr
begin
if (muldiv_done) begin
if (muldiv_error) begin
state <= 5'd25;
exc_priority <= 4'd3;
end else
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end else begin
state <= 5'd18;
end
end
5'd19: // extra state for RRS muldiv instr
begin
if (muldiv_done) begin
if (muldiv_error) begin
state <= 5'd25;
exc_priority <= 4'd3;
end else
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end else begin
state <= 5'd19;
end
end
5'd20: // extra state for RRH muldiv instr
begin
if (muldiv_done) begin
if (muldiv_error) begin
state <= 5'd25;
exc_priority <= 4'd3;
end else
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end else begin
state <= 5'd20;
end
end
5'd21: // execute mvfs instr
begin
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end
5'd22: // execute mvts instr
begin
state <= 5'd24;
end
5'd23: // execute rfx instr
begin
state <= 5'd24;
end
5'd24: // irq_trigger check for mvts and rfx
begin
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end
5'd25: // exception (locus is PC-4)
begin
state <= 5'd1;
end
5'd26: // exception (locus is PC)
begin
state <= 5'd1;
end
5'd27: // execute TLB instr
begin
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end
5'd28: // fetch instr (bus cycle)
begin
if (tlb_kmissed == 1 || tlb_umissed == 1) begin
state <= 5'd26;
exc_priority <= 4'd5;
end else
if (tlb_invalid == 1) begin
state <= 5'd26;
exc_priority <= 4'd7;
end else
if (bus_wt == 1) begin
if (bus_timeout == 1) begin
state <= 5'd26;
exc_priority <= 4'd0;
end else begin
state <= 5'd28;
end
end else begin
state <= 5'd2;
end
end
5'd29: // execute LD-type instr (bus cycle)
begin
if (tlb_kmissed == 1 || tlb_umissed == 1) begin
state <= 5'd25;
exc_priority <= 4'd5;
end else
if (tlb_invalid == 1) begin
state <= 5'd25;
exc_priority <= 4'd7;
end else
if (bus_wt == 1) begin
if (bus_timeout == 1) begin
state <= 5'd25;
exc_priority <= 4'd0;
end else begin
state <= 5'd29;
end
end else begin
state <= 5'd13;
end
end
5'd30: // execute ST-type instr (bus cycle)
begin
if (tlb_kmissed == 1 || tlb_umissed == 1) begin
state <= 5'd25;
exc_priority <= 4'd5;
end else
if (tlb_invalid == 1) begin
state <= 5'd25;
exc_priority <= 4'd7;
end else
if (tlb_wrtprot == 1) begin
state <= 5'd25;
exc_priority <= 4'd6;
end else
if (bus_wt == 1) begin
if (bus_timeout == 1) begin
state <= 5'd25;
exc_priority <= 4'd0;
end else begin
state <= 5'd30;
end
end else begin
if (irq_trigger) begin
state <= 5'd15;
end else begin
state <= 5'd1;
end
end
end
default: // all other states: unused
begin
state <= 5'd0;
end
endcase
end
end
// bus timeout detector
assign bus_timeout = (bus_count == 8'h00) ? 1 : 0;
always @(posedge clk) begin
if (bus_en == 1 && bus_wt == 1) begin
// bus is waiting
bus_count <= bus_count - 1;
end else begin
// bus is not waiting
bus_count <= 8'hFF;
end
end
// output logic
always @(*) begin
case (state)
5'd0: // reset
begin
pc_src = 3'b001;
pc_we = 1'b1;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'bxx;
reg_di2_src = 3'bxxx;
reg_we2 = 1'b0;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd1: // fetch instr (addr xlat)
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'b0;
mmu_fnc = (exc_prv_addr | exc_ill_addr) ? 3'b000 : 3'b001;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'b10; // enable illegal address detection
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'bxx;
reg_di2_src = 3'bxxx;
reg_we2 = 1'b0;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = exc_prv_addr | exc_ill_addr;
end
5'd2: // decode instr
// increment pc by 4
// possibly store pc+4 in $31
begin
pc_src = 3'b000;
pc_we = 1'b1;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = (type_link == 1) ? 2'b10 :
(type_rfx == 1) ? 2'b11 :
2'b00;
reg_di2_src = (type_link == 1) ? 3'b000 : 3'bxxx;
reg_we2 = (type_link == 1) ? 1'b1 : 1'b0;
alu_src1 = 1'b0;
alu_src2 = 3'b000;
alu_fnc = 3'b000;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd3: // execute RRR-type instr
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'b01;
reg_di2_src = 3'b000;
reg_we2 = type_fast;
alu_src1 = 1'b1;
alu_src2 = 3'b001;
alu_fnc = { opcode[4], opcode[2], opcode[1] };
shift_fnc = { opcode[2], opcode[1] };
muldiv_fnc = { opcode[3], opcode[2], opcode[1] };
muldiv_start = type_muldiv;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd4: // execute RRS-type instr
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'b00;
reg_di2_src = 3'b000;
reg_we2 = type_fast;
alu_src1 = 1'b1;
alu_src2 = 3'b010;
alu_fnc = { opcode[4], opcode[2], opcode[1] };
shift_fnc = 2'bxx;
muldiv_fnc = { opcode[3], opcode[2], opcode[1] };
muldiv_start = type_muldiv;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd5: // execute RRH-type instr
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'b00;
reg_di2_src = 3'b000;
reg_we2 = type_fast;
alu_src1 = 1'b1;
alu_src2 = 3'b011;
alu_fnc = { opcode[4], opcode[2], opcode[1] };
shift_fnc = { opcode[2], opcode[1] };
muldiv_fnc = { opcode[3], opcode[2], opcode[1] };
muldiv_start = type_muldiv;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd6: // execute RHH-type instr
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'b00;
reg_di2_src = 3'b000;
reg_we2 = 1'b1;
alu_src1 = 1'bx;
alu_src2 = 3'b100;
alu_fnc = 3'b011;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd7: // execute RRB-type instr (1)
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'bxx;
reg_di2_src = 3'bxxx;
reg_we2 = 1'b0;
alu_src1 = 1'b1;
alu_src2 = 3'b001;
alu_fnc = 3'b001;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd8: // execute RRB-type instr (2)
begin
pc_src = 3'b000;
pc_we = 1'b1;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'bxx;
reg_di2_src = 3'bxxx;
reg_we2 = 1'b0;
alu_src1 = 1'b0;
alu_src2 = 3'b101;
alu_fnc = 3'b000;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd9: // execute J-type instr
begin
pc_src = 3'b000;
pc_we = 1'b1;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'bxx;
reg_di2_src = 3'bxxx;
reg_we2 = 1'b0;
alu_src1 = 1'b0;
alu_src2 = 3'b110;
alu_fnc = 3'b000;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd10: // execute JR-type instr
begin
pc_src = 3'b000;
pc_we = 1'b1;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'bxx;
reg_di2_src = 3'bxxx;
reg_we2 = 1'b0;
alu_src1 = 1'b1;
alu_src2 = 3'bxxx;
alu_fnc = 3'b010;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd11: // execute LDST-type instr (1)
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b1;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b1;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'bxx;
reg_di2_src = 3'bxxx;
reg_we2 = 1'b0;
alu_src1 = 1'b1;
alu_src2 = 3'b010;
alu_fnc = 3'b000;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd12: // execute LD-type instr (addr xlat)
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'b1;
mmu_fnc = (exc_prv_addr | exc_ill_addr) ? 3'b000 : 3'b001;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = ldst_size; // enable illegal address detection
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'bxx;
reg_di2_src = 3'bxxx;
reg_we2 = 1'b0;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = exc_prv_addr | exc_ill_addr;
end
5'd13: // execute LD-type instr (3)
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = ldst_size;
mdir_we = 1'b0;
mdir_sx = opcode[0];
ir_we = 1'b0;
reg_src2 = 2'b00;
reg_di2_src = 3'b011;
reg_we2 = 1'b1;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd14: // execute ST-type instr (addr xlat)
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'b1;
mmu_fnc = (exc_prv_addr | exc_ill_addr) ? 3'b000 : 3'b001;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = ldst_size; // enable illegal address detection
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'bxx;
reg_di2_src = 3'bxxx;
reg_we2 = 1'b0;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = exc_prv_addr | exc_ill_addr;
end
5'd15: // interrupt
begin
pc_src = (psw[27] == 0) ? 3'b010 : 3'b011;
pc_we = 1'b1;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'b11;
reg_di2_src = 3'b000;
reg_we2 = 1'b1;
alu_src1 = 1'b0;
alu_src2 = 3'bxxx;
alu_fnc = 3'b010;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b1;
psw_new = {
psw[31:28],
psw[27],
1'b0, psw[26], psw[25],
1'b0, psw[23], psw[22],
1'b0, irq_priority,
psw[15:0]
};
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd16: // extra state for RRR shift instr
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'b01;
reg_di2_src = 3'b001;
reg_we2 = 1'b1;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd17: // extra state for RRH shift instr
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'b00;
reg_di2_src = 3'b001;
reg_we2 = 1'b1;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd18: // extra state for RRR muldiv instr
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'b01;
reg_di2_src = 3'b010;
reg_we2 = muldiv_done & ~muldiv_error;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd19: // extra state for RRS muldiv instr
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'b00;
reg_di2_src = 3'b010;
reg_we2 = muldiv_done & ~muldiv_error;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd20: // extra state for RRH muldiv instr
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'b00;
reg_di2_src = 3'b010;
reg_we2 = muldiv_done & ~muldiv_error;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd21: // execute mvfs instr
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'b00;
reg_di2_src = 3'b100;
reg_we2 = 1'b1;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd22: // execute mvts instr
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'bxx;
reg_di2_src = 3'bxxx;
reg_we2 = 1'b0;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b1;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd23: // execute rfx instr
begin
pc_src = 3'b000;
pc_we = 1'b1;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'bxx;
reg_di2_src = 3'bxxx;
reg_we2 = 1'b0;
alu_src1 = 1'bx;
alu_src2 = 3'b001;
alu_fnc = 3'b011;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b1;
psw_new = {
psw[31:28],
psw[27],
psw[25], psw[24], psw[24],
psw[22], psw[21], psw[21],
psw[20:16],
psw[15:0]
};
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd24: // irq_trigger check for mvts and rfx
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'bxx;
reg_di2_src = 3'bxxx;
reg_we2 = 1'b0;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd25: // exception (locus is PC-4)
begin
pc_src = (psw[27] != 0) ?
((tlb_umissed != 0) ? 3'b101 : 3'b011) :
((tlb_umissed != 0) ? 3'b100 : 3'b010);
pc_we = 1'b1;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'b11;
reg_di2_src = 3'b000;
reg_we2 = 1'b1;
alu_src1 = 1'b0;
alu_src2 = 3'b000;
alu_fnc = 3'b001;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b1;
psw_new = {
psw[31:28],
psw[27],
1'b0, psw[26], psw[25],
1'b0, psw[23], psw[22],
1'b1, exc_priority,
psw[15:0]
};
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd26: // exception (locus is PC)
begin
pc_src = (psw[27] != 0) ?
((tlb_umissed != 0) ? 3'b101 : 3'b011) :
((tlb_umissed != 0) ? 3'b100 : 3'b010);
pc_we = 1'b1;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'b11;
reg_di2_src = 3'b000;
reg_we2 = 1'b1;
alu_src1 = 1'b0;
alu_src2 = 3'bxxx;
alu_fnc = 3'b010;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b1;
psw_new = {
psw[31:28],
psw[27],
1'b0, psw[26], psw[25],
1'b0, psw[23], psw[22],
1'b1, exc_priority,
psw[15:0]
};
tlb_index_we = 1'b0;
tlb_entry_hi_we = 1'b0;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = 1'b0;
end
5'd27: // execute TLB instr
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'bx;
mmu_fnc = opcode[2:0];
mdor_we = 1'b0;
bus_en = 1'b0;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'bxx;
reg_di2_src = 3'bxxx;
reg_we2 = 1'b0;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = (opcode[2:0] == 3'b010) ? 1 : 0;
tlb_entry_hi_we = (opcode[2:0] == 3'b100) ? 1 : 0;
tlb_entry_lo_we = (opcode[2:0] == 3'b100) ? 1 : 0;
mmu_bad_addr_we = 1'b0;
end
5'd28: // fetch instr (bus cycle)
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'b0; // hold vaddr for latching in bad addr reg
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = ~exc_tlb_but_wrtprot;
bus_wr = 1'b0;
bus_size = 2'b10;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b1;
reg_src2 = 2'bxx;
reg_di2_src = 3'bxxx;
reg_we2 = 1'b0;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = exc_tlb_but_wrtprot;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = exc_tlb_but_wrtprot;
end
5'd29: // execute LD-type instr (bus cycle)
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'b1; // hold vaddr for latching in bad addr reg
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = ~exc_tlb_but_wrtprot;
bus_wr = 1'b0;
bus_size = ldst_size;
mdir_we = 1'b1;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'bxx;
reg_di2_src = 3'bxxx;
reg_we2 = 1'b0;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = exc_tlb_but_wrtprot;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = exc_tlb_but_wrtprot;
end
5'd30: // execute ST-type instr (bus cycle)
begin
pc_src = 3'bxxx;
pc_we = 1'b0;
mar_we = 1'b0;
ma_src = 1'b1; // hold vaddr for latching in bad addr reg
mmu_fnc = 3'b000;
mdor_we = 1'b0;
bus_en = ~exc_tlb_any;
bus_wr = 1'b1;
bus_size = ldst_size;
mdir_we = 1'b0;
mdir_sx = 1'bx;
ir_we = 1'b0;
reg_src2 = 2'bxx;
reg_di2_src = 3'bxxx;
reg_we2 = 1'b0;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'b0;
sreg_we = 1'b0;
psw_we = 1'b0;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'b0;
tlb_entry_hi_we = exc_tlb_any;
tlb_entry_lo_we = 1'b0;
mmu_bad_addr_we = exc_tlb_any;
end
default: // all other states: unused
begin
pc_src = 3'bxxx;
pc_we = 1'bx;
mar_we = 1'bx;
ma_src = 1'bx;
mmu_fnc = 3'bxxx;
mdor_we = 1'bx;
bus_en = 1'bx;
bus_wr = 1'bx;
bus_size = 2'bxx;
mdir_we = 1'bx;
mdir_sx = 1'bx;
ir_we = 1'bx;
reg_src2 = 2'bxx;
reg_di2_src = 3'bxxx;
reg_we2 = 1'bx;
alu_src1 = 1'bx;
alu_src2 = 3'bxxx;
alu_fnc = 3'bxxx;
shift_fnc = 2'bxx;
muldiv_fnc = 3'bxxx;
muldiv_start = 1'bx;
sreg_we = 1'bx;
psw_we = 1'bx;
psw_new = 32'hxxxxxxxx;
tlb_index_we = 1'bx;
tlb_entry_hi_we = 1'bx;
tlb_entry_lo_we = 1'bx;
mmu_bad_addr_we = 1'bx;
end
endcase
end
// branch logic
always @(*) begin
casex ( { opcode[3:0], alu_equ, alu_ult, alu_slt } )
// eq
7'b00000xx: branch = 0;
7'b00001xx: branch = 1;
// ne
7'b00010xx: branch = 1;
7'b00011xx: branch = 0;
// le
7'b00100x0: branch = 0;
7'b00101xx: branch = 1;
7'b0010xx1: branch = 1;
// leu
7'b001100x: branch = 0;
7'b00111xx: branch = 1;
7'b0011x1x: branch = 1;
// lt
7'b0100xx0: branch = 0;
7'b0100xx1: branch = 1;
// ltu
7'b0101x0x: branch = 0;
7'b0101x1x: branch = 1;
// ge
7'b0110xx0: branch = 1;
7'b0110xx1: branch = 0;
// geu
7'b0111x0x: branch = 1;
7'b0111x1x: branch = 0;
// gt
7'b10000x0: branch = 1;
7'b10001xx: branch = 0;
7'b1000xx1: branch = 0;
// gtu
7'b100100x: branch = 1;
7'b10011xx: branch = 0;
7'b1001x1x: branch = 0;
// other
default: branch = 1'bx;
endcase
end
// interrupts
assign irq_pending = irq[15:0] & psw[15:0];
assign irq_trigger = (| irq_pending) & psw[23];
always @(*) begin
if ((| irq_pending[15:8]) != 0) begin
if ((| irq_pending[15:12]) != 0) begin
if ((| irq_pending[15:14]) != 0) begin
if (irq_pending[15] != 0) begin
irq_priority = 4'd15;
end else begin
irq_priority = 4'd14;
end
end else begin
if (irq_pending[13] != 0) begin
irq_priority = 4'd13;
end else begin
irq_priority = 4'd12;
end
end
end else begin
if ((| irq_pending[11:10]) != 0) begin
if (irq_pending[11] != 0) begin
irq_priority = 4'd11;
end else begin
irq_priority = 4'd10;
end
end else begin
if (irq_pending[9] != 0) begin
irq_priority = 4'd9;
end else begin
irq_priority = 4'd8;
end
end
end
end else begin
if ((| irq_pending[7:4]) != 0) begin
if ((| irq_pending[7:6]) != 0) begin
if (irq_pending[7] != 0) begin
irq_priority = 4'd7;
end else begin
irq_priority = 4'd6;
end
end else begin
if (irq_pending[5] != 0) begin
irq_priority = 4'd5;
end else begin
irq_priority = 4'd4;
end
end
end else begin
if ((| irq_pending[3:2]) != 0) begin
if (irq_pending[3] != 0) begin
irq_priority = 4'd3;
end else begin
irq_priority = 4'd2;
end
end else begin
if (irq_pending[1] != 0) begin
irq_priority = 4'd1;
end else begin
irq_priority = 4'd0;
end
end
end
end
end
// exceptions
assign exc_prv_addr = psw[26] & va_31;
assign exc_ill_addr = (bus_size[0] & va_0) |
(bus_size[1] & va_0) |
(bus_size[1] & va_1);
assign exc_tlb_but_wrtprot = tlb_kmissed | tlb_umissed | tlb_invalid;
assign exc_tlb_any = exc_tlb_but_wrtprot | tlb_wrtprot;
endmodule
//--------------------------------------------------------------
// pc -- the program counter
//--------------------------------------------------------------
module pc(clk, pc_we, pc_next, pc);
input clk;
input pc_we;
input [31:0] pc_next;
output reg [31:0] pc;
always @(posedge clk) begin
if (pc_we == 1) begin
pc <= pc_next;
end
end
endmodule
//--------------------------------------------------------------
// mar -- the memory address register
//--------------------------------------------------------------
module mar(clk, mar_we, mar_next, mar);
input clk;
input mar_we;
input [31:0] mar_next;
output reg [31:0] mar;
always @(posedge clk) begin
if (mar_we == 1) begin
mar <= mar_next;
end
end
endmodule
//--------------------------------------------------------------
// mdor -- the memory data out register
//--------------------------------------------------------------
module mdor(clk, mdor_we, mdor_next, mdor);
input clk;
input mdor_we;
input [31:0] mdor_next;
output reg [31:0] mdor;
always @(posedge clk) begin
if (mdor_we == 1) begin
mdor <= mdor_next;
end
end
endmodule
//--------------------------------------------------------------
// mdir -- the memory data in register
//--------------------------------------------------------------
module mdir(clk, mdir_we, mdir_next, size, sx, mdir);
input clk;
input mdir_we;
input [31:0] mdir_next;
input [1:0] size;
input sx;
output reg [31:0] mdir;
reg [31:0] data;
always @(posedge clk) begin
if (mdir_we == 1) begin
data <= mdir_next;
end
end
always @(*) begin
case ({ size, sx })
3'b000:
begin
mdir[31:0] = { 24'h000000, data[7:0] };
end
3'b001:
begin
if (data[7] == 1) begin
mdir[31:0] = { 24'hFFFFFF, data[7:0] };
end else begin
mdir[31:0] = { 24'h000000, data[7:0] };
end
end
3'b010:
begin
mdir[31:0] = { 16'h0000, data[15:0] };
end
3'b011:
begin
if (data[15] == 1) begin
mdir[31:0] = { 16'hFFFF, data[15:0] };
end else begin
mdir[31:0] = { 16'h0000, data[15:0] };
end
end
default:
begin
mdir[31:0] = data[31:0];
end
endcase
end
endmodule
//--------------------------------------------------------------
// ir -- the instruction register and decoder
//--------------------------------------------------------------
module ir(clk,
ir_we, instr,
opcode, reg1, reg2, reg3,
sx16, zx16, hi16, sx16s2, sx26s2);
input clk;
input ir_we;
input [31:0] instr;
output [5:0] opcode;
output [4:0] reg1;
output [4:0] reg2;
output [4:0] reg3;
output [31:0] sx16;
output [31:0] zx16;
output [31:0] hi16;
output [31:0] sx16s2;
output [31:0] sx26s2;
reg [31:0] ir;
wire [15:0] copy_sign_16; // 16-bit copy of a 16-bit immediate's sign
wire [3:0] copy_sign_26; // 4-bit copy of a 26-bit immediate's sign
always @(posedge clk) begin
if (ir_we) begin
ir <= instr;
end
end
assign opcode[5:0] = ir[31:26];
assign reg1[4:0] = ir[25:21];
assign reg2[4:0] = ir[20:16];
assign reg3[4:0] = ir[15:11];
assign copy_sign_16[15:0] = (ir[15] == 1) ? 16'hFFFF : 16'h0000;
assign copy_sign_26[3:0] = (ir[25] == 1) ? 4'hF : 4'h0;
assign sx16[31:0] = { copy_sign_16[15:0], ir[15:0] };
assign zx16[31:0] = { 16'h0000, ir[15:0] };
assign hi16[31:0] = { ir[15:0], 16'h0000 };
assign sx16s2[31:0] = { copy_sign_16[13:0], ir[15:0], 2'b00 };
assign sx26s2[31:0] = { copy_sign_26[3:0], ir[25:0], 2'b00 };
endmodule
//--------------------------------------------------------------
// regs -- the register file
//--------------------------------------------------------------
module regs(clk,
rn1, do1,
rn2, do2, we2, di2);
input clk;
input [4:0] rn1;
output reg [31:0] do1;
input [4:0] rn2;
output reg [31:0] do2;
input we2;
input [31:0] di2;
reg [31:0] r[0:31];
always @(posedge clk) begin
do1 <= r[rn1];
if (we2 == 0) begin
do2 <= r[rn2];
end else begin
do2 <= di2;
r[rn2] <= di2;
end
end
endmodule
//--------------------------------------------------------------
// alu -- the arithmetic/logic unit
//--------------------------------------------------------------
module alu(a, b, fnc,
res, equ, ult, slt);
input [31:0] a;
input [31:0] b;
input [2:0] fnc;
output [31:0] res;
output equ;
output ult;
output slt;
wire [32:0] a1;
wire [32:0] b1;
reg [32:0] res1;
assign a1 = { 1'b0, a };
assign b1 = { 1'b0, b };
always @(*) begin
case (fnc)
3'b000: res1 = a1 + b1;
3'b001: res1 = a1 - b1;
3'b010: res1 = a1;
3'b011: res1 = b1;
3'b100: res1 = a1 & b1;
3'b101: res1 = a1 | b1;
3'b110: res1 = a1 ^ b1;
3'b111: res1 = a1 ~^ b1;
default: res1 = 33'hxxxxxxxx;
endcase
end
assign res = res1[31:0];
assign equ = ~| res1[31:0];
assign ult = res1[32];
assign slt = res1[32] ^ a[31] ^ b[31];
endmodule
//--------------------------------------------------------------
// shift -- the shift unit
//--------------------------------------------------------------
module shift(clk, data_in, shamt, fnc, data_out);
input clk;
input [31:0] data_in;
input [4:0] shamt;
input [1:0] fnc;
output reg [31:0] data_out;
always @(posedge clk) begin
if (fnc == 2'b00) begin
// sll
data_out <= data_in << shamt;
end else
if (fnc == 2'b01) begin
// slr
data_out <= data_in >> shamt;
end else
if (fnc == 2'b10) begin
// sar
if (data_in[31] == 1) begin
data_out <= ~(32'hFFFFFFFF >> shamt) |
(data_in >> shamt);
end else begin
data_out <= data_in >> shamt;
end
end else begin
data_out <= 32'hxxxxxxxx;
end
end
endmodule
//--------------------------------------------------------------
// muldiv -- the multiplier/divide unit
//--------------------------------------------------------------
module muldiv(clk, a, b, fnc, start, done, error, res);
input clk;
input [31:0] a;
input [31:0] b;
input [2:0] fnc;
input start;
output reg done;
output reg error;
output reg [31:0] res;
// fnc = 000 op = undefined
// 001 undefined
// 010 mul
// 011 mulu
// 100 div
// 101 divu
// 110 rem
// 111 remu
reg div;
reg rem;
reg [5:0] count;
reg a_neg;
reg b_neg;
reg [31:0] b_abs;
reg [64:0] q;
wire [64:1] s;
wire [64:0] d;
assign s[64:32] = q[64:32] + { 1'b0, b_abs };
assign s[31: 1] = q[31: 1];
assign d[64:32] = q[64:32] - { 1'b0, b_abs };
assign d[31: 0] = q[31: 0];
always @(posedge clk) begin
if (start == 1) begin
if (fnc[2] == 1 && (| b[31:0]) == 0) begin
// division by zero
done <= 1;
error <= 1;
end else begin
// operands are ok
done <= 0;
error <= 0;
end
div <= fnc[2];
rem <= fnc[1];
count <= 6'd0;
if (fnc[0] == 0 && a[31] == 1) begin
// negate first operand
a_neg <= 1;
if (fnc[2] == 0) begin
// initialize q for multiplication
q[64:32] <= 33'b0;
q[31: 0] <= ~a + 1;
end else begin
// initialize q for division and remainder
q[64:33] <= 32'b0;
q[32: 1] <= ~a + 1;
q[ 0: 0] <= 1'b0;
end
end else begin
// use first operand as is
a_neg <= 0;
if (fnc[2] == 0) begin
// initialize q for multiplication
q[64:32] <= 33'b0;
q[31: 0] <= a;
end else begin
// initialize q for division and remainder
q[64:33] <= 32'b0;
q[32: 1] <= a;
q[ 0: 0] <= 1'b0;
end
end
if (fnc[0] == 0 && b[31] == 1) begin
// negate second operand
b_neg <= 1;
b_abs <= ~b + 1;
end else begin
// use second operand as is
b_neg <= 0;
b_abs <= b;
end
end else begin
if (done == 0) begin
// algorithm not yet finished
if (div == 0) begin
//
// multiplication
//
if (count == 6'd32) begin
// last step
done <= 1;
if (a_neg == b_neg) begin
res <= q[31:0];
end else begin
res <= ~q[31:0] + 1;
end
end else begin
// all other steps
count <= count + 1;
if (q[0] == 1) begin
q <= { 1'b0, s[64:1] };
end else begin
q <= { 1'b0, q[64:1] };
end
end
end else begin
//
// division and remainder
//
if (count == 6'd32) begin
// last step
done <= 1;
if (rem == 0) begin
// result <= quotient
if (a_neg == b_neg) begin
res <= q[31:0];
end else begin
res <= ~q[31:0] + 1;
end
end else begin
// result <= remainder
if (a_neg == 0) begin
res <= q[64:33];
end else begin
res <= ~q[64:33] + 1;
end
end
end else begin
// all other steps
count <= count + 1;
if (d[64] == 0) begin
q <= { d[63:0], 1'b1 };
end else begin
q <= { q[63:0], 1'b0 };
end
end
end
end
end
end
endmodule
//--------------------------------------------------------------
// sregs -- the special registers
//--------------------------------------------------------------
module sregs(clk, reset,
rn, we, din, dout,
psw, psw_we, psw_new,
tlb_index, tlb_index_we, tlb_index_new,
tlb_entry_hi, tlb_entry_hi_we, tlb_entry_hi_new,
tlb_entry_lo, tlb_entry_lo_we, tlb_entry_lo_new,
mmu_bad_addr, mmu_bad_addr_we, mmu_bad_addr_new);
input clk;
input reset;
input [2:0] rn;
input we;
input [31:0] din;
output [31:0] dout;
output [31:0] psw;
input psw_we;
input [31:0] psw_new;
output [31:0] tlb_index;
input tlb_index_we;
input [31:0] tlb_index_new;
output [31:0] tlb_entry_hi;
input tlb_entry_hi_we;
input [31:0] tlb_entry_hi_new;
output [31:0] tlb_entry_lo;
input tlb_entry_lo_we;
input [31:0] tlb_entry_lo_new;
output [31:0] mmu_bad_addr;
input mmu_bad_addr_we;
input [31:0] mmu_bad_addr_new;
// rn = 000 register = PSW
// 001 TLB index
// 010 TLB entry high
// 011 TLB entry low
// 100 MMU bad address
// 101 - not used -
// 110 - not used -
// 111 - not used -
reg [31:0] sr[0:7];
assign dout = sr[rn];
assign psw = sr[0];
assign tlb_index = sr[1];
assign tlb_entry_hi = sr[2];
assign tlb_entry_lo = sr[3];
assign mmu_bad_addr = sr[4];
always @(posedge clk) begin
if (reset == 1) begin
sr[0] <= 32'h00000000;
end else begin
if (we == 1) begin
sr[rn] <= din;
end else begin
if (psw_we) begin
sr[0] <= psw_new;
end
if (tlb_index_we) begin
sr[1] <= tlb_index_new;
end
if (tlb_entry_hi_we) begin
sr[2] <= tlb_entry_hi_new;
end
if (tlb_entry_lo_we) begin
sr[3] <= tlb_entry_lo_new;
end
if (mmu_bad_addr_we) begin
sr[4] <= mmu_bad_addr_new;
end
end
end
end
endmodule
//--------------------------------------------------------------
// mmu -- the memory management unit
//--------------------------------------------------------------
module mmu(clk, reset, fnc, virt, phys,
tlb_index, tlb_index_new,
tlb_entry_hi, tlb_entry_hi_new,
tlb_entry_lo, tlb_entry_lo_new,
tlb_kmissed, tlb_umissed,
tlb_invalid, tlb_wrtprot);
input clk;
input reset;
input [2:0] fnc;
input [31:0] virt;
output [31:0] phys;
input [31:0] tlb_index;
output [31:0] tlb_index_new;
input [31:0] tlb_entry_hi;
output [31:0] tlb_entry_hi_new;
input [31:0] tlb_entry_lo;
output [31:0] tlb_entry_lo_new;
output tlb_kmissed;
output tlb_umissed;
output tlb_invalid;
output tlb_wrtprot;
// fnc = 000 no operation, hold output
// 001 map virt to phys address
// 010 tbs
// 011 tbwr
// 100 tbri
// 101 tbwi
// 110 undefined
// 111 undefined
wire map;
wire tbs;
wire tbwr;
wire tbri;
wire tbwi;
reg [19:0] page;
reg [11:0] offset;
wire [19:0] tlb_page;
wire tlb_miss;
wire [4:0] tlb_found;
wire tlb_enable;
wire [19:0] tlb_frame;
wire tlb_wbit;
wire tlb_vbit;
wire [4:0] rw_index;
wire [19:0] r_page;
wire [19:0] r_frame;
wire w_enable;
wire [19:0] w_page;
wire [19:0] w_frame;
wire direct;
wire [17:0] frame;
reg [4:0] random_index;
reg tlb_miss_delayed;
// decode function
assign map = (fnc == 3'b001) ? 1 : 0;
assign tbs = (fnc == 3'b010) ? 1 : 0;
assign tbwr = (fnc == 3'b011) ? 1 : 0;
assign tbri = (fnc == 3'b100) ? 1 : 0;
assign tbwi = (fnc == 3'b101) ? 1 : 0;
// latch virtual address
always @(posedge clk) begin
if (map == 1) begin
page <= virt[31:12];
offset <= virt[11:0];
end
end
// create tlb instance
assign tlb_page = (tbs == 1) ? tlb_entry_hi[31:12] : virt[31:12];
assign tlb_enable = map;
assign tlb_wbit = tlb_frame[1];
assign tlb_vbit = tlb_frame[0];
assign rw_index = (tbwr == 1) ? random_index : tlb_index[4:0];
assign tlb_index_new = { tlb_miss | tlb_index[31],
tlb_index[30:5], tlb_found };
assign tlb_entry_hi_new = { ((tbri == 1) ? r_page : page),
tlb_entry_hi[11:0] };
assign tlb_entry_lo_new = { tlb_entry_lo[31:30], r_frame[19:2],
tlb_entry_lo[11:2], r_frame[1:0] };
assign w_enable = tbwr | tbwi;
assign w_page = tlb_entry_hi[31:12];
assign w_frame = { tlb_entry_lo[29:12], tlb_entry_lo[1:0] };
tlb tlb1(tlb_page, tlb_miss, tlb_found,
clk, tlb_enable, tlb_frame,
rw_index, r_page, r_frame,
w_enable, w_page, w_frame);
// construct physical address
assign direct = (page[19:18] == 2'b11) ? 1 : 0;
assign frame = (direct == 1) ? page[17:0] : tlb_frame[19:2];
assign phys = { 2'b00, frame, offset };
// generate "random" index
always @(posedge clk) begin
if (reset == 1) begin
// the index register is counting down
// so we must start at topmost index
random_index <= 5'd31;
end else begin
// decrement index register "randomly"
// (whenever there is a mapping operation)
// skip "fixed" entries (0..3)
if (map == 1) begin
if (random_index == 5'd4) begin
random_index <= 5'd31;
end else begin
random_index <= random_index - 1;
end
end
end
end
// generate TLB exceptions
always @(posedge clk) begin
if (map == 1) begin
tlb_miss_delayed <= tlb_miss;
end
end
assign tlb_kmissed = tlb_miss_delayed & ~direct & page[19];
assign tlb_umissed = tlb_miss_delayed & ~direct & ~page[19];
assign tlb_invalid = ~tlb_vbit & ~direct;
assign tlb_wrtprot = ~tlb_wbit & ~direct;
endmodule
//--------------------------------------------------------------
// tlb -- the translation lookaside buffer
//--------------------------------------------------------------
module tlb(page_in, miss, found,
clk, enable, frame_out,
rw_index, r_page, r_frame,
w_enable, w_page, w_frame);
input [19:0] page_in;
output miss;
output [4:0] found;
input clk;
input enable;
output reg [19:0] frame_out;
input [4:0] rw_index;
output reg [19:0] r_page;
output reg [19:0] r_frame;
input w_enable;
input [19:0] w_page;
input [19:0] w_frame;
reg [19:0] page[0:31];
reg [19:0] frame[0:31];
wire [19:0] p00, p01, p02, p03;
wire [19:0] p04, p05, p06, p07;
wire [19:0] p08, p09, p10, p11;
wire [19:0] p12, p13, p14, p15;
wire [19:0] p16, p17, p18, p19;
wire [19:0] p20, p21, p22, p23;
wire [19:0] p24, p25, p26, p27;
wire [19:0] p28, p29, p30, p31;
wire [31:0] match;
assign p00 = page[ 0];
assign p01 = page[ 1];
assign p02 = page[ 2];
assign p03 = page[ 3];
assign p04 = page[ 4];
assign p05 = page[ 5];
assign p06 = page[ 6];
assign p07 = page[ 7];
assign p08 = page[ 8];
assign p09 = page[ 9];
assign p10 = page[10];
assign p11 = page[11];
assign p12 = page[12];
assign p13 = page[13];
assign p14 = page[14];
assign p15 = page[15];
assign p16 = page[16];
assign p17 = page[17];
assign p18 = page[18];
assign p19 = page[19];
assign p20 = page[20];
assign p21 = page[21];
assign p22 = page[22];
assign p23 = page[23];
assign p24 = page[24];
assign p25 = page[25];
assign p26 = page[26];
assign p27 = page[27];
assign p28 = page[28];
assign p29 = page[29];
assign p30 = page[30];
assign p31 = page[31];
assign match[ 0] = (page_in == p00) ? 1 : 0;
assign match[ 1] = (page_in == p01) ? 1 : 0;
assign match[ 2] = (page_in == p02) ? 1 : 0;
assign match[ 3] = (page_in == p03) ? 1 : 0;
assign match[ 4] = (page_in == p04) ? 1 : 0;
assign match[ 5] = (page_in == p05) ? 1 : 0;
assign match[ 6] = (page_in == p06) ? 1 : 0;
assign match[ 7] = (page_in == p07) ? 1 : 0;
assign match[ 8] = (page_in == p08) ? 1 : 0;
assign match[ 9] = (page_in == p09) ? 1 : 0;
assign match[10] = (page_in == p10) ? 1 : 0;
assign match[11] = (page_in == p11) ? 1 : 0;
assign match[12] = (page_in == p12) ? 1 : 0;
assign match[13] = (page_in == p13) ? 1 : 0;
assign match[14] = (page_in == p14) ? 1 : 0;
assign match[15] = (page_in == p15) ? 1 : 0;
assign match[16] = (page_in == p16) ? 1 : 0;
assign match[17] = (page_in == p17) ? 1 : 0;
assign match[18] = (page_in == p18) ? 1 : 0;
assign match[19] = (page_in == p19) ? 1 : 0;
assign match[20] = (page_in == p20) ? 1 : 0;
assign match[21] = (page_in == p21) ? 1 : 0;
assign match[22] = (page_in == p22) ? 1 : 0;
assign match[23] = (page_in == p23) ? 1 : 0;
assign match[24] = (page_in == p24) ? 1 : 0;
assign match[25] = (page_in == p25) ? 1 : 0;
assign match[26] = (page_in == p26) ? 1 : 0;
assign match[27] = (page_in == p27) ? 1 : 0;
assign match[28] = (page_in == p28) ? 1 : 0;
assign match[29] = (page_in == p29) ? 1 : 0;
assign match[30] = (page_in == p30) ? 1 : 0;
assign match[31] = (page_in == p31) ? 1 : 0;
assign miss = ~(| match[31:0]);
assign found[0] = match[ 1] | match[ 3] | match[ 5] | match[ 7] |
match[ 9] | match[11] | match[13] | match[15] |
match[17] | match[19] | match[21] | match[23] |
match[25] | match[27] | match[29] | match[31];
assign found[1] = match[ 2] | match[ 3] | match[ 6] | match[ 7] |
match[10] | match[11] | match[14] | match[15] |
match[18] | match[19] | match[22] | match[23] |
match[26] | match[27] | match[30] | match[31];
assign found[2] = match[ 4] | match[ 5] | match[ 6] | match[ 7] |
match[12] | match[13] | match[14] | match[15] |
match[20] | match[21] | match[22] | match[23] |
match[28] | match[29] | match[30] | match[31];
assign found[3] = match[ 8] | match[ 9] | match[10] | match[11] |
match[12] | match[13] | match[14] | match[15] |
match[24] | match[25] | match[26] | match[27] |
match[28] | match[29] | match[30] | match[31];
assign found[4] = match[16] | match[17] | match[18] | match[19] |
match[20] | match[21] | match[22] | match[23] |
match[24] | match[25] | match[26] | match[27] |
match[28] | match[29] | match[30] | match[31];
always @(posedge clk) begin
if (enable == 1) begin
frame_out <= frame[found];
end
end
always @(posedge clk) begin
if (w_enable == 1) begin
page[rw_index] <= w_page;
frame[rw_index] <= w_frame;
end else begin
r_page <= page[rw_index];
r_frame <= frame[rw_index];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND_BLACKBOX_V
`define SKY130_FD_SC_HD__TAPVGND_BLACKBOX_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tapvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BOI_M_V
`define SKY130_FD_SC_LP__A21BOI_M_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21boi_m (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21boi_m (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BOI_M_V
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_systeminit_dmg.v
// Version : v1.0
// Description: Rd/wr command generator
// various features/status of the core.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
`include "axi_traffic_gen_v2_0_defines.v"
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_systeminit_dmg
# (
parameter C_FAMILY = "virtex7" ,
parameter C_ATG_MIF_ADDR_BITS = 4 ,// 4(16),5(32),6(64),7(128),8(256)
parameter C_ATG_MIF_DATA_DEPTH = 16 ,// 4(16),5(32),6(64),7(128),8(256)
parameter C_ATG_MIF = "atg_init.mif"
) (
input [C_ATG_MIF_ADDR_BITS-1 : 0] a ,
input clk ,
input qspo_srst ,
output [31 : 0] qspo
);
//wire [31:0] rom_matrix[255:0] ;
//reg [31:0] qspo_i;
//assign rom_matrix[0] = {32'h81111111};
//assign rom_matrix[1] = {32'h82222222};
//assign rom_matrix[2] = {32'h73333333};
//assign rom_matrix[3] = {32'h84444444};
//assign rom_matrix[4] = {32'h85555555};
//assign rom_matrix[5] = {32'h86666666};
//assign rom_matrix[6] = {32'h87777777};
//assign rom_matrix[7] = {32'h88888888};
//assign rom_matrix[8] = {32'h89999999};
//assign rom_matrix[9] = {32'h80000000};
//assign rom_matrix[10] = {32'h8aaaaaaa};
//assign rom_matrix[11] = {32'h8bbbbbbb};
//assign rom_matrix[12] = {32'h8ccccccc};
//assign rom_matrix[13] = {32'h8ddddddd};
//assign rom_matrix[14] = {32'h0fffffff};
//assign rom_matrix[15] = {32'h8fffffff};
//assign rom_matrix[16] = {32'h23232323};
//assign rom_matrix[17] = {32'h11111111};
//assign rom_matrix[18] = {32'h22222222};
//assign rom_matrix[19] = {32'h33333333};
//assign rom_matrix[20] = {32'h44444444};
//assign rom_matrix[21] = {32'h55555555};
//assign rom_matrix[22] = {32'hffffffff};
//assign rom_matrix[23] = {32'h66666666};
//assign rom_matrix[24] = {32'h77777777};
//assign rom_matrix[25] = {32'h88888888};
//assign rom_matrix[26] = {32'h99999999};
//assign rom_matrix[27] = {32'haaaaaaaa};
//assign rom_matrix[28] = {32'hbbbbbbbb};
//assign rom_matrix[29] = {32'hcccccccc};
//assign rom_matrix[30] = {32'hdddddddd};
//assign rom_matrix[31] = {32'heeeeeeee};
//always @(posedge clk) begin
// if(qspo_srst == 1'b1) begin
// qspo_i <= 32'h0;
// end else begin
// qspo_i <= rom_matrix[a];
// end
//end
// assign qspo = qspo_i;
dist_mem_gen_v8_0 #(
.C_ADDR_WIDTH (C_ATG_MIF_ADDR_BITS ),
.C_DEFAULT_DATA ("0" ),
.C_DEPTH (C_ATG_MIF_DATA_DEPTH),
.C_FAMILY (C_FAMILY ),
.C_HAS_CLK (1 ),
.C_HAS_D (0 ),
.C_HAS_DPO (0 ),
.C_HAS_DPRA (0 ),
.C_HAS_I_CE (0 ),
.C_HAS_QDPO (0 ),
.C_HAS_QDPO_CE (0 ),
.C_HAS_QDPO_CLK (0 ),
.C_HAS_QDPO_RST (0 ),
.C_HAS_QDPO_SRST (0 ),
.C_HAS_QSPO (1 ),
.C_HAS_QSPO_CE (0 ),
.C_HAS_QSPO_RST (0 ),
.C_HAS_QSPO_SRST (1 ),
.C_HAS_SPO (0 ),
.C_HAS_WE (0 ),
.C_MEM_INIT_FILE (C_ATG_MIF ),
.C_MEM_TYPE (0 ),
.C_PARSER_TYPE (1 ),
.C_PIPELINE_STAGES(0 ),
.C_QCE_JOINED (0 ),
.C_QUALIFY_WE (0 ),
.C_READ_MIF (1 ),
.C_REG_A_D_INPUTS (0 ),
.C_REG_DPRA_INPUT (0 ),
.C_SYNC_ENABLE (1 ),
.C_WIDTH (32 )
)
inst (
.a (a ),
.clk (clk ),
.qspo_srst(qspo_srst ),
.qspo (qspo ),
//Default out/inputs
.d (32'h0 ),
.dpra ({C_ATG_MIF_ADDR_BITS{1'b0}}),
.we (1'b0 ),
.i_ce (1'b0 ),
.qspo_ce (1'b0 ),
.qdpo_ce (1'b0 ),
.qdpo_clk (1'b0 ),
.qspo_rst (1'b0 ),
.qdpo_rst (1'b0 ),
.qdpo_srst(1'b0 ),
.spo ( ),
.dpo ( ),
.qdpo ( )
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:30:32 05/09/2017
// Design Name: axi_spi_if
// Module Name: E:/University/AXI_SPI_IF/ise/axi_spi_test_registers.v
// Project Name: axi_spi_if
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: axi_spi_if
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module axi_spi_test_registers;
// Inputs
reg clk_i;
reg reset_n_i;
reg awvalid_i;
reg [27:0] awaddr_i;
reg awprot_i;
reg wvalid_i;
reg [31:0] wdata_i;
reg [3:0] wstrb_i;
reg bready_i;
reg arvalid_i;
reg [27:0] araddr_i;
reg [2:0] arprot_i;
reg rready_i;
reg spi_miso_i;
// Outputs
wire awready_o;
wire wready_o;
wire bvalid_o;
wire [1:0] bresp_o;
wire arready_o;
wire rvalid_o;
wire [31:0] rdata_o;
wire [1:0] rresp_o;
wire [3:0] spi_ssel_o;
wire spi_sck_o;
wire spi_mosi_o;
integer i;
// Instantiate the Unit Under Test (UUT)
axi_spi_if uut (
.clk_i(clk_i),
.reset_n_i(reset_n_i),
.awvalid_i(awvalid_i),
.awready_o(awready_o),
.awaddr_i(awaddr_i),
.awprot_i(awprot_i),
.wvalid_i(wvalid_i),
.wready_o(wready_o),
.wdata_i(wdata_i),
.wstrb_i(wstrb_i),
.bvalid_o(bvalid_o),
.bready_i(bready_i),
.bresp_o(bresp_o),
.arvalid_i(arvalid_i),
.arready_o(arready_o),
.araddr_i(araddr_i),
.arprot_i(arprot_i),
.rvalid_o(rvalid_o),
.rready_i(rready_i),
.rdata_o(rdata_o),
.rresp_o(rresp_o),
.spi_ssel_o(spi_ssel_o),
.spi_sck_o(spi_sck_o),
.spi_mosi_o(spi_mosi_o),
.spi_miso_i(spi_miso_i)
);
initial begin
// Initialize Inputs
clk_i = 0;
reset_n_i = 0;
awvalid_i = 0;
awaddr_i = 0;
awprot_i = 0;
wvalid_i = 0;
wdata_i = 0;
wstrb_i = 0;
bready_i = 0;
arvalid_i = 0;
araddr_i = 0;
arprot_i = 0;
rready_i = 0;
spi_miso_i = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset_n_i = 1;
spi_miso_i = 1;
bready_i = 1;
rready_i = 1;
/*
reg_control_i = 32'h0000_0602;
reg_trans_ctrl_i = 32'h0000_0002;
*/
// ===========================================
// WRITE CONTROL REGISTER
// ===========================================
wdata_i = 32'h0000_0602;
awaddr_i = 0;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
// ===========================================
// WRITE TRANSFER CONTROL REGISTER
// ===========================================
wdata_i = 32'h0000_0002;
awaddr_i = 1;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
// ===========================================
// WRITE STATUS REGISTER
// ===========================================
wdata_i = 32'h0000_0073;
awaddr_i = 2;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
// ===========================================
// WRITE TX FIFO
// ===========================================
for (i=0; i < 8; i = i + 1) begin
wdata_i = 32'd1 + i;
awaddr_i = 3;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
end
// ===========================================
// ACCESS ERROR TX
// ===========================================
for (i=8; i < 13; i = i + 1) begin
wdata_i = 32'd1 + i;
awaddr_i = 3;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
end
// ===========================================
// READ CONTROL REGISTER
// ===========================================
araddr_i = 0;
arvalid_i = 1;
wait(arready_o);
@(posedge clk_i) #1;
arvalid_i = 0;
#100;
// ===========================================
// READ TRANSFER CONTROL REGISTER
// ===========================================
araddr_i = 1;
arvalid_i = 1;
wait(arready_o);
@(posedge clk_i) #1;
arvalid_i = 0;
#100;
// ===========================================
// READ STATUS REGISTER
// ===========================================
araddr_i = 2;
arvalid_i = 1;
wait(arready_o);
@(posedge clk_i) #1;
arvalid_i = 0;
#100;
end
always #5 clk_i = ~clk_i;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:35:36 04/25/2015
// Design Name:
// Module Name: IR_fetch
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module IR_fetch(
input clock,
input PC_source,
input [11:0] PC_offset,
input [11:0] ISR_adr,
input branch_ISR,
input stall_d,
input stall_f,
input flush_d,
output reg [15:0] IR,
output reg [11:0] PC
);
wire [15:0] rom_data_out;
wire flush_decode;
assign flush_decode = flush_d || branch_ISR;
initial begin
IR = 0;
PC = 0;
flush_d_temp = 0;
end
ROM_4K instruction_rom (
.clka(clock), // input clka
.ena(~stall_d),
.addra(PC), // input [11 : 0] addra
.douta(rom_data_out) // output [15 : 0] douta
);
reg [11:0] nextOff;
reg [11:0] nextPC;
always @(*) begin
case (PC_source)
0: nextOff <= PC + 1;
1: nextOff <= PC + PC_offset;
endcase
case (branch_ISR)
0: nextPC <= nextOff;
1: nextPC <= ISR_adr;
endcase
end
reg flush_d_temp;
always @(posedge clock) begin
if (stall_f == 0) begin
PC = nextPC;
end
if (flush_decode == 1) begin
flush_d_temp <= 1;
end
else begin
flush_d_temp <= 0;
end
end
reg hiphop;
always @(rom_data_out ) begin // or flush_d_temp
if (stall_d == 0 && flush_d_temp == 0) begin
IR <= rom_data_out;
end
else if (flush_d_temp == 1) begin
IR <= 0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__AND4B_BEHAVIORAL_PP_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__and4b (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B, C, D );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4B_BEHAVIORAL_PP_V |
module pulse
#(parameter dly=3,
parameter len=2)
(input rstn,
input clk,
output reg pulse);
localparam width = $clog2(dly+len)+1;
reg [width-1:0] cnt;
always @(posedge clk or negedge rstn) begin
if (~rstn)
cnt <= 1'b0;
else if (cnt != dly+len)
cnt <= cnt + 1'b1;
end
always @(posedge clk or negedge rstn) begin
if (~rstn)
pulse <= 1'b0;
else if (cnt == dly)
pulse <= 1'b1;
else if (cnt == dly+len)
pulse <= 1'b0;
end
endmodule
module pulse_interclk
(input rstn,
input iclk,
input oclk,
input ipulse,
output opulse);
reg pulse0, pulse1, pulse2;
assign opulse = pulse1 & ~pulse2;
always @(posedge iclk or negedge rstn) begin
if (~rstn)
pulse0 <= 1'b0;
else if (ipulse)
pulse0 <= 1'b1;
end
always @(posedge oclk or negedge rstn) begin
if (~rstn) begin
pulse1 <= 1'b0;
pulse2 <= 1'b0;
end else begin
pulse1 <= pulse0;
pulse2 <= pulse1;
end
end
endmodule
module pulse_sim;
wire sys_clk;
sim_clk sysClk(sys_clk);
// ------------
reg rstn;
wire p[8:0];
initial rstn = 0;
initial #2 rstn = 1;
initial #65 rstn = 0;
pulse #(.dly(8), .len(0)) pulseI0(.rstn(rstn), .clk(sys_clk), .pulse(p[0]));
pulse #(.dly(8), .len(1)) pulseI1(.rstn(rstn), .clk(sys_clk), .pulse(p[1]));
pulse #(.dly(8), .len(1024)) pulseI2(.rstn(rstn), .clk(sys_clk), .pulse(p[2]));
pulse #(.dly(0), .len(1)) pulseI3(.rstn(rstn), .clk(sys_clk), .pulse(p[3]));
pulse #(.dly(1), .len(0)) pulseI4(.rstn(rstn), .clk(sys_clk), .pulse(p[4]));
pulse #(.dly(0), .len(0)) pulseI5(.rstn(rstn), .clk(sys_clk), .pulse(p[5]));
// ------------
wire slow_clk;
sim_clk #(.T(8)) slowClk(slow_clk);
wire fast_clk;
assign fast_clk = sys_clk;
wire pi[1:0];
reg po[1:0];
always @(posedge fast_clk, negedge rstn) begin
if (~rstn)
po[0] <= 1'b0;
else
po[0] <= 1'b1;
end
always @(posedge slow_clk, negedge rstn) begin
if (~rstn)
po[1] <= 1'b0;
else
po[1] <= 1'b1;
end
pulse_interclk pinterI0(.rstn(rstn), .iclk(fast_clk), .oclk(slow_clk), .ipulse(po[0]), .opulse(pi[0]));
pulse_interclk pinterI1(.rstn(rstn), .iclk(slow_clk), .oclk(fast_clk), .ipulse(po[1]), .opulse(pi[1]));
wire op;
reg op_flag;
always @(posedge fast_clk, negedge rstn) begin
if (~rstn)
op_flag <= 1'b0;
else if (~op_flag)
op_flag <= 1'b1;
else if (op)
op_flag <= 1'b0;
end
pulse_interclk pinterI2(.rstn(op_flag), .iclk(fast_clk), .oclk(fast_clk), .ipulse(1), .opulse(op));
// ------------
initial begin
$dumpfile(`VCD_PATH);
$dumpvars();
// $monitor("T=%t, clk=%d p[0]=%d p[1]=%d p[2]=%d p[3]=%d",
// $time, sys_clk,
// p[0],
// p[1],
// p[2],
// p[3])
#70 $finish;
end
endmodule
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// valid O 1
// addr O 64
// word64 O 64
// exc O 1
// exc_code O 4
// RDY_flush_server_request_put O 1 reg
// RDY_flush_server_response_get O 1 reg
// RDY_tlb_flush O 1 const
// ptw_client_request_get O 128 reg
// RDY_ptw_client_request_get O 1 reg
// RDY_ptw_client_response_put O 1 reg
// pte_writeback_g_get O 128 reg
// RDY_pte_writeback_g_get O 1 reg
// l1_to_l2_client_request_first O 69 reg
// RDY_l1_to_l2_client_request_first O 1 reg
// RDY_l1_to_l2_client_request_deq O 1 reg
// l1_to_l2_client_request_notEmpty O 1 reg
// RDY_l1_to_l2_client_request_notEmpty O 1 const
// RDY_l1_to_l2_client_response_enq O 1 reg
// l1_to_l2_client_response_notFull O 1 reg
// RDY_l1_to_l2_client_response_notFull O 1 const
// RDY_l2_to_l1_server_request_enq O 1 reg
// l2_to_l1_server_request_notFull O 1 reg
// RDY_l2_to_l1_server_request_notFull O 1 const
// l2_to_l1_server_response_first O 579 reg
// RDY_l2_to_l1_server_response_first O 1 reg
// RDY_l2_to_l1_server_response_deq O 1 reg
// l2_to_l1_server_response_notEmpty O 1 reg
// RDY_l2_to_l1_server_response_notEmpty O 1 const
// mmio_client_request_get O 131 reg
// RDY_mmio_client_request_get O 1 reg
// RDY_mmio_client_response_put O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// ma_req_va I 64
// ma_req_priv I 2
// ma_req_sstatus_SUM I 1
// ma_req_mstatus_MXR I 1
// ma_req_satp I 64
// flush_server_request_put I 1 reg
// ptw_client_response_put I 132 reg
// l1_to_l2_client_response_enq_x I 579 reg
// l2_to_l1_server_request_enq_x I 66 reg
// mmio_client_response_put I 65 reg
// EN_ma_req I 1
// EN_flush_server_request_put I 1
// EN_flush_server_response_get I 1
// EN_tlb_flush I 1
// EN_ptw_client_response_put I 1
// EN_l1_to_l2_client_request_deq I 1
// EN_l1_to_l2_client_response_enq I 1
// EN_l2_to_l1_server_request_enq I 1
// EN_l2_to_l1_server_response_deq I 1
// EN_mmio_client_response_put I 1
// EN_ptw_client_request_get I 1
// EN_pte_writeback_g_get I 1
// EN_mmio_client_request_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkI_MMU_Cache(CLK,
RST_N,
ma_req_va,
ma_req_priv,
ma_req_sstatus_SUM,
ma_req_mstatus_MXR,
ma_req_satp,
EN_ma_req,
valid,
addr,
word64,
exc,
exc_code,
flush_server_request_put,
EN_flush_server_request_put,
RDY_flush_server_request_put,
EN_flush_server_response_get,
RDY_flush_server_response_get,
EN_tlb_flush,
RDY_tlb_flush,
EN_ptw_client_request_get,
ptw_client_request_get,
RDY_ptw_client_request_get,
ptw_client_response_put,
EN_ptw_client_response_put,
RDY_ptw_client_response_put,
EN_pte_writeback_g_get,
pte_writeback_g_get,
RDY_pte_writeback_g_get,
l1_to_l2_client_request_first,
RDY_l1_to_l2_client_request_first,
EN_l1_to_l2_client_request_deq,
RDY_l1_to_l2_client_request_deq,
l1_to_l2_client_request_notEmpty,
RDY_l1_to_l2_client_request_notEmpty,
l1_to_l2_client_response_enq_x,
EN_l1_to_l2_client_response_enq,
RDY_l1_to_l2_client_response_enq,
l1_to_l2_client_response_notFull,
RDY_l1_to_l2_client_response_notFull,
l2_to_l1_server_request_enq_x,
EN_l2_to_l1_server_request_enq,
RDY_l2_to_l1_server_request_enq,
l2_to_l1_server_request_notFull,
RDY_l2_to_l1_server_request_notFull,
l2_to_l1_server_response_first,
RDY_l2_to_l1_server_response_first,
EN_l2_to_l1_server_response_deq,
RDY_l2_to_l1_server_response_deq,
l2_to_l1_server_response_notEmpty,
RDY_l2_to_l1_server_response_notEmpty,
EN_mmio_client_request_get,
mmio_client_request_get,
RDY_mmio_client_request_get,
mmio_client_response_put,
EN_mmio_client_response_put,
RDY_mmio_client_response_put);
input CLK;
input RST_N;
// action method ma_req
input [63 : 0] ma_req_va;
input [1 : 0] ma_req_priv;
input ma_req_sstatus_SUM;
input ma_req_mstatus_MXR;
input [63 : 0] ma_req_satp;
input EN_ma_req;
// value method valid
output valid;
// value method addr
output [63 : 0] addr;
// value method word64
output [63 : 0] word64;
// value method exc
output exc;
// value method exc_code
output [3 : 0] exc_code;
// action method flush_server_request_put
input flush_server_request_put;
input EN_flush_server_request_put;
output RDY_flush_server_request_put;
// action method flush_server_response_get
input EN_flush_server_response_get;
output RDY_flush_server_response_get;
// action method tlb_flush
input EN_tlb_flush;
output RDY_tlb_flush;
// actionvalue method ptw_client_request_get
input EN_ptw_client_request_get;
output [127 : 0] ptw_client_request_get;
output RDY_ptw_client_request_get;
// action method ptw_client_response_put
input [131 : 0] ptw_client_response_put;
input EN_ptw_client_response_put;
output RDY_ptw_client_response_put;
// actionvalue method pte_writeback_g_get
input EN_pte_writeback_g_get;
output [127 : 0] pte_writeback_g_get;
output RDY_pte_writeback_g_get;
// value method l1_to_l2_client_request_first
output [68 : 0] l1_to_l2_client_request_first;
output RDY_l1_to_l2_client_request_first;
// action method l1_to_l2_client_request_deq
input EN_l1_to_l2_client_request_deq;
output RDY_l1_to_l2_client_request_deq;
// value method l1_to_l2_client_request_notEmpty
output l1_to_l2_client_request_notEmpty;
output RDY_l1_to_l2_client_request_notEmpty;
// action method l1_to_l2_client_response_enq
input [578 : 0] l1_to_l2_client_response_enq_x;
input EN_l1_to_l2_client_response_enq;
output RDY_l1_to_l2_client_response_enq;
// value method l1_to_l2_client_response_notFull
output l1_to_l2_client_response_notFull;
output RDY_l1_to_l2_client_response_notFull;
// action method l2_to_l1_server_request_enq
input [65 : 0] l2_to_l1_server_request_enq_x;
input EN_l2_to_l1_server_request_enq;
output RDY_l2_to_l1_server_request_enq;
// value method l2_to_l1_server_request_notFull
output l2_to_l1_server_request_notFull;
output RDY_l2_to_l1_server_request_notFull;
// value method l2_to_l1_server_response_first
output [578 : 0] l2_to_l1_server_response_first;
output RDY_l2_to_l1_server_response_first;
// action method l2_to_l1_server_response_deq
input EN_l2_to_l1_server_response_deq;
output RDY_l2_to_l1_server_response_deq;
// value method l2_to_l1_server_response_notEmpty
output l2_to_l1_server_response_notEmpty;
output RDY_l2_to_l1_server_response_notEmpty;
// actionvalue method mmio_client_request_get
input EN_mmio_client_request_get;
output [130 : 0] mmio_client_request_get;
output RDY_mmio_client_request_get;
// action method mmio_client_response_put
input [64 : 0] mmio_client_response_put;
input EN_mmio_client_response_put;
output RDY_mmio_client_response_put;
// signals for module outputs
wire [578 : 0] l2_to_l1_server_response_first;
wire [130 : 0] mmio_client_request_get;
wire [127 : 0] pte_writeback_g_get, ptw_client_request_get;
wire [68 : 0] l1_to_l2_client_request_first;
wire [63 : 0] addr, word64;
wire [3 : 0] exc_code;
wire RDY_flush_server_request_put,
RDY_flush_server_response_get,
RDY_l1_to_l2_client_request_deq,
RDY_l1_to_l2_client_request_first,
RDY_l1_to_l2_client_request_notEmpty,
RDY_l1_to_l2_client_response_enq,
RDY_l1_to_l2_client_response_notFull,
RDY_l2_to_l1_server_request_enq,
RDY_l2_to_l1_server_request_notFull,
RDY_l2_to_l1_server_response_deq,
RDY_l2_to_l1_server_response_first,
RDY_l2_to_l1_server_response_notEmpty,
RDY_mmio_client_request_get,
RDY_mmio_client_response_put,
RDY_pte_writeback_g_get,
RDY_ptw_client_request_get,
RDY_ptw_client_response_put,
RDY_tlb_flush,
exc,
l1_to_l2_client_request_notEmpty,
l1_to_l2_client_response_notFull,
l2_to_l1_server_request_notFull,
l2_to_l1_server_response_notEmpty,
valid;
// inlined wires
reg [3 : 0] crg_exc_code$port0__write_1;
reg [2 : 0] crg_state$port0__write_1;
reg [1 : 0] crg_mmu_cache_req_state$port0__write_1;
reg crg_exc$port0__write_1;
wire [207 : 0] crg_mmu_cache_req$port1__write_1,
crg_mmu_cache_req$port2__read;
wire [63 : 0] crg_ld_val$port0__write_1, crg_ld_val$port1__read;
wire [3 : 0] crg_exc_code$port1__read;
wire [2 : 0] crg_state$port1__read;
wire [1 : 0] crg_mmu_cache_req_state$port1__read,
crg_mmu_cache_req_state$port1__write_1,
crg_mmu_cache_req_state$port2__read;
wire crg_exc$EN_port0__write,
crg_exc$port1__read,
crg_exc_code$EN_port0__write,
crg_ld_val$EN_port0__write,
crg_mmu_cache_req_state$EN_port0__write,
crg_state$EN_port0__write,
crg_valid$EN_port0__write,
crg_valid$port0__write_1,
crg_valid$port1__read,
crg_valid$port2__read;
// register crg_exc
reg crg_exc;
wire crg_exc$D_IN, crg_exc$EN;
// register crg_exc_code
reg [3 : 0] crg_exc_code;
wire [3 : 0] crg_exc_code$D_IN;
wire crg_exc_code$EN;
// register crg_ld_val
reg [63 : 0] crg_ld_val;
wire [63 : 0] crg_ld_val$D_IN;
wire crg_ld_val$EN;
// register crg_mmu_cache_req
reg [207 : 0] crg_mmu_cache_req;
wire [207 : 0] crg_mmu_cache_req$D_IN;
wire crg_mmu_cache_req$EN;
// register crg_mmu_cache_req_state
reg [1 : 0] crg_mmu_cache_req_state;
wire [1 : 0] crg_mmu_cache_req_state$D_IN;
wire crg_mmu_cache_req_state$EN;
// register crg_state
reg [2 : 0] crg_state;
wire [2 : 0] crg_state$D_IN;
wire crg_state$EN;
// register crg_valid
reg crg_valid;
wire crg_valid$D_IN, crg_valid$EN;
// ports of submodule cache
wire [578 : 0] cache$l1_to_l2_client_response_enq_x,
cache$l2_to_l1_server_response_first;
wire [207 : 0] cache$mav_request_pa_req;
wire [129 : 0] cache$mav_request_pa;
wire [68 : 0] cache$l1_to_l2_client_request_first;
wire [65 : 0] cache$l2_to_l1_server_request_enq_x;
wire [63 : 0] cache$ma_request_va_va, cache$mav_request_pa_pa;
wire cache$EN_flush_server_request_put,
cache$EN_flush_server_response_get,
cache$EN_l1_to_l2_client_request_deq,
cache$EN_l1_to_l2_client_response_enq,
cache$EN_l2_to_l1_server_request_enq,
cache$EN_l2_to_l1_server_response_deq,
cache$EN_ma_request_va,
cache$EN_mav_request_pa,
cache$RDY_flush_server_request_put,
cache$RDY_flush_server_response_get,
cache$RDY_l1_to_l2_client_request_deq,
cache$RDY_l1_to_l2_client_request_first,
cache$RDY_l1_to_l2_client_response_enq,
cache$RDY_l2_to_l1_server_request_enq,
cache$RDY_l2_to_l1_server_response_deq,
cache$RDY_l2_to_l1_server_response_first,
cache$RDY_mav_request_pa,
cache$RDY_mv_refill_ok,
cache$flush_server_request_put,
cache$l1_to_l2_client_request_notEmpty,
cache$l1_to_l2_client_response_notFull,
cache$l2_to_l1_server_request_notFull,
cache$l2_to_l1_server_response_notEmpty,
cache$mv_is_idle,
cache$mv_refill_ok;
// ports of submodule f_cache_flush_reqs
wire f_cache_flush_reqs$CLR,
f_cache_flush_reqs$DEQ,
f_cache_flush_reqs$D_IN,
f_cache_flush_reqs$D_OUT,
f_cache_flush_reqs$EMPTY_N,
f_cache_flush_reqs$ENQ,
f_cache_flush_reqs$FULL_N;
// ports of submodule f_cache_flush_rsps
wire f_cache_flush_rsps$CLR,
f_cache_flush_rsps$DEQ,
f_cache_flush_rsps$EMPTY_N,
f_cache_flush_rsps$ENQ,
f_cache_flush_rsps$FULL_N;
// ports of submodule f_imem_pte_writebacks
wire [127 : 0] f_imem_pte_writebacks$D_IN, f_imem_pte_writebacks$D_OUT;
wire f_imem_pte_writebacks$CLR,
f_imem_pte_writebacks$DEQ,
f_imem_pte_writebacks$EMPTY_N,
f_imem_pte_writebacks$ENQ,
f_imem_pte_writebacks$FULL_N;
// ports of submodule f_ptw_reqs
wire [127 : 0] f_ptw_reqs$D_IN, f_ptw_reqs$D_OUT;
wire f_ptw_reqs$CLR,
f_ptw_reqs$DEQ,
f_ptw_reqs$EMPTY_N,
f_ptw_reqs$ENQ,
f_ptw_reqs$FULL_N;
// ports of submodule f_ptw_rsps
wire [131 : 0] f_ptw_rsps$D_IN, f_ptw_rsps$D_OUT;
wire f_ptw_rsps$CLR,
f_ptw_rsps$DEQ,
f_ptw_rsps$EMPTY_N,
f_ptw_rsps$ENQ,
f_ptw_rsps$FULL_N;
// ports of submodule mmio
wire [207 : 0] mmio$req_mmu_cache_req;
wire [130 : 0] mmio$mmio_client_request_get;
wire [64 : 0] mmio$mmio_client_response_put;
wire [63 : 0] mmio$result_snd_fst, mmio$start_pa;
wire mmio$EN_mmio_client_request_get,
mmio$EN_mmio_client_response_put,
mmio$EN_req,
mmio$EN_start,
mmio$RDY_mmio_client_request_get,
mmio$RDY_mmio_client_response_put,
mmio$RDY_result_fst,
mmio$RDY_result_snd_fst,
mmio$result_fst;
// ports of submodule tlb
wire [200 : 0] tlb$mv_vm_xlate;
wire [63 : 0] tlb$ma_insert_pte,
tlb$ma_insert_pte_pa,
tlb$mv_vm_xlate_satp,
tlb$mv_vm_xlate_va;
wire [26 : 0] tlb$ma_insert_vpn;
wire [15 : 0] tlb$ma_insert_asid;
wire [1 : 0] tlb$ma_insert_level, tlb$mv_vm_xlate_priv;
wire tlb$EN_ma_flush,
tlb$EN_ma_insert,
tlb$mv_vm_xlate_mstatus_MXR,
tlb$mv_vm_xlate_read_not_write,
tlb$mv_vm_xlate_sstatus_SUM;
// rule scheduling signals
wire CAN_FIRE_RL_rl_CPU_ST_wait,
CAN_FIRE_RL_rl_CPU_cache_wait,
CAN_FIRE_RL_rl_CPU_req,
CAN_FIRE_RL_rl_CPU_req_A,
CAN_FIRE_RL_rl_CPU_req_B,
CAN_FIRE_RL_rl_CPU_req_mmio_WAIT,
CAN_FIRE_RL_rl_PTW_wait,
CAN_FIRE_RL_rl_cache_flush_finish,
CAN_FIRE_RL_rl_cache_flush_start,
CAN_FIRE_flush_server_request_put,
CAN_FIRE_flush_server_response_get,
CAN_FIRE_l1_to_l2_client_request_deq,
CAN_FIRE_l1_to_l2_client_response_enq,
CAN_FIRE_l2_to_l1_server_request_enq,
CAN_FIRE_l2_to_l1_server_response_deq,
CAN_FIRE_ma_req,
CAN_FIRE_mmio_client_request_get,
CAN_FIRE_mmio_client_response_put,
CAN_FIRE_pte_writeback_g_get,
CAN_FIRE_ptw_client_request_get,
CAN_FIRE_ptw_client_response_put,
CAN_FIRE_tlb_flush,
WILL_FIRE_RL_rl_CPU_ST_wait,
WILL_FIRE_RL_rl_CPU_cache_wait,
WILL_FIRE_RL_rl_CPU_req,
WILL_FIRE_RL_rl_CPU_req_A,
WILL_FIRE_RL_rl_CPU_req_B,
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT,
WILL_FIRE_RL_rl_PTW_wait,
WILL_FIRE_RL_rl_cache_flush_finish,
WILL_FIRE_RL_rl_cache_flush_start,
WILL_FIRE_flush_server_request_put,
WILL_FIRE_flush_server_response_get,
WILL_FIRE_l1_to_l2_client_request_deq,
WILL_FIRE_l1_to_l2_client_response_enq,
WILL_FIRE_l2_to_l1_server_request_enq,
WILL_FIRE_l2_to_l1_server_response_deq,
WILL_FIRE_ma_req,
WILL_FIRE_mmio_client_request_get,
WILL_FIRE_mmio_client_response_put,
WILL_FIRE_pte_writeback_g_get,
WILL_FIRE_ptw_client_request_get,
WILL_FIRE_ptw_client_response_put,
WILL_FIRE_tlb_flush;
// inputs to muxes for submodule ports
wire [3 : 0] MUX_crg_exc_code$port0__write_1__VAL_1,
MUX_crg_exc_code$port0__write_1__VAL_3;
wire [2 : 0] MUX_crg_state$port0__write_1__VAL_1;
wire [1 : 0] MUX_crg_mmu_cache_req_state$port0__write_1__VAL_3;
wire MUX_cache$ma_request_va_1__SEL_1,
MUX_crg_exc$port0__write_1__SEL_1,
MUX_crg_exc$port0__write_1__SEL_2,
MUX_crg_exc$port0__write_1__SEL_3,
MUX_crg_exc$port0__write_1__VAL_1,
MUX_crg_exc_code$port0__write_1__SEL_1,
MUX_crg_ld_val$port0__write_1__SEL_1,
MUX_crg_mmu_cache_req_state$port0__write_1__SEL_1,
MUX_crg_mmu_cache_req_state$port0__write_1__SEL_4,
MUX_crg_state$port0__write_1__SEL_1,
MUX_crg_state$port0__write_1__SEL_2,
MUX_crg_valid$port0__write_1__SEL_1,
MUX_crg_valid$port0__write_1__VAL_1,
MUX_tlb$ma_insert_1__SEL_1,
MUX_tlb$ma_insert_1__SEL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h3973;
reg [31 : 0] v__h4068;
reg [31 : 0] v__h4129;
reg [31 : 0] v__h1987;
reg [31 : 0] v__h1981;
reg [31 : 0] v__h3967;
reg [31 : 0] v__h4062;
reg [31 : 0] v__h4123;
// synopsys translate_on
// remaining internal signals
wire [2 : 0] IF_NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0_ETC___d200;
wire IF_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__re_ETC___d156,
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d177,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d184,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d218,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d226,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d239,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d245,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d251,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d257,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d266,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d275,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d282,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d289,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d296,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d303,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d310,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d317,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d324,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d331,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d338,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d363,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d371,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d379,
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d383,
cache_mav_request_pa_61_BITS_129_TO_128_62_EQ__ETC___d166,
cache_mav_request_pa_61_BITS_129_TO_128_62_EQ__ETC___d196,
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194,
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143,
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144,
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147,
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148,
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d153;
// action method ma_req
assign CAN_FIRE_ma_req = 1'd1 ;
assign WILL_FIRE_ma_req = EN_ma_req ;
// value method valid
assign valid = crg_valid ;
// value method addr
assign addr = crg_mmu_cache_req[202:139] ;
// value method word64
assign word64 = crg_ld_val ;
// value method exc
assign exc = crg_exc ;
// value method exc_code
assign exc_code = crg_exc_code ;
// action method flush_server_request_put
assign RDY_flush_server_request_put = f_cache_flush_reqs$FULL_N ;
assign CAN_FIRE_flush_server_request_put = f_cache_flush_reqs$FULL_N ;
assign WILL_FIRE_flush_server_request_put = EN_flush_server_request_put ;
// action method flush_server_response_get
assign RDY_flush_server_response_get = f_cache_flush_rsps$EMPTY_N ;
assign CAN_FIRE_flush_server_response_get = f_cache_flush_rsps$EMPTY_N ;
assign WILL_FIRE_flush_server_response_get = EN_flush_server_response_get ;
// action method tlb_flush
assign RDY_tlb_flush = 1'd1 ;
assign CAN_FIRE_tlb_flush = 1'd1 ;
assign WILL_FIRE_tlb_flush = EN_tlb_flush ;
// actionvalue method ptw_client_request_get
assign ptw_client_request_get = f_ptw_reqs$D_OUT ;
assign RDY_ptw_client_request_get = f_ptw_reqs$EMPTY_N ;
assign CAN_FIRE_ptw_client_request_get = f_ptw_reqs$EMPTY_N ;
assign WILL_FIRE_ptw_client_request_get = EN_ptw_client_request_get ;
// action method ptw_client_response_put
assign RDY_ptw_client_response_put = f_ptw_rsps$FULL_N ;
assign CAN_FIRE_ptw_client_response_put = f_ptw_rsps$FULL_N ;
assign WILL_FIRE_ptw_client_response_put = EN_ptw_client_response_put ;
// actionvalue method pte_writeback_g_get
assign pte_writeback_g_get = f_imem_pte_writebacks$D_OUT ;
assign RDY_pte_writeback_g_get = f_imem_pte_writebacks$EMPTY_N ;
assign CAN_FIRE_pte_writeback_g_get = f_imem_pte_writebacks$EMPTY_N ;
assign WILL_FIRE_pte_writeback_g_get = EN_pte_writeback_g_get ;
// value method l1_to_l2_client_request_first
assign l1_to_l2_client_request_first = cache$l1_to_l2_client_request_first ;
assign RDY_l1_to_l2_client_request_first =
cache$RDY_l1_to_l2_client_request_first ;
// action method l1_to_l2_client_request_deq
assign RDY_l1_to_l2_client_request_deq =
cache$RDY_l1_to_l2_client_request_deq ;
assign CAN_FIRE_l1_to_l2_client_request_deq =
cache$RDY_l1_to_l2_client_request_deq ;
assign WILL_FIRE_l1_to_l2_client_request_deq =
EN_l1_to_l2_client_request_deq ;
// value method l1_to_l2_client_request_notEmpty
assign l1_to_l2_client_request_notEmpty =
cache$l1_to_l2_client_request_notEmpty ;
assign RDY_l1_to_l2_client_request_notEmpty = 1'd1 ;
// action method l1_to_l2_client_response_enq
assign RDY_l1_to_l2_client_response_enq =
cache$RDY_l1_to_l2_client_response_enq ;
assign CAN_FIRE_l1_to_l2_client_response_enq =
cache$RDY_l1_to_l2_client_response_enq ;
assign WILL_FIRE_l1_to_l2_client_response_enq =
EN_l1_to_l2_client_response_enq ;
// value method l1_to_l2_client_response_notFull
assign l1_to_l2_client_response_notFull =
cache$l1_to_l2_client_response_notFull ;
assign RDY_l1_to_l2_client_response_notFull = 1'd1 ;
// action method l2_to_l1_server_request_enq
assign RDY_l2_to_l1_server_request_enq =
cache$RDY_l2_to_l1_server_request_enq ;
assign CAN_FIRE_l2_to_l1_server_request_enq =
cache$RDY_l2_to_l1_server_request_enq ;
assign WILL_FIRE_l2_to_l1_server_request_enq =
EN_l2_to_l1_server_request_enq ;
// value method l2_to_l1_server_request_notFull
assign l2_to_l1_server_request_notFull =
cache$l2_to_l1_server_request_notFull ;
assign RDY_l2_to_l1_server_request_notFull = 1'd1 ;
// value method l2_to_l1_server_response_first
assign l2_to_l1_server_response_first =
cache$l2_to_l1_server_response_first ;
assign RDY_l2_to_l1_server_response_first =
cache$RDY_l2_to_l1_server_response_first ;
// action method l2_to_l1_server_response_deq
assign RDY_l2_to_l1_server_response_deq =
cache$RDY_l2_to_l1_server_response_deq ;
assign CAN_FIRE_l2_to_l1_server_response_deq =
cache$RDY_l2_to_l1_server_response_deq ;
assign WILL_FIRE_l2_to_l1_server_response_deq =
EN_l2_to_l1_server_response_deq ;
// value method l2_to_l1_server_response_notEmpty
assign l2_to_l1_server_response_notEmpty =
cache$l2_to_l1_server_response_notEmpty ;
assign RDY_l2_to_l1_server_response_notEmpty = 1'd1 ;
// actionvalue method mmio_client_request_get
assign mmio_client_request_get = mmio$mmio_client_request_get ;
assign RDY_mmio_client_request_get = mmio$RDY_mmio_client_request_get ;
assign CAN_FIRE_mmio_client_request_get = mmio$RDY_mmio_client_request_get ;
assign WILL_FIRE_mmio_client_request_get = EN_mmio_client_request_get ;
// action method mmio_client_response_put
assign RDY_mmio_client_response_put = mmio$RDY_mmio_client_response_put ;
assign CAN_FIRE_mmio_client_response_put =
mmio$RDY_mmio_client_response_put ;
assign WILL_FIRE_mmio_client_response_put = EN_mmio_client_response_put ;
// submodule cache
mkCache #(.dcache_not_icache(1'd0), .verbosity(3'd0)) cache(.CLK(CLK),
.RST_N(RST_N),
.flush_server_request_put(cache$flush_server_request_put),
.l1_to_l2_client_response_enq_x(cache$l1_to_l2_client_response_enq_x),
.l2_to_l1_server_request_enq_x(cache$l2_to_l1_server_request_enq_x),
.ma_request_va_va(cache$ma_request_va_va),
.mav_request_pa_pa(cache$mav_request_pa_pa),
.mav_request_pa_req(cache$mav_request_pa_req),
.EN_ma_request_va(cache$EN_ma_request_va),
.EN_mav_request_pa(cache$EN_mav_request_pa),
.EN_flush_server_request_put(cache$EN_flush_server_request_put),
.EN_flush_server_response_get(cache$EN_flush_server_response_get),
.EN_l1_to_l2_client_request_deq(cache$EN_l1_to_l2_client_request_deq),
.EN_l1_to_l2_client_response_enq(cache$EN_l1_to_l2_client_response_enq),
.EN_l2_to_l1_server_request_enq(cache$EN_l2_to_l1_server_request_enq),
.EN_l2_to_l1_server_response_deq(cache$EN_l2_to_l1_server_response_deq),
.mav_request_pa(cache$mav_request_pa),
.RDY_mav_request_pa(cache$RDY_mav_request_pa),
.mv_is_idle(cache$mv_is_idle),
.mv_refill_ok(cache$mv_refill_ok),
.RDY_mv_refill_ok(cache$RDY_mv_refill_ok),
.RDY_flush_server_request_put(cache$RDY_flush_server_request_put),
.RDY_flush_server_response_get(cache$RDY_flush_server_response_get),
.l1_to_l2_client_request_first(cache$l1_to_l2_client_request_first),
.RDY_l1_to_l2_client_request_first(cache$RDY_l1_to_l2_client_request_first),
.RDY_l1_to_l2_client_request_deq(cache$RDY_l1_to_l2_client_request_deq),
.l1_to_l2_client_request_notEmpty(cache$l1_to_l2_client_request_notEmpty),
.RDY_l1_to_l2_client_request_notEmpty(),
.RDY_l1_to_l2_client_response_enq(cache$RDY_l1_to_l2_client_response_enq),
.l1_to_l2_client_response_notFull(cache$l1_to_l2_client_response_notFull),
.RDY_l1_to_l2_client_response_notFull(),
.RDY_l2_to_l1_server_request_enq(cache$RDY_l2_to_l1_server_request_enq),
.l2_to_l1_server_request_notFull(cache$l2_to_l1_server_request_notFull),
.RDY_l2_to_l1_server_request_notFull(),
.l2_to_l1_server_response_first(cache$l2_to_l1_server_response_first),
.RDY_l2_to_l1_server_response_first(cache$RDY_l2_to_l1_server_response_first),
.RDY_l2_to_l1_server_response_deq(cache$RDY_l2_to_l1_server_response_deq),
.l2_to_l1_server_response_notEmpty(cache$l2_to_l1_server_response_notEmpty),
.RDY_l2_to_l1_server_response_notEmpty());
// submodule f_cache_flush_reqs
FIFO2 #(.width(32'd1), .guarded(1'd1)) f_cache_flush_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_cache_flush_reqs$D_IN),
.ENQ(f_cache_flush_reqs$ENQ),
.DEQ(f_cache_flush_reqs$DEQ),
.CLR(f_cache_flush_reqs$CLR),
.D_OUT(f_cache_flush_reqs$D_OUT),
.FULL_N(f_cache_flush_reqs$FULL_N),
.EMPTY_N(f_cache_flush_reqs$EMPTY_N));
// submodule f_cache_flush_rsps
FIFO20 #(.guarded(1'd1)) f_cache_flush_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_cache_flush_rsps$ENQ),
.DEQ(f_cache_flush_rsps$DEQ),
.CLR(f_cache_flush_rsps$CLR),
.FULL_N(f_cache_flush_rsps$FULL_N),
.EMPTY_N(f_cache_flush_rsps$EMPTY_N));
// submodule f_imem_pte_writebacks
FIFO2 #(.width(32'd128), .guarded(1'd1)) f_imem_pte_writebacks(.RST(RST_N),
.CLK(CLK),
.D_IN(f_imem_pte_writebacks$D_IN),
.ENQ(f_imem_pte_writebacks$ENQ),
.DEQ(f_imem_pte_writebacks$DEQ),
.CLR(f_imem_pte_writebacks$CLR),
.D_OUT(f_imem_pte_writebacks$D_OUT),
.FULL_N(f_imem_pte_writebacks$FULL_N),
.EMPTY_N(f_imem_pte_writebacks$EMPTY_N));
// submodule f_ptw_reqs
FIFO2 #(.width(32'd128), .guarded(1'd1)) f_ptw_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_ptw_reqs$D_IN),
.ENQ(f_ptw_reqs$ENQ),
.DEQ(f_ptw_reqs$DEQ),
.CLR(f_ptw_reqs$CLR),
.D_OUT(f_ptw_reqs$D_OUT),
.FULL_N(f_ptw_reqs$FULL_N),
.EMPTY_N(f_ptw_reqs$EMPTY_N));
// submodule f_ptw_rsps
FIFO2 #(.width(32'd132), .guarded(1'd1)) f_ptw_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_ptw_rsps$D_IN),
.ENQ(f_ptw_rsps$ENQ),
.DEQ(f_ptw_rsps$DEQ),
.CLR(f_ptw_rsps$CLR),
.D_OUT(f_ptw_rsps$D_OUT),
.FULL_N(f_ptw_rsps$FULL_N),
.EMPTY_N(f_ptw_rsps$EMPTY_N));
// submodule mmio
mkMMIO #(.verbosity(3'd0)) mmio(.CLK(CLK),
.RST_N(RST_N),
.mmio_client_response_put(mmio$mmio_client_response_put),
.req_mmu_cache_req(mmio$req_mmu_cache_req),
.start_pa(mmio$start_pa),
.EN_req(mmio$EN_req),
.EN_start(mmio$EN_start),
.EN_mmio_client_request_get(mmio$EN_mmio_client_request_get),
.EN_mmio_client_response_put(mmio$EN_mmio_client_response_put),
.RDY_req(),
.RDY_start(),
.result_fst(mmio$result_fst),
.RDY_result_fst(mmio$RDY_result_fst),
.result_snd_fst(mmio$result_snd_fst),
.RDY_result_snd_fst(mmio$RDY_result_snd_fst),
.result_snd_snd(),
.RDY_result_snd_snd(),
.mmio_client_request_get(mmio$mmio_client_request_get),
.RDY_mmio_client_request_get(mmio$RDY_mmio_client_request_get),
.RDY_mmio_client_response_put(mmio$RDY_mmio_client_response_put));
// submodule tlb
mkTLB #(.dmem_not_imem(1'd0), .verbosity(3'd0)) tlb(.CLK(CLK),
.RST_N(RST_N),
.ma_insert_asid(tlb$ma_insert_asid),
.ma_insert_level(tlb$ma_insert_level),
.ma_insert_pte(tlb$ma_insert_pte),
.ma_insert_pte_pa(tlb$ma_insert_pte_pa),
.ma_insert_vpn(tlb$ma_insert_vpn),
.mv_vm_xlate_mstatus_MXR(tlb$mv_vm_xlate_mstatus_MXR),
.mv_vm_xlate_priv(tlb$mv_vm_xlate_priv),
.mv_vm_xlate_read_not_write(tlb$mv_vm_xlate_read_not_write),
.mv_vm_xlate_satp(tlb$mv_vm_xlate_satp),
.mv_vm_xlate_sstatus_SUM(tlb$mv_vm_xlate_sstatus_SUM),
.mv_vm_xlate_va(tlb$mv_vm_xlate_va),
.EN_ma_insert(tlb$EN_ma_insert),
.EN_ma_flush(tlb$EN_ma_flush),
.mv_vm_xlate(tlb$mv_vm_xlate),
.RDY_mv_vm_xlate(),
.RDY_ma_insert(),
.RDY_ma_flush());
// rule RL_rl_CPU_req_A
assign CAN_FIRE_RL_rl_CPU_req_A =
crg_state == 3'd0 && crg_mmu_cache_req_state == 2'd1 &&
cache$mv_is_idle ;
assign WILL_FIRE_RL_rl_CPU_req_A = CAN_FIRE_RL_rl_CPU_req_A && !EN_ma_req ;
// rule RL_rl_CPU_req_B
assign CAN_FIRE_RL_rl_CPU_req_B =
(NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ||
IF_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__re_ETC___d156) &&
crg_state == 3'd0 &&
crg_mmu_cache_req_state == 2'd2 ;
assign WILL_FIRE_RL_rl_CPU_req_B = CAN_FIRE_RL_rl_CPU_req_B && !EN_ma_req ;
// rule RL_rl_CPU_ST_wait
assign CAN_FIRE_RL_rl_CPU_ST_wait = crg_state == 3'd1 ;
assign WILL_FIRE_RL_rl_CPU_ST_wait = CAN_FIRE_RL_rl_CPU_ST_wait ;
// rule RL_rl_CPU_cache_wait
assign CAN_FIRE_RL_rl_CPU_cache_wait =
cache$RDY_mv_refill_ok && crg_state == 3'd2 ;
assign WILL_FIRE_RL_rl_CPU_cache_wait = CAN_FIRE_RL_rl_CPU_cache_wait ;
// rule RL_rl_CPU_req_mmio_WAIT
assign CAN_FIRE_RL_rl_CPU_req_mmio_WAIT =
mmio$RDY_result_snd_fst && mmio$RDY_result_fst &&
crg_state == 3'd3 ;
assign WILL_FIRE_RL_rl_CPU_req_mmio_WAIT =
CAN_FIRE_RL_rl_CPU_req_mmio_WAIT ;
// rule RL_rl_PTW_wait
assign CAN_FIRE_RL_rl_PTW_wait = f_ptw_rsps$EMPTY_N && crg_state == 3'd5 ;
assign WILL_FIRE_RL_rl_PTW_wait = CAN_FIRE_RL_rl_PTW_wait ;
// rule RL_rl_cache_flush_start
assign CAN_FIRE_RL_rl_cache_flush_start =
cache$RDY_flush_server_request_put &&
f_cache_flush_reqs$EMPTY_N &&
crg_state == 3'd0 &&
crg_mmu_cache_req_state == 2'd0 ;
assign WILL_FIRE_RL_rl_cache_flush_start =
CAN_FIRE_RL_rl_cache_flush_start ;
// rule RL_rl_cache_flush_finish
assign CAN_FIRE_RL_rl_cache_flush_finish =
cache$RDY_flush_server_response_get &&
f_cache_flush_reqs$EMPTY_N &&
f_cache_flush_rsps$FULL_N &&
crg_state == 3'd4 ;
assign WILL_FIRE_RL_rl_cache_flush_finish =
CAN_FIRE_RL_rl_cache_flush_finish ;
// rule RL_rl_CPU_req
assign CAN_FIRE_RL_rl_CPU_req = EN_ma_req ;
assign WILL_FIRE_RL_rl_CPU_req = EN_ma_req ;
// inputs to muxes for submodule ports
assign MUX_cache$ma_request_va_1__SEL_1 =
EN_ma_req && crg_state$port1__read == 3'd0 && cache$mv_is_idle ;
assign MUX_crg_exc$port0__write_1__SEL_1 =
WILL_FIRE_RL_rl_CPU_req_B &&
(NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ||
tlb$mv_vm_xlate[200:199] != 2'd1 &&
(tlb$mv_vm_xlate[200:199] == 2'd2 ||
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d177)) ;
assign MUX_crg_exc$port0__write_1__SEL_2 =
WILL_FIRE_RL_rl_CPU_cache_wait && !cache$mv_refill_ok ;
assign MUX_crg_exc$port0__write_1__SEL_3 =
WILL_FIRE_RL_rl_PTW_wait && f_ptw_rsps$D_OUT[131:130] != 2'd0 ;
assign MUX_crg_exc_code$port0__write_1__SEL_1 =
WILL_FIRE_RL_rl_CPU_req_B &&
(NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ||
tlb$mv_vm_xlate[200:199] == 2'd2) ;
assign MUX_crg_ld_val$port0__write_1__SEL_1 =
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d177 ;
assign MUX_crg_mmu_cache_req_state$port0__write_1__SEL_1 =
WILL_FIRE_RL_rl_CPU_req_B &&
(NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ||
tlb$mv_vm_xlate[200:199] != 2'd1 &&
(tlb$mv_vm_xlate[200:199] == 2'd2 ||
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d184)) ;
assign MUX_crg_mmu_cache_req_state$port0__write_1__SEL_4 =
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT ||
WILL_FIRE_RL_rl_CPU_ST_wait ;
assign MUX_crg_state$port0__write_1__SEL_1 =
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
(tlb$mv_vm_xlate[200:199] == 2'd1 ||
tlb$mv_vm_xlate[200:199] != 2'd2 &&
cache_mav_request_pa_61_BITS_129_TO_128_62_EQ__ETC___d196) ;
assign MUX_crg_state$port0__write_1__SEL_2 =
WILL_FIRE_RL_rl_cache_flush_finish || WILL_FIRE_RL_rl_PTW_wait ||
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT ||
WILL_FIRE_RL_rl_CPU_cache_wait ||
WILL_FIRE_RL_rl_CPU_ST_wait ;
assign MUX_crg_valid$port0__write_1__SEL_1 =
WILL_FIRE_RL_rl_CPU_req_B &&
(NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ||
tlb$mv_vm_xlate[200:199] == 2'd1 ||
tlb$mv_vm_xlate[200:199] == 2'd2 ||
cache_mav_request_pa_61_BITS_129_TO_128_62_EQ__ETC___d166) ;
assign MUX_tlb$ma_insert_1__SEL_1 =
WILL_FIRE_RL_rl_PTW_wait && f_ptw_rsps$D_OUT[131:130] == 2'd0 ;
assign MUX_tlb$ma_insert_1__SEL_2 =
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
tlb$mv_vm_xlate[130] ;
assign MUX_crg_exc$port0__write_1__VAL_1 =
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ||
tlb$mv_vm_xlate[200:199] == 2'd2 ;
assign MUX_crg_exc_code$port0__write_1__VAL_1 =
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ?
4'd0 :
tlb$mv_vm_xlate[134:131] ;
assign MUX_crg_exc_code$port0__write_1__VAL_3 =
(f_ptw_rsps$D_OUT[131:130] == 2'd1) ? 4'd1 : 4'd12 ;
assign MUX_crg_mmu_cache_req_state$port0__write_1__VAL_3 =
(f_ptw_rsps$D_OUT[131:130] == 2'd0) ? 2'd1 : 2'd0 ;
assign MUX_crg_state$port0__write_1__VAL_1 =
(tlb$mv_vm_xlate[200:199] == 2'd1) ?
3'd5 :
IF_NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0_ETC___d200 ;
assign MUX_crg_valid$port0__write_1__VAL_1 =
NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ||
tlb$mv_vm_xlate[200:199] != 2'd1 &&
(tlb$mv_vm_xlate[200:199] == 2'd2 ||
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d177) ;
// inlined wires
assign crg_state$EN_port0__write =
MUX_crg_state$port0__write_1__SEL_1 ||
WILL_FIRE_RL_rl_cache_flush_finish ||
WILL_FIRE_RL_rl_PTW_wait ||
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT ||
WILL_FIRE_RL_rl_CPU_cache_wait ||
WILL_FIRE_RL_rl_CPU_ST_wait ||
WILL_FIRE_RL_rl_cache_flush_start ;
always@(MUX_crg_state$port0__write_1__SEL_1 or
MUX_crg_state$port0__write_1__VAL_1 or
MUX_crg_state$port0__write_1__SEL_2 or
WILL_FIRE_RL_rl_cache_flush_start)
begin
case (1'b1) // synopsys parallel_case
MUX_crg_state$port0__write_1__SEL_1:
crg_state$port0__write_1 = MUX_crg_state$port0__write_1__VAL_1;
MUX_crg_state$port0__write_1__SEL_2: crg_state$port0__write_1 = 3'd0;
WILL_FIRE_RL_rl_cache_flush_start: crg_state$port0__write_1 = 3'd4;
default: crg_state$port0__write_1 = 3'b010 /* unspecified value */ ;
endcase
end
assign crg_state$port1__read =
crg_state$EN_port0__write ?
crg_state$port0__write_1 :
crg_state ;
assign crg_mmu_cache_req_state$EN_port0__write =
MUX_crg_mmu_cache_req_state$port0__write_1__SEL_1 ||
WILL_FIRE_RL_rl_CPU_cache_wait && !cache$mv_refill_ok ||
WILL_FIRE_RL_rl_PTW_wait ||
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT ||
WILL_FIRE_RL_rl_CPU_ST_wait ||
WILL_FIRE_RL_rl_CPU_req_A ;
always@(WILL_FIRE_RL_rl_PTW_wait or
MUX_crg_mmu_cache_req_state$port0__write_1__VAL_3 or
MUX_crg_mmu_cache_req_state$port0__write_1__SEL_1 or
MUX_crg_exc$port0__write_1__SEL_2 or
MUX_crg_mmu_cache_req_state$port0__write_1__SEL_4 or
WILL_FIRE_RL_rl_CPU_req_A)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_PTW_wait:
crg_mmu_cache_req_state$port0__write_1 =
MUX_crg_mmu_cache_req_state$port0__write_1__VAL_3;
MUX_crg_mmu_cache_req_state$port0__write_1__SEL_1 ||
MUX_crg_exc$port0__write_1__SEL_2 ||
MUX_crg_mmu_cache_req_state$port0__write_1__SEL_4:
crg_mmu_cache_req_state$port0__write_1 = 2'd0;
WILL_FIRE_RL_rl_CPU_req_A:
crg_mmu_cache_req_state$port0__write_1 = 2'd2;
default: crg_mmu_cache_req_state$port0__write_1 =
2'b10 /* unspecified value */ ;
endcase
end
assign crg_mmu_cache_req_state$port1__read =
crg_mmu_cache_req_state$EN_port0__write ?
crg_mmu_cache_req_state$port0__write_1 :
crg_mmu_cache_req_state ;
assign crg_mmu_cache_req_state$port1__write_1 =
(crg_state$port1__read != 3'd0 || !cache$mv_is_idle) ?
2'd1 :
2'd2 ;
assign crg_mmu_cache_req_state$port2__read =
EN_ma_req ?
crg_mmu_cache_req_state$port1__write_1 :
crg_mmu_cache_req_state$port1__read ;
assign crg_mmu_cache_req$port1__write_1 =
{ 5'd2,
ma_req_va,
71'h55555555555555552A,
ma_req_priv,
ma_req_sstatus_SUM,
ma_req_mstatus_MXR,
ma_req_satp } ;
assign crg_mmu_cache_req$port2__read =
EN_ma_req ?
crg_mmu_cache_req$port1__write_1 :
crg_mmu_cache_req ;
assign crg_valid$EN_port0__write =
WILL_FIRE_RL_rl_CPU_req_B &&
(NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ||
tlb$mv_vm_xlate[200:199] == 2'd1 ||
tlb$mv_vm_xlate[200:199] == 2'd2 ||
cache_mav_request_pa_61_BITS_129_TO_128_62_EQ__ETC___d166) ||
WILL_FIRE_RL_rl_CPU_cache_wait && !cache$mv_refill_ok ||
WILL_FIRE_RL_rl_PTW_wait && f_ptw_rsps$D_OUT[131:130] != 2'd0 ||
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT ||
WILL_FIRE_RL_rl_CPU_ST_wait ;
assign crg_valid$port0__write_1 =
!MUX_crg_valid$port0__write_1__SEL_1 ||
MUX_crg_valid$port0__write_1__VAL_1 ;
assign crg_valid$port1__read =
crg_valid$EN_port0__write ?
crg_valid$port0__write_1 :
crg_valid ;
assign crg_valid$port2__read = !EN_ma_req && crg_valid$port1__read ;
assign crg_exc$EN_port0__write =
MUX_crg_exc$port0__write_1__SEL_1 ||
WILL_FIRE_RL_rl_CPU_cache_wait && !cache$mv_refill_ok ||
WILL_FIRE_RL_rl_PTW_wait && f_ptw_rsps$D_OUT[131:130] != 2'd0 ||
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT ;
always@(WILL_FIRE_RL_rl_CPU_req_mmio_WAIT or
mmio$result_fst or
MUX_crg_exc$port0__write_1__SEL_1 or
MUX_crg_exc$port0__write_1__VAL_1 or
MUX_crg_exc$port0__write_1__SEL_2 or
MUX_crg_exc$port0__write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT:
crg_exc$port0__write_1 = mmio$result_fst;
MUX_crg_exc$port0__write_1__SEL_1:
crg_exc$port0__write_1 = MUX_crg_exc$port0__write_1__VAL_1;
MUX_crg_exc$port0__write_1__SEL_2 || MUX_crg_exc$port0__write_1__SEL_3:
crg_exc$port0__write_1 = 1'd1;
default: crg_exc$port0__write_1 = 1'b0 /* unspecified value */ ;
endcase
end
assign crg_exc$port1__read =
crg_exc$EN_port0__write ? crg_exc$port0__write_1 : crg_exc ;
assign crg_exc_code$EN_port0__write =
WILL_FIRE_RL_rl_CPU_req_B &&
(NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 ||
tlb$mv_vm_xlate[200:199] == 2'd2) ||
WILL_FIRE_RL_rl_CPU_cache_wait && !cache$mv_refill_ok ||
WILL_FIRE_RL_rl_PTW_wait && f_ptw_rsps$D_OUT[131:130] != 2'd0 ||
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT ;
always@(MUX_crg_exc_code$port0__write_1__SEL_1 or
MUX_crg_exc_code$port0__write_1__VAL_1 or
MUX_crg_exc$port0__write_1__SEL_3 or
MUX_crg_exc_code$port0__write_1__VAL_3 or
MUX_crg_exc$port0__write_1__SEL_2 or
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT)
begin
case (1'b1) // synopsys parallel_case
MUX_crg_exc_code$port0__write_1__SEL_1:
crg_exc_code$port0__write_1 =
MUX_crg_exc_code$port0__write_1__VAL_1;
MUX_crg_exc$port0__write_1__SEL_3:
crg_exc_code$port0__write_1 =
MUX_crg_exc_code$port0__write_1__VAL_3;
MUX_crg_exc$port0__write_1__SEL_2 || WILL_FIRE_RL_rl_CPU_req_mmio_WAIT:
crg_exc_code$port0__write_1 = 4'd1;
default: crg_exc_code$port0__write_1 = 4'b1010 /* unspecified value */ ;
endcase
end
assign crg_exc_code$port1__read =
crg_exc_code$EN_port0__write ?
crg_exc_code$port0__write_1 :
crg_exc_code ;
assign crg_ld_val$EN_port0__write =
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d177 ||
WILL_FIRE_RL_rl_CPU_req_mmio_WAIT ;
assign crg_ld_val$port0__write_1 =
MUX_crg_ld_val$port0__write_1__SEL_1 ?
cache$mav_request_pa[127:64] :
mmio$result_snd_fst ;
assign crg_ld_val$port1__read =
crg_ld_val$EN_port0__write ?
crg_ld_val$port0__write_1 :
crg_ld_val ;
// register crg_exc
assign crg_exc$D_IN = crg_exc$port1__read ;
assign crg_exc$EN = 1'b1 ;
// register crg_exc_code
assign crg_exc_code$D_IN = crg_exc_code$port1__read ;
assign crg_exc_code$EN = 1'b1 ;
// register crg_ld_val
assign crg_ld_val$D_IN = crg_ld_val$port1__read ;
assign crg_ld_val$EN = 1'b1 ;
// register crg_mmu_cache_req
assign crg_mmu_cache_req$D_IN = crg_mmu_cache_req$port2__read ;
assign crg_mmu_cache_req$EN = 1'b1 ;
// register crg_mmu_cache_req_state
assign crg_mmu_cache_req_state$D_IN = crg_mmu_cache_req_state$port2__read ;
assign crg_mmu_cache_req_state$EN = 1'b1 ;
// register crg_state
assign crg_state$D_IN = crg_state$port1__read ;
assign crg_state$EN = 1'b1 ;
// register crg_valid
assign crg_valid$D_IN = crg_valid$port2__read ;
assign crg_valid$EN = 1'b1 ;
// submodule cache
assign cache$flush_server_request_put = f_cache_flush_reqs$D_OUT ;
assign cache$l1_to_l2_client_response_enq_x =
l1_to_l2_client_response_enq_x ;
assign cache$l2_to_l1_server_request_enq_x = l2_to_l1_server_request_enq_x ;
assign cache$ma_request_va_va =
MUX_cache$ma_request_va_1__SEL_1 ?
crg_mmu_cache_req$port1__write_1[202:139] :
crg_mmu_cache_req[202:139] ;
assign cache$mav_request_pa_pa = tlb$mv_vm_xlate[198:135] ;
assign cache$mav_request_pa_req = crg_mmu_cache_req ;
assign cache$EN_ma_request_va =
EN_ma_req && crg_state$port1__read == 3'd0 && cache$mv_is_idle ||
WILL_FIRE_RL_rl_CPU_req_A ;
assign cache$EN_mav_request_pa =
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d218 ;
assign cache$EN_flush_server_request_put =
CAN_FIRE_RL_rl_cache_flush_start ;
assign cache$EN_flush_server_response_get =
CAN_FIRE_RL_rl_cache_flush_finish ;
assign cache$EN_l1_to_l2_client_request_deq =
EN_l1_to_l2_client_request_deq ;
assign cache$EN_l1_to_l2_client_response_enq =
EN_l1_to_l2_client_response_enq ;
assign cache$EN_l2_to_l1_server_request_enq =
EN_l2_to_l1_server_request_enq ;
assign cache$EN_l2_to_l1_server_response_deq =
EN_l2_to_l1_server_response_deq ;
// submodule f_cache_flush_reqs
assign f_cache_flush_reqs$D_IN = flush_server_request_put ;
assign f_cache_flush_reqs$ENQ = EN_flush_server_request_put ;
assign f_cache_flush_reqs$DEQ = CAN_FIRE_RL_rl_cache_flush_finish ;
assign f_cache_flush_reqs$CLR = 1'b0 ;
// submodule f_cache_flush_rsps
assign f_cache_flush_rsps$ENQ = CAN_FIRE_RL_rl_cache_flush_finish ;
assign f_cache_flush_rsps$DEQ = EN_flush_server_response_get ;
assign f_cache_flush_rsps$CLR = 1'b0 ;
// submodule f_imem_pte_writebacks
assign f_imem_pte_writebacks$D_IN =
{ tlb$mv_vm_xlate[63:0], tlb$mv_vm_xlate[129:66] } ;
assign f_imem_pte_writebacks$ENQ = MUX_tlb$ma_insert_1__SEL_2 ;
assign f_imem_pte_writebacks$DEQ = EN_pte_writeback_g_get ;
assign f_imem_pte_writebacks$CLR = 1'b0 ;
// submodule f_ptw_reqs
assign f_ptw_reqs$D_IN =
{ crg_mmu_cache_req[202:139], crg_mmu_cache_req[63:0] } ;
assign f_ptw_reqs$ENQ =
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] == 2'd1 ;
assign f_ptw_reqs$DEQ = EN_ptw_client_request_get ;
assign f_ptw_reqs$CLR = 1'b0 ;
// submodule f_ptw_rsps
assign f_ptw_rsps$D_IN = ptw_client_response_put ;
assign f_ptw_rsps$ENQ = EN_ptw_client_response_put ;
assign f_ptw_rsps$DEQ = CAN_FIRE_RL_rl_PTW_wait ;
assign f_ptw_rsps$CLR = 1'b0 ;
// submodule mmio
assign mmio$mmio_client_response_put = mmio_client_response_put ;
assign mmio$req_mmu_cache_req = crg_mmu_cache_req$port1__write_1 ;
assign mmio$start_pa = tlb$mv_vm_xlate[198:135] ;
assign mmio$EN_req = EN_ma_req ;
assign mmio$EN_start =
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d383 ;
assign mmio$EN_mmio_client_request_get = EN_mmio_client_request_get ;
assign mmio$EN_mmio_client_response_put = EN_mmio_client_response_put ;
// submodule tlb
assign tlb$ma_insert_asid = crg_mmu_cache_req[59:44] ;
assign tlb$ma_insert_level =
MUX_tlb$ma_insert_1__SEL_1 ?
f_ptw_rsps$D_OUT[65:64] :
tlb$mv_vm_xlate[65:64] ;
assign tlb$ma_insert_pte =
MUX_tlb$ma_insert_1__SEL_1 ?
f_ptw_rsps$D_OUT[129:66] :
tlb$mv_vm_xlate[129:66] ;
assign tlb$ma_insert_pte_pa =
MUX_tlb$ma_insert_1__SEL_1 ?
f_ptw_rsps$D_OUT[63:0] :
tlb$mv_vm_xlate[63:0] ;
assign tlb$ma_insert_vpn = crg_mmu_cache_req[177:151] ;
assign tlb$mv_vm_xlate_mstatus_MXR = crg_mmu_cache_req[64] ;
assign tlb$mv_vm_xlate_priv = crg_mmu_cache_req[67:66] ;
assign tlb$mv_vm_xlate_read_not_write = 1'd1 ;
assign tlb$mv_vm_xlate_satp = crg_mmu_cache_req[63:0] ;
assign tlb$mv_vm_xlate_sstatus_SUM = crg_mmu_cache_req[65] ;
assign tlb$mv_vm_xlate_va = crg_mmu_cache_req[202:139] ;
assign tlb$EN_ma_insert =
WILL_FIRE_RL_rl_PTW_wait && f_ptw_rsps$D_OUT[131:130] == 2'd0 ||
WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
tlb$mv_vm_xlate[130] ;
assign tlb$EN_ma_flush = EN_tlb_flush ;
// remaining internal signals
assign IF_NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0_ETC___d200 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) ?
3'd2 :
3'd3 ;
assign IF_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__re_ETC___d156 =
(tlb$mv_vm_xlate[200:199] == 2'd1) ?
f_ptw_reqs$FULL_N :
tlb$mv_vm_xlate[200:199] == 2'd2 ||
(!tlb$mv_vm_xlate[130] || f_imem_pte_writebacks$FULL_N) &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d153 ;
assign NOT_crg_mmu_cache_req_port0__read__05_BITS_204_ETC___d128 =
crg_mmu_cache_req[204:203] != 2'b0 &&
(crg_mmu_cache_req[204:203] != 2'b01 ||
crg_mmu_cache_req[139]) &&
(crg_mmu_cache_req[204:203] != 2'b10 ||
crg_mmu_cache_req[140:139] != 2'b0) &&
(crg_mmu_cache_req[204:203] != 2'b11 ||
crg_mmu_cache_req[141:139] != 3'b0) ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d177 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] != 2'd0 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d184 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd1 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d218 =
tlb$mv_vm_xlate[200:199] != 2'd2 &&
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d226 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d239 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
crg_mmu_cache_req[207:206] == 2'd2 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d245 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
crg_mmu_cache_req[207:206] != 2'd2 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d251 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
crg_mmu_cache_req[207:206] == 2'd0 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d257 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
crg_mmu_cache_req[207:206] == 2'd1 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d266 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
crg_mmu_cache_req[207:206] != 2'd2 &&
crg_mmu_cache_req[207:206] != 2'd0 &&
crg_mmu_cache_req[207:206] != 2'd1 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d275 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
crg_mmu_cache_req[207:206] == 2'd2 &&
crg_mmu_cache_req[74:70] == 5'b00010 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d282 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
crg_mmu_cache_req[207:206] == 2'd2 &&
crg_mmu_cache_req[74:70] == 5'b00011 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d289 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
crg_mmu_cache_req[207:206] == 2'd2 &&
crg_mmu_cache_req[74:70] == 5'b0 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d296 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
crg_mmu_cache_req[207:206] == 2'd2 &&
crg_mmu_cache_req[74:70] == 5'b00001 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d303 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
crg_mmu_cache_req[207:206] == 2'd2 &&
crg_mmu_cache_req[74:70] == 5'b00100 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d310 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
crg_mmu_cache_req[207:206] == 2'd2 &&
crg_mmu_cache_req[74:70] == 5'b01100 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d317 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
crg_mmu_cache_req[207:206] == 2'd2 &&
crg_mmu_cache_req[74:70] == 5'b01000 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d324 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
crg_mmu_cache_req[207:206] == 2'd2 &&
crg_mmu_cache_req[74:70] == 5'b10000 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d331 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
crg_mmu_cache_req[207:206] == 2'd2 &&
crg_mmu_cache_req[74:70] == 5'b10100 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d338 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
crg_mmu_cache_req[207:206] == 2'd2 &&
crg_mmu_cache_req[74:70] == 5'b11000 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d363 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
crg_mmu_cache_req[207:206] == 2'd2 &&
crg_mmu_cache_req[74:70] != 5'b00010 &&
crg_mmu_cache_req[74:70] != 5'b00011 &&
crg_mmu_cache_req[74:70] != 5'b0 &&
crg_mmu_cache_req[74:70] != 5'b00001 &&
crg_mmu_cache_req[74:70] != 5'b00100 &&
crg_mmu_cache_req[74:70] != 5'b01100 &&
crg_mmu_cache_req[74:70] != 5'b01000 &&
crg_mmu_cache_req[74:70] != 5'b10000 &&
crg_mmu_cache_req[74:70] != 5'b10100 &&
crg_mmu_cache_req[74:70] != 5'b11000 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d371 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
(crg_mmu_cache_req[207:206] == 2'd2 &&
crg_mmu_cache_req[74:70] != 5'b00010 ||
crg_mmu_cache_req[207:206] == 2'd1) ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d379 =
(!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 &&
tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) &&
cache$mav_request_pa[129:128] == 2'd2 &&
(crg_mmu_cache_req[207:206] != 2'd2 ||
crg_mmu_cache_req[74:70] == 5'b00010) &&
crg_mmu_cache_req[207:206] != 2'd1 ;
assign NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d383 =
tlb$mv_vm_xlate[200:199] != 2'd2 &&
(tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144) &&
(tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) ;
assign cache_mav_request_pa_61_BITS_129_TO_128_62_EQ__ETC___d166 =
cache$mav_request_pa[129:128] == 2'd0 ||
cache$mav_request_pa[129:128] == 2'd1 ||
(tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144) &&
(tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) ;
assign cache_mav_request_pa_61_BITS_129_TO_128_62_EQ__ETC___d196 =
cache$mav_request_pa[129:128] == 2'd0 ||
(tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144) &&
(tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) ;
assign crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 =
crg_mmu_cache_req[204:203] == 2'b0 ||
crg_mmu_cache_req[204:203] == 2'b01 && !crg_mmu_cache_req[139] ||
crg_mmu_cache_req[204:203] == 2'b10 &&
crg_mmu_cache_req[140:139] == 2'b0 ||
crg_mmu_cache_req[204:203] == 2'b11 &&
crg_mmu_cache_req[141:139] == 3'b0 ;
assign tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 =
tlb$mv_vm_xlate[198:135] < 64'h0000000000001000 ;
assign tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144 =
tlb$mv_vm_xlate[198:135] < 64'd8192 ;
assign tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 =
tlb$mv_vm_xlate[198:135] < 64'h0000000080000000 ;
assign tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148 =
tlb$mv_vm_xlate[198:135] < 64'h0000000090000000 ;
assign tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d153 =
(tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d143 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d144) &&
(tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d147 ||
!tlb_mv_vm_xlate_crg_mmu_cache_req_port0__read__ETC___d148) ||
cache$RDY_mav_request_pa ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
crg_mmu_cache_req_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
crg_state <= `BSV_ASSIGNMENT_DELAY 3'd0;
crg_valid <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (crg_mmu_cache_req_state$EN)
crg_mmu_cache_req_state <= `BSV_ASSIGNMENT_DELAY
crg_mmu_cache_req_state$D_IN;
if (crg_state$EN) crg_state <= `BSV_ASSIGNMENT_DELAY crg_state$D_IN;
if (crg_valid$EN) crg_valid <= `BSV_ASSIGNMENT_DELAY crg_valid$D_IN;
end
if (crg_exc$EN) crg_exc <= `BSV_ASSIGNMENT_DELAY crg_exc$D_IN;
if (crg_exc_code$EN)
crg_exc_code <= `BSV_ASSIGNMENT_DELAY crg_exc_code$D_IN;
if (crg_ld_val$EN) crg_ld_val <= `BSV_ASSIGNMENT_DELAY crg_ld_val$D_IN;
if (crg_mmu_cache_req$EN)
crg_mmu_cache_req <= `BSV_ASSIGNMENT_DELAY crg_mmu_cache_req$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
crg_exc = 1'h0;
crg_exc_code = 4'hA;
crg_ld_val = 64'hAAAAAAAAAAAAAAAA;
crg_mmu_cache_req =
208'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
crg_mmu_cache_req_state = 2'h2;
crg_state = 3'h2;
crg_valid = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
tlb$mv_vm_xlate[200:199] != 2'd0)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/I_MMU_Cache.bsv\", line 386, column 67\nFAIL: unknown vm_xlate result");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
tlb$mv_vm_xlate[200:199] != 2'd0)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d226)
begin
v__h3973 = $stime;
#0;
end
v__h3967 = v__h3973 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d226)
$display("%0d: %m.rl_CPU_req_B", v__h3967);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d226)
begin
v__h4068 = $stime;
#0;
end
v__h4062 = v__h4068 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d226)
$display(" INTERNAL ERROR: Impossible CACHE_WRITE_HIT in IMem",
v__h4062);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d226)
begin
v__h4129 = $stime;
#0;
end
v__h4123 = v__h4129 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d226)
$write(" ", v__h4123);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d239)
$write("MMU_Cache_Req{");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d245)
$write("MMU_Cache_Req{");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d239)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d251)
$write("CACHE_LD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d257)
$write("CACHE_ST");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d266)
$write("CACHE_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d239)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d245)
$write(" f3 %3b", crg_mmu_cache_req[205:203]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d239)
$write("CACHE_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d245)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d239)
$write(" f3 %3b", crg_mmu_cache_req[205:203]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d245)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d239)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d245)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d275)
$write("LR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d282)
$write("SC");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d289)
$write("ADD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d296)
$write("SWAP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d303)
$write("XOR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d310)
$write("AND");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d317)
$write("OR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d324)
$write("MIN");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d331)
$write("MAX");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d338)
$write("MINU");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d363)
$write("MAXU");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d245)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d239)
$write(" aqrl %2b", crg_mmu_cache_req[69:68]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d245)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d226)
$write(" va %0h", crg_mmu_cache_req[202:139]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d371)
$write(" st_val %0h", crg_mmu_cache_req[138:75]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d379)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d226)
$write(" priv %0d sstatus_SUM %0d mstatus_MXR %0d satp %0h",
crg_mmu_cache_req[67:66],
crg_mmu_cache_req[65],
crg_mmu_cache_req[64],
crg_mmu_cache_req[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d226)
$write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d226)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_CPU_req_B &&
crg_mmu_cache_req_port0__read__05_BITS_204_TO__ETC___d194 &&
tlb$mv_vm_xlate[200:199] != 2'd1 &&
tlb$mv_vm_xlate[200:199] != 2'd2 &&
NOT_tlb_mv_vm_xlate_crg_mmu_cache_req_port0__r_ETC___d226)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
begin
v__h1987 = $stime;
#0;
end
v__h1981 = v__h1987 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$display("%0d: %m.rl_CPU_req", v__h1981);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$write(" INTERNAL ERROR: crg_mmu_cache_req_state: ");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read == 2'd1)
$write("REQ_STATE_FULL_A");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req_state$port1__read != 2'd1)
$write("REQ_STATE_FULL_B");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$write("; expected EMPTY", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2)
$write("MMU_Cache_Req{");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd2)
$write("MMU_Cache_Req{");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd0)
$write("CACHE_LD");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd1)
$write("CACHE_ST");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd2 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd1)
$write("CACHE_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd2)
$write(" f3 %3b", crg_mmu_cache_req$port1__write_1[205:203]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2)
$write("CACHE_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2)
$write(" f3 %3b", crg_mmu_cache_req$port1__write_1[205:203]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b00010)
$write("LR");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b00011)
$write("SC");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b0)
$write("ADD");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b00001)
$write("SWAP");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b00100)
$write("XOR");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b01100)
$write("AND");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b01000)
$write("OR");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b10000)
$write("MIN");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b10100)
$write("MAX");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] == 5'b11000)
$write("MINU");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b00010 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b00011 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b0 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b00001 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b00100 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b01100 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b01000 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b10000 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b10100 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b11000)
$write("MAXU");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] == 2'd2)
$write(" aqrl %2b", crg_mmu_cache_req$port1__write_1[69:68]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$write(" va %0h", crg_mmu_cache_req$port1__write_1[202:139]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
(crg_mmu_cache_req$port1__write_1[207:206] == 2'd2 &&
crg_mmu_cache_req$port1__write_1[74:70] != 5'b00010 ||
crg_mmu_cache_req$port1__write_1[207:206] == 2'd1))
$write(" st_val %0h", crg_mmu_cache_req$port1__write_1[138:75]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0 &&
(crg_mmu_cache_req$port1__write_1[207:206] != 2'd2 ||
crg_mmu_cache_req$port1__write_1[74:70] == 5'b00010) &&
crg_mmu_cache_req$port1__write_1[207:206] != 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$write(" priv %0d sstatus_SUM %0d mstatus_MXR %0d satp %0h",
crg_mmu_cache_req$port1__write_1[67:66],
crg_mmu_cache_req$port1__write_1[65],
crg_mmu_cache_req$port1__write_1[64],
crg_mmu_cache_req$port1__write_1[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$write("}");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_ma_req && crg_mmu_cache_req_state$port1__read != 2'd0)
$finish(32'd1);
end
// synopsys translate_on
endmodule // mkI_MMU_Cache
|
// EE 454
// Spring 2015
// Lab 2 Part 2
// John Timms
// accumulator_memory_tb.v
`timescale 1 ns / 100 ps
module accumulator_memory_tb;
////////////////////////////////////////////////////////////////////////////////////////////////
// Set up the clock and reset
////////////////////////////////////////////////////////////////////////////////////////////////
reg clk_tb, reset_tb;
localparam CLK_PERIOD = 20;
integer clk_count;
initial
begin : CLK_GENERATOR
clk_tb = 0;
forever
begin
#(CLK_PERIOD/2) clk_tb = ~clk_tb;
end
end
initial
begin : RESET_GENERATOR
reset_tb = 1;
#(2 * CLK_PERIOD) reset_tb = 0;
end
initial
begin : CLK_COUNTER
clk_count = 0;
# (0.6 * CLK_PERIOD);
forever
begin
#(CLK_PERIOD) clk_count <= clk_count + 1;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////
// Set up the memory module for testing
////////////////////////////////////////////////////////////////////////////////////////////////
localparam
NOP = 2'b00, // No operation
FETCH = 2'b01, // Fetch an operand from the memory
SEND = 2'b10; // Send a result to the memory
reg [1:0] op_tb;
wire signal_tb;
wire [31:0] read_tb;
reg [31:0] write_tb;
reg load_tb;
wire full_tb;
wire [9:0] index_tb;
wire [31:0] preview_tb;
wire [4:0] state_tb;
reg [5*8:1] state_string;
integer random_internal;
integer results;
integer load_count = 0;
integer read_count = 0;
always @(*)
begin
case (state_tb)
5'b00001: state_string = "INI ";
5'b00010: state_string = "READ ";
5'b00100: state_string = "WRITE";
5'b01000: state_string = "READY";
5'b10000: state_string = "DONE ";
default: state_string = "UNKN ";
endcase
end
// accumulator_memory (clk, reset, op, signal, read, write, load, full, index, preview, state)
accumulator_memory UUT (clk_tb, reset_tb, op_tb, signal_tb, read_tb, write_tb, load_tb, full_tb, index_tb, preview_tb, state_tb);
////////////////////////////////////////////////////////////////////////////////////////////////
// Run the test
////////////////////////////////////////////////////////////////////////////////////////////////
initial
begin
results = $fopen("memory.txt", "w");
wait (!reset_tb);
while (load_count < 1023) begin
@(posedge clk_tb)
load_tb <= 1'b1;
random_internal = {$random} % 65536;
write_tb <= random_internal;
$fdisplay (results, "Load %h, %d", random_internal, load_count);
load_count <= load_count + 1;
end
// Loading done, now fetch
@(posedge clk_tb)
write_tb <= 'bx;
load_tb <= 1'b0;
op_tb <= FETCH;
// Must be 1024 because it takes multiple clocks to get a read
while (read_count < 1024) begin
@(posedge clk_tb)
if (signal_tb == 1) begin
$fdisplay (results, "Read %h, %d", read_tb, read_count);
read_count <= read_count + 1;
end
end
$fclose (results);
$stop;
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pipe_clock.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Filename : pcie3_7x_0_pipe_clock.v
// Description : PIPE Clock Module for 7 Series Transceiver
// Version : 20.2
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Clock Module -------------------------------------------------
module pcie3_7x_0_pipe_clock #
(
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_CLK_SHARING_EN= "FALSE", // Enable Clock Sharing
parameter PCIE_LANE = 1, // PCIe number of lanes
parameter PCIE_LINK_SPEED = 3, // PCIe link speed
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter PCIE_USERCLK1_FREQ = 2, // PCIe user clock 1 frequency
parameter PCIE_USERCLK2_FREQ = 2, // PCIe user clock 2 frequency
parameter PCIE_OOBCLK_MODE = 1, // PCIe oob clock mode
parameter PCIE_DEBUG_MODE = 0 // PCIe Debug mode
)
(
//---------- Input -------------------------------------
input CLK_CLK,
input CLK_TXOUTCLK,
input [PCIE_LANE-1:0] CLK_RXOUTCLK_IN,
input CLK_RST_N,
input [PCIE_LANE-1:0] CLK_PCLK_SEL,
input [PCIE_LANE-1:0] CLK_PCLK_SEL_SLAVE,
input CLK_GEN3,
//---------- Output ------------------------------------
output CLK_PCLK,
output CLK_PCLK_SLAVE,
output CLK_RXUSRCLK,
output [PCIE_LANE-1:0] CLK_RXOUTCLK_OUT,
output CLK_DCLK,
output CLK_OOBCLK,
output CLK_USERCLK1,
output CLK_USERCLK2,
output CLK_MMCM_LOCK
);
//---------- Select Clock Divider ----------------------
localparam DIVCLK_DIVIDE = (PCIE_REFCLK_FREQ == 2) ? 1 :
(PCIE_REFCLK_FREQ == 1) ? 1 : 1;
localparam CLKFBOUT_MULT_F = (PCIE_REFCLK_FREQ == 2) ? 4 :
(PCIE_REFCLK_FREQ == 1) ? 8 : 10;
localparam CLKIN1_PERIOD = (PCIE_REFCLK_FREQ == 2) ? 4 :
(PCIE_REFCLK_FREQ == 1) ? 8 : 10;
localparam CLKOUT0_DIVIDE_F = 8;
localparam CLKOUT1_DIVIDE = 4;
localparam CLKOUT2_DIVIDE = (PCIE_USERCLK1_FREQ == 5) ? 2 :
(PCIE_USERCLK1_FREQ == 4) ? 4 :
(PCIE_USERCLK1_FREQ == 3) ? 8 :
(PCIE_USERCLK1_FREQ == 1) ? 32 : 16;
localparam CLKOUT3_DIVIDE = (PCIE_USERCLK2_FREQ == 5) ? 2 :
(PCIE_USERCLK2_FREQ == 4) ? 4 :
(PCIE_USERCLK2_FREQ == 3) ? 8 :
(PCIE_USERCLK2_FREQ == 1) ? 32 : 16;
localparam CLKOUT4_DIVIDE = 20;
localparam PCIE_GEN1_MODE = 1'b0; // PCIe link speed is GEN1 only
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg1 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_slave_reg1 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1 = 1'd0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg2 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_slave_reg2 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2 = 1'd0;
//---------- Internal Signals --------------------------
wire refclk;
wire mmcm_fb;
wire clk_125mhz;
wire clk_125mhz_buf;
wire clk_250mhz;
wire userclk1;
wire userclk2;
wire oobclk;
reg pclk_sel = 1'd0;
reg pclk_sel_slave = 1'd0;
//---------- Output Registers --------------------------
wire pclk_1;
wire pclk;
wire userclk1_1;
wire userclk2_1;
wire mmcm_lock;
//---------- Generate Per-Lane Signals -----------------
genvar i; // Index for per-lane signals
//---------- Input FF ----------------------------------------------------------
always @ (posedge pclk)
begin
if (!CLK_RST_N)
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= {PCIE_LANE{1'd0}};
pclk_sel_slave_reg1 <= {PCIE_LANE{1'd0}};
gen3_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= {PCIE_LANE{1'd0}};
pclk_sel_slave_reg2 <= {PCIE_LANE{1'd0}};
gen3_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= CLK_PCLK_SEL;
pclk_sel_slave_reg1 <= CLK_PCLK_SEL_SLAVE;
gen3_reg1 <= CLK_GEN3;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= pclk_sel_reg1;
pclk_sel_slave_reg2 <= pclk_sel_slave_reg1;
gen3_reg2 <= gen3_reg1;
end
end
/*
//---------- Select Reference clock or TXOUTCLK --------------------------------
generate if ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3))
begin : refclk_i
//---------- Select Reference Clock ----------------------------------------
BUFG refclk_i
(
//---------- Input -------------------------------------
.I (CLK_CLK),
//---------- Output ------------------------------------
.O (refclk)
);
end
else
begin : txoutclk_i
//---------- Select TXOUTCLK -----------------------------------------------
BUFG txoutclk_i
(
//---------- Input -------------------------------------
.I (CLK_TXOUTCLK),
//---------- Output ------------------------------------
.O (refclk)
);
end
endgenerate
*/
//---------- MMCM --------------------------------------------------------------
MMCME2_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (CLKOUT0_DIVIDE_F),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),
.CLKOUT4_PHASE (0.000),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT4_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (CLKIN1_PERIOD),
.REF_JITTER1 (0.010)
)
mmcm_i
(
//---------- Input ------------------------------------
.CLKIN1 (CLK_TXOUTCLK),
.CLKIN2 (1'd0), // not used, comment out CLKIN2 if it cause implementation issues
//.CLKIN2 (refclk), // not used, comment out CLKIN2 if it cause implementation issues
.CLKINSEL (1'd1),
.CLKFBIN (mmcm_fb),
.RST (!CLK_RST_N),
.PWRDWN (1'd0),
//---------- Output ------------------------------------
.CLKFBOUT (mmcm_fb),
.CLKFBOUTB (),
.CLKOUT0 (clk_125mhz),
.CLKOUT0B (),
.CLKOUT1 (clk_250mhz),
.CLKOUT1B (),
.CLKOUT2 (userclk1),
.CLKOUT2B (),
.CLKOUT3 (userclk2),
.CLKOUT3B (),
.CLKOUT4 (oobclk),
.CLKOUT5 (),
.CLKOUT6 (),
.LOCKED (mmcm_lock),
//---------- Dynamic Reconfiguration -------------------
.DCLK ( 1'd0),
.DADDR ( 7'd0),
.DEN ( 1'd0),
.DWE ( 1'd0),
.DI (16'd0),
.DO (),
.DRDY (),
//---------- Dynamic Phase Shift -----------------------
.PSCLK (1'd0),
.PSEN (1'd0),
.PSINCDEC (1'd0),
.PSDONE (),
//---------- Status ------------------------------------
.CLKINSTOPPED (),
.CLKFBSTOPPED ()
);
//---------- Select PCLK MUX ---------------------------------------------------
generate if (PCIE_LINK_SPEED != 1)
begin : pclk_i1_bufgctrl
//---------- PCLK Mux ----------------------------------
BUFGCTRL pclk_i1
(
//---------- Input ---------------------------------
.CE0 (1'd1),
.CE1 (1'd1),
.I0 (clk_125mhz),
.I1 (clk_250mhz),
.IGNORE0 (1'd0),
.IGNORE1 (1'd0),
.S0 (~pclk_sel),
.S1 ( pclk_sel),
//---------- Output --------------------------------
.O (pclk_1)
);
end
else
//---------- Select PCLK Buffer ------------------------
begin : pclk_i1_bufg
//---------- PCLK Buffer -------------------------------
BUFG pclk_i1
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (clk_125mhz_buf)
);
assign pclk_1 = clk_125mhz_buf;
end
endgenerate
//---------- Select PCLK MUX for Slave---------------------------------------------------
generate if(PCIE_CLK_SHARING_EN == "FALSE")
//---------- PCLK MUX for Slave------------------//
begin : pclk_slave_disable
assign CLK_PCLK_SLAVE = 1'b0;
end
else if (PCIE_LINK_SPEED != 1)
begin : pclk_slave_bufgctrl
//---------- PCLK Mux ----------------------------------
BUFGCTRL pclk_slave
(
//---------- Input ---------------------------------
.CE0 (1'd1),
.CE1 (1'd1),
.I0 (clk_125mhz),
.I1 (clk_250mhz),
.IGNORE0 (1'd0),
.IGNORE1 (1'd0),
.S0 (~pclk_sel_slave),
.S1 ( pclk_sel_slave),
//---------- Output --------------------------------
.O (CLK_PCLK_SLAVE)
);
end
else
//---------- Select PCLK Buffer ------------------------
begin : pclk_slave_bufg
//---------- PCLK Buffer -------------------------------
BUFG pclk_slave
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (CLK_PCLK_SLAVE)
);
end
endgenerate
//---------- Generate RXOUTCLK Buffer for Debug --------------------------------
generate if ((PCIE_DEBUG_MODE == 1) || (PCIE_ASYNC_EN == "TRUE"))
begin : rxoutclk_per_lane
//---------- Generate per Lane -------------------------
for (i=0; i<PCIE_LANE; i=i+1)
begin : rxoutclk_i
//---------- RXOUTCLK Buffer -----------------------
BUFG rxoutclk_i
(
//---------- Input -----------------------------
.I (CLK_RXOUTCLK_IN[i]),
//---------- Output ----------------------------
.O (CLK_RXOUTCLK_OUT[i])
);
end
end
else
//---------- Disable RXOUTCLK Buffer for Normal Operation
begin : rxoutclk_i_disable
assign CLK_RXOUTCLK_OUT = {PCIE_LANE{1'd0}};
end
endgenerate
//---------- Generate DCLK Buffer ----------------------------------------------
generate if (PCIE_USERCLK2_FREQ <= 3)
//---------- Disable DCLK Buffer -----------------------
begin : dclk_i
assign CLK_DCLK = userclk2_1; // always less than 125Mhz
end
else
begin : dclk_i_bufg
//---------- DCLK Buffer -------------------------------
BUFG dclk_i
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (CLK_DCLK)
);
end
endgenerate
//---------- Generate USERCLK1 Buffer ------------------------------------------
generate if (PCIE_GEN1_MODE == 1'b1 && PCIE_USERCLK1_FREQ == 3)
//---------- USERCLK1 same as PCLK -------------------
begin :userclk1_i1_no_bufg
assign userclk1_1 = pclk_1;
end
else
begin : userclk1_i1
//---------- USERCLK1 Buffer ---------------------------
BUFG usrclk1_i1
(
//---------- Input ---------------------------------
.I (userclk1),
//---------- Output --------------------------------
.O (userclk1_1)
);
end
endgenerate
//---------- Generate USERCLK2 Buffer ------------------------------------------
generate if (PCIE_GEN1_MODE == 1'b1 && PCIE_USERCLK2_FREQ == 3 )
//---------- USERCLK2 same as PCLK -------------------
begin : userclk2_i1_no_bufg0
assign userclk2_1 = pclk_1;
end
else if (PCIE_USERCLK2_FREQ == PCIE_USERCLK1_FREQ )
//---------- USERCLK2 same as USERCLK1 -------------------
begin : userclk2_i1_no_bufg1
assign userclk2_1 = userclk1_1;
end
else
begin : userclk2_i1
//---------- USERCLK2 Buffer ---------------------------
BUFG usrclk2_i1
(
//---------- Input ---------------------------------
.I (userclk2),
//---------- Output --------------------------------
.O (userclk2_1)
);
end
endgenerate
//---------- Generate OOBCLK Buffer --------------------------------------------
generate if (PCIE_OOBCLK_MODE == 2)
begin : oobclk_i1
//---------- OOBCLK Buffer -----------------------------
BUFG oobclk_i1
(
//---------- Input ---------------------------------
.I (oobclk),
//---------- Output --------------------------------
.O (CLK_OOBCLK)
);
end
else
//---------- Disable OOBCLK Buffer ---------------------
begin : oobclk_i1_disable
assign CLK_OOBCLK = pclk;
end
endgenerate
// Disabled Second Stage Buffers
assign pclk = pclk_1;
assign CLK_RXUSRCLK = pclk_1;
assign CLK_USERCLK1 = userclk1_1;
assign CLK_USERCLK2 = userclk2_1;
//---------- Select PCLK -------------------------------------------------------
always @ (posedge pclk)
begin
if (!CLK_RST_N)
pclk_sel <= 1'd0;
else
begin
//---------- Select 250 MHz ------------------------
if (&pclk_sel_reg2)
pclk_sel <= 1'd1;
//---------- Select 125 MHz ------------------------
else if (&(~pclk_sel_reg2))
pclk_sel <= 1'd0;
//---------- Hold PCLK -----------------------------
else
pclk_sel <= pclk_sel;
end
end
always @ (posedge pclk)
begin
if (!CLK_RST_N)
pclk_sel_slave<= 1'd0;
else
begin
//---------- Select 250 MHz ------------------------
if (&pclk_sel_slave_reg2)
pclk_sel_slave <= 1'd1;
//---------- Select 125 MHz ------------------------
else if (&(~pclk_sel_slave_reg2))
pclk_sel_slave <= 1'd0;
//---------- Hold PCLK -----------------------------
else
pclk_sel_slave <= pclk_sel_slave;
end
end
//---------- PIPE Clock Output -------------------------------------------------
assign CLK_PCLK = pclk;
assign CLK_MMCM_LOCK = mmcm_lock;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVP_SYMBOL_V
`define SKY130_FD_SC_HS__EINVP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVP_SYMBOL_V
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-03-2019
*/
module jt10_adpcm_cnt(
input rst_n,
input clk, // CPU clock
input cen, // 666 kHz
// pipeline channel
input [ 5:0] cur_ch,
input [ 5:0] en_ch,
// Address writes from CPU
input [15:0] addr_in,
input [ 2:0] addr_ch,
input up_start,
input up_end,
// Counter control
input aon,
input aoff,
// ROM driver
output [19:0] addr_out,
output [ 3:0] bank,
output sel,
output roe_n,
output decon,
output clr, // inform the decoder that a new section begins
// Flags
output reg [ 5:0] flags,
input [ 5:0] clr_flags,
//
output [15:0] start_top,
output [15:0] end_top
);
reg [20:0] addr1, addr2, addr3, addr4, addr5, addr6;
reg [3:0] bank1, bank2, bank3, bank4, bank5, bank6;
reg [11:0] start1, start2, start3, start4, start5, start6,
end1, end2, end3, end4, end5, end6;
reg on1, on2, on3, on4, on5, on6;
reg done5, done6, done1;
reg [5:0] done_sr, zero;
reg roe_n1, decon1;
reg clr1, clr2, clr3, clr4, clr5, clr6;
reg skip1, skip2, skip3, skip4, skip5, skip6;
// All outputs from stage 1
assign addr_out = addr1[20:1];
assign sel = addr1[0];
assign bank = bank1;
assign roe_n = roe_n1;
assign clr = clr1;
assign decon = decon1;
// Two cycles early: 0 0 1 1 2 2 3 3 4 4 5 5
wire active5 = (en_ch[1] && cur_ch[4]) || (en_ch[2] && cur_ch[5]) || (en_ch[2] && cur_ch[0]) || (en_ch[3] && cur_ch[1]) || (en_ch[4] && cur_ch[2]) || (en_ch[5] && cur_ch[3]);//{ cur_ch[3:0], cur_ch[5:4] } == en_ch;
wire sumup5 = on5 && !done5 && active5;
reg sumup6;
reg [5:0] last_done, set_flags;
always @(posedge clk or negedge rst_n)
if( !rst_n ) begin
zero <= 6'd1;
done_sr <= ~6'd0;
last_done <= ~6'd0;
end else if(cen) begin
zero <= { zero[0], zero[5:1] };
done_sr <= { done1, done_sr[5:1]};
if( zero[0] ) begin
last_done <= done_sr;
set_flags <= ~last_done & done_sr;
end
end
always @(posedge clk or negedge rst_n)
if( !rst_n ) begin
flags <= 6'd0;
end else begin
flags <= ~clr_flags & (set_flags | flags);
end
`ifdef SIMULATION
wire [11:0] addr1_cmp = addr1[20:9];
`endif
assign start_top = {bank1, start1};
assign end_top = {bank1, end1};
reg [5:0] addr_ch_dec;
always @(*)
case(addr_ch)
3'd0: addr_ch_dec = 6'b000_001;
3'd1: addr_ch_dec = 6'b000_010;
3'd2: addr_ch_dec = 6'b000_100;
3'd3: addr_ch_dec = 6'b001_000;
3'd4: addr_ch_dec = 6'b010_000;
3'd5: addr_ch_dec = 6'b100_000;
default: addr_ch_dec = 6'd0;
endcase // up_addr
wire up1 = cur_ch == addr_ch_dec;
always @(posedge clk or negedge rst_n)
if( !rst_n ) begin
addr1 <= 'd0; addr2 <= 'd0; addr3 <= 'd0;
addr4 <= 'd0; addr5 <= 'd0; addr6 <= 'd0;
done1 <= 'd1; done5 <= 'd1; done6 <= 'd1;
start1 <= 'd0; start2 <= 'd0; start3 <= 'd0;
start4 <= 'd0; start5 <= 'd0; start6 <= 'd0;
end1 <= 'd0; end2 <= 'd0; end3 <= 'd0;
end4 <= 'd0; end5 <= 'd0; end6 <= 'd0;
skip1 <= 'd0; skip2 <= 'd0; skip3 <= 'd0;
skip4 <= 'd0; skip5 <= 'd0; skip6 <= 'd0;
end else if( cen ) begin
addr2 <= addr1;
on2 <= aoff ? 1'b0 : (aon | (on1 && ~done1));
clr2 <= aoff || aon || done1; // Each time a A-ON is sent the address counter restarts
start2 <= (up_start && up1) ? addr_in[11:0] : start1;
end2 <= (up_end && up1) ? addr_in[11:0] : end1;
bank2 <= (up_start && up1) ? addr_in[15:12] : bank1;
skip2 <= skip1;
addr3 <= addr2; // clr2 ? {start2,9'd0} : addr2;
on3 <= on2;
clr3 <= clr2;
start3 <= start2;
end3 <= end2;
bank3 <= bank2;
skip3 <= skip2;
addr4 <= addr3;
on4 <= on3;
clr4 <= clr3;
start4 <= start3;
end4 <= end3;
bank4 <= bank3;
skip4 <= skip3;
addr5 <= addr4;
on5 <= on4;
clr5 <= clr4;
done5 <= addr4[20:9] == end4 && addr4[8:0]==~9'b0 && ~(clr4 && on4);
start5 <= start4;
end5 <= end4;
bank5 <= bank4;
skip5 <= skip4;
// V
addr6 <= addr5;
on6 <= on5;
clr6 <= clr5;
done6 <= done5;
start6 <= start5;
end6 <= end5;
bank6 <= bank5;
sumup6 <= sumup5;
skip6 <= skip5;
addr1 <= (clr6 && on6) ? {start6,9'd0} : (sumup6 && ~skip6 ? addr6+21'd1 :addr6);
on1 <= on6;
done1 <= done6;
start1 <= start6;
end1 <= end6;
roe_n1 <= ~sumup6;
decon1 <= sumup6;
bank1 <= bank6;
clr1 <= clr6;
skip1 <= (clr6 && on6) ? 1'b1 : sumup6 ? 1'b0 : skip6;
end
endmodule // jt10_adpcm_cnt
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3_PP_SYMBOL_V
`define SKY130_FD_SC_HS__NOR3_PP_SYMBOL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3_PP_SYMBOL_V
|
`timescale 1ns / 1ps
module top_RAM( clk, load, efect0, ledsOut,dato_ram,dir,run_efect);
input clk;
input load; //Efect3
input [15:0] dato_ram;
input run_efect;
input efect0; //Efecto fijo
//input [7:0] d;
//input esc;
output [15:0] ledsOut;
output [7:0] dir;
//wire [15:0] C;
wire rst;
wire add1;
wire reset1;
wire add2;
wire reset2;
wire top1;
wire top2;
wire clk_out;
wire new_col;
wire reset_new;
wire load_crt;
wire done_crt;
wire load_leds;
wire [2:0] vuelta;
wire [3:0] T;
impresion imp( .clk(clk),.load_leds(load_leds),.leds(dato_ram),.ledsOut(ledsOut),.T(T));
recorrido_col recol(.clk_out(clk_out),.load_crt(load_crt), .done_crt(done_crt), .dir(dir), .new_col(new_col), .reset_new(reset_new));
divisor_de_frecuecia div_fr(.rst(rst),.clk(clk),.clk_out(clk_out));
acc_1 acca (.vuelta(vuelta), .clk(clk), .add_1(add1),.reset_1(reset1));
acc_2 accb (.T(T), .clk(clk), .add_2(add2), .reset_2(reset2));
comp_1 coma (.vuelta(vuelta), .top_1(top1));
comp_2 comb (.T(T), .top_2(top2));
control_leer contr(.clk(clk),.load_e(load),.efect0(efect0),.add_1(add1),.add_2(add2),.reset_1(reset1),.reset_2(reset2),.top_1(top1),.top_2(top2),.load_crt(load_crt),.done_crt(done_crt),.new_col(new_col),.reset_new(reset_new),.load_led(load_leds),.rst(rst),.run_efect(run_efect));
// top_efect toef(.clk(clk),.load(loa),.leds(A),.ledsOut(B),.dir(dr),.leer(loadm), .Efect(efect));
endmodule
|
///////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description :
// / /
// /__/ /\ Filename : GTHE2_COMMON.uniprim.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// Initial version
// 09/22/11 - 624065 - YML update
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 06/12/12 - 664920 - YML update
// 01/18/13 - 695630 - added drp monitor
// 08/29/14 - 821138 - add negedge specify section for IS_INVERTED*CLK*
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTHE2_COMMON (
DRPDO,
DRPRDY,
PMARSVDOUT,
QPLLDMONITOR,
QPLLFBCLKLOST,
QPLLLOCK,
QPLLOUTCLK,
QPLLOUTREFCLK,
QPLLREFCLKLOST,
REFCLKOUTMONITOR,
BGBYPASSB,
BGMONITORENB,
BGPDB,
BGRCALOVRD,
BGRCALOVRDENB,
DRPADDR,
DRPCLK,
DRPDI,
DRPEN,
DRPWE,
GTGREFCLK,
GTNORTHREFCLK0,
GTNORTHREFCLK1,
GTREFCLK0,
GTREFCLK1,
GTSOUTHREFCLK0,
GTSOUTHREFCLK1,
PMARSVD,
QPLLLOCKDETCLK,
QPLLLOCKEN,
QPLLOUTRESET,
QPLLPD,
QPLLREFCLKSEL,
QPLLRESET,
QPLLRSVD1,
QPLLRSVD2,
RCALENB
);
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED";
`endif
parameter [63:0] BIAS_CFG = 64'h0000040000001000;
parameter [31:0] COMMON_CFG = 32'h0000001C;
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0;
parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0;
parameter [26:0] QPLL_CFG = 27'h0480181;
parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000;
parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000;
parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0;
parameter [9:0] QPLL_CP = 10'b0000011111;
parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0;
parameter [0:0] QPLL_DMONITOR_SEL = 1'b0;
parameter [9:0] QPLL_FBDIV = 10'b0000000000;
parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0;
parameter [0:0] QPLL_FBDIV_RATIO = 1'b0;
parameter [23:0] QPLL_INIT_CFG = 24'h000006;
parameter [15:0] QPLL_LOCK_CFG = 16'h01E8;
parameter [3:0] QPLL_LPF = 4'b1111;
parameter integer QPLL_REFCLK_DIV = 2;
parameter [0:0] QPLL_RP_COMP = 1'b0;
parameter [1:0] QPLL_VTRL_RESET = 2'b00;
parameter [1:0] RCAL_CFG = 2'b00;
parameter [15:0] RSVD_ATTR0 = 16'h0000;
parameter [15:0] RSVD_ATTR1 = 16'h0000;
parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001;
parameter SIM_RESET_SPEEDUP = "TRUE";
parameter SIM_VERSION = "1.1";
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
output DRPRDY;
output QPLLFBCLKLOST;
output QPLLLOCK;
output QPLLOUTCLK;
output QPLLOUTREFCLK;
output QPLLREFCLKLOST;
output REFCLKOUTMONITOR;
output [15:0] DRPDO;
output [15:0] PMARSVDOUT;
output [7:0] QPLLDMONITOR;
input BGBYPASSB;
input BGMONITORENB;
input BGPDB;
input BGRCALOVRDENB;
input DRPCLK;
input DRPEN;
input DRPWE;
input GTGREFCLK;
input GTNORTHREFCLK0;
input GTNORTHREFCLK1;
input GTREFCLK0;
input GTREFCLK1;
input GTSOUTHREFCLK0;
input GTSOUTHREFCLK1;
input QPLLLOCKDETCLK;
input QPLLLOCKEN;
input QPLLOUTRESET;
input QPLLPD;
input QPLLRESET;
input RCALENB;
input [15:0] DRPDI;
input [15:0] QPLLRSVD1;
input [2:0] QPLLREFCLKSEL;
input [4:0] BGRCALOVRD;
input [4:0] QPLLRSVD2;
input [7:0] DRPADDR;
input [7:0] PMARSVD;
reg SIM_RESET_SPEEDUP_BINARY;
reg SIM_VERSION_BINARY;
reg [0:0] QPLL_COARSE_FREQ_OVRD_EN_BINARY;
reg [0:0] QPLL_CP_MONITOR_EN_BINARY;
reg [0:0] QPLL_DMONITOR_SEL_BINARY;
reg [0:0] QPLL_FBDIV_MONITOR_EN_BINARY;
reg [0:0] QPLL_FBDIV_RATIO_BINARY;
reg [0:0] QPLL_RP_COMP_BINARY;
reg [1:0] QPLL_VTRL_RESET_BINARY;
reg [1:0] RCAL_CFG_BINARY;
reg [2:0] SIM_QPLLREFCLK_SEL_BINARY;
reg [3:0] QPLL_CLKOUT_CFG_BINARY;
reg [3:0] QPLL_LPF_BINARY;
reg [4:0] QPLL_REFCLK_DIV_BINARY;
reg [5:0] QPLL_COARSE_FREQ_OVRD_BINARY;
reg [9:0] QPLL_CP_BINARY;
reg [9:0] QPLL_FBDIV_BINARY;
tri0 GSR = glbl.GSR;
reg notifier;
initial begin
case (QPLL_REFCLK_DIV)
2 : QPLL_REFCLK_DIV_BINARY = 5'b00000;
1 : QPLL_REFCLK_DIV_BINARY = 5'b10000;
3 : QPLL_REFCLK_DIV_BINARY = 5'b00001;
4 : QPLL_REFCLK_DIV_BINARY = 5'b00010;
5 : QPLL_REFCLK_DIV_BINARY = 5'b00011;
6 : QPLL_REFCLK_DIV_BINARY = 5'b00101;
8 : QPLL_REFCLK_DIV_BINARY = 5'b00110;
10 : QPLL_REFCLK_DIV_BINARY = 5'b00111;
12 : QPLL_REFCLK_DIV_BINARY = 5'b01101;
16 : QPLL_REFCLK_DIV_BINARY = 5'b01110;
20 : QPLL_REFCLK_DIV_BINARY = 5'b01111;
default : begin
$display("Attribute Syntax Error : The Attribute QPLL_REFCLK_DIV on GTHE2_COMMON instance %m is set to %d. Legal values for this attribute are 1 to 20.", QPLL_REFCLK_DIV, 2);
#1 $finish;
end
endcase
case (SIM_RESET_SPEEDUP)
"TRUE" : SIM_RESET_SPEEDUP_BINARY = 0;
"FALSE" : SIM_RESET_SPEEDUP_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_RESET_SPEEDUP on GTHE2_COMMON instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", SIM_RESET_SPEEDUP);
#1 $finish;
end
endcase
case (SIM_VERSION)
"1.1" : SIM_VERSION_BINARY = 0;
"1.0" : SIM_VERSION_BINARY = 0;
"2.0" : SIM_VERSION_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_VERSION on GTHE2_CHANNEL instance %m is set to %s. Legal values for this attribute are 1.1, 1.0, or 2.0.", SIM_VERSION);
#1 $finish;
end
endcase
if ((QPLL_CLKOUT_CFG >= 4'b0000) && (QPLL_CLKOUT_CFG <= 4'b1111))
QPLL_CLKOUT_CFG_BINARY = QPLL_CLKOUT_CFG;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_CLKOUT_CFG on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", QPLL_CLKOUT_CFG);
#1 $finish;
end
if ((QPLL_COARSE_FREQ_OVRD >= 6'b000000) && (QPLL_COARSE_FREQ_OVRD <= 6'b111111))
QPLL_COARSE_FREQ_OVRD_BINARY = QPLL_COARSE_FREQ_OVRD;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_COARSE_FREQ_OVRD on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111.", QPLL_COARSE_FREQ_OVRD);
#1 $finish;
end
if ((QPLL_COARSE_FREQ_OVRD_EN >= 1'b0) && (QPLL_COARSE_FREQ_OVRD_EN <= 1'b1))
QPLL_COARSE_FREQ_OVRD_EN_BINARY = QPLL_COARSE_FREQ_OVRD_EN;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_COARSE_FREQ_OVRD_EN on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_COARSE_FREQ_OVRD_EN);
#1 $finish;
end
if ((QPLL_CP >= 10'b0000000000) && (QPLL_CP <= 10'b1111111111))
QPLL_CP_BINARY = QPLL_CP;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_CP on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", QPLL_CP);
#1 $finish;
end
if ((QPLL_CP_MONITOR_EN >= 1'b0) && (QPLL_CP_MONITOR_EN <= 1'b1))
QPLL_CP_MONITOR_EN_BINARY = QPLL_CP_MONITOR_EN;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_CP_MONITOR_EN on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_CP_MONITOR_EN);
#1 $finish;
end
if ((QPLL_DMONITOR_SEL >= 1'b0) && (QPLL_DMONITOR_SEL <= 1'b1))
QPLL_DMONITOR_SEL_BINARY = QPLL_DMONITOR_SEL;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_DMONITOR_SEL on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_DMONITOR_SEL);
#1 $finish;
end
if ((QPLL_FBDIV >= 10'b0000000000) && (QPLL_FBDIV <= 10'b1111111111))
QPLL_FBDIV_BINARY = QPLL_FBDIV;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_FBDIV on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111.", QPLL_FBDIV);
#1 $finish;
end
if ((QPLL_FBDIV_MONITOR_EN >= 1'b0) && (QPLL_FBDIV_MONITOR_EN <= 1'b1))
QPLL_FBDIV_MONITOR_EN_BINARY = QPLL_FBDIV_MONITOR_EN;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_FBDIV_MONITOR_EN on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_FBDIV_MONITOR_EN);
#1 $finish;
end
if ((QPLL_FBDIV_RATIO >= 1'b0) && (QPLL_FBDIV_RATIO <= 1'b1))
QPLL_FBDIV_RATIO_BINARY = QPLL_FBDIV_RATIO;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_FBDIV_RATIO on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_FBDIV_RATIO);
#1 $finish;
end
if ((QPLL_LPF >= 4'b0000) && (QPLL_LPF <= 4'b1111))
QPLL_LPF_BINARY = QPLL_LPF;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_LPF on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111.", QPLL_LPF);
#1 $finish;
end
if ((QPLL_RP_COMP >= 1'b0) && (QPLL_RP_COMP <= 1'b1))
QPLL_RP_COMP_BINARY = QPLL_RP_COMP;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_RP_COMP on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", QPLL_RP_COMP);
#1 $finish;
end
if ((QPLL_VTRL_RESET >= 2'b00) && (QPLL_VTRL_RESET <= 2'b11))
QPLL_VTRL_RESET_BINARY = QPLL_VTRL_RESET;
else begin
$display("Attribute Syntax Error : The Attribute QPLL_VTRL_RESET on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", QPLL_VTRL_RESET);
#1 $finish;
end
if ((RCAL_CFG >= 2'b00) && (RCAL_CFG <= 2'b11))
RCAL_CFG_BINARY = RCAL_CFG;
else begin
$display("Attribute Syntax Error : The Attribute RCAL_CFG on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 2'b00 to 2'b11.", RCAL_CFG);
#1 $finish;
end
if ((SIM_QPLLREFCLK_SEL >= 3'b0) && (SIM_QPLLREFCLK_SEL <= 3'b111))
SIM_QPLLREFCLK_SEL_BINARY = SIM_QPLLREFCLK_SEL;
else begin
$display("Attribute Syntax Error : The Attribute SIM_QPLLREFCLK_SEL on GTHE2_COMMON instance %m is set to %b. Legal values for this attribute are 3'b0 to 3'b111.", SIM_QPLLREFCLK_SEL);
#1 $finish;
end
end
wire [15:0] delay_DRPDO;
wire [15:0] delay_PMARSVDOUT;
wire [7:0] delay_QPLLDMONITOR;
wire delay_DRPRDY;
wire delay_QPLLFBCLKLOST;
wire delay_QPLLLOCK;
wire delay_QPLLOUTCLK;
wire delay_QPLLOUTREFCLK;
wire delay_QPLLREFCLKLOST;
wire delay_REFCLKOUTMONITOR;
wire [15:0] delay_DRPDI;
wire [15:0] delay_QPLLRSVD1;
wire [2:0] delay_QPLLREFCLKSEL;
wire [4:0] delay_BGRCALOVRD;
wire [4:0] delay_QPLLRSVD2;
wire [7:0] delay_DRPADDR;
wire [7:0] delay_PMARSVD;
wire delay_BGBYPASSB;
wire delay_BGMONITORENB;
wire delay_BGPDB;
wire delay_BGRCALOVRDENB;
wire delay_DRPCLK;
wire delay_DRPEN;
wire delay_DRPWE;
wire delay_GTGREFCLK;
wire delay_GTNORTHREFCLK0;
wire delay_GTNORTHREFCLK1;
wire delay_GTREFCLK0;
wire delay_GTREFCLK1;
wire delay_GTSOUTHREFCLK0;
wire delay_GTSOUTHREFCLK1;
wire delay_QPLLLOCKDETCLK;
wire delay_QPLLLOCKEN;
wire delay_QPLLOUTRESET;
wire delay_QPLLPD;
wire delay_QPLLRESET;
wire delay_RCALENB;
//drp monitor
reg drpen_r1 = 1'b0;
reg drpen_r2 = 1'b0;
reg drpwe_r1 = 1'b0;
reg drpwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge delay_DRPCLK)
begin
// pipeline the DRPEN and DRPWE
drpen_r1 <= delay_DRPEN;
drpwe_r1 <= delay_DRPWE;
drpen_r2 <= drpen_r1;
drpwe_r2 <= drpwe_r1;
// Check - if DRPEN or DRPWE is more than 1 DCLK
if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1))
begin
$display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance");
$finish;
end
if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1))
begin
$display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance");
$finish;
end
//After the 1st DRPEN pulse, check the DRPEN and DRPRDY.
case (sfsm)
FSM_IDLE:
begin
if(delay_DRPEN == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DRPEN, 4 cases can happen
// DRPEN DRPRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRPRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRPRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0)
begin
$display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance");
$finish;
end
//Add the check for another DRPWE pulse
if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0))
begin
$display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance");
$finish;
end
if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM.");
$finish;
end
endcase
end // always @ (posedge delay_DRPCLK)
//end drp monitor
reg [0:0] IS_DRPCLK_INVERTED_REG = IS_DRPCLK_INVERTED;
reg [0:0] IS_GTGREFCLK_INVERTED_REG = IS_GTGREFCLK_INVERTED;
reg [0:0] IS_QPLLLOCKDETCLK_INVERTED_REG = IS_QPLLLOCKDETCLK_INVERTED;
assign QPLLOUTCLK = delay_QPLLOUTCLK;
assign REFCLKOUTMONITOR = delay_REFCLKOUTMONITOR;
assign DRPDO = delay_DRPDO;
assign DRPRDY = delay_DRPRDY;
assign PMARSVDOUT = delay_PMARSVDOUT;
assign QPLLDMONITOR = delay_QPLLDMONITOR;
assign QPLLFBCLKLOST = delay_QPLLFBCLKLOST;
assign QPLLLOCK = delay_QPLLLOCK;
assign QPLLOUTREFCLK = delay_QPLLOUTREFCLK;
assign QPLLREFCLKLOST = delay_QPLLREFCLKLOST;
`ifndef XIL_TIMING // unisim
assign delay_DRPCLK = DRPCLK ^ IS_DRPCLK_INVERTED_REG;
assign delay_GTGREFCLK = GTGREFCLK ^ IS_GTGREFCLK_INVERTED_REG;
assign delay_GTNORTHREFCLK0 = GTNORTHREFCLK0;
assign delay_GTNORTHREFCLK1 = GTNORTHREFCLK1;
assign delay_GTREFCLK0 = GTREFCLK0;
assign delay_GTREFCLK1 = GTREFCLK1;
assign delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0;
assign delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1;
assign delay_QPLLLOCKDETCLK = QPLLLOCKDETCLK ^ IS_QPLLLOCKDETCLK_INVERTED_REG;
assign delay_BGBYPASSB = BGBYPASSB;
assign delay_BGMONITORENB = BGMONITORENB;
assign delay_BGPDB = BGPDB;
assign delay_BGRCALOVRD = BGRCALOVRD;
assign delay_BGRCALOVRDENB = BGRCALOVRDENB;
assign delay_DRPADDR = DRPADDR;
assign delay_DRPDI = DRPDI;
assign delay_DRPEN = DRPEN;
assign delay_DRPWE = DRPWE;
assign delay_PMARSVD = PMARSVD;
assign delay_QPLLLOCKEN = QPLLLOCKEN;
assign delay_QPLLOUTRESET = QPLLOUTRESET;
assign delay_QPLLPD = QPLLPD;
assign delay_QPLLREFCLKSEL = QPLLREFCLKSEL;
assign delay_QPLLRESET = QPLLRESET;
assign delay_QPLLRSVD1 = QPLLRSVD1;
assign delay_QPLLRSVD2 = QPLLRSVD2;
assign delay_RCALENB = RCALENB;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING //Simprim
assign delay_BGBYPASSB = BGBYPASSB;
assign delay_BGMONITORENB = BGMONITORENB;
assign delay_BGPDB = BGPDB;
assign delay_BGRCALOVRD = BGRCALOVRD;
assign delay_BGRCALOVRDENB = BGRCALOVRDENB;
assign delay_GTGREFCLK = GTGREFCLK;
assign delay_GTNORTHREFCLK0 = GTNORTHREFCLK0;
assign delay_GTNORTHREFCLK1 = GTNORTHREFCLK1;
assign delay_GTREFCLK0 = GTREFCLK0;
assign delay_GTREFCLK1 = GTREFCLK1;
assign delay_GTSOUTHREFCLK0 = GTSOUTHREFCLK0;
assign delay_GTSOUTHREFCLK1 = GTSOUTHREFCLK1;
assign delay_PMARSVD = PMARSVD;
assign delay_QPLLLOCKDETCLK = QPLLLOCKDETCLK;
assign delay_QPLLLOCKEN = QPLLLOCKEN;
assign delay_QPLLOUTRESET = QPLLOUTRESET;
assign delay_QPLLPD = QPLLPD;
assign delay_QPLLREFCLKSEL = QPLLREFCLKSEL;
assign delay_QPLLRESET = QPLLRESET;
assign delay_QPLLRSVD1 = QPLLRSVD1;
assign delay_QPLLRSVD2 = QPLLRSVD2;
assign delay_RCALENB = RCALENB;
wire drpclk_en_p;
wire drpclk_en_n;
assign drpclk_en_p = ~IS_DRPCLK_INVERTED;
assign drpclk_en_n = IS_DRPCLK_INVERTED;
`endif
B_GTHE2_COMMON #(
.BIAS_CFG (BIAS_CFG),
.COMMON_CFG (COMMON_CFG),
.QPLL_CFG (QPLL_CFG),
.QPLL_CLKOUT_CFG (QPLL_CLKOUT_CFG),
.QPLL_COARSE_FREQ_OVRD (QPLL_COARSE_FREQ_OVRD),
.QPLL_COARSE_FREQ_OVRD_EN (QPLL_COARSE_FREQ_OVRD_EN),
.QPLL_CP (QPLL_CP),
.QPLL_CP_MONITOR_EN (QPLL_CP_MONITOR_EN),
.QPLL_DMONITOR_SEL (QPLL_DMONITOR_SEL),
.QPLL_FBDIV (QPLL_FBDIV),
.QPLL_FBDIV_MONITOR_EN (QPLL_FBDIV_MONITOR_EN),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (QPLL_INIT_CFG),
.QPLL_LOCK_CFG (QPLL_LOCK_CFG),
.QPLL_LPF (QPLL_LPF),
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL_RP_COMP (QPLL_RP_COMP),
.QPLL_VTRL_RESET (QPLL_VTRL_RESET),
.RCAL_CFG (RCAL_CFG),
.RSVD_ATTR0 (RSVD_ATTR0),
.RSVD_ATTR1 (RSVD_ATTR1),
.SIM_QPLLREFCLK_SEL (SIM_QPLLREFCLK_SEL),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP),
.SIM_VERSION (SIM_VERSION))
B_GTHE2_COMMON_INST (
.DRPDO (delay_DRPDO),
.DRPRDY (delay_DRPRDY),
.PMARSVDOUT (delay_PMARSVDOUT),
.QPLLDMONITOR (delay_QPLLDMONITOR),
.QPLLFBCLKLOST (delay_QPLLFBCLKLOST),
.QPLLLOCK (delay_QPLLLOCK),
.QPLLOUTCLK (delay_QPLLOUTCLK),
.QPLLOUTREFCLK (delay_QPLLOUTREFCLK),
.QPLLREFCLKLOST (delay_QPLLREFCLKLOST),
.REFCLKOUTMONITOR (delay_REFCLKOUTMONITOR),
.BGBYPASSB (delay_BGBYPASSB),
.BGMONITORENB (delay_BGMONITORENB),
.BGPDB (delay_BGPDB),
.BGRCALOVRD (delay_BGRCALOVRD),
.BGRCALOVRDENB (delay_BGRCALOVRDENB),
.DRPADDR (delay_DRPADDR),
.DRPCLK (delay_DRPCLK),
.DRPDI (delay_DRPDI),
.DRPEN (delay_DRPEN),
.DRPWE (delay_DRPWE),
.GTGREFCLK (delay_GTGREFCLK),
.GTNORTHREFCLK0 (delay_GTNORTHREFCLK0),
.GTNORTHREFCLK1 (delay_GTNORTHREFCLK1),
.GTREFCLK0 (delay_GTREFCLK0),
.GTREFCLK1 (delay_GTREFCLK1),
.GTSOUTHREFCLK0 (delay_GTSOUTHREFCLK0),
.GTSOUTHREFCLK1 (delay_GTSOUTHREFCLK1),
.PMARSVD (delay_PMARSVD),
.QPLLLOCKDETCLK (delay_QPLLLOCKDETCLK),
.QPLLLOCKEN (delay_QPLLLOCKEN),
.QPLLOUTRESET (delay_QPLLOUTRESET),
.QPLLPD (delay_QPLLPD),
.QPLLREFCLKSEL (delay_QPLLREFCLKSEL),
.QPLLRESET (delay_QPLLRESET),
.QPLLRSVD1 (delay_QPLLRSVD1),
.QPLLRSVD2 (delay_QPLLRSVD2),
.RCALENB (delay_RCALENB),
.GSR(GSR)
);
specify
`ifdef XIL_TIMING // Simprim
$period (posedge DRPCLK, 0:0:0, notifier);
$period (negedge DRPCLK, 0:0:0, notifier);
$period (posedge GTGREFCLK, 0:0:0, notifier);
$period (negedge GTGREFCLK, 0:0:0, notifier);
$period (posedge GTNORTHREFCLK0, 0:0:0, notifier);
$period (posedge GTNORTHREFCLK1, 0:0:0, notifier);
$period (posedge GTREFCLK0, 0:0:0, notifier);
$period (posedge GTREFCLK1, 0:0:0, notifier);
$period (posedge GTSOUTHREFCLK0, 0:0:0, notifier);
$period (posedge GTSOUTHREFCLK1, 0:0:0, notifier);
$period (posedge QPLLLOCKDETCLK, 0:0:0, notifier);
$period (negedge QPLLLOCKDETCLK, 0:0:0, notifier);
$period (posedge QPLLOUTCLK, 0:0:0, notifier);
$period (posedge REFCLKOUTMONITOR, 0:0:0, notifier);
$setuphold (posedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPADDR);
$setuphold (posedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPDI);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_p, drpclk_en_p, delay_DRPCLK, delay_DRPWE);
$setuphold (negedge DRPCLK, negedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR);
$setuphold (negedge DRPCLK, negedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI);
$setuphold (negedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN);
$setuphold (negedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE);
$setuphold (negedge DRPCLK, posedge DRPADDR, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPADDR);
$setuphold (negedge DRPCLK, posedge DRPDI, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPDI);
$setuphold (negedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPEN);
$setuphold (negedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, drpclk_en_n, drpclk_en_n, delay_DRPCLK, delay_DRPWE);
`endif
( DRPCLK *> DRPDO) = (0, 0);
( DRPCLK *> DRPRDY) = (0, 0);
( GTGREFCLK *> REFCLKOUTMONITOR) = (0, 0);
( GTNORTHREFCLK0 *> REFCLKOUTMONITOR) = (0, 0);
( GTNORTHREFCLK1 *> REFCLKOUTMONITOR) = (0, 0);
( GTREFCLK0 *> REFCLKOUTMONITOR) = (0, 0);
( GTREFCLK1 *> REFCLKOUTMONITOR) = (0, 0);
( GTSOUTHREFCLK0 *> REFCLKOUTMONITOR) = (0, 0);
( GTSOUTHREFCLK1 *> REFCLKOUTMONITOR) = (0, 0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31AI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__O31AI_PP_BLACKBOX_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o31ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31AI_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3B_TB_V
`define SKY130_FD_SC_LS__AND3B_TB_V
/**
* and3b: 3-input AND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and3b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A_N = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A_N = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A_N = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A_N = 1'bx;
end
sky130_fd_sc_ls__and3b dut (.A_N(A_N), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3B_TB_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_pc_2 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [1 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [1 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [1 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [1 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(2),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(2'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(2'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(2'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O31AI_FUNCTIONAL_PP_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o31ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31AI_FUNCTIONAL_PP_V |
`define NULL 0
`timescale 1ns / 1 ps
module rc_pcs_top (
// Common for all 4 Channels
// Resets
input wire ffc_lane_tx_rst,
input wire ffc_lane_rx_rst,
input wire ffc_trst,
input wire ffc_quad_rst,
input wire ffc_macro_rst,
// Clocks
input wire refclkp,
input wire refclkn,
input wire PCLK,
`ifdef ECP3
`ifdef Channel_0
output wire ff_tx_f_clk_0,
output wire ff_tx_h_clk_0,
`endif
`ifdef Channel_1
output wire ff_tx_f_clk_1,
output wire ff_tx_h_clk_1,
`endif
`ifdef Channel_2
output wire ff_tx_f_clk_2,
output wire ff_tx_h_clk_2,
`endif
`ifdef Channel_3
output wire ff_tx_f_clk_3,
output wire ff_tx_h_clk_3,
`endif
`else
output wire ff_tx_f_clk,
output wire ff_tx_h_clk,
`endif
input wire ffc_signal_detect,
input wire ffc_enb_cgalign,
output wire ffs_plol,
// SCI Interface
input wire sciwstn,
input wire [7:0] sciwritedata,
input wire [5:0] sciaddress,
input wire scienaux,
input wire sciselaux,
input wire scird,
output wire [7:0] scireaddata,
`ifdef Channel_0
input wire hdinp0,
input wire hdinn0,
input wire [7:0] TxData_ch0,
input wire TxDataK_ch0,
input wire TxCompliance_ch0,
input wire TxElecIdle_ch0,
input wire ffc_txpwdnb_0,
input wire ffc_rxpwdnb_0,
input wire ffc_rrst_ch0,
input wire ffc_pcie_ct_ch0,
input wire ffc_pcie_det_en_ch0,
input wire ffc_fb_loopback_ch0,
input wire RxPolarity_ch0,
input wire scisel_ch0,
input wire scien_ch0,
output wire ff_rx_fclk_ch0,
output wire hdoutp0,
output wire hdoutn0,
output wire [7:0] RxData_ch0,
output wire RxDataK_ch0,
output wire [2:0] RxStatus_ch0,
output wire RxValid_ch0,
output wire RxElecIdle_ch0,
output wire ffs_rlol_ch0,
output wire ffs_pcie_done_0,
output wire ffs_pcie_con_0,
`endif
`ifdef Channel_1
input wire hdinp1,
input wire hdinn1,
input wire [7:0] TxData_ch1,
input wire TxDataK_ch1,
input wire TxCompliance_ch1,
input wire TxElecIdle_ch1,
input wire ffc_txpwdnb_1,
input wire ffc_rxpwdnb_1,
input wire ffc_rrst_ch1,
input wire ffc_pcie_ct_ch1,
input wire ffc_pcie_det_en_ch1,
input wire ffc_fb_loopback_ch1,
input wire RxPolarity_ch1,
input wire scisel_ch1,
input wire scien_ch1,
output wire ff_rx_fclk_ch1,
output wire hdoutp1,
output wire hdoutn1,
output wire [7:0] RxData_ch1,
output wire RxDataK_ch1,
output wire [2:0] RxStatus_ch1,
output wire RxValid_ch1,
output wire RxElecIdle_ch1,
output wire ffs_rlol_ch1,
output wire ffs_pcie_done_1,
output wire ffs_pcie_con_1,
`endif
`ifdef Channel_2
input wire hdinp2,
input wire hdinn2,
input wire [7:0] TxData_ch2,
input wire TxDataK_ch2,
input wire TxCompliance_ch2,
input wire TxElecIdle_ch2,
input wire ffc_txpwdnb_2,
input wire ffc_rxpwdnb_2,
input wire ffc_rrst_ch2,
input wire ffc_pcie_ct_ch2,
input wire ffc_pcie_det_en_ch2,
input wire ffc_fb_loopback_ch2,
input wire RxPolarity_ch2,
input wire scisel_ch2,
input wire scien_ch2,
output wire ff_rx_fclk_ch2,
output wire hdoutp2,
output wire hdoutn2,
output wire [7:0] RxData_ch2,
output wire RxDataK_ch2,
output wire [2:0] RxStatus_ch2,
output wire RxValid_ch2,
output wire RxElecIdle_ch2,
output wire ffs_rlol_ch2,
output wire ffs_pcie_done_2,
output wire ffs_pcie_con_2,
`endif
`ifdef Channel_3
input wire hdinp3,
input wire hdinn3,
input wire [7:0] TxData_ch3,
input wire TxDataK_ch3,
input wire TxCompliance_ch3,
input wire TxElecIdle_ch3,
input wire ffc_txpwdnb_3,
input wire ffc_rxpwdnb_3,
input wire ffc_rrst_ch3,
input wire ffc_pcie_ct_ch3,
input wire ffc_pcie_det_en_ch3,
input wire ffc_fb_loopback_ch3,
input wire RxPolarity_ch3,
input wire scisel_ch3,
input wire scien_ch3,
output wire ff_rx_fclk_ch3,
output wire hdoutp3,
output wire hdoutn3,
output wire [7:0] RxData_ch3,
output wire RxDataK_ch3,
output wire [2:0] RxStatus_ch3,
output wire RxValid_ch3,
output wire RxElecIdle_ch3,
output wire ffs_rlol_ch3,
output wire ffs_pcie_done_3,
output wire ffs_pcie_con_3,
`endif
input wire [11:0] cin,
output wire [19:0] cout
) ;
// =============================================================================
//synopsys translate_off
`ifdef ECP3
`ifdef X1
parameter USER_CONFIG_FILE = "pcs_pipe_8b_x1.txt";
`else
parameter USER_CONFIG_FILE = "pcs_pipe_8b_x4.txt";
`endif
parameter QUAD_MODE = "SINGLE";
parameter PLL_SRC = "REFCLK_EXT";
parameter CH0_CDR_SRC = "REFCLK_EXT";
parameter CH1_CDR_SRC = "REFCLK_EXT";
parameter CH2_CDR_SRC = "REFCLK_EXT";
parameter CH3_CDR_SRC = "REFCLK_EXT";
defparam pcs_inst_0.CONFIG_FILE = USER_CONFIG_FILE;
defparam pcs_inst_0.QUAD_MODE = QUAD_MODE;
defparam pcs_inst_0.PLL_SRC = PLL_SRC;
defparam pcs_inst_0.CH0_CDR_SRC = CH0_CDR_SRC;
defparam pcs_inst_0.CH1_CDR_SRC = CH1_CDR_SRC;
defparam pcs_inst_0.CH2_CDR_SRC = CH2_CDR_SRC;
defparam pcs_inst_0.CH3_CDR_SRC = CH3_CDR_SRC;
`else
`ifdef X1
parameter USER_CONFIG_FILE = "pcs_pipe_8b_x1.txt";
defparam pcs_inst_0.CONFIG_FILE = USER_CONFIG_FILE;
`else
parameter USER_CONFIG_FILE = "pcs_pipe_8b_x4.txt";
defparam pcs_inst_0.CONFIG_FILE = USER_CONFIG_FILE;
`endif
`endif
integer file, r;
initial begin
file = $fopen(USER_CONFIG_FILE, "r");
if (file == `NULL) begin
$display ("ERROR : Auto configuration file for PCSC module not found.");
$display (" : PCSC internal configuration registers will not be ");
$display (" : initialized correctly during simulation!");
end
end
//synopsys translate_on
// =============================================================================
// Wires
// =============================================================================
wire pcs_refclkp, pcs_refclkn, pcs_PCLK ;
wire pcs_ffc_lane_tx_rst, pcs_ffc_lane_rx_rst ;
wire pcs_ffc_macro_rst, pcs_ffc_quad_rst, pcs_ffc_trst ;
`ifdef ECP3
wire pcs_ff_tx_f_clk_0, pcs_ff_tx_h_clk_0;
wire pcs_ff_tx_f_clk_1, pcs_ff_tx_h_clk_1;
wire pcs_ff_tx_f_clk_2, pcs_ff_tx_h_clk_2;
wire pcs_ff_tx_f_clk_3, pcs_ff_tx_h_clk_3;
`else
wire pcs_ff_tx_f_clk, pcs_ff_tx_h_clk;
`endif
wire pcs_ffc_signal_detect, pcs_ffc_enb_cgalign, pcs_ffs_plol ;
// SCI
wire [7:0] pcs_sciwritedata, pcs_scireaddata ;
wire [5:0] pcs_sciaddress ;
wire pcs_scienaux, pcs_sciselaux, pcs_scird, pcs_sciwstn ;
//CH0/CH1/CH2/CH3
wire pcs_hdinp0, pcs_hdinp1, pcs_hdinp2, pcs_hdinp3 ;
wire pcs_hdinn0, pcs_hdinn1, pcs_hdinn2, pcs_hdinn3 ;
wire pcs_hdoutp0, pcs_hdoutp1, pcs_hdoutp2, pcs_hdoutp3 ;
wire pcs_hdoutn0, pcs_hdoutn1, pcs_hdoutn2, pcs_hdoutn3 ;
wire pcs_scisel_ch0, pcs_scisel_ch1, pcs_scisel_ch2, pcs_scisel_ch3 ;
wire pcs_scien_ch0, pcs_scien_ch1, pcs_scien_ch2, pcs_scien_ch3 ;
wire pcs_ff_rx_fclk_ch0, pcs_ff_rx_fclk_ch1, pcs_ff_rx_fclk_ch2, pcs_ff_rx_fclk_ch3 ;
wire [7:0] pcs_TxData_ch0, pcs_TxData_ch1,pcs_TxData_ch2,pcs_TxData_ch3 ;
wire pcs_TxDataK_ch0, pcs_TxDataK_ch1, pcs_TxDataK_ch2, pcs_TxDataK_ch3 ;
wire pcs_TxCompliance_ch0, pcs_TxCompliance_ch1, pcs_TxCompliance_ch2, pcs_TxCompliance_ch3 ;
wire pcs_TxElecIdle_ch0, pcs_TxElecIdle_ch1, pcs_TxElecIdle_ch2, pcs_TxElecIdle_ch3 ;
wire [7:0] pcs_RxData_ch0, pcs_RxData_ch1, pcs_RxData_ch2, pcs_RxData_ch3 ;
wire pcs_RxDataK_ch0, pcs_RxDataK_ch1, pcs_RxDataK_ch2, pcs_RxDataK_ch3 ;
wire [2:0] pcs_RxStatus_ch0, pcs_RxStatus_ch1, pcs_RxStatus_ch2, pcs_RxStatus_ch3 ;
wire pcs_ffc_rrst_ch0, pcs_ffc_rrst_ch1, pcs_ffc_rrst_ch2, pcs_ffc_rrst_ch3 ;
wire pcs_ffc_fb_loopback_ch0, pcs_ffc_fb_loopback_ch1, pcs_ffc_fb_loopback_ch2, pcs_ffc_fb_loopback_ch3;
wire pcs_RxPolarity_ch0, pcs_RxPolarity_ch1, pcs_RxPolarity_ch2, pcs_RxPolarity_ch3 ;
wire pcs_ffc_pcie_ct_ch0, pcs_ffc_pcie_ct_ch1, pcs_ffc_pcie_ct_ch2, pcs_ffc_pcie_ct_ch3 ;
wire pcs_ffc_pcie_det_en_ch0, pcs_ffc_pcie_det_en_ch1, pcs_ffc_pcie_det_en_ch2, pcs_ffc_pcie_det_en_ch3 ;
wire pcs_ffs_pcie_done_0, pcs_ffs_pcie_done_1, pcs_ffs_pcie_done_2, pcs_ffs_pcie_done_3 ;
wire pcs_ffs_pcie_con_0, pcs_ffs_pcie_con_1, pcs_ffs_pcie_con_2, pcs_ffs_pcie_con_3 ;
wire pcs_ffc_txpwdnb_0, pcs_ffc_txpwdnb_1, pcs_ffc_txpwdnb_2, pcs_ffc_txpwdnb_3 ;
wire pcs_ffc_rxpwdnb_0, pcs_ffc_rxpwdnb_1, pcs_ffc_rxpwdnb_2, pcs_ffc_rxpwdnb_3 ;
wire pcs_RxElecIdle_ch0, pcs_RxElecIdle_ch1, pcs_RxElecIdle_ch2, pcs_RxElecIdle_ch3 ;
wire pcs_RxValid_ch0, pcs_RxValid_ch1, pcs_RxValid_ch2, pcs_RxValid_ch3 ;
wire pcs_ffs_rlol_ch0 ,pcs_ffs_rlol_ch1, pcs_ffs_rlol_ch2, pcs_ffs_rlol_ch3 ;
wire [11:0] pcs_cin ;
wire [19:0] pcs_cout ;
// =============================================================================
// PCS Connections
// =============================================================================
// Inputs
assign pcs_refclkp = refclkp ;
assign pcs_refclkn = refclkn ;
assign pcs_PCLK = PCLK ;
assign pcs_ffc_lane_tx_rst = ffc_lane_tx_rst;
assign pcs_ffc_lane_rx_rst = ffc_lane_rx_rst;
assign pcs_ffc_macro_rst = ffc_macro_rst;
assign pcs_ffc_quad_rst = ffc_quad_rst;
assign pcs_ffc_trst = ffc_trst;
assign pcs_ffc_signal_detect = ffc_signal_detect;
assign pcs_ffc_enb_cgalign = ffc_enb_cgalign;
assign pcs_sciwritedata = sciwritedata;
assign pcs_sciaddress = sciaddress;
assign pcs_scienaux = scienaux;
assign pcs_sciselaux = sciselaux;
assign pcs_scird = scird;
assign pcs_sciwstn = sciwstn;
assign pcs_cin = cin;
// Outputs
`ifdef ECP3
`ifdef Channel_0
assign ff_tx_f_clk_0 = pcs_ff_tx_f_clk_0;
assign ff_tx_h_clk_0 = pcs_ff_tx_h_clk_0;
`endif
`ifdef Channel_1
assign ff_tx_f_clk_1 = pcs_ff_tx_f_clk_1;
assign ff_tx_h_clk_1 = pcs_ff_tx_h_clk_1;
`endif
`ifdef Channel_2
assign ff_tx_f_clk_2 = pcs_ff_tx_f_clk_2;
assign ff_tx_h_clk_2 = pcs_ff_tx_h_clk_2;
`endif
`ifdef Channel_3
assign ff_tx_f_clk_3 = pcs_ff_tx_f_clk_3;
assign ff_tx_h_clk_3 = pcs_ff_tx_h_clk_3;
`endif
`else
assign ff_tx_f_clk = pcs_ff_tx_f_clk;
assign ff_tx_h_clk = pcs_ff_tx_h_clk;
`endif
assign ffs_plol = pcs_ffs_plol;
assign scireaddata = pcs_scireaddata;
assign cout = pcs_cout;
// ========================================================
`ifdef Channel_0
// Inputs
assign pcs_hdinp0 = hdinp0 ;
assign pcs_hdinn0 = hdinn0 ;
assign pcs_TxData_ch0 = TxData_ch0 ;
assign pcs_TxDataK_ch0 = TxDataK_ch0 ;
assign pcs_TxCompliance_ch0 = TxCompliance_ch0 ;
assign pcs_TxElecIdle_ch0 = TxElecIdle_ch0 ;
assign pcs_ffc_txpwdnb_0 = ffc_txpwdnb_0 ;
assign pcs_ffc_rxpwdnb_0 = ffc_rxpwdnb_0 ;
assign pcs_ffc_rrst_ch0 = ffc_rrst_ch0 ;
assign pcs_ffc_pcie_ct_ch0 = ffc_pcie_ct_ch0 ;
assign pcs_ffc_pcie_det_en_ch0 = ffc_pcie_det_en_ch0 ;
assign pcs_ffc_fb_loopback_ch0 = ffc_fb_loopback_ch0 ;
assign pcs_RxPolarity_ch0 = RxPolarity_ch0 ;
assign pcs_scisel_ch0 = scisel_ch0 ;
assign pcs_scien_ch0 = scien_ch0 ;
// Outputs
assign hdoutp0 = pcs_hdoutp0 ;
assign hdoutn0 = pcs_hdoutn0 ;
assign RxData_ch0 = pcs_RxData_ch0 ;
assign RxDataK_ch0 = pcs_RxDataK_ch0 ;
assign RxStatus_ch0 = pcs_RxStatus_ch0 ;
assign RxValid_ch0 = pcs_RxValid_ch0 ;
assign RxElecIdle_ch0 = pcs_RxElecIdle_ch0 ;
assign ffs_rlol_ch0 = pcs_ffs_rlol_ch0 ;
assign ffs_pcie_done_0 = pcs_ffs_pcie_done_0 ;
assign ff_rx_fclk_ch0 = pcs_ff_rx_fclk_ch0 ;
assign ffs_pcie_con_0 = pcs_ffs_pcie_con_0 ;
`else
// Inputs
assign pcs_hdinp0 = 'd0 ;
assign pcs_hdinn0 = 'd0 ;
assign pcs_TxData_ch0 = 'd0 ;
assign pcs_TxDataK_ch0 = 'd0 ;
assign pcs_TxCompliance_ch0 = 'd0 ;
assign pcs_TxElecIdle_ch0 = 'd0 ;
assign pcs_ffc_txpwdnb_0 = 'd0 ;
assign pcs_ffc_rxpwdnb_0 = 'd0 ;
assign pcs_ffc_rrst_ch0 = 'd0 ;
assign pcs_ffc_pcie_ct_ch0 = 'd0 ;
assign pcs_ffc_pcie_det_en_ch0 = 'd0 ;
assign pcs_ffc_fb_loopback_ch0 = 'd0 ;
assign pcs_RxPolarity_ch0 = 'd0 ;
assign pcs_scisel_ch0 = 'd0 ;
assign pcs_scien_ch0 = 'd0 ;
`endif
// ========================================================
`ifdef Channel_1
// Inputs
assign pcs_hdinp1 = hdinp1 ;
assign pcs_hdinn1 = hdinn1 ;
assign pcs_TxData_ch1 = TxData_ch1 ;
assign pcs_TxDataK_ch1 = TxDataK_ch1 ;
assign pcs_TxCompliance_ch1 = TxCompliance_ch1 ;
assign pcs_TxElecIdle_ch1 = TxElecIdle_ch1 ;
assign pcs_ffc_txpwdnb_1 = ffc_txpwdnb_1 ;
assign pcs_ffc_rxpwdnb_1 = ffc_rxpwdnb_1 ;
assign pcs_ffc_rrst_ch1 = ffc_rrst_ch1 ;
assign pcs_ffc_pcie_ct_ch1 = ffc_pcie_ct_ch1 ;
assign pcs_ffc_pcie_det_en_ch1 = ffc_pcie_det_en_ch1 ;
assign pcs_ffc_fb_loopback_ch1 = ffc_fb_loopback_ch1 ;
assign pcs_RxPolarity_ch1 = RxPolarity_ch1 ;
assign pcs_scisel_ch1 = scisel_ch1 ;
assign pcs_scien_ch1 = scien_ch1 ;
// Outputs
assign hdoutp1 = pcs_hdoutp1 ;
assign hdoutn1 = pcs_hdoutn1 ;
assign RxData_ch1 = pcs_RxData_ch1 ;
assign RxDataK_ch1 = pcs_RxDataK_ch1 ;
assign RxStatus_ch1 = pcs_RxStatus_ch1 ;
assign RxValid_ch1 = pcs_RxValid_ch1 ;
assign RxElecIdle_ch1 = pcs_RxElecIdle_ch1 ;
assign ffs_rlol_ch1 = pcs_ffs_rlol_ch1 ;
assign ffs_pcie_done_1 = pcs_ffs_pcie_done_1 ;
assign ff_rx_fclk_ch1 = pcs_ff_rx_fclk_ch1 ;
assign ffs_pcie_con_1 = pcs_ffs_pcie_con_1 ;
`else
// Inputs
assign pcs_hdinp1 = 'd0 ;
assign pcs_hdinn1 = 'd0 ;
assign pcs_TxData_ch1 = 'd0 ;
assign pcs_TxDataK_ch1 = 'd0 ;
assign pcs_TxCompliance_ch1 = 'd0 ;
assign pcs_TxElecIdle_ch1 = 'd0 ;
assign pcs_ffc_txpwdnb_1 = 'd0 ;
assign pcs_ffc_rxpwdnb_1 = 'd0 ;
assign pcs_ffc_rrst_ch1 = 'd0 ;
assign pcs_ffc_pcie_ct_ch1 = 'd0 ;
assign pcs_ffc_pcie_det_en_ch1 = 'd0 ;
assign pcs_ffc_fb_loopback_ch1 = 'd0 ;
assign pcs_RxPolarity_ch1 = 'd0 ;
assign pcs_scisel_ch1 = 'd0 ;
assign pcs_scien_ch1 = 'd0 ;
`endif
// ========================================================
`ifdef Channel_2
// Inputs
assign pcs_hdinp2 = hdinp2 ;
assign pcs_hdinn2 = hdinn2 ;
assign pcs_TxData_ch2 = TxData_ch2 ;
assign pcs_TxDataK_ch2 = TxDataK_ch2 ;
assign pcs_TxCompliance_ch2 = TxCompliance_ch2 ;
assign pcs_TxElecIdle_ch2 = TxElecIdle_ch2 ;
assign pcs_ffc_txpwdnb_2 = ffc_txpwdnb_2 ;
assign pcs_ffc_rxpwdnb_2 = ffc_rxpwdnb_2 ;
assign pcs_ffc_rrst_ch2 = ffc_rrst_ch2 ;
assign pcs_ffc_pcie_ct_ch2 = ffc_pcie_ct_ch2 ;
assign pcs_ffc_pcie_det_en_ch2 = ffc_pcie_det_en_ch2 ;
assign pcs_ffc_fb_loopback_ch2 = ffc_fb_loopback_ch2 ;
assign pcs_RxPolarity_ch2 = RxPolarity_ch2 ;
assign pcs_scisel_ch2 = scisel_ch2 ;
assign pcs_scien_ch2 = scien_ch2 ;
// Outputs
assign hdoutp2 = pcs_hdoutp2 ;
assign hdoutn2 = pcs_hdoutn2 ;
assign RxData_ch2 = pcs_RxData_ch2 ;
assign RxDataK_ch2 = pcs_RxDataK_ch2 ;
assign RxStatus_ch2 = pcs_RxStatus_ch2 ;
assign RxValid_ch2 = pcs_RxValid_ch2 ;
assign RxElecIdle_ch2 = pcs_RxElecIdle_ch2 ;
assign ffs_rlol_ch2 = pcs_ffs_rlol_ch2 ;
assign ffs_pcie_done_2 = pcs_ffs_pcie_done_2 ;
assign ff_rx_fclk_ch2 = pcs_ff_rx_fclk_ch2 ;
assign ffs_pcie_con_2 = pcs_ffs_pcie_con_2 ;
`else
// Inputs
assign pcs_hdinp2 = 'd0 ;
assign pcs_hdinn2 = 'd0 ;
assign pcs_TxData_ch2 = 'd0 ;
assign pcs_TxDataK_ch2 = 'd0 ;
assign pcs_TxCompliance_ch2 = 'd0 ;
assign pcs_TxElecIdle_ch2 = 'd0 ;
assign pcs_ffc_txpwdnb_2 = 'd0 ;
assign pcs_ffc_rxpwdnb_2 = 'd0 ;
assign pcs_ffc_rrst_ch2 = 'd0 ;
assign pcs_ffc_pcie_ct_ch2 = 'd0 ;
assign pcs_ffc_pcie_det_en_ch2 = 'd0 ;
assign pcs_ffc_fb_loopback_ch2 = 'd0 ;
assign pcs_RxPolarity_ch2 = 'd0 ;
assign pcs_scisel_ch2 = 'd0 ;
assign pcs_scien_ch2 = 'd0 ;
`endif
// ========================================================
`ifdef Channel_3
// Inputs
assign pcs_hdinp3 = hdinp3 ;
assign pcs_hdinn3 = hdinn3 ;
assign pcs_TxData_ch3 = TxData_ch3 ;
assign pcs_TxDataK_ch3 = TxDataK_ch3 ;
assign pcs_TxCompliance_ch3 = TxCompliance_ch3 ;
assign pcs_TxElecIdle_ch3 = TxElecIdle_ch3 ;
assign pcs_ffc_txpwdnb_3 = ffc_txpwdnb_3 ;
assign pcs_ffc_rxpwdnb_3 = ffc_rxpwdnb_3 ;
assign pcs_ffc_rrst_ch3 = ffc_rrst_ch3 ;
assign pcs_ffc_pcie_ct_ch3 = ffc_pcie_ct_ch3 ;
assign pcs_ffc_pcie_det_en_ch3 = ffc_pcie_det_en_ch3 ;
assign pcs_ffc_fb_loopback_ch3 = ffc_fb_loopback_ch3 ;
assign pcs_RxPolarity_ch3 = RxPolarity_ch3 ;
assign pcs_scisel_ch3 = scisel_ch3 ;
assign pcs_scien_ch3 = scien_ch3 ;
// Outputs
assign hdoutp3 = pcs_hdoutp3 ;
assign hdoutn3 = pcs_hdoutn3 ;
assign RxData_ch3 = pcs_RxData_ch3 ;
assign RxDataK_ch3 = pcs_RxDataK_ch3 ;
assign RxStatus_ch3 = pcs_RxStatus_ch3 ;
assign RxValid_ch3 = pcs_RxValid_ch3 ;
assign RxElecIdle_ch3 = pcs_RxElecIdle_ch3 ;
assign ffs_rlol_ch3 = pcs_ffs_rlol_ch3 ;
assign ffs_pcie_done_3 = pcs_ffs_pcie_done_3 ;
assign ff_rx_fclk_ch3 = pcs_ff_rx_fclk_ch3 ;
assign ffs_pcie_con_3 = pcs_ffs_pcie_con_3 ;
`else
// Inputs
assign pcs_hdinp3 = 'd0 ;
assign pcs_hdinn3 = 'd0 ;
assign pcs_TxData_ch3 = 'd0 ;
assign pcs_TxDataK_ch3 = 'd0 ;
assign pcs_TxCompliance_ch3 = 'd0 ;
assign pcs_TxElecIdle_ch3 = 'd0 ;
assign pcs_ffc_txpwdnb_3 = 'd0 ;
assign pcs_ffc_rxpwdnb_3 = 'd0 ;
assign pcs_ffc_rrst_ch3 = 'd0 ;
assign pcs_ffc_pcie_ct_ch3 = 'd0 ;
assign pcs_ffc_pcie_det_en_ch3 = 'd0 ;
assign pcs_ffc_fb_loopback_ch3 = 'd0 ;
assign pcs_RxPolarity_ch3 = 'd0 ;
assign pcs_scisel_ch3 = 'd0 ;
assign pcs_scien_ch3 = 'd0 ;
`endif
// =============================================================================
// PCS instantiation
// =============================================================================
`ifdef ECP3
`define PCS_CD PCSD
`else
`define PCS_CD PCSC
`endif
`PCS_CD pcs_inst_0 (
.REFCLKP ( pcs_refclkp ),
.REFCLKN ( pcs_refclkn ),
.FFC_CK_CORE_TX ( 1'b0 ),
//CH0
.HDINP0 ( pcs_hdinp0 ),
.HDINN0 ( pcs_hdinn0 ),
.HDOUTP0 ( pcs_hdoutp0 ),
.HDOUTN0 ( pcs_hdoutn0 ),
`ifdef ECP3
.PCIE_TXDETRX_PR2TLB_0 ( 1'b0 ),
.PCIE_TXCOMPLIANCE_0 ( 1'b0 ),
.PCIE_RXPOLARITY_0 ( 1'b0 ),
.PCIE_POWERDOWN_0_0 ( 1'b0 ),
.PCIE_POWERDOWN_0_1 ( 1'b0 ),
.PCIE_RXVALID_0 ( ),
.PCIE_PHYSTATUS_0 ( ),
.FF_TX_F_CLK_0 ( pcs_ff_tx_f_clk_0 ),
.FF_TX_H_CLK_0 ( pcs_ff_tx_h_clk_0 ),
.FFC_CK_CORE_RX_0 ( 1'b0 ),
.FFS_RLOS_HI_0 ( ),
.FFS_SKP_ADDED_0 ( ),
.FFS_SKP_DELETED_0 ( ),
.LDR_CORE2TX_0 ( 1'b0 ),
.FFC_LDR_CORE2TX_EN_0 ( 1'b0 ),
.LDR_RX2CORE_0 ( ),
.FFS_CDR_TRAIN_DONE_0 ( ),
.FFC_DIV11_MODE_TX_0 ( 1'b0 ),
.FFC_RATE_MODE_TX_0 ( 1'b0 ),
.FFC_DIV11_MODE_RX_0 ( 1'b0 ),
.FFC_RATE_MODE_RX_0 ( 1'b0 ),
`else
.FF_RX_Q_CLK_0 ( ),
.OOB_OUT_0 ( ),
`endif
.SCISELCH0 ( pcs_scisel_ch0 ),
.SCIENCH0 ( pcs_scien_ch0 ),
.FF_TXI_CLK_0 ( pcs_PCLK ),
`ifdef X4
.FF_RXI_CLK_0 ( pcs_ff_rx_fclk_ch0 ),
.FF_EBRD_CLK_0 ( 1'b0 ),
`else
.FF_RXI_CLK_0 ( pcs_PCLK ),
.FF_EBRD_CLK_0 ( pcs_PCLK ),
`endif
.FF_RX_F_CLK_0 ( pcs_ff_rx_fclk_ch0 ),
.FF_RX_H_CLK_0 ( ),
.FF_TX_D_0_0 ( pcs_TxData_ch0[0] ),
.FF_TX_D_0_1 ( pcs_TxData_ch0[1] ),
.FF_TX_D_0_2 ( pcs_TxData_ch0[2] ),
.FF_TX_D_0_3 ( pcs_TxData_ch0[3] ),
.FF_TX_D_0_4 ( pcs_TxData_ch0[4] ),
.FF_TX_D_0_5 ( pcs_TxData_ch0[5] ),
.FF_TX_D_0_6 ( pcs_TxData_ch0[6] ),
.FF_TX_D_0_7 ( pcs_TxData_ch0[7] ),
.FF_TX_D_0_8 ( pcs_TxDataK_ch0 ),
.FF_TX_D_0_9 ( pcs_TxCompliance_ch0 ),
.FF_TX_D_0_10 ( 1'b0 ),
.FF_TX_D_0_11 ( pcs_TxElecIdle_ch0 ),
.FF_TX_D_0_12 ( 1'b0 ),
.FF_TX_D_0_13 ( 1'b0 ),
.FF_TX_D_0_14 ( 1'b0 ),
.FF_TX_D_0_15 ( 1'b0 ),
.FF_TX_D_0_16 ( 1'b0 ),
.FF_TX_D_0_17 ( 1'b0 ),
.FF_TX_D_0_18 ( 1'b0 ),
.FF_TX_D_0_19 ( 1'b0 ),
.FF_TX_D_0_20 ( 1'b0 ),
.FF_TX_D_0_21 ( 1'b0 ),
.FF_TX_D_0_22 ( 1'b0 ),
.FF_TX_D_0_23 ( 1'b0 ),
.FF_RX_D_0_0 ( pcs_RxData_ch0[0] ),
.FF_RX_D_0_1 ( pcs_RxData_ch0[1] ),
.FF_RX_D_0_2 ( pcs_RxData_ch0[2] ),
.FF_RX_D_0_3 ( pcs_RxData_ch0[3] ),
.FF_RX_D_0_4 ( pcs_RxData_ch0[4] ),
.FF_RX_D_0_5 ( pcs_RxData_ch0[5] ),
.FF_RX_D_0_6 ( pcs_RxData_ch0[6] ),
.FF_RX_D_0_7 ( pcs_RxData_ch0[7] ),
.FF_RX_D_0_8 ( pcs_RxDataK_ch0 ),
.FF_RX_D_0_9 ( pcs_RxStatus_ch0[0] ),
.FF_RX_D_0_10 ( pcs_RxStatus_ch0[1] ),
.FF_RX_D_0_11 ( pcs_RxStatus_ch0[2] ),
.FF_RX_D_0_12 ( ),
.FF_RX_D_0_13 ( ),
.FF_RX_D_0_14 ( ),
.FF_RX_D_0_15 ( ),
.FF_RX_D_0_16 ( ),
.FF_RX_D_0_17 ( ),
.FF_RX_D_0_18 ( ),
.FF_RX_D_0_19 ( ),
.FF_RX_D_0_20 ( ),
.FF_RX_D_0_21 ( ),
.FF_RX_D_0_22 ( ),
.FF_RX_D_0_23 ( ),
.FFC_RRST_0 ( pcs_ffc_rrst_ch0 ),
.FFC_SIGNAL_DETECT_0 ( pcs_ffc_signal_detect ),
.FFC_ENABLE_CGALIGN_0 ( pcs_ffc_enb_cgalign ),
.FFC_SB_PFIFO_LP_0 ( 1'b0 ),
.FFC_PFIFO_CLR_0 ( 1'b0 ),
.FFC_FB_LOOPBACK_0 ( pcs_ffc_fb_loopback_ch0),
.FFC_SB_INV_RX_0 ( pcs_RxPolarity_ch0 ),
.FFC_PCIE_CT_0 ( pcs_ffc_pcie_ct_ch0 ),
.FFC_PCI_DET_EN_0 ( pcs_ffc_pcie_det_en_ch0 ),
.FFS_PCIE_DONE_0 ( pcs_ffs_pcie_done_0 ),
.FFS_PCIE_CON_0 ( pcs_ffs_pcie_con_0 ),
.FFC_EI_EN_0 ( 1'b0 ),
.FFC_LANE_TX_RST_0 ( pcs_ffc_lane_tx_rst ),
.FFC_LANE_RX_RST_0 ( pcs_ffc_lane_rx_rst ),
.FFC_TXPWDNB_0 ( pcs_ffc_txpwdnb_0 ),
.FFC_RXPWDNB_0 ( pcs_ffc_rxpwdnb_0 ),
.FFS_RLOS_LO_0 ( pcs_RxElecIdle_ch0 ),
.FFS_LS_SYNC_STATUS_0 ( pcs_RxValid_ch0 ),
.FFS_CC_UNDERRUN_0 ( ),
.FFS_CC_OVERRUN_0 ( ),
.FFS_RXFBFIFO_ERROR_0 ( ),
.FFS_TXFBFIFO_ERROR_0 ( ),
.FFS_RLOL_0 ( pcs_ffs_rlol_ch0 ),
//CH1
.HDINP1 ( pcs_hdinp1 ),
.HDINN1 ( pcs_hdinn1 ),
.HDOUTP1 ( pcs_hdoutp1 ),
.HDOUTN1 ( pcs_hdoutn1 ),
`ifdef ECP3
.PCIE_TXDETRX_PR2TLB_1 ( 1'b0 ),
.PCIE_TXCOMPLIANCE_1 ( 1'b0 ),
.PCIE_RXPOLARITY_1 ( 1'b0 ),
.PCIE_POWERDOWN_1_0 ( 1'b0 ),
.PCIE_POWERDOWN_1_1 ( 1'b0 ),
.PCIE_RXVALID_1 ( ),
.PCIE_PHYSTATUS_1 ( ),
.FF_TX_F_CLK_1 ( pcs_ff_tx_f_clk_1 ),
.FF_TX_H_CLK_1 ( pcs_ff_tx_h_clk_1 ),
.FFC_CK_CORE_RX_1 ( 1'b0 ),
.FFS_RLOS_HI_1 ( ),
.FFS_SKP_ADDED_1 ( ),
.FFS_SKP_DELETED_1 ( ),
.LDR_CORE2TX_1 ( 1'b0 ),
.FFC_LDR_CORE2TX_EN_1 ( 1'b0 ),
.LDR_RX2CORE_1 ( ),
.FFS_CDR_TRAIN_DONE_1 ( ),
.FFC_DIV11_MODE_TX_1 ( 1'b0 ),
.FFC_RATE_MODE_TX_1 ( 1'b0 ),
.FFC_DIV11_MODE_RX_1 ( 1'b0 ),
.FFC_RATE_MODE_RX_1 ( 1'b0 ),
`else
.FF_RX_Q_CLK_1 ( ),
.OOB_OUT_1 ( ),
`endif
.SCISELCH1 ( pcs_scisel_ch1 ),
.SCIENCH1 ( pcs_scien_ch1 ),
.FF_TXI_CLK_1 ( pcs_PCLK ),
`ifdef X4
.FF_RXI_CLK_1 ( pcs_ff_rx_fclk_ch1 ),
.FF_EBRD_CLK_1 ( 1'b0 ),
`else
.FF_RXI_CLK_1 ( pcs_PCLK ),
.FF_EBRD_CLK_1 ( pcs_PCLK ),
`endif
.FF_RX_F_CLK_1 ( pcs_ff_rx_fclk_ch1 ),
.FF_RX_H_CLK_1 ( ),
.FF_TX_D_1_0 ( pcs_TxData_ch1[0] ),
.FF_TX_D_1_1 ( pcs_TxData_ch1[1] ),
.FF_TX_D_1_2 ( pcs_TxData_ch1[2] ),
.FF_TX_D_1_3 ( pcs_TxData_ch1[3] ),
.FF_TX_D_1_4 ( pcs_TxData_ch1[4] ),
.FF_TX_D_1_5 ( pcs_TxData_ch1[5] ),
.FF_TX_D_1_6 ( pcs_TxData_ch1[6] ),
.FF_TX_D_1_7 ( pcs_TxData_ch1[7] ),
.FF_TX_D_1_8 ( pcs_TxDataK_ch1 ),
.FF_TX_D_1_9 ( pcs_TxCompliance_ch1 ),
.FF_TX_D_1_10 ( 1'b0 ),
.FF_TX_D_1_11 ( pcs_TxElecIdle_ch1 ),
.FF_TX_D_1_12 ( 1'b0 ),
.FF_TX_D_1_13 ( 1'b0 ),
.FF_TX_D_1_14 ( 1'b0 ),
.FF_TX_D_1_15 ( 1'b0 ),
.FF_TX_D_1_16 ( 1'b0 ),
.FF_TX_D_1_17 ( 1'b0 ),
.FF_TX_D_1_18 ( 1'b0 ),
.FF_TX_D_1_19 ( 1'b0 ),
.FF_TX_D_1_20 ( 1'b0 ),
.FF_TX_D_1_21 ( 1'b0 ),
.FF_TX_D_1_22 ( 1'b0 ),
.FF_TX_D_1_23 ( 1'b0 ),
.FF_RX_D_1_0 ( pcs_RxData_ch1[0] ),
.FF_RX_D_1_1 ( pcs_RxData_ch1[1] ),
.FF_RX_D_1_2 ( pcs_RxData_ch1[2] ),
.FF_RX_D_1_3 ( pcs_RxData_ch1[3] ),
.FF_RX_D_1_4 ( pcs_RxData_ch1[4] ),
.FF_RX_D_1_5 ( pcs_RxData_ch1[5] ),
.FF_RX_D_1_6 ( pcs_RxData_ch1[6] ),
.FF_RX_D_1_7 ( pcs_RxData_ch1[7] ),
.FF_RX_D_1_8 ( pcs_RxDataK_ch1 ),
.FF_RX_D_1_9 ( pcs_RxStatus_ch1[0] ),
.FF_RX_D_1_10 ( pcs_RxStatus_ch1[1] ),
.FF_RX_D_1_11 ( pcs_RxStatus_ch1[2] ),
.FF_RX_D_1_12 ( ),
.FF_RX_D_1_13 ( ),
.FF_RX_D_1_14 ( ),
.FF_RX_D_1_15 ( ),
.FF_RX_D_1_16 ( ),
.FF_RX_D_1_17 ( ),
.FF_RX_D_1_18 ( ),
.FF_RX_D_1_19 ( ),
.FF_RX_D_1_20 ( ),
.FF_RX_D_1_21 ( ),
.FF_RX_D_1_22 ( ),
.FF_RX_D_1_23 ( ),
.FFC_RRST_1 ( pcs_ffc_rrst_ch1 ),
.FFC_SIGNAL_DETECT_1 ( pcs_ffc_signal_detect ),
.FFC_ENABLE_CGALIGN_1 ( pcs_ffc_enb_cgalign ),
.FFC_SB_PFIFO_LP_1 ( 1'b0 ),
.FFC_PFIFO_CLR_1 ( 1'b0 ),
.FFC_FB_LOOPBACK_1 ( pcs_ffc_fb_loopback_ch1 ),
.FFC_SB_INV_RX_1 ( pcs_RxPolarity_ch1 ),
.FFC_PCIE_CT_1 ( pcs_ffc_pcie_ct_ch1 ),
.FFC_PCI_DET_EN_1 ( pcs_ffc_pcie_det_en_ch1 ),
.FFS_PCIE_DONE_1 ( pcs_ffs_pcie_done_1 ),
.FFS_PCIE_CON_1 ( pcs_ffs_pcie_con_1 ),
.FFC_EI_EN_1 ( 1'b0 ),
.FFC_LANE_TX_RST_1 ( pcs_ffc_lane_tx_rst ),
.FFC_LANE_RX_RST_1 ( pcs_ffc_lane_rx_rst ),
.FFC_TXPWDNB_1 ( pcs_ffc_txpwdnb_1 ),
.FFC_RXPWDNB_1 ( pcs_ffc_rxpwdnb_1 ),
.FFS_RLOS_LO_1 ( pcs_RxElecIdle_ch1 ),
.FFS_LS_SYNC_STATUS_1 ( pcs_RxValid_ch1 ),
.FFS_CC_UNDERRUN_1 ( ),
.FFS_CC_OVERRUN_1 ( ),
.FFS_RXFBFIFO_ERROR_1 ( ),
.FFS_TXFBFIFO_ERROR_1 ( ),
.FFS_RLOL_1 ( pcs_ffs_rlol_ch1 ),
//CH2
.HDINP2 ( pcs_hdinp2 ),
.HDINN2 ( pcs_hdinn2 ),
.HDOUTP2 ( pcs_hdoutp2 ),
.HDOUTN2 ( pcs_hdoutn2 ),
`ifdef ECP3
.PCIE_TXDETRX_PR2TLB_2 ( 1'b0 ),
.PCIE_TXCOMPLIANCE_2 ( 1'b0 ),
.PCIE_RXPOLARITY_2 ( 1'b0 ),
.PCIE_POWERDOWN_2_0 ( 1'b0 ),
.PCIE_POWERDOWN_2_1 ( 1'b0 ),
.PCIE_RXVALID_2 ( ),
.PCIE_PHYSTATUS_2 ( ),
.FF_TX_F_CLK_2 ( pcs_ff_tx_f_clk_2 ),
.FF_TX_H_CLK_2 ( pcs_ff_tx_h_clk_2 ),
.FFC_CK_CORE_RX_2 ( 1'b0 ),
.FFS_RLOS_HI_2 ( ),
.FFS_SKP_ADDED_2 ( ),
.FFS_SKP_DELETED_2 ( ),
.LDR_CORE2TX_2 ( 1'b0 ),
.FFC_LDR_CORE2TX_EN_2 ( 1'b0 ),
.LDR_RX2CORE_2 ( ),
.FFS_CDR_TRAIN_DONE_2 ( ),
.FFC_DIV11_MODE_TX_2 ( 1'b0 ),
.FFC_RATE_MODE_TX_2 ( 1'b0 ),
.FFC_DIV11_MODE_RX_2 ( 1'b0 ),
.FFC_RATE_MODE_RX_2 ( 1'b0 ),
`else
.FF_RX_Q_CLK_2 ( ),
.OOB_OUT_2 ( ),
`endif
.SCISELCH2 ( pcs_scisel_ch2 ),
.SCIENCH2 ( pcs_scien_ch2 ),
.FF_TXI_CLK_2 ( pcs_PCLK ),
`ifdef X4
.FF_RXI_CLK_2 ( pcs_ff_rx_fclk_ch2 ),
.FF_EBRD_CLK_2 ( 1'b0 ),
`else
.FF_RXI_CLK_2 ( pcs_PCLK ),
.FF_EBRD_CLK_2 ( pcs_PCLK ),
`endif
.FF_RX_F_CLK_2 ( pcs_ff_rx_fclk_ch2 ),
.FF_RX_H_CLK_2 ( ),
.FF_TX_D_2_0 ( pcs_TxData_ch2[0] ),
.FF_TX_D_2_1 ( pcs_TxData_ch2[1] ),
.FF_TX_D_2_2 ( pcs_TxData_ch2[2] ),
.FF_TX_D_2_3 ( pcs_TxData_ch2[3] ),
.FF_TX_D_2_4 ( pcs_TxData_ch2[4] ),
.FF_TX_D_2_5 ( pcs_TxData_ch2[5] ),
.FF_TX_D_2_6 ( pcs_TxData_ch2[6] ),
.FF_TX_D_2_7 ( pcs_TxData_ch2[7] ),
.FF_TX_D_2_8 ( pcs_TxDataK_ch2 ),
.FF_TX_D_2_9 ( pcs_TxCompliance_ch2 ),
.FF_TX_D_2_10 ( 1'b0 ),
.FF_TX_D_2_11 ( pcs_TxElecIdle_ch2 ),
.FF_TX_D_2_12 ( 1'b0 ),
.FF_TX_D_2_13 ( 1'b0 ),
.FF_TX_D_2_14 ( 1'b0 ),
.FF_TX_D_2_15 ( 1'b0 ),
.FF_TX_D_2_16 ( 1'b0 ),
.FF_TX_D_2_17 ( 1'b0 ),
.FF_TX_D_2_18 ( 1'b0 ),
.FF_TX_D_2_19 ( 1'b0 ),
.FF_TX_D_2_20 ( 1'b0 ),
.FF_TX_D_2_21 ( 1'b0 ),
.FF_TX_D_2_22 ( 1'b0 ),
.FF_TX_D_2_23 ( 1'b0 ),
.FF_RX_D_2_0 ( pcs_RxData_ch2[0] ),
.FF_RX_D_2_1 ( pcs_RxData_ch2[1] ),
.FF_RX_D_2_2 ( pcs_RxData_ch2[2] ),
.FF_RX_D_2_3 ( pcs_RxData_ch2[3] ),
.FF_RX_D_2_4 ( pcs_RxData_ch2[4] ),
.FF_RX_D_2_5 ( pcs_RxData_ch2[5] ),
.FF_RX_D_2_6 ( pcs_RxData_ch2[6] ),
.FF_RX_D_2_7 ( pcs_RxData_ch2[7] ),
.FF_RX_D_2_8 ( pcs_RxDataK_ch2 ),
.FF_RX_D_2_9 ( pcs_RxStatus_ch2[0] ),
.FF_RX_D_2_10 ( pcs_RxStatus_ch2[1] ),
.FF_RX_D_2_11 ( pcs_RxStatus_ch2[2] ),
.FF_RX_D_2_12 ( ),
.FF_RX_D_2_13 ( ),
.FF_RX_D_2_14 ( ),
.FF_RX_D_2_15 ( ),
.FF_RX_D_2_16 ( ),
.FF_RX_D_2_17 ( ),
.FF_RX_D_2_18 ( ),
.FF_RX_D_2_19 ( ),
.FF_RX_D_2_20 ( ),
.FF_RX_D_2_21 ( ),
.FF_RX_D_2_22 ( ),
.FF_RX_D_2_23 ( ),
.FFC_RRST_2 ( pcs_ffc_rrst_ch2 ),
.FFC_SIGNAL_DETECT_2 ( pcs_ffc_signal_detect ),
.FFC_ENABLE_CGALIGN_2 ( pcs_ffc_enb_cgalign ),
.FFC_SB_PFIFO_LP_2 ( 1'b0 ),
.FFC_PFIFO_CLR_2 ( 1'b0 ),
.FFC_FB_LOOPBACK_2 ( pcs_ffc_fb_loopback_ch2 ),
.FFC_SB_INV_RX_2 ( pcs_RxPolarity_ch2 ),
.FFC_PCIE_CT_2 ( pcs_ffc_pcie_ct_ch2 ),
.FFC_PCI_DET_EN_2 ( pcs_ffc_pcie_det_en_ch2 ),
.FFS_PCIE_DONE_2 ( pcs_ffs_pcie_done_2 ),
.FFS_PCIE_CON_2 ( pcs_ffs_pcie_con_2 ),
.FFC_EI_EN_2 ( 1'b0 ),
.FFC_LANE_TX_RST_2 ( pcs_ffc_lane_tx_rst ),
.FFC_LANE_RX_RST_2 ( pcs_ffc_lane_rx_rst ),
.FFC_TXPWDNB_2 ( pcs_ffc_txpwdnb_2 ),
.FFC_RXPWDNB_2 ( pcs_ffc_rxpwdnb_2 ),
.FFS_RLOS_LO_2 ( pcs_RxElecIdle_ch2 ),
.FFS_LS_SYNC_STATUS_2 ( pcs_RxValid_ch2 ),
.FFS_CC_UNDERRUN_2 ( ),
.FFS_CC_OVERRUN_2 ( ),
.FFS_RXFBFIFO_ERROR_2 ( ),
.FFS_TXFBFIFO_ERROR_2 ( ),
.FFS_RLOL_2 ( pcs_ffs_rlol_ch2 ),
//CH3
.HDINP3 ( pcs_hdinp3 ),
.HDINN3 ( pcs_hdinn3 ),
.HDOUTP3 ( pcs_hdoutp3 ),
.HDOUTN3 ( pcs_hdoutn3 ),
`ifdef ECP3
.PCIE_TXDETRX_PR2TLB_3 ( 1'b0 ),
.PCIE_TXCOMPLIANCE_3 ( 1'b0 ),
.PCIE_RXPOLARITY_3 ( 1'b0 ),
.PCIE_POWERDOWN_3_0 ( 1'b0 ),
.PCIE_POWERDOWN_3_1 ( 1'b0 ),
.PCIE_RXVALID_3 ( ),
.PCIE_PHYSTATUS_3 ( ),
.FF_TX_F_CLK_3 ( pcs_ff_tx_f_clk_3 ),
.FF_TX_H_CLK_3 ( pcs_ff_tx_h_clk_3 ),
.FFC_CK_CORE_RX_3 ( 1'b0 ),
.FFS_RLOS_HI_3 ( ),
.FFS_SKP_ADDED_3 ( ),
.FFS_SKP_DELETED_3 ( ),
.LDR_CORE2TX_3 ( 1'b0 ),
.FFC_LDR_CORE2TX_EN_3 ( 1'b0 ),
.LDR_RX2CORE_3 ( ),
.FFS_CDR_TRAIN_DONE_3 ( ),
.FFC_DIV11_MODE_TX_3 ( 1'b0 ),
.FFC_RATE_MODE_TX_3 ( 1'b0 ),
.FFC_DIV11_MODE_RX_3 ( 1'b0 ),
.FFC_RATE_MODE_RX_3 ( 1'b0 ),
`else
.FF_RX_Q_CLK_3 ( ),
.OOB_OUT_3 ( ),
`endif
.SCISELCH3 ( pcs_scisel_ch3 ),
.SCIENCH3 ( pcs_scien_ch3 ),
.FF_TXI_CLK_3 ( pcs_PCLK ),
`ifdef X4
.FF_RXI_CLK_3 ( pcs_ff_rx_fclk_ch3 ),
.FF_EBRD_CLK_3 ( 1'b0 ),
`else
.FF_RXI_CLK_3 ( pcs_PCLK ),
.FF_EBRD_CLK_3 ( pcs_PCLK ),
`endif
.FF_RX_F_CLK_3 ( pcs_ff_rx_fclk_ch3 ),
.FF_RX_H_CLK_3 ( ),
.FF_TX_D_3_0 ( pcs_TxData_ch3[0] ),
.FF_TX_D_3_1 ( pcs_TxData_ch3[1] ),
.FF_TX_D_3_2 ( pcs_TxData_ch3[2] ),
.FF_TX_D_3_3 ( pcs_TxData_ch3[3] ),
.FF_TX_D_3_4 ( pcs_TxData_ch3[4] ),
.FF_TX_D_3_5 ( pcs_TxData_ch3[5] ),
.FF_TX_D_3_6 ( pcs_TxData_ch3[6] ),
.FF_TX_D_3_7 ( pcs_TxData_ch3[7] ),
.FF_TX_D_3_8 ( pcs_TxDataK_ch3 ),
.FF_TX_D_3_9 ( pcs_TxCompliance_ch3 ),
.FF_TX_D_3_10 ( 1'b0 ),
.FF_TX_D_3_11 ( pcs_TxElecIdle_ch3 ),
.FF_TX_D_3_12 ( 1'b0 ),
.FF_TX_D_3_13 ( 1'b0 ),
.FF_TX_D_3_14 ( 1'b0 ),
.FF_TX_D_3_15 ( 1'b0 ),
.FF_TX_D_3_16 ( 1'b0 ),
.FF_TX_D_3_17 ( 1'b0 ),
.FF_TX_D_3_18 ( 1'b0 ),
.FF_TX_D_3_19 ( 1'b0 ),
.FF_TX_D_3_20 ( 1'b0 ),
.FF_TX_D_3_21 ( 1'b0 ),
.FF_TX_D_3_22 ( 1'b0 ),
.FF_TX_D_3_23 ( 1'b0 ),
.FF_RX_D_3_0 ( pcs_RxData_ch3[0] ),
.FF_RX_D_3_1 ( pcs_RxData_ch3[1] ),
.FF_RX_D_3_2 ( pcs_RxData_ch3[2] ),
.FF_RX_D_3_3 ( pcs_RxData_ch3[3] ),
.FF_RX_D_3_4 ( pcs_RxData_ch3[4] ),
.FF_RX_D_3_5 ( pcs_RxData_ch3[5] ),
.FF_RX_D_3_6 ( pcs_RxData_ch3[6] ),
.FF_RX_D_3_7 ( pcs_RxData_ch3[7] ),
.FF_RX_D_3_8 ( pcs_RxDataK_ch3 ),
.FF_RX_D_3_9 ( pcs_RxStatus_ch3[0] ),
.FF_RX_D_3_10 ( pcs_RxStatus_ch3[1] ),
.FF_RX_D_3_11 ( pcs_RxStatus_ch3[2] ),
.FF_RX_D_3_12 ( ),
.FF_RX_D_3_13 ( ),
.FF_RX_D_3_14 ( ),
.FF_RX_D_3_15 ( ),
.FF_RX_D_3_16 ( ),
.FF_RX_D_3_17 ( ),
.FF_RX_D_3_18 ( ),
.FF_RX_D_3_19 ( ),
.FF_RX_D_3_20 ( ),
.FF_RX_D_3_21 ( ),
.FF_RX_D_3_22 ( ),
.FF_RX_D_3_23 ( ),
.FFC_RRST_3 ( pcs_ffc_rrst_ch3 ),
.FFC_SIGNAL_DETECT_3 ( pcs_ffc_signal_detect ),
.FFC_ENABLE_CGALIGN_3 ( pcs_ffc_enb_cgalign ),
.FFC_SB_PFIFO_LP_3 ( 1'b0 ),
.FFC_PFIFO_CLR_3 ( 1'b0 ),
.FFC_FB_LOOPBACK_3 ( pcs_ffc_fb_loopback_ch3 ),
.FFC_SB_INV_RX_3 ( pcs_RxPolarity_ch3 ),
.FFC_PCIE_CT_3 ( pcs_ffc_pcie_ct_ch3 ),
.FFC_PCI_DET_EN_3 ( pcs_ffc_pcie_det_en_ch3 ),
.FFS_PCIE_DONE_3 ( pcs_ffs_pcie_done_3 ),
.FFS_PCIE_CON_3 ( pcs_ffs_pcie_con_3 ),
.FFC_EI_EN_3 ( 1'b0 ),
.FFC_LANE_TX_RST_3 ( pcs_ffc_lane_tx_rst ),
.FFC_LANE_RX_RST_3 ( pcs_ffc_lane_rx_rst ),
.FFC_TXPWDNB_3 ( pcs_ffc_txpwdnb_3 ),
.FFC_RXPWDNB_3 ( pcs_ffc_rxpwdnb_3 ),
.FFS_RLOS_LO_3 ( pcs_RxElecIdle_ch3 ),
.FFS_LS_SYNC_STATUS_3 ( pcs_RxValid_ch3 ),
.FFS_CC_UNDERRUN_3 ( ),
.FFS_CC_OVERRUN_3 ( ),
.FFS_RXFBFIFO_ERROR_3 ( ),
.FFS_TXFBFIFO_ERROR_3 ( ),
.FFS_RLOL_3 ( pcs_ffs_rlol_ch3 ),
// SCI PINS
.SCIWDATA0 ( pcs_sciwritedata[0] ),
.SCIWDATA1 ( pcs_sciwritedata[1] ),
.SCIWDATA2 ( pcs_sciwritedata[2] ),
.SCIWDATA3 ( pcs_sciwritedata[3] ),
.SCIWDATA4 ( pcs_sciwritedata[4] ),
.SCIWDATA5 ( pcs_sciwritedata[5] ),
.SCIWDATA6 ( pcs_sciwritedata[6] ),
.SCIWDATA7 ( pcs_sciwritedata[7] ),
.SCIADDR0 ( pcs_sciaddress[0] ),
.SCIADDR1 ( pcs_sciaddress[1] ),
.SCIADDR2 ( pcs_sciaddress[2] ),
.SCIADDR3 ( pcs_sciaddress[3] ),
.SCIADDR4 ( pcs_sciaddress[4] ),
.SCIADDR5 ( pcs_sciaddress[5] ),
.SCIRDATA0 ( pcs_scireaddata[0] ),
.SCIRDATA1 ( pcs_scireaddata[1] ),
.SCIRDATA2 ( pcs_scireaddata[2] ),
.SCIRDATA3 ( pcs_scireaddata[3] ),
.SCIRDATA4 ( pcs_scireaddata[4] ),
.SCIRDATA5 ( pcs_scireaddata[5] ),
.SCIRDATA6 ( pcs_scireaddata[6] ),
.SCIRDATA7 ( pcs_scireaddata[7] ),
.SCIENAUX ( pcs_scienaux ),
.SCISELAUX ( pcs_sciselaux ),
.SCIRD ( pcs_scird ),
.SCIWSTN ( pcs_sciwstn ),
.CYAWSTN ( 1'b0 ),
.SCIINT ( ),
`ifdef ECP3
.FFC_SYNC_TOGGLE ( 1'b0 ),
.REFCLK_FROM_NQ ( 1'b0 ),
.REFCLK_TO_NQ ( ),
`else
.FFC_CK_CORE_RX ( 1'b0 ),
.FF_TX_F_CLK ( pcs_ff_tx_f_clk ),
.FF_TX_H_CLK ( pcs_ff_tx_h_clk ),
.FF_TX_Q_CLK ( ),
`endif
.FFC_MACRO_RST ( pcs_ffc_macro_rst ),
.FFC_QUAD_RST ( pcs_ffc_quad_rst ),
.FFC_TRST ( pcs_ffc_trst ),
.REFCK2CORE ( ),
.CIN0 ( pcs_cin[0] ),
.CIN1 ( pcs_cin[1] ),
.CIN2 ( pcs_cin[2] ),
.CIN3 ( pcs_cin[3] ),
.CIN4 ( pcs_cin[4] ),
.CIN5 ( pcs_cin[5] ),
.CIN6 ( pcs_cin[6] ),
.CIN7 ( pcs_cin[7] ),
.CIN8 ( pcs_cin[8] ),
.CIN9 ( pcs_cin[9] ),
.CIN10 ( pcs_cin[10] ),
.CIN11 ( pcs_cin[11] ),
.COUT0 ( pcs_cout[0] ),
.COUT1 ( pcs_cout[1] ),
.COUT2 ( pcs_cout[2] ),
.COUT3 ( pcs_cout[3] ),
.COUT4 ( pcs_cout[4] ),
.COUT5 ( pcs_cout[5] ),
.COUT6 ( pcs_cout[6] ),
.COUT7 ( pcs_cout[7] ),
.COUT8 ( pcs_cout[8] ),
.COUT9 ( pcs_cout[9] ),
.COUT10 ( pcs_cout[10] ),
.COUT11 ( pcs_cout[11] ),
.COUT12 ( pcs_cout[12] ),
.COUT13 ( pcs_cout[13] ),
.COUT14 ( pcs_cout[14] ),
.COUT15 ( pcs_cout[15] ),
.COUT16 ( pcs_cout[16] ),
.COUT17 ( pcs_cout[17] ),
.COUT18 ( pcs_cout[18] ),
.COUT19 ( pcs_cout[19] ),
.FFS_PLOL ( pcs_ffs_plol )
`ifdef ECP3
`ifdef X1
) /* synthesis IS_ASB="ep5c00/data/ep5c00.acd" CONFIG_FILE="pcs_pipe_8b_x1.txt" */;
`else
) /* synthesis IS_ASB="ep5c00/data/ep5c00.acd" CONFIG_FILE="pcs_pipe_8b_x4.txt" */;
`endif
`else
`ifdef X1
) /* synthesis IS_ASB="ep5m00/data/ep5m00.acd" CONFIG_FILE="pcs_pipe_8b_x1.txt" */;
`else
) /* synthesis IS_ASB="ep5m00/data/ep5m00.acd" CONFIG_FILE="pcs_pipe_8b_x4.txt" */;
`endif
`endif
// =============================================================================
endmodule
|
module grid_AD7490(
// Qsys interface
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_address,
input [3:0] avs_ctrl_byteenable,
input avs_ctrl_write,
input avs_ctrl_read,
output avs_ctrl_waitrequest,
input csi_ADCCLK_clk,
// debug interface
//output [3:0] aso_adc_channel,
//output [15:0] aso_adc_data,
//output aso_adc_valid,
//input aso_adc_ready,
//ADC interface
output coe_DIN,
input coe_DOUT,
output coe_SCLK,
output coe_CSN
);
assign avs_ctrl_readdata = read_data;
assign avs_ctrl_waitrequest = 1'b0;
//assign aso_adc_channel = adc_aso_ch;
//assign aso_adc_data = {adc_aso_data, 4'b0};
//assign aso_adc_valid = adc_aso_valid;
assign coe_DIN = spi_din;
assign spi_dout = coe_DOUT;
assign coe_SCLK = spi_clk;
assign coe_CSN = spi_cs;
reg [31:0] read_data = 0;
reg spi_din = 0, spi_cs = 1, spi_clk = 1;
wire spi_dout;
reg [7:0] state = 0;
reg [7:0] delay = 0;
reg adc_range = 0;
reg adc_coding = 1;
reg adc_reset = 1;
reg [7:0] cnv_delay = 255;
reg [11:0] adc_ch[0:15];
reg [3:0] adc_addr = 0;
reg [3:0] adc_aso_ch = 0;
reg [11:0] adc_aso_data = 0;
reg adc_aso_valid = 0;
/*
* GRID_MOD_SIZE 0x0
* GRID_MOD_ID 0x4
* ADC_CTRL 0x8
* CNV_DELAY 0xC
* ADC_CH0 0x20
* ADC_CH1 0x22
* ADC_CH2 0x24
* ADC_CH3 0x26
* ADC_CH4 0x28
* ADC_CH5 0x2A
* ADC_CH6 0x2C
* ADC_CH7 0x2E
* ADC_CH8 0x30
* ADC_CH9 0x32
* ADC_CH10 0x34
* ADC_CH11 0x36
* ADC_CH12 0x38
* ADC_CH13 0x3A
* ADC_CH14 0x3C
* ADC_CH15 0x3E
*/
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
end
else begin
case(avs_ctrl_address)
0: read_data <= 64;
1: read_data <= 32'hEA680003;
2: read_data <= {4'b0, adc_addr, 7'b0, adc_range, 7'b0, adc_coding, 7'b0, adc_reset};
3: read_data <= {24'b0, cnv_delay};
8: read_data <= {adc_ch[1], 4'b0, adc_ch[0], 4'b0};
9: read_data <= {adc_ch[3], 4'b0, adc_ch[2], 4'b0};
10: read_data <= {adc_ch[5], 4'b0, adc_ch[4], 4'b0};
11: read_data <= {adc_ch[7], 4'b0, adc_ch[6], 4'b0};
12: read_data <= {adc_ch[9], 4'b0, adc_ch[8], 4'b0};
13: read_data <= {adc_ch[11], 4'b0, adc_ch[10], 4'b0};
14: read_data <= {adc_ch[13], 4'b0, adc_ch[12], 4'b0};
15: read_data <= {adc_ch[15], 4'b0, adc_ch[14], 4'b0};
default: read_data <= 0;
endcase
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
adc_range <= 0;
adc_coding <= 1;
adc_reset <= 1;
cnv_delay <= 255;
end
else begin
if(avs_ctrl_write) begin
case(avs_ctrl_address)
2: begin
if(avs_ctrl_byteenable[2]) adc_range <= avs_ctrl_writedata[16];
if(avs_ctrl_byteenable[1]) adc_coding <= avs_ctrl_writedata[8];
if(avs_ctrl_byteenable[0]) adc_reset <= avs_ctrl_writedata[0];
end
3: begin
if(avs_ctrl_byteenable[0]) cnv_delay <= avs_ctrl_writedata[7:0];
end
default: begin end
endcase
end
end
end
wire rWRITE = 1;
wire rSEQ = 0;
wire rPM1 = 1;
wire rPM0 = 1;
wire rSHADOW = 0;
wire rWEAKTRI = 0;
reg [7:0] clk_counter;
reg adc_clk_20m; //csi_ADCCLK_clk is 200M
always@(posedge csi_ADCCLK_clk or posedge adc_reset)
begin
if(adc_reset) begin
adc_clk_20m <= 1'b0;
clk_counter <= 8'b0;
end
else begin
clk_counter <= clk_counter + 1'b1;
if(clk_counter == 8'd5) begin
adc_clk_20m <= ~adc_clk_20m;
clk_counter <= 8'b0;
end
end
end
always@(posedge adc_clk_20m or posedge adc_reset)
begin
if(adc_reset) begin
adc_ch[0] <= 0;
adc_ch[1] <= 0;
adc_ch[2] <= 0;
adc_ch[3] <= 0;
adc_ch[4] <= 0;
adc_ch[5] <= 0;
adc_ch[6] <= 0;
adc_ch[7] <= 0;
adc_ch[8] <= 0;
adc_ch[9] <= 0;
adc_ch[10] <= 0;
adc_ch[11] <= 0;
adc_ch[12] <= 0;
adc_ch[13] <= 0;
adc_ch[14] <= 0;
adc_ch[15] <= 0;
adc_addr <= 0;
adc_aso_ch <= 0;
adc_aso_data <= 0;
adc_aso_valid <= 0;
spi_din <= 0;
spi_cs <= 1;
spi_clk <= 1;
state <= 0;
delay <= 0;
end
else begin
case(state)
0: begin state <= state + 1; spi_clk <= 1; spi_din <= rWRITE; spi_cs <= 1; delay <= 0; end
1: begin if(delay > cnv_delay) begin delay <= 0; state <= state + 1; end else delay <= delay + 1; end
2: begin state <= state + 1; spi_clk <= 1; spi_din <= rWRITE; spi_cs <= 0; end
3: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[3] <= spi_dout; end
4: begin state <= state + 1; spi_clk <= 1; spi_din <= rSEQ; end
5: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[2] <= spi_dout; end
6: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[3]; end
7: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[1] <= spi_dout; end
8: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[2]; end
9: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[0] <= spi_dout; end
10: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[1]; end
11: begin state <= state + 1; spi_clk <= 0; adc_aso_data[11] <= spi_dout; end
12: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[0]; end
13: begin state <= state + 1; spi_clk <= 0; adc_aso_data[10] <= spi_dout; end
14: begin state <= state + 1; spi_clk <= 1; spi_din <= rPM1; end
15: begin state <= state + 1; spi_clk <= 0; adc_aso_data[9] <= spi_dout; end
16: begin state <= state + 1; spi_clk <= 1; spi_din <= rPM0; end
17: begin state <= state + 1; spi_clk <= 0; adc_aso_data[8] <= spi_dout; end
18: begin state <= state + 1; spi_clk <= 1; spi_din <= rSHADOW; end
19: begin state <= state + 1; spi_clk <= 0; adc_aso_data[7] <= spi_dout; end
20: begin state <= state + 1; spi_clk <= 1; spi_din <= rWEAKTRI; end
21: begin state <= state + 1; spi_clk <= 0; adc_aso_data[6] <= spi_dout; end
22: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_range; end
23: begin state <= state + 1; spi_clk <= 0; adc_aso_data[5] <= spi_dout; end
24: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_coding; end
25: begin state <= state + 1; spi_clk <= 0; adc_aso_data[4] <= spi_dout; end
26: begin state <= state + 1; spi_clk <= 1; spi_din <= 0; end
27: begin state <= state + 1; spi_clk <= 0; adc_aso_data[3] <= spi_dout; end
28: begin state <= state + 1; spi_clk <= 1; end
29: begin state <= state + 1; spi_clk <= 0; adc_aso_data[2] <= spi_dout; end
30: begin state <= state + 1; spi_clk <= 1; end
31: begin state <= state + 1; spi_clk <= 0; adc_aso_data[1] <= spi_dout; end
32: begin state <= state + 1; spi_clk <= 1; end
33: begin state <= state + 1; spi_clk <= 0; adc_aso_data[0] <= spi_dout; end
34: begin state <= state + 1; spi_clk <= 1; adc_ch[adc_aso_ch] <= adc_aso_data; adc_aso_valid <= 1; end
35: begin state <= 0; spi_cs <= 1; adc_aso_valid <= 0; adc_addr <= adc_addr + 1; end
default: begin
adc_ch[0] <= 0;
adc_ch[1] <= 0;
adc_ch[2] <= 0;
adc_ch[3] <= 0;
adc_ch[4] <= 0;
adc_ch[5] <= 0;
adc_ch[6] <= 0;
adc_ch[7] <= 0;
adc_ch[8] <= 0;
adc_ch[9] <= 0;
adc_ch[10] <= 0;
adc_ch[11] <= 0;
adc_ch[12] <= 0;
adc_ch[13] <= 0;
adc_ch[14] <= 0;
adc_ch[15] <= 0;
adc_addr <= 0;
adc_aso_ch <= 0;
adc_aso_data <= 0;
adc_aso_valid <= 0;
spi_din <= 0;
spi_cs <= 1;
spi_clk <= 1;
state <= 0;
delay <= 0;
end
endcase
end
end
endmodule
|
//without read function
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// --------------------------------------------------------------------
module I8080_Controller#(
I8080_BUS_WIDTH = 32
)(
// global clock & reset
clk,
reset_n,
// mm slave
s_chipselect_n,
// s_read,
s_write_n,
// s_readdata,
s_writedata,
s_address,
i8080_cs,
i8080_rs,//command/data
i8080_rd,
i8080_wr,
i8080_data,
);
// global clock & reset
input clk;
input reset_n;
// mm slave
input s_chipselect_n;
//input s_read;
input s_write_n;
//output reg [31:0] s_readdata;
input [31:0] s_writedata;
input [2:0] s_address;
output i8080_cs;
output i8080_rs;//command/data
output i8080_rd;
output i8080_wr;
output [31:0] i8080_data;
assign i8080_cs = s_chipselect_n;
assign i8080_rs = s_address[2];
assign i8080_rd = 1'b1;
assign i8080_wr = s_write_n;
assign i8080_data = s_writedata[31:0];
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_ncio_mrqq_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
//
// Description: Mondo Request Queue Control
// Top level Module: jbi_ncio_mrqq_ctl
// Where Instantiated: jbi_ncio
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
`include "jbi.h"
module jbi_ncio_mrqq_ctl(/*AUTOARG*/
// Outputs
jbi_iob_mondo_vld, jbi_iob_mondo_data, iob_jbi_mondo_ack_ff,
iob_jbi_mondo_nack_ff, makq_push, makq_wdata, makq_nack, mrqq_wr_en,
mrqq_rd_en, mrqq_waddr, mrqq_wdata, mrqq_raddr, mtag_csn_wr,
mtag_waddr, mtag_raddr,
// Inputs
clk, rst_l, csr_jbi_config2_ord_int, io_jbi_j_ad_ff,
min_mondo_hdr_push, min_mondo_data_push, min_mondo_data_err,
iob_jbi_mondo_ack, iob_jbi_mondo_nack, mrqq_rdata, mtag_byps
);
input clk;
input rst_l;
// CSR Interface
input csr_jbi_config2_ord_int;
// Memory In (min) Interface
input [127:0] io_jbi_j_ad_ff; // flopped version of j_ad
input min_mondo_hdr_push;
input min_mondo_data_push;
input min_mondo_data_err;
// IOB Interface.
input iob_jbi_mondo_ack;
input iob_jbi_mondo_nack;
output jbi_iob_mondo_vld;
output [`JBI_IOB_MONDO_BUS_WIDTH-1:0] jbi_iob_mondo_data;
// Mondo Ack Interface
output iob_jbi_mondo_ack_ff;
output iob_jbi_mondo_nack_ff;
output makq_push;
output [`JBI_MAKQ_WIDTH-1:0] makq_wdata;
output makq_nack;
// Mondo Request Queue Interface
input [`JBI_MRQQ_WIDTH-1:0] mrqq_rdata;
output mrqq_wr_en;
output mrqq_rd_en;
output [`JBI_MRQQ_ADDR_WIDTH-1:0] mrqq_waddr;
output [`JBI_MRQQ_WIDTH-1:0] mrqq_wdata;
output [`JBI_MRQQ_ADDR_WIDTH-1:0] mrqq_raddr;
// Mondo Tag Interface
input mtag_byps;
output mtag_csn_wr;
output [3:0] mtag_waddr;
output [3:0] mtag_raddr;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire jbi_iob_mondo_vld;
wire [`JBI_IOB_MONDO_BUS_WIDTH-1:0] jbi_iob_mondo_data;
wire iob_jbi_mondo_ack_ff;
wire iob_jbi_mondo_nack_ff;
wire makq_push;
wire [`JBI_MAKQ_WIDTH-1:0] makq_wdata;
wire makq_nack;
wire mrqq_wr_en;
wire mrqq_rd_en;
wire [`JBI_MRQQ_ADDR_WIDTH-1:0] mrqq_waddr;
wire [`JBI_MRQQ_WIDTH-1:0] mrqq_wdata;
wire [`JBI_MRQQ_ADDR_WIDTH-1:0] mrqq_raddr;
wire mtag_csn_wr;
wire [3:0] mtag_waddr;
wire [3:0] mtag_raddr;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
parameter POP_HDR0 = 6'b000001,
POP_HDR1 = 6'b000010,
POP_DATA = 6'b000100,
POP_ACK_WAIT = 6'b001000,
POP_ERR0 = 6'b010000,
POP_ERR1 = 6'b100000;
parameter POP_HDR0_BIT = 0,
POP_HDR1_BIT = 1,
POP_DATA_BIT = 2,
POP_SM_WIDTH = 6;
wire [`JBI_AD_INT_AGTID_WIDTH-1:0] agtid_ff;
wire [`JBI_AD_INT_AGTID_WIDTH-1:0] cpuid_ff;
wire [`JBI_MRQQ_ADDR_WIDTH:0] wptr;
wire [`JBI_MRQQ_ADDR_WIDTH:0] rptr;
wire [POP_SM_WIDTH-1:0] pop_sm;
wire [3:0] data_cnt;
wire [`JBI_AD_INT_AGTID_WIDTH-1:0] next_agtid_ff;
wire [`JBI_AD_INT_AGTID_WIDTH-1:0] next_cpuid_ff;
reg [`JBI_MRQQ_ADDR_WIDTH:0] next_wptr;
reg [`JBI_MRQQ_ADDR_WIDTH:0] next_rptr;
reg [POP_SM_WIDTH-1:0] next_pop_sm;
wire [3:0] next_data_cnt;
wire data_cnt_rst_l;
wire mrqq_drdy;
wire mrqq_pop;
wire [127:0] mrqq_rdata_data;
reg [`JBI_IOB_MONDO_BUS_WIDTH-1:0] mondo_data;
wire next_jbi_iob_mondo_vld;
reg [`JBI_IOB_MONDO_BUS_WIDTH-1:0] next_jbi_iob_mondo_data;wire [`JBI_MRQQ_ADDR_WIDTH:0] wptr_d1;
wire [`JBI_MRQQ_ADDR_WIDTH:0] wptr_d2;
//
// Code start here
//
//*******************************************************************************
// Push Transaction into Mondo Request Queue
//*******************************************************************************
// Flop agent id and cpu id during first header cycle and push into mrqq
// with data during following cycle
assign next_agtid_ff = io_jbi_j_ad_ff[`JBI_AD_INT_AGTID_HI:`JBI_AD_INT_AGTID_LO];
assign next_cpuid_ff = io_jbi_j_ad_ff[`JBI_AD_INT_CPUID_HI:`JBI_AD_INT_CPUID_LO];
assign mrqq_wr_en = min_mondo_data_push;
assign mrqq_waddr = wptr[`JBI_MRQQ_ADDR_WIDTH-1:0];
assign mrqq_wdata[`JBI_MRQQ_DATA_HI:`JBI_MRQQ_DATA_LO] = io_jbi_j_ad_ff;
assign mrqq_wdata[`JBI_MRQQ_AGTID_HI:`JBI_MRQQ_AGTID_LO] = agtid_ff;
assign mrqq_wdata[`JBI_MRQQ_CPUID_HI:`JBI_MRQQ_CPUID_LO] = cpuid_ff;
assign mrqq_wdata[`JBI_MRQQ_ERR] = min_mondo_data_err;
//-------------------
// Pointer Management
//-------------------
always @ ( /*AUTOSENSE*/min_mondo_data_push or wptr) begin
if (min_mondo_data_push)
next_wptr = wptr + 1'b1;
else
next_wptr = wptr;
end
//*******************************************************************************
// Pop Transaction from Mondo Request Queue
//*******************************************************************************
//-------------------
// Pop State Machine
//-------------------
// mondos with par error are not forwarded to cmp bit are nacked on JBUS
assign mrqq_drdy = ~(rptr == wptr_d2)
& ( mtag_byps
| ~csr_jbi_config2_ord_int); // turn off wr-int ordering
always @ ( /*AUTOSENSE*/data_cnt or iob_jbi_mondo_ack_ff
or iob_jbi_mondo_nack_ff or mrqq_drdy or mrqq_rdata
or pop_sm) begin
case (pop_sm)
POP_HDR0: begin
if (mrqq_drdy) begin
if (mrqq_rdata[`JBI_MRQQ_ERR])
next_pop_sm = POP_ERR0;
else
next_pop_sm = POP_HDR1;
end
else
next_pop_sm = POP_HDR0;
end
POP_HDR1: next_pop_sm = POP_DATA;
POP_DATA: begin
if (&data_cnt)
next_pop_sm = POP_ACK_WAIT;
else
next_pop_sm = POP_DATA;
end
POP_ACK_WAIT: begin
if (iob_jbi_mondo_ack_ff | iob_jbi_mondo_nack_ff)
next_pop_sm = POP_HDR0;
else
next_pop_sm = POP_ACK_WAIT;
end
POP_ERR0: next_pop_sm = POP_ERR1;
POP_ERR1: next_pop_sm = POP_HDR0;
// CoverMeter line_off
default: begin
next_pop_sm = {POP_SM_WIDTH{1'bx}};
//synopsys translate_off
$dispmon ("jbi_ncio_mrqq_ctl", 49,"%d %m: pop_sm = %b", $time, pop_sm);
//synopsys translate_on
end
// CoverMeter line_on
endcase
end
assign data_cnt_rst_l = rst_l & pop_sm[POP_DATA_BIT];
assign next_data_cnt = data_cnt + 1'b1;
//-------------------
// Pointer Management
//-------------------
assign mrqq_pop = (pop_sm[POP_DATA_BIT] & (&data_cnt))
| (pop_sm[POP_HDR0_BIT] & mrqq_drdy & mrqq_rdata[`JBI_MRQQ_ERR]); //mondow with par error
always @ ( /*AUTOSENSE*/mrqq_pop or rptr) begin
if (mrqq_pop)
next_rptr = rptr + 1'b1;
else
next_rptr = rptr;
end
assign mrqq_raddr = next_rptr[`JBI_MRQQ_ADDR_WIDTH-1:0];
assign mrqq_rd_en = next_rptr != wptr;
//-------------------
// Drive Data
//-------------------
assign mrqq_rdata_data = mrqq_rdata[`JBI_MRQQ_DATA_HI:`JBI_MRQQ_DATA_LO];
always @ ( /*AUTOSENSE*/data_cnt or mrqq_rdata_data) begin
case (data_cnt)
4'd0: mondo_data = mrqq_rdata_data[127:120];
4'd1: mondo_data = mrqq_rdata_data[119:112];
4'd2: mondo_data = mrqq_rdata_data[111:104];
4'd3: mondo_data = mrqq_rdata_data[103: 96];
4'd4: mondo_data = mrqq_rdata_data[ 95: 88];
4'd5: mondo_data = mrqq_rdata_data[ 87: 80];
4'd6: mondo_data = mrqq_rdata_data[ 79: 72];
4'd7: mondo_data = mrqq_rdata_data[ 71: 64];
4'd8: mondo_data = mrqq_rdata_data[ 63: 56];
4'd9: mondo_data = mrqq_rdata_data[ 55: 48];
4'd10: mondo_data = mrqq_rdata_data[ 47: 40];
4'd11: mondo_data = mrqq_rdata_data[ 39: 32];
4'd12: mondo_data = mrqq_rdata_data[ 31: 24];
4'd13: mondo_data = mrqq_rdata_data[ 23: 16];
4'd14: mondo_data = mrqq_rdata_data[ 15: 8];
4'd15: mondo_data = mrqq_rdata_data[ 7: 0];
default: mondo_data = {8{1'bx}};
endcase
end
assign next_jbi_iob_mondo_vld = (pop_sm[POP_HDR0_BIT] & mrqq_drdy & ~mrqq_rdata[`JBI_MRQQ_ERR]) //next_pop_sm==POP_HDR1
| pop_sm[POP_HDR1_BIT]
| pop_sm[POP_DATA_BIT];
always @ ( /*AUTOSENSE*/mondo_data or mrqq_rdata or pop_sm) begin
if (pop_sm[POP_HDR0_BIT])
next_jbi_iob_mondo_data = {{`JBI_IOB_MONDO_RSV1_WIDTH{1'b0}},
mrqq_rdata[`JBI_MRQQ_CPUID_HI:`JBI_MRQQ_CPUID_LO]};
else if (pop_sm[POP_HDR1_BIT])
next_jbi_iob_mondo_data = {{`JBI_IOB_MONDO_RSV0_WIDTH{1'b0}},
mrqq_rdata[`JBI_MRQQ_AGTID_HI:`JBI_MRQQ_AGTID_LO]};
else
next_jbi_iob_mondo_data = mondo_data;
end
//--------------------------
// Transfer Data to Outbound
//--------------------------
assign makq_push = pop_sm[POP_HDR1_BIT]
| (pop_sm[POP_HDR0_BIT] & mrqq_drdy & mrqq_rdata[`JBI_MRQQ_ERR]);
assign makq_wdata[`JBI_MAKQ_CPUID_HI:`JBI_MAKQ_CPUID_LO] = mrqq_rdata[`JBI_MRQQ_CPUID_HI:`JBI_MRQQ_CPUID_LO];
assign makq_wdata[`JBI_MAKQ_AGTID_HI:`JBI_MAKQ_AGTID_LO] = mrqq_rdata[`JBI_MRQQ_AGTID_HI:`JBI_MRQQ_AGTID_LO];
assign makq_nack = mrqq_rdata[`JBI_MRQQ_ERR];
//*******************************************************************************
// Mondo Tag Queue
//*******************************************************************************
assign mtag_csn_wr = ~min_mondo_hdr_push;
assign mtag_waddr = wptr[`JBI_MRQQ_ADDR_WIDTH-1:0];
assign mtag_raddr = rptr[`JBI_MRQQ_ADDR_WIDTH-1:0];
//*******************************************************************************
// DFF Instantiations
//*******************************************************************************
dff_ns #(`JBI_AD_INT_AGTID_WIDTH) u_dff_agtid_ff
(.din(next_agtid_ff),
.clk(clk),
.q(agtid_ff)
);
dff_ns #(`JBI_AD_INT_AGTID_WIDTH) u_dff_cpuid_ff
(.din(next_cpuid_ff),
.clk(clk),
.q(cpuid_ff)
);
dff_ns #(`JBI_IOB_MONDO_BUS_WIDTH) u_dff_jbi_iob_mondo_data
(.din(next_jbi_iob_mondo_data),
.clk(clk),
.q(jbi_iob_mondo_data)
);
//*******************************************************************************
// DFFRL & DFFSL Instantiations
//*******************************************************************************
dffrl_ns #(POP_SM_WIDTH-1) u_dffrl_pop_sm
(.din(next_pop_sm[POP_SM_WIDTH-1:1]),
.clk(clk),
.rst_l(rst_l),
.q(pop_sm[POP_SM_WIDTH-1:1])
);
dffsl_ns #(1) u_dffrl_pop_sm0
(.din(next_pop_sm[POP_HDR0_BIT]),
.clk(clk),
.set_l(rst_l),
.q(pop_sm[POP_HDR0_BIT])
);
dffrl_ns #(`JBI_MRQQ_ADDR_WIDTH+1) u_dffrl_wptr
(.din(next_wptr),
.clk(clk),
.rst_l(rst_l),
.q(wptr)
);
dffrl_ns #(`JBI_MRQQ_ADDR_WIDTH+1) u_dffrl_rptr
(.din(next_rptr),
.clk(clk),
.rst_l(rst_l),
.q(rptr)
);
dffrl_ns #(4) u_dffrl_data_cnt
(.din(next_data_cnt),
.clk(clk),
.rst_l(data_cnt_rst_l),
.q(data_cnt)
);
dffrl_ns #(1) u_dffrl_jbi_iob_mondo_vld
(.din(next_jbi_iob_mondo_vld),
.clk(clk),
.rst_l(rst_l),
.q(jbi_iob_mondo_vld)
);
dffrl_ns #(`JBI_MRQQ_ADDR_WIDTH+1) u_dffrl_wptr_d1
(.din(wptr),
.clk(clk),
.rst_l(rst_l),
.q(wptr_d1)
);
dffrl_ns #(`JBI_MRQQ_ADDR_WIDTH+1) u_dffrl_wptr_d2
(.din(wptr_d1),
.clk(clk),
.rst_l(rst_l),
.q(wptr_d2)
);
dffrl_ns #(1) u_dffrl_iob_jbi_mondo_ack_ff
(.din(iob_jbi_mondo_ack),
.clk(clk),
.rst_l(rst_l),
.q(iob_jbi_mondo_ack_ff)
);
dffrl_ns #(1) u_dffrl_iob_jbi_mondo_nack_ff
(.din(iob_jbi_mondo_nack),
.clk(clk),
.rst_l(rst_l),
.q(iob_jbi_mondo_nack_ff)
);
//synopsys translate_off
//*******************************************************************************
// Rule Checks
//*******************************************************************************
wire mrqq_empty = rptr == wptr;
wire mrqq_full = wptr[`JBI_MRQQ_ADDR_WIDTH] != rptr[`JBI_MRQQ_ADDR_WIDTH]
& wptr[`JBI_MRQQ_ADDR_WIDTH-1:0] == rptr[`JBI_MRQQ_ADDR_WIDTH-1:0];
always @ ( /*AUTOSENSE*/min_mondo_data_push or mrqq_full) begin
@clk;
if (mrqq_full && min_mondo_data_push)
$dispmon ("jbi_ncio_mrqq_ctl", 49,"%d %m: ERROR - MRQQ overflow!", $time);
end
always @ ( /*AUTOSENSE*/mrqq_empty or mrqq_pop) begin
@clk;
if (mrqq_empty && mrqq_pop)
$dispmon ("jbi_ncio_mrqq_ctl", 49,"%d %m: ERROR - MRQQ underflow!", $time);
end
//*******************************************************************************
// Event Coverage Signals
//*******************************************************************************
wire ev_mrqq_drdy_stall = ~(rptr == wptr_d2)
& ~mtag_byps
& csr_jbi_config2_ord_int; // turn off wr-int ordering
//synopsys translate_on
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-sense-defines-constant:t
// End:
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 24.04.2017 13:28:22
// Design Name:
// Module Name: dragster_configurator
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dragster_configurator #
(
)
(
input clk,
input reset_n,
input wire miso,
output wire mosi,
output wire sclk,
output wire[1:0] ss_n
);
reg [15:0] command_buffer;
wire[7:0] incoming_data;
reg [3:0] register_counter;
reg configuration_done;
reg [1:0] slave;
reg enable;
reg start_transaction;
wire end_of_transaction;
//supply1 vcc;
/* wire internal_reset_n;
wire internal_reset_clk;
assign internal_reset_clk = clk & !internal_reset_n;*/
// enable generator
//FDRE reset_generator(.R(reset_n), .CE(vcc), .D(vcc), .C(clk), .Q(internal_reset));
//FDCE reset_generator(.CLR(~reset_n), .CE(vcc), .D(vcc), .C(clk), .Q(internal_reset_n));
//FDRE enable_generator(.R(enable), .CE(~busy & ~configuration_done & reset_n), .D(vcc), .C(clk), .Q(enable));
quick_spi spi_iml(
.clk(clk),
.reset_n(reset_n),
.enable(enable),
.start_transaction(start_transaction),
.slave(slave),
.incoming_data(incoming_data),
.outgoing_data(command_buffer),
.operation(1'b1),
.end_of_transaction(end_of_transaction),
.miso(miso),
.sclk(sclk),
.ss_n(ss_n),
.mosi(mosi));
always @ (posedge clk) begin
if(!reset_n) begin
register_counter <= 0;
end
else begin
if(!register_counter) begin
enable <= 1'b1;
start_transaction <= 1'b1;
command_buffer <= get_dragster_config(register_counter);
register_counter <= register_counter + 1;
end
if(end_of_transaction) begin
if(register_counter < 4) begin
command_buffer <= get_dragster_config(register_counter);
register_counter <= register_counter + 1;
end
if(register_counter == 4) begin
enable <= 1'b0;
start_transaction <= 1'b0;
end
end
end
end
function[15:0] get_dragster_config(reg [3:0] index);
reg[15:0] result;
begin
case (index)
0:
begin
// control register 3
result = {8'b00010011,8'b00000101};
end
1:
begin
// control register 2
result = {8'b00110010, 8'b00000010};
end
2: begin
// Inversed ADC gain register
result = {8'b11000000, 8'b00000011};
end
3:
begin
// end of range
result = {8'b00000111 /*8'b00001000*/, 8'b00001001};
end
4:
begin
// control register 1
result = {8'b10101001, 8'b00000001};
end
default:
begin
result = 16'b0000000000000000;
end
endcase
get_dragster_config = result;
end
endfunction
endmodule
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: hmc_controller_top
*
*/
`default_nettype none
module openhmc_top #(
//Define width of the datapath
parameter LOG_FPW = 2, //Legal Values: 1,2,3
parameter FPW = 4, //Legal Values: 2,4,6,8
parameter DWIDTH = FPW*128, //Leave untouched
//Define HMC interface width
parameter LOG_NUM_LANES = 3, //Set 3 for half-width, 4 for full-width
parameter NUM_LANES = 2**LOG_NUM_LANES, //Leave untouched
parameter NUM_DATA_BYTES = FPW*16, //Leave untouched
//Define width of the register file
parameter HMC_RF_WWIDTH = 64,
parameter HMC_RF_RWIDTH = 64,
parameter HMC_RF_AWIDTH = 4,
//Configure the Functionality
parameter LOG_MAX_RTC = 8, //Set the depth of the RX input buffer. Must be >= LOG(rf_rx_buffer_rtc) in the RF
parameter HMC_RX_AC_COUPLED = 1, //Set to 0 to remove the run length limiter, saves logic and 1 cycle delay
parameter CTRL_LANE_POLARITY = 1, //Set to 0 if lane polarity is not applicable or performed by the transceivers, saves logic and 1 cycle delay
parameter CTRL_LANE_REVERSAL = 1, //Set to 0 if lane reversal is not applicable or performed by the transceivers, saves logic
//Set the direction of bitslip. Set to 1 if bitslip performs a shift right, otherwise set to 0 (see the corresponding transceiver user guide)
parameter BITSLIP_SHIFT_RIGHT = 1,
//Debug Params
parameter DBG_RX_TOKEN_MON = 1 //Remove the RX Link token monitor, saves logic
) (
//----------------------------------
//----SYSTEM INTERFACES
//----------------------------------
input wire clk_user,
input wire clk_hmc,
input wire res_n_user,
input wire res_n_hmc,
//----------------------------------
//----Connect AXI Ports
//----------------------------------
//From AXI to HMC Ctrl TX
input wire s_axis_tx_TVALID,
output wire s_axis_tx_TREADY,
input wire [DWIDTH-1:0] s_axis_tx_TDATA,
input wire [NUM_DATA_BYTES-1:0] s_axis_tx_TUSER,
//From HMC Ctrl RX to AXI
output wire m_axis_rx_TVALID,
input wire m_axis_rx_TREADY,
output wire [DWIDTH-1:0] m_axis_rx_TDATA,
output wire [NUM_DATA_BYTES-1:0] m_axis_rx_TUSER,
//----------------------------------
//----Connect Transceiver
//----------------------------------
output wire [DWIDTH-1:0] phy_data_tx_link2phy,
input wire [DWIDTH-1:0] phy_data_rx_phy2link,
output wire [NUM_LANES-1:0] phy_bit_slip,
output wire [NUM_LANES-1:0] phy_lane_polarity, //All 0 if CTRL_LANE_POLARITY=1
input wire phy_ready,
//----------------------------------
//----Connect HMC
//----------------------------------
output wire P_RST_N,
output wire hmc_LxRXPS,
input wire hmc_LxTXPS,
input wire FERR_N, //Not connected
//----------------------------------
//----Connect RF
//----------------------------------
input wire [HMC_RF_AWIDTH-1:0] rf_address,
output wire [HMC_RF_RWIDTH-1:0] rf_read_data,
output wire rf_invalid_address,
output wire rf_access_complete,
input wire rf_read_en,
input wire rf_write_en,
input wire [HMC_RF_WWIDTH-1:0] rf_write_data
);
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
// ----Assign AXI interface wires
wire [4*FPW-1:0] m_axis_rx_TUSER_temp;
assign m_axis_rx_TUSER = {{NUM_DATA_BYTES-(4*FPW){1'b0}}, m_axis_rx_TUSER_temp};
wire s_axis_tx_TREADY_n;
assign s_axis_tx_TREADY = ~s_axis_tx_TREADY_n;
wire m_axis_rx_TVALID_n;
assign m_axis_rx_TVALID = ~m_axis_rx_TVALID_n;
// ----TX FIFO Wires
wire [DWIDTH-1:0] tx_d_in_data;
wire tx_shift_out;
wire tx_empty;
wire tx_a_empty;
wire [3*FPW-1:0] tx_d_in_ctrl;
// ----RX FIFO Wires
wire [DWIDTH-1:0] rx_d_in_data;
wire rx_shift_in;
wire rx_full;
wire rx_a_full;
wire [4*FPW-1:0] rx_d_in_ctrl;
// ----RX LINK TO TX LINK
wire rx2tx_link_retry;
wire rx2tx_error_abort_mode;
wire rx2tx_error_abort_mode_cleared;
wire [7:0] rx2tx_hmc_frp;
wire [7:0] rx2tx_rrp;
wire [7:0] rx2tx_returned_tokens;
wire [LOG_FPW:0] rx2tx_hmc_tokens_to_return;
wire [LOG_FPW:0] rx2tx_hmc_poisoned_tokens_to_return;
// ----Register File
//Counter
wire rf_cnt_retry;
wire rf_run_length_bit_flip;
wire rf_error_abort_not_cleared;
wire [HMC_RF_RWIDTH-1:0] rf_cnt_poisoned;
wire [HMC_RF_RWIDTH-1:0] rf_cnt_p;
wire [HMC_RF_RWIDTH-1:0] rf_cnt_np;
wire [HMC_RF_RWIDTH-1:0] rf_cnt_r;
wire [HMC_RF_RWIDTH-1:0] rf_cnt_rsp_rcvd;
//Status
wire [1:0] rf_link_status;
wire [2:0] rf_hmc_init_status;
wire [1:0] rf_tx_init_status;
wire [9:0] rf_hmc_tokens_av;
wire [9:0] rf_rx_tokens_av;
wire rf_hmc_sleep;
//Init Status
wire rf_all_descramblers_aligned;
wire [NUM_LANES-1:0] rf_descrambler_aligned;
wire [NUM_LANES-1:0] rf_descrambler_part_aligned;
//Control
wire [5:0] rf_bit_slip_time;
wire rf_hmc_init_cont_set;
wire rf_set_hmc_sleep;
wire rf_scrambler_disable;
wire [NUM_LANES-1:0] rf_lane_polarity;
wire [NUM_LANES-1:0] rf_descramblers_locked;
wire [9:0] rf_rx_buffer_rtc;
wire rf_lane_reversal_detected;
wire [4:0] rf_irtry_received_threshold;
wire [4:0] rf_irtry_to_send;
wire rf_run_length_enable;
wire [2:0] rf_first_cube_ID;
//Debug
wire rf_dbg_dont_send_tret;
wire rf_dbg_halt_on_error_abort;
wire rf_dbg_halt_on_tx_retry;
// ----Assign PHY wires
assign phy_lane_polarity = (CTRL_LANE_POLARITY==1) ? {NUM_LANES{1'b0}} : rf_lane_polarity;
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
//----------------------------------------------------------------------
//-----TX-----TX-----TX-----TX-----TX-----TX-----TX-----TX-----TX-----TX
//----------------------------------------------------------------------
openhmc_async_fifo #(
.DWIDTH(DWIDTH+(FPW*3)),
.ENTRIES(16)
) fifo_tx_data (
//System
.si_clk(clk_user),
.so_clk(clk_hmc),
.si_res_n(res_n_user),
.so_res_n(res_n_hmc),
//From AXI-4 TX IF
.d_in({s_axis_tx_TUSER[(FPW*3)-1:0],s_axis_tx_TDATA}),
.shift_in(s_axis_tx_TVALID && s_axis_tx_TREADY),
.full(s_axis_tx_TREADY_n),
.almost_full(),
//To TX Link Logic
.d_out({tx_d_in_ctrl,tx_d_in_data}),
.shift_out(tx_shift_out),
.empty(tx_empty),
.almost_empty(tx_a_empty)
);
tx_link #(
.LOG_FPW(LOG_FPW),
.FPW(FPW),
.NUM_LANES(NUM_LANES),
.HMC_PTR_SIZE(8),
.HMC_RF_RWIDTH(HMC_RF_RWIDTH),
.HMC_RX_AC_COUPLED(HMC_RX_AC_COUPLED),
//Debug
.DBG_RX_TOKEN_MON(DBG_RX_TOKEN_MON)
) tx_link_I(
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
.clk(clk_hmc),
.res_n(res_n_hmc),
//----------------------------------
//----TO HMC PHY
//----------------------------------
.phy_scrambled_data_out(phy_data_tx_link2phy),
//----------------------------------
//----HMC IF
//----------------------------------
.hmc_LxRXPS(hmc_LxRXPS),
.hmc_LxTXPS(hmc_LxTXPS),
//----------------------------------
//----FROM HMC_TX_HTAX_LOGIC
//----------------------------------
.d_in_data(tx_d_in_data),
.d_in_flit_is_valid(tx_d_in_ctrl[FPW-1:0]),
.d_in_flit_is_hdr(tx_d_in_ctrl[(2*FPW)-1:1*FPW]),
.d_in_flit_is_tail(tx_d_in_ctrl[(3*FPW)-1:(2*FPW)]),
.d_in_empty(tx_empty),
.d_in_a_empty(tx_a_empty),
.d_in_shift_out(tx_shift_out),
//----------------------------------
//----RX Block
//----------------------------------
.rx_force_tx_retry(rx2tx_link_retry),
.rx_error_abort_mode(rx2tx_error_abort_mode),
.rx_error_abort_mode_cleared(rx2tx_error_abort_mode_cleared),
.rx_hmc_frp(rx2tx_hmc_frp),
.rx_rrp(rx2tx_rrp),
.rx_returned_tokens(rx2tx_returned_tokens),
.rx_hmc_tokens_to_return(rx2tx_hmc_tokens_to_return),
.rx_hmc_poisoned_tokens_to_return(rx2tx_hmc_poisoned_tokens_to_return),
//----------------------------------
//----RF
//----------------------------------
//Monitoring 1-cycle set to increment
.rf_cnt_retry(rf_cnt_retry),
.rf_sent_p(rf_cnt_p),
.rf_sent_np(rf_cnt_np),
.rf_sent_r(rf_cnt_r),
.rf_run_length_bit_flip(rf_run_length_bit_flip),
.rf_error_abort_not_cleared(rf_error_abort_not_cleared),
//Status
.rf_hmc_is_in_sleep(rf_hmc_sleep),
.rf_hmc_received_init_null(rf_hmc_init_status[0]),
.rf_link_is_up(rf_link_status[1]),
.rf_descramblers_aligned(rf_all_descramblers_aligned),
.rf_tx_init_status(rf_tx_init_status),
.rf_hmc_tokens_av(rf_hmc_tokens_av),
.rf_rx_tokens_av(rf_rx_tokens_av),
//Control
.rf_hmc_sleep_requested(rf_set_hmc_sleep),
.rf_hmc_init_cont_set(rf_hmc_init_cont_set),
.rf_scrambler_disable(rf_scrambler_disable),
.rf_rx_buffer_rtc(rf_rx_buffer_rtc),
.rf_first_cube_ID(rf_first_cube_ID),
.rf_irtry_to_send(rf_irtry_to_send),
.rf_run_length_enable(rf_run_length_enable),
//Debug
.rf_dbg_dont_send_tret(rf_dbg_dont_send_tret),
.rf_dbg_halt_on_error_abort(rf_dbg_halt_on_error_abort),
.rf_dbg_halt_on_tx_retry(rf_dbg_halt_on_tx_retry)
);
//----------------------------------------------------------------------
//-----RX-----RX-----RX-----RX-----RX-----RX-----RX-----RX-----RX-----RX
//----------------------------------------------------------------------
rx_link #(
.LOG_FPW(LOG_FPW),
.FPW(FPW),
.LOG_NUM_LANES(LOG_NUM_LANES),
.HMC_RF_RWIDTH(HMC_RF_RWIDTH),
//Configure the functionality
.LOG_MAX_RTC(LOG_MAX_RTC),
.CTRL_LANE_POLARITY(CTRL_LANE_POLARITY),
.CTRL_LANE_REVERSAL(CTRL_LANE_REVERSAL),
.BITSLIP_SHIFT_RIGHT(BITSLIP_SHIFT_RIGHT)
) rx_link_I (
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
.clk(clk_hmc),
.res_n(res_n_hmc),
//----------------------------------
//----TO HMC PHY
//----------------------------------
.phy_scrambled_data_in(phy_data_rx_phy2link),
.init_bit_slip(phy_bit_slip),
//----------------------------------
//----FROM TO RX HTAX FIFO
//----------------------------------
.d_out_fifo_data(rx_d_in_data),
.d_out_fifo_full(rx_full),
.d_out_fifo_a_full(rx_a_full),
.d_out_fifo_shift_in(rx_shift_in),
.d_out_fifo_ctrl(rx_d_in_ctrl),
//----------------------------------
//----TO TX Block
//----------------------------------
.tx_link_retry(rx2tx_link_retry),
.tx_error_abort_mode(rx2tx_error_abort_mode),
.tx_error_abort_mode_cleared(rx2tx_error_abort_mode_cleared),
.tx_hmc_frp(rx2tx_hmc_frp),
.tx_rrp(rx2tx_rrp),
.tx_returned_tokens(rx2tx_returned_tokens),
.tx_hmc_tokens_to_return(rx2tx_hmc_tokens_to_return),
.tx_hmc_poisoned_tokens_to_return(rx2tx_hmc_poisoned_tokens_to_return),
//----------------------------------
//----RF
//----------------------------------
//Monitoring 1-cycle set to increment
.rf_cnt_poisoned(rf_cnt_poisoned),
.rf_cnt_rsp(rf_cnt_rsp_rcvd),
//Status
.rf_link_status(rf_link_status),
.rf_hmc_init_status(rf_hmc_init_status),
.rf_hmc_sleep(rf_hmc_sleep),
//Init Status
.rf_all_descramblers_aligned(rf_all_descramblers_aligned),
.rf_descrambler_aligned(rf_descrambler_aligned),
.rf_descrambler_part_aligned(rf_descrambler_part_aligned),
.rf_descramblers_locked(rf_descramblers_locked),
.rf_tx_sends_ts1(rf_tx_init_status[1] && !rf_tx_init_status[0]),
//Control
.rf_bit_slip_time(rf_bit_slip_time),
.rf_hmc_init_cont_set(rf_hmc_init_cont_set),
.rf_lane_polarity(rf_lane_polarity),
.rf_scrambler_disable(rf_scrambler_disable),
.rf_lane_reversal_detected(rf_lane_reversal_detected),
.rf_irtry_received_threshold(rf_irtry_received_threshold)
);
openhmc_async_fifo #(
.DWIDTH(DWIDTH+(FPW*4)),
.ENTRIES(16)
) fifo_rx_data(
//System
.si_clk(clk_hmc),
.so_clk(clk_user),
.si_res_n(res_n_hmc),
.so_res_n(res_n_user),
//To RX LINK Logic
.d_in({rx_d_in_ctrl,rx_d_in_data}),
.shift_in(rx_shift_in),
.full(rx_full),
.almost_full(rx_a_full),
//AXI-4 RX IF
.d_out({m_axis_rx_TUSER_temp,m_axis_rx_TDATA}),
.shift_out(m_axis_rx_TVALID && m_axis_rx_TREADY),
.empty(m_axis_rx_TVALID_n),
.almost_empty()
);
//----------------------------------------------------------------------
//---Register File---Register File---Register File---Register File---Reg
//----------------------------------------------------------------------
//Instantiate register file depending on the number of lanes
generate
if(NUM_LANES==8) begin : register_file_8x
openhmc_8x_rf openhmc_rf_I (
//system IF
.res_n(res_n_hmc),
.clk(clk_hmc),
//rf access
.address(rf_address),
.read_data(rf_read_data),
.invalid_address(rf_invalid_address),
.access_complete(rf_access_complete),
.read_en(rf_read_en),
.write_en(rf_write_en),
.write_data(rf_write_data),
//status registers
.status_general_link_up_next(rf_link_status[1]),
.status_general_link_training_next(rf_link_status[0]),
.status_general_sleep_mode_next(rf_hmc_sleep),
.status_general_phy_ready_next(phy_ready),
.status_general_lanes_reversed_next(rf_lane_reversal_detected),
.status_general_hmc_tokens_remaining_next(rf_hmc_tokens_av),
.status_general_rx_tokens_remaining_next(rf_rx_tokens_av),
.status_general_lane_polarity_reversed_next(rf_lane_polarity),
//init status
.status_init_lane_descramblers_locked_next(rf_descramblers_locked),
.status_init_descrambler_part_aligned_next(rf_descrambler_part_aligned),
.status_init_descrambler_aligned_next(rf_descrambler_aligned),
.status_init_all_descramblers_aligned_next(rf_all_descramblers_aligned),
.status_init_tx_init_status_next(rf_tx_init_status),
.status_init_hmc_init_TS1_next(rf_hmc_init_status[0]),
//counters
.sent_np_cnt_next(rf_cnt_np),
.sent_p_cnt_next(rf_cnt_p),
.sent_r_cnt_next(rf_cnt_r),
.poisoned_packets_cnt_next(rf_cnt_poisoned),
.rcvd_rsp_cnt_next(rf_cnt_rsp_rcvd),
//Single bit counter
.tx_link_retries_count_countup(rf_cnt_retry),
.errors_on_rx_count_countup(rx2tx_error_abort_mode_cleared),
.run_length_bit_flip_count_countup(rf_run_length_bit_flip),
.error_abort_not_cleared_count_countup(rf_error_abort_not_cleared),
//control
.control_p_rst_n(P_RST_N),
.control_hmc_init_cont_set(rf_hmc_init_cont_set),
.control_set_hmc_sleep(rf_set_hmc_sleep),
.control_scrambler_disable(rf_scrambler_disable),
.control_run_length_enable(rf_run_length_enable),
.control_first_cube_ID(rf_first_cube_ID),
.control_debug_dont_send_tret(rf_dbg_dont_send_tret),
.control_debug_halt_on_error_abort(rf_dbg_halt_on_error_abort),
.control_debug_halt_on_tx_retry(rf_dbg_halt_on_tx_retry),
.control_rx_token_count(rf_rx_buffer_rtc),
.control_irtry_received_threshold(rf_irtry_received_threshold),
.control_irtry_to_send(rf_irtry_to_send),
.control_bit_slip_time(rf_bit_slip_time)
);
end else begin : register_file_16x
openhmc_16x_rf openhmc_rf_I (
//system IF
.res_n(res_n_hmc),
.clk(clk_hmc),
//rf access
.address(rf_address),
.read_data(rf_read_data),
.invalid_address(rf_invalid_address),
.access_complete(rf_access_complete),
.read_en(rf_read_en),
.write_en(rf_write_en),
.write_data(rf_write_data),
//status registers
.status_general_link_up_next(rf_link_status[1]),
.status_general_link_training_next(rf_link_status[0]),
.status_general_sleep_mode_next(rf_hmc_sleep),
.status_general_phy_ready_next(phy_ready),
.status_general_lanes_reversed_next(rf_lane_reversal_detected),
.status_general_hmc_tokens_remaining_next(rf_hmc_tokens_av),
.status_general_rx_tokens_remaining_next(rf_rx_tokens_av),
.status_general_lane_polarity_reversed_next(rf_lane_polarity),
//init status
.status_init_lane_descramblers_locked_next(rf_descramblers_locked),
.status_init_descrambler_part_aligned_next(rf_descrambler_part_aligned),
.status_init_descrambler_aligned_next(rf_descrambler_aligned),
.status_init_all_descramblers_aligned_next(rf_all_descramblers_aligned),
.status_init_tx_init_status_next(rf_tx_init_status),
.status_init_hmc_init_TS1_next(rf_hmc_init_status[0]),
//counters
.sent_np_cnt_next(rf_cnt_np),
.sent_p_cnt_next(rf_cnt_p),
.sent_r_cnt_next(rf_cnt_r),
.poisoned_packets_cnt_next(rf_cnt_poisoned),
.rcvd_rsp_cnt_next(rf_cnt_rsp_rcvd),
//Single bit counter
.tx_link_retries_count_countup(rf_cnt_retry),
.errors_on_rx_count_countup(rx2tx_error_abort_mode_cleared),
.run_length_bit_flip_count_countup(rf_run_length_bit_flip),
.error_abort_not_cleared_count_countup(rf_error_abort_not_cleared),
//control
.control_p_rst_n(P_RST_N),
.control_hmc_init_cont_set(rf_hmc_init_cont_set),
.control_set_hmc_sleep(rf_set_hmc_sleep),
.control_scrambler_disable(rf_scrambler_disable),
.control_run_length_enable(rf_run_length_enable),
.control_first_cube_ID(rf_first_cube_ID),
.control_debug_dont_send_tret(rf_dbg_dont_send_tret),
.control_debug_halt_on_error_abort(rf_dbg_halt_on_error_abort),
.control_debug_halt_on_tx_retry(rf_dbg_halt_on_tx_retry),
.control_rx_token_count(rf_rx_buffer_rtc),
.control_irtry_received_threshold(rf_irtry_received_threshold),
.control_irtry_to_send(rf_irtry_to_send),
.control_bit_slip_time(rf_bit_slip_time)
);
end
endgenerate
endmodule
`default_nettype wire
|
/////////////////////////////////
// bsg_nonsynth_dramsim3_unmap //
/////////////////////////////////
`include "bsg_defines.v"
module bsg_nonsynth_dramsim3_unmap
import bsg_dramsim3_pkg::*;
#(parameter `BSG_INV_PARAM(channel_addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(num_channels_p)
, parameter `BSG_INV_PARAM(num_columns_p)
, parameter `BSG_INV_PARAM(num_rows_p)
, parameter `BSG_INV_PARAM(num_ba_p)
, parameter `BSG_INV_PARAM(num_bg_p)
, parameter `BSG_INV_PARAM(num_ranks_p)
, parameter `BSG_INV_PARAM(address_mapping_p)
, parameter `BSG_INV_PARAM(channel_select_p)
, parameter debug_p=0
, parameter lg_num_channels_lp=$clog2(num_channels_p)
, parameter lg_num_columns_lp=$clog2(num_columns_p)
, parameter lg_num_rows_lp=$clog2(num_rows_p)
, parameter lg_num_ba_lp=$clog2(num_ba_p)
, parameter lg_num_bg_lp=$clog2(num_bg_p)
, parameter lg_num_ranks_lp=$clog2(num_ranks_p)
, parameter data_mask_width_lp=(data_width_p>>3)
, parameter byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3)
, parameter addr_width_lp=lg_num_channels_lp+channel_addr_width_p
)
(
input logic [addr_width_lp-1:0] mem_addr_i
, output logic [channel_addr_width_p-1:0] ch_addr_o
);
if (address_mapping_p == e_ro_ra_bg_ba_co_ch) begin
assign ch_addr_o
= {
mem_addr_i[addr_width_lp-1:byte_offset_width_lp+lg_num_channels_lp],
{byte_offset_width_lp{1'b0}}
};
end
else if (address_mapping_p == e_ro_ra_bg_ba_ch_co) begin
assign ch_addr_o
= {
mem_addr_i[addr_width_lp-1:lg_num_channels_lp+lg_num_columns_lp+byte_offset_width_lp],
mem_addr_i[lg_num_columns_lp+byte_offset_width_lp-1:byte_offset_width_lp],
{byte_offset_width_lp{1'b0}}
};
end
else if (address_mapping_p == e_ro_ch_ra_ba_bg_co) begin
localparam mem_co_pos_lp = byte_offset_width_lp;
localparam mem_bg_pos_lp = mem_co_pos_lp + lg_num_columns_lp;
localparam mem_ba_pos_lp = mem_bg_pos_lp + lg_num_bg_lp;
localparam mem_ra_pos_lp = mem_ba_pos_lp + lg_num_ba_lp;
localparam mem_ch_pos_lp = mem_ra_pos_lp + lg_num_ranks_lp;
localparam mem_ro_pos_lp = mem_ch_pos_lp + lg_num_channels_lp;
assign ch_addr_o
= {
mem_addr_i[mem_ro_pos_lp+:lg_num_rows_lp],
{lg_num_ranks_lp!=0{mem_addr_i[mem_ra_pos_lp+:`BSG_MAX(lg_num_ranks_lp, 1)]}},
{lg_num_bg_lp!=0{mem_addr_i[mem_bg_pos_lp+:`BSG_MAX(lg_num_bg_lp, 1)]}},
{lg_num_ba_lp!=0{mem_addr_i[mem_ba_pos_lp+:`BSG_MAX(lg_num_ba_lp, 1)]}},
mem_addr_i[mem_co_pos_lp+:lg_num_columns_lp],
{byte_offset_width_lp{1'b0}}
};
end
endmodule // bsg_nonsynth_dramsim3_unmap
`BSG_ABSTRACT_MODULE(bsg_nonsynth_dramsim3_unmap)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111AI_TB_V
`define SKY130_FD_SC_LS__O2111AI_TB_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o2111ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 C1 = 1'b1;
#280 D1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 C1 = 1'b0;
#460 D1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 D1 = 1'b1;
#660 C1 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 D1 = 1'bx;
#840 C1 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__o2111ai dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111AI_TB_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
//
// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
////////////////////////////////////////////////////////////////////////////////
// Design Name: aurora_64b66b_25p4G_MULTI_GT
//
// Multi GT wrapper for ultrascale series
`timescale 1 ps / 1 ps
`define DLY #1
(* core_generation_info = "aurora_64b66b_25p4G,aurora_64b66b_v11_2_2,{c_aurora_lanes=1,c_column_used=left,c_gt_clock_1=GTYQ0,c_gt_clock_2=None,c_gt_loc_1=1,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=25.4,c_gt_type=GTYE4,c_qpll=true,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=100.0,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=false,c_user_k=false,flow_mode=None,interface_mode=Framing,dataflow_config=Duplex}" *)
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_MULTI_GT
(
// GT reset module interface ports starts
input gtwiz_reset_all_in ,
input gtwiz_reset_clk_freerun_in ,
input gtwiz_reset_tx_pll_and_datapath_in,
input gtwiz_reset_tx_datapath_in ,
input gtwiz_reset_rx_pll_and_datapath_in,
input gtwiz_reset_rx_datapath_in ,
input gtwiz_reset_rx_data_good_in ,
output gtwiz_reset_rx_cdr_stable_out ,
output gtwiz_reset_tx_done_out ,
output gtwiz_reset_rx_done_out ,
output gtwiz_reset_qpll0reset_output ,
// GT reset module interface ports ends
output fabric_pcs_reset ,
output bufg_gt_clr_out ,
input gtwiz_userclk_tx_active_out ,
output userclk_rx_active_out ,
input gt0_gtwiz_reset_qpll0lock_in ,
//--------------------------------------------------------------------------
input gt0_qpll0clk_in ,
input gt0_qpll0refclk_in ,
//--------------------------------------------------------------------------
//____________________________CHANNEL PORTS________________________________
//------------------------------- CPLL Ports -------------------------------
input gt0_gtrefclk0_in,
//-------------------------- Channel - DRP Ports --------------------------
input [9:0] gt0_drpaddr,
input gt0_drp_clk_in,
input [15:0] gt0_drpdi,
output [15:0] gt0_drpdo,
input gt0_drpen,
output gt0_drprdy,
input gt0_drpwe,
//---------------- Receive Ports - FPGA RX Interface Ports -----------------
output gt0_rxusrclk_out,
output gt0_rxusrclk2_out,
//---------------- Transmit Ports - FPGA TX Interface Ports ----------------
input gt0_txusrclk_in,
input gt0_txusrclk2_in,
//----------------------------- Loopback Ports -----------------------------
input [2:0] gt_loopback,
//------------------- RX Initialization and Reset Ports --------------------
input [0:0] gt_eyescanreset,
input [0:0] gt_rxpolarity,
//------------------------ RX Margin Analysis Ports ------------------------
output [0:0] gt_eyescandataerror,
input [0:0] gt_eyescantrigger,
//----------------------- Receive Ports - CDR Ports ------------------------
input gt0_rxcdrovrden_in,
input [0:0] gt_rxcdrhold,
//---------------- Receive Ports - FPGA RX interface Ports -----------------
output [63:0] gt0_rxdata_out,
//---------------------- Receive Ports - RX AFE Ports ----------------------
input gt0_gthrxn_in,
input gt0_gthrxp_in,
//----------------- Receive Ports - RX Buffer Bypass Ports -----------------
output [2:0] gt_rxbufstatus,
//------------------ Receive Ports - RX Equailizer Ports -------------------
input [0:0] gt_rxdfelpmreset,
//------------- Receive Ports - RX Fabric Output Control Ports -------------
output gt0_rxoutclk_out,
//-------------------- Receive Ports - RX Gearbox Ports --------------------
output gt0_rxdatavalid_out,
output [1:0] gt0_rxheader_out,
output gt0_rxheadervalid_out,
//------------------- Receive Ports - RX Gearbox Ports --------------------
input gt0_rxgearboxslip_in,
//---------------- Receive Ports - RX Margin Analysis ports ----------------
input [0:0] gt_rxlpmen,
//----------- Receive Ports - RX Initialization and Reset Ports ------------
input [0:0] gt_gtrxreset,
//------------ Receive Ports -RX Initialization and Reset Ports ------------
output [0:0] gt_rxresetdone,
//---------------------- TX Configurable Driver Ports ----------------------
input [4:0] gt_txpostcursor,
//------------------- TX Initialization and Reset Ports --------------------
input [0:0] gt_gttxreset,
//------------ Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
input [1:0] gt0_txheader_in,
//------------- Transmit Ports - TX Configurable Driver Ports --------------
input [4:0] gt_txdiffctrl,
output [15:0] gt_dmonitorout,
//---------------- Transmit Ports - TX Data Path interface -----------------
input [63:0] gt0_txdata_in,
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
output gt0_gthtxn_out,
output gt0_gthtxp_out,
//--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
output gt0_txoutclk_out,
output gt0_txoutclkfabric_out,
output gt0_txoutclkpcs_out,
//--------------- ---- Transmit Ports - TX Gearbox Ports --------------------
input [6:0] gt0_txsequence_in,
//--------------- Transmit Ports - TX Polarity Control Ports ---------------
input [0:0] gt_txpolarity,
input [0:0] gt_txinhibit,
input [15:0] gt_pcsrsvdin,
input [0:0] gt_txpmareset,
input [0:0] gt_txpcsreset,
input [0:0] gt_rxpcsreset,
input [0:0] gt_rxbufreset,
output [0:0] gt_rxpmaresetdone,
input [4:0] gt_txprecursor,
input [3:0] gt_txprbssel,
input [3:0] gt_rxprbssel,
input [0:0] gt_txprbsforceerr,
output [0:0] gt_rxprbserr,
input [0:0] gt_rxprbscntreset,
output [1:0] gt_txbufstatus,
input [0:0] gt_rxpmareset,
input [2:0] gt_rxrate,
//----------- GT POWERGOOD STATUS Port -----------
output [0:0] gt_powergood,
//----------- Transmit Ports - TX Initialization and Reset Ports -----------
output [0:0] gt_txresetdone
);
//***************************** Wire Declarations *****************************
// Ground and VCC signals
wire tied_to_ground_i;
wire [280:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
//********************************* Main Body of Code**************************
//------------------------- Static signal Assigments ---------------------
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 281'd0;
assign tied_to_vcc_i = 1'b1;
// wire definition starts
wire gtwiz_userclk_tx_active_out_i;
wire [0 : 0] gtrefclk0_in ;
wire [0 : 0] qpll0clk_in ;
wire [0 : 0] qpll0refclk_in ;
wire [0 : 0] qpll1clk_in ='H0 ;
wire [0 : 0] qpll1refclk_in ='H0 ;
wire [0:0] gtwiz_reset_qpll0lock_in;// changed for qpll0 ;
wire gtwiz_reset_qpll0reset_out;
//--------------------------------------------------------------------------
wire [9 : 0 ] drpaddr_in;
wire [0 : 0 ] drpclk_in;
wire [15 : 0 ] drpdi_in ;
wire [15 : 0 ] drpdo_out ;
wire [0 : 0 ] drpen_in ;
wire [0 : 0 ] drprdy_out;
wire [0 : 0 ] drpwe_in ;
wire [2 : 0 ] loopback_in;
wire [1 : 0 ] rxstartofseq_out;
wire [0 : 0 ] eyescanreset_in;
wire [0 : 0 ] rxpolarity_in ;
wire [0 : 0 ] eyescandataerror_out;
wire [0 : 0 ] eyescantrigger_in ;
wire [0 : 0 ] rxcdrovrden_in;
wire [0 : 0 ] rxcdrhold_in ;
wire [63: 0 ] gtwiz_userdata_rx_out;
wire [0 : 0 ] gtyrxn_in ;
wire [0 : 0 ] gtyrxp_in ;
wire [2 : 0 ] rxbufstatus_out ;//
wire [0 : 0 ] rxdfelpmreset_in ;//
wire [0 : 0 ] rxoutclk_out ;//
wire [1 : 0 ] rxdatavalid_out ;//
wire [5 : 0 ] rxheader_out ;//
wire [1 : 0 ] rxheadervalid_out ;//
wire [0 : 0 ] rxgearboxslip_in ;//
wire [0 : 0 ] rxlpmen_in ;//
wire [0 : 0 ] gtrxreset_in ;//
wire [0 : 0 ] rxresetdone_out ;//
wire [4 : 0 ] txpostcursor_in ;//
wire [0 : 0 ] gttxreset_in ;//
//wire [0 : 0 ] txuserrdy_in ;
wire [5 : 0 ] txheader_in ;//
wire [4 : 0 ] txdiffctrl_in ;//
wire [63 : 0 ] gtwiz_userdata_tx_in;//
wire [0 : 0 ] gtytxn_out ;//
wire [0 : 0 ] gtytxp_out ;//
wire [0 : 0 ] txoutclk_out ;//
wire [0 : 0 ] txoutclkfabric_out ;//
wire [0 : 0 ] txoutclkpcs_out ;//
wire [6 : 0 ] txsequence_in ;//
wire [0 : 0 ] txpolarity_in ;//
wire [0 : 0 ] txinhibit_in ;//
wire [0 : 0 ] txpmareset_in ;//
wire [0 : 0 ] txpcsreset_in ;//
wire [0 : 0 ] rxpcsreset_in ;//
wire [0 : 0 ] rxbufreset_in ;//
wire [0 : 0 ] rxpmaresetdone_out ;//
wire [4 : 0 ] txprecursor_in ;//
wire [3 : 0 ] txprbssel_in ;//
wire [3 : 0 ] rxprbssel_in ;//
wire [0 : 0 ] txprbsforceerr_in ;//
wire [0 : 0 ] rxprbserr_out ;//
wire [0 : 0 ] rxprbscntreset_in ;//
wire [15 : 0 ] pcsrsvdin_in ;//
wire [15 : 0 ] dmonitorout_out ;//
wire [1 : 0 ] txbufstatus_out ;//
wire [0 : 0 ] rxpmareset_in ;//
wire [2 : 0 ] rxrate_in ;//
wire [0 : 0 ] txresetdone_out ;//
wire [0 : 0 ] txusrclk_in ;
wire [0 : 0 ] txusrclk2_in ;
wire [0 : 0 ] rxusrclk_in ;
wire [0 : 0 ] rxusrclk2_in ;
reg [9:0] fabric_pcs_rst_extend_cntr = 10'b0; // 10 bit counter
reg [7:0] usrclk_rx_active_in_extend_cntr = 8'b0 ; // 8 bit counter
reg [7:0] usrclk_tx_active_in_extend_cntr = 8'b0 ; // 8 bit counter
wire [0 : 0 ] txpmaresetdone_out;
wire [0 : 0 ] txpmaresetdone_int;
wire [0 : 0 ] rxpmaresetdone_int;
wire [0 : 0 ] gtpowergood_out;
reg gtwiz_userclk_rx_reset_in_r=1'b0;
// Clocking module is outside of GT.
wire gtwiz_userclk_tx_active_in;
wire gtwiz_userclk_rx_active_in;
wire gtwiz_userclk_rx_usrclk2_out;// signals from Rx clocking module
wire gtwiz_userclk_rx_usrclk_out; // signals from Rx clocking module
wire gtwiz_userclk_tx_usrclk2_out;// signals from Tx clocking module
//wire gtwiz_userclk_tx_usrclk_out; // signals from Tx clocking module
wire gtwiz_userclk_tx_reset_in ;
wire gtwiz_userclk_rx_reset_in ;
// wire definition ends
// assignment starts
//--------------------------------------------------------------------------
// Power good assignment
assign gt_powergood = gtpowergood_out;
// start of QPLL loop
assign gtwiz_reset_qpll0lock_in = gt0_gtwiz_reset_qpll0lock_in;
//--------------------------------------------------------------------------
assign qpll0clk_in[0] = gt0_qpll0clk_in ;
assign qpll0refclk_in[0] = gt0_qpll0refclk_in ;
assign gtwiz_reset_qpll0reset_output = gtwiz_reset_qpll0reset_out;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
assign qpll1clk_in ='H0 ;
assign qpll1refclk_in ='H0 ;
// end of QPLL loop
//--------------------------------------------------------------------------
//--------- Port interface for the $lane for Aurora core and Ultrscale GT --
assign gtrefclk0_in[0] = gt0_gtrefclk0_in ;
// DRP interface for GT channel starts
assign gt0_drpdo = drpdo_out[15 : 0];
assign gt0_drprdy = drprdy_out[0];
assign drpaddr_in[9 : 0] = gt0_drpaddr;
assign drpclk_in[0] = gt0_drp_clk_in;
assign drpdi_in[15 : 0] = gt0_drpdi;
assign drpen_in[0] = gt0_drpen ;
assign drpwe_in[0] = gt0_drpwe ;
// DRP interface for GT channel ends
assign txsequence_in[6 : 0] = gt0_txsequence_in;
assign gt0_rxdata_out = gtwiz_userdata_rx_out[63 : 0];
assign gt_rxbufstatus[2 : 0] = rxbufstatus_out[2 : 0];
assign gt0_rxheader_out = rxheader_out[1 : 0];// connect only the 2 bits of this signal (out of 6 bits)
assign loopback_in[2 : 0] = gt_loopback[2 : 0];
assign txpostcursor_in[4 : 0] = gt_txpostcursor[4 : 0];
assign txheader_in[5 : 0] = {4'b0, gt0_txheader_in[1:0]};
assign txdiffctrl_in[4 : 0] = gt_txdiffctrl[4 : 0];
assign gtwiz_userdata_tx_in[63 : 0] = gt0_txdata_in;
assign txprecursor_in[4 : 0] = gt_txprecursor[4 : 0];
assign txprbssel_in[3 : 0] = gt_txprbssel[3 : 0];
assign rxprbssel_in[3 : 0] = gt_rxprbssel[3 : 0];
assign gt_dmonitorout[15 : 0] = dmonitorout_out[15 : 0];
assign gt_txbufstatus[1 : 0] = txbufstatus_out[1 : 0];
assign eyescanreset_in[0] = gt_eyescanreset[0] ;
assign rxpolarity_in[0] = gt_rxpolarity[0] ;
assign eyescantrigger_in[0] = gt_eyescantrigger[0];
assign rxcdrovrden_in[0] = gt0_rxcdrovrden_in ;
assign rxcdrhold_in[0] = gt_rxcdrhold[0] ;
assign gtyrxn_in[0] = gt0_gthrxn_in ;
assign gtyrxp_in[0] = gt0_gthrxp_in ;
assign rxdfelpmreset_in[0] = gt_rxdfelpmreset[0] ;
assign txpolarity_in[0] = gt_txpolarity[0] ;
assign txinhibit_in[0] = gt_txinhibit[0] ;
assign pcsrsvdin_in[15 : 0] = gt_pcsrsvdin[15 : 0];
assign txpmareset_in[0] = gt_txpmareset[0] ;
assign txpcsreset_in[0] = gt_txpcsreset[0] ;
assign rxpcsreset_in[0] = gt_rxpcsreset[0] ;
assign rxbufreset_in[0] = gt_rxbufreset[0] ;
assign rxgearboxslip_in[0] = gt0_rxgearboxslip_in ;
assign rxlpmen_in[0] = gt_rxlpmen[0] ;
assign gtrxreset_in[0] = gt_gtrxreset[0] ;
assign gttxreset_in[0] = gt_gttxreset[0] ;
assign txprbsforceerr_in[0] = gt_txprbsforceerr[0];
assign rxprbscntreset_in[0] = gt_rxprbscntreset[0];
assign gt_eyescandataerror[0] = eyescandataerror_out[0];
assign gt_rxprbserr[0] = rxprbserr_out[0] ;
assign gt0_rxoutclk_out = rxoutclk_out[0] ;
assign gt0_rxdatavalid_out = rxdatavalid_out[0];
assign gt0_rxheadervalid_out = rxheadervalid_out[0] ;
assign gt_rxresetdone[0] = rxresetdone_out[0] ;
assign gt0_gthtxn_out = gtytxn_out[0] ;
assign gt0_gthtxp_out = gtytxp_out[0] ;
assign gt0_txoutclk_out = txoutclk_out[0] ;
assign gt0_txoutclkfabric_out = txoutclkfabric_out[0];
assign gt0_txoutclkpcs_out = txoutclkpcs_out[0] ;
assign gt_rxpmaresetdone[0] = rxpmaresetdone_out[0];
assign gt_txresetdone[0] = txresetdone_out[0] ;
assign rxpmareset_in[0] = gt_rxpmareset[0];
assign rxrate_in[2 : 0] = gt_rxrate[2 : 0];
// clock module output clocks assignment to GT clock input pins
// for Tx path
assign txusrclk2_in[0] = gt0_txusrclk2_in;
assign txusrclk_in[0] = gt0_txusrclk_in;
// for Rx path, this will be connected to GT Rx clock inputs again
assign rxusrclk2_in[0] = gtwiz_userclk_rx_usrclk2_out;
assign rxusrclk_in[0] = gtwiz_userclk_rx_usrclk_out ;
// for Rx path, this will be connected outside of this module in WRAPPER logic
assign gt0_rxusrclk2_out = gtwiz_userclk_rx_usrclk2_out;
assign gt0_rxusrclk_out = gtwiz_userclk_rx_usrclk_out;
//------------------------------------------------------------------------------
// Rx is needed in below conditions
// duplex, Rx only, RX/TX simplex
// Ultrascale GT RX clocking module in outside of the GT
aurora_64b66b_25p4G_ultrascale_rx_userclk
#(
// parameter declaration
.P_CONTENTS (0),
.P_FREQ_RATIO_SOURCE_TO_USRCLK (1),
.P_FREQ_RATIO_USRCLK_TO_USRCLK2 (1)
)
ultrascale_rx_userclk
(
// port declaration
.gtwiz_reset_clk_freerun_in (gtwiz_reset_clk_freerun_in ),
.gtwiz_userclk_rx_srcclk_in (rxoutclk_out[0] ), // input wire
.gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in_r ), // input wire
.gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out ), // output wire
.gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_out), // output wire
.gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_out ) // output reg = 1'b0
);
//------------------------------------------------------------------------------
//--- fabric_pcs_reset reset extension counter based upon the stable clock
//connect output of main clocking module (user clock) here
assign gtwiz_userclk_tx_usrclk2_out = txusrclk2_in[0];
//--- synchronizing to usrclk2
aurora_64b66b_25p4G_rst_sync #
(
.c_mtbf_stages (3)
)u_rst_gtwiz_userclk_tx_active_out
(
.prmry_in (gtwiz_userclk_tx_active_out),
.scndry_aclk (gtwiz_userclk_tx_usrclk2_out),
.scndry_out (gtwiz_userclk_tx_active_out_i)
);
always @(posedge gtwiz_userclk_tx_usrclk2_out)
begin
if (!gtwiz_userclk_tx_active_out_i) // deactive counter when tx_active is not present
fabric_pcs_rst_extend_cntr <= 10'b0;
else if (!fabric_pcs_rst_extend_cntr[9]) // when tx active is asserted, extend with 10 bit counter
fabric_pcs_rst_extend_cntr <= fabric_pcs_rst_extend_cntr + 1'b1;
end
assign fabric_pcs_reset = !fabric_pcs_rst_extend_cntr[9];
//--- fabric_pcs_reset reset extension counter ends
//------------------------------------------------------------------------------
//--- gtwiz_userclk_tx_active_in delay extension counter based upon the stable tx clock
// 8-bit counter
always @(posedge gtwiz_userclk_tx_usrclk2_out)
begin
if (!gtwiz_userclk_tx_active_out_i) // deactive counter when tx_active is not present
usrclk_tx_active_in_extend_cntr <= 8'b0;
else if (fabric_pcs_rst_extend_cntr[9] && // Extended tx active from clock module with 10 bit counter
(!usrclk_tx_active_in_extend_cntr[7]))
usrclk_tx_active_in_extend_cntr <= usrclk_tx_active_in_extend_cntr + 1'b1;
end
assign userclk_tx_active_out = usrclk_tx_active_in_extend_cntr[7];
//--- gtwiz_userclk_tx_active_in reset extension counter ends
//------------------------------------------------------------------------------
//--- gtwiz_userclk_rx_active_in delay extension counter based upon the stable Rx clock
// 8-bit counter
always @(posedge gtwiz_userclk_rx_usrclk2_out)
begin
if (!gtwiz_userclk_rx_active_out) // deactive counter when rx_active is not present
usrclk_rx_active_in_extend_cntr <= 8'b0;
else if (gtwiz_userclk_rx_active_out && // Rx clock module is stable
(!usrclk_rx_active_in_extend_cntr[7]))
usrclk_rx_active_in_extend_cntr <= usrclk_rx_active_in_extend_cntr + 1'b1;
end
assign userclk_rx_active_out = !usrclk_rx_active_in_extend_cntr[7];
//--- gtwiz_userclk_rx_active_in reset extension counter ends
//------------------------------------------------------------------------------
// assginment of delayed counters of Tx and Rx active signals to GT ports
assign gtwiz_userclk_tx_active_in = userclk_tx_active_out;
//--------------------------------------------------------
// driving the gtwiz_userclk_rx_active_in different conditions
// Rx clocking module is included in the design
assign gtwiz_userclk_rx_active_in = usrclk_rx_active_in_extend_cntr[7];
//--------------------------------------------------------
//------------------------------------------------------------------------------
//-- txpmaresetdone logic starts
assign txpmaresetdone_int = txpmaresetdone_out;
assign gtwiz_userclk_tx_reset_in = ~(&txpmaresetdone_int);
assign bufg_gt_clr_out = ~(&txpmaresetdone_int);
//-- txpmaresetdone logic ends
//-- rxpmaresetdone logic starts
assign rxpmaresetdone_int = rxpmaresetdone_out;
assign gtwiz_userclk_rx_reset_in = ~(&rxpmaresetdone_int);
always @(posedge gtwiz_reset_clk_freerun_in)
gtwiz_userclk_rx_reset_in_r <= `DLY gtwiz_userclk_rx_reset_in;
//-- rxpmaresetdone logic ends
//-- GT Reference clock assignment
// decision is made to use qpll0 only - note the 1 at the end of QPLL, so below changes are needed
// to be incorporated
assign qpll0outclk_out = qpll0outclk_out;
assign qpll0outrefclk_out = qpll0outrefclk_out;
// dynamic GT instance call
aurora_64b66b_25p4G_gt aurora_64b66b_25p4G_gt_i
(
.dmonitorout_out(dmonitorout_out),
.drpaddr_in(drpaddr_in),
.drpclk_in(drpclk_in),
.drpdi_in(drpdi_in),
.drpdo_out(drpdo_out),
.drpen_in(drpen_in),
.drprdy_out(drprdy_out),
.drpwe_in(drpwe_in),
.eyescandataerror_out(eyescandataerror_out),
.eyescanreset_in(eyescanreset_in),
.eyescantrigger_in(eyescantrigger_in),
.gtpowergood_out(gtpowergood_out),
.gtrefclk0_in(gtrefclk0_in),
.gtwiz_reset_all_in(gtwiz_reset_all_in),
.gtwiz_reset_clk_freerun_in(gtwiz_reset_clk_freerun_in),
.gtwiz_reset_qpll0lock_in(gtwiz_reset_qpll0lock_in),
.gtwiz_reset_qpll0reset_out(gtwiz_reset_qpll0reset_out),
.gtwiz_reset_rx_cdr_stable_out(gtwiz_reset_rx_cdr_stable_out),
.gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in),
.gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out),
.gtwiz_reset_rx_pll_and_datapath_in(gtwiz_reset_rx_pll_and_datapath_in),
.gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_datapath_in),
.gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out),
.gtwiz_reset_tx_pll_and_datapath_in(gtwiz_reset_tx_pll_and_datapath_in),
.gtwiz_userclk_rx_active_in(gtwiz_userclk_rx_active_in),
.gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in),
.gtwiz_userdata_rx_out(gtwiz_userdata_rx_out),
.gtwiz_userdata_tx_in(gtwiz_userdata_tx_in),
.gtyrxn_in(gtyrxn_in),
.gtyrxp_in(gtyrxp_in),
.gtytxn_out(gtytxn_out),
.gtytxp_out(gtytxp_out),
.loopback_in(loopback_in),
.pcsrsvdin_in(pcsrsvdin_in),
.qpll0clk_in(qpll0clk_in),
.qpll0refclk_in(qpll0refclk_in),
.qpll1clk_in(qpll1clk_in),
.qpll1refclk_in(qpll1refclk_in),
.rxbufreset_in(rxbufreset_in),
.rxbufstatus_out(rxbufstatus_out),
.rxcdrhold_in(rxcdrhold_in),
.rxcdrovrden_in(rxcdrovrden_in),
.rxdatavalid_out(rxdatavalid_out),
.rxdfelpmreset_in(rxdfelpmreset_in),
.rxgearboxslip_in(rxgearboxslip_in),
.rxheader_out(rxheader_out),
.rxheadervalid_out(rxheadervalid_out),
.rxlpmen_in(rxlpmen_in),
.rxoutclk_out(rxoutclk_out),
.rxpcsreset_in(rxpcsreset_in),
.rxpmareset_in(rxpmareset_in),
.rxpmaresetdone_out(rxpmaresetdone_out),
.rxpolarity_in(rxpolarity_in),
.rxprbscntreset_in(rxprbscntreset_in),
.rxprbserr_out(rxprbserr_out),
.rxprbssel_in(rxprbssel_in),
.rxresetdone_out(rxresetdone_out),
.rxstartofseq_out(rxstartofseq_out),
.rxusrclk2_in(rxusrclk2_in),
.rxusrclk_in(rxusrclk_in),
.txbufstatus_out(txbufstatus_out),
.txdiffctrl_in(txdiffctrl_in),
.txheader_in(txheader_in),
.txinhibit_in(txinhibit_in),
.txoutclk_out(txoutclk_out),
.txoutclkfabric_out(txoutclkfabric_out),
.txoutclkpcs_out(txoutclkpcs_out),
.txpcsreset_in(txpcsreset_in),
.txpmareset_in(txpmareset_in),
.txpmaresetdone_out(txpmaresetdone_out),
.txpolarity_in(txpolarity_in),
.txpostcursor_in(txpostcursor_in),
.txprbsforceerr_in(txprbsforceerr_in),
.txprbssel_in(txprbssel_in),
.txprecursor_in(txprecursor_in),
.txresetdone_out(txresetdone_out),
.txsequence_in(txsequence_in),
.txusrclk2_in(txusrclk2_in),
.txusrclk_in(txusrclk_in)
);
endmodule
|
module mojo_top(
// 50MHz clock input
input clk,
// Input from rst button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard leds
output[7:0]led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy, // AVR Rx buffer full
output [23:0] io_led, // LEDs on IO Shield
output [7:0] io_seg, // 7-segment LEDs on IO Shield
output [3:0] io_sel, // Digit select on IO Shield
input [3:0] pb,
input en,
output pm
);
wire rst = ~rst_n; // make rst active high
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
assign led[7:0] = {8{slow_clk}};
reg [25:0] slow_clk_d, slow_clk_q;
reg slow_clk;
always @(slow_clk_q) begin
if (pb[0] && ~(slow_clk_q % 8'hFA)) begin
slow_clk_d = slow_clk_q + 8'hFA;
end else if (pb[1] && ~(slow_clk_q % 11'h4E2)) begin
slow_clk_d = slow_clk_q + 11'h4E2;
end else if (pb[2] && ~(slow_clk_q % 13'h186A)) begin
slow_clk_d = slow_clk_q + 13'h186A;
end else begin
slow_clk_d = slow_clk_q + 1'b1;
end
end
always @(posedge clk, posedge rst) begin
if (rst == 1) begin
slow_clk_q <= 25'b0;
slow_clk <= 1'b0;
end else if (slow_clk_q == 25'h17D7840) begin
slow_clk_q <= 25'b0;
slow_clk <= ~slow_clk;
end else begin
slow_clk_q <= slow_clk_d;
end
end
clock real_deal (
.clk(slow_clk),
.fast_clk(slow_clk_q[16]),
.rst(rst),
.en(~en),
.sec(io_led[7:0]),
.pm(io_led[23:8]),
.io_seg(io_seg),
.io_sel(io_sel)
);
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S4S_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DLYMETAL6S4S_FUNCTIONAL_PP_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__dlymetal6s4s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S4S_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4B_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__NAND4B_BEHAVIORAL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nand4b (
Y ,
A_N,
B ,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, D, C, B, not0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4B_BEHAVIORAL_V |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of rs_fe1_pre_dec
//
// Generated
// by: lutscher
// on: Tue Jun 23 11:51:21 2009
// cmd: /home/lutscher/work/MIX/mix_1.pl rs_test.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author$
// $Id$
// $Date$
// $Log$
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.109 2008/04/01 12:48:34 wig Exp
//
// Generator: mix_1.pl Revision: 1.3 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of rs_fe1_pre_dec
//
// No user `defines in this module
module rs_fe1_pre_dec
//
// Generated Module rs_fe1_pre_dec_i
//
(
input wire [13:0] addr_i,
output wire pre_dec_o,
output wire pre_dec_err_o
);
// Module parameters:
parameter N_DOMAINS = 2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
/* ------------------------------------------------------------
Generator information:
used package Micronas::Reg is version 1.88
this package RegViews.pm is version 1.93
use with RTL libraries (this release or higher):
ip_ocp/0002/ip_ocp_016_21Jan2009
ip_sync/0001/ip_sync_006_23jan2008
------------------------------------------------------------ */
// pre-address decoder (per clock-domain)
reg pre_dec;
reg pre_dec_err;
assign pre_dec_o = pre_dec;
assign pre_dec_err_o = pre_dec_err;
always @(addr_i) begin
pre_dec = 0;
pre_dec_err = 0;
case (addr_i[5:2])
// clock-domain #0 --> clk_a
'h0, 'h8, 'ha: pre_dec = 0;
// clock-domain #1 --> clk_f20
'h1, 'h2, 'h3, 'h4, 'h5, 'h6, 'h7: pre_dec = 1;
default: begin
pre_dec = 0;
pre_dec_err = 1;
end
endcase
end
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of rs_fe1_pre_dec
//
//
//!End of Module/s
// --------------------------------------------------------------
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: ddr2_phy_dqs_iob.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module places the data strobes in the IOBs.
//Reference:
//Revision History:
// Rev 1.1 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08
// Rev 1.2 - Parameter IODELAY_GRP added and constraint IODELAY_GROUP added
// on IODELAY primitives. PK. 11/27/08
// Rev 1.3 - IDDR primitve (u_iddr_dq_ce) is replaced with a negative-edge
// triggered flip-flop. PK. 03/20/09
// Rev 1.4 - To fix CR 540201, S and syn_preserve attributes are added
// for dqs_oe_n_r. PK. 01/08/10
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_phy_dqs_iob #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_36_1 module. Please refer to
// the mig_36_1 module for actual values.
parameter DDR_TYPE = 1,
parameter HIGH_PERFORMANCE_MODE = "TRUE",
parameter IODELAY_GRP = "IODELAY_MIG"
)
(
input clk0,
input clkdiv0,
input rst0,
input dlyinc_dqs,
input dlyce_dqs,
input dlyrst_dqs,
input dlyinc_gate,
input dlyce_gate,
input dlyrst_gate,
input dqs_oe_n,
input dqs_rst_n,
input en_dqs,
inout ddr_dqs,
inout ddr_dqs_n,
output dq_ce,
output delayed_dqs
);
wire clk180;
wire dqs_bufio;
wire dqs_ibuf;
wire dqs_idelay;
wire dqs_oe_n_delay;
(* S = "TRUE" *) wire dqs_oe_n_r /* synthesis syn_preserve = 1*/;
wire dqs_rst_n_delay;
reg dqs_rst_n_r /* synthesis syn_preserve = 1*/;
wire dqs_out;
wire en_dqs_sync /* synthesis syn_keep = 1 */;
// for simulation only. Synthesis should ignore this delay
localparam DQS_NET_DELAY = 0.8;
assign clk180 = ~clk0;
// add delta delay to inputs clocked by clk180 to avoid delta-delay
// simulation issues
assign dqs_rst_n_delay = dqs_rst_n;
assign dqs_oe_n_delay = dqs_oe_n;
//***************************************************************************
// DQS input-side resources:
// - IODELAY (pad -> IDELAY)
// - BUFIO (IDELAY -> BUFIO)
//***************************************************************************
// Route DQS from PAD to IDELAY
(* IODELAY_GROUP = IODELAY_GRP *) IODELAY #
(
.DELAY_SRC("I"),
.IDELAY_TYPE("VARIABLE"),
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE),
.IDELAY_VALUE(0),
.ODELAY_VALUE(0)
)
u_idelay_dqs
(
.DATAOUT (dqs_idelay),
.C (clkdiv0),
.CE (dlyce_dqs),
.DATAIN (),
.IDATAIN (dqs_ibuf),
.INC (dlyinc_dqs),
.ODATAIN (),
.RST (dlyrst_dqs),
.T ()
);
// From IDELAY to BUFIO
BUFIO u_bufio_dqs
(
.I (dqs_idelay),
.O (dqs_bufio)
);
// To model additional delay of DQS BUFIO + gating network
// for behavioral simulation. Make sure to select a delay number smaller
// than half clock cycle (otherwise output will not track input changes
// because of inertial delay). Duplicate to avoid delta delay issues.
assign #(DQS_NET_DELAY) i_delayed_dqs = dqs_bufio;
assign #(DQS_NET_DELAY) delayed_dqs = dqs_bufio;
//***************************************************************************
// DQS gate circuit (not supported for all controllers)
//***************************************************************************
// Gate routing:
// en_dqs -> IDELAY -> en_dqs_sync -> IDDR.S -> dq_ce ->
// capture IDDR.CE
// Delay CE control so that it's in phase with delayed DQS
(* IODELAY_GROUP = IODELAY_GRP *) IODELAY #
(
.DELAY_SRC ("DATAIN"),
.IDELAY_TYPE ("VARIABLE"),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.IDELAY_VALUE (0),
.ODELAY_VALUE (0)
)
u_iodelay_dq_ce
(
.DATAOUT (en_dqs_sync),
.C (clkdiv0),
.CE (dlyce_gate),
.DATAIN (en_dqs),
.IDATAIN (),
.INC (dlyinc_gate),
.ODATAIN (),
.RST (dlyrst_gate),
.T ()
);
// Generate sync'ed CE to DQ IDDR's using a negative-edge triggered flip-flop
// clocked by DQS. This flop should be locked to the IOB flip-flop at the same
// site as IODELAY u_idelay_dqs in order to use the dedicated route from
// the IODELAY to flip-flop (to keep this route as short as possible)
(* IOB = "FORCE" *) FDCPE_1 #
(
.INIT(1'b0)
)
u_iddr_dq_ce
(
.Q (dq_ce),
.C (i_delayed_dqs),
.CE (1'b1),
.CLR (1'b0),
.D (en_dqs_sync),
.PRE (en_dqs_sync)
) /* synthesis syn_useioff = 1 */
/* synthesis syn_replicate = 0 */;
//***************************************************************************
// DQS output-side resources
//***************************************************************************
// synthesis attribute keep of dqs_rst_n_r is "true"
always @(posedge clk180)
dqs_rst_n_r <= dqs_rst_n_delay;
ODDR #
(
.SRTYPE("SYNC"),
.DDR_CLK_EDGE("OPPOSITE_EDGE")
)
u_oddr_dqs
(
.Q (dqs_out),
.C (clk180),
.CE (1'b1),
.D1 (dqs_rst_n_r), // keep output deasserted for write preamble
.D2 (1'b0),
.R (1'b0),
.S (1'b0)
);
(* IOB = "FORCE" *) FDP u_tri_state_dqs
(
.D (dqs_oe_n_delay),
.Q (dqs_oe_n_r),
.C (clk180),
.PRE (rst0)
) /* synthesis syn_useioff = 1 */;
//***************************************************************************
// use either single-ended (for DDR1) or differential (for DDR2) DQS input
generate
if (DDR_TYPE > 0) begin: gen_dqs_iob_ddr2
IOBUFDS u_iobuf_dqs
(
.O (dqs_ibuf),
.IO (ddr_dqs),
.IOB (ddr_dqs_n),
.I (dqs_out),
.T (dqs_oe_n_r)
);
end else begin: gen_dqs_iob_ddr1
IOBUF u_iobuf_dqs
(
.O (dqs_ibuf),
.IO (ddr_dqs),
.I (dqs_out),
.T (dqs_oe_n_r)
);
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXBN_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DLXBN_FUNCTIONAL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_ms__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_ms__dlxbn (
Q ,
Q_N ,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Local signals
wire GATE ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (GATE , GATE_N );
sky130_fd_sc_ms__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXBN_FUNCTIONAL_V |
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 4
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_top,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "design_1_auto_us_0,axi_dwidth_converter_v2_1_top,{}" *)
(* CORE_GENERATION_INFO = "design_1_auto_us_0,axi_dwidth_converter_v2_1_top,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=1,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=0,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=16,C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_us_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [3 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
axi_dwidth_converter_v2_1_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(1),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(0),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(32'H00000000),
.s_axi_arlen(4'H0),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(2'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(3'H0),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_arvalid(1'H0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'H0),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_arvalid(),
.m_axi_arready(1'H0),
.m_axi_rdata(64'H0000000000000000),
.m_axi_rresp(2'H0),
.m_axi_rlast(1'H1),
.m_axi_rvalid(1'H0),
.m_axi_rready()
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/12/2016 06:18:20 PM
// Design Name:
// Module Name: Mux_Array
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mux_Array
#(parameter SWR=26, parameter EWR=5)
(
input wire clk,
input wire rst,
input wire load_i,
input wire [EWR-1:0] Shift_Value_i,
input wire [SWR-1:0] Data_i,
input wire FSM_left_right_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
////
wire [SWR-1:0] Data_array[EWR+1:0];
//////////////////7
genvar k;//Level
///////////////////77777
Rotate_Mux_Array #(.SWR(SWR)) first_rotate(
.Data_i(Data_i),
.select_i(FSM_left_right_i),
.Data_o(Data_array [0][SWR-1:0])
);
generate for (k=0; k < 3; k=k+1) begin
shift_mux_array #(.SWR(SWR), .LEVEL(k)) shift_mux_array(
.Data_i(Data_array[k]),
.select_i(Shift_Value_i[k]),
.bit_shift_i(bit_shift_i),
.Data_o(Data_array[k+1])
);
end
endgenerate
RegisterAdd #(.W(SWR)) Mid_Reg(
.clk(clk),
.rst(rst),
.load(1'b1),
.D(Data_array[3]),
.Q(Data_array[4])
);
generate for (k=3; k < EWR; k=k+1) begin
shift_mux_array #(.SWR(SWR), .LEVEL(k)) shift_mux_array(
.Data_i(Data_array[k+1]),
.select_i(Shift_Value_i[k]),
.bit_shift_i(bit_shift_i),
.Data_o(Data_array[k+2])
);
end
endgenerate
Rotate_Mux_Array #(.SWR(SWR)) last_rotate(
.Data_i(Data_array[EWR+1]),
.select_i(FSM_left_right_i),
.Data_o(Data_o)
);
endmodule
|
// bsg_hash_bank
//
// This module takes a binary address, and a constant number of banks, and then hashes the
// address across the banks efficiently; outputing the bank #, and the index at that bank.
// This is useful for banking memories; or spreading cache coherence directory information
// across multiple directories.
//
// Since we support non-power of two banks, some banks will be larger than others.
// The hash function guarantees that the difference in size of the banks is no greater than 1.
//
// Here is what is supported:
//
// Bank counts of 2^n * (2^m-1), where n=0,1,2... and m = 1,2,3,4,5...
//
// i.e., 2,3,4,6=2*3,7,8,12=3*4,14=7*2,15,16,24=3*8,28=4*7,30=15*2,32
// 1 3 7 15 31 63 127
// ------------------------
// 1| 1 3 7 15 31 63 127
// 2| 2 6 14 30 62 126 254 --> Bank counts of 1,2,3,4,6,7,8,12,14,15,16,24,28,30,31,32
// 4| 4 12 28 60 124 252 508
// 8| 8 24 56 120 248 504 ....
// 16|16 48 112 240 496
// 32|32 96 224
// 64|64 192
//
// The function uses the higher-order bits to select the bank number
// to use lower-order bits, you can reverse the bit sequence on input to the module
// using the {<< {i}} operator.
//
// see also the module bsg_hash_bank_reverse, which takes a bank and index
// and produces the original address
//
// TODO: it may make sense to add support for other #'s of banks via
// the Verilog modulo operator; it may be sufficiently efficient for small binary addresses
//
// TODO: evaluate PPA versus yosys and DC modulo operator
//
// TODO: a pathway to support hash functions that are a factor of 2^n+1 seems possible but is only onlined in this code
// see comments for how the math would work. This would support banking of 5,9 and maybe higher.
//
//
`include "bsg_defines.v"
module bsg_hash_bank #(parameter `BSG_INV_PARAM(banks_p)
,parameter `BSG_INV_PARAM(width_p),
index_width_lp=$clog2((2**width_p+banks_p-1)/banks_p),
lg_banks_lp=`BSG_SAFE_CLOG2(banks_p), debug_lp=0)
(/* input clk,*/
input [width_p-1:0] i
,output [lg_banks_lp-1:0] bank_o
,output [index_width_lp-1:0] index_o
);
genvar j;
if (banks_p == 1)
begin: hash1
assign index_o = i;
assign bank_o = 1'b0;
end
else
if (banks_p == 2)
begin: hash2
assign bank_o = i[width_p-1];
assign index_o = i[width_p-2:0];
end
else
if (~banks_p[0])
begin: hashpow2
assign bank_o [0] = i[width_p-1];
bsg_hash_bank #(.banks_p(banks_p >> 1),.width_p(width_p-1)) bhb (/* .clk(clk), */.i(i[width_p-2:0]),.bank_o(bank_o[lg_banks_lp-1:1]),.index_o(index_o));
end
else
if ((banks_p & (banks_p+1))==0) // test for (2^N)-1
begin : hash3
if ((width_p % lg_banks_lp)!=0)
begin : odd
wire _unused;
bsg_hash_bank #(.banks_p(banks_p),.width_p(width_p+1))
hf (/* .clk,*/ .i({i,1'b0}),.bank_o(bank_o),.index_o({index_o,_unused}));
end
else
begin : even
localparam frac_width_lp = width_p/lg_banks_lp;
wire [lg_banks_lp-1:0][frac_width_lp-1:0] unzippered;
// This is the hash function we implement.
// banks=3
// 00 XX XX -> Bank 0, 00 XX XX
// 01 XX XX -> Bank 1, 00 XX XX
// 10 XX XX -> Bank 2, 00 XX XX
// 11 00 XX -> Bank 0, 01 00 XX
// 11 01 XX -> Bank 1, 01 00 XX
// 11 10 XX -> Bank 2, 01 00 XX
// 11 11 00 -> Bank 0, 01 01 00
// 11 11 01 -> Bank 1, 01 01 00
// 11 11 10 -> Bank 2, 01 01 00
// 11 11 11 -> Bank 3, 01 01 01
// banks=5 --> partially reuse 2^N-1 = 15 trick
// banks=9 --> partially reuse 2^N-1 = 63 trick
// banks=21 --> partially reuse 2^N-1 = 63 trick
// banks=15 --> partially reuse 2^N-1 = 255 trick
// banks=17 --> partially reuse 2^N-1 = 255 trick
// banks=51 --> "
// banks=85 -->
// banks=73 --> 2^N-1=511
// banks=11,31,33,93,341 --> 2^N-1=1023
// banks=23,89->2047
// H
// Bank Index
//
// 0000 XXXX XXXX 0 00 XXXX XXXX
// 0001 XXXX XXXX 1 00 XXXX XXXX
// 0010 XXXX XXXX 2 00 XXXX XXXX
// 0011 XXXX XXXX 3 00 XXXX XXXX
// 0100 XXXX XXXX 4 00 XXXX XXXX
// 0101 XXXX XXXX 0 01 XXXX XXXX
// 0101 XXXX XXXX 0 01 XXXX XXXX
// 0101 XXXX XXXX 0 01 XXXX XXXX
// 0110 XXXX XXXX 1 01 XXXX XXXX
// 0111 XXXX XXXX 2 01 XXXX XXXX
// 1000 XXXX XXXX 3 01 XXXX XXXX
// 1001 XXXX XXXX 4 01 XXXX XXXX
// 1010 XXXX XXXX 0 10 XXXX XXXX
// 1011 XXXX XXXX 1 10 XXXX XXXX
// 1100 XXXX XXXX 2 10 XXXX XXXX
// 1101 XXXX XXXX 3 10 XXXX XXXX
// 1110 XXXX XXXX 4 10 XXXX XXXX
// 1111 0000 XXXX 0 11 0000 XXXX
// 1111 0001 XXXX 1 11 0000 XXXX
// 1111 0010 XXXX 2 11 0000 XXXX
// 1111 0011 XXXX 3 11 0000 XXXX
// 1111 0100 XXXX 4 11 0000 XXXX
// 1111 0101 XXXX 0 11 0001 XXXX
// 1111 0110 XXXX 1 11 0001 XXXX
// 1111 0111 XXXX 2 11 0001 XXXX
// 1111 1000 XXXX 3 11 0001 XXXX
// 1111 1001 XXXX 4 11 0001 XXXX
// 1111 1010 XXXX 0 11 0010 XXXX
// 1111 1011 XXXX 1 11 0010 XXXX
// 1111 1100 XXXX 2 11 0010 XXXX
// 1111 1101 XXXX 3 11 0010 XXXX
// 1111 1110 XXXX 4 11 0010 XXXX
// 1111 1111 XXXX 0 11 0011 XXXX
// 1111 1111 0000 0 11 0011 0000
// 1111 1111 0001 1 11 0011 0000
// 1111 1111 0010 2 11 0011 0000
// 1111 1111 0011 3 11 0011 0000
// 1111 1111 0100 4 11 0011 0000
// 1111 1111 0101 0 11 0011 0001
// 1111 1111 0110 1 11 0011 0001
// 1111 1111 0111 2 11 0011 0001
// 1111 1111 1000 3 11 0011 0001
// 1111 1111 1001 4 11 0011 0001
// 1111 1111 1010 0 11 0011 0010
// 1111 1111 1011 1 11 0011 0010
// 1111 1111 1100 2 11 0011 0010
// 1111 1111 1101 3 11 0011 0010
// 1111 1111 1110 4 11 0011 0010
// 1111 1111 1111 0 11 0011 0011
//
// So basically, for conversion:
// 1) replace 1111 with 0011 (base/5).
// 2) for first non-1111 value Y replace with Y/5
// (this generalizes for normal case of 15 banks --> 15/15 -> 1.
//
// banks=7
// bank index
// 000 XXX XXX --> 0 0 XXX XXX
// 001 XXX XXX --> 1 0 XXX XXX
// 010 XXX XXX --> 2 0 XXX XXX
// 011 XXX XXX --> 3 0 XXX XXX
// 100 XXX XXX --> 4 0 XXX XXX
// 101 XXX XXX --> 5 0 XXX XXX
// 110 XXX XXX --> 6 0 XXX XXX
// 111 000 XXX --> 0 1 000 XXX
// 111 001 XXX --> 1 1 000 XXX
// ...
// 111 110 XXX --> 6 1 000 XXX
// 111 111 000 --> 0 1 001 000
// 111 111 001 --> 1 1 001 000
// ..
// 111 111 110 --> 6 1 001 000
// 111 111 111 --> 0 1 001 001
// Notice the pattern -- if there is a 11 or 111, we skip to the next pair of bits
// to find the bank index.
// To compute the index, we use a 01 if it is a 11, a 00 if it the pair of
// bits after the last 11, othwerise we use the same bits as the input.
// for odd numbers of bits; add a zero to the end, invoke even routine, and then drop low bit of the index at the end.
//
// A D (a = add, d=drop)
// 00 XX X 0 -> Bank 0, 00 XX X0
// 01 XX X 0 -> Bank 1, 00 XX X0
// 10 XX X 0 -> Bank 2, 00 XX X0
// 11 00 X 0 -> Bank 0, 01 00 X0
// 11 01 X 0 -> Bank 1, 01 00 X0
// 11 10 X 0 -> Bank 2, 01 00 X0
// 11 11 0 0 -> Bank 0, 01 01 00
// 11 11 1 0 -> Bank 2, 01 01 00
// and tuplets of bank_p-1 consecutive bits
wire [frac_width_lp-1:0] one_one;
bsg_reduce_segmented #(.segments_p(frac_width_lp),.segment_width_p(lg_banks_lp),.and_p(1'b1)) brs
(.i(i),.o(one_one));
bsg_transpose #(.width_p(lg_banks_lp), .els_p(frac_width_lp)) unzip (.i(i),.o(unzippered));
wire [frac_width_lp-1:0] one_one_and_scan;
// and bits from top to bottom, zeroing everything out after first
// zero; this is the mask the determines when 11's end.
bsg_scan #(.width_p(frac_width_lp),.and_p(1)) scan(.i(one_one),.o(one_one_and_scan));
// 111000
// 111100
// ------
// 000100
wire [frac_width_lp-1:0] not_one_one_and_scan = ~one_one_and_scan;
wire [frac_width_lp-1:0] shifty;
if (frac_width_lp > 1)
assign shifty = { 1'b1, one_one_and_scan[frac_width_lp-1:1] };
else
assign shifty = { 1'b1 };
// wire [even_width_lp/2-1:0] border
// = (~one_one_and_scan) & {1'b1, one_one_and_scan >> 1};
wire [frac_width_lp-1:0] border = not_one_one_and_scan & shifty;
// for the top bit of each pair, it should be 0 if it
// is border or one_one_and_scan; otherwise it should be the top bit
// from the original sequence.
// for the bottom bit of each pair, it should be a 0 if border
// a one if one_one_and_scan, otherwise it should be the bit from the original
// sequence.
wire [lg_banks_lp-1:0][frac_width_lp-1:0] bits;
for (j = 1; j < lg_banks_lp; j = j + 1)
begin: rof2
assign bits[j] = unzippered[j] & ~(border | one_one_and_scan);
end
assign bits[0] = (one_one_and_scan) | (unzippered[0] & ~one_one_and_scan & ~border);
wire [width_p-1:0] transpose_lo;
bsg_transpose #(.els_p(lg_banks_lp), .width_p(frac_width_lp)) zip (.i({bits}),.o(transpose_lo));
assign index_o = transpose_lo[index_width_lp-1:0];
for (j = 0; j < lg_banks_lp; j = j + 1)
begin: rof1
// mask out all but border bits and use as the hash index bit
assign bank_o[j] = | (border & unzippered[j]);
end
/* if (debug_lp)
always @(negedge clk)
begin
$display ("%b -> %b %b %b %b %b %b %b %b %b %b",
i, one_one, one_one_and_scan, not_one_one_and_scan, shifty, border, unzippered[1],
unzippered[0], bits[1], bits[0], index_o);
end
*/
end
end
else
initial
begin
assert(0) else $error("unhandled case, banks_p = ", banks_p);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_hash_bank)
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / VCU
// /___/ /\ Filename : VCU.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module VCU #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer CORECLKREQ = 667,
parameter integer DECHORRESOLUTION = 3840,
parameter DECODERCHROMAFORMAT = "4_2_2",
parameter DECODERCODING = "H.265",
parameter integer DECODERCOLORDEPTH = 10,
parameter integer DECODERNUMCORES = 2,
parameter integer DECVERTRESOLUTION = 2160,
parameter ENABLEDECODER = "TRUE",
parameter ENABLEENCODER = "TRUE",
parameter integer ENCHORRESOLUTION = 3840,
parameter ENCODERCHROMAFORMAT = "4_2_2",
parameter ENCODERCODING = "H.265",
parameter integer ENCODERCOLORDEPTH = 10,
parameter integer ENCODERNUMCORES = 4,
parameter integer ENCVERTRESOLUTION = 2160
)(
output VCUPLARREADYAXILITEAPB,
output VCUPLAWREADYAXILITEAPB,
output [1:0] VCUPLBRESPAXILITEAPB,
output VCUPLBVALIDAXILITEAPB,
output VCUPLCORESTATUSCLKPLL,
output [43:0] VCUPLDECARADDR0,
output [43:0] VCUPLDECARADDR1,
output [1:0] VCUPLDECARBURST0,
output [1:0] VCUPLDECARBURST1,
output [3:0] VCUPLDECARCACHE0,
output [3:0] VCUPLDECARCACHE1,
output [3:0] VCUPLDECARID0,
output [3:0] VCUPLDECARID1,
output [7:0] VCUPLDECARLEN0,
output [7:0] VCUPLDECARLEN1,
output VCUPLDECARPROT0,
output VCUPLDECARPROT1,
output [3:0] VCUPLDECARQOS0,
output [3:0] VCUPLDECARQOS1,
output [2:0] VCUPLDECARSIZE0,
output [2:0] VCUPLDECARSIZE1,
output VCUPLDECARVALID0,
output VCUPLDECARVALID1,
output [43:0] VCUPLDECAWADDR0,
output [43:0] VCUPLDECAWADDR1,
output [1:0] VCUPLDECAWBURST0,
output [1:0] VCUPLDECAWBURST1,
output [3:0] VCUPLDECAWCACHE0,
output [3:0] VCUPLDECAWCACHE1,
output [3:0] VCUPLDECAWID0,
output [3:0] VCUPLDECAWID1,
output [7:0] VCUPLDECAWLEN0,
output [7:0] VCUPLDECAWLEN1,
output VCUPLDECAWPROT0,
output VCUPLDECAWPROT1,
output [3:0] VCUPLDECAWQOS0,
output [3:0] VCUPLDECAWQOS1,
output [2:0] VCUPLDECAWSIZE0,
output [2:0] VCUPLDECAWSIZE1,
output VCUPLDECAWVALID0,
output VCUPLDECAWVALID1,
output VCUPLDECBREADY0,
output VCUPLDECBREADY1,
output VCUPLDECRREADY0,
output VCUPLDECRREADY1,
output [127:0] VCUPLDECWDATA0,
output [127:0] VCUPLDECWDATA1,
output VCUPLDECWLAST0,
output VCUPLDECWLAST1,
output VCUPLDECWVALID0,
output VCUPLDECWVALID1,
output [16:0] VCUPLENCALL2CADDR,
output VCUPLENCALL2CRVALID,
output [319:0] VCUPLENCALL2CWDATA,
output VCUPLENCALL2CWVALID,
output [43:0] VCUPLENCARADDR0,
output [43:0] VCUPLENCARADDR1,
output [1:0] VCUPLENCARBURST0,
output [1:0] VCUPLENCARBURST1,
output [3:0] VCUPLENCARCACHE0,
output [3:0] VCUPLENCARCACHE1,
output [3:0] VCUPLENCARID0,
output [3:0] VCUPLENCARID1,
output [7:0] VCUPLENCARLEN0,
output [7:0] VCUPLENCARLEN1,
output VCUPLENCARPROT0,
output VCUPLENCARPROT1,
output [3:0] VCUPLENCARQOS0,
output [3:0] VCUPLENCARQOS1,
output [2:0] VCUPLENCARSIZE0,
output [2:0] VCUPLENCARSIZE1,
output VCUPLENCARVALID0,
output VCUPLENCARVALID1,
output [43:0] VCUPLENCAWADDR0,
output [43:0] VCUPLENCAWADDR1,
output [1:0] VCUPLENCAWBURST0,
output [1:0] VCUPLENCAWBURST1,
output [3:0] VCUPLENCAWCACHE0,
output [3:0] VCUPLENCAWCACHE1,
output [3:0] VCUPLENCAWID0,
output [3:0] VCUPLENCAWID1,
output [7:0] VCUPLENCAWLEN0,
output [7:0] VCUPLENCAWLEN1,
output VCUPLENCAWPROT0,
output VCUPLENCAWPROT1,
output [3:0] VCUPLENCAWQOS0,
output [3:0] VCUPLENCAWQOS1,
output [2:0] VCUPLENCAWSIZE0,
output [2:0] VCUPLENCAWSIZE1,
output VCUPLENCAWVALID0,
output VCUPLENCAWVALID1,
output VCUPLENCBREADY0,
output VCUPLENCBREADY1,
output VCUPLENCRREADY0,
output VCUPLENCRREADY1,
output [127:0] VCUPLENCWDATA0,
output [127:0] VCUPLENCWDATA1,
output VCUPLENCWLAST0,
output VCUPLENCWLAST1,
output VCUPLENCWVALID0,
output VCUPLENCWVALID1,
output [43:0] VCUPLMCUMAXIICDCARADDR,
output [1:0] VCUPLMCUMAXIICDCARBURST,
output [3:0] VCUPLMCUMAXIICDCARCACHE,
output [2:0] VCUPLMCUMAXIICDCARID,
output [7:0] VCUPLMCUMAXIICDCARLEN,
output VCUPLMCUMAXIICDCARLOCK,
output [2:0] VCUPLMCUMAXIICDCARPROT,
output [3:0] VCUPLMCUMAXIICDCARQOS,
output [2:0] VCUPLMCUMAXIICDCARSIZE,
output VCUPLMCUMAXIICDCARVALID,
output [43:0] VCUPLMCUMAXIICDCAWADDR,
output [1:0] VCUPLMCUMAXIICDCAWBURST,
output [3:0] VCUPLMCUMAXIICDCAWCACHE,
output [2:0] VCUPLMCUMAXIICDCAWID,
output [7:0] VCUPLMCUMAXIICDCAWLEN,
output VCUPLMCUMAXIICDCAWLOCK,
output [2:0] VCUPLMCUMAXIICDCAWPROT,
output [3:0] VCUPLMCUMAXIICDCAWQOS,
output [2:0] VCUPLMCUMAXIICDCAWSIZE,
output VCUPLMCUMAXIICDCAWVALID,
output VCUPLMCUMAXIICDCBREADY,
output VCUPLMCUMAXIICDCRREADY,
output [31:0] VCUPLMCUMAXIICDCWDATA,
output VCUPLMCUMAXIICDCWLAST,
output [3:0] VCUPLMCUMAXIICDCWSTRB,
output VCUPLMCUMAXIICDCWVALID,
output VCUPLMCUSTATUSCLKPLL,
output VCUPLPINTREQ,
output VCUPLPLLSTATUSPLLLOCK,
output VCUPLPWRSUPPLYSTATUSVCCAUX,
output VCUPLPWRSUPPLYSTATUSVCUINT,
output [31:0] VCUPLRDATAAXILITEAPB,
output [1:0] VCUPLRRESPAXILITEAPB,
output VCUPLRVALIDAXILITEAPB,
output VCUPLWREADYAXILITEAPB,
input INITPLVCUGASKETCLAMPCONTROLLVLSHVCCINTD,
input [19:0] PLVCUARADDRAXILITEAPB,
input [2:0] PLVCUARPROTAXILITEAPB,
input PLVCUARVALIDAXILITEAPB,
input [19:0] PLVCUAWADDRAXILITEAPB,
input [2:0] PLVCUAWPROTAXILITEAPB,
input PLVCUAWVALIDAXILITEAPB,
input PLVCUAXIDECCLK,
input PLVCUAXIENCCLK,
input PLVCUAXILITECLK,
input PLVCUAXIMCUCLK,
input PLVCUBREADYAXILITEAPB,
input PLVCUCORECLK,
input PLVCUDECARREADY0,
input PLVCUDECARREADY1,
input PLVCUDECAWREADY0,
input PLVCUDECAWREADY1,
input [3:0] PLVCUDECBID0,
input [3:0] PLVCUDECBID1,
input [1:0] PLVCUDECBRESP0,
input [1:0] PLVCUDECBRESP1,
input PLVCUDECBVALID0,
input PLVCUDECBVALID1,
input [127:0] PLVCUDECRDATA0,
input [127:0] PLVCUDECRDATA1,
input [3:0] PLVCUDECRID0,
input [3:0] PLVCUDECRID1,
input PLVCUDECRLAST0,
input PLVCUDECRLAST1,
input [1:0] PLVCUDECRRESP0,
input [1:0] PLVCUDECRRESP1,
input PLVCUDECRVALID0,
input PLVCUDECRVALID1,
input PLVCUDECWREADY0,
input PLVCUDECWREADY1,
input [319:0] PLVCUENCALL2CRDATA,
input PLVCUENCALL2CRREADY,
input PLVCUENCARREADY0,
input PLVCUENCARREADY1,
input PLVCUENCAWREADY0,
input PLVCUENCAWREADY1,
input [3:0] PLVCUENCBID0,
input [3:0] PLVCUENCBID1,
input [1:0] PLVCUENCBRESP0,
input [1:0] PLVCUENCBRESP1,
input PLVCUENCBVALID0,
input PLVCUENCBVALID1,
input PLVCUENCL2CCLK,
input [127:0] PLVCUENCRDATA0,
input [127:0] PLVCUENCRDATA1,
input [3:0] PLVCUENCRID0,
input [3:0] PLVCUENCRID1,
input PLVCUENCRLAST0,
input PLVCUENCRLAST1,
input [1:0] PLVCUENCRRESP0,
input [1:0] PLVCUENCRRESP1,
input PLVCUENCRVALID0,
input PLVCUENCRVALID1,
input PLVCUENCWREADY0,
input PLVCUENCWREADY1,
input PLVCUMCUCLK,
input PLVCUMCUMAXIICDCARREADY,
input PLVCUMCUMAXIICDCAWREADY,
input [2:0] PLVCUMCUMAXIICDCBID,
input [1:0] PLVCUMCUMAXIICDCBRESP,
input PLVCUMCUMAXIICDCBVALID,
input [31:0] PLVCUMCUMAXIICDCRDATA,
input [2:0] PLVCUMCUMAXIICDCRID,
input PLVCUMCUMAXIICDCRLAST,
input [1:0] PLVCUMCUMAXIICDCRRESP,
input PLVCUMCUMAXIICDCRVALID,
input PLVCUMCUMAXIICDCWREADY,
input PLVCUPLLREFCLKPL,
input PLVCURAWRSTN,
input PLVCURREADYAXILITEAPB,
input [31:0] PLVCUWDATAAXILITEAPB,
input [3:0] PLVCUWSTRBAXILITEAPB,
input PLVCUWVALIDAXILITEAPB
);
// define constants
localparam MODULE_NAME = "VCU";
// Parameter encodings and registers
localparam DECODERCHROMAFORMAT_4_2_0 = 1;
localparam DECODERCHROMAFORMAT_4_2_2 = 0;
localparam DECODERCODING_H_264 = 1;
localparam DECODERCODING_H_265 = 0;
localparam ENABLEDECODER_FALSE = 1;
localparam ENABLEDECODER_TRUE = 0;
localparam ENABLEENCODER_FALSE = 1;
localparam ENABLEENCODER_TRUE = 0;
localparam ENCODERCHROMAFORMAT_4_2_0 = 1;
localparam ENCODERCHROMAFORMAT_4_2_2 = 0;
localparam ENCODERCODING_H_264 = 1;
localparam ENCODERCODING_H_265 = 0;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "VCU_dr.v"
`else
reg [31:0] CORECLKREQ_REG = CORECLKREQ;
reg [31:0] DECHORRESOLUTION_REG = DECHORRESOLUTION;
reg [40:1] DECODERCHROMAFORMAT_REG = DECODERCHROMAFORMAT;
reg [40:1] DECODERCODING_REG = DECODERCODING;
reg [31:0] DECODERCOLORDEPTH_REG = DECODERCOLORDEPTH;
reg [31:0] DECODERNUMCORES_REG = DECODERNUMCORES;
reg [31:0] DECVERTRESOLUTION_REG = DECVERTRESOLUTION;
reg [40:1] ENABLEDECODER_REG = ENABLEDECODER;
reg [40:1] ENABLEENCODER_REG = ENABLEENCODER;
reg [31:0] ENCHORRESOLUTION_REG = ENCHORRESOLUTION;
reg [40:1] ENCODERCHROMAFORMAT_REG = ENCODERCHROMAFORMAT;
reg [40:1] ENCODERCODING_REG = ENCODERCODING;
reg [31:0] ENCODERCOLORDEPTH_REG = ENCODERCOLORDEPTH;
reg [31:0] ENCODERNUMCORES_REG = ENCODERNUMCORES;
reg [31:0] ENCVERTRESOLUTION_REG = ENCVERTRESOLUTION;
`endif
`ifdef XIL_XECLIB
wire [9:0] CORECLKREQ_BIN;
wire [13:0] DECHORRESOLUTION_BIN;
wire DECODERCHROMAFORMAT_BIN;
wire DECODERCODING_BIN;
wire [3:0] DECODERCOLORDEPTH_BIN;
wire [1:0] DECODERNUMCORES_BIN;
wire [12:0] DECVERTRESOLUTION_BIN;
wire ENABLEDECODER_BIN;
wire ENABLEENCODER_BIN;
wire [13:0] ENCHORRESOLUTION_BIN;
wire ENCODERCHROMAFORMAT_BIN;
wire ENCODERCODING_BIN;
wire [3:0] ENCODERCOLORDEPTH_BIN;
wire [2:0] ENCODERNUMCORES_BIN;
wire [12:0] ENCVERTRESOLUTION_BIN;
`else
reg [9:0] CORECLKREQ_BIN;
reg [13:0] DECHORRESOLUTION_BIN;
reg DECODERCHROMAFORMAT_BIN;
reg DECODERCODING_BIN;
reg [3:0] DECODERCOLORDEPTH_BIN;
reg [1:0] DECODERNUMCORES_BIN;
reg [12:0] DECVERTRESOLUTION_BIN;
reg ENABLEDECODER_BIN;
reg ENABLEENCODER_BIN;
reg [13:0] ENCHORRESOLUTION_BIN;
reg ENCODERCHROMAFORMAT_BIN;
reg ENCODERCODING_BIN;
reg [3:0] ENCODERCOLORDEPTH_BIN;
reg [2:0] ENCODERNUMCORES_BIN;
reg [12:0] ENCVERTRESOLUTION_BIN;
`endif
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
// reg VCUPLCORESTATUSCLKPLL_out;
// reg VCUPLMCUSTATUSCLKPLL_out;
reg VCUPLARREADYAXILITEAPB_out;
reg VCUPLAWREADYAXILITEAPB_out;
reg [1:0] VCUPLBRESPAXILITEAPB_out;
reg VCUPLBVALIDAXILITEAPB_out;
reg VCUPLCORESTATUSCLKPLL_out;
reg [43:0] VCUPLDECARADDR0_out;
reg [43:0] VCUPLDECARADDR1_out;
reg [1:0] VCUPLDECARBURST0_out;
reg [1:0] VCUPLDECARBURST1_out;
reg [3:0] VCUPLDECARCACHE0_out;
reg [3:0] VCUPLDECARCACHE1_out;
reg [3:0] VCUPLDECARID0_out;
reg [3:0] VCUPLDECARID1_out;
reg [7:0] VCUPLDECARLEN0_out;
reg [7:0] VCUPLDECARLEN1_out;
reg VCUPLDECARPROT0_out;
reg VCUPLDECARPROT1_out;
reg [3:0] VCUPLDECARQOS0_out;
reg [3:0] VCUPLDECARQOS1_out;
reg [2:0] VCUPLDECARSIZE0_out;
reg [2:0] VCUPLDECARSIZE1_out;
reg VCUPLDECARVALID0_out;
reg VCUPLDECARVALID1_out;
reg [43:0] VCUPLDECAWADDR0_out;
reg [43:0] VCUPLDECAWADDR1_out;
reg [1:0] VCUPLDECAWBURST0_out;
reg [1:0] VCUPLDECAWBURST1_out;
reg [3:0] VCUPLDECAWCACHE0_out;
reg [3:0] VCUPLDECAWCACHE1_out;
reg [3:0] VCUPLDECAWID0_out;
reg [3:0] VCUPLDECAWID1_out;
reg [7:0] VCUPLDECAWLEN0_out;
reg [7:0] VCUPLDECAWLEN1_out;
reg VCUPLDECAWPROT0_out;
reg VCUPLDECAWPROT1_out;
reg [3:0] VCUPLDECAWQOS0_out;
reg [3:0] VCUPLDECAWQOS1_out;
reg [2:0] VCUPLDECAWSIZE0_out;
reg [2:0] VCUPLDECAWSIZE1_out;
reg VCUPLDECAWVALID0_out;
reg VCUPLDECAWVALID1_out;
reg VCUPLDECBREADY0_out;
reg VCUPLDECBREADY1_out;
reg VCUPLDECRREADY0_out;
reg VCUPLDECRREADY1_out;
reg [127:0] VCUPLDECWDATA0_out;
reg [127:0] VCUPLDECWDATA1_out;
reg VCUPLDECWLAST0_out;
reg VCUPLDECWLAST1_out;
reg VCUPLDECWVALID0_out;
reg VCUPLDECWVALID1_out;
reg [16:0] VCUPLENCALL2CADDR_out;
reg VCUPLENCALL2CRVALID_out;
reg [319:0] VCUPLENCALL2CWDATA_out;
reg VCUPLENCALL2CWVALID_out;
reg [43:0] VCUPLENCARADDR0_out;
reg [43:0] VCUPLENCARADDR1_out;
reg [1:0] VCUPLENCARBURST0_out;
reg [1:0] VCUPLENCARBURST1_out;
reg [3:0] VCUPLENCARCACHE0_out;
reg [3:0] VCUPLENCARCACHE1_out;
reg [3:0] VCUPLENCARID0_out;
reg [3:0] VCUPLENCARID1_out;
reg [7:0] VCUPLENCARLEN0_out;
reg [7:0] VCUPLENCARLEN1_out;
reg VCUPLENCARPROT0_out;
reg VCUPLENCARPROT1_out;
reg [3:0] VCUPLENCARQOS0_out;
reg [3:0] VCUPLENCARQOS1_out;
reg [2:0] VCUPLENCARSIZE0_out;
reg [2:0] VCUPLENCARSIZE1_out;
reg VCUPLENCARVALID0_out;
reg VCUPLENCARVALID1_out;
reg [43:0] VCUPLENCAWADDR0_out;
reg [43:0] VCUPLENCAWADDR1_out;
reg [1:0] VCUPLENCAWBURST0_out;
reg [1:0] VCUPLENCAWBURST1_out;
reg [3:0] VCUPLENCAWCACHE0_out;
reg [3:0] VCUPLENCAWCACHE1_out;
reg [3:0] VCUPLENCAWID0_out;
reg [3:0] VCUPLENCAWID1_out;
reg [7:0] VCUPLENCAWLEN0_out;
reg [7:0] VCUPLENCAWLEN1_out;
reg VCUPLENCAWPROT0_out;
reg VCUPLENCAWPROT1_out;
reg [3:0] VCUPLENCAWQOS0_out;
reg [3:0] VCUPLENCAWQOS1_out;
reg [2:0] VCUPLENCAWSIZE0_out;
reg [2:0] VCUPLENCAWSIZE1_out;
reg VCUPLENCAWVALID0_out;
reg VCUPLENCAWVALID1_out;
reg VCUPLENCBREADY0_out;
reg VCUPLENCBREADY1_out;
reg VCUPLENCRREADY0_out;
reg VCUPLENCRREADY1_out;
reg [127:0] VCUPLENCWDATA0_out;
reg [127:0] VCUPLENCWDATA1_out;
reg VCUPLENCWLAST0_out;
reg VCUPLENCWLAST1_out;
reg VCUPLENCWVALID0_out;
reg VCUPLENCWVALID1_out;
reg [43:0] VCUPLMCUMAXIICDCARADDR_out;
reg [1:0] VCUPLMCUMAXIICDCARBURST_out;
reg [3:0] VCUPLMCUMAXIICDCARCACHE_out;
reg [2:0] VCUPLMCUMAXIICDCARID_out;
reg [7:0] VCUPLMCUMAXIICDCARLEN_out;
reg VCUPLMCUMAXIICDCARLOCK_out;
reg [2:0] VCUPLMCUMAXIICDCARPROT_out;
reg [3:0] VCUPLMCUMAXIICDCARQOS_out;
reg [2:0] VCUPLMCUMAXIICDCARSIZE_out;
reg VCUPLMCUMAXIICDCARVALID_out;
reg [43:0] VCUPLMCUMAXIICDCAWADDR_out;
reg [1:0] VCUPLMCUMAXIICDCAWBURST_out;
reg [3:0] VCUPLMCUMAXIICDCAWCACHE_out;
reg [2:0] VCUPLMCUMAXIICDCAWID_out;
reg [7:0] VCUPLMCUMAXIICDCAWLEN_out;
reg VCUPLMCUMAXIICDCAWLOCK_out;
reg [2:0] VCUPLMCUMAXIICDCAWPROT_out;
reg [3:0] VCUPLMCUMAXIICDCAWQOS_out;
reg [2:0] VCUPLMCUMAXIICDCAWSIZE_out;
reg VCUPLMCUMAXIICDCAWVALID_out;
reg VCUPLMCUMAXIICDCBREADY_out;
reg VCUPLMCUMAXIICDCRREADY_out;
reg [31:0] VCUPLMCUMAXIICDCWDATA_out;
reg VCUPLMCUMAXIICDCWLAST_out;
reg [3:0] VCUPLMCUMAXIICDCWSTRB_out;
reg VCUPLMCUMAXIICDCWVALID_out;
reg VCUPLMCUSTATUSCLKPLL_out;
reg VCUPLPINTREQ_out;
reg VCUPLPLLSTATUSPLLLOCK_out;
reg VCUPLPWRSUPPLYSTATUSVCCAUX_out;
reg VCUPLPWRSUPPLYSTATUSVCUINT_out;
reg [31:0] VCUPLRDATAAXILITEAPB_out;
reg [1:0] VCUPLRRESPAXILITEAPB_out;
reg VCUPLRVALIDAXILITEAPB_out;
reg VCUPLWREADYAXILITEAPB_out;
wire INITPLVCUGASKETCLAMPCONTROLLVLSHVCCINTD_in;
wire PLVCUARVALIDAXILITEAPB_in;
wire PLVCUAWVALIDAXILITEAPB_in;
wire PLVCUAXIDECCLK_in;
wire PLVCUAXIENCCLK_in;
wire PLVCUAXILITECLK_in;
wire PLVCUAXIMCUCLK_in;
wire PLVCUBREADYAXILITEAPB_in;
wire PLVCUCORECLK_in;
wire PLVCUDECARREADY0_in;
wire PLVCUDECARREADY1_in;
wire PLVCUDECAWREADY0_in;
wire PLVCUDECAWREADY1_in;
wire PLVCUDECBVALID0_in;
wire PLVCUDECBVALID1_in;
wire PLVCUDECRLAST0_in;
wire PLVCUDECRLAST1_in;
wire PLVCUDECRVALID0_in;
wire PLVCUDECRVALID1_in;
wire PLVCUDECWREADY0_in;
wire PLVCUDECWREADY1_in;
wire PLVCUENCALL2CRREADY_in;
wire PLVCUENCARREADY0_in;
wire PLVCUENCARREADY1_in;
wire PLVCUENCAWREADY0_in;
wire PLVCUENCAWREADY1_in;
wire PLVCUENCBVALID0_in;
wire PLVCUENCBVALID1_in;
wire PLVCUENCL2CCLK_in;
wire PLVCUENCRLAST0_in;
wire PLVCUENCRLAST1_in;
wire PLVCUENCRVALID0_in;
wire PLVCUENCRVALID1_in;
wire PLVCUENCWREADY0_in;
wire PLVCUENCWREADY1_in;
wire PLVCUMCUCLK_in;
wire PLVCUMCUMAXIICDCARREADY_in;
wire PLVCUMCUMAXIICDCAWREADY_in;
wire PLVCUMCUMAXIICDCBVALID_in;
wire PLVCUMCUMAXIICDCRLAST_in;
wire PLVCUMCUMAXIICDCRVALID_in;
wire PLVCUMCUMAXIICDCWREADY_in;
wire PLVCUPLLREFCLKPL_in;
wire PLVCURAWRSTN_in;
wire PLVCURREADYAXILITEAPB_in;
wire PLVCUWVALIDAXILITEAPB_in;
wire [127:0] PLVCUDECRDATA0_in;
wire [127:0] PLVCUDECRDATA1_in;
wire [127:0] PLVCUENCRDATA0_in;
wire [127:0] PLVCUENCRDATA1_in;
wire [19:0] PLVCUARADDRAXILITEAPB_in;
wire [19:0] PLVCUAWADDRAXILITEAPB_in;
wire [1:0] PLVCUDECBRESP0_in;
wire [1:0] PLVCUDECBRESP1_in;
wire [1:0] PLVCUDECRRESP0_in;
wire [1:0] PLVCUDECRRESP1_in;
wire [1:0] PLVCUENCBRESP0_in;
wire [1:0] PLVCUENCBRESP1_in;
wire [1:0] PLVCUENCRRESP0_in;
wire [1:0] PLVCUENCRRESP1_in;
wire [1:0] PLVCUMCUMAXIICDCBRESP_in;
wire [1:0] PLVCUMCUMAXIICDCRRESP_in;
wire [2:0] PLVCUARPROTAXILITEAPB_in;
wire [2:0] PLVCUAWPROTAXILITEAPB_in;
wire [2:0] PLVCUMCUMAXIICDCBID_in;
wire [2:0] PLVCUMCUMAXIICDCRID_in;
wire [319:0] PLVCUENCALL2CRDATA_in;
wire [31:0] PLVCUMCUMAXIICDCRDATA_in;
wire [31:0] PLVCUWDATAAXILITEAPB_in;
wire [3:0] PLVCUDECBID0_in;
wire [3:0] PLVCUDECBID1_in;
wire [3:0] PLVCUDECRID0_in;
wire [3:0] PLVCUDECRID1_in;
wire [3:0] PLVCUENCBID0_in;
wire [3:0] PLVCUENCBID1_in;
wire [3:0] PLVCUENCRID0_in;
wire [3:0] PLVCUENCRID1_in;
wire [3:0] PLVCUWSTRBAXILITEAPB_in;
`ifdef XIL_TIMING
wire PLVCUARVALIDAXILITEAPB_delay;
wire PLVCUAWVALIDAXILITEAPB_delay;
wire PLVCUAXIDECCLK_delay;
wire PLVCUAXIENCCLK_delay;
wire PLVCUAXILITECLK_delay;
wire PLVCUAXIMCUCLK_delay;
wire PLVCUBREADYAXILITEAPB_delay;
wire PLVCUDECARREADY0_delay;
wire PLVCUDECARREADY1_delay;
wire PLVCUDECAWREADY0_delay;
wire PLVCUDECAWREADY1_delay;
wire PLVCUDECBVALID0_delay;
wire PLVCUDECBVALID1_delay;
wire PLVCUDECRLAST0_delay;
wire PLVCUDECRLAST1_delay;
wire PLVCUDECRVALID0_delay;
wire PLVCUDECRVALID1_delay;
wire PLVCUDECWREADY0_delay;
wire PLVCUDECWREADY1_delay;
wire PLVCUENCALL2CRREADY_delay;
wire PLVCUENCARREADY0_delay;
wire PLVCUENCARREADY1_delay;
wire PLVCUENCAWREADY0_delay;
wire PLVCUENCAWREADY1_delay;
wire PLVCUENCBVALID0_delay;
wire PLVCUENCBVALID1_delay;
wire PLVCUENCL2CCLK_delay;
wire PLVCUENCRLAST0_delay;
wire PLVCUENCRLAST1_delay;
wire PLVCUENCRVALID0_delay;
wire PLVCUENCRVALID1_delay;
wire PLVCUENCWREADY0_delay;
wire PLVCUENCWREADY1_delay;
wire PLVCUMCUMAXIICDCARREADY_delay;
wire PLVCUMCUMAXIICDCAWREADY_delay;
wire PLVCUMCUMAXIICDCBVALID_delay;
wire PLVCUMCUMAXIICDCRLAST_delay;
wire PLVCUMCUMAXIICDCRVALID_delay;
wire PLVCUMCUMAXIICDCWREADY_delay;
wire PLVCURREADYAXILITEAPB_delay;
wire PLVCUWVALIDAXILITEAPB_delay;
wire [127:0] PLVCUDECRDATA0_delay;
wire [127:0] PLVCUDECRDATA1_delay;
wire [127:0] PLVCUENCRDATA0_delay;
wire [127:0] PLVCUENCRDATA1_delay;
wire [19:0] PLVCUARADDRAXILITEAPB_delay;
wire [19:0] PLVCUAWADDRAXILITEAPB_delay;
wire [1:0] PLVCUDECBRESP0_delay;
wire [1:0] PLVCUDECBRESP1_delay;
wire [1:0] PLVCUDECRRESP0_delay;
wire [1:0] PLVCUDECRRESP1_delay;
wire [1:0] PLVCUENCBRESP0_delay;
wire [1:0] PLVCUENCBRESP1_delay;
wire [1:0] PLVCUENCRRESP0_delay;
wire [1:0] PLVCUENCRRESP1_delay;
wire [1:0] PLVCUMCUMAXIICDCBRESP_delay;
wire [1:0] PLVCUMCUMAXIICDCRRESP_delay;
wire [2:0] PLVCUARPROTAXILITEAPB_delay;
wire [2:0] PLVCUAWPROTAXILITEAPB_delay;
wire [2:0] PLVCUMCUMAXIICDCBID_delay;
wire [2:0] PLVCUMCUMAXIICDCRID_delay;
wire [319:0] PLVCUENCALL2CRDATA_delay;
wire [31:0] PLVCUMCUMAXIICDCRDATA_delay;
wire [31:0] PLVCUWDATAAXILITEAPB_delay;
wire [3:0] PLVCUDECBID0_delay;
wire [3:0] PLVCUDECBID1_delay;
wire [3:0] PLVCUDECRID0_delay;
wire [3:0] PLVCUDECRID1_delay;
wire [3:0] PLVCUENCBID0_delay;
wire [3:0] PLVCUENCBID1_delay;
wire [3:0] PLVCUENCRID0_delay;
wire [3:0] PLVCUENCRID1_delay;
wire [3:0] PLVCUWSTRBAXILITEAPB_delay;
`endif
// assign VCUPLCORESTATUSCLKPLL = VCUPLCORESTATUSCLKPLL_out;
// assign VCUPLMCUSTATUSCLKPLL = VCUPLMCUSTATUSCLKPLL_out;
assign VCUPLARREADYAXILITEAPB = VCUPLARREADYAXILITEAPB_out;
assign VCUPLAWREADYAXILITEAPB = VCUPLAWREADYAXILITEAPB_out;
assign VCUPLBRESPAXILITEAPB = VCUPLBRESPAXILITEAPB_out;
assign VCUPLBVALIDAXILITEAPB = VCUPLBVALIDAXILITEAPB_out;
assign VCUPLCORESTATUSCLKPLL = VCUPLCORESTATUSCLKPLL_out;
assign VCUPLDECARADDR0 = VCUPLDECARADDR0_out;
assign VCUPLDECARADDR1 = VCUPLDECARADDR1_out;
assign VCUPLDECARBURST0 = VCUPLDECARBURST0_out;
assign VCUPLDECARBURST1 = VCUPLDECARBURST1_out;
assign VCUPLDECARCACHE0 = VCUPLDECARCACHE0_out;
assign VCUPLDECARCACHE1 = VCUPLDECARCACHE1_out;
assign VCUPLDECARID0 = VCUPLDECARID0_out;
assign VCUPLDECARID1 = VCUPLDECARID1_out;
assign VCUPLDECARLEN0 = VCUPLDECARLEN0_out;
assign VCUPLDECARLEN1 = VCUPLDECARLEN1_out;
assign VCUPLDECARPROT0 = VCUPLDECARPROT0_out;
assign VCUPLDECARPROT1 = VCUPLDECARPROT1_out;
assign VCUPLDECARQOS0 = VCUPLDECARQOS0_out;
assign VCUPLDECARQOS1 = VCUPLDECARQOS1_out;
assign VCUPLDECARSIZE0 = VCUPLDECARSIZE0_out;
assign VCUPLDECARSIZE1 = VCUPLDECARSIZE1_out;
assign VCUPLDECARVALID0 = VCUPLDECARVALID0_out;
assign VCUPLDECARVALID1 = VCUPLDECARVALID1_out;
assign VCUPLDECAWADDR0 = VCUPLDECAWADDR0_out;
assign VCUPLDECAWADDR1 = VCUPLDECAWADDR1_out;
assign VCUPLDECAWBURST0 = VCUPLDECAWBURST0_out;
assign VCUPLDECAWBURST1 = VCUPLDECAWBURST1_out;
assign VCUPLDECAWCACHE0 = VCUPLDECAWCACHE0_out;
assign VCUPLDECAWCACHE1 = VCUPLDECAWCACHE1_out;
assign VCUPLDECAWID0 = VCUPLDECAWID0_out;
assign VCUPLDECAWID1 = VCUPLDECAWID1_out;
assign VCUPLDECAWLEN0 = VCUPLDECAWLEN0_out;
assign VCUPLDECAWLEN1 = VCUPLDECAWLEN1_out;
assign VCUPLDECAWPROT0 = VCUPLDECAWPROT0_out;
assign VCUPLDECAWPROT1 = VCUPLDECAWPROT1_out;
assign VCUPLDECAWQOS0 = VCUPLDECAWQOS0_out;
assign VCUPLDECAWQOS1 = VCUPLDECAWQOS1_out;
assign VCUPLDECAWSIZE0 = VCUPLDECAWSIZE0_out;
assign VCUPLDECAWSIZE1 = VCUPLDECAWSIZE1_out;
assign VCUPLDECAWVALID0 = VCUPLDECAWVALID0_out;
assign VCUPLDECAWVALID1 = VCUPLDECAWVALID1_out;
assign VCUPLDECBREADY0 = VCUPLDECBREADY0_out;
assign VCUPLDECBREADY1 = VCUPLDECBREADY1_out;
assign VCUPLDECRREADY0 = VCUPLDECRREADY0_out;
assign VCUPLDECRREADY1 = VCUPLDECRREADY1_out;
assign VCUPLDECWDATA0 = VCUPLDECWDATA0_out;
assign VCUPLDECWDATA1 = VCUPLDECWDATA1_out;
assign VCUPLDECWLAST0 = VCUPLDECWLAST0_out;
assign VCUPLDECWLAST1 = VCUPLDECWLAST1_out;
assign VCUPLDECWVALID0 = VCUPLDECWVALID0_out;
assign VCUPLDECWVALID1 = VCUPLDECWVALID1_out;
assign VCUPLENCALL2CADDR = VCUPLENCALL2CADDR_out;
assign VCUPLENCALL2CRVALID = VCUPLENCALL2CRVALID_out;
assign VCUPLENCALL2CWDATA = VCUPLENCALL2CWDATA_out;
assign VCUPLENCALL2CWVALID = VCUPLENCALL2CWVALID_out;
assign VCUPLENCARADDR0 = VCUPLENCARADDR0_out;
assign VCUPLENCARADDR1 = VCUPLENCARADDR1_out;
assign VCUPLENCARBURST0 = VCUPLENCARBURST0_out;
assign VCUPLENCARBURST1 = VCUPLENCARBURST1_out;
assign VCUPLENCARCACHE0 = VCUPLENCARCACHE0_out;
assign VCUPLENCARCACHE1 = VCUPLENCARCACHE1_out;
assign VCUPLENCARID0 = VCUPLENCARID0_out;
assign VCUPLENCARID1 = VCUPLENCARID1_out;
assign VCUPLENCARLEN0 = VCUPLENCARLEN0_out;
assign VCUPLENCARLEN1 = VCUPLENCARLEN1_out;
assign VCUPLENCARPROT0 = VCUPLENCARPROT0_out;
assign VCUPLENCARPROT1 = VCUPLENCARPROT1_out;
assign VCUPLENCARQOS0 = VCUPLENCARQOS0_out;
assign VCUPLENCARQOS1 = VCUPLENCARQOS1_out;
assign VCUPLENCARSIZE0 = VCUPLENCARSIZE0_out;
assign VCUPLENCARSIZE1 = VCUPLENCARSIZE1_out;
assign VCUPLENCARVALID0 = VCUPLENCARVALID0_out;
assign VCUPLENCARVALID1 = VCUPLENCARVALID1_out;
assign VCUPLENCAWADDR0 = VCUPLENCAWADDR0_out;
assign VCUPLENCAWADDR1 = VCUPLENCAWADDR1_out;
assign VCUPLENCAWBURST0 = VCUPLENCAWBURST0_out;
assign VCUPLENCAWBURST1 = VCUPLENCAWBURST1_out;
assign VCUPLENCAWCACHE0 = VCUPLENCAWCACHE0_out;
assign VCUPLENCAWCACHE1 = VCUPLENCAWCACHE1_out;
assign VCUPLENCAWID0 = VCUPLENCAWID0_out;
assign VCUPLENCAWID1 = VCUPLENCAWID1_out;
assign VCUPLENCAWLEN0 = VCUPLENCAWLEN0_out;
assign VCUPLENCAWLEN1 = VCUPLENCAWLEN1_out;
assign VCUPLENCAWPROT0 = VCUPLENCAWPROT0_out;
assign VCUPLENCAWPROT1 = VCUPLENCAWPROT1_out;
assign VCUPLENCAWQOS0 = VCUPLENCAWQOS0_out;
assign VCUPLENCAWQOS1 = VCUPLENCAWQOS1_out;
assign VCUPLENCAWSIZE0 = VCUPLENCAWSIZE0_out;
assign VCUPLENCAWSIZE1 = VCUPLENCAWSIZE1_out;
assign VCUPLENCAWVALID0 = VCUPLENCAWVALID0_out;
assign VCUPLENCAWVALID1 = VCUPLENCAWVALID1_out;
assign VCUPLENCBREADY0 = VCUPLENCBREADY0_out;
assign VCUPLENCBREADY1 = VCUPLENCBREADY1_out;
assign VCUPLENCRREADY0 = VCUPLENCRREADY0_out;
assign VCUPLENCRREADY1 = VCUPLENCRREADY1_out;
assign VCUPLENCWDATA0 = VCUPLENCWDATA0_out;
assign VCUPLENCWDATA1 = VCUPLENCWDATA1_out;
assign VCUPLENCWLAST0 = VCUPLENCWLAST0_out;
assign VCUPLENCWLAST1 = VCUPLENCWLAST1_out;
assign VCUPLENCWVALID0 = VCUPLENCWVALID0_out;
assign VCUPLENCWVALID1 = VCUPLENCWVALID1_out;
assign VCUPLMCUMAXIICDCARADDR = VCUPLMCUMAXIICDCARADDR_out;
assign VCUPLMCUMAXIICDCARBURST = VCUPLMCUMAXIICDCARBURST_out;
assign VCUPLMCUMAXIICDCARCACHE = VCUPLMCUMAXIICDCARCACHE_out;
assign VCUPLMCUMAXIICDCARID = VCUPLMCUMAXIICDCARID_out;
assign VCUPLMCUMAXIICDCARLEN = VCUPLMCUMAXIICDCARLEN_out;
assign VCUPLMCUMAXIICDCARLOCK = VCUPLMCUMAXIICDCARLOCK_out;
assign VCUPLMCUMAXIICDCARPROT = VCUPLMCUMAXIICDCARPROT_out;
assign VCUPLMCUMAXIICDCARQOS = VCUPLMCUMAXIICDCARQOS_out;
assign VCUPLMCUMAXIICDCARSIZE = VCUPLMCUMAXIICDCARSIZE_out;
assign VCUPLMCUMAXIICDCARVALID = VCUPLMCUMAXIICDCARVALID_out;
assign VCUPLMCUMAXIICDCAWADDR = VCUPLMCUMAXIICDCAWADDR_out;
assign VCUPLMCUMAXIICDCAWBURST = VCUPLMCUMAXIICDCAWBURST_out;
assign VCUPLMCUMAXIICDCAWCACHE = VCUPLMCUMAXIICDCAWCACHE_out;
assign VCUPLMCUMAXIICDCAWID = VCUPLMCUMAXIICDCAWID_out;
assign VCUPLMCUMAXIICDCAWLEN = VCUPLMCUMAXIICDCAWLEN_out;
assign VCUPLMCUMAXIICDCAWLOCK = VCUPLMCUMAXIICDCAWLOCK_out;
assign VCUPLMCUMAXIICDCAWPROT = VCUPLMCUMAXIICDCAWPROT_out;
assign VCUPLMCUMAXIICDCAWQOS = VCUPLMCUMAXIICDCAWQOS_out;
assign VCUPLMCUMAXIICDCAWSIZE = VCUPLMCUMAXIICDCAWSIZE_out;
assign VCUPLMCUMAXIICDCAWVALID = VCUPLMCUMAXIICDCAWVALID_out;
assign VCUPLMCUMAXIICDCBREADY = VCUPLMCUMAXIICDCBREADY_out;
assign VCUPLMCUMAXIICDCRREADY = VCUPLMCUMAXIICDCRREADY_out;
assign VCUPLMCUMAXIICDCWDATA = VCUPLMCUMAXIICDCWDATA_out;
assign VCUPLMCUMAXIICDCWLAST = VCUPLMCUMAXIICDCWLAST_out;
assign VCUPLMCUMAXIICDCWSTRB = VCUPLMCUMAXIICDCWSTRB_out;
assign VCUPLMCUMAXIICDCWVALID = VCUPLMCUMAXIICDCWVALID_out;
assign VCUPLMCUSTATUSCLKPLL = VCUPLMCUSTATUSCLKPLL_out;
assign VCUPLPINTREQ = VCUPLPINTREQ_out;
assign VCUPLPLLSTATUSPLLLOCK = VCUPLPLLSTATUSPLLLOCK_out;
assign VCUPLPWRSUPPLYSTATUSVCCAUX = VCUPLPWRSUPPLYSTATUSVCCAUX_out;
assign VCUPLPWRSUPPLYSTATUSVCUINT = VCUPLPWRSUPPLYSTATUSVCUINT_out;
assign VCUPLRDATAAXILITEAPB = VCUPLRDATAAXILITEAPB_out;
assign VCUPLRRESPAXILITEAPB = VCUPLRRESPAXILITEAPB_out;
assign VCUPLRVALIDAXILITEAPB = VCUPLRVALIDAXILITEAPB_out;
assign VCUPLWREADYAXILITEAPB = VCUPLWREADYAXILITEAPB_out;
`ifdef XIL_TIMING
assign PLVCUARADDRAXILITEAPB_in = PLVCUARADDRAXILITEAPB_delay;
assign PLVCUARPROTAXILITEAPB_in = PLVCUARPROTAXILITEAPB_delay;
assign PLVCUARVALIDAXILITEAPB_in = PLVCUARVALIDAXILITEAPB_delay;
assign PLVCUAWADDRAXILITEAPB_in = PLVCUAWADDRAXILITEAPB_delay;
assign PLVCUAWPROTAXILITEAPB_in = PLVCUAWPROTAXILITEAPB_delay;
assign PLVCUAWVALIDAXILITEAPB_in = PLVCUAWVALIDAXILITEAPB_delay;
assign PLVCUAXIDECCLK_in = PLVCUAXIDECCLK_delay;
assign PLVCUAXIENCCLK_in = PLVCUAXIENCCLK_delay;
assign PLVCUAXILITECLK_in = PLVCUAXILITECLK_delay;
assign PLVCUAXIMCUCLK_in = PLVCUAXIMCUCLK_delay;
assign PLVCUBREADYAXILITEAPB_in = PLVCUBREADYAXILITEAPB_delay;
assign PLVCUDECARREADY0_in = PLVCUDECARREADY0_delay;
assign PLVCUDECARREADY1_in = PLVCUDECARREADY1_delay;
assign PLVCUDECAWREADY0_in = PLVCUDECAWREADY0_delay;
assign PLVCUDECAWREADY1_in = PLVCUDECAWREADY1_delay;
assign PLVCUDECBID0_in = PLVCUDECBID0_delay;
assign PLVCUDECBID1_in = PLVCUDECBID1_delay;
assign PLVCUDECBRESP0_in = PLVCUDECBRESP0_delay;
assign PLVCUDECBRESP1_in = PLVCUDECBRESP1_delay;
assign PLVCUDECBVALID0_in = PLVCUDECBVALID0_delay;
assign PLVCUDECBVALID1_in = PLVCUDECBVALID1_delay;
assign PLVCUDECRDATA0_in = PLVCUDECRDATA0_delay;
assign PLVCUDECRDATA1_in = PLVCUDECRDATA1_delay;
assign PLVCUDECRID0_in = PLVCUDECRID0_delay;
assign PLVCUDECRID1_in = PLVCUDECRID1_delay;
assign PLVCUDECRLAST0_in = PLVCUDECRLAST0_delay;
assign PLVCUDECRLAST1_in = PLVCUDECRLAST1_delay;
assign PLVCUDECRRESP0_in = PLVCUDECRRESP0_delay;
assign PLVCUDECRRESP1_in = PLVCUDECRRESP1_delay;
assign PLVCUDECRVALID0_in = PLVCUDECRVALID0_delay;
assign PLVCUDECRVALID1_in = PLVCUDECRVALID1_delay;
assign PLVCUDECWREADY0_in = PLVCUDECWREADY0_delay;
assign PLVCUDECWREADY1_in = PLVCUDECWREADY1_delay;
assign PLVCUENCALL2CRDATA_in = PLVCUENCALL2CRDATA_delay;
assign PLVCUENCALL2CRREADY_in = (PLVCUENCALL2CRREADY === 1'bz) || PLVCUENCALL2CRREADY_delay; // rv 1
assign PLVCUENCARREADY0_in = PLVCUENCARREADY0_delay;
assign PLVCUENCARREADY1_in = PLVCUENCARREADY1_delay;
assign PLVCUENCAWREADY0_in = PLVCUENCAWREADY0_delay;
assign PLVCUENCAWREADY1_in = PLVCUENCAWREADY1_delay;
assign PLVCUENCBID0_in = PLVCUENCBID0_delay;
assign PLVCUENCBID1_in = PLVCUENCBID1_delay;
assign PLVCUENCBRESP0_in = PLVCUENCBRESP0_delay;
assign PLVCUENCBRESP1_in = PLVCUENCBRESP1_delay;
assign PLVCUENCBVALID0_in = PLVCUENCBVALID0_delay;
assign PLVCUENCBVALID1_in = PLVCUENCBVALID1_delay;
assign PLVCUENCL2CCLK_in = PLVCUENCL2CCLK_delay;
assign PLVCUENCRDATA0_in = PLVCUENCRDATA0_delay;
assign PLVCUENCRDATA1_in = PLVCUENCRDATA1_delay;
assign PLVCUENCRID0_in = PLVCUENCRID0_delay;
assign PLVCUENCRID1_in = PLVCUENCRID1_delay;
assign PLVCUENCRLAST0_in = PLVCUENCRLAST0_delay;
assign PLVCUENCRLAST1_in = PLVCUENCRLAST1_delay;
assign PLVCUENCRRESP0_in = PLVCUENCRRESP0_delay;
assign PLVCUENCRRESP1_in = PLVCUENCRRESP1_delay;
assign PLVCUENCRVALID0_in = PLVCUENCRVALID0_delay;
assign PLVCUENCRVALID1_in = PLVCUENCRVALID1_delay;
assign PLVCUENCWREADY0_in = PLVCUENCWREADY0_delay;
assign PLVCUENCWREADY1_in = PLVCUENCWREADY1_delay;
assign PLVCUMCUMAXIICDCARREADY_in = PLVCUMCUMAXIICDCARREADY_delay;
assign PLVCUMCUMAXIICDCAWREADY_in = PLVCUMCUMAXIICDCAWREADY_delay;
assign PLVCUMCUMAXIICDCBID_in = PLVCUMCUMAXIICDCBID_delay;
assign PLVCUMCUMAXIICDCBRESP_in = PLVCUMCUMAXIICDCBRESP_delay;
assign PLVCUMCUMAXIICDCBVALID_in = PLVCUMCUMAXIICDCBVALID_delay;
assign PLVCUMCUMAXIICDCRDATA_in = PLVCUMCUMAXIICDCRDATA_delay;
assign PLVCUMCUMAXIICDCRID_in = PLVCUMCUMAXIICDCRID_delay;
assign PLVCUMCUMAXIICDCRLAST_in = PLVCUMCUMAXIICDCRLAST_delay;
assign PLVCUMCUMAXIICDCRRESP_in = PLVCUMCUMAXIICDCRRESP_delay;
assign PLVCUMCUMAXIICDCRVALID_in = PLVCUMCUMAXIICDCRVALID_delay;
assign PLVCUMCUMAXIICDCWREADY_in = PLVCUMCUMAXIICDCWREADY_delay;
assign PLVCURREADYAXILITEAPB_in = PLVCURREADYAXILITEAPB_delay;
assign PLVCUWDATAAXILITEAPB_in = PLVCUWDATAAXILITEAPB_delay;
assign PLVCUWSTRBAXILITEAPB_in = PLVCUWSTRBAXILITEAPB_delay;
assign PLVCUWVALIDAXILITEAPB_in = PLVCUWVALIDAXILITEAPB_delay;
`else
assign PLVCUARADDRAXILITEAPB_in = PLVCUARADDRAXILITEAPB;
assign PLVCUARPROTAXILITEAPB_in = PLVCUARPROTAXILITEAPB;
assign PLVCUARVALIDAXILITEAPB_in = PLVCUARVALIDAXILITEAPB;
assign PLVCUAWADDRAXILITEAPB_in = PLVCUAWADDRAXILITEAPB;
assign PLVCUAWPROTAXILITEAPB_in = PLVCUAWPROTAXILITEAPB;
assign PLVCUAWVALIDAXILITEAPB_in = PLVCUAWVALIDAXILITEAPB;
assign PLVCUAXIDECCLK_in = PLVCUAXIDECCLK;
assign PLVCUAXIENCCLK_in = PLVCUAXIENCCLK;
assign PLVCUAXILITECLK_in = PLVCUAXILITECLK;
assign PLVCUAXIMCUCLK_in = PLVCUAXIMCUCLK;
assign PLVCUBREADYAXILITEAPB_in = PLVCUBREADYAXILITEAPB;
assign PLVCUDECARREADY0_in = PLVCUDECARREADY0;
assign PLVCUDECARREADY1_in = PLVCUDECARREADY1;
assign PLVCUDECAWREADY0_in = PLVCUDECAWREADY0;
assign PLVCUDECAWREADY1_in = PLVCUDECAWREADY1;
assign PLVCUDECBID0_in = PLVCUDECBID0;
assign PLVCUDECBID1_in = PLVCUDECBID1;
assign PLVCUDECBRESP0_in = PLVCUDECBRESP0;
assign PLVCUDECBRESP1_in = PLVCUDECBRESP1;
assign PLVCUDECBVALID0_in = PLVCUDECBVALID0;
assign PLVCUDECBVALID1_in = PLVCUDECBVALID1;
assign PLVCUDECRDATA0_in = PLVCUDECRDATA0;
assign PLVCUDECRDATA1_in = PLVCUDECRDATA1;
assign PLVCUDECRID0_in = PLVCUDECRID0;
assign PLVCUDECRID1_in = PLVCUDECRID1;
assign PLVCUDECRLAST0_in = PLVCUDECRLAST0;
assign PLVCUDECRLAST1_in = PLVCUDECRLAST1;
assign PLVCUDECRRESP0_in = PLVCUDECRRESP0;
assign PLVCUDECRRESP1_in = PLVCUDECRRESP1;
assign PLVCUDECRVALID0_in = PLVCUDECRVALID0;
assign PLVCUDECRVALID1_in = PLVCUDECRVALID1;
assign PLVCUDECWREADY0_in = PLVCUDECWREADY0;
assign PLVCUDECWREADY1_in = PLVCUDECWREADY1;
assign PLVCUENCALL2CRDATA_in = PLVCUENCALL2CRDATA;
assign PLVCUENCALL2CRREADY_in = (PLVCUENCALL2CRREADY === 1'bz) || PLVCUENCALL2CRREADY; // rv 1
assign PLVCUENCARREADY0_in = PLVCUENCARREADY0;
assign PLVCUENCARREADY1_in = PLVCUENCARREADY1;
assign PLVCUENCAWREADY0_in = PLVCUENCAWREADY0;
assign PLVCUENCAWREADY1_in = PLVCUENCAWREADY1;
assign PLVCUENCBID0_in = PLVCUENCBID0;
assign PLVCUENCBID1_in = PLVCUENCBID1;
assign PLVCUENCBRESP0_in = PLVCUENCBRESP0;
assign PLVCUENCBRESP1_in = PLVCUENCBRESP1;
assign PLVCUENCBVALID0_in = PLVCUENCBVALID0;
assign PLVCUENCBVALID1_in = PLVCUENCBVALID1;
assign PLVCUENCL2CCLK_in = PLVCUENCL2CCLK;
assign PLVCUENCRDATA0_in = PLVCUENCRDATA0;
assign PLVCUENCRDATA1_in = PLVCUENCRDATA1;
assign PLVCUENCRID0_in = PLVCUENCRID0;
assign PLVCUENCRID1_in = PLVCUENCRID1;
assign PLVCUENCRLAST0_in = PLVCUENCRLAST0;
assign PLVCUENCRLAST1_in = PLVCUENCRLAST1;
assign PLVCUENCRRESP0_in = PLVCUENCRRESP0;
assign PLVCUENCRRESP1_in = PLVCUENCRRESP1;
assign PLVCUENCRVALID0_in = PLVCUENCRVALID0;
assign PLVCUENCRVALID1_in = PLVCUENCRVALID1;
assign PLVCUENCWREADY0_in = PLVCUENCWREADY0;
assign PLVCUENCWREADY1_in = PLVCUENCWREADY1;
assign PLVCUMCUMAXIICDCARREADY_in = PLVCUMCUMAXIICDCARREADY;
assign PLVCUMCUMAXIICDCAWREADY_in = PLVCUMCUMAXIICDCAWREADY;
assign PLVCUMCUMAXIICDCBID_in = PLVCUMCUMAXIICDCBID;
assign PLVCUMCUMAXIICDCBRESP_in = PLVCUMCUMAXIICDCBRESP;
assign PLVCUMCUMAXIICDCBVALID_in = PLVCUMCUMAXIICDCBVALID;
assign PLVCUMCUMAXIICDCRDATA_in = PLVCUMCUMAXIICDCRDATA;
assign PLVCUMCUMAXIICDCRID_in = PLVCUMCUMAXIICDCRID;
assign PLVCUMCUMAXIICDCRLAST_in = PLVCUMCUMAXIICDCRLAST;
assign PLVCUMCUMAXIICDCRRESP_in = PLVCUMCUMAXIICDCRRESP;
assign PLVCUMCUMAXIICDCRVALID_in = PLVCUMCUMAXIICDCRVALID;
assign PLVCUMCUMAXIICDCWREADY_in = PLVCUMCUMAXIICDCWREADY;
assign PLVCURREADYAXILITEAPB_in = PLVCURREADYAXILITEAPB;
assign PLVCUWDATAAXILITEAPB_in = PLVCUWDATAAXILITEAPB;
assign PLVCUWSTRBAXILITEAPB_in = PLVCUWSTRBAXILITEAPB;
assign PLVCUWVALIDAXILITEAPB_in = PLVCUWVALIDAXILITEAPB;
`endif
assign INITPLVCUGASKETCLAMPCONTROLLVLSHVCCINTD_in = INITPLVCUGASKETCLAMPCONTROLLVLSHVCCINTD;
assign PLVCUCORECLK_in = PLVCUCORECLK;
assign PLVCUMCUCLK_in = PLVCUMCUCLK;
assign PLVCUPLLREFCLKPL_in = PLVCUPLLREFCLKPL;
assign PLVCURAWRSTN_in = PLVCURAWRSTN;
`ifndef XIL_XECLIB
initial begin
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign CORECLKREQ_BIN = CORECLKREQ_REG[9:0];
assign DECHORRESOLUTION_BIN = DECHORRESOLUTION_REG[13:0];
assign DECODERCHROMAFORMAT_BIN =
(DECODERCHROMAFORMAT_REG == "4_2_2") ? DECODERCHROMAFORMAT_4_2_2 :
(DECODERCHROMAFORMAT_REG == "4_2_0") ? DECODERCHROMAFORMAT_4_2_0 :
DECODERCHROMAFORMAT_4_2_2;
assign DECODERCODING_BIN =
(DECODERCODING_REG == "H.265") ? DECODERCODING_H_265 :
(DECODERCODING_REG == "H.264") ? DECODERCODING_H_264 :
DECODERCODING_H_265;
assign DECODERCOLORDEPTH_BIN = DECODERCOLORDEPTH_REG[3:0];
assign DECODERNUMCORES_BIN = DECODERNUMCORES_REG[1:0];
assign DECVERTRESOLUTION_BIN = DECVERTRESOLUTION_REG[12:0];
assign ENABLEDECODER_BIN =
(ENABLEDECODER_REG == "TRUE") ? ENABLEDECODER_TRUE :
(ENABLEDECODER_REG == "FALSE") ? ENABLEDECODER_FALSE :
ENABLEDECODER_TRUE;
assign ENABLEENCODER_BIN =
(ENABLEENCODER_REG == "TRUE") ? ENABLEENCODER_TRUE :
(ENABLEENCODER_REG == "FALSE") ? ENABLEENCODER_FALSE :
ENABLEENCODER_TRUE;
assign ENCHORRESOLUTION_BIN = ENCHORRESOLUTION_REG[13:0];
assign ENCODERCHROMAFORMAT_BIN =
(ENCODERCHROMAFORMAT_REG == "4_2_2") ? ENCODERCHROMAFORMAT_4_2_2 :
(ENCODERCHROMAFORMAT_REG == "4_2_0") ? ENCODERCHROMAFORMAT_4_2_0 :
ENCODERCHROMAFORMAT_4_2_2;
assign ENCODERCODING_BIN =
(ENCODERCODING_REG == "H.265") ? ENCODERCODING_H_265 :
(ENCODERCODING_REG == "H.264") ? ENCODERCODING_H_264 :
ENCODERCODING_H_265;
assign ENCODERCOLORDEPTH_BIN = ENCODERCOLORDEPTH_REG[3:0];
assign ENCODERNUMCORES_BIN = ENCODERNUMCORES_REG[2:0];
assign ENCVERTRESOLUTION_BIN = ENCVERTRESOLUTION_REG[12:0];
`else
always @ (trig_attr) begin
#1;
CORECLKREQ_BIN = CORECLKREQ_REG[9:0];
DECHORRESOLUTION_BIN = DECHORRESOLUTION_REG[13:0];
DECODERCHROMAFORMAT_BIN =
(DECODERCHROMAFORMAT_REG == "4_2_2") ? DECODERCHROMAFORMAT_4_2_2 :
(DECODERCHROMAFORMAT_REG == "4_2_0") ? DECODERCHROMAFORMAT_4_2_0 :
DECODERCHROMAFORMAT_4_2_2;
DECODERCODING_BIN =
(DECODERCODING_REG == "H.265") ? DECODERCODING_H_265 :
(DECODERCODING_REG == "H.264") ? DECODERCODING_H_264 :
DECODERCODING_H_265;
DECODERCOLORDEPTH_BIN = DECODERCOLORDEPTH_REG[3:0];
DECODERNUMCORES_BIN = DECODERNUMCORES_REG[1:0];
DECVERTRESOLUTION_BIN = DECVERTRESOLUTION_REG[12:0];
ENABLEDECODER_BIN =
(ENABLEDECODER_REG == "TRUE") ? ENABLEDECODER_TRUE :
(ENABLEDECODER_REG == "FALSE") ? ENABLEDECODER_FALSE :
ENABLEDECODER_TRUE;
ENABLEENCODER_BIN =
(ENABLEENCODER_REG == "TRUE") ? ENABLEENCODER_TRUE :
(ENABLEENCODER_REG == "FALSE") ? ENABLEENCODER_FALSE :
ENABLEENCODER_TRUE;
ENCHORRESOLUTION_BIN = ENCHORRESOLUTION_REG[13:0];
ENCODERCHROMAFORMAT_BIN =
(ENCODERCHROMAFORMAT_REG == "4_2_2") ? ENCODERCHROMAFORMAT_4_2_2 :
(ENCODERCHROMAFORMAT_REG == "4_2_0") ? ENCODERCHROMAFORMAT_4_2_0 :
ENCODERCHROMAFORMAT_4_2_2;
ENCODERCODING_BIN =
(ENCODERCODING_REG == "H.265") ? ENCODERCODING_H_265 :
(ENCODERCODING_REG == "H.264") ? ENCODERCODING_H_264 :
ENCODERCODING_H_265;
ENCODERCOLORDEPTH_BIN = ENCODERCOLORDEPTH_REG[3:0];
ENCODERNUMCORES_BIN = ENCODERNUMCORES_REG[2:0];
ENCVERTRESOLUTION_BIN = ENCVERTRESOLUTION_REG[12:0];
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((CORECLKREQ_REG < 0) || (CORECLKREQ_REG > 667))) begin
$display("Error: [Unisim %s-101] CORECLKREQ attribute is set to %d. Legal values for this attribute are 0 to 667. Instance: %m", MODULE_NAME, CORECLKREQ_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DECHORRESOLUTION_REG < 320) || (DECHORRESOLUTION_REG > 8192))) begin
$display("Error: [Unisim %s-102] DECHORRESOLUTION attribute is set to %d. Legal values for this attribute are 320 to 8192. Instance: %m", MODULE_NAME, DECHORRESOLUTION_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DECODERCHROMAFORMAT_REG != "4_2_2") &&
(DECODERCHROMAFORMAT_REG != "4_2_0"))) begin
$display("Error: [Unisim %s-103] DECODERCHROMAFORMAT attribute is set to %s. Legal values for this attribute are 4_2_2 or 4_2_0. Instance: %m", MODULE_NAME, DECODERCHROMAFORMAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DECODERCODING_REG != "H.265") &&
(DECODERCODING_REG != "H.264"))) begin
$display("Error: [Unisim %s-104] DECODERCODING attribute is set to %s. Legal values for this attribute are H.265 or H.264. Instance: %m", MODULE_NAME, DECODERCODING_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DECODERCOLORDEPTH_REG != 10) &&
(DECODERCOLORDEPTH_REG != 8))) begin
$display("Error: [Unisim %s-105] DECODERCOLORDEPTH attribute is set to %d. Legal values for this attribute are 10 or 8. Instance: %m", MODULE_NAME, DECODERCOLORDEPTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DECODERNUMCORES_REG < 1) || (DECODERNUMCORES_REG > 2))) begin
$display("Error: [Unisim %s-106] DECODERNUMCORES attribute is set to %d. Legal values for this attribute are 1 to 2. Instance: %m", MODULE_NAME, DECODERNUMCORES_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DECVERTRESOLUTION_REG < 240) || (DECVERTRESOLUTION_REG > 4352))) begin
$display("Error: [Unisim %s-107] DECVERTRESOLUTION attribute is set to %d. Legal values for this attribute are 240 to 4352. Instance: %m", MODULE_NAME, DECVERTRESOLUTION_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ENABLEDECODER_REG != "TRUE") &&
(ENABLEDECODER_REG != "FALSE"))) begin
$display("Error: [Unisim %s-108] ENABLEDECODER attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ENABLEDECODER_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ENABLEENCODER_REG != "TRUE") &&
(ENABLEENCODER_REG != "FALSE"))) begin
$display("Error: [Unisim %s-109] ENABLEENCODER attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ENABLEENCODER_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ENCHORRESOLUTION_REG < 320) || (ENCHORRESOLUTION_REG > 8192))) begin
$display("Error: [Unisim %s-110] ENCHORRESOLUTION attribute is set to %d. Legal values for this attribute are 320 to 8192. Instance: %m", MODULE_NAME, ENCHORRESOLUTION_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ENCODERCHROMAFORMAT_REG != "4_2_2") &&
(ENCODERCHROMAFORMAT_REG != "4_2_0"))) begin
$display("Error: [Unisim %s-111] ENCODERCHROMAFORMAT attribute is set to %s. Legal values for this attribute are 4_2_2 or 4_2_0. Instance: %m", MODULE_NAME, ENCODERCHROMAFORMAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ENCODERCODING_REG != "H.265") &&
(ENCODERCODING_REG != "H.264"))) begin
$display("Error: [Unisim %s-112] ENCODERCODING attribute is set to %s. Legal values for this attribute are H.265 or H.264. Instance: %m", MODULE_NAME, ENCODERCODING_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ENCODERCOLORDEPTH_REG != 10) &&
(ENCODERCOLORDEPTH_REG != 8))) begin
$display("Error: [Unisim %s-113] ENCODERCOLORDEPTH attribute is set to %d. Legal values for this attribute are 10 or 8. Instance: %m", MODULE_NAME, ENCODERCOLORDEPTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ENCODERNUMCORES_REG < 1) || (ENCODERNUMCORES_REG > 4))) begin
$display("Error: [Unisim %s-114] ENCODERNUMCORES attribute is set to %d. Legal values for this attribute are 1 to 4. Instance: %m", MODULE_NAME, ENCODERNUMCORES_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ENCVERTRESOLUTION_REG < 240) || (ENCVERTRESOLUTION_REG > 4352))) begin
$display("Error: [Unisim %s-115] ENCVERTRESOLUTION attribute is set to %d. Legal values for this attribute are 240 to 4352. Instance: %m", MODULE_NAME, ENCVERTRESOLUTION_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
reg notifier;
`endif
specify
(PLVCUAXIDECCLK => VCUPLDECARADDR0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[10]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[11]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[12]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[13]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[14]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[15]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[16]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[17]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[18]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[19]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[20]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[21]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[22]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[23]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[24]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[25]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[26]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[27]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[28]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[29]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[30]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[31]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[32]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[33]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[34]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[35]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[36]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[37]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[38]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[39]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[40]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[41]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[42]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[43]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[4]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[5]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[6]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[7]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[8]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR0[9]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[10]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[11]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[12]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[13]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[14]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[15]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[16]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[17]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[18]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[19]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[20]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[21]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[22]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[23]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[24]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[25]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[26]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[27]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[28]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[29]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[30]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[31]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[32]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[33]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[34]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[35]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[36]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[37]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[38]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[39]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[40]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[41]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[42]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[43]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[4]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[5]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[6]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[7]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[8]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARADDR1[9]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARBURST0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARBURST0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARBURST1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARBURST1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARCACHE0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARCACHE0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARCACHE0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARCACHE0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARCACHE1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARCACHE1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARCACHE1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARCACHE1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARID0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARID0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARID0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARID0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARID1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARID1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARID1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARID1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARLEN0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARLEN0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARLEN0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARLEN0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARLEN0[4]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARLEN0[5]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARLEN0[6]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARLEN0[7]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARLEN1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARLEN1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARLEN1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARLEN1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARLEN1[4]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARLEN1[5]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARLEN1[6]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARLEN1[7]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARPROT0) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARPROT1) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARQOS0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARQOS0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARQOS0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARQOS0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARQOS1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARQOS1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARQOS1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARQOS1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARSIZE0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARSIZE0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARSIZE0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARSIZE1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARSIZE1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARSIZE1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARVALID0) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECARVALID1) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[10]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[11]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[12]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[13]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[14]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[15]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[16]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[17]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[18]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[19]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[20]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[21]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[22]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[23]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[24]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[25]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[26]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[27]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[28]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[29]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[30]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[31]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[32]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[33]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[34]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[35]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[36]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[37]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[38]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[39]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[40]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[41]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[42]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[43]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[4]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[5]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[6]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[7]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[8]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR0[9]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[10]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[11]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[12]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[13]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[14]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[15]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[16]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[17]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[18]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[19]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[20]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[21]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[22]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[23]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[24]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[25]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[26]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[27]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[28]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[29]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[30]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[31]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[32]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[33]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[34]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[35]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[36]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[37]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[38]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[39]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[40]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[41]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[42]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[43]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[4]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[5]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[6]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[7]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[8]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWADDR1[9]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWBURST0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWBURST0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWBURST1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWBURST1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWCACHE0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWCACHE0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWCACHE0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWCACHE0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWCACHE1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWCACHE1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWCACHE1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWCACHE1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWID0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWID0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWID0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWID0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWID1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWID1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWID1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWID1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWLEN0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWLEN0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWLEN0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWLEN0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWLEN0[4]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWLEN0[5]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWLEN0[6]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWLEN0[7]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWLEN1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWLEN1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWLEN1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWLEN1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWLEN1[4]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWLEN1[5]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWLEN1[6]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWLEN1[7]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWPROT0) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWPROT1) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWQOS0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWQOS0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWQOS0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWQOS0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWQOS1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWQOS1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWQOS1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWQOS1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWSIZE0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWSIZE0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWSIZE0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWSIZE1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWSIZE1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWSIZE1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWVALID0) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECAWVALID1) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECBREADY0) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECBREADY1) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECRREADY0) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECRREADY1) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[100]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[101]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[102]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[103]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[104]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[105]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[106]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[107]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[108]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[109]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[10]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[110]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[111]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[112]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[113]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[114]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[115]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[116]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[117]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[118]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[119]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[11]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[120]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[121]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[122]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[123]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[124]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[125]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[126]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[127]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[12]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[13]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[14]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[15]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[16]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[17]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[18]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[19]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[20]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[21]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[22]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[23]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[24]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[25]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[26]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[27]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[28]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[29]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[30]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[31]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[32]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[33]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[34]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[35]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[36]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[37]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[38]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[39]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[40]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[41]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[42]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[43]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[44]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[45]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[46]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[47]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[48]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[49]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[4]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[50]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[51]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[52]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[53]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[54]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[55]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[56]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[57]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[58]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[59]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[5]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[60]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[61]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[62]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[63]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[64]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[65]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[66]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[67]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[68]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[69]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[6]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[70]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[71]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[72]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[73]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[74]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[75]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[76]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[77]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[78]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[79]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[7]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[80]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[81]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[82]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[83]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[84]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[85]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[86]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[87]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[88]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[89]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[8]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[90]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[91]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[92]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[93]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[94]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[95]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[96]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[97]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[98]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[99]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA0[9]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[100]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[101]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[102]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[103]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[104]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[105]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[106]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[107]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[108]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[109]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[10]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[110]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[111]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[112]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[113]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[114]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[115]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[116]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[117]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[118]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[119]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[11]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[120]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[121]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[122]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[123]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[124]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[125]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[126]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[127]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[12]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[13]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[14]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[15]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[16]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[17]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[18]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[19]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[20]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[21]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[22]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[23]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[24]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[25]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[26]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[27]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[28]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[29]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[30]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[31]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[32]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[33]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[34]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[35]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[36]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[37]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[38]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[39]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[40]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[41]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[42]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[43]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[44]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[45]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[46]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[47]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[48]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[49]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[4]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[50]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[51]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[52]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[53]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[54]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[55]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[56]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[57]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[58]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[59]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[5]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[60]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[61]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[62]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[63]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[64]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[65]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[66]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[67]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[68]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[69]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[6]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[70]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[71]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[72]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[73]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[74]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[75]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[76]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[77]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[78]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[79]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[7]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[80]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[81]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[82]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[83]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[84]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[85]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[86]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[87]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[88]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[89]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[8]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[90]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[91]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[92]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[93]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[94]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[95]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[96]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[97]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[98]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[99]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWDATA1[9]) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWLAST0) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWLAST1) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWVALID0) = (100:100:100, 100:100:100);
(PLVCUAXIDECCLK => VCUPLDECWVALID1) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[10]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[11]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[12]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[13]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[14]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[15]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[16]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[17]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[18]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[19]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[20]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[21]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[22]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[23]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[24]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[25]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[26]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[27]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[28]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[29]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[30]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[31]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[32]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[33]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[34]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[35]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[36]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[37]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[38]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[39]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[40]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[41]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[42]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[43]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[4]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[5]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[6]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[7]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[8]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR0[9]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[10]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[11]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[12]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[13]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[14]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[15]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[16]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[17]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[18]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[19]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[20]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[21]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[22]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[23]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[24]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[25]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[26]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[27]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[28]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[29]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[30]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[31]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[32]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[33]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[34]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[35]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[36]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[37]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[38]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[39]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[40]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[41]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[42]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[43]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[4]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[5]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[6]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[7]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[8]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARADDR1[9]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARBURST0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARBURST0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARBURST1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARBURST1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARCACHE0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARCACHE0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARCACHE0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARCACHE0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARCACHE1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARCACHE1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARCACHE1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARCACHE1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARID0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARID0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARID0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARID0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARID1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARID1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARID1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARID1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARLEN0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARLEN0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARLEN0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARLEN0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARLEN0[4]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARLEN0[5]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARLEN0[6]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARLEN0[7]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARLEN1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARLEN1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARLEN1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARLEN1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARLEN1[4]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARLEN1[5]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARLEN1[6]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARLEN1[7]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARPROT0) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARPROT1) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARQOS0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARQOS0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARQOS0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARQOS0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARQOS1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARQOS1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARQOS1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARQOS1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARSIZE0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARSIZE0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARSIZE0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARSIZE1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARSIZE1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARSIZE1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARVALID0) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCARVALID1) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[10]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[11]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[12]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[13]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[14]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[15]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[16]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[17]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[18]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[19]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[20]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[21]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[22]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[23]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[24]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[25]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[26]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[27]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[28]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[29]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[30]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[31]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[32]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[33]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[34]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[35]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[36]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[37]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[38]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[39]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[40]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[41]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[42]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[43]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[4]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[5]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[6]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[7]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[8]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR0[9]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[10]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[11]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[12]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[13]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[14]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[15]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[16]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[17]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[18]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[19]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[20]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[21]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[22]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[23]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[24]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[25]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[26]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[27]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[28]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[29]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[30]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[31]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[32]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[33]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[34]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[35]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[36]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[37]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[38]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[39]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[40]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[41]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[42]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[43]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[4]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[5]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[6]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[7]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[8]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWADDR1[9]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWBURST0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWBURST0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWBURST1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWBURST1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWCACHE0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWCACHE0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWCACHE0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWCACHE0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWCACHE1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWCACHE1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWCACHE1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWCACHE1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWID0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWID0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWID0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWID0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWID1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWID1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWID1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWID1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWLEN0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWLEN0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWLEN0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWLEN0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWLEN0[4]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWLEN0[5]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWLEN0[6]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWLEN0[7]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWLEN1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWLEN1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWLEN1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWLEN1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWLEN1[4]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWLEN1[5]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWLEN1[6]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWLEN1[7]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWPROT0) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWPROT1) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWQOS0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWQOS0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWQOS0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWQOS0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWQOS1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWQOS1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWQOS1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWQOS1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWSIZE0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWSIZE0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWSIZE0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWSIZE1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWSIZE1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWSIZE1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWVALID0) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCAWVALID1) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCBREADY0) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCBREADY1) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCRREADY0) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCRREADY1) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[100]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[101]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[102]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[103]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[104]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[105]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[106]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[107]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[108]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[109]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[10]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[110]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[111]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[112]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[113]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[114]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[115]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[116]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[117]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[118]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[119]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[11]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[120]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[121]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[122]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[123]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[124]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[125]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[126]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[127]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[12]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[13]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[14]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[15]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[16]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[17]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[18]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[19]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[20]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[21]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[22]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[23]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[24]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[25]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[26]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[27]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[28]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[29]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[30]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[31]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[32]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[33]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[34]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[35]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[36]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[37]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[38]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[39]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[40]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[41]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[42]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[43]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[44]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[45]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[46]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[47]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[48]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[49]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[4]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[50]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[51]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[52]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[53]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[54]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[55]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[56]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[57]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[58]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[59]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[5]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[60]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[61]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[62]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[63]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[64]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[65]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[66]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[67]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[68]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[69]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[6]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[70]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[71]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[72]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[73]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[74]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[75]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[76]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[77]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[78]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[79]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[7]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[80]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[81]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[82]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[83]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[84]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[85]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[86]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[87]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[88]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[89]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[8]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[90]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[91]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[92]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[93]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[94]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[95]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[96]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[97]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[98]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[99]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA0[9]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[0]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[100]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[101]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[102]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[103]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[104]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[105]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[106]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[107]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[108]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[109]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[10]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[110]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[111]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[112]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[113]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[114]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[115]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[116]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[117]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[118]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[119]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[11]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[120]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[121]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[122]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[123]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[124]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[125]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[126]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[127]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[12]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[13]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[14]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[15]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[16]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[17]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[18]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[19]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[1]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[20]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[21]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[22]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[23]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[24]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[25]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[26]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[27]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[28]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[29]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[2]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[30]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[31]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[32]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[33]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[34]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[35]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[36]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[37]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[38]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[39]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[3]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[40]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[41]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[42]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[43]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[44]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[45]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[46]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[47]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[48]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[49]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[4]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[50]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[51]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[52]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[53]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[54]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[55]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[56]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[57]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[58]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[59]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[5]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[60]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[61]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[62]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[63]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[64]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[65]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[66]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[67]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[68]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[69]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[6]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[70]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[71]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[72]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[73]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[74]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[75]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[76]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[77]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[78]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[79]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[7]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[80]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[81]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[82]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[83]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[84]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[85]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[86]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[87]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[88]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[89]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[8]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[90]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[91]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[92]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[93]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[94]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[95]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[96]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[97]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[98]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[99]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWDATA1[9]) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWLAST0) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWLAST1) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWVALID0) = (100:100:100, 100:100:100);
(PLVCUAXIENCCLK => VCUPLENCWVALID1) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLARREADYAXILITEAPB) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLAWREADYAXILITEAPB) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLBRESPAXILITEAPB[0]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLBRESPAXILITEAPB[1]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLBVALIDAXILITEAPB) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLPINTREQ) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[0]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[10]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[11]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[12]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[13]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[14]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[15]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[16]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[17]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[18]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[19]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[1]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[20]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[21]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[22]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[23]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[24]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[25]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[26]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[27]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[28]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[29]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[2]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[30]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[31]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[3]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[4]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[5]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[6]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[7]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[8]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRDATAAXILITEAPB[9]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRRESPAXILITEAPB[0]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRRESPAXILITEAPB[1]) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLRVALIDAXILITEAPB) = (100:100:100, 100:100:100);
(PLVCUAXILITECLK => VCUPLWREADYAXILITEAPB) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[10]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[11]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[12]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[13]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[14]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[15]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[16]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[17]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[18]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[19]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[20]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[21]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[22]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[23]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[24]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[25]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[26]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[27]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[28]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[29]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[2]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[30]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[31]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[32]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[33]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[34]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[35]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[36]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[37]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[38]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[39]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[3]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[40]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[41]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[42]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[43]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[4]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[5]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[6]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[7]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[8]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARADDR[9]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARBURST[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARBURST[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARCACHE[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARCACHE[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARCACHE[2]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARCACHE[3]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARID[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARID[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARID[2]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLEN[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLEN[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLEN[2]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLEN[3]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLEN[4]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLEN[5]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLEN[6]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLEN[7]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARLOCK) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARPROT[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARPROT[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARPROT[2]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARQOS[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARQOS[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARQOS[2]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARQOS[3]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARSIZE[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARSIZE[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARSIZE[2]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCARVALID) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[10]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[11]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[12]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[13]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[14]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[15]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[16]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[17]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[18]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[19]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[20]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[21]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[22]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[23]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[24]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[25]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[26]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[27]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[28]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[29]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[2]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[30]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[31]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[32]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[33]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[34]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[35]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[36]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[37]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[38]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[39]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[3]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[40]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[41]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[42]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[43]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[4]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[5]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[6]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[7]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[8]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWADDR[9]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWBURST[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWBURST[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWCACHE[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWCACHE[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWCACHE[2]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWCACHE[3]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWID[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWID[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWID[2]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLEN[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLEN[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLEN[2]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLEN[3]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLEN[4]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLEN[5]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLEN[6]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLEN[7]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWLOCK) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWPROT[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWPROT[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWPROT[2]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWQOS[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWQOS[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWQOS[2]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWQOS[3]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWSIZE[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWSIZE[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWSIZE[2]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCAWVALID) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCBREADY) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCRREADY) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[10]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[11]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[12]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[13]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[14]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[15]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[16]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[17]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[18]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[19]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[20]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[21]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[22]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[23]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[24]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[25]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[26]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[27]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[28]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[29]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[2]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[30]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[31]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[3]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[4]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[5]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[6]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[7]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[8]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWDATA[9]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWLAST) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWSTRB[0]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWSTRB[1]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWSTRB[2]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWSTRB[3]) = (100:100:100, 100:100:100);
(PLVCUAXIMCUCLK => VCUPLMCUMAXIICDCWVALID) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CADDR[0]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CADDR[10]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CADDR[11]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CADDR[12]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CADDR[13]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CADDR[14]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CADDR[15]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CADDR[16]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CADDR[1]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CADDR[2]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CADDR[3]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CADDR[4]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CADDR[5]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CADDR[6]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CADDR[7]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CADDR[8]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CADDR[9]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CRVALID) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[0]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[100]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[101]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[102]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[103]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[104]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[105]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[106]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[107]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[108]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[109]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[10]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[110]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[111]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[112]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[113]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[114]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[115]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[116]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[117]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[118]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[119]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[11]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[120]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[121]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[122]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[123]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[124]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[125]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[126]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[127]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[128]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[129]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[12]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[130]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[131]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[132]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[133]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[134]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[135]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[136]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[137]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[138]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[139]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[13]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[140]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[141]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[142]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[143]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[144]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[145]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[146]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[147]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[148]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[149]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[14]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[150]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[151]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[152]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[153]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[154]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[155]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[156]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[157]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[158]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[159]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[15]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[160]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[161]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[162]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[163]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[164]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[165]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[166]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[167]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[168]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[169]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[16]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[170]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[171]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[172]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[173]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[174]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[175]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[176]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[177]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[178]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[179]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[17]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[180]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[181]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[182]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[183]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[184]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[185]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[186]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[187]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[188]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[189]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[18]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[190]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[191]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[192]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[193]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[194]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[195]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[196]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[197]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[198]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[199]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[19]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[1]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[200]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[201]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[202]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[203]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[204]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[205]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[206]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[207]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[208]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[209]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[20]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[210]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[211]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[212]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[213]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[214]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[215]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[216]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[217]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[218]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[219]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[21]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[220]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[221]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[222]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[223]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[224]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[225]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[226]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[227]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[228]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[229]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[22]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[230]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[231]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[232]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[233]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[234]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[235]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[236]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[237]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[238]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[239]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[23]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[240]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[241]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[242]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[243]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[244]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[245]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[246]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[247]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[248]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[249]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[24]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[250]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[251]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[252]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[253]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[254]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[255]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[256]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[257]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[258]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[259]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[25]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[260]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[261]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[262]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[263]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[264]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[265]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[266]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[267]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[268]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[269]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[26]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[270]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[271]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[272]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[273]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[274]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[275]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[276]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[277]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[278]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[279]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[27]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[280]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[281]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[282]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[283]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[284]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[285]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[286]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[287]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[288]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[289]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[28]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[290]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[291]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[292]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[293]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[294]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[295]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[296]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[297]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[298]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[299]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[29]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[2]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[300]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[301]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[302]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[303]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[304]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[305]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[306]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[307]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[308]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[309]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[30]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[310]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[311]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[312]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[313]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[314]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[315]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[316]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[317]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[318]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[319]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[31]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[32]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[33]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[34]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[35]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[36]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[37]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[38]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[39]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[3]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[40]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[41]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[42]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[43]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[44]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[45]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[46]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[47]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[48]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[49]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[4]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[50]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[51]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[52]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[53]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[54]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[55]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[56]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[57]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[58]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[59]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[5]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[60]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[61]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[62]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[63]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[64]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[65]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[66]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[67]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[68]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[69]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[6]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[70]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[71]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[72]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[73]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[74]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[75]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[76]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[77]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[78]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[79]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[7]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[80]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[81]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[82]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[83]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[84]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[85]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[86]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[87]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[88]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[89]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[8]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[90]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[91]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[92]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[93]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[94]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[95]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[96]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[97]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[98]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[99]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWDATA[9]) = (100:100:100, 100:100:100);
(PLVCUENCL2CCLK => VCUPLENCALL2CWVALID) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge PLVCUAXIDECCLK, 0:0:0, notifier);
$period (negedge PLVCUAXIENCCLK, 0:0:0, notifier);
$period (negedge PLVCUAXILITECLK, 0:0:0, notifier);
$period (negedge PLVCUAXIMCUCLK, 0:0:0, notifier);
$period (negedge PLVCUCORECLK, 0:0:0, notifier);
$period (negedge PLVCUENCL2CCLK, 0:0:0, notifier);
$period (negedge PLVCUMCUCLK, 0:0:0, notifier);
$period (negedge PLVCUPLLREFCLKPL, 0:0:0, notifier);
$period (negedge VCUPLCORESTATUSCLKPLL, 0:0:0, notifier);
$period (negedge VCUPLMCUSTATUSCLKPLL, 0:0:0, notifier);
$period (posedge PLVCUAXIDECCLK, 0:0:0, notifier);
$period (posedge PLVCUAXIENCCLK, 0:0:0, notifier);
$period (posedge PLVCUAXILITECLK, 0:0:0, notifier);
$period (posedge PLVCUAXIMCUCLK, 0:0:0, notifier);
$period (posedge PLVCUCORECLK, 0:0:0, notifier);
$period (posedge PLVCUENCL2CCLK, 0:0:0, notifier);
$period (posedge PLVCUMCUCLK, 0:0:0, notifier);
$period (posedge PLVCUPLLREFCLKPL, 0:0:0, notifier);
$period (posedge VCUPLCORESTATUSCLKPLL, 0:0:0, notifier);
$period (posedge VCUPLMCUSTATUSCLKPLL, 0:0:0, notifier);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECARREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECARREADY0_delay);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECARREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECARREADY1_delay);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECAWREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECAWREADY0_delay);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECAWREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECAWREADY1_delay);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBID0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID0_delay[0]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBID0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID0_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBID0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID0_delay[2]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBID0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID0_delay[3]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBID1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID1_delay[0]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBID1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID1_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBID1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID1_delay[2]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBID1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID1_delay[3]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBRESP0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBRESP0_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBRESP1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBRESP1_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBVALID0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBVALID0_delay);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECBVALID1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBVALID1_delay);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[0]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[100], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[100]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[101], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[101]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[102], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[102]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[103], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[103]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[104], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[104]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[105], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[105]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[106], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[106]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[107], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[107]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[108], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[108]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[109], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[109]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[10]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[110], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[110]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[111], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[111]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[112], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[112]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[113], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[113]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[114], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[114]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[115], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[115]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[116], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[116]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[117], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[117]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[118], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[118]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[119], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[119]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[11]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[120], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[120]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[121], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[121]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[122], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[122]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[123], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[123]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[124], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[124]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[125], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[125]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[126], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[126]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[127], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[127]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[12]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[13]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[14]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[15]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[16]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[17]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[18]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[19]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[20]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[21]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[22]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[23]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[24]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[25]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[26]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[27]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[28]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[29]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[2]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[30]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[31]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[32], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[32]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[33], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[33]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[34], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[34]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[35], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[35]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[36], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[36]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[37], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[37]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[38], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[38]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[39], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[39]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[3]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[40], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[40]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[41], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[41]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[42], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[42]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[43], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[43]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[44], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[44]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[45], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[45]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[46], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[46]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[47], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[47]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[48], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[48]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[49], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[49]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[4]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[50], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[50]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[51], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[51]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[52], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[52]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[53], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[53]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[54], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[54]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[55], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[55]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[56], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[56]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[57], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[57]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[58], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[58]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[59], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[59]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[5]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[60], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[60]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[61], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[61]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[62], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[62]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[63], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[63]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[64], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[64]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[65], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[65]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[66], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[66]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[67], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[67]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[68], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[68]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[69], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[69]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[6]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[70], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[70]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[71], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[71]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[72], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[72]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[73], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[73]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[74], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[74]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[75], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[75]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[76], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[76]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[77], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[77]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[78], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[78]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[79], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[79]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[7]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[80], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[80]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[81], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[81]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[82], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[82]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[83], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[83]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[84], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[84]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[85], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[85]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[86], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[86]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[87], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[87]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[88], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[88]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[89], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[89]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[8]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[90], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[90]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[91], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[91]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[92], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[92]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[93], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[93]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[94], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[94]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[95], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[95]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[96], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[96]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[97], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[97]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[98], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[98]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[99], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[99]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA0[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[9]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[0]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[100], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[100]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[101], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[101]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[102], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[102]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[103], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[103]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[104], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[104]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[105], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[105]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[106], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[106]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[107], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[107]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[108], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[108]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[109], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[109]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[10]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[110], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[110]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[111], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[111]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[112], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[112]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[113], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[113]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[114], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[114]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[115], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[115]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[116], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[116]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[117], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[117]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[118], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[118]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[119], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[119]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[11]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[120], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[120]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[121], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[121]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[122], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[122]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[123], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[123]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[124], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[124]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[125], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[125]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[126], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[126]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[127], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[127]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[12]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[13]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[14]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[15]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[16]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[17]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[18]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[19]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[20]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[21]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[22]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[23]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[24]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[25]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[26]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[27]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[28]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[29]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[2]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[30]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[31]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[32], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[32]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[33], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[33]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[34], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[34]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[35], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[35]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[36], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[36]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[37], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[37]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[38], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[38]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[39], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[39]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[3]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[40], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[40]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[41], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[41]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[42], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[42]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[43], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[43]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[44], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[44]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[45], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[45]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[46], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[46]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[47], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[47]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[48], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[48]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[49], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[49]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[4]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[50], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[50]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[51], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[51]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[52], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[52]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[53], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[53]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[54], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[54]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[55], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[55]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[56], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[56]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[57], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[57]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[58], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[58]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[59], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[59]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[5]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[60], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[60]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[61], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[61]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[62], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[62]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[63], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[63]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[64], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[64]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[65], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[65]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[66], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[66]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[67], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[67]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[68], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[68]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[69], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[69]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[6]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[70], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[70]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[71], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[71]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[72], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[72]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[73], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[73]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[74], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[74]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[75], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[75]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[76], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[76]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[77], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[77]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[78], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[78]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[79], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[79]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[7]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[80], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[80]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[81], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[81]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[82], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[82]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[83], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[83]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[84], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[84]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[85], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[85]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[86], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[86]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[87], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[87]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[88], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[88]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[89], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[89]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[8]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[90], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[90]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[91], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[91]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[92], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[92]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[93], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[93]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[94], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[94]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[95], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[95]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[96], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[96]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[97], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[97]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[98], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[98]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[99], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[99]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRDATA1[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[9]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRID0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID0_delay[0]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRID0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID0_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRID0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID0_delay[2]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRID0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID0_delay[3]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRID1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID1_delay[0]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRID1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID1_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRID1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID1_delay[2]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRID1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID1_delay[3]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRLAST0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRLAST0_delay);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRLAST1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRLAST1_delay);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRRESP0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRRESP0_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRRESP1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRRESP1_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRVALID0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRVALID0_delay);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECRVALID1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRVALID1_delay);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECWREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECWREADY0_delay);
$setuphold (posedge PLVCUAXIDECCLK, negedge PLVCUDECWREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECWREADY1_delay);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECARREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECARREADY0_delay);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECARREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECARREADY1_delay);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECAWREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECAWREADY0_delay);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECAWREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECAWREADY1_delay);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBID0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID0_delay[0]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBID0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID0_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBID0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID0_delay[2]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBID0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID0_delay[3]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBID1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID1_delay[0]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBID1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID1_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBID1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID1_delay[2]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBID1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBID1_delay[3]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBRESP0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBRESP0_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBRESP1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBRESP1_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBVALID0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBVALID0_delay);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECBVALID1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECBVALID1_delay);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[0]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[100], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[100]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[101], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[101]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[102], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[102]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[103], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[103]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[104], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[104]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[105], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[105]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[106], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[106]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[107], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[107]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[108], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[108]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[109], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[109]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[10]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[110], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[110]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[111], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[111]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[112], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[112]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[113], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[113]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[114], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[114]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[115], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[115]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[116], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[116]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[117], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[117]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[118], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[118]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[119], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[119]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[11]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[120], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[120]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[121], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[121]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[122], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[122]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[123], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[123]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[124], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[124]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[125], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[125]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[126], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[126]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[127], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[127]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[12]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[13]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[14]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[15]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[16]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[17]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[18]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[19]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[20]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[21]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[22]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[23]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[24]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[25]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[26]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[27]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[28]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[29]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[2]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[30]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[31]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[32], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[32]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[33], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[33]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[34], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[34]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[35], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[35]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[36], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[36]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[37], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[37]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[38], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[38]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[39], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[39]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[3]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[40], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[40]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[41], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[41]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[42], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[42]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[43], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[43]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[44], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[44]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[45], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[45]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[46], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[46]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[47], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[47]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[48], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[48]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[49], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[49]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[4]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[50], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[50]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[51], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[51]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[52], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[52]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[53], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[53]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[54], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[54]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[55], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[55]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[56], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[56]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[57], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[57]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[58], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[58]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[59], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[59]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[5]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[60], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[60]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[61], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[61]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[62], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[62]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[63], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[63]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[64], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[64]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[65], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[65]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[66], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[66]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[67], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[67]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[68], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[68]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[69], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[69]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[6]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[70], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[70]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[71], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[71]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[72], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[72]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[73], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[73]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[74], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[74]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[75], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[75]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[76], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[76]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[77], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[77]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[78], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[78]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[79], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[79]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[7]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[80], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[80]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[81], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[81]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[82], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[82]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[83], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[83]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[84], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[84]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[85], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[85]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[86], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[86]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[87], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[87]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[88], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[88]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[89], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[89]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[8]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[90], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[90]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[91], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[91]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[92], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[92]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[93], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[93]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[94], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[94]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[95], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[95]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[96], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[96]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[97], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[97]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[98], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[98]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[99], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[99]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA0[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA0_delay[9]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[0]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[100], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[100]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[101], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[101]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[102], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[102]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[103], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[103]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[104], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[104]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[105], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[105]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[106], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[106]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[107], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[107]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[108], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[108]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[109], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[109]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[10]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[110], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[110]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[111], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[111]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[112], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[112]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[113], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[113]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[114], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[114]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[115], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[115]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[116], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[116]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[117], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[117]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[118], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[118]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[119], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[119]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[11]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[120], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[120]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[121], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[121]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[122], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[122]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[123], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[123]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[124], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[124]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[125], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[125]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[126], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[126]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[127], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[127]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[12]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[13]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[14]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[15]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[16]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[17]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[18]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[19]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[20]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[21]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[22]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[23]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[24]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[25]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[26]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[27]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[28]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[29]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[2]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[30]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[31]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[32], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[32]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[33], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[33]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[34], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[34]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[35], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[35]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[36], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[36]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[37], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[37]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[38], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[38]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[39], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[39]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[3]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[40], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[40]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[41], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[41]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[42], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[42]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[43], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[43]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[44], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[44]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[45], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[45]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[46], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[46]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[47], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[47]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[48], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[48]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[49], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[49]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[4]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[50], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[50]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[51], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[51]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[52], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[52]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[53], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[53]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[54], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[54]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[55], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[55]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[56], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[56]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[57], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[57]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[58], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[58]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[59], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[59]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[5]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[60], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[60]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[61], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[61]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[62], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[62]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[63], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[63]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[64], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[64]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[65], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[65]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[66], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[66]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[67], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[67]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[68], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[68]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[69], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[69]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[6]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[70], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[70]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[71], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[71]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[72], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[72]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[73], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[73]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[74], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[74]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[75], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[75]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[76], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[76]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[77], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[77]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[78], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[78]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[79], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[79]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[7]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[80], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[80]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[81], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[81]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[82], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[82]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[83], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[83]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[84], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[84]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[85], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[85]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[86], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[86]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[87], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[87]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[88], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[88]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[89], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[89]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[8]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[90], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[90]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[91], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[91]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[92], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[92]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[93], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[93]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[94], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[94]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[95], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[95]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[96], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[96]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[97], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[97]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[98], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[98]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[99], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[99]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRDATA1[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRDATA1_delay[9]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRID0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID0_delay[0]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRID0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID0_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRID0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID0_delay[2]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRID0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID0_delay[3]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRID1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID1_delay[0]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRID1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID1_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRID1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID1_delay[2]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRID1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRID1_delay[3]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRLAST0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRLAST0_delay);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRLAST1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRLAST1_delay);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRRESP0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRRESP0_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRRESP1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRRESP1_delay[1]);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRVALID0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRVALID0_delay);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECRVALID1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECRVALID1_delay);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECWREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECWREADY0_delay);
$setuphold (posedge PLVCUAXIDECCLK, posedge PLVCUDECWREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIDECCLK_delay, PLVCUDECWREADY1_delay);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCARREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCARREADY0_delay);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCARREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCARREADY1_delay);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCAWREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCAWREADY0_delay);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCAWREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCAWREADY1_delay);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBID0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID0_delay[0]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBID0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID0_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBID0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID0_delay[2]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBID0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID0_delay[3]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBID1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID1_delay[0]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBID1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID1_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBID1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID1_delay[2]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBID1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID1_delay[3]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBRESP0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBRESP0_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBRESP1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBRESP1_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBVALID0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBVALID0_delay);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCBVALID1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBVALID1_delay);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[0]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[100], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[100]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[101], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[101]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[102], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[102]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[103], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[103]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[104], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[104]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[105], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[105]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[106], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[106]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[107], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[107]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[108], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[108]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[109], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[109]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[10]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[110], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[110]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[111], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[111]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[112], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[112]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[113], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[113]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[114], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[114]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[115], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[115]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[116], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[116]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[117], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[117]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[118], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[118]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[119], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[119]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[11]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[120], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[120]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[121], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[121]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[122], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[122]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[123], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[123]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[124], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[124]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[125], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[125]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[126], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[126]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[127], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[127]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[12]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[13]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[14]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[15]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[16]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[17]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[18]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[19]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[20]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[21]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[22]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[23]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[24]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[25]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[26]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[27]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[28]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[29]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[2]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[30]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[31]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[32], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[32]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[33], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[33]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[34], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[34]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[35], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[35]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[36], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[36]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[37], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[37]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[38], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[38]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[39], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[39]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[3]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[40], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[40]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[41], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[41]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[42], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[42]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[43], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[43]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[44], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[44]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[45], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[45]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[46], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[46]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[47], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[47]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[48], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[48]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[49], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[49]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[4]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[50], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[50]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[51], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[51]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[52], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[52]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[53], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[53]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[54], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[54]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[55], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[55]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[56], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[56]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[57], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[57]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[58], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[58]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[59], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[59]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[5]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[60], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[60]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[61], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[61]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[62], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[62]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[63], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[63]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[64], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[64]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[65], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[65]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[66], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[66]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[67], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[67]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[68], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[68]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[69], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[69]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[6]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[70], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[70]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[71], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[71]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[72], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[72]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[73], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[73]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[74], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[74]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[75], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[75]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[76], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[76]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[77], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[77]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[78], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[78]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[79], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[79]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[7]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[80], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[80]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[81], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[81]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[82], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[82]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[83], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[83]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[84], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[84]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[85], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[85]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[86], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[86]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[87], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[87]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[88], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[88]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[89], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[89]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[8]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[90], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[90]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[91], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[91]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[92], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[92]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[93], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[93]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[94], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[94]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[95], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[95]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[96], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[96]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[97], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[97]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[98], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[98]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[99], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[99]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA0[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[9]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[0]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[100], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[100]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[101], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[101]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[102], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[102]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[103], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[103]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[104], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[104]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[105], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[105]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[106], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[106]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[107], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[107]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[108], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[108]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[109], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[109]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[10]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[110], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[110]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[111], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[111]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[112], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[112]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[113], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[113]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[114], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[114]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[115], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[115]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[116], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[116]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[117], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[117]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[118], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[118]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[119], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[119]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[11]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[120], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[120]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[121], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[121]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[122], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[122]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[123], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[123]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[124], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[124]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[125], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[125]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[126], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[126]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[127], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[127]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[12]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[13]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[14]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[15]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[16]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[17]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[18]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[19]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[20]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[21]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[22]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[23]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[24]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[25]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[26]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[27]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[28]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[29]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[2]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[30]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[31]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[32], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[32]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[33], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[33]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[34], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[34]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[35], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[35]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[36], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[36]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[37], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[37]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[38], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[38]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[39], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[39]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[3]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[40], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[40]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[41], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[41]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[42], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[42]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[43], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[43]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[44], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[44]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[45], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[45]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[46], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[46]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[47], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[47]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[48], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[48]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[49], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[49]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[4]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[50], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[50]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[51], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[51]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[52], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[52]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[53], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[53]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[54], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[54]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[55], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[55]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[56], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[56]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[57], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[57]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[58], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[58]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[59], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[59]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[5]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[60], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[60]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[61], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[61]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[62], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[62]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[63], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[63]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[64], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[64]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[65], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[65]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[66], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[66]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[67], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[67]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[68], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[68]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[69], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[69]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[6]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[70], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[70]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[71], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[71]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[72], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[72]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[73], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[73]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[74], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[74]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[75], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[75]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[76], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[76]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[77], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[77]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[78], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[78]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[79], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[79]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[7]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[80], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[80]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[81], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[81]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[82], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[82]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[83], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[83]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[84], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[84]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[85], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[85]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[86], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[86]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[87], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[87]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[88], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[88]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[89], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[89]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[8]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[90], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[90]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[91], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[91]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[92], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[92]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[93], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[93]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[94], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[94]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[95], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[95]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[96], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[96]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[97], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[97]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[98], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[98]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[99], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[99]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRDATA1[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[9]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRID0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID0_delay[0]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRID0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID0_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRID0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID0_delay[2]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRID0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID0_delay[3]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRID1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID1_delay[0]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRID1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID1_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRID1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID1_delay[2]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRID1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID1_delay[3]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRLAST0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRLAST0_delay);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRLAST1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRLAST1_delay);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRRESP0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRRESP0_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRRESP1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRRESP1_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRVALID0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRVALID0_delay);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCRVALID1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRVALID1_delay);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCWREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCWREADY0_delay);
$setuphold (posedge PLVCUAXIENCCLK, negedge PLVCUENCWREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCWREADY1_delay);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCARREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCARREADY0_delay);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCARREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCARREADY1_delay);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCAWREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCAWREADY0_delay);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCAWREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCAWREADY1_delay);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBID0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID0_delay[0]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBID0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID0_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBID0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID0_delay[2]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBID0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID0_delay[3]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBID1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID1_delay[0]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBID1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID1_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBID1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID1_delay[2]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBID1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBID1_delay[3]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBRESP0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBRESP0_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBRESP1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBRESP1_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBVALID0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBVALID0_delay);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCBVALID1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCBVALID1_delay);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[0]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[100], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[100]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[101], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[101]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[102], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[102]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[103], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[103]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[104], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[104]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[105], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[105]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[106], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[106]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[107], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[107]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[108], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[108]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[109], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[109]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[10]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[110], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[110]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[111], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[111]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[112], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[112]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[113], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[113]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[114], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[114]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[115], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[115]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[116], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[116]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[117], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[117]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[118], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[118]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[119], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[119]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[11]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[120], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[120]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[121], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[121]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[122], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[122]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[123], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[123]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[124], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[124]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[125], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[125]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[126], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[126]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[127], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[127]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[12]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[13]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[14]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[15]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[16]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[17]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[18]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[19]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[20]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[21]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[22]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[23]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[24]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[25]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[26]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[27]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[28]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[29]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[2]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[30]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[31]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[32], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[32]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[33], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[33]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[34], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[34]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[35], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[35]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[36], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[36]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[37], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[37]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[38], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[38]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[39], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[39]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[3]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[40], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[40]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[41], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[41]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[42], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[42]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[43], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[43]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[44], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[44]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[45], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[45]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[46], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[46]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[47], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[47]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[48], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[48]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[49], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[49]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[4]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[50], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[50]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[51], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[51]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[52], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[52]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[53], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[53]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[54], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[54]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[55], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[55]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[56], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[56]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[57], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[57]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[58], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[58]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[59], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[59]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[5]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[60], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[60]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[61], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[61]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[62], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[62]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[63], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[63]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[64], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[64]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[65], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[65]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[66], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[66]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[67], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[67]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[68], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[68]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[69], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[69]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[6]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[70], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[70]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[71], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[71]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[72], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[72]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[73], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[73]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[74], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[74]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[75], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[75]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[76], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[76]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[77], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[77]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[78], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[78]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[79], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[79]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[7]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[80], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[80]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[81], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[81]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[82], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[82]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[83], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[83]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[84], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[84]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[85], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[85]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[86], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[86]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[87], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[87]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[88], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[88]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[89], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[89]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[8]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[90], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[90]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[91], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[91]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[92], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[92]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[93], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[93]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[94], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[94]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[95], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[95]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[96], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[96]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[97], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[97]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[98], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[98]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[99], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[99]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA0[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA0_delay[9]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[0]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[100], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[100]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[101], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[101]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[102], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[102]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[103], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[103]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[104], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[104]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[105], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[105]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[106], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[106]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[107], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[107]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[108], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[108]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[109], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[109]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[10]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[110], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[110]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[111], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[111]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[112], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[112]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[113], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[113]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[114], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[114]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[115], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[115]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[116], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[116]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[117], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[117]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[118], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[118]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[119], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[119]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[11]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[120], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[120]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[121], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[121]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[122], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[122]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[123], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[123]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[124], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[124]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[125], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[125]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[126], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[126]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[127], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[127]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[12]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[13]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[14]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[15]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[16]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[17]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[18]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[19]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[20]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[21]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[22]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[23]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[24]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[25]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[26]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[27]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[28]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[29]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[2]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[30]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[31]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[32], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[32]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[33], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[33]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[34], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[34]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[35], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[35]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[36], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[36]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[37], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[37]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[38], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[38]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[39], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[39]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[3]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[40], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[40]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[41], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[41]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[42], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[42]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[43], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[43]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[44], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[44]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[45], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[45]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[46], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[46]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[47], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[47]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[48], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[48]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[49], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[49]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[4]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[50], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[50]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[51], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[51]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[52], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[52]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[53], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[53]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[54], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[54]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[55], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[55]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[56], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[56]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[57], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[57]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[58], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[58]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[59], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[59]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[5]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[60], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[60]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[61], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[61]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[62], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[62]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[63], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[63]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[64], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[64]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[65], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[65]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[66], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[66]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[67], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[67]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[68], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[68]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[69], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[69]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[6]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[70], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[70]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[71], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[71]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[72], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[72]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[73], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[73]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[74], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[74]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[75], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[75]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[76], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[76]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[77], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[77]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[78], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[78]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[79], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[79]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[7]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[80], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[80]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[81], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[81]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[82], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[82]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[83], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[83]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[84], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[84]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[85], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[85]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[86], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[86]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[87], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[87]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[88], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[88]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[89], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[89]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[8]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[90], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[90]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[91], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[91]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[92], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[92]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[93], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[93]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[94], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[94]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[95], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[95]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[96], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[96]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[97], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[97]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[98], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[98]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[99], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[99]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRDATA1[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRDATA1_delay[9]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRID0[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID0_delay[0]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRID0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID0_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRID0[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID0_delay[2]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRID0[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID0_delay[3]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRID1[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID1_delay[0]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRID1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID1_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRID1[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID1_delay[2]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRID1[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRID1_delay[3]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRLAST0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRLAST0_delay);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRLAST1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRLAST1_delay);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRRESP0[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRRESP0_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRRESP1[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRRESP1_delay[1]);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRVALID0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRVALID0_delay);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCRVALID1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCRVALID1_delay);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCWREADY0, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCWREADY0_delay);
$setuphold (posedge PLVCUAXIENCCLK, posedge PLVCUENCWREADY1, 0:0:0, 0:0:0, notifier, , , PLVCUAXIENCCLK_delay, PLVCUENCWREADY1_delay);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[0]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[10]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[11]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[12]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[13]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[14]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[15]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[16]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[17]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[18]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[19]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[1]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[2]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[3]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[4]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[5]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[6]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[7]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[8]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARADDRAXILITEAPB[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[9]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARPROTAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARPROTAXILITEAPB_delay[0]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARPROTAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARPROTAXILITEAPB_delay[1]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARPROTAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARPROTAXILITEAPB_delay[2]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUARVALIDAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARVALIDAXILITEAPB_delay);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[0]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[10]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[11]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[12]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[13]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[14]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[15]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[16]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[17]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[18]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[19]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[1]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[2]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[3]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[4]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[5]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[6]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[7]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[8]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWADDRAXILITEAPB[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[9]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWPROTAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWPROTAXILITEAPB_delay[0]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWPROTAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWPROTAXILITEAPB_delay[1]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWPROTAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWPROTAXILITEAPB_delay[2]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUAWVALIDAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWVALIDAXILITEAPB_delay);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUBREADYAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUBREADYAXILITEAPB_delay);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCURREADYAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCURREADYAXILITEAPB_delay);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[0]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[10]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[11]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[12]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[13]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[14]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[15]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[16]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[17]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[18]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[19]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[1]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[20]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[21]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[22]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[23]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[24]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[25]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[26]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[27]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[28]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[29]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[2]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[30]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[31]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[3]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[4]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[5]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[6]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[7]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[8]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWDATAAXILITEAPB[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[9]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWSTRBAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWSTRBAXILITEAPB_delay[0]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWSTRBAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWSTRBAXILITEAPB_delay[1]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWSTRBAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWSTRBAXILITEAPB_delay[2]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWSTRBAXILITEAPB[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWSTRBAXILITEAPB_delay[3]);
$setuphold (posedge PLVCUAXILITECLK, negedge PLVCUWVALIDAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWVALIDAXILITEAPB_delay);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[0]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[10]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[11]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[12]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[13]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[14]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[15]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[16]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[17]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[18]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[19]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[1]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[2]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[3]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[4]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[5]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[6]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[7]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[8]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARADDRAXILITEAPB[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARADDRAXILITEAPB_delay[9]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARPROTAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARPROTAXILITEAPB_delay[0]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARPROTAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARPROTAXILITEAPB_delay[1]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARPROTAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARPROTAXILITEAPB_delay[2]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUARVALIDAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUARVALIDAXILITEAPB_delay);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[0]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[10]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[11]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[12]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[13]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[14]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[15]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[16]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[17]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[18]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[19]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[1]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[2]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[3]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[4]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[5]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[6]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[7]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[8]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWADDRAXILITEAPB[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWADDRAXILITEAPB_delay[9]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWPROTAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWPROTAXILITEAPB_delay[0]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWPROTAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWPROTAXILITEAPB_delay[1]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWPROTAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWPROTAXILITEAPB_delay[2]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUAWVALIDAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUAWVALIDAXILITEAPB_delay);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUBREADYAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUBREADYAXILITEAPB_delay);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCURREADYAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCURREADYAXILITEAPB_delay);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[0]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[10]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[11]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[12]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[13]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[14]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[15]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[16]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[17]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[18]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[19]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[1]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[20]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[21]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[22]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[23]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[24]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[25]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[26]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[27]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[28]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[29]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[2]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[30]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[31]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[3]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[4]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[5]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[6]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[7]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[8]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWDATAAXILITEAPB[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWDATAAXILITEAPB_delay[9]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWSTRBAXILITEAPB[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWSTRBAXILITEAPB_delay[0]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWSTRBAXILITEAPB[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWSTRBAXILITEAPB_delay[1]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWSTRBAXILITEAPB[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWSTRBAXILITEAPB_delay[2]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWSTRBAXILITEAPB[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWSTRBAXILITEAPB_delay[3]);
$setuphold (posedge PLVCUAXILITECLK, posedge PLVCUWVALIDAXILITEAPB, 0:0:0, 0:0:0, notifier, , , PLVCUAXILITECLK_delay, PLVCUWVALIDAXILITEAPB_delay);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCARREADY, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCARREADY_delay);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCAWREADY, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCAWREADY_delay);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCBID[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBID_delay[0]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCBID[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBID_delay[1]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCBID[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBID_delay[2]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCBRESP[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBRESP_delay[0]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCBRESP[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBRESP_delay[1]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCBVALID, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBVALID_delay);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[0]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[10]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[11]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[12]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[13]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[14]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[15]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[16]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[17]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[18]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[19]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[1]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[20]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[21]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[22]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[23]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[24]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[25]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[26]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[27]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[28]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[29]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[2]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[30]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[31]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[3]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[4]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[5]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[6]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[7]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[8]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRDATA[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[9]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRID[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRID_delay[0]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRID[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRID_delay[1]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRID[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRID_delay[2]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRLAST, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRLAST_delay);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRRESP[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRRESP_delay[0]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRRESP[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRRESP_delay[1]);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCRVALID, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRVALID_delay);
$setuphold (posedge PLVCUAXIMCUCLK, negedge PLVCUMCUMAXIICDCWREADY, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCWREADY_delay);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCARREADY, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCARREADY_delay);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCAWREADY, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCAWREADY_delay);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCBID[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBID_delay[0]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCBID[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBID_delay[1]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCBID[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBID_delay[2]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCBRESP[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBRESP_delay[0]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCBRESP[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBRESP_delay[1]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCBVALID, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCBVALID_delay);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[0]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[10], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[10]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[11], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[11]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[12], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[12]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[13], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[13]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[14], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[14]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[15], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[15]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[16], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[16]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[17], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[17]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[18], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[18]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[19], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[19]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[1]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[20], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[20]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[21], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[21]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[22], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[22]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[23], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[23]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[24], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[24]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[25], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[25]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[26], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[26]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[27], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[27]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[28], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[28]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[29], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[29]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[2]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[30], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[30]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[31], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[31]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[3], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[3]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[4], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[4]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[5], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[5]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[6], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[6]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[7], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[7]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[8], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[8]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRDATA[9], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRDATA_delay[9]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRID[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRID_delay[0]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRID[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRID_delay[1]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRID[2], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRID_delay[2]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRLAST, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRLAST_delay);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRRESP[0], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRRESP_delay[0]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRRESP[1], 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRRESP_delay[1]);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCRVALID, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCRVALID_delay);
$setuphold (posedge PLVCUAXIMCUCLK, posedge PLVCUMCUMAXIICDCWREADY, 0:0:0, 0:0:0, notifier, , , PLVCUAXIMCUCLK_delay, PLVCUMCUMAXIICDCWREADY_delay);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[0], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[0]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[100], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[100]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[101], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[101]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[102], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[102]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[103], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[103]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[104], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[104]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[105], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[105]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[106], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[106]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[107], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[107]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[108], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[108]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[109], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[109]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[10], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[10]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[110], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[110]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[111], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[111]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[112], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[112]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[113], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[113]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[114], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[114]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[115], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[115]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[116], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[116]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[117], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[117]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[118], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[118]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[119], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[119]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[11], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[11]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[120], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[120]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[121], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[121]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[122], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[122]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[123], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[123]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[124], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[124]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[125], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[125]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[126], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[126]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[127], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[127]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[128], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[128]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[129], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[129]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[12], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[12]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[130], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[130]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[131], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[131]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[132], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[132]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[133], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[133]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[134], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[134]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[135], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[135]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[136], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[136]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[137], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[137]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[138], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[138]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[139], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[139]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[13], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[13]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[140], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[140]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[141], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[141]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[142], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[142]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[143], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[143]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[144], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[144]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[145], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[145]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[146], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[146]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[147], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[147]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[148], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[148]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[149], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[149]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[14], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[14]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[150], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[150]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[151], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[151]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[152], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[152]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[153], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[153]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[154], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[154]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[155], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[155]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[156], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[156]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[157], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[157]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[158], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[158]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[159], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[159]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[15], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[15]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[160], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[160]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[161], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[161]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[162], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[162]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[163], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[163]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[164], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[164]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[165], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[165]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[166], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[166]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[167], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[167]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[168], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[168]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[169], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[169]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[16], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[16]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[170], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[170]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[171], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[171]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[172], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[172]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[173], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[173]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[174], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[174]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[175], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[175]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[176], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[176]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[177], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[177]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[178], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[178]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[179], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[179]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[17], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[17]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[180], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[180]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[181], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[181]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[182], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[182]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[183], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[183]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[184], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[184]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[185], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[185]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[186], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[186]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[187], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[187]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[188], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[188]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[189], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[189]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[18], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[18]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[190], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[190]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[191], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[191]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[192], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[192]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[193], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[193]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[194], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[194]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[195], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[195]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[196], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[196]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[197], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[197]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[198], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[198]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[199], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[199]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[19], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[19]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[1], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[1]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[200], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[200]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[201], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[201]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[202], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[202]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[203], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[203]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[204], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[204]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[205], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[205]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[206], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[206]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[207], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[207]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[208], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[208]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[209], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[209]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[20], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[20]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[210], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[210]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[211], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[211]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[212], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[212]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[213], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[213]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[214], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[214]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[215], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[215]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[216], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[216]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[217], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[217]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[218], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[218]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[219], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[219]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[21], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[21]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[220], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[220]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[221], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[221]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[222], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[222]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[223], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[223]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[224], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[224]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[225], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[225]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[226], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[226]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[227], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[227]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[228], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[228]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[229], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[229]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[22], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[22]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[230], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[230]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[231], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[231]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[232], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[232]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[233], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[233]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[234], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[234]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[235], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[235]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[236], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[236]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[237], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[237]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[238], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[238]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[239], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[239]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[23], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[23]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[240], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[240]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[241], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[241]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[242], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[242]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[243], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[243]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[244], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[244]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[245], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[245]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[246], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[246]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[247], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[247]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[248], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[248]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[249], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[249]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[24], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[24]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[250], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[250]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[251], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[251]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[252], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[252]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[253], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[253]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[254], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[254]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[255], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[255]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[256], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[256]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[257], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[257]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[258], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[258]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[259], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[259]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[25], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[25]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[260], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[260]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[261], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[261]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[262], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[262]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[263], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[263]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[264], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[264]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[265], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[265]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[266], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[266]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[267], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[267]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[268], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[268]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[269], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[269]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[26], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[26]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[270], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[270]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[271], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[271]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[272], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[272]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[273], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[273]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[274], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[274]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[275], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[275]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[276], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[276]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[277], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[277]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[278], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[278]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[279], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[279]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[27], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[27]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[280], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[280]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[281], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[281]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[282], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[282]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[283], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[283]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[284], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[284]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[285], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[285]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[286], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[286]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[287], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[287]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[288], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[288]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[289], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[289]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[28], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[28]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[290], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[290]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[291], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[291]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[292], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[292]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[293], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[293]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[294], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[294]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[295], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[295]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[296], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[296]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[297], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[297]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[298], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[298]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[299], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[299]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[29], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[29]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[2], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[2]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[300], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[300]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[301], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[301]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[302], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[302]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[303], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[303]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[304], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[304]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[305], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[305]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[306], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[306]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[307], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[307]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[308], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[308]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[309], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[309]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[30], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[30]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[310], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[310]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[311], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[311]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[312], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[312]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[313], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[313]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[314], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[314]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[315], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[315]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[316], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[316]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[317], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[317]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[318], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[318]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[319], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[319]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[31], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[31]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[32], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[32]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[33], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[33]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[34], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[34]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[35], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[35]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[36], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[36]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[37], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[37]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[38], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[38]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[39], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[39]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[3], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[3]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[40], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[40]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[41], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[41]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[42], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[42]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[43], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[43]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[44], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[44]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[45], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[45]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[46], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[46]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[47], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[47]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[48], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[48]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[49], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[49]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[4], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[4]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[50], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[50]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[51], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[51]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[52], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[52]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[53], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[53]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[54], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[54]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[55], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[55]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[56], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[56]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[57], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[57]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[58], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[58]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[59], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[59]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[5], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[5]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[60], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[60]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[61], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[61]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[62], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[62]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[63], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[63]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[64], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[64]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[65], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[65]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[66], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[66]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[67], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[67]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[68], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[68]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[69], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[69]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[6], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[6]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[70], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[70]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[71], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[71]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[72], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[72]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[73], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[73]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[74], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[74]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[75], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[75]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[76], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[76]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[77], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[77]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[78], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[78]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[79], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[79]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[7], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[7]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[80], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[80]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[81], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[81]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[82], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[82]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[83], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[83]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[84], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[84]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[85], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[85]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[86], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[86]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[87], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[87]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[88], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[88]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[89], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[89]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[8], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[8]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[90], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[90]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[91], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[91]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[92], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[92]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[93], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[93]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[94], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[94]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[95], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[95]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[96], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[96]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[97], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[97]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[98], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[98]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[99], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[99]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRDATA[9], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[9]);
$setuphold (posedge PLVCUENCL2CCLK, negedge PLVCUENCALL2CRREADY, 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRREADY_delay);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[0], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[0]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[100], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[100]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[101], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[101]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[102], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[102]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[103], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[103]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[104], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[104]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[105], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[105]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[106], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[106]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[107], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[107]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[108], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[108]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[109], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[109]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[10], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[10]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[110], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[110]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[111], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[111]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[112], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[112]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[113], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[113]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[114], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[114]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[115], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[115]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[116], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[116]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[117], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[117]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[118], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[118]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[119], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[119]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[11], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[11]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[120], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[120]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[121], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[121]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[122], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[122]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[123], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[123]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[124], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[124]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[125], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[125]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[126], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[126]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[127], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[127]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[128], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[128]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[129], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[129]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[12], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[12]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[130], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[130]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[131], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[131]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[132], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[132]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[133], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[133]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[134], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[134]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[135], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[135]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[136], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[136]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[137], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[137]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[138], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[138]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[139], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[139]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[13], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[13]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[140], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[140]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[141], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[141]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[142], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[142]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[143], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[143]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[144], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[144]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[145], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[145]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[146], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[146]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[147], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[147]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[148], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[148]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[149], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[149]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[14], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[14]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[150], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[150]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[151], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[151]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[152], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[152]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[153], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[153]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[154], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[154]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[155], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[155]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[156], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[156]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[157], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[157]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[158], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[158]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[159], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[159]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[15], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[15]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[160], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[160]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[161], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[161]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[162], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[162]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[163], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[163]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[164], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[164]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[165], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[165]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[166], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[166]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[167], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[167]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[168], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[168]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[169], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[169]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[16], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[16]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[170], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[170]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[171], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[171]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[172], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[172]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[173], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[173]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[174], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[174]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[175], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[175]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[176], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[176]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[177], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[177]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[178], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[178]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[179], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[179]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[17], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[17]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[180], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[180]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[181], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[181]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[182], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[182]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[183], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[183]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[184], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[184]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[185], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[185]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[186], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[186]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[187], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[187]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[188], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[188]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[189], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[189]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[18], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[18]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[190], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[190]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[191], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[191]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[192], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[192]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[193], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[193]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[194], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[194]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[195], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[195]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[196], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[196]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[197], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[197]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[198], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[198]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[199], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[199]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[19], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[19]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[1], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[1]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[200], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[200]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[201], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[201]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[202], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[202]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[203], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[203]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[204], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[204]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[205], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[205]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[206], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[206]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[207], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[207]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[208], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[208]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[209], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[209]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[20], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[20]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[210], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[210]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[211], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[211]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[212], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[212]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[213], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[213]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[214], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[214]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[215], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[215]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[216], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[216]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[217], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[217]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[218], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[218]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[219], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[219]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[21], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[21]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[220], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[220]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[221], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[221]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[222], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[222]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[223], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[223]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[224], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[224]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[225], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[225]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[226], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[226]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[227], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[227]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[228], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[228]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[229], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[229]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[22], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[22]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[230], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[230]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[231], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[231]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[232], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[232]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[233], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[233]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[234], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[234]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[235], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[235]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[236], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[236]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[237], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[237]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[238], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[238]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[239], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[239]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[23], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[23]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[240], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[240]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[241], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[241]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[242], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[242]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[243], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[243]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[244], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[244]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[245], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[245]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[246], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[246]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[247], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[247]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[248], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[248]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[249], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[249]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[24], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[24]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[250], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[250]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[251], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[251]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[252], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[252]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[253], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[253]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[254], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[254]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[255], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[255]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[256], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[256]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[257], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[257]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[258], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[258]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[259], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[259]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[25], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[25]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[260], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[260]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[261], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[261]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[262], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[262]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[263], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[263]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[264], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[264]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[265], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[265]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[266], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[266]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[267], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[267]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[268], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[268]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[269], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[269]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[26], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[26]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[270], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[270]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[271], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[271]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[272], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[272]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[273], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[273]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[274], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[274]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[275], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[275]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[276], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[276]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[277], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[277]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[278], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[278]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[279], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[279]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[27], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[27]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[280], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[280]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[281], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[281]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[282], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[282]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[283], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[283]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[284], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[284]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[285], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[285]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[286], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[286]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[287], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[287]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[288], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[288]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[289], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[289]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[28], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[28]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[290], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[290]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[291], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[291]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[292], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[292]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[293], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[293]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[294], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[294]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[295], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[295]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[296], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[296]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[297], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[297]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[298], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[298]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[299], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[299]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[29], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[29]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[2], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[2]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[300], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[300]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[301], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[301]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[302], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[302]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[303], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[303]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[304], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[304]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[305], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[305]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[306], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[306]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[307], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[307]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[308], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[308]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[309], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[309]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[30], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[30]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[310], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[310]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[311], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[311]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[312], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[312]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[313], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[313]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[314], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[314]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[315], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[315]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[316], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[316]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[317], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[317]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[318], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[318]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[319], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[319]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[31], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[31]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[32], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[32]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[33], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[33]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[34], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[34]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[35], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[35]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[36], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[36]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[37], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[37]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[38], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[38]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[39], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[39]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[3], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[3]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[40], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[40]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[41], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[41]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[42], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[42]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[43], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[43]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[44], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[44]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[45], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[45]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[46], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[46]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[47], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[47]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[48], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[48]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[49], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[49]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[4], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[4]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[50], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[50]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[51], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[51]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[52], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[52]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[53], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[53]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[54], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[54]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[55], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[55]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[56], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[56]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[57], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[57]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[58], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[58]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[59], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[59]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[5], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[5]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[60], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[60]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[61], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[61]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[62], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[62]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[63], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[63]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[64], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[64]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[65], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[65]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[66], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[66]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[67], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[67]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[68], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[68]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[69], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[69]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[6], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[6]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[70], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[70]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[71], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[71]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[72], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[72]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[73], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[73]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[74], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[74]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[75], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[75]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[76], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[76]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[77], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[77]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[78], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[78]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[79], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[79]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[7], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[7]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[80], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[80]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[81], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[81]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[82], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[82]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[83], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[83]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[84], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[84]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[85], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[85]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[86], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[86]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[87], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[87]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[88], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[88]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[89], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[89]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[8], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[8]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[90], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[90]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[91], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[91]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[92], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[92]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[93], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[93]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[94], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[94]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[95], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[95]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[96], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[96]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[97], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[97]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[98], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[98]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[99], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[99]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRDATA[9], 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRDATA_delay[9]);
$setuphold (posedge PLVCUENCL2CCLK, posedge PLVCUENCALL2CRREADY, 0:0:0, 0:0:0, notifier, , , PLVCUENCL2CCLK_delay, PLVCUENCALL2CRREADY_delay);
$width (negedge PLVCUAXIDECCLK, 0:0:0, 0, notifier);
$width (negedge PLVCUAXIENCCLK, 0:0:0, 0, notifier);
$width (negedge PLVCUAXILITECLK, 0:0:0, 0, notifier);
$width (negedge PLVCUAXIMCUCLK, 0:0:0, 0, notifier);
$width (negedge PLVCUCORECLK, 0:0:0, 0, notifier);
$width (negedge PLVCUENCL2CCLK, 0:0:0, 0, notifier);
$width (negedge PLVCUMCUCLK, 0:0:0, 0, notifier);
$width (negedge PLVCUPLLREFCLKPL, 0:0:0, 0, notifier);
$width (posedge PLVCUAXIDECCLK, 0:0:0, 0, notifier);
$width (posedge PLVCUAXIENCCLK, 0:0:0, 0, notifier);
$width (posedge PLVCUAXILITECLK, 0:0:0, 0, notifier);
$width (posedge PLVCUAXIMCUCLK, 0:0:0, 0, notifier);
$width (posedge PLVCUCORECLK, 0:0:0, 0, notifier);
$width (posedge PLVCUENCL2CCLK, 0:0:0, 0, notifier);
$width (posedge PLVCUMCUCLK, 0:0:0, 0, notifier);
$width (posedge PLVCUPLLREFCLKPL, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
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