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module inst_memory_controll
#(
parameter DATA_WIDTH = 32,
parameter DATA_ADDR_WIDTH = 32,
parameter SRAM_ADDR_WIDTH = 20,
parameter SRAM_DATA_WIDTH = 16
)
(/*autoport*/
input clk,
input rst_n,
output data_rd_en,
output data_wr_en,
output [DATA_ADDR_WIDTH-1:0] data_addr,
input [DATA_WIDTH-1:0] data_in,
output [DATA_WIDTH-1:0] data_out,
//SRAM
output [SRAM_ADDR_WIDTH-1:0] sram_addr,
output sram_ce_n,
inout [SRAM_DATA_WIDTH-1:0] sram_dq,
output sram_lb_n,
output sram_oe_n,
output sram_ub_n,
output sram_we_n
);
//*******************************************************
//Internal
//*******************************************************
//Local Parameters
//Wires
//Registers
//*******************************************************
//General Purpose Signals
//*******************************************************
//*******************************************************
//Outputs
//*******************************************************
//*******************************************************
//Instantiations
//*******************************************************
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A2111O_FUNCTIONAL_PP_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a2111o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , C1, B1, and0_out, D1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111O_FUNCTIONAL_PP_V |
module processor;
wire [31:0] mux4out,pcout,imemout,reg1out,reg2out,mux3out,signout,mux2out,xorout,arith1out,dmemout,mux6out,arith2out,shiftlout,arith3out,andout,orout,mux5out;
wire [4:0] mux1out;
reg reset;
clock clock1(clk);
programcounter PC(mux4out,clk,pcout,reset);
instructionmemory imem(imemout,pcout[6:0],clk);
registerfile regis(RegWrite,reg1out,reg2out,imemout[25:21],imemout[20:16],mux1out,mux3out,clk);
xor32bit xor1(xorout, mux2out, sub);
alunit arith1(arith1out,reg1out, xorout,sub,zero);
datamemory dmem(dmemout,mux6out[15:0],reg2out,MemWrite,MemRead,clk);
alucontroler acontrol(imemout[5:0],sub,select5,select6,AluOp);
alunit arith2(arith2out,32'b00000000000000000000000000000100, pcout,0,zero2);
shift2 shiftl(signout,shiftlout);
alunit arith3(arith3out,arith2out, shiftlout,0,zero3);
and32bit and1(andout, mux2out, reg1out);
or32bit or1(orout, mux2out, reg1out);
mux5bit mux1(imemout[20:16],imemout[15:11],mux1out,RegDst);
mux32bit mux2(reg2out,signout,mux2out,ALUSrc);
mux32bit mux3(dmemout,mux6out,mux3out,MemToReg);
mux32bit mux4(arith2out,arith3out,mux4out,andcout);
mux32bit mux5(andout,orout,mux5out,select5);
mux32bit mux6(mux5out, arith1out,mux6out,select6);
and(andcout,zero,branch);
signextend signextender(imemout[15:0],signout);
controlunit cntrlunit(imemout[31:26],branch,MemWrite,MemRead,ALUSrc,RegWrite,RegDst,AluOp,MemToReg);
initial
begin
$monitor("PC=%b;INS=%b;data1=%b;data2=%b;ALU=%b;writeback=%b;clock=%b",pcout,imemout,reg1out,reg2out,mux6out,mux3out,clk);
#2
reset=1'b0;
//#2
reset=1'b1;
//#2
reset=1'b0;
#70
$finish();
end
endmodule
|
`timescale 1ns / 1ps
module VGAInterface(
input CLK, //Clock signal of 25MHz
output REFRESH, //gives trigger when display was refreshed
input [7:0] COLOUR_IN, //colour comes that should be displayd
output reg [7:0] COLOUR_OUT, //colour goes that was modified to produce colour_in at the rigth moment
output [9:0] ADDRH, //Address of the horizontal pixel
output [8:0] ADDRV, //Address of vertical pixel
output reg HS, //Horizontal Synch signal
output reg VS, //Vertical Synch signal
//output [9:0] VertCounter,
//output [9:0] HorzCounter
// output EndHorzCounter
input DOWNCOUNTER
);
//In many places you will see Value - 1; that minus 1 stands for the fact
//that we are counting synch times & addresses of pixels starting from
//0 to max-1 value;
wire [9:0] VertCounter; //Vertical Synch time Counter
wire [9:0] HorzCounter; //Horizontal Synch time Counter
wire EndHorzTrigger; //Trigger to detect end of line
initial begin //Initial values
HS = 0;
VS = 0;
COLOUR_OUT = 8'b0;
end
//Time in horizontal lines
parameter HorzTimeToPulseWidthEnd = 10'd96;
parameter HorzTimeToBackPorchEnd = 10'd144;
parameter HorzTimeToDisplayTimeEnd = 10'd784;
parameter HorzTimeToFrontPorchEnd = 10'd800;
//Time in Vertincal lines
parameter VertTimeToPulseWidthEnd = 10'd2; //2 values for different resolution.. maybe will perform better?
parameter VertTimeToBackPorchEnd = 10'd31; //33? //35?
parameter VertTimeToDisplayTimeEnd = 10'd511; //515
parameter VertTimeToFrontPorchEnd = 10'd521; //525
Counter # (
.MaxValue(HorzTimeToFrontPorchEnd-1), //max value of synch - 1; for counting from 0 to max-1;
.Size(10) //Size in bits of the max value
)
TimeCounterHorizontal(
.CLK(CLK), //Clock signal
.ENABLE(DOWNCOUNTER), //downcounter which here is the same as original clock signal
.TRIGGER_OUT(EndHorzTrigger), //triggers when line ends
.TIME_COUNT(HorzCounter) //produces value of horizontal synch
);
Counter # (
.MaxValue(VertTimeToFrontPorchEnd-1), //max value - 1
.Size(10) //Size of max balue in bits
)
TimeCounterVertical(
.CLK(CLK), //Clock signal
.ENABLE(EndHorzTrigger), //downcounter counts how many lines ended
.TRIGGER_OUT(REFRESH), //if vertical line ended -> produces a trigger which signals refresh of the screen
.TIME_COUNT(VertCounter) //value of vertical synch timer
);
//Checks if produce HS -> LOW or HIGH
always @(posedge CLK) begin//-1
if ((HorzCounter < HorzTimeToPulseWidthEnd-1) || (HorzCounter == HorzTimeToFrontPorchEnd-1))//if less that TimeToPulseWidthEnd
HS <= 1'b0;
else
HS <= 1'b1;
end
//Check if VS -> LOW or HIGH
always @(posedge CLK) begin//-1
if (EndHorzTrigger)begin
if ((VertCounter < VertTimeToPulseWidthEnd-1) || (VertCounter == VertTimeToFrontPorchEnd-1))
VS <= 1'b0;
else
VS <= 1'b1;
end
end
//Checks if COLOUR_OUT -> COLOUR_IN or make COLOUR_OUT -> BLACK
always @(posedge CLK) begin
if (DOWNCOUNTER) begin
if ( (HorzCounter > HorzTimeToBackPorchEnd-2) //-2 for shifting to the left
&& (HorzCounter <= HorzTimeToDisplayTimeEnd-2)
&& (VertCounter > VertTimeToBackPorchEnd-1)
&& (VertCounter <= VertTimeToDisplayTimeEnd-1) )
COLOUR_OUT <= COLOUR_IN;
else
COLOUR_OUT <= 8'b0;
end
end
//Gets address of horizontal pixel
PixCounter # (
.AddressSize(10), //Size of the max value of address
.TimeToBackPorchEnd (HorzTimeToBackPorchEnd-1), //lower value of synch timer; -1 corrects the fact that synch starts from 0 to max-1 too;
.TimeToDisplayTimeEnd (HorzTimeToDisplayTimeEnd-1) //upper value of synch timer
)
HorzPix(
.CLK(CLK), //clock signal
.SYNCH_TIME(HorzCounter), //gets Synch time
.ENABLE(DOWNCOUNTER), //trigger in which here is just CLK
.PIXCOUNT(ADDRH) //actual horizontal address of a pixel
);
//Gets address of vertical pixel; The same as to horizontal but for vertical
PixCounter # (
.AddressSize(9),
.TimeToBackPorchEnd (VertTimeToBackPorchEnd-1),
.TimeToDisplayTimeEnd (VertTimeToDisplayTimeEnd-1)
)
VertPix(
.CLK(CLK),
.SYNCH_TIME(VertCounter),
.ENABLE(EndHorzTrigger), //downcounter checks if line ended
.PIXCOUNT(ADDRV)
);
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file ram_16x8k_dp.v when simulating
// the core, ram_16x8k_dp. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module ram_16x8k_dp(
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb
);
input clka;
input ena;
input [1 : 0] wea;
input [12 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
input clkb;
input enb;
input [1 : 0] web;
input [12 : 0] addrb;
input [15 : 0] dinb;
output [15 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_2 #(
.C_ADDRA_WIDTH(13),
.C_ADDRB_WIDTH(13),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(1),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(8192),
.C_READ_DEPTH_B(8192),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(2),
.C_WEB_WIDTH(2),
.C_WRITE_DEPTH_A(8192),
.C_WRITE_DEPTH_B(8192),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.ENB(enb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.RSTB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
// Date : Tue Jun 21 04:37:54 2016
// Host : jalapeno running 64-bit unknown
// Command : write_verilog -force -mode synth_stub {/home/hhassan/git/GateKeeper/FPGA
// Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/clk_gen/clk_gen_stub.v}
// Design : clk_gen
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx690tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_gen(clk_in1, clk_out1, reset)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,reset" */;
input clk_in1;
output clk_out1;
input reset;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jan 22 23:54:01 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_gpio_0_0_stub.v
// Design : design_1_axi_gpio_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio2_io_i)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio2_io_i[3:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [3:0]gpio_io_i;
input [3:0]gpio2_io_i;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/20/2016 10:52:34 PM
// Design Name:
// Module Name: selNextPPV
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "global.vh"
module selNextPPV(
pre_nppv,
outdir,
nppv
);
input [`NUM_PORT*4-1:0] pre_nppv;
input [1:0] outdir;
output [`NUM_PORT-1:0] nppv;
wire [`NUM_PORT-1:0] w_nppv [0:3];
genvar i;
generate
for (i=0; i<4; i=i+1) begin : split_nppv
assign w_nppv[i] = pre_nppv[i*`NUM_PORT +: `NUM_PORT];
end
endgenerate
assign nppv = outdir == 0 ? w_nppv[0] :
outdir == 1 ? w_nppv[1] :
outdir == 2 ? w_nppv[2] :
outdir == 3 ? w_nppv[3] :
`NUM_PORT'h0;
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : cabac_mvd.v
// Author : guo yong
// Created : 2013-06
// Description : H.264 encode mvd, modified
//
//-------------------------------------------------------------------
`define MEM_TOP_DEPTH 9
`include "enc_defines.v"
module cabac_mvd(
//input
clk ,
rst_n ,
mb_x_i ,
mb_y_i ,
curr_state_i ,
mb_partition_i ,
mb_sub_partition_i ,
mvd_curr_i ,
//output
r_addr_mvd_o ,
mvd_done_o ,
ctx_pair_mvd_0_o ,
ctx_pair_mvd_1_o ,
ctx_pair_mvd_2_o ,
ctx_pair_mvd_3_o ,
ctx_pair_mvd_4_o ,
ctx_pair_mvd_5_o ,
ctx_pair_mvd_6_o ,
ctx_pair_mvd_7_o ,
ctx_pair_mvd_8_o ,
ctx_pair_mvd_9_o ,
ctx_pair_mvd_10_o ,
ctx_pair_mvd_11_o ,
ctx_pair_mvd_12_o ,
ctx_pair_mvd_13_o ,
ctx_pair_mvd_14_o ,
ctx_pair_mvd_15_o ,
valid_num_bin_mvd_o
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter CABAC_mvd = 5'd11 ;
//mb_sub_partition
parameter D_L0_4x4 = 2'd3 ,
D_L0_8x4 = 2'd1 ,
D_L0_4x8 = 2'd2 ,
D_L0_8x8 = 2'd0 ;
//mb_partition
parameter D_8x8 = 2'd3 ,
D_16x8 = 2'd1 ,
D_8x16 = 2'd2 ,
D_16x16 = 2'd0 ;
//mvd_encode_state
parameter MVD_IDLE = 2'd0 ,
MVD_ENCODE = 2'd1 ,
MVD_DONE = 2'd2 ;
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
//input
input clk ; //clock signal
input rst_n ; //reset signal
input [`PIC_X_WIDTH-1:0] mb_x_i ; //mb_x
input [`PIC_Y_WIDTH-1:0] mb_y_i ; //mb_y
input [4:0] curr_state_i ; //binarization machine state
input [1:0] mb_partition_i ; //mb_partition
input [7:0] mb_sub_partition_i ; //mb sub_partition
input [2*(`FMV_WIDTH+1)-1:0] mvd_curr_i ; //mvd of a 4x4 block in one macroblock from memory
//output
output [3:0] r_addr_mvd_o ; //mvd address of mvd memory for read mvd
output mvd_done_o ; //coding mvd done signal
output [11:0] ctx_pair_mvd_0_o ; //context pair of mvd 0
output [11:0] ctx_pair_mvd_1_o ; //context pair of mvd 1
output [11:0] ctx_pair_mvd_2_o ; //context pair of mvd 2
output [11:0] ctx_pair_mvd_3_o ; //context pair of mvd 3
output [11:0] ctx_pair_mvd_4_o ; //context pair of mvd 4
output [11:0] ctx_pair_mvd_5_o ; //context pair of mvd 5
output [11:0] ctx_pair_mvd_6_o ; //context pair of mvd 6
output [11:0] ctx_pair_mvd_7_o ; //context pair of mvd 7
output [11:0] ctx_pair_mvd_8_o ; //context pair of mvd 8
output [11:0] ctx_pair_mvd_9_o ; //context pair of mvd 9
output [11:0] ctx_pair_mvd_10_o ; //context pair of mvd 10
output [11:0] ctx_pair_mvd_11_o ; //context pair of mvd 11
output [11:0] ctx_pair_mvd_12_o ; //context pair of mvd 12
output [11:0] ctx_pair_mvd_13_o ; //context pair of mvd 13
output [11:0] ctx_pair_mvd_14_o ; //context pair of mvd 14
output [11:0] ctx_pair_mvd_15_o ; //context pair of mvd 15
output [3:0] valid_num_bin_mvd_o ; //valid number bin of mvd
// ********************************************
//
// Reg / Wire DECLARATION
//
// ********************************************
reg mvd_done_o ; //coding mvd done signal
reg [11:0] ctx_pair_mvd_0_o ; //context pair of mvd 0
reg [11:0] ctx_pair_mvd_1_o ; //context pair of mvd 1
reg [11:0] ctx_pair_mvd_2_o ; //context pair of mvd 2
reg [11:0] ctx_pair_mvd_3_o ; //context pair of mvd 3
reg [11:0] ctx_pair_mvd_4_o ; //context pair of mvd 4
reg [11:0] ctx_pair_mvd_5_o ; //context pair of mvd 5
reg [11:0] ctx_pair_mvd_6_o ; //context pair of mvd 6
reg [11:0] ctx_pair_mvd_7_o ; //context pair of mvd 7
reg [11:0] ctx_pair_mvd_8_o ; //context pair of mvd 8
reg [11:0] ctx_pair_mvd_9_o ; //context pair of mvd 9
reg [11:0] ctx_pair_mvd_10_o ; //context pair of mvd 10
reg [11:0] ctx_pair_mvd_11_o ; //context pair of mvd 11
reg [11:0] ctx_pair_mvd_12_o ; //context pair of mvd 12
reg [11:0] ctx_pair_mvd_13_o ; //context pair of mvd 13
reg [11:0] ctx_pair_mvd_14_o ; //context pair of mvd 14
reg [11:0] ctx_pair_mvd_15_o ; //context pair of mvd 15
reg [3:0] valid_num_bin_mvd_o ; //valid number bin of mvd
reg [3:0] valid_num_bin_mvd_r ; //valid number bin of mvd reg
wire [11:0] ctx_pair_mvd_bypass_w ; //last bin of mvd sign
reg [1:0] mb_sub_part_r ; //sub partition read in a macroblock
reg [1:0] mb_sub_part_encode_r ; //sub partition encode
reg [3:0] mvd_idx_r ; //mvd_idx:0~15, when read
reg [3:0] mvd_idx_0_r ; //
reg [3:0] mvd_idx_encode_r ; //mvd_idx:0~15, when encode
reg [1:0] mvd_8x8_idx_r ; //mvd index of sub block reading
reg [1:0] mvd_8x8_idx_encode_r ; //mvd index of sub block encoding
reg [1:0] mvd_8x8_sub_idx_r ; //mvd sub_idx of 4x4 block
reg mvd_8x8_done_r ; //mvd of sub 8x8 block done flag
reg mvd_encode_done_r ; //mvd encode done flag, and then write neighbour info
//to corresponding sram
reg mvd_e_done_r ; //one mvd encode finish
reg mvd_e_done_delay_r ; //e_done delay signal
reg [2*(`FMV_WIDTH+1)-1:0] mvd_curr_r ; //mvd of a 4x4 block in one macroblock from memory
//sign_abs_x, sign_abs_y
wire sign_x_w ;
wire sign_y_w ;
reg [2*(`FMV_WIDTH+1)-1:0] mvd_encode_r ; //current encode mvd
reg [2*(`FMV_WIDTH+1)-1:0] mvd_left_r ; //current encode mvd
reg [2*(`FMV_WIDTH+1)-1:0] mvd_top_r ; //current encode mvd
reg [`FMV_WIDTH:0] abs_ref_mvd_r ; //left abs mvd add top abs mvd
reg [`FMV_WIDTH-1:0] abs_mvd_r ; //mvd absolution
reg [`FMV_WIDTH-1:0] abs_mvd_bypass_r ; //abs_mvd-9
wire [`FMV_WIDTH:0] mvd_x_curr_w ; //current block mvd_x
wire [`FMV_WIDTH:0] mvd_y_curr_w ; //current block mvd_y
wire [`FMV_WIDTH:0] mvd_x_left_w ; //left block mvd_x
wire [`FMV_WIDTH:0] mvd_y_left_w ; //left block mvd_y
wire [`FMV_WIDTH:0] mvd_x_top_w ; //top block mvd_x
wire [`FMV_WIDTH:0] mvd_y_top_w ; //top block mvd_y
reg [8:0] ctx_idx_mvd_0_r ; //context index of mvd 0
reg [8:0] ctx_idx_mvd_1_r ; //context index of mvd 1
reg [8:0] ctx_idx_mvd_2_r ; //context index of mvd 2
reg [8:0] ctx_idx_mvd_3_r ; //context index of mvd 3
reg [8:0] ctx_idx_mvd_4_r ; //context index of mvd 4
reg [8:0] ctx_idx_mvd_5_r ; //context index of mvd 5
reg [8:0] ctx_idx_mvd_6_r ; //context index of mvd 6
reg [8:0] ctx_idx_mvd_7_r ; //context index of mvd 7
reg [8:0] ctx_idx_mvd_8_r ; //context index of mvd 8
reg [8:0] bin_string_mvd_prefix_r ; //bin string of mvd_x/mvd_y prefix after binarization
reg [3:0] valid_num_bin_mvd_prefix_r ; //valid number of bin of mvd prefix
wire [11:0] ctx_pair_mvd_prefix_0_w ; //context pair of mvd_x/mvd_y prefix 0
wire [11:0] ctx_pair_mvd_prefix_1_w ; //context pair of mvd_x/mvd_y prefix 1
wire [11:0] ctx_pair_mvd_prefix_2_w ; //context pair of mvd_x/mvd_y prefix 2
wire [11:0] ctx_pair_mvd_prefix_3_w ; //context pair of mvd_x/mvd_y prefix 3
wire [11:0] ctx_pair_mvd_prefix_4_w ; //context pair of mvd_x/mvd_y prefix 4
wire [11:0] ctx_pair_mvd_prefix_5_w ; //context pair of mvd_x/mvd_y prefix 5
wire [11:0] ctx_pair_mvd_prefix_6_w ; //context pair of mvd_x/mvd_y prefix 6
wire [11:0] ctx_pair_mvd_prefix_7_w ; //context pair of mvd_x/mvd_y prefix 7
wire [11:0] ctx_pair_mvd_prefix_8_w ; //context pair of mvd_x/mvd_y prefix 8
reg [15:0] bin_string_mvd_suffix_r ; //bin string of mvd_x/mvd_y suffix after binarization
reg [3:0] mvd_suffix_length_r ; //mvd suffix length
reg [3:0] mvd_bypass_length_r ; //mvd bypass length
//neighbour memory signal
wire r_mvd_left_en_w ; //read left memory enable signal
wire w_mvd_left_en_w ; //write left memory enable signal
wire [1 :0] r_addr_mvd_left_w ; //read left memory address signal
wire [1 :0] w_addr_mvd_left_w ; //write left memory address signal
wire [2*(`FMV_WIDTH+1)-1:0] r_data_mvd_left_w ; //read data from left memory
wire [2*(`FMV_WIDTH+1)-1:0] w_data_mvd_left_w ; //write data to left memory
wire r_mvd_top_en_w ; //read top memory enable signal
wire w_mvd_top_en_w ; //write top memory enable signal
wire [(`MEM_TOP_DEPTH-1):0] r_addr_mvd_top_w ; //read top memory address signal
wire [(`MEM_TOP_DEPTH-1):0] w_addr_mvd_top_w ; //write top memory address signal
wire [2*(`FMV_WIDTH+1)-1:0] r_data_mvd_top_w ; //read data from top memory
wire [2*(`FMV_WIDTH+1)-1:0] w_data_mvd_top_w ; //write data to top memory
reg r_mvd_left_en_r ; //read left memory enable signal
reg w_mvd_left_en_r ; //write left memory enable signal
reg [1 :0] r_addr_mvd_left_r ; //read left memory address signal
reg [1 :0] w_addr_mvd_left_r ; //write left memory address signal
reg [2*(`FMV_WIDTH+1)-1:0] r_data_mvd_left_r ; //read data from left memory
reg [2*(`FMV_WIDTH+1)-1:0] w_data_mvd_left_r ; //write data to left memory
reg r_mvd_top_en_r ; //read top memory enable signal
reg w_mvd_top_en_r ; //write top memory enable signal
reg [(`MEM_TOP_DEPTH-1):0] r_addr_mvd_top_r ; //read top memory address signal
reg [(`MEM_TOP_DEPTH-1):0] w_addr_mvd_top_r ; //write top memory address signal
reg [2*(`FMV_WIDTH+1)-1:0] r_data_mvd_top_r ; //read data from top memory
reg [2*(`FMV_WIDTH+1)-1:0] w_data_mvd_top_r ; //write data to top memory
reg [3 :0] write_cyc_num_r ; //write data cycle number
reg y_encode_flag_r ; //encode mvd_y after encode mvd_x
reg prefix_encode_flag_r ; //encode prefix of mvd_x or mvd_y
reg [2 :0] mvd_encode_total_num_r ; //total cycle number of encode one mvd
reg [2 :0] mvd_encode_count_r ; //count cycle number of encode one mvd, 2 or 3 or 4
wire mvd_x_less9_w ; //mvd_x less than 9
wire mvd_y_less9_w ; //mvd_y less than 9
reg [2*(`FMV_WIDTH+1)-1:0] cache_left_r ; //cache left data
reg [2*(`FMV_WIDTH+1)-1:0] cache_top_r ; //cache top data
reg [2*(`FMV_WIDTH+1)-1:0] cache0_r ; //cache0
reg [2*(`FMV_WIDTH+1)-1:0] cache1_r ; //cache1
reg [1 :0] mvd_curr_state_r ; //curr_state
reg [1 :0] mvd_next_state_r ; //next_state
reg [3 :0] valid_num_bin_minus1_r ; //valid_num_bin_mvd_r - 1
reg [2 :0] output_cyc_cnt_r ; //output cycle count
reg [2 :0] output_cyc_tot_r ; //output_cycle total
wire trans_en_w ; //transform to next block enable
//valid_num_bin_minus1_r
always @* begin
if(valid_num_bin_mvd_r>1)
valid_num_bin_minus1_r = valid_num_bin_mvd_r - 1;
else
valid_num_bin_minus1_r = valid_num_bin_mvd_r;
end
//sign_x_w, sign_y_w
assign sign_x_w = mvd_curr_i[(2*`FMV_WIDTH)+1];
assign sign_y_w = mvd_curr_i[`FMV_WIDTH];
reg [`FMV_WIDTH:0] abs_x_w;
reg [`FMV_WIDTH:0] abs_y_w;
always @* begin
if(mvd_curr_i[2*`FMV_WIDTH+1])
abs_x_w = {1'b1, (~mvd_curr_i[(2*`FMV_WIDTH):(`FMV_WIDTH+1)])+1};
else
abs_x_w = mvd_curr_i[2*`FMV_WIDTH+1:`FMV_WIDTH+1];
end
always @* begin
if(mvd_curr_i[`FMV_WIDTH])
abs_y_w = {1'b1, (~mvd_curr_i[(`FMV_WIDTH-1):0]+1)};
else
abs_y_w = mvd_curr_i[`FMV_WIDTH:0];
end
//mvd_curr_r
always @* begin
mvd_curr_r = {abs_x_w, abs_y_w};
end
//output_cyc_cnt_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
output_cyc_cnt_r <= 0;
else if(mvd_curr_state_r!=MVD_ENCODE)
output_cyc_cnt_r <= 0;
else if(output_cyc_cnt_r==(output_cyc_tot_r-1))
output_cyc_cnt_r <= 0;
else
output_cyc_cnt_r <= output_cyc_cnt_r + 1;
end
//output_cyc_tot_r
always @* begin
case(valid_num_bin_minus1_r[3:2])
2'b00: output_cyc_tot_r = 1;
2'b01: output_cyc_tot_r = 2;
2'b10: output_cyc_tot_r = 3;
2'b11: output_cyc_tot_r = 4;
default:output_cyc_tot_r = 0;
endcase
end
//transform to next block
assign trans_en_w = (output_cyc_cnt_r==(output_cyc_tot_r-1) ? 1 : 0);
assign mvd_y_curr_w = mvd_encode_r [`FMV_WIDTH:0];
assign mvd_x_curr_w = mvd_encode_r [2*(`FMV_WIDTH)+1:(`FMV_WIDTH+1)];
assign mvd_y_left_w = mvd_left_r [`FMV_WIDTH:0];
assign mvd_x_left_w = mvd_left_r [2*(`FMV_WIDTH)+1:(`FMV_WIDTH+1)];
assign mvd_y_top_w = mvd_top_r [`FMV_WIDTH:0];
assign mvd_x_top_w = mvd_top_r [2*(`FMV_WIDTH)+1:(`FMV_WIDTH+1)];
assign ctx_pair_mvd_prefix_0_w = {2'b00, bin_string_mvd_prefix_r[8], ctx_idx_mvd_0_r};
assign ctx_pair_mvd_prefix_1_w = {2'b00, bin_string_mvd_prefix_r[7], ctx_idx_mvd_1_r};
assign ctx_pair_mvd_prefix_2_w = {2'b00, bin_string_mvd_prefix_r[6], ctx_idx_mvd_2_r};
assign ctx_pair_mvd_prefix_3_w = {2'b00, bin_string_mvd_prefix_r[5], ctx_idx_mvd_3_r};
assign ctx_pair_mvd_prefix_4_w = {2'b00, bin_string_mvd_prefix_r[4], ctx_idx_mvd_4_r};
assign ctx_pair_mvd_prefix_5_w = {2'b00, bin_string_mvd_prefix_r[3], ctx_idx_mvd_5_r};
assign ctx_pair_mvd_prefix_6_w = {2'b00, bin_string_mvd_prefix_r[2], ctx_idx_mvd_6_r};
assign ctx_pair_mvd_prefix_7_w = {2'b00, bin_string_mvd_prefix_r[1], ctx_idx_mvd_7_r};
assign ctx_pair_mvd_prefix_8_w = {2'b00, bin_string_mvd_prefix_r[0], ctx_idx_mvd_8_r};
assign ctx_pair_mvd_bypass_w = {2'b01, (y_encode_flag_r ? mvd_y_curr_w[`FMV_WIDTH] : mvd_x_curr_w[`FMV_WIDTH]), 9'd511};
assign r_addr_mvd_o = mvd_idx_r;
// ********************************************
//
// Combinational Logic
//
// ********************************************
//mvd_curr_state_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
mvd_curr_state_r <= MVD_IDLE;
else
mvd_curr_state_r <= mvd_next_state_r;
end
//mvd_next_state_r
always @* begin
if(curr_state_i!=CABAC_mvd)
mvd_next_state_r = MVD_IDLE;
else begin
case(mvd_curr_state_r)
MVD_IDLE: mvd_next_state_r = MVD_ENCODE;
MVD_ENCODE: if(write_cyc_num_r==8)
mvd_next_state_r = MVD_DONE;
else
mvd_next_state_r = MVD_ENCODE;
MVD_DONE: mvd_next_state_r = MVD_IDLE;
default: mvd_next_state_r = MVD_IDLE;
endcase
end
end
assign mvd_x_less9_w = (mvd_x_curr_w[(`FMV_WIDTH-1):0]<9);
assign mvd_y_less9_w = (mvd_y_curr_w[(`FMV_WIDTH-1):0]<9);
always @* begin
if(curr_state_i!=CABAC_mvd)
mvd_encode_total_num_r = 0;
else if(mvd_x_less9_w && mvd_y_less9_w)
mvd_encode_total_num_r = 2;
else if(mvd_x_less9_w)
mvd_encode_total_num_r = 3;
else if(mvd_y_less9_w)
mvd_encode_total_num_r = 3;
else
mvd_encode_total_num_r = 4;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
mvd_encode_count_r <= 0;
else if(curr_state_i!=CABAC_mvd)
mvd_encode_count_r <= 0;
else if(mvd_curr_state_r==MVD_IDLE)
mvd_encode_count_r <= 0;
else if(mvd_encode_count_r==(mvd_encode_total_num_r-1) && trans_en_w)
mvd_encode_count_r <= 0;
else if(trans_en_w)
mvd_encode_count_r <= mvd_encode_count_r + 1;
else
mvd_encode_count_r <= mvd_encode_count_r;
end
always @* begin
if(mvd_x_less9_w && mvd_encode_count_r>=1)
y_encode_flag_r = 1;
else if(~mvd_x_less9_w && mvd_encode_count_r>=2)
y_encode_flag_r = 1;
else
y_encode_flag_r = 0;
end
always @* begin
if(curr_state_i!=CABAC_mvd)
prefix_encode_flag_r = 0;
else if(mvd_idx_r>0 || mvd_idx_encode_r>0) begin
case(mvd_encode_count_r)
0: begin
prefix_encode_flag_r = 1;
end
1: begin
if(mvd_x_less9_w)
prefix_encode_flag_r = 1;
else
prefix_encode_flag_r = 0;
end
2: begin
if(~mvd_x_less9_w)
prefix_encode_flag_r = 1;
else
prefix_encode_flag_r = 0;
end
default:
prefix_encode_flag_r = 0;
endcase
end
else
prefix_encode_flag_r = 0;
end
//one mvd encode finish
always @* begin
if(mvd_encode_done_r)
mvd_e_done_r = 0;
else if(mvd_curr_state_r==MVD_IDLE)
mvd_e_done_r = 1;
else if(mvd_encode_count_r==(mvd_encode_total_num_r-1) && trans_en_w)
mvd_e_done_r = 1;
else
mvd_e_done_r = 0;
end
//mvd_e_done_delay_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
mvd_e_done_delay_r <= 0;
else
mvd_e_done_delay_r <= mvd_e_done_r;
end
//cache_left_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
cache_left_r <= 0;
else if(mvd_e_done_r) begin
if(mb_partition_i!=D_8x8)
cache_left_r <= mvd_encode_r;
else begin
case(mvd_idx_encode_r)
0, 1, 8, 9, 14: begin
cache_left_r <= mvd_encode_r;
end
2: begin
if(mb_sub_part_encode_r==D_L0_4x4)
cache_left_r <= mvd_encode_r;
else
cache_left_r <= cache_left_r;
end
3: begin
cache_left_r <= cache_top_r;
end
4, 12: begin
case(mb_sub_part_encode_r)
D_L0_4x4, D_L0_4x8: cache_left_r <= mvd_encode_r;
D_L0_8x4, D_L0_8x8: cache_left_r <= cache0_r;
default: cache_left_r <= cache_left_r;
endcase
end
5, 13: begin
if(mb_sub_part_encode_r==D_L0_4x4)
cache_left_r <= cache0_r;
else
cache_left_r <= cache_left_r;
end
6, 10: begin
if(mb_sub_part_encode_r==D_L0_4x4)
cache_left_r <= mvd_encode_r;
else
cache_left_r <= cache_left_r;
end
7: begin
cache_left_r <= cache0_r;
end
11: begin
cache_left_r <= mvd_top_r;
end
default: cache_left_r <= cache_left_r;
endcase
end
end
else
cache_left_r <= cache_left_r;
end
//cache_top_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
cache_top_r <= 0;
end
else if(mvd_e_done_r) begin
if(mb_partition_i!=D_8x8)
cache_top_r <= mvd_encode_r;
else begin
case(mvd_idx_encode_r)
0: begin
cache_top_r <= mvd_encode_r;
end
1: begin
cache_top_r <= cache_top_r;
end
2: begin
if(mb_sub_part_encode_r==D_L0_4x4)
cache_top_r <= cache_left_r;
else
cache_top_r <= mvd_encode_r;
end
3: begin
cache_top_r <= cache_left_r;
end
4: begin
if(mb_sub_part_encode_r==D_L0_8x8)
cache_top_r <= cache_top_r;
else
cache_top_r <= mvd_encode_r;
end
5: begin
if(mb_sub_part_encode_r==D_L0_4x4)
cache_top_r <= cache_top_r;
else
cache_top_r <= cache1_r;
end
6, 7: begin
cache_top_r <= cache1_r;
end
8: begin
if(mb_sub_part_encode_r==D_L0_4x4 || mb_sub_part_encode_r==D_L0_4x8) begin
if(mb_sub_partition_i[3:2]==D_L0_4x8)
cache_top_r <= cache1_r;
else
cache_top_r <= cache_left_r;
end
else if(mb_sub_part_encode_r==D_L0_8x4) begin
cache_top_r <= mvd_encode_r;
end
else begin
if(mb_sub_partition_i[3:2]==D_L0_4x8)
cache_top_r <= cache_left_r;
else
cache_top_r <= cache0_r;
end
end
9, 10: begin
if(mb_sub_part_encode_r==D_L0_4x4)
cache_top_r <= cache_left_r;
else
cache_top_r <= cache0_r;
end
11: begin
cache_top_r <= cache0_r;
end
12: begin
case(mb_sub_part_encode_r)
D_L0_4x4, D_L0_4x8: cache_top_r <= cache1_r;
default: cache_top_r <= mvd_encode_r;
endcase
end
13: begin
if(mb_sub_part_encode_r==D_L0_4x4)
cache_top_r <= cache_left_r;
else
cache_top_r <= cache_top_r;
end
14: begin
if(mb_sub_part_encode_r==D_L0_4x4)
cache_top_r <= cache0_r;
else
cache_top_r <= cache_top_r;
end
default:
cache_top_r <= cache_top_r;
endcase
end
end
else
cache_top_r <= cache_top_r;
end
//cache0_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
cache0_r <= 0;
end
else if(mvd_e_done_r) begin
if(mb_partition_i!=D_8x8)
cache0_r <= mvd_encode_r;
else begin
case(mvd_idx_encode_r)
0, 1, 2, 3, 11, 13: begin
cache0_r <= mvd_encode_r;
end
4: begin
case(mb_sub_part_encode_r)
D_L0_4x4, D_L0_4x8: cache0_r <= cache0_r;
default: cache0_r <= mvd_encode_r;
endcase
end
5: begin
if(mb_sub_part_encode_r==D_L0_4x4)
cache0_r <= cache1_r;
else
cache0_r <= mvd_encode_r;
end
6: begin
if(mb_sub_part_encode_r==D_L0_4x4)
cache0_r <= cache_left_r;
else
cache0_r <= mvd_encode_r;
end
7: begin
cache0_r <= cache_left_r;
end
8: begin
if(mb_sub_part_encode_r==D_L0_8x8)
cache0_r <= mvd_encode_r;
else begin
if(mb_sub_partition_i[3:2]==D_L0_4x8)
cache0_r <= cache_left_r;
else
cache0_r <= cache0_r;
end
end
9, 10, 12: begin
if(mb_sub_part_encode_r==D_L0_4x4)
cache0_r <= cache0_r;
else
cache0_r <= mvd_encode_r;
end
default:
cache0_r <= cache0_r;
endcase
end
end
else
cache0_r <= cache0_r;
end
//cache1_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
cache1_r <= 0;
end
else if(mvd_e_done_r) begin
if(mb_partition_i!=D_8x8)
cache1_r <= mvd_encode_r;
else begin
case(mvd_idx_encode_r)
0, 1, 2, 3, 7, 12, 13: begin
cache1_r <= mvd_encode_r;
end
4: begin
if(mb_sub_part_encode_r==D_L0_8x8)
cache1_r <= mvd_encode_r;
else
cache1_r <= cache_top_r;
end
5: begin
if(mb_sub_part_encode_r==D_L0_4x4)
cache1_r <= mvd_encode_r;
else
cache1_r <= cache0_r;
end
6: begin
if(mb_sub_part_encode_r==D_L0_4x4)
cache1_r <= cache0_r;
else
cache1_r <= mvd_encode_r;
end
8: begin
case(mb_sub_partition_i[3:2])
D_L0_4x4, D_L0_8x4: cache1_r <= cache1_r;
default: cache1_r <= cache0_r;
endcase
end
9, 10, 11: begin
cache1_r <= cache1_r;
end
default:
cache1_r <= cache1_r;
endcase
end
end
else
cache1_r <= cache1_r;
end
//encode mvd data when mvd_idx_encode_r is range from 0 to 15
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
mvd_encode_r <= 0;
else if(mvd_encode_done_r)
mvd_encode_r <= 0;
else if(mvd_e_done_r)
mvd_encode_r <= mvd_curr_r;
else
mvd_encode_r <= mvd_encode_r;
end
//left mvd
always @* begin
case(mvd_idx_encode_r)
0, 2, 8, 10: begin
if(mb_x_i==0)
mvd_left_r = 0;
else if(mvd_e_done_delay_r)
mvd_left_r = r_data_mvd_left_w;
else
mvd_left_r = r_data_mvd_left_r;
end
default: begin
mvd_left_r = cache_left_r;
end
endcase
end
//top mvd
always @* begin
case(mvd_idx_encode_r)
0, 1, 4, 5: begin
if(mb_y_i==0)
mvd_top_r = 0;
else if(mvd_e_done_delay_r)
mvd_top_r = r_data_mvd_top_w;
else
mvd_top_r = r_data_mvd_top_r;
end
default: begin
mvd_top_r = cache_top_r;
end
endcase
end
//one sub 8x8 block mvd done flag
always @* begin
if(mvd_e_done_r &&
( ((mb_sub_part_r==D_L0_8x8) && (mvd_8x8_sub_idx_r==0))
|| ((mb_sub_part_r==D_L0_8x4) && (mvd_8x8_sub_idx_r==2))
|| ((mb_sub_part_r==D_L0_4x8) && (mvd_8x8_sub_idx_r==1))
|| ((mb_sub_part_r==D_L0_4x4) && (mvd_8x8_sub_idx_r==3)) ) ) begin
mvd_8x8_done_r = 1'b1;
end
else begin
mvd_8x8_done_r = 1'b0;
end
end
//mb sub partition
always @* begin
case(mvd_8x8_idx_r)
0: mb_sub_part_r = mb_sub_partition_i[1:0];
1: mb_sub_part_r = mb_sub_partition_i[3:2];
2: mb_sub_part_r = mb_sub_partition_i[5:4];
3: mb_sub_part_r = mb_sub_partition_i[7:6];
default:
mb_sub_part_r = mb_sub_partition_i[1:0];
endcase
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
mb_sub_part_encode_r <= 0;
else if(mvd_e_done_r)
mb_sub_part_encode_r <= mb_sub_part_r;
else
mb_sub_part_encode_r <= mb_sub_part_encode_r;
end
//sum of abs mvd_left and abs mvd_top
always @* begin
if(~y_encode_flag_r)
abs_ref_mvd_r = mvd_x_left_w[(`FMV_WIDTH-1):0] + mvd_x_top_w[(`FMV_WIDTH-1):0];
else
abs_ref_mvd_r = mvd_y_left_w[(`FMV_WIDTH-1):0] + mvd_y_top_w[(`FMV_WIDTH-1):0];
end
//abs of mvd_x or mvd_y
always @* begin
if(~y_encode_flag_r)
abs_mvd_r = mvd_x_curr_w[(`FMV_WIDTH-1):0];
else
abs_mvd_r = mvd_y_curr_w[(`FMV_WIDTH-1):0];
end
wire [1:0] abs_ref_mvd_dec_w ; //decide the range of abs_ref_mvd_r
assign abs_ref_mvd_dec_w = (abs_ref_mvd_r>2) + (abs_ref_mvd_r>32);
reg [8:0] ctx_base ; //mvd_x : 40, mvd_y :47
reg [8:0] ctx_addr_mvd_r ; //real address of ctx addr mvd in memory
always @* begin
if(curr_state_i!=CABAC_mvd)
ctx_addr_mvd_r = 0;
if(~y_encode_flag_r) begin //mvd_x
ctx_addr_mvd_r = {3'd0, (5+abs_ref_mvd_dec_w)}; //40~42
end
else if(y_encode_flag_r) begin //mvd_y
ctx_addr_mvd_r = {3'd0, (8+abs_ref_mvd_dec_w)}; //47~49
end
else
ctx_addr_mvd_r = 0;
end
//context index of prefix
always @* begin
if(curr_state_i!=CABAC_mvd) begin
valid_num_bin_mvd_prefix_r = 0;
ctx_idx_mvd_0_r = 0;
ctx_idx_mvd_1_r = 0;
ctx_idx_mvd_2_r = 0;
ctx_idx_mvd_3_r = 0;
ctx_idx_mvd_4_r = 0;
ctx_idx_mvd_5_r = 0;
ctx_idx_mvd_6_r = 0;
ctx_idx_mvd_7_r = 0;
ctx_idx_mvd_8_r = 0;
bin_string_mvd_prefix_r = 0;
end
else if(prefix_encode_flag_r) begin
if(abs_mvd_r<9) begin
case(abs_mvd_r)
0: begin
bin_string_mvd_prefix_r = 9'b000000000;
ctx_idx_mvd_0_r = ctx_addr_mvd_r;
ctx_idx_mvd_1_r = 0;
ctx_idx_mvd_2_r = 0;
ctx_idx_mvd_3_r = 0;
ctx_idx_mvd_4_r = 0;
ctx_idx_mvd_5_r = 0;
ctx_idx_mvd_6_r = 0;
ctx_idx_mvd_7_r = 0;
ctx_idx_mvd_8_r = 0;
valid_num_bin_mvd_prefix_r = 1;
end
1: begin
bin_string_mvd_prefix_r = 9'b10_0000000;
ctx_idx_mvd_0_r = ctx_addr_mvd_r;
ctx_idx_mvd_1_r = y_encode_flag_r ? {3'd1, 6'd8} : {3'd1, 6'd7}; //47+3 : 40 + 3;
ctx_idx_mvd_2_r = 0;
ctx_idx_mvd_3_r = 0;
ctx_idx_mvd_4_r = 0;
ctx_idx_mvd_5_r = 0;
ctx_idx_mvd_6_r = 0;
ctx_idx_mvd_7_r = 0;
ctx_idx_mvd_8_r = 0;
valid_num_bin_mvd_prefix_r = (abs_mvd_r + 2);
end
2: begin
bin_string_mvd_prefix_r = 9'b110_000000;
ctx_idx_mvd_0_r = ctx_addr_mvd_r;
ctx_idx_mvd_1_r = y_encode_flag_r ? {3'd1, 6'd8} : {3'd1, 6'd7}; //47+3 : 40 + 3;
ctx_idx_mvd_2_r = y_encode_flag_r ? {3'd2, 6'd8} : {3'd2, 6'd6}; //47+4 : 40 + 4;
ctx_idx_mvd_3_r = 0;
ctx_idx_mvd_4_r = 0;
ctx_idx_mvd_5_r = 0;
ctx_idx_mvd_6_r = 0;
ctx_idx_mvd_7_r = 0;
ctx_idx_mvd_8_r = 0;
valid_num_bin_mvd_prefix_r = (abs_mvd_r + 2);
end
3: begin
bin_string_mvd_prefix_r = 9'b1110_00000;
ctx_idx_mvd_0_r = ctx_addr_mvd_r;
ctx_idx_mvd_1_r = y_encode_flag_r ? {3'd1, 6'd8} : {3'd1, 6'd7}; //47+3 : 40 + 3;
ctx_idx_mvd_2_r = y_encode_flag_r ? {3'd2, 6'd8} : {3'd2, 6'd6}; //47+4 : 40 + 4;
ctx_idx_mvd_3_r = y_encode_flag_r ? {3'd3, 6'd11} : {3'd3, 6'd10}; //47+5 : 40 + 5;
ctx_idx_mvd_4_r = 0;
ctx_idx_mvd_5_r = 0;
ctx_idx_mvd_6_r = 0;
ctx_idx_mvd_7_r = 0;
ctx_idx_mvd_8_r = 0;
valid_num_bin_mvd_prefix_r = (abs_mvd_r + 2);
end
4: begin
bin_string_mvd_prefix_r = 9'b11110_0000;
ctx_idx_mvd_0_r = ctx_addr_mvd_r;
ctx_idx_mvd_1_r = y_encode_flag_r ? {3'd1, 6'd8} : {3'd1, 6'd7}; //47+3 : 40 + 3;
ctx_idx_mvd_2_r = y_encode_flag_r ? {3'd2, 6'd8} : {3'd2, 6'd6}; //47+4 : 40 + 4;
ctx_idx_mvd_3_r = y_encode_flag_r ? {3'd3, 6'd11} : {3'd3, 6'd10}; //47+5 : 40 + 5;
ctx_idx_mvd_4_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_5_r = 0;
ctx_idx_mvd_6_r = 0;
ctx_idx_mvd_7_r = 0;
ctx_idx_mvd_8_r = 0;
valid_num_bin_mvd_prefix_r = (abs_mvd_r + 2);
end
5: begin
bin_string_mvd_prefix_r = 9'b111110_000;
ctx_idx_mvd_0_r = ctx_addr_mvd_r;
ctx_idx_mvd_1_r = y_encode_flag_r ? {3'd1, 6'd8} : {3'd1, 6'd7}; //47+3 : 40 + 3;
ctx_idx_mvd_2_r = y_encode_flag_r ? {3'd2, 6'd8} : {3'd2, 6'd6}; //47+4 : 40 + 4;
ctx_idx_mvd_3_r = y_encode_flag_r ? {3'd3, 6'd11} : {3'd3, 6'd10}; //47+5 : 40 + 5;
ctx_idx_mvd_4_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_5_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_6_r = 0;
ctx_idx_mvd_7_r = 0;
ctx_idx_mvd_8_r = 0;
valid_num_bin_mvd_prefix_r = (abs_mvd_r + 2);
end
6: begin
bin_string_mvd_prefix_r = 9'b1111110_00;
ctx_idx_mvd_0_r = ctx_addr_mvd_r;
ctx_idx_mvd_1_r = y_encode_flag_r ? {3'd1, 6'd8} : {3'd1, 6'd7}; //47+3 : 40 + 3;
ctx_idx_mvd_2_r = y_encode_flag_r ? {3'd2, 6'd8} : {3'd2, 6'd6}; //47+4 : 40 + 4;
ctx_idx_mvd_3_r = y_encode_flag_r ? {3'd3, 6'd11} : {3'd3, 6'd10}; //47+5 : 40 + 5;
ctx_idx_mvd_4_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_5_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_6_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_7_r = 0;
ctx_idx_mvd_8_r = 0;
valid_num_bin_mvd_prefix_r = (abs_mvd_r + 2);
end
7: begin
bin_string_mvd_prefix_r = 9'b11111110_0;
ctx_idx_mvd_0_r = ctx_addr_mvd_r;
ctx_idx_mvd_1_r = y_encode_flag_r ? {3'd1, 6'd8} : {3'd1, 6'd7}; //47+3 : 40 + 3;
ctx_idx_mvd_2_r = y_encode_flag_r ? {3'd2, 6'd8} : {3'd2, 6'd6}; //47+4 : 40 + 4;
ctx_idx_mvd_3_r = y_encode_flag_r ? {3'd3, 6'd11} : {3'd3, 6'd10}; //47+5 : 40 + 5;
ctx_idx_mvd_4_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_5_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_6_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_7_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_8_r = 0;
valid_num_bin_mvd_prefix_r = (abs_mvd_r + 2);
end
8: begin
bin_string_mvd_prefix_r = 9'b111111110;
ctx_idx_mvd_0_r = ctx_addr_mvd_r;
ctx_idx_mvd_1_r = y_encode_flag_r ? {3'd1, 6'd8} : {3'd1, 6'd7}; //47+3 : 40 + 3;
ctx_idx_mvd_2_r = y_encode_flag_r ? {3'd2, 6'd8} : {3'd2, 6'd6}; //47+4 : 40 + 4;
ctx_idx_mvd_3_r = y_encode_flag_r ? {3'd3, 6'd11} : {3'd3, 6'd10}; //47+5 : 40 + 5;
ctx_idx_mvd_4_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_5_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_6_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_7_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_8_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
valid_num_bin_mvd_prefix_r = (abs_mvd_r + 2);
end
default:
begin
bin_string_mvd_prefix_r = 0;
ctx_idx_mvd_0_r = 0;
ctx_idx_mvd_1_r = 0;
ctx_idx_mvd_2_r = 0;
ctx_idx_mvd_3_r = 0;
ctx_idx_mvd_4_r = 0;
ctx_idx_mvd_5_r = 0;
ctx_idx_mvd_6_r = 0;
ctx_idx_mvd_7_r = 0;
ctx_idx_mvd_8_r = 0;
valid_num_bin_mvd_prefix_r = 0;
end
endcase
end
else begin
bin_string_mvd_prefix_r = 9'b111111111;
ctx_idx_mvd_0_r = ctx_addr_mvd_r;
ctx_idx_mvd_1_r = y_encode_flag_r ? {3'd1, 6'd8} : {3'd1, 6'd7}; //47+3 : 40 + 3;
ctx_idx_mvd_2_r = y_encode_flag_r ? {3'd2, 6'd8} : {3'd2, 6'd6}; //47+4 : 40 + 4;
ctx_idx_mvd_3_r = y_encode_flag_r ? {3'd3, 6'd11} : {3'd3, 6'd10}; //47+5 : 40 + 5;
ctx_idx_mvd_4_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_5_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_6_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_7_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
ctx_idx_mvd_8_r = y_encode_flag_r ? {3'd2, 6'd9} : {3'd2, 6'd7}; //47+6 : 40 + 6;
valid_num_bin_mvd_prefix_r = 9;
end
end
else begin
bin_string_mvd_prefix_r = 0;
ctx_idx_mvd_0_r = 0;
ctx_idx_mvd_1_r = 0;
ctx_idx_mvd_2_r = 0;
ctx_idx_mvd_3_r = 0;
ctx_idx_mvd_4_r = 0;
ctx_idx_mvd_5_r = 0;
ctx_idx_mvd_6_r = 0;
ctx_idx_mvd_7_r = 0;
ctx_idx_mvd_8_r = 0;
valid_num_bin_mvd_prefix_r = 0;
end
end
always @* begin
mvd_bypass_length_r = (mvd_suffix_length_r + mvd_suffix_length_r + 4);
end
wire [`FMV_WIDTH:0] abs_mvd_minus1_w ;
wire [`FMV_WIDTH:0] abs_mvd_bypass_minus8_w ;
wire [`FMV_WIDTH:0] abs_mvd_bypass_minus24_w ;
wire [`FMV_WIDTH:0] abs_mvd_bypass_minus56_w ;
wire [`FMV_WIDTH:0] abs_mvd_bypass_minus120_w ;
wire [`FMV_WIDTH:0] abs_mvd_bypass_minus248_w ;
always @* begin
if(abs_mvd_minus1_w[7]) begin
mvd_suffix_length_r = 4;
end
else if(abs_mvd_minus1_w[6]) begin
mvd_suffix_length_r = 3;
end
else if(abs_mvd_minus1_w[5]) begin
mvd_suffix_length_r = 2;
end
else if(abs_mvd_minus1_w[4]) begin
mvd_suffix_length_r = 1;
end
else begin
mvd_suffix_length_r = 0;
end
end
assign abs_mvd_minus1_w = abs_mvd_r - 1;
assign abs_mvd_bypass_minus8_w = abs_mvd_r - 17;
assign abs_mvd_bypass_minus24_w = abs_mvd_r - 33;
assign abs_mvd_bypass_minus56_w = abs_mvd_r - 65;
assign abs_mvd_bypass_minus120_w = abs_mvd_r - 129;
assign abs_mvd_bypass_minus248_w = abs_mvd_r - 257;
always @* begin
case(mvd_bypass_length_r)
0: bin_string_mvd_suffix_r = 16'd0;
4: bin_string_mvd_suffix_r = {1'b0, abs_mvd_minus1_w[2:0], 12'd0};
6: bin_string_mvd_suffix_r = {2'b10, abs_mvd_bypass_minus8_w[3:0], 10'd0};
8: bin_string_mvd_suffix_r = {3'b110, abs_mvd_bypass_minus24_w[4:0], 8'd0 };
10: bin_string_mvd_suffix_r = {4'b1110, abs_mvd_bypass_minus56_w[5:0], 6'd0 };
12: bin_string_mvd_suffix_r = {5'b11110, abs_mvd_bypass_minus120_w[6:0], 4'd0 };
14: bin_string_mvd_suffix_r = {6'b111110, abs_mvd_bypass_minus248_w[7:0], 2'd0 };
default:
bin_string_mvd_suffix_r = 16'd0;
endcase
end
//valid_num_bin_mvd_r
always @* begin
if(curr_state_i!=CABAC_mvd)
valid_num_bin_mvd_r = 0;
else if(mvd_curr_state_r==MVD_IDLE)
valid_num_bin_mvd_r = 0;
else if(prefix_encode_flag_r) begin
if(abs_mvd_r>=9) begin
valid_num_bin_mvd_r = 9;
end
else begin
valid_num_bin_mvd_r = valid_num_bin_mvd_prefix_r;
end
end
else begin
if(abs_mvd_r<9)
valid_num_bin_mvd_r = 0;
else begin
case(mvd_bypass_length_r)
4: valid_num_bin_mvd_r = 5;
6: valid_num_bin_mvd_r = 7;
8: valid_num_bin_mvd_r = 9;
10: valid_num_bin_mvd_r = 11;
12: valid_num_bin_mvd_r = 13;
default:valid_num_bin_mvd_r = 0;
endcase
end
end
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
ctx_pair_mvd_0_o <= 0;
ctx_pair_mvd_1_o <= 0;
ctx_pair_mvd_2_o <= 0;
ctx_pair_mvd_3_o <= 0;
ctx_pair_mvd_4_o <= 0;
ctx_pair_mvd_5_o <= 0;
ctx_pair_mvd_6_o <= 0;
ctx_pair_mvd_7_o <= 0;
ctx_pair_mvd_8_o <= 0;
ctx_pair_mvd_8_o <= 0;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= 0;
end
else if(curr_state_i!=CABAC_mvd)
valid_num_bin_mvd_o <= 0;
else if(mvd_curr_state_r==MVD_IDLE)
valid_num_bin_mvd_o <= 0;
else if(mvd_encode_done_r)
valid_num_bin_mvd_o <= 0;
else if(prefix_encode_flag_r) begin
if(abs_mvd_r>=9) begin
ctx_pair_mvd_0_o <= ctx_pair_mvd_prefix_0_w;
ctx_pair_mvd_1_o <= ctx_pair_mvd_prefix_1_w;
ctx_pair_mvd_2_o <= ctx_pair_mvd_prefix_2_w;
ctx_pair_mvd_3_o <= ctx_pair_mvd_prefix_3_w;
ctx_pair_mvd_4_o <= ctx_pair_mvd_prefix_4_w;
ctx_pair_mvd_5_o <= ctx_pair_mvd_prefix_5_w;
ctx_pair_mvd_6_o <= ctx_pair_mvd_prefix_6_w;
ctx_pair_mvd_7_o <= ctx_pair_mvd_prefix_7_w;
ctx_pair_mvd_8_o <= ctx_pair_mvd_prefix_8_w;
ctx_pair_mvd_9_o <= 0;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= 9;
end
else begin
case(abs_mvd_r)
0: begin
ctx_pair_mvd_0_o <= ctx_pair_mvd_prefix_0_w;
ctx_pair_mvd_1_o <= 0;
ctx_pair_mvd_2_o <= 0;
ctx_pair_mvd_3_o <= 0;
ctx_pair_mvd_4_o <= 0;
ctx_pair_mvd_5_o <= 0;
ctx_pair_mvd_6_o <= 0;
ctx_pair_mvd_7_o <= 0;
ctx_pair_mvd_8_o <= 0;
ctx_pair_mvd_9_o <= 0;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= valid_num_bin_mvd_prefix_r;
end
1: begin
ctx_pair_mvd_0_o <= ctx_pair_mvd_prefix_0_w;
ctx_pair_mvd_1_o <= ctx_pair_mvd_prefix_1_w;
ctx_pair_mvd_2_o <= ctx_pair_mvd_bypass_w;
ctx_pair_mvd_3_o <= 0;
ctx_pair_mvd_4_o <= 0;
ctx_pair_mvd_5_o <= 0;
ctx_pair_mvd_6_o <= 0;
ctx_pair_mvd_7_o <= 0;
ctx_pair_mvd_8_o <= 0;
ctx_pair_mvd_9_o <= 0;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= valid_num_bin_mvd_prefix_r;
end
2: begin
ctx_pair_mvd_0_o <= ctx_pair_mvd_prefix_0_w;
ctx_pair_mvd_1_o <= ctx_pair_mvd_prefix_1_w;
ctx_pair_mvd_2_o <= ctx_pair_mvd_prefix_2_w;
ctx_pair_mvd_3_o <= ctx_pair_mvd_bypass_w;
ctx_pair_mvd_4_o <= 0;
ctx_pair_mvd_5_o <= 0;
ctx_pair_mvd_6_o <= 0;
ctx_pair_mvd_7_o <= 0;
ctx_pair_mvd_8_o <= 0;
ctx_pair_mvd_9_o <= 0;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= valid_num_bin_mvd_prefix_r;
end
3: begin
ctx_pair_mvd_0_o <= ctx_pair_mvd_prefix_0_w;
ctx_pair_mvd_1_o <= ctx_pair_mvd_prefix_1_w;
ctx_pair_mvd_2_o <= ctx_pair_mvd_prefix_2_w;
ctx_pair_mvd_3_o <= ctx_pair_mvd_prefix_3_w;
ctx_pair_mvd_4_o <= ctx_pair_mvd_bypass_w;
ctx_pair_mvd_5_o <= 0;
ctx_pair_mvd_6_o <= 0;
ctx_pair_mvd_7_o <= 0;
ctx_pair_mvd_8_o <= 0;
ctx_pair_mvd_9_o <= 0;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= valid_num_bin_mvd_prefix_r;
end
4: begin
ctx_pair_mvd_0_o <= ctx_pair_mvd_prefix_0_w;
ctx_pair_mvd_1_o <= ctx_pair_mvd_prefix_1_w;
ctx_pair_mvd_2_o <= ctx_pair_mvd_prefix_2_w;
ctx_pair_mvd_3_o <= ctx_pair_mvd_prefix_3_w;
ctx_pair_mvd_4_o <= ctx_pair_mvd_prefix_4_w;
ctx_pair_mvd_5_o <= ctx_pair_mvd_bypass_w;
ctx_pair_mvd_6_o <= 0;
ctx_pair_mvd_7_o <= 0;
ctx_pair_mvd_8_o <= 0;
ctx_pair_mvd_9_o <= 0;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= valid_num_bin_mvd_prefix_r;
end
5: begin
ctx_pair_mvd_0_o <= ctx_pair_mvd_prefix_0_w;
ctx_pair_mvd_1_o <= ctx_pair_mvd_prefix_1_w;
ctx_pair_mvd_2_o <= ctx_pair_mvd_prefix_2_w;
ctx_pair_mvd_3_o <= ctx_pair_mvd_prefix_3_w;
ctx_pair_mvd_4_o <= ctx_pair_mvd_prefix_4_w;
ctx_pair_mvd_5_o <= ctx_pair_mvd_prefix_5_w;
ctx_pair_mvd_6_o <= ctx_pair_mvd_bypass_w;
ctx_pair_mvd_7_o <= 0;
ctx_pair_mvd_8_o <= 0;
ctx_pair_mvd_9_o <= 0;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= valid_num_bin_mvd_prefix_r;
end
6: begin
ctx_pair_mvd_0_o <= ctx_pair_mvd_prefix_0_w;
ctx_pair_mvd_1_o <= ctx_pair_mvd_prefix_1_w;
ctx_pair_mvd_2_o <= ctx_pair_mvd_prefix_2_w;
ctx_pair_mvd_3_o <= ctx_pair_mvd_prefix_3_w;
ctx_pair_mvd_4_o <= ctx_pair_mvd_prefix_4_w;
ctx_pair_mvd_5_o <= ctx_pair_mvd_prefix_5_w;
ctx_pair_mvd_6_o <= ctx_pair_mvd_prefix_6_w;
ctx_pair_mvd_7_o <= ctx_pair_mvd_bypass_w;
ctx_pair_mvd_8_o <= 0;
ctx_pair_mvd_9_o <= 0;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= valid_num_bin_mvd_prefix_r;
end
7: begin
ctx_pair_mvd_0_o <= ctx_pair_mvd_prefix_0_w;
ctx_pair_mvd_1_o <= ctx_pair_mvd_prefix_1_w;
ctx_pair_mvd_2_o <= ctx_pair_mvd_prefix_2_w;
ctx_pair_mvd_3_o <= ctx_pair_mvd_prefix_3_w;
ctx_pair_mvd_4_o <= ctx_pair_mvd_prefix_4_w;
ctx_pair_mvd_5_o <= ctx_pair_mvd_prefix_5_w;
ctx_pair_mvd_6_o <= ctx_pair_mvd_prefix_6_w;
ctx_pair_mvd_7_o <= ctx_pair_mvd_prefix_7_w;
ctx_pair_mvd_8_o <= ctx_pair_mvd_bypass_w;
ctx_pair_mvd_9_o <= 0;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= valid_num_bin_mvd_prefix_r;
end
8: begin
ctx_pair_mvd_0_o <= ctx_pair_mvd_prefix_0_w;
ctx_pair_mvd_1_o <= ctx_pair_mvd_prefix_1_w;
ctx_pair_mvd_2_o <= ctx_pair_mvd_prefix_2_w;
ctx_pair_mvd_3_o <= ctx_pair_mvd_prefix_3_w;
ctx_pair_mvd_4_o <= ctx_pair_mvd_prefix_4_w;
ctx_pair_mvd_5_o <= ctx_pair_mvd_prefix_5_w;
ctx_pair_mvd_6_o <= ctx_pair_mvd_prefix_6_w;
ctx_pair_mvd_7_o <= ctx_pair_mvd_prefix_7_w;
ctx_pair_mvd_8_o <= ctx_pair_mvd_prefix_8_w;
ctx_pair_mvd_9_o <= ctx_pair_mvd_bypass_w;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= valid_num_bin_mvd_prefix_r;
end
default: begin
ctx_pair_mvd_0_o <= 0;
ctx_pair_mvd_1_o <= 0;
ctx_pair_mvd_2_o <= 0;
ctx_pair_mvd_3_o <= 0;
ctx_pair_mvd_4_o <= 0;
ctx_pair_mvd_5_o <= 0;
ctx_pair_mvd_6_o <= 0;
ctx_pair_mvd_7_o <= 0;
ctx_pair_mvd_8_o <= 0;
ctx_pair_mvd_9_o <= 0;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= 0;
end
endcase
end
end
else if(~prefix_encode_flag_r) begin
if(abs_mvd_r<9) begin
ctx_pair_mvd_0_o <= 0;
ctx_pair_mvd_1_o <= 0;
ctx_pair_mvd_2_o <= 0;
ctx_pair_mvd_3_o <= 0;
ctx_pair_mvd_4_o <= 0;
ctx_pair_mvd_5_o <= 0;
ctx_pair_mvd_6_o <= 0;
ctx_pair_mvd_7_o <= 0;
ctx_pair_mvd_8_o <= 0;
ctx_pair_mvd_9_o <= 0;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= 0;
end
else begin
case(mvd_bypass_length_r)
4: begin
ctx_pair_mvd_0_o <= {2'b01, bin_string_mvd_suffix_r[15], 9'd511};
ctx_pair_mvd_1_o <= {2'b01, bin_string_mvd_suffix_r[14], 9'd511};
ctx_pair_mvd_2_o <= {2'b01, bin_string_mvd_suffix_r[13], 9'd511};
ctx_pair_mvd_3_o <= {2'b01, bin_string_mvd_suffix_r[12], 9'd511};
ctx_pair_mvd_4_o <= ctx_pair_mvd_bypass_w;
ctx_pair_mvd_5_o <= 0;
ctx_pair_mvd_6_o <= 0;
ctx_pair_mvd_7_o <= 0;
ctx_pair_mvd_8_o <= 0;
ctx_pair_mvd_9_o <= 0;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= 5;
end
6: begin
ctx_pair_mvd_0_o <= {2'b01, bin_string_mvd_suffix_r[15], 9'd511};
ctx_pair_mvd_1_o <= {2'b01, bin_string_mvd_suffix_r[14], 9'd511};
ctx_pair_mvd_2_o <= {2'b01, bin_string_mvd_suffix_r[13], 9'd511};
ctx_pair_mvd_3_o <= {2'b01, bin_string_mvd_suffix_r[12], 9'd511};
ctx_pair_mvd_4_o <= {2'b01, bin_string_mvd_suffix_r[11], 9'd511};
ctx_pair_mvd_5_o <= {2'b01, bin_string_mvd_suffix_r[10], 9'd511};
ctx_pair_mvd_6_o <= ctx_pair_mvd_bypass_w;
ctx_pair_mvd_7_o <= 0;
ctx_pair_mvd_8_o <= 0;
ctx_pair_mvd_9_o <= 0;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= 7;
end
8: begin
ctx_pair_mvd_0_o <= {2'b01, bin_string_mvd_suffix_r[15], 9'd511};
ctx_pair_mvd_1_o <= {2'b01, bin_string_mvd_suffix_r[14], 9'd511};
ctx_pair_mvd_2_o <= {2'b01, bin_string_mvd_suffix_r[13], 9'd511};
ctx_pair_mvd_3_o <= {2'b01, bin_string_mvd_suffix_r[12], 9'd511};
ctx_pair_mvd_4_o <= {2'b01, bin_string_mvd_suffix_r[11], 9'd511};
ctx_pair_mvd_5_o <= {2'b01, bin_string_mvd_suffix_r[10], 9'd511};
ctx_pair_mvd_6_o <= {2'b01, bin_string_mvd_suffix_r[9], 9'd511};
ctx_pair_mvd_7_o <= {2'b01, bin_string_mvd_suffix_r[8], 9'd511};
ctx_pair_mvd_8_o <= ctx_pair_mvd_bypass_w;
ctx_pair_mvd_9_o <= 0;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= 9;
end
10: begin
ctx_pair_mvd_0_o <= {2'b01, bin_string_mvd_suffix_r[15], 9'd511};
ctx_pair_mvd_1_o <= {2'b01, bin_string_mvd_suffix_r[14], 9'd511};
ctx_pair_mvd_2_o <= {2'b01, bin_string_mvd_suffix_r[13], 9'd511};
ctx_pair_mvd_3_o <= {2'b01, bin_string_mvd_suffix_r[12], 9'd511};
ctx_pair_mvd_4_o <= {2'b01, bin_string_mvd_suffix_r[11], 9'd511};
ctx_pair_mvd_5_o <= {2'b01, bin_string_mvd_suffix_r[10], 9'd511};
ctx_pair_mvd_6_o <= {2'b01, bin_string_mvd_suffix_r[9], 9'd511};
ctx_pair_mvd_7_o <= {2'b01, bin_string_mvd_suffix_r[8], 9'd511};
ctx_pair_mvd_8_o <= {2'b01, bin_string_mvd_suffix_r[7], 9'd511};
ctx_pair_mvd_9_o <= {2'b01, bin_string_mvd_suffix_r[6], 9'd511};
ctx_pair_mvd_10_o <= ctx_pair_mvd_bypass_w;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= 11;
end
12: begin
ctx_pair_mvd_0_o <= {2'b01, bin_string_mvd_suffix_r[15], 9'd511};
ctx_pair_mvd_1_o <= {2'b01, bin_string_mvd_suffix_r[14], 9'd511};
ctx_pair_mvd_2_o <= {2'b01, bin_string_mvd_suffix_r[13], 9'd511};
ctx_pair_mvd_3_o <= {2'b01, bin_string_mvd_suffix_r[12], 9'd511};
ctx_pair_mvd_4_o <= {2'b01, bin_string_mvd_suffix_r[11], 9'd511};
ctx_pair_mvd_5_o <= {2'b01, bin_string_mvd_suffix_r[10], 9'd511};
ctx_pair_mvd_6_o <= {2'b01, bin_string_mvd_suffix_r[9], 9'd511};
ctx_pair_mvd_7_o <= {2'b01, bin_string_mvd_suffix_r[8], 9'd511};
ctx_pair_mvd_8_o <= {2'b01, bin_string_mvd_suffix_r[7], 9'd511};
ctx_pair_mvd_9_o <= {2'b01, bin_string_mvd_suffix_r[6], 9'd511};
ctx_pair_mvd_10_o <= {2'b01, bin_string_mvd_suffix_r[5], 9'd511};
ctx_pair_mvd_11_o <= {2'b01, bin_string_mvd_suffix_r[4], 9'd511};
ctx_pair_mvd_12_o <= ctx_pair_mvd_bypass_w;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= 13;
end
default: begin
ctx_pair_mvd_0_o <= 0;
ctx_pair_mvd_1_o <= 0;
ctx_pair_mvd_2_o <= 0;
ctx_pair_mvd_3_o <= 0;
ctx_pair_mvd_4_o <= 0;
ctx_pair_mvd_5_o <= 0;
ctx_pair_mvd_6_o <= 0;
ctx_pair_mvd_7_o <= 0;
ctx_pair_mvd_8_o <= 0;
ctx_pair_mvd_9_o <= 0;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= 0;
end
endcase
end
end
else begin
ctx_pair_mvd_0_o <= 0;
ctx_pair_mvd_1_o <= 0;
ctx_pair_mvd_2_o <= 0;
ctx_pair_mvd_3_o <= 0;
ctx_pair_mvd_4_o <= 0;
ctx_pair_mvd_5_o <= 0;
ctx_pair_mvd_6_o <= 0;
ctx_pair_mvd_7_o <= 0;
ctx_pair_mvd_8_o <= 0;
ctx_pair_mvd_9_o <= 0;
ctx_pair_mvd_10_o <= 0;
ctx_pair_mvd_11_o <= 0;
ctx_pair_mvd_12_o <= 0;
ctx_pair_mvd_13_o <= 0;
ctx_pair_mvd_14_o <= 0;
ctx_pair_mvd_15_o <= 0;
valid_num_bin_mvd_o <= 0;
end
end
// ********************************************
//
// Sequential Logic
//
// ********************************************
//mvd done flag
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
mvd_done_o <= 0;
else if(curr_state_i==CABAC_mvd && write_cyc_num_r==7)
mvd_done_o <= 1;
else
mvd_done_o <= 0;
end
//mvd encode done flag
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
mvd_encode_done_r <= 0;
else if((mvd_curr_state_r==MVD_ENCODE) && (mb_partition_i!=D_8x8) && mvd_e_done_r) begin
case(mb_partition_i)
D_16x16: begin
if(mvd_idx_encode_r==0 && mvd_idx_r==1)
mvd_encode_done_r <= 1;
else
mvd_encode_done_r <= 0;
end
D_16x8: begin
if(mvd_idx_encode_r==8)
mvd_encode_done_r <= 1;
else
mvd_encode_done_r <= 0;
end
D_8x16: begin
if(mvd_idx_encode_r==4)
mvd_encode_done_r <= 1;
else
mvd_encode_done_r <= 0;
end
default: begin
mvd_encode_done_r <= 0;
end
endcase
end
else if((mvd_curr_state_r==MVD_ENCODE) && (mb_partition_i==D_8x8) && (mvd_8x8_idx_encode_r==3) && mvd_e_done_r) begin
case(mb_sub_part_encode_r)
D_L0_8x8: begin
if(mvd_idx_encode_r==12)
mvd_encode_done_r <= 1;
else
mvd_encode_done_r <= 0;
end
D_L0_8x4: begin
if(mvd_idx_encode_r==14)
mvd_encode_done_r <= 1;
else
mvd_encode_done_r <= 0;
end
D_L0_4x8: begin
if(mvd_idx_encode_r==13)
mvd_encode_done_r <= 1;
else
mvd_encode_done_r <= 0;
end
D_L0_4x4: begin
if(mvd_idx_encode_r==15)
mvd_encode_done_r <= 1;
else
mvd_encode_done_r <= 0;
end
default: begin
mvd_encode_done_r <= 0;
end
endcase
end
else if(curr_state_i!=CABAC_mvd)
mvd_encode_done_r <= 0;
else
mvd_encode_done_r <= mvd_encode_done_r;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
mvd_idx_encode_r <= 0;
else if(mvd_encode_done_r)
mvd_idx_encode_r <= 0;
else if(mvd_e_done_r)
mvd_idx_encode_r <= mvd_idx_r;
else
mvd_idx_encode_r <= mvd_idx_encode_r;
end
//mvd index of sub block
always@(posedge clk or negedge rst_n) begin
if(!rst_n)begin
mvd_idx_0_r <= 0;
end
else if(curr_state_i!=CABAC_mvd)
mvd_idx_0_r <= 0;
else if(mvd_encode_done_r)begin
case(write_cyc_num_r)
0: begin mvd_idx_0_r <= 5; end
1: begin mvd_idx_0_r <= 7; end
2: begin mvd_idx_0_r <= 13; end
3: begin mvd_idx_0_r <= 15; end
4: begin mvd_idx_0_r <= 14; end
5: begin mvd_idx_0_r <= 11; end
6: begin mvd_idx_0_r <= 10; end
default:
begin mvd_idx_0_r <= 0; end
endcase
end
else begin
case(mb_partition_i)
D_16x16 : begin
if(mvd_e_done_r)
mvd_idx_0_r <= 1;
else
mvd_idx_0_r <= mvd_idx_0_r;
end
D_16x8 : begin
if(mvd_e_done_r) begin
mvd_idx_0_r <= 8;
end
else begin
mvd_idx_0_r <= mvd_idx_0_r;
end
end
D_8x16 : begin
if(mvd_e_done_r) begin
mvd_idx_0_r <= 4;
end
else begin
mvd_idx_0_r <= mvd_idx_0_r;
end
end
default:
mvd_idx_0_r <= 0;
endcase
end
end
always @* begin
if(curr_state_i!=CABAC_mvd)
mvd_idx_r = 0;
else if(mvd_encode_done_r)
mvd_idx_r = mvd_idx_0_r;
else
mvd_idx_r = mb_partition_i==D_8x8 ? ((mvd_8x8_idx_r<<2) + mvd_8x8_sub_idx_r) : mvd_idx_0_r;
end
//mvd index of 8x8 block reading
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
mvd_8x8_idx_r <= 0;
end
else if(curr_state_i!=CABAC_mvd)
mvd_8x8_idx_r <= 0;
else if(mvd_encode_done_r) begin
mvd_8x8_idx_r <= 0;
end
else if(mvd_8x8_done_r) begin
if(mvd_8x8_idx_r==3) begin
mvd_8x8_idx_r <= 0;
end
else begin
mvd_8x8_idx_r <= mvd_8x8_idx_r + 1;
end
end
else begin
mvd_8x8_idx_r <= mvd_8x8_idx_r;
end
end
//mvd index of 8x8 block encoding
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
mvd_8x8_idx_encode_r <= 0;
else if(mvd_e_done_r)
mvd_8x8_idx_encode_r <= mvd_8x8_idx_r;
else
mvd_8x8_idx_encode_r <= mvd_8x8_idx_encode_r;
end
//mvd sub_idx of 4x4 block
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
mvd_8x8_sub_idx_r <= 0;
else if(curr_state_i!=CABAC_mvd)
mvd_8x8_sub_idx_r <= 0;
else if(mvd_encode_done_r)
mvd_8x8_sub_idx_r <= 0;
else if(mvd_idx_r==0 && mvd_idx_encode_r>0)
mvd_8x8_sub_idx_r <= 0;
else begin
case(mb_sub_part_r)
D_L0_8x8: begin
mvd_8x8_sub_idx_r <= 0;
end
D_L0_8x4: begin
if(mvd_e_done_r) begin
if(mvd_8x8_sub_idx_r==2)
mvd_8x8_sub_idx_r <= 0;
else
mvd_8x8_sub_idx_r <= 2;
end
else
mvd_8x8_sub_idx_r <= mvd_8x8_sub_idx_r;
end
D_L0_4x8: begin
if(mvd_e_done_r) begin
if(mvd_8x8_sub_idx_r==1)
mvd_8x8_sub_idx_r <= 0;
else
mvd_8x8_sub_idx_r <= 1;
end
else
mvd_8x8_sub_idx_r <= mvd_8x8_sub_idx_r;
end
D_L0_4x4: begin
if(mvd_e_done_r) begin
if(mvd_8x8_sub_idx_r==3)
mvd_8x8_sub_idx_r <= 0;
else
mvd_8x8_sub_idx_r <= mvd_8x8_sub_idx_r + 1;
end
else
mvd_8x8_sub_idx_r <= mvd_8x8_sub_idx_r;
end
default: begin
mvd_8x8_sub_idx_r <= mvd_8x8_sub_idx_r;
end
endcase
end
end
//neighbour infor
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
write_cyc_num_r <= 0;
else if(curr_state_i!=CABAC_mvd)
write_cyc_num_r <= 0;
else if(write_cyc_num_r==8)
write_cyc_num_r <= 0;
else if(mvd_encode_done_r)
write_cyc_num_r <= write_cyc_num_r + 1;
else
write_cyc_num_r <= write_cyc_num_r;
end
//left
assign r_mvd_left_en_w = r_mvd_left_en_r ;
assign w_mvd_left_en_w = w_mvd_left_en_r ;
assign r_addr_mvd_left_w = r_addr_mvd_left_r ;
assign w_addr_mvd_left_w = w_addr_mvd_left_r ;
assign w_data_mvd_left_w = w_data_mvd_left_r ;
//left read
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
r_data_mvd_left_r <= 0;
else if(mvd_e_done_delay_r)
r_data_mvd_left_r <= r_data_mvd_left_w;
else
r_data_mvd_left_r <= r_data_mvd_left_r;
end
//read left enable and address
always @* begin
if(curr_state_i!=CABAC_mvd) begin
r_mvd_left_en_r = 0;
r_addr_mvd_left_r = 0;
end
else if(mvd_curr_state_r==MVD_IDLE) begin //0
r_mvd_left_en_r = 1;
r_addr_mvd_left_r = 0;
end
else if(mvd_e_done_r) begin
if(mb_partition_i!=D_8x8) begin
if(mb_partition_i==D_16x8) begin //8
r_mvd_left_en_r = 1;
r_addr_mvd_left_r = 2;
end
else begin
r_mvd_left_en_r = 0;
r_addr_mvd_left_r = 0;
end
end
else if(mb_partition_i==D_8x8) begin
if(mb_sub_partition_i[1:0]==D_L0_4x4 && mvd_idx_encode_r==1) begin //2
r_mvd_left_en_r = 1;
r_addr_mvd_left_r = 1;
end
else if(mb_sub_partition_i[1:0]==D_L0_8x4 && mvd_idx_encode_r==0) begin //2
r_mvd_left_en_r = 1;
r_addr_mvd_left_r = 1;
end
else if(mb_sub_partition_i[3:2]==D_L0_4x4 && mvd_idx_encode_r==7) begin //8
r_mvd_left_en_r = 1;
r_addr_mvd_left_r = 2;
end
else if(mb_sub_partition_i[3:2]==D_L0_8x4 && mvd_idx_encode_r==6) begin
r_mvd_left_en_r = 1;
r_addr_mvd_left_r = 2;
end
else if(mb_sub_partition_i[3:2]==D_L0_4x8 && mvd_idx_encode_r==5) begin
r_mvd_left_en_r = 1;
r_addr_mvd_left_r = 2;
end
else if(mb_sub_partition_i[3:2]==D_L0_8x8 && mvd_idx_encode_r==4) begin
r_mvd_left_en_r = 1;
r_addr_mvd_left_r = 2;
end
else if(mb_sub_partition_i[5:4]==D_L0_4x4 && mvd_idx_encode_r==9) begin //10
r_mvd_left_en_r = 1;
r_addr_mvd_left_r = 3;
end
else if(mb_sub_partition_i[5:4]==D_L0_8x4 && mvd_idx_encode_r==8) begin
r_mvd_left_en_r = 1;
r_addr_mvd_left_r = 3;
end
else begin
r_mvd_left_en_r = 0;
r_addr_mvd_left_r = 0;
end
end
else begin
r_mvd_left_en_r = 0;
r_addr_mvd_left_r = 0;
end
end
else begin
r_mvd_left_en_r = 0;
r_addr_mvd_left_r = 0;
end
end
//left write
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
w_mvd_left_en_r <= 0;
else if(curr_state_i==CABAC_mvd && write_cyc_num_r>=1 && write_cyc_num_r<=4)
w_mvd_left_en_r <= 1;
else
w_mvd_left_en_r <= 0;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
w_addr_mvd_left_r <= 0;
else if(w_addr_mvd_left_r==3)
w_addr_mvd_left_r <= 0;
else if(w_mvd_left_en_r && write_cyc_num_r>=2 && write_cyc_num_r<=4)
w_addr_mvd_left_r <= w_addr_mvd_left_r + 1;
else
w_addr_mvd_left_r <= 0;
end
always @* begin
w_data_mvd_left_r = mvd_curr_r;
end
//top
assign r_mvd_top_en_w = r_mvd_top_en_r ;
assign w_mvd_top_en_w = w_mvd_top_en_r ;
assign r_addr_mvd_top_w = r_addr_mvd_top_r ;
assign w_addr_mvd_top_w = w_addr_mvd_top_r ;
assign w_data_mvd_top_w = w_data_mvd_top_r ;
//top read
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
r_data_mvd_top_r <= 0;
else if(mvd_e_done_delay_r)
r_data_mvd_top_r <= r_data_mvd_top_w;
else
r_data_mvd_top_r <= r_data_mvd_top_r;
end
wire [8:0] r_addr_mvd_top_base_w ;
assign r_addr_mvd_top_base_w = (mb_x_i << 2);
//read top enable and address
always @* begin
if(curr_state_i!=CABAC_mvd) begin
r_mvd_top_en_r = 0;
r_addr_mvd_top_r = 0;
end
else if(mvd_curr_state_r==MVD_IDLE) begin
r_mvd_top_en_r = 1;
r_addr_mvd_top_r = r_addr_mvd_top_base_w;
end
else if(mvd_e_done_r) begin
if(mb_partition_i!=D_8x8) begin
if(mb_partition_i==D_8x16) begin
r_mvd_top_en_r = 1;
r_addr_mvd_top_r = r_addr_mvd_top_base_w + 2;
end
else begin
r_mvd_top_en_r = 0;
r_addr_mvd_top_r = 0;
end
end
else if(mb_partition_i==D_8x8) begin
if((mb_sub_partition_i[1:0]==D_L0_4x4 || mb_sub_partition_i[1:0]==D_L0_4x8) && mvd_idx_encode_r==0) begin
r_mvd_top_en_r = 1;
r_addr_mvd_top_r = r_addr_mvd_top_base_w + 1;
end
else if(mb_sub_partition_i[1:0]==D_L0_4x4 && mvd_idx_encode_r==3) begin
r_mvd_top_en_r = 1;
r_addr_mvd_top_r = r_addr_mvd_top_base_w + 2;
end
else if(mb_sub_partition_i[1:0]==D_L0_4x8 && mvd_idx_encode_r==1) begin
r_mvd_top_en_r = 1;
r_addr_mvd_top_r = r_addr_mvd_top_base_w + 2;
end
else if(mb_sub_partition_i[1:0]==D_L0_8x4 && mvd_idx_encode_r==2) begin
r_mvd_top_en_r = 1;
r_addr_mvd_top_r = r_addr_mvd_top_base_w + 2;
end
else if(mb_sub_partition_i[1:0]==D_L0_8x8 && mvd_idx_encode_r==0) begin
r_mvd_top_en_r = 1;
r_addr_mvd_top_r = r_addr_mvd_top_base_w + 2;
end
else if((mb_sub_partition_i[3:2]==D_L0_4x4 || mb_sub_partition_i[3:2]==D_L0_4x8) && mvd_idx_encode_r==4) begin
r_mvd_top_en_r = 1;
r_addr_mvd_top_r = r_addr_mvd_top_base_w + 3;
end
else begin
r_mvd_top_en_r = 0;
r_addr_mvd_top_r = 0;
end
end
else begin
r_mvd_top_en_r = 0;
r_addr_mvd_top_r = 0;
end
end
else begin
r_mvd_top_en_r = 0;
r_addr_mvd_top_r = 0;
end
end
//top write
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
w_mvd_top_en_r <= 0;
else if(curr_state_i==CABAC_mvd && (write_cyc_num_r>=4 && write_cyc_num_r<=7))
w_mvd_top_en_r <= 1;
else
w_mvd_top_en_r <= 0;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
w_addr_mvd_top_r <= 0;
else if(write_cyc_num_r==8)
w_addr_mvd_top_r <= 0;
else begin
case(write_cyc_num_r)
7: begin w_addr_mvd_top_r <= r_addr_mvd_top_base_w; end
6: begin w_addr_mvd_top_r <= r_addr_mvd_top_base_w + 1; end
5: begin w_addr_mvd_top_r <= r_addr_mvd_top_base_w + 2; end
4: begin w_addr_mvd_top_r <= r_addr_mvd_top_base_w + 3; end
default:
begin w_addr_mvd_top_r <= r_addr_mvd_top_base_w; end
endcase
end
end
always @* begin
w_data_mvd_top_r = mvd_curr_r;
end
// ********************************************
//
// Sub Block
//
// ********************************************
cabac_mvd_left_2p_18x4 cabac_mvd_left_2p_18x4_u0(
.clk (clk ),
.r_en (r_mvd_left_en_w ),
.r_addr (r_addr_mvd_left_w ),
.r_data (r_data_mvd_left_w ),
.w_en (w_mvd_left_en_w ),
.w_addr (w_addr_mvd_left_w ),
.w_data (w_data_mvd_left_w )
);
cabac_mvd_top_2p_18xMB_X_TOTAL cabac_mvd_top_2p_18xMB_X_TOTAL_u0(
.clk (clk ),
.r_en (r_mvd_top_en_w ),
.r_addr (r_addr_mvd_top_w ),
.r_data (r_data_mvd_top_w ),
.w_en (w_mvd_top_en_w ),
.w_addr (w_addr_mvd_top_w ),
.w_data (w_data_mvd_top_w )
);
endmodule |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_async_edgelogic.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_async_edgelogic(/*AUTOARG*/
// Outputs
to_pad,
// Inputs
data
);
//////////////////////////////////////////////////////////////////////////
// INPUTS
//////////////////////////////////////////////////////////////////////////
input data;
//////////////////////////////////////////////////////////////////////////
// OUTPUTS
//////////////////////////////////////////////////////////////////////////
output to_pad;
//////////////////////////////////////////////////////////////////////////
// CODE
//////////////////////////////////////////////////////////////////////////
wire n0 = data;
assign to_pad = n0;
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012, Ameer M. Abdelhadi; [email protected]. All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// bin2bcd.v: Parametric Binary to BCD Converter //
// Using Double Dabble / Shift and Add 3 Algorithm //
// //
// Ameer M.S. Abdelhadi ([email protected]; [email protected]), Sept. 2012 //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// 18-bit Example //
// //
// B B B B B B B B B B B B B B B B B B //
// I I I I I I I I I I I I I I I I I I //
// N N N N N N N N N N N N N N N N N N //
// 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 //
// '0 '0 '0 '0 '0 7 6 5 4 3 2 1 0 | | | | | | | | | | //
// | | | | | | | | | | | | | | | | | | | | | | | //
// | | | | V__V__V__V | | | | | | | | | | | | | | | //
// | | | | /IF>4THEN+3\ | | | | | | | | | | | | | | | //
// | | | | \__________/ | | | | | | | | | | | | | | | //
// | | | | | | | | | | | | | | | | | | | | | | | //
// | | | | | V__V__V__V | | | | | | | | | | | | | | //
// | | | | | /IF>4THEN+3\ | | | | | | | | | | | | | | //
// | | | | | \__________/ | | | | | | | | | | | | | | //
// | | | | | | | | | | | | | | | | | | | | | | | //
// | | | | | | V__V__V__V | | | | | | | | | | | | | //
// | | | | | | /IF>4THEN+3\ | | | | | | | | | | | | | //
// | | | | | | \__________/ | | | | | | | | | | | | | //
// | | | | | | | | | | | | | | | | | | | | | | | //
// | | | V__V__V__V V__V__V__V | | | | | | | | | | | | //
// | | | /IF>4THEN+3\/IF>4THEN+3\ | | | | | | | | | | | | //
// | | | \__________/\__________/ | | | | | | | | | | | | //
// | | | | | | | | | | | | | | | | | | | | | | | //
// | | | | V__V__V__V V__V__V__V | | | | | | | | | | | //
// | | | | /IF>4THEN+3\/IF>4THEN+3\ | | | | | | | | | | | //
// | | | | \__________/\__________/ | | | | | | | | | | | //
// | | | | | | | | | | | | | | | | | | | | | | | //
// | | | | | V__V__V__V V__V__V__V | | | | | | | | | | //
// | | | | | /IF>4THEN+3\/IF>4THEN+3\ | | | | | | | | | | //
// | | | | | \__________/\__________/ | | | | | | | | | | //
// | | | | | | | | | | | | | | | | | | | | | | | //
// | | V__V__V__V V__V__V__V V__V__V__V | | | | | | | | | //
// | | /IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\ | | | | | | | | | //
// | | \__________/\__________/\__________/ | | | | | | | | | //
// | | | | | | | | | | | | | | | | | | | | | | | //
// | | | V__V__V__V V__V__V__V V__V__V__V | | | | | | | | //
// | | | /IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\ | | | | | | | | //
// | | | \__________/\__________/\__________/ | | | | | | | | //
// | | | | | | | | | | | | | | | | | | | | | | | //
// | | | | V__V__V__V V__V__V__V V__V__V__V | | | | | | | //
// | | | | /IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\ | | | | | | | //
// | | | | \__________/\__________/\__________/ | | | | | | | //
// | | | | | | | | | | | | | | | | | | | | | | | //
// | V__V__V__V V__V__V__V V__V__V__V V__V__V__V | | | | | | //
// | /IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\ | | | | | | //
// | \__________/\__________/\__________/\__________/ | | | | | | //
// | | | | | | | | | | | | | | | | | | | | | | | //
// | | V__V__V__V V__V__V__V V__V__V__V V__V__V__V | | | | | //
// | | /IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\ | | | | | //
// | | \__________/\__________/\__________/\__________/ | | | | | //
// | | | | | | | | | | | | | | | | | | | | | | | //
// | | | V__V__V__V V__V__V__V V__V__V__V V__V__V__V | | | | //
// | | | /IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\ | | | | //
// | | | \__________/\__________/\__________/\__________/ | | | | //
// | | | | | | | | | | | | | | | | | | | | | | | //
// V__V__V__V V__V__V__V V__V__V__V V__V__V__V V__V__V__V | | | //
// /IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\ | | | //
// \__________/\__________/\__________/\__________/\__________/ | | | //
// | | | | | | | | | | | | | | | | | | | | | | | //
// | V__V__V__V V__V__V__V V__V__V__V V__V__V__V V__V__V__V | | //
// | /IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\ | | //
// | \__________/\__________/\__________/\__________/\__________/ | | //
// | | | | | | | | | | | | | | | | | | | | | | | //
// | | V__V__V__V V__V__V__V V__V__V__V V__V__V__V V__V__V__V | //
// | | /IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\/IF>4THEN+3\ | //
// | | \__________/\__________/\__________/\__________/\__________/ | //
// | | | | | | | | | | | | | | | | | | | | | | | //
// B B B B B B B B B B B B B B B B B B B B B B B //
// C C C C C C C C C C C C C C C C C C C C C C C //
// D D D D D D D D D D D D D D D D D D D D D D D //
// 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 //
// 2 1 0 9 8 7 6 5 4 3 2 1 0 //
// \_______/\__________/\__________/\__________/\__________/\__________/ //
// 100,000's 10,000's 1000's 100's 10's 1's //
// //
////////////////////////////////////////////////////////////////////////////////////
module bin2bcd
#( parameter W = 18) // input width
( input [W-1 :0] bin , // binary
output reg [W+(W-4)/3:0] bcd ); // bcd {...,thousands,hundreds,tens,ones}
integer i,j;
always @(bin) begin
for(i = 0; i <= W+(W-4)/3; i = i+1) bcd[i] = 0; // initialize with zeros
bcd[W-1:0] = bin; // initialize with input vector
for(i = 0; i <= W-4; i = i+1) // iterate on structure depth
for(j = 0; j <= i/3; j = j+1) // iterate on structure width
if (bcd[W-i+4*j -: 4] > 4) // if > 4
bcd[W-i+4*j -: 4] = bcd[W-i+4*j -: 4] + 4'd3; // add 3
end
endmodule
|
/*
Copyright (C) 2016 Cedric Orban
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
The neural network's basic execution unit.
Internal register width is dependent on the
largest possible value that can be stored.
This number is calculated by multiplying the
largest weight value by the number of nodes in
the previous layer of the network. Doing this
prevents overflow. One bit is added because this
module uses signed values. Another 8 bits are added
for the fractional portion of the number.
The overflow caps help cap node_o so that
it falls into sig_368p's input range.
If WEIGHT_WIDTH is changed, the case statement
setting the multiplication factors must be changed
manually.
*/
module processing_unit #(
parameter PRV_SIZE = 16,
parameter PRV_LOOP = 1,
parameter WEIGHT_WIDTH = 3,
parameter FRACTION_WIDTH = 8,
parameter REG_WIDTH = $clog2(PRV_SIZE*PRV_LOOP*3) + 8 + 1,
parameter BIAS = 0
)(
input clk_i,
input en_i,
input rst_i,
input [WEIGHT_WIDTH - 1:0] weight_i,
input [7:0] data_i,
output reg [9:0] proc_unit_o
);
reg [9:0] product = 0;
reg [REG_WIDTH - 1:0] signed_product = 0;
reg [REG_WIDTH - 1:0] sum = 0;
wire positive_cap;
wire negative_cap;
assign positive_cap = sum[REG_WIDTH - 2 : 11] != 0;
assign negative_cap = !(sum[REG_WIDTH - 2 : 11] == {(REG_WIDTH - 12){1'b1}});
always@(*)begin
//multiplication factor depends on the weight
/*
//3-bit [-3,3]
case(weight[1:0])
2'd0: product = 10'd0;
2'd1: product = data_i;
2'd2: product = data_i << 1;
2'd3: product = (data_i << 1) + data_i;
endcase
*/
/*
//3-bit [-1.5,1.5]
case(weight[1:0])
2'd0: product = 10'd0;
2'd1: product = {3'b000, data_i[7:1]};
2'd2: product = data_i;
2'd3: product = data_i + data_i[7:1];
endcase
*/
//4-bit [-1.5,1.5]
case(weight_i[2:0])
3'd0: product = 10'd0;
3'd1: product = {5'd0, data_i[7:3]};
3'd2: product = {4'd0, data_i[7:2]};
3'd3: product = {3'd0, data_i[7:1]};
3'd4: product = data_i[7:1] + data_i[7:2];
3'd5: product = data_i;
3'd6: product = data_i + data_i[7:2];
3'd7: product = data_i + data_i[7:1];
endcase
//compute the 2's complement and sign extend
if(!weight_i[WEIGHT_WIDTH - 1'b1] || product == 0)
signed_product = {{(REG_WIDTH - 10){1'b0}}, product};
else
signed_product = {{(REG_WIDTH - 10){1'b1}},~product + 1'b1};
//cap the input to sig_337p if dataOut contains a value > 7.875 or < -7.875
if(positive_cap && !sum[REG_WIDTH - 1])
proc_unit_o = 10'b0111111111;
else if((negative_cap || sum[11:2] == 10'b1000000000) && sum[REG_WIDTH - 1])
proc_unit_o = 10'b1000000001;
else
proc_unit_o = sum[11:2];
end
always@(posedge clk_i) begin
if(rst_i)
sum <= BIAS;
else if(en_i)
sum <= sum + signed_product;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:35:04 05/05/2015
// Design Name:
// Module Name: pc2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pc2(
l,
r,
outpc2
);
input [28:1] l;
input [28:1] r;
output reg [48:1] outpc2;
wire [56:1] pwire;
assign pwire = {l, r};
always@(pwire)
begin
outpc2[1] <= pwire[14];
outpc2[2] <= pwire[17];
outpc2[3] <= pwire[11];
outpc2[4] <= pwire[24];
outpc2[5] <= pwire[1];
outpc2[6] <= pwire[5];
outpc2[7] <= pwire[3];
outpc2[8] <= pwire[28];
outpc2[9] <= pwire[15];
outpc2[10] <= pwire[6];
outpc2[11] <= pwire[21];
outpc2[12] <= pwire[10];
outpc2[13] <= pwire[23];
outpc2[14] <= pwire[19];
outpc2[15] <= pwire[12];
outpc2[16] <= pwire[4];
outpc2[17] <= pwire[26];
outpc2[18] <= pwire[8];
outpc2[19] <= pwire[16];
outpc2[20] <= pwire[7];
outpc2[21] <= pwire[27];
outpc2[22] <= pwire[20];
outpc2[23] <= pwire[13];
outpc2[24] <= pwire[2];
outpc2[25] <= pwire[41];
outpc2[26] <= pwire[52];
outpc2[27] <= pwire[31];
outpc2[28] <= pwire[37];
outpc2[29] <= pwire[47];
outpc2[30] <= pwire[55];
outpc2[31] <= pwire[30];
outpc2[32] <= pwire[40];
outpc2[33] <= pwire[51];
outpc2[34] <= pwire[45];
outpc2[35] <= pwire[33];
outpc2[36] <= pwire[48];
outpc2[37] <= pwire[44];
outpc2[38] <= pwire[49];
outpc2[39] <= pwire[39];
outpc2[40] <= pwire[56];
outpc2[41] <= pwire[34];
outpc2[42] <= pwire[53];
outpc2[43] <= pwire[46];
outpc2[44] <= pwire[42];
outpc2[45] <= pwire[50];
outpc2[46] <= pwire[36];
outpc2[47] <= pwire[29];
outpc2[48] <= pwire[32];
end
endmodule
|
/*
read sequence
clk ``\____/````\____/` ..... _/````\____/````\____/` ..... _/````\____/````\____/`
| | | | | | |
start XXXX```````````\__ ....... ____________________________________________________
| | | | | | |
rnw XXXXXX```XXXXXXXXX ....... XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
| | some | | | | |
ready XXXXXXX\__________ clocks __/`````````````````` ....... ```````````\__________
before | |
rdat ------------------ ready -< cell 0 | cell 1 | ....... |last cell>-----------
| | | | | | |
stop XXXXXXX\__________ ....... _____________________ ....... ___________/``````````
^all operations stopped until next start strobe
write sequence
clk ``\____/````\____/` ..... _/````\____/````\____/````\____/````\____/````\____/````\____/````\____/
| | some | | some | | | | | |
start XXXX```````````\__ ....... _____________ .... ______________ .... ________________________________
| | clocks | | clocks | | | | | |
rnw XXXXXX___XXXXXXXXX ....... XXXXXXXXXXXXX .... XXXXXXXXXXXXXX .... XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
| | before | | before | | | | | |
ready XXXXXXX\__________ ....... _/`````````\_ .... __/`````````\_ .... __/`````````\___________________
| | first | | next | | | | | |
wdat XXXXXXXXXXXXXXXXXXXXXXXXXXXX< cell 0 >X .... XX< cell 1 >X .... XX<last cell>XXXXXXXXXXXXXXXXXXX
| | ready | | ready | | | | | |
stop XXXXXXX\__________ ....... _____________ .... ______________ .... ____________/```````````````````
| | strobe | | strobe | | | | | |
clk ``\____/````\____/````\____/````\____/````\____/````\____/````\____/````\____/````\____/````\____/````\____/````\____/``
| | | | | | | | | | | |
ready __________________/`````````\___________________/`````````\___________________/`````````\___________________/`````````\_
| | | | | | | | | | | |
wdat cell 0 | cell 1 | cell 2 | cell 3 |
| | | | | | | | | | | |
sram_adr XXXXXXXXXXXXXXXXXXXXXXXXX| 0 | 1 | 2 |
| | | | | | | | | | | |
sram_dat XXXXXXXXXXXXXXXXXXXXXXXXX| cell 0 | cell 1 | cell 2 |
| | | | | | | | | | | |
sram_we_n```````````````````````````````````\_________/```````````````````\_________/```````````````````\_________/``````````
| BEG | PRE1 | PRE2 | | | | | | | | |
| | | CYC1 | CYC2 | CYC3 | CYC1 | CYC2 | CYC3 | CYC1 | CYC2 | CYC3 |
*/
module sram_control(
clk,
clk2, //latching of SRAM data out
start, // initializing input, address=0
stop, // when all addresses are done, nothing will happen after stop is set, need another start signal
rnw, // 1 - read, 0 - write sequence (latched when start=1)
ready, // strobe. when writing, one mean that data from wdat written to the memory (2^SRAM_ADDR_SIZE strobes total)
// when reading, one mean that data read from memory is on rdat output (2^SRAM_ADDR_SIZE strobes total)
wdat, // input, data to be written to memory
rdat, // output, data last read from memory
SRAM_DQ, // sram inout databus
SRAM_ADDR, // sram address bus
SRAM_UB_N, // sram control signals
SRAM_LB_N, //
SRAM_WE_N, //
SRAM_CE_N, //
SRAM_OE_N //
);
parameter SRAM_DATA_SIZE = 16;
parameter SRAM_ADDR_SIZE = 18;
input clk;
input clk2;
input start,rnw;
output stop;
reg stop;
output ready;
reg ready;
input [SRAM_DATA_SIZE-1:0] wdat;
output [SRAM_DATA_SIZE-1:0] rdat;
reg [SRAM_DATA_SIZE-1:0] rdat;
inout [SRAM_DATA_SIZE-1:0] SRAM_DQ;
wire [SRAM_DATA_SIZE-1:0] SRAM_DQ;
output [SRAM_ADDR_SIZE-1:0] SRAM_ADDR;
wire [SRAM_ADDR_SIZE-1:0] SRAM_ADDR;
output SRAM_UB_N,SRAM_LB_N,SRAM_WE_N,SRAM_CE_N,SRAM_OE_N;
reg SRAM_UB_N,SRAM_LB_N, /*SRAM_WE_N,*/ SRAM_CE_N,SRAM_OE_N;
wire SRAM_WE_N;
reg SRAM_WE_N_reg;
assign SRAM_WE_N = SRAM_WE_N_reg; // | clk;
reg [SRAM_DATA_SIZE-1:0] wdat2;
reg dbin; //data bus direction control
reg [SRAM_ADDR_SIZE:0] sram_addr_ctr; // one bit bigger to have stop flag
wire [SRAM_ADDR_SIZE:0] sram_addr_nxt; // next sram address
reg [SRAM_DATA_SIZE-1:0] rdat2;
assign SRAM_ADDR = sram_addr_ctr[SRAM_ADDR_SIZE-1:0];
assign sram_addr_nxt = sram_addr_ctr + 1;
// data bus control
assign SRAM_DQ = dbin ? 'hZ : wdat2;
always @(posedge clk)
begin
rdat <= SRAM_DQ;
end
always @(posedge clk)
begin
if( ready ) wdat2 <= wdat;
end
reg [4:0] curr_state,next_state;
parameter START_STATE = 5'h00; // reset state
parameter INIT_STATE = 5'h01; // initialization state
parameter READ_BEG = 5'h02; // read branch: prepare signals
parameter READ_PRE = 5'h03;
parameter READ_CYCLE1 = 5'h04; // read in progress: increment address, set ready, out data, do so until all addresses done
parameter READ_CYCLE2 = 5'h05; // read in progress: increment address, set ready, out data, do so until all addresses done
parameter READ_POST = 5'h06;
parameter READ_END = 5'h07; // read end: deassert some signals, go to stop state
parameter WRITE_BEG = 5'h10; // prepare signals
parameter WRITE_PRE1 = 5'h11; // assert ready
parameter WRITE_PRE2 = 5'h12; // capture wdat, negate ready, NO INCREMENT address, next state is WRITE_CYC2
parameter WRITE_CYC1 = 5'h13; // capture wdat, negate ready, increment address
parameter WRITE_CYC1E = 5'h14;
parameter WRITE_CYC2 = 5'h15; // assert SRAM_WE_N, go to WRITE_END if sram_addr_nxt is out of memory region
parameter WRITE_CYC3 = 5'h16; // negate SRAM_WE_N, assert ready (wdat will be captured in WRITE_CYC1)
parameter WRITE_END = 5'h17; // deassert sram control signals, go to STOP_STATE
parameter STOP_STATE = 5'h1F; // full stop state
// FSM states
always @*
begin
case( curr_state )
////////////////////////////////////////////////////////////////////////
START_STATE:
next_state = INIT_STATE;
////////////////////////////////////////////////////////////////////////
INIT_STATE:
begin
if( rnw ) // read
next_state = READ_BEG;
else // !rnw - write
next_state = WRITE_BEG;
end
////////////////////////////////////////////////////////////////////////
READ_BEG:
next_state = READ_PRE;
READ_PRE:
next_state = READ_CYCLE1;
READ_CYCLE1:
next_state = READ_CYCLE2;
READ_CYCLE2:
if( !sram_addr_ctr[SRAM_ADDR_SIZE] )
next_state = READ_CYCLE1;
else
next_state = READ_POST;
READ_POST:
next_state = READ_END;
READ_END:
next_state = STOP_STATE;
////////////////////////////////////////////////////////////////////////
WRITE_BEG:
next_state = WRITE_PRE1;
WRITE_PRE1:
next_state = WRITE_PRE2;
WRITE_PRE2:
next_state = WRITE_CYC1E;
WRITE_CYC1:
next_state = WRITE_CYC1E;
WRITE_CYC1E:
next_state = WRITE_CYC2;
WRITE_CYC2:
if( !sram_addr_nxt[SRAM_ADDR_SIZE] )
next_state = WRITE_CYC3;
else
next_state = WRITE_END;
WRITE_CYC3:
next_state = WRITE_CYC1;
WRITE_END:
next_state = STOP_STATE;
////////////////////////////////////////////////////////////////////////
STOP_STATE:
next_state = STOP_STATE;
////////////////////////////////////////////////////////////////////////
default:
next_state = STOP_STATE;
endcase
end
// FSM flip-flops
always @(posedge clk)
begin
if( start )
curr_state <= START_STATE;
else
curr_state <= next_state;
end
// FSM outputs
always @(posedge clk)
begin
case( next_state )
////////////////////////////////////////////////////////////////////////
INIT_STATE:
begin
stop <= 1'b0;
SRAM_UB_N <= 1'b1;
SRAM_LB_N <= 1'b1;
SRAM_CE_N <= 1'b1;
SRAM_OE_N <= 1'b1;
SRAM_WE_N_reg <= 1'b1;
dbin <= 1'b1;
sram_addr_ctr <= 0;
ready <= 1'b0;
end
////////////////////////////////////////////////////////////////////////
READ_BEG:
begin
SRAM_UB_N <= 1'b0;
SRAM_LB_N <= 1'b0;
SRAM_CE_N <= 1'b0;
SRAM_OE_N <= 1'b0;
end
READ_PRE:
begin
// sram_addr_ctr <= sram_addr_nxt;
end
READ_CYCLE1:
begin
ready <= 1'b1;
sram_addr_ctr <= sram_addr_nxt;
end
READ_CYCLE2:
begin
ready <= 1'b0;
end
READ_POST:
begin
ready <= 1'b0; // in read sequence, ready and data are 2 cycles past the actual read.
end
READ_END:
begin
SRAM_UB_N <= 1'b1;
SRAM_LB_N <= 1'b1;
SRAM_CE_N <= 1'b1;
SRAM_OE_N <= 1'b1;
ready <= 1'b0;
end
////////////////////////////////////////////////////////////////////////
WRITE_BEG:
begin
SRAM_UB_N <= 1'b0;
SRAM_LB_N <= 1'b0;
SRAM_CE_N <= 1'b0;
dbin <= 1'b0;
end
WRITE_PRE1:
begin
ready <= 1'b1;
end
WRITE_PRE2:
begin
ready <= 1'b0;
end
WRITE_CYC1:
begin
ready <= 1'b0;
sram_addr_ctr <= sram_addr_nxt;
end
WRITE_CYC2:
begin
SRAM_WE_N_reg <= 1'b0;
end
WRITE_CYC3:
begin
SRAM_WE_N_reg <= 1'b1;
ready <= 1'b1;
end
WRITE_END:
begin
ready <= 1'b0;
SRAM_WE_N_reg <= 1'b1;
SRAM_UB_N <= 1'b1;
SRAM_LB_N <= 1'b1;
SRAM_CE_N <= 1'b1;
end
////////////////////////////////////////////////////////////////////////
STOP_STATE:
begin
stop <= 1'b1;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4B_FUNCTIONAL_V
`define SKY130_FD_SC_LP__NOR4B_FUNCTIONAL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nor4b (
Y ,
A ,
B ,
C ,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Local signals
wire not0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y, A, B, C, not0_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4B_FUNCTIONAL_V |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module video_scaler_ctrl_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 6,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
// user signals
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle,
output wire [31:0] in_width,
output wire [31:0] in_height,
output wire [31:0] out_width,
output wire [31:0] out_height
);
//------------------------Address Info-------------------
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : Data signal of in_width
// bit 31~0 - in_width[31:0] (Read/Write)
// 0x14 : reserved
// 0x18 : Data signal of in_height
// bit 31~0 - in_height[31:0] (Read/Write)
// 0x1c : reserved
// 0x20 : Data signal of out_width
// bit 31~0 - out_width[31:0] (Read/Write)
// 0x24 : reserved
// 0x28 : Data signal of out_height
// bit 31~0 - out_height[31:0] (Read/Write)
// 0x2c : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_AP_CTRL = 6'h00,
ADDR_GIE = 6'h04,
ADDR_IER = 6'h08,
ADDR_ISR = 6'h0c,
ADDR_IN_WIDTH_DATA_0 = 6'h10,
ADDR_IN_WIDTH_CTRL = 6'h14,
ADDR_IN_HEIGHT_DATA_0 = 6'h18,
ADDR_IN_HEIGHT_CTRL = 6'h1c,
ADDR_OUT_WIDTH_DATA_0 = 6'h20,
ADDR_OUT_WIDTH_CTRL = 6'h24,
ADDR_OUT_HEIGHT_DATA_0 = 6'h28,
ADDR_OUT_HEIGHT_CTRL = 6'h2c,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
WRRESET = 2'd3,
RDIDLE = 2'd0,
RDDATA = 2'd1,
RDRESET = 2'd2,
ADDR_BITS = 6;
//------------------------Local signal-------------------
reg [1:0] wstate = WRRESET;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate = RDRESET;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
reg int_ap_idle;
reg int_ap_ready;
reg int_ap_done = 1'b0;
reg int_ap_start = 1'b0;
reg int_auto_restart = 1'b0;
reg int_gie = 1'b0;
reg [1:0] int_ier = 2'b0;
reg [1:0] int_isr = 2'b0;
reg [31:0] int_in_width = 'b0;
reg [31:0] int_in_height = 'b0;
reg [31:0] int_out_width = 'b0;
reg [31:0] int_out_height = 'b0;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRRESET;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDRESET;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
ADDR_IN_WIDTH_DATA_0: begin
rdata <= int_in_width[31:0];
end
ADDR_IN_HEIGHT_DATA_0: begin
rdata <= int_in_height[31:0];
end
ADDR_OUT_WIDTH_DATA_0: begin
rdata <= int_out_width[31:0];
end
ADDR_OUT_HEIGHT_DATA_0: begin
rdata <= int_out_height[31:0];
end
endcase
end
end
end
//------------------------Register logic-----------------
assign interrupt = int_gie & (|int_isr);
assign ap_start = int_ap_start;
assign in_width = int_in_width;
assign in_height = int_in_height;
assign out_width = int_out_width;
assign out_height = int_out_height;
// int_ap_start
always @(posedge ACLK) begin
if (ARESET)
int_ap_start <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
int_ap_start <= 1'b1;
else if (ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
end
// int_ap_done
always @(posedge ACLK) begin
if (ARESET)
int_ap_done <= 1'b0;
else if (ACLK_EN) begin
if (ap_done)
int_ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_ap_done <= 1'b0; // clear on read
end
end
// int_ap_idle
always @(posedge ACLK) begin
if (ARESET)
int_ap_idle <= 1'b0;
else if (ACLK_EN) begin
int_ap_idle <= ap_idle;
end
end
// int_ap_ready
always @(posedge ACLK) begin
if (ARESET)
int_ap_ready <= 1'b0;
else if (ACLK_EN) begin
int_ap_ready <= ap_ready;
end
end
// int_auto_restart
always @(posedge ACLK) begin
if (ARESET)
int_auto_restart <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
int_auto_restart <= WDATA[7];
end
end
// int_gie
always @(posedge ACLK) begin
if (ARESET)
int_gie <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
end
// int_ier
always @(posedge ACLK) begin
if (ARESET)
int_ier <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[1:0];
end
end
// int_isr[0]
always @(posedge ACLK) begin
if (ARESET)
int_isr[0] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
end
// int_isr[1]
always @(posedge ACLK) begin
if (ARESET)
int_isr[1] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
end
// int_in_width[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_in_width[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IN_WIDTH_DATA_0)
int_in_width[31:0] <= (WDATA[31:0] & wmask) | (int_in_width[31:0] & ~wmask);
end
end
// int_in_height[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_in_height[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IN_HEIGHT_DATA_0)
int_in_height[31:0] <= (WDATA[31:0] & wmask) | (int_in_height[31:0] & ~wmask);
end
end
// int_out_width[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_out_width[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_OUT_WIDTH_DATA_0)
int_out_width[31:0] <= (WDATA[31:0] & wmask) | (int_out_width[31:0] & ~wmask);
end
end
// int_out_height[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_out_height[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_OUT_HEIGHT_DATA_0)
int_out_height[31:0] <= (WDATA[31:0] & wmask) | (int_out_height[31:0] & ~wmask);
end
end
//------------------------Memory logic-------------------
endmodule
|
`timescale 1ns/10ps
module RotarySim;
reg clock;
reg reset;
reg [11:0] inst;
reg inst_en;
reg [1:0] rotary;
wire rotary_left_status;
wire rotary_right_status;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#10000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
#8 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
rotary = 2'b00;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
#5 rotary = 2'b01;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#7 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
rotary = 2'b00;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
#5 rotary = 2'b10;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#7 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test disabled instruction.
#4 rotary = 2'b01;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 0;
#4 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test bad instruction.
#4 inst = {8'hF,8'hAA};
inst_en = 1;
#4 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
#4 reset = 1;
#8 reset = 0;
#4 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test multiple left turns before one read.
#4 rotary = 2'b01;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 rotary = 2'b01;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 rotary = 2'b01;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test multiple right turns before one read.
#4 rotary = 2'b10;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 rotary = 2'b10;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 rotary = 2'b10;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test multiple left turns before one read. Some of the turns are caused by bounces.
#4 rotary = 2'b01;
#18 rotary = 2'b00;
#2 rotary = 2'b01;
#18 rotary = 2'b00;
#2 rotary = 2'b01;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_RDLS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test multiple right turns before one read. Some of the turns are caused by bounces.
#4 rotary = 2'b10;
#18 rotary = 2'b00;
#2 rotary = 2'b10;
#18 rotary = 2'b00;
#2 rotary = 2'b10;
#30 rotary = 2'b11;
#30 rotary = 2'b00;
#8 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_RDRS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Rotary_NOP,8'bxxxxxxxx};
inst_en = 1;
end
Rotary
rotary (.clock(clock),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.rotary(rotary),
.rotary_left_status(rotary_left_status),
.rotary_right_status(rotary_right_status));
endmodule // RotarySim
|
`include "cpu_data.v"
module Decoder(
word,
operator_group, operator,
rg1, rg2, val, flags, relative_addr);
input [15:0] word;
output [3:0] operator;
output reg [3:0] operator_group;
output [2:0] rg1, rg2;
output [7:0] val;
output [7:0] flags;
output [9:0] relative_addr;
assign val = word[11:4];
assign flags = word[15:8];
assign rg1 = word[0] ? word[7:5] : word[3:1];
assign rg2 = word[10:8];
assign operator = word[15:12];
assign relative_addr = word[11:2];
always @*
casez (word[4:0])
5'b????0: operator_group = `GROUP_CRVMATH;
5'b???01: operator_group = `GROUP_RJMP;
5'b00111: operator_group = `GROUP_CRRMATH;
5'b01111: operator_group = `GROUP_CRSMATH;
5'b10111: casez(word[15:12])
4'b1011: operator_group = `GROUP_WRRMATH;
4'b1111: operator_group = `GROUP_WRRMATH;
4'b1???: operator_group = `GROUP_WRRMATH_MEM;
default: operator_group = `GROUP_WRRMATH;
endcase
5'b11111: casez(word[15:13])
3'b111: operator_group = `GROUP_WRSMATH_STACK;
default: operator_group = `GROUP_WRSMATH;
endcase
5'b00011: operator_group = `GROUP_SFLAG;
5'b10011: operator_group = `GROUP_UFLAG;
5'b11011: casez(word[15:14])
2'b11: operator_group = `GROUP_SPECIAL_LONG;
default: operator_group = `GROUP_SPECIAL;
endcase
default: operator_group = `GROUP_SPECIAL;
endcase
endmodule
|
module mandelbrot(clk, reset, c_real_in, c_imag_in, overflow, real_out, imag_out, iters);
parameter width = 20;
parameter iterations = 30;
input reset;
input clk;
input signed [width - 1:0] c_real_in;
input signed [width - 1:0] c_imag_in;
output reg overflow;
output signed [width - 1:0] real_out;
output signed [width - 1:0] imag_out;
output unsigned [7:0] iters;
reg signed [width - 1:0] i_real[0:iterations - 1];
reg signed [width - 1:0] i_imag[0:iterations - 1];
reg signed [width - 1:0] c_real[0:iterations - 1];
reg signed [width - 1:0] c_imag[0:iterations - 1];
wire signed [width - 1:0] o_real[0:iterations - 1];
wire signed [width - 1:0] o_imag[0:iterations - 1];
wire signed [width - 1:0] size_square[0:iterations - 1];
reg unsigned [7:0] iters_in[0:iterations - 1];
wire unsigned [7:0] iters_out[0:iterations - 1];
assign real_out = o_real[iterations - 1];
assign imag_out = o_imag[iterations - 1];
assign iters = iters_out[iterations - 1];
genvar i;
generate
for (i = 0; i < iterations; i = i + 1) begin: mandelbrots
mandelbrot_iter m(i_real[i], i_imag[i], c_real[i],
c_imag[i], o_real[i], o_imag[i], size_square[i],
iters_in[i], iters_out[i]);
end
always @(posedge clk or negedge reset) begin
if (~reset) begin
i_real[0] <= 32'd0;
i_imag[0] <= 32'd0;
c_real[0] <= 32'd0;
c_imag[0] <= 32'd0;
overflow <= 0;
end else begin
i_real[0] <= 32'd0;
i_imag[0] <= 32'd0;
c_real[0] <= c_real_in;
c_imag[0] <= c_imag_in;
overflow <= size_square[iterations - 1] >= 32'h1000000; // 4 in Q10.22
end
end
for (i = 1; i < iterations; i = i + 1) begin: sets
always @(posedge clk or negedge reset) begin
if (~reset) begin
i_real[i] <= 32'd0;
i_imag[i] <= 32'd0;
c_real[i] <= 32'd0;
c_imag[i] <= 32'd0;
iters_in[i] <= 8'd0;
end else begin
if (size_square[i - 1] >= 32'h1000000) begin
i_real[i] <= 32'h1000000;
i_imag[i] <= 32'h1000000;
c_real[i] <= c_real[i - 1];
c_imag[i] <= c_imag[i - 1];
iters_in[i] <= iters_out[i - 1];
end else begin
i_real[i] <= o_real[i - 1];
i_imag[i] <= o_imag[i - 1];
c_real[i] <= c_real[i - 1];
c_imag[i] <= c_imag[i - 1];
iters_in[i] <= iters_out[i - 1];
end
end
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2_1_V
`define SKY130_FD_SC_HDLL__NOR2_1_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDLCLKP_SYMBOL_V
`define SKY130_FD_SC_HS__SDLCLKP_SYMBOL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDLCLKP_SYMBOL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_impctl_avgcnt.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_impctl_avgcnt(adv_sgn ,so_i ,above ,sclk ,avgcntr_rst ,se ,
si_l ,global_reset_n ,l2clk );
output adv_sgn ;
output so_i ;
input above ;
input sclk ;
input avgcntr_rst ;
input se ;
input si_l ;
input global_reset_n ;
input l2clk ;
wire [8:0] count ;
wire [7:0] scan_data ;
wire [7:0] pcarry ;
wire [8:0] next_count ;
wire [1:0] net085 ;
wire [1:0] din ;
wire [1:0] net082 ;
wire net200 ;
wire net183 ;
wire net201 ;
wire net185 ;
wire net203 ;
wire net112 ;
wire net194 ;
wire net195 ;
wire net196 ;
wire net115 ;
wire net199 ;
wire net216 ;
wire sc ;
wire net223 ;
wire net228 ;
wire net229 ;
wire net231 ;
wire net232 ;
wire net234 ;
wire net240 ;
wire net241 ;
wire net247 ;
wire net249 ;
wire net250 ;
wire scan_in ;
wire scan_out ;
wire net179 ;
bw_u1_inv_4x I227 (
.z (net216 ),
.a (avgcntr_rst ) );
bw_u1_inv_4x I229 (
.z (scan_in ),
.a (si_l ) );
bw_u1_soffr_4x I182_0_ (
.q (count[0] ),
.so (scan_data[0] ),
.ck (l2clk ),
.d (din[0] ),
.se (se ),
.sd (scan_in ),
.r_l (net201 ) );
bw_u1_soffr_4x I182_8_ (
.q (count[8] ),
.so (scan_out ),
.ck (l2clk ),
.d (next_count[8] ),
.se (se ),
.sd (scan_data[7] ),
.r_l (net201 ) );
bw_u1_xor2_2x I231 (
.z (next_count[1] ),
.a (net228 ),
.b (pcarry[0] ) );
bw_u1_xor2_4x I232 (
.z (net228 ),
.a (net185 ),
.b (count[1] ) );
bw_u1_xor2_2x I233 (
.z (net240 ),
.a (net185 ),
.b (count[3] ) );
bw_u1_xor2_2x I234 (
.z (next_count[3] ),
.a (pcarry[2] ),
.b (count[3] ) );
bw_u1_nand2_2x I298_0_ (
.z (net085[1] ),
.a (next_count[0] ),
.b (sc ) );
bw_u1_xor2_2x I235 (
.z (next_count[2] ),
.a (pcarry[1] ),
.b (count[2] ) );
bw_u1_xor2_2x I236 (
.z (net200 ),
.a (net185 ),
.b (count[2] ) );
bw_u1_xnor2_2x I237 (
.z (next_count[7] ),
.a (pcarry[6] ),
.b (count[7] ) );
bw_u1_xor2_2x I238 (
.z (net231 ),
.a (net185 ),
.b (count[7] ) );
bw_u1_xor2_2x I239 (
.z (net196 ),
.a (net185 ),
.b (count[6] ) );
bw_u1_soffr_4x I182_7_ (
.q (count[7] ),
.so (scan_data[7] ),
.ck (l2clk ),
.d (next_count[7] ),
.se (se ),
.sd (scan_data[6] ),
.r_l (net201 ) );
bw_u1_xnor2_2x I240 (
.z (next_count[6] ),
.a (pcarry[5] ),
.b (count[6] ) );
bw_u1_xnor2_2x I241 (
.z (next_count[5] ),
.a (pcarry[4] ),
.b (count[5] ) );
bw_u1_xor2_2x I242 (
.z (net249 ),
.a (net185 ),
.b (count[5] ) );
bw_u1_xor2_2x I243 (
.z (net234 ),
.a (net185 ),
.b (count[4] ) );
bw_u1_xor2_2x I244 (
.z (next_count[4] ),
.a (pcarry[3] ),
.b (count[4] ) );
bw_u1_xnor2_2x I246 (
.z (next_count[8] ),
.a (pcarry[7] ),
.b (count[8] ) );
bw_u1_soffr_4x I182_6_ (
.q (count[6] ),
.so (scan_data[6] ),
.ck (l2clk ),
.d (next_count[6] ),
.se (se ),
.sd (scan_data[5] ),
.r_l (net201 ) );
bw_u1_inv_4x I250 (
.z (pcarry[0] ),
.a (next_count[0] ) );
bw_u1_nand3_5x I251 (
.z (net229 ),
.a (net194 ),
.b (sc ),
.c (net228 ) );
bw_u1_inv_2x I252 (
.z (net199 ),
.a (net200 ) );
bw_u1_nand2_4x I253 (
.z (net241 ),
.a (net200 ),
.b (net240 ) );
bw_u1_nor2_6x I254 (
.z (pcarry[3] ),
.a (net241 ),
.b (net229 ) );
bw_u1_nor2_2x I255 (
.z (net115 ),
.a (net232 ),
.b (net250 ) );
bw_u1_nor2_2x I256 (
.z (net112 ),
.a (net195 ),
.b (net250 ) );
bw_u1_inv_2x I259 (
.z (net203 ),
.a (net250 ) );
bw_u1_soffr_4x I182_5_ (
.q (count[5] ),
.so (scan_data[5] ),
.ck (l2clk ),
.d (next_count[5] ),
.se (se ),
.sd (scan_data[4] ),
.r_l (net201 ) );
bw_u1_inv_2x I260 (
.z (net195 ),
.a (net196 ) );
bw_u1_nand2_4x I261 (
.z (pcarry[4] ),
.a (pcarry[3] ),
.b (net234 ) );
bw_u1_nand2_2x I262 (
.z (net232 ),
.a (net196 ),
.b (net231 ) );
bw_u1_inv_4x I165 (
.z (pcarry[1] ),
.a (net229 ) );
bw_u1_nand2_4x I296_1_ (
.z (din[1] ),
.a (net082[0] ),
.b (net085[0] ) );
bw_u1_nand2_4x I264 (
.z (pcarry[6] ),
.a (pcarry[3] ),
.b (net112 ) );
bw_u1_nor2_4x I167 (
.z (pcarry[2] ),
.a (net199 ),
.b (net229 ) );
bw_u1_nand2_4x I266 (
.z (pcarry[5] ),
.a (pcarry[3] ),
.b (net203 ) );
bw_u1_nand2_4x I168 (
.z (pcarry[7] ),
.a (pcarry[3] ),
.b (net115 ) );
bw_u1_nand2_4x I267 (
.z (net250 ),
.a (net234 ),
.b (net249 ) );
bw_u1_nand2_4x I269 (
.z (net247 ),
.a (global_reset_n ),
.b (net183 ) );
bw_u1_soffr_4x I182_4_ (
.q (count[4] ),
.so (scan_data[4] ),
.ck (l2clk ),
.d (next_count[4] ),
.se (se ),
.sd (scan_data[3] ),
.r_l (net201 ) );
bw_u1_inv_5x I270 (
.z (net201 ),
.a (net247 ) );
bw_u1_inv_5x I271 (
.z (net183 ),
.a (avgcntr_rst ) );
bw_u1_inv_3x I273 (
.z (net179 ),
.a (count[8] ) );
bw_u1_nand2_4x I296_0_ (
.z (din[0] ),
.a (net082[1] ),
.b (net085[1] ) );
bw_u1_inv_10x I274 (
.z (adv_sgn ),
.a (net179 ) );
bw_u1_soffr_4x I182_3_ (
.q (count[3] ),
.so (scan_data[3] ),
.ck (l2clk ),
.d (next_count[3] ),
.se (se ),
.sd (scan_data[2] ),
.r_l (net201 ) );
bw_u1_inv_8x I282 (
.z (net185 ),
.a (above ) );
bw_u1_inv_2x I302 (
.z (next_count[0] ),
.a (count[0] ) );
bw_u1_nand2_2x I297_1_ (
.z (net082[0] ),
.a (count[1] ),
.b (net223 ) );
bw_u1_soffr_4x I182_2_ (
.q (count[2] ),
.so (scan_data[2] ),
.ck (l2clk ),
.d (next_count[2] ),
.se (se ),
.sd (scan_data[1] ),
.r_l (net201 ) );
bw_u1_nand2_2x I297_0_ (
.z (net082[1] ),
.a (count[0] ),
.b (net223 ) );
bw_u1_inv_4x I198 (
.z (so_i ),
.a (scan_out ) );
bw_u1_xor2_4x I217 (
.z (net194 ),
.a (net185 ),
.b (count[0] ) );
bw_u1_inv_5x I219 (
.z (sc ),
.a (net223 ) );
bw_u1_soffr_4x I182_1_ (
.q (count[1] ),
.so (scan_data[1] ),
.ck (l2clk ),
.d (din[1] ),
.se (se ),
.sd (scan_data[0] ),
.r_l (net201 ) );
bw_u1_nand2_4x I220 (
.z (net223 ),
.a (sclk ),
.b (net216 ) );
bw_u1_nand2_2x I298_1_ (
.z (net085[0] ),
.a (next_count[1] ),
.b (sc ) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S18_1_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S18_1_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog wrapper for clkdlybuf4s18 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkdlybuf4s18.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s18_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkdlybuf4s18 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s18_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkdlybuf4s18 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S18_1_V
|
/* Decode Unit Testbench*/
`timescale 1ns / 100ps
`include "../decode_32.v"
module decode_test();
localparam MEM_SIZE = 32;
/* Clocks */
reg clk;
always
#10 clk = ~ clk; //100MHz
/* Input signals to drive */
reg reset;
reg stall;
reg [31:0] insn;
reg [31:0] insn_address;
//integer insn_address;
reg [7:0] sysreg_data_input;
/* Output signals to observe*/
wire [4:0] reg_select;
wire [4:0] rsa;
wire [4:0] rsb;
wire [4:0] rd;
wire [20:0] imm;
wire [3:0] aluop;
wire jlnk;
wire pc_change_relative;
wire pc_change_absolute;
wire mem_read;
wire mem_write;
wire nri_flag;
wire [1:0] branch_funct;
wire stall_output;
wire memsync;
wire syscall;
wire permission_inc;
wire permission_dec;
wire [7:0] sysreg_addr;
wire [7:0] sysreg_data;
wire [31:0] insn_pc_output;
wire [30:0] cp_insn;
/* Memory Test Registers */
reg [31:0] insn_mem [0:MEM_SIZE-1]; //1024 addresses, 2^10
decode_32 decode_ut( //Decode unit under test
.insn_in(insn), //Instruction Input
.reset_in(reset), //Reset line input (active low)
.clk_in(clk), //Clock input
.insn_pc_in(insn_address), //Current instruction PC Address
.stall_in(stall), //CCCP Leader... nah just a stall signal
.reg_select_out(reg_select), //What register bank the instruction wants to access
.rsa_out(rsa), //RSa address
.rsb_out(rsb), //RSb address
.rd_out(rd), //Rd address
.imm_out(imm), //Immediate value (if used)
.aluop_out(aluop), //What operation to tell the ALU to do
.jlnk_out(jlnk), //Saving the PC to $R4/RA?
.pc_change_rel_out(pc_change_relative), //PC Relative address change
.pc_change_abs_out(pc_change_absolute), //PC Absolute address change
.mem_read_out(mem_read), //Memory read access
.mem_write_out(mem_write), //Memory write access
.nri_flg_out(nri_flag), //Not a real instruction, flag
.branch_funct_out(branch_funct), //Branch code, determines if branch should be taken or not along with output
.stall_out(stall_output), //Send stall signal out
.memsync_out(memsync), //Sync memory signal
.syscall_out(syscall), //Instruction is system call
.pem_inc_req_out(permission_inc), //Permission increase request
.pem_dec_req_out(permission_dec), //Permission decrease request
.sysreg_addr_out(sysreg_addr), //System/Special purpose register address to access
.sysreg_data_out(sysreg_data), //Data to write to System/Special purpose register
.sysreg_data_in(sysreg_data_input), //Data read from System/Special purpose register
.insn_pc_out(insn_pc_output), //Output PC value (for debugging)
/*Co-Processor Connections*/
.cp_insn_out(cp_insn) //Output instruction to Co-Processor to decode
);
integer i;
integer count;
/* Initial Conditions */
initial begin
$dumpfile("decode.vcd");
$dumpvars(0,decode_test);
$readmemh("test_insn.txt", insn_mem); //Fill memory
for( i = 0; i < MEM_SIZE; i = i + 1) begin
$display("Data read from insn_mem: %h | address: %h", insn_mem[i], i);
#10;
end
#100 //wait a bit before doing anything
clk <= 1'b0;
reset <= 1'b0; //put into reset to start
#10 //let the reset propagate
stall <= 1'b0;
// insn <= 32'b0;
insn_address <= 0;
sysreg_data_input <= 8'b0;
#10
reset <= 1'b1; //and they're off!
count <= 0;
/* Testing */
//always @(posedge clk) begin
#5
for( insn_address = 0; insn_address <= MEM_SIZE; insn_address = insn_address + 1) begin
#20;
insn <= insn_mem[insn_address]; //get instruction from memory address
$display("Current Address: %h | Instruction: %h", insn_address, insn);
end
//end
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__EDFXTP_FUNCTIONAL_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_edf_p_pg/sky130_fd_sc_hs__u_edf_p_pg.v"
`celldefine
module sky130_fd_sc_hs__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_edf_p_pg `UNIT_DELAY u_edf_p_pg0 (buf_Q , D, CLK, DE, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXTP_FUNCTIONAL_V |
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Mon Oct 26 08:39:08 EDT 2015
//
// Method conflict info:
// Method: allocate
// Sequenced before: next
// Sequenced before (restricted): allocate
//
// Method: next
// Sequenced after: allocate
// Conflicts: next
//
//
// Ports:
// Name I/O size props
// allocate O 25
// pipeline I 1
// CLK I 1 clock
// RST_N I 1 reset
// allocate_alloc_input I 25
// EN_next I 1
// EN_allocate I 1
//
// Combinational paths from inputs to outputs:
// (allocate_alloc_input, pipeline) -> allocate
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkSepRouterAllocator(pipeline,
CLK,
RST_N,
allocate_alloc_input,
EN_allocate,
allocate,
EN_next);
input pipeline;
input CLK;
input RST_N;
// actionvalue method allocate
input [24 : 0] allocate_alloc_input;
input EN_allocate;
output [24 : 0] allocate;
// action method next
input EN_next;
// signals for module outputs
wire [24 : 0] allocate;
// register as_inputArbGrants_reg_0
reg as_inputArbGrants_reg_0;
wire as_inputArbGrants_reg_0$D_IN, as_inputArbGrants_reg_0$EN;
// register as_inputArbGrants_reg_0_1
reg as_inputArbGrants_reg_0_1;
wire as_inputArbGrants_reg_0_1$D_IN, as_inputArbGrants_reg_0_1$EN;
// register as_inputArbGrants_reg_0_2
reg as_inputArbGrants_reg_0_2;
wire as_inputArbGrants_reg_0_2$D_IN, as_inputArbGrants_reg_0_2$EN;
// register as_inputArbGrants_reg_0_3
reg as_inputArbGrants_reg_0_3;
wire as_inputArbGrants_reg_0_3$D_IN, as_inputArbGrants_reg_0_3$EN;
// register as_inputArbGrants_reg_0_4
reg as_inputArbGrants_reg_0_4;
wire as_inputArbGrants_reg_0_4$D_IN, as_inputArbGrants_reg_0_4$EN;
// register as_inputArbGrants_reg_1
reg as_inputArbGrants_reg_1;
wire as_inputArbGrants_reg_1$D_IN, as_inputArbGrants_reg_1$EN;
// register as_inputArbGrants_reg_1_1
reg as_inputArbGrants_reg_1_1;
wire as_inputArbGrants_reg_1_1$D_IN, as_inputArbGrants_reg_1_1$EN;
// register as_inputArbGrants_reg_1_2
reg as_inputArbGrants_reg_1_2;
wire as_inputArbGrants_reg_1_2$D_IN, as_inputArbGrants_reg_1_2$EN;
// register as_inputArbGrants_reg_1_3
reg as_inputArbGrants_reg_1_3;
wire as_inputArbGrants_reg_1_3$D_IN, as_inputArbGrants_reg_1_3$EN;
// register as_inputArbGrants_reg_1_4
reg as_inputArbGrants_reg_1_4;
wire as_inputArbGrants_reg_1_4$D_IN, as_inputArbGrants_reg_1_4$EN;
// register as_inputArbGrants_reg_2
reg as_inputArbGrants_reg_2;
wire as_inputArbGrants_reg_2$D_IN, as_inputArbGrants_reg_2$EN;
// register as_inputArbGrants_reg_2_1
reg as_inputArbGrants_reg_2_1;
wire as_inputArbGrants_reg_2_1$D_IN, as_inputArbGrants_reg_2_1$EN;
// register as_inputArbGrants_reg_2_2
reg as_inputArbGrants_reg_2_2;
wire as_inputArbGrants_reg_2_2$D_IN, as_inputArbGrants_reg_2_2$EN;
// register as_inputArbGrants_reg_2_3
reg as_inputArbGrants_reg_2_3;
wire as_inputArbGrants_reg_2_3$D_IN, as_inputArbGrants_reg_2_3$EN;
// register as_inputArbGrants_reg_2_4
reg as_inputArbGrants_reg_2_4;
wire as_inputArbGrants_reg_2_4$D_IN, as_inputArbGrants_reg_2_4$EN;
// register as_inputArbGrants_reg_3
reg as_inputArbGrants_reg_3;
wire as_inputArbGrants_reg_3$D_IN, as_inputArbGrants_reg_3$EN;
// register as_inputArbGrants_reg_3_1
reg as_inputArbGrants_reg_3_1;
wire as_inputArbGrants_reg_3_1$D_IN, as_inputArbGrants_reg_3_1$EN;
// register as_inputArbGrants_reg_3_2
reg as_inputArbGrants_reg_3_2;
wire as_inputArbGrants_reg_3_2$D_IN, as_inputArbGrants_reg_3_2$EN;
// register as_inputArbGrants_reg_3_3
reg as_inputArbGrants_reg_3_3;
wire as_inputArbGrants_reg_3_3$D_IN, as_inputArbGrants_reg_3_3$EN;
// register as_inputArbGrants_reg_3_4
reg as_inputArbGrants_reg_3_4;
wire as_inputArbGrants_reg_3_4$D_IN, as_inputArbGrants_reg_3_4$EN;
// register as_inputArbGrants_reg_4
reg as_inputArbGrants_reg_4;
wire as_inputArbGrants_reg_4$D_IN, as_inputArbGrants_reg_4$EN;
// register as_inputArbGrants_reg_4_1
reg as_inputArbGrants_reg_4_1;
wire as_inputArbGrants_reg_4_1$D_IN, as_inputArbGrants_reg_4_1$EN;
// register as_inputArbGrants_reg_4_2
reg as_inputArbGrants_reg_4_2;
wire as_inputArbGrants_reg_4_2$D_IN, as_inputArbGrants_reg_4_2$EN;
// register as_inputArbGrants_reg_4_3
reg as_inputArbGrants_reg_4_3;
wire as_inputArbGrants_reg_4_3$D_IN, as_inputArbGrants_reg_4_3$EN;
// register as_inputArbGrants_reg_4_4
reg as_inputArbGrants_reg_4_4;
wire as_inputArbGrants_reg_4_4$D_IN, as_inputArbGrants_reg_4_4$EN;
// ports of submodule inputArbs
wire [4 : 0] inputArbs$input_arbs_0_select,
inputArbs$input_arbs_0_select_requests,
inputArbs$input_arbs_1_select,
inputArbs$input_arbs_1_select_requests,
inputArbs$input_arbs_2_select,
inputArbs$input_arbs_2_select_requests,
inputArbs$input_arbs_3_select,
inputArbs$input_arbs_3_select_requests,
inputArbs$input_arbs_4_select,
inputArbs$input_arbs_4_select_requests;
wire inputArbs$EN_input_arbs_0_next,
inputArbs$EN_input_arbs_1_next,
inputArbs$EN_input_arbs_2_next,
inputArbs$EN_input_arbs_3_next,
inputArbs$EN_input_arbs_4_next;
// ports of submodule outputArbs
wire [4 : 0] outputArbs$output_arbs_0_select,
outputArbs$output_arbs_0_select_requests,
outputArbs$output_arbs_1_select,
outputArbs$output_arbs_1_select_requests,
outputArbs$output_arbs_2_select,
outputArbs$output_arbs_2_select_requests,
outputArbs$output_arbs_3_select,
outputArbs$output_arbs_3_select_requests,
outputArbs$output_arbs_4_select,
outputArbs$output_arbs_4_select_requests;
wire outputArbs$EN_output_arbs_0_next,
outputArbs$EN_output_arbs_1_next,
outputArbs$EN_output_arbs_2_next,
outputArbs$EN_output_arbs_3_next,
outputArbs$EN_output_arbs_4_next;
// actionvalue method allocate
assign allocate =
{ outputArbs$output_arbs_4_select[4],
outputArbs$output_arbs_3_select[4],
outputArbs$output_arbs_2_select[4],
outputArbs$output_arbs_1_select[4],
outputArbs$output_arbs_0_select[4],
outputArbs$output_arbs_4_select[3],
outputArbs$output_arbs_3_select[3],
outputArbs$output_arbs_2_select[3],
outputArbs$output_arbs_1_select[3],
outputArbs$output_arbs_0_select[3],
outputArbs$output_arbs_4_select[2],
outputArbs$output_arbs_3_select[2],
outputArbs$output_arbs_2_select[2],
outputArbs$output_arbs_1_select[2],
outputArbs$output_arbs_0_select[2],
outputArbs$output_arbs_4_select[1],
outputArbs$output_arbs_3_select[1],
outputArbs$output_arbs_2_select[1],
outputArbs$output_arbs_1_select[1],
outputArbs$output_arbs_0_select[1],
outputArbs$output_arbs_4_select[0],
outputArbs$output_arbs_3_select[0],
outputArbs$output_arbs_2_select[0],
outputArbs$output_arbs_1_select[0],
outputArbs$output_arbs_0_select[0] } ;
// submodule inputArbs
mkRouterInputArbitersRoundRobin inputArbs(.CLK(CLK),
.RST_N(RST_N),
.input_arbs_0_select_requests(inputArbs$input_arbs_0_select_requests),
.input_arbs_1_select_requests(inputArbs$input_arbs_1_select_requests),
.input_arbs_2_select_requests(inputArbs$input_arbs_2_select_requests),
.input_arbs_3_select_requests(inputArbs$input_arbs_3_select_requests),
.input_arbs_4_select_requests(inputArbs$input_arbs_4_select_requests),
.EN_input_arbs_0_next(inputArbs$EN_input_arbs_0_next),
.EN_input_arbs_1_next(inputArbs$EN_input_arbs_1_next),
.EN_input_arbs_2_next(inputArbs$EN_input_arbs_2_next),
.EN_input_arbs_3_next(inputArbs$EN_input_arbs_3_next),
.EN_input_arbs_4_next(inputArbs$EN_input_arbs_4_next),
.input_arbs_0_select(inputArbs$input_arbs_0_select),
.input_arbs_1_select(inputArbs$input_arbs_1_select),
.input_arbs_2_select(inputArbs$input_arbs_2_select),
.input_arbs_3_select(inputArbs$input_arbs_3_select),
.input_arbs_4_select(inputArbs$input_arbs_4_select));
// submodule outputArbs
mkRouterOutputArbitersRoundRobin outputArbs(.CLK(CLK),
.RST_N(RST_N),
.output_arbs_0_select_requests(outputArbs$output_arbs_0_select_requests),
.output_arbs_1_select_requests(outputArbs$output_arbs_1_select_requests),
.output_arbs_2_select_requests(outputArbs$output_arbs_2_select_requests),
.output_arbs_3_select_requests(outputArbs$output_arbs_3_select_requests),
.output_arbs_4_select_requests(outputArbs$output_arbs_4_select_requests),
.EN_output_arbs_0_next(outputArbs$EN_output_arbs_0_next),
.EN_output_arbs_1_next(outputArbs$EN_output_arbs_1_next),
.EN_output_arbs_2_next(outputArbs$EN_output_arbs_2_next),
.EN_output_arbs_3_next(outputArbs$EN_output_arbs_3_next),
.EN_output_arbs_4_next(outputArbs$EN_output_arbs_4_next),
.output_arbs_0_select(outputArbs$output_arbs_0_select),
.output_arbs_1_select(outputArbs$output_arbs_1_select),
.output_arbs_2_select(outputArbs$output_arbs_2_select),
.output_arbs_3_select(outputArbs$output_arbs_3_select),
.output_arbs_4_select(outputArbs$output_arbs_4_select));
// register as_inputArbGrants_reg_0
assign as_inputArbGrants_reg_0$D_IN = inputArbs$input_arbs_0_select[0] ;
assign as_inputArbGrants_reg_0$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_0_1
assign as_inputArbGrants_reg_0_1$D_IN = inputArbs$input_arbs_0_select[1] ;
assign as_inputArbGrants_reg_0_1$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_0_2
assign as_inputArbGrants_reg_0_2$D_IN = inputArbs$input_arbs_0_select[2] ;
assign as_inputArbGrants_reg_0_2$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_0_3
assign as_inputArbGrants_reg_0_3$D_IN = inputArbs$input_arbs_0_select[3] ;
assign as_inputArbGrants_reg_0_3$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_0_4
assign as_inputArbGrants_reg_0_4$D_IN = inputArbs$input_arbs_0_select[4] ;
assign as_inputArbGrants_reg_0_4$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_1
assign as_inputArbGrants_reg_1$D_IN = inputArbs$input_arbs_1_select[0] ;
assign as_inputArbGrants_reg_1$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_1_1
assign as_inputArbGrants_reg_1_1$D_IN = inputArbs$input_arbs_1_select[1] ;
assign as_inputArbGrants_reg_1_1$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_1_2
assign as_inputArbGrants_reg_1_2$D_IN = inputArbs$input_arbs_1_select[2] ;
assign as_inputArbGrants_reg_1_2$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_1_3
assign as_inputArbGrants_reg_1_3$D_IN = inputArbs$input_arbs_1_select[3] ;
assign as_inputArbGrants_reg_1_3$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_1_4
assign as_inputArbGrants_reg_1_4$D_IN = inputArbs$input_arbs_1_select[4] ;
assign as_inputArbGrants_reg_1_4$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_2
assign as_inputArbGrants_reg_2$D_IN = inputArbs$input_arbs_2_select[0] ;
assign as_inputArbGrants_reg_2$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_2_1
assign as_inputArbGrants_reg_2_1$D_IN = inputArbs$input_arbs_2_select[1] ;
assign as_inputArbGrants_reg_2_1$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_2_2
assign as_inputArbGrants_reg_2_2$D_IN = inputArbs$input_arbs_2_select[2] ;
assign as_inputArbGrants_reg_2_2$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_2_3
assign as_inputArbGrants_reg_2_3$D_IN = inputArbs$input_arbs_2_select[3] ;
assign as_inputArbGrants_reg_2_3$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_2_4
assign as_inputArbGrants_reg_2_4$D_IN = inputArbs$input_arbs_2_select[4] ;
assign as_inputArbGrants_reg_2_4$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_3
assign as_inputArbGrants_reg_3$D_IN = inputArbs$input_arbs_3_select[0] ;
assign as_inputArbGrants_reg_3$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_3_1
assign as_inputArbGrants_reg_3_1$D_IN = inputArbs$input_arbs_3_select[1] ;
assign as_inputArbGrants_reg_3_1$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_3_2
assign as_inputArbGrants_reg_3_2$D_IN = inputArbs$input_arbs_3_select[2] ;
assign as_inputArbGrants_reg_3_2$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_3_3
assign as_inputArbGrants_reg_3_3$D_IN = inputArbs$input_arbs_3_select[3] ;
assign as_inputArbGrants_reg_3_3$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_3_4
assign as_inputArbGrants_reg_3_4$D_IN = inputArbs$input_arbs_3_select[4] ;
assign as_inputArbGrants_reg_3_4$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_4
assign as_inputArbGrants_reg_4$D_IN = inputArbs$input_arbs_4_select[0] ;
assign as_inputArbGrants_reg_4$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_4_1
assign as_inputArbGrants_reg_4_1$D_IN = inputArbs$input_arbs_4_select[1] ;
assign as_inputArbGrants_reg_4_1$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_4_2
assign as_inputArbGrants_reg_4_2$D_IN = inputArbs$input_arbs_4_select[2] ;
assign as_inputArbGrants_reg_4_2$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_4_3
assign as_inputArbGrants_reg_4_3$D_IN = inputArbs$input_arbs_4_select[3] ;
assign as_inputArbGrants_reg_4_3$EN = EN_allocate && pipeline ;
// register as_inputArbGrants_reg_4_4
assign as_inputArbGrants_reg_4_4$D_IN = inputArbs$input_arbs_4_select[4] ;
assign as_inputArbGrants_reg_4_4$EN = EN_allocate && pipeline ;
// submodule inputArbs
assign inputArbs$input_arbs_0_select_requests = allocate_alloc_input[4:0] ;
assign inputArbs$input_arbs_1_select_requests = allocate_alloc_input[9:5] ;
assign inputArbs$input_arbs_2_select_requests =
allocate_alloc_input[14:10] ;
assign inputArbs$input_arbs_3_select_requests =
allocate_alloc_input[19:15] ;
assign inputArbs$input_arbs_4_select_requests =
allocate_alloc_input[24:20] ;
assign inputArbs$EN_input_arbs_0_next = EN_next ;
assign inputArbs$EN_input_arbs_1_next = EN_next ;
assign inputArbs$EN_input_arbs_2_next = EN_next ;
assign inputArbs$EN_input_arbs_3_next = EN_next ;
assign inputArbs$EN_input_arbs_4_next = EN_next ;
// submodule outputArbs
assign outputArbs$output_arbs_0_select_requests =
pipeline ?
{ as_inputArbGrants_reg_4,
as_inputArbGrants_reg_3,
as_inputArbGrants_reg_2,
as_inputArbGrants_reg_1,
as_inputArbGrants_reg_0 } :
{ inputArbs$input_arbs_4_select[0],
inputArbs$input_arbs_3_select[0],
inputArbs$input_arbs_2_select[0],
inputArbs$input_arbs_1_select[0],
inputArbs$input_arbs_0_select[0] } ;
assign outputArbs$output_arbs_1_select_requests =
pipeline ?
{ as_inputArbGrants_reg_4_1,
as_inputArbGrants_reg_3_1,
as_inputArbGrants_reg_2_1,
as_inputArbGrants_reg_1_1,
as_inputArbGrants_reg_0_1 } :
{ inputArbs$input_arbs_4_select[1],
inputArbs$input_arbs_3_select[1],
inputArbs$input_arbs_2_select[1],
inputArbs$input_arbs_1_select[1],
inputArbs$input_arbs_0_select[1] } ;
assign outputArbs$output_arbs_2_select_requests =
pipeline ?
{ as_inputArbGrants_reg_4_2,
as_inputArbGrants_reg_3_2,
as_inputArbGrants_reg_2_2,
as_inputArbGrants_reg_1_2,
as_inputArbGrants_reg_0_2 } :
{ inputArbs$input_arbs_4_select[2],
inputArbs$input_arbs_3_select[2],
inputArbs$input_arbs_2_select[2],
inputArbs$input_arbs_1_select[2],
inputArbs$input_arbs_0_select[2] } ;
assign outputArbs$output_arbs_3_select_requests =
pipeline ?
{ as_inputArbGrants_reg_4_3,
as_inputArbGrants_reg_3_3,
as_inputArbGrants_reg_2_3,
as_inputArbGrants_reg_1_3,
as_inputArbGrants_reg_0_3 } :
{ inputArbs$input_arbs_4_select[3],
inputArbs$input_arbs_3_select[3],
inputArbs$input_arbs_2_select[3],
inputArbs$input_arbs_1_select[3],
inputArbs$input_arbs_0_select[3] } ;
assign outputArbs$output_arbs_4_select_requests =
pipeline ?
{ as_inputArbGrants_reg_4_4,
as_inputArbGrants_reg_3_4,
as_inputArbGrants_reg_2_4,
as_inputArbGrants_reg_1_4,
as_inputArbGrants_reg_0_4 } :
{ inputArbs$input_arbs_4_select[4],
inputArbs$input_arbs_3_select[4],
inputArbs$input_arbs_2_select[4],
inputArbs$input_arbs_1_select[4],
inputArbs$input_arbs_0_select[4] } ;
assign outputArbs$EN_output_arbs_0_next = EN_next ;
assign outputArbs$EN_output_arbs_1_next = EN_next ;
assign outputArbs$EN_output_arbs_2_next = EN_next ;
assign outputArbs$EN_output_arbs_3_next = EN_next ;
assign outputArbs$EN_output_arbs_4_next = EN_next ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
as_inputArbGrants_reg_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_0_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_0_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_0_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_0_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_1_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_1_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_1_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_1_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_2_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_2_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_2_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_2_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_3_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_3_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_3_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_3_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_4_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_4_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_4_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
as_inputArbGrants_reg_4_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (as_inputArbGrants_reg_0$EN)
as_inputArbGrants_reg_0 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_0$D_IN;
if (as_inputArbGrants_reg_0_1$EN)
as_inputArbGrants_reg_0_1 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_0_1$D_IN;
if (as_inputArbGrants_reg_0_2$EN)
as_inputArbGrants_reg_0_2 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_0_2$D_IN;
if (as_inputArbGrants_reg_0_3$EN)
as_inputArbGrants_reg_0_3 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_0_3$D_IN;
if (as_inputArbGrants_reg_0_4$EN)
as_inputArbGrants_reg_0_4 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_0_4$D_IN;
if (as_inputArbGrants_reg_1$EN)
as_inputArbGrants_reg_1 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_1$D_IN;
if (as_inputArbGrants_reg_1_1$EN)
as_inputArbGrants_reg_1_1 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_1_1$D_IN;
if (as_inputArbGrants_reg_1_2$EN)
as_inputArbGrants_reg_1_2 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_1_2$D_IN;
if (as_inputArbGrants_reg_1_3$EN)
as_inputArbGrants_reg_1_3 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_1_3$D_IN;
if (as_inputArbGrants_reg_1_4$EN)
as_inputArbGrants_reg_1_4 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_1_4$D_IN;
if (as_inputArbGrants_reg_2$EN)
as_inputArbGrants_reg_2 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_2$D_IN;
if (as_inputArbGrants_reg_2_1$EN)
as_inputArbGrants_reg_2_1 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_2_1$D_IN;
if (as_inputArbGrants_reg_2_2$EN)
as_inputArbGrants_reg_2_2 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_2_2$D_IN;
if (as_inputArbGrants_reg_2_3$EN)
as_inputArbGrants_reg_2_3 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_2_3$D_IN;
if (as_inputArbGrants_reg_2_4$EN)
as_inputArbGrants_reg_2_4 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_2_4$D_IN;
if (as_inputArbGrants_reg_3$EN)
as_inputArbGrants_reg_3 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_3$D_IN;
if (as_inputArbGrants_reg_3_1$EN)
as_inputArbGrants_reg_3_1 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_3_1$D_IN;
if (as_inputArbGrants_reg_3_2$EN)
as_inputArbGrants_reg_3_2 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_3_2$D_IN;
if (as_inputArbGrants_reg_3_3$EN)
as_inputArbGrants_reg_3_3 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_3_3$D_IN;
if (as_inputArbGrants_reg_3_4$EN)
as_inputArbGrants_reg_3_4 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_3_4$D_IN;
if (as_inputArbGrants_reg_4$EN)
as_inputArbGrants_reg_4 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_4$D_IN;
if (as_inputArbGrants_reg_4_1$EN)
as_inputArbGrants_reg_4_1 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_4_1$D_IN;
if (as_inputArbGrants_reg_4_2$EN)
as_inputArbGrants_reg_4_2 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_4_2$D_IN;
if (as_inputArbGrants_reg_4_3$EN)
as_inputArbGrants_reg_4_3 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_4_3$D_IN;
if (as_inputArbGrants_reg_4_4$EN)
as_inputArbGrants_reg_4_4 <= `BSV_ASSIGNMENT_DELAY
as_inputArbGrants_reg_4_4$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
as_inputArbGrants_reg_0 = 1'h0;
as_inputArbGrants_reg_0_1 = 1'h0;
as_inputArbGrants_reg_0_2 = 1'h0;
as_inputArbGrants_reg_0_3 = 1'h0;
as_inputArbGrants_reg_0_4 = 1'h0;
as_inputArbGrants_reg_1 = 1'h0;
as_inputArbGrants_reg_1_1 = 1'h0;
as_inputArbGrants_reg_1_2 = 1'h0;
as_inputArbGrants_reg_1_3 = 1'h0;
as_inputArbGrants_reg_1_4 = 1'h0;
as_inputArbGrants_reg_2 = 1'h0;
as_inputArbGrants_reg_2_1 = 1'h0;
as_inputArbGrants_reg_2_2 = 1'h0;
as_inputArbGrants_reg_2_3 = 1'h0;
as_inputArbGrants_reg_2_4 = 1'h0;
as_inputArbGrants_reg_3 = 1'h0;
as_inputArbGrants_reg_3_1 = 1'h0;
as_inputArbGrants_reg_3_2 = 1'h0;
as_inputArbGrants_reg_3_3 = 1'h0;
as_inputArbGrants_reg_3_4 = 1'h0;
as_inputArbGrants_reg_4 = 1'h0;
as_inputArbGrants_reg_4_1 = 1'h0;
as_inputArbGrants_reg_4_2 = 1'h0;
as_inputArbGrants_reg_4_3 = 1'h0;
as_inputArbGrants_reg_4_4 = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkSepRouterAllocator
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:06:55 06/01/2016
// Design Name:
// Module Name: MUX
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MUX(
input clk,
input [7:0] Estado,
input [5:0] Cuenta_Segundos,
input [5:0] Cuenta_Minutos,
input [4:0] Cuenta_Horas,
input [4:0] Cuenta_Year,
input [3:0] Cuenta_Mes,
input [6:0] Cuenta_Dia,
output reg [7:0] Salida_1,
output reg [7:0] Salida_2,
output reg [7:0] Salida_3
);
always @(posedge clk)
if (Estado == 8'h6C || Estado == 8'h75)
begin
Salida_1 <= Cuenta_Segundos;
Salida_2 <= Cuenta_Minutos;
Salida_3 <= Cuenta_Horas;
end
else
begin
Salida_1 <= Cuenta_Year;
Salida_2 <= Cuenta_Mes;
Salida_3 <= Cuenta_Dia;
end
endmodule
|
`define NULL 0
`timescale 1ns / 1 ps
module pcs_top (
// Common for all 4 Channels
// Resets
input wire ffc_lane_tx_rst,
input wire [3:0] ffc_lane_rx_rst,
input wire ffc_trst,
input wire ffc_quad_rst,
input wire ffc_macro_rst,
// Clocks
input wire refclkp,
input wire refclkn,
output wire refclk,
input wire PCLK,
`ifdef ECP3
`ifdef Channel_0
output wire ff_tx_f_clk_0,
output wire ff_tx_h_clk_0,
`endif
`ifdef Channel_1
output wire ff_tx_f_clk_1,
output wire ff_tx_h_clk_1,
`endif
`ifdef Channel_2
output wire ff_tx_f_clk_2,
output wire ff_tx_h_clk_2,
`endif
`ifdef Channel_3
output wire ff_tx_f_clk_3,
output wire ff_tx_h_clk_3,
`endif
`else
output wire ff_tx_f_clk,
output wire ff_tx_h_clk,
`endif
input wire ffc_signal_detect,
input wire ffc_enb_cgalign,
output wire ffs_plol,
// SCI Interface
input wire sciwstn,
input wire [7:0] sciwritedata,
input wire [5:0] sciaddress,
input wire scienaux,
input wire sciselaux,
input wire scird,
output wire [7:0] scireaddata,
`ifdef Channel_0
input wire hdinp0,
input wire hdinn0,
input wire [7:0] TxData_ch0,
input wire TxDataK_ch0,
input wire TxCompliance_ch0,
input wire TxElecIdle_ch0,
input wire ffc_txpwdnb_0,
input wire ffc_rxpwdnb_0,
input wire ffc_rrst_ch0,
input wire ffc_pcie_ct_ch0,
input wire ffc_pcie_det_en_ch0,
input wire ffc_fb_loopback_ch0,
input wire RxPolarity_ch0,
input wire scisel_ch0,
input wire scien_ch0,
output wire ff_rx_fclk_ch0,
output wire hdoutp0,
output wire hdoutn0,
output wire [7:0] RxData_ch0,
output wire RxDataK_ch0,
output wire [2:0] RxStatus_ch0,
output wire RxValid_ch0,
output wire RxElecIdle_ch0,
output wire ffs_rlol_ch0,
output wire ffs_pcie_done_0,
output wire ffs_pcie_con_0,
`endif
`ifdef Channel_1
input wire hdinp1,
input wire hdinn1,
input wire [7:0] TxData_ch1,
input wire TxDataK_ch1,
input wire TxCompliance_ch1,
input wire TxElecIdle_ch1,
input wire ffc_txpwdnb_1,
input wire ffc_rxpwdnb_1,
input wire ffc_rrst_ch1,
input wire ffc_pcie_ct_ch1,
input wire ffc_pcie_det_en_ch1,
input wire ffc_fb_loopback_ch1,
input wire RxPolarity_ch1,
input wire scisel_ch1,
input wire scien_ch1,
output wire ff_rx_fclk_ch1,
output wire hdoutp1,
output wire hdoutn1,
output wire [7:0] RxData_ch1,
output wire RxDataK_ch1,
output wire [2:0] RxStatus_ch1,
output wire RxValid_ch1,
output wire RxElecIdle_ch1,
output wire ffs_rlol_ch1,
output wire ffs_pcie_done_1,
output wire ffs_pcie_con_1,
`endif
`ifdef Channel_2
input wire hdinp2,
input wire hdinn2,
input wire [7:0] TxData_ch2,
input wire TxDataK_ch2,
input wire TxCompliance_ch2,
input wire TxElecIdle_ch2,
input wire ffc_txpwdnb_2,
input wire ffc_rxpwdnb_2,
input wire ffc_rrst_ch2,
input wire ffc_pcie_ct_ch2,
input wire ffc_pcie_det_en_ch2,
input wire ffc_fb_loopback_ch2,
input wire RxPolarity_ch2,
input wire scisel_ch2,
input wire scien_ch2,
output wire ff_rx_fclk_ch2,
output wire hdoutp2,
output wire hdoutn2,
output wire [7:0] RxData_ch2,
output wire RxDataK_ch2,
output wire [2:0] RxStatus_ch2,
output wire RxValid_ch2,
output wire RxElecIdle_ch2,
output wire ffs_rlol_ch2,
output wire ffs_pcie_done_2,
output wire ffs_pcie_con_2,
`endif
`ifdef Channel_3
input wire hdinp3,
input wire hdinn3,
input wire [7:0] TxData_ch3,
input wire TxDataK_ch3,
input wire TxCompliance_ch3,
input wire TxElecIdle_ch3,
input wire ffc_txpwdnb_3,
input wire ffc_rxpwdnb_3,
input wire ffc_rrst_ch3,
input wire ffc_pcie_ct_ch3,
input wire ffc_pcie_det_en_ch3,
input wire ffc_fb_loopback_ch3,
input wire RxPolarity_ch3,
input wire scisel_ch3,
input wire scien_ch3,
output wire ff_rx_fclk_ch3,
output wire hdoutp3,
output wire hdoutn3,
output wire [7:0] RxData_ch3,
output wire RxDataK_ch3,
output wire [2:0] RxStatus_ch3,
output wire RxValid_ch3,
output wire RxElecIdle_ch3,
output wire ffs_rlol_ch3,
output wire ffs_pcie_done_3,
output wire ffs_pcie_con_3,
`endif
input wire [11:0] cin,
output wire [19:0] cout
) ;
// =============================================================================
//synopsys translate_off
`ifdef ECP3
`ifdef X1
parameter USER_CONFIG_FILE = "pcs_pipe_8b_x1.txt";
`else
parameter USER_CONFIG_FILE = "pcs_pipe_8b_x4.txt";
`endif
parameter QUAD_MODE = "SINGLE";
parameter PLL_SRC = "REFCLK_EXT";
parameter CH0_CDR_SRC = "REFCLK_EXT";
parameter CH1_CDR_SRC = "REFCLK_EXT";
parameter CH2_CDR_SRC = "REFCLK_EXT";
parameter CH3_CDR_SRC = "REFCLK_EXT";
defparam pcs_inst_0.CONFIG_FILE = USER_CONFIG_FILE;
defparam pcs_inst_0.QUAD_MODE = QUAD_MODE;
defparam pcs_inst_0.PLL_SRC = PLL_SRC;
defparam pcs_inst_0.CH0_CDR_SRC = CH0_CDR_SRC;
defparam pcs_inst_0.CH1_CDR_SRC = CH1_CDR_SRC;
defparam pcs_inst_0.CH2_CDR_SRC = CH2_CDR_SRC;
defparam pcs_inst_0.CH3_CDR_SRC = CH3_CDR_SRC;
`else
`ifdef X1
parameter USER_CONFIG_FILE = "pcs_pipe_8b_x1.txt";
defparam pcs_inst_0.CONFIG_FILE = USER_CONFIG_FILE;
`else
parameter USER_CONFIG_FILE = "pcs_pipe_8b_x4.txt";
defparam pcs_inst_0.CONFIG_FILE = USER_CONFIG_FILE;
`endif
`endif
integer file, r;
initial begin
file = $fopen(USER_CONFIG_FILE, "r");
if (file == `NULL) begin
$display ("ERROR : Auto configuration file for PCSC module not found.");
$display (" : PCSC internal configuration registers will not be ");
$display (" : initialized correctly during simulation!");
end
end
//synopsys translate_on
// =============================================================================
// Wires
// =============================================================================
wire pcs_refclkp, pcs_refclkn, pcs_PCLK ;
wire pcs_ffc_lane_tx_rst ;
wire [3:0] pcs_ffc_lane_rx_rst ;
wire pcs_ffc_macro_rst, pcs_ffc_quad_rst, pcs_ffc_trst ;
`ifdef ECP3
wire pcs_ff_tx_f_clk_0, pcs_ff_tx_h_clk_0;
wire pcs_ff_tx_f_clk_1, pcs_ff_tx_h_clk_1;
wire pcs_ff_tx_f_clk_2, pcs_ff_tx_h_clk_2;
wire pcs_ff_tx_f_clk_3, pcs_ff_tx_h_clk_3;
`else
wire pcs_ff_tx_f_clk, pcs_ff_tx_h_clk;
`endif
wire pcs_ffc_signal_detect, pcs_ffc_enb_cgalign, pcs_ffs_plol ;
// SCI
wire [7:0] pcs_sciwritedata, pcs_scireaddata ;
wire [5:0] pcs_sciaddress ;
wire pcs_scienaux, pcs_sciselaux, pcs_scird, pcs_sciwstn ;
//CH0/CH1/CH2/CH3
wire pcs_hdinp0, pcs_hdinp1, pcs_hdinp2, pcs_hdinp3 ;
wire pcs_hdinn0, pcs_hdinn1, pcs_hdinn2, pcs_hdinn3 ;
wire pcs_hdoutp0, pcs_hdoutp1, pcs_hdoutp2, pcs_hdoutp3 ;
wire pcs_hdoutn0, pcs_hdoutn1, pcs_hdoutn2, pcs_hdoutn3 ;
wire pcs_scisel_ch0, pcs_scisel_ch1, pcs_scisel_ch2, pcs_scisel_ch3 ;
wire pcs_scien_ch0, pcs_scien_ch1, pcs_scien_ch2, pcs_scien_ch3 ;
wire pcs_ff_rx_fclk_ch0, pcs_ff_rx_fclk_ch1, pcs_ff_rx_fclk_ch2, pcs_ff_rx_fclk_ch3 ;
wire [7:0] pcs_TxData_ch0, pcs_TxData_ch1,pcs_TxData_ch2,pcs_TxData_ch3 ;
wire pcs_TxDataK_ch0, pcs_TxDataK_ch1, pcs_TxDataK_ch2, pcs_TxDataK_ch3 ;
wire pcs_TxCompliance_ch0, pcs_TxCompliance_ch1, pcs_TxCompliance_ch2, pcs_TxCompliance_ch3 ;
wire pcs_TxElecIdle_ch0, pcs_TxElecIdle_ch1, pcs_TxElecIdle_ch2, pcs_TxElecIdle_ch3 ;
wire [7:0] pcs_RxData_ch0, pcs_RxData_ch1, pcs_RxData_ch2, pcs_RxData_ch3 ;
wire pcs_RxDataK_ch0, pcs_RxDataK_ch1, pcs_RxDataK_ch2, pcs_RxDataK_ch3 ;
wire [2:0] pcs_RxStatus_ch0, pcs_RxStatus_ch1, pcs_RxStatus_ch2, pcs_RxStatus_ch3 ;
wire pcs_ffc_rrst_ch0, pcs_ffc_rrst_ch1, pcs_ffc_rrst_ch2, pcs_ffc_rrst_ch3 ;
wire pcs_ffc_fb_loopback_ch0, pcs_ffc_fb_loopback_ch1, pcs_ffc_fb_loopback_ch2, pcs_ffc_fb_loopback_ch3;
wire pcs_RxPolarity_ch0, pcs_RxPolarity_ch1, pcs_RxPolarity_ch2, pcs_RxPolarity_ch3 ;
wire pcs_ffc_pcie_ct_ch0, pcs_ffc_pcie_ct_ch1, pcs_ffc_pcie_ct_ch2, pcs_ffc_pcie_ct_ch3 ;
wire pcs_ffc_pcie_det_en_ch0, pcs_ffc_pcie_det_en_ch1, pcs_ffc_pcie_det_en_ch2, pcs_ffc_pcie_det_en_ch3 ;
wire pcs_ffs_pcie_done_0, pcs_ffs_pcie_done_1, pcs_ffs_pcie_done_2, pcs_ffs_pcie_done_3 ;
wire pcs_ffs_pcie_con_0, pcs_ffs_pcie_con_1, pcs_ffs_pcie_con_2, pcs_ffs_pcie_con_3 ;
wire pcs_ffc_txpwdnb_0, pcs_ffc_txpwdnb_1, pcs_ffc_txpwdnb_2, pcs_ffc_txpwdnb_3 ;
wire pcs_ffc_rxpwdnb_0, pcs_ffc_rxpwdnb_1, pcs_ffc_rxpwdnb_2, pcs_ffc_rxpwdnb_3 ;
wire pcs_RxElecIdle_ch0, pcs_RxElecIdle_ch1, pcs_RxElecIdle_ch2, pcs_RxElecIdle_ch3 ;
wire pcs_RxValid_ch0, pcs_RxValid_ch1, pcs_RxValid_ch2, pcs_RxValid_ch3 ;
wire pcs_ffs_rlol_ch0 ,pcs_ffs_rlol_ch1, pcs_ffs_rlol_ch2, pcs_ffs_rlol_ch3 ;
wire [11:0] pcs_cin ;
wire [19:0] pcs_cout ;
// =============================================================================
// PCS Connections
// =============================================================================
// Inputs
assign pcs_refclkp = refclkp ;
assign pcs_refclkn = refclkn ;
assign pcs_PCLK = PCLK ;
assign pcs_ffc_lane_tx_rst = ffc_lane_tx_rst;
assign pcs_ffc_lane_rx_rst = ffc_lane_rx_rst;
assign pcs_ffc_macro_rst = ffc_macro_rst;
assign pcs_ffc_quad_rst = ffc_quad_rst;
assign pcs_ffc_trst = ffc_trst;
assign pcs_ffc_signal_detect = ffc_signal_detect;
assign pcs_ffc_enb_cgalign = ffc_enb_cgalign;
assign pcs_sciwritedata = sciwritedata;
assign pcs_sciaddress = sciaddress;
assign pcs_scienaux = scienaux;
assign pcs_sciselaux = sciselaux;
assign pcs_scird = scird;
assign pcs_sciwstn = sciwstn;
assign pcs_cin = cin;
// Outputs
`ifdef ECP3
`ifdef Channel_0
assign ff_tx_f_clk_0 = pcs_ff_tx_f_clk_0;
assign ff_tx_h_clk_0 = pcs_ff_tx_h_clk_0;
`endif
`ifdef Channel_1
assign ff_tx_f_clk_1 = pcs_ff_tx_f_clk_1;
assign ff_tx_h_clk_1 = pcs_ff_tx_h_clk_1;
`endif
`ifdef Channel_2
assign ff_tx_f_clk_2 = pcs_ff_tx_f_clk_2;
assign ff_tx_h_clk_2 = pcs_ff_tx_h_clk_2;
`endif
`ifdef Channel_3
assign ff_tx_f_clk_3 = pcs_ff_tx_f_clk_3;
assign ff_tx_h_clk_3 = pcs_ff_tx_h_clk_3;
`endif
`else
assign ff_tx_f_clk = pcs_ff_tx_f_clk;
assign ff_tx_h_clk = pcs_ff_tx_h_clk;
`endif
assign ffs_plol = pcs_ffs_plol;
assign scireaddata = pcs_scireaddata;
assign cout = pcs_cout;
// ========================================================
`ifdef Channel_0
// Inputs
assign pcs_hdinp0 = hdinp0 ;
assign pcs_hdinn0 = hdinn0 ;
assign pcs_TxData_ch0 = TxData_ch0 ;
assign pcs_TxDataK_ch0 = TxDataK_ch0 ;
assign pcs_TxCompliance_ch0 = TxCompliance_ch0 ;
assign pcs_TxElecIdle_ch0 = TxElecIdle_ch0 ;
assign pcs_ffc_txpwdnb_0 = ffc_txpwdnb_0 ;
assign pcs_ffc_rxpwdnb_0 = ffc_rxpwdnb_0 ;
assign pcs_ffc_rrst_ch0 = ffc_rrst_ch0 ;
assign pcs_ffc_pcie_ct_ch0 = ffc_pcie_ct_ch0 ;
assign pcs_ffc_pcie_det_en_ch0 = ffc_pcie_det_en_ch0 ;
assign pcs_ffc_fb_loopback_ch0 = ffc_fb_loopback_ch0 ;
assign pcs_RxPolarity_ch0 = RxPolarity_ch0 ;
assign pcs_scisel_ch0 = scisel_ch0 ;
assign pcs_scien_ch0 = scien_ch0 ;
// Outputs
assign hdoutp0 = pcs_hdoutp0 ;
assign hdoutn0 = pcs_hdoutn0 ;
assign RxData_ch0 = pcs_RxData_ch0 ;
assign RxDataK_ch0 = pcs_RxDataK_ch0 ;
assign RxStatus_ch0 = pcs_RxStatus_ch0 ;
assign RxValid_ch0 = pcs_RxValid_ch0 ;
assign RxElecIdle_ch0 = pcs_RxElecIdle_ch0 ;
assign ffs_rlol_ch0 = pcs_ffs_rlol_ch0 ;
assign ffs_pcie_done_0 = pcs_ffs_pcie_done_0 ;
assign ff_rx_fclk_ch0 = pcs_ff_rx_fclk_ch0 ;
assign ffs_pcie_con_0 = pcs_ffs_pcie_con_0 ;
`else
// Inputs
assign pcs_hdinp0 = 'd0 ;
assign pcs_hdinn0 = 'd0 ;
assign pcs_TxData_ch0 = 'd0 ;
assign pcs_TxDataK_ch0 = 'd0 ;
assign pcs_TxCompliance_ch0 = 'd0 ;
assign pcs_TxElecIdle_ch0 = 'd0 ;
assign pcs_ffc_txpwdnb_0 = 'd0 ;
assign pcs_ffc_rxpwdnb_0 = 'd0 ;
assign pcs_ffc_rrst_ch0 = 'd0 ;
assign pcs_ffc_pcie_ct_ch0 = 'd0 ;
assign pcs_ffc_pcie_det_en_ch0 = 'd0 ;
assign pcs_ffc_fb_loopback_ch0 = 'd0 ;
assign pcs_RxPolarity_ch0 = 'd0 ;
assign pcs_scisel_ch0 = 'd0 ;
assign pcs_scien_ch0 = 'd0 ;
`endif
// ========================================================
`ifdef Channel_1
// Inputs
assign pcs_hdinp1 = hdinp1 ;
assign pcs_hdinn1 = hdinn1 ;
assign pcs_TxData_ch1 = TxData_ch1 ;
assign pcs_TxDataK_ch1 = TxDataK_ch1 ;
assign pcs_TxCompliance_ch1 = TxCompliance_ch1 ;
assign pcs_TxElecIdle_ch1 = TxElecIdle_ch1 ;
assign pcs_ffc_txpwdnb_1 = ffc_txpwdnb_1 ;
assign pcs_ffc_rxpwdnb_1 = ffc_rxpwdnb_1 ;
assign pcs_ffc_rrst_ch1 = ffc_rrst_ch1 ;
assign pcs_ffc_pcie_ct_ch1 = ffc_pcie_ct_ch1 ;
assign pcs_ffc_pcie_det_en_ch1 = ffc_pcie_det_en_ch1 ;
assign pcs_ffc_fb_loopback_ch1 = ffc_fb_loopback_ch1 ;
assign pcs_RxPolarity_ch1 = RxPolarity_ch1 ;
assign pcs_scisel_ch1 = scisel_ch1 ;
assign pcs_scien_ch1 = scien_ch1 ;
// Outputs
assign hdoutp1 = pcs_hdoutp1 ;
assign hdoutn1 = pcs_hdoutn1 ;
assign RxData_ch1 = pcs_RxData_ch1 ;
assign RxDataK_ch1 = pcs_RxDataK_ch1 ;
assign RxStatus_ch1 = pcs_RxStatus_ch1 ;
assign RxValid_ch1 = pcs_RxValid_ch1 ;
assign RxElecIdle_ch1 = pcs_RxElecIdle_ch1 ;
assign ffs_rlol_ch1 = pcs_ffs_rlol_ch1 ;
assign ffs_pcie_done_1 = pcs_ffs_pcie_done_1 ;
assign ff_rx_fclk_ch1 = pcs_ff_rx_fclk_ch1 ;
assign ffs_pcie_con_1 = pcs_ffs_pcie_con_1 ;
`else
// Inputs
assign pcs_hdinp1 = 'd0 ;
assign pcs_hdinn1 = 'd0 ;
assign pcs_TxData_ch1 = 'd0 ;
assign pcs_TxDataK_ch1 = 'd0 ;
assign pcs_TxCompliance_ch1 = 'd0 ;
assign pcs_TxElecIdle_ch1 = 'd0 ;
assign pcs_ffc_txpwdnb_1 = 'd0 ;
assign pcs_ffc_rxpwdnb_1 = 'd0 ;
assign pcs_ffc_rrst_ch1 = 'd0 ;
assign pcs_ffc_pcie_ct_ch1 = 'd0 ;
assign pcs_ffc_pcie_det_en_ch1 = 'd0 ;
assign pcs_ffc_fb_loopback_ch1 = 'd0 ;
assign pcs_RxPolarity_ch1 = 'd0 ;
assign pcs_scisel_ch1 = 'd0 ;
assign pcs_scien_ch1 = 'd0 ;
`endif
// ========================================================
`ifdef Channel_2
// Inputs
assign pcs_hdinp2 = hdinp2 ;
assign pcs_hdinn2 = hdinn2 ;
assign pcs_TxData_ch2 = TxData_ch2 ;
assign pcs_TxDataK_ch2 = TxDataK_ch2 ;
assign pcs_TxCompliance_ch2 = TxCompliance_ch2 ;
assign pcs_TxElecIdle_ch2 = TxElecIdle_ch2 ;
assign pcs_ffc_txpwdnb_2 = ffc_txpwdnb_2 ;
assign pcs_ffc_rxpwdnb_2 = ffc_rxpwdnb_2 ;
assign pcs_ffc_rrst_ch2 = ffc_rrst_ch2 ;
assign pcs_ffc_pcie_ct_ch2 = ffc_pcie_ct_ch2 ;
assign pcs_ffc_pcie_det_en_ch2 = ffc_pcie_det_en_ch2 ;
assign pcs_ffc_fb_loopback_ch2 = ffc_fb_loopback_ch2 ;
assign pcs_RxPolarity_ch2 = RxPolarity_ch2 ;
assign pcs_scisel_ch2 = scisel_ch2 ;
assign pcs_scien_ch2 = scien_ch2 ;
// Outputs
assign hdoutp2 = pcs_hdoutp2 ;
assign hdoutn2 = pcs_hdoutn2 ;
assign RxData_ch2 = pcs_RxData_ch2 ;
assign RxDataK_ch2 = pcs_RxDataK_ch2 ;
assign RxStatus_ch2 = pcs_RxStatus_ch2 ;
assign RxValid_ch2 = pcs_RxValid_ch2 ;
assign RxElecIdle_ch2 = pcs_RxElecIdle_ch2 ;
assign ffs_rlol_ch2 = pcs_ffs_rlol_ch2 ;
assign ffs_pcie_done_2 = pcs_ffs_pcie_done_2 ;
assign ff_rx_fclk_ch2 = pcs_ff_rx_fclk_ch2 ;
assign ffs_pcie_con_2 = pcs_ffs_pcie_con_2 ;
`else
// Inputs
assign pcs_hdinp2 = 'd0 ;
assign pcs_hdinn2 = 'd0 ;
assign pcs_TxData_ch2 = 'd0 ;
assign pcs_TxDataK_ch2 = 'd0 ;
assign pcs_TxCompliance_ch2 = 'd0 ;
assign pcs_TxElecIdle_ch2 = 'd0 ;
assign pcs_ffc_txpwdnb_2 = 'd0 ;
assign pcs_ffc_rxpwdnb_2 = 'd0 ;
assign pcs_ffc_rrst_ch2 = 'd0 ;
assign pcs_ffc_pcie_ct_ch2 = 'd0 ;
assign pcs_ffc_pcie_det_en_ch2 = 'd0 ;
assign pcs_ffc_fb_loopback_ch2 = 'd0 ;
assign pcs_RxPolarity_ch2 = 'd0 ;
assign pcs_scisel_ch2 = 'd0 ;
assign pcs_scien_ch2 = 'd0 ;
`endif
// ========================================================
`ifdef Channel_3
// Inputs
assign pcs_hdinp3 = hdinp3 ;
assign pcs_hdinn3 = hdinn3 ;
assign pcs_TxData_ch3 = TxData_ch3 ;
assign pcs_TxDataK_ch3 = TxDataK_ch3 ;
assign pcs_TxCompliance_ch3 = TxCompliance_ch3 ;
assign pcs_TxElecIdle_ch3 = TxElecIdle_ch3 ;
assign pcs_ffc_txpwdnb_3 = ffc_txpwdnb_3 ;
assign pcs_ffc_rxpwdnb_3 = ffc_rxpwdnb_3 ;
assign pcs_ffc_rrst_ch3 = ffc_rrst_ch3 ;
assign pcs_ffc_pcie_ct_ch3 = ffc_pcie_ct_ch3 ;
assign pcs_ffc_pcie_det_en_ch3 = ffc_pcie_det_en_ch3 ;
assign pcs_ffc_fb_loopback_ch3 = ffc_fb_loopback_ch3 ;
assign pcs_RxPolarity_ch3 = RxPolarity_ch3 ;
assign pcs_scisel_ch3 = scisel_ch3 ;
assign pcs_scien_ch3 = scien_ch3 ;
// Outputs
assign hdoutp3 = pcs_hdoutp3 ;
assign hdoutn3 = pcs_hdoutn3 ;
assign RxData_ch3 = pcs_RxData_ch3 ;
assign RxDataK_ch3 = pcs_RxDataK_ch3 ;
assign RxStatus_ch3 = pcs_RxStatus_ch3 ;
assign RxValid_ch3 = pcs_RxValid_ch3 ;
assign RxElecIdle_ch3 = pcs_RxElecIdle_ch3 ;
assign ffs_rlol_ch3 = pcs_ffs_rlol_ch3 ;
assign ffs_pcie_done_3 = pcs_ffs_pcie_done_3 ;
assign ff_rx_fclk_ch3 = pcs_ff_rx_fclk_ch3 ;
assign ffs_pcie_con_3 = pcs_ffs_pcie_con_3 ;
`else
// Inputs
assign pcs_hdinp3 = 'd0 ;
assign pcs_hdinn3 = 'd0 ;
assign pcs_TxData_ch3 = 'd0 ;
assign pcs_TxDataK_ch3 = 'd0 ;
assign pcs_TxCompliance_ch3 = 'd0 ;
assign pcs_TxElecIdle_ch3 = 'd0 ;
assign pcs_ffc_txpwdnb_3 = 'd0 ;
assign pcs_ffc_rxpwdnb_3 = 'd0 ;
assign pcs_ffc_rrst_ch3 = 'd0 ;
assign pcs_ffc_pcie_ct_ch3 = 'd0 ;
assign pcs_ffc_pcie_det_en_ch3 = 'd0 ;
assign pcs_ffc_fb_loopback_ch3 = 'd0 ;
assign pcs_RxPolarity_ch3 = 'd0 ;
assign pcs_scisel_ch3 = 'd0 ;
assign pcs_scien_ch3 = 'd0 ;
`endif
// =============================================================================
// PCS instantiation
// =============================================================================
`ifdef ECP3
`define PCS_CD PCSD
`else
`define PCS_CD PCSC
`endif
`PCS_CD pcs_inst_0 (
.REFCLKP ( pcs_refclkp ),
.REFCLKN ( pcs_refclkn ),
.FFC_CK_CORE_TX ( 1'b0 ),
//CH0
.HDINP0 ( pcs_hdinp0 ),
.HDINN0 ( pcs_hdinn0 ),
.HDOUTP0 ( pcs_hdoutp0 ),
.HDOUTN0 ( pcs_hdoutn0 ),
`ifdef ECP3
.PCIE_TXDETRX_PR2TLB_0 ( 1'b0 ),
.PCIE_TXCOMPLIANCE_0 ( 1'b0 ),
.PCIE_RXPOLARITY_0 ( 1'b0 ),
.PCIE_POWERDOWN_0_0 ( 1'b0 ),
.PCIE_POWERDOWN_0_1 ( 1'b0 ),
.PCIE_RXVALID_0 ( ),
.PCIE_PHYSTATUS_0 ( ),
.FF_TX_F_CLK_0 ( pcs_ff_tx_f_clk_0 ),
.FF_TX_H_CLK_0 ( pcs_ff_tx_h_clk_0 ),
.FFC_CK_CORE_RX_0 ( 1'b0 ),
.FFS_RLOS_HI_0 ( ),
.FFS_SKP_ADDED_0 ( ),
.FFS_SKP_DELETED_0 ( ),
.LDR_CORE2TX_0 ( 1'b0 ),
.FFC_LDR_CORE2TX_EN_0 ( 1'b0 ),
.LDR_RX2CORE_0 ( ),
.FFS_CDR_TRAIN_DONE_0 ( ),
.FFC_DIV11_MODE_TX_0 ( 1'b0 ),
.FFC_RATE_MODE_TX_0 ( 1'b0 ),
.FFC_DIV11_MODE_RX_0 ( 1'b0 ),
.FFC_RATE_MODE_RX_0 ( 1'b0 ),
`else
.FF_RX_Q_CLK_0 ( ),
.OOB_OUT_0 ( ),
`endif
.SCISELCH0 ( pcs_scisel_ch0 ),
.SCIENCH0 ( pcs_scien_ch0 ),
.FF_TXI_CLK_0 ( pcs_PCLK ),
`ifdef X4
.FF_RXI_CLK_0 ( pcs_ff_rx_fclk_ch0 ),
.FF_EBRD_CLK_0 ( 1'b0 ),
`else
.FF_RXI_CLK_0 ( pcs_PCLK ),
.FF_EBRD_CLK_0 ( pcs_PCLK ),
`endif
.FF_RX_F_CLK_0 ( pcs_ff_rx_fclk_ch0 ),
.FF_RX_H_CLK_0 ( ),
.FF_TX_D_0_0 ( pcs_TxData_ch0[0] ),
.FF_TX_D_0_1 ( pcs_TxData_ch0[1] ),
.FF_TX_D_0_2 ( pcs_TxData_ch0[2] ),
.FF_TX_D_0_3 ( pcs_TxData_ch0[3] ),
.FF_TX_D_0_4 ( pcs_TxData_ch0[4] ),
.FF_TX_D_0_5 ( pcs_TxData_ch0[5] ),
.FF_TX_D_0_6 ( pcs_TxData_ch0[6] ),
.FF_TX_D_0_7 ( pcs_TxData_ch0[7] ),
.FF_TX_D_0_8 ( pcs_TxDataK_ch0 ),
.FF_TX_D_0_9 ( pcs_TxCompliance_ch0 ),
.FF_TX_D_0_10 ( 1'b0 ),
.FF_TX_D_0_11 ( pcs_TxElecIdle_ch0 ),
.FF_TX_D_0_12 ( 1'b0 ),
.FF_TX_D_0_13 ( 1'b0 ),
.FF_TX_D_0_14 ( 1'b0 ),
.FF_TX_D_0_15 ( 1'b0 ),
.FF_TX_D_0_16 ( 1'b0 ),
.FF_TX_D_0_17 ( 1'b0 ),
.FF_TX_D_0_18 ( 1'b0 ),
.FF_TX_D_0_19 ( 1'b0 ),
.FF_TX_D_0_20 ( 1'b0 ),
.FF_TX_D_0_21 ( 1'b0 ),
.FF_TX_D_0_22 ( 1'b0 ),
.FF_TX_D_0_23 ( 1'b0 ),
.FF_RX_D_0_0 ( pcs_RxData_ch0[0] ),
.FF_RX_D_0_1 ( pcs_RxData_ch0[1] ),
.FF_RX_D_0_2 ( pcs_RxData_ch0[2] ),
.FF_RX_D_0_3 ( pcs_RxData_ch0[3] ),
.FF_RX_D_0_4 ( pcs_RxData_ch0[4] ),
.FF_RX_D_0_5 ( pcs_RxData_ch0[5] ),
.FF_RX_D_0_6 ( pcs_RxData_ch0[6] ),
.FF_RX_D_0_7 ( pcs_RxData_ch0[7] ),
.FF_RX_D_0_8 ( pcs_RxDataK_ch0 ),
.FF_RX_D_0_9 ( pcs_RxStatus_ch0[0] ),
.FF_RX_D_0_10 ( pcs_RxStatus_ch0[1] ),
.FF_RX_D_0_11 ( pcs_RxStatus_ch0[2] ),
.FF_RX_D_0_12 ( ),
.FF_RX_D_0_13 ( ),
.FF_RX_D_0_14 ( ),
.FF_RX_D_0_15 ( ),
.FF_RX_D_0_16 ( ),
.FF_RX_D_0_17 ( ),
.FF_RX_D_0_18 ( ),
.FF_RX_D_0_19 ( ),
.FF_RX_D_0_20 ( ),
.FF_RX_D_0_21 ( ),
.FF_RX_D_0_22 ( ),
.FF_RX_D_0_23 ( ),
.FFC_RRST_0 ( pcs_ffc_rrst_ch0 ),
.FFC_SIGNAL_DETECT_0 ( pcs_ffc_signal_detect ),
.FFC_ENABLE_CGALIGN_0 ( pcs_ffc_enb_cgalign ),
.FFC_SB_PFIFO_LP_0 ( 1'b0 ),
.FFC_PFIFO_CLR_0 ( 1'b0 ),
.FFC_FB_LOOPBACK_0 ( pcs_ffc_fb_loopback_ch0),
.FFC_SB_INV_RX_0 ( pcs_RxPolarity_ch0 ),
.FFC_PCIE_CT_0 ( pcs_ffc_pcie_ct_ch0 ),
.FFC_PCI_DET_EN_0 ( pcs_ffc_pcie_det_en_ch0 ),
.FFS_PCIE_DONE_0 ( pcs_ffs_pcie_done_0 ),
.FFS_PCIE_CON_0 ( pcs_ffs_pcie_con_0 ),
.FFC_EI_EN_0 ( 1'b0 ),
.FFC_LANE_TX_RST_0 ( pcs_ffc_lane_tx_rst ),
.FFC_LANE_RX_RST_0 ( pcs_ffc_lane_rx_rst[0] ),
.FFC_TXPWDNB_0 ( pcs_ffc_txpwdnb_0 ),
.FFC_RXPWDNB_0 ( pcs_ffc_rxpwdnb_0 ),
.FFS_RLOS_LO_0 ( pcs_RxElecIdle_ch0 ),
.FFS_LS_SYNC_STATUS_0 ( pcs_RxValid_ch0 ),
.FFS_CC_UNDERRUN_0 ( ),
.FFS_CC_OVERRUN_0 ( ),
.FFS_RXFBFIFO_ERROR_0 ( ),
.FFS_TXFBFIFO_ERROR_0 ( ),
.FFS_RLOL_0 ( pcs_ffs_rlol_ch0 ),
//CH1
.HDINP1 ( pcs_hdinp1 ),
.HDINN1 ( pcs_hdinn1 ),
.HDOUTP1 ( pcs_hdoutp1 ),
.HDOUTN1 ( pcs_hdoutn1 ),
`ifdef ECP3
.PCIE_TXDETRX_PR2TLB_1 ( 1'b0 ),
.PCIE_TXCOMPLIANCE_1 ( 1'b0 ),
.PCIE_RXPOLARITY_1 ( 1'b0 ),
.PCIE_POWERDOWN_1_0 ( 1'b0 ),
.PCIE_POWERDOWN_1_1 ( 1'b0 ),
.PCIE_RXVALID_1 ( ),
.PCIE_PHYSTATUS_1 ( ),
.FF_TX_F_CLK_1 ( pcs_ff_tx_f_clk_1 ),
.FF_TX_H_CLK_1 ( pcs_ff_tx_h_clk_1 ),
.FFC_CK_CORE_RX_1 ( 1'b0 ),
.FFS_RLOS_HI_1 ( ),
.FFS_SKP_ADDED_1 ( ),
.FFS_SKP_DELETED_1 ( ),
.LDR_CORE2TX_1 ( 1'b0 ),
.FFC_LDR_CORE2TX_EN_1 ( 1'b0 ),
.LDR_RX2CORE_1 ( ),
.FFS_CDR_TRAIN_DONE_1 ( ),
.FFC_DIV11_MODE_TX_1 ( 1'b0 ),
.FFC_RATE_MODE_TX_1 ( 1'b0 ),
.FFC_DIV11_MODE_RX_1 ( 1'b0 ),
.FFC_RATE_MODE_RX_1 ( 1'b0 ),
`else
.FF_RX_Q_CLK_1 ( ),
.OOB_OUT_1 ( ),
`endif
.SCISELCH1 ( pcs_scisel_ch1 ),
.SCIENCH1 ( pcs_scien_ch1 ),
.FF_TXI_CLK_1 ( pcs_PCLK ),
`ifdef X4
.FF_RXI_CLK_1 ( pcs_ff_rx_fclk_ch1 ),
.FF_EBRD_CLK_1 ( 1'b0 ),
`else
.FF_RXI_CLK_1 ( pcs_PCLK ),
.FF_EBRD_CLK_1 ( pcs_PCLK ),
`endif
.FF_RX_F_CLK_1 ( pcs_ff_rx_fclk_ch1 ),
.FF_RX_H_CLK_1 ( ),
.FF_TX_D_1_0 ( pcs_TxData_ch1[0] ),
.FF_TX_D_1_1 ( pcs_TxData_ch1[1] ),
.FF_TX_D_1_2 ( pcs_TxData_ch1[2] ),
.FF_TX_D_1_3 ( pcs_TxData_ch1[3] ),
.FF_TX_D_1_4 ( pcs_TxData_ch1[4] ),
.FF_TX_D_1_5 ( pcs_TxData_ch1[5] ),
.FF_TX_D_1_6 ( pcs_TxData_ch1[6] ),
.FF_TX_D_1_7 ( pcs_TxData_ch1[7] ),
.FF_TX_D_1_8 ( pcs_TxDataK_ch1 ),
.FF_TX_D_1_9 ( pcs_TxCompliance_ch1 ),
.FF_TX_D_1_10 ( 1'b0 ),
.FF_TX_D_1_11 ( pcs_TxElecIdle_ch1 ),
.FF_TX_D_1_12 ( 1'b0 ),
.FF_TX_D_1_13 ( 1'b0 ),
.FF_TX_D_1_14 ( 1'b0 ),
.FF_TX_D_1_15 ( 1'b0 ),
.FF_TX_D_1_16 ( 1'b0 ),
.FF_TX_D_1_17 ( 1'b0 ),
.FF_TX_D_1_18 ( 1'b0 ),
.FF_TX_D_1_19 ( 1'b0 ),
.FF_TX_D_1_20 ( 1'b0 ),
.FF_TX_D_1_21 ( 1'b0 ),
.FF_TX_D_1_22 ( 1'b0 ),
.FF_TX_D_1_23 ( 1'b0 ),
.FF_RX_D_1_0 ( pcs_RxData_ch1[0] ),
.FF_RX_D_1_1 ( pcs_RxData_ch1[1] ),
.FF_RX_D_1_2 ( pcs_RxData_ch1[2] ),
.FF_RX_D_1_3 ( pcs_RxData_ch1[3] ),
.FF_RX_D_1_4 ( pcs_RxData_ch1[4] ),
.FF_RX_D_1_5 ( pcs_RxData_ch1[5] ),
.FF_RX_D_1_6 ( pcs_RxData_ch1[6] ),
.FF_RX_D_1_7 ( pcs_RxData_ch1[7] ),
.FF_RX_D_1_8 ( pcs_RxDataK_ch1 ),
.FF_RX_D_1_9 ( pcs_RxStatus_ch1[0] ),
.FF_RX_D_1_10 ( pcs_RxStatus_ch1[1] ),
.FF_RX_D_1_11 ( pcs_RxStatus_ch1[2] ),
.FF_RX_D_1_12 ( ),
.FF_RX_D_1_13 ( ),
.FF_RX_D_1_14 ( ),
.FF_RX_D_1_15 ( ),
.FF_RX_D_1_16 ( ),
.FF_RX_D_1_17 ( ),
.FF_RX_D_1_18 ( ),
.FF_RX_D_1_19 ( ),
.FF_RX_D_1_20 ( ),
.FF_RX_D_1_21 ( ),
.FF_RX_D_1_22 ( ),
.FF_RX_D_1_23 ( ),
.FFC_RRST_1 ( pcs_ffc_rrst_ch1 ),
.FFC_SIGNAL_DETECT_1 ( pcs_ffc_signal_detect ),
.FFC_ENABLE_CGALIGN_1 ( pcs_ffc_enb_cgalign ),
.FFC_SB_PFIFO_LP_1 ( 1'b0 ),
.FFC_PFIFO_CLR_1 ( 1'b0 ),
.FFC_FB_LOOPBACK_1 ( pcs_ffc_fb_loopback_ch1 ),
.FFC_SB_INV_RX_1 ( pcs_RxPolarity_ch1 ),
.FFC_PCIE_CT_1 ( pcs_ffc_pcie_ct_ch1 ),
.FFC_PCI_DET_EN_1 ( pcs_ffc_pcie_det_en_ch1 ),
.FFS_PCIE_DONE_1 ( pcs_ffs_pcie_done_1 ),
.FFS_PCIE_CON_1 ( pcs_ffs_pcie_con_1 ),
.FFC_EI_EN_1 ( 1'b0 ),
.FFC_LANE_TX_RST_1 ( pcs_ffc_lane_tx_rst ),
.FFC_LANE_RX_RST_1 ( pcs_ffc_lane_rx_rst[1] ),
.FFC_TXPWDNB_1 ( pcs_ffc_txpwdnb_1 ),
.FFC_RXPWDNB_1 ( pcs_ffc_rxpwdnb_1 ),
.FFS_RLOS_LO_1 ( pcs_RxElecIdle_ch1 ),
.FFS_LS_SYNC_STATUS_1 ( pcs_RxValid_ch1 ),
.FFS_CC_UNDERRUN_1 ( ),
.FFS_CC_OVERRUN_1 ( ),
.FFS_RXFBFIFO_ERROR_1 ( ),
.FFS_TXFBFIFO_ERROR_1 ( ),
.FFS_RLOL_1 ( pcs_ffs_rlol_ch1 ),
//CH2
.HDINP2 ( pcs_hdinp2 ),
.HDINN2 ( pcs_hdinn2 ),
.HDOUTP2 ( pcs_hdoutp2 ),
.HDOUTN2 ( pcs_hdoutn2 ),
`ifdef ECP3
.PCIE_TXDETRX_PR2TLB_2 ( 1'b0 ),
.PCIE_TXCOMPLIANCE_2 ( 1'b0 ),
.PCIE_RXPOLARITY_2 ( 1'b0 ),
.PCIE_POWERDOWN_2_0 ( 1'b0 ),
.PCIE_POWERDOWN_2_1 ( 1'b0 ),
.PCIE_RXVALID_2 ( ),
.PCIE_PHYSTATUS_2 ( ),
.FF_TX_F_CLK_2 ( pcs_ff_tx_f_clk_2 ),
.FF_TX_H_CLK_2 ( pcs_ff_tx_h_clk_2 ),
.FFC_CK_CORE_RX_2 ( 1'b0 ),
.FFS_RLOS_HI_2 ( ),
.FFS_SKP_ADDED_2 ( ),
.FFS_SKP_DELETED_2 ( ),
.LDR_CORE2TX_2 ( 1'b0 ),
.FFC_LDR_CORE2TX_EN_2 ( 1'b0 ),
.LDR_RX2CORE_2 ( ),
.FFS_CDR_TRAIN_DONE_2 ( ),
.FFC_DIV11_MODE_TX_2 ( 1'b0 ),
.FFC_RATE_MODE_TX_2 ( 1'b0 ),
.FFC_DIV11_MODE_RX_2 ( 1'b0 ),
.FFC_RATE_MODE_RX_2 ( 1'b0 ),
`else
.FF_RX_Q_CLK_2 ( ),
.OOB_OUT_2 ( ),
`endif
.SCISELCH2 ( pcs_scisel_ch2 ),
.SCIENCH2 ( pcs_scien_ch2 ),
.FF_TXI_CLK_2 ( pcs_PCLK ),
`ifdef X4
.FF_RXI_CLK_2 ( pcs_ff_rx_fclk_ch2 ),
.FF_EBRD_CLK_2 ( 1'b0 ),
`else
.FF_RXI_CLK_2 ( pcs_PCLK ),
.FF_EBRD_CLK_2 ( pcs_PCLK ),
`endif
.FF_RX_F_CLK_2 ( pcs_ff_rx_fclk_ch2 ),
.FF_RX_H_CLK_2 ( ),
.FF_TX_D_2_0 ( pcs_TxData_ch2[0] ),
.FF_TX_D_2_1 ( pcs_TxData_ch2[1] ),
.FF_TX_D_2_2 ( pcs_TxData_ch2[2] ),
.FF_TX_D_2_3 ( pcs_TxData_ch2[3] ),
.FF_TX_D_2_4 ( pcs_TxData_ch2[4] ),
.FF_TX_D_2_5 ( pcs_TxData_ch2[5] ),
.FF_TX_D_2_6 ( pcs_TxData_ch2[6] ),
.FF_TX_D_2_7 ( pcs_TxData_ch2[7] ),
.FF_TX_D_2_8 ( pcs_TxDataK_ch2 ),
.FF_TX_D_2_9 ( pcs_TxCompliance_ch2 ),
.FF_TX_D_2_10 ( 1'b0 ),
.FF_TX_D_2_11 ( pcs_TxElecIdle_ch2 ),
.FF_TX_D_2_12 ( 1'b0 ),
.FF_TX_D_2_13 ( 1'b0 ),
.FF_TX_D_2_14 ( 1'b0 ),
.FF_TX_D_2_15 ( 1'b0 ),
.FF_TX_D_2_16 ( 1'b0 ),
.FF_TX_D_2_17 ( 1'b0 ),
.FF_TX_D_2_18 ( 1'b0 ),
.FF_TX_D_2_19 ( 1'b0 ),
.FF_TX_D_2_20 ( 1'b0 ),
.FF_TX_D_2_21 ( 1'b0 ),
.FF_TX_D_2_22 ( 1'b0 ),
.FF_TX_D_2_23 ( 1'b0 ),
.FF_RX_D_2_0 ( pcs_RxData_ch2[0] ),
.FF_RX_D_2_1 ( pcs_RxData_ch2[1] ),
.FF_RX_D_2_2 ( pcs_RxData_ch2[2] ),
.FF_RX_D_2_3 ( pcs_RxData_ch2[3] ),
.FF_RX_D_2_4 ( pcs_RxData_ch2[4] ),
.FF_RX_D_2_5 ( pcs_RxData_ch2[5] ),
.FF_RX_D_2_6 ( pcs_RxData_ch2[6] ),
.FF_RX_D_2_7 ( pcs_RxData_ch2[7] ),
.FF_RX_D_2_8 ( pcs_RxDataK_ch2 ),
.FF_RX_D_2_9 ( pcs_RxStatus_ch2[0] ),
.FF_RX_D_2_10 ( pcs_RxStatus_ch2[1] ),
.FF_RX_D_2_11 ( pcs_RxStatus_ch2[2] ),
.FF_RX_D_2_12 ( ),
.FF_RX_D_2_13 ( ),
.FF_RX_D_2_14 ( ),
.FF_RX_D_2_15 ( ),
.FF_RX_D_2_16 ( ),
.FF_RX_D_2_17 ( ),
.FF_RX_D_2_18 ( ),
.FF_RX_D_2_19 ( ),
.FF_RX_D_2_20 ( ),
.FF_RX_D_2_21 ( ),
.FF_RX_D_2_22 ( ),
.FF_RX_D_2_23 ( ),
.FFC_RRST_2 ( pcs_ffc_rrst_ch2 ),
.FFC_SIGNAL_DETECT_2 ( pcs_ffc_signal_detect ),
.FFC_ENABLE_CGALIGN_2 ( pcs_ffc_enb_cgalign ),
.FFC_SB_PFIFO_LP_2 ( 1'b0 ),
.FFC_PFIFO_CLR_2 ( 1'b0 ),
.FFC_FB_LOOPBACK_2 ( pcs_ffc_fb_loopback_ch2 ),
.FFC_SB_INV_RX_2 ( pcs_RxPolarity_ch2 ),
.FFC_PCIE_CT_2 ( pcs_ffc_pcie_ct_ch2 ),
.FFC_PCI_DET_EN_2 ( pcs_ffc_pcie_det_en_ch2 ),
.FFS_PCIE_DONE_2 ( pcs_ffs_pcie_done_2 ),
.FFS_PCIE_CON_2 ( pcs_ffs_pcie_con_2 ),
.FFC_EI_EN_2 ( 1'b0 ),
.FFC_LANE_TX_RST_2 ( pcs_ffc_lane_tx_rst ),
.FFC_LANE_RX_RST_2 ( pcs_ffc_lane_rx_rst[2] ),
.FFC_TXPWDNB_2 ( pcs_ffc_txpwdnb_2 ),
.FFC_RXPWDNB_2 ( pcs_ffc_rxpwdnb_2 ),
.FFS_RLOS_LO_2 ( pcs_RxElecIdle_ch2 ),
.FFS_LS_SYNC_STATUS_2 ( pcs_RxValid_ch2 ),
.FFS_CC_UNDERRUN_2 ( ),
.FFS_CC_OVERRUN_2 ( ),
.FFS_RXFBFIFO_ERROR_2 ( ),
.FFS_TXFBFIFO_ERROR_2 ( ),
.FFS_RLOL_2 ( pcs_ffs_rlol_ch2 ),
//CH3
.HDINP3 ( pcs_hdinp3 ),
.HDINN3 ( pcs_hdinn3 ),
.HDOUTP3 ( pcs_hdoutp3 ),
.HDOUTN3 ( pcs_hdoutn3 ),
`ifdef ECP3
.PCIE_TXDETRX_PR2TLB_3 ( 1'b0 ),
.PCIE_TXCOMPLIANCE_3 ( 1'b0 ),
.PCIE_RXPOLARITY_3 ( 1'b0 ),
.PCIE_POWERDOWN_3_0 ( 1'b0 ),
.PCIE_POWERDOWN_3_1 ( 1'b0 ),
.PCIE_RXVALID_3 ( ),
.PCIE_PHYSTATUS_3 ( ),
.FF_TX_F_CLK_3 ( pcs_ff_tx_f_clk_3 ),
.FF_TX_H_CLK_3 ( pcs_ff_tx_h_clk_3 ),
.FFC_CK_CORE_RX_3 ( 1'b0 ),
.FFS_RLOS_HI_3 ( ),
.FFS_SKP_ADDED_3 ( ),
.FFS_SKP_DELETED_3 ( ),
.LDR_CORE2TX_3 ( 1'b0 ),
.FFC_LDR_CORE2TX_EN_3 ( 1'b0 ),
.LDR_RX2CORE_3 ( ),
.FFS_CDR_TRAIN_DONE_3 ( ),
.FFC_DIV11_MODE_TX_3 ( 1'b0 ),
.FFC_RATE_MODE_TX_3 ( 1'b0 ),
.FFC_DIV11_MODE_RX_3 ( 1'b0 ),
.FFC_RATE_MODE_RX_3 ( 1'b0 ),
`else
.FF_RX_Q_CLK_3 ( ),
.OOB_OUT_3 ( ),
`endif
.SCISELCH3 ( pcs_scisel_ch3 ),
.SCIENCH3 ( pcs_scien_ch3 ),
.FF_TXI_CLK_3 ( pcs_PCLK ),
`ifdef X4
.FF_RXI_CLK_3 ( pcs_ff_rx_fclk_ch3 ),
.FF_EBRD_CLK_3 ( 1'b0 ),
`else
.FF_RXI_CLK_3 ( pcs_PCLK ),
.FF_EBRD_CLK_3 ( pcs_PCLK ),
`endif
.FF_RX_F_CLK_3 ( pcs_ff_rx_fclk_ch3 ),
.FF_RX_H_CLK_3 ( ),
.FF_TX_D_3_0 ( pcs_TxData_ch3[0] ),
.FF_TX_D_3_1 ( pcs_TxData_ch3[1] ),
.FF_TX_D_3_2 ( pcs_TxData_ch3[2] ),
.FF_TX_D_3_3 ( pcs_TxData_ch3[3] ),
.FF_TX_D_3_4 ( pcs_TxData_ch3[4] ),
.FF_TX_D_3_5 ( pcs_TxData_ch3[5] ),
.FF_TX_D_3_6 ( pcs_TxData_ch3[6] ),
.FF_TX_D_3_7 ( pcs_TxData_ch3[7] ),
.FF_TX_D_3_8 ( pcs_TxDataK_ch3 ),
.FF_TX_D_3_9 ( pcs_TxCompliance_ch3 ),
.FF_TX_D_3_10 ( 1'b0 ),
.FF_TX_D_3_11 ( pcs_TxElecIdle_ch3 ),
.FF_TX_D_3_12 ( 1'b0 ),
.FF_TX_D_3_13 ( 1'b0 ),
.FF_TX_D_3_14 ( 1'b0 ),
.FF_TX_D_3_15 ( 1'b0 ),
.FF_TX_D_3_16 ( 1'b0 ),
.FF_TX_D_3_17 ( 1'b0 ),
.FF_TX_D_3_18 ( 1'b0 ),
.FF_TX_D_3_19 ( 1'b0 ),
.FF_TX_D_3_20 ( 1'b0 ),
.FF_TX_D_3_21 ( 1'b0 ),
.FF_TX_D_3_22 ( 1'b0 ),
.FF_TX_D_3_23 ( 1'b0 ),
.FF_RX_D_3_0 ( pcs_RxData_ch3[0] ),
.FF_RX_D_3_1 ( pcs_RxData_ch3[1] ),
.FF_RX_D_3_2 ( pcs_RxData_ch3[2] ),
.FF_RX_D_3_3 ( pcs_RxData_ch3[3] ),
.FF_RX_D_3_4 ( pcs_RxData_ch3[4] ),
.FF_RX_D_3_5 ( pcs_RxData_ch3[5] ),
.FF_RX_D_3_6 ( pcs_RxData_ch3[6] ),
.FF_RX_D_3_7 ( pcs_RxData_ch3[7] ),
.FF_RX_D_3_8 ( pcs_RxDataK_ch3 ),
.FF_RX_D_3_9 ( pcs_RxStatus_ch3[0] ),
.FF_RX_D_3_10 ( pcs_RxStatus_ch3[1] ),
.FF_RX_D_3_11 ( pcs_RxStatus_ch3[2] ),
.FF_RX_D_3_12 ( ),
.FF_RX_D_3_13 ( ),
.FF_RX_D_3_14 ( ),
.FF_RX_D_3_15 ( ),
.FF_RX_D_3_16 ( ),
.FF_RX_D_3_17 ( ),
.FF_RX_D_3_18 ( ),
.FF_RX_D_3_19 ( ),
.FF_RX_D_3_20 ( ),
.FF_RX_D_3_21 ( ),
.FF_RX_D_3_22 ( ),
.FF_RX_D_3_23 ( ),
.FFC_RRST_3 ( pcs_ffc_rrst_ch3 ),
.FFC_SIGNAL_DETECT_3 ( pcs_ffc_signal_detect ),
.FFC_ENABLE_CGALIGN_3 ( pcs_ffc_enb_cgalign ),
.FFC_SB_PFIFO_LP_3 ( 1'b0 ),
.FFC_PFIFO_CLR_3 ( 1'b0 ),
.FFC_FB_LOOPBACK_3 ( pcs_ffc_fb_loopback_ch3 ),
.FFC_SB_INV_RX_3 ( pcs_RxPolarity_ch3 ),
.FFC_PCIE_CT_3 ( pcs_ffc_pcie_ct_ch3 ),
.FFC_PCI_DET_EN_3 ( pcs_ffc_pcie_det_en_ch3 ),
.FFS_PCIE_DONE_3 ( pcs_ffs_pcie_done_3 ),
.FFS_PCIE_CON_3 ( pcs_ffs_pcie_con_3 ),
.FFC_EI_EN_3 ( 1'b0 ),
.FFC_LANE_TX_RST_3 ( pcs_ffc_lane_tx_rst ),
.FFC_LANE_RX_RST_3 ( pcs_ffc_lane_rx_rst[3] ),
.FFC_TXPWDNB_3 ( pcs_ffc_txpwdnb_3 ),
.FFC_RXPWDNB_3 ( pcs_ffc_rxpwdnb_3 ),
.FFS_RLOS_LO_3 ( pcs_RxElecIdle_ch3 ),
.FFS_LS_SYNC_STATUS_3 ( pcs_RxValid_ch3 ),
.FFS_CC_UNDERRUN_3 ( ),
.FFS_CC_OVERRUN_3 ( ),
.FFS_RXFBFIFO_ERROR_3 ( ),
.FFS_TXFBFIFO_ERROR_3 ( ),
.FFS_RLOL_3 ( pcs_ffs_rlol_ch3 ),
// SCI PINS
.SCIWDATA0 ( pcs_sciwritedata[0] ),
.SCIWDATA1 ( pcs_sciwritedata[1] ),
.SCIWDATA2 ( pcs_sciwritedata[2] ),
.SCIWDATA3 ( pcs_sciwritedata[3] ),
.SCIWDATA4 ( pcs_sciwritedata[4] ),
.SCIWDATA5 ( pcs_sciwritedata[5] ),
.SCIWDATA6 ( pcs_sciwritedata[6] ),
.SCIWDATA7 ( pcs_sciwritedata[7] ),
.SCIADDR0 ( pcs_sciaddress[0] ),
.SCIADDR1 ( pcs_sciaddress[1] ),
.SCIADDR2 ( pcs_sciaddress[2] ),
.SCIADDR3 ( pcs_sciaddress[3] ),
.SCIADDR4 ( pcs_sciaddress[4] ),
.SCIADDR5 ( pcs_sciaddress[5] ),
.SCIRDATA0 ( pcs_scireaddata[0] ),
.SCIRDATA1 ( pcs_scireaddata[1] ),
.SCIRDATA2 ( pcs_scireaddata[2] ),
.SCIRDATA3 ( pcs_scireaddata[3] ),
.SCIRDATA4 ( pcs_scireaddata[4] ),
.SCIRDATA5 ( pcs_scireaddata[5] ),
.SCIRDATA6 ( pcs_scireaddata[6] ),
.SCIRDATA7 ( pcs_scireaddata[7] ),
.SCIENAUX ( pcs_scienaux ),
.SCISELAUX ( pcs_sciselaux ),
.SCIRD ( pcs_scird ),
.SCIWSTN ( pcs_sciwstn ),
.CYAWSTN ( 1'b0 ),
.SCIINT ( ),
`ifdef ECP3
.FFC_SYNC_TOGGLE ( 1'b0 ),
.REFCLK_FROM_NQ ( 1'b0 ),
.REFCLK_TO_NQ ( ),
`else
.FFC_CK_CORE_RX ( 1'b0 ),
.FF_TX_F_CLK ( pcs_ff_tx_f_clk ),
.FF_TX_H_CLK ( pcs_ff_tx_h_clk ),
.FF_TX_Q_CLK ( ),
`endif
.FFC_MACRO_RST ( pcs_ffc_macro_rst ),
.FFC_QUAD_RST ( pcs_ffc_quad_rst ),
.FFC_TRST ( pcs_ffc_trst ),
.REFCK2CORE ( refclk ),
.CIN0 ( pcs_cin[0] ),
.CIN1 ( pcs_cin[1] ),
.CIN2 ( pcs_cin[2] ),
.CIN3 ( pcs_cin[3] ),
.CIN4 ( pcs_cin[4] ),
.CIN5 ( pcs_cin[5] ),
.CIN6 ( pcs_cin[6] ),
.CIN7 ( pcs_cin[7] ),
.CIN8 ( pcs_cin[8] ),
.CIN9 ( pcs_cin[9] ),
.CIN10 ( pcs_cin[10] ),
.CIN11 ( pcs_cin[11] ),
.COUT0 ( pcs_cout[0] ),
.COUT1 ( pcs_cout[1] ),
.COUT2 ( pcs_cout[2] ),
.COUT3 ( pcs_cout[3] ),
.COUT4 ( pcs_cout[4] ),
.COUT5 ( pcs_cout[5] ),
.COUT6 ( pcs_cout[6] ),
.COUT7 ( pcs_cout[7] ),
.COUT8 ( pcs_cout[8] ),
.COUT9 ( pcs_cout[9] ),
.COUT10 ( pcs_cout[10] ),
.COUT11 ( pcs_cout[11] ),
.COUT12 ( pcs_cout[12] ),
.COUT13 ( pcs_cout[13] ),
.COUT14 ( pcs_cout[14] ),
.COUT15 ( pcs_cout[15] ),
.COUT16 ( pcs_cout[16] ),
.COUT17 ( pcs_cout[17] ),
.COUT18 ( pcs_cout[18] ),
.COUT19 ( pcs_cout[19] ),
.FFS_PLOL ( pcs_ffs_plol )
`ifdef ECP3
`ifdef X1
) /* synthesis IS_ASB="ep5c00/data/ep5c00.acd" CONFIG_FILE="pcs_pipe_8b_x1.txt" */;
`else
) /* synthesis IS_ASB="ep5c00/data/ep5c00.acd" CONFIG_FILE="pcs_pipe_8b_x4.txt" */;
`endif
`else
`ifdef X1
) /* synthesis IS_ASB="ep5m00/data/ep5m00.acd" CONFIG_FILE="pcs_pipe_8b_x1.txt" */;
`else
) /* synthesis IS_ASB="ep5m00/data/ep5m00.acd" CONFIG_FILE="pcs_pipe_8b_x4.txt" */;
`endif
`endif
// =============================================================================
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Sep 19 16:48:52 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[3:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [3:0]probe5;
endmodule
|
(** * MoreLogic: More on Logic in Coq *)
Require Export "Prop".
(* ############################################################ *)
(** * Existential Quantification *)
(** Another critical logical connective is _existential
quantification_. We can express it with the following
definition: *)
Inductive ex (X:Type) (P : X->Prop) : Prop :=
ex_intro : forall (witness:X), P witness -> ex X P.
(** That is, [ex] is a family of propositions indexed by a type [X]
and a property [P] over [X]. In order to give evidence for the
assertion "there exists an [x] for which the property [P] holds"
we must actually name a _witness_ -- a specific value [x] -- and
then give evidence for [P x], i.e., evidence that [x] has the
property [P].
*)
(** *** *)
(** Coq's [Notation] facility can be used to introduce more
familiar notation for writing existentially quantified
propositions, exactly parallel to the built-in syntax for
universally quantified propositions. Instead of writing [ex nat
ev] to express the proposition that there exists some number that
is even, for example, we can write [exists x:nat, ev x]. (It is
not necessary to understand exactly how the [Notation] definition
works.) *)
Notation "'exists' x , p" := (ex _ (fun x => p))
(at level 200, x ident, right associativity) : type_scope.
Notation "'exists' x : X , p" := (ex _ (fun x:X => p))
(at level 200, x ident, right associativity) : type_scope.
(** *** *)
(** We can use the usual set of tactics for
manipulating existentials. For example, to prove an
existential, we can [apply] the constructor [ex_intro]. Since the
premise of [ex_intro] involves a variable ([witness]) that does
not appear in its conclusion, we need to explicitly give its value
when we use [apply]. *)
Example exists_example_1 : exists n, n + (n * n) = 6.
Proof.
apply ex_intro with (witness:=2).
reflexivity. Qed.
(** Note that we have to explicitly give the witness. *)
(** *** *)
(** Or, instead of writing [apply ex_intro with (witness:=e)] all the
time, we can use the convenient shorthand [exists e], which means
the same thing. *)
Example exists_example_1' : exists n, n + (n * n) = 6.
Proof.
exists 2.
reflexivity. Qed.
(** *** *)
(** Conversely, if we have an existential hypothesis in the
context, we can eliminate it with [inversion]. Note the use
of the [as...] pattern to name the variable that Coq
introduces to name the witness value and get evidence that
the hypothesis holds for the witness. (If we don't
explicitly choose one, Coq will just call it [witness], which
makes proofs confusing.) *)
Theorem exists_example_2 : forall n,
(exists m, n = 4 + m) ->
(exists o, n = 2 + o).
Proof.
intros n H.
inversion H as [m Hm].
exists (2 + m).
apply Hm. Qed.
(** Here is another example of how to work with existentials. *)
Lemma exists_example_3 :
exists (n:nat), even n /\ beautiful n.
Proof.
(* WORKED IN CLASS *)
exists 8.
split.
unfold even. simpl. reflexivity.
apply b_sum with (n:=3) (m:=5).
apply b_3. apply b_5.
Qed.
(** **** Exercise: 1 star, optional (english_exists) *)
(** In English, what does the proposition
ex nat (fun n => beautiful (S n))
]]
mean? *)
(* FILL IN HERE *)
(*
*)
(** **** Exercise: 1 star (dist_not_exists) *)
(** Prove that "[P] holds for all [x]" implies "there is no [x] for
which [P] does not hold." *)
Theorem dist_not_exists : forall (X:Type) (P : X -> Prop),
(forall x, P x) -> ~ (exists x, ~ P x).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (not_exists_dist) *)
(** (The other direction of this theorem requires the classical "law
of the excluded middle".) *)
Theorem not_exists_dist :
excluded_middle ->
forall (X:Type) (P : X -> Prop),
~ (exists x, ~ P x) -> (forall x, P x).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (dist_exists_or) *)
(** Prove that existential quantification distributes over
disjunction. *)
Theorem dist_exists_or : forall (X:Type) (P Q : X -> Prop),
(exists x, P x \/ Q x) <-> (exists x, P x) \/ (exists x, Q x).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Evidence-Carrying Booleans *)
(** So far we've seen two different forms of equality predicates:
[eq], which produces a [Prop], and the type-specific forms, like
[beq_nat], that produce [boolean] values. The former are more
convenient to reason about, but we've relied on the latter to let
us use equality tests in _computations_. While it is
straightforward to write lemmas (e.g. [beq_nat_true] and
[beq_nat_false]) that connect the two forms, using these lemmas
quickly gets tedious. *)
(** *** *)
(** It turns out that we can get the benefits of both forms at once by
using a construct called [sumbool]. *)
Inductive sumbool (A B : Prop) : Set :=
| left : A -> sumbool A B
| right : B -> sumbool A B.
Notation "{ A } + { B }" := (sumbool A B) : type_scope.
(** Think of [sumbool] as being like the [boolean] type, but instead
of its values being just [true] and [false], they carry _evidence_
of truth or falsity. This means that when we [destruct] them, we
are left with the relevant evidence as a hypothesis -- just as
with [or]. (In fact, the definition of [sumbool] is almost the
same as for [or]. The only difference is that values of [sumbool]
are declared to be in [Set] rather than in [Prop]; this is a
technical distinction that allows us to compute with them.) *)
(** *** *)
(** Here's how we can define a [sumbool] for equality on [nat]s *)
Theorem eq_nat_dec : forall n m : nat, {n = m} + {n <> m}.
Proof.
(* WORKED IN CLASS *)
intros n.
induction n as [|n'].
- (* n = 0 *)
intros m.
destruct m as [|m'].
+ (* m = 0 *)
left. reflexivity.
+ (* m = S m' *)
right. intros contra. inversion contra.
- (* n = S n' *)
intros m.
destruct m as [|m'].
+ (* m = 0 *)
right. intros contra. inversion contra.
+ (* m = S m' *)
destruct IHn' with (m := m') as [eq | neq].
left. apply f_equal. apply eq.
right. intros Heq. inversion Heq as [Heq']. apply neq. apply Heq'.
Defined.
(** Read as a theorem, this says that equality on [nat]s is decidable:
that is, given two [nat] values, we can always produce either
evidence that they are equal or evidence that they are not. Read
computationally, [eq_nat_dec] takes two [nat] values and returns a
[sumbool] constructed with [left] if they are equal and [right] if
they are not; this result can be tested with a [match] or, better,
with an [if-then-else], just like a regular [boolean]. (Notice
that we ended this proof with [Defined] rather than [Qed]. The
only difference this makes is that the proof becomes
_transparent_, meaning that its definition is available when Coq
tries to do reductions, which is important for the computational
interpretation.) *)
(** *** *)
(** Here's a simple example illustrating the advantages of the
[sumbool] form. *)
Definition override' {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if eq_nat_dec k k' then x else f k'.
Theorem override_same' : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override' f k1 x1) k2 = f k2.
Proof.
intros X x1 k1 k2 f. intros Hx1.
unfold override'.
destruct (eq_nat_dec k1 k2). (* observe what appears as a hypothesis *)
- (* k1 = k2 *)
rewrite <- e.
symmetry. apply Hx1.
- (* k1 <> k2 *)
reflexivity. Qed.
(** Compare this to the more laborious proof (in BasicTactics.v) for the
version of [override] defined using [beq_nat], where we had to use
the auxiliary lemma [beq_nat_true] to convert a fact about
booleans to a Prop. *)
(** **** Exercise: 1 star (override_shadow') *)
Theorem override_shadow' : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override' (override' f k1 x2) k1 x1) k2 = (override' f k1 x1) k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (all_forallb) *)
(** Inductively define a property [all] of lists, parameterized by a
type [X] and a property [P : X -> Prop], such that [all X P l]
asserts that [P] is true for every element of the list [l]. *)
Inductive all (X : Type) (P : X -> Prop) : list X -> Prop :=
(* FILL IN HERE *)
.
(** Recall the function [forallb], from the exercise
[forall_exists_challenge] in chapter [Poly]: *)
Fixpoint forallb {X : Type} (test : X -> bool) (l : list X) : bool :=
match l with
| [] => true
| x :: l' => andb (test x) (forallb test l')
end.
(** Using the property [all], write down a specification for [forallb],
and prove that it satisfies the specification. Try to make your
specification as precise as possible.
Are there any important properties of the function [forallb] which
are not captured by your specification? *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, advanced (filter_challenge) *)
(** One of the main purposes of Coq is to prove that programs match
their specifications. To this end, let's prove that our
definition of [filter] matches a specification. Here is the
specification, written out informally in English.
Suppose we have a set [X], a function [test: X->bool], and a list
[l] of type [list X]. Suppose further that [l] is an "in-order
merge" of two lists, [l1] and [l2], such that every item in [l1]
satisfies [test] and no item in [l2] satisfies test. Then [filter
test l = l1].
A list [l] is an "in-order merge" of [l1] and [l2] if it contains
all the same elements as [l1] and [l2], in the same order as [l1]
and [l2], but possibly interleaved. For example,
[1,4,6,2,3]
is an in-order merge of
[1,6,2]
and
[4,3].
Your job is to translate this specification into a Coq theorem and
prove it. (Hint: You'll need to begin by defining what it means
for one list to be a merge of two others. Do this with an
inductive relation, not a [Fixpoint].) *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 5 stars, advanced, optional (filter_challenge_2) *)
(** A different way to formally characterize the behavior of [filter]
goes like this: Among all subsequences of [l] with the property
that [test] evaluates to [true] on all their members, [filter test
l] is the longest. Express this claim formally and prove it. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, advanced (no_repeats) *)
(** The following inductively defined proposition... *)
Inductive appears_in {X:Type} (a:X) : list X -> Prop :=
| ai_here : forall l, appears_in a (a::l)
| ai_later : forall b l, appears_in a l -> appears_in a (b::l).
(** ...gives us a precise way of saying that a value [a] appears at
least once as a member of a list [l].
Here's a pair of warm-ups about [appears_in].
*)
Lemma appears_in_app : forall (X:Type) (xs ys : list X) (x:X),
appears_in x (xs ++ ys) -> appears_in x xs \/ appears_in x ys.
Proof.
(* FILL IN HERE *) Admitted.
Lemma app_appears_in : forall (X:Type) (xs ys : list X) (x:X),
appears_in x xs \/ appears_in x ys -> appears_in x (xs ++ ys).
Proof.
(* FILL IN HERE *) Admitted.
(** Now use [appears_in] to define a proposition [disjoint X l1 l2],
which should be provable exactly when [l1] and [l2] are
lists (with elements of type X) that have no elements in common. *)
(* FILL IN HERE *)
(** Next, use [appears_in] to define an inductive proposition
[no_repeats X l], which should be provable exactly when [l] is a
list (with elements of type [X]) where every member is different
from every other. For example, [no_repeats nat [1,2,3,4]] and
[no_repeats bool []] should be provable, while [no_repeats nat
[1,2,1]] and [no_repeats bool [true,true]] should not be. *)
(* FILL IN HERE *)
(** Finally, state and prove one or more interesting theorems relating
[disjoint], [no_repeats] and [++] (list append). *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (nostutter) *)
(** Formulating inductive definitions of predicates is an important
skill you'll need in this course. Try to solve this exercise
without any help at all.
We say that a list of numbers "stutters" if it repeats the same
number consecutively. The predicate "[nostutter mylist]" means
that [mylist] does not stutter. Formulate an inductive definition
for [nostutter]. (This is different from the [no_repeats]
predicate in the exercise above; the sequence [1;4;1] repeats but
does not stutter.) *)
Inductive nostutter: list nat -> Prop :=
(* FILL IN HERE *)
.
(** Make sure each of these tests succeeds, but you are free
to change the proof if the given one doesn't work for you.
Your definition might be different from mine and still correct,
in which case the examples might need a different proof.
The suggested proofs for the examples (in comments) use a number
of tactics we haven't talked about, to try to make them robust
with respect to different possible ways of defining [nostutter].
You should be able to just uncomment and use them as-is, but if
you prefer you can also prove each example with more basic
tactics. *)
Example test_nostutter_1: nostutter [3;1;4;1;5;6].
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_2: nostutter [].
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_3: nostutter [5].
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_4: not (nostutter [3;1;1;4]).
(* FILL IN HERE *) Admitted.
(*
Proof. intro.
repeat match goal with
h: nostutter _ |- _ => inversion h; clear h; subst
end.
contradiction H1; auto. Qed.
*)
(** [] *)
(** **** Exercise: 4 stars, advanced (pigeonhole principle) *)
(** The "pigeonhole principle" states a basic fact about counting:
if you distribute more than [n] items into [n] pigeonholes, some
pigeonhole must contain at least two items. As is often the case,
this apparently trivial fact about numbers requires non-trivial
machinery to prove, but we now have enough... *)
(** First a pair of useful lemmas (we already proved these for lists
of naturals, but not for arbitrary lists). *)
Lemma app_length : forall (X:Type) (l1 l2 : list X),
length (l1 ++ l2) = length l1 + length l2.
Proof.
(* FILL IN HERE *) Admitted.
Lemma appears_in_app_split : forall (X:Type) (x:X) (l:list X),
appears_in x l ->
exists l1, exists l2, l = l1 ++ (x::l2).
Proof.
(* FILL IN HERE *) Admitted.
(** Now define a predicate [repeats] (analogous to [no_repeats] in the
exercise above), such that [repeats X l] asserts that [l] contains
at least one repeated element (of type [X]). *)
Inductive repeats {X:Type} : list X -> Prop :=
(* FILL IN HERE *)
.
(** Now here's a way to formalize the pigeonhole principle. List [l2]
represents a list of pigeonhole labels, and list [l1] represents
the labels assigned to a list of items: if there are more items
than labels, at least two items must have the same label. This
proof is much easier if you use the [excluded_middle] hypothesis
to show that [appears_in] is decidable, i.e. [forall x
l, (appears_in x l) \/ ~ (appears_in x l)]. However, it is also
possible to make the proof go through _without_ assuming that
[appears_in] is decidable; if you can manage to do this, you will
not need the [excluded_middle] hypothesis. *)
Theorem pigeonhole_principle: forall (X:Type) (l1 l2:list X),
excluded_middle ->
(forall x, appears_in x l1 -> appears_in x l2) ->
length l2 < length l1 ->
repeats l1.
Proof.
intros X l1. induction l1 as [|x l1'].
(* FILL IN HERE *) Admitted.
(** [] *)
(* FILL IN HERE *)
(** $Date$ *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S50KAPWR_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLYBUF4S50KAPWR_FUNCTIONAL_V
/**
* dlybuf4s50kapwr: Delay Buffer 4-stage 0.50um length inner stage
* gates on keep-alive power rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__dlybuf4s50kapwr (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S50KAPWR_FUNCTIONAL_V |
`timescale 1ns / 1ps
/*
-- Module Name: Selector
-- Description: Seleccion de peticion activa para este ciclo de reloj.
El uso de algoritmos adaptativos o semi adaptativos
produce una o mas salidas validas para un paquete. Sin
embargo la solicitud de dos o mas puertos de salida a la
vez puede ocacionar dupliacion o liberacion de paquetes
corruptos a la red.
Este modulo recibe una o mas solicitudes para los
"planificadores de salida", pero solo permite la salida
de una peticion a la vez.
La seleccion de peticion activa depende de un esquema de
prioridad y de la disponibilidad de puertos.
-- Dependencies: -- system.vh
-- Parameters: -- PORT_DIR: Direccion del puerto de entrada
conectado a este modulo {x+, y+
x-, y-}.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
(05/06/2015) El esquema de prioridad utilizado es fijo, y otorga
preferencia de salida en el siguiente orden {pe, x+, y+, x-, y-}
-- History:
-- Creacion 05 de Junio 2015
*/
module des_control
(
input wire clk,
input wire reset,
// -- input ---------------------------------------------------------- >>>>>
input wire start_strobe_din,
// -- output --------------------------------------------------------- >>>>>
output wire enable_dout,
output wire source_dout,
output wire active_dout,
output reg round_shift_dout,
output wire done_strobe_dout
);
// -- Parametros Locales ------------------------------------------------- >>>>>
localparam IDLE = 1'b0;
localparam ACTIVE = 1'b1;
// -- Declaracion temprana de Señales ------------------------------------ >>>>>
reg [3:0] round_counter;
// -- FSM::DES ----------------------------------------------------------- >>>>>
reg state_reg;
reg state_next;
// -- Elementos de memoria FSM --------------------------------------- >>>>>
always @(posedge clk)
if(reset)
state_reg <= IDLE;
else
state_reg <= state_next;
// -- Logica de estado siguiente ------------------------------------- >>>>>
always @(*)
begin
state_next = state_reg;
case (state_reg)
IDLE: if (start_strobe_din)
state_next = ACTIVE;
ACTIVE: if (round_counter == 4'b1111)
state_next = IDLE;
endcase // state_reg
end
// -- Contador de rondas --------------------------------------------- >>>>>
always @(posedge clk)
if (state_reg)
round_counter <= round_counter + 1'b1;
else
round_counter <= {4{1'b0}};
// -- Logica de salidas de control ----------------------------------- >>>>>
// -- enable ----------------------------------------------------- >>>>>
assign enable_dout = (state_next | state_reg) ? 1'b1 : 1'b0;
// -- round shift ------------------------------------------------ >>>>>
always @(*)
case (round_counter)
4'd0 : round_shift_dout = 1'b0;
4'd1 : round_shift_dout = 1'b0;
4'd8 : round_shift_dout = 1'b0;
4'd15: round_shift_dout = 1'b0;
default : round_shift_dout = 1'b1;
endcase // round_counter
// -- source select ---------------------------------------------- >>>>>
assign source_dout = (state_reg) ? 1'b1 : 1'b0;
// -- done strobe ------------------------------------------------ >>>>>
assign done_strobe_dout = (&round_counter) ? 1'b1 : 1'b0;
// -- active ----------------------------------------------------- >>>>>
assign active_dout = (state_reg) ? 1'b1 : 1'b0;
// -- Simbolos de Depuracion ----------------------------------------- >>>>>
wire [6*8:0] estado_presente;
wire [6*8:0] estado_siguiente;
assign estado_presente = (state_reg) ? "ACTIVE" : "IDLE";
assign estado_siguiente = (state_next) ? "ACTIVE" : "IDLE";
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD2_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DLYGATE4SD2_PP_SYMBOL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlygate4sd2 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD2_PP_SYMBOL_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Verilog code that really should be replaced with a generate
* statement, but it does not work with some free simulators.
* So I put it in a module so as not to make other code unreadable,
* and keep compatibility with as many simulators as possible.
*/
module hpdmc_oddr16 #(
parameter DDR_ALIGNMENT = "C0",
parameter INIT = 1'b0,
parameter SRTYPE = "ASYNC"
) (
output [15:0] Q,
input C0,
input C1,
input CE,
input [15:0] D0,
input [15:0] D1,
input R,
input S
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr0 (
.Q(Q[0]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[0]),
.D1(D1[0]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr1 (
.Q(Q[1]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[1]),
.D1(D1[1]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr2 (
.Q(Q[2]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[2]),
.D1(D1[2]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr3 (
.Q(Q[3]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[3]),
.D1(D1[3]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr4 (
.Q(Q[4]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[4]),
.D1(D1[4]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr5 (
.Q(Q[5]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[5]),
.D1(D1[5]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr6 (
.Q(Q[6]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[6]),
.D1(D1[6]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr7 (
.Q(Q[7]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[7]),
.D1(D1[7]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr8 (
.Q(Q[8]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[8]),
.D1(D1[8]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr9 (
.Q(Q[9]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[9]),
.D1(D1[9]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr10 (
.Q(Q[10]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[10]),
.D1(D1[10]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr11 (
.Q(Q[11]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[11]),
.D1(D1[11]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr12 (
.Q(Q[12]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[12]),
.D1(D1[12]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr13 (
.Q(Q[13]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[13]),
.D1(D1[13]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr14 (
.Q(Q[14]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[14]),
.D1(D1[14]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr15 (
.Q(Q[15]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[15]),
.D1(D1[15]),
.R(R),
.S(S)
);
endmodule
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module aes_256 (state, key, out);
input [127:0] state;
input [255:0] key;
output [127:0] out;
reg [127:0] s0;
reg [255:0] k0, k0a, k1;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8,
s9, s10, s11, s12, s13;
wire [255:0] k2, k3, k4, k5, k6, k7, k8,
k9, k10, k11, k12, k13;
wire [127:0] k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b,
k9b, k10b, k11b, k12b, k13b;
always @ (*)
begin
s0 <= state ^ key[255:128];
k0 <= key;
k0a <= k0;
k1 <= k0a;
end
assign k0b = k0a[127:0];
expand_key_type_A_256
a1 (k1, 8'h1, k2, k1b),
a3 (k3, 8'h2, k4, k3b),
a5 (k5, 8'h4, k6, k5b),
a7 (k7, 8'h8, k8, k7b),
a9 (k9, 8'h10, k10, k9b),
a11 (k11, 8'h20, k12, k11b),
a13 (k13, 8'h40, , k13b);
expand_key_type_B_256
a2 (k2, k3, k2b),
a4 (k4, k5, k4b),
a6 (k6, k7, k6b),
a8 (k8, k9, k8b),
a10 (k10, k11, k10b),
a12 (k12, k13, k12b);
one_round
r1 (s0, k0b, s1),
r2 (s1, k1b, s2),
r3 (s2, k2b, s3),
r4 (s3, k3b, s4),
r5 (s4, k4b, s5),
r6 (s5, k5b, s6),
r7 (s6, k6b, s7),
r8 (s7, k7b, s8),
r9 (s8, k8b, s9),
r10 (s9, k9b, s10),
r11 (s10, k10b, s11),
r12 (s11, k11b, s12),
r13 (s12, k12b, s13);
final_round
rf (s13, k13b, out);
endmodule
/* expand k0,k1,k2,k3 for every two clock cycles */
module expand_key_type_A_256 (in, rcon, out_1, out_2);
input [255:0] in;
input [7:0] rcon;
output reg [255:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5, k6, k7,
v0, v1, v2, v3;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a, k6a, k7a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8a;
assign {k0, k1, k2, k3, k4, k5, k6, k7} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
assign v2 = v1 ^ k2;
assign v3 = v2 ^ k3;
always @ (*)
{k0a, k1a, k2a, k3a, k4a, k5a, k6a, k7a} <= {v0, v1, v2, v3, k4, k5, k6, k7};
S4
S4_0 ({k7[23:0], k7[31:24]}, k8a);
assign k0b = k0a ^ k8a;
assign k1b = k1a ^ k8a;
assign k2b = k2a ^ k8a;
assign k3b = k3a ^ k8a;
assign {k4b, k5b, k6b, k7b} = {k4a, k5a, k6a, k7a};
always @ (*)
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b};
assign out_2 = {k0b, k1b, k2b, k3b};
endmodule
/* expand k4,k5,k6,k7 for every two clock cycles */
module expand_key_type_B_256 (in, out_1, out_2);
input [255:0] in;
output reg [255:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5, k6, k7,
v5, v6, v7;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a, k6a, k7a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8a;
assign {k0, k1, k2, k3, k4, k5, k6, k7} = in;
assign v5 = k4 ^ k5;
assign v6 = v5 ^ k6;
assign v7 = v6 ^ k7;
always @ (*)
{k0a, k1a, k2a, k3a, k4a, k5a, k6a, k7a} <= {k0, k1, k2, k3, k4, v5, v6, v7};
S4
S4_0 (k3, k8a);
assign {k0b, k1b, k2b, k3b} = {k0a, k1a, k2a, k3a};
assign k4b = k4a ^ k8a;
assign k5b = k5a ^ k8a;
assign k6b = k6a ^ k8a;
assign k7b = k7a ^ k8a;
always @ (*)
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b};
assign out_2 = {k4b, k5b, k6b, k7b};
endmodule
|
module hdmi_video_reconfig(
input clock,
input [7:0] data_in,
output r2v_f,
output HDMIVideoConfig hdmiVideoConfig
);
`ifdef std
`include "config/std/hdmi_config.v"
`elsif hq2x
`include "config/hq2x/hdmi_config.v"
`endif
`include "config/hdmi_config.v"
reg [7:0] data_in_reg = 0;
HDMIVideoConfig _hdmiVideoConfig_reg;
HDMIVideoConfig hdmiVideoConfig_reg;
reg _r2v_f_reg;
reg r2v_f_reg;
initial begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_1080P;
hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_1080P;
_r2v_f_reg <= 1'b1;
r2v_f_reg <= 1'b1;
end
assign hdmiVideoConfig = hdmiVideoConfig_reg;
assign r2v_f = r2v_f_reg;
always @(posedge clock) begin
data_in_reg <= data_in;
if (data_in_reg != data_in) begin
case (data_in[6:0])
// RECONF
7'h00: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_1080P;
_r2v_f_reg <= 1'b1;
end
7'h01: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_960P;
_r2v_f_reg <= 1'b1;
end
7'h02: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_480P;
_r2v_f_reg <= 0;
end
7'h03: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_VGA;
_r2v_f_reg <= 0;
end
7'h04: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_288P;
_r2v_f_reg <= 0;
end
7'h05: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_288P;
_r2v_f_reg <= 0;
end
7'h06: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_288P;
_r2v_f_reg <= 0;
end
7'h07: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_288P;
_r2v_f_reg <= 0;
end
7'h08: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_576P;
_r2v_f_reg <= 0;
end
7'h09: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_576P;
_r2v_f_reg <= 0;
end
7'h0A: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_576P;
_r2v_f_reg <= 0;
end
7'h0B: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_576P;
_r2v_f_reg <= 0;
end
7'h10: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_240P_1080P;
_r2v_f_reg <= 0;
end
7'h11: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_240P_960P;
_r2v_f_reg <= 0;
end
7'h12: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_240P_480P;
_r2v_f_reg <= 0;
end
7'h13: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_240P_VGA;
_r2v_f_reg <= 0;
end
7'h20: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_480I;
_r2v_f_reg <= 0;
end
7'h21: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_480I;
_r2v_f_reg <= 0;
end
7'h22: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_480I;
_r2v_f_reg <= 0;
end
7'h23: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_480I;
_r2v_f_reg <= 0;
end
7'h40: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_576I;
_r2v_f_reg <= 0;
end
7'h41: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_576I;
_r2v_f_reg <= 0;
end
7'h42: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_576I;
_r2v_f_reg <= 0;
end
7'h43: begin
_hdmiVideoConfig_reg <= HDMI_VIDEO_CONFIG_576I;
_r2v_f_reg <= 0;
end
endcase
end
hdmiVideoConfig_reg <= _hdmiVideoConfig_reg;
r2v_f_reg <= _r2v_f_reg;
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__HA_PP_SYMBOL_V
`define SKY130_FD_SC_HS__HA_PP_SYMBOL_V
/**
* ha: Half adder.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__ha (
//# {{data|Data Signals}}
input A ,
input B ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__HA_PP_SYMBOL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: l_cache_mon.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module l_cache_mon(/*AUTOARG*/
// Inputs
clk, rst_l, spc, index_f, wrreq_f, wrway_f, wrtag_f, wr_data,
wren_f, wrreq_bf, wrindex_bf, cpx_spc_data_cx,
cpx_spc_data_rdy_cx, spc_pcx_data_pa, spc_pcx_req_pq, w0, w1, w2,
w3
);
input clk, rst_l;
input [31:0] spc;
//ict signal
input [11:5] index_f;
input wrreq_f;
input [1:0] wrway_f;
input [28:0] wrtag_f;
//icv
// input [1:0] wr_data;
input wr_data;
input [15:0] wren_f;
input wrreq_bf;
input [11:7] wrindex_bf;
// cpx packet
input [`CPX_WIDTH-1:0] cpx_spc_data_cx;
input cpx_spc_data_rdy_cx;
input [`PCX_WIDTH-1:0] spc_pcx_data_pa;
input [4:0] spc_pcx_req_pq;
input [127:0] w0;
input [127:0] w1;
input [127:0] w2;
input [127:0] w3;
// define dummy tag
reg [28:0] tag[512:0];
reg [512:0] vld;
reg [28:0] t_tag[3:0];
reg [3:0] vbit;
reg [7:0] vbit_32b;
wire [6:0] index = index_f[11:5];
wire [4:0] w_index = wrindex_bf[11:7];
integer i;
//array for pcx packet
reg [6:0] imiss_index[4:0];
reg [1:0] imiss_way[4:0];
reg [6:0] load_index[4:0];
reg [1:0] load_way[4:0];
reg [3:0] i_ptr, l_ptr, ia_ptr, la_ptr;
reg [127:0] wait_fill[3:0];
reg [127:0] one_way;
reg l1warm;
reg ictag_check_off;
initial begin
i_ptr = 0;
l_ptr = 0;
ia_ptr = 0;
la_ptr = 0;
l1warm = 1;
if($value$plusargs("l1warm=%h", l1warm))begin
l1warm = 0;
end
ictag_check_off = 0;
if($value$plusargs("ictag_check_off=%d", ictag_check_off))begin
$display("Info:ictag check off\n");
ictag_check_off = 1;
end
for(i = 0; i <= 512 ; i = i + 1) begin
vld[i] = 1'b0;
tag[i] = 29'b0;
end
end // initial begin
//make delay version
reg delay_bf;
reg [4:0] delay_ix;
always @(posedge clk)begin
delay_bf <= wrreq_bf;
delay_ix <= w_index;
end
// monitor tag
always @(negedge clk) begin
if(rst_l)begin
if(wrreq_f) begin
t_tag[0] = tag[{index, 2'b00}];
t_tag[1] = tag[{index, 2'b01}];
t_tag[2] = tag[{index, 2'b10}];
t_tag[3] = tag[{index, 2'b11}];
vbit[0] = vld[{index, 2'b00}];
vbit[1] = vld[{index, 2'b01}];
vbit[2] = vld[{index, 2'b10}];
vbit[3] = vld[{index, 2'b11}];
// check: new tag is identical to valid tag but written to different way
for(i=0; i < 4; i=i+1) begin
if((vbit[i] == 1'b1) && (wrtag_f == t_tag[i]) && (wrway_f != i)) begin
$display("I_CACHE : Same tag written to different way(%x) index(%x) Tag(%x)", i, index, wrtag_f);
if (ictag_check_off == 1'b0)
`MONITOR_PATH.fail("I_CACHE : Same tag written to different");
end
end
tag[{index, wrway_f}] = wrtag_f;
$display("Info (%d): Tag updated, index = %x, way = %x, tag = %x", $time, index, wrway_f, wrtag_f);
end // if (wrreq_f)
if(delay_bf)begin
if (wren_f[0])begin
vld[{delay_ix, 4'b0000}] = wr_data;
one_way = wait_fill[0];
one_way[{delay_ix, 4'b0000}] = wr_data;
//wait_fill[0] = one_way;
end
if (wren_f[1])begin
vld[{delay_ix, 4'b0001}] = wr_data;
one_way = wait_fill[1];
one_way[{delay_ix, 4'b0001}] = wr_data;
//wait_fill[1] = one_way;
end
if (wren_f[2])begin
vld[{delay_ix, 4'b0010}] = wr_data;
one_way = wait_fill[2];
one_way[{delay_ix, 4'b0010}] = wr_data;
//wait_fill[2] = one_way;
end
if (wren_f[3])begin
vld[{delay_ix, 4'b0011}] = wr_data;
one_way = wait_fill[3];
one_way[{delay_ix, 4'b0011}] = wr_data;
//wait_fill[3] = one_way;
end
if (wren_f[4])begin
vld[{delay_ix, 4'b0100}] = wr_data;
one_way = wait_fill[0];
one_way[{delay_ix, 4'b0100}] = wr_data;
//wait_fill[0] = one_way;
end
if (wren_f[5])begin
vld[{delay_ix, 4'b0101}] = wr_data;
one_way = wait_fill[1];
one_way[{delay_ix, 4'b0101}] = wr_data;
//wait_fill[1] = one_way;
end
if (wren_f[6])begin
vld[{delay_ix, 4'b0110}] = wr_data;
one_way = wait_fill[2];
one_way[{delay_ix, 4'b0110}] = wr_data;
//wait_fill[2] = one_way;
end
if (wren_f[7])begin
vld[{delay_ix, 4'b0111}] = wr_data;
one_way = wait_fill[3];
one_way[{delay_ix, 4'b0111}] = wr_data;
//wait_fill[3] = one_way;
end
if (wren_f[8])begin
vld[{delay_ix, 4'b1000}] = wr_data;
one_way = wait_fill[0];
one_way[{delay_ix, 4'b1000}] = wr_data;
//wait_fill[0] = one_way;
end
if (wren_f[9])begin
vld[{delay_ix, 4'b1001}] = wr_data;
one_way = wait_fill[1];
one_way[{delay_ix, 4'b1001}] = wr_data;
//wait_fill[1] = one_way;
end
if (wren_f[10])begin
vld[{delay_ix, 4'b1010}] = wr_data;
one_way = wait_fill[2];
one_way[{delay_ix, 4'b1010}] = wr_data;
//wait_fill[2] = one_way;
end
if (wren_f[11])begin
vld[{delay_ix, 4'b1011}] = wr_data;
one_way = wait_fill[3];
one_way[{delay_ix, 4'b1011}] = wr_data;
//wait_fill[3] = one_way;
end
if (wren_f[12])begin
vld[{delay_ix, 4'b1100}] = wr_data;
one_way = wait_fill[0];
one_way[{delay_ix, 4'b1100}] = wr_data;
//wait_fill[0] = one_way;
end
if (wren_f[13])begin
vld[{delay_ix, 4'b1101}] = wr_data;
one_way = wait_fill[1];
one_way[{delay_ix, 4'b1101}] = wr_data;
//wait_fill[1] = one_way;
end
if (wren_f[14])begin
vld[{delay_ix, 4'b1110}] = wr_data;
one_way = wait_fill[2];
one_way[{delay_ix, 4'b1110}] = wr_data;
//wait_fill[2] = one_way;
end
if (wren_f[15])begin
vld[{delay_ix, 4'b1111}] = wr_data;
one_way = wait_fill[3];
one_way[{delay_ix, 4'b1111}] = wr_data;
//wait_fill[3] = one_way;
end
end // if (delay_bf)
end // if (rst_l)
else begin
vld = 0;
end // else: !if(rst_l)
end // always @ (negedge clk)
//i$ and d$
integer at_pos ;
reg [1:0] way;
reg [5:0] addr_index;
reg [6:0] d_index, i_index;
reg [127:0] i_cache [3:0];
reg [127:0] d_cache [3:0];
reg [`CPX_WIDTH-1:0] cpx;
reg [3:0] d_watch_dog;
reg [3:0] i_watch_dog;
reg [3:0] pcx_dwatch_dog;
reg [3:0] pcx_iwatch_dog;
reg [7:0] d_count[255:0];
reg [7:0] i_count[255:0];
reg [127:0] pcx_icache [3:0];
reg [127:0] pcx_dcache [3:0];
reg [7:0] pcx_dcount[511:0];
reg [7:0] pcx_icount[511:0];
reg [1:0] thrid;
reg [127:0] t_vald;
reg [3:0] imiss_vld;
initial begin
for(i = 0; i < 4;i = i + 1)begin
i_cache[i] = 0;
d_cache[i] = 0;
pcx_icache[i] = 0;
pcx_dcache[i] = 0;
pcx_dcount[i] = 0;
pcx_icount[i] = 0;
wait_fill[i] = 0;
end
for(i = 0; i < 255;i = i + 1)begin
i_count[i] = 0;
d_count[i] = 0;
end
d_watch_dog = 0;
i_watch_dog = 0;
imiss_vld = 0;
end
//generate watch dog signal
task watch;
begin
i_watch_dog = 0;
d_watch_dog = 0;
pcx_dwatch_dog = 0;
pcx_iwatch_dog = 0;
for(i = 0; i < 4;i = i + 1)begin
d_watch_dog[i] = |d_cache[i];
i_watch_dog[i] = |i_cache[i];
end
end
endtask
//generate cache update bit.
task update_cache;
input [1:0] db;
input ib;
input i_ok;
reg [63:0] dw;
begin
if(cpx[0])begin
case(way)
2'b00 : dw = w0;
2'b01 : dw = w1;
2'b10 : dw = w2;
2'b11 : dw = w3;
endcase // case(way)
d_index = {addr_index[3:0], db};
one_way = (1 << d_index);
d_cache[way] = d_cache[way] | one_way;
if(dw[d_index] == 1'b0)begin
/*$display("%0d:Error->way(%x) index(%x) Dcache valid bit is zero.",
$time, way, d_index);
$display("%d : Simulation -> FAIL(%0s)", $time, "Dcache valid bit is zero");
$sas_client("quit");
repeat(5)@(posedge clk);
`TOP_MOD.fail_flag = 1'b1;
$finish;*/
end
end
if(i_ok) begin
if(cpx[1])begin //icache
d_index = {addr_index[5:0], ib};
one_way = (1 << d_index);
i_cache[way] = i_cache[way] | one_way;
if(vld[{d_index, way}] == 1'b0 && l1warm)begin
if(wait_ifill(d_index, way))begin
$display("%0d:Error->way(%x) index(%x) Icache received the store invalid befor imiss return",
$time, way, d_index);
$display("%d : Simulation -> FAIL(%0s)", $time, "Icache valid bit is zero");
repeat(5)@(posedge clk);
`MONITOR_PATH.fail("Icache received the store invalid before imiss return");
end
end
end
end
end
endtask // update_cache
//cal index and way to generate a cache invalid signal
task cal_index;
begin
at_pos = spc << 2;
cpx = cpx_spc_data_cx;//save
addr_index[5:0] = cpx[117:112];//address 10:6
cpx = (cpx >> at_pos);
way = cpx[3:2];
update_cache(0, 0, 1);
cpx = cpx >> 32;
way = cpx[2:1];
update_cache(1, 0, 0);
cpx = cpx >> 24;
way = cpx[3:2];
update_cache(2, 1, 1);
cpx = cpx >> 32;
way = cpx[2:1];
update_cache(3, 0, 0);
watch;
end
endtask // cal_index
//monitor cpx packe and generate invalid information.
reg [127:0] tmp_one;
always @(posedge clk) begin
if(rst_l && cpx_spc_data_rdy_cx && cpx_spc_data_cx[`CPX_VLD])begin
case(cpx_spc_data_cx[`CPX_RQ_HI:`CPX_RQ_LO])
`ST_ACK,`STRST_ACK,`EVICT_REQ : begin
if(cpx_spc_data_cx[`CPX_DA_LO+111:`CPX_DA_LO] != 0)begin
$display("%0d:Info: Spc(%x) received invalid packet -> %x", $time, spc[2:0], cpx_spc_data_cx);
cal_index;
end
end
`IFILL_RET : begin
thrid = cpx_spc_data_cx[`CPX_TH_HI:`CPX_TH_LO];
if((cpx_spc_data_cx[`CPX_NC] == 0) &&
imiss_vld[thrid] )begin
one_way = (1 << imiss_index[thrid]);
tmp_one = wait_fill[imiss_way[thrid]];
pcx_icache[imiss_way[thrid]] = pcx_icache[imiss_way[thrid]] | one_way;
pcx_iwatch_dog = |pcx_icache[imiss_way[thrid]];
wait_fill[imiss_way[thrid]] = one_way | tmp_one ;
imiss_vld[thrid] = 0;
end
end
`LOAD_RET : begin
if((cpx_spc_data_cx[`CPX_NC] == 0) && (l_ptr != la_ptr))begin
la_ptr = la_ptr + 1;
end //
end
endcase
end
end // always @ (posedge clk)
function wait_ifill;
input [7:0] index;
input [1:0] way;
reg [127:0] valid;
begin
valid = wait_fill[way];
wait_ifill = ~valid[index];
end
endfunction // wait_ifill
// check dcache
function [63:0] check_valid_dcache;
input [63:0] dw;
input [63:0] w;
input [7:0] ind;
input [1:0] way;
integer i;
begin
check_valid_dcache = dw;
for(i = 0; i < 128; i = i + 1)begin
if(dw[i])begin
if(w[i] == 0)begin//invalid happen
check_valid_dcache[i] = 0;
d_count[ind+i] = 0;
d_watch_dog[way] = |check_valid_dcache;
$display("%0d:Info:Dcache updated way(%x) index(%x)", $time, way, i);
end
else if(d_count[i] > `CPX_INVALID_TIME)begin/*
$display("Error: Dcache not invalidated during %0d cycles way(%x) index(%x)",
`CPX_INVALID_TIME, way, i);
$display("%d : Simulation -> FAIL(%0s)", $time, "Dcache not Invalidated");
$sas_client("quit");
`TOP_MOD.fail_flag = 1'b1;
$finish;*/
end
else d_count[ind+i] = d_count[ind+i] + 1;
end
end
end
endfunction // check_valid
//check icache
reg [127:0] check_valid_icache_reg;
task check_valid_icache;
input [127:0] dw;
input [7:0] ind;
input [1:0] way;
integer i;
begin
check_valid_icache_reg = dw;
for(i = 0; i < 128; i = i + 1)begin
if(dw[i])begin
if(vld[{i, way}] == 0)begin//invalid happen
check_valid_icache_reg[i] = 0;
i_count[ind+i] = 0;
i_watch_dog[way] = |check_valid_icache_reg;
$display("%0d:Info:Icache updated way(%x) index(%x)", $time, way, i);
end
else if(i_count[i] > `CPX_INVALID_TIME)begin
$display("Error: Icache not invalidated during %0d cycles way(%x) index(%x)",
`CPX_INVALID_TIME, way, i);
$display("%d : Simulation -> FAIL(%0s)", $time, "Icache not Invalidated");
`MONITOR_PATH.fail("Icache not Invalidated");
end
else i_count[ind+i] = i_count[ind+i] + 1;
end
end
end
endtask
//check icache for data validation.
function [127:0] check_valid_pcx_icache;
input [127:0] dw;
input [7:0] ind;
input [1:0] way;
integer i;
begin
check_valid_pcx_icache = dw;
for(i = 0; i < 127; i = i + 1)begin
if(dw[i])begin
if(vld[{i, way}])begin//invalid happen
check_valid_pcx_icache[i] = 0;
pcx_icount[ind+i] = 0;
pcx_iwatch_dog[way] = |check_valid_pcx_icache;
$display("%0d:Info:Icache updated way(%x) index(%x)", $time, way, i);
end
else if(pcx_icount[i] > `CPX_INVALID_TIME)begin
// $display("Error: Icache not validated during %0d cycles way(%x) index(%x)",
// `CPX_INVALID_TIME, way, i);
// $display("%d : Simulation -> FAIL(%0s)", $time, "Icache not validated");
// $sas_client("quit");
// `TOP_MOD.fail_flag = 1'b1;
// $finish;
end
else pcx_icount[ind+i] = pcx_icount[ind+i] + 1;
end
end
end
endfunction // check_validinteger ind;
reg [3:0] ind;
always @(negedge clk)begin
if(rst_l && ((|d_watch_dog) || (|i_watch_dog) || (|pcx_iwatch_dog)))begin
for(ind = 0; ind < 4; ind = ind + 1)begin
if(d_watch_dog[ind])begin
case(ind)
0 : d_cache[ind] = check_valid_dcache(d_cache[ind], w0, 0, 0);
1 : d_cache[ind] = check_valid_dcache(d_cache[ind], w1, 128, 1);
2 : d_cache[ind] = check_valid_dcache(d_cache[ind], w2, 256, 2);
3 : d_cache[ind] = check_valid_dcache(d_cache[ind], w3, 384, 3);
endcase
end
if(i_watch_dog[ind])begin
case(ind)
0 : begin check_valid_icache(i_cache[ind], 0, 0);i_cache[ind] = check_valid_icache_reg;end
1 : begin check_valid_icache(i_cache[ind], 128, 1);i_cache[ind] = check_valid_icache_reg;end
2 : begin check_valid_icache(i_cache[ind], 256, 2);i_cache[ind] = check_valid_icache_reg;end
3 : begin check_valid_icache(i_cache[ind], 384, 3);i_cache[ind] = check_valid_icache_reg;end
endcase
end
if(pcx_iwatch_dog[ind])begin
case(ind)
0 : pcx_icache[ind] = check_valid_pcx_icache(pcx_icache[ind], 0, 0);
1 : pcx_icache[ind] = check_valid_pcx_icache(pcx_icache[ind], 128, 1);
2 : pcx_icache[ind] = check_valid_pcx_icache(pcx_icache[ind], 256, 2);
3 : pcx_icache[ind] = check_valid_pcx_icache(pcx_icache[ind], 384, 3);
endcase
end
end
end
end
//monitor pcx packet
reg [1:0] wy;
reg [6:0] idx;
always @(posedge clk)begin
if(rst_l)begin
if(spc_pcx_data_pa[`PCX_VLD])begin
case(spc_pcx_data_pa[`PCX_RQ_HI:`PCX_RQ_LO])
`IMISS_RQ : begin
if(spc_pcx_data_pa[`PCX_NC] == 0)begin
thrid = spc_pcx_data_pa[`PCX_TH_HI:`PCX_TH_LO];//new implement
idx = spc_pcx_data_pa[`PCX_AD_LO+11:`PCX_AD_LO+5];//new implement
wy = spc_pcx_data_pa[`PCX_WY_HI:`PCX_WY_LO];
// t_vald = wait_fill[wy];
t_vald[idx] = 0;
imiss_vld[thrid] = 1'b1;
// wait_fill[wy] = t_vald;
imiss_index[thrid] = idx;
imiss_way[thrid] = wy;
end
end // case: `IMISS_RQ
`LOAD_RQ : begin
if((spc_pcx_data_pa[`PCX_NC] == 0) && (spc_pcx_data_pa[`PCX_AD_HI:`PCX_AD_HI] == 0))begin
load_index[l_ptr] = spc_pcx_data_pa[`PCX_AD_LO+10:`PCX_AD_LO+4];
load_way[l_ptr] = spc_pcx_data_pa[`PCX_WY_HI:`PCX_WY_LO];
l_ptr = l_ptr + 1;
end
end
endcase
end
end
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_256_134.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_256_134 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q,
usedw);
input aclr;
input clock;
input [133:0] data;
input rdreq;
input wrreq;
output empty;
output [133:0] q;
output [7:0] usedw;
wire sub_wire0;
wire [133:0] sub_wire1;
wire [7:0] sub_wire2;
wire empty = sub_wire0;
wire [133:0] q = sub_wire1[133:0];
wire [7:0] usedw = sub_wire2[7:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.usedw (sub_wire2),
.almost_empty (),
.almost_full (),
.full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 134,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "134"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "134"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "134"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 134 0 INPUT NODEFVAL "data[133..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: q 0 0 134 0 OUTPUT NODEFVAL "q[133..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 134 0 data 0 0 134 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: q 0 0 134 0 @q 0 0 134 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_256_134_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
module controller(clk, IR, N, Z, P, StateID, Mux1, Mux2, Mux3, Mux4, Mux5, Mux6, Mux7, Mux11, Mux12, wrf, wpc, wir, lccr, aluop, alushop, wmem); // Implements the designed controller for LC-3b.
input [15:0] IR;
input clk, N, Z, P;
output reg [3:0] StateID;
output reg Mux1;
output reg [1:0] Mux2;
output reg [2:0] Mux3;
output reg [1:0] Mux4;
output reg [1:0] Mux5;
output reg [1:0] Mux6;
output reg [1:0] Mux7;
output reg Mux11;
output reg Mux12;
output reg wrf;
output reg wpc;
output reg wir;
output reg lccr;
output reg [1:0] aluop;
output reg [1:0] alushop;
output reg wmem;
assign Mux8 = IR[5];
assign Mux9 = (IR[11] && N) || (IR[10] && Z) || (IR[9] && P);
assign Mux10 = IR[11];
always@(posedge clk) begin
case(StateID)
1: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b01;
Mux5 = 2'b01;
Mux6 = 2'b10;
Mux7 = 2'b10;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b0;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
2: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b000;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
end
3: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b0;
aluop = {IR[15], IR[14]};
alushop = {IR[5], IR[4]};
wmem = 1'b1;
end
4: begin
Mux1 = 1'b1;
Mux2 = 2'b01;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b0;
Mux12 = 1'b0;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
end
5: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b011;
Mux4 = 2'b01;
Mux5 = 2'b00;
Mux6 = 2'b00;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
6: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
end
7: begin
Mux1 = 1'b1;
Mux2 = 2'b10;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
end
8: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b001;
Mux4 = 2'b01;
Mux5 = 2'b00;
Mux6 = 2'b01;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b0;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
9: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b101;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
10: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b01;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
end
11: begin
Mux1 = 1'b1;
Mux2 = 2'b00;
Mux3 = 3'b111;
Mux4 = 2'b10;
Mux5 = 2'b10;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b0;
Mux12 = 1'b0;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b0;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
12: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b010;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
13: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b011;
Mux4 = 2'b01;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b0;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
14: begin
Mux1 = 1'b1;
Mux2 = 2'b01;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b0;
Mux12 = 1'b0;
wrf = 1'b0;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
end
15: begin
Mux1 = 1'b0;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b1;
end
16: begin
Mux1 = 1'b0;
Mux2 = 2'b11;
Mux3 = 3'b101;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
17: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b111;
Mux4 = 2'b11;
Mux5 = 2'b11;
Mux6 = 2'b11;
Mux7 = 2'b01;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b11;
alushop = 2'b11;
wmem = 1'b0;
end
18: begin
Mux1 = 1'b1;
Mux2 = 2'b11;
Mux3 = 3'b010;
Mux4 = 2'b00;
Mux5 = 2'b00;
Mux6 = 2'b11;
Mux7 = 2'b11;
Mux11 = 1'b1;
Mux12 = 1'b0;
wrf = 1'b1;
wpc = 1'b1;
wir = 1'b1;
lccr = 1'b1;
aluop = 2'b00;
alushop = 2'b11;
wmem = 1'b1;
end
endcase
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFXTP_4_V
`define SKY130_FD_SC_HS__SDFXTP_4_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfxtp_4 (
CLK ,
D ,
Q ,
SCD ,
SCE ,
VPWR,
VGND
);
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
sky130_fd_sc_hs__sdfxtp base (
.CLK(CLK),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfxtp_4 (
CLK,
D ,
Q ,
SCD,
SCE
);
input CLK;
input D ;
output Q ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfxtp base (
.CLK(CLK),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFXTP_4_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Wed Oct 18 10:48:44 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top srio_gen2_0 -prefix
// srio_gen2_0_ srio_gen2_0_stub.v
// Design : srio_gen2_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "srio_gen2_v4_0_5,Vivado 2015.1.0" *)
module srio_gen2_0(sys_clkp, sys_clkn, sys_rst, log_clk_out,
phy_clk_out, gt_clk_out, gt_pcs_clk_out, drpclk_out, refclk_out, clk_lock_out, cfg_rst_out,
log_rst_out, buf_rst_out, phy_rst_out, gt_pcs_rst_out, gt0_qpll_clk_out,
gt0_qpll_out_refclk_out, srio_rxn0, srio_rxp0, srio_rxn1, srio_rxp1, srio_txn0, srio_txp0,
srio_txn1, srio_txp1, s_axis_iotx_tvalid, s_axis_iotx_tready, s_axis_iotx_tlast,
s_axis_iotx_tdata, s_axis_iotx_tkeep, s_axis_iotx_tuser, m_axis_iorx_tvalid,
m_axis_iorx_tready, m_axis_iorx_tlast, m_axis_iorx_tdata, m_axis_iorx_tkeep,
m_axis_iorx_tuser, s_axi_maintr_rst, s_axi_maintr_awvalid, s_axi_maintr_awready,
s_axi_maintr_awaddr, s_axi_maintr_wvalid, s_axi_maintr_wready, s_axi_maintr_wdata,
s_axi_maintr_bvalid, s_axi_maintr_bready, s_axi_maintr_bresp, s_axi_maintr_arvalid,
s_axi_maintr_arready, s_axi_maintr_araddr, s_axi_maintr_rvalid, s_axi_maintr_rready,
s_axi_maintr_rdata, s_axi_maintr_rresp, sim_train_en, force_reinit, phy_mce,
phy_link_reset, phy_rcvd_mce, phy_rcvd_link_reset, phy_debug, gtrx_disperr_or,
gtrx_notintable_or, port_error, port_timeout, srio_host, port_decode_error, deviceid,
idle2_selected, phy_lcl_master_enable_out, buf_lcl_response_only_out,
buf_lcl_tx_flow_control_out, buf_lcl_phy_buf_stat_out, phy_lcl_phy_next_fm_out,
phy_lcl_phy_last_ack_out, phy_lcl_phy_rewind_out, phy_lcl_phy_rcvd_buf_stat_out,
phy_lcl_maint_only_out, port_initialized, link_initialized, idle_selected, mode_1x)
/* synthesis syn_black_box black_box_pad_pin="sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_rxn1,srio_rxp1,srio_txn0,srio_txp0,srio_txn1,srio_txp1,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x" */;
input sys_clkp;
input sys_clkn;
input sys_rst;
output log_clk_out;
output phy_clk_out;
output gt_clk_out;
output gt_pcs_clk_out;
output drpclk_out;
output refclk_out;
output clk_lock_out;
output cfg_rst_out;
output log_rst_out;
output buf_rst_out;
output phy_rst_out;
output gt_pcs_rst_out;
output gt0_qpll_clk_out;
output gt0_qpll_out_refclk_out;
input srio_rxn0;
input srio_rxp0;
input srio_rxn1;
input srio_rxp1;
output srio_txn0;
output srio_txp0;
output srio_txn1;
output srio_txp1;
input s_axis_iotx_tvalid;
output s_axis_iotx_tready;
input s_axis_iotx_tlast;
input [63:0]s_axis_iotx_tdata;
input [7:0]s_axis_iotx_tkeep;
input [31:0]s_axis_iotx_tuser;
output m_axis_iorx_tvalid;
input m_axis_iorx_tready;
output m_axis_iorx_tlast;
output [63:0]m_axis_iorx_tdata;
output [7:0]m_axis_iorx_tkeep;
output [31:0]m_axis_iorx_tuser;
input s_axi_maintr_rst;
input s_axi_maintr_awvalid;
output s_axi_maintr_awready;
input [31:0]s_axi_maintr_awaddr;
input s_axi_maintr_wvalid;
output s_axi_maintr_wready;
input [31:0]s_axi_maintr_wdata;
output s_axi_maintr_bvalid;
input s_axi_maintr_bready;
output [1:0]s_axi_maintr_bresp;
input s_axi_maintr_arvalid;
output s_axi_maintr_arready;
input [31:0]s_axi_maintr_araddr;
output s_axi_maintr_rvalid;
input s_axi_maintr_rready;
output [31:0]s_axi_maintr_rdata;
output [1:0]s_axi_maintr_rresp;
input sim_train_en;
input force_reinit;
input phy_mce;
input phy_link_reset;
output phy_rcvd_mce;
output phy_rcvd_link_reset;
output [223:0]phy_debug;
output gtrx_disperr_or;
output gtrx_notintable_or;
output port_error;
output [23:0]port_timeout;
output srio_host;
output port_decode_error;
output [15:0]deviceid;
output idle2_selected;
output phy_lcl_master_enable_out;
output buf_lcl_response_only_out;
output buf_lcl_tx_flow_control_out;
output [5:0]buf_lcl_phy_buf_stat_out;
output [5:0]phy_lcl_phy_next_fm_out;
output [5:0]phy_lcl_phy_last_ack_out;
output phy_lcl_phy_rewind_out;
output [5:0]phy_lcl_phy_rcvd_buf_stat_out;
output phy_lcl_maint_only_out;
output port_initialized;
output link_initialized;
output idle_selected;
output mode_1x;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__A211OI_BEHAVIORAL_PP_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211OI_BEHAVIORAL_PP_V |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module AESL_automem_prod (
clk,
rst,
ce0,
we0,
address0,
din0,
dout0,
ce1,
we1,
address1,
din1,
dout1,
ready,
done
);
//------------------------Parameter----------------------
localparam
TV_IN = "../tv/cdatafile/c.matrix_mult.autotvin_prod.dat",
TV_OUT = "../tv/rtldatafile/rtl.matrix_mult.autotvout_prod.dat";
//------------------------Local signal-------------------
parameter DATA_WIDTH = 32'd 16;
parameter ADDR_WIDTH = 32'd 5;
parameter DEPTH = 32'd 25;
parameter DLY = 0.1;
// Input and Output
input clk;
input rst;
input ce0, ce1;
input we0, we1;
input [ADDR_WIDTH - 1 : 0] address0, address1;
input [DATA_WIDTH - 1 : 0] din0, din1;
output reg [DATA_WIDTH - 1 : 0] dout0, dout1;
input ready;
input done;
// Inner signals
reg [DATA_WIDTH - 1 : 0] mem [0 : DEPTH - 1];
initial begin : initialize_mem
integer i;
for (i = 0; i < DEPTH; i = i + 1) begin
mem[i] = 0;
end
end
reg writed_flag;
event write_process_done;
//------------------------Task and function--------------
task read_token;
input integer fp;
output reg [127 :0] token;
integer ret;
begin
token = "";
ret = 0;
ret = $fscanf(fp,"%s",token);
end
endtask
//------------------------Read array-------------------
// Read data form file to array
initial begin : read_file_process
integer fp;
integer err;
integer ret;
reg [127 : 0] token;
reg [ 8*5 : 1] str;
reg [ DATA_WIDTH - 1 : 0 ] mem_tmp;
integer transaction_idx;
integer i;
transaction_idx = 0;
wait(rst === 0);
@(write_process_done);
fp = $fopen(TV_IN,"r");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", TV_IN);
$finish;
end
read_token(fp, token);
if (token != "[[[runtime]]]") begin // Illegal format
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
while (token != "[[[/runtime]]]") begin
if (token != "[[transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token); // skip transaction number
while(ready == 0) begin
@(write_process_done);
end
for(i = 0; i < DEPTH; i = i + 1) begin
read_token(fp, token);
ret = $sscanf(token, "0x%x", mem_tmp);
mem[i] = mem_tmp;
if (ret != 1) begin
$display("Failed to parse token!");
$finish;
end
end
@(write_process_done);
read_token(fp, token);
if(token != "[[/transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
transaction_idx = transaction_idx + 1;
end
$fclose(fp);
end
// Read data from array to RTL
always @ (posedge clk or rst) begin
if(rst === 1) begin
dout0 = 0;
end
else begin
if((we0 == 0) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
dout0 = #DLY din1;
else if(ce0 == 1)
dout0 = #DLY mem[address0];
else ;
end
end
always @ (posedge clk or rst) begin
if(rst === 1) begin
dout1 = 0;
end
else begin
if((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 0) && (address0 == address1))
dout1 = #DLY din0;
else if(ce1 == 1)
dout1 = #DLY mem[address1];
else ;
end
end
//------------------------Write array-------------------
// Write data from RTL to array
always @ (posedge clk) begin
if((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
mem[address0] <= #DLY din1;
else if ((we0 == 1) && (ce0 == 1))
mem[address0] <= #DLY din0;
end
always @ (posedge clk) begin
if((ce1 == 1) && (we1 == 1))
mem[address1] <= #DLY din1;
end
// Write data from array to file
initial begin : write_file_proc
integer fp;
integer transaction_num;
reg [ 8*5 : 1] str;
integer i;
transaction_num = 0;
writed_flag = 1;
wait(rst === 0);
@(negedge clk);
while(1) begin
while(done == 0) begin
-> write_process_done;
@(negedge clk);
end
fp = $fopen(TV_OUT, "a");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", TV_OUT);
$finish;
end
$fdisplay(fp, "[[transaction]] %d", transaction_num);
for (i = 0; i < DEPTH; i = i + 1) begin
$fdisplay(fp,"0x%x",mem[i]);
end
$fdisplay(fp, "[[/transaction]]");
transaction_num = transaction_num + 1;
$fclose(fp);
writed_flag = 1;
-> write_process_done;
@(negedge clk);
end
end
//------------------------conflict check-------------------
always @ (posedge clk) begin
if ((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
$display($time,"WARNING:write conflict----port0 and port1 write to the same address:%h at the same clock. Port1 has the high priority.",address0);
end
always @ (posedge clk) begin
if ((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 0) && (address0 == address1))
$display($time,"NOTE:read & write conflict----port0 write and port1 read to the same address:%h at the same clock. Write first Mode.",address0);
end
always @ (posedge clk) begin
if ((we0 == 0) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
$display($time,"NOTE:read & write conflict----port0 read and port1 write to the same address:%h at the same clock. Write first Mode.",address0);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBE_P_TB_V
`define SKY130_FD_SC_HDLL__PROBE_P_TB_V
/**
* probe_p: Virtual voltage probe point.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__probe_p.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hdll__probe_p dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBE_P_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DIODE_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DIODE_PP_BLACKBOX_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DIODE_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EDFXBP_BLACKBOX_V
`define SKY130_FD_SC_LP__EDFXBP_BLACKBOX_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__edfxbp (
Q ,
Q_N,
CLK,
D ,
DE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__EDFXBP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BO_2_V
`define SKY130_FD_SC_HDLL__A21BO_2_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21bo_2 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21bo_2 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BO_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__NAND3B_BEHAVIORAL_PP_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand3b (
VPWR,
VGND,
Y ,
A_N ,
B ,
C
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A_N ;
input B ;
input C ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , B, not0_out, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3B_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/27 21:57:27
// Design Name:
// Module Name: Datapath_with_mux_adder_register_memory
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Datapath_with_mux_adder_register_memory
#(parameter DATA_WIDTH = 8)
(
input Clk,
input reset,
input [(DATA_WIDTH - 1):0] reset_value,
input a_sel,
input next_sel,
input sum_sel,
output [(DATA_WIDTH - 1):0] a_o,
output [(DATA_WIDTH - 1):0] next_o,
output [(DATA_WIDTH - 1):0] sum_o,
output [(DATA_WIDTH - 1):0] ld_next_o,
output [(DATA_WIDTH - 1):0] ld_sum_o,
output [(DATA_WIDTH - 1):0] add1_o,
output [(DATA_WIDTH - 1):0] add2_o,
output [(DATA_WIDTH - 1):0] mem_o,
output next_zero
);
assign next_zero = (next_o == 0);
mux_8bit_2to1_behavior #(DATA_WIDTH) A (.x(ld_next_o), .y(add2_o), .s(a_sel), .m(a_o));
mux_8bit_2to1_behavior #(DATA_WIDTH) NEXT (.x(0), .y(mem_o), .s(next_sel), .m(next_o));
mux_8bit_2to1_behavior #(DATA_WIDTH) SUM (.x(0), .y(add1_o), .s(sum_sel), .m(sum_o));
Register_behavior #(DATA_WIDTH) LD_NEXT (.Clk(Clk), .D(next_o), .reset(reset), .reset_value(reset_value), .Q(ld_next_o));
Register_behavior #(DATA_WIDTH) LD_SUM (.Clk(Clk), .D(sum_o), .reset(reset), .reset_value(reset_value), .Q(ld_sum_o));
Adder_dataflow #(DATA_WIDTH) ADD1 (.a(ld_sum_o), .b(mem_o), .s(add1_o));
Adder_dataflow #(DATA_WIDTH) ADD2 (.a(ld_next_o), .b(1), .s(add2_o));
memory #(DATA_WIDTH) MEM (.address(a_o), .data(mem_o));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41A_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__O41A_PP_BLACKBOX_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41A_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3_TB_V
`define SKY130_FD_SC_HD__NAND3_TB_V
/**
* nand3: 3-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hd__nand3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311OI_2_V
`define SKY130_FD_SC_LP__A311OI_2_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a311oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311oi_2 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311OI_2_V
|
// hps_sdram.v
// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2015.01.07.15:40:35
`timescale 1 ps / 1 ps
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_7"),
.ENUM_MEM_IF_TCWL ("TCWL_7"),
.ENUM_MEM_IF_TFAW ("TFAW_15"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_14"),
.ENUM_MEM_IF_TRC ("TRC_20"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_3"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_4"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (3120),
.INTG_MEM_IF_TRFC (120),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FILL_PP_SYMBOL_V
`define SKY130_FD_SC_HD__FILL_PP_SYMBOL_V
/**
* fill: Fill cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fill (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FILL_PP_SYMBOL_V
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
//
// Intel PSG Max 10 DevKit Reference Design
//
module ip_test_top
(
input clk_50,
input clk_slow,
input fpga_reset_n,
output qspi_clk,
inout [3:0] qspi_io,
output qspi_csn,
input uart_0_rx,
output uart_0_tx,
input uart_1_rx,
output uart_1_tx,
output [4:0] user_led,
input [3:0] user_pb
);
assign user_led = 5'b0;
wire irom_cs;
wire [23:0] irom_addr;
wire [31:0] irom_data;
irom irom
(
.clk(clk_50),
.addr(irom_addr),
.cs(irom_cs),
.dout(irom_data)
);
wire [31:0] dram_addr;
wire dram_cs;
wire dram_wr;
wire [3:0] dram_mask;
wire [31:0] dram_din;
wire [31:0] dram_dout;
dram dram
(
.clk(clk_50),
.addr(dram_addr),
.cs(dram_cs),
.wr(dram_wr),
.mask(dram_mask),
.din(dram_din),
.dout(dram_dout)
);
wire [31:0] test_progress;
wire [31:0] test_fail;
wire [31:0] test_pass;
wire [68:0] rcn_00;
wire [68:0] rcn_01;
wire [68:0] rcn_02;
wire [68:0] rcn_03;
wire [68:0] rcn_04;
wire [68:0] rcn_05;
tawas #(.MASTER_ID(0)) tawas
(
.clk(clk_50),
.rst(!fpga_reset_n),
.ics(irom_cs),
.iaddr(irom_addr),
.idata(irom_data),
.dcs(dram_cs),
.dwr(dram_wr),
.daddr(dram_addr),
.dmask(dram_mask),
.dout(dram_din),
.din(dram_dout),
.rcn_in(rcn_00),
.rcn_out(rcn_01)
);
rcn_testregs #(.ADDR_BASE(24'hFFFFF0)) testregs
(
.clk(clk_50),
.rst(!fpga_reset_n),
.test_progress(),
.test_progress(),
.test_pass(),
.rcn_in(rcn_01),
.rcn_out(rcn_02)
);
rcn_ram #(.ADDR_BASE(24'hFE0000)) sram_0
(
.clk(clk_50),
.rst(!fpga_reset_n),
.rcn_in(rcn_02),
.rcn_out(rcn_03)
);
wire uart_0_tx_req;
wire uart_0_rx_req;
wire uart_1_tx_req;
wire uart_1_rx_req;
rcn_uart #(.ADDR_BASE(24'hFFFFB8), .SAMPLE_CLK_DIV(6'd3)) uart_0
(
.clk(clk_50),
.clk_50(clk_50),
.rst(!fpga_reset_n),
.rcn_in(rcn_03),
.rcn_out(rcn_04),
.tx_req(uart_0_tx_req),
.rx_req(uart_0_rx_req),
.uart_tx(uart_0_tx),
.uart_rx(uart_0_rx)
);
wire [68:0] rcn_10;
wire [68:0] rcn_11;
wire [68:0] rcn_12;
rcn_bridge_buf #(.ID_MASK(6'h3C), .ID_BASE(6'h04),
.ADDR_MASK(24'hF00000), .ADDR_BASE(24'h000000)) bridge_1
(
.clk(clk_50),
.rst(!fpga_reset_n),
.main_rcn_in(rcn_04),
.main_rcn_out(rcn_05),
.sub_rcn_in(rcn_10),
.sub_rcn_out(rcn_11)
);
rcn_ram #(.ADDR_BASE(24'h0E0000)) sram_1
(
.clk(clk_50),
.rst(!fpga_reset_n),
.rcn_in(rcn_11),
.rcn_out(rcn_12)
);
rcn_dma #(.ADDR_BASE(24'h0FFFC0), .MASTER_ID(4)) dma_1
(
.clk(clk_50),
.rst(!fpga_reset_n),
.rcn_in(rcn_12),
.rcn_out(rcn_10),
.req({11'd0, uart_1_rx_req, uart_1_tx_req,
uart_0_rx_req, uart_0_tx_req, 1'b1}),
.done()
);
wire [68:0] rcn_20;
wire [68:0] rcn_21;
wire [68:0] rcn_22;
wire [68:0] rcn_23;
rcn_bridge_async #(.ID_MASK(6'h3C), .ID_BASE(6'h08),
.ADDR_MASK(24'h300000), .ADDR_BASE(24'h100000)) bridge_2
(
.main_clk(clk_50),
.main_rst(!fpga_reset_n),
.sub_clk(clk_slow),
.main_rcn_in(rcn_05),
.main_rcn_out(rcn_00),
.sub_rcn_in(rcn_20),
.sub_rcn_out(rcn_21)
);
rcn_ram #(.ADDR_BASE(24'h1E0000)) sram_2
(
.clk(clk_slow),
.rst(!fpga_reset_n),
.rcn_in(rcn_21),
.rcn_out(rcn_22)
);
rcn_spdr #(.MASTER_ID(9), .SAMPLE_CLK_DIV(6'd3)) spdr_1
(
.clk(clk_slow),
.clk_50(clk_50),
.rst(!fpga_reset_n),
.rcn_in(rcn_22),
.rcn_out(rcn_23),
.gpi(32'hDEADBEEF),
.gpi_strobe(),
.gpo(),
.gpo_strobe(),
.uart_tx(uart_1_tx),
.uart_rx(uart_1_rx)
);
rcn_dma #(.ADDR_BASE(24'h1FFFC0), .MASTER_ID(8)) dma_2
(
.clk(clk_slow),
.rst(!fpga_reset_n),
.rcn_in(rcn_23),
.rcn_out(rcn_20),
.req(16'h0001),
.done()
);
endmodule
|
/* a lpc decoder
* lpc signals:
* lpc_ad: 4 data lines
* lpc_frame: frame to start a new transaction. active low
* lpc_reset: reset line. active low
* output signals:
* out_cyctype_dir: type and direction. same as in LPC Spec 1.1
* out_addr: 16-bit address
* out_data: data read or written (1byte)
* out_clock_enable: on rising edge all data must read.
*/
module lpc(
input [3:0] lpc_ad,
input lpc_clock,
input lpc_frame,
input lpc_reset,
input reset,
output [3:0] out_cyctype_dir,
output [31:0] out_addr,
output [7:0] out_data,
output out_sync_timeout,
output reg out_clock_enable);
/* type and direction. same as in LPC Spec 1.1 */
/* addr + data written or read */
/* state machine */
reg [3:0] state = 0;
localparam idle = 0, start = 1, cycle_dir = 2, address = 3, tar = 4, sync = 5, read_data = 6, abort = 7;
/* counter used by some states */
reg [3:0] counter;
/* mode + direction. same as in LPC Spec 1.1 */
reg [3:0] cyctype_dir;
reg [31:0] addr;
reg [7:0] data;
always @(negedge lpc_clock or negedge lpc_reset) begin
if (~lpc_reset) begin
state <= idle;
counter <= 1;
end
else begin
if (~lpc_frame) begin
counter <= 1;
if (lpc_ad == 4'b0000) /* start condition */
state <= cycle_dir;
else
state <= idle; /* abort */
end else begin
counter <= counter - 1;
case (state)
cycle_dir:
cyctype_dir <= lpc_ad;
address: begin
addr[31:4] <= addr[27:0];
addr[3:0] <= lpc_ad;
end
read_data: begin
data[7:4] <= lpc_ad;
data[3:0] <= data[7:4];
end
sync: begin
if (lpc_ad == 4'b0000)
if (cyctype_dir[3] == 0) begin /* i/o or memory */
state <= read_data;
data <= 0;
counter <= 2;
end else
state <= idle; /* unsupported dma or reserved */
end
default:
begin end
endcase
if (counter == 1) begin
case (state)
idle: begin end
cycle_dir: begin
out_clock_enable <= 0;
out_sync_timeout <= 0;
if (lpc_ad[3:2] == 2'b00) begin /* i/o */
state <= address;
counter <= 4;
addr <= 0;
end
else if (lpc_ad[3:2] == 2'b01) begin /* memory */
state <= address;
counter <= 8;
addr <= 0;
end else begin /* dma or reserved not yet supported */
state <= idle;
end
end
address: begin
if (cyctype_dir[1]) /* write memory or i/o */
state <= read_data;
else /* read memory or i/o */
state <= tar;
counter <= 2;
end
tar: begin
state <= sync;
counter <= 1;
end
sync: begin
if (lpc_ad == 4'b1111) begin
out_sync_timeout <= 1;
out_clock_enable <= 1;
state <= idle;
end
end
read_data: begin
out_clock_enable <= 1;
state <= idle;
end
/* todo: missing TAR after read_data */
abort: counter <= 2;
endcase
end
end
end
end
assign out_cyctype_dir = cyctype_dir;
assign out_data = data;
assign out_addr = addr;
endmodule
|
`timescale 1ns/10ps
module MainTest;
wire [7:0] leds;
initial begin
$dumpfile("./projects/LedPattern/LedPattern.vcd");
$dumpvars;
#100 $finish;
end
LedPattern
ledPattern(.leds(leds));
endmodule // MainTest
module UpCounter(clock,reset,count,data_o);
parameter Size = 8;
input wire [('b1) - ('b1):0] clock;
input wire [('b1) - ('b1):0] reset;
input wire [('b1) - ('b1):0] count;
output reg [(Size) - ('b1):0] data_o;
always @ (posedge clock) begin
if (reset) begin
data_o <= {Size{1'b0}};
end
else begin
if (count) begin
data_o <= data_o + 1;
end
end
end
endmodule // UpCounter
module UDCounter(clock,reset,count,direction,data_o);
parameter Size = 8;
input wire [('b1) - ('b1):0] clock;
input wire [('b1) - ('b1):0] reset;
input wire [('b1) - ('b1):0] count;
input wire [('b1) - ('b1):0] direction;
output reg [(Size) - ('b1):0] data_o;
always @ (posedge clock) begin
if (reset) begin
data_o <= {Size{1'b0}};
end
else begin
if (count) begin
case (direction)
'b0: data_o <= data_o + 1;
'b1: data_o <= data_o - 1;
endcase
end
end
end
endmodule // UDCounter
module Mux2(select,data_i00,data_i01,data_o);
parameter Size = 8;
input wire [('d1) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
output reg [(Size) - ('b1):0] data_o;
always @ (select or data_i00 or data_i01) begin
case (select)
'b0:data_o = data_i00;
'b1:data_o = data_i01;
endcase // case (select)
end
endmodule // Mux2
module Mux4(select,data_i00,data_i01,data_i02,data_i03,data_o);
parameter Size = 8;
input wire [('d2) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03) begin
case (select)
'b00: data_o = data_i00;
'b01: data_o = data_i01;
'b10: data_o = data_i02;
'b11: data_o = data_i03;
endcase
end
endmodule // Mux4
module Mux8(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_o);
parameter Size = 8;
input wire [('d3) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07) begin
case (select)
'b000: data_o = data_i00;
'b001: data_o = data_i01;
'b010: data_o = data_i02;
'b011: data_o = data_i03;
'b100: data_o = data_i04;
'b101: data_o = data_i05;
'b110: data_o = data_i06;
'b111: data_o = data_i07;
endcase
end
endmodule // Mux8
module Mux16(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_i08,data_i09,data_i10,data_i11,data_i12,data_i13,data_i14,data_i15,data_o);
parameter Size = 8;
input wire [('d4) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
input wire [(Size) - ('b1):0] data_i08;
input wire [(Size) - ('b1):0] data_i09;
input wire [(Size) - ('b1):0] data_i10;
input wire [(Size) - ('b1):0] data_i11;
input wire [(Size) - ('b1):0] data_i12;
input wire [(Size) - ('b1):0] data_i13;
input wire [(Size) - ('b1):0] data_i14;
input wire [(Size) - ('b1):0] data_i15;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07 or
data_i08 or data_i09 or data_i10 or data_i11 or data_i12 or data_i13 or data_i14 or data_i15) begin
case (select)
'b0000: data_o = data_i00;
'b0001: data_o = data_i01;
'b0010: data_o = data_i02;
'b0011: data_o = data_i03;
'b0100: data_o = data_i04;
'b0101: data_o = data_i05;
'b0110: data_o = data_i06;
'b0111: data_o = data_i07;
'b1000: data_o = data_i08;
'b1001: data_o = data_i09;
'b1010: data_o = data_i10;
'b1011: data_o = data_i11;
'b1100: data_o = data_i12;
'b1101: data_o = data_i13;
'b1110: data_o = data_i14;
'b1111: data_o = data_i15;
endcase
end
endmodule // Mux16
module Mux32(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_i08,data_i09,data_i10,data_i11,data_i12,data_i13,data_i14,data_i15,data_i16,data_i17,data_i18,data_i19,data_i20,data_i21,data_i22,data_i23,data_i24,data_i25,data_i26,data_i27,data_i28,data_i29,data_i30,data_i31,data_o);
parameter Size = 8;
input wire [('d5) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
input wire [(Size) - ('b1):0] data_i08;
input wire [(Size) - ('b1):0] data_i09;
input wire [(Size) - ('b1):0] data_i10;
input wire [(Size) - ('b1):0] data_i11;
input wire [(Size) - ('b1):0] data_i12;
input wire [(Size) - ('b1):0] data_i13;
input wire [(Size) - ('b1):0] data_i14;
input wire [(Size) - ('b1):0] data_i15;
input wire [(Size) - ('b1):0] data_i16;
input wire [(Size) - ('b1):0] data_i17;
input wire [(Size) - ('b1):0] data_i18;
input wire [(Size) - ('b1):0] data_i19;
input wire [(Size) - ('b1):0] data_i20;
input wire [(Size) - ('b1):0] data_i21;
input wire [(Size) - ('b1):0] data_i22;
input wire [(Size) - ('b1):0] data_i23;
input wire [(Size) - ('b1):0] data_i24;
input wire [(Size) - ('b1):0] data_i25;
input wire [(Size) - ('b1):0] data_i26;
input wire [(Size) - ('b1):0] data_i27;
input wire [(Size) - ('b1):0] data_i28;
input wire [(Size) - ('b1):0] data_i29;
input wire [(Size) - ('b1):0] data_i30;
input wire [(Size) - ('b1):0] data_i31;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07 or
data_i08 or data_i09 or data_i10 or data_i11 or data_i12 or data_i13 or data_i14 or data_i15 or
data_i16 or data_i17 or data_i18 or data_i19 or data_i20 or data_i21 or data_i22 or data_i23 or
data_i24 or data_i25 or data_i26 or data_i27 or data_i28 or data_i29 or data_i30 or data_i31) begin
case (select)
'b00000: data_o = data_i00;
'b00001: data_o = data_i01;
'b00010: data_o = data_i02;
'b00011: data_o = data_i03;
'b00100: data_o = data_i04;
'b00101: data_o = data_i05;
'b00110: data_o = data_i06;
'b00111: data_o = data_i07;
'b01000: data_o = data_i08;
'b01001: data_o = data_i09;
'b01010: data_o = data_i10;
'b01011: data_o = data_i11;
'b01100: data_o = data_i12;
'b01101: data_o = data_i13;
'b01110: data_o = data_i14;
'b01111: data_o = data_i15;
'b10000: data_o = data_i16;
'b10001: data_o = data_i17;
'b10010: data_o = data_i18;
'b10011: data_o = data_i19;
'b10100: data_o = data_i20;
'b10101: data_o = data_i21;
'b10110: data_o = data_i22;
'b10111: data_o = data_i23;
'b11000: data_o = data_i24;
'b11001: data_o = data_i25;
'b11010: data_o = data_i26;
'b11011: data_o = data_i27;
'b11100: data_o = data_i28;
'b11101: data_o = data_i29;
'b11110: data_o = data_i30;
'b11111: data_o = data_i31;
endcase
end
endmodule // Mux32
module Reg(clock,reset,data_i,writeEn,data_o);
parameter Size = 8;
input wire [('d1) - ('b1):0] clock;
input wire [('d1) - ('b1):0] reset;
input wire [(Size) - ('b1):0] data_i;
input wire [('d1) - ('b1):0] writeEn;
output reg [(Size) - ('b1):0] data_o;
always @ (posedge clock) begin
if (reset) begin
data_o <= {Size{1'b0}};
end
else begin
if (writeEn) begin
data_o <= data_i;
end
end
end
endmodule // Reg
module FPGADCM(clock,reset,locked,clock_o0,clock_o90,clock_o180,clock_o270,clock_o2x,clock_o2x180);
input wire [('b1) - ('b1):0] clock;
input wire [('b1) - ('b1):0] reset;
output wire [('b1) - ('b1):0] locked;
output wire [('b1) - ('b1):0] clock_o0;
output wire [('b1) - ('b1):0] clock_o90;
output wire [('b1) - ('b1):0] clock_o180;
output wire [('b1) - ('b1):0] clock_o270;
output wire [('b1) - ('b1):0] clock_o2x;
output wire [('b1) - ('b1):0] clock_o2x180;
wire FPGABUFG_o;
wire FPGASPDCM_CLK0;
assign clock_o0 = FPGASPDCM_CLK0;
DCM_SP #(.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(0.0),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE"))
FPGASPDCM (.CLKIN(clock),
.CLKFB(FPGABUFG_o),
.RST(reset),
.DSSEN(0),
.PSINCDEC(0),
.PSEN(0),
.PSCLK(0),
.LOCKED(locked),
.CLK0(FPGASPDCM_CLK0),
.CLK90(clock_o90),
.CLK180(clock_o180),
.CLK270(clock_o270),
.CLK2X(clock_o2x),
.CLK2X180(clock_o2x180));
BUFG
FPGABUFG (.I(FPGASPDCM_CLK0),
.O(FPGABUFG_o));
endmodule // DCM
module LedPattern(
output wire [('b1000) - ('b1):0] leds);
assign leds = 'b10010100;
endmodule // LedPattern
|
(** %\chapter{Inductive Reasoning in SSReflect}% *)
From mathcomp.ssreflect
Require Import ssreflect eqtype ssrnat ssrbool ssrfun seq.
Module SsrStyle.
(**
In the rest of this lecture we will be constantly relying on a series
of standard SSReflect modules, such as [ssrbool], [ssrnat] and
[eqtype], which we import right away.
*)
(** * Structuring the proof scripts
An important part of the proof process is keeping to an established
proof layout, which helps to maintain the proofs readable and restore
the intuition driving the prover's hand. SSReflect offers a number of
syntactic primitives that help to maintain such a layout, and in this
section we give a short overview of them. As usual, the SSReflect
reference manual provides an exhaustive formal definition of each
primitive's semantics, so we will just cover the base cases here,
hoping that the subsequent proofs will provide more intuition on
typical usage scenarios.
** Bullets and terminators
*)
Lemma andb_true_elim b c: b && c -> c = true.
Proof.
case: c.
(**
[[
true = true
subgoal 2 (ID 15) is:
b && false -> false = true
]]
*)
- by case: b.
(** ** Using selectors and discharging subgoals
Let us restart this proof and show an alternative way to structure the
proof script, which should account for multiple cases.
*)
Restart.
case: c; first by [].
(**
[[
b : bool
============================
b && false -> false = true
]]
*)
Restart.
case:c; [by [] | by case: b].
(**
The script above solves the first generated goal using [by []], and
then solves the second one via [by case: b].
*)
(** ** Iteration and alternatives *)
Restart.
by do ![done | apply: eqxx | case: b | case: c].
Qed.
(** * Inductive predicates that should be functions *)
Inductive isZero (n: nat) : Prop := IsZero of n = 0.
(**
Naturally, such equality can be exploited to derived paradoxes, as the
following lemma shows:
*)
Lemma isZero_paradox: isZero 1 -> False.
Proof. by case. Qed.
(**
However, the equality on natural numbers is, decidable, so the very
same definition can be rewritten as a function employing the boolean
equality [(==)], which will make the proofs of paradoxes even shorter
than they already are:
*)
Definition is_zero n : bool := n == 0.
Lemma is_zero_paradox: is_zero 1 -> False.
Proof. done. Qed.
(**
That is, instead of the unavoidable case-analysis with the first
[Prop]-based definition, the functional definition made Coq compute
the result for us, deriving the falsehood automatically.
The benefits of the computable definitions become even more obvious
when considering the next example, the predicate defining whether a
natural number is even or odd. Again, we define two versions, the
inductive predicate and a boolean function.
*)
Inductive evenP n : Prop :=
Even0 of n = 0 | EvenSS m of n = m.+2 & evenP m.
Fixpoint evenb n := if n is n'.+2 then evenb n' else n == 0.
(**
Let us now prove a simple property: that fact that [(n + 1 + n)] is
even leads to a paradox. We first prove it for the version defined in
[Prop].
*)
Lemma evenP_contra n : evenP (n + 1 + n) -> False.
Proof.
elim: n=>//[| n Hn]; first by rewrite addn0 add0n; case=>//.
(**
[[
n : nat
Hn : evenP (n + 1 + n) -> False
============================
evenP (n.+1 + 1 + n.+1) -> False
]]
*)
rewrite addn1 addnS addnC !addnS.
rewrite addnC addn1 addnS in Hn.
(**
[[
n : nat
Hn : evenP (n + n).+1 -> False
============================
evenP (n + n).+3 -> False
]]
*)
case=>// m /eqP.
(**
[[
n : nat
Hn : evenP (n + n).+1 -> False
m : nat
============================
(n + n).+3 = m.+2 -> evenP m -> False
]]
*)
by rewrite !eqSS; move/eqP=><-.
Qed.
(**
Now, let us take a look at the proof of the same fact, but with the
computable version of the predicate [evenb].
*)
Lemma evenb_contra n: evenb (n + 1 + n) -> False.
Proof.
elim: n=>[|n IH] //.
(**
[[
n : nat
IH : evenb (n + 1 + n) -> False
============================
evenb (n.+1 + 1 + n.+1) -> False
]]
*)
by rewrite addSn addnS.
Qed.
(**
Sometimes, though, the value "orbits", which can be advantageous for
the proofs involving [bool]-returning predicates, might require a bit
trickier induction hypotheses than just the statement required to be
proved. Let us compare the two proofs of the same fact, formulated
with [evenP] and [evennb].
*)
Lemma evenP_plus n m : evenP n -> evenP m -> evenP (n + m).
Proof.
elim=>//n'; first by move=>->; rewrite add0n.
(**
[[
n : nat
m : nat
n' : nat
============================
forall m0 : nat,
n' = m0.+2 ->
evenP m0 -> (evenP m -> evenP (m0 + m)) -> evenP m -> evenP (n' + m)
]]
*)
move=> m'->{n'} H1 H2 H3; rewrite addnC !addnS addnC.
(**
[[
n : nat
m : nat
m' : nat
H1 : evenP m'
H2 : evenP m -> evenP (m' + m)
H3 : evenP m
============================
evenP (m' + m).+2
]]
*)
Check EvenSS.
(**
[[
EvenSS
: forall n m : nat, n = m.+2 -> evenP m -> evenP n
]]
*)
apply: (EvenSS _ (m' + m))=>//.
(**
[[
n : nat
m : nat
m' : nat
H1 : evenP m'
H2 : evenP m -> evenP (m' + m)
H3 : evenP m
============================
evenP (m' + m)
]]
*)
by apply: H2.
Qed.
(**
In this particular case, the resulting proof was quite
straightforward, thanks to the explicit equality [n = m.+2] in the
definition of the [EvenSS] constructor.
In the case of the boolean specification, though, the induction should
be done on the natural argument itself, which makes the first attempt
of the proof to be not entirely trivial.
*)
Lemma evenb_plus n m : evenb n -> evenb m -> evenb (n + m).
Proof.
elim: n=>[|n Hn]; first by rewrite add0n.
(**
[[
m : nat
n : nat
Hn : evenb n -> evenb m -> evenb (n + m)
============================
evenb n.+1 -> evenb m -> evenb (n.+1 + m)
]]
The problem now is that, if we keep building the proof by induction on
[n] or [m], the induction hypothesis and the goal will be always
"mismatched" by one, which will prevent us finishing the proof using
the hypothesis.
There are multiple ways to escape this vicious circle, and one of them
is to _generalize_ the induction hypothesis. To do so, let us restart
the proof.
*)
Restart.
move: (leqnn n).
(**
[[
n : nat
m : nat
============================
n <= n -> evenb n -> evenb m -> evenb (n + m)
]]
Now, we are going to proceed with the proof by _selective_ induction
on [n], such that some of its occurrences in the goal will be a
subject of inductive reasoning (namely, the second one), and some
others will be left generalized (that is, bound by a forall-quantified
variable). We do so by using SSReflect's tactics [elim] with explicit
_occurrence selectors_.
*)
elim: n {-2}n.
(**
[[
m : nat
============================
forall n : nat, n <= 0 -> evenb n -> evenb m -> evenb (n + m)
subgoal 2 (ID 860) is:
forall n : nat,
(forall n0 : nat, n0 <= n -> evenb n0 -> evenb m -> evenb (n0 + m)) ->
forall n0 : nat, n0 <= n.+1 -> evenb n0 -> evenb m -> evenb (n0 + m)
]]
The same effect could be achieved by using [elim: n {1 3 4}n], that
is, indicating which occurrences of [n] _should_ be generalized,
instead of specifying, which ones should not (as we did by means of
[{-2}n]).
*)
- by case=>//.
(**
For the second goal, we first move some of the assumptions to the context.
*)
move=>n Hn.
(**
[[
m : nat
n : nat
Hn : forall n0 : nat, n0 <= n -> evenb n0 -> evenb m -> evenb (n0 + m)
============================
forall n0 : nat, n0 <= n.+1 -> evenb n0 -> evenb m -> evenb (n0 + m)
]]
We then perform the case-analysis on [n0] in the goal, which results
in two goals, one of which is automatically discharged.
*)
case=>//.
(**
[[
m : nat
n : nat
Hn : forall n0 : nat, n0 <= n -> evenb n0 -> evenb m -> evenb (n0 + m)
============================
forall n0 : nat, n0 < n.+1 -> evenb n0.+1 -> evenb m -> evenb (n0.+1 + m)
]]
Doing _one more_ case analysis will adde one more [1] to the induction
variable [n0], which will bring us to the desired [(.+2)]-orbit.
*)
case=>// n0.
(**
[[
m : nat
n : nat
Hn : forall n0 : nat, n0 <= n -> evenb n0 -> evenb m -> evenb (n0 + m)
n0 : nat
============================
n0.+1 < n.+1 -> evenb n0.+2 -> evenb m -> evenb (n0.+2 + m)
]]
The only thing left to do is to tweak the top assumption (by relaxing
the inequality via the [ltnW] lemma), so we could apply the induction
hypothesis [Hn].
*)
by move/ltnW /Hn=>//.
Qed.
(** ** Eliminating assumptions with a custom induction hypothesis
The functions like [evenb], with specific value orbits, are not
particularly uncommon, and it is useful to understand the key
induction principles to reason about them. In particular, the above
discussed proof could have been much more straightforward if we first
proved a different induction principle [nat2_ind] for natural numbers.
*)
Lemma nat2_ind (P: nat -> Prop):
P 0 -> P 1 -> (forall n, P n -> P (n.+2)) -> forall n, P n.
Proof.
move=> H0 H1 H n.
(**
[[
P : nat -> Prop
H0 : P 0
H1 : P 1
H : forall n : nat, P n -> P n.+2
n : nat
============================
P n
]]
Unsurprisingly, the proof of this induction principle follows the same
pattern as the proof of [evenb_plus]---generalizing the hypothesis. In
this particular case, we generalize it in the way that it would
provide an "impedance matcher" between the 1-step "default" induction
principle on natural numbers and the 2-step induction in the
hypothesis [H]. We show that for the proof it is sufficient to
establish [(P n /\ P (n.+1))]:
*)
suff: (P n /\ P (n.+1)) by case.
(**
The rest of the proof proceeds by the standard induction on [n].
*)
by elim: n=>//n; case=> H2 H3; split=>//; last by apply: H.
Qed.
(**
Now, since the new induction principle [nat2_ind] exactly matches the
2-orbit, we can directly employ it for the proof of the previous result.
*)
Lemma evenb_plus' n m : evenb n -> evenb m -> evenb (n + m).
Proof.
by elim/nat2_ind : n.
Qed.
(**
Notice that we used the version of the [elim] tactics with specific
_elimination view_ [nat2_ind], different from the default one, which
is possible using the view tactical [/]. In this sense, the "standard
induction" [elim: n] would be equivalent to [elim/nat_ind: n].
*)
(** * Inductive predicates that are hard to avoid *)
Inductive beautiful (n: nat) : Prop :=
| b_0 of n = 0
| b_3 of n = 3
| b_5 of n = 5
| b_sum n' m' of beautiful n' & beautiful m' & n = n' + m'.
(**
The number is beautiful if it's either [0], [3], [5] or a sum of two
beautiful numbers. Indeed, there are many ways to decompose some
numbers into the sum $3 * n + 5 * n$. Encoding a function,
which checks whether a number is beautiful or not, although not
impossible, is not entirely trivial (and, in particular, it's not
trivial to prove the correctness of such function with respect to the
definition above). Therefore, if one decides to stick with the
predicate definition, some operations become tedious, as, even for
constants the property should be _inferred_ rather than proved:
*)
Theorem eight_is_beautiful: beautiful 8.
Proof.
apply: (b_sum _ 3 5)=>//; first by apply: b_3.
by apply b_5.
Qed.
Theorem b_times2 n: beautiful n -> beautiful (2 * n).
Proof.
by move=>H; apply: (b_sum _ n n)=>//; rewrite mul2n addnn.
Qed.
(**
In particular, the negation proofs become much less straightforward
than one would expect:
*)
Lemma one_not_beautiful n: n = 1 -> ~ beautiful n.
Proof.
move=>E H.
(**
[[
n : nat
E : n = 1
H : beautiful n
============================
False
]]
*)
elim: H E=>n'; do?[by move=>->].
move=> n1 m' _ H2 _ H4 -> {n' n}.
(**
Notice how the assumptions [n'] and [n] are removed from the context
(since we don't need them any more) by enumerating them using [{n' n}]
notation.
*)
case: n1 H2=>// n'=> H3.
by case: n' H3=>//; case.
Qed.
(** * Working with SSReflect libraries
We conclude this chapter with a short overview of a subset of the
standard SSReflect programming and naming policies, which will,
hopefully, simplify the use of the libraries in a standalone
development.
** Notation and standard operation properties
SSReflect's module [ssrbool] introduces convenient notation for
predicate connectives, such as [/\] and [\/]. In particular, multiple
conjunctions and disjunctions are better to be written as [[ /\ P1, P2
& P3]] and [[ \/ P1, P2 | P3]], respectively, opposed to [P1 /\ P2 /\
P3] and [P1 \/ P2 \/ P3]. The specific notation makes it more
convenient to use such connectives in the proofs that proceed by case
analysis. Compare.
*)
Lemma conj4 P1 P2 P3 P4 : P1 /\ P2 /\ P3 /\ P4 -> P3.
Proof. by case=>p1 [p2][p3]. Qed.
Lemma conj4' P1 P2 P3 P4 : [ /\ P1, P2, P3 & P4] -> P3.
Proof. by case. Qed.
Locate "_ ^~ _".
(**
[[
"f ^~ y" := fun x => f x y : fun_scope
]]
For instance, this is how one can now express the partially applied
function, which applies its argument to the list [[:: 1; 2; 3]]:
*)
Check map ^~ [:: 1; 2; 3].
(**
[[
map^~ [:: 1; 2; 3]
: (nat -> ?2919) -> seq ?2919
]]
Finally, [ssrfun] defines a number of standard operator properties,
such as commutativity, distributivity etc in the form of the
correspondingly defined predicates: [commutative], [right_inverse]
etc. For example, since we have now [ssrbool] and [ssrnat] imported,
we can search for left-distributive operations defined in those two
modules (such that they come with the proofs of the corresponding
predicates):
*)
Search _ (left_distributive _).
(**
[[
andb_orl left_distributive andb orb
orb_andl left_distributive orb andb
andb_addl left_distributive andb addb
addn_maxl left_distributive addn maxn
addn_minl left_distributive addn minn
...
]]
*)
(** ** A library for lists
For instance, properties of some of the functions, such as _list
reversal_ are simpler to prove not by the standard "direct" induction
on the list structure, but rather iterating the list from its last
element, for which the [seq] library provides the necessary definition
and induction principle:
[[
Fixpoint rcons s z := if s is x :: s' then x :: rcons s' z else [:: z].
]]
*)
Check last_ind.
(**
[[
last_ind
: forall (T : Type) (P : seq T -> Type),
P [::] ->
(forall (s : seq T) (x : T), P s -> P (rcons s x)) ->
forall s : seq T, P s
]]
To demonstrate the power of the library for reasoning with lists, let
us prove the following property, known as _Dirichlet's box principle_
(sometimes also referred to as _pigeonhole principle_).
*)
Variable A : eqType.
Fixpoint has_repeats (xs : seq A) :=
if xs is x :: xs' then (x \in xs') || has_repeats xs' else false.
(**
The following lemma states that for two lists [xs1] and [xs2], is the
size [xs2] is strictly smaller than the size of [xs1], but
nevertheless [xs1] as a set is a subset of [xs2] then there ought to
be repetitions in [xs1].
*)
Theorem dirichlet xs1 xs2 :
size xs2 < size xs1 -> {subset xs1 <= xs2} -> has_repeats xs1.
Proof.
(**
First, the proof scripts initiates the induction on the structure of
the first, "longer", list [xs1], simplifying and moving to the context
some hypotheses in the "step" case (as the [nil]-case is proved
automatically).
*)
elim: xs1 xs2=>[|x xs1 IH] xs2 //= H1 H2.
(**
[[
x : A
xs1 : seq A
IH : forall xs2 : seq A,
size xs2 < size xs1 -> {subset xs1 <= xs2} -> has_repeats xs1
xs2 : seq A
H1 : size xs2 < (size xs1).+1
H2 : {subset x :: xs1 <= xs2}
============================
(x \in xs1) || has_repeats xs1
]]
*)
case H3: (x \in xs1) => //=.
(**
[[
...
H3 : (x \in xs1) = false
============================
has_repeats xs1
]]
*)
pose xs2' := filter (predC (pred1 x)) xs2.
apply: (IH xs2'); last first.
(**
[[
...
H2 : {subset x :: xs1 <= xs2}
H3 : (x \in xs1) = false
xs2' := [seq x <- xs2 | (predC (pred1 x)) x0] : seq A
============================
{subset xs1 <= xs2'}
subgoal 2 (ID 5716) is:
size xs2' < size xs1
]]
*)
- move=>y H4; move: (H2 y); rewrite inE H4 orbT mem_filter /=.
by move => -> //; case: eqP H3 H4 => // ->->.
(**
The second goal requires to prove the inequality, which states that
after removal of [x] from [xs2], the length of the resulting list
[xs2] is smaller than the length of [xs1].
*)
rewrite ltnS in H1; apply: leq_trans H1.
rewrite -(count_predC (pred1 x) xs2) -addn1 addnC.
rewrite /xs2' size_filter leq_add2r -has_count.
(**
[[
...
H2 : {subset x :: xs1 <= xs2}
H3 : (x \in xs1) = false
xs2' := [seq x <- xs2 | (predC (pred1 x)) x0] : seq A
============================
has (pred1 x) xs2
]]
*)
by apply/hasP; exists x=>//=; apply: H2; rewrite inE eq_refl.
Qed.
(*******************************************************************)
(** * Exercices * *)
(*******************************************************************)
(**
---------------------------------------------------------------------
Exercise [Integer binary division]
---------------------------------------------------------------------
Let us define the binary division function [div2] as follows.
*)
Fixpoint div2 (n: nat) := if n is p.+2 then (div2 p).+1 else 0.
(**
Prove the following lemma directly by induction on [n], _without_
using the [nat2_ind] induction principle. Then prove it using
[nat2_ind].
*)
Lemma div2_le n: div2 n <= n.
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
---------------------------------------------------------------------
Exercise [Some facts about beautiful numbers]
---------------------------------------------------------------------
Proof the following theorem about beautiful numbers.
Hint: Choose wisely, what to build the induction on.
*)
Lemma b_timesm n m: beautiful n -> beautiful (m * n).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
---------------------------------------------------------------------
Exercise [Gorgeous numbers]
---------------------------------------------------------------------
To practice with proofs by induction, let us consider yet another
inductive predicate, defining which of natural numbers are _gorgeous_.
*)
Inductive gorgeous (n: nat) : Prop :=
| g_0 of n = 0
| g_plus3 m of gorgeous m & n = m + 3
| g_plus5 m of gorgeous m & n = m + 5.
(**
Prove by induction the following statements about gorgeous numbers.
Hint: As usual, do not hesitate to use the [Search] utility for
finding the necessary rewriting lemmas from the [ssrnat] module.
*)
Lemma gorgeous_plus13 n: gorgeous n -> gorgeous (n + 13).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
Lemma beautiful_gorgeous (n: nat) : beautiful n -> gorgeous n.
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
Lemma g_times2 (n: nat): gorgeous n -> gorgeous (n * 2).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
Lemma gorgeous_beautiful (n: nat) : gorgeous n -> beautiful n.
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
---------------------------------------------------------------------
Exercise [Gorgeous reflection]
---------------------------------------------------------------------
Gorgeous and beautiful numbers, defining, in fact, exactly the same
subset of [nat] are a particular case of Frobenius coin problem, which
asks for the largest integer amount of money, that cannot be obtained
using only coins of specified denominations. In the case of
[beautiful] and [gorgeous] numbers we have two denominations
available, namely 3 and 5. An explicit formula exists for the case
of only two denominations n_1 and n_2, which allows one to compute
the Frobenius number as
g(n_1, n_2) = n_1 * n_2 - n_1 - n_2.
That said, for the case n_1 = 3 and n_2 = 5 the Frobenius number is 7,
which means that all numbers greater or equal than 8 are in fact
beautiful and gorgeous (since the two are equivalent, as was
established by the previous exercise).
In this exercise, we suggest the reader to prove that the efficient
procedure of "checking" for gorgeousness is in fact correct. First,
let us defined the following candidate function.
*)
Fixpoint gorgeous_b n : bool := match n with
| 1 | 2 | 4 | 7 => false
| _ => true
end.
(**
The ultimate goal of this exercise is to prove the proposition
[reflect (gorgeous n) (gorgeous_b n)], which would mean that the two
representations are equivalent. Let us divide the proof into two
stages:
- The first stage is proving that all numbers greater or equal than
8 are gorgeous. To prove thism it might be useful to have the
following two facts established:
Hint: Use the tactic [constructor i] to prove a goal, which is an
n-ary disjunction, which is satisfied if its i-th disjunct is true.
*)
Lemma repr3 n : n >= 8 ->
exists k, [\/ n = 3 * k + 8, n = 3 * k + 9 | n = 3 * k + 10].
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
Lemma gorg3 n : gorgeous (3 * n).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
Next, we can establish by induction the following criteria using the
lemmas [repr3] and [gorg3] in the subgoals of the proof.
*)
Lemma gorg_criteria n : n >= 8 -> gorgeous n.
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
This makes the proof of the following lemma trivial.
*)
Lemma gorg_refl' n: n >= 8 -> reflect (gorgeous n) true.
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
- In the second stage of the proof of reflection, we will
need to prove four totally boring but unavoidable lemmas.
Hint: The rewriting lemmas [addnC] and [eqSS] from the [ssrnat]
module might be particularly useful here.
*)
Lemma not_g1: ~(gorgeous 1).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
Lemma not_g2: ~(gorgeous 2).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
Lemma not_g4: ~(gorgeous 4).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
Lemma not_g7: ~(gorgeous 7).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
We can finally provide prove the ultimate reflection predicate,
relating [gorgeous] and [gorgeous_b].
*)
Lemma gorg_refl n : reflect (gorgeous n) (gorgeous_b n).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
---------------------------------------------------------------------
Exercise [Boolean element inclusion predicate for lists]
---------------------------------------------------------------------
Assuming a type [X] with the boolean equality (i.e., elements of [X]
can be compared for being equal using the [==] operator returning
[true] or [false]), define a recursive funciton [appears_in] on lists
that takes an element [a : X], a list [l : seq X] and returns a
boolean value indicating whether [a] appears in [l] or not.
*)
Section Appears_bool.
Variable X: eqType.
Fixpoint appears_in (a: X) (l: seq X) : bool :=
(* fill in your implemenation istead of the [false] stub *)
false.
(**
Next, prove the following lemma, relating [appears_in] and list
concatenation [++].
*)
Lemma appears_in_app (xs ys : seq X) (x:X):
appears_in x (xs ++ ys) = appears_in x xs || appears_in x ys.
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
Let us define the functions [disjoint] and [no_repeats] using
[appears_in] as follows:
*)
Fixpoint disjoint (l1 l2: seq X): bool :=
if l1 is x::xs then ~~(appears_in x l2) && disjoint xs l2 else true.
Fixpoint no_repeats (ls : seq X) :=
if ls is x :: xs then ~~ (appears_in x xs) && no_repeats xs else true.
(**
Finally, prove the following lemma, realting [no_repeats] and
[disjoint].
*)
Theorem norep_disj_app l1 l2:
no_repeats l1 -> no_repeats l2 -> disjoint l1 l2 -> no_repeats (l1 ++ l2).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
End Appears_bool.
Eval compute in appears_in (EqType nat _) 1 [:: 1; 2; 3].
(* true *)
Eval compute in appears_in (EqType nat _) 1 [:: 2; 4; 3].
(* false *)
(**
---------------------------------------------------------------------
Exercise [Element inclusion predicate for lists in Prop]
---------------------------------------------------------------------
For types [Y] with propositional equality, define the [appears_inP]
predicate, which returns [Prop].
*)
Section Appears_Prop.
Variable Y: Type.
Variable appears_inP : forall (a: Y) (l: seq Y), Prop.
(* Replace Variable by the actual implementation *)
(**
Prove the lemma [appears_in_appP]:
*)
Lemma appears_in_appP (xs ys : seq Y) (x:Y):
appears_inP x (xs ++ ys) <-> appears_inP x xs \/ appears_inP x ys.
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
(**
Finally, define the [Prop]-versions of the [disjoint] and [no_repeat]
predicates: [disjointP] and [no_repeatP] and prove the following lemma
relating them.
*)
Variable disjointP : forall (l1 l2: seq Y), Prop.
(* Replace Variable by the actual implementation *)
Variable no_repeatsP : forall (ls : seq Y), Prop.
(* Replace Variable by the actual implementation *)
Theorem norep_disj_appP l1 l2:
no_repeatsP l1 -> no_repeatsP l2 -> disjointP l1 l2 -> no_repeatsP (l1 ++ l2).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
End Appears_Prop.
(**
---------------------------------------------------------------------
Exercise ["All" predicate for lists]
---------------------------------------------------------------------
Define two version of version of "all-elements-satisfy" predicate for
lists.
- The version [all] takes a type [X], a predicate [P : X -> Prop] and
a list [ls: seq X] and returns element of sort [Prop] which carries
a proof that all elements of ls satisfy [P].
- The decidable version [allb] takes a type [X], a predicate [test : X
-> bool] and a list [ls: seq X], and returns a boolean result.
Prove the lemma [allP], stating that the two representations are
equivalent whenever [P] and [test] are equivalent.
*)
Variable all : forall {X} (P : X -> Prop) (ls: seq X), Prop.
(* Replace Variable by the actual implementation *)
Variable allb : forall {X : Type} (test : X -> bool) (ls : seq X), bool.
(* Replace Variable by the actual implementation *)
Lemma allP T P test:
(forall x: T, reflect (P x) (test x)) ->
forall ls, reflect (all P ls) (allb test ls).
Proof.
(* fill in your proof here instead of [admit] *)
Admitted.
End SsrStyle.
|
module x (/*AUTOARG*/);
// Which Internal Bank
`define DMC_AG_HADDR_BADDR_BST2_RNG 1:0 // Bank Address Range within Hexabyte Address for 2-Burst
`define DMC_AG_HADDR_BADDR_BST4_RNG 2:1 // Bank Address Range within Hexabyte Address for 4-Burst
`define DMC_AG_HADDR_BADDR_BST8_RNG 3:2 // Bank Address Range within Hexabyte Address for 8-Burst
reg [NumBnks-1:0] ibnk_sel_s; // Muxed internal bank address subfield of
command address
always @(/*AUTOSENSE*/lio_buscfg_brstlen2_sr or lio_buscfg_brstlen4_sr or m_cdq_haddr_sr)
begin : PeelIntBnkAddr
case ({lio_buscfg_brstlen4_sr,lio_buscfg_brstlen2_sr})
2'b01: // 2-burst
begin
ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST2_RNG];
end
2'b10: // 4-burst
begin
ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST4_RNG];
end
default: // 8-burst
begin
ibnk_sel_s = m_cdq_haddr_sr[`DMC_AG_HADDR_BADDR_BST8_RNG];
end
endcase
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
|
//-----------------------------------------------------------------------------
// File : register_bank.v
// Creation date : 16.05.2017
// Creation time : 11:39:39
// Description : Stores registers and the logic needed to access them. In case of multiple simultaenous writes, the one with most priority is done.
// Created by : TermosPullo
// Tool : Kactus2 3.4.106 32-bit
// Plugin : Verilog generator 2.0e
// This file was generated based on IP-XACT component tut.fi:cpu.logic:register_bank:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/cpu.logic/register_bank/1.0/register_bank.1.0.xml
//-----------------------------------------------------------------------------
module register_bank #(
parameter DATA_WIDTH = 16, // Width for data in registers and instructions.
parameter REGISTER_ID_WIDTH = 4, // Bits reserved for identification a single register.
parameter REGISTER_COUNT = 8 // How many registers are supported in the core.
) (
// Interface: cpu_clk_sink
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i, // The mandatory reset, as this is synchronous logic.
// Interface: cpu_system
input alu_active_i,
input [DATA_WIDTH-1:0] alu_result_i,
input [REGISTER_ID_WIDTH-1:0] choose_register_i1,
input [REGISTER_ID_WIDTH-1:0] choose_register_i2,
input [DATA_WIDTH-1:0] load_value_i,
input mem_read_rdy_i,
input register_active_i,
input [DATA_WIDTH-1:0] register_input,
output reg [DATA_WIDTH-1:0] register_output1,
output reg [DATA_WIDTH-1:0] register_output2
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
// The registers.
reg [DATA_WIDTH-1:0] registers [REGISTER_COUNT-1:0];
// Iterator for the reset
integer index;
always @* begin
// Select new output when ever registers are activated.
register_output1 <= registers[choose_register_i1];
register_output2 <= registers[choose_register_i2];
end
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
for (index = 0; index < REGISTER_COUNT; index = index + 1) begin
registers[index] <= 0;
end
end
else begin
if (alu_active_i) begin
// Alu is expected to yield a value: Save to the register.
registers[choose_register_i1] <= alu_result_i;
end
else if (mem_read_rdy_i) begin
// Alu is expected to yield a value: Save to the register.
registers[choose_register_i1] <= load_value_i;
end
else if (register_active_i) begin
// Alu is expected to yield a value: Save to the register.
registers[choose_register_i1] <= register_input[DATA_WIDTH-1:0];
end
end
end
endmodule
|
//==================================================================================================
// Filename : antares_load_store_unit.v
// Created On : Sat Sep 5 10:38:09 2015
// Last Modified : Sat Nov 07 12:09:07 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Handle memory access; using a 4-way handshaking protocol:
// 1.- Assert enable signal.
// 2.- Ready goes high when data is available.
// 3.- If Ready is high; enable signal goes low.
// 4.- Next cycle; if enable is low, clear Ready signal.
//
// Time diagram:
//
// Clock Tick: | | | | | | | | | | |
// ______ ___
// Enable: __| |_______| |______
// __ __
// Ready: _____| |________| |____
//==================================================================================================
`include "antares_defines.v"
module antares_load_store_unit (
input clk, // Clock
input rst, // Reset
// Instruction interface: LSU <-> CPU
input [31:0] imem_address, // Instruction address
output reg [31:0] imem_data, // Instruction data
// MEM interface: LSU <-> CPU
input [31:0] dmem_address, // Data address
input [31:0] dmem_data_i, // Data to memory
input dmem_halfword, // halfword access
input dmem_byte, // byte access
input dmem_read, // read data memory
input dmem_write, // write data memory
input dmem_sign_extend, // read data (byte/half) with sign extended
output reg [31:0] dmem_data_o, // data from memory
// Instruction Port: LSU <-> MEM[instruction]
input [31:0] iport_data_i, // Data from memory
input iport_ready, // memory is ready
input iport_error, // Bus error
output [31:0] iport_address, // data address
output [3:0] iport_wr, // write = byte select, read = 0000,
output iport_enable, // enable operation
// Data Port : LSU <-> (MEM[data], I/O)
input [31:0] dport_data_i, // Data from memory
input dport_ready, // memory is ready
input dport_error, // Bus error
output [31:0] dport_address, // data address
output [31:0] dport_data_o, // data to memory
output reg [3:0] dport_wr, // write = byte select, read = 0000,
output dport_enable, // enable operation
// pipeline signals
input exception_ready,
input mem_kernel_mode, // For exception logic
input mem_llsc, // Atomic operation
input id_eret, // for llsc1
output exc_address_if, // panic
output exc_address_l_mem, // panic
output exc_address_s_mem, // panic
output imem_request_stall, // long operation
output dmem_request_stall // long operation
);
//--------------------------------------------------------------------------
// wire and registers
//--------------------------------------------------------------------------
wire exc_invalid_word_iaddress; // Not word-aligned instructions address
wire exc_invalid_space_iaddress; // try to access I/O space
wire exc_invalid_word_maddress; // Not word-aligned data address
wire exc_invalid_half_maddress; // Not halfword-aligned data address
wire exc_invalid_space_maddress; // try to access kernel space
wire dmem_operation; // Read or Write?
wire data_word; // LW/SW operation
wire exc_invalid_maddress;
wire write_enable;
wire read_enable;
reg [29:0] llsc_address;
reg llsc_atomic;
wire llsc_mem_write_mask;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
// Check for invalid access from instruction port.
assign exc_invalid_word_iaddress = imem_address[1] | imem_address[0];
assign exc_invalid_space_iaddress = 0; // TODO: check for invalid IM access.
// Check for invalid access from data port.
assign exc_invalid_word_maddress = (dmem_address[1] | dmem_address[0]) & data_word;
assign exc_invalid_half_maddress = dmem_address[0] & dmem_halfword;
assign exc_invalid_space_maddress = ~mem_kernel_mode & (dmem_address < `ANTARES_SEG_2_SPACE_LOW);
assign exc_invalid_maddress = exc_invalid_space_maddress | exc_invalid_word_maddress | exc_invalid_half_maddress;
// Exception signals.
assign exc_address_if = exc_invalid_word_iaddress | exc_invalid_space_iaddress;
assign exc_address_l_mem = dmem_read & exc_invalid_maddress;
assign exc_address_s_mem = dmem_write & exc_invalid_maddress;
assign write_enable = dmem_write & ~exc_invalid_maddress & ~llsc_mem_write_mask;
assign read_enable = dmem_read & ~exc_invalid_maddress;
assign dmem_operation = (write_enable ^ read_enable) | mem_llsc;
assign data_word = ~(dmem_halfword | dmem_byte);
assign imem_request_stall = iport_enable;
assign dmem_request_stall = dport_enable;
assign iport_enable = (~rst & ~iport_ready & ~exception_ready & ~iport_error);
assign dport_enable = ~dport_ready & dmem_operation & ~dport_error;
//--------------------------------------------------------------------------
// Load Linked and Store Conditional logic
//--------------------------------------------------------------------------
/*
From XUM project:
A 32-bit register keeps track of the address for atomic Load Linked / Store Conditional
operations. This register can be updated during stalls since it is not visible to
forward stages. It does not need to be flushed during exceptions, since ERET destroys
the atomicity condition and there are no detrimental effects in an exception handler.
The atomic condition is set with a Load Linked instruction, and cleared on an ERET
instruction or when any store instruction writes to one or more bytes covered by
the word address register. It does not update on a stall condition.
The MIPS32 spec states that an ERET instruction between LL and SC will cause the
atomicity condition to fail. This implementation uses the ERET signal from the ID
stage, which means instruction sequences such as "LL SC" could appear to have an
ERET instruction between them even though they don't. One way to fix this is to pass
the ERET signal through the pipeline to the MEM stage. However, because of the nature
of LL/SC operations (they occur in a loop which checks the result at each iteration),
an ERET will normally never be inserted into the pipeline programmatically until the
LL/SC sequence has completed (exceptions such as interrupts can still cause ERET, but
they can still cause them in the LL SC sequence as well). In other words, by not passing
ERET through the pipeline, the only possible effect is a performance penalty. Also this
may be irrelevant since currently ERET stalls for forward stages which can cause exceptions,
which includes LL and SC.
*/
always @(posedge clk) begin
llsc_address <= (rst) ? 30'b0 : ( (dmem_read & mem_llsc) ? dmem_address[31:2] : llsc_address );
end
always @(posedge clk) begin
if (rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
llsc_atomic <= 1'h0;
// End of automatics
end
else if (dmem_read) begin
llsc_atomic <= (mem_llsc) ? 1'b1 : llsc_atomic;
end
else if (id_eret | (~dmem_request_stall & dmem_write & (dmem_address[31:2] == llsc_address))) begin
llsc_atomic <= 1'b0;
end
else begin
llsc_atomic <= llsc_atomic;
end
end // always @ (posedge clk)
// If atomic and using the same address: enable the write. Else, ignore.
assign llsc_mem_write_mask = (mem_llsc & dmem_write & (~llsc_atomic | (dmem_address[31:2] != llsc_address)));
//--------------------------------------------------------------------------
// Map address and I/O ports
//--------------------------------------------------------------------------
assign iport_address = imem_address[31:0]; // full assign
assign dport_address = dmem_address[31:0]; // full assign
//--------------------------------------------------------------------------
// Read instruction memory
//--------------------------------------------------------------------------
assign iport_wr = 4'b0000; // DO NOT WRITE
always @(*) begin
imem_data = iport_data_i; // simple
end
//--------------------------------------------------------------------------
// Read from data data port.
//--------------------------------------------------------------------------
always @(*) begin
if (dmem_byte) begin
case (dmem_address[1:0])
2'b00 : dmem_data_o = (dmem_sign_extend) ? { {24{dport_data_i[7]} }, dport_data_i[7:0] } : {24'b0, dport_data_i[7:0]};
2'b01 : dmem_data_o = (dmem_sign_extend) ? { {24{dport_data_i[15]} }, dport_data_i[15:8] } : {24'b0, dport_data_i[15:8]};
2'b10 : dmem_data_o = (dmem_sign_extend) ? { {24{dport_data_i[23]} }, dport_data_i[23:16] } : {24'b0, dport_data_i[23:16]};
2'b11 : dmem_data_o = (dmem_sign_extend) ? { {24{dport_data_i[31]} }, dport_data_i[31:24] } : {24'b0, dport_data_i[31:24]};
default : dmem_data_o = 32'hx;
endcase // case (dmem_address[1:0])
end
else if (dmem_halfword) begin
case (dmem_address[1])
1'b0 : dmem_data_o = (dmem_sign_extend) ? { {16{dport_data_i[15]} }, dport_data_i[15:0] } : {16'b0, dport_data_i[15:0]};
1'b1 : dmem_data_o = (dmem_sign_extend) ? { {16{dport_data_i[31]} }, dport_data_i[31:16] } : {16'b0, dport_data_i[31:16]};
default : dmem_data_o = 32'hx;
endcase // case (dmem_address[1])
end
else if (mem_llsc & dmem_write) begin
dmem_data_o = (llsc_atomic & (dmem_address[31:2] == llsc_address)) ? 32'h0000_0001 : 32'h0000_0000;
end
else begin
dmem_data_o = dport_data_i;
end
end // always @ (*)
//--------------------------------------------------------------------------
// Write to data port
// Format data:
// byte : {b, b, b, b}
// half : {h, h}
// word : {w}
//
// Modify to implement Reverse Endian
//--------------------------------------------------------------------------
always @(*) begin
dport_wr = 4'b0000;
if (write_enable) begin
dport_wr[3] = (dmem_byte & (dmem_address[1:0] == 2'b11)) | (dmem_halfword & dmem_address[1]) | data_word;
dport_wr[2] = (dmem_byte & (dmem_address[1:0] == 2'b10)) | (dmem_halfword & dmem_address[1]) | data_word;
dport_wr[1] = (dmem_byte & (dmem_address[1:0] == 2'b01)) | (dmem_halfword & ~dmem_address[1]) | data_word;
dport_wr[0] = (dmem_byte & (dmem_address[1:0] == 2'b00)) | (dmem_halfword & ~dmem_address[1]) | data_word;
end
end
assign dport_data_o[31:24] = (dmem_byte) ? dmem_data_i[7:0] : ((dmem_halfword) ? dmem_data_i[15:8] : dmem_data_i[31:24]);
assign dport_data_o[23:16] = (dmem_byte | dmem_halfword) ? dmem_data_i[7:0] : dmem_data_i[23:16];
assign dport_data_o[15:8] = (dmem_byte) ? dmem_data_i[7:0]: dmem_data_i[15:8];
assign dport_data_o[7:0] = dmem_data_i[7:0];
endmodule // antares_load_store_unit
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_pio_led (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 9: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 9: 0] data_out;
wire [ 9: 0] out_port;
wire [ 9: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {10 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 682;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[9 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
// system_acl_iface.v
// Generated using ACDS version 14.0 200 at 2015.04.18.10:44:13
`timescale 1 ps / 1 ps
module system_acl_iface (
input wire config_clk_clk, // config_clk.clk
input wire reset_n, // global_reset.reset_n
input wire kernel_pll_refclk_clk, // kernel_pll_refclk.clk
output wire kernel_clk_clk, // kernel_clk.clk
output wire kernel_reset_reset_n, // kernel_reset.reset_n
output wire kernel_clk2x_clk, // kernel_clk2x.clk
output wire kernel_mem0_waitrequest, // kernel_mem0.waitrequest
output wire [255:0] kernel_mem0_readdata, // .readdata
output wire kernel_mem0_readdatavalid, // .readdatavalid
input wire [4:0] kernel_mem0_burstcount, // .burstcount
input wire [255:0] kernel_mem0_writedata, // .writedata
input wire [29:0] kernel_mem0_address, // .address
input wire kernel_mem0_write, // .write
input wire kernel_mem0_read, // .read
input wire [31:0] kernel_mem0_byteenable, // .byteenable
input wire kernel_mem0_debugaccess, // .debugaccess
output wire acl_kernel_clk_kernel_pll_locked_export, // acl_kernel_clk_kernel_pll_locked.export
output wire kernel_clk_snoop_clk, // kernel_clk_snoop.clk
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
output wire peripheral_hps_io_emac1_inst_TX_CLK, // peripheral.hps_io_emac1_inst_TX_CLK
output wire peripheral_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire peripheral_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire peripheral_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire peripheral_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire peripheral_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire peripheral_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire peripheral_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire peripheral_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire peripheral_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire peripheral_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire peripheral_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire peripheral_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire peripheral_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire peripheral_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire peripheral_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire peripheral_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire peripheral_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire peripheral_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire peripheral_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
input wire peripheral_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire peripheral_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire peripheral_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire peripheral_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire peripheral_hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
output wire [1:0] acl_internal_memorg_kernel_mode, // acl_internal_memorg_kernel.mode
input wire [0:0] kernel_irq_irq, // kernel_irq.irq
input wire kernel_cra_waitrequest, // kernel_cra.waitrequest
input wire [63:0] kernel_cra_readdata, // .readdata
input wire kernel_cra_readdatavalid, // .readdatavalid
output wire [0:0] kernel_cra_burstcount, // .burstcount
output wire [63:0] kernel_cra_writedata, // .writedata
output wire [29:0] kernel_cra_address, // .address
output wire kernel_cra_write, // .write
output wire kernel_cra_read, // .read
output wire [7:0] kernel_cra_byteenable, // .byteenable
output wire kernel_cra_debugaccess, // .debugaccess
output wire [1:0] kernel_interface_acl_bsp_memorg_host_mode // kernel_interface_acl_bsp_memorg_host.mode
);
wire pll_outclk0_clk; // pll:outclk_0 -> [address_span_extender_kernel:clk, clock_cross_kernel_mem1:m0_clk, hps:f2h_sdram0_clk, mm_interconnect_1:pll_outclk0_clk, mm_interconnect_2:pll_outclk0_clk, rst_controller_001:clk, rst_controller_003:clk]
wire hps_h2f_lw_axi_master_awvalid; // hps:h2f_lw_AWVALID -> mm_interconnect_0:hps_h2f_lw_axi_master_awvalid
wire [2:0] hps_h2f_lw_axi_master_arsize; // hps:h2f_lw_ARSIZE -> mm_interconnect_0:hps_h2f_lw_axi_master_arsize
wire [1:0] hps_h2f_lw_axi_master_arlock; // hps:h2f_lw_ARLOCK -> mm_interconnect_0:hps_h2f_lw_axi_master_arlock
wire [3:0] hps_h2f_lw_axi_master_awcache; // hps:h2f_lw_AWCACHE -> mm_interconnect_0:hps_h2f_lw_axi_master_awcache
wire hps_h2f_lw_axi_master_arready; // mm_interconnect_0:hps_h2f_lw_axi_master_arready -> hps:h2f_lw_ARREADY
wire [11:0] hps_h2f_lw_axi_master_arid; // hps:h2f_lw_ARID -> mm_interconnect_0:hps_h2f_lw_axi_master_arid
wire hps_h2f_lw_axi_master_rready; // hps:h2f_lw_RREADY -> mm_interconnect_0:hps_h2f_lw_axi_master_rready
wire hps_h2f_lw_axi_master_bready; // hps:h2f_lw_BREADY -> mm_interconnect_0:hps_h2f_lw_axi_master_bready
wire [2:0] hps_h2f_lw_axi_master_awsize; // hps:h2f_lw_AWSIZE -> mm_interconnect_0:hps_h2f_lw_axi_master_awsize
wire [2:0] hps_h2f_lw_axi_master_awprot; // hps:h2f_lw_AWPROT -> mm_interconnect_0:hps_h2f_lw_axi_master_awprot
wire hps_h2f_lw_axi_master_arvalid; // hps:h2f_lw_ARVALID -> mm_interconnect_0:hps_h2f_lw_axi_master_arvalid
wire [2:0] hps_h2f_lw_axi_master_arprot; // hps:h2f_lw_ARPROT -> mm_interconnect_0:hps_h2f_lw_axi_master_arprot
wire [11:0] hps_h2f_lw_axi_master_bid; // mm_interconnect_0:hps_h2f_lw_axi_master_bid -> hps:h2f_lw_BID
wire [3:0] hps_h2f_lw_axi_master_arlen; // hps:h2f_lw_ARLEN -> mm_interconnect_0:hps_h2f_lw_axi_master_arlen
wire hps_h2f_lw_axi_master_awready; // mm_interconnect_0:hps_h2f_lw_axi_master_awready -> hps:h2f_lw_AWREADY
wire [11:0] hps_h2f_lw_axi_master_awid; // hps:h2f_lw_AWID -> mm_interconnect_0:hps_h2f_lw_axi_master_awid
wire hps_h2f_lw_axi_master_bvalid; // mm_interconnect_0:hps_h2f_lw_axi_master_bvalid -> hps:h2f_lw_BVALID
wire [11:0] hps_h2f_lw_axi_master_wid; // hps:h2f_lw_WID -> mm_interconnect_0:hps_h2f_lw_axi_master_wid
wire [1:0] hps_h2f_lw_axi_master_awlock; // hps:h2f_lw_AWLOCK -> mm_interconnect_0:hps_h2f_lw_axi_master_awlock
wire [1:0] hps_h2f_lw_axi_master_awburst; // hps:h2f_lw_AWBURST -> mm_interconnect_0:hps_h2f_lw_axi_master_awburst
wire [1:0] hps_h2f_lw_axi_master_bresp; // mm_interconnect_0:hps_h2f_lw_axi_master_bresp -> hps:h2f_lw_BRESP
wire [3:0] hps_h2f_lw_axi_master_wstrb; // hps:h2f_lw_WSTRB -> mm_interconnect_0:hps_h2f_lw_axi_master_wstrb
wire hps_h2f_lw_axi_master_rvalid; // mm_interconnect_0:hps_h2f_lw_axi_master_rvalid -> hps:h2f_lw_RVALID
wire [31:0] hps_h2f_lw_axi_master_wdata; // hps:h2f_lw_WDATA -> mm_interconnect_0:hps_h2f_lw_axi_master_wdata
wire hps_h2f_lw_axi_master_wready; // mm_interconnect_0:hps_h2f_lw_axi_master_wready -> hps:h2f_lw_WREADY
wire [1:0] hps_h2f_lw_axi_master_arburst; // hps:h2f_lw_ARBURST -> mm_interconnect_0:hps_h2f_lw_axi_master_arburst
wire [31:0] hps_h2f_lw_axi_master_rdata; // mm_interconnect_0:hps_h2f_lw_axi_master_rdata -> hps:h2f_lw_RDATA
wire [20:0] hps_h2f_lw_axi_master_araddr; // hps:h2f_lw_ARADDR -> mm_interconnect_0:hps_h2f_lw_axi_master_araddr
wire [3:0] hps_h2f_lw_axi_master_arcache; // hps:h2f_lw_ARCACHE -> mm_interconnect_0:hps_h2f_lw_axi_master_arcache
wire [3:0] hps_h2f_lw_axi_master_awlen; // hps:h2f_lw_AWLEN -> mm_interconnect_0:hps_h2f_lw_axi_master_awlen
wire [20:0] hps_h2f_lw_axi_master_awaddr; // hps:h2f_lw_AWADDR -> mm_interconnect_0:hps_h2f_lw_axi_master_awaddr
wire [11:0] hps_h2f_lw_axi_master_rid; // mm_interconnect_0:hps_h2f_lw_axi_master_rid -> hps:h2f_lw_RID
wire hps_h2f_lw_axi_master_wvalid; // hps:h2f_lw_WVALID -> mm_interconnect_0:hps_h2f_lw_axi_master_wvalid
wire [1:0] hps_h2f_lw_axi_master_rresp; // mm_interconnect_0:hps_h2f_lw_axi_master_rresp -> hps:h2f_lw_RRESP
wire hps_h2f_lw_axi_master_wlast; // hps:h2f_lw_WLAST -> mm_interconnect_0:hps_h2f_lw_axi_master_wlast
wire hps_h2f_lw_axi_master_rlast; // mm_interconnect_0:hps_h2f_lw_axi_master_rlast -> hps:h2f_lw_RLAST
wire mm_interconnect_0_version_id_s_read; // mm_interconnect_0:version_id_s_read -> version_id:slave_read
wire [31:0] mm_interconnect_0_version_id_s_readdata; // version_id:slave_readdata -> mm_interconnect_0:version_id_s_readdata
wire mm_interconnect_0_acl_kernel_interface_kernel_cntrl_waitrequest; // acl_kernel_interface:kernel_cntrl_waitrequest -> mm_interconnect_0:acl_kernel_interface_kernel_cntrl_waitrequest
wire [0:0] mm_interconnect_0_acl_kernel_interface_kernel_cntrl_burstcount; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_burstcount -> acl_kernel_interface:kernel_cntrl_burstcount
wire [31:0] mm_interconnect_0_acl_kernel_interface_kernel_cntrl_writedata; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_writedata -> acl_kernel_interface:kernel_cntrl_writedata
wire [13:0] mm_interconnect_0_acl_kernel_interface_kernel_cntrl_address; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_address -> acl_kernel_interface:kernel_cntrl_address
wire mm_interconnect_0_acl_kernel_interface_kernel_cntrl_write; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_write -> acl_kernel_interface:kernel_cntrl_write
wire mm_interconnect_0_acl_kernel_interface_kernel_cntrl_read; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_read -> acl_kernel_interface:kernel_cntrl_read
wire [31:0] mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdata; // acl_kernel_interface:kernel_cntrl_readdata -> mm_interconnect_0:acl_kernel_interface_kernel_cntrl_readdata
wire mm_interconnect_0_acl_kernel_interface_kernel_cntrl_debugaccess; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_debugaccess -> acl_kernel_interface:kernel_cntrl_debugaccess
wire mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdatavalid; // acl_kernel_interface:kernel_cntrl_readdatavalid -> mm_interconnect_0:acl_kernel_interface_kernel_cntrl_readdatavalid
wire [3:0] mm_interconnect_0_acl_kernel_interface_kernel_cntrl_byteenable; // mm_interconnect_0:acl_kernel_interface_kernel_cntrl_byteenable -> acl_kernel_interface:kernel_cntrl_byteenable
wire mm_interconnect_0_acl_kernel_clk_ctrl_waitrequest; // acl_kernel_clk:ctrl_waitrequest -> mm_interconnect_0:acl_kernel_clk_ctrl_waitrequest
wire [0:0] mm_interconnect_0_acl_kernel_clk_ctrl_burstcount; // mm_interconnect_0:acl_kernel_clk_ctrl_burstcount -> acl_kernel_clk:ctrl_burstcount
wire [31:0] mm_interconnect_0_acl_kernel_clk_ctrl_writedata; // mm_interconnect_0:acl_kernel_clk_ctrl_writedata -> acl_kernel_clk:ctrl_writedata
wire [10:0] mm_interconnect_0_acl_kernel_clk_ctrl_address; // mm_interconnect_0:acl_kernel_clk_ctrl_address -> acl_kernel_clk:ctrl_address
wire mm_interconnect_0_acl_kernel_clk_ctrl_write; // mm_interconnect_0:acl_kernel_clk_ctrl_write -> acl_kernel_clk:ctrl_write
wire mm_interconnect_0_acl_kernel_clk_ctrl_read; // mm_interconnect_0:acl_kernel_clk_ctrl_read -> acl_kernel_clk:ctrl_read
wire [31:0] mm_interconnect_0_acl_kernel_clk_ctrl_readdata; // acl_kernel_clk:ctrl_readdata -> mm_interconnect_0:acl_kernel_clk_ctrl_readdata
wire mm_interconnect_0_acl_kernel_clk_ctrl_debugaccess; // mm_interconnect_0:acl_kernel_clk_ctrl_debugaccess -> acl_kernel_clk:ctrl_debugaccess
wire mm_interconnect_0_acl_kernel_clk_ctrl_readdatavalid; // acl_kernel_clk:ctrl_readdatavalid -> mm_interconnect_0:acl_kernel_clk_ctrl_readdatavalid
wire [3:0] mm_interconnect_0_acl_kernel_clk_ctrl_byteenable; // mm_interconnect_0:acl_kernel_clk_ctrl_byteenable -> acl_kernel_clk:ctrl_byteenable
wire [4:0] clock_cross_kernel_mem1_m0_burstcount; // clock_cross_kernel_mem1:m0_burstcount -> mm_interconnect_1:clock_cross_kernel_mem1_m0_burstcount
wire clock_cross_kernel_mem1_m0_waitrequest; // mm_interconnect_1:clock_cross_kernel_mem1_m0_waitrequest -> clock_cross_kernel_mem1:m0_waitrequest
wire [29:0] clock_cross_kernel_mem1_m0_address; // clock_cross_kernel_mem1:m0_address -> mm_interconnect_1:clock_cross_kernel_mem1_m0_address
wire [255:0] clock_cross_kernel_mem1_m0_writedata; // clock_cross_kernel_mem1:m0_writedata -> mm_interconnect_1:clock_cross_kernel_mem1_m0_writedata
wire clock_cross_kernel_mem1_m0_write; // clock_cross_kernel_mem1:m0_write -> mm_interconnect_1:clock_cross_kernel_mem1_m0_write
wire clock_cross_kernel_mem1_m0_read; // clock_cross_kernel_mem1:m0_read -> mm_interconnect_1:clock_cross_kernel_mem1_m0_read
wire [255:0] clock_cross_kernel_mem1_m0_readdata; // mm_interconnect_1:clock_cross_kernel_mem1_m0_readdata -> clock_cross_kernel_mem1:m0_readdata
wire clock_cross_kernel_mem1_m0_debugaccess; // clock_cross_kernel_mem1:m0_debugaccess -> mm_interconnect_1:clock_cross_kernel_mem1_m0_debugaccess
wire [31:0] clock_cross_kernel_mem1_m0_byteenable; // clock_cross_kernel_mem1:m0_byteenable -> mm_interconnect_1:clock_cross_kernel_mem1_m0_byteenable
wire clock_cross_kernel_mem1_m0_readdatavalid; // mm_interconnect_1:clock_cross_kernel_mem1_m0_readdatavalid -> clock_cross_kernel_mem1:m0_readdatavalid
wire mm_interconnect_1_address_span_extender_kernel_windowed_slave_waitrequest; // address_span_extender_kernel:avs_s0_waitrequest -> mm_interconnect_1:address_span_extender_kernel_windowed_slave_waitrequest
wire [4:0] mm_interconnect_1_address_span_extender_kernel_windowed_slave_burstcount; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_burstcount -> address_span_extender_kernel:avs_s0_burstcount
wire [255:0] mm_interconnect_1_address_span_extender_kernel_windowed_slave_writedata; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_writedata -> address_span_extender_kernel:avs_s0_writedata
wire [24:0] mm_interconnect_1_address_span_extender_kernel_windowed_slave_address; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_address -> address_span_extender_kernel:avs_s0_address
wire mm_interconnect_1_address_span_extender_kernel_windowed_slave_write; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_write -> address_span_extender_kernel:avs_s0_write
wire mm_interconnect_1_address_span_extender_kernel_windowed_slave_read; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_read -> address_span_extender_kernel:avs_s0_read
wire [255:0] mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdata; // address_span_extender_kernel:avs_s0_readdata -> mm_interconnect_1:address_span_extender_kernel_windowed_slave_readdata
wire mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdatavalid; // address_span_extender_kernel:avs_s0_readdatavalid -> mm_interconnect_1:address_span_extender_kernel_windowed_slave_readdatavalid
wire [31:0] mm_interconnect_1_address_span_extender_kernel_windowed_slave_byteenable; // mm_interconnect_1:address_span_extender_kernel_windowed_slave_byteenable -> address_span_extender_kernel:avs_s0_byteenable
wire [4:0] address_span_extender_kernel_expanded_master_burstcount; // address_span_extender_kernel:avm_m0_burstcount -> mm_interconnect_2:address_span_extender_kernel_expanded_master_burstcount
wire address_span_extender_kernel_expanded_master_waitrequest; // mm_interconnect_2:address_span_extender_kernel_expanded_master_waitrequest -> address_span_extender_kernel:avm_m0_waitrequest
wire [255:0] address_span_extender_kernel_expanded_master_writedata; // address_span_extender_kernel:avm_m0_writedata -> mm_interconnect_2:address_span_extender_kernel_expanded_master_writedata
wire [31:0] address_span_extender_kernel_expanded_master_address; // address_span_extender_kernel:avm_m0_address -> mm_interconnect_2:address_span_extender_kernel_expanded_master_address
wire address_span_extender_kernel_expanded_master_write; // address_span_extender_kernel:avm_m0_write -> mm_interconnect_2:address_span_extender_kernel_expanded_master_write
wire address_span_extender_kernel_expanded_master_read; // address_span_extender_kernel:avm_m0_read -> mm_interconnect_2:address_span_extender_kernel_expanded_master_read
wire [255:0] address_span_extender_kernel_expanded_master_readdata; // mm_interconnect_2:address_span_extender_kernel_expanded_master_readdata -> address_span_extender_kernel:avm_m0_readdata
wire [31:0] address_span_extender_kernel_expanded_master_byteenable; // address_span_extender_kernel:avm_m0_byteenable -> mm_interconnect_2:address_span_extender_kernel_expanded_master_byteenable
wire address_span_extender_kernel_expanded_master_readdatavalid; // mm_interconnect_2:address_span_extender_kernel_expanded_master_readdatavalid -> address_span_extender_kernel:avm_m0_readdatavalid
wire mm_interconnect_2_hps_f2h_sdram0_data_waitrequest; // hps:f2h_sdram0_WAITREQUEST -> mm_interconnect_2:hps_f2h_sdram0_data_waitrequest
wire [7:0] mm_interconnect_2_hps_f2h_sdram0_data_burstcount; // mm_interconnect_2:hps_f2h_sdram0_data_burstcount -> hps:f2h_sdram0_BURSTCOUNT
wire [255:0] mm_interconnect_2_hps_f2h_sdram0_data_writedata; // mm_interconnect_2:hps_f2h_sdram0_data_writedata -> hps:f2h_sdram0_WRITEDATA
wire [26:0] mm_interconnect_2_hps_f2h_sdram0_data_address; // mm_interconnect_2:hps_f2h_sdram0_data_address -> hps:f2h_sdram0_ADDRESS
wire mm_interconnect_2_hps_f2h_sdram0_data_write; // mm_interconnect_2:hps_f2h_sdram0_data_write -> hps:f2h_sdram0_WRITE
wire mm_interconnect_2_hps_f2h_sdram0_data_read; // mm_interconnect_2:hps_f2h_sdram0_data_read -> hps:f2h_sdram0_READ
wire [255:0] mm_interconnect_2_hps_f2h_sdram0_data_readdata; // hps:f2h_sdram0_READDATA -> mm_interconnect_2:hps_f2h_sdram0_data_readdata
wire mm_interconnect_2_hps_f2h_sdram0_data_readdatavalid; // hps:f2h_sdram0_READDATAVALID -> mm_interconnect_2:hps_f2h_sdram0_data_readdatavalid
wire [31:0] mm_interconnect_2_hps_f2h_sdram0_data_byteenable; // mm_interconnect_2:hps_f2h_sdram0_data_byteenable -> hps:f2h_sdram0_BYTEENABLE
wire irq_mapper_receiver0_irq; // acl_kernel_interface:kernel_irq_to_host_irq -> irq_mapper:receiver0_irq
wire [31:0] hps_f2h_irq0_irq; // irq_mapper:sender_irq -> hps:f2h_irq_p0
wire [31:0] hps_f2h_irq1_irq; // irq_mapper_001:sender_irq -> hps:f2h_irq_p1
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [acl_kernel_clk:reset_reset_n, acl_kernel_interface:reset_reset_n, acl_kernel_interface:sw_reset_in_reset, mm_interconnect_0:version_id_clk_reset_reset_bridge_in_reset_reset, pll:rst, version_id:resetn]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [address_span_extender_kernel:reset, clock_cross_kernel_mem1:m0_reset, mm_interconnect_1:clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset_reset, mm_interconnect_2:address_span_extender_kernel_reset_reset_bridge_in_reset_reset]
wire acl_kernel_interface_sw_reset_export_reset; // acl_kernel_interface:sw_reset_export_reset_n -> rst_controller_001:reset_in0
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> mm_interconnect_0:hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset
wire hps_h2f_reset_reset; // hps:h2f_rst_n -> [rst_controller_002:reset_in0, rst_controller_003:reset_in0]
wire rst_controller_003_reset_out_reset; // rst_controller_003:reset_out -> mm_interconnect_2:hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset
system_acl_iface_acl_kernel_clk acl_kernel_clk (
.kernel_clk2x_clk (kernel_clk2x_clk), // kernel_clk2x.clk
.pll_refclk_clk (kernel_pll_refclk_clk), // pll_refclk.clk
.ctrl_waitrequest (mm_interconnect_0_acl_kernel_clk_ctrl_waitrequest), // ctrl.waitrequest
.ctrl_readdata (mm_interconnect_0_acl_kernel_clk_ctrl_readdata), // .readdata
.ctrl_readdatavalid (mm_interconnect_0_acl_kernel_clk_ctrl_readdatavalid), // .readdatavalid
.ctrl_burstcount (mm_interconnect_0_acl_kernel_clk_ctrl_burstcount), // .burstcount
.ctrl_writedata (mm_interconnect_0_acl_kernel_clk_ctrl_writedata), // .writedata
.ctrl_address (mm_interconnect_0_acl_kernel_clk_ctrl_address), // .address
.ctrl_write (mm_interconnect_0_acl_kernel_clk_ctrl_write), // .write
.ctrl_read (mm_interconnect_0_acl_kernel_clk_ctrl_read), // .read
.ctrl_byteenable (mm_interconnect_0_acl_kernel_clk_ctrl_byteenable), // .byteenable
.ctrl_debugaccess (mm_interconnect_0_acl_kernel_clk_ctrl_debugaccess), // .debugaccess
.kernel_clk_clk (kernel_clk_clk), // kernel_clk.clk
.kernel_pll_locked_export (acl_kernel_clk_kernel_pll_locked_export), // kernel_pll_locked.export
.clk_clk (config_clk_clk), // clk.clk
.reset_reset_n (~rst_controller_reset_out_reset) // reset.reset_n
);
altera_avalon_mm_clock_crossing_bridge #(
.DATA_WIDTH (256),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (30),
.BURSTCOUNT_WIDTH (5),
.COMMAND_FIFO_DEPTH (64),
.RESPONSE_FIFO_DEPTH (64),
.MASTER_SYNC_DEPTH (2),
.SLAVE_SYNC_DEPTH (2)
) clock_cross_kernel_mem1 (
.m0_clk (pll_outclk0_clk), // m0_clk.clk
.m0_reset (rst_controller_001_reset_out_reset), // m0_reset.reset
.s0_clk (kernel_clk_clk), // s0_clk.clk
.s0_reset (~kernel_reset_reset_n), // s0_reset.reset
.s0_waitrequest (kernel_mem0_waitrequest), // s0.waitrequest
.s0_readdata (kernel_mem0_readdata), // .readdata
.s0_readdatavalid (kernel_mem0_readdatavalid), // .readdatavalid
.s0_burstcount (kernel_mem0_burstcount), // .burstcount
.s0_writedata (kernel_mem0_writedata), // .writedata
.s0_address (kernel_mem0_address), // .address
.s0_write (kernel_mem0_write), // .write
.s0_read (kernel_mem0_read), // .read
.s0_byteenable (kernel_mem0_byteenable), // .byteenable
.s0_debugaccess (kernel_mem0_debugaccess), // .debugaccess
.m0_waitrequest (clock_cross_kernel_mem1_m0_waitrequest), // m0.waitrequest
.m0_readdata (clock_cross_kernel_mem1_m0_readdata), // .readdata
.m0_readdatavalid (clock_cross_kernel_mem1_m0_readdatavalid), // .readdatavalid
.m0_burstcount (clock_cross_kernel_mem1_m0_burstcount), // .burstcount
.m0_writedata (clock_cross_kernel_mem1_m0_writedata), // .writedata
.m0_address (clock_cross_kernel_mem1_m0_address), // .address
.m0_write (clock_cross_kernel_mem1_m0_write), // .write
.m0_read (clock_cross_kernel_mem1_m0_read), // .read
.m0_byteenable (clock_cross_kernel_mem1_m0_byteenable), // .byteenable
.m0_debugaccess (clock_cross_kernel_mem1_m0_debugaccess) // .debugaccess
);
version_id #(
.WIDTH (32),
.VERSION_ID (-1597521440)
) version_id (
.clk (config_clk_clk), // clk.clk
.resetn (~rst_controller_reset_out_reset), // clk_reset.reset_n
.slave_read (mm_interconnect_0_version_id_s_read), // s.read
.slave_readdata (mm_interconnect_0_version_id_s_readdata) // .readdata
);
system_acl_iface_hps #(
.F2S_Width (0),
.S2F_Width (0)
) hps (
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (peripheral_hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (peripheral_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (peripheral_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (peripheral_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (peripheral_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (peripheral_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (peripheral_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (peripheral_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (peripheral_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (peripheral_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (peripheral_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (peripheral_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (peripheral_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (peripheral_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (peripheral_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (peripheral_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (peripheral_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (peripheral_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (peripheral_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (peripheral_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_uart0_inst_RX (peripheral_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (peripheral_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c1_inst_SDA (peripheral_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (peripheral_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO53 (peripheral_hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n
.f2h_sdram0_clk (pll_outclk0_clk), // f2h_sdram0_clock.clk
.f2h_sdram0_ADDRESS (mm_interconnect_2_hps_f2h_sdram0_data_address), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (mm_interconnect_2_hps_f2h_sdram0_data_burstcount), // .burstcount
.f2h_sdram0_WAITREQUEST (mm_interconnect_2_hps_f2h_sdram0_data_waitrequest), // .waitrequest
.f2h_sdram0_READDATA (mm_interconnect_2_hps_f2h_sdram0_data_readdata), // .readdata
.f2h_sdram0_READDATAVALID (mm_interconnect_2_hps_f2h_sdram0_data_readdatavalid), // .readdatavalid
.f2h_sdram0_READ (mm_interconnect_2_hps_f2h_sdram0_data_read), // .read
.f2h_sdram0_WRITEDATA (mm_interconnect_2_hps_f2h_sdram0_data_writedata), // .writedata
.f2h_sdram0_BYTEENABLE (mm_interconnect_2_hps_f2h_sdram0_data_byteenable), // .byteenable
.f2h_sdram0_WRITE (mm_interconnect_2_hps_f2h_sdram0_data_write), // .write
.h2f_lw_axi_clk (config_clk_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (hps_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (hps_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (hps_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (hps_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (hps_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (hps_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (hps_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (hps_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (hps_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (hps_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (hps_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (hps_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (hps_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (hps_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (hps_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (hps_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (hps_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (hps_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (hps_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (hps_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (hps_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (hps_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (hps_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (hps_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (hps_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (hps_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (hps_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (hps_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (hps_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (hps_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (hps_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (hps_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (hps_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (hps_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (hps_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (hps_h2f_lw_axi_master_rready), // .rready
.f2h_irq_p0 (hps_f2h_irq0_irq), // f2h_irq0.irq
.f2h_irq_p1 (hps_f2h_irq1_irq) // f2h_irq1.irq
);
system_acl_iface_acl_kernel_interface acl_kernel_interface (
.clk_clk (config_clk_clk), // clk.clk
.reset_reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.kernel_cntrl_waitrequest (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_waitrequest), // kernel_cntrl.waitrequest
.kernel_cntrl_readdata (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdata), // .readdata
.kernel_cntrl_readdatavalid (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdatavalid), // .readdatavalid
.kernel_cntrl_burstcount (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_burstcount), // .burstcount
.kernel_cntrl_writedata (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_writedata), // .writedata
.kernel_cntrl_address (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_address), // .address
.kernel_cntrl_write (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_write), // .write
.kernel_cntrl_read (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_read), // .read
.kernel_cntrl_byteenable (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_byteenable), // .byteenable
.kernel_cntrl_debugaccess (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_debugaccess), // .debugaccess
.kernel_cra_waitrequest (kernel_cra_waitrequest), // kernel_cra.waitrequest
.kernel_cra_readdata (kernel_cra_readdata), // .readdata
.kernel_cra_readdatavalid (kernel_cra_readdatavalid), // .readdatavalid
.kernel_cra_burstcount (kernel_cra_burstcount), // .burstcount
.kernel_cra_writedata (kernel_cra_writedata), // .writedata
.kernel_cra_address (kernel_cra_address), // .address
.kernel_cra_write (kernel_cra_write), // .write
.kernel_cra_read (kernel_cra_read), // .read
.kernel_cra_byteenable (kernel_cra_byteenable), // .byteenable
.kernel_cra_debugaccess (kernel_cra_debugaccess), // .debugaccess
.kernel_irq_from_kernel_irq (kernel_irq_irq), // kernel_irq_from_kernel.irq
.acl_bsp_memorg_kernel_mode (acl_internal_memorg_kernel_mode), // acl_bsp_memorg_kernel.mode
.acl_bsp_memorg_host_mode (kernel_interface_acl_bsp_memorg_host_mode), // acl_bsp_memorg_host.mode
.sw_reset_in_reset (rst_controller_reset_out_reset), // sw_reset_in.reset
.kernel_clk_clk (kernel_clk_clk), // kernel_clk.clk
.sw_reset_export_reset_n (acl_kernel_interface_sw_reset_export_reset), // sw_reset_export.reset_n
.kernel_reset_reset_n (kernel_reset_reset_n), // kernel_reset.reset_n
.kernel_irq_to_host_irq (irq_mapper_receiver0_irq) // kernel_irq_to_host.irq
);
system_acl_iface_pll pll (
.refclk (config_clk_clk), // refclk.clk
.rst (rst_controller_reset_out_reset), // reset.reset
.outclk_0 (pll_outclk0_clk), // outclk0.clk
.locked () // (terminated)
);
altera_address_span_extender #(
.DATA_WIDTH (256),
.BYTEENABLE_WIDTH (32),
.MASTER_ADDRESS_WIDTH (32),
.SLAVE_ADDRESS_WIDTH (25),
.SLAVE_ADDRESS_SHIFT (5),
.BURSTCOUNT_WIDTH (5),
.CNTL_ADDRESS_WIDTH (1),
.SUB_WINDOW_COUNT (1),
.MASTER_ADDRESS_DEF (64'b0000000000000000000000000000000000000000000000000000000000000000)
) address_span_extender_kernel (
.clk (pll_outclk0_clk), // clock.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.avs_s0_address (mm_interconnect_1_address_span_extender_kernel_windowed_slave_address), // windowed_slave.address
.avs_s0_read (mm_interconnect_1_address_span_extender_kernel_windowed_slave_read), // .read
.avs_s0_readdata (mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdata), // .readdata
.avs_s0_write (mm_interconnect_1_address_span_extender_kernel_windowed_slave_write), // .write
.avs_s0_writedata (mm_interconnect_1_address_span_extender_kernel_windowed_slave_writedata), // .writedata
.avs_s0_readdatavalid (mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdatavalid), // .readdatavalid
.avs_s0_waitrequest (mm_interconnect_1_address_span_extender_kernel_windowed_slave_waitrequest), // .waitrequest
.avs_s0_byteenable (mm_interconnect_1_address_span_extender_kernel_windowed_slave_byteenable), // .byteenable
.avs_s0_burstcount (mm_interconnect_1_address_span_extender_kernel_windowed_slave_burstcount), // .burstcount
.avm_m0_address (address_span_extender_kernel_expanded_master_address), // expanded_master.address
.avm_m0_read (address_span_extender_kernel_expanded_master_read), // .read
.avm_m0_waitrequest (address_span_extender_kernel_expanded_master_waitrequest), // .waitrequest
.avm_m0_readdata (address_span_extender_kernel_expanded_master_readdata), // .readdata
.avm_m0_write (address_span_extender_kernel_expanded_master_write), // .write
.avm_m0_writedata (address_span_extender_kernel_expanded_master_writedata), // .writedata
.avm_m0_readdatavalid (address_span_extender_kernel_expanded_master_readdatavalid), // .readdatavalid
.avm_m0_byteenable (address_span_extender_kernel_expanded_master_byteenable), // .byteenable
.avm_m0_burstcount (address_span_extender_kernel_expanded_master_burstcount), // .burstcount
.avs_cntl_address (1'b0), // (terminated)
.avs_cntl_read (1'b0), // (terminated)
.avs_cntl_readdata (), // (terminated)
.avs_cntl_write (1'b0), // (terminated)
.avs_cntl_writedata (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.avs_cntl_byteenable (8'b00000000) // (terminated)
);
system_acl_iface_mm_interconnect_0 mm_interconnect_0 (
.hps_h2f_lw_axi_master_awid (hps_h2f_lw_axi_master_awid), // hps_h2f_lw_axi_master.awid
.hps_h2f_lw_axi_master_awaddr (hps_h2f_lw_axi_master_awaddr), // .awaddr
.hps_h2f_lw_axi_master_awlen (hps_h2f_lw_axi_master_awlen), // .awlen
.hps_h2f_lw_axi_master_awsize (hps_h2f_lw_axi_master_awsize), // .awsize
.hps_h2f_lw_axi_master_awburst (hps_h2f_lw_axi_master_awburst), // .awburst
.hps_h2f_lw_axi_master_awlock (hps_h2f_lw_axi_master_awlock), // .awlock
.hps_h2f_lw_axi_master_awcache (hps_h2f_lw_axi_master_awcache), // .awcache
.hps_h2f_lw_axi_master_awprot (hps_h2f_lw_axi_master_awprot), // .awprot
.hps_h2f_lw_axi_master_awvalid (hps_h2f_lw_axi_master_awvalid), // .awvalid
.hps_h2f_lw_axi_master_awready (hps_h2f_lw_axi_master_awready), // .awready
.hps_h2f_lw_axi_master_wid (hps_h2f_lw_axi_master_wid), // .wid
.hps_h2f_lw_axi_master_wdata (hps_h2f_lw_axi_master_wdata), // .wdata
.hps_h2f_lw_axi_master_wstrb (hps_h2f_lw_axi_master_wstrb), // .wstrb
.hps_h2f_lw_axi_master_wlast (hps_h2f_lw_axi_master_wlast), // .wlast
.hps_h2f_lw_axi_master_wvalid (hps_h2f_lw_axi_master_wvalid), // .wvalid
.hps_h2f_lw_axi_master_wready (hps_h2f_lw_axi_master_wready), // .wready
.hps_h2f_lw_axi_master_bid (hps_h2f_lw_axi_master_bid), // .bid
.hps_h2f_lw_axi_master_bresp (hps_h2f_lw_axi_master_bresp), // .bresp
.hps_h2f_lw_axi_master_bvalid (hps_h2f_lw_axi_master_bvalid), // .bvalid
.hps_h2f_lw_axi_master_bready (hps_h2f_lw_axi_master_bready), // .bready
.hps_h2f_lw_axi_master_arid (hps_h2f_lw_axi_master_arid), // .arid
.hps_h2f_lw_axi_master_araddr (hps_h2f_lw_axi_master_araddr), // .araddr
.hps_h2f_lw_axi_master_arlen (hps_h2f_lw_axi_master_arlen), // .arlen
.hps_h2f_lw_axi_master_arsize (hps_h2f_lw_axi_master_arsize), // .arsize
.hps_h2f_lw_axi_master_arburst (hps_h2f_lw_axi_master_arburst), // .arburst
.hps_h2f_lw_axi_master_arlock (hps_h2f_lw_axi_master_arlock), // .arlock
.hps_h2f_lw_axi_master_arcache (hps_h2f_lw_axi_master_arcache), // .arcache
.hps_h2f_lw_axi_master_arprot (hps_h2f_lw_axi_master_arprot), // .arprot
.hps_h2f_lw_axi_master_arvalid (hps_h2f_lw_axi_master_arvalid), // .arvalid
.hps_h2f_lw_axi_master_arready (hps_h2f_lw_axi_master_arready), // .arready
.hps_h2f_lw_axi_master_rid (hps_h2f_lw_axi_master_rid), // .rid
.hps_h2f_lw_axi_master_rdata (hps_h2f_lw_axi_master_rdata), // .rdata
.hps_h2f_lw_axi_master_rresp (hps_h2f_lw_axi_master_rresp), // .rresp
.hps_h2f_lw_axi_master_rlast (hps_h2f_lw_axi_master_rlast), // .rlast
.hps_h2f_lw_axi_master_rvalid (hps_h2f_lw_axi_master_rvalid), // .rvalid
.hps_h2f_lw_axi_master_rready (hps_h2f_lw_axi_master_rready), // .rready
.config_clk_out_clk_clk (config_clk_clk), // config_clk_out_clk.clk
.hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.version_id_clk_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // version_id_clk_reset_reset_bridge_in_reset.reset
.acl_kernel_clk_ctrl_address (mm_interconnect_0_acl_kernel_clk_ctrl_address), // acl_kernel_clk_ctrl.address
.acl_kernel_clk_ctrl_write (mm_interconnect_0_acl_kernel_clk_ctrl_write), // .write
.acl_kernel_clk_ctrl_read (mm_interconnect_0_acl_kernel_clk_ctrl_read), // .read
.acl_kernel_clk_ctrl_readdata (mm_interconnect_0_acl_kernel_clk_ctrl_readdata), // .readdata
.acl_kernel_clk_ctrl_writedata (mm_interconnect_0_acl_kernel_clk_ctrl_writedata), // .writedata
.acl_kernel_clk_ctrl_burstcount (mm_interconnect_0_acl_kernel_clk_ctrl_burstcount), // .burstcount
.acl_kernel_clk_ctrl_byteenable (mm_interconnect_0_acl_kernel_clk_ctrl_byteenable), // .byteenable
.acl_kernel_clk_ctrl_readdatavalid (mm_interconnect_0_acl_kernel_clk_ctrl_readdatavalid), // .readdatavalid
.acl_kernel_clk_ctrl_waitrequest (mm_interconnect_0_acl_kernel_clk_ctrl_waitrequest), // .waitrequest
.acl_kernel_clk_ctrl_debugaccess (mm_interconnect_0_acl_kernel_clk_ctrl_debugaccess), // .debugaccess
.acl_kernel_interface_kernel_cntrl_address (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_address), // acl_kernel_interface_kernel_cntrl.address
.acl_kernel_interface_kernel_cntrl_write (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_write), // .write
.acl_kernel_interface_kernel_cntrl_read (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_read), // .read
.acl_kernel_interface_kernel_cntrl_readdata (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdata), // .readdata
.acl_kernel_interface_kernel_cntrl_writedata (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_writedata), // .writedata
.acl_kernel_interface_kernel_cntrl_burstcount (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_burstcount), // .burstcount
.acl_kernel_interface_kernel_cntrl_byteenable (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_byteenable), // .byteenable
.acl_kernel_interface_kernel_cntrl_readdatavalid (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_readdatavalid), // .readdatavalid
.acl_kernel_interface_kernel_cntrl_waitrequest (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_waitrequest), // .waitrequest
.acl_kernel_interface_kernel_cntrl_debugaccess (mm_interconnect_0_acl_kernel_interface_kernel_cntrl_debugaccess), // .debugaccess
.version_id_s_read (mm_interconnect_0_version_id_s_read), // version_id_s.read
.version_id_s_readdata (mm_interconnect_0_version_id_s_readdata) // .readdata
);
system_acl_iface_mm_interconnect_1 mm_interconnect_1 (
.pll_outclk0_clk (pll_outclk0_clk), // pll_outclk0.clk
.clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset.reset
.clock_cross_kernel_mem1_m0_address (clock_cross_kernel_mem1_m0_address), // clock_cross_kernel_mem1_m0.address
.clock_cross_kernel_mem1_m0_waitrequest (clock_cross_kernel_mem1_m0_waitrequest), // .waitrequest
.clock_cross_kernel_mem1_m0_burstcount (clock_cross_kernel_mem1_m0_burstcount), // .burstcount
.clock_cross_kernel_mem1_m0_byteenable (clock_cross_kernel_mem1_m0_byteenable), // .byteenable
.clock_cross_kernel_mem1_m0_read (clock_cross_kernel_mem1_m0_read), // .read
.clock_cross_kernel_mem1_m0_readdata (clock_cross_kernel_mem1_m0_readdata), // .readdata
.clock_cross_kernel_mem1_m0_readdatavalid (clock_cross_kernel_mem1_m0_readdatavalid), // .readdatavalid
.clock_cross_kernel_mem1_m0_write (clock_cross_kernel_mem1_m0_write), // .write
.clock_cross_kernel_mem1_m0_writedata (clock_cross_kernel_mem1_m0_writedata), // .writedata
.clock_cross_kernel_mem1_m0_debugaccess (clock_cross_kernel_mem1_m0_debugaccess), // .debugaccess
.address_span_extender_kernel_windowed_slave_address (mm_interconnect_1_address_span_extender_kernel_windowed_slave_address), // address_span_extender_kernel_windowed_slave.address
.address_span_extender_kernel_windowed_slave_write (mm_interconnect_1_address_span_extender_kernel_windowed_slave_write), // .write
.address_span_extender_kernel_windowed_slave_read (mm_interconnect_1_address_span_extender_kernel_windowed_slave_read), // .read
.address_span_extender_kernel_windowed_slave_readdata (mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdata), // .readdata
.address_span_extender_kernel_windowed_slave_writedata (mm_interconnect_1_address_span_extender_kernel_windowed_slave_writedata), // .writedata
.address_span_extender_kernel_windowed_slave_burstcount (mm_interconnect_1_address_span_extender_kernel_windowed_slave_burstcount), // .burstcount
.address_span_extender_kernel_windowed_slave_byteenable (mm_interconnect_1_address_span_extender_kernel_windowed_slave_byteenable), // .byteenable
.address_span_extender_kernel_windowed_slave_readdatavalid (mm_interconnect_1_address_span_extender_kernel_windowed_slave_readdatavalid), // .readdatavalid
.address_span_extender_kernel_windowed_slave_waitrequest (mm_interconnect_1_address_span_extender_kernel_windowed_slave_waitrequest) // .waitrequest
);
system_acl_iface_mm_interconnect_2 mm_interconnect_2 (
.pll_outclk0_clk (pll_outclk0_clk), // pll_outclk0.clk
.address_span_extender_kernel_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // address_span_extender_kernel_reset_reset_bridge_in_reset.reset
.hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset_reset (rst_controller_003_reset_out_reset), // hps_f2h_sdram0_data_translator_reset_reset_bridge_in_reset.reset
.address_span_extender_kernel_expanded_master_address (address_span_extender_kernel_expanded_master_address), // address_span_extender_kernel_expanded_master.address
.address_span_extender_kernel_expanded_master_waitrequest (address_span_extender_kernel_expanded_master_waitrequest), // .waitrequest
.address_span_extender_kernel_expanded_master_burstcount (address_span_extender_kernel_expanded_master_burstcount), // .burstcount
.address_span_extender_kernel_expanded_master_byteenable (address_span_extender_kernel_expanded_master_byteenable), // .byteenable
.address_span_extender_kernel_expanded_master_read (address_span_extender_kernel_expanded_master_read), // .read
.address_span_extender_kernel_expanded_master_readdata (address_span_extender_kernel_expanded_master_readdata), // .readdata
.address_span_extender_kernel_expanded_master_readdatavalid (address_span_extender_kernel_expanded_master_readdatavalid), // .readdatavalid
.address_span_extender_kernel_expanded_master_write (address_span_extender_kernel_expanded_master_write), // .write
.address_span_extender_kernel_expanded_master_writedata (address_span_extender_kernel_expanded_master_writedata), // .writedata
.hps_f2h_sdram0_data_address (mm_interconnect_2_hps_f2h_sdram0_data_address), // hps_f2h_sdram0_data.address
.hps_f2h_sdram0_data_write (mm_interconnect_2_hps_f2h_sdram0_data_write), // .write
.hps_f2h_sdram0_data_read (mm_interconnect_2_hps_f2h_sdram0_data_read), // .read
.hps_f2h_sdram0_data_readdata (mm_interconnect_2_hps_f2h_sdram0_data_readdata), // .readdata
.hps_f2h_sdram0_data_writedata (mm_interconnect_2_hps_f2h_sdram0_data_writedata), // .writedata
.hps_f2h_sdram0_data_burstcount (mm_interconnect_2_hps_f2h_sdram0_data_burstcount), // .burstcount
.hps_f2h_sdram0_data_byteenable (mm_interconnect_2_hps_f2h_sdram0_data_byteenable), // .byteenable
.hps_f2h_sdram0_data_readdatavalid (mm_interconnect_2_hps_f2h_sdram0_data_readdatavalid), // .readdatavalid
.hps_f2h_sdram0_data_waitrequest (mm_interconnect_2_hps_f2h_sdram0_data_waitrequest) // .waitrequest
);
system_acl_iface_irq_mapper irq_mapper (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (hps_f2h_irq0_irq) // sender.irq
);
system_acl_iface_irq_mapper_001 irq_mapper_001 (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.sender_irq (hps_f2h_irq1_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_n), // reset_in0.reset
.clk (config_clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~acl_kernel_interface_sw_reset_export_reset), // reset_in0.reset
.clk (pll_outclk0_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~hps_h2f_reset_reset), // reset_in0.reset
.clk (config_clk_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_003 (
.reset_in0 (~hps_h2f_reset_reset), // reset_in0.reset
.clk (pll_outclk0_clk), // clk.clk
.reset_out (rst_controller_003_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
assign kernel_clk_snoop_clk = kernel_clk_clk;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:44:40 07/14/2015
// Design Name:
// Module Name: SendCommand
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SendCommand
( input Clk,
output reg [7:0] SendData,
output reg SendReq,
input SendAck,
input [5:0] Command,
input [31:0] Args,
input [6:0] CRC,
input CmdSend,
output reg CmdAck
);
integer Status;
integer Count;
reg [7:0] Buffer [5:0];
initial
begin
Status = 0;
SendData = 8'hFF;
SendReq = 0;
CmdAck = 0;
end
always @(posedge Clk)
begin
case(Status)
0: begin
if (CmdSend == 1) Status = 1;
else Status = 0;
end
1: begin
Buffer[0] = {1'b0, 1'b1, Command};
Buffer[1] = Args[31:24];
Buffer[2] = Args[23:16];
Buffer[3] = Args[15:8];
Buffer[4] = Args[7:0];
Buffer[5] = {CRC, 1'b1};
CmdAck = 1;
Count = 0;
Status = 2;
end
2: begin
if (SendAck == 0)
begin
SendData = Buffer[Count];
SendReq = 1;
Status = 3;
end
else Status = 2;
end
3: begin
if (SendAck == 1)
begin
SendReq = 0;
Status = 4;
end
else Status = 3;
end
4: begin
if (Count < 5)
begin
Count = Count + 1;
Status = 2;
end
else Status = 5;
end
5: begin
if (SendAck == 0)
begin
CmdAck = 0;
Status = 0;
end
else Status = 5;
end
endcase
end
endmodule
|
module arbitro (
// Request bundles are composed by:
// * request_bundle[2] :: hit_x
// * request_bundle[1] :: hit_y
// * request_bundle[0] :: request
input wire [2:0] pe_request_bundle,
input wire [2:0] north_request_bundle,
input wire [2:0] east_request_bundle,
// Configuration bundles are composed by:
// * cfg_bundle[2] :: mux_ctrl[1]
// * cfg_bundle[1] :: mux_ctrl[0]
// * cfg_bundle[0] :: toggle
output reg [1:0] pe_cfg_bundle,
output reg [2:0] south_cfg_bundle,
output reg [2:0] west_cfg_bundle,
// ACK that a request from the PE has been accepted
output reg r2pe_ack
);
// Local Symbols
localparam MUX_EAST = 3'b111;
localparam MUX_NORTH = 3'b101;
localparam MUX_PE = 3'b001;
localparam MUX_NULL = 3'b000;
localparam PE_NULL = 2'b00;
// Signal for visivility at debug
wire [2:0] request_vector;
assign request_vector = {east_request_bundle[0], north_request_bundle[0], pe_request_bundle[0]};
// First level classification - by active request
always @(*)
begin
// default values to infer combinational logic
west_cfg_bundle = MUX_NULL;
south_cfg_bundle = MUX_NULL;
pe_cfg_bundle = PE_NULL;
r2pe_ack = 1'b0;
case (request_vector)
3'b000: // None
begin
// Everything on default
end
3'b001: // PE
begin
r2pe_ack = 1'b1;
case (pe_request_bundle[2:1])
2'b00: west_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
2'b01: west_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
2'b10: south_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
2'b11:
begin
r2pe_ack = 1'b0;
south_cfg_bundle = MUX_NULL; // invalid
end
endcase
end
3'b010: // North
case (north_request_bundle[2:1])
2'b00: west_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
2'b01: west_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
2'b10: south_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
2'b11: pe_cfg_bundle = 2'b01; // mux1 -> north toggle -> 1
endcase
3'b011: // North, PE
begin
r2pe_ack = 1'b1;
case (north_request_bundle[2:1])
2'b00:
begin
west_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
south_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
end
2'b01:
begin
west_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
south_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
end
2'b10:
begin
south_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
west_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
end
2'b11:
begin
west_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
pe_cfg_bundle = 2'b01; // mux1 -> north toggle -> 1
end
endcase
end
3'b100: // East
case (east_request_bundle[2:1])
2'b00: west_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
2'b01: west_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
2'b10: south_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
2'b11: pe_cfg_bundle = 2'b11; // mux1 -> east toggle -> 1
endcase
3'b101: // East, PE
begin
r2pe_ack = 1'b1;
case (east_request_bundle[2:1])
2'b00:
begin
west_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
south_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
end
2'b01:
begin
west_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
south_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
end
2'b10:
begin
south_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
west_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
end
2'b11:
begin
west_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
pe_cfg_bundle = 2'b11; // mux1 -> east toggle -> 1
end
endcase
end
3'b110: // East, North
case (east_request_bundle[2:1])
2'b00:
begin
west_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
south_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
end
2'b01:
begin
west_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
south_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
end
2'b10:
begin
south_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
west_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
end
2'b11:
begin
west_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
pe_cfg_bundle = 2'b11; // mux1 -> east toggle -> 1
end
endcase
3'b111: // East, North, PE
case (east_request_bundle[2:1])
2'b00:
begin
west_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
south_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
end
2'b01:
begin
west_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
if (north_request_bundle[2:1] == 2'b11)
begin
south_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
pe_cfg_bundle = 2'b01; // mux1 -> north, toggle -> 1
r2pe_ack = 1'b1;
end
else
south_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
end
2'b10:
begin
west_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
if (north_request_bundle[2:1] == 2'b11)
begin
west_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
pe_cfg_bundle = 2'b01; // mux1 -> north, toggle -> 1
r2pe_ack = 1'b1;
end
else
south_cfg_bundle = MUX_EAST; // mux1 -> ports, mux2 -> east, toggle -> 1
end
2'b11:
begin
if (north_request_bundle[2:1] == 2'b01)
begin
west_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
south_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
end
else
begin
west_cfg_bundle = MUX_PE; // mux1 -> pe, mux2 -> north, toggle -> 1
south_cfg_bundle = MUX_NORTH; // mux1 -> ports, mux2 -> north, toggle -> 1
end
pe_cfg_bundle = 2'b11; // mux1 -> east toggle -> 1
r2pe_ack = 1'b1;
end
endcase
endcase // first level descrimination :: by active request
end // arbiter body
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4_FUNCTIONAL_V
`define SKY130_FD_SC_MS__NAND4_FUNCTIONAL_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nand4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, D, C, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4_FUNCTIONAL_V |
`timescale 1ns / 1ps
//----------------------------------------------------------
//Copyright (c) 2016, Xilinx, Inc.
//All rights reserved.
//
//Redistribution and use in source and binary forms, with or without modification,
//are permitted provided that the following conditions are met:
//
//1. Redistributions of source code must retain the above copyright notice,
//this list of conditions and the following disclaimer.
//
//2. Redistributions in binary form must reproduce the above copyright notice,
//this list of conditions and the following disclaimer in the documentation
//and/or other materials provided with the distribution.
//
//3. Neither the name of the copyright holder nor the names of its contributors
//may be used to endorse or promote products derived from this software
//without specific prior written permission.
//
//THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
//ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
//THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
//INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
//PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
//HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
//OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
//EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//----------------------------------------------------------
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22.08.2013 08:35:02
// Design Name:
// Module Name: network_module
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module network_module(
input clk156,
input reset,
input aresetn,
input dclk,
input txusrclk,
input txusrclk2,
output txclk322,
//input ref_clk_n,
input areset_refclk_bufh,
input areset_clk156,
input mmcm_locked_clk156,
input gttxreset_txusrclk2,
input gttxreset,
input gtrxreset,
input txuserrdy,
input qplllock,
input qplloutclk,
input qplloutrefclk,
input reset_counter_done,
output tx_resetdone,
output txp,
output txn,
input rxp,
input rxn,
//Axi Stream Interface
input[63:0] tx_axis_tdata,
input tx_axis_tvalid,
input tx_axis_tlast,
input tx_axis_tuser,
input[7:0] tx_axis_tkeep,
output tx_axis_tready,
output[63:0] rx_axis_tdata,
output rx_axis_tvalid,
output rx_axis_tlast,
output rx_axis_tuser,
output[7:0] rx_axis_tkeep,
input rx_axis_tready,
input core_reset, //TODO
input tx_fault,
input signal_detect,
// input[4:0] prtad,
input[7:0] tx_ifg_delay,
output tx_disable,
output[7:0] core_status
);
wire[535:0] configuration_vector;
assign configuration_vector = 0;
wire[63:0] xgmii_txd;
wire[7:0] xgmii_txc;
wire[63:0] xgmii_rxd;
wire[7:0] xgmii_rxc;
reg[63:0] xgmii_txd_reg;
reg[7:0] xgmii_txc_reg;
reg[63:0] xgmii_rxd_reg;
reg[7:0] xgmii_rxc_reg;
reg[63:0] xgmii_txd_reg2;
reg[7:0] xgmii_txc_reg2;
reg[63:0] xgmii_rxd_reg2;
reg[7:0] xgmii_rxc_reg2;
reg[63:0] xgmii_txd_reg3;
reg[7:0] xgmii_txc_reg3;
reg[63:0] xgmii_rxd_reg3;
reg[7:0] xgmii_rxc_reg3;
wire[63:0] axi_str_tdata_to_xgmac;
wire[7:0] axi_str_tkeep_to_xgmac;
wire axi_str_tvalid_to_xgmac;
wire axi_str_tlast_to_xgmac;
wire axi_str_tready_to_xgmac;
wire[63:0] axi_str_rd_tdata_to_fifo;
wire[7:0] axi_str_rd_tkeep_to_fifo;
wire[0:0] axi_str_rd_tuser_to_fifo;
wire axi_str_rd_tvalid_to_fifo;
wire axi_str_rd_tlast_to_fifo;
// Wires for axi register slices
wire tx_axis_slice2interface_tvalid;
wire tx_axis_slice2interface_tready;
wire[63:0] tx_axis_slice2interface_tdata;
wire[7:0] tx_axis_slice2interface_tkeep;
wire tx_axis_slice2interface_tlast;
wire rx_axis_interface2slice_tvalid;
wire rx_axis_interface2slice_tready;
wire[63:0] rx_axis_interface2slice_tdata;
wire[7:0] rx_axis_interface2slice_tkeep;
wire rx_axis_interface2slice_tlast;
wire rx_statistics_valid;
wire [29:0] rx_statistics_vector;
//wire resetdone;
//assign resetdone = tx_resetdone & rx_resetdone;
// Delay serial paths
always @(posedge clk156) begin
xgmii_rxd_reg <= xgmii_rxd;
xgmii_rxc_reg <= xgmii_rxc;
xgmii_txd_reg <= xgmii_txd;
xgmii_txc_reg <= xgmii_txc;
xgmii_rxd_reg2 <= xgmii_rxd_reg;
xgmii_rxc_reg2 <= xgmii_rxc_reg;
xgmii_txd_reg2 <= xgmii_txd_reg;
xgmii_txc_reg2 <= xgmii_txc_reg;
xgmii_rxd_reg3 <= xgmii_rxd_reg2;
xgmii_rxc_reg3 <= xgmii_rxc_reg2;
xgmii_txd_reg3 <= xgmii_txd_reg2;
xgmii_txc_reg3 <= xgmii_txc_reg2;
/*if (reset == 1'b1) begin
xgmii_rxd_reg <= 0;
xgmii_rxc_reg <= 0;
xgmii_txd_reg <= 0;
xgmii_txc_reg <= 0;
end
else begin
xgmii_rxd_reg <= xgmii_rxd;
xgmii_rxc_reg <= xgmii_rxc;
xgmii_txd_reg <= xgmii_txd;
xgmii_txc_reg <= xgmii_txc;
end*/
end
ten_gig_eth_pcs_pma_ip ten_gig_eth_pcs_pma_inst
(
.clk156(clk156),
.dclk(dclk),
.txusrclk(txusrclk),
.txusrclk2(txusrclk2),
.areset(reset),
.txclk322(txclk322),
//.areset_refclk_bufh(areset_refclk_bufh),
.areset_clk156(areset_clk156),
//.mmcm_locked_clk156(mmcm_locked_clk156),
//.gttxreset_txusrclk2(gttxreset_txusrclk2),
.gttxreset(gttxreset),
.gtrxreset(gtrxreset),
.txuserrdy(txuserrdy),
.qplllock(qplllock),
.qplloutclk(qplloutclk),
.qplloutrefclk(qplloutrefclk),
.reset_counter_done(reset_counter_done),
.xgmii_txd(xgmii_txd_reg3),
.xgmii_txc(xgmii_txc_reg3),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.txp(txp),
.txn(txn),
.rxp(rxp),
.rxn(rxn),
.sim_speedup_control(1'b1), // input wire sim_speedup_control INTRODUCED Vivado 2014.3
.configuration_vector(configuration_vector),
.status_vector(),
.core_status(core_status),
.tx_resetdone(tx_resetdone),
.rx_resetdone(),
.signal_detect(signal_detect),
.tx_fault(tx_fault),
//extra drp signals introduced in vivado 2013.4 core gen
.drp_req(drp_req), // output wire drp_req
.drp_gnt(drp_req), // input wire drp_gnt
.drp_den_o(drp_den_o), // output wire drp_den_o
.drp_dwe_o(drp_dwe_o), // output wire drp_dwe_o
.drp_daddr_o(drp_daddr_o), // output wire [15 : 0] drp_daddr_o
.drp_di_o(drp_di_o), // output wire [15 : 0] drp_di_o
.drp_drdy_o(drp_drdy_o), // output wire drp_drdy_o
.drp_drpdo_o(drp_drpdo_o), // output wire [15 : 0] drp_drpdo_o
.drp_den_i(drp_den_o), // input wire drp_den_i
.drp_dwe_i(drp_dwe_o), // input wire drp_dwe_i
.drp_daddr_i(drp_daddr_o), // input wire [15 : 0] drp_daddr_i
.drp_di_i(drp_di_o), // input wire [15 : 0] drp_di_i
.drp_drdy_i(drp_drdy_o), // input wire drp_drdy_i
.drp_drpdo_i(drp_drpdo_o),
.pma_pmd_type(3'b101),
//.pma_pmd_type(pma_pmd_type),
.tx_disable(tx_disable)
);
ten_gig_eth_mac_ip ten_gig_eth_mac_inst
(
.reset(reset),
.tx_axis_aresetn(!reset),
.tx_axis_tdata(axi_str_tdata_to_xgmac),
.tx_axis_tvalid(axi_str_tvalid_to_xgmac),
.tx_axis_tlast(axi_str_tlast_to_xgmac),
.tx_axis_tuser(1'b0),
.tx_ifg_delay(tx_ifg_delay),
.tx_axis_tkeep(axi_str_tkeep_to_xgmac),
.tx_axis_tready(axi_str_tready_from_xgmac),
.tx_statistics_vector(),
.tx_statistics_valid(),
.rx_axis_aresetn(!reset),
.rx_axis_tdata(axi_str_rd_tdata_to_fifo),
.rx_axis_tvalid(axi_str_rd_tvalid_to_fifo),
.rx_axis_tuser(axi_str_rd_tuser_to_fifo),
.rx_axis_tlast(axi_str_rd_tlast_to_fifo),
.rx_axis_tkeep(axi_str_rd_tkeep_to_fifo),
.rx_statistics_vector(rx_statistics_vector),
.rx_statistics_valid(rx_statistics_valid),
.pause_val(16'b0),
.pause_req(1'b0),
.tx_configuration_vector(80'h00000000000000000016),
.rx_configuration_vector(80'h00000000000000000016),
.status_vector(),
.tx_clk0(clk156),
.tx_dcm_locked(mmcm_locked_clk156),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.rx_clk0(clk156),
.rx_dcm_locked(mmcm_locked_clk156),
.xgmii_rxd(xgmii_rxd_reg3),
.xgmii_rxc(xgmii_rxc_reg3)
);
rx_interface
rx_interface_i (
.axi_str_tdata_from_xgmac (axi_str_rd_tdata_to_fifo ),
.axi_str_tkeep_from_xgmac (axi_str_rd_tkeep_to_fifo ),
.axi_str_tvalid_from_xgmac (axi_str_rd_tvalid_to_fifo ),
.axi_str_tlast_from_xgmac (axi_str_rd_tlast_to_fifo ),
.axi_str_tuser_from_xgmac (axi_str_rd_tuser_to_fifo ),
//.mac_id (48'h000000000000 ),
//.mac_id_valid (1'b0 ),
//.promiscuous_mode_en (1'b0 ),
.axi_str_tready_from_fifo (rx_axis_interface2slice_tready),
.axi_str_tdata_to_fifo (rx_axis_interface2slice_tdata),
.axi_str_tkeep_to_fifo (rx_axis_interface2slice_tkeep),
.axi_str_tvalid_to_fifo (rx_axis_interface2slice_tvalid),
.axi_str_tlast_to_fifo (rx_axis_interface2slice_tlast),
.rx_statistics_vector (rx_statistics_vector ),
.rx_statistics_valid (rx_statistics_valid ),
.rd_data_count ( ), //TODO
.rd_pkt_len ( ),
.rx_fifo_overflow ( ), //TODO
.user_clk (clk156 ),
.soft_reset (reset ),
.reset (reset )
);
tx_interface tx_interface_i (
.axi_str_tdata_to_xgmac (axi_str_tdata_to_xgmac ),
.axi_str_tkeep_to_xgmac (axi_str_tkeep_to_xgmac ),
.axi_str_tvalid_to_xgmac (axi_str_tvalid_to_xgmac ),
.axi_str_tlast_to_xgmac (axi_str_tlast_to_xgmac ),
.axi_str_tuser_to_xgmac (axi_str_tuser_to_xgmac ),
.axi_str_tready_from_xgmac(axi_str_tready_from_xgmac ),
.axi_str_tready_to_fifo (tx_axis_slice2interface_tready),
.axi_str_tdata_from_fifo (tx_axis_slice2interface_tdata),
.axi_str_tkeep_from_fifo (tx_axis_slice2interface_tkeep),
.axi_str_tvalid_from_fifo (tx_axis_slice2interface_tvalid),
.axi_str_tlast_from_fifo (tx_axis_slice2interface_tlast),
.user_clk (clk156),
.reset (reset)
);
// TX Input Slice
axis_register_slice_64 axis_register_input_slice(
.aclk(clk156),
.aresetn(aresetn),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tlast(tx_axis_tlast),
.m_axis_tvalid(tx_axis_slice2interface_tvalid),
.m_axis_tready(tx_axis_slice2interface_tready),
.m_axis_tdata(tx_axis_slice2interface_tdata),
.m_axis_tkeep(tx_axis_slice2interface_tkeep),
.m_axis_tlast(tx_axis_slice2interface_tlast)
);
// RX Output slice
axis_register_slice_64 axis_register_output_slice(
.aclk(clk156),
.aresetn(aresetn),
.s_axis_tvalid(rx_axis_interface2slice_tvalid),
.s_axis_tready(rx_axis_interface2slice_tready),
.s_axis_tdata(rx_axis_interface2slice_tdata),
.s_axis_tkeep(rx_axis_interface2slice_tkeep),
.s_axis_tlast(rx_axis_interface2slice_tlast),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tlast(rx_axis_tlast)
);
endmodule
|
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
Require Export CoRN.reals.Intervals.
(**
* Metric Spaces (traditional)
*)
Section Relations.
(**
** Relations necessary for Pseudo Metric Spaces and Metric Spaces
%\begin{convention}%
Let [A : CSetoid], [d : (CSetoid_bin_fun A A IR)].
%\end{convention}%
*)
Variable A : CSetoid.
Variable d : CSetoid_bin_fun A A IR.
Set Implicit Arguments.
Unset Strict Implicit.
Definition com : Prop := forall x y : A, d x y[=]d y x.
Definition nneg : Prop := forall x y : A, [0][<=]d x y.
Definition pos_imp_ap : CProp := forall x y : A, [0][<]d x y -> x[#]y.
Definition tri_ineq : Prop := forall x y z : A, d x z[<=]d x y[+]d y z.
Set Strict Implicit.
Unset Implicit Arguments.
Definition diag_zero (X : CSetoid) (d : CSetoid_bin_fun X X IR) : Prop :=
forall x : X, d x x[=][0].
Definition apdiag_imp_grzero (X : CSetoid) (d : CSetoid_bin_fun X X IR) :
CProp := forall x y : X, x[#]y -> [0][<]d x y.
End Relations.
Section Definition_PsMS0.
(**
** Definition of Pseudo Metric Space
*)
(**
A pseudo metric space consists of a setoid and a %''pseudo metric''% #"pseudo metric"#, also called
%''distance''% #"distance"#, a binairy function that fulfils certain properties.
*)
Record is_CPsMetricSpace (A : CSetoid) (d : CSetoid_bin_fun A A IR) :
Type :=
{ax_d_com : com d;
ax_d_nneg : nneg d;
ax_d_pos_imp_ap : pos_imp_ap d;
ax_d_tri_ineq : tri_ineq d}.
Record CPsMetricSpace : Type :=
{cms_crr :> CSetoid;
cms_d : CSetoid_bin_fun cms_crr cms_crr IR;
cms_proof : is_CPsMetricSpace cms_crr cms_d}.
End Definition_PsMS0.
Arguments cms_d {c}.
Infix "[-d]" := cms_d (at level 68, left associativity).
Section PsMS_axioms.
(**
** Pseudo Metric Space axioms
%\begin{convention}%
Let [A] be a pseudo metric space.
%\end{convention}%
*)
Variable A : CPsMetricSpace.
Lemma CPsMetricSpace_is_CPsMetricSpace : is_CPsMetricSpace A cms_d.
Proof cms_proof A.
Lemma d_com : com (cms_d (c:=A)).
Proof.
elim CPsMetricSpace_is_CPsMetricSpace.
auto.
Qed.
Lemma d_nneg : nneg (cms_d (c:=A)).
Proof.
elim CPsMetricSpace_is_CPsMetricSpace.
auto.
Qed.
Lemma d_pos_imp_ap : pos_imp_ap (cms_d (c:=A)).
Proof.
elim CPsMetricSpace_is_CPsMetricSpace.
auto.
Qed.
Lemma d_tri_ineq : tri_ineq (cms_d (c:=A)).
Proof.
elim CPsMetricSpace_is_CPsMetricSpace.
auto.
Qed.
End PsMS_axioms.
Section PsMS_basics.
(**
** Pseudo Metric Space basics
%\begin{convention}%
Let [Y] be a pseudo metric space.
%\end{convention}%
*)
Variable Y : CPsMetricSpace.
Lemma rev_tri_ineq :
forall a b c : cms_crr Y, AbsSmall (b[-d]c) ((a[-d]b)[-](a[-d]c)).
Proof.
intros.
unfold AbsSmall in |- *.
split.
apply shift_leEq_minus.
apply shift_plus_leEq'.
unfold cg_minus in |- *.
cut ([--][--](b[-d]c)[=]b[-d]c).
intros.
apply leEq_wdr with ((a[-d]b)[+](b[-d]c)).
apply ax_d_tri_ineq.
apply CPsMetricSpace_is_CPsMetricSpace.
apply eq_symmetric_unfolded.
apply bin_op_wd_unfolded.
apply eq_reflexive_unfolded.
exact H.
apply cg_inv_inv.
astepr (c[-d]b).
apply shift_minus_leEq.
apply shift_leEq_plus'.
apply shift_minus_leEq.
apply ax_d_tri_ineq.
apply CPsMetricSpace_is_CPsMetricSpace.
apply ax_d_com.
apply CPsMetricSpace_is_CPsMetricSpace.
Qed.
(**
Instead of taking [pos_imp_ap] as axiom,
we could as well have taken [diag_zero].
*)
Lemma diag_zero_imp_pos_imp_ap :
forall (X : CSetoid) (d : CSetoid_bin_fun X X IR),
diag_zero X d -> pos_imp_ap d.
Proof.
intros X d.
unfold diag_zero in |- *.
unfold pos_imp_ap in |- *.
intros H.
intros x y H0.
cut (x[#]x or x[#]y).
intro H1.
elim H1.
cut (Not (x[#]x)).
intros H3 H4.
set (H5 := H3 H4) in *.
intuition.
apply ap_irreflexive_unfolded.
intro H2.
exact H2.
apply (csbf_strext X X IR d).
astepl ZeroR.
apply less_imp_ap.
exact H0.
Qed.
Lemma pos_imp_ap_imp_diag_zero :
forall (X : CSetoid) (d : CSetoid_bin_fun X X IR),
pos_imp_ap d -> nneg d -> diag_zero X d.
Proof.
intros X d.
unfold pos_imp_ap in |- *.
unfold nneg in |- *.
intros H H6.
unfold diag_zero in |- *.
intro x.
apply not_ap_imp_eq.
red in |- *.
intro H0.
set (H1 := less_conf_ap IR (d x x) [0]) in *.
generalize H1.
unfold Iff in |- *.
intro H2.
elim H2.
intros H3 H4.
set (H5 := H3 H0) in *.
elim H5.
generalize H6.
intros H7 H8.
set (H9 := H7 x x) in *.
rewrite -> leEq_def in H9.
set (H10 := H9 H8) in *.
exact H10.
intro H7.
set (H8 := H x x) in *.
set (H9 := H8 H7) in *.
set (H10 := ap_irreflexive_unfolded X x H9) in *.
exact H10.
Qed.
Lemma is_CPsMetricSpace_diag_zero :
forall (X : CSetoid) (d : CSetoid_bin_fun X X IR),
com d /\ tri_ineq d /\ nneg d /\ diag_zero X d -> is_CPsMetricSpace X d.
Proof.
intros X d H.
elim H.
intros H1 H2.
elim H2.
intros H3 H4.
elim H4.
intros H5 H6.
apply (Build_is_CPsMetricSpace X d H1 H5 (diag_zero_imp_pos_imp_ap X d H6) H3).
Qed.
End PsMS_basics.
Section Zerof.
(**
** Zero function
*)
(**
Every setoid forms with the binary function that always returns zero,
a pseudo metric space.
*)
Definition zero_fun (X : CSetoid) (x y : X) : IR := ZeroR.
Lemma zero_fun_strext :
forall X : CSetoid, bin_fun_strext X X IR (zero_fun X).
Proof.
intro X.
unfold bin_fun_strext in |- *.
unfold zero_fun in |- *.
intros x1 x2 y1 y2 Z.
set (H := ap_irreflexive_unfolded IR [0] Z) in *.
intuition.
Qed.
Definition Zero_fun (X : CSetoid) :=
Build_CSetoid_bin_fun X X IR (zero_fun X) (zero_fun_strext X).
Lemma zero_fun_com : forall X : CSetoid, com (Zero_fun X).
Proof.
intro X.
unfold com in |- *.
intros x y.
unfold Zero_fun in |- *.
simpl in |- *.
unfold zero_fun in |- *.
intuition.
Qed.
Lemma zero_fun_nneg : forall X : CSetoid, nneg (Zero_fun X).
Proof.
intro X.
unfold nneg in |- *.
intros x y.
unfold Zero_fun in |- *.
simpl in |- *.
unfold zero_fun in |- *.
apply eq_imp_leEq.
intuition.
Qed.
Lemma zero_fun_pos_imp_ap : forall X : CSetoid, pos_imp_ap (Zero_fun X).
Proof.
intro X.
unfold pos_imp_ap in |- *.
intros x y.
unfold Zero_fun in |- *.
simpl in |- *.
unfold zero_fun in |- *.
intro Z.
set (H := less_irreflexive IR [0] Z) in *.
intuition.
Qed.
Lemma zero_fun_tri_ineq : forall X : CSetoid, tri_ineq (Zero_fun X).
Proof.
intro X.
unfold tri_ineq in |- *.
intros x y z.
unfold Zero_fun in |- *.
simpl in |- *.
unfold zero_fun in |- *.
apply eq_imp_leEq.
rational.
Qed.
Definition zf_is_CPsMetricSpace (X : CSetoid) :=
Build_is_CPsMetricSpace X (Zero_fun X) (zero_fun_com X) (
zero_fun_nneg X) (zero_fun_pos_imp_ap X) (zero_fun_tri_ineq X).
Definition zf_as_CPsMetricSpace (X : CSetoid) :=
Build_CPsMetricSpace X (Zero_fun X) (zf_is_CPsMetricSpace X).
End Zerof.
|
/*
* The MIT License (MIT)
*
* Copyright (c) 2015 Stefan Wendler
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
/**
* Testbench for rcswitch_reveive.
*
* I use this with iverilog and gtkwave:
*
* iverilog -o rcswitch.vvp clockdiv.v rcswitch.v rcswitch_receive_tb.v
* ./rcswitch_receive.vvp
* gtkwace rcswitch_receive.vcd
*/
module rcswitch_test;
reg in;
initial begin
#0 in = 0;
// Garbage
#30 in = 1; // 1000 - 1
#10 in = 0;
#22 in = 1; // 1000
#10 in = 0;
#30 in = 1; // 1000 - 2
#10 in = 0;
#30 in = 1; // 1000
#11 in = 0;
// Sync 10000000_00000000_00000000_00000000
#30 in = 1; // 1000 - 1
#10 in = 0;
#30 in = 0; // 0000
#30 in = 0;
#10 in = 0; // 0000 - 2
#30 in = 0;
#10 in = 0; // 0000
#30 in = 0;
#10 in = 0; // 0000 - 3
#30 in = 0;
#10 in = 0; // 0000
#30 in = 0;
#10 in = 0; // 0000 - 4
#30 in = 0;
#10 in = 0; // 0000
#30 in = 0;
// Address 10001000_10001000_10001000_10001000_10001000
#10 in = 1; // 1000 - 1
#10 in = 0;
#30 in = 1; // 1000
#08 in = 0;
#30 in = 1; // 1000 - 2
#10 in = 0;
#25 in = 1; // 1000
#10 in = 0;
#30 in = 1; // 1000 - 3
#10 in = 0;
#22 in = 1; // 1000
#10 in = 0;
#30 in = 1; // 1000 - 4
#10 in = 0;
#30 in = 1; // 1000
#11 in = 0;
#30 in = 1; // 1000 - 5
#10 in = 0;
#30 in = 1; // 1000
#10 in = 0;
// Channel 10001000_10001110_10001110_10001110_10001110
#30 in = 1; // 1000 - 1
#11 in = 0;
#30 in = 1; // 1000
#10 in = 0;
#30 in = 1; // 1000 - 2
#10 in = 0;
#30 in = 1; // 1110
#30 in = 0;
#10 in = 1; // 1000 - 3
#10 in = 0;
#30 in = 1; // 1110
#30 in = 0;
#10 in = 1; // 1000 - 4
#10 in = 0;
#30 in = 1; // 1110
#30 in = 0;
#10 in = 1; // 1000 - 5
#10 in = 0;
#30 in = 1; // 1110
#30 in = 0;
// Stat 10001110_10001000
#10 in = 1; // 1000 - 1
#10 in = 0;
#30 in = 1; // 1110
#30 in = 0;
#10 in = 1; // 1000 - 2
#10 in = 0;
#30 in = 1; // 1000
#10 in = 0;
// Sync 10000000_00000000_00000000_00000000
#30 in = 1; // 1000 - 1
#10 in = 0;
#30 in = 0; // 0000
#30 in = 0;
#10 in = 0; // 0000 - 2
#30 in = 0;
#10 in = 0; // 0000
#30 in = 0;
#10 in = 0; // 0000 - 3
#30 in = 0;
#10 in = 0; // 0000
#30 in = 0;
#10 in = 0; // 0000 - 4
#30 in = 0;
#10 in = 0; // 0000
#30 in = 0;
// Garbage
#30 in = 1; // 1000 - 1
#10 in = 0;
#22 in = 1; // 1000
#10 in = 0;
#30 in = 1; // 1000 - 2
#10 in = 0;
#30 in = 1; // 1000
#11 in = 0;
#100 $finish;
end
// clock
reg clk = 0;
always #1 clk = !clk;
wire [39:0] addr;
wire [39:0] chan;
wire [15:0] stat;
wire ready;
rcswitch_receive rcswitch_receive_inst (
.clk(clk),
.rst(1'b0),
.in(in),
.addr(addr),
.chan(chan),
.stat(stat),
.ready(ready)
);
initial
begin
$dumpfile("rcswitch_receive.vcd");
$dumpvars(0, rcswitch_receive_inst);
end
always @(posedge ready) begin
$display("RECEIVED:");
$display(" addr=%b", addr);
$display(" chan=%b", chan);
$display(" stat=%b", stat);
/*
if(addr == 40'h8888888888) begin
$display("MATCH: addr");
end
if(chan == 40'h888E8E8E8E) begin
$display("MATCH: chan");
end
if(stat == 16'h8E88) begin
$display("MATCH: stat");
end
*/
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111AI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O2111AI_BEHAVIORAL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o2111ai (
Y ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111AI_BEHAVIORAL_V |
module fpu_array (
pcx_fpio_data_rdy_px2,
pcx_fpio_data_px2,
arst_l,
grst_l,
gclk,
cluster_cken,
fp_cpx_req_cq,
fp_cpx_data_ca,
ctu_tst_pre_grst_l,
global_shift_enable,
ctu_tst_scan_disable,
ctu_tst_scanmode,
ctu_tst_macrotest,
ctu_tst_short_chain,
si,
so
);
parameter SIZE = 8;
input pcx_fpio_data_rdy_px2; // FPU request ready from PCX
input [123:0] pcx_fpio_data_px2; // FPU request data from PCX
input arst_l; // chip async. reset- asserted low
input grst_l; // chip sync. reset- asserted low
input gclk; // chip clock
input cluster_cken; // cluster clock enable
output [7:0] fp_cpx_req_cq; // FPU result request to CPX
output [144:0] fp_cpx_data_ca; // FPU result to CPX
input ctu_tst_pre_grst_l;
input global_shift_enable;
input ctu_tst_scan_disable;
input ctu_tst_scanmode;
input ctu_tst_macrotest;
input ctu_tst_short_chain;
input si; // scan in
output so; // scan out
reg [123:0] pcx_fpio_data_px2_bus[SIZE:0];
reg pcx_fpio_data_rdy_px2_bus[SIZE:0];
wire [7:0] fp_cpx_req_cq_bus[SIZE:0];
wire [144:0] fp_cpx_data_ca_bus[SIZE:0];
genvar i;
generate
for ( i = 0; i < SIZE; i = i+1 )
begin : array
fpu fpu(
pcx_fpio_data_rdy_px2_bus[i],
pcx_fpio_data_px2_bus[i],
arst_l,
grst_l,
gclk,
cluster_cken,
fp_cpx_req_cq,
fp_cpx_data_ca,
ctu_tst_pre_grst_l,
global_shift_enable,
ctu_tst_scan_disable,
ctu_tst_scanmode,
ctu_tst_macrotest,
ctu_tst_short_chain,
si,
so
);
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S15KAPWR_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLYBUF4S15KAPWR_FUNCTIONAL_PP_V
/**
* dlybuf4s15kapwr: Delay Buffer 4-stage 0.15um length inner stage
* gates on keep-alive power rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__dlybuf4s15kapwr (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, KAPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S15KAPWR_FUNCTIONAL_PP_V |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk_125mhz,
input wire clk90_125mhz,
input wire rst_125mhz,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire ledu,
output wire ledl,
output wire ledd,
output wire ledr,
output wire ledc,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
/*
* Silicon Labs CP2103 USB UART
*/
output wire uart_rxd,
input wire uart_txd,
input wire uart_rts,
output wire uart_cts
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk_125mhz) begin
if (rst_125mhz) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk_125mhz) begin
if (rst_125mhz) begin
led_reg <= 0;
end else begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
end
end
//assign led = sw;
assign ledu = 0;
assign ledl = 0;
assign ledd = 0;
assign ledr = 0;
assign ledc = 0;
assign led = led_reg;
assign phy_reset_n = !rst_125mhz;
assign uart_rxd = 0;
assign uart_cts = 0;
eth_mac_1g_rgmii_fifo #(
.TARGET(TARGET),
.IODDR_STYLE("IODDR"),
.CLOCK_INPUT_STYLE("BUFR"),
.USE_CLK90("TRUE"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk_125mhz),
.gtx_clk90(clk90_125mhz),
.gtx_rst(rst_125mhz),
.logic_clk(clk_125mhz),
.logic_rst(rst_125mhz),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.rgmii_rx_clk(phy_rx_clk),
.rgmii_rxd(phy_rxd),
.rgmii_rx_ctl(phy_rx_ctl),
.rgmii_tx_clk(phy_tx_clk),
.rgmii_txd(phy_txd),
.rgmii_tx_ctl(phy_tx_ctl),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk_125mhz),
.rst(rst_125mhz),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk_125mhz),
.rst(rst_125mhz),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk_125mhz),
.rst(rst_125mhz),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk_125mhz),
.rst(rst_125mhz),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
`resetall
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : ime_sad_16x16_buffer.v
// Author : Huang Lei Lei
// Created : 2014-12-10
// Description : buffer 16x16 sad
//
//-------------------------------------------------------------------
//
// Modified : 2014-12-21
// Description : bug removed (port name and memory datawidth)
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module ime_sad_16x16_buffer (
// global
clk ,
rstn ,
// ctrl_i
addr_i ,
wren_i ,
block_i ,
// sad_i
sad_16x16_x0_i ,
sad_16x16_x1_i ,
sad_16x16_x2_i ,
sad_16x16_x3_i ,
// sad_o
sad_16x16_00_o ,
sad_16x16_01_o ,
sad_16x16_02_o ,
sad_16x16_03_o ,
sad_16x16_10_o ,
sad_16x16_11_o ,
sad_16x16_12_o ,
sad_16x16_13_o ,
sad_16x16_20_o ,
sad_16x16_21_o ,
sad_16x16_22_o ,
sad_16x16_23_o
);
//*** PARAMETER DECLARATION ****************************************************
//*** INPUT/OUTPUT DECLARATION *************************************************
// global
input clk ;
input rstn ;
// ctrl_i
input [4 : 0] addr_i ;
input wren_i ;
input [1 : 0] block_i ;
// sad_i
input [`PIXEL_WIDTH+7 : 0] sad_16x16_x0_i ;
input [`PIXEL_WIDTH+7 : 0] sad_16x16_x1_i ;
input [`PIXEL_WIDTH+7 : 0] sad_16x16_x2_i ;
input [`PIXEL_WIDTH+7 : 0] sad_16x16_x3_i ;
// sad_o
output [`PIXEL_WIDTH+7 : 0] sad_16x16_00_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_01_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_02_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_03_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_10_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_11_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_12_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_13_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_20_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_21_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_22_o ;
output [`PIXEL_WIDTH+7 : 0] sad_16x16_23_o ;
//*** WIRE & REG DECLARATION ***************************************************
//*** MAIN BODY ****************************************************************
rf_1p #(
.Word_Width ( 16*4 ),
.Addr_Width ( 5 )
) buffer0 (
.clk ( clk ),
.cen_i ( 1'b0 ),
.wen_i ( !(wren_i & (block_i==2'b00)) ),
.addr_i ( addr_i ),
.data_i ( { sad_16x16_x0_i ,sad_16x16_x1_i ,sad_16x16_x2_i ,sad_16x16_x3_i } ),
.data_o ( { sad_16x16_00_o ,sad_16x16_01_o ,sad_16x16_02_o ,sad_16x16_03_o } )
);
rf_1p #(
.Word_Width ( 16*4 ),
.Addr_Width ( 5 )
) buffer1 (
.clk ( clk ),
.cen_i ( 1'b0 ),
.wen_i ( !(wren_i & (block_i==2'b01)) ),
.addr_i ( addr_i ),
.data_i ( { sad_16x16_x0_i ,sad_16x16_x1_i ,sad_16x16_x2_i ,sad_16x16_x3_i } ),
.data_o ( { sad_16x16_10_o ,sad_16x16_11_o ,sad_16x16_12_o ,sad_16x16_13_o } )
);
rf_1p #(
.Word_Width ( 16*4 ),
.Addr_Width ( 5 )
) buffer2 (
.clk ( clk ),
.cen_i ( 1'b0 ),
.wen_i ( !(wren_i & (block_i==2'b10)) ),
.addr_i ( addr_i ),
.data_i ( { sad_16x16_x0_i ,sad_16x16_x1_i ,sad_16x16_x2_i ,sad_16x16_x3_i } ),
.data_o ( { sad_16x16_20_o ,sad_16x16_21_o ,sad_16x16_22_o ,sad_16x16_23_o } )
);
//*** DEBUG ********************************************************************
endmodule |
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: alt_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire5;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire locked = sub_wire5;
altpll altpll_component (
.areset (areset),
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire5),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 5,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 8,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "MAX 10",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=alt_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "80.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "80.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "alt_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: aluparam_synthesis.v
// /___/ /\ Timestamp: Sun Apr 05 19:40:38 2015
// \ \ / \
// \___\/\___\
//
// Command : -intstyle ise -tm aluparamsynthesis -insert_glbl true -w -dir netgen/synthesis -ofmt verilog -sim aluparam.ngc aluparam_synthesis.v
// Device : xc6slx16-3-csg324
// Input file : aluparam.ngc
// Output file : C:\Users\Joseph\Documents\Xilinx\HW2\netgen\synthesis\aluparam_synthesis.v
// # of Modules : 1
// Design Name : aluparam
// Xilinx : D:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module aluparamsynthesis (
A, B, sel, Y, flags
);
input [15 : 0] A;
input [15 : 0] B;
input [3 : 0] sel;
output [15 : 0] Y;
output [15 : 0] flags;
wire A_0_IBUF_0;
wire A_1_IBUF_1;
wire A_2_IBUF_2;
wire A_3_IBUF_3;
wire A_4_IBUF_4;
wire A_5_IBUF_5;
wire A_6_IBUF_6;
wire A_7_IBUF_7;
wire A_8_IBUF_8;
wire A_9_IBUF_9;
wire A_10_IBUF_10;
wire A_11_IBUF_11;
wire A_12_IBUF_12;
wire A_13_IBUF_13;
wire A_14_IBUF_14;
wire A_15_IBUF_15;
wire B_0_IBUF_16;
wire B_1_IBUF_17;
wire B_2_IBUF_18;
wire B_3_IBUF_19;
wire B_4_IBUF_20;
wire B_5_IBUF_21;
wire B_6_IBUF_22;
wire B_7_IBUF_23;
wire B_8_IBUF_24;
wire B_9_IBUF_25;
wire B_10_IBUF_26;
wire B_11_IBUF_27;
wire B_12_IBUF_28;
wire B_13_IBUF_29;
wire B_14_IBUF_30;
wire B_15_IBUF_31;
wire sel_0_IBUF_32;
wire sel_2_IBUF_33;
wire sel_3_IBUF_34;
wire sel_1_IBUF_35;
wire Y_0_OBUF_36;
wire Y_1_OBUF_37;
wire Y_2_OBUF_38;
wire Y_3_OBUF_39;
wire Y_4_OBUF_40;
wire Y_5_OBUF_41;
wire Y_6_OBUF_42;
wire Y_7_OBUF_43;
wire Y_8_OBUF_44;
wire Y_9_OBUF_45;
wire Y_10_OBUF_46;
wire Y_11_OBUF_47;
wire Y_12_OBUF_48;
wire Y_13_OBUF_49;
wire Y_14_OBUF_50;
wire flags_7_OBUF_51;
wire flags_2_OBUF_67;
wire flags_0_OBUF_68;
wire flags_5_OBUF_69;
wire flags_6_OBUF_70;
wire flags_1_OBUF_71;
wire \GEN_FULL_ADDERS[15].full_adders/n0006 ;
wire \flags<6>1_73 ;
wire \flags<6>2_74 ;
wire N2;
wire N4;
wire N6;
wire N8;
wire N10;
wire N12;
wire N14;
wire N16;
wire N18;
wire N20;
wire N22;
wire N24;
wire N26;
wire N28;
wire [15 : 1] Cin;
GND XST_GND (
.G(flags_1_OBUF_71)
);
LUT6 #(
.INIT ( 64'hDADADA8A8ADA8A8A ))
\GEN_CARRY_MUX[1].carry_mux/Mmux_pin<0><0>11 (
.I0(sel_1_IBUF_35),
.I1(B_1_IBUF_17),
.I2(sel_2_IBUF_33),
.I3(B_0_IBUF_16),
.I4(sel_0_IBUF_32),
.I5(A_0_IBUF_0),
.O(Cin[1])
);
LUT5 #(
.INIT ( 32'h92E9E992 ))
\GEN_OUT_MUX[1].out_mux/Mmux_pin<0><0>11 (
.I0(Cin[1]),
.I1(sel_3_IBUF_34),
.I2(A_1_IBUF_1),
.I3(B_1_IBUF_17),
.I4(sel_0_IBUF_32),
.O(Y_1_OBUF_37)
);
LUT5 #(
.INIT ( 32'h00000080 ))
out3 (
.I0(\GEN_FULL_ADDERS[15].full_adders/n0006 ),
.I1(sel_0_IBUF_32),
.I2(sel_2_IBUF_33),
.I3(sel_3_IBUF_34),
.I4(sel_1_IBUF_35),
.O(flags_2_OBUF_67)
);
LUT5 #(
.INIT ( 32'h00000010 ))
out11 (
.I0(\GEN_FULL_ADDERS[15].full_adders/n0006 ),
.I1(sel_0_IBUF_32),
.I2(sel_2_IBUF_33),
.I3(sel_3_IBUF_34),
.I4(sel_1_IBUF_35),
.O(flags_0_OBUF_68)
);
LUT5 #(
.INIT ( 32'h04000004 ))
out21 (
.I0(sel_1_IBUF_35),
.I1(sel_2_IBUF_33),
.I2(sel_3_IBUF_34),
.I3(Cin[15]),
.I4(\GEN_FULL_ADDERS[15].full_adders/n0006 ),
.O(flags_5_OBUF_69)
);
LUT5 #(
.INIT ( 32'h92E9E992 ))
\GEN_OUT_MUX[2].out_mux/Mmux_pin<0><0>11 (
.I0(Cin[2]),
.I1(sel_3_IBUF_34),
.I2(A_2_IBUF_2),
.I3(B_2_IBUF_18),
.I4(sel_0_IBUF_32),
.O(Y_2_OBUF_38)
);
LUT5 #(
.INIT ( 32'h92E9E992 ))
\GEN_OUT_MUX[3].out_mux/Mmux_pin<0><0>11 (
.I0(Cin[3]),
.I1(sel_3_IBUF_34),
.I2(A_3_IBUF_3),
.I3(B_3_IBUF_19),
.I4(sel_0_IBUF_32),
.O(Y_3_OBUF_39)
);
LUT5 #(
.INIT ( 32'h92E9E992 ))
\GEN_OUT_MUX[4].out_mux/Mmux_pin<0><0>11 (
.I0(Cin[4]),
.I1(sel_3_IBUF_34),
.I2(A_4_IBUF_4),
.I3(B_4_IBUF_20),
.I4(sel_0_IBUF_32),
.O(Y_4_OBUF_40)
);
LUT5 #(
.INIT ( 32'h92E9E992 ))
\GEN_OUT_MUX[5].out_mux/Mmux_pin<0><0>11 (
.I0(Cin[5]),
.I1(sel_3_IBUF_34),
.I2(A_5_IBUF_5),
.I3(B_5_IBUF_21),
.I4(sel_0_IBUF_32),
.O(Y_5_OBUF_41)
);
LUT5 #(
.INIT ( 32'h92E9E992 ))
\GEN_OUT_MUX[6].out_mux/Mmux_pin<0><0>11 (
.I0(Cin[6]),
.I1(sel_3_IBUF_34),
.I2(A_6_IBUF_6),
.I3(B_6_IBUF_22),
.I4(sel_0_IBUF_32),
.O(Y_6_OBUF_42)
);
LUT5 #(
.INIT ( 32'h92E9E992 ))
\GEN_OUT_MUX[7].out_mux/Mmux_pin<0><0>11 (
.I0(Cin[7]),
.I1(sel_3_IBUF_34),
.I2(A_7_IBUF_7),
.I3(B_7_IBUF_23),
.I4(sel_0_IBUF_32),
.O(Y_7_OBUF_43)
);
LUT5 #(
.INIT ( 32'h92E9E992 ))
\GEN_OUT_MUX[8].out_mux/Mmux_pin<0><0>11 (
.I0(Cin[8]),
.I1(sel_3_IBUF_34),
.I2(A_8_IBUF_8),
.I3(B_8_IBUF_24),
.I4(sel_0_IBUF_32),
.O(Y_8_OBUF_44)
);
LUT5 #(
.INIT ( 32'h92E9E992 ))
\GEN_OUT_MUX[9].out_mux/Mmux_pin<0><0>11 (
.I0(Cin[9]),
.I1(sel_3_IBUF_34),
.I2(A_9_IBUF_9),
.I3(B_9_IBUF_25),
.I4(sel_0_IBUF_32),
.O(Y_9_OBUF_45)
);
LUT5 #(
.INIT ( 32'h92E9E992 ))
\GEN_OUT_MUX[10].out_mux/Mmux_pin<0><0>11 (
.I0(Cin[10]),
.I1(sel_3_IBUF_34),
.I2(A_10_IBUF_10),
.I3(B_10_IBUF_26),
.I4(sel_0_IBUF_32),
.O(Y_10_OBUF_46)
);
LUT5 #(
.INIT ( 32'h92E9E992 ))
\GEN_OUT_MUX[11].out_mux/Mmux_pin<0><0>11 (
.I0(Cin[11]),
.I1(sel_3_IBUF_34),
.I2(A_11_IBUF_11),
.I3(B_11_IBUF_27),
.I4(sel_0_IBUF_32),
.O(Y_11_OBUF_47)
);
LUT5 #(
.INIT ( 32'h92E9E992 ))
\GEN_OUT_MUX[12].out_mux/Mmux_pin<0><0>11 (
.I0(Cin[12]),
.I1(sel_3_IBUF_34),
.I2(A_12_IBUF_12),
.I3(B_12_IBUF_28),
.I4(sel_0_IBUF_32),
.O(Y_12_OBUF_48)
);
LUT5 #(
.INIT ( 32'h92E9E992 ))
\GEN_OUT_MUX[13].out_mux/Mmux_pin<0><0>11 (
.I0(Cin[13]),
.I1(sel_3_IBUF_34),
.I2(A_13_IBUF_13),
.I3(B_13_IBUF_29),
.I4(sel_0_IBUF_32),
.O(Y_13_OBUF_49)
);
LUT5 #(
.INIT ( 32'h92E9E992 ))
\GEN_OUT_MUX[14].out_mux/Mmux_pin<0><0>11 (
.I0(Cin[14]),
.I1(sel_3_IBUF_34),
.I2(A_14_IBUF_14),
.I3(B_14_IBUF_30),
.I4(sel_0_IBUF_32),
.O(Y_14_OBUF_50)
);
LUT4 #(
.INIT ( 16'h7117 ))
\GEN_FULL_ADDERS[15].full_adders/n00061 (
.I0(A_15_IBUF_15),
.I1(Cin[15]),
.I2(B_15_IBUF_31),
.I3(sel_0_IBUF_32),
.O(\GEN_FULL_ADDERS[15].full_adders/n0006 )
);
LUT6 #(
.INIT ( 64'hE2E43C5AF6606996 ))
\GEN_OUT_MUX[0].out_mux/Mmux_pin<0><0>11 (
.I0(B_0_IBUF_16),
.I1(sel_0_IBUF_32),
.I2(A_0_IBUF_0),
.I3(sel_1_IBUF_35),
.I4(sel_3_IBUF_34),
.I5(sel_2_IBUF_33),
.O(Y_0_OBUF_36)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
\flags<6>1 (
.I0(Y_1_OBUF_37),
.I1(Y_0_OBUF_36),
.I2(Y_2_OBUF_38),
.I3(Y_3_OBUF_39),
.I4(Y_4_OBUF_40),
.I5(Y_5_OBUF_41),
.O(\flags<6>1_73 )
);
LUT6 #(
.INIT ( 64'h0000000000010000 ))
\flags<6>2 (
.I0(Y_6_OBUF_42),
.I1(Y_7_OBUF_43),
.I2(Y_8_OBUF_44),
.I3(Y_9_OBUF_45),
.I4(\flags<6>1_73 ),
.I5(Y_10_OBUF_46),
.O(\flags<6>2_74 )
);
LUT6 #(
.INIT ( 64'h0000000000010000 ))
\flags<6>3 (
.I0(Y_11_OBUF_47),
.I1(Y_12_OBUF_48),
.I2(Y_13_OBUF_49),
.I3(Y_14_OBUF_50),
.I4(\flags<6>2_74 ),
.I5(flags_7_OBUF_51),
.O(flags_6_OBUF_70)
);
LUT2 #(
.INIT ( 4'h9 ))
\GEN_CARRY_MUX[2].carry_mux/Mmux_pin<0><0>1_SW0 (
.I0(sel_0_IBUF_32),
.I1(B_1_IBUF_17),
.O(N2)
);
LUT6 #(
.INIT ( 64'hECCCEEEC64446664 ))
\GEN_CARRY_MUX[2].carry_mux/Mmux_pin<0><0>1 (
.I0(sel_2_IBUF_33),
.I1(sel_1_IBUF_35),
.I2(Cin[1]),
.I3(A_1_IBUF_1),
.I4(N2),
.I5(B_2_IBUF_18),
.O(Cin[2])
);
LUT2 #(
.INIT ( 4'h9 ))
\GEN_CARRY_MUX[3].carry_mux/Mmux_pin<0><0>1_SW0 (
.I0(sel_0_IBUF_32),
.I1(B_2_IBUF_18),
.O(N4)
);
LUT6 #(
.INIT ( 64'hECCCEEEC64446664 ))
\GEN_CARRY_MUX[3].carry_mux/Mmux_pin<0><0>1 (
.I0(sel_2_IBUF_33),
.I1(sel_1_IBUF_35),
.I2(A_2_IBUF_2),
.I3(Cin[2]),
.I4(N4),
.I5(B_3_IBUF_19),
.O(Cin[3])
);
LUT2 #(
.INIT ( 4'h9 ))
\GEN_CARRY_MUX[4].carry_mux/Mmux_pin<0><0>1_SW0 (
.I0(sel_0_IBUF_32),
.I1(B_3_IBUF_19),
.O(N6)
);
LUT6 #(
.INIT ( 64'hECCCEEEC64446664 ))
\GEN_CARRY_MUX[4].carry_mux/Mmux_pin<0><0>1 (
.I0(sel_2_IBUF_33),
.I1(sel_1_IBUF_35),
.I2(A_3_IBUF_3),
.I3(Cin[3]),
.I4(N6),
.I5(B_4_IBUF_20),
.O(Cin[4])
);
LUT2 #(
.INIT ( 4'h9 ))
\GEN_CARRY_MUX[5].carry_mux/Mmux_pin<0><0>1_SW0 (
.I0(sel_0_IBUF_32),
.I1(B_4_IBUF_20),
.O(N8)
);
LUT6 #(
.INIT ( 64'hECCCEEEC64446664 ))
\GEN_CARRY_MUX[5].carry_mux/Mmux_pin<0><0>1 (
.I0(sel_2_IBUF_33),
.I1(sel_1_IBUF_35),
.I2(A_4_IBUF_4),
.I3(Cin[4]),
.I4(N8),
.I5(B_5_IBUF_21),
.O(Cin[5])
);
LUT2 #(
.INIT ( 4'h9 ))
\GEN_CARRY_MUX[6].carry_mux/Mmux_pin<0><0>1_SW0 (
.I0(sel_0_IBUF_32),
.I1(B_5_IBUF_21),
.O(N10)
);
LUT6 #(
.INIT ( 64'hECCCEEEC64446664 ))
\GEN_CARRY_MUX[6].carry_mux/Mmux_pin<0><0>1 (
.I0(sel_2_IBUF_33),
.I1(sel_1_IBUF_35),
.I2(A_5_IBUF_5),
.I3(Cin[5]),
.I4(N10),
.I5(B_6_IBUF_22),
.O(Cin[6])
);
LUT2 #(
.INIT ( 4'h9 ))
\GEN_CARRY_MUX[7].carry_mux/Mmux_pin<0><0>1_SW0 (
.I0(sel_0_IBUF_32),
.I1(B_6_IBUF_22),
.O(N12)
);
LUT6 #(
.INIT ( 64'hECCCEEEC64446664 ))
\GEN_CARRY_MUX[7].carry_mux/Mmux_pin<0><0>1 (
.I0(sel_2_IBUF_33),
.I1(sel_1_IBUF_35),
.I2(A_6_IBUF_6),
.I3(Cin[6]),
.I4(N12),
.I5(B_7_IBUF_23),
.O(Cin[7])
);
LUT2 #(
.INIT ( 4'h9 ))
\GEN_CARRY_MUX[8].carry_mux/Mmux_pin<0><0>1_SW0 (
.I0(sel_0_IBUF_32),
.I1(B_7_IBUF_23),
.O(N14)
);
LUT6 #(
.INIT ( 64'hECCCEEEC64446664 ))
\GEN_CARRY_MUX[8].carry_mux/Mmux_pin<0><0>1 (
.I0(sel_2_IBUF_33),
.I1(sel_1_IBUF_35),
.I2(A_7_IBUF_7),
.I3(Cin[7]),
.I4(N14),
.I5(B_8_IBUF_24),
.O(Cin[8])
);
LUT2 #(
.INIT ( 4'h9 ))
\GEN_CARRY_MUX[9].carry_mux/Mmux_pin<0><0>1_SW0 (
.I0(sel_0_IBUF_32),
.I1(B_8_IBUF_24),
.O(N16)
);
LUT6 #(
.INIT ( 64'hECCCEEEC64446664 ))
\GEN_CARRY_MUX[9].carry_mux/Mmux_pin<0><0>1 (
.I0(sel_2_IBUF_33),
.I1(sel_1_IBUF_35),
.I2(A_8_IBUF_8),
.I3(Cin[8]),
.I4(N16),
.I5(B_9_IBUF_25),
.O(Cin[9])
);
LUT2 #(
.INIT ( 4'h9 ))
\GEN_CARRY_MUX[10].carry_mux/Mmux_pin<0><0>1_SW0 (
.I0(sel_0_IBUF_32),
.I1(B_9_IBUF_25),
.O(N18)
);
LUT6 #(
.INIT ( 64'hECCCEEEC64446664 ))
\GEN_CARRY_MUX[10].carry_mux/Mmux_pin<0><0>1 (
.I0(sel_2_IBUF_33),
.I1(sel_1_IBUF_35),
.I2(A_9_IBUF_9),
.I3(Cin[9]),
.I4(N18),
.I5(B_10_IBUF_26),
.O(Cin[10])
);
LUT2 #(
.INIT ( 4'h9 ))
\GEN_CARRY_MUX[11].carry_mux/Mmux_pin<0><0>1_SW0 (
.I0(sel_0_IBUF_32),
.I1(B_10_IBUF_26),
.O(N20)
);
LUT6 #(
.INIT ( 64'hECCCEEEC64446664 ))
\GEN_CARRY_MUX[11].carry_mux/Mmux_pin<0><0>1 (
.I0(sel_2_IBUF_33),
.I1(sel_1_IBUF_35),
.I2(A_10_IBUF_10),
.I3(Cin[10]),
.I4(N20),
.I5(B_11_IBUF_27),
.O(Cin[11])
);
LUT2 #(
.INIT ( 4'h9 ))
\GEN_CARRY_MUX[12].carry_mux/Mmux_pin<0><0>1_SW0 (
.I0(sel_0_IBUF_32),
.I1(B_11_IBUF_27),
.O(N22)
);
LUT6 #(
.INIT ( 64'hECCCEEEC64446664 ))
\GEN_CARRY_MUX[12].carry_mux/Mmux_pin<0><0>1 (
.I0(sel_2_IBUF_33),
.I1(sel_1_IBUF_35),
.I2(A_11_IBUF_11),
.I3(Cin[11]),
.I4(N22),
.I5(B_12_IBUF_28),
.O(Cin[12])
);
LUT2 #(
.INIT ( 4'h9 ))
\GEN_CARRY_MUX[13].carry_mux/Mmux_pin<0><0>1_SW0 (
.I0(sel_0_IBUF_32),
.I1(B_12_IBUF_28),
.O(N24)
);
LUT6 #(
.INIT ( 64'hECCCEEEC64446664 ))
\GEN_CARRY_MUX[13].carry_mux/Mmux_pin<0><0>1 (
.I0(sel_2_IBUF_33),
.I1(sel_1_IBUF_35),
.I2(A_12_IBUF_12),
.I3(Cin[12]),
.I4(N24),
.I5(B_13_IBUF_29),
.O(Cin[13])
);
LUT2 #(
.INIT ( 4'h9 ))
\GEN_CARRY_MUX[14].carry_mux/Mmux_pin<0><0>1_SW0 (
.I0(sel_0_IBUF_32),
.I1(B_13_IBUF_29),
.O(N26)
);
LUT6 #(
.INIT ( 64'hECCCEEEC64446664 ))
\GEN_CARRY_MUX[14].carry_mux/Mmux_pin<0><0>1 (
.I0(sel_2_IBUF_33),
.I1(sel_1_IBUF_35),
.I2(A_13_IBUF_13),
.I3(Cin[13]),
.I4(N26),
.I5(B_14_IBUF_30),
.O(Cin[14])
);
LUT2 #(
.INIT ( 4'h9 ))
\GEN_CARRY_MUX[15].carry_mux/Mmux_pin<0><0>1_SW0 (
.I0(sel_0_IBUF_32),
.I1(B_14_IBUF_30),
.O(N28)
);
LUT6 #(
.INIT ( 64'hECCCEEEC64446664 ))
\GEN_CARRY_MUX[15].carry_mux/Mmux_pin<0><0>1 (
.I0(sel_2_IBUF_33),
.I1(sel_1_IBUF_35),
.I2(A_14_IBUF_14),
.I3(Cin[14]),
.I4(N28),
.I5(B_15_IBUF_31),
.O(Cin[15])
);
IBUF A_15_IBUF (
.I(A[15]),
.O(A_15_IBUF_15)
);
IBUF A_14_IBUF (
.I(A[14]),
.O(A_14_IBUF_14)
);
IBUF A_13_IBUF (
.I(A[13]),
.O(A_13_IBUF_13)
);
IBUF A_12_IBUF (
.I(A[12]),
.O(A_12_IBUF_12)
);
IBUF A_11_IBUF (
.I(A[11]),
.O(A_11_IBUF_11)
);
IBUF A_10_IBUF (
.I(A[10]),
.O(A_10_IBUF_10)
);
IBUF A_9_IBUF (
.I(A[9]),
.O(A_9_IBUF_9)
);
IBUF A_8_IBUF (
.I(A[8]),
.O(A_8_IBUF_8)
);
IBUF A_7_IBUF (
.I(A[7]),
.O(A_7_IBUF_7)
);
IBUF A_6_IBUF (
.I(A[6]),
.O(A_6_IBUF_6)
);
IBUF A_5_IBUF (
.I(A[5]),
.O(A_5_IBUF_5)
);
IBUF A_4_IBUF (
.I(A[4]),
.O(A_4_IBUF_4)
);
IBUF A_3_IBUF (
.I(A[3]),
.O(A_3_IBUF_3)
);
IBUF A_2_IBUF (
.I(A[2]),
.O(A_2_IBUF_2)
);
IBUF A_1_IBUF (
.I(A[1]),
.O(A_1_IBUF_1)
);
IBUF A_0_IBUF (
.I(A[0]),
.O(A_0_IBUF_0)
);
IBUF B_15_IBUF (
.I(B[15]),
.O(B_15_IBUF_31)
);
IBUF B_14_IBUF (
.I(B[14]),
.O(B_14_IBUF_30)
);
IBUF B_13_IBUF (
.I(B[13]),
.O(B_13_IBUF_29)
);
IBUF B_12_IBUF (
.I(B[12]),
.O(B_12_IBUF_28)
);
IBUF B_11_IBUF (
.I(B[11]),
.O(B_11_IBUF_27)
);
IBUF B_10_IBUF (
.I(B[10]),
.O(B_10_IBUF_26)
);
IBUF B_9_IBUF (
.I(B[9]),
.O(B_9_IBUF_25)
);
IBUF B_8_IBUF (
.I(B[8]),
.O(B_8_IBUF_24)
);
IBUF B_7_IBUF (
.I(B[7]),
.O(B_7_IBUF_23)
);
IBUF B_6_IBUF (
.I(B[6]),
.O(B_6_IBUF_22)
);
IBUF B_5_IBUF (
.I(B[5]),
.O(B_5_IBUF_21)
);
IBUF B_4_IBUF (
.I(B[4]),
.O(B_4_IBUF_20)
);
IBUF B_3_IBUF (
.I(B[3]),
.O(B_3_IBUF_19)
);
IBUF B_2_IBUF (
.I(B[2]),
.O(B_2_IBUF_18)
);
IBUF B_1_IBUF (
.I(B[1]),
.O(B_1_IBUF_17)
);
IBUF B_0_IBUF (
.I(B[0]),
.O(B_0_IBUF_16)
);
IBUF sel_3_IBUF (
.I(sel[3]),
.O(sel_3_IBUF_34)
);
IBUF sel_2_IBUF (
.I(sel[2]),
.O(sel_2_IBUF_33)
);
IBUF sel_1_IBUF (
.I(sel[1]),
.O(sel_1_IBUF_35)
);
IBUF sel_0_IBUF (
.I(sel[0]),
.O(sel_0_IBUF_32)
);
OBUF Y_15_OBUF (
.I(flags_7_OBUF_51),
.O(Y[15])
);
OBUF Y_14_OBUF (
.I(Y_14_OBUF_50),
.O(Y[14])
);
OBUF Y_13_OBUF (
.I(Y_13_OBUF_49),
.O(Y[13])
);
OBUF Y_12_OBUF (
.I(Y_12_OBUF_48),
.O(Y[12])
);
OBUF Y_11_OBUF (
.I(Y_11_OBUF_47),
.O(Y[11])
);
OBUF Y_10_OBUF (
.I(Y_10_OBUF_46),
.O(Y[10])
);
OBUF Y_9_OBUF (
.I(Y_9_OBUF_45),
.O(Y[9])
);
OBUF Y_8_OBUF (
.I(Y_8_OBUF_44),
.O(Y[8])
);
OBUF Y_7_OBUF (
.I(Y_7_OBUF_43),
.O(Y[7])
);
OBUF Y_6_OBUF (
.I(Y_6_OBUF_42),
.O(Y[6])
);
OBUF Y_5_OBUF (
.I(Y_5_OBUF_41),
.O(Y[5])
);
OBUF Y_4_OBUF (
.I(Y_4_OBUF_40),
.O(Y[4])
);
OBUF Y_3_OBUF (
.I(Y_3_OBUF_39),
.O(Y[3])
);
OBUF Y_2_OBUF (
.I(Y_2_OBUF_38),
.O(Y[2])
);
OBUF Y_1_OBUF (
.I(Y_1_OBUF_37),
.O(Y[1])
);
OBUF Y_0_OBUF (
.I(Y_0_OBUF_36),
.O(Y[0])
);
OBUF flags_15_OBUF (
.I(flags_1_OBUF_71),
.O(flags[15])
);
OBUF flags_14_OBUF (
.I(flags_1_OBUF_71),
.O(flags[14])
);
OBUF flags_13_OBUF (
.I(flags_1_OBUF_71),
.O(flags[13])
);
OBUF flags_12_OBUF (
.I(flags_1_OBUF_71),
.O(flags[12])
);
OBUF flags_11_OBUF (
.I(flags_1_OBUF_71),
.O(flags[11])
);
OBUF flags_10_OBUF (
.I(flags_1_OBUF_71),
.O(flags[10])
);
OBUF flags_9_OBUF (
.I(flags_1_OBUF_71),
.O(flags[9])
);
OBUF flags_8_OBUF (
.I(flags_1_OBUF_71),
.O(flags[8])
);
OBUF flags_7_OBUF (
.I(flags_7_OBUF_51),
.O(flags[7])
);
OBUF flags_6_OBUF (
.I(flags_6_OBUF_70),
.O(flags[6])
);
OBUF flags_5_OBUF (
.I(flags_5_OBUF_69),
.O(flags[5])
);
OBUF flags_4_OBUF (
.I(flags_1_OBUF_71),
.O(flags[4])
);
OBUF flags_3_OBUF (
.I(flags_1_OBUF_71),
.O(flags[3])
);
OBUF flags_2_OBUF (
.I(flags_2_OBUF_67),
.O(flags[2])
);
OBUF flags_1_OBUF (
.I(flags_1_OBUF_71),
.O(flags[1])
);
OBUF flags_0_OBUF (
.I(flags_0_OBUF_68),
.O(flags[0])
);
LUT5 #(
.INIT ( 32'h92E9E992 ))
\GEN_OUT_MUX[15].out_mux/Mmux_pin<0><0>11 (
.I0(Cin[15]),
.I1(sel_3_IBUF_34),
.I2(A_15_IBUF_15),
.I3(sel_0_IBUF_32),
.I4(B_15_IBUF_31),
.O(flags_7_OBUF_51)
);
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVN_M_V
`define SKY130_FD_SC_LP__EINVN_M_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvn_m (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvn_m (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVN_M_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__INV_8_V
`define SKY130_FD_SC_MS__INV_8_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__inv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__inv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__INV_8_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSTP_1_V
`define SKY130_FD_SC_LS__SDFSTP_1_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfstp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfstp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSTP_1_V
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// bcam_bhv.v: Behavioral description of binary CAM //
// //
// Author: Ameer M. S. Abdelhadi ( [email protected] ; [email protected] ) //
// SRAM-based Modular II-2D-BCAM ; The University of British Columbia , Sep. 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module bcam_bhv
#( parameter CDEP = 512, // CAM depth
parameter PWID = 32 , // CAM/pattern width
parameter INOM = 1 ) // binary / Initial CAM with no match (has priority over IFILE)
( input clk , // clock
input rst , // global registers reset
input wEnb , // write enable
input [`log2(CDEP)-1:0] wAddr , // write address
input [ PWID -1:0] wPatt , // write pattern
input [ PWID -1:0] mPatt , // patern to match
output reg match , // match indicator
output reg [`log2(CDEP)-1:0] mAddr ); // matched address
// assign memory array
reg [PWID-1:0] mem [0:CDEP-1];
// valid bit
reg [CDEP-1:0] vld;
// initialize memory, with zeros if INOM or file if IFILE.
integer i;
initial
if (INOM)
for (i=0; i<CDEP; i=i+1)
{vld[i],mem[i]} = {1'b0,{PWID{1'b0}}};
always @(posedge clk) begin
// write to memory
if (wEnb)
{vld[wAddr],mem[wAddr]} = {1'b1,wPatt};
// search memory
match = 0;
mAddr = 0;
match = (mem[mAddr]==mPatt) && vld[mAddr];
while ((!match) && (mAddr<(CDEP-1))) begin
mAddr=mAddr+1;
match = (mem[mAddr]==mPatt) && vld[mAddr];
end
end
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
// Date : Fri Jun 3 00:16:36 2016
// Host : Dries007-Arch running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/dries/Projects/Basys3/VGA_text/VGA_text.srcs/sources_1/ip/FrameBuffer/FrameBuffer_stub.v
// Design : FrameBuffer
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_1,Vivado 2015.4" *)
module FrameBuffer(clka, ena, wea, addra, dina, douta, clkb, web, addrb, dinb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[13:0],dina[7:0],douta[7:0],clkb,web[0:0],addrb[13:0],dinb[7:0],doutb[7:0]" */;
input clka;
input ena;
input [0:0]wea;
input [13:0]addra;
input [7:0]dina;
output [7:0]douta;
input clkb;
input [0:0]web;
input [13:0]addrb;
input [7:0]dinb;
output [7:0]doutb;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DFSTP_BEHAVIORAL_PP_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ms__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ms__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSTP_BEHAVIORAL_PP_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_dac_if (
rst,
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_a_p,
dac_data_out_a_n,
dac_data_out_b_p,
dac_data_out_b_n,
dac_div3_clk,
dds_data_00,
dds_data_01,
dds_data_02,
dds_data_03,
dds_data_04,
dds_data_05,
dds_data_06,
dds_data_07,
dds_data_08,
dds_data_09,
dds_data_10,
dds_data_11,
up_dds_enable,
up_dds_parity_type);
input rst;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [13:0] dac_data_out_a_p;
output [13:0] dac_data_out_a_n;
output [13:0] dac_data_out_b_p;
output [13:0] dac_data_out_b_n;
output dac_div3_clk;
input [13:0] dds_data_00;
input [13:0] dds_data_01;
input [13:0] dds_data_02;
input [13:0] dds_data_03;
input [13:0] dds_data_04;
input [13:0] dds_data_05;
input [13:0] dds_data_06;
input [13:0] dds_data_07;
input [13:0] dds_data_08;
input [13:0] dds_data_09;
input [13:0] dds_data_10;
input [13:0] dds_data_11;
input up_dds_enable;
input up_dds_parity_type;
reg [ 5:0] dds_data_a[13:0];
reg [ 5:0] dds_data_b[13:0];
reg dds_parity_type_m1 = 'd0;
reg dds_parity_type = 'd0;
reg [ 5:0] dds_parity = 'd0;
wire dac_clk_in_s;
wire dac_clk_out_s;
wire dac_frame_out_s;
wire [13:0] dac_data_out_a_s;
wire [13:0] dac_data_out_b_s;
wire serdes_preset_s;
wire serdes_rst_s;
wire dac_clk;
wire dac_div3_clk_s;
always @(posedge dac_div3_clk) begin
dds_data_a[13] <= {dds_data_10[13], dds_data_08[13], dds_data_06[13],
dds_data_04[13], dds_data_02[13], dds_data_00[13]};
dds_data_a[12] <= {dds_data_10[12], dds_data_08[12], dds_data_06[12],
dds_data_04[12], dds_data_02[12], dds_data_00[12]};
dds_data_a[11] <= {dds_data_10[11], dds_data_08[11], dds_data_06[11],
dds_data_04[11], dds_data_02[11], dds_data_00[11]};
dds_data_a[10] <= {dds_data_10[10], dds_data_08[10], dds_data_06[10],
dds_data_04[10], dds_data_02[10], dds_data_00[10]};
dds_data_a[ 9] <= {dds_data_10[ 9], dds_data_08[ 9], dds_data_06[ 9],
dds_data_04[ 9], dds_data_02[ 9], dds_data_00[ 9]};
dds_data_a[ 8] <= {dds_data_10[ 8], dds_data_08[ 8], dds_data_06[ 8],
dds_data_04[ 8], dds_data_02[ 8], dds_data_00[ 8]};
dds_data_a[ 7] <= {dds_data_10[ 7], dds_data_08[ 7], dds_data_06[ 7],
dds_data_04[ 7], dds_data_02[ 7], dds_data_00[ 7]};
dds_data_a[ 6] <= {dds_data_10[ 6], dds_data_08[ 6], dds_data_06[ 6],
dds_data_04[ 6], dds_data_02[ 6], dds_data_00[ 6]};
dds_data_a[ 5] <= {dds_data_10[ 5], dds_data_08[ 5], dds_data_06[ 5],
dds_data_04[ 5], dds_data_02[ 5], dds_data_00[ 5]};
dds_data_a[ 4] <= {dds_data_10[ 4], dds_data_08[ 4], dds_data_06[ 4],
dds_data_04[ 4], dds_data_02[ 4], dds_data_00[ 4]};
dds_data_a[ 3] <= {dds_data_10[ 3], dds_data_08[ 3], dds_data_06[ 3],
dds_data_04[ 3], dds_data_02[ 3], dds_data_00[ 3]};
dds_data_a[ 2] <= {dds_data_10[ 2], dds_data_08[ 2], dds_data_06[ 2],
dds_data_04[ 2], dds_data_02[ 2], dds_data_00[ 2]};
dds_data_a[ 1] <= {dds_data_10[ 1], dds_data_08[ 1], dds_data_06[ 1],
dds_data_04[ 1], dds_data_02[ 1], dds_data_00[ 1]};
dds_data_a[ 0] <= {dds_data_10[ 0], dds_data_08[ 0], dds_data_06[ 0],
dds_data_04[ 0], dds_data_02[ 0], dds_data_00[ 0]};
dds_data_b[13] <= {dds_data_11[13], dds_data_09[13], dds_data_07[13],
dds_data_05[13], dds_data_03[13], dds_data_01[13]};
dds_data_b[12] <= {dds_data_11[12], dds_data_09[12], dds_data_07[12],
dds_data_05[12], dds_data_03[12], dds_data_01[12]};
dds_data_b[11] <= {dds_data_11[11], dds_data_09[11], dds_data_07[11],
dds_data_05[11], dds_data_03[11], dds_data_01[11]};
dds_data_b[10] <= {dds_data_11[10], dds_data_09[10], dds_data_07[10],
dds_data_05[10], dds_data_03[10], dds_data_01[10]};
dds_data_b[ 9] <= {dds_data_11[ 9], dds_data_09[ 9], dds_data_07[ 9],
dds_data_05[ 9], dds_data_03[ 9], dds_data_01[ 9]};
dds_data_b[ 8] <= {dds_data_11[ 8], dds_data_09[ 8], dds_data_07[ 8],
dds_data_05[ 8], dds_data_03[ 8], dds_data_01[ 8]};
dds_data_b[ 7] <= {dds_data_11[ 7], dds_data_09[ 7], dds_data_07[ 7],
dds_data_05[ 7], dds_data_03[ 7], dds_data_01[ 7]};
dds_data_b[ 6] <= {dds_data_11[ 6], dds_data_09[ 6], dds_data_07[ 6],
dds_data_05[ 6], dds_data_03[ 6], dds_data_01[ 6]};
dds_data_b[ 5] <= {dds_data_11[ 5], dds_data_09[ 5], dds_data_07[ 5],
dds_data_05[ 5], dds_data_03[ 5], dds_data_01[ 5]};
dds_data_b[ 4] <= {dds_data_11[ 4], dds_data_09[ 4], dds_data_07[ 4],
dds_data_05[ 4], dds_data_03[ 4], dds_data_01[ 4]};
dds_data_b[ 3] <= {dds_data_11[ 3], dds_data_09[ 3], dds_data_07[ 3],
dds_data_05[ 3], dds_data_03[ 3], dds_data_01[ 3]};
dds_data_b[ 2] <= {dds_data_11[ 2], dds_data_09[ 2], dds_data_07[ 2],
dds_data_05[ 2], dds_data_03[ 2], dds_data_01[ 2]};
dds_data_b[ 1] <= {dds_data_11[ 1], dds_data_09[ 1], dds_data_07[ 1],
dds_data_05[ 1], dds_data_03[ 1], dds_data_01[ 1]};
dds_data_b[ 0] <= {dds_data_11[ 0], dds_data_09[ 0], dds_data_07[ 0],
dds_data_05[ 0], dds_data_03[ 0], dds_data_01[ 0]};
end
always @(posedge dac_div3_clk) begin
dds_parity_type_m1 <= up_dds_parity_type;
dds_parity_type <= dds_parity_type_m1;
dds_parity[5] <= (^(dds_data_11 ^ dds_data_10)) ^ dds_parity_type;
dds_parity[4] <= (^(dds_data_09 ^ dds_data_08)) ^ dds_parity_type;
dds_parity[3] <= (^(dds_data_07 ^ dds_data_06)) ^ dds_parity_type;
dds_parity[2] <= (^(dds_data_05 ^ dds_data_04)) ^ dds_parity_type;
dds_parity[1] <= (^(dds_data_03 ^ dds_data_02)) ^ dds_parity_type;
dds_parity[0] <= (^(dds_data_01 ^ dds_data_00)) ^ dds_parity_type;
end
assign serdes_preset_s = rst | ~up_dds_enable;
FDPE #(.INIT(1'b1)) i_serdes_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (serdes_preset_s),
.C (dac_div3_clk),
.Q (serdes_rst_s));
// dac data output serdes(s) & buffers
genvar l_inst;
generate
for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin: g_dac_data
OSERDESE1 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (6),
.INTERFACE_TYPE ("DEFAULT"),
.TRISTATE_WIDTH (1),
.SERDES_MODE ("MASTER"))
i_dac_data_out_a_oserdes (
.D1 (dds_data_a[l_inst][0]),
.D2 (dds_data_a[l_inst][1]),
.D3 (dds_data_a[l_inst][2]),
.D4 (dds_data_a[l_inst][3]),
.D5 (dds_data_a[l_inst][4]),
.D6 (dds_data_a[l_inst][5]),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.OCE (1'b1),
.CLK (dac_clk),
.CLKDIV (dac_div3_clk),
.CLKPERF (1'b0),
.CLKPERFDELAY (1'b0),
.WC (1'b0),
.ODV (1'b0),
.OQ (dac_data_out_a_s[l_inst]),
.TQ (),
.OCBEXTEND (),
.OFB (),
.TFB (),
.TCE (1'b0),
.RST (serdes_rst_s));
OBUFDS #(
.IOSTANDARD ("LVDS_25"))
i_dac_data_out_a_buf (
.I (dac_data_out_a_s[l_inst]),
.O (dac_data_out_a_p[l_inst]),
.OB (dac_data_out_a_n[l_inst]));
OSERDESE1 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (6),
.INTERFACE_TYPE ("DEFAULT"),
.TRISTATE_WIDTH (1),
.SERDES_MODE ("MASTER"))
i_dac_data_out_b_oserdes (
.D1 (dds_data_b[l_inst][0]),
.D2 (dds_data_b[l_inst][1]),
.D3 (dds_data_b[l_inst][2]),
.D4 (dds_data_b[l_inst][3]),
.D5 (dds_data_b[l_inst][4]),
.D6 (dds_data_b[l_inst][5]),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.OCE (1'b1),
.CLK (dac_clk),
.CLKDIV (dac_div3_clk),
.CLKPERF (1'b0),
.CLKPERFDELAY (1'b0),
.WC (1'b0),
.ODV (1'b0),
.OQ (dac_data_out_b_s[l_inst]),
.TQ (),
.OCBEXTEND (),
.OFB (),
.TFB (),
.TCE (1'b0),
.RST (serdes_rst_s));
OBUFDS #(
.IOSTANDARD ("LVDS_25"))
i_dac_data_out_b_buf (
.I (dac_data_out_b_s[l_inst]),
.O (dac_data_out_b_p[l_inst]),
.OB (dac_data_out_b_n[l_inst]));
end
endgenerate
// dac parity output
OSERDESE1 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (6),
.INTERFACE_TYPE ("DEFAULT"),
.TRISTATE_WIDTH (1),
.SERDES_MODE ("MASTER"))
i_dac_frame_out_oserdes (
.D1 (dds_parity[0]),
.D2 (dds_parity[1]),
.D3 (dds_parity[2]),
.D4 (dds_parity[3]),
.D5 (dds_parity[4]),
.D6 (dds_parity[5]),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.OCE (1'b1),
.CLK (dac_clk),
.CLKDIV (dac_div3_clk),
.CLKPERF (1'b0),
.CLKPERFDELAY (1'b0),
.WC (1'b0),
.ODV (1'b0),
.OQ (dac_frame_out_s),
.TQ (),
.OCBEXTEND (),
.OFB (),
.TFB (),
.TCE (1'b0),
.RST (serdes_rst_s));
OBUFDS #(
.IOSTANDARD ("LVDS_25"))
i_dac_frame_out_buf (
.I (dac_frame_out_s),
.O (dac_frame_out_p),
.OB (dac_frame_out_n));
// dac clock output serdes & buffer
OSERDESE1 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (6),
.INTERFACE_TYPE ("DEFAULT"),
.TRISTATE_WIDTH (1),
.SERDES_MODE ("MASTER"))
i_dac_clk_out_oserdes (
.D1 (1'b0),
.D2 (1'b1),
.D3 (1'b0),
.D4 (1'b1),
.D5 (1'b0),
.D6 (1'b1),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.OCE (1'b1),
.CLK (dac_clk),
.CLKDIV (dac_div3_clk),
.CLKPERF (1'b0),
.CLKPERFDELAY (1'b0),
.WC (1'b0),
.ODV (1'b0),
.OQ (dac_clk_out_s),
.TQ (),
.OCBEXTEND (),
.OFB (),
.TFB (),
.TCE (1'b0),
.RST (serdes_rst_s));
OBUFDS #(
.IOSTANDARD ("LVDS_25"))
i_dac_clk_out_obuf (
.I (dac_clk_out_s),
.O (dac_clk_out_p),
.OB (dac_clk_out_n));
// dac clock input buffers
IBUFGDS #(
.IOSTANDARD ("LVDS_25"))
i_dac_clk_in_ibuf (
.I (dac_clk_in_p),
.IB (dac_clk_in_n),
.O (dac_clk_in_s));
BUFG i_dac_clk_in_gbuf (
.I (dac_clk_in_s),
.O (dac_clk));
BUFR #(
.SIM_DEVICE("VIRTEX6"),
.BUFR_DIVIDE("3"))
i_dac_div3_clk_rbuf (
.CLR (1'b0),
.CE (1'b1),
.I (dac_clk),
.O (dac_div3_clk_s));
BUFG i_dac_div3_clk_gbuf (
.I (dac_div3_clk_s),
.O (dac_div3_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1491173393 : 0;
endmodule
|
Set Implicit Arguments.
Require Import FunctionalExtensionality.
Require Import DblibTactics.
Require Import DeBruijn.
Require Import Lia.
(* ---------------------------------------------------------------------------- *)
(* Environments map variables to data. *)
(* Environments are homogeneous -- there is only one kind of variables --
and non-dependent -- variables do not occur within data. *)
(* We represent environments as functions of type [nat -> option A], as
opposed to lists of type [list A], because functions are slightly more
pleasant to work with than lists. In particular, their domain need not
be contiguous, and this makes the definition of insertion more natural. *)
Definition env A :=
nat -> option A.
(* ---------------------------------------------------------------------------- *)
(* Operations on environments. *)
(* The empty environment is undefined everywhere. *)
Definition empty A : env A :=
fun y => None.
(* Environment lookup is just function application. *)
Definition lookup A (x : nat) (e : env A) : option A :=
e x.
(* [insert x a e] inserts a new variable [x], associated with data [a], in the
environment [e]. The pre-existing environment entries at index [x] and
above are shifted up. Thus, [insert x] is closely analogous to [shift x]
for terms. *)
Definition insert A (x : nat) (a : A) (e : env A) : env A :=
fun y =>
match lt_eq_lt_dec x y with
| inleft (left _) (* x < y *) => e (y - 1)
| inleft (right _) (* x = y *) => Some a
| inright _ (* x > y *) => e y
end.
(* [remove x] is the inverse of [insert x a]. That is, [remove x e] destroys
the variable [x] in the environment [e]. The variables at index [x + 1]
and above are shifted down. Thus, [remove x] is closely analogous to
[subst v x] for terms. *)
(* Experience suggests that it is good style to always work with [insert]
and avoid using [remove]. This leads to simpler goals and proofs. *)
Definition remove A (x : nat) (e : env A) : env A :=
fun y =>
match le_gt_dec x y with
| left _ (* x <= y *) => e (1 + y)
| right _ (* x > y *) => e y
end.
(* [map f e] is the environment obtained by applying [f] to every datum
in the environment [e]. *)
Definition map A (f : A -> A) (e : env A) :=
fun y =>
match e y with
| None => None
| Some a => Some (f a)
end.
(* ---------------------------------------------------------------------------- *)
(* Basic arithmetic simplifications. *)
Lemma one_plus_x_minus_one_left:
forall x,
(1 + x) - 1 = x.
Proof.
intros. lia.
Qed.
Lemma one_plus_x_minus_one_right:
forall x,
x > 0 ->
1 + (x - 1) = x.
Proof.
intros. lia.
Qed.
Ltac one_plus_x_minus_one :=
repeat rewrite one_plus_x_minus_one_left;
repeat rewrite one_plus_x_minus_one_right by lia.
(* I tried [autorewrite with ... using lia]; it does not work. *)
(* ---------------------------------------------------------------------------- *)
(* Interaction between [lookup] and [empty]. *)
Lemma lookup_empty_None:
forall A x,
lookup x (@empty A) = None.
Proof.
unfold lookup, empty. reflexivity.
Qed.
Lemma lookup_empty_Some:
forall A x (a : A),
lookup x (@empty _) = Some a ->
False.
Proof.
unfold lookup, empty. intros. congruence.
Qed.
(* ---------------------------------------------------------------------------- *)
(* Interaction between [lookup] and [insert]. *)
Lemma lookup_insert_bingo:
forall A x y (a : A) e,
x = y ->
lookup x (insert y a e) = Some a.
Proof.
intros. subst. unfold lookup, insert. dblib_by_cases. reflexivity.
Qed.
Lemma lookup_insert_recent:
forall A x y (a : A) e,
x < y ->
lookup x (insert y a e) = lookup x e.
Proof.
intros. unfold lookup, insert. dblib_by_cases. reflexivity.
Qed.
Lemma lookup_insert_old:
forall A x y (a : A) e,
x > y ->
lookup x (insert y a e) = lookup (x - 1) e.
Proof.
intros. unfold lookup, insert. dblib_by_cases. reflexivity.
Qed.
Lemma lookup_shift_insert:
forall A x y (a : A) e,
lookup (shift y x) (insert y a e) = lookup x e.
Proof.
intros. destruct_lift_idx.
rewrite lookup_insert_old by lia. f_equal. lia.
rewrite lookup_insert_recent by lia. reflexivity.
Qed.
Ltac lookup_insert :=
first [
rewrite lookup_insert_bingo by lia
| rewrite lookup_insert_old by lia; one_plus_x_minus_one
| rewrite lookup_insert_recent by lia
| rewrite lookup_shift_insert
].
Ltac lookup_insert_all :=
first [
rewrite lookup_insert_bingo in * by lia
| rewrite lookup_insert_old in * by lia; one_plus_x_minus_one
| rewrite lookup_insert_recent in * by lia
| rewrite lookup_shift_insert in *
].
Hint Extern 1 (lookup _ (insert _ _ _) = _) =>
lookup_insert
: lookup_insert.
Hint Extern 1 (lookup _ _ = _) =>
lookup_insert_all
: lookup_insert.
(* ---------------------------------------------------------------------------- *)
(* Interaction between [lookup] and [map]. *)
Lemma lookup_map_some:
forall A x (a : A) e f,
lookup x e = Some a ->
lookup x (map f e) = Some (f a).
Proof.
unfold lookup, map. intros. case_eq (e x); intros; congruence.
Qed.
(* ---------------------------------------------------------------------------- *)
(* [insert] commutes itself, just like [lift] commutes with itself. *)
Lemma insert_insert:
forall A k s (a b : A) e,
k <= s ->
insert k a (insert s b e) = insert (1 + s) b (insert k a e).
Proof.
unfold insert. intros. extensionality y. dblib_by_cases; eauto with f_equal lia.
Qed.
(* Attempting to rewrite in both directions may seem redundant, because of the
symmetry of the law [insert_insert]. It is not: because [lia] fails in
the presence of meta-variables, rewriting in one direction may be possible
while the other direction fails. *)
Ltac insert_insert :=
first [
rewrite insert_insert by lia; reflexivity
| rewrite <- insert_insert by lia; reflexivity
].
Hint Extern 1 (insert _ _ (insert _ _ _) = _) =>
insert_insert
: insert_insert.
Hint Extern 1 (_ = insert _ _ (insert _ _ _)) =>
insert_insert
: insert_insert.
(* ---------------------------------------------------------------------------- *)
(* Interaction between [remove] and [insert]. *)
Lemma remove_insert:
forall A x (a : A) e,
remove x (insert x a e) = e.
Proof.
intros. unfold remove, insert. extensionality y.
dblib_by_cases; eauto with f_equal lia.
Qed.
Lemma insert_remove_bingo:
forall A x y (a : A) e,
lookup x e = Some a ->
y = x ->
insert y a (remove x e) = e.
Proof.
unfold lookup, remove, insert. intros. extensionality z.
dblib_by_cases; eauto with f_equal lia; congruence.
Qed.
Lemma insert_remove_recent:
forall A x y (a : A) e,
y <= x ->
insert y a (remove x e) = remove (1 + x) (insert y a e).
Proof.
intros. unfold insert, remove. extensionality z.
dblib_by_cases; eauto with f_equal lia.
Qed.
Lemma insert_remove_old:
forall A x y (a : A) e,
y >= x ->
insert y a (remove x e) = remove x (insert (1 + y) a e).
Proof.
intros. unfold insert, remove. extensionality z.
dblib_by_cases; eauto with f_equal lia.
Qed.
Ltac insert_remove :=
first [
rewrite insert_remove_recent by lia; reflexivity
| rewrite insert_remove_old by lia; reflexivity
| rewrite <- insert_remove_recent by lia; reflexivity
| rewrite <- insert_remove_old by lia; reflexivity
].
Hint Extern 1 (remove _ (insert _ _ _) = insert _ _ (remove _ _)) =>
insert_remove
: insert_remove.
Hint Extern 1 (insert _ _ (remove _ _)= remove _ (insert _ _ _) ) =>
insert_remove
: insert_remove.
(* ---------------------------------------------------------------------------- *)
(* Interaction between [lookup] and [remove]. *)
Lemma lookup_remove:
forall A x y (e : env A),
lookup y (remove x e) = lookup (shift x y) e.
Proof.
intros. unfold lookup, remove. destruct_lift_idx; reflexivity.
Qed.
Lemma lookup_remove_old:
forall A x y (e : env A),
y >= x ->
lookup y (remove x e) = lookup (1 + y) e.
Proof.
intros. unfold lookup, remove. dblib_by_cases; eauto with f_equal lia.
Qed.
Lemma lookup_remove_recent:
forall A x y (e : env A),
y < x ->
lookup y (remove x e) = lookup y e.
Proof.
intros. unfold lookup, remove. dblib_by_cases; eauto with f_equal lia.
Qed.
Ltac lookup_remove :=
first [
rewrite lookup_remove_old by lia; one_plus_x_minus_one
| rewrite lookup_remove_recent by lia
].
Hint Extern 1 (lookup _ (remove _ _) = _) =>
lookup_remove
: lookup_remove.
(* ---------------------------------------------------------------------------- *)
(* Interaction between [map] and [insert]. *)
Lemma map_insert:
forall A f x (a : A) e,
map f (insert x a e) = insert x (f a) (map f e).
Proof.
unfold map, insert. intros. extensionality y. dblib_by_cases; eauto with f_equal lia.
Qed.
Ltac map_insert :=
first [
rewrite map_insert; reflexivity
| rewrite <- map_insert; reflexivity
].
Hint Extern 1 (map _ (insert _ _ _) = insert _ _ (map _ _)) =>
map_insert
: map_insert.
Hint Extern 1 (insert _ _ (map _ _) = map _ (insert _ _ _)) =>
map_insert
: map_insert.
(* ---------------------------------------------------------------------------- *)
(* [map] composes with itself. *)
Lemma map_map_fuse:
forall A f g h e,
(forall (d : A), f (g d) = h d) ->
map f (map g e) = map h e.
Proof.
intros. unfold map. extensionality y. case_eq (e y); congruence.
Qed.
Lemma map_map_exchange:
forall A f1 f2 g1 g2 e,
(forall (d : A), f1 (f2 d) = g1 (g2 d)) ->
map f1 (map f2 e) = map g1 (map g2 e).
Proof.
intros. unfold map. extensionality y. case_eq (e y); congruence.
Qed.
Lemma map_lift_map_lift:
forall T k s wk ws (e : env T),
forall `{Lift T},
@LiftLift T _ ->
k <= s ->
map (lift wk k) (map (lift ws s) e) = map (lift ws (wk + s)) (map (lift wk k) e).
Proof.
eauto using map_map_exchange, @lift_lift.
Qed.
Lemma map_map_vanish:
forall A f g (e : env A),
(forall x, f (g x) = x) ->
map f (map g e) = e.
Proof.
intros. unfold map. extensionality y. case_eq (e y); congruence.
Qed.
(* ---------------------------------------------------------------------------- *)
(* A definition of (an upper bound on) the length of an environment. *)
Definition length A (e : env A) (k : nat) :=
forall x,
k <= x ->
lookup x e = None.
(* Every variable that is defined in the environment is less than the
length of the environment. *)
Lemma defined_implies_below_length:
forall A (e : env A) x k a,
length e k ->
lookup x e = Some a ->
x < k.
Proof.
intros.
(* If [x < k] holds, the result is immediate. Consider the other case,
[k <= x]. *)
case (le_gt_dec k x); intro; try tauto.
(* By definition of [length], [lookup x e] is [None]. *)
assert (lookup x e = None). auto.
(* We obtain a contradiction. *)
congruence.
Qed.
Hint Resolve defined_implies_below_length : lift_idx_hints.
(* The empty environment has zero length. *)
Lemma length_empty:
forall A k,
length (@empty A) k.
Proof.
repeat intro. apply lookup_empty_None.
Qed.
(* Extending an environment increments its length by one. *)
Lemma length_insert:
forall A (e : env A) k a,
length e k ->
length (insert 0 a e) (1 + k).
Proof.
unfold length; intros. lookup_insert. eauto with lia.
Qed.
Hint Resolve length_empty length_insert : length.
Hint Resolve length_insert : construction_closed.
(* ---------------------------------------------------------------------------- *)
(* A definition of when two environments agree up to length [k]. *)
Definition agree A (e1 e2 : env A) (k : nat) :=
forall x,
x < k ->
lookup x e1 = lookup x e2.
(* A simple consequence of the definition. *)
Lemma agree_below:
forall A (e1 e2 : env A) x a k,
lookup x e1 = Some a ->
length e1 k ->
agree e1 e2 k ->
lookup x e2 = Some a.
Proof.
do 6 intro. intros hlookup ? ?.
rewrite <- hlookup. symmetry.
eauto using defined_implies_below_length.
Qed.
(* The empty environment agrees with every environment up to length [0]. *)
Lemma agree_empty:
forall A (e : env A),
agree (@empty _) e 0.
Proof.
unfold agree. intros. elimtype False. lia.
Qed.
(* If two environments that agree up to [k] are extended with a new variable,
then they agree up to [k+1]. *)
Lemma agree_insert:
forall A (e1 e2 : env A) k,
agree e1 e2 k ->
forall x a,
x <= k ->
agree (insert x a e1) (insert x a e2) (1 + k).
Proof.
unfold agree, lookup, insert. intros. dblib_by_cases; eauto with lia.
Qed.
Hint Resolve agree_below agree_empty agree_insert : agree.
(* ---------------------------------------------------------------------------- *)
(* Extending an environment with a list of bindings found in a pattern. *)
(* Note that we cannot define the concatenation of two environments, because
we view environments as functions, so we do not have precise control over
their domain. Only a list has finite domain. *)
(* Concatenation is just an iterated version of [insert 0]. *)
Fixpoint concat (A : Type) (e1 : env A) (e2 : list A) : env A :=
match e2 with
| nil =>
e1
| cons a e2 =>
concat (insert 0 a e1) e2
end.
(* Concatenation acts upon the length of the environment in an obvious
manner. *)
Lemma length_concat:
forall A (e2 : list A) (e1 : env A) n1 n,
length e1 n1 ->
n1 + List.length e2 = n ->
length (concat e1 e2) n.
Proof.
induction e2; simpl; intros.
replace n with n1 by lia. assumption.
eauto using length_insert with lia.
Qed.
Hint Resolve length_concat : length construction_closed.
(* If [e1] and [e2] agree up to depth [k], then, after extending them
with a common suffix [e], they agree up to depth [k + length e]. *)
Lemma agree_concat:
forall A (e : list A) (e1 e2 : env A) k n,
agree e1 e2 k ->
k + List.length e = n ->
agree (concat e1 e) (concat e2 e) n.
Proof.
induction e; simpl; intros.
replace n with k by lia. assumption.
eauto using agree_insert with lia.
Qed.
Hint Resolve agree_concat : agree.
(* Concatenation and insertion commute. *)
Lemma insert_concat:
forall (A : Type) n x nx (a : A) e1 e2,
List.length e2 = n ->
n + x = nx ->
insert nx a (concat e1 e2) = concat (insert x a e1) e2.
Proof.
induction n; intros; subst; destruct e2; simpl in *; try discriminate; auto.
rewrite insert_insert by lia.
erewrite <- (IHn (1 + x)) by first [ congruence | eauto ].
eauto with f_equal lia.
Qed.
(* [replicate n a] is a list of [n] elements, all of which are
equal to [a]. *)
Fixpoint replicate (A : Type) (n : nat) (a : A) : list A :=
match n with
| 0 =>
@nil _
| S n =>
cons a (replicate n a)
end.
(* The list [replicate n a] has length [n]. *)
Lemma length_replicate:
forall (A : Type) n (a : A),
List.length (replicate n a) = n.
Proof.
induction n; simpl; auto.
Qed.
(* A special case of [insert_concat]. *)
Lemma insert_concat_replicate:
forall (A : Type) n x nx (a b : A) e1,
n + x = nx ->
insert nx a (concat e1 (replicate n b)) = concat (insert x a e1) (replicate n b).
Proof.
eauto using insert_concat, length_replicate.
Qed.
(* [concat . (replicate . a)] is just an iterated version of [insert . a]. *)
Lemma concat_replicate_is_iterated_insert:
forall (A : Type) n (a : A) e,
insert n a (concat e (replicate n a)) =
concat e (replicate (S n) a).
Proof.
intros. simpl. eauto using insert_concat, length_replicate.
Qed.
Hint Resolve insert_concat length_replicate insert_concat_replicate
concat_replicate_is_iterated_insert : insert_concat.
(* A special case of [length_concat]. *)
Lemma length_concat_replicate:
forall A (a : A) (e1 : env A) n1 n2 n,
length e1 n1 ->
n1 + n2 = n ->
length (concat e1 (replicate n2 a)) n.
Proof.
intros. eapply length_concat. eauto. rewrite length_replicate. eauto.
Qed.
Hint Resolve length_concat_replicate : length construction_closed.
(* ---------------------------------------------------------------------------- *)
(* Make some definitions opaque, so that Coq does not over-simplify in
unexpected (and fragile) ways. *)
Global Opaque empty lookup insert remove map.
|
/***********************************************************************************************************************
* *
* ANTIKERNEL v0.1 *
* *
* Copyright(c) 2012-2017 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
*(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
*(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/
/**
@file
@author Andrew D. Zonenberg
@brief Low-level wrapper for the Xilinx Zynq
*/
module XilinxZynq7CPU(
//EMIO JTAG pins for the CPU
//Useful for debugging the CPU from the FPGA or just breaking them out to GPIOs
output wire cpu_jtag_tdo,
input wire cpu_jtag_tdi,
input wire cpu_jtag_tms,
input wire cpu_jtag_tck,
//Note that these pins are INPUTS.
//The multiple-driver warning is a false positive (see AR#50430).
//The __nowarn_528_ prefix will make Splash filter it out
inout wire __nowarn_528_cpu_clk,
inout wire __nowarn_528_cpu_por_n,
inout wire __nowarn_528_cpu_srst_n
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Unused signals (tied off to default values now to avoid warnings, not yet brought out to top level)
//Clocks from CPU PLL to FPGA, plus associated resets
wire[3:0] fabric_clock_unbuffered;
wire[3:0] async_cpu_reset_complete;
//FPGA to CoreSight bridge signals
wire[31:0] cpu_to_fpga_debug_gpioreg;
wire[31:0] fpga_to_cpu_debug_gpioreg = 32'h0;
wire[3:0] cpu_to_fpga_trace_trigger;
wire[3:0] cpu_to_fpga_trace_ack = cpu_to_fpga_trace_trigger;
wire[3:0] fpga_to_cpu_trace_trigger = 4'h0;
wire[3:0] fpga_to_cpu_trace_ack;
wire fpga_trace_clk = 1'h0;
wire fpga_trace_valid = 1'h0;
wire[31:0] fpga_trace_data = 32'h0;
wire[3:0] fpga_trace_id = 4'h0;
//CPU trace signals
wire trace_clk = 1'h0;
wire trace_ctl;
wire[31:0] trace_data;
//System watchdog timer
wire watchdog_clk = 1'h0;
wire watchdog_reset_out;
//CPU events
wire cpu_event_req = 1'h0;
wire cpu_event_ack;
wire[1:0] cpu_waiting_for_event;
wire[1:0] cpu_waiting_for_irq;
//CPU interrupts
wire[15:0] fpga_to_cpu_irq = 16'h0;
wire[1:0] cpu_fiq_n = 2'h3;
wire[1:0] cpu_irq_n = 2'h3;
wire[28:0] cpu_to_fpga_irq; //copies of IRQs from various peripherals
/*{
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC7,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC0,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1
} */
//DMA channels
wire[3:0] dma_rst_n;
wire[3:0] dma_clk = 4'h0;
wire[3:0] dma_req_ready;
wire[3:0] dma_req_valid = 4'h0;
wire[7:0] dma_req_type = 8'h0;
wire[3:0] dma_req_last = 4'h0;
wire[3:0] dma_ack_ready = 4'h0;
wire[3:0] dma_ack_valid;
wire[7:0] dma_ack_type;
//CAN interfaces
wire[1:0] can_phy_rx = 2'h0;
wire[1:0] can_phy_tx;
//Ethernet interfaces: data/control
wire[1:0] eth_ext_int = 2'h0;
wire[1:0] eth_gmii_txc = 2'h0; //we have to externally mux the tx clock!
wire[1:0] eth_gmii_tx_en;
wire[1:0] eth_gmii_tx_er;
wire[15:0] eth_gmii_txd;
wire[1:0] eth_gmii_rxc = 2'h0;
wire[1:0] eth_gmii_rx_dv = 2'h0;
wire[1:0] eth_gmii_rx_er = 2'h0;
wire[15:0] eth_gmii_rxd = 16'h0;
wire[1:0] eth_gmii_rx_col = 2'h0;
wire[1:0] eth_gmii_rx_crs = 2'h0;
wire[1:0] eth_mgmt_mdio_out;
wire[1:0] eth_mgmt_mdio_tris;
wire[1:0] eth_mgmt_mdio_in = 2'h0;
wire[1:0] eth_mgmt_mdc;
//Ethernet interfaces: PTP timestamping
wire[1:0] eth_ptp_rx_sof;
wire[1:0] eth_ptp_rx_ptp_delay_req;
wire[1:0] eth_ptp_rx_ptp_peer_delay;
wire[1:0] eth_ptp_rx_ptp_peer_delay_resp;
wire[1:0] eth_ptp_rx_ptp_sync;
wire[1:0] eth_ptp_tx_sof;
wire[1:0] eth_ptp_tx_ptp_delay_req;
wire[1:0] eth_ptp_tx_ptp_peer_delay;
wire[1:0] eth_ptp_tx_ptp_peer_delay_resp;
wire[1:0] eth_ptp_tx_ptp_sync;
//GPIO interfaces
wire[63:0] gpio_in = 64'h0;
wire[63:0] gpio_out;
wire[63:0] gpio_tris;
//I2C interfaces
wire[1:0] i2c_scl_in = 2'h0;
wire[1:0] i2c_scl_out;
wire[1:0] i2c_scl_tris;
wire[1:0] i2c_sda_in = 2'h0;
wire[1:0] i2c_sda_out;
wire[1:0] i2c_sda_tris;
//SD/SDIO interfaces
wire[1:0] sdio_clk;
wire[1:0] sdio_clkfb = sdio_clk;
wire[1:0] sdio_cmd_in = 2'h0;
wire[1:0] sdio_cmd_out;
wire[1:0] sdio_cmd_tris;
wire[7:0] sdio_data_in = 8'h0;
wire[7:0] sdio_data_out;
wire[7:0] sdio_data_tris;
wire[1:0] sdio_card_detect = 2'h0;
wire[1:0] sdio_write_protect = 2'h0;
wire[1:0] sdio_power_en;
wire[1:0] sdio_led_en;
wire[5:0] sdio_bus_voltage;
//SPI interfaces
wire[1:0] spi_clk_in = 2'h0;
wire[1:0] spi_clk_out;
wire[1:0] spi_clk_tris;
wire[1:0] spi_mosi_in = 2'h0;
wire[1:0] spi_mosi_out;
wire[1:0] spi_mosi_tris;
wire[1:0] spi_miso_in = 2'h0;
wire[1:0] spi_miso_out;
wire[1:0] spi_miso_tris;
wire[1:0] spi_csn_in = 2'h3;
wire[5:0] spi_csn_out;
wire[1:0] spi_csn_tris;
//Triple timer/counters
wire[5:0] tmrcnt_clk = 6'h0;
wire[5:0] tmrcnt_wave_out;
//UARTs
wire[1:0] uart_txd;
wire[1:0] uart_rxd = 2'h3;
wire[1:0] uart_cts = 2'h0;
wire[1:0] uart_rts;
wire[1:0] uart_dsr = 2'h0;
wire[1:0] uart_dcd = 2'h0;
wire[1:0] uart_ri = 2'h0;
wire[1:0] uart_dtr;
//USB status signals. The actual ULPI data lines are hard IP and not routed to fabric.
wire[3:0] usb_indicator;
wire[1:0] usb_pwr_fault = 2'h0;
wire[1:0] usb_pwr_select;
//AXI bus power saving stuff
wire fpga_axi_buses_idle = 1'h0;
//Master AXI links (transactions initiated by CPU, 32 bits)
wire[1:0] master_axi_clk = 2'h0;
wire[1:0] master_axi_rst_n;
wire[63:0] master_axi_rdreq_addr;
wire[1:0] master_axi_rdreq_valid;
wire[1:0] master_axi_rdreq_ready = 2'h0;
wire[23:0] master_axi_rdreq_id;
wire[3:0] master_axi_rdreq_lock;
wire[7:0] master_axi_rdreq_cache;
wire[5:0] master_axi_rdreq_prot;
wire[7:0] master_axi_rdreq_len;
wire[3:0] master_axi_rdreq_size;
wire[3:0] master_axi_rdreq_burst;
wire[7:0] master_axi_rdreq_qos;
wire[63:0] master_axi_rdresp_data = 64'h0;
wire[1:0] master_axi_rdresp_valid = 2'h0;
wire[1:0] master_axi_rdresp_ready;
wire[23:0] master_axi_rdresp_id = 24'h0;
wire[1:0] master_axi_rdresp_last = 2'h0;
wire[3:0] master_axi_rdresp_resp = 2'h0;
wire[63:0] master_axi_wrreq_addr;
wire[1:0] master_axi_wrreq_valid;
wire[1:0] master_axi_wrreq_ready = 2'h0;
wire[23:0] master_axi_wrreq_id;
wire[3:0] master_axi_wrreq_lock;
wire[7:0] master_axi_wrreq_cache;
wire[5:0] master_axi_wrreq_prot;
wire[7:0] master_axi_wrreq_len;
wire[3:0] master_axi_wrreq_size;
wire[3:0] master_axi_wrreq_burst;
wire[7:0] master_axi_wrreq_qos;
wire[63:0] master_axi_wrdat_data;
wire[1:0] master_axi_wrdat_valid;
wire[1:0] master_axi_wrdat_ready = 2'h0;
wire[23:0] master_axi_wrdat_id;
wire[1:0] master_axi_wrdat_last;
wire[7:0] master_axi_wrdat_mask;
wire[1:0] master_axi_wrresp_valid = 2'h0;
wire[1:0] master_axi_wrresp_ready;
wire[23:0] master_axi_wrresp_id = 24'h0;
wire[3:0] master_axi_wrresp_resp = 4'h0;
//Slave AXI ACP links (transactions initiated by FPGA, cache coherent, 64 bits)
wire acp_axi_clk = 1'h0;
wire acp_axi_rst_n;
wire[31:0] acp_axi_rdreq_addr = 32'h0;
wire acp_axi_rdreq_valid = 1'h0;
wire acp_axi_rdreq_ready;
wire[2:0] acp_axi_rdreq_id = 3'h0;
wire[4:0] acp_axi_rdreq_user = 5'h0;
wire[1:0] acp_axi_rdreq_lock = 2'h0;
wire[3:0] acp_axi_rdreq_cache = 4'h0;
wire[2:0] acp_axi_rdreq_prot = 3'h0;
wire[3:0] acp_axi_rdreq_len = 4'h0;
wire[1:0] acp_axi_rdreq_size = 2'h0;
wire[1:0] acp_axi_rdreq_burst = 2'h0;
wire[3:0] acp_axi_rdreq_qos = 4'h0;
wire[63:0] acp_axi_rdresp_data;
wire acp_axi_rdresp_valid;
wire acp_axi_rdresp_ready = 1'h0;
wire[2:0] acp_axi_rdresp_id = 3'h0;
wire acp_axi_rdresp_last;
wire[1:0] acp_axi_rdresp_resp;
wire[31:0] acp_axi_wrreq_addr = 32'h0;
wire acp_axi_wrreq_valid = 1'h0;
wire acp_axi_wrreq_ready;
wire[2:0] acp_axi_wrreq_id = 3'h0;
wire[4:0] acp_axi_wrreq_user = 5'h0;
wire[1:0] acp_axi_wrreq_lock = 2'h0;
wire[3:0] acp_axi_wrreq_cache = 4'h0;
wire[2:0] acp_axi_wrreq_prot = 3'h0;
wire[3:0] acp_axi_wrreq_len = 4'h0;
wire[1:0] acp_axi_wrreq_size = 2'h0;
wire[1:0] acp_axi_wrreq_burst = 2'h0;
wire[3:0] acp_axi_wrreq_qos = 4'h0;
wire[63:0] acp_axi_wrdat_data = 64'h0;
wire acp_axi_wrdat_valid = 1'h0;
wire acp_axi_wrdat_ready = 1'h0;
wire[2:0] acp_axi_wrdat_id = 3'h0;
wire acp_axi_wrdat_last = 1'h0;
wire[7:0] acp_axi_wrdat_mask = 8'h0;
wire acp_axi_wrresp_valid;
wire acp_axi_wrresp_ready = 1'h0;
wire[2:0] acp_axi_wrresp_id;
wire[1:0] acp_axi_wrresp_resp;
//Slave AXI general purpose links (transactions initiated by FPGA, no buffering, 32 bits)
wire[1:0] slavegp_axi_clk = 2'h0;
wire[1:0] slavegp_axi_rst_n;
wire[63:0] slavegp_axi_rdreq_addr = 64'h0;
wire[1:0] slavegp_axi_rdreq_valid = 2'h0;
wire[1:0] slavegp_axi_rdreq_ready;
wire[11:0] slavegp_axi_rdreq_id = 12'h0;
wire[3:0] slavegp_axi_rdreq_lock = 4'h0;
wire[7:0] slavegp_axi_rdreq_cache = 8'h0;
wire[5:0] slavegp_axi_rdreq_prot = 6'h0;
wire[7:0] slavegp_axi_rdreq_len = 8'h0;
wire[3:0] slavegp_axi_rdreq_size = 4'h0;
wire[3:0] slavegp_axi_rdreq_burst = 4'h0;
wire[7:0] slavegp_axi_rdreq_qos = 8'h0;
wire[63:0] slavegp_axi_rdresp_data;
wire[1:0] slavegp_axi_rdresp_valid;
wire[1:0] slavegp_axi_rdresp_ready = 2'h0;
wire[11:0] slavegp_axi_rdresp_id;
wire[1:0] slavegp_axi_rdresp_last;
wire[3:0] slavegp_axi_rdresp_resp;
wire[63:0] slavegp_axi_wrreq_addr = 64'h0;
wire[1:0] slavegp_axi_wrreq_valid = 2'h0;
wire[1:0] slavegp_axi_wrreq_ready;
wire[11:0] slavegp_axi_wrreq_id = 12'h0;
wire[3:0] slavegp_axi_wrreq_lock = 4'h0;
wire[7:0] slavegp_axi_wrreq_cache = 8'h0;
wire[5:0] slavegp_axi_wrreq_prot = 6'h0;
wire[7:0] slavegp_axi_wrreq_len = 8'h0;
wire[3:0] slavegp_axi_wrreq_size = 4'h0;
wire[3:0] slavegp_axi_wrreq_burst = 4'h0;
wire[7:0] slavegp_axi_wrreq_qos = 8'h0;
wire[63:0] slavegp_axi_wrdat_data = 64'h0;
wire[1:0] slavegp_axi_wrdat_valid = 2'h0;
wire[1:0] slavegp_axi_wrdat_ready;
wire[23:0] slavegp_axi_wrdat_id = 24'h0;
wire[1:0] slavegp_axi_wrdat_last = 2'h0;
wire[7:0] slavegp_axi_wrdat_mask = 8'h0;
wire[1:0] slavegp_axi_wrresp_valid;
wire[1:0] slavegp_axi_wrresp_ready = 2'h0;
wire[11:0] slavegp_axi_wrresp_id;
wire[3:0] slavegp_axi_wrresp_resp;
//Slave AXI high performance links (transactions initiated by FPGA, fifo buffering, 64 bits)
wire[3:0] slavehp_axi_clk = 4'h0;
wire[3:0] slavehp_axi_rst_n;
wire[127:0] slavehp_axi_rdreq_addr = 128'h0;
wire[23:0] slavehp_axi_rdreq_fifosize;
wire[3:0] slavehp_axi_rdreq_valid = 4'h0;
wire[3:0] slavehp_axi_rdreq_ready;
wire[23:0] slavehp_axi_rdreq_id = 24'h0;
wire[7:0] slavehp_axi_rdreq_lock = 8'h0;
wire[15:0] slavehp_axi_rdreq_cache = 16'h0;
wire[11:0] slavehp_axi_rdreq_prot = 12'h0;
wire[15:0] slavehp_axi_rdreq_len = 16'h0;
wire[7:0] slavehp_axi_rdreq_size = 8'h0;
wire[7:0] slavehp_axi_rdreq_burst = 8'h0;
wire[15:0] slavehp_axi_rdreq_qos = 16'h0;
wire[255:0] slavehp_axi_rdresp_data;
wire[31:0] slavehp_axi_rdresp_fifosize;
wire[3:0] slavehp_axi_rdresp_valid;
wire[3:0] slavehp_axi_rdresp_ready = 4'h0;
wire[23:0] slavehp_axi_rdresp_id;
wire[3:0] slavehp_axi_rdresp_last;
wire[7:0] slavehp_axi_rdresp_resp;
wire[3:0] slavehp_axi_rdissuecap1en = 4'h0; //wut is this?
wire[127:0] slavehp_axi_wrreq_addr = 128'h0;
wire[23:0] slavehp_axi_wrreq_fifosize;
wire[3:0] slavehp_axi_wrreq_valid = 4'h0;
wire[3:0] slavehp_axi_wrreq_ready;
wire[23:0] slavehp_axi_wrreq_id = 24'h0;
wire[7:0] slavehp_axi_wrreq_lock = 8'h0;
wire[15:0] slavehp_axi_wrreq_cache = 16'h0;
wire[11:0] slavehp_axi_wrreq_prot = 12'h0;
wire[15:0] slavehp_axi_wrreq_len = 16'h0;
wire[7:0] slavehp_axi_wrreq_size = 8'h0;
wire[7:0] slavehp_axi_wrreq_burst = 8'h0;
wire[15:0] slavehp_axi_wrreq_qos = 16'h0;
wire[255:0] slavehp_axi_wrdat_data = 256'h0;
wire[31:0] slavehp_axi_wrdat_fifosize;
wire[3:0] slavehp_axi_wrdat_valid = 4'h0;
wire[3:0] slavehp_axi_wrdat_ready;
wire[23:0] slavehp_axi_wrdat_id = 24'h0;
wire[3:0] slavehp_axi_wrdat_last = 4'h0;
wire[31:0] slavehp_axi_wrdat_mask = 32'h0;
wire[3:0] slavehp_axi_wrresp_valid;
wire[3:0] slavehp_axi_wrresp_ready = 4'h0;
wire[23:0] slavehp_axi_wrresp_id;
wire[7:0] slavehp_axi_wrresp_resp;
wire[3:0] slavehp_axi_wrissuecap1en = 4'h0; //wut is this?
//DDR RAM signals (TODO: break these out to top level and hook them up)
wire[14:0] ddr_addr;
wire[2:0] ddr_bankaddr;
wire ddr_cas_n;
wire ddr_cke;
wire ddr_clk_n;
wire ddr_clk_p;
wire ddr_cs_n;
wire[3:0] ddr_dm;
wire[31:0] ddr_dq;
wire[3:0] ddr_dqs_n;
wire[3:0] ddr_dqs_p;
wire ddr_reset_n;
wire ddr_odt;
wire ddr_ras_n;
wire ddr_vr_n;
wire ddr_vr_p;
wire ddr_we_n;
//Muxed GPIO signals
wire[53:0] muxed_gpio;
//IRQ from external SRAM
wire sram_irq = 1'h0;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The actual CPU
PS7 cpu(
//CPU clock and reset
.PSCLK(__nowarn_528_cpu_clk),
.PSPORB(__nowarn_528_cpu_por_n),
.PSSRSTB(__nowarn_528_cpu_srst_n),
//CPU JTAG
.EMIOPJTAGTDO(cpu_jtag_tdo),
.EMIOPJTAGTDTN(), //JTAG TDO tristate enable (not used for now)
.EMIOPJTAGTCK(cpu_jtag_tck),
.EMIOPJTAGTDI(cpu_jtag_tdi),
.EMIOPJTAGTMS(cpu_jtag_tms),
//Clocks from CPU to FPGA
.FCLKCLK(fabric_clock_unbuffered),
.FCLKRESETN(async_cpu_reset_complete),
.FCLKCLKTRIGN(4'h0), //Unimplemented, must be tied to ground per Zynq TRM 2.7.1
//AXI bus power management
.FPGAIDLEN(fpga_axi_buses_idle),
//Fabric Trace Monitor (FPGA to CoreSight bridge)
.FTMTF2PDEBUG(fpga_to_cpu_debug_gpioreg),
.FTMTP2FDEBUG(cpu_to_fpga_debug_gpioreg),
.FTMTF2PTRIG(fpga_to_cpu_trace_trigger),
.FTMTF2PTRIGACK(fpga_to_cpu_trace_ack),
.FTMTP2FTRIG(cpu_to_fpga_trace_trigger),
.FTMTP2FTRIGACK(cpu_to_fpga_trace_ack),
.FTMDTRACEINVALID(fpga_trace_valid),
.FTMDTRACEINCLOCK(fpga_trace_clk),
.FTMDTRACEINDATA(fpga_trace_data),
.FTMDTRACEINATID(fpga_trace_id),
//EMIO trace port
.EMIOTRACECLK(trace_clk),
.EMIOTRACECTL(trace_ctl),
.EMIOTRACEDATA(trace_data),
//Watchdog timer (not yet used)
.EMIOWDTRSTO(watchdog_reset_out),
.EMIOWDTCLKI(watchdog_clk),
//Event handling
.EVENTEVENTI(cpu_event_req),
.EVENTEVENTO(cpu_event_ack),
.EVENTSTANDBYWFE(cpu_waiting_for_event),
.EVENTSTANDBYWFI(cpu_waiting_for_irq),
//Interrupts
//NOTE: Zynq TRM 2.7.2 specifies "both CPUs" for nFIQ, nIRQ as bits 19:16
//but does not specify the ordering within those four bits!
.IRQF2P({cpu_fiq_n, cpu_irq_n, fpga_to_cpu_irq}),
.IRQP2F(cpu_to_fpga_irq),
//Muxed I/O signals from hard IP
.MIO(muxed_gpio),
//SRAM external interrupt signal
.EMIOSRAMINTIN(sram_irq),
//DDR RAM
.DDRDRSTB(ddr_reset_n),
.DDRCKE(ddr_cke),
.DDRODT(ddr_odt),
.DDRCSB(ddr_cs_n),
.DDRVRP(ddr_vr_p),
.DDRVRN(ddr_vr_n),
.DDRCKP(ddr_clk_p),
.DDRCKN(ddr_clk_n),
.DDRA(ddr_addr),
.DDRBA(ddr_bankaddr),
.DDRARB(), //what does this do? doesn't seem to be doc'd anywhere!
.DDRCASB(ddr_cas_n),
.DDRRASB(ddr_ras_n),
.DDRWEB(ddr_we_n),
.DDRDM(ddr_dm),
.DDRDQ(ddr_dq),
.DDRDQSP(ddr_dqs_p),
.DDRDQSN(ddr_dqs_n),
//CPU DMA ports
.DMA0ACLK(dma_clk[0]),
.DMA0DRREADY(dma_req_ready[0]),
.DMA0DRVALID(dma_req_valid[0]),
.DMA0DRTYPE(dma_req_type[0*2 +: 2]),
.DMA0DRLAST(dma_req_last[0]),
.DMA0DAREADY(dma_ack_ready[0]),
.DMA0DAVALID(dma_ack_valid[0]),
.DMA0DATYPE(dma_ack_type[0*2 +: 2]),
.DMA0RSTN(dma_rst_n[0]),
.DMA1ACLK(dma_clk[1]),
.DMA1DRREADY(dma_req_ready[1]),
.DMA1DRVALID(dma_req_valid[1]),
.DMA1DRTYPE(dma_req_type[1*2 +: 2]),
.DMA1DRLAST(dma_req_last[1]),
.DMA1DAREADY(dma_ack_ready[1]),
.DMA1DAVALID(dma_ack_valid[1]),
.DMA1DATYPE(dma_ack_type[1*2 +: 2]),
.DMA1RSTN(dma_rst_n[1]),
.DMA2ACLK(dma_clk[2]),
.DMA2DRREADY(dma_req_ready[2]),
.DMA2DRVALID(dma_req_valid[2]),
.DMA2DRTYPE(dma_req_type[2*2 +: 2]),
.DMA2DRLAST(dma_req_last[2]),
.DMA2DAREADY(dma_ack_ready[2]),
.DMA2DAVALID(dma_ack_valid[2]),
.DMA2DATYPE(dma_ack_type[2*2 +: 2]),
.DMA2RSTN(dma_rst_n[2]),
.DMA3ACLK(dma_clk[3]),
.DMA3DRREADY(dma_req_ready[3]),
.DMA3DRVALID(dma_req_valid[3]),
.DMA3DRTYPE(dma_req_type[3*2 +: 2]),
.DMA3DRLAST(dma_req_last[3]),
.DMA3DAREADY(dma_ack_ready[3]),
.DMA3DAVALID(dma_ack_valid[3]),
.DMA3DATYPE(dma_ack_type[3*2 +: 2]),
.DMA3RSTN(dma_rst_n[3]),
//EMIO CAN
.EMIOCAN0PHYTX(can_phy_tx[0]),
.EMIOCAN0PHYRX(can_phy_rx[0]),
.EMIOCAN1PHYTX(can_phy_tx[1]),
.EMIOCAN1PHYRX(can_phy_rx[1]),
//EMIO Ethernet 0
.EMIOENET0MDIOMDC(eth_mgmt_mdc[0]),
.EMIOENET0MDIOO(eth_mgmt_mdio_out[0] ),
.EMIOENET0MDIOTN(eth_mgmt_mdio_tris[0] ),
.EMIOENET0MDIOI(eth_mgmt_mdio_in[0]),
.EMIOENET0GMIITXCLK(eth_gmii_txc[0]),
.EMIOENET0GMIITXD(eth_gmii_txd[7:0] ),
.EMIOENET0GMIITXEN(eth_gmii_tx_en[0]),
.EMIOENET0GMIITXER(eth_gmii_tx_er[0]),
.EMIOENET0GMIIRXCLK(eth_gmii_rxc[0]),
.EMIOENET0GMIICOL(eth_gmii_rx_col[0]),
.EMIOENET0GMIICRS(eth_gmii_rx_crs[0]),
.EMIOENET0GMIIRXER(eth_gmii_rx_er[0]),
.EMIOENET0GMIIRXDV(eth_gmii_rx_dv[0]),
.EMIOENET0GMIIRXD(eth_gmii_rxd[7:0]),
.EMIOENET0SOFRX(eth_ptp_rx_sof[0]),
.EMIOENET0PTPDELAYREQRX(eth_ptp_rx_ptp_delay_req[0]),
.EMIOENET0PTPPDELAYREQRX(eth_ptp_rx_ptp_peer_delay[0]),
.EMIOENET0PTPPDELAYRESPRX(eth_ptp_rx_ptp_peer_delay_resp[0]),
.EMIOENET0PTPSYNCFRAMERX(eth_ptp_rx_ptp_sync[0]),
.EMIOENET0SOFTX(eth_ptp_tx_sof[0]),
.EMIOENET0PTPDELAYREQTX(eth_ptp_tx_ptp_delay_req[0]),
.EMIOENET0PTPPDELAYREQTX(eth_ptp_tx_ptp_peer_delay[0]),
.EMIOENET0PTPPDELAYRESPTX(eth_ptp_tx_ptp_peer_delay_resp[0]),
.EMIOENET0PTPSYNCFRAMETX(eth_ptp_tx_ptp_sync[0]),
.EMIOENET0EXTINTIN(eth_ext_int[0]),
//EMIO Ethernet 1
.EMIOENET1MDIOMDC(eth_mgmt_mdc[1]),
.EMIOENET1MDIOO(eth_mgmt_mdio_out[1] ),
.EMIOENET1MDIOTN(eth_mgmt_mdio_tris[1] ),
.EMIOENET1MDIOI(eth_mgmt_mdio_in[1]),
.EMIOENET1GMIITXCLK(eth_gmii_txc[1]),
.EMIOENET1GMIITXD(eth_gmii_txd[15:8] ),
.EMIOENET1GMIITXEN(eth_gmii_tx_en[1]),
.EMIOENET1GMIITXER(eth_gmii_tx_er[1]),
.EMIOENET1GMIIRXCLK(eth_gmii_rxc[1]),
.EMIOENET1GMIICOL(eth_gmii_rx_col[1]),
.EMIOENET1GMIICRS(eth_gmii_rx_crs[1]),
.EMIOENET1GMIIRXER(eth_gmii_rx_er[1]),
.EMIOENET1GMIIRXDV(eth_gmii_rx_dv[1]),
.EMIOENET1GMIIRXD(eth_gmii_rxd[15:8]),
.EMIOENET1SOFRX(eth_ptp_rx_sof[1]),
.EMIOENET1PTPDELAYREQRX(eth_ptp_rx_ptp_delay_req[1]),
.EMIOENET1PTPPDELAYREQRX(eth_ptp_rx_ptp_peer_delay[1]),
.EMIOENET1PTPPDELAYRESPRX(eth_ptp_rx_ptp_peer_delay_resp[1]),
.EMIOENET1PTPSYNCFRAMERX(eth_ptp_rx_ptp_sync[1]),
.EMIOENET1SOFTX(eth_ptp_tx_sof[1]),
.EMIOENET1PTPDELAYREQTX(eth_ptp_tx_ptp_delay_req[1]),
.EMIOENET1PTPPDELAYREQTX(eth_ptp_tx_ptp_peer_delay[1]),
.EMIOENET1PTPPDELAYRESPTX(eth_ptp_tx_ptp_peer_delay_resp[1]),
.EMIOENET1PTPSYNCFRAMETX(eth_ptp_tx_ptp_sync[1]),
.EMIOENET1EXTINTIN(eth_ext_int[1]),
//EMIO GPIO
.EMIOGPIOO(gpio_out),
.EMIOGPIOTN(gpio_tris),
.EMIOGPIOI(gpio_in),
//EMIO I2C 0
.EMIOI2C0SCLO(i2c_scl_out[0]),
.EMIOI2C0SCLTN(i2c_scl_tris[0]),
.EMIOI2C0SCLI(i2c_scl_in[0]),
.EMIOI2C0SDAO(i2c_sda_out[0]),
.EMIOI2C0SDATN(i2c_sda_tris[0]),
.EMIOI2C0SDAI(i2c_sda_in[0]),
//EMIO I2C 1
.EMIOI2C1SCLO(i2c_scl_out[1]),
.EMIOI2C1SCLTN(i2c_scl_tris[1]),
.EMIOI2C1SCLI(i2c_scl_in[1]),
.EMIOI2C1SDAO(i2c_sda_out[1]),
.EMIOI2C1SDATN(i2c_sda_tris[1]),
.EMIOI2C1SDAI(i2c_sda_in[1]),
//EMIO SD 0
.EMIOSDIO0CLK(sdio_clk[0]),
.EMIOSDIO0CLKFB(sdio_clkfb[0]),
.EMIOSDIO0CMDO(sdio_cmd_out[0]),
.EMIOSDIO0CMDTN(sdio_cmd_tris[0]),
.EMIOSDIO0CMDI(sdio_cmd_in[0]),
.EMIOSDIO0DATAO(sdio_data_out[3:0]),
.EMIOSDIO0DATATN(sdio_data_tris[3:0]),
.EMIOSDIO0DATAI(sdio_data_in[3:0]),
.EMIOSDIO0BUSPOW(sdio_power_en[0]),
.EMIOSDIO0LED(sdio_led_en[0]),
.EMIOSDIO0BUSVOLT(sdio_bus_voltage[2:0]),
.EMIOSDIO0CDN(sdio_card_detect[0]),
.EMIOSDIO0WP(sdio_write_protect[0]),
//EMIO SD 1
.EMIOSDIO1CLK(sdio_clk[1]),
.EMIOSDIO1CLKFB(sdio_clkfb[1]),
.EMIOSDIO1CMDO(sdio_cmd_out[1]),
.EMIOSDIO1CMDTN(sdio_cmd_tris[1]),
.EMIOSDIO1CMDI(sdio_cmd_in[1]),
.EMIOSDIO1DATAO(sdio_data_out[7:4]),
.EMIOSDIO1DATATN(sdio_data_tris[7:4]),
.EMIOSDIO1DATAI(sdio_data_in[7:4]),
.EMIOSDIO1BUSPOW(sdio_power_en[1]),
.EMIOSDIO1LED(sdio_led_en[1]),
.EMIOSDIO1BUSVOLT(sdio_bus_voltage[5:3]),
.EMIOSDIO1CDN(sdio_card_detect[1]),
.EMIOSDIO1WP(sdio_write_protect[1]),
//EMIO SPI 0 (not yet used)
.EMIOSPI0SCLKO(spi_clk_out[0]),
.EMIOSPI0SCLKTN(spi_clk_tris[0]),
.EMIOSPI0SCLKI(spi_clk_in[0]),
.EMIOSPI0MO(spi_mosi_out[0]),
.EMIOSPI0MOTN(spi_mosi_tris[0]),
.EMIOSPI0SI(spi_mosi_in[0]),
.EMIOSPI0SO(spi_miso_out[0]),
.EMIOSPI0STN(spi_miso_tris[0]),
.EMIOSPI0MI(spi_miso_in[0]),
.EMIOSPI0SSON(spi_csn_out[2:0]),
.EMIOSPI0SSNTN(spi_csn_tris[0]),
.EMIOSPI0SSIN(spi_csn_in[0]),
//EMIO SPI 1 (not yet used)
.EMIOSPI1SCLKO(spi_clk_out[1]),
.EMIOSPI1SCLKTN(spi_clk_tris[1]),
.EMIOSPI1SCLKI(spi_clk_in[1]),
.EMIOSPI1MO(spi_mosi_out[1]),
.EMIOSPI1MOTN(spi_mosi_tris[1]),
.EMIOSPI1SI(spi_mosi_in[1]),
.EMIOSPI1SO(spi_miso_out[1]),
.EMIOSPI1STN(spi_miso_tris[1]),
.EMIOSPI1MI(spi_miso_in[1]),
.EMIOSPI1SSON(spi_csn_out[5:3]),
.EMIOSPI1SSNTN(spi_csn_tris[1]),
.EMIOSPI1SSIN(spi_csn_in[1]),
//Triple timer/counters
.EMIOTTC0CLKI(tmrcnt_clk[2:0]),
.EMIOTTC0WAVEO(tmrcnt_wave_out[2:0]),
.EMIOTTC1CLKI(tmrcnt_clk[5:3]),
.EMIOTTC1WAVEO(tmrcnt_wave_out[2:0]),
//EMIO UART 0
.EMIOUART0TX(uart_txd[0]),
.EMIOUART0RX(uart_rxd[0]),
.EMIOUART0DTRN(uart_dtr[0]),
.EMIOUART0DSRN(uart_dsr[0]),
.EMIOUART0RTSN(uart_rts[0]),
.EMIOUART0DCDN(uart_dcd[0]),
.EMIOUART0CTSN(uart_cts[0]),
.EMIOUART0RIN(uart_ri[0]),
//EMIO UART 1
.EMIOUART1TX(uart_txd[1]),
.EMIOUART1RX(uart_rxd[1]),
.EMIOUART1DTRN(uart_dtr[1]),
.EMIOUART1DSRN(uart_dsr[1]),
.EMIOUART1RTSN(uart_rts[1]),
.EMIOUART1DCDN(uart_dcd[1]),
.EMIOUART1CTSN(uart_cts[1]),
.EMIOUART1RIN(uart_ri[1]),
//EMIO USB 0
.EMIOUSB0PORTINDCTL(usb_indicator[1:0]),
.EMIOUSB0VBUSPWRSELECT(usb_pwr_select[0]),
.EMIOUSB0VBUSPWRFAULT(usb_pwr_fault[0]),
//EMIO USB 1
.EMIOUSB1PORTINDCTL(usb_indicator[3:2]),
.EMIOUSB1VBUSPWRSELECT(usb_pwr_select[1]),
.EMIOUSB1VBUSPWRFAULT(usb_pwr_fault[1]),
//Master AXI GP 0
.MAXIGP0ACLK(master_axi_clk[0]),
.MAXIGP0ARESETN(master_axi_rst_n[0]),
.MAXIGP0ARADDR(master_axi_rdreq_addr[31:0]),
.MAXIGP0ARVALID(master_axi_rdreq_valid[0]),
.MAXIGP0ARREADY(master_axi_rdreq_ready[0]),
.MAXIGP0ARID(master_axi_rdreq_id[11:0]),
.MAXIGP0ARLOCK(master_axi_rdreq_lock[1:0]),
.MAXIGP0ARCACHE(master_axi_rdreq_cache[3:0]),
.MAXIGP0ARPROT(master_axi_rdreq_prot[2:0]),
.MAXIGP0ARLEN(master_axi_rdreq_len[3:0]),
.MAXIGP0ARSIZE(master_axi_rdreq_size[1:0]),
.MAXIGP0ARBURST(master_axi_rdreq_burst[1:0]),
.MAXIGP0ARQOS(master_axi_rdreq_qos[3:0]),
.MAXIGP0RDATA(master_axi_rdresp_data[31:0]),
.MAXIGP0RVALID(master_axi_rdresp_valid[0]),
.MAXIGP0RREADY(master_axi_rdresp_ready[0]),
.MAXIGP0RID(master_axi_rdresp_id[11:0]),
.MAXIGP0RLAST(master_axi_rdresp_last[0]),
.MAXIGP0RRESP(master_axi_rdresp_resp[1:0]),
.MAXIGP0AWADDR(master_axi_wrreq_addr[31:0]),
.MAXIGP0AWVALID(master_axi_wrreq_valid[0]),
.MAXIGP0AWREADY(master_axi_wrreq_ready[0]),
.MAXIGP0AWID(master_axi_wrreq_id[11:0]),
.MAXIGP0AWLOCK(master_axi_wrreq_lock[1:0]),
.MAXIGP0AWCACHE(master_axi_wrreq_cache[3:0]),
.MAXIGP0AWPROT(master_axi_wrreq_prot[2:0]),
.MAXIGP0AWLEN(master_axi_wrreq_len[3:0]),
.MAXIGP0AWSIZE(master_axi_wrreq_size[1:0]),
.MAXIGP0AWBURST(master_axi_wrreq_burst[1:0]),
.MAXIGP0AWQOS(master_axi_wrreq_qos[3:0]),
.MAXIGP0WDATA(master_axi_wrdat_data[31:0]),
.MAXIGP0WVALID(master_axi_wrdat_valid[0]),
.MAXIGP0WREADY(master_axi_wrdat_ready[0]),
.MAXIGP0WID(master_axi_wrdat_id[11:0]),
.MAXIGP0WLAST(master_axi_wrdat_last[0]),
.MAXIGP0WSTRB(master_axi_wrdat_mask[3:0]),
.MAXIGP0BVALID(master_axi_wrresp_valid[0]),
.MAXIGP0BREADY(master_axi_wrresp_ready[0]),
.MAXIGP0BID(master_axi_wrresp_id[11:0]),
.MAXIGP0BRESP(master_axi_wrresp_resp[1:0]),
//Master AXI GP 1
.MAXIGP1ACLK(master_axi_clk[1]),
.MAXIGP1ARESETN(master_axi_rst_n[1]),
.MAXIGP1ARADDR(master_axi_rdreq_addr[63:32]),
.MAXIGP1ARVALID(master_axi_rdreq_valid[1]),
.MAXIGP1ARREADY(master_axi_rdreq_ready[1]),
.MAXIGP1ARID(master_axi_rdreq_id[23:12]),
.MAXIGP1ARLOCK(master_axi_rdreq_lock[3:2]),
.MAXIGP1ARCACHE(master_axi_rdreq_cache[7:4]),
.MAXIGP1ARPROT(master_axi_rdreq_prot[5:3]),
.MAXIGP1ARLEN(master_axi_rdreq_len[7:4]),
.MAXIGP1ARSIZE(master_axi_rdreq_size[3:2]),
.MAXIGP1ARBURST(master_axi_rdreq_burst[3:2]),
.MAXIGP1ARQOS(master_axi_rdreq_qos[7:4]),
.MAXIGP1RDATA(master_axi_rdresp_data[63:32]),
.MAXIGP1RVALID(master_axi_rdresp_valid[1]),
.MAXIGP1RREADY(master_axi_rdresp_ready[1]),
.MAXIGP1RID(master_axi_rdresp_id[23:12]),
.MAXIGP1RLAST(master_axi_rdresp_last[1]),
.MAXIGP1RRESP(master_axi_rdresp_resp[3:2]),
.MAXIGP1AWADDR(master_axi_wrreq_addr[63:32]),
.MAXIGP1AWVALID(master_axi_wrreq_valid[1]),
.MAXIGP1AWREADY(master_axi_wrreq_ready[1]),
.MAXIGP1AWID(master_axi_wrreq_id[23:12]),
.MAXIGP1AWLOCK(master_axi_wrreq_lock[3:2]),
.MAXIGP1AWCACHE(master_axi_wrreq_cache[7:4]),
.MAXIGP1AWPROT(master_axi_wrreq_prot[5:3]),
.MAXIGP1AWLEN(master_axi_wrreq_len[7:4]),
.MAXIGP1AWSIZE(master_axi_wrreq_size[3:2]),
.MAXIGP1AWBURST(master_axi_wrreq_burst[3:2]),
.MAXIGP1AWQOS(master_axi_wrreq_qos[7:4]),
.MAXIGP1WDATA(master_axi_wrdat_data[63:32]),
.MAXIGP1WVALID(master_axi_wrdat_valid[1]),
.MAXIGP1WREADY(master_axi_wrdat_ready[1]),
.MAXIGP1WID(master_axi_wrdat_id[23:12]),
.MAXIGP1WLAST(master_axi_wrdat_last[1]),
.MAXIGP1WSTRB(master_axi_wrdat_mask[7:4]),
.MAXIGP1BVALID(master_axi_wrresp_valid[1]),
.MAXIGP1BREADY(master_axi_wrresp_ready[1]),
.MAXIGP1BID(master_axi_wrresp_id[23:12]),
.MAXIGP1BRESP(master_axi_wrresp_resp[3:2]),
//Slave AXI ACP (not yet used)
.SAXIACPACLK(acp_axi_clk),
.SAXIACPARESETN(acp_axi_rst_n),
.SAXIACPARADDR(acp_axi_rdreq_addr),
.SAXIACPARVALID(acp_axi_rdreq_valid),
.SAXIACPARREADY(acp_axi_rdreq_ready),
.SAXIACPRID(acp_axi_rdreq_id),
.SAXIACPARUSER(acp_axi_rdreq_user ),
.SAXIACPARLOCK(acp_axi_rdreq_lock),
.SAXIACPARCACHE(acp_axi_rdreq_cache),
.SAXIACPARPROT(acp_axi_rdreq_prot),
.SAXIACPARLEN(acp_axi_rdreq_len),
.SAXIACPARSIZE(acp_axi_rdreq_size),
.SAXIACPARBURST(acp_axi_rdreq_burst),
.SAXIACPARQOS(acp_axi_rdreq_qos),
.SAXIACPRDATA(acp_axi_rdresp_data),
.SAXIACPRVALID(acp_axi_rdresp_valid),
.SAXIACPRREADY(acp_axi_rdresp_ready),
.SAXIACPARID(acp_axi_rdresp_id),
.SAXIACPRLAST(acp_axi_rdresp_last),
.SAXIACPRRESP(acp_axi_rdresp_resp),
.SAXIACPAWADDR(acp_axi_wrreq_addr ),
.SAXIACPAWVALID(acp_axi_wrreq_valid),
.SAXIACPAWREADY(acp_axi_wrreq_ready),
.SAXIACPAWID(acp_axi_wrreq_id),
.SAXIACPAWUSER(acp_axi_wrreq_user),
.SAXIACPAWLOCK(acp_axi_wrreq_lock),
.SAXIACPAWCACHE(acp_axi_wrreq_cache),
.SAXIACPAWPROT(acp_axi_wrreq_prot),
.SAXIACPAWLEN(acp_axi_wrreq_len),
.SAXIACPAWSIZE(acp_axi_wrreq_size),
.SAXIACPAWBURST(acp_axi_wrreq_burst),
.SAXIACPAWQOS(acp_axi_wrreq_qos),
.SAXIACPWDATA(acp_axi_wrdat_data),
.SAXIACPWVALID(acp_axi_wrdat_valid ),
.SAXIACPWREADY(acp_axi_wrdat_ready),
.SAXIACPWID(acp_axi_wrdat_id),
.SAXIACPWLAST(acp_axi_wrdat_last),
.SAXIACPWSTRB(acp_axi_wrdat_mask),
.SAXIACPBVALID(acp_axi_wrresp_valid ),
.SAXIACPBREADY(acp_axi_wrresp_ready),
.SAXIACPBID(acp_axi_wrresp_id),
.SAXIACPBRESP(acp_axi_wrresp_resp),
//Slave AXI GP 0
.SAXIGP0ACLK(slavegp_axi_clk[0]),
.SAXIGP0ARESETN(slavegp_axi_rst_n[0]),
.SAXIGP0ARADDR(slavegp_axi_rdreq_addr[31:0]),
.SAXIGP0ARVALID(slavegp_axi_rdreq_valid[0]),
.SAXIGP0ARREADY(slavegp_axi_rdreq_ready[0]),
.SAXIGP0ARID(slavegp_axi_rdreq_id[5:0]),
.SAXIGP0ARLOCK(slavegp_axi_rdreq_lock[1:0]),
.SAXIGP0ARCACHE(slavegp_axi_rdreq_cache[3:0]),
.SAXIGP0ARPROT(slavegp_axi_rdreq_prot[2:0]),
.SAXIGP0ARLEN(slavegp_axi_rdreq_len[3:0]),
.SAXIGP0ARSIZE(slavegp_axi_rdreq_size[1:0]),
.SAXIGP0ARBURST(slavegp_axi_rdreq_burst[1:0]),
.SAXIGP0ARQOS(slavegp_axi_rdreq_qos[3:0]),
.SAXIGP0RDATA(slavegp_axi_rdresp_data[31:0]),
.SAXIGP0RVALID(slavegp_axi_rdresp_valid[0]),
.SAXIGP0RREADY(slavegp_axi_rdresp_ready[0]),
.SAXIGP0RID(slavegp_axi_rdresp_id[5:0]),
.SAXIGP0RLAST(slavegp_axi_rdresp_last[0]),
.SAXIGP0RRESP(slavegp_axi_rdresp_resp[1:0]),
.SAXIGP0AWADDR(slavegp_axi_wrreq_addr[31:0]),
.SAXIGP0AWVALID(slavegp_axi_wrreq_valid[0]),
.SAXIGP0AWREADY(slavegp_axi_wrreq_ready[0]),
.SAXIGP0AWID(slavegp_axi_wrreq_id[5:0]),
.SAXIGP0AWLOCK(slavegp_axi_wrreq_lock[1:0]),
.SAXIGP0AWCACHE(slavegp_axi_wrreq_cache[3:0]),
.SAXIGP0AWPROT(slavegp_axi_wrreq_prot[2:0]),
.SAXIGP0AWLEN(slavegp_axi_wrreq_len[3:0]),
.SAXIGP0AWSIZE(slavegp_axi_wrreq_size[1:0]),
.SAXIGP0AWBURST(slavegp_axi_wrreq_burst[1:0]),
.SAXIGP0AWQOS(slavegp_axi_wrreq_qos[3:0]),
.SAXIGP0WDATA(slavegp_axi_wrdat_data[31:0]),
.SAXIGP0WVALID(slavegp_axi_wrdat_valid[0]),
.SAXIGP0WREADY(slavegp_axi_wrdat_ready[0]),
.SAXIGP0WID(slavegp_axi_wrdat_id[5:0]),
.SAXIGP0WLAST(slavegp_axi_wrdat_last[0]),
.SAXIGP0WSTRB(slavegp_axi_wrdat_mask[3:0]),
.SAXIGP0BVALID(slavegp_axi_wrresp_valid[0]),
.SAXIGP0BREADY(slavegp_axi_wrresp_ready[0]),
.SAXIGP0BID(slavegp_axi_wrresp_id[5:0]),
.SAXIGP0BRESP(slavegp_axi_wrresp_resp[1:0]),
//Slave AXI GP 1
.SAXIGP1ACLK(slavegp_axi_clk[1]),
.SAXIGP1ARESETN(slavegp_axi_rst_n[1]),
.SAXIGP1ARADDR(slavegp_axi_rdreq_addr[63:32]),
.SAXIGP1ARVALID(slavegp_axi_rdreq_valid[1]),
.SAXIGP1ARREADY(slavegp_axi_rdreq_ready[1]),
.SAXIGP1ARID(slavegp_axi_rdreq_id[11:6]),
.SAXIGP1ARLOCK(slavegp_axi_rdreq_lock[3:2]),
.SAXIGP1ARCACHE(slavegp_axi_rdreq_cache[7:4]),
.SAXIGP1ARPROT(slavegp_axi_rdreq_prot[5:3]),
.SAXIGP1ARLEN(slavegp_axi_rdreq_len[7:4]),
.SAXIGP1ARSIZE(slavegp_axi_rdreq_size[3:2]),
.SAXIGP1ARBURST(slavegp_axi_rdreq_burst[3:2]),
.SAXIGP1ARQOS(slavegp_axi_rdreq_qos[7:4]),
.SAXIGP1RDATA(slavegp_axi_rdresp_data[63:32]),
.SAXIGP1RVALID(slavegp_axi_rdresp_valid[1]),
.SAXIGP1RREADY(slavegp_axi_rdresp_ready[1]),
.SAXIGP1RID(slavegp_axi_rdresp_id[11:6]),
.SAXIGP1RLAST(slavegp_axi_rdresp_last[1]),
.SAXIGP1RRESP(slavegp_axi_rdresp_resp[3:2]),
.SAXIGP1AWADDR(slavegp_axi_wrreq_addr[63:32]),
.SAXIGP1AWVALID(slavegp_axi_wrreq_valid[1]),
.SAXIGP1AWREADY(slavegp_axi_wrreq_ready[1]),
.SAXIGP1AWID(slavegp_axi_wrreq_id[11:6]),
.SAXIGP1AWLOCK(slavegp_axi_wrreq_lock[3:2]),
.SAXIGP1AWCACHE(slavegp_axi_wrreq_cache[7:4]),
.SAXIGP1AWPROT(slavegp_axi_wrreq_prot[5:3]),
.SAXIGP1AWLEN(slavegp_axi_wrreq_len[7:4]),
.SAXIGP1AWSIZE(slavegp_axi_wrreq_size[3:2]),
.SAXIGP1AWBURST(slavegp_axi_wrreq_burst[3:2]),
.SAXIGP1AWQOS(slavegp_axi_wrreq_qos[7:4]),
.SAXIGP1WDATA(slavegp_axi_wrdat_data[63:32]),
.SAXIGP1WVALID(slavegp_axi_wrdat_valid[1]),
.SAXIGP1WREADY(slavegp_axi_wrdat_ready[1]),
.SAXIGP1WID(slavegp_axi_wrdat_id[11:6]),
.SAXIGP1WLAST(slavegp_axi_wrdat_last[1]),
.SAXIGP1WSTRB(slavegp_axi_wrdat_mask[7:4]),
.SAXIGP1BVALID(slavegp_axi_wrresp_valid[1]),
.SAXIGP1BREADY(slavegp_axi_wrresp_ready[1]),
.SAXIGP1BID(slavegp_axi_wrresp_id[11:6]),
.SAXIGP1BRESP(slavegp_axi_wrresp_resp[3:2]),
//Slave AXI HP 0
.SAXIHP0ACLK(slavehp_axi_clk[0]),
.SAXIHP0RDISSUECAP1EN(slavehp_axi_rdissuecap1en[0]),
.SAXIHP0ARESETN(slavehp_axi_rst_n[0]),
.SAXIHP0ARADDR(slavehp_axi_rdreq_addr[31:0]),
.SAXIHP0RACOUNT(slavehp_axi_rdreq_fifosize[2:0]),
.SAXIHP0ARVALID(slavehp_axi_rdreq_valid[0]),
.SAXIHP0ARREADY(slavehp_axi_rdreq_ready[0]),
.SAXIHP0ARID(slavehp_axi_rdreq_id[5:0]),
.SAXIHP0ARLOCK(slavehp_axi_rdreq_lock[1:0]),
.SAXIHP0ARCACHE(slavehp_axi_rdreq_cache[3:0]),
.SAXIHP0ARPROT(slavehp_axi_rdreq_prot[2:0]),
.SAXIHP0ARLEN(slavehp_axi_rdreq_len[3:0]),
.SAXIHP0ARSIZE(slavehp_axi_rdreq_size[1:0]),
.SAXIHP0ARBURST(slavehp_axi_rdreq_burst[1:0]),
.SAXIHP0ARQOS(slavehp_axi_rdreq_qos[3:0]),
.SAXIHP0RDATA(slavehp_axi_rdresp_data[63:0]),
.SAXIHP0RCOUNT(slavehp_axi_rdresp_fifosize[7:0]),
.SAXIHP0RVALID(slavehp_axi_rdresp_valid[0]),
.SAXIHP0RREADY(slavehp_axi_rdresp_ready[0]),
.SAXIHP0RID(slavehp_axi_rdresp_id[5:0]),
.SAXIHP0RLAST(slavehp_axi_rdresp_last[0]),
.SAXIHP0RRESP(slavehp_axi_rdresp_resp[1:0]),
.SAXIHP0WRISSUECAP1EN(slavehp_axi_wrissuecap1en[0]),
.SAXIHP0AWADDR(slavehp_axi_wrreq_addr[31:0]),
.SAXIHP0WACOUNT(slavehp_axi_wrreq_fifosize[5:0]),
.SAXIHP0AWVALID(slavehp_axi_wrreq_valid[0]),
.SAXIHP0AWREADY(slavehp_axi_wrreq_ready[0]),
.SAXIHP0AWID(slavehp_axi_wrreq_id[5:0]),
.SAXIHP0AWLOCK(slavehp_axi_wrreq_lock[1:0]),
.SAXIHP0AWCACHE(slavehp_axi_wrreq_cache[3:0]),
.SAXIHP0AWPROT(slavehp_axi_wrreq_prot[2:0]),
.SAXIHP0AWLEN(slavehp_axi_wrreq_len[3:0]),
.SAXIHP0AWSIZE(slavehp_axi_wrreq_size[1:0]),
.SAXIHP0AWBURST(slavehp_axi_wrreq_burst[1:0]),
.SAXIHP0AWQOS(slavehp_axi_wrreq_qos[3:0]),
.SAXIHP0WDATA(slavehp_axi_wrdat_data[63:0]),
.SAXIHP0WCOUNT(slavehp_axi_wrdat_fifosize[7:0]),
.SAXIHP0WVALID(slavehp_axi_wrdat_valid[0]),
.SAXIHP0WREADY(slavehp_axi_wrdat_ready[0]),
.SAXIHP0WID(slavehp_axi_wrdat_id[5:0]),
.SAXIHP0WLAST(slavehp_axi_wrdat_last[0]),
.SAXIHP0WSTRB(slavehp_axi_wrdat_mask[7:0]),
.SAXIHP0BVALID(slavehp_axi_wrresp_valid[0]),
.SAXIHP0BREADY(slavehp_axi_wrresp_ready[0]),
.SAXIHP0BID(slavehp_axi_wrresp_id[5:0]),
.SAXIHP0BRESP(slavehp_axi_wrresp_resp[1:0]),
//Slave AXI HP 1
.SAXIHP1ACLK(slavehp_axi_clk[1]),
.SAXIHP1RDISSUECAP1EN(slavehp_axi_rdissuecap1en[1]),
.SAXIHP1ARESETN(slavehp_axi_rst_n[1]),
.SAXIHP1ARADDR(slavehp_axi_rdreq_addr[63:32]),
.SAXIHP1RACOUNT(slavehp_axi_rdreq_fifosize[5:3]),
.SAXIHP1ARVALID(slavehp_axi_rdreq_valid[1]),
.SAXIHP1ARREADY(slavehp_axi_rdreq_ready[1]),
.SAXIHP1ARID(slavehp_axi_rdreq_id[11:6]),
.SAXIHP1ARLOCK(slavehp_axi_rdreq_lock[3:2]),
.SAXIHP1ARCACHE(slavehp_axi_rdreq_cache[7:4]),
.SAXIHP1ARPROT(slavehp_axi_rdreq_prot[5:3]),
.SAXIHP1ARLEN(slavehp_axi_rdreq_len[7:4]),
.SAXIHP1ARSIZE(slavehp_axi_rdreq_size[3:2]),
.SAXIHP1ARBURST(slavehp_axi_rdreq_burst[3:2]),
.SAXIHP1ARQOS(slavehp_axi_rdreq_qos[7:4]),
.SAXIHP1RDATA(slavehp_axi_rdresp_data[127:64]),
.SAXIHP1RCOUNT(slavehp_axi_rdresp_fifosize[15:8]),
.SAXIHP1RVALID(slavehp_axi_rdresp_valid[1]),
.SAXIHP1RREADY(slavehp_axi_rdresp_ready[1]),
.SAXIHP1RID(slavehp_axi_rdresp_id[11:6]),
.SAXIHP1RLAST(slavehp_axi_rdresp_last[1]),
.SAXIHP1RRESP(slavehp_axi_rdresp_resp[3:2]),
.SAXIHP1WRISSUECAP1EN(slavehp_axi_wrissuecap1en[1]),
.SAXIHP1AWADDR(slavehp_axi_wrreq_addr[63:32]),
.SAXIHP1WACOUNT(slavehp_axi_wrreq_fifosize[11:6]),
.SAXIHP1AWVALID(slavehp_axi_wrreq_valid[1]),
.SAXIHP1AWREADY(slavehp_axi_wrreq_ready[1]),
.SAXIHP1AWID(slavehp_axi_wrreq_id[11:6]),
.SAXIHP1AWLOCK(slavehp_axi_wrreq_lock[3:2]),
.SAXIHP1AWCACHE(slavehp_axi_wrreq_cache[7:4]),
.SAXIHP1AWPROT(slavehp_axi_wrreq_prot[5:3]),
.SAXIHP1AWLEN(slavehp_axi_wrreq_len[7:4]),
.SAXIHP1AWSIZE(slavehp_axi_wrreq_size[3:2]),
.SAXIHP1AWBURST(slavehp_axi_wrreq_burst[3:2]),
.SAXIHP1AWQOS(slavehp_axi_wrreq_qos[7:4]),
.SAXIHP1WDATA(slavehp_axi_wrdat_data[127:64]),
.SAXIHP1WCOUNT(slavehp_axi_wrdat_fifosize[15:8]),
.SAXIHP1WVALID(slavehp_axi_wrdat_valid[1]),
.SAXIHP1WREADY(slavehp_axi_wrdat_ready[1]),
.SAXIHP1WID(slavehp_axi_wrdat_id[11:6]),
.SAXIHP1WLAST(slavehp_axi_wrdat_last[1]),
.SAXIHP1WSTRB(slavehp_axi_wrdat_mask[15:8]),
.SAXIHP1BVALID(slavehp_axi_wrresp_valid[1]),
.SAXIHP1BREADY(slavehp_axi_wrresp_ready[1]),
.SAXIHP1BID(slavehp_axi_wrresp_id[11:6]),
.SAXIHP1BRESP(slavehp_axi_wrresp_resp[3:2]),
//Slave AXI HP 2
.SAXIHP2ACLK(slavehp_axi_clk[2]),
.SAXIHP2RDISSUECAP1EN(slavehp_axi_rdissuecap1en[2]),
.SAXIHP2ARESETN(slavehp_axi_rst_n[2]),
.SAXIHP2ARADDR(slavehp_axi_rdreq_addr[95:64]),
.SAXIHP2RACOUNT(slavehp_axi_rdreq_fifosize[8:6]),
.SAXIHP2ARVALID(slavehp_axi_rdreq_valid[2]),
.SAXIHP2ARREADY(slavehp_axi_rdreq_ready[2]),
.SAXIHP2ARID(slavehp_axi_rdreq_id[17:12]),
.SAXIHP2ARLOCK(slavehp_axi_rdreq_lock[5:4]),
.SAXIHP2ARCACHE(slavehp_axi_rdreq_cache[11:8]),
.SAXIHP2ARPROT(slavehp_axi_rdreq_prot[8:6]),
.SAXIHP2ARLEN(slavehp_axi_rdreq_len[11:8]),
.SAXIHP2ARSIZE(slavehp_axi_rdreq_size[5:4]),
.SAXIHP2ARBURST(slavehp_axi_rdreq_burst[5:4]),
.SAXIHP2ARQOS(slavehp_axi_rdreq_qos[11:8]),
.SAXIHP2RDATA(slavehp_axi_rdresp_data[191:128]),
.SAXIHP2RCOUNT(slavehp_axi_rdresp_fifosize[23:16]),
.SAXIHP2RVALID(slavehp_axi_rdresp_valid[2]),
.SAXIHP2RREADY(slavehp_axi_rdresp_ready[2]),
.SAXIHP2RID(slavehp_axi_rdresp_id[17:12]),
.SAXIHP2RLAST(slavehp_axi_rdresp_last[2]),
.SAXIHP2RRESP(slavehp_axi_rdresp_resp[5:4]),
.SAXIHP2WRISSUECAP1EN(slavehp_axi_wrissuecap1en[2]),
.SAXIHP2AWADDR(slavehp_axi_wrreq_addr[95:64]),
.SAXIHP2WACOUNT(slavehp_axi_wrreq_fifosize[17:12]),
.SAXIHP2AWVALID(slavehp_axi_wrreq_valid[2]),
.SAXIHP2AWREADY(slavehp_axi_wrreq_ready[2]),
.SAXIHP2AWID(slavehp_axi_wrreq_id[17:12]),
.SAXIHP2AWLOCK(slavehp_axi_wrreq_lock[5:4]),
.SAXIHP2AWCACHE(slavehp_axi_wrreq_cache[11:8]),
.SAXIHP2AWPROT(slavehp_axi_wrreq_prot[8:6]),
.SAXIHP2AWLEN(slavehp_axi_wrreq_len[11:8]),
.SAXIHP2AWSIZE(slavehp_axi_wrreq_size[5:4]),
.SAXIHP2AWBURST(slavehp_axi_wrreq_burst[5:4]),
.SAXIHP2AWQOS(slavehp_axi_wrreq_qos[11:8]),
.SAXIHP2WDATA(slavehp_axi_wrdat_data[191:128]),
.SAXIHP2WCOUNT(slavehp_axi_wrdat_fifosize[23:16]),
.SAXIHP2WVALID(slavehp_axi_wrdat_valid[2]),
.SAXIHP2WREADY(slavehp_axi_wrdat_ready[2]),
.SAXIHP2WID(slavehp_axi_wrdat_id[17:12]),
.SAXIHP2WLAST(slavehp_axi_wrdat_last[2]),
.SAXIHP2WSTRB(slavehp_axi_wrdat_mask[23:16]),
.SAXIHP2BVALID(slavehp_axi_wrresp_valid[2]),
.SAXIHP2BREADY(slavehp_axi_wrresp_ready[2]),
.SAXIHP2BID(slavehp_axi_wrresp_id[17:12]),
.SAXIHP2BRESP(slavehp_axi_wrresp_resp[5:4]),
//Slave AXI HP 3
.SAXIHP3ACLK(slavehp_axi_clk[3]),
.SAXIHP3RDISSUECAP1EN(slavehp_axi_rdissuecap1en[3]),
.SAXIHP3ARESETN(slavehp_axi_rst_n[3]),
.SAXIHP3ARADDR(slavehp_axi_rdreq_addr[127:96]),
.SAXIHP3RACOUNT(slavehp_axi_rdreq_fifosize[11:9]),
.SAXIHP3ARVALID(slavehp_axi_rdreq_valid[3]),
.SAXIHP3ARREADY(slavehp_axi_rdreq_ready[3]),
.SAXIHP3ARID(slavehp_axi_rdreq_id[23:18]),
.SAXIHP3ARLOCK(slavehp_axi_rdreq_lock[7:6]),
.SAXIHP3ARCACHE(slavehp_axi_rdreq_cache[15:12]),
.SAXIHP3ARPROT(slavehp_axi_rdreq_prot[11:9]),
.SAXIHP3ARLEN(slavehp_axi_rdreq_len[15:12]),
.SAXIHP3ARSIZE(slavehp_axi_rdreq_size[7:6]),
.SAXIHP3ARBURST(slavehp_axi_rdreq_burst[7:6]),
.SAXIHP3ARQOS(slavehp_axi_rdreq_qos[15:12]),
.SAXIHP3RDATA(slavehp_axi_rdresp_data[255:192]),
.SAXIHP3RCOUNT(slavehp_axi_rdresp_fifosize[31:24]),
.SAXIHP3RVALID(slavehp_axi_rdresp_valid[3]),
.SAXIHP3RREADY(slavehp_axi_rdresp_ready[3]),
.SAXIHP3RID(slavehp_axi_rdresp_id[23:18]),
.SAXIHP3RLAST(slavehp_axi_rdresp_last[3]),
.SAXIHP3RRESP(slavehp_axi_rdresp_resp[7:6]),
.SAXIHP3WRISSUECAP1EN(slavehp_axi_wrissuecap1en[3]),
.SAXIHP3AWADDR(slavehp_axi_wrreq_addr[127:96]),
.SAXIHP3WACOUNT(slavehp_axi_wrreq_fifosize[23:18]),
.SAXIHP3AWVALID(slavehp_axi_wrreq_valid[3]),
.SAXIHP3AWREADY(slavehp_axi_wrreq_ready[3]),
.SAXIHP3AWID(slavehp_axi_wrreq_id[23:18]),
.SAXIHP3AWLOCK(slavehp_axi_wrreq_lock[7:6]),
.SAXIHP3AWCACHE(slavehp_axi_wrreq_cache[15:12]),
.SAXIHP3AWPROT(slavehp_axi_wrreq_prot[11:9]),
.SAXIHP3AWLEN(slavehp_axi_wrreq_len[15:12]),
.SAXIHP3AWSIZE(slavehp_axi_wrreq_size[7:6]),
.SAXIHP3AWBURST(slavehp_axi_wrreq_burst[7:6]),
.SAXIHP3AWQOS(slavehp_axi_wrreq_qos[15:12]),
.SAXIHP3WDATA(slavehp_axi_wrdat_data[255:192]),
.SAXIHP3WCOUNT(slavehp_axi_wrdat_fifosize[31:24]),
.SAXIHP3WVALID(slavehp_axi_wrdat_valid[3]),
.SAXIHP3WREADY(slavehp_axi_wrdat_ready[3]),
.SAXIHP3WID(slavehp_axi_wrdat_id[23:18]),
.SAXIHP3WLAST(slavehp_axi_wrdat_last[3]),
.SAXIHP3WSTRB(slavehp_axi_wrdat_mask[31:24]),
.SAXIHP3BVALID(slavehp_axi_wrresp_valid[3]),
.SAXIHP3BREADY(slavehp_axi_wrresp_ready[3]),
.SAXIHP3BID(slavehp_axi_wrresp_id[23:18]),
.SAXIHP3BRESP(slavehp_axi_wrresp_resp[7:6])
);
endmodule
|
`timescale 1ns / 1ps
// @input
// clk_src: input event detective
// switch_power: power on/off state switch
// switch_en: start/pause state switch
// sig_change: plus signal for sel_value
// @output
// sel_value
module selector_mode
#(parameter LO = 2, HI = 5, CLK_CH = 25)
(
input [31:0]clk,
input switch_power,
input switch_en,
input sig_change,
input [1:0]washing_machine_running,
output reg push,
output reg [2:0] sel_value
);
reg init_flag;
wire real_clk;
initial begin
init_flag <= 1;
sel_value <= LO;
push <= 1'b0;
end
// change signal change to level change(with clk[CLK_CH] Hz)
always @(posedge clk[CLK_CH]) begin
if (switch_power) begin
// pause
if (!switch_en) begin
// washing finished
if(washing_machine_running[1]) begin
push = 1'b1;
sel_value = LO;
// true pause
end else begin
if(init_flag) begin
sel_value = LO;
init_flag = 0;
push = 1'b0;
end
// start to change value
if (sig_change) begin
sel_value = (sel_value + 1) % (HI+1) ? (sel_value + 1) % (HI+1) : LO;
push = 1'b1;
// otherwise, keep current state
end else begin
sel_value = sel_value;
push = push;
end
end
// washing running
end else begin
push = 1'b0;
sel_value = sel_value;
end
// power off
end else begin
init_flag = 1;
sel_value = LO;
push = 1'b0;
end
end
endmodule |
`timescale 1ns / 1ps
// pwm_ctl.v ver 1.0
// Kazushi Yamashina
// [email protected]
//
// para_in <= 0 ~ 19999
// -Interval of asserting "en_out" will change
// depending on the value of the "para_in".
// -The more you increase the value the interval will increase.
//
// dir_in <= 1: positive rotate, 0: negative rotate
module pwm_ctl(
input clk,
input rst,
input [14:0] para_in,
input [0:0] dir_in,
output [0:0] dir_out,
output [0:0] en_out
);
// //copy this instance to top module
//pwm_ctl pwm_ctl
//(
//.clk(bus_clk),
// .rst(rst),
// .para_in(para_in),
// .dir_out(dir_out),
// .en_out(en_out)
//);
parameter MAX = 19999;
reg dir;
reg dir_;
reg en;
reg [14:0] in_;
reg [31:0] counter;
wire [31:0] divflag;
reg [31:0] PWMctl_clk;
initial PWMctl_clk = MAX;
initial in_ = MAX;
assign divflag = PWMctl_clk - in_;
assign dir_out = dir;
assign en_out = en;
always @(posedge clk)begin
if(rst)begin
in_ <= 19999;
dir_ <= 0;
end
else if(0 < para_in && para_in < PWMctl_clk)begin
in_ <= para_in;
dir_ <= dir_in;
end
else
in_ <= MAX;
end
always @(posedge clk)begin
if(rst)begin
dir <= 0;
en <= 0;
end
else if(divflag > counter)begin
dir <= dir_;
en <= 1;
end
else begin
en <= 0;
end
end
always @(posedge clk)begin
if(rst)begin
counter <= 0;
end
else if(PWMctl_clk == counter)
counter <= 0;
else
counter <= counter + 1;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFSBP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DFSBP_BEHAVIORAL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_df_p_s_no_pg/sky130_fd_sc_hs__u_df_p_s_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dfsbp (
CLK ,
D ,
Q ,
Q_N ,
SET_B,
VPWR ,
VGND
);
// Module ports
input CLK ;
input D ;
output Q ;
output Q_N ;
input SET_B;
input VPWR ;
input VGND ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hs__u_df_p_s_no_pg u_df_p_s_no_pg0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFSBP_BEHAVIORAL_V |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`ifdef BASIL_SBUS
`define SPLIT_BUS
`elsif BASIL_TOPSBUS
`define SPLIT_BUS
`endif
`include "gpio/gpio_core.v"
`ifndef BASIL_SBUS
`include "utils/bus_to_ip.v"
`include "gpio/gpio.v"
`else
`include "utils/sbus_to_ip.v"
`include "gpio/gpio_sbus.v"
`endif
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [15:0] BUS_ADD,
`ifndef SPLIT_BUS
inout wire [7:0] BUS_DATA,
`else
input wire [7:0] BUS_DATA_IN,
output wire [7:0] BUS_DATA_OUT,
`endif
input wire BUS_RD,
input wire BUS_WR
);
localparam GPIO_BASEADDR = 16'h0000;
localparam GPIO_HIGHADDR = 16'h000f;
localparam GPIO2_BASEADDR = 16'h0010;
localparam GPIO2_HIGHADDR = 16'h001f;
// Connect tb internal bus to external split bus
`ifdef BASIL_TOPSBUS
wire [7:0] BUS_DATA;
assign BUS_DATA = BUS_DATA_IN;
assign BUS_DATA_OUT = BUS_DATA;
`elsif BASIL_SBUS
wire [7:0] BUS_DATA_OUT_1;
wire [7:0] BUS_DATA_OUT_2;
assign BUS_DATA_OUT = BUS_DATA_OUT_1 | BUS_DATA_OUT_2;
`endif
/* verilator lint_off UNOPT */
wire [23:0] IO;
assign IO[15:8] = IO[7:0];
assign IO[23:20] = IO[19:16];
/* verilator lint_on UNOPT */
`ifndef BASIL_SBUS
gpio #(
`else
gpio_sbus #(
`endif
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.IO_WIDTH(24),
.IO_DIRECTION(24'h0000ff),
.IO_TRI(24'hff0000)
) i_gpio (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
`ifndef BASIL_SBUS
.BUS_DATA(BUS_DATA),
`else
.BUS_DATA_IN(BUS_DATA_IN),
.BUS_DATA_OUT(BUS_DATA_OUT_1),
`endif
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(IO)
);
wire [15:0] IO_2;
assign IO_2 = 16'ha5cd;
`ifndef BASIL_SBUS
gpio #(
`else
gpio_sbus #(
`endif
.BASEADDR(GPIO2_BASEADDR),
.HIGHADDR(GPIO2_HIGHADDR),
.IO_WIDTH(16),
.IO_DIRECTION(16'h0000)
) i_gpio2 (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
`ifndef BASIL_SBUS
.BUS_DATA(BUS_DATA),
`else
.BUS_DATA_IN(BUS_DATA_IN),
.BUS_DATA_OUT(BUS_DATA_OUT_2),
`endif
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(IO_2)
);
`ifndef VERILATOR_SIM
initial begin
$dumpfile("gpio.vcd");
$dumpvars(0);
end
`endif
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module tlu_controller #(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter DIVISOR = 8,
parameter WIDTH = 8,
parameter TLU_TRIGGER_MAX_CLOCK_CYCLES = 17,
parameter TIMESTAMP_N_OF_BIT = 32
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
input wire TRIGGER_CLK, // clock of the TLU FSM, usually connect clock of command sequencer here
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
output wire FIFO_PREEMPT_REQ,
output wire TRIGGER_ENABLED,
output wire [WIDTH-1:0] TRIGGER_SELECTED,
output wire TLU_ENABLED,
input wire [WIDTH-1:0] TRIGGER,
input wire [WIDTH-1:0] TRIGGER_VETO,
input wire TIMESTAMP_RESET,
input wire EXT_TRIGGER_ENABLE,
input wire TRIGGER_ACKNOWLEDGE,
output wire TRIGGER_ACCEPTED_FLAG,
input wire TLU_TRIGGER,
input wire TLU_RESET,
output wire TLU_BUSY,
output wire TLU_CLOCK,
input wire [TIMESTAMP_N_OF_BIT-1:0] EXT_TIMESTAMP,
output wire [TIMESTAMP_N_OF_BIT-1:0] TIMESTAMP
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR) ,
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
tlu_controller_core #(
.DIVISOR(DIVISOR),
.ABUSWIDTH(ABUSWIDTH),
.TLU_TRIGGER_MAX_CLOCK_CYCLES(TLU_TRIGGER_MAX_CLOCK_CYCLES),
.WIDTH(WIDTH),
.TIMESTAMP_N_OF_BIT(TIMESTAMP_N_OF_BIT)
) i_tlu_controller_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.TRIGGER_CLK(TRIGGER_CLK),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_PREEMPT_REQ(FIFO_PREEMPT_REQ),
.TRIGGER(TRIGGER),
.TRIGGER_VETO(TRIGGER_VETO),
.TIMESTAMP_RESET(TIMESTAMP_RESET),
.TRIGGER_SELECTED(TRIGGER_SELECTED),
.EXT_TRIGGER_ENABLE(EXT_TRIGGER_ENABLE),
.TRIGGER_ACKNOWLEDGE(TRIGGER_ACKNOWLEDGE),
.TRIGGER_ACCEPTED_FLAG(TRIGGER_ACCEPTED_FLAG),
.TRIGGER_ENABLED(TRIGGER_ENABLED),
.TLU_ENABLED(TLU_ENABLED),
.TLU_TRIGGER(TLU_TRIGGER),
.TLU_RESET(TLU_RESET),
.TLU_BUSY(TLU_BUSY),
.TLU_CLOCK(TLU_CLOCK),
.EXT_TIMESTAMP(EXT_TIMESTAMP),
.TIMESTAMP(TIMESTAMP)
);
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_nios2_oci_debug (
// inputs:
clk,
dbrk_break,
debugreq,
hbreak_enabled,
jdo,
jrst_n,
ocireg_ers,
ocireg_mrs,
reset,
st_ready_test_idle,
take_action_ocimem_a,
take_action_ocireg,
xbrk_break,
// outputs:
debugack,
monitor_error,
monitor_go,
monitor_ready,
oci_hbreak_req,
resetlatch,
resetrequest
)
;
output debugack;
output monitor_error;
output monitor_go;
output monitor_ready;
output oci_hbreak_req;
output resetlatch;
output resetrequest;
input clk;
input dbrk_break;
input debugreq;
input hbreak_enabled;
input [ 37: 0] jdo;
input jrst_n;
input ocireg_ers;
input ocireg_mrs;
input reset;
input st_ready_test_idle;
input take_action_ocimem_a;
input take_action_ocireg;
input xbrk_break;
reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire debugack;
reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire oci_hbreak_req;
wire reset_sync;
reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire unxcomplemented_resetxx0;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (clk),
.din (reset),
.dout (reset_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
break_on_reset <= 1'b0;
resetrequest <= 1'b0;
jtag_break <= 1'b0;
end
else if (take_action_ocimem_a)
begin
resetrequest <= jdo[22];
jtag_break <= jdo[21] ? 1
: jdo[20] ? 0
: jtag_break;
break_on_reset <= jdo[19] ? 1
: jdo[18] ? 0
: break_on_reset;
resetlatch <= jdo[24] ? 0 : resetlatch;
end
else if (reset_sync)
begin
jtag_break <= break_on_reset;
resetlatch <= 1;
end
else if (debugreq & ~debugack & break_on_reset)
jtag_break <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
monitor_ready <= 1'b0;
monitor_error <= 1'b0;
monitor_go <= 1'b0;
end
else
begin
if (take_action_ocimem_a && jdo[25])
monitor_ready <= 1'b0;
else if (take_action_ocireg && ocireg_mrs)
monitor_ready <= 1'b1;
if (take_action_ocimem_a && jdo[25])
monitor_error <= 1'b0;
else if (take_action_ocireg && ocireg_ers)
monitor_error <= 1'b1;
if (take_action_ocimem_a && jdo[23])
monitor_go <= 1'b1;
else if (st_ready_test_idle)
monitor_go <= 1'b0;
end
end
assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
assign debugack = ~hbreak_enabled;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input [ 7: 0] address;
input [ 3: 0] byteenable;
input clock;
input [ 31: 0] data;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clock),
.data_a (data),
.q_a (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 8;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_nios2_ocimem (
// inputs:
address,
byteenable,
clk,
debugaccess,
jdo,
jrst_n,
read,
take_action_ocimem_a,
take_action_ocimem_b,
take_no_action_ocimem_a,
write,
writedata,
// outputs:
MonDReg,
ociram_readdata,
waitrequest
)
;
output [ 31: 0] MonDReg;
output [ 31: 0] ociram_readdata;
output waitrequest;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input clk;
input debugaccess;
input [ 37: 0] jdo;
input jrst_n;
input read;
input take_action_ocimem_a;
input take_action_ocimem_b;
input take_no_action_ocimem_a;
input write;
input [ 31: 0] writedata;
reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 8: 0] MonARegAddrInc;
wire MonARegAddrIncAccessingRAM;
reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire avalon_ram_wr;
wire [ 31: 0] cfgrom_readdata;
reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 7: 0] ociram_addr;
wire [ 3: 0] ociram_byteenable;
wire [ 31: 0] ociram_readdata;
wire [ 31: 0] ociram_wr_data;
wire ociram_wr_en;
reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
jtag_rd <= 1'b0;
jtag_rd_d1 <= 1'b0;
jtag_ram_wr <= 1'b0;
jtag_ram_rd <= 1'b0;
jtag_ram_rd_d1 <= 1'b0;
jtag_ram_access <= 1'b0;
MonAReg <= 0;
MonDReg <= 0;
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else
begin
if (take_no_action_ocimem_a)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
jtag_rd <= 1'b1;
jtag_ram_rd <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else if (take_action_ocimem_a)
begin
MonAReg[10 : 2] <= { jdo[17],
jdo[33 : 26] };
jtag_rd <= 1'b1;
jtag_ram_rd <= ~jdo[17];
jtag_ram_access <= ~jdo[17];
end
else if (take_action_ocimem_b)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
MonDReg <= jdo[34 : 3];
jtag_ram_wr <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else
begin
jtag_rd <= 0;
jtag_ram_wr <= 0;
jtag_ram_rd <= 0;
jtag_ram_access <= 0;
if (jtag_rd_d1)
MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata;
end
jtag_rd_d1 <= jtag_rd;
jtag_ram_rd_d1 <= jtag_ram_rd;
if (~waitrequest)
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else if (write)
waitrequest <= ~address[8] & jtag_ram_access;
else if (read)
begin
avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access);
waitrequest <= ~avalon_ociram_readdata_ready;
end
else
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
end
end
assign MonARegAddrInc = MonAReg[10 : 2]+1;
assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8];
assign avalon_ram_wr = write & ~address[8] & debugaccess;
assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0];
assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata;
assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable;
assign ociram_wr_en = jtag_ram_wr | avalon_ram_wr;
//nios_system_nios2_qsys_0_ociram_sp_ram, which is an nios_sp_ram
nios_system_nios2_qsys_0_ociram_sp_ram_module nios_system_nios2_qsys_0_ociram_sp_ram
(
.address (ociram_addr),
.byteenable (ociram_byteenable),
.clock (clk),
.data (ociram_wr_data),
.q (ociram_readdata),
.wren (ociram_wr_en)
);
//synthesis translate_off
`ifdef NO_PLI
defparam nios_system_nios2_qsys_0_ociram_sp_ram.lpm_file = "nios_system_nios2_qsys_0_ociram_default_contents.dat";
`else
defparam nios_system_nios2_qsys_0_ociram_sp_ram.lpm_file = "nios_system_nios2_qsys_0_ociram_default_contents.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam nios_system_nios2_qsys_0_ociram_sp_ram.lpm_file = "nios_system_nios2_qsys_0_ociram_default_contents.mif";
//synthesis read_comments_as_HDL off
assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h01000020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001919 :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000000 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
(MonAReg[4 : 2] == 3'd5)? 32'h01000000 :
(MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
32'h00000000;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
)
;
output [ 31: 0] oci_ienable;
output [ 31: 0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [ 8: 0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [ 31: 0] writedata;
reg [ 31: 0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [ 31: 0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_single_step_mode <= 1'b0;
else if (take_action_ocireg)
oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_ienable <= 32'b00000000000000000000000000101111;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000101111);
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_nios2_oci_break (
// inputs:
clk,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
jdo,
jrst_n,
reset_n,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
xbrk_goto0,
xbrk_goto1,
// outputs:
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
trigbrktype,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3
)
;
output [ 31: 0] break_readreg;
output dbrk_hit0_latch;
output dbrk_hit1_latch;
output dbrk_hit2_latch;
output dbrk_hit3_latch;
output trigbrktype;
output trigger_state_0;
output trigger_state_1;
output [ 7: 0] xbrk_ctrl0;
output [ 7: 0] xbrk_ctrl1;
output [ 7: 0] xbrk_ctrl2;
output [ 7: 0] xbrk_ctrl3;
input clk;
input dbrk_break;
input dbrk_goto0;
input dbrk_goto1;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_break_a;
input take_action_break_b;
input take_action_break_c;
input take_no_action_break_a;
input take_no_action_break_b;
input take_no_action_break_c;
input xbrk_goto0;
input xbrk_goto1;
wire [ 3: 0] break_a_wpr;
wire [ 1: 0] break_a_wpr_high_bits;
wire [ 1: 0] break_a_wpr_low_bits;
wire [ 1: 0] break_b_rr;
wire [ 1: 0] break_c_rr;
reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire dbrk0_high_value;
wire dbrk0_low_value;
wire dbrk1_high_value;
wire dbrk1_low_value;
wire dbrk2_high_value;
wire dbrk2_low_value;
wire dbrk3_high_value;
wire dbrk3_low_value;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire take_action_any_break;
reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg trigger_state;
wire trigger_state_0;
wire trigger_state_1;
wire [ 31: 0] xbrk0_value;
wire [ 31: 0] xbrk1_value;
wire [ 31: 0] xbrk2_value;
wire [ 31: 0] xbrk3_value;
reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
assign break_a_wpr = jdo[35 : 32];
assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
assign break_b_rr = jdo[33 : 32];
assign break_c_rr = jdo[33 : 32];
assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
xbrk_ctrl0 <= 0;
xbrk_ctrl1 <= 0;
xbrk_ctrl2 <= 0;
xbrk_ctrl3 <= 0;
trigbrktype <= 0;
end
else
begin
if (take_action_any_break)
trigbrktype <= 0;
else if (dbrk_break)
trigbrktype <= 1;
if (take_action_break_b)
begin
if ((break_b_rr == 2'b00) && (0 >= 1))
begin
xbrk_ctrl0[0] <= jdo[27];
xbrk_ctrl0[1] <= jdo[28];
xbrk_ctrl0[2] <= jdo[29];
xbrk_ctrl0[3] <= jdo[30];
xbrk_ctrl0[4] <= jdo[21];
xbrk_ctrl0[5] <= jdo[20];
xbrk_ctrl0[6] <= jdo[19];
xbrk_ctrl0[7] <= jdo[18];
end
if ((break_b_rr == 2'b01) && (0 >= 2))
begin
xbrk_ctrl1[0] <= jdo[27];
xbrk_ctrl1[1] <= jdo[28];
xbrk_ctrl1[2] <= jdo[29];
xbrk_ctrl1[3] <= jdo[30];
xbrk_ctrl1[4] <= jdo[21];
xbrk_ctrl1[5] <= jdo[20];
xbrk_ctrl1[6] <= jdo[19];
xbrk_ctrl1[7] <= jdo[18];
end
if ((break_b_rr == 2'b10) && (0 >= 3))
begin
xbrk_ctrl2[0] <= jdo[27];
xbrk_ctrl2[1] <= jdo[28];
xbrk_ctrl2[2] <= jdo[29];
xbrk_ctrl2[3] <= jdo[30];
xbrk_ctrl2[4] <= jdo[21];
xbrk_ctrl2[5] <= jdo[20];
xbrk_ctrl2[6] <= jdo[19];
xbrk_ctrl2[7] <= jdo[18];
end
if ((break_b_rr == 2'b11) && (0 >= 4))
begin
xbrk_ctrl3[0] <= jdo[27];
xbrk_ctrl3[1] <= jdo[28];
xbrk_ctrl3[2] <= jdo[29];
xbrk_ctrl3[3] <= jdo[30];
xbrk_ctrl3[4] <= jdo[21];
xbrk_ctrl3[5] <= jdo[20];
xbrk_ctrl3[6] <= jdo[19];
xbrk_ctrl3[7] <= jdo[18];
end
end
end
end
assign dbrk_hit0_latch = 1'b0;
assign dbrk0_low_value = 0;
assign dbrk0_high_value = 0;
assign dbrk_hit1_latch = 1'b0;
assign dbrk1_low_value = 0;
assign dbrk1_high_value = 0;
assign dbrk_hit2_latch = 1'b0;
assign dbrk2_low_value = 0;
assign dbrk2_high_value = 0;
assign dbrk_hit3_latch = 1'b0;
assign dbrk3_low_value = 0;
assign dbrk3_high_value = 0;
assign xbrk0_value = 32'b0;
assign xbrk1_value = 32'b0;
assign xbrk2_value = 32'b0;
assign xbrk3_value = 32'b0;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
break_readreg <= 32'b0;
else if (take_action_any_break)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_a)
case (break_a_wpr_high_bits)
2'd0: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= xbrk0_value;
end // 2'd0
2'd1: begin
break_readreg <= xbrk1_value;
end // 2'd1
2'd2: begin
break_readreg <= xbrk2_value;
end // 2'd2
2'd3: begin
break_readreg <= xbrk3_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd0
2'd1: begin
break_readreg <= 32'b0;
end // 2'd1
2'd2: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_low_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_low_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_low_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_low_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd2
2'd3: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_high_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_high_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_high_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_high_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd3
endcase // break_a_wpr_high_bits
else if (take_no_action_break_b)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_c)
break_readreg <= jdo[31 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trigger_state <= 0;
else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
trigger_state <= 0;
else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
trigger_state <= -1;
end
assign trigger_state_0 = ~trigger_state;
assign trigger_state_1 = trigger_state;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_nios2_oci_xbrk (
// inputs:
D_valid,
E_valid,
F_pc,
clk,
reset_n,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3,
// outputs:
xbrk_break,
xbrk_goto0,
xbrk_goto1,
xbrk_traceoff,
xbrk_traceon,
xbrk_trigout
)
;
output xbrk_break;
output xbrk_goto0;
output xbrk_goto1;
output xbrk_traceoff;
output xbrk_traceon;
output xbrk_trigout;
input D_valid;
input E_valid;
input [ 22: 0] F_pc;
input clk;
input reset_n;
input trigger_state_0;
input trigger_state_1;
input [ 7: 0] xbrk_ctrl0;
input [ 7: 0] xbrk_ctrl1;
input [ 7: 0] xbrk_ctrl2;
input [ 7: 0] xbrk_ctrl3;
wire D_cpu_addr_en;
wire E_cpu_addr_en;
reg E_xbrk_goto0;
reg E_xbrk_goto1;
reg E_xbrk_traceoff;
reg E_xbrk_traceon;
reg E_xbrk_trigout;
wire [ 24: 0] cpu_i_address;
wire xbrk0_armed;
wire xbrk0_break_hit;
wire xbrk0_goto0_hit;
wire xbrk0_goto1_hit;
wire xbrk0_toff_hit;
wire xbrk0_ton_hit;
wire xbrk0_tout_hit;
wire xbrk1_armed;
wire xbrk1_break_hit;
wire xbrk1_goto0_hit;
wire xbrk1_goto1_hit;
wire xbrk1_toff_hit;
wire xbrk1_ton_hit;
wire xbrk1_tout_hit;
wire xbrk2_armed;
wire xbrk2_break_hit;
wire xbrk2_goto0_hit;
wire xbrk2_goto1_hit;
wire xbrk2_toff_hit;
wire xbrk2_ton_hit;
wire xbrk2_tout_hit;
wire xbrk3_armed;
wire xbrk3_break_hit;
wire xbrk3_goto0_hit;
wire xbrk3_goto1_hit;
wire xbrk3_toff_hit;
wire xbrk3_ton_hit;
wire xbrk3_tout_hit;
reg xbrk_break;
wire xbrk_break_hit;
wire xbrk_goto0;
wire xbrk_goto0_hit;
wire xbrk_goto1;
wire xbrk_goto1_hit;
wire xbrk_toff_hit;
wire xbrk_ton_hit;
wire xbrk_tout_hit;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
assign cpu_i_address = {F_pc, 2'b00};
assign D_cpu_addr_en = D_valid;
assign E_cpu_addr_en = E_valid;
assign xbrk0_break_hit = 0;
assign xbrk0_ton_hit = 0;
assign xbrk0_toff_hit = 0;
assign xbrk0_tout_hit = 0;
assign xbrk0_goto0_hit = 0;
assign xbrk0_goto1_hit = 0;
assign xbrk1_break_hit = 0;
assign xbrk1_ton_hit = 0;
assign xbrk1_toff_hit = 0;
assign xbrk1_tout_hit = 0;
assign xbrk1_goto0_hit = 0;
assign xbrk1_goto1_hit = 0;
assign xbrk2_break_hit = 0;
assign xbrk2_ton_hit = 0;
assign xbrk2_toff_hit = 0;
assign xbrk2_tout_hit = 0;
assign xbrk2_goto0_hit = 0;
assign xbrk2_goto1_hit = 0;
assign xbrk3_break_hit = 0;
assign xbrk3_ton_hit = 0;
assign xbrk3_toff_hit = 0;
assign xbrk3_tout_hit = 0;
assign xbrk3_goto0_hit = 0;
assign xbrk3_goto1_hit = 0;
assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
xbrk_break <= 0;
else if (E_cpu_addr_en)
xbrk_break <= xbrk_break_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceon <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceon <= xbrk_ton_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceoff <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceoff <= xbrk_toff_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_trigout <= 0;
else if (E_cpu_addr_en)
E_xbrk_trigout <= xbrk_tout_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto0 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto0 <= xbrk_goto0_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto1 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto1 <= xbrk_goto1_hit;
end
assign xbrk_traceon = 1'b0;
assign xbrk_traceoff = 1'b0;
assign xbrk_trigout = 1'b0;
assign xbrk_goto0 = 1'b0;
assign xbrk_goto1 = 1'b0;
assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
(xbrk_ctrl0[5] & trigger_state_1);
assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
(xbrk_ctrl1[5] & trigger_state_1);
assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
(xbrk_ctrl2[5] & trigger_state_1);
assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
(xbrk_ctrl3[5] & trigger_state_1);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_nios2_oci_dbrk (
// inputs:
E_st_data,
av_ld_data_aligned_filtered,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugack,
reset_n,
// outputs:
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dbrk_trigout
)
;
output [ 24: 0] cpu_d_address;
output cpu_d_read;
output [ 31: 0] cpu_d_readdata;
output cpu_d_wait;
output cpu_d_write;
output [ 31: 0] cpu_d_writedata;
output dbrk_break;
output dbrk_goto0;
output dbrk_goto1;
output dbrk_traceme;
output dbrk_traceoff;
output dbrk_traceon;
output dbrk_trigout;
input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered;
input clk;
input [ 24: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugack;
input reset_n;
wire [ 24: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk0_armed;
wire dbrk0_break_pulse;
wire dbrk0_goto0;
wire dbrk0_goto1;
wire dbrk0_traceme;
wire dbrk0_traceoff;
wire dbrk0_traceon;
wire dbrk0_trigout;
wire dbrk1_armed;
wire dbrk1_break_pulse;
wire dbrk1_goto0;
wire dbrk1_goto1;
wire dbrk1_traceme;
wire dbrk1_traceoff;
wire dbrk1_traceon;
wire dbrk1_trigout;
wire dbrk2_armed;
wire dbrk2_break_pulse;
wire dbrk2_goto0;
wire dbrk2_goto1;
wire dbrk2_traceme;
wire dbrk2_traceoff;
wire dbrk2_traceon;
wire dbrk2_trigout;
wire dbrk3_armed;
wire dbrk3_break_pulse;
wire dbrk3_goto0;
wire dbrk3_goto1;
wire dbrk3_traceme;
wire dbrk3_traceoff;
wire dbrk3_traceon;
wire dbrk3_trigout;
reg dbrk_break;
reg dbrk_break_pulse;
wire [ 31: 0] dbrk_data;
reg dbrk_goto0;
reg dbrk_goto1;
reg dbrk_traceme;
reg dbrk_traceoff;
reg dbrk_traceon;
reg dbrk_trigout;
assign cpu_d_address = d_address;
assign cpu_d_readdata = av_ld_data_aligned_filtered;
assign cpu_d_read = d_read;
assign cpu_d_writedata = E_st_data;
assign cpu_d_write = d_write;
assign cpu_d_wait = d_waitrequest;
assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbrk_break <= 0;
else
dbrk_break <= dbrk_break ? ~debugack
: dbrk_break_pulse;
end
assign dbrk0_armed = 1'b0;
assign dbrk0_trigout = 1'b0;
assign dbrk0_break_pulse = 1'b0;
assign dbrk0_traceoff = 1'b0;
assign dbrk0_traceon = 1'b0;
assign dbrk0_traceme = 1'b0;
assign dbrk0_goto0 = 1'b0;
assign dbrk0_goto1 = 1'b0;
assign dbrk1_armed = 1'b0;
assign dbrk1_trigout = 1'b0;
assign dbrk1_break_pulse = 1'b0;
assign dbrk1_traceoff = 1'b0;
assign dbrk1_traceon = 1'b0;
assign dbrk1_traceme = 1'b0;
assign dbrk1_goto0 = 1'b0;
assign dbrk1_goto1 = 1'b0;
assign dbrk2_armed = 1'b0;
assign dbrk2_trigout = 1'b0;
assign dbrk2_break_pulse = 1'b0;
assign dbrk2_traceoff = 1'b0;
assign dbrk2_traceon = 1'b0;
assign dbrk2_traceme = 1'b0;
assign dbrk2_goto0 = 1'b0;
assign dbrk2_goto1 = 1'b0;
assign dbrk3_armed = 1'b0;
assign dbrk3_trigout = 1'b0;
assign dbrk3_break_pulse = 1'b0;
assign dbrk3_traceoff = 1'b0;
assign dbrk3_traceon = 1'b0;
assign dbrk3_traceme = 1'b0;
assign dbrk3_goto0 = 1'b0;
assign dbrk3_goto1 = 1'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dbrk_trigout <= 0;
dbrk_break_pulse <= 0;
dbrk_traceoff <= 0;
dbrk_traceon <= 0;
dbrk_traceme <= 0;
dbrk_goto0 <= 0;
dbrk_goto1 <= 0;
end
else
begin
dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_nios2_oci_itrace (
// inputs:
clk,
dbrk_traceoff,
dbrk_traceon,
jdo,
jrst_n,
take_action_tracectrl,
trc_enb,
xbrk_traceoff,
xbrk_traceon,
xbrk_wrap_traceoff,
// outputs:
dct_buffer,
dct_count,
itm,
trc_ctrl,
trc_on
)
;
output [ 29: 0] dct_buffer;
output [ 3: 0] dct_count;
output [ 35: 0] itm;
output [ 15: 0] trc_ctrl;
output trc_on;
input clk;
input dbrk_traceoff;
input dbrk_traceon;
input [ 15: 0] jdo;
input jrst_n;
input take_action_tracectrl;
input trc_enb;
input xbrk_traceoff;
input xbrk_traceon;
input xbrk_wrap_traceoff;
wire curr_pid;
reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] dct_code;
reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dct_is_taken;
wire [ 31: 0] excaddr;
wire instr_retired;
wire is_advanced_exception;
wire is_cond_dct;
wire is_dct;
wire is_exception_no_break;
wire is_fast_tlb_miss_exception;
wire is_idct;
reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire not_in_debug_mode;
reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_excaddr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exctype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_dct_outcome_in_sync;
wire record_itrace;
wire [ 31: 0] retired_pcb;
reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] sync_code;
wire [ 6: 0] sync_interval;
wire sync_pending;
reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 6: 0] sync_timer_next;
reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 15: 0] trc_ctrl;
reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire trc_on;
assign is_cond_dct = 1'b0;
assign is_dct = 1'b0;
assign dct_is_taken = 1'b0;
assign is_idct = 1'b0;
assign retired_pcb = 32'b0;
assign not_in_debug_mode = 1'b0;
assign instr_retired = 1'b0;
assign is_advanced_exception = 1'b0;
assign is_exception_no_break = 1'b0;
assign is_fast_tlb_miss_exception = 1'b0;
assign curr_pid = 1'b0;
assign excaddr = 32'b0;
assign sync_code = trc_ctrl[3 : 2];
assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
assign sync_pending = sync_timer == 0;
assign record_dct_outcome_in_sync = dct_is_taken & sync_pending;
assign sync_timer_next = sync_pending ? sync_timer : (sync_timer - 1);
assign record_itrace = trc_on & trc_ctrl[4];
assign dct_code = {is_cond_dct, dct_is_taken};
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trc_clear <= 0;
else
trc_clear <= ~trc_enb &
take_action_tracectrl & jdo[4];
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exctype <= 1'b0;
pending_excaddr <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else if (trc_clear || (!0 && !0))
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exctype <= 1'b0;
pending_excaddr <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else
begin
if (!prev_pid_valid)
begin
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if (instr_retired | is_advanced_exception)
begin
if (~record_itrace)
pending_frametype <= 4'b1010;
else if (is_exception_no_break)
begin
pending_frametype <= 4'b0010;
pending_excaddr <= excaddr;
if (is_fast_tlb_miss_exception)
pending_exctype <= 1'b1;
else
pending_exctype <= 1'b0;
end
else if (is_idct)
pending_frametype <= 4'b1001;
else if (record_dct_outcome_in_sync)
pending_frametype <= 4'b1000;
else if (!is_dct & snapped_pid)
begin
pending_frametype <= 4'b0011;
pending_curr_pid <= snapped_curr_pid;
pending_prev_pid <= snapped_prev_pid;
snapped_pid <= 0;
end
else
pending_frametype <= 4'b0000;
if ((dct_count != 0) &
(~record_itrace |
is_exception_no_break |
is_idct |
record_dct_outcome_in_sync |
(!is_dct & snapped_pid)))
begin
itm <= {4'b0001, dct_buffer, 2'b00};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
begin
if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~is_advanced_exception)
begin
dct_buffer <= {dct_code, dct_buffer[29 : 2]};
dct_count <= dct_count + 1;
end
if (record_itrace & (pending_frametype == 4'b0010))
itm <= {4'b0010, pending_excaddr[31 : 1], pending_exctype};
else if (record_itrace & (
(pending_frametype == 4'b1000) |
(pending_frametype == 4'b1010) |
(pending_frametype == 4'b1001)))
begin
itm <= {pending_frametype, retired_pcb};
sync_timer <= sync_interval;
if (0 &
((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) &
!snapped_pid & prev_pid_valid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
end
end
else if (record_itrace &
0 & (pending_frametype == 4'b0011))
itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid};
else if (record_itrace & is_dct)
begin
if (dct_count == 4'd15)
begin
itm <= {4'b0001, dct_code, dct_buffer};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
itm <= 4'b0000;
end
else
itm <= {4'b0000, 32'b0};
end
end
else
itm <= {4'b0000, 32'b0};
end
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_ctrl_reg[0] <= 1'b0;
trc_ctrl_reg[1] <= 1'b0;
trc_ctrl_reg[3 : 2] <= 2'b00;
trc_ctrl_reg[4] <= 1'b0;
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 0;
trc_ctrl_reg[9] <= 1'b0;
trc_ctrl_reg[10] <= 1'b0;
end
else if (take_action_tracectrl)
begin
trc_ctrl_reg[0] <= jdo[5];
trc_ctrl_reg[1] <= jdo[6];
trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
trc_ctrl_reg[4] <= jdo[9];
trc_ctrl_reg[9] <= jdo[14];
trc_ctrl_reg[10] <= jdo[2];
if (0)
trc_ctrl_reg[7 : 5] <= jdo[12 : 10];
if (0 & 0)
trc_ctrl_reg[8] <= jdo[13];
end
else if (xbrk_wrap_traceoff)
begin
trc_ctrl_reg[1] <= 0;
trc_ctrl_reg[0] <= 0;
end
else if (dbrk_traceoff | xbrk_traceoff)
trc_ctrl_reg[1] <= 0;
else if (trc_ctrl_reg[0] &
(dbrk_traceon | xbrk_traceon))
trc_ctrl_reg[1] <= 1;
end
assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0;
assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
)
;
output [ 3: 0] td_mode;
input [ 8: 0] ctrl;
wire [ 2: 0] ctrl_bits_for_mux;
reg [ 3: 0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux)
begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
)
;
output [ 35: 0] atm;
output [ 35: 0] dtm;
input clk;
input [ 24: 0] cpu_d_address;
input cpu_d_read;
input [ 31: 0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [ 31: 0] cpu_d_writedata;
input jrst_n;
input [ 15: 0] trc_ctrl;
reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 31: 0] cpu_d_address_0_padded;
wire [ 31: 0] cpu_d_readdata_0_padded;
wire [ 31: 0] cpu_d_writedata_0_padded;
reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3: 0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//nios_system_nios2_qsys_0_nios2_oci_trc_ctrl_td_mode, which is an e_instance
nios_system_nios2_qsys_0_nios2_oci_td_mode nios_system_nios2_qsys_0_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode (td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
atm <= 0;
dtm <= 0;
end
else if (0)
begin
if (cpu_d_write & ~cpu_d_wait & record_store_addr)
atm <= {4'b0101, cpu_d_address_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_addr)
atm <= {4'b0100, cpu_d_address_0_padded};
else
atm <= {4'b0000, cpu_d_address_0_padded};
if (cpu_d_write & ~cpu_d_wait & record_store_data)
dtm <= {4'b0111, cpu_d_writedata_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_data)
dtm <= {4'b0110, cpu_d_readdata_0_padded};
else
dtm <= {4'b0000, cpu_d_readdata_0_padded};
end
else
begin
atm <= 0;
dtm <= 0;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
)
;
output [ 1: 0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [ 1: 0] compute_tm_count;
wire [ 2: 0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux)
begin
case (switch_for_mux)
3'b000: begin
compute_tm_count = 0;
end // 3'b000
3'b001: begin
compute_tm_count = 1;
end // 3'b001
3'b010: begin
compute_tm_count = 1;
end // 3'b010
3'b011: begin
compute_tm_count = 2;
end // 3'b011
3'b100: begin
compute_tm_count = 1;
end // 3'b100
3'b101: begin
compute_tm_count = 2;
end // 3'b101
3'b110: begin
compute_tm_count = 2;
end // 3'b110
3'b111: begin
compute_tm_count = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
)
;
output [ 3: 0] fifowp_inc;
input free2;
input free3;
input [ 1: 0] tm_count;
reg [ 3: 0] fifowp_inc;
always @(free2 or free3 or tm_count)
begin
if (free3 & (tm_count == 3))
fifowp_inc = 3;
else if (free2 & (tm_count >= 2))
fifowp_inc = 2;
else if (tm_count >= 1)
fifowp_inc = 1;
else
fifowp_inc = 0;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
)
;
output [ 4: 0] fifocount_inc;
input empty;
input free2;
input free3;
input [ 1: 0] tm_count;
reg [ 4: 0] fifocount_inc;
always @(empty or free2 or free3 or tm_count)
begin
if (empty)
fifocount_inc = tm_count[1 : 0];
else if (free3 & (tm_count == 3))
fifocount_inc = 2;
else if (free2 & (tm_count >= 2))
fifocount_inc = 1;
else if (tm_count >= 1)
fifocount_inc = 0;
else
fifocount_inc = {5{1'b1}};
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_nios2_oci_fifo (
// inputs:
atm,
clk,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dct_buffer,
dct_count,
dtm,
itm,
jrst_n,
reset_n,
test_ending,
test_has_ended,
trc_on,
// outputs:
tw
)
;
output [ 35: 0] tw;
input [ 35: 0] atm;
input clk;
input dbrk_traceme;
input dbrk_traceoff;
input dbrk_traceon;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input [ 35: 0] dtm;
input [ 35: 0] itm;
input jrst_n;
input reset_n;
input test_ending;
input test_has_ended;
input trc_on;
wire atm_valid;
wire [ 1: 0] compute_tm_count_tm_count;
wire dtm_valid;
wire empty;
reg [ 35: 0] fifo_0;
wire fifo_0_enable;
wire [ 35: 0] fifo_0_mux;
reg [ 35: 0] fifo_1;
reg [ 35: 0] fifo_10;
wire fifo_10_enable;
wire [ 35: 0] fifo_10_mux;
reg [ 35: 0] fifo_11;
wire fifo_11_enable;
wire [ 35: 0] fifo_11_mux;
reg [ 35: 0] fifo_12;
wire fifo_12_enable;
wire [ 35: 0] fifo_12_mux;
reg [ 35: 0] fifo_13;
wire fifo_13_enable;
wire [ 35: 0] fifo_13_mux;
reg [ 35: 0] fifo_14;
wire fifo_14_enable;
wire [ 35: 0] fifo_14_mux;
reg [ 35: 0] fifo_15;
wire fifo_15_enable;
wire [ 35: 0] fifo_15_mux;
wire fifo_1_enable;
wire [ 35: 0] fifo_1_mux;
reg [ 35: 0] fifo_2;
wire fifo_2_enable;
wire [ 35: 0] fifo_2_mux;
reg [ 35: 0] fifo_3;
wire fifo_3_enable;
wire [ 35: 0] fifo_3_mux;
reg [ 35: 0] fifo_4;
wire fifo_4_enable;
wire [ 35: 0] fifo_4_mux;
reg [ 35: 0] fifo_5;
wire fifo_5_enable;
wire [ 35: 0] fifo_5_mux;
reg [ 35: 0] fifo_6;
wire fifo_6_enable;
wire [ 35: 0] fifo_6_mux;
reg [ 35: 0] fifo_7;
wire fifo_7_enable;
wire [ 35: 0] fifo_7_mux;
reg [ 35: 0] fifo_8;
wire fifo_8_enable;
wire [ 35: 0] fifo_8_mux;
reg [ 35: 0] fifo_9;
wire fifo_9_enable;
wire [ 35: 0] fifo_9_mux;
wire [ 35: 0] fifo_read_mux;
reg [ 4: 0] fifocount /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 4: 0] fifocount_inc_fifocount;
wire [ 35: 0] fifohead;
reg [ 3: 0] fiforp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] fifowp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 3: 0] fifowp1;
wire [ 3: 0] fifowp2;
wire [ 3: 0] fifowp_inc_fifowp;
wire free2;
wire free3;
wire itm_valid;
reg ovf_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] ovr_pending_atm;
wire [ 35: 0] ovr_pending_dtm;
wire [ 1: 0] tm_count;
wire tm_count_ge1;
wire tm_count_ge2;
wire tm_count_ge3;
wire trc_this;
wire [ 35: 0] tw;
assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
assign itm_valid = |itm[35 : 32];
assign atm_valid = |atm[35 : 32] & trc_this;
assign dtm_valid = |dtm[35 : 32] & trc_this;
assign free2 = ~fifocount[4];
assign free3 = ~fifocount[4] & ~&fifocount[3 : 0];
assign empty = ~|fifocount;
assign fifowp1 = fifowp + 1;
assign fifowp2 = fifowp + 2;
//nios_system_nios2_qsys_0_nios2_oci_compute_tm_count_tm_count, which is an e_instance
nios_system_nios2_qsys_0_nios2_oci_compute_tm_count nios_system_nios2_qsys_0_nios2_oci_compute_tm_count_tm_count
(
.atm_valid (atm_valid),
.compute_tm_count (compute_tm_count_tm_count),
.dtm_valid (dtm_valid),
.itm_valid (itm_valid)
);
assign tm_count = compute_tm_count_tm_count;
//nios_system_nios2_qsys_0_nios2_oci_fifowp_inc_fifowp, which is an e_instance
nios_system_nios2_qsys_0_nios2_oci_fifowp_inc nios_system_nios2_qsys_0_nios2_oci_fifowp_inc_fifowp
(
.fifowp_inc (fifowp_inc_fifowp),
.free2 (free2),
.free3 (free3),
.tm_count (tm_count)
);
//nios_system_nios2_qsys_0_nios2_oci_fifocount_inc_fifocount, which is an e_instance
nios_system_nios2_qsys_0_nios2_oci_fifocount_inc nios_system_nios2_qsys_0_nios2_oci_fifocount_inc_fifocount
(
.empty (empty),
.fifocount_inc (fifocount_inc_fifocount),
.free2 (free2),
.free3 (free3),
.tm_count (tm_count)
);
//the_nios_system_nios2_qsys_0_oci_test_bench, which is an e_instance
nios_system_nios2_qsys_0_oci_test_bench the_nios_system_nios2_qsys_0_oci_test_bench
(
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.test_ending (test_ending),
.test_has_ended (test_has_ended)
);
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
fiforp <= 0;
fifowp <= 0;
fifocount <= 0;
ovf_pending <= 1;
end
else
begin
fifowp <= fifowp + fifowp_inc_fifowp;
fifocount <= fifocount + fifocount_inc_fifocount;
if (~empty)
fiforp <= fiforp + 1;
if (~trc_this || (~free2 & tm_count[1]) || (~free3 & (&tm_count)))
ovf_pending <= 1;
else if (atm_valid | dtm_valid)
ovf_pending <= 0;
end
end
assign fifohead = fifo_read_mux;
assign tw = 0 ? { (empty ? 4'h0 : fifohead[35 : 32]), fifohead[31 : 0]} : itm;
assign fifo_0_enable = ((fifowp == 4'd0) && tm_count_ge1) || (free2 && (fifowp1== 4'd0) && tm_count_ge2) ||(free3 && (fifowp2== 4'd0) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_0 <= 0;
else if (fifo_0_enable)
fifo_0 <= fifo_0_mux;
end
assign fifo_0_mux = (((fifowp == 4'd0) && itm_valid))? itm :
(((fifowp == 4'd0) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd0) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd0) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd0) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd0) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_1_enable = ((fifowp == 4'd1) && tm_count_ge1) || (free2 && (fifowp1== 4'd1) && tm_count_ge2) ||(free3 && (fifowp2== 4'd1) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_1 <= 0;
else if (fifo_1_enable)
fifo_1 <= fifo_1_mux;
end
assign fifo_1_mux = (((fifowp == 4'd1) && itm_valid))? itm :
(((fifowp == 4'd1) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd1) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd1) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd1) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd1) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_2_enable = ((fifowp == 4'd2) && tm_count_ge1) || (free2 && (fifowp1== 4'd2) && tm_count_ge2) ||(free3 && (fifowp2== 4'd2) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_2 <= 0;
else if (fifo_2_enable)
fifo_2 <= fifo_2_mux;
end
assign fifo_2_mux = (((fifowp == 4'd2) && itm_valid))? itm :
(((fifowp == 4'd2) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd2) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd2) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd2) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd2) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_3_enable = ((fifowp == 4'd3) && tm_count_ge1) || (free2 && (fifowp1== 4'd3) && tm_count_ge2) ||(free3 && (fifowp2== 4'd3) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_3 <= 0;
else if (fifo_3_enable)
fifo_3 <= fifo_3_mux;
end
assign fifo_3_mux = (((fifowp == 4'd3) && itm_valid))? itm :
(((fifowp == 4'd3) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd3) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd3) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd3) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd3) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_4_enable = ((fifowp == 4'd4) && tm_count_ge1) || (free2 && (fifowp1== 4'd4) && tm_count_ge2) ||(free3 && (fifowp2== 4'd4) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_4 <= 0;
else if (fifo_4_enable)
fifo_4 <= fifo_4_mux;
end
assign fifo_4_mux = (((fifowp == 4'd4) && itm_valid))? itm :
(((fifowp == 4'd4) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd4) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd4) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd4) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd4) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_5_enable = ((fifowp == 4'd5) && tm_count_ge1) || (free2 && (fifowp1== 4'd5) && tm_count_ge2) ||(free3 && (fifowp2== 4'd5) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_5 <= 0;
else if (fifo_5_enable)
fifo_5 <= fifo_5_mux;
end
assign fifo_5_mux = (((fifowp == 4'd5) && itm_valid))? itm :
(((fifowp == 4'd5) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd5) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd5) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd5) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd5) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_6_enable = ((fifowp == 4'd6) && tm_count_ge1) || (free2 && (fifowp1== 4'd6) && tm_count_ge2) ||(free3 && (fifowp2== 4'd6) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_6 <= 0;
else if (fifo_6_enable)
fifo_6 <= fifo_6_mux;
end
assign fifo_6_mux = (((fifowp == 4'd6) && itm_valid))? itm :
(((fifowp == 4'd6) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd6) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd6) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd6) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd6) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_7_enable = ((fifowp == 4'd7) && tm_count_ge1) || (free2 && (fifowp1== 4'd7) && tm_count_ge2) ||(free3 && (fifowp2== 4'd7) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_7 <= 0;
else if (fifo_7_enable)
fifo_7 <= fifo_7_mux;
end
assign fifo_7_mux = (((fifowp == 4'd7) && itm_valid))? itm :
(((fifowp == 4'd7) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd7) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd7) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd7) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd7) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_8_enable = ((fifowp == 4'd8) && tm_count_ge1) || (free2 && (fifowp1== 4'd8) && tm_count_ge2) ||(free3 && (fifowp2== 4'd8) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_8 <= 0;
else if (fifo_8_enable)
fifo_8 <= fifo_8_mux;
end
assign fifo_8_mux = (((fifowp == 4'd8) && itm_valid))? itm :
(((fifowp == 4'd8) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd8) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd8) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd8) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd8) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_9_enable = ((fifowp == 4'd9) && tm_count_ge1) || (free2 && (fifowp1== 4'd9) && tm_count_ge2) ||(free3 && (fifowp2== 4'd9) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_9 <= 0;
else if (fifo_9_enable)
fifo_9 <= fifo_9_mux;
end
assign fifo_9_mux = (((fifowp == 4'd9) && itm_valid))? itm :
(((fifowp == 4'd9) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd9) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd9) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd9) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd9) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_10_enable = ((fifowp == 4'd10) && tm_count_ge1) || (free2 && (fifowp1== 4'd10) && tm_count_ge2) ||(free3 && (fifowp2== 4'd10) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_10 <= 0;
else if (fifo_10_enable)
fifo_10 <= fifo_10_mux;
end
assign fifo_10_mux = (((fifowp == 4'd10) && itm_valid))? itm :
(((fifowp == 4'd10) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd10) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd10) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd10) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd10) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_11_enable = ((fifowp == 4'd11) && tm_count_ge1) || (free2 && (fifowp1== 4'd11) && tm_count_ge2) ||(free3 && (fifowp2== 4'd11) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_11 <= 0;
else if (fifo_11_enable)
fifo_11 <= fifo_11_mux;
end
assign fifo_11_mux = (((fifowp == 4'd11) && itm_valid))? itm :
(((fifowp == 4'd11) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd11) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd11) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd11) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd11) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_12_enable = ((fifowp == 4'd12) && tm_count_ge1) || (free2 && (fifowp1== 4'd12) && tm_count_ge2) ||(free3 && (fifowp2== 4'd12) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_12 <= 0;
else if (fifo_12_enable)
fifo_12 <= fifo_12_mux;
end
assign fifo_12_mux = (((fifowp == 4'd12) && itm_valid))? itm :
(((fifowp == 4'd12) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd12) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd12) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd12) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd12) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_13_enable = ((fifowp == 4'd13) && tm_count_ge1) || (free2 && (fifowp1== 4'd13) && tm_count_ge2) ||(free3 && (fifowp2== 4'd13) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_13 <= 0;
else if (fifo_13_enable)
fifo_13 <= fifo_13_mux;
end
assign fifo_13_mux = (((fifowp == 4'd13) && itm_valid))? itm :
(((fifowp == 4'd13) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd13) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd13) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd13) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd13) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_14_enable = ((fifowp == 4'd14) && tm_count_ge1) || (free2 && (fifowp1== 4'd14) && tm_count_ge2) ||(free3 && (fifowp2== 4'd14) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_14 <= 0;
else if (fifo_14_enable)
fifo_14 <= fifo_14_mux;
end
assign fifo_14_mux = (((fifowp == 4'd14) && itm_valid))? itm :
(((fifowp == 4'd14) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd14) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd14) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd14) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd14) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_15_enable = ((fifowp == 4'd15) && tm_count_ge1) || (free2 && (fifowp1== 4'd15) && tm_count_ge2) ||(free3 && (fifowp2== 4'd15) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_15 <= 0;
else if (fifo_15_enable)
fifo_15 <= fifo_15_mux;
end
assign fifo_15_mux = (((fifowp == 4'd15) && itm_valid))? itm :
(((fifowp == 4'd15) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd15) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd15) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd15) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd15) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign tm_count_ge1 = |tm_count;
assign tm_count_ge2 = tm_count[1];
assign tm_count_ge3 = &tm_count;
assign ovr_pending_atm = {ovf_pending, atm[34 : 0]};
assign ovr_pending_dtm = {ovf_pending, dtm[34 : 0]};
assign fifo_read_mux = (fiforp == 4'd0)? fifo_0 :
(fiforp == 4'd1)? fifo_1 :
(fiforp == 4'd2)? fifo_2 :
(fiforp == 4'd3)? fifo_3 :
(fiforp == 4'd4)? fifo_4 :
(fiforp == 4'd5)? fifo_5 :
(fiforp == 4'd6)? fifo_6 :
(fiforp == 4'd7)? fifo_7 :
(fiforp == 4'd8)? fifo_8 :
(fiforp == 4'd9)? fifo_9 :
(fiforp == 4'd10)? fifo_10 :
(fiforp == 4'd11)? fifo_11 :
(fiforp == 4'd12)? fifo_12 :
(fiforp == 4'd13)? fifo_13 :
(fiforp == 4'd14)? fifo_14 :
fifo_15;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
)
;
output tr_clk;
output [ 17: 0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [ 35: 0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 17: 0] tr_data;
reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
assign phase = x1^x2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
x1 <= 0;
else
x1 <= ~x1;
end
always @(posedge clkx2 or negedge jrst_n)
begin
if (jrst_n == 0)
begin
x2 <= 0;
tr_clk_reg <= 0;
tr_data_reg <= 0;
end
else
begin
x2 <= x1;
tr_clk_reg <= ~phase;
tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18];
end
end
assign tr_clk = 0 ? tr_clk_reg : 0;
assign tr_data = 0 ? tr_data_reg : 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
)
;
output tracemem_on;
output [ 35: 0] tracemem_trcdata;
output tracemem_tw;
output trc_enb;
output [ 6: 0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_tracectrl;
input take_action_tracemem_a;
input take_action_tracemem_b;
input take_no_action_tracemem_a;
input [ 15: 0] trc_ctrl;
input [ 35: 0] tw;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire trc_enb;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 35: 0] trc_im_data;
reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (!0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (take_action_tracectrl &&
(jdo[4] | jdo[3]))
begin
if (jdo[4])
trc_im_addr <= 0;
if (jdo[3])
trc_wrap <= 0;
end
else if (trc_enb & trc_on_chip & tw_valid)
begin
trc_im_addr <= trc_im_addr+1;
if (&trc_im_addr)
trc_wrap <= 1;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trc_jtag_addr <= 0;
else if (take_action_tracemem_a ||
take_no_action_tracemem_a ||
take_action_tracemem_b)
trc_jtag_addr <= take_action_tracemem_a ?
jdo[35 : 19] :
trc_jtag_addr + 1;
end
assign trc_enb = trc_ctrl[0];
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_tw = trc_wrap;
assign tracemem_on = trc_enb;
assign tracemem_trcdata = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_nios2_performance_monitors
;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_nios2_oci (
// inputs:
D_valid,
E_st_data,
E_valid,
F_pc,
address_nxt,
av_ld_data_aligned_filtered,
byteenable_nxt,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugaccess_nxt,
hbreak_enabled,
read_nxt,
reset,
reset_n,
test_ending,
test_has_ended,
write_nxt,
writedata_nxt,
// outputs:
jtag_debug_module_debugaccess_to_roms,
oci_hbreak_req,
oci_ienable,
oci_single_step_mode,
readdata,
resetrequest,
waitrequest
)
;
output jtag_debug_module_debugaccess_to_roms;
output oci_hbreak_req;
output [ 31: 0] oci_ienable;
output oci_single_step_mode;
output [ 31: 0] readdata;
output resetrequest;
output waitrequest;
input D_valid;
input [ 31: 0] E_st_data;
input E_valid;
input [ 22: 0] F_pc;
input [ 8: 0] address_nxt;
input [ 31: 0] av_ld_data_aligned_filtered;
input [ 3: 0] byteenable_nxt;
input clk;
input [ 24: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugaccess_nxt;
input hbreak_enabled;
input read_nxt;
input reset;
input reset_n;
input test_ending;
input test_has_ended;
input write_nxt;
input [ 31: 0] writedata_nxt;
wire [ 31: 0] MonDReg;
reg [ 8: 0] address;
wire [ 35: 0] atm;
wire [ 31: 0] break_readreg;
reg [ 3: 0] byteenable;
wire clkx2;
wire [ 24: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk_break;
wire dbrk_goto0;
wire dbrk_goto1;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire dbrk_traceme;
wire dbrk_traceoff;
wire dbrk_traceon;
wire dbrk_trigout;
wire [ 29: 0] dct_buffer;
wire [ 3: 0] dct_count;
reg debugaccess;
wire debugack;
wire debugreq;
wire [ 35: 0] dtm;
wire dummy_sink;
wire [ 35: 0] itm;
wire [ 37: 0] jdo;
wire jrst_n;
wire jtag_debug_module_debugaccess_to_roms;
wire monitor_error;
wire monitor_go;
wire monitor_ready;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire [ 31: 0] oci_reg_readdata;
wire oci_single_step_mode;
wire [ 31: 0] ociram_readdata;
wire ocireg_ers;
wire ocireg_mrs;
reg read;
reg [ 31: 0] readdata;
wire resetlatch;
wire resetrequest;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_ocireg;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire tr_clk;
wire [ 17: 0] tr_data;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire [ 15: 0] trc_ctrl;
wire trc_enb;
wire [ 6: 0] trc_im_addr;
wire trc_on;
wire trc_wrap;
wire trigbrktype;
wire trigger_state_0;
wire trigger_state_1;
wire trigout;
wire [ 35: 0] tw;
wire waitrequest;
reg write;
reg [ 31: 0] writedata;
wire xbrk_break;
wire [ 7: 0] xbrk_ctrl0;
wire [ 7: 0] xbrk_ctrl1;
wire [ 7: 0] xbrk_ctrl2;
wire [ 7: 0] xbrk_ctrl3;
wire xbrk_goto0;
wire xbrk_goto1;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
wire xbrk_wrap_traceoff;
nios_system_nios2_qsys_0_nios2_oci_debug the_nios_system_nios2_qsys_0_nios2_oci_debug
(
.clk (clk),
.dbrk_break (dbrk_break),
.debugack (debugack),
.debugreq (debugreq),
.hbreak_enabled (hbreak_enabled),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_hbreak_req (oci_hbreak_req),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset (reset),
.resetlatch (resetlatch),
.resetrequest (resetrequest),
.st_ready_test_idle (st_ready_test_idle),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocireg (take_action_ocireg),
.xbrk_break (xbrk_break)
);
nios_system_nios2_qsys_0_nios2_ocimem the_nios_system_nios2_qsys_0_nios2_ocimem
(
.MonDReg (MonDReg),
.address (address),
.byteenable (byteenable),
.clk (clk),
.debugaccess (debugaccess),
.jdo (jdo),
.jrst_n (jrst_n),
.ociram_readdata (ociram_readdata),
.read (read),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata)
);
nios_system_nios2_qsys_0_nios2_avalon_reg the_nios_system_nios2_qsys_0_nios2_avalon_reg
(
.address (address),
.clk (clk),
.debugaccess (debugaccess),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_ienable (oci_ienable),
.oci_reg_readdata (oci_reg_readdata),
.oci_single_step_mode (oci_single_step_mode),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset_n (reset_n),
.take_action_ocireg (take_action_ocireg),
.write (write),
.writedata (writedata)
);
nios_system_nios2_qsys_0_nios2_oci_break the_nios_system_nios2_qsys_0_nios2_oci_break
(
.break_readreg (break_readreg),
.clk (clk),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.trigbrktype (trigbrktype),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1)
);
nios_system_nios2_qsys_0_nios2_oci_xbrk the_nios_system_nios2_qsys_0_nios2_oci_xbrk
(
.D_valid (D_valid),
.E_valid (E_valid),
.F_pc (F_pc),
.clk (clk),
.reset_n (reset_n),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_break (xbrk_break),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_trigout (xbrk_trigout)
);
nios_system_nios2_qsys_0_nios2_oci_dbrk the_nios_system_nios2_qsys_0_nios2_oci_dbrk
(
.E_st_data (E_st_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dbrk_trigout (dbrk_trigout),
.debugack (debugack),
.reset_n (reset_n)
);
nios_system_nios2_qsys_0_nios2_oci_itrace the_nios_system_nios2_qsys_0_nios2_oci_itrace
(
.clk (clk),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.itm (itm),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_tracectrl (take_action_tracectrl),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_on (trc_on),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
nios_system_nios2_qsys_0_nios2_oci_dtrace the_nios_system_nios2_qsys_0_nios2_oci_dtrace
(
.atm (atm),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.dtm (dtm),
.jrst_n (jrst_n),
.trc_ctrl (trc_ctrl)
);
nios_system_nios2_qsys_0_nios2_oci_fifo the_nios_system_nios2_qsys_0_nios2_oci_fifo
(
.atm (atm),
.clk (clk),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.dtm (dtm),
.itm (itm),
.jrst_n (jrst_n),
.reset_n (reset_n),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.trc_on (trc_on),
.tw (tw)
);
nios_system_nios2_qsys_0_nios2_oci_pib the_nios_system_nios2_qsys_0_nios2_oci_pib
(
.clk (clk),
.clkx2 (clkx2),
.jrst_n (jrst_n),
.tr_clk (tr_clk),
.tr_data (tr_data),
.tw (tw)
);
nios_system_nios2_qsys_0_nios2_oci_im the_nios_system_nios2_qsys_0_nios2_oci_im
(
.clk (clk),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_im_addr (trc_im_addr),
.trc_wrap (trc_wrap),
.tw (tw),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
assign trigout = dbrk_trigout | xbrk_trigout;
assign jtag_debug_module_debugaccess_to_roms = debugack;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
address <= 0;
else
address <= address_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
byteenable <= 0;
else
byteenable <= byteenable_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
writedata <= 0;
else
writedata <= writedata_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
debugaccess <= 0;
else
debugaccess <= debugaccess_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
read <= 0;
else
read <= read ? waitrequest : read_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
write <= 0;
else
write <= write ? waitrequest : write_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
readdata <= 0;
else
readdata <= address[8] ? oci_reg_readdata : ociram_readdata;
end
nios_system_nios2_qsys_0_jtag_debug_module_wrapper the_nios_system_nios2_qsys_0_jtag_debug_module_wrapper
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.clk (clk),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.st_ready_test_idle (st_ready_test_idle),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1)
);
//dummy sink, which is an e_mux
assign dummy_sink = tr_clk |
tr_data |
trigout |
debugack;
assign debugreq = 0;
assign clkx2 = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0 (
// inputs:
clk,
d_irq,
d_readdata,
d_waitrequest,
i_readdata,
i_waitrequest,
jtag_debug_module_address,
jtag_debug_module_byteenable,
jtag_debug_module_debugaccess,
jtag_debug_module_read,
jtag_debug_module_write,
jtag_debug_module_writedata,
reset_n,
// outputs:
d_address,
d_byteenable,
d_read,
d_write,
d_writedata,
i_address,
i_read,
jtag_debug_module_debugaccess_to_roms,
jtag_debug_module_readdata,
jtag_debug_module_resetrequest,
jtag_debug_module_waitrequest,
no_ci_readra
)
;
output [ 24: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
output [ 31: 0] d_writedata;
output [ 24: 0] i_address;
output i_read;
output jtag_debug_module_debugaccess_to_roms;
output [ 31: 0] jtag_debug_module_readdata;
output jtag_debug_module_resetrequest;
output jtag_debug_module_waitrequest;
output no_ci_readra;
input clk;
input [ 31: 0] d_irq;
input [ 31: 0] d_readdata;
input d_waitrequest;
input [ 31: 0] i_readdata;
input i_waitrequest;
input [ 8: 0] jtag_debug_module_address;
input [ 3: 0] jtag_debug_module_byteenable;
input jtag_debug_module_debugaccess;
input jtag_debug_module_read;
input jtag_debug_module_write;
input [ 31: 0] jtag_debug_module_writedata;
input reset_n;
wire [ 1: 0] D_compare_op;
wire D_ctrl_alu_force_xor;
wire D_ctrl_alu_signed_comparison;
wire D_ctrl_alu_subtract;
wire D_ctrl_b_is_dst;
wire D_ctrl_br;
wire D_ctrl_br_cmp;
wire D_ctrl_br_uncond;
wire D_ctrl_break;
wire D_ctrl_crst;
wire D_ctrl_custom;
wire D_ctrl_custom_multi;
wire D_ctrl_exception;
wire D_ctrl_force_src2_zero;
wire D_ctrl_hi_imm16;
wire D_ctrl_ignore_dst;
wire D_ctrl_implicit_dst_eretaddr;
wire D_ctrl_implicit_dst_retaddr;
wire D_ctrl_jmp_direct;
wire D_ctrl_jmp_indirect;
wire D_ctrl_ld;
wire D_ctrl_ld_io;
wire D_ctrl_ld_non_io;
wire D_ctrl_ld_signed;
wire D_ctrl_logic;
wire D_ctrl_rdctl_inst;
wire D_ctrl_retaddr;
wire D_ctrl_rot_right;
wire D_ctrl_shift_logical;
wire D_ctrl_shift_right_arith;
wire D_ctrl_shift_rot;
wire D_ctrl_shift_rot_right;
wire D_ctrl_src2_choose_imm;
wire D_ctrl_st;
wire D_ctrl_uncond_cti_non_br;
wire D_ctrl_unsigned_lo_imm16;
wire D_ctrl_wrctl_inst;
wire [ 4: 0] D_dst_regnum;
wire [ 55: 0] D_inst;
reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 4: 0] D_iw_a;
wire [ 4: 0] D_iw_b;
wire [ 4: 0] D_iw_c;
wire [ 2: 0] D_iw_control_regnum;
wire [ 7: 0] D_iw_custom_n;
wire D_iw_custom_readra;
wire D_iw_custom_readrb;
wire D_iw_custom_writerc;
wire [ 15: 0] D_iw_imm16;
wire [ 25: 0] D_iw_imm26;
wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 4: 0] D_iw_shift_imm5;
wire [ 4: 0] D_iw_trap_break_imm5;
wire [ 22: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
wire D_mem32;
wire D_mem8;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
reg D_valid;
wire [ 55: 0] D_vinst;
wire D_wr_dst_reg;
wire [ 31: 0] E_alu_result;
reg E_alu_sub;
wire [ 32: 0] E_arith_result;
wire [ 31: 0] E_arith_src1;
wire [ 31: 0] E_arith_src2;
wire E_ci_multi_stall;
wire [ 31: 0] E_ci_result;
wire E_cmp_result;
wire [ 31: 0] E_control_rd_data;
wire E_eq;
reg E_invert_arith_src_msb;
wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 24: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
reg [ 4: 0] E_shift_rot_cnt;
wire [ 4: 0] E_shift_rot_cnt_nxt;
wire E_shift_rot_done;
wire E_shift_rot_fill_bit;
reg [ 31: 0] E_shift_rot_result;
wire [ 31: 0] E_shift_rot_result_nxt;
wire E_shift_rot_stall;
reg [ 31: 0] E_src1;
reg [ 31: 0] E_src2;
wire [ 31: 0] E_st_data;
wire E_st_stall;
wire E_stall;
reg E_valid;
wire [ 55: 0] E_vinst;
wire E_wrctl_bstatus;
wire E_wrctl_estatus;
wire E_wrctl_ienable;
wire E_wrctl_status;
wire [ 31: 0] F_av_iw;
wire [ 4: 0] F_av_iw_a;
wire [ 4: 0] F_av_iw_b;
wire [ 4: 0] F_av_iw_c;
wire [ 2: 0] F_av_iw_control_regnum;
wire [ 7: 0] F_av_iw_custom_n;
wire F_av_iw_custom_readra;
wire F_av_iw_custom_readrb;
wire F_av_iw_custom_writerc;
wire [ 15: 0] F_av_iw_imm16;
wire [ 25: 0] F_av_iw_imm26;
wire [ 4: 0] F_av_iw_imm5;
wire [ 1: 0] F_av_iw_memsz;
wire [ 5: 0] F_av_iw_op;
wire [ 5: 0] F_av_iw_opx;
wire [ 4: 0] F_av_iw_shift_imm5;
wire [ 4: 0] F_av_iw_trap_break_imm5;
wire F_av_mem16;
wire F_av_mem32;
wire F_av_mem8;
wire [ 55: 0] F_inst;
wire [ 31: 0] F_iw;
wire [ 4: 0] F_iw_a;
wire [ 4: 0] F_iw_b;
wire [ 4: 0] F_iw_c;
wire [ 2: 0] F_iw_control_regnum;
wire [ 7: 0] F_iw_custom_n;
wire F_iw_custom_readra;
wire F_iw_custom_readrb;
wire F_iw_custom_writerc;
wire [ 15: 0] F_iw_imm16;
wire [ 25: 0] F_iw_imm26;
wire [ 4: 0] F_iw_imm5;
wire [ 1: 0] F_iw_memsz;
wire [ 5: 0] F_iw_op;
wire [ 5: 0] F_iw_opx;
wire [ 4: 0] F_iw_shift_imm5;
wire [ 4: 0] F_iw_trap_break_imm5;
wire F_mem16;
wire F_mem32;
wire F_mem8;
wire F_op_add;
wire F_op_addi;
wire F_op_and;
wire F_op_andhi;
wire F_op_andi;
wire F_op_beq;
wire F_op_bge;
wire F_op_bgeu;
wire F_op_blt;
wire F_op_bltu;
wire F_op_bne;
wire F_op_br;
wire F_op_break;
wire F_op_bret;
wire F_op_call;
wire F_op_callr;
wire F_op_cmpeq;
wire F_op_cmpeqi;
wire F_op_cmpge;
wire F_op_cmpgei;
wire F_op_cmpgeu;
wire F_op_cmpgeui;
wire F_op_cmplt;
wire F_op_cmplti;
wire F_op_cmpltu;
wire F_op_cmpltui;
wire F_op_cmpne;
wire F_op_cmpnei;
wire F_op_crst;
wire F_op_custom;
wire F_op_div;
wire F_op_divu;
wire F_op_eret;
wire F_op_flushd;
wire F_op_flushda;
wire F_op_flushi;
wire F_op_flushp;
wire F_op_hbreak;
wire F_op_initd;
wire F_op_initda;
wire F_op_initi;
wire F_op_intr;
wire F_op_jmp;
wire F_op_jmpi;
wire F_op_ldb;
wire F_op_ldbio;
wire F_op_ldbu;
wire F_op_ldbuio;
wire F_op_ldh;
wire F_op_ldhio;
wire F_op_ldhu;
wire F_op_ldhuio;
wire F_op_ldl;
wire F_op_ldw;
wire F_op_ldwio;
wire F_op_mul;
wire F_op_muli;
wire F_op_mulxss;
wire F_op_mulxsu;
wire F_op_mulxuu;
wire F_op_nextpc;
wire F_op_nor;
wire F_op_opx;
wire F_op_or;
wire F_op_orhi;
wire F_op_ori;
wire F_op_rdctl;
wire F_op_rdprs;
wire F_op_ret;
wire F_op_rol;
wire F_op_roli;
wire F_op_ror;
wire F_op_rsv02;
wire F_op_rsv09;
wire F_op_rsv10;
wire F_op_rsv17;
wire F_op_rsv18;
wire F_op_rsv25;
wire F_op_rsv26;
wire F_op_rsv33;
wire F_op_rsv34;
wire F_op_rsv41;
wire F_op_rsv42;
wire F_op_rsv49;
wire F_op_rsv57;
wire F_op_rsv61;
wire F_op_rsv62;
wire F_op_rsv63;
wire F_op_rsvx00;
wire F_op_rsvx10;
wire F_op_rsvx15;
wire F_op_rsvx17;
wire F_op_rsvx21;
wire F_op_rsvx25;
wire F_op_rsvx33;
wire F_op_rsvx34;
wire F_op_rsvx35;
wire F_op_rsvx42;
wire F_op_rsvx43;
wire F_op_rsvx44;
wire F_op_rsvx47;
wire F_op_rsvx50;
wire F_op_rsvx51;
wire F_op_rsvx55;
wire F_op_rsvx56;
wire F_op_rsvx60;
wire F_op_rsvx63;
wire F_op_sll;
wire F_op_slli;
wire F_op_sra;
wire F_op_srai;
wire F_op_srl;
wire F_op_srli;
wire F_op_stb;
wire F_op_stbio;
wire F_op_stc;
wire F_op_sth;
wire F_op_sthio;
wire F_op_stw;
wire F_op_stwio;
wire F_op_sub;
wire F_op_sync;
wire F_op_trap;
wire F_op_wrctl;
wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 22: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 22: 0] F_pc_no_crst_nxt;
wire [ 22: 0] F_pc_nxt;
wire [ 22: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 24: 0] F_pcb;
wire [ 24: 0] F_pcb_nxt;
wire [ 24: 0] F_pcb_plus_four;
wire F_valid;
wire [ 55: 0] F_vinst;
reg [ 1: 0] R_compare_op;
reg R_ctrl_alu_force_xor;
wire R_ctrl_alu_force_xor_nxt;
reg R_ctrl_alu_signed_comparison;
wire R_ctrl_alu_signed_comparison_nxt;
reg R_ctrl_alu_subtract;
wire R_ctrl_alu_subtract_nxt;
reg R_ctrl_b_is_dst;
wire R_ctrl_b_is_dst_nxt;
reg R_ctrl_br;
reg R_ctrl_br_cmp;
wire R_ctrl_br_cmp_nxt;
wire R_ctrl_br_nxt;
reg R_ctrl_br_uncond;
wire R_ctrl_br_uncond_nxt;
reg R_ctrl_break;
wire R_ctrl_break_nxt;
reg R_ctrl_crst;
wire R_ctrl_crst_nxt;
reg R_ctrl_custom;
reg R_ctrl_custom_multi;
wire R_ctrl_custom_multi_nxt;
wire R_ctrl_custom_nxt;
reg R_ctrl_exception;
wire R_ctrl_exception_nxt;
reg R_ctrl_force_src2_zero;
wire R_ctrl_force_src2_zero_nxt;
reg R_ctrl_hi_imm16;
wire R_ctrl_hi_imm16_nxt;
reg R_ctrl_ignore_dst;
wire R_ctrl_ignore_dst_nxt;
reg R_ctrl_implicit_dst_eretaddr;
wire R_ctrl_implicit_dst_eretaddr_nxt;
reg R_ctrl_implicit_dst_retaddr;
wire R_ctrl_implicit_dst_retaddr_nxt;
reg R_ctrl_jmp_direct;
wire R_ctrl_jmp_direct_nxt;
reg R_ctrl_jmp_indirect;
wire R_ctrl_jmp_indirect_nxt;
reg R_ctrl_ld;
reg R_ctrl_ld_io;
wire R_ctrl_ld_io_nxt;
reg R_ctrl_ld_non_io;
wire R_ctrl_ld_non_io_nxt;
wire R_ctrl_ld_nxt;
reg R_ctrl_ld_signed;
wire R_ctrl_ld_signed_nxt;
reg R_ctrl_logic;
wire R_ctrl_logic_nxt;
reg R_ctrl_rdctl_inst;
wire R_ctrl_rdctl_inst_nxt;
reg R_ctrl_retaddr;
wire R_ctrl_retaddr_nxt;
reg R_ctrl_rot_right;
wire R_ctrl_rot_right_nxt;
reg R_ctrl_shift_logical;
wire R_ctrl_shift_logical_nxt;
reg R_ctrl_shift_right_arith;
wire R_ctrl_shift_right_arith_nxt;
reg R_ctrl_shift_rot;
wire R_ctrl_shift_rot_nxt;
reg R_ctrl_shift_rot_right;
wire R_ctrl_shift_rot_right_nxt;
reg R_ctrl_src2_choose_imm;
wire R_ctrl_src2_choose_imm_nxt;
reg R_ctrl_st;
wire R_ctrl_st_nxt;
reg R_ctrl_uncond_cti_non_br;
wire R_ctrl_uncond_cti_non_br_nxt;
reg R_ctrl_unsigned_lo_imm16;
wire R_ctrl_unsigned_lo_imm16_nxt;
reg R_ctrl_wrctl_inst;
wire R_ctrl_wrctl_inst_nxt;
reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire R_en;
reg [ 1: 0] R_logic_op;
wire [ 31: 0] R_rf_a;
wire [ 31: 0] R_rf_b;
wire [ 31: 0] R_src1;
wire [ 31: 0] R_src2;
wire [ 15: 0] R_src2_hi;
wire [ 15: 0] R_src2_lo;
reg R_src2_use_imm;
wire [ 7: 0] R_stb_data;
wire [ 15: 0] R_sth_data;
reg R_valid;
wire [ 55: 0] R_vinst;
reg R_wr_dst_reg;
reg [ 31: 0] W_alu_result;
wire W_br_taken;
reg W_bstatus_reg;
wire W_bstatus_reg_inst_nxt;
wire W_bstatus_reg_nxt;
reg W_cmp_result;
reg [ 31: 0] W_control_rd_data;
reg W_estatus_reg;
wire W_estatus_reg_inst_nxt;
wire W_estatus_reg_nxt;
reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 24: 0] W_mem_baddr;
wire [ 31: 0] W_rf_wr_data;
wire W_rf_wren;
wire W_status_reg;
reg W_status_reg_pie;
wire W_status_reg_pie_inst_nxt;
wire W_status_reg_pie_nxt;
reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 55: 0] W_vinst;
wire [ 31: 0] W_wr_data;
wire [ 31: 0] W_wr_data_non_zero;
wire av_fill_bit;
reg [ 1: 0] av_ld_align_cycle;
wire [ 1: 0] av_ld_align_cycle_nxt;
wire av_ld_align_one_more_cycle;
reg av_ld_aligning_data;
wire av_ld_aligning_data_nxt;
reg [ 7: 0] av_ld_byte0_data;
wire [ 7: 0] av_ld_byte0_data_nxt;
reg [ 7: 0] av_ld_byte1_data;
wire av_ld_byte1_data_en;
wire [ 7: 0] av_ld_byte1_data_nxt;
reg [ 7: 0] av_ld_byte2_data;
wire [ 7: 0] av_ld_byte2_data_nxt;
reg [ 7: 0] av_ld_byte3_data;
wire [ 7: 0] av_ld_byte3_data_nxt;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire [ 31: 0] av_ld_data_aligned_unfiltered;
wire av_ld_done;
wire av_ld_extend;
wire av_ld_getting_data;
wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 24: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
wire d_write;
wire d_write_nxt;
reg [ 31: 0] d_writedata;
reg hbreak_enabled;
reg hbreak_pending;
wire hbreak_pending_nxt;
wire hbreak_req;
wire [ 24: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
wire intr_req;
wire jtag_debug_module_clk;
wire jtag_debug_module_debugaccess_to_roms;
wire [ 31: 0] jtag_debug_module_readdata;
wire jtag_debug_module_reset;
wire jtag_debug_module_resetrequest;
wire jtag_debug_module_waitrequest;
wire no_ci_readra;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire oci_single_step_mode;
wire oci_tb_hbreak_req;
wire test_ending;
wire test_has_ended;
reg wait_for_one_post_bret_inst;
//the_nios_system_nios2_qsys_0_test_bench, which is an e_instance
nios_system_nios2_qsys_0_test_bench the_nios_system_nios2_qsys_0_test_bench
(
.D_iw (D_iw),
.D_iw_op (D_iw_op),
.D_iw_opx (D_iw_opx),
.D_valid (D_valid),
.E_valid (E_valid),
.F_pcb (F_pcb),
.F_valid (F_valid),
.R_ctrl_ld (R_ctrl_ld),
.R_ctrl_ld_non_io (R_ctrl_ld_non_io),
.R_dst_regnum (R_dst_regnum),
.R_wr_dst_reg (R_wr_dst_reg),
.W_valid (W_valid),
.W_vinst (W_vinst),
.W_wr_data (W_wr_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
.clk (clk),
.d_address (d_address),
.d_byteenable (d_byteenable),
.d_read (d_read),
.d_write (d_write),
.d_write_nxt (d_write_nxt),
.i_address (i_address),
.i_read (i_read),
.i_readdata (i_readdata),
.i_waitrequest (i_waitrequest),
.reset_n (reset_n),
.test_has_ended (test_has_ended)
);
assign F_av_iw_a = F_av_iw[31 : 27];
assign F_av_iw_b = F_av_iw[26 : 22];
assign F_av_iw_c = F_av_iw[21 : 17];
assign F_av_iw_custom_n = F_av_iw[13 : 6];
assign F_av_iw_custom_readra = F_av_iw[16];
assign F_av_iw_custom_readrb = F_av_iw[15];
assign F_av_iw_custom_writerc = F_av_iw[14];
assign F_av_iw_opx = F_av_iw[16 : 11];
assign F_av_iw_op = F_av_iw[5 : 0];
assign F_av_iw_shift_imm5 = F_av_iw[10 : 6];
assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm16 = F_av_iw[21 : 6];
assign F_av_iw_imm26 = F_av_iw[31 : 6];
assign F_av_iw_memsz = F_av_iw[4 : 3];
assign F_av_iw_control_regnum = F_av_iw[8 : 6];
assign F_av_mem8 = F_av_iw_memsz == 2'b00;
assign F_av_mem16 = F_av_iw_memsz == 2'b01;
assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
assign F_iw_a = F_iw[31 : 27];
assign F_iw_b = F_iw[26 : 22];
assign F_iw_c = F_iw[21 : 17];
assign F_iw_custom_n = F_iw[13 : 6];
assign F_iw_custom_readra = F_iw[16];
assign F_iw_custom_readrb = F_iw[15];
assign F_iw_custom_writerc = F_iw[14];
assign F_iw_opx = F_iw[16 : 11];
assign F_iw_op = F_iw[5 : 0];
assign F_iw_shift_imm5 = F_iw[10 : 6];
assign F_iw_trap_break_imm5 = F_iw[10 : 6];
assign F_iw_imm5 = F_iw[10 : 6];
assign F_iw_imm16 = F_iw[21 : 6];
assign F_iw_imm26 = F_iw[31 : 6];
assign F_iw_memsz = F_iw[4 : 3];
assign F_iw_control_regnum = F_iw[8 : 6];
assign F_mem8 = F_iw_memsz == 2'b00;
assign F_mem16 = F_iw_memsz == 2'b01;
assign F_mem32 = F_iw_memsz[1] == 1'b1;
assign D_iw_a = D_iw[31 : 27];
assign D_iw_b = D_iw[26 : 22];
assign D_iw_c = D_iw[21 : 17];
assign D_iw_custom_n = D_iw[13 : 6];
assign D_iw_custom_readra = D_iw[16];
assign D_iw_custom_readrb = D_iw[15];
assign D_iw_custom_writerc = D_iw[14];
assign D_iw_opx = D_iw[16 : 11];
assign D_iw_op = D_iw[5 : 0];
assign D_iw_shift_imm5 = D_iw[10 : 6];
assign D_iw_trap_break_imm5 = D_iw[10 : 6];
assign D_iw_imm5 = D_iw[10 : 6];
assign D_iw_imm16 = D_iw[21 : 6];
assign D_iw_imm26 = D_iw[31 : 6];
assign D_iw_memsz = D_iw[4 : 3];
assign D_iw_control_regnum = D_iw[8 : 6];
assign D_mem8 = D_iw_memsz == 2'b00;
assign D_mem16 = D_iw_memsz == 2'b01;
assign D_mem32 = D_iw_memsz[1] == 1'b1;
assign F_op_call = F_iw_op == 0;
assign F_op_jmpi = F_iw_op == 1;
assign F_op_ldbu = F_iw_op == 3;
assign F_op_addi = F_iw_op == 4;
assign F_op_stb = F_iw_op == 5;
assign F_op_br = F_iw_op == 6;
assign F_op_ldb = F_iw_op == 7;
assign F_op_cmpgei = F_iw_op == 8;
assign F_op_ldhu = F_iw_op == 11;
assign F_op_andi = F_iw_op == 12;
assign F_op_sth = F_iw_op == 13;
assign F_op_bge = F_iw_op == 14;
assign F_op_ldh = F_iw_op == 15;
assign F_op_cmplti = F_iw_op == 16;
assign F_op_initda = F_iw_op == 19;
assign F_op_ori = F_iw_op == 20;
assign F_op_stw = F_iw_op == 21;
assign F_op_blt = F_iw_op == 22;
assign F_op_ldw = F_iw_op == 23;
assign F_op_cmpnei = F_iw_op == 24;
assign F_op_flushda = F_iw_op == 27;
assign F_op_xori = F_iw_op == 28;
assign F_op_stc = F_iw_op == 29;
assign F_op_bne = F_iw_op == 30;
assign F_op_ldl = F_iw_op == 31;
assign F_op_cmpeqi = F_iw_op == 32;
assign F_op_ldbuio = F_iw_op == 35;
assign F_op_muli = F_iw_op == 36;
assign F_op_stbio = F_iw_op == 37;
assign F_op_beq = F_iw_op == 38;
assign F_op_ldbio = F_iw_op == 39;
assign F_op_cmpgeui = F_iw_op == 40;
assign F_op_ldhuio = F_iw_op == 43;
assign F_op_andhi = F_iw_op == 44;
assign F_op_sthio = F_iw_op == 45;
assign F_op_bgeu = F_iw_op == 46;
assign F_op_ldhio = F_iw_op == 47;
assign F_op_cmpltui = F_iw_op == 48;
assign F_op_initd = F_iw_op == 51;
assign F_op_orhi = F_iw_op == 52;
assign F_op_stwio = F_iw_op == 53;
assign F_op_bltu = F_iw_op == 54;
assign F_op_ldwio = F_iw_op == 55;
assign F_op_rdprs = F_iw_op == 56;
assign F_op_flushd = F_iw_op == 59;
assign F_op_xorhi = F_iw_op == 60;
assign F_op_rsv02 = F_iw_op == 2;
assign F_op_rsv09 = F_iw_op == 9;
assign F_op_rsv10 = F_iw_op == 10;
assign F_op_rsv17 = F_iw_op == 17;
assign F_op_rsv18 = F_iw_op == 18;
assign F_op_rsv25 = F_iw_op == 25;
assign F_op_rsv26 = F_iw_op == 26;
assign F_op_rsv33 = F_iw_op == 33;
assign F_op_rsv34 = F_iw_op == 34;
assign F_op_rsv41 = F_iw_op == 41;
assign F_op_rsv42 = F_iw_op == 42;
assign F_op_rsv49 = F_iw_op == 49;
assign F_op_rsv57 = F_iw_op == 57;
assign F_op_rsv61 = F_iw_op == 61;
assign F_op_rsv62 = F_iw_op == 62;
assign F_op_rsv63 = F_iw_op == 63;
assign F_op_eret = F_op_opx & (F_iw_opx == 1);
assign F_op_roli = F_op_opx & (F_iw_opx == 2);
assign F_op_rol = F_op_opx & (F_iw_opx == 3);
assign F_op_flushp = F_op_opx & (F_iw_opx == 4);
assign F_op_ret = F_op_opx & (F_iw_opx == 5);
assign F_op_nor = F_op_opx & (F_iw_opx == 6);
assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7);
assign F_op_cmpge = F_op_opx & (F_iw_opx == 8);
assign F_op_bret = F_op_opx & (F_iw_opx == 9);
assign F_op_ror = F_op_opx & (F_iw_opx == 11);
assign F_op_flushi = F_op_opx & (F_iw_opx == 12);
assign F_op_jmp = F_op_opx & (F_iw_opx == 13);
assign F_op_and = F_op_opx & (F_iw_opx == 14);
assign F_op_cmplt = F_op_opx & (F_iw_opx == 16);
assign F_op_slli = F_op_opx & (F_iw_opx == 18);
assign F_op_sll = F_op_opx & (F_iw_opx == 19);
assign F_op_wrprs = F_op_opx & (F_iw_opx == 20);
assign F_op_or = F_op_opx & (F_iw_opx == 22);
assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23);
assign F_op_cmpne = F_op_opx & (F_iw_opx == 24);
assign F_op_srli = F_op_opx & (F_iw_opx == 26);
assign F_op_srl = F_op_opx & (F_iw_opx == 27);
assign F_op_nextpc = F_op_opx & (F_iw_opx == 28);
assign F_op_callr = F_op_opx & (F_iw_opx == 29);
assign F_op_xor = F_op_opx & (F_iw_opx == 30);
assign F_op_mulxss = F_op_opx & (F_iw_opx == 31);
assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32);
assign F_op_divu = F_op_opx & (F_iw_opx == 36);
assign F_op_div = F_op_opx & (F_iw_opx == 37);
assign F_op_rdctl = F_op_opx & (F_iw_opx == 38);
assign F_op_mul = F_op_opx & (F_iw_opx == 39);
assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40);
assign F_op_initi = F_op_opx & (F_iw_opx == 41);
assign F_op_trap = F_op_opx & (F_iw_opx == 45);
assign F_op_wrctl = F_op_opx & (F_iw_opx == 46);
assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48);
assign F_op_add = F_op_opx & (F_iw_opx == 49);
assign F_op_break = F_op_opx & (F_iw_opx == 52);
assign F_op_hbreak = F_op_opx & (F_iw_opx == 53);
assign F_op_sync = F_op_opx & (F_iw_opx == 54);
assign F_op_sub = F_op_opx & (F_iw_opx == 57);
assign F_op_srai = F_op_opx & (F_iw_opx == 58);
assign F_op_sra = F_op_opx & (F_iw_opx == 59);
assign F_op_intr = F_op_opx & (F_iw_opx == 61);
assign F_op_crst = F_op_opx & (F_iw_opx == 62);
assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0);
assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10);
assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15);
assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17);
assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21);
assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25);
assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33);
assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34);
assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35);
assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42);
assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43);
assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44);
assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47);
assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50);
assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51);
assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55);
assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56);
assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60);
assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63);
assign F_op_opx = F_iw_op == 58;
assign F_op_custom = F_iw_op == 50;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
assign R_en = 1'b1;
assign E_ci_result = 0;
//custom_instruction_master, which is an e_custom_instruction_master
assign no_ci_readra = 1'b0;
assign E_ci_multi_stall = 1'b0;
assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000101111;
assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 :
R_ctrl_break ? 2'b01 :
(W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 :
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 4194312 :
(F_pc_sel_nxt == 2'b01)? 1544 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[24 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
assign F_pcb_nxt = {F_pc_nxt, 2'b00};
assign F_pc_en = W_valid;
assign F_pc_plus_one = F_pc + 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
F_pc <= 4194304;
else if (F_pc_en)
F_pc <= F_pc_nxt;
end
assign F_pcb = {F_pc, 2'b00};
assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
assign F_valid = i_read & ~i_waitrequest;
assign i_read_nxt = W_valid | (i_read & i_waitrequest);
assign i_address = {F_pc, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i_read <= 1'b1;
else
i_read <= i_read_nxt;
end
assign oci_tb_hbreak_req = oci_hbreak_req;
assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid);
assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled
: hbreak_req;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wait_for_one_post_bret_inst <= 1'b0;
else
wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_pending <= 1'b0;
else
hbreak_pending <= hbreak_pending_nxt;
end
assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
assign F_av_iw = i_readdata;
assign F_iw = hbreak_req ? 4040762 :
1'b0 ? 127034 :
intr_req ? 3926074 :
F_av_iw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_iw <= 0;
else if (F_valid)
D_iw <= F_iw;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_valid <= 0;
else
D_valid <= F_valid;
end
assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 :
D_ctrl_implicit_dst_eretaddr ? 5'd29 :
D_ctrl_b_is_dst ? D_iw_b :
D_iw_c;
assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw;
assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_jmp_direct_target_waddr = D_iw[31 : 6];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_valid <= 0;
else
R_valid <= D_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_wr_dst_reg <= 0;
else
R_wr_dst_reg <= D_wr_dst_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_dst_regnum <= 0;
else
R_dst_regnum <= D_dst_regnum;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_logic_op <= 0;
else
R_logic_op <= D_logic_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_compare_op <= 0;
else
R_compare_op <= D_compare_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_src2_use_imm <= 0;
else
R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
end
assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n;
assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
//nios_system_nios2_qsys_0_register_bank_a, which is an nios_sdp_ram
nios_system_nios2_qsys_0_register_bank_a_module nios_system_nios2_qsys_0_register_bank_a
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_a),
.rdaddress (D_iw_a),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam nios_system_nios2_qsys_0_register_bank_a.lpm_file = "nios_system_nios2_qsys_0_rf_ram_a.dat";
`else
defparam nios_system_nios2_qsys_0_register_bank_a.lpm_file = "nios_system_nios2_qsys_0_rf_ram_a.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam nios_system_nios2_qsys_0_register_bank_a.lpm_file = "nios_system_nios2_qsys_0_rf_ram_a.mif";
//synthesis read_comments_as_HDL off
//nios_system_nios2_qsys_0_register_bank_b, which is an nios_sdp_ram
nios_system_nios2_qsys_0_register_bank_b_module nios_system_nios2_qsys_0_register_bank_b
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_b),
.rdaddress (D_iw_b),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam nios_system_nios2_qsys_0_register_bank_b.lpm_file = "nios_system_nios2_qsys_0_rf_ram_b.dat";
`else
defparam nios_system_nios2_qsys_0_register_bank_b.lpm_file = "nios_system_nios2_qsys_0_rf_ram_b.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam nios_system_nios2_qsys_0_register_bank_b.lpm_file = "nios_system_nios2_qsys_0_rf_ram_b.mif";
//synthesis read_comments_as_HDL off
assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} :
R_rf_a;
assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 :
(R_src2_use_imm)? D_iw_imm16 :
R_rf_b[15 : 0];
assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 :
(R_ctrl_hi_imm16)? D_iw_imm16 :
(R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
R_rf_b[31 : 16];
assign R_src2 = {R_src2_hi, R_src2_lo};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_valid <= 0;
else
E_valid <= R_valid | E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_new_inst <= 0;
else
E_new_inst <= R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src1 <= 0;
else
E_src1 <= R_src1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src2 <= 0;
else
E_src2 <= R_src2;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_invert_arith_src_msb <= 0;
else
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_alu_sub <= 0;
else
E_alu_sub <= D_ctrl_alu_subtract & R_valid;
end
assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall;
assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb,
E_src1[30 : 0]};
assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb,
E_src2[30 : 0]};
assign E_arith_result = E_alu_sub ?
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[24 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
(E_src1 ^ E_src2);
assign E_logic_result_is_0 = E_logic_result == 0;
assign E_eq = E_logic_result_is_0;
assign E_lt = E_arith_result[32];
assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
(R_compare_op == 2'b01)? ~E_lt :
(R_compare_op == 2'b10)? E_lt :
~E_eq;
assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1;
assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
(R_ctrl_rot_right ? E_shift_rot_result[0] :
E_shift_rot_result[31]);
assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
(R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
{E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_result <= 0;
else
E_shift_rot_result <= E_shift_rot_result_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_cnt <= 0;
else
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end
assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg :
(D_iw_control_regnum == 3'd1)? W_estatus_reg :
(D_iw_control_regnum == 3'd2)? W_bstatus_reg :
(D_iw_control_regnum == 3'd3)? W_ienable_reg :
(D_iw_control_regnum == 3'd4)? W_ipending_reg :
0;
assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 :
(R_ctrl_shift_rot)? E_shift_rot_result :
(R_ctrl_logic)? E_logic_result :
(R_ctrl_custom)? E_ci_result :
E_arith_result;
assign R_stb_data = R_rf_b[7 : 0];
assign R_sth_data = R_rf_b[15 : 0];
assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
(D_mem16)? {R_sth_data, R_sth_data} :
R_rf_b;
assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 :
4'b1111;
assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest);
assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest);
assign E_st_stall = d_write_nxt;
assign d_address = W_mem_baddr;
assign av_ld_getting_data = d_read & ~d_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_read <= 0;
else
d_read <= d_read_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_writedata <= 0;
else
d_writedata <= E_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_byteenable <= 0;
else
d_byteenable <= E_mem_byte_en;
end
assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3);
assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
~av_ld_align_one_more_cycle :
(~D_mem32 & av_ld_getting_data);
assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
~av_ld_getting_data :
(R_ctrl_ld & E_new_inst);
assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt);
assign av_ld_rshift8 = av_ld_aligning_data &
(av_ld_align_cycle < (W_mem_baddr[1 : 0]));
assign av_ld_extend = av_ld_aligning_data;
assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
av_ld_extend ? av_ld_byte0_data :
d_readdata[7 : 0];
assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[15 : 8];
assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[23 : 16];
assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[31 : 24];
assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8);
assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
av_ld_byte1_data, av_ld_byte0_data};
assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_align_cycle <= 0;
else
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_waiting_for_data <= 0;
else
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_aligning_data <= 0;
else
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte0_data <= 0;
else
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte1_data <= 0;
else if (av_ld_byte1_data_en)
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte2_data <= 0;
else
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte3_data <= 0;
else
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid <= 0;
else
W_valid <= E_valid & ~E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_control_rd_data <= 0;
else
W_control_rd_data <= E_control_rd_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= E_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_alu_result <= 0;
else
W_alu_result <= E_alu_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_status_reg_pie <= 0;
else
W_status_reg_pie <= W_status_reg_pie_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_estatus_reg <= 0;
else
W_estatus_reg <= W_estatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_bstatus_reg <= 0;
else
W_bstatus_reg <= W_bstatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ienable_reg <= 0;
else
W_ienable_reg <= W_ienable_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ipending_reg <= 0;
else
W_ipending_reg <= W_ipending_reg_nxt;
end
assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
R_ctrl_rdctl_inst ? W_control_rd_data :
W_alu_result[31 : 0];
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br & W_cmp_result;
assign W_mem_baddr = W_alu_result[24 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd0);
assign E_wrctl_estatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd1);
assign E_wrctl_bstatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd2);
assign E_wrctl_ienable = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd3);
assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 :
(D_op_eret) ? W_estatus_reg :
(D_op_bret) ? W_bstatus_reg :
(E_wrctl_status) ? E_src1[0] :
W_status_reg_pie;
assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 :
(R_ctrl_exception) ? W_status_reg :
(E_wrctl_estatus) ? E_src1[0] :
W_estatus_reg;
assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg :
(E_wrctl_bstatus) ? E_src1[0] :
W_bstatus_reg;
assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ?
E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000101111;
assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000101111;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_enabled <= 1'b1;
else if (E_valid)
hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled;
end
nios_system_nios2_qsys_0_nios2_oci the_nios_system_nios2_qsys_0_nios2_oci
(
.D_valid (D_valid),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pc (F_pc),
.address_nxt (jtag_debug_module_address),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.byteenable_nxt (jtag_debug_module_byteenable),
.clk (jtag_debug_module_clk),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.debugaccess_nxt (jtag_debug_module_debugaccess),
.hbreak_enabled (hbreak_enabled),
.jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms),
.oci_hbreak_req (oci_hbreak_req),
.oci_ienable (oci_ienable),
.oci_single_step_mode (oci_single_step_mode),
.read_nxt (jtag_debug_module_read),
.readdata (jtag_debug_module_readdata),
.reset (jtag_debug_module_reset),
.reset_n (reset_n),
.resetrequest (jtag_debug_module_resetrequest),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.waitrequest (jtag_debug_module_waitrequest),
.write_nxt (jtag_debug_module_write),
.writedata_nxt (jtag_debug_module_writedata)
);
//jtag_debug_module, which is an e_avalon_slave
assign jtag_debug_module_clk = clk;
assign jtag_debug_module_reset = ~reset_n;
assign D_ctrl_custom = 1'b0;
assign R_ctrl_custom_nxt = D_ctrl_custom;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom <= 0;
else if (R_en)
R_ctrl_custom <= R_ctrl_custom_nxt;
end
assign D_ctrl_custom_multi = 1'b0;
assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom_multi <= 0;
else if (R_en)
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end
assign D_ctrl_jmp_indirect = D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_indirect <= 0;
else if (R_en)
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end
assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_direct <= 0;
else if (R_en)
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end
assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02;
assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_retaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end
assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu;
assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_eretaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end
assign D_ctrl_exception = D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60;
assign R_ctrl_exception_nxt = D_ctrl_exception;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_exception <= 0;
else if (R_en)
R_ctrl_exception <= R_ctrl_exception_nxt;
end
assign D_ctrl_break = D_op_break|D_op_hbreak;
assign R_ctrl_break_nxt = D_ctrl_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_break <= 0;
else if (R_en)
R_ctrl_break <= R_ctrl_break_nxt;
end
assign D_ctrl_crst = D_op_crst|D_op_rsvx63;
assign R_ctrl_crst_nxt = D_ctrl_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_crst <= 0;
else if (R_en)
R_ctrl_crst <= R_ctrl_crst_nxt;
end
assign D_ctrl_uncond_cti_non_br = D_op_call|
D_op_jmpi|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_uncond_cti_non_br <= 0;
else if (R_en)
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end
assign D_ctrl_retaddr = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak;
assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_retaddr <= 0;
else if (R_en)
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end
assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_logical <= 0;
else if (R_en)
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end
assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_right_arith <= 0;
else if (R_en)
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end
assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43;
assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rot_right <= 0;
else if (R_en)
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end
assign D_ctrl_shift_rot_right = D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot_right <= 0;
else if (R_en)
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end
assign D_ctrl_shift_rot = D_op_slli|
D_op_rsvx50|
D_op_sll|
D_op_rsvx51|
D_op_roli|
D_op_rsvx34|
D_op_rol|
D_op_rsvx35|
D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot <= 0;
else if (R_en)
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end
assign D_ctrl_logic = D_op_and|
D_op_or|
D_op_xor|
D_op_nor|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori;
assign R_ctrl_logic_nxt = D_ctrl_logic;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_logic <= 0;
else if (R_en)
R_ctrl_logic <= R_ctrl_logic_nxt;
end
assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_hi_imm16 <= 0;
else if (R_en)
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end
assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
D_op_cmpltui|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_unsigned_lo_imm16 <= 0;
else if (R_en)
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end
assign D_ctrl_br_uncond = D_op_br|D_op_rsv02;
assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_uncond <= 0;
else if (R_en)
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end
assign D_ctrl_br = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62;
assign R_ctrl_br_nxt = D_ctrl_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br <= 0;
else if (R_en)
R_ctrl_br <= R_ctrl_br_nxt;
end
assign D_ctrl_alu_subtract = D_op_sub|
D_op_rsvx25|
D_op_cmplti|
D_op_cmpltui|
D_op_cmplt|
D_op_cmpltu|
D_op_blt|
D_op_bltu|
D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpge|
D_op_cmpgeu|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42;
assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_subtract <= 0;
else if (R_en)
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end
assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_signed_comparison <= 0;
else if (R_en)
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end
assign D_ctrl_br_cmp = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_rsvx00|
D_op_cmpge|
D_op_cmplt|
D_op_cmpne|
D_op_cmpgeu|
D_op_cmpltu|
D_op_cmpeq|
D_op_rsvx56;
assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_cmp <= 0;
else if (R_en)
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end
assign D_ctrl_ld_signed = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63;
assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_signed <= 0;
else if (R_en)
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end
assign D_ctrl_ld = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio;
assign R_ctrl_ld_nxt = D_ctrl_ld;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld <= 0;
else if (R_en)
R_ctrl_ld <= R_ctrl_ld_nxt;
end
assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl;
assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_non_io <= 0;
else if (R_en)
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end
assign D_ctrl_st = D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61;
assign R_ctrl_st_nxt = D_ctrl_st;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st <= 0;
else if (R_en)
R_ctrl_st <= R_ctrl_st_nxt;
end
assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63;
assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_io <= 0;
else if (R_en)
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end
assign D_ctrl_b_is_dst = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda;
assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_b_is_dst <= 0;
else if (R_en)
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end
assign D_ctrl_ignore_dst = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57;
assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ignore_dst <= 0;
else if (R_en)
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end
assign D_ctrl_src2_choose_imm = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src2_choose_imm <= 0;
else if (R_en)
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end
assign D_ctrl_wrctl_inst = D_op_wrctl;
assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_wrctl_inst <= 0;
else if (R_en)
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end
assign D_ctrl_rdctl_inst = D_op_rdctl;
assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rdctl_inst <= 0;
else if (R_en)
R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt;
end
assign D_ctrl_force_src2_zero = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_jmpi;
assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_force_src2_zero <= 0;
else if (R_en)
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end
assign D_ctrl_alu_force_xor = D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmpgeu|
D_op_cmpeq|
D_op_cmpnei|
D_op_cmpne|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42|
D_op_beq|
D_op_rsv34|
D_op_bne|
D_op_rsv62|
D_op_br|
D_op_rsv02;
assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_xor <= 0;
else if (R_en)
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end
//data_master, which is an e_avalon_master
//instruction_master, which is an e_avalon_master
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign F_inst = (F_op_call)? 56'h20202063616c6c :
(F_op_jmpi)? 56'h2020206a6d7069 :
(F_op_ldbu)? 56'h2020206c646275 :
(F_op_addi)? 56'h20202061646469 :
(F_op_stb)? 56'h20202020737462 :
(F_op_br)? 56'h20202020206272 :
(F_op_ldb)? 56'h202020206c6462 :
(F_op_cmpgei)? 56'h20636d70676569 :
(F_op_ldhu)? 56'h2020206c646875 :
(F_op_andi)? 56'h202020616e6469 :
(F_op_sth)? 56'h20202020737468 :
(F_op_bge)? 56'h20202020626765 :
(F_op_ldh)? 56'h202020206c6468 :
(F_op_cmplti)? 56'h20636d706c7469 :
(F_op_initda)? 56'h20696e69746461 :
(F_op_ori)? 56'h202020206f7269 :
(F_op_stw)? 56'h20202020737477 :
(F_op_blt)? 56'h20202020626c74 :
(F_op_ldw)? 56'h202020206c6477 :
(F_op_cmpnei)? 56'h20636d706e6569 :
(F_op_flushda)? 56'h666c7573686461 :
(F_op_xori)? 56'h202020786f7269 :
(F_op_bne)? 56'h20202020626e65 :
(F_op_cmpeqi)? 56'h20636d70657169 :
(F_op_ldbuio)? 56'h206c646275696f :
(F_op_muli)? 56'h2020206d756c69 :
(F_op_stbio)? 56'h2020737462696f :
(F_op_beq)? 56'h20202020626571 :
(F_op_ldbio)? 56'h20206c6462696f :
(F_op_cmpgeui)? 56'h636d7067657569 :
(F_op_ldhuio)? 56'h206c646875696f :
(F_op_andhi)? 56'h2020616e646869 :
(F_op_sthio)? 56'h2020737468696f :
(F_op_bgeu)? 56'h20202062676575 :
(F_op_ldhio)? 56'h20206c6468696f :
(F_op_cmpltui)? 56'h636d706c747569 :
(F_op_initd)? 56'h2020696e697464 :
(F_op_orhi)? 56'h2020206f726869 :
(F_op_stwio)? 56'h2020737477696f :
(F_op_bltu)? 56'h202020626c7475 :
(F_op_ldwio)? 56'h20206c6477696f :
(F_op_flushd)? 56'h20666c75736864 :
(F_op_xorhi)? 56'h2020786f726869 :
(F_op_eret)? 56'h20202065726574 :
(F_op_roli)? 56'h202020726f6c69 :
(F_op_rol)? 56'h20202020726f6c :
(F_op_flushp)? 56'h20666c75736870 :
(F_op_ret)? 56'h20202020726574 :
(F_op_nor)? 56'h202020206e6f72 :
(F_op_mulxuu)? 56'h206d756c787575 :
(F_op_cmpge)? 56'h2020636d706765 :
(F_op_bret)? 56'h20202062726574 :
(F_op_ror)? 56'h20202020726f72 :
(F_op_flushi)? 56'h20666c75736869 :
(F_op_jmp)? 56'h202020206a6d70 :
(F_op_and)? 56'h20202020616e64 :
(F_op_cmplt)? 56'h2020636d706c74 :
(F_op_slli)? 56'h202020736c6c69 :
(F_op_sll)? 56'h20202020736c6c :
(F_op_or)? 56'h20202020206f72 :
(F_op_mulxsu)? 56'h206d756c787375 :
(F_op_cmpne)? 56'h2020636d706e65 :
(F_op_srli)? 56'h20202073726c69 :
(F_op_srl)? 56'h2020202073726c :
(F_op_nextpc)? 56'h206e6578747063 :
(F_op_callr)? 56'h202063616c6c72 :
(F_op_xor)? 56'h20202020786f72 :
(F_op_mulxss)? 56'h206d756c787373 :
(F_op_cmpeq)? 56'h2020636d706571 :
(F_op_divu)? 56'h20202064697675 :
(F_op_div)? 56'h20202020646976 :
(F_op_rdctl)? 56'h2020726463746c :
(F_op_mul)? 56'h202020206d756c :
(F_op_cmpgeu)? 56'h20636d70676575 :
(F_op_initi)? 56'h2020696e697469 :
(F_op_trap)? 56'h20202074726170 :
(F_op_wrctl)? 56'h2020777263746c :
(F_op_cmpltu)? 56'h20636d706c7475 :
(F_op_add)? 56'h20202020616464 :
(F_op_break)? 56'h2020627265616b :
(F_op_hbreak)? 56'h2068627265616b :
(F_op_sync)? 56'h20202073796e63 :
(F_op_sub)? 56'h20202020737562 :
(F_op_srai)? 56'h20202073726169 :
(F_op_sra)? 56'h20202020737261 :
(F_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign D_inst = (D_op_call)? 56'h20202063616c6c :
(D_op_jmpi)? 56'h2020206a6d7069 :
(D_op_ldbu)? 56'h2020206c646275 :
(D_op_addi)? 56'h20202061646469 :
(D_op_stb)? 56'h20202020737462 :
(D_op_br)? 56'h20202020206272 :
(D_op_ldb)? 56'h202020206c6462 :
(D_op_cmpgei)? 56'h20636d70676569 :
(D_op_ldhu)? 56'h2020206c646875 :
(D_op_andi)? 56'h202020616e6469 :
(D_op_sth)? 56'h20202020737468 :
(D_op_bge)? 56'h20202020626765 :
(D_op_ldh)? 56'h202020206c6468 :
(D_op_cmplti)? 56'h20636d706c7469 :
(D_op_initda)? 56'h20696e69746461 :
(D_op_ori)? 56'h202020206f7269 :
(D_op_stw)? 56'h20202020737477 :
(D_op_blt)? 56'h20202020626c74 :
(D_op_ldw)? 56'h202020206c6477 :
(D_op_cmpnei)? 56'h20636d706e6569 :
(D_op_flushda)? 56'h666c7573686461 :
(D_op_xori)? 56'h202020786f7269 :
(D_op_bne)? 56'h20202020626e65 :
(D_op_cmpeqi)? 56'h20636d70657169 :
(D_op_ldbuio)? 56'h206c646275696f :
(D_op_muli)? 56'h2020206d756c69 :
(D_op_stbio)? 56'h2020737462696f :
(D_op_beq)? 56'h20202020626571 :
(D_op_ldbio)? 56'h20206c6462696f :
(D_op_cmpgeui)? 56'h636d7067657569 :
(D_op_ldhuio)? 56'h206c646875696f :
(D_op_andhi)? 56'h2020616e646869 :
(D_op_sthio)? 56'h2020737468696f :
(D_op_bgeu)? 56'h20202062676575 :
(D_op_ldhio)? 56'h20206c6468696f :
(D_op_cmpltui)? 56'h636d706c747569 :
(D_op_initd)? 56'h2020696e697464 :
(D_op_orhi)? 56'h2020206f726869 :
(D_op_stwio)? 56'h2020737477696f :
(D_op_bltu)? 56'h202020626c7475 :
(D_op_ldwio)? 56'h20206c6477696f :
(D_op_flushd)? 56'h20666c75736864 :
(D_op_xorhi)? 56'h2020786f726869 :
(D_op_eret)? 56'h20202065726574 :
(D_op_roli)? 56'h202020726f6c69 :
(D_op_rol)? 56'h20202020726f6c :
(D_op_flushp)? 56'h20666c75736870 :
(D_op_ret)? 56'h20202020726574 :
(D_op_nor)? 56'h202020206e6f72 :
(D_op_mulxuu)? 56'h206d756c787575 :
(D_op_cmpge)? 56'h2020636d706765 :
(D_op_bret)? 56'h20202062726574 :
(D_op_ror)? 56'h20202020726f72 :
(D_op_flushi)? 56'h20666c75736869 :
(D_op_jmp)? 56'h202020206a6d70 :
(D_op_and)? 56'h20202020616e64 :
(D_op_cmplt)? 56'h2020636d706c74 :
(D_op_slli)? 56'h202020736c6c69 :
(D_op_sll)? 56'h20202020736c6c :
(D_op_or)? 56'h20202020206f72 :
(D_op_mulxsu)? 56'h206d756c787375 :
(D_op_cmpne)? 56'h2020636d706e65 :
(D_op_srli)? 56'h20202073726c69 :
(D_op_srl)? 56'h2020202073726c :
(D_op_nextpc)? 56'h206e6578747063 :
(D_op_callr)? 56'h202063616c6c72 :
(D_op_xor)? 56'h20202020786f72 :
(D_op_mulxss)? 56'h206d756c787373 :
(D_op_cmpeq)? 56'h2020636d706571 :
(D_op_divu)? 56'h20202064697675 :
(D_op_div)? 56'h20202020646976 :
(D_op_rdctl)? 56'h2020726463746c :
(D_op_mul)? 56'h202020206d756c :
(D_op_cmpgeu)? 56'h20636d70676575 :
(D_op_initi)? 56'h2020696e697469 :
(D_op_trap)? 56'h20202074726170 :
(D_op_wrctl)? 56'h2020777263746c :
(D_op_cmpltu)? 56'h20636d706c7475 :
(D_op_add)? 56'h20202020616464 :
(D_op_break)? 56'h2020627265616b :
(D_op_hbreak)? 56'h2068627265616b :
(D_op_sync)? 56'h20202073796e63 :
(D_op_sub)? 56'h20202020737562 :
(D_op_srai)? 56'h20202073726169 :
(D_op_sra)? 56'h20202020737261 :
(D_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign F_vinst = F_valid ? F_inst : {7{8'h2d}};
assign D_vinst = D_valid ? D_inst : {7{8'h2d}};
assign R_vinst = R_valid ? D_inst : {7{8'h2d}};
assign E_vinst = E_valid ? D_inst : {7{8'h2d}};
assign W_vinst = W_valid ? D_inst : {7{8'h2d}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
// Date : Sat Oct 31 15:04:15 2015
// Host : cascade.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.1 (Maipo)
// Command : write_verilog -force -mode synth_stub
// /afs/ece.cmu.edu/usr/rmrobert/Private/18545/Atari7800/Atari7800/Atari7800.srcs/sources_1/ip/BIOS_ROM/BIOS_ROM_stub.v
// Design : BIOS_ROM
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2015.2" *)
module BIOS_ROM(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[11:0],dina[7:0],douta[7:0]" */;
input clka;
input ena;
input [0:0]wea;
input [11:0]addra;
input [7:0]dina;
output [7:0]douta;
endmodule
|
/*!
* <b>Module:</b>ahci_top
* @file ahci_top.v
* @date 2016-01-09
* @author Andrey Filippov
*
* @brief Top module of the AHCI implementation
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_top.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ahci_top.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*/
`timescale 1ns/1ps
module ahci_top#(
parameter PREFETCH_ALWAYS = 0,
parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen
// parameter READ_CT_LATENCY = 1, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen
parameter READ_CT_LATENCY = 2, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen
parameter ADDRESS_BITS = 10, // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle)
parameter HBA_RESET_BITS = 9, // duration of HBA reset in aclk periods (9: ~10usec)
parameter RESET_TO_FIRST_ACCESS = 1, // keep port reset until first R/W any register by software
parameter FREQ_METER_WIDTH = 12
)(
input aclk, // clock - should be buffered
input arst, // @aclk sync reset, active high
input mclk, // SATA system clock (current 75MHz for SATA2)
input mrst, // reset in mclk clock domain (after SATA PLL is on)
// async reset for SATA (mrst will be response to it)
output hba_arst, // hba async reset (currently does ~ the same as port reset)
output port_arst, // port0 async set by software (does not include arst)
output port_arst_any, // port0 async set by software and by arst
input hclk, // AXI HP interface clock for 64-bit DMA (current - 150MHz
input hrst, // reset in hclk clock domain
// MAXIGP1
// AXI Write Address
input [31:0] awaddr, // AWADDR[31:0], input
input awvalid, // AWVALID, input
output awready, // AWREADY, output
input [11:0] awid, // AWID[11:0], input
input [ 3:0] awlen, // AWLEN[3:0], input
input [ 1:0] awsize, // AWSIZE[1:0], input
input [ 1:0] awburst, // AWBURST[1:0], input
// AXI PS Master GP0: Write Data
input [31:0] wdata, // WDATA[31:0], input
input wvalid, // WVALID, input
output wready, // WREADY, output
input [11:0] wid, // WID[11:0], input
input wlast, // WLAST, input
input [ 3:0] wstb, // WSTRB[3:0], input
// AXI PS Master GP0: Write response
output bvalid, // BVALID, output
input bready, // BREADY, input
output [11:0] bid, // BID[11:0], output
output [ 1:0] bresp, // BRESP[1:0], output
// AXI Read Address
input [31:0] araddr, // ARADDR[31:0], input
input arvalid, // ARVALID, input
output arready, // ARREADY, output
input [11:0] arid, // ARID[11:0], input
input [ 3:0] arlen, // ARLEN[3:0], input
input [ 1:0] arsize, // ARSIZE[1:0], input
input [ 1:0] arburst, // ARBURST[1:0], input
// AXI Read Data
output [31:0] rdata, // RDATA[31:0], output
output rvalid, // RVALID, output
input rready, // RREADY, input
output [11:0] rid, // RID[11:0], output
output rlast, // RLAST, output
output [ 1:0] rresp, // RRESP
// SAXIHP3
// axi_hp signals write channel
// write address
output [31:0] afi_awaddr,
output afi_awvalid,
input afi_awready, // @SuppressThisWarning VEditor unused - used FIF0 level
output [ 5:0] afi_awid,
output [ 1:0] afi_awlock,
output [ 3:0] afi_awcache,
output [ 2:0] afi_awprot,
output [ 3:0] afi_awlen,
output [ 1:0] afi_awsize,
output [ 1:0] afi_awburst,
output [ 3:0] afi_awqos,
// write data
output [63:0] afi_wdata,
output afi_wvalid,
input afi_wready, // @ SuppressThisWarning VEditor unused - used FIF0 level
output [ 5:0] afi_wid,
output afi_wlast,
output [ 7:0] afi_wstrb,
// write response
input afi_bvalid, // @SuppressThisWarning VEditor unused
output afi_bready,
input [ 5:0] afi_bid, // @SuppressThisWarning VEditor unused
input [ 1:0] afi_bresp, // @SuppressThisWarning VEditor unused
// PL extra (non-AXI) signals
input [ 7:0] afi_wcount,
input [ 5:0] afi_wacount,
output afi_wrissuecap1en,
// AXI_HP signals - read channel
// read address
output [31:0] afi_araddr,
output afi_arvalid,
input afi_arready, // @SuppressThisWarning VEditor unused - used FIF0 level
output [ 5:0] afi_arid,
output [ 1:0] afi_arlock,
output [ 3:0] afi_arcache,
output [ 2:0] afi_arprot,
output [ 3:0] afi_arlen,
output [ 1:0] afi_arsize,
output [ 1:0] afi_arburst,
output [ 3:0] afi_arqos,
// read data
input [63:0] afi_rdata,
input afi_rvalid,
output afi_rready,
input [ 5:0] afi_rid, // @SuppressThisWarning VEditor unused
input afi_rlast, // @SuppressThisWarning VEditor unused
input [ 1:0] afi_rresp, // @SuppressThisWarning VEditor unused
// PL extra (non-AXI) signals
input [ 7:0] afi_rcount,
input [ 2:0] afi_racount,
output afi_rdissuecap1en,
// Data/type FIFO, host -> device
// Data System memory or FIS -> device
output [31:0] h2d_data, // 32-bit data from the system memory to HBA (dma data)
output [ 1:0] h2d_type, // 0 - data, 1 - FIS head, 2 - FIS END (make FIS_Last?)
output h2d_valid, // output register full
input h2d_ready, // send FIFO has room for data (>= 8? dwords)
// Data/type FIFO, device -> host
input [31:0] d2h_data, // FIFO output data
input [ 1:0] d2h_type, // 0 - data, 1 - FIS head, 2 - R_OK, 3 - R_ERR
input d2h_valid, // Data available from the transport layer in FIFO
input d2h_many, // Multiple DWORDs available from the transport layer in FIFO
output d2h_ready, // This module or DMA consumes DWORD
// communication with transport/link/phys layers
// input phy_rst, // frome phy, as a response to hba_arst || port_arst. It is deasserted when clock is stable
input [ 1:0] phy_ready, // 0 - not ready, 1..3 - negotiated speed
input xmit_ok, // FIS transmission acknowledged OK
input xmit_err, // Error during sending of a FIS
input syncesc_recv, // These two inputs interrupt transmit
output pcmd_st_cleared, // bit was cleared by software
output syncesc_send, // Send sync escape
input syncesc_send_done, // "SYNC escape until the interface is quiescent..."
output comreset_send, // Not possible yet?
input cominit_got,
output set_offline, // electrically idle
input x_rdy_collision, // X_RDY/X_RDY collision on interface
output send_R_OK, // Should it be originated in this layer SM?
output send_R_ERR,
// additional errors from SATA layers (single-clock pulses):
input serr_DT, // RWC: Transport state transition error
input serr_DS, // RWC: Link sequence error
input serr_DH, // RWC: Handshake Error (i.e. Device got CRC error)
input serr_DC, // RWC: CRC error in Link layer
input serr_DB, // RWC: 10B to 8B decode error
input serr_DW, // RWC: COMMWAKE signal was detected
input serr_DI, // RWC: PHY Internal Error
// sirq_PRC,
// sirq_IF || // sirq_INF
input serr_EE, // RWC: Internal error (such as elastic buffer overflow or primitive mis-alignment)
input serr_EP, // RWC: Protocol Error - a violation of SATA protocol detected
input serr_EC, // RWC: Persistent Communication or Data Integrity Error
input serr_ET, // RWC: Transient Data Integrity Error (error not recovered by the interface)
input serr_EM, // RWC: Communication between the device and host was lost but re-established
input serr_EI, // RWC: Recovered Data integrity Error
// additional control signals for SATA layers
output [3:0] sctl_ipm, // Interface power management transitions allowed
output [3:0] sctl_spd, // Interface maximal speed
output irq, // CPU interrupt request
input debug_link_send_data, // @posedge sata_clk - last symbol was data output (to count sent out)
input debug_link_dmatp, // link received DMATp from device
`ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read)
input datascope1_clk,
input [ADDRESS_BITS-1:0] datascope1_waddr,
input datascope1_we,
input [31:0] datascope1_di,
`endif
`ifdef USE_DRP
output drp_en, // @aclk strobes drp_ad
output drp_we,
output [14:0] drp_addr,
output [15:0] drp_di,
input drp_rdy,
input [15:0] drp_do,
`endif
input [FREQ_METER_WIDTH - 1:0] xclk_period, // relative (to 2*clk) xclk period
input [31:0] debug_in_phy,
input [31:0] debug_in_link
);
`ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read)
wire datascope_clk;
wire [ADDRESS_BITS-1:0] datascope_waddr;
wire datascope_we;
wire [31:0] datascope_di;
`endif
// axi_ahci_regs signals:
// 1. Notification of data written @ hba_clk
wire [ADDRESS_BITS-1:0] soft_write_addr; // register address written by software
wire [31:0] soft_write_data; // register data written (after applying wstb and type (RO, RW, RWC, RW1)
wire soft_write_en; // write enable for data write
// wire hba_arst; // hba async reset (currently does ~ the same as port reset)
// wire port_arst; // port0 async reset by software
// 2. HBA R/W registers, use hba clock
// wire hba_rst;
wire regs_we_acs;
// wire [1:0] regs_re_fsm;
wire [31:0] regs_din_from_acs; // from fsm
wire regs_we_freceive;
wire [1:0] regs_re_ftransmit; // [0] - re, [1] - regen
wire [ADDRESS_BITS-1:0] regs_saddr; // read/write adderss from ahci_fsm
wire [ADDRESS_BITS-1:0] regs_waddr;
wire [ADDRESS_BITS-1:0] regs_raddr;
wire [31:0] regs_din_from_freceive;
wire [31:0] regs_dout;
reg en_port;
wire [1:0] regs_re = en_port ? regs_re_ftransmit : 2'b0; // [0] - re, [1] - regen
wire regs_we = en_port ? ( regs_we_freceive | regs_we_acs) : 1'b0;
wire [ADDRESS_BITS-1:0] regs_addr = ({ADDRESS_BITS{regs_we_freceive}} & regs_waddr) |
({ADDRESS_BITS{regs_re_ftransmit[0]}} & regs_raddr) |
({ADDRESS_BITS{regs_we_acs}} & regs_saddr);
/*
wire [ADDRESS_BITS-1:0] regs_addr = ({ADDRESS_BITS{en_port & regs_we_freceive}} & regs_waddr) |
({ADDRESS_BITS{en_port & regs_re_ftransmit[0]}} & regs_raddr) |
({ADDRESS_BITS{en_port & regs_we_acs}} & regs_saddr);
*/
wire [31:0] regs_din = ({32{regs_we_freceive}} & regs_din_from_freceive) |
({32{regs_we_acs}} & regs_din_from_acs);
// wire [1:0] regs_re = regs_re_ftransmit | regs_re_fsm; // [0] - re, [1] - regen
//---------------------
// wire [31:7] ctba; // input[31:7]
wire ctba_ld; // input
wire [15:0] prdtl; // input[15:0]
wire dev_wr; // input
wire dma_cmd_start; // input
wire dma_prd_start; // input
wire dma_cmd_abort_xmit; // input
wire dma_cmd_abort_fsm; // abort from FSM (also from ahci_fis_transmit)
// Use some of the custom registers in the address space?
wire [17:0] fsm_pgm_ad; // @aclk, address/data to program the AHCI FSM
wire fsm_pgm_wa; // @aclk, address strobe to program the AHCI FSM
wire fsm_pgm_wd; // @aclk, data strobe to program the AHCI FSM
wire [ 3:0] axi_wr_cache_mode; // input[3:0]
wire [ 3:0] axi_rd_cache_mode; // input[3:0]
wire set_axi_cache_mode; // input (both axi_wr_cache_mode and axi_rd_cache_mode)
wire dma_ct_busy; // output reg
wire [ 4:0] dma_ct_addr; // input[4:0]
wire [ 1:0] dma_ct_re; // input
wire [31:0] dma_ct_data; // output[31:0] reg
/// wire dma_prd_done; // output (finished next prd)
wire dma_prd_irq_clear; // reset pending prd_irq
wire dma_prd_irq_pend; // prd interrupt pending. This is just a condition for irq - actual will be generated after FIS OK
wire dma_cmd_busy; // output reg (DMA engine is processing PRDs)
wire dma_cmd_done; // output (last PRD is over)
wire dma_abort_busy;
wire dma_abort_done;
wire axi_mismatch;
wire [31:0] dma_dout; // output[31:0]
wire dma_dav; // output
wire dma_re; // input
wire last_h2d_data;// when active and no new data for 2 clocks - that was the last one
wire dma_in_ready; // output
wire dma_we; // input
wire dma_extra_din; // all DRDs are transferred to memory, but FIFO has some data. Valid when transfer is stopped
// ---------------------------------------
// fsm <-> ahc_fis_receive
// fsm ->
wire frcv_first_vld;
// To debug/recover -
wire frcv_first_invalid; // Some data available from FIFO, but not FIS head
wire frcv_first_flush; // Skip FIFO data until empty or FIS head
wire frcv_get_dsfis;
wire frcv_get_psfis;
wire frcv_get_rfis;
wire frcv_get_sdbfis;
wire frcv_get_ufis;
wire frcv_get_data_fis;
wire frcv_get_ignore; // ignore whatever FIS (use for DMA activate too?)
// short commands:
// next commands use register address/data/we for 1 clock cycle - after next to command (commnd - t0, we - t2)
wire frcv_update_err_sts;// update PxTFD.STS and PxTFD.ERR from the last received regs d2h
wire frcv_update_pio; // update PxTFD.STS and PxTFD.ERR from pio_* (entry PIO:Update)
wire frcv_update_prdbc; // update PRDBC in registers
wire frcv_clear_bsy_drq; // clear PxTFD.STS.BSY and PxTFD.STS.DRQ, update
wire frcv_clear_bsy_set_drq; // clear PxTFD.STS.BSY and sets PxTFD.STS.DRQ, update
wire frcv_set_bsy; // set PxTFD.STS.BSY, update
wire frcv_set_sts_7f; // set PxTFD.STS = 0x7f, update
wire frcv_set_sts_80; // set PxTFD.STS = 0x80 (may be combined with set_sts_7f), update
wire frcv_decr_dwcr; // decrement DMA Xfer counter after read // need pulse to 'update_prdbc' to write to registers
wire frcv_decr_dwcw; // decrement DMA Xfer counter after write // need pulse to 'update_prdbc' to write to registers
wire frcv_clear_xfer_cntr; // Clear pXferCntr to 0
// fsm <-
wire frcv_busy; // busy processing FIS
wire frcv_done; // done processing FIS (see fis_ok, fis_err, fis_ferr)
wire frcv_ok; // FIS done, checksum OK reset by starting a new get FIS
wire frcv_err; // FIS done, checksum ERROR reset by starting a new get FIS
wire frcv_ferr; // FIS done, fatal error - FIS too long
wire frcv_extra; // DMA all transferred, but some data is still in left. . Does not deny frcv_ok
wire frcv_set_update_sig; // when set, enables get_sig (and resets itself)
/// wire frcv_pUpdateSig; // state variable
/// wire frcv_sig_available; // signature data available
wire frcv_update_sig; // update signature
// fsm <- state variables that are maintained inside 'ahc_fis_receive'
wire [7:0] tfd_sts; // Current PxTFD status field (updated after regFIS and SDB - certain fields)
// tfd_sts[7] - BSY, tfd_sts[3] - DRQ, tfd_sts[0] - ERR
// wire [7:0] tfd_err; // Current PxTFD error field (updated after regFIS and SDB)
wire fis_i; // value of "I" field in received regsD2H or SDB FIS
/// wire sdb_n; // value of "N" field in received SDB FIS
wire dma_a; // value of "A" field in received DMA Setup FIS
/// wire dma_d; // value of "D" field in received DMA Setup FIS
wire pio_i; // value of "I" field in received PIO Setup FIS
wire pio_d; // value of "D" field in received PIO Setup FIS
/// wire [7:0] pio_es; // value of PIO E_Status
wire pPioXfer;
/// wire sactive0; // bit 0 of sActive DWORD received in SDB FIS
// Using even word count (will be rounded up), partial DWORD (last) will be handled by PRD length if needed
wire [31:2] xfer_cntr;
wire xfer_cntr_zero;
/// wire [11:0] data_in_dwords; // number of DWORDs received in data FIS (can be updated internally). Is it needed?
// fsm <-> ahc_fis_transmit
// Command pulses to execute states fsm -> ahc_fis_transmit
wire fsnd_fetch_cmd; // Enter p:FetchCmd, fetch command header (from the register memory, prefetch command FIS)
// wait for either fetch_cmd_busy == 0 or pCmdToIssue ==1 after fetch_cmd
wire fsnd_cfis_xmit; // transmit command (wait for dma_ct_busy == 0)
wire fsnd_dx_xmit; // send FIS header DWORD, (just 0x46), then forward DMA data
// transmit until error, 2048DWords or pDmaXferCnt
wire fsnd_atapi_xmit; // tarsmit ATAPI command FIS
// responses fsm <- ahc_fis_transmit
wire fsnd_done;
/// wire fsnd_busy;
// Short action pulses fsm -> ahc_fis_transmit
wire fsnd_clearCmdToIssue; // From CFIS:SUCCESS
// State variables fsm <- ahc_fis_transmit
wire fsnd_pCmdToIssue; // AHCI port variable
wire [ 2:0] fsnd_dx_err; // bit 0 - syncesc_recv, 1 - R_ERR (was xmit_err) 2 - X-RDY/X_RDY collision (valid @ xmit_err and later, reset by new command)
wire fsnd_ch_c; // Clear busy upon R_OK for this FIS
wire fsnd_ch_b; // Built-in self test command
wire fsnd_ch_r; // reset - may need to send SYNC escape before this command
wire fsnd_ch_p; // prefetchable - only used with non-zero PRDTL or ATAPI bit set
wire fsnd_ch_w; // Write: system memory -> device
wire fsnd_ch_a; // ATAPI: 1 means device should send PIO setup FIS for ATAPI command
/// wire [4:0] fsnd_ch_cfl; // length of the command FIS in DW, 0 means none. 0 and 1 - illegal, ... Maybe not needed outside ahc_fis_transmit
wire [11:0] data_out_dwords; // number of DWORDs sent in data FIS
wire was_hba_rst;
wire was_port_rst;
// signals between ahci_fsm and ahci_ctrl_stat
/// wire update_regs_pending;
wire update_all_regs;
wire update_regs_busy; // valid same cycle as update_all_regs
/// wire st01_pending; // software turned PxCMD.ST from 0 to 1
/// wire st10_pending; // software turned PxCMD.ST from 1 to 0
/// wire st_pending_reset;// reset both st01_pending and st10_pending
// these following individual signals may be unneded - use update_all_regs -> update_regs_busy
// wire update_GHC__IS;
// wire update_HBA_PORT__PxIS;
// wire update_HBA_PORT__PxSSTS;
// wire update_HBA_PORT__PxSERR;
// wire update_HBA_PORT__PxCMD;
// wire update_HBA_PORT__PxCI;
// PxCMD
// wire pcmd_clear_icc; // clear PxCMD.ICC field
wire pcmd_esp = 1'b0; // external SATA port (just forward value)
/// wire pcmd_cr; // command list run - current - read only by software (set by HBA)
wire pcmd_cr_set; // command list run set
wire pcmd_cr_reset; // command list run reset
// wire pcmd_fr; // ahci_fis_receive:get_fis_busy - use frcv_busy
wire pcmd_fre0; // FIS enable copy to memory
wire pcmd_fre = pcmd_fre0 || 1; // FIS enable copy to memory
// wire pcmd_clear_bsy_drq; // == ahci_fis_receive:clear_bsy_drq
wire pcmd_clo; // RW1, causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit
// wire pcmd_clear_st; // RW clear ST (start) bit
wire pcmd_st; // current value
wire pfsm_started; // H: FSM done, P: FSM started (enable sensing pcmd_st_cleared)
//clear_bsy_drq
// Interrupt inputs
wire sirq_TFE; // RWC: Task File Error Status
wire sirq_IF; // RWC: Interface Fatal Error Status (sect. 6.1.2)
wire sirq_INF; // RWC: Interface Non-Fatal Error Status (sect. 6.1.2)
wire sirq_OF; // RWC: Overflow Status
wire sirq_PRC; // RO: PhyRdy changed Status
wire sirq_PC; // RO: Port Connect Change Status
wire sirq_DP; // RWC: Descriptor Processed with "I" bit on
wire sirq_UF; // RO: Unknown FIS
wire sirq_SDB; // RWC: Set Device Bits Interrupt - Set Device bits FIS with 'I' bit set
wire sirq_DS; // RWC: DMA Setup FIS Interrupt - DMA Setup FIS received with 'I' bit set
wire sirq_PS; // RWC: PIO Setup FIS Interrupt - PIO Setup FIS received with 'I' bit set
wire sirq_DHR; // RWC: D2H Register FIS Interrupt - D2H Register FIS received with 'I' bit set
// SCR1:SError (only inputs that are not available in sirq_* ones
//sirq_PC;
//sirq_UF
wire serr_diag_X; // value of PxSERR.DIAG.X
// SCR0: SStatus
wire ssts_ipm_dnp; // device not present or communication not established
wire ssts_ipm_active; // device in active state
wire ssts_ipm_part; // device in partial state
wire ssts_ipm_slumb; // device in slumber state
wire ssts_ipm_devsleep; // device in DevSleep state
wire ssts_spd_dnp; // device not present or communication not established
wire ssts_spd_gen1; // Gen 1 rate negotiated
wire ssts_spd_gen2; // Gen 2 rate negotiated
wire ssts_spd_gen3; // Gen 3 rate negotiated
wire ssts_det_ndnp; // no device detected, phy communication not established
wire ssts_det_dnp; // device detected, but phy communication not established
wire ssts_det_dp; // device detected, phy communication established
wire ssts_det_offline; // device detected, phy communication established
wire [3:0] ssts_det; // current value of PxSSTS.DET
// SCR2:SControl (written by software only)
wire [3:0] sctl_det; // Device detection initialization requested
wire sctl_det_changed; // Software had written new value to sctl_det
wire sctl_det_reset; // clear sctl_det_changed
wire pxci0_clear; // PxCI clear
wire pxci0; // pxCI current value
wire hba_rst_done; // HBA reset done - clear GHC.HR (and some other regs)
wire comreset_send0; // just disabling it
wire [9:0] last_jump_addr;
wire [31:0] debug_dma;
wire [31:0] debug_dma1;
wire [31:0] debug_dma_h2d;
wire unsolicited_en; // enable processing of cominit_got and PxERR.DIAG.W interrupts from
// this bit is reset at reset, set when PxSSTS.DET==3 or PxSCTL.DET==4
assign comreset_send = comreset_send0 && 0;
// Async FF
always @ (posedge mrst or posedge mclk) begin
if (mrst) en_port <= 0;
else en_port <= 1;
end
/*
reg [1:0] port_en; //disable port signals until initialized from the hardware (currently - PLL)
wire ports_rst = ~port_en[1];
always @ (posedge mclk) begin
if (port_arst_any) port_en[0] <= 0;
else if (mrst) port_en[0] <= 1;
if (port_arst_any) port_en[1] <= 0;
else if (!mrst && port_en[0]) port_en[1] <= 1;
end
*/
ahci_fsm// #(
// .READ_REG_LATENCY(2),
// .ADDRESS_BITS(10)
// )
ahci_fsm_i (
.hba_rst (mrst), // input
.mclk (mclk), // input
.was_hba_rst (was_hba_rst), // input
.was_port_rst (was_port_rst), // input
.aclk (aclk), // input
.arst (arst), // input
.pgm_ad (fsm_pgm_ad), // input[17:0]
.pgm_wa (fsm_pgm_wa), // input
.pgm_wd (fsm_pgm_wd), // input
.phy_ready (phy_ready), // input
.syncesc_send (syncesc_send), // output
.comreset_send (comreset_send0), // output
.syncesc_send_done (syncesc_send_done), // input
.cominit_got (cominit_got), // input
.set_offline (set_offline), // output
// .x_rdy_collision (x_rdy_collision), // input
.send_R_OK (send_R_OK), // output
.send_R_ERR (send_R_ERR), // output
/// .update_pending (update_regs_pending),// input
.update_all (update_all_regs), // output
.update_busy (update_regs_busy), // input
/// .update_gis (update_GHC__IS), // output
/// .update_pis (update_HBA_PORT__PxIS), // output
/// .update_ssts (update_HBA_PORT__PxSSTS), // output
/// .update_serr (update_HBA_PORT__PxSERR), // output
/// .update_pcmd (update_HBA_PORT__PxCMD), // output
/// .update_pci (update_HBA_PORT__PxCI), // output
/// .st01_pending (st01_pending), // input
/// .st10_pending (st10_pending), // input
/// .st_pending_reset (st_pending_reset), // output
// .pcmd_clear_icc (pcmd_clear_icc), // output
// .pcmd_esp (pcmd_esp), // output
// .pcmd_cr (pcmd_cr), // input
.pcmd_cr_set (pcmd_cr_set), // output
.pcmd_cr_reset (pcmd_cr_reset), // output
// .pcmd_fr (pcmd_fr), // output
// .pcmd_clear_bsy_drq (pcmd_clear_bsy_drq),// output
.pcmd_clo (pcmd_clo), // input
// .pcmd_clear_st (pcmd_clear_st), // output
.pcmd_st (pcmd_st), // input
.pfsm_started (pfsm_started), // output
.pcmd_st_cleared (pcmd_st_cleared), // input
.sirq_TFE (sirq_TFE), // output
.sirq_IF (sirq_IF), // output
.sirq_INF (sirq_INF), // output
.sirq_OF (sirq_OF), // output
.sirq_PRC (sirq_PRC), // output
.sirq_PC (sirq_PC), // output
.sirq_DP (sirq_DP), // output
.sirq_UF (sirq_UF), // output
.sirq_SDB (sirq_SDB), // output
.sirq_DS (sirq_DS), // output
.sirq_PS (sirq_PS), // output
.sirq_DHR (sirq_DHR), // output
.serr_diag_X (serr_diag_X), // input
.ssts_ipm_dnp (ssts_ipm_dnp), // output
.ssts_ipm_active (ssts_ipm_active), // output
.ssts_ipm_part (ssts_ipm_part), // output
.ssts_ipm_slumb (ssts_ipm_slumb), // output
.ssts_ipm_devsleep (ssts_ipm_devsleep), // output
.ssts_spd_dnp (ssts_spd_dnp), // output
.ssts_spd_gen1 (ssts_spd_gen1), // output
.ssts_spd_gen2 (ssts_spd_gen2), // output
.ssts_spd_gen3 (ssts_spd_gen3), // output
.ssts_det_ndnp (ssts_det_ndnp), // output
.ssts_det_dnp (ssts_det_dnp), // output
.ssts_det_dp (ssts_det_dp), // output
.ssts_det_offline (ssts_det_offline), // output
.ssts_det (ssts_det), // input[3:0]
/// .sctl_ipm (sctl_ipm), // input[3:0]
/// .sctl_spd (sctl_spd), // input[3:0]
.sctl_det (sctl_det), // input[3:0]
.sctl_det_changed (sctl_det_changed), // input
.sctl_det_reset (sctl_det_reset), // output
.hba_rst_done (hba_rst_done), // output
.pxci0_clear (pxci0_clear), // output
.pxci0 (pxci0), // input
/// .dma_prd_done (dma_prd_done), // input
.dma_prd_irq_clear (dma_prd_irq_clear), // output
.dma_prd_irq_pend (dma_prd_irq_pend), // input
.dma_cmd_busy (dma_cmd_busy), // input
/// .dma_cmd_done (dma_cmd_done), // input
.dma_cmd_abort (dma_cmd_abort_fsm), // output
.dma_abort_done (dma_abort_done), // input
.fis_first_invalid (frcv_first_invalid),// input
.fis_first_flush (frcv_first_flush), // output
.fis_first_vld (frcv_first_vld), // input
.fis_type (d2h_data[7:0]), // input[7:0] FIS type (low byte in the first FIS DWORD), valid with 'fis_first_vld'
.bist_bits (d2h_data[23:16]), // bits that define built-in self test
.get_dsfis (frcv_get_dsfis), // output
.get_psfis (frcv_get_psfis), // output
.get_rfis (frcv_get_rfis), // output
.get_sdbfis (frcv_get_sdbfis), // output
.get_ufis (frcv_get_ufis), // output
.get_data_fis (frcv_get_data_fis), // output
.get_ignore (frcv_get_ignore), // output
/// .get_fis_busy (frcv_busy), // input
.get_fis_done (frcv_done), // input
.fis_ok (frcv_ok), // input
.fis_err (frcv_err), // input
.fis_ferr (frcv_ferr), // input
.fis_extra (frcv_extra || dma_extra_din), // input // more data got from FIS than DMA can accept. Does not deny fis_ok. May have latency
.set_update_sig (frcv_set_update_sig),// output
/// .pUpdateSig (frcv_pUpdateSig), // input
/// .sig_available (frcv_sig_available), // input
.update_sig (frcv_update_sig), // output
.update_err_sts (frcv_update_err_sts),// output
.update_pio (frcv_update_pio), // output
.update_prdbc (frcv_update_prdbc), // output
.clear_bsy_drq (frcv_clear_bsy_drq), // output
.clear_bsy_set_drq (frcv_clear_bsy_set_drq), //output
.set_bsy (frcv_set_bsy), // output
.set_sts_7f (frcv_set_sts_7f), // output
.set_sts_80 (frcv_set_sts_80), // output
.clear_xfer_cntr (frcv_clear_xfer_cntr), //output Clear pXferCntr
.decr_dwcr (frcv_decr_dwcr), // output increment pXferCntr after transmit by data transmitted)
.decr_dwcw (frcv_decr_dwcw), // output increment pXferCntr after transmit by data transmitted)
// .decr_DXC_dw (data_out_dwords), // output[11:2] **** Probably not needed
.pxcmd_fre ( pcmd_fre), // input
.pPioXfer (pPioXfer), // input
.tfd_sts (tfd_sts), // input[7:0]
/// .tfd_err (tfd_err), // input[7:0]
.fis_i (fis_i), // input
/// .sdb_n (sdb_n), // input
.dma_a (dma_a), // input
/// .dma_d (dma_d), // input
.pio_i (pio_i), // input
.pio_d (pio_d), // input
/// .sactive0 (sactive0), // input
/// .pio_es (pio_es), // input[7:0]
/// .xfer_cntr (xfer_cntr[31:2]), // input[31:2]
.xfer_cntr_zero (xfer_cntr_zero), // input
.fetch_cmd (fsnd_fetch_cmd), // output
.cfis_xmit (fsnd_cfis_xmit), // output
.dx_xmit (fsnd_dx_xmit), // output
.atapi_xmit (fsnd_atapi_xmit), // output
.xmit_done (fsnd_done), // input
/// .xmit_busy (fsnd_busy), // input
.clearCmdToIssue (fsnd_clearCmdToIssue),// output // From CFIS:SUCCESS
.pCmdToIssue (fsnd_pCmdToIssue), // input
.dx_err (fsnd_dx_err), // input[2:0]
/// .ch_prdtl (prdtl), // input[15:0]
.ch_c (fsnd_ch_c), // input
.ch_b (fsnd_ch_b), // input
.ch_r (fsnd_ch_r), // input
.ch_p (fsnd_ch_p), // input
.ch_w (fsnd_ch_w), // input
.ch_a (fsnd_ch_a), // input
/// .ch_cfl (fsnd_ch_cfl), // input[4:0]
/// .dwords_sent (data_out_dwords) // input[11:0] ????
.unsolicited_en (unsolicited_en), // input
.last_jump_addr (last_jump_addr)
);
wire debug_data_in_ready; // output
wire debug_fis_end_w; // output
wire[1:0] debug_fis_end_r; // output[1:0]
wire[1:0] debug_get_fis_busy_r; // output[1:0]
localparam DATA_TYPE_DMA = 0;
localparam DATA_TYPE_FIS_HEAD = 1;
localparam DATA_TYPE_OK = 2;
localparam DATA_TYPE_ERR = 3;
reg [12:0] debug_d2h_length;
reg [12:0] debug_d2h_length_prev;
reg was_good_bad;
reg was_good_bad_prev;
always @(posedge mclk) if (d2h_ready && d2h_valid) begin
if (d2h_type == DATA_TYPE_FIS_HEAD) debug_d2h_length_prev <= debug_d2h_length;
if (d2h_type == DATA_TYPE_FIS_HEAD) debug_d2h_length <= 0;
else if (d2h_type == DATA_TYPE_DMA) debug_d2h_length <= debug_d2h_length + 1;
if (d2h_type == DATA_TYPE_FIS_HEAD) was_good_bad_prev <= was_good_bad;
if ((d2h_type == DATA_TYPE_OK) || (d2h_type == DATA_TYPE_ERR)) was_good_bad <= (d2h_type == DATA_TYPE_OK);
end
axi_ahci_regs #(
.ADDRESS_BITS (ADDRESS_BITS),
.HBA_RESET_BITS (HBA_RESET_BITS),
.RESET_TO_FIRST_ACCESS (RESET_TO_FIRST_ACCESS)
) axi_ahci_regs_i (
.aclk (aclk), // input
.arst (arst), // input
.awaddr (awaddr), // input[31:0]
.awvalid (awvalid), // input
.awready (awready), // output
.awid (awid), // input[11:0]
.awlen (awlen), // input[3:0]
.awsize (awsize), // input[1:0]
.awburst (awburst), // input[1:0]
.wdata (wdata), // input[31:0]
.wvalid (wvalid), // input
.wready (wready), // output
.wid (wid), // input[11:0]
.wlast (wlast), // input
.wstb (wstb), // input[3:0]
.bvalid (bvalid), // output
.bready (bready), // input
.bid (bid), // output[11:0]
.bresp (bresp), // output[1:0]
.araddr (araddr), // input[31:0]
.arvalid (arvalid), // input
.arready (arready), // output
.arid (arid), // input[11:0]
.arlen (arlen), // input[3:0]
.arsize (arsize), // input[1:0]
.arburst (arburst), // input[1:0]
.rdata (rdata), // output[31:0]
.rvalid (rvalid), // output
.rready (rready), // input
.rid (rid), // output[11:0]
.rlast (rlast), // output
.rresp (rresp), // output[1:0]
.soft_write_addr (soft_write_addr), // output[9:0]
.soft_write_data (soft_write_data), // output[31:0]
.soft_write_en (soft_write_en), // output
.hba_arst (hba_arst), // output // does not include arst
.port_arst_any (port_arst_any), // async set by arst
.port_arst (port_arst), // output // does not include arst
.hba_clk (mclk), // input
.hba_rst (mrst), // input // deasserted when mclk is stable
.hba_addr (regs_addr), // input[9:0]
.hba_we (regs_we), // input
.hba_re (regs_re), // input[1:0]
.hba_din (regs_din), // input[31:0]
.hba_dout (regs_dout), // output[31:0]
.pgm_ad (fsm_pgm_ad), // output[17:0] reg
.pgm_wa (fsm_pgm_wa), // output reg
.pgm_wd (fsm_pgm_wd), // output reg
.afi_wcache (axi_wr_cache_mode),// output[3:0] reg
.afi_rcache (axi_rd_cache_mode),// output[3:0] reg
.afi_cache_set (set_axi_cache_mode), // output
.was_hba_rst (was_hba_rst), // output
.was_port_rst (was_port_rst), // output
.debug_in0 ({ 2'b0,
was_good_bad_prev,
debug_d2h_length_prev[12:0],
2'b0,
was_good_bad,
debug_d2h_length[12:0]
}),
// .debug_in1 ({xclk_period[7:0], // lower 8 bits of 12-bit value. Same frequency would be 0x800 (msb opposite to 3 next bits)
// debug_dma1[23:0]}), // debug_in_link), // input[31:0]
.debug_in1 ({debug_in_link[15:8],
debug_dma1[23:0]}), // debug_in_link), // input[31:0]
.debug_in2 (debug_in_phy), // input[31:0] // debug from phy/link
// .debug_in3 ({22'b0, last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer
.debug_in3 ({debug_in_link[7:0],
frcv_busy,frcv_ok, // 2'b0,
`ifdef USE_DATASCOPE
datascope_waddr[9:0],
`else
10'b0,
`endif
frcv_err,frcv_ferr, // 2'b0,
last_jump_addr[9:0]}) // input[31:0]// Last jump address in the AHDCI sequencer
`ifdef USE_DRP
,.drp_en (drp_en), // output reg
.drp_we (drp_we), // output reg
.drp_addr (drp_addr), // output[14:0] reg
.drp_di (drp_di), // output[15:0] reg
.drp_rdy (drp_rdy), // input
.drp_do (drp_do) // input[15:0]
`endif
`ifdef USE_DATASCOPE
,.datascope_clk (datascope_clk), // input
.datascope_waddr (datascope_waddr), // input[9:0]
.datascope_we (datascope_we), // input
.datascope_di (datascope_di), // input[31:0]
.datascope1_clk (datascope1_clk), // input
.datascope1_waddr (datascope1_waddr),// input[9:0]
.datascope1_we (datascope1_we), // input
.datascope1_di (datascope1_di) // input[31:0]
`endif
/// .debug_in (debug_in[31:0])
);
ahci_ctrl_stat #(
.ADDRESS_BITS (ADDRESS_BITS)
) ahci_ctrl_stat_i (
.mrst (mrst), // input
.mclk (mclk), // input
.was_hba_rst (was_hba_rst), // input
.was_port_rst (was_port_rst), // input
.soft_write_addr (soft_write_addr), // input[9:0]
.soft_write_data (soft_write_data), // input[31:0]
.soft_write_en (soft_write_en), // input
.regs_addr (regs_saddr), // output[9:0] reg
.regs_we (regs_we_acs), // output reg
.regs_din (regs_din_from_acs), // output[31:0] reg
.update_pending (), /// update_regs_pending), // output
.update_all (update_all_regs), // input
.update_busy (update_regs_busy), // output
/// .st01_pending (st01_pending), // output reg
/// .st10_pending (st10_pending), // output reg
/// .st_pending_reset (st_pending_reset), // input
.update_gis (1'b0), // update_GHC__IS), // input
.update_pis (1'b0), // update_HBA_PORT__PxIS), // input
.update_ssts (1'b0), // update_HBA_PORT__PxSSTS), // input
.update_serr (1'b0), // update_HBA_PORT__PxSERR), // input
.update_pcmd (1'b0), // update_HBA_PORT__PxCMD), // input
.update_pci (1'b0), // update_HBA_PORT__PxCI), // input
.update_ghc (1'b0), // update _GHC_GHC, // input
// .pcmd_clear_icc (1'b0), // pcmd_clear_icc), // input
.pcmd_esp (pcmd_esp), // input
.pcmd_cr (), //pcmd_cr), // output
.pcmd_cr_set (pcmd_cr_set), // input
.pcmd_cr_reset (pcmd_cr_reset), // input
.pcmd_fr (frcv_busy), // input
.pcmd_fre (pcmd_fre0), // output
.pcmd_clear_bsy_drq (frcv_clear_bsy_drq), // input
.pcmd_clo (pcmd_clo), // output
.pcmd_clear_st (1'b0), // pcmd_clear_st), // input
.pcmd_st (pcmd_st), // output
.pfsm_started (pfsm_started), // input
.pcmd_st_cleared (pcmd_st_cleared), // output reg
.sirq_TFE (sirq_TFE), // input
.sirq_IF (sirq_IF), // input
.sirq_INF (sirq_INF), // input
.sirq_OF (sirq_OF), // input
.sirq_PRC (sirq_PRC), // input
.sirq_PC (sirq_PC), // input
.sirq_DP (sirq_DP), // input
.sirq_UF (sirq_UF), // input
.sirq_SDB (sirq_SDB), // input
.sirq_DS (sirq_DS), // input
.sirq_PS (sirq_PS), // input
.sirq_DHR (sirq_DHR), // input
.serr_DT (serr_DT), // input
.serr_DS (serr_DS), // input
.serr_DH (serr_DH), // input
.serr_DC (serr_DC), // input
.serr_DB (serr_DB), // input
.serr_DW (serr_DW), // input
.serr_DI (serr_DI), // input
.serr_EE (serr_EE), // input
.serr_EP (serr_EP), // input
.serr_EC (serr_EC), // input
.serr_ET (serr_ET), // input
.serr_EM (serr_EM), // input
.serr_EI (serr_EI), // input
.serr_diag_X (serr_diag_X), // output
.ssts_ipm_dnp (ssts_ipm_dnp), // input
.ssts_ipm_active (ssts_ipm_active), // input
.ssts_ipm_part (ssts_ipm_part), // input
.ssts_ipm_slumb (ssts_ipm_slumb), // input
.ssts_ipm_devsleep (ssts_ipm_devsleep), // input
.ssts_spd_dnp (ssts_spd_dnp), // input
.ssts_spd_gen1 (ssts_spd_gen1), // input
.ssts_spd_gen2 (ssts_spd_gen2), // input
.ssts_spd_gen3 (ssts_spd_gen3), // input
.ssts_det_ndnp (ssts_det_ndnp), // input
.ssts_det_dnp (ssts_det_dnp), // input
.ssts_det_dp (ssts_det_dp), // input
.ssts_det_offline (ssts_det_offline), // input
.ssts_det (ssts_det), // output[3:0]
.sctl_ipm (sctl_ipm), // output[3:0] reg
.sctl_spd (sctl_spd), // output[3:0] reg
.sctl_det (sctl_det), // output[3:0] reg
.sctl_det_changed (sctl_det_changed), // output reg
.sctl_det_reset (sctl_det_reset), // input
.pxci0_clear (pxci0_clear), // input
.pxci0 (pxci0), // output
.hba_reset_done (hba_rst_done), // input
.unsolicited_en (unsolicited_en), // output
.irq (irq) // output reg
);
ahci_dma ahci_dma_i (
.mrst (mrst), // input
.hrst (hrst), // input
.mclk (mclk), // input
.hclk (hclk), // input
// .ctba (regs_dout[31:7]),// input[31:7]
.ctba (regs_dout[31:4]),// input[31:4]
.ctba_ld (ctba_ld), // input
.prdtl (prdtl), // input[15:0]
.dev_wr (dev_wr), // input
.cmd_start (dma_cmd_start), // input
.prd_start (dma_prd_start), // input
.cmd_abort (dma_cmd_abort_xmit || dma_cmd_abort_fsm), // input
.axi_wr_cache_mode (axi_wr_cache_mode), // input[3:0]
.axi_rd_cache_mode (axi_rd_cache_mode), // input[3:0]
.set_axi_wr_cache_mode (set_axi_cache_mode), // input
.set_axi_rd_cache_mode (set_axi_cache_mode), // input
.ct_busy (dma_ct_busy), // output reg
.ct_addr (dma_ct_addr), // input[4:0]
.ct_re (dma_ct_re), // input[1:0]
.ct_data (dma_ct_data), // output[31:0] reg
.prd_done (), /// dma_prd_done), // output
.prd_irq_clear (dma_prd_irq_clear),// input
.prd_irq_pend (dma_prd_irq_pend), // output reg
.cmd_busy (dma_cmd_busy), // dma_cmd_busy), // output reg Some data to transmit!
.cmd_done (dma_cmd_done), // output
.abort_busy (dma_abort_busy),
.abort_done (dma_abort_done),
.axi_mismatch (axi_mismatch), // handled, but may report as an error - axi counters are 0, but calculated ones are not
.sys_out (dma_dout), // output[31:0]
.sys_dav (dma_dav), // output
.sys_re (dma_re), // input
.last_h2d_data (last_h2d_data), // output
.sys_in (d2h_data), // input[31:0]
.sys_nfull (dma_in_ready), // output
.sys_we (dma_we), // input
.extra_din (dma_extra_din), // output reg
.afi_awaddr (afi_awaddr), // output[31:0]
.afi_awvalid (afi_awvalid), // output
.afi_awready (afi_awready), // input
.afi_awid (afi_awid), // output[5:0]
.afi_awlock (afi_awlock), // output[1:0]
.afi_awcache (afi_awcache), // output[3:0] reg
.afi_awprot (afi_awprot), // output[2:0]
.afi_awlen (afi_awlen), // output[3:0]
.afi_awsize (afi_awsize), // output[1:0]
.afi_awburst (afi_awburst), // output[1:0]
.afi_awqos (afi_awqos), // output[3:0]
.afi_wdata (afi_wdata), // output[63:0]
.afi_wvalid (afi_wvalid), // output
.afi_wready (afi_wready), // input
.afi_wid (afi_wid), // output[5:0]
.afi_wlast (afi_wlast), // output
.afi_wstrb (afi_wstrb), // output[7:0]
.afi_bvalid (afi_bvalid), // input
.afi_bready (afi_bready), // output
.afi_bid (afi_bid), // input[5:0]
.afi_bresp (afi_bresp), // input[1:0]
.afi_wcount (afi_wcount), // input[7:0]
.afi_wacount (afi_wacount), // input[5:0]
.afi_wrissuecap1en (afi_wrissuecap1en), // output
.afi_araddr (afi_araddr), // output[31:0]
.afi_arvalid (afi_arvalid), // output
.afi_arready (afi_arready), // input
.afi_arid (afi_arid), // output[5:0]
.afi_arlock (afi_arlock), // output[1:0]
.afi_arcache (afi_arcache), // output[3:0] reg
.afi_arprot (afi_arprot), // output[2:0]
.afi_arlen (afi_arlen), // output[3:0]
.afi_arsize (afi_arsize), // output[1:0]
.afi_arburst (afi_arburst), // output[1:0]
.afi_arqos (afi_arqos), // output[3:0]
.afi_rdata (afi_rdata), // input[63:0]
.afi_rvalid (afi_rvalid), // input
.afi_rready (afi_rready), // output
.afi_rid (afi_rid), // input[5:0]
.afi_rlast (afi_rlast), // input
.afi_rresp (afi_rresp), // input[1:0]
.afi_rcount (afi_rcount), // input[7:0]
.afi_racount (afi_racount), // input[2:0]
.afi_rdissuecap1en (afi_rdissuecap1en), // output
.debug_out (debug_dma), // output[31:0]
.debug_out1 (debug_dma1) // output[31:0]
,.debug_dma_h2d (debug_dma_h2d)
);
ahci_fis_receive #(
.ADDRESS_BITS (ADDRESS_BITS)
) ahci_fis_receive_i (
.hba_rst (mrst), // input
.mclk (mclk), // input
.pcmd_st_cleared (pcmd_st_cleared), // input
.fis_first_vld (frcv_first_vld), // output reg
.fis_first_invalid (frcv_first_invalid), // output
.fis_first_flush (frcv_first_flush), // input
.get_dsfis (frcv_get_dsfis), // input
.get_psfis (frcv_get_psfis), // input
.get_rfis (frcv_get_rfis), // input
.get_sdbfis (frcv_get_sdbfis), // input
.get_ufis (frcv_get_ufis), // input
.get_data_fis (frcv_get_data_fis), // input
.get_ignore (frcv_get_ignore), // input
.get_fis_busy (frcv_busy), // output reg
.get_fis_done (frcv_done), // output reg
.fis_ok (frcv_ok), // output reg
.fis_err (frcv_err), // output reg
.fis_ferr (frcv_ferr), // output
.dma_prds_done (dma_cmd_done), // input
.fis_extra (frcv_extra), // output
.set_update_sig (frcv_set_update_sig), // input
.pUpdateSig (), /// frcv_pUpdateSig), // output
.sig_available (), ///frcv_sig_available), // output reg
.update_sig (frcv_update_sig), // input
.update_err_sts (frcv_update_err_sts), // input
.update_pio (frcv_update_pio), // input update PxTFD.STS and PxTFD.ERR from pio_* (entry PIO:Update)
.update_prdbc (frcv_update_prdbc), // input
.clear_prdbc (fsnd_fetch_cmd), // input save resources - clear prdbc for every commnad
.clear_bsy_drq (frcv_clear_bsy_drq), // input
.clear_bsy_set_drq (frcv_clear_bsy_set_drq), // input
.set_bsy (frcv_set_bsy), // input
.set_sts_7f (frcv_set_sts_7f), // input
.set_sts_80 (frcv_set_sts_80), // input
.clear_xfer_cntr (frcv_clear_xfer_cntr), // input Clear pXferCntr
.decr_dwcr (frcv_decr_dwcr), // input
.decr_dwcw (frcv_decr_dwcw), // input
.decr_DXC_dw (data_out_dwords), // input[11:2]
.pcmd_fre (pcmd_fre), // input
.pPioXfer (pPioXfer), // output reg
.tfd_sts (tfd_sts), // output[7:0]
.tfd_err (), /// tfd_err), // output[7:0]
.fis_i (fis_i), // output reg
.sdb_n (), /// sdb_n), // output reg
.dma_a (dma_a), // output reg
.dma_d (), /// dma_d), // output reg
.pio_i (pio_i), // output reg
.pio_d (pio_d), // output reg
.pio_es (), /// pio_es), // output[7:0] reg
.sactive0 (), /// sactive0), // output reg
.xfer_cntr (xfer_cntr[31:2]), // output[31:2]
.xfer_cntr_zero (xfer_cntr_zero), // output reg
.data_in_dwords (), /// data_in_dwords), // output[11:0]
.reg_addr (regs_waddr), // output[9:0] reg
.reg_we (regs_we_freceive), // output reg
.reg_data (regs_din_from_freceive), // output[31:0] reg
.hba_data_in (d2h_data), // input[31:0]
.hba_data_in_type (d2h_type), // input[1:0]
.hba_data_in_valid (d2h_valid), // input
.hba_data_in_many (d2h_many), // input
.hba_data_in_ready (d2h_ready), // output
.dma_in_ready (dma_in_ready), // input
.dma_in_valid (dma_we) // output
,.debug_data_in_ready (debug_data_in_ready), // output
.debug_fis_end_w (debug_fis_end_w), // output
.debug_fis_end_r (debug_fis_end_r), // output[1:0]
.debug_get_fis_busy_r (debug_get_fis_busy_r) // output[1:0]
);
wire ahci_fis_transmit_busy;
wire [9:0] xmit_dbg_01;
ahci_fis_transmit #(
.PREFETCH_ALWAYS (PREFETCH_ALWAYS),
.READ_REG_LATENCY (READ_REG_LATENCY),
.READ_CT_LATENCY (READ_CT_LATENCY),
.ADDRESS_BITS (ADDRESS_BITS)
) ahci_fis_transmit_i (
// .hba_rst (mrst), // input TODO: Reset when !PxCMD.ST? pcmd_st
.hba_rst (mrst || !pcmd_st), // input TODO: Reset when !PxCMD.ST? pcmd_st
.mclk (mclk), // input
.pcmd_st_cleared (pcmd_st_cleared), // input
.fetch_cmd (fsnd_fetch_cmd), // input
.cfis_xmit (fsnd_cfis_xmit), // input
.dx_xmit (fsnd_dx_xmit), // input
.atapi_xmit (fsnd_atapi_xmit), // input
.done (fsnd_done), // output reg
.busy (ahci_fis_transmit_busy), /// fsnd_busy), // output reg
.clearCmdToIssue (fsnd_clearCmdToIssue), // input
.pCmdToIssue (fsnd_pCmdToIssue), // output
.xmit_ok (xmit_ok), // input
.xmit_err (xmit_err), // input
.syncesc_recv (syncesc_recv), // input
.xrdy_collision (x_rdy_collision), // input
.dx_err (fsnd_dx_err), // output[1:0]
.ch_prdtl (prdtl), // output[15:0]
.ch_c (fsnd_ch_c), // output
.ch_b (fsnd_ch_b), // output
.ch_r (fsnd_ch_r), // output
.ch_p (fsnd_ch_p), // output
.ch_w (fsnd_ch_w), // output
.ch_a (fsnd_ch_a), // output
.ch_cfl (), /// fsnd_ch_cfl), // output[4:0]
.dwords_sent (data_out_dwords), // output[11:0] reg
.reg_addr (regs_raddr), // output[9:0] reg
.reg_re (regs_re_ftransmit), // output[1:0]
.reg_rdata (regs_dout), // input[31:0]
.xfer_cntr (xfer_cntr[31:2]), // input[31:2]
.xfer_cntr_zero (xfer_cntr_zero), // input
.dma_ctba_ld (ctba_ld), // output
.dma_start (dma_cmd_start), // output
.dma_dev_wr (dev_wr), // output
.dma_ct_busy (dma_ct_busy), // input
.dma_prd_start (dma_prd_start), // output reg
.dma_cmd_abort (dma_cmd_abort_xmit), // output reg
.ct_addr (dma_ct_addr), // output[4:0] reg
.ct_re (dma_ct_re), // output[1:0]
.ct_data (dma_ct_data), // input[31:0]
.dma_out (dma_dout), // input[31:0]
.dma_dav (dma_dav), // input
.dma_re (dma_re), // output
.last_h2d_data (last_h2d_data), // input
.todev_data (h2d_data), // output[31:0] reg
.todev_type (h2d_type), // output[1:0] reg
.todev_valid (h2d_valid), // output
.todev_ready (h2d_ready) // input
,.debug_01(xmit_dbg_01)
);
// Datascope code
//`define DATASCOPE_V2
// Datascope interface (write to memory that can be software-read)
`define DATASCOPE_FIS_DATA 1
`ifdef USE_DATASCOPE
`ifdef DATASCOPE_V2
reg [ADDRESS_BITS-1:0] datascope_waddr_r;
reg [1:0] datascope_run;
// reg [1:0] datascope_run;
assign datascope_we = datascope_run[1];
assign datascope_clk = mclk;
assign datascope_waddr = datascope_waddr_r;
assign datascope_di = {
debug_dma_h2d[3], // done_flush_mclk,
debug_dma_h2d[2], // dout_vld,
debug_dma_h2d[1], // dout_re,
debug_dma_h2d[0], // last_DW,
dma_dout[27:16],
debug_dma_h2d[19:18], // 2'b0
debug_dma_h2d[17], // fifo_rd
debug_dma_h2d[16:12], // raddr[4:0]
debug_dma_h2d[11:8], //fifo_do_vld[3:0]
debug_dma_h2d[7], // fifo_dav
debug_dma_h2d[6], // fifo_dav2_w
debug_dma_h2d[5], // fifo_dav2
debug_dma_h2d[4] // flushing_mclk
};
// dma_dout[
always @ (posedge mclk) begin
if (mrst) datascope_run[0] <= 0;
else if (dma_cmd_start) datascope_run[0] <= 1;
else if (dma_cmd_done) datascope_run[0] <= 0;
if (mrst || !datascope_run[0]) datascope_run[1] <= 0;
else if (dma_dav) datascope_run[1] <= 1;
if (fsnd_cfis_xmit) datascope_waddr_r <= 0;
else if (datascope_we) datascope_waddr_r <= datascope_waddr_r + 1;
end
//`endif // DATASCOPE_V2
`else
//`ifdef DATASCOPE_V1
`ifdef DATASCOPE_FIS_DATA
datascope_timing #(
.ADDRESS_BITS(10),
.FIS_LEN(5)
) datascope_timing_i (
.clk (mclk), // input
.rst (mrst), // input
.soft_write_addr (soft_write_addr), // input[9:0]
.soft_write_data (soft_write_data), // input[31:0]
.soft_write_en (soft_write_en), // input
.cfis (fsnd_cfis_xmit), // input command FIS - to reset dword counter
.h2d_data (h2d_data), // input[31:0]
.h2d_type (h2d_type), // input[1:0]
.h2d_valid (h2d_valid), // input
.h2d_ready (h2d_ready), // input
.d2h_data (d2h_data), // input[31:0]
.d2h_type (d2h_type), // input[1:0]
.d2h_valid (d2h_valid), // input
.d2h_ready (d2h_ready), // input
.debug_link_send_data(debug_link_send_data), // input
.debug_link_dmatp (debug_link_dmatp), // link received DMATp from device
.irq (irq), // system IRQ
.datascope_clk (datascope_clk), // output
.datascope_waddr (datascope_waddr), // output[9:0] reg
.datascope_we (datascope_we), // output
.datascope_di (datascope_di) // output[31:0] reg
);
`else // DATASCOPE_FIS_DATA
localparam DATASCOPE_CFIS_START=0;
localparam DATASCOPE_INCOMING_POST=32;
reg [ADDRESS_BITS-1:0] datascope_waddr_r=0;
reg [1:0] datascope_run;
reg datascope_link_run;
wire datascope_is_state_send_ready = (debug_in_link[4:0] == 16);
wire datascope_is_state_idle = (debug_in_link[4:0] == 22);
reg datascope_was_state_send_ready;
reg [3:0] datascope_id;
wire datascope_incoming_start = debug_in_link[22]; // set_rcvr_wait; // start logging
wire datascope_incoming_started = debug_in_phy[21:20] == 1; //
wire datascope_incomining_preend = debug_in_phy[21]; // d2h_type_in[1
reg [2:0] datascope_incoming_run;
reg [7:0] datascope_incoming_cntr;
reg datascope_receive_fis;
reg [9:0] datascope_last_jump_addr=0;
reg [1:0] datascope_new_jump = 0;
reg [15:0] datascope_jump_cntr = 0;
//last_jump_addr[9:0]
always @(posedge mclk) begin
if (mrst) datascope_new_jump[0] <= 0;
else datascope_new_jump[0] <= datascope_last_jump_addr != last_jump_addr;
if (mrst) datascope_new_jump[1] <= 0;
else datascope_new_jump[1] <= datascope_new_jump[0];
if (mrst) datascope_last_jump_addr <= 0;
if (datascope_new_jump) datascope_last_jump_addr <= last_jump_addr;
if (datascope_we) datascope_jump_cntr <= datascope_jump_cntr+1;
if (mrst) datascope_receive_fis <= 0;
else if (datascope_incoming_start) datascope_receive_fis <= 1;
else if (frcv_get_dsfis ||
frcv_get_psfis ||
frcv_get_rfis ||
frcv_get_sdbfis ||
frcv_get_ufis ||
frcv_get_data_fis ||
frcv_get_ignore) datascope_receive_fis <= 0;
if (mrst) datascope_incoming_run[0] <= 0;
else if (datascope_incoming_start || datascope_receive_fis) datascope_incoming_run[0] <= 1;
else if (datascope_incoming_cntr == 0) datascope_incoming_run[0] <= 0;
if (mrst || datascope_incoming_start) datascope_incoming_run[1] <= 0;
else if (datascope_incoming_run[0] && datascope_incoming_started) datascope_incoming_run[1] <= 1;
else if (datascope_incoming_run[2]) datascope_incoming_run[1] <= 0;
if (mrst || datascope_incoming_start) datascope_incoming_run[2] <= 0;
else if (datascope_incoming_run[1] && datascope_incomining_preend) datascope_incoming_run[2] <= 1;
else if (datascope_incoming_cntr == 0) datascope_incoming_run[2] <= 0;
if (mrst || !datascope_incoming_run[2] ||
datascope_incoming_start ||
datascope_receive_fis) datascope_incoming_cntr <= DATASCOPE_INCOMING_POST;
else if (|datascope_incoming_cntr) datascope_incoming_cntr <= datascope_incoming_cntr - 1;
end
assign datascope_clk = mclk;
assign datascope_waddr = last_jump_addr;
assign datascope_we = &datascope_new_jump;
assign datascope_di = {2'h3, fsnd_pCmdToIssue, xfer_cntr_zero, 2'b0, last_jump_addr[9:0],datascope_jump_cntr};
always @(posedge mclk) begin
if (mrst) datascope_run[0] <= 0;
else if (fsnd_cfis_xmit) datascope_run[0] <= 1;
else if (h2d_valid && h2d_ready && (h2d_type == 2)) datascope_run[0] <= 0;
if (mrst) datascope_link_run <= 0;
else if (datascope_is_state_send_ready && !datascope_was_state_send_ready) datascope_link_run <= 1; // state_send_sof
else if (datascope_is_state_idle) datascope_link_run <= 0; // state_idle
datascope_was_state_send_ready <= datascope_is_state_send_ready;
datascope_run[1] <= datascope_run[0];
if (mrst) datascope_id <= 0;
else if (fsnd_cfis_xmit) datascope_id <= datascope_id + 1;
end
`endif // DATASCOPE_FIS_DATA
`endif // DATASCOPE_V1
`endif // USE_DATASCOPE
endmodule
module datascope_timing #(
parameter ADDRESS_BITS = 10, // for datascope
parameter FIS_LEN = 5 // Record this number of DWORDS in each FIS
)(
input clk,
input rst,
// receiving time punch command and 3-bit tag
input [ADDRESS_BITS-1:0] soft_write_addr,
input [31:0] soft_write_data,
input soft_write_en,
input cfis, // to reset send counter
// outgoing FISes
input [31:0] h2d_data, // 32-bit data from the system memory to HBA (dma data)
input [ 1:0] h2d_type, // 0 - data, 1 - FIS head, 2 - FIS END (make FIS_Last?)
input h2d_valid, // output register full
input h2d_ready, // send FIFO has room for data (>= 8? dwords)
// Incoming FISes
// Data/type FIFO, device -> host
input [31:0] d2h_data, // FIFO output data
input [ 1:0] d2h_type, // 0 - data, 1 - FIS head, 2 - R_OK, 3 - R_ERR
input d2h_valid, // Data available from the transport layer in FIFO
input d2h_ready, // This module or DMA consumes DWORD
input debug_link_send_data, // @posedge mclk (sata_clk, 75MHz) - last symbol was data output (to count sent out)
input debug_link_dmatp, // link received DMATp from device
input irq, // system irq
output datascope_clk,
output reg [ADDRESS_BITS-1:0] datascope_waddr,
output datascope_we,
output reg [31:0] datascope_di
);
`include "includes/ahci_localparams.vh" // @SuppressThisWarning VEditor : Unused localparams
reg [2:0] punch_tag;
wire write_tag_w = soft_write_en && (soft_write_addr[ADDRESS_BITS-1:0] == HBA_PORT__PunchTime__TAG__ADDR);
reg pend_punch_time;
wire write_punch_time = pend_punch_time && !fis_start && !fis_run && !fis_run_d;
reg fis_run;
reg fis_run_d;
reg fis_we; // recording FIS data (until end or max len)
reg [12:0] fis_len;
reg [12:0] fis_left;
reg [31:0] fis_data;
reg [27:0] cur_time;
reg was_h2d_last;
reg h2d_ready_d; // delayed h2d_ready to count 1->0 transitions
reg [ 7:0] h2d_nready_cntr; // count (infrequent) events when h2d FIFO turns off ready
// reg
wire fis_start = (h2d_valid && h2d_ready && (h2d_type == 1)) ||
(d2h_valid && d2h_ready && (d2h_type == 1));
wire fis_end = (d2h_valid? (d2h_valid && d2h_ready && d2h_type[1]): was_h2d_last);
// wire fis_end_we = (fis_left == 0) || fis_end;
wire pre_we_w = fis_run && (d2h_valid?(d2h_valid && d2h_ready):(h2d_valid && h2d_ready));
reg fis_run_d2;
reg fis_run_d3;
reg fis_run_d4; // to read non 0x39 d2h fis
reg fis_run_d5; // number of dwords sent by link a s data symbols
// reg fis_first;
reg data_fis;
reg pre_we_r;
reg we_r;
wire inc_dw_cntr = fis_run && (d2h_valid?(d2h_ready && (d2h_type == 0)):(h2d_valid && h2d_ready));
wire is_cfis_w = h2d_valid && (h2d_data[ 7: 0] == 8'h27) && // valid @ fis_start
((h2d_data[23:16] == 8'h25) || // Read DMA Extended
(h2d_data[23:16] == 8'h35) || // Write DMA Extended
(h2d_data[23:16] == 8'hC8) || // Read DMA
(h2d_data[23:16] == 8'hCA)); // Write DMA
reg is_cfis_r;
reg [23:0] last_dma_cmd;
reg set_dma_count;
reg [21:0] dw_count;
wire [7:0] fis_data_w = d2h_valid ? d2h_data[7:0] : h2d_data[7:0];
reg [31:0] non_dma_act; // last D2H FIS that was not DMA activate, received after DMA/IO command
reg set_non_dma_act;
reg [21:0] link_count;
reg [21:0] link_count_latched;
reg reset_link_count; // data FIS from dma command until
reg was_link_dmatp; //
reg irq_r;
reg irq_was;
wire we_w = write_punch_time || fis_start || (fis_we ? pre_we_r : (!fis_run && (fis_run_d || fis_run_d2 || fis_run_d3 || fis_run_d4 || fis_run_d5))); // 3 after
wire we_irq= (irq_was ^ irq_r) && !we_w; // only when not irq
// input debug_link_dmatp, // link received DMATp from device
assign datascope_we = we_r;
assign datascope_clk = clk;
always @ (posedge clk) begin
was_h2d_last <= h2d_type[1] && h2d_valid && h2d_ready;
if (rst) cur_time <= 0;
else cur_time <= cur_time + 1;
if (write_tag_w) punch_tag <= soft_write_data[2:0];
if (rst) pend_punch_time <= 0;
else if (write_tag_w) pend_punch_time <= 1;
else if (write_punch_time) pend_punch_time <= 0;
if (write_punch_time || fis_start) datascope_di <= {write_punch_time?{1'b1,punch_tag}:{3'b0,d2h_valid},cur_time};
else if (fis_we) datascope_di <= fis_data;
else if (!fis_run && fis_run_d) datascope_di <= {19'h7fff8, fis_len};
else if (!fis_run_d && fis_run_d2) datascope_di <= {10'h2a8, dw_count};
else if (!fis_run_d2 && fis_run_d3) datascope_di <= {8'h55, last_dma_cmd};
else if (!fis_run_d3 && fis_run_d4) datascope_di <= non_dma_act;
else if (!fis_run_d4 && fis_run_d5) datascope_di <= {h2d_nready_cntr[7:0], was_link_dmatp, 1'b0, link_count_latched};
else if (we_irq) datascope_di <= {3'h7,irq_r,cur_time};
pre_we_r <= pre_we_w || fis_start ;
// we_r <= write_punch_time || fis_start || (fis_we ? pre_we_r : (!fis_run && fis_run_d));
we_r <= we_w || we_irq;
if (fis_start) fis_left <= FIS_LEN - 1;
else if (pre_we_w) fis_left <= fis_left - 1;
// if (fis_start) fis_first <= 1;
// else if (pre_we_w) fis_first <= 0;
if (fis_end) data_fis <= 0;
// else if (pre_we_w && fis_start) data_fis <= fis_data_w == 8'h46;
else if (fis_start) data_fis <= fis_data_w == 8'h46;
if (rst) fis_we <= 0;
else if (fis_start) fis_we <= 1;
else if ((fis_left == 0) || fis_end) fis_we <= 0;
if (rst) fis_run <= 0;
else if (fis_start) fis_run <= 1;
else if (fis_end) fis_run <= 0;
fis_run_d <= fis_run;
fis_run_d2 <= fis_run_d;
fis_run_d3 <= fis_run_d2;
fis_run_d4 <= fis_run_d3;
fis_run_d5 <= fis_run_d4;
if (cfis) dw_count <= 0;
else if (inc_dw_cntr && data_fis) dw_count <= dw_count + 1;
if (rst) reset_link_count <= 0;
else if (cfis) reset_link_count <= 1;
else if (fis_start && (fis_data_w == 8'h46)) reset_link_count <= 0;
if (reset_link_count) link_count <= 0;
else if (debug_link_send_data) link_count <= link_count + 1; // will only be valid later, latch at next fis start
if (fis_start) link_count_latched <= link_count;
if (reset_link_count) was_link_dmatp <= 0;
else if (debug_link_dmatp) was_link_dmatp <= 1;
h2d_ready_d <= h2d_ready;
if (rst) h2d_nready_cntr <= 0;
else if (!h2d_ready && h2d_ready_d) h2d_nready_cntr <= h2d_nready_cntr+1;
if (fis_start) is_cfis_r <= is_cfis_w;
if (fis_start && is_cfis_w) last_dma_cmd[23:16] <= h2d_data[23:16]; // command code
set_dma_count <= (fis_len == 3) && h2d_valid && h2d_ready && is_cfis_r;
if (set_dma_count) last_dma_cmd[15:0] <= fis_data[15:0];
set_non_dma_act <= fis_start && d2h_valid && (fis_data_w != 8'h39);
if (set_dma_count) non_dma_act <= 32'h33333333;
else if (set_non_dma_act) non_dma_act <= fis_data;
if (fis_start) fis_len <= d2h_valid? 0 : 1;
else if (pre_we_w) fis_len <= fis_len + 1;
if (fis_start || pre_we_w) fis_data <= d2h_valid ? d2h_data : h2d_data;
if (rst) datascope_waddr <= 0;
else if (we_r) datascope_waddr <= datascope_waddr + 1;
irq_r <= irq;
if (rst) irq_was <=0;
else if (we_irq) irq_was <= irq_r;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32OI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A32OI_BEHAVIORAL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32OI_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DIODE_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__DIODE_PP_SYMBOL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__diode (
//# {{power|Power}}
input DIODE,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DIODE_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__OR3_BEHAVIORAL_PP_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR3_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO0P_BLACKBOX_V
`define SKY130_FD_SC_LP__LSBUFISO0P_BLACKBOX_V
/**
* lsbufiso0p: ????.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__lsbufiso0p (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 DESTPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 DESTVPB;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO0P_BLACKBOX_V
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
//
// Filename : mc_chroma_ip4x4.v
// Created On : 2013-11-18 12:42:37
// Last Modified : 2013-11-24 16:38:17
// Revision :
// Author : Yufeng Bai
// Email : [email protected]
// Description :
//-------------------------------------------------------------------
`include "enc_defines.v"
module mc_chroma_ip4x4(
clk,
rstn,
frac_i,
blk_start_i,
refuv_valid_i,
refuv_p0_i,
refuv_p1_i,
refuv_p2_i,
refuv_p3_i,
refuv_p4_i,
refuv_p5_i,
refuv_p6_i,
frac_valid_o ,
end_oneblk_ip_o,
fracuv_o
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk;
input rstn;
input [5 :0] frac_i;
input blk_start_i;
input refuv_valid_i;
input [`PIXEL_WIDTH-1:0] refuv_p0_i;
input [`PIXEL_WIDTH-1:0] refuv_p1_i;
input [`PIXEL_WIDTH-1:0] refuv_p2_i;
input [`PIXEL_WIDTH-1:0] refuv_p3_i;
input [`PIXEL_WIDTH-1:0] refuv_p4_i;
input [`PIXEL_WIDTH-1:0] refuv_p5_i;
input [`PIXEL_WIDTH-1:0] refuv_p6_i;
output end_oneblk_ip_o;
output frac_valid_o;
output [4*`PIXEL_WIDTH-1:0] fracuv_o;
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [1:0] cnt_ip_row;
//reg end_oneblk_ip_o;
reg frac_valid_o;
reg [4*`PIXEL_WIDTH-1:0] fracuv_o;
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
wire [2:0] fracx;
wire [2:0] fracy;
wire fracuv_valid;
wire [`PIXEL_WIDTH-1:0] fracuv_p0;
wire [`PIXEL_WIDTH-1:0] fracuv_p1;
wire [`PIXEL_WIDTH-1:0] fracuv_p2;
wire [`PIXEL_WIDTH-1:0] fracuv_p3;
assign fracx = frac_i[2:0];
assign fracy = frac_i[5:3];
// ********************************************
//
// Sequential Logic Combinational Logic
//
// ********************************************
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
cnt_ip_row <= 'd0;
end
else if (blk_start_i || (end_oneblk_ip_o)) begin
cnt_ip_row <= 'd0;
end
else if (frac_valid_o) begin
cnt_ip_row <= cnt_ip_row + 'd1;
end
end
assign end_oneblk_ip_o = (cnt_ip_row == 'd3);
// ********************************************
//
// Sub Module
//
// ********************************************
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
fracuv_o <= 'd0;
frac_valid_o<= 'd0;
end
else if (fracuv_valid) begin
fracuv_o <= {fracuv_p0,fracuv_p1,fracuv_p2,fracuv_p3};
frac_valid_o<= 'd1;
end
else begin
fracuv_o <= fracuv_o;
frac_valid_o<= 'd0;
end
end
mc_chroma_ip_1p mc_chroma_ip0(
.clk (clk),
.rstn (rstn),
.blk_start_i (blk_start_i),
.fracx_i (fracx),
.fracy_i (fracy),
.ref_valid_i (refuv_valid_i),
.refuv_p0_i (refuv_p0_i),
.refuv_p1_i (refuv_p1_i),
.refuv_p2_i (refuv_p2_i),
.refuv_p3_i (refuv_p3_i),
.fracuv_valid_o(fracuv_valid),
.fracuv_p_o (fracuv_p0)
);
mc_chroma_ip_1p mc_chroma_ip1(
.clk (clk),
.rstn (rstn),
.blk_start_i (blk_start_i),
.fracx_i (fracx),
.fracy_i (fracy),
.ref_valid_i (refuv_valid_i),
.refuv_p0_i (refuv_p1_i),
.refuv_p1_i (refuv_p2_i),
.refuv_p2_i (refuv_p3_i),
.refuv_p3_i (refuv_p4_i),
.fracuv_valid_o(/*fracuv_valid*/),
.fracuv_p_o (fracuv_p1)
);
mc_chroma_ip_1p mc_chroma_ip2(
.clk (clk),
.rstn (rstn),
.blk_start_i (blk_start_i),
.fracx_i (fracx),
.fracy_i (fracy),
.ref_valid_i (refuv_valid_i),
.refuv_p0_i (refuv_p2_i),
.refuv_p1_i (refuv_p3_i),
.refuv_p2_i (refuv_p4_i),
.refuv_p3_i (refuv_p5_i),
.fracuv_valid_o(/*fracuv_valid*/),
.fracuv_p_o (fracuv_p2)
);
mc_chroma_ip_1p mc_chroma_ip3(
.clk (clk),
.rstn (rstn),
.blk_start_i (blk_start_i),
.fracx_i (fracx),
.fracy_i (fracy),
.ref_valid_i (refuv_valid_i),
.refuv_p0_i (refuv_p3_i),
.refuv_p1_i (refuv_p4_i),
.refuv_p2_i (refuv_p5_i),
.refuv_p3_i (refuv_p6_i),
.fracuv_valid_o(/*fracuv_valid*/),
.fracuv_p_o (fracuv_p3)
);
endmodule
|
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