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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Fri Sep 22 20:11:26 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ tx_axis_gen_stub.v
// Design : tx_axis_gen
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, rst, din, wr_en, rd_en, dout, full, almost_full,
empty)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,din[64:0],wr_en,rd_en,dout[64:0],full,almost_full,empty" */;
input clk;
input rst;
input [64:0]din;
input wr_en;
input rd_en;
output [64:0]dout;
output full;
output almost_full;
output empty;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__HA_PP_SYMBOL_V
`define SKY130_FD_SC_HD__HA_PP_SYMBOL_V
/**
* ha: Half adder.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__ha (
//# {{data|Data Signals}}
input A ,
input B ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__HA_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVKAPWR_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__INVKAPWR_PP_BLACKBOX_V
/**
* invkapwr: Inverter on keep-alive power rail.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__invkapwr (
Y ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVKAPWR_PP_BLACKBOX_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of aou
//
// Generated
// by: wig
// on: Mon Jun 26 16:38:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../nreset2.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: aou.v,v 1.3 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: aou.v,v $
// Revision 1.3 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of aou
//
// No user `defines in this module
module aou
//
// Generated Module aou_i1
//
(
reset_i_n // Async. Reset (CGU,PAD)
);
// Generated Module Inputs:
input reset_i_n;
// Generated Wires:
wire reset_i_n;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of aou
//
//
//!End of Module/s
// --------------------------------------------------------------
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_nios2_qsys_test_bench (
// inputs:
A_bstatus_reg,
A_ctrl_ld_non_bypass,
A_en,
A_estatus_reg,
A_status_reg,
A_valid,
A_wr_data_unfiltered,
A_wr_dst_reg,
E_add_br_to_taken_history_unfiltered,
E_valid,
M_bht_ptr_unfiltered,
M_bht_wr_data_unfiltered,
M_bht_wr_en_unfiltered,
M_mem_baddr,
M_target_pcb,
M_valid,
W_dst_regnum,
W_iw,
W_iw_op,
W_iw_opx,
W_pcb,
W_valid,
W_vinst,
W_wr_dst_reg,
clk,
d_address,
d_byteenable,
d_read,
d_write,
i_address,
i_read,
i_readdatavalid,
reset_n,
// outputs:
A_wr_data_filtered,
E_add_br_to_taken_history_filtered,
M_bht_ptr_filtered,
M_bht_wr_data_filtered,
M_bht_wr_en_filtered,
test_has_ended
)
;
output [ 31: 0] A_wr_data_filtered;
output E_add_br_to_taken_history_filtered;
output [ 7: 0] M_bht_ptr_filtered;
output [ 1: 0] M_bht_wr_data_filtered;
output M_bht_wr_en_filtered;
output test_has_ended;
input [ 31: 0] A_bstatus_reg;
input A_ctrl_ld_non_bypass;
input A_en;
input [ 31: 0] A_estatus_reg;
input [ 31: 0] A_status_reg;
input A_valid;
input [ 31: 0] A_wr_data_unfiltered;
input A_wr_dst_reg;
input E_add_br_to_taken_history_unfiltered;
input E_valid;
input [ 7: 0] M_bht_ptr_unfiltered;
input [ 1: 0] M_bht_wr_data_unfiltered;
input M_bht_wr_en_unfiltered;
input [ 19: 0] M_mem_baddr;
input [ 19: 0] M_target_pcb;
input M_valid;
input [ 4: 0] W_dst_regnum;
input [ 31: 0] W_iw;
input [ 5: 0] W_iw_op;
input [ 5: 0] W_iw_opx;
input [ 19: 0] W_pcb;
input W_valid;
input [ 55: 0] W_vinst;
input W_wr_dst_reg;
input clk;
input [ 19: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 19: 0] i_address;
input i_read;
input i_readdatavalid;
input reset_n;
reg [ 19: 0] A_mem_baddr;
reg [ 19: 0] A_target_pcb;
wire [ 31: 0] A_wr_data_filtered;
wire A_wr_data_unfiltered_0_is_x;
wire A_wr_data_unfiltered_10_is_x;
wire A_wr_data_unfiltered_11_is_x;
wire A_wr_data_unfiltered_12_is_x;
wire A_wr_data_unfiltered_13_is_x;
wire A_wr_data_unfiltered_14_is_x;
wire A_wr_data_unfiltered_15_is_x;
wire A_wr_data_unfiltered_16_is_x;
wire A_wr_data_unfiltered_17_is_x;
wire A_wr_data_unfiltered_18_is_x;
wire A_wr_data_unfiltered_19_is_x;
wire A_wr_data_unfiltered_1_is_x;
wire A_wr_data_unfiltered_20_is_x;
wire A_wr_data_unfiltered_21_is_x;
wire A_wr_data_unfiltered_22_is_x;
wire A_wr_data_unfiltered_23_is_x;
wire A_wr_data_unfiltered_24_is_x;
wire A_wr_data_unfiltered_25_is_x;
wire A_wr_data_unfiltered_26_is_x;
wire A_wr_data_unfiltered_27_is_x;
wire A_wr_data_unfiltered_28_is_x;
wire A_wr_data_unfiltered_29_is_x;
wire A_wr_data_unfiltered_2_is_x;
wire A_wr_data_unfiltered_30_is_x;
wire A_wr_data_unfiltered_31_is_x;
wire A_wr_data_unfiltered_3_is_x;
wire A_wr_data_unfiltered_4_is_x;
wire A_wr_data_unfiltered_5_is_x;
wire A_wr_data_unfiltered_6_is_x;
wire A_wr_data_unfiltered_7_is_x;
wire A_wr_data_unfiltered_8_is_x;
wire A_wr_data_unfiltered_9_is_x;
wire E_add_br_to_taken_history_filtered;
wire [ 7: 0] M_bht_ptr_filtered;
wire [ 1: 0] M_bht_wr_data_filtered;
wire M_bht_wr_en_filtered;
wire W_op_add;
wire W_op_addi;
wire W_op_and;
wire W_op_andhi;
wire W_op_andi;
wire W_op_beq;
wire W_op_bge;
wire W_op_bgeu;
wire W_op_blt;
wire W_op_bltu;
wire W_op_bne;
wire W_op_br;
wire W_op_break;
wire W_op_bret;
wire W_op_call;
wire W_op_callr;
wire W_op_cmpeq;
wire W_op_cmpeqi;
wire W_op_cmpge;
wire W_op_cmpgei;
wire W_op_cmpgeu;
wire W_op_cmpgeui;
wire W_op_cmplt;
wire W_op_cmplti;
wire W_op_cmpltu;
wire W_op_cmpltui;
wire W_op_cmpne;
wire W_op_cmpnei;
wire W_op_crst;
wire W_op_custom;
wire W_op_div;
wire W_op_divu;
wire W_op_eret;
wire W_op_flushd;
wire W_op_flushda;
wire W_op_flushi;
wire W_op_flushp;
wire W_op_hbreak;
wire W_op_initd;
wire W_op_initda;
wire W_op_initi;
wire W_op_intr;
wire W_op_jmp;
wire W_op_jmpi;
wire W_op_ldb;
wire W_op_ldbio;
wire W_op_ldbu;
wire W_op_ldbuio;
wire W_op_ldh;
wire W_op_ldhio;
wire W_op_ldhu;
wire W_op_ldhuio;
wire W_op_ldl;
wire W_op_ldw;
wire W_op_ldwio;
wire W_op_mul;
wire W_op_muli;
wire W_op_mulxss;
wire W_op_mulxsu;
wire W_op_mulxuu;
wire W_op_nextpc;
wire W_op_nor;
wire W_op_opx;
wire W_op_or;
wire W_op_orhi;
wire W_op_ori;
wire W_op_rdctl;
wire W_op_rdprs;
wire W_op_ret;
wire W_op_rol;
wire W_op_roli;
wire W_op_ror;
wire W_op_rsv02;
wire W_op_rsv09;
wire W_op_rsv10;
wire W_op_rsv17;
wire W_op_rsv18;
wire W_op_rsv25;
wire W_op_rsv26;
wire W_op_rsv33;
wire W_op_rsv34;
wire W_op_rsv41;
wire W_op_rsv42;
wire W_op_rsv49;
wire W_op_rsv57;
wire W_op_rsv61;
wire W_op_rsv62;
wire W_op_rsv63;
wire W_op_rsvx00;
wire W_op_rsvx10;
wire W_op_rsvx15;
wire W_op_rsvx17;
wire W_op_rsvx21;
wire W_op_rsvx25;
wire W_op_rsvx33;
wire W_op_rsvx34;
wire W_op_rsvx35;
wire W_op_rsvx42;
wire W_op_rsvx43;
wire W_op_rsvx44;
wire W_op_rsvx47;
wire W_op_rsvx50;
wire W_op_rsvx51;
wire W_op_rsvx55;
wire W_op_rsvx56;
wire W_op_rsvx60;
wire W_op_rsvx63;
wire W_op_sll;
wire W_op_slli;
wire W_op_sra;
wire W_op_srai;
wire W_op_srl;
wire W_op_srli;
wire W_op_stb;
wire W_op_stbio;
wire W_op_stc;
wire W_op_sth;
wire W_op_sthio;
wire W_op_stw;
wire W_op_stwio;
wire W_op_sub;
wire W_op_sync;
wire W_op_trap;
wire W_op_wrctl;
wire W_op_wrprs;
wire W_op_xor;
wire W_op_xorhi;
wire W_op_xori;
wire test_has_ended;
assign W_op_call = W_iw_op == 0;
assign W_op_jmpi = W_iw_op == 1;
assign W_op_ldbu = W_iw_op == 3;
assign W_op_addi = W_iw_op == 4;
assign W_op_stb = W_iw_op == 5;
assign W_op_br = W_iw_op == 6;
assign W_op_ldb = W_iw_op == 7;
assign W_op_cmpgei = W_iw_op == 8;
assign W_op_ldhu = W_iw_op == 11;
assign W_op_andi = W_iw_op == 12;
assign W_op_sth = W_iw_op == 13;
assign W_op_bge = W_iw_op == 14;
assign W_op_ldh = W_iw_op == 15;
assign W_op_cmplti = W_iw_op == 16;
assign W_op_initda = W_iw_op == 19;
assign W_op_ori = W_iw_op == 20;
assign W_op_stw = W_iw_op == 21;
assign W_op_blt = W_iw_op == 22;
assign W_op_ldw = W_iw_op == 23;
assign W_op_cmpnei = W_iw_op == 24;
assign W_op_flushda = W_iw_op == 27;
assign W_op_xori = W_iw_op == 28;
assign W_op_stc = W_iw_op == 29;
assign W_op_bne = W_iw_op == 30;
assign W_op_ldl = W_iw_op == 31;
assign W_op_cmpeqi = W_iw_op == 32;
assign W_op_ldbuio = W_iw_op == 35;
assign W_op_muli = W_iw_op == 36;
assign W_op_stbio = W_iw_op == 37;
assign W_op_beq = W_iw_op == 38;
assign W_op_ldbio = W_iw_op == 39;
assign W_op_cmpgeui = W_iw_op == 40;
assign W_op_ldhuio = W_iw_op == 43;
assign W_op_andhi = W_iw_op == 44;
assign W_op_sthio = W_iw_op == 45;
assign W_op_bgeu = W_iw_op == 46;
assign W_op_ldhio = W_iw_op == 47;
assign W_op_cmpltui = W_iw_op == 48;
assign W_op_initd = W_iw_op == 51;
assign W_op_orhi = W_iw_op == 52;
assign W_op_stwio = W_iw_op == 53;
assign W_op_bltu = W_iw_op == 54;
assign W_op_ldwio = W_iw_op == 55;
assign W_op_rdprs = W_iw_op == 56;
assign W_op_flushd = W_iw_op == 59;
assign W_op_xorhi = W_iw_op == 60;
assign W_op_rsv02 = W_iw_op == 2;
assign W_op_rsv09 = W_iw_op == 9;
assign W_op_rsv10 = W_iw_op == 10;
assign W_op_rsv17 = W_iw_op == 17;
assign W_op_rsv18 = W_iw_op == 18;
assign W_op_rsv25 = W_iw_op == 25;
assign W_op_rsv26 = W_iw_op == 26;
assign W_op_rsv33 = W_iw_op == 33;
assign W_op_rsv34 = W_iw_op == 34;
assign W_op_rsv41 = W_iw_op == 41;
assign W_op_rsv42 = W_iw_op == 42;
assign W_op_rsv49 = W_iw_op == 49;
assign W_op_rsv57 = W_iw_op == 57;
assign W_op_rsv61 = W_iw_op == 61;
assign W_op_rsv62 = W_iw_op == 62;
assign W_op_rsv63 = W_iw_op == 63;
assign W_op_eret = W_op_opx & (W_iw_opx == 1);
assign W_op_roli = W_op_opx & (W_iw_opx == 2);
assign W_op_rol = W_op_opx & (W_iw_opx == 3);
assign W_op_flushp = W_op_opx & (W_iw_opx == 4);
assign W_op_ret = W_op_opx & (W_iw_opx == 5);
assign W_op_nor = W_op_opx & (W_iw_opx == 6);
assign W_op_mulxuu = W_op_opx & (W_iw_opx == 7);
assign W_op_cmpge = W_op_opx & (W_iw_opx == 8);
assign W_op_bret = W_op_opx & (W_iw_opx == 9);
assign W_op_ror = W_op_opx & (W_iw_opx == 11);
assign W_op_flushi = W_op_opx & (W_iw_opx == 12);
assign W_op_jmp = W_op_opx & (W_iw_opx == 13);
assign W_op_and = W_op_opx & (W_iw_opx == 14);
assign W_op_cmplt = W_op_opx & (W_iw_opx == 16);
assign W_op_slli = W_op_opx & (W_iw_opx == 18);
assign W_op_sll = W_op_opx & (W_iw_opx == 19);
assign W_op_wrprs = W_op_opx & (W_iw_opx == 20);
assign W_op_or = W_op_opx & (W_iw_opx == 22);
assign W_op_mulxsu = W_op_opx & (W_iw_opx == 23);
assign W_op_cmpne = W_op_opx & (W_iw_opx == 24);
assign W_op_srli = W_op_opx & (W_iw_opx == 26);
assign W_op_srl = W_op_opx & (W_iw_opx == 27);
assign W_op_nextpc = W_op_opx & (W_iw_opx == 28);
assign W_op_callr = W_op_opx & (W_iw_opx == 29);
assign W_op_xor = W_op_opx & (W_iw_opx == 30);
assign W_op_mulxss = W_op_opx & (W_iw_opx == 31);
assign W_op_cmpeq = W_op_opx & (W_iw_opx == 32);
assign W_op_divu = W_op_opx & (W_iw_opx == 36);
assign W_op_div = W_op_opx & (W_iw_opx == 37);
assign W_op_rdctl = W_op_opx & (W_iw_opx == 38);
assign W_op_mul = W_op_opx & (W_iw_opx == 39);
assign W_op_cmpgeu = W_op_opx & (W_iw_opx == 40);
assign W_op_initi = W_op_opx & (W_iw_opx == 41);
assign W_op_trap = W_op_opx & (W_iw_opx == 45);
assign W_op_wrctl = W_op_opx & (W_iw_opx == 46);
assign W_op_cmpltu = W_op_opx & (W_iw_opx == 48);
assign W_op_add = W_op_opx & (W_iw_opx == 49);
assign W_op_break = W_op_opx & (W_iw_opx == 52);
assign W_op_hbreak = W_op_opx & (W_iw_opx == 53);
assign W_op_sync = W_op_opx & (W_iw_opx == 54);
assign W_op_sub = W_op_opx & (W_iw_opx == 57);
assign W_op_srai = W_op_opx & (W_iw_opx == 58);
assign W_op_sra = W_op_opx & (W_iw_opx == 59);
assign W_op_intr = W_op_opx & (W_iw_opx == 61);
assign W_op_crst = W_op_opx & (W_iw_opx == 62);
assign W_op_rsvx00 = W_op_opx & (W_iw_opx == 0);
assign W_op_rsvx10 = W_op_opx & (W_iw_opx == 10);
assign W_op_rsvx15 = W_op_opx & (W_iw_opx == 15);
assign W_op_rsvx17 = W_op_opx & (W_iw_opx == 17);
assign W_op_rsvx21 = W_op_opx & (W_iw_opx == 21);
assign W_op_rsvx25 = W_op_opx & (W_iw_opx == 25);
assign W_op_rsvx33 = W_op_opx & (W_iw_opx == 33);
assign W_op_rsvx34 = W_op_opx & (W_iw_opx == 34);
assign W_op_rsvx35 = W_op_opx & (W_iw_opx == 35);
assign W_op_rsvx42 = W_op_opx & (W_iw_opx == 42);
assign W_op_rsvx43 = W_op_opx & (W_iw_opx == 43);
assign W_op_rsvx44 = W_op_opx & (W_iw_opx == 44);
assign W_op_rsvx47 = W_op_opx & (W_iw_opx == 47);
assign W_op_rsvx50 = W_op_opx & (W_iw_opx == 50);
assign W_op_rsvx51 = W_op_opx & (W_iw_opx == 51);
assign W_op_rsvx55 = W_op_opx & (W_iw_opx == 55);
assign W_op_rsvx56 = W_op_opx & (W_iw_opx == 56);
assign W_op_rsvx60 = W_op_opx & (W_iw_opx == 60);
assign W_op_rsvx63 = W_op_opx & (W_iw_opx == 63);
assign W_op_opx = W_iw_op == 58;
assign W_op_custom = W_iw_op == 50;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_target_pcb <= 0;
else if (A_en)
A_target_pcb <= M_target_pcb;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_mem_baddr <= 0;
else if (A_en)
A_mem_baddr <= M_mem_baddr;
end
//Propagating 'X' data bits
assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered;
//Propagating 'X' data bits
assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered;
//Propagating 'X' data bits
assign M_bht_wr_data_filtered = M_bht_wr_data_unfiltered;
//Propagating 'X' data bits
assign M_bht_ptr_filtered = M_bht_ptr_unfiltered;
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign A_wr_data_unfiltered_0_is_x = ^(A_wr_data_unfiltered[0]) === 1'bx;
assign A_wr_data_filtered[0] = (A_wr_data_unfiltered_0_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[0];
assign A_wr_data_unfiltered_1_is_x = ^(A_wr_data_unfiltered[1]) === 1'bx;
assign A_wr_data_filtered[1] = (A_wr_data_unfiltered_1_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[1];
assign A_wr_data_unfiltered_2_is_x = ^(A_wr_data_unfiltered[2]) === 1'bx;
assign A_wr_data_filtered[2] = (A_wr_data_unfiltered_2_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[2];
assign A_wr_data_unfiltered_3_is_x = ^(A_wr_data_unfiltered[3]) === 1'bx;
assign A_wr_data_filtered[3] = (A_wr_data_unfiltered_3_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[3];
assign A_wr_data_unfiltered_4_is_x = ^(A_wr_data_unfiltered[4]) === 1'bx;
assign A_wr_data_filtered[4] = (A_wr_data_unfiltered_4_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[4];
assign A_wr_data_unfiltered_5_is_x = ^(A_wr_data_unfiltered[5]) === 1'bx;
assign A_wr_data_filtered[5] = (A_wr_data_unfiltered_5_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[5];
assign A_wr_data_unfiltered_6_is_x = ^(A_wr_data_unfiltered[6]) === 1'bx;
assign A_wr_data_filtered[6] = (A_wr_data_unfiltered_6_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[6];
assign A_wr_data_unfiltered_7_is_x = ^(A_wr_data_unfiltered[7]) === 1'bx;
assign A_wr_data_filtered[7] = (A_wr_data_unfiltered_7_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[7];
assign A_wr_data_unfiltered_8_is_x = ^(A_wr_data_unfiltered[8]) === 1'bx;
assign A_wr_data_filtered[8] = (A_wr_data_unfiltered_8_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[8];
assign A_wr_data_unfiltered_9_is_x = ^(A_wr_data_unfiltered[9]) === 1'bx;
assign A_wr_data_filtered[9] = (A_wr_data_unfiltered_9_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[9];
assign A_wr_data_unfiltered_10_is_x = ^(A_wr_data_unfiltered[10]) === 1'bx;
assign A_wr_data_filtered[10] = (A_wr_data_unfiltered_10_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[10];
assign A_wr_data_unfiltered_11_is_x = ^(A_wr_data_unfiltered[11]) === 1'bx;
assign A_wr_data_filtered[11] = (A_wr_data_unfiltered_11_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[11];
assign A_wr_data_unfiltered_12_is_x = ^(A_wr_data_unfiltered[12]) === 1'bx;
assign A_wr_data_filtered[12] = (A_wr_data_unfiltered_12_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[12];
assign A_wr_data_unfiltered_13_is_x = ^(A_wr_data_unfiltered[13]) === 1'bx;
assign A_wr_data_filtered[13] = (A_wr_data_unfiltered_13_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[13];
assign A_wr_data_unfiltered_14_is_x = ^(A_wr_data_unfiltered[14]) === 1'bx;
assign A_wr_data_filtered[14] = (A_wr_data_unfiltered_14_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[14];
assign A_wr_data_unfiltered_15_is_x = ^(A_wr_data_unfiltered[15]) === 1'bx;
assign A_wr_data_filtered[15] = (A_wr_data_unfiltered_15_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[15];
assign A_wr_data_unfiltered_16_is_x = ^(A_wr_data_unfiltered[16]) === 1'bx;
assign A_wr_data_filtered[16] = (A_wr_data_unfiltered_16_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[16];
assign A_wr_data_unfiltered_17_is_x = ^(A_wr_data_unfiltered[17]) === 1'bx;
assign A_wr_data_filtered[17] = (A_wr_data_unfiltered_17_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[17];
assign A_wr_data_unfiltered_18_is_x = ^(A_wr_data_unfiltered[18]) === 1'bx;
assign A_wr_data_filtered[18] = (A_wr_data_unfiltered_18_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[18];
assign A_wr_data_unfiltered_19_is_x = ^(A_wr_data_unfiltered[19]) === 1'bx;
assign A_wr_data_filtered[19] = (A_wr_data_unfiltered_19_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[19];
assign A_wr_data_unfiltered_20_is_x = ^(A_wr_data_unfiltered[20]) === 1'bx;
assign A_wr_data_filtered[20] = (A_wr_data_unfiltered_20_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[20];
assign A_wr_data_unfiltered_21_is_x = ^(A_wr_data_unfiltered[21]) === 1'bx;
assign A_wr_data_filtered[21] = (A_wr_data_unfiltered_21_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[21];
assign A_wr_data_unfiltered_22_is_x = ^(A_wr_data_unfiltered[22]) === 1'bx;
assign A_wr_data_filtered[22] = (A_wr_data_unfiltered_22_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[22];
assign A_wr_data_unfiltered_23_is_x = ^(A_wr_data_unfiltered[23]) === 1'bx;
assign A_wr_data_filtered[23] = (A_wr_data_unfiltered_23_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[23];
assign A_wr_data_unfiltered_24_is_x = ^(A_wr_data_unfiltered[24]) === 1'bx;
assign A_wr_data_filtered[24] = (A_wr_data_unfiltered_24_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[24];
assign A_wr_data_unfiltered_25_is_x = ^(A_wr_data_unfiltered[25]) === 1'bx;
assign A_wr_data_filtered[25] = (A_wr_data_unfiltered_25_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[25];
assign A_wr_data_unfiltered_26_is_x = ^(A_wr_data_unfiltered[26]) === 1'bx;
assign A_wr_data_filtered[26] = (A_wr_data_unfiltered_26_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[26];
assign A_wr_data_unfiltered_27_is_x = ^(A_wr_data_unfiltered[27]) === 1'bx;
assign A_wr_data_filtered[27] = (A_wr_data_unfiltered_27_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[27];
assign A_wr_data_unfiltered_28_is_x = ^(A_wr_data_unfiltered[28]) === 1'bx;
assign A_wr_data_filtered[28] = (A_wr_data_unfiltered_28_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[28];
assign A_wr_data_unfiltered_29_is_x = ^(A_wr_data_unfiltered[29]) === 1'bx;
assign A_wr_data_filtered[29] = (A_wr_data_unfiltered_29_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[29];
assign A_wr_data_unfiltered_30_is_x = ^(A_wr_data_unfiltered[30]) === 1'bx;
assign A_wr_data_filtered[30] = (A_wr_data_unfiltered_30_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[30];
assign A_wr_data_unfiltered_31_is_x = ^(A_wr_data_unfiltered[31]) === 1'bx;
assign A_wr_data_filtered[31] = (A_wr_data_unfiltered_31_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(W_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/W_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_wr_dst_reg)
if (^(W_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/W_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_pcb) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/W_pcb is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_iw) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/W_iw is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_en) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/A_en is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(M_valid) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/M_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_valid) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/A_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (A_valid & A_en & A_wr_dst_reg)
if (^(A_wr_data_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/A_wr_data_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_status_reg) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/A_status_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_estatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/A_estatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_bstatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/A_bstatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_readdatavalid) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/i_readdatavalid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: DE0_NANO_SOC_QSYS_nios2_qsys_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign A_wr_data_filtered = A_wr_data_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTN_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__SDFRTN_FUNCTIONAL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_pr/sky130_fd_sc_hdll__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_hdll__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTN_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31O_BLACKBOX_V
`define SKY130_FD_SC_HD__A31O_BLACKBOX_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a31o (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31O_BLACKBOX_V
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Data MMU top level ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of all DMMU blocks. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dmmu_top.v,v $
// Revision 1.1 2008/05/07 22:43:21 daughtry
// Initial Demo RTL check-in
//
// Revision 1.9 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.7.4.2 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.7.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.7 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.6 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.5 2002/02/14 15:34:02 simons
// Lapsus fixed.
//
// Revision 1.4 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/17 08:03:35 lampret
// *** empty log message ***
//
// Revision 1.2 2001/07/22 03:31:53 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
//
// Data MMU
//
module or1200_dmmu_top(
// Rst and clk
clk, rst,
// CPU i/f
dc_en, dmmu_en, supv, dcpu_adr_i, dcpu_cycstb_i, dcpu_we_i,
dcpu_tag_o, dcpu_err_o,
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// DC i/f
qmemdmmu_err_i, qmemdmmu_tag_i, qmemdmmu_adr_o, qmemdmmu_cycstb_o, qmemdmmu_ci_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// CPU I/F
//
input dc_en;
input dmmu_en;
input supv;
input [aw-1:0] dcpu_adr_i;
input dcpu_cycstb_i;
input dcpu_we_i;
output [3:0] dcpu_tag_o;
output dcpu_err_o;
//
// SPR access
//
input spr_cs;
input spr_write;
input [aw-1:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// DC I/F
//
input qmemdmmu_err_i;
input [3:0] qmemdmmu_tag_i;
output [aw-1:0] qmemdmmu_adr_o;
output qmemdmmu_cycstb_o;
output qmemdmmu_ci_o;
//
// Internal wires and regs
//
wire dtlb_spr_access;
wire [31:`OR1200_DMMU_PS] dtlb_ppn;
wire dtlb_hit;
wire dtlb_uwe;
wire dtlb_ure;
wire dtlb_swe;
wire dtlb_sre;
wire [31:0] dtlb_dat_o;
wire dtlb_en;
wire dtlb_ci;
wire fault;
wire miss;
`ifdef OR1200_NO_DMMU
`else
reg dtlb_done;
reg [31:`OR1200_DMMU_PS] dcpu_vpn_r;
`endif
//
// Implemented bits inside match and translate registers
//
// dtlbwYmrX: vpn 31-10 v 0
// dtlbwYtrX: ppn 31-10 swe 9 sre 8 uwe 7 ure 6
//
// dtlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 4 bits for protection
// 1 bit for cache inhibit
`ifdef OR1200_NO_DMMU
//
// Put all outputs in inactive state
//
assign spr_dat_o = 32'h00000000;
assign qmemdmmu_adr_o = dcpu_adr_i;
assign dcpu_tag_o = qmemdmmu_tag_i;
assign qmemdmmu_cycstb_o = dcpu_cycstb_i;
assign dcpu_err_o = qmemdmmu_err_i;
assign qmemdmmu_ci_o = `OR1200_DMMU_CI;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// DTLB SPR access
//
// 0A00 - 0AFF dtlbmr w0
// 0A00 - 0A3F dtlbmr w0 [63:0]
//
// 0B00 - 0BFF dtlbtr w0
// 0B00 - 0B3F dtlbtr w0 [63:0]
//
assign dtlb_spr_access = spr_cs;
//
// Tags:
//
// OR1200_DTAG_TE - TLB miss Exception
// OR1200_DTAG_PE - Page fault Exception
//
assign dcpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : qmemdmmu_tag_i;
//
// dcpu_err_o
//
assign dcpu_err_o = miss | fault | qmemdmmu_err_i;
//
// Assert dtlb_done one clock cycle after new address and dtlb_en must be active.
//
always @(posedge clk or posedge rst)
if (rst)
dtlb_done <= #1 1'b0;
else if (dtlb_en)
dtlb_done <= #1 dcpu_cycstb_i;
else
dtlb_done <= #1 1'b0;
//
// Cut transfer if something goes wrong with translation. Also delayed signals because of translation delay.
//
assign qmemdmmu_cycstb_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dtlb_done & dcpu_cycstb_i : ~(miss | fault) & dcpu_cycstb_i;
//assign qmemdmmu_cycstb_o = (dmmu_en) ? ~(miss | fault) & dcpu_cycstb_i : (miss | fault) ? 1'b0 : dcpu_cycstb_i;
//
// Cache Inhibit
//
assign qmemdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : `OR1200_DMMU_CI;
//
// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is expected to come
// one clock cycle after offset part.
//
always @(posedge clk or posedge rst)
if (rst)
dcpu_vpn_r <= #1 {31-`OR1200_DMMU_PS{1'b0}};
else
dcpu_vpn_r <= #1 dcpu_adr_i[31:`OR1200_DMMU_PS];
//
// Physical address is either translated virtual address or
// simply equal when DMMU is disabled
//
assign qmemdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : {dcpu_vpn_r, dcpu_adr_i[`OR1200_DMMU_PS-1:0]};
//assign qmemdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} : dcpu_adr_i;
//
// Output to SPRS unit
//
assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000;
//
// Page fault exception logic
//
assign fault = dtlb_done &
( (!dcpu_we_i & !supv & !dtlb_ure) // Load in user mode not enabled
|| (!dcpu_we_i & supv & !dtlb_sre) // Load in supv mode not enabled
|| (dcpu_we_i & !supv & !dtlb_uwe) // Store in user mode not enabled
|| (dcpu_we_i & supv & !dtlb_swe) ); // Store in supv mode not enabled
//
// TLB Miss exception logic
//
assign miss = dtlb_done & !dtlb_hit;
//
// DTLB Enable
//
assign dtlb_en = dmmu_en & dcpu_cycstb_i;
//
// Instantiation of DTLB
//
or1200_dmmu_tlb or1200_dmmu_tlb(
// Rst and clk
.clk(clk),
.rst(rst),
// I/F for translation
.tlb_en(dtlb_en),
.vaddr(dcpu_adr_i),
.hit(dtlb_hit),
.ppn(dtlb_ppn),
.uwe(dtlb_uwe),
.ure(dtlb_ure),
.swe(dtlb_swe),
.sre(dtlb_sre),
.ci(dtlb_ci),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// SPR access
.spr_cs(dtlb_spr_access),
.spr_write(spr_write),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_i),
.spr_dat_o(dtlb_dat_o)
);
`endif
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:30:32 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_0/zynq_design_1_auto_pc_0_stub.v
// Design : zynq_design_1_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module zynq_design_1_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready,
s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock,
s_axi_arcache, s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready,
s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
`include "../command_defines.v"
module op_lut_process_sm
#(parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter NUM_QUEUES = 8,
parameter NUM_QUEUES_WIDTH = log2(NUM_QUEUES),
parameter STAGE_NUM = 4,
parameter IOQ_STAGE_NUM = 8'hff)
(// --- interface to input fifo - fallthrough
input in_fifo_vld,
input [DATA_WIDTH-1:0] in_fifo_data,
input [CTRL_WIDTH-1:0] in_fifo_ctrl,
output reg in_fifo_rd_en,
// --- interface to eth_parser
input is_arp_pkt,
input is_ip_pkt,
input is_for_us,
input is_broadcast,
input eth_parser_info_vld,
input [NUM_QUEUES_WIDTH-1:0] mac_dst_port_num,
// --- interface to ip_arp
input [47:0] next_hop_mac,
input [NUM_QUEUES-1:0] output_port,
input arp_lookup_hit, // indicates if the next hop mac is correct
input lpm_lookup_hit, // indicates if the route to the destination IP was found
input arp_mac_vld, // indicates the lookup is done
// --- interface to op_lut_hdr_parser
input is_from_cpu,
input [NUM_QUEUES-1:0] to_cpu_output_port, // where to send pkts this pkt if it has to go to the CPU
input [NUM_QUEUES-1:0] from_cpu_output_port, // where to send this pkt if it is coming from the CPU
input is_from_cpu_vld,
input [NUM_QUEUES_WIDTH-1:0] input_port_num,
// --- interface to IP_checksum
input ip_checksum_vld,
input ip_checksum_is_good,
input ip_hdr_has_options,
input [15:0] ip_new_checksum, // new checksum assuming decremented TTL
input ip_ttl_is_good,
input [7:0] ip_new_ttl,
// --- input to dest_ip_filter
input dest_ip_hit,
input dest_ip_filter_vld,
// -- connected to all preprocess blocks
output reg rd_preprocess_info,
// --- interface to next module
output reg out_wr,
output reg [DATA_WIDTH-1:0] out_data,
output reg [CTRL_WIDTH-1:0] out_ctrl, // new checksum assuming decremented TTL
input out_rdy,
// --- interface to registers
output reg pkt_sent_from_cpu, // pulsed: we've sent a pkt from the CPU
output reg pkt_sent_to_cpu_options_ver, // pulsed: we've sent a pkt to the CPU coz it has options/bad version
output reg pkt_sent_to_cpu_bad_ttl, // pulsed: sent a pkt to the CPU coz the TTL is 1 or 0
output reg pkt_sent_to_cpu_dest_ip_hit, // pulsed: sent a pkt to the CPU coz it has hit in the destination ip filter list
output reg pkt_forwarded , // pulsed: forwarded pkt to the destination port
output reg pkt_dropped_checksum, // pulsed: dropped pkt coz bad checksum
output reg pkt_sent_to_cpu_non_ip, // pulsed: sent pkt to cpu coz it's not IP
output reg pkt_sent_to_cpu_arp_miss, // pulsed: sent pkt to cpu coz we didn't find arp entry for next hop ip
output reg pkt_sent_to_cpu_lpm_miss, // pulsed: sent pkt to cpu coz we didn't find lpm entry for destination ip
output reg pkt_dropped_wrong_dst_mac, // pulsed: dropped pkt not destined to us
input [47:0] mac_0, // address of rx queue 0
input [47:0] mac_1, // address of rx queue 1
input [47:0] mac_2, // address of rx queue 2
input [47:0] mac_3, // address of rx queue 3
// -- avalon interface to access ethernet rx buffer (Deepak)
input [ 9: 0] address,
output [ 31: 0] readdata,
input [ 3: 0] byteenable,
input chipselect,
input write,
input [ 31: 0] writedata,
//i/f b/w op_lut_process_sm.v and RX EXT FIFO
output reg [63:0] rx_ext_update_data,
input rx_ext_update_0_full,
output rx_ext_update_0_wrreq,
input rx_ext_update_1_full,
output rx_ext_update_1_wrreq,
input rx_ext_update_2_full,
output rx_ext_update_2_wrreq,
input rx_ext_update_3_full,
output rx_ext_update_3_wrreq,
input rx_ext_update_4_full,
output rx_ext_update_4_wrreq,
input rx_ext_update_5_full,
output rx_ext_update_5_wrreq,
input rx_ext_update_6_full,
output rx_ext_update_6_wrreq,
input rx_ext_update_7_full,
output rx_ext_update_7_wrreq,
output reg start_update,
output reg flush_ddr,
output reg check_terminate,
output reg flush_data,
output reg start_load,
output reg compute_system_reset,
//write interface to DDR (used by load data function)
output reg [63:0] dram_fifo_writedata,
output reg dram_fifo_write,
input dram_fifo_full,
input [7:0] proc_bit_mask,
// misc
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//------------------- Internal parameters -----------------------
localparam NUM_STATES = 10;
localparam WAIT_PREPROCESS_RDY = 1;
localparam MOVE_MODULE_HDRS = 2;
localparam SEND_SRC_MAC_LO = 4;
localparam SEND_IP_TTL = 8;
localparam SEND_IP_CHECKSUM = 16;
localparam MOVE_UDP = 32;
localparam INTERPRET_COMMAND = 64;
localparam LOAD_KEY_VALUE = 128;
localparam ACCUM_KEY_VALUE = 256;
localparam DROP_PKT = 512;
//---------------------- Wires and regs -------------------------
wire preprocess_vld;
reg [NUM_STATES-1:0] state;
reg [NUM_STATES-1:0] state_next;
reg [DATA_WIDTH-1:0] out_data_next;
reg [CTRL_WIDTH-1:0] out_ctrl_next;
reg out_wr_next;
reg ctrl_prev_is_0;
wire eop;
reg [47:0] src_mac_sel;
reg [NUM_QUEUES-1:0] dst_port;
reg [NUM_QUEUES-1:0] dst_port_next;
reg to_from_cpu;
reg to_from_cpu_next;
reg [63:0] rx_ext_update_data_next;
reg [7:0] rx_ext_update_wrreq, rx_ext_update_wrreq_next;
wire [7:0] rx_ext_update_full;
reg [1:0] command, command_next;
reg start_update_next;
reg flush_ddr_next;
reg start_load_next;
reg check_terminate_next;
reg flush_data_next;
wire is_safe_to_write_packet;
reg compute_system_reset_next;
reg [63:0] dram_fifo_writedata_next;
reg dram_fifo_write_next;
reg [4:0] rx_ext_fifo_sel, rx_ext_fifo_sel_next;
wire [4:0] next_external_fifo;
reg [31:0] packet_rcv /*synthesis noprune*/;
reg [31:0] packet_rcv_next /*synthesis noprune*/;
assign rx_ext_update_0_wrreq = rx_ext_update_wrreq[0];
assign rx_ext_update_1_wrreq = rx_ext_update_wrreq[1];
assign rx_ext_update_2_wrreq = rx_ext_update_wrreq[2];
assign rx_ext_update_3_wrreq = rx_ext_update_wrreq[3];
assign rx_ext_update_4_wrreq = rx_ext_update_wrreq[4];
assign rx_ext_update_5_wrreq = rx_ext_update_wrreq[5];
assign rx_ext_update_6_wrreq = rx_ext_update_wrreq[6];
assign rx_ext_update_7_wrreq = rx_ext_update_wrreq[7];
assign rx_ext_update_full[0] = rx_ext_update_0_full;
assign rx_ext_update_full[1] = rx_ext_update_1_full;
assign rx_ext_update_full[2] = rx_ext_update_2_full;
assign rx_ext_update_full[3] = rx_ext_update_3_full;
assign rx_ext_update_full[4] = rx_ext_update_4_full;
assign rx_ext_update_full[5] = rx_ext_update_5_full;
assign rx_ext_update_full[6] = rx_ext_update_6_full;
assign rx_ext_update_full[7] = rx_ext_update_7_full;
reg [3:0] ext_start;
always@(*) begin
case(proc_bit_mask) //ext_start represents bit position in proc_mask
8'h00: ext_start = 0;
8'h01: ext_start = 1;
8'h03: ext_start = 2;
8'h07: ext_start = 3;
8'h0f: ext_start = 4;
8'h1f: ext_start = 5;
8'h3f: ext_start = 6;
8'h7f: ext_start = 7;
8'hff: ext_start = 0; //Illegal - should never happen!
default: ext_start = 0;
endcase
end
localparam INVALID=0;
localparam LOAD=1;
localparam ACCUMULATE=2;
//-------------------------- Logic ------------------------------
assign preprocess_vld = eth_parser_info_vld & ip_checksum_vld;
assign eop = (ctrl_prev_is_0 && (in_fifo_ctrl!=0));
/* select the src mac address to write in the forwarded pkt */
always @(*) begin
case(output_port)
'h1: src_mac_sel = mac_0;
'h4: src_mac_sel = mac_1;
'h10: src_mac_sel = mac_2;
'h40: src_mac_sel = mac_3;
default: src_mac_sel = mac_0;
endcase // case(output_port)
end
/* Modify the packet's hdrs and add the module hdr */
always @(*) begin
rd_preprocess_info = 0;
state_next = state;
in_fifo_rd_en = 0;
pkt_dropped_wrong_dst_mac = 0;
rx_ext_update_data_next = rx_ext_update_data;
rx_ext_update_wrreq_next = 1'b0;
command_next = command;
//start_update_next = 1'b0;
start_update_next = start_update;
flush_ddr_next = 1'b0;
start_load_next = start_load;
check_terminate_next = 1'b0;
flush_data_next = 1'b0;
dram_fifo_writedata_next = dram_fifo_writedata;
dram_fifo_write_next = 1'b0;
compute_system_reset_next = 1'b0;
rx_ext_fifo_sel_next = rx_ext_fifo_sel;
packet_rcv_next = packet_rcv;
case(state)
WAIT_PREPROCESS_RDY: begin
if(preprocess_vld) begin
//if(is_for_us && is_ip_pkt && ip_checksum_is_good) begin
if(is_for_us && is_ip_pkt) begin //skip checksum for now
state_next = MOVE_MODULE_HDRS;
packet_rcv_next = packet_rcv+1;
end // else: !if(ip_hdr_has_options | !ip_ttl_is_good)
else begin
pkt_dropped_wrong_dst_mac = 1;
rd_preprocess_info = 1;
in_fifo_rd_en = 1;
state_next = DROP_PKT;
end
end
end // case: WAIT_PREPROCESS_RDY
MOVE_MODULE_HDRS: begin
if(in_fifo_vld) begin
in_fifo_rd_en = 1;
if(in_fifo_ctrl==0) begin
state_next = SEND_SRC_MAC_LO;
end
end
end // case: MOVE_MODULE_HDRS
SEND_SRC_MAC_LO: begin
if(in_fifo_vld) begin
in_fifo_rd_en = 1;
state_next = SEND_IP_TTL;
end
end
SEND_IP_TTL: begin
if(in_fifo_vld) begin
in_fifo_rd_en = 1;
state_next = SEND_IP_CHECKSUM;
end
end
SEND_IP_CHECKSUM: begin
if(in_fifo_vld) begin
in_fifo_rd_en = 1;
rd_preprocess_info = 1;
state_next = MOVE_UDP;
end
end
MOVE_UDP: begin
if(in_fifo_vld) begin
in_fifo_rd_en = 1;
state_next = INTERPRET_COMMAND;
end
end
INTERPRET_COMMAND: begin
if(in_fifo_vld) begin
in_fifo_rd_en = 1;
//interpret command here TODO
if(in_fifo_data[47:40]==`START_LOAD) begin
start_load_next = 1'b1;
state_next = DROP_PKT;
end
else if(in_fifo_data[47:40]==`LOAD_DATA) begin
state_next = LOAD_KEY_VALUE;
end
else if(in_fifo_data[47:40]==`END_LOAD) begin
start_load_next = 1'b0;
compute_system_reset_next = 1'b1; //reset the compute system
state_next = DROP_PKT;
end
else if(in_fifo_data[47:40]==`FPGA_TO_WORKER_PUT_REQUEST) begin //updates from FPGA workers to this FPGA
state_next = ACCUM_KEY_VALUE;
end
else if(in_fifo_data[47:40]==`WORKER_TO_FPGA_PUT_REQUEST) begin //updaets from CPU workers to this FPGA
state_next = ACCUM_KEY_VALUE;
end
else if(in_fifo_data[47:40]==`START_UPDATE) begin
start_update_next = 1'b1;
state_next = DROP_PKT;
end
else if(in_fifo_data[47:40]==`END_UPDATE) begin
start_update_next = 1'b0;
state_next = DROP_PKT;
end
else if(in_fifo_data[47:40]==`START_CHECK_TERMINATE) begin
check_terminate_next = 1'b1;
state_next = DROP_PKT;
end
else if(in_fifo_data[47:40]==`START_FLUSH_DATA) begin
flush_ddr_next = 1'b1;
state_next = DROP_PKT;
end
else begin
state_next = DROP_PKT;
end
end //end if(in_fifo)
end
LOAD_KEY_VALUE: begin //FIX THIS
if(in_fifo_vld && (!dram_fifo_full)) begin
dram_fifo_writedata_next = in_fifo_data[63:0];
dram_fifo_write_next = 1'b1;
state_next = (eop)?WAIT_PREPROCESS_RDY:LOAD_KEY_VALUE;
in_fifo_rd_en = (eop)?0:1;
end
end
ACCUM_KEY_VALUE: begin
if(in_fifo_vld) begin
//Make sure key!=0 AND val!=0
//If rx fifo is full, simply DROP packets - dont head-of-line
//block the packets
if((|in_fifo_data)&&(!rx_ext_update_full[rx_ext_fifo_sel])) begin
rx_ext_update_data_next = in_fifo_data[63:0];
rx_ext_update_wrreq_next[rx_ext_fifo_sel] = 1'b1;
rx_ext_fifo_sel_next = ((rx_ext_fifo_sel+1)==8)?ext_start:(rx_ext_fifo_sel+1);
end
in_fifo_rd_en = 1'b1;
if(eop) begin
state_next = WAIT_PREPROCESS_RDY;
end
else begin
//state_next = DROP_PKT;
state_next = ACCUM_KEY_VALUE;
end
end
end
DROP_PKT: begin
if(in_fifo_vld) begin
in_fifo_rd_en = 1;
if(eop) begin
state_next = WAIT_PREPROCESS_RDY;
end
end
end
endcase // case(state)
end // always @ (*)
always @(posedge clk or posedge reset) begin
if(reset) begin
state <= WAIT_PREPROCESS_RDY;
ctrl_prev_is_0 <= 0;
rx_ext_update_data <= 0;
rx_ext_update_wrreq <= 0;
start_update <= 0;
start_load <= 0;
check_terminate <= 0;
flush_ddr <= 0;
dram_fifo_writedata <= 0;
dram_fifo_write <= 0;
compute_system_reset <= 0;
rx_ext_fifo_sel <= 0;
packet_rcv <= 0;
end
else begin
state <= state_next;
ctrl_prev_is_0 <= in_fifo_rd_en ? (in_fifo_ctrl==0) : ctrl_prev_is_0;
rx_ext_update_data <= rx_ext_update_data_next;
rx_ext_update_wrreq <= rx_ext_update_wrreq_next;
start_update <= start_update_next;
start_load <= start_load_next;
check_terminate <= check_terminate_next;
flush_ddr <= flush_ddr_next;
dram_fifo_writedata <= dram_fifo_writedata_next;
dram_fifo_write <= dram_fifo_write_next;
compute_system_reset <= compute_system_reset_next;
rx_ext_fifo_sel <= (rx_ext_fifo_sel_next<ext_start)?ext_start:rx_ext_fifo_sel_next;
packet_rcv <= packet_rcv_next;
end // else: !if(reset)
end // always @ (posedge clk)
endmodule // op_lut_process_sm
|
// megafunction wizard: %ALTFP_CONVERT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_CONVERT
// ============================================================
// File Name: fp_convert.v
// Megafunction Name(s):
// ALTFP_CONVERT
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_convert CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" OPERATION="INT2FLOAT" ROUNDING="TO_NEAREST" WIDTH_DATA=32 WIDTH_EXP_INPUT=8 WIDTH_EXP_OUTPUT=8 WIDTH_INT=32 WIDTH_MAN_INPUT=23 WIDTH_MAN_OUTPUT=23 WIDTH_RESULT=32 clock dataa result
//VERSION_BEGIN 13.1 cbx_altbarrel_shift 2013:10:23:18:05:48:SJ cbx_altfp_convert 2013:10:23:18:05:48:SJ cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_altsyncram 2013:10:23:18:05:48:SJ cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_abs 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_compare 2013:10:23:18:05:48:SJ cbx_lpm_decode 2013:10:23:18:05:48:SJ cbx_lpm_divide 2013:10:23:18:05:48:SJ cbx_lpm_mux 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ cbx_stratixiii 2013:10:23:18:05:48:SJ cbx_stratixv 2013:10:23:18:05:48:SJ cbx_util_mgl 2013:10:23:18:05:48:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" PIPELINE=2 SHIFTDIR="LEFT" SHIFTTYPE="LOGICAL" WIDTH=32 WIDTHDIST=5 aclr clk_en clock data distance result
//VERSION_BEGIN 13.1 cbx_altbarrel_shift 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//synthesis_resources = reg 68
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_convert_altbarrel_shift_fof
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [31:0] data;
input [4:0] distance;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] dir_pipe;
reg [31:0] sbit_piper1d;
reg [31:0] sbit_piper2d;
reg sel_pipec3r1d;
reg sel_pipec4r1d;
wire [5:0] dir_w;
wire direction_w;
wire [15:0] pad_w;
wire [191:0] sbit_w;
wire [4:0] sel_w;
wire [159:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 2'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[4], dir_w[2]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 32'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[95:64];
// synopsys translate_off
initial
sbit_piper2d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper2d <= 32'b0;
else if (clk_en == 1'b1) sbit_piper2d <= smux_w[159:128];
// synopsys translate_off
initial
sel_pipec3r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec3r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec3r1d <= distance[3];
// synopsys translate_off
initial
sel_pipec4r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec4r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec4r1d <= distance[4];
assign
dir_w = {dir_pipe[1], dir_w[3], dir_pipe[0], dir_w[1:0], direction_w},
direction_w = 1'b0,
pad_w = {16{1'b0}},
result = sbit_w[191:160],
sbit_w = {sbit_piper2d, smux_w[127:96], sbit_piper1d, smux_w[63:0], data},
sel_w = {sel_pipec4r1d, sel_pipec3r1d, distance[2:0]},
smux_w = {((({32{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[143:128], pad_w[15:0]}) | ({32{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[159:144]})) | ({32{(~ sel_w[4])}} & sbit_w[159:128])), ((({32{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[119:96], pad_w[7:0]}) | ({32{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[127:104]})) | ({32{(~ sel_w[3])}} & sbit_w[127:96])), ((({32{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[91:64], pad_w[3:0]}) | ({32{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[95:68]})) | ({32{(~ sel_w[2])}} & sbit_w[95:64])), ((({32{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[61:32], pad_w[1:0]}) | ({32{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[63:34]})) | ({32{(~ sel_w[1])}} & sbit_w[63:32])), ((({32{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[30:0], pad_w[0]}) | ({32{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[31:1]})) | ({32{(~ sel_w[0])}} & sbit_w[31:0]))};
endmodule //fp_convert_altbarrel_shift_fof
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_convert_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule //fp_convert_altpriority_encoder_3e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_convert_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder15_q;
wire wire_altpriority_encoder15_zero;
wire [0:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
fp_convert_altpriority_encoder_3e8 altpriority_encoder15
(
.data(data[1:0]),
.q(wire_altpriority_encoder15_q),
.zero(wire_altpriority_encoder15_zero));
fp_convert_altpriority_encoder_3e8 altpriority_encoder16
(
.data(data[3:2]),
.q(wire_altpriority_encoder16_q),
.zero(wire_altpriority_encoder16_zero));
assign
q = {(~ wire_altpriority_encoder16_zero), ((wire_altpriority_encoder16_zero & wire_altpriority_encoder15_q) | ((~ wire_altpriority_encoder16_zero) & wire_altpriority_encoder16_q))},
zero = (wire_altpriority_encoder15_zero & wire_altpriority_encoder16_zero);
endmodule //fp_convert_altpriority_encoder_6e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_convert_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
wire [1:0] wire_altpriority_encoder14_q;
wire wire_altpriority_encoder14_zero;
fp_convert_altpriority_encoder_6e8 altpriority_encoder13
(
.data(data[3:0]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
fp_convert_altpriority_encoder_6e8 altpriority_encoder14
(
.data(data[7:4]),
.q(wire_altpriority_encoder14_q),
.zero(wire_altpriority_encoder14_zero));
assign
q = {(~ wire_altpriority_encoder14_zero), (({2{wire_altpriority_encoder14_zero}} & wire_altpriority_encoder13_q) | ({2{(~ wire_altpriority_encoder14_zero)}} & wire_altpriority_encoder14_q))},
zero = (wire_altpriority_encoder13_zero & wire_altpriority_encoder14_zero);
endmodule //fp_convert_altpriority_encoder_be8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_convert_altpriority_encoder_rf8
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
wire [2:0] wire_altpriority_encoder12_q;
wire wire_altpriority_encoder12_zero;
fp_convert_altpriority_encoder_be8 altpriority_encoder11
(
.data(data[7:0]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
fp_convert_altpriority_encoder_be8 altpriority_encoder12
(
.data(data[15:8]),
.q(wire_altpriority_encoder12_q),
.zero(wire_altpriority_encoder12_zero));
assign
q = {(~ wire_altpriority_encoder12_zero), (({3{wire_altpriority_encoder12_zero}} & wire_altpriority_encoder11_q) | ({3{(~ wire_altpriority_encoder12_zero)}} & wire_altpriority_encoder12_q))},
zero = (wire_altpriority_encoder11_zero & wire_altpriority_encoder12_zero);
endmodule //fp_convert_altpriority_encoder_rf8
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 13.1 cbx_altpriority_encoder 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_convert_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule //fp_convert_altpriority_encoder_3v7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_convert_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder21_q;
wire [0:0] wire_altpriority_encoder22_q;
wire wire_altpriority_encoder22_zero;
fp_convert_altpriority_encoder_3v7 altpriority_encoder21
(
.data(data[1:0]),
.q(wire_altpriority_encoder21_q));
fp_convert_altpriority_encoder_3e8 altpriority_encoder22
(
.data(data[3:2]),
.q(wire_altpriority_encoder22_q),
.zero(wire_altpriority_encoder22_zero));
assign
q = {(~ wire_altpriority_encoder22_zero), ((wire_altpriority_encoder22_zero & wire_altpriority_encoder21_q) | ((~ wire_altpriority_encoder22_zero) & wire_altpriority_encoder22_q))};
endmodule //fp_convert_altpriority_encoder_6v7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_convert_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder19_q;
wire [1:0] wire_altpriority_encoder20_q;
wire wire_altpriority_encoder20_zero;
fp_convert_altpriority_encoder_6v7 altpriority_encoder19
(
.data(data[3:0]),
.q(wire_altpriority_encoder19_q));
fp_convert_altpriority_encoder_6e8 altpriority_encoder20
(
.data(data[7:4]),
.q(wire_altpriority_encoder20_q),
.zero(wire_altpriority_encoder20_zero));
assign
q = {(~ wire_altpriority_encoder20_zero), (({2{wire_altpriority_encoder20_zero}} & wire_altpriority_encoder19_q) | ({2{(~ wire_altpriority_encoder20_zero)}} & wire_altpriority_encoder20_q))};
endmodule //fp_convert_altpriority_encoder_bv7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_convert_altpriority_encoder_r08
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder17_q;
wire [2:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
fp_convert_altpriority_encoder_bv7 altpriority_encoder17
(
.data(data[7:0]),
.q(wire_altpriority_encoder17_q));
fp_convert_altpriority_encoder_be8 altpriority_encoder18
(
.data(data[15:8]),
.q(wire_altpriority_encoder18_q),
.zero(wire_altpriority_encoder18_zero));
assign
q = {(~ wire_altpriority_encoder18_zero), (({3{wire_altpriority_encoder18_zero}} & wire_altpriority_encoder17_q) | ({3{(~ wire_altpriority_encoder18_zero)}} & wire_altpriority_encoder18_q))};
endmodule //fp_convert_altpriority_encoder_r08
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_convert_altpriority_encoder_qb6
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder10_q;
wire wire_altpriority_encoder10_zero;
wire [3:0] wire_altpriority_encoder9_q;
fp_convert_altpriority_encoder_rf8 altpriority_encoder10
(
.data(data[31:16]),
.q(wire_altpriority_encoder10_q),
.zero(wire_altpriority_encoder10_zero));
fp_convert_altpriority_encoder_r08 altpriority_encoder9
(
.data(data[15:0]),
.q(wire_altpriority_encoder9_q));
assign
q = {(~ wire_altpriority_encoder10_zero), (({4{wire_altpriority_encoder10_zero}} & wire_altpriority_encoder9_q) | ({4{(~ wire_altpriority_encoder10_zero)}} & wire_altpriority_encoder10_q))};
endmodule //fp_convert_altpriority_encoder_qb6
//synthesis_resources = lpm_add_sub 5 lpm_compare 1 reg 247
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_convert_altfp_convert_7qm
(
clock,
dataa,
result) ;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] wire_altbarrel_shift5_result;
wire [4:0] wire_altpriority_encoder2_q;
reg add_1_adder1_cout_reg;
reg [11:0] add_1_adder1_reg;
reg add_1_adder2_cout_reg;
reg [11:0] add_1_adder2_reg;
reg add_1_reg;
reg [7:0] exponent_bus_pre_reg;
reg [7:0] exponent_bus_pre_reg2;
reg [7:0] exponent_bus_pre_reg3;
reg [30:0] mag_int_a_reg;
reg [30:0] mag_int_a_reg2;
reg [23:0] mantissa_pre_round_reg;
reg [4:0] priority_encoder_reg;
reg [31:0] result_reg;
reg sign_int_a_reg1;
reg sign_int_a_reg2;
reg sign_int_a_reg3;
reg sign_int_a_reg4;
reg sign_int_a_reg5;
wire [30:0] wire_add_sub1_result;
wire [7:0] wire_add_sub3_result;
wire wire_add_sub6_cout;
wire [11:0] wire_add_sub6_result;
wire wire_add_sub7_cout;
wire [11:0] wire_add_sub7_result;
wire [7:0] wire_add_sub8_result;
wire wire_cmpr4_alb;
wire aclr;
wire [11:0] add_1_adder1_w;
wire [11:0] add_1_adder2_w;
wire [23:0] add_1_adder_w;
wire add_1_w;
wire [7:0] bias_value_w;
wire clk_en;
wire [7:0] const_bias_value_add_width_int_w;
wire [7:0] exceptions_value;
wire [7:0] exponent_bus;
wire [7:0] exponent_bus_pre;
wire [7:0] exponent_output_w;
wire [7:0] exponent_rounded;
wire [7:0] exponent_zero_w;
wire guard_bit_w;
wire [30:0] int_a;
wire [30:0] int_a_2s;
wire [30:0] invert_int_a;
wire [4:0] leading_zeroes;
wire [30:0] mag_int_a;
wire [22:0] mantissa_bus;
wire mantissa_overflow;
wire [23:0] mantissa_post_round;
wire [23:0] mantissa_pre_round;
wire [23:0] mantissa_rounded;
wire max_neg_value_selector;
wire [7:0] max_neg_value_w;
wire [7:0] minus_leading_zero;
wire [31:0] prio_mag_int_a;
wire [31:0] result_w;
wire round_bit_w;
wire [30:0] shifted_mag_int_a;
wire sign_bus;
wire sign_int_a;
wire [5:0] sticky_bit_bus;
wire [5:0] sticky_bit_or_w;
wire sticky_bit_w;
wire [2:0] zero_padding_w;
fp_convert_altbarrel_shift_fof altbarrel_shift5
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({1'b0, mag_int_a_reg2}),
.distance(leading_zeroes),
.result(wire_altbarrel_shift5_result));
fp_convert_altpriority_encoder_qb6 altpriority_encoder2
(
.data(prio_mag_int_a),
.q(wire_altpriority_encoder2_q));
// synopsys translate_off
initial
add_1_adder1_cout_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_1_adder1_cout_reg <= 1'b0;
else if (clk_en == 1'b1) add_1_adder1_cout_reg <= wire_add_sub6_cout;
// synopsys translate_off
initial
add_1_adder1_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_1_adder1_reg <= 12'b0;
else if (clk_en == 1'b1) add_1_adder1_reg <= wire_add_sub6_result;
// synopsys translate_off
initial
add_1_adder2_cout_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_1_adder2_cout_reg <= 1'b0;
else if (clk_en == 1'b1) add_1_adder2_cout_reg <= wire_add_sub7_cout;
// synopsys translate_off
initial
add_1_adder2_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_1_adder2_reg <= 12'b0;
else if (clk_en == 1'b1) add_1_adder2_reg <= wire_add_sub7_result;
// synopsys translate_off
initial
add_1_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_1_reg <= 1'b0;
else if (clk_en == 1'b1) add_1_reg <= add_1_w;
// synopsys translate_off
initial
exponent_bus_pre_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg <= 8'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg <= exponent_bus_pre_reg2;
// synopsys translate_off
initial
exponent_bus_pre_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg2 <= 8'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg2 <= exponent_bus_pre_reg3;
// synopsys translate_off
initial
exponent_bus_pre_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg3 <= 8'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg3 <= exponent_bus_pre;
// synopsys translate_off
initial
mag_int_a_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg <= 31'b0;
else if (clk_en == 1'b1) mag_int_a_reg <= mag_int_a;
// synopsys translate_off
initial
mag_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg2 <= 31'b0;
else if (clk_en == 1'b1) mag_int_a_reg2 <= mag_int_a_reg;
// synopsys translate_off
initial
mantissa_pre_round_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mantissa_pre_round_reg <= 24'b0;
else if (clk_en == 1'b1) mantissa_pre_round_reg <= mantissa_pre_round;
// synopsys translate_off
initial
priority_encoder_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) priority_encoder_reg <= 5'b0;
else if (clk_en == 1'b1) priority_encoder_reg <= wire_altpriority_encoder2_q;
// synopsys translate_off
initial
result_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) result_reg <= 32'b0;
else if (clk_en == 1'b1) result_reg <= result_w;
// synopsys translate_off
initial
sign_int_a_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg1 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg1 <= sign_int_a;
// synopsys translate_off
initial
sign_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg2 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg2 <= sign_int_a_reg1;
// synopsys translate_off
initial
sign_int_a_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg3 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg3 <= sign_int_a_reg2;
// synopsys translate_off
initial
sign_int_a_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg4 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg4 <= sign_int_a_reg3;
// synopsys translate_off
initial
sign_int_a_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg5 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg5 <= sign_int_a_reg4;
lpm_add_sub add_sub1
(
.cout(),
.dataa(invert_int_a),
.datab(31'b0000000000000000000000000000001),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "ADD",
add_sub1.lpm_width = 31,
add_sub1.lpm_type = "lpm_add_sub",
add_sub1.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub3
(
.cout(),
.dataa(const_bias_value_add_width_int_w),
.datab(minus_leading_zero),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "SUB",
add_sub3.lpm_width = 8,
add_sub3.lpm_type = "lpm_add_sub",
add_sub3.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub6
(
.cout(wire_add_sub6_cout),
.dataa(mantissa_pre_round[11:0]),
.datab(12'b000000000001),
.overflow(),
.result(wire_add_sub6_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub6.lpm_direction = "ADD",
add_sub6.lpm_width = 12,
add_sub6.lpm_type = "lpm_add_sub",
add_sub6.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub7
(
.cout(wire_add_sub7_cout),
.dataa(mantissa_pre_round[23:12]),
.datab(12'b000000000001),
.overflow(),
.result(wire_add_sub7_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub7.lpm_direction = "ADD",
add_sub7.lpm_width = 12,
add_sub7.lpm_type = "lpm_add_sub",
add_sub7.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub8
(
.cout(),
.dataa(exponent_bus_pre_reg),
.datab(8'b00000001),
.overflow(),
.result(wire_add_sub8_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub8.lpm_direction = "ADD",
add_sub8.lpm_width = 8,
add_sub8.lpm_type = "lpm_add_sub",
add_sub8.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_compare cmpr4
(
.aeb(),
.agb(),
.ageb(),
.alb(wire_cmpr4_alb),
.aleb(),
.aneb(),
.dataa(exponent_output_w),
.datab(bias_value_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr4.lpm_representation = "UNSIGNED",
cmpr4.lpm_width = 8,
cmpr4.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
add_1_adder1_w = add_1_adder1_reg,
add_1_adder2_w = (({12{(~ add_1_adder1_cout_reg)}} & mantissa_pre_round_reg[23:12]) | ({12{add_1_adder1_cout_reg}} & add_1_adder2_reg)),
add_1_adder_w = {add_1_adder2_w, add_1_adder1_w},
add_1_w = ((((~ guard_bit_w) & round_bit_w) & sticky_bit_w) | (guard_bit_w & round_bit_w)),
bias_value_w = 8'b01111111,
clk_en = 1'b1,
const_bias_value_add_width_int_w = 8'b10011101,
exceptions_value = (({8{(~ max_neg_value_selector)}} & exponent_zero_w) | ({8{max_neg_value_selector}} & max_neg_value_w)),
exponent_bus = exponent_rounded,
exponent_bus_pre = (({8{(~ wire_cmpr4_alb)}} & exponent_output_w) | ({8{wire_cmpr4_alb}} & exceptions_value)),
exponent_output_w = wire_add_sub3_result,
exponent_rounded = (({8{(~ mantissa_overflow)}} & exponent_bus_pre_reg) | ({8{mantissa_overflow}} & wire_add_sub8_result)),
exponent_zero_w = {8{1'b0}},
guard_bit_w = shifted_mag_int_a[7],
int_a = dataa[30:0],
int_a_2s = wire_add_sub1_result,
invert_int_a = (~ int_a),
leading_zeroes = (~ priority_encoder_reg),
mag_int_a = (({31{(~ sign_int_a)}} & int_a) | ({31{sign_int_a}} & int_a_2s)),
mantissa_bus = mantissa_rounded[22:0],
mantissa_overflow = ((add_1_reg & add_1_adder1_cout_reg) & add_1_adder2_cout_reg),
mantissa_post_round = add_1_adder_w,
mantissa_pre_round = shifted_mag_int_a[30:7],
mantissa_rounded = (({24{(~ add_1_reg)}} & mantissa_pre_round_reg) | ({24{add_1_reg}} & mantissa_post_round)),
max_neg_value_selector = (wire_cmpr4_alb & sign_int_a_reg2),
max_neg_value_w = 8'b10011110,
minus_leading_zero = {zero_padding_w, leading_zeroes},
prio_mag_int_a = {mag_int_a_reg, 1'b1},
result = result_reg,
result_w = {sign_bus, exponent_bus, mantissa_bus},
round_bit_w = shifted_mag_int_a[6],
shifted_mag_int_a = wire_altbarrel_shift5_result[30:0],
sign_bus = sign_int_a_reg5,
sign_int_a = dataa[31],
sticky_bit_bus = shifted_mag_int_a[5:0],
sticky_bit_or_w = {(sticky_bit_or_w[4] | sticky_bit_bus[5]), (sticky_bit_or_w[3] | sticky_bit_bus[4]), (sticky_bit_or_w[2] | sticky_bit_bus[3]), (sticky_bit_or_w[1] | sticky_bit_bus[2]), (sticky_bit_or_w[0] | sticky_bit_bus[1]), sticky_bit_bus[0]},
sticky_bit_w = sticky_bit_or_w[5],
zero_padding_w = {3{1'b0}};
endmodule //fp_convert_altfp_convert_7qm
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fp_convert (
clock,
dataa,
result);
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_convert_altfp_convert_7qm fp_convert_altfp_convert_7qm_component (
.clock (clock),
.dataa (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_convert"
// Retrieval info: CONSTANT: OPERATION STRING "INT2FLOAT"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_DATA NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_EXP_INPUT NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_EXP_OUTPUT NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_INT NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_MAN_INPUT NUMERIC "23"
// Retrieval info: CONSTANT: WIDTH_MAN_OUTPUT NUMERIC "23"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_convert.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_convert.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_convert.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_convert_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_convert_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_convert.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_convert.cmp TRUE TRUE
// Retrieval info: LIB_FILE: lpm
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2_LP_V
`define SKY130_FD_SC_LP__MUX2_LP_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_lp (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_lp (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2_LP_V
|
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03.07.2016 12:04:13
// Design Name:
// Module Name: pm0
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module pc_ctrl_pm0 #(
parameter DATA_W_IN_BYTES = 4,
parameter ADDR_W_IN_BITS = 32,
parameter DCADDR_LOW_BIT_W = 8
) (
input wire [31:0] accum_low_period,
input wire [15:0] pulse_per_second,
input wire ready_to_read ,
output reg [31:0] clk_freq = 32'd100000000,
output reg [31:0] clk_subsample = 32'd0,
output reg enable = 1'd1,
output reg use_one_pps_in = 1'd0,
input wire reg_bank_rd_start, // read start strobe
output wire reg_bank_rd_done, // read done strobe
input wire [DCADDR_LOW_BIT_W - 1:0] reg_bank_rd_addr, // read address bus
output reg [(DATA_W_IN_BYTES*8) - 1:0] reg_bank_rd_data=0,// read data bus
input wire reg_bank_wr_start, // write start strobe
output wire reg_bank_wr_done, // write done strobe
input wire [DCADDR_LOW_BIT_W - 1:0] reg_bank_wr_addr, // write address bus
input wire [(DATA_W_IN_BYTES*8) - 1:0] reg_bank_wr_data, // write data bus
input wire ACLK , // Clock source
input wire ARESETn // Reset source
);
//------------------------------------------------------------------------------
// Declare registers
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// In the basic bank these are completed straight away. Recall ....XX_start is
// a registered signal.
//------------------------------------------------------------------------------
assign reg_bank_wr_done = reg_bank_wr_start;
assign reg_bank_rd_done = reg_bank_rd_start;
//------------------------------------------------------------------------------
// Write logic
//------------------------------------------------------------------------------
always @(posedge ACLK) begin
if(!ARESETn) begin
clk_freq <= 32'd100000000;
clk_subsample <= 32'd0;
enable <= 1'd1;
use_one_pps_in <= 1'd0;
end else begin
if(reg_bank_wr_start) begin
case (reg_bank_wr_addr[DCADDR_LOW_BIT_W-1:2])
0 : begin
enable <= reg_bank_wr_data[0:0];
end
1 : begin
use_one_pps_in <= reg_bank_wr_data[0:0];
end
2 : begin
clk_freq <= reg_bank_wr_data[31:0];
end
3 : begin
clk_subsample <= reg_bank_wr_data[31:0];
end
endcase
end
end
end
//------------------------------------------------------------------------------
// READ logic
//------------------------------------------------------------------------------
always @(*) begin
// Zero the complete bus. We will set specific bits in the case
reg_bank_rd_data = 'd0;
case (reg_bank_rd_addr[DCADDR_LOW_BIT_W-1:2])
0 : begin
reg_bank_rd_data[0:0] = enable;
end
1 : begin
reg_bank_rd_data[0:0] = use_one_pps_in;
end
2 : begin
reg_bank_rd_data[31:0] = clk_freq;
end
3 : begin
reg_bank_rd_data[31:0] = clk_subsample;
end
4 : begin
reg_bank_rd_data[15:0] = pulse_per_second;
end
5 : begin
reg_bank_rd_data[31:0] = accum_low_period;
end
6 : begin
reg_bank_rd_data[0:0] = ready_to_read;
end
endcase
end
endmodule |
`timescale 1ns / 1ps
//-----------------------------------------------------------------------------
// Title : JTAG VPI virtual interface
// Project : KPU
//-----------------------------------------------------------------------------
// File : v_jtag_vpi.v
// Author : acorallo <[email protected]>
// Created : 03.06.2017
//-----------------------------------------------------------------------------
// Description :
// Execution stage implementation file for KPU
//-----------------------------------------------------------------------------
// This file is part of KPU.
// KPU is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// KPU is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY;
// without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with KPU. If not, see <http://www.gnu.org/licenses/>.
//
// Copyright (c) 2017 by Authors.
//------------------------------------------------------------------------------
// Derived from SoC/OpenRISC Development Interface
// Orignal Authors Author(s):
// Igor Mohor ([email protected])
// Gyorgy Jeney ([email protected])
// Nathan Yawn ([email protected])
//-----------------------------------------------------------------------------
`ifndef _v_jtag
`define _v_jtag
`define JP_PORT "4567"
`define TIMEOUT_COUNT 6'd20 // 1/2 of a TCK clock will be this many clk_o ticks. Must be less than 6 bits.
// `define JTAG_INPUT_FILE "tap_input_test_data.txt"
// `define JTAG_OUTPUT_FILE "tap_output_test_data.txt"
module v_jtag (
input wire clk_i,
output wire tms_o,
output wire tck_o,
output wire trst_o,
output wire tdi_o,
input wire tdo_i,
input wire tdo_oe_i
);
reg [4:0] memory;
reg [3:0] in_word_r;
reg [5:0] clk_count;
`ifdef JTAG_INPUT_FILE
reg [8:0] c;
integer t;
integer fd_in;
integer fd_out;
integer read_count;
`endif
// Handle commands from the upper level
initial begin
in_word_r = 5'b0;
memory = 5'b0;
`ifndef JTAG_INPUT_FILE
$jp_init(`JP_PORT);
`else
fd_in = $fopen(`JTAG_INPUT_FILE, "r");
if (fd_in == 0)
$display ("JTAG: stimulus file wasn't found");
fd_out = $fopen(`JTAG_OUTPUT_FILE, "w");
`endif
#5500; // Wait until reset is complete
while(1) begin
#1;
`ifndef JTAG_INPUT_FILE
$jp_in(memory); // This will not change memory if no command has been sent from jp
`else
memory[4] = 1;
if (fd_in)
read_count = $fscanf (fd_in, "%b", memory[3:0]);
if (!read_count) begin
c = $fgetc(fd_in);
if (c == "\#") begin
// Comment
while ($fgetc(fd_in) != "\n")
#0;
end
else if (c == "\S") begin
// Sleep
read_count = $fscanf (fd_in, "%b", t);
while(t) begin
t = t - 1;
#1;
end
end
end // if (!read_count)
#100; // jtag is supposed to be much slower then the cpu
`endif
if(memory[4]) begin
in_word_r = memory[3:0];
memory = memory & 4'b1111;
clk_count = 6'b000000; // Reset the timeout clock in case jp wants to wait for a timeout / half TCK period
end
end
end
// Send the output bit to the upper layer
`ifndef JTAG_INPUT_FILE
always @ (tdo_i)
$jp_out(tdo_i);
`else
always @ (posedge tck_o)
if (tdo_oe_i)
$fwrite(fd_out, "%b", tdo_i);
`endif
assign tck_o = in_word_r[0];
assign trst_o = in_word_r[1];
assign tdi_o = in_word_r[2];
assign tms_o = in_word_r[3];
// Send timeouts / wait periods to the upper layer
always @ (posedge clk_i) begin
if(clk_count < `TIMEOUT_COUNT) clk_count[5:0] = clk_count[5:0] + 1;
else if(clk_count == `TIMEOUT_COUNT) begin //
`ifndef JTAG_INPUT_FILE
$jp_wait_time(); //
`endif
clk_count[5:0] = clk_count[5:0] + 1;
end //
// else it's already timed out, don't do anything
end
endmodule
`endif
|
/**
* sseg_driver.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
/* seven segment display driver */
module sseg_driver(
input wire [ 3 : 0] digit, /* digit to show */
input wire [ 1 : 0] sel, /* place to show */
output reg [ 3 : 0] anode, /* common anode enable */
output reg [ 6 : 0] cathode /* cathode enable */
);
/* decode anode enable signal */
always @(sel) begin
case(sel)
2'b00: anode = 4'b1110;
2'b01: anode = 4'b1101;
2'b10: anode = 4'b1011;
2'b11: anode = 4'b0111;
endcase
end
/* decode digit into 7-segment driver output */
always @(digit) begin
case(digit) /* ABCDEFG */
4'h0: cathode = 7'b0000001;
4'h1: cathode = 7'b1001111;
4'h2: cathode = 7'b0010010;
4'h3: cathode = 7'b0000110;
4'h4: cathode = 7'b1001100;
4'h5: cathode = 7'b0100100;
4'h6: cathode = 7'b0100000;
4'h7: cathode = 7'b0001111;
4'h8: cathode = 7'b0000000;
4'h9: cathode = 7'b0000100;
4'ha: cathode = 7'b0001000;
4'hb: cathode = 7'b1100000;
4'hc: cathode = 7'b0110001;
4'hd: cathode = 7'b1000010;
4'he: cathode = 7'b0110000;
4'hf: cathode = 7'b0111000;
endcase
end
endmodule
/* vim: set ts=4 tw=79 syntax=verilog */
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO_64_TX_ENGINE.v
// Version : 2.4
//-- Description: 64 bit Local-Link Transmit Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module PIO_64_TX_ENGINE #(
// RX/TX interface data width
parameter C_DATA_WIDTH = 64,
parameter TCQ = 1,
// KEEP width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8
)(
input clk,
input rst_n,
// AXIS
input s_axis_tx_tready,
output reg [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output reg [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
output reg s_axis_tx_tlast,
output reg s_axis_tx_tvalid,
output tx_src_dsc,
input req_compl_i,
input req_compl_wd_i,
output reg compl_done_o,
input [2:0] req_tc_i,
input req_td_i,
input req_ep_i,
input [1:0] req_attr_i,
input [9:0] req_len_i,
input [15:0] req_rid_i,
input [7:0] req_tag_i,
input [7:0] req_be_i,
input [12:0] req_addr_i,
output [10:0] rd_addr_o,
output [3:0] rd_be_o,
input [31:0] rd_data_i,
input [15:0] completer_id_i,
input cfg_bus_mstr_enable_i
);
localparam PIO_64_CPLD_FMT_TYPE = 7'b10_01010;
localparam PIO_64_CPL_FMT_TYPE = 7'b00_01010;
localparam PIO_64_TX_RST_STATE = 1'b0;
localparam PIO_64_TX_CPLD_QW1 = 1'b1;
// Local registers
reg [11:0] byte_count;
reg [06:0] lower_addr;
reg req_compl_q;
reg req_compl_wd_q;
reg [0:0] state;
// Local wires
// Unused discontinue
assign tx_src_dsc = 1'b0;
/*
* Present address and byte enable to memory module
*/
assign rd_addr_o = req_addr_i[12:2];
assign rd_be_o = req_be_i[3:0];
/*
* Calculate byte count based on byte enable
*/
always @ (rd_be_o) begin
casex (rd_be_o[3:0])
4'b1xx1 : byte_count = 12'h004;
4'b01x1 : byte_count = 12'h003;
4'b1x10 : byte_count = 12'h003;
4'b0011 : byte_count = 12'h002;
4'b0110 : byte_count = 12'h002;
4'b1100 : byte_count = 12'h002;
4'b0001 : byte_count = 12'h001;
4'b0010 : byte_count = 12'h001;
4'b0100 : byte_count = 12'h001;
4'b1000 : byte_count = 12'h001;
4'b0000 : byte_count = 12'h001;
endcase
end
/*
* Calculate lower address based on byte enable
*/
always @ (rd_be_o or req_addr_i or req_compl_wd_q) begin
casex ({req_compl_wd_q, rd_be_o[3:0]})
5'b0_xxxx : lower_addr = 8'h0;
5'bx_0000 : lower_addr = {req_addr_i[6:2], 2'b00};
5'bx_xxx1 : lower_addr = {req_addr_i[6:2], 2'b00};
5'bx_xx10 : lower_addr = {req_addr_i[6:2], 2'b01};
5'bx_x100 : lower_addr = {req_addr_i[6:2], 2'b10};
5'bx_1000 : lower_addr = {req_addr_i[6:2], 2'b11};
endcase
end
always @ ( posedge clk ) begin
if (!rst_n ) begin
req_compl_q <= #TCQ 1'b0;
req_compl_wd_q <= #TCQ 1'b1;
end else begin
req_compl_q <= #TCQ req_compl_i;
req_compl_wd_q <= #TCQ req_compl_wd_i;
end
end
/*
* Generate Completion with 1 DW Payload
*/
always @ ( posedge clk ) begin
if (!rst_n ) begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b0;
s_axis_tx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
s_axis_tx_tkeep <= #TCQ {KEEP_WIDTH{1'b1}};
compl_done_o <= #TCQ 1'b0;
state <= #TCQ PIO_64_TX_RST_STATE;
end else begin
case ( state )
PIO_64_TX_RST_STATE : begin
if (req_compl_q) begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b1;
// Swap DWORDS for AXI
s_axis_tx_tdata <= #TCQ { // Bits
completer_id_i, // 16
{3'b0}, // 3
{1'b0}, // 1
byte_count, // 12
{1'b0}, // 1
(req_compl_wd_q ?
PIO_64_CPLD_FMT_TYPE :
PIO_64_CPL_FMT_TYPE), // 7
{1'b0}, // 1
req_tc_i, // 3
{4'b0}, // 4
req_td_i, // 1
req_ep_i, // 1
req_attr_i, // 2
{2'b0}, // 2
req_len_i // 10
};
s_axis_tx_tkeep <= #TCQ 8'hFF;
// Wait in this state if the PCIe core does not accept
// the first beat of the packet
if (s_axis_tx_tready)
state <= #TCQ PIO_64_TX_CPLD_QW1;
else
state <= #TCQ PIO_64_TX_RST_STATE;
end else begin
s_axis_tx_tlast <= #TCQ 1'b0;
s_axis_tx_tvalid <= #TCQ 1'b0;
s_axis_tx_tdata <= #TCQ 64'b0;
s_axis_tx_tkeep <= #TCQ 8'hFF;
compl_done_o <= #TCQ 1'b0;
state <= #TCQ PIO_64_TX_RST_STATE;
end
end
PIO_64_TX_CPLD_QW1 : begin
if (s_axis_tx_tready) begin
s_axis_tx_tlast <= #TCQ 1'b1;
s_axis_tx_tvalid <= #TCQ 1'b1;
// Swap DWORDS for AXI
s_axis_tx_tdata <= #TCQ { // Bits
rd_data_i, // 32
req_rid_i, // 16
req_tag_i, // 8
{1'b0}, // 1
lower_addr // 7
};
// Here we select if the packet has data or
// not. The strobe signal will mask data
// when it is not needed. No reason to change
// the data bus.
if (req_compl_wd_q)
s_axis_tx_tkeep <= #TCQ 8'hFF;
else
s_axis_tx_tkeep <= #TCQ 8'h0F;
compl_done_o <= #TCQ 1'b1;
state <= #TCQ PIO_64_TX_RST_STATE;
end else
state <= #TCQ PIO_64_TX_CPLD_QW1;
end
endcase
end
end
endmodule // PIO_64_TX_ENGINE
|
// lab9_soc.v
// Generated using ACDS version 14.0 200 at 2015.04.09.03:29:19
`timescale 1 ps / 1 ps
module lab9_soc (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
output wire [7:0] led_wire_export, // led_wire.export
output wire [12:0] sdram_wire_addr, // sdram_wire.addr
output wire [1:0] sdram_wire_ba, // .ba
output wire sdram_wire_cas_n, // .cas_n
output wire sdram_wire_cke, // .cke
output wire sdram_wire_cs_n, // .cs_n
inout wire [31:0] sdram_wire_dq, // .dq
output wire [3:0] sdram_wire_dqm, // .dqm
output wire sdram_wire_ras_n, // .ras_n
output wire sdram_wire_we_n, // .we_n
output wire sdram_clk_clk, // sdram_clk.clk
output wire [7:0] to_hw_port_export, // to_hw_port.export
output wire [1:0] to_hw_sig_export, // to_hw_sig.export
input wire [7:0] to_sw_port_export, // to_sw_port.export
input wire [1:0] to_sw_sig_export // to_sw_sig.export
);
wire sdram_pll_c0_clk; // sdram_pll:c0 -> [mm_interconnect_0:sdram_pll_c0_clk, rst_controller_001:clk, sdram:clk]
wire nios2_qsys_0_instruction_master_waitrequest; // mm_interconnect_0:nios2_qsys_0_instruction_master_waitrequest -> nios2_qsys_0:i_waitrequest
wire [28:0] nios2_qsys_0_instruction_master_address; // nios2_qsys_0:i_address -> mm_interconnect_0:nios2_qsys_0_instruction_master_address
wire nios2_qsys_0_instruction_master_read; // nios2_qsys_0:i_read -> mm_interconnect_0:nios2_qsys_0_instruction_master_read
wire [31:0] nios2_qsys_0_instruction_master_readdata; // mm_interconnect_0:nios2_qsys_0_instruction_master_readdata -> nios2_qsys_0:i_readdata
wire nios2_qsys_0_data_master_waitrequest; // mm_interconnect_0:nios2_qsys_0_data_master_waitrequest -> nios2_qsys_0:d_waitrequest
wire [31:0] nios2_qsys_0_data_master_writedata; // nios2_qsys_0:d_writedata -> mm_interconnect_0:nios2_qsys_0_data_master_writedata
wire [28:0] nios2_qsys_0_data_master_address; // nios2_qsys_0:d_address -> mm_interconnect_0:nios2_qsys_0_data_master_address
wire nios2_qsys_0_data_master_write; // nios2_qsys_0:d_write -> mm_interconnect_0:nios2_qsys_0_data_master_write
wire nios2_qsys_0_data_master_read; // nios2_qsys_0:d_read -> mm_interconnect_0:nios2_qsys_0_data_master_read
wire [31:0] nios2_qsys_0_data_master_readdata; // mm_interconnect_0:nios2_qsys_0_data_master_readdata -> nios2_qsys_0:d_readdata
wire nios2_qsys_0_data_master_debugaccess; // nios2_qsys_0:jtag_debug_module_debugaccess_to_roms -> mm_interconnect_0:nios2_qsys_0_data_master_debugaccess
wire [3:0] nios2_qsys_0_data_master_byteenable; // nios2_qsys_0:d_byteenable -> mm_interconnect_0:nios2_qsys_0_data_master_byteenable
wire mm_interconnect_0_nios2_qsys_0_jtag_debug_module_waitrequest; // nios2_qsys_0:jtag_debug_module_waitrequest -> mm_interconnect_0:nios2_qsys_0_jtag_debug_module_waitrequest
wire [31:0] mm_interconnect_0_nios2_qsys_0_jtag_debug_module_writedata; // mm_interconnect_0:nios2_qsys_0_jtag_debug_module_writedata -> nios2_qsys_0:jtag_debug_module_writedata
wire [8:0] mm_interconnect_0_nios2_qsys_0_jtag_debug_module_address; // mm_interconnect_0:nios2_qsys_0_jtag_debug_module_address -> nios2_qsys_0:jtag_debug_module_address
wire mm_interconnect_0_nios2_qsys_0_jtag_debug_module_write; // mm_interconnect_0:nios2_qsys_0_jtag_debug_module_write -> nios2_qsys_0:jtag_debug_module_write
wire mm_interconnect_0_nios2_qsys_0_jtag_debug_module_read; // mm_interconnect_0:nios2_qsys_0_jtag_debug_module_read -> nios2_qsys_0:jtag_debug_module_read
wire [31:0] mm_interconnect_0_nios2_qsys_0_jtag_debug_module_readdata; // nios2_qsys_0:jtag_debug_module_readdata -> mm_interconnect_0:nios2_qsys_0_jtag_debug_module_readdata
wire mm_interconnect_0_nios2_qsys_0_jtag_debug_module_debugaccess; // mm_interconnect_0:nios2_qsys_0_jtag_debug_module_debugaccess -> nios2_qsys_0:jtag_debug_module_debugaccess
wire [3:0] mm_interconnect_0_nios2_qsys_0_jtag_debug_module_byteenable; // mm_interconnect_0:nios2_qsys_0_jtag_debug_module_byteenable -> nios2_qsys_0:jtag_debug_module_byteenable
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire [1:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [3:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_sdram_s1_waitrequest; // sdram:za_waitrequest -> mm_interconnect_0:sdram_s1_waitrequest
wire [31:0] mm_interconnect_0_sdram_s1_writedata; // mm_interconnect_0:sdram_s1_writedata -> sdram:az_data
wire [24:0] mm_interconnect_0_sdram_s1_address; // mm_interconnect_0:sdram_s1_address -> sdram:az_addr
wire mm_interconnect_0_sdram_s1_chipselect; // mm_interconnect_0:sdram_s1_chipselect -> sdram:az_cs
wire mm_interconnect_0_sdram_s1_write; // mm_interconnect_0:sdram_s1_write -> sdram:az_wr_n
wire mm_interconnect_0_sdram_s1_read; // mm_interconnect_0:sdram_s1_read -> sdram:az_rd_n
wire [31:0] mm_interconnect_0_sdram_s1_readdata; // sdram:za_data -> mm_interconnect_0:sdram_s1_readdata
wire mm_interconnect_0_sdram_s1_readdatavalid; // sdram:za_valid -> mm_interconnect_0:sdram_s1_readdatavalid
wire [3:0] mm_interconnect_0_sdram_s1_byteenable; // mm_interconnect_0:sdram_s1_byteenable -> sdram:az_be_n
wire [31:0] mm_interconnect_0_sdram_pll_pll_slave_writedata; // mm_interconnect_0:sdram_pll_pll_slave_writedata -> sdram_pll:writedata
wire [1:0] mm_interconnect_0_sdram_pll_pll_slave_address; // mm_interconnect_0:sdram_pll_pll_slave_address -> sdram_pll:address
wire mm_interconnect_0_sdram_pll_pll_slave_write; // mm_interconnect_0:sdram_pll_pll_slave_write -> sdram_pll:write
wire mm_interconnect_0_sdram_pll_pll_slave_read; // mm_interconnect_0:sdram_pll_pll_slave_read -> sdram_pll:read
wire [31:0] mm_interconnect_0_sdram_pll_pll_slave_readdata; // sdram_pll:readdata -> mm_interconnect_0:sdram_pll_pll_slave_readdata
wire [0:0] mm_interconnect_0_sysid_qsys_0_control_slave_address; // mm_interconnect_0:sysid_qsys_0_control_slave_address -> sysid_qsys_0:address
wire [31:0] mm_interconnect_0_sysid_qsys_0_control_slave_readdata; // sysid_qsys_0:readdata -> mm_interconnect_0:sysid_qsys_0_control_slave_readdata
wire [31:0] mm_interconnect_0_led_s1_writedata; // mm_interconnect_0:led_s1_writedata -> led:writedata
wire [1:0] mm_interconnect_0_led_s1_address; // mm_interconnect_0:led_s1_address -> led:address
wire mm_interconnect_0_led_s1_chipselect; // mm_interconnect_0:led_s1_chipselect -> led:chipselect
wire mm_interconnect_0_led_s1_write; // mm_interconnect_0:led_s1_write -> led:write_n
wire [31:0] mm_interconnect_0_led_s1_readdata; // led:readdata -> mm_interconnect_0:led_s1_readdata
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest; // jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
wire [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
wire [0:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> jtag_uart_0:av_write_n
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> jtag_uart_0:av_read_n
wire [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata; // jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
wire [31:0] mm_interconnect_0_to_hw_port_s1_writedata; // mm_interconnect_0:to_hw_port_s1_writedata -> to_hw_port:writedata
wire [1:0] mm_interconnect_0_to_hw_port_s1_address; // mm_interconnect_0:to_hw_port_s1_address -> to_hw_port:address
wire mm_interconnect_0_to_hw_port_s1_chipselect; // mm_interconnect_0:to_hw_port_s1_chipselect -> to_hw_port:chipselect
wire mm_interconnect_0_to_hw_port_s1_write; // mm_interconnect_0:to_hw_port_s1_write -> to_hw_port:write_n
wire [31:0] mm_interconnect_0_to_hw_port_s1_readdata; // to_hw_port:readdata -> mm_interconnect_0:to_hw_port_s1_readdata
wire [31:0] mm_interconnect_0_to_hw_sig_s1_writedata; // mm_interconnect_0:to_hw_sig_s1_writedata -> to_hw_sig:writedata
wire [1:0] mm_interconnect_0_to_hw_sig_s1_address; // mm_interconnect_0:to_hw_sig_s1_address -> to_hw_sig:address
wire mm_interconnect_0_to_hw_sig_s1_chipselect; // mm_interconnect_0:to_hw_sig_s1_chipselect -> to_hw_sig:chipselect
wire mm_interconnect_0_to_hw_sig_s1_write; // mm_interconnect_0:to_hw_sig_s1_write -> to_hw_sig:write_n
wire [31:0] mm_interconnect_0_to_hw_sig_s1_readdata; // to_hw_sig:readdata -> mm_interconnect_0:to_hw_sig_s1_readdata
wire [1:0] mm_interconnect_0_to_sw_port_s1_address; // mm_interconnect_0:to_sw_port_s1_address -> to_sw_port:address
wire [31:0] mm_interconnect_0_to_sw_port_s1_readdata; // to_sw_port:readdata -> mm_interconnect_0:to_sw_port_s1_readdata
wire [1:0] mm_interconnect_0_to_sw_sig_s1_address; // mm_interconnect_0:to_sw_sig_s1_address -> to_sw_sig:address
wire [31:0] mm_interconnect_0_to_sw_sig_s1_readdata; // to_sw_sig:readdata -> mm_interconnect_0:to_sw_sig_s1_readdata
wire irq_mapper_receiver0_irq; // jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
wire [31:0] nios2_qsys_0_d_irq_irq; // irq_mapper:sender_irq -> nios2_qsys_0:d_irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [irq_mapper:reset, jtag_uart_0:rst_n, led:reset_n, mm_interconnect_0:nios2_qsys_0_reset_n_reset_bridge_in_reset_reset, nios2_qsys_0:reset_n, onchip_memory2_0:reset, rst_translator:in_reset, sdram_pll:reset, sysid_qsys_0:reset_n, to_hw_port:reset_n, to_hw_sig:reset_n, to_sw_port:reset_n, to_sw_sig:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [nios2_qsys_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [mm_interconnect_0:sdram_reset_reset_bridge_in_reset_reset, sdram:reset_n]
lab9_soc_nios2_qsys_0 nios2_qsys_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.d_address (nios2_qsys_0_data_master_address), // data_master.address
.d_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable
.d_read (nios2_qsys_0_data_master_read), // .read
.d_readdata (nios2_qsys_0_data_master_readdata), // .readdata
.d_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest
.d_write (nios2_qsys_0_data_master_write), // .write
.d_writedata (nios2_qsys_0_data_master_writedata), // .writedata
.jtag_debug_module_debugaccess_to_roms (nios2_qsys_0_data_master_debugaccess), // .debugaccess
.i_address (nios2_qsys_0_instruction_master_address), // instruction_master.address
.i_read (nios2_qsys_0_instruction_master_read), // .read
.i_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata
.i_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest
.d_irq (nios2_qsys_0_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (), // jtag_debug_module_reset.reset
.jtag_debug_module_address (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_address), // jtag_debug_module.address
.jtag_debug_module_byteenable (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_byteenable), // .byteenable
.jtag_debug_module_debugaccess (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_debugaccess), // .debugaccess
.jtag_debug_module_read (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_read), // .read
.jtag_debug_module_readdata (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_readdata), // .readdata
.jtag_debug_module_waitrequest (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_waitrequest), // .waitrequest
.jtag_debug_module_write (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_write), // .write
.jtag_debug_module_writedata (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
lab9_soc_onchip_memory2_0 onchip_memory2_0 (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
lab9_soc_led led (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_led_s1_address), // s1.address
.write_n (~mm_interconnect_0_led_s1_write), // .write_n
.writedata (mm_interconnect_0_led_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_led_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_led_s1_readdata), // .readdata
.out_port (led_wire_export) // external_connection.export
);
lab9_soc_sdram sdram (
.clk (sdram_pll_c0_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.az_addr (mm_interconnect_0_sdram_s1_address), // s1.address
.az_be_n (~mm_interconnect_0_sdram_s1_byteenable), // .byteenable_n
.az_cs (mm_interconnect_0_sdram_s1_chipselect), // .chipselect
.az_data (mm_interconnect_0_sdram_s1_writedata), // .writedata
.az_rd_n (~mm_interconnect_0_sdram_s1_read), // .read_n
.az_wr_n (~mm_interconnect_0_sdram_s1_write), // .write_n
.za_data (mm_interconnect_0_sdram_s1_readdata), // .readdata
.za_valid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.za_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.zs_addr (sdram_wire_addr), // wire.export
.zs_ba (sdram_wire_ba), // .export
.zs_cas_n (sdram_wire_cas_n), // .export
.zs_cke (sdram_wire_cke), // .export
.zs_cs_n (sdram_wire_cs_n), // .export
.zs_dq (sdram_wire_dq), // .export
.zs_dqm (sdram_wire_dqm), // .export
.zs_ras_n (sdram_wire_ras_n), // .export
.zs_we_n (sdram_wire_we_n) // .export
);
lab9_soc_sdram_pll sdram_pll (
.clk (clk_clk), // inclk_interface.clk
.reset (rst_controller_reset_out_reset), // inclk_interface_reset.reset
.read (mm_interconnect_0_sdram_pll_pll_slave_read), // pll_slave.read
.write (mm_interconnect_0_sdram_pll_pll_slave_write), // .write
.address (mm_interconnect_0_sdram_pll_pll_slave_address), // .address
.readdata (mm_interconnect_0_sdram_pll_pll_slave_readdata), // .readdata
.writedata (mm_interconnect_0_sdram_pll_pll_slave_writedata), // .writedata
.c0 (sdram_pll_c0_clk), // c0.clk
.c1 (sdram_clk_clk), // c1.clk
.areset (), // areset_conduit.export
.locked (), // locked_conduit.export
.phasedone () // phasedone_conduit.export
);
lab9_soc_sysid_qsys_0 sysid_qsys_0 (
.clock (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.readdata (mm_interconnect_0_sysid_qsys_0_control_slave_readdata), // control_slave.readdata
.address (mm_interconnect_0_sysid_qsys_0_control_slave_address) // .address
);
lab9_soc_jtag_uart_0 jtag_uart_0 (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver0_irq) // irq.irq
);
lab9_soc_led to_hw_port (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_to_hw_port_s1_address), // s1.address
.write_n (~mm_interconnect_0_to_hw_port_s1_write), // .write_n
.writedata (mm_interconnect_0_to_hw_port_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_to_hw_port_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_to_hw_port_s1_readdata), // .readdata
.out_port (to_hw_port_export) // external_connection.export
);
lab9_soc_to_hw_sig to_hw_sig (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_to_hw_sig_s1_address), // s1.address
.write_n (~mm_interconnect_0_to_hw_sig_s1_write), // .write_n
.writedata (mm_interconnect_0_to_hw_sig_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_to_hw_sig_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_to_hw_sig_s1_readdata), // .readdata
.out_port (to_hw_sig_export) // external_connection.export
);
lab9_soc_to_sw_port to_sw_port (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_to_sw_port_s1_address), // s1.address
.readdata (mm_interconnect_0_to_sw_port_s1_readdata), // .readdata
.in_port (to_sw_port_export) // external_connection.export
);
lab9_soc_to_sw_sig to_sw_sig (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_to_sw_sig_s1_address), // s1.address
.readdata (mm_interconnect_0_to_sw_sig_s1_readdata), // .readdata
.in_port (to_sw_sig_export) // external_connection.export
);
lab9_soc_mm_interconnect_0 mm_interconnect_0 (
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.sdram_pll_c0_clk (sdram_pll_c0_clk), // sdram_pll_c0.clk
.nios2_qsys_0_reset_n_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // nios2_qsys_0_reset_n_reset_bridge_in_reset.reset
.sdram_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // sdram_reset_reset_bridge_in_reset.reset
.nios2_qsys_0_data_master_address (nios2_qsys_0_data_master_address), // nios2_qsys_0_data_master.address
.nios2_qsys_0_data_master_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest
.nios2_qsys_0_data_master_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable
.nios2_qsys_0_data_master_read (nios2_qsys_0_data_master_read), // .read
.nios2_qsys_0_data_master_readdata (nios2_qsys_0_data_master_readdata), // .readdata
.nios2_qsys_0_data_master_write (nios2_qsys_0_data_master_write), // .write
.nios2_qsys_0_data_master_writedata (nios2_qsys_0_data_master_writedata), // .writedata
.nios2_qsys_0_data_master_debugaccess (nios2_qsys_0_data_master_debugaccess), // .debugaccess
.nios2_qsys_0_instruction_master_address (nios2_qsys_0_instruction_master_address), // nios2_qsys_0_instruction_master.address
.nios2_qsys_0_instruction_master_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest
.nios2_qsys_0_instruction_master_read (nios2_qsys_0_instruction_master_read), // .read
.nios2_qsys_0_instruction_master_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata
.jtag_uart_0_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address), // jtag_uart_0_avalon_jtag_slave.address
.jtag_uart_0_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write), // .write
.jtag_uart_0_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read), // .read
.jtag_uart_0_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_0_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_0_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_0_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect), // .chipselect
.led_s1_address (mm_interconnect_0_led_s1_address), // led_s1.address
.led_s1_write (mm_interconnect_0_led_s1_write), // .write
.led_s1_readdata (mm_interconnect_0_led_s1_readdata), // .readdata
.led_s1_writedata (mm_interconnect_0_led_s1_writedata), // .writedata
.led_s1_chipselect (mm_interconnect_0_led_s1_chipselect), // .chipselect
.nios2_qsys_0_jtag_debug_module_address (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_address), // nios2_qsys_0_jtag_debug_module.address
.nios2_qsys_0_jtag_debug_module_write (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_write), // .write
.nios2_qsys_0_jtag_debug_module_read (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_read), // .read
.nios2_qsys_0_jtag_debug_module_readdata (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_readdata), // .readdata
.nios2_qsys_0_jtag_debug_module_writedata (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_writedata), // .writedata
.nios2_qsys_0_jtag_debug_module_byteenable (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_byteenable), // .byteenable
.nios2_qsys_0_jtag_debug_module_waitrequest (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_waitrequest), // .waitrequest
.nios2_qsys_0_jtag_debug_module_debugaccess (mm_interconnect_0_nios2_qsys_0_jtag_debug_module_debugaccess), // .debugaccess
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.sdram_s1_address (mm_interconnect_0_sdram_s1_address), // sdram_s1.address
.sdram_s1_write (mm_interconnect_0_sdram_s1_write), // .write
.sdram_s1_read (mm_interconnect_0_sdram_s1_read), // .read
.sdram_s1_readdata (mm_interconnect_0_sdram_s1_readdata), // .readdata
.sdram_s1_writedata (mm_interconnect_0_sdram_s1_writedata), // .writedata
.sdram_s1_byteenable (mm_interconnect_0_sdram_s1_byteenable), // .byteenable
.sdram_s1_readdatavalid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.sdram_s1_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.sdram_s1_chipselect (mm_interconnect_0_sdram_s1_chipselect), // .chipselect
.sdram_pll_pll_slave_address (mm_interconnect_0_sdram_pll_pll_slave_address), // sdram_pll_pll_slave.address
.sdram_pll_pll_slave_write (mm_interconnect_0_sdram_pll_pll_slave_write), // .write
.sdram_pll_pll_slave_read (mm_interconnect_0_sdram_pll_pll_slave_read), // .read
.sdram_pll_pll_slave_readdata (mm_interconnect_0_sdram_pll_pll_slave_readdata), // .readdata
.sdram_pll_pll_slave_writedata (mm_interconnect_0_sdram_pll_pll_slave_writedata), // .writedata
.sysid_qsys_0_control_slave_address (mm_interconnect_0_sysid_qsys_0_control_slave_address), // sysid_qsys_0_control_slave.address
.sysid_qsys_0_control_slave_readdata (mm_interconnect_0_sysid_qsys_0_control_slave_readdata), // .readdata
.to_hw_port_s1_address (mm_interconnect_0_to_hw_port_s1_address), // to_hw_port_s1.address
.to_hw_port_s1_write (mm_interconnect_0_to_hw_port_s1_write), // .write
.to_hw_port_s1_readdata (mm_interconnect_0_to_hw_port_s1_readdata), // .readdata
.to_hw_port_s1_writedata (mm_interconnect_0_to_hw_port_s1_writedata), // .writedata
.to_hw_port_s1_chipselect (mm_interconnect_0_to_hw_port_s1_chipselect), // .chipselect
.to_hw_sig_s1_address (mm_interconnect_0_to_hw_sig_s1_address), // to_hw_sig_s1.address
.to_hw_sig_s1_write (mm_interconnect_0_to_hw_sig_s1_write), // .write
.to_hw_sig_s1_readdata (mm_interconnect_0_to_hw_sig_s1_readdata), // .readdata
.to_hw_sig_s1_writedata (mm_interconnect_0_to_hw_sig_s1_writedata), // .writedata
.to_hw_sig_s1_chipselect (mm_interconnect_0_to_hw_sig_s1_chipselect), // .chipselect
.to_sw_port_s1_address (mm_interconnect_0_to_sw_port_s1_address), // to_sw_port_s1.address
.to_sw_port_s1_readdata (mm_interconnect_0_to_sw_port_s1_readdata), // .readdata
.to_sw_sig_s1_address (mm_interconnect_0_to_sw_sig_s1_address), // to_sw_sig_s1.address
.to_sw_sig_s1_readdata (mm_interconnect_0_to_sw_sig_s1_readdata) // .readdata
);
lab9_soc_irq_mapper irq_mapper (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (nios2_qsys_0_d_irq_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (sdram_pll_c0_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
`timescale 1ns / 1ps
`include "Defintions.v"
`define LOOP1 8'd8
`define LOOP2 8'd5
module ROM
(
input wire[15:0] iAddress,
output reg [27:0] oInstruction
);
always @ ( iAddress )
begin
case (iAddress)
0: oInstruction = { `NOP ,24'd4000 };
1: oInstruction = { `STO , `R7,16'b0001 };
2: oInstruction = { `STO ,`R3,16'h1 };
3: oInstruction = { `STO, `R4,16'd1000 };
4: oInstruction = { `STO, `R5,16'd0 }; //j
//LOOP2:
5: oInstruction = { `LED ,8'b0,`R7,8'b0 };
6: oInstruction = { `STO ,`R1,16'h0 };
7: oInstruction = { `STO ,`R2,16'd5000 };
//LOOP1:
8: oInstruction = { `ADD ,`R1,`R1,`R3 };
9: oInstruction = { `BLE ,`LOOP1,`R1,`R2 };
10: oInstruction = { `ADD ,`R5,`R5,`R3 };
11: oInstruction = { `BLE ,`LOOP2,`R5,`R4 };
12: oInstruction = { `NOP ,24'd4000 };
13: oInstruction = { `SUB ,`R7,`R7,`R3 };
14: oInstruction = { `JMP , 8'd2,16'b0 };
default:
oInstruction = { `LED , 24'b10101010 }; //NOP
endcase
end
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_implication (clock, reset, enable, antecedent_expr, consequent_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input antecedent_expr, consequent_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_IMPLICATION";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/ovl_implication_logic.v"
`endif
`ifdef OVL_SVA
`include "./sva05/ovl_implication_logic.sv"
`endif
`ifdef OVL_PSL
`include "./psl05/assert_implication_psl_logic.v"
`else
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endmodule // ovl_implication
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:13:33 03/13/2014
// Design Name:
// Module Name: alu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alu(
A,
B,
ALU_operation,
shamt,
res,
zero,
overflow
);
input wire [31: 0] A, B;
input wire [ 3: 0] ALU_operation;
input wire [ 4: 0] shamt;
output reg [31: 0] res;
output wire zero;
output wire overflow;
wire [31: 0] res_and, res_or, res_add, res_sub, res_nor, res_slt,
res_xor, res_srl, res_sll, res_addu, res_subu, res_sltu, res_lh, res_sh, res_sra, res_lhu;
reg [31: 0] mask4 = 32'h0000_ffff;
wire [31: 0] mask;
wire [31: 0] res_tmp;
reg flag = 0;
//assign mask = B[1] ? 32'hffff_0000 : 32'h0000_ffff;
assign mask = res_add[1] ? 32'hffff_0000 : 32'h0000_ffff;
always @(ALU_operation) begin
flag <= res_add[1];
end
assign res_tmp = A & (flag?32'hffff_0000 : 32'h0000_ffff);
//assign res_tmp = A & mask;
always @(posedge ALU_operation[0]) mask4 = mask;
parameter one = 32'h00000001, zero_0 = 32'h00000000;
assign res_and = A & B;
assign res_or = A | B;
assign res_nor = ~(A | B);
assign res_xor = A ^ B;
assign res_srl = B >> shamt;
assign res_sll = B << shamt;
assign res_sra = $signed(B) >>> shamt;
assign res_add = $signed(A) + $signed(B);
assign res_sub = $signed(A) - $signed(B);
assign res_slt = ($signed(A) < $signed(B)) ? one : zero_0;
assign res_addu = $unsigned(A) + $unsigned(B);
assign res_subu = $unsigned(A) - $unsigned(B);
assign res_sltu = ($unsigned(A) < $unsigned(B)) ? one : zero_0;
assign res_lh = flag ? {{16{res_tmp[31]}}, res_tmp[31:16]} : {{16{res_tmp[15]}}, res_tmp[15:0]};
assign res_lhu = flag ? {16'h0, res_tmp[31:16]} : {16'h0, res_tmp[15:0]};
assign res_sh = mask4[0] ? (A&(~mask4) | {16'h0, B[15:0]}) : (A&(~mask4) | {B[15:0], 16'h0});
always @(*)
case (ALU_operation)
4'b0000: res = res_and;
4'b0001: res = res_or;
4'b0010: res = res_add;
4'b0110: res = res_sub;
4'b0100: res = res_nor;
4'b0111: res = res_slt;
4'b0011: res = res_xor;
4'b0101: res = res_srl;
4'b1000: res = res_sll;
4'b1001: res = res_addu;
4'b1010: res = res_subu;
4'b1011: res = res_sltu;
4'b1100: res = res_lh;
4'b1101: res = res_sh;
4'b1110: res = res_sra;
4'b1111: res = res_lhu;
default: res = res_add;
endcase
assign zero = (res == zero_0) ? 1'b1 : 1'b0;
endmodule
|
//`#start header` -- edit after this line, do not edit this line
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 04/23/2015 at 13:22
// Component: FIFO
module FIFO (
output drq,
input clk,
input [7:0] D,
input load
);
//`#start body` -- edit after this line, do not edit this line
cy_psoc3_dp #(.cy_dpconfig(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
8'hFF, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*CFG13-12: */
`SC_A0_SRC_PIN, `SC_SHIFT_SL, 1'h0,
1'h0, `SC_FIFO1_BUS, `SC_FIFO0_ALU,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
}
)) dp(
/* input */ .reset(1'b0),
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr(3'b0),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(load),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(),
/* output */ .f0_bus_stat(drq),
/* output */ .f0_blk_stat(),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat(),
/* input */ .ci(1'b0), // Carry in from previous stage
/* output */ .co(), // Carry out to next stage
/* input */ .sir(1'b0), // Shift in from right side
/* output */ .sor(), // Shift out to right side
/* input */ .sil(1'b0), // Shift in from left side
/* output */ .sol(), // Shift out to left side
/* input */ .msbi(1'b0), // MSB chain in
/* output */ .msbo(), // MSB chain out
/* input [01:00] */ .cei(2'b0), // Compare equal in from prev stage
/* output [01:00] */ .ceo(), // Compare equal out to next stage
/* input [01:00] */ .cli(2'b0), // Compare less than in from prv stage
/* output [01:00] */ .clo(), // Compare less than out to next stage
/* input [01:00] */ .zi(2'b0), // Zero detect in from previous stage
/* output [01:00] */ .zo(), // Zero detect out to next stage
/* input [01:00] */ .fi(2'b0), // 0xFF detect in from previous stage
/* output [01:00] */ .fo(), // 0xFF detect out to next stage
/* input [01:00] */ .capi(2'b0), // Software capture from previous stage
/* output [01:00] */ .capo(), // Software capture to next stage
/* input */ .cfbi(1'b0), // CRC Feedback in from previous stage
/* output */ .cfbo(), // CRC Feedback out to next stage
/* input [07:00] */ .pi(D), // Parallel data port
/* output [07:00] */ .po() // Parallel data port
);
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line
|
/*
Copyright (c) 2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for lfsr_prbs_gen
*/
module test_lfsr_prbs_gen_prbs31;
// Parameters
parameter LFSR_WIDTH = 31;
parameter LFSR_POLY = 31'h10000001;
parameter LFSR_INIT = {LFSR_WIDTH{1'b1}};
parameter LFSR_CONFIG = "FIBONACCI";
parameter REVERSE = 0;
parameter INVERT = 1;
parameter DATA_WIDTH = 8;
parameter STYLE = "AUTO";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg enable = 0;
// Outputs
wire [DATA_WIDTH-1:0] data_out;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
enable
);
$to_myhdl(
data_out
);
// dump file
$dumpfile("test_lfsr_prbs_gen_prbs31.lxt");
$dumpvars(0, test_lfsr_prbs_gen_prbs31);
end
lfsr_prbs_gen #(
.LFSR_WIDTH(LFSR_WIDTH),
.LFSR_POLY(LFSR_POLY),
.LFSR_INIT(LFSR_INIT),
.LFSR_CONFIG(LFSR_CONFIG),
.REVERSE(REVERSE),
.INVERT(INVERT),
.DATA_WIDTH(DATA_WIDTH),
.STYLE(STYLE)
)
UUT (
.clk(clk),
.rst(rst),
.enable(enable),
.data_out(data_out)
);
endmodule
|
`timescale 1ns / 1ps
`define SIMULATION
module peripheral_audio_TB;
reg clk;
reg rst;
reg reset;
reg start;
reg [15:0]d_in;
reg cs;
reg [1:0]addr;
reg rd;
reg wr;
wire [15:0]d_out;
reg micData;
peripheral_audio uut (.clk(clk) , .rst(reset) , .d_in(d_in) , .cs(cs) , .addr(addr) , .rd(rd) , .wr(wr), .d_out(d_out),.micData(micData) );
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
reg [20:0] i;
event reset_trigger;
reg d;
initial begin // Initialize Inputs
clk = 0; reset = 1; start = 0; d_in = 16'd0035; addr = 16'h0000; cs=1; rd=0; wr=1;
end
initial begin // Process for clk
#OFFSET;
forever
begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
end
initial begin // Reset the system, Start the image capture process
forever begin
@ (reset_trigger);
@ (posedge clk);
start = 0;
@ (posedge clk);
start = 1;
for(i=0; i<2; i=i+1) begin
@ (posedge clk);
end
start = 0;
#4 reset=0;
// stimulus here
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
//d_in = 16'h0001; //envio 1
addr = 16'h0000;
cs=1; rd=0; wr=1;
addr = 16'h0002;
cs=1; rd=1; wr=0;
for(i=0; i<40000; i=i+1) begin
@ (posedge clk);
end
//d_in = 16'h0002; //envio 1
addr = 16'h0000;
cs=1; rd=0; wr=1;
end
end
initial begin: TEST_CASE
$dumpfile("peripheral_audio_TB.vcd");
$dumpvars(-1, uut);
#10 -> reset_trigger;
#((PERIOD*DUTY_CYCLE)*200000) $finish;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: DE5QGen1x8If64.v
// Version:
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Altera Stratix V Avalong Streaming Interface to PCI
// Express module and the Terasic DE5 Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "functions.vh"
`include "riffa.vh"
`include "altera.vh"
`timescale 1ps / 1ps
module DE5QGen1x8If64_CLK
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 12,
// Number of PCIe Lanes
parameter C_NUM_LANES = 8,
// Settings from Quartus IP Library
parameter C_PCI_DATA_WIDTH = 64,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5
)
(
// ----------LEDs----------
output [7:0] LED,
// ----------PCIE----------
input PCIE_RESET_N,
input PCIE_REFCLK,
// ----------PCIE Serial RX----------
input [C_NUM_LANES-1:0] PCIE_RX_IN,
// ----------PCIE Serial TX----------
output [C_NUM_LANES-1:0] PCIE_TX_OUT,
// ----------Oscillators----------
input OSC_BANK3D_50MHZ
);
wire npor;
wire pin_perst;
// ----------TL Config interface----------
wire [3:0] tl_cfg_add;
wire [31:0] tl_cfg_ctl;
wire [52:0] tl_cfg_sts;
// ----------Rx/TX Interfaces----------
wire [0:0] rx_st_sop;
wire [0:0] rx_st_eop;
wire [0:0] rx_st_err;
wire [0:0] rx_st_valid;
wire rx_st_ready;
wire [C_PCI_DATA_WIDTH-1:0] rx_st_data;
wire [0:0] rx_st_empty;
wire [0:0] tx_st_sop;
wire [0:0] tx_st_eop;
wire [0:0] tx_st_err;
wire [0:0] tx_st_valid;
wire tx_st_ready;
wire [C_PCI_DATA_WIDTH-1:0] tx_st_data;
wire [0:0] tx_st_empty;
// ----------Clocks & Locks----------
wire pld_clk;
wire coreclkout_hip;
wire refclk;
wire pld_core_ready;
wire reset_status;
wire serdes_pll_locked;
wire riffa_5_clk;
wire riffa_10_clk;
wire riffa_25_clk;
wire riffa_50_clk;
wire riffa_75_clk;
wire riffa_100_clk;
wire riffa_125_clk;
wire riffa_150_clk;
wire riffa_175_clk;
wire riffa_200_clk;
wire riffa_225_clk;
wire riffa_250_clk;
// ----------Interrupt Interfaces----------
wire app_msi_req;
wire app_msi_ack;
// ----------Reconfiguration Controller signals----------
wire mgmt_clk_clk;
wire mgmt_rst_reset;
// ----------Reconfiguration Driver Signals----------
wire reconfig_xcvr_clk;
wire reconfig_xcvr_rst;
wire [7:0] rx_in;
wire [7:0] tx_out;
// ------------Status Interface------------
wire derr_cor_ext_rcv;
wire derr_cor_ext_rpl;
wire derr_rpl;
wire dlup;
wire dlup_exit;
wire ev128ns;
wire ev1us;
wire hotrst_exit;
wire [3:0] int_status;
wire l2_exit;
wire [3:0] lane_act;
wire [4:0] ltssmstate;
wire rx_par_err;
wire [1:0] tx_par_err;
wire cfg_par_err;
wire [7:0] ko_cpl_spc_header;
wire [11:0] ko_cpl_spc_data;
// ----------Clocks----------
assign pld_clk = coreclkout_hip;
assign mgmt_clk_clk = PCIE_REFCLK;
assign reconfig_xcvr_clk = PCIE_REFCLK;
assign refclk = PCIE_REFCLK;
assign pld_core_ready = serdes_pll_locked;
// ----------Resets----------
assign reconfig_xcvr_rst = 1'b0;
assign mgmt_rst_reset = 1'b0;
assign pin_perst = PCIE_RESET_N;
assign npor = PCIE_RESET_N;
// ----------LED's----------
assign LED[7:0] = 8'hff;
QSysDE5QGen1x8If64_CLK
pcie_system_inst
(
// Outputs
.rx_st_startofpacket (rx_st_sop[0:0]),
.rx_st_endofpacket (rx_st_eop[0:0]),
.rx_st_valid (rx_st_valid[0:0]),
.rx_st_data (rx_st_data[63:0]),
.tx_st_ready (tx_st_ready),
.pciehip_reset_status (reset_status),
.pciehip_serdes_pll_locked (serdes_pll_locked),
.pciecfg_tl_cfg_add (tl_cfg_add[3:0]),
.pciecfg_tl_cfg_ctl (tl_cfg_ctl[31:0]),
.pciecfg_tl_cfg_sts (tl_cfg_sts[52:0]),
.pciecoreclk_clk (coreclkout_hip),
.pcieserial_tx_out0 (PCIE_TX_OUT[0]),
.pcieserial_tx_out1 (PCIE_TX_OUT[1]),
.pcieserial_tx_out2 (PCIE_TX_OUT[2]),
.pcieserial_tx_out3 (PCIE_TX_OUT[3]),
.pcieserial_tx_out4 (PCIE_TX_OUT[4]),
.pcieserial_tx_out5 (PCIE_TX_OUT[5]),
.pcieserial_tx_out6 (PCIE_TX_OUT[6]),
.pcieserial_tx_out7 (PCIE_TX_OUT[7]),
.pciemsi_app_int_ack (app_int_ack),
.pciemsi_app_msi_ack (app_msi_ack),
.pciestat_derr_cor_ext_rcv (derr_cor_ext_rcv),
.pciestat_derr_cor_ext_rpl (derr_cor_ext_rpl),
.pciestat_derr_rpl (derr_rpl),
.pciestat_dlup (dlup),
.pciestat_dlup_exit (dlup_exit),
.pciestat_ev128ns (ev128ns),
.pciestat_ev1us (ev1us),
.pciestat_hotrst_exit (hotrst_exit),
.pciestat_int_status (int_status),
.pciestat_l2_exit (l2_exit),
.pciestat_lane_act (lane_act),
.pciestat_ltssmstate (ltssmstate),
.pciestat_rx_par_err (rx_par_err),
.pciestat_tx_par_err (tx_par_err),
.pciestat_cfg_par_err (cfg_par_err),
.pciestat_ko_cpl_spc_header (ko_cpl_spc_header),
.pciestat_ko_cpl_spc_data (ko_cpl_spc_data),
.riffa_5_clk (riffa_5_clk),
.riffa_10_clk (riffa_10_clk),
.riffa_25_clk (riffa_25_clk),
.riffa_50_clk (riffa_50_clk),
.riffa_75_clk (riffa_75_clk),
.riffa_100_clk (riffa_100_clk),
.riffa_125_clk (riffa_125_clk),
.riffa_150_clk (riffa_150_clk),
.riffa_175_clk (riffa_175_clk),
.riffa_200_clk (riffa_200_clk),
.riffa_225_clk (riffa_225_clk),
.riffa_250_clk (riffa_250_clk),
// Inputs
.rx_st_ready (rx_st_ready),
.tx_st_startofpacket (tx_st_sop[0:0]),
.tx_st_endofpacket (tx_st_eop[0:0]),
.tx_st_valid (tx_st_valid[0:0]),
.tx_st_data (tx_st_data[63:0]),
.pciehip_pld_core_ready (pld_core_ready),
.pcienpor_npor (npor),
.pcienpor_pin_perst (pin_perst),
.pcierefclk_clk (refclk),
.reconfigrefclk_clk (reconfig_xcvr_clk),
.pciepld_clk (pld_clk),
.reconfigrst_reset (reconfig_xcvr_rst),
.mgmtrst_reset (mgmt_rst_reset),
.mgmtclk_clk (mgmt_clk_clk),
.reconfigpldclk_clk (pld_clk),
.pcieserial_rx_in0 (PCIE_RX_IN[0]),
.pcieserial_rx_in1 (PCIE_RX_IN[1]),
.pcieserial_rx_in2 (PCIE_RX_IN[2]),
.pcieserial_rx_in3 (PCIE_RX_IN[3]),
.pcieserial_rx_in4 (PCIE_RX_IN[4]),
.pcieserial_rx_in5 (PCIE_RX_IN[5]),
.pcieserial_rx_in6 (PCIE_RX_IN[6]),
.pcieserial_rx_in7 (PCIE_RX_IN[7]),
.pciemsi_app_msi_req (app_msi_req),
.drvstat_derr_cor_ext_rcv (derr_cor_ext_rcv),
.drvstat_derr_cor_ext_rpl (derr_cor_ext_rpl),
.drvstat_derr_rpl (derr_rpl),
.drvstat_dlup (dlup),
.drvstat_dlup_exit (dlup_exit),
.drvstat_ev128ns (ev128ns),
.drvstat_ev1us (ev1us),
.drvstat_hotrst_exit (hotrst_exit),
.drvstat_int_status (int_status),
.drvstat_l2_exit (l2_exit),
.drvstat_lane_act (lane_act),
.drvstat_ltssmstate (ltssmstate),
.drvstat_rx_par_err (rx_par_err),
.drvstat_tx_par_err (tx_par_err),
.drvstat_cfg_par_err (cfg_par_err),
.drvstat_ko_cpl_spc_header (ko_cpl_spc_header),
.drvstat_ko_cpl_spc_data (ko_cpl_spc_data),
.pllrefclk_clk (OSC_BANK3D_50MHZ),
.pllrst_reset_n (1'b1));
// -------------------- END ALTERA IP INSTANTIATION --------------------
// -------------------- BEGIN RIFFA INSTANTAION --------------------
// RIFFA channel interface
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
wire chnl_reset;
wire chnl_clk;
wire riffa_reset;
wire riffa_clk;
assign riffa_reset = reset_status;
assign riffa_clk = pld_clk;
assign chnl_clk = pld_clk;
assign chnl_reset = rst_out;
riffa_wrapper_de5
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(
// Outputs
.RX_ST_READY (rx_st_ready),
.TX_ST_DATA (tx_st_data[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (tx_st_valid[0:0]),
.TX_ST_EOP (tx_st_eop[0:0]),
.TX_ST_SOP (tx_st_sop[0:0]),
.TX_ST_EMPTY (tx_st_empty[0:0]),
.APP_MSI_REQ (app_msi_req),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.RX_ST_DATA (rx_st_data[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (rx_st_eop[0:0]),
.RX_ST_SOP (rx_st_sop[0:0]),
.RX_ST_VALID (rx_st_valid[0:0]),
.RX_ST_EMPTY (rx_st_empty[0:0]),
.TX_ST_READY (tx_st_ready),
.TL_CFG_CTL (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
.TL_CFG_ADD (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
.TL_CFG_STS (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
.KO_CPL_SPC_HEADER (ko_cpl_spc_header[`SIG_KO_CPLH_W-1:0]),
.KO_CPL_SPC_DATA (ko_cpl_spc_data[`SIG_KO_CPLD_W-1:0]),
.APP_MSI_ACK (app_msi_ack),
.PLD_CLK (pld_clk),
.RESET_STATUS (reset_status),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
// -------------------- END RIFFA INSTANTAION --------------------
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_5mhz
(.CLK(riffa_5_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[0]),
.CHNL_RX(chnl_rx[0]),
.CHNL_RX_ACK(chnl_rx_ack[0]),
.CHNL_RX_LAST(chnl_rx_last[0]),
.CHNL_RX_LEN(chnl_rx_len[32*0 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*0 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*0 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[0]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[0]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[0]),
.CHNL_TX(chnl_tx[0]),
.CHNL_TX_ACK(chnl_tx_ack[0]),
.CHNL_TX_LAST(chnl_tx_last[0]),
.CHNL_TX_LEN(chnl_tx_len[32*0 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*0 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*0 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[0]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[0]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_10mhz
(.CLK(riffa_10_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[1]),
.CHNL_RX(chnl_rx[1]),
.CHNL_RX_ACK(chnl_rx_ack[1]),
.CHNL_RX_LAST(chnl_rx_last[1]),
.CHNL_RX_LEN(chnl_rx_len[32*1 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*1 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*1 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[1]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[1]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[1]),
.CHNL_TX(chnl_tx[1]),
.CHNL_TX_ACK(chnl_tx_ack[1]),
.CHNL_TX_LAST(chnl_tx_last[1]),
.CHNL_TX_LEN(chnl_tx_len[32*1 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*1 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*1 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[1]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[1]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_25mhz
(.CLK(riffa_25_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[2]),
.CHNL_RX(chnl_rx[2]),
.CHNL_RX_ACK(chnl_rx_ack[2]),
.CHNL_RX_LAST(chnl_rx_last[2]),
.CHNL_RX_LEN(chnl_rx_len[32*2 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*2 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*2 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[2]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[2]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[2]),
.CHNL_TX(chnl_tx[2]),
.CHNL_TX_ACK(chnl_tx_ack[2]),
.CHNL_TX_LAST(chnl_tx_last[2]),
.CHNL_TX_LEN(chnl_tx_len[32*2 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*2 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*2 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[2]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[2]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_50mhz
(.CLK(riffa_50_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[3]),
.CHNL_RX(chnl_rx[3]),
.CHNL_RX_ACK(chnl_rx_ack[3]),
.CHNL_RX_LAST(chnl_rx_last[3]),
.CHNL_RX_LEN(chnl_rx_len[32*3 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*3 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*3 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[3]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[3]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[3]),
.CHNL_TX(chnl_tx[3]),
.CHNL_TX_ACK(chnl_tx_ack[3]),
.CHNL_TX_LAST(chnl_tx_last[3]),
.CHNL_TX_LEN(chnl_tx_len[32*3 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*3 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*3 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[3]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[3]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_75mhz
(.CLK(riffa_75_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[4]),
.CHNL_RX(chnl_rx[4]),
.CHNL_RX_ACK(chnl_rx_ack[4]),
.CHNL_RX_LAST(chnl_rx_last[4]),
.CHNL_RX_LEN(chnl_rx_len[32*4 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*4 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*4 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[4]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[4]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[4]),
.CHNL_TX(chnl_tx[4]),
.CHNL_TX_ACK(chnl_tx_ack[4]),
.CHNL_TX_LAST(chnl_tx_last[4]),
.CHNL_TX_LEN(chnl_tx_len[32*4 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*4 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*4 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[4]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[4]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_100mhz
(.CLK(riffa_100_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[5]),
.CHNL_RX(chnl_rx[5]),
.CHNL_RX_ACK(chnl_rx_ack[5]),
.CHNL_RX_LAST(chnl_rx_last[5]),
.CHNL_RX_LEN(chnl_rx_len[32*5 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*5 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*5 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[5]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[5]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[5]),
.CHNL_TX(chnl_tx[5]),
.CHNL_TX_ACK(chnl_tx_ack[5]),
.CHNL_TX_LAST(chnl_tx_last[5]),
.CHNL_TX_LEN(chnl_tx_len[32*5 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*5 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*5 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[5]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[5]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_125mhz
(.CLK(riffa_125_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[6]),
.CHNL_RX(chnl_rx[6]),
.CHNL_RX_ACK(chnl_rx_ack[6]),
.CHNL_RX_LAST(chnl_rx_last[6]),
.CHNL_RX_LEN(chnl_rx_len[32*6 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*6 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*6 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[6]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[6]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[6]),
.CHNL_TX(chnl_tx[6]),
.CHNL_TX_ACK(chnl_tx_ack[6]),
.CHNL_TX_LAST(chnl_tx_last[6]),
.CHNL_TX_LEN(chnl_tx_len[32*6 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*6 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*6 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[6]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[6]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_150mhz
(.CLK(riffa_150_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[7]),
.CHNL_RX(chnl_rx[7]),
.CHNL_RX_ACK(chnl_rx_ack[7]),
.CHNL_RX_LAST(chnl_rx_last[7]),
.CHNL_RX_LEN(chnl_rx_len[32*7 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*7 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*7 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[7]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[7]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[7]),
.CHNL_TX(chnl_tx[7]),
.CHNL_TX_ACK(chnl_tx_ack[7]),
.CHNL_TX_LAST(chnl_tx_last[7]),
.CHNL_TX_LEN(chnl_tx_len[32*7 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*7 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*7 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[7]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[7]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_175mhz
(.CLK(riffa_175_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[8]),
.CHNL_RX(chnl_rx[8]),
.CHNL_RX_ACK(chnl_rx_ack[8]),
.CHNL_RX_LAST(chnl_rx_last[8]),
.CHNL_RX_LEN(chnl_rx_len[32*8 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*8 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*8 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[8]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[8]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[8]),
.CHNL_TX(chnl_tx[8]),
.CHNL_TX_ACK(chnl_tx_ack[8]),
.CHNL_TX_LAST(chnl_tx_last[8]),
.CHNL_TX_LEN(chnl_tx_len[32*8 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*8 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*8 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[8]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[8]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_200mhz
(.CLK(riffa_200_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[9]),
.CHNL_RX(chnl_rx[9]),
.CHNL_RX_ACK(chnl_rx_ack[9]),
.CHNL_RX_LAST(chnl_rx_last[9]),
.CHNL_RX_LEN(chnl_rx_len[32*9 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*9 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*9 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[9]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[9]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[9]),
.CHNL_TX(chnl_tx[9]),
.CHNL_TX_ACK(chnl_tx_ack[9]),
.CHNL_TX_LAST(chnl_tx_last[9]),
.CHNL_TX_LEN(chnl_tx_len[32*9 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*9 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*9 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[9]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[9]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_225mhz
(.CLK(riffa_225_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[10]),
.CHNL_RX(chnl_rx[10]),
.CHNL_RX_ACK(chnl_rx_ack[10]),
.CHNL_RX_LAST(chnl_rx_last[10]),
.CHNL_RX_LEN(chnl_rx_len[32*10 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*10 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*10 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[10]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[10]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[10]),
.CHNL_TX(chnl_tx[10]),
.CHNL_TX_ACK(chnl_tx_ack[10]),
.CHNL_TX_LAST(chnl_tx_last[10]),
.CHNL_TX_LEN(chnl_tx_len[32*10 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*10 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*10 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[10]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[10]));
chnl_tester
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
chnl_tester_250mhz
(.CLK(riffa_250_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[11]),
.CHNL_RX(chnl_rx[11]),
.CHNL_RX_ACK(chnl_rx_ack[11]),
.CHNL_RX_LAST(chnl_rx_last[11]),
.CHNL_RX_LEN(chnl_rx_len[32*11 +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*11 +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*11 +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[11]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[11]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[11]),
.CHNL_TX(chnl_tx[11]),
.CHNL_TX_ACK(chnl_tx_ack[11]),
.CHNL_TX_LAST(chnl_tx_last[11]),
.CHNL_TX_LEN(chnl_tx_len[32*11 +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*11 +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*11 +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[11]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[11]));
endmodule
|
//===============================================================================
// Copyright (c) 2014 by Cuong-TV
//===============================================================================
// Project : Video and Image Processing Design Using FPGAs
// File name: DE1_TOP.v
// Author : cuongtv
// Email : [email protected] - [email protected]
//===============================================================================
// Description
// Revision History :
// --------+----------------+-----------+--------------------------------+
// Ver | Author | Mod. Date | Changes Made: |
// --------+----------------+-----------+--------------------------------+
// V1.0 | Cuong-TV | 2014/11/1 | Initial Revision |
// --------+----------------+-----------+--------------------------------+
`timescale 1ns/1ns
module I2C_OV7670_Config
(
input [7:0] LUT_INDEX,
output reg [15:0] LUT_DATA
);
parameter Read_DATA = 0; //Read data LUT Address
parameter SET_OV7670 = 2; //SET_OV LUT Adderss
///////////////////// Config Data LUT //////////////////////////
always@(*)
begin
case(LUT_INDEX)
//Audio Config Data
//Read Data Index
Read_DATA + 0 : LUT_DATA = {8'h0A, 8'h76}; //PID
Read_DATA + 1 : LUT_DATA = {8'h0B, 8'h73}; //VER
// Read_DATA + 0 : LUT_DATA = {8'h1C, 8'h7F}; //MIDH
// Read_DATA + 1 : LUT_DATA = {8'h1D, 8'hA2}; //MIDL
// OV7670 : VGA RGB565
SET_OV7670 + 0 : LUT_DATA = 16'h3a00; //00:YUYV, 01:YVYU, 10:UYVY, 11:VYUY(CbYCrY)
SET_OV7670 + 1 : LUT_DATA = 16'h40d0; //RGB565, 00-FF, RGB565YUVҪģ
SET_OV7670 + 2 : LUT_DATA = 16'h1280; //VGA 04 :RGB565 (80:YUV 82:YUV,84:RGB,86:RGB)
SET_OV7670 + 3 : LUT_DATA = 16'h32b6; //HREF (80)
SET_OV7670 + 4 : LUT_DATA = 16'h1713; //HSTART
SET_OV7670 + 5 : LUT_DATA = 16'h1801; //HSTOP
SET_OV7670 + 6 : LUT_DATA = 16'h1902; //VSTART
SET_OV7670 + 7 : LUT_DATA = 16'h1a7a; //VSTOP
SET_OV7670 + 8 : LUT_DATA = 16'h030a; //VREF
SET_OV7670 + 9 : LUT_DATA = 16'h0c00; //DCW
SET_OV7670 + 10 : LUT_DATA = 16'h3e00; //
SET_OV7670 + 11 : LUT_DATA = 16'h7000; //
SET_OV7670 + 12 : LUT_DATA = 16'h7100; //
SET_OV7670 + 13 : LUT_DATA = 16'h7211; //
SET_OV7670 + 14 : LUT_DATA = 16'h7300; //
SET_OV7670 + 15 : LUT_DATA = 16'ha202; //
SET_OV7670 + 17 : LUT_DATA = 16'h7a20;
SET_OV7670 + 18 : LUT_DATA = 16'h7b1c;
SET_OV7670 + 19 : LUT_DATA = 16'h7c28;
SET_OV7670 + 20 : LUT_DATA = 16'h7d3c;
SET_OV7670 + 21 : LUT_DATA = 16'h7e55;
SET_OV7670 + 22 : LUT_DATA = 16'h7f68;
SET_OV7670 + 23 : LUT_DATA = 16'h8076;
SET_OV7670 + 24 : LUT_DATA = 16'h8180;
SET_OV7670 + 25 : LUT_DATA = 16'h8288;
SET_OV7670 + 26 : LUT_DATA = 16'h838f;
SET_OV7670 + 27 : LUT_DATA = 16'h8496;
SET_OV7670 + 28 : LUT_DATA = 16'h85a3;
SET_OV7670 + 29 : LUT_DATA = 16'h86af;
SET_OV7670 + 30 : LUT_DATA = 16'h87c4;
SET_OV7670 + 31 : LUT_DATA = 16'h88d7;
SET_OV7670 + 32 : LUT_DATA = 16'h89e8;
SET_OV7670 + 33 : LUT_DATA = 16'h13e0;
SET_OV7670 + 34 : LUT_DATA = 16'h0000;
SET_OV7670 + 35 : LUT_DATA = 16'h1000;
SET_OV7670 + 36 : LUT_DATA = 16'h0d00;
SET_OV7670 + 37 : LUT_DATA = 16'h1428; //
SET_OV7670 + 38 : LUT_DATA = 16'ha505;
SET_OV7670 + 39 : LUT_DATA = 16'hab07;
SET_OV7670 + 40 : LUT_DATA = 16'h2475;
SET_OV7670 + 41 : LUT_DATA = 16'h2563;
SET_OV7670 + 42 : LUT_DATA = 16'h26a5;
SET_OV7670 + 43 : LUT_DATA = 16'h9f78;
SET_OV7670 + 44 : LUT_DATA = 16'ha068;
SET_OV7670 + 45 : LUT_DATA = 16'ha103;
SET_OV7670 + 46 : LUT_DATA = 16'ha6df;
SET_OV7670 + 47 : LUT_DATA = 16'ha7df;
SET_OV7670 + 48 : LUT_DATA = 16'ha8f0;
SET_OV7670 + 49 : LUT_DATA = 16'ha990;
SET_OV7670 + 50 : LUT_DATA = 16'haa94;
SET_OV7670 + 51 : LUT_DATA = 16'h13ef; //
SET_OV7670 + 52 : LUT_DATA = 16'h0e61;
SET_OV7670 + 53 : LUT_DATA = 16'h0f4b;
SET_OV7670 + 54 : LUT_DATA = 16'h1602;
SET_OV7670 + 55 : LUT_DATA = 16'h1e20; //Ĭ01Bit[5]ˮƽBit[4]ֱ
SET_OV7670 + 56 : LUT_DATA = 16'h2102;
SET_OV7670 + 57 : LUT_DATA = 16'h2291;
SET_OV7670 + 58 : LUT_DATA = 16'h2907;
SET_OV7670 + 59 : LUT_DATA = 16'h330b;
SET_OV7670 + 60 : LUT_DATA = 16'h350b;
SET_OV7670 + 61 : LUT_DATA = 16'h371d;
SET_OV7670 + 62 : LUT_DATA = 16'h3871;
SET_OV7670 + 63 : LUT_DATA = 16'h392a;
SET_OV7670 + 64 : LUT_DATA = 16'h3c78;
SET_OV7670 + 65 : LUT_DATA = 16'h4d40;
SET_OV7670 + 66 : LUT_DATA = 16'h4e20;
SET_OV7670 + 67 : LUT_DATA = 16'h6900;
SET_OV7670 + 68 : LUT_DATA = 16'h6b00; //·PLLƵ0x0AرڲLDO0x00LDO
SET_OV7670 + 69 : LUT_DATA = 16'h7419;
SET_OV7670 + 70 : LUT_DATA = 16'h8d4f;
SET_OV7670 + 71 : LUT_DATA = 16'h8e00;
SET_OV7670 + 72 : LUT_DATA = 16'h8f00;
SET_OV7670 + 73 : LUT_DATA = 16'h9000;
SET_OV7670 + 74 : LUT_DATA = 16'h9100;
SET_OV7670 + 75 : LUT_DATA = 16'h9200;
SET_OV7670 + 76 : LUT_DATA = 16'h9600;
SET_OV7670 + 77 : LUT_DATA = 16'h9a80;
SET_OV7670 + 78 : LUT_DATA = 16'hb084;
SET_OV7670 + 79 : LUT_DATA = 16'hb10c;
SET_OV7670 + 80 : LUT_DATA = 16'hb20e;
SET_OV7670 + 81 : LUT_DATA = 16'hb382;
SET_OV7670 + 82 : LUT_DATA = 16'hb80a;
SET_OV7670 + 83 : LUT_DATA = 16'h4314;
SET_OV7670 + 84 : LUT_DATA = 16'h44f0;
SET_OV7670 + 85 : LUT_DATA = 16'h4534;
SET_OV7670 + 86 : LUT_DATA = 16'h4658;
SET_OV7670 + 87 : LUT_DATA = 16'h4728;
SET_OV7670 + 88 : LUT_DATA = 16'h483a;
SET_OV7670 + 89 : LUT_DATA = 16'h5988;
SET_OV7670 + 90 : LUT_DATA = 16'h5a88;
SET_OV7670 + 91 : LUT_DATA = 16'h5b44;
SET_OV7670 + 92 : LUT_DATA = 16'h5c67;
SET_OV7670 + 93 : LUT_DATA = 16'h5d49;
SET_OV7670 + 94 : LUT_DATA = 16'h5e0e;
SET_OV7670 + 95 : LUT_DATA = 16'h6404;
SET_OV7670 + 96 : LUT_DATA = 16'h6520;
SET_OV7670 + 97 : LUT_DATA = 16'h6605;
SET_OV7670 + 98 : LUT_DATA = 16'h9404;
SET_OV7670 + 99 : LUT_DATA = 16'h9508;
SET_OV7670 + 100 : LUT_DATA = 16'h6c0a;
SET_OV7670 + 101 : LUT_DATA = 16'h6d55;
SET_OV7670 + 102 : LUT_DATA = 16'h6e11;
SET_OV7670 + 103 : LUT_DATA = 16'h6f9f;
SET_OV7670 + 104 : LUT_DATA = 16'h6a40;
SET_OV7670 + 105 : LUT_DATA = 16'h0140;
SET_OV7670 + 106 : LUT_DATA = 16'h0240;
SET_OV7670 + 107 : LUT_DATA = 16'h13ef;//gia tri cu ef
SET_OV7670 + 108 : LUT_DATA = 16'h1500;
SET_OV7670 + 109 : LUT_DATA = 16'h4f80;
SET_OV7670 + 110 : LUT_DATA = 16'h5080;
SET_OV7670 + 111 : LUT_DATA = 16'h5100;
SET_OV7670 + 112 : LUT_DATA = 16'h5222;
SET_OV7670 + 113 : LUT_DATA = 16'h535e;
SET_OV7670 + 114 : LUT_DATA = 16'h5480;
SET_OV7670 + 115 : LUT_DATA = 16'h589e;
SET_OV7670 + 116 : LUT_DATA = 16'h4108;
SET_OV7670 + 117 : LUT_DATA = 16'h3f00;
SET_OV7670 + 118 : LUT_DATA = 16'h7505;
SET_OV7670 + 119 : LUT_DATA = 16'h76e1;
SET_OV7670 + 120 : LUT_DATA = 16'h4c00;
SET_OV7670 + 121 : LUT_DATA = 16'h7701;
SET_OV7670 + 122 : LUT_DATA = 16'h3dc2;
SET_OV7670 + 123 : LUT_DATA = 16'h4b09;
SET_OV7670 + 124 : LUT_DATA = 16'hc960;
SET_OV7670 + 125 : LUT_DATA = 16'h4138;
SET_OV7670 + 126 : LUT_DATA = 16'h5640;
SET_OV7670 + 127 : LUT_DATA = 16'h3411;
SET_OV7670 + 128 : LUT_DATA = 16'h3b02;// night mode : 82, day : 02
SET_OV7670 + 129 : LUT_DATA = 16'ha489;
SET_OV7670 + 130 : LUT_DATA = 16'h9600;
SET_OV7670 + 131 : LUT_DATA = 16'h9730;
SET_OV7670 + 132 : LUT_DATA = 16'h9820;
SET_OV7670 + 133 : LUT_DATA = 16'h9930;
SET_OV7670 + 134 : LUT_DATA = 16'h9a84;
SET_OV7670 + 135 : LUT_DATA = 16'h9b29;
SET_OV7670 + 136 : LUT_DATA = 16'h9c03;
SET_OV7670 + 137 : LUT_DATA = 16'h9d4c;
SET_OV7670 + 138 : LUT_DATA = 16'h9e3f;
SET_OV7670 + 139 : LUT_DATA = 16'h7804;
SET_OV7670 + 140 : LUT_DATA = 16'h7901;
SET_OV7670 + 141 : LUT_DATA = 16'hc8f0;
SET_OV7670 + 142 : LUT_DATA = 16'h790f;
SET_OV7670 + 143 : LUT_DATA = 16'hc800;
SET_OV7670 + 144 : LUT_DATA = 16'h7910;
SET_OV7670 + 145 : LUT_DATA = 16'hc87e;
SET_OV7670 + 146 : LUT_DATA = 16'h790a;
SET_OV7670 + 147 : LUT_DATA = 16'hc880;
SET_OV7670 + 148 : LUT_DATA = 16'h790b;
SET_OV7670 + 149 : LUT_DATA = 16'hc801;
SET_OV7670 + 150 : LUT_DATA = 16'h790c;
SET_OV7670 + 151 : LUT_DATA = 16'hc80f;
SET_OV7670 + 152 : LUT_DATA = 16'h790d;
SET_OV7670 + 153 : LUT_DATA = 16'hc820;
SET_OV7670 + 154 : LUT_DATA = 16'h7909;
SET_OV7670 + 155 : LUT_DATA = 16'hc880;
SET_OV7670 + 156 : LUT_DATA = 16'h7902;
SET_OV7670 + 157 : LUT_DATA = 16'hc8c0;
SET_OV7670 + 158 : LUT_DATA = 16'h7903;
SET_OV7670 + 159 : LUT_DATA = 16'hc840;
SET_OV7670 + 160 : LUT_DATA = 16'h7905;
SET_OV7670 + 161 : LUT_DATA = 16'hc830;
SET_OV7670 + 162 : LUT_DATA = 16'h7926;
SET_OV7670 + 163 : LUT_DATA = 16'h0903;
SET_OV7670 + 164 : LUT_DATA = 16'h3b42;// day 42, night A2
default : LUT_DATA = 0;
endcase
end
endmodule
|
`timescale 1ns / 1ps
// Documented Verilog UART
// Copyright (C) 2010 Timothy Goddard ([email protected])
// 2013 Aaron Dahlen
// Distributed under the MIT licence.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
//** INSTANTIATION ********************************************
//
// To instantiate this module copy this section to your main code...
//
// uart #(
// .baud_rate(baud_rate), // default is 9600
// .sys_clk_freq(sys_clk_freq) // default is 100000000
// )
// instance_name(
// .clk(clk), // The master clock for this module
// .rst(rst), // Synchronous reset
// .rx(rx), // Incoming serial line
// .tx(tx), // Outgoing serial line
// .transmit(transmit), // Signal to transmit
// .tx_byte(tx_byte), // Byte to transmit
// .received(received), // Indicated that a byte has been received
// .rx_byte(rx_byte), // Byte received
// .is_receiving(is_receiving), // Low when receive line is idle
// .is_transmitting(is_transmitting),// Low when transmit line is idle
// .recv_error(recv_error) // Indicates error in receiving packet.
// //.recv_state(recv_state), // for test bench
// //.tx_state(tx_state) // for test bench
// );
//
module uart(
input clk, // The master clock for this module
input rst, // Synchronous reset
input rx, // Incoming serial line
output tx, // Outgoing serial line
input transmit, // Assert to begin transmission
input [7:0] tx_byte, // Byte to transmit
output received, // Indicates that a byte has been received
output [7:0] rx_byte, // Byte received
output wire is_receiving, // Low when receive line is idle.
output wire is_transmitting,// Low when transmit line is idle.
output wire recv_error, // Indicates error in receiving packet.
output reg [3:0] rx_samples,
output reg [3:0] rx_sample_countdown
);
// The clock_divider is calculated using baud_rate and sys_clk_freq.
// To modify baud rate you can modify the defaults shown below or instantiate
// the module using the template shown in the INSTANTIATION section above.
// For aditional information about instantiation please see:
// http://www.sunburst-design.com/papers/CummingsHDLCON2002_Parameters_rev1_2.pdf
parameter baud_rate = 9600;
parameter sys_clk_freq = 12000000;
localparam one_baud_cnt = sys_clk_freq / (baud_rate);
localparam one_BC_div2 = one_baud_cnt / 2;
localparam one_BC_div8 = one_baud_cnt / 8;
localparam one_BC_mul3 = one_baud_cnt * 3;
localparam one_BC_mul16 = one_baud_cnt * 16;
localparam one_BC_23div8 = one_BC_div2 + one_BC_mul3 / 8;
localparam sys_clk_div = 8 * sys_clk_freq / (baud_rate);
//** SYMBOLIC STATE DECLARATIONS ******************************
localparam [2:0]
RX_IDLE = 3'd0,
RX_CHECK_START = 3'd1,
RX_SAMPLE_BITS = 3'd2,
RX_READ_BITS = 3'd3,
RX_CHECK_STOP = 3'd4,
RX_DELAY_RESTART = 3'd5,
RX_ERROR = 3'd6,
RX_RECEIVED = 3'd7;
localparam [1:0]
TX_IDLE = 2'd0,
TX_SENDING = 2'd1,
TX_DELAY_RESTART = 2'd2,
TX_RECOVER = 2'd3;
//** SIGNAL DECLARATIONS **************************************
reg [log2(one_baud_cnt * 16)-1:0] rx_clk;
reg [log2(one_baud_cnt)-1:0] tx_clk;
reg [2:0] recv_state = RX_IDLE;
reg [3:0] rx_bits_remaining;
reg [7:0] rx_data;
reg tx_out = 1'b1;
reg [1:0] tx_state = TX_IDLE;
reg [3:0] tx_bits_remaining;
reg [7:0] tx_data;
//** ASSIGN STATEMENTS ****************************************
assign received = recv_state == RX_RECEIVED;
assign recv_error = recv_state == RX_ERROR;
assign is_receiving = recv_state != RX_IDLE;
assign rx_byte = rx_data;
assign tx = tx_out;
assign is_transmitting = tx_state != TX_IDLE;
//** TASKS / FUNCTIONS ****************************************
function integer log2(input integer M);
integer i;
begin
log2 = 1;
for (i = 0; 2**i <= M; i = i + 1)
log2 = i + 1;
end endfunction
//** Body *****************************************************
always @(posedge clk) begin
if (rst) begin
recv_state <= RX_IDLE;
tx_state <= TX_IDLE;
end
// Countdown timers for the receiving and transmitting
// state machines are decremented.
if(rx_clk) begin
rx_clk <= rx_clk - 1'd1;
end
if(tx_clk) begin
tx_clk <= tx_clk - 1'd1;
end
//** Receive state machine ************************************
case (recv_state)
RX_IDLE: begin
// A low pulse on the receive line indicates the
// start of data.
if (!rx) begin
// Wait 1/2 of the bit period
rx_clk <= one_BC_div2;
recv_state <= RX_CHECK_START;
end
end
RX_CHECK_START: begin
if (!rx_clk) begin
// Check the pulse is still there
if (!rx) begin
// Pulse still there - good
// Wait the bit period plus 3/8 of the next
rx_clk <= one_BC_23div8;
rx_bits_remaining <= 8;
recv_state <= RX_SAMPLE_BITS;
rx_samples <= 0;
rx_sample_countdown <= 5;
end else begin
// Pulse lasted less than half the period -
// not a valid transmission.
recv_state <= RX_ERROR;
end
end
end
RX_SAMPLE_BITS: begin
// sample the rx line multiple times
if (!rx_clk) begin
if (rx) begin
rx_samples <= rx_samples + 1'd1;
end
rx_clk <= one_BC_div8;
rx_sample_countdown <= rx_sample_countdown -1'd1;
recv_state <= (rx_sample_countdown -1'd1) ? RX_SAMPLE_BITS : RX_READ_BITS;
end
end
RX_READ_BITS: begin
if (!rx_clk) begin
// Should be finished sampling the pulse here.
// Update and prep for next
if (rx_samples > 3) begin
rx_data <= {1'd1, rx_data[7:1]};
end else begin
rx_data <= {1'd0, rx_data[7:1]};
end
rx_clk <= one_BC_mul3 / 8;
rx_samples <= 0;
rx_sample_countdown <= 5;
rx_bits_remaining <= rx_bits_remaining - 1'd1;
if(rx_bits_remaining)begin
recv_state <= RX_SAMPLE_BITS;
end else begin
recv_state <= RX_CHECK_STOP;
rx_clk <= one_BC_div2;
end
end
end
RX_CHECK_STOP: begin
if (!rx_clk) begin
// Should resume half-way through the stop bit
// This should be high - if not, reject the
// transmission and signal an error.
recv_state <= rx ? RX_RECEIVED : RX_ERROR;
end
end
RX_ERROR: begin
// There was an error receiving.
// Raises the recv_error flag for one clock
// cycle while in this state and then waits
// 2 bit periods before accepting another
// transmission.
rx_clk <= sys_clk_div;
recv_state <= RX_DELAY_RESTART;
end
// why is this state needed? Why not go to idle and wait for next?
RX_DELAY_RESTART: begin
// Waits a set number of cycles before accepting
// another transmission.
recv_state <= rx_clk ? RX_DELAY_RESTART : RX_IDLE;
end
RX_RECEIVED: begin
// Successfully received a byte.
// Raises the received flag for one clock
// cycle while in this state.
recv_state <= RX_IDLE;
end
endcase
//** Transmit state machine ***********************************
case (tx_state)
TX_IDLE: begin
if (transmit) begin
// If the transmit flag is raised in the idle
// state, start transmitting the current content
// of the tx_byte input.
tx_data <= tx_byte;
// Send the initial, low pulse of 1 bit period
// to signal the start, followed by the data
// tx_clk_divider = clock_divide;
tx_clk <= one_baud_cnt;
tx_out <= 0;
tx_bits_remaining <= 8;
tx_state <= TX_SENDING;
end
end
TX_SENDING: begin
if (!tx_clk) begin
if (tx_bits_remaining) begin
tx_bits_remaining <= tx_bits_remaining - 1'd1;
tx_out = tx_data[0];//not sure how to replace these 2 with non-blocking
tx_data = {1'b0, tx_data[7:1]};
tx_clk <= one_baud_cnt;
tx_state <= TX_SENDING;
end else begin
// Set delay to send out 2 stop bits.
tx_out <= 1;
tx_clk <= one_BC_mul16;// tx_countdown = 16;
tx_state <= TX_DELAY_RESTART;
end
end
end
TX_DELAY_RESTART: begin
// Wait until tx_countdown reaches the end before
// we send another transmission. This covers the
// "stop bit" delay.
tx_state <= tx_clk ? TX_DELAY_RESTART : TX_RECOVER;// TX_IDLE;
end
TX_RECOVER: begin
// Wait unitil the transmit line is deactivated. This prevents repeated characters
tx_state <= transmit ? TX_RECOVER : TX_IDLE;
end
endcase
end
endmodule
|
module dec_5to32 (
input [4:0] a,
output [31:0] b);
and (b[0 ], ~a[4], ~a[3], ~a[2], ~a[1], ~a[0]);
and (b[1 ], ~a[4], ~a[3], ~a[2], ~a[1], a[0]);
and (b[2 ], ~a[4], ~a[3], ~a[2], a[1], ~a[0]);
and (b[3 ], ~a[4], ~a[3], ~a[2], a[1], a[0]);
and (b[4 ], ~a[4], ~a[3], a[2], ~a[1], ~a[0]);
and (b[5 ], ~a[4], ~a[3], a[2], ~a[1], a[0]);
and (b[6 ], ~a[4], ~a[3], a[2], a[1], ~a[0]);
and (b[7 ], ~a[4], ~a[3], a[2], a[1], a[0]);
and (b[8 ], ~a[4], a[3], ~a[2], ~a[1], ~a[0]);
and (b[9 ], ~a[4], a[3], ~a[2], ~a[1], a[0]);
and (b[10], ~a[4], a[3], ~a[2], a[1], ~a[0]);
and (b[11], ~a[4], a[3], ~a[2], a[1], a[0]);
and (b[12], ~a[4], a[3], a[2], ~a[1], ~a[0]);
and (b[13], ~a[4], a[3], a[2], ~a[1], a[0]);
and (b[14], ~a[4], a[3], a[2], a[1], ~a[0]);
and (b[15], ~a[4], a[3], a[2], a[1], a[0]);
and (b[16], a[4], ~a[3], ~a[2], ~a[1], ~a[0]);
and (b[17], a[4], ~a[3], ~a[2], ~a[1], a[0]);
and (b[18], a[4], ~a[3], ~a[2], a[1], ~a[0]);
and (b[19], a[4], ~a[3], ~a[2], a[1], a[0]);
and (b[20], a[4], ~a[3], a[2], ~a[1], ~a[0]);
and (b[21], a[4], ~a[3], a[2], ~a[1], a[0]);
and (b[22], a[4], ~a[3], a[2], a[1], ~a[0]);
and (b[23], a[4], ~a[3], a[2], a[1], a[0]);
and (b[24], a[4], a[3], ~a[2], ~a[1], ~a[0]);
and (b[25], a[4], a[3], ~a[2], ~a[1], a[0]);
and (b[26], a[4], a[3], ~a[2], a[1], ~a[0]);
and (b[27], a[4], a[3], ~a[2], a[1], a[0]);
and (b[28], a[4], a[3], a[2], ~a[1], ~a[0]);
and (b[29], a[4], a[3], a[2], ~a[1], a[0]);
and (b[30], a[4], a[3], a[2], a[1], ~a[0]);
and (b[31], a[4], a[3], a[2], a[1], a[0]);
endmodule
|
`timescale 1ns / 1ps
/*
* File : uart_rx.v
* Creator(s) : Grant Ayers ([email protected])
*
* Rev Date Initials Description of Change
* 1.0 26-May-2010 GEA Initial design.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* Recovers received data from the serial port with 16x clock over-sampling.
* 'data_ready' is a synchronous pulse indicator.
*
* Uses 8N1.
*/
module uart_rx(
input clock,
input reset,
input uart_tick_16x,
input RxD,
output reg [7:0] RxD_data = 0,
output data_ready
);
/* Synchronize incoming RxD */
reg [1:0] RxD_sync = 2'b11;
always @(posedge clock) begin
RxD_sync <= (uart_tick_16x) ? {RxD_sync[0], RxD} : RxD_sync;
end
/* Filter Input */
reg [1:0] RxD_cnt = 2'b00;
reg RxD_bit = 1'b1;
always @(posedge clock) begin
if (uart_tick_16x) begin
case (RxD_sync[1])
1'b0: RxD_cnt <= (RxD_cnt == 2'b11) ? RxD_cnt : RxD_cnt + 1'b1;
1'b1: RxD_cnt <= (RxD_cnt == 2'b00) ? RxD_cnt : RxD_cnt - 1'b1;
endcase
RxD_bit <= (RxD_cnt == 2'b11) ? 1'b0 : ((RxD_cnt == 2'b00) ? 1'b1 : RxD_bit);
end
else begin
RxD_cnt <= RxD_cnt;
RxD_bit <= RxD_bit;
end
end
/* State Definitions */
localparam [3:0] IDLE=0, BIT_0=1, BIT_1=2, BIT_2=3, BIT_3=4, BIT_4=5, BIT_5=6,
BIT_6=7, BIT_7=8, STOP=9;
reg [3:0] state = IDLE;
/* Next-bit spacing and clock locking */
reg clock_lock = 1'b0;
reg [3:0] bit_spacing = 4'b1110; // Enable quick jumping from IDLE to BIT_0 when line was idle.
always @(posedge clock) begin
if (uart_tick_16x) begin
if (~clock_lock) begin
clock_lock <= ~RxD_bit; // We lock on when we detect a filtered 0 from idle
end
else begin
clock_lock <= ((state == IDLE) && (RxD_bit == 1'b1)) ? 1'b0 : clock_lock;
end
bit_spacing <= (clock_lock) ? bit_spacing + 1'b1 : 4'b1110;
end
else begin
clock_lock <= clock_lock;
bit_spacing <= bit_spacing;
end
end
wire next_bit = (bit_spacing == 4'b1111);
/* State Machine */
always @(posedge clock) begin
if (reset) begin
state <= IDLE;
end
else if (uart_tick_16x) begin
case (state)
IDLE: state <= (next_bit & (RxD_bit == 1'b0)) ? BIT_0 : IDLE; // Start bit is 0
BIT_0: state <= (next_bit) ? BIT_1 : BIT_0;
BIT_1: state <= (next_bit) ? BIT_2 : BIT_1;
BIT_2: state <= (next_bit) ? BIT_3 : BIT_2;
BIT_3: state <= (next_bit) ? BIT_4 : BIT_3;
BIT_4: state <= (next_bit) ? BIT_5 : BIT_4;
BIT_5: state <= (next_bit) ? BIT_6 : BIT_5;
BIT_6: state <= (next_bit) ? BIT_7 : BIT_6;
BIT_7: state <= (next_bit) ? STOP : BIT_7;
STOP: state <= (next_bit) ? IDLE : STOP;
default: state <= 4'bxxxx;
endcase
end
else state <= state;
end
/* Shift Register to Collect Rx bits as they come */
wire capture = (uart_tick_16x & next_bit & (state!=IDLE) & (state!=STOP));
always @(posedge clock) begin
RxD_data <= (capture) ? {RxD_bit, RxD_data[7:1]} : RxD_data[7:0];
end
assign data_ready = (uart_tick_16x & next_bit & (state==STOP));
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:18:55 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_3/bram_1024_3_sim_netlist.v
// Design : bram_1024_3
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "bram_1024_3,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module bram_1024_3
(clka,
ena,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [9:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [19:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [19:0]douta;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [19:0]NLW_U0_doutb_UNCONNECTED;
wire [9:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [9:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [19:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "10" *)
(* C_ADDRB_WIDTH = "10" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.74095 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "bram_1024_3.mem" *)
(* C_INIT_FILE_NAME = "bram_1024_3.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1024" *)
(* C_READ_DEPTH_B = "1024" *)
(* C_READ_WIDTH_A = "20" *)
(* C_READ_WIDTH_B = "20" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1024" *)
(* C_WRITE_DEPTH_B = "1024" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "20" *)
(* C_WRITE_WIDTH_B = "20" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
bram_1024_3_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[19:0]),
.eccpipece(1'b0),
.ena(ena),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[9:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[9:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[19:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bram_1024_3_blk_mem_gen_generic_cstr
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_1024_3_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bram_1024_3_blk_mem_gen_prim_width
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_1024_3_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bram_1024_3_blk_mem_gen_prim_wrapper_init
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h000001000000001C0000001800000014000000100000000C0000000800000004),
.INIT_01(256'h000002000000011C0000011800000114000001100000010C0000010800000104),
.INIT_02(256'h000003000000021C0000021800000214000002100000020C0000020800000204),
.INIT_03(256'h000004000000031C0000031800000314000003100000030C0000030800000304),
.INIT_04(256'h000005000000041C0000041800000414000004100000040C0000040800000404),
.INIT_05(256'h000006000000051C0000051800000514000005100000050C0000050800000504),
.INIT_06(256'h000007000000061C0000061800000614000006100000060C0000060800000604),
.INIT_07(256'h000008000000071C0000071800000714000007100000070C0000070800000704),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,dina[19:15],1'b0,1'b0,1'b0,dina[14:10],1'b0,1'b0,1'b0,dina[9:5],1'b0,1'b0,1'b0,dina[4:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23 ,douta[19:15],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31 ,douta[14:10],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39 ,douta[9:5],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47 ,douta[4:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bram_1024_3_blk_mem_gen_top
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_1024_3_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "10" *) (* C_ADDRB_WIDTH = "10" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.74095 mW" *)
(* C_FAMILY = "zynq" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "bram_1024_3.mem" *)
(* C_INIT_FILE_NAME = "bram_1024_3.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1024" *) (* C_READ_DEPTH_B = "1024" *) (* C_READ_WIDTH_A = "20" *)
(* C_READ_WIDTH_B = "20" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1024" *) (* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "20" *) (* C_WRITE_WIDTH_B = "20" *)
(* C_XDEVICEFAMILY = "zynq" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module bram_1024_3_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [9:0]addra;
input [19:0]dina;
output [19:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [9:0]addrb;
input [19:0]dinb;
output [19:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [9:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [19:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [19:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [9:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[19] = \<const0> ;
assign doutb[18] = \<const0> ;
assign doutb[17] = \<const0> ;
assign doutb[16] = \<const0> ;
assign doutb[15] = \<const0> ;
assign doutb[14] = \<const0> ;
assign doutb[13] = \<const0> ;
assign doutb[12] = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
bram_1024_3_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module bram_1024_3_blk_mem_gen_v8_3_5_synth
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_1024_3_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
`include "setseed.vh"
module top(input clk, din, stb, output dout);
reg [41:0] din_bits;
wire [78:0] dout_bits;
reg [41:0] din_shr;
reg [78:0] dout_shr;
always @(posedge clk) begin
if (stb) begin
din_bits <= din_shr;
dout_shr <= dout_bits;
end else begin
din_shr <= {din_shr, din};
dout_shr <= {dout_shr, din_shr[41]};
end
end
assign dout = dout_shr[78];
roi roi (
.clk(clk),
.din_bits(din_bits),
.dout_bits(dout_bits)
);
endmodule
module roi(input clk, input [41:0] din_bits, output [78:0] dout_bits);
picorv32 picorv32 (
.clk(clk),
.resetn(din_bits[0]),
.mem_valid(dout_bits[0]),
.mem_instr(dout_bits[1]),
.mem_ready(din_bits[1]),
.mem_addr(dout_bits[33:2]),
.mem_wdata(dout_bits[66:34]),
.mem_wstrb(dout_bits[70:67]),
.mem_rdata(din_bits[33:2])
);
randluts randluts (
.din(din_bits[41:34]),
.dout(dout_bits[78:71])
);
endmodule
module randluts(input [7:0] din, output [7:0] dout);
localparam integer N =
`SEED % 3 == 2 ? 250 :
`SEED % 3 == 1 ? 100 : 10;
function [31:0] xorshift32(input [31:0] xorin);
begin
xorshift32 = xorin;
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
function [63:0] lutinit(input [7:0] a, b);
begin
lutinit[63:32] = xorshift32(xorshift32(xorshift32(xorshift32({a, b} ^ `SEED))));
lutinit[31: 0] = xorshift32(xorshift32(xorshift32(xorshift32({b, a} ^ `SEED))));
end
endfunction
wire [(N+1)*8-1:0] nets;
assign nets[7:0] = din;
assign dout = nets[(N+1)*8-1:N*8];
genvar i, j;
generate
for (i = 0; i < N; i = i+1) begin:is
for (j = 0; j < 8; j = j+1) begin:js
localparam integer k = xorshift32(xorshift32(xorshift32(xorshift32((i << 20) ^ (j << 10) ^ `SEED)))) & 255;
LUT6 #(
.INIT(lutinit(i, j))
) lut (
.I0(nets[8*i+(k+0)%8]),
.I1(nets[8*i+(k+1)%8]),
.I2(nets[8*i+(k+2)%8]),
.I3(nets[8*i+(k+3)%8]),
.I4(nets[8*i+(k+4)%8]),
.I5(nets[8*i+(k+5)%8]),
.O(nets[8*i+8+j])
);
end
end
endgenerate
endmodule
|
module test_wb_ppfifo_2_mem (
input clk,
input rst,
//wishbone slave signals
input i_wbs_we,
input i_wbs_stb,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_adr,
input [31:0] i_wbs_dat,
output reg [31:0] o_wbs_dat,
output reg o_wbs_ack,
output reg o_wbs_int,
//master control signal for memory arbitration
output o_mem_we,
output o_mem_stb,
output o_mem_cyc,
output [3:0] o_mem_sel,
output [31:0] o_mem_adr,
output [31:0] o_mem_dat,
input [31:0] i_mem_dat,
input i_mem_ack,
input i_mem_int
);
//Local Parameters
localparam REG_CONTROL = 32'h00000000;
localparam REG_STATUS = 32'h00000001;
localparam REG_MEM_0_BASE = 32'h00000002;
localparam REG_MEM_0_SIZE = 32'h00000003;
localparam REG_MEM_1_BASE = 32'h00000004;
localparam REG_MEM_1_SIZE = 32'h00000005;
localparam CLOCK_DIVISOR = 32'h00000006;
//Wires/Registers
reg r_enable;
reg [31:0] r_clock_divisor = 0;
reg [31:0] r_clock_count;
reg dclock;
reg r_dclock;
/*-------------------------------------
* Copy the Following into you core
*-------------------------------------*/
reg [31:0] r_memory_0_base;
reg [31:0] r_memory_0_size;
wire [31:0] w_memory_0_count;
reg r_memory_0_ready;
wire w_memory_0_empty;
wire [31:0] w_default_mem_0_base;
reg [31:0] r_memory_1_base;
reg [31:0] r_memory_1_size;
wire [31:0] w_memory_1_count;
reg r_memory_1_ready;
wire w_memory_1_empty;
wire [31:0] w_default_mem_1_base;
wire w_write_finished;
//Ping Pong FIFO Write Side
wire [23:0] w_wfifo_size;
wire [1:0] w_wfifo_ready;
reg [1:0] r_wfifo_activate;
reg r_wfifo_strobe;
reg [31:0] r_wfifo_data;
wire [23:0] w_rfifo_size;
wire w_rfifo_ready;
wire w_rfifo_activate;
wire w_rfifo_strobe;
wire [31:0] w_rfifo_data;
reg [23:0] r_wfifo_count;
//Submodules
wb_ppfifo_2_mem p2m(
.clk (clk ),
.rst (rst ),
//Control
.i_enable (r_enable ),
.i_memory_0_base (r_memory_0_base ),
.i_memory_0_size (r_memory_0_size ),
.o_memory_0_count (w_memory_0_count ),
.i_memory_0_ready (r_memory_0_ready ),
.o_memory_0_empty (w_memory_0_empty ),
.o_default_mem_0_base (w_default_mem_0_base ),
.i_memory_1_base (r_memory_1_base ),
.i_memory_1_size (r_memory_1_size ),
.o_memory_1_count (w_memory_1_count ),
.i_memory_1_ready (r_memory_1_ready ),
.o_memory_1_empty (w_memory_1_empty ),
.o_default_mem_1_base (w_default_mem_1_base ),
.o_write_finished (w_write_finished ),
//master control signal for memory arbitration
.o_mem_we (o_mem_we ),
.o_mem_stb (o_mem_stb ),
.o_mem_cyc (o_mem_cyc ),
.o_mem_sel (o_mem_sel ),
.o_mem_adr (o_mem_adr ),
.o_mem_dat (o_mem_dat ),
.i_mem_dat (i_mem_dat ),
.i_mem_ack (i_mem_ack ),
.i_mem_int (i_mem_int ),
//Ping Pong FIFO Interface (Read)
.i_ppfifo_rdy (w_rfifo_ready ),
.o_ppfifo_act (w_rfifo_activate ),
.i_ppfifo_size (w_rfifo_size ),
.o_ppfifo_stb (w_rfifo_strobe ),
.i_ppfifo_data (w_rfifo_data )
);
ppfifo #(
.DATA_WIDTH (32 ), //Size will always be 32 bits for mem
.ADDRESS_WIDTH (2 ) //Really small ping pong FIFO (only 4 items)
) ping_pong (
.reset (rst ),
//write
.write_clock (dclock ),
.write_ready (w_wfifo_ready ),
.write_activate (r_wfifo_activate ),
.write_fifo_size (w_wfifo_size ),
.write_strobe (r_wfifo_strobe ),
.write_data (r_wfifo_data ),
//read
.read_clock (clk ),
.read_strobe (w_rfifo_strobe ),
.read_ready (w_rfifo_ready ),
.read_activate (w_rfifo_activate ),
.read_count (w_rfifo_size ),
.read_data (w_rfifo_data )
);
/*-------------------------------------*/
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
r_enable <= 0;
r_clock_divisor <= 0;
/*-------------------------------------
* Copy the following into you module
-------------------------------------*/
//Default base, user can change this from the API
r_memory_0_base <= w_default_mem_0_base;
r_memory_1_base <= w_default_mem_1_base;
//Nothing in the memory initially
r_memory_0_size <= 0;
r_memory_1_size <= 0;
r_memory_0_ready <= 0;
r_memory_1_ready <= 0;
/*-------------------------------------*/
end
else begin
/*-------------------------------------
* Copy the following into you module
-------------------------------------*/
r_memory_0_ready <= 0;
r_memory_1_ready <= 0;
/*-------------------------------------*/
//when the master acks our ack, then put our ack down
if (o_wbs_ack & ~ i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb & i_wbs_cyc) begin
//master is requesting somethign
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
REG_CONTROL: begin
r_enable <= i_wbs_dat[0];
end
REG_STATUS: begin
end
/*-------------------------------------
* Copy the following into you module
-------------------------------------*/
REG_MEM_0_BASE: begin
r_memory_0_base <= i_wbs_dat;
end
REG_MEM_0_SIZE: begin
r_memory_0_size <= i_wbs_dat;
if (i_wbs_dat > 0) begin
r_memory_0_ready <= 1;
end
end
REG_MEM_1_BASE: begin
r_memory_1_base <= i_wbs_dat;
end
REG_MEM_1_SIZE: begin
r_memory_1_size <= i_wbs_dat;
if (i_wbs_dat > 0) begin
r_memory_1_ready <= 1;
end
end
/*-----------------------------------*/
CLOCK_DIVISOR: begin
r_clock_divisor <= i_wbs_dat;
end
default: begin
end
endcase
end
else begin
//Reading
case (i_wbs_adr)
REG_CONTROL: begin
o_wbs_dat <= {31'b0, r_enable};
end
REG_STATUS: begin
//Indicates which memory bank is empty
o_wbs_dat <= {30'h00000000, w_memory_1_empty, w_memory_0_empty};
end
/*-------------------------------------
* Copy these signals directly into your module
-------------------------------------*/
REG_MEM_0_BASE: begin
o_wbs_dat <= r_memory_0_base;
end
REG_MEM_0_SIZE: begin
o_wbs_dat <= w_memory_0_count;
end
REG_MEM_1_BASE: begin
o_wbs_dat <= r_memory_1_base;
end
REG_MEM_1_SIZE: begin
o_wbs_dat <= w_memory_1_count;
end
CLOCK_DIVISOR: begin
o_wbs_dat <= r_clock_divisor;
end
/*-----------------------------------*/
default: begin
o_wbs_dat <= 32'h00;
end
endcase
end
o_wbs_ack <= 1;
end
end
end
always @ (clk) begin
if (r_clock_divisor == 0) begin
dclock = clk;
end
else begin
if (r_clock_count == 0) begin
dclock = r_dclock;
end
end
end
always @ (posedge clk) begin
if (rst) begin
r_clock_count <= 0;
r_dclock <= 0;
end
else begin
if (r_clock_count < r_clock_divisor) begin
r_clock_count <= r_clock_count + 1;
end
else begin
r_clock_count <= 0;
r_dclock <= ~r_dclock;
end
end
end
//Fill up the Ping Pong FIFO with an incrementing number pattern
//You can use this as a starting point for your own module
always @ (posedge dclock) begin
if (rst) begin
r_wfifo_activate <= 0;
r_wfifo_strobe <= 0;
r_wfifo_data <= 0;
r_wfifo_count <= 0;
end
else begin
//Strobes
r_wfifo_strobe <= 0;
if (r_wfifo_strobe) begin
r_wfifo_data <= r_wfifo_data + 1;
end
if ((w_wfifo_ready > 0) && (r_wfifo_activate == 0)) begin
r_wfifo_count <= 0;
if (w_wfifo_ready[0]) begin
r_wfifo_activate[0] <= 1;
end
else begin
r_wfifo_activate[1] <= 1;
end
end
else if (r_wfifo_activate > 0) begin
if (r_wfifo_count < w_wfifo_size) begin
r_wfifo_count <= r_wfifo_count + 1;
r_wfifo_strobe<= 1;
end
else begin
r_wfifo_activate <= 0;
end
end
end
end
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: Dave McCoy ([email protected])
* Description:
* Translates data from an AXI stream interface to a Ping Pong FIFO
*
*
* Changes Who? What?
* 12/26/2015: DFM Initial Checkin
* 04/06/2017: DFM Modified documentation, there is no need for the
* data of either the PPFIFO or AXI Stream to be the same
* size
*/
module adapter_axi_stream_2_ppfifo #(
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = DATA_WIDTH / 8,
parameter USE_KEEP = 0
)(
input rst,
//AXI Stream Input
input i_axi_clk,
output o_axi_ready,
input [DATA_WIDTH - 1:0] i_axi_data,
input [STROBE_WIDTH - 1:0] i_axi_keep,
input i_axi_last,
input i_axi_valid,
//Ping Pong FIFO Write Controller
output o_ppfifo_clk,
input [1:0] i_ppfifo_rdy,
output reg [1:0] o_ppfifo_act,
input [23:0] i_ppfifo_size,
output reg o_ppfifo_stb,
output reg [DATA_WIDTH - 1:0] o_ppfifo_data
);
//local parameters
localparam IDLE = 0;
localparam READY = 1;
localparam RELEASE = 2;
//registes/wires
wire clk; //Convenience Signal
reg [3:0] state;
reg [23:0] r_count;
//submodules
//asynchronous logic
//This is a little strange to just connect the output clock with the input clock but if this is done
//Users do not need to figure out how to hook up the clocks
assign o_ppfifo_clk = i_axi_clk;
assign clk = i_axi_clk;
assign o_axi_ready = (o_ppfifo_act > 0) && (r_count < i_ppfifo_size);
//synchronous logic
always @ (posedge clk) begin
o_ppfifo_stb <= 0;
if (rst) begin
r_count <= 0;
o_ppfifo_act <= 0;
o_ppfifo_data <= 0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
o_ppfifo_act <= 0;
if ((i_ppfifo_rdy > 0) && (o_ppfifo_act == 0)) begin
r_count <= 0;
if (i_ppfifo_rdy[0]) begin
o_ppfifo_act[0] <= 1;
end
else begin
o_ppfifo_act[1] <= 1;
end
state <= READY;
end
end
READY: begin
if (r_count < i_ppfifo_size) begin
if (i_axi_valid) begin
o_ppfifo_stb <= 1;
o_ppfifo_data <= i_axi_data;
r_count <= r_count + 1;
end
end
//Conditions to release the FIFO or stop a transaction
else begin
state <= RELEASE;
end
if (i_axi_last) begin
state <= RELEASE;
end
end
RELEASE: begin
o_ppfifo_act <= 0;
state <= IDLE;
end
default: begin
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4B_1_V
`define SKY130_FD_SC_LS__NOR4B_1_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4b_1 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4b_1 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4B_1_V
|
module myAddSub(A,B,CI,ADD,BOP,Y,CO,OVF);
input [7:0] A;
input [7:0] B;
input CI;
input ADD;
input BOP;
output [7:0] Y;
output CO;
output OVF;
//------------------------------------------------------------
// This is an ADDER/SUBTRACTOR based on the adder subtractor
// that is in the schematic capture library. I added another
// control input that zeros out the B input so that this thing
// can also be used as an incrementer/decrementer depeding on
// the carry input.
//
// parameter:
// A............8 bit bus, input A of Adder/Subtractor
// B............8 bit bus, input B of Adder/Subtractor
// CI...........Carry/nBorrow input
// ADD..........if true, perform addition, 0 perform subtraction
// BOP..........if 1, pass B input, if 0, B = 0
// Y............8 bit bus, 8 bit sum output
// CO...........Carry/nBorrow output
// OVF..........overflow status output
//
//-------------------------------------------------------------
reg[7:0] I;
wire [7:0] Y;
wire C0,C1,C2,C3,C4,C5,C6;
wire C6O;
always @(A or B or CI or ADD or BOP)
begin
I[0] = A[0] ^ (B[0] & BOP) ^ ~ADD;
I[1] = A[1] ^ (B[1] & BOP) ^ ~ADD;
I[2] = A[2] ^ (B[2] & BOP) ^ ~ADD;
I[3] = A[3] ^ (B[3] & BOP) ^ ~ADD;
I[4] = A[4] ^ (B[4] & BOP) ^ ~ADD;
I[5] = A[5] ^ (B[5] & BOP) ^ ~ADD;
I[6] = A[6] ^ (B[6] & BOP) ^ ~ADD;
I[7] = A[7] ^ (B[7] & BOP) ^ ~ADD;
end
MUXCY_L MUXCY_L0 (.LO(C0),.CI(CI),.DI(A[0]),.S(I[0]) );
MUXCY_L MUXCY_L1 (.LO(C1),.CI(C0),.DI(A[1]),.S(I[1]) );
MUXCY_L MUXCY_L2 (.LO(C2),.CI(C1),.DI(A[2]),.S(I[2]) );
MUXCY_L MUXCY_L3 (.LO(C3),.CI(C2),.DI(A[3]),.S(I[3]) );
MUXCY_L MUXCY_L4 (.LO(C4),.CI(C3),.DI(A[4]),.S(I[4]) );
MUXCY_L MUXCY_L5 (.LO(C5),.CI(C4),.DI(A[5]),.S(I[5]) );
MUXCY_D MUXCY_D6 (.LO(C6),.O(C6O),.CI(C5),.DI(A[6]),.S(I[6]) );
MUXCY MUXCY_7 (.O(CO),.CI(C6),.DI(A[7]),.S(I[7]) );
XORCY XORCY0 (.O(Y[0]),.CI(CI), .LI(I[0]));
XORCY XORCY1 (.O(Y[1]),.CI(C0),.LI(I[1]));
XORCY XORCY2 (.O(Y[2]),.CI(C1),.LI(I[2]));
XORCY XORCY3 (.O(Y[3]),.CI(C2),.LI(I[3]));
XORCY XORCY4 (.O(Y[4]),.CI(C3),.LI(I[4]));
XORCY XORCY5 (.O(Y[5]),.CI(C4),.LI(I[5]));
XORCY XORCY6 (.O(Y[6]),.CI(C5),.LI(I[6]));
XORCY XORCY7 (.O(Y[7]),.CI(C6),.LI(I[7]));
XOR2 X1(.O(OVF),.I0(C6O),.I1(CO));
endmodule
|
// File: record_play.v
// Generated by MyHDL 1.0dev
// Date: Sat Nov 4 15:53:54 2017
`timescale 1ns/10ps
module record_play (
clk_i,
button_a,
button_b,
leds_o
);
// Sample value on button B input, store in RAM, and playback by turning LEDs on/off.
// Inputs:
// clk_i: Clock input.
// button_a: Button A input. High when pressed. Controls record/play operation.
// button_b: Button B input. High when pressed. Used to input samples for controlling LEDs.
// Outputs:
// leds_o: LED outputs.
input clk_i;
input button_a;
input button_b;
output [4:0] leds_o;
reg [4:0] leds_o;
reg [0:0] data_i;
reg wr;
reg do_sample;
reg [0:0] data_o;
reg reset;
reg [2:0] state;
reg [10:0] end_addr;
reg [10:0] addr;
reg [16:0] chunk_insts_0_cntr;
reg [0:0] chunk_insts_1_cntr;
reg [0:0] k_mem [0:2048-1];
always @(posedge clk_i) begin: RECORD_PLAY_LOC_INSTS_CHUNK_INSTS_0_LOC_INSTS_CHUNK_INSTS_K
chunk_insts_0_cntr <= (chunk_insts_0_cntr + 1);
do_sample <= 0;
if ((chunk_insts_0_cntr == 119999)) begin
do_sample <= 1;
chunk_insts_0_cntr <= 0;
end
end
always @(posedge clk_i) begin: RECORD_PLAY_LOC_INSTS_CHUNK_INSTS_1_LOC_INSTS_CHUNK_INSTS_K
if ((chunk_insts_1_cntr < 1)) begin
chunk_insts_1_cntr <= (chunk_insts_1_cntr + 1);
reset <= 1;
end
else begin
reset <= 0;
end
end
always @(posedge clk_i) begin: RECORD_PLAY_LOC_INSTS_CHUNK_INSTS_2
wr <= 0;
if (reset) begin
state <= 0;
end
else if (do_sample) begin
case (state)
'h0: begin
leds_o <= 21;
if ((button_a == 1)) begin
state <= 1;
end
end
'h1: begin
leds_o <= 26;
if ((button_a == 0)) begin
addr <= 0;
data_i <= button_b;
wr <= 1;
state <= 2;
end
end
'h2: begin
addr <= (addr + 1);
data_i <= button_b;
wr <= 1;
leds_o <= {1, button_b, button_b, button_b, button_b};
if ((button_a == 1)) begin
end_addr <= (addr + 1);
state <= 3;
end
end
'h3: begin
leds_o <= 16;
if ((button_a == 0)) begin
addr <= 0;
state <= 4;
end
end
'h4: begin
leds_o <= {1, data_o[0], data_o[0], data_o[0], data_o[0]};
addr <= (addr + 1);
if ((addr == end_addr)) begin
addr <= 0;
end
if ((button_a == 1)) begin
state <= 1;
end
end
endcase
end
end
always @(posedge clk_i) begin: RECORD_PLAY_LOC_INSTS_CHUNK_INSTS_K_LOC_INSTS_CHUNK_INSTS_K
if (wr) begin
k_mem[addr] <= data_i;
end
else begin
data_o <= k_mem[addr];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTN_SYMBOL_V
`define SKY130_FD_SC_LP__DLXTN_SYMBOL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlxtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTN_SYMBOL_V
|
`timescale 1ns/1ns
`include "crt.v"
module crt_test;
reg clk;
initial clk = 0;
always #1 clk <= ~clk;
reg reset;
reg cs, we;
wire [15:0] data;
wire [3:0] addr;
reg [3:0] outaddr;
reg [15:0] outdata;
wire irq;
wire hs, vs;
wire ven;
wire [31:0] pixaddr;
assign data = we ? outdata : 16'bz;
assign addr = cs ? outaddr : 4'bz;
crt uut(
.clk(clk),
.reset(reset),
.cs(cs),
.we(we),
.addr(addr),
.data(data),
.irq(irq),
.vs(vs),
.hs(hs),
.ven(ven),
.pixaddr(pixaddr)
);
initial
begin
$dumpfile("crt_test.vcd");
$dumpvars(0, crt_test);
reset <= 1;
cs <= 0;
we <= 0;
#2;
reset <= 0;
// IRQ at column 200
#2;
cs <= 1'b1;
we <= 1'b1;
outaddr <= 4'hC;
outdata <= 16'd200;
// IRQ at row 300
#2;
cs <= 1'b1;
we <= 1'b1;
outaddr <= 4'hD;
outdata <= 16'd300;
// Enable IRQ
#2;
cs <= 1'b1;
we <= 1'b1;
outaddr <= 4'hF;
outdata <= 16'b1000000000000010;
#2;
cs <= 1'b0;
we <= 1'b0;
outaddr <= 4'h0;
outdata <= 16'bz;
// Read all the registers
#2;
cs <= 1'b1;
we <= 1'b0;
outaddr <= 4'h0;
#2 outaddr <= 4'h1;
#2 outaddr <= 4'h2;
#2 outaddr <= 4'h3;
#2 outaddr <= 4'h4;
#2 outaddr <= 4'h5;
#2 outaddr <= 4'h6;
#2 outaddr <= 4'h7;
#2 outaddr <= 4'h8;
#2 outaddr <= 4'h9;
#2 outaddr <= 4'hA;
#2 outaddr <= 4'hB;
#2 outaddr <= 4'hC;
#2 outaddr <= 4'hD;
#2 outaddr <= 4'hE;
#2 outaddr <= 4'hF;
#2;
cs <= 1'b0;
outaddr <= 4'h1;
#1320402;
cs <= 1'b1;
we <= 1'b1;
outaddr <= 4'hE;
outdata <= 16'b0;
#2;
cs <= 1'b0;
we <= 1'b0;
outaddr <= 4'h0;
outdata <= 16'b0;
//9900030
#(2201*1125*2*2+30) $finish;
end
endmodule
module crt_ramdac(clk, pixaddr, ven, qpixel, breq, back);
parameter ADDR_SIZE = 32;
localparam PIXEL_SIZE = 32;
input clk;
input [ADDR_SIZE-1:0] pixaddr;
input ven;
output [PIXEL_SIZE-1:0] qpixel;
output breq;
input back;
always @(posedge clk)
begin
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:11:59 11/11/2015
// Design Name:
// Module Name: LEDWorm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LEDWorm (clk1, clk2, clk3, SSLED, LEDSEL, inClk, buttonA, buttonB, reset);
input inClk, buttonA, buttonB, reset;
output clk1, clk2, clk3;
output [3:0] LEDSEL;
output [6:0] SSLED;
reg [2:0] clockSelect;
wire rotClk, I1, I2, I3;
clockGen_50MHz_to_3Hz prescale_1 (clk1, inClk); // clk1 --> 3Hz
clockGen_divBy2 prescale_2 (clk2, clk1); // clk2 --> 3Hz / 2 = 1.5Hz
clockGen_divBy4 prescale_3 (clk3, clk1); // clk3 --> 3Hz / 4 = 0.75Hz
LEDRotator L1 (SSLED, LEDSEL, rotClk, reset); // Keeps rotating SSLED @rotClk
// Clock Selection Logic
and sel_1 (I1, clk1, clockSelect[2]);
and sel_2 (I2, clk2, clockSelect[1]);
and sel_3 (I3, clk3, clockSelect[0]);
or sel_4 (rotClk, I1, I2, I3);
// Input Signal Handling Logic
always @(posedge buttonA or posedge buttonB or posedge reset) begin
if (reset) begin
clockSelect = 3'b100; // Choose 3Hz Clock on Reset
end else
if (buttonA) begin
// Shift clockwise in set {clk1, clk2, clk3}
case (clockSelect)
3'b100: clockSelect = 3'b010; // clk1 --> clk2
3'b010: clockSelect = 3'b001; // clk2 --> clk3
3'b001: clockSelect = 3'b100; // clk3 --> clk1
default: clockSelect = 3'b100; // Any arbitrary selection goes to a valid selection
endcase
end
else begin
// Shift counter-clockwise in set {clk1, clk2, clk3}
case (clockSelect)
3'b100: clockSelect = 3'b001; // clk1 --> clk3
3'b001: clockSelect = 3'b010; // clk3 --> clk2
3'b010: clockSelect = 3'b100; // clk2 --> clk1
default: clockSelect = 3'b100; // Any arbitrary selection goes to a valid selection
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HDLL__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
/**
* udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dff$PS_pp$PG$N (
Q ,
D ,
CLK ,
SET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input SET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSBP_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFSBP_BLACKBOX_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSBP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__NOR4_BEHAVIORAL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B, C, D );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4_BEHAVIORAL_V |
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1
// read_csr O 65
// read_csr_port2 O 65
// mav_read_csr O 65
// mav_csr_write O 129
// read_frm O 3 reg
// read_fflags O 5 reg
// mv_update_fcsr_fflags O 5
// mv_update_mstatus_fs O 64
// read_misa O 28 const
// read_mstatus O 64 reg
// read_sstatus O 64
// read_ustatus O 64
// read_satp O 64 reg
// csr_trap_actions O 194
// RDY_csr_trap_actions O 1 const
// csr_ret_actions O 130
// RDY_csr_ret_actions O 1 const
// read_csr_minstret O 64 reg
// read_csr_mcycle O 64 reg
// read_csr_mtime O 64 reg
// access_permitted_1 O 1
// access_permitted_2 O 1
// csr_counter_read_fault O 1
// csr_mip_read O 64
// interrupt_pending O 5
// wfi_resume O 1
// nmi_pending O 1 reg
// RDY_debug O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// read_csr_csr_addr I 12
// read_csr_port2_csr_addr I 12
// mav_read_csr_csr_addr I 12
// mav_csr_write_csr_addr I 12
// mav_csr_write_word I 64
// mv_update_fcsr_fflags_flags I 5
// ma_update_fcsr_fflags_flags I 5
// mv_update_mstatus_fs_fs I 2
// ma_update_mstatus_fs_fs I 2
// csr_trap_actions_from_priv I 2
// csr_trap_actions_pc I 64
// csr_trap_actions_nmi I 1
// csr_trap_actions_interrupt I 1
// csr_trap_actions_exc_code I 4
// csr_trap_actions_xtval I 64
// csr_ret_actions_from_priv I 2
// access_permitted_1_priv I 2
// access_permitted_1_csr_addr I 12
// access_permitted_1_read_not_write I 1
// access_permitted_2_priv I 2
// access_permitted_2_csr_addr I 12
// access_permitted_2_read_not_write I 1
// csr_counter_read_fault_priv I 2
// csr_counter_read_fault_csr_addr I 12
// m_external_interrupt_req_set_not_clear I 1 reg
// s_external_interrupt_req_set_not_clear I 1 reg
// timer_interrupt_req_set_not_clear I 1 reg
// software_interrupt_req_set_not_clear I 1 reg
// interrupt_pending_cur_priv I 2
// nmi_req_set_not_clear I 1
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_ma_update_fcsr_fflags I 1
// EN_ma_update_mstatus_fs I 1
// EN_csr_minstret_incr I 1
// EN_debug I 1 unused
// EN_mav_read_csr I 1 unused
// EN_mav_csr_write I 1
// EN_csr_trap_actions I 1
// EN_csr_ret_actions I 1
//
// Combinational paths from inputs to outputs:
// read_csr_csr_addr -> read_csr
// read_csr_port2_csr_addr -> read_csr_port2
// mv_update_fcsr_fflags_flags -> mv_update_fcsr_fflags
// mv_update_mstatus_fs_fs -> mv_update_mstatus_fs
// (access_permitted_1_priv,
// access_permitted_1_csr_addr,
// access_permitted_1_read_not_write) -> access_permitted_1
// (access_permitted_2_priv,
// access_permitted_2_csr_addr,
// access_permitted_2_read_not_write) -> access_permitted_2
// (csr_counter_read_fault_priv,
// csr_counter_read_fault_csr_addr) -> csr_counter_read_fault
// interrupt_pending_cur_priv -> interrupt_pending
// mav_read_csr_csr_addr -> mav_read_csr
// (mav_csr_write_csr_addr,
// mav_csr_write_word,
// EN_mav_csr_write) -> mav_csr_write
// (csr_trap_actions_from_priv,
// csr_trap_actions_nmi,
// csr_trap_actions_interrupt,
// csr_trap_actions_exc_code) -> csr_trap_actions
// csr_ret_actions_from_priv -> csr_ret_actions
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCSR_RegFile(CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
read_csr_csr_addr,
read_csr,
read_csr_port2_csr_addr,
read_csr_port2,
mav_read_csr_csr_addr,
EN_mav_read_csr,
mav_read_csr,
mav_csr_write_csr_addr,
mav_csr_write_word,
EN_mav_csr_write,
mav_csr_write,
read_frm,
read_fflags,
mv_update_fcsr_fflags_flags,
mv_update_fcsr_fflags,
ma_update_fcsr_fflags_flags,
EN_ma_update_fcsr_fflags,
mv_update_mstatus_fs_fs,
mv_update_mstatus_fs,
ma_update_mstatus_fs_fs,
EN_ma_update_mstatus_fs,
read_misa,
read_mstatus,
read_sstatus,
read_ustatus,
read_satp,
csr_trap_actions_from_priv,
csr_trap_actions_pc,
csr_trap_actions_nmi,
csr_trap_actions_interrupt,
csr_trap_actions_exc_code,
csr_trap_actions_xtval,
EN_csr_trap_actions,
csr_trap_actions,
RDY_csr_trap_actions,
csr_ret_actions_from_priv,
EN_csr_ret_actions,
csr_ret_actions,
RDY_csr_ret_actions,
read_csr_minstret,
EN_csr_minstret_incr,
read_csr_mcycle,
read_csr_mtime,
access_permitted_1_priv,
access_permitted_1_csr_addr,
access_permitted_1_read_not_write,
access_permitted_1,
access_permitted_2_priv,
access_permitted_2_csr_addr,
access_permitted_2_read_not_write,
access_permitted_2,
csr_counter_read_fault_priv,
csr_counter_read_fault_csr_addr,
csr_counter_read_fault,
csr_mip_read,
m_external_interrupt_req_set_not_clear,
s_external_interrupt_req_set_not_clear,
timer_interrupt_req_set_not_clear,
software_interrupt_req_set_not_clear,
interrupt_pending_cur_priv,
interrupt_pending,
wfi_resume,
nmi_req_set_not_clear,
nmi_pending,
EN_debug,
RDY_debug);
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// value method read_csr
input [11 : 0] read_csr_csr_addr;
output [64 : 0] read_csr;
// value method read_csr_port2
input [11 : 0] read_csr_port2_csr_addr;
output [64 : 0] read_csr_port2;
// actionvalue method mav_read_csr
input [11 : 0] mav_read_csr_csr_addr;
input EN_mav_read_csr;
output [64 : 0] mav_read_csr;
// actionvalue method mav_csr_write
input [11 : 0] mav_csr_write_csr_addr;
input [63 : 0] mav_csr_write_word;
input EN_mav_csr_write;
output [128 : 0] mav_csr_write;
// value method read_frm
output [2 : 0] read_frm;
// value method read_fflags
output [4 : 0] read_fflags;
// value method mv_update_fcsr_fflags
input [4 : 0] mv_update_fcsr_fflags_flags;
output [4 : 0] mv_update_fcsr_fflags;
// action method ma_update_fcsr_fflags
input [4 : 0] ma_update_fcsr_fflags_flags;
input EN_ma_update_fcsr_fflags;
// value method mv_update_mstatus_fs
input [1 : 0] mv_update_mstatus_fs_fs;
output [63 : 0] mv_update_mstatus_fs;
// action method ma_update_mstatus_fs
input [1 : 0] ma_update_mstatus_fs_fs;
input EN_ma_update_mstatus_fs;
// value method read_misa
output [27 : 0] read_misa;
// value method read_mstatus
output [63 : 0] read_mstatus;
// value method read_sstatus
output [63 : 0] read_sstatus;
// value method read_ustatus
output [63 : 0] read_ustatus;
// value method read_satp
output [63 : 0] read_satp;
// actionvalue method csr_trap_actions
input [1 : 0] csr_trap_actions_from_priv;
input [63 : 0] csr_trap_actions_pc;
input csr_trap_actions_nmi;
input csr_trap_actions_interrupt;
input [3 : 0] csr_trap_actions_exc_code;
input [63 : 0] csr_trap_actions_xtval;
input EN_csr_trap_actions;
output [193 : 0] csr_trap_actions;
output RDY_csr_trap_actions;
// actionvalue method csr_ret_actions
input [1 : 0] csr_ret_actions_from_priv;
input EN_csr_ret_actions;
output [129 : 0] csr_ret_actions;
output RDY_csr_ret_actions;
// value method read_csr_minstret
output [63 : 0] read_csr_minstret;
// action method csr_minstret_incr
input EN_csr_minstret_incr;
// value method read_csr_mcycle
output [63 : 0] read_csr_mcycle;
// value method read_csr_mtime
output [63 : 0] read_csr_mtime;
// value method access_permitted_1
input [1 : 0] access_permitted_1_priv;
input [11 : 0] access_permitted_1_csr_addr;
input access_permitted_1_read_not_write;
output access_permitted_1;
// value method access_permitted_2
input [1 : 0] access_permitted_2_priv;
input [11 : 0] access_permitted_2_csr_addr;
input access_permitted_2_read_not_write;
output access_permitted_2;
// value method csr_counter_read_fault
input [1 : 0] csr_counter_read_fault_priv;
input [11 : 0] csr_counter_read_fault_csr_addr;
output csr_counter_read_fault;
// value method csr_mip_read
output [63 : 0] csr_mip_read;
// action method m_external_interrupt_req
input m_external_interrupt_req_set_not_clear;
// action method s_external_interrupt_req
input s_external_interrupt_req_set_not_clear;
// action method timer_interrupt_req
input timer_interrupt_req_set_not_clear;
// action method software_interrupt_req
input software_interrupt_req_set_not_clear;
// value method interrupt_pending
input [1 : 0] interrupt_pending_cur_priv;
output [4 : 0] interrupt_pending;
// value method wfi_resume
output wfi_resume;
// action method nmi_req
input nmi_req_set_not_clear;
// value method nmi_pending
output nmi_pending;
// action method debug
input EN_debug;
output RDY_debug;
// signals for module outputs
wire [193 : 0] csr_trap_actions;
wire [129 : 0] csr_ret_actions;
wire [128 : 0] mav_csr_write;
wire [64 : 0] mav_read_csr, read_csr, read_csr_port2;
wire [63 : 0] csr_mip_read,
mv_update_mstatus_fs,
read_csr_mcycle,
read_csr_minstret,
read_csr_mtime,
read_mstatus,
read_satp,
read_sstatus,
read_ustatus;
wire [27 : 0] read_misa;
wire [4 : 0] interrupt_pending, mv_update_fcsr_fflags, read_fflags;
wire [2 : 0] read_frm;
wire RDY_csr_ret_actions,
RDY_csr_trap_actions,
RDY_debug,
RDY_server_reset_request_put,
RDY_server_reset_response_get,
access_permitted_1,
access_permitted_2,
csr_counter_read_fault,
nmi_pending,
wfi_resume;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register csr_mstatus_rg_mstatus
reg [63 : 0] csr_mstatus_rg_mstatus;
reg [63 : 0] csr_mstatus_rg_mstatus$D_IN;
wire csr_mstatus_rg_mstatus$EN;
// register rg_dcsr
reg [31 : 0] rg_dcsr;
wire [31 : 0] rg_dcsr$D_IN;
wire rg_dcsr$EN;
// register rg_dpc
reg [63 : 0] rg_dpc;
wire [63 : 0] rg_dpc$D_IN;
wire rg_dpc$EN;
// register rg_dscratch0
reg [63 : 0] rg_dscratch0;
wire [63 : 0] rg_dscratch0$D_IN;
wire rg_dscratch0$EN;
// register rg_dscratch1
reg [63 : 0] rg_dscratch1;
wire [63 : 0] rg_dscratch1$D_IN;
wire rg_dscratch1$EN;
// register rg_fflags
reg [4 : 0] rg_fflags;
reg [4 : 0] rg_fflags$D_IN;
wire rg_fflags$EN;
// register rg_frm
reg [2 : 0] rg_frm;
wire [2 : 0] rg_frm$D_IN;
wire rg_frm$EN;
// register rg_mcause
reg [4 : 0] rg_mcause;
reg [4 : 0] rg_mcause$D_IN;
wire rg_mcause$EN;
// register rg_mcounteren
reg [2 : 0] rg_mcounteren;
wire [2 : 0] rg_mcounteren$D_IN;
wire rg_mcounteren$EN;
// register rg_mcycle
reg [63 : 0] rg_mcycle;
wire [63 : 0] rg_mcycle$D_IN;
wire rg_mcycle$EN;
// register rg_medeleg
reg [15 : 0] rg_medeleg;
wire [15 : 0] rg_medeleg$D_IN;
wire rg_medeleg$EN;
// register rg_mepc
reg [63 : 0] rg_mepc;
wire [63 : 0] rg_mepc$D_IN;
wire rg_mepc$EN;
// register rg_mideleg
reg [11 : 0] rg_mideleg;
wire [11 : 0] rg_mideleg$D_IN;
wire rg_mideleg$EN;
// register rg_minstret
reg [63 : 0] rg_minstret;
wire [63 : 0] rg_minstret$D_IN;
wire rg_minstret$EN;
// register rg_mscratch
reg [63 : 0] rg_mscratch;
wire [63 : 0] rg_mscratch$D_IN;
wire rg_mscratch$EN;
// register rg_mtval
reg [63 : 0] rg_mtval;
wire [63 : 0] rg_mtval$D_IN;
wire rg_mtval$EN;
// register rg_mtvec
reg [62 : 0] rg_mtvec;
wire [62 : 0] rg_mtvec$D_IN;
wire rg_mtvec$EN;
// register rg_nmi
reg rg_nmi;
wire rg_nmi$D_IN, rg_nmi$EN;
// register rg_nmi_vector
reg [63 : 0] rg_nmi_vector;
wire [63 : 0] rg_nmi_vector$D_IN;
wire rg_nmi_vector$EN;
// register rg_satp
reg [63 : 0] rg_satp;
wire [63 : 0] rg_satp$D_IN;
wire rg_satp$EN;
// register rg_scause
reg [4 : 0] rg_scause;
reg [4 : 0] rg_scause$D_IN;
wire rg_scause$EN;
// register rg_sepc
reg [63 : 0] rg_sepc;
wire [63 : 0] rg_sepc$D_IN;
wire rg_sepc$EN;
// register rg_sscratch
reg [63 : 0] rg_sscratch;
wire [63 : 0] rg_sscratch$D_IN;
wire rg_sscratch$EN;
// register rg_state
reg rg_state;
wire rg_state$D_IN, rg_state$EN;
// register rg_stval
reg [63 : 0] rg_stval;
wire [63 : 0] rg_stval$D_IN;
wire rg_stval$EN;
// register rg_stvec
reg [62 : 0] rg_stvec;
wire [62 : 0] rg_stvec$D_IN;
wire rg_stvec$EN;
// register rg_tdata1
reg [63 : 0] rg_tdata1;
wire [63 : 0] rg_tdata1$D_IN;
wire rg_tdata1$EN;
// register rg_tdata2
reg [63 : 0] rg_tdata2;
wire [63 : 0] rg_tdata2$D_IN;
wire rg_tdata2$EN;
// register rg_tdata3
reg [63 : 0] rg_tdata3;
wire [63 : 0] rg_tdata3$D_IN;
wire rg_tdata3$EN;
// register rg_tselect
reg [63 : 0] rg_tselect;
wire [63 : 0] rg_tselect$D_IN;
wire rg_tselect$EN;
// ports of submodule csr_mie
wire [63 : 0] csr_mie$mav_sie_write,
csr_mie$mav_sie_write_wordxl,
csr_mie$mav_write,
csr_mie$mav_write_wordxl,
csr_mie$mv_read,
csr_mie$mv_sie_read;
wire [27 : 0] csr_mie$mav_sie_write_misa, csr_mie$mav_write_misa;
wire csr_mie$EN_mav_sie_write, csr_mie$EN_mav_write, csr_mie$EN_reset;
// ports of submodule csr_mip
wire [63 : 0] csr_mip$mav_sip_write,
csr_mip$mav_sip_write_wordxl,
csr_mip$mav_write,
csr_mip$mav_write_wordxl,
csr_mip$mv_read,
csr_mip$mv_sip_read;
wire [27 : 0] csr_mip$mav_sip_write_misa, csr_mip$mav_write_misa;
wire csr_mip$EN_mav_sip_write,
csr_mip$EN_mav_write,
csr_mip$EN_reset,
csr_mip$m_external_interrupt_req_req,
csr_mip$s_external_interrupt_req_req,
csr_mip$software_interrupt_req_req,
csr_mip$timer_interrupt_req_req;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_mtvec_reset_value,
soc_map$m_nmivec_reset_value;
// rule scheduling signals
wire CAN_FIRE_RL_rl_mcycle_incr,
CAN_FIRE_RL_rl_reset_start,
CAN_FIRE_RL_rl_upd_minstret_csrrx,
CAN_FIRE_RL_rl_upd_minstret_incr,
CAN_FIRE_csr_minstret_incr,
CAN_FIRE_csr_ret_actions,
CAN_FIRE_csr_trap_actions,
CAN_FIRE_debug,
CAN_FIRE_m_external_interrupt_req,
CAN_FIRE_ma_update_fcsr_fflags,
CAN_FIRE_ma_update_mstatus_fs,
CAN_FIRE_mav_csr_write,
CAN_FIRE_mav_read_csr,
CAN_FIRE_nmi_req,
CAN_FIRE_s_external_interrupt_req,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_software_interrupt_req,
CAN_FIRE_timer_interrupt_req,
WILL_FIRE_RL_rl_mcycle_incr,
WILL_FIRE_RL_rl_reset_start,
WILL_FIRE_RL_rl_upd_minstret_csrrx,
WILL_FIRE_RL_rl_upd_minstret_incr,
WILL_FIRE_csr_minstret_incr,
WILL_FIRE_csr_ret_actions,
WILL_FIRE_csr_trap_actions,
WILL_FIRE_debug,
WILL_FIRE_m_external_interrupt_req,
WILL_FIRE_ma_update_fcsr_fflags,
WILL_FIRE_ma_update_mstatus_fs,
WILL_FIRE_mav_csr_write,
WILL_FIRE_mav_read_csr,
WILL_FIRE_nmi_req,
WILL_FIRE_s_external_interrupt_req,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_software_interrupt_req,
WILL_FIRE_timer_interrupt_req;
// inputs to muxes for submodule ports
reg [63 : 0] MUX_csr_mstatus_rg_mstatus$write_1__VAL_5;
wire [63 : 0] MUX_csr_mstatus_rg_mstatus$write_1__VAL_2,
MUX_csr_mstatus_rg_mstatus$write_1__VAL_4,
MUX_rg_minstret$write_1__VAL_1,
MUX_rg_minstret$write_1__VAL_2;
wire [62 : 0] MUX_rg_mtvec$write_1__VAL_1, MUX_rg_mtvec$write_1__VAL_2;
wire [15 : 0] MUX_rg_medeleg$write_1__VAL_1;
wire [4 : 0] MUX_rg_fflags$write_1__VAL_3,
MUX_rg_mcause$write_1__VAL_2,
MUX_rg_mcause$write_1__VAL_3;
wire [2 : 0] MUX_rg_frm$write_1__VAL_1;
wire MUX_csr_mstatus_rg_mstatus$write_1__SEL_5,
MUX_rg_fflags$write_1__SEL_2,
MUX_rg_frm$write_1__SEL_1,
MUX_rg_mcause$write_1__SEL_2,
MUX_rg_mcause$write_1__SEL_3,
MUX_rg_mcounteren$write_1__SEL_1,
MUX_rg_medeleg$write_1__SEL_1,
MUX_rg_mideleg$write_1__SEL_1,
MUX_rg_mtvec$write_1__SEL_1,
MUX_rg_satp$write_1__SEL_1,
MUX_rg_scause$write_1__SEL_2,
MUX_rg_scause$write_1__SEL_3,
MUX_rg_sepc$write_1__SEL_1,
MUX_rg_state$write_1__SEL_2,
MUX_rg_stval$write_1__SEL_1,
MUX_rg_stvec$write_1__SEL_1,
MUX_rg_tdata1$write_1__SEL_1,
MUX_rw_minstret$wset_1__SEL_1;
// remaining internal signals
reg [63 : 0] IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731,
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291,
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511,
y_avValue_fst__h11071;
reg [61 : 0] CASE_new_priv3604_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1;
reg CASE_new_priv3604_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2,
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1761,
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1864;
wire [63 : 0] IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1294,
IF_csr_ret_actions_from_priv_EQ_0b11_476_THEN__ETC___d1496,
_theResult___fst__h15874,
_theResult___fst__h16075,
csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1489,
csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1286,
exc_pc___1__h14867,
exc_pc__h14793,
mask__h13813,
mask__h13830,
mask__h15895,
mask__h15912,
mav_csr_write_word_BITS_14_TO_13_68_EQ_0x3_69__ETC___d799,
new_csr_value__h10690,
new_csr_value__h9962,
v__h10003,
v__h13609,
v__h7767,
v__h9124,
v__h9160,
v__h9770,
val__h13814,
val__h13831,
val__h15913,
vector_offset__h14794,
wordxl1__h7197,
wordxl1__h9207,
x__h12581,
x__h13812,
x__h13825,
x__h13842,
x__h15718,
x__h15719,
x__h15894,
x__h15907,
x__h15924,
x__h5601,
y__h13826,
y__h13843,
y__h15908,
y__h15925,
y_avValue_fst__h10831,
y_avValue_fst__h10836,
y_avValue_fst__h10841,
y_avValue_fst__h14750,
y_avValue_fst__h14767,
y_avValue_snd_snd__h14840;
wire [22 : 0] fixed_up_val_23__h11439,
fixed_up_val_23__h11993,
fixed_up_val_23__h13653,
fixed_up_val_23__h15781,
fixed_up_val_23__h7238,
fixed_up_val_23__h7818,
fixed_up_val_23__h9248;
wire [5 : 0] ie_from_x__h15858,
ie_to_x__h13730,
pie_from_x__h15859,
pie_to_x__h13731;
wire [3 : 0] IF_NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_N_ETC___d1942,
IF_NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_N_ETC___d1944,
IF_NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_N_ETC___d1945,
IF_NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_N_ETC___d1947,
exc_code__h15560;
wire [1 : 0] IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_59__ETC___d761,
_theResult____h17471,
_theResult____h17683,
_theResult____h17895,
_theResult____h18107,
_theResult____h18319,
_theResult____h18531,
_theResult____h18743,
_theResult____h18955,
_theResult____h19167,
_theResult___fst__h13742,
new_priv__h13604,
to_y__h16074;
wire NOT_access_permitted_1_csr_addr_ULT_0xC03_517__ETC___d1617,
NOT_access_permitted_2_csr_addr_ULT_0xC03_622__ETC___d1720,
NOT_cfg_verbosity_read__53_ULE_1_54___d955,
NOT_csr_mip_mv_read__53_BIT_0_831_922_OR_NOT_c_ETC___d1929,
NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_NOT__ETC___d1867,
NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_NOT__ETC___d1894,
NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_NOT__ETC___d1921,
NOT_csr_mip_mv_read__53_BIT_1_798_895_OR_NOT_c_ETC___d1902,
NOT_csr_mip_mv_read__53_BIT_3_765_868_OR_NOT_c_ETC___d1875,
NOT_csr_mip_mv_read__53_BIT_5_809_904_OR_NOT_c_ETC___d1911,
NOT_csr_mip_mv_read__53_BIT_7_776_877_OR_NOT_c_ETC___d1884,
NOT_csr_mip_mv_read__53_BIT_8_820_913_OR_NOT_c_ETC___d1920,
NOT_csr_mip_mv_read__53_BIT_9_787_886_OR_NOT_c_ETC___d1893,
NOT_csr_trap_actions_nmi_311_AND_csr_trap_acti_ETC___d1421,
b__h13829,
b__h15911,
csr_mip_mv_read__53_BIT_0_831_AND_csr_mie_mv_r_ETC___d1840,
csr_mip_mv_read__53_BIT_11_747_AND_csr_mie_mv__ETC___d1764,
csr_mip_mv_read__53_BIT_11_747_AND_csr_mie_mv__ETC___d1830,
csr_mip_mv_read__53_BIT_1_798_AND_csr_mie_mv_r_ETC___d1807,
csr_mip_mv_read__53_BIT_3_765_AND_csr_mie_mv_r_ETC___d1774,
csr_mip_mv_read__53_BIT_4_842_AND_csr_mie_mv_r_ETC___d1851,
csr_mip_mv_read__53_BIT_5_809_AND_csr_mie_mv_r_ETC___d1818,
csr_mip_mv_read__53_BIT_7_776_AND_csr_mie_mv_r_ETC___d1785,
csr_mip_mv_read__53_BIT_8_820_AND_csr_mie_mv_r_ETC___d1829,
csr_mip_mv_read__53_BIT_9_787_AND_csr_mie_mv_r_ETC___d1796,
csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1320,
csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1472,
deleg_bit___1__h13751,
deleg_bit___1__h13766,
interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1753,
interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1771,
interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1782,
interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1793,
interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1804,
interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1815,
interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1826,
interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1837,
interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1752,
interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1770,
interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1781,
interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1792,
interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1803,
interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1814,
interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1825,
interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1836,
mav_csr_write_csr_addr_ULE_0x33F___d739,
mav_csr_write_csr_addr_ULE_0xB1F___d735,
mav_csr_write_csr_addr_ULT_0x323_38_OR_NOT_mav_ETC___d951,
mav_csr_write_csr_addr_ULT_0x323___d738,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d1022,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d755,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d808,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d815,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d826,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d828,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d832,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d839,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d842,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d844,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d846,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d848,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d850,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d852,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d854,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d856,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d860,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d862,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d864,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d868,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d870,
mav_csr_write_csr_addr_ULT_0xB03___d734,
sd__h11438,
sd__h11992,
sd__h13652,
sd__h15780,
sd__h9247;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get = rg_state && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get =
rg_state && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// value method read_csr
assign read_csr =
{ read_csr_csr_addr >= 12'hC03 && read_csr_csr_addr <= 12'hC1F ||
read_csr_csr_addr >= 12'hB03 && read_csr_csr_addr <= 12'hB1F ||
read_csr_csr_addr >= 12'h323 && read_csr_csr_addr <= 12'h33F ||
read_csr_csr_addr == 12'h001 ||
read_csr_csr_addr == 12'h002 ||
read_csr_csr_addr == 12'h003 ||
read_csr_csr_addr == 12'hC00 ||
read_csr_csr_addr == 12'hC02 ||
read_csr_csr_addr == 12'h100 ||
read_csr_csr_addr == 12'h102 ||
read_csr_csr_addr == 12'h103 ||
read_csr_csr_addr == 12'h104 ||
read_csr_csr_addr == 12'h105 ||
read_csr_csr_addr == 12'h106 ||
read_csr_csr_addr == 12'h140 ||
read_csr_csr_addr == 12'h141 ||
read_csr_csr_addr == 12'h142 ||
read_csr_csr_addr == 12'h143 ||
read_csr_csr_addr == 12'h144 ||
read_csr_csr_addr == 12'h180 ||
read_csr_csr_addr == 12'h302 ||
read_csr_csr_addr == 12'h303 ||
read_csr_csr_addr == 12'hF11 ||
read_csr_csr_addr == 12'hF12 ||
read_csr_csr_addr == 12'hF13 ||
read_csr_csr_addr == 12'hF14 ||
read_csr_csr_addr == 12'h300 ||
read_csr_csr_addr == 12'h301 ||
read_csr_csr_addr == 12'h304 ||
read_csr_csr_addr == 12'h305 ||
read_csr_csr_addr == 12'h306 ||
read_csr_csr_addr == 12'h340 ||
read_csr_csr_addr == 12'h341 ||
read_csr_csr_addr == 12'h342 ||
read_csr_csr_addr == 12'h343 ||
read_csr_csr_addr == 12'h344 ||
read_csr_csr_addr == 12'hB00 ||
read_csr_csr_addr == 12'hB02 ||
read_csr_csr_addr == 12'h7A0 ||
read_csr_csr_addr == 12'h7A1 ||
read_csr_csr_addr == 12'h7A2 ||
read_csr_csr_addr == 12'h7A3,
(read_csr_csr_addr >= 12'hC03 &&
read_csr_csr_addr <= 12'hC1F ||
read_csr_csr_addr >= 12'hB03 &&
read_csr_csr_addr <= 12'hB1F ||
read_csr_csr_addr >= 12'h323 &&
read_csr_csr_addr <= 12'h33F) ?
64'd0 :
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 } ;
// value method read_csr_port2
assign read_csr_port2 =
{ read_csr_port2_csr_addr >= 12'hC03 &&
read_csr_port2_csr_addr <= 12'hC1F ||
read_csr_port2_csr_addr >= 12'hB03 &&
read_csr_port2_csr_addr <= 12'hB1F ||
read_csr_port2_csr_addr >= 12'h323 &&
read_csr_port2_csr_addr <= 12'h33F ||
read_csr_port2_csr_addr == 12'h001 ||
read_csr_port2_csr_addr == 12'h002 ||
read_csr_port2_csr_addr == 12'h003 ||
read_csr_port2_csr_addr == 12'hC00 ||
read_csr_port2_csr_addr == 12'hC02 ||
read_csr_port2_csr_addr == 12'h100 ||
read_csr_port2_csr_addr == 12'h102 ||
read_csr_port2_csr_addr == 12'h103 ||
read_csr_port2_csr_addr == 12'h104 ||
read_csr_port2_csr_addr == 12'h105 ||
read_csr_port2_csr_addr == 12'h106 ||
read_csr_port2_csr_addr == 12'h140 ||
read_csr_port2_csr_addr == 12'h141 ||
read_csr_port2_csr_addr == 12'h142 ||
read_csr_port2_csr_addr == 12'h143 ||
read_csr_port2_csr_addr == 12'h144 ||
read_csr_port2_csr_addr == 12'h180 ||
read_csr_port2_csr_addr == 12'h302 ||
read_csr_port2_csr_addr == 12'h303 ||
read_csr_port2_csr_addr == 12'hF11 ||
read_csr_port2_csr_addr == 12'hF12 ||
read_csr_port2_csr_addr == 12'hF13 ||
read_csr_port2_csr_addr == 12'hF14 ||
read_csr_port2_csr_addr == 12'h300 ||
read_csr_port2_csr_addr == 12'h301 ||
read_csr_port2_csr_addr == 12'h304 ||
read_csr_port2_csr_addr == 12'h305 ||
read_csr_port2_csr_addr == 12'h306 ||
read_csr_port2_csr_addr == 12'h340 ||
read_csr_port2_csr_addr == 12'h341 ||
read_csr_port2_csr_addr == 12'h342 ||
read_csr_port2_csr_addr == 12'h343 ||
read_csr_port2_csr_addr == 12'h344 ||
read_csr_port2_csr_addr == 12'hB00 ||
read_csr_port2_csr_addr == 12'hB02 ||
read_csr_port2_csr_addr == 12'h7A0 ||
read_csr_port2_csr_addr == 12'h7A1 ||
read_csr_port2_csr_addr == 12'h7A2 ||
read_csr_port2_csr_addr == 12'h7A3,
(read_csr_port2_csr_addr >= 12'hC03 &&
read_csr_port2_csr_addr <= 12'hC1F ||
read_csr_port2_csr_addr >= 12'hB03 &&
read_csr_port2_csr_addr <= 12'hB1F ||
read_csr_port2_csr_addr >= 12'h323 &&
read_csr_port2_csr_addr <= 12'h33F) ?
64'd0 :
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 } ;
// actionvalue method mav_read_csr
assign mav_read_csr =
{ mav_read_csr_csr_addr >= 12'hC03 &&
mav_read_csr_csr_addr <= 12'hC1F ||
mav_read_csr_csr_addr >= 12'hB03 &&
mav_read_csr_csr_addr <= 12'hB1F ||
mav_read_csr_csr_addr >= 12'h323 &&
mav_read_csr_csr_addr <= 12'h33F ||
mav_read_csr_csr_addr == 12'h001 ||
mav_read_csr_csr_addr == 12'h002 ||
mav_read_csr_csr_addr == 12'h003 ||
mav_read_csr_csr_addr == 12'hC00 ||
mav_read_csr_csr_addr == 12'hC02 ||
mav_read_csr_csr_addr == 12'h100 ||
mav_read_csr_csr_addr == 12'h102 ||
mav_read_csr_csr_addr == 12'h103 ||
mav_read_csr_csr_addr == 12'h104 ||
mav_read_csr_csr_addr == 12'h105 ||
mav_read_csr_csr_addr == 12'h106 ||
mav_read_csr_csr_addr == 12'h140 ||
mav_read_csr_csr_addr == 12'h141 ||
mav_read_csr_csr_addr == 12'h142 ||
mav_read_csr_csr_addr == 12'h143 ||
mav_read_csr_csr_addr == 12'h144 ||
mav_read_csr_csr_addr == 12'h180 ||
mav_read_csr_csr_addr == 12'h302 ||
mav_read_csr_csr_addr == 12'h303 ||
mav_read_csr_csr_addr == 12'hF11 ||
mav_read_csr_csr_addr == 12'hF12 ||
mav_read_csr_csr_addr == 12'hF13 ||
mav_read_csr_csr_addr == 12'hF14 ||
mav_read_csr_csr_addr == 12'h300 ||
mav_read_csr_csr_addr == 12'h301 ||
mav_read_csr_csr_addr == 12'h304 ||
mav_read_csr_csr_addr == 12'h305 ||
mav_read_csr_csr_addr == 12'h306 ||
mav_read_csr_csr_addr == 12'h340 ||
mav_read_csr_csr_addr == 12'h341 ||
mav_read_csr_csr_addr == 12'h342 ||
mav_read_csr_csr_addr == 12'h343 ||
mav_read_csr_csr_addr == 12'h344 ||
mav_read_csr_csr_addr == 12'hB00 ||
mav_read_csr_csr_addr == 12'hB02 ||
mav_read_csr_csr_addr == 12'h7A0 ||
mav_read_csr_csr_addr == 12'h7A1 ||
mav_read_csr_csr_addr == 12'h7A2 ||
mav_read_csr_csr_addr == 12'h7A3,
(mav_read_csr_csr_addr >= 12'hC03 &&
mav_read_csr_csr_addr <= 12'hC1F ||
mav_read_csr_csr_addr >= 12'hB03 &&
mav_read_csr_csr_addr <= 12'hB1F ||
mav_read_csr_csr_addr >= 12'h323 &&
mav_read_csr_csr_addr <= 12'h33F) ?
64'd0 :
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 } ;
assign CAN_FIRE_mav_read_csr = 1'd1 ;
assign WILL_FIRE_mav_read_csr = EN_mav_read_csr ;
// actionvalue method mav_csr_write
assign mav_csr_write =
{ x__h5601,
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d1022,
wordxl1__h7197 } ;
assign CAN_FIRE_mav_csr_write = 1'd1 ;
assign WILL_FIRE_mav_csr_write = EN_mav_csr_write ;
// value method read_frm
assign read_frm = rg_frm ;
// value method read_fflags
assign read_fflags = rg_fflags ;
// value method mv_update_fcsr_fflags
assign mv_update_fcsr_fflags = rg_fflags | mv_update_fcsr_fflags_flags ;
// action method ma_update_fcsr_fflags
assign CAN_FIRE_ma_update_fcsr_fflags = 1'd1 ;
assign WILL_FIRE_ma_update_fcsr_fflags = EN_ma_update_fcsr_fflags ;
// value method mv_update_mstatus_fs
assign mv_update_mstatus_fs =
{ sd__h11438, 40'd5120, fixed_up_val_23__h11439 } ;
// action method ma_update_mstatus_fs
assign CAN_FIRE_ma_update_mstatus_fs = 1'd1 ;
assign WILL_FIRE_ma_update_mstatus_fs = EN_ma_update_mstatus_fs ;
// value method read_misa
assign read_misa = 28'd135532845 ;
// value method read_mstatus
assign read_mstatus = csr_mstatus_rg_mstatus ;
// value method read_sstatus
assign read_sstatus =
{ csr_mstatus_rg_mstatus[63],
29'd0,
csr_mstatus_rg_mstatus[33:32],
12'd0,
csr_mstatus_rg_mstatus[19:18],
1'd0,
csr_mstatus_rg_mstatus[16:13],
4'd0,
csr_mstatus_rg_mstatus[8],
2'd0,
csr_mstatus_rg_mstatus[5:4],
2'd0,
csr_mstatus_rg_mstatus[1:0] } ;
// value method read_ustatus
assign read_ustatus =
{ 59'd0,
csr_mstatus_rg_mstatus[4],
3'd0,
csr_mstatus_rg_mstatus[0] } ;
// value method read_satp
assign read_satp = rg_satp ;
// actionvalue method csr_trap_actions
assign csr_trap_actions =
{ x__h12581, x__h15718, x__h15719, new_priv__h13604 } ;
assign RDY_csr_trap_actions = 1'd1 ;
assign CAN_FIRE_csr_trap_actions = 1'd1 ;
assign WILL_FIRE_csr_trap_actions = EN_csr_trap_actions ;
// actionvalue method csr_ret_actions
assign csr_ret_actions =
(csr_ret_actions_from_priv == 2'b11) ?
{ rg_mepc,
csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1489[12:11],
_theResult___fst__h15874 } :
{ rg_sepc, to_y__h16074, _theResult___fst__h16075 } ;
assign RDY_csr_ret_actions = 1'd1 ;
assign CAN_FIRE_csr_ret_actions = 1'd1 ;
assign WILL_FIRE_csr_ret_actions = EN_csr_ret_actions ;
// value method read_csr_minstret
assign read_csr_minstret = rg_minstret ;
// action method csr_minstret_incr
assign CAN_FIRE_csr_minstret_incr = 1'd1 ;
assign WILL_FIRE_csr_minstret_incr = EN_csr_minstret_incr ;
// value method read_csr_mcycle
assign read_csr_mcycle = rg_mcycle ;
// value method read_csr_mtime
assign read_csr_mtime = rg_mcycle ;
// value method access_permitted_1
assign access_permitted_1 =
NOT_access_permitted_1_csr_addr_ULT_0xC03_517__ETC___d1617 &&
(access_permitted_1_read_not_write ||
access_permitted_1_csr_addr[11:10] != 2'b11) ;
// value method access_permitted_2
assign access_permitted_2 =
NOT_access_permitted_2_csr_addr_ULT_0xC03_622__ETC___d1720 &&
(access_permitted_2_read_not_write ||
access_permitted_2_csr_addr[11:10] != 2'b11) ;
// value method csr_counter_read_fault
assign csr_counter_read_fault =
(csr_counter_read_fault_priv == 2'b01 ||
csr_counter_read_fault_priv == 2'b0) &&
(csr_counter_read_fault_csr_addr == 12'hC00 &&
!rg_mcounteren[0] ||
csr_counter_read_fault_csr_addr == 12'hC01 &&
!rg_mcounteren[1] ||
csr_counter_read_fault_csr_addr == 12'hC02 &&
!rg_mcounteren[2] ||
csr_counter_read_fault_csr_addr >= 12'hC03 &&
csr_counter_read_fault_csr_addr <= 12'hC1F) ;
// value method csr_mip_read
assign csr_mip_read = csr_mip$mv_read ;
// action method m_external_interrupt_req
assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;
// action method s_external_interrupt_req
assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;
// action method timer_interrupt_req
assign CAN_FIRE_timer_interrupt_req = 1'd1 ;
assign WILL_FIRE_timer_interrupt_req = 1'd1 ;
// action method software_interrupt_req
assign CAN_FIRE_software_interrupt_req = 1'd1 ;
assign WILL_FIRE_software_interrupt_req = 1'd1 ;
// value method interrupt_pending
assign interrupt_pending =
{ csr_mip_mv_read__53_BIT_11_747_AND_csr_mie_mv__ETC___d1830 ||
csr_mip_mv_read__53_BIT_0_831_AND_csr_mie_mv_r_ETC___d1840 ||
csr_mip_mv_read__53_BIT_4_842_AND_csr_mie_mv_r_ETC___d1851,
IF_NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_N_ETC___d1947 } ;
// value method wfi_resume
assign wfi_resume = (csr_mip$mv_read & csr_mie$mv_read) != 64'd0 ;
// action method nmi_req
assign CAN_FIRE_nmi_req = 1'd1 ;
assign WILL_FIRE_nmi_req = 1'd1 ;
// value method nmi_pending
assign nmi_pending = rg_nmi ;
// action method debug
assign RDY_debug = 1'd1 ;
assign CAN_FIRE_debug = 1'd1 ;
assign WILL_FIRE_debug = EN_debug ;
// submodule csr_mie
mkCSR_MIE csr_mie(.CLK(CLK),
.RST_N(RST_N),
.mav_sie_write_misa(csr_mie$mav_sie_write_misa),
.mav_sie_write_wordxl(csr_mie$mav_sie_write_wordxl),
.mav_write_misa(csr_mie$mav_write_misa),
.mav_write_wordxl(csr_mie$mav_write_wordxl),
.EN_reset(csr_mie$EN_reset),
.EN_mav_write(csr_mie$EN_mav_write),
.EN_mav_sie_write(csr_mie$EN_mav_sie_write),
.mv_read(csr_mie$mv_read),
.mav_write(csr_mie$mav_write),
.mv_sie_read(csr_mie$mv_sie_read),
.mav_sie_write(csr_mie$mav_sie_write));
// submodule csr_mip
mkCSR_MIP csr_mip(.CLK(CLK),
.RST_N(RST_N),
.m_external_interrupt_req_req(csr_mip$m_external_interrupt_req_req),
.mav_sip_write_misa(csr_mip$mav_sip_write_misa),
.mav_sip_write_wordxl(csr_mip$mav_sip_write_wordxl),
.mav_write_misa(csr_mip$mav_write_misa),
.mav_write_wordxl(csr_mip$mav_write_wordxl),
.s_external_interrupt_req_req(csr_mip$s_external_interrupt_req_req),
.software_interrupt_req_req(csr_mip$software_interrupt_req_req),
.timer_interrupt_req_req(csr_mip$timer_interrupt_req_req),
.EN_reset(csr_mip$EN_reset),
.EN_mav_write(csr_mip$EN_mav_write),
.EN_mav_sip_write(csr_mip$EN_mav_sip_write),
.mv_read(csr_mip$mv_read),
.mav_write(csr_mip$mav_write),
.mv_sip_read(csr_mip$mv_sip_read),
.mav_sip_write(csr_mip$mav_sip_write));
// submodule f_reset_rsps
FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(soc_map$m_mtvec_reset_value),
.m_nmivec_reset_value(soc_map$m_nmivec_reset_value));
// rule RL_rl_reset_start
assign CAN_FIRE_RL_rl_reset_start = !rg_state ;
assign WILL_FIRE_RL_rl_reset_start = MUX_rg_state$write_1__SEL_2 ;
// rule RL_rl_mcycle_incr
assign CAN_FIRE_RL_rl_mcycle_incr = 1'd1 ;
assign WILL_FIRE_RL_rl_mcycle_incr = 1'd1 ;
// rule RL_rl_upd_minstret_csrrx
assign CAN_FIRE_RL_rl_upd_minstret_csrrx =
MUX_rw_minstret$wset_1__SEL_1 || WILL_FIRE_RL_rl_reset_start ;
assign WILL_FIRE_RL_rl_upd_minstret_csrrx =
CAN_FIRE_RL_rl_upd_minstret_csrrx ;
// rule RL_rl_upd_minstret_incr
assign CAN_FIRE_RL_rl_upd_minstret_incr =
!CAN_FIRE_RL_rl_upd_minstret_csrrx && EN_csr_minstret_incr ;
assign WILL_FIRE_RL_rl_upd_minstret_incr =
CAN_FIRE_RL_rl_upd_minstret_incr ;
// inputs to muxes for submodule ports
assign MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d755 ;
assign MUX_rg_fflags$write_1__SEL_2 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746 ;
assign MUX_rg_frm$write_1__SEL_1 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803 ;
assign MUX_rg_mcause$write_1__SEL_2 =
EN_csr_trap_actions &&
(csr_trap_actions_nmi || new_priv__h13604 == 2'b11) ;
assign MUX_rg_mcause$write_1__SEL_3 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d852 ;
assign MUX_rg_mcounteren$write_1__SEL_1 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d846 ;
assign MUX_rg_medeleg$write_1__SEL_1 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d832 ;
assign MUX_rg_mideleg$write_1__SEL_1 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d839 ;
assign MUX_rg_mtvec$write_1__SEL_1 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d844 ;
assign MUX_rg_satp$write_1__SEL_1 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830 ;
assign MUX_rg_scause$write_1__SEL_2 =
EN_csr_trap_actions && !csr_trap_actions_nmi &&
new_priv__h13604 == 2'b01 ;
assign MUX_rg_scause$write_1__SEL_3 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821 ;
assign MUX_rg_sepc$write_1__SEL_1 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817 ;
assign MUX_rg_state$write_1__SEL_2 =
CAN_FIRE_RL_rl_reset_start && !EN_mav_csr_write ;
assign MUX_rg_stval$write_1__SEL_1 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d826 ;
assign MUX_rg_stvec$write_1__SEL_1 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810 ;
assign MUX_rg_tdata1$write_1__SEL_1 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d864 ;
assign MUX_rw_minstret$wset_1__SEL_1 =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d860 ;
assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 =
{ sd__h15780, 40'd5120, fixed_up_val_23__h15781 } ;
assign MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 =
{ sd__h11992, 40'd5120, fixed_up_val_23__h11993 } ;
always@(mav_csr_write_csr_addr or
mav_csr_write_word_BITS_14_TO_13_68_EQ_0x3_69__ETC___d799 or
wordxl1__h7197)
begin
case (mav_csr_write_csr_addr)
12'h001, 12'h002, 12'h003:
MUX_csr_mstatus_rg_mstatus$write_1__VAL_5 = wordxl1__h7197;
default: MUX_csr_mstatus_rg_mstatus$write_1__VAL_5 =
mav_csr_write_word_BITS_14_TO_13_68_EQ_0x3_69__ETC___d799;
endcase
end
assign MUX_rg_fflags$write_1__VAL_3 =
rg_fflags | ma_update_fcsr_fflags_flags ;
assign MUX_rg_frm$write_1__VAL_1 =
(mav_csr_write_csr_addr == 12'h002) ?
mav_csr_write_word[2:0] :
mav_csr_write_word[7:5] ;
assign MUX_rg_mcause$write_1__VAL_2 =
{ !csr_trap_actions_nmi && csr_trap_actions_interrupt,
exc_code__h15560 } ;
assign MUX_rg_mcause$write_1__VAL_3 =
{ mav_csr_write_word[63], mav_csr_write_word[3:0] } ;
assign MUX_rg_medeleg$write_1__VAL_1 =
{ mav_csr_write_word[15],
1'd0,
mav_csr_write_word[13:12],
2'd0,
mav_csr_write_word[9:0] } ;
assign MUX_rg_minstret$write_1__VAL_1 =
MUX_rw_minstret$wset_1__SEL_1 ? mav_csr_write_word : 64'd0 ;
assign MUX_rg_minstret$write_1__VAL_2 = rg_minstret + 64'd1 ;
assign MUX_rg_mtvec$write_1__VAL_1 =
{ mav_csr_write_word[63:2], mav_csr_write_word[0] } ;
assign MUX_rg_mtvec$write_1__VAL_2 =
{ soc_map$m_mtvec_reset_value[63:2],
soc_map$m_mtvec_reset_value[0] } ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = 4'h0 ;
assign cfg_verbosity$EN = 1'b0 ;
// register csr_mstatus_rg_mstatus
always@(WILL_FIRE_RL_rl_reset_start or
EN_csr_ret_actions or
MUX_csr_mstatus_rg_mstatus$write_1__VAL_2 or
EN_csr_trap_actions or
v__h13609 or
EN_ma_update_mstatus_fs or
MUX_csr_mstatus_rg_mstatus$write_1__VAL_4 or
MUX_csr_mstatus_rg_mstatus$write_1__SEL_5 or
MUX_csr_mstatus_rg_mstatus$write_1__VAL_5)
case (1'b1)
WILL_FIRE_RL_rl_reset_start:
csr_mstatus_rg_mstatus$D_IN = 64'h0000000A00002000;
EN_csr_ret_actions:
csr_mstatus_rg_mstatus$D_IN =
MUX_csr_mstatus_rg_mstatus$write_1__VAL_2;
EN_csr_trap_actions: csr_mstatus_rg_mstatus$D_IN = v__h13609;
EN_ma_update_mstatus_fs:
csr_mstatus_rg_mstatus$D_IN =
MUX_csr_mstatus_rg_mstatus$write_1__VAL_4;
MUX_csr_mstatus_rg_mstatus$write_1__SEL_5:
csr_mstatus_rg_mstatus$D_IN =
MUX_csr_mstatus_rg_mstatus$write_1__VAL_5;
default: csr_mstatus_rg_mstatus$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csr_mstatus_rg_mstatus$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d755 ||
EN_csr_trap_actions ||
EN_ma_update_mstatus_fs ||
EN_csr_ret_actions ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_dcsr
assign rg_dcsr$D_IN = 32'h0 ;
assign rg_dcsr$EN = 1'b0 ;
// register rg_dpc
assign rg_dpc$D_IN = 64'h0 ;
assign rg_dpc$EN = 1'b0 ;
// register rg_dscratch0
assign rg_dscratch0$D_IN = 64'h0 ;
assign rg_dscratch0$EN = 1'b0 ;
// register rg_dscratch1
assign rg_dscratch1$D_IN = 64'h0 ;
assign rg_dscratch1$EN = 1'b0 ;
// register rg_fflags
always@(WILL_FIRE_RL_rl_reset_start or
MUX_rg_fflags$write_1__SEL_2 or
mav_csr_write_word or
EN_ma_update_fcsr_fflags or MUX_rg_fflags$write_1__VAL_3)
case (1'b1)
WILL_FIRE_RL_rl_reset_start: rg_fflags$D_IN = 5'd0;
MUX_rg_fflags$write_1__SEL_2: rg_fflags$D_IN = mav_csr_write_word[4:0];
EN_ma_update_fcsr_fflags: rg_fflags$D_IN = MUX_rg_fflags$write_1__VAL_3;
default: rg_fflags$D_IN = 5'b01010 /* unspecified value */ ;
endcase
assign rg_fflags$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746 ||
EN_ma_update_fcsr_fflags ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_frm
assign rg_frm$D_IN =
MUX_rg_frm$write_1__SEL_1 ? MUX_rg_frm$write_1__VAL_1 : 3'd0 ;
assign rg_frm$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803 ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_mcause
always@(WILL_FIRE_RL_rl_reset_start or
MUX_rg_mcause$write_1__SEL_2 or
MUX_rg_mcause$write_1__VAL_2 or
MUX_rg_mcause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3)
case (1'b1)
WILL_FIRE_RL_rl_reset_start: rg_mcause$D_IN = 5'd0;
MUX_rg_mcause$write_1__SEL_2:
rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_2;
MUX_rg_mcause$write_1__SEL_3:
rg_mcause$D_IN = MUX_rg_mcause$write_1__VAL_3;
default: rg_mcause$D_IN = 5'b01010 /* unspecified value */ ;
endcase
assign rg_mcause$EN =
EN_csr_trap_actions &&
(csr_trap_actions_nmi || new_priv__h13604 == 2'b11) ||
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d852 ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_mcounteren
assign rg_mcounteren$D_IN =
MUX_rg_mcounteren$write_1__SEL_1 ?
mav_csr_write_word[2:0] :
3'd0 ;
assign rg_mcounteren$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d846 ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_mcycle
assign rg_mcycle$D_IN = rg_mcycle + 64'd1 ;
assign rg_mcycle$EN = 1'd1 ;
// register rg_medeleg
assign rg_medeleg$D_IN =
MUX_rg_medeleg$write_1__SEL_1 ?
MUX_rg_medeleg$write_1__VAL_1 :
16'd0 ;
assign rg_medeleg$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d832 ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_mepc
assign rg_mepc$D_IN =
MUX_rg_mcause$write_1__SEL_2 ?
csr_trap_actions_pc :
new_csr_value__h9962 ;
assign rg_mepc$EN =
EN_csr_trap_actions &&
(csr_trap_actions_nmi || new_priv__h13604 == 2'b11) ||
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d850 ;
// register rg_mideleg
assign rg_mideleg$D_IN =
MUX_rg_mideleg$write_1__SEL_1 ?
mav_csr_write_word[11:0] :
12'd0 ;
assign rg_mideleg$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d839 ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_minstret
assign rg_minstret$D_IN =
WILL_FIRE_RL_rl_upd_minstret_csrrx ?
MUX_rg_minstret$write_1__VAL_1 :
MUX_rg_minstret$write_1__VAL_2 ;
assign rg_minstret$EN =
WILL_FIRE_RL_rl_upd_minstret_csrrx ||
WILL_FIRE_RL_rl_upd_minstret_incr ;
// register rg_mscratch
assign rg_mscratch$D_IN = mav_csr_write_word ;
assign rg_mscratch$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d848 ;
// register rg_mtval
assign rg_mtval$D_IN =
MUX_rg_mcause$write_1__SEL_2 ?
csr_trap_actions_xtval :
mav_csr_write_word ;
assign rg_mtval$EN =
EN_csr_trap_actions &&
(csr_trap_actions_nmi || new_priv__h13604 == 2'b11) ||
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d854 ;
// register rg_mtvec
assign rg_mtvec$D_IN =
MUX_rg_mtvec$write_1__SEL_1 ?
MUX_rg_mtvec$write_1__VAL_1 :
MUX_rg_mtvec$write_1__VAL_2 ;
assign rg_mtvec$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d844 ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_nmi
assign rg_nmi$D_IN = !WILL_FIRE_RL_rl_reset_start && nmi_req_set_not_clear ;
assign rg_nmi$EN = 1'b1 ;
// register rg_nmi_vector
assign rg_nmi_vector$D_IN = soc_map$m_nmivec_reset_value ;
assign rg_nmi_vector$EN = MUX_rg_state$write_1__SEL_2 ;
// register rg_satp
assign rg_satp$D_IN =
MUX_rg_satp$write_1__SEL_1 ? mav_csr_write_word : 64'd0 ;
assign rg_satp$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830 ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_scause
always@(WILL_FIRE_RL_rl_reset_start or
MUX_rg_scause$write_1__SEL_2 or
MUX_rg_mcause$write_1__VAL_2 or
MUX_rg_scause$write_1__SEL_3 or MUX_rg_mcause$write_1__VAL_3)
case (1'b1)
WILL_FIRE_RL_rl_reset_start: rg_scause$D_IN = 5'd0;
MUX_rg_scause$write_1__SEL_2:
rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_2;
MUX_rg_scause$write_1__SEL_3:
rg_scause$D_IN = MUX_rg_mcause$write_1__VAL_3;
default: rg_scause$D_IN = 5'b01010 /* unspecified value */ ;
endcase
assign rg_scause$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821 ||
EN_csr_trap_actions && !csr_trap_actions_nmi &&
new_priv__h13604 == 2'b01 ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_sepc
assign rg_sepc$D_IN =
MUX_rg_sepc$write_1__SEL_1 ?
new_csr_value__h9962 :
csr_trap_actions_pc ;
assign rg_sepc$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817 ||
EN_csr_trap_actions && !csr_trap_actions_nmi &&
new_priv__h13604 == 2'b01 ;
// register rg_sscratch
assign rg_sscratch$D_IN = mav_csr_write_word ;
assign rg_sscratch$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d815 ;
// register rg_state
assign rg_state$D_IN = !EN_server_reset_request_put ;
assign rg_state$EN =
EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ;
// register rg_stval
assign rg_stval$D_IN =
MUX_rg_stval$write_1__SEL_1 ?
mav_csr_write_word :
csr_trap_actions_xtval ;
assign rg_stval$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d826 ||
EN_csr_trap_actions && !csr_trap_actions_nmi &&
new_priv__h13604 == 2'b01 ;
// register rg_stvec
assign rg_stvec$D_IN =
MUX_rg_stvec$write_1__SEL_1 ?
MUX_rg_mtvec$write_1__VAL_1 :
MUX_rg_mtvec$write_1__VAL_2 ;
assign rg_stvec$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810 ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_tdata1
assign rg_tdata1$D_IN =
MUX_rg_tdata1$write_1__SEL_1 ? new_csr_value__h10690 : 64'd0 ;
assign rg_tdata1$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d864 ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_tdata2
assign rg_tdata2$D_IN = mav_csr_write_word ;
assign rg_tdata2$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d868 ;
// register rg_tdata3
assign rg_tdata3$D_IN = mav_csr_write_word ;
assign rg_tdata3$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d870 ;
// register rg_tselect
assign rg_tselect$D_IN = 64'd0 ;
assign rg_tselect$EN =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d862 ||
WILL_FIRE_RL_rl_reset_start ;
// submodule csr_mie
assign csr_mie$mav_sie_write_misa = 28'd135532845 ;
assign csr_mie$mav_sie_write_wordxl = mav_csr_write_word ;
assign csr_mie$mav_write_misa = 28'd135532845 ;
assign csr_mie$mav_write_wordxl = mav_csr_write_word ;
assign csr_mie$EN_reset = MUX_rg_state$write_1__SEL_2 ;
assign csr_mie$EN_mav_write =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d842 ;
assign csr_mie$EN_mav_sie_write =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d808 ;
// submodule csr_mip
assign csr_mip$m_external_interrupt_req_req =
m_external_interrupt_req_set_not_clear ;
assign csr_mip$mav_sip_write_misa = 28'd135532845 ;
assign csr_mip$mav_sip_write_wordxl = mav_csr_write_word ;
assign csr_mip$mav_write_misa = 28'd135532845 ;
assign csr_mip$mav_write_wordxl = mav_csr_write_word ;
assign csr_mip$s_external_interrupt_req_req =
s_external_interrupt_req_set_not_clear ;
assign csr_mip$software_interrupt_req_req =
software_interrupt_req_set_not_clear ;
assign csr_mip$timer_interrupt_req_req = timer_interrupt_req_set_not_clear ;
assign csr_mip$EN_reset = MUX_rg_state$write_1__SEL_2 ;
assign csr_mip$EN_mav_write =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d856 ;
assign csr_mip$EN_mav_sip_write =
EN_mav_csr_write &&
mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d828 ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = EN_server_reset_request_put ;
assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1294 =
(new_priv__h13604 == 2'b11) ?
{ csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1286[63:13],
csr_trap_actions_from_priv,
csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1286[10:0] } :
{ csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1286[63:9],
csr_trap_actions_from_priv[0],
csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1286[7:0] } ;
assign IF_NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_N_ETC___d1942 =
(NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_NOT__ETC___d1867 &&
NOT_csr_mip_mv_read__53_BIT_3_765_868_OR_NOT_c_ETC___d1875 &&
NOT_csr_mip_mv_read__53_BIT_7_776_877_OR_NOT_c_ETC___d1884) ?
4'd9 :
((NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_NOT__ETC___d1867 &&
NOT_csr_mip_mv_read__53_BIT_3_765_868_OR_NOT_c_ETC___d1875) ?
4'd7 :
(NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_NOT__ETC___d1867 ?
4'd3 :
4'd11)) ;
assign IF_NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_N_ETC___d1944 =
(NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_NOT__ETC___d1894 &&
NOT_csr_mip_mv_read__53_BIT_1_798_895_OR_NOT_c_ETC___d1902) ?
4'd5 :
(NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_NOT__ETC___d1894 ?
4'd1 :
IF_NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_N_ETC___d1942) ;
assign IF_NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_N_ETC___d1945 =
(NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_NOT__ETC___d1894 &&
NOT_csr_mip_mv_read__53_BIT_1_798_895_OR_NOT_c_ETC___d1902 &&
NOT_csr_mip_mv_read__53_BIT_5_809_904_OR_NOT_c_ETC___d1911) ?
4'd8 :
IF_NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_N_ETC___d1944 ;
assign IF_NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_N_ETC___d1947 =
(NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_NOT__ETC___d1921 &&
NOT_csr_mip_mv_read__53_BIT_0_831_922_OR_NOT_c_ETC___d1929) ?
4'd4 :
(NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_NOT__ETC___d1921 ?
4'd0 :
IF_NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_N_ETC___d1945) ;
assign IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_59__ETC___d761 =
(csr_mstatus_rg_mstatus[12:11] == 2'b10) ?
2'b01 :
csr_mstatus_rg_mstatus[12:11] ;
assign IF_csr_ret_actions_from_priv_EQ_0b11_476_THEN__ETC___d1496 =
(csr_ret_actions_from_priv == 2'b11) ?
_theResult___fst__h15874 :
_theResult___fst__h16075 ;
assign NOT_access_permitted_1_csr_addr_ULT_0xC03_517__ETC___d1617 =
(access_permitted_1_csr_addr >= 12'hC03 &&
access_permitted_1_csr_addr <= 12'hC1F ||
access_permitted_1_csr_addr >= 12'hB03 &&
access_permitted_1_csr_addr <= 12'hB1F ||
access_permitted_1_csr_addr >= 12'h323 &&
access_permitted_1_csr_addr <= 12'h33F ||
access_permitted_1_csr_addr == 12'h001 ||
access_permitted_1_csr_addr == 12'h002 ||
access_permitted_1_csr_addr == 12'h003 ||
access_permitted_1_csr_addr == 12'hC00 ||
access_permitted_1_csr_addr == 12'hC02 ||
access_permitted_1_csr_addr == 12'h100 ||
access_permitted_1_csr_addr == 12'h102 ||
access_permitted_1_csr_addr == 12'h103 ||
access_permitted_1_csr_addr == 12'h104 ||
access_permitted_1_csr_addr == 12'h105 ||
access_permitted_1_csr_addr == 12'h106 ||
access_permitted_1_csr_addr == 12'h140 ||
access_permitted_1_csr_addr == 12'h141 ||
access_permitted_1_csr_addr == 12'h142 ||
access_permitted_1_csr_addr == 12'h143 ||
access_permitted_1_csr_addr == 12'h144 ||
access_permitted_1_csr_addr == 12'h180 ||
access_permitted_1_csr_addr == 12'h302 ||
access_permitted_1_csr_addr == 12'h303 ||
access_permitted_1_csr_addr == 12'hF11 ||
access_permitted_1_csr_addr == 12'hF12 ||
access_permitted_1_csr_addr == 12'hF13 ||
access_permitted_1_csr_addr == 12'hF14 ||
access_permitted_1_csr_addr == 12'h300 ||
access_permitted_1_csr_addr == 12'h301 ||
access_permitted_1_csr_addr == 12'h304 ||
access_permitted_1_csr_addr == 12'h305 ||
access_permitted_1_csr_addr == 12'h306 ||
access_permitted_1_csr_addr == 12'h340 ||
access_permitted_1_csr_addr == 12'h341 ||
access_permitted_1_csr_addr == 12'h342 ||
access_permitted_1_csr_addr == 12'h343 ||
access_permitted_1_csr_addr == 12'h344 ||
access_permitted_1_csr_addr == 12'hB00 ||
access_permitted_1_csr_addr == 12'hB02 ||
access_permitted_1_csr_addr == 12'h7A0 ||
access_permitted_1_csr_addr == 12'h7A1 ||
access_permitted_1_csr_addr == 12'h7A2 ||
access_permitted_1_csr_addr == 12'h7A3) &&
access_permitted_1_priv >= access_permitted_1_csr_addr[9:8] &&
(access_permitted_1_csr_addr != 12'h180 ||
!csr_mstatus_rg_mstatus[20]) ;
assign NOT_access_permitted_2_csr_addr_ULT_0xC03_622__ETC___d1720 =
(access_permitted_2_csr_addr >= 12'hC03 &&
access_permitted_2_csr_addr <= 12'hC1F ||
access_permitted_2_csr_addr >= 12'hB03 &&
access_permitted_2_csr_addr <= 12'hB1F ||
access_permitted_2_csr_addr >= 12'h323 &&
access_permitted_2_csr_addr <= 12'h33F ||
access_permitted_2_csr_addr == 12'h001 ||
access_permitted_2_csr_addr == 12'h002 ||
access_permitted_2_csr_addr == 12'h003 ||
access_permitted_2_csr_addr == 12'hC00 ||
access_permitted_2_csr_addr == 12'hC02 ||
access_permitted_2_csr_addr == 12'h100 ||
access_permitted_2_csr_addr == 12'h102 ||
access_permitted_2_csr_addr == 12'h103 ||
access_permitted_2_csr_addr == 12'h104 ||
access_permitted_2_csr_addr == 12'h105 ||
access_permitted_2_csr_addr == 12'h106 ||
access_permitted_2_csr_addr == 12'h140 ||
access_permitted_2_csr_addr == 12'h141 ||
access_permitted_2_csr_addr == 12'h142 ||
access_permitted_2_csr_addr == 12'h143 ||
access_permitted_2_csr_addr == 12'h144 ||
access_permitted_2_csr_addr == 12'h180 ||
access_permitted_2_csr_addr == 12'h302 ||
access_permitted_2_csr_addr == 12'h303 ||
access_permitted_2_csr_addr == 12'hF11 ||
access_permitted_2_csr_addr == 12'hF12 ||
access_permitted_2_csr_addr == 12'hF13 ||
access_permitted_2_csr_addr == 12'hF14 ||
access_permitted_2_csr_addr == 12'h300 ||
access_permitted_2_csr_addr == 12'h301 ||
access_permitted_2_csr_addr == 12'h304 ||
access_permitted_2_csr_addr == 12'h305 ||
access_permitted_2_csr_addr == 12'h306 ||
access_permitted_2_csr_addr == 12'h340 ||
access_permitted_2_csr_addr == 12'h341 ||
access_permitted_2_csr_addr == 12'h342 ||
access_permitted_2_csr_addr == 12'h343 ||
access_permitted_2_csr_addr == 12'h344 ||
access_permitted_2_csr_addr == 12'hB00 ||
access_permitted_2_csr_addr == 12'hB02 ||
access_permitted_2_csr_addr == 12'h7A0 ||
access_permitted_2_csr_addr == 12'h7A1 ||
access_permitted_2_csr_addr == 12'h7A2 ||
access_permitted_2_csr_addr == 12'h7A3) &&
access_permitted_2_priv >= access_permitted_2_csr_addr[9:8] &&
(access_permitted_2_csr_addr != 12'h180 ||
!csr_mstatus_rg_mstatus[20]) ;
assign NOT_cfg_verbosity_read__53_ULE_1_54___d955 = cfg_verbosity > 4'd1 ;
assign NOT_csr_mip_mv_read__53_BIT_0_831_922_OR_NOT_c_ETC___d1929 =
!csr_mip$mv_read[0] || !csr_mie$mv_read[0] ||
!interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1836 &&
(!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1837 ||
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1864) ;
assign NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_NOT__ETC___d1867 =
!csr_mip$mv_read[11] || !csr_mie$mv_read[11] ||
!interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1752 &&
(!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1753 ||
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1864) ;
assign NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_NOT__ETC___d1894 =
NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_NOT__ETC___d1867 &&
NOT_csr_mip_mv_read__53_BIT_3_765_868_OR_NOT_c_ETC___d1875 &&
NOT_csr_mip_mv_read__53_BIT_7_776_877_OR_NOT_c_ETC___d1884 &&
NOT_csr_mip_mv_read__53_BIT_9_787_886_OR_NOT_c_ETC___d1893 ;
assign NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_NOT__ETC___d1921 =
NOT_csr_mip_mv_read__53_BIT_11_747_853_OR_NOT__ETC___d1894 &&
NOT_csr_mip_mv_read__53_BIT_1_798_895_OR_NOT_c_ETC___d1902 &&
NOT_csr_mip_mv_read__53_BIT_5_809_904_OR_NOT_c_ETC___d1911 &&
NOT_csr_mip_mv_read__53_BIT_8_820_913_OR_NOT_c_ETC___d1920 ;
assign NOT_csr_mip_mv_read__53_BIT_1_798_895_OR_NOT_c_ETC___d1902 =
!csr_mip$mv_read[1] || !csr_mie$mv_read[1] ||
!interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1803 &&
(!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1804 ||
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1864) ;
assign NOT_csr_mip_mv_read__53_BIT_3_765_868_OR_NOT_c_ETC___d1875 =
!csr_mip$mv_read[3] || !csr_mie$mv_read[3] ||
!interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1770 &&
(!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1771 ||
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1864) ;
assign NOT_csr_mip_mv_read__53_BIT_5_809_904_OR_NOT_c_ETC___d1911 =
!csr_mip$mv_read[5] || !csr_mie$mv_read[5] ||
!interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1814 &&
(!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1815 ||
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1864) ;
assign NOT_csr_mip_mv_read__53_BIT_7_776_877_OR_NOT_c_ETC___d1884 =
!csr_mip$mv_read[7] || !csr_mie$mv_read[7] ||
!interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1781 &&
(!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1782 ||
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1864) ;
assign NOT_csr_mip_mv_read__53_BIT_8_820_913_OR_NOT_c_ETC___d1920 =
!csr_mip$mv_read[8] || !csr_mie$mv_read[8] ||
!interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1825 &&
(!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1826 ||
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1864) ;
assign NOT_csr_mip_mv_read__53_BIT_9_787_886_OR_NOT_c_ETC___d1893 =
!csr_mip$mv_read[9] || !csr_mie$mv_read[9] ||
!interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1792 &&
(!interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1793 ||
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1864) ;
assign NOT_csr_trap_actions_nmi_311_AND_csr_trap_acti_ETC___d1421 =
!csr_trap_actions_nmi && csr_trap_actions_interrupt &&
exc_code__h15560 != 4'd0 &&
exc_code__h15560 != 4'd1 &&
exc_code__h15560 != 4'd2 &&
exc_code__h15560 != 4'd3 &&
exc_code__h15560 != 4'd4 &&
exc_code__h15560 != 4'd5 &&
exc_code__h15560 != 4'd6 &&
exc_code__h15560 != 4'd7 &&
exc_code__h15560 != 4'd8 &&
exc_code__h15560 != 4'd9 &&
exc_code__h15560 != 4'd10 &&
exc_code__h15560 != 4'd11 ;
assign _theResult____h17471 = rg_mideleg[11] ? 2'b01 : 2'b11 ;
assign _theResult____h17683 = rg_mideleg[3] ? 2'b01 : 2'b11 ;
assign _theResult____h17895 = rg_mideleg[7] ? 2'b01 : 2'b11 ;
assign _theResult____h18107 = rg_mideleg[9] ? 2'b01 : 2'b11 ;
assign _theResult____h18319 = rg_mideleg[1] ? 2'b01 : 2'b11 ;
assign _theResult____h18531 = rg_mideleg[5] ? 2'b01 : 2'b11 ;
assign _theResult____h18743 = rg_mideleg[8] ? 2'b01 : 2'b11 ;
assign _theResult____h18955 = rg_mideleg[0] ? 2'b01 : 2'b11 ;
assign _theResult____h19167 = rg_mideleg[4] ? 2'b01 : 2'b11 ;
assign _theResult___fst__h13742 =
(csr_trap_actions_interrupt ?
deleg_bit___1__h13751 :
deleg_bit___1__h13766) ?
2'b01 :
2'b11 ;
assign _theResult___fst__h15874 =
{ csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1489[63:13],
2'd0,
csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1489[10:0] } ;
assign _theResult___fst__h16075 =
{ csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1489[63:9],
1'd0,
csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1489[7:0] } ;
assign b__h13829 = csr_mstatus_rg_mstatus[ie_to_x__h13730] ;
assign b__h15911 = csr_mstatus_rg_mstatus[pie_from_x__h15859] ;
assign csr_mip_mv_read__53_BIT_0_831_AND_csr_mie_mv_r_ETC___d1840 =
csr_mip$mv_read[0] && csr_mie$mv_read[0] &&
(interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1836 ||
interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1837 &&
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1761) ;
assign csr_mip_mv_read__53_BIT_11_747_AND_csr_mie_mv__ETC___d1764 =
csr_mip$mv_read[11] && csr_mie$mv_read[11] &&
(interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1752 ||
interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1753 &&
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1761) ;
assign csr_mip_mv_read__53_BIT_11_747_AND_csr_mie_mv__ETC___d1830 =
csr_mip_mv_read__53_BIT_11_747_AND_csr_mie_mv__ETC___d1764 ||
csr_mip_mv_read__53_BIT_3_765_AND_csr_mie_mv_r_ETC___d1774 ||
csr_mip_mv_read__53_BIT_7_776_AND_csr_mie_mv_r_ETC___d1785 ||
csr_mip_mv_read__53_BIT_9_787_AND_csr_mie_mv_r_ETC___d1796 ||
csr_mip_mv_read__53_BIT_1_798_AND_csr_mie_mv_r_ETC___d1807 ||
csr_mip_mv_read__53_BIT_5_809_AND_csr_mie_mv_r_ETC___d1818 ||
csr_mip_mv_read__53_BIT_8_820_AND_csr_mie_mv_r_ETC___d1829 ;
assign csr_mip_mv_read__53_BIT_1_798_AND_csr_mie_mv_r_ETC___d1807 =
csr_mip$mv_read[1] && csr_mie$mv_read[1] &&
(interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1803 ||
interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1804 &&
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1761) ;
assign csr_mip_mv_read__53_BIT_3_765_AND_csr_mie_mv_r_ETC___d1774 =
csr_mip$mv_read[3] && csr_mie$mv_read[3] &&
(interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1770 ||
interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1771 &&
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1761) ;
assign csr_mip_mv_read__53_BIT_4_842_AND_csr_mie_mv_r_ETC___d1851 =
csr_mip$mv_read[4] && csr_mie$mv_read[4] &&
(interrupt_pending_cur_priv < _theResult____h19167 ||
interrupt_pending_cur_priv == _theResult____h19167 &&
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1761) ;
assign csr_mip_mv_read__53_BIT_5_809_AND_csr_mie_mv_r_ETC___d1818 =
csr_mip$mv_read[5] && csr_mie$mv_read[5] &&
(interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1814 ||
interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1815 &&
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1761) ;
assign csr_mip_mv_read__53_BIT_7_776_AND_csr_mie_mv_r_ETC___d1785 =
csr_mip$mv_read[7] && csr_mie$mv_read[7] &&
(interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1781 ||
interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1782 &&
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1761) ;
assign csr_mip_mv_read__53_BIT_8_820_AND_csr_mie_mv_r_ETC___d1829 =
csr_mip$mv_read[8] && csr_mie$mv_read[8] &&
(interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1825 ||
interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1826 &&
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1761) ;
assign csr_mip_mv_read__53_BIT_9_787_AND_csr_mie_mv_r_ETC___d1796 =
csr_mip$mv_read[9] && csr_mie$mv_read[9] &&
(interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1792 ||
interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1793 &&
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1761) ;
assign csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1489 =
x__h15907 | mask__h15895 ;
assign csr_mstatus_rg_mstatus_03_AND_INV_1_SL_1_CONCA_ETC___d1286 =
x__h13825 | val__h13814 ;
assign csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1320 =
csr_trap_actions_interrupt && !csr_trap_actions_nmi &&
CASE_new_priv3604_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 ;
assign csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1472 =
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h15560 != 4'd0 &&
exc_code__h15560 != 4'd1 &&
exc_code__h15560 != 4'd2 &&
exc_code__h15560 != 4'd3 &&
exc_code__h15560 != 4'd4 &&
exc_code__h15560 != 4'd5 &&
exc_code__h15560 != 4'd6 &&
exc_code__h15560 != 4'd7 &&
exc_code__h15560 != 4'd8 &&
exc_code__h15560 != 4'd9 &&
exc_code__h15560 != 4'd11 &&
exc_code__h15560 != 4'd12 &&
exc_code__h15560 != 4'd13 &&
exc_code__h15560 != 4'd15 ;
assign deleg_bit___1__h13751 = rg_mideleg[csr_trap_actions_exc_code] ;
assign deleg_bit___1__h13766 = rg_medeleg[csr_trap_actions_exc_code] ;
assign exc_code__h15560 =
csr_trap_actions_nmi ? 4'd0 : csr_trap_actions_exc_code ;
assign exc_pc___1__h14867 = exc_pc__h14793 + vector_offset__h14794 ;
assign exc_pc__h14793 =
csr_trap_actions_nmi ?
rg_nmi_vector :
y_avValue_snd_snd__h14840 ;
assign fixed_up_val_23__h11439 =
{ csr_mstatus_rg_mstatus[22:17],
2'd0,
mv_update_mstatus_fs_fs,
IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_59__ETC___d761,
csr_mstatus_rg_mstatus[10:5],
1'd0,
csr_mstatus_rg_mstatus[3:1],
1'd0 } ;
assign fixed_up_val_23__h11993 =
{ csr_mstatus_rg_mstatus[22:17],
2'd0,
ma_update_mstatus_fs_fs,
IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_59__ETC___d761,
csr_mstatus_rg_mstatus[10:5],
1'd0,
csr_mstatus_rg_mstatus[3:1],
1'd0 } ;
assign fixed_up_val_23__h13653 =
{ IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1294[22:17],
2'd0,
IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1294[14:13],
(IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1294[12:11] ==
2'b10) ?
2'b01 :
IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1294[12:11],
IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1294[10:5],
1'd0,
IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1294[3:1],
1'd0 } ;
assign fixed_up_val_23__h15781 =
{ IF_csr_ret_actions_from_priv_EQ_0b11_476_THEN__ETC___d1496[22:17],
2'd0,
IF_csr_ret_actions_from_priv_EQ_0b11_476_THEN__ETC___d1496[14:13],
(IF_csr_ret_actions_from_priv_EQ_0b11_476_THEN__ETC___d1496[12:11] ==
2'b10) ?
2'b01 :
IF_csr_ret_actions_from_priv_EQ_0b11_476_THEN__ETC___d1496[12:11],
IF_csr_ret_actions_from_priv_EQ_0b11_476_THEN__ETC___d1496[10:5],
1'd0,
IF_csr_ret_actions_from_priv_EQ_0b11_476_THEN__ETC___d1496[3:1],
1'd0 } ;
assign fixed_up_val_23__h7238 =
{ csr_mstatus_rg_mstatus[22:17],
4'd3,
IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_59__ETC___d761,
csr_mstatus_rg_mstatus[10:5],
1'd0,
csr_mstatus_rg_mstatus[3:1],
1'd0 } ;
assign fixed_up_val_23__h7818 =
{ csr_mstatus_rg_mstatus[22:20],
mav_csr_write_word[19:18],
csr_mstatus_rg_mstatus[17],
2'd0,
mav_csr_write_word[14:13],
IF_csr_mstatus_rg_mstatus_03_BITS_12_TO_11_59__ETC___d761,
csr_mstatus_rg_mstatus[10:9],
mav_csr_write_word[8],
csr_mstatus_rg_mstatus[7:6],
mav_csr_write_word[5],
1'd0,
csr_mstatus_rg_mstatus[3:2],
mav_csr_write_word[1],
1'd0 } ;
assign fixed_up_val_23__h9248 =
{ mav_csr_write_word[22:17],
2'd0,
mav_csr_write_word[14:13],
(mav_csr_write_word[12:11] == 2'b10) ?
2'b01 :
mav_csr_write_word[12:11],
mav_csr_write_word[10:5],
1'd0,
mav_csr_write_word[3:1],
1'd0 } ;
assign ie_from_x__h15858 = { 4'd0, csr_ret_actions_from_priv } ;
assign ie_to_x__h13730 = { 4'd0, new_priv__h13604 } ;
assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1753 =
interrupt_pending_cur_priv == _theResult____h17471 ;
assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1771 =
interrupt_pending_cur_priv == _theResult____h17683 ;
assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1782 =
interrupt_pending_cur_priv == _theResult____h17895 ;
assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1793 =
interrupt_pending_cur_priv == _theResult____h18107 ;
assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1804 =
interrupt_pending_cur_priv == _theResult____h18319 ;
assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1815 =
interrupt_pending_cur_priv == _theResult____h18531 ;
assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1826 =
interrupt_pending_cur_priv == _theResult____h18743 ;
assign interrupt_pending_cur_priv_EQ_IF_rg_mideleg_34_ETC___d1837 =
interrupt_pending_cur_priv == _theResult____h18955 ;
assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1752 =
interrupt_pending_cur_priv < _theResult____h17471 ;
assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1770 =
interrupt_pending_cur_priv < _theResult____h17683 ;
assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1781 =
interrupt_pending_cur_priv < _theResult____h17895 ;
assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1792 =
interrupt_pending_cur_priv < _theResult____h18107 ;
assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1803 =
interrupt_pending_cur_priv < _theResult____h18319 ;
assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1814 =
interrupt_pending_cur_priv < _theResult____h18531 ;
assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1825 =
interrupt_pending_cur_priv < _theResult____h18743 ;
assign interrupt_pending_cur_priv_ULT_IF_rg_mideleg_3_ETC___d1836 =
interrupt_pending_cur_priv < _theResult____h18955 ;
assign mask__h13813 = 64'd1 << ie_to_x__h13730 ;
assign mask__h13830 = 64'd1 << pie_to_x__h13731 ;
assign mask__h15895 = 64'd1 << pie_from_x__h15859 ;
assign mask__h15912 = 64'd1 << ie_from_x__h15858 ;
assign mav_csr_write_csr_addr_ULE_0x33F___d739 =
mav_csr_write_csr_addr <= 12'h33F ;
assign mav_csr_write_csr_addr_ULE_0xB1F___d735 =
mav_csr_write_csr_addr <= 12'hB1F ;
assign mav_csr_write_csr_addr_ULT_0x323_38_OR_NOT_mav_ETC___d951 =
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr != 12'h001 &&
mav_csr_write_csr_addr != 12'h002 &&
mav_csr_write_csr_addr != 12'h003 &&
mav_csr_write_csr_addr != 12'h100 &&
mav_csr_write_csr_addr != 12'h102 &&
mav_csr_write_csr_addr != 12'h103 &&
mav_csr_write_csr_addr != 12'h104 &&
mav_csr_write_csr_addr != 12'h105 &&
mav_csr_write_csr_addr != 12'h106 &&
mav_csr_write_csr_addr != 12'h140 &&
mav_csr_write_csr_addr != 12'h141 &&
mav_csr_write_csr_addr != 12'h142 &&
mav_csr_write_csr_addr != 12'h143 &&
mav_csr_write_csr_addr != 12'h144 &&
mav_csr_write_csr_addr != 12'h180 &&
mav_csr_write_csr_addr != 12'h302 &&
mav_csr_write_csr_addr != 12'h303 &&
mav_csr_write_csr_addr != 12'hF11 &&
mav_csr_write_csr_addr != 12'hF12 &&
mav_csr_write_csr_addr != 12'hF13 &&
mav_csr_write_csr_addr != 12'hF14 &&
mav_csr_write_csr_addr != 12'h300 &&
mav_csr_write_csr_addr != 12'h301 &&
mav_csr_write_csr_addr != 12'h304 &&
mav_csr_write_csr_addr != 12'h305 &&
mav_csr_write_csr_addr != 12'h306 &&
mav_csr_write_csr_addr != 12'h340 &&
mav_csr_write_csr_addr != 12'h341 &&
mav_csr_write_csr_addr != 12'h342 &&
mav_csr_write_csr_addr != 12'h343 &&
mav_csr_write_csr_addr != 12'h344 &&
mav_csr_write_csr_addr != 12'hB00 &&
mav_csr_write_csr_addr != 12'hB02 &&
mav_csr_write_csr_addr != 12'h7A0 &&
mav_csr_write_csr_addr != 12'h7A1 &&
mav_csr_write_csr_addr != 12'h7A2 &&
mav_csr_write_csr_addr != 12'h7A3 ;
assign mav_csr_write_csr_addr_ULT_0x323___d738 =
mav_csr_write_csr_addr < 12'h323 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d1022 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
(mav_csr_write_csr_addr == 12'h001 ||
mav_csr_write_csr_addr == 12'h002 ||
mav_csr_write_csr_addr == 12'h003) ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d746 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
(mav_csr_write_csr_addr == 12'h001 ||
mav_csr_write_csr_addr == 12'h003) ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d755 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
(mav_csr_write_csr_addr == 12'h001 ||
mav_csr_write_csr_addr == 12'h002 ||
mav_csr_write_csr_addr == 12'h003 ||
mav_csr_write_csr_addr == 12'h100 ||
mav_csr_write_csr_addr == 12'h300) ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d803 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
(mav_csr_write_csr_addr == 12'h002 ||
mav_csr_write_csr_addr == 12'h003) ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d808 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h104 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d810 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h105 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d815 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h140 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d817 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h141 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d821 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h142 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d826 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h143 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d828 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h144 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d830 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h180 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d832 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h302 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d839 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h303 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d842 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h304 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d844 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h305 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d846 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h306 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d848 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h340 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d850 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h341 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d852 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h342 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d854 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h343 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d856 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h344 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d860 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'hB02 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d862 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h7A0 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d864 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h7A1 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d868 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h7A2 ;
assign mav_csr_write_csr_addr_ULT_0xB03_34_OR_NOT_mav_ETC___d870 =
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
(mav_csr_write_csr_addr_ULT_0x323___d738 ||
!mav_csr_write_csr_addr_ULE_0x33F___d739) &&
mav_csr_write_csr_addr == 12'h7A3 ;
assign mav_csr_write_csr_addr_ULT_0xB03___d734 =
mav_csr_write_csr_addr < 12'hB03 ;
assign mav_csr_write_word_BITS_14_TO_13_68_EQ_0x3_69__ETC___d799 =
{ sd__h9247,
40'd5120,
(mav_csr_write_csr_addr == 12'h100) ?
fixed_up_val_23__h7818 :
fixed_up_val_23__h9248 } ;
assign new_csr_value__h10690 = { 4'd0, mav_csr_write_word[59:0] } ;
assign new_csr_value__h9962 = { mav_csr_write_word[63:1], 1'd0 } ;
assign new_priv__h13604 =
csr_trap_actions_nmi ?
2'b11 :
((csr_trap_actions_from_priv == 2'b11) ?
csr_trap_actions_from_priv :
_theResult___fst__h13742) ;
assign pie_from_x__h15859 = { 4'd1, csr_ret_actions_from_priv } ;
assign pie_to_x__h13731 = { 4'd1, new_priv__h13604 } ;
assign sd__h11438 = mv_update_mstatus_fs_fs == 2'h3 ;
assign sd__h11992 = ma_update_mstatus_fs_fs == 2'h3 ;
assign sd__h13652 =
IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1294[14:13] ==
2'h3 ;
assign sd__h15780 =
IF_csr_ret_actions_from_priv_EQ_0b11_476_THEN__ETC___d1496[14:13] ==
2'h3 ;
assign sd__h9247 = mav_csr_write_word[14:13] == 2'h3 ;
assign to_y__h16074 =
{ 1'b0,
csr_mstatus_rg_mstatus_03_AND_INV_1_SL_0_CONCA_ETC___d1489[8] } ;
assign v__h10003 =
{ mav_csr_write_word[63], 59'd0, mav_csr_write_word[3:0] } ;
assign v__h13609 = { sd__h13652, 40'd5120, fixed_up_val_23__h13653 } ;
assign v__h7767 =
{ sd__h9247,
43'd8192,
mav_csr_write_word[19:18],
3'd0,
mav_csr_write_word[14:13],
4'd0,
mav_csr_write_word[8],
2'd0,
mav_csr_write_word[5],
3'd0,
mav_csr_write_word[1],
1'd0 } ;
assign v__h9124 =
{ 48'd0,
mav_csr_write_word[15],
1'd0,
mav_csr_write_word[13:12],
2'd0,
mav_csr_write_word[9:0] } ;
assign v__h9160 = { 52'd0, mav_csr_write_word[11:0] } ;
assign v__h9770 =
{ mav_csr_write_word[63:2], 1'b0, mav_csr_write_word[0] } ;
assign val__h13814 = 64'd0 << ie_to_x__h13730 ;
assign val__h13831 = { 63'd0, b__h13829 } << pie_to_x__h13731 ;
assign val__h15913 = { 63'd0, b__h15911 } << ie_from_x__h15858 ;
assign vector_offset__h14794 = { 58'd0, csr_trap_actions_exc_code, 2'd0 } ;
assign wordxl1__h7197 = { 41'h10000001400, fixed_up_val_23__h7238 } ;
assign wordxl1__h9207 = { sd__h9247, 40'd5120, fixed_up_val_23__h9248 } ;
assign x__h12581 =
csr_trap_actions_interrupt_AND_NOT_csr_trap_ac_ETC___d1320 ?
exc_pc___1__h14867 :
exc_pc__h14793 ;
assign x__h13812 = x__h13842 | val__h13831 ;
assign x__h13825 = x__h13812 & y__h13826 ;
assign x__h13842 = csr_mstatus_rg_mstatus & y__h13843 ;
assign x__h15718 =
(csr_trap_actions_nmi || new_priv__h13604 == 2'b11) ?
v__h13609 :
y_avValue_fst__h14767 ;
assign x__h15719 =
{ !csr_trap_actions_nmi && csr_trap_actions_interrupt,
59'd0,
exc_code__h15560 } ;
assign x__h15894 = x__h15924 | val__h15913 ;
assign x__h15907 = x__h15894 & y__h15908 ;
assign x__h15924 = csr_mstatus_rg_mstatus & y__h15925 ;
assign x__h5601 =
(!mav_csr_write_csr_addr_ULT_0xB03___d734 &&
mav_csr_write_csr_addr_ULE_0xB1F___d735 ||
!mav_csr_write_csr_addr_ULT_0x323___d738 &&
mav_csr_write_csr_addr_ULE_0x33F___d739) ?
64'd0 :
y_avValue_fst__h11071 ;
assign y__h13826 = ~mask__h13813 ;
assign y__h13843 = ~mask__h13830 ;
assign y__h15908 = ~mask__h15895 ;
assign y__h15925 = ~mask__h15912 ;
assign y_avValue_fst__h10831 = { 59'd0, mav_csr_write_word[4:0] } ;
assign y_avValue_fst__h10836 = { 61'd0, mav_csr_write_word[2:0] } ;
assign y_avValue_fst__h10841 = { 56'd0, mav_csr_write_word[7:0] } ;
assign y_avValue_fst__h14750 =
{ sd__h13652,
43'd8192,
IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1294[19:18],
3'd0,
IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1294[14:13],
4'd0,
IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1294[8],
2'd0,
IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1294[5],
3'd0,
IF_IF_csr_trap_actions_nmi_THEN_0b11_ELSE_IF_c_ETC___d1294[1],
1'd0 } ;
assign y_avValue_fst__h14767 =
(new_priv__h13604 == 2'b01) ? y_avValue_fst__h14750 : v__h13609 ;
assign y_avValue_snd_snd__h14840 =
{ CASE_new_priv3604_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1,
2'd0 } ;
always@(mav_csr_write_csr_addr or
mav_csr_write_word or
y_avValue_fst__h10831 or
y_avValue_fst__h10836 or
y_avValue_fst__h10841 or
v__h7767 or
csr_mie$mav_sie_write or
v__h9770 or
new_csr_value__h9962 or
v__h10003 or
csr_mip$mav_sip_write or
wordxl1__h9207 or
v__h9124 or
v__h9160 or
csr_mie$mav_write or csr_mip$mav_write or new_csr_value__h10690)
begin
case (mav_csr_write_csr_addr)
12'h001: y_avValue_fst__h11071 = y_avValue_fst__h10831;
12'h002, 12'h306: y_avValue_fst__h11071 = y_avValue_fst__h10836;
12'h003: y_avValue_fst__h11071 = y_avValue_fst__h10841;
12'h100: y_avValue_fst__h11071 = v__h7767;
12'h102, 12'h103, 12'h106, 12'h7A0, 12'hF11, 12'hF12, 12'hF13, 12'hF14:
y_avValue_fst__h11071 = 64'd0;
12'h104: y_avValue_fst__h11071 = csr_mie$mav_sie_write;
12'h105, 12'h305: y_avValue_fst__h11071 = v__h9770;
12'h140, 12'h143, 12'h180, 12'h340, 12'h343, 12'hB00, 12'hB02:
y_avValue_fst__h11071 = mav_csr_write_word;
12'h141, 12'h341: y_avValue_fst__h11071 = new_csr_value__h9962;
12'h142, 12'h342: y_avValue_fst__h11071 = v__h10003;
12'h144: y_avValue_fst__h11071 = csr_mip$mav_sip_write;
12'h300: y_avValue_fst__h11071 = wordxl1__h9207;
12'h301: y_avValue_fst__h11071 = 64'h800000000014112D;
12'h302: y_avValue_fst__h11071 = v__h9124;
12'h303: y_avValue_fst__h11071 = v__h9160;
12'h304: y_avValue_fst__h11071 = csr_mie$mav_write;
12'h344: y_avValue_fst__h11071 = csr_mip$mav_write;
12'h7A1: y_avValue_fst__h11071 = new_csr_value__h10690;
default: y_avValue_fst__h11071 = mav_csr_write_word;
endcase
end
always@(new_priv__h13604 or rg_mtvec or rg_stvec)
begin
case (new_priv__h13604)
2'b01:
CASE_new_priv3604_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 =
rg_stvec[62:1];
2'b11:
CASE_new_priv3604_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 =
rg_mtvec[62:1];
default: CASE_new_priv3604_0b1_rg_stvec_BITS_62_TO_1_0b_ETC__q1 =
rg_mtvec[62:1];
endcase
end
always@(new_priv__h13604 or rg_mtvec or rg_stvec)
begin
case (new_priv__h13604)
2'b01:
CASE_new_priv3604_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 =
rg_stvec[0];
2'b11:
CASE_new_priv3604_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 =
rg_mtvec[0];
default: CASE_new_priv3604_0b1_rg_stvec_BIT_0_0b11_rg_m_ETC__q2 =
rg_mtvec[0];
endcase
end
always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus)
begin
case (interrupt_pending_cur_priv)
2'b0:
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1761 =
csr_mstatus_rg_mstatus[0];
2'b01:
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1761 =
csr_mstatus_rg_mstatus[1];
default: IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1761 =
interrupt_pending_cur_priv == 2'b11 &&
csr_mstatus_rg_mstatus[3];
endcase
end
always@(interrupt_pending_cur_priv or csr_mstatus_rg_mstatus)
begin
case (interrupt_pending_cur_priv)
2'b0:
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1864 =
!csr_mstatus_rg_mstatus[0];
2'b01:
IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1864 =
!csr_mstatus_rg_mstatus[1];
default: IF_interrupt_pending_cur_priv_EQ_0b0_754_THEN__ETC___d1864 =
interrupt_pending_cur_priv != 2'b11 ||
!csr_mstatus_rg_mstatus[3];
endcase
end
always@(read_csr_csr_addr or
rg_tdata3 or
rg_fflags or
rg_frm or
csr_mstatus_rg_mstatus or
csr_mie$mv_sie_read or
rg_stvec or
rg_sscratch or
rg_sepc or
rg_scause or
rg_stval or
csr_mip$mv_sip_read or
rg_satp or
rg_medeleg or
rg_mideleg or
csr_mie$mv_read or
rg_mtvec or
rg_mcounteren or
rg_mscratch or
rg_mepc or
rg_mcause or
rg_mtval or
csr_mip$mv_read or
rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret)
begin
case (read_csr_csr_addr)
12'h001:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
{ 59'd0, rg_fflags };
12'h002:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
{ 61'd0, rg_frm };
12'h003:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
{ 56'd0, rg_frm, rg_fflags };
12'h100:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
{ csr_mstatus_rg_mstatus[63],
29'd0,
csr_mstatus_rg_mstatus[33:32],
12'd0,
csr_mstatus_rg_mstatus[19:18],
1'd0,
csr_mstatus_rg_mstatus[16:13],
4'd0,
csr_mstatus_rg_mstatus[8],
2'd0,
csr_mstatus_rg_mstatus[5:4],
2'd0,
csr_mstatus_rg_mstatus[1:0] };
12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = 64'd0;
12'h104:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
csr_mie$mv_sie_read;
12'h105:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
{ rg_stvec[62:1], 1'b0, rg_stvec[0] };
12'h140:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
rg_sscratch;
12'h141:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_sepc;
12'h142:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
{ rg_scause[4], 59'd0, rg_scause[3:0] };
12'h143:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
rg_stval;
12'h144:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
csr_mip$mv_sip_read;
12'h180:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_satp;
12'h300:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
csr_mstatus_rg_mstatus;
12'h301:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
64'h800000000014112D;
12'h302:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
{ 48'd0, rg_medeleg };
12'h303:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
{ 52'd0, rg_mideleg };
12'h304:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
csr_mie$mv_read;
12'h305:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
{ rg_mtvec[62:1], 1'b0, rg_mtvec[0] };
12'h306:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
{ 61'd0, rg_mcounteren };
12'h340:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
rg_mscratch;
12'h341:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 = rg_mepc;
12'h342:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
{ rg_mcause[4], 59'd0, rg_mcause[3:0] };
12'h343:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
rg_mtval;
12'h344:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
csr_mip$mv_read;
12'h7A0:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
rg_tselect;
12'h7A1:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
rg_tdata1;
12'h7A2:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
rg_tdata2;
12'hB00, 12'hC00:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
rg_mcycle;
12'hB02, 12'hC02:
IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
rg_minstret;
default: IF_read_csr_csr_addr_EQ_0x1_0_THEN_0_CONCAT_rg_ETC___d291 =
rg_tdata3;
endcase
end
always@(mav_read_csr_csr_addr or
rg_tdata3 or
rg_fflags or
rg_frm or
csr_mstatus_rg_mstatus or
csr_mie$mv_sie_read or
rg_stvec or
rg_sscratch or
rg_sepc or
rg_scause or
rg_stval or
csr_mip$mv_sip_read or
rg_satp or
rg_medeleg or
rg_mideleg or
csr_mie$mv_read or
rg_mtvec or
rg_mcounteren or
rg_mscratch or
rg_mepc or
rg_mcause or
rg_mtval or
csr_mip$mv_read or
rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret)
begin
case (mav_read_csr_csr_addr)
12'h001:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
{ 59'd0, rg_fflags };
12'h002:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
{ 61'd0, rg_frm };
12'h003:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
{ 56'd0, rg_frm, rg_fflags };
12'h100:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
{ csr_mstatus_rg_mstatus[63],
29'd0,
csr_mstatus_rg_mstatus[33:32],
12'd0,
csr_mstatus_rg_mstatus[19:18],
1'd0,
csr_mstatus_rg_mstatus[16:13],
4'd0,
csr_mstatus_rg_mstatus[8],
2'd0,
csr_mstatus_rg_mstatus[5:4],
2'd0,
csr_mstatus_rg_mstatus[1:0] };
12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = 64'd0;
12'h104:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
csr_mie$mv_sie_read;
12'h105:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
{ rg_stvec[62:1], 1'b0, rg_stvec[0] };
12'h140:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
rg_sscratch;
12'h141:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_sepc;
12'h142:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
{ rg_scause[4], 59'd0, rg_scause[3:0] };
12'h143:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
rg_stval;
12'h144:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
csr_mip$mv_sip_read;
12'h180:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_satp;
12'h300:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
csr_mstatus_rg_mstatus;
12'h301:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
64'h800000000014112D;
12'h302:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
{ 48'd0, rg_medeleg };
12'h303:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
{ 52'd0, rg_mideleg };
12'h304:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
csr_mie$mv_read;
12'h305:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
{ rg_mtvec[62:1], 1'b0, rg_mtvec[0] };
12'h306:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
{ 61'd0, rg_mcounteren };
12'h340:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
rg_mscratch;
12'h341:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 = rg_mepc;
12'h342:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
{ rg_mcause[4], 59'd0, rg_mcause[3:0] };
12'h343:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
rg_mtval;
12'h344:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
csr_mip$mv_read;
12'h7A0:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
rg_tselect;
12'h7A1:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
rg_tdata1;
12'h7A2:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
rg_tdata2;
12'hB00, 12'hC00:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
rg_mcycle;
12'hB02, 12'hC02:
IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
rg_minstret;
default: IF_mav_read_csr_csr_addr_EQ_0x1_26_THEN_0_CONC_ETC___d731 =
rg_tdata3;
endcase
end
always@(read_csr_port2_csr_addr or
rg_tdata3 or
rg_fflags or
rg_frm or
csr_mstatus_rg_mstatus or
csr_mie$mv_sie_read or
rg_stvec or
rg_sscratch or
rg_sepc or
rg_scause or
rg_stval or
csr_mip$mv_sip_read or
rg_satp or
rg_medeleg or
rg_mideleg or
csr_mie$mv_read or
rg_mtvec or
rg_mcounteren or
rg_mscratch or
rg_mepc or
rg_mcause or
rg_mtval or
csr_mip$mv_read or
rg_tselect or rg_tdata1 or rg_tdata2 or rg_mcycle or rg_minstret)
begin
case (read_csr_port2_csr_addr)
12'h001:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
{ 59'd0, rg_fflags };
12'h002:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
{ 61'd0, rg_frm };
12'h003:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
{ 56'd0, rg_frm, rg_fflags };
12'h100:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
{ csr_mstatus_rg_mstatus[63],
29'd0,
csr_mstatus_rg_mstatus[33:32],
12'd0,
csr_mstatus_rg_mstatus[19:18],
1'd0,
csr_mstatus_rg_mstatus[16:13],
4'd0,
csr_mstatus_rg_mstatus[8],
2'd0,
csr_mstatus_rg_mstatus[5:4],
2'd0,
csr_mstatus_rg_mstatus[1:0] };
12'h102, 12'h103, 12'h106, 12'hF11, 12'hF12, 12'hF13, 12'hF14:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = 64'd0;
12'h104:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
csr_mie$mv_sie_read;
12'h105:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
{ rg_stvec[62:1], 1'b0, rg_stvec[0] };
12'h140:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
rg_sscratch;
12'h141:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_sepc;
12'h142:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
{ rg_scause[4], 59'd0, rg_scause[3:0] };
12'h143:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
rg_stval;
12'h144:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
csr_mip$mv_sip_read;
12'h180:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_satp;
12'h300:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
csr_mstatus_rg_mstatus;
12'h301:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
64'h800000000014112D;
12'h302:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
{ 48'd0, rg_medeleg };
12'h303:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
{ 52'd0, rg_mideleg };
12'h304:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
csr_mie$mv_read;
12'h305:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
{ rg_mtvec[62:1], 1'b0, rg_mtvec[0] };
12'h306:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
{ 61'd0, rg_mcounteren };
12'h340:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
rg_mscratch;
12'h341:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 = rg_mepc;
12'h342:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
{ rg_mcause[4], 59'd0, rg_mcause[3:0] };
12'h343:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
rg_mtval;
12'h344:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
csr_mip$mv_read;
12'h7A0:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
rg_tselect;
12'h7A1:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
rg_tdata1;
12'h7A2:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
rg_tdata2;
12'hB00, 12'hC00:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
rg_mcycle;
12'hB02, 12'hC02:
IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
rg_minstret;
default: IF_read_csr_port2_csr_addr_EQ_0x1_06_THEN_0_CO_ETC___d511 =
rg_tdata3;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY 64'h0000000A00002000;
rg_mcycle <= `BSV_ASSIGNMENT_DELAY 64'd0;
rg_minstret <= `BSV_ASSIGNMENT_DELAY 64'd0;
rg_nmi <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (csr_mstatus_rg_mstatus$EN)
csr_mstatus_rg_mstatus <= `BSV_ASSIGNMENT_DELAY
csr_mstatus_rg_mstatus$D_IN;
if (rg_mcycle$EN) rg_mcycle <= `BSV_ASSIGNMENT_DELAY rg_mcycle$D_IN;
if (rg_minstret$EN)
rg_minstret <= `BSV_ASSIGNMENT_DELAY rg_minstret$D_IN;
if (rg_nmi$EN) rg_nmi <= `BSV_ASSIGNMENT_DELAY rg_nmi$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
if (rg_dcsr$EN) rg_dcsr <= `BSV_ASSIGNMENT_DELAY rg_dcsr$D_IN;
if (rg_dpc$EN) rg_dpc <= `BSV_ASSIGNMENT_DELAY rg_dpc$D_IN;
if (rg_dscratch0$EN)
rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY rg_dscratch0$D_IN;
if (rg_dscratch1$EN)
rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY rg_dscratch1$D_IN;
if (rg_fflags$EN) rg_fflags <= `BSV_ASSIGNMENT_DELAY rg_fflags$D_IN;
if (rg_frm$EN) rg_frm <= `BSV_ASSIGNMENT_DELAY rg_frm$D_IN;
if (rg_mcause$EN) rg_mcause <= `BSV_ASSIGNMENT_DELAY rg_mcause$D_IN;
if (rg_mcounteren$EN)
rg_mcounteren <= `BSV_ASSIGNMENT_DELAY rg_mcounteren$D_IN;
if (rg_medeleg$EN) rg_medeleg <= `BSV_ASSIGNMENT_DELAY rg_medeleg$D_IN;
if (rg_mepc$EN) rg_mepc <= `BSV_ASSIGNMENT_DELAY rg_mepc$D_IN;
if (rg_mideleg$EN) rg_mideleg <= `BSV_ASSIGNMENT_DELAY rg_mideleg$D_IN;
if (rg_mscratch$EN) rg_mscratch <= `BSV_ASSIGNMENT_DELAY rg_mscratch$D_IN;
if (rg_mtval$EN) rg_mtval <= `BSV_ASSIGNMENT_DELAY rg_mtval$D_IN;
if (rg_mtvec$EN) rg_mtvec <= `BSV_ASSIGNMENT_DELAY rg_mtvec$D_IN;
if (rg_nmi_vector$EN)
rg_nmi_vector <= `BSV_ASSIGNMENT_DELAY rg_nmi_vector$D_IN;
if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN;
if (rg_scause$EN) rg_scause <= `BSV_ASSIGNMENT_DELAY rg_scause$D_IN;
if (rg_sepc$EN) rg_sepc <= `BSV_ASSIGNMENT_DELAY rg_sepc$D_IN;
if (rg_sscratch$EN) rg_sscratch <= `BSV_ASSIGNMENT_DELAY rg_sscratch$D_IN;
if (rg_stval$EN) rg_stval <= `BSV_ASSIGNMENT_DELAY rg_stval$D_IN;
if (rg_stvec$EN) rg_stvec <= `BSV_ASSIGNMENT_DELAY rg_stvec$D_IN;
if (rg_tdata1$EN) rg_tdata1 <= `BSV_ASSIGNMENT_DELAY rg_tdata1$D_IN;
if (rg_tdata2$EN) rg_tdata2 <= `BSV_ASSIGNMENT_DELAY rg_tdata2$D_IN;
if (rg_tdata3$EN) rg_tdata3 <= `BSV_ASSIGNMENT_DELAY rg_tdata3$D_IN;
if (rg_tselect$EN) rg_tselect <= `BSV_ASSIGNMENT_DELAY rg_tselect$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
csr_mstatus_rg_mstatus = 64'hAAAAAAAAAAAAAAAA;
rg_dcsr = 32'hAAAAAAAA;
rg_dpc = 64'hAAAAAAAAAAAAAAAA;
rg_dscratch0 = 64'hAAAAAAAAAAAAAAAA;
rg_dscratch1 = 64'hAAAAAAAAAAAAAAAA;
rg_fflags = 5'h0A;
rg_frm = 3'h2;
rg_mcause = 5'h0A;
rg_mcounteren = 3'h2;
rg_mcycle = 64'hAAAAAAAAAAAAAAAA;
rg_medeleg = 16'hAAAA;
rg_mepc = 64'hAAAAAAAAAAAAAAAA;
rg_mideleg = 12'hAAA;
rg_minstret = 64'hAAAAAAAAAAAAAAAA;
rg_mscratch = 64'hAAAAAAAAAAAAAAAA;
rg_mtval = 64'hAAAAAAAAAAAAAAAA;
rg_mtvec = 63'h2AAAAAAAAAAAAAAA;
rg_nmi = 1'h0;
rg_nmi_vector = 64'hAAAAAAAAAAAAAAAA;
rg_satp = 64'hAAAAAAAAAAAAAAAA;
rg_scause = 5'h0A;
rg_sepc = 64'hAAAAAAAAAAAAAAAA;
rg_sscratch = 64'hAAAAAAAAAAAAAAAA;
rg_state = 1'h0;
rg_stval = 64'hAAAAAAAAAAAAAAAA;
rg_stvec = 63'h2AAAAAAAAAAAAAAA;
rg_tdata1 = 64'hAAAAAAAAAAAAAAAA;
rg_tdata2 = 64'hAAAAAAAAAAAAAAAA;
rg_tdata3 = 64'hAAAAAAAAAAAAAAAA;
rg_tselect = 64'hAAAAAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_debug) $display("mstatus = 0x%0h", csr_mstatus_rg_mstatus);
if (RST_N != `BSV_RESET_VALUE)
if (EN_debug)
$display("sstatus = 0x%0h",
{ csr_mstatus_rg_mstatus[63],
29'd0,
csr_mstatus_rg_mstatus[33:32],
12'd0,
csr_mstatus_rg_mstatus[19:18],
1'd0,
csr_mstatus_rg_mstatus[16:13],
4'd0,
csr_mstatus_rg_mstatus[8],
2'd0,
csr_mstatus_rg_mstatus[5:4],
2'd0,
csr_mstatus_rg_mstatus[1:0] });
if (RST_N != `BSV_RESET_VALUE)
if (EN_debug) $display("mip = 0x%0h", csr_mip$mv_read);
if (RST_N != `BSV_RESET_VALUE)
if (EN_debug) $display("sip = 0x%0h", csr_mip$mv_sip_read);
if (RST_N != `BSV_RESET_VALUE)
if (EN_debug) $display("mie = 0x%0h", csr_mie$mv_read);
if (RST_N != `BSV_RESET_VALUE)
if (EN_debug) $display("sie = 0x%0h", csr_mie$mv_sie_read);
if (RST_N != `BSV_RESET_VALUE)
if (EN_mav_csr_write &&
(mav_csr_write_csr_addr_ULT_0xB03___d734 ||
!mav_csr_write_csr_addr_ULE_0xB1F___d735) &&
mav_csr_write_csr_addr_ULT_0x323_38_OR_NOT_mav_ETC___d951 &&
NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$display("%0d: ERROR: CSR-write addr 0x%0h val 0x%0h not successful",
rg_mcycle,
mav_csr_write_csr_addr,
mav_csr_write_word);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$display("%0d: CSR_Regfile.csr_trap_actions:", rg_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$display(" from priv %0d pc 0x%0h interrupt %0d exc_code %0d xtval 0x%0h",
csr_trap_actions_from_priv,
csr_trap_actions_pc,
csr_trap_actions_interrupt,
csr_trap_actions_exc_code,
csr_trap_actions_xtval);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" priv %0d: ", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" ip: 0x%0h", csr_mip$mv_read);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" ie: 0x%0h", csr_mie$mv_read);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" edeleg: 0x%0h", 16'd0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" ideleg: 0x%0h", 12'd0);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" cause:");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_scause[4] &&
rg_scause[3:0] == 4'd0)
$write("USER_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_scause[4] &&
rg_scause[3:0] == 4'd1)
$write("SUPERVISOR_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_scause[4] &&
rg_scause[3:0] == 4'd2)
$write("HYPERVISOR_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_scause[4] &&
rg_scause[3:0] == 4'd3)
$write("MACHINE_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_scause[4] &&
rg_scause[3:0] == 4'd4)
$write("USER_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_scause[4] &&
rg_scause[3:0] == 4'd5)
$write("SUPERVISOR_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_scause[4] &&
rg_scause[3:0] == 4'd6)
$write("HYPERVISOR_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_scause[4] &&
rg_scause[3:0] == 4'd7)
$write("MACHINE_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_scause[4] &&
rg_scause[3:0] == 4'd8)
$write("USER_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_scause[4] &&
rg_scause[3:0] == 4'd9)
$write("SUPERVISOR_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_scause[4] &&
rg_scause[3:0] == 4'd10)
$write("HYPERVISOR_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_scause[4] &&
rg_scause[3:0] == 4'd11)
$write("MACHINE_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_scause[4] &&
rg_scause[3:0] != 4'd0 &&
rg_scause[3:0] != 4'd1 &&
rg_scause[3:0] != 4'd2 &&
rg_scause[3:0] != 4'd3 &&
rg_scause[3:0] != 4'd4 &&
rg_scause[3:0] != 4'd5 &&
rg_scause[3:0] != 4'd6 &&
rg_scause[3:0] != 4'd7 &&
rg_scause[3:0] != 4'd8 &&
rg_scause[3:0] != 4'd9 &&
rg_scause[3:0] != 4'd10 &&
rg_scause[3:0] != 4'd11)
$write("unknown interrupt Exc_Code %d", rg_scause[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_scause[4] &&
rg_scause[3:0] == 4'd0)
$write("INSTRUCTION_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_scause[4] &&
rg_scause[3:0] == 4'd1)
$write("INSTRUCTION_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_scause[4] &&
rg_scause[3:0] == 4'd2)
$write("ILLEGAL_INSTRUCTION");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_scause[4] &&
rg_scause[3:0] == 4'd3)
$write("BREAKPOINT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_scause[4] &&
rg_scause[3:0] == 4'd4)
$write("LOAD_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_scause[4] &&
rg_scause[3:0] == 4'd5)
$write("LOAD_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_scause[4] &&
rg_scause[3:0] == 4'd6)
$write("STORE_AMO_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_scause[4] &&
rg_scause[3:0] == 4'd7)
$write("STORE_AMO_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_scause[4] &&
rg_scause[3:0] == 4'd8)
$write("ECALL_FROM_U");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_scause[4] &&
rg_scause[3:0] == 4'd9)
$write("ECALL_FROM_S");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_scause[4] &&
rg_scause[3:0] == 4'd11)
$write("ECALL_FROM_M");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_scause[4] &&
rg_scause[3:0] == 4'd12)
$write("INSTRUCTION_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_scause[4] &&
rg_scause[3:0] == 4'd13)
$write("LOAD_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_scause[4] &&
rg_scause[3:0] == 4'd15)
$write("STORE_AMO_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_scause[4] &&
rg_scause[3:0] != 4'd0 &&
rg_scause[3:0] != 4'd1 &&
rg_scause[3:0] != 4'd2 &&
rg_scause[3:0] != 4'd3 &&
rg_scause[3:0] != 4'd4 &&
rg_scause[3:0] != 4'd5 &&
rg_scause[3:0] != 4'd6 &&
rg_scause[3:0] != 4'd7 &&
rg_scause[3:0] != 4'd8 &&
rg_scause[3:0] != 4'd9 &&
rg_scause[3:0] != 4'd11 &&
rg_scause[3:0] != 4'd12 &&
rg_scause[3:0] != 4'd13 &&
rg_scause[3:0] != 4'd15)
$write("unknown trap Exc_Code %d", rg_scause[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" status: 0x%0h",
{ csr_mstatus_rg_mstatus[63],
29'd0,
csr_mstatus_rg_mstatus[33:32],
12'd0,
csr_mstatus_rg_mstatus[19:18],
1'd0,
csr_mstatus_rg_mstatus[16:13],
4'd0,
csr_mstatus_rg_mstatus[8],
2'd0,
csr_mstatus_rg_mstatus[5:4],
2'd0,
csr_mstatus_rg_mstatus[1:0] });
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" tvec: 0x%0h", { rg_stvec[62:1], 1'b0, rg_stvec[0] });
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" epc: 0x%0h", rg_sepc);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" tval: 0x%0h", rg_stval);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" priv %0d: ", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" ip: 0x%0h", csr_mip$mv_read);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" ie: 0x%0h", csr_mie$mv_read);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" edeleg: 0x%0h", rg_medeleg);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" ideleg: 0x%0h", rg_mideleg);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" cause:");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd0)
$write("USER_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd1)
$write("SUPERVISOR_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd2)
$write("HYPERVISOR_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd3)
$write("MACHINE_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd4)
$write("USER_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd5)
$write("SUPERVISOR_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd6)
$write("HYPERVISOR_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd7)
$write("MACHINE_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd8)
$write("USER_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd9)
$write("SUPERVISOR_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd10)
$write("HYPERVISOR_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_mcause[4] &&
rg_mcause[3:0] == 4'd11)
$write("MACHINE_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
rg_mcause[4] &&
rg_mcause[3:0] != 4'd0 &&
rg_mcause[3:0] != 4'd1 &&
rg_mcause[3:0] != 4'd2 &&
rg_mcause[3:0] != 4'd3 &&
rg_mcause[3:0] != 4'd4 &&
rg_mcause[3:0] != 4'd5 &&
rg_mcause[3:0] != 4'd6 &&
rg_mcause[3:0] != 4'd7 &&
rg_mcause[3:0] != 4'd8 &&
rg_mcause[3:0] != 4'd9 &&
rg_mcause[3:0] != 4'd10 &&
rg_mcause[3:0] != 4'd11)
$write("unknown interrupt Exc_Code %d", rg_mcause[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd0)
$write("INSTRUCTION_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd1)
$write("INSTRUCTION_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd2)
$write("ILLEGAL_INSTRUCTION");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd3)
$write("BREAKPOINT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd4)
$write("LOAD_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd5)
$write("LOAD_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd6)
$write("STORE_AMO_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd7)
$write("STORE_AMO_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd8)
$write("ECALL_FROM_U");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd9)
$write("ECALL_FROM_S");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd11)
$write("ECALL_FROM_M");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd12)
$write("INSTRUCTION_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd13)
$write("LOAD_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_mcause[4] &&
rg_mcause[3:0] == 4'd15)
$write("STORE_AMO_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!rg_mcause[4] &&
rg_mcause[3:0] != 4'd0 &&
rg_mcause[3:0] != 4'd1 &&
rg_mcause[3:0] != 4'd2 &&
rg_mcause[3:0] != 4'd3 &&
rg_mcause[3:0] != 4'd4 &&
rg_mcause[3:0] != 4'd5 &&
rg_mcause[3:0] != 4'd6 &&
rg_mcause[3:0] != 4'd7 &&
rg_mcause[3:0] != 4'd8 &&
rg_mcause[3:0] != 4'd9 &&
rg_mcause[3:0] != 4'd11 &&
rg_mcause[3:0] != 4'd12 &&
rg_mcause[3:0] != 4'd13 &&
rg_mcause[3:0] != 4'd15)
$write("unknown trap Exc_Code %d", rg_mcause[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" status: 0x%0h", csr_mstatus_rg_mstatus);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" tvec: 0x%0h", { rg_mtvec[62:1], 1'b0, rg_mtvec[0] });
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" epc: 0x%0h", rg_mepc);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" tval: 0x%0h", rg_mtval);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" Return: new pc 0x%0h ", x__h12581);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" new mstatus:");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write("MStatus{",
"sd:%0d",
x__h15718[14:13] == 2'h3 || x__h15718[16:15] == 2'h3);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" sxl:%0d uxl:%0d", x__h15718[35:34], x__h15718[33:32]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" tsr:%0d", x__h15718[22]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" tw:%0d", x__h15718[21]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" tvm:%0d", x__h15718[20]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" mxr:%0d", x__h15718[19]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" sum:%0d", x__h15718[18]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" mprv:%0d", x__h15718[17]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" xs:%0d", x__h15718[16:15]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" fs:%0d", x__h15718[14:13]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" mpp:%0d", x__h15718[12:11]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" spp:%0d", x__h15718[8]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" pies:%0d_%0d%0d", x__h15718[7], x__h15718[5], x__h15718[4]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" ies:%0d_%0d%0d", x__h15718[3], x__h15718[1], x__h15718[0]);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write("}");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" new xcause:");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h15560 == 4'd0)
$write("USER_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h15560 == 4'd1)
$write("SUPERVISOR_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h15560 == 4'd2)
$write("HYPERVISOR_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h15560 == 4'd3)
$write("MACHINE_SW_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h15560 == 4'd4)
$write("USER_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h15560 == 4'd5)
$write("SUPERVISOR_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h15560 == 4'd6)
$write("HYPERVISOR_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h15560 == 4'd7)
$write("MACHINE_TIMER_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h15560 == 4'd8)
$write("USER_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h15560 == 4'd9)
$write("SUPERVISOR_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h15560 == 4'd10)
$write("HYPERVISOR_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
!csr_trap_actions_nmi &&
csr_trap_actions_interrupt &&
exc_code__h15560 == 4'd11)
$write("MACHINE_EXTERNAL_INTERRUPT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
NOT_csr_trap_actions_nmi_311_AND_csr_trap_acti_ETC___d1421)
$write("unknown interrupt Exc_Code %d", exc_code__h15560);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h15560 == 4'd0)
$write("INSTRUCTION_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h15560 == 4'd1)
$write("INSTRUCTION_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h15560 == 4'd2)
$write("ILLEGAL_INSTRUCTION");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h15560 == 4'd3)
$write("BREAKPOINT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h15560 == 4'd4)
$write("LOAD_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h15560 == 4'd5)
$write("LOAD_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h15560 == 4'd6)
$write("STORE_AMO_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h15560 == 4'd7)
$write("STORE_AMO_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h15560 == 4'd8)
$write("ECALL_FROM_U");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h15560 == 4'd9)
$write("ECALL_FROM_S");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h15560 == 4'd11)
$write("ECALL_FROM_M");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h15560 == 4'd12)
$write("INSTRUCTION_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h15560 == 4'd13)
$write("LOAD_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
(csr_trap_actions_nmi || !csr_trap_actions_interrupt) &&
exc_code__h15560 == 4'd15)
$write("STORE_AMO_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955 &&
csr_trap_actions_nmi_OR_NOT_csr_trap_actions_i_ETC___d1472)
$write("unknown trap Exc_Code %d", exc_code__h15560);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$write(" new priv %0d", new_priv__h13604);
if (RST_N != `BSV_RESET_VALUE)
if (EN_csr_trap_actions && NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$display("%0d: CSR_RegFile: m_external_interrupt_req: %x",
rg_mcycle,
m_external_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$display("%0d: CSR_RegFile: s_external_interrupt_req: %x",
rg_mcycle,
s_external_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$display("%0d: CSR_RegFile: timer_interrupt_req: %x",
rg_mcycle,
timer_interrupt_req_set_not_clear);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_cfg_verbosity_read__53_ULE_1_54___d955)
$display("%0d: CSR_RegFile: software_interrupt_req: %x",
rg_mcycle,
software_interrupt_req_set_not_clear);
end
// synopsys translate_on
endmodule // mkCSR_RegFile
|
/* Top level module for button demo without debouncing
(not a good way of doing things!)
This uses button 1 of the keypad when installed correctly.
*/
module top (
// input hardware clock (12 MHz)
hwclk,
// LED
led1,
// Keypad lines
keypad_r1,
keypad_c1,
);
/* Clock input */
input hwclk;
/* LED outputs */
output led1;
/* Numpad I/O */
output keypad_r1=0;
input keypad_c1;
/* LED register */
reg ledval = 1'b0;
/* Numpad pull-up settings for columns:
PIN_TYPE: <output_type=0>_<input=1>
PULLUP: <enable=1>
PACKAGE_PIN: <user pad name>
D_IN_0: <internal pin wire (data in)>
*/
wire keypad_c1_din;
SB_IO #(
.PIN_TYPE(6'b0000_01),
.PULLUP(1'b1)
) keypad_c1_config (
.PACKAGE_PIN(keypad_c1),
.D_IN_0(keypad_c1_din)
);
/* LED Wiring */
assign led1=ledval;
/* Toggle LED when button [1] pressed */
always @ (negedge keypad_c1_din) begin
ledval = ~ledval;
end
endmodule |
`timescale 1ns / 1ps
`define SIMULATION
module peripheral_mult_TB;
reg clk;
reg rst;
reg reset;
reg start;
reg [15:0]d_in;
reg cs;
reg [1:0]addr;
reg rd;
reg wr;
wire [15:0]d_out;
peripheral uut (.clk(clk) , .rst(rst) , .d_in(d_in) , .cs(cs) , .addr(addr) , .rd(rd) , .wr(wr), .d_out(d_out) );
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
reg [20:0] i;
event reset_trigger;
initial begin // Initialize Inputs
clk = 0; reset = 1; start = 0; d_in = 16'd0035; addr = 16'h0000; cs=1; rd=0; wr=1;
end
initial begin // Process for clk
#OFFSET;
forever
begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin // Reset the system, Start the image capture process
forever begin
@ (reset_trigger);
@ (posedge clk);
start = 0;
@ (posedge clk);
start = 1;
for(i=0; i<2; i=i+1) begin
@ (posedge clk);
end
start = 0;
// stimulus here
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'd0005; //envio A
addr = 16'h0000;
cs=1; rd=0; wr=1;
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'd0002; //envio B
addr = 16'h0001;
cs=1; rd=0; wr=1;
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'd0001; //envio init
addr = 16'h0002;
cs=1; rd=0; wr=1;
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'd0000; //recibo dato
addr = 16'h0002;
cs=0; rd=1; wr=0;
end
end
initial begin: TEST_CASE
$dumpfile("peripheral_mult_TB.vcd");
$dumpvars(-1, uut);
#10 -> reset_trigger;
#((PERIOD*DUTY_CYCLE)*200) $finish;
end
endmodule
|
module mapper_noc(clk, rst, data_in, data_in_ready, fifo_in_ready, data_out, data_out_ready);
parameter IDLE = 4'b0000;
parameter IDLE1 = 4'b1111;
parameter KEYWORD = 4'b0001;
parameter TEXTFILE = 4'b0010;
parameter TEXTFILE_1 = 4'b0011;
parameter PAIR_NUM = 10;
input clk;
input rst;
input [31:0] data_in;
input data_in_ready;
input fifo_in_ready; // mapper can write to router when fifo_in_ready==1
output reg [31:0] data_out;
output reg data_out_ready;
reg [31:0] text_in;
wire [31:0] keyword_in;
reg [31:0] keyword_in_reg;
wire [31:0] pair;
wire pair_out;
reg pair_out_reg;
reg [127:0] pair_reg [PAIR_NUM-1:0]; // Store at most 10 pairs now.
reg [4:0] i; // Index the pair_reg
reg [4:0] pair_reg_index;
reg [4:0] pair_reg_index_1;
reg [2:0] pair_reg_counter;
reg [2:0] pair_reg_counter_1;
reg [3:0] current_state;
reg [3:0] next_state;
reg [2:0] key_counter; // Counter keyword reception for 4 cycles.
reg key_en;
reg text_en;
reg [127:0] mem [128:0];
reg [31:0] pt_in;
reg [31:0] pt_out;
reg data_wr;
reg [2:0] data_wr_counter;
always@(posedge clk or negedge rst)
if(!rst) begin
data_out <= 0;
data_out_ready <= 0;
pair_reg_index_1 <= 0;
pair_reg_counter_1 <= 0;
end
else if(pair_reg_index_1<pair_reg_index && fifo_in_ready==1) begin
data_out_ready <= 1;
case(pair_reg_counter_1)
0: begin
data_out <= pair_reg[pair_reg_index_1][31:0];
pair_reg_counter_1 <= 1;
end
1: begin
data_out <= pair_reg[pair_reg_index_1][63:32];
pair_reg_counter_1 <= 2;
end
2: begin
data_out <= pair_reg[pair_reg_index_1][95:64];
pair_reg_counter_1 <= 3;
end
3: begin
data_out <= pair_reg[pair_reg_index_1][127:96];
pair_reg_index_1 <= pair_reg_index_1 + 1;
pair_reg_counter_1 <= 0;
end
default: begin
end
endcase
end
else begin
data_out_ready <= 0;
data_out <= 0;
end
always@(posedge clk or negedge rst)
if(!rst)
pair_out_reg <= 0;
else
pair_out_reg <= pair_out;
always@(posedge clk or negedge rst)
if(!rst) begin
for(i=0; i<PAIR_NUM; i=i+1)
pair_reg[i] <= 0;
pair_reg_counter <= 0;
pair_reg_index <= 0;
end
else if(pair_out_reg == 1) begin
case(pair_reg_counter)
0: begin
pair_reg[pair_reg_index][31:0] <= pair;
pair_reg_counter <= 1;
end
1: begin
pair_reg[pair_reg_index][63:32] <= pair;
pair_reg_counter <= 2;
end
2: begin
pair_reg[pair_reg_index][95:64] <= pair;
pair_reg_counter <= 3;
end
3: begin
pair_reg[pair_reg_index][127:96] <= pair;
pair_reg_counter <= 0;
pair_reg_index <= pair_reg_index + 1;
end
default: begin
pair_reg[pair_reg_index] <= pair_reg[pair_reg_index];
end
endcase
//pair_reg_index <= pair_reg_index + 1;
end
else
pair_reg[pair_reg_index] <= pair_reg[pair_reg_index];
/*always@(posedge clk or negedge rst)
if(!rst) begin
data_out <= 0;
data_out_ready <= 0;
end
else if(fifo_in_ready==1) begin
data_out <= 0;
data_out_ready <= 0;
end
else begin
end */
assign keyword_in = (key_en == 1'b1)?keyword_in_reg:32'bz;
always@(posedge clk or negedge rst)
if(!rst)
current_state <= IDLE;
else
current_state <= next_state;
always@*
case(current_state)
IDLE: begin
if(data_in_ready == 1'b1) next_state = IDLE1;
else next_state = IDLE;
end
IDLE1: begin
next_state = KEYWORD;
end
KEYWORD: begin
if(key_counter == 3) next_state = TEXTFILE;
else next_state = KEYWORD;
end
TEXTFILE: begin
if( pt_out==pt_in && pt_in!=0 ) next_state = TEXTFILE_1;
else next_state = TEXTFILE;
end
TEXTFILE_1: begin
end
default: begin
next_state = IDLE;
end
endcase
always@(posedge clk)
case(current_state)
IDLE: begin
key_counter <= 0;
key_en <= 0;
text_en <= 0;
pt_in <= 0;
pt_out <= 0;
data_wr_counter <= 0;
end
IDLE1: begin
end
KEYWORD: begin
key_counter <= key_counter + 1'd1;
key_en <= 1;
keyword_in_reg <= data_in[31:0];
end
TEXTFILE: begin
key_en <= 0;
text_en <= 1;
if(data_in_ready == 1)
mem[pt_in] <= data_in;
else begin
end
if(data_in_ready==1 && pt_in < 1024) begin
pt_in <= pt_in + 1;
end
else if(pt_in < 1024) begin
pt_in <= pt_in;
end
else begin
pt_in <= 0;
end
if(data_wr_counter == 6) begin
data_wr_counter <=0;
end
else if(data_wr_counter == 1) begin
data_wr <= 1'b1;
data_wr_counter <= data_wr_counter + 1;
text_in <= mem[pt_out];
pt_out <= pt_out + 1;
end
else if(data_wr_counter == 2) begin
data_wr <= 1'b0;
data_wr_counter <= data_wr_counter + 1;
end
else
data_wr_counter <= data_wr_counter + 1;
end
default: begin
end
endcase
mapper mapper0(
.clk(clk),
.rst(rst),
.data_in_1(text_in),
.keyword(keyword_in),
.key_en(key_en),
.data_wr(data_wr),
.write_free(),
.pair(pair),
//.pair_out(pair_out),
.pair_out(pair_out));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221A_2_V
`define SKY130_FD_SC_LS__O221A_2_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o221a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o221a_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o221a_2 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221A_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MAJ3_SYMBOL_V
`define SKY130_FD_SC_HS__MAJ3_SYMBOL_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__maj3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MAJ3_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
////////////////////////////////////////////////////////////////////////////////
//
// Module Common Logic CBCC
// Generated by Xilinx Aurora 64B66B
`timescale 1 ps / 1 ps
`define DLY #1
(* DowngradeIPIdentifiedWarnings="yes" *)
//***********************************Entity Declaration*******************************
module aurora_64b66b_25p4G_common_logic_cbcc #
(
parameter BACKWARD_COMP_MODE1 = 1'b0 //disable check for interCB gap
)
(
input start_cb_writes_in,
input do_rd_en_in,
input bit_err_chan_bond_in,
input final_gater_for_fifo_din_in,
input any_vld_btf_in,
input cbcc_fifo_reset_wr_clk,
input cbcc_fifo_reset_rd_clk,
output reg all_start_cb_writes_out,
output reg master_do_rd_en_out,
output reg cb_bit_err_out,
output reg all_vld_btf_out,
input rxrecclk_to_fabric,
input rxusrclk2_in
);
//********************************* Reg declaration **************************
reg second_cb_write_failed =1'b0;
//********************************* Main Body of Code**************************
always @(posedge rxrecclk_to_fabric)
begin
if(cbcc_fifo_reset_wr_clk)
begin
all_start_cb_writes_out <= `DLY 1'b0;
end
else
begin
all_start_cb_writes_out <= `DLY start_cb_writes_in;
end
end
always @(posedge rxrecclk_to_fabric)
begin
if(cbcc_fifo_reset_wr_clk)
begin
all_vld_btf_out <= `DLY 1'b0;
end
else
begin
all_vld_btf_out <= `DLY any_vld_btf_in;
end
end
always @(posedge rxusrclk2_in)
begin
if(cbcc_fifo_reset_rd_clk)
begin
master_do_rd_en_out <= `DLY 1'b0;
end
else
begin
master_do_rd_en_out <= `DLY do_rd_en_in;
end
end
always @(posedge rxrecclk_to_fabric)
begin
if(cbcc_fifo_reset_wr_clk)
second_cb_write_failed <= `DLY 1'b0;
else
second_cb_write_failed <= bit_err_chan_bond_in;
end
always @(posedge rxrecclk_to_fabric)
begin
if(cbcc_fifo_reset_wr_clk)
cb_bit_err_out <= `DLY 1'b0;
else
cb_bit_err_out <= (BACKWARD_COMP_MODE1) ? 1'b0 : second_cb_write_failed ;
end
endmodule
|
// nios_system.v
// Generated using ACDS version 14.1 186 at 2016.05.04.10:35:16
`timescale 1 ps / 1 ps
module nios_system (
output wire [31:0] alu_a_export, // alu_a.export
output wire [31:0] alu_b_export, // alu_b.export
input wire alu_carry_out_export, // alu_carry_out.export
output wire [2:0] alu_control_export, // alu_control.export
input wire alu_negative_export, // alu_negative.export
input wire [31:0] alu_out_export, // alu_out.export
input wire alu_overflow_export, // alu_overflow.export
input wire alu_zero_export, // alu_zero.export
input wire clk_clk, // clk.clk
output wire [3:0] hex_0_export, // hex_0.export
output wire [3:0] hex_1_export, // hex_1.export
output wire [3:0] hex_2_export, // hex_2.export
output wire [3:0] hex_3_export, // hex_3.export
output wire [3:0] hex_4_export, // hex_4.export
output wire [3:0] hex_5_export, // hex_5.export
input wire [3:0] keys_export, // keys.export
output wire [9:0] leds_export, // leds.export
output wire [31:0] regfile_data_export, // regfile_data.export
output wire [5:0] regfile_r1sel_export, // regfile_r1sel.export
output wire [5:0] regfile_r2sel_export, // regfile_r2sel.export
input wire [31:0] regfile_reg1_export, // regfile_reg1.export
input wire [31:0] regfile_reg2_export, // regfile_reg2.export
output wire regfile_we_export, // regfile_we.export
output wire [5:0] regfile_wsel_export, // regfile_wsel.export
input wire reset_reset_n, // reset.reset_n
output wire [10:0] sram_addr_export, // sram_addr.export
output wire sram_cs_export, // sram_cs.export
inout wire [15:0] sram_data_in_export, // sram_data_in.export
output wire sram_oe_export, // sram_oe.export
output wire sram_read_write_export, // sram_read_write.export
input wire [9:0] switches_export // switches.export
);
wire [31:0] nios2_qsys_0_data_master_readdata; // mm_interconnect_0:nios2_qsys_0_data_master_readdata -> nios2_qsys_0:d_readdata
wire nios2_qsys_0_data_master_waitrequest; // mm_interconnect_0:nios2_qsys_0_data_master_waitrequest -> nios2_qsys_0:d_waitrequest
wire nios2_qsys_0_data_master_debugaccess; // nios2_qsys_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_qsys_0_data_master_debugaccess
wire [18:0] nios2_qsys_0_data_master_address; // nios2_qsys_0:d_address -> mm_interconnect_0:nios2_qsys_0_data_master_address
wire [3:0] nios2_qsys_0_data_master_byteenable; // nios2_qsys_0:d_byteenable -> mm_interconnect_0:nios2_qsys_0_data_master_byteenable
wire nios2_qsys_0_data_master_read; // nios2_qsys_0:d_read -> mm_interconnect_0:nios2_qsys_0_data_master_read
wire nios2_qsys_0_data_master_write; // nios2_qsys_0:d_write -> mm_interconnect_0:nios2_qsys_0_data_master_write
wire [31:0] nios2_qsys_0_data_master_writedata; // nios2_qsys_0:d_writedata -> mm_interconnect_0:nios2_qsys_0_data_master_writedata
wire [31:0] nios2_qsys_0_instruction_master_readdata; // mm_interconnect_0:nios2_qsys_0_instruction_master_readdata -> nios2_qsys_0:i_readdata
wire nios2_qsys_0_instruction_master_waitrequest; // mm_interconnect_0:nios2_qsys_0_instruction_master_waitrequest -> nios2_qsys_0:i_waitrequest
wire [18:0] nios2_qsys_0_instruction_master_address; // nios2_qsys_0:i_address -> mm_interconnect_0:nios2_qsys_0_instruction_master_address
wire nios2_qsys_0_instruction_master_read; // nios2_qsys_0:i_read -> mm_interconnect_0:nios2_qsys_0_instruction_master_read
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata; // jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest; // jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> jtag_uart_0:av_read_n
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> jtag_uart_0:av_write_n
wire [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
wire [31:0] mm_interconnect_0_nios2_qsys_0_debug_mem_slave_readdata; // nios2_qsys_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_qsys_0_debug_mem_slave_readdata
wire mm_interconnect_0_nios2_qsys_0_debug_mem_slave_waitrequest; // nios2_qsys_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_qsys_0_debug_mem_slave_waitrequest
wire mm_interconnect_0_nios2_qsys_0_debug_mem_slave_debugaccess; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_debugaccess -> nios2_qsys_0:debug_mem_slave_debugaccess
wire [8:0] mm_interconnect_0_nios2_qsys_0_debug_mem_slave_address; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_address -> nios2_qsys_0:debug_mem_slave_address
wire mm_interconnect_0_nios2_qsys_0_debug_mem_slave_read; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_read -> nios2_qsys_0:debug_mem_slave_read
wire [3:0] mm_interconnect_0_nios2_qsys_0_debug_mem_slave_byteenable; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_byteenable -> nios2_qsys_0:debug_mem_slave_byteenable
wire mm_interconnect_0_nios2_qsys_0_debug_mem_slave_write; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_write -> nios2_qsys_0:debug_mem_slave_write
wire [31:0] mm_interconnect_0_nios2_qsys_0_debug_mem_slave_writedata; // mm_interconnect_0:nios2_qsys_0_debug_mem_slave_writedata -> nios2_qsys_0:debug_mem_slave_writedata
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [14:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire [3:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire mm_interconnect_0_leds_s1_chipselect; // mm_interconnect_0:LEDs_s1_chipselect -> LEDs:chipselect
wire [31:0] mm_interconnect_0_leds_s1_readdata; // LEDs:readdata -> mm_interconnect_0:LEDs_s1_readdata
wire [1:0] mm_interconnect_0_leds_s1_address; // mm_interconnect_0:LEDs_s1_address -> LEDs:address
wire mm_interconnect_0_leds_s1_write; // mm_interconnect_0:LEDs_s1_write -> LEDs:write_n
wire [31:0] mm_interconnect_0_leds_s1_writedata; // mm_interconnect_0:LEDs_s1_writedata -> LEDs:writedata
wire [31:0] mm_interconnect_0_switches_s1_readdata; // switches:readdata -> mm_interconnect_0:switches_s1_readdata
wire [1:0] mm_interconnect_0_switches_s1_address; // mm_interconnect_0:switches_s1_address -> switches:address
wire mm_interconnect_0_sram_data_s1_chipselect; // mm_interconnect_0:sram_data_s1_chipselect -> sram_data:chipselect
wire [31:0] mm_interconnect_0_sram_data_s1_readdata; // sram_data:readdata -> mm_interconnect_0:sram_data_s1_readdata
wire [1:0] mm_interconnect_0_sram_data_s1_address; // mm_interconnect_0:sram_data_s1_address -> sram_data:address
wire mm_interconnect_0_sram_data_s1_write; // mm_interconnect_0:sram_data_s1_write -> sram_data:write_n
wire [31:0] mm_interconnect_0_sram_data_s1_writedata; // mm_interconnect_0:sram_data_s1_writedata -> sram_data:writedata
wire mm_interconnect_0_sram_addr_s1_chipselect; // mm_interconnect_0:sram_addr_s1_chipselect -> sram_addr:chipselect
wire [31:0] mm_interconnect_0_sram_addr_s1_readdata; // sram_addr:readdata -> mm_interconnect_0:sram_addr_s1_readdata
wire [1:0] mm_interconnect_0_sram_addr_s1_address; // mm_interconnect_0:sram_addr_s1_address -> sram_addr:address
wire mm_interconnect_0_sram_addr_s1_write; // mm_interconnect_0:sram_addr_s1_write -> sram_addr:write_n
wire [31:0] mm_interconnect_0_sram_addr_s1_writedata; // mm_interconnect_0:sram_addr_s1_writedata -> sram_addr:writedata
wire mm_interconnect_0_sram_read_write_s1_chipselect; // mm_interconnect_0:sram_read_write_s1_chipselect -> sram_read_write:chipselect
wire [31:0] mm_interconnect_0_sram_read_write_s1_readdata; // sram_read_write:readdata -> mm_interconnect_0:sram_read_write_s1_readdata
wire [1:0] mm_interconnect_0_sram_read_write_s1_address; // mm_interconnect_0:sram_read_write_s1_address -> sram_read_write:address
wire mm_interconnect_0_sram_read_write_s1_write; // mm_interconnect_0:sram_read_write_s1_write -> sram_read_write:write_n
wire [31:0] mm_interconnect_0_sram_read_write_s1_writedata; // mm_interconnect_0:sram_read_write_s1_writedata -> sram_read_write:writedata
wire mm_interconnect_0_sram_cs_s1_chipselect; // mm_interconnect_0:sram_cs_s1_chipselect -> sram_cs:chipselect
wire [31:0] mm_interconnect_0_sram_cs_s1_readdata; // sram_cs:readdata -> mm_interconnect_0:sram_cs_s1_readdata
wire [1:0] mm_interconnect_0_sram_cs_s1_address; // mm_interconnect_0:sram_cs_s1_address -> sram_cs:address
wire mm_interconnect_0_sram_cs_s1_write; // mm_interconnect_0:sram_cs_s1_write -> sram_cs:write_n
wire [31:0] mm_interconnect_0_sram_cs_s1_writedata; // mm_interconnect_0:sram_cs_s1_writedata -> sram_cs:writedata
wire mm_interconnect_0_sram_oe_s1_chipselect; // mm_interconnect_0:sram_oe_s1_chipselect -> sram_oe:chipselect
wire [31:0] mm_interconnect_0_sram_oe_s1_readdata; // sram_oe:readdata -> mm_interconnect_0:sram_oe_s1_readdata
wire [1:0] mm_interconnect_0_sram_oe_s1_address; // mm_interconnect_0:sram_oe_s1_address -> sram_oe:address
wire mm_interconnect_0_sram_oe_s1_write; // mm_interconnect_0:sram_oe_s1_write -> sram_oe:write_n
wire [31:0] mm_interconnect_0_sram_oe_s1_writedata; // mm_interconnect_0:sram_oe_s1_writedata -> sram_oe:writedata
wire mm_interconnect_0_regfile_data_s1_chipselect; // mm_interconnect_0:regfile_data_s1_chipselect -> regfile_data:chipselect
wire [31:0] mm_interconnect_0_regfile_data_s1_readdata; // regfile_data:readdata -> mm_interconnect_0:regfile_data_s1_readdata
wire [1:0] mm_interconnect_0_regfile_data_s1_address; // mm_interconnect_0:regfile_data_s1_address -> regfile_data:address
wire mm_interconnect_0_regfile_data_s1_write; // mm_interconnect_0:regfile_data_s1_write -> regfile_data:write_n
wire [31:0] mm_interconnect_0_regfile_data_s1_writedata; // mm_interconnect_0:regfile_data_s1_writedata -> regfile_data:writedata
wire [31:0] mm_interconnect_0_regfile_reg1_s1_readdata; // regfile_reg1:readdata -> mm_interconnect_0:regfile_reg1_s1_readdata
wire [1:0] mm_interconnect_0_regfile_reg1_s1_address; // mm_interconnect_0:regfile_reg1_s1_address -> regfile_reg1:address
wire [31:0] mm_interconnect_0_regfile_reg2_s1_readdata; // regfile_reg2:readdata -> mm_interconnect_0:regfile_reg2_s1_readdata
wire [1:0] mm_interconnect_0_regfile_reg2_s1_address; // mm_interconnect_0:regfile_reg2_s1_address -> regfile_reg2:address
wire mm_interconnect_0_regfile_r1sel_s1_chipselect; // mm_interconnect_0:regfile_r1sel_s1_chipselect -> regfile_r1sel:chipselect
wire [31:0] mm_interconnect_0_regfile_r1sel_s1_readdata; // regfile_r1sel:readdata -> mm_interconnect_0:regfile_r1sel_s1_readdata
wire [1:0] mm_interconnect_0_regfile_r1sel_s1_address; // mm_interconnect_0:regfile_r1sel_s1_address -> regfile_r1sel:address
wire mm_interconnect_0_regfile_r1sel_s1_write; // mm_interconnect_0:regfile_r1sel_s1_write -> regfile_r1sel:write_n
wire [31:0] mm_interconnect_0_regfile_r1sel_s1_writedata; // mm_interconnect_0:regfile_r1sel_s1_writedata -> regfile_r1sel:writedata
wire mm_interconnect_0_regfile_r2sel_s1_chipselect; // mm_interconnect_0:regfile_r2sel_s1_chipselect -> regfile_r2sel:chipselect
wire [31:0] mm_interconnect_0_regfile_r2sel_s1_readdata; // regfile_r2sel:readdata -> mm_interconnect_0:regfile_r2sel_s1_readdata
wire [1:0] mm_interconnect_0_regfile_r2sel_s1_address; // mm_interconnect_0:regfile_r2sel_s1_address -> regfile_r2sel:address
wire mm_interconnect_0_regfile_r2sel_s1_write; // mm_interconnect_0:regfile_r2sel_s1_write -> regfile_r2sel:write_n
wire [31:0] mm_interconnect_0_regfile_r2sel_s1_writedata; // mm_interconnect_0:regfile_r2sel_s1_writedata -> regfile_r2sel:writedata
wire mm_interconnect_0_regfile_wsel_s1_chipselect; // mm_interconnect_0:regfile_wsel_s1_chipselect -> regfile_wsel:chipselect
wire [31:0] mm_interconnect_0_regfile_wsel_s1_readdata; // regfile_wsel:readdata -> mm_interconnect_0:regfile_wsel_s1_readdata
wire [1:0] mm_interconnect_0_regfile_wsel_s1_address; // mm_interconnect_0:regfile_wsel_s1_address -> regfile_wsel:address
wire mm_interconnect_0_regfile_wsel_s1_write; // mm_interconnect_0:regfile_wsel_s1_write -> regfile_wsel:write_n
wire [31:0] mm_interconnect_0_regfile_wsel_s1_writedata; // mm_interconnect_0:regfile_wsel_s1_writedata -> regfile_wsel:writedata
wire mm_interconnect_0_regfile_we_s1_chipselect; // mm_interconnect_0:regfile_we_s1_chipselect -> regfile_we:chipselect
wire [31:0] mm_interconnect_0_regfile_we_s1_readdata; // regfile_we:readdata -> mm_interconnect_0:regfile_we_s1_readdata
wire [1:0] mm_interconnect_0_regfile_we_s1_address; // mm_interconnect_0:regfile_we_s1_address -> regfile_we:address
wire mm_interconnect_0_regfile_we_s1_write; // mm_interconnect_0:regfile_we_s1_write -> regfile_we:write_n
wire [31:0] mm_interconnect_0_regfile_we_s1_writedata; // mm_interconnect_0:regfile_we_s1_writedata -> regfile_we:writedata
wire mm_interconnect_0_hex_0_s1_chipselect; // mm_interconnect_0:hex_0_s1_chipselect -> hex_0:chipselect
wire [31:0] mm_interconnect_0_hex_0_s1_readdata; // hex_0:readdata -> mm_interconnect_0:hex_0_s1_readdata
wire [1:0] mm_interconnect_0_hex_0_s1_address; // mm_interconnect_0:hex_0_s1_address -> hex_0:address
wire mm_interconnect_0_hex_0_s1_write; // mm_interconnect_0:hex_0_s1_write -> hex_0:write_n
wire [31:0] mm_interconnect_0_hex_0_s1_writedata; // mm_interconnect_0:hex_0_s1_writedata -> hex_0:writedata
wire mm_interconnect_0_hex_1_s1_chipselect; // mm_interconnect_0:hex_1_s1_chipselect -> hex_1:chipselect
wire [31:0] mm_interconnect_0_hex_1_s1_readdata; // hex_1:readdata -> mm_interconnect_0:hex_1_s1_readdata
wire [1:0] mm_interconnect_0_hex_1_s1_address; // mm_interconnect_0:hex_1_s1_address -> hex_1:address
wire mm_interconnect_0_hex_1_s1_write; // mm_interconnect_0:hex_1_s1_write -> hex_1:write_n
wire [31:0] mm_interconnect_0_hex_1_s1_writedata; // mm_interconnect_0:hex_1_s1_writedata -> hex_1:writedata
wire mm_interconnect_0_hex_2_s1_chipselect; // mm_interconnect_0:hex_2_s1_chipselect -> hex_2:chipselect
wire [31:0] mm_interconnect_0_hex_2_s1_readdata; // hex_2:readdata -> mm_interconnect_0:hex_2_s1_readdata
wire [1:0] mm_interconnect_0_hex_2_s1_address; // mm_interconnect_0:hex_2_s1_address -> hex_2:address
wire mm_interconnect_0_hex_2_s1_write; // mm_interconnect_0:hex_2_s1_write -> hex_2:write_n
wire [31:0] mm_interconnect_0_hex_2_s1_writedata; // mm_interconnect_0:hex_2_s1_writedata -> hex_2:writedata
wire mm_interconnect_0_hex_3_s1_chipselect; // mm_interconnect_0:hex_3_s1_chipselect -> hex_3:chipselect
wire [31:0] mm_interconnect_0_hex_3_s1_readdata; // hex_3:readdata -> mm_interconnect_0:hex_3_s1_readdata
wire [1:0] mm_interconnect_0_hex_3_s1_address; // mm_interconnect_0:hex_3_s1_address -> hex_3:address
wire mm_interconnect_0_hex_3_s1_write; // mm_interconnect_0:hex_3_s1_write -> hex_3:write_n
wire [31:0] mm_interconnect_0_hex_3_s1_writedata; // mm_interconnect_0:hex_3_s1_writedata -> hex_3:writedata
wire mm_interconnect_0_hex_4_s1_chipselect; // mm_interconnect_0:hex_4_s1_chipselect -> hex_4:chipselect
wire [31:0] mm_interconnect_0_hex_4_s1_readdata; // hex_4:readdata -> mm_interconnect_0:hex_4_s1_readdata
wire [1:0] mm_interconnect_0_hex_4_s1_address; // mm_interconnect_0:hex_4_s1_address -> hex_4:address
wire mm_interconnect_0_hex_4_s1_write; // mm_interconnect_0:hex_4_s1_write -> hex_4:write_n
wire [31:0] mm_interconnect_0_hex_4_s1_writedata; // mm_interconnect_0:hex_4_s1_writedata -> hex_4:writedata
wire mm_interconnect_0_hex_5_s1_chipselect; // mm_interconnect_0:hex_5_s1_chipselect -> hex_5:chipselect
wire [31:0] mm_interconnect_0_hex_5_s1_readdata; // hex_5:readdata -> mm_interconnect_0:hex_5_s1_readdata
wire [1:0] mm_interconnect_0_hex_5_s1_address; // mm_interconnect_0:hex_5_s1_address -> hex_5:address
wire mm_interconnect_0_hex_5_s1_write; // mm_interconnect_0:hex_5_s1_write -> hex_5:write_n
wire [31:0] mm_interconnect_0_hex_5_s1_writedata; // mm_interconnect_0:hex_5_s1_writedata -> hex_5:writedata
wire mm_interconnect_0_alu_a_s1_chipselect; // mm_interconnect_0:alu_a_s1_chipselect -> alu_a:chipselect
wire [31:0] mm_interconnect_0_alu_a_s1_readdata; // alu_a:readdata -> mm_interconnect_0:alu_a_s1_readdata
wire [1:0] mm_interconnect_0_alu_a_s1_address; // mm_interconnect_0:alu_a_s1_address -> alu_a:address
wire mm_interconnect_0_alu_a_s1_write; // mm_interconnect_0:alu_a_s1_write -> alu_a:write_n
wire [31:0] mm_interconnect_0_alu_a_s1_writedata; // mm_interconnect_0:alu_a_s1_writedata -> alu_a:writedata
wire mm_interconnect_0_alu_b_s1_chipselect; // mm_interconnect_0:alu_b_s1_chipselect -> alu_b:chipselect
wire [31:0] mm_interconnect_0_alu_b_s1_readdata; // alu_b:readdata -> mm_interconnect_0:alu_b_s1_readdata
wire [1:0] mm_interconnect_0_alu_b_s1_address; // mm_interconnect_0:alu_b_s1_address -> alu_b:address
wire mm_interconnect_0_alu_b_s1_write; // mm_interconnect_0:alu_b_s1_write -> alu_b:write_n
wire [31:0] mm_interconnect_0_alu_b_s1_writedata; // mm_interconnect_0:alu_b_s1_writedata -> alu_b:writedata
wire mm_interconnect_0_alu_control_s1_chipselect; // mm_interconnect_0:alu_control_s1_chipselect -> alu_control:chipselect
wire [31:0] mm_interconnect_0_alu_control_s1_readdata; // alu_control:readdata -> mm_interconnect_0:alu_control_s1_readdata
wire [1:0] mm_interconnect_0_alu_control_s1_address; // mm_interconnect_0:alu_control_s1_address -> alu_control:address
wire mm_interconnect_0_alu_control_s1_write; // mm_interconnect_0:alu_control_s1_write -> alu_control:write_n
wire [31:0] mm_interconnect_0_alu_control_s1_writedata; // mm_interconnect_0:alu_control_s1_writedata -> alu_control:writedata
wire [31:0] mm_interconnect_0_alu_out_s1_readdata; // alu_out:readdata -> mm_interconnect_0:alu_out_s1_readdata
wire [1:0] mm_interconnect_0_alu_out_s1_address; // mm_interconnect_0:alu_out_s1_address -> alu_out:address
wire [31:0] mm_interconnect_0_alu_zero_s1_readdata; // alu_zero:readdata -> mm_interconnect_0:alu_zero_s1_readdata
wire [1:0] mm_interconnect_0_alu_zero_s1_address; // mm_interconnect_0:alu_zero_s1_address -> alu_zero:address
wire [31:0] mm_interconnect_0_alu_overflow_s1_readdata; // alu_overflow:readdata -> mm_interconnect_0:alu_overflow_s1_readdata
wire [1:0] mm_interconnect_0_alu_overflow_s1_address; // mm_interconnect_0:alu_overflow_s1_address -> alu_overflow:address
wire [31:0] mm_interconnect_0_alu_carry_out_s1_readdata; // alu_carry_out:readdata -> mm_interconnect_0:alu_carry_out_s1_readdata
wire [1:0] mm_interconnect_0_alu_carry_out_s1_address; // mm_interconnect_0:alu_carry_out_s1_address -> alu_carry_out:address
wire [31:0] mm_interconnect_0_alu_negative_s1_readdata; // alu_negative:readdata -> mm_interconnect_0:alu_negative_s1_readdata
wire [1:0] mm_interconnect_0_alu_negative_s1_address; // mm_interconnect_0:alu_negative_s1_address -> alu_negative:address
wire [31:0] mm_interconnect_0_keys_s1_readdata; // keys:readdata -> mm_interconnect_0:keys_s1_readdata
wire [1:0] mm_interconnect_0_keys_s1_address; // mm_interconnect_0:keys_s1_address -> keys:address
wire irq_mapper_receiver0_irq; // jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
wire [31:0] nios2_qsys_0_irq_irq; // irq_mapper:sender_irq -> nios2_qsys_0:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [LEDs:reset_n, alu_a:reset_n, alu_b:reset_n, alu_carry_out:reset_n, alu_control:reset_n, alu_negative:reset_n, alu_out:reset_n, alu_overflow:reset_n, alu_zero:reset_n, hex_0:reset_n, hex_1:reset_n, hex_2:reset_n, hex_3:reset_n, hex_4:reset_n, hex_5:reset_n, irq_mapper:reset, jtag_uart_0:rst_n, keys:reset_n, mm_interconnect_0:nios2_qsys_0_reset_reset_bridge_in_reset_reset, nios2_qsys_0:reset_n, onchip_memory2_0:reset, regfile_data:reset_n, regfile_r1sel:reset_n, regfile_r2sel:reset_n, regfile_reg1:reset_n, regfile_reg2:reset_n, regfile_we:reset_n, regfile_wsel:reset_n, rst_translator:in_reset, sram_addr:reset_n, sram_cs:reset_n, sram_data:reset_n, sram_oe:reset_n, sram_read_write:reset_n, switches:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [nios2_qsys_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
wire nios2_qsys_0_debug_reset_request_reset; // nios2_qsys_0:debug_reset_request -> rst_controller:reset_in1
nios_system_LEDs leds (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_leds_s1_address), // s1.address
.write_n (~mm_interconnect_0_leds_s1_write), // .write_n
.writedata (mm_interconnect_0_leds_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_leds_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_leds_s1_readdata), // .readdata
.out_port (leds_export) // external_connection.export
);
nios_system_alu_a alu_a (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_a_s1_address), // s1.address
.write_n (~mm_interconnect_0_alu_a_s1_write), // .write_n
.writedata (mm_interconnect_0_alu_a_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_alu_a_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_alu_a_s1_readdata), // .readdata
.out_port (alu_a_export) // external_connection.export
);
nios_system_alu_a alu_b (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_b_s1_address), // s1.address
.write_n (~mm_interconnect_0_alu_b_s1_write), // .write_n
.writedata (mm_interconnect_0_alu_b_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_alu_b_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_alu_b_s1_readdata), // .readdata
.out_port (alu_b_export) // external_connection.export
);
nios_system_alu_carry_out alu_carry_out (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_carry_out_s1_address), // s1.address
.readdata (mm_interconnect_0_alu_carry_out_s1_readdata), // .readdata
.in_port (alu_carry_out_export) // external_connection.export
);
nios_system_alu_control alu_control (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_control_s1_address), // s1.address
.write_n (~mm_interconnect_0_alu_control_s1_write), // .write_n
.writedata (mm_interconnect_0_alu_control_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_alu_control_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_alu_control_s1_readdata), // .readdata
.out_port (alu_control_export) // external_connection.export
);
nios_system_alu_carry_out alu_negative (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_negative_s1_address), // s1.address
.readdata (mm_interconnect_0_alu_negative_s1_readdata), // .readdata
.in_port (alu_negative_export) // external_connection.export
);
nios_system_alu_out alu_out (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_out_s1_address), // s1.address
.readdata (mm_interconnect_0_alu_out_s1_readdata), // .readdata
.in_port (alu_out_export) // external_connection.export
);
nios_system_alu_carry_out alu_overflow (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_overflow_s1_address), // s1.address
.readdata (mm_interconnect_0_alu_overflow_s1_readdata), // .readdata
.in_port (alu_overflow_export) // external_connection.export
);
nios_system_alu_carry_out alu_zero (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_alu_zero_s1_address), // s1.address
.readdata (mm_interconnect_0_alu_zero_s1_readdata), // .readdata
.in_port (alu_zero_export) // external_connection.export
);
nios_system_hex_0 hex_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_0_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_0_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_0_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_0_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_0_s1_readdata), // .readdata
.out_port (hex_0_export) // external_connection.export
);
nios_system_hex_0 hex_1 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_1_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_1_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_1_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_1_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_1_s1_readdata), // .readdata
.out_port (hex_1_export) // external_connection.export
);
nios_system_hex_0 hex_2 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_2_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_2_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_2_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_2_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_2_s1_readdata), // .readdata
.out_port (hex_2_export) // external_connection.export
);
nios_system_hex_0 hex_3 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_3_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_3_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_3_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_3_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_3_s1_readdata), // .readdata
.out_port (hex_3_export) // external_connection.export
);
nios_system_hex_0 hex_4 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_4_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_4_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_4_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_4_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_4_s1_readdata), // .readdata
.out_port (hex_4_export) // external_connection.export
);
nios_system_hex_0 hex_5 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_hex_5_s1_address), // s1.address
.write_n (~mm_interconnect_0_hex_5_s1_write), // .write_n
.writedata (mm_interconnect_0_hex_5_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_hex_5_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_hex_5_s1_readdata), // .readdata
.out_port (hex_5_export) // external_connection.export
);
nios_system_jtag_uart_0 jtag_uart_0 (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver0_irq) // irq.irq
);
nios_system_keys keys (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_keys_s1_address), // s1.address
.readdata (mm_interconnect_0_keys_s1_readdata), // .readdata
.in_port (keys_export) // external_connection.export
);
nios_system_nios2_qsys_0 nios2_qsys_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.d_address (nios2_qsys_0_data_master_address), // data_master.address
.d_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable
.d_read (nios2_qsys_0_data_master_read), // .read
.d_readdata (nios2_qsys_0_data_master_readdata), // .readdata
.d_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest
.d_write (nios2_qsys_0_data_master_write), // .write
.d_writedata (nios2_qsys_0_data_master_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (nios2_qsys_0_data_master_debugaccess), // .debugaccess
.i_address (nios2_qsys_0_instruction_master_address), // instruction_master.address
.i_read (nios2_qsys_0_instruction_master_read), // .read
.i_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata
.i_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest
.irq (nios2_qsys_0_irq_irq), // irq.irq
.debug_reset_request (nios2_qsys_0_debug_reset_request_reset), // debug_reset_request.reset
.debug_mem_slave_address (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_read), // .read
.debug_mem_slave_readdata (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_write), // .write
.debug_mem_slave_writedata (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_writedata), // .writedata
.dummy_ci_port () // custom_instruction_master.readra
);
nios_system_onchip_memory2_0 onchip_memory2_0 (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
nios_system_alu_a regfile_data (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_data_s1_address), // s1.address
.write_n (~mm_interconnect_0_regfile_data_s1_write), // .write_n
.writedata (mm_interconnect_0_regfile_data_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_regfile_data_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_regfile_data_s1_readdata), // .readdata
.out_port (regfile_data_export) // external_connection.export
);
nios_system_regfile_r1sel regfile_r1sel (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_r1sel_s1_address), // s1.address
.write_n (~mm_interconnect_0_regfile_r1sel_s1_write), // .write_n
.writedata (mm_interconnect_0_regfile_r1sel_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_regfile_r1sel_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_regfile_r1sel_s1_readdata), // .readdata
.out_port (regfile_r1sel_export) // external_connection.export
);
nios_system_regfile_r1sel regfile_r2sel (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_r2sel_s1_address), // s1.address
.write_n (~mm_interconnect_0_regfile_r2sel_s1_write), // .write_n
.writedata (mm_interconnect_0_regfile_r2sel_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_regfile_r2sel_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_regfile_r2sel_s1_readdata), // .readdata
.out_port (regfile_r2sel_export) // external_connection.export
);
nios_system_alu_out regfile_reg1 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_reg1_s1_address), // s1.address
.readdata (mm_interconnect_0_regfile_reg1_s1_readdata), // .readdata
.in_port (regfile_reg1_export) // external_connection.export
);
nios_system_alu_out regfile_reg2 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_reg2_s1_address), // s1.address
.readdata (mm_interconnect_0_regfile_reg2_s1_readdata), // .readdata
.in_port (regfile_reg2_export) // external_connection.export
);
nios_system_regfile_we regfile_we (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_we_s1_address), // s1.address
.write_n (~mm_interconnect_0_regfile_we_s1_write), // .write_n
.writedata (mm_interconnect_0_regfile_we_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_regfile_we_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_regfile_we_s1_readdata), // .readdata
.out_port (regfile_we_export) // external_connection.export
);
nios_system_regfile_r1sel regfile_wsel (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_regfile_wsel_s1_address), // s1.address
.write_n (~mm_interconnect_0_regfile_wsel_s1_write), // .write_n
.writedata (mm_interconnect_0_regfile_wsel_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_regfile_wsel_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_regfile_wsel_s1_readdata), // .readdata
.out_port (regfile_wsel_export) // external_connection.export
);
nios_system_sram_addr sram_addr (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sram_addr_s1_address), // s1.address
.write_n (~mm_interconnect_0_sram_addr_s1_write), // .write_n
.writedata (mm_interconnect_0_sram_addr_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_sram_addr_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_sram_addr_s1_readdata), // .readdata
.out_port (sram_addr_export) // external_connection.export
);
nios_system_regfile_we sram_cs (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sram_cs_s1_address), // s1.address
.write_n (~mm_interconnect_0_sram_cs_s1_write), // .write_n
.writedata (mm_interconnect_0_sram_cs_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_sram_cs_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_sram_cs_s1_readdata), // .readdata
.out_port (sram_cs_export) // external_connection.export
);
nios_system_sram_data sram_data (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sram_data_s1_address), // s1.address
.write_n (~mm_interconnect_0_sram_data_s1_write), // .write_n
.writedata (mm_interconnect_0_sram_data_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_sram_data_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_sram_data_s1_readdata), // .readdata
.bidir_port (sram_data_in_export) // external_connection.export
);
nios_system_regfile_we sram_oe (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sram_oe_s1_address), // s1.address
.write_n (~mm_interconnect_0_sram_oe_s1_write), // .write_n
.writedata (mm_interconnect_0_sram_oe_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_sram_oe_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_sram_oe_s1_readdata), // .readdata
.out_port (sram_oe_export) // external_connection.export
);
nios_system_regfile_we sram_read_write (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_sram_read_write_s1_address), // s1.address
.write_n (~mm_interconnect_0_sram_read_write_s1_write), // .write_n
.writedata (mm_interconnect_0_sram_read_write_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_sram_read_write_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_sram_read_write_s1_readdata), // .readdata
.out_port (sram_read_write_export) // external_connection.export
);
nios_system_switches switches (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_switches_s1_address), // s1.address
.readdata (mm_interconnect_0_switches_s1_readdata), // .readdata
.in_port (switches_export) // external_connection.export
);
nios_system_mm_interconnect_0 mm_interconnect_0 (
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.nios2_qsys_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // nios2_qsys_0_reset_reset_bridge_in_reset.reset
.nios2_qsys_0_data_master_address (nios2_qsys_0_data_master_address), // nios2_qsys_0_data_master.address
.nios2_qsys_0_data_master_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest
.nios2_qsys_0_data_master_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable
.nios2_qsys_0_data_master_read (nios2_qsys_0_data_master_read), // .read
.nios2_qsys_0_data_master_readdata (nios2_qsys_0_data_master_readdata), // .readdata
.nios2_qsys_0_data_master_write (nios2_qsys_0_data_master_write), // .write
.nios2_qsys_0_data_master_writedata (nios2_qsys_0_data_master_writedata), // .writedata
.nios2_qsys_0_data_master_debugaccess (nios2_qsys_0_data_master_debugaccess), // .debugaccess
.nios2_qsys_0_instruction_master_address (nios2_qsys_0_instruction_master_address), // nios2_qsys_0_instruction_master.address
.nios2_qsys_0_instruction_master_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest
.nios2_qsys_0_instruction_master_read (nios2_qsys_0_instruction_master_read), // .read
.nios2_qsys_0_instruction_master_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata
.alu_a_s1_address (mm_interconnect_0_alu_a_s1_address), // alu_a_s1.address
.alu_a_s1_write (mm_interconnect_0_alu_a_s1_write), // .write
.alu_a_s1_readdata (mm_interconnect_0_alu_a_s1_readdata), // .readdata
.alu_a_s1_writedata (mm_interconnect_0_alu_a_s1_writedata), // .writedata
.alu_a_s1_chipselect (mm_interconnect_0_alu_a_s1_chipselect), // .chipselect
.alu_b_s1_address (mm_interconnect_0_alu_b_s1_address), // alu_b_s1.address
.alu_b_s1_write (mm_interconnect_0_alu_b_s1_write), // .write
.alu_b_s1_readdata (mm_interconnect_0_alu_b_s1_readdata), // .readdata
.alu_b_s1_writedata (mm_interconnect_0_alu_b_s1_writedata), // .writedata
.alu_b_s1_chipselect (mm_interconnect_0_alu_b_s1_chipselect), // .chipselect
.alu_carry_out_s1_address (mm_interconnect_0_alu_carry_out_s1_address), // alu_carry_out_s1.address
.alu_carry_out_s1_readdata (mm_interconnect_0_alu_carry_out_s1_readdata), // .readdata
.alu_control_s1_address (mm_interconnect_0_alu_control_s1_address), // alu_control_s1.address
.alu_control_s1_write (mm_interconnect_0_alu_control_s1_write), // .write
.alu_control_s1_readdata (mm_interconnect_0_alu_control_s1_readdata), // .readdata
.alu_control_s1_writedata (mm_interconnect_0_alu_control_s1_writedata), // .writedata
.alu_control_s1_chipselect (mm_interconnect_0_alu_control_s1_chipselect), // .chipselect
.alu_negative_s1_address (mm_interconnect_0_alu_negative_s1_address), // alu_negative_s1.address
.alu_negative_s1_readdata (mm_interconnect_0_alu_negative_s1_readdata), // .readdata
.alu_out_s1_address (mm_interconnect_0_alu_out_s1_address), // alu_out_s1.address
.alu_out_s1_readdata (mm_interconnect_0_alu_out_s1_readdata), // .readdata
.alu_overflow_s1_address (mm_interconnect_0_alu_overflow_s1_address), // alu_overflow_s1.address
.alu_overflow_s1_readdata (mm_interconnect_0_alu_overflow_s1_readdata), // .readdata
.alu_zero_s1_address (mm_interconnect_0_alu_zero_s1_address), // alu_zero_s1.address
.alu_zero_s1_readdata (mm_interconnect_0_alu_zero_s1_readdata), // .readdata
.hex_0_s1_address (mm_interconnect_0_hex_0_s1_address), // hex_0_s1.address
.hex_0_s1_write (mm_interconnect_0_hex_0_s1_write), // .write
.hex_0_s1_readdata (mm_interconnect_0_hex_0_s1_readdata), // .readdata
.hex_0_s1_writedata (mm_interconnect_0_hex_0_s1_writedata), // .writedata
.hex_0_s1_chipselect (mm_interconnect_0_hex_0_s1_chipselect), // .chipselect
.hex_1_s1_address (mm_interconnect_0_hex_1_s1_address), // hex_1_s1.address
.hex_1_s1_write (mm_interconnect_0_hex_1_s1_write), // .write
.hex_1_s1_readdata (mm_interconnect_0_hex_1_s1_readdata), // .readdata
.hex_1_s1_writedata (mm_interconnect_0_hex_1_s1_writedata), // .writedata
.hex_1_s1_chipselect (mm_interconnect_0_hex_1_s1_chipselect), // .chipselect
.hex_2_s1_address (mm_interconnect_0_hex_2_s1_address), // hex_2_s1.address
.hex_2_s1_write (mm_interconnect_0_hex_2_s1_write), // .write
.hex_2_s1_readdata (mm_interconnect_0_hex_2_s1_readdata), // .readdata
.hex_2_s1_writedata (mm_interconnect_0_hex_2_s1_writedata), // .writedata
.hex_2_s1_chipselect (mm_interconnect_0_hex_2_s1_chipselect), // .chipselect
.hex_3_s1_address (mm_interconnect_0_hex_3_s1_address), // hex_3_s1.address
.hex_3_s1_write (mm_interconnect_0_hex_3_s1_write), // .write
.hex_3_s1_readdata (mm_interconnect_0_hex_3_s1_readdata), // .readdata
.hex_3_s1_writedata (mm_interconnect_0_hex_3_s1_writedata), // .writedata
.hex_3_s1_chipselect (mm_interconnect_0_hex_3_s1_chipselect), // .chipselect
.hex_4_s1_address (mm_interconnect_0_hex_4_s1_address), // hex_4_s1.address
.hex_4_s1_write (mm_interconnect_0_hex_4_s1_write), // .write
.hex_4_s1_readdata (mm_interconnect_0_hex_4_s1_readdata), // .readdata
.hex_4_s1_writedata (mm_interconnect_0_hex_4_s1_writedata), // .writedata
.hex_4_s1_chipselect (mm_interconnect_0_hex_4_s1_chipselect), // .chipselect
.hex_5_s1_address (mm_interconnect_0_hex_5_s1_address), // hex_5_s1.address
.hex_5_s1_write (mm_interconnect_0_hex_5_s1_write), // .write
.hex_5_s1_readdata (mm_interconnect_0_hex_5_s1_readdata), // .readdata
.hex_5_s1_writedata (mm_interconnect_0_hex_5_s1_writedata), // .writedata
.hex_5_s1_chipselect (mm_interconnect_0_hex_5_s1_chipselect), // .chipselect
.jtag_uart_0_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address), // jtag_uart_0_avalon_jtag_slave.address
.jtag_uart_0_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write), // .write
.jtag_uart_0_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read), // .read
.jtag_uart_0_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_0_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_0_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_0_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect), // .chipselect
.keys_s1_address (mm_interconnect_0_keys_s1_address), // keys_s1.address
.keys_s1_readdata (mm_interconnect_0_keys_s1_readdata), // .readdata
.LEDs_s1_address (mm_interconnect_0_leds_s1_address), // LEDs_s1.address
.LEDs_s1_write (mm_interconnect_0_leds_s1_write), // .write
.LEDs_s1_readdata (mm_interconnect_0_leds_s1_readdata), // .readdata
.LEDs_s1_writedata (mm_interconnect_0_leds_s1_writedata), // .writedata
.LEDs_s1_chipselect (mm_interconnect_0_leds_s1_chipselect), // .chipselect
.nios2_qsys_0_debug_mem_slave_address (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_address), // nios2_qsys_0_debug_mem_slave.address
.nios2_qsys_0_debug_mem_slave_write (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_write), // .write
.nios2_qsys_0_debug_mem_slave_read (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_read), // .read
.nios2_qsys_0_debug_mem_slave_readdata (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_readdata), // .readdata
.nios2_qsys_0_debug_mem_slave_writedata (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_writedata), // .writedata
.nios2_qsys_0_debug_mem_slave_byteenable (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_byteenable), // .byteenable
.nios2_qsys_0_debug_mem_slave_waitrequest (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_waitrequest), // .waitrequest
.nios2_qsys_0_debug_mem_slave_debugaccess (mm_interconnect_0_nios2_qsys_0_debug_mem_slave_debugaccess), // .debugaccess
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.regfile_data_s1_address (mm_interconnect_0_regfile_data_s1_address), // regfile_data_s1.address
.regfile_data_s1_write (mm_interconnect_0_regfile_data_s1_write), // .write
.regfile_data_s1_readdata (mm_interconnect_0_regfile_data_s1_readdata), // .readdata
.regfile_data_s1_writedata (mm_interconnect_0_regfile_data_s1_writedata), // .writedata
.regfile_data_s1_chipselect (mm_interconnect_0_regfile_data_s1_chipselect), // .chipselect
.regfile_r1sel_s1_address (mm_interconnect_0_regfile_r1sel_s1_address), // regfile_r1sel_s1.address
.regfile_r1sel_s1_write (mm_interconnect_0_regfile_r1sel_s1_write), // .write
.regfile_r1sel_s1_readdata (mm_interconnect_0_regfile_r1sel_s1_readdata), // .readdata
.regfile_r1sel_s1_writedata (mm_interconnect_0_regfile_r1sel_s1_writedata), // .writedata
.regfile_r1sel_s1_chipselect (mm_interconnect_0_regfile_r1sel_s1_chipselect), // .chipselect
.regfile_r2sel_s1_address (mm_interconnect_0_regfile_r2sel_s1_address), // regfile_r2sel_s1.address
.regfile_r2sel_s1_write (mm_interconnect_0_regfile_r2sel_s1_write), // .write
.regfile_r2sel_s1_readdata (mm_interconnect_0_regfile_r2sel_s1_readdata), // .readdata
.regfile_r2sel_s1_writedata (mm_interconnect_0_regfile_r2sel_s1_writedata), // .writedata
.regfile_r2sel_s1_chipselect (mm_interconnect_0_regfile_r2sel_s1_chipselect), // .chipselect
.regfile_reg1_s1_address (mm_interconnect_0_regfile_reg1_s1_address), // regfile_reg1_s1.address
.regfile_reg1_s1_readdata (mm_interconnect_0_regfile_reg1_s1_readdata), // .readdata
.regfile_reg2_s1_address (mm_interconnect_0_regfile_reg2_s1_address), // regfile_reg2_s1.address
.regfile_reg2_s1_readdata (mm_interconnect_0_regfile_reg2_s1_readdata), // .readdata
.regfile_we_s1_address (mm_interconnect_0_regfile_we_s1_address), // regfile_we_s1.address
.regfile_we_s1_write (mm_interconnect_0_regfile_we_s1_write), // .write
.regfile_we_s1_readdata (mm_interconnect_0_regfile_we_s1_readdata), // .readdata
.regfile_we_s1_writedata (mm_interconnect_0_regfile_we_s1_writedata), // .writedata
.regfile_we_s1_chipselect (mm_interconnect_0_regfile_we_s1_chipselect), // .chipselect
.regfile_wsel_s1_address (mm_interconnect_0_regfile_wsel_s1_address), // regfile_wsel_s1.address
.regfile_wsel_s1_write (mm_interconnect_0_regfile_wsel_s1_write), // .write
.regfile_wsel_s1_readdata (mm_interconnect_0_regfile_wsel_s1_readdata), // .readdata
.regfile_wsel_s1_writedata (mm_interconnect_0_regfile_wsel_s1_writedata), // .writedata
.regfile_wsel_s1_chipselect (mm_interconnect_0_regfile_wsel_s1_chipselect), // .chipselect
.sram_addr_s1_address (mm_interconnect_0_sram_addr_s1_address), // sram_addr_s1.address
.sram_addr_s1_write (mm_interconnect_0_sram_addr_s1_write), // .write
.sram_addr_s1_readdata (mm_interconnect_0_sram_addr_s1_readdata), // .readdata
.sram_addr_s1_writedata (mm_interconnect_0_sram_addr_s1_writedata), // .writedata
.sram_addr_s1_chipselect (mm_interconnect_0_sram_addr_s1_chipselect), // .chipselect
.sram_cs_s1_address (mm_interconnect_0_sram_cs_s1_address), // sram_cs_s1.address
.sram_cs_s1_write (mm_interconnect_0_sram_cs_s1_write), // .write
.sram_cs_s1_readdata (mm_interconnect_0_sram_cs_s1_readdata), // .readdata
.sram_cs_s1_writedata (mm_interconnect_0_sram_cs_s1_writedata), // .writedata
.sram_cs_s1_chipselect (mm_interconnect_0_sram_cs_s1_chipselect), // .chipselect
.sram_data_s1_address (mm_interconnect_0_sram_data_s1_address), // sram_data_s1.address
.sram_data_s1_write (mm_interconnect_0_sram_data_s1_write), // .write
.sram_data_s1_readdata (mm_interconnect_0_sram_data_s1_readdata), // .readdata
.sram_data_s1_writedata (mm_interconnect_0_sram_data_s1_writedata), // .writedata
.sram_data_s1_chipselect (mm_interconnect_0_sram_data_s1_chipselect), // .chipselect
.sram_oe_s1_address (mm_interconnect_0_sram_oe_s1_address), // sram_oe_s1.address
.sram_oe_s1_write (mm_interconnect_0_sram_oe_s1_write), // .write
.sram_oe_s1_readdata (mm_interconnect_0_sram_oe_s1_readdata), // .readdata
.sram_oe_s1_writedata (mm_interconnect_0_sram_oe_s1_writedata), // .writedata
.sram_oe_s1_chipselect (mm_interconnect_0_sram_oe_s1_chipselect), // .chipselect
.sram_read_write_s1_address (mm_interconnect_0_sram_read_write_s1_address), // sram_read_write_s1.address
.sram_read_write_s1_write (mm_interconnect_0_sram_read_write_s1_write), // .write
.sram_read_write_s1_readdata (mm_interconnect_0_sram_read_write_s1_readdata), // .readdata
.sram_read_write_s1_writedata (mm_interconnect_0_sram_read_write_s1_writedata), // .writedata
.sram_read_write_s1_chipselect (mm_interconnect_0_sram_read_write_s1_chipselect), // .chipselect
.switches_s1_address (mm_interconnect_0_switches_s1_address), // switches_s1.address
.switches_s1_readdata (mm_interconnect_0_switches_s1_readdata) // .readdata
);
nios_system_irq_mapper irq_mapper (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (nios2_qsys_0_irq_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (nios2_qsys_0_debug_reset_request_reset), // reset_in1.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
//
// fixed for 9.1 jan 21 2010 cruben
//
//`include "timescale.v"
`include "i2c_master_defines.v"
module i2c_opencores
(
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, /*wb_cyc_i,*/ wb_ack_o, wb_inta_o,
scl_pad_io, sda_pad_io
);
// Common bus signals
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
// Slave signals
input [2:0] wb_adr_i; // WISHBONE address input
input [7:0] wb_dat_i; // WISHBONE data input
output [7:0] wb_dat_o; // WISHBONE data output
input wb_we_i; // WISHBONE write enable input
input wb_stb_i; // WISHBONE strobe input
//input wb_cyc_i; // WISHBONE cycle input
output wb_ack_o; // WISHBONE acknowledge output
output wb_inta_o; // WISHBONE interrupt output
// I2C signals
inout scl_pad_io; // I2C clock io
inout sda_pad_io; // I2C data io
wire wb_cyc_i; // WISHBONE cycle input
// Wire tri-state scl/sda
wire scl_pad_i;
wire scl_pad_o;
wire scl_pad_io;
wire scl_padoen_o;
assign wb_cyc_i = wb_stb_i;
assign scl_pad_i = scl_pad_io;
assign scl_pad_io = scl_padoen_o ? 1'bZ : scl_pad_o;
wire sda_pad_i;
wire sda_pad_o;
wire sda_pad_io;
wire sda_padoen_o;
assign sda_pad_i = sda_pad_io;
assign sda_pad_io = sda_padoen_o ? 1'bZ : sda_pad_o;
// Avalon doesn't have an asynchronous reset
// set it to be inactive and just use synchronous reset
// reset level is a parameter, 0 is the default (active-low reset)
wire arst_i;
assign arst_i = 1'b1;
// Connect the top level I2C core
i2c_master_top i2c_master_top_inst
(
.wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), .arst_i(arst_i),
.wb_adr_i(wb_adr_i), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
.wb_we_i(wb_we_i), .wb_stb_i(wb_stb_i), .wb_cyc_i(wb_cyc_i),
.wb_ack_o(wb_ack_o), .wb_inta_o(wb_inta_o),
.scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_padoen_o(scl_padoen_o),
.sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_padoen_o(sda_padoen_o)
);
endmodule
|
// STD 10-30-16
//
// Synchronous 1-port ram with byte masking
// Only one read or one write may be done per cycle.
//
`define bsg_mem_1rw_sync_macro_byte(words,bits,lgEls,mux) \
if (els_p == words && data_width_p == bits) \
begin: macro \
wire [data_width_p-1:0] wen; \
genvar i; \
for(i=0;i<write_mask_width_lp;i++) \
assign wen[8*i+:8] = {8{write_mask_i[i]}}; \
tsmc40_1rw_lg``lgEls``_w``bits``_m``mux mem \
(.A ( addr_i ) \
,.D ( data_i ) \
,.BWEB ( ~wen ) \
,.WEB ( ~w_i ) \
,.CEB ( ~v_i ) \
,.CLK ( clk_i ) \
,.Q ( data_o ) \
,.DELAY ( 2'b0 ) \
,.TEST ( 2'b0 )); \
end
`define bsg_mem_1rf_sync_macro_byte(words,bits,lgEls,mux) \
if (els_p == words && data_width_p == bits) \
begin: macro \
wire [data_width_p-1:0] wen; \
genvar i; \
for(i=0;i<write_mask_width_lp;i++) \
assign wen[8*i+:8] = {8{write_mask_i[i]}}; \
tsmc40_1rf_lg``lgEls``_w``bits``_m``mux mem \
(.A ( addr_i ) \
,.D ( data_i ) \
,.BWEB ( ~wen ) \
,.WEB ( ~w_i ) \
,.CEB ( ~v_i ) \
,.CLK ( clk_i ) \
,.Q ( data_o ) \
,.DELAY ( 2'b0 )); \
end
`define bsg_mem_1rf_sync_macro_byte_banks(words,bits,lgEls,mux) \
if (els_p == 2*``words`` && data_width_p == bits) \
begin: macro \
wire [data_width_p-1:0] wen; \
wire [data_width_p-1:0] bank_data [0:1]; \
logic sel; \
always_ff @(posedge clk_i) \
sel <= addr_i[0]; \
genvar i; \
for(i=0;i<write_mask_width_lp;i++) \
assign wen[8*i+:8] = {8{write_mask_i[i]}}; \
tsmc40_1rf_lg``lgEls``_w``bits``_m``mux mem0 \
(.A ( addr_i[addr_width_lp-1:1] ) \
,.D ( data_i ) \
,.BWEB ( ~wen ) \
,.WEB ( ~w_i | addr_i[0] ) \
,.CEB ( ~v_i | addr_i[0] ) \
,.CLK ( clk_i ) \
,.Q ( bank_data[0] ) \
,.DELAY ( 2'b0 )); \
tsmc40_1rf_lg``lgEls``_w``bits``_m``mux mem1 \
(.A ( addr_i[addr_width_lp-1:1] ) \
,.D ( data_i ) \
,.BWEB ( ~wen ) \
,.WEB ( ~w_i | ~addr_i[0] ) \
,.CEB ( ~v_i | ~addr_i[0] ) \
,.CLK ( clk_i ) \
,.Q ( bank_data[1] ) \
,.DELAY ( 2'b0 )); \
assign data_o = sel? bank_data[1]: bank_data[0]; \
end
module bsg_mem_1rw_sync_mask_write_byte
#(parameter `BSG_INV_PARAM(els_p )
,parameter `BSG_INV_PARAM(data_width_p )
,parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
,parameter write_mask_width_lp = data_width_p>>3
)
(input clk_i
,input reset_i
,input v_i
,input w_i
,input [addr_width_lp-1:0] addr_i
,input [data_width_p-1:0] data_i
,input [write_mask_width_lp-1:0] write_mask_i
,output [data_width_p-1:0] data_o
);
wire unused = reset_i;
`bsg_mem_1rw_sync_macro_byte(4096,64,12,8) else
`bsg_mem_1rw_sync_macro_byte(2048,64,11,4) else
`bsg_mem_1rw_sync_macro_byte(2048,64,11,4) else
`bsg_mem_1rf_sync_macro_byte_banks(512,32,9,4) else
`bsg_mem_1rf_sync_macro_byte(1024,32,10,8) else
`bsg_mem_1rw_sync_macro_byte(1024,32,10,4) else
// no hardened version found
begin : notmacro
bsg_mem_1rw_sync_mask_write_byte_synth
#(.els_p(els_p), .data_width_p(data_width_p))
synth (.*);
end
// synopsys translate_off
always_comb
assert (data_width_p % 8 == 0)
else $error("data width should be a multiple of 8 for byte masking");
initial
begin
$display("## bsg_mem_1rw_sync_mask_write_byte: instantiating data_width_p=%d, els_p=%d (%m)",data_width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_byte)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__EDFXBP_FUNCTIONAL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_edf_p_pg/sky130_fd_sc_hs__u_edf_p_pg.v"
`celldefine
module sky130_fd_sc_hs__edfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_edf_p_pg `UNIT_DELAY u_edf_p_pg0 (buf_Q , D, CLK, DE, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXBP_FUNCTIONAL_V |
//name : main_0
//input : input_rs232_rx:16
//input : input_gps_rx:16
//input : input_gps_count:16
//output : output_freq_out:16
//output : output_am_out:16
//output : output_ctl_out:16
//output : output_rs232_tx:16
//output : output_gps_tx:16
//output : output_leds:16
//source_file : /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c
///+============================================================================+
///| |
///| This file was generated by Chips |
///| |
///| Chips |
///| |
///| http://github.com/dawsonjon/Chips-2.0 |
///| |
///| Python powered |
///+============================================================================+
module main_0(input_rs232_rx,input_gps_rx,input_gps_count,input_rs232_rx_stb,input_gps_rx_stb,input_gps_count_stb,output_freq_out_ack,output_am_out_ack,output_ctl_out_ack,output_rs232_tx_ack,output_gps_tx_ack,output_leds_ack,clk,rst,output_freq_out,output_am_out,output_ctl_out,output_rs232_tx,output_gps_tx,output_leds,output_freq_out_stb,output_am_out_stb,output_ctl_out_stb,output_rs232_tx_stb,output_gps_tx_stb,output_leds_stb,input_rs232_rx_ack,input_gps_rx_ack,input_gps_count_ack,exception);
integer file_count;
parameter stop = 4'd0,
instruction_fetch = 4'd1,
operand_fetch = 4'd2,
execute = 4'd3,
load = 4'd4,
wait_state = 4'd5,
read = 4'd6,
write = 4'd7,
unsigned_divide = 4'd8,
unsigned_modulo = 4'd9,
multiply = 4'd10;
input [31:0] input_rs232_rx;
input [31:0] input_gps_rx;
input [31:0] input_gps_count;
input input_rs232_rx_stb;
input input_gps_rx_stb;
input input_gps_count_stb;
input output_freq_out_ack;
input output_am_out_ack;
input output_ctl_out_ack;
input output_rs232_tx_ack;
input output_gps_tx_ack;
input output_leds_ack;
input clk;
input rst;
output [31:0] output_freq_out;
output [31:0] output_am_out;
output [31:0] output_ctl_out;
output [31:0] output_rs232_tx;
output [31:0] output_gps_tx;
output [31:0] output_leds;
output output_freq_out_stb;
output output_am_out_stb;
output output_ctl_out_stb;
output output_rs232_tx_stb;
output output_gps_tx_stb;
output output_leds_stb;
output input_rs232_rx_ack;
output input_gps_rx_ack;
output input_gps_count_ack;
reg [31:0] timer;
reg [63:0] timer_clock;
reg [15:0] program_counter;
reg [15:0] program_counter_1;
reg [15:0] program_counter_2;
reg [44:0] instruction;
reg [4:0] opcode_2;
reg [3:0] a;
reg [3:0] b;
reg [3:0] z;
reg write_enable;
reg [3:0] address_a_2;
reg [3:0] address_b_2;
reg [3:0] address_z_2;
reg [3:0] address_z_3;
reg [31:0] load_data;
reg [31:0] write_output;
reg [31:0] write_value;
reg [31:0] read_input;
reg [15:0] literal_2;
reg [31:0] a_hi;
reg [31:0] b_hi;
reg [31:0] a_lo;
reg [31:0] b_lo;
reg [63:0] long_result;
reg [31:0] result;
reg [15:0] address;
reg [31:0] data_out;
reg [31:0] data_in;
reg [31:0] carry;
reg [31:0] s_output_freq_out_stb;
reg [31:0] s_output_am_out_stb;
reg [31:0] s_output_ctl_out_stb;
reg [31:0] s_output_rs232_tx_stb;
reg [31:0] s_output_gps_tx_stb;
reg [31:0] s_output_leds_stb;
reg [31:0] s_output_freq_out;
reg [31:0] s_output_am_out;
reg [31:0] s_output_ctl_out;
reg [31:0] s_output_rs232_tx;
reg [31:0] s_output_gps_tx;
reg [31:0] s_output_leds;
reg [31:0] s_input_rs232_rx_ack;
reg [31:0] s_input_gps_rx_ack;
reg [31:0] s_input_gps_count_ack;
reg [10:0] state;
output reg exception;
reg [28:0] instructions [1485:0];
reg [31:0] memory [4096:0];
reg [31:0] registers [15:0];
wire [31:0] operand_a;
wire [31:0] operand_b;
wire [31:0] register_a;
wire [31:0] register_b;
wire [15:0] literal;
wire [4:0] opcode;
wire [3:0] address_a;
wire [3:0] address_b;
wire [3:0] address_z;
wire [15:0] load_address;
wire [15:0] store_address;
wire [31:0] store_data;
wire store_enable;
reg [31:0] shifter;
reg [32:0] difference;
reg [31:0] divisor;
reg [31:0] dividend;
reg [31:0] quotient;
reg [31:0] remainder;
reg quotient_sign;
reg dividend_sign;
reg [31:0] product_a;
reg [31:0] product_b;
reg [31:0] product_c;
reg [31:0] product_d;
//////////////////////////////////////////////////////////////////////////////
// INSTRUCTION INITIALIZATION
//
// Initialise the contents of the instruction memory
//
// Intruction Set
// ==============
// 0 {'literal': True, 'op': 'literal'}
// 1 {'literal': True, 'op': 'addl'}
// 2 {'literal': False, 'op': 'store'}
// 3 {'literal': True, 'op': 'call'}
// 4 {'literal': False, 'op': 'stop'}
// 5 {'literal': False, 'op': 'load'}
// 6 {'literal': False, 'op': 'equal'}
// 7 {'literal': True, 'op': 'jmp_if_true'}
// 8 {'literal': True, 'op': 'goto'}
// 9 {'literal': False, 'op': 'read'}
// 10 {'literal': False, 'op': 'write'}
// 11 {'literal': False, 'op': 'timer_low'}
// 12 {'literal': False, 'op': 'subtract'}
// 13 {'literal': False, 'op': 'unsigned_greater'}
// 14 {'literal': True, 'op': 'jmp_if_false'}
// 15 {'literal': False, 'op': 'shift_left'}
// 16 {'literal': False, 'op': 'or'}
// 17 {'literal': True, 'op': 'literal_hi'}
// 18 {'literal': False, 'op': 'add'}
// 19 {'literal': False, 'op': 'return'}
// 20 {'literal': False, 'op': 'wait_clocks'}
// 21 {'literal': False, 'op': 'ready'}
// 22 {'literal': False, 'op': 'unsigned_divide'}
// 23 {'literal': False, 'op': 'and'}
// 24 {'literal': False, 'op': 'a_lo'}
// 25 {'literal': False, 'line': 26, 'file': '/usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h', 'op': 'report'}
// 26 {'literal': False, 'op': 'unsigned_modulo'}
// 27 {'literal': False, 'op': 'multiply'}
// 28 {'literal': False, 'op': 'greater_equal'}
// 29 {'literal': False, 'op': 'shift_right'}
// 30 {'literal': False, 'op': 'greater'}
// 31 {'literal': False, 'op': 'unsigned_shift_right'}
// Intructions
// ===========
initial
begin
instructions[0] = {5'd0, 4'd3, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 144 {'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 144, 'op': 'literal'}
instructions[1] = {5'd0, 4'd4, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 144 {'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 144, 'op': 'literal'}
instructions[2] = {5'd1, 4'd3, 4'd3, 16'd41};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 144 {'a': 3, 'literal': 41, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 144, 'op': 'addl'}
instructions[3] = {5'd0, 4'd8, 4'd0, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'literal': 10, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'literal'}
instructions[4] = {5'd0, 4'd2, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'literal'}
instructions[5] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'store'}
instructions[6] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'literal'}
instructions[7] = {5'd0, 4'd2, 4'd0, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'literal': 1, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'literal'}
instructions[8] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'store'}
instructions[9] = {5'd0, 4'd8, 4'd0, 16'd4};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 5 {'literal': 4, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 5, 'op': 'literal'}
instructions[10] = {5'd0, 4'd2, 4'd0, 16'd2};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 5 {'literal': 2, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 5, 'op': 'literal'}
instructions[11] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 5 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 5, 'op': 'store'}
instructions[12] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 1 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 1, 'op': 'literal'}
instructions[13] = {5'd0, 4'd2, 4'd0, 16'd4};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 1 {'literal': 4, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 1, 'op': 'literal'}
instructions[14] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 1 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 1, 'op': 'store'}
instructions[15] = {5'd0, 4'd8, 4'd0, 16'd62};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'literal': 62, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'literal'}
instructions[16] = {5'd0, 4'd2, 4'd0, 16'd5};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'literal': 5, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'literal'}
instructions[17] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'store'}
instructions[18] = {5'd0, 4'd8, 4'd0, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'literal': 10, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'literal'}
instructions[19] = {5'd0, 4'd2, 4'd0, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'literal': 6, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'literal'}
instructions[20] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'store'}
instructions[21] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'literal'}
instructions[22] = {5'd0, 4'd2, 4'd0, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'literal': 7, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'literal'}
instructions[23] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'store'}
instructions[24] = {5'd0, 4'd8, 4'd0, 16'd2};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 3 {'literal': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 3, 'op': 'literal'}
instructions[25] = {5'd0, 4'd2, 4'd0, 16'd9};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 3 {'literal': 9, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 3, 'op': 'literal'}
instructions[26] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 3 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 3, 'op': 'store'}
instructions[27] = {5'd0, 4'd8, 4'd0, 16'd5};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 6 {'literal': 5, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 6, 'op': 'literal'}
instructions[28] = {5'd0, 4'd2, 4'd0, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 6 {'literal': 10, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 6, 'op': 'literal'}
instructions[29] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 6 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 6, 'op': 'store'}
instructions[30] = {5'd0, 4'd8, 4'd0, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5 {'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5, 'op': 'literal'}
instructions[31] = {5'd0, 4'd2, 4'd0, 16'd11};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5 {'literal': 11, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5, 'op': 'literal'}
instructions[32] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 5, 'op': 'store'}
instructions[33] = {5'd0, 4'd8, 4'd0, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 7 {'literal': 6, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 7, 'op': 'literal'}
instructions[34] = {5'd0, 4'd2, 4'd0, 16'd13};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 7 {'literal': 13, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 7, 'op': 'literal'}
instructions[35] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 7 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 7, 'op': 'store'}
instructions[36] = {5'd0, 4'd8, 4'd0, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'literal': 10, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'literal'}
instructions[37] = {5'd0, 4'd2, 4'd0, 16'd14};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'literal': 14, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'literal'}
instructions[38] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'store'}
instructions[39] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'literal'}
instructions[40] = {5'd0, 4'd2, 4'd0, 16'd15};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'literal': 15, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'literal'}
instructions[41] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'store'}
instructions[42] = {5'd0, 4'd8, 4'd0, 16'd62};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'literal': 62, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'literal'}
instructions[43] = {5'd0, 4'd2, 4'd0, 16'd16};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'literal': 16, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'literal'}
instructions[44] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'store'}
instructions[45] = {5'd0, 4'd8, 4'd0, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'literal': 10, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'literal'}
instructions[46] = {5'd0, 4'd2, 4'd0, 16'd17};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'literal': 17, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'literal'}
instructions[47] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'store'}
instructions[48] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'literal'}
instructions[49] = {5'd0, 4'd2, 4'd0, 16'd18};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'literal': 18, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'literal'}
instructions[50] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'store'}
instructions[51] = {5'd0, 4'd8, 4'd0, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 9 {'literal': 8, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 9, 'op': 'literal'}
instructions[52] = {5'd0, 4'd2, 4'd0, 16'd19};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 9 {'literal': 19, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 9, 'op': 'literal'}
instructions[53] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 9 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 9, 'op': 'store'}
instructions[54] = {5'd0, 4'd8, 4'd0, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'literal': 10, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'literal'}
instructions[55] = {5'd0, 4'd2, 4'd0, 16'd20};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'literal': 20, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'literal'}
instructions[56] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'store'}
instructions[57] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'literal'}
instructions[58] = {5'd0, 4'd2, 4'd0, 16'd21};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'literal': 21, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'literal'}
instructions[59] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'store'}
instructions[60] = {5'd0, 4'd8, 4'd0, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'literal': 10, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'literal'}
instructions[61] = {5'd0, 4'd2, 4'd0, 16'd22};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'literal': 22, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'literal'}
instructions[62] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'store'}
instructions[63] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'literal'}
instructions[64] = {5'd0, 4'd2, 4'd0, 16'd23};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'literal': 23, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'literal'}
instructions[65] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'store'}
instructions[66] = {5'd0, 4'd8, 4'd0, 16'd62};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'literal': 62, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'literal'}
instructions[67] = {5'd0, 4'd2, 4'd0, 16'd24};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'literal': 24, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'literal'}
instructions[68] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'store'}
instructions[69] = {5'd0, 4'd8, 4'd0, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'literal': 10, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'literal'}
instructions[70] = {5'd0, 4'd2, 4'd0, 16'd25};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'literal': 25, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'literal'}
instructions[71] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'store'}
instructions[72] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'literal'}
instructions[73] = {5'd0, 4'd2, 4'd0, 16'd26};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'literal': 26, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'literal'}
instructions[74] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'store'}
instructions[75] = {5'd0, 4'd8, 4'd0, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'literal': 10, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'literal'}
instructions[76] = {5'd0, 4'd2, 4'd0, 16'd27};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'literal': 27, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'literal'}
instructions[77] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'store'}
instructions[78] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'literal'}
instructions[79] = {5'd0, 4'd2, 4'd0, 16'd28};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'literal': 28, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'literal'}
instructions[80] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'store'}
instructions[81] = {5'd0, 4'd8, 4'd0, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 4 {'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 4, 'op': 'literal'}
instructions[82] = {5'd0, 4'd2, 4'd0, 16'd29};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 4 {'literal': 29, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 4, 'op': 'literal'}
instructions[83] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 4 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 4, 'op': 'store'}
instructions[84] = {5'd0, 4'd8, 4'd0, 16'd62};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'literal': 62, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'literal'}
instructions[85] = {5'd0, 4'd2, 4'd0, 16'd30};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'literal': 30, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'literal'}
instructions[86] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'store'}
instructions[87] = {5'd0, 4'd8, 4'd0, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'literal': 10, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'literal'}
instructions[88] = {5'd0, 4'd2, 4'd0, 16'd31};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'literal': 31, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'literal'}
instructions[89] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'store'}
instructions[90] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'literal'}
instructions[91] = {5'd0, 4'd2, 4'd0, 16'd32};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'literal': 32, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'literal'}
instructions[92] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'store'}
instructions[93] = {5'd0, 4'd8, 4'd0, 16'd3};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 4 {'literal': 3, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 4, 'op': 'literal'}
instructions[94] = {5'd0, 4'd2, 4'd0, 16'd33};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 4 {'literal': 33, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 4, 'op': 'literal'}
instructions[95] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 4 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 4, 'op': 'store'}
instructions[96] = {5'd0, 4'd8, 4'd0, 16'd62};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'literal': 62, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'literal'}
instructions[97] = {5'd0, 4'd2, 4'd0, 16'd35};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'literal': 35, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'literal'}
instructions[98] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'store'}
instructions[99] = {5'd0, 4'd8, 4'd0, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'literal': 10, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'literal'}
instructions[100] = {5'd0, 4'd2, 4'd0, 16'd36};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'literal': 36, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'literal'}
instructions[101] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'store'}
instructions[102] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'literal'}
instructions[103] = {5'd0, 4'd2, 4'd0, 16'd37};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'literal': 37, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'literal'}
instructions[104] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'store'}
instructions[105] = {5'd0, 4'd8, 4'd0, 16'd62};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'literal': 62, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'literal'}
instructions[106] = {5'd0, 4'd2, 4'd0, 16'd38};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'literal': 38, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'literal'}
instructions[107] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'store'}
instructions[108] = {5'd0, 4'd8, 4'd0, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'literal': 10, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'literal'}
instructions[109] = {5'd0, 4'd2, 4'd0, 16'd39};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'literal': 39, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'literal'}
instructions[110] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'store'}
instructions[111] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'literal'}
instructions[112] = {5'd0, 4'd2, 4'd0, 16'd40};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'literal': 40, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'literal'}
instructions[113] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'store'}
instructions[114] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 144 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 144, 'op': 'addl'}
instructions[115] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 144 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 144, 'op': 'addl'}
instructions[116] = {5'd3, 4'd6, 4'd0, 16'd118};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 144 {'z': 6, 'label': 118, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 144, 'op': 'call'}
instructions[117] = {5'd4, 4'd0, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 144 {'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 144, 'op': 'stop'}
instructions[118] = {5'd1, 4'd3, 4'd3, 16'd38};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 50 {'a': 3, 'literal': 38, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 50, 'op': 'addl'}
instructions[119] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 52 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 52, 'op': 'literal'}
instructions[120] = {5'd1, 4'd2, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 52 {'a': 4, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 52, 'op': 'addl'}
instructions[121] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 52 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 52, 'op': 'store'}
instructions[122] = {5'd0, 4'd8, 4'd0, 16'd8333};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 53 {'literal': 8333, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 53, 'op': 'literal'}
instructions[123] = {5'd1, 4'd2, 4'd4, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 53 {'a': 4, 'literal': 1, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 53, 'op': 'addl'}
instructions[124] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 53 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 53, 'op': 'store'}
instructions[125] = {5'd0, 4'd8, 4'd0, 16'd105};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 54 {'literal': 105, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 54, 'op': 'literal'}
instructions[126] = {5'd1, 4'd2, 4'd4, 16'd2};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 54 {'a': 4, 'literal': 2, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 54, 'op': 'addl'}
instructions[127] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 54 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 54, 'op': 'store'}
instructions[128] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 55 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 55, 'op': 'literal'}
instructions[129] = {5'd1, 4'd2, 4'd4, 16'd3};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 55 {'a': 4, 'literal': 3, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 55, 'op': 'addl'}
instructions[130] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 55 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 55, 'op': 'store'}
instructions[131] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 56 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 56, 'op': 'literal'}
instructions[132] = {5'd1, 4'd2, 4'd4, 16'd4};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 56 {'a': 4, 'literal': 4, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 56, 'op': 'addl'}
instructions[133] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 56 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 56, 'op': 'store'}
instructions[134] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 57 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 57, 'op': 'literal'}
instructions[135] = {5'd1, 4'd2, 4'd4, 16'd5};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 57 {'a': 4, 'literal': 5, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 57, 'op': 'addl'}
instructions[136] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 57 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 57, 'op': 'store'}
instructions[137] = {5'd0, 4'd8, 4'd0, 16'd13};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 61 {'literal': 13, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 61, 'op': 'literal'}
instructions[138] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 61 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 61, 'op': 'addl'}
instructions[139] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 61 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 61, 'op': 'load'}
instructions[140] = {5'd0, 4'd2, 4'd0, 16'd11};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 61 {'literal': 11, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 61, 'op': 'literal'}
instructions[141] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 61 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 61, 'op': 'store'}
instructions[142] = {5'd0, 4'd8, 4'd0, 16'd4};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 62 {'literal': 4, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 62, 'op': 'literal'}
instructions[143] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 62 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 62, 'op': 'addl'}
instructions[144] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 62 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 62, 'op': 'load'}
instructions[145] = {5'd0, 4'd2, 4'd0, 16'd29};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 62 {'literal': 29, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 62, 'op': 'literal'}
instructions[146] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 62 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 62, 'op': 'store'}
instructions[147] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63, 'op': 'store'}
instructions[148] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63, 'op': 'addl'}
instructions[149] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63, 'op': 'store'}
instructions[150] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63, 'op': 'addl'}
instructions[151] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63, 'op': 'addl'}
instructions[152] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63, 'op': 'addl'}
instructions[153] = {5'd3, 4'd6, 4'd0, 16'd797};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63 {'z': 6, 'label': 797, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63, 'op': 'call'}
instructions[154] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63, 'op': 'addl'}
instructions[155] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[156] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63, 'op': 'load'}
instructions[157] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[158] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63, 'op': 'load'}
instructions[159] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 63, 'op': 'addl'}
instructions[160] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67, 'op': 'store'}
instructions[161] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67, 'op': 'addl'}
instructions[162] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67, 'op': 'store'}
instructions[163] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67, 'op': 'addl'}
instructions[164] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67, 'op': 'addl'}
instructions[165] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67, 'op': 'addl'}
instructions[166] = {5'd3, 4'd6, 4'd0, 16'd832};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67 {'z': 6, 'label': 832, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67, 'op': 'call'}
instructions[167] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67, 'op': 'addl'}
instructions[168] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[169] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67, 'op': 'load'}
instructions[170] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[171] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67, 'op': 'load'}
instructions[172] = {5'd0, 4'd2, 4'd0, 16'd12};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67 {'literal': 12, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67, 'op': 'literal'}
instructions[173] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67, 'op': 'load'}
instructions[174] = {5'd1, 4'd2, 4'd4, 16'd9};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67 {'a': 4, 'literal': 9, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67, 'op': 'addl'}
instructions[175] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 67, 'op': 'store'}
instructions[176] = {5'd1, 4'd8, 4'd4, 16'd9};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 4, 'literal': 9, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'addl'}
instructions[177] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'addl'}
instructions[178] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'load'}
instructions[179] = {5'd0, 4'd0, 4'd0, 16'd97};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'literal': 97, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'literal'}
instructions[180] = {5'd6, 4'd0, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 8, 'b': 0, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'equal'}
instructions[181] = {5'd7, 4'd0, 4'd0, 16'd570};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 0, 'label': 570, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'jmp_if_true'}
instructions[182] = {5'd0, 4'd0, 4'd0, 16'd98};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'literal': 98, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'literal'}
instructions[183] = {5'd6, 4'd0, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 8, 'b': 0, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'equal'}
instructions[184] = {5'd7, 4'd0, 4'd0, 16'd713};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 0, 'label': 713, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'jmp_if_true'}
instructions[185] = {5'd0, 4'd0, 4'd0, 16'd99};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'literal': 99, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'literal'}
instructions[186] = {5'd6, 4'd0, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 8, 'b': 0, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'equal'}
instructions[187] = {5'd7, 4'd0, 4'd0, 16'd491};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 0, 'label': 491, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'jmp_if_true'}
instructions[188] = {5'd0, 4'd0, 4'd0, 16'd100};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'literal': 100, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'literal'}
instructions[189] = {5'd6, 4'd0, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 8, 'b': 0, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'equal'}
instructions[190] = {5'd7, 4'd0, 4'd0, 16'd424};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 0, 'label': 424, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'jmp_if_true'}
instructions[191] = {5'd0, 4'd0, 4'd0, 16'd102};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'literal': 102, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'literal'}
instructions[192] = {5'd6, 4'd0, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 8, 'b': 0, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'equal'}
instructions[193] = {5'd7, 4'd0, 4'd0, 16'd278};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 0, 'label': 278, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'jmp_if_true'}
instructions[194] = {5'd0, 4'd0, 4'd0, 16'd103};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'literal': 103, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'literal'}
instructions[195] = {5'd6, 4'd0, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 8, 'b': 0, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'equal'}
instructions[196] = {5'd7, 4'd0, 4'd0, 16'd221};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 0, 'label': 221, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'jmp_if_true'}
instructions[197] = {5'd0, 4'd0, 4'd0, 16'd115};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'literal': 115, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'literal'}
instructions[198] = {5'd6, 4'd0, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 8, 'b': 0, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'equal'}
instructions[199] = {5'd7, 4'd0, 4'd0, 16'd357};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 0, 'label': 357, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'jmp_if_true'}
instructions[200] = {5'd0, 4'd0, 4'd0, 16'd62};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'literal': 62, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'literal'}
instructions[201] = {5'd6, 4'd0, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 8, 'b': 0, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'equal'}
instructions[202] = {5'd7, 4'd0, 4'd0, 16'd204};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'a': 0, 'label': 204, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'jmp_if_true'}
instructions[203] = {5'd8, 4'd0, 4'd0, 16'd793};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69 {'label': 793, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 69, 'op': 'goto'}
instructions[204] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'store'}
instructions[205] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'addl'}
instructions[206] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'store'}
instructions[207] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'addl'}
instructions[208] = {5'd0, 4'd8, 4'd0, 16'd24};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'literal': 24, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'literal'}
instructions[209] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'store'}
instructions[210] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'addl'}
instructions[211] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'addl'}
instructions[212] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'addl'}
instructions[213] = {5'd3, 4'd6, 4'd0, 16'd842};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'z': 6, 'label': 842, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'call'}
instructions[214] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'addl'}
instructions[215] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[216] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'load'}
instructions[217] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[218] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'load'}
instructions[219] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 73, 'op': 'addl'}
instructions[220] = {5'd8, 4'd0, 4'd0, 16'd793};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 74 {'label': 793, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 74, 'op': 'goto'}
instructions[221] = {5'd0, 4'd8, 4'd0, 16'd9};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 78 {'literal': 9, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 78, 'op': 'literal'}
instructions[222] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 78 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 78, 'op': 'addl'}
instructions[223] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 78 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 78, 'op': 'load'}
instructions[224] = {5'd9, 4'd8, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 78 {'a': 8, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 78, 'op': 'read'}
instructions[225] = {5'd1, 4'd2, 4'd4, 16'd5};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 78 {'a': 4, 'literal': 5, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 78, 'op': 'addl'}
instructions[226] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 78 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 78, 'op': 'store'}
instructions[227] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'op': 'store'}
instructions[228] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'op': 'addl'}
instructions[229] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'op': 'store'}
instructions[230] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'op': 'addl'}
instructions[231] = {5'd1, 4'd8, 4'd4, 16'd5};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'a': 4, 'literal': 5, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'op': 'addl'}
instructions[232] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'op': 'addl'}
instructions[233] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'op': 'load'}
instructions[234] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'op': 'store'}
instructions[235] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'op': 'addl'}
instructions[236] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'op': 'addl'}
instructions[237] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'op': 'addl'}
instructions[238] = {5'd3, 4'd6, 4'd0, 16'd933};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'z': 6, 'label': 933, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'op': 'call'}
instructions[239] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'op': 'addl'}
instructions[240] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[241] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'op': 'load'}
instructions[242] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[243] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'op': 'load'}
instructions[244] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 79, 'op': 'addl'}
instructions[245] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'store'}
instructions[246] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'addl'}
instructions[247] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'store'}
instructions[248] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'addl'}
instructions[249] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'literal'}
instructions[250] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'store'}
instructions[251] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'addl'}
instructions[252] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'addl'}
instructions[253] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'addl'}
instructions[254] = {5'd3, 4'd6, 4'd0, 16'd842};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'z': 6, 'label': 842, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'call'}
instructions[255] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'addl'}
instructions[256] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[257] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'load'}
instructions[258] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[259] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'load'}
instructions[260] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 80, 'op': 'addl'}
instructions[261] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'store'}
instructions[262] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'addl'}
instructions[263] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'store'}
instructions[264] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'addl'}
instructions[265] = {5'd0, 4'd8, 4'd0, 16'd5};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'literal': 5, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'literal'}
instructions[266] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'store'}
instructions[267] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'addl'}
instructions[268] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'addl'}
instructions[269] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'addl'}
instructions[270] = {5'd3, 4'd6, 4'd0, 16'd842};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'z': 6, 'label': 842, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'call'}
instructions[271] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'addl'}
instructions[272] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[273] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'load'}
instructions[274] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[275] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'load'}
instructions[276] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 81, 'op': 'addl'}
instructions[277] = {5'd8, 4'd0, 4'd0, 16'd793};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 82 {'label': 793, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 82, 'op': 'goto'}
instructions[278] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86, 'op': 'store'}
instructions[279] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86, 'op': 'addl'}
instructions[280] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86, 'op': 'store'}
instructions[281] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86, 'op': 'addl'}
instructions[282] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86, 'op': 'addl'}
instructions[283] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86, 'op': 'addl'}
instructions[284] = {5'd3, 4'd6, 4'd0, 16'd1123};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86 {'z': 6, 'label': 1123, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86, 'op': 'call'}
instructions[285] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86, 'op': 'addl'}
instructions[286] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[287] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86, 'op': 'load'}
instructions[288] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[289] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86, 'op': 'load'}
instructions[290] = {5'd0, 4'd2, 4'd0, 16'd34};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86 {'literal': 34, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86, 'op': 'literal'}
instructions[291] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86, 'op': 'load'}
instructions[292] = {5'd1, 4'd2, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86 {'a': 4, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86, 'op': 'addl'}
instructions[293] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 86, 'op': 'store'}
instructions[294] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'op': 'store'}
instructions[295] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'op': 'addl'}
instructions[296] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'op': 'store'}
instructions[297] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'op': 'addl'}
instructions[298] = {5'd1, 4'd8, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'a': 4, 'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'op': 'addl'}
instructions[299] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'op': 'addl'}
instructions[300] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'op': 'load'}
instructions[301] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'op': 'store'}
instructions[302] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'op': 'addl'}
instructions[303] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'op': 'addl'}
instructions[304] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'op': 'addl'}
instructions[305] = {5'd3, 4'd6, 4'd0, 16'd933};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'z': 6, 'label': 933, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'op': 'call'}
instructions[306] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'op': 'addl'}
instructions[307] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[308] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'op': 'load'}
instructions[309] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[310] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'op': 'load'}
instructions[311] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 87, 'op': 'addl'}
instructions[312] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'store'}
instructions[313] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'addl'}
instructions[314] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'store'}
instructions[315] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'addl'}
instructions[316] = {5'd0, 4'd8, 4'd0, 16'd14};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'literal': 14, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'literal'}
instructions[317] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'store'}
instructions[318] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'addl'}
instructions[319] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'addl'}
instructions[320] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'addl'}
instructions[321] = {5'd3, 4'd6, 4'd0, 16'd842};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'z': 6, 'label': 842, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'call'}
instructions[322] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'addl'}
instructions[323] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[324] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'load'}
instructions[325] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[326] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'load'}
instructions[327] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 88, 'op': 'addl'}
instructions[328] = {5'd0, 4'd8, 4'd0, 16'd33};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89 {'literal': 33, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89, 'op': 'literal'}
instructions[329] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89, 'op': 'addl'}
instructions[330] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89, 'op': 'load'}
instructions[331] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89, 'op': 'store'}
instructions[332] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89, 'op': 'addl'}
instructions[333] = {5'd1, 4'd8, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89 {'a': 4, 'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89, 'op': 'addl'}
instructions[334] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89, 'op': 'addl'}
instructions[335] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89, 'op': 'load'}
instructions[336] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[337] = {5'd5, 4'd0, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89 {'a': 3, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89, 'op': 'load'}
instructions[338] = {5'd10, 4'd0, 4'd0, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89 {'a': 0, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89, 'op': 'write'}
instructions[339] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 89, 'op': 'addl'}
instructions[340] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'store'}
instructions[341] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'addl'}
instructions[342] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'store'}
instructions[343] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'addl'}
instructions[344] = {5'd0, 4'd8, 4'd0, 16'd38};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'literal': 38, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'literal'}
instructions[345] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'store'}
instructions[346] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'addl'}
instructions[347] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'addl'}
instructions[348] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'addl'}
instructions[349] = {5'd3, 4'd6, 4'd0, 16'd842};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'z': 6, 'label': 842, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'call'}
instructions[350] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'addl'}
instructions[351] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[352] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'load'}
instructions[353] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[354] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'load'}
instructions[355] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 90, 'op': 'addl'}
instructions[356] = {5'd8, 4'd0, 4'd0, 16'd793};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 91 {'label': 793, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 91, 'op': 'goto'}
instructions[357] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95, 'op': 'store'}
instructions[358] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95, 'op': 'addl'}
instructions[359] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95, 'op': 'store'}
instructions[360] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95, 'op': 'addl'}
instructions[361] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95, 'op': 'addl'}
instructions[362] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95, 'op': 'addl'}
instructions[363] = {5'd3, 4'd6, 4'd0, 16'd1123};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95 {'z': 6, 'label': 1123, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95, 'op': 'call'}
instructions[364] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95, 'op': 'addl'}
instructions[365] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[366] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95, 'op': 'load'}
instructions[367] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[368] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95, 'op': 'load'}
instructions[369] = {5'd0, 4'd2, 4'd0, 16'd34};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95 {'literal': 34, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95, 'op': 'literal'}
instructions[370] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95, 'op': 'load'}
instructions[371] = {5'd1, 4'd2, 4'd4, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95 {'a': 4, 'literal': 1, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95, 'op': 'addl'}
instructions[372] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 95, 'op': 'store'}
instructions[373] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'op': 'store'}
instructions[374] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'op': 'addl'}
instructions[375] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'op': 'store'}
instructions[376] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'op': 'addl'}
instructions[377] = {5'd1, 4'd8, 4'd4, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'a': 4, 'literal': 1, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'op': 'addl'}
instructions[378] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'op': 'addl'}
instructions[379] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'op': 'load'}
instructions[380] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'op': 'store'}
instructions[381] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'op': 'addl'}
instructions[382] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'op': 'addl'}
instructions[383] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'op': 'addl'}
instructions[384] = {5'd3, 4'd6, 4'd0, 16'd933};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'z': 6, 'label': 933, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'op': 'call'}
instructions[385] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'op': 'addl'}
instructions[386] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[387] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'op': 'load'}
instructions[388] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[389] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'op': 'load'}
instructions[390] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 96, 'op': 'addl'}
instructions[391] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'store'}
instructions[392] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'addl'}
instructions[393] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'store'}
instructions[394] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'addl'}
instructions[395] = {5'd0, 4'd8, 4'd0, 16'd22};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'literal': 22, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'literal'}
instructions[396] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'store'}
instructions[397] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'addl'}
instructions[398] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'addl'}
instructions[399] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'addl'}
instructions[400] = {5'd3, 4'd6, 4'd0, 16'd842};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'z': 6, 'label': 842, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'call'}
instructions[401] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'addl'}
instructions[402] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[403] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'load'}
instructions[404] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[405] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'load'}
instructions[406] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 97, 'op': 'addl'}
instructions[407] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'store'}
instructions[408] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'addl'}
instructions[409] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'store'}
instructions[410] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'addl'}
instructions[411] = {5'd0, 4'd8, 4'd0, 16'd30};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'literal': 30, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'literal'}
instructions[412] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'store'}
instructions[413] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'addl'}
instructions[414] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'addl'}
instructions[415] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'addl'}
instructions[416] = {5'd3, 4'd6, 4'd0, 16'd842};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'z': 6, 'label': 842, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'call'}
instructions[417] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'addl'}
instructions[418] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[419] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'load'}
instructions[420] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[421] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'load'}
instructions[422] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 98, 'op': 'addl'}
instructions[423] = {5'd8, 4'd0, 4'd0, 16'd793};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 99 {'label': 793, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 99, 'op': 'goto'}
instructions[424] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103, 'op': 'store'}
instructions[425] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103, 'op': 'addl'}
instructions[426] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103, 'op': 'store'}
instructions[427] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103, 'op': 'addl'}
instructions[428] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103, 'op': 'addl'}
instructions[429] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103, 'op': 'addl'}
instructions[430] = {5'd3, 4'd6, 4'd0, 16'd1123};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103 {'z': 6, 'label': 1123, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103, 'op': 'call'}
instructions[431] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103, 'op': 'addl'}
instructions[432] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[433] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103, 'op': 'load'}
instructions[434] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[435] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103, 'op': 'load'}
instructions[436] = {5'd0, 4'd2, 4'd0, 16'd34};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103 {'literal': 34, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103, 'op': 'literal'}
instructions[437] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103, 'op': 'load'}
instructions[438] = {5'd1, 4'd2, 4'd4, 16'd2};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103 {'a': 4, 'literal': 2, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103, 'op': 'addl'}
instructions[439] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 103, 'op': 'store'}
instructions[440] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'op': 'store'}
instructions[441] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'op': 'addl'}
instructions[442] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'op': 'store'}
instructions[443] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'op': 'addl'}
instructions[444] = {5'd1, 4'd8, 4'd4, 16'd2};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'a': 4, 'literal': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'op': 'addl'}
instructions[445] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'op': 'addl'}
instructions[446] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'op': 'load'}
instructions[447] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'op': 'store'}
instructions[448] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'op': 'addl'}
instructions[449] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'op': 'addl'}
instructions[450] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'op': 'addl'}
instructions[451] = {5'd3, 4'd6, 4'd0, 16'd933};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'z': 6, 'label': 933, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'op': 'call'}
instructions[452] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'op': 'addl'}
instructions[453] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[454] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'op': 'load'}
instructions[455] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[456] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'op': 'load'}
instructions[457] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 104, 'op': 'addl'}
instructions[458] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'store'}
instructions[459] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'addl'}
instructions[460] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'store'}
instructions[461] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'addl'}
instructions[462] = {5'd0, 4'd8, 4'd0, 16'd27};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'literal': 27, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'literal'}
instructions[463] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'store'}
instructions[464] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'addl'}
instructions[465] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'addl'}
instructions[466] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'addl'}
instructions[467] = {5'd3, 4'd6, 4'd0, 16'd842};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'z': 6, 'label': 842, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'call'}
instructions[468] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'addl'}
instructions[469] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[470] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'load'}
instructions[471] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[472] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'load'}
instructions[473] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 105, 'op': 'addl'}
instructions[474] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'store'}
instructions[475] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'addl'}
instructions[476] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'store'}
instructions[477] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'addl'}
instructions[478] = {5'd0, 4'd8, 4'd0, 16'd35};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'literal': 35, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'literal'}
instructions[479] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'store'}
instructions[480] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'addl'}
instructions[481] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'addl'}
instructions[482] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'addl'}
instructions[483] = {5'd3, 4'd6, 4'd0, 16'd842};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'z': 6, 'label': 842, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'call'}
instructions[484] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'addl'}
instructions[485] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[486] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'load'}
instructions[487] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[488] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'load'}
instructions[489] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 106, 'op': 'addl'}
instructions[490] = {5'd8, 4'd0, 4'd0, 16'd793};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 107 {'label': 793, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 107, 'op': 'goto'}
instructions[491] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111, 'op': 'store'}
instructions[492] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111, 'op': 'addl'}
instructions[493] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111, 'op': 'store'}
instructions[494] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111, 'op': 'addl'}
instructions[495] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111, 'op': 'addl'}
instructions[496] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111, 'op': 'addl'}
instructions[497] = {5'd3, 4'd6, 4'd0, 16'd1123};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111 {'z': 6, 'label': 1123, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111, 'op': 'call'}
instructions[498] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111, 'op': 'addl'}
instructions[499] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[500] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111, 'op': 'load'}
instructions[501] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[502] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111, 'op': 'load'}
instructions[503] = {5'd0, 4'd2, 4'd0, 16'd34};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111 {'literal': 34, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111, 'op': 'literal'}
instructions[504] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111, 'op': 'load'}
instructions[505] = {5'd1, 4'd2, 4'd4, 16'd3};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111 {'a': 4, 'literal': 3, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111, 'op': 'addl'}
instructions[506] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 111, 'op': 'store'}
instructions[507] = {5'd0, 4'd8, 4'd0, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112 {'literal': 10, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112, 'op': 'literal'}
instructions[508] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112, 'op': 'addl'}
instructions[509] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112, 'op': 'load'}
instructions[510] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112, 'op': 'store'}
instructions[511] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112, 'op': 'addl'}
instructions[512] = {5'd1, 4'd8, 4'd4, 16'd3};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112 {'a': 4, 'literal': 3, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112, 'op': 'addl'}
instructions[513] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112, 'op': 'addl'}
instructions[514] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112, 'op': 'load'}
instructions[515] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[516] = {5'd5, 4'd0, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112 {'a': 3, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112, 'op': 'load'}
instructions[517] = {5'd10, 4'd0, 4'd0, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112 {'a': 0, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112, 'op': 'write'}
instructions[518] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 112, 'op': 'addl'}
instructions[519] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'op': 'store'}
instructions[520] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'op': 'addl'}
instructions[521] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'op': 'store'}
instructions[522] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'op': 'addl'}
instructions[523] = {5'd1, 4'd8, 4'd4, 16'd3};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'a': 4, 'literal': 3, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'op': 'addl'}
instructions[524] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'op': 'addl'}
instructions[525] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'op': 'load'}
instructions[526] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'op': 'store'}
instructions[527] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'op': 'addl'}
instructions[528] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'op': 'addl'}
instructions[529] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'op': 'addl'}
instructions[530] = {5'd3, 4'd6, 4'd0, 16'd933};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'z': 6, 'label': 933, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'op': 'call'}
instructions[531] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'op': 'addl'}
instructions[532] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[533] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'op': 'load'}
instructions[534] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[535] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'op': 'load'}
instructions[536] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 113, 'op': 'addl'}
instructions[537] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'store'}
instructions[538] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'addl'}
instructions[539] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'store'}
instructions[540] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'addl'}
instructions[541] = {5'd0, 4'd8, 4'd0, 16'd20};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'literal': 20, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'literal'}
instructions[542] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'store'}
instructions[543] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'addl'}
instructions[544] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'addl'}
instructions[545] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'addl'}
instructions[546] = {5'd3, 4'd6, 4'd0, 16'd842};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'z': 6, 'label': 842, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'call'}
instructions[547] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'addl'}
instructions[548] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[549] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'load'}
instructions[550] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[551] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'load'}
instructions[552] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 114, 'op': 'addl'}
instructions[553] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'store'}
instructions[554] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'addl'}
instructions[555] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'store'}
instructions[556] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'addl'}
instructions[557] = {5'd0, 4'd8, 4'd0, 16'd16};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'literal': 16, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'literal'}
instructions[558] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'store'}
instructions[559] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'addl'}
instructions[560] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'addl'}
instructions[561] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'addl'}
instructions[562] = {5'd3, 4'd6, 4'd0, 16'd842};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'z': 6, 'label': 842, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'call'}
instructions[563] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'addl'}
instructions[564] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[565] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'load'}
instructions[566] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[567] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'load'}
instructions[568] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 115, 'op': 'addl'}
instructions[569] = {5'd8, 4'd0, 4'd0, 16'd793};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 116 {'label': 793, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 116, 'op': 'goto'}
instructions[570] = {5'd1, 4'd8, 4'd4, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'a': 4, 'literal': 1, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'op': 'addl'}
instructions[571] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'op': 'addl'}
instructions[572] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'op': 'load'}
instructions[573] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'op': 'store'}
instructions[574] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'op': 'addl'}
instructions[575] = {5'd1, 4'd8, 4'd4, 16'd4};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'a': 4, 'literal': 4, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'op': 'addl'}
instructions[576] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'op': 'addl'}
instructions[577] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'op': 'load'}
instructions[578] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'op': 'store'}
instructions[579] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'op': 'addl'}
instructions[580] = {5'd11, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'op': 'timer_low'}
instructions[581] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[582] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'op': 'load'}
instructions[583] = {5'd12, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'op': 'subtract'}
instructions[584] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[585] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'op': 'load'}
instructions[586] = {5'd13, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'op': 'unsigned_greater'}
instructions[587] = {5'd14, 4'd0, 4'd8, 16'd592};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'a': 8, 'label': 592, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'op': 'jmp_if_false'}
instructions[588] = {5'd11, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 121 {'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 121, 'op': 'timer_low'}
instructions[589] = {5'd1, 4'd2, 4'd4, 16'd4};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 121 {'a': 4, 'literal': 4, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 121, 'op': 'addl'}
instructions[590] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 121 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 121, 'op': 'store'}
instructions[591] = {5'd8, 4'd0, 4'd0, 16'd592};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120 {'label': 592, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 120, 'op': 'goto'}
instructions[592] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123, 'op': 'store'}
instructions[593] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123, 'op': 'addl'}
instructions[594] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123, 'op': 'store'}
instructions[595] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123, 'op': 'addl'}
instructions[596] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123, 'op': 'addl'}
instructions[597] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123, 'op': 'addl'}
instructions[598] = {5'd3, 4'd6, 4'd0, 16'd832};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123 {'z': 6, 'label': 832, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123, 'op': 'call'}
instructions[599] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123, 'op': 'addl'}
instructions[600] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[601] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123, 'op': 'load'}
instructions[602] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[603] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123, 'op': 'load'}
instructions[604] = {5'd0, 4'd2, 4'd0, 16'd12};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123 {'literal': 12, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123, 'op': 'literal'}
instructions[605] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123, 'op': 'load'}
instructions[606] = {5'd1, 4'd2, 4'd4, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123 {'a': 4, 'literal': 6, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123, 'op': 'addl'}
instructions[607] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 123, 'op': 'store'}
instructions[608] = {5'd0, 4'd8, 4'd0, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'literal': 8, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'literal'}
instructions[609] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'store'}
instructions[610] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'addl'}
instructions[611] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'store'}
instructions[612] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'addl'}
instructions[613] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'store'}
instructions[614] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'addl'}
instructions[615] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'addl'}
instructions[616] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'addl'}
instructions[617] = {5'd3, 4'd6, 4'd0, 16'd832};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'z': 6, 'label': 832, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'call'}
instructions[618] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'addl'}
instructions[619] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[620] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'load'}
instructions[621] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[622] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'load'}
instructions[623] = {5'd0, 4'd2, 4'd0, 16'd12};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'literal': 12, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'literal'}
instructions[624] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'load'}
instructions[625] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[626] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'load'}
instructions[627] = {5'd15, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'shift_left'}
instructions[628] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'store'}
instructions[629] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'addl'}
instructions[630] = {5'd1, 4'd8, 4'd4, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 4, 'literal': 6, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'addl'}
instructions[631] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'addl'}
instructions[632] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'load'}
instructions[633] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[634] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'load'}
instructions[635] = {5'd16, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'or'}
instructions[636] = {5'd1, 4'd2, 4'd4, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 4, 'literal': 6, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'addl'}
instructions[637] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 124, 'op': 'store'}
instructions[638] = {5'd0, 4'd8, 4'd0, 16'd32768};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125 {'literal': 32768, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125, 'op': 'literal'}
instructions[639] = {5'd17, 4'd8, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125 {'a': 8, 'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125, 'op': 'literal_hi'}
instructions[640] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125, 'op': 'store'}
instructions[641] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125, 'op': 'addl'}
instructions[642] = {5'd1, 4'd8, 4'd4, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125 {'a': 4, 'literal': 6, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125, 'op': 'addl'}
instructions[643] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125, 'op': 'addl'}
instructions[644] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125, 'op': 'load'}
instructions[645] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[646] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125, 'op': 'load'}
instructions[647] = {5'd12, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125, 'op': 'subtract'}
instructions[648] = {5'd1, 4'd2, 4'd4, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125 {'a': 4, 'literal': 6, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125, 'op': 'addl'}
instructions[649] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 125, 'op': 'store'}
instructions[650] = {5'd1, 4'd8, 4'd4, 16'd4};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'a': 4, 'literal': 4, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'op': 'addl'}
instructions[651] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'op': 'addl'}
instructions[652] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'op': 'load'}
instructions[653] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'op': 'store'}
instructions[654] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'op': 'addl'}
instructions[655] = {5'd11, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'op': 'timer_low'}
instructions[656] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[657] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'op': 'load'}
instructions[658] = {5'd12, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'op': 'subtract'}
instructions[659] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'op': 'store'}
instructions[660] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'op': 'addl'}
instructions[661] = {5'd1, 4'd8, 4'd4, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'a': 4, 'literal': 1, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'op': 'addl'}
instructions[662] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'op': 'addl'}
instructions[663] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'op': 'load'}
instructions[664] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[665] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'op': 'load'}
instructions[666] = {5'd13, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'op': 'unsigned_greater'}
instructions[667] = {5'd14, 4'd0, 4'd8, 16'd669};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127 {'a': 8, 'label': 669, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127, 'op': 'jmp_if_false'}
instructions[668] = {5'd8, 4'd0, 4'd0, 16'd670};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127 {'label': 670, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127, 'op': 'goto'}
instructions[669] = {5'd8, 4'd0, 4'd0, 16'd671};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127 {'label': 671, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127, 'op': 'goto'}
instructions[670] = {5'd8, 4'd0, 4'd0, 16'd650};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126 {'label': 650, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 126, 'op': 'goto'}
instructions[671] = {5'd1, 4'd8, 4'd4, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127 {'a': 4, 'literal': 1, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127, 'op': 'addl'}
instructions[672] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127, 'op': 'addl'}
instructions[673] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127, 'op': 'load'}
instructions[674] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127, 'op': 'store'}
instructions[675] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127, 'op': 'addl'}
instructions[676] = {5'd1, 4'd8, 4'd4, 16'd4};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127 {'a': 4, 'literal': 4, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127, 'op': 'addl'}
instructions[677] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127, 'op': 'addl'}
instructions[678] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127, 'op': 'load'}
instructions[679] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[680] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127, 'op': 'load'}
instructions[681] = {5'd18, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127, 'op': 'add'}
instructions[682] = {5'd1, 4'd2, 4'd4, 16'd4};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127 {'a': 4, 'literal': 4, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127, 'op': 'addl'}
instructions[683] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 127, 'op': 'store'}
instructions[684] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'store'}
instructions[685] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'addl'}
instructions[686] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'store'}
instructions[687] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'addl'}
instructions[688] = {5'd1, 4'd8, 4'd4, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 4, 'literal': 6, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'addl'}
instructions[689] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'addl'}
instructions[690] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'load'}
instructions[691] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'store'}
instructions[692] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'addl'}
instructions[693] = {5'd1, 4'd8, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 4, 'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'addl'}
instructions[694] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'addl'}
instructions[695] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'load'}
instructions[696] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'store'}
instructions[697] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'addl'}
instructions[698] = {5'd1, 4'd8, 4'd4, 16'd2};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 4, 'literal': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'addl'}
instructions[699] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'addl'}
instructions[700] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'load'}
instructions[701] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'store'}
instructions[702] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'addl'}
instructions[703] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'addl'}
instructions[704] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'addl'}
instructions[705] = {5'd3, 4'd6, 4'd0, 16'd1250};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'z': 6, 'label': 1250, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'call'}
instructions[706] = {5'd1, 4'd3, 4'd3, -16'd3};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 3, 'literal': -3, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'addl'}
instructions[707] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[708] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'load'}
instructions[709] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[710] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'load'}
instructions[711] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 128, 'op': 'addl'}
instructions[712] = {5'd8, 4'd0, 4'd0, 16'd793};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 129 {'label': 793, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 129, 'op': 'goto'}
instructions[713] = {5'd0, 4'd8, 4'd0, 16'd33};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134 {'literal': 33, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134, 'op': 'literal'}
instructions[714] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134, 'op': 'addl'}
instructions[715] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134, 'op': 'load'}
instructions[716] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134, 'op': 'store'}
instructions[717] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134, 'op': 'addl'}
instructions[718] = {5'd1, 4'd8, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134 {'a': 4, 'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134, 'op': 'addl'}
instructions[719] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134, 'op': 'addl'}
instructions[720] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134, 'op': 'load'}
instructions[721] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[722] = {5'd5, 4'd0, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134 {'a': 3, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134, 'op': 'load'}
instructions[723] = {5'd10, 4'd0, 4'd0, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134 {'a': 0, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134, 'op': 'write'}
instructions[724] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 134, 'op': 'addl'}
instructions[725] = {5'd0, 4'd8, 4'd0, 16'd128};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'literal': 128, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'literal'}
instructions[726] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'store'}
instructions[727] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'addl'}
instructions[728] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'store'}
instructions[729] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'addl'}
instructions[730] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'store'}
instructions[731] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'addl'}
instructions[732] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'addl'}
instructions[733] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'addl'}
instructions[734] = {5'd3, 4'd6, 4'd0, 16'd832};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'z': 6, 'label': 832, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'call'}
instructions[735] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'addl'}
instructions[736] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[737] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'load'}
instructions[738] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[739] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'load'}
instructions[740] = {5'd0, 4'd2, 4'd0, 16'd12};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'literal': 12, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'literal'}
instructions[741] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'load'}
instructions[742] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[743] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'load'}
instructions[744] = {5'd12, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'subtract'}
instructions[745] = {5'd1, 4'd2, 4'd4, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 4, 'literal': 7, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'addl'}
instructions[746] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 135, 'op': 'store'}
instructions[747] = {5'd0, 4'd8, 4'd0, 16'd128};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'literal': 128, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'literal'}
instructions[748] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'store'}
instructions[749] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'addl'}
instructions[750] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'store'}
instructions[751] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'addl'}
instructions[752] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'store'}
instructions[753] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'addl'}
instructions[754] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'addl'}
instructions[755] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'addl'}
instructions[756] = {5'd3, 4'd6, 4'd0, 16'd832};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'z': 6, 'label': 832, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'call'}
instructions[757] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'addl'}
instructions[758] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[759] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'load'}
instructions[760] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[761] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'load'}
instructions[762] = {5'd0, 4'd2, 4'd0, 16'd12};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'literal': 12, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'literal'}
instructions[763] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'load'}
instructions[764] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[765] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'load'}
instructions[766] = {5'd12, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'subtract'}
instructions[767] = {5'd1, 4'd2, 4'd4, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 4, 'literal': 8, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'addl'}
instructions[768] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 136, 'op': 'store'}
instructions[769] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'store'}
instructions[770] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'addl'}
instructions[771] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'store'}
instructions[772] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'addl'}
instructions[773] = {5'd1, 4'd8, 4'd4, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 4, 'literal': 7, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'addl'}
instructions[774] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'addl'}
instructions[775] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'load'}
instructions[776] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'store'}
instructions[777] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'addl'}
instructions[778] = {5'd1, 4'd8, 4'd4, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 4, 'literal': 8, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'addl'}
instructions[779] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'addl'}
instructions[780] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'load'}
instructions[781] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'store'}
instructions[782] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'addl'}
instructions[783] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'addl'}
instructions[784] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'addl'}
instructions[785] = {5'd3, 4'd6, 4'd0, 16'd1396};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'z': 6, 'label': 1396, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'call'}
instructions[786] = {5'd1, 4'd3, 4'd3, -16'd2};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 3, 'literal': -2, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'addl'}
instructions[787] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[788] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'load'}
instructions[789] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[790] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'load'}
instructions[791] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 137, 'op': 'addl'}
instructions[792] = {5'd8, 4'd0, 4'd0, 16'd793};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 139 {'label': 793, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 139, 'op': 'goto'}
instructions[793] = {5'd8, 4'd0, 4'd0, 16'd160};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 65 {'label': 160, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 65, 'op': 'goto'}
instructions[794] = {5'd1, 4'd3, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 50 {'a': 4, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 50, 'op': 'addl'}
instructions[795] = {5'd1, 4'd4, 4'd7, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 50 {'a': 7, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 50, 'op': 'addl'}
instructions[796] = {5'd19, 4'd0, 4'd6, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 50 {'a': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 50, 'op': 'return'}
instructions[797] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 21 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 21, 'op': 'addl'}
instructions[798] = {5'd0, 4'd8, 4'd0, 16'd61568};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 23 {'literal': 61568, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 23, 'op': 'literal'}
instructions[799] = {5'd17, 4'd8, 4'd8, 16'd762};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 23 {'a': 8, 'literal': 762, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 23, 'op': 'literal_hi'}
instructions[800] = {5'd20, 4'd0, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 23 {'a': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 23, 'op': 'wait_clocks'}
instructions[801] = {5'd0, 4'd8, 4'd0, 16'd29};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 24 {'literal': 29, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 24, 'op': 'literal'}
instructions[802] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 24 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 24, 'op': 'addl'}
instructions[803] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 24 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 24, 'op': 'load'}
instructions[804] = {5'd21, 4'd8, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 24 {'a': 8, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 24, 'op': 'ready'}
instructions[805] = {5'd14, 4'd0, 4'd8, 16'd814};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'a': 8, 'label': 814, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'op': 'jmp_if_false'}
instructions[806] = {5'd0, 4'd8, 4'd0, 16'd29};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 25 {'literal': 29, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 25, 'op': 'literal'}
instructions[807] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 25 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 25, 'op': 'addl'}
instructions[808] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 25 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 25, 'op': 'load'}
instructions[809] = {5'd9, 4'd8, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 25 {'a': 8, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 25, 'op': 'read'}
instructions[810] = {5'd0, 4'd8, 4'd0, 16'd38528};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 26 {'literal': 38528, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 26, 'op': 'literal'}
instructions[811] = {5'd17, 4'd8, 4'd8, 16'd152};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 26 {'a': 8, 'literal': 152, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 26, 'op': 'literal_hi'}
instructions[812] = {5'd20, 4'd0, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 26 {'a': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 26, 'op': 'wait_clocks'}
instructions[813] = {5'd8, 4'd0, 4'd0, 16'd815};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'label': 815, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'op': 'goto'}
instructions[814] = {5'd8, 4'd0, 4'd0, 16'd816};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'label': 816, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'op': 'goto'}
instructions[815] = {5'd8, 4'd0, 4'd0, 16'd801};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 24 {'label': 801, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 24, 'op': 'goto'}
instructions[816] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'op': 'literal'}
instructions[817] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'op': 'store'}
instructions[818] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'op': 'addl'}
instructions[819] = {5'd0, 4'd8, 4'd0, 16'd29};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'literal': 29, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'op': 'literal'}
instructions[820] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'op': 'addl'}
instructions[821] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'op': 'load'}
instructions[822] = {5'd21, 4'd8, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'a': 8, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'op': 'ready'}
instructions[823] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[824] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'op': 'load'}
instructions[825] = {5'd6, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'op': 'equal'}
instructions[826] = {5'd14, 4'd0, 4'd8, 16'd831};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'a': 8, 'label': 831, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'op': 'jmp_if_false'}
instructions[827] = {5'd1, 4'd3, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'a': 4, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'op': 'addl'}
instructions[828] = {5'd1, 4'd4, 4'd7, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'a': 7, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'op': 'addl'}
instructions[829] = {5'd19, 4'd0, 4'd6, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'a': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'op': 'return'}
instructions[830] = {5'd8, 4'd0, 4'd0, 16'd831};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28 {'label': 831, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 28, 'op': 'goto'}
instructions[831] = {5'd8, 4'd0, 4'd0, 16'd798};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 22 {'label': 798, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 22, 'op': 'goto'}
instructions[832] = {5'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 84 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 84, 'op': 'addl'}
instructions[833] = {5'd0, 4'd8, 4'd0, 16'd29};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85 {'literal': 29, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85, 'op': 'literal'}
instructions[834] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85, 'op': 'addl'}
instructions[835] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85, 'op': 'load'}
instructions[836] = {5'd9, 4'd8, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85 {'a': 8, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85, 'op': 'read'}
instructions[837] = {5'd0, 4'd2, 4'd0, 16'd12};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85 {'literal': 12, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85, 'op': 'literal'}
instructions[838] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85, 'op': 'store'}
instructions[839] = {5'd1, 4'd3, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85 {'a': 4, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85, 'op': 'addl'}
instructions[840] = {5'd1, 4'd4, 4'd7, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85 {'a': 7, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85, 'op': 'addl'}
instructions[841] = {5'd19, 4'd0, 4'd6, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85 {'a': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 85, 'op': 'return'}
instructions[842] = {5'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73, 'op': 'addl'}
instructions[843] = {5'd2, 4'd0, 4'd3, 16'd6};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'store'}
instructions[844] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[845] = {5'd2, 4'd0, 4'd3, 16'd7};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'store'}
instructions[846] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[847] = {5'd1, 4'd8, 4'd4, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 4, 'literal': -1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[848] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[849] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'load'}
instructions[850] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'store'}
instructions[851] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[852] = {5'd0, 4'd8, 4'd0, 16'd11};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'literal': 11, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'literal'}
instructions[853] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[854] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'load'}
instructions[855] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'store'}
instructions[856] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[857] = {5'd1, 4'd7, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 4, 'literal': 0, 'z': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[858] = {5'd1, 4'd4, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[859] = {5'd3, 4'd6, 4'd0, 16'd869};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'z': 6, 'label': 869, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'call'}
instructions[860] = {5'd1, 4'd3, 4'd3, -16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': -2, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[861] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[862] = {5'd5, 4'd7, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'z': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'load'}
instructions[863] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[864] = {5'd5, 4'd6, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'z': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'load'}
instructions[865] = {5'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 74, 'op': 'addl'}
instructions[866] = {5'd1, 4'd3, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73 {'a': 4, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73, 'op': 'addl'}
instructions[867] = {5'd1, 4'd4, 4'd7, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73 {'a': 7, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73, 'op': 'addl'}
instructions[868] = {5'd19, 4'd0, 4'd6, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73 {'a': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 73, 'op': 'return'}
instructions[869] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23, 'op': 'addl'}
instructions[870] = {5'd0, 4'd8, 4'd0, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24 {'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24, 'op': 'literal'}
instructions[871] = {5'd1, 4'd2, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24 {'a': 4, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24, 'op': 'addl'}
instructions[872] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 24, 'op': 'store'}
instructions[873] = {5'd1, 4'd8, 4'd4, -16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 4, 'literal': -2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[874] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[875] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'load'}
instructions[876] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'store'}
instructions[877] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[878] = {5'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[879] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[880] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'load'}
instructions[881] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[882] = {5'd5, 4'd2, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 3, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'load'}
instructions[883] = {5'd18, 4'd8, 4'd8, 16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 8, 'z': 8, 'b': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'add'}
instructions[884] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'addl'}
instructions[885] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'load'}
instructions[886] = {5'd14, 4'd0, 4'd8, 16'd928};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29 {'a': 8, 'label': 928, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29, 'op': 'jmp_if_false'}
instructions[887] = {5'd1, 4'd8, 4'd4, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 4, 'literal': -1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[888] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[889] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[890] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'store'}
instructions[891] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[892] = {5'd1, 4'd8, 4'd4, -16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 4, 'literal': -2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[893] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[894] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[895] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'store'}
instructions[896] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[897] = {5'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[898] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[899] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[900] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[901] = {5'd5, 4'd2, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[902] = {5'd18, 4'd8, 4'd8, 16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'z': 8, 'b': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'add'}
instructions[903] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[904] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[905] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[906] = {5'd5, 4'd0, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'z': 0, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'load'}
instructions[907] = {5'd10, 4'd0, 4'd0, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 0, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'write'}
instructions[908] = {5'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 26, 'op': 'addl'}
instructions[909] = {5'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[910] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[911] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'load'}
instructions[912] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'store'}
instructions[913] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[914] = {5'd0, 4'd8, 4'd0, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'literal': 1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'literal'}
instructions[915] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'store'}
instructions[916] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[917] = {5'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[918] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[919] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'load'}
instructions[920] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[921] = {5'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'load'}
instructions[922] = {5'd18, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'add'}
instructions[923] = {5'd1, 4'd2, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 4, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'addl'}
instructions[924] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'store'}
instructions[925] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[926] = {5'd5, 4'd8, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27 {'a': 3, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 27, 'op': 'load'}
instructions[927] = {5'd8, 4'd0, 4'd0, 16'd929};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29 {'label': 929, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29, 'op': 'goto'}
instructions[928] = {5'd8, 4'd0, 4'd0, 16'd930};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29 {'label': 930, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 29, 'op': 'goto'}
instructions[929] = {5'd8, 4'd0, 4'd0, 16'd873};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25 {'label': 873, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 25, 'op': 'goto'}
instructions[930] = {5'd1, 4'd3, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23 {'a': 4, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23, 'op': 'addl'}
instructions[931] = {5'd1, 4'd4, 4'd7, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23 {'a': 7, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23, 'op': 'addl'}
instructions[932] = {5'd19, 4'd0, 4'd6, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23 {'a': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/stdio.h : 23, 'op': 'return'}
instructions[933] = {5'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 128 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 128, 'op': 'addl'}
instructions[934] = {5'd2, 4'd0, 4'd3, 16'd6};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'store'}
instructions[935] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'addl'}
instructions[936] = {5'd2, 4'd0, 4'd3, 16'd7};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'store'}
instructions[937] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'addl'}
instructions[938] = {5'd1, 4'd8, 4'd4, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 4, 'literal': -1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'addl'}
instructions[939] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'addl'}
instructions[940] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'load'}
instructions[941] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'store'}
instructions[942] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'addl'}
instructions[943] = {5'd0, 4'd8, 4'd0, 16'd11};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'literal': 11, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'literal'}
instructions[944] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'addl'}
instructions[945] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'load'}
instructions[946] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'store'}
instructions[947] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'addl'}
instructions[948] = {5'd1, 4'd7, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 4, 'literal': 0, 'z': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'addl'}
instructions[949] = {5'd1, 4'd4, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 3, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'addl'}
instructions[950] = {5'd3, 4'd6, 4'd0, 16'd960};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'z': 6, 'label': 960, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'call'}
instructions[951] = {5'd1, 4'd3, 4'd3, -16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 3, 'literal': -2, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'addl'}
instructions[952] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[953] = {5'd5, 4'd7, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 3, 'z': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'load'}
instructions[954] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[955] = {5'd5, 4'd6, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 3, 'z': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'load'}
instructions[956] = {5'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 129, 'op': 'addl'}
instructions[957] = {5'd1, 4'd3, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 128 {'a': 4, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 128, 'op': 'addl'}
instructions[958] = {5'd1, 4'd4, 4'd7, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 128 {'a': 7, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 128, 'op': 'addl'}
instructions[959] = {5'd19, 4'd0, 4'd6, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 128 {'a': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 128, 'op': 'return'}
instructions[960] = {5'd1, 4'd3, 4'd3, 16'd12};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 16 {'a': 3, 'literal': 12, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 16, 'op': 'addl'}
instructions[961] = {5'd0, 4'd8, 4'd0, 16'd51712};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 21 {'literal': 51712, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 21, 'op': 'literal'}
instructions[962] = {5'd17, 4'd8, 4'd8, 16'd15258};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 21 {'a': 8, 'literal': 15258, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 21, 'op': 'literal_hi'}
instructions[963] = {5'd1, 4'd2, 4'd4, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 21 {'a': 4, 'literal': 10, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 21, 'op': 'addl'}
instructions[964] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 21 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 21, 'op': 'store'}
instructions[965] = {5'd0, 4'd8, 4'd0, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 22 {'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 22, 'op': 'literal'}
instructions[966] = {5'd1, 4'd2, 4'd4, 16'd11};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 22 {'a': 4, 'literal': 11, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 22, 'op': 'addl'}
instructions[967] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 22 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 22, 'op': 'store'}
instructions[968] = {5'd1, 4'd8, 4'd4, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 23 {'a': 4, 'literal': 10, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 23, 'op': 'addl'}
instructions[969] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 23 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 23, 'op': 'addl'}
instructions[970] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 23 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 23, 'op': 'load'}
instructions[971] = {5'd14, 4'd0, 4'd8, 16'd1066};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 8, 'label': 1066, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'jmp_if_false'}
instructions[972] = {5'd0, 4'd8, 4'd0, 16'd48};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'literal': 48, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'literal'}
instructions[973] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'store'}
instructions[974] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'addl'}
instructions[975] = {5'd0, 4'd8, 4'd0, 16'd15};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'literal': 15, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'literal'}
instructions[976] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'store'}
instructions[977] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'addl'}
instructions[978] = {5'd1, 4'd8, 4'd4, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 4, 'literal': 10, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'addl'}
instructions[979] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'addl'}
instructions[980] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'load'}
instructions[981] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'store'}
instructions[982] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'addl'}
instructions[983] = {5'd1, 4'd8, 4'd4, -16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 4, 'literal': -2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'addl'}
instructions[984] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'addl'}
instructions[985] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'load'}
instructions[986] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[987] = {5'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'load'}
instructions[988] = {5'd22, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'unsigned_divide'}
instructions[989] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[990] = {5'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'load'}
instructions[991] = {5'd23, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'and'}
instructions[992] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[993] = {5'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'load'}
instructions[994] = {5'd16, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'or'}
instructions[995] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'store'}
instructions[996] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'addl'}
instructions[997] = {5'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'addl'}
instructions[998] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'store'}
instructions[999] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'addl'}
instructions[1000] = {5'd1, 4'd8, 4'd4, 16'd11};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 4, 'literal': 11, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'addl'}
instructions[1001] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'addl'}
instructions[1002] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'load'}
instructions[1003] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1004] = {5'd5, 4'd2, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'load'}
instructions[1005] = {5'd18, 4'd8, 4'd8, 16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 8, 'z': 8, 'b': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'add'}
instructions[1006] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'addl'}
instructions[1007] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1008] = {5'd5, 4'd8, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 3, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'load'}
instructions[1009] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 24, 'op': 'store'}
instructions[1010] = {5'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25, 'op': 'addl'}
instructions[1011] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25, 'op': 'store'}
instructions[1012] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25, 'op': 'addl'}
instructions[1013] = {5'd1, 4'd8, 4'd4, 16'd11};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25 {'a': 4, 'literal': 11, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25, 'op': 'addl'}
instructions[1014] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25, 'op': 'addl'}
instructions[1015] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25, 'op': 'load'}
instructions[1016] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1017] = {5'd5, 4'd2, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25 {'a': 3, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25, 'op': 'load'}
instructions[1018] = {5'd18, 4'd8, 4'd8, 16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25 {'a': 8, 'z': 8, 'b': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25, 'op': 'add'}
instructions[1019] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25, 'op': 'addl'}
instructions[1020] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25, 'op': 'load'}
instructions[1021] = {5'd24, 4'd8, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25 {'a': 8, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25, 'op': 'a_lo'}
instructions[1022] = {5'd25, 4'd0, 4'd0, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25 {'line': 26, 'file': '/usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 25, 'op': 'report'}
instructions[1023] = {5'd1, 4'd8, 4'd4, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26 {'a': 4, 'literal': 10, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26, 'op': 'addl'}
instructions[1024] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26, 'op': 'addl'}
instructions[1025] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26, 'op': 'load'}
instructions[1026] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26, 'op': 'store'}
instructions[1027] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26, 'op': 'addl'}
instructions[1028] = {5'd1, 4'd8, 4'd4, -16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26 {'a': 4, 'literal': -2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26, 'op': 'addl'}
instructions[1029] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26, 'op': 'addl'}
instructions[1030] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26, 'op': 'load'}
instructions[1031] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1032] = {5'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26, 'op': 'load'}
instructions[1033] = {5'd26, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26, 'op': 'unsigned_modulo'}
instructions[1034] = {5'd1, 4'd2, 4'd4, -16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26 {'a': 4, 'literal': -2, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26, 'op': 'addl'}
instructions[1035] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 26, 'op': 'store'}
instructions[1036] = {5'd0, 4'd8, 4'd0, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27 {'literal': 10, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27, 'op': 'literal'}
instructions[1037] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27, 'op': 'store'}
instructions[1038] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27, 'op': 'addl'}
instructions[1039] = {5'd1, 4'd8, 4'd4, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27 {'a': 4, 'literal': 10, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27, 'op': 'addl'}
instructions[1040] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27, 'op': 'addl'}
instructions[1041] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27, 'op': 'load'}
instructions[1042] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1043] = {5'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27, 'op': 'load'}
instructions[1044] = {5'd22, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27, 'op': 'unsigned_divide'}
instructions[1045] = {5'd1, 4'd2, 4'd4, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27 {'a': 4, 'literal': 10, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27, 'op': 'addl'}
instructions[1046] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 27, 'op': 'store'}
instructions[1047] = {5'd1, 4'd8, 4'd4, 16'd11};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'a': 4, 'literal': 11, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'op': 'addl'}
instructions[1048] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'op': 'addl'}
instructions[1049] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'op': 'load'}
instructions[1050] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'op': 'store'}
instructions[1051] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'op': 'addl'}
instructions[1052] = {5'd0, 4'd8, 4'd0, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'literal': 1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'op': 'literal'}
instructions[1053] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'op': 'store'}
instructions[1054] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'op': 'addl'}
instructions[1055] = {5'd1, 4'd8, 4'd4, 16'd11};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'a': 4, 'literal': 11, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'op': 'addl'}
instructions[1056] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'op': 'addl'}
instructions[1057] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'op': 'load'}
instructions[1058] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1059] = {5'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'op': 'load'}
instructions[1060] = {5'd18, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'op': 'add'}
instructions[1061] = {5'd1, 4'd2, 4'd4, 16'd11};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'a': 4, 'literal': 11, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'op': 'addl'}
instructions[1062] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'op': 'store'}
instructions[1063] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1064] = {5'd5, 4'd8, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28 {'a': 3, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 28, 'op': 'load'}
instructions[1065] = {5'd8, 4'd0, 4'd0, 16'd1067};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'label': 1067, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'goto'}
instructions[1066] = {5'd8, 4'd0, 4'd0, 16'd1068};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'label': 1068, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'goto'}
instructions[1067] = {5'd8, 4'd0, 4'd0, 16'd968};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 23 {'label': 968, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 23, 'op': 'goto'}
instructions[1068] = {5'd0, 4'd8, 4'd0, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'literal'}
instructions[1069] = {5'd1, 4'd2, 4'd4, 16'd11};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 4, 'literal': 11, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1070] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'store'}
instructions[1071] = {5'd1, 4'd8, 4'd4, 16'd11};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 4, 'literal': 11, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1072] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1073] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'load'}
instructions[1074] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'store'}
instructions[1075] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1076] = {5'd0, 4'd8, 4'd0, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'literal': 10, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'literal'}
instructions[1077] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1078] = {5'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'load'}
instructions[1079] = {5'd13, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'unsigned_greater'}
instructions[1080] = {5'd14, 4'd0, 4'd8, 16'd1120};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 8, 'label': 1120, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'jmp_if_false'}
instructions[1081] = {5'd1, 4'd8, 4'd4, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 4, 'literal': -1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1082] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1083] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'load'}
instructions[1084] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'store'}
instructions[1085] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1086] = {5'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1087] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'store'}
instructions[1088] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1089] = {5'd1, 4'd8, 4'd4, 16'd11};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 4, 'literal': 11, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1090] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1091] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'load'}
instructions[1092] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1093] = {5'd5, 4'd2, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'load'}
instructions[1094] = {5'd18, 4'd8, 4'd8, 16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 8, 'z': 8, 'b': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'add'}
instructions[1095] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1096] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'load'}
instructions[1097] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1098] = {5'd5, 4'd0, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'z': 0, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'load'}
instructions[1099] = {5'd10, 4'd0, 4'd0, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 0, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'write'}
instructions[1100] = {5'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1101] = {5'd1, 4'd8, 4'd4, 16'd11};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 4, 'literal': 11, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1102] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1103] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'load'}
instructions[1104] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'store'}
instructions[1105] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1106] = {5'd0, 4'd8, 4'd0, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'literal': 1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'literal'}
instructions[1107] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'store'}
instructions[1108] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1109] = {5'd1, 4'd8, 4'd4, 16'd11};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 4, 'literal': 11, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1110] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1111] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'load'}
instructions[1112] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1113] = {5'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'load'}
instructions[1114] = {5'd18, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'add'}
instructions[1115] = {5'd1, 4'd2, 4'd4, 16'd11};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 4, 'literal': 11, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'addl'}
instructions[1116] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'store'}
instructions[1117] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1118] = {5'd5, 4'd8, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'a': 3, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'load'}
instructions[1119] = {5'd8, 4'd0, 4'd0, 16'd1071};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30 {'label': 1071, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 30, 'op': 'goto'}
instructions[1120] = {5'd1, 4'd3, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 16 {'a': 4, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 16, 'op': 'addl'}
instructions[1121] = {5'd1, 4'd4, 4'd7, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 16 {'a': 7, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 16, 'op': 'addl'}
instructions[1122] = {5'd19, 4'd0, 4'd6, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 16 {'a': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h : 16, 'op': 'return'}
instructions[1123] = {5'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 155 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 155, 'op': 'addl'}
instructions[1124] = {5'd2, 4'd0, 4'd3, 16'd6};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'store'}
instructions[1125] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'addl'}
instructions[1126] = {5'd2, 4'd0, 4'd3, 16'd7};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'store'}
instructions[1127] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'addl'}
instructions[1128] = {5'd0, 4'd8, 4'd0, 16'd29};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'literal': 29, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'literal'}
instructions[1129] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'addl'}
instructions[1130] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'load'}
instructions[1131] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'store'}
instructions[1132] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'addl'}
instructions[1133] = {5'd1, 4'd7, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 4, 'literal': 0, 'z': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'addl'}
instructions[1134] = {5'd1, 4'd4, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 3, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'addl'}
instructions[1135] = {5'd3, 4'd6, 4'd0, 16'd1148};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'z': 6, 'label': 1148, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'call'}
instructions[1136] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 3, 'literal': -1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'addl'}
instructions[1137] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1138] = {5'd5, 4'd7, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 3, 'z': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'load'}
instructions[1139] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1140] = {5'd5, 4'd6, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 3, 'z': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'load'}
instructions[1141] = {5'd0, 4'd2, 4'd0, 16'd3};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'literal': 3, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'literal'}
instructions[1142] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'load'}
instructions[1143] = {5'd0, 4'd2, 4'd0, 16'd34};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'literal': 34, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'literal'}
instructions[1144] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'store'}
instructions[1145] = {5'd1, 4'd3, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 4, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'addl'}
instructions[1146] = {5'd1, 4'd4, 4'd7, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 7, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'addl'}
instructions[1147] = {5'd19, 4'd0, 4'd6, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156 {'a': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 156, 'op': 'return'}
instructions[1148] = {5'd1, 4'd3, 4'd3, 16'd2};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 26 {'a': 3, 'literal': 2, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 26, 'op': 'addl'}
instructions[1149] = {5'd0, 4'd8, 4'd0, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 29 {'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 29, 'op': 'literal'}
instructions[1150] = {5'd1, 4'd2, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 29 {'a': 4, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 29, 'op': 'addl'}
instructions[1151] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 29 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 29, 'op': 'store'}
instructions[1152] = {5'd1, 4'd8, 4'd4, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 31 {'a': 4, 'literal': -1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 31, 'op': 'addl'}
instructions[1153] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 31 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 31, 'op': 'addl'}
instructions[1154] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 31 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 31, 'op': 'load'}
instructions[1155] = {5'd9, 4'd8, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 31 {'a': 8, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 31, 'op': 'read'}
instructions[1156] = {5'd1, 4'd2, 4'd4, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 31 {'a': 4, 'literal': 1, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 31, 'op': 'addl'}
instructions[1157] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 31 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 31, 'op': 'store'}
instructions[1158] = {5'd0, 4'd8, 4'd0, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'literal'}
instructions[1159] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'store'}
instructions[1160] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'addl'}
instructions[1161] = {5'd2, 4'd0, 4'd3, 16'd6};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'store'}
instructions[1162] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'addl'}
instructions[1163] = {5'd2, 4'd0, 4'd3, 16'd7};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'store'}
instructions[1164] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'addl'}
instructions[1165] = {5'd1, 4'd8, 4'd4, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 4, 'literal': 1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'addl'}
instructions[1166] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'addl'}
instructions[1167] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'load'}
instructions[1168] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'store'}
instructions[1169] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'addl'}
instructions[1170] = {5'd1, 4'd7, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 4, 'literal': 0, 'z': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'addl'}
instructions[1171] = {5'd1, 4'd4, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 3, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'addl'}
instructions[1172] = {5'd3, 4'd6, 4'd0, 16'd1225};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'z': 6, 'label': 1225, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'call'}
instructions[1173] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 3, 'literal': -1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'addl'}
instructions[1174] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1175] = {5'd5, 4'd7, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 3, 'z': 7, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'load'}
instructions[1176] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1177] = {5'd5, 4'd6, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 3, 'z': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'load'}
instructions[1178] = {5'd0, 4'd2, 4'd0, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'literal': 8, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'literal'}
instructions[1179] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'load'}
instructions[1180] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1181] = {5'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'load'}
instructions[1182] = {5'd6, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'equal'}
instructions[1183] = {5'd14, 4'd0, 4'd8, 16'd1186};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'a': 8, 'label': 1186, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'jmp_if_false'}
instructions[1184] = {5'd8, 4'd0, 4'd0, 16'd1217};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'label': 1217, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'goto'}
instructions[1185] = {5'd8, 4'd0, 4'd0, 16'd1186};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32 {'label': 1186, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 32, 'op': 'goto'}
instructions[1186] = {5'd0, 4'd8, 4'd0, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33 {'literal': 10, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33, 'op': 'literal'}
instructions[1187] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33, 'op': 'store'}
instructions[1188] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33, 'op': 'addl'}
instructions[1189] = {5'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33, 'op': 'addl'}
instructions[1190] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33, 'op': 'addl'}
instructions[1191] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33, 'op': 'load'}
instructions[1192] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1193] = {5'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33, 'op': 'load'}
instructions[1194] = {5'd27, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33, 'op': 'multiply'}
instructions[1195] = {5'd1, 4'd2, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33 {'a': 4, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33, 'op': 'addl'}
instructions[1196] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 33, 'op': 'store'}
instructions[1197] = {5'd0, 4'd8, 4'd0, 16'd48};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'literal': 48, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'op': 'literal'}
instructions[1198] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'op': 'store'}
instructions[1199] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'op': 'addl'}
instructions[1200] = {5'd1, 4'd8, 4'd4, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 4, 'literal': 1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'op': 'addl'}
instructions[1201] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'op': 'addl'}
instructions[1202] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'op': 'load'}
instructions[1203] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1204] = {5'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'op': 'load'}
instructions[1205] = {5'd12, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'op': 'subtract'}
instructions[1206] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'op': 'store'}
instructions[1207] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'op': 'addl'}
instructions[1208] = {5'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'op': 'addl'}
instructions[1209] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'op': 'addl'}
instructions[1210] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'op': 'load'}
instructions[1211] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1212] = {5'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'op': 'load'}
instructions[1213] = {5'd18, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'op': 'add'}
instructions[1214] = {5'd1, 4'd2, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 4, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'op': 'addl'}
instructions[1215] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 34, 'op': 'store'}
instructions[1216] = {5'd8, 4'd0, 4'd0, 16'd1152};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 30 {'label': 1152, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 30, 'op': 'goto'}
instructions[1217] = {5'd1, 4'd8, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 36 {'a': 4, 'literal': 0, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 36, 'op': 'addl'}
instructions[1218] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 36 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 36, 'op': 'addl'}
instructions[1219] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 36 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 36, 'op': 'load'}
instructions[1220] = {5'd0, 4'd2, 4'd0, 16'd3};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 36 {'literal': 3, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 36, 'op': 'literal'}
instructions[1221] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 36 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 36, 'op': 'store'}
instructions[1222] = {5'd1, 4'd3, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 36 {'a': 4, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 36, 'op': 'addl'}
instructions[1223] = {5'd1, 4'd4, 4'd7, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 36 {'a': 7, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 36, 'op': 'addl'}
instructions[1224] = {5'd19, 4'd0, 4'd6, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 36 {'a': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/scan.h : 36, 'op': 'return'}
instructions[1225] = {5'd1, 4'd3, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 86 {'a': 3, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 86, 'op': 'addl'}
instructions[1226] = {5'd0, 4'd8, 4'd0, 16'd48};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'literal': 48, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'literal'}
instructions[1227] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'store'}
instructions[1228] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'addl'}
instructions[1229] = {5'd1, 4'd8, 4'd4, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 4, 'literal': -1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'addl'}
instructions[1230] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'addl'}
instructions[1231] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'load'}
instructions[1232] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1233] = {5'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'load'}
instructions[1234] = {5'd28, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'greater_equal'}
instructions[1235] = {5'd14, 4'd0, 4'd8, 16'd1245};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 8, 'label': 1245, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'jmp_if_false'}
instructions[1236] = {5'd1, 4'd8, 4'd4, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 4, 'literal': -1, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'addl'}
instructions[1237] = {5'd1, 4'd2, 4'd8, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 8, 'literal': 0, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'addl'}
instructions[1238] = {5'd5, 4'd8, 4'd2, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 2, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'load'}
instructions[1239] = {5'd2, 4'd0, 4'd3, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'store'}
instructions[1240] = {5'd1, 4'd3, 4'd3, 16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 3, 'literal': 1, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'addl'}
instructions[1241] = {5'd0, 4'd8, 4'd0, 16'd57};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'literal': 57, 'z': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'literal'}
instructions[1242] = {5'd1, 4'd3, 4'd3, -16'd1};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 3, 'comment': 'pop', 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1243] = {5'd5, 4'd10, 4'd3, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 3, 'z': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'load'}
instructions[1244] = {5'd28, 4'd8, 4'd8, 16'd10};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 8, 'z': 8, 'b': 10, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'greater_equal'}
instructions[1245] = {5'd0, 4'd2, 4'd0, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'literal': 8, 'z': 2, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'literal'}
instructions[1246] = {5'd2, 4'd0, 4'd2, 16'd8};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 2, 'b': 8, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'store'}
instructions[1247] = {5'd1, 4'd3, 4'd4, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 4, 'literal': 0, 'z': 3, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'addl'}
instructions[1248] = {5'd1, 4'd4, 4'd7, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 7, 'literal': 0, 'z': 4, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'addl'}
instructions[1249] = {5'd19, 4'd0, 4'd6, 16'd0};///usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87 {'a': 6, 'trace': /usr/local/lib/python2.7/dist-packages/chips/compiler/include/ctype.h : 87, 'op': 'return'}
instructions[1250] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 40 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 40, 'op': 'addl'}
instructions[1251] = {5'd1, 4'd8, 4'd4, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43 {'a': 4, 'literal': -1, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43, 'op': 'addl'}
instructions[1252] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43, 'op': 'addl'}
instructions[1253] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43, 'op': 'load'}
instructions[1254] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43, 'op': 'store'}
instructions[1255] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43, 'op': 'addl'}
instructions[1256] = {5'd1, 4'd8, 4'd4, -16'd3};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43 {'a': 4, 'literal': -3, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43, 'op': 'addl'}
instructions[1257] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43, 'op': 'addl'}
instructions[1258] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43, 'op': 'load'}
instructions[1259] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1260] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43, 'op': 'load'}
instructions[1261] = {5'd27, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43, 'op': 'multiply'}
instructions[1262] = {5'd1, 4'd2, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43 {'a': 4, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43, 'op': 'addl'}
instructions[1263] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 43, 'op': 'store'}
instructions[1264] = {5'd0, 4'd8, 4'd0, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44 {'literal': 8, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44, 'op': 'literal'}
instructions[1265] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44, 'op': 'store'}
instructions[1266] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44, 'op': 'addl'}
instructions[1267] = {5'd1, 4'd8, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44 {'a': 4, 'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44, 'op': 'addl'}
instructions[1268] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44, 'op': 'addl'}
instructions[1269] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44, 'op': 'load'}
instructions[1270] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1271] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44, 'op': 'load'}
instructions[1272] = {5'd29, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44, 'op': 'shift_right'}
instructions[1273] = {5'd1, 4'd2, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44 {'a': 4, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44, 'op': 'addl'}
instructions[1274] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 44, 'op': 'store'}
instructions[1275] = {5'd1, 4'd8, 4'd4, -16'd2};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45 {'a': 4, 'literal': -2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45, 'op': 'addl'}
instructions[1276] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45, 'op': 'addl'}
instructions[1277] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45, 'op': 'load'}
instructions[1278] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45, 'op': 'store'}
instructions[1279] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45, 'op': 'addl'}
instructions[1280] = {5'd1, 4'd8, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45 {'a': 4, 'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45, 'op': 'addl'}
instructions[1281] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45, 'op': 'addl'}
instructions[1282] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45, 'op': 'load'}
instructions[1283] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1284] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45, 'op': 'load'}
instructions[1285] = {5'd18, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45, 'op': 'add'}
instructions[1286] = {5'd1, 4'd2, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45 {'a': 4, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45, 'op': 'addl'}
instructions[1287] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 45, 'op': 'store'}
instructions[1288] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'store'}
instructions[1289] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'addl'}
instructions[1290] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'store'}
instructions[1291] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'addl'}
instructions[1292] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'literal'}
instructions[1293] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'store'}
instructions[1294] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'addl'}
instructions[1295] = {5'd1, 4'd8, 4'd4, -16'd3};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 4, 'literal': -3, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'addl'}
instructions[1296] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'addl'}
instructions[1297] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'load'}
instructions[1298] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1299] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'load'}
instructions[1300] = {5'd30, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'greater'}
instructions[1301] = {5'd14, 4'd0, 4'd8, 16'd1306};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 8, 'label': 1306, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'jmp_if_false'}
instructions[1302] = {5'd1, 4'd8, 4'd4, -16'd3};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 4, 'literal': -3, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'addl'}
instructions[1303] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'addl'}
instructions[1304] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'load'}
instructions[1305] = {5'd8, 4'd0, 4'd8, 16'd1321};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 8, 'label': 1321, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'goto'}
instructions[1306] = {5'd0, 4'd8, 4'd0, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'literal': 8, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'literal'}
instructions[1307] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'store'}
instructions[1308] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'addl'}
instructions[1309] = {5'd1, 4'd8, 4'd4, -16'd3};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 4, 'literal': -3, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'addl'}
instructions[1310] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'addl'}
instructions[1311] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'load'}
instructions[1312] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'store'}
instructions[1313] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'addl'}
instructions[1314] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'literal'}
instructions[1315] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1316] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'load'}
instructions[1317] = {5'd12, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'subtract'}
instructions[1318] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1319] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'load'}
instructions[1320] = {5'd29, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'shift_right'}
instructions[1321] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'store'}
instructions[1322] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'addl'}
instructions[1323] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'addl'}
instructions[1324] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'addl'}
instructions[1325] = {5'd3, 4'd6, 4'd0, 16'd1347};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'z': 6, 'label': 1347, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'call'}
instructions[1326] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'addl'}
instructions[1327] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1328] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'load'}
instructions[1329] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1330] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'load'}
instructions[1331] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 46, 'op': 'addl'}
instructions[1332] = {5'd0, 4'd8, 4'd0, 16'd33};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47 {'literal': 33, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47, 'op': 'literal'}
instructions[1333] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47, 'op': 'addl'}
instructions[1334] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47, 'op': 'load'}
instructions[1335] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47, 'op': 'store'}
instructions[1336] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47, 'op': 'addl'}
instructions[1337] = {5'd1, 4'd8, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47 {'a': 4, 'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47, 'op': 'addl'}
instructions[1338] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47, 'op': 'addl'}
instructions[1339] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47, 'op': 'load'}
instructions[1340] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1341] = {5'd5, 4'd0, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47 {'a': 3, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47, 'op': 'load'}
instructions[1342] = {5'd10, 4'd0, 4'd0, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47 {'a': 0, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47, 'op': 'write'}
instructions[1343] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 47, 'op': 'addl'}
instructions[1344] = {5'd1, 4'd3, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 40 {'a': 4, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 40, 'op': 'addl'}
instructions[1345] = {5'd1, 4'd4, 4'd7, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 40 {'a': 7, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 40, 'op': 'addl'}
instructions[1346] = {5'd19, 4'd0, 4'd6, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 40 {'a': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 40, 'op': 'return'}
instructions[1347] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 14 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 14, 'op': 'addl'}
instructions[1348] = {5'd0, 4'd8, 4'd0, 16'd5};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15 {'literal': 5, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15, 'op': 'literal'}
instructions[1349] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15, 'op': 'store'}
instructions[1350] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15, 'op': 'addl'}
instructions[1351] = {5'd1, 4'd8, 4'd4, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15 {'a': 4, 'literal': -1, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15, 'op': 'addl'}
instructions[1352] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15, 'op': 'addl'}
instructions[1353] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15, 'op': 'load'}
instructions[1354] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1355] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15, 'op': 'load'}
instructions[1356] = {5'd31, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15, 'op': 'unsigned_shift_right'}
instructions[1357] = {5'd1, 4'd2, 4'd4, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15 {'a': 4, 'literal': -1, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15, 'op': 'addl'}
instructions[1358] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 15, 'op': 'store'}
instructions[1359] = {5'd1, 4'd8, 4'd4, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16 {'a': 4, 'literal': -1, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16, 'op': 'addl'}
instructions[1360] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16, 'op': 'addl'}
instructions[1361] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16, 'op': 'load'}
instructions[1362] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16, 'op': 'store'}
instructions[1363] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16, 'op': 'addl'}
instructions[1364] = {5'd0, 4'd8, 4'd0, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16 {'literal': 8, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16, 'op': 'literal'}
instructions[1365] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1366] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16, 'op': 'load'}
instructions[1367] = {5'd12, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16, 'op': 'subtract'}
instructions[1368] = {5'd1, 4'd2, 4'd4, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16 {'a': 4, 'literal': -1, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16, 'op': 'addl'}
instructions[1369] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 16, 'op': 'store'}
instructions[1370] = {5'd1, 4'd8, 4'd4, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17 {'a': 4, 'literal': -1, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17, 'op': 'addl'}
instructions[1371] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17, 'op': 'addl'}
instructions[1372] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17, 'op': 'load'}
instructions[1373] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17, 'op': 'store'}
instructions[1374] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17, 'op': 'addl'}
instructions[1375] = {5'd0, 4'd8, 4'd0, 16'd255};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17 {'literal': 255, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17, 'op': 'literal'}
instructions[1376] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1377] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17, 'op': 'load'}
instructions[1378] = {5'd31, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17, 'op': 'unsigned_shift_right'}
instructions[1379] = {5'd1, 4'd2, 4'd4, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17 {'a': 4, 'literal': -1, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17, 'op': 'addl'}
instructions[1380] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 17, 'op': 'store'}
instructions[1381] = {5'd0, 4'd8, 4'd0, 16'd19};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18 {'literal': 19, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18, 'op': 'literal'}
instructions[1382] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18, 'op': 'addl'}
instructions[1383] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18, 'op': 'load'}
instructions[1384] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18, 'op': 'store'}
instructions[1385] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18, 'op': 'addl'}
instructions[1386] = {5'd1, 4'd8, 4'd4, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18 {'a': 4, 'literal': -1, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18, 'op': 'addl'}
instructions[1387] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18, 'op': 'addl'}
instructions[1388] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18, 'op': 'load'}
instructions[1389] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1390] = {5'd5, 4'd0, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18 {'a': 3, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18, 'op': 'load'}
instructions[1391] = {5'd10, 4'd0, 4'd0, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18 {'a': 0, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18, 'op': 'write'}
instructions[1392] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 18, 'op': 'addl'}
instructions[1393] = {5'd1, 4'd3, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 14 {'a': 4, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 14, 'op': 'addl'}
instructions[1394] = {5'd1, 4'd4, 4'd7, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 14 {'a': 7, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 14, 'op': 'addl'}
instructions[1395] = {5'd19, 4'd0, 4'd6, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 14 {'a': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 14, 'op': 'return'}
instructions[1396] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 32 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 32, 'op': 'addl'}
instructions[1397] = {5'd0, 4'd8, 4'd0, 16'd16};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34 {'literal': 16, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34, 'op': 'literal'}
instructions[1398] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34, 'op': 'store'}
instructions[1399] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34, 'op': 'addl'}
instructions[1400] = {5'd0, 4'd8, 4'd0, 16'd255};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34 {'literal': 255, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34, 'op': 'literal'}
instructions[1401] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34, 'op': 'store'}
instructions[1402] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34, 'op': 'addl'}
instructions[1403] = {5'd1, 4'd8, 4'd4, -16'd2};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34 {'a': 4, 'literal': -2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34, 'op': 'addl'}
instructions[1404] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34, 'op': 'addl'}
instructions[1405] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34, 'op': 'load'}
instructions[1406] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1407] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34, 'op': 'load'}
instructions[1408] = {5'd23, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34, 'op': 'and'}
instructions[1409] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1410] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34, 'op': 'load'}
instructions[1411] = {5'd15, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34, 'op': 'shift_left'}
instructions[1412] = {5'd1, 4'd2, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34 {'a': 4, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34, 'op': 'addl'}
instructions[1413] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 34, 'op': 'store'}
instructions[1414] = {5'd0, 4'd8, 4'd0, 16'd255};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'literal': 255, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'op': 'literal'}
instructions[1415] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'op': 'store'}
instructions[1416] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'op': 'addl'}
instructions[1417] = {5'd1, 4'd8, 4'd4, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 4, 'literal': -1, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'op': 'addl'}
instructions[1418] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'op': 'addl'}
instructions[1419] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'op': 'load'}
instructions[1420] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1421] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'op': 'load'}
instructions[1422] = {5'd23, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'op': 'and'}
instructions[1423] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'op': 'store'}
instructions[1424] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'op': 'addl'}
instructions[1425] = {5'd1, 4'd8, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 4, 'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'op': 'addl'}
instructions[1426] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'op': 'addl'}
instructions[1427] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'op': 'load'}
instructions[1428] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1429] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'op': 'load'}
instructions[1430] = {5'd16, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'op': 'or'}
instructions[1431] = {5'd1, 4'd2, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 4, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'op': 'addl'}
instructions[1432] = {5'd2, 4'd0, 4'd2, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35 {'a': 2, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 35, 'op': 'store'}
instructions[1433] = {5'd2, 4'd0, 4'd3, 16'd6};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'comment': 'push', 'b': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'store'}
instructions[1434] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'addl'}
instructions[1435] = {5'd2, 4'd0, 4'd3, 16'd7};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'comment': 'push', 'b': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'store'}
instructions[1436] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'addl'}
instructions[1437] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'literal'}
instructions[1438] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'store'}
instructions[1439] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'addl'}
instructions[1440] = {5'd1, 4'd8, 4'd4, -16'd2};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 4, 'literal': -2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'addl'}
instructions[1441] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'addl'}
instructions[1442] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'load'}
instructions[1443] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1444] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'load'}
instructions[1445] = {5'd30, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'greater'}
instructions[1446] = {5'd14, 4'd0, 4'd8, 16'd1451};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 8, 'label': 1451, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'jmp_if_false'}
instructions[1447] = {5'd1, 4'd8, 4'd4, -16'd2};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 4, 'literal': -2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'addl'}
instructions[1448] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'addl'}
instructions[1449] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'load'}
instructions[1450] = {5'd8, 4'd0, 4'd8, 16'd1460};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 8, 'label': 1460, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'goto'}
instructions[1451] = {5'd1, 4'd8, 4'd4, -16'd2};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 4, 'literal': -2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'addl'}
instructions[1452] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'addl'}
instructions[1453] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'load'}
instructions[1454] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'store'}
instructions[1455] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'addl'}
instructions[1456] = {5'd0, 4'd8, 4'd0, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'literal'}
instructions[1457] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1458] = {5'd5, 4'd10, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'z': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'load'}
instructions[1459] = {5'd12, 4'd8, 4'd8, 16'd10};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 8, 'z': 8, 'b': 10, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'subtract'}
instructions[1460] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'store'}
instructions[1461] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'addl'}
instructions[1462] = {5'd1, 4'd7, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 4, 'literal': 0, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'addl'}
instructions[1463] = {5'd1, 4'd4, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'addl'}
instructions[1464] = {5'd3, 4'd6, 4'd0, 16'd1347};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'z': 6, 'label': 1347, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'call'}
instructions[1465] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'literal': -1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'addl'}
instructions[1466] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1467] = {5'd5, 4'd7, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'z': 7, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'load'}
instructions[1468] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1469] = {5'd5, 4'd6, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'z': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'load'}
instructions[1470] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 36, 'op': 'addl'}
instructions[1471] = {5'd0, 4'd8, 4'd0, 16'd2};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37 {'literal': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37, 'op': 'literal'}
instructions[1472] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37, 'op': 'addl'}
instructions[1473] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37, 'op': 'load'}
instructions[1474] = {5'd2, 4'd0, 4'd3, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37 {'a': 3, 'comment': 'push', 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37, 'op': 'store'}
instructions[1475] = {5'd1, 4'd3, 4'd3, 16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37 {'a': 3, 'literal': 1, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37, 'op': 'addl'}
instructions[1476] = {5'd1, 4'd8, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37 {'a': 4, 'literal': 0, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37, 'op': 'addl'}
instructions[1477] = {5'd1, 4'd2, 4'd8, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37 {'a': 8, 'literal': 0, 'z': 2, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37, 'op': 'addl'}
instructions[1478] = {5'd5, 4'd8, 4'd2, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37 {'a': 2, 'z': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37, 'op': 'load'}
instructions[1479] = {5'd1, 4'd3, 4'd3, -16'd1};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37 {'a': 3, 'comment': 'pop', 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37, 'literal': -1, 'z': 3, 'op': 'addl'}
instructions[1480] = {5'd5, 4'd0, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37 {'a': 3, 'z': 0, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37, 'op': 'load'}
instructions[1481] = {5'd10, 4'd0, 4'd0, 16'd8};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37 {'a': 0, 'b': 8, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37, 'op': 'write'}
instructions[1482] = {5'd1, 4'd3, 4'd3, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37 {'a': 3, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 37, 'op': 'addl'}
instructions[1483] = {5'd1, 4'd3, 4'd4, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 32 {'a': 4, 'literal': 0, 'z': 3, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 32, 'op': 'addl'}
instructions[1484] = {5'd1, 4'd4, 4'd7, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 32 {'a': 7, 'literal': 0, 'z': 4, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 32, 'op': 'addl'}
instructions[1485] = {5'd19, 4'd0, 4'd6, 16'd0};///home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 32 {'a': 6, 'trace': /home/storage/Projects/FPGA-TX/fpga_tx/c_code/application.c : 32, 'op': 'return'}
end
always @(posedge clk)
begin
load_data <= memory[load_address];
if(store_enable && state == execute) begin
memory[store_address] <= store_data;
end
end
//////////////////////////////////////////////////////////////////////////////
// PIPELINE STAGE 1 -- FETCH INSTRUCTION
//
always @(posedge clk)
begin
//implement memory for instructions
if (state == instruction_fetch || state == operand_fetch || state == execute) begin
instruction <= instructions[program_counter];
program_counter_1 <= program_counter;
end
end
assign opcode = instruction[28:24];
assign address_z = instruction[23:20];
assign address_a = instruction[19:16];
assign address_b = instruction[3:0];
assign literal = instruction[15:0];
//////////////////////////////////////////////////////////////////////////////
// PIPELINE STAGE 2 -- FETCH OPERANDS
//
always @(posedge clk)
begin
if (write_enable) begin
registers[address_z_3] <= result;
end
if (state == operand_fetch || state == execute) begin
opcode_2 <= opcode;
literal_2 <= literal;
address_a_2 <= address_a;
address_b_2 <= address_b;
address_z_2 <= address_z;
program_counter_2 <= program_counter_1;
end
end
assign register_a = registers[address_a_2];
assign register_b = registers[address_b_2];
assign operand_a = (address_a_2 == address_z_3 && write_enable)?result:register_a;
assign operand_b = (address_b_2 == address_z_3 && write_enable)?result:register_b;
assign store_address = operand_a;
assign load_address = operand_a;
assign store_data = operand_b;
assign store_enable = (opcode_2==2);
//////////////////////////////////////////////////////////////////////////////
// PIPELINE STAGE 3 -- EXECUTE
//
always @(posedge clk)
begin
write_enable <= 0;
timer_clock <= timer_clock + 1;
case(state)
//instruction_fetch
instruction_fetch: begin
program_counter <= program_counter + 1;
state <= operand_fetch;
end
//operand_fetch
operand_fetch: begin
program_counter <= program_counter + 1;
state <= execute;
end
//execute
execute: begin
program_counter <= program_counter + 1;
address_z_3 <= address_z_2;
case(opcode_2)
//literal
16'd0:
begin
result<=$signed(literal_2);
write_enable <= 1;
end
//addl
16'd1:
begin
result<=operand_a + literal_2;
write_enable <= 1;
end
//store
16'd2:
begin
end
//call
16'd3:
begin
result <= program_counter_2 + 1;
write_enable <= 1;
program_counter <= literal_2;
state <= instruction_fetch;
end
//stop
16'd4:
begin
state <= stop;
end
//load
16'd5:
begin
state <= load;
end
//equal
16'd6:
begin
result <= operand_a == operand_b;
write_enable <= 1;
end
//jmp_if_true
16'd7:
begin
if (operand_a != 0) begin
program_counter <= literal_2;
state <= instruction_fetch;
end
end
//goto
16'd8:
begin
program_counter <= literal_2;
state <= instruction_fetch;
end
//read
16'd9:
begin
state <= read;
read_input <= operand_a;
end
//write
16'd10:
begin
state <= write;
write_output <= operand_a;
write_value <= operand_b;
end
//timer_low
16'd11:
begin
result <= timer_clock[31:0];
write_enable <= 1;
end
//subtract
16'd12:
begin
long_result = operand_a + (~operand_b) + 1;
result <= long_result[31:0];
carry[0] <= ~long_result[32];
write_enable <= 1;
end
//unsigned_greater
16'd13:
begin
result <= $unsigned(operand_a) > $unsigned(operand_b);
write_enable <= 1;
end
//jmp_if_false
16'd14:
begin
if (operand_a == 0) begin
program_counter <= literal_2;
state <= instruction_fetch;
end
end
//shift_left
16'd15:
begin
if(operand_b < 32) begin
result <= operand_a << operand_b;
carry <= operand_a >> (32-operand_b);
end else begin
result <= 0;
carry <= operand_a;
end
write_enable <= 1;
end
//or
16'd16:
begin
result <= operand_a | operand_b;
write_enable <= 1;
end
//literal_hi
16'd17:
begin
result<= {literal_2, operand_a[15:0]};
write_enable <= 1;
end
//add
16'd18:
begin
long_result = operand_a + operand_b;
result <= long_result[31:0];
carry[0] <= long_result[32];
write_enable <= 1;
end
//return
16'd19:
begin
program_counter <= operand_a;
state <= instruction_fetch;
end
//wait_clocks
16'd20:
begin
timer <= operand_a;
state <= wait_state;
end
//ready
16'd21:
begin
result <= 0;
case(operand_a)
0:
begin
result[0] <= input_rs232_rx_stb;
end
1:
begin
result[0] <= input_gps_rx_stb;
end
2:
begin
result[0] <= input_gps_count_stb;
end
endcase
write_enable <= 1;
end
//unsigned_divide
16'd22:
begin
dividend <= operand_a;
divisor <= operand_b;
timer <= 32;
remainder <= 0;
quotient <= 0;
state <= unsigned_divide;
end
//and
16'd23:
begin
result <= operand_a & operand_b;
write_enable <= 1;
end
//a_lo
16'd24:
begin
a_lo <= operand_a;
result <= a_lo;
write_enable <= 1;
end
//report
16'd25:
begin
$display ("%d (report (int) at line: 26 in file: /usr/local/lib/python2.7/dist-packages/chips/compiler/include/print.h)", $signed(a_lo));
end
//unsigned_modulo
16'd26:
begin
dividend <= operand_a;
divisor <= operand_b;
timer <= 32;
remainder <= 0;
quotient <= 0;
state <= unsigned_modulo;
end
//multiply
16'd27:
begin
product_a <= operand_a[15:0] * operand_b[15:0];
product_b <= operand_a[15:0] * operand_b[31:16];
product_c <= operand_a[31:16] * operand_b[15:0];
product_d <= operand_a[31:16] * operand_b[31:16];
state <= multiply;
end
//greater_equal
16'd28:
begin
result <= $signed(operand_a) >= $signed(operand_b);
write_enable <= 1;
end
//shift_right
16'd29:
begin
if(operand_b < 32) begin
result <= $signed(operand_a) >>> operand_b;
carry <= operand_a << (32-operand_b);
end else begin
result <= operand_a[31]?-1:0;
carry <= operand_a;
end
write_enable <= 1;
end
//greater
16'd30:
begin
result <= $signed(operand_a) > $signed(operand_b);
write_enable <= 1;
end
//unsigned_shift_right
16'd31:
begin
if(operand_b < 32) begin
result <= operand_a >> operand_b;
carry <= operand_a << (32-operand_b);
end else begin
result <= 0;
carry <= operand_a;
end
write_enable <= 1;
end
endcase
end
multiply:
begin
long_result = product_a +
(product_b << 16) +
(product_c << 16) +
(product_d << 32);
result <= long_result[31:0];
carry <= long_result[63:32];
write_enable <= 1;
state <= execute;
end
unsigned_divide:
begin
if (timer) begin
timer <= timer - 1;
end else begin
result <= quotient;
state <= execute;
write_enable <= 1;
end
end
unsigned_modulo:
begin
if (timer) begin
timer <= timer - 1;
end else begin
result <= remainder;
state <= execute;
write_enable <= 1;
end
end
read:
begin
case(read_input)
0:
begin
s_input_rs232_rx_ack <= 1;
if (s_input_rs232_rx_ack && input_rs232_rx_stb) begin
result <= input_rs232_rx;
write_enable <= 1;
s_input_rs232_rx_ack <= 0;
state <= execute;
end
end
1:
begin
s_input_gps_rx_ack <= 1;
if (s_input_gps_rx_ack && input_gps_rx_stb) begin
result <= input_gps_rx;
write_enable <= 1;
s_input_gps_rx_ack <= 0;
state <= execute;
end
end
2:
begin
s_input_gps_count_ack <= 1;
if (s_input_gps_count_ack && input_gps_count_stb) begin
result <= input_gps_count;
write_enable <= 1;
s_input_gps_count_ack <= 0;
state <= execute;
end
end
endcase
end
write:
begin
case(write_output)
3:
begin
s_output_freq_out_stb <= 1;
s_output_freq_out <= write_value;
if (output_freq_out_ack && s_output_freq_out_stb) begin
s_output_freq_out_stb <= 0;
state <= execute;
end
end
4:
begin
s_output_am_out_stb <= 1;
s_output_am_out <= write_value;
if (output_am_out_ack && s_output_am_out_stb) begin
s_output_am_out_stb <= 0;
state <= execute;
end
end
5:
begin
s_output_ctl_out_stb <= 1;
s_output_ctl_out <= write_value;
if (output_ctl_out_ack && s_output_ctl_out_stb) begin
s_output_ctl_out_stb <= 0;
state <= execute;
end
end
6:
begin
s_output_rs232_tx_stb <= 1;
s_output_rs232_tx <= write_value;
if (output_rs232_tx_ack && s_output_rs232_tx_stb) begin
s_output_rs232_tx_stb <= 0;
state <= execute;
end
end
7:
begin
s_output_gps_tx_stb <= 1;
s_output_gps_tx <= write_value;
if (output_gps_tx_ack && s_output_gps_tx_stb) begin
s_output_gps_tx_stb <= 0;
state <= execute;
end
end
8:
begin
s_output_leds_stb <= 1;
s_output_leds <= write_value;
if (output_leds_ack && s_output_leds_stb) begin
s_output_leds_stb <= 0;
state <= execute;
end
end
endcase
end
load:
begin
result <= load_data;
write_enable <= 1;
state <= execute;
end
wait_state:
begin
if (timer) begin
timer <= timer - 1;
end else begin
state <= execute;
end
end
stop:
begin
end
endcase
//divider kernel logic
repeat (1) begin
shifter = {remainder[30:0], dividend[31]};
difference = shifter - divisor;
dividend = dividend << 1;
if (difference[32]) begin
remainder = shifter;
quotient = quotient << 1;
end else begin
remainder = difference[31:0];
quotient = quotient << 1 | 1;
end
end
if (rst == 1'b1) begin
timer <= 0;
timer_clock <= 0;
program_counter <= 0;
address_z_3 <= 0;
result <= 0;
a = 0;
b = 0;
z = 0;
state <= instruction_fetch;
s_input_rs232_rx_ack <= 0;
s_input_gps_rx_ack <= 0;
s_input_gps_count_ack <= 0;
s_output_freq_out_stb <= 0;
s_output_am_out_stb <= 0;
s_output_ctl_out_stb <= 0;
s_output_rs232_tx_stb <= 0;
s_output_gps_tx_stb <= 0;
s_output_leds_stb <= 0;
end
end
assign input_rs232_rx_ack = s_input_rs232_rx_ack;
assign input_gps_rx_ack = s_input_gps_rx_ack;
assign input_gps_count_ack = s_input_gps_count_ack;
assign output_freq_out_stb = s_output_freq_out_stb;
assign output_freq_out = s_output_freq_out;
assign output_am_out_stb = s_output_am_out_stb;
assign output_am_out = s_output_am_out;
assign output_ctl_out_stb = s_output_ctl_out_stb;
assign output_ctl_out = s_output_ctl_out;
assign output_rs232_tx_stb = s_output_rs232_tx_stb;
assign output_rs232_tx = s_output_rs232_tx;
assign output_gps_tx_stb = s_output_gps_tx_stb;
assign output_gps_tx = s_output_gps_tx;
assign output_leds_stb = s_output_leds_stb;
assign output_leds = s_output_leds;
endmodule
|
module m1(clk, rstn, leds);
parameter width=8;
input clk;
input rstn;
output reg [width-1:0] leds;
always @(posedge clk, negedge rstn) begin
if (~rstn)
leds <= {width{1'b0}};
else
leds <= leds + {{width-1{1'b0}}, 1'b1};
end
endmodule
module m1_de0nano(sys_clk, rstn, rstn_it, leds);
input sys_clk;
input rstn;
input rstn_it;
output [7:0] leds;
wire clk;
wire [1:0] top;
clkdiv #(50000000) clkDiv(.rstn(rstn),
.iclk(sys_clk), .oclk(clk));
m1 #(.width(4)) m1I(.clk(clk),
.rstn(rstn), .leds(leds[3:0]));
cnt #(.width(2)) cntUp(.clk(clk),
.top(3), .rstn(rstn), .clr_it(rstn_it), .start(1), .freerun(1),
.cnt(leds[6:4]), .it(leds[7]));
endmodule
module m1_sim;
wire sys_clk;
sim_clk simClk(sys_clk);
reg rstn;
initial begin
rstn = 0;
#2 rstn = 1;
end
wire clk;
clkdiv #(50) clkDiv(.rstn(rstn), .iclk(sys_clk), .oclk(clk));
wire [3:0] leds0;
wire [2:0] leds1;
wire led3;
m1 #(.width(4)) m1I(.clk(clk), .rstn(rstn), .leds(leds0));
cnt #(.width(3)) cntUp(.clk(clk), .top(3), .rstn(rstn), .start(1), .freerun(1), .cnt(leds1), .it(led3));
initial begin
$dumpfile(`VCD_PATH);
$dumpvars();
// $monitor("T=%t, i=%0d", $time, clk);
#2000 $finish;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: iobdg_dbg.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: iobdg_dbg (IO Bridge debug/visibility)
// Description:
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module iobdg_dbg (/*AUTOARG*/
// Outputs
l2_vis_buf_wr_lo_l, l2_vis_buf_wr_hi_l, l2_vis_buf_tail_ptr,
l2_vis_buf_rd_lo_l, l2_vis_buf_rd_hi_l, l2_vis_buf_head_ptr,
l2_vis_buf_din_lo, l2_vis_buf_din_hi, l2_vis_armin,
iob_jbi_dbg_lo_vld, iob_jbi_dbg_lo_data, iob_jbi_dbg_hi_vld,
iob_jbi_dbg_hi_data, iob_io_dbg_en, iob_io_dbg_data,
iob_io_dbg_ck_p, iob_io_dbg_ck_n, iob_clk_tr, iob_clk_l2_tr,
// Inputs
ucb_buf_acpt, tx_sync, tap_iob_vld, tap_iob_stall, tap_iob_data,
rx_sync, rst_l, l2_vis_buf_dout_lo, l2_vis_buf_dout_hi,
l2_dbgbus_23, l2_dbgbus_01, jbi_iob_spi_vld, jbi_iob_spi_stall,
jbi_iob_spi_data, jbi_iob_pio_vld, jbi_iob_pio_stall,
jbi_iob_pio_data, iob_tap_vld, iob_tap_stall, iob_tap_data,
iob_jbi_spi_vld, iob_jbi_spi_stall, iob_jbi_spi_data,
iob_jbi_pio_vld, iob_jbi_pio_stall, iob_jbi_pio_data,
iob_dram13_vld, iob_dram13_stall, iob_dram13_data, iob_dram02_vld,
iob_dram02_stall, iob_dram02_data, iob_clk_vld, iob_clk_stall,
iob_clk_data, io_trigin, dram13_iob_vld, dram13_iob_stall,
dram13_iob_data, dram02_iob_vld, dram02_iob_stall,
dram02_iob_data, dbg_en_23, dbg_en_01,
creg_dbg_l2_vis_trig_delay_s, creg_dbg_l2_vis_maskb_s,
creg_dbg_l2_vis_maska_s, creg_dbg_l2_vis_ctrl,
creg_dbg_l2_vis_cmpb_s, creg_dbg_l2_vis_cmpa_s,
creg_dbg_jbus_lo_mask1, creg_dbg_jbus_lo_mask0,
creg_dbg_jbus_lo_cnt1, creg_dbg_jbus_lo_cnt0,
creg_dbg_jbus_lo_cmp1, creg_dbg_jbus_lo_cmp0,
creg_dbg_jbus_hi_mask1, creg_dbg_jbus_hi_mask0,
creg_dbg_jbus_hi_cnt1, creg_dbg_jbus_hi_cnt0,
creg_dbg_jbus_hi_cmp1, creg_dbg_jbus_hi_cmp0, creg_dbg_jbus_ctrl,
creg_dbg_iob_vis_ctrl, creg_dbg_enet_idleval, creg_dbg_enet_ctrl,
cpu_rst_l, cpu_clk, clk_iob_vld, clk_iob_stall, clk_iob_data, clk,
c2i_packet
);
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [`UCB_64PAY_PKT_WIDTH-1:0]c2i_packet; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input clk; // To iobdg_dbg_iob of iobdg_dbg_iob.v, ...
input [`CLK_IOB_WIDTH-1:0]clk_iob_data; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input clk_iob_stall; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input clk_iob_vld; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input cpu_clk; // To iobdg_dbg_l2 of iobdg_dbg_l2.v
input cpu_rst_l; // To iobdg_dbg_l2 of iobdg_dbg_l2.v
input [63:0] creg_dbg_enet_ctrl; // To iobdg_dbg_porta of iobdg_dbg_porta.v
input [63:0] creg_dbg_enet_idleval; // To iobdg_dbg_porta of iobdg_dbg_porta.v
input [63:0] creg_dbg_iob_vis_ctrl; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input [63:0] creg_dbg_jbus_ctrl; // To iobdg_dbg_portb_hi of iobdg_dbg_portb.v, ...
input [63:0] creg_dbg_jbus_hi_cmp0; // To iobdg_dbg_portb_hi of iobdg_dbg_portb.v
input [63:0] creg_dbg_jbus_hi_cmp1; // To iobdg_dbg_portb_hi of iobdg_dbg_portb.v
input [63:0] creg_dbg_jbus_hi_cnt0; // To iobdg_dbg_portb_hi of iobdg_dbg_portb.v
input [63:0] creg_dbg_jbus_hi_cnt1; // To iobdg_dbg_portb_hi of iobdg_dbg_portb.v
input [63:0] creg_dbg_jbus_hi_mask0; // To iobdg_dbg_portb_hi of iobdg_dbg_portb.v
input [63:0] creg_dbg_jbus_hi_mask1; // To iobdg_dbg_portb_hi of iobdg_dbg_portb.v
input [63:0] creg_dbg_jbus_lo_cmp0; // To iobdg_dbg_portb_lo of iobdg_dbg_portb.v
input [63:0] creg_dbg_jbus_lo_cmp1; // To iobdg_dbg_portb_lo of iobdg_dbg_portb.v
input [63:0] creg_dbg_jbus_lo_cnt0; // To iobdg_dbg_portb_lo of iobdg_dbg_portb.v
input [63:0] creg_dbg_jbus_lo_cnt1; // To iobdg_dbg_portb_lo of iobdg_dbg_portb.v
input [63:0] creg_dbg_jbus_lo_mask0; // To iobdg_dbg_portb_lo of iobdg_dbg_portb.v
input [63:0] creg_dbg_jbus_lo_mask1; // To iobdg_dbg_portb_lo of iobdg_dbg_portb.v
input [63:0] creg_dbg_l2_vis_cmpa_s; // To iobdg_dbg_l2 of iobdg_dbg_l2.v
input [63:0] creg_dbg_l2_vis_cmpb_s; // To iobdg_dbg_l2 of iobdg_dbg_l2.v
input [63:0] creg_dbg_l2_vis_ctrl; // To iobdg_dbg_l2 of iobdg_dbg_l2.v
input [63:0] creg_dbg_l2_vis_maska_s;// To iobdg_dbg_l2 of iobdg_dbg_l2.v
input [63:0] creg_dbg_l2_vis_maskb_s;// To iobdg_dbg_l2 of iobdg_dbg_l2.v
input [63:0] creg_dbg_l2_vis_trig_delay_s;// To iobdg_dbg_l2 of iobdg_dbg_l2.v
input dbg_en_01; // To iobdg_dbg_l2 of iobdg_dbg_l2.v
input dbg_en_23; // To iobdg_dbg_l2 of iobdg_dbg_l2.v
input [`DRAM_IOB_WIDTH-1:0]dram02_iob_data; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input dram02_iob_stall; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input dram02_iob_vld; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input [`DRAM_IOB_WIDTH-1:0]dram13_iob_data; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input dram13_iob_stall; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input dram13_iob_vld; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input io_trigin; // To iobdg_dbg_porta of iobdg_dbg_porta.v
input [`IOB_CLK_WIDTH-1:0]iob_clk_data; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input iob_clk_stall; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input iob_clk_vld; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input [`IOB_DRAM_WIDTH-1:0]iob_dram02_data; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input iob_dram02_stall; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input iob_dram02_vld; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input [`IOB_DRAM_WIDTH-1:0]iob_dram13_data; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input iob_dram13_stall; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input iob_dram13_vld; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input [`IOB_JBI_WIDTH-1:0]iob_jbi_pio_data; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input iob_jbi_pio_stall; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input iob_jbi_pio_vld; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input [`IOB_SPI_WIDTH-1:0]iob_jbi_spi_data; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input iob_jbi_spi_stall; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input iob_jbi_spi_vld; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input [`IOB_TAP_WIDTH-1:0]iob_tap_data; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input iob_tap_stall; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input iob_tap_vld; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input [`JBI_IOB_WIDTH-1:0]jbi_iob_pio_data; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input jbi_iob_pio_stall; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input jbi_iob_pio_vld; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input [`SPI_IOB_WIDTH-1:0]jbi_iob_spi_data; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input jbi_iob_spi_stall; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input jbi_iob_spi_vld; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input [39:0] l2_dbgbus_01; // To iobdg_dbg_l2 of iobdg_dbg_l2.v
input [39:0] l2_dbgbus_23; // To iobdg_dbg_l2 of iobdg_dbg_l2.v
input [64:0] l2_vis_buf_dout_hi; // To iobdg_dbg_l2 of iobdg_dbg_l2.v
input [64:0] l2_vis_buf_dout_lo; // To iobdg_dbg_l2 of iobdg_dbg_l2.v
input rst_l; // To iobdg_dbg_iob of iobdg_dbg_iob.v, ...
input rx_sync; // To iobdg_dbg_l2 of iobdg_dbg_l2.v
input [`TAP_IOB_WIDTH-1:0]tap_iob_data; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input tap_iob_stall; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input tap_iob_vld; // To iobdg_dbg_iob of iobdg_dbg_iob.v
input tx_sync; // To iobdg_dbg_l2 of iobdg_dbg_l2.v
input ucb_buf_acpt; // To iobdg_dbg_iob of iobdg_dbg_iob.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output iob_clk_l2_tr; // From iobdg_dbg_l2 of iobdg_dbg_l2.v
output iob_clk_tr; // From iobdg_dbg_porta of iobdg_dbg_porta.v
output [2:0] iob_io_dbg_ck_n; // From iobdg_dbg_porta of iobdg_dbg_porta.v
output [2:0] iob_io_dbg_ck_p; // From iobdg_dbg_porta of iobdg_dbg_porta.v
output [39:0] iob_io_dbg_data; // From iobdg_dbg_porta of iobdg_dbg_porta.v
output iob_io_dbg_en; // From iobdg_dbg_porta of iobdg_dbg_porta.v
output [47:0] iob_jbi_dbg_hi_data; // From iobdg_dbg_portb_hi of iobdg_dbg_portb.v
output iob_jbi_dbg_hi_vld; // From iobdg_dbg_portb_hi of iobdg_dbg_portb.v
output [47:0] iob_jbi_dbg_lo_data; // From iobdg_dbg_portb_lo of iobdg_dbg_portb.v
output iob_jbi_dbg_lo_vld; // From iobdg_dbg_portb_lo of iobdg_dbg_portb.v
output l2_vis_armin; // From iobdg_dbg_porta of iobdg_dbg_porta.v
output [64:0] l2_vis_buf_din_hi; // From iobdg_dbg_l2 of iobdg_dbg_l2.v
output [64:0] l2_vis_buf_din_lo; // From iobdg_dbg_l2 of iobdg_dbg_l2.v
output [`IOB_L2_VIS_BUF_INDEX-1:0]l2_vis_buf_head_ptr;// From iobdg_dbg_l2 of iobdg_dbg_l2.v
output l2_vis_buf_rd_hi_l; // From iobdg_dbg_l2 of iobdg_dbg_l2.v
output l2_vis_buf_rd_lo_l; // From iobdg_dbg_l2 of iobdg_dbg_l2.v
output [`IOB_L2_VIS_BUF_INDEX-1:0]l2_vis_buf_tail_ptr;// From iobdg_dbg_l2 of iobdg_dbg_l2.v
output l2_vis_buf_wr_hi_l; // From iobdg_dbg_l2 of iobdg_dbg_l2.v
output l2_vis_buf_wr_lo_l; // From iobdg_dbg_l2 of iobdg_dbg_l2.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [43:0] iob_dbg_bus; // From iobdg_dbg_iob of iobdg_dbg_iob.v
wire [39:0] l2_dbg_data; // From iobdg_dbg_l2 of iobdg_dbg_l2.v
wire l2_dbg_vld; // From iobdg_dbg_l2 of iobdg_dbg_l2.v
// End of automatics
wire [`IOB_JBI_WIDTH-1:0] iob_jbi_pio_data_d1;
wire [`JBI_IOB_WIDTH-1:0] jbi_iob_pio_data_d1;
wire [5:0] iob_vld_bus;
wire [5:0] iob_stall_bus;
wire [5:0] iob_vld_bus_d1;
wire [5:0] iob_stall_bus_d1;
wire [5:0] iob_vld_qual_bus;
wire [5:0] iob_soh_bus;
wire [7:0] l2_dbg_tstamp;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
/*****************************************************************
* IOB debug mux
*****************************************************************/
iobdg_dbg_iob iobdg_dbg_iob (.iob_jbi_pio_data_d1(iob_jbi_pio_data_d1[`IOB_JBI_WIDTH-1:0]),
.jbi_iob_pio_data_d1(jbi_iob_pio_data_d1[`JBI_IOB_WIDTH-1:0]),
/*AUTOINST*/
// Outputs
.iob_dbg_bus(iob_dbg_bus[43:0]),
// Inputs
.rst_l (rst_l),
.clk (clk),
.c2i_packet(c2i_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
.ucb_buf_acpt(ucb_buf_acpt),
.creg_dbg_iob_vis_ctrl(creg_dbg_iob_vis_ctrl[63:0]),
.iob_clk_vld(iob_clk_vld),
.iob_clk_data(iob_clk_data[`IOB_CLK_WIDTH-1:0]),
.clk_iob_stall(clk_iob_stall),
.iob_dram02_vld(iob_dram02_vld),
.iob_dram02_data(iob_dram02_data[`IOB_DRAM_WIDTH-1:0]),
.dram02_iob_stall(dram02_iob_stall),
.iob_dram13_vld(iob_dram13_vld),
.iob_dram13_data(iob_dram13_data[`IOB_DRAM_WIDTH-1:0]),
.dram13_iob_stall(dram13_iob_stall),
.iob_jbi_pio_vld(iob_jbi_pio_vld),
.iob_jbi_pio_data(iob_jbi_pio_data[`IOB_JBI_WIDTH-1:0]),
.jbi_iob_pio_stall(jbi_iob_pio_stall),
.iob_jbi_spi_vld(iob_jbi_spi_vld),
.iob_jbi_spi_data(iob_jbi_spi_data[`IOB_SPI_WIDTH-1:0]),
.jbi_iob_spi_stall(jbi_iob_spi_stall),
.iob_tap_vld(iob_tap_vld),
.iob_tap_data(iob_tap_data[`IOB_TAP_WIDTH-1:0]),
.tap_iob_stall(tap_iob_stall),
.clk_iob_vld(clk_iob_vld),
.clk_iob_data(clk_iob_data[`CLK_IOB_WIDTH-1:0]),
.iob_clk_stall(iob_clk_stall),
.dram02_iob_vld(dram02_iob_vld),
.dram02_iob_data(dram02_iob_data[`DRAM_IOB_WIDTH-1:0]),
.iob_dram02_stall(iob_dram02_stall),
.dram13_iob_vld(dram13_iob_vld),
.dram13_iob_data(dram13_iob_data[`DRAM_IOB_WIDTH-1:0]),
.iob_dram13_stall(iob_dram13_stall),
.jbi_iob_pio_vld(jbi_iob_pio_vld),
.jbi_iob_pio_data(jbi_iob_pio_data[`JBI_IOB_WIDTH-1:0]),
.iob_jbi_pio_stall(iob_jbi_pio_stall),
.jbi_iob_spi_vld(jbi_iob_spi_vld),
.jbi_iob_spi_data(jbi_iob_spi_data[`SPI_IOB_WIDTH-1:0]),
.iob_jbi_spi_stall(iob_jbi_spi_stall),
.tap_iob_vld(tap_iob_vld),
.tap_iob_data(tap_iob_data[`TAP_IOB_WIDTH-1:0]),
.iob_tap_stall(iob_tap_stall));
assign iob_vld_bus = {iob_dbg_bus[43],
iob_dbg_bus[41],
iob_dbg_bus[39],
iob_dbg_bus[37],
iob_dbg_bus[35],
iob_dbg_bus[33]};
assign iob_stall_bus = {iob_dbg_bus[42],
iob_dbg_bus[40],
iob_dbg_bus[38],
iob_dbg_bus[36],
iob_dbg_bus[34],
iob_dbg_bus[32]};
dff_ns #(6) iob_vld_bus_d1_ff (.din(iob_vld_bus),
.clk(clk),
.q(iob_vld_bus_d1));
dff_ns #(6) iob_stall_bus_d1_ff (.din(iob_stall_bus),
.clk(clk),
.q(iob_stall_bus_d1));
assign iob_vld_qual_bus = iob_vld_bus & ~iob_stall_bus_d1;
assign iob_soh_bus = ~iob_vld_bus_d1 & iob_vld_bus;
/*****************************************************************
* L2 debug filter/buffer
*****************************************************************/
/* iobdg_dbg_l2 AUTO_TEMPLATE (
// Outputs
.l2_dbg_tstamp ({l2_dbg_tstamp[7:0]}),
// Inputs
); */
iobdg_dbg_l2 iobdg_dbg_l2 (
/*AUTOINST*/
// Outputs
.l2_dbg_vld(l2_dbg_vld),
.l2_dbg_tstamp({l2_dbg_tstamp[7:0]}), // Templated
.l2_dbg_data(l2_dbg_data[39:0]),
.iob_clk_l2_tr(iob_clk_l2_tr),
.l2_vis_buf_wr_lo_l(l2_vis_buf_wr_lo_l),
.l2_vis_buf_wr_hi_l(l2_vis_buf_wr_hi_l),
.l2_vis_buf_rd_lo_l(l2_vis_buf_rd_lo_l),
.l2_vis_buf_rd_hi_l(l2_vis_buf_rd_hi_l),
.l2_vis_buf_tail_ptr(l2_vis_buf_tail_ptr[`IOB_L2_VIS_BUF_INDEX-1:0]),
.l2_vis_buf_head_ptr(l2_vis_buf_head_ptr[`IOB_L2_VIS_BUF_INDEX-1:0]),
.l2_vis_buf_din_lo(l2_vis_buf_din_lo[64:0]),
.l2_vis_buf_din_hi(l2_vis_buf_din_hi[64:0]),
// Inputs
.cpu_rst_l(cpu_rst_l),
.rst_l (rst_l),
.cpu_clk (cpu_clk),
.clk (clk),
.tx_sync (tx_sync),
.rx_sync (rx_sync),
.l2_dbgbus_01(l2_dbgbus_01[39:0]),
.l2_dbgbus_23(l2_dbgbus_23[39:0]),
.dbg_en_01(dbg_en_01),
.dbg_en_23(dbg_en_23),
.creg_dbg_l2_vis_ctrl(creg_dbg_l2_vis_ctrl[63:0]),
.creg_dbg_l2_vis_maska_s(creg_dbg_l2_vis_maska_s[63:0]),
.creg_dbg_l2_vis_cmpa_s(creg_dbg_l2_vis_cmpa_s[63:0]),
.creg_dbg_l2_vis_maskb_s(creg_dbg_l2_vis_maskb_s[63:0]),
.creg_dbg_l2_vis_cmpb_s(creg_dbg_l2_vis_cmpb_s[63:0]),
.creg_dbg_l2_vis_trig_delay_s(creg_dbg_l2_vis_trig_delay_s[63:0]),
.l2_vis_buf_dout_lo(l2_vis_buf_dout_lo[64:0]),
.l2_vis_buf_dout_hi(l2_vis_buf_dout_hi[64:0]));
/*****************************************************************
* Debug Port A
*****************************************************************/
/* iobdg_dbg_porta AUTO_TEMPLATE (
// Outputs
// Inputs
.src0_data (l2_dbg_data[39:0]),
.src1_data ({l2_dbg_data[39:30],l2_dbg_tstamp[7:0],l2_dbg_data[21:0]}),
.src2_data (iob_dbg_bus[39:0]),
.src3_data ({1'b0,|iob_soh_bus[5:0],iob_vld_qual_bus[5:0],iob_dbg_bus[31:0]}),
.src4_data ({iob_dbg_bus[39:35],iob_dbg_bus[41],iob_dbg_bus[33:0]}),
.src0_vld (l2_dbg_vld),
.src1_vld (l2_dbg_vld),
.src2_vld (1'b1),
.src3_vld ({|iob_vld_qual_bus[5:0]}),
.src4_vld (iob_dbg_bus[43]),
); */
iobdg_dbg_porta iobdg_dbg_porta (
/*AUTOINST*/
// Outputs
.iob_io_dbg_data(iob_io_dbg_data[39:0]),
.iob_io_dbg_en(iob_io_dbg_en),
.iob_io_dbg_ck_p(iob_io_dbg_ck_p[2:0]),
.iob_io_dbg_ck_n(iob_io_dbg_ck_n[2:0]),
.l2_vis_armin(l2_vis_armin),
.iob_clk_tr(iob_clk_tr),
// Inputs
.rst_l(rst_l),
.clk(clk),
.src0_data(l2_dbg_data[39:0]), // Templated
.src1_data({l2_dbg_data[39:30],l2_dbg_tstamp[7:0],l2_dbg_data[21:0]}), // Templated
.src2_data(iob_dbg_bus[39:0]), // Templated
.src3_data({1'b0,|iob_soh_bus[5:0],iob_vld_qual_bus[5:0],iob_dbg_bus[31:0]}), // Templated
.src4_data({iob_dbg_bus[39:35],iob_dbg_bus[41],iob_dbg_bus[33:0]}), // Templated
.src0_vld(l2_dbg_vld), // Templated
.src1_vld(l2_dbg_vld), // Templated
.src2_vld(1'b1), // Templated
.src3_vld({|iob_vld_qual_bus[5:0]}), // Templated
.src4_vld(iob_dbg_bus[43]), // Templated
.creg_dbg_enet_ctrl(creg_dbg_enet_ctrl[63:0]),
.creg_dbg_enet_idleval(creg_dbg_enet_idleval[63:0]),
.io_trigin(io_trigin));
/*****************************************************************
* Debug Port B Hi
*****************************************************************/
/* iobdg_dbg_portb AUTO_TEMPLATE (
// Outputs
.dbg_data (iob_jbi_dbg_hi_data[47:0]),
.dbg_vld (iob_jbi_dbg_hi_vld),
// Inputs
.src0_data ({l2_dbg_vld,l2_dbg_tstamp[7:0],l2_dbg_data[39:0]}),
.src2_data ({iob_vld_qual_bus[4],4'b0,iob_soh_bus[5:4],iob_vld_qual_bus[5:4],iob_dbg_bus[39:0]}),
.src3_data ({iob_vld_qual_bus[4],4'b0,iob_soh_bus[5:4],iob_vld_qual_bus[5:4],iob_soh_bus[3:0],iob_vld_qual_bus[3:0],iob_dbg_bus[31:0]}),
.src4_data ({iob_dbg_bus[40],4'b0,iob_dbg_bus[43:0]}),
.src0_vld (l2_dbg_vld),
.src2_vld ({|iob_vld_qual_bus[5:4]}),
.src3_vld ({|iob_vld_qual_bus[5:0]}),
.src4_vld (1'b1),
.i_am_hi (1'b1),
.creg_dbg_jbus_ctrl (creg_dbg_jbus_ctrl[63:0]),
.creg_dbg_jbus_mask0(creg_dbg_jbus_hi_mask0[63:0]),
.creg_dbg_jbus_cmp0 (creg_dbg_jbus_hi_cmp0[63:0]),
.creg_dbg_jbus_cnt0 (creg_dbg_jbus_hi_cnt0[63:0]),
.creg_dbg_jbus_mask1(creg_dbg_jbus_hi_mask1[63:0]),
.creg_dbg_jbus_cmp1 (creg_dbg_jbus_hi_cmp1[63:0]),
.creg_dbg_jbus_cnt1 (creg_dbg_jbus_hi_cnt1[63:0]),
); */
iobdg_dbg_portb iobdg_dbg_portb_hi (
/*AUTOINST*/
// Outputs
.dbg_data(iob_jbi_dbg_hi_data[47:0]), // Templated
.dbg_vld(iob_jbi_dbg_hi_vld), // Templated
// Inputs
.rst_l(rst_l),
.clk(clk),
.src0_data({l2_dbg_vld,l2_dbg_tstamp[7:0],l2_dbg_data[39:0]}), // Templated
.src2_data({iob_vld_qual_bus[4],4'b0,iob_soh_bus[5:4],iob_vld_qual_bus[5:4],iob_dbg_bus[39:0]}), // Templated
.src3_data({iob_vld_qual_bus[4],4'b0,iob_soh_bus[5:4],iob_vld_qual_bus[5:4],iob_soh_bus[3:0],iob_vld_qual_bus[3:0],iob_dbg_bus[31:0]}), // Templated
.src4_data({iob_dbg_bus[40],4'b0,iob_dbg_bus[43:0]}), // Templated
.src0_vld(l2_dbg_vld), // Templated
.src2_vld({|iob_vld_qual_bus[5:4]}), // Templated
.src3_vld({|iob_vld_qual_bus[5:0]}), // Templated
.src4_vld(1'b1), // Templated
.i_am_hi(1'b1), // Templated
.creg_dbg_jbus_ctrl(creg_dbg_jbus_ctrl[63:0]), // Templated
.creg_dbg_jbus_mask0(creg_dbg_jbus_hi_mask0[63:0]), // Templated
.creg_dbg_jbus_cmp0(creg_dbg_jbus_hi_cmp0[63:0]), // Templated
.creg_dbg_jbus_cnt0(creg_dbg_jbus_hi_cnt0[63:0]), // Templated
.creg_dbg_jbus_mask1(creg_dbg_jbus_hi_mask1[63:0]), // Templated
.creg_dbg_jbus_cmp1(creg_dbg_jbus_hi_cmp1[63:0]), // Templated
.creg_dbg_jbus_cnt1(creg_dbg_jbus_hi_cnt1[63:0])); // Templated
/*****************************************************************
* Debug Port B Lo
*****************************************************************/
/* iobdg_dbg_portb AUTO_TEMPLATE (
// Outputs
.dbg_data (iob_jbi_dbg_lo_data[47:0]),
.dbg_vld (iob_jbi_dbg_lo_vld),
// Inputs
.src0_data ({l2_dbg_vld,l2_dbg_tstamp[7:0],l2_dbg_data[39:0]}),
.src2_data ({iob_vld_qual_bus[4],4'b0,iob_soh_bus[5:4],iob_vld_qual_bus[5:4],jbi_iob_pio_data_d1[7:0],iob_jbi_pio_data_d1[31:0]}),
.src3_data ({iob_vld_qual_bus[4],4'b0,iob_soh_bus[5:4],iob_vld_qual_bus[5:4],iob_soh_bus[3:0],iob_vld_qual_bus[3:0],iob_dbg_bus[31:0]}),
.src4_data ({iob_dbg_bus[40],4'b0,iob_dbg_bus[43:0]}),
.src0_vld (l2_dbg_vld),
.src2_vld ({|iob_vld_qual_bus[5:4]}),
.src3_vld ({|iob_vld_qual_bus[5:0]}),
.src4_vld (1'b1),
.i_am_hi (1'b0),
.creg_dbg_jbus_ctrl (creg_dbg_jbus_ctrl[63:0]),
.creg_dbg_jbus_mask0(creg_dbg_jbus_lo_mask0[63:0]),
.creg_dbg_jbus_cmp0 (creg_dbg_jbus_lo_cmp0[63:0]),
.creg_dbg_jbus_cnt0 (creg_dbg_jbus_lo_cnt0[63:0]),
.creg_dbg_jbus_mask1(creg_dbg_jbus_lo_mask1[63:0]),
.creg_dbg_jbus_cmp1 (creg_dbg_jbus_lo_cmp1[63:0]),
.creg_dbg_jbus_cnt1 (creg_dbg_jbus_lo_cnt1[63:0]),
); */
iobdg_dbg_portb iobdg_dbg_portb_lo (
/*AUTOINST*/
// Outputs
.dbg_data(iob_jbi_dbg_lo_data[47:0]), // Templated
.dbg_vld(iob_jbi_dbg_lo_vld), // Templated
// Inputs
.rst_l(rst_l),
.clk(clk),
.src0_data({l2_dbg_vld,l2_dbg_tstamp[7:0],l2_dbg_data[39:0]}), // Templated
.src2_data({iob_vld_qual_bus[4],4'b0,iob_soh_bus[5:4],iob_vld_qual_bus[5:4],jbi_iob_pio_data_d1[7:0],iob_jbi_pio_data_d1[31:0]}), // Templated
.src3_data({iob_vld_qual_bus[4],4'b0,iob_soh_bus[5:4],iob_vld_qual_bus[5:4],iob_soh_bus[3:0],iob_vld_qual_bus[3:0],iob_dbg_bus[31:0]}), // Templated
.src4_data({iob_dbg_bus[40],4'b0,iob_dbg_bus[43:0]}), // Templated
.src0_vld(l2_dbg_vld), // Templated
.src2_vld({|iob_vld_qual_bus[5:4]}), // Templated
.src3_vld({|iob_vld_qual_bus[5:0]}), // Templated
.src4_vld(1'b1), // Templated
.i_am_hi(1'b0), // Templated
.creg_dbg_jbus_ctrl(creg_dbg_jbus_ctrl[63:0]), // Templated
.creg_dbg_jbus_mask0(creg_dbg_jbus_lo_mask0[63:0]), // Templated
.creg_dbg_jbus_cmp0(creg_dbg_jbus_lo_cmp0[63:0]), // Templated
.creg_dbg_jbus_cnt0(creg_dbg_jbus_lo_cnt0[63:0]), // Templated
.creg_dbg_jbus_mask1(creg_dbg_jbus_lo_mask1[63:0]), // Templated
.creg_dbg_jbus_cmp1(creg_dbg_jbus_lo_cmp1[63:0]), // Templated
.creg_dbg_jbus_cnt1(creg_dbg_jbus_lo_cnt1[63:0])); // Templated
endmodule // iobdg_dbg
// Local Variables:
// verilog-library-directories:("." "../../common/rtl")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2B_4_V
`define SKY130_FD_SC_HDLL__NAND2B_4_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog wrapper for nand2b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand2b_4 (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand2b_4 (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2B_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SDFRTP_FUNCTIONAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EDFXBP_SYMBOL_V
`define SKY130_FD_SC_MS__EDFXBP_SYMBOL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__edfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EDFXBP_SYMBOL_V
|
`timescale 1ns/1ps
module tb_multiplier (); /* this is automatically generated */
// clock
initial begin
clk = 0;
forever #5 clk = ~clk;
end
// (*NOTE*) replace reset, clock
reg [SW-1:0] a;
reg [SW-1:0] b;
// wire [2*SW-2:0] BinaryRES;
// wire [2*SW-1:0] FKOARES;
// wire [2*SW-1:0] RKOARES;
//wire [2*SW-2:0] SimpleRES;
// wire [2*SW-2:0] HybridRES;
wire [2*SW-1:0] Simple_KOA;
// wire [2*SW-1:0] Recursive_KOA;
reg clk;
parameter SW = 24;
// Bks26 inst_Bks26 (.a(a), .b(b), .d(BinaryRES));
// Sgf_Multiplication #(.SW(SW)) inst_Sgf_Multiplication (.clk(clk),.Data_A_i(a), .Data_B_i(b), .sgf_result_o(FKOARES));
// Sks26 inst_Sks26 (.a(a), .b(b), .d(SimpleRES));
// Hks26 inst_Hks26 (.a(a), .b(b), .d(HybridRES));
//RKOA #(.SW(SW)) inst_RKOA (.Data_A_i(a), .Data_B_i(b), .sgf_result_o(RKOARES));
Simple_KOA #(.SW(SW)) i_Simple_KOA (.Data_A_i(a), .Data_B_i(b), .sgf_result_o(Simple_KOA));
// Recursive_KOA #(.SW(SW)) inst_Recursive_KOA (.Data_A_i(a), .Data_B_i(b), .sgf_result_o(Recursive_KOA));
integer i = 1;
parameter cycles = 1024;
initial begin
$monitor(a,b, Simple_KOA);
end
initial begin
b = 1;
a = 1;
#100;
b = 2;
repeat (cycles) begin
a = i;
b = b + 2;
i = i + 1;
#50;
end
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4_BLACKBOX_V
`define SKY130_FD_SC_HDLL__AND4_BLACKBOX_V
/**
* and4: 4-input AND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4_BLACKBOX_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: nco_g.v
// /___/ /\ Timestamp: Tue Nov 19 22:36:02 2013
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog "C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/CON SOLO NCO/tec-drums/ipcore_dir/tmp/_cg/nco_g.ngc" "C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/CON SOLO NCO/tec-drums/ipcore_dir/tmp/_cg/nco_g.v"
// Device : 6slx16csg324-3
// Input file : C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/CON SOLO NCO/tec-drums/ipcore_dir/tmp/_cg/nco_g.ngc
// Output file : C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/CON SOLO NCO/tec-drums/ipcore_dir/tmp/_cg/nco_g.v
// # of Modules : 1
// Design Name : nco_g
// Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module nco_g (
clk, sine
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [15 : 0] sine;
// synthesis translate_off
wire sig00000001;
wire sig00000002;
wire sig00000003;
wire sig00000004;
wire sig00000005;
wire sig00000006;
wire sig00000007;
wire sig00000008;
wire sig00000009;
wire sig0000000a;
wire sig0000000b;
wire sig0000000c;
wire sig0000000d;
wire sig0000000e;
wire sig0000000f;
wire sig00000010;
wire sig00000011;
wire sig00000012;
wire sig00000013;
wire sig00000014;
wire sig00000015;
wire sig00000016;
wire sig00000017;
wire sig00000018;
wire sig00000019;
wire sig0000001a;
wire sig0000001b;
wire sig0000001c;
wire sig0000001d;
wire sig0000001e;
wire sig0000001f;
wire sig00000020;
wire sig00000021;
wire sig00000022;
wire sig00000023;
wire sig00000024;
wire sig00000025;
wire sig00000026;
wire sig00000027;
wire sig00000028;
wire sig00000029;
wire sig0000002a;
wire sig0000002b;
wire sig0000002c;
wire sig0000002d;
wire sig0000002e;
wire sig0000002f;
wire sig00000030;
wire sig00000031;
wire sig00000032;
wire sig00000033;
wire sig00000034;
wire sig00000035;
wire sig00000036;
wire sig00000037;
wire sig00000038;
wire sig00000039;
wire sig0000003a;
wire sig0000003b;
wire sig0000003c;
wire sig0000003d;
wire sig0000003e;
wire sig0000003f;
wire sig00000040;
wire sig00000041;
wire sig00000042;
wire sig00000043;
wire sig00000044;
wire sig00000045;
wire sig00000046;
wire sig00000047;
wire sig00000048;
wire sig00000049;
wire sig0000004a;
wire sig0000004b;
wire sig0000004c;
wire sig0000004d;
wire sig0000004e;
wire sig0000004f;
wire sig00000050;
wire sig00000051;
wire sig00000052;
wire sig00000053;
wire sig00000054;
wire sig00000055;
wire sig00000056;
wire sig00000057;
wire sig00000058;
wire sig00000059;
wire sig0000005a;
wire sig0000005b;
wire sig0000005c;
wire sig0000005d;
wire sig0000005e;
wire sig0000005f;
wire sig00000060;
wire sig00000061;
wire sig00000062;
wire sig00000063;
wire sig00000064;
wire sig00000065;
wire sig00000066;
wire sig00000067;
wire sig00000068;
wire sig00000069;
wire sig0000006a;
wire sig0000006b;
wire sig0000006c;
wire sig0000006d;
wire sig0000006e;
wire sig0000006f;
wire sig00000070;
wire sig00000071;
wire sig00000072;
wire sig00000073;
wire sig00000074;
wire sig00000075;
wire sig00000076;
wire sig00000077;
wire sig00000078;
wire sig00000079;
wire sig0000007a;
wire sig0000007b;
wire sig0000007c;
wire sig0000007d;
wire sig0000007e;
wire sig0000007f;
wire sig00000080;
wire sig00000081;
wire sig00000082;
wire sig00000083;
wire sig00000084;
wire sig00000085;
wire sig00000086;
wire sig00000087;
wire sig00000088;
wire sig00000089;
wire sig0000008a;
wire sig0000008b;
wire sig0000008c;
wire sig0000008d;
wire sig0000008e;
wire sig0000008f;
wire sig00000090;
wire sig00000091;
wire sig00000092;
wire sig00000093;
wire sig00000094;
wire sig00000095;
wire sig00000096;
wire sig00000097;
wire sig00000098;
wire sig00000099;
wire sig0000009a;
wire sig0000009b;
wire sig0000009c;
wire sig0000009d;
wire sig0000009e;
wire sig0000009f;
wire sig000000a0;
wire sig000000a1;
wire sig000000a2;
wire sig000000a3;
wire sig000000a4;
wire sig000000a5;
wire sig000000a6;
wire sig000000a7;
wire sig000000a8;
wire sig000000a9;
wire sig000000aa;
wire sig000000ab;
wire sig000000ac;
wire sig000000ad;
wire sig000000ae;
wire sig000000af;
wire sig000000b0;
wire sig000000b1;
wire sig000000b2;
wire sig000000b3;
wire sig000000b4;
wire sig000000b5;
wire sig000000b6;
wire sig000000b7;
wire sig000000b8;
wire sig000000b9;
wire sig000000ba;
wire sig000000bb;
wire sig000000bc;
wire sig000000bd;
wire sig000000be;
wire sig000000bf;
wire sig000000c0;
wire sig000000c1;
wire sig000000c2;
wire sig000000c3;
wire sig000000c4;
wire sig000000c5;
wire sig000000c6;
wire sig000000c7;
wire sig000000c8;
wire sig000000c9;
wire sig000000ca;
wire sig000000cb;
wire sig000000cc;
wire sig000000cd;
wire sig000000ce;
wire sig000000cf;
wire sig000000d0;
wire sig000000d1;
wire sig000000d2;
wire sig000000d3;
wire sig000000d4;
wire sig000000d5;
wire sig000000d6;
wire sig000000d7;
wire sig000000d8;
wire sig000000d9;
wire sig000000da;
wire sig000000db;
wire sig000000dc;
wire sig000000dd;
wire sig000000de;
wire sig000000df;
wire sig000000e0;
wire sig000000e1;
wire sig000000e2;
wire sig000000e3;
wire sig000000e4;
wire sig000000e5;
wire sig000000e6;
wire sig000000e7;
wire sig000000e8;
wire sig000000e9;
wire sig000000ea;
wire sig000000eb;
wire sig000000ec;
wire sig000000ed;
wire sig000000ee;
wire sig000000ef;
wire sig000000f0;
wire sig000000f1;
wire sig000000f2;
wire sig000000f3;
wire sig000000f4;
wire sig000000f5;
wire sig000000f6;
wire sig000000f7;
wire sig000000f8;
wire sig000000f9;
wire sig000000fa;
wire sig000000fb;
wire sig000000fc;
wire sig000000fd;
wire sig000000fe;
wire sig000000ff;
wire sig00000100;
wire sig00000101;
wire sig00000102;
wire sig00000103;
wire sig00000104;
wire sig00000105;
wire sig00000106;
wire sig00000107;
wire sig00000108;
wire sig00000109;
wire sig0000010a;
wire sig0000010b;
wire sig0000010c;
wire sig0000010d;
wire sig0000010e;
wire sig0000010f;
wire sig00000110;
wire sig00000111;
wire sig00000112;
wire sig00000113;
wire sig00000114;
wire sig00000115;
wire sig00000116;
wire sig00000117;
wire sig00000118;
wire sig00000119;
wire sig0000011a;
wire sig0000011b;
wire sig0000011c;
wire sig0000011d;
wire sig0000011e;
wire sig0000011f;
wire sig00000120;
wire sig00000121;
wire sig00000122;
wire sig00000123;
wire sig00000124;
wire sig00000125;
wire sig00000126;
wire sig00000127;
wire sig00000128;
wire sig00000129;
wire sig0000012a;
wire sig0000012b;
wire sig0000012c;
wire sig0000012d;
wire sig0000012e;
wire sig0000012f;
wire sig00000130;
wire sig00000131;
wire sig00000132;
wire sig00000133;
wire sig00000134;
wire sig00000135;
wire sig00000136;
wire sig00000137;
wire sig00000138;
wire sig00000139;
wire sig0000013a;
wire sig0000013b;
wire sig0000013c;
wire sig0000013d;
wire sig0000013e;
wire sig0000013f;
wire sig00000140;
wire sig00000141;
wire sig00000142;
wire sig00000143;
wire sig00000144;
wire sig00000145;
wire sig00000146;
wire sig00000147;
wire sig00000148;
wire \blk00000025/sig00000198 ;
wire \blk00000025/sig00000197 ;
wire \blk00000025/sig00000196 ;
wire \blk00000025/sig00000195 ;
wire \blk00000025/sig00000194 ;
wire \blk00000025/sig00000193 ;
wire \blk00000025/sig00000192 ;
wire \blk00000025/sig00000191 ;
wire \blk00000025/sig00000190 ;
wire \blk00000025/sig0000018f ;
wire \blk00000025/sig0000018e ;
wire \blk00000025/sig0000018d ;
wire \blk00000025/sig0000018c ;
wire \blk00000025/sig0000018b ;
wire \blk00000025/sig0000018a ;
wire \blk00000025/sig00000189 ;
wire \blk00000025/sig00000188 ;
wire \blk00000025/sig00000187 ;
wire \blk00000025/sig00000186 ;
wire \blk00000025/sig00000185 ;
wire \blk00000025/sig00000184 ;
wire \blk00000025/sig00000183 ;
wire \blk00000025/sig00000182 ;
wire \blk00000025/sig00000181 ;
wire \blk00000025/sig00000180 ;
wire \blk00000025/sig0000017f ;
wire \blk00000025/sig0000017e ;
wire \blk00000025/sig0000017d ;
wire \blk00000025/sig0000017c ;
wire \blk00000025/sig0000017b ;
wire \blk00000025/sig0000017a ;
wire \blk00000056/sig000001e9 ;
wire \blk00000056/sig000001e8 ;
wire \blk00000056/sig000001e7 ;
wire \blk00000056/sig000001e6 ;
wire \blk00000056/sig000001e5 ;
wire \blk00000056/sig000001e4 ;
wire \blk00000056/sig000001e3 ;
wire \blk00000056/sig000001e2 ;
wire \blk00000056/sig000001e1 ;
wire \blk00000056/sig000001e0 ;
wire \blk00000056/sig000001df ;
wire \blk00000056/sig000001de ;
wire \blk00000056/sig000001dd ;
wire \blk00000056/sig000001dc ;
wire \blk00000056/sig000001db ;
wire \blk00000056/sig000001da ;
wire \blk00000056/sig000001d9 ;
wire \blk00000056/sig000001d8 ;
wire \blk00000056/sig000001d7 ;
wire \blk00000056/sig000001d6 ;
wire \blk00000056/sig000001d5 ;
wire \blk00000056/sig000001d4 ;
wire \blk00000056/sig000001d3 ;
wire \blk00000056/sig000001d2 ;
wire \blk00000056/sig000001d1 ;
wire \blk00000056/sig000001d0 ;
wire \blk00000056/sig000001cf ;
wire \blk00000056/sig000001ce ;
wire \blk00000056/sig000001cd ;
wire \blk00000056/sig000001cc ;
wire \blk00000056/sig000001cb ;
wire \blk00000087/sig000001ff ;
wire \blk00000087/sig000001fe ;
wire \blk00000087/sig000001fd ;
wire \blk00000087/sig000001fc ;
wire \blk00000087/sig000001fb ;
wire \blk00000087/sig000001fa ;
wire \blk00000087/sig000001f9 ;
wire \blk00000087/sig000001f8 ;
wire \blk00000087/sig000001f7 ;
wire \blk00000087/sig000001f6 ;
wire \blk00000087/sig000001f2 ;
wire \blk00000087/sig000001f1 ;
wire \blk00000087/sig000001f0 ;
wire \blk00000087/sig000001ef ;
wire \blk00000087/sig000001ee ;
wire \blk00000087/sig000001ed ;
wire \blk00000087/sig000001ec ;
wire \NLW_blk0000014d_DIPA<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPA<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPA<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPA<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<31>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<30>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<29>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<28>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<27>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<26>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<25>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<24>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<23>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<22>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<21>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<20>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<19>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<18>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<17>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<16>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<15>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<14>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<13>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<12>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<11>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<10>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<9>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<8>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<7>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<6>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<5>_UNCONNECTED ;
wire \NLW_blk0000014d_DOA<4>_UNCONNECTED ;
wire \NLW_blk0000014d_ADDRA<1>_UNCONNECTED ;
wire \NLW_blk0000014d_ADDRA<0>_UNCONNECTED ;
wire \NLW_blk0000014d_ADDRB<1>_UNCONNECTED ;
wire \NLW_blk0000014d_ADDRB<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<31>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<30>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<29>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<28>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<27>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<26>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<25>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<24>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<23>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<22>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<21>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<20>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<19>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<18>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<17>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<16>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<15>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<14>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<13>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<12>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<11>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<10>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<9>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<8>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<7>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<6>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<5>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<4>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DIB<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPA<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPA<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPA<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPA<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPB<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPB<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPB<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DIPB<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPB<3>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPB<2>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPB<1>_UNCONNECTED ;
wire \NLW_blk0000014d_DOPB<0>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<31>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<30>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<29>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<28>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<27>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<26>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<25>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<24>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<23>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<22>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<21>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<20>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<19>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<18>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<17>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<16>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<15>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<14>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<13>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<12>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<11>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<10>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<9>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<8>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<7>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<6>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<5>_UNCONNECTED ;
wire \NLW_blk0000014d_DOB<4>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<31>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<30>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<29>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<28>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<27>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<26>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<25>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<24>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<23>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<22>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<21>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<20>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<19>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<18>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<17>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<16>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<15>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<14>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<13>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<12>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<11>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<10>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<9>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<8>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<7>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<6>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<5>_UNCONNECTED ;
wire \NLW_blk0000014d_DIA<4>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPA<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPA<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPA<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPA<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<31>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<30>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<29>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<28>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<27>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<26>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<25>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<24>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<23>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<22>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<21>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<20>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<19>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<18>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<17>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<16>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<15>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<14>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<13>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<12>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<11>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<10>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<9>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<8>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<7>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<6>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<5>_UNCONNECTED ;
wire \NLW_blk0000014e_DOA<4>_UNCONNECTED ;
wire \NLW_blk0000014e_ADDRA<1>_UNCONNECTED ;
wire \NLW_blk0000014e_ADDRA<0>_UNCONNECTED ;
wire \NLW_blk0000014e_ADDRB<1>_UNCONNECTED ;
wire \NLW_blk0000014e_ADDRB<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<31>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<30>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<29>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<28>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<27>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<26>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<25>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<24>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<23>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<22>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<21>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<20>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<19>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<18>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<17>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<16>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<15>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<14>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<13>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<12>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<11>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<10>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<9>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<8>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<7>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<6>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<5>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<4>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DIB<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPA<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPA<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPA<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPA<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPB<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPB<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPB<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DIPB<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPB<3>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPB<2>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPB<1>_UNCONNECTED ;
wire \NLW_blk0000014e_DOPB<0>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<31>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<30>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<29>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<28>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<27>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<26>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<25>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<24>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<23>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<22>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<21>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<20>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<19>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<18>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<17>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<16>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<15>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<14>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<13>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<12>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<11>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<10>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<9>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<8>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<7>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<6>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<5>_UNCONNECTED ;
wire \NLW_blk0000014e_DOB<4>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<31>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<30>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<29>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<28>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<27>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<26>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<25>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<24>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<23>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<22>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<21>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<20>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<19>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<18>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<17>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<16>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<15>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<14>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<13>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<12>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<11>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<10>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<9>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<8>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<7>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<6>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<5>_UNCONNECTED ;
wire \NLW_blk0000014e_DIA<4>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPA<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPA<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPA<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPA<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<31>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<30>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<29>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<28>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<27>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<26>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<25>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<24>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<23>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<22>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<21>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<20>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<19>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<18>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<17>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<16>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<15>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<14>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<13>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<12>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<11>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<10>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<9>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<8>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<7>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<6>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<5>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<4>_UNCONNECTED ;
wire \NLW_blk0000014f_DOA<3>_UNCONNECTED ;
wire \NLW_blk0000014f_ADDRA<1>_UNCONNECTED ;
wire \NLW_blk0000014f_ADDRA<0>_UNCONNECTED ;
wire \NLW_blk0000014f_ADDRB<1>_UNCONNECTED ;
wire \NLW_blk0000014f_ADDRB<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<31>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<30>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<29>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<28>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<27>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<26>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<25>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<24>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<23>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<22>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<21>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<20>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<19>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<18>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<17>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<16>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<15>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<14>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<13>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<12>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<11>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<10>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<9>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<8>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<7>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<6>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<5>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<4>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DIB<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPA<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPA<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPA<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPA<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPB<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPB<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPB<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DIPB<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPB<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPB<2>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPB<1>_UNCONNECTED ;
wire \NLW_blk0000014f_DOPB<0>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<31>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<30>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<29>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<28>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<27>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<26>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<25>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<24>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<23>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<22>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<21>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<20>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<19>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<18>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<17>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<16>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<15>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<14>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<13>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<12>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<11>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<10>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<9>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<8>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<7>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<6>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<5>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<4>_UNCONNECTED ;
wire \NLW_blk0000014f_DOB<3>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<31>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<30>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<29>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<28>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<27>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<26>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<25>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<24>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<23>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<22>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<21>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<20>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<19>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<18>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<17>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<16>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<15>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<14>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<13>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<12>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<11>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<10>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<9>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<8>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<7>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<6>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<5>_UNCONNECTED ;
wire \NLW_blk0000014f_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000150_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000150_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000150_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000150_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000150_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000150_ADDRA<1>_UNCONNECTED ;
wire \NLW_blk00000150_ADDRA<0>_UNCONNECTED ;
wire \NLW_blk00000150_ADDRB<1>_UNCONNECTED ;
wire \NLW_blk00000150_ADDRB<0>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000150_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000150_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000150_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000150_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000150_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000150_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000150_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000150_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000150_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000150_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000150_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000150_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000150_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000150_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000150_DIA<4>_UNCONNECTED ;
wire NLW_blk00000151_Q15_UNCONNECTED;
wire NLW_blk00000153_Q15_UNCONNECTED;
wire NLW_blk00000155_Q15_UNCONNECTED;
wire NLW_blk00000157_Q15_UNCONNECTED;
wire NLW_blk00000159_Q15_UNCONNECTED;
wire NLW_blk0000015b_Q15_UNCONNECTED;
wire NLW_blk0000015d_Q15_UNCONNECTED;
wire NLW_blk0000015f_Q15_UNCONNECTED;
wire NLW_blk00000161_Q15_UNCONNECTED;
wire NLW_blk00000163_Q15_UNCONNECTED;
wire NLW_blk00000165_Q15_UNCONNECTED;
wire NLW_blk00000167_Q15_UNCONNECTED;
wire NLW_blk00000169_Q15_UNCONNECTED;
wire NLW_blk0000016b_Q15_UNCONNECTED;
wire NLW_blk0000016d_Q15_UNCONNECTED;
wire NLW_blk0000016f_Q15_UNCONNECTED;
wire NLW_blk00000171_Q15_UNCONNECTED;
wire NLW_blk00000173_Q15_UNCONNECTED;
wire NLW_blk00000175_Q15_UNCONNECTED;
wire NLW_blk00000177_Q15_UNCONNECTED;
wire NLW_blk00000179_Q15_UNCONNECTED;
wire NLW_blk0000017b_Q15_UNCONNECTED;
wire NLW_blk0000017d_Q15_UNCONNECTED;
wire NLW_blk0000017f_Q15_UNCONNECTED;
wire NLW_blk00000181_Q15_UNCONNECTED;
wire NLW_blk00000183_Q15_UNCONNECTED;
wire NLW_blk00000185_Q15_UNCONNECTED;
wire NLW_blk00000187_Q15_UNCONNECTED;
wire NLW_blk00000189_Q15_UNCONNECTED;
wire NLW_blk0000018b_Q15_UNCONNECTED;
wire NLW_blk0000018d_Q15_UNCONNECTED;
wire NLW_blk0000018f_Q15_UNCONNECTED;
wire [7 : 0] \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q ;
wire [7 : 0] \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q ;
assign
sine[15] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [7],
sine[14] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [6],
sine[13] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [5],
sine[12] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [4],
sine[11] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [3],
sine[10] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [2],
sine[9] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [1],
sine[8] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [0],
sine[7] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [7],
sine[6] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [6],
sine[5] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [5],
sine[4] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [4],
sine[3] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [3],
sine[2] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [2],
sine[1] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [1],
sine[0] = \U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [0];
VCC blk00000001 (
.P(sig00000001)
);
GND blk00000002 (
.G(sig00000002)
);
FD #(
.INIT ( 1'b0 ))
blk00000003 (
.C(clk),
.D(sig00000003),
.Q(sig00000046)
);
FD #(
.INIT ( 1'b0 ))
blk00000004 (
.C(clk),
.D(sig00000004),
.Q(sig00000045)
);
FD #(
.INIT ( 1'b0 ))
blk00000005 (
.C(clk),
.D(sig00000005),
.Q(sig00000044)
);
FD #(
.INIT ( 1'b0 ))
blk00000006 (
.C(clk),
.D(sig00000006),
.Q(sig00000043)
);
FD #(
.INIT ( 1'b0 ))
blk00000007 (
.C(clk),
.D(sig00000007),
.Q(sig00000042)
);
FD #(
.INIT ( 1'b0 ))
blk00000008 (
.C(clk),
.D(sig00000008),
.Q(sig00000041)
);
FD #(
.INIT ( 1'b0 ))
blk00000009 (
.C(clk),
.D(sig00000009),
.Q(sig00000040)
);
FD #(
.INIT ( 1'b0 ))
blk0000000a (
.C(clk),
.D(sig0000000a),
.Q(sig0000003f)
);
FD #(
.INIT ( 1'b0 ))
blk0000000b (
.C(clk),
.D(sig0000000b),
.Q(sig0000003e)
);
FD #(
.INIT ( 1'b0 ))
blk0000000c (
.C(clk),
.D(sig0000000c),
.Q(sig0000003d)
);
FD #(
.INIT ( 1'b0 ))
blk0000000d (
.C(clk),
.D(sig0000000d),
.Q(sig0000003c)
);
FD #(
.INIT ( 1'b0 ))
blk0000000e (
.C(clk),
.D(sig0000000e),
.Q(sig0000003b)
);
FD #(
.INIT ( 1'b0 ))
blk0000000f (
.C(clk),
.D(sig0000000f),
.Q(sig0000003a)
);
FD #(
.INIT ( 1'b0 ))
blk00000010 (
.C(clk),
.D(sig00000010),
.Q(sig00000039)
);
FD #(
.INIT ( 1'b0 ))
blk00000011 (
.C(clk),
.D(sig00000011),
.Q(sig00000038)
);
FD #(
.INIT ( 1'b0 ))
blk00000012 (
.C(clk),
.D(sig00000012),
.Q(sig00000037)
);
FD #(
.INIT ( 1'b0 ))
blk00000013 (
.C(clk),
.D(sig00000013),
.Q(sig00000036)
);
FD #(
.INIT ( 1'b0 ))
blk00000014 (
.C(clk),
.D(sig00000024),
.Q(sig00000049)
);
FD #(
.INIT ( 1'b0 ))
blk00000015 (
.C(clk),
.D(sig00000023),
.Q(sig00000032)
);
FD #(
.INIT ( 1'b0 ))
blk00000016 (
.C(clk),
.D(sig00000022),
.Q(sig00000031)
);
FD #(
.INIT ( 1'b0 ))
blk00000017 (
.C(clk),
.D(sig00000021),
.Q(sig00000030)
);
FD #(
.INIT ( 1'b0 ))
blk00000018 (
.C(clk),
.D(sig00000020),
.Q(sig0000002f)
);
FD #(
.INIT ( 1'b0 ))
blk00000019 (
.C(clk),
.D(sig0000001f),
.Q(sig0000002e)
);
FD #(
.INIT ( 1'b0 ))
blk0000001a (
.C(clk),
.D(sig0000001e),
.Q(sig0000002d)
);
FD #(
.INIT ( 1'b0 ))
blk0000001b (
.C(clk),
.D(sig0000001d),
.Q(sig0000002c)
);
FD #(
.INIT ( 1'b0 ))
blk0000001c (
.C(clk),
.D(sig0000001c),
.Q(sig0000002b)
);
FD #(
.INIT ( 1'b0 ))
blk0000001d (
.C(clk),
.D(sig0000001b),
.Q(sig0000002a)
);
FD #(
.INIT ( 1'b0 ))
blk0000001e (
.C(clk),
.D(sig0000001a),
.Q(sig00000029)
);
FD #(
.INIT ( 1'b0 ))
blk0000001f (
.C(clk),
.D(sig00000019),
.Q(sig00000028)
);
FD #(
.INIT ( 1'b0 ))
blk00000020 (
.C(clk),
.D(sig00000018),
.Q(sig00000027)
);
FD #(
.INIT ( 1'b0 ))
blk00000021 (
.C(clk),
.D(sig00000017),
.Q(sig00000026)
);
FD #(
.INIT ( 1'b0 ))
blk00000022 (
.C(clk),
.D(sig00000016),
.Q(sig00000025)
);
FD #(
.INIT ( 1'b0 ))
blk00000023 (
.C(clk),
.D(sig00000015),
.Q(sig00000048)
);
FD #(
.INIT ( 1'b0 ))
blk00000024 (
.C(clk),
.D(sig00000014),
.Q(sig00000047)
);
XORCY blk0000009c (
.CI(sig0000005d),
.LI(sig0000007d),
.O(sig00000075)
);
MUXCY blk0000009d (
.CI(sig0000005d),
.DI(sig00000002),
.S(sig0000007d),
.O(sig0000005c)
);
XORCY blk0000009e (
.CI(sig0000005e),
.LI(sig0000007c),
.O(sig00000074)
);
MUXCY blk0000009f (
.CI(sig0000005e),
.DI(sig00000002),
.S(sig0000007c),
.O(sig0000005d)
);
XORCY blk000000a0 (
.CI(sig0000005f),
.LI(sig0000007b),
.O(sig00000073)
);
MUXCY blk000000a1 (
.CI(sig0000005f),
.DI(sig00000002),
.S(sig0000007b),
.O(sig0000005e)
);
XORCY blk000000a2 (
.CI(sig00000060),
.LI(sig0000007a),
.O(sig00000072)
);
MUXCY blk000000a3 (
.CI(sig00000060),
.DI(sig00000002),
.S(sig0000007a),
.O(sig0000005f)
);
XORCY blk000000a4 (
.CI(sig00000061),
.LI(sig00000079),
.O(sig00000071)
);
MUXCY blk000000a5 (
.CI(sig00000061),
.DI(sig00000002),
.S(sig00000079),
.O(sig00000060)
);
XORCY blk000000a6 (
.CI(sig00000062),
.LI(sig00000078),
.O(sig00000070)
);
MUXCY blk000000a7 (
.CI(sig00000062),
.DI(sig00000002),
.S(sig00000078),
.O(sig00000061)
);
XORCY blk000000a8 (
.CI(sig00000063),
.LI(sig00000077),
.O(sig0000006f)
);
MUXCY blk000000a9 (
.CI(sig00000063),
.DI(sig00000002),
.S(sig00000077),
.O(sig00000062)
);
XORCY blk000000aa (
.CI(sig00000064),
.LI(sig00000076),
.O(sig0000006e)
);
MUXCY blk000000ab (
.CI(sig00000064),
.DI(sig00000002),
.S(sig00000076),
.O(sig00000063)
);
MUXCY blk000000ac (
.CI(sig00000002),
.DI(sig00000001),
.S(sig00000065),
.O(sig00000064)
);
XORCY blk000000ad (
.CI(sig00000067),
.LI(sig00000094),
.O(sig0000008d)
);
MUXCY blk000000ae (
.CI(sig00000067),
.DI(sig00000002),
.S(sig00000094),
.O(sig00000066)
);
XORCY blk000000af (
.CI(sig00000068),
.LI(sig00000093),
.O(sig0000008c)
);
MUXCY blk000000b0 (
.CI(sig00000068),
.DI(sig00000002),
.S(sig00000093),
.O(sig00000067)
);
XORCY blk000000b1 (
.CI(sig00000069),
.LI(sig00000092),
.O(sig0000008b)
);
MUXCY blk000000b2 (
.CI(sig00000069),
.DI(sig00000002),
.S(sig00000092),
.O(sig00000068)
);
XORCY blk000000b3 (
.CI(sig0000006a),
.LI(sig00000091),
.O(sig0000008a)
);
MUXCY blk000000b4 (
.CI(sig0000006a),
.DI(sig00000002),
.S(sig00000091),
.O(sig00000069)
);
XORCY blk000000b5 (
.CI(sig0000006b),
.LI(sig00000090),
.O(sig00000089)
);
MUXCY blk000000b6 (
.CI(sig0000006b),
.DI(sig00000002),
.S(sig00000090),
.O(sig0000006a)
);
XORCY blk000000b7 (
.CI(sig0000006c),
.LI(sig0000008f),
.O(sig00000088)
);
MUXCY blk000000b8 (
.CI(sig0000006c),
.DI(sig00000002),
.S(sig0000008f),
.O(sig0000006b)
);
XORCY blk000000b9 (
.CI(sig0000006d),
.LI(sig0000008e),
.O(sig00000087)
);
MUXCY blk000000ba (
.CI(sig0000006d),
.DI(sig00000002),
.S(sig0000008e),
.O(sig0000006c)
);
XORCY blk000000bb (
.CI(sig00000002),
.LI(sig00000127),
.O(sig00000086)
);
MUXCY blk000000bc (
.CI(sig00000002),
.DI(sig0000009c),
.S(sig00000127),
.O(sig0000006d)
);
FD #(
.INIT ( 1'b0 ))
blk000000bd (
.C(clk),
.D(sig000000b6),
.Q(sig000000c2)
);
FD #(
.INIT ( 1'b0 ))
blk000000be (
.C(clk),
.D(sig000000b5),
.Q(sig000000c1)
);
FD #(
.INIT ( 1'b0 ))
blk000000bf (
.C(clk),
.D(sig000000b4),
.Q(sig000000c0)
);
FD #(
.INIT ( 1'b0 ))
blk000000c0 (
.C(clk),
.D(sig000000b3),
.Q(sig000000bf)
);
FD #(
.INIT ( 1'b0 ))
blk000000c1 (
.C(clk),
.D(sig000000b2),
.Q(sig000000be)
);
FD #(
.INIT ( 1'b0 ))
blk000000c2 (
.C(clk),
.D(sig000000b1),
.Q(sig000000bd)
);
FD #(
.INIT ( 1'b0 ))
blk000000c3 (
.C(clk),
.D(sig000000b0),
.Q(sig000000bc)
);
FD #(
.INIT ( 1'b0 ))
blk000000c4 (
.C(clk),
.D(sig000000af),
.Q(sig000000bb)
);
FD #(
.INIT ( 1'b0 ))
blk000000c5 (
.C(clk),
.D(sig000000ae),
.Q(sig000000ba)
);
FD #(
.INIT ( 1'b0 ))
blk000000c6 (
.C(clk),
.D(sig000000ad),
.Q(sig000000b9)
);
FD #(
.INIT ( 1'b0 ))
blk000000c7 (
.C(clk),
.D(sig000000ac),
.Q(sig000000b8)
);
FD #(
.INIT ( 1'b0 ))
blk000000c8 (
.C(clk),
.D(sig000000ab),
.Q(sig000000b7)
);
FD #(
.INIT ( 1'b0 ))
blk000000c9 (
.C(clk),
.D(sig00000124),
.Q(sig0000009c)
);
FD #(
.INIT ( 1'b0 ))
blk000000ca (
.C(clk),
.D(sig00000032),
.Q(sig00000126)
);
FD #(
.INIT ( 1'b0 ))
blk000000cb (
.C(clk),
.D(sig00000031),
.Q(sig00000125)
);
FD #(
.INIT ( 1'b0 ))
blk000000cc (
.C(clk),
.D(sig000000f8),
.Q(sig000000e8)
);
FD #(
.INIT ( 1'b0 ))
blk000000cd (
.C(clk),
.D(sig000000f7),
.Q(sig000000e7)
);
FD #(
.INIT ( 1'b0 ))
blk000000ce (
.C(clk),
.D(sig000000f6),
.Q(sig000000e6)
);
FD #(
.INIT ( 1'b0 ))
blk000000cf (
.C(clk),
.D(sig000000f5),
.Q(sig000000e5)
);
FD #(
.INIT ( 1'b0 ))
blk000000d0 (
.C(clk),
.D(sig000000f4),
.Q(sig000000e4)
);
FD #(
.INIT ( 1'b0 ))
blk000000d1 (
.C(clk),
.D(sig000000f3),
.Q(sig000000e3)
);
FD #(
.INIT ( 1'b0 ))
blk000000d2 (
.C(clk),
.D(sig000000f2),
.Q(sig000000e2)
);
FD #(
.INIT ( 1'b0 ))
blk000000d3 (
.C(clk),
.D(sig000000f1),
.Q(sig000000e1)
);
FD #(
.INIT ( 1'b0 ))
blk000000d4 (
.C(clk),
.D(sig000000a3),
.Q(sig000000f0)
);
FD #(
.INIT ( 1'b0 ))
blk000000d5 (
.C(clk),
.D(sig000000a2),
.Q(sig000000ef)
);
FD #(
.INIT ( 1'b0 ))
blk000000d6 (
.C(clk),
.D(sig000000a1),
.Q(sig000000ee)
);
FD #(
.INIT ( 1'b0 ))
blk000000d7 (
.C(clk),
.D(sig000000a0),
.Q(sig000000ed)
);
FD #(
.INIT ( 1'b0 ))
blk000000d8 (
.C(clk),
.D(sig0000009f),
.Q(sig000000ec)
);
FD #(
.INIT ( 1'b0 ))
blk000000d9 (
.C(clk),
.D(sig0000009e),
.Q(sig000000eb)
);
FD #(
.INIT ( 1'b0 ))
blk000000da (
.C(clk),
.D(sig0000009d),
.Q(sig000000ea)
);
FD #(
.INIT ( 1'b0 ))
blk000000db (
.C(clk),
.D(sig00000053),
.Q(sig000000e9)
);
FD #(
.INIT ( 1'b0 ))
blk000000dc (
.C(clk),
.D(sig00000102),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [7])
);
FD #(
.INIT ( 1'b0 ))
blk000000dd (
.C(clk),
.D(sig00000101),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [6])
);
FD #(
.INIT ( 1'b0 ))
blk000000de (
.C(clk),
.D(sig00000100),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [5])
);
FD #(
.INIT ( 1'b0 ))
blk000000df (
.C(clk),
.D(sig000000ff),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [4])
);
FD #(
.INIT ( 1'b0 ))
blk000000e0 (
.C(clk),
.D(sig000000fe),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [3])
);
FD #(
.INIT ( 1'b0 ))
blk000000e1 (
.C(clk),
.D(sig000000fd),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [2])
);
FD #(
.INIT ( 1'b0 ))
blk000000e2 (
.C(clk),
.D(sig000000fc),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [1])
);
FD #(
.INIT ( 1'b0 ))
blk000000e3 (
.C(clk),
.D(sig000000fb),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q [0])
);
FD #(
.INIT ( 1'b0 ))
blk000000e4 (
.C(clk),
.D(sig000000aa),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [7])
);
FD #(
.INIT ( 1'b0 ))
blk000000e5 (
.C(clk),
.D(sig000000a9),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [6])
);
FD #(
.INIT ( 1'b0 ))
blk000000e6 (
.C(clk),
.D(sig000000a8),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [5])
);
FD #(
.INIT ( 1'b0 ))
blk000000e7 (
.C(clk),
.D(sig000000a7),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [4])
);
FD #(
.INIT ( 1'b0 ))
blk000000e8 (
.C(clk),
.D(sig000000a6),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [3])
);
FD #(
.INIT ( 1'b0 ))
blk000000e9 (
.C(clk),
.D(sig000000a5),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [2])
);
FD #(
.INIT ( 1'b0 ))
blk000000ea (
.C(clk),
.D(sig000000a4),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [1])
);
FD #(
.INIT ( 1'b0 ))
blk000000eb (
.C(clk),
.D(sig0000005b),
.Q(\U0/i_synth/I_SINCOS.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q [0])
);
FD #(
.INIT ( 1'b0 ))
blk000000ec (
.C(clk),
.D(sig00000085),
.Q(sig0000004c)
);
FD #(
.INIT ( 1'b0 ))
blk000000ed (
.C(clk),
.D(sig00000084),
.Q(sig0000004d)
);
FD #(
.INIT ( 1'b0 ))
blk000000ee (
.C(clk),
.D(sig00000083),
.Q(sig0000004e)
);
FD #(
.INIT ( 1'b0 ))
blk000000ef (
.C(clk),
.D(sig00000082),
.Q(sig0000004f)
);
FD #(
.INIT ( 1'b0 ))
blk000000f0 (
.C(clk),
.D(sig00000081),
.Q(sig00000050)
);
FD #(
.INIT ( 1'b0 ))
blk000000f1 (
.C(clk),
.D(sig00000080),
.Q(sig00000051)
);
FD #(
.INIT ( 1'b0 ))
blk000000f2 (
.C(clk),
.D(sig0000007f),
.Q(sig00000052)
);
FD #(
.INIT ( 1'b0 ))
blk000000f3 (
.C(clk),
.D(sig0000007e),
.Q(sig000000fa)
);
FD #(
.INIT ( 1'b0 ))
blk000000f4 (
.C(clk),
.D(sig0000009c),
.Q(sig00000054)
);
FD #(
.INIT ( 1'b0 ))
blk000000f5 (
.C(clk),
.D(sig0000009b),
.Q(sig00000055)
);
FD #(
.INIT ( 1'b0 ))
blk000000f6 (
.C(clk),
.D(sig0000009a),
.Q(sig00000056)
);
FD #(
.INIT ( 1'b0 ))
blk000000f7 (
.C(clk),
.D(sig00000099),
.Q(sig00000057)
);
FD #(
.INIT ( 1'b0 ))
blk000000f8 (
.C(clk),
.D(sig00000098),
.Q(sig00000058)
);
FD #(
.INIT ( 1'b0 ))
blk000000f9 (
.C(clk),
.D(sig00000097),
.Q(sig00000059)
);
FD #(
.INIT ( 1'b0 ))
blk000000fa (
.C(clk),
.D(sig00000096),
.Q(sig0000005a)
);
FD #(
.INIT ( 1'b0 ))
blk000000fb (
.C(clk),
.D(sig00000095),
.Q(sig00000104)
);
FD #(
.INIT ( 1'b0 ))
blk000000fc (
.C(clk),
.D(sig0000005c),
.Q(sig000000f9)
);
FD #(
.INIT ( 1'b0 ))
blk000000fd (
.C(clk),
.D(sig00000075),
.Q(sig000000f8)
);
FD #(
.INIT ( 1'b0 ))
blk000000fe (
.C(clk),
.D(sig00000074),
.Q(sig000000f7)
);
FD #(
.INIT ( 1'b0 ))
blk000000ff (
.C(clk),
.D(sig00000073),
.Q(sig000000f6)
);
FD #(
.INIT ( 1'b0 ))
blk00000100 (
.C(clk),
.D(sig00000072),
.Q(sig000000f5)
);
FD #(
.INIT ( 1'b0 ))
blk00000101 (
.C(clk),
.D(sig00000071),
.Q(sig000000f4)
);
FD #(
.INIT ( 1'b0 ))
blk00000102 (
.C(clk),
.D(sig00000070),
.Q(sig000000f3)
);
FD #(
.INIT ( 1'b0 ))
blk00000103 (
.C(clk),
.D(sig0000006f),
.Q(sig000000f2)
);
FD #(
.INIT ( 1'b0 ))
blk00000104 (
.C(clk),
.D(sig0000006e),
.Q(sig000000f1)
);
FD #(
.INIT ( 1'b0 ))
blk00000105 (
.C(clk),
.D(sig00000066),
.Q(sig00000103)
);
FD #(
.INIT ( 1'b0 ))
blk00000106 (
.C(clk),
.D(sig0000008d),
.Q(sig00000102)
);
FD #(
.INIT ( 1'b0 ))
blk00000107 (
.C(clk),
.D(sig0000008c),
.Q(sig00000101)
);
FD #(
.INIT ( 1'b0 ))
blk00000108 (
.C(clk),
.D(sig0000008b),
.Q(sig00000100)
);
FD #(
.INIT ( 1'b0 ))
blk00000109 (
.C(clk),
.D(sig0000008a),
.Q(sig000000ff)
);
FD #(
.INIT ( 1'b0 ))
blk0000010a (
.C(clk),
.D(sig00000089),
.Q(sig000000fe)
);
FD #(
.INIT ( 1'b0 ))
blk0000010b (
.C(clk),
.D(sig00000088),
.Q(sig000000fd)
);
FD #(
.INIT ( 1'b0 ))
blk0000010c (
.C(clk),
.D(sig00000087),
.Q(sig000000fc)
);
FD #(
.INIT ( 1'b0 ))
blk0000010d (
.C(clk),
.D(sig00000086),
.Q(sig000000fb)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000010e (
.I0(sig00000056),
.I1(sig0000004a),
.O(sig000000a8)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000010f (
.I0(sig0000004e),
.I1(sig0000004b),
.O(sig000000a1)
);
LUT3 #(
.INIT ( 8'hA6 ))
blk00000110 (
.I0(sig00000055),
.I1(sig00000056),
.I2(sig0000004a),
.O(sig000000a9)
);
LUT3 #(
.INIT ( 8'hA6 ))
blk00000111 (
.I0(sig0000004d),
.I1(sig0000004e),
.I2(sig0000004b),
.O(sig000000a2)
);
LUT4 #(
.INIT ( 16'hAA6A ))
blk00000112 (
.I0(sig00000054),
.I1(sig00000055),
.I2(sig00000056),
.I3(sig0000004a),
.O(sig000000aa)
);
LUT4 #(
.INIT ( 16'hAA6A ))
blk00000113 (
.I0(sig0000004c),
.I1(sig0000004d),
.I2(sig0000004e),
.I3(sig0000004b),
.O(sig000000a3)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000114 (
.I0(sig00000115),
.I1(sig00000128),
.O(sig0000008e)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000115 (
.I0(sig00000116),
.I1(sig00000128),
.O(sig0000008f)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000116 (
.I0(sig00000117),
.I1(sig00000128),
.O(sig00000090)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000117 (
.I0(sig00000118),
.I1(sig00000128),
.O(sig00000091)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000118 (
.I0(sig00000119),
.I1(sig00000128),
.O(sig00000092)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000119 (
.I0(sig0000011a),
.I1(sig0000009c),
.O(sig00000093)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011a (
.I0(sig0000011b),
.I1(sig0000009c),
.O(sig00000094)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011b (
.I0(sig0000011c),
.I1(sig0000009c),
.O(sig00000095)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011c (
.I0(sig0000011d),
.I1(sig0000009c),
.O(sig00000096)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011d (
.I0(sig0000011e),
.I1(sig0000009c),
.O(sig00000097)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011e (
.I0(sig0000011f),
.I1(sig0000009c),
.O(sig00000098)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000011f (
.I0(sig00000120),
.I1(sig0000009c),
.O(sig00000099)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000120 (
.I0(sig00000121),
.I1(sig0000009c),
.O(sig0000009a)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000121 (
.I0(sig00000122),
.I1(sig0000009c),
.O(sig0000009b)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000122 (
.I0(sig00000025),
.I1(sig00000031),
.O(sig000000ab)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000123 (
.I0(sig0000002f),
.I1(sig00000031),
.O(sig000000b5)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000124 (
.I0(sig00000030),
.I1(sig00000031),
.O(sig000000b6)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000125 (
.I0(sig00000026),
.I1(sig00000031),
.O(sig000000ac)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000126 (
.I0(sig00000027),
.I1(sig00000031),
.O(sig000000ad)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000127 (
.I0(sig00000028),
.I1(sig00000031),
.O(sig000000ae)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000128 (
.I0(sig00000029),
.I1(sig00000031),
.O(sig000000af)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000129 (
.I0(sig0000002a),
.I1(sig00000031),
.O(sig000000b0)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012a (
.I0(sig0000002b),
.I1(sig00000031),
.O(sig000000b1)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012b (
.I0(sig0000002c),
.I1(sig00000031),
.O(sig000000b2)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012c (
.I0(sig0000002d),
.I1(sig00000031),
.O(sig000000b3)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012d (
.I0(sig0000002e),
.I1(sig00000031),
.O(sig000000b4)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012e (
.I0(sig00000123),
.I1(sig0000009c),
.O(sig00000085)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000012f (
.I0(sig000000fa),
.I1(sig000000f9),
.O(sig00000053)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000130 (
.I0(sig00000104),
.I1(sig00000103),
.O(sig0000005b)
);
LUT6 #(
.INIT ( 64'h7FFFFFFFFFFFFFFF ))
blk00000131 (
.I0(sig00000057),
.I1(sig00000058),
.I2(sig00000059),
.I3(sig0000005a),
.I4(sig00000103),
.I5(sig00000104),
.O(sig0000004a)
);
LUT6 #(
.INIT ( 64'h7FFFFFFFFFFFFFFF ))
blk00000132 (
.I0(sig0000004f),
.I1(sig00000050),
.I2(sig00000051),
.I3(sig00000052),
.I4(sig000000f9),
.I5(sig000000fa),
.O(sig0000004b)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000133 (
.I0(sig00000128),
.I1(sig00000123),
.O(sig00000065)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000134 (
.I0(sig00000105),
.I1(sig00000128),
.I2(sig00000123),
.O(sig00000076)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000135 (
.I0(sig00000106),
.I1(sig00000128),
.I2(sig00000123),
.O(sig00000077)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000136 (
.I0(sig00000107),
.I1(sig00000128),
.I2(sig00000123),
.O(sig00000078)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000137 (
.I0(sig00000108),
.I1(sig00000128),
.I2(sig00000123),
.O(sig00000079)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000138 (
.I0(sig00000109),
.I1(sig00000128),
.I2(sig00000123),
.O(sig0000007a)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000139 (
.I0(sig0000010a),
.I1(sig00000128),
.I2(sig00000123),
.O(sig0000007b)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000013a (
.I0(sig0000010b),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig0000007c)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000013b (
.I0(sig0000010c),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig0000007d)
);
LUT5 #(
.INIT ( 32'h6AAAAAAA ))
blk0000013c (
.I0(sig00000058),
.I1(sig00000104),
.I2(sig00000103),
.I3(sig0000005a),
.I4(sig00000059),
.O(sig000000a6)
);
LUT6 #(
.INIT ( 64'h6AAAAAAAAAAAAAAA ))
blk0000013d (
.I0(sig00000057),
.I1(sig00000104),
.I2(sig00000103),
.I3(sig0000005a),
.I4(sig00000059),
.I5(sig00000058),
.O(sig000000a7)
);
LUT4 #(
.INIT ( 16'h6AAA ))
blk0000013e (
.I0(sig00000059),
.I1(sig00000104),
.I2(sig00000103),
.I3(sig0000005a),
.O(sig000000a5)
);
LUT5 #(
.INIT ( 32'h6AAAAAAA ))
blk0000013f (
.I0(sig00000050),
.I1(sig000000fa),
.I2(sig000000f9),
.I3(sig00000052),
.I4(sig00000051),
.O(sig0000009f)
);
LUT6 #(
.INIT ( 64'h6AAAAAAAAAAAAAAA ))
blk00000140 (
.I0(sig0000004f),
.I1(sig000000fa),
.I2(sig000000f9),
.I3(sig00000052),
.I4(sig00000051),
.I5(sig00000050),
.O(sig000000a0)
);
LUT4 #(
.INIT ( 16'h6AAA ))
blk00000141 (
.I0(sig00000051),
.I1(sig000000fa),
.I2(sig000000f9),
.I3(sig00000052),
.O(sig0000009e)
);
LUT3 #(
.INIT ( 8'h6A ))
blk00000142 (
.I0(sig00000052),
.I1(sig000000fa),
.I2(sig000000f9),
.O(sig0000009d)
);
LUT3 #(
.INIT ( 8'h6A ))
blk00000143 (
.I0(sig0000005a),
.I1(sig00000104),
.I2(sig00000103),
.O(sig000000a4)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000144 (
.I0(sig0000010d),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig0000007e)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000145 (
.I0(sig0000010e),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig0000007f)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000146 (
.I0(sig0000010f),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000080)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000147 (
.I0(sig00000110),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000081)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000148 (
.I0(sig00000111),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000082)
);
LUT3 #(
.INIT ( 8'h96 ))
blk00000149 (
.I0(sig00000112),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000083)
);
LUT3 #(
.INIT ( 8'h96 ))
blk0000014a (
.I0(sig00000113),
.I1(sig00000123),
.I2(sig0000009c),
.O(sig00000084)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000014b (
.I0(sig00000114),
.O(sig00000127)
);
FD #(
.INIT ( 1'b0 ))
blk0000014c (
.C(clk),
.D(sig00000124),
.Q(sig00000128)
);
RAMB16BWER #(
.INIT_00 ( 256'h3332222222222222222222211111111111111111111100000000000000000000 ),
.INIT_01 ( 256'h6666665555555555555555555544444444444444444444433333333333333333 ),
.INIT_02 ( 256'h9999999998888888888888888888877777777777777777777666666666666666 ),
.INIT_03 ( 256'hCCCCCCCCCCCBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAA999999999999 ),
.INIT_04 ( 256'hFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDCCCCCCCCC ),
.INIT_05 ( 256'h222222222222222211111111111111111111100000000000000000000FFFFFFF ),
.INIT_06 ( 256'h5555555555555555554444444444444444444443333333333333333333332222 ),
.INIT_07 ( 256'h8888888888888888888877777777777777777777766666666666666666666655 ),
.INIT_08 ( 256'hCBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAA999999999999999999998 ),
.INIT_09 ( 256'hFFEEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCCCCCCC ),
.INIT_0A ( 256'h222111111111111111111111000000000000000000000FFFFFFFFFFFFFFFFFFF ),
.INIT_0B ( 256'h5554444444444444444444444333333333333333333333222222222222222222 ),
.INIT_0C ( 256'h8887777777777777777777777666666666666666666666555555555555555555 ),
.INIT_0D ( 256'hBBBAAAAAAAAAAAAAAAAAAAAA9999999999999999999999888888888888888888 ),
.INIT_0E ( 256'hEDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCCCCCCCCCBBBBBBBBBBBBBBBBBBB ),
.INIT_0F ( 256'h0000000000000000000000FFFFFFFFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEEEEE ),
.INIT_10 ( 256'h3333333333333333333222222222222222222222221111111111111111111111 ),
.INIT_11 ( 256'h6666666666666666555555555555555555555554444444444444444444444333 ),
.INIT_12 ( 256'h9999999999998888888888888888888888877777777777777777777777666666 ),
.INIT_13 ( 256'hCCCCCCCCBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAAAA9999999999 ),
.INIT_14 ( 256'hFFEEEEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCC ),
.INIT_15 ( 256'h1111111111111111111000000000000000000000000FFFFFFFFFFFFFFFFFFFFF ),
.INIT_16 ( 256'h4444444444433333333333333333333333322222222222222222222222211111 ),
.INIT_17 ( 256'h7776666666666666666666666665555555555555555555555554444444444444 ),
.INIT_18 ( 256'h9999999999999999988888888888888888888888887777777777777777777777 ),
.INIT_19 ( 256'hCCCCCCBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAAAAAAA9999999 ),
.INIT_1A ( 256'hEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCCCCCC ),
.INIT_1B ( 256'h1111100000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFEEEEEEE ),
.INIT_1C ( 256'h3333333333333333222222222222222222222222222111111111111111111111 ),
.INIT_1D ( 256'h5555555555555555555555555544444444444444444444444444433333333333 ),
.INIT_1E ( 256'h8888888777777777777777777777777777766666666666666666666666666665 ),
.INIT_1F ( 256'hAAAAAAAAAAAAAAA9999999999999999999999999999888888888888888888888 ),
.INIT_20 ( 256'hCCCCCCCCCCCCCCCCCCCCCBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAA ),
.INIT_21 ( 256'hEEEEEEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCC ),
.INIT_22 ( 256'h0000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEEEEE ),
.INIT_23 ( 256'h2222222222222222222222222222221111111111111111111111111111111000 ),
.INIT_24 ( 256'h4444444444444444444444444444443333333333333333333333333333333322 ),
.INIT_25 ( 256'h6666666666666666666666666665555555555555555555555555555555555444 ),
.INIT_26 ( 256'h8888888888888888888888877777777777777777777777777777777776666666 ),
.INIT_27 ( 256'hAAAAAAAAAAAAAAA9999999999999999999999999999999999998888888888888 ),
.INIT_28 ( 256'hCCCCCBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAA ),
.INIT_29 ( 256'hDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC ),
.INIT_2A ( 256'hFFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEDDDDDDDDD ),
.INIT_2B ( 256'h00000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2C ( 256'h2222222222222221111111111111111111111111111111111111111111100000 ),
.INIT_2D ( 256'h3333333333333333333333333333333332222222222222222222222222222222 ),
.INIT_2E ( 256'h5444444444444444444444444444444444444444444444444433333333333333 ),
.INIT_2F ( 256'h6666666666666555555555555555555555555555555555555555555555555555 ),
.INIT_30 ( 256'h7777777777777777777777766666666666666666666666666666666666666666 ),
.INIT_31 ( 256'h8888888888888888888888888888887777777777777777777777777777777777 ),
.INIT_32 ( 256'h9999999999999999999999999999999999888888888888888888888888888888 ),
.INIT_33 ( 256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA9999999999999999999999999999999 ),
.INIT_34 ( 256'hBBBBBBBBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ),
.INIT_35 ( 256'hCCCCCCCCCCCCCBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB ),
.INIT_36 ( 256'hCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC ),
.INIT_37 ( 256'hDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDCCCCCCCCCCC ),
.INIT_38 ( 256'hEEEEEEEEEEEEEDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD ),
.INIT_39 ( 256'hEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE ),
.INIT_3A ( 256'hFFFFFEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE ),
.INIT_3B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 4 ),
.DATA_WIDTH_B ( 4 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
blk0000014d (
.REGCEA(sig00000002),
.CLKA(clk),
.ENB(sig00000001),
.RSTB(sig00000002),
.CLKB(clk),
.REGCEB(sig00000002),
.RSTA(sig00000002),
.ENA(sig00000001),
.DIPA({\NLW_blk0000014d_DIPA<3>_UNCONNECTED , \NLW_blk0000014d_DIPA<2>_UNCONNECTED , \NLW_blk0000014d_DIPA<1>_UNCONNECTED ,
\NLW_blk0000014d_DIPA<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.DOA({\NLW_blk0000014d_DOA<31>_UNCONNECTED , \NLW_blk0000014d_DOA<30>_UNCONNECTED , \NLW_blk0000014d_DOA<29>_UNCONNECTED ,
\NLW_blk0000014d_DOA<28>_UNCONNECTED , \NLW_blk0000014d_DOA<27>_UNCONNECTED , \NLW_blk0000014d_DOA<26>_UNCONNECTED ,
\NLW_blk0000014d_DOA<25>_UNCONNECTED , \NLW_blk0000014d_DOA<24>_UNCONNECTED , \NLW_blk0000014d_DOA<23>_UNCONNECTED ,
\NLW_blk0000014d_DOA<22>_UNCONNECTED , \NLW_blk0000014d_DOA<21>_UNCONNECTED , \NLW_blk0000014d_DOA<20>_UNCONNECTED ,
\NLW_blk0000014d_DOA<19>_UNCONNECTED , \NLW_blk0000014d_DOA<18>_UNCONNECTED , \NLW_blk0000014d_DOA<17>_UNCONNECTED ,
\NLW_blk0000014d_DOA<16>_UNCONNECTED , \NLW_blk0000014d_DOA<15>_UNCONNECTED , \NLW_blk0000014d_DOA<14>_UNCONNECTED ,
\NLW_blk0000014d_DOA<13>_UNCONNECTED , \NLW_blk0000014d_DOA<12>_UNCONNECTED , \NLW_blk0000014d_DOA<11>_UNCONNECTED ,
\NLW_blk0000014d_DOA<10>_UNCONNECTED , \NLW_blk0000014d_DOA<9>_UNCONNECTED , \NLW_blk0000014d_DOA<8>_UNCONNECTED ,
\NLW_blk0000014d_DOA<7>_UNCONNECTED , \NLW_blk0000014d_DOA<6>_UNCONNECTED , \NLW_blk0000014d_DOA<5>_UNCONNECTED , \NLW_blk0000014d_DOA<4>_UNCONNECTED
, sig000000dd, sig000000dc, sig000000db, sig000000da}),
.ADDRA({sig000000c2, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000bb, sig000000ba, sig000000b9,
sig000000b8, sig000000b7, \NLW_blk0000014d_ADDRA<1>_UNCONNECTED , \NLW_blk0000014d_ADDRA<0>_UNCONNECTED }),
.ADDRB({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, \NLW_blk0000014d_ADDRB<1>_UNCONNECTED , \NLW_blk0000014d_ADDRB<0>_UNCONNECTED }),
.DIB({\NLW_blk0000014d_DIB<31>_UNCONNECTED , \NLW_blk0000014d_DIB<30>_UNCONNECTED , \NLW_blk0000014d_DIB<29>_UNCONNECTED ,
\NLW_blk0000014d_DIB<28>_UNCONNECTED , \NLW_blk0000014d_DIB<27>_UNCONNECTED , \NLW_blk0000014d_DIB<26>_UNCONNECTED ,
\NLW_blk0000014d_DIB<25>_UNCONNECTED , \NLW_blk0000014d_DIB<24>_UNCONNECTED , \NLW_blk0000014d_DIB<23>_UNCONNECTED ,
\NLW_blk0000014d_DIB<22>_UNCONNECTED , \NLW_blk0000014d_DIB<21>_UNCONNECTED , \NLW_blk0000014d_DIB<20>_UNCONNECTED ,
\NLW_blk0000014d_DIB<19>_UNCONNECTED , \NLW_blk0000014d_DIB<18>_UNCONNECTED , \NLW_blk0000014d_DIB<17>_UNCONNECTED ,
\NLW_blk0000014d_DIB<16>_UNCONNECTED , \NLW_blk0000014d_DIB<15>_UNCONNECTED , \NLW_blk0000014d_DIB<14>_UNCONNECTED ,
\NLW_blk0000014d_DIB<13>_UNCONNECTED , \NLW_blk0000014d_DIB<12>_UNCONNECTED , \NLW_blk0000014d_DIB<11>_UNCONNECTED ,
\NLW_blk0000014d_DIB<10>_UNCONNECTED , \NLW_blk0000014d_DIB<9>_UNCONNECTED , \NLW_blk0000014d_DIB<8>_UNCONNECTED ,
\NLW_blk0000014d_DIB<7>_UNCONNECTED , \NLW_blk0000014d_DIB<6>_UNCONNECTED , \NLW_blk0000014d_DIB<5>_UNCONNECTED , \NLW_blk0000014d_DIB<4>_UNCONNECTED
, \NLW_blk0000014d_DIB<3>_UNCONNECTED , \NLW_blk0000014d_DIB<2>_UNCONNECTED , \NLW_blk0000014d_DIB<1>_UNCONNECTED ,
\NLW_blk0000014d_DIB<0>_UNCONNECTED }),
.DOPA({\NLW_blk0000014d_DOPA<3>_UNCONNECTED , \NLW_blk0000014d_DOPA<2>_UNCONNECTED , \NLW_blk0000014d_DOPA<1>_UNCONNECTED ,
\NLW_blk0000014d_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk0000014d_DIPB<3>_UNCONNECTED , \NLW_blk0000014d_DIPB<2>_UNCONNECTED , \NLW_blk0000014d_DIPB<1>_UNCONNECTED ,
\NLW_blk0000014d_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk0000014d_DOPB<3>_UNCONNECTED , \NLW_blk0000014d_DOPB<2>_UNCONNECTED , \NLW_blk0000014d_DOPB<1>_UNCONNECTED ,
\NLW_blk0000014d_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk0000014d_DOB<31>_UNCONNECTED , \NLW_blk0000014d_DOB<30>_UNCONNECTED , \NLW_blk0000014d_DOB<29>_UNCONNECTED ,
\NLW_blk0000014d_DOB<28>_UNCONNECTED , \NLW_blk0000014d_DOB<27>_UNCONNECTED , \NLW_blk0000014d_DOB<26>_UNCONNECTED ,
\NLW_blk0000014d_DOB<25>_UNCONNECTED , \NLW_blk0000014d_DOB<24>_UNCONNECTED , \NLW_blk0000014d_DOB<23>_UNCONNECTED ,
\NLW_blk0000014d_DOB<22>_UNCONNECTED , \NLW_blk0000014d_DOB<21>_UNCONNECTED , \NLW_blk0000014d_DOB<20>_UNCONNECTED ,
\NLW_blk0000014d_DOB<19>_UNCONNECTED , \NLW_blk0000014d_DOB<18>_UNCONNECTED , \NLW_blk0000014d_DOB<17>_UNCONNECTED ,
\NLW_blk0000014d_DOB<16>_UNCONNECTED , \NLW_blk0000014d_DOB<15>_UNCONNECTED , \NLW_blk0000014d_DOB<14>_UNCONNECTED ,
\NLW_blk0000014d_DOB<13>_UNCONNECTED , \NLW_blk0000014d_DOB<12>_UNCONNECTED , \NLW_blk0000014d_DOB<11>_UNCONNECTED ,
\NLW_blk0000014d_DOB<10>_UNCONNECTED , \NLW_blk0000014d_DOB<9>_UNCONNECTED , \NLW_blk0000014d_DOB<8>_UNCONNECTED ,
\NLW_blk0000014d_DOB<7>_UNCONNECTED , \NLW_blk0000014d_DOB<6>_UNCONNECTED , \NLW_blk0000014d_DOB<5>_UNCONNECTED , \NLW_blk0000014d_DOB<4>_UNCONNECTED
, sig000000ce, sig000000cd, sig000000cc, sig000000cb}),
.WEB({sig00000002, sig00000002, sig00000002, sig00000002}),
.DIA({\NLW_blk0000014d_DIA<31>_UNCONNECTED , \NLW_blk0000014d_DIA<30>_UNCONNECTED , \NLW_blk0000014d_DIA<29>_UNCONNECTED ,
\NLW_blk0000014d_DIA<28>_UNCONNECTED , \NLW_blk0000014d_DIA<27>_UNCONNECTED , \NLW_blk0000014d_DIA<26>_UNCONNECTED ,
\NLW_blk0000014d_DIA<25>_UNCONNECTED , \NLW_blk0000014d_DIA<24>_UNCONNECTED , \NLW_blk0000014d_DIA<23>_UNCONNECTED ,
\NLW_blk0000014d_DIA<22>_UNCONNECTED , \NLW_blk0000014d_DIA<21>_UNCONNECTED , \NLW_blk0000014d_DIA<20>_UNCONNECTED ,
\NLW_blk0000014d_DIA<19>_UNCONNECTED , \NLW_blk0000014d_DIA<18>_UNCONNECTED , \NLW_blk0000014d_DIA<17>_UNCONNECTED ,
\NLW_blk0000014d_DIA<16>_UNCONNECTED , \NLW_blk0000014d_DIA<15>_UNCONNECTED , \NLW_blk0000014d_DIA<14>_UNCONNECTED ,
\NLW_blk0000014d_DIA<13>_UNCONNECTED , \NLW_blk0000014d_DIA<12>_UNCONNECTED , \NLW_blk0000014d_DIA<11>_UNCONNECTED ,
\NLW_blk0000014d_DIA<10>_UNCONNECTED , \NLW_blk0000014d_DIA<9>_UNCONNECTED , \NLW_blk0000014d_DIA<8>_UNCONNECTED ,
\NLW_blk0000014d_DIA<7>_UNCONNECTED , \NLW_blk0000014d_DIA<6>_UNCONNECTED , \NLW_blk0000014d_DIA<5>_UNCONNECTED , \NLW_blk0000014d_DIA<4>_UNCONNECTED
, sig00000002, sig00000002, sig00000002, sig00000002})
);
RAMB16BWER #(
.INIT_00 ( 256'h110FEDDCBAA987665432210FFEDCBBA9877654432100FEDCCBA9987655432110 ),
.INIT_01 ( 256'h432100FEDDCBA9987665432210FEEDCBBA9877654332100FEDCCBA9887655432 ),
.INIT_02 ( 256'h654332100FEDCCBA9887655432110FEEDCBAA987665433210FFEDCBBA9887654 ),
.INIT_03 ( 256'h87665432210FEEDCBBA9877654432100FEDCCBA9987655432210FEEDCBAA9877 ),
.INIT_04 ( 256'hA9877654432100FEDDCBA9987665432210FFEDCBBA9877654432100FEDDCBA99 ),
.INIT_05 ( 256'hCBA9987655432210FEEDCBBA9877654432100FEDDCBA9987665432210FEEDCBB ),
.INIT_06 ( 256'hDCCBA9987665432210FFEDCBBA9887654432110FEDDCBAA9877654332100FEDC ),
.INIT_07 ( 256'hFEDCCBA9987655432210FEEDCBBA9887654432110FEDDCBAA9877654332100FE ),
.INIT_08 ( 256'h0FEEDCBAA9877654432110FEDDCBAA9877654332100FEDDCBA9987665433210F ),
.INIT_09 ( 256'h10FEEDCBBA9887655432110FEEDCBBA9887655432110FEEDCBBA987765443211 ),
.INIT_0A ( 256'h110FEEDCBBA9887654432110FEEDCBBA9887655432110FEEDCBBA98876554322 ),
.INIT_0B ( 256'h210FFEDCCBA99876654332100FEDDCBAA9877654332100FEDDCBAA9877654432 ),
.INIT_0C ( 256'h210FFEDCCBA99876654332100FEDDCBAA9877654432110FEEDCBBA9887655432 ),
.INIT_0D ( 256'h100FEDDCBAA9877654432210FFEDCCBA99876654332100FEDDCBAA9887655432 ),
.INIT_0E ( 256'h0FFEDDCBAA9877654432210FFEDCCBA99876654432110FEEDCBBA98876654332 ),
.INIT_0F ( 256'hFEDDCBBA98876554332100FEDDCBAA98876554322100FEDDCBAA988765543221 ),
.INIT_10 ( 256'hDCCBA99877654432210FFEDDCBAA98776554322100FEDDCBAA98876554322100 ),
.INIT_11 ( 256'hBA99876654432210FFEDDCBAA98876554332100FEEDCBBA99876654432110FEE ),
.INIT_12 ( 256'h877654432210FFEDDCBBA98876654432110FFEDCCBAA98876554332100FEEDCB ),
.INIT_13 ( 256'h54322100FEEDCCBA998776554322100FEEDCCBA998776554322100FEEDCBBA99 ),
.INIT_14 ( 256'h10FFEDCCBAA98876654432210FFEDDCBBA998776544322100FEEDCBBA9987765 ),
.INIT_15 ( 256'hCBBA998776554332110FFEDCCBAA988766544322100FEEDCBBA9987765543321 ),
.INIT_16 ( 256'h76554332110FFEEDCCBAA98876654332110FFEDDCBBA998776554332110FFEDD ),
.INIT_17 ( 256'h100FEEDCCBAA988766554332110FFEDDCBBA998776554332110FFEDDCBBA9987 ),
.INIT_18 ( 256'hAA988776554332110FFEEDCCBAA988766544332110FFEDDCBBA9987766544322 ),
.INIT_19 ( 256'h332110FFEDDCCBAA988766554332110FFEEDCCBAA9887765543321100FEEDCCB ),
.INIT_1A ( 256'hBBA9987766544322110FFEDDCCBAA9887765543322100FEEDDCBBA9988766544 ),
.INIT_1B ( 256'h22110FFEEDCCBAA9987766544332110FFEEDCCBBA9987766544332110FFEEDCC ),
.INIT_1C ( 256'h9887665543322110FFEEDCCBBA99887665543322100FEEDDCBBAA98877655443 ),
.INIT_1D ( 256'hFEDDCCBAA99887665543322100FFEEDCCBBA99887665544322110FFEEDCCBBA9 ),
.INIT_1E ( 256'h3322100FFEEDCCBBAA98877665443322100FFEEDCCBBAA98877655443321100F ),
.INIT_1F ( 256'h776655433221100FEEDDCCBAA998877655443321100FFEEDCCBBAA9887766544 ),
.INIT_20 ( 256'hAA9988776654433221100FEEDDCCBBAA988776655433221100FFEDDCCBBAA988 ),
.INIT_21 ( 256'hDCCBBA9988776655443322100FFEEDDCCBBAA988776655443321100FFEEDDCCB ),
.INIT_22 ( 256'hEDDCCBBAA9988776655443322110FFEEDDCCBBAA9988776655433221100FFEED ),
.INIT_23 ( 256'hEEDDCCBBAA99887766554433221100FFEEDDCCBBAA9988776655443322110FFE ),
.INIT_24 ( 256'hEDDCCBBAA998877665544433221100FFEEDDCCBBAA99887766554433221100FF ),
.INIT_25 ( 256'hCCBBAA998877766554433221100FFEEEDDCCBBAA998877665544433221100FFE ),
.INIT_26 ( 256'hA9988776665544332211100FFEEDDCCBBBAA998877665554433221100FFFEEDD ),
.INIT_27 ( 256'h665544333221100FFFEEDDCCCBBAA9988877665544433221100FFFEEDDCCBBBA ),
.INIT_28 ( 256'h11100FFFEEDDCCCBBAA999887766655443332211000FFEEDDDCCBBAAA9988776 ),
.INIT_29 ( 256'hCBBBAA9998877766555443322211000FFEEEDDCCBBBAA9998877766554443322 ),
.INIT_2A ( 256'h554443322211100FFFEEDDDCCBBBAA9998877766555443332211100FFFEEDDDC ),
.INIT_2B ( 256'hDDDCCCBBAAA999887776665544433322111000FFEEEDDCCCBBBAA99988777666 ),
.INIT_2C ( 256'h544433222111000FFFEEDDDCCCBBBAA9998887776655544433322111000FFFEE ),
.INIT_2D ( 256'hBAAA99988877766655544433222111000FFFEEEDDDCCCBBBAA99988877766655 ),
.INIT_2E ( 256'h0FFFEEEDDDCCCBBBAAA9998888777666555444333222111000FFFEEEDDDCCCBB ),
.INIT_2F ( 256'h3332222111000FFFFEEEDDDCCCBBBBAAA9998887776666555444333222111100 ),
.INIT_30 ( 256'h66555544433332221111000FFFFEEEDDDDCCCBBBBAAA99988887776665555444 ),
.INIT_31 ( 256'h877776665555444433322221111000FFFFEEEEDDDCCCCBBBBAAA999988877776 ),
.INIT_32 ( 256'h8877776666555544443333222211110000FFFFEEEEDDDDCCCCBBBAAAA9999888 ),
.INIT_33 ( 256'h777666665555444433332222211110000FFFFEEEEEDDDDCCCCBBBBAAAA999988 ),
.INIT_34 ( 256'h555444443333322222111100000FFFFEEEEEDDDDDCCCCBBBBBAAAA9999888887 ),
.INIT_35 ( 256'h2221111100000FFFFFEEEEEDDDDDCCCCCBBBBBAAAAA999998888877777666665 ),
.INIT_36 ( 256'hEDDDDDDCCCCCBBBBBBAAAAAA9999988888877777666666555554444433333322 ),
.INIT_37 ( 256'h88887777776666665555555444444333333222222111111000000FFFFFFEEEEE ),
.INIT_38 ( 256'h1111110000000FFFFFFFEEEEEEEDDDDDDDCCCCCCCBBBBBBBAAAAAA9999999888 ),
.INIT_39 ( 256'h9999998888888887777777766666666555555554444444433333333222222211 ),
.INIT_3A ( 256'h00000FFFFFFFFFFEEEEEEEEEEDDDDDDDDDDCCCCCCCCCBBBBBBBBBAAAAAAAAA99 ),
.INIT_3B ( 256'h6555555555555444444444444333333333333222222222221111111111100000 ),
.INIT_3C ( 256'hAAAAAA9999999999999999888888888888888777777777777776666666666666 ),
.INIT_3D ( 256'hDDDDDDDDDDDCCCCCCCCCCCCCCCCCCCCCCBBBBBBBBBBBBBBBBBBBBAAAAAAAAAAA ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEDDDDDDDDDDDDDDD ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 4 ),
.DATA_WIDTH_B ( 4 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
blk0000014e (
.REGCEA(sig00000002),
.CLKA(clk),
.ENB(sig00000001),
.RSTB(sig00000002),
.CLKB(clk),
.REGCEB(sig00000002),
.RSTA(sig00000002),
.ENA(sig00000001),
.DIPA({\NLW_blk0000014e_DIPA<3>_UNCONNECTED , \NLW_blk0000014e_DIPA<2>_UNCONNECTED , \NLW_blk0000014e_DIPA<1>_UNCONNECTED ,
\NLW_blk0000014e_DIPA<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.DOA({\NLW_blk0000014e_DOA<31>_UNCONNECTED , \NLW_blk0000014e_DOA<30>_UNCONNECTED , \NLW_blk0000014e_DOA<29>_UNCONNECTED ,
\NLW_blk0000014e_DOA<28>_UNCONNECTED , \NLW_blk0000014e_DOA<27>_UNCONNECTED , \NLW_blk0000014e_DOA<26>_UNCONNECTED ,
\NLW_blk0000014e_DOA<25>_UNCONNECTED , \NLW_blk0000014e_DOA<24>_UNCONNECTED , \NLW_blk0000014e_DOA<23>_UNCONNECTED ,
\NLW_blk0000014e_DOA<22>_UNCONNECTED , \NLW_blk0000014e_DOA<21>_UNCONNECTED , \NLW_blk0000014e_DOA<20>_UNCONNECTED ,
\NLW_blk0000014e_DOA<19>_UNCONNECTED , \NLW_blk0000014e_DOA<18>_UNCONNECTED , \NLW_blk0000014e_DOA<17>_UNCONNECTED ,
\NLW_blk0000014e_DOA<16>_UNCONNECTED , \NLW_blk0000014e_DOA<15>_UNCONNECTED , \NLW_blk0000014e_DOA<14>_UNCONNECTED ,
\NLW_blk0000014e_DOA<13>_UNCONNECTED , \NLW_blk0000014e_DOA<12>_UNCONNECTED , \NLW_blk0000014e_DOA<11>_UNCONNECTED ,
\NLW_blk0000014e_DOA<10>_UNCONNECTED , \NLW_blk0000014e_DOA<9>_UNCONNECTED , \NLW_blk0000014e_DOA<8>_UNCONNECTED ,
\NLW_blk0000014e_DOA<7>_UNCONNECTED , \NLW_blk0000014e_DOA<6>_UNCONNECTED , \NLW_blk0000014e_DOA<5>_UNCONNECTED , \NLW_blk0000014e_DOA<4>_UNCONNECTED
, sig000000d9, sig000000d8, sig000000d7, sig000000d6}),
.ADDRA({sig000000c2, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000bb, sig000000ba, sig000000b9,
sig000000b8, sig000000b7, \NLW_blk0000014e_ADDRA<1>_UNCONNECTED , \NLW_blk0000014e_ADDRA<0>_UNCONNECTED }),
.ADDRB({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, \NLW_blk0000014e_ADDRB<1>_UNCONNECTED , \NLW_blk0000014e_ADDRB<0>_UNCONNECTED }),
.DIB({\NLW_blk0000014e_DIB<31>_UNCONNECTED , \NLW_blk0000014e_DIB<30>_UNCONNECTED , \NLW_blk0000014e_DIB<29>_UNCONNECTED ,
\NLW_blk0000014e_DIB<28>_UNCONNECTED , \NLW_blk0000014e_DIB<27>_UNCONNECTED , \NLW_blk0000014e_DIB<26>_UNCONNECTED ,
\NLW_blk0000014e_DIB<25>_UNCONNECTED , \NLW_blk0000014e_DIB<24>_UNCONNECTED , \NLW_blk0000014e_DIB<23>_UNCONNECTED ,
\NLW_blk0000014e_DIB<22>_UNCONNECTED , \NLW_blk0000014e_DIB<21>_UNCONNECTED , \NLW_blk0000014e_DIB<20>_UNCONNECTED ,
\NLW_blk0000014e_DIB<19>_UNCONNECTED , \NLW_blk0000014e_DIB<18>_UNCONNECTED , \NLW_blk0000014e_DIB<17>_UNCONNECTED ,
\NLW_blk0000014e_DIB<16>_UNCONNECTED , \NLW_blk0000014e_DIB<15>_UNCONNECTED , \NLW_blk0000014e_DIB<14>_UNCONNECTED ,
\NLW_blk0000014e_DIB<13>_UNCONNECTED , \NLW_blk0000014e_DIB<12>_UNCONNECTED , \NLW_blk0000014e_DIB<11>_UNCONNECTED ,
\NLW_blk0000014e_DIB<10>_UNCONNECTED , \NLW_blk0000014e_DIB<9>_UNCONNECTED , \NLW_blk0000014e_DIB<8>_UNCONNECTED ,
\NLW_blk0000014e_DIB<7>_UNCONNECTED , \NLW_blk0000014e_DIB<6>_UNCONNECTED , \NLW_blk0000014e_DIB<5>_UNCONNECTED , \NLW_blk0000014e_DIB<4>_UNCONNECTED
, \NLW_blk0000014e_DIB<3>_UNCONNECTED , \NLW_blk0000014e_DIB<2>_UNCONNECTED , \NLW_blk0000014e_DIB<1>_UNCONNECTED ,
\NLW_blk0000014e_DIB<0>_UNCONNECTED }),
.DOPA({\NLW_blk0000014e_DOPA<3>_UNCONNECTED , \NLW_blk0000014e_DOPA<2>_UNCONNECTED , \NLW_blk0000014e_DOPA<1>_UNCONNECTED ,
\NLW_blk0000014e_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk0000014e_DIPB<3>_UNCONNECTED , \NLW_blk0000014e_DIPB<2>_UNCONNECTED , \NLW_blk0000014e_DIPB<1>_UNCONNECTED ,
\NLW_blk0000014e_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk0000014e_DOPB<3>_UNCONNECTED , \NLW_blk0000014e_DOPB<2>_UNCONNECTED , \NLW_blk0000014e_DOPB<1>_UNCONNECTED ,
\NLW_blk0000014e_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk0000014e_DOB<31>_UNCONNECTED , \NLW_blk0000014e_DOB<30>_UNCONNECTED , \NLW_blk0000014e_DOB<29>_UNCONNECTED ,
\NLW_blk0000014e_DOB<28>_UNCONNECTED , \NLW_blk0000014e_DOB<27>_UNCONNECTED , \NLW_blk0000014e_DOB<26>_UNCONNECTED ,
\NLW_blk0000014e_DOB<25>_UNCONNECTED , \NLW_blk0000014e_DOB<24>_UNCONNECTED , \NLW_blk0000014e_DOB<23>_UNCONNECTED ,
\NLW_blk0000014e_DOB<22>_UNCONNECTED , \NLW_blk0000014e_DOB<21>_UNCONNECTED , \NLW_blk0000014e_DOB<20>_UNCONNECTED ,
\NLW_blk0000014e_DOB<19>_UNCONNECTED , \NLW_blk0000014e_DOB<18>_UNCONNECTED , \NLW_blk0000014e_DOB<17>_UNCONNECTED ,
\NLW_blk0000014e_DOB<16>_UNCONNECTED , \NLW_blk0000014e_DOB<15>_UNCONNECTED , \NLW_blk0000014e_DOB<14>_UNCONNECTED ,
\NLW_blk0000014e_DOB<13>_UNCONNECTED , \NLW_blk0000014e_DOB<12>_UNCONNECTED , \NLW_blk0000014e_DOB<11>_UNCONNECTED ,
\NLW_blk0000014e_DOB<10>_UNCONNECTED , \NLW_blk0000014e_DOB<9>_UNCONNECTED , \NLW_blk0000014e_DOB<8>_UNCONNECTED ,
\NLW_blk0000014e_DOB<7>_UNCONNECTED , \NLW_blk0000014e_DOB<6>_UNCONNECTED , \NLW_blk0000014e_DOB<5>_UNCONNECTED , \NLW_blk0000014e_DOB<4>_UNCONNECTED
, sig000000ca, sig000000c9, sig000000c8, sig000000c7}),
.WEB({sig00000002, sig00000002, sig00000002, sig00000002}),
.DIA({\NLW_blk0000014e_DIA<31>_UNCONNECTED , \NLW_blk0000014e_DIA<30>_UNCONNECTED , \NLW_blk0000014e_DIA<29>_UNCONNECTED ,
\NLW_blk0000014e_DIA<28>_UNCONNECTED , \NLW_blk0000014e_DIA<27>_UNCONNECTED , \NLW_blk0000014e_DIA<26>_UNCONNECTED ,
\NLW_blk0000014e_DIA<25>_UNCONNECTED , \NLW_blk0000014e_DIA<24>_UNCONNECTED , \NLW_blk0000014e_DIA<23>_UNCONNECTED ,
\NLW_blk0000014e_DIA<22>_UNCONNECTED , \NLW_blk0000014e_DIA<21>_UNCONNECTED , \NLW_blk0000014e_DIA<20>_UNCONNECTED ,
\NLW_blk0000014e_DIA<19>_UNCONNECTED , \NLW_blk0000014e_DIA<18>_UNCONNECTED , \NLW_blk0000014e_DIA<17>_UNCONNECTED ,
\NLW_blk0000014e_DIA<16>_UNCONNECTED , \NLW_blk0000014e_DIA<15>_UNCONNECTED , \NLW_blk0000014e_DIA<14>_UNCONNECTED ,
\NLW_blk0000014e_DIA<13>_UNCONNECTED , \NLW_blk0000014e_DIA<12>_UNCONNECTED , \NLW_blk0000014e_DIA<11>_UNCONNECTED ,
\NLW_blk0000014e_DIA<10>_UNCONNECTED , \NLW_blk0000014e_DIA<9>_UNCONNECTED , \NLW_blk0000014e_DIA<8>_UNCONNECTED ,
\NLW_blk0000014e_DIA<7>_UNCONNECTED , \NLW_blk0000014e_DIA<6>_UNCONNECTED , \NLW_blk0000014e_DIA<5>_UNCONNECTED , \NLW_blk0000014e_DIA<4>_UNCONNECTED
, sig00000002, sig00000002, sig00000002, sig00000002})
);
RAMB16BWER #(
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h1111111111111111111111111111111111111111111111111111111110000000 ),
.INIT_06 ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_07 ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_08 ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_09 ( 256'h1111111111111111111111111111111111111111111111111111111111111111 ),
.INIT_0A ( 256'h2222222222222222222222222222222222222222222221111111111111111111 ),
.INIT_0B ( 256'h2222222222222222222222222222222222222222222222222222222222222222 ),
.INIT_0C ( 256'h2222222222222222222222222222222222222222222222222222222222222222 ),
.INIT_0D ( 256'h2222222222222222222222222222222222222222222222222222222222222222 ),
.INIT_0E ( 256'h2222222222222222222222222222222222222222222222222222222222222222 ),
.INIT_0F ( 256'h3333333333333333333333222222222222222222222222222222222222222222 ),
.INIT_10 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_11 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_12 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_13 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_14 ( 256'h3333333333333333333333333333333333333333333333333333333333333333 ),
.INIT_15 ( 256'h4444444444444444444444444444444444444444444333333333333333333333 ),
.INIT_16 ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_17 ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_18 ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_19 ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_1A ( 256'h4444444444444444444444444444444444444444444444444444444444444444 ),
.INIT_1B ( 256'h5555555555555555555555555555555444444444444444444444444444444444 ),
.INIT_1C ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_1D ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_1E ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_1F ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_20 ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_21 ( 256'h5555555555555555555555555555555555555555555555555555555555555555 ),
.INIT_22 ( 256'h6666666666666666666666666666555555555555555555555555555555555555 ),
.INIT_23 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_24 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_25 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_26 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_27 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_28 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_29 ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_2A ( 256'h6666666666666666666666666666666666666666666666666666666666666666 ),
.INIT_2B ( 256'h7777777777777777777777777777777777777766666666666666666666666666 ),
.INIT_2C ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_2D ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_2E ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_2F ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_30 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_31 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_32 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_33 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_34 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_35 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_36 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_37 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_38 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_39 ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3A ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3B ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3C ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3D ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3E ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_3F ( 256'h7777777777777777777777777777777777777777777777777777777777777777 ),
.INIT_A ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 4 ),
.DATA_WIDTH_B ( 4 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_B ( 36'h000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
blk0000014f (
.REGCEA(sig00000002),
.CLKA(clk),
.ENB(sig00000001),
.RSTB(sig00000002),
.CLKB(clk),
.REGCEB(sig00000002),
.RSTA(sig00000002),
.ENA(sig00000001),
.DIPA({\NLW_blk0000014f_DIPA<3>_UNCONNECTED , \NLW_blk0000014f_DIPA<2>_UNCONNECTED , \NLW_blk0000014f_DIPA<1>_UNCONNECTED ,
\NLW_blk0000014f_DIPA<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.DOA({\NLW_blk0000014f_DOA<31>_UNCONNECTED , \NLW_blk0000014f_DOA<30>_UNCONNECTED , \NLW_blk0000014f_DOA<29>_UNCONNECTED ,
\NLW_blk0000014f_DOA<28>_UNCONNECTED , \NLW_blk0000014f_DOA<27>_UNCONNECTED , \NLW_blk0000014f_DOA<26>_UNCONNECTED ,
\NLW_blk0000014f_DOA<25>_UNCONNECTED , \NLW_blk0000014f_DOA<24>_UNCONNECTED , \NLW_blk0000014f_DOA<23>_UNCONNECTED ,
\NLW_blk0000014f_DOA<22>_UNCONNECTED , \NLW_blk0000014f_DOA<21>_UNCONNECTED , \NLW_blk0000014f_DOA<20>_UNCONNECTED ,
\NLW_blk0000014f_DOA<19>_UNCONNECTED , \NLW_blk0000014f_DOA<18>_UNCONNECTED , \NLW_blk0000014f_DOA<17>_UNCONNECTED ,
\NLW_blk0000014f_DOA<16>_UNCONNECTED , \NLW_blk0000014f_DOA<15>_UNCONNECTED , \NLW_blk0000014f_DOA<14>_UNCONNECTED ,
\NLW_blk0000014f_DOA<13>_UNCONNECTED , \NLW_blk0000014f_DOA<12>_UNCONNECTED , \NLW_blk0000014f_DOA<11>_UNCONNECTED ,
\NLW_blk0000014f_DOA<10>_UNCONNECTED , \NLW_blk0000014f_DOA<9>_UNCONNECTED , \NLW_blk0000014f_DOA<8>_UNCONNECTED ,
\NLW_blk0000014f_DOA<7>_UNCONNECTED , \NLW_blk0000014f_DOA<6>_UNCONNECTED , \NLW_blk0000014f_DOA<5>_UNCONNECTED , \NLW_blk0000014f_DOA<4>_UNCONNECTED
, \NLW_blk0000014f_DOA<3>_UNCONNECTED , sig000000e0, sig000000df, sig000000de}),
.ADDRA({sig000000c2, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000bb, sig000000ba, sig000000b9,
sig000000b8, sig000000b7, \NLW_blk0000014f_ADDRA<1>_UNCONNECTED , \NLW_blk0000014f_ADDRA<0>_UNCONNECTED }),
.ADDRB({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, \NLW_blk0000014f_ADDRB<1>_UNCONNECTED , \NLW_blk0000014f_ADDRB<0>_UNCONNECTED }),
.DIB({\NLW_blk0000014f_DIB<31>_UNCONNECTED , \NLW_blk0000014f_DIB<30>_UNCONNECTED , \NLW_blk0000014f_DIB<29>_UNCONNECTED ,
\NLW_blk0000014f_DIB<28>_UNCONNECTED , \NLW_blk0000014f_DIB<27>_UNCONNECTED , \NLW_blk0000014f_DIB<26>_UNCONNECTED ,
\NLW_blk0000014f_DIB<25>_UNCONNECTED , \NLW_blk0000014f_DIB<24>_UNCONNECTED , \NLW_blk0000014f_DIB<23>_UNCONNECTED ,
\NLW_blk0000014f_DIB<22>_UNCONNECTED , \NLW_blk0000014f_DIB<21>_UNCONNECTED , \NLW_blk0000014f_DIB<20>_UNCONNECTED ,
\NLW_blk0000014f_DIB<19>_UNCONNECTED , \NLW_blk0000014f_DIB<18>_UNCONNECTED , \NLW_blk0000014f_DIB<17>_UNCONNECTED ,
\NLW_blk0000014f_DIB<16>_UNCONNECTED , \NLW_blk0000014f_DIB<15>_UNCONNECTED , \NLW_blk0000014f_DIB<14>_UNCONNECTED ,
\NLW_blk0000014f_DIB<13>_UNCONNECTED , \NLW_blk0000014f_DIB<12>_UNCONNECTED , \NLW_blk0000014f_DIB<11>_UNCONNECTED ,
\NLW_blk0000014f_DIB<10>_UNCONNECTED , \NLW_blk0000014f_DIB<9>_UNCONNECTED , \NLW_blk0000014f_DIB<8>_UNCONNECTED ,
\NLW_blk0000014f_DIB<7>_UNCONNECTED , \NLW_blk0000014f_DIB<6>_UNCONNECTED , \NLW_blk0000014f_DIB<5>_UNCONNECTED , \NLW_blk0000014f_DIB<4>_UNCONNECTED
, \NLW_blk0000014f_DIB<3>_UNCONNECTED , \NLW_blk0000014f_DIB<2>_UNCONNECTED , \NLW_blk0000014f_DIB<1>_UNCONNECTED ,
\NLW_blk0000014f_DIB<0>_UNCONNECTED }),
.DOPA({\NLW_blk0000014f_DOPA<3>_UNCONNECTED , \NLW_blk0000014f_DOPA<2>_UNCONNECTED , \NLW_blk0000014f_DOPA<1>_UNCONNECTED ,
\NLW_blk0000014f_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk0000014f_DIPB<3>_UNCONNECTED , \NLW_blk0000014f_DIPB<2>_UNCONNECTED , \NLW_blk0000014f_DIPB<1>_UNCONNECTED ,
\NLW_blk0000014f_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk0000014f_DOPB<3>_UNCONNECTED , \NLW_blk0000014f_DOPB<2>_UNCONNECTED , \NLW_blk0000014f_DOPB<1>_UNCONNECTED ,
\NLW_blk0000014f_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk0000014f_DOB<31>_UNCONNECTED , \NLW_blk0000014f_DOB<30>_UNCONNECTED , \NLW_blk0000014f_DOB<29>_UNCONNECTED ,
\NLW_blk0000014f_DOB<28>_UNCONNECTED , \NLW_blk0000014f_DOB<27>_UNCONNECTED , \NLW_blk0000014f_DOB<26>_UNCONNECTED ,
\NLW_blk0000014f_DOB<25>_UNCONNECTED , \NLW_blk0000014f_DOB<24>_UNCONNECTED , \NLW_blk0000014f_DOB<23>_UNCONNECTED ,
\NLW_blk0000014f_DOB<22>_UNCONNECTED , \NLW_blk0000014f_DOB<21>_UNCONNECTED , \NLW_blk0000014f_DOB<20>_UNCONNECTED ,
\NLW_blk0000014f_DOB<19>_UNCONNECTED , \NLW_blk0000014f_DOB<18>_UNCONNECTED , \NLW_blk0000014f_DOB<17>_UNCONNECTED ,
\NLW_blk0000014f_DOB<16>_UNCONNECTED , \NLW_blk0000014f_DOB<15>_UNCONNECTED , \NLW_blk0000014f_DOB<14>_UNCONNECTED ,
\NLW_blk0000014f_DOB<13>_UNCONNECTED , \NLW_blk0000014f_DOB<12>_UNCONNECTED , \NLW_blk0000014f_DOB<11>_UNCONNECTED ,
\NLW_blk0000014f_DOB<10>_UNCONNECTED , \NLW_blk0000014f_DOB<9>_UNCONNECTED , \NLW_blk0000014f_DOB<8>_UNCONNECTED ,
\NLW_blk0000014f_DOB<7>_UNCONNECTED , \NLW_blk0000014f_DOB<6>_UNCONNECTED , \NLW_blk0000014f_DOB<5>_UNCONNECTED , \NLW_blk0000014f_DOB<4>_UNCONNECTED
, \NLW_blk0000014f_DOB<3>_UNCONNECTED , sig000000d1, sig000000d0, sig000000cf}),
.WEB({sig00000002, sig00000002, sig00000002, sig00000002}),
.DIA({\NLW_blk0000014f_DIA<31>_UNCONNECTED , \NLW_blk0000014f_DIA<30>_UNCONNECTED , \NLW_blk0000014f_DIA<29>_UNCONNECTED ,
\NLW_blk0000014f_DIA<28>_UNCONNECTED , \NLW_blk0000014f_DIA<27>_UNCONNECTED , \NLW_blk0000014f_DIA<26>_UNCONNECTED ,
\NLW_blk0000014f_DIA<25>_UNCONNECTED , \NLW_blk0000014f_DIA<24>_UNCONNECTED , \NLW_blk0000014f_DIA<23>_UNCONNECTED ,
\NLW_blk0000014f_DIA<22>_UNCONNECTED , \NLW_blk0000014f_DIA<21>_UNCONNECTED , \NLW_blk0000014f_DIA<20>_UNCONNECTED ,
\NLW_blk0000014f_DIA<19>_UNCONNECTED , \NLW_blk0000014f_DIA<18>_UNCONNECTED , \NLW_blk0000014f_DIA<17>_UNCONNECTED ,
\NLW_blk0000014f_DIA<16>_UNCONNECTED , \NLW_blk0000014f_DIA<15>_UNCONNECTED , \NLW_blk0000014f_DIA<14>_UNCONNECTED ,
\NLW_blk0000014f_DIA<13>_UNCONNECTED , \NLW_blk0000014f_DIA<12>_UNCONNECTED , \NLW_blk0000014f_DIA<11>_UNCONNECTED ,
\NLW_blk0000014f_DIA<10>_UNCONNECTED , \NLW_blk0000014f_DIA<9>_UNCONNECTED , \NLW_blk0000014f_DIA<8>_UNCONNECTED ,
\NLW_blk0000014f_DIA<7>_UNCONNECTED , \NLW_blk0000014f_DIA<6>_UNCONNECTED , \NLW_blk0000014f_DIA<5>_UNCONNECTED , \NLW_blk0000014f_DIA<4>_UNCONNECTED
, sig00000002, sig00000002, sig00000002, sig00000002})
);
RAMB16BWER #(
.INIT_00 ( 256'hE158CF269D047BE158CF369D047BE258CF36AD047BE258CF36AD147BE259CF36 ),
.INIT_01 ( 256'h158CF36AD147BE259C036AD148BF259C037AE148BF269C037AE158BF269D047A ),
.INIT_02 ( 256'h48BF259C037AE158CF369D047BE259C036AD148BF269C037AE158CF269D047BE ),
.INIT_03 ( 256'h59C037AE158CF36AD148BF269D047BE158CF36AD148BF269D047BE158CF36AD1 ),
.INIT_04 ( 256'h58CF36AD148BF26AD148BF269D047BE259C037AE158CF36AD148BF269D047BE2 ),
.INIT_05 ( 256'h259C037BE259C037BE259C037BE259C037BE259C037AE259C037AE158CF37AE1 ),
.INIT_06 ( 256'hCF36AE158C037BE259D047BF269D148BF36AD148CF36AE158C037AE159C037AE ),
.INIT_07 ( 256'h26AD158C037BE269D148BF36AE159C047BF26AD148CF37AE259C047BF269D148 ),
.INIT_08 ( 256'h59C048BF37AE259D148C037BE26AD158C037BF26AD158C047BF26AD158C037BE ),
.INIT_09 ( 256'h37BF36AE269D159C048CF37BF26AE159D148C037BF26AE159D048CF37BE26AD1 ),
.INIT_0A ( 256'hD159D048C048C037BF37BE26AE269D159D148C048BF37BF26AE269D159D048C0 ),
.INIT_0B ( 256'h159D159D159D159D159D159D048C048C048C048BF37BF37BF36AE26AE26AD159 ),
.INIT_0C ( 256'h048C049D159D159D159D159D159D159E26AE26AE26AE26AE26AE26AE26AE26AD ),
.INIT_0D ( 256'h9D159D26AE26BF37BF38C048C049D159D15AE26AE26AE37BF37BF37B048C048C ),
.INIT_0E ( 256'hAF37C048D159E26AF37B048C159D16AE27BF37C048D159D26AE26BF37B048C04 ),
.INIT_0F ( 256'h5AE27B048D15AE27B048D15AE27BF48C159E26BF38C059D26AE37B048C159E26 ),
.INIT_10 ( 256'h8D16AF38C15AE37C059E27B049D16AF38C15AE27B049D16AF38C059E26BF48C1 ),
.INIT_11 ( 256'h48D26BF49D27B049E27B059E27C059E27C059E27C059E27B059E27B049D26BF4 ),
.INIT_12 ( 256'h6B059E38C16BF49E27C15AF48D26B059E37C16AF48D26B049E27C05AE38C16AF ),
.INIT_13 ( 256'h05AF49E38C16B05AF48D27C16AF49E38C16B059E38D26B05AE38D26B05AE38D2 ),
.INIT_14 ( 256'h16B05AF49E38D28D27C16B05AF49E38D27C16B05AF48D27C16B05AF49E38D16B ),
.INIT_15 ( 256'h8D27D27C17C16B16B05A05AF49F49E38E38D27C17C16B05AF5AF49E38D27D27C ),
.INIT_16 ( 256'h4AF5AF5AF5AF5A05A05A05A05A05AF5AF5AF5AF4AF4AF49F49E49E39E38E38D2 ),
.INIT_17 ( 256'h7C27D28D38E39F4AF5A05B06B16B16C17C27D28D28D38E39E39E49E49F49F4AF ),
.INIT_18 ( 256'hE49F5A06C17D28E39F4A05B16C27D38E49F4A05B16C17D28D39E49F5A05B06B1 ),
.INIT_19 ( 256'hA05B17D39F5A06C28E39F5B17C28E4AF5B17C28E49F5B16C28D39F4A06B17D28 ),
.INIT_1A ( 256'hA06C28E4A07D39F5B17D39F5B17D39F5B17D39F5B17D39F5B17D38E4A06C28E4 ),
.INIT_1B ( 256'hE4A17D3A06C39F5C28E5B17D4A06C39F5B28E4A07D39F5C28E4A07D39F5B17E4 ),
.INIT_1C ( 256'h5C29F5C29F6C3906C3906D3906D3906D3906C3906C39F6C29F5C28F5B28E5B17 ),
.INIT_1D ( 256'h06D4A18E5C2906D4A18E5B29F6C3A07D4B18E5B29F6C3906D3A17E4B18E5B28F ),
.INIT_1E ( 256'hD4B28F6D4B29F6D4B29F6D4B28F6D4A18F6C3A17E5C2907D4B28F6D3A17E5C29 ),
.INIT_1F ( 256'hD4B2907E5C4B2907E5C3A18F6D4B2907E6D3A18F6D4B2907E5C3A18F6D3A18F6 ),
.INIT_20 ( 256'hE6D4C3A2908F6D5C3B2908F6D5C3A2907E6D4B3A18F6E5C3A2907E5C4B2907E6 ),
.INIT_21 ( 256'h291808F7E6D5C4B3A291807F6E5D4C3A291807E6D5C4B2A1907F6D5C4B2A1807 ),
.INIT_22 ( 256'h7E6E6E5D5D4C4C3B3B2A29191808F7F6E6D5D4C4B3B2A291808F7E6E5D4C4B3A ),
.INIT_23 ( 256'hC4D5D5D5D5D5D5C4C4C4C4C4C4C4C4C4B3B3B3B3B2A2A2A29191919080807F7F ),
.INIT_24 ( 256'h3B4C4C5D5D6E6E6F7F7F808081919192A2A2A2B3B3B3B3B3C4C4C4C4C4C4C4C4 ),
.INIT_25 ( 256'hA3B4C5D6E7F808192A3B4C5D5E6F7F809192A2B3C4C5D5E6E7F70809191A2A3B ),
.INIT_26 ( 256'h1A3C4D6F7092A3C4D6E7091A3B4D5E6F8092A3C4D5E7F8091A3B4C5D6E708192 ),
.INIT_27 ( 256'h81A3C5E7092B4D6F81A3C5E7092A3C5E7092A3C5E7081A3C5D6F81A2B4D6E709 ),
.INIT_28 ( 256'hF82B4D7092C5E71A3C5F81A3D6F81A4D6F81A4D6F81A3C5F81A3C5E7092B4D6F ),
.INIT_29 ( 256'h5F82B5E81B4E71A4D70A3C6F92C5F81B4E70A3D6F92B5E71A4D6092B5E71A3D6 ),
.INIT_2A ( 256'hA4E81B5F82C6093D70A4D71B4E81B5E82B5F82C5F92C6F92C6F92C6F92C5F82C ),
.INIT_2B ( 256'hE82C60A4F93D71B5F93D71B5F93D60A4E82C60A4E81B5F93D71A4E82C5F93D70 ),
.INIT_2C ( 256'h1B50A4F93E82C71B60A4F93D82C61B5FA4E82D71B5FA4E82C61B5F93D72C60A4 ),
.INIT_2D ( 256'h1C71C61C61B61B60B50B50A5FA4F94E93E83D82D71C61B60A5FA4E93E82D71C6 ),
.INIT_2E ( 256'h0B61C72D82D83E94E94FA4FA50B50B60B61B61C61C71C71C72C72C72C72C72C7 ),
.INIT_2F ( 256'hD94FA50C72D83FA50B61C73E94FA50B61C72D83E94FA50B61C72D83E94FA50B6 ),
.INIT_30 ( 256'h84FB62D84FB62D84FB61D84FA61C83EA50C72E940B61D83FA50C72D94FA51C72 ),
.INIT_31 ( 256'h1C840B73EA62D950C84FB72EA51D84FB72E951C83FB62D940C73EA51C83FA61D ),
.INIT_32 ( 256'h62EA62FB73FB73FB73FB62EA62EA62EA62E951D951D840C840B73FB62EA61D95 ),
.INIT_33 ( 256'h962EB730C851D962EB73FC840D951DA62EB73FB740C840D951D951DA62EA62EA ),
.INIT_34 ( 256'h963FC952EB841DA730C952FB841DA63FC851EA730C851EA730C851EA63FB841D ),
.INIT_35 ( 256'h730DA741EB852EB852FC852FC952FC962FC952FC952FC852EB851EB741DA730D ),
.INIT_36 ( 256'h0EB8530DA752FC9741EB8630DA741FC9630DA741FC9630DA741EB852FC9630DA ),
.INIT_37 ( 256'h7520DB8631EC9742FDA8530DB8631EB9641EC9741FC9741FC9741FC9641EB963 ),
.INIT_38 ( 256'hB86420EB97530ECA8531FCA8631FCA8631FCA8531ECA7530EB9742FDB8631FCA ),
.INIT_39 ( 256'hA97531FDCA86420ECA86531FDB97531FDB97531FDB97530ECA86420EC97531FD ),
.INIT_3A ( 256'h75421FDCA976421FECA975420FDBA865310ECB975420EDB976420EDB975420EC ),
.INIT_3B ( 256'h0EDCB98764320FEDBA9765321FEDBA8764310FDCA9865320FDCA9764310EDBA8 ),
.INIT_3C ( 256'h543210FEDCBA9876543210FEDCBA987654210FEDCBA87654320FEDCB98765321 ),
.INIT_3D ( 256'h66544322100FEEDCCBAA9877655432110FEEDCBAA987655432100FEDCBA98876 ),
.INIT_3E ( 256'h44333222111000FFEEEDDCCCBBAA998887766554433221100FEEDDCCBAA99877 ),
.INIT_3F ( 256'hEEEEEEEEEEEEEEDDDDDDDDDDDCCCCCCCBBBBBBAAAAA999998888777766655554 ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 4 ),
.DATA_WIDTH_B ( 4 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
blk00000150 (
.REGCEA(sig00000002),
.CLKA(clk),
.ENB(sig00000001),
.RSTB(sig00000002),
.CLKB(clk),
.REGCEB(sig00000002),
.RSTA(sig00000002),
.ENA(sig00000001),
.DIPA({\NLW_blk00000150_DIPA<3>_UNCONNECTED , \NLW_blk00000150_DIPA<2>_UNCONNECTED , \NLW_blk00000150_DIPA<1>_UNCONNECTED ,
\NLW_blk00000150_DIPA<0>_UNCONNECTED }),
.WEA({sig00000002, sig00000002, sig00000002, sig00000002}),
.DOA({\NLW_blk00000150_DOA<31>_UNCONNECTED , \NLW_blk00000150_DOA<30>_UNCONNECTED , \NLW_blk00000150_DOA<29>_UNCONNECTED ,
\NLW_blk00000150_DOA<28>_UNCONNECTED , \NLW_blk00000150_DOA<27>_UNCONNECTED , \NLW_blk00000150_DOA<26>_UNCONNECTED ,
\NLW_blk00000150_DOA<25>_UNCONNECTED , \NLW_blk00000150_DOA<24>_UNCONNECTED , \NLW_blk00000150_DOA<23>_UNCONNECTED ,
\NLW_blk00000150_DOA<22>_UNCONNECTED , \NLW_blk00000150_DOA<21>_UNCONNECTED , \NLW_blk00000150_DOA<20>_UNCONNECTED ,
\NLW_blk00000150_DOA<19>_UNCONNECTED , \NLW_blk00000150_DOA<18>_UNCONNECTED , \NLW_blk00000150_DOA<17>_UNCONNECTED ,
\NLW_blk00000150_DOA<16>_UNCONNECTED , \NLW_blk00000150_DOA<15>_UNCONNECTED , \NLW_blk00000150_DOA<14>_UNCONNECTED ,
\NLW_blk00000150_DOA<13>_UNCONNECTED , \NLW_blk00000150_DOA<12>_UNCONNECTED , \NLW_blk00000150_DOA<11>_UNCONNECTED ,
\NLW_blk00000150_DOA<10>_UNCONNECTED , \NLW_blk00000150_DOA<9>_UNCONNECTED , \NLW_blk00000150_DOA<8>_UNCONNECTED ,
\NLW_blk00000150_DOA<7>_UNCONNECTED , \NLW_blk00000150_DOA<6>_UNCONNECTED , \NLW_blk00000150_DOA<5>_UNCONNECTED , \NLW_blk00000150_DOA<4>_UNCONNECTED
, sig000000d5, sig000000d4, sig000000d3, sig000000d2}),
.ADDRA({sig000000c2, sig000000c1, sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bc, sig000000bb, sig000000ba, sig000000b9,
sig000000b8, sig000000b7, \NLW_blk00000150_ADDRA<1>_UNCONNECTED , \NLW_blk00000150_ADDRA<0>_UNCONNECTED }),
.ADDRB({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, \NLW_blk00000150_ADDRB<1>_UNCONNECTED , \NLW_blk00000150_ADDRB<0>_UNCONNECTED }),
.DIB({\NLW_blk00000150_DIB<31>_UNCONNECTED , \NLW_blk00000150_DIB<30>_UNCONNECTED , \NLW_blk00000150_DIB<29>_UNCONNECTED ,
\NLW_blk00000150_DIB<28>_UNCONNECTED , \NLW_blk00000150_DIB<27>_UNCONNECTED , \NLW_blk00000150_DIB<26>_UNCONNECTED ,
\NLW_blk00000150_DIB<25>_UNCONNECTED , \NLW_blk00000150_DIB<24>_UNCONNECTED , \NLW_blk00000150_DIB<23>_UNCONNECTED ,
\NLW_blk00000150_DIB<22>_UNCONNECTED , \NLW_blk00000150_DIB<21>_UNCONNECTED , \NLW_blk00000150_DIB<20>_UNCONNECTED ,
\NLW_blk00000150_DIB<19>_UNCONNECTED , \NLW_blk00000150_DIB<18>_UNCONNECTED , \NLW_blk00000150_DIB<17>_UNCONNECTED ,
\NLW_blk00000150_DIB<16>_UNCONNECTED , \NLW_blk00000150_DIB<15>_UNCONNECTED , \NLW_blk00000150_DIB<14>_UNCONNECTED ,
\NLW_blk00000150_DIB<13>_UNCONNECTED , \NLW_blk00000150_DIB<12>_UNCONNECTED , \NLW_blk00000150_DIB<11>_UNCONNECTED ,
\NLW_blk00000150_DIB<10>_UNCONNECTED , \NLW_blk00000150_DIB<9>_UNCONNECTED , \NLW_blk00000150_DIB<8>_UNCONNECTED ,
\NLW_blk00000150_DIB<7>_UNCONNECTED , \NLW_blk00000150_DIB<6>_UNCONNECTED , \NLW_blk00000150_DIB<5>_UNCONNECTED , \NLW_blk00000150_DIB<4>_UNCONNECTED
, \NLW_blk00000150_DIB<3>_UNCONNECTED , \NLW_blk00000150_DIB<2>_UNCONNECTED , \NLW_blk00000150_DIB<1>_UNCONNECTED ,
\NLW_blk00000150_DIB<0>_UNCONNECTED }),
.DOPA({\NLW_blk00000150_DOPA<3>_UNCONNECTED , \NLW_blk00000150_DOPA<2>_UNCONNECTED , \NLW_blk00000150_DOPA<1>_UNCONNECTED ,
\NLW_blk00000150_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000150_DIPB<3>_UNCONNECTED , \NLW_blk00000150_DIPB<2>_UNCONNECTED , \NLW_blk00000150_DIPB<1>_UNCONNECTED ,
\NLW_blk00000150_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000150_DOPB<3>_UNCONNECTED , \NLW_blk00000150_DOPB<2>_UNCONNECTED , \NLW_blk00000150_DOPB<1>_UNCONNECTED ,
\NLW_blk00000150_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000150_DOB<31>_UNCONNECTED , \NLW_blk00000150_DOB<30>_UNCONNECTED , \NLW_blk00000150_DOB<29>_UNCONNECTED ,
\NLW_blk00000150_DOB<28>_UNCONNECTED , \NLW_blk00000150_DOB<27>_UNCONNECTED , \NLW_blk00000150_DOB<26>_UNCONNECTED ,
\NLW_blk00000150_DOB<25>_UNCONNECTED , \NLW_blk00000150_DOB<24>_UNCONNECTED , \NLW_blk00000150_DOB<23>_UNCONNECTED ,
\NLW_blk00000150_DOB<22>_UNCONNECTED , \NLW_blk00000150_DOB<21>_UNCONNECTED , \NLW_blk00000150_DOB<20>_UNCONNECTED ,
\NLW_blk00000150_DOB<19>_UNCONNECTED , \NLW_blk00000150_DOB<18>_UNCONNECTED , \NLW_blk00000150_DOB<17>_UNCONNECTED ,
\NLW_blk00000150_DOB<16>_UNCONNECTED , \NLW_blk00000150_DOB<15>_UNCONNECTED , \NLW_blk00000150_DOB<14>_UNCONNECTED ,
\NLW_blk00000150_DOB<13>_UNCONNECTED , \NLW_blk00000150_DOB<12>_UNCONNECTED , \NLW_blk00000150_DOB<11>_UNCONNECTED ,
\NLW_blk00000150_DOB<10>_UNCONNECTED , \NLW_blk00000150_DOB<9>_UNCONNECTED , \NLW_blk00000150_DOB<8>_UNCONNECTED ,
\NLW_blk00000150_DOB<7>_UNCONNECTED , \NLW_blk00000150_DOB<6>_UNCONNECTED , \NLW_blk00000150_DOB<5>_UNCONNECTED , \NLW_blk00000150_DOB<4>_UNCONNECTED
, sig000000c6, sig000000c5, sig000000c4, sig000000c3}),
.WEB({sig00000002, sig00000002, sig00000002, sig00000002}),
.DIA({\NLW_blk00000150_DIA<31>_UNCONNECTED , \NLW_blk00000150_DIA<30>_UNCONNECTED , \NLW_blk00000150_DIA<29>_UNCONNECTED ,
\NLW_blk00000150_DIA<28>_UNCONNECTED , \NLW_blk00000150_DIA<27>_UNCONNECTED , \NLW_blk00000150_DIA<26>_UNCONNECTED ,
\NLW_blk00000150_DIA<25>_UNCONNECTED , \NLW_blk00000150_DIA<24>_UNCONNECTED , \NLW_blk00000150_DIA<23>_UNCONNECTED ,
\NLW_blk00000150_DIA<22>_UNCONNECTED , \NLW_blk00000150_DIA<21>_UNCONNECTED , \NLW_blk00000150_DIA<20>_UNCONNECTED ,
\NLW_blk00000150_DIA<19>_UNCONNECTED , \NLW_blk00000150_DIA<18>_UNCONNECTED , \NLW_blk00000150_DIA<17>_UNCONNECTED ,
\NLW_blk00000150_DIA<16>_UNCONNECTED , \NLW_blk00000150_DIA<15>_UNCONNECTED , \NLW_blk00000150_DIA<14>_UNCONNECTED ,
\NLW_blk00000150_DIA<13>_UNCONNECTED , \NLW_blk00000150_DIA<12>_UNCONNECTED , \NLW_blk00000150_DIA<11>_UNCONNECTED ,
\NLW_blk00000150_DIA<10>_UNCONNECTED , \NLW_blk00000150_DIA<9>_UNCONNECTED , \NLW_blk00000150_DIA<8>_UNCONNECTED ,
\NLW_blk00000150_DIA<7>_UNCONNECTED , \NLW_blk00000150_DIA<6>_UNCONNECTED , \NLW_blk00000150_DIA<5>_UNCONNECTED , \NLW_blk00000150_DIA<4>_UNCONNECTED
, sig00000002, sig00000002, sig00000002, sig00000002})
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000151 (
.A0(sig00000001),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig00000125),
.Q(sig00000129),
.Q15(NLW_blk00000151_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000152 (
.C(clk),
.CE(sig00000001),
.D(sig00000129),
.Q(sig00000123)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000153 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig00000126),
.Q(sig0000012a),
.Q15(NLW_blk00000153_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000154 (
.C(clk),
.CE(sig00000001),
.D(sig0000012a),
.Q(sig00000124)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000155 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d1),
.Q(sig0000012b),
.Q15(NLW_blk00000155_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000156 (
.C(clk),
.CE(sig00000001),
.D(sig0000012b),
.Q(sig00000113)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000157 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d0),
.Q(sig0000012c),
.Q15(NLW_blk00000157_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000158 (
.C(clk),
.CE(sig00000001),
.D(sig0000012c),
.Q(sig00000112)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000159 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000cf),
.Q(sig0000012d),
.Q15(NLW_blk00000159_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015a (
.C(clk),
.CE(sig00000001),
.D(sig0000012d),
.Q(sig00000111)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000015b (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000ce),
.Q(sig0000012e),
.Q15(NLW_blk0000015b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015c (
.C(clk),
.CE(sig00000001),
.D(sig0000012e),
.Q(sig00000110)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000015d (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000cd),
.Q(sig0000012f),
.Q15(NLW_blk0000015d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015e (
.C(clk),
.CE(sig00000001),
.D(sig0000012f),
.Q(sig0000010f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000015f (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000cc),
.Q(sig00000130),
.Q15(NLW_blk0000015f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000160 (
.C(clk),
.CE(sig00000001),
.D(sig00000130),
.Q(sig0000010e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000161 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000cb),
.Q(sig00000131),
.Q15(NLW_blk00000161_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000162 (
.C(clk),
.CE(sig00000001),
.D(sig00000131),
.Q(sig0000010d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000163 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000ca),
.Q(sig00000132),
.Q15(NLW_blk00000163_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000164 (
.C(clk),
.CE(sig00000001),
.D(sig00000132),
.Q(sig0000010c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000165 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c9),
.Q(sig00000133),
.Q15(NLW_blk00000165_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000166 (
.C(clk),
.CE(sig00000001),
.D(sig00000133),
.Q(sig0000010b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000167 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c8),
.Q(sig00000134),
.Q15(NLW_blk00000167_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000168 (
.C(clk),
.CE(sig00000001),
.D(sig00000134),
.Q(sig0000010a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000169 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c7),
.Q(sig00000135),
.Q15(NLW_blk00000169_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016a (
.C(clk),
.CE(sig00000001),
.D(sig00000135),
.Q(sig00000109)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000016b (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c6),
.Q(sig00000136),
.Q15(NLW_blk0000016b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016c (
.C(clk),
.CE(sig00000001),
.D(sig00000136),
.Q(sig00000108)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000016d (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c5),
.Q(sig00000137),
.Q15(NLW_blk0000016d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016e (
.C(clk),
.CE(sig00000001),
.D(sig00000137),
.Q(sig00000107)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000016f (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c4),
.Q(sig00000138),
.Q15(NLW_blk0000016f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000170 (
.C(clk),
.CE(sig00000001),
.D(sig00000138),
.Q(sig00000106)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000171 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000c3),
.Q(sig00000139),
.Q15(NLW_blk00000171_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000172 (
.C(clk),
.CE(sig00000001),
.D(sig00000139),
.Q(sig00000105)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000173 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000e0),
.Q(sig0000013a),
.Q15(NLW_blk00000173_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000174 (
.C(clk),
.CE(sig00000001),
.D(sig0000013a),
.Q(sig00000122)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000175 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000df),
.Q(sig0000013b),
.Q15(NLW_blk00000175_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000176 (
.C(clk),
.CE(sig00000001),
.D(sig0000013b),
.Q(sig00000121)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000177 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000de),
.Q(sig0000013c),
.Q15(NLW_blk00000177_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000178 (
.C(clk),
.CE(sig00000001),
.D(sig0000013c),
.Q(sig00000120)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000179 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000dd),
.Q(sig0000013d),
.Q15(NLW_blk00000179_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017a (
.C(clk),
.CE(sig00000001),
.D(sig0000013d),
.Q(sig0000011f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000017b (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000dc),
.Q(sig0000013e),
.Q15(NLW_blk0000017b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017c (
.C(clk),
.CE(sig00000001),
.D(sig0000013e),
.Q(sig0000011e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000017d (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000db),
.Q(sig0000013f),
.Q15(NLW_blk0000017d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017e (
.C(clk),
.CE(sig00000001),
.D(sig0000013f),
.Q(sig0000011d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000017f (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000da),
.Q(sig00000140),
.Q15(NLW_blk0000017f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000180 (
.C(clk),
.CE(sig00000001),
.D(sig00000140),
.Q(sig0000011c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000181 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d9),
.Q(sig00000141),
.Q15(NLW_blk00000181_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000182 (
.C(clk),
.CE(sig00000001),
.D(sig00000141),
.Q(sig0000011b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000183 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d8),
.Q(sig00000142),
.Q15(NLW_blk00000183_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000184 (
.C(clk),
.CE(sig00000001),
.D(sig00000142),
.Q(sig0000011a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000185 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d7),
.Q(sig00000143),
.Q15(NLW_blk00000185_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000186 (
.C(clk),
.CE(sig00000001),
.D(sig00000143),
.Q(sig00000119)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000187 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d6),
.Q(sig00000144),
.Q15(NLW_blk00000187_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000188 (
.C(clk),
.CE(sig00000001),
.D(sig00000144),
.Q(sig00000118)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000189 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d5),
.Q(sig00000145),
.Q15(NLW_blk00000189_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018a (
.C(clk),
.CE(sig00000001),
.D(sig00000145),
.Q(sig00000117)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000018b (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d4),
.Q(sig00000146),
.Q15(NLW_blk0000018b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018c (
.C(clk),
.CE(sig00000001),
.D(sig00000146),
.Q(sig00000116)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000018d (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d3),
.Q(sig00000147),
.Q15(NLW_blk0000018d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000018e (
.C(clk),
.CE(sig00000001),
.D(sig00000147),
.Q(sig00000115)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000018f (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(sig00000001),
.CLK(clk),
.D(sig000000d2),
.Q(sig00000148),
.Q15(NLW_blk0000018f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000190 (
.C(clk),
.CE(sig00000001),
.D(sig00000148),
.Q(sig00000114)
);
XORCY \blk00000025/blk00000055 (
.CI(\blk00000025/sig00000197 ),
.LI(\blk00000025/sig00000198 ),
.O(sig00000004)
);
MUXCY \blk00000025/blk00000054 (
.CI(\blk00000025/sig00000197 ),
.DI(sig00000045),
.S(\blk00000025/sig00000198 ),
.O(sig00000003)
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000053 (
.I0(sig00000045),
.I1(sig00000002),
.O(\blk00000025/sig00000198 )
);
XORCY \blk00000025/blk00000052 (
.CI(\blk00000025/sig00000195 ),
.LI(\blk00000025/sig00000196 ),
.O(sig00000005)
);
MUXCY \blk00000025/blk00000051 (
.CI(\blk00000025/sig00000195 ),
.DI(sig00000044),
.S(\blk00000025/sig00000196 ),
.O(\blk00000025/sig00000197 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000050 (
.I0(sig00000044),
.I1(sig00000002),
.O(\blk00000025/sig00000196 )
);
XORCY \blk00000025/blk0000004f (
.CI(\blk00000025/sig00000193 ),
.LI(\blk00000025/sig00000194 ),
.O(sig00000006)
);
MUXCY \blk00000025/blk0000004e (
.CI(\blk00000025/sig00000193 ),
.DI(sig00000043),
.S(\blk00000025/sig00000194 ),
.O(\blk00000025/sig00000195 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000004d (
.I0(sig00000043),
.I1(sig00000002),
.O(\blk00000025/sig00000194 )
);
XORCY \blk00000025/blk0000004c (
.CI(\blk00000025/sig00000191 ),
.LI(\blk00000025/sig00000192 ),
.O(sig00000007)
);
MUXCY \blk00000025/blk0000004b (
.CI(\blk00000025/sig00000191 ),
.DI(sig00000042),
.S(\blk00000025/sig00000192 ),
.O(\blk00000025/sig00000193 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000004a (
.I0(sig00000042),
.I1(sig00000002),
.O(\blk00000025/sig00000192 )
);
XORCY \blk00000025/blk00000049 (
.CI(\blk00000025/sig0000018f ),
.LI(\blk00000025/sig00000190 ),
.O(sig00000008)
);
MUXCY \blk00000025/blk00000048 (
.CI(\blk00000025/sig0000018f ),
.DI(sig00000041),
.S(\blk00000025/sig00000190 ),
.O(\blk00000025/sig00000191 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000047 (
.I0(sig00000041),
.I1(sig00000002),
.O(\blk00000025/sig00000190 )
);
XORCY \blk00000025/blk00000046 (
.CI(\blk00000025/sig0000018d ),
.LI(\blk00000025/sig0000018e ),
.O(sig00000009)
);
MUXCY \blk00000025/blk00000045 (
.CI(\blk00000025/sig0000018d ),
.DI(sig00000040),
.S(\blk00000025/sig0000018e ),
.O(\blk00000025/sig0000018f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000044 (
.I0(sig00000040),
.I1(sig00000002),
.O(\blk00000025/sig0000018e )
);
XORCY \blk00000025/blk00000043 (
.CI(\blk00000025/sig0000018b ),
.LI(\blk00000025/sig0000018c ),
.O(sig0000000a)
);
MUXCY \blk00000025/blk00000042 (
.CI(\blk00000025/sig0000018b ),
.DI(sig0000003f),
.S(\blk00000025/sig0000018c ),
.O(\blk00000025/sig0000018d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000041 (
.I0(sig0000003f),
.I1(sig00000001),
.O(\blk00000025/sig0000018c )
);
XORCY \blk00000025/blk00000040 (
.CI(\blk00000025/sig00000189 ),
.LI(\blk00000025/sig0000018a ),
.O(sig0000000b)
);
MUXCY \blk00000025/blk0000003f (
.CI(\blk00000025/sig00000189 ),
.DI(sig0000003e),
.S(\blk00000025/sig0000018a ),
.O(\blk00000025/sig0000018b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000003e (
.I0(sig0000003e),
.I1(sig00000002),
.O(\blk00000025/sig0000018a )
);
XORCY \blk00000025/blk0000003d (
.CI(\blk00000025/sig00000187 ),
.LI(\blk00000025/sig00000188 ),
.O(sig0000000c)
);
MUXCY \blk00000025/blk0000003c (
.CI(\blk00000025/sig00000187 ),
.DI(sig0000003d),
.S(\blk00000025/sig00000188 ),
.O(\blk00000025/sig00000189 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000003b (
.I0(sig0000003d),
.I1(sig00000002),
.O(\blk00000025/sig00000188 )
);
XORCY \blk00000025/blk0000003a (
.CI(\blk00000025/sig00000185 ),
.LI(\blk00000025/sig00000186 ),
.O(sig0000000d)
);
MUXCY \blk00000025/blk00000039 (
.CI(\blk00000025/sig00000185 ),
.DI(sig0000003c),
.S(\blk00000025/sig00000186 ),
.O(\blk00000025/sig00000187 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000038 (
.I0(sig0000003c),
.I1(sig00000002),
.O(\blk00000025/sig00000186 )
);
XORCY \blk00000025/blk00000037 (
.CI(\blk00000025/sig00000183 ),
.LI(\blk00000025/sig00000184 ),
.O(sig0000000e)
);
MUXCY \blk00000025/blk00000036 (
.CI(\blk00000025/sig00000183 ),
.DI(sig0000003b),
.S(\blk00000025/sig00000184 ),
.O(\blk00000025/sig00000185 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000035 (
.I0(sig0000003b),
.I1(sig00000002),
.O(\blk00000025/sig00000184 )
);
XORCY \blk00000025/blk00000034 (
.CI(\blk00000025/sig00000181 ),
.LI(\blk00000025/sig00000182 ),
.O(sig0000000f)
);
MUXCY \blk00000025/blk00000033 (
.CI(\blk00000025/sig00000181 ),
.DI(sig0000003a),
.S(\blk00000025/sig00000182 ),
.O(\blk00000025/sig00000183 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000032 (
.I0(sig00000002),
.I1(sig0000003a),
.O(\blk00000025/sig00000182 )
);
XORCY \blk00000025/blk00000031 (
.CI(\blk00000025/sig0000017f ),
.LI(\blk00000025/sig00000180 ),
.O(sig00000010)
);
MUXCY \blk00000025/blk00000030 (
.CI(\blk00000025/sig0000017f ),
.DI(sig00000039),
.S(\blk00000025/sig00000180 ),
.O(\blk00000025/sig00000181 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000002f (
.I0(sig00000001),
.I1(sig00000039),
.O(\blk00000025/sig00000180 )
);
XORCY \blk00000025/blk0000002e (
.CI(\blk00000025/sig0000017d ),
.LI(\blk00000025/sig0000017e ),
.O(sig00000011)
);
MUXCY \blk00000025/blk0000002d (
.CI(\blk00000025/sig0000017d ),
.DI(sig00000038),
.S(\blk00000025/sig0000017e ),
.O(\blk00000025/sig0000017f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk0000002c (
.I0(sig00000001),
.I1(sig00000038),
.O(\blk00000025/sig0000017e )
);
XORCY \blk00000025/blk0000002b (
.CI(\blk00000025/sig0000017b ),
.LI(\blk00000025/sig0000017c ),
.O(sig00000012)
);
MUXCY \blk00000025/blk0000002a (
.CI(\blk00000025/sig0000017b ),
.DI(sig00000037),
.S(\blk00000025/sig0000017c ),
.O(\blk00000025/sig0000017d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000029 (
.I0(sig00000001),
.I1(sig00000037),
.O(\blk00000025/sig0000017c )
);
XORCY \blk00000025/blk00000028 (
.CI(sig00000002),
.LI(\blk00000025/sig0000017a ),
.O(sig00000013)
);
MUXCY \blk00000025/blk00000027 (
.CI(sig00000002),
.DI(sig00000036),
.S(\blk00000025/sig0000017a ),
.O(\blk00000025/sig0000017b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000025/blk00000026 (
.I0(sig00000002),
.I1(sig00000036),
.O(\blk00000025/sig0000017a )
);
XORCY \blk00000056/blk00000086 (
.CI(\blk00000056/sig000001e8 ),
.LI(\blk00000056/sig000001e9 ),
.O(sig00000023)
);
MUXCY \blk00000056/blk00000085 (
.CI(\blk00000056/sig000001e8 ),
.DI(sig00000045),
.S(\blk00000056/sig000001e9 ),
.O(sig00000024)
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000084 (
.I0(sig00000045),
.I1(sig00000035),
.O(\blk00000056/sig000001e9 )
);
XORCY \blk00000056/blk00000083 (
.CI(\blk00000056/sig000001e6 ),
.LI(\blk00000056/sig000001e7 ),
.O(sig00000022)
);
MUXCY \blk00000056/blk00000082 (
.CI(\blk00000056/sig000001e6 ),
.DI(sig00000044),
.S(\blk00000056/sig000001e7 ),
.O(\blk00000056/sig000001e8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000081 (
.I0(sig00000044),
.I1(sig00000035),
.O(\blk00000056/sig000001e7 )
);
XORCY \blk00000056/blk00000080 (
.CI(\blk00000056/sig000001e4 ),
.LI(\blk00000056/sig000001e5 ),
.O(sig00000021)
);
MUXCY \blk00000056/blk0000007f (
.CI(\blk00000056/sig000001e4 ),
.DI(sig00000043),
.S(\blk00000056/sig000001e5 ),
.O(\blk00000056/sig000001e6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000007e (
.I0(sig00000043),
.I1(sig00000035),
.O(\blk00000056/sig000001e5 )
);
XORCY \blk00000056/blk0000007d (
.CI(\blk00000056/sig000001e2 ),
.LI(\blk00000056/sig000001e3 ),
.O(sig00000020)
);
MUXCY \blk00000056/blk0000007c (
.CI(\blk00000056/sig000001e2 ),
.DI(sig00000042),
.S(\blk00000056/sig000001e3 ),
.O(\blk00000056/sig000001e4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000007b (
.I0(sig00000042),
.I1(sig00000035),
.O(\blk00000056/sig000001e3 )
);
XORCY \blk00000056/blk0000007a (
.CI(\blk00000056/sig000001e0 ),
.LI(\blk00000056/sig000001e1 ),
.O(sig0000001f)
);
MUXCY \blk00000056/blk00000079 (
.CI(\blk00000056/sig000001e0 ),
.DI(sig00000041),
.S(\blk00000056/sig000001e1 ),
.O(\blk00000056/sig000001e2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000078 (
.I0(sig00000041),
.I1(sig00000035),
.O(\blk00000056/sig000001e1 )
);
XORCY \blk00000056/blk00000077 (
.CI(\blk00000056/sig000001de ),
.LI(\blk00000056/sig000001df ),
.O(sig0000001e)
);
MUXCY \blk00000056/blk00000076 (
.CI(\blk00000056/sig000001de ),
.DI(sig00000040),
.S(\blk00000056/sig000001df ),
.O(\blk00000056/sig000001e0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000075 (
.I0(sig00000040),
.I1(sig00000035),
.O(\blk00000056/sig000001df )
);
XORCY \blk00000056/blk00000074 (
.CI(\blk00000056/sig000001dc ),
.LI(\blk00000056/sig000001dd ),
.O(sig0000001d)
);
MUXCY \blk00000056/blk00000073 (
.CI(\blk00000056/sig000001dc ),
.DI(sig0000003f),
.S(\blk00000056/sig000001dd ),
.O(\blk00000056/sig000001de )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000072 (
.I0(sig0000003f),
.I1(sig00000035),
.O(\blk00000056/sig000001dd )
);
XORCY \blk00000056/blk00000071 (
.CI(\blk00000056/sig000001da ),
.LI(\blk00000056/sig000001db ),
.O(sig0000001c)
);
MUXCY \blk00000056/blk00000070 (
.CI(\blk00000056/sig000001da ),
.DI(sig0000003e),
.S(\blk00000056/sig000001db ),
.O(\blk00000056/sig000001dc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000006f (
.I0(sig0000003e),
.I1(sig00000035),
.O(\blk00000056/sig000001db )
);
XORCY \blk00000056/blk0000006e (
.CI(\blk00000056/sig000001d8 ),
.LI(\blk00000056/sig000001d9 ),
.O(sig0000001b)
);
MUXCY \blk00000056/blk0000006d (
.CI(\blk00000056/sig000001d8 ),
.DI(sig0000003d),
.S(\blk00000056/sig000001d9 ),
.O(\blk00000056/sig000001da )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000006c (
.I0(sig0000003d),
.I1(sig00000035),
.O(\blk00000056/sig000001d9 )
);
XORCY \blk00000056/blk0000006b (
.CI(\blk00000056/sig000001d6 ),
.LI(\blk00000056/sig000001d7 ),
.O(sig0000001a)
);
MUXCY \blk00000056/blk0000006a (
.CI(\blk00000056/sig000001d6 ),
.DI(sig0000003c),
.S(\blk00000056/sig000001d7 ),
.O(\blk00000056/sig000001d8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000069 (
.I0(sig0000003c),
.I1(sig00000035),
.O(\blk00000056/sig000001d7 )
);
XORCY \blk00000056/blk00000068 (
.CI(\blk00000056/sig000001d4 ),
.LI(\blk00000056/sig000001d5 ),
.O(sig00000019)
);
MUXCY \blk00000056/blk00000067 (
.CI(\blk00000056/sig000001d4 ),
.DI(sig0000003b),
.S(\blk00000056/sig000001d5 ),
.O(\blk00000056/sig000001d6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000066 (
.I0(sig0000003b),
.I1(sig00000035),
.O(\blk00000056/sig000001d5 )
);
XORCY \blk00000056/blk00000065 (
.CI(\blk00000056/sig000001d2 ),
.LI(\blk00000056/sig000001d3 ),
.O(sig00000018)
);
MUXCY \blk00000056/blk00000064 (
.CI(\blk00000056/sig000001d2 ),
.DI(sig0000003a),
.S(\blk00000056/sig000001d3 ),
.O(\blk00000056/sig000001d4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000063 (
.I0(sig0000003a),
.I1(sig00000035),
.O(\blk00000056/sig000001d3 )
);
XORCY \blk00000056/blk00000062 (
.CI(\blk00000056/sig000001d0 ),
.LI(\blk00000056/sig000001d1 ),
.O(sig00000017)
);
MUXCY \blk00000056/blk00000061 (
.CI(\blk00000056/sig000001d0 ),
.DI(sig00000039),
.S(\blk00000056/sig000001d1 ),
.O(\blk00000056/sig000001d2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000060 (
.I0(sig00000039),
.I1(sig00000035),
.O(\blk00000056/sig000001d1 )
);
XORCY \blk00000056/blk0000005f (
.CI(\blk00000056/sig000001ce ),
.LI(\blk00000056/sig000001cf ),
.O(sig00000016)
);
MUXCY \blk00000056/blk0000005e (
.CI(\blk00000056/sig000001ce ),
.DI(sig00000038),
.S(\blk00000056/sig000001cf ),
.O(\blk00000056/sig000001d0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000005d (
.I0(sig00000038),
.I1(sig00000035),
.O(\blk00000056/sig000001cf )
);
XORCY \blk00000056/blk0000005c (
.CI(\blk00000056/sig000001cc ),
.LI(\blk00000056/sig000001cd ),
.O(sig00000015)
);
MUXCY \blk00000056/blk0000005b (
.CI(\blk00000056/sig000001cc ),
.DI(sig00000037),
.S(\blk00000056/sig000001cd ),
.O(\blk00000056/sig000001ce )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk0000005a (
.I0(sig00000037),
.I1(sig00000034),
.O(\blk00000056/sig000001cd )
);
XORCY \blk00000056/blk00000059 (
.CI(sig00000002),
.LI(\blk00000056/sig000001cb ),
.O(sig00000014)
);
MUXCY \blk00000056/blk00000058 (
.CI(sig00000002),
.DI(sig00000036),
.S(\blk00000056/sig000001cb ),
.O(\blk00000056/sig000001cc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000056/blk00000057 (
.I0(sig00000036),
.I1(sig00000033),
.O(\blk00000056/sig000001cb )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk0000009b (
.I0(\blk00000087/sig000001f1 ),
.I1(\blk00000087/sig000001f0 ),
.O(\blk00000087/sig000001ff )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000087/blk0000009a (
.I0(sig00000033),
.I1(\blk00000087/sig000001f1 ),
.I2(\blk00000087/sig000001f0 ),
.O(\blk00000087/sig000001f8 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000099 (
.I0(\blk00000087/sig000001ef ),
.I1(\blk00000087/sig000001ee ),
.O(\blk00000087/sig000001fe )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000087/blk00000098 (
.I0(sig00000034),
.I1(\blk00000087/sig000001ef ),
.I2(\blk00000087/sig000001ee ),
.O(\blk00000087/sig000001f7 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000097 (
.I0(\blk00000087/sig000001ec ),
.I1(\blk00000087/sig000001ed ),
.O(\blk00000087/sig000001fd )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000087/blk00000096 (
.I0(sig00000035),
.I1(\blk00000087/sig000001ec ),
.I2(\blk00000087/sig000001ed ),
.O(\blk00000087/sig000001f6 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000095 (
.I0(sig00000033),
.I1(\blk00000087/sig000001f2 ),
.O(\blk00000087/sig000001fc )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000094 (
.I0(sig00000035),
.I1(\blk00000087/sig000001ef ),
.O(\blk00000087/sig000001fa )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000093 (
.I0(\blk00000087/sig000001f2 ),
.I1(\blk00000087/sig000001ed ),
.O(\blk00000087/sig000001f9 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000087/blk00000092 (
.I0(sig00000034),
.I1(\blk00000087/sig000001f1 ),
.O(\blk00000087/sig000001fb )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk00000091 (
.C(clk),
.D(\blk00000087/sig000001fd ),
.Q(\blk00000087/sig000001ec )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk00000090 (
.C(clk),
.D(\blk00000087/sig000001fe ),
.Q(\blk00000087/sig000001ee )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008f (
.C(clk),
.D(\blk00000087/sig000001ff ),
.Q(\blk00000087/sig000001f0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008e (
.C(clk),
.D(\blk00000087/sig000001f9 ),
.Q(\blk00000087/sig000001ed )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008d (
.C(clk),
.D(\blk00000087/sig000001fa ),
.Q(\blk00000087/sig000001ef )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008c (
.C(clk),
.D(\blk00000087/sig000001fb ),
.Q(\blk00000087/sig000001f1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008b (
.C(clk),
.D(\blk00000087/sig000001fc ),
.Q(\blk00000087/sig000001f2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk0000008a (
.C(clk),
.D(\blk00000087/sig000001f6 ),
.Q(sig00000035)
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk00000089 (
.C(clk),
.D(\blk00000087/sig000001f7 ),
.Q(sig00000034)
);
FD #(
.INIT ( 1'b0 ))
\blk00000087/blk00000088 (
.C(clk),
.D(\blk00000087/sig000001f8 ),
.Q(sig00000033)
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
module tb_m_elink_stub;
reg [1:0] elink_txrr_packet;
reg elink_txi_wr_wait_p;
wire elink_txo_lclk_p;
wire elink_txo_frame_n;
wire elink_rx_lclk_pll;
wire elink_rxwr_access;
reg elink_rxrd_wait;
wire elink_txrd_wait;
wire elink_mailbox_full;
reg elink_rx_ref_clk;
reg elink_tx_lclk;
reg elink_txwr_access;
wire elink_txo_lclk_n;
wire [1:0] elink_rxrr_packet;
wire elink_txrr_wait;
reg elink_rxi_frame_n;
reg [7:0] elink_rxi_data_n;
reg elink_txi_rd_wait_p;
reg elink_txrr_access;
reg elink_sys_clk;
reg [1:0] elink_txrd_packet;
reg elink_txi_rd_wait_n;
reg elink_tx_lclk90;
reg elink_rx_lclk;
reg elink_rxi_frame_p;
wire [7:0] elink_txo_data_n;
reg elink_txrd_access;
wire elink_rxo_rd_wait_p;
reg elink_rxrr_wait;
wire [1:0] elink_rxwr_packet;
wire elink_rxo_rd_wait_n;
wire elink_mailbox_not_empty;
reg elink_txi_wr_wait_n;
wire elink_rxrr_access;
wire elink_txwr_wait;
reg [1:0] elink_txwr_packet;
wire [7:0] elink_txo_data_p;
wire elink_txo_frame_p;
reg elink_reset;
reg elink_rxwr_wait;
wire [1:0] elink_rxrd_packet;
reg elink_rxi_lclk_p;
wire elink_rxo_wr_wait_p;
wire [11:0] elink_chipid;
reg elink_tx_lclk_div4;
wire elink_rxrd_access;
reg [7:0] elink_rxi_data_p;
reg elink_rx_lclk_div4;
wire elink_elink_en;
wire elink_timeout;
wire elink_rxo_wr_wait_n;
reg elink_rxi_lclk_n;
initial begin
$from_myhdl(
elink_txrr_packet,
elink_txi_wr_wait_p,
elink_rxrd_wait,
elink_rx_ref_clk,
elink_tx_lclk,
elink_txwr_access,
elink_rxi_frame_n,
elink_rxi_data_n,
elink_txi_rd_wait_p,
elink_txrr_access,
elink_sys_clk,
elink_txrd_packet,
elink_txi_rd_wait_n,
elink_tx_lclk90,
elink_rx_lclk,
elink_rxi_frame_p,
elink_txrd_access,
elink_rxrr_wait,
elink_txi_wr_wait_n,
elink_txwr_packet,
elink_reset,
elink_rxwr_wait,
elink_rxi_lclk_p,
elink_tx_lclk_div4,
elink_rxi_data_p,
elink_rx_lclk_div4,
elink_rxi_lclk_n
);
$to_myhdl(
elink_txo_lclk_p,
elink_txo_frame_n,
elink_rx_lclk_pll,
elink_rxwr_access,
elink_txrd_wait,
elink_mailbox_full,
elink_txo_lclk_n,
elink_rxrr_packet,
elink_txrr_wait,
elink_txo_data_n,
elink_rxo_rd_wait_p,
elink_rxwr_packet,
elink_rxo_rd_wait_n,
elink_mailbox_not_empty,
elink_rxrr_access,
elink_txwr_wait,
elink_txo_data_p,
elink_txo_frame_p,
elink_rxrd_packet,
elink_rxo_wr_wait_p,
elink_chipid,
elink_rxrd_access,
elink_elink_en,
elink_timeout,
elink_rxo_wr_wait_n
);
end
m_elink_stub dut(
elink_txrr_packet,
elink_txi_wr_wait_p,
elink_txo_lclk_p,
elink_txo_frame_n,
elink_rx_lclk_pll,
elink_rxwr_access,
elink_rxrd_wait,
elink_txrd_wait,
elink_mailbox_full,
elink_rx_ref_clk,
elink_tx_lclk,
elink_txwr_access,
elink_txo_lclk_n,
elink_rxrr_packet,
elink_txrr_wait,
elink_rxi_frame_n,
elink_rxi_data_n,
elink_txi_rd_wait_p,
elink_txrr_access,
elink_sys_clk,
elink_txrd_packet,
elink_txi_rd_wait_n,
elink_tx_lclk90,
elink_rx_lclk,
elink_rxi_frame_p,
elink_txo_data_n,
elink_txrd_access,
elink_rxo_rd_wait_p,
elink_rxrr_wait,
elink_rxwr_packet,
elink_rxo_rd_wait_n,
elink_mailbox_not_empty,
elink_txi_wr_wait_n,
elink_rxrr_access,
elink_txwr_wait,
elink_txwr_packet,
elink_txo_data_p,
elink_txo_frame_p,
elink_reset,
elink_rxwr_wait,
elink_rxrd_packet,
elink_rxi_lclk_p,
elink_rxo_wr_wait_p,
elink_chipid,
elink_tx_lclk_div4,
elink_rxrd_access,
elink_rxi_data_p,
elink_rx_lclk_div4,
elink_elink_en,
elink_timeout,
elink_rxo_wr_wait_n,
elink_rxi_lclk_n
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR3_BLACKBOX_V
`define SKY130_FD_SC_HDLL__XNOR3_BLACKBOX_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__xnor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR3_BLACKBOX_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: afifo_32x256.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module afifo_32x256 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [31:0] sub_wire1;
wire sub_wire2;
wire [7:0] sub_wire3;
wire wrfull = sub_wire0;
wire [31:0] q = sub_wire1[31:0];
wire rdempty = sub_wire2;
wire [7:0] wrusedw = sub_wire3[7:0];
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.wrusedw (sub_wire3),
.rdfull (),
.rdusedw (),
.wrempty ());
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL "wrusedw[7..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL afifo_32x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL afifo_32x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL afifo_32x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL afifo_32x256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL afifo_32x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL afifo_32x256_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
(* Copyright (c) 2008-2012, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import List.
Require Import CpdtTactics MoreSpecif.
Set Implicit Arguments.
(* end hide *)
(** %\chapter{Proof by Reflection}% *)
(** The last chapter highlighted a very heuristic approach to proving. In this chapter, we will study an alternative technique,%\index{proof by reflection}% _proof by reflection_ %\cite{reflection}%. We will write, in Gallina, decision procedures with proofs of correctness, and we will appeal to these procedures in writing very short proofs. Such a proof is checked by running the decision procedure. The term _reflection_ applies because we will need to translate Gallina propositions into values of inductive types representing syntax, so that Gallina programs may analyze them, and translating such a term back to the original form is called _reflecting_ it. *)
(** * Proving Evenness *)
(** Proving that particular natural number constants are even is certainly something we would rather have happen automatically. The Ltac-programming techniques that we learned in the last chapter make it easy to implement such a procedure. *)
Inductive isEven : nat -> Prop :=
| Even_O : isEven O
| Even_SS : forall n, isEven n -> isEven (S (S n)).
(* begin thide *)
Ltac prove_even := repeat constructor.
(* end thide *)
Theorem even_256 : isEven 256.
prove_even.
Qed.
Print even_256.
(** %\vspace{-.15in}% [[
even_256 =
Even_SS
(Even_SS
(Even_SS
(Even_SS
]]
%\noindent%...and so on. This procedure always works (at least on machines with infinite resources), but it has a serious drawback, which we see when we print the proof it generates that 256 is even. The final proof term has length super-linear in the input value. Coq's implicit arguments mechanism is hiding the values given for parameter [n] of [Even_SS], which is why the proof term only appears linear here. Also, proof terms are represented internally as syntax trees, with opportunity for sharing of node representations, but in this chapter we will measure proof term size as simple textual length or as the number of nodes in the term's syntax tree, two measures that are approximately equivalent. Sometimes apparently large proof terms have enough internal sharing that they take up less memory than we expect, but one avoids having to reason about such sharing by ensuring that the size of a sharing-free version of a term is low enough.
Superlinear evenness proof terms seem like a shame, since we could write a trivial and trustworthy program to verify evenness of constants. The proof checker could simply call our program where needed.
It is also unfortunate not to have static typing guarantees that our tactic always behaves appropriately. Other invocations of similar tactics might fail with dynamic type errors, and we would not know about the bugs behind these errors until we happened to attempt to prove complex enough goals.
The techniques of proof by reflection address both complaints. We will be able to write proofs like in the example above with constant size overhead beyond the size of the input, and we will do it with verified decision procedures written in Gallina.
For this example, we begin by using a type from the [MoreSpecif] module (included in the book source) to write a certified evenness checker. *)
(* begin hide *)
(* begin thide *)
Definition paartial := partial.
(* end thide *)
(* end hide *)
Print partial.
(** %\vspace{-.15in}% [[
Inductive partial (P : Prop) : Set := Proved : P -> [P] | Uncertain : [P]
]]
A [partial P] value is an optional proof of [P]. The notation [[P]] stands for [partial P]. *)
Local Open Scope partial_scope.
(** We bring into scope some notations for the [partial] type. These overlap with some of the notations we have seen previously for specification types, so they were placed in a separate scope that needs separate opening. *)
(* begin thide *)
Definition check_even : forall n : nat, [isEven n].
Hint Constructors isEven.
refine (fix F (n : nat) : [isEven n] :=
match n with
| 0 => Yes
| 1 => No
| S (S n') => Reduce (F n')
end); auto.
Defined.
(** The function [check_even] may be viewed as a _verified decision procedure_, because its type guarantees that it never returns %\coqdocnotation{%#<tt>#Yes#</tt>#%}% for inputs that are not even.
Now we can use dependent pattern-matching to write a function that performs a surprising feat. When given a [partial P], this function [partialOut] returns a proof of [P] if the [partial] value contains a proof, and it returns a (useless) proof of [True] otherwise. From the standpoint of ML and Haskell programming, it seems impossible to write such a type, but it is trivial with a [return] annotation. *)
Definition partialOut (P : Prop) (x : [P]) :=
match x return (match x with
| Proved _ => P
| Uncertain => True
end) with
| Proved pf => pf
| Uncertain => I
end.
(** It may seem strange to define a function like this. However, it turns out to be very useful in writing a reflective version of our earlier [prove_even] tactic: *)
Ltac prove_even_reflective :=
match goal with
| [ |- isEven ?N] => exact (partialOut (check_even N))
end.
(* end thide *)
(** We identify which natural number we are considering, and we "prove" its evenness by pulling the proof out of the appropriate [check_even] call. Recall that the %\index{tactics!exact}%[exact] tactic proves a proposition [P] when given a proof term of precisely type [P]. *)
Theorem even_256' : isEven 256.
prove_even_reflective.
Qed.
Print even_256'.
(** %\vspace{-.15in}% [[
even_256' = partialOut (check_even 256)
: isEven 256
]]
We can see a constant wrapper around the object of the proof. For any even number, this form of proof will suffice. The size of the proof term is now linear in the number being checked, containing two repetitions of the unary form of that number, one of which is hidden above within the implicit argument to [partialOut].
What happens if we try the tactic with an odd number? *)
Theorem even_255 : isEven 255.
(** %\vspace{-.275in}%[[
prove_even_reflective.
]]
<<
User error: No matching clauses for match goal
>>
Thankfully, the tactic fails. To see more precisely what goes wrong, we can run manually the body of the [match].
%\vspace{-.15in}%[[
exact (partialOut (check_even 255)).
]]
<<
Error: The term "partialOut (check_even 255)" has type
"match check_even 255 with
| Yes => isEven 255
| No => True
end" while it is expected to have type "isEven 255"
>>
As usual, the type checker performs no reductions to simplify error messages. If we reduced the first term ourselves, we would see that [check_even 255] reduces to a %\coqdocnotation{%#<tt>#No#</tt>#%}%, so that the first term is equivalent to [True], which certainly does not unify with [isEven 255]. *)
Abort.
(** Our tactic [prove_even_reflective] is reflective because it performs a proof search process (a trivial one, in this case) wholly within Gallina, where the only use of Ltac is to translate a goal into an appropriate use of [check_even]. *)
(** * Reifying the Syntax of a Trivial Tautology Language *)
(** We might also like to have reflective proofs of trivial tautologies like this one: *)
Theorem true_galore : (True /\ True) -> (True \/ (True /\ (True -> True))).
tauto.
Qed.
(* begin hide *)
(* begin thide *)
Definition tg := (and_ind, or_introl).
(* end thide *)
(* end hide *)
Print true_galore.
(** %\vspace{-.15in}% [[
true_galore =
fun H : True /\ True =>
and_ind (fun _ _ : True => or_introl (True /\ (True -> True)) I) H
: True /\ True -> True \/ True /\ (True -> True)
]]
As we might expect, the proof that [tauto] builds contains explicit applications of natural deduction rules. For large formulas, this can add a linear amount of proof size overhead, beyond the size of the input.
To write a reflective procedure for this class of goals, we will need to get into the actual "reflection" part of "proof by reflection." It is impossible to case-analyze a [Prop] in any way in Gallina. We must%\index{reification}% _reify_ [Prop] into some type that we _can_ analyze. This inductive type is a good candidate: *)
(* begin thide *)
Inductive taut : Set :=
| TautTrue : taut
| TautAnd : taut -> taut -> taut
| TautOr : taut -> taut -> taut
| TautImp : taut -> taut -> taut.
(** We write a recursive function to _reflect_ this syntax back to [Prop]. Such functions are also called%\index{interpretation function}% _interpretation functions_, and we have used them in previous examples to give semantics to small programming languages. *)
Fixpoint tautDenote (t : taut) : Prop :=
match t with
| TautTrue => True
| TautAnd t1 t2 => tautDenote t1 /\ tautDenote t2
| TautOr t1 t2 => tautDenote t1 \/ tautDenote t2
| TautImp t1 t2 => tautDenote t1 -> tautDenote t2
end.
(** It is easy to prove that every formula in the range of [tautDenote] is true. *)
Theorem tautTrue : forall t, tautDenote t.
induction t; crush.
Qed.
(** To use [tautTrue] to prove particular formulas, we need to implement the syntax reification process. A recursive Ltac function does the job. *)
Ltac tautReify P :=
match P with
| True => TautTrue
| ?P1 /\ ?P2 =>
let t1 := tautReify P1 in
let t2 := tautReify P2 in
constr:(TautAnd t1 t2)
| ?P1 \/ ?P2 =>
let t1 := tautReify P1 in
let t2 := tautReify P2 in
constr:(TautOr t1 t2)
| ?P1 -> ?P2 =>
let t1 := tautReify P1 in
let t2 := tautReify P2 in
constr:(TautImp t1 t2)
end.
(** With [tautReify] available, it is easy to finish our reflective tactic. We look at the goal formula, reify it, and apply [tautTrue] to the reified formula. *)
Ltac obvious :=
match goal with
| [ |- ?P ] =>
let t := tautReify P in
exact (tautTrue t)
end.
(** We can verify that [obvious] solves our original example, with a proof term that does not mention details of the proof. *)
(* end thide *)
Theorem true_galore' : (True /\ True) -> (True \/ (True /\ (True -> True))).
obvious.
Qed.
Print true_galore'.
(** %\vspace{-.15in}% [[
true_galore' =
tautTrue
(TautImp (TautAnd TautTrue TautTrue)
(TautOr TautTrue (TautAnd TautTrue (TautImp TautTrue TautTrue))))
: True /\ True -> True \/ True /\ (True -> True)
]]
It is worth considering how the reflective tactic improves on a pure-Ltac implementation. The formula reification process is just as ad-hoc as before, so we gain little there. In general, proofs will be more complicated than formula translation, and the "generic proof rule" that we apply here _is_ on much better formal footing than a recursive Ltac function. The dependent type of the proof guarantees that it "works" on any input formula. This benefit is in addition to the proof-size improvement that we have already seen.
It may also be worth pointing out that our previous example of evenness testing used a function [partialOut] for sound handling of input goals that the verified decision procedure fails to prove. Here, we prove that our procedure [tautTrue] (recall that an inductive proof may be viewed as a recursive procedure) is able to prove any goal representable in [taut], so no extra step is necessary. *)
(** * A Monoid Expression Simplifier *)
(** Proof by reflection does not require encoding of all of the syntax in a goal. We can insert "variables" in our syntax types to allow injection of arbitrary pieces, even if we cannot apply specialized reasoning to them. In this section, we explore that possibility by writing a tactic for normalizing monoid equations. *)
Section monoid.
Variable A : Set.
Variable e : A.
Variable f : A -> A -> A.
Infix "+" := f.
Hypothesis assoc : forall a b c, (a + b) + c = a + (b + c).
Hypothesis identl : forall a, e + a = a.
Hypothesis identr : forall a, a + e = a.
(** We add variables and hypotheses characterizing an arbitrary instance of the algebraic structure of monoids. We have an associative binary operator and an identity element for it.
It is easy to define an expression tree type for monoid expressions. A [Var] constructor is a "catch-all" case for subexpressions that we cannot model. These subexpressions could be actual Gallina variables, or they could just use functions that our tactic is unable to understand. *)
(* begin thide *)
Inductive mexp : Set :=
| Ident : mexp
| Var : A -> mexp
| Op : mexp -> mexp -> mexp.
(** Next, we write an interpretation function. *)
Fixpoint mdenote (me : mexp) : A :=
match me with
| Ident => e
| Var v => v
| Op me1 me2 => mdenote me1 + mdenote me2
end.
(** We will normalize expressions by flattening them into lists, via associativity, so it is helpful to have a denotation function for lists of monoid values. *)
Fixpoint mldenote (ls : list A) : A :=
match ls with
| nil => e
| x :: ls' => x + mldenote ls'
end.
(** The flattening function itself is easy to implement. *)
Fixpoint flatten (me : mexp) : list A :=
match me with
| Ident => nil
| Var x => x :: nil
| Op me1 me2 => flatten me1 ++ flatten me2
end.
(** This function has a straightforward correctness proof in terms of our [denote] functions. *)
Lemma flatten_correct' : forall ml2 ml1,
mldenote ml1 + mldenote ml2 = mldenote (ml1 ++ ml2).
induction ml1; crush.
Qed.
Theorem flatten_correct : forall me, mdenote me = mldenote (flatten me).
Hint Resolve flatten_correct'.
induction me; crush.
Qed.
(** Now it is easy to prove a theorem that will be the main tool behind our simplification tactic. *)
Theorem monoid_reflect : forall me1 me2,
mldenote (flatten me1) = mldenote (flatten me2)
-> mdenote me1 = mdenote me2.
intros; repeat rewrite flatten_correct; assumption.
Qed.
(** We implement reification into the [mexp] type. *)
Ltac reify me :=
match me with
| e => Ident
| ?me1 + ?me2 =>
let r1 := reify me1 in
let r2 := reify me2 in
constr:(Op r1 r2)
| _ => constr:(Var me)
end.
(** The final [monoid] tactic works on goals that equate two monoid terms. We reify each and change the goal to refer to the reified versions, finishing off by applying [monoid_reflect] and simplifying uses of [mldenote]. Recall that the %\index{tactics!change}%[change] tactic replaces a conclusion formula with another that is definitionally equal to it. *)
Ltac monoid :=
match goal with
| [ |- ?me1 = ?me2 ] =>
let r1 := reify me1 in
let r2 := reify me2 in
change (mdenote r1 = mdenote r2);
apply monoid_reflect; simpl
end.
(** We can make short work of theorems like this one: *)
(* end thide *)
Theorem t1 : forall a b c d, a + b + c + d = a + (b + c) + d.
intros; monoid.
(** [[
============================
a + (b + (c + (d + e))) = a + (b + (c + (d + e)))
]]
Our tactic has canonicalized both sides of the equality, such that we can finish the proof by reflexivity. *)
reflexivity.
Qed.
(** It is interesting to look at the form of the proof. *)
Print t1.
(** %\vspace{-.15in}% [[
t1 =
fun a b c d : A =>
monoid_reflect (Op (Op (Op (Var a) (Var b)) (Var c)) (Var d))
(Op (Op (Var a) (Op (Var b) (Var c))) (Var d))
(eq_refl (a + (b + (c + (d + e)))))
: forall a b c d : A, a + b + c + d = a + (b + c) + d
]]
The proof term contains only restatements of the equality operands in reified form, followed by a use of reflexivity on the shared canonical form. *)
End monoid.
(** Extensions of this basic approach are used in the implementations of the %\index{tactics!ring}%[ring] and %\index{tactics!field}%[field] tactics that come packaged with Coq. *)
(** * A Smarter Tautology Solver *)
(** Now we are ready to revisit our earlier tautology solver example. We want to broaden the scope of the tactic to include formulas whose truth is not syntactically apparent. We will want to allow injection of arbitrary formulas, like we allowed arbitrary monoid expressions in the last example. Since we are working in a richer theory, it is important to be able to use equalities between different injected formulas. For instance, we cannot prove [P -> P] by translating the formula into a value like [Imp (Var P) (Var P)], because a Gallina function has no way of comparing the two [P]s for equality.
To arrive at a nice implementation satisfying these criteria, we introduce the %\index{tactics!quote}%[quote] tactic and its associated library. *)
Require Import Quote.
(* begin thide *)
Inductive formula : Set :=
| Atomic : index -> formula
| Truth : formula
| Falsehood : formula
| And : formula -> formula -> formula
| Or : formula -> formula -> formula
| Imp : formula -> formula -> formula.
(* end thide *)
(** The type %\index{Gallina terms!index}%[index] comes from the [Quote] library and represents a countable variable type. The rest of [formula]'s definition should be old hat by now.
The [quote] tactic will implement injection from [Prop] into [formula] for us, but it is not quite as smart as we might like. In particular, it wants to treat function types specially, so it gets confused if function types are part of the structure we want to encode syntactically. To trick [quote] into not noticing our uses of function types to express logical implication, we will need to declare a wrapper definition for implication, as we did in the last chapter. *)
Definition imp (P1 P2 : Prop) := P1 -> P2.
Infix "-->" := imp (no associativity, at level 95).
(** Now we can define our denotation function. *)
Definition asgn := varmap Prop.
(* begin thide *)
Fixpoint formulaDenote (atomics : asgn) (f : formula) : Prop :=
match f with
| Atomic v => varmap_find False v atomics
| Truth => True
| Falsehood => False
| And f1 f2 => formulaDenote atomics f1 /\ formulaDenote atomics f2
| Or f1 f2 => formulaDenote atomics f1 \/ formulaDenote atomics f2
| Imp f1 f2 => formulaDenote atomics f1 --> formulaDenote atomics f2
end.
(* end thide *)
(** The %\index{Gallina terms!varmap}%[varmap] type family implements maps from [index] values. In this case, we define an assignment as a map from variables to [Prop]s. Our interpretation function [formulaDenote] works with an assignment, and we use the [varmap_find] function to consult the assignment in the [Atomic] case. The first argument to [varmap_find] is a default value, in case the variable is not found. *)
Section my_tauto.
Variable atomics : asgn.
Definition holds (v : index) := varmap_find False v atomics.
(** We define some shorthand for a particular variable being true, and now we are ready to define some helpful functions based on the [ListSet] module of the standard library, which (unsurprisingly) presents a view of lists as sets. *)
Require Import ListSet.
Definition index_eq : forall x y : index, {x = y} + {x <> y}.
decide equality.
Defined.
Definition add (s : set index) (v : index) := set_add index_eq v s.
Definition In_dec : forall v (s : set index), {In v s} + {~ In v s}.
Local Open Scope specif_scope.
intro; refine (fix F (s : set index) : {In v s} + {~ In v s} :=
match s with
| nil => No
| v' :: s' => index_eq v' v || F s'
end); crush.
Defined.
(** We define what it means for all members of an index set to represent true propositions, and we prove some lemmas about this notion. *)
Fixpoint allTrue (s : set index) : Prop :=
match s with
| nil => True
| v :: s' => holds v /\ allTrue s'
end.
Theorem allTrue_add : forall v s,
allTrue s
-> holds v
-> allTrue (add s v).
induction s; crush;
match goal with
| [ |- context[if ?E then _ else _] ] => destruct E
end; crush.
Qed.
Theorem allTrue_In : forall v s,
allTrue s
-> set_In v s
-> varmap_find False v atomics.
induction s; crush.
Qed.
Hint Resolve allTrue_add allTrue_In.
Local Open Scope partial_scope.
(** Now we can write a function [forward] that implements deconstruction of hypotheses, expanding a compound formula into a set of sets of atomic formulas covering all possible cases introduced with use of [Or]. To handle consideration of multiple cases, the function takes in a continuation argument, which will be called once for each case.
The [forward] function has a dependent type, in the style of Chapter 6, guaranteeing correctness. The arguments to [forward] are a goal formula [f], a set [known] of atomic formulas that we may assume are true, a hypothesis formula [hyp], and a success continuation [cont] that we call when we have extended [known] to hold new truths implied by [hyp]. *)
Definition forward : forall (f : formula) (known : set index) (hyp : formula)
(cont : forall known', [allTrue known' -> formulaDenote atomics f]),
[allTrue known -> formulaDenote atomics hyp -> formulaDenote atomics f].
refine (fix F (f : formula) (known : set index) (hyp : formula)
(cont : forall known', [allTrue known' -> formulaDenote atomics f])
: [allTrue known -> formulaDenote atomics hyp -> formulaDenote atomics f] :=
match hyp with
| Atomic v => Reduce (cont (add known v))
| Truth => Reduce (cont known)
| Falsehood => Yes
| And h1 h2 =>
Reduce (F (Imp h2 f) known h1 (fun known' =>
Reduce (F f known' h2 cont)))
| Or h1 h2 => F f known h1 cont && F f known h2 cont
| Imp _ _ => Reduce (cont known)
end); crush.
Defined.
(** A [backward] function implements analysis of the final goal. It calls [forward] to handle implications. *)
(* begin thide *)
Definition backward : forall (known : set index) (f : formula),
[allTrue known -> formulaDenote atomics f].
refine (fix F (known : set index) (f : formula)
: [allTrue known -> formulaDenote atomics f] :=
match f with
| Atomic v => Reduce (In_dec v known)
| Truth => Yes
| Falsehood => No
| And f1 f2 => F known f1 && F known f2
| Or f1 f2 => F known f1 || F known f2
| Imp f1 f2 => forward f2 known f1 (fun known' => F known' f2)
end); crush; eauto.
Defined.
(* end thide *)
(** A simple wrapper around [backward] gives us the usual type of a partial decision procedure. *)
Definition my_tauto : forall f : formula, [formulaDenote atomics f].
(* begin thide *)
intro; refine (Reduce (backward nil f)); crush.
Defined.
(* end thide *)
End my_tauto.
(** Our final tactic implementation is now fairly straightforward. First, we [intro] all quantifiers that do not bind [Prop]s. Then we call the [quote] tactic, which implements the reification for us. Finally, we are able to construct an exact proof via [partialOut] and the [my_tauto] Gallina function. *)
Ltac my_tauto :=
repeat match goal with
| [ |- forall x : ?P, _ ] =>
match type of P with
| Prop => fail 1
| _ => intro
end
end;
quote formulaDenote;
match goal with
| [ |- formulaDenote ?m ?f ] => exact (partialOut (my_tauto m f))
end.
(* end thide *)
(** A few examples demonstrate how the tactic works. *)
Theorem mt1 : True.
my_tauto.
Qed.
Print mt1.
(** %\vspace{-.15in}% [[
mt1 = partialOut (my_tauto (Empty_vm Prop) Truth)
: True
]]
We see [my_tauto] applied with an empty [varmap], since every subformula is handled by [formulaDenote]. *)
Theorem mt2 : forall x y : nat, x = y --> x = y.
my_tauto.
Qed.
(* begin hide *)
(* begin thide *)
Definition nvm := (Node_vm, Empty_vm, End_idx, Left_idx, Right_idx).
(* end thide *)
(* end hide *)
Print mt2.
(** %\vspace{-.15in}% [[
mt2 =
fun x y : nat =>
partialOut
(my_tauto (Node_vm (x = y) (Empty_vm Prop) (Empty_vm Prop))
(Imp (Atomic End_idx) (Atomic End_idx)))
: forall x y : nat, x = y --> x = y
]]
Crucially, both instances of [x = y] are represented with the same index, [End_idx]. The value of this index only needs to appear once in the [varmap], whose form reveals that [varmap]s are represented as binary trees, where [index] values denote paths from tree roots to leaves. *)
Theorem mt3 : forall x y z,
(x < y /\ y > z) \/ (y > z /\ x < S y)
--> y > z /\ (x < y \/ x < S y).
my_tauto.
Qed.
Print mt3.
(** %\vspace{-.15in}% [[
fun x y z : nat =>
partialOut
(my_tauto
(Node_vm (x < S y) (Node_vm (x < y) (Empty_vm Prop) (Empty_vm Prop))
(Node_vm (y > z) (Empty_vm Prop) (Empty_vm Prop)))
(Imp
(Or (And (Atomic (Left_idx End_idx)) (Atomic (Right_idx End_idx)))
(And (Atomic (Right_idx End_idx)) (Atomic End_idx)))
(And (Atomic (Right_idx End_idx))
(Or (Atomic (Left_idx End_idx)) (Atomic End_idx)))))
: forall x y z : nat,
x < y /\ y > z \/ y > z /\ x < S y --> y > z /\ (x < y \/ x < S y)
]]
Our goal contained three distinct atomic formulas, and we see that a three-element [varmap] is generated.
It can be interesting to observe differences between the level of repetition in proof terms generated by [my_tauto] and [tauto] for especially trivial theorems. *)
Theorem mt4 : True /\ True /\ True /\ True /\ True /\ True /\ False --> False.
my_tauto.
Qed.
Print mt4.
(** %\vspace{-.15in}% [[
mt4 =
partialOut
(my_tauto (Empty_vm Prop)
(Imp
(And Truth
(And Truth
(And Truth (And Truth (And Truth (And Truth Falsehood))))))
Falsehood))
: True /\ True /\ True /\ True /\ True /\ True /\ False --> False
]]
*)
Theorem mt4' : True /\ True /\ True /\ True /\ True /\ True /\ False -> False.
tauto.
Qed.
(* begin hide *)
(* begin thide *)
Definition fi := False_ind.
(* end thide *)
(* end hide *)
Print mt4'.
(** %\vspace{-.15in}% [[
mt4' =
fun H : True /\ True /\ True /\ True /\ True /\ True /\ False =>
and_ind
(fun (_ : True) (H1 : True /\ True /\ True /\ True /\ True /\ False) =>
and_ind
(fun (_ : True) (H3 : True /\ True /\ True /\ True /\ False) =>
and_ind
(fun (_ : True) (H5 : True /\ True /\ True /\ False) =>
and_ind
(fun (_ : True) (H7 : True /\ True /\ False) =>
and_ind
(fun (_ : True) (H9 : True /\ False) =>
and_ind (fun (_ : True) (H11 : False) => False_ind False H11)
H9) H7) H5) H3) H1) H
: True /\ True /\ True /\ True /\ True /\ True /\ False -> False
]]
The traditional [tauto] tactic introduces a quadratic blow-up in the size of the proof term, whereas proofs produced by [my_tauto] always have linear size. *)
(** ** Manual Reification of Terms with Variables *)
(* begin thide *)
(** The action of the [quote] tactic above may seem like magic. Somehow it performs equality comparison between subterms of arbitrary types, so that these subterms may be represented with the same reified variable. While [quote] is implemented in OCaml, we can code the reification process completely in Ltac, as well. To make our job simpler, we will represent variables as [nat]s, indexing into a simple list of variable values that may be referenced.
Step one of the process is to crawl over a term, building a duplicate-free list of all values that appear in positions we will encode as variables. A useful helper function adds an element to a list, preventing duplicates. Note how we use Ltac pattern matching to implement an equality test on Gallina terms; this is simple syntactic equality, not even the richer definitional equality. We also represent lists as nested tuples, to allow different list elements to have different Gallina types. *)
Ltac inList x xs :=
match xs with
| tt => false
| (x, _) => true
| (_, ?xs') => inList x xs'
end.
Ltac addToList x xs :=
let b := inList x xs in
match b with
| true => xs
| false => constr:(x, xs)
end.
(** Now we can write our recursive function to calculate the list of variable values we will want to use to represent a term. *)
Ltac allVars xs e :=
match e with
| True => xs
| False => xs
| ?e1 /\ ?e2 =>
let xs := allVars xs e1 in
allVars xs e2
| ?e1 \/ ?e2 =>
let xs := allVars xs e1 in
allVars xs e2
| ?e1 -> ?e2 =>
let xs := allVars xs e1 in
allVars xs e2
| _ => addToList e xs
end.
(** We will also need a way to map a value to its position in a list. *)
Ltac lookup x xs :=
match xs with
| (x, _) => O
| (_, ?xs') =>
let n := lookup x xs' in
constr:(S n)
end.
(** The next building block is a procedure for reifying a term, given a list of all allowed variable values. We are free to make this procedure partial, where tactic failure may be triggered upon attempting to reify a term containing subterms not included in the list of variables. The type of the output term is a copy of [formula] where [index] is replaced by [nat], in the type of the constructor for atomic formulas. *)
Inductive formula' : Set :=
| Atomic' : nat -> formula'
| Truth' : formula'
| Falsehood' : formula'
| And' : formula' -> formula' -> formula'
| Or' : formula' -> formula' -> formula'
| Imp' : formula' -> formula' -> formula'.
(** Note that, when we write our own Ltac procedure, we can work directly with the normal [->] operator, rather than needing to introduce a wrapper for it. *)
Ltac reifyTerm xs e :=
match e with
| True => constr:Truth'
| False => constr:Falsehood'
| ?e1 /\ ?e2 =>
let p1 := reifyTerm xs e1 in
let p2 := reifyTerm xs e2 in
constr:(And' p1 p2)
| ?e1 \/ ?e2 =>
let p1 := reifyTerm xs e1 in
let p2 := reifyTerm xs e2 in
constr:(Or' p1 p2)
| ?e1 -> ?e2 =>
let p1 := reifyTerm xs e1 in
let p2 := reifyTerm xs e2 in
constr:(Imp' p1 p2)
| _ =>
let n := lookup e xs in
constr:(Atomic' n)
end.
(** Finally, we bring all the pieces together. *)
Ltac reify :=
match goal with
| [ |- ?G ] => let xs := allVars tt G in
let p := reifyTerm xs G in
pose p
end.
(** A quick test verifies that we are doing reification correctly. *)
Theorem mt3' : forall x y z,
(x < y /\ y > z) \/ (y > z /\ x < S y)
-> y > z /\ (x < y \/ x < S y).
do 3 intro; reify.
(** Our simple tactic adds the translated term as a new variable:
[[
f := Imp'
(Or' (And' (Atomic' 2) (Atomic' 1)) (And' (Atomic' 1) (Atomic' 0)))
(And' (Atomic' 1) (Or' (Atomic' 2) (Atomic' 0))) : formula'
]]
*)
Abort.
(** More work would be needed to complete the reflective tactic, as we must connect our new syntax type with the real meanings of formulas, but the details are the same as in our prior implementation with [quote]. *)
(* end thide *)
(** * Building a Reification Tactic that Recurses Under Binders *)
(** All of our examples so far have stayed away from reifying the syntax of terms that use such features as quantifiers and [fun] function abstractions. Such cases are complicated by the fact that different subterms may be allowed to reference different sets of free variables. Some cleverness is needed to clear this hurdle, but a few simple patterns will suffice. Consider this example of a simple dependently typed term language, where a function abstraction body is represented conveniently with a Coq function. *)
Inductive type : Type :=
| Nat : type
| NatFunc : type -> type.
Inductive term : type -> Type :=
| Const : nat -> term Nat
| Plus : term Nat -> term Nat -> term Nat
| Abs : forall t, (nat -> term t) -> term (NatFunc t).
Fixpoint typeDenote (t : type) : Type :=
match t with
| Nat => nat
| NatFunc t => nat -> typeDenote t
end.
Fixpoint termDenote t (e : term t) : typeDenote t :=
match e with
| Const n => n
| Plus e1 e2 => termDenote e1 + termDenote e2
| Abs _ e1 => fun x => termDenote (e1 x)
end.
(** Here is a %\%naive%{}% first attempt at a reification tactic. *)
Ltac refl' e :=
match e with
| ?E1 + ?E2 =>
let r1 := refl' E1 in
let r2 := refl' E2 in
constr:(Plus r1 r2)
| fun x : nat => ?E1 =>
let r1 := refl' E1 in
constr:(Abs (fun x => r1 x))
| _ => constr:(Const e)
end.
(** Recall that a regular Ltac pattern variable [?X] only matches terms that _do not mention new variables introduced within the pattern_. In our %\%naive%{}% implementation, the case for matching function abstractions matches the function body in a way that prevents it from mentioning the function argument! Our code above plays fast and loose with the function body in a way that leads to independent problems, but we could change the code so that it indeed handles function abstractions that ignore their arguments.
To handle functions in general, we will use the pattern variable form [@?X], which allows [X] to mention newly introduced variables that are declared explicitly. A use of [@?X] must be followed by a list of the local variables that may be mentioned. The variable [X] then comes to stand for a Gallina function over the values of those variables. For instance: *)
Reset refl'.
Ltac refl' e :=
match e with
| ?E1 + ?E2 =>
let r1 := refl' E1 in
let r2 := refl' E2 in
constr:(Plus r1 r2)
| fun x : nat => @?E1 x =>
let r1 := refl' E1 in
constr:(Abs r1)
| _ => constr:(Const e)
end.
(** Now, in the abstraction case, we bind [E1] as a function from an [x] value to the value of the abstraction body. Unfortunately, our recursive call there is not destined for success. It will match the same abstraction pattern and trigger another recursive call, and so on through infinite recursion. One last refactoring yields a working procedure. The key idea is to consider every input to [refl'] as _a function over the values of variables introduced during recursion_. *)
Reset refl'.
Ltac refl' e :=
match eval simpl in e with
| fun x : ?T => @?E1 x + @?E2 x =>
let r1 := refl' E1 in
let r2 := refl' E2 in
constr:(fun x => Plus (r1 x) (r2 x))
| fun (x : ?T) (y : nat) => @?E1 x y =>
let r1 := refl' (fun p : T * nat => E1 (fst p) (snd p)) in
constr:(fun x => Abs (fun y => r1 (x, y)))
| _ => constr:(fun x => Const (e x))
end.
(** Note how now even the addition case works in terms of functions, with [@?X] patterns. The abstraction case introduces a new variable by extending the type used to represent the free variables. In particular, the argument to [refl'] used type [T] to represent all free variables. We extend the type to [T * nat] for the type representing free variable values within the abstraction body. A bit of bookkeeping with pairs and their projections produces an appropriate version of the abstraction body to pass in a recursive call. To ensure that all this repackaging of terms does not interfere with pattern matching, we add an extra [simpl] reduction on the function argument, in the first line of the body of [refl'].
Now one more tactic provides an example of how to apply reification. Let us consider goals that are equalities between terms that can be reified. We want to change such goals into equalities between appropriate calls to [termDenote]. *)
Ltac refl :=
match goal with
| [ |- ?E1 = ?E2 ] =>
let E1' := refl' (fun _ : unit => E1) in
let E2' := refl' (fun _ : unit => E2) in
change (termDenote (E1' tt) = termDenote (E2' tt));
cbv beta iota delta [fst snd]
end.
Goal (fun (x y : nat) => x + y + 13) = (fun (_ z : nat) => z).
refl.
(** %\vspace{-.15in}%[[
============================
termDenote
(Abs
(fun y : nat =>
Abs (fun y0 : nat => Plus (Plus (Const y) (Const y0)) (Const 13)))) =
termDenote (Abs (fun _ : nat => Abs (fun y0 : nat => Const y0)))
]]
*)
Abort.
(** Our encoding here uses Coq functions to represent binding within the terms we reify, which makes it difficult to implement certain functions over reified terms. An alternative would be to represent variables with numbers. This can be done by writing a slightly smarter reification function that identifies variable references by detecting when term arguments are just compositions of [fst] and [snd]; from the order of the compositions we may read off the variable number. We leave the details as an exercise (though not a trivial one!) for the reader. *)
|
(** * Imp: Simple Imperative Programs *)
(** In this chapter, we begin a new direction that will continue for
the rest of the course. Up to now most of our attention has been
focused on various aspects of Coq itself, while from now on we'll
mostly be using Coq to formalize other things. (We'll continue to
pause from time to time to introduce a few additional aspects of
Coq.)
Our first case study is a _simple imperative programming language_
called Imp, embodying a tiny core fragment of conventional
mainstream languages such as C and Java. Here is a familiar
mathematical function written in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
*)
(** This chapter looks at how to define the _syntax_ and _semantics_
of Imp; the chapters that follow develop a theory of _program
equivalence_ and introduce _Hoare Logic_, a widely used logic for
reasoning about imperative programs. *)
(* ####################################################### *)
(** *** Sflib *)
(** A minor technical point: Instead of asking Coq to import our
earlier definitions from chapter [Logic], we import a small library
called [Sflib.v], containing just a few definitions and theorems
from earlier chapters that we'll actually use in the rest of the
course. This change should be nearly invisible, since most of what's
missing from Sflib has identical definitions in the Coq standard
library. The main reason for doing it is to tidy the global Coq
environment so that, for example, it is easier to search for
relevant theorems. *)
Require Export SfLib.
(* ####################################################### *)
(** * Arithmetic and Boolean Expressions *)
(** We'll present Imp in three parts: first a core language of
_arithmetic and boolean expressions_, then an extension of these
expressions with _variables_, and finally a language of _commands_
including assignment, conditions, sequencing, and loops. *)
(* ####################################################### *)
(** ** Syntax *)
Module AExp.
(** These two definitions specify the _abstract syntax_ of
arithmetic and boolean expressions. *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
(** In this chapter, we'll elide the translation from the
concrete syntax that a programmer would actually write to these
abstract syntax trees -- the process that, for example, would
translate the string ["1+2*3"] to the AST [APlus (ANum
1) (AMult (ANum 2) (ANum 3))]. The optional chapter [ImpParser]
develops a simple implementation of a lexical analyzer and parser
that can perform this translation. You do _not_ need to
understand that file to understand this one, but if you haven't
taken a course where these techniques are covered (e.g., a
compilers course) you may want to skim it. *)
(** *** *)
(** For comparison, here's a conventional BNF (Backus-Naur Form)
grammar defining the same abstract syntax:
a ::= nat
| a + a
| a - a
| a * a
b ::= true
| false
| a = a
| a <= a
| not b
| b and b
*)
(** Compared to the Coq version above...
- The BNF is more informal -- for example, it gives some
suggestions about the surface syntax of expressions (like the
fact that the addition operation is written [+] and is an
infix symbol) while leaving other aspects of lexical analysis
and parsing (like the relative precedence of [+], [-], and
[*]) unspecified. Some additional information -- and human
intelligence -- would be required to turn this description
into a formal definition (when implementing a compiler, for
example).
The Coq version consistently omits all this information and
concentrates on the abstract syntax only.
- On the other hand, the BNF version is lighter and
easier to read. Its informality makes it flexible, which is
a huge advantage in situations like discussions at the
blackboard, where conveying general ideas is more important
than getting every detail nailed down precisely.
Indeed, there are dozens of BNF-like notations and people
switch freely among them, usually without bothering to say which
form of BNF they're using because there is no need to: a
rough-and-ready informal understanding is all that's
needed. *)
(** It's good to be comfortable with both sorts of notations:
informal ones for communicating between humans and formal ones for
carrying out implementations and proofs. *)
(* ####################################################### *)
(** ** Evaluation *)
(** _Evaluating_ an arithmetic expression produces a number. *)
Fixpoint aeval (a : aexp) : nat :=
match a with
| ANum n => n
| APlus a1 a2 => (aeval a1) + (aeval a2)
| AMinus a1 a2 => (aeval a1) - (aeval a2)
| AMult a1 a2 => (aeval a1) * (aeval a2)
end.
Example test_aeval1:
aeval (APlus (ANum 2) (ANum 2)) = 4.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, evaluating a boolean expression yields a boolean. *)
Fixpoint beval (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval a1) (aeval a2)
| BLe a1 a2 => ble_nat (aeval a1) (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
(* ####################################################### *)
(** ** Optimization *)
(** We haven't defined very much yet, but we can already get
some mileage out of the definitions. Suppose we define a function
that takes an arithmetic expression and slightly simplifies it,
changing every occurrence of [0+e] (i.e., [(APlus (ANum 0) e])
into just [e]. *)
Fixpoint optimize_0plus (a:aexp) : aexp :=
match a with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
(** To make sure our optimization is doing the right thing we
can test it on some examples and see if the output looks OK. *)
Example test_optimize_0plus:
optimize_0plus (APlus (ANum 2)
(APlus (ANum 0)
(APlus (ANum 0) (ANum 1))))
= APlus (ANum 2) (ANum 1).
Proof. reflexivity. Qed.
(** But if we want to be sure the optimization is correct --
i.e., that evaluating an optimized expression gives the same
result as the original -- we should prove it. *)
Theorem optimize_0plus_sound: forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a. induction a.
Case "ANum". reflexivity.
Case "APlus". destruct a1.
SCase "a1 = ANum n". destruct n.
SSCase "n = 0". simpl. apply IHa2.
SSCase "n <> 0". simpl. rewrite IHa2. reflexivity.
SCase "a1 = APlus a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
SCase "a1 = AMinus a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
SCase "a1 = AMult a1_1 a1_2".
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
Case "AMinus".
simpl. rewrite IHa1. rewrite IHa2. reflexivity.
Case "AMult".
simpl. rewrite IHa1. rewrite IHa2. reflexivity. Qed.
(* ####################################################### *)
(** * Coq Automation *)
(** The repetition in this last proof is starting to be a little
annoying. If either the language of arithmetic expressions or the
optimization being proved sound were significantly more complex,
it would begin to be a real problem.
So far, we've been doing all our proofs using just a small handful
of Coq's tactics and completely ignoring its powerful facilities
for constructing parts of proofs automatically. This section
introduces some of these facilities, and we will see more over the
next several chapters. Getting used to them will take some
energy -- Coq's automation is a power tool -- but it will allow us
to scale up our efforts to more complex definitions and more
interesting properties without becoming overwhelmed by boring,
repetitive, low-level details. *)
(* ####################################################### *)
(** ** Tacticals *)
(** _Tacticals_ is Coq's term for tactics that take other tactics as
arguments -- "higher-order tactics," if you will. *)
(* ####################################################### *)
(** *** The [repeat] Tactical *)
(** The [repeat] tactical takes another tactic and keeps applying
this tactic until the tactic fails. Here is an example showing
that [100] is even using repeat. *)
Theorem ev100 : ev 100.
Proof.
repeat (apply ev_SS). (* applies ev_SS 50 times,
until [apply ev_SS] fails *)
apply ev_0.
Qed.
(* Print ev100. *)
(** The [repeat T] tactic never fails; if the tactic [T] doesn't apply
to the original goal, then repeat still succeeds without changing
the original goal (it repeats zero times). *)
Theorem ev100' : ev 100.
Proof.
repeat (apply ev_0). (* doesn't fail, applies ev_0 zero times *)
repeat (apply ev_SS). apply ev_0. (* we can continue the proof *)
Qed.
(** The [repeat T] tactic does not have any bound on the number of
times it applies [T]. If [T] is a tactic that always succeeds then
repeat [T] will loop forever (e.g. [repeat simpl] loops forever
since [simpl] always succeeds). While Coq's term language is
guaranteed to terminate, Coq's tactic language is not! *)
(* ####################################################### *)
(** *** The [try] Tactical *)
(** If [T] is a tactic, then [try T] is a tactic that is just like [T]
except that, if [T] fails, [try T] _successfully_ does nothing at
all (instead of failing). *)
Theorem silly1 : forall ae, aeval ae = aeval ae.
Proof. try reflexivity. (* this just does [reflexivity] *) Qed.
Theorem silly2 : forall (P : Prop), P -> P.
Proof.
intros P HP.
try reflexivity. (* just [reflexivity] would have failed *)
apply HP. (* we can still finish the proof in some other way *)
Qed.
(** Using [try] in a completely manual proof is a bit silly, but
we'll see below that [try] is very useful for doing automated
proofs in conjunction with the [;] tactical. *)
(* ####################################################### *)
(** *** The [;] Tactical (Simple Form) *)
(** In its most commonly used form, the [;] tactical takes two tactics
as argument: [T;T'] first performs the tactic [T] and then
performs the tactic [T'] on _each subgoal_ generated by [T]. *)
(** For example, consider the following trivial lemma: *)
Lemma foo : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n.
(* Leaves two subgoals, which are discharged identically... *)
Case "n=0". simpl. reflexivity.
Case "n=Sn'". simpl. reflexivity.
Qed.
(** We can simplify this proof using the [;] tactical: *)
Lemma foo' : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n; (* [destruct] the current goal *)
simpl; (* then [simpl] each resulting subgoal *)
reflexivity. (* and do [reflexivity] on each resulting subgoal *)
Qed.
(** Using [try] and [;] together, we can get rid of the repetition in
the proof that was bothering us a little while ago. *)
Theorem optimize_0plus_sound': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
(* The remaining cases -- ANum and APlus -- are different *)
Case "ANum". reflexivity.
Case "APlus".
destruct a1;
(* Again, most cases follow directly by the IH *)
try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
(* The interesting case, on which the [try...] does nothing,
is when [e1 = ANum n]. In this case, we have to destruct
[n] (to see whether the optimization applies) and rewrite
with the induction hypothesis. *)
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** Coq experts often use this "[...; try... ]" idiom after a tactic
like [induction] to take care of many similar cases all at once.
Naturally, this practice has an analog in informal proofs.
Here is an informal proof of this theorem that matches the
structure of the formal one:
_Theorem_: For all arithmetic expressions [a],
aeval (optimize_0plus a) = aeval a.
_Proof_: By induction on [a]. The [AMinus] and [AMult] cases
follow directly from the IH. The remaining cases are as follows:
- Suppose [a = ANum n] for some [n]. We must show
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
This is immediate from the definition of [optimize_0plus].
- Suppose [a = APlus a1 a2] for some [a1] and [a2]. We
must show
aeval (optimize_0plus (APlus a1 a2))
= aeval (APlus a1 a2).
Consider the possible forms of [a1]. For most of them,
[optimize_0plus] simply calls itself recursively for the
subexpressions and rebuilds a new expression of the same form
as [a1]; in these cases, the result follows directly from the
IH.
The interesting case is when [a1 = ANum n] for some [n].
If [n = ANum 0], then
optimize_0plus (APlus a1 a2) = optimize_0plus a2
and the IH for [a2] is exactly what we need. On the other
hand, if [n = S n'] for some [n'], then again [optimize_0plus]
simply calls itself recursively, and the result follows from
the IH. [] *)
(** This proof can still be improved: the first case (for [a = ANum
n]) is very trivial -- even more trivial than the cases that we
said simply followed from the IH -- yet we have chosen to write it
out in full. It would be better and clearer to drop it and just
say, at the top, "Most cases are either immediate or direct from
the IH. The only interesting case is the one for [APlus]..." We
can make the same improvement in our formal proof too. Here's how
it looks: *)
Theorem optimize_0plus_sound'': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
(* ... or are immediate by definition *)
try reflexivity.
(* The interesting case is when a = APlus a1 a2. *)
Case "APlus".
destruct a1; try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(* ####################################################### *)
(** *** The [;] Tactical (General Form) *)
(** The [;] tactical has a more general than the simple [T;T'] we've
seen above, which is sometimes also useful. If [T], [T1], ...,
[Tn] are tactics, then
T; [T1 | T2 | ... | Tn]
is a tactic that first performs [T] and then performs [T1] on the
first subgoal generated by [T], performs [T2] on the second
subgoal, etc.
So [T;T'] is just special notation for the case when all of the
[Ti]'s are the same tactic; i.e. [T;T'] is just a shorthand for:
T; [T' | T' | ... | T']
*)
(* ####################################################### *)
(** ** Defining New Tactic Notations *)
(** Coq also provides several ways of "programming" tactic scripts.
- The [Tactic Notation] idiom illustrated below gives a handy
way to define "shorthand tactics" that bundle several tactics
into a single command.
- For more sophisticated programming, Coq offers a small
built-in programming language called [Ltac] with primitives
that can examine and modify the proof state. The details are
a bit too complicated to get into here (and it is generally
agreed that [Ltac] is not the most beautiful part of Coq's
design!), but they can be found in the reference manual, and
there are many examples of [Ltac] definitions in the Coq
standard library that you can use as examples.
- There is also an OCaml API, which can be used to build tactics
that access Coq's internal structures at a lower level, but
this is seldom worth the trouble for ordinary Coq users.
The [Tactic Notation] mechanism is the easiest to come to grips with,
and it offers plenty of power for many purposes. Here's an example.
*)
Tactic Notation "simpl_and_try" tactic(c) :=
simpl;
try c.
(** This defines a new tactical called [simpl_and_try] which
takes one tactic [c] as an argument, and is defined to be
equivalent to the tactic [simpl; try c]. For example, writing
"[simpl_and_try reflexivity.]" in a proof would be the same as
writing "[simpl; try reflexivity.]" *)
(** The next subsection gives a more sophisticated use of this
feature... *)
(* ####################################################### *)
(** *** Bulletproofing Case Analyses *)
(** Being able to deal with most of the cases of an [induction]
or [destruct] all at the same time is very convenient, but it can
also be a little confusing. One problem that often comes up is
that _maintaining_ proofs written in this style can be difficult.
For example, suppose that, later, we extended the definition of
[aexp] with another constructor that also required a special
argument. The above proof might break because Coq generated the
subgoals for this constructor before the one for [APlus], so that,
at the point when we start working on the [APlus] case, Coq is
actually expecting the argument for a completely different
constructor. What we'd like is to get a sensible error message
saying "I was expecting the [AFoo] case at this point, but the
proof script is talking about [APlus]." Here's a nice trick (due
to Aaron Bohannon) that smoothly achieves this. *)
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** ([Case_aux] implements the common functionality of [Case],
[SCase], [SSCase], etc. For example, [Case "foo"] is defined as
[Case_aux Case "foo".) *)
(** For example, if [a] is a variable of type [aexp], then doing
aexp_cases (induction a) Case
will perform an induction on [a] (the same as if we had just typed
[induction a]) and _also_ add a [Case] tag to each subgoal
generated by the [induction], labeling which constructor it comes
from. For example, here is yet another proof of
[optimize_0plus_sound], using [aexp_cases]: *)
Theorem optimize_0plus_sound''': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
aexp_cases (induction a) Case;
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
try reflexivity.
(* At this point, there is already an ["APlus"] case name
in the context. The [Case "APlus"] here in the proof
text has the effect of a sanity check: if the "Case"
string in the context is anything _other_ than ["APlus"]
(for example, because we added a clause to the definition
of [aexp] and forgot to change the proof) we'll get a
helpful error at this point telling us that this is now
the wrong case. *)
Case "APlus".
aexp_cases (destruct a1) SCase;
try (simpl; simpl in IHa1;
rewrite IHa1; rewrite IHa2; reflexivity).
SCase "ANum". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** **** Exercise: 3 stars (optimize_0plus_b) *)
(** Since the [optimize_0plus] tranformation doesn't change the value
of [aexp]s, we should be able to apply it to all the [aexp]s that
appear in a [bexp] without changing the [bexp]'s value. Write a
function which performs that transformation on [bexp]s, and prove
it is sound. Use the tacticals we've just seen to make the proof
as elegant as possible. *)
Fixpoint optimize_0plus_b (b : bexp) : bexp :=
match b with
| BEq a1 a2 => BEq (optimize_0plus a1) (optimize_0plus a2)
| BLe a1 a2 => BLe (optimize_0plus a1) (optimize_0plus a2)
| _ => b
end.
Theorem optimize_0plus_b_sound : forall b,
beval (optimize_0plus_b b) = beval b.
Proof.
intros b.
induction b;
try simpl;
try (rewrite optimize_0plus_sound);
try (rewrite optimize_0plus_sound);
try reflexivity.
Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (optimizer) *)
(** _Design exercise_: The optimization implemented by our
[optimize_0plus] function is only one of many imaginable
optimizations on arithmetic and boolean expressions. Write a more
sophisticated optimizer and prove it correct.
(* FILL IN HERE *)
*)
Fixpoint optimize_ultimate (a:aexp) : aexp := ANum (aeval a).
(** [] *)
(* ####################################################### *)
(** ** The [omega] Tactic *)
(** The [omega] tactic implements a decision procedure for a subset of
first-order logic called _Presburger arithmetic_. It is based on
the Omega algorithm invented in 1992 by William Pugh.
If the goal is a universally quantified formula made out of
- numeric constants, addition ([+] and [S]), subtraction ([-]
and [pred]), and multiplication by constants (this is what
makes it Presburger arithmetic),
- equality ([=] and [<>]) and inequality ([<=]), and
- the logical connectives [/\], [\/], [~], and [->],
then invoking [omega] will either solve the goal or tell you that
it is actually false. *)
Example silly_presburger_example : forall m n o p,
m + n <= n + o /\ o + 3 = p + 3 ->
m <= p.
Proof.
intros. omega.
Qed.
(** Leibniz wrote, "It is unworthy of excellent men to lose
hours like slaves in the labor of calculation which could be
relegated to anyone else if machines were used." We recommend
using the omega tactic whenever possible. *)
(* ####################################################### *)
(** ** A Few More Handy Tactics *)
(** Finally, here are some miscellaneous tactics that you may find
convenient.
- [clear H]: Delete hypothesis [H] from the context.
- [subst x]: Find an assumption [x = e] or [e = x] in the
context, replace [x] with [e] throughout the context and
current goal, and clear the assumption.
- [subst]: Substitute away _all_ assumptions of the form [x = e]
or [e = x].
- [rename... into...]: Change the name of a hypothesis in the
proof context. For example, if the context includes a variable
named [x], then [rename x into y] will change all occurrences
of [x] to [y].
- [assumption]: Try to find a hypothesis [H] in the context that
exactly matches the goal; if one is found, behave just like
[apply H].
- [contradiction]: Try to find a hypothesis [H] in the current
context that is logically equivalent to [False]. If one is
found, solve the goal.
- [constructor]: Try to find a constructor [c] (from some
[Inductive] definition in the current environment) that can be
applied to solve the current goal. If one is found, behave
like [apply c]. *)
(** We'll see many examples of these in the proofs below. *)
(* ####################################################### *)
(** * Evaluation as a Relation *)
(** We have presented [aeval] and [beval] as functions defined by
[Fixpoints]. Another way to think about evaluation -- one that we
will see is often more flexible -- is as a _relation_ between
expressions and their values. This leads naturally to [Inductive]
definitions like the following one for arithmetic
expressions... *)
Module aevalR_first_try.
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n: nat),
aevalR (ANum n) n
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus: forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMult e1 e2) (n1 * n2).
(** As is often the case with relations, we'll find it
convenient to define infix notation for [aevalR]. We'll write [e
|| n] to mean that arithmetic expression [e] evaluates to value
[n]. (This notation is one place where the limitation to ASCII
symbols becomes a little bothersome. The standard notation for
the evaluation relation is a double down-arrow. We'll typeset it
like this in the HTML version of the notes and use a double
vertical bar as the closest approximation in [.v] files.) *)
Notation "e '||' n" := (aevalR e n) : type_scope.
End aevalR_first_try.
(** In fact, Coq provides a way to use this notation in the definition
of [aevalR] itself. This avoids situations where we're working on
a proof involving statements in the form [e || n] but we have to
refer back to a definition written using the form [aevalR e n].
We do this by first "reserving" the notation, then giving the
definition together with a declaration of what the notation
means. *)
Reserved Notation "e '||' n" (at level 50, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (APlus e1 e2) || (n1 + n2)
| E_AMinus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMinus e1 e2) || (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMult e1 e2) || (n1 * n2)
where "e '||' n" := (aevalR e n) : type_scope.
Tactic Notation "aevalR_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_ANum" | Case_aux c "E_APlus"
| Case_aux c "E_AMinus" | Case_aux c "E_AMult" ].
(* ####################################################### *)
(** ** Inference Rule Notation *)
(** In informal discussions, it is convenient to write the rules for
[aevalR] and similar relations in the more readable graphical form
of _inference rules_, where the premises above the line justify
the conclusion below the line (we have already seen them in the
Prop chapter). *)
(** For example, the constructor [E_APlus]...
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
...would be written like this as an inference rule:
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
*)
(** Formally, there is nothing very deep about inference rules:
they are just implications. You can read the rule name on the
right as the name of the constructor and read each of the
linebreaks between the premises above the line and the line itself
as [->]. All the variables mentioned in the rule ([e1], [n1],
etc.) are implicitly bound by universal quantifiers at the
beginning. (Such variables are often called _metavariables_ to
distinguish them from the variables of the language we are
defining. At the moment, our arithmetic expressions don't include
variables, but we'll soon be adding them.) The whole collection
of rules is understood as being wrapped in an [Inductive]
declaration (informally, this is either elided or else indicated
by saying something like "Let [aevalR] be the smallest relation
closed under the following rules..."). *)
(** For example, [||] is the smallest relation closed under these
rules:
----------- (E_ANum)
ANum n || n
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
e1 || n1
e2 || n2
--------------------- (E_AMinus)
AMinus e1 e2 || n1-n2
e1 || n1
e2 || n2
-------------------- (E_AMult)
AMult e1 e2 || n1*n2
*)
(* ####################################################### *)
(** ** Equivalence of the Definitions *)
(** It is straightforward to prove that the relational and functional
definitions of evaluation agree on all possible arithmetic
expressions... *)
Theorem aeval_iff_aevalR : forall a n,
(a || n) <-> aeval a = n.
Proof.
split.
Case "->".
intros H.
aevalR_cases (induction H) SCase; simpl.
SCase "E_ANum".
reflexivity.
SCase "E_APlus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMinus".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
SCase "E_AMult".
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
Case "<-".
generalize dependent n.
aexp_cases (induction a) SCase;
simpl; intros; subst.
SCase "ANum".
apply E_ANum.
SCase "APlus".
apply E_APlus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMinus".
apply E_AMinus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
SCase "AMult".
apply E_AMult.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
Qed.
(** Note: if you're reading the HTML file, you'll see an empty square box instead
of a proof for this theorem.
You can click on this box to "unfold" the text to see the proof.
Click on the unfolded to text to "fold" it back up to a box. We'll be using
this style frequently from now on to help keep the HTML easier to read.
The full proofs always appear in the .v files. *)
(** We can make the proof quite a bit shorter by making more
use of tacticals... *)
Theorem aeval_iff_aevalR' : forall a n,
(a || n) <-> aeval a = n.
Proof.
(* WORKED IN CLASS *)
split.
Case "->".
intros H; induction H; subst; reflexivity.
Case "<-".
generalize dependent n.
induction a; simpl; intros; subst; constructor;
try apply IHa1; try apply IHa2; reflexivity.
Qed.
(** **** Exercise: 3 stars (bevalR) *)
(** Write a relation [bevalR] in the same style as
[aevalR], and prove that it is equivalent to [beval].*)
Inductive bevalR : bexp -> bool -> Prop :=
| E_BTrue : bevalR BTrue true
| E_BFalse : bevalR BFalse false
| E_BEq : forall (a1 a2: aexp) (n1 n2: nat),
a1 || n1 -> a2 || n2 ->
bevalR (BEq a1 a2) (beq_nat n1 n2)
| E_BLe : forall (a1 a2: aexp) (n1 n2: nat),
a1 || n1 -> a2 || n2 ->
bevalR (BLe a1 a2) (ble_nat n1 n2)
| E_BNot : forall (b: bexp) (bo: bool),
bevalR b bo ->
bevalR (BNot b) (negb bo)
| E_BAnd : forall (b1 b2: bexp) (bo1 bo2: bool),
bevalR b1 bo1 ->
bevalR b2 bo2 ->
bevalR (BAnd b1 b2) (andb bo1 bo2).
Theorem beval_iff_bevalR : forall b bo,
bevalR b bo <-> beval b = bo.
Proof.
split.
Case "->".
intros H. induction H; subst; try reflexivity; try constructor; simpl;
apply aeval_iff_aevalR in H;
apply aeval_iff_aevalR in H0; subst; reflexivity.
Case "<-".
generalize dependent bo.
induction b;
intros; subst; simpl;
constructor;
try (apply aeval_iff_aevalR);
try reflexivity.
apply IHb. reflexivity.
apply IHb1. reflexivity.
apply IHb2. reflexivity.
Qed.
End AExp.
(* ####################################################### *)
(** ** Computational vs. Relational Definitions *)
(** For the definitions of evaluation for arithmetic and boolean
expressions, the choice of whether to use functional or relational
definitions is mainly a matter of taste. In general, Coq has
somewhat better support for working with relations. On the other
hand, in some sense function definitions carry more information,
because functions are necessarily deterministic and defined on all
arguments; for a relation we have to show these properties
explicitly if we need them. Functions also take advantage of Coq's
computations mechanism.
However, there are circumstances where relational definitions of
evaluation are preferable to functional ones. *)
Module aevalR_division.
(** For example, suppose that we wanted to extend the arithmetic
operations by considering also a division operation:*)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp
| ADiv : aexp -> aexp -> aexp. (* <--- new *)
(** Extending the definition of [aeval] to handle this new operation
would not be straightforward (what should we return as the result
of [ADiv (ANum 5) (ANum 0)]?). But extending [aevalR] is
straightforward. *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
| E_ADiv : forall (a1 a2: aexp) (n1 n2 n3: nat),
(a1 || n1) -> (a2 || n2) -> (mult n2 n3 = n1) -> (ADiv a1 a2) || n3
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_division.
Module aevalR_extended.
(** Suppose, instead, that we want to extend the arithmetic operations
by a nondeterministic number generator [any]:*)
Inductive aexp : Type :=
| AAny : aexp (* <--- NEW *)
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
(** Again, extending [aeval] would be tricky (because evaluation is
_not_ a deterministic function from expressions to numbers), but
extending [aevalR] is no problem: *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_Any : forall (n:nat),
AAny || n (* <--- new *)
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_extended.
(** * Expressions With Variables *)
(** Let's turn our attention back to defining Imp. The next thing we
need to do is to enrich our arithmetic and boolean expressions
with variables. To keep things simple, we'll assume that all
variables are global and that they only hold numbers. *)
(* ##################################################### *)
(** ** Identifiers *)
(** To begin, we'll need to formalize _identifiers_ such as program
variables. We could use strings for this -- or, in a real
compiler, fancier structures like pointers into a symbol table.
But for simplicity let's just use natural numbers as identifiers. *)
(** (We hide this section in a module because these definitions are
actually in [SfLib], but we want to repeat them here so that we
can explain them.) *)
Module Id.
(** We define a new inductive datatype [Id] so that we won't confuse
identifiers and numbers. We use [sumbool] to define a computable
equality operator on [Id]. *)
Inductive id : Type :=
Id : nat -> id.
Theorem eq_id_dec : forall id1 id2 : id, {id1 = id2} + {id1 <> id2}.
Proof.
intros id1 id2.
destruct id1 as [n1]. destruct id2 as [n2].
destruct (eq_nat_dec n1 n2) as [Heq | Hneq].
Case "n1 = n2".
left. rewrite Heq. reflexivity.
Case "n1 <> n2".
right. intros contra. inversion contra. apply Hneq. apply H0.
Defined.
(** The following lemmas will be useful for rewriting terms involving [eq_id_dec]. *)
Lemma eq_id : forall (T:Type) x (p q:T),
(if eq_id_dec x x then p else q) = p.
Proof.
intros.
destruct (eq_id_dec x x).
Case "x = x".
reflexivity.
Case "x <> x (impossible)".
apply ex_falso_quodlibet; apply n; reflexivity. Qed.
(** **** Exercise: 1 star, optional (neq_id) *)
Lemma neq_id : forall (T:Type) x y (p q:T), x <> y ->
(if eq_id_dec x y then p else q) = q.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Id.
(* ####################################################### *)
(** ** States *)
(** A _state_ represents the current values of _all_ the variables at
some point in the execution of a program. *)
(** For simplicity (to avoid dealing with partial functions), we
let the state be defined for _all_ variables, even though any
given program is only going to mention a finite number of them.
The state captures all of the information stored in memory. For Imp
programs, because each variable stores only a natural number, we
can represent the state as a mapping from identifiers to [nat].
For more complex programming languages, the state might have more
structure.
*)
Definition state := id -> nat.
Definition empty_state : state :=
fun _ => 0.
Definition update (st : state) (x : id) (n : nat) : state :=
fun x' => if eq_id_dec x x' then n else st x'.
(** For proofs involving states, we'll need several simple properties
of [update]. *)
(** **** Exercise: 1 star (update_eq) *)
Theorem update_eq : forall n x st,
(update st x n) x = n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (update_neq) *)
Theorem update_neq : forall x2 x1 n st,
x2 <> x1 ->
(update st x2 n) x1 = (st x1).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (update_example) *)
(** Before starting to play with tactics, make sure you understand
exactly what the theorem is saying! *)
Theorem update_example : forall (n:nat),
(update empty_state (Id 2) n) (Id 3) = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (update_shadow) *)
Theorem update_shadow : forall n1 n2 x1 x2 (st : state),
(update (update st x2 n1) x2 n2) x1 = (update st x2 n2) x1.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (update_same) *)
Theorem update_same : forall n1 x1 x2 (st : state),
st x1 = n1 ->
(update st x1 n1) x2 = st x2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (update_permute) *)
Theorem update_permute : forall n1 n2 x1 x2 x3 st,
x2 <> x1 ->
(update (update st x2 n1) x1 n2) x3 = (update (update st x1 n2) x2 n1) x3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################### *)
(** ** Syntax *)
(** We can add variables to the arithmetic expressions we had before by
simply adding one more constructor: *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| AId : id -> aexp (* <----- NEW *)
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "AId" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** Defining a few variable names as notational shorthands will make
examples easier to read: *)
Definition X : id := Id 0.
Definition Y : id := Id 1.
Definition Z : id := Id 2.
(** (This convention for naming program variables ([X], [Y],
[Z]) clashes a bit with our earlier use of uppercase letters for
types. Since we're not using polymorphism heavily in this part of
the course, this overloading should not cause confusion.) *)
(** The definition of [bexp]s is the same as before (using the new
[aexp]s): *)
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
Tactic Notation "bexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "BTrue" | Case_aux c "BFalse" | Case_aux c "BEq"
| Case_aux c "BLe" | Case_aux c "BNot" | Case_aux c "BAnd" ].
(* ################################################### *)
(** ** Evaluation *)
(** The arith and boolean evaluators can be extended to handle
variables in the obvious way: *)
Fixpoint aeval (st : state) (a : aexp) : nat :=
match a with
| ANum n => n
| AId x => st x (* <----- NEW *)
| APlus a1 a2 => (aeval st a1) + (aeval st a2)
| AMinus a1 a2 => (aeval st a1) - (aeval st a2)
| AMult a1 a2 => (aeval st a1) * (aeval st a2)
end.
Fixpoint beval (st : state) (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval st a1) (aeval st a2)
| BLe a1 a2 => ble_nat (aeval st a1) (aeval st a2)
| BNot b1 => negb (beval st b1)
| BAnd b1 b2 => andb (beval st b1) (beval st b2)
end.
Example aexp1 :
aeval (update empty_state X 5)
(APlus (ANum 3) (AMult (AId X) (ANum 2)))
= 13.
Proof. reflexivity. Qed.
Example bexp1 :
beval (update empty_state X 5)
(BAnd BTrue (BNot (BLe (AId X) (ANum 4))))
= true.
Proof. reflexivity. Qed.
(* ####################################################### *)
(** * Commands *)
(** Now we are ready define the syntax and behavior of Imp
_commands_ (often called _statements_). *)
(* ################################################### *)
(** ** Syntax *)
(** Informally, commands [c] are described by the following BNF
grammar:
c ::= SKIP
| x ::= a
| c ;; c
| WHILE b DO c END
| IFB b THEN c ELSE c FI
]]
*)
(**
For example, here's the factorial function in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
When this command terminates, the variable [Y] will contain the
factorial of the initial value of [X].
*)
(** Here is the formal definition of the syntax of commands: *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";;"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
(** As usual, we can use a few [Notation] declarations to make things
more readable. We need to be a bit careful to avoid conflicts
with Coq's built-in notations, so we'll keep this light -- in
particular, we won't introduce any notations for [aexps] and
[bexps] to avoid confusion with the numerical and boolean
operators we've already defined. We use the keyword [IFB] for
conditionals instead of [IF], for similar reasons. *)
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** For example, here is the factorial function again, written as a
formal definition to Coq: *)
Definition fact_in_coq : com :=
Z ::= AId X;;
Y ::= ANum 1;;
WHILE BNot (BEq (AId Z) (ANum 0)) DO
Y ::= AMult (AId Y) (AId Z);;
Z ::= AMinus (AId Z) (ANum 1)
END.
(* ####################################################### *)
(** ** Examples *)
(** Assignment: *)
Definition plus2 : com :=
X ::= (APlus (AId X) (ANum 2)).
Definition XtimesYinZ : com :=
Z ::= (AMult (AId X) (AId Y)).
Definition subtract_slowly_body : com :=
Z ::= AMinus (AId Z) (ANum 1) ;;
X ::= AMinus (AId X) (ANum 1).
(** *** Loops *)
Definition subtract_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
subtract_slowly_body
END.
Definition subtract_3_from_5_slowly : com :=
X ::= ANum 3 ;;
Z ::= ANum 5 ;;
subtract_slowly.
(** *** An infinite loop: *)
Definition loop : com :=
WHILE BTrue DO
SKIP
END.
(* ################################################################ *)
(** * Evaluation *)
(** Next we need to define what it means to evaluate an Imp command.
The fact that [WHILE] loops don't necessarily terminate makes defining
an evaluation function tricky... *)
(* #################################### *)
(** ** Evaluation as a Function (Failed Attempt) *)
(** Here's an attempt at defining an evaluation function for commands,
omitting the [WHILE] case. *)
Fixpoint ceval_fun_no_while (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| x ::= a1 =>
update st x (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_fun_no_while st c1 in
ceval_fun_no_while st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_fun_no_while st c1
else ceval_fun_no_while st c2
| WHILE b DO c END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the [WHILE] case as follows:
<<
Fixpoint ceval_fun (st : state) (c : com) : state :=
match c with
...
| WHILE b DO c END =>
if (beval st b1)
then ceval_fun st (c1; WHILE b DO c END)
else st
end.
>>
Coq doesn't accept such a definition ("Error: Cannot guess
decreasing argument of fix") because the function we want to
define is not guaranteed to terminate. Indeed, it doesn't always
terminate: for example, the full version of the [ceval_fun]
function applied to the [loop] program above would never
terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is
an (invalid!) Coq program showing what would go wrong if Coq
allowed non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become provable
(e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_fun] cannot be written in Coq -- at least not without
additional tricks (see chapter [ImpCEvalFun] if curious). *)
(* #################################### *)
(** ** Evaluation as a Relation *)
(** Here's a better way: we define [ceval] as a _relation_ rather than
a _function_ -- i.e., we define it in [Prop] instead of [Type], as
we did for [aevalR] above. *)
(** This is an important change. Besides freeing us from the awkward
workarounds that would be needed to define evaluation as a
function, it gives us a lot more flexibility in the definition.
For example, if we added concurrency features to the language,
we'd want the definition of evaluation to be non-deterministic --
i.e., not only would it not be total, it would not even be a
partial function! *)
(** We'll use the notation [c / st || st'] for our [ceval] relation:
[c / st || st'] means that executing program [c] in a starting
state [st] results in an ending state [st']. This can be
pronounced "[c] takes state [st] to [st']".
*)
(** *** Operational Semantics
---------------- (E_Skip)
SKIP / st || st
aeval st a1 = n
-------------------------------- (E_Ass)
x := a1 / st || (update st x n)
c1 / st || st'
c2 / st' || st''
------------------- (E_Seq)
c1;;c2 / st || st''
beval st b1 = true
c1 / st || st'
------------------------------------- (E_IfTrue)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
c2 / st || st'
------------------------------------- (E_IfFalse)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
------------------------------ (E_WhileEnd)
WHILE b DO c END / st || st
beval st b1 = true
c / st || st'
WHILE b DO c END / st' || st''
--------------------------------- (E_WhileLoop)
WHILE b DO c END / st || st''
*)
(** Here is the formal definition. (Make sure you understand
how it corresponds to the inference rules.) *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
SKIP / st || st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
(x ::= a1) / st || (update st x n)
| E_Seq : forall c1 c2 st st' st'',
c1 / st || st' ->
c2 / st' || st'' ->
(c1 ;; c2) / st || st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
c1 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
c2 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall b st c,
beval st b = false ->
(WHILE b DO c END) / st || st
| E_WhileLoop : forall st st' st'' b c,
beval st b = true ->
c / st || st' ->
(WHILE b DO c END) / st' || st'' ->
(WHILE b DO c END) / st || st''
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop" ].
(** *** *)
(** The cost of defining evaluation as a relation instead of a
function is that we now need to construct _proofs_ that some
program evaluates to some result state, rather than just letting
Coq's computation mechanism do it for us. *)
Example ceval_example1:
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)
/ empty_state
|| (update (update empty_state X 2) Z 4).
Proof.
(* We must supply the intermediate state *)
apply E_Seq with (update empty_state X 2).
Case "assignment command".
apply E_Ass. reflexivity.
Case "if command".
apply E_IfFalse.
reflexivity.
apply E_Ass. reflexivity. Qed.
(** **** Exercise: 2 stars (ceval_example2) *)
Example ceval_example2:
(X ::= ANum 0;; Y ::= ANum 1;; Z ::= ANum 2) / empty_state ||
(update (update (update empty_state X 0) Y 1) Z 2).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y].
Prove that this program executes as intended for X = 2
(this latter part is trickier than you might expect). *)
Definition pup_to_n : com :=
(* FILL IN HERE *) admit.
Theorem pup_to_2_ceval :
pup_to_n / (update empty_state X 2) ||
update (update (update (update (update (update empty_state
X 2) Y 0) Y 2) X 1) Y 3) X 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** ** Determinism of Evaluation *)
(** Changing from a computational to a relational definition of
evaluation is a good move because it allows us to escape from the
artificial requirement (imposed by Coq's restrictions on
[Fixpoint] definitions) that evaluation should be a total
function. But it also raises a question: Is the second definition
of evaluation actually a partial function? That is, is it
possible that, beginning from the same state [st], we could
evaluate some command [c] in different ways to reach two different
output states [st'] and [st'']?
In fact, this cannot happen: [ceval] is a partial function.
Here's the proof: *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
ceval_cases (induction E1) Case;
intros st2 E2; inversion E2; subst.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b1 evaluates to true".
apply IHE1. assumption.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b1 evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b1 evaluates to false".
reflexivity.
SCase "b1 evaluates to true (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b1 evaluates to false (contradiction)".
rewrite H in H4. inversion H4.
SCase "b1 evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption. Qed.
(* ####################################################### *)
(** * Reasoning About Imp Programs *)
(** We'll get much deeper into systematic techniques for reasoning
about Imp programs in the following chapters, but we can do quite
a bit just working with the bare definitions. *)
(* This section explores some examples. *)
Theorem plus2_spec : forall st n st',
st X = n ->
plus2 / st || st' ->
st' X = n + 2.
Proof.
intros st n st' HX Heval.
(* Inverting Heval essentially forces Coq to expand one
step of the ceval computation - in this case revealing
that st' must be st extended with the new value of X,
since plus2 is an assignment *)
inversion Heval. subst. clear Heval. simpl.
apply update_eq. Qed.
(** **** Exercise: 3 stars (XtimesYinZ_spec) *)
(** State and prove a specification of [XtimesYinZ]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (loop_never_stops) *)
Theorem loop_never_stops : forall st st',
~(loop / st || st').
Proof.
intros st st' contra. unfold loop in contra.
remember (WHILE BTrue DO SKIP END) as loopdef eqn:Heqloopdef.
(* Proceed by induction on the assumed derivation showing that
[loopdef] terminates. Most of the cases are immediately
contradictory (and so can be solved in one step with
[inversion]). *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (no_whilesR) *)
(** Consider the definition of the [no_whiles] property below: *)
Fixpoint no_whiles (c : com) : bool :=
match c with
| SKIP => true
| _ ::= _ => true
| c1 ;; c2 => andb (no_whiles c1) (no_whiles c2)
| IFB _ THEN ct ELSE cf FI => andb (no_whiles ct) (no_whiles cf)
| WHILE _ DO _ END => false
end.
(** This property yields [true] just on programs that
have no while loops. Using [Inductive], write a property
[no_whilesR] such that [no_whilesR c] is provable exactly when [c]
is a program with no while loops. Then prove its equivalence
with [no_whiles]. *)
Inductive no_whilesR: com -> Prop :=
(* FILL IN HERE *)
.
Theorem no_whiles_eqv:
forall c, no_whiles c = true <-> no_whilesR c.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars (no_whiles_terminating) *)
(** Imp programs that don't involve while loops always terminate.
State and prove a theorem [no_whiles_terminating] that says this. *)
(** (Use either [no_whiles] or [no_whilesR], as you prefer.) *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (stack_compiler) *)
(** HP Calculators, programming languages like Forth and Postscript,
and abstract machines like the Java Virtual Machine all evaluate
arithmetic expressions using a stack. For instance, the expression
<<
(2*3)+(3*(4-2))
>>
would be entered as
<<
2 3 * 3 4 2 - * +
>>
and evaluated like this:
<<
[] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
>>
The task of this exercise is to write a small compiler that
translates [aexp]s into stack machine instructions.
The instruction set for our stack language will consist of the
following instructions:
- [SPush n]: Push the number [n] on the stack.
- [SLoad x]: Load the identifier [x] from the store and push it
on the stack
- [SPlus]: Pop the two top numbers from the stack, add them, and
push the result onto the stack.
- [SMinus]: Similar, but subtract.
- [SMult]: Similar, but multiply. *)
Inductive sinstr : Type :=
| SPush : nat -> sinstr
| SLoad : id -> sinstr
| SPlus : sinstr
| SMinus : sinstr
| SMult : sinstr.
(** Write a function to evaluate programs in the stack language. It
takes as input a state, a stack represented as a list of
numbers (top stack item is the head of the list), and a program
represented as a list of instructions, and returns the stack after
executing the program. Test your function on the examples below.
Note that the specification leaves unspecified what to do when
encountering an [SPlus], [SMinus], or [SMult] instruction if the
stack contains less than two elements. In a sense, it is
immaterial what we do, since our compiler will never emit such a
malformed program. *)
Fixpoint s_execute (st : state) (stack : list nat)
(prog : list sinstr)
: list nat :=
(* FILL IN HERE *) admit.
Example s_execute1 :
s_execute empty_state []
[SPush 5; SPush 3; SPush 1; SMinus]
= [2; 5].
(* FILL IN HERE *) Admitted.
Example s_execute2 :
s_execute (update empty_state X 3) [3;4]
[SPush 4; SLoad X; SMult; SPlus]
= [15; 4].
(* FILL IN HERE *) Admitted.
(** Next, write a function which compiles an [aexp] into a stack
machine program. The effect of running the program should be the
same as pushing the value of the expression on the stack. *)
Fixpoint s_compile (e : aexp) : list sinstr :=
(* FILL IN HERE *) admit.
(** After you've defined [s_compile], prove the following to test
that it works. *)
Example s_compile1 :
s_compile (AMinus (AId X) (AMult (ANum 2) (AId Y)))
= [SLoad X; SPush 2; SLoad Y; SMult; SMinus].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (stack_compiler_correct) *)
(** The task of this exercise is to prove the correctness of the
compiler implemented in the previous exercise. Remember that
the specification left unspecified what to do when encountering an
[SPlus], [SMinus], or [SMult] instruction if the stack contains
less than two elements. (In order to make your correctness proof
easier you may find it useful to go back and change your
implementation!)
Prove the following theorem, stating that the [compile] function
behaves correctly. You will need to start by stating a more
general lemma to get a usable induction hypothesis; the main
theorem will then be a simple corollary of this lemma. *)
Theorem s_compile_correct : forall (st : state) (e : aexp),
s_execute st [] (s_compile e) = [ aeval st e ].
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 5 stars, advanced (break_imp) *)
Module BreakImp.
(** Imperative languages such as C or Java often have a [break] or
similar statement for interrupting the execution of loops. In this
exercise we will consider how to add [break] to Imp.
First, we need to enrich the language of commands with an
additional case. *)
Inductive com : Type :=
| CSkip : com
| CBreak : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "BREAK" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
Notation "'SKIP'" :=
CSkip.
Notation "'BREAK'" :=
CBreak.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** Next, we need to define the behavior of [BREAK]. Informally,
whenever [BREAK] is executed in a sequence of commands, it stops
the execution of that sequence and signals that the innermost
enclosing loop (if any) should terminate. If there aren't any
enclosing loops, then the whole program simply terminates. The
final state should be the same as the one in which the [BREAK]
statement was executed.
One important point is what to do when there are multiple loops
enclosing a given [BREAK]. In those cases, [BREAK] should only
terminate the _innermost_ loop where it occurs. Thus, after
executing the following piece of code...
X ::= 0;;
Y ::= 1;;
WHILE 0 <> Y DO
WHILE TRUE DO
BREAK
END;;
X ::= 1;;
Y ::= Y - 1
END
... the value of [X] should be [1], and not [0].
One way of expressing this behavior is to add another parameter to
the evaluation relation that specifies whether evaluation of a
command executes a [BREAK] statement: *)
Inductive status : Type :=
| SContinue : status
| SBreak : status.
Reserved Notation "c1 '/' st '||' s '/' st'"
(at level 40, st, s at level 39).
(** Intuitively, [c / st || s / st'] means that, if [c] is started in
state [st], then it terminates in state [st'] and either signals
that any surrounding loop (or the whole program) should exit
immediately ([s = SBreak]) or that execution should continue
normally ([s = SContinue]).
The definition of the "[c / st || s / st']" relation is very
similar to the one we gave above for the regular evaluation
relation ([c / st || s / st']) -- we just need to handle the
termination signals appropriately:
- If the command is [SKIP], then the state doesn't change, and
execution of any enclosing loop can continue normally.
- If the command is [BREAK], the state stays unchanged, but we
signal a [SBreak].
- If the command is an assignment, then we update the binding for
that variable in the state accordingly and signal that execution
can continue normally.
- If the command is of the form [IF b THEN c1 ELSE c2 FI], then
the state is updated as in the original semantics of Imp, except
that we also propagate the signal from the execution of
whichever branch was taken.
- If the command is a sequence [c1 ; c2], we first execute
[c1]. If this yields a [SBreak], we skip the execution of [c2]
and propagate the [SBreak] signal to the surrounding context;
the resulting state should be the same as the one obtained by
executing [c1] alone. Otherwise, we execute [c2] on the state
obtained after executing [c1], and propagate the signal that was
generated there.
- Finally, for a loop of the form [WHILE b DO c END], the
semantics is almost the same as before. The only difference is
that, when [b] evaluates to true, we execute [c] and check the
signal that it raises. If that signal is [SContinue], then the
execution proceeds as in the original semantics. Otherwise, we
stop the execution of the loop, and the resulting state is the
same as the one resulting from the execution of the current
iteration. In either case, since [BREAK] only terminates the
innermost loop, [WHILE] signals [SContinue]. *)
(** Based on the above description, complete the definition of the
[ceval] relation. *)
Inductive ceval : com -> state -> status -> state -> Prop :=
| E_Skip : forall st,
CSkip / st || SContinue / st
(* FILL IN HERE *)
where "c1 '/' st '||' s '/' st'" := (ceval c1 st s st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip"
(* FILL IN HERE *)
].
(** Now the following properties of your definition of [ceval]: *)
Theorem break_ignore : forall c st st' s,
(BREAK;; c) / st || s / st' ->
st = st'.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_continue : forall b c st st' s,
(WHILE b DO c END) / st || s / st' ->
s = SContinue.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_stops_on_break : forall b c st st',
beval st b = true ->
c / st || SBreak / st' ->
(WHILE b DO c END) / st || SContinue / st'.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 3 stars, advanced, optional (while_break_true) *)
Theorem while_break_true : forall b c st st',
(WHILE b DO c END) / st || SContinue / st' ->
beval st' b = true ->
exists st'', c / st'' || SBreak / st'.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 4 stars, advanced, optional (ceval_deterministic) *)
Theorem ceval_deterministic: forall (c:com) st st1 st2 s1 s2,
c / st || s1 / st1 ->
c / st || s2 / st2 ->
st1 = st2 /\ s1 = s2.
Proof.
(* FILL IN HERE *) Admitted.
End BreakImp.
(** [] *)
(** **** Exercise: 3 stars, optional (short_circuit) *)
(** Most modern programming languages use a "short-circuit" evaluation
rule for boolean [and]: to evaluate [BAnd b1 b2], first evaluate
[b1]. If it evaluates to [false], then the entire [BAnd]
expression evaluates to [false] immediately, without evaluating
[b2]. Otherwise, [b2] is evaluated to determine the result of the
[BAnd] expression.
Write an alternate version of [beval] that performs short-circuit
evaluation of [BAnd] in this manner, and prove that it is
equivalent to [beval]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, optional (add_for_loop) *)
(** Add C-style [for] loops to the language of commands, update the
[ceval] definition to define the semantics of [for] loops, and add
cases for [for] loops as needed so that all the proofs in this file
are accepted by Coq.
A [for] loop should be parameterized by (a) a statement executed
initially, (b) a test that is run on each iteration of the loop to
determine whether the loop should continue, (c) a statement
executed at the end of each loop iteration, and (d) a statement
that makes up the body of the loop. (You don't need to worry
about making up a concrete Notation for [for] loops, but feel free
to play with this too if you like.) *)
(* FILL IN HERE *)
(** [] *)
(* <$Date: 2014-12-26 15:20:26 -0500 (Fri, 26 Dec 2014) $ *)
|
// File : ../RTL/hostController/softransmit.v
// Generated : 11/10/06 05:37:21
// From : ../RTL/hostController/softransmit.asf
// By : FSM2VHDL ver. 5.0.0.9
//////////////////////////////////////////////////////////////////////
//// ////
//// softransmit
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbHostControl_h.v"
module SOFTransmit (SOFEnable, SOFSent, SOFSyncEn, SOFTimerClr, SOFTimer, clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn, fullSpeedRate);
input SOFEnable; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
input SOFSyncEn;
input [15:0] SOFTimer;
input clk;
input rst;
input sendPacketArbiterGnt;
input sendPacketRdy;
output SOFSent; // single cycle pulse
output SOFTimerClr; // Single cycle pulse
output sendPacketArbiterReq;
output sendPacketWEn;
input fullSpeedRate;
wire SOFEnable;
reg SOFSent, next_SOFSent;
wire SOFSyncEn;
reg SOFTimerClr, next_SOFTimerClr;
wire [15:0] SOFTimer;
wire clk;
wire rst;
wire sendPacketArbiterGnt;
reg sendPacketArbiterReq, next_sendPacketArbiterReq;
wire sendPacketRdy;
reg sendPacketWEn, next_sendPacketWEn;
reg [15:0] SOFNearTime;
// diagram signals declarations
reg [7:0]i, next_i;
// BINARY ENCODED state machine: SOFTx
// State codes definitions:
`define START_STX 3'b000
`define WAIT_SOF_NEAR 3'b001
`define WAIT_SP_GNT 3'b010
`define WAIT_SOF_NOW 3'b011
`define SOF_FIN 3'b100
`define DLY_SOF_CHK1 3'b101
`define DLY_SOF_CHK2 3'b110
reg [2:0] CurrState_SOFTx;
reg [2:0] NextState_SOFTx;
//--------------------------------------------------------------------
// Machine: SOFTx
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (i or SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or sendPacketArbiterReq or sendPacketWEn or SOFTimerClr or SOFSent or CurrState_SOFTx)
begin : SOFTx_NextState
NextState_SOFTx <= CurrState_SOFTx;
// Set default values for outputs and signals
next_sendPacketArbiterReq <= sendPacketArbiterReq;
next_sendPacketWEn <= sendPacketWEn;
next_SOFTimerClr <= SOFTimerClr;
next_SOFSent <= SOFSent;
next_i <= i;
case (CurrState_SOFTx)
`START_STX:
NextState_SOFTx <= `WAIT_SOF_NEAR;
`WAIT_SOF_NEAR:
if (SOFTimer >= SOFNearTime ||
(SOFSyncEn == 1'b1 &&
SOFEnable == 1'b1))
begin
NextState_SOFTx <= `WAIT_SP_GNT;
next_sendPacketArbiterReq <= 1'b1;
end
`WAIT_SP_GNT:
if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
NextState_SOFTx <= `WAIT_SOF_NOW;
`WAIT_SOF_NOW:
if (SOFTimer >= `SOF_TX_TIME)
begin
NextState_SOFTx <= `SOF_FIN;
next_sendPacketWEn <= 1'b1;
next_SOFTimerClr <= 1'b1;
next_SOFSent <= 1'b1;
end
else if (SOFEnable == 1'b0)
begin
NextState_SOFTx <= `SOF_FIN;
next_SOFTimerClr <= 1'b1;
end
`SOF_FIN:
begin
next_sendPacketWEn <= 1'b0;
next_SOFTimerClr <= 1'b0;
next_SOFSent <= 1'b0;
if (sendPacketRdy == 1'b1)
begin
NextState_SOFTx <= `DLY_SOF_CHK1;
next_i <= 8'h00;
end
end
`DLY_SOF_CHK1:
begin
next_i <= i + 1'b1;
if (i==8'hff)
begin
NextState_SOFTx <= `DLY_SOF_CHK2;
next_sendPacketArbiterReq <= 1'b0;
next_i <= 8'h00;
end
end
`DLY_SOF_CHK2:
begin
next_i <= i + 1'b1;
if (i==8'hff)
NextState_SOFTx <= `WAIT_SOF_NEAR;
end
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : SOFTx_CurrentState
if (rst)
CurrState_SOFTx <= `START_STX;
else
CurrState_SOFTx <= NextState_SOFTx;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : SOFTx_RegOutput
if (rst)
begin
i <= 8'h00;
SOFSent <= 1'b0;
SOFTimerClr <= 1'b0;
sendPacketArbiterReq <= 1'b0;
sendPacketWEn <= 1'b0;
SOFNearTime <= 16'h0000;
end
else
begin
i <= next_i;
SOFSent <= next_SOFSent;
SOFTimerClr <= next_SOFTimerClr;
sendPacketArbiterReq <= next_sendPacketArbiterReq;
sendPacketWEn <= next_sendPacketWEn;
if (fullSpeedRate == 1'b1)
SOFNearTime <= `SOF_TX_TIME - `SOF_TX_MARGIN;
else
SOFNearTime <= `SOF_TX_TIME - `SOF_TX_MARGIN_LOW_SPEED;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_SYMBOL_V
`define SKY130_FD_SC_HVL__DFSTP_SYMBOL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_SYMBOL_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <[email protected]>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_dest_fifo_inf (
input clk,
input resetn,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
output [C_ID_WIDTH-1:0] data_id,
input data_eot,
input response_eot,
input en,
output [C_DATA_WIDTH-1:0] dout,
output valid,
output underflow,
output xfer_req,
output fifo_ready,
input fifo_valid,
input [C_DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
output response_valid,
input response_ready,
output response_resp_eot,
output [1:0] response_resp
);
parameter C_ID_WIDTH = 3;
parameter C_DATA_WIDTH = 64;
parameter C_BEATS_PER_BURST_WIDTH = 4;
assign sync_id_ret = sync_id;
wire data_enabled;
wire _fifo_ready;
assign fifo_ready = _fifo_ready | ~enabled;
reg en_d1;
wire data_ready;
wire data_valid;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
en_d1 <= 1'b0;
end else begin
en_d1 <= en;
end
end
assign underflow = en_d1 & (~data_valid | ~enable);
assign data_ready = en_d1 & (data_valid | ~enable);
assign valid = en_d1 & data_valid & enable;
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH),
.C_DISABLE_WAIT_FOR_ID(0)
) i_data_mover (
.clk(clk),
.resetn(resetn),
.enable(enable),
.enabled(data_enabled),
.sync_id(sync_id),
.xfer_req(xfer_req),
.request_id(request_id),
.response_id(data_id),
.eot(data_eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.s_axi_ready(_fifo_ready),
.s_axi_valid(fifo_valid),
.s_axi_data(fifo_data),
.m_axi_ready(data_ready),
.m_axi_valid(data_valid),
.m_axi_data(dout),
.m_axi_last()
);
dmac_response_generator # (
.C_ID_WIDTH(C_ID_WIDTH)
) i_response_generator (
.clk(clk),
.resetn(resetn),
.enable(data_enabled),
.enabled(enabled),
.sync_id(sync_id),
.request_id(data_id),
.response_id(response_id),
.eot(response_eot),
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_eot(response_resp_eot),
.resp_resp(response_resp)
);
endmodule
|
module j1soc#(
//parameter bootram_file = "../../firmware/hello_world/j1.mem" // For synthesis
parameter bootram_file = "../firmware/Hello_World/j1.mem" // For simulation
)(
trigger, echo, done, [15:0]distance
sys_clk_i, sys_rst_i
);
input sys_clk_i, sys_rst_i, trigger;
output echo, done, [15:0]distance;
output done;
//------------------------------------ regs and wires-------------------------------
wire j1_io_rd;//********************** J1
wire j1_io_wr;//********************** J1
wire [15:0] j1_io_addr;//************* J1
reg [15:0] j1_io_din;//************** J1
wire [15:0] j1_io_dout;//************* J1
reg [1:4]cs; // CHIP-SELECT
wire [15:0]ult_out;
//------------------------------------ regs and wires-------------------------------
j1 #(bootram_file) cpu0(sys_clk_i, sys_rst_i, j1_io_din, j1_io_rd, j1_io_wr, j1_io_addr, j1_io_dout);
peripherial_ultrasnd ultra(.clk(sys_clk_i),.reset(sys_rst_i),.d_in(j1_io_dout),.cs(cs[1]),.addr(j1_io_addr[3:0]),.rd(j1_io_rd),.wr(j1_io_wr),.d_out(ult_out),.trigger(trigger),.echo(echo),.done(done),.d_out(distance));
dpRAM_interface dpRm(.clk(sys_clk_i), .d_in(j1_io_dout), .cs(cs[4]), .addr(j1_io_addr[7:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(dp_ram_dout));
// ============== Chip_Select (Addres decoder) ======================== // se hace con los 8 bits mas significativos de j1_io_addr
always @* begin
case (j1_io_addr[15:8]) // direcciones - chip_select
8'h67: cs= 4'b1000; //mult
8'h68: cs= 4'b0100; //div
8'h69: cs= 4'b0010; //uart
8'h70: cs= 4'b0001; //dp_ram
default: cs= 3'b000;
endcase
end
//============== Chip_Select (Addres decoder) ======================== //
// ============== MUX ======================== // se encarga de lecturas del J1
always @* begin
case (cs)
4'b1000: j1_io_din = ult_out;
4'b0001: j1_io_din = dp_ram_dout;
default: j1_io_din = 16'h0666;
endcase
end
// ============== MUX ======================== //
endmodule // top
|
// -*- Mode: Verilog -*-
// Filename : cpu.v
// Description : Complete Picoblaze Design
// Author : Philip Tracton
// Created On : Thu May 21 22:33:37 2015
// Last Modified By: Philip Tracton
// Last Modified On: Thu May 21 22:33:37 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`timescale 1ns/1ns
module cpu (/*AUTOARG*/
// Outputs
port_id, out_port, write_strobe, read_strobe, interrupt_ack,
// Inputs
clk, in_port, interrupt, kcpsm6_sleep, cpu_reset
) ;
input clk;
input [7:0] in_port;
output [7:0] port_id;
output [7:0] out_port;
output write_strobe;
output read_strobe;
input interrupt; //See note above
output interrupt_ack;
input kcpsm6_sleep;
input cpu_reset;
/*AUTOWIRE*/
/*AUTOREG*/
//
// Signals for connection of KCPSM6 and Program Memory.
//
wire [11:0] address;
wire [17:0] instruction;
wire [7:0] out_port;
wire [7:0] port_id;
wire bram_enable;
wire k_write_strobe;
wire kcpsm6_reset; //See note above
wire interrupt_ack;
wire read_strobe;
wire write_strobe;
//
// Some additional signals are required if your system also needs to reset KCPSM6.
//
//
// When interrupt is to be used then the recommended circuit included below requires
// the following signal to represent the request made from your system.
//
wire int_request;
kcpsm6 #(
.interrupt_vector (12'h3FF),
.scratch_pad_memory_size(64),
.hwbuild (8'h00))
processor (
.address (address),
.instruction (instruction),
.bram_enable (bram_enable),
.port_id (port_id),
.write_strobe (write_strobe),
.k_write_strobe (k_write_strobe),
.out_port (out_port),
.read_strobe (read_strobe),
.in_port (in_port),
.interrupt (interrupt),
.interrupt_ack (interrupt_ack),
.reset (kcpsm6_reset),
.sleep (kcpsm6_sleep),
.clk (clk));
//
// If your design also needs to be able to reset KCPSM6 the arrangement below should be
// used to 'OR' your signal with 'rdl' from the program memory.
//
display_rom
program_rom ( //Name to match your PSM file
.enable (bram_enable),
.address (address),
.instruction (instruction),
.clk (clk));
assign kcpsm6_reset = cpu_reset;
endmodule // cpu
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211AI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__O211AI_PP_BLACKBOX_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211AI_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGNDNOVPB_SYMBOL_V
`define SKY130_FD_SC_LS__TAPVGNDNOVPB_SYMBOL_V
/**
* tapvgndnovpb: Substrate only tap cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapvgndnovpb ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGNDNOVPB_SYMBOL_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: engine_layer.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The engine layer encapsulates the RX and TX engines.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
`include "ultrascale.vh"
module engine_layer
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_LOG_NUM_TAGS=6,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_MAX_PAYLOAD_DWORDS = 64,
parameter C_VENDOR="ULTRASCALE"
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
input RX_TLP_VALID,
input RX_TLP_START_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
input RX_TLP_END_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
input [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
output RX_TLP_READY,
// Interface: TX Classic
input TX_TLP_READY,
output [C_PCI_DATA_WIDTH-1:0] TX_TLP,
output TX_TLP_VALID,
output TX_TLP_START_FLAG,
output [`SIG_OFFSET_W-1:0] TX_TLP_START_OFFSET,
output TX_TLP_END_FLAG,
output [`SIG_OFFSET_W-1:0] TX_TLP_END_OFFSET,
//Interface: CQ Ultrascale (RXR)
input M_AXIS_CQ_TVALID,
input M_AXIS_CQ_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_CQ_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_CQ_TKEEP,
input [`SIG_CQ_TUSER_W-1:0] M_AXIS_CQ_TUSER,
output M_AXIS_CQ_TREADY,
//Interface: RC Ultrascale (RXC)
input M_AXIS_RC_TVALID,
input M_AXIS_RC_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RC_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_RC_TKEEP,
input [`SIG_RC_TUSER_W-1:0] M_AXIS_RC_TUSER,
output M_AXIS_RC_TREADY,
//Interface: CC Ultrascale (TXC)
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER,
//Interface: RQ Ultrascale (TXR)
input S_AXIS_RQ_TREADY,
output S_AXIS_RQ_TVALID,
output S_AXIS_RQ_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_RQ_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_RQ_TKEEP,
output [`SIG_RQ_TUSER_W-1:0] S_AXIS_RQ_TUSER,
// Interface: RXC Engine
output [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
output RXC_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
output RXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
output RXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
output [`SIG_LBE_W-1:0] RXC_META_LDWBE,
output [`SIG_FBE_W-1:0] RXC_META_FDWBE,
output [`SIG_TAG_W-1:0] RXC_META_TAG,
output [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
output [`SIG_TYPE_W-1:0] RXC_META_TYPE,
output [`SIG_LEN_W-1:0] RXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
output [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
output RXC_META_EP,
// Interface: RXR Engine
output [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
output RXR_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
output RXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
output RXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
output [`SIG_FBE_W-1:0] RXR_META_FDWBE,
output [`SIG_LBE_W-1:0] RXR_META_LDWBE,
output [`SIG_TC_W-1:0] RXR_META_TC,
output [`SIG_ATTR_W-1:0] RXR_META_ATTR,
output [`SIG_TAG_W-1:0] RXR_META_TAG,
output [`SIG_TYPE_W-1:0] RXR_META_TYPE,
output [`SIG_ADDR_W-1:0] RXR_META_ADDR,
output [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
output [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
output [`SIG_LEN_W-1:0] RXR_META_LENGTH,
output RXR_META_EP,
// Interface: TXC Engine
input TXC_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
input TXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
input TXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
output TXC_DATA_READY,
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY,
output TXC_SENT,
// Interface: TXR Engine
input TXR_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
input TXR_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
input TXR_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
output TXR_DATA_READY,
input TXR_META_VALID,
input [`SIG_FBE_W-1:0] TXR_META_FDWBE,
input [`SIG_LBE_W-1:0] TXR_META_LDWBE,
input [`SIG_ADDR_W-1:0] TXR_META_ADDR,
input [`SIG_LEN_W-1:0] TXR_META_LENGTH,
input [`SIG_TAG_W-1:0] TXR_META_TAG,
input [`SIG_TC_W-1:0] TXR_META_TC,
input [`SIG_ATTR_W-1:0] TXR_META_ATTR,
input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
input TXR_META_EP,
output TXR_META_READY,
output TXR_SENT
);
generate
/* verilator lint_off WIDTH */
if(C_VENDOR != "ULTRASCALE") begin
assign M_AXIS_CQ_TREADY = 0;
assign M_AXIS_RC_TREADY = 0;
assign S_AXIS_CC_TVALID = 0;
assign S_AXIS_CC_TLAST = 0;
assign S_AXIS_CC_TDATA = 0;
assign S_AXIS_CC_TKEEP = 0;
assign S_AXIS_CC_TUSER = 0;
assign S_AXIS_RQ_TVALID = 0;
assign S_AXIS_RQ_TLAST = 0;
assign S_AXIS_RQ_TDATA = 0;
assign S_AXIS_RQ_TKEEP = 0;
assign S_AXIS_RQ_TUSER = 0;
/* verilator lint_on WIDTH */
rx_engine_classic
#(/*AUTOINSTPARAM*/
// Parameters
.C_VENDOR (C_VENDOR),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS))
rx_engine_classic_inst
(/*AUTOINST*/
// Outputs
.RX_TLP_READY (RX_TLP_READY),
.RXC_DATA (RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_VALID (RXC_DATA_VALID),
.RXC_DATA_WORD_ENABLE (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_START_FLAG (RXC_DATA_START_FLAG),
.RXC_DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (RXC_DATA_END_FLAG),
.RXC_DATA_END_OFFSET (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (RXC_META_LDWBE[`SIG_LBE_W-1:0]),
.RXC_META_FDWBE (RXC_META_FDWBE[`SIG_FBE_W-1:0]),
.RXC_META_TAG (RXC_META_TAG[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (RXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (RXC_META_TYPE[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (RXC_META_LENGTH[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING(RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (RXC_META_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.RXC_META_EP (RXC_META_EP),
.RXR_DATA (RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (RXR_DATA_VALID),
.RXR_DATA_WORD_ENABLE (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_START_FLAG (RXR_DATA_START_FLAG),
.RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (RXR_DATA_END_FLAG),
.RXR_DATA_END_OFFSET (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
.RXR_META_TC (RXR_META_TC[`SIG_TC_W-1:0]),
.RXR_META_ATTR (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (RXR_META_TAG[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (RXR_META_LENGTH[`SIG_LEN_W-1:0]),
.RXR_META_EP (RXR_META_EP),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.RX_TLP (RX_TLP[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (RX_TLP_VALID),
.RX_TLP_START_FLAG (RX_TLP_START_FLAG),
.RX_TLP_START_OFFSET (RX_TLP_START_OFFSET[`SIG_OFFSET_W-1:0]),
.RX_TLP_END_FLAG (RX_TLP_END_FLAG),
.RX_TLP_END_OFFSET (RX_TLP_END_OFFSET[`SIG_OFFSET_W-1:0]),
.RX_TLP_BAR_DECODE (RX_TLP_BAR_DECODE[`SIG_BARDECODE_W-1:0]));
tx_engine_classic
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
.C_VENDOR (C_VENDOR))
tx_engine_classic_inst
(/*AUTOINST*/
// Outputs
.TX_TLP (TX_TLP[C_PCI_DATA_WIDTH-1:0]),
.TX_TLP_VALID (TX_TLP_VALID),
.TX_TLP_START_FLAG (TX_TLP_START_FLAG),
.TX_TLP_START_OFFSET (TX_TLP_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TX_TLP_END_FLAG (TX_TLP_END_FLAG),
.TX_TLP_END_OFFSET (TX_TLP_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_READY (TXC_DATA_READY),
.TXC_META_READY (TXC_META_READY),
.TXC_SENT (TXC_SENT),
.TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY),
.TXR_SENT (TXR_SENT),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TX_TLP_READY (TX_TLP_READY),
.TXC_DATA_VALID (TXC_DATA_VALID),
.TXC_DATA (TXC_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (TXC_DATA_START_FLAG),
.TXC_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (TXC_DATA_END_FLAG),
.TXC_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (TXC_META_VALID),
.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
.TXC_META_EP (TXC_META_EP),
.TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP));
end else begin
assign TX_TLP = 0;
assign TX_TLP_VALID = 0;
assign TX_TLP_START_FLAG = 0;
assign TX_TLP_START_OFFSET = 0;
assign TX_TLP_END_FLAG = 0;
assign TX_TLP_END_OFFSET = 0;
assign RX_TLP_READY = 0;
rx_engine_ultrascale
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
rx_engine_ultrascale_inst
(/*AUTOINST*/
// Outputs
.M_AXIS_CQ_TREADY (M_AXIS_CQ_TREADY),
.M_AXIS_RC_TREADY (M_AXIS_RC_TREADY),
.RXC_DATA (RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_VALID (RXC_DATA_VALID),
.RXC_DATA_WORD_ENABLE (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_START_FLAG (RXC_DATA_START_FLAG),
.RXC_DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (RXC_DATA_END_FLAG),
.RXC_DATA_END_OFFSET (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (RXC_META_LDWBE[`SIG_LBE_W-1:0]),
.RXC_META_FDWBE (RXC_META_FDWBE[`SIG_FBE_W-1:0]),
.RXC_META_TAG (RXC_META_TAG[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (RXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (RXC_META_TYPE[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (RXC_META_LENGTH[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING(RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (RXC_META_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.RXC_META_EP (RXC_META_EP),
.RXR_DATA (RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (RXR_DATA_VALID),
.RXR_DATA_WORD_ENABLE (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_START_FLAG (RXR_DATA_START_FLAG),
.RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (RXR_DATA_END_FLAG),
.RXR_DATA_END_OFFSET (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
.RXR_META_TC (RXR_META_TC[`SIG_TC_W-1:0]),
.RXR_META_ATTR (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (RXR_META_TAG[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (RXR_META_LENGTH[`SIG_LEN_W-1:0]),
.RXR_META_EP (RXR_META_EP),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.M_AXIS_CQ_TVALID (M_AXIS_CQ_TVALID),
.M_AXIS_CQ_TLAST (M_AXIS_CQ_TLAST),
.M_AXIS_CQ_TDATA (M_AXIS_CQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (M_AXIS_CQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (M_AXIS_CQ_TUSER[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (M_AXIS_RC_TVALID),
.M_AXIS_RC_TLAST (M_AXIS_RC_TLAST),
.M_AXIS_RC_TDATA (M_AXIS_RC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (M_AXIS_RC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (M_AXIS_RC_TUSER[`SIG_RC_TUSER_W-1:0]));
tx_engine_ultrascale
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS))
tx_engine_ultrascale_inst
(/*AUTOINST*/
// Outputs
.S_AXIS_CC_TVALID (S_AXIS_CC_TVALID),
.S_AXIS_CC_TLAST (S_AXIS_CC_TLAST),
.S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
.TXC_DATA_READY (TXC_DATA_READY),
.TXC_META_READY (TXC_META_READY),
.TXC_SENT (TXC_SENT),
.S_AXIS_RQ_TVALID (S_AXIS_RQ_TVALID),
.S_AXIS_RQ_TLAST (S_AXIS_RQ_TLAST),
.S_AXIS_RQ_TDATA (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),
.TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY),
.TXR_SENT (TXR_SENT),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.S_AXIS_CC_TREADY (S_AXIS_CC_TREADY),
.TXC_DATA_VALID (TXC_DATA_VALID),
.TXC_DATA (TXC_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (TXC_DATA_START_FLAG),
.TXC_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (TXC_DATA_END_FLAG),
.TXC_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (TXC_META_VALID),
.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
.TXC_META_EP (TXC_META_EP),
.S_AXIS_RQ_TREADY (S_AXIS_RQ_TREADY),
.TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP));
end
endgenerate
endmodule // engine_layer
// Local Variables:
// verilog-library-directories:("." "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/")
// End:
|
module main(CLK,HSYNC,VSYNC,R,G,B,XCLK,PCLK,D,HIN,VIN);
input CLK;
output reg HSYNC;
output reg VSYNC;
output reg R;
output reg G;
output reg B;
output reg XCLK;
input PCLK;
input [7:0] D;
input HIN;
input VIN;
//hsync = 1589
//pulse = 191
//vsync = 834150
//pulse = 3200
reg [15:0] HCNT;
reg [15:0] VCNT;
reg drawH;
reg drawV;
reg [7:0] CAMDAT [1:0];
reg BCNT;
reg [15:0] PXCNT;
reg [15:0] PVCNT;
reg [255:0] RDAT [127:0];
reg [255:0] GDAT [127:0];
reg [255:0] BDAT [127:0];
reg CR;
reg CG;
reg CB;
always @(posedge PCLK)begin
if(VIN)
PVCNT <= 7'd0;
else
if(!HIN)begin
if(PXCNT != 8'h0)
PVCNT <= PVCNT + 7'd1;
BCNT <= 1'b0;
PXCNT <= 8'h0;
end else begin
BCNT <= !BCNT;
if(BCNT)
PXCNT <= PXCNT + 8'd1;
end
CAMDAT[BCNT] <= D;
end
always @(negedge CLK) begin
XCLK <= ~XCLK;
HCNT <= HCNT + 16'h1;
if(HCNT == 16'd1588)begin
HCNT <= 16'h0;
drawH <= 1'b1;
end else if(HCNT == 16'd1302)begin
HSYNC <= 1'b0;
VCNT <= VCNT + 16'h1;
end else if(HCNT == 16'd1493)begin
HSYNC <= 1'b1;
end else if(HCNT == 16'd1270)begin
drawH <= 1'b0;
end
if(VCNT == 16'd513)begin
VSYNC <= 1'b0;
end else if(VCNT == 16'd515)begin
VSYNC <= 1'b1;
end else if(VCNT == 16'd524)begin
drawV <= 1'b1;
VCNT <= 16'h0;
end else if(VCNT == 16'd480)begin
drawV <= 1'b0;
end
if(!BCNT && HIN && !VIN && PVCNT[15:8]==0 && PXCNT[15:9]==0) begin
RDAT[PVCNT[7:1]][PXCNT[8:1]] <= CAMDAT[1][6];
GDAT[PVCNT[7:1]][PXCNT[8:1]] <= CAMDAT[1][7];
BDAT[PVCNT[7:1]][PXCNT[8:1]] <= CAMDAT[1][5];
end
CR <= RDAT[VCNT[7:1]][HCNT[9:2]];
CG <= GDAT[VCNT[7:1]][HCNT[9:2]];
CB <= BDAT[VCNT[7:1]][HCNT[9:2]];
R <= drawH && drawV && CR;
G <= drawH && drawV && CG;
B <= drawH && drawV && CB;
end
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module DIGDUG_ROM (
clka,
addra,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [13 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(3),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("DIGDUG_ROM.mif"),
.C_INIT_FILE("DIGDUG_ROM.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(16384),
.C_READ_DEPTH_A(16384),
.C_ADDRA_WIDTH(14),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(16384),
.C_READ_DEPTH_B(16384),
.C_ADDRB_WIDTH(14),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("4"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.326399 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(1'B0),
.addra(addra),
.dina(8'B0),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(14'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 24.02.2016 19:15:37
// Design Name:
// Module Name: SPI_testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SPI_testbench();
parameter integer m = 16;
reg GCLK;
reg st;
reg LEFT;
reg RST;
wire MISO;
wire MOSI;
wire SS;
wire SCLK;
// I/O buffers
wire [m-1:0] MASTER_RX;
reg [m-1:0] MASTER_TX = 16'hdeaf;
wire [m-1:0] SLAVE_RX;
reg [m-1:0] SLAVE_TX = 16'b110101100110110;
wire clk_Tbit; // Clock for bit timing
/*
SPI_MASTER #(.m(m)) spi_master
(
.clk(GCLK),
.ce(clk_Tbit),
.st(st),
.SCLK(SCLK),
.MISO(MISO),
.MOSI(MOSI),
.LOAD(SS),
.TX_MD(MASTER_TX),
.RX_SD(MASTER_RX),
.LEFT(LEFT)
);*/
SPI_sender spi_master (
.CLK(GCLK),
.DATA(MASTER_TX),
.T_DIV(2),
.RST(RST),
.ST(st),
.SCK(SCLK),
.MOSI(MOSI),
.SS(SS)
);
SPI_SLAVE #(.m(m)) spi_slave
(
.RST(RST),
.SCLK(SCLK),
.MISO(MISO),
.MOSI(MOSI),
.SS(SS),
.DIN(SLAVE_TX),
.DOUT(SLAVE_RX)
);
/*
CLK_DIV clk_div
(
.GCLK(GCLK),
.out(clk_Tbit),
.T(64'd2)
);
*/
always begin
GCLK = 1'b0;
#10;
GCLK = 1'b1;
#10;
end
initial begin
GCLK = 1'b0;
st = 1'b0;
LEFT = 1'b1;
RST = 1'b0;
#100
st = 1'b1;
#200
st = 1'b0;
#11000
MASTER_TX = 16'habcd;
st = 1'b1;
#200
st = 1'b0;
#8000
$finish;
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD3_1_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD3_1_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog wrapper for dlygate4sd3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlygate4sd3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlygate4sd3_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dlygate4sd3 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlygate4sd3_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dlygate4sd3 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD3_1_V
|
// File: memory_array.v
// Generated by MyHDL 0.10
// Date: Mon Aug 27 20:10:17 2018
`timescale 1ns/10ps
module memory_array (
data_in,
fifo_we,
wptr,
rptr,
data_out,
clk,
clear
);
// Input:
// data_in(8bit): data to be writen
// fifo_we(bool): write enable
// wptr(5bit): write memory address pointer
// rptr(5bit): read memory address pointer
// clk(bool): clock
// clear(bool): signal to clear clear memeory to 0
// Ouput:
// data_out(8bit): data to be read out based on`rptr`
input [7:0] data_in;
input fifo_we;
input [4:0] wptr;
input [4:0] rptr;
output [7:0] data_out;
wire [7:0] data_out;
input clk;
input clear;
reg [7:0] data_out_i [0:16-1];
initial begin: INITIALIZE_DATA_OUT_I
integer i;
for(i=0; i<16; i=i+1) begin
data_out_i[i] = 0;
end
end
always @(posedge clk) begin: MEMORY_ARRAY_UPTAKE
if (fifo_we) begin
data_out_i[wptr[4-1:0]] <= data_in;
end
end
assign data_out = data_out_i[rptr[4-1:0]];
always @(negedge clear) begin: MEMORY_ARRAY_CLEARMEM
integer i;
for (i=0; i<16; i=i+1) begin
data_out_i[i] <= 0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S6S_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLYMETAL6S6S_FUNCTIONAL_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__dlymetal6s6s (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S6S_FUNCTIONAL_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:39:25 01/29/2016
// Design Name: control_unit
// Module Name: /home/poche002/Desktop/ArqComp/Trabajo_final/arquitectura_tpf/control_unit_tb.v
// Project Name: arquitectura_tpf
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: control_unit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module control_unit_tb;
// Inputs
reg clk;
reg [31:0] instruction;
// Outputs
wire [3:0] ex_ctrl_sgnl;
wire [2:0] mem_ctrl_sgnl;
wire [1:0] wb_ctrl_sgnl;
// Instantiate the Unit Under Test (UUT)
control_unit uut (
.clk(clk),
.instruction(instruction),
.ex_ctrl_sgnl(ex_ctrl_sgnl),
.mem_ctrl_sgnl(mem_ctrl_sgnl),
.wb_ctrl_sgnl(wb_ctrl_sgnl)
);
initial begin
// Initialize Inputs
clk = 0;
instruction = 0;
// Wait 100 ns for global reset to finish
#10;
// Add stimulus here
#10 instruction = 32'b00000000_00000000_00000000_00000000; //r-type
#10 instruction = 32'b10001100_00000000_00000000_00000000; //lw
#10 instruction = 32'b10101100_00000000_00000000_00000000; //sw
#10 instruction = 32'b00010000_00000000_00000000_00000000; //beq
end
always
#1 clk=~clk;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVPWRVGND_SYMBOL_V
`define SKY130_FD_SC_MS__TAPVPWRVGND_SYMBOL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapvpwrvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVPWRVGND_SYMBOL_V
|
// Code generated by Icestudio 0.8.1w202112300112
`default_nettype none
//---- Top entity
module main (
input [1:0] v38003d,
output [1:0] v81f397,
output [1:0] vb6741a
);
wire [0:1] w0;
wire [0:1] w1;
wire [0:1] w2;
assign w0 = v38003d;
assign v81f397 = w0;
assign vb6741a = w1;
assign w2 = v38003d;
assign w2 = w0;
v76f7ce v6ccb58 (
.v8fd8fb(w1),
.va8fcbc(w2)
);
endmodule
//---- Top entity
module v76f7ce (
input [1:0] va8fcbc,
output [1:0] v8fd8fb
);
wire [0:1] w0;
wire [0:1] w1;
wire w2;
wire w3;
wire w4;
wire w5;
assign w0 = va8fcbc;
assign v8fd8fb = w1;
v0dbcb9 v7d1cb8 (
.v8b19dd(w0),
.v3f8943(w2),
.v64d863(w4)
);
v80ac84 v1cc6f4 (
.v67a3fc(w1),
.vee8a83(w3),
.v03aaf0(w5)
);
v3676a0 v214cf3 (
.v0e28cb(w2),
.vcbab45(w3)
);
v3676a0 v8b12b1 (
.v0e28cb(w4),
.vcbab45(w5)
);
endmodule
//---------------------------------------------------
//-- not-x2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- not-x2: 2-bits not gate
//---------------------------------------------------
//---- Top entity
module v0dbcb9 (
input [1:0] v8b19dd,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire [0:1] w2;
assign v3f8943 = w0;
assign v64d863 = w1;
assign w2 = v8b19dd;
v0dbcb9_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.i(w2)
);
endmodule
//---------------------------------------------------
//-- Bus2-Split-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus2-Split-all: Split the 2-bits bus into two wires
//---------------------------------------------------
module v0dbcb9_v9a2a06 (
input [1:0] i,
output o1,
output o0
);
assign o1 = i[1];
assign o0 = i[0];
endmodule
//---- Top entity
module v80ac84 (
input vee8a83,
input v03aaf0,
output [1:0] v67a3fc
);
wire w0;
wire w1;
wire [0:1] w2;
assign w0 = vee8a83;
assign w1 = v03aaf0;
assign v67a3fc = w2;
v80ac84_v9a2a06 v9a2a06 (
.i1(w0),
.i0(w1),
.o(w2)
);
endmodule
//---------------------------------------------------
//-- Bus2-Join-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus2-Join-all: Joint two wires into a 2-bits Bus
//---------------------------------------------------
module v80ac84_v9a2a06 (
input i1,
input i0,
output [1:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module v3676a0 (
input v0e28cb,
output vcbab45
);
wire w0;
wire w1;
assign w0 = v0e28cb;
assign vcbab45 = w1;
v3676a0_vd54ca1 vd54ca1 (
.a(w0),
.q(w1)
);
endmodule
//---------------------------------------------------
//-- NOT
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- NOT gate (Verilog implementation)
//---------------------------------------------------
module v3676a0_vd54ca1 (
input a,
output q
);
//-- NOT Gate
assign q = ~a;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFBUF_SYMBOL_V
`define SKY130_FD_SC_LP__BUFBUF_SYMBOL_V
/**
* bufbuf: Double buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bufbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFBUF_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_BEHAVIORAL_V
`define SKY130_FD_SC_LP__OR4_BEHAVIORAL_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__or4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2_8_V
`define SKY130_FD_SC_HD__NOR2_8_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor2_8 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor2_8 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2_8_V
|
//# 3 inputs
//# 6 outputs
//# 21 D-type flipflops
//# 62 inverters
//# 119 gates (13 ANDs + 58 NANDs + 14 ORs + 34 NORs)
module dff (CK,Q,D);
input CK,D;
output Q;
wire NM,NCK;
trireg NQ,M;
nmos N7 (M,D,NCK);
not P3 (NM,M);
nmos N9 (NQ,NM,CK);
not P5 (Q,NQ);
not P1 (NCK,CK);
endmodule
module s444(GND,VDD,CK,G0,G1,G107,G108,G118,G119,G167,G168,G2);
input GND,VDD,CK,G0,G1,G2;
output G118,G167,G107,G119,G168,G108;
wire G11,G37,G12,G41,G13,G45,G14,G49,G15,G58,G16,G62,G17,G66,G18,G70,G19,G80,
G20,G84,G21,G88,G22,G92,G23,G101,G24,G162BF,G25,G109,G26,G110,G27,G111,G28,
G112,G29,G113,G30,G114,G31,G155,IIII372,IIII382,IIII318,G34,IIII180,G35,
G77,G135,G36,G78,G144,G32,G74,G142,IIII392,G55,G102,G136,G156,G56,G143,
G161,IIII321,G53,IIII324,G76,G150,IIII336,G152,G160,G106,G43,IIII182,G99,
G139,G153,G157,G103,G38,G40,G60,G57,G79,G97,G42,G44,G46,G48,IIII105,G162,
G166,G50,G52,G82,G59,G61,G63,G65,G67,G69,G71,G73,G81,G83,G85,G87,G89,G91,
G94,G96,G122,G121,G124,G125,G126,G127,G154,G158,G159,G100,G104,G105,G115,
G117,G163,G165,G116,G164,G141,G137,G138,G140,G133,G134,G145,G146,G147,G131,
G129,IIII181,IIII190,IIII200,G47,IIII210,G51,G120,G128,G132,G123,G151,
IIII191,IIII192,IIII201,IIII202,G149,G130,IIII211,IIII212,G148,IIII225,
IIII235,G64,IIII245,G68,IIII255,G72,IIII226,IIII227,IIII236,IIII237,
IIII246,IIII247,IIII256,IIII257,IIII271,IIII281,G86,IIII291,G90,IIII302,
G95,IIII272,IIII273,IIII282,IIII283,IIII292,IIII293,IIII303,IIII304,G33,
G54,G75,G98,G93;
dff DFF_0(CK,G11,G37);
dff DFF_1(CK,G12,G41);
dff DFF_2(CK,G13,G45);
dff DFF_3(CK,G14,G49);
dff DFF_4(CK,G15,G58);
dff DFF_5(CK,G16,G62);
dff DFF_6(CK,G17,G66);
dff DFF_7(CK,G18,G70);
dff DFF_8(CK,G19,G80);
dff DFF_9(CK,G20,G84);
dff DFF_10(CK,G21,G88);
dff DFF_11(CK,G22,G92);
dff DFF_12(CK,G23,G101);
dff DFF_13(CK,G24,G162BF);
dff DFF_14(CK,G25,G109);
dff DFF_15(CK,G26,G110);
dff DFF_16(CK,G27,G111);
dff DFF_17(CK,G28,G112);
dff DFF_18(CK,G29,G113);
dff DFF_19(CK,G30,G114);
dff DFF_20(CK,G31,G155);
not NOT_0(IIII372,G0);
not NOT_1(IIII382,G1);
not NOT_2(IIII318,G2);
not NOT_3(G34,G11);
not NOT_4(IIII180,G11);
not NOT_5(G35,G12);
not NOT_6(G77,G20);
not NOT_7(G135,G20);
not NOT_8(G36,G13);
not NOT_9(G78,G21);
not NOT_10(G144,G21);
not NOT_11(G32,G14);
not NOT_12(G74,G22);
not NOT_13(G142,G22);
not NOT_14(IIII392,G30);
not NOT_15(G55,G15);
not NOT_16(G102,G23);
not NOT_17(G136,G23);
not NOT_18(G156,G31);
not NOT_19(G56,G16);
not NOT_20(G143,G24);
not NOT_21(G161,G17);
not NOT_22(IIII321,G25);
not NOT_23(G53,G18);
not NOT_24(IIII324,G26);
not NOT_25(G76,G19);
not NOT_26(G150,G19);
not NOT_27(IIII336,G27);
not NOT_28(G119,G28);
not NOT_29(G167,G29);
not NOT_30(G152,IIII372);
not NOT_31(G160,IIII382);
not NOT_32(G106,IIII318);
not NOT_33(G43,G34);
not NOT_34(IIII182,IIII180);
not NOT_35(G168,IIII392);
not NOT_36(G107,IIII321);
not NOT_37(G108,IIII324);
not NOT_38(G118,IIII336);
not NOT_39(G99,G152);
not NOT_40(G139,G152);
not NOT_41(G153,G152);
not NOT_42(G157,G160);
not NOT_43(G103,G106);
not NOT_44(G38,G40);
not NOT_45(G60,G57);
not NOT_46(G79,G97);
not NOT_47(G42,G44);
not NOT_48(G46,G48);
not NOT_49(IIII105,G162);
not NOT_50(G166,G162);
not NOT_51(G50,G52);
not NOT_52(G82,G79);
not NOT_53(G162BF,IIII105);
not NOT_54(G59,G61);
not NOT_55(G63,G65);
not NOT_56(G67,G69);
not NOT_57(G71,G73);
not NOT_58(G81,G83);
not NOT_59(G85,G87);
not NOT_60(G89,G91);
not NOT_61(G94,G96);
and AND2_0(G122,G24,G121);
and AND3_0(G124,G139,G22,G150);
and AND3_1(G125,G139,G20,G19);
and AND2_1(G126,G139,G21);
and AND2_2(G127,G139,G24);
and AND2_3(G154,G158,G159);
and AND2_4(G100,G104,G105);
and AND2_5(G155,G154,G153);
and AND2_6(G101,G100,G99);
and AND3_2(G115,G161,G117,G162);
and AND3_3(G163,G161,G165,G162);
and AND2_7(G116,G117,G166);
and AND2_8(G164,G165,G166);
or OR3_0(G141,G24,G22,G21);
or OR3_1(G137,G136,G20,G19);
or OR2_0(G138,G136,G142);
or OR4_0(G140,G24,G21,G20,G150);
or OR4_1(G133,G152,G136,G22,G144);
or OR3_2(G134,G152,G142,G21);
or OR4_2(G145,G152,G142,G20,G19);
or OR2_1(G146,G152,G143);
or OR2_2(G147,G152,G144);
or OR2_3(G158,G31,G160);
or OR2_4(G104,G23,G106);
or OR4_3(G131,G144,G22,G23,G129);
or OR2_5(G159,G156,G157);
or OR2_6(G105,G102,G103);
nand NAND2_0(IIII181,G11,IIII180);
nand NAND2_1(G129,G19,G135);
nand NAND4_0(G121,G19,G135,G142,G136);
nand NAND2_2(IIII190,G12,G43);
nand NAND2_3(G40,IIII181,IIII182);
nand NAND2_4(IIII200,G13,G47);
nand NAND2_5(IIII210,G14,G51);
nand NAND2_6(G120,G150,G128);
nand NAND2_7(G132,G133,G134);
nand NAND3_0(G111,G140,G141,G139);
nand NAND4_1(G123,G137,G138,G21,G139);
nand NAND4_2(G151,G20,G144,G143,G139);
nand NAND3_1(G117,G145,G146,G147);
nand NAND2_8(IIII191,G12,IIII190);
nand NAND2_9(IIII192,G43,IIII190);
nand NAND2_10(IIII201,G13,IIII200);
nand NAND2_11(IIII202,G47,IIII200);
nand NAND2_12(G149,G131,G130);
nand NAND2_13(IIII211,G14,IIII210);
nand NAND2_14(IIII212,G51,IIII210);
nand NAND3_2(G148,G150,G135,G132);
nand NAND2_15(G44,IIII191,IIII192);
nand NAND2_16(G48,IIII201,IIII202);
nand NAND2_17(G162,G120,G149);
nand NAND2_18(G52,IIII211,IIII212);
nand NAND2_19(IIII225,G15,G60);
nand NAND2_20(IIII235,G16,G64);
nand NAND2_21(IIII245,G17,G68);
nand NAND2_22(IIII255,G18,G72);
nand NAND2_23(G165,G148,G149);
nand NAND2_24(IIII226,G15,IIII225);
nand NAND2_25(IIII227,G60,IIII225);
nand NAND2_26(IIII236,G16,IIII235);
nand NAND2_27(IIII237,G64,IIII235);
nand NAND2_28(IIII246,G17,IIII245);
nand NAND2_29(IIII247,G68,IIII245);
nand NAND2_30(IIII256,G18,IIII255);
nand NAND2_31(IIII257,G72,IIII255);
nand NAND2_32(G61,IIII226,IIII227);
nand NAND2_33(G65,IIII236,IIII237);
nand NAND2_34(G69,IIII246,IIII247);
nand NAND2_35(G73,IIII256,IIII257);
nand NAND2_36(IIII271,G19,G82);
nand NAND2_37(IIII281,G20,G86);
nand NAND2_38(IIII291,G21,G90);
nand NAND2_39(IIII302,G22,G95);
nand NAND2_40(IIII272,G19,IIII271);
nand NAND2_41(IIII273,G82,IIII271);
nand NAND2_42(IIII282,G20,IIII281);
nand NAND2_43(IIII283,G86,IIII281);
nand NAND2_44(IIII292,G21,IIII291);
nand NAND2_45(IIII293,G90,IIII291);
nand NAND2_46(IIII303,G22,IIII302);
nand NAND2_47(IIII304,G95,IIII302);
nand NAND2_48(G83,IIII272,IIII273);
nand NAND2_49(G87,IIII282,IIII283);
nand NAND2_50(G91,IIII292,IIII293);
nand NAND2_51(G96,IIII303,IIII304);
nor NOR3_0(G33,G11,G12,G13);
nor NOR3_1(G54,G15,G16,G17);
nor NOR3_2(G75,G19,G20,G21);
nor NOR2_0(G47,G34,G35);
nor NOR3_3(G51,G34,G35,G36);
nor NOR2_1(G98,G32,G33);
nor NOR4_0(G128,G20,G144,G136,G152);
nor NOR2_2(G130,G143,G152);
nor NOR2_3(G57,G31,G98);
nor NOR2_4(G64,G55,G57);
nor NOR3_4(G68,G55,G56,G57);
nor NOR4_1(G72,G55,G56,G161,G57);
nor NOR3_5(G97,G53,G57,G54);
nor NOR2_5(G109,G122,G123);
nor NOR4_2(G110,G124,G125,G126,G127);
nor NOR2_6(G114,G150,G151);
nor NOR3_6(G37,G98,G38,G152);
nor NOR2_7(G86,G76,G79);
nor NOR3_7(G90,G76,G77,G79);
nor NOR3_8(G93,G74,G79,G75);
nor NOR4_3(G95,G76,G77,G78,G79);
nor NOR3_9(G41,G98,G42,G152);
nor NOR3_10(G45,G98,G46,G152);
nor NOR3_11(G49,G98,G50,G152);
nor NOR2_8(G112,G115,G116);
nor NOR2_9(G113,G163,G164);
nor NOR3_12(G58,G97,G59,G152);
nor NOR3_13(G62,G97,G63,G152);
nor NOR3_14(G66,G97,G67,G152);
nor NOR3_15(G70,G97,G71,G152);
nor NOR3_16(G80,G93,G81,G152);
nor NOR3_17(G84,G93,G85,G152);
nor NOR3_18(G88,G93,G89,G152);
nor NOR3_19(G92,G93,G94,G152);
endmodule
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core
(
/*
* Clock: 156.25MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire [3:0] btn,
input wire [3:0] sw,
output wire [3:0] led,
output wire [3:0] led_bkt,
output wire [6:0] led_hex0_d,
output wire led_hex0_dp,
output wire [6:0] led_hex1_d,
output wire led_hex1_dp,
/*
* 10G Ethernet
*/
output wire [63:0] sfp_a_txd,
output wire [7:0] sfp_a_txc,
input wire [63:0] sfp_a_rxd,
input wire [7:0] sfp_a_rxc,
output wire [63:0] sfp_b_txd,
output wire [7:0] sfp_b_txc,
input wire [63:0] sfp_b_rxd,
input wire [7:0] sfp_b_rxc,
output wire [63:0] sfp_c_txd,
output wire [7:0] sfp_c_txc,
input wire [63:0] sfp_c_rxd,
input wire [7:0] sfp_c_rxc,
output wire [63:0] sfp_d_txd,
output wire [7:0] sfp_d_txc,
input wire [63:0] sfp_d_rxd,
input wire [7:0] sfp_d_rxc
);
// AXI between MAC and Ethernet modules
wire [63:0] rx_axis_tdata;
wire [7:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [63:0] tx_axis_tdata;
wire [7:0] tx_axis_tkeep;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [63:0] rx_eth_payload_axis_tdata;
wire [7:0] rx_eth_payload_axis_tkeep;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [63:0] tx_eth_payload_axis_tdata;
wire [7:0] tx_eth_payload_axis_tkeep;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [63:0] rx_ip_payload_axis_tdata;
wire [7:0] rx_ip_payload_axis_tkeep;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [63:0] tx_ip_payload_axis_tdata;
wire [7:0] tx_ip_payload_axis_tkeep;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [63:0] rx_udp_payload_axis_tdata;
wire [7:0] rx_udp_payload_axis_tkeep;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [63:0] tx_udp_payload_axis_tdata;
wire [7:0] tx_udp_payload_axis_tkeep;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [63:0] rx_fifo_udp_payload_axis_tdata;
wire [7:0] rx_fifo_udp_payload_axis_tkeep;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [63:0] tx_fifo_udp_payload_axis_tdata;
wire [7:0] tx_fifo_udp_payload_axis_tkeep;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tkeep = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
end
end
//assign led = sw;
assign led = led_reg;
assign led_bkt = led_reg;
assign led_hex0_d = 7'h00;
assign led_hex0_dp = 1'b0;
assign led_hex1_d = 7'h00;
assign led_hex1_dp = 1'b0;
assign sfp_b_txd = 64'h0707070707070707;
assign sfp_b_txc = 8'hff;
assign sfp_c_txd = 64'h0707070707070707;
assign sfp_c_txc = 8'hff;
assign sfp_d_txd = 64'h0707070707070707;
assign sfp_d_txc = 8'hff;
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(clk),
.rx_rst(rst),
.tx_clk(clk),
.tx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.xgmii_rxd(sfp_a_rxd),
.xgmii_rxc(sfp_a_rxc),
.xgmii_txd(sfp_a_txd),
.xgmii_txc(sfp_a_txc),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
);
eth_axis_rx #(
.DATA_WIDTH(64)
)
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx #(
.DATA_WIDTH(64)
)
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tkeep(tx_axis_tkeep),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete_64
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(1'b0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
`resetall
|
//b12015 Rohit Patiyal
`include "ALU/Arith/Signed/SSubtractor/mux32to16.v" //`
`include "ALU/Arith/Signed/SSubtractor/mux48to16.v" //`
`include "ALU/Arith/Signed/SAdder/SAdder.v"
`include "ALU/Arith/Signed/SSubtractor/SSubtractor.v"
`include "ALU/Arith/Signed/SDivider/SDivider.v"
`include "ALU/Arith/Signed/SMultiplier/SMultiplier.v"
//`include "ALU/mux4to1.v"//`
module Signed(output [31:0] Answer, input [31:0] A,input [31:0] B,input [1:0] OpCode);
output [31:0] Sum;
output [31:0] Difference;
output [63:0] Product;
output [31:0] Quotient;
output [31:0] Remainder;
wire carry_out;
wire overflow;
// SDivider myDiv(Quotient, Remainder, A, B);
// SAdder myAdder(Sum, carry_out, overflow, A, B ,0);
// SDivider myDiv3(Difference, Remainder, A, B);
SAdder myAdd(Sum, Remainder, A, B);
SSubtractor mySub(Difference, Remainder, A, B);
SMultiplier myProduct(Product, A, B);
SDivider myDiv(Quotient, Remainder, A, B);
genvar i;
generate for(i=0;i<32;i=i+1) begin: muxingthebits
mux4to1 m(Answer[i], Sum[i], Difference[i], Product[i], Quotient[i], OpCode);
end endgenerate
endmodule |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cl_efc_jbus.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: bw_clk_cl_efc_jbus (efc clock cluster header)
// Description: This block contains efc clock cluster header.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h" // definitions common at the iop level
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module bw_clk_cl_efc_jbus (/*AUTOARG*/
// Outputs
dbginit_l, cluster_grst_l, rclk, so,
// Inputs
gclk, cluster_cken, arst_l, grst_l, adbginit_l, gdbginit_l, si,
se
);
////////////////////////////////////////////////////////////////////
// Local defines
////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////
// Outputs
output dbginit_l;
output cluster_grst_l;
output rclk;
output so;
// Inputs
input gclk;
input cluster_cken;
input arst_l;
input grst_l;
input adbginit_l;
input gdbginit_l;
input si;
input se;
////////////////////////////////////////////////////////////////////
// Code start here
////////////////////////////////////////////////////////////////////
cluster_header cluster_header (/*AUTOINST*/
// Outputs
.dbginit_l(dbginit_l),
.cluster_grst_l(cluster_grst_l),
.rclk(rclk),
.so (so),
// Inputs
.gclk(gclk),
.cluster_cken(cluster_cken),
.arst_l(arst_l),
.grst_l(grst_l),
.adbginit_l(adbginit_l),
.gdbginit_l(gdbginit_l),
.si (si),
.se (se));
endmodule // bw_clk_cl_efc_jbus
// Local Variables:
// verilog-library-directories:("." "../../common/rtl/")
// End:
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Wed Jul 16 10:16:52 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_b.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:13 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.19 2003/07/09 07:52:44 wig Exp
//
// Generator: mix_0.pl Revision: 1.13 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
'timescale 1ns / 1ns;
//
//
// Start of Generated Module rtl of ent_b
//
module ent_b
//
// Generated module inst_b
//
(
port_b_1,
port_b_3,
port_b_4,
port_b_5_1,
port_b_5_2,
port_b_6i,
port_b_6o,
sig_07,
sig_08,
);
// Generated Module Inputs:
input port_b_1;
input port_b_3;
input port_b_5_1;
input port_b_5_2;
input [3:0] port_b_6i;
input [5:0] sig_07;
input [8:2] sig_08;
// Generated Module Outputs:
output port_b_4;
output [3:0] port_b_6o;
// Generated Wires:
wire port_b_1;
wire port_b_3;
wire port_b_4;
wire port_b_5_1;
wire port_b_5_2;
wire [3:0] port_b_6i;
wire [3:0] port_b_6o;
wire [5:0] sig_07;
wire [8:2] sig_08;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//TODO: %VERI_CONSTANTS%
// %VERI_CONCURS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_ba
ent_ba inst_ba(
);// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb(
);// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Tue Jul 22 11:18:49 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_b.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:13 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.21 2003/07/17 12:10:43 wig Exp
//
// Generator: mix_0.pl Revision: 1.13 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps;
//
//
// Start of Generated Module rtl of ent_b
//
// No `defines in this module
module ent_b
//
// Generated module inst_b
//
(
port_b_1,
port_b_3,
port_b_4,
port_b_5_1,
port_b_5_2,
port_b_6i,
port_b_6o,
sig_07,
sig_08,
);
// Generated Module Inputs:
input port_b_1;
input port_b_3;
input port_b_5_1;
input port_b_5_2;
input [3:0] port_b_6i;
input [5:0] sig_07;
input [8:2] sig_08;
// Generated Module Outputs:
output port_b_4;
output [3:0] port_b_6o;
// Generated Wires:
wire port_b_1;
wire port_b_3;
wire port_b_4;
wire port_b_5_1;
wire port_b_5_2;
wire [3:0] port_b_6i;
wire [3:0] port_b_6o;
wire [5:0] sig_07;
wire [8:2] sig_08;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//TODO: %VERI_CONSTANTS%
// %VERI_CONCURS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_ba
ent_ba inst_ba(
);// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb(
);// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Tue Aug 12 16:53:17 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_b.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:13 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.24 2003/08/11 07:16:25 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_b
//
// No `defines in this module
module ent_b
//
// Generated module inst_b
//
(
port_b_1,
port_b_3,
port_b_4,
port_b_5_1,
port_b_5_2,
port_b_6i,
port_b_6o,
sig_07,
sig_08,
);
// Generated Module Inputs:
input port_b_1;
input port_b_3;
input port_b_5_1;
input port_b_5_2;
input [3:0] port_b_6i;
input [5:0] sig_07;
input [8:2] sig_08;
// Generated Module Outputs:
output port_b_4;
output [3:0] port_b_6o;
// Generated Wires:
wire port_b_1;
wire port_b_3;
wire port_b_4;
wire port_b_5_1;
wire port_b_5_2;
wire [3:0] port_b_6i;
wire [3:0] port_b_6o;
wire [5:0] sig_07;
wire [8:2] sig_08;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_ba
ent_ba inst_ba(
);// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb(
);// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Mon Sep 8 17:52:50 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_b.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:13 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_b
//
// No `defines in this module
module ent_b
//
// Generated module inst_b
//
(
port_b_1,
port_b_3,
port_b_4,
port_b_5_1,
port_b_5_2,
port_b_6i,
port_b_6o,
sig_07,
sig_08,
);
// Generated Module Inputs:
input port_b_1;
input port_b_3;
input port_b_5_1;
input port_b_5_2;
input [3:0] port_b_6i;
input [5:0] sig_07;
input [8:2] sig_08;
// Generated Module Outputs:
output port_b_4;
output [3:0] port_b_6o;
// Generated Wires:
wire port_b_1;
wire port_b_3;
wire port_b_4;
wire port_b_5_1;
wire port_b_5_2;
wire [3:0] port_b_6i;
wire [3:0] port_b_6o;
wire [5:0] sig_07;
wire [8:2] sig_08;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_ba
ent_ba inst_ba(
);
// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb(
);
// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Wed Oct 8 09:51:06 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_b.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:13 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_b
//
// No `defines in this module
module ent_b
//
// Generated module inst_b
//
(
port_b_1,
port_b_3,
port_b_4,
port_b_5_1,
port_b_5_2,
port_b_6i,
port_b_6o,
sig_07,
sig_08
);
// Generated Module Inputs:
input port_b_1;
input port_b_3;
input port_b_5_1;
input port_b_5_2;
input [3:0] port_b_6i;
input [5:0] sig_07;
input [8:2] sig_08;
// Generated Module Outputs:
output port_b_4;
output [3:0] port_b_6o;
// Generated Wires:
wire port_b_1;
wire port_b_3;
wire port_b_4;
wire port_b_5_1;
wire port_b_5_2;
wire [3:0] port_b_6i;
wire [3:0] port_b_6o;
wire [5:0] sig_07;
wire [8:2] sig_08;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_ba
ent_ba inst_ba(
);
// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb(
);
// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Wed Oct 8 10:24:03 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_b.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:13 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_b
//
// No `defines in this module
module ent_b
//
// Generated module inst_b
//
(
port_b_1,
port_b_3,
port_b_4,
port_b_5_1,
port_b_5_2,
port_b_6i,
port_b_6o,
sig_07,
sig_08
);
// Generated Module Inputs:
input port_b_1;
input port_b_3;
input port_b_5_1;
input port_b_5_2;
input [3:0] port_b_6i;
input [5:0] sig_07;
input [8:2] sig_08;
// Generated Module Outputs:
output port_b_4;
output [3:0] port_b_6o;
// Generated Wires:
wire port_b_1;
wire port_b_3;
wire port_b_4;
wire port_b_5_1;
wire port_b_5_2;
wire [3:0] port_b_6i;
wire [3:0] port_b_6o;
wire [5:0] sig_07;
wire [8:2] sig_08;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_ba
ent_ba inst_ba(
);
// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb(
);
// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Mon Oct 13 09:32:34 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_b.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:13 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_b
//
// No `defines in this module
module ent_b
//
// Generated module inst_b
//
(
port_b_1,
port_b_3,
port_b_4,
port_b_5_1,
port_b_5_2,
port_b_6i,
port_b_6o,
sig_07,
sig_08
);
// Generated Module Inputs:
input port_b_1;
input port_b_3;
input port_b_5_1;
input port_b_5_2;
input [3:0] port_b_6i;
input [5:0] sig_07;
input [8:2] sig_08;
// Generated Module Outputs:
output port_b_4;
output [3:0] port_b_6o;
// Generated Wires:
wire port_b_1;
wire port_b_3;
wire port_b_4;
wire port_b_5_1;
wire port_b_5_2;
wire [3:0] port_b_6i;
wire [3:0] port_b_6o;
wire [5:0] sig_07;
wire [8:2] sig_08;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_ba
ent_ba inst_ba(
);
// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb(
);
// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Thu Nov 6 15:57:35 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_b.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:13 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.17 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_b
//
// No `defines in this module
module ent_b
//
// Generated module inst_b
//
(
port_b_1,
port_b_3,
port_b_4,
port_b_5_1,
port_b_5_2,
port_b_6i,
port_b_6o,
sig_07,
sig_08
);
// Generated Module Inputs:
input port_b_1;
input port_b_3;
input port_b_5_1;
input port_b_5_2;
input [3:0] port_b_6i;
input [5:0] sig_07;
input [8:2] sig_08;
// Generated Module Outputs:
output port_b_4;
output [3:0] port_b_6o;
// Generated Wires:
wire port_b_1;
wire port_b_3;
wire port_b_4;
wire port_b_5_1;
wire port_b_5_2;
wire [3:0] port_b_6i;
wire [3:0] port_b_6o;
wire [5:0] sig_07;
wire [8:2] sig_08;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_ba
ent_ba inst_ba(
);
// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb(
);
// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Fri Jul 15 12:55:13 2005
// cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_b.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
//
// Generator: mix_0.pl Revision: 1.36 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_b
//
// No `defines in this module
module ent_b
//
// Generated module inst_b
//
(
port_b_1,
port_b_3,
port_b_4,
port_b_5_1,
port_b_5_2,
port_b_6i,
port_b_6o,
sig_07,
sig_08
);
// Generated Module Inputs:
input port_b_1;
input port_b_3;
input port_b_5_1;
input port_b_5_2;
input [3:0] port_b_6i;
input [5:0] sig_07;
input [8:2] sig_08;
// Generated Module Outputs:
output port_b_4;
output [3:0] port_b_6o;
// Generated Wires:
wire port_b_1;
wire port_b_3;
wire port_b_4;
wire port_b_5_1;
wire port_b_5_2;
wire [3:0] port_b_6i;
wire [3:0] port_b_6o;
wire [5:0] sig_07;
wire [8:2] sig_08;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_ba
ent_ba inst_ba (
);
// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb (
);
// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAHCON_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__FAHCON_PP_BLACKBOX_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAHCON_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGSBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SREGSBP_PP_BLACKBOX_V
/**
* sregsbp: ????.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sregsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
ASYNC,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input ASYNC;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGSBP_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_V |
Require Import List.
Import ListNotations.
Require Import StructTact.StructTactics.
Require Import StructTact.Util.
Require Import InfSeqExt.infseq.
Require Import InfSeqExt.classical.
Require Import Verdi.DynamicNet.
Require Import Chord.InfSeqTactics.
Require Import Chord.Chord.
Require Import Chord.HandlerLemmas.
Require Import Chord.SystemLemmas.
Require Import Chord.SystemReachable.
Require Import Chord.SystemPointers.
Require Import Chord.LiveNodesStayLive.
Require Import Chord.NodesHaveState.
Require Import Chord.QueryInvariant.
Require Import Chord.TimeoutMeansActive.
Require Import Chord.ValidPointersInvariant.
Require Import Chord.LabeledLemmas.
Require Import Chord.LabeledMeasures.
Set Bullet Behavior "Strict Subproofs".
Lemma reachable_st_lb_execution_cons :
forall o o' ex,
lb_execution (Cons o (Cons o' ex)) ->
reachable_st (occ_gst o) ->
reachable_st (occ_gst o').
Proof using.
intros.
inv_lb_execution.
eauto using reachableStep, labeled_step_is_unlabeled_step.
Qed.
Lemma reachable_st_always :
forall ex,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
always ((fun ex' => reachable_st (occ_gst (hd ex'))) /\_ lb_execution) ex.
Proof.
intros.
eapply always_inv.
- intros.
destruct s.
inv_prop and_tl.
split;
eauto using lb_execution_invar, reachable_st_lb_execution_cons.
- firstorder.
Qed.
Lemma channel_stays_empty' :
forall gst gst' src dst,
(forall p, In (src, (dst, p)) (msgs gst') -> In (src, (dst, p)) (msgs gst)) ->
channel gst src dst = [] ->
channel gst' src dst = [].
Proof.
intros.
destruct (channel gst' src dst) eqn:?; auto.
exfalso.
assert (In p (channel gst' src dst)) by (find_rewrite; intuition).
find_apply_lem_hyp in_channel_in_msgs. find_apply_hyp_hyp.
find_apply_lem_hyp in_msgs_in_channel. repeat find_rewrite. solve_by_inversion.
Qed.
Lemma channel_stays_empty :
forall ex src dst,
reachable_st (occ_gst (hd ex)) ->
lb_execution ex ->
In src (failed_nodes (occ_gst (hd ex))) ->
channel (occ_gst (hd ex)) src dst = [] ->
channel (occ_gst (hd (tl ex))) src dst = [].
Proof.
intros. destruct ex. simpl in *.
inv_prop lb_execution.
inv_prop labeled_step_dynamic; simpl in *; repeat find_rewrite.
- destruct (addr_eq_dec h src); subst; try congruence.
eapply channel_stays_empty'; [|eauto]; simpl in *.
intros. in_crush. destruct x. find_rewrite_lem send_definition.
congruence.
- destruct (addr_eq_dec (fst (snd m)) src); subst; try congruence.
eapply channel_stays_empty'; [|eauto]; simpl in *.
intros. repeat find_rewrite. in_crush.
destruct x. find_rewrite_lem send_definition.
congruence.
- find_eapply_lem_hyp clients_not_in_failed; eauto.
intuition. destruct (addr_eq_dec h src); subst; intuition.
eapply channel_stays_empty'; [|eauto]; simpl in *.
intros. intuition.
find_rewrite_lem send_definition.
congruence.
- eapply channel_stays_empty'; [|eauto]; simpl in *.
intros. find_rewrite. in_crush.
(*
USED: In phase one (transitively)
DIFFICULTY: 1
*)
Qed.
Lemma open_request_until_timeout :
forall h dst req ex,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
channel (occ_gst (hd ex)) dst h = [] ->
In h (active_nodes (occ_gst (hd ex))) ->
In dst (failed_nodes (occ_gst (hd ex))) ->
open_request_to (occ_gst (hd ex)) h dst req ->
weak_until (now (fun occ => open_request_to (occ_gst occ) h dst req))
(now (occurred (Timeout h (Request dst req) DetectFailure)))
ex.
Proof.
intros h dst req.
cofix c.
destruct ex.
intros.
inv_prop lb_execution.
find_copy_eapply_lem_hyp open_request_to_dead_node_preserved_or_times_out;
(* eauto will grab the coinduction hypothesis if we don't do something like this *)
match goal with
| |- weak_until _ _ _ => idtac
| _ => eauto using in_active_in_nodes, in_active_not_failed
end.
break_or_hyp.
- apply W_tl; [assumption|].
apply c;
invar_eauto;
eauto using active_nodes_invar, failed_nodes_never_removed, channel_stays_empty.
- now apply W0.
Qed.
Definition channel_measure from to gst :=
length (channel gst from to).
Definition channel_measure_zero_empty :
forall s from to,
now (measure_zero (channel_measure from to)) s ->
now (fun occ => channel (occ_gst occ) from to = []) s.
Proof.
intros. destruct s. simpl in *.
unfold measure_zero, channel_measure in *.
destruct (channel (occ_gst o) from to); simpl in *; congruence.
Qed.
Lemma filterMap_map :
forall A B C (f : B -> option C) (g : A -> B) (l : list A),
filterMap f (map g l) =
filterMap (fun x => f (g x)) l.
Proof.
intros. induction l; auto.
- simpl. break_match; congruence.
Qed.
Lemma channel_measure_nonincreasing :
forall ex dead h,
reachable_st (occ_gst (hd ex)) ->
lb_execution ex ->
In dead (failed_nodes (occ_gst (hd ex))) ->
always (consecutive (measure_nonincreasing (channel_measure dead h))) ex.
Proof.
cofix c.
intros.
apply Always.
- clear c.
inv_prop lb_execution. simpl in *.
unfold measure_nonincreasing, channel_measure.
inv_prop labeled_step_dynamic.
+ simpl in *.
unfold channel.
repeat find_rewrite. simpl.
rewrite filterMap_app.
rewrite filterMap_map.
simpl.
destruct (addr_eq_dec h0 dead); subst; try congruence.
simpl.
rewrite filterMap_all_None; intuition.
+ simpl in *. unfold channel.
repeat find_rewrite. simpl.
rewrite filterMap_app.
simpl.
rewrite filterMap_map.
simpl.
destruct (addr_eq_dec (fst (snd m)) dead); subst; try congruence.
simpl.
rewrite filterMap_all_None; intuition.
simpl.
repeat rewrite filterMap_app. repeat rewrite app_length.
simpl; break_match; simpl; intuition.
+ simpl in *. unfold channel.
repeat find_rewrite. simpl.
destruct (addr_eq_dec h0 dead); subst; [exfalso; eapply clients_not_in_failed; eauto|].
simpl. auto.
+ unfold channel. repeat find_rewrite.
simpl.
repeat rewrite filterMap_app. repeat rewrite app_length.
simpl; break_match; simpl; intuition.
- inv_prop lb_execution.
simpl in *.
apply c; eauto using reachable_st_lb_execution_cons.
simpl in *.
erewrite <- labeled_step_dynamic_preserves_failed_nodes; eauto.
Qed.
Lemma channel_measure_zero_or_eventually_decreasing :
forall ex dead h,
reachable_st (occ_gst (hd ex)) ->
lb_execution ex ->
weak_local_fairness ex ->
In dead (failed_nodes (occ_gst (hd ex))) ->
In h (nodes (occ_gst (hd ex))) ->
~ In h (failed_nodes (occ_gst (hd ex))) ->
always (zero_or_eventually_decreasing (channel_measure dead h)) ex.
Proof.
cofix c.
intros.
apply Always.
- clear c.
unfold zero_or_eventually_decreasing.
unfold or_tl.
destruct (channel (occ_gst (hd ex)) dead h) eqn:?.
+ left. destruct ex. simpl in *. unfold measure_zero, channel_measure.
repeat find_rewrite. auto.
+ right.
find_copy_apply_lem_hyp nodes_have_state; auto. break_exists.
eapply eventually_monotonic with (J := lb_execution); auto.
eauto using lb_execution_invar.
2:eapply RecvMsg_eventually_occurred with (src := dead) (m := p); eauto.
* intros.
inv_prop lb_execution.
simpl in *.
unfold occurred in *.
repeat find_reverse_rewrite.
inv_prop labeled_step_dynamic.
-- unfold timeout_handler_l in *.
break_let. solve_by_inversion.
-- unfold recv_handler_l in *.
find_inversion.
unfold measure_decreasing, channel_measure, channel.
repeat find_rewrite. simpl.
rewrite filterMap_app.
simpl.
rewrite filterMap_map.
simpl.
destruct (addr_eq_dec (fst (snd m)) (fst m));
repeat find_rewrite; intuition.
simpl.
rewrite filterMap_all_None; intuition.
simpl.
repeat rewrite filterMap_app.
simpl.
repeat match goal with
| |- context [addr_eq_dec ?x ?x] =>
destruct (addr_eq_dec x x); try congruence
end.
simpl. repeat rewrite app_length. simpl. intuition.
-- unfold label_input in *. congruence.
-- unfold label_output in *. congruence.
* apply in_channel_in_msgs; repeat find_rewrite; in_crush.
- destruct ex. simpl.
inv_prop lb_execution.
apply c;
eauto using weak_local_fairness_invar, reachable_st_lb_execution_cons;
try solve [erewrite <- labeled_step_dynamic_preserves_failed_nodes; eauto];
try solve [erewrite <- labeled_step_dynamic_preserves_nodes; eauto].
Qed.
Lemma dead_node_channel_empties_out' :
forall ex dead h,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
In h (nodes (occ_gst (hd ex))) ->
~ In h (failed_nodes (occ_gst (hd ex))) ->
In dead (failed_nodes (occ_gst (hd ex))) ->
weak_local_fairness ex ->
continuously (now (fun occ => channel (occ_gst occ) dead h = [])) ex.
Proof.
intros.
eapply continuously_monotonic; [intros; eapply channel_measure_zero_empty; eauto|].
eapply measure_decreasing_to_zero;
eauto using channel_measure_nonincreasing, channel_measure_zero_or_eventually_decreasing.
Qed.
Lemma dead_node_channel_empties_out :
forall ex dead h,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
live_node (occ_gst (hd ex)) h ->
In dead (failed_nodes (occ_gst (hd ex))) ->
weak_local_fairness ex ->
continuously (now (fun occ => channel (occ_gst occ) dead h = [])) ex.
Proof.
unfold live_node in *. eauto using dead_node_channel_empties_out'.
Qed.
Lemma live_node_in_active :
forall h gst,
live_node gst h ->
In h (active_nodes gst).
Proof.
intros.
inv_prop live_node; expand_def.
eapply in_nodes_not_failed_in_active; auto.
Qed.
Lemma request_eventually_fires :
forall h dst req ex,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
weak_local_fairness ex ->
live_node (occ_gst (hd ex)) h ->
In dst (failed_nodes (occ_gst (hd ex))) ->
open_request_to (occ_gst (hd ex)) h dst req ->
channel (occ_gst (hd ex)) dst h = [] ->
eventually (now (occurred (Timeout h (Request dst req) DetectFailure))) ex.
Proof.
intros.
find_apply_lem_hyp open_request_until_timeout; auto using live_node_in_active.
find_apply_lem_hyp weak_until_until_or_always.
break_or_hyp; [eauto using until_eventually|].
find_copy_apply_lem_hyp (dead_node_channel_empties_out ex dst h); auto.
find_apply_lem_hyp always_continuously.
destruct ex. apply always_now.
match goal with
| H : weak_local_fairness _ |- _ => apply H
end.
assert (continuously
(now (fun occ => open_request_to (occ_gst occ) h dst req) /\_
now (fun occ => channel (occ_gst occ) dst h = []) /\_
(fun ex => lb_execution ex /\
now (fun occ => live_node (occ_gst occ) h /\
In dst (failed_nodes (occ_gst occ))) ex))
(Cons o ex)).
{
apply continuously_and_tl; auto.
apply continuously_and_tl; auto.
apply E0.
apply always_inv; [|firstorder].
intros.
split; break_and; eauto using lb_execution_invar.
destruct s.
inv_prop lb_execution; simpl in *; break_and.
split.
- eapply live_node_invariant; eauto.
- eapply failed_nodes_never_removed; eauto.
}
eapply continuously_monotonic; [|eauto].
intros.
destruct s.
do 2 invcs_prop and_tl.
repeat break_and.
inv_prop live_node; expand_def.
eapply Timeout_enabled_when_open_request_to_dead_node; eauto.
intros.
rewrite channel_contents.
find_rewrite.
tauto.
Qed.
Lemma sent_message_means_in_nodes_or_client :
forall gst src dst p,
reachable_st gst ->
In (src, (dst, p)) (msgs gst) ->
In src (nodes gst) \/ client_payload p /\ client_addr src.
Proof.
intros.
generalize dependent p.
generalize dependent dst.
generalize dependent src.
pattern gst.
apply chord_net_invariant; do 2 autounfold; simpl; intros;
repeat find_rewrite; intuition eauto;
try solve [
find_apply_lem_hyp in_app_or; break_or_hyp;
[find_apply_lem_hyp in_map_iff; expand_def; unfold send in *; find_injection; in_crush
|in_crush; eauto with datatypes]
].
- inv_prop initial_st; break_and.
repeat find_rewrite.
in_crush.
- in_crush; eauto.
+ unfold send in *.
find_injection; tauto.
+ find_apply_hyp_hyp; tauto.
- unfold send in *.
simpl in *.
break_or_hyp.
+ find_injection; tauto.
+ find_apply_hyp_hyp; tauto.
- simpl in *.
assert (In (src, (dst, p)) (xs ++ m :: ys)) by in_crush.
find_apply_hyp_hyp; tauto.
Qed.
(*TODO move to wherever response_payload is defined *)
Definition response_payload_dec :
forall p,
{response_payload p} + {~ response_payload p}.
Proof.
destruct p;
solve [left; constructor
|right; intro; inv_prop response_payload].
Defined.
Lemma req_res_pair_response_payload :
forall req res,
request_response_pair req res ->
response_payload res.
Proof.
intros.
inv_prop request_response_pair; constructor.
Qed.
Hint Resolve req_res_pair_response_payload.
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* XGMII 10GBASE-R encoder
*/
module xgmii_baser_enc_64 #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2
)
(
input wire clk,
input wire rst,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_txd,
input wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* 10GBASE-R encoded interface
*/
output wire [DATA_WIDTH-1:0] encoded_tx_data,
output wire [HDR_WIDTH-1:0] encoded_tx_hdr
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
localparam [7:0]
XGMII_IDLE = 8'h07,
XGMII_LPI = 8'h06,
XGMII_START = 8'hfb,
XGMII_TERM = 8'hfd,
XGMII_ERROR = 8'hfe,
XGMII_SEQ_OS = 8'h9c,
XGMII_RES_0 = 8'h1c,
XGMII_RES_1 = 8'h3c,
XGMII_RES_2 = 8'h7c,
XGMII_RES_3 = 8'hbc,
XGMII_RES_4 = 8'hdc,
XGMII_RES_5 = 8'hf7,
XGMII_SIG_OS = 8'h5c;
localparam [6:0]
CTRL_IDLE = 7'h00,
CTRL_LPI = 7'h06,
CTRL_ERROR = 7'h1e,
CTRL_RES_0 = 7'h2d,
CTRL_RES_1 = 7'h33,
CTRL_RES_2 = 7'h4b,
CTRL_RES_3 = 7'h55,
CTRL_RES_4 = 7'h66,
CTRL_RES_5 = 7'h78;
localparam [3:0]
O_SEQ_OS = 4'h0,
O_SIG_OS = 4'hf;
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
localparam [7:0]
BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT
BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_START = 8'h66, // D7 D6 D5 O0 D3 D2 D1 BT
BLOCK_TYPE_OS_04 = 8'h55, // D7 D6 D5 O4 O0 D3 D2 D1 BT
BLOCK_TYPE_START_0 = 8'h78, // D7 D6 D5 D4 D3 D2 D1 BT
BLOCK_TYPE_OS_0 = 8'h4b, // C7 C6 C5 C4 O0 D3 D2 D1 BT
BLOCK_TYPE_TERM_0 = 8'h87, // C7 C6 C5 C4 C3 C2 C1 BT
BLOCK_TYPE_TERM_1 = 8'h99, // C7 C6 C5 C4 C3 C2 D0 BT
BLOCK_TYPE_TERM_2 = 8'haa, // C7 C6 C5 C4 C3 D1 D0 BT
BLOCK_TYPE_TERM_3 = 8'hb4, // C7 C6 C5 C4 D2 D1 D0 BT
BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT
reg [DATA_WIDTH*7/8-1:0] encoded_ctrl;
reg [CTRL_WIDTH-1:0] encode_err;
reg [DATA_WIDTH-1:0] encoded_tx_data_reg = {DATA_WIDTH{1'b0}}, encoded_tx_data_next;
reg [HDR_WIDTH-1:0] encoded_tx_hdr_reg = {HDR_WIDTH{1'b0}}, encoded_tx_hdr_next;
assign encoded_tx_data = encoded_tx_data_reg;
assign encoded_tx_hdr = encoded_tx_hdr_reg;
integer i;
always @* begin
for (i = 0; i < CTRL_WIDTH; i = i + 1) begin
if (xgmii_txc[i]) begin
// control
case (xgmii_txd[8*i +: 8])
XGMII_IDLE: begin
encoded_ctrl[7*i +: 7] = CTRL_IDLE;
encode_err[i] = 1'b0;
end
XGMII_ERROR: begin
encoded_ctrl[7*i +: 7] = CTRL_ERROR;
encode_err[i] = 1'b0;
end
XGMII_RES_0: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_0;
encode_err[i] = 1'b0;
end
XGMII_RES_1: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_1;
encode_err[i] = 1'b0;
end
XGMII_RES_2: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_2;
encode_err[i] = 1'b0;
end
XGMII_RES_3: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_3;
encode_err[i] = 1'b0;
end
XGMII_RES_4: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_4;
encode_err[i] = 1'b0;
end
XGMII_RES_5: begin
encoded_ctrl[7*i +: 7] = CTRL_RES_5;
encode_err[i] = 1'b0;
end
default: begin
encoded_ctrl[7*i +: 7] = CTRL_ERROR;
encode_err[i] = 1'b1;
end
endcase
end else begin
// data (always invalid as control)
encoded_ctrl[7*i +: 7] = CTRL_ERROR;
encode_err[i] = 1'b1;
end
end
if (xgmii_txc == 8'h00) begin
encoded_tx_data_next = xgmii_txd;
encoded_tx_hdr_next = SYNC_DATA;
end else begin
if (xgmii_txc[0] && xgmii_txd[7:0] == XGMII_START && !xgmii_txc[7:1]) begin
// start in lane 0
encoded_tx_data_next = {xgmii_txd[63:8], BLOCK_TYPE_START_0};
end else if (xgmii_txc[4] && xgmii_txd[39:32] == XGMII_START && !xgmii_txc[7:5]) begin
// start in lane 4
if (xgmii_txc[0] && xgmii_txd[7:0] == XGMII_SEQ_OS && !xgmii_txc[3:1]) begin
// ordered set in lane 0
encoded_tx_data_next[35:0] = {O_SEQ_OS, xgmii_txd[31:8], BLOCK_TYPE_START_4};
end else begin
encoded_tx_data_next[35:0] = {encoded_ctrl[27:0], BLOCK_TYPE_START_4};
end
encoded_tx_data_next[63:36] = {xgmii_txd[63:40], 4'd0};
end else if (xgmii_txc[0] && xgmii_txd[7:0] == XGMII_SEQ_OS && !xgmii_txc[3:1]) begin
// ordered set in lane 0
encoded_tx_data_next[35:8] = {O_SEQ_OS, xgmii_txd[31:8]};
if (xgmii_txc[4] && xgmii_txd[39:32] == XGMII_SEQ_OS && !xgmii_txc[7:5]) begin
// ordered set in lane 4
encoded_tx_data_next[63:36] = {xgmii_txd[63:40], O_SEQ_OS};
encoded_tx_data_next[7:0] = BLOCK_TYPE_OS_04;
end else begin
encoded_tx_data_next[63:36] = encoded_ctrl[55:28];
encoded_tx_data_next[7:0] = BLOCK_TYPE_OS_0;
end
end else if (xgmii_txc[4] && xgmii_txd[39:32] == XGMII_SEQ_OS && !xgmii_txc[7:5]) begin
// ordered set in lane 4
encoded_tx_data_next = {xgmii_txd[63:40], O_SEQ_OS, 4'd0, encoded_ctrl[27:0], BLOCK_TYPE_OS_4};
end else if (xgmii_txc[0] && xgmii_txd[7:0] == XGMII_TERM) begin
// terminate in lane 0
encoded_tx_data_next = {encoded_ctrl[55:7], 7'd0, BLOCK_TYPE_TERM_0};
end else if (xgmii_txc[1] && xgmii_txd[15:8] == XGMII_TERM && !xgmii_txc[0]) begin
// terminate in lane 1
encoded_tx_data_next = {encoded_ctrl[55:14], 6'd0, xgmii_txd[7:0], BLOCK_TYPE_TERM_1};
end else if (xgmii_txc[2] && xgmii_txd[23:16] == XGMII_TERM && !xgmii_txc[1:0]) begin
// terminate in lane 2
encoded_tx_data_next = {encoded_ctrl[55:21], 5'd0, xgmii_txd[15:0], BLOCK_TYPE_TERM_2};
end else if (xgmii_txc[3] && xgmii_txd[31:24] == XGMII_TERM && !xgmii_txc[2:0]) begin
// terminate in lane 3
encoded_tx_data_next = {encoded_ctrl[55:28], 4'd0, xgmii_txd[23:0], BLOCK_TYPE_TERM_3};
end else if (xgmii_txc[4] && xgmii_txd[39:32] == XGMII_TERM && !xgmii_txc[3:0]) begin
// terminate in lane 4
encoded_tx_data_next = {encoded_ctrl[55:35], 3'd0, xgmii_txd[31:0], BLOCK_TYPE_TERM_4};
end else if (xgmii_txc[5] && xgmii_txd[47:40] == XGMII_TERM && !xgmii_txc[4:0]) begin
// terminate in lane 5
encoded_tx_data_next = {encoded_ctrl[55:42], 2'd0, xgmii_txd[39:0], BLOCK_TYPE_TERM_5};
end else if (xgmii_txc[6] && xgmii_txd[55:48] == XGMII_TERM && !xgmii_txc[5:0]) begin
// terminate in lane 6
encoded_tx_data_next = {encoded_ctrl[55:49], 1'd0, xgmii_txd[47:0], BLOCK_TYPE_TERM_6};
end else if (xgmii_txc[7] && xgmii_txd[63:56] == XGMII_TERM && !xgmii_txc[6:0]) begin
// terminate in lane 7
encoded_tx_data_next = {xgmii_txd[55:0], BLOCK_TYPE_TERM_7};
end else begin
// all control
encoded_tx_data_next = {encoded_ctrl, BLOCK_TYPE_CTRL};
end
encoded_tx_hdr_next = SYNC_CTRL;
end
end
always @(posedge clk) begin
encoded_tx_data_reg <= encoded_tx_data_next;
encoded_tx_hdr_reg <= encoded_tx_hdr_next;
end
endmodule
|
module TubeROM (
input wire[3:0] value,
input wire auxValue,
output reg[6:0] segments
);
always @ (*) begin
if (auxValue) begin
case (value)
4'h0: segments = 7'h00; // Empty
4'h1: segments = 7'h73; // P
4'h2: segments = 7'h78; // T
4'h3: segments = 7'h50; // R
4'h4: segments = 7'h1C; // V
4'h5: segments = 7'h76; // H
4'h6: segments = 7'h38; // L
default: segments = 7'b0;
endcase
end
else begin
case (value)
4'h0: segments = 7'h3F; // 0
4'h1: segments = 7'h06; // 1
4'h2: segments = 7'h5B; // 2
4'h3: segments = 7'h4F; // 3
4'h4: segments = 7'h66; // 4
4'h5: segments = 7'h6D; // 5
4'h6: segments = 7'h7D; // 6
4'h7: segments = 7'h07; // 7
4'h8: segments = 7'h7F; // 8
4'h9: segments = 7'h6F; // 9
4'hA: segments = 7'h77; // A
4'hB: segments = 7'h7C; // B
4'hC: segments = 7'h39; // C
4'hD: segments = 7'h5E; // D
4'hE: segments = 7'h79; // E
4'hF: segments = 7'h71; // F
default: segments = 7'b0;
endcase
end
end
endmodule
module TubeController (
input wire[1:0] dig,
input wire[3:0] dig1,
input wire[3:0] dig2,
input wire[3:0] dig3,
input wire[3:0] dig4,
input wire[3:0] dots,
input wire[3:0] auxs,
output wire[3:0] tubeDig,
output wire[7:0] tubeSeg
);
wire[3:0] value = (dig == 2'd0)? dig1 :
(dig == 2'd1)? dig2 :
(dig == 2'd2)? dig3 :
dig4;
TubeROM rom (value, auxs[dig], tubeSeg[6:0]);
assign tubeSeg[7] = dots[dig];
assign tubeDig = (dig == 2'd0)? 4'b0001 :
(dig == 2'd1)? 4'b0010 :
(dig == 2'd2)? 4'b0100 :
4'b1000;
endmodule
|
`timescale 1ns / 1ps
`default_nettype none //To avoid bugs involving implicit nets
////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Acknowledgements: Prof. Kyle Gilsdorf (Arizona State)
// - http://www.public.asu.edu/~kyle135/
// - [email protected]
//
//
// Author: Rushang Vinod Vandana Karia
// - Masters in Computer Science @ Arizona State
// - [email protected]
// - 4806283130
// - github.com/RushangKaria
//
//
// Module: Touch_Controller.v
//
// Description : Touch Controller to calculate X,Y and Pressure values
//
// Copyright : Copyright (C) 2014 Rushang Vinod Vandana Karia
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
module Touch_Controller #(parameter CLOCKFREQ = 100)
(
input wire CLK_I,
input wire RST_I,
input wire PENIRQ_I,
input wire DOUT_I,
input wire BUSY_I,
output wire [11:0] X_O,
output wire [11:0] Y_O,
output wire [11:0] Z_O,
output wire CS_O,
output wire DIN_O,
output wire DCLK_O
);
///////////////////////////////////////////////////////////////////////
// MODULE SPECIFIC PARAMETER DECLARATIONS
///////////////////////////////////////////////////////////////////////
parameter integer TCH_CL = 250;
parameter integer TSETTLE = 10000;
parameter integer DCLK_CYCLES = (CLOCKFREQ*TCH_CL)/(1000);
parameter integer SETTLE_CYCLES = (CLOCKFREQ*TSETTLE)/(1000);
parameter integer BITS_PER_CONVERSION = 12;
parameter integer CLOCKS_PER_CONVERSION = 15;
parameter integer ACQ_FROM_BIT = 5;
parameter integer AVERAGE_FACTOR = 3;
parameter ADS_START = 1'b1;
parameter ADS_AX = 3'b101;
parameter ADS_AY = 3'b001;
parameter ADS_AZ1 = 3'b011;
parameter ADS_12BIT = 1'b0;
parameter ADS_DIF = 1'b0;
parameter ADS_NOPD = 2'b11;
parameter ADS_PD = 2'b00;
parameter integer STATE_IDLE = 0;
parameter integer STATE_CMD_LOAD = 1;
parameter integer STATE_CMD = 2;
parameter integer STATE_BUSY = 3;
parameter integer STATE_ACQ_DELAY = 4;
parameter integer STATE_SAMPLE = 0;
parameter integer STATE_WINDOWING = 1;
parameter integer STATE_X_DIV_Z1 = 2;
parameter integer STATE_NEW_DATA = 3;
parameter integer X_POS = 0;
parameter integer Y_POS = 1;
parameter integer Z1_POS = 2;
///////////////////////////////////////////////////////////////////////////////////////
// SIGNALS LOCAL TO MODULE
///////////////////////////////////////////////////////////////////////////////////////
reg [2:0] controller_state;
reg [2:0] controller_next_state;
reg [1:0] sample_state;
reg [1:0] sample_next_state;
reg [1:0] measure_state;
reg [1:0] previous_measure_state;
reg [2:0] ads_A;
wire [7:0] ads_cmd;
reg [BITS_PER_CONVERSION-1+AVERAGE_FACTOR+1:0] avgAcc;
wire [BITS_PER_CONVERSION-1+AVERAGE_FACTOR+1:0] wAvg1;
wire [BITS_PER_CONVERSION-1+AVERAGE_FACTOR+1:0] wAvg;
reg [BITS_PER_CONVERSION-1:0] sampleMin;
reg [BITS_PER_CONVERSION-1:0] sampleMax;
wire avgCntEn;
reg avgCntRst;
reg [4:0] sampleCnt;
reg sampleCntEn;
reg sampleCntRst;
reg [BITS_PER_CONVERSION-1:0] int_X;
reg [BITS_PER_CONVERSION-1:0] int_Y;
reg [BITS_PER_CONVERSION-1:0] int_Z;
reg [BITS_PER_CONVERSION-1:0] fX_Z1;
reg [BITS_PER_CONVERSION:0] qX_Z1;
wire rfd;
wire rdyX_Z1;
reg ndX_Z1;
wire [BITS_PER_CONVERSION*2-1:0] X_Z1_4096;
reg [BITS_PER_CONVERSION*2-1:0] RTouch_4;
reg [BITS_PER_CONVERSION*2-1:0] RTouch;
wire [((BITS_PER_CONVERSION*2+1)/8+1)*8-1:0] m_axis_dout_tdata;
reg [$clog2(DCLK_CYCLES)-1:0] clkCnt;
reg clkCntEn;
reg int_DCLK;
reg int_CS;
reg dclkREdge;
reg dclkFEdge;
reg [$clog2(CLOCKS_PER_CONVERSION)-1:0] bitCnt;
wire bitCntEn;
wire bitCntRst;
reg [$clog2(SETTLE_CYCLES)-1:0] settleCnt;
reg settleCntEn;
reg settleCntRst;
reg [BITS_PER_CONVERSION-1:0] srDataIn;
reg [7:0] srDataOut;
reg shiftOutLd;
///////////////////////////////////////////////////////////////////////////////////////
// SYNTHESIS SPECIFIC INSTRUCTIONS
///////////////////////////////////////////////////////////////////////////////////////
initial
begin
controller_state = STATE_IDLE;
measure_state = X_POS;
previous_measure_state = X_POS;
sample_state = STATE_SAMPLE;
sampleMin = 12'hFFF;
sampleMax = 12'h000;
sampleCnt = 2**AVERAGE_FACTOR+2-1;
int_DCLK = 1'b0;
int_CS = 1'b0;
dclkREdge = 1'b0;
dclkFEdge = 1'b0;
clkCntEn = 1'b0;
end
///////////////////////////////////////////////////////////////////////////////////////
// INPUT | OUTPUT SHIFT REGISTERS
///////////////////////////////////////////////////////////////////////////////////////
always@(posedge CLK_I)
begin
if(dclkREdge)
srDataIn <= {srDataIn[BITS_PER_CONVERSION-2:0],DOUT_I};
if(shiftOutLd)
srDataOut <= ads_cmd;
else if(dclkFEdge)
srDataOut <= {srDataOut[6:0],1'b0};
end
assign DIN_O = srDataOut[7];
assign DCLK_O = int_DCLK;
assign CS_O = int_CS;
assign X_O = int_X;
assign Y_O = int_Y;
assign Z_O = int_Z;
always@(measure_state)
case(measure_state)
X_POS : ads_A = ADS_AX;
Y_POS : ads_A = ADS_AY;
Z1_POS : ads_A = ADS_AZ1;
endcase
assign ads_cmd = {ADS_START,ads_A,ADS_12BIT,ADS_DIF,ADS_NOPD};
///////////////////////////////////////////////////////////////////////////////////////
// CLOCK DIVIDER
///////////////////////////////////////////////////////////////////////////////////////
always@(posedge CLK_I)
if(clkCntEn)
if(clkCnt == 0)
begin
clkCnt <= DCLK_CYCLES - 1;
int_DCLK <= ~int_DCLK;
end
else
clkCnt <= clkCnt - 1;
always@*
if(clkCnt)
begin
dclkREdge = 1'b0;
dclkFEdge = 1'b0;
end
else
begin
dclkREdge = ~int_DCLK;
dclkFEdge = int_DCLK;
end
///////////////////////////////////////////////////////////////////////////////////////
// BIT COUNTER
///////////////////////////////////////////////////////////////////////////////////////
always@(posedge CLK_I)
if(bitCntRst)
bitCnt <= 'b0;
else if(dclkFEdge)
if(bitCnt == CLOCKS_PER_CONVERSION-1)
bitCnt <= 'b0;
else
bitCnt <= bitCnt+1;
///////////////////////////////////////////////////////////////////////////////////////
// SETTLE TIME COUNTER -- to delay acquistion and allow the voltage to stabilize
///////////////////////////////////////////////////////////////////////////////////////
always@(posedge CLK_I)
if(settleCntRst)
settleCnt <= SETTLE_CYCLES - 1;
else if(settleCntEn && settleCnt != 'b0)
settleCnt <= settleCnt - 1;
///////////////////////////////////////////////////////////////////////////////////////
// SAMPLE COUNTER -- for filtering
///////////////////////////////////////////////////////////////////////////////////////
always@(posedge CLK_I)
if(sampleCntRst)
sampleCnt <= 2**AVERAGE_FACTOR + 2 - 1;
else if(sampleCntEn)
sampleCnt <= sampleCnt - 1;
///////////////////////////////////////////////////////////////////////////////////////
// MEASUREMENT TYPE
///////////////////////////////////////////////////////////////////////////////////////
always@(posedge CLK_I)
if(dclkFEdge && bitCnt == 8)
begin
previous_measure_state <= measure_state;
if(sampleCnt == 'b0)
case(measure_state)
X_POS : measure_state <= Y_POS;
Y_POS : measure_state <= Z1_POS;
Z1_POS : measure_state <= X_POS;
default : measure_state <= X_POS;
endcase
end
///////////////////////////////////////////////////////////////////////////////////////
// ACCUMULATOR -- for averaging the converted co-ordinates
///////////////////////////////////////////////////////////////////////////////////////
always@(posedge CLK_I)
if(avgCntRst)
begin
avgAcc <= 'b0;
sampleMin <= 'hFFF;
sampleMax <= 'h000;
end
else if(avgCntEn)
begin
avgAcc <= avgAcc + srDataIn;
if(srDataIn < sampleMin)
sampleMin <= srDataIn;
if(srDataIn > sampleMax)
sampleMax <= srDataIn;
end
//Check this logic
assign avgCntEn = sampleCntEn;
assign wAvg1 = avgAcc-{{(BITS_PER_CONVERSION+AVERAGE_FACTOR+1){1'b0}},sampleMin};
assign wAvg = wAvg1-{{(BITS_PER_CONVERSION+AVERAGE_FACTOR+1){1'b0}},sampleMax};
///////////////////////////////////////////////////////////////////////////////////////
// X/Z1 DIVIDER :: CORE INSTANTIATION
// :: A high radix divider with a 12 bit fractional part. The result
// :: is actually scaled to 4096 by concatenating the quotient
// :: with the fractional.
///////////////////////////////////////////////////////////////////////////////////////
div Inst_X_div_Z1
(
.aclk (CLK_I),
.s_axis_divisor_tvalid (ndX_Z1),
.s_axis_divisor_tready (),
.s_axis_divisor_tdata ({4'b0000,wAvg[BITS_PER_CONVERSION-1+AVERAGE_FACTOR:AVERAGE_FACTOR]}),
.s_axis_dividend_tvalid (ndX_Z1),
.s_axis_dividend_tready (rfd),
.s_axis_dividend_tdata ({4'b0000,int_X}),
.m_axis_dout_tvalid (rdyX_Z1),
.m_axis_dout_tdata (m_axis_dout_tdata)
);
assign X_Z1_4096 = m_axis_dout_tdata[BITS_PER_CONVERSION*2-1:0];
always@(posedge CLK_I)
RTouch_4 <= X_Z1_4096 - int_X + int_Y[BITS_PER_CONVERSION-1:2] - 'd1024;
///////////////////////////////////////////////////////////////////////////////////////
// CO-ORDINATE BUFFERS
///////////////////////////////////////////////////////////////////////////////////////
always@(posedge CLK_I)
if(sample_state == STATE_NEW_DATA)
begin
case(previous_measure_state)
X_POS : int_X <= wAvg[BITS_PER_CONVERSION-1+AVERAGE_FACTOR:AVERAGE_FACTOR];
Y_POS : int_Y <= wAvg[BITS_PER_CONVERSION-1+AVERAGE_FACTOR:AVERAGE_FACTOR];
Z1_POS : if(RTouch_4[BITS_PER_CONVERSION*2-1:BITS_PER_CONVERSION-1+3]!=0)
int_Z <= {BITS_PER_CONVERSION{1'b1}};
else
int_Z <= RTouch_4[BITS_PER_CONVERSION-1+2:2];
endcase
end
///////////////////////////////////////////////////////////////////////////////////////
// ACQUIRE STATE MACHINE
///////////////////////////////////////////////////////////////////////////////////////
//assign LED_O = (controller_state == STATE_ACQ_DELAY)?8'b11111111:0;
always@(posedge CLK_I)
if(RST_I)
controller_state <= STATE_IDLE;
else
controller_state <= controller_next_state;
always@*
begin
clkCntEn = (controller_state == STATE_CMD ||controller_state == STATE_BUSY || controller_state == STATE_CMD_LOAD);
settleCntEn = (controller_state == STATE_ACQ_DELAY);
settleCntRst = (dclkFEdge && bitCnt == 8 && sampleCnt == 0);
shiftOutLd = (controller_state == STATE_CMD_LOAD);
int_CS = (controller_state == STATE_IDLE);
if(dclkFEdge && bitCnt == ACQ_FROM_BIT)
begin
sampleCntEn = 1'b1;
if(sampleCnt == 0)
sampleCntRst = 1'b1;
else
sampleCntRst = 1'b0;
end
else
begin
sampleCntEn = 1'b0;
sampleCntRst = 1'b0;
end
end
always@*
case(controller_state)
STATE_IDLE : controller_next_state = STATE_CMD_LOAD;
STATE_CMD_LOAD : controller_next_state = STATE_CMD;
STATE_CMD : if(dclkFEdge)
if(bitCnt == ACQ_FROM_BIT && SETTLE_CYCLES > 0 && settleCnt != 0)
controller_next_state = STATE_ACQ_DELAY;
else if(bitCnt == 7)
controller_next_state = STATE_BUSY;
else if(bitCnt == CLOCKS_PER_CONVERSION-1)
controller_next_state = STATE_CMD_LOAD;
else
controller_next_state = STATE_CMD;
STATE_ACQ_DELAY : controller_next_state = (settleCnt == 0) ? STATE_CMD :STATE_ACQ_DELAY;
STATE_BUSY : controller_next_state = (dclkFEdge) ? STATE_CMD :STATE_BUSY;
default : controller_next_state = STATE_IDLE;
endcase
///////////////////////////////////////////////////////////////////////////////////////
// FILTERING AND TOUCH CALCULATION FSM
///////////////////////////////////////////////////////////////////////////////////////
always@(posedge CLK_I)
if(RST_I)
sample_state <= STATE_SAMPLE;
else
sample_state <= sample_next_state;
always@*
begin
avgCntRst = (sample_state == STATE_NEW_DATA);
ndX_Z1 = (sample_state == STATE_WINDOWING);
end
always@*
case(sample_state)
STATE_SAMPLE : sample_next_state = (sampleCntRst == 1) ? STATE_WINDOWING :STATE_SAMPLE;
STATE_WINDOWING : sample_next_state = (previous_measure_state == Z1_POS) ? STATE_X_DIV_Z1 :STATE_NEW_DATA;
STATE_X_DIV_Z1 : sample_next_state = (rdyX_Z1) ? STATE_NEW_DATA :STATE_X_DIV_Z1;
STATE_NEW_DATA : sample_next_state = STATE_SAMPLE;
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLCLKP_BLACKBOX_V
`define SKY130_FD_SC_MS__DLCLKP_BLACKBOX_V
/**
* dlclkp: Clock gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlclkp (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLCLKP_BLACKBOX_V
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20 // clock period
module test_const;
// Inputs
reg clk;
reg [5:0] addr;
// Outputs
wire [197:0] out;
wire effective;
reg [197:0] w_out;
reg w_effective;
// Instantiate the Unit Under Test (UUT)
const uut (
.clk(clk),
.addr(addr),
.out(out),
.effective(effective)
);
initial begin
// Initialize Inputs
addr = 0; clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
addr = 1; w_out = 0; w_effective = 1;
#(`P); check;
addr = 2; w_out = 1;
#(`P); check;
addr = 4; w_out = {6'b000101, 192'd0};
#(`P); check;
addr = 8; w_out = {6'b001001, 192'd0};
#(`P); check;
addr = 16; w_out = {6'b010101, 192'd0};
#(`P); check;
addr = 0; w_out = 0; w_effective = 0;
#(`P); check;
$display("Good");
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
task check;
begin
if (out !== w_out || effective !== w_effective)
$display("E %d %h %h", addr, out, w_out);
end
endtask
endmodule
|
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